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//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_top.v
// /___/ /\ Date Last Modified: $Date: 2009/01/15 14:22:14 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// System level module. This level contains just the memory controller.
// This level will be intiantated when the user wants to remove the
// synthesizable test bench, IDELAY control block and the clock
// generation modules.
//Reference:
//Revision History:
// Rev 1.1 - Parameter USE_DM_PORT added. PK. 6/25/08
// Rev 1.2 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.3 - Parameter IODELAY_GRP added. PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_top #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module ddr2_mig module. Please refer to
// the ddr2_mig module for actual values.
parameter BANK_WIDTH = 2, // # of memory bank addr bits
parameter CKE_WIDTH = 1, // # of memory clock enable outputs
parameter CLK_WIDTH = 1, // # of clock outputs
parameter COL_WIDTH = 10, // # of memory column bits
parameter CS_NUM = 1, // # of separate memory chip selects
parameter CS_BITS = 0, // set to log2(CS_NUM) (rounded up)
parameter CS_WIDTH = 1, // # of total memory chip selects
parameter USE_DM_PORT = 1, // enable Data Mask (=1 enable)
parameter DM_WIDTH = 9, // # of data mask bits
parameter DQ_WIDTH = 72, // # of data width
parameter DQ_BITS = 7, // set to log2(DQS_WIDTH*DQ_PER_DQS)
parameter DQ_PER_DQS = 8, // # of DQ data bits per strobe
parameter DQS_WIDTH = 9, // # of DQS strobes
parameter DQS_BITS = 4, // set to log2(DQS_WIDTH)
parameter HIGH_PERFORMANCE_MODE = "TRUE", // IODELAY Performance Mode
parameter IODELAY_GRP = "IODELAY_MIG", // IODELAY Group Name
parameter ODT_WIDTH = 1, // # of memory on-die term enables
parameter ROW_WIDTH = 14, // # of memory row & # of addr bits
parameter APPDATA_WIDTH = 144, // # of usr read/write data bus bits
parameter ADDITIVE_LAT = 0, // additive write latency
parameter BURST_LEN = 4, // burst length (in double words)
parameter BURST_TYPE = 0, // burst type (=0 seq; =1 interlved)
parameter CAS_LAT = 5, // CAS latency
parameter ECC_ENABLE = 0, // enable ECC (=1 enable)
parameter ODT_TYPE = 1, // ODT (=0(none),=1(75),=2(150),=3(50))
parameter MULTI_BANK_EN = 1, // enable bank management
parameter TWO_T_TIME_EN = 0, // 2t timing for unbuffered dimms
parameter REDUCE_DRV = 0, // reduced strength mem I/O (=1 yes)
parameter REG_ENABLE = 1, // registered addr/ctrl (=1 yes)
parameter TREFI_NS = 7800, // auto refresh interval (ns)
parameter TRAS = 40000, // active->precharge delay
parameter TRCD = 15000, // active->read/write delay
parameter TRFC = 105000, // ref->ref, ref->active delay
parameter TRP = 15000, // precharge->command delay
parameter TRTP = 7500, // read->precharge delay
parameter TWR = 15000, // used to determine wr->prech
parameter TWTR = 10000, // write->read delay
parameter CLK_PERIOD = 3000, // Core/Mem clk period (in ps)
parameter SIM_ONLY = 0, // = 1 to skip power up delay
parameter DEBUG_EN = 0, // Enable debug signals/controls
parameter FPGA_SPEED_GRADE = 2 // FPGA Speed Grade
)
(
input clk0,
input usr_clk, // jb
input clk90,
input clkdiv0,
input rst0,
input rst90,
input rstdiv0,
input [2:0] app_af_cmd,
input [30:0] app_af_addr,
input app_af_wren,
input app_wdf_wren,
input [APPDATA_WIDTH-1:0] app_wdf_data,
input [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data,
output app_af_afull,
output app_wdf_afull,
output rd_data_valid,
output [APPDATA_WIDTH-1:0] rd_data_fifo_out,
output [1:0] rd_ecc_error,
output phy_init_done,
output [CLK_WIDTH-1:0] ddr2_ck,
output [CLK_WIDTH-1:0] ddr2_ck_n,
output [ROW_WIDTH-1:0] ddr2_a,
output [BANK_WIDTH-1:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [CS_WIDTH-1:0] ddr2_cs_n,
output [CKE_WIDTH-1:0] ddr2_cke,
output [ODT_WIDTH-1:0] ddr2_odt,
output [DM_WIDTH-1:0] ddr2_dm,
inout [DQS_WIDTH-1:0] ddr2_dqs,
inout [DQS_WIDTH-1:0] ddr2_dqs_n,
inout [DQ_WIDTH-1:0] ddr2_dq,
// Debug signals (optional use)
input dbg_idel_up_all,
input dbg_idel_down_all,
input dbg_idel_up_dq,
input dbg_idel_down_dq,
input dbg_idel_up_dqs,
input dbg_idel_down_dqs,
input dbg_idel_up_gate,
input dbg_idel_down_gate,
input [DQ_BITS-1:0] dbg_sel_idel_dq,
input dbg_sel_all_idel_dq,
input [DQS_BITS:0] dbg_sel_idel_dqs,
input dbg_sel_all_idel_dqs,
input [DQS_BITS:0] dbg_sel_idel_gate,
input dbg_sel_all_idel_gate,
output [3:0] dbg_calib_done,
output [3:0] dbg_calib_err,
output [(6*DQ_WIDTH)-1:0] dbg_calib_dq_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_dqs_tap_cnt,
output [(6*DQS_WIDTH)-1:0] dbg_calib_gate_tap_cnt,
output [DQS_WIDTH-1:0] dbg_calib_rd_data_sel,
output [(5*DQS_WIDTH)-1:0] dbg_calib_rden_dly,
output [(5*DQS_WIDTH)-1:0] dbg_calib_gate_dly
, input sp_refresh_disable
);
// memory initialization/control logic
ddr2_mem_if_top #
(
.BANK_WIDTH (BANK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.CLK_WIDTH (CLK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_BITS (CS_BITS),
.CS_NUM (CS_NUM),
.CS_WIDTH (CS_WIDTH),
.USE_DM_PORT (USE_DM_PORT),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQ_BITS (DQ_BITS),
.DQ_PER_DQS (DQ_PER_DQS),
.DQS_BITS (DQS_BITS),
.DQS_WIDTH (DQS_WIDTH),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IODELAY_GRP (IODELAY_GRP),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.APPDATA_WIDTH (APPDATA_WIDTH),
.ADDITIVE_LAT (ADDITIVE_LAT),
.BURST_LEN (BURST_LEN),
.BURST_TYPE (BURST_TYPE),
.CAS_LAT (CAS_LAT),
.ECC_ENABLE (ECC_ENABLE),
.MULTI_BANK_EN (MULTI_BANK_EN),
.TWO_T_TIME_EN (TWO_T_TIME_EN),
.ODT_TYPE (ODT_TYPE),
.DDR_TYPE (1),
.REDUCE_DRV (REDUCE_DRV),
.REG_ENABLE (REG_ENABLE),
.TREFI_NS (TREFI_NS),
.TRAS (TRAS),
.TRCD (TRCD),
.TRFC (TRFC),
.TRP (TRP),
.TRTP (TRTP),
.TWR (TWR),
.TWTR (TWTR),
.CLK_PERIOD (CLK_PERIOD),
.SIM_ONLY (SIM_ONLY),
.DEBUG_EN (DEBUG_EN),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE)
)
u_mem_if_top
(
.clk0 (clk0),
.usr_clk (usr_clk), // jb
.clk90 (clk90),
.clkdiv0 (clkdiv0),
.rst0 (rst0),
.rst90 (rst90),
.rstdiv0 (rstdiv0),
.app_af_cmd (app_af_cmd),
.app_af_addr (app_af_addr),
.app_af_wren (app_af_wren),
.app_wdf_wren (app_wdf_wren),
.app_wdf_data (app_wdf_data),
.app_wdf_mask_data (app_wdf_mask_data),
.app_af_afull (app_af_afull),
.app_wdf_afull (app_wdf_afull),
.rd_data_valid (rd_data_valid),
.rd_data_fifo_out (rd_data_fifo_out),
.rd_ecc_error (rd_ecc_error),
.phy_init_done (phy_init_done),
.ddr_ck (ddr2_ck),
.ddr_ck_n (ddr2_ck_n),
.ddr_addr (ddr2_a),
.ddr_ba (ddr2_ba),
.ddr_ras_n (ddr2_ras_n),
.ddr_cas_n (ddr2_cas_n),
.ddr_we_n (ddr2_we_n),
.ddr_cs_n (ddr2_cs_n),
.ddr_cke (ddr2_cke),
.ddr_odt (ddr2_odt),
.ddr_dm (ddr2_dm),
.ddr_dqs (ddr2_dqs),
.ddr_dqs_n (ddr2_dqs_n),
.ddr_dq (ddr2_dq),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_dq (dbg_idel_up_dq),
.dbg_idel_down_dq (dbg_idel_down_dq),
.dbg_idel_up_dqs (dbg_idel_up_dqs),
.dbg_idel_down_dqs (dbg_idel_down_dqs),
.dbg_idel_up_gate (dbg_idel_up_gate),
.dbg_idel_down_gate (dbg_idel_down_gate),
.dbg_sel_idel_dq (dbg_sel_idel_dq),
.dbg_sel_all_idel_dq (dbg_sel_all_idel_dq),
.dbg_sel_idel_dqs (dbg_sel_idel_dqs),
.dbg_sel_all_idel_dqs (dbg_sel_all_idel_dqs),
.dbg_sel_idel_gate (dbg_sel_idel_gate),
.dbg_sel_all_idel_gate (dbg_sel_all_idel_gate),
.dbg_calib_done (dbg_calib_done),
.dbg_calib_err (dbg_calib_err),
.dbg_calib_dq_tap_cnt (dbg_calib_dq_tap_cnt),
.dbg_calib_dqs_tap_cnt (dbg_calib_dqs_tap_cnt),
.dbg_calib_gate_tap_cnt (dbg_calib_gate_tap_cnt),
.dbg_calib_rd_data_sel (dbg_calib_rd_data_sel),
.dbg_calib_rden_dly (dbg_calib_rden_dly),
.dbg_calib_gate_dly (dbg_calib_gate_dly)
, .sp_refresh_disable(sp_refresh_disable)
);
endmodule
|
/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_keccak;
// Inputs
reg clk;
reg reset;
reg [31:0] in;
reg in_ready;
reg is_last;
reg [1:0] byte_num;
// Outputs
wire buffer_full;
wire [511:0] out;
wire out_ready;
// Var
integer i;
// Instantiate the Unit Under Test (UUT)
keccak uut (
.clk(clk),
.reset(reset),
.in(in),
.in_ready(in_ready),
.is_last(is_last),
.byte_num(byte_num),
.buffer_full(buffer_full),
.out(out),
.out_ready(out_ready)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
in = 0;
in_ready = 0;
is_last = 0;
byte_num = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@ (negedge clk);
// SHA3-512("The quick brown fox jumps over the lazy dog")
reset = 1; #(`P); reset = 0;
in_ready = 1; is_last = 0;
in = "The "; #(`P);
in = "quic"; #(`P);
in = "k br"; #(`P);
in = "own "; #(`P);
in = "fox "; #(`P);
in = "jump"; #(`P);
in = "s ov"; #(`P);
in = "er t"; #(`P);
in = "he l"; #(`P);
in = "azy "; #(`P);
in = "dog "; byte_num = 3; is_last = 1; #(`P); /* !!! not in = "dog" */
in_ready = 0; is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'hd135bb84d0439dbac432247ee573a23ea7d3c9deb2a968eb31d47c4fb45f1ef4422d6c531b5b9bd6f449ebcc449ea94d0a8f05f62130fda612da53c79659f609);
// SHA3-512("The quick brown fox jumps over the lazy dog.")
reset = 1; #(`P); reset = 0;
in_ready = 1; is_last = 0;
in = "The "; #(`P);
in = "quic"; #(`P);
in = "k br"; #(`P);
in = "own "; #(`P);
in = "fox "; #(`P);
in = "jump"; #(`P);
in = "s ov"; #(`P);
in = "er t"; #(`P);
in = "he l"; #(`P);
in = "azy "; #(`P);
in = "dog."; #(`P);
in = 0; byte_num = 0; is_last = 1; #(`P); /* !!! */
in_ready = 0; is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'hab7192d2b11f51c7dd744e7b3441febf397ca07bf812cceae122ca4ded6387889064f8db9230f173f6d1ab6e24b6e50f065b039f799f5592360a6558eb52d760);
// hash an string "\xA1\xA2\xA3\xA4\xA5", len == 5
reset = 1; #(`P); reset = 0;
#(7*`P); // wait some cycles
in_ready = 1; is_last = 0; byte_num = 1;
in = 32'hA1A2A3A4;
#(`P);
is_last = 1; byte_num = 1;
in = 32'hA5000000;
#(`P);
in = 32'h12345678; // next input
in_ready = 1;
is_last = 1;
#(`P/2);
if (buffer_full === 1) error; // should be 0
#(`P/2);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'h12f4a85b68b091e8836219e79dfff7eb9594a42f5566515423b2aa4c67c454de83a62989e44b5303022bfe8c1a9976781b747a596cdab0458e20d8750df6ddfb);
for(i=0; i<5; i=i+1)
begin
#(`P);
if (buffer_full !== 0) error; // should keep 0
end
// hash an empty string, should not eat next input
reset = 1; #(`P); reset = 0;
#(7*`P); // wait some cycles
in = 32'h12345678; // should not be eat
byte_num = 0;
in_ready = 1;
is_last = 1;
#(`P);
in = 32'hddddd; // should not be eat
in_ready = 1; // next input
is_last = 1;
#(`P);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'h0eab42de4c3ceb9235fc91acffe746b29c29a8c366b7c60e4e67c466f36a4304c00fa9caf9d87976ba469bcbe06713b435f091ef2769fb160cdab33d3670680e);
for(i=0; i<5; i=i+1)
begin
#(`P);
if (buffer_full !== 0) error; // should keep 0
end
// hash an (576-8) bit string
reset = 1; #(`P); reset = 0;
#(4*`P); // wait some cycles
in_ready = 1;
byte_num = 3; /* should have no effect */
is_last = 0;
for (i=0; i<8; i=i+1)
begin
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; #(`P);
end
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; is_last = 1; #(`P);
in_ready = 0;
is_last = 0;
while (out_ready !== 1)
#(`P);
check(512'hf7f6b44069dba8900b6711ffcbe40523d4bb718cc8ed7f0a0bd28a1b18ee9374359f0ca0c9c1e96fcfca29ee2f282b46d5045eff01f7a7549eaa6b652cbf6270);
// pad an (576-64) bit string
reset = 1; #(`P); reset = 0;
// don't wait any cycle
in_ready = 1;
byte_num = 7; /* should have no effect */
is_last = 0;
for (i=0; i<8; i=i+1)
begin
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; #(`P);
end
is_last = 1;
byte_num = 0;
#(`P);
in_ready = 0;
is_last = 0;
in = 0;
while (out_ready !== 1)
#(`P);
check(512'hccd91653872c106f6eea1b8b68a4c2901c8d9bed9c180201f8a6144e7e6e6c251afcb6f6da44780b2d9aabff254036664719425469671f7e21fb67e5280a27ed);
// pad an (576*2-16) bit string
reset = 1; #(`P); reset = 0;
in_ready = 1;
byte_num = 1; /* should have no effect */
is_last = 0;
for (i=0; i<9; i=i+1)
begin
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; #(`P);
end
#(`P/2);
if (buffer_full !== 1) error; // should not eat
#(`P/2);
in = 32'h999; // should not eat this
in_ready = 0;
#(`P/2);
if (buffer_full !== 0) error; // should not eat, but buffer should not be full
#(`P/2);
#(`P);
// feed next (576-16) bit
in_ready = 1;
for (i=0; i<8; i=i+1)
begin
in = 32'hEFCDAB90; #(`P);
in = 32'h78563412; #(`P);
end
in = 32'hEFCDAB90; #(`P);
byte_num = 2;
is_last = 1;
in = 32'h78563412;
#(`P);
is_last = 0;
in_ready = 0;
while (out_ready !== 1)
#(`P);
check(512'h0f385323604e279251e80f928cfd9ce9492ba5df775063ea106eebe2a2c7785a3e33b4397fca66e90f67470334c66ea12016cb1f06170b9b033f158a7c01933e);
$display("Good!");
$finish;
end
always #(`P/2) clk = ~ clk;
task error;
begin
$display("E");
$finish;
end
endtask
task check;
input [511:0] wish;
begin
if (out !== wish)
begin
$display("%h %h", out, wish); error;
end
end
endtask
endmodule
`undef P
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O221A_PP_BLACKBOX_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam, LLC
// Engineer: Adam Michael
//
// Create Date: 22:42:16 09/08/2015
// Design Name: hw1problem3
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/hw1problem3/hw1problem3TB.v
// Project Name: hw1problem3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: hw1problem3
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module hw1problem3TB;
reg X, RESET, CLOCK;
wire Z;
wire Q1 = Unit2.Q1;
wire Q0 = Unit2.Q0;
initial begin #0 CLOCK = 1; end
always #1 CLOCK = ~CLOCK;
initial fork
#0 RESET = 1; // I added the inital reset because otherwise Q1 will
#0 X = 0; // depend on previous (non-existant) value of Q1.
#1 RESET = 0;
#2 X = 0; // X changes every 2 time units because CLOCK flips once
#4 X = 0; // per time unit and we only change state on rising edges.
#6 X = 1;
#8 X = 0;
#10 X = 1;
#12 X = 0;
#14 X = 0;
#16 X = 1;
#18 X = 1;
#20 X = 0;
#22 X = 1;
#24 X = 0;
#26 X = 1;
#28 X = 0;
#30 X = 0;
#32 X = 1;
#34 X = 0;
#36 X = 1;
#38 X = 1;
#40 X = 0;
#42 $stop;
join
hw1problem3 Unit2(X, Z, RESET, CLOCK);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4BB_2_V
`define SKY130_FD_SC_HS__AND4BB_2_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4BB_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: one_hot_mux_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////////////
// WARNING: Do not modify this file directly. This file was generated using pal.
// Please make all modifications to one_hot_mux_mon.vpal and run
// % pal -r -o one_hot_mux_mon.v one_hot_mux_mon.vpal to generate this file.
//
//
////////////////////////////////////////////////////////////////////////////////
`include "cross_module.h"
`include "sys.h"
`include "iop.h"
module one_hot_mux_mon ();
wire clk = cmp_top.iop.sparc0.rclk ;
wire rst_l = cmp_top.iop.sparc0.spc_grst_l ;
reg check_on ;
reg rst_done ;
////////////////////////////////////////////////////////////////////////////////
// Look for proper reset deassertion
////////////////////////////////////////////////////////////////////////////////
initial begin
rst_done = 1'b0 ;
repeat (4) @(posedge cmp_top.iop.sparc0.rclk) ;
@(posedge cmp_top.iop.sparc0.spc_grst_l) ;
repeat (4) @(posedge cmp_top.iop.sparc0.rclk) ;
rst_done = 1'b1 ;
end
////////////////////////////////////////////////////////////////////////////////
// enable/disable using a +arg
////////////////////////////////////////////////////////////////////////////////
initial begin
check_on = 0 ;
if ($test$plusargs("one_hot_mux_mon_on")) begin
check_on = 1 ;
end
end
////////////////////////////////////////////////////////////////////////////////
// check one hot sel for 3 sel muxes
////////////////////////////////////////////////////////////////////////////////
task one_hot_mux3 ;
input rst_l ;
input [2:0] sel ;
input [4095:0] name ;
if (rst_l) begin
if ((sel !== 3'b001) &&
(sel !== 3'b010) &&
(sel !== 3'b100)) begin
$display("%0d : ERROR : %0s is not one hot, it has the value %3b\n", $time, name, sel) ;
$finish() ;
end
end
endtask
////////////////////////////////////////////////////////////////////////////////
// check one hot sel for 4 sel muxes
////////////////////////////////////////////////////////////////////////////////
task one_hot_mux4 ;
input rst_l ;
input [3:0] sel ;
input [4095:0] name ;
if (rst_l) begin
if ((sel !== 4'b0001) &&
(sel !== 4'b0010) &&
(sel !== 4'b0100) &&
(sel !== 4'b1000)) begin
$display("%0d : ERROR : %0s is not one hot, it has the value %4b\n", $time, name, sel) ;
$finish() ;
end
end
endtask
`ifdef RTL_SPARC0
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc0.ifu.icd.icden_mux.sel, "sparc0.ifu.icd.icden_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.dcdp.align_byte1_1h_mx.sel, "sparc0.lsu.dcdp.align_byte1_1h_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.dcdp.align_byte2_1st_mx.sel, "sparc0.lsu.dcdp.align_byte2_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.dcdp.align_byte3_1st_mx.sel, "sparc0.lsu.dcdp.align_byte3_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.dctldp.tlb_ctxt_mux.sel, "sparc0.lsu.dctldp.tlb_ctxt_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp1.ldbyp0_data_mx.sel, "sparc0.lsu.qdp1.ldbyp0_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp1.ldbyp0_ldxa_mx.sel, "sparc0.lsu.qdp1.ldbyp0_ldxa_mx") ;
`ifdef FPGA_SYN_1THREAD
`else
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp1.ldbyp1_data_mx.sel, "sparc0.lsu.qdp1.ldbyp1_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp1.ldbyp1_ldxa_mx.sel, "sparc0.lsu.qdp1.ldbyp1_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp1.ldbyp2_data_mx.sel, "sparc0.lsu.qdp1.ldbyp2_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp1.ldbyp2_ldxa_mx.sel, "sparc0.lsu.qdp1.ldbyp2_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp1.ldbyp3_data_mx.sel, "sparc0.lsu.qdp1.ldbyp3_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp1.ldbyp3_ldxa_mx.sel, "sparc0.lsu.qdp1.ldbyp3_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp1.lmq_dthrd_sel1.sel, "sparc0.lsu.qdp1.lmq_dthrd_sel1") ;
`endif
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.stb_rwdp.swap_byte0_mx.sel, "sparc0.lsu.stb_rwdp.swap_byte0_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.stb_rwdp.swap_byte1_mx.sel, "sparc0.lsu.stb_rwdp.swap_byte1_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.stb_rwdp.swap_byte2_mx.sel, "sparc0.lsu.stb_rwdp.swap_byte2_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.stb_rwdp.swap_byte3_mx.sel, "sparc0.lsu.stb_rwdp.swap_byte3_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.stb_rwdp.swap_byte4_mx.sel, "sparc0.lsu.stb_rwdp.swap_byte4_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.stb_rwdp.swap_byte5_mx.sel, "sparc0.lsu.stb_rwdp.swap_byte5_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.stb_rwdp.swap_byte6_mx.sel, "sparc0.lsu.stb_rwdp.swap_byte6_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.stb_rwdp.swap_byte7_mx.sel, "sparc0.lsu.stb_rwdp.swap_byte7_mx") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc0.tlu.mmu_dp.dtag_access_dsel.sel, "sparc0.tlu.mmu_dp.dtag_access_dsel") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc0.lsu.qdp2.st_dcfill_wrway_sel_b54.sel, "sparc0.lsu.qdp2.st_dcfill_wrway_sel_b54") ;
end
end
`endif
`ifdef RTL_SPARC1
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc1.ifu.icd.icden_mux.sel, "sparc1.ifu.icd.icden_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.dcdp.align_byte1_1h_mx.sel, "sparc1.lsu.dcdp.align_byte1_1h_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.dcdp.align_byte2_1st_mx.sel, "sparc1.lsu.dcdp.align_byte2_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.dcdp.align_byte3_1st_mx.sel, "sparc1.lsu.dcdp.align_byte3_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.dctldp.tlb_ctxt_mux.sel, "sparc1.lsu.dctldp.tlb_ctxt_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp1.ldbyp0_data_mx.sel, "sparc1.lsu.qdp1.ldbyp0_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp1.ldbyp0_ldxa_mx.sel, "sparc1.lsu.qdp1.ldbyp0_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp1.ldbyp1_data_mx.sel, "sparc1.lsu.qdp1.ldbyp1_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp1.ldbyp1_ldxa_mx.sel, "sparc1.lsu.qdp1.ldbyp1_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp1.ldbyp2_data_mx.sel, "sparc1.lsu.qdp1.ldbyp2_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp1.ldbyp2_ldxa_mx.sel, "sparc1.lsu.qdp1.ldbyp2_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp1.ldbyp3_data_mx.sel, "sparc1.lsu.qdp1.ldbyp3_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp1.ldbyp3_ldxa_mx.sel, "sparc1.lsu.qdp1.ldbyp3_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp1.lmq_dthrd_sel1.sel, "sparc1.lsu.qdp1.lmq_dthrd_sel1") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.stb_rwdp.swap_byte0_mx.sel, "sparc1.lsu.stb_rwdp.swap_byte0_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.stb_rwdp.swap_byte1_mx.sel, "sparc1.lsu.stb_rwdp.swap_byte1_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.stb_rwdp.swap_byte2_mx.sel, "sparc1.lsu.stb_rwdp.swap_byte2_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.stb_rwdp.swap_byte3_mx.sel, "sparc1.lsu.stb_rwdp.swap_byte3_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.stb_rwdp.swap_byte4_mx.sel, "sparc1.lsu.stb_rwdp.swap_byte4_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.stb_rwdp.swap_byte5_mx.sel, "sparc1.lsu.stb_rwdp.swap_byte5_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.stb_rwdp.swap_byte6_mx.sel, "sparc1.lsu.stb_rwdp.swap_byte6_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.stb_rwdp.swap_byte7_mx.sel, "sparc1.lsu.stb_rwdp.swap_byte7_mx") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc1.tlu.mmu_dp.dtag_access_dsel.sel, "sparc1.tlu.mmu_dp.dtag_access_dsel") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc1.lsu.qdp2.st_dcfill_wrway_sel_b54.sel, "sparc1.lsu.qdp2.st_dcfill_wrway_sel_b54") ;
end
end
`endif
`ifdef RTL_SPARC2
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc2.ifu.icd.icden_mux.sel, "sparc2.ifu.icd.icden_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.dcdp.align_byte1_1h_mx.sel, "sparc2.lsu.dcdp.align_byte1_1h_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.dcdp.align_byte2_1st_mx.sel, "sparc2.lsu.dcdp.align_byte2_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.dcdp.align_byte3_1st_mx.sel, "sparc2.lsu.dcdp.align_byte3_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.dctldp.tlb_ctxt_mux.sel, "sparc2.lsu.dctldp.tlb_ctxt_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp1.ldbyp0_data_mx.sel, "sparc2.lsu.qdp1.ldbyp0_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp1.ldbyp0_ldxa_mx.sel, "sparc2.lsu.qdp1.ldbyp0_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp1.ldbyp1_data_mx.sel, "sparc2.lsu.qdp1.ldbyp1_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp1.ldbyp1_ldxa_mx.sel, "sparc2.lsu.qdp1.ldbyp1_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp1.ldbyp2_data_mx.sel, "sparc2.lsu.qdp1.ldbyp2_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp1.ldbyp2_ldxa_mx.sel, "sparc2.lsu.qdp1.ldbyp2_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp1.ldbyp3_data_mx.sel, "sparc2.lsu.qdp1.ldbyp3_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp1.ldbyp3_ldxa_mx.sel, "sparc2.lsu.qdp1.ldbyp3_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp1.lmq_dthrd_sel1.sel, "sparc2.lsu.qdp1.lmq_dthrd_sel1") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.stb_rwdp.swap_byte0_mx.sel, "sparc2.lsu.stb_rwdp.swap_byte0_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.stb_rwdp.swap_byte1_mx.sel, "sparc2.lsu.stb_rwdp.swap_byte1_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.stb_rwdp.swap_byte2_mx.sel, "sparc2.lsu.stb_rwdp.swap_byte2_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.stb_rwdp.swap_byte3_mx.sel, "sparc2.lsu.stb_rwdp.swap_byte3_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.stb_rwdp.swap_byte4_mx.sel, "sparc2.lsu.stb_rwdp.swap_byte4_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.stb_rwdp.swap_byte5_mx.sel, "sparc2.lsu.stb_rwdp.swap_byte5_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.stb_rwdp.swap_byte6_mx.sel, "sparc2.lsu.stb_rwdp.swap_byte6_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.stb_rwdp.swap_byte7_mx.sel, "sparc2.lsu.stb_rwdp.swap_byte7_mx") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc2.tlu.mmu_dp.dtag_access_dsel.sel, "sparc2.tlu.mmu_dp.dtag_access_dsel") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc2.lsu.qdp2.st_dcfill_wrway_sel_b54.sel, "sparc2.lsu.qdp2.st_dcfill_wrway_sel_b54") ;
end
end
`endif
`ifdef RTL_SPARC3
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc3.ifu.icd.icden_mux.sel, "sparc3.ifu.icd.icden_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.dcdp.align_byte1_1h_mx.sel, "sparc3.lsu.dcdp.align_byte1_1h_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.dcdp.align_byte2_1st_mx.sel, "sparc3.lsu.dcdp.align_byte2_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.dcdp.align_byte3_1st_mx.sel, "sparc3.lsu.dcdp.align_byte3_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.dctldp.tlb_ctxt_mux.sel, "sparc3.lsu.dctldp.tlb_ctxt_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp1.ldbyp0_data_mx.sel, "sparc3.lsu.qdp1.ldbyp0_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp1.ldbyp0_ldxa_mx.sel, "sparc3.lsu.qdp1.ldbyp0_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp1.ldbyp1_data_mx.sel, "sparc3.lsu.qdp1.ldbyp1_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp1.ldbyp1_ldxa_mx.sel, "sparc3.lsu.qdp1.ldbyp1_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp1.ldbyp2_data_mx.sel, "sparc3.lsu.qdp1.ldbyp2_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp1.ldbyp2_ldxa_mx.sel, "sparc3.lsu.qdp1.ldbyp2_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp1.ldbyp3_data_mx.sel, "sparc3.lsu.qdp1.ldbyp3_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp1.ldbyp3_ldxa_mx.sel, "sparc3.lsu.qdp1.ldbyp3_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp1.lmq_dthrd_sel1.sel, "sparc3.lsu.qdp1.lmq_dthrd_sel1") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.stb_rwdp.swap_byte0_mx.sel, "sparc3.lsu.stb_rwdp.swap_byte0_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.stb_rwdp.swap_byte1_mx.sel, "sparc3.lsu.stb_rwdp.swap_byte1_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.stb_rwdp.swap_byte2_mx.sel, "sparc3.lsu.stb_rwdp.swap_byte2_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.stb_rwdp.swap_byte3_mx.sel, "sparc3.lsu.stb_rwdp.swap_byte3_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.stb_rwdp.swap_byte4_mx.sel, "sparc3.lsu.stb_rwdp.swap_byte4_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.stb_rwdp.swap_byte5_mx.sel, "sparc3.lsu.stb_rwdp.swap_byte5_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.stb_rwdp.swap_byte6_mx.sel, "sparc3.lsu.stb_rwdp.swap_byte6_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.stb_rwdp.swap_byte7_mx.sel, "sparc3.lsu.stb_rwdp.swap_byte7_mx") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc3.tlu.mmu_dp.dtag_access_dsel.sel, "sparc3.tlu.mmu_dp.dtag_access_dsel") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc3.lsu.qdp2.st_dcfill_wrway_sel_b54.sel, "sparc3.lsu.qdp2.st_dcfill_wrway_sel_b54") ;
end
end
`endif
`ifdef RTL_SPARC4
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc4.ifu.icd.icden_mux.sel, "sparc4.ifu.icd.icden_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.dcdp.align_byte1_1h_mx.sel, "sparc4.lsu.dcdp.align_byte1_1h_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.dcdp.align_byte2_1st_mx.sel, "sparc4.lsu.dcdp.align_byte2_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.dcdp.align_byte3_1st_mx.sel, "sparc4.lsu.dcdp.align_byte3_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.dctldp.tlb_ctxt_mux.sel, "sparc4.lsu.dctldp.tlb_ctxt_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp1.ldbyp0_data_mx.sel, "sparc4.lsu.qdp1.ldbyp0_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp1.ldbyp0_ldxa_mx.sel, "sparc4.lsu.qdp1.ldbyp0_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp1.ldbyp1_data_mx.sel, "sparc4.lsu.qdp1.ldbyp1_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp1.ldbyp1_ldxa_mx.sel, "sparc4.lsu.qdp1.ldbyp1_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp1.ldbyp2_data_mx.sel, "sparc4.lsu.qdp1.ldbyp2_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp1.ldbyp2_ldxa_mx.sel, "sparc4.lsu.qdp1.ldbyp2_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp1.ldbyp3_data_mx.sel, "sparc4.lsu.qdp1.ldbyp3_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp1.ldbyp3_ldxa_mx.sel, "sparc4.lsu.qdp1.ldbyp3_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp1.lmq_dthrd_sel1.sel, "sparc4.lsu.qdp1.lmq_dthrd_sel1") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.stb_rwdp.swap_byte0_mx.sel, "sparc4.lsu.stb_rwdp.swap_byte0_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.stb_rwdp.swap_byte1_mx.sel, "sparc4.lsu.stb_rwdp.swap_byte1_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.stb_rwdp.swap_byte2_mx.sel, "sparc4.lsu.stb_rwdp.swap_byte2_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.stb_rwdp.swap_byte3_mx.sel, "sparc4.lsu.stb_rwdp.swap_byte3_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.stb_rwdp.swap_byte4_mx.sel, "sparc4.lsu.stb_rwdp.swap_byte4_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.stb_rwdp.swap_byte5_mx.sel, "sparc4.lsu.stb_rwdp.swap_byte5_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.stb_rwdp.swap_byte6_mx.sel, "sparc4.lsu.stb_rwdp.swap_byte6_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.stb_rwdp.swap_byte7_mx.sel, "sparc4.lsu.stb_rwdp.swap_byte7_mx") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc4.tlu.mmu_dp.dtag_access_dsel.sel, "sparc4.tlu.mmu_dp.dtag_access_dsel") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc4.lsu.qdp2.st_dcfill_wrway_sel_b54.sel, "sparc4.lsu.qdp2.st_dcfill_wrway_sel_b54") ;
end
end
`endif
`ifdef RTL_SPARC5
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc5.ifu.icd.icden_mux.sel, "sparc5.ifu.icd.icden_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.dcdp.align_byte1_1h_mx.sel, "sparc5.lsu.dcdp.align_byte1_1h_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.dcdp.align_byte2_1st_mx.sel, "sparc5.lsu.dcdp.align_byte2_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.dcdp.align_byte3_1st_mx.sel, "sparc5.lsu.dcdp.align_byte3_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.dctldp.tlb_ctxt_mux.sel, "sparc5.lsu.dctldp.tlb_ctxt_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp1.ldbyp0_data_mx.sel, "sparc5.lsu.qdp1.ldbyp0_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp1.ldbyp0_ldxa_mx.sel, "sparc5.lsu.qdp1.ldbyp0_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp1.ldbyp1_data_mx.sel, "sparc5.lsu.qdp1.ldbyp1_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp1.ldbyp1_ldxa_mx.sel, "sparc5.lsu.qdp1.ldbyp1_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp1.ldbyp2_data_mx.sel, "sparc5.lsu.qdp1.ldbyp2_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp1.ldbyp2_ldxa_mx.sel, "sparc5.lsu.qdp1.ldbyp2_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp1.ldbyp3_data_mx.sel, "sparc5.lsu.qdp1.ldbyp3_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp1.ldbyp3_ldxa_mx.sel, "sparc5.lsu.qdp1.ldbyp3_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp1.lmq_dthrd_sel1.sel, "sparc5.lsu.qdp1.lmq_dthrd_sel1") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.stb_rwdp.swap_byte0_mx.sel, "sparc5.lsu.stb_rwdp.swap_byte0_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.stb_rwdp.swap_byte1_mx.sel, "sparc5.lsu.stb_rwdp.swap_byte1_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.stb_rwdp.swap_byte2_mx.sel, "sparc5.lsu.stb_rwdp.swap_byte2_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.stb_rwdp.swap_byte3_mx.sel, "sparc5.lsu.stb_rwdp.swap_byte3_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.stb_rwdp.swap_byte4_mx.sel, "sparc5.lsu.stb_rwdp.swap_byte4_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.stb_rwdp.swap_byte5_mx.sel, "sparc5.lsu.stb_rwdp.swap_byte5_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.stb_rwdp.swap_byte6_mx.sel, "sparc5.lsu.stb_rwdp.swap_byte6_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.stb_rwdp.swap_byte7_mx.sel, "sparc5.lsu.stb_rwdp.swap_byte7_mx") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc5.tlu.mmu_dp.dtag_access_dsel.sel, "sparc5.tlu.mmu_dp.dtag_access_dsel") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc5.lsu.qdp2.st_dcfill_wrway_sel_b54.sel, "sparc5.lsu.qdp2.st_dcfill_wrway_sel_b54") ;
end
end
`endif
`ifdef RTL_SPARC6
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc6.ifu.icd.icden_mux.sel, "sparc6.ifu.icd.icden_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.dcdp.align_byte1_1h_mx.sel, "sparc6.lsu.dcdp.align_byte1_1h_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.dcdp.align_byte2_1st_mx.sel, "sparc6.lsu.dcdp.align_byte2_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.dcdp.align_byte3_1st_mx.sel, "sparc6.lsu.dcdp.align_byte3_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.dctldp.tlb_ctxt_mux.sel, "sparc6.lsu.dctldp.tlb_ctxt_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp1.ldbyp0_data_mx.sel, "sparc6.lsu.qdp1.ldbyp0_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp1.ldbyp0_ldxa_mx.sel, "sparc6.lsu.qdp1.ldbyp0_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp1.ldbyp1_data_mx.sel, "sparc6.lsu.qdp1.ldbyp1_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp1.ldbyp1_ldxa_mx.sel, "sparc6.lsu.qdp1.ldbyp1_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp1.ldbyp2_data_mx.sel, "sparc6.lsu.qdp1.ldbyp2_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp1.ldbyp2_ldxa_mx.sel, "sparc6.lsu.qdp1.ldbyp2_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp1.ldbyp3_data_mx.sel, "sparc6.lsu.qdp1.ldbyp3_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp1.ldbyp3_ldxa_mx.sel, "sparc6.lsu.qdp1.ldbyp3_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp1.lmq_dthrd_sel1.sel, "sparc6.lsu.qdp1.lmq_dthrd_sel1") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.stb_rwdp.swap_byte0_mx.sel, "sparc6.lsu.stb_rwdp.swap_byte0_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.stb_rwdp.swap_byte1_mx.sel, "sparc6.lsu.stb_rwdp.swap_byte1_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.stb_rwdp.swap_byte2_mx.sel, "sparc6.lsu.stb_rwdp.swap_byte2_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.stb_rwdp.swap_byte3_mx.sel, "sparc6.lsu.stb_rwdp.swap_byte3_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.stb_rwdp.swap_byte4_mx.sel, "sparc6.lsu.stb_rwdp.swap_byte4_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.stb_rwdp.swap_byte5_mx.sel, "sparc6.lsu.stb_rwdp.swap_byte5_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.stb_rwdp.swap_byte6_mx.sel, "sparc6.lsu.stb_rwdp.swap_byte6_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.stb_rwdp.swap_byte7_mx.sel, "sparc6.lsu.stb_rwdp.swap_byte7_mx") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc6.tlu.mmu_dp.dtag_access_dsel.sel, "sparc6.tlu.mmu_dp.dtag_access_dsel") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc6.lsu.qdp2.st_dcfill_wrway_sel_b54.sel, "sparc6.lsu.qdp2.st_dcfill_wrway_sel_b54") ;
end
end
`endif
`ifdef RTL_SPARC7
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc7.ifu.icd.icden_mux.sel, "sparc7.ifu.icd.icden_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.dcdp.align_byte1_1h_mx.sel, "sparc7.lsu.dcdp.align_byte1_1h_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.dcdp.align_byte2_1st_mx.sel, "sparc7.lsu.dcdp.align_byte2_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.dcdp.align_byte3_1st_mx.sel, "sparc7.lsu.dcdp.align_byte3_1st_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.dctldp.tlb_ctxt_mux.sel, "sparc7.lsu.dctldp.tlb_ctxt_mux") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp1.ldbyp0_data_mx.sel, "sparc7.lsu.qdp1.ldbyp0_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp1.ldbyp0_ldxa_mx.sel, "sparc7.lsu.qdp1.ldbyp0_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp1.ldbyp1_data_mx.sel, "sparc7.lsu.qdp1.ldbyp1_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp1.ldbyp1_ldxa_mx.sel, "sparc7.lsu.qdp1.ldbyp1_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp1.ldbyp2_data_mx.sel, "sparc7.lsu.qdp1.ldbyp2_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp1.ldbyp2_ldxa_mx.sel, "sparc7.lsu.qdp1.ldbyp2_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp1.ldbyp3_data_mx.sel, "sparc7.lsu.qdp1.ldbyp3_data_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp1.ldbyp3_ldxa_mx.sel, "sparc7.lsu.qdp1.ldbyp3_ldxa_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp1.lmq_dthrd_sel1.sel, "sparc7.lsu.qdp1.lmq_dthrd_sel1") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.stb_rwdp.swap_byte0_mx.sel, "sparc7.lsu.stb_rwdp.swap_byte0_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.stb_rwdp.swap_byte1_mx.sel, "sparc7.lsu.stb_rwdp.swap_byte1_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.stb_rwdp.swap_byte2_mx.sel, "sparc7.lsu.stb_rwdp.swap_byte2_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.stb_rwdp.swap_byte3_mx.sel, "sparc7.lsu.stb_rwdp.swap_byte3_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.stb_rwdp.swap_byte4_mx.sel, "sparc7.lsu.stb_rwdp.swap_byte4_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.stb_rwdp.swap_byte5_mx.sel, "sparc7.lsu.stb_rwdp.swap_byte5_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.stb_rwdp.swap_byte6_mx.sel, "sparc7.lsu.stb_rwdp.swap_byte6_mx") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.stb_rwdp.swap_byte7_mx.sel, "sparc7.lsu.stb_rwdp.swap_byte7_mx") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sparc7.tlu.mmu_dp.dtag_access_dsel.sel, "sparc7.tlu.mmu_dp.dtag_access_dsel") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sparc7.lsu.qdp2.st_dcfill_wrway_sel_b54.sel, "sparc7.lsu.qdp2.st_dcfill_wrway_sel_b54") ;
end
end
`endif
`ifdef RTL_SCTAG0
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux4 (rst_l, `TOP_DESIGN.sctag0.oqdp.mux_tmp_inv_data_c7.sel, "sctag0.oqdp.mux_tmp_inv_data_c7") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sctag0.tagdp.mux_lru_tag.sel, "sctag0.tagdp.mux_lru_tag") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag0.tagl_dp_1.mux_tag_triad0.sel, "sctag0.tagl_dp_1.mux_tag_triad0") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag0.tagl_dp_1.mux_tag_triad1.sel, "sctag0.tagl_dp_1.mux_tag_triad1") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag0.tagl_dp_2.mux_tag_triad0.sel, "sctag0.tagl_dp_1.mux_tag_triad0") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag0.tagl_dp_2.mux_tag_triad1.sel, "sctag0.tagl_dp_1.mux_tag_triad1") ;
end
end
`endif
`ifdef RTL_SCTAG1
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux4 (rst_l, `TOP_DESIGN.sctag1.oqdp.mux_tmp_inv_data_c7.sel, "sctag1.oqdp.mux_tmp_inv_data_c7") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sctag1.tagdp.mux_lru_tag.sel, "sctag1.tagdp.mux_lru_tag") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag1.tagl_dp_1.mux_tag_triad0.sel, "sctag1.tagl_dp_1.mux_tag_triad0") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag1.tagl_dp_1.mux_tag_triad1.sel, "sctag1.tagl_dp_1.mux_tag_triad1") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag1.tagl_dp_2.mux_tag_triad0.sel, "sctag1.tagl_dp_1.mux_tag_triad0") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag1.tagl_dp_2.mux_tag_triad1.sel, "sctag1.tagl_dp_1.mux_tag_triad1") ;
end
end
`endif
`ifdef RTL_SCTAG2
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux4 (rst_l, `TOP_DESIGN.sctag2.oqdp.mux_tmp_inv_data_c7.sel, "sctag2.oqdp.mux_tmp_inv_data_c7") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sctag2.tagdp.mux_lru_tag.sel, "sctag2.tagdp.mux_lru_tag") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag2.tagl_dp_1.mux_tag_triad0.sel, "sctag2.tagl_dp_1.mux_tag_triad0") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag2.tagl_dp_1.mux_tag_triad1.sel, "sctag2.tagl_dp_1.mux_tag_triad1") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag2.tagl_dp_2.mux_tag_triad0.sel, "sctag2.tagl_dp_1.mux_tag_triad0") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag2.tagl_dp_2.mux_tag_triad1.sel, "sctag2.tagl_dp_1.mux_tag_triad1") ;
end
end
`endif
`ifdef RTL_SCTAG3
always @(posedge clk) begin
if (rst_done && check_on) begin
one_hot_mux4 (rst_l, `TOP_DESIGN.sctag3.oqdp.mux_tmp_inv_data_c7.sel, "sctag3.oqdp.mux_tmp_inv_data_c7") ;
one_hot_mux4 (rst_l, `TOP_DESIGN.sctag3.tagdp.mux_lru_tag.sel, "sctag3.tagdp.mux_lru_tag") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag3.tagl_dp_1.mux_tag_triad0.sel, "sctag3.tagl_dp_1.mux_tag_triad0") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag3.tagl_dp_1.mux_tag_triad1.sel, "sctag3.tagl_dp_1.mux_tag_triad1") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag3.tagl_dp_2.mux_tag_triad0.sel, "sctag3.tagl_dp_1.mux_tag_triad0") ;
one_hot_mux3 (rst_l, `TOP_DESIGN.sctag3.tagl_dp_2.mux_tag_triad1.sel, "sctag3.tagl_dp_1.mux_tag_triad1") ;
end
end
`endif
endmodule
|
module contrast_box_in_out #(parameter CLOCK_FREQUENCY = 16000000,
parameter PWM_FREQ = 1000,
parameter EXPONENT = 3, //Exponent which is used to calculate the pwm_on_value = value^EXPONENT
parameter INCREASE_VALUE_AUTOMATIC = 11,
parameter TIME_TO_INCREASE_AUTOMATIC = 100, //value in 10ms //TIME_TO_INCREASE_BIT limits the time: 25->0ms - 2097 ms
parameter INCREASE_VALUE_SWITCH = 11,
parameter TIME_TO_INCREASE_SWITCH = 5, //value in 10ms //TIME_TO_INCREASE_BIT limits the time: 25->0ms - 2097 ms
parameter DECREASE_VALUE_SWITCH = 11,
parameter PWM_REG_WIDTH = 10,
parameter PWM_CYCLE = 1023, //max 2^PWM_REG_WIDTH-1
parameter DEBOUNCE_CNTR_WIDTH = 17) (
input wire clk, //Clock
input wire reset, //Reset-Signal
input wire switch_up, //Switch to increase the value
input wire switch_down, //Switch to decrease the value
output reg pwm_on_value_changed, //1 if the pwm value changed, 0 otherwise
output wire pwm,
//output reg [PWM_REG_WIDTH-1:0] pwm_on_time //the linear pwm_on_value
output wire [PWM_REG_WIDTH-1:0] pwm_exponent_value
);
parameter PWM_CLK_CYCLES = (CLOCK_FREQUENCY/PWM_FREQ)/(PWM_CYCLE+1);
parameter TIME_TO_INCREASE_CYCLE_SWITCH = CLOCK_FREQUENCY*TIME_TO_INCREASE_SWITCH/100;
parameter TIME_TO_INCREASE_CYCLE_AUTO = CLOCK_FREQUENCY*TIME_TO_INCREASE_AUTOMATIC/100;
parameter MAX_PWM_ON_VALUE_SWITCH = PWM_CYCLE - INCREASE_VALUE_SWITCH + 1;
parameter MAX_PWM_ON_VALUE_AUTO = PWM_CYCLE - INCREASE_VALUE_AUTOMATIC + 1;
parameter TIME_TO_INCREASE_BIT = 25;
//control registers
reg [PWM_REG_WIDTH-1:0] pwm_on_time;
//wire [PWM_REG_WIDTH-1:0] pwm_exponent_value;
reg [PWM_REG_WIDTH-1:0] pwm_counter;
wire switch_down_state;
wire switch_down_state_continuous;
wire switch_up_state_continuous;
wire pwm_clk;
reg [PWM_REG_WIDTH-1:0] pwm_clk_cnt; //BIT BREITE MUSS ANGEPASST WERDEN
reg [TIME_TO_INCREASE_BIT-1:0] time_to_increase_switch_cnt;
reg [TIME_TO_INCREASE_BIT-1:0] time_to_increase_auto_cnt;
reg time_to_increase_switch;
reg time_to_increase_auto;
//Button debounce => active LOW switch
//Variate the COUNTER_WIDTH for longer or shorter debounce time
PushButton_Debouncer #(.COUNTER_WIDTH(DEBOUNCE_CNTR_WIDTH)) debounce_down (
.clk(clk),
.PB(switch_down),
.PB_state(switch_down_state_continuous),
.PB_down(),
.PB_up(switch_down_state));
PushButton_Debouncer #(.COUNTER_WIDTH(DEBOUNCE_CNTR_WIDTH)) debounce_up (
.clk(clk),
.PB(switch_up),
.PB_state(switch_up_state_continuous),
.PB_down(),
.PB_up());
init_ROM #(.ROM_WIDTH(PWM_REG_WIDTH), .ROM_DEPTH(PWM_REG_WIDTH), .EXPONENT(EXPONENT)) rom (
.addr(pwm_on_time),
.data_out(pwm_exponent_value));
//automatic increase pwm duty cycle
always @(posedge clk or posedge reset) begin
if(reset) begin
time_to_increase_switch_cnt <= {(TIME_TO_INCREASE_BIT){1'b0}};
time_to_increase_switch <= 1'b0;
time_to_increase_auto_cnt <= {(TIME_TO_INCREASE_BIT){1'b0}};
time_to_increase_auto <= 1'b0;
end else begin
if((switch_down_state_continuous ^ switch_up_state_continuous)) begin
//If one button is pressed, increase or decrease the pwm_on_value in the given time intervales
if(time_to_increase_switch_cnt < TIME_TO_INCREASE_CYCLE_SWITCH) time_to_increase_switch_cnt <= time_to_increase_switch_cnt + 1;
else time_to_increase_switch_cnt <= {(TIME_TO_INCREASE_BIT){1'b0}};
if(time_to_increase_switch_cnt == TIME_TO_INCREASE_CYCLE_SWITCH) time_to_increase_switch <= 1'b1;
else time_to_increase_switch <= 1'b0;
end else begin
time_to_increase_switch_cnt <= {(TIME_TO_INCREASE_BIT){1'b0}};
time_to_increase_switch <= 1'b0;
end
if(TIME_TO_INCREASE_AUTOMATIC > 0) begin
//Automatic increase
if(time_to_increase_auto_cnt < TIME_TO_INCREASE_CYCLE_AUTO) time_to_increase_auto_cnt <= time_to_increase_auto_cnt + 1;
else time_to_increase_auto_cnt <= {(TIME_TO_INCREASE_BIT){1'b0}};
if(time_to_increase_auto_cnt == TIME_TO_INCREASE_CYCLE_AUTO) time_to_increase_auto <= 1'b1;
else time_to_increase_auto <= 1'b0;
end else begin
time_to_increase_auto_cnt <= {(TIME_TO_INCREASE_BIT){1'b0}};
time_to_increase_auto <= 1'b0;
end
end
end
//Button logic
always @(posedge clk) begin
//Continous case
//increase or decrease the pwm value if the button is pressed
if(switch_down_state_continuous ^ switch_up_state_continuous) begin
if(switch_down_state_continuous) begin
if(time_to_increase_switch && (pwm_on_time > (DECREASE_VALUE_SWITCH-1))) begin
pwm_on_time <= pwm_on_time - DECREASE_VALUE_SWITCH;
pwm_on_value_changed <= 1'b1;
end else pwm_on_value_changed <= 1'b0;
end else begin
if(time_to_increase_switch && (pwm_on_time < MAX_PWM_ON_VALUE_SWITCH)) begin
pwm_on_time <= pwm_on_time + INCREASE_VALUE_SWITCH;
pwm_on_value_changed <= 1'b1;
end else pwm_on_value_changed <= 1'b0;
end
end else begin
if(time_to_increase_auto && (pwm_on_time < MAX_PWM_ON_VALUE_AUTO)) begin
pwm_on_time <= pwm_on_time + INCREASE_VALUE_AUTOMATIC;
pwm_on_value_changed <= 1'b1;
end else pwm_on_value_changed <= 1'b0;
end
end
//PWM logic
//Generate PWM Clock
assign pwm_clk = pwm_clk_cnt < (PWM_CLK_CYCLES>>2);
always @(posedge clk or posedge reset) begin
if(reset) begin
pwm_clk_cnt <= {(PWM_REG_WIDTH){1'b0}}; //reset counter to 0
end else begin
if(pwm_clk_cnt < PWM_CLK_CYCLES) pwm_clk_cnt <= pwm_clk_cnt + 1;
else pwm_clk_cnt <= {(PWM_REG_WIDTH){1'b0}};
end
end
//assign pwm = (pwm_counter < pwm_on_time); //the linear pwm_on_value
assign pwm = (pwm_counter < pwm_exponent_value);
always @(posedge pwm_clk or posedge reset) begin
if(reset) begin
pwm_counter <= {(PWM_REG_WIDTH){1'b0}}; //reset counter to 0
end else begin
if (pwm_counter == PWM_CYCLE) begin
pwm_counter <= {(PWM_REG_WIDTH){1'b0}}; //reset counter if max value reached
end else begin
pwm_counter <= pwm_counter + 1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:48:59 03/24/2015
// Design Name:
// Module Name: Adder32
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Adder16(
input [15:0] A,
input [15:0] B,
input C0,
output [3:0] P,
output [3:0] G,
output [15:0] sum,
output SF,
output CF,
output OF,
output PF,
output ZF
);
wire[15:0] _p_,_g_;
wire[4:0] C;
wire[3:0] _sf_,_cf_,_of_,_pf_,_zf_;
pg_to_PG pgtoPG(_p_,_g_,P,G);
ParallelCarry4 PC(P,G,C0,C);
Adder4
a1(A[ 3: 0],B[ 3: 0],C[0],_p_[ 3: 0],_g_[ 3: 0],sum[ 3: 0],_sf_[0],_cf_[0],_of_[0],_pf_[0],_zf_[0]),
a2(A[ 7: 4],B[ 7: 4],C[1],_p_[ 7: 4],_g_[ 7: 4],sum[ 7: 4],_sf_[1],_cf_[1],_of_[1],_pf_[1],_zf_[1]),
a3(A[11: 8],B[11: 8],C[2],_p_[11: 8],_g_[11: 8],sum[11: 8],_sf_[2],_cf_[2],_of_[2],_pf_[2],_zf_[2]),
a4(A[15:12],B[15:12],C[3],_p_[15:12],_g_[15:12],sum[15:12],_sf_[3],_cf_[3],_of_[3],_pf_[3],_zf_[3]);
assign SF=_sf_[3],
CF=C[4],
OF=_of_[3],
PF=^_pf_[3:0],
ZF= ~|(~_zf_[3:0]);
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Tawas RCN bus interface:
//
// Perform load/store operations over RCN.
// Stall issueing thread while transaction is pending.
// Stall all threads if bus backpressure fills issue buffer.
//
module tawas_rcn
(
input clk,
input rst,
input [4:0] thread_decode,
output [31:0] rcn_stall,
input rcn_cs,
input rcn_xch,
input rcn_wr,
input [31:0] rcn_addr,
input [2:0] rcn_wbreg,
input [3:0] rcn_mask,
input [31:0] rcn_wdata,
output reg rcn_load_en,
output reg [4:0] rcn_load_thread,
output reg [2:0] rcn_load_reg,
output reg [31:0] rcn_load_data,
input [68:0] rcn_in,
output [68:0] rcn_out
);
parameter MASTER_GROUP_8 = 0;
reg [4:0] seq;
wire rdone;
wire wdone;
wire [4:0] rsp_seq;
wire [3:0] rsp_mask;
wire [31:0] rsp_data;
wire master_full;
always @ (posedge clk)
seq <= thread_decode;
tawas_rcn_master_buf #(.MASTER_GROUP_8(MASTER_GROUP_8)) rcn_master
(
.rst(rst),
.clk(clk),
.rcn_in(rcn_in),
.rcn_out(rcn_out),
.cs(rcn_cs),
.seq(seq),
.wr(rcn_wr),
.mask(rcn_mask),
.addr(rcn_addr[23:0]),
.wdata(rcn_wdata),
.full(master_full),
.rdone(rdone),
.wdone(wdone),
.rsp_seq(rsp_seq),
.rsp_mask(rsp_mask),
.rsp_addr(),
.rsp_data(rsp_data)
);
//
// Core thread stalls
//
reg rdone_d1;
reg rdone_d2;
reg rdone_d3;
reg wdone_d1;
reg wdone_d2;
reg wdone_d3;
reg [4:0] rsp_seq_d1;
reg [4:0] rsp_seq_d2;
reg [4:0] rsp_seq_d3;
always @ (posedge clk)
begin
rdone_d1 <= rdone;
rdone_d2 <= rdone_d1;
rdone_d3 <= rdone_d2;
wdone_d1 <= wdone;
wdone_d2 <= wdone_d1;
wdone_d3 <= wdone_d2;
rsp_seq_d1 <= rsp_seq;
rsp_seq_d2 <= rsp_seq_d1;
rsp_seq_d3 <= rsp_seq_d2;
end
reg [31:0] pending_stall;
wire [31:0] set_pending_stall = (rcn_cs) ? (32'd1 << seq) : 32'd0;
wire [31:0] clr_pending_stall = (rdone_d3 || wdone_d3) ? (32'd1 << rsp_seq_d3) : 32'd0;
always @ (posedge clk or posedge rst)
if (rst)
pending_stall <= 32'd0;
else
pending_stall <= (pending_stall | set_pending_stall) & ~clr_pending_stall;
assign rcn_stall = pending_stall | {32{master_full}};
//
// Read retire
//
reg [2:0] wbreg[31:0];
reg xch[31:0];
always @ (posedge clk)
if (rcn_cs)
begin
wbreg[seq] <= rcn_wbreg;
xch[seq] <= rcn_wr && rcn_xch;
end
wire [31:0] rsp_data_adj = (rsp_mask[3:0] == 4'b1111) ? rsp_data[31:0] :
(rsp_mask[3:2] == 2'b11) ? {16'd0, rsp_data[31:16]} :
(rsp_mask[1:0] == 2'b11) ? {16'd0, rsp_data[15:0]} :
(rsp_mask[3]) ? {24'd0, rsp_data[31:24]} :
(rsp_mask[2]) ? {24'd0, rsp_data[23:16]} :
(rsp_mask[1]) ? {24'd0, rsp_data[15:8]} : {24'd0, rsp_data[7:0]};
always @ *
begin
rcn_load_en = rdone || (wdone && xch[rsp_seq]);
rcn_load_thread = rsp_seq;
rcn_load_reg = wbreg[rsp_seq];
rcn_load_data = rsp_data_adj;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_adc_1c (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
// dma interface (refer to xilinx AXI_DMA doc. for details)
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
// processor (control) interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
up_status,
// delay elements clock (200MHz for most devices)
delay_clk,
// dma debug and monitor signals (for chipscope)
dma_dbg_data,
dma_dbg_trigger,
// adc debug and monitor signals (for chipscope)
adc_clk,
adc_dbg_data,
adc_dbg_trigger,
adc_mon_valid,
adc_mon_data);
// This parameter controls the buffer type based on the target device.
// Refer to the adc interface, where IOBUF*s are instantiated for details.
// The default (0x0) is 7 series and covers Zynq also.
parameter C_CF_BUFTYPE = 0;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
// dma interface (refer to xilinx AXI_DMA doc. for details)
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
// processor (control) interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output [ 7:0] up_status;
// delay elements clock (200MHz for most devices)
input delay_clk;
// dma debug and monitor signals (for chipscope)
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
// adc debug and monitor signals (for chipscope)
output adc_clk;
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
output adc_mon_valid;
output [15:0] adc_mon_data;
reg up_capture = 'd0;
reg [15:0] up_capture_count = 'd0;
reg up_dma_unf_hold = 'd0;
reg up_dma_ovf_hold = 'd0;
reg up_dma_status = 'd0;
reg up_adc_or_hold = 'd0;
reg up_adc_pn_oos_hold = 'd0;
reg up_adc_pn_err_hold = 'd0;
reg up_dmode = 'd0;
reg up_delay_sel = 'd0;
reg up_delay_rwn = 'd0;
reg [ 3:0] up_delay_addr = 'd0;
reg [ 4:0] up_delay_wdata = 'd0;
reg up_pn_type = 'd0;
reg [ 7:0] up_status = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
reg up_dma_ovf_m1 = 'd0;
reg up_dma_ovf_m2 = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf_m1 = 'd0;
reg up_dma_unf_m2 = 'd0;
reg up_dma_unf = 'd0;
reg up_dma_complete_m1 = 'd0;
reg up_dma_complete_m2 = 'd0;
reg up_dma_complete_m3 = 'd0;
reg up_dma_complete = 'd0;
reg up_adc_or_m1 = 'd0;
reg up_adc_or_m2 = 'd0;
reg up_adc_or = 'd0;
reg up_adc_pn_oos_m1 = 'd0;
reg up_adc_pn_oos_m2 = 'd0;
reg up_adc_pn_oos = 'd0;
reg up_adc_pn_err_m1 = 'd0;
reg up_adc_pn_err_m2 = 'd0;
reg up_adc_pn_err = 'd0;
reg up_delay_ack_m1 = 'd0;
reg up_delay_ack_m2 = 'd0;
reg up_delay_ack_m3 = 'd0;
reg up_delay_ack = 'd0;
reg [ 4:0] up_delay_rdata = 'd0;
reg up_delay_locked = 'd0;
wire up_wr_s;
wire up_ack_s;
wire dma_ovf_s;
wire dma_unf_s;
wire dma_complete_s;
wire adc_valid_s;
wire [63:0] adc_data_s;
wire adc_or_s;
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire delay_ack_s;
wire [ 4:0] delay_rdata_s;
wire delay_locked_s;
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
// Processor write interface (see regmap.txt file in the pcore root directory
// for address map and details of register functions).
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_capture <= 'd0;
up_capture_count <= 'd0;
up_dma_unf_hold <= 'd0;
up_dma_ovf_hold <= 'd0;
up_dma_status <= 'd0;
up_adc_or_hold <= 'd0;
up_adc_pn_oos_hold <= 'd0;
up_adc_pn_err_hold <= 'd0;
up_dmode <= 'd0;
up_delay_sel <= 'd0;
up_delay_rwn <= 'd0;
up_delay_addr <= 'd0;
up_delay_wdata <= 'd0;
up_pn_type <= 'd0;
up_status <= 'd0;
end else begin
if ((up_addr == 5'h03) && (up_wr_s == 1'b1)) begin
up_capture <= up_wdata[16];
up_capture_count <= up_wdata[15:0];
end
if (up_dma_unf == 1'b1) begin
up_dma_unf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_dma_unf_hold <= up_dma_unf_hold & ~up_wdata[2];
end
if (up_dma_ovf == 1'b1) begin
up_dma_ovf_hold <= 1'b1;
end else if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_dma_ovf_hold <= up_dma_ovf_hold & ~up_wdata[2];
end
if (up_dma_complete == 1'b1) begin
up_dma_status <= 1'b0;
end else if ((up_addr == 5'h03) && (up_wr_s == 1'b1) && (up_dma_status == 1'b0)) begin
up_dma_status <= up_wdata[16];
end
if (up_adc_or == 1'b1) begin
up_adc_or_hold <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_or_hold <= up_adc_or_hold & ~up_wdata[0];
end
if (up_adc_pn_oos == 1'b1) begin
up_adc_pn_oos_hold <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_oos_hold <= up_adc_pn_oos_hold & ~up_wdata[1];
end
if (up_adc_pn_err == 1'b1) begin
up_adc_pn_err_hold <= 1'b1;
end else if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_adc_pn_err_hold <= up_adc_pn_err_hold & ~up_wdata[2];
end
if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_dmode <= up_wdata[0];
end
if ((up_addr == 5'h07) && (up_wr_s == 1'b1)) begin
up_delay_sel <= up_wdata[17];
up_delay_rwn <= up_wdata[16];
up_delay_addr <= up_wdata[11:8];
up_delay_wdata <= up_wdata[4:0];
end
if ((up_addr == 5'h09) && (up_wr_s == 1'b1)) begin
up_pn_type <= up_wdata[0];
end
up_status <= {5'd1, up_capture, up_dma_ovf, up_dma_status};
end
end
// Processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010061;
5'h03: up_rdata <= {15'd0, up_capture, up_capture_count};
5'h04: up_rdata <= {29'd0, up_dma_unf_hold, up_dma_ovf_hold, up_dma_status};
5'h05: up_rdata <= {29'd0, up_adc_pn_err_hold, up_adc_pn_oos_hold, up_adc_or_hold};
5'h06: up_rdata <= {30'd0, up_dmode};
5'h07: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, 4'd0, up_delay_addr,
3'd0, up_delay_wdata};
5'h08: up_rdata <= {23'd0, up_delay_locked, 3'd0, up_delay_rdata};
5'h09: up_rdata <= {31'd0, up_pn_type};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// Status signals from ADC are transferred to the processor clock,
// all signals are strectched to multiple processor clocks from the adc.
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_ovf_m1 <= 'd0;
up_dma_ovf_m2 <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf_m1 <= 'd0;
up_dma_unf_m2 <= 'd0;
up_dma_unf <= 'd0;
up_dma_complete_m1 <= 'd0;
up_dma_complete_m2 <= 'd0;
up_dma_complete_m3 <= 'd0;
up_dma_complete <= 'd0;
end else begin
up_dma_ovf_m1 <= dma_ovf_s;
up_dma_ovf_m2 <= up_dma_ovf_m1;
up_dma_ovf <= up_dma_ovf_m2;
up_dma_unf_m1 <= dma_unf_s;
up_dma_unf_m2 <= up_dma_unf_m1;
up_dma_unf <= up_dma_unf_m2;
up_dma_complete_m1 <= dma_complete_s;
up_dma_complete_m2 <= up_dma_complete_m1;
up_dma_complete_m3 <= up_dma_complete_m2;
up_dma_complete <= up_dma_complete_m3 ^ up_dma_complete_m2;
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_or_m1 <= 'd0;
up_adc_or_m2 <= 'd0;
up_adc_or <= 'd0;
up_adc_pn_oos_m1 <= 'd0;
up_adc_pn_oos_m2 <= 'd0;
up_adc_pn_oos <= 'd0;
up_adc_pn_err_m1 <= 'd0;
up_adc_pn_err_m2 <= 'd0;
up_adc_pn_err <= 'd0;
up_delay_ack_m1 <= 'd0;
up_delay_ack_m2 <= 'd0;
up_delay_ack_m3 <= 'd0;
up_delay_ack <= 'd0;
up_delay_rdata <= 'd0;
up_delay_locked <= 'd0;
end else begin
up_adc_or_m1 <= adc_or_s;
up_adc_or_m2 <= up_adc_or_m1;
up_adc_or <= up_adc_or_m2;
up_adc_pn_oos_m1 <= adc_pn_oos_s;
up_adc_pn_oos_m2 <= up_adc_pn_oos_m1;
up_adc_pn_oos <= up_adc_pn_oos_m2;
up_adc_pn_err_m1 <= adc_pn_err_s;
up_adc_pn_err_m2 <= up_adc_pn_err_m1;
up_adc_pn_err <= up_adc_pn_err_m2;
up_delay_ack_m1 <= delay_ack_s;
up_delay_ack_m2 <= up_delay_ack_m1;
up_delay_ack_m3 <= up_delay_ack_m2;
up_delay_ack <= up_delay_ack_m3 ^ up_delay_ack_m2;
if (up_delay_ack == 1'b1) begin
up_delay_rdata <= delay_rdata_s;
up_delay_locked <= delay_locked_s;
end
end
end
// dma interface, this module transfers data from adc clock domain to
// dma clock domain.
cf_dma_wr i_dma_wr (
.adc_clk (adc_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_master_capture (up_capture),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.dma_ovf (dma_ovf_s),
.dma_unf (dma_unf_s),
.dma_complete (dma_complete_s),
.up_capture_count (up_capture_count),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger));
// adc interface, this module captures data from the adc interface,
// and transfers it to the dma interface module above.
cf_adc_wr #(.C_CF_BUFTYPE(C_CF_BUFTYPE)) i_adc_wr (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_or_p (adc_data_or_p),
.adc_data_or_n (adc_data_or_n),
.adc_clk (adc_clk),
.adc_valid (adc_valid_s),
.adc_data (adc_data_s),
.adc_or (adc_or_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.up_pn_type (up_pn_type),
.up_dmode (up_dmode),
.up_delay_sel (up_delay_sel),
.up_delay_rwn (up_delay_rwn),
.up_delay_addr (up_delay_addr),
.up_delay_wdata (up_delay_wdata),
.delay_clk (delay_clk),
.delay_ack (delay_ack_s),
.delay_rdata (delay_rdata_s),
.delay_locked (delay_locked_s),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A31O_PP_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a31o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_PP_SYMBOL_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 8
(* X_CORE_INFO = "axi_protocol_converter_v2_1_8_axi_protocol_converter,Vivado 2016.1" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_0,axi_protocol_converter_v2_1_8_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_pc_0,axi_protocol_converter_v2_1_8_axi_protocol_converter,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=1,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH\
=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [0 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [0 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [0 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [0 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [0 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_8_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(1),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
/*
Pipeline operator
*/
module jt51_op(
`ifdef TEST_SUPPORT
input test_eg,
input test_op0,
`endif
input clk, // P1
input [9:0] pg_phase_X,
input [2:0] con_I,
input [2:0] fb_II,
// volume
input [9:0] eg_atten_XI,
// modulation
input use_prevprev1,
input use_internal_x,
input use_internal_y,
input use_prev2,
input use_prev1,
input test_214,
input m1_enters,
input c1_enters,
`ifdef SIMULATION
input zero,
`endif
// output data
output signed [13:0] op_XVII
);
/* enters exits
m1 c1
m2 S4
c1 m1
S4 m2
*/
wire signed [13:0] prev1, prevprev1, prev2;
jt51_sh #( .width(14), .stages(8)) prev1_buffer(
.clk ( clk ),
.din ( c1_enters ? op_XVII : prev1 ),
.drop ( prev1 )
);
jt51_sh #( .width(14), .stages(8)) prevprev1_buffer(
.clk ( clk ),
.din ( c1_enters ? prev1 : prevprev1 ),
.drop ( prevprev1 )
);
jt51_sh #( .width(14), .stages(8)) prev2_buffer(
.clk ( clk ),
.din ( m1_enters ? op_XVII : prev2 ),
.drop ( prev2 )
);
// REGISTER/CYCLE 1
// Creation of phase modulation (FM) feedback signal, before shifting
reg [13:0] x, y;
reg [14:0] xs, ys, pm_preshift_II;
reg m1_II;
always @(*) begin
x = ( {14{use_prevprev1}} & prevprev1 ) |
( {14{use_internal_x}} & op_XVII ) |
( {14{use_prev2}} & prev2 );
y = ( {14{use_prev1}} & prev1 ) |
( {14{use_internal_y}} & op_XVII );
xs = { x[13], x }; // sign-extend
ys = { y[13], y }; // sign-extend
end
always @(posedge clk) begin
pm_preshift_II <= xs + ys; // carry is discarded
m1_II <= m1_enters;
end
/* REGISTER/CYCLE 2-7 (also YM2612 extra cycles 1-6)
Shifting of FM feedback signal, adding phase from PG to FM phase
In YM2203, phasemod_II is not registered at all, it is latched on the first edge
in add_pg_phase and the second edge is the output of add_pg_phase. In the YM2612, there
are 6 cycles worth of registers between the generated (non-registered) phasemod_II signal
and the input to add_pg_phase. */
reg [9:0] phasemod_II;
wire [9:0] phasemod_X;
always @(*) begin
// Shift FM feedback signal
if (!m1_II ) // Not m1
phasemod_II = pm_preshift_II[10:1]; // Bit 0 of pm_preshift_II is never used
else // m1
case( fb_II )
3'd0: phasemod_II = 10'd0;
3'd1: phasemod_II = { {4{pm_preshift_II[14]}}, pm_preshift_II[14:9] };
3'd2: phasemod_II = { {3{pm_preshift_II[14]}}, pm_preshift_II[14:8] };
3'd3: phasemod_II = { {2{pm_preshift_II[14]}}, pm_preshift_II[14:7] };
3'd4: phasemod_II = { pm_preshift_II[14], pm_preshift_II[14:6] };
3'd5: phasemod_II = pm_preshift_II[14:5];
3'd6: phasemod_II = pm_preshift_II[13:4];
3'd7: phasemod_II = pm_preshift_II[12:3];
default: phasemod_II = 10'dx;
endcase
end
// REGISTER/CYCLE 2-9
jt51_sh #( .width(10), .stages(8)) phasemod_sh(
.clk ( clk ),
.din ( phasemod_II ),
.drop ( phasemod_X )
);
// REGISTER/CYCLE 10
reg [ 9:0] phase;
// Sets the maximum number of fanouts for a register or combinational
// cell. The Quartus II software will replicate the cell and split
// the fanouts among the duplicates until the fanout of each cell
// is below the maximum.
reg [ 7:0] phaselo_XI, aux_X;
reg signbit_X;
always @(*) begin
phase = phasemod_X + pg_phase_X;
aux_X = phase[7:0] ^ {8{~phase[8]}};
signbit_X = phase[9];
end
always @(posedge clk) begin
phaselo_XI <= aux_X;
end
wire [45:0] sta_XI;
jt51_phrom u_phrom(
.clk ( clk ),
.addr ( aux_X[5:1]),
.ph ( sta_XI )
);
// REGISTER/CYCLE 11
// Sine table
// Main sine table body
reg [18:0] stb;
reg [10:0] stf, stg;
reg [11:0] logsin;
reg [10:0] subtresult;
reg [11:0] atten_internal_XI;
always @(*) begin
//sta_XI = sinetable[ phaselo_XI[5:1] ];
// 2-bit row chooser
case( phaselo_XI[7:6] )
2'b00: stb = { 10'b0, sta_XI[29], sta_XI[25], 2'b0, sta_XI[18],
sta_XI[14], 1'b0, sta_XI[7] , sta_XI[3] };
2'b01: stb = { 6'b0 , sta_XI[37], sta_XI[34], 2'b0, sta_XI[28],
sta_XI[24], 2'b0, sta_XI[17], sta_XI[13], sta_XI[10], sta_XI[6], sta_XI[2] };
2'b10: stb = { 2'b0, sta_XI[43], sta_XI[41], 2'b0, sta_XI[36],
sta_XI[33], 2'b0, sta_XI[27], sta_XI[23], 1'b0, sta_XI[20],
sta_XI[16], sta_XI[12], sta_XI[9], sta_XI[5], sta_XI[1] };
2'b11: stb = {
sta_XI[45], sta_XI[44], sta_XI[42], sta_XI[40]
, sta_XI[39], sta_XI[38], sta_XI[35], sta_XI[32]
, sta_XI[31], sta_XI[30], sta_XI[26], sta_XI[22]
, sta_XI[21], sta_XI[19], sta_XI[15], sta_XI[11]
, sta_XI[8], sta_XI[4], sta_XI[0] };
default: stb = 19'dx;
endcase
// Fixed value to sum
stf = { stb[18:15], stb[12:11], stb[8:7], stb[4:3], stb[0] };
// Gated value to sum; bit 14 is indeed used twice
if( phaselo_XI[0] )
stg = { 2'b0, stb[14], stb[14:13], stb[10:9], stb[6:5], stb[2:1] };
else
stg = 11'd0;
// Sum to produce final logsin value
logsin = stf + stg; // Carry-out of 11-bit addition becomes 12th bit
// Invert-subtract logsin value from EG attenuation value, with inverted carry
// In the actual chip, the output of the above logsin sum is already inverted.
// The two LSBs go through inverters (so they're non-inverted); the eg_atten_XI signal goes through inverters.
// The adder is normal except the carry-in is 1. It's a 10-bit adder.
// The outputs are inverted outputs, including the carry bit.
//subtresult = not (('0' & not eg_atten_XI) - ('1' & logsin([11:2])));
// After a little pencil-and-paper, turns out this is equivalent to a regular adder!
subtresult = eg_atten_XI + logsin[11:2];
// Place all but carry bit into result; also two LSBs of logsin
// If addition overflowed, make it the largest value (saturate)
atten_internal_XI = { subtresult[9:0], logsin[1:0] } | {12{subtresult[10]}};
end
// Register cycle 12
// Exponential table
wire [44:0] exp_XII;
reg [11:0] totalatten_XII;
reg [12:0] etb;
reg [ 9:0] etf, etg;
jt51_exprom u_exprom(
.clk ( clk ),
.addr ( atten_internal_XI[5:1] ),
.exp ( exp_XII )
);
always @(posedge clk) begin
totalatten_XII <= atten_internal_XI;
end
//wire [1:0] et_sel = totalatten_XII[7:6];
//wire [4:0] et_fine = totalatten_XII[5:1];
// Main sine table body
always @(*) begin
// 2-bit row chooser
case( totalatten_XII[7:6] )
2'b00: begin
etf = { 1'b1, exp_XII[44:36] };
etg = { 1'b1, exp_XII[35:34] };
end
2'b01: begin
etf = exp_XII[33:24];
etg = { 2'b10, exp_XII[23] };
end
2'b10: begin
etf = { 1'b0, exp_XII[22:14] };
etg = exp_XII[13:11];
end
2'b11: begin
etf = { 2'b00, exp_XII[10:3] };
etg = exp_XII[2:0];
end
default: begin
etf = 10'dx;
etg = 10'dx;
end
endcase
end
reg [9:0] mantissa_XIII;
reg [3:0] exponent_XIII;
always @(posedge clk) begin
//RESULT
mantissa_XIII <= etf + ( totalatten_XII[0] ? 3'd0 : etg ); //carry-out discarded
exponent_XIII <= totalatten_XII[11:8];
end
// REGISTER/CYCLE 13
// Introduce test bit as MSB, 2's complement & Carry-out discarded
reg [12:0] shifter, shifter_2, shifter_3;
always @(*) begin
// Floating-point to integer, and incorporating sign bit
// Two-stage shifting of mantissa_XIII by exponent_XIII
shifter = { 3'b001, mantissa_XIII };
case( ~exponent_XIII[1:0] )
2'b00: shifter_2 = { 1'b0, shifter[12:1] }; // LSB discarded
2'b01: shifter_2 = shifter;
2'b10: shifter_2 = { shifter[11:0], 1'b0 };
2'b11: shifter_2 = { shifter[10:0], 2'b0 };
default: shifter_2 = {12{1'bx}};
endcase
case( ~exponent_XIII[3:2] )
2'b00: shifter_3 = {12'b0, shifter_2[12] };
2'b01: shifter_3 = { 8'b0, shifter_2[12:8] };
2'b10: shifter_3 = { 4'b0, shifter_2[12:4] };
2'b11: shifter_3 = shifter_2;
default: shifter_3 = {12{1'bx}};
endcase
end
reg signed [13:0] op_XIII;
wire signbit_XIII;
always @(*) begin
op_XIII = ({ test_214, shifter_3 } ^ {14{signbit_XIII}}) + signbit_XIII;
end
jt51_sh #( .width(14), .stages(4)) out_padding(
.clk ( clk ),
.din ( op_XIII ), // note op_XIII was not latched, is a comb output
.drop ( op_XVII )
);
jt51_sh #( .width(1), .stages(3)) shsignbit(
.clk ( clk ),
.din ( signbit_X ),
.drop ( signbit_XIII )
);
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt;
sep32_cnt u_sep32_cnt (.clk(clk), .zero(zero), .cnt(cnt));
sep32 #(.width(14),.stg(17)) sep_op(
.clk ( clk ),
.mixed ( op_XVII ),
.cnt ( cnt )
);
/* verilator lint_on PINMISSING */
`endif
endmodule
|
`timescale 1ns/1ps
module tb_cocotb #(
parameter DATA_WIDTH = 32,
parameter FIFO_WIDTH = 8
)(
input rst,
input [31:0] test_id,
//write side
input WR_CLK,
output WR_RDY,
input WR_ACT,
output [23:0] WR_SIZE,
input WR_STB,
input [DATA_WIDTH - 1: 0] WR_DATA,
output WR_STARVED,
//read side
input RD_CLK,
input RD_STB,
output RD_RDY,
input RD_ACT,
output [23:0] RD_SIZE,
output [DATA_WIDTH - 1: 0] RD_DATA,
output RD_INACTIVE
);
//Local Parameters
//Registers/Wires
reg r_rst;
//Submodules
block_fifo#(
.DATA_WIDTH (DATA_WIDTH ),
.ADDRESS_WIDTH (FIFO_WIDTH )
)pp(
//universal input
.reset (r_rst ),
//Write Path
.write_clock (WR_CLK ),
.write_ready (WR_RDY ),
.write_activate (WR_ACT ),
.write_fifo_size (WR_SIZE ),
.write_strobe (WR_STB ),
.write_data (WR_DATA ),
.starved (WR_STARVED ),
//Read Path
.read_clock (RD_CLK ),
.read_strobe (RD_STB ),
.read_ready (RD_RDY ),
.read_activate (RD_ACT ),
.read_count (RD_SIZE ),
.read_data (RD_DATA ),
.inactive (RD_INACTIVE )
);
//There is a timing thing in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
//`timescale 1 ms /1 us
`include "mux81c.v"
module chap4p32c_tb (S);
// module declaration
output [0:3] S;
reg [0:3] S;
//S[0]=A, S[1]=B, S[2]=C, S[3]=D
wire [0:7] I;
wire Y;
integer fp;
// program body
assign I[0]=~S[3];
assign I[1]=~S[3];
assign I[2]=S[3];
assign I[3]=S[3];
assign I[4]=1'b0;
assign I[5]=S[3];
assign I[6]=1'b0;
assign I[7]=~S[3];
mux81c I1 (I,S[0:2],Y);
initial
begin
fp=$fopen("./chap4p32c_tb.out");
$fmonitor(fp,"time=%0d",$time,,"I=%b S=%b Y=%b",I,S,Y);
#2000
$fclose(fp);
$finish;
end
initial
begin
S=4'b0000;
#100
S=4'b0001;
#100
S=4'b0010;
#100
S=4'b0011;
#100
S=4'b0100;
#100
S=4'b0101;
#100
S=4'b0110;
#100
S=4'b0111;
#100
S=4'b1000;
#100
S=4'b1001;
#100
S=4'b1010;
#100
S=4'b1011;
#100
S=4'b1100;
#100
S=4'b1101;
#100
S=4'b1110;
#100
S=4'b1111;
end
initial #4000 $finish;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22A_BLACKBOX_V
`define SKY130_FD_SC_HD__O22A_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o22a (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22A_BLACKBOX_V
|
`timescale 1ns / 1ps
/* tf528_ram_top.v
Copyright (C) 2016-2017, Stephen J. Leary
All rights reserved.
This file is part of TF328 (Terrible Fire CD32 RAM + IDE BOARD)
TF328 is free: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
TF530 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with TF328. If not, see <http://www.gnu.org/licenses/>.
*/
module ramcpld(
input CLKCPU,
input RESET,
input [23:0] A,
inout [7:0] D,
input [1:0] SIZ,
input IDEINT,
output INT2,
input AS20,
input RW20,
input DS20,
// ram chip control
output RAM_MUX,
output RAMOE,
output [3:0] CAS,
output [1:0] RAS,
output [1:0] RAM_A,
output [1:0] DSACK,
output PUNT,
output IOR,
output IOW,
output [1:0] IDECS
);
// produce an internal data strobe
wire GAYLE_INT2;
// $DA0000
wire GAYLE_IDE = ({A[23:15]} != {8'hDA,1'b0}) | AS20;
// $DE0000 or $DA8000 (Ignores A18)
wire GAYLE_REGS = (A[23:15] != {8'hDA, 1'b1});
wire GAYLE_ID= (A[23:15] != {8'hDE, 1'b0});
wire GAYLE_ACCESS = (GAYLE_ID & GAYLE_REGS) | AS20;
reg [2:0] POR = 3'b111;
wire gayle_dout;
gayle GAYLE(
.CLKCPU ( CLKCPU ),
.RESET ( RESET ),
.CS ( GAYLE_ACCESS ),
.DS ( DS20 | GAYLE_ACCESS ),
.RW ( RW20 ),
.A18 ( A[18] ),
.A ( {A[13:12]} ),
.IDE_INT( IDEINT ),
.INT2 ( GAYLE_INT2 ),
.D7 ( D[7] ),
.DOUT7 ( gayle_dout )
);
reg AS20_D = 1'b1;
reg AS20_D2 = 1'b1;
fastmem FASTRAM(
.CLKCPU ( CLKCPU ),
.RESET ( RESET & ~POR[2] ),
.AS20 ( AS20 ),
.DS20 ( DS20 ),
.RW20 ( RW20 ),
.A ( A ),
.D ( D ),
.SIZ ( SIZ ),
.CAS ( CAS ),
.RAS ( RAS ),
.RAM_MUX ( RAM_MUX ),
.RAMOE ( RAMOE ),
.RAM_A ( RAM_A ),
.RAM_ACCESS ( RAM_ACCESS),
.Z2_ACCESS ( Z2_ACCESS ),
.WAIT ( RAM_WAIT )
);
reg intcycle_dout = 1'b0;
reg GAYLE_D = 1'b1;
reg GAYLE_D2 = 1'b1;
wire DSHOLD2 = {AS20_D,AS20, RW20} == {1'b1,1'b0,1'b0};
wire IOR_INT = ~RW20 | GAYLE_IDE | DSHOLD2;
wire IOW_INT = RW20 | GAYLE_IDE | DSHOLD2;
wire fastcycle_int = (RAM_ACCESS | RAM_WAIT) & GAYLE_D2 & Z2_ACCESS & GAYLE_ACCESS & GAYLE_IDE;
FDCP #(.INIT(1'b1))
FASTCYCLE1_FF (
.Q(FASTCYCLE1), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(fastcycle_int), // Data input
.PRE(AS20) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
FASTCYCLE0_FF (
.Q(FASTCYCLE0), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(fastcycle_int | RAM_ACCESS), // Data input
.PRE(AS20) // Asynchronous set input
);
always @(posedge CLKCPU or negedge RESET) begin
if (RESET == 1'b0) begin
POR <= 'hF;
end else begin
// shift until all 0's
// this will not happen if there isnt a clock
POR[2:0] <= {POR[1:0], 1'b0};
end
end
always @(posedge CLKCPU or posedge AS20) begin
if (AS20 == 1'b1) begin
AS20_D <= 1'b1;
AS20_D2 <= 1'b1;
GAYLE_D <= 1'b1;
GAYLE_D2 <= 1'b1;
end else begin
intcycle_dout <= (~GAYLE_ACCESS) & RW20;
AS20_D <= AS20;
AS20_D2 <= AS20_D;
GAYLE_D2 <= GAYLE_D;
if (GAYLE_IDE == 1'b0) begin
GAYLE_D <= 1'b0;
end
end
end
FDCP #(.INIT(1'b1))
IOR_FF (
.Q(IOR), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(IOR_INT), // Data input
.PRE(AS20) // Asynchronous set input
);
FDCP #(.INIT(1'b1))
IOW_FF (
.Q(IOW), // Data output
.C(CLKCPU), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(IOW_INT), // Data input
.PRE(AS20) // Asynchronous set input
);
assign PUNT = POR[2] | GAYLE_ACCESS & GAYLE_IDE & RAM_ACCESS & Z2_ACCESS ? 1'bz : 1'b0;
assign IDECS = A[12] ? {GAYLE_IDE, 1'b1} : {1'b1, GAYLE_IDE};
assign INT2 = GAYLE_INT2 ? 1'b0 : 1'bz;
wire [7:4] data_out = GAYLE_ACCESS ? 4'b1111 : {gayle_dout,3'b000};
assign D[7:0] = (intcycle_dout) ? {data_out[7:4], 4'h0} : 8'bzzzzzzzz;
assign DSACK[1] = FASTCYCLE1 ? 1'bz : 1'b0;
assign DSACK[0] = FASTCYCLE0 ? 1'bz : 1'b0;
endmodule
|
// final sub module for text
module study_text
(
input wire clk,
input wire [9:0] pix_x, pix_y,
output wire [3:0] study_on,
output reg [2:0] study_rgb
// we output text_rgb only because we have to select it according to FSM
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_r;
// char_addr is the final address selected by MUX
// s stands for score (and ball, but I can not use sb...)
// l stands for logo (well, our special plalindrome logo WPPW)
// r stands for registration information (in this case, student ID and name)
// o stands for over (actually game over I assume, anyway)
reg [3:0] row_addr;
reg [2:0] bit_addr;
wire [7:0] font_word;
wire word_on, font_bit;
wire [5:0] word_rom_addr;
wire [3:0] row_addr_r;
wire [2:0] bit_addr_r;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
assign word_on = (pix_x[9:7]==2) && (pix_y[9:6]==2);
assign row_addr_r = pix_y[3:0];
assign bit_addr_r = pix_x[2:0];
assign word_rom_addr = {pix_y[5:4], pix_x[6:3]};
always @*
case (word_rom_addr)
// row 1 generated by MATLAB
6'h00: char_addr_r = 7'h62;
6'h01: char_addr_r = 7'h6f;
6'h02: char_addr_r = 7'h79;
6'h03: char_addr_r = 7'h20;
6'h04: char_addr_r = 7'h20;
6'h05: char_addr_r = 7'h20;
6'h06: char_addr_r = 7'h20;
6'h07: char_addr_r = 7'h20;
6'h08: char_addr_r = 7'h20;
6'h09: char_addr_r = 7'h20;
6'h0A: char_addr_r = 7'h20;
6'h0B: char_addr_r = 7'h20;
6'h0C: char_addr_r = 7'h20;
6'h0D: char_addr_r = 7'h20;
// visualization
// well
6'h0E: char_addr_r = 7'h20;
6'h0F: char_addr_r = 7'h20;
// row 2
6'h10: char_addr_r = 7'h67;
6'h11: char_addr_r = 7'h69;
6'h12: char_addr_r = 7'h72;
6'h13: char_addr_r = 7'h6c;
6'h14: char_addr_r = 7'h20;
6'h15: char_addr_r = 7'h20;
6'h16: char_addr_r = 7'h20;
6'h17: char_addr_r = 7'h20;
6'h18: char_addr_r = 7'h20;
6'h19: char_addr_r = 7'h20;
6'h1A: char_addr_r = 7'h20;
6'h1B: char_addr_r = 7'h20;
6'h1C: char_addr_r = 7'h20;
6'h1D: char_addr_r = 7'h20;
// visualization
// well
6'h1E: char_addr_r = 7'h20;
6'h1F: char_addr_r = 7'h20;
// row 3
6'h20: char_addr_r = 7'h63;
6'h21: char_addr_r = 7'h61;
6'h22: char_addr_r = 7'h74;
6'h23: char_addr_r = 7'h20;
6'h24: char_addr_r = 7'h20;
6'h25: char_addr_r = 7'h20;
6'h26: char_addr_r = 7'h20;
6'h27: char_addr_r = 7'h20;
6'h28: char_addr_r = 7'h20;
6'h29: char_addr_r = 7'h20;
6'h2A: char_addr_r = 7'h20;
6'h2B: char_addr_r = 7'h20;
6'h2C: char_addr_r = 7'h20;
6'h2D: char_addr_r = 7'h20;
// visualization
// well
6'h2E: char_addr_r = 7'h20;
6'h2F: char_addr_r = 7'h20;
// row 4
6'h30: char_addr_r = 7'h20;
6'h31: char_addr_r = 7'h20;
6'h32: char_addr_r = 7'h20;
6'h33: char_addr_r = 7'h20;
6'h34: char_addr_r = 7'h20;
6'h35: char_addr_r = 7'h20;
6'h36: char_addr_r = 7'h20;
6'h37: char_addr_r = 7'h20;
6'h38: char_addr_r = 7'h20;
6'h39: char_addr_r = 7'h20;
6'h3A: char_addr_r = 7'h20;
6'h3B: char_addr_r = 7'h20;
6'h3C: char_addr_r = 7'h20;
6'h3D: char_addr_r = 7'h20;
// well, this is very annoying, try consola?
6'h3E: char_addr_r = 7'h20;
6'h3F: char_addr_r = 7'h20;
endcase
//-------------------------------------------
// game over region
// - display "Game Over" at center
// - scale to 32-by-64 fonts
//-----------------------------------------
//-------------------------------------------
// mux for font ROM addresses and rgb
//-------------------------------------------
// you can adjust color here
always @*
begin
study_rgb = 3'b110; // background, yellow
if (word_on)
begin
char_addr = char_addr_r;
row_addr = row_addr_r;
bit_addr = bit_addr_r;
if (font_bit)
study_rgb = 3'b001;
end
end
assign study_on = word_on;
//-------------------------------------------
// font rom interface (well)
//-------------------------------------------
// just concatenation
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:44:24 03/10/2015
// Design Name:
// Module Name: Immediate_Extend
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// load :
// 0. 7:0 s
// 1. 3:0 s
// 2. 10:0 s
// 3. 2:0 t
// 4. 7:0 z
// 5. 4:0 s
// 6. 4:2 t
//////////////////////////////////////////////////////////////////////////////////
module Immediate_Extend(
output [15 : 0] data_out,
input [2 : 0] load,
input [15 : 0] data_in
);
assign data_out =
(load == 0) ? {{8{data_in[7]}}, data_in[7 : 0]} :
(load == 1) ? {{12{data_in[3]}}, data_in[3 : 0]} :
(load == 2) ? {{5{data_in[10]}}, data_in[10 : 0]} :
(load == 3) ? {12'b0, data_in[3 : 0]} :
(load == 4) ? {8'b0, data_in[7 : 0]} :
(load == 5) ? {{11{data_in[4]}}, data_in[4 : 0]} :
{13'b0, data_in[4 : 2]};
endmodule
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
`ifdef SMV
`include "ovl_ported/std_ovl_defines.h"
`else
`include "std_ovl_defines.h"
`endif
`module ovl_combo (clock, reset, enable, num_cks, start_event, test_expr, select, fire_comb);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter check_overlapping = 1;
parameter check_missing_start = 0;
parameter num_cks_max = 7;
parameter num_cks_width = 3;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [num_cks_width-1:0] num_cks;
input start_event, test_expr;
input [1:0] select;
output [`OVL_FIRE_WIDTH-1:0] fire_comb;
// Parameters that should not be edited
parameter assert_name = "OVL_COMBO";
`ifdef SMV
`include "ovl_ported/std_ovl_reset.h"
`include "ovl_ported/std_ovl_clock.h"
`include "ovl_ported/std_ovl_cover.h"
`include "ovl_ported/std_ovl_init.h"
`else
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`endif // !`ifdef SMV
`ifdef SMV
`include "./ovl_ported/vlog95/ovl_combo_logic.v"
`else
`include "./vlog95/ovl_combo_logic.v"
`endif
assign fire_comb = {2'b0, fire_2state_comb};
`endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Wed Jul 16 10:16:52 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.19 2003/07/09 07:52:44 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
'timescale 1ns / 1ns;
//
//
// Start of Generated Module rtl of ent_ac
//
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2,
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Tue Jul 22 11:18:49 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.21 2003/07/17 12:10:43 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps;
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2,
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Tue Aug 12 16:53:17 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.24 2003/08/11 07:16:25 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2,
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Mon Sep 8 17:52:50 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2,
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Wed Oct 8 09:51:06 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Wed Oct 8 10:24:03 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Mon Oct 13 09:32:34 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Thu Nov 6 15:57:35 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:09 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.17 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Fri Jul 15 12:55:13 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_ac.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
port_ac_2
);
// Generated Module Outputs:
output port_ac_2;
// Generated Wires:
wire port_ac_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_P_BLACKBOX_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dlatch$P (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_P_BLACKBOX_V
|
`timescale 1ns / 1ps
// This module is a third order delta/sigma modulator
// It uses no multiply only shifts by 1, 2 or 13
// There are only 7 adders used, it takes around 110 LUTs
module hq_dac
(
input reset,
input clk,
input clk_ena,
input [19:0] pcm_in,
output reg dac_out
);
// ======================================
// ============== Stage #1 ==============
// ======================================
wire [23:0] w_data_in_p0;
wire [23:0] w_data_err_p0;
wire [23:0] w_data_int_p0;
reg [23:0] r_data_fwd_p1;
// PCM input extended to 24 bits
assign w_data_in_p0 = { {4{pcm_in[19]}}, pcm_in };
// Error between the input and the quantizer output
assign w_data_err_p0 = w_data_in_p0 - w_data_qt_p2;
// First integrator adder
assign w_data_int_p0 = { {3{w_data_err_p0[23]}}, w_data_err_p0[22:2] } // Divide by 4
+ r_data_fwd_p1;
// First integrator forward delay
always @(posedge reset or posedge clk)
if (reset)
r_data_fwd_p1 <= 24'd0;
else if (clk_ena)
r_data_fwd_p1 <= w_data_int_p0;
// ======================================
// ============== Stage #2 ==============
// ======================================
wire [23:0] w_data_fb1_p1;
wire [23:0] w_data_fb2_p1;
wire [23:0] w_data_lpf_p1;
reg [23:0] r_data_lpf_p2;
// Feedback from the quantizer output
assign w_data_fb1_p1 = { {3{r_data_fwd_p1[23]}}, r_data_fwd_p1[22:2] } // Divide by 4
- { {3{w_data_qt_p2[23]}}, w_data_qt_p2[22:2] }; // Divide by 4
// Feedback from the third stage
assign w_data_fb2_p1 = w_data_fb1_p1
- { {14{r_data_fwd_p2[23]}}, r_data_fwd_p2[22:13] }; // Divide by 8192
// Low pass filter
assign w_data_lpf_p1 = w_data_fb2_p1 + r_data_lpf_p2;
// Low pass filter feedback delay
always @(posedge reset or posedge clk)
if (reset)
r_data_lpf_p2 <= 24'd0;
else if (clk_ena)
r_data_lpf_p2 <= w_data_lpf_p1;
// ======================================
// ============== Stage #3 ==============
// ======================================
wire [23:0] w_data_fb3_p1;
wire [23:0] w_data_int_p1;
reg [23:0] r_data_fwd_p2;
// Feedback from the quantizer output
assign w_data_fb3_p1 = { {2{w_data_lpf_p1[23]}}, w_data_lpf_p1[22:1] } // Divide by 2
- { {2{w_data_qt_p2[23]}}, w_data_qt_p2[22:1] }; // Divide by 2
// Second integrator adder
assign w_data_int_p1 = w_data_fb3_p1 + r_data_fwd_p2;
// Second integrator forward delay
always @(posedge reset or posedge clk)
if (reset)
r_data_fwd_p2 <= 24'd0;
else if (clk_ena)
r_data_fwd_p2 <= w_data_int_p1;
// =====================================
// ========== 1-bit quantizer ==========
// =====================================
wire [23:0] w_data_qt_p2;
assign w_data_qt_p2 = (r_data_fwd_p2[23]) ? 24'hF00000 : 24'h100000;
always @(posedge reset or posedge clk)
if (reset)
dac_out <= 1'b0;
else if (clk_ena)
dac_out <= ~r_data_fwd_p2[23];
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Set Implicit Arguments.
Require Export Notations.
Notation "A -> B" := (forall (_ : A), B) : type_scope.
(** * Propositional connectives *)
(** [True] is the always true proposition *)
Inductive True : Prop :=
I : True.
Register True as core.True.type.
Register I as core.True.I.
(** [False] is the always false proposition *)
Inductive False : Prop :=.
Register False as core.False.type.
(** [not A], written [~A], is the negation of [A] *)
Definition not (A:Prop) := A -> False.
Notation "~ x" := (not x) : type_scope.
Register not as core.not.type.
(** Create the "core" hint database, and set its transparent state for
variables and constants explicitely. *)
Create HintDb core.
Hint Variables Opaque : core.
Hint Constants Opaque : core.
Hint Unfold not: core.
(** [and A B], written [A /\ B], is the conjunction of [A] and [B]
[conj p q] is a proof of [A /\ B] as soon as
[p] is a proof of [A] and [q] a proof of [B]
[proj1] and [proj2] are first and second projections of a conjunction *)
Inductive and (A B:Prop) : Prop :=
conj : A -> B -> A /\ B
where "A /\ B" := (and A B) : type_scope.
Register and as core.and.type.
Register conj as core.and.conj.
Section Conjunction.
Variables A B : Prop.
Theorem proj1 : A /\ B -> A.
Proof.
destruct 1; trivial.
Qed.
Theorem proj2 : A /\ B -> B.
Proof.
destruct 1; trivial.
Qed.
End Conjunction.
(** [or A B], written [A \/ B], is the disjunction of [A] and [B] *)
Inductive or (A B:Prop) : Prop :=
| or_introl : A -> A \/ B
| or_intror : B -> A \/ B
where "A \/ B" := (or A B) : type_scope.
Arguments or_introl [A B] _, [A] B _.
Arguments or_intror [A B] _, A [B] _.
Register or as core.or.type.
(** [iff A B], written [A <-> B], expresses the equivalence of [A] and [B] *)
Definition iff (A B:Prop) := (A -> B) /\ (B -> A).
Notation "A <-> B" := (iff A B) : type_scope.
Register iff as core.iff.type.
Register proj1 as core.iff.proj1.
Register proj2 as core.iff.proj2.
Section Equivalence.
Theorem iff_refl : forall A:Prop, A <-> A.
Proof.
split; auto.
Qed.
Theorem iff_trans : forall A B C:Prop, (A <-> B) -> (B <-> C) -> (A <-> C).
Proof.
intros A B C [H1 H2] [H3 H4]; split; auto.
Qed.
Theorem iff_sym : forall A B:Prop, (A <-> B) -> (B <-> A).
Proof.
intros A B [H1 H2]; split; auto.
Qed.
End Equivalence.
Hint Unfold iff: extcore.
(** Backward direction of the equivalences above does not need assumptions *)
Theorem and_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A /\ B <-> A /\ C).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ assumption | ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem and_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B /\ A <-> C /\ A).
Proof.
intros ? ? ? [Hl Hr]; split; intros [? ?]; (split; [ | assumption ]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_l : forall A B C : Prop,
(B <-> C) -> (A \/ B <-> A \/ C).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left; assumption| right]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem or_iff_compat_r : forall A B C : Prop,
(B <-> C) -> (B \/ A <-> C \/ A).
Proof.
intros ? ? ? [Hl Hr]; split; (intros [?|?]; [left| right; assumption]);
[apply Hl | apply Hr]; assumption.
Qed.
Theorem imp_iff_compat_l : forall A B C : Prop,
(B <-> C) -> ((A -> B) <-> (A -> C)).
Proof.
intros ? ? ? [Hl Hr]; split; intros H ?; [apply Hl | apply Hr]; apply H; assumption.
Qed.
Theorem imp_iff_compat_r : forall A B C : Prop,
(B <-> C) -> ((B -> A) <-> (C -> A)).
Proof.
intros ? ? ? [Hl Hr]; split; intros H ?; [apply H, Hr | apply H, Hl]; assumption.
Qed.
Theorem not_iff_compat : forall A B : Prop,
(A <-> B) -> (~ A <-> ~B).
Proof.
intros; apply imp_iff_compat_r; assumption.
Qed.
(** Some equivalences *)
Theorem neg_false : forall A : Prop, ~ A <-> (A <-> False).
Proof.
intro A; unfold not; split.
- intro H; split; [exact H | intro H1; elim H1].
- intros [H _]; exact H.
Qed.
Theorem and_cancel_l : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((A /\ B <-> A /\ C) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_l]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [apply Hl | ]; assumption.
+ apply HypR; split; [apply Hr | ]; assumption.
Qed.
Theorem and_cancel_r : forall A B C : Prop,
(B -> A) -> (C -> A) -> ((B /\ A <-> C /\ A) <-> (B <-> C)).
Proof.
intros A B C Hl Hr.
split; [ | apply and_iff_compat_r]; intros [HypL HypR]; split; intros.
+ apply HypL; split; [ | apply Hl ]; assumption.
+ apply HypR; split; [ | apply Hr ]; assumption.
Qed.
Theorem and_comm : forall A B : Prop, A /\ B <-> B /\ A.
Proof.
intros; split; intros [? ?]; split; assumption.
Qed.
Theorem and_assoc : forall A B C : Prop, (A /\ B) /\ C <-> A /\ B /\ C.
Proof.
intros; split; [ intros [[? ?] ?]| intros [? [? ?]]]; repeat split; assumption.
Qed.
Theorem or_cancel_l : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((A \/ B <-> A \/ C) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_l]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ right | destruct Fl | ]; assumption. }
{ destruct Hr; [ right | destruct Fr | ]; assumption. }
Qed.
Theorem or_cancel_r : forall A B C : Prop,
(B -> ~ A) -> (C -> ~ A) -> ((B \/ A <-> C \/ A) <-> (B <-> C)).
Proof.
intros ? ? ? Fl Fr; split; [ | apply or_iff_compat_r]; intros [Hl Hr]; split; intros.
{ destruct Hl; [ left | | destruct Fl ]; assumption. }
{ destruct Hr; [ left | | destruct Fr ]; assumption. }
Qed.
Theorem or_comm : forall A B : Prop, (A \/ B) <-> (B \/ A).
Proof.
intros; split; (intros [? | ?]; [ right | left ]; assumption).
Qed.
Theorem or_assoc : forall A B C : Prop, (A \/ B) \/ C <-> A \/ B \/ C.
Proof.
intros; split; [ intros [[?|?]|?]| intros [?|[?|?]]].
+ left; assumption.
+ right; left; assumption.
+ right; right; assumption.
+ left; left; assumption.
+ left; right; assumption.
+ right; assumption.
Qed.
Lemma iff_and : forall A B : Prop, (A <-> B) -> (A -> B) /\ (B -> A).
Proof.
intros A B []; split; trivial.
Qed.
Lemma iff_to_and : forall A B : Prop, (A <-> B) <-> (A -> B) /\ (B -> A).
Proof.
intros; split; intros [Hl Hr]; (split; intros; [ apply Hl | apply Hr]); assumption.
Qed.
(** [(IF_then_else P Q R)], written [IF P then Q else R] denotes
either [P] and [Q], or [~P] and [R] *)
Definition IF_then_else (P Q R:Prop) := P /\ Q \/ ~ P /\ R.
Notation "'IF' c1 'then' c2 'else' c3" := (IF_then_else c1 c2 c3)
(at level 200, right associativity) : type_scope.
(** * First-order quantifiers *)
(** [ex P], or simply [exists x, P x], or also [exists x:A, P x],
expresses the existence of an [x] of some type [A] in [Set] which
satisfies the predicate [P]. This is existential quantification.
[ex2 P Q], or simply [exists2 x, P x & Q x], or also
[exists2 x:A, P x & Q x], expresses the existence of an [x] of
type [A] which satisfies both predicates [P] and [Q].
Universal quantification is primitively written [forall x:A, Q]. By
symmetry with existential quantification, the construction [all P]
is provided too.
*)
Inductive ex (A:Type) (P:A -> Prop) : Prop :=
ex_intro : forall x:A, P x -> ex (A:=A) P.
Register ex as core.ex.type.
Inductive ex2 (A:Type) (P Q:A -> Prop) : Prop :=
ex_intro2 : forall x:A, P x -> Q x -> ex2 (A:=A) P Q.
Definition all (A:Type) (P:A -> Prop) := forall x:A, P x.
(* Rule order is important to give printing priority to fully typed exists *)
Notation "'exists' x .. y , p" := (ex (fun x => .. (ex (fun y => p)) ..))
(at level 200, x binder, right associativity,
format "'[' 'exists' '/ ' x .. y , '/ ' p ']'")
: type_scope.
Notation "'exists2' x , p & q" := (ex2 (fun x => p) (fun x => q))
(at level 200, x ident, p at level 200, right associativity) : type_scope.
Notation "'exists2' x : A , p & q" := (ex2 (A:=A) (fun x => p) (fun x => q))
(at level 200, x ident, A at level 200, p at level 200, right associativity,
format "'[' 'exists2' '/ ' x : A , '/ ' '[' p & '/' q ']' ']'")
: type_scope.
Notation "'exists2' ' x , p & q" := (ex2 (fun x => p) (fun x => q))
(at level 200, x strict pattern, p at level 200, right associativity) : type_scope.
Notation "'exists2' ' x : A , p & q" := (ex2 (A:=A) (fun x => p) (fun x => q))
(at level 200, x strict pattern, A at level 200, p at level 200, right associativity,
format "'[' 'exists2' '/ ' ' x : A , '/ ' '[' p & '/' q ']' ']'")
: type_scope.
(** Derived rules for universal quantification *)
Section universal_quantification.
Variable A : Type.
Variable P : A -> Prop.
Theorem inst : forall x:A, all (fun x => P x) -> P x.
Proof.
unfold all; auto.
Qed.
Theorem gen : forall (B:Prop) (f:forall y:A, B -> P y), B -> all P.
Proof.
red; auto.
Qed.
End universal_quantification.
(** * Equality *)
(** [eq x y], or simply [x=y] expresses the equality of [x] and
[y]. Both [x] and [y] must belong to the same type [A].
The definition is inductive and states the reflexivity of the equality.
The others properties (symmetry, transitivity, replacement of
equals by equals) are proved below. The type of [x] and [y] can be
made explicit using the notation [x = y :> A]. This is Leibniz equality
as it expresses that [x] and [y] are equal iff every property on
[A] which is true of [x] is also true of [y] *)
Inductive eq (A:Type) (x:A) : A -> Prop :=
eq_refl : x = x :>A
where "x = y :> A" := (@eq A x y) : type_scope.
Notation "x = y" := (x = y :>_) : type_scope.
Notation "x <> y :> T" := (~ x = y :>T) : type_scope.
Notation "x <> y" := (x <> y :>_) : type_scope.
Arguments eq {A} x _.
Arguments eq_refl {A x} , [A] x.
Arguments eq_ind [A] x P _ y _.
Arguments eq_rec [A] x P _ y _.
Arguments eq_rect [A] x P _ y _.
Hint Resolve I conj or_introl or_intror : core.
Hint Resolve eq_refl: core.
Hint Resolve ex_intro ex_intro2: core.
Register eq as core.eq.type.
Register eq_refl as core.eq.refl.
Register eq_ind as core.eq.ind.
Register eq_rect as core.eq.rect.
Section Logic_lemmas.
Theorem absurd : forall A C:Prop, A -> ~ A -> C.
Proof.
unfold not; intros A C h1 h2.
destruct (h2 h1).
Qed.
Section equality.
Variables A B : Type.
Variable f : A -> B.
Variables x y z : A.
Theorem eq_sym : x = y -> y = x.
Proof.
destruct 1; trivial.
Defined.
Register eq_sym as core.eq.sym.
Theorem eq_trans : x = y -> y = z -> x = z.
Proof.
destruct 2; trivial.
Defined.
Register eq_trans as core.eq.trans.
Theorem eq_trans_r : x = y -> z = y -> x = z.
Proof.
destruct 2; trivial.
Defined.
Theorem f_equal : x = y -> f x = f y.
Proof.
destruct 1; trivial.
Defined.
Register f_equal as core.eq.congr.
Theorem not_eq_sym : x <> y -> y <> x.
Proof.
red; intros h1 h2; apply h1; destruct h2; trivial.
Qed.
End equality.
Definition eq_sind_r :
forall (A:Type) (x:A) (P:A -> SProp), P x -> forall y:A, y = x -> P y.
Proof.
intros A x P H y H0. elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_ind_r :
forall (A:Type) (x:A) (P:A -> Prop), P x -> forall y:A, y = x -> P y.
intros A x P H y H0. elim eq_sym with (1 := H0); assumption.
Defined.
Register eq_ind_r as core.eq.ind_r.
Definition eq_rec_r :
forall (A:Type) (x:A) (P:A -> Set), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
Definition eq_rect_r :
forall (A:Type) (x:A) (P:A -> Type), P x -> forall y:A, y = x -> P y.
intros A x P H y H0; elim eq_sym with (1 := H0); assumption.
Defined.
End Logic_lemmas.
Module EqNotations.
Notation "'rew' H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' H in '/' H' ']'").
Notation "'rew' [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10,
format "'[' 'rew' [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' <- H 'in' H'" := (eq_rect_r _ H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- H in '/' H' ']'").
Notation "'rew' <- [ P ] H 'in' H'" := (eq_rect_r P H' H)
(at level 10, H' at level 10,
format "'[' 'rew' <- [ P ] '/ ' H in '/' H' ']'").
Notation "'rew' -> H 'in' H'" := (eq_rect _ _ H' _ H)
(at level 10, H' at level 10, only parsing).
Notation "'rew' -> [ P ] H 'in' H'" := (eq_rect _ P H' _ H)
(at level 10, H' at level 10, only parsing).
End EqNotations.
Import EqNotations.
Section equality_dep.
Variable A : Type.
Variable B : A -> Type.
Variable f : forall x, B x.
Variables x y : A.
Theorem f_equal_dep : forall (H: x = y), rew H in f x = f y.
Proof.
destruct H; reflexivity.
Defined.
End equality_dep.
Section equality_dep2.
Variable A A' : Type.
Variable B : A -> Type.
Variable B' : A' -> Type.
Variable f : A -> A'.
Variable g : forall a:A, B a -> B' (f a).
Variables x y : A.
Lemma f_equal_dep2 : forall {A A' B B'} (f : A -> A') (g : forall a:A, B a -> B' (f a))
{x1 x2 : A} {y1 : B x1} {y2 : B x2} (H : x1 = x2),
rew H in y1 = y2 -> rew f_equal f H in g x1 y1 = g x2 y2.
Proof.
destruct H, 1. reflexivity.
Defined.
End equality_dep2.
Lemma rew_opp_r : forall A (P:A->Type) (x y:A) (H:x=y) (a:P y), rew H in rew <- H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Lemma rew_opp_l : forall A (P:A->Type) (x y:A) (H:x=y) (a:P x), rew <- H in rew H in a = a.
Proof.
intros.
destruct H.
reflexivity.
Defined.
Theorem f_equal2 :
forall (A1 A2 B:Type) (f:A1 -> A2 -> B) (x1 y1:A1)
(x2 y2:A2), x1 = y1 -> x2 = y2 -> f x1 x2 = f y1 y2.
Proof.
destruct 1; destruct 1; reflexivity.
Qed.
Register f_equal2 as core.eq.congr2.
Theorem f_equal3 :
forall (A1 A2 A3 B:Type) (f:A1 -> A2 -> A3 -> B) (x1 y1:A1)
(x2 y2:A2) (x3 y3:A3),
x1 = y1 -> x2 = y2 -> x3 = y3 -> f x1 x2 x3 = f y1 y2 y3.
Proof.
destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal4 :
forall (A1 A2 A3 A4 B:Type) (f:A1 -> A2 -> A3 -> A4 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4),
x1 = y1 -> x2 = y2 -> x3 = y3 -> x4 = y4 -> f x1 x2 x3 x4 = f y1 y2 y3 y4.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal5 :
forall (A1 A2 A3 A4 A5 B:Type) (f:A1 -> A2 -> A3 -> A4 -> A5 -> B)
(x1 y1:A1) (x2 y2:A2) (x3 y3:A3) (x4 y4:A4) (x5 y5:A5),
x1 = y1 ->
x2 = y2 ->
x3 = y3 -> x4 = y4 -> x5 = y5 -> f x1 x2 x3 x4 x5 = f y1 y2 y3 y4 y5.
Proof.
destruct 1; destruct 1; destruct 1; destruct 1; destruct 1; reflexivity.
Qed.
Theorem f_equal_compose : forall A B C (a b:A) (f:A->B) (g:B->C) (e:a=b),
f_equal g (f_equal f e) = f_equal (fun a => g (f a)) e.
Proof.
destruct e. reflexivity.
Defined.
(** The groupoid structure of equality *)
Theorem eq_trans_refl_l : forall A (x y:A) (e:x=y), eq_trans eq_refl e = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_trans_refl_r : forall A (x y:A) (e:x=y), eq_trans e eq_refl = e.
Proof.
destruct e. reflexivity.
Defined.
Theorem eq_sym_involutive : forall A (x y:A) (e:x=y), eq_sym (eq_sym e) = e.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_l : forall A (x y:A) (e:x=y), eq_trans (eq_sym e) e = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_sym_inv_r : forall A (x y:A) (e:x=y), eq_trans e (eq_sym e) = eq_refl.
Proof.
destruct e; reflexivity.
Defined.
Theorem eq_trans_assoc : forall A (x y z t:A) (e:x=y) (e':y=z) (e'':z=t),
eq_trans e (eq_trans e' e'') = eq_trans (eq_trans e e') e''.
Proof.
destruct e''; reflexivity.
Defined.
Theorem rew_map : forall A B (P:B->Type) (f:A->B) x1 x2 (H:x1=x2) (y:P (f x1)),
rew [fun x => P (f x)] H in y = rew f_equal f H in y.
Proof.
destruct H; reflexivity.
Defined.
Theorem eq_trans_map : forall {A B} {x1 x2 x3:A} {y1:B x1} {y2:B x2} {y3:B x3},
forall (H1:x1=x2) (H2:x2=x3) (H1': rew H1 in y1 = y2) (H2': rew H2 in y2 = y3),
rew eq_trans H1 H2 in y1 = y3.
Proof.
intros. destruct H2. exact (eq_trans H1' H2').
Defined.
Lemma map_subst : forall {A} {P Q:A->Type} (f : forall x, P x -> Q x) {x y} (H:x=y) (z:P x),
rew H in f x z = f y (rew H in z).
Proof.
destruct H. reflexivity.
Defined.
Lemma map_subst_map : forall {A B} {P:A->Type} {Q:B->Type} (f:A->B) (g : forall x, P x -> Q (f x)),
forall {x y} (H:x=y) (z:P x), rew f_equal f H in g x z = g y (rew H in z).
Proof.
destruct H. reflexivity.
Defined.
Lemma rew_swap : forall A (P:A->Type) x1 x2 (H:x1=x2) (y1:P x1) (y2:P x2), rew H in y1 = y2 -> y1 = rew <- H in y2.
Proof.
destruct H. trivial.
Defined.
Lemma rew_compose : forall A (P:A->Type) x1 x2 x3 (H1:x1=x2) (H2:x2=x3) (y:P x1),
rew H2 in rew H1 in y = rew (eq_trans H1 H2) in y.
Proof.
destruct H2. reflexivity.
Defined.
(** Extra properties of equality *)
Theorem eq_id_comm_l : forall A (f:A->A) (Hf:forall a, a = f a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf a)).
destruct (Hf a) at 1 2.
destruct (Hf a).
reflexivity.
Defined.
Theorem eq_id_comm_r : forall A (f:A->A) (Hf:forall a, f a = a), forall a, f_equal f (Hf a) = Hf (f a).
Proof.
intros.
unfold f_equal.
rewrite <- (eq_trans_sym_inv_l (Hf (f (f a)))).
set (Hfsymf := fun a => eq_sym (Hf a)).
change (eq_sym (Hf (f (f a)))) with (Hfsymf (f (f a))).
pattern (Hfsymf (f (f a))).
destruct (eq_id_comm_l f Hfsymf (f a)).
destruct (eq_id_comm_l f Hfsymf a).
unfold Hfsymf.
destruct (Hf a). simpl.
rewrite eq_trans_refl_l.
reflexivity.
Defined.
Lemma eq_refl_map_distr : forall A B x (f:A->B), f_equal f (eq_refl x) = eq_refl (f x).
Proof.
reflexivity.
Qed.
Lemma eq_trans_map_distr : forall A B x y z (f:A->B) (e:x=y) (e':y=z), f_equal f (eq_trans e e') = eq_trans (f_equal f e) (f_equal f e').
Proof.
destruct e'.
reflexivity.
Defined.
Lemma eq_sym_map_distr : forall A B (x y:A) (f:A->B) (e:x=y), eq_sym (f_equal f e) = f_equal f (eq_sym e).
Proof.
destruct e.
reflexivity.
Defined.
Lemma eq_trans_sym_distr : forall A (x y z:A) (e:x=y) (e':y=z), eq_sym (eq_trans e e') = eq_trans (eq_sym e') (eq_sym e).
Proof.
destruct e, e'.
reflexivity.
Defined.
Lemma eq_trans_rew_distr : forall A (P:A -> Type) (x y z:A) (e:x=y) (e':y=z) (k:P x),
rew (eq_trans e e') in k = rew e' in rew e in k.
Proof.
destruct e, e'; reflexivity.
Qed.
Lemma rew_const : forall A P (x y:A) (e:x=y) (k:P),
rew [fun _ => P] e in k = k.
Proof.
destruct e; reflexivity.
Qed.
(* Aliases *)
Notation sym_eq := eq_sym (only parsing).
Notation trans_eq := eq_trans (only parsing).
Notation sym_not_eq := not_eq_sym (only parsing).
Notation refl_equal := eq_refl (only parsing).
Notation sym_equal := eq_sym (only parsing).
Notation trans_equal := eq_trans (only parsing).
Notation sym_not_equal := not_eq_sym (only parsing).
Hint Immediate eq_sym not_eq_sym: core.
(** Basic definitions about relations and properties *)
Definition subrelation (A B : Type) (R R' : A->B->Prop) :=
forall x y, R x y -> R' x y.
Definition unique (A : Type) (P : A->Prop) (x:A) :=
P x /\ forall (x':A), P x' -> x=x'.
Definition uniqueness (A:Type) (P:A->Prop) := forall x y, P x -> P y -> x = y.
(** Unique existence *)
Notation "'exists' ! x .. y , p" :=
(ex (unique (fun x => .. (ex (unique (fun y => p))) ..)))
(at level 200, x binder, right associativity,
format "'[' 'exists' ! '/ ' x .. y , '/ ' p ']'")
: type_scope.
Lemma unique_existence : forall (A:Type) (P:A->Prop),
((exists x, P x) /\ uniqueness P) <-> (exists! x, P x).
Proof.
intros A P; split.
- intros ((x,Hx),Huni); exists x; red; auto.
- intros (x,(Hx,Huni)); split.
+ exists x; assumption.
+ intros x' x'' Hx' Hx''; transitivity x.
* symmetry; auto.
* auto.
Qed.
Lemma forall_exists_unique_domain_coincide :
forall A (P:A->Prop), (exists! x, P x) ->
forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x).
Proof.
intros A P (x & Hp & Huniq); split.
- intro; exists x; auto.
- intros (x0 & HPx0 & HQx0) x1 HPx1.
assert (H : x0 = x1) by (transitivity x; [symmetry|]; auto).
destruct H.
assumption.
Qed.
Lemma forall_exists_coincide_unique_domain :
forall A (P:A->Prop),
(forall Q:A->Prop, (forall x, P x -> Q x) <-> (exists x, P x /\ Q x))
-> (exists! x, P x).
Proof.
intros A P H.
destruct H with (Q:=P) as ((x & Hx & _),_); [trivial|].
exists x. split; [trivial|].
destruct H with (Q:=fun x'=>x=x') as (_,Huniq).
apply Huniq. exists x; auto.
Qed.
(** * Being inhabited *)
(** The predicate [inhabited] can be used in different contexts. If [A] is
thought as a type, [inhabited A] states that [A] is inhabited. If [A] is
thought as a computationally relevant proposition, then
[inhabited A] weakens [A] so as to hide its computational meaning.
The so-weakened proof remains computationally relevant but only in
a propositional context.
*)
Inductive inhabited (A:Type) : Prop := inhabits : A -> inhabited A.
Hint Resolve inhabits: core.
Lemma exists_inhabited : forall (A:Type) (P:A->Prop),
(exists x, P x) -> inhabited A.
Proof.
destruct 1; auto.
Qed.
Lemma inhabited_covariant (A B : Type) : (A -> B) -> inhabited A -> inhabited B.
Proof.
intros f [x];exact (inhabits (f x)).
Qed.
(** Declaration of stepl and stepr for eq and iff *)
Lemma eq_stepl : forall (A : Type) (x y z : A), x = y -> x = z -> z = y.
Proof.
intros A x y z H1 H2. rewrite <- H2; exact H1.
Qed.
Declare Left Step eq_stepl.
Declare Right Step eq_trans.
Lemma iff_stepl : forall A B C : Prop, (A <-> B) -> (A <-> C) -> (C <-> B).
Proof.
intros ? ? ? [? ?] [? ?]; split; intros; auto.
Qed.
Declare Left Step iff_stepl.
Declare Right Step iff_trans.
Local Notation "'rew' 'dependent' H 'in' H'"
:= (match H with
| eq_refl => H'
end)
(at level 10, H' at level 10,
format "'[' 'rew' 'dependent' '/ ' H in '/' H' ']'").
(** Equality for [ex] *)
Section ex.
Local Unset Implicit Arguments.
Definition eq_ex_uncurried {A : Type} (P : A -> Prop) {u1 v1 : A} {u2 : P u1} {v2 : P v1}
(pq : exists p : u1 = v1, rew p in u2 = v2)
: ex_intro P u1 u2 = ex_intro P v1 v2.
Proof.
destruct pq as [p q].
destruct q; simpl in *.
destruct p; reflexivity.
Qed.
Definition eq_ex {A : Type} {P : A -> Prop} (u1 v1 : A) (u2 : P u1) (v2 : P v1)
(p : u1 = v1) (q : rew p in u2 = v2)
: ex_intro P u1 u2 = ex_intro P v1 v2
:= eq_ex_uncurried P (ex_intro _ p q).
Definition eq_ex_hprop {A} {P : A -> Prop} (P_hprop : forall (x : A) (p q : P x), p = q)
(u1 v1 : A) (u2 : P u1) (v2 : P v1)
(p : u1 = v1)
: ex_intro P u1 u2 = ex_intro P v1 v2
:= eq_ex u1 v1 u2 v2 p (P_hprop _ _ _).
Lemma rew_ex {A x} {P : A -> Type} (Q : forall a, P a -> Prop) (u : exists p, Q x p) {y} (H : x = y)
: rew [fun a => exists p, Q a p] H in u
= match u with
| ex_intro _ u1 u2
=> ex_intro
(Q y)
(rew H in u1)
(rew dependent H in u2)
end.
Proof.
destruct H, u; reflexivity.
Qed.
End ex.
(** Equality for [ex2] *)
Section ex2.
Local Unset Implicit Arguments.
Definition eq_ex2_uncurried {A : Type} (P Q : A -> Prop) {u1 v1 : A}
{u2 : P u1} {v2 : P v1}
{u3 : Q u1} {v3 : Q v1}
(pq : exists2 p : u1 = v1, rew p in u2 = v2 & rew p in u3 = v3)
: ex_intro2 P Q u1 u2 u3 = ex_intro2 P Q v1 v2 v3.
Proof.
destruct pq as [p q r].
destruct r, q, p; simpl in *.
reflexivity.
Qed.
Definition eq_ex2 {A : Type} {P Q : A -> Prop}
(u1 v1 : A)
(u2 : P u1) (v2 : P v1)
(u3 : Q u1) (v3 : Q v1)
(p : u1 = v1) (q : rew p in u2 = v2) (r : rew p in u3 = v3)
: ex_intro2 P Q u1 u2 u3 = ex_intro2 P Q v1 v2 v3
:= eq_ex2_uncurried P Q (ex_intro2 _ _ p q r).
Definition eq_ex2_hprop {A} {P Q : A -> Prop}
(P_hprop : forall (x : A) (p q : P x), p = q)
(Q_hprop : forall (x : A) (p q : Q x), p = q)
(u1 v1 : A) (u2 : P u1) (v2 : P v1) (u3 : Q u1) (v3 : Q v1)
(p : u1 = v1)
: ex_intro2 P Q u1 u2 u3 = ex_intro2 P Q v1 v2 v3
:= eq_ex2 u1 v1 u2 v2 u3 v3 p (P_hprop _ _ _) (Q_hprop _ _ _).
Lemma rew_ex2 {A x} {P : A -> Type}
(Q : forall a, P a -> Prop)
(R : forall a, P a -> Prop)
(u : exists2 p, Q x p & R x p) {y} (H : x = y)
: rew [fun a => exists2 p, Q a p & R a p] H in u
= match u with
| ex_intro2 _ _ u1 u2 u3
=> ex_intro2
(Q y)
(R y)
(rew H in u1)
(rew dependent H in u2)
(rew dependent H in u3)
end.
Proof.
destruct H, u; reflexivity.
Qed.
End ex2.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFXBP_PP_BLACKBOX_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_PP_BLACKBOX_V
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 17
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "gcd_zynq_snick_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "gcd_zynq_snick_auto_pc_0,axi_protocol_converter_v2_1_17_axi_protocol_converter,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=17,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI\
_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gcd_zynq_snick_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 49999947, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, NUM_READ_THR\
EADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 49999947, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, NUM_READ_T\
HREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_17_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__FAHCON_PP_BLACKBOX_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_PP_BLACKBOX_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:ovld_reg:1.0
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_get_0_val_r_0 (
data_in,
vld_in,
ap_done,
clk,
data_out,
vld_out
);
input wire [31 : 0] data_in;
input wire vld_in;
(* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done" *)
input wire ap_done;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
output wire [31 : 0] data_out;
output wire vld_out;
ovld_reg #(
.DATA_WIDTH(32)
) inst (
.data_in(data_in),
.vld_in(vld_in),
.ap_done(ap_done),
.clk(clk),
.data_out(data_out),
.vld_out(vld_out)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__TAP_BEHAVIORAL_PP_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_BEHAVIORAL_PP_V
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_softusb();
reg sys_clk;
reg sys_rst;
reg usb_clk;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
/* 50MHz USB clock (should be 48) */
initial usb_clk = 1'b0;
always #10 usb_clk = ~usb_clk;
wire usba_vp;
wire usba_vm;
softusb dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.usb_clk(usb_clk),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_do(csr_do),
.csr_di(csr_di),
.irq(irq),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_sel_i(4'hf),
.wb_ack_o(wb_ack_o),
.usba_spd(),
.usba_oe_n(),
.usba_rcv(usba_vp),
.usba_vp(usba_vp),
.usba_vm(usba_vm),
.usbb_spd(),
.usbb_oe_n(),
.usbb_rcv(),
.usbb_vp(),
.usbb_vm()
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("CSR write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("CSR read : %x=%x", address, csr_do);
end
endtask
always begin
$dumpfile("softusb.vcd");
$dumpvars(0, dut);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
wb_adr_i = 32'd0;
wb_dat_i = 32'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
csrwrite(32'h00, 32'h00);
#7000;
wbread(32'h00020000);
wbread(32'h00020004);
$finish;
end
/* transmitter */
reg usb_clk_tx;
initial usb_clk_tx = 1'b0;
always #10 usb_clk_tx = ~usb_clk_tx;
reg usb_rst_tx;
reg [7:0] tx_data;
reg tx_valid;
wire txp;
wire txm;
wire txoe;
softusb_tx tx(
.usb_clk(usb_clk_tx),
.usb_rst(usb_rst_tx),
.tx_data(tx_data),
.tx_valid(tx_valid),
.tx_ready(),
.txp(txp),
.txm(txm),
.txoe(txoe),
.low_speed(1'b0),
.generate_eop(1'b0)
);
pullup(usba_vp);
pulldown(usba_vm);
assign usba_vp = txoe ? txp : 1'bz;
assign usba_vm = txoe ? txm : 1'bz;
initial begin
$dumpvars(0, tx);
usb_rst_tx = 1'b1;
tx_valid = 1'b0;
#20;
usb_rst_tx = 1'b0;
#4000;
tx_data = 8'h80;
tx_valid = 1'b1;
#400;
tx_data = 8'h56;
#400;
tx_valid = 1'b0;
end
endmodule
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 503 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 (1008-1)
module pairing(clk, reset, sel, addr, w, update, ready, i, o, done);
input clk;
input reset; // for the arithmethic core
input sel;
input [5:0] addr;
input w;
input update; // update reg_in & reg_out
input ready; // shift reg_in & reg_out
input i;
output o;
output done;
reg [`WIDTH_D0:0] reg_in, reg_out;
wire [`WIDTH_D0:0] out;
assign o = reg_out[0];
tiny
tiny0 (clk, reset, sel, addr, w, reg_in, out, done);
always @ (posedge clk) // write LSB firstly
if (update) reg_in <= 0;
else if (ready) reg_in <= {i,reg_in[`WIDTH_D0:1]};
always @ (posedge clk) // read LSB firstly
if (update) reg_out <= out;
else if (ready) reg_out <= reg_out>>1;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: VGAclocker.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.0 Build 156 04/24/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module VGAclocker (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 125,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 63,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=VGAclocker",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.200001"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.20000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "VGAclocker.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "125"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAclocker.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAclocker.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAclocker.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAclocker.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAclocker.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAclocker_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGAclocker_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's ALU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// ALU ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_alu.v,v $
// Revision 1.15 2005/01/07 09:23:39 andreje
// l.ff1 and l.cmov instructions added
//
// Revision 1.14 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.13 2004/05/09 19:49:03 lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.12 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.11 2003/04/24 00:16:07 lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.10 2002/09/08 05:52:16 lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.9 2002/09/07 19:16:10 lampret
// If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].
//
// Revision 1.8 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.7 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.6 2002/03/29 16:40:10 lampret
// Added a directive to ignore signed division variables that are only used in simulation.
//
// Revision 1.5 2002/03/29 16:33:59 lampret
// Added again just recently removed full_case directive
//
// Revision 1.4 2002/03/29 15:16:53 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/01/28 01:15:59 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/19 23:28:45 lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_alu(
a, b, mult_mac_result, macrc_op,
alu_op, shrot_op, comp_op,
cust5_op, cust5_limm,
result, flagforw, flag_we,
cyforw, cy_we, carry, flag
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
input [width-1:0] a;
input [width-1:0] b;
input [width-1:0] mult_mac_result;
input macrc_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
input [4:0] cust5_op;
input [5:0] cust5_limm;
output [width-1:0] result;
output flagforw;
output flag_we;
output cyforw;
output cy_we;
input carry;
input flag;
//
// Internal wires and regs
//
reg [width-1:0] result;
reg [width-1:0] shifted_rotated;
reg [width-1:0] result_cust5;
reg flagforw;
reg flagcomp;
reg flag_we;
reg cy_we;
wire [width-1:0] comp_a;
wire [width-1:0] comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire a_eq_b;
wire a_lt_b;
`endif
wire [width-1:0] result_sum;
`ifdef OR1200_IMPL_ADDC
wire [width-1:0] result_csum;
wire cy_csum;
`endif
wire [width-1:0] result_and;
wire cy_sum;
reg cyforw;
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
assign {cy_sum, result_sum} = a + b;
`ifdef OR1200_IMPL_ADDC
assign {cy_csum, result_csum} = a + b + {32'd0, carry};
`endif
assign result_and = a & b;
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
if (result === 32'bx)
$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
//
// Central part of the ALU
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
`ifdef OR1200_CASE_DEFAULT
casex (alu_op) // synopsys parallel_case
`else
casex (alu_op) // synopsys full_case parallel_case
`endif
`OR1200_ALUOP_FF1: begin
result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
end
`OR1200_ALUOP_CUST5 : begin
result = result_cust5;
end
`OR1200_ALUOP_SHROT : begin
result = shifted_rotated;
end
`OR1200_ALUOP_ADD : begin
result = result_sum;
end
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC : begin
result = result_csum;
end
`endif
`OR1200_ALUOP_SUB : begin
result = a - b;
end
`OR1200_ALUOP_XOR : begin
result = a ^ b;
end
`OR1200_ALUOP_OR : begin
result = a | b;
end
`OR1200_ALUOP_IMM : begin
result = b;
end
`OR1200_ALUOP_MOVHI : begin
if (macrc_op) begin
result = mult_mac_result;
end
else begin
result = b << 16;
end
end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_IMPL_DIV
`OR1200_ALUOP_DIV,
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL : begin
result = mult_mac_result;
end
`endif
`OR1200_ALUOP_CMOV: begin
result = flag ? a : b;
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND:
begin
`endif
result=result_and;
end
endcase
end
//
// l.cust5 custom instructions
//
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
casex (cust5_op) // synopsys parallel_case
5'h1 : begin
casex (cust5_limm[1:0])
2'h0: result_cust5 = {a[31:8], b[7:0]};
2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
2'h3: result_cust5 = {b[7:0], a[23:0]};
endcase
end
5'h2 :
result_cust5 = a | (1 << cust5_limm);
5'h3 :
result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
default: begin
result_cust5 = a;
end
endcase
end
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp) begin
casex (alu_op) // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`OR1200_ALUOP_ADD : begin
flagforw = (result_sum == 32'h0000_0000);
flag_we = 1'b1;
end
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC : begin
flagforw = (result_csum == 32'h0000_0000);
flag_we = 1'b1;
end
`endif
`OR1200_ALUOP_AND: begin
flagforw = (result_and == 32'h0000_0000);
flag_we = 1'b1;
end
`endif
`OR1200_ALUOP_COMP: begin
flagforw = flagcomp;
flag_we = 1'b1;
end
default: begin
flagforw = 1'b0;
flag_we = 1'b0;
end
endcase
end
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_ADDC
or cy_csum
`endif
) begin
casex (alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`OR1200_ALUOP_ADD : begin
cyforw = cy_sum;
cy_we = 1'b1;
end
`ifdef OR1200_IMPL_ADDC
`OR1200_ALUOP_ADDC: begin
cyforw = cy_csum;
cy_we = 1'b1;
end
`endif
`endif
default: begin
cyforw = 1'b0;
cy_we = 1'b0;
end
endcase
end
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
case (shrot_op) // synopsys parallel_case
`OR1200_SHROTOP_SLL :
shifted_rotated = (a << b[4:0]);
`OR1200_SHROTOP_SRL :
shifted_rotated = (a >> b[4:0]);
`ifdef OR1200_IMPL_ALU_ROTATE
`OR1200_SHROTOP_ROR :
shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
default:
shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
endcase
end
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = a_eq_b;
`OR1200_COP_SFNE:
flagcomp = ~a_eq_b;
`OR1200_COP_SFGT:
flagcomp = ~(a_eq_b | a_lt_b);
`OR1200_COP_SFGE:
flagcomp = ~a_lt_b;
`OR1200_COP_SFLT:
flagcomp = a_lt_b;
`OR1200_COP_SFLE:
flagcomp = a_eq_b | a_lt_b;
default:
flagcomp = 1'b0;
endcase
end
`endif
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = (comp_a == comp_b);
`OR1200_COP_SFNE:
flagcomp = (comp_a != comp_b);
`OR1200_COP_SFGT:
flagcomp = (comp_a > comp_b);
`OR1200_COP_SFGE:
flagcomp = (comp_a >= comp_b);
`OR1200_COP_SFLT:
flagcomp = (comp_a < comp_b);
`OR1200_COP_SFLE:
flagcomp = (comp_a <= comp_b);
default:
flagcomp = 1'b0;
endcase
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O41AI_PP_SYMBOL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o41ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Setup State Machine
// File : des_state.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module des_state
(
input se_clk,
input se_rstn,
input go_sup,
input line_3d_actv_15,
input ns1_eqz,
input ns2_eqz,
input co_linear,
input det_eqz,
input cull,
output reg sup_done,
output reg abort_cmd,
output reg [5:0] se_cstate
);
`include "define_3d.h"
reg go_sup_1;
reg go_sup_2;
/*******************Setup Engine Program Counter *******************/
always @ (posedge se_clk or negedge se_rstn) begin
if (!se_rstn) begin
se_cstate <= 6'b000000;
sup_done <= 1'b0;
abort_cmd <= 1'b0;
go_sup_1 <= 1'b0;
go_sup_2 <= 1'b0;
end
else begin
go_sup_2 <= go_sup_1;
go_sup_1 <= go_sup;
abort_cmd <= 1'b0;
if((se_cstate == 6'b000000) & go_sup_2) se_cstate <= 6'b000001;
else if((se_cstate == `COLIN_STATE) & co_linear & ~line_3d_actv_15) begin
abort_cmd <= 1'b1;
se_cstate <= 6'b000000;
end
else if((se_cstate == `NL1_NL2_STATE) & (ns1_eqz & ns2_eqz & ~line_3d_actv_15)) begin
abort_cmd <= 1'b1;
se_cstate <= 6'b000000;
end
else if((se_cstate == `NO_AREA_STATE) & ((cull | det_eqz) & ~line_3d_actv_15)) begin
abort_cmd <= 1'b1;
se_cstate <= 6'b000000;
end
else if(se_cstate == 6'b000000) se_cstate <= 6'b000000;
else if((se_cstate == `SETUP_END)) se_cstate <= 6'b000000;
else se_cstate <= se_cstate + 6'b000001;
sup_done <= (se_cstate == `SETUP_END);
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_stdatarep.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_stdatarep(/*AUTOARG*/
// Outputs
rep_store_data_c2, sctag_scdata_stdecc_c2,
// Inputs
arbdp_store_data_c2
);
// The left has 78 M3 pins.
// This control block needs to be 300-350U tall and ~50-60U wide.
input [77:0] arbdp_store_data_c2; // LEft
output [77:0] rep_store_data_c2; // Top
output [77:0] sctag_scdata_stdecc_c2; // Right
// 78 data bits.
assign sctag_scdata_stdecc_c2 = arbdp_store_data_c2 ;
assign rep_store_data_c2 = arbdp_store_data_c2 ;
endmodule
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module Multiplexer4(
i_data0,
i_data1,
i_data2,
i_data3,
i_select0,
i_select1,
i_select2,
i_select3,
o_data,
o_error);
parameter width = 1;
input [width - 1:0] i_data0;
input [width - 1:0] i_data1;
input [width - 1:0] i_data2;
input [width - 1:0] i_data3;
input i_select0;
input i_select1;
input i_select2;
input i_select3;
output [width - 1:0] o_data;
output o_error;
wire [ 2:0] w_sum;
assign o_data = i_select0 ? i_data0 :
i_select1 ? i_data1 :
i_select2 ? i_data2 :
i_select3 ? i_data3 : 0;
assign w_sum = i_select0 + i_select1 + i_select2 + i_select3;
assign o_error = w_sum[2] | w_sum[1] | (w_sum == 3'h0);
endmodule // Multiplexer4
|
/*
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: David McCoy
* Description: Card Controller for device side of SDIO
* This layer is above the PHY, it expects that data will arrive as data
* values instead of a stream of bits
* This behaves as a register map and controls data transfers
*
* SPI MODE IS NOT SUPORTED YET, SO IF CS_N IS LOW DO NOT REPSOND!
*
* Changes:
* 2015.08.09: Inital Commit
* 2015.08.13: Changed name to card controller
*/
/* TODO:
* - How to implement busy??
*/
module sdio_card_control #(
parameter NUM_FUNCS = 1, /* Number of SDIO Functions available */
parameter MEM_PRESENT = 0, /* Not supported yet */
parameter UHSII_AVAILABLE = 0, /* UHS Mode Not available yet */
parameter IO_OCR = 24'hFFF0, /* Operating condition mode (voltage range) */
parameter BUFFER_DEPTH = 8, /* 256 byte depth buffer */
parameter EN_8BIT_BUS = 0 /* Enable 8-bit bus */
)(
input sdio_clk,
input rst,
//Function Interface
output reg o_func_stb,
output reg o_func_inc_addr,
output reg o_func_block_mode,
output reg o_func_num,
output reg o_func_write_flag, /* Read = 0, Write = 1 */
output reg o_func_read_after_write,
output reg [17:0] o_func_reg_addr,
output reg [7:0] o_func_reg_write_data,
input [7:0] o_func_reg_read_data,
output o_func_data_rdy,
output reg [15:0] o_func_data_count;
output reg tunning_block,
//Function Interface From CIA
output [7:0] o_func_enable,
input [7:0] i_func_ready,
output [7:0] o_func_int_enable,
input [7:0] i_func_int_pending,
input [7:0] i_func_ready_for_data,
output [2:0] o_func_abort_stb,
output [3:0] o_func_select,
input [7:0] i_func_exec_status,
output o_soft_reset,
output o_en_card_detect_n,
output o_en_4bit_block_int,
input i_func_active,
output o_bus_release_req_stb,
output [15:0] o_max_f0_block_size,
output o_1_bit_mode,
output o_4_bit_mode,
output o_8_bit_mode,
output o_sdr_12,
output o_sdr_25,
output o_sdr_50,
output o_ddr_50,
output o_sdr_104,
output o_driver_type_a,
output o_driver_type_b,
output o_driver_type_c,
output o_driver_type_d,
output o_enable_async_interrupt
//PHY Interface
input i_cmd_stb,
input i_cmd_crc_good_stb,
input [5:0] i_cmd,
input [31:0] i_cmd_arg,
input i_cmd_phy_idle,
input i_chip_select_n,
output [135:0] o_rsps,
output [7:0] o_rsps_len,
output reg o_rsps_stb,
//PHY Data Interface
input i_phy_data_ready,
input i_phy_data_data_stb,
input [7:0] i_phy_data_data_in,
output o_phy_data_ready,
output [7:0] o_phy_data_data_out,
output o_phy_data_data_stb,
output o_phy_data_finished
);
//local parameters
localparam NORMAL_RESPONSE = 1'b0;
localparam EXTENDED_RESPONSE = 1'b1;
localparam RESET = 4'h0;
localparam INITIALIZE = 4'h1;
localparam STANDBY = 4'h2;
localparam COMMAND = 4'h3;
localparam TRANSFER = 4'h4;
localparam INACTIVE = 4'h5;
localparam R1 = 4'h0;
localparam R4 = 4'h1;
localparam R5 = 4'h2;
localparam R6 = 4'h3;
localparam R7 = 4'h4;
//registes/wires
reg [3:0] state;
reg [47:0] response_value;
reg [136:0] response_value_extended;
reg response_type;
reg [15:0] register_card_address; /* Host can set this so later it can be used to identify this card */
reg [3:0] voltage_select;
reg v1p8_sel;
reg [23:0] vio_ocr;
reg busy;
reg bad_crc;
reg cmd_arg_out_of_range;
reg illegal_command;
reg card_error;
reg [3:0] response_index;
wire [1:0] r5_cmd;
wire [15:0] max_f0_block_size;
wire enable_async_interrupt;
wire data_txrx_in_progress_flag,
reg [3:0] component_select;
/*
* Needed
*
* OCR (32 bit) CMD5 (SD_CMD_SEND_OP_CMD) ****
* X CID (128 bit) CMD10 (SD_CMD_SEND_CID) NOT SUPPORTED ON SDIO ONLY
* X CSD (128 bit) CMD9 (SD_CMD_SEND_CSD) NOT SUPPORTED ON SDIO ONLY
* RCA (16 bit) ???
* X DSR (16 bit optional) NOT SUPPORTED ON SDIO ONLY
* X SCR (64 bit) NOT SUPPORTED ON SDIO ONLY
* X SD_CARD_STATUS (512 bit) NOT SUPPORED ON SDIO ONLY
* CCCR
*/
//Function to Controller
wire [7:0] fc_ready; //(Bitmask) Function is ready to receive data
//Controller to Function
wire [7:0] fc_activate; //(Bitmask) Activate a function transaction
wire cf_ready; //Controller is ready to receive data
wire cf_write_flag; //This is a write transaction
wire cf_inc_addr_flag; //Increment the Address
wire [17:0] cf_address; //Offset Removed, this will enable modular function
wire cia_activate;
//submodules
sdio_cia #(
.BUFFER_DEPTH (BUFFER_DEPTH ),
.EN_8BIT_BUS (EN_8BIT_BUS )
) cccr (
.sdio_clk (sdio_clk ),
.rst (rst ),
//CIA Function
.i_activate (cia_activate ),
.i_write_flag (o_func_write_flag ),
.i_address (o_func_reg_addr ),
.i_inc_addr (o_func_inc_addr ),
.i_data_count (o_func_data_count ),
//SDIO Data Interface
.i_ready (i_phy_data_ready ),
.i_data_stb (i_phy_data_data_stb ),
.i_data_in (i_phy_data_data_in ),
.o_ready (o_phy_data_ready ),
.o_data_out (o_phy_data_data_out ),
.o_data_stb (o_phy_data_data_stb ),
.o_finished (o_phy_data_finished ),
//Function Configuration Interface
.o_func_enable (o_func_enable ),
.i_func_ready (i_func_ready ),
.o_func_int_enable (o_func_int_enable ),
.i_func_int_pending (i_func_int_pending ),
.i_func_ready_for_data (i_func_ready_for_data ),
.o_func_abort_stb (o_func_abort_stb ),
.o_func_select (o_func_select ),
.i_func_exec_status (i_func_exec_status ),
//SDCard Configuration Interface
.o_en_card_detect_n (o_en_card_detect_n ),
.o_en_4bit_block_int (o_en_4bit_block_int ),
.i_func_active (i_func_active ),
.o_bus_release_req_stb (o_bus_release_req_stb ),
.o_soft_reset (o_soft_reset ),
.i_data_txrx_in_progress_flag(data_txrx_in_progress_flag ),
.o_max_f0_block_size (max_f0_block_size ),
.o_1_bit_mode (o_1_bit_mode ),
.o_4_bit_mode (o_4_bit_mode ),
.o_8_bit_mode (o_8_bit_mode ),
.o_sdr_12 (o_sdr_12 ),
.o_sdr_25 (o_sdr_25 ),
.o_sdr_50 (o_sdr_50 ),
.o_ddr_50 (o_ddr_50 ),
.o_sdr_104 (o_sdr_104 ),
.o_driver_type_a (o_driver_type_a ),
.o_driver_type_b (o_driver_type_b ),
.o_driver_type_c (o_driver_type_c ),
.o_driver_type_d (o_driver_type_d ),
.o_enable_async_interrupt (enable_async_interrupt )
);
//asynchronous logic
assign o_rsps[135] = 1'b0; //Start bit
assign o_rsps[134] = 1'b0; //Direction bit (to the host)
assign o_rsps[133:0] = response_type ? response_value_extended[133:0] : {response_value[45:0], 87'h0};
assign o_rsps_len = response_type ? 128 : 40;
assign r5_cmd = (state == RESET) || (state == INITIALIZE) || (state == STANDBY) || (state == INACTIVE) ? 2'b00 :
(state == COMMAND) ? 2'b01 :
(state == TRANSFER) ? 2'b10 :
2'b11;
assign func_data_rdy = i_cmd_phy_idle; /* Can only send data when i_cmd phy is not sending data */
assign cia_activate = (o_func_num == 0);
//synchronous logic
always @ (posedge sdio_clk) begin
if (rst) begin
response_type <= NORMAL_RESPONSE;
response_value <= 32'h00000000;
response_value_extended <= 128'h00;
end
else if (o_rsps_stb) begin
//Strobe
//Process Command
case (response_index)
R1: begin
//R1
response_type <= NORMAL_RESPONSE;
response_value <= 48'h0;
response_value[`CMD_RSP_CMD] <= i_cmd;
response_value[`R1_OUT_OF_RANGE] <= cmd_arg_out_of_range;
response_value[`R1_COM_CRC_ERROR] <= bad_crc;
response_value[`R1_ILLEGAL_COMMAND] <= illegal_command;
response_value[`R1_ERROR] <= card_error;
response_value[`R1_CURRENT_STATE] <= 4'hF;
end
R4: begin
//R4:
response_type <= NORMAL_RESPONSE;
response_value <= 48'h0;
response_value[`R4_RSRVD] <= 6'h3F;
response_value[`R4_READY] <= 1'b1;
response_value[`R4_NUM_FUNCS] <= NUM_FUNCS;
response_value[`R4_MEM_PRESENT] <= MEM_PRESENT;
response_value[`R4_UHSII_AVAILABLE] <= UHSII_AVAILABLE;
response_value[`R4_IO_OCR] <= 24'hFFFF00;
response_value[15:8] <= 8'h00;
end
R5: begin
//R5:
response_type <= NORMAL_RESPONSE;
response_value <= 48'h0;
response_value[`CMD_RSP_CMD] <= i_cmd;
response_value[`R5_FLAG_CRC_ERROR] <= bad_crc;
response_value[`R5_INVALID_CMD] <= illegal_command;
response_value[`R5_FLAG_CURR_STATE] <= r5_cmd;
response_value[`R5_FLAG_ERROR] <= card_error;
end
R6: begin
//R6: Relative address response
response_type <= NORMAL_RESPONSE;
response_value <= 48'h0;
response_value[`CMD_RSP_CMD] <= i_cmd;
response_value[`R6_REL_ADDR] <= register_card_address;
response_value[`R6_STS_CRC_COMM_ERR] <= bad_crc;
response_value[`R6_STS_ILLEGAL_CMD] <= illegal_command;
response_value[`R6_STS_ERROR] <= card_error;
end
R7: begin
//R7
response_type <= NORMAL_RESPONSE;
response_value <= 48'h0;
response_value[`CMD_RSP_CMD] <= i_cmd;
response_value[`R7_VHS] <= i_cmd_arg[`CMD5_ARG_VHS] & `VHS_DEFAULT_VALUE;
response_value[`R7_PATTERN] <= i_cmd_arg[`CMD8_ARG_PATTERN];
end
default: begin
end
endcase
end
end
always @ (posedge sdio_clk) begin
//Deassert Strobes
o_rsps_stb <= 0;
o_func_stb <= 0;
if (rst || o_soft_reset) begin
state <= INITIALIZE;
register_card_address <= 16'h0001; // Initializes the RCA to 0
voltage_select <= `VHS_DEFAULT_VALUE;
v1p8_sel <= 0;
vio_ocr <= 24'hFFFF00;
bad_crc <= 0;
cmd_arg_out_of_range <= 0;
illegal_command <= 0; //Illegal Command for the Given State
card_error <= 0; //Unknown Error
o_func_stb <= 0;
o_func_inc_addr <= 0;
o_func_block_mode <= 0;
o_func_num <= 4'h0;
o_func_write_flag <= 0; /* Read Write Flag R = 0, W = 1 */
o_func_read_after_write <= 0;
o_func_reg_addr <= 18'h0;
o_func_reg_write_data <= 8'h00;
o_func_reg_read_data <= 8'h00;
o_func_data_count <= 8'h00;
busy <= 0;
o_func_ack_stb <= 0;
response_index <= 0;
tunning_block <= 0;
o_func_data_count <= 0;
end
else if (i_cmd_stb && !i_cmd_crc_good_stb) begin
bad_crc <= 1;
//Do not send a response
end
else if (i_cmd_stb) begin
//Strobe
//Card Bootup Sequence
case (state)
RESET: begin
state <= INITIALIZE;
end
INITIALIZE: begin
case (i_cmd)
`SD_CMD_IO_SEND_OP_CMD: begin
response_index <= R4;
o_rsps_stb <= 1;
end
`SD_CMD_SEND_RELATIVE_ADDR: begin
state <= STANDBY;
response_index <= R6;
o_rsps_stb <= 1;
end
`SD_CMD_GO_INACTIVE_STATE: begin
state <= INACTIVE;
end
default: begin
illegal_command <= 1;
end
endcase
end
STANDBY: begin
case (i_cmd)
`SD_CMD_SEND_RELATIVE_ADDR: begin
state <= STANDBY;
response_index <= R6;
o_rsps_stb <= 1;
end
`SD_CMD_SEL_DESEL_CARD: begin
if (register_card_address == i_cmd_arg[15:0]) begin
state <= COMMAND;
end
response_index <= R1;
o_rsps_stb <= 1;
end
`SD_CMD_GO_INACTIVE_STATE: begin
state <= INACTIVE;
end
default: begin
illegal_command <= 1;
end
endcase
end
COMMAND: begin
case (i_cmd)
`SD_CMD_IO_RW_DIRECT: begin
o_func_write_flag <= i_cmd_arg[`CMD52_ARG_RW_FLAG ];
o_func_read_after_write <= i_cmd_arg[`CMD52_ARG_RAW_FLAG];
o_func_num <= i_cmd_arg[`CMD52_ARG_FNUM ];
o_func_reg_addr <= i_cmd_arg[`CMD52_ARG_REG_ADDR];
o_func_reg_write_data <= i_cmd_arg[`CMD52_ARG_WR_DATA ];
o_func_inc_addr <= 0;
o_func_data_count <= 1;
o_func_stb <= 1;
busy <= 1;
o_rsps_stb <= 1;
state <= TRANSFER;
end
`SD_CMD_IO_RW_EXTENDED: begin
o_func_write_flag <= i_cmd_arg[`CMD53_ARG_RW_FLAG ];
o_func_read_after_write <= 0;
o_func_num <= i_cmd_arg[`CMD53_ARG_FNUM ];
o_func_reg_addr <= i_cmd_arg[`CMD53_ARG_REG_ADDR ];
o_func_data_count <= i_cmd_arg[`CMD53_ARG_DATA_COUNT];
o_func_block_mode <= i_cmd_arg[`CMD53_ARG_BLOCK_MODE];
o_func_inc_addr <= i_cmd_arg[`CMD53_ARG_INC_ADDR ];
o_func_stb <= 1;
busy <= 1;
o_rsps_stb <= 1;
state <= TRANSFER;
end
`SD_CMD_SEL_DESEL_CARD: begin
if (register_card_address != i_cmd_arg[15:0]) begin
state <= STANDBY;
end
response_index <= R1;
o_rsps_stb <= 1;
end
`SD_CMD_SEND_TUNNING_BLOCK: begin
response_index <= R1;
o_rsps_stb <= 1;
tunning_block <= 1;
end
`SD_CMD_IO_RW_DIRECT: begin
o_rsps_stb <= 1;
end
`SD_CMD_IO_RW_EXTENDED: begin
response_index <= R5;
state <= TRANSFER;
o_rsps_stb <= 1;
end
`SD_CMD_GO_INACTIVE_STATE: begin
state <= INACTIVE;
end
default: begin
illegal_command <= 1;
end
endcase
end
TRANSFER: begin
if (o_func_ack_stb) begin
state <= COMMAND;
end
case (i_cmd)
`SD_CMD_IO_RW_DIRECT: begin
o_func_write_flag <= i_cmd_arg[`CMD52_ARG_RW_FLAG ];
o_func_read_after_write <= i_cmd_arg[`CMD52_ARG_RAW_FLAG];
o_func_num <= i_cmd_arg[`CMD52_ARG_FNUM ];
o_func_reg_addr <= i_cmd_arg[`CMD52_ARG_REG_ADDR];
o_func_reg_write_data <= i_cmd_arg[`CMD52_ARG_WR_DATA ];
o_func_stb <= 1;
busy <= 1;
o_rsps_stb <= 1;
o_func_data_count <= 1;
end
default: begin
illegal_command <= 1;
end
endcase
end
INACTIVE: begin
//Nothing Going on here
end
default: begin
end
endcase
//Always Respond to these commands regardless of state
if (i_cmd_stb) begin
case (i_cmd)
`SD_CMD_GO_IDLE_STATE: begin
$display ("Initialize SD or SPI Mode, SPI MODE NOT SUPPORTED NOW!!");
illegal_command <= 0;
response_index <= R1;
if (!chip_select_n) begin
//We are in SD Mode
o_rsps_stb <= 1;
end
else begin
//XXX: SPI MODE IS NOT SUPPORTED YET!!!
end
end
`SD_CMD_SEND_IF_COND: begin
$display ("Send Interface Condition");
illegal_command <= 0;
response_index <= R7;
/*XXX Check if this should IO_OCR */
if (i_cmd_arg[`CMD5_ARG_VHS] & `VHS_DEFAULT_VALUE) begin
v1p8_sel <= i_cmd_arg[`CMD5_ARG_S18R];
vio_ocr <= i_cmd_arg[`CMD5_ARG_VHS ];
if (i_cmd_arg[`CMD5_ARG_VHS] & `VHS_DEFAULT_VALUE)
voltage_select <= i_cmd_arg[`CMD5_ARG_VHS ] & `VHS_DEFAULT_VALUE;
o_rsps_stb <= 1;
end
end
`SD_CMD_VOLTAGE_SWITCH: begin
$display ("Voltage Mode Switch");
illegal_command <= 0;
response_index <= R1;
o_rsps_stb <= 1;
end
default: begin
end
endcase
end
end
else if (o_rsps_stb) begin
//Whenever a response is successful de-assert any of the errors, they will have been picked up by the response
bad_crc <= 0;
cmd_arg_out_of_range <= 0;
illegal_command <= 0;
card_error <= 0; //Unknown Error
end
else if (o_phy_data_finished) begin
busy <= 0;
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module AESL_axi_slave_AXI_CTRL (
clk,
reset,
TRAN_s_axi_AXI_CTRL_AWADDR,
TRAN_s_axi_AXI_CTRL_AWVALID,
TRAN_s_axi_AXI_CTRL_AWREADY,
TRAN_s_axi_AXI_CTRL_WVALID,
TRAN_s_axi_AXI_CTRL_WREADY,
TRAN_s_axi_AXI_CTRL_WDATA,
TRAN_s_axi_AXI_CTRL_WSTRB,
TRAN_s_axi_AXI_CTRL_ARADDR,
TRAN_s_axi_AXI_CTRL_ARVALID,
TRAN_s_axi_AXI_CTRL_ARREADY,
TRAN_s_axi_AXI_CTRL_RVALID,
TRAN_s_axi_AXI_CTRL_RREADY,
TRAN_s_axi_AXI_CTRL_RDATA,
TRAN_s_axi_AXI_CTRL_RRESP,
TRAN_s_axi_AXI_CTRL_BVALID,
TRAN_s_axi_AXI_CTRL_BREADY,
TRAN_s_axi_AXI_CTRL_BRESP,
TRAN_AXI_CTRL_write_data_finish,
TRAN_AXI_CTRL_read_data_finish,
TRAN_AXI_CTRL_start_in,
TRAN_AXI_CTRL_idle_out,
TRAN_AXI_CTRL_ready_out,
TRAN_AXI_CTRL_ready_in,
TRAN_AXI_CTRL_done_out,
TRAN_AXI_CTRL_write_start_in ,
TRAN_AXI_CTRL_write_start_finish,
TRAN_AXI_CTRL_transaction_done_in,
TRAN_AXI_CTRL_interrupt
);
//------------------------Parameter----------------------
`define TV_IN_a "./c.adder.autotvin_a.dat"
`define TV_IN_b "./c.adder.autotvin_b.dat"
`define TV_OUT_c "./rtl.adder.autotvout_c.dat"
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 32;
parameter a_DEPTH = 1;
reg [31 : 0] a_OPERATE_DEPTH = 0;
parameter a_c_bitwidth = 32;
parameter b_DEPTH = 1;
reg [31 : 0] b_OPERATE_DEPTH = 0;
parameter b_c_bitwidth = 32;
parameter c_DEPTH = 1;
reg [31 : 0] c_OPERATE_DEPTH = 0;
parameter c_c_bitwidth = 32;
parameter START_ADDR = 0;
parameter adder_continue_addr = 0;
parameter adder_auto_start_addr = 0;
parameter a_data_in_addr = 16;
parameter b_data_in_addr = 24;
parameter c_data_out_addr = 32;
parameter c_valid_out_addr = 36;
parameter STATUS_ADDR = 0;
output [ADDR_WIDTH - 1 : 0] TRAN_s_axi_AXI_CTRL_AWADDR;
output TRAN_s_axi_AXI_CTRL_AWVALID;
input TRAN_s_axi_AXI_CTRL_AWREADY;
output TRAN_s_axi_AXI_CTRL_WVALID;
input TRAN_s_axi_AXI_CTRL_WREADY;
output [DATA_WIDTH - 1 : 0] TRAN_s_axi_AXI_CTRL_WDATA;
output [DATA_WIDTH/8 - 1 : 0] TRAN_s_axi_AXI_CTRL_WSTRB;
output [ADDR_WIDTH - 1 : 0] TRAN_s_axi_AXI_CTRL_ARADDR;
output TRAN_s_axi_AXI_CTRL_ARVALID;
input TRAN_s_axi_AXI_CTRL_ARREADY;
input TRAN_s_axi_AXI_CTRL_RVALID;
output TRAN_s_axi_AXI_CTRL_RREADY;
input [DATA_WIDTH - 1 : 0] TRAN_s_axi_AXI_CTRL_RDATA;
input [2 - 1 : 0] TRAN_s_axi_AXI_CTRL_RRESP;
input TRAN_s_axi_AXI_CTRL_BVALID;
output TRAN_s_axi_AXI_CTRL_BREADY;
input [2 - 1 : 0] TRAN_s_axi_AXI_CTRL_BRESP;
output TRAN_AXI_CTRL_write_data_finish;
output TRAN_AXI_CTRL_read_data_finish;
input clk;
input reset;
input TRAN_AXI_CTRL_start_in;
output TRAN_AXI_CTRL_done_out;
output TRAN_AXI_CTRL_ready_out;
input TRAN_AXI_CTRL_ready_in;
output TRAN_AXI_CTRL_idle_out;
input TRAN_AXI_CTRL_write_start_in ;
output TRAN_AXI_CTRL_write_start_finish;
input TRAN_AXI_CTRL_interrupt;
input TRAN_AXI_CTRL_transaction_done_in;
reg [ADDR_WIDTH - 1 : 0] AWADDR_reg = 0;
reg AWVALID_reg = 0;
reg WVALID_reg = 0;
reg [DATA_WIDTH - 1 : 0] WDATA_reg = 0;
reg [DATA_WIDTH/8 - 1 : 0] WSTRB_reg = 0;
reg [ADDR_WIDTH - 1 : 0] ARADDR_reg = 0;
reg ARVALID_reg = 0;
reg RREADY_reg = 0;
reg [DATA_WIDTH - 1 : 0] RDATA_reg = 0;
reg BREADY_reg = 0;
reg [DATA_WIDTH - 1 : 0] mem_a [a_DEPTH - 1 : 0];
reg a_write_data_finish;
reg [DATA_WIDTH - 1 : 0] mem_b [b_DEPTH - 1 : 0];
reg b_write_data_finish;
reg [DATA_WIDTH - 1 : 0] mem_c [c_DEPTH - 1 : 0];
reg c_read_data_finish;
reg AESL_ready_out_index_reg;
reg AESL_write_start_finish;
reg AESL_ready_reg;
reg ready_initial;
reg AESL_done_index_reg = 0;
reg AESL_idle_index_reg = 0;
reg AESL_auto_restart_index_reg;
reg process_0_finish = 0;
reg process_1_finish = 0;
reg process_2_finish = 0;
reg process_3_finish = 0;
reg process_4_finish = 0;
//write a reg
reg [31 : 0] write_a_count = 0;
reg write_a_run_flag = 0;
reg write_one_a_data_done = 0;
//write b reg
reg [31 : 0] write_b_count = 0;
reg write_b_run_flag = 0;
reg write_one_b_data_done = 0;
//read c reg
reg [31 : 0] read_c_count = 0;
reg read_c_run_flag = 0;
reg read_one_c_data_done = 0;
reg [31 : 0] write_start_count = 0;
reg write_start_run_flag = 0;
//===================process control=================
reg [31 : 0] ongoing_process_number = 0;
//process number depends on how much processes needed.
reg process_busy = 0;
//=================== signal connection ==============
assign TRAN_s_axi_AXI_CTRL_AWADDR = AWADDR_reg;
assign TRAN_s_axi_AXI_CTRL_AWVALID = AWVALID_reg;
assign TRAN_s_axi_AXI_CTRL_WVALID = WVALID_reg;
assign TRAN_s_axi_AXI_CTRL_WDATA = WDATA_reg;
assign TRAN_s_axi_AXI_CTRL_WSTRB = WSTRB_reg;
assign TRAN_s_axi_AXI_CTRL_ARADDR = ARADDR_reg;
assign TRAN_s_axi_AXI_CTRL_ARVALID = ARVALID_reg;
assign TRAN_s_axi_AXI_CTRL_RREADY = RREADY_reg;
assign TRAN_s_axi_AXI_CTRL_BREADY = BREADY_reg;
assign TRAN_AXI_CTRL_write_start_finish = AESL_write_start_finish;
assign TRAN_AXI_CTRL_done_out = AESL_done_index_reg;
assign TRAN_AXI_CTRL_ready_out = AESL_ready_out_index_reg;
assign TRAN_AXI_CTRL_idle_out = AESL_idle_index_reg;
assign TRAN_AXI_CTRL_read_data_finish = 1 & c_read_data_finish;
assign TRAN_AXI_CTRL_write_data_finish = 1 & a_write_data_finish & b_write_data_finish;
always @(TRAN_AXI_CTRL_ready_in or ready_initial)
begin
AESL_ready_reg <= TRAN_AXI_CTRL_ready_in | ready_initial;
end
always @(reset or process_0_finish or process_1_finish or process_2_finish or process_3_finish or process_4_finish ) begin
if (reset == 0) begin
ongoing_process_number <= 0;
end
else if (ongoing_process_number == 0 && process_0_finish == 1) begin
ongoing_process_number <= ongoing_process_number + 1;
end
else if (ongoing_process_number == 1 && process_1_finish == 1) begin
ongoing_process_number <= ongoing_process_number + 1;
end
else if (ongoing_process_number == 2 && process_2_finish == 1) begin
ongoing_process_number <= ongoing_process_number + 1;
end
else if (ongoing_process_number == 3 && process_3_finish == 1) begin
ongoing_process_number <= ongoing_process_number + 1;
end
else if (ongoing_process_number == 4 && process_4_finish == 1) begin
ongoing_process_number <= 0;
end
end
task count_c_data_four_byte_num_by_bitwidth;
input integer bitwidth;
output integer num;
integer factor;
integer i;
begin
factor = 32;
for (i = 1; i <= 32; i = i + 1) begin
if (bitwidth <= factor && bitwidth > factor - 32) begin
num = i;
end
factor = factor + 32;
end
end
endtask
task count_seperate_factor_by_bitwidth;
input integer bitwidth;
output integer factor;
begin
if (bitwidth <= 8 ) begin
factor=4;
end
if (bitwidth <= 16 & bitwidth > 8 ) begin
factor=2;
end
if (bitwidth <= 32 & bitwidth > 16 ) begin
factor=1;
end
if (bitwidth <= 1024 & bitwidth > 32 ) begin
factor=1;
end
end
endtask
task count_operate_depth_by_bitwidth_and_depth;
input integer bitwidth;
input integer depth;
output integer operate_depth;
integer factor;
integer remain;
begin
count_seperate_factor_by_bitwidth (bitwidth , factor);
operate_depth = depth / factor;
remain = depth % factor;
if (remain > 0) begin
operate_depth = operate_depth + 1;
end
end
endtask
task write; /*{{{*/
input reg [ADDR_WIDTH - 1:0] waddr; // write address
input reg [DATA_WIDTH - 1:0] wdata; // write data
output reg wresp;
reg aw_flag;
reg w_flag;
reg [DATA_WIDTH/8 - 1:0] wstrb_reg;
integer i;
begin
wresp = 0;
aw_flag = 0;
w_flag = 0;
//=======================one single write operate======================
AWADDR_reg <= waddr;
AWVALID_reg <= 1;
WDATA_reg <= wdata;
WVALID_reg <= 1;
for (i = 0; i < DATA_WIDTH/8; i = i + 1) begin
wstrb_reg [i] = 1;
end
WSTRB_reg <= wstrb_reg;
while (!(aw_flag && w_flag)) begin
@(posedge clk);
if (aw_flag != 1)
aw_flag = TRAN_s_axi_AXI_CTRL_AWREADY & AWVALID_reg;
if (w_flag != 1)
w_flag = TRAN_s_axi_AXI_CTRL_WREADY & WVALID_reg;
AWVALID_reg <= !aw_flag;
WVALID_reg <= !w_flag;
end
BREADY_reg <= 1;
while (TRAN_s_axi_AXI_CTRL_BVALID != 1) begin
//wait for response
@(posedge clk);
end
@(posedge clk);
BREADY_reg <= 0;
if (TRAN_s_axi_AXI_CTRL_BRESP === 2'b00) begin
wresp = 1;
//input success. in fact BRESP is always 2'b00
end
//=======================one single write operate======================
end
endtask/*}}}*/
task read (/*{{{*/
input [ADDR_WIDTH - 1:0] raddr , // write address
output [DATA_WIDTH - 1:0] RDATA_result ,
output rresp
);
begin
rresp = 0;
//=======================one single read operate======================
ARADDR_reg <= raddr;
ARVALID_reg <= 1;
while (TRAN_s_axi_AXI_CTRL_ARREADY !== 1) begin
@(posedge clk);
end
@(posedge clk);
ARVALID_reg <= 0;
RREADY_reg <= 1;
while (TRAN_s_axi_AXI_CTRL_RVALID !== 1) begin
//wait for response
@(posedge clk);
end
@(posedge clk);
RDATA_result <= TRAN_s_axi_AXI_CTRL_RDATA;
RREADY_reg <= 0;
if (TRAN_s_axi_AXI_CTRL_RRESP === 2'b00 ) begin
rresp <= 1;
//output success. in fact RRESP is always 2'b00
end
@(posedge clk);
//=======================one single read operate end======================
end
endtask/*}}}*/
initial begin : ready_initial_process
ready_initial = 0;
wait(reset === 1);
@(posedge clk);
ready_initial = 1;
@(posedge clk);
ready_initial = 0;
end
initial begin : update_status
integer process_num ;
integer read_status_resp;
wait(reset === 1);
@(posedge clk);
process_num = 0;
while (1) begin
process_0_finish = 0;
AESL_done_index_reg <= 0;
AESL_ready_out_index_reg <= 0;
if (ongoing_process_number === process_num && process_busy === 0) begin
process_busy = 1;
read (STATUS_ADDR, RDATA_reg, read_status_resp);
AESL_done_index_reg <= RDATA_reg[1 : 1];
AESL_ready_out_index_reg <= RDATA_reg[1 : 1];
AESL_idle_index_reg <= RDATA_reg[2 : 2];
process_0_finish = 1;
process_busy = 0;
end
@(posedge clk);
end
end
always @(reset or posedge clk) begin
if (reset == 0) begin
write_a_run_flag <= 0;
write_a_count = 0;
count_operate_depth_by_bitwidth_and_depth (a_c_bitwidth, a_DEPTH, a_OPERATE_DEPTH);
end
else begin
if (TRAN_AXI_CTRL_start_in === 1) begin
a_write_data_finish <= 0;
end
if (AESL_ready_reg === 1) begin
write_a_run_flag <= 1;
write_a_count = 0;
end
if (write_one_a_data_done === 1) begin
write_a_count = write_a_count + 1;
if (write_a_count == a_OPERATE_DEPTH) begin
write_a_run_flag <= 0;
a_write_data_finish <= 1;
end
end
end
end
initial begin : write_a
integer write_a_resp;
integer process_num ;
integer get_ack;
integer four_byte_num;
integer c_bitwidth;
integer i;
integer j;
reg [31 : 0] a_data_tmp_reg;
wait(reset === 1);
@(posedge clk);
c_bitwidth = a_c_bitwidth;
process_num = 1;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (1) begin
process_1_finish <= 0;
if (ongoing_process_number === process_num && process_busy === 0 ) begin
get_ack = 1;
if (write_a_run_flag === 1 && get_ack === 1) begin
process_busy = 1;
//write a data
for (i = 0 ; i < four_byte_num ; i = i+1) begin
if (a_c_bitwidth < 32) begin
a_data_tmp_reg = mem_a[write_a_count];
end
else begin
for (j=0 ; j<32 ; j = j + 1) begin
if (i*32 + j < a_c_bitwidth) begin
a_data_tmp_reg[j] = mem_a[write_a_count][i*32 + j];
end
else begin
a_data_tmp_reg[j] = 0;
end
end
end
write (a_data_in_addr + write_a_count * four_byte_num * 4 + i * 4, a_data_tmp_reg, write_a_resp);
end
process_busy = 0;
write_one_a_data_done <= 1;
@(posedge clk);
write_one_a_data_done <= 0;
end
process_1_finish <= 1;
end
@(posedge clk);
end
end
always @(reset or posedge clk) begin
if (reset == 0) begin
write_b_run_flag <= 0;
write_b_count = 0;
count_operate_depth_by_bitwidth_and_depth (b_c_bitwidth, b_DEPTH, b_OPERATE_DEPTH);
end
else begin
if (TRAN_AXI_CTRL_start_in === 1) begin
b_write_data_finish <= 0;
end
if (AESL_ready_reg === 1) begin
write_b_run_flag <= 1;
write_b_count = 0;
end
if (write_one_b_data_done === 1) begin
write_b_count = write_b_count + 1;
if (write_b_count == b_OPERATE_DEPTH) begin
write_b_run_flag <= 0;
b_write_data_finish <= 1;
end
end
end
end
initial begin : write_b
integer write_b_resp;
integer process_num ;
integer get_ack;
integer four_byte_num;
integer c_bitwidth;
integer i;
integer j;
reg [31 : 0] b_data_tmp_reg;
wait(reset === 1);
@(posedge clk);
c_bitwidth = b_c_bitwidth;
process_num = 2;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (1) begin
process_2_finish <= 0;
if (ongoing_process_number === process_num && process_busy === 0 ) begin
get_ack = 1;
if (write_b_run_flag === 1 && get_ack === 1) begin
process_busy = 1;
//write b data
for (i = 0 ; i < four_byte_num ; i = i+1) begin
if (b_c_bitwidth < 32) begin
b_data_tmp_reg = mem_b[write_b_count];
end
else begin
for (j=0 ; j<32 ; j = j + 1) begin
if (i*32 + j < b_c_bitwidth) begin
b_data_tmp_reg[j] = mem_b[write_b_count][i*32 + j];
end
else begin
b_data_tmp_reg[j] = 0;
end
end
end
write (b_data_in_addr + write_b_count * four_byte_num * 4 + i * 4, b_data_tmp_reg, write_b_resp);
end
process_busy = 0;
write_one_b_data_done <= 1;
@(posedge clk);
write_one_b_data_done <= 0;
end
process_2_finish <= 1;
end
@(posedge clk);
end
end
always @(reset or posedge clk) begin
if (reset == 0) begin
write_start_run_flag <= 0;
write_start_count <= 0;
end
else begin
if (write_start_count >= 1) begin
write_start_run_flag <= 0;
end
else if (TRAN_AXI_CTRL_write_start_in === 1) begin
write_start_run_flag <= 1;
end
if (AESL_write_start_finish === 1) begin
write_start_count <= write_start_count + 1;
write_start_run_flag <= 0;
end
end
end
initial begin : write_start
reg [DATA_WIDTH - 1 : 0] write_start_tmp;
integer process_num;
integer write_start_resp;
wait(reset === 1);
@(posedge clk);
process_num = 3;
while (1) begin
process_3_finish = 0;
if (ongoing_process_number === process_num && process_busy === 0 ) begin
if (write_start_run_flag === 1) begin
process_busy = 1;
write_start_tmp=0;
write_start_tmp[0 : 0] = 1;
write (START_ADDR, write_start_tmp, write_start_resp);
process_busy = 0;
AESL_write_start_finish <= 1;
@(posedge clk);
AESL_write_start_finish <= 0;
end
process_3_finish <= 1;
end
@(posedge clk);
end
end
always @(reset or posedge clk) begin
if (reset == 0) begin
read_c_run_flag <= 0;
read_c_count = 0;
count_operate_depth_by_bitwidth_and_depth (c_c_bitwidth, c_DEPTH, c_OPERATE_DEPTH);
end
else begin
if (TRAN_AXI_CTRL_start_in === 1) begin
read_c_run_flag = 1;
end
if (TRAN_AXI_CTRL_transaction_done_in === 1) begin
c_read_data_finish <= 0;
read_c_count = 0;
end
if (read_one_c_data_done === 1) begin
read_c_count = read_c_count + 1;
if (read_c_count == c_OPERATE_DEPTH) begin
read_c_run_flag <= 0;
c_read_data_finish <= 1;
end
end
end
end
initial begin : read_c
integer read_c_resp;
integer process_num;
integer get_vld;
integer four_byte_num;
integer c_bitwidth;
integer i;
integer j;
wait(reset === 1);
@(posedge clk);
c_bitwidth = c_c_bitwidth;
process_num = 4;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (1) begin
process_4_finish <= 0;
if (ongoing_process_number === process_num && process_busy === 0 ) begin
if (read_c_run_flag === 1) begin
process_busy = 1;
get_vld = 0;
//read c vld
read (c_valid_out_addr, RDATA_reg, read_c_resp);
if (RDATA_reg[0 : 0] == 1) begin
get_vld = 1;
end
if (get_vld == 1) begin
//read c data
for (i = 0 ; i < four_byte_num ; i = i+1) begin
read (c_data_out_addr + read_c_count * four_byte_num * 4 + i * 4, RDATA_reg, read_c_resp);
if (c_c_bitwidth < 32) begin
mem_c[read_c_count] <= RDATA_reg;
end
else begin
for (j=0 ; j < 32 ; j = j + 1) begin
if (i*32 + j < c_c_bitwidth) begin
mem_c[read_c_count][i*32 + j] <= RDATA_reg[j];
end
end
end
end
read_one_c_data_done <= 1;
@(posedge clk);
read_one_c_data_done <= 0;
end
process_busy = 0;
end
process_4_finish <= 1;
end
@(posedge clk);
end
end
//------------------------Task and function--------------
task read_token;
input integer fp;
output reg [127 : 0] token;
reg [7:0] c;
reg intoken;
reg done;
begin
token = "";
intoken = 0;
done = 0;
while (!done) begin
c = $fgetc(fp);
if (c == 8'hff) begin // EOF
done = 1;
end
else if (c == " " || c == "\011" || c == "\012" || c == "\015") begin // blank
if (intoken) begin
done = 1;
end
end
else begin // valid character
intoken = 1;
token = (token << 8) | c;
end
end
end
endtask
//------------------------Read file------------------------
// Read data from file
initial begin : read_a_file_process
integer fp;
integer ret;
integer factor;
reg [127 : 0] token;
reg [a_c_bitwidth - 1 : 0] token_tmp;
reg [DATA_WIDTH - 1 : 0] mem_tmp;
reg [ 8*5 : 1] str;
integer transaction_idx;
integer i;
transaction_idx = 0;
mem_tmp [DATA_WIDTH - 1 : 0] = 0;
count_seperate_factor_by_bitwidth (a_c_bitwidth , factor);
fp = $fopen(`TV_IN_a ,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `TV_IN_a);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
@(posedge clk);
# 0.2;
while(AESL_ready_reg !== 1) begin
@(posedge clk);
# 0.2;
end
for(i = 0; i < a_DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", token_tmp);
if (factor == 4) begin
if (i%factor == 0) begin
mem_tmp [7 : 0] = token_tmp;
end
if (i%factor == 1) begin
mem_tmp [15 : 8] = token_tmp;
end
if (i%factor == 2) begin
mem_tmp [23 : 16] = token_tmp;
end
if (i%factor == 3) begin
mem_tmp [31 : 24] = token_tmp;
mem_a [i/factor] = mem_tmp;
mem_tmp [DATA_WIDTH - 1 : 0] = 0;
end
end
if (factor == 2) begin
if (i%factor == 0) begin
mem_tmp [15 : 0] = token_tmp;
end
if (i%factor == 1) begin
mem_tmp [31 : 16] = token_tmp;
mem_a [i/factor] = mem_tmp;
mem_tmp [DATA_WIDTH - 1: 0] = 0;
end
end
if (factor == 1) begin
mem_a [i] = token_tmp;
end
end
if (factor == 4) begin
if (i%factor != 0) begin
mem_a [i/factor] = mem_tmp;
end
end
if (factor == 2) begin
if (i%factor != 0) begin
mem_a [i/factor] = mem_tmp;
end
end
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
//------------------------Read file------------------------
// Read data from file
initial begin : read_b_file_process
integer fp;
integer ret;
integer factor;
reg [127 : 0] token;
reg [b_c_bitwidth - 1 : 0] token_tmp;
reg [DATA_WIDTH - 1 : 0] mem_tmp;
reg [ 8*5 : 1] str;
integer transaction_idx;
integer i;
transaction_idx = 0;
mem_tmp [DATA_WIDTH - 1 : 0] = 0;
count_seperate_factor_by_bitwidth (b_c_bitwidth , factor);
fp = $fopen(`TV_IN_b ,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `TV_IN_b);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
@(posedge clk);
# 0.2;
while(AESL_ready_reg !== 1) begin
@(posedge clk);
# 0.2;
end
for(i = 0; i < b_DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", token_tmp);
if (factor == 4) begin
if (i%factor == 0) begin
mem_tmp [7 : 0] = token_tmp;
end
if (i%factor == 1) begin
mem_tmp [15 : 8] = token_tmp;
end
if (i%factor == 2) begin
mem_tmp [23 : 16] = token_tmp;
end
if (i%factor == 3) begin
mem_tmp [31 : 24] = token_tmp;
mem_b [i/factor] = mem_tmp;
mem_tmp [DATA_WIDTH - 1 : 0] = 0;
end
end
if (factor == 2) begin
if (i%factor == 0) begin
mem_tmp [15 : 0] = token_tmp;
end
if (i%factor == 1) begin
mem_tmp [31 : 16] = token_tmp;
mem_b [i/factor] = mem_tmp;
mem_tmp [DATA_WIDTH - 1: 0] = 0;
end
end
if (factor == 1) begin
mem_b [i] = token_tmp;
end
end
if (factor == 4) begin
if (i%factor != 0) begin
mem_b [i/factor] = mem_tmp;
end
end
if (factor == 2) begin
if (i%factor != 0) begin
mem_b [i/factor] = mem_tmp;
end
end
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
//------------------------Write file-----------------------
// Write data to file
initial begin : write_c_file_proc
integer fp;
integer factor;
integer transaction_idx;
reg [c_c_bitwidth - 1 : 0] mem_tmp;
reg [ 100*8 : 1] str;
integer i;
transaction_idx = 0;
count_seperate_factor_by_bitwidth (c_c_bitwidth , factor);
while(1) begin
@(posedge clk);
while (c_read_data_finish !== 1) begin
@(posedge clk);
end
# 0.1;
fp = $fopen(`TV_OUT_c, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `TV_OUT_c);
$finish;
end
$fdisplay(fp, "[[transaction]] %d", transaction_idx);
for (i = 0; i < (c_DEPTH - c_DEPTH % factor); i = i + 1) begin
if (factor == 4) begin
if (i%factor == 0) begin
mem_tmp = mem_c[i/factor][7:0];
end
if (i%factor == 1) begin
mem_tmp = mem_c[i/factor][15:8];
end
if (i%factor == 2) begin
mem_tmp = mem_c[i/factor][23:16];
end
if (i%factor == 3) begin
mem_tmp = mem_c[i/factor][31:24];
end
$fdisplay(fp,"0x%x",mem_tmp);
end
if (factor == 2) begin
if (i%factor == 0) begin
mem_tmp = mem_c[i/factor][15:0];
end
if (i%factor == 1) begin
mem_tmp = mem_c[i/factor][31:16];
end
$fdisplay(fp,"0x%x",mem_tmp);
end
if (factor == 1) begin
$fdisplay(fp,"0x%x",mem_c[i]);
end
end
if (factor == 4) begin
if ((c_DEPTH - 1) % factor == 2) begin
$fdisplay(fp,"0x%x",mem_c[c_DEPTH / factor][7:0]);
$fdisplay(fp,"0x%x",mem_c[c_DEPTH / factor][15:8]);
$fdisplay(fp,"0x%x",mem_c[c_DEPTH / factor][23:16]);
end
if ((c_DEPTH - 1) % factor == 1) begin
$fdisplay(fp,"0x%x",mem_c[c_DEPTH / factor][7:0]);
$fdisplay(fp,"0x%x",mem_c[c_DEPTH / factor][15:8]);
end
if ((c_DEPTH - 1) % factor == 0) begin
$fdisplay(fp,"0x%x",mem_c[c_DEPTH / factor][7:0]);
end
end
if (factor == 2) begin
if ((c_DEPTH - 1) % factor == 0) begin
$fdisplay(fp,"0x%x",mem_c[c_DEPTH / factor][15:0]);
end
end
$fdisplay(fp, "[[/transaction]]");
transaction_idx = transaction_idx + 1;
$fclose(fp);
while (TRAN_AXI_CTRL_start_in !== 1) begin
@(posedge clk);
end
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: init_mem_pattern_ctr.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:41:58 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This moduel has a small FSM to control the operation of
// mcb_traffic_gen module.It first fill up the memory with a selected
// DATA pattern and then starts the memory testing state.
//Reference:
//Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
// and the fixed_bl_o is fixed at 64 if data_mode_o == PRBA and FAMILY == "SPARTAN6"
// The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
// 1.2 10-1-2009 Added parameter TST_MEM_INSTR_MODE to select instruction pattern during
// memory testing phase.
//*****************************************************************************
`timescale 1ps/1ps
module init_mem_pattern_ctr #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6", // VIRTEX6, SPARTAN6
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands:
// "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE"
// "R_W_INSTR_MODE", "RP_WP_INSTR_MODE
// "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE"
// Virtex 6 Available commands:
// "FIXED_INSTR_R_MODE" - Only Read commands will be generated.
// "FIXED_INSTR_W_MODE" -- Only Write commands will be generated.
// "R_W_INSTR_MODE" - Random Read/Write commands will be generated.
parameter MEM_BURST_LEN = 8, // VIRTEX 6 Option.
parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_ALL" option generates all available
// commands pattern.
parameter BEGIN_ADDRESS = 32'h00000000,
parameter END_ADDRESS = 32'h00000fff,
parameter ADDR_WIDTH = 30,
parameter DWIDTH = 32,
parameter CMD_SEED_VALUE = 32'h12345678,
parameter DATA_SEED_VALUE = 32'hca345675,
parameter DATA_MODE = 4'b0010,
parameter PORT_MODE = "BI_MODE", // V6 Option: "BI_MODE"; SP6 Option: "WR_MODE", "RD_MODE", "BI_MODE"
parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory signals.
// Traffic Generator will only write to one single location and no
// read transactions will be generated.
)
(
input clk_i,
input rst_i,
input [ADDR_WIDTH-1:0] mcb_cmd_addr_i,
input [5:0] mcb_cmd_bl_i,
input mcb_cmd_en_i,
input [2:0] mcb_cmd_instr_i,
input mcb_wr_en_i,
input vio_modify_enable, // 0: default to ADDR as DATA PATTERN. No runtime change in data mode.
// 1: enable exteral VIO to control the data_mode pattern
// and address mode pattern during runtime.
input [2:0] vio_data_mode_value,
input [2:0] vio_addr_mode_value,
input [1:0] vio_bl_mode_value,
input [5:0] vio_fixed_bl_value, // valid range is: from 1 to 64.
input mcb_init_done_i,
input cmp_error,
output reg run_traffic_o,
// runtime parameter
output [31:0] start_addr_o, // define the start of address
output [31:0] end_addr_o,
output [31:0] cmd_seed_o, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen
output [31:0] data_seed_o,
output reg load_seed_o, //
// upper layer inputs to determine the command bus and data pattern
// internal traffic generator initialize the memory with
output reg [2:0] addr_mode_o, // "00" = bram; takes the address from bram output
// "001" = fixed address from the fixed_addr input
// "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "011" = sequential
// for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
// in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
output reg [3:0] instr_mode_o, // "0000" = Fixed
// "0001" = bram; takes instruction from bram output
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
output reg [1:0] bl_mode_o, // "00" = bram; takes the burst length from bram output
// "01" = fixed , takes the burst length from the fixed_bl input
// "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
output reg [3:0] data_mode_o, // "00" = bram;
// "01" = fixed data from the fixed_data input
// "10" = psuedo ramdom pattern; generated from internal 32 bit LFSR
// "11" = sequential using the addrs as the starting data pattern
output reg mode_load_o,
// fixed pattern inputs interface
output reg [5:0] fixed_bl_o, // range from 1 to 64
output reg [2:0] fixed_instr_o, //RD 3'b001
//RDP 3'b011
//WR 3'b000
//WRP 3'b010
//REFRESH 3'b100
output [31:0] fixed_addr_o // only upper 30 bits will be used
);
//FSM State Defination
parameter IDLE = 5'b00001,
INIT_MEM_WRITE = 5'b00010,
INIT_MEM_READ = 5'b00100,
TEST_MEM = 5'b01000,
CMP_ERROR = 5'b10000;
localparam BRAM_ADDR = 2'b00;
localparam FIXED_ADDR = 2'b01;
localparam PRBS_ADDR = 2'b10;
localparam SEQUENTIAL_ADDR = 2'b11;
localparam BRAM_INSTR_MODE = 4'b0000;
localparam FIXED_INSTR_MODE = 4'b0001;
localparam R_W_INSTR_MODE = 4'b0010;
localparam RP_WP_INSTR_MODE = 4'b0011;
localparam R_RP_W_WP_INSTR_MODE = 4'b0100;
localparam R_RP_W_WP_REF_INSTR_MODE = 4'b0101;
localparam BRAM_BL_MODE = 2'b00;
localparam FIXED_BL_MODE = 2'b01;
localparam PRBS_BL_MODE = 2'b10;
localparam BRAM_DATAL_MODE = 4'b0000;
localparam FIXED_DATA_MODE = 4'b0001;
localparam ADDR_DATA_MODE = 4'b0010;
localparam HAMMER_DATA_MODE = 4'b0011;
localparam NEIGHBOR_DATA_MODE = 4'b0100;
localparam WALKING1_DATA_MODE = 4'b0101;
localparam WALKING0_DATA_MODE = 4'b0110;
localparam PRBS_DATA_MODE = 4'b0111;
// type fixed instruction
localparam RD_INSTR = 3'b001;
localparam RDP_INSTR = 3'b011;
localparam WR_INSTR = 3'b000;
localparam WRP_INSTR = 3'b010;
localparam REFRESH_INSTR = 3'b100;
localparam NOP_WR_INSTR = 3'b101;
reg [4:0] current_state;
reg [4:0] next_state;
reg mcb_init_done_reg;
reg AC2_G_E2,AC1_G_E1,AC3_G_E3;
reg upper_end_matched;
reg [31:0] end_boundary_addr;
reg [31:0] mcb_cmd_addr_r;
reg mcb_cmd_en_r;
//reg [ADDR_WIDTH-1:0] mcb_cmd_addr_r;
reg [5:0] mcb_cmd_bl_r;
reg lower_end_matched;
reg end_addr_reached;
reg run_traffic;
reg bram_mode_enable;
wire tst_matched;
reg [31:0] current_address;
reg [5:0] fix_bl_value;
reg [3:0] data_mode_sel;
reg [2:0] addr_mode_sel;
reg [1:0] bl_mode_sel;
reg [2:0] addr_mode;
reg [10:0] INC_COUNTS;
wire [5:0] FIXEDBL;
wire [3:0] test_mem_instr_mode;
assign test_mem_instr_mode = (TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE") ? 4'b0000:
(TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" ||
TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") ? 4'b0001:
(TST_MEM_INSTR_MODE == "R_W_INSTR_MODE") ? 4'b0010:
(TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0011:
(TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0100:
(TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0101:
4'b0010;
assign FIXEDBL = 64; // This is fixed for current Spartan 6 Example Design
generate
if (FAMILY == "SPARTAN6" ) begin : INC_COUNTS_S
always @ (posedge clk_i)
INC_COUNTS <= (DWIDTH/8);
end
endgenerate
generate
if (FAMILY == "VIRTEX6" ) begin : INC_COUNTS_V
always @ (posedge clk_i)
begin
if ( (DWIDTH >= 256 && DWIDTH <= 576)) // 64 144
INC_COUNTS <= 32 ;
else if ((DWIDTH >= 128) && (DWIDTH <= 224)) // 32 dq pins or 566 dq pins
INC_COUNTS <= 16 ;
else if ((DWIDTH == 64) || (DWIDTH == 96)) // 16 dq pins or 24 dqpins
INC_COUNTS <= 8 ;
else if ((DWIDTH == 32) ) // 8 dq pins
INC_COUNTS <= 4 ;
end
end
endgenerate
always @ (posedge clk_i)
begin
if (rst_i)
current_address <= BEGIN_ADDRESS;
else if (mcb_wr_en_i && (current_state == INIT_MEM_WRITE && (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE"))
|| (mcb_wr_en_i && (current_state == IDLE && PORT_MODE == "RD_MODE")) )
current_address <= current_address + INC_COUNTS;
else
current_address <= current_address;
end
always @ (posedge clk_i)
begin
if (current_address[29:24] >= end_boundary_addr[29:24])
AC3_G_E3 <= 1'b1;
else
AC3_G_E3 <= 1'b0;
if (current_address[23:16] >= end_boundary_addr[23:16])
AC2_G_E2 <= 1'b1;
else
AC2_G_E2 <= 1'b0;
if (current_address[15:8] >= end_boundary_addr[15:8])
AC1_G_E1 <= 1'b1;
else
AC1_G_E1 <= 1'b0;
end
always @(posedge clk_i)
begin
if (rst_i)
upper_end_matched <= 1'b0;
else if (mcb_cmd_en_i)
upper_end_matched <= AC3_G_E3 & AC2_G_E2 & AC1_G_E1;
end
wire [6:0] FIXED_BL_VALUE;
assign FIXED_BL_VALUE = (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 8) ? 2 :
(FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4) ? 1 :
FIXEDBL;
always @(posedge clk_i)
begin
// end_boundary_addr <= (END_ADDRESS[31:0] - (DWIDTH/8)*FIXEDBL +1) ;
end_boundary_addr <= (END_ADDRESS[31:0] - (DWIDTH/8) +1) ;
end
always @(posedge clk_i)
begin
if (current_address[7:0] >= end_boundary_addr[7:0])
lower_end_matched <= 1'b1;
else
lower_end_matched <= 1'b0;
end
always @(posedge clk_i)
begin
if (mcb_cmd_en_i )
mcb_cmd_addr_r <= mcb_cmd_addr_i;
end
always @(posedge clk_i)
begin
if (mcb_cmd_en_i)
mcb_cmd_bl_r <= mcb_cmd_bl_i;
end
always @(posedge clk_i)
begin
if ((upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 32) ||
(upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 64) ||
(upper_end_matched && DWIDTH == 128 && FAMILY == "SPARTAN6") ||
(upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6"))
end_addr_reached <= 1'b1;
else
end_addr_reached <= 1'b0;
end
assign tst_matched = upper_end_matched & lower_end_matched;
assign fixed_addr_o = 32'h00001234;
always @ (posedge clk_i)
begin
mcb_init_done_reg <= mcb_init_done_i;
end
always @ (posedge clk_i)
run_traffic_o <= run_traffic;
always @ (posedge clk_i)
begin
if (rst_i)
current_state <= 5'b00001;
else
current_state <= next_state;
end
assign start_addr_o = BEGIN_ADDRESS;//BEGIN_ADDRESS;
assign end_addr_o = END_ADDRESS;
assign cmd_seed_o = CMD_SEED_VALUE;
assign data_seed_o = DATA_SEED_VALUE;
reg [2:0] syn1_vio_data_mode_value;
reg [2:0] syn1_vio_addr_mode_value;
always @ (posedge clk_i)
begin
if (rst_i) begin
syn1_vio_data_mode_value <= 3'b011;
syn1_vio_addr_mode_value <= 2'b11;
end
else if (vio_modify_enable == 1'b1) begin
syn1_vio_data_mode_value <= vio_data_mode_value;
syn1_vio_addr_mode_value <= vio_addr_mode_value;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
data_mode_sel <= DATA_MODE;//ADDR_DATA_MODE;
addr_mode_sel <= 2'b11;
end
else if (vio_modify_enable == 1'b1) begin
data_mode_sel <= syn1_vio_data_mode_value[2:0];
addr_mode_sel <= vio_addr_mode_value;
end
end
always @ (posedge clk_i)
begin
if (rst_i || FAMILY == "VIRTEX6")
fix_bl_value <= FIXED_BL_VALUE;//ADDR_DATA_MODE;
else if (vio_modify_enable == 1'b1) begin
fix_bl_value <= vio_fixed_bl_value;
end
end
always @ (posedge clk_i)
begin
if (rst_i || (FAMILY == "VIRTEX6"))
if (FAMILY == "VIRTEX6")
bl_mode_sel <= FIXED_BL_MODE;
else
bl_mode_sel <= PRBS_BL_MODE;
else if (vio_modify_enable == 1'b1) begin
bl_mode_sel <= vio_bl_mode_value;
end
end
always @ (posedge clk_i)
begin
data_mode_o <= data_mode_sel;
addr_mode_o <= addr_mode;
// assuming if vio_modify_enable is enabled and vio_addr_mode_value is set to zero
// user wants to have bram interface.
if (syn1_vio_addr_mode_value == 0 && vio_modify_enable == 1'b1)
bram_mode_enable <= 1'b1;
else
bram_mode_enable <= 1'b0;
end
always @ (*)
begin
load_seed_o = 1'b0;
if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
addr_mode = 'b0;
else
addr_mode = SEQUENTIAL_ADDR;
if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
instr_mode_o = 'b0;
else
instr_mode_o = FIXED_INSTR_MODE;
if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
bl_mode_o = 'b0;
else
bl_mode_o = FIXED_BL_MODE;
if (FAMILY == "VIRTEX6")
fixed_bl_o = FIXED_BL_VALUE;
// PRBS mode
else if (data_mode_o[2:0] == 3'b111 && FAMILY == "SPARTAN6")
fixed_bl_o = 64; // Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o = fix_bl_value;
mode_load_o = 1'b0;
run_traffic = 1'b0;
next_state = IDLE;
if (PORT_MODE == "RD_MODE") begin
fixed_instr_o = RD_INSTR;
end
else if( PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") begin
fixed_instr_o = WR_INSTR;
end
case(current_state)
IDLE:
begin
if(mcb_init_done_reg ) //rdp_rdy_i comes from read_data path
begin
if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") begin
next_state = INIT_MEM_WRITE;
mode_load_o = 1'b1;
run_traffic = 1'b0;
load_seed_o = 1'b1;
end
else if (PORT_MODE == "RD_MODE" && end_addr_reached) begin
next_state = TEST_MEM;
mode_load_o = 1'b1;
run_traffic = 1'b1;
load_seed_o = 1'b1;
end
end
else
begin
next_state = IDLE;
run_traffic = 1'b0;
load_seed_o = 1'b0;
end
end
INIT_MEM_WRITE: begin
if (end_addr_reached && EYE_TEST == "FALSE" )
begin
next_state = TEST_MEM;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
run_traffic = 1'b1;
end
else
begin
next_state = INIT_MEM_WRITE;
run_traffic = 1'b1;
mode_load_o = 1'b0;
load_seed_o = 1'b0;
if (EYE_TEST == "TRUE")
addr_mode = FIXED_ADDR;
else if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
addr_mode = 'b0;
else
addr_mode = SEQUENTIAL_ADDR;
end
end
INIT_MEM_READ: begin
if (end_addr_reached )
begin
next_state = TEST_MEM;
mode_load_o = 1'b1;
load_seed_o = 1'b1;
end
else
begin
next_state = INIT_MEM_READ;
run_traffic = 1'b0;
mode_load_o = 1'b0;
load_seed_o = 1'b0;
end
end
TEST_MEM: begin
if (cmp_error)
next_state = CMP_ERROR;
else
next_state = TEST_MEM;
run_traffic = 1'b1;
if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE")
fixed_instr_o = WR_INSTR;
else if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE")
fixed_instr_o = RD_INSTR;
else if (PORT_MODE == "RD_MODE")
fixed_instr_o = RD_INSTR;
else if( PORT_MODE == "WR_MODE")
fixed_instr_o = WR_INSTR;
if (FAMILY == "VIRTEX6")
fixed_bl_o = fix_bl_value;
else if ((data_mode_o == 3'b111) && (FAMILY == "SPARTAN6"))
fixed_bl_o = 64; // Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
else
fixed_bl_o = fix_bl_value;
bl_mode_o = bl_mode_sel;//FIXED_BL_MODE;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE;
if (bl_mode_o == PRBS_BL_MODE)
addr_mode = PRBS_ADDR;
else
addr_mode = addr_mode_sel;
if(PORT_MODE == "BI_MODE") begin
if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
instr_mode_o = BRAM_INSTR_MODE;
else
instr_mode_o = test_mem_instr_mode;//R_RP_W_WP_REF_INSTR_MODE;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;//
end
else if (PORT_MODE == "RD_MODE" || PORT_MODE == "WR_MODE") begin
instr_mode_o = FIXED_INSTR_MODE;
end
end
CMP_ERROR:
begin
next_state = CMP_ERROR;
bl_mode_o = bl_mode_sel;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE;
fixed_instr_o = RD_INSTR;
addr_mode = SEQUENTIAL_ADDR;//PRBS_ADDR;//PRBS_ADDR;//PRBS_ADDR;//SEQUENTIAL_ADDR;
if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
instr_mode_o = BRAM_INSTR_MODE;//
else
instr_mode_o = test_mem_instr_mode;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;//
run_traffic = 1'b1; // ?? keep it running or stop if error happened
end
default:
begin
next_state = IDLE;
//run_traffic = 1'b0;
end
endcase
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 3
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.1" *)
(* CHECK_LICENSE_TYPE = "opl3_cpu_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "opl3_cpu_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CH\
ECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C\
_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=false,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module opl3_cpu_processing_system7_0_0 (
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
SDIO0_WP,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *)
input wire I2C0_SDA_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *)
output wire I2C0_SDA_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *)
output wire I2C0_SDA_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *)
input wire I2C0_SCL_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *)
output wire I2C0_SCL_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *)
output wire I2C0_SCL_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *)
input wire SDIO0_WP;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("false"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(I2C0_SDA_I),
.I2C0_SDA_O(I2C0_SDA_O),
.I2C0_SDA_T(I2C0_SDA_T),
.I2C0_SCL_I(I2C0_SCL_I),
.I2C0_SCL_O(I2C0_SCL_O),
.I2C0_SCL_T(I2C0_SCL_T),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(SDIO0_WP),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(),
.TTC0_WAVE1_OUT(),
.TTC0_WAVE2_OUT(),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_MATLAB_Function_block3.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_MATLAB_Function_block3
// Source Path: controllerHdl/MATLAB Function
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_MATLAB_Function_block3
(
CLK_IN,
reset,
enb_1_2000_0,
u,
y
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input signed [18:0] u; // sfix19_En14
output signed [18:0] y; // sfix19_En14
reg signed [18:0] y_1; // sfix19_En14
reg sel;
reg [15:0] count_n; // ufix16
reg [15:0] count_p; // ufix16
reg signed [18:0] u_n1; // sfix19
reg signed [18:0] u_filter_p; // sfix19
reg signed [18:0] u_filter_n; // sfix19
reg sel_next;
reg [15:0] count_n_next; // ufix16
reg [15:0] count_p_next; // ufix16
reg signed [18:0] u_n1_next; // sfix19_En14
reg signed [18:0] u_filter_p_next; // sfix19_En14
reg signed [18:0] u_filter_n_next; // sfix19_En14
reg signed [37:0] a1_1; // sfix38_En28
reg signed [37:0] b1_1; // sfix38_En28
reg signed [37:0] c1_1; // sfix38_En28
reg signed [37:0] a1_0_1; // sfix38_En28
reg signed [37:0] b1_0_1; // sfix38_En28
reg signed [37:0] c1_0_1; // sfix38_En28
reg sel_temp_1;
reg signed [18:0] u_filter_p_temp_1; // sfix19_En14
reg signed [18:0] u_filter_n_temp_1; // sfix19_En14
always @(posedge CLK_IN)
begin : MATLAB_Function_process
if (reset == 1'b1) begin
sel <= 1'b0;
u_n1 <= 19'sb0000000000000000000;
u_filter_p <= 19'sb0000000000000000000;
u_filter_n <= 19'sb0000000000000000000;
count_n <= 16'b0000000000000000;
count_p <= 16'b0000000000000000;
end
else if (enb_1_2000_0) begin
sel <= sel_next;
count_n <= count_n_next;
count_p <= count_p_next;
u_n1 <= u_n1_next;
u_filter_p <= u_filter_p_next;
u_filter_n <= u_filter_n_next;
end
end
always @(u, sel, count_n, count_p, u_n1, u_filter_p, u_filter_n) begin
sel_temp_1 = sel;
u_filter_p_temp_1 = u_filter_p;
u_filter_n_temp_1 = u_filter_n;
count_n_next = count_n;
count_p_next = count_p;
//MATLAB Function 'MATLAB Function': '<S4>:1'
if ((u < 19'sb0000000000000000000) && (u_n1 > 19'sb0000000000000000000)) begin
//'<S4>:1:25'
sel_temp_1 = count_p > count_n;
//'<S4>:1:26'
count_n_next = 16'b0000000000000000;
//'<S4>:1:27'
count_p_next = 16'b0000000000000000;
end
else if (u > 19'sb0000000000000000000) begin
//'<S4>:1:31'
a1_0_1 = 14336 * u_filter_p;
b1_0_1 = {{8{u[18]}}, {u, 11'b00000000000}};
c1_0_1 = a1_0_1 + b1_0_1;
if (((c1_0_1[37] == 1'b0) && (c1_0_1[36:32] != 5'b00000)) || ((c1_0_1[37] == 1'b0) && (c1_0_1[32:14] == 19'sb0111111111111111111))) begin
u_filter_p_temp_1 = 19'sb0111111111111111111;
end
else if ((c1_0_1[37] == 1'b1) && (c1_0_1[36:32] != 5'b11111)) begin
u_filter_p_temp_1 = 19'sb1000000000000000000;
end
else begin
u_filter_p_temp_1 = c1_0_1[32:14] + $signed({1'b0, c1_0_1[13]});
end
//'<S4>:1:32'
count_p_next = count_p + 1;
end
else begin
//'<S4>:1:34'
a1_1 = 14336 * u_filter_n;
b1_1 = {{8{u[18]}}, {u, 11'b00000000000}};
c1_1 = a1_1 + b1_1;
if (((c1_1[37] == 1'b0) && (c1_1[36:32] != 5'b00000)) || ((c1_1[37] == 1'b0) && (c1_1[32:14] == 19'sb0111111111111111111))) begin
u_filter_n_temp_1 = 19'sb0111111111111111111;
end
else if ((c1_1[37] == 1'b1) && (c1_1[36:32] != 5'b11111)) begin
u_filter_n_temp_1 = 19'sb1000000000000000000;
end
else begin
u_filter_n_temp_1 = c1_1[32:14] + $signed({1'b0, c1_1[13]});
end
//'<S4>:1:35'
count_n_next = count_n + 1;
end
//'<S4>:1:39'
u_n1_next = u;
if (sel_temp_1) begin
//'<S4>:1:40'
//'<S4>:1:41'
y_1 = u_filter_p_temp_1;
end
else begin
//'<S4>:1:43'
y_1 = u_filter_n_temp_1;
end
sel_next = sel_temp_1;
u_filter_p_next = u_filter_p_temp_1;
u_filter_n_next = u_filter_n_temp_1;
end
assign y = y_1;
endmodule // controllerHdl_MATLAB_Function_block3
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx2mb_sm.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* pcx2mb_sm.v: State machine to control shifting out of data.
*
* NOTE: Pipeline stages from SPARC point of view are
* PQ Initial Request
* PA Data sent for request.
* PX Grant returned, Request sent to cache
* PX2 Data sent to cache
*
* $Id: pcx2mb_sm.v,v 1.1 2007/06/30 00:23:40 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module pcx2mb_sm (
// Outputs
load_data,
shift_data,
entry1_active,
pcx_fsl_m_control,
pcx_fsl_m_write,
pcx_spc_grant_px,
// Inputs
rclk,
reset_l,
any_req_pq,
any_req_pa,
spc_pcx_atom_pq,
entry1_dest,
entry2_active,
entry2_atom,
fsl_pcx_m_full
);
`ifdef PCX2MB_5_BIT_REQ
parameter PCX_REQ_WIDTH = 5;
`else
parameter PCX_REQ_WIDTH = 2;
`endif
parameter PCX_GEAR_RATIO = (((`PCX_WIDTH+PCX_REQ_WIDTH)/`FSL_D_WIDTH)+1);
parameter PCX_FSL_EXTRA_BITS = (`FSL_D_WIDTH * PCX_GEAR_RATIO) -
(`PCX_WIDTH+PCX_REQ_WIDTH+1);
parameter [2:0] PCX_START_COUNT = PCX_GEAR_RATIO - 1;
parameter pFLS_IDLE = 0,
pFLS_LOAD = 1,
pFLS_SHIFT = 2,
pFLS_LDWAIT = 3,
pFLS_WAIT = 4;
parameter FLS_IDLE = 5'b00001,
FLS_LOAD = 5'b00010,
FLS_SHIFT = 5'b00100,
FLS_LDWAIT = 5'b01000,
FLS_WAIT = 5'b10000;
output load_data;
output shift_data;
output entry1_active;
output pcx_fsl_m_control;
output pcx_fsl_m_write;
output [4:0] pcx_spc_grant_px;
input rclk;
input reset_l;
input any_req_pq;
input any_req_pa;
input spc_pcx_atom_pq;
input [4:0] entry1_dest;
input entry2_active;
input entry2_atom;
input fsl_pcx_m_full;
wire pcx_fsl_m_control;
wire pcx_fsl_m_write;
// State machine to control the shifting out of the data.
reg [4:0] curr_state;
reg [4:0] next_state;
reg [2:0] curr_count;
reg [2:0] next_count;
reg data_write;
reg next_data_write;
reg [4:0] pcx_spc_grant_px;
reg next_grant;
reg atomic_first; // First part of an atomic txn
reg atomic_second; // Second part of an atomic txn
reg next_atomic_first;
reg next_atomic_second;
reg atomic_second_d1;
reg [4:0] entry1_dest_d1;
reg data_control;
reg next_control;
always @ (posedge rclk) begin // Start with a synchronous reset
if (!reset_l) begin
curr_state <= 5'b00001;
curr_count <= 3'b000;
data_write <= 1'b0;
pcx_spc_grant_px <= 5'b00000;
atomic_first <= 1'b0;
atomic_second <= 1'b0;
data_control <= 1'b0;
end
else begin
curr_state <= next_state;
curr_count <= next_count;
data_write <= next_data_write;
pcx_spc_grant_px <= {5{next_grant}} & entry1_dest_d1;
atomic_first <= next_atomic_first;
atomic_second <= next_atomic_second;
data_control <= next_control;
end
end
always @(posedge rclk) begin
atomic_second_d1 <= atomic_second;
entry1_dest_d1 <= entry1_dest;
end
always @ (curr_state or any_req_pq or any_req_pa or entry2_active or
curr_count or spc_pcx_atom_pq or atomic_first or atomic_second or
atomic_second_d1 or fsl_pcx_m_full or data_write or entry2_atom)
begin
case (1)
curr_state[pFLS_IDLE] : begin
next_count = 3'b000;
next_data_write = 1'b0;
next_grant = atomic_second_d1;
next_atomic_second = 1'b0;
next_control = 1'b0;
if (any_req_pq) begin
next_state = FLS_LOAD;
next_atomic_first = spc_pcx_atom_pq;
end
else begin
next_state = FLS_IDLE;
next_atomic_first = 1'b0;
end
end
curr_state[pFLS_LOAD] : begin
next_state = FLS_SHIFT;
next_count = PCX_START_COUNT;
next_grant = atomic_second_d1;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b1;
end
curr_state[pFLS_SHIFT] : begin
if (fsl_pcx_m_full) begin
next_state = FLS_SHIFT;
next_count = curr_count;
next_grant = atomic_second_d1 && !atomic_second;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = (curr_count == PCX_START_COUNT);
end
else if (curr_count > 3'd1) begin
next_state = FLS_SHIFT;
next_count = curr_count-3'b1;
next_grant = atomic_second_d1 && !atomic_second;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b0;
end
else if (entry2_active || any_req_pa || any_req_pq) begin
next_state = FLS_LDWAIT;
next_count = curr_count-3'b1;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b0;
end
else begin
next_state = FLS_WAIT;
next_count = curr_count-3'b1;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b0;
end
end
// The last beat of the transaction, and a load is ready
// But we can't load until we know the last beat of the last
// txn has been accepted
curr_state[pFLS_LDWAIT] : begin
if (fsl_pcx_m_full) begin
next_state = FLS_LDWAIT;
next_count = curr_count;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
next_control = 1'b0;
end
else begin
next_state = FLS_SHIFT;
next_count = PCX_START_COUNT;
next_grant = !atomic_first;
next_atomic_first = entry2_atom;
next_atomic_second = atomic_first;
next_data_write = 1'b1;
next_control = 1'b1;
end
end
// The last beat of the transaction: Don't go to IDLE or
// give grant to SPC until we know the beat was accepted.
curr_state[pFLS_WAIT] : begin
next_control = 1'b0;
if (fsl_pcx_m_full &&
(entry2_active || any_req_pa || any_req_pq) ) begin
next_state = FLS_LDWAIT;
next_count = curr_count;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
end
else if (fsl_pcx_m_full) begin
next_state = FLS_WAIT;
next_count = curr_count;
next_grant = 1'b0;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_data_write = 1'b1;
end
else if (entry2_active || any_req_pa || any_req_pq) begin
next_state = FLS_LOAD;
next_grant = !atomic_first; // No grant on first atomic
next_atomic_first = 1'b0;
next_atomic_second = atomic_first;
next_count = curr_count-3'b1;
next_data_write = 1'b0;
end
else begin
next_state = FLS_IDLE;
next_grant = 1'b1;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
next_count = curr_count-3'b1;
next_data_write = 1'b0;
end
end
default : begin
next_state = FLS_IDLE;
next_data_write = 1'b0;
next_count = 3'b000;
next_grant = 1'b0;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
next_control = 1'b0;
end
endcase
end
// Outputs of the state machine
assign load_data = curr_state[pFLS_LOAD] ||
(curr_state[pFLS_LDWAIT] && !fsl_pcx_m_full);
assign shift_data = curr_state[pFLS_SHIFT] && !fsl_pcx_m_full;
assign entry1_active = !curr_state[pFLS_IDLE] ||
(data_write && fsl_pcx_m_full);
assign pcx_fsl_m_write = data_write && !fsl_pcx_m_full;
assign pcx_fsl_m_control = data_control;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NAND3_PP_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR3_PP_SYMBOL_V
`define SKY130_FD_SC_HS__XNOR3_PP_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xnor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR3_PP_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
// ----------------------------------------------------------------------
// Filename: Filename: tx_multiplexer.v
// Version: Version: 1.0
// Verilog Standard: Verilog-2005
// Description: the TX Multiplexer services read and write requests from
// RIFFA channels in round robin order.
// Author: Dustin Richmond (@darichmond)
// ----------------------------------------------------------------------
`include "trellis.vh"
module tx_multiplexer
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_TAG_WIDTH = 5,
parameter C_VENDOR = "ALTERA",
parameter C_DEPTH_PACKETS = 10
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
output [C_NUM_CHNL-1:0] WR_SENT, // Write Reuqest has been sent to the core
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY,
input TXR_SENT);
`include "functions.vh"
wire [C_NUM_CHNL-1:0] wAckRdData;
wire wAckValid;
reg [C_NUM_CHNL-1:0] rAckWrData; // Registered fifo input (only write acks)
reg [C_NUM_CHNL-1:0] rAckRdData; // Registered fifo output (only write acks)
reg rAckWrEn,_rAckWrEn; // Fifo write enable (RD or WR_ACK)
reg rAckRdEn; // Fifo read enable (TXR_SENT)
always @(*) begin
_rAckWrEn = (WR_ACK != 0) | (RD_ACK != 0);
end
always @(posedge CLK) begin
rAckWrData <= WR_ACK;
rAckWrEn <= _rAckWrEn;
end
always @(posedge CLK) begin
rAckRdEn <= TXR_SENT;
if(rAckRdEn & wAckValid) begin
rAckRdData <= wAckRdData;//
end else begin
rAckRdData <= 0;
end
end
assign WR_SENT = rAckRdData;
fifo
#(// Parameters
.C_WIDTH (C_NUM_CHNL),
.C_DEPTH (C_DEPTH_PACKETS*8), // This is an extremely conservative estimate...
.C_DELAY (0)
/*AUTOINSTPARAM*/)
req_ack_fifo
(// Outputs
.WR_READY (),
.RD_DATA (wAckRdData),
.RD_VALID (wAckValid),
// Inputs
.WR_DATA (rAckWrData),
.WR_VALID (rAckWrEn),
.RD_READY (rAckRdEn),
.RST (RST_IN),
/*AUTOINST*/
// Inputs
.CLK (CLK));
generate
if(C_PCI_DATA_WIDTH == 32) begin
tx_multiplexer_32
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR))
tx_mux
(/*AUTOINST*/
// Outputs
.WR_DATA_REN (WR_DATA_REN[C_NUM_CHNL-1:0]),
.WR_ACK (WR_ACK[C_NUM_CHNL-1:0]),
.RD_ACK (RD_ACK[C_NUM_CHNL-1:0]),
.INT_TAG (INT_TAG[5:0]),
.INT_TAG_VALID (INT_TAG_VALID),
.TX_ENG_RD_REQ_SENT (TX_ENG_RD_REQ_SENT),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_REQ (WR_REQ[C_NUM_CHNL-1:0]),
.WR_ADDR (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.RD_REQ (RD_REQ[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (EXT_TAG[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (EXT_TAG_VALID),
.RXBUF_SPACE_AVAIL (RXBUF_SPACE_AVAIL),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY));
end else if(C_PCI_DATA_WIDTH == 64) begin
tx_multiplexer_64
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR))
tx_mux
(/*AUTOINST*/
// Outputs
.WR_DATA_REN (WR_DATA_REN[C_NUM_CHNL-1:0]),
.WR_ACK (WR_ACK[C_NUM_CHNL-1:0]),
.RD_ACK (RD_ACK[C_NUM_CHNL-1:0]),
.INT_TAG (INT_TAG[5:0]),
.INT_TAG_VALID (INT_TAG_VALID),
.TX_ENG_RD_REQ_SENT (TX_ENG_RD_REQ_SENT),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_REQ (WR_REQ[C_NUM_CHNL-1:0]),
.WR_ADDR (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.RD_REQ (RD_REQ[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (EXT_TAG[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (EXT_TAG_VALID),
.RXBUF_SPACE_AVAIL (RXBUF_SPACE_AVAIL),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY));
end else if(C_PCI_DATA_WIDTH == 128) begin
tx_multiplexer_128
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR))
tx_mux_128_inst
(/*AUTOINST*/
// Outputs
.WR_DATA_REN (WR_DATA_REN[C_NUM_CHNL-1:0]),
.WR_ACK (WR_ACK[C_NUM_CHNL-1:0]),
.RD_ACK (RD_ACK[C_NUM_CHNL-1:0]),
.INT_TAG (INT_TAG[5:0]),
.INT_TAG_VALID (INT_TAG_VALID),
.TX_ENG_RD_REQ_SENT (TX_ENG_RD_REQ_SENT),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_REQ (WR_REQ[C_NUM_CHNL-1:0]),
.WR_ADDR (WR_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (WR_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (WR_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.RD_REQ (RD_REQ[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (RD_SG_CHNL[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (RD_ADDR[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (RD_LEN[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (EXT_TAG[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (EXT_TAG_VALID),
.RXBUF_SPACE_AVAIL (RXBUF_SPACE_AVAIL),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY));
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "../common/")
// End:
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*
* SVN revision information:
* $Rev:: $:
* $Author:: $:
* $Date:: $:
*/
module SiLibUSB (input FCLK);
reg RD_B;
reg WR_B;
tri [7:0] DATA;
reg [15:0] ADD;
reg FREAD;
reg FSTROBE;
reg FMODE;
tri [7:0] FD;
reg [7:0] DATA_T;
assign DATA = ~WR_B ? DATA_T : 8'bzzzz_zzzz;
initial begin
RD_B = 1;
WR_B = 1;
ADD = 0;
FREAD = 0;
FSTROBE = 0;
FMODE = 0;
end
task ReadExternal;
input [15:0] ADDIN;
output [7:0] DATAOUT;
begin
RD_B = 1;
ADD = 16'hxxxx;
repeat (5)
@(posedge FCLK);
@(posedge FCLK);
ADD = ADDIN + 16'h4000;
@(posedge FCLK);
RD_B = 0;
@(posedge FCLK);
RD_B = 0;
@(posedge FCLK);
DATAOUT = DATA;
RD_B = 1;
@(posedge FCLK);
RD_B = 1;
ADD = 16'hxxxx;
repeat (5)
@(posedge FCLK);
end
endtask
task WriteExternal;
input [15:0] ADDIN;
input [7:0] DATAIN;
begin
WR_B = 1;
ADD = 16'hxxxx;
DATA_T = 16'hxxxx;
repeat (5)
@(posedge FCLK);
@(posedge FCLK);
ADD = ADDIN + 16'h4000;
DATA_T = DATAIN;
@(posedge FCLK);
WR_B = 0;
@(posedge FCLK);
WR_B = 0;
@(posedge FCLK);
WR_B = 1;
@(posedge FCLK);
WR_B = 1;
ADD = 16'hxxxx;
DATA_T = 16'hxxxx;
repeat (5)
@(posedge FCLK);
end
endtask
task FastBlockRead;
output [7:0] DATAOUT;
begin
@(posedge FCLK);
@(posedge FCLK); #1 FREAD <= 1; FSTROBE <= 1;
@(posedge FCLK)
DATAOUT <= FD;
#1 FREAD <= 0; FSTROBE = 0;
@(posedge FCLK);
end
endtask
endmodule
|
`include "assert.vh"
`include "SuperStack.vh"
module SuperStack_tb();
parameter WIDTH = 8;
parameter DEPTH = 1; // frames (exponential)
localparam MAX_STACK = (1 << DEPTH+1) - 1;
reg clk = 0;
reg reset;
reg [ 2:0] op;
reg [WIDTH-1:0] data;
reg [DEPTH :0] offset;
reg [DEPTH :0] underflow_limit=0;
reg [DEPTH :0] upper_limit=0;
wire [DEPTH :0] index;
wire [WIDTH-1:0] out;
wire [WIDTH-1:0] out1;
wire [WIDTH-1:0] out2;
wire [WIDTH-1:0] getter;
wire [ 1:0] status;
wire [ 1:0] error;
SuperStack #(
.WIDTH(WIDTH),
.DEPTH(DEPTH),
.ZEROED_SLICES(1)
)
dut(
.clk(clk),
.reset(reset),
.op(op),
.data(data),
.offset(offset),
.underflow_limit(underflow_limit),
.upper_limit(upper_limit),
.lower_limit(2'b0),
.dropTos(1'b0),
.index(index),
.out(out),
.out1(out1),
.out2(out2),
.getter(getter),
.status(status),
.error(error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("SuperStack_tb.vcd");
$dumpvars(0, SuperStack_tb);
// `status` is `empty` by default
`assert(status, `EMPTY);
// Underflow
op <= `POP;
data <= 0;
#2
`assert(error, `UNDERFLOW);
// Push
op <= `PUSH;
data <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h00);
op <= `PUSH;
data <= 1;
#2
`assert(status, `NONE);
`assert(out , 8'h01);
`assert(out1 , 8'h00);
op <= `PUSH;
data <= 2;
#2
`assert(status, `FULL);
`assert(out , 8'h02);
`assert(out1 , 8'h01);
`assert(out2 , 8'h00);
// Top of Stack
op <= `NONE;
#2
`assert(status, `FULL);
`assert(out , 8'h02);
`assert(out1 , 8'h01);
`assert(out2 , 8'h00);
// Overflow
op <= `PUSH;
data <= 3;
#2
`assert(error, `OVERFLOW);
`assert(out , 8'h02);
`assert(out1 , 8'h01);
`assert(out2 , 8'h00);
// Pop
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h01);
`assert(out1 , 8'h00);
op <= `POP;
data <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h00);
op <= `POP;
data <= 0;
#2
`assert(status, `EMPTY);
// Replace
op <= `REPLACE;
data <= 4;
#2
`assert(error, `UNDERFLOW);
op <= `PUSH;
data <= 5;
#2
`assert(status, `NONE);
`assert(out , 8'h05);
op <= `REPLACE;
data <= 6;
#2
`assert(status, `NONE);
`assert(out , 8'h06);
op <= `NONE;
#2
`assert(status, `NONE);
`assert(out , 8'h06);
// Reset
reset <= 1;
#2
reset <= 0;
`assert(status, `EMPTY);
`assert(index , 0);
//
// Underflow limit
//
// Underflow after change limit
op <= `NONE;
underflow_limit <= 1;
#2
`assert(status, `UNDERFLOW);
// `assert(out , 8'h06);
`assert(index , 0);
// Push data while we are under the underflow limit...
// and get an empty stack! Magic! :-P
op <= `PUSH;
data <= 8;
#2
`assert(status, `EMPTY);
`assert(out , 8'h08);
`assert(index , 1);
// Reset with underflow limit set
op <= `PUSH;
data <= 9;
#2
`assert(status, `NONE);
`assert(out , 8'h09);
`assert(out1 , 8'h08);
`assert(index , 2);
op <= `INDEX_RESET;
offset <= 1;
#2
`assert(status, `EMPTY);
`assert(out , 8'h08);
`assert(index , 1);
// Get underflow error when underflow limit is not zero (data is protected)
op <= `POP;
data <= 0;
#2
op <= `NONE;
`assert(error, `UNDERFLOW);
`assert(out , 8'h08);
`assert(index, 1);
// Reset underflow limit, and now we can access the data
underflow_limit <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h08);
`assert(index , 1);
// Get empty when index get zero
op <= `POP;
data <= 0;
#2
`assert(status, `EMPTY);
`assert(index , 0);
// Underflow reset push
op <= `INDEX_RESET_AND_PUSH;
data <= 10;
underflow_limit <= 2;
offset <= 0;
#2
`assert(status, `UNDERFLOW);
`assert(out , 8'h0a);
`assert(index , 1);
op <= `INDEX_RESET_AND_PUSH;
data <= 11;
underflow_limit <= 0;
#2
`assert(status, `NONE);
`assert(out , 8'h0b);
`assert(index , 1);
// Underfow set
op <= `UNDERFLOW_SET;
data <= 12;
underflow_limit <= 1;
offset <= 0;
#2
`assert(error, `BAD_OFFSET);
`assert(out , 8'h0b);
`assert(index, 1);
upper_limit <= 1;
#2
`assert(status, `EMPTY);
`assert(out , 8'h0c);
`assert(index , 1);
op <= `NONE;
#2
`assert(status, `EMPTY);
`assert(index , 1);
op <= `PUSH;
data <= 13;
#2
`assert(status, `NONE);
`assert(out , 8'h0d);
`assert(index , 2);
// Underfow get
offset <= 0;
op <= `UNDERFLOW_GET;
#2
`assert(status, `NONE);
`assert(getter, 8'h0c);
`assert(index , 2);
offset <= 1;
op <= `UNDERFLOW_GET;
#2
`assert(error, `BAD_OFFSET);
`assert(index, 2);
// Reset index over current one and fill with zeroes
op <= `INDEX_RESET;
offset <= 3;
#2
`assert(status, `FULL);
`assert(out , 8'h00);
`assert(out1 , 8'h0d);
`assert(out2 , 8'h0c);
`assert(index , 3);
$finish;
end
endmodule
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 1-31-2017
*/
module jt12_sh24 #(parameter width=5 )
(
input clk,
input clk_en /* synthesis direct_enable */,
input [width-1:0] din,
output reg [width-1:0] st1,
output reg [width-1:0] st2,
output reg [width-1:0] st3,
output reg [width-1:0] st4,
output reg [width-1:0] st5,
output reg [width-1:0] st6,
output reg [width-1:0] st7,
output reg [width-1:0] st8,
output reg [width-1:0] st9,
output reg [width-1:0] st10,
output reg [width-1:0] st11,
output reg [width-1:0] st12,
output reg [width-1:0] st13,
output reg [width-1:0] st14,
output reg [width-1:0] st15,
output reg [width-1:0] st16,
output reg [width-1:0] st17,
output reg [width-1:0] st18,
output reg [width-1:0] st19,
output reg [width-1:0] st20,
output reg [width-1:0] st21,
output reg [width-1:0] st22,
output reg [width-1:0] st23,
output reg [width-1:0] st24
);
always @(posedge clk) if(clk_en) begin
st24<= st23;
st23<= st22;
st22<= st21;
st21<= st20;
st20<= st19;
st19<= st18;
st18<= st17;
st17<= st16;
st16<= st15;
st15<= st14;
st14<= st13;
st13<= st12;
st12<= st11;
st11<= st10;
st10<= st9;
st9 <= st8;
st8 <= st7;
st7 <= st6;
st6 <= st5;
st5 <= st4;
st4 <= st3;
st3 <= st2;
st2 <= st1;
st1 <= din;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:29:17 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, underflow_flag_mult, overflow_flag_addsubt,
underflow_flag_addsubt, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_operation_out, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_exp_operation_A_S,
FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag,
FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_intAS, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1483, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648,
n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829,
n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839,
n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849,
n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859,
n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889,
n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899,
n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909,
n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919,
n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929,
n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939,
n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949,
n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959,
n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969,
n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979,
n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989,
n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999,
n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009,
n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079,
n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089,
n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099,
n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109,
n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119,
n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129,
n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139,
n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149,
n2150, n2151, n2193, DP_OP_26J210_123_9022_n18,
DP_OP_26J210_123_9022_n17, DP_OP_26J210_123_9022_n16,
DP_OP_26J210_123_9022_n15, DP_OP_26J210_123_9022_n14,
DP_OP_26J210_123_9022_n8, DP_OP_26J210_123_9022_n7,
DP_OP_26J210_123_9022_n6, DP_OP_26J210_123_9022_n5,
DP_OP_26J210_123_9022_n4, DP_OP_26J210_123_9022_n3,
DP_OP_26J210_123_9022_n2, DP_OP_26J210_123_9022_n1,
DP_OP_234J210_126_8543_n22, DP_OP_234J210_126_8543_n21,
DP_OP_234J210_126_8543_n20, DP_OP_234J210_126_8543_n19,
DP_OP_234J210_126_8543_n18, DP_OP_234J210_126_8543_n17,
DP_OP_234J210_126_8543_n16, DP_OP_234J210_126_8543_n15,
DP_OP_234J210_126_8543_n9, DP_OP_234J210_126_8543_n8,
DP_OP_234J210_126_8543_n7, DP_OP_234J210_126_8543_n6,
DP_OP_234J210_126_8543_n5, DP_OP_234J210_126_8543_n4,
DP_OP_234J210_126_8543_n3, DP_OP_234J210_126_8543_n2,
DP_OP_234J210_126_8543_n1, intadd_477_CI, intadd_477_SUM_2_,
intadd_477_SUM_1_, intadd_477_SUM_0_, intadd_477_n3, intadd_477_n2,
intadd_477_n1, intadd_478_CI, intadd_478_SUM_2_, intadd_478_SUM_1_,
intadd_478_SUM_0_, intadd_478_n3, intadd_478_n2, intadd_478_n1,
DP_OP_453J210_122_681_n2030, DP_OP_453J210_122_681_n788,
DP_OP_453J210_122_681_n787, DP_OP_453J210_122_681_n786,
DP_OP_453J210_122_681_n785, DP_OP_453J210_122_681_n784,
DP_OP_453J210_122_681_n783, DP_OP_453J210_122_681_n782,
DP_OP_453J210_122_681_n781, DP_OP_453J210_122_681_n780,
DP_OP_453J210_122_681_n779, DP_OP_453J210_122_681_n778,
DP_OP_453J210_122_681_n777, DP_OP_453J210_122_681_n776,
DP_OP_453J210_122_681_n775, DP_OP_453J210_122_681_n774,
DP_OP_453J210_122_681_n773, DP_OP_453J210_122_681_n772,
DP_OP_453J210_122_681_n771, DP_OP_453J210_122_681_n770,
DP_OP_453J210_122_681_n769, DP_OP_453J210_122_681_n768,
DP_OP_453J210_122_681_n767, DP_OP_453J210_122_681_n766,
DP_OP_453J210_122_681_n667, DP_OP_453J210_122_681_n535,
DP_OP_453J210_122_681_n534, DP_OP_453J210_122_681_n531,
DP_OP_453J210_122_681_n530, DP_OP_453J210_122_681_n529,
DP_OP_453J210_122_681_n528, DP_OP_453J210_122_681_n527,
DP_OP_453J210_122_681_n526, DP_OP_453J210_122_681_n525,
DP_OP_453J210_122_681_n524, DP_OP_453J210_122_681_n522,
DP_OP_453J210_122_681_n518, DP_OP_453J210_122_681_n517,
DP_OP_453J210_122_681_n516, DP_OP_453J210_122_681_n515,
DP_OP_453J210_122_681_n514, DP_OP_453J210_122_681_n513,
DP_OP_453J210_122_681_n512, DP_OP_453J210_122_681_n511,
DP_OP_453J210_122_681_n510, DP_OP_453J210_122_681_n505,
DP_OP_453J210_122_681_n504, DP_OP_453J210_122_681_n503,
DP_OP_453J210_122_681_n502, DP_OP_453J210_122_681_n501,
DP_OP_453J210_122_681_n500, DP_OP_453J210_122_681_n499,
DP_OP_453J210_122_681_n498, DP_OP_453J210_122_681_n497,
DP_OP_453J210_122_681_n496, DP_OP_453J210_122_681_n495,
DP_OP_453J210_122_681_n494, DP_OP_453J210_122_681_n493,
DP_OP_453J210_122_681_n492, DP_OP_453J210_122_681_n488,
DP_OP_453J210_122_681_n487, DP_OP_453J210_122_681_n486,
DP_OP_453J210_122_681_n485, DP_OP_453J210_122_681_n483,
DP_OP_453J210_122_681_n482, DP_OP_453J210_122_681_n481,
DP_OP_453J210_122_681_n480, DP_OP_453J210_122_681_n475,
DP_OP_453J210_122_681_n474, DP_OP_453J210_122_681_n473,
DP_OP_453J210_122_681_n472, DP_OP_453J210_122_681_n471,
DP_OP_453J210_122_681_n470, DP_OP_453J210_122_681_n468,
DP_OP_453J210_122_681_n467, DP_OP_453J210_122_681_n466,
DP_OP_453J210_122_681_n464, DP_OP_453J210_122_681_n463,
DP_OP_453J210_122_681_n462, DP_OP_453J210_122_681_n456,
DP_OP_453J210_122_681_n455, DP_OP_453J210_122_681_n454,
DP_OP_453J210_122_681_n452, DP_OP_453J210_122_681_n451,
DP_OP_453J210_122_681_n450, DP_OP_453J210_122_681_n448,
DP_OP_453J210_122_681_n442, DP_OP_453J210_122_681_n441,
DP_OP_453J210_122_681_n438, DP_OP_453J210_122_681_n437,
DP_OP_453J210_122_681_n435, DP_OP_453J210_122_681_n425,
DP_OP_453J210_122_681_n424, DP_OP_453J210_122_681_n423,
DP_OP_453J210_122_681_n422, DP_OP_453J210_122_681_n421,
DP_OP_453J210_122_681_n420, DP_OP_453J210_122_681_n419,
DP_OP_453J210_122_681_n418, DP_OP_453J210_122_681_n417,
DP_OP_453J210_122_681_n416, DP_OP_453J210_122_681_n415,
DP_OP_453J210_122_681_n414, DP_OP_453J210_122_681_n413,
DP_OP_453J210_122_681_n412, DP_OP_453J210_122_681_n411,
DP_OP_453J210_122_681_n410, DP_OP_453J210_122_681_n409,
DP_OP_453J210_122_681_n408, DP_OP_453J210_122_681_n407,
DP_OP_453J210_122_681_n406, DP_OP_453J210_122_681_n405,
DP_OP_453J210_122_681_n404, DP_OP_453J210_122_681_n401,
DP_OP_453J210_122_681_n400, DP_OP_453J210_122_681_n399,
DP_OP_453J210_122_681_n398, DP_OP_453J210_122_681_n397,
DP_OP_453J210_122_681_n396, DP_OP_453J210_122_681_n395,
DP_OP_453J210_122_681_n394, DP_OP_453J210_122_681_n393,
DP_OP_453J210_122_681_n392, DP_OP_453J210_122_681_n391,
DP_OP_453J210_122_681_n390, DP_OP_453J210_122_681_n389,
DP_OP_453J210_122_681_n387, DP_OP_453J210_122_681_n386,
DP_OP_453J210_122_681_n385, DP_OP_453J210_122_681_n384,
DP_OP_453J210_122_681_n383, DP_OP_453J210_122_681_n382,
DP_OP_453J210_122_681_n381, DP_OP_453J210_122_681_n380,
DP_OP_453J210_122_681_n379, DP_OP_453J210_122_681_n378,
DP_OP_453J210_122_681_n377, DP_OP_453J210_122_681_n376,
DP_OP_453J210_122_681_n375, DP_OP_453J210_122_681_n373,
DP_OP_453J210_122_681_n372, DP_OP_453J210_122_681_n371,
DP_OP_453J210_122_681_n370, DP_OP_453J210_122_681_n369,
DP_OP_453J210_122_681_n368, DP_OP_453J210_122_681_n367,
DP_OP_453J210_122_681_n365, DP_OP_453J210_122_681_n364,
DP_OP_453J210_122_681_n363, DP_OP_453J210_122_681_n362,
DP_OP_453J210_122_681_n361, DP_OP_453J210_122_681_n360,
DP_OP_453J210_122_681_n358, DP_OP_453J210_122_681_n357,
DP_OP_453J210_122_681_n356, DP_OP_453J210_122_681_n355,
DP_OP_453J210_122_681_n354, DP_OP_453J210_122_681_n353,
DP_OP_453J210_122_681_n352, DP_OP_453J210_122_681_n351,
DP_OP_453J210_122_681_n350, DP_OP_453J210_122_681_n349,
DP_OP_453J210_122_681_n348, DP_OP_453J210_122_681_n347,
DP_OP_453J210_122_681_n346, DP_OP_453J210_122_681_n345,
DP_OP_453J210_122_681_n344, DP_OP_453J210_122_681_n343,
DP_OP_453J210_122_681_n342, DP_OP_453J210_122_681_n341,
DP_OP_453J210_122_681_n340, DP_OP_453J210_122_681_n338,
DP_OP_453J210_122_681_n337, DP_OP_453J210_122_681_n336,
DP_OP_453J210_122_681_n335, DP_OP_453J210_122_681_n334,
DP_OP_453J210_122_681_n333, DP_OP_453J210_122_681_n332,
DP_OP_453J210_122_681_n331, DP_OP_453J210_122_681_n330,
DP_OP_453J210_122_681_n329, DP_OP_453J210_122_681_n327,
DP_OP_453J210_122_681_n326, DP_OP_453J210_122_681_n325,
DP_OP_453J210_122_681_n324, DP_OP_453J210_122_681_n323,
DP_OP_453J210_122_681_n322, DP_OP_453J210_122_681_n321,
DP_OP_453J210_122_681_n320, DP_OP_453J210_122_681_n319,
DP_OP_453J210_122_681_n318, DP_OP_453J210_122_681_n317,
DP_OP_453J210_122_681_n316, DP_OP_453J210_122_681_n315,
DP_OP_453J210_122_681_n314, DP_OP_453J210_122_681_n313,
DP_OP_453J210_122_681_n312, DP_OP_453J210_122_681_n311,
DP_OP_453J210_122_681_n310, DP_OP_453J210_122_681_n309,
DP_OP_453J210_122_681_n308, DP_OP_453J210_122_681_n307,
DP_OP_453J210_122_681_n306, DP_OP_453J210_122_681_n305,
DP_OP_453J210_122_681_n304, DP_OP_453J210_122_681_n303,
DP_OP_453J210_122_681_n302, DP_OP_453J210_122_681_n301,
DP_OP_453J210_122_681_n300, DP_OP_453J210_122_681_n299,
DP_OP_453J210_122_681_n298, DP_OP_453J210_122_681_n297,
DP_OP_453J210_122_681_n296, DP_OP_453J210_122_681_n295,
DP_OP_453J210_122_681_n294, DP_OP_453J210_122_681_n293,
DP_OP_453J210_122_681_n292, DP_OP_453J210_122_681_n291,
DP_OP_453J210_122_681_n290, DP_OP_453J210_122_681_n289,
DP_OP_453J210_122_681_n288, DP_OP_453J210_122_681_n287,
DP_OP_453J210_122_681_n286, DP_OP_453J210_122_681_n285,
DP_OP_453J210_122_681_n284, DP_OP_453J210_122_681_n283,
DP_OP_453J210_122_681_n282, DP_OP_453J210_122_681_n281,
DP_OP_453J210_122_681_n280, DP_OP_453J210_122_681_n279,
DP_OP_453J210_122_681_n278, DP_OP_453J210_122_681_n277,
DP_OP_453J210_122_681_n276, DP_OP_453J210_122_681_n275,
DP_OP_453J210_122_681_n274, DP_OP_453J210_122_681_n273,
DP_OP_453J210_122_681_n272, DP_OP_453J210_122_681_n271,
DP_OP_453J210_122_681_n270, DP_OP_453J210_122_681_n269,
DP_OP_453J210_122_681_n268, DP_OP_453J210_122_681_n267,
DP_OP_453J210_122_681_n266, DP_OP_453J210_122_681_n265,
DP_OP_453J210_122_681_n264, DP_OP_453J210_122_681_n263,
DP_OP_453J210_122_681_n262, DP_OP_453J210_122_681_n261,
DP_OP_453J210_122_681_n260, DP_OP_453J210_122_681_n259,
DP_OP_453J210_122_681_n258, DP_OP_453J210_122_681_n257,
DP_OP_453J210_122_681_n256, DP_OP_453J210_122_681_n255,
DP_OP_453J210_122_681_n254, DP_OP_453J210_122_681_n253,
DP_OP_453J210_122_681_n252, DP_OP_453J210_122_681_n251,
DP_OP_453J210_122_681_n250, DP_OP_453J210_122_681_n249,
DP_OP_453J210_122_681_n248, DP_OP_453J210_122_681_n247,
DP_OP_453J210_122_681_n246, DP_OP_453J210_122_681_n245,
DP_OP_453J210_122_681_n244, DP_OP_453J210_122_681_n243,
DP_OP_453J210_122_681_n242, DP_OP_453J210_122_681_n241,
DP_OP_453J210_122_681_n240, DP_OP_453J210_122_681_n239,
DP_OP_453J210_122_681_n238, DP_OP_453J210_122_681_n237,
DP_OP_453J210_122_681_n236, DP_OP_453J210_122_681_n235,
DP_OP_453J210_122_681_n234, DP_OP_453J210_122_681_n233,
DP_OP_453J210_122_681_n232, DP_OP_453J210_122_681_n231,
DP_OP_453J210_122_681_n230, DP_OP_453J210_122_681_n229,
DP_OP_453J210_122_681_n228, DP_OP_453J210_122_681_n227,
DP_OP_453J210_122_681_n226, DP_OP_453J210_122_681_n225,
DP_OP_453J210_122_681_n224, DP_OP_453J210_122_681_n223,
DP_OP_453J210_122_681_n222, DP_OP_453J210_122_681_n221, n2197, n2198,
n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208,
n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218,
n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228,
n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238,
n2239, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259,
n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269,
n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279,
n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289,
n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299,
n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309,
n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319,
n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369,
n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379,
n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389,
n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399,
n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409,
n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419,
n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429,
n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439,
n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449,
n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459,
n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469,
n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479,
n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679,
n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769,
n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859,
n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869,
n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109,
n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119,
n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129,
n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139,
n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149,
n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159,
n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169,
n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179,
n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189,
n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199,
n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209,
n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219,
n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229,
n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239,
n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249,
n3250, n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259,
n3260, n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269,
n3270, n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279,
n3280, n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289,
n3290, n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299,
n3300, n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309,
n3310, n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319,
n3320, n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3339, n3340, n3341,
n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351,
n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361,
n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371,
n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381,
n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391,
n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401,
n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411,
n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421,
n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431,
n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441,
n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451,
n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461,
n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471,
n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481,
n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491,
n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501,
n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511,
n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521,
n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531,
n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541,
n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551,
n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561,
n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571,
n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581,
n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591,
n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601,
n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611,
n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621,
n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631,
n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641,
n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651,
n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661,
n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671,
n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681,
n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691,
n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701,
n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711,
n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721,
n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731,
n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741,
n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751,
n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761,
n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771,
n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781,
n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791,
n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801,
n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811,
n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821,
n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831,
n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841,
n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851,
n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861,
n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871,
n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881,
n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891,
n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901,
n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911,
n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921,
n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931,
n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941,
n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951,
n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961,
n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971,
n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981,
n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991,
n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001,
n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011,
n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021,
n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031,
n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041,
n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051,
n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061,
n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071,
n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081,
n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091,
n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101,
n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111,
n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121,
n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131,
n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141,
n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151,
n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161,
n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171,
n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181,
n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191,
n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201,
n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211,
n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221,
n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231,
n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241,
n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251,
n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261,
n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271,
n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281,
n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291,
n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301,
n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311,
n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321,
n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331,
n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341,
n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351,
n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361,
n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371,
n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381,
n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391,
n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401,
n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411,
n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421,
n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431,
n4432, n4433, n4434, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4560, n4561, n4562, n4563,
n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573,
n4574, n4575, n4576, n4577, n4578, n4580, n4581, n4582, n4583, n4584,
n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594,
n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604,
n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614,
n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624,
n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634,
n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644,
n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654,
n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664,
n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674,
n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684,
n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694,
n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704,
n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714,
n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724,
n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734,
n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744,
n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754,
n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764,
n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774,
n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784,
n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794,
n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804,
n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814,
n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824,
n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834,
n4835, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4956,
n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965, n4966,
n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975, n4976,
n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985, n4986,
n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995, n4996,
n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005, n5006,
n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015, n5016,
n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025, n5026,
n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035, n5036,
n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045, n5046,
n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055, n5056,
n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, n5066,
n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075, n5076,
n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085, n5086,
n5087, n5088, n5089, n5090, n5092, n5093, n5094, n5095, n5096, n5097,
n5098, n5099, n5100, n5101, n5102, n5104, n5105, n5106, n5107, n5108,
n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116, n5117, n5118,
n5119, n5120, n5121, n5122, n5123, n5125, n5126, n5127, n5128, n5129,
n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5138, n5139, n5140,
n5141, n5142, n5143, n5144, n5145, n5146, n5147, n5148, n5149, n5150,
n5151, n5152, n5153, n5154, n5155, n5156, n5157, n5158, n5159, n5160,
n5161, n5162, n5163, n5164, n5165, n5166, n5167, n5169, n5170, n5171,
n5172, n5173, n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181,
n5182, n5183, n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191,
n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201,
n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211,
n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221,
n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231,
n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241,
n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251,
n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261,
n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271,
n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281,
n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291,
n5292, n5293, n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301,
n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311,
n5312, n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321,
n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331,
n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341,
n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351,
n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361,
n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371,
n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381,
n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391,
n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401,
n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411,
n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421,
n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431,
n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441,
n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451,
n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461,
n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471,
n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481,
n5482, n5483, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5517, n5518, n5519, n5520, n5521, n5522, n5523,
n5524, n5525;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:1] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:1] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [23:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:1] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [23:14] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n2237), .Q(
dataA[25]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n2237), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n2237), .Q(
dataA[27]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n2237), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n5489), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n5489), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n5489), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n5489), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n5489), .Q(
dataB[31]) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n5489), .Q(NaN_flag)
);
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2133), .CK(clk), .RN(n5490), .Q(
FPSENCOS_d_ff3_LUT_out[2]), .QN(n2258) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2129), .CK(clk), .RN(n5477), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2128), .CK(clk), .RN(n5492), .Q(
FPSENCOS_d_ff3_LUT_out[7]), .QN(n2256) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2127), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2123), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2121), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2115), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1854), .CK(clk), .RN(n2207),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1853), .CK(clk), .RN(n2207),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1852), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1851), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1850), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1849), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1848), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1949), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1948), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1947), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1946), .CK(clk), .RN(n5491),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2114), .CK(clk), .RN(n5489), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2113), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2112), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2111), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2110), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2109), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2108), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2107), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2106), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2105), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2104), .CK(clk), .RN(n3739), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2103), .CK(clk), .RN(n5495), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2102), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2101), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2100), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2099), .CK(clk), .RN(n5486), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2098), .CK(clk), .RN(n5497), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2097), .CK(clk), .RN(n2237), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2096), .CK(clk), .RN(n3739), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2095), .CK(clk), .RN(n5495), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2094), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2093), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2092), .CK(clk), .RN(n5490), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2091), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2090), .CK(clk), .RN(n5489), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2089), .CK(clk), .RN(n5490), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2088), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2087), .CK(clk), .RN(n5490), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2086), .CK(clk), .RN(n5490), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2085), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2084), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2083), .CK(clk), .RN(n5490), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1788), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1743), .CK(clk), .RN(
n5496), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n2207),
.Q(cordic_result[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1785), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1742), .CK(clk), .RN(
n5496), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n5486),
.Q(cordic_result[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1782), .CK(clk), .RN(n3739), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1741), .CK(clk), .RN(
n5495), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n5493),
.Q(cordic_result[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1779), .CK(clk), .RN(n5486), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1740), .CK(clk), .RN(
n5497), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n5495),
.Q(cordic_result[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1776), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1739), .CK(clk), .RN(
n5498), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n5497),
.Q(cordic_result[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1773), .CK(clk), .RN(n2237), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1738), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1858), .CK(clk), .RN(
n2207), .Q(FPSENCOS_d_ff2_Y[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n5499),
.Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1770), .CK(clk), .RN(n5496), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1737), .CK(clk), .RN(
n5502), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n5496),
.Q(cordic_result[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1767), .CK(clk), .RN(n5502), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1736), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n5496),
.Q(cordic_result[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2010), .CK(clk), .RN(n5502), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1744), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1864), .CK(clk), .RN(n5483),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1962), .CK(clk), .RN(n5480),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2031), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1751), .CK(clk), .RN(
n5483), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1878), .CK(clk), .RN(n5480),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1976), .CK(clk), .RN(n5485),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2022), .CK(clk), .RN(n5486), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1748), .CK(clk), .RN(
n5497), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1872), .CK(clk), .RN(n5495),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1970), .CK(clk), .RN(n5498),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2013), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1745), .CK(clk), .RN(
n5486), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1866), .CK(clk), .RN(n5499),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2019), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1747), .CK(clk), .RN(
n5487), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1870), .CK(clk), .RN(n3737),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1968), .CK(clk), .RN(n5487),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2016), .CK(clk), .RN(n5482), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1746), .CK(clk), .RN(
n2217), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1868), .CK(clk), .RN(n5483),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1966), .CK(clk), .RN(n5483),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2025), .CK(clk), .RN(n5483), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1749), .CK(clk), .RN(
n5483), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1874), .CK(clk), .RN(n5483),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1972), .CK(clk), .RN(n5503),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2064), .CK(clk), .RN(n5487), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1762), .CK(clk), .RN(
n5482), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1900), .CK(clk), .RN(n3737),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2058), .CK(clk), .RN(n5487), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1760), .CK(clk), .RN(
n5482), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1896), .CK(clk), .RN(n5481),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1803), .CK(clk), .RN(n5475), .QN(n2232) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2037), .CK(clk), .RN(n5481), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1882), .CK(clk), .RN(n5481),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1980), .CK(clk), .RN(n5503),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2028), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1750), .CK(clk), .RN(
n5503), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1876), .CK(clk), .RN(n5489),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1974), .CK(clk), .RN(n5503),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1804), .CK(clk), .RN(n5473), .QN(n2231) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2052), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1758), .CK(clk), .RN(
n5503), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1892), .CK(clk), .RN(n5480),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2043), .CK(clk), .RN(n5480), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1886), .CK(clk), .RN(n5480),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1984), .CK(clk), .RN(n5482),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2034), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1752), .CK(clk), .RN(
n5487), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1880), .CK(clk), .RN(n5482),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1978), .CK(clk), .RN(n5487),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2046), .CK(clk), .RN(n2237), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1756), .CK(clk), .RN(
n5482), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1888), .CK(clk), .RN(n5479),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2040), .CK(clk), .RN(n5479), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1754), .CK(clk), .RN(
n5479), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1884), .CK(clk), .RN(n5479),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1911), .CK(clk), .RN(n5478), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1847), .CK(clk), .RN(
n5478), .Q(FPSENCOS_d_ff2_Y[31]), .QN(n2282) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1846), .CK(clk), .RN(n5478),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1944), .CK(clk), .RN(n5478),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2080), .CK(clk), .RN(
n5463), .Q(FPADDSUB_left_right_SHT2) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2067), .CK(clk), .RN(n5478), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1902), .CK(clk), .RN(n5477),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n2000), .CK(clk), .RN(n5477),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n5477),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2070), .CK(clk), .RN(n5477), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1764), .CK(clk), .RN(
n5477), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1904), .CK(clk), .RN(n5491),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2055), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1759), .CK(clk), .RN(
n5491), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1894), .CK(clk), .RN(n5491),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1992), .CK(clk), .RN(n5489),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n5488),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2076), .CK(clk), .RN(n5492), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1766), .CK(clk), .RN(
n5491), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1908), .CK(clk), .RN(n5481),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n5500),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2073), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1765), .CK(clk), .RN(
n5490), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1906), .CK(clk), .RN(n5500),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n5490),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2049), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1757), .CK(clk), .RN(
n5488), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1890), .CK(clk), .RN(n5490),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n5495),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2061), .CK(clk), .RN(n5490), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1761), .CK(clk), .RN(
n5500), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1898), .CK(clk), .RN(n5500),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1996), .CK(clk), .RN(n5488),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n5488),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n5488),
.Q(cordic_result[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n5488),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n5488),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n5488),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n5488),
.Q(cordic_result[13]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1696), .CK(clk),
.RN(n5505), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1626), .CK(
clk), .RN(n2204), .Q(FPMULT_zero_flag) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1671), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[12]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1659), .CK(clk),
.RN(n5510), .Q(FPMULT_Op_MX[0]), .QN(n2283) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1658), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1624), .CK(clk), .RN(
n2204), .Q(FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1601), .CK(clk),
.RN(n2215), .Q(FPMULT_Add_result[23]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1632), .CK(clk),
.RN(n5506), .QN(n2218) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n1599), .CK(clk),
.RN(n5481), .Q(FPMULT_P_Sgf[46]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n1598), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[45]), .QN(n5387) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n1597), .CK(clk),
.RN(n5491), .Q(FPMULT_P_Sgf[44]), .QN(n5381) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n1596), .CK(clk),
.RN(n5492), .Q(FPMULT_P_Sgf[43]), .QN(n5389) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n1595), .CK(clk),
.RN(n5500), .Q(FPMULT_P_Sgf[42]), .QN(n5390) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1576), .CK(clk),
.RN(n2237), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1575), .CK(clk),
.RN(n3739), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1574), .CK(clk),
.RN(n5495), .Q(FPMULT_P_Sgf[21]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1573), .CK(clk),
.RN(n5501), .Q(FPMULT_P_Sgf[20]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1572), .CK(clk),
.RN(n5498), .Q(FPMULT_P_Sgf[19]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1571), .CK(clk),
.RN(n5493), .Q(FPMULT_P_Sgf[18]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1570), .CK(clk),
.RN(n5486), .Q(FPMULT_P_Sgf[17]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1569), .CK(clk),
.RN(n5497), .Q(FPMULT_P_Sgf[16]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1568), .CK(clk),
.RN(n2237), .Q(FPMULT_P_Sgf[15]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1567), .CK(clk),
.RN(n5495), .Q(FPMULT_P_Sgf[14]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1566), .CK(clk),
.RN(n5501), .Q(FPMULT_P_Sgf[13]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1565), .CK(clk),
.RN(n5498), .Q(FPMULT_P_Sgf[12]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1562), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[9]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1558), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[5]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1557), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[4]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1556), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[3]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1555), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[2]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1554), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1553), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1518), .CK(
clk), .RN(n5511), .QN(n2223) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1515), .CK(clk), .RN(n5504), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1514), .CK(clk), .RN(n5506), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1513), .CK(clk), .RN(n5510), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1512), .CK(clk), .RN(n5507), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1511), .CK(clk), .RN(n5504), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1510), .CK(clk), .RN(n5505), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1509), .CK(clk), .RN(n5508), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1508), .CK(clk), .RN(n2215), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1507), .CK(clk), .RN(n5451), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1506), .CK(clk), .RN(n2204), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1505), .CK(clk), .RN(n5509), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1504), .CK(clk), .RN(n2204), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1503), .CK(clk), .RN(n2215), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1502), .CK(clk), .RN(n5506), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1501), .CK(clk), .RN(n5510), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1500), .CK(clk), .RN(n5507), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1499), .CK(clk), .RN(n5504), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1498), .CK(clk), .RN(n5505), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1497), .CK(clk), .RN(n5510), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1496), .CK(clk), .RN(n5507), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1495), .CK(clk), .RN(n2215), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1494), .CK(clk), .RN(n5508), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1493), .CK(clk), .RN(n5451), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1492), .CK(clk), .RN(n2204), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1491), .CK(clk), .RN(n5509), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1490), .CK(clk), .RN(n5510), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1489), .CK(clk), .RN(n5507), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1488), .CK(clk), .RN(n2215), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1487), .CK(clk), .RN(n5508), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1486), .CK(clk), .RN(n5508), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1485), .CK(clk), .RN(n2204), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1483), .CK(clk), .RN(n5509), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1480), .CK(clk), .RN(
n3738), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1479), .CK(clk), .RN(
n3749), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1478), .CK(clk), .RN(
n2212), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1477), .CK(clk), .RN(
n5467), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1476), .CK(clk), .RN(
n5468), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1475), .CK(clk), .RN(
n5460), .QN(n2227) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1473), .CK(clk), .RN(
n5474), .QN(n2225) );
DFFRXLTS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1469), .CK(clk), .RN(
n5476), .QN(n2226) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1462), .CK(clk), .RN(n5469),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1461), .CK(clk), .RN(n5472),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1460), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1459), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1458), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n2211),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1456), .CK(clk), .RN(
n5473), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1454), .CK(clk), .RN(n5465),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1453), .CK(clk), .RN(n2238),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n3738),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1451), .CK(clk), .RN(
n5474), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1449), .CK(clk), .RN(n2212),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1448), .CK(clk), .RN(n2212),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n3749),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1446), .CK(clk), .RN(
n5453), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1444), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n5457),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1441), .CK(clk), .RN(
n5453), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n2211),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n3749),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n5457),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1436), .CK(clk), .RN(
n5475), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1434), .CK(clk), .RN(n5475),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n5457),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1431), .CK(clk), .RN(
n5476), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1429), .CK(clk), .RN(n5475),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1428), .CK(clk), .RN(n5473),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1426), .CK(clk), .RN(
n5476), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1424), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n5473),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1421), .CK(clk), .RN(
n5453), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1414), .CK(clk), .RN(n2211), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1413), .CK(clk), .RN(n5454), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1411), .CK(clk), .RN(
n5474), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1409), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n3738), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1406), .CK(clk), .RN(n5456),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n3738), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1403), .CK(clk), .RN(n3738),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n5463), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1400), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n5463), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1397), .CK(clk), .RN(n2211),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n2211), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1394), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n5463), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1391), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n5463), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1388), .CK(clk), .RN(n5463),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n5463), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n2211), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1382), .CK(clk), .RN(n3738),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n2211), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1379), .CK(clk), .RN(n5463),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n5456), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1376), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n5462), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1373), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n2211), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1370), .CK(clk), .RN(n3738),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n5456), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1367), .CK(clk), .RN(n5456),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n5456), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1364), .CK(clk), .RN(n5456),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n5462), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n5462), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n2211),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1360), .CK(clk), .RN(n5462),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1359), .CK(clk), .RN(
n5476), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n3738),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n3738), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n2211), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1332), .CK(clk), .RN(
n5473), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n2210), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n5465),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1324), .CK(clk), .RN(
n5474), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1320), .CK(clk), .RN(
n5460), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1316), .CK(clk), .RN(
n5474), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1314), .CK(clk), .RN(n2238),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n5464), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n5466),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(n5465),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n2238),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1307), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n2210), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n5466),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n5465),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1300), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n5466), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n2238),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1293), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n2210), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(n5466),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n5465),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1286), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n2210), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(n5466),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1279), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n2238), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1273), .CK(clk), .RN(n5466),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1272), .CK(clk), .RN(
n5465), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n5473),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n2238),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1267), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1266), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1263), .CK(clk), .RN(n5467),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1262), .CK(clk), .RN(n5468),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n5471),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1259), .CK(clk), .RN(n5469),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n5472),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1255), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1254), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1251), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1250), .CK(clk), .RN(n5467),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n5468),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1247), .CK(clk), .RN(n5471),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1246), .CK(clk), .RN(n5469),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1243), .CK(clk), .RN(n5472),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1242), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1239), .CK(clk), .RN(n5467),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1238), .CK(clk), .RN(n5468),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n5471),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1235), .CK(clk), .RN(n5469),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1234), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n5472),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1231), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1230), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n5467),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1227), .CK(clk), .RN(n5468),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1226), .CK(clk), .RN(n5471),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n5469),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1223), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1222), .CK(clk), .RN(n5472),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1219), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1218), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n5467),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1215), .CK(clk), .RN(n5468),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1214), .CK(clk), .RN(n5471),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n5469),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1211), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1210), .CK(clk), .RN(n5472),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(
n5470), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]) );
CMPR32X2TS DP_OP_234J210_126_8543_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_234J210_126_8543_n22), .CO(
DP_OP_234J210_126_8543_n9), .S(FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J210_126_8543_U9 ( .A(DP_OP_234J210_126_8543_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J210_126_8543_n9), .CO(
DP_OP_234J210_126_8543_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J210_126_8543_U8 ( .A(DP_OP_234J210_126_8543_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J210_126_8543_n8), .CO(
DP_OP_234J210_126_8543_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J210_126_8543_U7 ( .A(DP_OP_234J210_126_8543_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J210_126_8543_n7), .CO(
DP_OP_234J210_126_8543_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J210_126_8543_U6 ( .A(DP_OP_234J210_126_8543_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J210_126_8543_n6), .CO(
DP_OP_234J210_126_8543_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J210_126_8543_U5 ( .A(DP_OP_234J210_126_8543_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J210_126_8543_n5), .CO(
DP_OP_234J210_126_8543_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J210_126_8543_U4 ( .A(DP_OP_234J210_126_8543_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J210_126_8543_n4), .CO(
DP_OP_234J210_126_8543_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J210_126_8543_U3 ( .A(DP_OP_234J210_126_8543_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J210_126_8543_n3), .CO(
DP_OP_234J210_126_8543_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_234J210_126_8543_U2 ( .A(FPMULT_FSM_exp_operation_A_S), .B(
FPMULT_S_Oper_A_exp[8]), .C(DP_OP_234J210_126_8543_n2), .CO(
DP_OP_234J210_126_8543_n1), .S(FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_477_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n5314), .C(
intadd_477_CI), .CO(intadd_477_n3), .S(intadd_477_SUM_0_) );
CMPR32X2TS intadd_477_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n4441), .C(
intadd_477_n3), .CO(intadd_477_n2), .S(intadd_477_SUM_1_) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1625), .CK(
clk), .RN(n5507), .Q(FPMULT_Sgf_normalized_result[23]), .QN(n5380) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1622), .CK(clk), .RN(
n5506), .Q(FPMULT_Add_result[2]), .QN(n5379) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1860), .CK(clk), .RN(
n5497), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n5378) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1861), .CK(clk), .RN(
n2237), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n5377) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1862), .CK(clk), .RN(
n5499), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n5376) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1516), .CK(clk), .RN(
n5504), .Q(underflow_flag_mult), .QN(n5375) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1856), .CK(clk), .RN(
n2207), .Q(FPSENCOS_d_ff2_Y[30]), .QN(n5374) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1859), .CK(clk), .RN(
n5495), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n5373) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1857), .CK(clk), .RN(
n2207), .Q(FPSENCOS_d_ff2_Y[29]), .QN(n5372) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1182), .CK(clk), .RN(
n5460), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n5371) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(n5478), .Q(
FPSENCOS_d_ff_Yn[31]), .QN(n5370) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1956), .CK(clk), .RN(
n5502), .Q(FPSENCOS_d_ff2_X[28]), .QN(n5368) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1539), .CK(
clk), .RN(n5510), .Q(FPMULT_Sgf_normalized_result[22]), .QN(n5366) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1820), .CK(clk), .RN(
n5460), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n5365) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1819), .CK(clk), .RN(
n5475), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n5364) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SFG[22]), .QN(n5362) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1690), .CK(clk), .RN(n5504), .Q(
FPMULT_FSM_selector_C), .QN(n5361) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2137), .CK(clk), .RN(n2237),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n5360) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1467), .CK(clk), .RN(n5472),
.Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n5359) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1537), .CK(
clk), .RN(n5506), .Q(FPMULT_Sgf_normalized_result[20]), .QN(n5358) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1809), .CK(clk), .RN(n5462), .Q(FPADDSUB_Data_array_SWR[18]), .QN(n5357) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1810), .CK(clk), .RN(n5465), .Q(FPADDSUB_Data_array_SWR[19]), .QN(n5356) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1351), .CK(clk), .RN(
n2211), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n5354) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1914), .CK(clk), .RN(
n5457), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n5352) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1812), .CK(clk), .RN(n5461), .Q(FPADDSUB_Data_array_SWR[21]), .QN(n5351) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1811), .CK(clk), .RN(n5460), .Q(FPADDSUB_Data_array_SWR[20]), .QN(n5350) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1943), .CK(clk), .RN(
n2212), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n5349) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1185), .CK(clk), .RN(
n5474), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n5345) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1928), .CK(clk), .RN(
n2210), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n5344) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1922), .CK(clk), .RN(
n3738), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n5343) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1930), .CK(clk), .RN(
n5476), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n5342) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1926), .CK(clk), .RN(
n5461), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n5341) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1932), .CK(clk), .RN(
n5468), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n5340) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1934), .CK(clk), .RN(
n2212), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n5339) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1942), .CK(clk), .RN(
n2212), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n5338) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1916), .CK(clk), .RN(
n5460), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n5337) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1924), .CK(clk), .RN(
n5463), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n5334) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1941), .CK(clk), .RN(
n3749), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n5333) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1935), .CK(clk), .RN(
n5469), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n5332) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1535), .CK(
clk), .RN(n5508), .Q(FPMULT_Sgf_normalized_result[18]), .QN(n5331) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2079), .CK(clk), .RN(
n5473), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n5330) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2081), .CK(clk), .RN(
n5476), .Q(FPADDSUB_bit_shift_SHT2), .QN(n5329) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n5467),
.Q(FPADDSUB_DMP_SFG[21]), .QN(n5328) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1337), .CK(clk), .RN(
n2210), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n5326) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1187), .CK(clk), .RN(
n5474), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n5325) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1551), .CK(clk), .RN(n2204), .Q(
FPMULT_FSM_selector_B[0]), .QN(n5324) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1816), .CK(clk), .RN(
n5475), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n5323) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1533), .CK(
clk), .RN(n2215), .Q(FPMULT_Sgf_normalized_result[16]), .QN(n5319) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n5498), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n5318) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1322), .CK(clk), .RN(
n2210), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n5316) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1333), .CK(clk), .RN(
n2211), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n5315) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1472), .CK(clk), .RN(
n5473), .Q(result_add_subt[26]), .QN(n5313) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1471), .CK(clk), .RN(
n5473), .Q(result_add_subt[27]), .QN(n5312) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1470), .CK(clk), .RN(
n5454), .Q(result_add_subt[28]), .QN(n5311) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1280), .CK(clk), .RN(
n2210), .Q(result_add_subt[5]), .QN(n5308) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1287), .CK(clk), .RN(
n5464), .Q(result_add_subt[9]), .QN(n5307) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1294), .CK(clk), .RN(
n2210), .Q(result_add_subt[1]), .QN(n5306) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1301), .CK(clk), .RN(
n2238), .Q(result_add_subt[0]), .QN(n5305) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1308), .CK(clk), .RN(
n5455), .Q(result_add_subt[7]), .QN(n5304) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1315), .CK(clk), .RN(
n2238), .Q(result_add_subt[2]), .QN(n5303) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1331), .CK(clk), .RN(
n2210), .Q(result_add_subt[3]), .QN(n5302) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1365), .CK(clk), .RN(
n5461), .Q(result_add_subt[12]), .QN(n5301) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1368), .CK(clk), .RN(
n5462), .Q(result_add_subt[10]), .QN(n5300) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1371), .CK(clk), .RN(
n5463), .Q(result_add_subt[14]), .QN(n5299) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1374), .CK(clk), .RN(
n2211), .Q(result_add_subt[11]), .QN(n5298) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1377), .CK(clk), .RN(
n5463), .Q(result_add_subt[8]), .QN(n5297) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1380), .CK(clk), .RN(
n3738), .Q(result_add_subt[16]), .QN(n5296) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1383), .CK(clk), .RN(
n2211), .Q(result_add_subt[13]), .QN(n5295) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(
n3738), .Q(result_add_subt[6]), .QN(n5294) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(
n2211), .Q(result_add_subt[4]), .QN(n5293) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1392), .CK(clk), .RN(
n5456), .Q(result_add_subt[17]), .QN(n5292) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1395), .CK(clk), .RN(
n5463), .Q(result_add_subt[20]), .QN(n5291) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1398), .CK(clk), .RN(
n3738), .Q(result_add_subt[19]), .QN(n5290) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1401), .CK(clk), .RN(
n5456), .Q(result_add_subt[21]), .QN(n5289) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1404), .CK(clk), .RN(
n5461), .Q(result_add_subt[18]), .QN(n5288) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1407), .CK(clk), .RN(
n2211), .Q(result_add_subt[15]), .QN(n5287) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1410), .CK(clk), .RN(
n5462), .Q(result_add_subt[22]), .QN(n5286) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1189), .CK(clk), .RN(
n5476), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n5280) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1531), .CK(
clk), .RN(n2204), .Q(FPMULT_Sgf_normalized_result[14]), .QN(n5279) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2193), .CK(
clk), .RN(n5476), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n5278) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n5468),
.Q(FPADDSUB_DMP_SFG[19]), .QN(n5275) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1529), .CK(
clk), .RN(n5509), .Q(FPMULT_Sgf_normalized_result[12]), .QN(n5273) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(
n5454), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n5272) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SFG[17]), .QN(n5271) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1527), .CK(
clk), .RN(n2204), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n5270) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1193), .CK(clk), .RN(
n5460), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n5269) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_SFG[15]), .QN(n5268) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1525), .CK(
clk), .RN(n2215), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n5267) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1336), .CK(clk), .RN(
n2238), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n5266) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1195), .CK(clk), .RN(
n5459), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n5265) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1523), .CK(
clk), .RN(n2215), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n5264) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1317), .CK(clk), .RN(
n5464), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n5263) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_SFG[13]), .QN(n5262) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1521), .CK(
clk), .RN(n5505), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n5261) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1197), .CK(clk), .RN(
n5468), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n5260) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1199), .CK(clk), .RN(
n5472), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n5259) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n5467),
.Q(FPADDSUB_DMP_SFG[11]), .QN(n5258) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1201), .CK(clk), .RN(
n5470), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n5257) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1203), .CK(clk), .RN(
n5458), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n5256) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DMP_SFG[9]), .QN(n5255) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DMP_SFG[0]), .QN(n5254) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n2212),
.Q(FPADDSUB_DMP_SFG[7]), .QN(n5253) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n5466),
.Q(FPADDSUB_DMP_SFG[5]), .QN(n5252) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DMP_SFG[3]), .QN(n5251) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n5465),
.Q(FPADDSUB_DMP_SFG[1]), .QN(n5250) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1417), .CK(clk), .RN(n2211),
.Q(FPADDSUB_DmP_EXP_EWSW[25]), .QN(n5249) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1464), .CK(clk), .RN(n5471),
.Q(FPADDSUB_DMP_EXP_EWSW[26]), .QN(n5248) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1416), .CK(clk), .RN(n3738),
.Q(FPADDSUB_DmP_EXP_EWSW[26]), .QN(n5246) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1541), .CK(clk), .RN(
n5505), .Q(FPMULT_exp_oper_result[8]), .QN(n5245) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n2299), .CK(clk), .RN(n5474), .Q(
ready_add_subt), .QN(n5244) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1465), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_EXP_EWSW[25]), .QN(n5243) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2136), .CK(clk), .RN(n5497),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n5242) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1813), .CK(clk), .RN(n5454), .Q(FPADDSUB_Data_array_SWR[22]), .QN(n5241) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1913), .CK(clk), .RN(
n5453), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n5240) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1814), .CK(clk), .RN(n5453), .Q(FPADDSUB_Data_array_SWR[23]), .QN(n5239) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1921), .CK(clk), .RN(
n2210), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n5238) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1925), .CK(clk), .RN(
n5464), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n5237) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1929), .CK(clk), .RN(
n5471), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n5236) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1931), .CK(clk), .RN(
n5462), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n5235) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1940), .CK(clk), .RN(
n5474), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n5232) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1923), .CK(clk), .RN(
n5463), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n5231) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1863), .CK(clk), .RN(
n5496), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n5230) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1184), .CK(clk), .RN(
n5457), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n5229) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1815), .CK(clk), .RN(
n5466), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n5228) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1344), .CK(clk), .RN(
n5462), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n5227) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1474), .CK(clk), .RN(
n5453), .Q(result_add_subt[24]), .QN(n5225) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n5486), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .QN(n5224) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1350), .CK(clk), .RN(
n5456), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n5222) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n5501), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n5221) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1346), .CK(clk), .RN(
n2211), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n5220) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1358), .CK(clk), .RN(
n5456), .Q(result_add_subt[31]), .QN(n5219) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2151), .CK(
clk), .RN(n5460), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n5217) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1186), .CK(clk), .RN(
n5473), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n5216) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1188), .CK(clk), .RN(
n5473), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n5215) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1342), .CK(clk), .RN(
n2211), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n5214) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1190), .CK(clk), .RN(
n5474), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n5212) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1192), .CK(clk), .RN(
n5476), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n5210) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1194), .CK(clk), .RN(
n5470), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n5209) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1196), .CK(clk), .RN(
n5469), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n5208) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1198), .CK(clk), .RN(
n5459), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n5207) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1200), .CK(clk), .RN(
n5467), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n5206) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1202), .CK(clk), .RN(
n5471), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n5205) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1204), .CK(clk), .RN(
n5472), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n5204) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2149), .CK(clk), .RN(
n5476), .Q(n5185), .QN(n5369) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1338), .CK(clk), .RN(
n2210), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n5203) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1341), .CK(clk), .RN(
n5465), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n5202) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2082), .CK(clk), .RN(n5500),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n5201) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1466), .CK(clk), .RN(n5469),
.Q(FPADDSUB_DMP_EXP_EWSW[24]), .QN(n5200) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1418), .CK(clk), .RN(n5457),
.Q(FPADDSUB_DmP_EXP_EWSW[24]), .QN(n5199) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1918), .CK(clk), .RN(
n5453), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n5198) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1917), .CK(clk), .RN(
n5457), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n5197) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1339), .CK(clk), .RN(
n5464), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n5196) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1321), .CK(clk), .RN(
n5466), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n5195) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1347), .CK(clk), .RN(
n5456), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n5194) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1345), .CK(clk), .RN(
n2211), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n5193) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(
n5461), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n5191) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1334), .CK(clk), .RN(
n5455), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n5188) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1318), .CK(clk), .RN(
n5465), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]), .QN(n5187) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1207), .CK(clk), .RN(
n5468), .QN(n5186) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1340), .CK(clk), .RN(
n5466), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n5184) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1919), .CK(clk), .RN(
n5475), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n5183) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(
n2210), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n5180) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2143), .CK(clk), .RN(n5489),
.Q(n5452), .QN(n5525) );
DFFSX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n2224), .CK(clk),
.SN(n5451), .Q(DP_OP_453J210_122_681_n667), .QN(FPMULT_Op_MX[11]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n5476),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n5189) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(
n5475), .Q(FPADDSUB_ADD_OVRFLW_NRM2) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1691), .CK(clk), .RN(n5511), .Q(
FPMULT_FSM_selector_A), .QN(n5367) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1550), .CK(clk), .RN(n5506), .Q(
FPMULT_FSM_selector_B[1]), .QN(n5327) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1348), .CK(clk), .RN(
n3738), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n5192) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2142), .CK(clk), .RN(n5489),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n5314) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2140), .CK(clk), .RN(n5501),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n5213) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2139), .CK(clk), .RN(n2237),
.Q(FPSENCOS_cont_var_out[0]), .QN(n5363) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1693), .CK(clk), .RN(n5491),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n5190) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1694), .CK(clk), .RN(n5487),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n5274) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1692), .CK(clk), .RN(n3737),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n5182) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1695), .CK(clk), .RN(n3737),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n5211) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1335), .CK(clk), .RN(
n2238), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n5181) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1933), .CK(clk), .RN(
n5470), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n5335) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1920), .CK(clk), .RN(
n5453), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n5347) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1838), .CK(clk), .RN(
n5457), .Q(FPADDSUB_intDY_EWSW[7]), .QN(n5346) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1826), .CK(clk), .RN(
n3738), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n5226) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1827), .CK(clk), .RN(
n5466), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n5321) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1831), .CK(clk), .RN(
n5459), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n5276) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1832), .CK(clk), .RN(
n5474), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n5284) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1834), .CK(clk), .RN(
n5470), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n5309) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1823), .CK(clk), .RN(
n5465), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n5282) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1936), .CK(clk), .RN(
n5475), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n5355) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1938), .CK(clk), .RN(
n2212), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n5348) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1825), .CK(clk), .RN(
n5462), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n5283) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1828), .CK(clk), .RN(
n5456), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n5310) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1830), .CK(clk), .RN(
n5474), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n5218) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1842), .CK(clk), .RN(
n3738), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n5281) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1937), .CK(clk), .RN(
n5474), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n5233) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1939), .CK(clk), .RN(
n5473), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n5234) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1927), .CK(clk), .RN(
n5457), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n5336) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1915), .CK(clk), .RN(
n5473), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n5353) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1821), .CK(clk), .RN(
n5475), .Q(FPADDSUB_intDY_EWSW[24]), .QN(n5247) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1822), .CK(clk), .RN(
n5460), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n5223) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1824), .CK(clk), .RN(
n5455), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n5317) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1833), .CK(clk), .RN(
n5467), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n5277) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1837), .CK(clk), .RN(
n5454), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n5320) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1844), .CK(clk), .RN(
n2211), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n5285) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n5493), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .QN(n5322) );
DFFSX1TS R_11 ( .D(n5446), .CK(clk), .SN(n5502), .Q(n5522) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2132), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n5431) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2006), .CK(clk), .RN(n5490),
.Q(FPSENCOS_d_ff3_sh_x_out[0]), .QN(n5433) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1867), .CK(clk), .RN(
n5493), .Q(FPSENCOS_d_ff2_Y[21]), .QN(n5425) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n1579), .CK(clk),
.RN(n5487), .Q(FPMULT_P_Sgf[26]), .QN(n5384) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n1594), .CK(clk),
.RN(n5490), .Q(FPMULT_P_Sgf[41]), .QN(n5391) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1673), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[14]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1679), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[20]), .QN(n2286) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1681), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[22]), .QN(n2307) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1840), .CK(clk), .RN(
n3749), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2138), .CK(clk), .RN(n5497),
.Q(FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1643), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1839), .CK(clk), .RN(
n5476), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1835), .CK(clk), .RN(
n5468), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1843), .CK(clk), .RN(
n5476), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1829), .CK(clk), .RN(
n5453), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1818), .CK(clk), .RN(
n5453), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1517), .CK(
clk), .RN(n5511), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1660), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MX[1]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1662), .CK(clk),
.RN(n5509), .Q(FPMULT_Op_MX[3]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1665), .CK(clk),
.RN(n2204), .Q(FPMULT_Op_MX[6]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1845), .CK(clk), .RN(
n5455), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1183), .CK(clk), .RN(
n5457), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n5471),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n5470),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n5467),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n5469),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n5472),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n2210),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2078), .CK(clk), .RN(
n3749), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1323), .CK(clk), .RN(
n2210), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1633), .CK(clk),
.RN(n2204), .Q(FPMULT_Op_MY[6]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1629), .CK(clk),
.RN(n5505), .Q(FPMULT_Op_MY[2]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1649), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MY[22]), .QN(n2302) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1637), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MY[10]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1806), .CK(clk), .RN(n3738), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1805), .CK(clk), .RN(n5454), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1807), .CK(clk), .RN(n3749), .Q(FPADDSUB_Data_array_SWR[16]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1808), .CK(clk), .RN(n5463), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1802), .CK(clk), .RN(n5469), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1801), .CK(clk), .RN(n5471), .Q(FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1205), .CK(clk), .RN(
n5458), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1628), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MY[1]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1349), .CK(clk), .RN(
n2211), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1957), .CK(clk), .RN(
n5498), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1468), .CK(clk), .RN(
n5474), .Q(result_add_subt[30]) );
DFFRX4TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n5461),
.Q(n2301), .QN(n5515) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n5493), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n5489), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1955), .CK(clk), .RN(
n5496), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(
n5508), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1961), .CK(clk), .RN(
n2207), .Q(FPSENCOS_d_ff2_X[23]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1520), .CK(
clk), .RN(n5507), .Q(FPMULT_Sgf_normalized_result[3]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1522), .CK(
clk), .RN(n5510), .Q(FPMULT_Sgf_normalized_result[5]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1524), .CK(
clk), .RN(n5508), .Q(FPMULT_Sgf_normalized_result[7]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1526), .CK(
clk), .RN(n2204), .Q(FPMULT_Sgf_normalized_result[9]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1528), .CK(
clk), .RN(n2215), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1530), .CK(
clk), .RN(n5505), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1532), .CK(
clk), .RN(n5504), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1534), .CK(
clk), .RN(n5507), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1536), .CK(
clk), .RN(n5510), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1538), .CK(
clk), .RN(n2215), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1912), .CK(clk), .RN(
n5456), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1634), .CK(clk),
.RN(n5510), .Q(FPMULT_Op_MY[7]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1627), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[0]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1672), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[13]), .QN(n2289) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1958), .CK(clk), .RN(
n3739), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1959), .CK(clk), .RN(
n5493), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1960), .CK(clk), .RN(
n5502), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1412), .CK(clk), .RN(
n5456), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n2222) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1796), .CK(clk), .RN(n5474),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1795), .CK(clk), .RN(n5463),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1686), .CK(clk),
.RN(n5509), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1353), .CK(clk), .RN(n5462),
.Q(FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1419), .CK(clk), .RN(n5476),
.Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1735), .CK(clk), .RN(
n5478), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n5477),
.Q(operation_reg[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1954), .CK(clk), .RN(
n5502), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n1552), .CK(clk),
.RN(n2217), .Q(FPMULT_P_Sgf[47]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n5496),
.Q(operation_reg[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n5488), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n5490), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n5479), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n5477), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n5479), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n5479), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n5482), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n5481), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n5481), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n5483), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n5483), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n5487), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n5490), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n5480), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n5480), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n5486), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n5485), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1542), .CK(clk), .RN(
n5510), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1543), .CK(clk), .RN(
n5507), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1544), .CK(clk), .RN(
n2215), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1546), .CK(clk), .RN(
n5509), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1547), .CK(clk), .RN(
n5506), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1548), .CK(clk), .RN(
n2204), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1549), .CK(clk), .RN(
n2204), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1772), .CK(clk), .RN(n5502), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n5495), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2060), .CK(clk), .RN(n5480), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2072), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2075), .CK(clk), .RN(n5481), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2066), .CK(clk), .RN(n5477), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2063), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1600), .CK(clk),
.RN(n5509), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1657), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MY[30]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1653), .CK(clk),
.RN(n2204), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1654), .CK(clk),
.RN(n5506), .Q(FPMULT_Op_MY[27]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1635), .CK(clk),
.RN(n5508), .Q(FPMULT_Op_MY[8]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1630), .CK(clk),
.RN(n5511), .Q(FPMULT_Op_MY[3]) );
DFFSX1TS R_3 ( .D(n5448), .CK(clk), .SN(n2217), .Q(n5519) );
DFFSX1TS R_2 ( .D(n5449), .CK(clk), .SN(n5496), .Q(n5524) );
DFFSX1TS R_1 ( .D(n5450), .CK(clk), .SN(n2217), .Q(n5523) );
DFFSX1TS R_4 ( .D(n5447), .CK(clk), .SN(n2217), .Q(n5520) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1730), .CK(clk), .RN(
n5463), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1420), .CK(clk), .RN(
n5453), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1425), .CK(clk), .RN(
n5476), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1430), .CK(clk), .RN(
n5453), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1435), .CK(clk), .RN(
n5454), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1440), .CK(clk), .RN(
n5475), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1445), .CK(clk), .RN(
n5473), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1450), .CK(clk), .RN(
n5473), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1455), .CK(clk), .RN(
n5453), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n5489), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n2237), .Q(
dataA[29]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1792), .CK(clk), .RN(n5462),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1791), .CK(clk), .RN(n2210),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1790), .CK(clk), .RN(n5455),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1855), .CK(clk), .RN(n2207),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2117), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2118), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2125), .CK(clk), .RN(n5488), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2131), .CK(clk), .RN(n5481), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n5479), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2130), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2116), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1677), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[18]), .QN(n2287) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1675), .CK(clk),
.RN(n5518), .Q(FPMULT_Op_MX[16]), .QN(n2319) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1680), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[21]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1678), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[19]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1676), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[17]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1674), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MX[15]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1841), .CK(clk), .RN(
n2211), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1836), .CK(clk), .RN(
n3749), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1817), .CK(clk), .RN(
n5473), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1667), .CK(clk),
.RN(n2204), .Q(FPMULT_Op_MX[8]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1663), .CK(clk),
.RN(n5505), .Q(FPMULT_Op_MX[4]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1666), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MX[7]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1661), .CK(clk),
.RN(n5510), .Q(FPMULT_Op_MX[2]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1664), .CK(clk),
.RN(n5510), .Q(FPMULT_Op_MX[5]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1631), .CK(clk),
.RN(n5511), .Q(FPMULT_Op_MY[4]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1639), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MY[12]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1636), .CK(clk),
.RN(n5509), .Q(FPMULT_Op_MY[9]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1798), .CK(clk), .RN(n5458),
.Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1800), .CK(clk), .RN(n5472), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1799), .CK(clk), .RN(n3749), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1797), .CK(clk), .RN(n3738),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1519), .CK(
clk), .RN(n2215), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1646), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[19]), .QN(n2304) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1644), .CK(clk),
.RN(n5510), .Q(FPMULT_Op_MY[17]), .QN(n2288) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1642), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MY[15]), .QN(n2300) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1648), .CK(clk),
.RN(n2204), .Q(FPMULT_Op_MY[21]), .QN(n2303) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n5512), .CK(clk),
.RN(n5493), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1687), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1619), .CK(clk), .RN(
n2204), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1683), .CK(clk),
.RN(n2204), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1651), .CK(clk),
.RN(n5510), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1945), .CK(clk), .RN(
n5478), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1650), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1545), .CK(clk), .RN(
n5508), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n5496), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1641), .CK(clk),
.RN(n2204), .Q(FPMULT_Op_MY[14]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1638), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MY[11]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1794), .CK(clk), .RN(n2238),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2141), .CK(clk), .RN(n5495),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n2311) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n3739), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n5499), .Q(
dataB[23]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1656), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MY[29]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1655), .CK(clk),
.RN(n5451), .Q(FPMULT_Op_MY[28]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1652), .CK(clk),
.RN(n5508), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1755), .CK(clk), .RN(
n5480), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1991), .CK(clk), .RN(
n5480), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1753), .CK(clk), .RN(
n5481), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1995), .CK(clk), .RN(
n5481), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1987), .CK(clk), .RN(
n5479), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2045), .CK(clk), .RN(n5479), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n5491),
.Q(cordic_result[2]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2003), .CK(clk), .RN(
n5491), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1734), .CK(clk), .RN(n5478), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1983), .CK(clk), .RN(
n5478), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1967), .CK(clk), .RN(
n5483), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n2217),
.Q(cordic_result[6]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n2217),
.Q(cordic_result[4]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n2217),
.Q(cordic_result[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n5503),
.Q(cordic_result[20]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n5483),
.Q(cordic_result[19]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n5480),
.Q(cordic_result[21]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n3737),
.Q(cordic_result[18]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n3737),
.Q(cordic_result[15]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n3737),
.Q(cordic_result[22]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n2001), .CK(clk), .RN(
n5477), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1763), .CK(clk), .RN(
n5477), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1963), .CK(clk), .RN(
n5485), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n5488),
.Q(cordic_result[12]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n5488),
.Q(cordic_result[31]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n5488),
.Q(cordic_result[5]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1997), .CK(clk), .RN(
n5488), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1559), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[6]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1560), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[7]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1561), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[8]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1563), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1564), .CK(clk),
.RN(n5485), .Q(FPMULT_P_Sgf[11]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n2217), .Q(
dataB[24]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1733), .CK(clk), .RN(
n5462), .Q(FPADDSUB_intAS) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n2237), .Q(
dataA[30]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2119), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1415), .CK(clk), .RN(n5456),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n2237), .Q(
dataA[28]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1789), .CK(clk), .RN(n3749),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n2237), .Q(
dataA[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n5492), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2009), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff_Xn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2039), .CK(clk), .RN(n5479), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2069), .CK(clk), .RN(n5477), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2024), .CK(clk), .RN(n5483), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2057), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2018), .CK(clk), .RN(n5482), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2015), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2021), .CK(clk), .RN(n2237), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2012), .CK(clk), .RN(n5497), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n5494), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2030), .CK(clk), .RN(n2217), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n5489), .Q(
dataB[28]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1793), .CK(clk), .RN(n2212),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1682), .CK(clk),
.RN(n5506), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1688), .CK(clk),
.RN(n5510), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1685), .CK(clk),
.RN(n2204), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1689), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1684), .CK(clk),
.RN(n2215), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1618), .CK(clk), .RN(
n5508), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1616), .CK(clk), .RN(
n5505), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1614), .CK(clk),
.RN(n5507), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1612), .CK(clk),
.RN(n2204), .Q(FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1610), .CK(clk),
.RN(n2215), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1608), .CK(clk),
.RN(n5505), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1606), .CK(clk),
.RN(n5507), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1604), .CK(clk),
.RN(n5506), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1602), .CK(clk),
.RN(n2204), .Q(FPMULT_Add_result[22]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1623), .CK(clk), .RN(
n5509), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1463), .CK(clk), .RN(n5471),
.Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1617), .CK(clk), .RN(
n2215), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1603), .CK(clk),
.RN(n2215), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1605), .CK(clk),
.RN(n5510), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1607), .CK(clk),
.RN(n5504), .Q(FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1609), .CK(clk),
.RN(n5508), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1611), .CK(clk),
.RN(n2204), .Q(FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1613), .CK(clk),
.RN(n5509), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1615), .CK(clk), .RN(
n5504), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1620), .CK(clk), .RN(
n2215), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1621), .CK(clk), .RN(
n2204), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1969), .CK(clk), .RN(
n5503), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1973), .CK(clk), .RN(
n5483), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1981), .CK(clk), .RN(
n5481), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1975), .CK(clk), .RN(
n2237), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1979), .CK(clk), .RN(
n5503), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1993), .CK(clk), .RN(
n5489), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2005), .CK(clk), .RN(
n5483), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1977), .CK(clk), .RN(
n2217), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1971), .CK(clk), .RN(
n5501), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1985), .CK(clk), .RN(
n2207), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1965), .CK(clk), .RN(
n5498), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1999), .CK(clk), .RN(
n5503), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2007), .CK(clk), .RN(
n5497), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1989), .CK(clk), .RN(
n5500), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2147), .CK(clk), .RN(
n5454), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n5494), .Q(
FPSENCOS_d_ff_Xn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1787), .CK(clk), .RN(n5502), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1784), .CK(clk), .RN(n5502), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1781), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1778), .CK(clk), .RN(n2237), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1732), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2036), .CK(clk), .RN(n5481), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2027), .CK(clk), .RN(n2237), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2051), .CK(clk), .RN(n5503), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2042), .CK(clk), .RN(n5480), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2033), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2054), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2048), .CK(clk), .RN(n5485), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1731), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n5497), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n2237), .Q(
dataA[24]) );
DFFSX1TS R_12_IP ( .D(n2281), .CK(clk), .SN(n5499), .QN(n5521) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2126), .CK(clk), .RN(n5478), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n5430) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2124), .CK(clk), .RN(n5477), .Q(
FPSENCOS_d_ff3_LUT_out[12]), .QN(n5427) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2122), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n5432) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1986), .CK(clk), .RN(n5479),
.Q(FPSENCOS_d_ff3_sh_x_out[10]), .QN(n5440) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1994), .CK(clk), .RN(n5481),
.Q(FPSENCOS_d_ff3_sh_x_out[6]), .QN(n5437) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1950), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_x_out[26]), .QN(n5445) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1951), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_x_out[25]), .QN(n5444) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1952), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_x_out[24]), .QN(n5443) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1964), .CK(clk), .RN(n2217),
.Q(FPSENCOS_d_ff3_sh_x_out[21]), .QN(n5442) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1988), .CK(clk), .RN(n5500),
.Q(FPSENCOS_d_ff3_sh_x_out[9]), .QN(n5439) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1990), .CK(clk), .RN(n5480),
.Q(FPSENCOS_d_ff3_sh_x_out[8]), .QN(n5438) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1982), .CK(clk), .RN(n5478),
.Q(FPSENCOS_d_ff3_sh_x_out[12]), .QN(n5441) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1998), .CK(clk), .RN(n5487),
.Q(FPSENCOS_d_ff3_sh_x_out[4]), .QN(n5436) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2002), .CK(clk), .RN(n5491),
.Q(FPSENCOS_d_ff3_sh_x_out[2]), .QN(n5435) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2004), .CK(clk), .RN(n5500),
.Q(FPSENCOS_d_ff3_sh_x_out[1]), .QN(n5434) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2120), .CK(clk), .RN(n2207), .Q(
FPSENCOS_d_ff3_LUT_out[21]), .QN(n5428) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1953), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_x_out[23]), .QN(n5429) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n5478), .Q(
FPSENCOS_d_ff_Xn[31]), .QN(n5388) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1901), .CK(clk), .RN(
n5487), .Q(FPSENCOS_d_ff2_Y[4]), .QN(n5408) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1903), .CK(clk), .RN(
n5477), .Q(FPSENCOS_d_ff2_Y[3]), .QN(n5407) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1905), .CK(clk), .RN(
n5480), .Q(FPSENCOS_d_ff2_Y[2]), .QN(n5406) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1907), .CK(clk), .RN(
n5490), .Q(FPSENCOS_d_ff2_Y[1]), .QN(n5405) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1909), .CK(clk), .RN(
n5500), .Q(FPSENCOS_d_ff2_Y[0]), .QN(n5404) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1893), .CK(clk), .RN(
n5480), .Q(FPSENCOS_d_ff2_Y[8]), .QN(n5412) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1895), .CK(clk), .RN(
n5491), .Q(FPSENCOS_d_ff2_Y[7]), .QN(n5411) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1897), .CK(clk), .RN(
n5481), .Q(FPSENCOS_d_ff2_Y[6]), .QN(n5410) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1899), .CK(clk), .RN(
n5490), .Q(FPSENCOS_d_ff2_Y[5]), .QN(n5409) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1865), .CK(clk), .RN(
n5499), .Q(FPSENCOS_d_ff2_Y[22]), .QN(n5426) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1869), .CK(clk), .RN(
n5483), .Q(FPSENCOS_d_ff2_Y[20]), .QN(n5424) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1871), .CK(clk), .RN(
n5487), .Q(FPSENCOS_d_ff2_Y[19]), .QN(n5423) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1873), .CK(clk), .RN(
n5486), .Q(FPSENCOS_d_ff2_Y[18]), .QN(n5422) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1875), .CK(clk), .RN(
n5483), .Q(FPSENCOS_d_ff2_Y[17]), .QN(n5421) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1877), .CK(clk), .RN(
n5479), .Q(FPSENCOS_d_ff2_Y[16]), .QN(n5420) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1879), .CK(clk), .RN(
n5503), .Q(FPSENCOS_d_ff2_Y[15]), .QN(n5419) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1881), .CK(clk), .RN(
n5487), .Q(FPSENCOS_d_ff2_Y[14]), .QN(n5418) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1883), .CK(clk), .RN(
n5481), .Q(FPSENCOS_d_ff2_Y[13]), .QN(n5417) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1885), .CK(clk), .RN(
n5479), .Q(FPSENCOS_d_ff2_Y[12]), .QN(n5416) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1887), .CK(clk), .RN(
n5480), .Q(FPSENCOS_d_ff2_Y[11]), .QN(n5415) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1889), .CK(clk), .RN(
n5479), .Q(FPSENCOS_d_ff2_Y[10]), .QN(n5414) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1891), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_Y[9]), .QN(n5413) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n1578), .CK(clk),
.RN(n5503), .Q(FPMULT_P_Sgf[25]), .QN(n5385) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n1580), .CK(clk),
.RN(n5482), .Q(FPMULT_P_Sgf[27]), .QN(n5383) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n1582), .CK(clk),
.RN(n5487), .Q(FPMULT_P_Sgf[29]), .QN(n5403) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n1583), .CK(clk),
.RN(n5503), .Q(FPMULT_P_Sgf[30]), .QN(n5402) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n1584), .CK(clk),
.RN(n5478), .Q(FPMULT_P_Sgf[31]), .QN(n5401) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n1585), .CK(clk),
.RN(n5482), .Q(FPMULT_P_Sgf[32]), .QN(n5400) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n1586), .CK(clk),
.RN(n5487), .Q(FPMULT_P_Sgf[33]), .QN(n5399) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n1587), .CK(clk),
.RN(n5503), .Q(FPMULT_P_Sgf[34]), .QN(n5398) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n1588), .CK(clk),
.RN(n5482), .Q(FPMULT_P_Sgf[35]), .QN(n5397) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n1589), .CK(clk),
.RN(n5488), .Q(FPMULT_P_Sgf[36]), .QN(n5396) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n1590), .CK(clk),
.RN(n5478), .Q(FPMULT_P_Sgf[37]), .QN(n5395) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n1591), .CK(clk),
.RN(n5479), .Q(FPMULT_P_Sgf[38]), .QN(n5394) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n1592), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[39]), .QN(n5393) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n1593), .CK(clk),
.RN(n5478), .Q(FPMULT_P_Sgf[40]), .QN(n5392) );
ADDFX1TS intadd_478_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n4441), .CI(
intadd_478_n3), .CO(intadd_478_n2), .S(intadd_478_SUM_1_) );
ADDFX1TS DP_OP_26J210_123_9022_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n2239), .CI(DP_OP_26J210_123_9022_n18), .CO(DP_OP_26J210_123_9022_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
ADDFX1TS intadd_477_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n5213), .CI(
intadd_477_n2), .CO(intadd_477_n1), .S(intadd_477_SUM_2_) );
ADDFX1TS DP_OP_26J210_123_9022_U7 ( .A(DP_OP_26J210_123_9022_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .CI(DP_OP_26J210_123_9022_n7), .CO(
DP_OP_26J210_123_9022_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_26J210_123_9022_U6 ( .A(DP_OP_26J210_123_9022_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .CI(DP_OP_26J210_123_9022_n6), .CO(
DP_OP_26J210_123_9022_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_26J210_123_9022_U4 ( .A(n2239), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .CI(DP_OP_26J210_123_9022_n4), .CO(
DP_OP_26J210_123_9022_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1577), .CK(clk),
.RN(n5487), .Q(FPMULT_P_Sgf[24]), .QN(n5386) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n1581), .CK(clk),
.RN(n2207), .Q(FPMULT_P_Sgf[28]), .QN(n5382) );
DFFSX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n2220), .CK(clk),
.SN(n5508), .Q(DP_OP_453J210_122_681_n2030), .QN(FPMULT_Op_MY[13]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1669), .CK(clk),
.RN(n5506), .Q(FPMULT_Op_MX[10]), .QN(n2200) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1668), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[9]), .QN(n2199) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1645), .CK(clk),
.RN(n5511), .Q(FPMULT_Op_MY[18]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1647), .CK(clk),
.RN(n5505), .Q(FPMULT_Op_MY[20]) );
CMPR32X2TS DP_OP_26J210_123_9022_U8 ( .A(DP_OP_26J210_123_9022_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J210_123_9022_n8), .CO(
DP_OP_26J210_123_9022_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2145), .CK(clk), .RN(
n5457), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2305) );
CMPR32X2TS DP_OP_26J210_123_9022_U5 ( .A(DP_OP_26J210_123_9022_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J210_123_9022_n5), .CO(
DP_OP_26J210_123_9022_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2148), .CK(clk), .RN(
n5460), .Q(busy), .QN(n5517) );
CMPR32X2TS DP_OP_26J210_123_9022_U3 ( .A(n2239), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J210_123_9022_n3), .CO(
DP_OP_26J210_123_9022_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS intadd_478_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n5314), .C(
intadd_478_CI), .CO(intadd_478_n3), .S(intadd_478_SUM_0_) );
CMPR32X2TS DP_OP_26J210_123_9022_U2 ( .A(n2239), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J210_123_9022_n2), .CO(
DP_OP_26J210_123_9022_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2077), .CK(clk), .RN(
n3738), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2198) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2144), .CK(clk), .RN(
n5476), .Q(n2299), .QN(n5514) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2150), .CK(clk), .RN(
n5454), .QN(n2312) );
CMPR32X2TS intadd_478_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n5213), .C(
intadd_478_n2), .CO(intadd_478_n1), .S(intadd_478_SUM_2_) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2146), .CK(clk), .RN(
n5474), .Q(n2197), .QN(n5513) );
BUFX8TS U2219 ( .A(n2237), .Y(n5503) );
AOI222X1TS U2220 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n3934) );
AOI222X1TS U2221 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n3939) );
AOI222X1TS U2222 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n3947) );
AOI222X1TS U2223 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n3948) );
AOI222X1TS U2224 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n3946) );
AOI222X1TS U2225 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n3944) );
AOI222X1TS U2226 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n3925)
);
AOI222X1TS U2227 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n3933) );
AOI222X1TS U2228 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n3930) );
AOI222X1TS U2229 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n3931) );
AOI222X1TS U2230 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n3924) );
AOI222X1TS U2231 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n3943) );
AOI222X1TS U2232 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n3945) );
AOI222X1TS U2233 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n3941)
);
AOI222X1TS U2234 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n3912)
);
AOI222X1TS U2235 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n3911)
);
AOI222X1TS U2236 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n3921) );
AOI222X1TS U2237 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n3923) );
AOI222X1TS U2238 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n3936) );
AOI222X1TS U2239 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n3927) );
AOI222X1TS U2240 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n3928) );
AOI222X1TS U2241 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4488), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n3929)
);
AOI222X1TS U2242 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n3937), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n4488), .Y(n3938)
);
AOI222X1TS U2243 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4488), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n3917)
);
AOI222X1TS U2244 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4488), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n3916)
);
AOI222X1TS U2245 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4488), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n3913), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n3914)
);
AOI222X1TS U2246 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n3922) );
AOI222X1TS U2247 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n3926) );
AOI211X1TS U2248 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n4506), .B0(n3817),
.C0(n3816), .Y(n3818) );
NAND2X6TS U2249 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(n5514), .Y(n5163) );
BUFX4TS U2250 ( .A(n4228), .Y(n4300) );
CLKINVX6TS U2251 ( .A(n4556), .Y(n4149) );
AOI211X2TS U2252 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n4437), .B0(
n4384), .C0(n4094), .Y(n4212) );
CMPR32X2TS U2253 ( .A(n4699), .B(n4698), .C(n4697), .CO(n4693), .S(n4700) );
CMPR32X2TS U2254 ( .A(n4707), .B(n4706), .C(n4705), .CO(n4701), .S(n4708) );
CMPR32X2TS U2255 ( .A(n3112), .B(n3111), .C(n3110), .CO(n3131), .S(n3128) );
CMPR32X2TS U2256 ( .A(n2971), .B(n2970), .C(n2969), .CO(n3157), .S(n3010) );
CMPR32X2TS U2257 ( .A(n3160), .B(n3159), .C(n3158), .CO(n3185), .S(n3156) );
CMPR32X2TS U2258 ( .A(n3149), .B(n3148), .C(n3147), .CO(n3198), .S(n3168) );
CMPR32X2TS U2259 ( .A(n3022), .B(n3021), .C(n3020), .CO(n3019), .S(n3045) );
CMPR32X2TS U2260 ( .A(n3025), .B(n3024), .C(n3023), .CO(n3017), .S(n3044) );
CMPR32X2TS U2261 ( .A(n3115), .B(n3114), .C(n3113), .CO(n3121), .S(n3123) );
CMPR32X2TS U2262 ( .A(n3054), .B(n3053), .C(n3052), .CO(n3043), .S(n3117) );
CMPR32X2TS U2263 ( .A(n3069), .B(n3068), .C(n3067), .CO(n3097), .S(n3070) );
NOR2XLTS U2264 ( .A(n3189), .B(n3315), .Y(n2958) );
NOR2XLTS U2265 ( .A(n3189), .B(n3270), .Y(n2990) );
NOR2XLTS U2266 ( .A(n3238), .B(n3295), .Y(n3144) );
NOR2XLTS U2267 ( .A(n3212), .B(n2199), .Y(n3192) );
NOR2XLTS U2268 ( .A(n3291), .B(n3315), .Y(n3237) );
NOR2XLTS U2269 ( .A(DP_OP_453J210_122_681_n2030), .B(n3566), .Y(n2351) );
NOR2XLTS U2270 ( .A(n3314), .B(n3193), .Y(n2973) );
NOR2XLTS U2271 ( .A(n3238), .B(n3245), .Y(n2976) );
NOR2XLTS U2272 ( .A(n3238), .B(n3193), .Y(n3021) );
NOR2XLTS U2273 ( .A(n3339), .B(n3245), .Y(n3241) );
NOR2XLTS U2274 ( .A(n3314), .B(n3164), .Y(n2961) );
NOR2XLTS U2275 ( .A(n3212), .B(n3193), .Y(n3053) );
NOR2XLTS U2276 ( .A(n3212), .B(n3213), .Y(n3036) );
NOR2XLTS U2277 ( .A(n3339), .B(n3295), .Y(n3290) );
NOR2XLTS U2278 ( .A(n3339), .B(n3315), .Y(n3309) );
NOR2XLTS U2279 ( .A(n3339), .B(n2200), .Y(n3340) );
NOR2XLTS U2280 ( .A(n3212), .B(n3077), .Y(n3095) );
OAI21XLTS U2281 ( .A0(n3422), .A1(n3428), .B0(n3423), .Y(n3139) );
NOR2XLTS U2282 ( .A(n3565), .B(n3291), .Y(n3120) );
OR2X1TS U2283 ( .A(n2559), .B(n2558), .Y(n2325) );
OAI21XLTS U2284 ( .A0(n3623), .A1(n3625), .B0(n3626), .Y(n3591) );
OR2X1TS U2285 ( .A(n2465), .B(n2464), .Y(n2321) );
OAI21XLTS U2286 ( .A0(n3486), .A1(n3489), .B0(n3490), .Y(n2564) );
OAI21XLTS U2287 ( .A0(n3488), .A1(n3487), .B0(n3486), .Y(n3493) );
OAI21XLTS U2288 ( .A0(n3665), .A1(n3661), .B0(n3662), .Y(n3660) );
OAI21XLTS U2289 ( .A0(n3431), .A1(n3427), .B0(n3428), .Y(n3426) );
CLKXOR2X2TS U2290 ( .A(n2242), .B(FPMULT_Op_MY[22]), .Y(n2201) );
INVX1TS U2291 ( .A(n3634), .Y(n3590) );
OAI21X1TS U2292 ( .A0(n3684), .A1(n3680), .B0(n3681), .Y(n3679) );
CLKBUFX2TS U2293 ( .A(n4061), .Y(n2235) );
NAND3XLTS U2294 ( .A(n4515), .B(n4514), .C(n4516), .Y(n1838) );
NAND3XLTS U2295 ( .A(n4520), .B(n4519), .C(n4532), .Y(n1832) );
NAND3XLTS U2296 ( .A(n4544), .B(n4543), .C(n4542), .Y(n1823) );
NAND3XLTS U2297 ( .A(n4512), .B(n4511), .C(n4521), .Y(n1840) );
NAND3XLTS U2298 ( .A(n4523), .B(n4522), .C(n4521), .Y(n1831) );
NAND3XLTS U2299 ( .A(n4529), .B(n4528), .C(n4527), .Y(n1829) );
NAND3XLTS U2300 ( .A(n4537), .B(n4536), .C(n4542), .Y(n1826) );
NAND3XLTS U2301 ( .A(n4547), .B(n4546), .C(n4551), .Y(n1818) );
NAND3XLTS U2302 ( .A(n4508), .B(n4507), .C(n4527), .Y(n1842) );
NAND3XLTS U2303 ( .A(n4549), .B(n4548), .C(n4551), .Y(n1817) );
NAND3XLTS U2304 ( .A(n4525), .B(n4524), .C(n4539), .Y(n1830) );
NAND3XLTS U2305 ( .A(n4534), .B(n4533), .C(n4532), .Y(n1827) );
NAND3XLTS U2306 ( .A(n4531), .B(n4530), .C(n4539), .Y(n1828) );
NAND3XLTS U2307 ( .A(n4541), .B(n4540), .C(n4539), .Y(n1825) );
NAND3XLTS U2308 ( .A(n4518), .B(n4517), .C(n4516), .Y(n1834) );
NAND3XLTS U2309 ( .A(n4553), .B(n4552), .C(n4551), .Y(n1816) );
INVX6TS U2310 ( .A(n2209), .Y(n2202) );
NOR2X6TS U2311 ( .A(n2312), .B(n4950), .Y(n3907) );
OAI21X1TS U2312 ( .A0(n3444), .A1(n3450), .B0(n3445), .Y(n3129) );
CLKINVX6TS U2313 ( .A(n4505), .Y(n4488) );
BUFX6TS U2314 ( .A(n3749), .Y(n3738) );
NOR2X8TS U2315 ( .A(rst), .B(n4440), .Y(n3749) );
OAI21XLTS U2316 ( .A0(n4363), .A1(n5312), .B0(n4346), .Y(op_result[27]) );
OAI21XLTS U2317 ( .A0(n4363), .A1(n5311), .B0(n4342), .Y(op_result[28]) );
OAI21XLTS U2318 ( .A0(n4363), .A1(n5219), .B0(n4335), .Y(op_result[31]) );
CLKINVX6TS U2319 ( .A(n3743), .Y(n3744) );
OAI21X1TS U2320 ( .A0(n2700), .A1(n2724), .B0(n2701), .Y(n2654) );
NOR2X1TS U2321 ( .A(n3146), .B(DP_OP_453J210_122_681_n667), .Y(n3194) );
NOR2X1TS U2322 ( .A(n3189), .B(n2200), .Y(n3179) );
NOR2X1TS U2323 ( .A(n3291), .B(n3270), .Y(n3196) );
NOR2X1TS U2324 ( .A(n3564), .B(DP_OP_453J210_122_681_n667), .Y(n2959) );
NOR2X1TS U2325 ( .A(n3348), .B(n3164), .Y(n3190) );
NOR2X1TS U2326 ( .A(n3146), .B(n2200), .Y(n3150) );
INVX6TS U2327 ( .A(n4083), .Y(n2203) );
NOR2X1TS U2328 ( .A(n3189), .B(n2199), .Y(n3151) );
NOR2X1TS U2329 ( .A(n3189), .B(n3295), .Y(n2953) );
BUFX6TS U2330 ( .A(n5451), .Y(n2204) );
INVX6TS U2331 ( .A(n3756), .Y(n2205) );
BUFX4TS U2332 ( .A(n4568), .Y(n4473) );
BUFX6TS U2333 ( .A(n5163), .Y(n2206) );
BUFX6TS U2334 ( .A(n2217), .Y(n2237) );
BUFX6TS U2335 ( .A(n2217), .Y(n5493) );
OR3X6TS U2336 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n5244), .Y(n4569) );
INVX3TS U2337 ( .A(FPMULT_Op_MY[10]), .Y(n3339) );
INVX3TS U2338 ( .A(FPMULT_Op_MY[9]), .Y(n3327) );
CLKBUFX2TS U2339 ( .A(FPMULT_Op_MX[0]), .Y(n2253) );
BUFX6TS U2340 ( .A(n2217), .Y(n2207) );
AO22X1TS U2341 ( .A0(n4809), .A1(FPMULT_P_Sgf[47]), .B0(n4671), .B1(n3722),
.Y(n1552) );
AO22X1TS U2342 ( .A0(n4809), .A1(FPMULT_P_Sgf[45]), .B0(n4781), .B1(n4670),
.Y(n1598) );
AO22X1TS U2343 ( .A0(n4782), .A1(FPMULT_P_Sgf[44]), .B0(n4796), .B1(n4674),
.Y(n1597) );
AO22X1TS U2344 ( .A0(n4809), .A1(FPMULT_P_Sgf[43]), .B0(n4808), .B1(n4676),
.Y(n1596) );
AO22X1TS U2345 ( .A0(n4782), .A1(FPMULT_P_Sgf[42]), .B0(n4781), .B1(n4679),
.Y(n1595) );
AO22X1TS U2346 ( .A0(n4809), .A1(FPMULT_P_Sgf[41]), .B0(n4781), .B1(n4681),
.Y(n1594) );
AO22X1TS U2347 ( .A0(n4782), .A1(FPMULT_P_Sgf[40]), .B0(n4781), .B1(n4684),
.Y(n1593) );
AO22X1TS U2348 ( .A0(n4809), .A1(FPMULT_P_Sgf[39]), .B0(n4781), .B1(n4686),
.Y(n1592) );
AO22X1TS U2349 ( .A0(n4782), .A1(FPMULT_P_Sgf[38]), .B0(n4781), .B1(n4688),
.Y(n1591) );
AO22X1TS U2350 ( .A0(n4809), .A1(FPMULT_P_Sgf[37]), .B0(n4781), .B1(n4692),
.Y(n1590) );
AO22X1TS U2351 ( .A0(n4782), .A1(FPMULT_P_Sgf[36]), .B0(n4781), .B1(n4696),
.Y(n1589) );
ADDFX1TS U2352 ( .A(n4715), .B(n4714), .CI(n4713), .CO(n4709), .S(n4716) );
ADDFX1TS U2353 ( .A(n4723), .B(n4722), .CI(n4721), .CO(n4717), .S(n4724) );
OAI21X1TS U2354 ( .A0(n3605), .A1(n3601), .B0(n3602), .Y(n3600) );
OAI21X1TS U2355 ( .A0(n3616), .A1(n3612), .B0(n3613), .Y(n3611) );
OAI21X1TS U2356 ( .A0(n3637), .A1(n3624), .B0(n3623), .Y(n3629) );
OAI21X1TS U2357 ( .A0(n3637), .A1(n3630), .B0(n3634), .Y(n3633) );
AOI21X1TS U2358 ( .A0(n3592), .A1(n3622), .B0(n3591), .Y(n3621) );
NOR2X1TS U2359 ( .A(n3607), .B(n3612), .Y(n3594) );
OAI21X1TS U2360 ( .A0(n3607), .A1(n3613), .B0(n3608), .Y(n3593) );
ADDFX1TS U2361 ( .A(n4755), .B(n4754), .CI(n4753), .CO(n4749), .S(n4756) );
OAI21X1TS U2362 ( .A0(n3588), .A1(n3638), .B0(n3587), .Y(n3622) );
AOI21X1TS U2363 ( .A0(n3585), .A1(n3655), .B0(n3584), .Y(n3638) );
ADDFX1TS U2364 ( .A(n4763), .B(n4762), .CI(n4761), .CO(n4757), .S(n4764) );
OAI21X1TS U2365 ( .A0(n3666), .A1(n3583), .B0(n3582), .Y(n3655) );
NAND2X1TS U2366 ( .A(DP_OP_453J210_122_681_n288), .B(
DP_OP_453J210_122_681_n298), .Y(n3651) );
AOI21X1TS U2367 ( .A0(n3580), .A1(n3674), .B0(n3579), .Y(n3666) );
ADDFX1TS U2368 ( .A(n4771), .B(n4770), .CI(n4769), .CO(n4765), .S(n4772) );
NOR2XLTS U2369 ( .A(n4212), .B(n4219), .Y(n4123) );
INVX1TS U2370 ( .A(DP_OP_453J210_122_681_n404), .Y(n4746) );
NOR2XLTS U2371 ( .A(n4118), .B(n4219), .Y(n4119) );
AO22XLTS U2372 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[1]), .A1(n4954), .B0(
n2203), .B1(n4383), .Y(n4117) );
XNOR2X1TS U2373 ( .A(n3501), .B(n3500), .Y(n4690) );
XOR2X1TS U2374 ( .A(n3513), .B(n3512), .Y(n4698) );
XOR2X1TS U2375 ( .A(n3506), .B(n3505), .Y(n4694) );
INVX2TS U2376 ( .A(n4774), .Y(DP_OP_453J210_122_681_n411) );
NOR2X1TS U2377 ( .A(n3487), .B(n3489), .Y(n2565) );
XNOR2X1TS U2378 ( .A(n3517), .B(n3516), .Y(n4702) );
OAI21X1TS U2379 ( .A0(n3418), .A1(n3405), .B0(n3404), .Y(n3408) );
XOR2X1TS U2380 ( .A(n3528), .B(n3527), .Y(n4710) );
OAI21X1TS U2381 ( .A0(n3418), .A1(n3396), .B0(n3395), .Y(n3401) );
XOR2X1TS U2382 ( .A(n3533), .B(n3532), .Y(n4714) );
OAI21X1TS U2383 ( .A0(n3418), .A1(n3414), .B0(n3415), .Y(n3413) );
AOI21X1TS U2384 ( .A0(n3518), .A1(n2494), .B0(n2493), .Y(n3494) );
OAI21X1TS U2385 ( .A0(n3497), .A1(n3503), .B0(n3498), .Y(n2503) );
OAI21X1TS U2386 ( .A0(n3395), .A1(n3397), .B0(n3398), .Y(n3261) );
ADDFX1TS U2387 ( .A(n2683), .B(n2682), .CI(DP_OP_453J210_122_681_n232), .CO(
DP_OP_453J210_122_681_n227), .S(DP_OP_453J210_122_681_n228) );
NOR2X1TS U2388 ( .A(n3396), .B(n3397), .Y(n3262) );
ADDFX1TS U2389 ( .A(n2839), .B(n2838), .CI(n2837), .CO(
DP_OP_453J210_122_681_n385), .S(DP_OP_453J210_122_681_n386) );
INVX4TS U2390 ( .A(n4042), .Y(n2208) );
ADDFX1TS U2391 ( .A(n2813), .B(n2812), .CI(n2811), .CO(
DP_OP_453J210_122_681_n356), .S(DP_OP_453J210_122_681_n357) );
ADDFX1TS U2392 ( .A(n2720), .B(n2719), .CI(n2718), .CO(
DP_OP_453J210_122_681_n247), .S(DP_OP_453J210_122_681_n248) );
ADDFX1TS U2393 ( .A(n2523), .B(n2522), .CI(n2521), .CO(n2556), .S(n2502) );
ADDFX1TS U2394 ( .A(n2540), .B(n2539), .CI(n2538), .CO(n2558), .S(n2557) );
ADDFX1TS U2395 ( .A(n2543), .B(n2542), .CI(n2541), .CO(n2563), .S(n2559) );
ADDFX1TS U2396 ( .A(n2568), .B(n2567), .CI(n2566), .CO(n2582), .S(n2562) );
ADDFX1TS U2397 ( .A(n2585), .B(n2584), .CI(n2583), .CO(n2595), .S(n2581) );
ADDFX1TS U2398 ( .A(n2798), .B(n2797), .CI(n2796), .CO(
DP_OP_453J210_122_681_n317), .S(DP_OP_453J210_122_681_n318) );
ADDFX1TS U2399 ( .A(n2778), .B(n2777), .CI(n2776), .CO(
DP_OP_453J210_122_681_n295), .S(DP_OP_453J210_122_681_n296) );
ADDFX1TS U2400 ( .A(n2787), .B(n2786), .CI(n2785), .CO(
DP_OP_453J210_122_681_n306), .S(DP_OP_453J210_122_681_n307) );
ADDFX1TS U2401 ( .A(n2760), .B(n2759), .CI(n2758), .CO(
DP_OP_453J210_122_681_n284), .S(DP_OP_453J210_122_681_n285) );
ADDFX1TS U2402 ( .A(n2740), .B(n2739), .CI(n2738), .CO(
DP_OP_453J210_122_681_n255), .S(DP_OP_453J210_122_681_n256) );
ADDFX1TS U2403 ( .A(n2369), .B(n2368), .CI(n2367), .CO(n2501), .S(n2500) );
NOR2X4TS U2404 ( .A(n4229), .B(n4418), .Y(n4238) );
NOR2X4TS U2405 ( .A(operation[1]), .B(n4513), .Y(n4285) );
ADDFX1TS U2406 ( .A(n2818), .B(n2817), .CI(n2816), .CO(n2811), .S(
DP_OP_453J210_122_681_n367) );
ADDFX1TS U2407 ( .A(n2801), .B(n2800), .CI(n2799), .CO(n2796), .S(
DP_OP_453J210_122_681_n329) );
ADDFX1TS U2408 ( .A(n2846), .B(n2845), .CI(n2844), .CO(
DP_OP_453J210_122_681_n392), .S(DP_OP_453J210_122_681_n393) );
NAND3XLTS U2409 ( .A(n4078), .B(n5214), .C(n5191), .Y(n4074) );
ADDFX1TS U2410 ( .A(n2622), .B(n2621), .CI(n2620), .CO(n2628), .S(n2617) );
ADDFX1TS U2411 ( .A(n2386), .B(n2385), .CI(n2384), .CO(n2499), .S(n2498) );
ADDFX1TS U2412 ( .A(n2612), .B(n2611), .CI(n2610), .CO(n2618), .S(n2608) );
ADDFX1TS U2413 ( .A(n2599), .B(n2598), .CI(n2597), .CO(n2609), .S(n2594) );
ADDFX1TS U2414 ( .A(n2555), .B(n2554), .CI(n2553), .CO(n2566), .S(n2541) );
ADDFX1TS U2415 ( .A(n2529), .B(n2528), .CI(n2527), .CO(n2542), .S(n2538) );
ADDFX1TS U2416 ( .A(n2512), .B(n2511), .CI(n2510), .CO(n2539), .S(n2521) );
ADDFX1TS U2417 ( .A(n2366), .B(n2365), .CI(n2364), .CO(n2522), .S(n2367) );
ADDFX1TS U2418 ( .A(n2580), .B(n2579), .CI(n2578), .CO(n2583), .S(n2567) );
BUFX6TS U2419 ( .A(n4509), .Y(n2209) );
ADDFX1TS U2420 ( .A(n2372), .B(n2371), .CI(n2370), .CO(n2364), .S(n2386) );
ADDFX1TS U2421 ( .A(n2509), .B(n2508), .CI(n2507), .CO(n2540), .S(n2523) );
ADDFX1TS U2422 ( .A(n2383), .B(n2382), .CI(n2381), .CO(n2368), .S(n2384) );
ADDFX1TS U2423 ( .A(n2607), .B(n2606), .CI(n2605), .CO(n2610), .S(n2598) );
ADDFX1TS U2424 ( .A(n2526), .B(n2525), .CI(n2524), .CO(n2543), .S(n2527) );
ADDFX1TS U2425 ( .A(n2355), .B(n2354), .CI(n2353), .CO(n2510), .S(n2369) );
ADDFX1TS U2426 ( .A(n2593), .B(n2592), .CI(n2591), .CO(n2597), .S(n2584) );
ADDFX1TS U2427 ( .A(n2546), .B(n2545), .CI(n2544), .CO(n2568), .S(n2553) );
ADDFX1TS U2428 ( .A(n2571), .B(n2570), .CI(n2569), .CO(n2585), .S(n2578) );
ADDFX1TS U2429 ( .A(n2402), .B(n2401), .CI(n2400), .CO(n2497), .S(n2496) );
ADDFX1TS U2430 ( .A(n2616), .B(n2615), .CI(n2614), .CO(n2620), .S(n2611) );
ADDFX1TS U2431 ( .A(n2307), .B(n2201), .CI(n2644), .CO(n2648), .S(n2641) );
ADDFX1TS U2432 ( .A(n4738), .B(n4805), .CI(n3561), .CO(n3572), .S(n3570) );
ADDFX1TS U2433 ( .A(n2639), .B(n2638), .CI(n2637), .CO(n2642), .S(n2627) );
BUFX4TS U2434 ( .A(n3913), .Y(n3937) );
NOR2BX2TS U2435 ( .AN(n3983), .B(n4026), .Y(n3984) );
ADDFX1TS U2436 ( .A(n3287), .B(n3286), .CI(n3285), .CO(n3303), .S(n3283) );
ADDFX1TS U2437 ( .A(n2463), .B(n2462), .CI(n2461), .CO(n2464), .S(n2437) );
ADDFX1TS U2438 ( .A(n3202), .B(n3201), .CI(n3200), .CO(n3254), .S(n3253) );
ADDFX1TS U2439 ( .A(n2460), .B(n2459), .CI(n2458), .CO(n2466), .S(n2465) );
ADDFX1TS U2440 ( .A(n2319), .B(n2573), .CI(n2572), .CO(n2592), .S(n2580) );
ADDFX1TS U2441 ( .A(n2485), .B(n2484), .CI(n2483), .CO(n2491), .S(n2490) );
ADDFX1TS U2442 ( .A(n2287), .B(n2601), .CI(n2600), .CO(n2612), .S(n2605) );
ADDFX1TS U2443 ( .A(n2488), .B(n2487), .CI(n2486), .CO(n2489), .S(n2467) );
CLKXOR2X2TS U2444 ( .A(n2775), .B(n2774), .Y(n2925) );
ADDFX1TS U2445 ( .A(n3173), .B(n3172), .CI(n3171), .CO(n3252), .S(n3138) );
ADDFX1TS U2446 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MX[16]), .CI(n2590),
.CO(n2606), .S(n2593) );
ADDFX1TS U2447 ( .A(n2278), .B(n2352), .CI(n2351), .CO(n2508), .S(n2353) );
ADDFX1TS U2448 ( .A(n3051), .B(n3050), .CI(n3049), .CO(n3133), .S(n3132) );
ADDFX1TS U2449 ( .A(n2289), .B(n2520), .CI(n2519), .CO(n2524), .S(n2507) );
ADDFX1TS U2450 ( .A(n2399), .B(n2398), .CI(n2397), .CO(n2385), .S(n2400) );
ADDFX1TS U2451 ( .A(n3034), .B(n3033), .CI(n3032), .CO(n3135), .S(n3134) );
ADDFX1TS U2452 ( .A(n3265), .B(n3264), .CI(n3263), .CO(n3284), .S(n3259) );
ADDFX1TS U2453 ( .A(n3228), .B(n3227), .CI(n3226), .CO(n3256), .S(n3255) );
ADDFX1TS U2454 ( .A(n2289), .B(FPMULT_Op_MX[14]), .CI(n2537), .CO(n2545),
.S(n2525) );
ADDFX1TS U2455 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[13]), .CI(n2552),
.CO(n2569), .S(n2544) );
ADDFX1TS U2456 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MX[20]), .CI(n2640),
.CO(n2644), .S(n2638) );
ADDFX1TS U2457 ( .A(n2473), .B(n2472), .CI(n2471), .CO(n2495), .S(n2492) );
ADDFX1TS U2458 ( .A(n2361), .B(n2360), .CI(n2359), .CO(n2366), .S(n2382) );
ADDFX1TS U2459 ( .A(n3013), .B(n3012), .CI(n3011), .CO(n3137), .S(n3136) );
ADDFX1TS U2460 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[18]), .CI(n2613),
.CO(n2622), .S(n2614) );
ADDFX1TS U2461 ( .A(n2286), .B(n2626), .CI(n2625), .CO(n2637), .S(n2621) );
ADDFX1TS U2462 ( .A(n3231), .B(n3230), .CI(n3229), .CO(n3260), .S(n3257) );
CLKXOR2X2TS U2463 ( .A(n2704), .B(n2703), .Y(n2943) );
ADDFX1TS U2464 ( .A(n2550), .B(n2549), .CI(n2548), .CO(n2579), .S(n2554) );
ADDFX1TS U2465 ( .A(n3121), .B(n3120), .CI(n3119), .CO(n3127), .S(n3126) );
ADDFX1TS U2466 ( .A(n3048), .B(n3047), .CI(n3046), .CO(n3033), .S(n3049) );
ADDFX1TS U2467 ( .A(n3282), .B(n3281), .CI(n3280), .CO(n3285), .S(n3264) );
ADDFX1TS U2468 ( .A(n2479), .B(n2478), .CI(n2477), .CO(n2484), .S(n2486) );
ADDFX1TS U2469 ( .A(n3185), .B(n3184), .CI(n3183), .CO(n3227), .S(n3200) );
NOR2XLTS U2470 ( .A(n2645), .B(FPMULT_Op_MX[22]), .Y(n2640) );
ADDFX1TS U2471 ( .A(n2482), .B(n2481), .CI(n2480), .CO(n2472), .S(n2483) );
ADDFX1TS U2472 ( .A(n3307), .B(n3306), .CI(n3305), .CO(n3320), .S(n3302) );
ADDFX1TS U2473 ( .A(n3157), .B(n3156), .CI(n3155), .CO(n3201), .S(n3171) );
ADDFX1TS U2474 ( .A(n3010), .B(n3009), .CI(n3008), .CO(n3172), .S(n3011) );
ADDFX1TS U2475 ( .A(n3031), .B(n3030), .CI(n3029), .CO(n3012), .S(n3032) );
ADDFX1TS U2476 ( .A(n2405), .B(n2404), .CI(n2403), .CO(n2397), .S(n2473) );
ADDFX1TS U2477 ( .A(n2457), .B(n2456), .CI(n2455), .CO(n2487), .S(n2458) );
ADDFX1TS U2478 ( .A(n3323), .B(n3322), .CI(n3321), .CO(n3333), .S(n3319) );
ADDFX1TS U2479 ( .A(n2411), .B(n2410), .CI(n2409), .CO(n2401), .S(n2471) );
ADDFX1TS U2480 ( .A(n2418), .B(n2417), .CI(n2416), .CO(n2436), .S(n2435) );
ADDFX1TS U2481 ( .A(n3208), .B(n3207), .CI(n3206), .CO(n3230), .S(n3226) );
ADDFX1TS U2482 ( .A(n3251), .B(n3250), .CI(n3249), .CO(n3263), .S(n3229) );
ADDFX1TS U2483 ( .A(n2389), .B(n2388), .CI(n2387), .CO(n2381), .S(n2402) );
ADDFX1TS U2484 ( .A(n3118), .B(n3117), .CI(n3116), .CO(n3112), .S(n3119) );
BUFX6TS U2485 ( .A(n3749), .Y(n2210) );
ADDFX1TS U2486 ( .A(n3060), .B(n3059), .CI(n3058), .CO(n3050), .S(n3110) );
ADDFX1TS U2487 ( .A(n2344), .B(n2343), .CI(n2342), .CO(n2512), .S(n2365) );
ADDFX1TS U2488 ( .A(n3124), .B(n3123), .CI(n3122), .CO(n3125), .S(n3106) );
ADDFX1TS U2489 ( .A(n2515), .B(n2514), .CI(n2513), .CO(n2529), .S(n2511) );
ADDFX1TS U2490 ( .A(n3102), .B(n3101), .CI(n3100), .CO(n3105), .S(n3104) );
ADDFX1TS U2491 ( .A(n3170), .B(n3169), .CI(n3168), .CO(n3183), .S(n3173) );
ADDFX1TS U2492 ( .A(n3199), .B(n3198), .CI(n3197), .CO(n3206), .S(n3202) );
ADDFX1TS U2493 ( .A(n2532), .B(n2531), .CI(n2530), .CO(n2555), .S(n2528) );
ADDFX1TS U2494 ( .A(n2588), .B(n2587), .CI(n2586), .CO(n2599), .S(n2591) );
ADDFX1TS U2495 ( .A(n2377), .B(n2376), .CI(n2375), .CO(n2383), .S(n2398) );
ADDFX1TS U2496 ( .A(n3016), .B(n3015), .CI(n3014), .CO(n3008), .S(n3034) );
AO22X1TS U2497 ( .A0(operation[1]), .A1(n4092), .B0(begin_operation), .B1(
n4431), .Y(n4223) );
ADDFX1TS U2498 ( .A(n3028), .B(n3027), .CI(n3026), .CO(n3030), .S(n3046) );
AO21XLTS U2499 ( .A0(n2430), .A1(n2271), .B0(n2300), .Y(n2548) );
ADDFX1TS U2500 ( .A(n2996), .B(n2995), .CI(n2994), .CO(n3155), .S(n3013) );
OAI21X1TS U2501 ( .A0(n2679), .A1(n2678), .B0(n2677), .Y(n2680) );
ADDFX1TS U2502 ( .A(n3301), .B(n3300), .CI(n3299), .CO(n3305), .S(n3286) );
ADDFX1TS U2503 ( .A(n3268), .B(n3267), .CI(n3266), .CO(n3287), .S(n3280) );
ADDFX1TS U2504 ( .A(n3188), .B(n3187), .CI(n3186), .CO(n3208), .S(n3184) );
ADDFX1TS U2505 ( .A(n3205), .B(n3204), .CI(n3203), .CO(n3231), .S(n3228) );
BUFX6TS U2506 ( .A(n4471), .Y(n4467) );
BUFX6TS U2507 ( .A(n3738), .Y(n2211) );
ADDFX1TS U2508 ( .A(n3234), .B(n3233), .CI(n3232), .CO(n3265), .S(n3249) );
ADDFX1TS U2509 ( .A(n2476), .B(n2475), .CI(n2474), .CO(n2409), .S(n2485) );
ADDFX1TS U2510 ( .A(n3318), .B(n3317), .CI(n3316), .CO(n3321), .S(n3306) );
INVX4TS U2511 ( .A(n2201), .Y(n2247) );
ADDFX1TS U2512 ( .A(n3167), .B(n3166), .CI(n3165), .CO(n3186), .S(n3170) );
ADDFX1TS U2513 ( .A(n2983), .B(n2982), .CI(n2981), .CO(n3158), .S(n2996) );
ADDFX1TS U2514 ( .A(n2986), .B(n2985), .CI(n2984), .CO(n3169), .S(n2995) );
ADDFX1TS U2515 ( .A(n2965), .B(n2964), .CI(n2963), .CO(n2969), .S(n3015) );
ADDFX1TS U2516 ( .A(n2999), .B(n2998), .CI(n2997), .CO(n2994), .S(n3031) );
ADDFX1TS U2517 ( .A(n3176), .B(n3175), .CI(n3174), .CO(n3205), .S(n3199) );
ADDFX1TS U2518 ( .A(n3019), .B(n3018), .CI(n3017), .CO(n3014), .S(n3048) );
ADDFX1TS U2519 ( .A(n3216), .B(n3215), .CI(n3214), .CO(n3250), .S(n3207) );
ADDFX1TS U2520 ( .A(n3225), .B(n3224), .CI(n3223), .CO(n3232), .S(n3204) );
ADDFX1TS U2521 ( .A(n3037), .B(n3036), .CI(n3035), .CO(n3026), .S(n3060) );
ADDFX1TS U2522 ( .A(n3045), .B(n3044), .CI(n3043), .CO(n3047), .S(n3058) );
ADDFX1TS U2523 ( .A(n3182), .B(n3181), .CI(n3180), .CO(n3203), .S(n3197) );
ADDFX1TS U2524 ( .A(n3057), .B(n3056), .CI(n3055), .CO(n3059), .S(n3116) );
ADDFX1TS U2525 ( .A(n3248), .B(n3247), .CI(n3246), .CO(n3266), .S(n3233) );
ADDFX1TS U2526 ( .A(n3276), .B(n3275), .CI(n3274), .CO(n3300), .S(n3282) );
ADDFX1TS U2527 ( .A(n3096), .B(n3095), .CI(n3094), .CO(n3124), .S(n3101) );
BUFX6TS U2528 ( .A(n3749), .Y(n2212) );
ADDFX1TS U2529 ( .A(n3099), .B(n3098), .CI(n3097), .CO(n3100), .S(n3072) );
ADDFX1TS U2530 ( .A(n3294), .B(n3293), .CI(n3292), .CO(n3317), .S(n3301) );
ADDFX1TS U2531 ( .A(n3337), .B(n3336), .CI(n3335), .CO(n3344), .S(n3332) );
NOR2X4TS U2532 ( .A(n4433), .B(n3981), .Y(n4018) );
INVX3TS U2533 ( .A(n2219), .Y(n2246) );
INVX4TS U2534 ( .A(n2535), .Y(n2271) );
ADDFX1TS U2535 ( .A(n3080), .B(n3079), .CI(n3078), .CO(n3094), .S(n3098) );
ADDFX1TS U2536 ( .A(n3042), .B(n3041), .CI(n3040), .CO(n3035), .S(n3055) );
ADDFX1TS U2537 ( .A(n3093), .B(n3092), .CI(n3091), .CO(n3114), .S(n3102) );
ADDFX1TS U2538 ( .A(n3083), .B(n3082), .CI(n3081), .CO(n3056), .S(n3115) );
ADDFX1TS U2539 ( .A(n3090), .B(n3089), .CI(n3088), .CO(n3118), .S(n3113) );
ADDFX1TS U2540 ( .A(n3219), .B(n3218), .CI(n3217), .CO(n3234), .S(n3214) );
ADDFX1TS U2541 ( .A(n3241), .B(n3240), .CI(n3239), .CO(n3281), .S(n3251) );
ADDFX1TS U2542 ( .A(n3145), .B(n3144), .CI(n3143), .CO(n3175), .S(n3165) );
ADDFX1TS U2543 ( .A(n3222), .B(n3221), .CI(n3220), .CO(n3247), .S(n3225) );
ADDFX1TS U2544 ( .A(n3237), .B(n3236), .CI(n3235), .CO(n3276), .S(n3246) );
ADDFX1TS U2545 ( .A(n3290), .B(n3289), .CI(n3288), .CO(n3307), .S(n3299) );
ADDFX1TS U2546 ( .A(n3273), .B(n3272), .CI(n3271), .CO(n3292), .S(n3275) );
ADDFX1TS U2547 ( .A(n3154), .B(n3153), .CI(n3152), .CO(n3180), .S(n3147) );
ADDFX1TS U2548 ( .A(n3310), .B(n3309), .CI(n3308), .CO(n3323), .S(n3316) );
ADDFX1TS U2549 ( .A(n3331), .B(n3330), .CI(n3329), .CO(n3335), .S(n3322) );
BUFX4TS U2550 ( .A(n4478), .Y(n2213) );
ADDFX1TS U2551 ( .A(n3179), .B(n3178), .CI(n3177), .CO(n3223), .S(n3181) );
ADDFX1TS U2552 ( .A(n2980), .B(n2979), .CI(n2978), .CO(n3166), .S(n2981) );
ADDFX1TS U2553 ( .A(n2957), .B(n2956), .CI(n2955), .CO(n3148), .S(n2984) );
ADDFX1TS U2554 ( .A(n2977), .B(n2976), .CI(n2975), .CO(n2982), .S(n2963) );
ADDFX1TS U2555 ( .A(n2989), .B(n2988), .CI(n2987), .CO(n2985), .S(n2999) );
ADDFX1TS U2556 ( .A(n3347), .B(n3346), .CI(n3345), .CO(n3350), .S(n3343) );
ADDFX1TS U2557 ( .A(n2968), .B(n2967), .CI(n2966), .CO(n2964), .S(n3018) );
ADDFX1TS U2558 ( .A(n3002), .B(n3001), .CI(n3000), .CO(n2998), .S(n3028) );
NOR2X1TS U2559 ( .A(n3238), .B(DP_OP_453J210_122_681_n667), .Y(n3271) );
ADDFX1TS U2560 ( .A(n3298), .B(n3297), .CI(n3296), .CO(n3308), .S(n3289) );
ADDFX1TS U2561 ( .A(n3279), .B(n3278), .CI(n3277), .CO(n3288), .S(n3267) );
NOR2X1TS U2562 ( .A(n3238), .B(n2199), .Y(n3220) );
OR2X6TS U2563 ( .A(n4618), .B(FPMULT_FSM_selector_C), .Y(n3806) );
ADDFX1TS U2564 ( .A(n3163), .B(n3162), .CI(n3161), .CO(n3188), .S(n3159) );
ADDFX1TS U2565 ( .A(n3192), .B(n3191), .CI(n3190), .CO(n3215), .S(n3187) );
ADDFX1TS U2566 ( .A(n2974), .B(n2973), .CI(n2972), .CO(n3160), .S(n2970) );
ADDFX1TS U2567 ( .A(n3196), .B(n3195), .CI(n3194), .CO(n3217), .S(n3174) );
ADDFX1TS U2568 ( .A(n3005), .B(n3004), .CI(n3003), .CO(n2997), .S(n3027) );
ADDFX1TS U2569 ( .A(n2962), .B(n2961), .CI(n2960), .CO(n2971), .S(n3016) );
ADDFX1TS U2570 ( .A(n3244), .B(n3243), .CI(n3242), .CO(n3268), .S(n3239) );
ADDFX1TS U2571 ( .A(n3211), .B(n3210), .CI(n3209), .CO(n3240), .S(n3216) );
NAND2X4TS U2572 ( .A(n2198), .B(n5142), .Y(n4848) );
INVX3TS U2573 ( .A(n4910), .Y(n4843) );
ADDFX1TS U2574 ( .A(n3313), .B(n3312), .CI(n3311), .CO(n3330), .S(n3318) );
BUFX4TS U2575 ( .A(n3744), .Y(n2214) );
CLKINVX6TS U2576 ( .A(n4184), .Y(n4094) );
NAND2BX2TS U2577 ( .AN(n3753), .B(n3556), .Y(n4671) );
ADDFX1TS U2578 ( .A(n3326), .B(n3325), .CI(n3324), .CO(n3337), .S(n3329) );
ADDFX1TS U2579 ( .A(n3342), .B(n3341), .CI(n3340), .CO(n3345), .S(n3336) );
NOR2X1TS U2580 ( .A(n3314), .B(n3270), .Y(n3209) );
NOR2X1TS U2581 ( .A(n3327), .B(n3270), .Y(n3235) );
NOR2X1TS U2582 ( .A(n3189), .B(DP_OP_453J210_122_681_n667), .Y(n3211) );
NOR2X1TS U2583 ( .A(n3348), .B(n3245), .Y(n3277) );
NOR2X1TS U2584 ( .A(n3314), .B(n3315), .Y(n3279) );
BUFX6TS U2585 ( .A(n5451), .Y(n2215) );
OA21X1TS U2586 ( .A0(n3755), .A1(n3754), .B0(FPMULT_FS_Module_state_reg[1]),
.Y(n3756) );
NOR2X1TS U2587 ( .A(n3348), .B(n3213), .Y(n3242) );
NOR2X1TS U2588 ( .A(n3212), .B(DP_OP_453J210_122_681_n667), .Y(n3244) );
NOR2X1TS U2589 ( .A(n3314), .B(n3295), .Y(n3248) );
NOR2X1TS U2590 ( .A(n3269), .B(n3315), .Y(n3219) );
NOR2X1TS U2591 ( .A(n3291), .B(n3295), .Y(n3222) );
NOR2X1TS U2592 ( .A(n3339), .B(n3270), .Y(n3274) );
OR2X4TS U2593 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n4954), .Y(n4083) );
NOR2X1TS U2594 ( .A(n3291), .B(n2200), .Y(n3298) );
NAND2X4TS U2595 ( .A(n5176), .B(n2198), .Y(n4876) );
NOR2X1TS U2596 ( .A(n3348), .B(n3295), .Y(n3310) );
BUFX6TS U2597 ( .A(n4645), .Y(n4664) );
NOR2X1TS U2598 ( .A(n3314), .B(n2200), .Y(n3311) );
NOR2XLTS U2599 ( .A(n3348), .B(n2200), .Y(n3347) );
NOR2XLTS U2600 ( .A(n3339), .B(DP_OP_453J210_122_681_n667), .Y(n3346) );
NOR2X1TS U2601 ( .A(n3291), .B(DP_OP_453J210_122_681_n667), .Y(n3313) );
NOR2X1TS U2602 ( .A(n3339), .B(n2199), .Y(n3331) );
NOR2X1TS U2603 ( .A(n3327), .B(DP_OP_453J210_122_681_n667), .Y(n3342) );
NOR2X1TS U2604 ( .A(n3327), .B(n2200), .Y(n3326) );
NOR2X1TS U2605 ( .A(n3291), .B(n2199), .Y(n3273) );
NOR2X1TS U2606 ( .A(n3269), .B(DP_OP_453J210_122_681_n667), .Y(n3294) );
NOR2X1TS U2607 ( .A(n3314), .B(n2199), .Y(n3296) );
INVX3TS U2608 ( .A(FPMULT_Op_MX[2]), .Y(n3164) );
XOR2X1TS U2609 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[4]), .Y(n2827) );
INVX3TS U2610 ( .A(FPMULT_Op_MY[8]), .Y(n3314) );
BUFX6TS U2611 ( .A(FPMULT_Op_MY[17]), .Y(n2244) );
BUFX6TS U2612 ( .A(FPMULT_Op_MY[15]), .Y(n2243) );
INVX3TS U2613 ( .A(FPMULT_Op_MY[7]), .Y(n3291) );
INVX3TS U2614 ( .A(FPMULT_Op_MY[1]), .Y(n3076) );
OR3X6TS U2615 ( .A(FPSENCOS_cont_var_out[1]), .B(n5363), .C(n5244), .Y(n4474) );
BUFX6TS U2616 ( .A(FPMULT_Op_MY[19]), .Y(n2245) );
INVX3TS U2617 ( .A(FPMULT_Op_MY[0]), .Y(n3564) );
OAI21X1TS U2618 ( .A0(FPMULT_Op_MX[20]), .A1(FPMULT_Op_MX[8]), .B0(
FPMULT_Op_MX[7]), .Y(n2663) );
INVX4TS U2619 ( .A(FPMULT_Op_MY[11]), .Y(n3348) );
CLKINVX6TS U2620 ( .A(n5128), .Y(n2216) );
INVX3TS U2621 ( .A(FPMULT_Op_MX[6]), .Y(n3270) );
INVX3TS U2622 ( .A(FPMULT_Op_MX[5]), .Y(n3245) );
NOR2X1TS U2623 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[21]), .Y(n2661) );
INVX4TS U2624 ( .A(n4431), .Y(n4331) );
NOR2X6TS U2625 ( .A(n4332), .B(operation[2]), .Y(n4344) );
NOR2X6TS U2626 ( .A(operation[1]), .B(n4421), .Y(n4359) );
BUFX6TS U2627 ( .A(n3737), .Y(n2217) );
ADDHXLTS U2628 ( .A(n3151), .B(n3150), .CO(n3177), .S(n3153) );
ADDHXLTS U2629 ( .A(n2959), .B(n2958), .CO(n3154), .S(n2956) );
ADDHXLTS U2630 ( .A(n2954), .B(n2953), .CO(n2955), .S(n2988) );
NOR2XLTS U2631 ( .A(n2200), .B(n3564), .Y(n2954) );
XNOR2X1TS U2632 ( .A(n2242), .B(FPMULT_Op_MX[17]), .Y(n2517) );
XNOR2X1TS U2633 ( .A(n2245), .B(FPMULT_Op_MX[19]), .Y(n2516) );
XNOR2X1TS U2634 ( .A(n2242), .B(FPMULT_Op_MX[16]), .Y(n2346) );
XNOR2X1TS U2635 ( .A(n2245), .B(FPMULT_Op_MX[18]), .Y(n2345) );
NOR2X1TS U2636 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n2741) );
XNOR2X1TS U2637 ( .A(n2244), .B(FPMULT_Op_MX[19]), .Y(n2341) );
XNOR2X1TS U2638 ( .A(n2245), .B(FPMULT_Op_MX[17]), .Y(n2338) );
XNOR2X1TS U2639 ( .A(n2242), .B(FPMULT_Op_MX[15]), .Y(n2339) );
XNOR2X1TS U2640 ( .A(n2245), .B(FPMULT_Op_MX[16]), .Y(n2357) );
XNOR2X1TS U2641 ( .A(n2242), .B(FPMULT_Op_MX[14]), .Y(n2358) );
XNOR2X1TS U2642 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[21]), .Y(n2373) );
XNOR2X1TS U2643 ( .A(n2943), .B(n2266), .Y(n2868) );
XNOR2X1TS U2644 ( .A(n2949), .B(n2867), .Y(n2792) );
ADDHXLTS U2645 ( .A(n3007), .B(n3006), .CO(n3024), .S(n3040) );
NOR2XLTS U2646 ( .A(n3189), .B(n3213), .Y(n3006) );
NOR2XLTS U2647 ( .A(n3295), .B(n3564), .Y(n3007) );
ADDHXLTS U2648 ( .A(n2993), .B(n2992), .CO(n3001), .S(n3025) );
NOR2XLTS U2649 ( .A(n3291), .B(n3077), .Y(n2992) );
NOR2XLTS U2650 ( .A(n3315), .B(n3564), .Y(n2993) );
ADDHXLTS U2651 ( .A(n2991), .B(n2990), .CO(n2987), .S(n3002) );
NOR2XLTS U2652 ( .A(n2199), .B(n3564), .Y(n2991) );
OAI21X1TS U2653 ( .A0(n2779), .A1(n2788), .B0(n2780), .Y(n2743) );
NOR2XLTS U2654 ( .A(n3348), .B(n3077), .Y(n3161) );
NOR2XLTS U2655 ( .A(n3076), .B(DP_OP_453J210_122_681_n667), .Y(n3163) );
NOR2X1TS U2656 ( .A(n3314), .B(n3213), .Y(n3162) );
NOR2XLTS U2657 ( .A(n3291), .B(n3245), .Y(n3145) );
NOR2XLTS U2658 ( .A(n3327), .B(n3193), .Y(n3143) );
NOR2XLTS U2659 ( .A(n3269), .B(n3270), .Y(n3152) );
NOR2X1TS U2660 ( .A(n3238), .B(n3315), .Y(n3178) );
NOR2X1TS U2661 ( .A(n3327), .B(n3213), .Y(n3195) );
NOR2X1TS U2662 ( .A(n3269), .B(n3295), .Y(n3191) );
NOR2X1TS U2663 ( .A(n3212), .B(n2200), .Y(n3210) );
NOR2X1TS U2664 ( .A(n3238), .B(n2200), .Y(n3236) );
NOR2X1TS U2665 ( .A(n3327), .B(n3295), .Y(n3272) );
OAI21XLTS U2666 ( .A0(n2697), .A1(n2723), .B0(n2724), .Y(n2698) );
NOR2XLTS U2667 ( .A(n2696), .B(n2723), .Y(n2699) );
INVX2TS U2668 ( .A(n2722), .Y(n2696) );
NOR2X2TS U2669 ( .A(n2244), .B(n2254), .Y(n2771) );
NAND2X1TS U2670 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n2724) );
INVX2TS U2671 ( .A(n2695), .Y(n2770) );
INVX2TS U2672 ( .A(n2705), .Y(n2731) );
INVX2TS U2673 ( .A(n2729), .Y(n2730) );
XNOR2X1TS U2674 ( .A(n2951), .B(n2867), .Y(n2795) );
XNOR2X1TS U2675 ( .A(n2244), .B(FPMULT_Op_MX[22]), .Y(n2534) );
XNOR2X1TS U2676 ( .A(n2245), .B(FPMULT_Op_MX[20]), .Y(n2533) );
XNOR2X1TS U2677 ( .A(n2245), .B(FPMULT_Op_MX[21]), .Y(n2547) );
NOR2XLTS U2678 ( .A(n3269), .B(n3245), .Y(n2972) );
NOR2XLTS U2679 ( .A(n3076), .B(n2200), .Y(n2974) );
NOR2XLTS U2680 ( .A(n3327), .B(n3164), .Y(n2957) );
NOR2XLTS U2681 ( .A(n3146), .B(n2199), .Y(n2978) );
NOR2XLTS U2682 ( .A(n3291), .B(n3213), .Y(n2980) );
NOR2X1TS U2683 ( .A(n3238), .B(n3270), .Y(n2979) );
NOR2XLTS U2684 ( .A(n3146), .B(n3315), .Y(n2975) );
NOR2XLTS U2685 ( .A(n3291), .B(n3193), .Y(n2977) );
NOR2XLTS U2686 ( .A(n3327), .B(n3077), .Y(n2989) );
XNOR2X1TS U2687 ( .A(n2242), .B(FPMULT_Op_MX[18]), .Y(n2536) );
OAI22X1TS U2688 ( .A0(n2624), .A1(n2517), .B0(n2273), .B1(n2536), .Y(n2531)
);
OAI22X1TS U2689 ( .A0(n2604), .A1(n2516), .B0(n2274), .B1(n2533), .Y(n2532)
);
OAI22X1TS U2690 ( .A0(n2604), .A1(n2345), .B0(n2275), .B1(n2516), .Y(n2515)
);
OAI22X1TS U2691 ( .A0(n2624), .A1(n2346), .B0(n2273), .B1(n2517), .Y(n2514)
);
XNOR2X1TS U2692 ( .A(n2244), .B(FPMULT_Op_MX[20]), .Y(n2340) );
XNOR2X1TS U2693 ( .A(n2244), .B(FPMULT_Op_MX[21]), .Y(n2518) );
OAI22X1TS U2694 ( .A0(n2645), .A1(FPMULT_Op_MX[14]), .B0(n2247), .B1(
FPMULT_Op_MX[15]), .Y(n2520) );
OAI22X1TS U2695 ( .A0(n2577), .A1(n2341), .B0(n2277), .B1(n2340), .Y(n2342)
);
OAI22X1TS U2696 ( .A0(n2604), .A1(n2338), .B0(n2274), .B1(n2345), .Y(n2344)
);
OAI22X1TS U2697 ( .A0(n2624), .A1(n2339), .B0(n2272), .B1(n2346), .Y(n2343)
);
OAI22X1TS U2698 ( .A0(n2645), .A1(FPMULT_Op_MX[13]), .B0(n2247), .B1(
FPMULT_Op_MX[14]), .Y(n2352) );
NAND2X1TS U2699 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n2729) );
AOI21X2TS U2700 ( .A0(n2743), .A1(n2653), .B0(n2652), .Y(n2695) );
NOR2X1TS U2701 ( .A(n2761), .B(n2744), .Y(n2653) );
OAI21X1TS U2702 ( .A0(n2744), .A1(n2762), .B0(n2745), .Y(n2652) );
OAI21X2TS U2703 ( .A0(n2771), .A1(n2767), .B0(n2772), .Y(n2721) );
NOR2X2TS U2704 ( .A(n2771), .B(n2741), .Y(n2722) );
NOR2X1TS U2705 ( .A(n2733), .B(n2705), .Y(n2670) );
XNOR2X1TS U2706 ( .A(n2243), .B(FPMULT_Op_MX[21]), .Y(n2348) );
XNOR2X1TS U2707 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[22]), .Y(n2356) );
ADDHXLTS U2708 ( .A(n2350), .B(n2349), .CO(n2354), .S(n2370) );
OAI22X1TS U2709 ( .A0(n2577), .A1(n2363), .B0(n2276), .B1(n2341), .Y(n2349)
);
OAI21XLTS U2710 ( .A0(n2278), .A1(n2247), .B0(n2645), .Y(n2350) );
OAI22X1TS U2711 ( .A0(n2624), .A1(n2358), .B0(n2272), .B1(n2339), .Y(n2359)
);
OAI22X1TS U2712 ( .A0(n2604), .A1(n2357), .B0(n2275), .B1(n2338), .Y(n2360)
);
XNOR2X1TS U2713 ( .A(n2243), .B(FPMULT_Op_MX[20]), .Y(n2362) );
XNOR2X1TS U2714 ( .A(n2244), .B(FPMULT_Op_MX[17]), .Y(n2374) );
OAI22X1TS U2715 ( .A0(n2444), .A1(n2373), .B0(n2356), .B1(n3566), .Y(n2377)
);
OAI22X1TS U2716 ( .A0(n2624), .A1(n2390), .B0(n2272), .B1(n2358), .Y(n2375)
);
OAI22X1TS U2717 ( .A0(n2604), .A1(n2379), .B0(n2274), .B1(n2357), .Y(n2376)
);
ADDHXLTS U2718 ( .A(n2393), .B(n2392), .CO(n2399), .S(n2410) );
OAI22X1TS U2719 ( .A0(n2444), .A1(n2394), .B0(n2373), .B1(n3566), .Y(n2393)
);
OAI22X1TS U2720 ( .A0(n2577), .A1(n2396), .B0(n2277), .B1(n2374), .Y(n2392)
);
XNOR2X1TS U2721 ( .A(n2243), .B(FPMULT_Op_MX[19]), .Y(n2378) );
INVX2TS U2722 ( .A(n3595), .Y(n2934) );
XNOR2X1TS U2723 ( .A(n2243), .B(FPMULT_Op_MX[18]), .Y(n2406) );
XNOR2X1TS U2724 ( .A(n2245), .B(FPMULT_Op_MX[14]), .Y(n2395) );
XNOR2X1TS U2725 ( .A(n2244), .B(FPMULT_Op_MX[15]), .Y(n2408) );
XNOR2X1TS U2726 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[19]), .Y(n2407) );
XNOR2X1TS U2727 ( .A(n2243), .B(FPMULT_Op_MX[17]), .Y(n2448) );
XNOR2X1TS U2728 ( .A(n2245), .B(FPMULT_Op_MX[13]), .Y(n2451) );
XNOR2X1TS U2729 ( .A(n2934), .B(n2269), .Y(n2889) );
XNOR2X1TS U2730 ( .A(n2941), .B(n2266), .Y(n2866) );
INVX2TS U2731 ( .A(n2943), .Y(n2728) );
NOR2XLTS U2732 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .Y(n2708) );
NAND2X1TS U2733 ( .A(n2694), .B(n2693), .Y(n2710) );
OAI21XLTS U2734 ( .A0(FPMULT_Op_MX[18]), .A1(FPMULT_Op_MX[6]), .B0(
FPMULT_Op_MX[5]), .Y(n2694) );
XOR2X1TS U2735 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[8]), .Y(n2714) );
XNOR2X1TS U2736 ( .A(n2244), .B(FPMULT_Op_MX[14]), .Y(n2446) );
XNOR2X1TS U2737 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[18]), .Y(n2442) );
XNOR2X1TS U2738 ( .A(n2243), .B(FPMULT_Op_MX[16]), .Y(n2449) );
INVX2TS U2739 ( .A(n2945), .Y(n2857) );
XNOR2X1TS U2740 ( .A(n2939), .B(n2270), .Y(n2878) );
XNOR2X1TS U2741 ( .A(n2243), .B(FPMULT_Op_MX[15]), .Y(n2445) );
XNOR2X1TS U2742 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[17]), .Y(n2443) );
XNOR2X1TS U2743 ( .A(n2941), .B(n2270), .Y(n2877) );
XNOR2X1TS U2744 ( .A(n2935), .B(n2269), .Y(n2890) );
INVX2TS U2745 ( .A(n2928), .Y(n2858) );
INVX2TS U2746 ( .A(n2925), .Y(n2860) );
XNOR2X1TS U2747 ( .A(n2945), .B(n2266), .Y(n2869) );
XNOR2X1TS U2748 ( .A(n2934), .B(n2268), .Y(n2903) );
XNOR2X1TS U2749 ( .A(n2937), .B(n2269), .Y(n2891) );
XNOR2X1TS U2750 ( .A(n2911), .B(n2867), .Y(n2790) );
XNOR2X1TS U2751 ( .A(n2941), .B(n2269), .Y(n2892) );
XNOR2X1TS U2752 ( .A(n2945), .B(n2270), .Y(n2880) );
XNOR2X1TS U2753 ( .A(n2943), .B(n2270), .Y(n2879) );
XNOR2X1TS U2754 ( .A(n2935), .B(n2268), .Y(n2904) );
XNOR2X1TS U2755 ( .A(n2939), .B(n2269), .Y(n2893) );
XNOR2X1TS U2756 ( .A(n2928), .B(n2867), .Y(n2784) );
XNOR2X1TS U2757 ( .A(n2934), .B(n2267), .Y(n2919) );
XNOR2X1TS U2758 ( .A(n2925), .B(n2266), .Y(n2871) );
XNOR2X1TS U2759 ( .A(n2928), .B(n2883), .Y(n2882) );
XNOR2X1TS U2760 ( .A(n2925), .B(n2270), .Y(n2881) );
XNOR2X1TS U2761 ( .A(n2943), .B(n2269), .Y(n2894) );
OAI22X1TS U2762 ( .A0(n2790), .A1(n2261), .B0(n2792), .B1(n2870), .Y(n2797)
);
OAI22X1TS U2763 ( .A0(n2792), .A1(n2261), .B0(n2795), .B1(n2870), .Y(n2800)
);
XNOR2X1TS U2764 ( .A(n2945), .B(n2269), .Y(n2895) );
XNOR2X1TS U2765 ( .A(n2934), .B(n2246), .Y(n2936) );
ADDHXLTS U2766 ( .A(n3039), .B(n3038), .CO(n3054), .S(n3081) );
NOR2XLTS U2767 ( .A(n3189), .B(n3193), .Y(n3038) );
NOR2XLTS U2768 ( .A(n3270), .B(n3564), .Y(n3039) );
NOR2X1TS U2769 ( .A(n3146), .B(n3245), .Y(n3041) );
NOR2XLTS U2770 ( .A(n3238), .B(n3164), .Y(n3042) );
NOR2XLTS U2771 ( .A(n3146), .B(n3295), .Y(n2966) );
NOR2XLTS U2772 ( .A(n3291), .B(n3164), .Y(n2968) );
NOR2X1TS U2773 ( .A(n3238), .B(n3213), .Y(n2967) );
NOR2XLTS U2774 ( .A(n3146), .B(n3270), .Y(n3020) );
NOR2XLTS U2775 ( .A(n3189), .B(n3245), .Y(n3022) );
NOR2XLTS U2776 ( .A(n3269), .B(n3164), .Y(n3023) );
NOR2XLTS U2777 ( .A(n3269), .B(n3193), .Y(n3000) );
NOR2XLTS U2778 ( .A(n3212), .B(n3245), .Y(n3003) );
NOR2X1TS U2779 ( .A(n3314), .B(n3077), .Y(n3004) );
NOR2XLTS U2780 ( .A(n3076), .B(n3315), .Y(n3005) );
NOR2XLTS U2781 ( .A(n3212), .B(n3315), .Y(n3167) );
NOR2XLTS U2782 ( .A(n3339), .B(n3164), .Y(n3149) );
CLKAND2X2TS U2783 ( .A(n2253), .B(n2278), .Y(n2297) );
NOR2X2TS U2784 ( .A(n2243), .B(FPMULT_Op_MY[3]), .Y(n2744) );
NOR2XLTS U2785 ( .A(n3314), .B(n3245), .Y(n3176) );
NOR2XLTS U2786 ( .A(n3339), .B(n3193), .Y(n3182) );
NAND2X1TS U2787 ( .A(n2757), .B(n2756), .Y(n2823) );
OAI21XLTS U2788 ( .A0(FPMULT_Op_MX[14]), .A1(FPMULT_Op_MX[2]), .B0(
FPMULT_Op_MX[1]), .Y(n2757) );
NOR2X1TS U2789 ( .A(n3339), .B(n3213), .Y(n3224) );
NOR2X1TS U2790 ( .A(n3269), .B(n2199), .Y(n3243) );
NOR2X1TS U2791 ( .A(n3269), .B(n2200), .Y(n3278) );
NAND2X1TS U2792 ( .A(n2686), .B(n2685), .Y(n2831) );
OAI21XLTS U2793 ( .A0(FPMULT_Op_MX[16]), .A1(FPMULT_Op_MX[4]), .B0(
FPMULT_Op_MX[3]), .Y(n2686) );
XOR2X1TS U2794 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[6]), .Y(n2690) );
NOR2XLTS U2795 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MX[17]), .Y(n2684) );
NOR2X1TS U2796 ( .A(n3327), .B(n3315), .Y(n3297) );
NOR2X1TS U2797 ( .A(n3348), .B(n3270), .Y(n3293) );
NOR2X1TS U2798 ( .A(n3327), .B(n2199), .Y(n3312) );
INVX4TS U2799 ( .A(n2896), .Y(n2269) );
XNOR2X1TS U2800 ( .A(n2951), .B(n2269), .Y(n2810) );
NAND2X1TS U2801 ( .A(n2702), .B(n2701), .Y(n2703) );
AOI21X1TS U2802 ( .A0(n2770), .A1(n2699), .B0(n2698), .Y(n2704) );
NAND2X1TS U2803 ( .A(n2773), .B(n2772), .Y(n2774) );
AOI21X1TS U2804 ( .A0(n2770), .A1(n2769), .B0(n2768), .Y(n2775) );
INVX2TS U2805 ( .A(n2771), .Y(n2773) );
XNOR2X1TS U2806 ( .A(n2949), .B(n2269), .Y(n2806) );
XNOR2X1TS U2807 ( .A(n2911), .B(n2269), .Y(n2899) );
INVX4TS U2808 ( .A(n2913), .Y(n2268) );
AOI21X1TS U2809 ( .A0(n2770), .A1(n2722), .B0(n2721), .Y(n2727) );
XNOR2X2TS U2810 ( .A(n2827), .B(n2821), .Y(n2825) );
CLKXOR2X2TS U2811 ( .A(n2825), .B(n2824), .Y(n2917) );
AOI21X1TS U2812 ( .A0(n2732), .A1(n2670), .B0(n2676), .Y(n2673) );
XNOR2X1TS U2813 ( .A(n2951), .B(n2883), .Y(n2886) );
ADDHXLTS U2814 ( .A(n2815), .B(n2814), .CO(DP_OP_453J210_122_681_n358), .S(
n2813) );
OAI22X1TS U2815 ( .A0(n2885), .A1(n2873), .B0(n2263), .B1(n2804), .Y(n2815)
);
NAND2BXLTS U2816 ( .AN(n3568), .B(n2883), .Y(n2804) );
NAND2X1TS U2817 ( .A(n2735), .B(n2734), .Y(n2736) );
AOI21X1TS U2818 ( .A0(n2732), .A1(n2731), .B0(n2730), .Y(n2737) );
XNOR2X1TS U2819 ( .A(n2949), .B(n2883), .Y(n2888) );
XNOR2X1TS U2820 ( .A(n2928), .B(n2269), .Y(n2900) );
XNOR2X1TS U2821 ( .A(n2911), .B(n2883), .Y(n2884) );
XNOR2X1TS U2822 ( .A(n2943), .B(n2268), .Y(n2908) );
XNOR2X1TS U2823 ( .A(n2925), .B(n2269), .Y(n2897) );
ADDHXLTS U2824 ( .A(n2803), .B(n2802), .CO(n2799), .S(
DP_OP_453J210_122_681_n340) );
OAI22X1TS U2825 ( .A0(n2870), .A1(n2861), .B0(n2261), .B1(n2793), .Y(n2803)
);
NAND2BXLTS U2826 ( .AN(n3568), .B(n2867), .Y(n2793) );
XOR2X1TS U2827 ( .A(n2691), .B(n2709), .Y(n2692) );
NOR2XLTS U2828 ( .A(n2690), .B(n2689), .Y(n2691) );
XOR2X1TS U2829 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n2752) );
XNOR2X1TS U2830 ( .A(n2242), .B(FPMULT_Op_MX[19]), .Y(n2551) );
OAI22X1TS U2831 ( .A0(n2604), .A1(n2533), .B0(n2275), .B1(n2547), .Y(n2550)
);
OAI22X1TS U2832 ( .A0(n2577), .A1(n2534), .B0(n2277), .B1(n2244), .Y(n2549)
);
XNOR2X1TS U2833 ( .A(n2242), .B(FPMULT_Op_MX[20]), .Y(n2575) );
XNOR2X1TS U2834 ( .A(n2245), .B(FPMULT_Op_MX[22]), .Y(n2574) );
OAI22X1TS U2835 ( .A0(n2604), .A1(n2547), .B0(n2275), .B1(n2574), .Y(n2572)
);
OAI22X1TS U2836 ( .A0(n2645), .A1(FPMULT_Op_MX[17]), .B0(n2247), .B1(
FPMULT_Op_MX[18]), .Y(n2573) );
NAND2X4TS U2837 ( .A(n2336), .B(n2603), .Y(n2604) );
XOR2X1TS U2838 ( .A(FPMULT_Op_MY[18]), .B(n2245), .Y(n2336) );
NOR2XLTS U2839 ( .A(n3339), .B(n3077), .Y(n2986) );
NOR2XLTS U2840 ( .A(n3212), .B(n3295), .Y(n2983) );
NOR2XLTS U2841 ( .A(n3212), .B(n3270), .Y(n2965) );
NOR2XLTS U2842 ( .A(n3269), .B(n3213), .Y(n2960) );
NOR2XLTS U2843 ( .A(n3076), .B(n2199), .Y(n2962) );
NOR2X1TS U2844 ( .A(n3146), .B(n3213), .Y(n3082) );
NOR2XLTS U2845 ( .A(n3238), .B(n3077), .Y(n3083) );
XNOR2X2TS U2846 ( .A(FPMULT_Op_MY[20]), .B(n2245), .Y(n2623) );
OAI22X1TS U2847 ( .A0(n2624), .A1(n2536), .B0(n2273), .B1(n2551), .Y(n2546)
);
OAI22X1TS U2848 ( .A0(n2577), .A1(n2340), .B0(n2277), .B1(n2518), .Y(n2509)
);
OAI21X2TS U2849 ( .A0(n2733), .A1(n2729), .B0(n2734), .Y(n2676) );
NAND2X1TS U2850 ( .A(n2722), .B(n2655), .Y(n2657) );
AOI21X1TS U2851 ( .A0(n2721), .A1(n2655), .B0(n2654), .Y(n2656) );
NOR2X1TS U2852 ( .A(n2723), .B(n2700), .Y(n2655) );
CLKAND2X2TS U2853 ( .A(n2670), .B(n2671), .Y(n2284) );
AOI21X1TS U2854 ( .A0(n2732), .A1(n2284), .B0(n2680), .Y(n2681) );
NAND2X1TS U2855 ( .A(n2663), .B(n2662), .Y(n2707) );
XOR2X1TS U2856 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .Y(n2666) );
OAI22X1TS U2857 ( .A0(n2444), .A1(n2356), .B0(FPMULT_Op_MY[13]), .B1(n3566),
.Y(n2372) );
OAI22X1TS U2858 ( .A0(n2430), .A1(n2362), .B0(n2271), .B1(n2348), .Y(n2371)
);
OAI22X1TS U2859 ( .A0(n2577), .A1(n2374), .B0(n2277), .B1(n2363), .Y(n2387)
);
OAI22X1TS U2860 ( .A0(n2430), .A1(n2378), .B0(n2271), .B1(n2362), .Y(n2388)
);
XNOR2X1TS U2861 ( .A(n2934), .B(n2266), .Y(n2862) );
INVX2TS U2862 ( .A(n2937), .Y(n2854) );
OAI22X1TS U2863 ( .A0(n2391), .A1(n2624), .B0(n2623), .B1(n2390), .Y(n2411)
);
OAI22X1TS U2864 ( .A0(n2380), .A1(n2272), .B0(n2624), .B1(n2303), .Y(n2403)
);
OAI22X1TS U2865 ( .A0(n2604), .A1(n2395), .B0(n2275), .B1(n2379), .Y(n2404)
);
OAI22X1TS U2866 ( .A0(n2430), .A1(n2406), .B0(n2271), .B1(n2378), .Y(n2405)
);
XNOR2X1TS U2867 ( .A(n2934), .B(n2270), .Y(n2874) );
INVX2TS U2868 ( .A(n2941), .Y(n2855) );
XNOR2X1TS U2869 ( .A(n2935), .B(n2266), .Y(n2863) );
INVX2TS U2870 ( .A(n2939), .Y(n2856) );
OAI22X1TS U2871 ( .A0(n2430), .A1(n2448), .B0(n2271), .B1(n2406), .Y(n2481)
);
OAI22X1TS U2872 ( .A0(n2444), .A1(n2407), .B0(n2394), .B1(n3566), .Y(n2476)
);
OAI22X1TS U2873 ( .A0(n2577), .A1(n2408), .B0(n2276), .B1(n2396), .Y(n2474)
);
OAI22X1TS U2874 ( .A0(n2604), .A1(n2451), .B0(n2274), .B1(n2395), .Y(n2475)
);
XNOR2X1TS U2875 ( .A(n2939), .B(n2266), .Y(n2865) );
XNOR2X1TS U2876 ( .A(n2937), .B(n2266), .Y(n2864) );
AO21XLTS U2877 ( .A0(n2898), .A1(n2262), .B0(n2808), .Y(n2720) );
OAI22X1TS U2878 ( .A0(n2728), .A1(n2675), .B0(n2855), .B1(n2859), .Y(n2719)
);
ADDHXLTS U2879 ( .A(n2441), .B(n2440), .CO(n2480), .S(n2488) );
OAI22X1TS U2880 ( .A0(n2444), .A1(n2442), .B0(n2407), .B1(n3566), .Y(n2441)
);
OAI22X1TS U2881 ( .A0(n2452), .A1(n2604), .B0(n2603), .B1(n2451), .Y(n2477)
);
OAI22X1TS U2882 ( .A0(n2450), .A1(n2603), .B0(n2604), .B1(n2304), .Y(n2478)
);
OAI22X1TS U2883 ( .A0(n2430), .A1(n2449), .B0(n2271), .B1(n2448), .Y(n2479)
);
XNOR2X1TS U2884 ( .A(n2937), .B(n2270), .Y(n2876) );
OAI22X1TS U2885 ( .A0(n2857), .A1(n2675), .B0(n2728), .B1(n2859), .Y(n2740)
);
OAI22X1TS U2886 ( .A0(n2889), .A1(n2898), .B0(n2262), .B1(n2808), .Y(n2739)
);
XNOR2X1TS U2887 ( .A(n2935), .B(n2270), .Y(n2875) );
NAND2X1TS U2888 ( .A(n2710), .B(n2709), .Y(n2711) );
XNOR2X1TS U2889 ( .A(n2714), .B(n2708), .Y(n2712) );
XOR2X1TS U2890 ( .A(n2716), .B(n2715), .Y(n2717) );
NOR2XLTS U2891 ( .A(n2714), .B(n2713), .Y(n2716) );
OAI22X1TS U2892 ( .A0(n2444), .A1(n2443), .B0(n2442), .B1(n3566), .Y(n2457)
);
OAI22X1TS U2893 ( .A0(n2430), .A1(n2445), .B0(n2271), .B1(n2449), .Y(n2456)
);
CMPR42X1TS U2894 ( .A(DP_OP_453J210_122_681_n493), .B(
DP_OP_453J210_122_681_n441), .C(DP_OP_453J210_122_681_n454), .D(
DP_OP_453J210_122_681_n480), .ICI(DP_OP_453J210_122_681_n467), .S(
DP_OP_453J210_122_681_n265), .ICO(DP_OP_453J210_122_681_n263), .CO(
DP_OP_453J210_122_681_n264) );
AO21XLTS U2895 ( .A0(n2915), .A1(n2264), .B0(n2902), .Y(
DP_OP_453J210_122_681_n493) );
ADDHXLTS U2896 ( .A(n2454), .B(n2453), .CO(n2459), .S(n2461) );
OAI22X1TS U2897 ( .A0(n2444), .A1(n2414), .B0(n2443), .B1(n3566), .Y(n2454)
);
XNOR2X1TS U2898 ( .A(n2244), .B(FPMULT_Op_MX[13]), .Y(n2447) );
NAND2X4TS U2899 ( .A(n2334), .B(n2576), .Y(n2577) );
XOR2X1TS U2900 ( .A(n2244), .B(FPMULT_Op_MY[16]), .Y(n2334) );
AO21XLTS U2901 ( .A0(n2932), .A1(n2265), .B0(n2848), .Y(n2759) );
OAI22X1TS U2902 ( .A0(n2858), .A1(n2859), .B0(n2766), .B1(n2675), .Y(n2760)
);
CMPR42X1TS U2903 ( .A(DP_OP_453J210_122_681_n442), .B(
DP_OP_453J210_122_681_n494), .C(DP_OP_453J210_122_681_n455), .D(
DP_OP_453J210_122_681_n468), .ICI(DP_OP_453J210_122_681_n481), .S(
DP_OP_453J210_122_681_n274), .ICO(DP_OP_453J210_122_681_n272), .CO(
DP_OP_453J210_122_681_n273) );
OAI22X1TS U2904 ( .A0(n2860), .A1(n2859), .B0(n2858), .B1(n2675), .Y(
DP_OP_453J210_122_681_n442) );
XNOR2X1TS U2905 ( .A(n2243), .B(FPMULT_Op_MX[14]), .Y(n2415) );
CMPR42X1TS U2906 ( .A(DP_OP_453J210_122_681_n456), .B(
DP_OP_453J210_122_681_n495), .C(DP_OP_453J210_122_681_n482), .D(
DP_OP_453J210_122_681_n285), .ICI(DP_OP_453J210_122_681_n292), .S(
DP_OP_453J210_122_681_n283), .ICO(DP_OP_453J210_122_681_n281), .CO(
DP_OP_453J210_122_681_n282) );
XNOR2X1TS U2907 ( .A(n2243), .B(FPMULT_Op_MX[13]), .Y(n2429) );
XNOR2X1TS U2908 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[14]), .Y(n2422) );
XNOR2X1TS U2909 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[15]), .Y(n2419) );
NAND2X4TS U2910 ( .A(n2335), .B(n2271), .Y(n2430) );
XOR2X1TS U2911 ( .A(FPMULT_Op_MY[14]), .B(n2243), .Y(n2335) );
OAI22X1TS U2912 ( .A0(n2784), .A1(n2261), .B0(n2790), .B1(n2870), .Y(n2786)
);
XNOR2X1TS U2913 ( .A(n2937), .B(n2268), .Y(n2905) );
CMPR42X1TS U2914 ( .A(DP_OP_453J210_122_681_n471), .B(n2219), .C(
DP_OP_453J210_122_681_n317), .D(DP_OP_453J210_122_681_n510), .ICI(
DP_OP_453J210_122_681_n314), .S(DP_OP_453J210_122_681_n305), .ICO(
DP_OP_453J210_122_681_n303), .CO(DP_OP_453J210_122_681_n304) );
CMPR42X1TS U2915 ( .A(DP_OP_453J210_122_681_n470), .B(
DP_OP_453J210_122_681_n483), .C(DP_OP_453J210_122_681_n306), .D(
DP_OP_453J210_122_681_n496), .ICI(DP_OP_453J210_122_681_n303), .S(
DP_OP_453J210_122_681_n294), .ICO(DP_OP_453J210_122_681_n292), .CO(
DP_OP_453J210_122_681_n293) );
OAI22X1TS U2916 ( .A0(n2766), .A1(n2859), .B0(n2783), .B1(n2675), .Y(n2778)
);
OAI22X1TS U2917 ( .A0(n2919), .A1(n2932), .B0(n2265), .B1(n2848), .Y(n2777)
);
XNOR2X1TS U2918 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[13]), .Y(n2423) );
XNOR2X1TS U2919 ( .A(n2941), .B(n2268), .Y(n2907) );
XNOR2X1TS U2920 ( .A(n2935), .B(n2267), .Y(n2920) );
XNOR2X1TS U2921 ( .A(n2939), .B(n2268), .Y(n2906) );
CMPR42X1TS U2922 ( .A(DP_OP_453J210_122_681_n524), .B(
DP_OP_453J210_122_681_n472), .C(DP_OP_453J210_122_681_n485), .D(
DP_OP_453J210_122_681_n318), .ICI(DP_OP_453J210_122_681_n325), .S(
DP_OP_453J210_122_681_n316), .ICO(DP_OP_453J210_122_681_n314), .CO(
DP_OP_453J210_122_681_n315) );
OAI22X1TS U2923 ( .A0(n3562), .A1(n2936), .B0(n3567), .B1(n2219), .Y(
DP_OP_453J210_122_681_n524) );
XNOR2X1TS U2924 ( .A(n2937), .B(n2267), .Y(n2921) );
CMPR42X1TS U2925 ( .A(DP_OP_453J210_122_681_n473), .B(
DP_OP_453J210_122_681_n329), .C(DP_OP_453J210_122_681_n499), .D(
DP_OP_453J210_122_681_n486), .ICI(DP_OP_453J210_122_681_n525), .S(
DP_OP_453J210_122_681_n327), .ICO(DP_OP_453J210_122_681_n325), .CO(
DP_OP_453J210_122_681_n326) );
OAI22X1TS U2926 ( .A0(n2938), .A1(n3562), .B0(n2936), .B1(n3567), .Y(
DP_OP_453J210_122_681_n525) );
ADDHXLTS U2927 ( .A(n3087), .B(n3086), .CO(n3091), .S(n3079) );
NOR2XLTS U2928 ( .A(n3189), .B(n3077), .Y(n3086) );
NOR2XLTS U2929 ( .A(n3213), .B(n3564), .Y(n3087) );
ADDHXLTS U2930 ( .A(n3085), .B(n3084), .CO(n3090), .S(n3092) );
NOR2XLTS U2931 ( .A(n3189), .B(n3164), .Y(n3084) );
NOR2XLTS U2932 ( .A(n3245), .B(n3564), .Y(n3085) );
NOR2XLTS U2933 ( .A(n3269), .B(n3077), .Y(n3052) );
NOR2XLTS U2934 ( .A(n3212), .B(n3164), .Y(n3088) );
NOR2XLTS U2935 ( .A(n3076), .B(n3295), .Y(n3037) );
NOR2XLTS U2936 ( .A(n3076), .B(n3270), .Y(n3057) );
NAND2X1TS U2937 ( .A(n2746), .B(n2745), .Y(n2747) );
INVX2TS U2938 ( .A(n2744), .Y(n2746) );
XNOR2X1TS U2939 ( .A(n2951), .B(n2267), .Y(n2849) );
XNOR2X1TS U2940 ( .A(n2911), .B(n2267), .Y(n2931) );
XNOR2X1TS U2941 ( .A(n2949), .B(n2267), .Y(n2842) );
XNOR2X1TS U2942 ( .A(n2246), .B(n2928), .Y(n2843) );
XNOR2X1TS U2943 ( .A(n2951), .B(n2268), .Y(n2916) );
XNOR2X1TS U2944 ( .A(n2925), .B(n2246), .Y(n2948) );
ADDHXLTS U2945 ( .A(n2841), .B(n2840), .CO(DP_OP_453J210_122_681_n387), .S(
n2839) );
OAI22X1TS U2946 ( .A0(n2915), .A1(n2902), .B0(n2917), .B1(n2832), .Y(n2841)
);
NAND2BXLTS U2947 ( .AN(n3568), .B(n2268), .Y(n2832) );
XNOR2X1TS U2948 ( .A(n2690), .B(n2684), .Y(n2688) );
NAND2X1TS U2949 ( .A(n2831), .B(n2830), .Y(n2687) );
NOR2X1TS U2950 ( .A(n3314), .B(DP_OP_453J210_122_681_n667), .Y(n3325) );
XNOR2X1TS U2951 ( .A(n2928), .B(n2267), .Y(n2930) );
XNOR2X1TS U2952 ( .A(n2949), .B(n2268), .Y(n2918) );
XNOR2X1TS U2953 ( .A(n2945), .B(n2246), .Y(n2947) );
ADDHXLTS U2954 ( .A(n2820), .B(n2819), .CO(n2816), .S(
DP_OP_453J210_122_681_n375) );
OAI22X1TS U2955 ( .A0(n2898), .A1(n2808), .B0(n2262), .B1(n2807), .Y(n2820)
);
NAND2BXLTS U2956 ( .AN(n3568), .B(n2269), .Y(n2807) );
XNOR2X1TS U2957 ( .A(n2911), .B(n2268), .Y(n2914) );
XNOR2X1TS U2958 ( .A(n2925), .B(n2267), .Y(n2929) );
XNOR2X1TS U2959 ( .A(n2943), .B(n2246), .Y(n2946) );
OAI22X1TS U2960 ( .A0(n2806), .A1(n2262), .B0(n2810), .B1(n2898), .Y(n2817)
);
XNOR2X1TS U2961 ( .A(n2945), .B(n2267), .Y(n2926) );
XNOR2X1TS U2962 ( .A(n2928), .B(n2268), .Y(n2912) );
XNOR2X1TS U2963 ( .A(n2941), .B(n2246), .Y(n2944) );
XNOR2X1TS U2964 ( .A(n2943), .B(n2267), .Y(n2924) );
XNOR2X1TS U2965 ( .A(n2925), .B(n2268), .Y(n2910) );
XNOR2X1TS U2966 ( .A(n2939), .B(n2246), .Y(n2942) );
OAI22X1TS U2967 ( .A0(n2899), .A1(n2262), .B0(n2806), .B1(n2898), .Y(n2812)
);
XNOR2X1TS U2968 ( .A(n2945), .B(n2268), .Y(n2909) );
XOR2X1TS U2969 ( .A(n2828), .B(n2830), .Y(n2829) );
NOR2XLTS U2970 ( .A(n2827), .B(n2826), .Y(n2828) );
XNOR2X1TS U2971 ( .A(n2937), .B(n2246), .Y(n2940) );
XNOR2X1TS U2972 ( .A(n2941), .B(n2267), .Y(n2923) );
XNOR2X1TS U2973 ( .A(n2935), .B(n2246), .Y(n2938) );
CMPR42X1TS U2974 ( .A(DP_OP_453J210_122_681_n462), .B(
DP_OP_453J210_122_681_n475), .C(DP_OP_453J210_122_681_n358), .D(
DP_OP_453J210_122_681_n488), .ICI(DP_OP_453J210_122_681_n514), .S(
DP_OP_453J210_122_681_n349), .ICO(DP_OP_453J210_122_681_n347), .CO(
DP_OP_453J210_122_681_n348) );
XNOR2X1TS U2975 ( .A(n2939), .B(n2267), .Y(n2922) );
CMPR42X1TS U2976 ( .A(DP_OP_453J210_122_681_n340), .B(
DP_OP_453J210_122_681_n474), .C(DP_OP_453J210_122_681_n347), .D(
DP_OP_453J210_122_681_n487), .ICI(DP_OP_453J210_122_681_n500), .S(
DP_OP_453J210_122_681_n338), .ICO(DP_OP_453J210_122_681_n336), .CO(
DP_OP_453J210_122_681_n337) );
XOR2X1TS U2977 ( .A(n2754), .B(n2822), .Y(n2755) );
NOR2XLTS U2978 ( .A(n2753), .B(n2752), .Y(n2754) );
XOR2XLTS U2979 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[13]), .Y(n2753) );
OAI22X1TS U2980 ( .A0(n2624), .A1(n2551), .B0(n2273), .B1(n2575), .Y(n2570)
);
OAI22X1TS U2981 ( .A0(n2604), .A1(n2574), .B0(n2274), .B1(n2245), .Y(n2588)
);
AO21XLTS U2982 ( .A0(n2577), .A1(n2276), .B0(n2288), .Y(n2586) );
OAI22X1TS U2983 ( .A0(n2624), .A1(n2575), .B0(n2273), .B1(n2589), .Y(n2587)
);
OAI22X1TS U2984 ( .A0(n2645), .A1(FPMULT_Op_MX[19]), .B0(n2247), .B1(
FPMULT_Op_MX[20]), .Y(n2601) );
AO21XLTS U2985 ( .A0(n2604), .A1(n2274), .B0(n2304), .Y(n2615) );
NOR2XLTS U2986 ( .A(n3565), .B(n3348), .Y(n3009) );
NAND2X4TS U2987 ( .A(n2337), .B(n2623), .Y(n2624) );
XOR2X1TS U2988 ( .A(n2242), .B(FPMULT_Op_MY[20]), .Y(n2337) );
OAI22X1TS U2989 ( .A0(n2645), .A1(FPMULT_Op_MX[21]), .B0(n2247), .B1(
FPMULT_Op_MX[22]), .Y(n2626) );
OAI22X1TS U2990 ( .A0(n2444), .A1(n2423), .B0(n2422), .B1(n3566), .Y(n2424)
);
OAI21X1TS U2991 ( .A0(n2506), .A1(n3494), .B0(n2505), .Y(n2631) );
NAND2X1TS U2992 ( .A(n2504), .B(n3496), .Y(n2506) );
AOI21X1TS U2993 ( .A0(n2504), .A1(n3495), .B0(n2503), .Y(n2505) );
NOR2X1TS U2994 ( .A(n3497), .B(n3502), .Y(n2504) );
OAI21X1TS U2995 ( .A0(n3509), .A1(n3514), .B0(n3510), .Y(n3495) );
NOR2X1TS U2996 ( .A(n3509), .B(n3507), .Y(n3496) );
INVX3TS U2997 ( .A(n2675), .Y(n2859) );
NAND2X4TS U2998 ( .A(n2674), .B(FPMULT_Op_MX[11]), .Y(n2675) );
AOI21X2TS U2999 ( .A0(n2732), .A1(n2284), .B0(n2279), .Y(n3595) );
AO21XLTS U3000 ( .A0(n2676), .A1(n2671), .B0(n2658), .Y(n2279) );
XOR2X1TS U3001 ( .A(n2668), .B(FPMULT_Op_MX[11]), .Y(n2669) );
NOR2XLTS U3002 ( .A(n2667), .B(n2666), .Y(n2668) );
XNOR2X1TS U3003 ( .A(n2666), .B(n2661), .Y(n2665) );
NAND2X1TS U3004 ( .A(n2707), .B(n2715), .Y(n2664) );
OAI22X1TS U3005 ( .A0(n2854), .A1(n2675), .B0(n2853), .B1(n2859), .Y(n2682)
);
NOR2X1TS U3006 ( .A(n3519), .B(n3524), .Y(n2494) );
OAI21X1TS U3007 ( .A0(n3519), .A1(n3525), .B0(n3520), .Y(n2493) );
NOR2X1TS U3008 ( .A(n2496), .B(n2495), .Y(n3507) );
CMPR42X1TS U3009 ( .A(DP_OP_453J210_122_681_n463), .B(
DP_OP_453J210_122_681_n437), .C(DP_OP_453J210_122_681_n450), .D(
DP_OP_453J210_122_681_n238), .ICI(DP_OP_453J210_122_681_n239), .S(
DP_OP_453J210_122_681_n234), .ICO(DP_OP_453J210_122_681_n232), .CO(
DP_OP_453J210_122_681_n233) );
AO21XLTS U3010 ( .A0(n2885), .A1(n2263), .B0(n2873), .Y(
DP_OP_453J210_122_681_n463) );
OAI22X1TS U3011 ( .A0(n2856), .A1(n2675), .B0(n2854), .B1(n2859), .Y(
DP_OP_453J210_122_681_n437) );
CMPR42X1TS U3012 ( .A(DP_OP_453J210_122_681_n464), .B(
DP_OP_453J210_122_681_n438), .C(DP_OP_453J210_122_681_n451), .D(
DP_OP_453J210_122_681_n247), .ICI(DP_OP_453J210_122_681_n244), .S(
DP_OP_453J210_122_681_n240), .ICO(DP_OP_453J210_122_681_n238), .CO(
DP_OP_453J210_122_681_n239) );
OAI22X1TS U3013 ( .A0(n2856), .A1(n2859), .B0(n2855), .B1(n2675), .Y(
DP_OP_453J210_122_681_n438) );
OAI21X1TS U3014 ( .A0(n3529), .A1(n2470), .B0(n2469), .Y(n3518) );
AOI21X1TS U3015 ( .A0(n2322), .A1(n3530), .B0(n2468), .Y(n2469) );
NAND2X1TS U3016 ( .A(n2322), .B(n2321), .Y(n2470) );
INVX2TS U3017 ( .A(n3531), .Y(n2468) );
CMPR42X1TS U3018 ( .A(DP_OP_453J210_122_681_n452), .B(
DP_OP_453J210_122_681_n255), .C(DP_OP_453J210_122_681_n248), .D(
DP_OP_453J210_122_681_n252), .ICI(DP_OP_453J210_122_681_n253), .S(
DP_OP_453J210_122_681_n246), .ICO(DP_OP_453J210_122_681_n244), .CO(
DP_OP_453J210_122_681_n245) );
CMPR42X1TS U3019 ( .A(DP_OP_453J210_122_681_n466), .B(
DP_OP_453J210_122_681_n263), .C(DP_OP_453J210_122_681_n256), .D(
DP_OP_453J210_122_681_n264), .ICI(DP_OP_453J210_122_681_n260), .S(
DP_OP_453J210_122_681_n254), .ICO(DP_OP_453J210_122_681_n252), .CO(
DP_OP_453J210_122_681_n253) );
AOI21X1TS U3020 ( .A0(n2439), .A1(n3537), .B0(n2438), .Y(n3529) );
NOR2X1TS U3021 ( .A(n3538), .B(n3543), .Y(n2439) );
OAI21X1TS U3022 ( .A0(n3538), .A1(n3544), .B0(n3539), .Y(n2438) );
CMPR42X1TS U3023 ( .A(DP_OP_453J210_122_681_n272), .B(
DP_OP_453J210_122_681_n273), .C(DP_OP_453J210_122_681_n265), .D(
DP_OP_453J210_122_681_n269), .ICI(DP_OP_453J210_122_681_n409), .S(
DP_OP_453J210_122_681_n262), .ICO(DP_OP_453J210_122_681_n260), .CO(
DP_OP_453J210_122_681_n261) );
OAI22X1TS U3024 ( .A0(n2413), .A1(n2577), .B0(n2276), .B1(n2447), .Y(n2462)
);
OAI22X1TS U3025 ( .A0(n2412), .A1(n2277), .B0(n2577), .B1(n2288), .Y(n2463)
);
CMPR42X1TS U3026 ( .A(DP_OP_453J210_122_681_n284), .B(
DP_OP_453J210_122_681_n281), .C(DP_OP_453J210_122_681_n274), .D(
DP_OP_453J210_122_681_n282), .ICI(DP_OP_453J210_122_681_n278), .S(
DP_OP_453J210_122_681_n271), .ICO(DP_OP_453J210_122_681_n269), .CO(
DP_OP_453J210_122_681_n270) );
OAI21X1TS U3027 ( .A0(n3551), .A1(n3548), .B0(n3549), .Y(n3537) );
NOR2BX1TS U3028 ( .AN(n2278), .B(n2576), .Y(n2417) );
OAI22X1TS U3029 ( .A0(n2444), .A1(n2419), .B0(n2414), .B1(n3566), .Y(n2418)
);
CMPR42X1TS U3030 ( .A(DP_OP_453J210_122_681_n295), .B(
DP_OP_453J210_122_681_n293), .C(DP_OP_453J210_122_681_n283), .D(
DP_OP_453J210_122_681_n411), .ICI(DP_OP_453J210_122_681_n289), .S(
DP_OP_453J210_122_681_n280), .ICO(DP_OP_453J210_122_681_n278), .CO(
DP_OP_453J210_122_681_n279) );
OAI22X1TS U3031 ( .A0(n2431), .A1(n2430), .B0(n2271), .B1(n2429), .Y(n2432)
);
ADDHX1TS U3032 ( .A(n2428), .B(n2427), .CO(n2434), .S(n2433) );
OAI22X1TS U3033 ( .A0(n2444), .A1(n2422), .B0(n2419), .B1(n3566), .Y(n2428)
);
OAI22X1TS U3034 ( .A0(n2420), .A1(n2271), .B0(n2430), .B1(n2300), .Y(n2427)
);
NAND2BXLTS U3035 ( .AN(n2278), .B(n2243), .Y(n2420) );
CMPR42X1TS U3036 ( .A(DP_OP_453J210_122_681_n497), .B(
DP_OP_453J210_122_681_n307), .C(DP_OP_453J210_122_681_n315), .D(
DP_OP_453J210_122_681_n305), .ICI(DP_OP_453J210_122_681_n311), .S(
DP_OP_453J210_122_681_n302), .ICO(DP_OP_453J210_122_681_n300), .CO(
DP_OP_453J210_122_681_n301) );
CMPR42X1TS U3037 ( .A(DP_OP_453J210_122_681_n296), .B(
DP_OP_453J210_122_681_n304), .C(DP_OP_453J210_122_681_n294), .D(
DP_OP_453J210_122_681_n300), .ICI(DP_OP_453J210_122_681_n412), .S(
DP_OP_453J210_122_681_n291), .ICO(DP_OP_453J210_122_681_n289), .CO(
DP_OP_453J210_122_681_n290) );
OAI22X1TS U3038 ( .A0(n2278), .A1(n2444), .B0(n2423), .B1(n3566), .Y(n3368)
);
OAI22X1TS U3039 ( .A0(n2421), .A1(n3566), .B0(n2444), .B1(
DP_OP_453J210_122_681_n2030), .Y(n3367) );
NAND2BXLTS U3040 ( .AN(n2278), .B(FPMULT_Op_MY[13]), .Y(n2421) );
NAND2X1TS U3041 ( .A(n3368), .B(n3367), .Y(n3369) );
CMPR42X1TS U3042 ( .A(DP_OP_453J210_122_681_n498), .B(
DP_OP_453J210_122_681_n511), .C(DP_OP_453J210_122_681_n326), .D(
DP_OP_453J210_122_681_n322), .ICI(DP_OP_453J210_122_681_n316), .S(
DP_OP_453J210_122_681_n313), .ICO(DP_OP_453J210_122_681_n311), .CO(
DP_OP_453J210_122_681_n312) );
CMPR42X1TS U3043 ( .A(DP_OP_453J210_122_681_n336), .B(
DP_OP_453J210_122_681_n512), .C(DP_OP_453J210_122_681_n337), .D(
DP_OP_453J210_122_681_n333), .ICI(DP_OP_453J210_122_681_n327), .S(
DP_OP_453J210_122_681_n324), .ICO(DP_OP_453J210_122_681_n322), .CO(
DP_OP_453J210_122_681_n323) );
NAND2BXLTS U3044 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n3870) );
ADDHXLTS U3045 ( .A(n3066), .B(n3065), .CO(n3078), .S(n3069) );
NOR2XLTS U3046 ( .A(n3146), .B(n3077), .Y(n3065) );
NOR2XLTS U3047 ( .A(n3193), .B(n3564), .Y(n3066) );
NOR2XLTS U3048 ( .A(n3146), .B(n3164), .Y(n3080) );
NOR2XLTS U3049 ( .A(n3076), .B(n3213), .Y(n3096) );
NOR2XLTS U3050 ( .A(n3146), .B(n3193), .Y(n3093) );
CLKXOR2X2TS U3051 ( .A(n2751), .B(n2750), .Y(n2933) );
XNOR2X1TS U3052 ( .A(n2246), .B(n2951), .Y(n3560) );
XNOR2X1TS U3053 ( .A(n2246), .B(n2949), .Y(n2952) );
XNOR2X1TS U3054 ( .A(n2246), .B(n2911), .Y(n2950) );
NAND2X4TS U3055 ( .A(n2836), .B(n3567), .Y(n3562) );
XOR2X1TS U3056 ( .A(n2283), .B(n2835), .Y(n2836) );
ADDHX1TS U3057 ( .A(n2852), .B(n2851), .CO(DP_OP_453J210_122_681_n397), .S(
DP_OP_453J210_122_681_n398) );
OAI22X1TS U3058 ( .A0(n2932), .A1(n2848), .B0(n2265), .B1(n2847), .Y(n2852)
);
NAND2BXLTS U3059 ( .AN(n3568), .B(n2267), .Y(n2847) );
OAI22X1TS U3060 ( .A0(n3562), .A1(n2950), .B0(n2843), .B1(n3567), .Y(n2844)
);
OAI22X1TS U3061 ( .A0(n2932), .A1(n2849), .B0(n2265), .B1(n2842), .Y(n2845)
);
OAI22X1TS U3062 ( .A0(n2948), .A1(n3567), .B0(n3562), .B1(n2843), .Y(n2837)
);
OAI22X1TS U3063 ( .A0(n2932), .A1(n2842), .B0(n2265), .B1(n2931), .Y(n2838)
);
CMPR42X1TS U3064 ( .A(DP_OP_453J210_122_681_n492), .B(
DP_OP_453J210_122_681_n505), .C(DP_OP_453J210_122_681_n387), .D(
DP_OP_453J210_122_681_n518), .ICI(DP_OP_453J210_122_681_n531), .S(
DP_OP_453J210_122_681_n381), .ICO(DP_OP_453J210_122_681_n379), .CO(
DP_OP_453J210_122_681_n380) );
CMPR42X1TS U3065 ( .A(DP_OP_453J210_122_681_n375), .B(
DP_OP_453J210_122_681_n504), .C(DP_OP_453J210_122_681_n379), .D(
DP_OP_453J210_122_681_n517), .ICI(DP_OP_453J210_122_681_n530), .S(
DP_OP_453J210_122_681_n373), .ICO(DP_OP_453J210_122_681_n371), .CO(
DP_OP_453J210_122_681_n372) );
CMPR42X1TS U3066 ( .A(DP_OP_453J210_122_681_n503), .B(
DP_OP_453J210_122_681_n367), .C(DP_OP_453J210_122_681_n529), .D(
DP_OP_453J210_122_681_n516), .ICI(DP_OP_453J210_122_681_n371), .S(
DP_OP_453J210_122_681_n365), .ICO(DP_OP_453J210_122_681_n363), .CO(
DP_OP_453J210_122_681_n364) );
OAI22X1TS U3067 ( .A0(n2946), .A1(n3562), .B0(n2944), .B1(n3567), .Y(
DP_OP_453J210_122_681_n529) );
CMPR42X1TS U3068 ( .A(DP_OP_453J210_122_681_n502), .B(
DP_OP_453J210_122_681_n515), .C(DP_OP_453J210_122_681_n357), .D(
DP_OP_453J210_122_681_n528), .ICI(DP_OP_453J210_122_681_n363), .S(
DP_OP_453J210_122_681_n355), .ICO(DP_OP_453J210_122_681_n353), .CO(
DP_OP_453J210_122_681_n354) );
OAI22X1TS U3069 ( .A0(n2942), .A1(n3567), .B0(n3562), .B1(n2944), .Y(
DP_OP_453J210_122_681_n528) );
CMPR42X1TS U3070 ( .A(DP_OP_453J210_122_681_n501), .B(
DP_OP_453J210_122_681_n356), .C(DP_OP_453J210_122_681_n527), .D(
DP_OP_453J210_122_681_n349), .ICI(DP_OP_453J210_122_681_n353), .S(
DP_OP_453J210_122_681_n346), .ICO(DP_OP_453J210_122_681_n344), .CO(
DP_OP_453J210_122_681_n345) );
CMPR42X1TS U3071 ( .A(DP_OP_453J210_122_681_n513), .B(
DP_OP_453J210_122_681_n526), .C(DP_OP_453J210_122_681_n348), .D(
DP_OP_453J210_122_681_n344), .ICI(DP_OP_453J210_122_681_n338), .S(
DP_OP_453J210_122_681_n335), .ICO(DP_OP_453J210_122_681_n333), .CO(
DP_OP_453J210_122_681_n334) );
OAI22X1TS U3072 ( .A0(n2940), .A1(n3562), .B0(n2938), .B1(n3567), .Y(
DP_OP_453J210_122_681_n526) );
NOR2XLTS U3073 ( .A(n3565), .B(n3269), .Y(n3122) );
NAND2X4TS U3074 ( .A(n2247), .B(n2302), .Y(n2645) );
AO21XLTS U3075 ( .A0(n2624), .A1(n2273), .B0(n2303), .Y(n2639) );
AOI21X1TS U3076 ( .A0(n2631), .A1(n2565), .B0(n2564), .Y(n3361) );
NOR2X1TS U3077 ( .A(n2582), .B(n2581), .Y(n3357) );
NAND2X1TS U3078 ( .A(n2582), .B(n2581), .Y(n3358) );
INVX2TS U3079 ( .A(n3369), .Y(n3554) );
NOR2X2TS U3080 ( .A(DP_OP_453J210_122_681_n299), .B(
DP_OP_453J210_122_681_n309), .Y(n3656) );
NOR2X2TS U3081 ( .A(n2563), .B(n2562), .Y(n3489) );
NAND2X1TS U3082 ( .A(n2632), .B(n2325), .Y(n3487) );
AOI21X1TS U3083 ( .A0(n2325), .A1(n2561), .B0(n2560), .Y(n3486) );
INVX2TS U3084 ( .A(n3364), .Y(n2560) );
NAND2X1TS U3085 ( .A(n2563), .B(n2562), .Y(n3490) );
NAND2X1TS U3086 ( .A(n2559), .B(n2558), .Y(n3364) );
NOR2X1TS U3087 ( .A(n2557), .B(n2556), .Y(n3363) );
NAND2X1TS U3088 ( .A(n2557), .B(n2556), .Y(n3362) );
INVX2TS U3089 ( .A(n3363), .Y(n2632) );
INVX2TS U3090 ( .A(n2631), .Y(n3488) );
NAND2X1TS U3091 ( .A(n2502), .B(n2501), .Y(n3498) );
NOR2X2TS U3092 ( .A(n2502), .B(n2501), .Y(n3497) );
XOR2X1TS U3093 ( .A(DP_OP_453J210_122_681_n221), .B(n3596), .Y(n3597) );
AOI21X1TS U3094 ( .A0(n3517), .A1(n3496), .B0(n3495), .Y(n3506) );
NOR2X2TS U3095 ( .A(n2500), .B(n2499), .Y(n3502) );
NAND2X1TS U3096 ( .A(n2500), .B(n2499), .Y(n3503) );
CMPR42X1TS U3097 ( .A(DP_OP_453J210_122_681_n448), .B(
DP_OP_453J210_122_681_n435), .C(DP_OP_453J210_122_681_n227), .D(
DP_OP_453J210_122_681_n224), .ICI(DP_OP_453J210_122_681_n766), .S(
DP_OP_453J210_122_681_n223), .ICO(DP_OP_453J210_122_681_n221), .CO(
DP_OP_453J210_122_681_n222) );
INVX2TS U3098 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[23]), .Y(
DP_OP_453J210_122_681_n766) );
INVX2TS U3099 ( .A(n3514), .Y(n3508) );
NAND2X1TS U3100 ( .A(n2498), .B(n2497), .Y(n3510) );
NOR2X2TS U3101 ( .A(n2498), .B(n2497), .Y(n3509) );
NOR2X2TS U3102 ( .A(DP_OP_453J210_122_681_n226), .B(
DP_OP_453J210_122_681_n230), .Y(n3607) );
CMPR42X1TS U3103 ( .A(DP_OP_453J210_122_681_n228), .B(
DP_OP_453J210_122_681_n233), .C(DP_OP_453J210_122_681_n404), .D(
DP_OP_453J210_122_681_n229), .ICI(
FPMULT_Sgf_operation_EVEN1_Q_left[23]), .S(DP_OP_453J210_122_681_n226),
.ICO(DP_OP_453J210_122_681_n224), .CO(DP_OP_453J210_122_681_n225) );
NAND2X1TS U3104 ( .A(n2496), .B(n2495), .Y(n3514) );
INVX2TS U3105 ( .A(n3494), .Y(n3517) );
INVX2TS U3106 ( .A(n3507), .Y(n3515) );
OAI21X1TS U3107 ( .A0(n3621), .A1(n3617), .B0(n3618), .Y(n3606) );
CMPR42X1TS U3108 ( .A(DP_OP_453J210_122_681_n234), .B(
DP_OP_453J210_122_681_n405), .C(DP_OP_453J210_122_681_n768), .D(
DP_OP_453J210_122_681_n235), .ICI(DP_OP_453J210_122_681_n767), .S(
DP_OP_453J210_122_681_n231), .ICO(DP_OP_453J210_122_681_n229), .CO(
DP_OP_453J210_122_681_n230) );
INVX2TS U3109 ( .A(n3725), .Y(DP_OP_453J210_122_681_n767) );
INVX2TS U3110 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .Y(
DP_OP_453J210_122_681_n768) );
NOR2X2TS U3111 ( .A(n2492), .B(n2491), .Y(n3519) );
CMPR42X1TS U3112 ( .A(DP_OP_453J210_122_681_n240), .B(
DP_OP_453J210_122_681_n245), .C(DP_OP_453J210_122_681_n406), .D(
DP_OP_453J210_122_681_n241), .ICI(
FPMULT_Sgf_operation_EVEN1_Q_left[21]), .S(DP_OP_453J210_122_681_n237),
.ICO(DP_OP_453J210_122_681_n235), .CO(DP_OP_453J210_122_681_n236) );
INVX2TS U3113 ( .A(n3518), .Y(n3528) );
NOR2X2TS U3114 ( .A(n2490), .B(n2489), .Y(n3524) );
NAND2X1TS U3115 ( .A(n2490), .B(n2489), .Y(n3525) );
CMPR42X1TS U3116 ( .A(DP_OP_453J210_122_681_n246), .B(
DP_OP_453J210_122_681_n407), .C(DP_OP_453J210_122_681_n770), .D(
DP_OP_453J210_122_681_n249), .ICI(DP_OP_453J210_122_681_n769), .S(
DP_OP_453J210_122_681_n243), .ICO(DP_OP_453J210_122_681_n241), .CO(
DP_OP_453J210_122_681_n242) );
INVX2TS U3117 ( .A(n4673), .Y(DP_OP_453J210_122_681_n769) );
INVX2TS U3118 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .Y(
DP_OP_453J210_122_681_n770) );
NOR2X2TS U3119 ( .A(DP_OP_453J210_122_681_n243), .B(
DP_OP_453J210_122_681_n250), .Y(n3625) );
NAND2X1TS U3120 ( .A(n2467), .B(n2466), .Y(n3531) );
INVX2TS U3121 ( .A(n3534), .Y(n3530) );
CMPR42X1TS U3122 ( .A(DP_OP_453J210_122_681_n254), .B(
DP_OP_453J210_122_681_n261), .C(DP_OP_453J210_122_681_n408), .D(
DP_OP_453J210_122_681_n257), .ICI(
FPMULT_Sgf_operation_EVEN1_Q_left[19]), .S(DP_OP_453J210_122_681_n251),
.ICO(DP_OP_453J210_122_681_n249), .CO(DP_OP_453J210_122_681_n250) );
INVX2TS U3123 ( .A(n3529), .Y(n3536) );
CMPR42X1TS U3124 ( .A(DP_OP_453J210_122_681_n270), .B(
DP_OP_453J210_122_681_n772), .C(DP_OP_453J210_122_681_n771), .D(
DP_OP_453J210_122_681_n262), .ICI(DP_OP_453J210_122_681_n266), .S(
DP_OP_453J210_122_681_n259), .ICO(DP_OP_453J210_122_681_n257), .CO(
DP_OP_453J210_122_681_n258) );
INVX2TS U3125 ( .A(n4678), .Y(DP_OP_453J210_122_681_n771) );
INVX2TS U3126 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .Y(
DP_OP_453J210_122_681_n772) );
NAND2X1TS U3127 ( .A(n3640), .B(n2323), .Y(n3588) );
AOI21X1TS U3128 ( .A0(n3639), .A1(n2323), .B0(n3586), .Y(n3587) );
INVX2TS U3129 ( .A(n3641), .Y(n3586) );
NOR2X2TS U3130 ( .A(n2437), .B(n2436), .Y(n3538) );
NAND2X1TS U3131 ( .A(n2437), .B(n2436), .Y(n3539) );
CMPR42X1TS U3132 ( .A(DP_OP_453J210_122_681_n410), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[17]), .C(DP_OP_453J210_122_681_n271),
.D(DP_OP_453J210_122_681_n279), .ICI(DP_OP_453J210_122_681_n275), .S(
DP_OP_453J210_122_681_n268), .ICO(DP_OP_453J210_122_681_n266), .CO(
DP_OP_453J210_122_681_n267) );
INVX2TS U3133 ( .A(n3537), .Y(n3547) );
NOR2X2TS U3134 ( .A(n2435), .B(n2434), .Y(n3543) );
NAND2X1TS U3135 ( .A(n2435), .B(n2434), .Y(n3544) );
NOR2X2TS U3136 ( .A(DP_OP_453J210_122_681_n277), .B(
DP_OP_453J210_122_681_n287), .Y(n3646) );
CMPR42X1TS U3137 ( .A(DP_OP_453J210_122_681_n773), .B(
DP_OP_453J210_122_681_n774), .C(DP_OP_453J210_122_681_n290), .D(
DP_OP_453J210_122_681_n286), .ICI(DP_OP_453J210_122_681_n280), .S(
DP_OP_453J210_122_681_n277), .ICO(DP_OP_453J210_122_681_n275), .CO(
DP_OP_453J210_122_681_n276) );
INVX2TS U3138 ( .A(n4683), .Y(DP_OP_453J210_122_681_n773) );
NOR2X1TS U3139 ( .A(n2433), .B(n2432), .Y(n3548) );
AOI21X1TS U3140 ( .A0(n3554), .A1(n2298), .B0(n2426), .Y(n3551) );
NAND2X1TS U3141 ( .A(n2433), .B(n2432), .Y(n3549) );
CMPR42X1TS U3142 ( .A(DP_OP_453J210_122_681_n413), .B(
DP_OP_453J210_122_681_n312), .C(FPMULT_Sgf_operation_EVEN1_Q_left[14]),
.D(DP_OP_453J210_122_681_n302), .ICI(DP_OP_453J210_122_681_n308), .S(
DP_OP_453J210_122_681_n299), .ICO(DP_OP_453J210_122_681_n297), .CO(
DP_OP_453J210_122_681_n298) );
CMPR42X1TS U3143 ( .A(DP_OP_453J210_122_681_n775), .B(
DP_OP_453J210_122_681_n301), .C(FPMULT_Sgf_operation_EVEN1_Q_left[15]),
.D(DP_OP_453J210_122_681_n297), .ICI(DP_OP_453J210_122_681_n291), .S(
DP_OP_453J210_122_681_n288), .ICO(DP_OP_453J210_122_681_n286), .CO(
DP_OP_453J210_122_681_n287) );
INVX2TS U3144 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[14]), .Y(
DP_OP_453J210_122_681_n775) );
NOR2X1TS U3145 ( .A(DP_OP_453J210_122_681_n288), .B(
DP_OP_453J210_122_681_n298), .Y(n3644) );
NOR2X1TS U3146 ( .A(n3656), .B(n3661), .Y(n3585) );
OAI21X1TS U3147 ( .A0(n3656), .A1(n3662), .B0(n3657), .Y(n3584) );
NAND2X1TS U3148 ( .A(n2221), .B(n3369), .Y(DP_OP_453J210_122_681_n788) );
NAND2X1TS U3149 ( .A(n2316), .B(n2317), .Y(n3583) );
AOI21X1TS U3150 ( .A0(n2316), .A1(n3667), .B0(n3581), .Y(n3582) );
INVX2TS U3151 ( .A(n3668), .Y(n3581) );
CMPR42X1TS U3152 ( .A(DP_OP_453J210_122_681_n323), .B(
DP_OP_453J210_122_681_n414), .C(DP_OP_453J210_122_681_n776), .D(
DP_OP_453J210_122_681_n313), .ICI(DP_OP_453J210_122_681_n319), .S(
DP_OP_453J210_122_681_n310), .ICO(DP_OP_453J210_122_681_n308), .CO(
DP_OP_453J210_122_681_n309) );
INVX2TS U3153 ( .A(n4690), .Y(DP_OP_453J210_122_681_n776) );
CMPR42X1TS U3154 ( .A(DP_OP_453J210_122_681_n334), .B(
DP_OP_453J210_122_681_n415), .C(DP_OP_453J210_122_681_n324), .D(
DP_OP_453J210_122_681_n777), .ICI(DP_OP_453J210_122_681_n330), .S(
DP_OP_453J210_122_681_n321), .ICO(DP_OP_453J210_122_681_n319), .CO(
DP_OP_453J210_122_681_n320) );
INVX2TS U3155 ( .A(n4694), .Y(DP_OP_453J210_122_681_n777) );
ADDHX1TS U3156 ( .A(n3064), .B(n3063), .CO(n3067), .S(n3061) );
NOR2X1TS U3157 ( .A(n3076), .B(n3164), .Y(n3068) );
NOR2XLTS U3158 ( .A(n3076), .B(n3193), .Y(n3099) );
NOR2X1TS U3159 ( .A(n3565), .B(n3314), .Y(n3111) );
NOR2XLTS U3160 ( .A(n3444), .B(n3449), .Y(n3130) );
INVX4TS U3161 ( .A(n2834), .Y(n3567) );
XOR2X1TS U3162 ( .A(n2253), .B(n2278), .Y(n2834) );
NAND2BXLTS U3163 ( .AN(n3568), .B(n2246), .Y(n3563) );
OAI22X1TS U3164 ( .A0(n3562), .A1(n3568), .B0(n3560), .B1(n3567), .Y(n3561)
);
CMPR42X1TS U3165 ( .A(DP_OP_453J210_122_681_n522), .B(
DP_OP_453J210_122_681_n787), .C(DP_OP_453J210_122_681_n788), .D(
DP_OP_453J210_122_681_n535), .ICI(DP_OP_453J210_122_681_n425), .S(
DP_OP_453J210_122_681_n401), .ICO(DP_OP_453J210_122_681_n399), .CO(
DP_OP_453J210_122_681_n400) );
OAI22X1TS U3166 ( .A0(n3562), .A1(n3560), .B0(n2952), .B1(n3567), .Y(
DP_OP_453J210_122_681_n535) );
CMPR42X1TS U3167 ( .A(DP_OP_453J210_122_681_n534), .B(
DP_OP_453J210_122_681_n398), .C(DP_OP_453J210_122_681_n399), .D(
DP_OP_453J210_122_681_n424), .ICI(DP_OP_453J210_122_681_n786), .S(
DP_OP_453J210_122_681_n396), .ICO(DP_OP_453J210_122_681_n394), .CO(
DP_OP_453J210_122_681_n395) );
OAI22X1TS U3168 ( .A0(n3562), .A1(n2952), .B0(n2950), .B1(n3567), .Y(
DP_OP_453J210_122_681_n534) );
INVX2TS U3169 ( .A(n4803), .Y(DP_OP_453J210_122_681_n424) );
CMPR42X1TS U3170 ( .A(DP_OP_453J210_122_681_n397), .B(
DP_OP_453J210_122_681_n423), .C(DP_OP_453J210_122_681_n393), .D(
DP_OP_453J210_122_681_n785), .ICI(DP_OP_453J210_122_681_n394), .S(
DP_OP_453J210_122_681_n391), .ICO(DP_OP_453J210_122_681_n389), .CO(
DP_OP_453J210_122_681_n390) );
CMPR42X1TS U3171 ( .A(DP_OP_453J210_122_681_n392), .B(
DP_OP_453J210_122_681_n422), .C(DP_OP_453J210_122_681_n386), .D(
DP_OP_453J210_122_681_n784), .ICI(DP_OP_453J210_122_681_n389), .S(
DP_OP_453J210_122_681_n384), .ICO(DP_OP_453J210_122_681_n382), .CO(
DP_OP_453J210_122_681_n383) );
INVX2TS U3172 ( .A(n4722), .Y(DP_OP_453J210_122_681_n784) );
AOI21X1TS U3173 ( .A0(n3695), .A1(n2313), .B0(n3575), .Y(n3685) );
INVX2TS U3174 ( .A(n3693), .Y(n3575) );
CMPR42X1TS U3175 ( .A(DP_OP_453J210_122_681_n385), .B(
DP_OP_453J210_122_681_n381), .C(DP_OP_453J210_122_681_n382), .D(
DP_OP_453J210_122_681_n421), .ICI(DP_OP_453J210_122_681_n783), .S(
DP_OP_453J210_122_681_n378), .ICO(DP_OP_453J210_122_681_n376), .CO(
DP_OP_453J210_122_681_n377) );
INVX2TS U3176 ( .A(n4800), .Y(DP_OP_453J210_122_681_n421) );
CMPR42X1TS U3177 ( .A(DP_OP_453J210_122_681_n380), .B(
DP_OP_453J210_122_681_n420), .C(DP_OP_453J210_122_681_n373), .D(
DP_OP_453J210_122_681_n376), .ICI(DP_OP_453J210_122_681_n782), .S(
DP_OP_453J210_122_681_n370), .ICO(DP_OP_453J210_122_681_n368), .CO(
DP_OP_453J210_122_681_n369) );
INVX2TS U3178 ( .A(n4714), .Y(DP_OP_453J210_122_681_n782) );
OAI21X1TS U3179 ( .A0(n3685), .A1(n3578), .B0(n3577), .Y(n3674) );
NAND2X1TS U3180 ( .A(n2315), .B(n2314), .Y(n3578) );
AOI21X1TS U3181 ( .A0(n2315), .A1(n3686), .B0(n3576), .Y(n3577) );
INVX2TS U3182 ( .A(n3687), .Y(n3576) );
CMPR42X1TS U3183 ( .A(DP_OP_453J210_122_681_n372), .B(
DP_OP_453J210_122_681_n419), .C(DP_OP_453J210_122_681_n365), .D(
DP_OP_453J210_122_681_n781), .ICI(DP_OP_453J210_122_681_n368), .S(
DP_OP_453J210_122_681_n362), .ICO(DP_OP_453J210_122_681_n360), .CO(
DP_OP_453J210_122_681_n361) );
INVX2TS U3184 ( .A(n4710), .Y(DP_OP_453J210_122_681_n781) );
NOR2X2TS U3185 ( .A(DP_OP_453J210_122_681_n343), .B(
DP_OP_453J210_122_681_n351), .Y(n3675) );
CMPR42X1TS U3186 ( .A(DP_OP_453J210_122_681_n364), .B(
DP_OP_453J210_122_681_n418), .C(DP_OP_453J210_122_681_n355), .D(
DP_OP_453J210_122_681_n360), .ICI(DP_OP_453J210_122_681_n780), .S(
DP_OP_453J210_122_681_n352), .ICO(DP_OP_453J210_122_681_n350), .CO(
DP_OP_453J210_122_681_n351) );
INVX2TS U3187 ( .A(n4706), .Y(DP_OP_453J210_122_681_n780) );
CMPR42X1TS U3188 ( .A(DP_OP_453J210_122_681_n354), .B(
DP_OP_453J210_122_681_n779), .C(DP_OP_453J210_122_681_n417), .D(
DP_OP_453J210_122_681_n346), .ICI(DP_OP_453J210_122_681_n350), .S(
DP_OP_453J210_122_681_n343), .ICO(DP_OP_453J210_122_681_n341), .CO(
DP_OP_453J210_122_681_n342) );
INVX2TS U3189 ( .A(n4702), .Y(DP_OP_453J210_122_681_n779) );
CMPR42X1TS U3190 ( .A(DP_OP_453J210_122_681_n345), .B(
DP_OP_453J210_122_681_n416), .C(DP_OP_453J210_122_681_n335), .D(
DP_OP_453J210_122_681_n341), .ICI(DP_OP_453J210_122_681_n778), .S(
DP_OP_453J210_122_681_n332), .ICO(DP_OP_453J210_122_681_n330), .CO(
DP_OP_453J210_122_681_n331) );
INVX2TS U3191 ( .A(n4698), .Y(DP_OP_453J210_122_681_n778) );
NOR2X1TS U3192 ( .A(n3675), .B(n3680), .Y(n3580) );
OAI21X1TS U3193 ( .A0(n3675), .A1(n3681), .B0(n3676), .Y(n3579) );
NAND2X1TS U3194 ( .A(n2595), .B(n2594), .Y(n3483) );
OAI21X1TS U3195 ( .A0(n3361), .A1(n3357), .B0(n3358), .Y(n3485) );
NOR2X1TS U3196 ( .A(n2609), .B(n2608), .Y(n3352) );
AOI21X1TS U3197 ( .A0(n3485), .A1(n2320), .B0(n2596), .Y(n3356) );
INVX2TS U3198 ( .A(n3483), .Y(n2596) );
NAND2X1TS U3199 ( .A(n2609), .B(n2608), .Y(n3353) );
NAND2X1TS U3200 ( .A(n2618), .B(n2617), .Y(n3480) );
OAI21X1TS U3201 ( .A0(n3356), .A1(n3352), .B0(n3353), .Y(n3482) );
NOR2X1TS U3202 ( .A(n2628), .B(n2627), .Y(n2635) );
NAND2X1TS U3203 ( .A(n2628), .B(n2627), .Y(n2634) );
AOI21X1TS U3204 ( .A0(n3482), .A1(n2318), .B0(n2619), .Y(n2636) );
INVX2TS U3205 ( .A(n3480), .Y(n2619) );
NAND2X1TS U3206 ( .A(n2642), .B(n2641), .Y(n3477) );
XNOR2X1TS U3207 ( .A(n2646), .B(FPMULT_Op_MX[22]), .Y(n2647) );
CLKAND2X2TS U3208 ( .A(n2645), .B(n2247), .Y(n2646) );
OAI21X1TS U3209 ( .A0(n2636), .A1(n2635), .B0(n2634), .Y(n3479) );
INVX2TS U3210 ( .A(n3477), .Y(n2643) );
CLKXOR2X2TS U3211 ( .A(n3361), .B(n3360), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[17]) );
INVX2TS U3212 ( .A(n3656), .Y(n3658) );
NAND2X1TS U3213 ( .A(DP_OP_453J210_122_681_n299), .B(
DP_OP_453J210_122_681_n309), .Y(n3657) );
XNOR2X1TS U3214 ( .A(n3493), .B(n3492), .Y(n4683) );
NAND2X1TS U3215 ( .A(n3491), .B(n3490), .Y(n3492) );
INVX2TS U3216 ( .A(n3489), .Y(n3491) );
XNOR2X2TS U3217 ( .A(n3366), .B(n3365), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[15]) );
NAND2X1TS U3218 ( .A(n2325), .B(n3364), .Y(n3365) );
OAI21X1TS U3219 ( .A0(n3488), .A1(n3363), .B0(n3362), .Y(n3366) );
CLKXOR2X2TS U3220 ( .A(n3488), .B(n2633), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[14]) );
NAND2X1TS U3221 ( .A(n2632), .B(n3362), .Y(n2633) );
NAND2X1TS U3222 ( .A(n3499), .B(n3498), .Y(n3500) );
OAI21X1TS U3223 ( .A0(n3506), .A1(n3502), .B0(n3503), .Y(n3501) );
INVX2TS U3224 ( .A(n3497), .Y(n3499) );
NAND2X1TS U3225 ( .A(DP_OP_453J210_122_681_n222), .B(n3597), .Y(n3598) );
NAND2X1TS U3226 ( .A(n3504), .B(n3503), .Y(n3505) );
INVX2TS U3227 ( .A(n3502), .Y(n3504) );
AOI21X1TS U3228 ( .A0(n3594), .A1(n3606), .B0(n3593), .Y(n3605) );
NOR2X1TS U3229 ( .A(DP_OP_453J210_122_681_n223), .B(
DP_OP_453J210_122_681_n225), .Y(n3601) );
NAND2X1TS U3230 ( .A(DP_OP_453J210_122_681_n223), .B(
DP_OP_453J210_122_681_n225), .Y(n3602) );
NAND2X1TS U3231 ( .A(n3511), .B(n3510), .Y(n3512) );
AOI21X1TS U3232 ( .A0(n3517), .A1(n3515), .B0(n3508), .Y(n3513) );
INVX2TS U3233 ( .A(n3509), .Y(n3511) );
INVX2TS U3234 ( .A(n3607), .Y(n3609) );
NAND2X1TS U3235 ( .A(DP_OP_453J210_122_681_n226), .B(
DP_OP_453J210_122_681_n230), .Y(n3608) );
NAND2X1TS U3236 ( .A(n3515), .B(n3514), .Y(n3516) );
INVX2TS U3237 ( .A(n3606), .Y(n3616) );
NAND2X1TS U3238 ( .A(DP_OP_453J210_122_681_n231), .B(
DP_OP_453J210_122_681_n236), .Y(n3613) );
NOR2X2TS U3239 ( .A(DP_OP_453J210_122_681_n231), .B(
DP_OP_453J210_122_681_n236), .Y(n3612) );
XNOR2X1TS U3240 ( .A(n3523), .B(n3522), .Y(n4706) );
NAND2X1TS U3241 ( .A(n3521), .B(n3520), .Y(n3522) );
OAI21X1TS U3242 ( .A0(n3528), .A1(n3524), .B0(n3525), .Y(n3523) );
INVX2TS U3243 ( .A(n3519), .Y(n3521) );
NOR2X1TS U3244 ( .A(DP_OP_453J210_122_681_n237), .B(
DP_OP_453J210_122_681_n242), .Y(n3617) );
NAND2X1TS U3245 ( .A(DP_OP_453J210_122_681_n237), .B(
DP_OP_453J210_122_681_n242), .Y(n3618) );
NAND2X1TS U3246 ( .A(n3526), .B(n3525), .Y(n3527) );
INVX2TS U3247 ( .A(n3524), .Y(n3526) );
NAND2X1TS U3248 ( .A(DP_OP_453J210_122_681_n243), .B(
DP_OP_453J210_122_681_n250), .Y(n3626) );
INVX2TS U3249 ( .A(n3625), .Y(n3627) );
AOI21X1TS U3250 ( .A0(n2324), .A1(n3590), .B0(n3589), .Y(n3623) );
NAND2X1TS U3251 ( .A(n2324), .B(n3635), .Y(n3624) );
NAND2X1TS U3252 ( .A(n2322), .B(n3531), .Y(n3532) );
NOR2X1TS U3253 ( .A(DP_OP_453J210_122_681_n259), .B(
DP_OP_453J210_122_681_n267), .Y(n3630) );
NAND2X1TS U3254 ( .A(DP_OP_453J210_122_681_n251), .B(
DP_OP_453J210_122_681_n258), .Y(n3631) );
INVX2TS U3255 ( .A(n3630), .Y(n3635) );
NAND2X1TS U3256 ( .A(DP_OP_453J210_122_681_n259), .B(
DP_OP_453J210_122_681_n267), .Y(n3634) );
INVX2TS U3257 ( .A(n3622), .Y(n3637) );
XNOR2X1TS U3258 ( .A(n3542), .B(n3541), .Y(n4722) );
OAI21X1TS U3259 ( .A0(n3547), .A1(n3543), .B0(n3544), .Y(n3542) );
NAND2X1TS U3260 ( .A(n3540), .B(n3539), .Y(n3541) );
INVX2TS U3261 ( .A(n3538), .Y(n3540) );
NAND2X1TS U3262 ( .A(DP_OP_453J210_122_681_n268), .B(
DP_OP_453J210_122_681_n276), .Y(n3641) );
OAI21X1TS U3263 ( .A0(n3646), .A1(n3651), .B0(n3647), .Y(n3639) );
NOR2X1TS U3264 ( .A(n3646), .B(n3644), .Y(n3640) );
XOR2X1TS U3265 ( .A(n3547), .B(n3546), .Y(n4726) );
NAND2X1TS U3266 ( .A(n3545), .B(n3544), .Y(n3546) );
INVX2TS U3267 ( .A(n3651), .Y(n3645) );
INVX2TS U3268 ( .A(n3646), .Y(n3648) );
NAND2X1TS U3269 ( .A(DP_OP_453J210_122_681_n277), .B(
DP_OP_453J210_122_681_n287), .Y(n3647) );
XOR2X1TS U3270 ( .A(n3552), .B(n3551), .Y(n4730) );
NAND2X1TS U3271 ( .A(n3550), .B(n3549), .Y(n3552) );
INVX2TS U3272 ( .A(n3644), .Y(n3652) );
INVX2TS U3273 ( .A(n3638), .Y(n3654) );
INVX2TS U3274 ( .A(n3655), .Y(n3665) );
NAND2X1TS U3275 ( .A(DP_OP_453J210_122_681_n310), .B(
DP_OP_453J210_122_681_n320), .Y(n3662) );
NOR2X2TS U3276 ( .A(DP_OP_453J210_122_681_n310), .B(
DP_OP_453J210_122_681_n320), .Y(n3661) );
NAND2X1TS U3277 ( .A(DP_OP_453J210_122_681_n321), .B(
DP_OP_453J210_122_681_n331), .Y(n3668) );
INVX2TS U3278 ( .A(n3671), .Y(n3667) );
AO21XLTS U3279 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n4902), .B0(n4859),
.Y(n2230) );
AOI211X2TS U3280 ( .A0(n4902), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n4901),
.C0(n4842), .Y(n4880) );
NAND2BXLTS U3281 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n3844) );
NOR2X1TS U3282 ( .A(n3570), .B(n3569), .Y(n3713) );
NAND2X1TS U3283 ( .A(n3570), .B(n3569), .Y(n3714) );
NAND2X1TS U3284 ( .A(DP_OP_453J210_122_681_n401), .B(n3572), .Y(n3710) );
OAI21X1TS U3285 ( .A0(n3713), .A1(n3571), .B0(n3714), .Y(n3711) );
NOR2X1TS U3286 ( .A(DP_OP_453J210_122_681_n396), .B(
DP_OP_453J210_122_681_n400), .Y(n3705) );
AOI21X1TS U3287 ( .A0(n2285), .A1(n3711), .B0(n3573), .Y(n3708) );
NAND2X1TS U3288 ( .A(DP_OP_453J210_122_681_n396), .B(
DP_OP_453J210_122_681_n400), .Y(n3706) );
NAND2X1TS U3289 ( .A(DP_OP_453J210_122_681_n391), .B(
DP_OP_453J210_122_681_n395), .Y(n3701) );
OR2X1TS U3290 ( .A(DP_OP_453J210_122_681_n391), .B(
DP_OP_453J210_122_681_n395), .Y(n3702) );
OAI21X1TS U3291 ( .A0(n3708), .A1(n3705), .B0(n3706), .Y(n3703) );
NOR2X1TS U3292 ( .A(DP_OP_453J210_122_681_n384), .B(
DP_OP_453J210_122_681_n390), .Y(n3696) );
AOI21X1TS U3293 ( .A0(n3703), .A1(n3702), .B0(n3574), .Y(n3700) );
INVX2TS U3294 ( .A(n3701), .Y(n3574) );
NAND2X1TS U3295 ( .A(DP_OP_453J210_122_681_n384), .B(
DP_OP_453J210_122_681_n390), .Y(n3697) );
XOR2X1TS U3296 ( .A(n3393), .B(n3392), .Y(n4770) );
NAND2X1TS U3297 ( .A(DP_OP_453J210_122_681_n378), .B(
DP_OP_453J210_122_681_n383), .Y(n3693) );
OAI21X1TS U3298 ( .A0(n3700), .A1(n3696), .B0(n3697), .Y(n3695) );
NAND2X1TS U3299 ( .A(DP_OP_453J210_122_681_n370), .B(
DP_OP_453J210_122_681_n377), .Y(n3690) );
XOR2X1TS U3300 ( .A(n3385), .B(n3384), .Y(n4762) );
INVX2TS U3301 ( .A(n3685), .Y(n3692) );
OR2X1TS U3302 ( .A(DP_OP_453J210_122_681_n370), .B(
DP_OP_453J210_122_681_n377), .Y(n2314) );
INVX2TS U3303 ( .A(n3690), .Y(n3686) );
NAND2X1TS U3304 ( .A(DP_OP_453J210_122_681_n362), .B(
DP_OP_453J210_122_681_n369), .Y(n3687) );
XOR2X1TS U3305 ( .A(n3377), .B(n3376), .Y(n4754) );
INVX2TS U3306 ( .A(n3674), .Y(n3684) );
NOR2X2TS U3307 ( .A(DP_OP_453J210_122_681_n352), .B(
DP_OP_453J210_122_681_n361), .Y(n3680) );
NAND2X1TS U3308 ( .A(DP_OP_453J210_122_681_n352), .B(
DP_OP_453J210_122_681_n361), .Y(n3681) );
INVX2TS U3309 ( .A(n3675), .Y(n3677) );
NAND2X1TS U3310 ( .A(DP_OP_453J210_122_681_n343), .B(
DP_OP_453J210_122_681_n351), .Y(n3676) );
NAND2X1TS U3311 ( .A(DP_OP_453J210_122_681_n332), .B(
DP_OP_453J210_122_681_n342), .Y(n3671) );
INVX2TS U3312 ( .A(n3666), .Y(n3673) );
XNOR2X1TS U3313 ( .A(n3485), .B(n3484), .Y(n4678) );
NAND2X1TS U3314 ( .A(n2320), .B(n3483), .Y(n3484) );
CLKXOR2X2TS U3315 ( .A(n3356), .B(n3355), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[19]) );
NAND2X1TS U3316 ( .A(n3354), .B(n3353), .Y(n3355) );
INVX2TS U3317 ( .A(n3352), .Y(n3354) );
XNOR2X1TS U3318 ( .A(n3482), .B(n3481), .Y(n4673) );
NAND2X1TS U3319 ( .A(n2318), .B(n3480), .Y(n3481) );
CLKXOR2X2TS U3320 ( .A(n2636), .B(n2630), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[21]) );
NAND2X1TS U3321 ( .A(n2629), .B(n2634), .Y(n2630) );
INVX2TS U3322 ( .A(n2635), .Y(n2629) );
NAND2X1TS U3323 ( .A(n2309), .B(n3477), .Y(n3478) );
OAI21XLTS U3324 ( .A0(n3453), .A1(n3449), .B0(n3450), .Y(n3448) );
CLKXOR2X2TS U3325 ( .A(n2651), .B(n2650), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[23]) );
NAND2X1TS U3326 ( .A(n2308), .B(n2649), .Y(n2650) );
AOI21X1TS U3327 ( .A0(n3479), .A1(n2309), .B0(n2643), .Y(n2651) );
NAND2X1TS U3328 ( .A(n2648), .B(n2647), .Y(n2649) );
AOI222X4TS U3329 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(
FPADDSUB_DMP_SFG[16]), .B0(FPADDSUB_DmP_mant_SFG_SWR[18]), .B1(n5055),
.C0(FPADDSUB_DMP_SFG[16]), .C1(n5055), .Y(n5062) );
XNOR2X1TS U3330 ( .A(n3660), .B(n3659), .Y(n4735) );
NAND2X1TS U3331 ( .A(n3658), .B(n3657), .Y(n3659) );
ADDHXLTS U3332 ( .A(n4683), .B(n4682), .CO(n4680), .S(n4684) );
ADDHXLTS U3333 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[14]), .B(n4687), .CO(
n4685), .S(n4688) );
XNOR2X1TS U3334 ( .A(n3600), .B(n3599), .Y(n4691) );
NAND2X1TS U3335 ( .A(n2280), .B(n3598), .Y(n3599) );
XOR2X1TS U3336 ( .A(n3605), .B(n3604), .Y(n4695) );
NAND2X1TS U3337 ( .A(n3603), .B(n3602), .Y(n3604) );
XNOR2X1TS U3338 ( .A(n3611), .B(n3610), .Y(n4699) );
XOR2X1TS U3339 ( .A(n3616), .B(n3615), .Y(n4703) );
NAND2X1TS U3340 ( .A(n3614), .B(n3613), .Y(n3615) );
INVX2TS U3341 ( .A(n3612), .Y(n3614) );
NAND2X1TS U3342 ( .A(n3619), .B(n3618), .Y(n3620) );
INVX2TS U3343 ( .A(n3617), .Y(n3619) );
XNOR2X1TS U3344 ( .A(n3629), .B(n3628), .Y(n4711) );
NAND2X1TS U3345 ( .A(n3627), .B(n3626), .Y(n3628) );
XNOR2X1TS U3346 ( .A(n3633), .B(n3632), .Y(n4715) );
NAND2X1TS U3347 ( .A(n2324), .B(n3631), .Y(n3632) );
XOR2X1TS U3348 ( .A(n3637), .B(n3636), .Y(n4719) );
NAND2X1TS U3349 ( .A(n3635), .B(n3634), .Y(n3636) );
XOR2X1TS U3350 ( .A(n3643), .B(n3642), .Y(n4723) );
NAND2X1TS U3351 ( .A(n2323), .B(n3641), .Y(n3642) );
AOI21X1TS U3352 ( .A0(n3654), .A1(n3640), .B0(n3639), .Y(n3643) );
XOR2X1TS U3353 ( .A(n3650), .B(n3649), .Y(n4727) );
NAND2X1TS U3354 ( .A(n3648), .B(n3647), .Y(n3649) );
AOI21X1TS U3355 ( .A0(n3654), .A1(n3652), .B0(n3645), .Y(n3650) );
XNOR2X1TS U3356 ( .A(n3654), .B(n3653), .Y(n4731) );
NAND2X1TS U3357 ( .A(n3652), .B(n3651), .Y(n3653) );
XOR2X1TS U3358 ( .A(n3665), .B(n3664), .Y(n4739) );
NAND2X1TS U3359 ( .A(n3663), .B(n3662), .Y(n3664) );
INVX2TS U3360 ( .A(n3661), .Y(n3663) );
XOR2X1TS U3361 ( .A(n3670), .B(n3669), .Y(n4743) );
AOI21X1TS U3362 ( .A0(n3673), .A1(n2317), .B0(n3667), .Y(n3670) );
NAND2X1TS U3363 ( .A(n2316), .B(n3668), .Y(n3669) );
AOI222X4TS U3364 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1(
FPADDSUB_DMP_SFG[14]), .B0(FPADDSUB_DmP_mant_SFG_SWR[16]), .B1(n5043),
.C0(FPADDSUB_DMP_SFG[14]), .C1(n5043), .Y(n5048) );
AOI222X4TS U3365 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(
FPADDSUB_DMP_SFG[18]), .B0(FPADDSUB_DmP_mant_SFG_SWR[20]), .B1(n5069),
.C0(FPADDSUB_DMP_SFG[18]), .C1(n5069), .Y(n5074) );
AOI222X4TS U3366 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(
FPADDSUB_DMP_SFG[2]), .B0(FPADDSUB_DmP_mant_SFG_SWR[4]), .B1(n4971),
.C0(FPADDSUB_DMP_SFG[2]), .C1(n4971), .Y(n4976) );
AOI222X4TS U3367 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(
FPADDSUB_DMP_SFG[4]), .B0(FPADDSUB_DmP_mant_SFG_SWR[6]), .B1(n4983),
.C0(FPADDSUB_DMP_SFG[4]), .C1(n4983), .Y(n4988) );
AOI222X4TS U3368 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(
FPADDSUB_DMP_SFG[12]), .B0(FPADDSUB_DmP_mant_SFG_SWR[14]), .B1(n5031),
.C0(FPADDSUB_DMP_SFG[12]), .C1(n5031), .Y(n5036) );
AOI31X1TS U3369 ( .A0(n4103), .A1(n4102), .A2(n4101), .B0(n4437), .Y(n4384)
);
NAND2X1TS U3370 ( .A(n3715), .B(n3714), .Y(n3717) );
XNOR2X1TS U3371 ( .A(n3712), .B(n3711), .Y(n4785) );
NAND2X1TS U3372 ( .A(n2285), .B(n3710), .Y(n3712) );
XOR2X1TS U3373 ( .A(n3709), .B(n3708), .Y(n4779) );
NAND2X1TS U3374 ( .A(n3707), .B(n3706), .Y(n3709) );
XNOR2X1TS U3375 ( .A(n3704), .B(n3703), .Y(n4775) );
NAND2X1TS U3376 ( .A(n3702), .B(n3701), .Y(n3704) );
XOR2X1TS U3377 ( .A(n3700), .B(n3699), .Y(n4771) );
NAND2X1TS U3378 ( .A(n3698), .B(n3697), .Y(n3699) );
NAND2X1TS U3379 ( .A(n2313), .B(n3693), .Y(n3694) );
XNOR2X1TS U3380 ( .A(n3692), .B(n3691), .Y(n4763) );
NAND2X1TS U3381 ( .A(n2314), .B(n3690), .Y(n3691) );
XOR2X1TS U3382 ( .A(n3689), .B(n3688), .Y(n4759) );
NAND2X1TS U3383 ( .A(n2315), .B(n3687), .Y(n3688) );
XOR2X1TS U3384 ( .A(n3684), .B(n3683), .Y(n4755) );
NAND2X1TS U3385 ( .A(n3682), .B(n3681), .Y(n3683) );
INVX2TS U3386 ( .A(n3680), .Y(n3682) );
XNOR2X1TS U3387 ( .A(n3679), .B(n3678), .Y(n4751) );
NAND2X1TS U3388 ( .A(n3677), .B(n3676), .Y(n3678) );
XNOR2X1TS U3389 ( .A(n3673), .B(n3672), .Y(n4747) );
NAND2X1TS U3390 ( .A(n2317), .B(n3671), .Y(n3672) );
ADDHXLTS U3391 ( .A(n4678), .B(n4677), .CO(n4675), .S(n4679) );
ADDHXLTS U3392 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .B(n4669), .CO(
n3724), .S(n4670) );
ADDHXLTS U3393 ( .A(n3725), .B(n3724), .CO(n3721), .S(n3726) );
NAND4XLTS U3394 ( .A(n4596), .B(n4595), .C(n4594), .D(n4593), .Y(n4612) );
BUFX4TS U3395 ( .A(n4488), .Y(n4489) );
AO22XLTS U3396 ( .A0(n4475), .A1(result_add_subt[0]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(n2074) );
AO22XLTS U3397 ( .A0(n4582), .A1(result_add_subt[30]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(n1731) );
AO22XLTS U3398 ( .A0(n4576), .A1(result_add_subt[9]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[9]), .Y(n2048) );
AO22XLTS U3399 ( .A0(n4576), .A1(result_add_subt[7]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[7]), .Y(n2054) );
AO22XLTS U3400 ( .A0(n4576), .A1(result_add_subt[14]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[14]), .Y(n2033) );
AO22XLTS U3401 ( .A0(n4576), .A1(result_add_subt[11]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[11]), .Y(n2042) );
AO22XLTS U3402 ( .A0(n4576), .A1(result_add_subt[8]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[8]), .Y(n2051) );
AO22XLTS U3403 ( .A0(n4576), .A1(result_add_subt[16]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[16]), .Y(n2027) );
AO22XLTS U3404 ( .A0(n4576), .A1(result_add_subt[13]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[13]), .Y(n2036) );
AO22XLTS U3405 ( .A0(n4582), .A1(n2248), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(n1768) );
AO22XLTS U3406 ( .A0(n4582), .A1(result_add_subt[27]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(n1774) );
AO22XLTS U3407 ( .A0(n4582), .A1(result_add_subt[26]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(n1777) );
AO22XLTS U3408 ( .A0(n4438), .A1(busy), .B0(n4436), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2147) );
AO22XLTS U3409 ( .A0(n4668), .A1(n4625), .B0(n4664), .B1(
FPMULT_Add_result[4]), .Y(n1620) );
AO22XLTS U3410 ( .A0(n4668), .A1(n4658), .B0(n4664), .B1(
FPMULT_Add_result[20]), .Y(n1604) );
AO22XLTS U3411 ( .A0(n4668), .A1(n4654), .B0(n4664), .B1(
FPMULT_Add_result[18]), .Y(n1606) );
AO22XLTS U3412 ( .A0(n4668), .A1(n4650), .B0(n4664), .B1(
FPMULT_Add_result[16]), .Y(n1608) );
AO22XLTS U3413 ( .A0(n4668), .A1(n4646), .B0(n4645), .B1(
FPMULT_Add_result[14]), .Y(n1610) );
AO22XLTS U3414 ( .A0(n4668), .A1(n4641), .B0(n4645), .B1(
FPMULT_Add_result[12]), .Y(n1612) );
AO22XLTS U3415 ( .A0(n4668), .A1(n4637), .B0(n4664), .B1(
FPMULT_Add_result[10]), .Y(n1614) );
AO22XLTS U3416 ( .A0(n4668), .A1(n4633), .B0(n4664), .B1(
FPMULT_Add_result[8]), .Y(n1616) );
AO22XLTS U3417 ( .A0(n4668), .A1(n4629), .B0(n4664), .B1(
FPMULT_Add_result[6]), .Y(n1618) );
AO22XLTS U3418 ( .A0(n4589), .A1(Data_2[20]), .B0(n4591), .B1(
FPMULT_Op_MY[20]), .Y(n1647) );
AO22XLTS U3419 ( .A0(n4576), .A1(result_add_subt[15]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[15]), .Y(n2030) );
AO22XLTS U3420 ( .A0(n4571), .A1(result_add_subt[21]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[21]), .Y(n2012) );
AO22XLTS U3421 ( .A0(n4571), .A1(result_add_subt[18]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[18]), .Y(n2021) );
AO22XLTS U3422 ( .A0(n4571), .A1(result_add_subt[20]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[20]), .Y(n2015) );
AO22XLTS U3423 ( .A0(n4571), .A1(result_add_subt[19]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[19]), .Y(n2018) );
AO22XLTS U3424 ( .A0(n4576), .A1(result_add_subt[6]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[6]), .Y(n2057) );
AO22XLTS U3425 ( .A0(n4576), .A1(result_add_subt[17]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[17]), .Y(n2024) );
AO22XLTS U3426 ( .A0(n4576), .A1(result_add_subt[2]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[2]), .Y(n2069) );
AO22XLTS U3427 ( .A0(n4576), .A1(result_add_subt[12]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[12]), .Y(n2039) );
AO22XLTS U3428 ( .A0(n4582), .A1(n2249), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(n1780) );
AO22XLTS U3429 ( .A0(n4576), .A1(result_add_subt[10]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[10]), .Y(n2045) );
AO22XLTS U3430 ( .A0(n4592), .A1(Data_2[11]), .B0(n2326), .B1(
FPMULT_Op_MY[11]), .Y(n1638) );
AO22XLTS U3431 ( .A0(n4592), .A1(Data_2[14]), .B0(n4591), .B1(
FPMULT_Op_MY[14]), .Y(n1641) );
AO22XLTS U3432 ( .A0(n4582), .A1(result_add_subt[24]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(n1783) );
AO22XLTS U3433 ( .A0(n4589), .A1(Data_2[21]), .B0(n4591), .B1(n2242), .Y(
n1648) );
AO22XLTS U3434 ( .A0(n4592), .A1(Data_2[15]), .B0(n4591), .B1(n2243), .Y(
n1642) );
AO22XLTS U3435 ( .A0(n4592), .A1(Data_2[17]), .B0(n4591), .B1(n2244), .Y(
n1644) );
AO22XLTS U3436 ( .A0(n4589), .A1(Data_2[19]), .B0(n4591), .B1(n2245), .Y(
n1646) );
AO22XLTS U3437 ( .A0(n4592), .A1(Data_2[9]), .B0(n2326), .B1(FPMULT_Op_MY[9]), .Y(n1636) );
AO22XLTS U3438 ( .A0(n4592), .A1(Data_2[12]), .B0(n2326), .B1(
FPMULT_Op_MY[12]), .Y(n1639) );
AO22XLTS U3439 ( .A0(n4589), .A1(Data_1[5]), .B0(n4590), .B1(FPMULT_Op_MX[5]), .Y(n1664) );
AO22XLTS U3440 ( .A0(n4589), .A1(Data_1[2]), .B0(n4591), .B1(FPMULT_Op_MX[2]), .Y(n1661) );
AO22XLTS U3441 ( .A0(n4588), .A1(Data_1[15]), .B0(n2326), .B1(
FPMULT_Op_MX[15]), .Y(n1674) );
AO22XLTS U3442 ( .A0(n4588), .A1(Data_1[17]), .B0(n2326), .B1(
FPMULT_Op_MX[17]), .Y(n1676) );
AO22XLTS U3443 ( .A0(n4588), .A1(Data_1[19]), .B0(n2326), .B1(
FPMULT_Op_MX[19]), .Y(n1678) );
AO22XLTS U3444 ( .A0(n4588), .A1(Data_1[21]), .B0(n4590), .B1(
FPMULT_Op_MX[21]), .Y(n1680) );
AO22XLTS U3445 ( .A0(n4588), .A1(Data_1[16]), .B0(n2326), .B1(
FPMULT_Op_MX[16]), .Y(n1675) );
AO22XLTS U3446 ( .A0(n4588), .A1(Data_1[18]), .B0(n2326), .B1(
FPMULT_Op_MX[18]), .Y(n1677) );
AO22XLTS U3447 ( .A0(n4592), .A1(Data_2[3]), .B0(n4590), .B1(FPMULT_Op_MY[3]), .Y(n1630) );
AO22XLTS U3448 ( .A0(n4592), .A1(Data_2[8]), .B0(n2326), .B1(FPMULT_Op_MY[8]), .Y(n1635) );
AO22XLTS U3449 ( .A0(n4576), .A1(result_add_subt[4]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[4]), .Y(n2063) );
AO22XLTS U3450 ( .A0(n4576), .A1(result_add_subt[3]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[3]), .Y(n2066) );
AO22XLTS U3451 ( .A0(n4571), .A1(result_add_subt[0]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[0]), .Y(n2075) );
AO22XLTS U3452 ( .A0(n4576), .A1(result_add_subt[1]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[1]), .Y(n2072) );
AO22XLTS U3453 ( .A0(n4576), .A1(result_add_subt[5]), .B0(n4476), .B1(
FPSENCOS_d_ff_Yn[5]), .Y(n2060) );
AO22XLTS U3454 ( .A0(n4582), .A1(result_add_subt[22]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(n2008) );
AO22XLTS U3455 ( .A0(n4475), .A1(result_add_subt[15]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(n2029) );
AO22XLTS U3456 ( .A0(n4582), .A1(result_add_subt[18]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(n2020) );
AO22XLTS U3457 ( .A0(n4582), .A1(result_add_subt[21]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(n2011) );
AO22XLTS U3458 ( .A0(n4475), .A1(result_add_subt[4]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(n2062) );
AO22XLTS U3459 ( .A0(n4475), .A1(result_add_subt[8]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(n2050) );
AO22XLTS U3460 ( .A0(n4475), .A1(result_add_subt[11]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(n2041) );
AO22XLTS U3461 ( .A0(n4475), .A1(result_add_subt[9]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(n2047) );
AO22XLTS U3462 ( .A0(n4582), .A1(result_add_subt[28]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(n1771) );
AO22XLTS U3463 ( .A0(n4582), .A1(result_add_subt[19]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(n2017) );
AO22XLTS U3464 ( .A0(n4582), .A1(result_add_subt[20]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(n2014) );
AO22XLTS U3465 ( .A0(n4475), .A1(result_add_subt[17]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(n2023) );
AO22XLTS U3466 ( .A0(n4475), .A1(result_add_subt[6]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(n2056) );
AO22XLTS U3467 ( .A0(n4475), .A1(result_add_subt[13]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(n2035) );
AO22XLTS U3468 ( .A0(n4475), .A1(result_add_subt[16]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(n2026) );
AO22XLTS U3469 ( .A0(n4475), .A1(result_add_subt[14]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(n2032) );
AO22XLTS U3470 ( .A0(n4475), .A1(result_add_subt[10]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(n2044) );
AO22XLTS U3471 ( .A0(n4475), .A1(result_add_subt[12]), .B0(n4569), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(n2038) );
AO22XLTS U3472 ( .A0(n4475), .A1(result_add_subt[3]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(n2065) );
AO22XLTS U3473 ( .A0(n4475), .A1(result_add_subt[2]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(n2068) );
AO22XLTS U3474 ( .A0(n4475), .A1(result_add_subt[7]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(n2053) );
AO22XLTS U3475 ( .A0(n4475), .A1(result_add_subt[1]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(n2071) );
AO22XLTS U3476 ( .A0(n4475), .A1(result_add_subt[5]), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(n2059) );
XOR2X1TS U3477 ( .A(n3721), .B(FPMULT_Sgf_operation_EVEN1_Q_left[23]), .Y(
n3722) );
AOI222X1TS U3478 ( .A0(n3958), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DmP_EXP_EWSW[23]), .B1(n4038), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3907), .Y(n3959) );
AO22XLTS U3479 ( .A0(n2197), .A1(n4957), .B0(n5513), .B1(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n1353) );
AO22XLTS U3480 ( .A0(n4588), .A1(Data_1[13]), .B0(n4590), .B1(
FPMULT_Op_MX[13]), .Y(n1672) );
AO22XLTS U3481 ( .A0(n4592), .A1(Data_2[0]), .B0(n4591), .B1(FPMULT_Op_MY[0]), .Y(n1627) );
AO22XLTS U3482 ( .A0(n4592), .A1(Data_2[7]), .B0(n2326), .B1(FPMULT_Op_MY[7]), .Y(n1634) );
AO22XLTS U3483 ( .A0(n4851), .A1(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B0(n5514),
.B1(result_add_subt[30]), .Y(n1468) );
AO22XLTS U3484 ( .A0(n4592), .A1(Data_2[1]), .B0(n2326), .B1(FPMULT_Op_MY[1]), .Y(n1628) );
AO22XLTS U3485 ( .A0(n4592), .A1(Data_2[10]), .B0(n4591), .B1(
FPMULT_Op_MY[10]), .Y(n1637) );
AO22XLTS U3486 ( .A0(n4589), .A1(Data_2[22]), .B0(n4591), .B1(
FPMULT_Op_MY[22]), .Y(n1649) );
AO22XLTS U3487 ( .A0(n4592), .A1(Data_2[6]), .B0(n2326), .B1(FPMULT_Op_MY[6]), .Y(n1633) );
AO22XLTS U3488 ( .A0(n4589), .A1(Data_1[1]), .B0(n4591), .B1(FPMULT_Op_MX[1]), .Y(n1660) );
AO22XLTS U3489 ( .A0(n4589), .A1(Data_2[18]), .B0(n4591), .B1(
FPMULT_Op_MY[18]), .Y(n1645) );
AO22XLTS U3490 ( .A0(n4592), .A1(Data_2[16]), .B0(n4591), .B1(
FPMULT_Op_MY[16]), .Y(n1643) );
AO22XLTS U3491 ( .A0(n4588), .A1(Data_1[22]), .B0(n4590), .B1(
FPMULT_Op_MX[22]), .Y(n1681) );
AO22XLTS U3492 ( .A0(n4588), .A1(Data_1[20]), .B0(n2326), .B1(
FPMULT_Op_MX[20]), .Y(n1679) );
AO22XLTS U3493 ( .A0(n4588), .A1(Data_1[14]), .B0(n2326), .B1(
FPMULT_Op_MX[14]), .Y(n1673) );
AO22XLTS U3494 ( .A0(n4782), .A1(FPMULT_P_Sgf[26]), .B0(n4796), .B1(n4736),
.Y(n1579) );
AO22XLTS U3495 ( .A0(n4481), .A1(FPSENCOS_d_ff3_sh_x_out[0]), .B0(n2214),
.B1(FPSENCOS_d_ff2_X[0]), .Y(n2006) );
AO22XLTS U3496 ( .A0(n4809), .A1(FPMULT_P_Sgf[35]), .B0(n4781), .B1(n4700),
.Y(n1588) );
AO22XLTS U3497 ( .A0(n4782), .A1(FPMULT_P_Sgf[34]), .B0(n4781), .B1(n4704),
.Y(n1587) );
AO22XLTS U3498 ( .A0(n4809), .A1(FPMULT_P_Sgf[33]), .B0(n4781), .B1(n4708),
.Y(n1586) );
AO22XLTS U3499 ( .A0(n4782), .A1(FPMULT_P_Sgf[32]), .B0(n4781), .B1(n4712),
.Y(n1585) );
AO22XLTS U3500 ( .A0(n4782), .A1(FPMULT_P_Sgf[31]), .B0(n4781), .B1(n4716),
.Y(n1584) );
AO22XLTS U3501 ( .A0(n4782), .A1(FPMULT_P_Sgf[30]), .B0(n4796), .B1(n4720),
.Y(n1583) );
AO22XLTS U3502 ( .A0(n4782), .A1(FPMULT_P_Sgf[29]), .B0(n4796), .B1(n4724),
.Y(n1582) );
AO22XLTS U3503 ( .A0(n4782), .A1(FPMULT_P_Sgf[28]), .B0(n4796), .B1(n4728),
.Y(n1581) );
AO22XLTS U3504 ( .A0(n4782), .A1(FPMULT_P_Sgf[27]), .B0(n4796), .B1(n4732),
.Y(n1580) );
AO22XLTS U3505 ( .A0(n4782), .A1(FPMULT_P_Sgf[25]), .B0(n4796), .B1(n4740),
.Y(n1578) );
AO22XLTS U3506 ( .A0(n4782), .A1(FPMULT_P_Sgf[24]), .B0(n4796), .B1(n4744),
.Y(n1577) );
NOR2XLTS U3507 ( .A(n4461), .B(n4451), .Y(n4459) );
AO22XLTS U3508 ( .A0(n4481), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n4500),
.B1(FPSENCOS_d_ff2_X[1]), .Y(n2004) );
AO22XLTS U3509 ( .A0(n4481), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n2214),
.B1(FPSENCOS_d_ff2_X[2]), .Y(n2002) );
AO22XLTS U3510 ( .A0(n4481), .A1(FPSENCOS_d_ff3_sh_x_out[4]), .B0(n2214),
.B1(FPSENCOS_d_ff2_X[4]), .Y(n1998) );
AO22XLTS U3511 ( .A0(n4503), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n4491),
.B1(FPSENCOS_d_ff2_X[12]), .Y(n1982) );
AO22XLTS U3512 ( .A0(n4503), .A1(FPSENCOS_d_ff3_sh_x_out[8]), .B0(n4500),
.B1(FPSENCOS_d_ff2_X[8]), .Y(n1990) );
AO22XLTS U3513 ( .A0(n4503), .A1(FPSENCOS_d_ff3_sh_x_out[9]), .B0(n4500),
.B1(FPSENCOS_d_ff2_X[9]), .Y(n1988) );
AO22XLTS U3514 ( .A0(n4503), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n4500),
.B1(FPSENCOS_d_ff2_X[21]), .Y(n1964) );
AO22XLTS U3515 ( .A0(n4503), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n2214),
.B1(FPSENCOS_d_ff2_X[6]), .Y(n1994) );
AO22XLTS U3516 ( .A0(n4503), .A1(FPSENCOS_d_ff3_sh_x_out[10]), .B0(n2214),
.B1(FPSENCOS_d_ff2_X[10]), .Y(n1986) );
AO22XLTS U3517 ( .A0(n4436), .A1(n5093), .B0(n4438), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2146) );
AOI211XLTS U3518 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(n4584), .B0(n4616), .C0(n4811), .Y(n4587) );
AO22XLTS U3519 ( .A0(n5129), .A1(n4828), .B0(n5369), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1477) );
AO22XLTS U3520 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4810), .B0(
mult_result[5]), .B1(n4812), .Y(n1510) );
AO22XLTS U3521 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4810), .B0(
mult_result[3]), .B1(n4812), .Y(n1512) );
AO22XLTS U3522 ( .A0(n2255), .A1(n4810), .B0(mult_result[1]), .B1(n4812),
.Y(n1514) );
AO22XLTS U3523 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n4810), .B0(
mult_result[0]), .B1(n4812), .Y(n1515) );
AO22XLTS U3524 ( .A0(n4782), .A1(FPMULT_P_Sgf[23]), .B0(n4796), .B1(n4748),
.Y(n1576) );
AO22X1TS U3525 ( .A0(n4782), .A1(FPMULT_P_Sgf[46]), .B0(n4671), .B1(n3726),
.Y(n1599) );
AO22XLTS U3526 ( .A0(n4592), .A1(Data_2[5]), .B0(n2326), .B1(n2254), .Y(
n1632) );
AO22XLTS U3527 ( .A0(n4589), .A1(Data_1[0]), .B0(n4591), .B1(n2253), .Y(
n1659) );
AO22XLTS U3528 ( .A0(n4588), .A1(Data_1[12]), .B0(n4590), .B1(n2278), .Y(
n1671) );
NAND4XLTS U3529 ( .A(n4604), .B(n4603), .C(n4602), .D(n4601), .Y(n4610) );
CLKXOR2X2TS U3530 ( .A(n2297), .B(n2835), .Y(n2219) );
AOI22X1TS U3531 ( .A0(n4592), .A1(Data_2[13]), .B0(n4591), .B1(
FPMULT_Op_MY[13]), .Y(n2220) );
OR2X1TS U3532 ( .A(n3368), .B(n3367), .Y(n2221) );
AOI22X1TS U3533 ( .A0(n4588), .A1(Data_1[11]), .B0(n4590), .B1(
FPMULT_Op_MX[11]), .Y(n2224) );
OA21XLTS U3534 ( .A0(n5194), .A1(n4184), .B0(n4120), .Y(n2228) );
OA21XLTS U3535 ( .A0(n5220), .A1(n4083), .B0(n4169), .Y(n2229) );
OAI221X1TS U3536 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n5346), .B0(n5355), .B1(
FPADDSUB_intDY_EWSW[7]), .C0(n4933), .Y(n4943) );
CLKINVX6TS U3537 ( .A(n2213), .Y(n4494) );
OAI21X2TS U3538 ( .A0(n5187), .A1(n4083), .B0(n4122), .Y(n4560) );
NOR2X2TS U3539 ( .A(n5213), .B(n2311), .Y(n3821) );
NAND2X2TS U3540 ( .A(n2214), .B(FPSENCOS_cont_iter_out[1]), .Y(n4460) );
AOI222X4TS U3541 ( .A0(n4976), .A1(n5205), .B0(n4976), .B1(n5251), .C0(n5205), .C1(n5251), .Y(n4983) );
AOI222X4TS U3542 ( .A0(n5024), .A1(n5209), .B0(n5024), .B1(n5258), .C0(n5209), .C1(n5258), .Y(n5031) );
AOI222X4TS U3543 ( .A0(n5036), .A1(n5210), .B0(n5036), .B1(n5262), .C0(n5210), .C1(n5262), .Y(n5043) );
AOI222X4TS U3544 ( .A0(n5048), .A1(n5212), .B0(n5048), .B1(n5268), .C0(n5212), .C1(n5268), .Y(n5055) );
AOI222X4TS U3545 ( .A0(n5062), .A1(n5215), .B0(n5062), .B1(n5271), .C0(n5215), .C1(n5271), .Y(n5069) );
AOI32X2TS U3546 ( .A0(n3905), .A1(n3906), .A2(n3904), .B0(n3903), .B1(n3906),
.Y(n4950) );
INVX2TS U3547 ( .A(n2228), .Y(n2233) );
OAI21X2TS U3548 ( .A0(n5196), .A1(n4184), .B0(n4133), .Y(n4179) );
OAI21X2TS U3549 ( .A0(n5191), .A1(n4184), .B0(n4129), .Y(n4162) );
OAI21X2TS U3550 ( .A0(n5193), .A1(n4184), .B0(n4128), .Y(n4156) );
NOR2X1TS U3551 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n2705) );
BUFX6TS U3552 ( .A(n3909), .Y(n4505) );
OAI32X1TS U3553 ( .A0(n5515), .A1(n5094), .A2(n4838), .B0(n4956), .B1(n5098),
.Y(n4839) );
OAI31X1TS U3554 ( .A0(n4444), .A1(FPSENCOS_cont_var_out[1]), .A2(n5363),
.B0(n4364), .Y(n2138) );
NOR2X2TS U3555 ( .A(ready_add_subt), .B(n4409), .Y(n4444) );
AOI222X1TS U3556 ( .A0(n4018), .A1(cordic_result[15]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[15]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[15]), .Y(n4009) );
AOI222X1TS U3557 ( .A0(n4022), .A1(cordic_result[21]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[21]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[21]), .Y(n3992) );
AOI222X1TS U3558 ( .A0(n4018), .A1(cordic_result[18]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[18]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[18]), .Y(n4007) );
AOI222X1TS U3559 ( .A0(n4022), .A1(cordic_result[20]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[20]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[20]), .Y(n3991) );
AOI222X1TS U3560 ( .A0(n4022), .A1(cordic_result[19]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[19]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[19]), .Y(n3993) );
AOI222X1TS U3561 ( .A0(n4018), .A1(cordic_result[17]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[17]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[17]), .Y(n4010) );
AOI222X1TS U3562 ( .A0(n4022), .A1(cordic_result[12]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[12]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[12]), .Y(n4011) );
AOI222X1TS U3563 ( .A0(n4022), .A1(cordic_result[22]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[22]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[22]), .Y(n3990) );
OAI21X2TS U3564 ( .A0(n5326), .A1(n4184), .B0(n4151), .Y(n4188) );
OAI21X2TS U3565 ( .A0(n5315), .A1(n4184), .B0(n4173), .Y(n4200) );
OAI21X2TS U3566 ( .A0(n5181), .A1(n4184), .B0(n4183), .Y(n4202) );
INVX2TS U3567 ( .A(n2229), .Y(n2234) );
CLKINVX6TS U3568 ( .A(n5513), .Y(n5093) );
INVX3TS U3569 ( .A(n4121), .Y(n4215) );
BUFX4TS U3570 ( .A(n2326), .Y(n4590) );
OR4X4TS U3571 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .C(FPMULT_FS_Module_state_reg[1]), .D(
n5274), .Y(n2326) );
CLKINVX6TS U3572 ( .A(n5163), .Y(n5170) );
CLKINVX6TS U3573 ( .A(n3744), .Y(n4481) );
CLKINVX6TS U3574 ( .A(n3744), .Y(n4574) );
BUFX6TS U3575 ( .A(n3758), .Y(n3808) );
OAI21X1TS U3576 ( .A0(n5239), .A1(n4899), .B0(n4868), .Y(n4856) );
OAI21X1TS U3577 ( .A0(n5350), .A1(n4899), .B0(n4868), .Y(n4861) );
OAI21X1TS U3578 ( .A0(n5351), .A1(n4899), .B0(n4868), .Y(n4869) );
CLKINVX6TS U3579 ( .A(n2213), .Y(n4490) );
NOR4X2TS U3580 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .C(n5211), .D(n5182), .Y(n4429) );
NAND3X2TS U3581 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n3754), .C(n5190),
.Y(n4585) );
NOR2X2TS U3582 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n4499), .Y(n4502) );
NOR2X2TS U3583 ( .A(n4068), .B(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n4100) );
INVX1TS U3584 ( .A(n4850), .Y(n3840) );
NAND3X2TS U3585 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n4087),
.C(n5322), .Y(n4419) );
NOR2X2TS U3586 ( .A(n5366), .B(n4662), .Y(n4665) );
AOI222X1TS U3587 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4488), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n3915)
);
AOI21X2TS U3588 ( .A0(n4902), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n4895),
.Y(n5174) );
BUFX4TS U3589 ( .A(n5496), .Y(n5485) );
NOR2X2TS U3590 ( .A(n5264), .B(n4628), .Y(n4630) );
NOR2X2TS U3591 ( .A(n5267), .B(n4632), .Y(n4634) );
NOR2X2TS U3592 ( .A(n5270), .B(n4636), .Y(n4638) );
NOR2X2TS U3593 ( .A(n5273), .B(n4640), .Y(n4642) );
NOR2X2TS U3594 ( .A(n5279), .B(n4644), .Y(n4647) );
NOR2X2TS U3595 ( .A(n5319), .B(n4649), .Y(n4651) );
NOR2X2TS U3596 ( .A(n5331), .B(n4653), .Y(n4655) );
NOR2X2TS U3597 ( .A(n5358), .B(n4657), .Y(n4660) );
BUFX4TS U3598 ( .A(n5486), .Y(n5488) );
NOR4X1TS U3599 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n5211), .C(n5274),
.D(n5190), .Y(n4583) );
AOI21X2TS U3600 ( .A0(n4902), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n4895),
.Y(n5140) );
OAI22X1TS U3601 ( .A0(n2430), .A1(n2348), .B0(n2271), .B1(n2347), .Y(n2355)
);
OAI22X1TS U3602 ( .A0(n2624), .A1(n2602), .B0(n2272), .B1(n2242), .Y(n2616)
);
AOI21X2TS U3603 ( .A0(n4902), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n4895),
.Y(n5112) );
AOI21X2TS U3604 ( .A0(n4902), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n4895),
.Y(n5109) );
BUFX4TS U3605 ( .A(n4841), .Y(n4902) );
INVX2TS U3606 ( .A(n2230), .Y(n2236) );
BUFX4TS U3607 ( .A(n5493), .Y(n5477) );
XNOR2X1TS U3608 ( .A(n2752), .B(n2749), .Y(n2750) );
BUFX4TS U3609 ( .A(n5493), .Y(n5483) );
BUFX4TS U3610 ( .A(n5493), .Y(n5478) );
BUFX4TS U3611 ( .A(n5486), .Y(n5491) );
NOR4X1TS U3612 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[15]), .C(
FPMULT_Op_MX[16]), .D(FPMULT_Op_MX[17]), .Y(n4603) );
NOR4X1TS U3613 ( .A(FPMULT_Op_MY[14]), .B(n2243), .C(FPMULT_Op_MY[16]), .D(
n2244), .Y(n4595) );
BUFX4TS U3614 ( .A(n2237), .Y(n5479) );
BUFX4TS U3615 ( .A(n5493), .Y(n5481) );
BUFX4TS U3616 ( .A(n2207), .Y(n5492) );
BUFX4TS U3617 ( .A(n4473), .Y(n4572) );
NOR4X1TS U3618 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[19]), .C(
FPMULT_Op_MX[20]), .D(FPMULT_Op_MX[21]), .Y(n4604) );
BUFX4TS U3619 ( .A(n5502), .Y(n5480) );
BUFX6TS U3620 ( .A(n5123), .Y(n5125) );
BUFX4TS U3621 ( .A(n5128), .Y(n5123) );
BUFX3TS U3622 ( .A(n2217), .Y(n5502) );
AOI32X2TS U3623 ( .A0(n4430), .A1(n4220), .A2(begin_operation), .B0(n5508),
.B1(n4220), .Y(n4584) );
BUFX4TS U3624 ( .A(n5502), .Y(n5489) );
BUFX4TS U3625 ( .A(n5496), .Y(n5500) );
BUFX4TS U3626 ( .A(n5499), .Y(n5490) );
BUFX3TS U3627 ( .A(n3749), .Y(n2238) );
BUFX4TS U3628 ( .A(n2212), .Y(n5453) );
BUFX4TS U3629 ( .A(n2212), .Y(n5476) );
BUFX4TS U3630 ( .A(n2212), .Y(n5474) );
BUFX4TS U3631 ( .A(n2212), .Y(n5473) );
BUFX4TS U3632 ( .A(n5451), .Y(n5510) );
BUFX4TS U3633 ( .A(n3738), .Y(n5456) );
BUFX4TS U3634 ( .A(n3738), .Y(n5463) );
BUFX4TS U3635 ( .A(n3738), .Y(n5462) );
OAI221X2TS U3636 ( .A0(n2203), .A1(n2222), .B0(n4083), .B1(n5354), .C0(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4211) );
BUFX4TS U3637 ( .A(n5451), .Y(n5508) );
OAI22X1TS U3638 ( .A0(n2577), .A1(n2518), .B0(n2276), .B1(n2534), .Y(n2530)
);
OAI22X1TS U3639 ( .A0(n2430), .A1(n2429), .B0(n2271), .B1(n2415), .Y(n2416)
);
OAI22X1TS U3640 ( .A0(n2430), .A1(n2415), .B0(n2271), .B1(n2445), .Y(n2453)
);
OAI22X1TS U3641 ( .A0(n2577), .A1(n2447), .B0(n2277), .B1(n2446), .Y(n2455)
);
OAI22X1TS U3642 ( .A0(n2577), .A1(n2446), .B0(n2276), .B1(n2408), .Y(n2440)
);
CLKINVX3TS U3643 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2239) );
OAI32X1TS U3644 ( .A0(n4442), .A1(n4439), .A2(n5525), .B0(n5314), .B1(n4442),
.Y(n2142) );
NOR3X4TS U3645 ( .A(n4439), .B(n5314), .C(n5525), .Y(n4442) );
BUFX4TS U3646 ( .A(n2212), .Y(n5459) );
BUFX4TS U3647 ( .A(n2212), .Y(n5470) );
NOR3XLTS U3648 ( .A(FPMULT_Op_MY[23]), .B(FPMULT_Op_MY[0]), .C(
FPMULT_Op_MY[1]), .Y(n4599) );
NOR2X4TS U3649 ( .A(operation[1]), .B(operation[2]), .Y(n4431) );
NOR3XLTS U3650 ( .A(FPMULT_Op_MX[24]), .B(n2253), .C(FPMULT_Op_MX[1]), .Y(
n4607) );
NOR4X1TS U3651 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[28]), .Y(n4601) );
NOR4X1TS U3652 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n3747) );
BUFX6TS U3653 ( .A(n2305), .Y(n4954) );
OAI21X2TS U3654 ( .A0(n5192), .A1(n4083), .B0(n4166), .Y(n4206) );
AOI221X1TS U3655 ( .A0(n5176), .A1(n4905), .B0(n5142), .B1(n4906), .C0(n4907), .Y(n5158) );
NOR2X4TS U3656 ( .A(n2198), .B(n5329), .Y(n4907) );
BUFX4TS U3657 ( .A(n3937), .Y(n3935) );
OAI21X2TS U3658 ( .A0(n5202), .A1(n4184), .B0(n4132), .Y(n4161) );
BUFX4TS U3659 ( .A(n4149), .Y(n4160) );
CLKINVX3TS U3660 ( .A(n4116), .Y(n4213) );
BUFX4TS U3661 ( .A(n4845), .Y(n5133) );
INVX2TS U3662 ( .A(FPMULT_Op_MY[21]), .Y(n2241) );
CLKINVX6TS U3663 ( .A(n2241), .Y(n2242) );
BUFX4TS U3664 ( .A(n4844), .Y(n5134) );
CLKINVX6TS U3665 ( .A(n4509), .Y(n4329) );
INVX3TS U3666 ( .A(n4664), .Y(n4659) );
INVX3TS U3667 ( .A(n4664), .Y(n4668) );
BUFX6TS U3668 ( .A(n3757), .Y(n3803) );
NOR3XLTS U3669 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n4812), .Y(n4813) );
BUFX4TS U3670 ( .A(n4816), .Y(n4812) );
BUFX6TS U3671 ( .A(n4344), .Y(n4427) );
BUFX4TS U3672 ( .A(n5163), .Y(n5131) );
INVX4TS U3673 ( .A(n4048), .Y(n4835) );
BUFX6TS U3674 ( .A(n3958), .Y(n4048) );
INVX3TS U3675 ( .A(n5515), .Y(n5098) );
INVX3TS U3676 ( .A(n4474), .Y(n4571) );
INVX3TS U3677 ( .A(n4569), .Y(n4582) );
BUFX6TS U3678 ( .A(n4852), .Y(n5121) );
BUFX6TS U3679 ( .A(n4119), .Y(n4561) );
CLKINVX6TS U3680 ( .A(n2296), .Y(n4810) );
CLKINVX6TS U3681 ( .A(n4473), .Y(n4573) );
BUFX6TS U3682 ( .A(n4050), .Y(n4038) );
BUFX6TS U3683 ( .A(n4285), .Y(n4526) );
NOR4X1TS U3684 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[11]), .C(
FPMULT_Op_MY[12]), .D(FPMULT_Op_MY[13]), .Y(n4598) );
INVX2TS U3685 ( .A(n2226), .Y(n2248) );
INVX2TS U3686 ( .A(n2225), .Y(n2249) );
INVX2TS U3687 ( .A(n2227), .Y(n2250) );
INVX2TS U3688 ( .A(n2231), .Y(n2251) );
INVX2TS U3689 ( .A(n2232), .Y(n2252) );
NOR4X1TS U3690 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[7]), .C(
FPMULT_Op_MY[8]), .D(FPMULT_Op_MY[9]), .Y(n4597) );
INVX4TS U3691 ( .A(FPMULT_Op_MY[12]), .Y(n3566) );
NAND2X1TS U3692 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n2767) );
NOR4X1TS U3693 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[3]), .C(
FPMULT_Op_MY[4]), .D(n2254), .Y(n4600) );
INVX2TS U3694 ( .A(n2218), .Y(n2254) );
INVX2TS U3695 ( .A(n2223), .Y(n2255) );
XNOR2X2TS U3696 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MX[17]), .Y(n2830) );
NOR4X1TS U3697 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[3]), .C(
FPMULT_Op_MX[4]), .D(FPMULT_Op_MX[5]), .Y(n4608) );
NAND2X1TS U3698 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[2]), .Y(n2756) );
XNOR2X2TS U3699 ( .A(FPMULT_Op_MX[7]), .B(FPMULT_Op_MX[19]), .Y(n2709) );
NOR4X1TS U3700 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[7]), .C(
FPMULT_Op_MX[8]), .D(FPMULT_Op_MX[9]), .Y(n4605) );
XNOR2X4TS U3701 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[21]), .Y(n2715) );
OAI21X1TS U3702 ( .A0(FPMULT_Op_MX[10]), .A1(FPMULT_Op_MX[22]), .B0(
FPMULT_Op_MX[9]), .Y(n2660) );
OAI221X1TS U3703 ( .A0(n5353), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n5337),
.B1(FPADDSUB_intDY_EWSW[27]), .C0(n4924), .Y(n4927) );
OAI221X1TS U3704 ( .A0(n5335), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n5339),
.B1(FPADDSUB_intDY_EWSW[9]), .C0(n4922), .Y(n4929) );
AOI222X1TS U3705 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n5234), .B0(n3859), .B1(
n3858), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n5348), .Y(n3861) );
AOI221X1TS U3706 ( .A0(n5234), .A1(FPADDSUB_intDY_EWSW[4]), .B0(
FPADDSUB_intDY_EWSW[5]), .B1(n5348), .C0(n4936), .Y(n4939) );
NOR4X1TS U3707 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[11]), .C(n2278), .D(
FPMULT_Op_MX[13]), .Y(n4606) );
XNOR2X2TS U3708 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[15]), .Y(n2822) );
NOR2X1TS U3709 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[15]), .Y(n2821) );
XOR2XLTS U3710 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[21]), .Y(n2667) );
XOR2XLTS U3711 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[15]), .Y(n2826) );
NAND2X1TS U3712 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[6]), .Y(n2693) );
XOR2XLTS U3713 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[17]), .Y(n2689) );
OAI221X1TS U3714 ( .A0(n5183), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n5347),
.B1(FPADDSUB_intDY_EWSW[23]), .C0(n4930), .Y(n4945) );
OAI221X1TS U3715 ( .A0(n5237), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n5341),
.B1(FPADDSUB_intDY_EWSW[17]), .C0(n4914), .Y(n4921) );
INVX2TS U3716 ( .A(n2256), .Y(n2257) );
INVX2TS U3717 ( .A(n2258), .Y(n2259) );
XOR2XLTS U3718 ( .A(FPSENCOS_d_ff_Yn[31]), .B(n3985), .Y(n3986) );
OAI33X4TS U3719 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .A2(n5360), .B0(n5201), .B1(
n5242), .B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n3985) );
AOI222X4TS U3720 ( .A0(n4022), .A1(cordic_result[23]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[23]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[23]), .Y(n3995) );
AOI222X4TS U3721 ( .A0(n4022), .A1(cordic_result[24]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[24]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[24]), .Y(n3989) );
AOI222X4TS U3722 ( .A0(n4022), .A1(cordic_result[25]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[25]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[25]), .Y(n3994) );
AOI222X4TS U3723 ( .A0(n4022), .A1(cordic_result[26]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[26]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[26]), .Y(n3998) );
AOI222X4TS U3724 ( .A0(n4022), .A1(cordic_result[30]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[30]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[30]), .Y(n4002) );
NOR2X1TS U3725 ( .A(n4461), .B(n4451), .Y(n2260) );
NOR2X2TS U3726 ( .A(FPSENCOS_cont_iter_out[3]), .B(n2311), .Y(n4461) );
CLKINVX3TS U3727 ( .A(n2312), .Y(n4953) );
NOR4X1TS U3728 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5447) );
NOR4X1TS U3729 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n5450) );
NOR4X1TS U3730 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n5449) );
NOR4X1TS U3731 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5448) );
NOR4X1TS U3732 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n3723),
.Y(n5446) );
AOI211X1TS U3733 ( .A0(n4065), .A1(n4064), .B0(n4109), .C0(n4063), .Y(n4067)
);
AOI211X1TS U3734 ( .A0(n4099), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n4109),
.C0(n4098), .Y(n4103) );
NOR2X2TS U3735 ( .A(n5326), .B(n4062), .Y(n4109) );
NOR2X2TS U3736 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_477_n1), .Y(n4497) );
AOI21X2TS U3737 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n4902), .B0(n4856),
.Y(n5104) );
BUFX4TS U3738 ( .A(n5451), .Y(n5507) );
BUFX6TS U3739 ( .A(n5518), .Y(n5451) );
NOR2X2TS U3740 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n4074), .Y(n4099) );
AOI211X2TS U3741 ( .A0(n4902), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n4901),
.C0(n4900), .Y(n5138) );
NOR2X2TS U3742 ( .A(n5330), .B(n4868), .Y(n4901) );
NOR2X2TS U3743 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n5217),
.Y(n4408) );
INVX2TS U3744 ( .A(n2700), .Y(n2702) );
NAND3X2TS U3745 ( .A(n4082), .B(n5220), .C(n5194), .Y(n4079) );
NOR2X2TS U3746 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n4054), .Y(n4104) );
BUFX4TS U3747 ( .A(n5503), .Y(n5487) );
OAI211X2TS U3748 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n5277), .B0(n3878),
.C0(n3864), .Y(n3880) );
AOI211XLTS U3749 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5336), .B0(n3892),
.C0(n3893), .Y(n3884) );
OAI211X2TS U3750 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n5283), .B0(n3898),
.C0(n3883), .Y(n3892) );
NOR4X1TS U3751 ( .A(FPMULT_Op_MY[18]), .B(n2245), .C(FPMULT_Op_MY[20]), .D(
n2242), .Y(n4596) );
INVX6TS U3752 ( .A(n4671), .Y(n4782) );
OAI211X2TS U3753 ( .A0(n5452), .A1(n4463), .B0(n3827), .C0(n4456), .Y(n4449)
);
OAI21X2TS U3754 ( .A0(n3821), .A1(n5525), .B0(n4456), .Y(n4451) );
AOI211X1TS U3755 ( .A0(n5314), .A1(n5525), .B0(n4506), .C0(n4456), .Y(n3817)
);
NAND2X2TS U3756 ( .A(FPSENCOS_cont_iter_out[3]), .B(n4441), .Y(n4456) );
NOR4X1TS U3757 ( .A(FPMULT_Op_MY[26]), .B(FPMULT_Op_MY[25]), .C(
FPMULT_Op_MY[30]), .D(FPMULT_Op_MY[24]), .Y(n4594) );
AOI222X4TS U3758 ( .A0(n4022), .A1(cordic_result[27]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[27]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[27]), .Y(n4001) );
AOI222X4TS U3759 ( .A0(n4022), .A1(cordic_result[29]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[29]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[29]), .Y(n3999) );
AOI222X1TS U3760 ( .A0(n4026), .A1(cordic_result[4]), .B0(n3984), .B1(
FPSENCOS_d_ff_Yn[4]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[4]), .Y(n4003)
);
AOI222X4TS U3761 ( .A0(n4022), .A1(cordic_result[28]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[28]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[28]), .Y(n4000) );
AOI222X4TS U3762 ( .A0(n4026), .A1(cordic_result[3]), .B0(n3984), .B1(
FPSENCOS_d_ff_Yn[3]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[3]), .Y(n3997)
);
AOI222X4TS U3763 ( .A0(n4026), .A1(cordic_result[1]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[1]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[1]), .Y(n4005)
);
AOI222X1TS U3764 ( .A0(n4026), .A1(cordic_result[5]), .B0(n3984), .B1(
FPSENCOS_d_ff_Yn[5]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[5]), .Y(n4006)
);
AOI222X4TS U3765 ( .A0(n5204), .A1(n5250), .B0(n5204), .B1(n4965), .C0(n5250), .C1(n4965), .Y(n4971) );
NAND2X1TS U3766 ( .A(FPADDSUB_DmP_mant_SFG_SWR[2]), .B(FPADDSUB_DMP_SFG[0]),
.Y(n4965) );
AOI222X4TS U3767 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(
FPADDSUB_DMP_SFG[6]), .B0(FPADDSUB_DmP_mant_SFG_SWR[8]), .B1(n4995),
.C0(FPADDSUB_DMP_SFG[6]), .C1(n4995), .Y(n5000) );
AOI222X4TS U3768 ( .A0(n4988), .A1(n5206), .B0(n4988), .B1(n5252), .C0(n5206), .C1(n5252), .Y(n4995) );
AOI222X1TS U3769 ( .A0(n4494), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4487), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n3942) );
NAND2X4TS U3770 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4184) );
BUFX6TS U3771 ( .A(n5369), .Y(n5128) );
XNOR2X2TS U3772 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[1]), .Y(n2835) );
CLKINVX6TS U3773 ( .A(n5176), .Y(n5142) );
BUFX6TS U3774 ( .A(FPADDSUB_left_right_SHT2), .Y(n5176) );
BUFX6TS U3775 ( .A(n2305), .Y(n4437) );
AOI222X4TS U3776 ( .A0(n4022), .A1(cordic_result[13]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[13]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[13]), .Y(n4014) );
AOI222X4TS U3777 ( .A0(n4018), .A1(cordic_result[16]), .B0(n4004), .B1(
FPSENCOS_d_ff_Yn[16]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[16]), .Y(n4012) );
AOI222X4TS U3778 ( .A0(n4022), .A1(cordic_result[14]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[14]), .C0(n4013), .C1(FPSENCOS_d_ff_Xn[14]), .Y(n4008) );
AOI222X4TS U3779 ( .A0(n4026), .A1(cordic_result[7]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[7]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[7]), .Y(n4027)
);
AOI222X4TS U3780 ( .A0(n4022), .A1(cordic_result[11]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[11]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[11]), .Y(n4023) );
AOI222X1TS U3781 ( .A0(n4026), .A1(cordic_result[6]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[6]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[6]), .Y(n4021)
);
AOI222X1TS U3782 ( .A0(n4026), .A1(cordic_result[2]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[2]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[2]), .Y(n4020)
);
AOI222X4TS U3783 ( .A0(n4018), .A1(cordic_result[10]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[10]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[10]), .Y(n4019) );
AOI222X4TS U3784 ( .A0(n4026), .A1(cordic_result[0]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[0]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[0]), .Y(n4017)
);
AOI222X4TS U3785 ( .A0(n4026), .A1(cordic_result[9]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[9]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[9]), .Y(n4016)
);
AOI222X4TS U3786 ( .A0(n4026), .A1(cordic_result[8]), .B0(n4025), .B1(
FPSENCOS_d_ff_Yn[8]), .C0(n4024), .C1(FPSENCOS_d_ff_Xn[8]), .Y(n4015)
);
BUFX4TS U3787 ( .A(n3984), .Y(n4004) );
INVX4TS U3788 ( .A(n3958), .Y(n3974) );
CLKAND2X4TS U3789 ( .A(n3753), .B(n5190), .Y(FPMULT_FSM_exp_operation_A_S)
);
NOR3X2TS U3790 ( .A(n5182), .B(FPMULT_FS_Module_state_reg[0]), .C(
FPMULT_FS_Module_state_reg[3]), .Y(n3753) );
BUFX4TS U3791 ( .A(n4489), .Y(n4492) );
OAI32X1TS U3792 ( .A0(n4421), .A1(FPMULT_exp_oper_result[8]), .A2(
FPMULT_Exp_module_Overflow_flag_A), .B0(overflow_flag_addsubt), .B1(
operation[2]), .Y(n4330) );
INVX4TS U3793 ( .A(n4042), .Y(n4834) );
NAND4X2TS U3794 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n3820),
.C(n5224), .D(n5322), .Y(n4420) );
AOI32X1TS U3795 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n4556), .A2(
n4437), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n4149), .Y(n4084)
);
INVX4TS U3796 ( .A(n4467), .Y(n4468) );
BUFX6TS U3797 ( .A(n4123), .Y(n4563) );
BUFX6TS U3798 ( .A(n4359), .Y(n4430) );
CLKINVX6TS U3799 ( .A(n2214), .Y(n4503) );
BUFX6TS U3800 ( .A(n3760), .Y(n3807) );
NOR3X4TS U3801 ( .A(n3750), .B(FPMULT_FS_Module_state_reg[3]), .C(
FPMULT_FS_Module_state_reg[2]), .Y(n4616) );
CLKINVX6TS U3802 ( .A(n2213), .Y(n4477) );
CLKINVX6TS U3803 ( .A(n5514), .Y(n5122) );
AOI222X4TS U3804 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n5254), .B0(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(n4960), .C0(n5254), .C1(n4960), .Y(
n4966) );
AOI21X2TS U3805 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4902), .B0(n4869),
.Y(n4877) );
AOI21X2TS U3806 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n4902), .B0(n4861),
.Y(n5117) );
NOR2X1TS U3807 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .Y(n2678) );
NAND2X1TS U3808 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .Y(n2677) );
NOR4X1TS U3809 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[29]), .C(
FPMULT_Op_MY[28]), .D(FPMULT_Op_MY[27]), .Y(n4593) );
NOR2X2TS U3810 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n2761) );
NAND2X1TS U3811 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[2]), .Y(n2762) );
NOR2X2TS U3812 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n2723) );
XNOR2X1TS U3813 ( .A(n2665), .B(n2664), .Y(n2872) );
CLKINVX6TS U3814 ( .A(n2872), .Y(n2261) );
OAI22X1TS U3815 ( .A0(n2863), .A1(n2870), .B0(n2862), .B1(n2261), .Y(
DP_OP_453J210_122_681_n450) );
OAI22X1TS U3816 ( .A0(n2864), .A1(n2870), .B0(n2863), .B1(n2261), .Y(
DP_OP_453J210_122_681_n451) );
OAI22X1TS U3817 ( .A0(n2865), .A1(n2261), .B0(n2866), .B1(n2870), .Y(n2738)
);
OAI22X1TS U3818 ( .A0(n2868), .A1(n2870), .B0(n2866), .B1(n2261), .Y(
DP_OP_453J210_122_681_n454) );
OAI22X1TS U3819 ( .A0(n2871), .A1(n2261), .B0(n2784), .B1(n2870), .Y(n2776)
);
OAI22X1TS U3820 ( .A0(n2869), .A1(n2870), .B0(n2868), .B1(n2261), .Y(
DP_OP_453J210_122_681_n455) );
OAI22X1TS U3821 ( .A0(n2795), .A1(n2261), .B0(n2870), .B1(n2794), .Y(n2802)
);
NOR2BX1TS U3822 ( .AN(n3568), .B(n2261), .Y(DP_OP_453J210_122_681_n462) );
NAND2X4TS U3823 ( .A(n2261), .B(n2669), .Y(n2870) );
AOI32X1TS U3824 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n4556), .A2(
n4437), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n4160), .Y(n4071)
);
NAND2X2TS U3825 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n4868) );
AOI222X4TS U3826 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(
FPADDSUB_DMP_SFG[10]), .B0(FPADDSUB_DmP_mant_SFG_SWR[12]), .B1(n5019),
.C0(FPADDSUB_DMP_SFG[10]), .C1(n5019), .Y(n5024) );
AOI222X4TS U3827 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(
FPADDSUB_DMP_SFG[8]), .B0(FPADDSUB_DmP_mant_SFG_SWR[10]), .B1(n5007),
.C0(FPADDSUB_DMP_SFG[8]), .C1(n5007), .Y(n5012) );
AOI222X4TS U3828 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(
FPADDSUB_DMP_SFG[20]), .B0(FPADDSUB_DmP_mant_SFG_SWR[22]), .B1(n5081),
.C0(FPADDSUB_DMP_SFG[20]), .C1(n5081), .Y(n5086) );
AOI222X4TS U3829 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(
FPADDSUB_DMP_SFG[22]), .B0(FPADDSUB_DmP_mant_SFG_SWR[24]), .B1(n5096),
.C0(FPADDSUB_DMP_SFG[22]), .C1(n5096), .Y(n4956) );
XNOR2X1TS U3830 ( .A(n2688), .B(n2687), .Y(n2901) );
CLKINVX6TS U3831 ( .A(n2901), .Y(n2262) );
OAI22X1TS U3832 ( .A0(n2890), .A1(n2898), .B0(n2889), .B1(n2262), .Y(
DP_OP_453J210_122_681_n480) );
OAI22X1TS U3833 ( .A0(n2891), .A1(n2898), .B0(n2890), .B1(n2262), .Y(
DP_OP_453J210_122_681_n481) );
OAI22X1TS U3834 ( .A0(n2893), .A1(n2898), .B0(n2891), .B1(n2262), .Y(
DP_OP_453J210_122_681_n482) );
OAI22X1TS U3835 ( .A0(n2893), .A1(n2262), .B0(n2892), .B1(n2898), .Y(
DP_OP_453J210_122_681_n483) );
OAI22X1TS U3836 ( .A0(n2894), .A1(n2898), .B0(n2892), .B1(n2262), .Y(n2785)
);
OAI22X1TS U3837 ( .A0(n2897), .A1(n2898), .B0(n2895), .B1(n2262), .Y(
DP_OP_453J210_122_681_n486) );
OAI22X1TS U3838 ( .A0(n2897), .A1(n2262), .B0(n2900), .B1(n2898), .Y(
DP_OP_453J210_122_681_n487) );
OAI22X1TS U3839 ( .A0(n2900), .A1(n2262), .B0(n2899), .B1(n2898), .Y(
DP_OP_453J210_122_681_n488) );
OAI22X1TS U3840 ( .A0(n2810), .A1(n2262), .B0(n2898), .B1(n2809), .Y(n2819)
);
NOR2BX1TS U3841 ( .AN(n3568), .B(n2262), .Y(DP_OP_453J210_122_681_n492) );
NAND2X4TS U3842 ( .A(n2262), .B(n2692), .Y(n2898) );
XNOR2X1TS U3843 ( .A(n2712), .B(n2711), .Y(n2887) );
CLKINVX6TS U3844 ( .A(n2887), .Y(n2263) );
OAI22X1TS U3845 ( .A0(n2874), .A1(n2885), .B0(n2263), .B1(n2873), .Y(
DP_OP_453J210_122_681_n464) );
OAI22X1TS U3846 ( .A0(n2875), .A1(n2885), .B0(n2874), .B1(n2263), .Y(n2718)
);
OAI22X1TS U3847 ( .A0(n2876), .A1(n2885), .B0(n2875), .B1(n2263), .Y(
DP_OP_453J210_122_681_n466) );
OAI22X1TS U3848 ( .A0(n2878), .A1(n2885), .B0(n2876), .B1(n2263), .Y(
DP_OP_453J210_122_681_n467) );
OAI22X1TS U3849 ( .A0(n2878), .A1(n2263), .B0(n2877), .B1(n2885), .Y(
DP_OP_453J210_122_681_n468) );
OAI22X1TS U3850 ( .A0(n2879), .A1(n2885), .B0(n2877), .B1(n2263), .Y(n2758)
);
OAI22X1TS U3851 ( .A0(n2880), .A1(n2885), .B0(n2879), .B1(n2263), .Y(
DP_OP_453J210_122_681_n470) );
OAI22X1TS U3852 ( .A0(n2881), .A1(n2885), .B0(n2880), .B1(n2263), .Y(
DP_OP_453J210_122_681_n471) );
OAI22X1TS U3853 ( .A0(n2881), .A1(n2263), .B0(n2882), .B1(n2885), .Y(
DP_OP_453J210_122_681_n472) );
OAI22X1TS U3854 ( .A0(n2882), .A1(n2263), .B0(n2884), .B1(n2885), .Y(
DP_OP_453J210_122_681_n473) );
OAI22X1TS U3855 ( .A0(n2884), .A1(n2263), .B0(n2888), .B1(n2885), .Y(
DP_OP_453J210_122_681_n474) );
OAI22X1TS U3856 ( .A0(n2888), .A1(n2263), .B0(n2886), .B1(n2885), .Y(
DP_OP_453J210_122_681_n475) );
OAI22X1TS U3857 ( .A0(n2886), .A1(n2263), .B0(n2885), .B1(n2805), .Y(n2814)
);
NOR2BX1TS U3858 ( .AN(n3568), .B(n2263), .Y(n2818) );
NAND2X4TS U3859 ( .A(n2263), .B(n2717), .Y(n2885) );
CLKXOR2X4TS U3860 ( .A(n2825), .B(n2824), .Y(n2264) );
OAI22X1TS U3861 ( .A0(n2904), .A1(n2915), .B0(n2903), .B1(n2264), .Y(
DP_OP_453J210_122_681_n495) );
OAI22X1TS U3862 ( .A0(n2905), .A1(n2915), .B0(n2904), .B1(n2264), .Y(
DP_OP_453J210_122_681_n496) );
OAI22X1TS U3863 ( .A0(n2903), .A1(n2915), .B0(n2264), .B1(n2902), .Y(
DP_OP_453J210_122_681_n494) );
OAI22X1TS U3864 ( .A0(n2906), .A1(n2915), .B0(n2905), .B1(n2264), .Y(
DP_OP_453J210_122_681_n497) );
OAI22X1TS U3865 ( .A0(n2906), .A1(n2264), .B0(n2907), .B1(n2915), .Y(
DP_OP_453J210_122_681_n498) );
OAI22X1TS U3866 ( .A0(n2909), .A1(n2915), .B0(n2908), .B1(n2264), .Y(
DP_OP_453J210_122_681_n500) );
OAI22X1TS U3867 ( .A0(n2908), .A1(n2915), .B0(n2907), .B1(n2264), .Y(
DP_OP_453J210_122_681_n499) );
OAI22X1TS U3868 ( .A0(n2910), .A1(n2915), .B0(n2909), .B1(n2264), .Y(
DP_OP_453J210_122_681_n501) );
OAI22X1TS U3869 ( .A0(n2910), .A1(n2264), .B0(n2912), .B1(n2915), .Y(
DP_OP_453J210_122_681_n502) );
OAI22X1TS U3870 ( .A0(n2912), .A1(n2264), .B0(n2914), .B1(n2915), .Y(
DP_OP_453J210_122_681_n503) );
OAI22X1TS U3871 ( .A0(n2914), .A1(n2264), .B0(n2918), .B1(n2915), .Y(
DP_OP_453J210_122_681_n504) );
OAI22X1TS U3872 ( .A0(n2918), .A1(n2264), .B0(n2916), .B1(n2915), .Y(
DP_OP_453J210_122_681_n505) );
OAI22X1TS U3873 ( .A0(n2916), .A1(n2264), .B0(n2915), .B1(n2833), .Y(n2840)
);
NAND2X4TS U3874 ( .A(n2917), .B(n2829), .Y(n2915) );
NAND2X1TS U3875 ( .A(n2823), .B(n2822), .Y(n2824) );
CLKXOR2X4TS U3876 ( .A(n2751), .B(n2750), .Y(n2265) );
OAI22X1TS U3877 ( .A0(n2921), .A1(n2932), .B0(n2920), .B1(n2265), .Y(
DP_OP_453J210_122_681_n511) );
OAI22X1TS U3878 ( .A0(n2920), .A1(n2932), .B0(n2919), .B1(n2265), .Y(
DP_OP_453J210_122_681_n510) );
OAI22X1TS U3879 ( .A0(n2922), .A1(n2932), .B0(n2921), .B1(n2265), .Y(
DP_OP_453J210_122_681_n512) );
OAI22X1TS U3880 ( .A0(n2922), .A1(n2265), .B0(n2923), .B1(n2932), .Y(
DP_OP_453J210_122_681_n513) );
OAI22X1TS U3881 ( .A0(n2924), .A1(n2932), .B0(n2923), .B1(n2265), .Y(
DP_OP_453J210_122_681_n514) );
OAI22X1TS U3882 ( .A0(n2926), .A1(n2932), .B0(n2924), .B1(n2265), .Y(
DP_OP_453J210_122_681_n515) );
OAI22X1TS U3883 ( .A0(n2929), .A1(n2932), .B0(n2926), .B1(n2265), .Y(
DP_OP_453J210_122_681_n516) );
OAI22X1TS U3884 ( .A0(n2929), .A1(n2265), .B0(n2932), .B1(n2930), .Y(
DP_OP_453J210_122_681_n517) );
OAI22X1TS U3885 ( .A0(n2932), .A1(n2931), .B0(n2265), .B1(n2930), .Y(
DP_OP_453J210_122_681_n518) );
OAI22X1TS U3886 ( .A0(n2932), .A1(n2850), .B0(n2933), .B1(n2849), .Y(n2851)
);
NOR2BX1TS U3887 ( .AN(n3568), .B(n2933), .Y(DP_OP_453J210_122_681_n522) );
NAND2X4TS U3888 ( .A(n2933), .B(n2755), .Y(n2932) );
NAND2X1TS U3889 ( .A(n2297), .B(n2835), .Y(n2751) );
XNOR2X4TS U3890 ( .A(n2674), .B(FPMULT_Op_MX[11]), .Y(n2266) );
NAND2X2TS U3891 ( .A(n2660), .B(n2659), .Y(n2674) );
BUFX4TS U3892 ( .A(n2927), .Y(n2267) );
XNOR2X1TS U3893 ( .A(n2823), .B(n2822), .Y(n2927) );
XOR2X1TS U3894 ( .A(n2831), .B(n2830), .Y(n2913) );
NOR2XLTS U3895 ( .A(FPMULT_Op_MX[13]), .B(FPMULT_Op_MX[1]), .Y(n2749) );
XOR2X1TS U3896 ( .A(n2710), .B(n2709), .Y(n2896) );
XNOR2X1TS U3897 ( .A(n2269), .B(n3568), .Y(n2809) );
XNOR2X4TS U3898 ( .A(n2707), .B(n2715), .Y(n2270) );
INVX2TS U3899 ( .A(n2883), .Y(n2873) );
XNOR2X1TS U3900 ( .A(n2883), .B(n3568), .Y(n2805) );
OAI221X1TS U3901 ( .A0(n5336), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5344),
.B1(FPADDSUB_intDY_EWSW[15]), .C0(n4915), .Y(n4920) );
XOR2X1TS U3902 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[13]), .Y(n2535) );
XNOR2X4TS U3903 ( .A(FPMULT_Op_MY[20]), .B(n2245), .Y(n2272) );
XNOR2X4TS U3904 ( .A(FPMULT_Op_MY[20]), .B(n2245), .Y(n2273) );
XNOR2X4TS U3905 ( .A(n2244), .B(FPMULT_Op_MY[18]), .Y(n2274) );
XNOR2X4TS U3906 ( .A(n2244), .B(FPMULT_Op_MY[18]), .Y(n2275) );
XNOR2X4TS U3907 ( .A(FPMULT_Op_MY[16]), .B(n2243), .Y(n2276) );
XNOR2X4TS U3908 ( .A(FPMULT_Op_MY[16]), .B(n2243), .Y(n2277) );
XNOR2X2TS U3909 ( .A(FPMULT_Op_MY[16]), .B(n2243), .Y(n2576) );
XOR2XLTS U3910 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[19]), .Y(n2713) );
BUFX6TS U3911 ( .A(FPMULT_Op_MX[12]), .Y(n2278) );
NOR2BX1TS U3912 ( .AN(n2278), .B(n2271), .Y(n2425) );
NOR2BX1TS U3913 ( .AN(n2278), .B(n2247), .Y(n2389) );
NOR2BX1TS U3914 ( .AN(n2278), .B(n2272), .Y(n2482) );
NOR2BX1TS U3915 ( .AN(n2278), .B(n2603), .Y(n2460) );
OR2X1TS U3916 ( .A(DP_OP_453J210_122_681_n222), .B(n3597), .Y(n2280) );
AND3X1TS U3917 ( .A(n2333), .B(n2332), .C(n2331), .Y(n2281) );
OR2X1TS U3918 ( .A(DP_OP_453J210_122_681_n401), .B(n3572), .Y(n2285) );
OR2X1TS U3919 ( .A(n3333), .B(n3332), .Y(n2290) );
OR2X1TS U3920 ( .A(n3350), .B(n3349), .Y(n2291) );
OR2X1TS U3921 ( .A(n3106), .B(n3105), .Y(n2292) );
OR2X1TS U3922 ( .A(n3104), .B(n3103), .Y(n2293) );
OR2X1TS U3923 ( .A(n3303), .B(n3302), .Y(n2294) );
OR2X1TS U3924 ( .A(n3558), .B(n3557), .Y(n2295) );
OR4X2TS U3925 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .C(underflow_flag_mult), .D(n4812), .Y(
n2296) );
OR2X1TS U3926 ( .A(n2425), .B(n2424), .Y(n2298) );
OR2X1TS U3927 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n2306) );
OR2X1TS U3928 ( .A(n2648), .B(n2647), .Y(n2308) );
OR2X1TS U3929 ( .A(n2642), .B(n2641), .Y(n2309) );
OR2X1TS U3930 ( .A(n3257), .B(n3256), .Y(n2310) );
INVX2TS U3931 ( .A(FPSENCOS_cont_iter_out[2]), .Y(n4441) );
OR2X1TS U3932 ( .A(DP_OP_453J210_122_681_n378), .B(
DP_OP_453J210_122_681_n383), .Y(n2313) );
OR2X2TS U3933 ( .A(DP_OP_453J210_122_681_n362), .B(
DP_OP_453J210_122_681_n369), .Y(n2315) );
OR2X2TS U3934 ( .A(DP_OP_453J210_122_681_n321), .B(
DP_OP_453J210_122_681_n331), .Y(n2316) );
OR2X2TS U3935 ( .A(DP_OP_453J210_122_681_n332), .B(
DP_OP_453J210_122_681_n342), .Y(n2317) );
OR2X1TS U3936 ( .A(n2618), .B(n2617), .Y(n2318) );
OR2X1TS U3937 ( .A(n2595), .B(n2594), .Y(n2320) );
OR2X2TS U3938 ( .A(n2467), .B(n2466), .Y(n2322) );
OR2X2TS U3939 ( .A(DP_OP_453J210_122_681_n268), .B(
DP_OP_453J210_122_681_n276), .Y(n2323) );
OR2X2TS U3940 ( .A(DP_OP_453J210_122_681_n251), .B(
DP_OP_453J210_122_681_n258), .Y(n2324) );
INVX2TS U3941 ( .A(n2721), .Y(n2697) );
INVX2TS U3942 ( .A(n2676), .Y(n2679) );
INVX2TS U3943 ( .A(n2733), .Y(n2735) );
NAND2X1TS U3944 ( .A(n2677), .B(n3348), .Y(n2658) );
INVX2TS U3945 ( .A(n2911), .Y(n2766) );
NOR2BX1TS U3946 ( .AN(n3568), .B(n2859), .Y(n2801) );
AO21XLTS U3947 ( .A0(n2444), .A1(n3566), .B0(DP_OP_453J210_122_681_n2030),
.Y(n2513) );
OAI22X1TS U3948 ( .A0(n2430), .A1(n2347), .B0(n2271), .B1(n2243), .Y(n2519)
);
OAI22X1TS U3949 ( .A0(n2860), .A1(n2675), .B0(n2857), .B1(n2859), .Y(
DP_OP_453J210_122_681_n441) );
OAI22X1TS U3950 ( .A0(n2871), .A1(n2870), .B0(n2869), .B1(n2261), .Y(
DP_OP_453J210_122_681_n456) );
OAI22X1TS U3951 ( .A0(n2895), .A1(n2898), .B0(n2894), .B1(n2262), .Y(
DP_OP_453J210_122_681_n485) );
OAI21XLTS U3952 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n5281), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n3857) );
OAI22X1TS U3953 ( .A0(n2645), .A1(FPMULT_Op_MX[15]), .B0(n2247), .B1(
FPMULT_Op_MX[16]), .Y(n2537) );
OAI22X1TS U3954 ( .A0(n2430), .A1(n2243), .B0(n2271), .B1(n2300), .Y(n2526)
);
INVX2TS U3955 ( .A(n2867), .Y(n2861) );
OAI22X1TS U3956 ( .A0(n2865), .A1(n2870), .B0(n2864), .B1(n2261), .Y(
DP_OP_453J210_122_681_n452) );
OAI21XLTS U3957 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n5284), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n3865) );
OAI22X1TS U3958 ( .A0(n2948), .A1(n3562), .B0(n2947), .B1(n3567), .Y(
DP_OP_453J210_122_681_n531) );
OAI22X1TS U3959 ( .A0(n2947), .A1(n3562), .B0(n2946), .B1(n3567), .Y(
DP_OP_453J210_122_681_n530) );
OAI22X1TS U3960 ( .A0(n2942), .A1(n3562), .B0(n2940), .B1(n3567), .Y(
DP_OP_453J210_122_681_n527) );
OAI22X1TS U3961 ( .A0(n2624), .A1(n2589), .B0(n2273), .B1(n2602), .Y(n2607)
);
NOR2XLTS U3962 ( .A(n3595), .B(n2675), .Y(n3596) );
INVX2TS U3963 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .Y(
DP_OP_453J210_122_681_n774) );
NAND2X4TS U3964 ( .A(FPMULT_Op_MY[13]), .B(n3566), .Y(n2444) );
NAND2X1TS U3965 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[0]), .Y(n2788) );
INVX2TS U3966 ( .A(n4718), .Y(DP_OP_453J210_122_681_n783) );
INVX2TS U3967 ( .A(n3362), .Y(n2561) );
INVX2TS U3968 ( .A(n3631), .Y(n3589) );
AND3X1TS U3969 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .C(FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(
n3835) );
INVX3TS U3970 ( .A(FPMULT_Op_MY[3]), .Y(n3189) );
OAI21X1TS U3971 ( .A0(n3409), .A1(n3415), .B0(n3410), .Y(n3403) );
INVX2TS U3972 ( .A(n3357), .Y(n3359) );
INVX2TS U3973 ( .A(n3601), .Y(n3603) );
NAND2X1TS U3974 ( .A(n2492), .B(n2491), .Y(n3520) );
NAND2X1TS U3975 ( .A(n2425), .B(n2424), .Y(n3553) );
NOR2X1TS U3976 ( .A(n3565), .B(n3189), .Y(n3071) );
NOR2X2TS U3977 ( .A(n3253), .B(n3252), .Y(n3414) );
NAND2X1TS U3978 ( .A(n3402), .B(n2310), .Y(n3396) );
INVX2TS U3979 ( .A(n3373), .Y(n3375) );
NAND2X1TS U3980 ( .A(n3359), .B(n3358), .Y(n3360) );
NAND2X1TS U3981 ( .A(n3609), .B(n3608), .Y(n3610) );
AOI21X1TS U3982 ( .A0(n3536), .A1(n2321), .B0(n3530), .Y(n3533) );
OAI21XLTS U3983 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4373), .B0(n4372), .Y(
n4374) );
INVX2TS U3984 ( .A(n3463), .Y(n3465) );
NAND2X1TS U3985 ( .A(n3132), .B(n3131), .Y(n3439) );
NAND2X1TS U3986 ( .A(n3416), .B(n3415), .Y(n3417) );
NAND2X1TS U3987 ( .A(n3391), .B(n3390), .Y(n3392) );
AOI21X1TS U3988 ( .A0(n3692), .A1(n2314), .B0(n3686), .Y(n3689) );
XOR2X1TS U3989 ( .A(n3621), .B(n3620), .Y(n4707) );
INVX2TS U3990 ( .A(DP_OP_453J210_122_681_n788), .Y(n4738) );
OAI21XLTS U3991 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n5250), .B0(n4964),
.Y(n4968) );
OAI21XLTS U3992 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n5275), .B0(n5076),
.Y(n5077) );
OAI21XLTS U3993 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n5251), .B0(n4978),
.Y(n4979) );
NOR2XLTS U3994 ( .A(n4877), .B(n4848), .Y(n4875) );
AOI31XLTS U3995 ( .A0(n4948), .A1(n4947), .A2(n4946), .B0(n4950), .Y(n4951)
);
INVX2TS U3996 ( .A(n3462), .Y(n3472) );
NAND2X1TS U3997 ( .A(n3429), .B(n3428), .Y(n3430) );
XNOR2X1TS U3998 ( .A(n3695), .B(n3694), .Y(n4767) );
XNOR2X1TS U3999 ( .A(n3479), .B(n3478), .Y(n3725) );
NOR2X1TS U4000 ( .A(n3565), .B(n3564), .Y(n4807) );
OAI21XLTS U4001 ( .A0(n4665), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
n4667), .Y(n4666) );
OAI211XLTS U4002 ( .A0(n4614), .A1(n4586), .B0(n2205), .C0(n4222), .Y(n1695)
);
OAI21XLTS U4003 ( .A0(n4408), .A1(n4093), .B0(n4422), .Y(n2151) );
OAI211XLTS U4004 ( .A0(n4329), .A1(n5416), .B0(n4268), .C0(n4267), .Y(n1931)
);
OAI211XLTS U4005 ( .A0(n3806), .A1(n5400), .B0(n3790), .C0(n3789), .Y(n1525)
);
OAI211XLTS U4006 ( .A0(n4329), .A1(n5419), .B0(n4235), .C0(n4234), .Y(n1928)
);
OAI211XLTS U4007 ( .A0(n4329), .A1(n5444), .B0(n4310), .C0(n4309), .Y(n1820)
);
OAI21XLTS U4008 ( .A0(n5231), .A1(n4835), .B0(n3920), .Y(n1231) );
OAI21XLTS U4009 ( .A0(n5342), .A1(n3974), .B0(n3908), .Y(n1247) );
OAI21XLTS U4010 ( .A0(n5238), .A1(n2208), .B0(n4046), .Y(n1409) );
OAI211XLTS U4011 ( .A0(n3806), .A1(n5403), .B0(n3770), .C0(n3769), .Y(n1522)
);
OAI211XLTS U4012 ( .A0(n4155), .A1(n4213), .B0(n4142), .C0(n4141), .Y(n1797)
);
OAI211XLTS U4013 ( .A0(n2202), .A1(n2282), .B0(n4242), .C0(n4241), .Y(n1912)
);
OAI211XLTS U4014 ( .A0(n4187), .A1(n4213), .B0(n4181), .C0(n4180), .Y(n1801)
);
OAI21XLTS U4015 ( .A0(n4463), .A1(n4460), .B0(n3826), .Y(n2131) );
OAI21XLTS U4016 ( .A0(n4331), .A1(n5308), .B0(n4339), .Y(op_result[5]) );
OAI21XLTS U4017 ( .A0(n4363), .A1(n5291), .B0(n4351), .Y(op_result[20]) );
NOR4X1TS U4018 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n2333) );
NOR4X1TS U4019 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n2332) );
NOR4X1TS U4020 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n2330) );
NOR3XLTS U4021 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n2329) );
NOR4X1TS U4022 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n2328) );
NOR4X1TS U4023 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n2327) );
AND4X1TS U4024 ( .A(n2330), .B(n2329), .C(n2328), .D(n2327), .Y(n2331) );
BUFX4TS U4025 ( .A(n2326), .Y(n4591) );
INVX4TS U4026 ( .A(n4591), .Y(n4588) );
INVX4TS U4027 ( .A(n4590), .Y(n4592) );
XNOR2X1TS U4028 ( .A(n2243), .B(FPMULT_Op_MX[22]), .Y(n2347) );
OAI22X1TS U4029 ( .A0(n2278), .A1(n2645), .B0(n2247), .B1(FPMULT_Op_MX[13]),
.Y(n2361) );
XNOR2X2TS U4030 ( .A(n2244), .B(FPMULT_Op_MY[18]), .Y(n2603) );
XNOR2X1TS U4031 ( .A(n2244), .B(FPMULT_Op_MX[18]), .Y(n2363) );
XNOR2X1TS U4032 ( .A(n2245), .B(FPMULT_Op_MX[15]), .Y(n2379) );
XNOR2X1TS U4033 ( .A(n2242), .B(FPMULT_Op_MX[13]), .Y(n2390) );
XNOR2X1TS U4034 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[20]), .Y(n2394) );
XNOR2X1TS U4035 ( .A(n2244), .B(FPMULT_Op_MX[16]), .Y(n2396) );
NAND2BXLTS U4036 ( .AN(n2278), .B(n2242), .Y(n2380) );
XNOR2X1TS U4037 ( .A(n2278), .B(n2242), .Y(n2391) );
NAND2BXLTS U4038 ( .AN(n2278), .B(n2244), .Y(n2412) );
XNOR2X1TS U4039 ( .A(n2278), .B(n2244), .Y(n2413) );
XNOR2X1TS U4040 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MX[16]), .Y(n2414) );
INVX2TS U4041 ( .A(n3553), .Y(n2426) );
XNOR2X1TS U4042 ( .A(n2278), .B(n2243), .Y(n2431) );
NAND2BXLTS U4043 ( .AN(n2278), .B(n2245), .Y(n2450) );
XNOR2X1TS U4044 ( .A(n2278), .B(n2245), .Y(n2452) );
NAND2X1TS U4045 ( .A(n2465), .B(n2464), .Y(n3534) );
OAI22X1TS U4046 ( .A0(n2645), .A1(FPMULT_Op_MX[16]), .B0(n2247), .B1(
FPMULT_Op_MX[17]), .Y(n2552) );
OAI22X1TS U4047 ( .A0(n2577), .A1(n2244), .B0(n2276), .B1(n2288), .Y(n2571)
);
OAI22X1TS U4048 ( .A0(n2645), .A1(FPMULT_Op_MX[18]), .B0(n2247), .B1(
FPMULT_Op_MX[19]), .Y(n2590) );
XNOR2X1TS U4049 ( .A(n2242), .B(FPMULT_Op_MX[21]), .Y(n2589) );
XNOR2X1TS U4050 ( .A(n2242), .B(FPMULT_Op_MX[22]), .Y(n2602) );
OAI22X1TS U4051 ( .A0(n2604), .A1(n2245), .B0(n2275), .B1(n2304), .Y(n2600)
);
OAI22X1TS U4052 ( .A0(n2645), .A1(FPMULT_Op_MX[20]), .B0(n2247), .B1(
FPMULT_Op_MX[21]), .Y(n2613) );
OAI22X1TS U4053 ( .A0(n2624), .A1(n2242), .B0(n2272), .B1(n2303), .Y(n2625)
);
NOR2X1TS U4054 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[1]), .Y(n2779) );
NAND2X1TS U4055 ( .A(FPMULT_Op_MY[13]), .B(FPMULT_Op_MY[1]), .Y(n2780) );
NAND2X1TS U4056 ( .A(n2243), .B(FPMULT_Op_MY[3]), .Y(n2745) );
NOR2X2TS U4057 ( .A(n2245), .B(FPMULT_Op_MY[7]), .Y(n2700) );
NAND2X1TS U4058 ( .A(n2244), .B(n2254), .Y(n2772) );
NAND2X1TS U4059 ( .A(n2245), .B(FPMULT_Op_MY[7]), .Y(n2701) );
OAI21X4TS U4060 ( .A0(n2695), .A1(n2657), .B0(n2656), .Y(n2732) );
NOR2X2TS U4061 ( .A(n2242), .B(FPMULT_Op_MY[9]), .Y(n2733) );
INVX2TS U4062 ( .A(n2678), .Y(n2671) );
NAND2X1TS U4063 ( .A(n2242), .B(FPMULT_Op_MY[9]), .Y(n2734) );
NAND2X1TS U4064 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[22]), .Y(n2659) );
XNOR2X4TS U4065 ( .A(n2674), .B(FPMULT_Op_MX[11]), .Y(n2867) );
NAND2X1TS U4066 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[8]), .Y(n2662) );
OAI22X1TS U4067 ( .A0(n2862), .A1(n2870), .B0(n2261), .B1(n2861), .Y(n2683)
);
NAND2X1TS U4068 ( .A(n2671), .B(n2677), .Y(n2672) );
CLKXOR2X2TS U4069 ( .A(n2673), .B(n2672), .Y(n2937) );
CLKXOR2X2TS U4070 ( .A(n2681), .B(FPMULT_Op_MY[11]), .Y(n2935) );
INVX2TS U4071 ( .A(n2935), .Y(n2853) );
NAND2X1TS U4072 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[4]), .Y(n2685) );
INVX2TS U4073 ( .A(n2269), .Y(n2808) );
NAND2X1TS U4074 ( .A(n2731), .B(n2729), .Y(n2706) );
XNOR2X4TS U4075 ( .A(n2732), .B(n2706), .Y(n2941) );
XNOR2X4TS U4076 ( .A(n2707), .B(n2715), .Y(n2883) );
INVX2TS U4077 ( .A(n2723), .Y(n2725) );
NAND2X1TS U4078 ( .A(n2725), .B(n2724), .Y(n2726) );
CLKXOR2X2TS U4079 ( .A(n2727), .B(n2726), .Y(n2945) );
CLKXOR2X2TS U4080 ( .A(n2737), .B(n2736), .Y(n2939) );
INVX2TS U4081 ( .A(n2741), .Y(n2769) );
NAND2X1TS U4082 ( .A(n2769), .B(n2767), .Y(n2742) );
XNOR2X4TS U4083 ( .A(n2770), .B(n2742), .Y(n2928) );
INVX2TS U4084 ( .A(n2743), .Y(n2765) );
OAI21X1TS U4085 ( .A0(n2765), .A1(n2761), .B0(n2762), .Y(n2748) );
XNOR2X4TS U4086 ( .A(n2748), .B(n2747), .Y(n2911) );
INVX2TS U4087 ( .A(n2267), .Y(n2848) );
INVX2TS U4088 ( .A(n2761), .Y(n2763) );
NAND2X1TS U4089 ( .A(n2763), .B(n2762), .Y(n2764) );
CLKXOR2X2TS U4090 ( .A(n2765), .B(n2764), .Y(n2949) );
INVX2TS U4091 ( .A(n2949), .Y(n2783) );
INVX2TS U4092 ( .A(n2767), .Y(n2768) );
INVX2TS U4093 ( .A(n2779), .Y(n2781) );
NAND2X1TS U4094 ( .A(n2781), .B(n2780), .Y(n2782) );
CLKXOR2X2TS U4095 ( .A(n2782), .B(n2788), .Y(n2951) );
INVX2TS U4096 ( .A(n2951), .Y(n2789) );
OAI22X1TS U4097 ( .A0(n2783), .A1(n2859), .B0(n2789), .B1(n2675), .Y(n2787)
);
NAND2X1TS U4098 ( .A(n2306), .B(n2788), .Y(n2791) );
OAI22X1TS U4099 ( .A0(n2789), .A1(n2859), .B0(n2675), .B1(n2791), .Y(n2798)
);
CLKINVX6TS U4100 ( .A(n2791), .Y(n3568) );
XNOR2X1TS U4101 ( .A(n2867), .B(n3568), .Y(n2794) );
INVX2TS U4102 ( .A(n2268), .Y(n2902) );
XNOR2X1TS U4103 ( .A(n2268), .B(n3568), .Y(n2833) );
NOR2BX1TS U4104 ( .AN(n3568), .B(n2264), .Y(n2846) );
XNOR2X1TS U4105 ( .A(n2267), .B(n3568), .Y(n2850) );
OAI22X1TS U4106 ( .A0(n2853), .A1(n2675), .B0(n3595), .B1(n2859), .Y(
DP_OP_453J210_122_681_n435) );
AO21XLTS U4107 ( .A0(n2870), .A1(n2261), .B0(n2861), .Y(
DP_OP_453J210_122_681_n448) );
INVX3TS U4108 ( .A(FPMULT_Op_MY[4]), .Y(n3212) );
INVX3TS U4109 ( .A(FPMULT_Op_MX[8]), .Y(n3315) );
INVX3TS U4110 ( .A(FPMULT_Op_MX[4]), .Y(n3213) );
INVX3TS U4111 ( .A(n2254), .Y(n3238) );
INVX3TS U4112 ( .A(FPMULT_Op_MY[2]), .Y(n3146) );
INVX3TS U4113 ( .A(FPMULT_Op_MX[7]), .Y(n3295) );
INVX3TS U4114 ( .A(FPMULT_Op_MX[3]), .Y(n3193) );
INVX3TS U4115 ( .A(FPMULT_Op_MX[1]), .Y(n3077) );
INVX3TS U4116 ( .A(FPMULT_Op_MY[6]), .Y(n3269) );
INVX3TS U4117 ( .A(n2253), .Y(n3565) );
NOR2XLTS U4118 ( .A(n3565), .B(n3339), .Y(n3029) );
NOR2X2TS U4119 ( .A(n3138), .B(n3137), .Y(n3422) );
NOR2X2TS U4120 ( .A(n3136), .B(n3135), .Y(n3427) );
NOR2X1TS U4121 ( .A(n3422), .B(n3427), .Y(n3140) );
NOR2XLTS U4122 ( .A(n3565), .B(n3327), .Y(n3051) );
NOR2X2TS U4123 ( .A(n3134), .B(n3133), .Y(n3434) );
NOR2X1TS U4124 ( .A(n3076), .B(n3245), .Y(n3089) );
NOR2X1TS U4125 ( .A(n3132), .B(n3131), .Y(n3432) );
NOR2X1TS U4126 ( .A(n3434), .B(n3432), .Y(n3421) );
NAND2X1TS U4127 ( .A(n3140), .B(n3421), .Y(n3142) );
NOR2X1TS U4128 ( .A(n3565), .B(n3146), .Y(n3062) );
NOR2X1TS U4129 ( .A(n3164), .B(n3564), .Y(n3064) );
NOR2X1TS U4130 ( .A(n3076), .B(n3077), .Y(n3063) );
NOR2X1TS U4131 ( .A(n3062), .B(n3061), .Y(n3473) );
NOR2X1TS U4132 ( .A(n3565), .B(n3076), .Y(n3558) );
NOR2X1TS U4133 ( .A(n3077), .B(n3564), .Y(n3557) );
NAND2X1TS U4134 ( .A(n3558), .B(n3557), .Y(n3559) );
NAND2X1TS U4135 ( .A(n3062), .B(n3061), .Y(n3474) );
OAI21X1TS U4136 ( .A0(n3473), .A1(n3559), .B0(n3474), .Y(n3462) );
NOR2X2TS U4137 ( .A(n3071), .B(n3070), .Y(n3468) );
NOR2X1TS U4138 ( .A(n3565), .B(n3212), .Y(n3073) );
NOR2X2TS U4139 ( .A(n3073), .B(n3072), .Y(n3463) );
NOR2XLTS U4140 ( .A(n3468), .B(n3463), .Y(n3075) );
NAND2X1TS U4141 ( .A(n3071), .B(n3070), .Y(n3469) );
NAND2X1TS U4142 ( .A(n3073), .B(n3072), .Y(n3464) );
OAI21XLTS U4143 ( .A0(n3463), .A1(n3469), .B0(n3464), .Y(n3074) );
AOI21X1TS U4144 ( .A0(n3462), .A1(n3075), .B0(n3074), .Y(n3454) );
NOR2X1TS U4145 ( .A(n3565), .B(n3238), .Y(n3103) );
NAND2X1TS U4146 ( .A(n2292), .B(n2293), .Y(n3109) );
NAND2X1TS U4147 ( .A(n3104), .B(n3103), .Y(n3459) );
INVX2TS U4148 ( .A(n3459), .Y(n3455) );
NAND2X1TS U4149 ( .A(n3106), .B(n3105), .Y(n3456) );
INVX2TS U4150 ( .A(n3456), .Y(n3107) );
AOI21X1TS U4151 ( .A0(n2292), .A1(n3455), .B0(n3107), .Y(n3108) );
OAI21X1TS U4152 ( .A0(n3454), .A1(n3109), .B0(n3108), .Y(n3443) );
NOR2X2TS U4153 ( .A(n3128), .B(n3127), .Y(n3444) );
NOR2X2TS U4154 ( .A(n3126), .B(n3125), .Y(n3449) );
NAND2X1TS U4155 ( .A(n3126), .B(n3125), .Y(n3450) );
NAND2X1TS U4156 ( .A(n3128), .B(n3127), .Y(n3445) );
AOI21X1TS U4157 ( .A0(n3443), .A1(n3130), .B0(n3129), .Y(n3419) );
NAND2X1TS U4158 ( .A(n3134), .B(n3133), .Y(n3435) );
OAI21X1TS U4159 ( .A0(n3434), .A1(n3439), .B0(n3435), .Y(n3420) );
NAND2X1TS U4160 ( .A(n3136), .B(n3135), .Y(n3428) );
NAND2X1TS U4161 ( .A(n3138), .B(n3137), .Y(n3423) );
AOI21X1TS U4162 ( .A0(n3140), .A1(n3420), .B0(n3139), .Y(n3141) );
OAI21X1TS U4163 ( .A0(n3142), .A1(n3419), .B0(n3141), .Y(n3394) );
NOR2X1TS U4164 ( .A(n3327), .B(n3245), .Y(n3221) );
NOR2X1TS U4165 ( .A(n3348), .B(n3193), .Y(n3218) );
NOR2X2TS U4166 ( .A(n3255), .B(n3254), .Y(n3409) );
NOR2X1TS U4167 ( .A(n3414), .B(n3409), .Y(n3402) );
NOR2X2TS U4168 ( .A(n3260), .B(n3259), .Y(n3397) );
NAND2X1TS U4169 ( .A(n3253), .B(n3252), .Y(n3415) );
NAND2X1TS U4170 ( .A(n3255), .B(n3254), .Y(n3410) );
NAND2X1TS U4171 ( .A(n3257), .B(n3256), .Y(n3406) );
INVX2TS U4172 ( .A(n3406), .Y(n3258) );
AOI21X1TS U4173 ( .A0(n3403), .A1(n2310), .B0(n3258), .Y(n3395) );
NAND2X1TS U4174 ( .A(n3260), .B(n3259), .Y(n3398) );
AOI21X1TS U4175 ( .A0(n3394), .A1(n3262), .B0(n3261), .Y(n3393) );
NOR2X1TS U4176 ( .A(n3284), .B(n3283), .Y(n3389) );
NAND2X1TS U4177 ( .A(n3284), .B(n3283), .Y(n3390) );
OAI21X1TS U4178 ( .A0(n3393), .A1(n3389), .B0(n3390), .Y(n3388) );
NAND2X1TS U4179 ( .A(n3303), .B(n3302), .Y(n3386) );
INVX2TS U4180 ( .A(n3386), .Y(n3304) );
AOI21X1TS U4181 ( .A0(n3388), .A1(n2294), .B0(n3304), .Y(n3385) );
NOR2X1TS U4182 ( .A(n3348), .B(n3315), .Y(n3324) );
NOR2X1TS U4183 ( .A(n3320), .B(n3319), .Y(n3381) );
NAND2X1TS U4184 ( .A(n3320), .B(n3319), .Y(n3382) );
OAI21X1TS U4185 ( .A0(n3385), .A1(n3381), .B0(n3382), .Y(n3380) );
NOR2X1TS U4186 ( .A(n3348), .B(n2199), .Y(n3341) );
NAND2X1TS U4187 ( .A(n3333), .B(n3332), .Y(n3378) );
INVX2TS U4188 ( .A(n3378), .Y(n3334) );
AOI21X1TS U4189 ( .A0(n3380), .A1(n2290), .B0(n3334), .Y(n3377) );
NOR2X1TS U4190 ( .A(n3344), .B(n3343), .Y(n3373) );
NAND2X1TS U4191 ( .A(n3344), .B(n3343), .Y(n3374) );
OAI21X1TS U4192 ( .A0(n3377), .A1(n3373), .B0(n3374), .Y(n3372) );
NOR2X1TS U4193 ( .A(n3348), .B(DP_OP_453J210_122_681_n667), .Y(n3349) );
NAND2X1TS U4194 ( .A(n3350), .B(n3349), .Y(n3370) );
INVX2TS U4195 ( .A(n3370), .Y(n3351) );
AOI21X1TS U4196 ( .A0(n3372), .A1(n2291), .B0(n3351), .Y(
DP_OP_453J210_122_681_n404) );
NAND2X1TS U4197 ( .A(n2291), .B(n3370), .Y(n3371) );
XNOR2X1TS U4198 ( .A(n3372), .B(n3371), .Y(n4750) );
INVX2TS U4199 ( .A(n4750), .Y(DP_OP_453J210_122_681_n405) );
NAND2X1TS U4200 ( .A(n3375), .B(n3374), .Y(n3376) );
INVX2TS U4201 ( .A(n4754), .Y(DP_OP_453J210_122_681_n406) );
NAND2X1TS U4202 ( .A(n2290), .B(n3378), .Y(n3379) );
XNOR2X1TS U4203 ( .A(n3380), .B(n3379), .Y(n4758) );
INVX2TS U4204 ( .A(n4758), .Y(DP_OP_453J210_122_681_n407) );
INVX2TS U4205 ( .A(n3381), .Y(n3383) );
NAND2X1TS U4206 ( .A(n3383), .B(n3382), .Y(n3384) );
INVX2TS U4207 ( .A(n4762), .Y(DP_OP_453J210_122_681_n408) );
NAND2X1TS U4208 ( .A(n2294), .B(n3386), .Y(n3387) );
XNOR2X1TS U4209 ( .A(n3388), .B(n3387), .Y(n4766) );
INVX2TS U4210 ( .A(n4766), .Y(DP_OP_453J210_122_681_n409) );
INVX2TS U4211 ( .A(n3389), .Y(n3391) );
INVX2TS U4212 ( .A(n4770), .Y(DP_OP_453J210_122_681_n410) );
INVX2TS U4213 ( .A(n3394), .Y(n3418) );
INVX2TS U4214 ( .A(n3397), .Y(n3399) );
NAND2X1TS U4215 ( .A(n3399), .B(n3398), .Y(n3400) );
XNOR2X1TS U4216 ( .A(n3401), .B(n3400), .Y(n4774) );
INVX2TS U4217 ( .A(n3402), .Y(n3405) );
INVX2TS U4218 ( .A(n3403), .Y(n3404) );
NAND2X1TS U4219 ( .A(n2310), .B(n3406), .Y(n3407) );
XNOR2X1TS U4220 ( .A(n3408), .B(n3407), .Y(n4778) );
INVX2TS U4221 ( .A(n4778), .Y(DP_OP_453J210_122_681_n412) );
INVX2TS U4222 ( .A(n3409), .Y(n3411) );
NAND2X1TS U4223 ( .A(n3411), .B(n3410), .Y(n3412) );
XNOR2X1TS U4224 ( .A(n3413), .B(n3412), .Y(n4784) );
INVX2TS U4225 ( .A(n4784), .Y(DP_OP_453J210_122_681_n413) );
INVX2TS U4226 ( .A(n3414), .Y(n3416) );
XOR2X1TS U4227 ( .A(n3418), .B(n3417), .Y(n4788) );
INVX2TS U4228 ( .A(n4788), .Y(DP_OP_453J210_122_681_n414) );
INVX2TS U4229 ( .A(n3419), .Y(n3442) );
AOI21X1TS U4230 ( .A0(n3442), .A1(n3421), .B0(n3420), .Y(n3431) );
INVX2TS U4231 ( .A(n3422), .Y(n3424) );
NAND2X1TS U4232 ( .A(n3424), .B(n3423), .Y(n3425) );
XNOR2X1TS U4233 ( .A(n3426), .B(n3425), .Y(n4792) );
INVX2TS U4234 ( .A(n4792), .Y(DP_OP_453J210_122_681_n415) );
INVX2TS U4235 ( .A(n3427), .Y(n3429) );
XOR2X1TS U4236 ( .A(n3431), .B(n3430), .Y(n4794) );
INVX2TS U4237 ( .A(n4794), .Y(DP_OP_453J210_122_681_n416) );
INVX2TS U4238 ( .A(n3432), .Y(n3440) );
INVX2TS U4239 ( .A(n3439), .Y(n3433) );
AOI21X1TS U4240 ( .A0(n3442), .A1(n3440), .B0(n3433), .Y(n3438) );
INVX2TS U4241 ( .A(n3434), .Y(n3436) );
NAND2X1TS U4242 ( .A(n3436), .B(n3435), .Y(n3437) );
XOR2X1TS U4243 ( .A(n3438), .B(n3437), .Y(n4795) );
INVX2TS U4244 ( .A(n4795), .Y(DP_OP_453J210_122_681_n417) );
NAND2X1TS U4245 ( .A(n3440), .B(n3439), .Y(n3441) );
XNOR2X1TS U4246 ( .A(n3442), .B(n3441), .Y(n4797) );
INVX2TS U4247 ( .A(n4797), .Y(DP_OP_453J210_122_681_n418) );
INVX2TS U4248 ( .A(n3443), .Y(n3453) );
INVX2TS U4249 ( .A(n3444), .Y(n3446) );
NAND2X1TS U4250 ( .A(n3446), .B(n3445), .Y(n3447) );
XNOR2X1TS U4251 ( .A(n3448), .B(n3447), .Y(n4798) );
INVX2TS U4252 ( .A(n4798), .Y(DP_OP_453J210_122_681_n419) );
INVX2TS U4253 ( .A(n3449), .Y(n3451) );
NAND2X1TS U4254 ( .A(n3451), .B(n3450), .Y(n3452) );
XOR2X1TS U4255 ( .A(n3453), .B(n3452), .Y(n4799) );
INVX2TS U4256 ( .A(n4799), .Y(DP_OP_453J210_122_681_n420) );
INVX2TS U4257 ( .A(n3454), .Y(n3461) );
AOI21X1TS U4258 ( .A0(n3461), .A1(n2293), .B0(n3455), .Y(n3458) );
NAND2X1TS U4259 ( .A(n2292), .B(n3456), .Y(n3457) );
XOR2X1TS U4260 ( .A(n3458), .B(n3457), .Y(n4800) );
NAND2X1TS U4261 ( .A(n2293), .B(n3459), .Y(n3460) );
XNOR2X1TS U4262 ( .A(n3461), .B(n3460), .Y(n4801) );
INVX2TS U4263 ( .A(n4801), .Y(DP_OP_453J210_122_681_n422) );
OAI21XLTS U4264 ( .A0(n3472), .A1(n3468), .B0(n3469), .Y(n3467) );
NAND2X1TS U4265 ( .A(n3465), .B(n3464), .Y(n3466) );
XNOR2X1TS U4266 ( .A(n3467), .B(n3466), .Y(n4802) );
INVX2TS U4267 ( .A(n4802), .Y(DP_OP_453J210_122_681_n423) );
INVX2TS U4268 ( .A(n3468), .Y(n3470) );
NAND2X1TS U4269 ( .A(n3470), .B(n3469), .Y(n3471) );
XOR2X1TS U4270 ( .A(n3472), .B(n3471), .Y(n4803) );
INVX2TS U4271 ( .A(n3473), .Y(n3475) );
NAND2X1TS U4272 ( .A(n3475), .B(n3474), .Y(n3476) );
XOR2X1TS U4273 ( .A(n3476), .B(n3559), .Y(n4804) );
INVX2TS U4274 ( .A(n4804), .Y(DP_OP_453J210_122_681_n425) );
NAND2X1TS U4275 ( .A(n2321), .B(n3534), .Y(n3535) );
XNOR2X1TS U4276 ( .A(n3536), .B(n3535), .Y(n4718) );
INVX2TS U4277 ( .A(n3543), .Y(n3545) );
INVX2TS U4278 ( .A(n4726), .Y(DP_OP_453J210_122_681_n785) );
INVX2TS U4279 ( .A(n3548), .Y(n3550) );
INVX2TS U4280 ( .A(n4730), .Y(DP_OP_453J210_122_681_n786) );
NAND2X1TS U4281 ( .A(n2298), .B(n3553), .Y(n3555) );
XNOR2X1TS U4282 ( .A(n3555), .B(n3554), .Y(n4734) );
INVX2TS U4283 ( .A(n4734), .Y(DP_OP_453J210_122_681_n787) );
NOR3X2TS U4284 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[2]), .C(n5211), .Y(n3755) );
NAND3XLTS U4285 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FSM_add_overflow_flag), .C(n3755), .Y(n3556) );
CLKINVX6TS U4286 ( .A(n4671), .Y(n4809) );
NOR2X1TS U4287 ( .A(n3624), .B(n3625), .Y(n3592) );
NAND2X1TS U4288 ( .A(n2295), .B(n3559), .Y(n4805) );
NAND2X1TS U4289 ( .A(n3563), .B(n3562), .Y(n3569) );
INVX2TS U4290 ( .A(n4807), .Y(n3720) );
NOR2BX1TS U4291 ( .AN(n2278), .B(n3566), .Y(n4742) );
INVX2TS U4292 ( .A(n4742), .Y(n3719) );
NOR2BX1TS U4293 ( .AN(n3568), .B(n3567), .Y(n3718) );
INVX2TS U4294 ( .A(n3716), .Y(n3571) );
INVX2TS U4295 ( .A(n3710), .Y(n3573) );
INVX2TS U4296 ( .A(n3696), .Y(n3698) );
INVX2TS U4297 ( .A(n3705), .Y(n3707) );
INVX2TS U4298 ( .A(n3713), .Y(n3715) );
XNOR2X1TS U4299 ( .A(n3717), .B(n3716), .Y(n4789) );
CMPR32X2TS U4300 ( .A(n3720), .B(n3719), .C(n3718), .CO(n3716), .S(n4791) );
OR4X2TS U4301 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n3723) );
NAND4X1TS U4302 ( .A(n5182), .B(n5190), .C(n5274), .D(n5211), .Y(n5518) );
CLKBUFX2TS U4303 ( .A(n5451), .Y(n5511) );
INVX2TS U4304 ( .A(n4441), .Y(n4463) );
INVX2TS U4305 ( .A(rst), .Y(n3737) );
INVX2TS U4306 ( .A(n3755), .Y(n4090) );
NOR4X1TS U4307 ( .A(FPMULT_P_Sgf[14]), .B(FPMULT_P_Sgf[15]), .C(
FPMULT_P_Sgf[16]), .D(FPMULT_P_Sgf[17]), .Y(n3735) );
NOR4X1TS U4308 ( .A(FPMULT_P_Sgf[18]), .B(FPMULT_P_Sgf[19]), .C(
FPMULT_P_Sgf[20]), .D(FPMULT_P_Sgf[21]), .Y(n3734) );
NOR4X1TS U4309 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_P_Sgf[3]), .C(
FPMULT_P_Sgf[4]), .D(FPMULT_P_Sgf[5]), .Y(n3730) );
NOR3XLTS U4310 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[0]), .C(
FPMULT_P_Sgf[1]), .Y(n3729) );
NOR4X1TS U4311 ( .A(FPMULT_P_Sgf[10]), .B(FPMULT_P_Sgf[11]), .C(
FPMULT_P_Sgf[12]), .D(FPMULT_P_Sgf[13]), .Y(n3728) );
NOR4X1TS U4312 ( .A(FPMULT_P_Sgf[6]), .B(FPMULT_P_Sgf[7]), .C(
FPMULT_P_Sgf[8]), .D(FPMULT_P_Sgf[9]), .Y(n3727) );
AND4X1TS U4313 ( .A(n3730), .B(n3729), .C(n3728), .D(n3727), .Y(n3733) );
XOR2X1TS U4314 ( .A(FPMULT_Op_MX[31]), .B(FPMULT_Op_MY[31]), .Y(n4814) );
MXI2X1TS U4315 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n4814), .Y(n3731) );
OAI21XLTS U4316 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n3731), .Y(n3732) );
AOI31X1TS U4317 ( .A0(n3735), .A1(n3734), .A2(n3733), .B0(n3732), .Y(n4091)
);
INVX2TS U4318 ( .A(n4091), .Y(n3736) );
OAI31X1TS U4319 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(n4090), .A2(n3736),
.B0(n5361), .Y(n1690) );
CLKBUFX2TS U4320 ( .A(n2217), .Y(n3739) );
BUFX3TS U4321 ( .A(n5451), .Y(n5504) );
BUFX3TS U4322 ( .A(n2217), .Y(n5486) );
BUFX3TS U4323 ( .A(n5451), .Y(n5505) );
BUFX3TS U4324 ( .A(n5451), .Y(n5509) );
NOR2BX1TS U4325 ( .AN(n3747), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.Y(n3746) );
NAND4X2TS U4326 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n3746),
.C(n5221), .D(n5318), .Y(n4439) );
INVX2TS U4327 ( .A(n4439), .Y(n4440) );
BUFX3TS U4328 ( .A(n2217), .Y(n5495) );
BUFX3TS U4329 ( .A(n5503), .Y(n5482) );
CLKBUFX2TS U4330 ( .A(n2217), .Y(n5494) );
BUFX3TS U4331 ( .A(n2217), .Y(n5501) );
BUFX3TS U4332 ( .A(n2217), .Y(n5498) );
BUFX3TS U4333 ( .A(n2217), .Y(n5497) );
BUFX3TS U4334 ( .A(n2217), .Y(n5496) );
BUFX3TS U4335 ( .A(n2217), .Y(n5499) );
BUFX3TS U4336 ( .A(n2212), .Y(n5475) );
BUFX3TS U4337 ( .A(n3738), .Y(n5461) );
BUFX3TS U4338 ( .A(n2212), .Y(n5457) );
BUFX3TS U4339 ( .A(n3749), .Y(n5455) );
BUFX3TS U4340 ( .A(n2212), .Y(n5469) );
BUFX3TS U4341 ( .A(n2212), .Y(n5471) );
BUFX3TS U4342 ( .A(n3749), .Y(n5466) );
BUFX3TS U4343 ( .A(n2212), .Y(n5468) );
BUFX3TS U4344 ( .A(n3749), .Y(n5464) );
BUFX3TS U4345 ( .A(n5451), .Y(n5506) );
BUFX3TS U4346 ( .A(n2212), .Y(n5467) );
BUFX3TS U4347 ( .A(n2212), .Y(n5454) );
BUFX3TS U4348 ( .A(n2212), .Y(n5460) );
BUFX3TS U4349 ( .A(n2212), .Y(n5472) );
BUFX3TS U4350 ( .A(n2212), .Y(n5458) );
BUFX3TS U4351 ( .A(n3749), .Y(n5465) );
CLKXOR2X2TS U4352 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n4949) );
AOI2BB2XLTS U4353 ( .B0(FPADDSUB_intDX_EWSW[31]), .B1(n4949), .A0N(n4949),
.A1N(FPADDSUB_intDX_EWSW[31]), .Y(n3740) );
AO22XLTS U4354 ( .A0(n4953), .A1(n3740), .B0(n2312), .B1(
FPADDSUB_OP_FLAG_EXP), .Y(n1357) );
AO22XLTS U4355 ( .A0(n5185), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n5123),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1429) );
AO22XLTS U4356 ( .A0(n5185), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n5123),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1444) );
AO22XLTS U4357 ( .A0(n5185), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n5123),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1434) );
NAND2X1TS U4358 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n4418) );
INVX2TS U4359 ( .A(n4418), .Y(n3745) );
OR4X2TS U4360 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3742) );
NOR2X1TS U4361 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(n3742),
.Y(n3820) );
NOR2BX1TS U4362 ( .AN(n3820), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n4087) );
NOR3XLTS U4363 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n3741) );
NAND3BXLTS U4364 ( .AN(n3742), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]),
.C(n3741), .Y(n3743) );
INVX4TS U4365 ( .A(n3744), .Y(n4506) );
OAI21XLTS U4366 ( .A0(n3745), .A1(n4419), .B0(n4574), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
NAND2BX1TS U4367 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n3746),
.Y(n4415) );
NOR3X1TS U4368 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n5318),
.C(n4415), .Y(n4478) );
BUFX3TS U4369 ( .A(n2213), .Y(n5512) );
NOR3XLTS U4370 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3748) );
NAND3XLTS U4371 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(n3748),
.C(n3747), .Y(n3980) );
AOI21X1TS U4372 ( .A0(operation[1]), .A1(ack_operation), .B0(n3980), .Y(
n4412) );
NAND3XLTS U4373 ( .A(FPSENCOS_cont_iter_out[1]), .B(n5452), .C(n3821), .Y(
n4417) );
NOR2X1TS U4374 ( .A(n4439), .B(n4417), .Y(n3981) );
OR2X1TS U4375 ( .A(n4412), .B(n3981), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
OAI21XLTS U4376 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n2239), .B0(n4184),
.Y(n1352) );
NAND2X2TS U4377 ( .A(n4954), .B(n5517), .Y(n4556) );
OAI21XLTS U4378 ( .A0(n4556), .A1(n5142), .B0(n4083), .Y(n2080) );
OAI21XLTS U4379 ( .A0(n4556), .A1(n5329), .B0(n4184), .Y(n2081) );
NOR2X1TS U4380 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n5182), .Y(n3754) );
NOR2BX1TS U4381 ( .AN(FPMULT_P_Sgf[47]), .B(n4585), .Y(n3751) );
NAND4X1TS U4382 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[0]), .C(n5182), .D(n5190), .Y(n4645) );
NAND2X1TS U4383 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FS_Module_state_reg[0]), .Y(n3750) );
INVX2TS U4384 ( .A(n4616), .Y(n4613) );
OAI211XLTS U4385 ( .A0(n3751), .A1(n5324), .B0(n4664), .C0(n4613), .Y(n1551)
);
INVX2TS U4386 ( .A(n3751), .Y(n3752) );
OAI31X1TS U4387 ( .A0(n4616), .A1(n4668), .A2(n5327), .B0(n3752), .Y(n1550)
);
AOI32X4TS U4388 ( .A0(FPMULT_FSM_add_overflow_flag), .A1(
FPMULT_FS_Module_state_reg[1]), .A2(n3755), .B0(n3753), .B1(
FPMULT_FS_Module_state_reg[1]), .Y(n4618) );
NOR2XLTS U4389 ( .A(n4618), .B(n5361), .Y(n3757) );
AOI22X1TS U4390 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n2205), .B0(
n3803), .B1(FPMULT_Add_result[3]), .Y(n3762) );
NAND2X1TS U4391 ( .A(n3756), .B(n4618), .Y(n3759) );
NOR2XLTS U4392 ( .A(FPMULT_FSM_selector_C), .B(n3759), .Y(n3758) );
NOR2XLTS U4393 ( .A(n5361), .B(n3759), .Y(n3760) );
AOI22X1TS U4394 ( .A0(n3808), .A1(FPMULT_P_Sgf[25]), .B0(n3807), .B1(
FPMULT_Add_result[2]), .Y(n3761) );
OAI211XLTS U4395 ( .A0(n3806), .A1(n5384), .B0(n3762), .C0(n3761), .Y(n1519)
);
AOI22X1TS U4396 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n2205), .B0(
n3803), .B1(FPMULT_Add_result[1]), .Y(n3764) );
AOI22X1TS U4397 ( .A0(n3808), .A1(FPMULT_P_Sgf[23]), .B0(n3807), .B1(
FPMULT_Add_result[0]), .Y(n3763) );
OAI211XLTS U4398 ( .A0(n3806), .A1(n5386), .B0(n3764), .C0(n3763), .Y(n1517)
);
AOI22X1TS U4399 ( .A0(n2255), .A1(n2205), .B0(n3803), .B1(
FPMULT_Add_result[2]), .Y(n3766) );
AOI22X1TS U4400 ( .A0(n3808), .A1(FPMULT_P_Sgf[24]), .B0(n3807), .B1(
FPMULT_Add_result[1]), .Y(n3765) );
OAI211XLTS U4401 ( .A0(n3806), .A1(n5385), .B0(n3766), .C0(n3765), .Y(n1518)
);
AOI22X1TS U4402 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n2205), .B0(
n3803), .B1(FPMULT_Add_result[4]), .Y(n3768) );
AOI22X1TS U4403 ( .A0(n3808), .A1(FPMULT_P_Sgf[26]), .B0(n3807), .B1(
FPMULT_Add_result[3]), .Y(n3767) );
OAI211XLTS U4404 ( .A0(n3806), .A1(n5383), .B0(n3768), .C0(n3767), .Y(n1520)
);
AOI22X1TS U4405 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n2205), .B0(
FPMULT_Add_result[6]), .B1(n3803), .Y(n3770) );
AOI22X1TS U4406 ( .A0(n3808), .A1(FPMULT_P_Sgf[28]), .B0(n3807), .B1(
FPMULT_Add_result[5]), .Y(n3769) );
AOI22X1TS U4407 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n2205), .B0(
n3803), .B1(FPMULT_Add_result[5]), .Y(n3772) );
AOI22X1TS U4408 ( .A0(n3808), .A1(FPMULT_P_Sgf[27]), .B0(n3807), .B1(
FPMULT_Add_result[4]), .Y(n3771) );
OAI211XLTS U4409 ( .A0(n3806), .A1(n5382), .B0(n3772), .C0(n3771), .Y(n1521)
);
AOI22X1TS U4410 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n2205), .B0(
FPMULT_Add_result[8]), .B1(n3803), .Y(n3774) );
AOI22X1TS U4411 ( .A0(FPMULT_Add_result[7]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[30]), .Y(n3773) );
OAI211XLTS U4412 ( .A0(n3806), .A1(n5401), .B0(n3774), .C0(n3773), .Y(n1524)
);
AOI22X1TS U4413 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n2205), .B0(
FPMULT_Add_result[18]), .B1(n3803), .Y(n3776) );
AOI22X1TS U4414 ( .A0(FPMULT_Add_result[17]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[40]), .Y(n3775) );
OAI211XLTS U4415 ( .A0(n3806), .A1(n5391), .B0(n3776), .C0(n3775), .Y(n1534)
);
AOI22X1TS U4416 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n2205), .B0(
FPMULT_Add_result[20]), .B1(n3803), .Y(n3778) );
AOI22X1TS U4417 ( .A0(FPMULT_Add_result[19]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[42]), .Y(n3777) );
OAI211XLTS U4418 ( .A0(n3806), .A1(n5389), .B0(n3778), .C0(n3777), .Y(n1536)
);
AOI22X1TS U4419 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n2205), .B0(
FPMULT_Add_result[22]), .B1(n3803), .Y(n3780) );
AOI22X1TS U4420 ( .A0(FPMULT_Add_result[21]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[44]), .Y(n3779) );
OAI211XLTS U4421 ( .A0(n5387), .A1(n3806), .B0(n3780), .C0(n3779), .Y(n1538)
);
AOI22X1TS U4422 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n2205), .B0(
FPMULT_Add_result[12]), .B1(n3803), .Y(n3782) );
AOI22X1TS U4423 ( .A0(FPMULT_Add_result[11]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[34]), .Y(n3781) );
OAI211XLTS U4424 ( .A0(n3806), .A1(n5397), .B0(n3782), .C0(n3781), .Y(n1528)
);
AOI22X1TS U4425 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n2205), .B0(
FPMULT_Add_result[10]), .B1(n3803), .Y(n3784) );
AOI22X1TS U4426 ( .A0(FPMULT_Add_result[9]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[32]), .Y(n3783) );
OAI211XLTS U4427 ( .A0(n3806), .A1(n5399), .B0(n3784), .C0(n3783), .Y(n1526)
);
AOI22X1TS U4428 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n2205), .B0(
FPMULT_Add_result[16]), .B1(n3803), .Y(n3786) );
AOI22X1TS U4429 ( .A0(FPMULT_Add_result[15]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[38]), .Y(n3785) );
OAI211XLTS U4430 ( .A0(n3806), .A1(n5393), .B0(n3786), .C0(n3785), .Y(n1532)
);
AOI22X1TS U4431 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n2205), .B0(
FPMULT_Add_result[14]), .B1(n3803), .Y(n3788) );
AOI22X1TS U4432 ( .A0(FPMULT_Add_result[13]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[36]), .Y(n3787) );
OAI211XLTS U4433 ( .A0(n3806), .A1(n5395), .B0(n3788), .C0(n3787), .Y(n1530)
);
AOI22X1TS U4434 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n2205), .B0(
FPMULT_Add_result[9]), .B1(n3803), .Y(n3790) );
AOI22X1TS U4435 ( .A0(FPMULT_Add_result[8]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[31]), .Y(n3789) );
AOI22X1TS U4436 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n2205), .B0(
FPMULT_Add_result[13]), .B1(n3803), .Y(n3792) );
AOI22X1TS U4437 ( .A0(FPMULT_Add_result[12]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[35]), .Y(n3791) );
OAI211XLTS U4438 ( .A0(n3806), .A1(n5396), .B0(n3792), .C0(n3791), .Y(n1529)
);
AOI22X1TS U4439 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n2205), .B0(
FPMULT_Add_result[21]), .B1(n3803), .Y(n3794) );
AOI22X1TS U4440 ( .A0(FPMULT_Add_result[20]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[43]), .Y(n3793) );
OAI211XLTS U4441 ( .A0(n5381), .A1(n3806), .B0(n3794), .C0(n3793), .Y(n1537)
);
AOI22X1TS U4442 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n2205), .B0(
FPMULT_Add_result[7]), .B1(n3803), .Y(n3796) );
AOI22X1TS U4443 ( .A0(FPMULT_Add_result[6]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[29]), .Y(n3795) );
OAI211XLTS U4444 ( .A0(n3806), .A1(n5402), .B0(n3796), .C0(n3795), .Y(n1523)
);
AOI22X1TS U4445 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n2205), .B0(
FPMULT_Add_result[11]), .B1(n3803), .Y(n3798) );
AOI22X1TS U4446 ( .A0(FPMULT_Add_result[10]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[33]), .Y(n3797) );
OAI211XLTS U4447 ( .A0(n3806), .A1(n5398), .B0(n3798), .C0(n3797), .Y(n1527)
);
AOI22X1TS U4448 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n2205), .B0(
FPMULT_Add_result[17]), .B1(n3803), .Y(n3800) );
AOI22X1TS U4449 ( .A0(FPMULT_Add_result[16]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[39]), .Y(n3799) );
OAI211XLTS U4450 ( .A0(n3806), .A1(n5392), .B0(n3800), .C0(n3799), .Y(n1533)
);
AOI22X1TS U4451 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n2205), .B0(
FPMULT_Add_result[19]), .B1(n3803), .Y(n3802) );
AOI22X1TS U4452 ( .A0(FPMULT_Add_result[18]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[41]), .Y(n3801) );
OAI211XLTS U4453 ( .A0(n3806), .A1(n5390), .B0(n3802), .C0(n3801), .Y(n1535)
);
AOI22X1TS U4454 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n2205), .B0(
FPMULT_Add_result[15]), .B1(n3803), .Y(n3805) );
AOI22X1TS U4455 ( .A0(FPMULT_Add_result[14]), .A1(n3807), .B0(n3808), .B1(
FPMULT_P_Sgf[37]), .Y(n3804) );
OAI211XLTS U4456 ( .A0(n3806), .A1(n5394), .B0(n3805), .C0(n3804), .Y(n1531)
);
AOI22X1TS U4457 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n5361), .Y(n4617) );
AOI22X1TS U4458 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n2205), .B0(
FPMULT_Add_result[22]), .B1(n3807), .Y(n3810) );
NAND2X1TS U4459 ( .A(n3808), .B(FPMULT_P_Sgf[45]), .Y(n3809) );
OAI211XLTS U4460 ( .A0(n4618), .A1(n4617), .B0(n3810), .C0(n3809), .Y(n1539)
);
NAND2X1TS U4461 ( .A(n5452), .B(n5230), .Y(intadd_477_CI) );
NAND2X1TS U4462 ( .A(n2214), .B(n5525), .Y(n4464) );
INVX2TS U4463 ( .A(n4464), .Y(n3814) );
AOI22X1TS U4464 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n3814), .B0(
FPSENCOS_d_ff3_sh_y_out[23]), .B1(n4506), .Y(n3811) );
OAI21XLTS U4465 ( .A0(n4574), .A1(intadd_477_CI), .B0(n3811), .Y(n1855) );
NAND2X2TS U4466 ( .A(n2214), .B(n5314), .Y(n4466) );
AOI21X1TS U4467 ( .A0(n5452), .A1(n4463), .B0(FPSENCOS_cont_iter_out[3]),
.Y(n3825) );
AOI22X1TS U4468 ( .A0(n3744), .A1(n3825), .B0(FPSENCOS_d_ff3_LUT_out[26]),
.B1(n4506), .Y(n3812) );
OAI21XLTS U4469 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n4466), .B0(n3812),
.Y(n2116) );
INVX2TS U4470 ( .A(n4461), .Y(n3827) );
NOR3X1TS U4471 ( .A(n4463), .B(n5525), .C(n4460), .Y(n3816) );
AOI21X1TS U4472 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n4506), .B0(n3816),
.Y(n3813) );
OAI21XLTS U4473 ( .A0(n4466), .A1(n3827), .B0(n3813), .Y(n2133) );
OR2X1TS U4474 ( .A(FPSENCOS_d_ff2_X[23]), .B(n5525), .Y(intadd_478_CI) );
AOI22X1TS U4475 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n3814), .B0(
FPSENCOS_d_ff3_sh_x_out[23]), .B1(n4506), .Y(n3815) );
OAI21XLTS U4476 ( .A0(n4574), .A1(intadd_478_CI), .B0(n3815), .Y(n1953) );
OAI31X1TS U4477 ( .A0(n5452), .A1(FPSENCOS_cont_iter_out[3]), .A2(n4466),
.B0(n3818), .Y(n2129) );
INVX2TS U4478 ( .A(n3821), .Y(n4457) );
AOI32X1TS U4479 ( .A0(n5452), .A1(n3744), .A2(n4457), .B0(
FPSENCOS_d_ff3_LUT_out[23]), .B1(n4506), .Y(n3819) );
OAI21XLTS U4480 ( .A0(n4457), .A1(n4464), .B0(n3819), .Y(n2119) );
NAND3X1TS U4481 ( .A(FPSENCOS_cont_var_out[1]), .B(ready_add_subt), .C(n5363), .Y(n4568) );
NOR2XLTS U4482 ( .A(n4420), .B(n4473), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
AOI211X1TS U4483 ( .A0(n5452), .A1(n5213), .B0(n4463), .C0(n4466), .Y(n4454)
);
AOI21X1TS U4484 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n4506), .B0(n4454),
.Y(n3822) );
OAI21XLTS U4485 ( .A0(n2260), .A1(n4460), .B0(n3822), .Y(n2135) );
INVX2TS U4486 ( .A(n4460), .Y(n4452) );
NAND2X1TS U4487 ( .A(n4452), .B(n4457), .Y(n4458) );
OAI2BB1X1TS U4488 ( .A0N(n4456), .A1N(n3827), .B0(n2214), .Y(n4445) );
OAI211XLTS U4489 ( .A0(n3744), .A1(n5432), .B0(n4458), .C0(n4445), .Y(n2122)
);
INVX2TS U4490 ( .A(n4466), .Y(n4447) );
NAND2X1TS U4491 ( .A(n5452), .B(n4457), .Y(n3823) );
AOI22X1TS U4492 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n4506), .B0(n4447),
.B1(n3823), .Y(n3824) );
OAI21XLTS U4493 ( .A0(n5525), .A1(n4458), .B0(n3824), .Y(n2118) );
AOI22X1TS U4494 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n4506), .B0(n4447),
.B1(n3825), .Y(n3826) );
NAND2X1TS U4495 ( .A(n4447), .B(n4457), .Y(n3828) );
OAI211XLTS U4496 ( .A0(n3744), .A1(n5431), .B0(n3828), .C0(n4445), .Y(n2132)
);
NAND2X1TS U4497 ( .A(n4452), .B(n4449), .Y(n4455) );
OAI211XLTS U4498 ( .A0(n3744), .A1(n5430), .B0(n4455), .C0(n3828), .Y(n2126)
);
XNOR2X1TS U4499 ( .A(DP_OP_26J210_123_9022_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n3838) );
NOR2XLTS U4500 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n3830) );
INVX2TS U4501 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n4388) );
INVX2TS U4502 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n3829) );
NAND4BXLTS U4503 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n3830), .C(n4388),
.D(n3829), .Y(n3831) );
NOR2XLTS U4504 ( .A(n3831), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n3832) );
NOR2BX1TS U4505 ( .AN(n3832), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n3833)
);
NOR2BX1TS U4506 ( .AN(n3833), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n3834)
);
NAND2BX1TS U4507 ( .AN(n3838), .B(n3834), .Y(n4850) );
AND3X1TS U4508 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[3]), .C(n3835), .Y(n3836) );
NAND4XLTS U4509 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[6]), .D(
n3836), .Y(n3837) );
NOR2BX1TS U4510 ( .AN(n3838), .B(n3837), .Y(n3839) );
NOR2X2TS U4511 ( .A(n3839), .B(n5514), .Y(n4851) );
OAI21XLTS U4512 ( .A0(n3840), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n4851),
.Y(n3841) );
OAI21XLTS U4513 ( .A0(n2299), .A1(n5219), .B0(n3841), .Y(n1358) );
NOR2XLTS U4514 ( .A(n5245), .B(n5367), .Y(FPMULT_S_Oper_A_exp[8]) );
NOR2X1TS U4515 ( .A(n5365), .B(FPADDSUB_intDX_EWSW[25]), .Y(n3901) );
NOR2XLTS U4516 ( .A(n3901), .B(FPADDSUB_intDY_EWSW[24]), .Y(n3842) );
AOI22X1TS U4517 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n5365), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n3842), .Y(n3846) );
NAND2BXLTS U4518 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n3843) );
OAI21X1TS U4519 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n5364), .B0(n3843), .Y(
n3902) );
NAND3XLTS U4520 ( .A(n5364), .B(n3843), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n3845) );
OAI211XLTS U4521 ( .A0(n3846), .A1(n3902), .B0(n3845), .C0(n3844), .Y(n3851)
);
NOR2X1TS U4522 ( .A(n5228), .B(FPADDSUB_intDX_EWSW[30]), .Y(n3849) );
NOR2X1TS U4523 ( .A(n5323), .B(FPADDSUB_intDX_EWSW[29]), .Y(n3847) );
AOI211X1TS U4524 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n5353), .B0(n3849),
.C0(n3847), .Y(n3900) );
NOR3X1TS U4525 ( .A(n5353), .B(n3847), .C(FPADDSUB_intDY_EWSW[28]), .Y(n3848) );
AOI221X1TS U4526 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n5228), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n5323), .C0(n3848), .Y(n3850) );
AOI2BB2X1TS U4527 ( .B0(n3851), .B1(n3900), .A0N(n3850), .A1N(n3849), .Y(
n3906) );
NOR2X1TS U4528 ( .A(n5310), .B(FPADDSUB_intDX_EWSW[17]), .Y(n3887) );
NAND2BXLTS U4529 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n3868) );
NOR2X1TS U4530 ( .A(n5309), .B(FPADDSUB_intDX_EWSW[11]), .Y(n3866) );
AOI21X1TS U4531 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n5335), .B0(n3866), .Y(
n3871) );
OAI211XLTS U4532 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n5320), .B0(n3868), .C0(
n3871), .Y(n3882) );
OAI2BB1X1TS U4533 ( .A0N(n5348), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n3852) );
OAI22X1TS U4534 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3852), .B0(n5348), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n3863) );
OAI2BB1X1TS U4535 ( .A0N(n5355), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n3853) );
OAI22X1TS U4536 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3853), .B0(n5355), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n3862) );
OAI21XLTS U4537 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n5285), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n3854) );
OAI2BB2XLTS U4538 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n3854), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n5285), .Y(n3856) );
NAND2BXLTS U4539 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n3855) );
OAI211XLTS U4540 ( .A0(n5281), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n3856), .C0(
n3855), .Y(n3859) );
AOI2BB2XLTS U4541 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n5281), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n3857), .Y(n3858) );
AOI22X1TS U4542 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n5355), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n5233), .Y(n3860) );
OAI32X1TS U4543 ( .A0(n3863), .A1(n3862), .A2(n3861), .B0(n3860), .B1(n3862),
.Y(n3881) );
OA22X1TS U4544 ( .A0(n5276), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n5218), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n3878) );
NAND2BXLTS U4545 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n3864) );
OAI2BB2XLTS U4546 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n3865), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n5284), .Y(n3877) );
NOR2XLTS U4547 ( .A(n3866), .B(FPADDSUB_intDY_EWSW[10]), .Y(n3867) );
AOI22X1TS U4548 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n5309), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n3867), .Y(n3873) );
NAND3XLTS U4549 ( .A(n5320), .B(n3868), .C(FPADDSUB_intDX_EWSW[8]), .Y(n3869) );
AOI21X1TS U4550 ( .A0(n3870), .A1(n3869), .B0(n3880), .Y(n3872) );
OAI2BB2XLTS U4551 ( .B0(n3873), .B1(n3880), .A0N(n3872), .A1N(n3871), .Y(
n3876) );
OAI21XLTS U4552 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n5218), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n3874) );
OAI2BB2XLTS U4553 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n3874), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n5218), .Y(n3875) );
AOI211X1TS U4554 ( .A0(n3878), .A1(n3877), .B0(n3876), .C0(n3875), .Y(n3879)
);
OAI31X1TS U4555 ( .A0(n3882), .A1(n3881), .A2(n3880), .B0(n3879), .Y(n3885)
);
OA22X1TS U4556 ( .A0(n5282), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n5223), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n3898) );
NAND2BXLTS U4557 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n3883) );
NAND2BXLTS U4558 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n3889) );
OAI21X1TS U4559 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n5321), .B0(n3889), .Y(
n3893) );
NAND3BXLTS U4560 ( .AN(n3887), .B(n3885), .C(n3884), .Y(n3905) );
OAI21XLTS U4561 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n5317), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n3886) );
OAI2BB2XLTS U4562 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n3886), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n5317), .Y(n3897) );
NOR2XLTS U4563 ( .A(n3887), .B(FPADDSUB_intDY_EWSW[16]), .Y(n3888) );
AOI22X1TS U4564 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n5310), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n3888), .Y(n3891) );
AOI32X1TS U4565 ( .A0(n5321), .A1(n3889), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n5226), .Y(n3890) );
OAI32X1TS U4566 ( .A0(n3893), .A1(n3892), .A2(n3891), .B0(n3890), .B1(n3892),
.Y(n3896) );
OAI21XLTS U4567 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n5223), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n3894) );
OAI2BB2XLTS U4568 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n3894), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n5223), .Y(n3895) );
AOI211X1TS U4569 ( .A0(n3898), .A1(n3897), .B0(n3896), .C0(n3895), .Y(n3904)
);
NAND2BXLTS U4570 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n3899) );
NAND4BBX1TS U4571 ( .AN(n3902), .BN(n3901), .C(n3900), .D(n3899), .Y(n3903)
);
CLKAND2X2TS U4572 ( .A(n4953), .B(n4950), .Y(n3958) );
AOI22X1TS U4573 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n2312), .Y(n3908) );
NAND4XLTS U4574 ( .A(n5314), .B(n5525), .C(n5213), .D(n4441), .Y(n3910) );
NAND2X1TS U4575 ( .A(n3910), .B(n2213), .Y(n3909) );
NOR2X1TS U4576 ( .A(n4494), .B(n3910), .Y(n3913) );
INVX2TS U4577 ( .A(n3911), .Y(n1759) );
INVX2TS U4578 ( .A(n3912), .Y(n1761) );
INVX2TS U4579 ( .A(n3914), .Y(n1762) );
INVX2TS U4580 ( .A(n3915), .Y(n1763) );
INVX2TS U4581 ( .A(n3916), .Y(n1760) );
INVX2TS U4582 ( .A(n3917), .Y(n1764) );
AOI22X1TS U4583 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n2312), .Y(n3918) );
OAI21XLTS U4584 ( .A0(n5344), .A1(n4835), .B0(n3918), .Y(n1215) );
AOI22X1TS U4585 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n2312), .Y(n3919) );
OAI21XLTS U4586 ( .A0(n5237), .A1(n4835), .B0(n3919), .Y(n1219) );
AOI22X1TS U4587 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n2312), .Y(n3920) );
BUFX4TS U4588 ( .A(n4488), .Y(n4487) );
INVX2TS U4589 ( .A(n3921), .Y(n1742) );
INVX2TS U4590 ( .A(n3922), .Y(n1749) );
INVX2TS U4591 ( .A(n3923), .Y(n1743) );
INVX2TS U4592 ( .A(n3924), .Y(n1751) );
INVX2TS U4593 ( .A(n3925), .Y(n1757) );
INVX2TS U4594 ( .A(n3926), .Y(n1746) );
INVX2TS U4595 ( .A(n3927), .Y(n1744) );
INVX2TS U4596 ( .A(n3928), .Y(n1745) );
INVX2TS U4597 ( .A(n3929), .Y(n1765) );
INVX2TS U4598 ( .A(n3930), .Y(n1750) );
INVX2TS U4599 ( .A(n3931), .Y(n1748) );
AOI222X1TS U4600 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n3935), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n3932) );
INVX2TS U4601 ( .A(n3932), .Y(n1753) );
INVX2TS U4602 ( .A(n3933), .Y(n1752) );
INVX2TS U4603 ( .A(n3934), .Y(n1747) );
INVX2TS U4604 ( .A(n3936), .Y(n1741) );
INVX2TS U4605 ( .A(n3938), .Y(n1766) );
INVX2TS U4606 ( .A(n3939), .Y(n1736) );
AOI222X1TS U4607 ( .A0(n4477), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n4489), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n3937), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n3940) );
INVX2TS U4608 ( .A(n3940), .Y(n1755) );
INVX2TS U4609 ( .A(n3941), .Y(n1758) );
INVX2TS U4610 ( .A(n3942), .Y(n1735) );
INVX2TS U4611 ( .A(n3943), .Y(n1754) );
INVX2TS U4612 ( .A(n3944), .Y(n1738) );
INVX2TS U4613 ( .A(n3945), .Y(n1756) );
INVX2TS U4614 ( .A(n3946), .Y(n1740) );
INVX2TS U4615 ( .A(n3947), .Y(n1737) );
INVX2TS U4616 ( .A(n3948), .Y(n1739) );
BUFX4TS U4617 ( .A(n2312), .Y(n4050) );
AOI22X1TS U4618 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n4050), .Y(n3949) );
OAI21XLTS U4619 ( .A0(n5352), .A1(n4835), .B0(n3949), .Y(n1461) );
AOI22X1TS U4620 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n4050), .Y(n3950) );
OAI21XLTS U4621 ( .A0(n5240), .A1(n3974), .B0(n3950), .Y(n1460) );
AOI22X1TS U4622 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n2312), .Y(n3951) );
OAI21XLTS U4623 ( .A0(n5334), .A1(n4835), .B0(n3951), .Y(n1227) );
AOI22X1TS U4624 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n2312), .Y(n3952) );
OAI21XLTS U4625 ( .A0(n5343), .A1(n4835), .B0(n3952), .Y(n1223) );
AOI22X1TS U4626 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n4038), .Y(n3953) );
OAI21XLTS U4627 ( .A0(n5232), .A1(n3974), .B0(n3953), .Y(n1328) );
AOI222X1TS U4628 ( .A0(n3907), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DMP_EXP_EWSW[23]), .B1(n4038), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3958), .Y(n3954) );
INVX2TS U4629 ( .A(n3954), .Y(n1467) );
AOI22X1TS U4630 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n4050), .Y(n3955) );
OAI21XLTS U4631 ( .A0(n5353), .A1(n4835), .B0(n3955), .Y(n1462) );
AOI22X1TS U4632 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[27]), .B1(n4038), .Y(n3956) );
OAI21XLTS U4633 ( .A0(n5337), .A1(n4835), .B0(n3956), .Y(n1463) );
AOI22X1TS U4634 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3907), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n4050), .Y(n3957) );
OAI21XLTS U4635 ( .A0(n5333), .A1(n3974), .B0(n3957), .Y(n1312) );
INVX2TS U4636 ( .A(n3959), .Y(n1419) );
BUFX4TS U4637 ( .A(n3907), .Y(n4042) );
AOI22X1TS U4638 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n2312), .Y(n3960) );
OAI21XLTS U4639 ( .A0(n5341), .A1(n4835), .B0(n3960), .Y(n1235) );
AOI22X1TS U4640 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n4038), .Y(n3961) );
OAI21XLTS U4641 ( .A0(n5338), .A1(n3974), .B0(n3961), .Y(n1291) );
AOI22X1TS U4642 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n4038), .Y(n3962) );
OAI21XLTS U4643 ( .A0(n5340), .A1(n3974), .B0(n3962), .Y(n1259) );
AOI22X1TS U4644 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n4038), .Y(n3963) );
OAI21XLTS U4645 ( .A0(n5235), .A1(n3974), .B0(n3963), .Y(n1271) );
AOI22X1TS U4646 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n4038), .Y(n3964) );
OAI21XLTS U4647 ( .A0(n5238), .A1(n3974), .B0(n3964), .Y(n1211) );
AOI22X1TS U4648 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n2312), .Y(n3965) );
OAI21XLTS U4649 ( .A0(n5332), .A1(n3974), .B0(n3965), .Y(n1255) );
AOI22X1TS U4650 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n4038), .Y(n3966) );
OAI21XLTS U4651 ( .A0(n5236), .A1(n3974), .B0(n3966), .Y(n1263) );
AOI22X1TS U4652 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n4038), .Y(n3967) );
OAI21XLTS U4653 ( .A0(n5349), .A1(n3974), .B0(n3967), .Y(n1298) );
AOI22X1TS U4654 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n4038), .Y(n3968) );
OAI21XLTS U4655 ( .A0(n5339), .A1(n3974), .B0(n3968), .Y(n1284) );
AOI22X1TS U4656 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n4038), .Y(n3969) );
OAI21XLTS U4657 ( .A0(n5335), .A1(n3974), .B0(n3969), .Y(n1267) );
AOI22X1TS U4658 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n2312), .Y(n3970) );
OAI21XLTS U4659 ( .A0(n5336), .A1(n3974), .B0(n3970), .Y(n1251) );
AOI22X1TS U4660 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n2312), .Y(n3971) );
OAI21XLTS U4661 ( .A0(n5234), .A1(n3974), .B0(n3971), .Y(n1239) );
AOI22X1TS U4662 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n2312), .Y(n3972) );
OAI21XLTS U4663 ( .A0(n5233), .A1(n3974), .B0(n3972), .Y(n1243) );
AOI22X1TS U4664 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n4042), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n4038), .Y(n3973) );
OAI21XLTS U4665 ( .A0(n5348), .A1(n3974), .B0(n3973), .Y(n1277) );
AOI22X1TS U4666 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n4038), .Y(n3975) );
OAI21XLTS U4667 ( .A0(n5348), .A1(n4834), .B0(n3975), .Y(n1279) );
AOI22X1TS U4668 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n4038), .Y(n3976) );
OAI21XLTS U4669 ( .A0(n5235), .A1(n4834), .B0(n3976), .Y(n1273) );
AOI22X1TS U4670 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n4038), .Y(n3977) );
OAI21XLTS U4671 ( .A0(n5349), .A1(n2208), .B0(n3977), .Y(n1300) );
AOI22X1TS U4672 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3958), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n4038), .Y(n3978) );
OAI21XLTS U4673 ( .A0(n5338), .A1(n4834), .B0(n3978), .Y(n1293) );
AOI22X1TS U4674 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n3958), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n4038), .Y(n3979) );
OAI21XLTS U4675 ( .A0(n5339), .A1(n4834), .B0(n3979), .Y(n1286) );
XNOR2X1TS U4676 ( .A(n3985), .B(FPSENCOS_d_ff_Xn[31]), .Y(n3988) );
INVX2TS U4677 ( .A(n3980), .Y(n4433) );
BUFX4TS U4678 ( .A(n4018), .Y(n4022) );
XNOR2X1TS U4679 ( .A(FPSENCOS_d_ff1_operation_out), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n3982) );
XNOR2X1TS U4680 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n3982),
.Y(n3983) );
OR2X1TS U4681 ( .A(n4022), .B(n3983), .Y(n3996) );
BUFX3TS U4682 ( .A(n4018), .Y(n4026) );
AOI22X1TS U4683 ( .A0(n4022), .A1(cordic_result[31]), .B0(n4025), .B1(n3986),
.Y(n3987) );
OAI21XLTS U4684 ( .A0(n3988), .A1(n3996), .B0(n3987), .Y(n1697) );
INVX4TS U4685 ( .A(n3996), .Y(n4013) );
INVX2TS U4686 ( .A(n3989), .Y(n1704) );
INVX2TS U4687 ( .A(n3990), .Y(n1706) );
INVX2TS U4688 ( .A(n3991), .Y(n1708) );
INVX2TS U4689 ( .A(n3992), .Y(n1707) );
INVX2TS U4690 ( .A(n3993), .Y(n1709) );
INVX2TS U4691 ( .A(n3994), .Y(n1703) );
INVX2TS U4692 ( .A(n3995), .Y(n1705) );
INVX4TS U4693 ( .A(n3996), .Y(n4024) );
INVX2TS U4694 ( .A(n3997), .Y(n1725) );
INVX2TS U4695 ( .A(n3998), .Y(n1702) );
INVX2TS U4696 ( .A(n3999), .Y(n1699) );
INVX2TS U4697 ( .A(n4000), .Y(n1700) );
INVX2TS U4698 ( .A(n4001), .Y(n1701) );
INVX2TS U4699 ( .A(n4002), .Y(n1698) );
INVX2TS U4700 ( .A(n4003), .Y(n1724) );
INVX2TS U4701 ( .A(n4005), .Y(n1727) );
INVX2TS U4702 ( .A(n4006), .Y(n1723) );
BUFX3TS U4703 ( .A(n3984), .Y(n4025) );
INVX2TS U4704 ( .A(n4007), .Y(n1710) );
INVX2TS U4705 ( .A(n4008), .Y(n1714) );
INVX2TS U4706 ( .A(n4009), .Y(n1713) );
INVX2TS U4707 ( .A(n4010), .Y(n1711) );
INVX2TS U4708 ( .A(n4011), .Y(n1716) );
INVX2TS U4709 ( .A(n4012), .Y(n1712) );
INVX2TS U4710 ( .A(n4014), .Y(n1715) );
INVX2TS U4711 ( .A(n4015), .Y(n1720) );
INVX2TS U4712 ( .A(n4016), .Y(n1719) );
INVX2TS U4713 ( .A(n4017), .Y(n1728) );
INVX2TS U4714 ( .A(n4019), .Y(n1718) );
INVX2TS U4715 ( .A(n4020), .Y(n1726) );
INVX2TS U4716 ( .A(n4021), .Y(n1722) );
INVX2TS U4717 ( .A(n4023), .Y(n1717) );
INVX2TS U4718 ( .A(n4027), .Y(n1721) );
AOI22X1TS U4719 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n4038), .Y(n4028) );
OAI21XLTS U4720 ( .A0(n5355), .A1(n2208), .B0(n4028), .Y(n1307) );
AOI22X1TS U4721 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n4038), .Y(n4029) );
OAI21XLTS U4722 ( .A0(n5342), .A1(n2208), .B0(n4029), .Y(n1382) );
AOI22X1TS U4723 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n4050), .Y(n4030) );
OAI21XLTS U4724 ( .A0(n5335), .A1(n2208), .B0(n4030), .Y(n1367) );
AOI22X1TS U4725 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n4050), .Y(n4031) );
OAI21XLTS U4726 ( .A0(n5341), .A1(n2208), .B0(n4031), .Y(n1391) );
AOI22X1TS U4727 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n4048), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n4038), .Y(n4032) );
OAI21XLTS U4728 ( .A0(n5346), .A1(n2208), .B0(n4032), .Y(n1305) );
AOI22X1TS U4729 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n4038), .Y(n4033) );
OAI21XLTS U4730 ( .A0(n5336), .A1(n2208), .B0(n4033), .Y(n1379) );
AOI22X1TS U4731 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n4050), .Y(n4034) );
OAI21XLTS U4732 ( .A0(n5234), .A1(n2208), .B0(n4034), .Y(n1388) );
AOI22X1TS U4733 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n4050), .Y(n4035) );
OAI21XLTS U4734 ( .A0(n5333), .A1(n2208), .B0(n4035), .Y(n1314) );
AOI22X1TS U4735 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n4038), .Y(n4036) );
OAI21XLTS U4736 ( .A0(n5236), .A1(n2208), .B0(n4036), .Y(n1370) );
AOI22X1TS U4737 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n4038), .Y(n4037) );
OAI21XLTS U4738 ( .A0(n5332), .A1(n4834), .B0(n4037), .Y(n1376) );
AOI22X1TS U4739 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n4038), .Y(n4039) );
OAI21XLTS U4740 ( .A0(n5340), .A1(n4834), .B0(n4039), .Y(n1373) );
AOI22X1TS U4741 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n4050), .Y(n4040) );
OAI21XLTS U4742 ( .A0(n5233), .A1(n2208), .B0(n4040), .Y(n1385) );
AOI22X1TS U4743 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n4050), .Y(n4041) );
OAI21XLTS U4744 ( .A0(n5232), .A1(n4834), .B0(n4041), .Y(n1330) );
AOI22X1TS U4745 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n4050), .Y(n4043) );
OAI21XLTS U4746 ( .A0(n5237), .A1(n4834), .B0(n4043), .Y(n1403) );
AOI22X1TS U4747 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n4050), .Y(n4044) );
OAI21XLTS U4748 ( .A0(n5231), .A1(n4834), .B0(n4044), .Y(n1394) );
AOI22X1TS U4749 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n4050), .Y(n4045) );
OAI21XLTS U4750 ( .A0(n5337), .A1(n2208), .B0(n4045), .Y(n1415) );
AOI22X1TS U4751 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n4050), .Y(n4046) );
AOI22X1TS U4752 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n4050), .Y(n4047) );
OAI21XLTS U4753 ( .A0(n5344), .A1(n4834), .B0(n4047), .Y(n1406) );
AOI22X1TS U4754 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n4050), .Y(n4049) );
OAI21XLTS U4755 ( .A0(n5334), .A1(n4834), .B0(n4049), .Y(n1397) );
AOI22X1TS U4756 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n4048), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n4050), .Y(n4051) );
OAI21XLTS U4757 ( .A0(n5343), .A1(n2208), .B0(n4051), .Y(n1400) );
NAND4XLTS U4758 ( .A(n2222), .B(n5263), .C(n5187), .D(n5180), .Y(n4055) );
OR4X2TS U4759 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .D(
n4055), .Y(n4097) );
NOR2X1TS U4760 ( .A(n4097), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4065) );
NAND4XLTS U4761 ( .A(n5188), .B(n5181), .C(n5266), .D(n4065), .Y(n4062) );
OR2X1TS U4762 ( .A(n4062), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n4054) );
INVX2TS U4763 ( .A(n4104), .Y(n4068) );
NAND2X1TS U4764 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n4100), .Y(n4066) );
OAI22X1TS U4765 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n4066), .B0(n5315),
.B1(n4097), .Y(n4105) );
AOI32X1TS U4766 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n5192), .A2(n5222),
.B0(FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n5192), .Y(n4052) );
NOR3BX1TS U4767 ( .AN(n4100), .B(FPADDSUB_Raw_mant_NRM_SWR[12]), .C(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n4078) );
NAND2X1TS U4768 ( .A(n4099), .B(n5193), .Y(n4056) );
AOI211X1TS U4769 ( .A0(n5194), .A1(n4052), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C0(n4056), .Y(n4053) );
AOI211X1TS U4770 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n4104), .B0(n4105), .C0(n4053), .Y(n4102) );
AOI21X1TS U4771 ( .A0(n5203), .A1(n5184), .B0(n4054), .Y(n4063) );
NAND2X1TS U4772 ( .A(n5195), .B(n5316), .Y(n4106) );
AOI2BB1XLTS U4773 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1N(n4106), .B0(
n4055), .Y(n4058) );
INVX2TS U4774 ( .A(n4056), .Y(n4082) );
OAI22X1TS U4775 ( .A0(n5220), .A1(n4056), .B0(n4079), .B1(n5192), .Y(n4057)
);
NOR4BX1TS U4776 ( .AN(n4102), .B(n4063), .C(n4058), .D(n4057), .Y(n4061) );
AOI32X1TS U4777 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n4556), .A2(
n4437), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n4160), .Y(n4059)
);
OAI21XLTS U4778 ( .A0(n2235), .A1(n4083), .B0(n4059), .Y(n2079) );
NAND2X1TS U4779 ( .A(n4437), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n4060)
);
OAI21XLTS U4780 ( .A0(n4437), .A1(n2235), .B0(n4060), .Y(n1320) );
INVX2TS U4781 ( .A(n4079), .Y(n4070) );
NOR2X1TS U4782 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4076) );
NAND3XLTS U4783 ( .A(n5188), .B(n5181), .C(n5266), .Y(n4064) );
OAI211XLTS U4784 ( .A0(n4068), .A1(n5196), .B0(n4067), .C0(n4066), .Y(n4069)
);
AOI31X1TS U4785 ( .A0(n4070), .A1(n4076), .A2(FPADDSUB_Raw_mant_NRM_SWR[1]),
.B0(n4069), .Y(n4073) );
OAI21XLTS U4786 ( .A0(n4073), .A1(n4083), .B0(n4071), .Y(n2078) );
NAND2X1TS U4787 ( .A(n4437), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n4072)
);
OAI21XLTS U4788 ( .A0(n4073), .A1(n4437), .B0(n4072), .Y(n1324) );
AO21XLTS U4789 ( .A0(n5193), .A1(n5227), .B0(n4074), .Y(n4075) );
OAI21X1TS U4790 ( .A0(n4076), .A1(n4079), .B0(n4075), .Y(n4108) );
NAND2X1TS U4791 ( .A(n5214), .B(n5191), .Y(n4077) );
AOI22X1TS U4792 ( .A0(n4099), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n4078),
.B1(n4077), .Y(n4080) );
AOI32X1TS U4793 ( .A0(n5222), .A1(n4080), .A2(n5354), .B0(n4079), .B1(n4080),
.Y(n4081) );
AOI211X1TS U4794 ( .A0(n4082), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n4108),
.C0(n4081), .Y(n4086) );
OAI21XLTS U4795 ( .A0(n4086), .A1(n4083), .B0(n4084), .Y(n2077) );
NAND2X1TS U4796 ( .A(n4437), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n4085)
);
OAI21XLTS U4797 ( .A0(n4086), .A1(n4437), .B0(n4085), .Y(n1332) );
NAND3X1TS U4798 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n4087),
.C(n5224), .Y(n4413) );
OAI31X1TS U4799 ( .A0(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .A1(n5221),
.A2(n4415), .B0(n4413), .Y(n4471) );
INVX2TS U4800 ( .A(operation[0]), .Y(n4088) );
INVX2TS U4801 ( .A(operation[1]), .Y(n4332) );
OAI32X1TS U4802 ( .A0(n4468), .A1(n4088), .A2(n4332), .B0(n5201), .B1(n4467),
.Y(n2082) );
OAI221XLTS U4803 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(
FPMULT_FS_Module_state_reg[1]), .B0(n5274), .B1(n5190), .C0(n5182),
.Y(n4089) );
OAI211XLTS U4804 ( .A0(n4091), .A1(n4090), .B0(n4089), .C0(n4585), .Y(n1693)
);
NAND2X1TS U4805 ( .A(n4420), .B(n4419), .Y(n4092) );
AOI22X1TS U4806 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n5278), .B0(n4223), .B1(n5189), .Y(n4093) );
NAND3XLTS U4807 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n5189),
.C(n5217), .Y(n4422) );
AOI222X4TS U4808 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(n2203), .B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .C0(FPADDSUB_Raw_mant_NRM_SWR[24]), .C1(
n4094), .Y(n4214) );
OAI32X1TS U4809 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n5316), .B0(n5180), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4095) );
OAI21XLTS U4810 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n4095), .B0(n2222),
.Y(n4096) );
OAI31X1TS U4811 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n5181), .A2(n4097),
.B0(n4096), .Y(n4098) );
NAND3XLTS U4812 ( .A(n4100), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n5214),
.Y(n4101) );
INVX2TS U4813 ( .A(n4212), .Y(n4118) );
NAND2X1TS U4814 ( .A(n4104), .B(n5196), .Y(n4114) );
INVX2TS U4815 ( .A(n4105), .Y(n4113) );
NOR2XLTS U4816 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4111) );
AOI31XLTS U4817 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n5188), .A2(n5181),
.B0(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4107) );
OAI211XLTS U4818 ( .A0(n4107), .A1(n4106), .B0(n5187), .C0(n5180), .Y(n4110)
);
AOI211X1TS U4819 ( .A0(n4111), .A1(n4110), .B0(n4109), .C0(n4108), .Y(n4112)
);
OAI211X1TS U4820 ( .A0(n5184), .A1(n4114), .B0(n4113), .C0(n4112), .Y(n4383)
);
NAND2BX1TS U4821 ( .AN(n4117), .B(n4556), .Y(n4557) );
NOR2X1TS U4822 ( .A(n4118), .B(n4557), .Y(n4121) );
NOR2X1TS U4823 ( .A(n4557), .B(n4212), .Y(n4116) );
BUFX3TS U4824 ( .A(n4116), .Y(n4196) );
AOI22X1TS U4825 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n4196),
.B1(n4211), .Y(n4115) );
OAI21XLTS U4826 ( .A0(n4214), .A1(n4215), .B0(n4115), .Y(n1813) );
AOI222X4TS U4827 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n4094), .C0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .C1(n2203), .Y(n4146) );
NAND2X1TS U4828 ( .A(n4117), .B(n4556), .Y(n4219) );
AOI22X1TS U4829 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[21]), .A1(n2203), .B0(
FPADDSUB_DmP_mant_SHT1_SW[2]), .B1(n4437), .Y(n4120) );
AOI22X1TS U4830 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n4561),
.B1(n2233), .Y(n4125) );
BUFX3TS U4831 ( .A(n4121), .Y(n4207) );
AOI22X1TS U4832 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[2]), .A1(n4094), .B0(
FPADDSUB_DmP_mant_SHT1_SW[0]), .B1(n4954), .Y(n4122) );
AOI222X4TS U4833 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n4094), .C0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C1(n2203), .Y(n4139) );
INVX2TS U4834 ( .A(n4139), .Y(n4143) );
AOI22X1TS U4835 ( .A0(n4207), .A1(n4560), .B0(n4563), .B1(n4143), .Y(n4124)
);
OAI211XLTS U4836 ( .A0(n4146), .A1(n4213), .B0(n4125), .C0(n4124), .Y(n1791)
);
AOI22X1TS U4837 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n2203), .B0(n4094),
.B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n4566) );
INVX2TS U4838 ( .A(n4146), .Y(n4562) );
AOI22X1TS U4839 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n4561),
.B1(n4562), .Y(n4127) );
AOI22X1TS U4840 ( .A0(n4196), .A1(n4560), .B0(n4563), .B1(n2233), .Y(n4126)
);
OAI211XLTS U4841 ( .A0(n4566), .A1(n4215), .B0(n4127), .C0(n4126), .Y(n1790)
);
AOI222X4TS U4842 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n4094), .C0(
FPADDSUB_Raw_mant_NRM_SWR[18]), .C1(n2203), .Y(n4165) );
INVX2TS U4843 ( .A(n4165), .Y(n4136) );
AOI22X1TS U4844 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n4561),
.B1(n4136), .Y(n4131) );
AOI22X1TS U4845 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n2203), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n4954), .Y(n4128) );
AOI22X1TS U4846 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n2203), .B0(
FPADDSUB_DmP_mant_SHT1_SW[6]), .B1(n4437), .Y(n4129) );
AOI22X1TS U4847 ( .A0(n4196), .A1(n4156), .B0(n4563), .B1(n4162), .Y(n4130)
);
OAI211XLTS U4848 ( .A0(n4139), .A1(n4215), .B0(n4131), .C0(n4130), .Y(n1794)
);
AOI222X4TS U4849 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n4094), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n2203), .Y(n4155) );
AOI222X4TS U4850 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n4094), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n2203), .Y(n4154) );
INVX2TS U4851 ( .A(n4154), .Y(n4140) );
AOI22X1TS U4852 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n4561),
.B1(n4140), .Y(n4135) );
AOI22X1TS U4853 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n2203), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n4437), .Y(n4132) );
AOI22X1TS U4854 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n2203), .B0(
FPADDSUB_DmP_mant_SHT1_SW[10]), .B1(n4437), .Y(n4133) );
AOI22X1TS U4855 ( .A0(n4196), .A1(n4161), .B0(n4563), .B1(n4179), .Y(n4134)
);
OAI211XLTS U4856 ( .A0(n4155), .A1(n4215), .B0(n4135), .C0(n4134), .Y(n1798)
);
AOI22X1TS U4857 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n4561),
.B1(n4156), .Y(n4138) );
AOI22X1TS U4858 ( .A0(n4207), .A1(n2233), .B0(n4563), .B1(n4136), .Y(n4137)
);
OAI211XLTS U4859 ( .A0(n4139), .A1(n4213), .B0(n4138), .C0(n4137), .Y(n1793)
);
AOI22X1TS U4860 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n4561),
.B1(n4161), .Y(n4142) );
AOI22X1TS U4861 ( .A0(n4207), .A1(n4162), .B0(n4563), .B1(n4140), .Y(n4141)
);
AOI22X1TS U4862 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n4561),
.B1(n4143), .Y(n4145) );
AOI22X1TS U4863 ( .A0(n4196), .A1(n2233), .B0(n4563), .B1(n4156), .Y(n4144)
);
OAI211XLTS U4864 ( .A0(n4146), .A1(n4215), .B0(n4145), .C0(n4144), .Y(n1792)
);
AOI22X1TS U4865 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n4561),
.B1(n4179), .Y(n4148) );
AOI222X4TS U4866 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n2203), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n4094), .Y(n4187) );
INVX2TS U4867 ( .A(n4187), .Y(n4150) );
AOI22X1TS U4868 ( .A0(n4207), .A1(n4161), .B0(n4563), .B1(n4150), .Y(n4147)
);
OAI211XLTS U4869 ( .A0(n4154), .A1(n4213), .B0(n4148), .C0(n4147), .Y(n1799)
);
AOI22X1TS U4870 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n4561),
.B1(n4150), .Y(n4153) );
AOI22X1TS U4871 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n2203), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n4437), .Y(n4151) );
AOI22X1TS U4872 ( .A0(n4196), .A1(n4179), .B0(n4563), .B1(n4188), .Y(n4152)
);
OAI211XLTS U4873 ( .A0(n4154), .A1(n4215), .B0(n4153), .C0(n4152), .Y(n1800)
);
AOI22X1TS U4874 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n4561),
.B1(n4162), .Y(n4158) );
INVX2TS U4875 ( .A(n4155), .Y(n4159) );
AOI22X1TS U4876 ( .A0(n4207), .A1(n4156), .B0(n4563), .B1(n4159), .Y(n4157)
);
OAI211XLTS U4877 ( .A0(n4165), .A1(n4213), .B0(n4158), .C0(n4157), .Y(n1795)
);
AOI22X1TS U4878 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n4561),
.B1(n4159), .Y(n4164) );
AOI22X1TS U4879 ( .A0(n4196), .A1(n4162), .B0(n4563), .B1(n4161), .Y(n4163)
);
OAI211XLTS U4880 ( .A0(n4165), .A1(n4215), .B0(n4164), .C0(n4163), .Y(n1796)
);
AOI222X4TS U4881 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[4]), .B1(n2203), .C0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .C1(n4094), .Y(n4176) );
AOI222X4TS U4882 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n2203), .C0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .C1(n4094), .Y(n4216) );
INVX2TS U4883 ( .A(n4216), .Y(n4170) );
AOI22X1TS U4884 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n4561),
.B1(n4170), .Y(n4168) );
AOI22X1TS U4885 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[22]), .A1(n4094), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n4954), .Y(n4166) );
INVX2TS U4886 ( .A(n4214), .Y(n4208) );
AOI22X1TS U4887 ( .A0(n4196), .A1(n4206), .B0(n4563), .B1(n4208), .Y(n4167)
);
OAI211XLTS U4888 ( .A0(n4176), .A1(n4215), .B0(n4168), .C0(n4167), .Y(n1810)
);
AOI22X1TS U4889 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n4561),
.B1(n4206), .Y(n4172) );
AOI22X1TS U4890 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[20]), .A1(n4094), .B0(
FPADDSUB_DmP_mant_SHT1_SW[18]), .B1(n4954), .Y(n4169) );
AOI22X1TS U4891 ( .A0(n4207), .A1(n2234), .B0(n4563), .B1(n4170), .Y(n4171)
);
OAI211XLTS U4892 ( .A0(n4176), .A1(n4213), .B0(n4172), .C0(n4171), .Y(n1809)
);
AOI222X4TS U4893 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n2203), .C0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n4094), .Y(n4205) );
AOI222X4TS U4894 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n2203), .C0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .C1(n4094), .Y(n4194) );
INVX2TS U4895 ( .A(n4194), .Y(n4201) );
AOI22X1TS U4896 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n4561),
.B1(n4201), .Y(n4175) );
AOI22X1TS U4897 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n2203), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n4954), .Y(n4173) );
AOI22X1TS U4898 ( .A0(n4196), .A1(n4200), .B0(n4563), .B1(n2234), .Y(n4174)
);
OAI211XLTS U4899 ( .A0(n4205), .A1(n4215), .B0(n4175), .C0(n4174), .Y(n1806)
);
AOI22X1TS U4900 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n4561),
.B1(n2234), .Y(n4178) );
INVX2TS U4901 ( .A(n4176), .Y(n4191) );
AOI22X1TS U4902 ( .A0(n4207), .A1(n4200), .B0(n4563), .B1(n4191), .Y(n4177)
);
OAI211XLTS U4903 ( .A0(n4194), .A1(n4213), .B0(n4178), .C0(n4177), .Y(n1807)
);
AOI22X1TS U4904 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n4561),
.B1(n4188), .Y(n4181) );
AOI222X4TS U4905 ( .A0(n4954), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n2203), .C0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n4094), .Y(n4199) );
INVX2TS U4906 ( .A(n4199), .Y(n4182) );
AOI22X1TS U4907 ( .A0(n4207), .A1(n4179), .B0(n4563), .B1(n4182), .Y(n4180)
);
AOI22X1TS U4908 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n4561),
.B1(n4182), .Y(n4186) );
AOI22X1TS U4909 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n2203), .B0(
FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(n4437), .Y(n4183) );
AOI22X1TS U4910 ( .A0(n4196), .A1(n4188), .B0(n4563), .B1(n4202), .Y(n4185)
);
OAI211XLTS U4911 ( .A0(n4187), .A1(n4215), .B0(n4186), .C0(n4185), .Y(n1802)
);
AOI22X1TS U4912 ( .A0(n4149), .A1(n2252), .B0(n4561), .B1(n4202), .Y(n4190)
);
INVX2TS U4913 ( .A(n4205), .Y(n4195) );
AOI22X1TS U4914 ( .A0(n4207), .A1(n4188), .B0(n4563), .B1(n4195), .Y(n4189)
);
OAI211XLTS U4915 ( .A0(n4199), .A1(n4213), .B0(n4190), .C0(n4189), .Y(n1803)
);
AOI22X1TS U4916 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n4561),
.B1(n4191), .Y(n4193) );
AOI22X1TS U4917 ( .A0(n4196), .A1(n2234), .B0(n4563), .B1(n4206), .Y(n4192)
);
OAI211XLTS U4918 ( .A0(n4194), .A1(n4215), .B0(n4193), .C0(n4192), .Y(n1808)
);
AOI22X1TS U4919 ( .A0(n4149), .A1(n2251), .B0(n4561), .B1(n4195), .Y(n4198)
);
AOI22X1TS U4920 ( .A0(n4196), .A1(n4202), .B0(n4563), .B1(n4200), .Y(n4197)
);
OAI211XLTS U4921 ( .A0(n4199), .A1(n4215), .B0(n4198), .C0(n4197), .Y(n1804)
);
AOI22X1TS U4922 ( .A0(n4160), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n4561),
.B1(n4200), .Y(n4204) );
AOI22X1TS U4923 ( .A0(n4207), .A1(n4202), .B0(n4563), .B1(n4201), .Y(n4203)
);
OAI211XLTS U4924 ( .A0(n4205), .A1(n4213), .B0(n4204), .C0(n4203), .Y(n1805)
);
AOI22X1TS U4925 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n4207),
.B1(n4206), .Y(n4210) );
AOI22X1TS U4926 ( .A0(n4561), .A1(n4208), .B0(n4563), .B1(n4211), .Y(n4209)
);
OAI211XLTS U4927 ( .A0(n4216), .A1(n4213), .B0(n4210), .C0(n4209), .Y(n1811)
);
AOI21X1TS U4928 ( .A0(n4212), .A1(n4211), .B0(n4094), .Y(n4558) );
OAI22X1TS U4929 ( .A0(n4216), .A1(n4215), .B0(n4214), .B1(n4213), .Y(n4217)
);
AOI21X1TS U4930 ( .A0(n4149), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n4217),
.Y(n4218) );
OAI21XLTS U4931 ( .A0(n4558), .A1(n4219), .B0(n4218), .Y(n1812) );
INVX2TS U4932 ( .A(FPMULT_zero_flag), .Y(n4614) );
AOI22X1TS U4933 ( .A0(FPMULT_FSM_exp_operation_A_S), .A1(n4614), .B0(n5274),
.B1(n5182), .Y(n4221) );
INVX2TS U4934 ( .A(operation[2]), .Y(n4421) );
OAI2BB1X1TS U4935 ( .A0N(ack_operation), .A1N(n4359), .B0(n4429), .Y(n4220)
);
OAI22X1TS U4936 ( .A0(n4221), .A1(n4584), .B0(FPMULT_P_Sgf[47]), .B1(n4585),
.Y(n1694) );
INVX2TS U4937 ( .A(FPMULT_FSM_exp_operation_A_S), .Y(n4586) );
OAI21XLTS U4938 ( .A0(n5182), .A1(n4584), .B0(FPMULT_FS_Module_state_reg[3]),
.Y(n4222) );
AOI22X1TS U4939 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n4408), .B0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n5189),
.Y(n4434) );
NAND2X1TS U4940 ( .A(n4434), .B(n4223), .Y(n4224) );
NOR2X1TS U4941 ( .A(n4332), .B(n4224), .Y(n4227) );
INVX2TS U4942 ( .A(n4227), .Y(n4229) );
AOI2BB2XLTS U4943 ( .B0(FPSENCOS_d_ff3_sign_out), .B1(n5363), .A0N(n5363),
.A1N(FPSENCOS_d_ff3_sign_out), .Y(n4226) );
BUFX4TS U4944 ( .A(n4224), .Y(n4290) );
BUFX4TS U4945 ( .A(n4290), .Y(n4513) );
BUFX4TS U4946 ( .A(n4285), .Y(n4550) );
BUFX4TS U4947 ( .A(n4290), .Y(n4577) );
AOI22X1TS U4948 ( .A0(operation[0]), .A1(n4550), .B0(FPADDSUB_intAS), .B1(
n4577), .Y(n4225) );
OAI21XLTS U4949 ( .A0(n4229), .A1(n4226), .B0(n4225), .Y(n1733) );
AND3X1TS U4950 ( .A(FPSENCOS_cont_var_out[1]), .B(n4227), .C(n5363), .Y(
n4509) );
AOI22X1TS U4951 ( .A0(Data_1[11]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n4290), .Y(n4231) );
NOR3XLTS U4952 ( .A(FPSENCOS_cont_var_out[1]), .B(n5363), .C(n4229), .Y(
n4228) );
BUFX4TS U4953 ( .A(n4300), .Y(n4317) );
AOI22X1TS U4954 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[11]), .B0(n4238), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n4230) );
OAI211XLTS U4955 ( .A0(n2202), .A1(n5415), .B0(n4231), .C0(n4230), .Y(n1932)
);
AOI22X1TS U4956 ( .A0(Data_1[20]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n4577), .Y(n4233) );
BUFX4TS U4957 ( .A(n4300), .Y(n4510) );
AOI22X1TS U4958 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[20]), .B0(n4238), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n4232) );
OAI211XLTS U4959 ( .A0(n4329), .A1(n5424), .B0(n4233), .C0(n4232), .Y(n1923)
);
AOI22X1TS U4960 ( .A0(Data_1[15]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n4290), .Y(n4235) );
AOI22X1TS U4961 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4238), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n4234) );
AOI22X1TS U4962 ( .A0(Data_1[14]), .A1(n4550), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n4290), .Y(n4237) );
AOI22X1TS U4963 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4238), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n4236) );
OAI211XLTS U4964 ( .A0(n4329), .A1(n5418), .B0(n4237), .C0(n4236), .Y(n1929)
);
AOI22X1TS U4965 ( .A0(Data_1[16]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n4290), .Y(n4240) );
AOI22X1TS U4966 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4238), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n4239) );
OAI211XLTS U4967 ( .A0(n4329), .A1(n5420), .B0(n4240), .C0(n4239), .Y(n1927)
);
AOI22X1TS U4968 ( .A0(Data_1[31]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n4513), .Y(n4242) );
BUFX4TS U4969 ( .A(n4238), .Y(n4295) );
AOI22X1TS U4970 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[31]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n4241) );
AOI22X1TS U4971 ( .A0(Data_1[9]), .A1(n4285), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n4290), .Y(n4244) );
AOI22X1TS U4972 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[9]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n4243) );
OAI211XLTS U4973 ( .A0(n2202), .A1(n5413), .B0(n4244), .C0(n4243), .Y(n1934)
);
AOI22X1TS U4974 ( .A0(Data_1[30]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n4513), .Y(n4246) );
AOI22X1TS U4975 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[30]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n4245) );
OAI211XLTS U4976 ( .A0(n2202), .A1(n5374), .B0(n4246), .C0(n4245), .Y(n1913)
);
BUFX4TS U4977 ( .A(n4285), .Y(n4578) );
AOI22X1TS U4978 ( .A0(Data_1[24]), .A1(n4578), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n4290), .Y(n4248) );
AOI22X1TS U4979 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[24]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n4247) );
OAI211XLTS U4980 ( .A0(n2202), .A1(n5376), .B0(n4248), .C0(n4247), .Y(n1919)
);
AOI22X1TS U4981 ( .A0(Data_1[25]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n4513), .Y(n4250) );
AOI22X1TS U4982 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[25]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n4249) );
OAI211XLTS U4983 ( .A0(n2202), .A1(n5377), .B0(n4250), .C0(n4249), .Y(n1918)
);
AOI22X1TS U4984 ( .A0(Data_1[10]), .A1(n4285), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n4290), .Y(n4252) );
AOI22X1TS U4985 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[10]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n4251) );
OAI211XLTS U4986 ( .A0(n2202), .A1(n5414), .B0(n4252), .C0(n4251), .Y(n1933)
);
AOI22X1TS U4987 ( .A0(Data_1[8]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n4290), .Y(n4254) );
BUFX4TS U4988 ( .A(n4238), .Y(n4545) );
AOI22X1TS U4989 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[8]), .B0(n4545), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n4253) );
OAI211XLTS U4990 ( .A0(n2202), .A1(n5412), .B0(n4254), .C0(n4253), .Y(n1935)
);
BUFX4TS U4991 ( .A(n4290), .Y(n4538) );
AOI22X1TS U4992 ( .A0(Data_1[2]), .A1(n4285), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n4538), .Y(n4256) );
AOI22X1TS U4993 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[2]), .B0(n4545), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n4255) );
OAI211XLTS U4994 ( .A0(n2202), .A1(n5406), .B0(n4256), .C0(n4255), .Y(n1941)
);
AOI22X1TS U4995 ( .A0(Data_1[7]), .A1(n4578), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n4290), .Y(n4258) );
AOI22X1TS U4996 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[7]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n4257) );
OAI211XLTS U4997 ( .A0(n2202), .A1(n5411), .B0(n4258), .C0(n4257), .Y(n1936)
);
AOI22X1TS U4998 ( .A0(Data_1[1]), .A1(n4550), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n4577), .Y(n4260) );
AOI22X1TS U4999 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[1]), .B0(n4545), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n4259) );
OAI211XLTS U5000 ( .A0(n2202), .A1(n5405), .B0(n4260), .C0(n4259), .Y(n1942)
);
AOI22X1TS U5001 ( .A0(Data_1[3]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n4577), .Y(n4262) );
AOI22X1TS U5002 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4545), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n4261) );
OAI211XLTS U5003 ( .A0(n2202), .A1(n5407), .B0(n4262), .C0(n4261), .Y(n1940)
);
AOI22X1TS U5004 ( .A0(Data_1[5]), .A1(n4550), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n4290), .Y(n4264) );
AOI22X1TS U5005 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[5]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n4263) );
OAI211XLTS U5006 ( .A0(n2202), .A1(n5409), .B0(n4264), .C0(n4263), .Y(n1938)
);
AOI22X1TS U5007 ( .A0(Data_1[18]), .A1(n4550), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n4538), .Y(n4266) );
AOI22X1TS U5008 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n4265) );
OAI211XLTS U5009 ( .A0(n4329), .A1(n5422), .B0(n4266), .C0(n4265), .Y(n1925)
);
AOI22X1TS U5010 ( .A0(Data_1[12]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n4290), .Y(n4268) );
AOI22X1TS U5011 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[12]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n4267) );
AOI22X1TS U5012 ( .A0(Data_1[21]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n4577), .Y(n4270) );
AOI22X1TS U5013 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[21]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n4269) );
OAI211XLTS U5014 ( .A0(n4329), .A1(n5425), .B0(n4270), .C0(n4269), .Y(n1922)
);
AOI22X1TS U5015 ( .A0(Data_1[22]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n4290), .Y(n4272) );
AOI22X1TS U5016 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n4271) );
OAI211XLTS U5017 ( .A0(n4329), .A1(n5426), .B0(n4272), .C0(n4271), .Y(n1921)
);
AOI22X1TS U5018 ( .A0(Data_1[6]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n4290), .Y(n4274) );
AOI22X1TS U5019 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[6]), .B0(n4545), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n4273) );
OAI211XLTS U5020 ( .A0(n2202), .A1(n5410), .B0(n4274), .C0(n4273), .Y(n1937)
);
AOI22X1TS U5021 ( .A0(Data_1[4]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n4577), .Y(n4276) );
AOI22X1TS U5022 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[4]), .B0(n4545), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n4275) );
OAI211XLTS U5023 ( .A0(n2202), .A1(n5408), .B0(n4276), .C0(n4275), .Y(n1939)
);
AOI22X1TS U5024 ( .A0(Data_1[17]), .A1(n4578), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n4538), .Y(n4278) );
AOI22X1TS U5025 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[17]), .B0(n4545), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n4277) );
OAI211XLTS U5026 ( .A0(n4329), .A1(n5421), .B0(n4278), .C0(n4277), .Y(n1926)
);
AOI22X1TS U5027 ( .A0(Data_1[13]), .A1(n4550), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n4290), .Y(n4280) );
AOI22X1TS U5028 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[13]), .B0(n4545), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n4279) );
OAI211XLTS U5029 ( .A0(n4329), .A1(n5417), .B0(n4280), .C0(n4279), .Y(n1930)
);
AOI22X1TS U5030 ( .A0(Data_1[19]), .A1(n4550), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n4513), .Y(n4282) );
AOI22X1TS U5031 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[19]), .B0(n4545), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n4281) );
OAI211XLTS U5032 ( .A0(n4329), .A1(n5423), .B0(n4282), .C0(n4281), .Y(n1924)
);
AOI22X1TS U5033 ( .A0(Data_1[29]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n4513), .Y(n4284) );
AOI22X1TS U5034 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[29]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n4283) );
OAI211XLTS U5035 ( .A0(n2202), .A1(n5372), .B0(n4284), .C0(n4283), .Y(n1914)
);
AOI22X1TS U5036 ( .A0(Data_1[23]), .A1(n4285), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n4538), .Y(n4287) );
AOI22X1TS U5037 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[23]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n4286) );
OAI211XLTS U5038 ( .A0(n4329), .A1(n5230), .B0(n4287), .C0(n4286), .Y(n1920)
);
AOI22X1TS U5039 ( .A0(Data_2[0]), .A1(n4526), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n4513), .Y(n4289) );
BUFX4TS U5040 ( .A(n4300), .Y(n4535) );
AOI22X1TS U5041 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n4295),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n4288) );
OAI211XLTS U5042 ( .A0(n2202), .A1(n5433), .B0(n4289), .C0(n4288), .Y(n1845)
);
AOI22X1TS U5043 ( .A0(Data_1[26]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n4290), .Y(n4292) );
AOI22X1TS U5044 ( .A0(n4535), .A1(FPSENCOS_d_ff2_X[26]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n4291) );
OAI211XLTS U5045 ( .A0(n2202), .A1(n5378), .B0(n4292), .C0(n4291), .Y(n1917)
);
INVX1TS U5046 ( .A(FPSENCOS_d_ff2_Y[28]), .Y(n4496) );
AOI22X1TS U5047 ( .A0(Data_1[28]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n4513), .Y(n4294) );
AOI22X1TS U5048 ( .A0(n4535), .A1(FPSENCOS_d_ff2_X[28]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n4293) );
OAI211XLTS U5049 ( .A0(n2202), .A1(n4496), .B0(n4294), .C0(n4293), .Y(n1915)
);
AOI22X1TS U5050 ( .A0(Data_1[27]), .A1(n4526), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n4577), .Y(n4297) );
AOI22X1TS U5051 ( .A0(n4510), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4295), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n4296) );
OAI211XLTS U5052 ( .A0(n2202), .A1(n5373), .B0(n4297), .C0(n4296), .Y(n1916)
);
AOI22X1TS U5053 ( .A0(n4550), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n4538), .Y(n4299) );
AOI22X1TS U5054 ( .A0(n4317), .A1(FPSENCOS_d_ff2_X[0]), .B0(
FPSENCOS_d_ff2_Z[0]), .B1(n4545), .Y(n4298) );
OAI211XLTS U5055 ( .A0(n2202), .A1(n5404), .B0(n4299), .C0(n4298), .Y(n1943)
);
AOI22X1TS U5056 ( .A0(Data_2[21]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n4577), .Y(n4302) );
BUFX3TS U5057 ( .A(n4545), .Y(n4326) );
AOI22X1TS U5058 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n4301) );
OAI211XLTS U5059 ( .A0(n4329), .A1(n5442), .B0(n4302), .C0(n4301), .Y(n1824)
);
AOI22X1TS U5060 ( .A0(Data_2[6]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n4513), .Y(n4304) );
AOI22X1TS U5061 ( .A0(n4317), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n4303) );
OAI211XLTS U5062 ( .A0(n2202), .A1(n5437), .B0(n4304), .C0(n4303), .Y(n1839)
);
AOI22X1TS U5063 ( .A0(Data_2[2]), .A1(n4526), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n4513), .Y(n4306) );
AOI22X1TS U5064 ( .A0(n4510), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n4326),
.B1(n2259), .Y(n4305) );
OAI211XLTS U5065 ( .A0(n2202), .A1(n5435), .B0(n4306), .C0(n4305), .Y(n1843)
);
AOI22X1TS U5066 ( .A0(Data_2[26]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n4577), .Y(n4308) );
AOI22X1TS U5067 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n4307) );
OAI211XLTS U5068 ( .A0(n4329), .A1(n5445), .B0(n4308), .C0(n4307), .Y(n1819)
);
AOI22X1TS U5069 ( .A0(Data_2[25]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n4577), .Y(n4310) );
AOI22X1TS U5070 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n4309) );
AOI22X1TS U5071 ( .A0(Data_2[24]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n4577), .Y(n4312) );
AOI22X1TS U5072 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n4311) );
OAI211XLTS U5073 ( .A0(n4329), .A1(n5443), .B0(n4312), .C0(n4311), .Y(n1821)
);
AOI22X1TS U5074 ( .A0(Data_2[23]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n4577), .Y(n4314) );
AOI22X1TS U5075 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n4313) );
OAI211XLTS U5076 ( .A0(n4329), .A1(n5429), .B0(n4314), .C0(n4313), .Y(n1822)
);
AOI22X1TS U5077 ( .A0(Data_2[4]), .A1(n4526), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n4513), .Y(n4316) );
AOI22X1TS U5078 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n4315) );
OAI211XLTS U5079 ( .A0(n2202), .A1(n5436), .B0(n4316), .C0(n4315), .Y(n1841)
);
AOI22X1TS U5080 ( .A0(Data_2[1]), .A1(n4526), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n4513), .Y(n4319) );
AOI22X1TS U5081 ( .A0(n4317), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n4318) );
OAI211XLTS U5082 ( .A0(n2202), .A1(n5434), .B0(n4319), .C0(n4318), .Y(n1844)
);
AOI22X1TS U5083 ( .A0(Data_2[9]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n4538), .Y(n4321) );
AOI22X1TS U5084 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n4320) );
OAI211XLTS U5085 ( .A0(n4329), .A1(n5439), .B0(n4321), .C0(n4320), .Y(n1836)
);
AOI22X1TS U5086 ( .A0(Data_2[10]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n4538), .Y(n4323) );
AOI22X1TS U5087 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n4322) );
OAI211XLTS U5088 ( .A0(n4329), .A1(n5440), .B0(n4323), .C0(n4322), .Y(n1835)
);
AOI22X1TS U5089 ( .A0(Data_2[12]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n4538), .Y(n4325) );
AOI22X1TS U5090 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n4324) );
OAI211XLTS U5091 ( .A0(n4329), .A1(n5441), .B0(n4325), .C0(n4324), .Y(n1833)
);
AOI22X1TS U5092 ( .A0(Data_2[8]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n4513), .Y(n4328) );
AOI22X1TS U5093 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n4326),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n4327) );
OAI211XLTS U5094 ( .A0(n4329), .A1(n5438), .B0(n4328), .C0(n4327), .Y(n1837)
);
INVX2TS U5095 ( .A(n4330), .Y(overflow_flag) );
BUFX3TS U5096 ( .A(n4331), .Y(n4363) );
AOI22X1TS U5097 ( .A0(cordic_result[2]), .A1(n4344), .B0(n4430), .B1(
mult_result[2]), .Y(n4333) );
OAI21XLTS U5098 ( .A0(n4363), .A1(n5303), .B0(n4333), .Y(op_result[2]) );
AOI22X1TS U5099 ( .A0(cordic_result[4]), .A1(n4344), .B0(n4430), .B1(
mult_result[4]), .Y(n4334) );
OAI21XLTS U5100 ( .A0(n4331), .A1(n5293), .B0(n4334), .Y(op_result[4]) );
AOI22X1TS U5101 ( .A0(cordic_result[31]), .A1(n4427), .B0(n4430), .B1(
mult_result[31]), .Y(n4335) );
AOI22X1TS U5102 ( .A0(n4344), .A1(cordic_result[3]), .B0(n4430), .B1(
mult_result[3]), .Y(n4336) );
OAI21XLTS U5103 ( .A0(n4331), .A1(n5302), .B0(n4336), .Y(op_result[3]) );
AOI22X1TS U5104 ( .A0(n4344), .A1(cordic_result[0]), .B0(n4430), .B1(
mult_result[0]), .Y(n4337) );
OAI21XLTS U5105 ( .A0(n4363), .A1(n5305), .B0(n4337), .Y(op_result[0]) );
AOI22X1TS U5106 ( .A0(cordic_result[6]), .A1(n4344), .B0(n4430), .B1(
mult_result[6]), .Y(n4338) );
OAI21XLTS U5107 ( .A0(n4331), .A1(n5294), .B0(n4338), .Y(op_result[6]) );
AOI22X1TS U5108 ( .A0(cordic_result[5]), .A1(n4344), .B0(n4430), .B1(
mult_result[5]), .Y(n4339) );
AOI22X1TS U5109 ( .A0(n4344), .A1(cordic_result[1]), .B0(n4430), .B1(
mult_result[1]), .Y(n4340) );
OAI21XLTS U5110 ( .A0(n4331), .A1(n5306), .B0(n4340), .Y(op_result[1]) );
AOI22X1TS U5111 ( .A0(n4344), .A1(cordic_result[7]), .B0(n4430), .B1(
mult_result[7]), .Y(n4341) );
OAI21XLTS U5112 ( .A0(n4331), .A1(n5304), .B0(n4341), .Y(op_result[7]) );
AOI22X1TS U5113 ( .A0(n4427), .A1(cordic_result[28]), .B0(n4359), .B1(
mult_result[28]), .Y(n4342) );
AOI22X1TS U5114 ( .A0(n4344), .A1(cordic_result[8]), .B0(n4430), .B1(
mult_result[8]), .Y(n4343) );
OAI21XLTS U5115 ( .A0(n4331), .A1(n5297), .B0(n4343), .Y(op_result[8]) );
AOI22X1TS U5116 ( .A0(n4344), .A1(cordic_result[9]), .B0(n4430), .B1(
mult_result[9]), .Y(n4345) );
OAI21XLTS U5117 ( .A0(n4331), .A1(n5307), .B0(n4345), .Y(op_result[9]) );
AOI22X1TS U5118 ( .A0(n4427), .A1(cordic_result[27]), .B0(n4359), .B1(
mult_result[27]), .Y(n4346) );
AOI22X1TS U5119 ( .A0(n4427), .A1(cordic_result[26]), .B0(n4359), .B1(
mult_result[26]), .Y(n4347) );
OAI21XLTS U5120 ( .A0(n4363), .A1(n5313), .B0(n4347), .Y(op_result[26]) );
AOI22X1TS U5121 ( .A0(n4427), .A1(cordic_result[24]), .B0(n4359), .B1(
mult_result[24]), .Y(n4348) );
OAI21XLTS U5122 ( .A0(n4363), .A1(n5225), .B0(n4348), .Y(op_result[24]) );
AOI22X1TS U5123 ( .A0(n4427), .A1(cordic_result[11]), .B0(n4430), .B1(
mult_result[11]), .Y(n4349) );
OAI21XLTS U5124 ( .A0(n4331), .A1(n5298), .B0(n4349), .Y(op_result[11]) );
AOI22X1TS U5125 ( .A0(cordic_result[22]), .A1(n4427), .B0(n4430), .B1(
mult_result[22]), .Y(n4350) );
OAI21XLTS U5126 ( .A0(n4363), .A1(n5286), .B0(n4350), .Y(op_result[22]) );
AOI22X1TS U5127 ( .A0(cordic_result[20]), .A1(n4427), .B0(n4359), .B1(
mult_result[20]), .Y(n4351) );
AOI22X1TS U5128 ( .A0(cordic_result[21]), .A1(n4427), .B0(n4430), .B1(
mult_result[21]), .Y(n4352) );
OAI21XLTS U5129 ( .A0(n4363), .A1(n5289), .B0(n4352), .Y(op_result[21]) );
AOI22X1TS U5130 ( .A0(cordic_result[18]), .A1(n4427), .B0(n4430), .B1(
mult_result[18]), .Y(n4353) );
OAI21XLTS U5131 ( .A0(n4363), .A1(n5288), .B0(n4353), .Y(op_result[18]) );
AOI22X1TS U5132 ( .A0(cordic_result[19]), .A1(n4427), .B0(n4359), .B1(
mult_result[19]), .Y(n4354) );
OAI21XLTS U5133 ( .A0(n4363), .A1(n5290), .B0(n4354), .Y(op_result[19]) );
AOI22X1TS U5134 ( .A0(n4427), .A1(cordic_result[10]), .B0(n4430), .B1(
mult_result[10]), .Y(n4355) );
OAI21XLTS U5135 ( .A0(n4331), .A1(n5300), .B0(n4355), .Y(op_result[10]) );
AOI22X1TS U5136 ( .A0(n4427), .A1(cordic_result[16]), .B0(n4430), .B1(
mult_result[16]), .Y(n4356) );
OAI21XLTS U5137 ( .A0(n4363), .A1(n5296), .B0(n4356), .Y(op_result[16]) );
AOI22X1TS U5138 ( .A0(cordic_result[15]), .A1(n4427), .B0(n4430), .B1(
mult_result[15]), .Y(n4357) );
OAI21XLTS U5139 ( .A0(n4331), .A1(n5287), .B0(n4357), .Y(op_result[15]) );
AOI22X1TS U5140 ( .A0(cordic_result[12]), .A1(n4427), .B0(n4430), .B1(
mult_result[12]), .Y(n4358) );
OAI21XLTS U5141 ( .A0(n4331), .A1(n5301), .B0(n4358), .Y(op_result[12]) );
AOI22X1TS U5142 ( .A0(n4427), .A1(cordic_result[13]), .B0(n4359), .B1(
mult_result[13]), .Y(n4360) );
OAI21XLTS U5143 ( .A0(n4331), .A1(n5295), .B0(n4360), .Y(op_result[13]) );
AOI22X1TS U5144 ( .A0(n4427), .A1(cordic_result[14]), .B0(n4430), .B1(
mult_result[14]), .Y(n4361) );
OAI21XLTS U5145 ( .A0(n4331), .A1(n5299), .B0(n4361), .Y(op_result[14]) );
AOI22X1TS U5146 ( .A0(cordic_result[17]), .A1(n4427), .B0(n4430), .B1(
mult_result[17]), .Y(n4362) );
OAI21XLTS U5147 ( .A0(n4363), .A1(n5292), .B0(n4362), .Y(op_result[17]) );
NAND2X1TS U5148 ( .A(n4419), .B(n4439), .Y(n4409) );
OAI21XLTS U5149 ( .A0(n4444), .A1(n5363), .B0(FPSENCOS_cont_var_out[1]), .Y(
n4364) );
NOR3BX1TS U5150 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n4365) );
XOR2X1TS U5151 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4365), .Y(
DP_OP_234J210_126_8543_n15) );
OR2X2TS U5152 ( .A(FPMULT_FSM_selector_B[1]), .B(n5324), .Y(n4372) );
OAI2BB1X1TS U5153 ( .A0N(FPMULT_Op_MY[29]), .A1N(n5327), .B0(n4372), .Y(
n4366) );
XOR2X1TS U5154 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4366), .Y(
DP_OP_234J210_126_8543_n16) );
OAI2BB1X1TS U5155 ( .A0N(FPMULT_Op_MY[28]), .A1N(n5327), .B0(n4372), .Y(
n4367) );
XOR2X1TS U5156 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4367), .Y(
DP_OP_234J210_126_8543_n17) );
OAI2BB1X1TS U5157 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5327), .B0(n4372), .Y(
n4368) );
XOR2X1TS U5158 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4368), .Y(
DP_OP_234J210_126_8543_n18) );
OAI2BB1X1TS U5159 ( .A0N(FPMULT_Op_MY[26]), .A1N(n5327), .B0(n4372), .Y(
n4369) );
XOR2X1TS U5160 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4369), .Y(
DP_OP_234J210_126_8543_n19) );
OAI2BB1X1TS U5161 ( .A0N(FPMULT_Op_MY[25]), .A1N(n5327), .B0(n4372), .Y(
n4370) );
XOR2X1TS U5162 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4370), .Y(
DP_OP_234J210_126_8543_n20) );
OAI2BB1X1TS U5163 ( .A0N(FPMULT_Op_MY[24]), .A1N(n5327), .B0(n4372), .Y(
n4371) );
XOR2X1TS U5164 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4371), .Y(
DP_OP_234J210_126_8543_n21) );
NOR2XLTS U5165 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n4373) );
XOR2X1TS U5166 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n4374), .Y(
DP_OP_234J210_126_8543_n22) );
NOR2BX1TS U5167 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4375) );
XOR2X1TS U5168 ( .A(n2239), .B(n4375), .Y(DP_OP_26J210_123_9022_n14) );
NOR2BX1TS U5169 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4376) );
XOR2X1TS U5170 ( .A(n2239), .B(n4376), .Y(DP_OP_26J210_123_9022_n15) );
NOR2BX1TS U5171 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4377) );
XOR2X1TS U5172 ( .A(n2239), .B(n4377), .Y(DP_OP_26J210_123_9022_n16) );
NOR2BX1TS U5173 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4378) );
XOR2X1TS U5174 ( .A(n2239), .B(n4378), .Y(DP_OP_26J210_123_9022_n17) );
OR2X1TS U5175 ( .A(FPADDSUB_LZD_output_NRM2_EW[0]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4379) );
XOR2X1TS U5176 ( .A(n2239), .B(n4379), .Y(DP_OP_26J210_123_9022_n18) );
NAND2X1TS U5177 ( .A(n4613), .B(n5367), .Y(n1691) );
INVX4TS U5178 ( .A(n4590), .Y(n4380) );
MX2X1TS U5179 ( .A(FPMULT_Op_MX[30]), .B(Data_1[30]), .S0(n4380), .Y(n1689)
);
BUFX4TS U5180 ( .A(n4671), .Y(n4808) );
NOR2X4TS U5181 ( .A(n4616), .B(n4808), .Y(n4381) );
MX2X1TS U5182 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n4381), .Y(n1542) );
MX2X1TS U5183 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
MX2X1TS U5184 ( .A(FPMULT_Op_MX[29]), .B(Data_1[29]), .S0(n4380), .Y(n1688)
);
MX2X1TS U5185 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_exp_oper_result[6]), .S0(n4381), .Y(n1543) );
MX2X1TS U5186 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U5187 ( .A(FPMULT_Op_MX[28]), .B(Data_1[28]), .S0(n4380), .Y(n1687)
);
MX2X1TS U5188 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n4381), .Y(n1544) );
MX2X1TS U5189 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U5190 ( .A(FPMULT_Op_MX[27]), .B(Data_1[27]), .S0(n4380), .Y(n1686)
);
MX2X1TS U5191 ( .A(FPMULT_Exp_module_Data_S[4]), .B(
FPMULT_exp_oper_result[4]), .S0(n4381), .Y(n1545) );
MX2X1TS U5192 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U5193 ( .A(FPMULT_Op_MX[26]), .B(Data_1[26]), .S0(n4380), .Y(n1685)
);
MX2X1TS U5194 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n4381), .Y(n1546) );
MX2X1TS U5195 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U5196 ( .A(FPMULT_Op_MX[25]), .B(Data_1[25]), .S0(n4380), .Y(n1684)
);
MX2X1TS U5197 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n4381), .Y(n1547) );
MX2X1TS U5198 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U5199 ( .A(FPMULT_Op_MX[24]), .B(Data_1[24]), .S0(n4380), .Y(n1683)
);
MX2X1TS U5200 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_exp_oper_result[1]), .S0(n4381), .Y(n1548) );
MX2X1TS U5201 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U5202 ( .A(FPMULT_Op_MX[23]), .B(Data_1[23]), .S0(n4380), .Y(n1682)
);
MX2X1TS U5203 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n4381), .Y(n1549) );
MX2X1TS U5204 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U5205 ( .A(FPMULT_Op_MY[30]), .B(Data_2[30]), .S0(n4380), .Y(n1657)
);
MX2X1TS U5206 ( .A(FPMULT_Op_MY[29]), .B(Data_2[29]), .S0(n4380), .Y(n1656)
);
MX2X1TS U5207 ( .A(FPMULT_Op_MY[28]), .B(Data_2[28]), .S0(n4380), .Y(n1655)
);
MX2X1TS U5208 ( .A(FPMULT_Op_MY[27]), .B(Data_2[27]), .S0(n4380), .Y(n1654)
);
MX2X1TS U5209 ( .A(FPMULT_Op_MY[26]), .B(Data_2[26]), .S0(n4380), .Y(n1653)
);
MX2X1TS U5210 ( .A(FPMULT_Op_MY[25]), .B(Data_2[25]), .S0(n4588), .Y(n1652)
);
MX2X1TS U5211 ( .A(FPMULT_Op_MY[24]), .B(Data_2[24]), .S0(n4588), .Y(n1651)
);
MX2X1TS U5212 ( .A(FPMULT_Op_MY[23]), .B(Data_2[23]), .S0(n4588), .Y(n1650)
);
MX2X1TS U5213 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n4381), .Y(n1541) );
XNOR2X1TS U5214 ( .A(DP_OP_234J210_126_8543_n1), .B(n4586), .Y(n4382) );
MX2X1TS U5215 ( .A(n4382), .B(FPMULT_Exp_module_Overflow_flag_A), .S0(n4809),
.Y(n1540) );
MX2X1TS U5216 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1420) );
MX2X1TS U5217 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1425) );
MX2X1TS U5218 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1430) );
MX2X1TS U5219 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1435) );
MX2X1TS U5220 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1440) );
MX2X1TS U5221 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1445) );
MX2X1TS U5222 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1450) );
MX2X1TS U5223 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1455) );
MX2X1TS U5224 ( .A(n4383), .B(FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n4437),
.Y(n1411) );
AO21XLTS U5225 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n4437), .B0(n4384),
.Y(n1316) );
AOI2BB1XLTS U5226 ( .A0N(n5122), .A1N(overflow_flag_addsubt), .B0(n4851),
.Y(n1413) );
NAND4XLTS U5227 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n4385) );
NAND4BXLTS U5228 ( .AN(n4385), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n4386) );
NAND3BXLTS U5229 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n4616), .C(n4386),
.Y(n4387) );
OAI22X1TS U5230 ( .A0(FPMULT_Exp_module_Data_S[8]), .A1(n4387), .B0(n4616),
.B1(n5375), .Y(n1516) );
NAND2X2TS U5231 ( .A(n4850), .B(n5122), .Y(n4390) );
OA22X1TS U5232 ( .A0(n4390), .A1(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B0(n5122),
.B1(n2248), .Y(n1469) );
AOI2BB2XLTS U5233 ( .B0(n5514), .B1(n5311), .A0N(n4390), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n1470) );
AOI2BB2XLTS U5234 ( .B0(n5514), .B1(n5312), .A0N(n4390), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(n1471) );
INVX2TS U5235 ( .A(n4390), .Y(n4389) );
AOI22X1TS U5236 ( .A0(n4389), .A1(n4388), .B0(n5514), .B1(n5313), .Y(n1472)
);
OA22X1TS U5237 ( .A0(n4390), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(n5122),
.B1(n2249), .Y(n1473) );
AOI2BB2XLTS U5238 ( .B0(n5514), .B1(n5225), .A0N(n4390), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n1474) );
OA22X1TS U5239 ( .A0(n4390), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(n5122),
.B1(n2250), .Y(n1475) );
NAND4XLTS U5240 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4392) );
NAND4XLTS U5241 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4391) );
NOR3X1TS U5242 ( .A(n5521), .B(n4392), .C(n4391), .Y(n4397) );
NOR4X1TS U5243 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[28]), .D(dataB[23]),
.Y(n4394) );
NOR3XLTS U5244 ( .A(dataB[26]), .B(dataB[29]), .C(dataB[25]), .Y(n4393) );
NAND4XLTS U5245 ( .A(n4397), .B(operation_reg[1]), .C(n4394), .D(n4393), .Y(
n4395) );
NOR3XLTS U5246 ( .A(operation_reg[0]), .B(dataB[31]), .C(n4395), .Y(n4396)
);
OAI211XLTS U5247 ( .A0(dataB[27]), .A1(n4396), .B0(n5520), .C0(n5519), .Y(
n4407) );
NOR4X1TS U5248 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[28]), .D(dataA[26]),
.Y(n4400) );
NOR4BX1TS U5249 ( .AN(operation_reg[1]), .B(dataA[31]), .C(dataA[24]), .D(
dataA[25]), .Y(n4399) );
NOR4X1TS U5250 ( .A(n5521), .B(dataA[30]), .C(operation_reg[0]), .D(
dataA[27]), .Y(n4398) );
NOR2BX1TS U5251 ( .AN(n4397), .B(operation_reg[1]), .Y(n4405) );
AOI31XLTS U5252 ( .A0(n4400), .A1(n4399), .A2(n4398), .B0(n4405), .Y(n4403)
);
NAND3XLTS U5253 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n4402) );
NAND4XLTS U5254 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n4401) );
OAI31X1TS U5255 ( .A0(n4403), .A1(n4402), .A2(n4401), .B0(dataB[27]), .Y(
n4404) );
NAND4XLTS U5256 ( .A(n5524), .B(n5523), .C(n5522), .D(n4404), .Y(n4406) );
OAI2BB2XLTS U5257 ( .B0(n4407), .B1(n4406), .A0N(n4405), .A1N(
operation_reg[0]), .Y(NaN_reg) );
INVX2TS U5258 ( .A(n4408), .Y(n4423) );
AOI22X1TS U5259 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n4423), .B1(n5189),
.Y(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR3XLTS U5260 ( .A(n2213), .B(n4467), .C(n4409), .Y(n4410) );
NAND3XLTS U5261 ( .A(n4410), .B(n4506), .C(n4420), .Y(n4411) );
CLKAND2X2TS U5262 ( .A(begin_operation), .B(operation[1]), .Y(n4414) );
OAI22X1TS U5263 ( .A0(n4412), .A1(n4411), .B0(n4414), .B1(n4413), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U5264 ( .AN(n4414), .B(n4413), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
NOR3XLTS U5265 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n5221),
.C(n4415), .Y(n4416) );
AO21XLTS U5266 ( .A0(n4440), .A1(n4417), .B0(n4416), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
OAI22X1TS U5267 ( .A0(n4573), .A1(n4420), .B0(n4419), .B1(n4418), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
AO22XLTS U5268 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n4421),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
NAND2X1TS U5269 ( .A(n4423), .B(n4422), .Y(n2193) );
AOI22X1TS U5270 ( .A0(n4427), .A1(cordic_result[30]), .B0(n4359), .B1(
mult_result[30]), .Y(n4424) );
OAI2BB1X1TS U5271 ( .A0N(n4431), .A1N(result_add_subt[30]), .B0(n4424), .Y(
op_result[30]) );
AOI22X1TS U5272 ( .A0(n4427), .A1(cordic_result[29]), .B0(n4359), .B1(
mult_result[29]), .Y(n4425) );
OAI2BB1X1TS U5273 ( .A0N(n4431), .A1N(n2248), .B0(n4425), .Y(op_result[29])
);
AOI22X1TS U5274 ( .A0(n4427), .A1(cordic_result[25]), .B0(n4359), .B1(
mult_result[25]), .Y(n4426) );
OAI2BB1X1TS U5275 ( .A0N(n4431), .A1N(n2249), .B0(n4426), .Y(op_result[25])
);
AOI22X1TS U5276 ( .A0(n4427), .A1(cordic_result[23]), .B0(n4359), .B1(
mult_result[23]), .Y(n4428) );
OAI2BB1X1TS U5277 ( .A0N(n4431), .A1N(n2250), .B0(n4428), .Y(op_result[23])
);
AOI22X1TS U5278 ( .A0(n4431), .A1(ready_add_subt), .B0(n4430), .B1(n4429),
.Y(n4432) );
OAI2BB1X1TS U5279 ( .A0N(n4433), .A1N(n4344), .B0(n4432), .Y(operation_ready) );
OAI33X4TS U5280 ( .A0(n5278), .A1(n5189), .A2(n5217), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n4436) );
INVX2TS U5281 ( .A(n4436), .Y(n4438) );
AO22XLTS U5282 ( .A0(n4436), .A1(n4953), .B0(n4438), .B1(n4434), .Y(n2150)
);
AOI22X1TS U5283 ( .A0(n4438), .A1(n2312), .B0(n5125), .B1(n4436), .Y(n2149)
);
AOI22X1TS U5284 ( .A0(n4438), .A1(n5125), .B0(n5517), .B1(n4436), .Y(n2148)
);
AOI22X1TS U5285 ( .A0(n4438), .A1(n5513), .B0(n4437), .B1(n4436), .Y(n2145)
);
AOI22X1TS U5286 ( .A0(n4438), .A1(n4437), .B0(n5514), .B1(n4436), .Y(n2144)
);
AOI22X1TS U5287 ( .A0(n4440), .A1(n5452), .B0(n5525), .B1(n4439), .Y(n2143)
);
AOI2BB2XLTS U5288 ( .B0(n4463), .B1(n4442), .A0N(n4442), .A1N(n4463), .Y(
n2141) );
NAND2X1TS U5289 ( .A(n4463), .B(n4442), .Y(n4443) );
XNOR2X1TS U5290 ( .A(FPSENCOS_cont_iter_out[3]), .B(n4443), .Y(n2140) );
AOI2BB2XLTS U5291 ( .B0(n4444), .B1(n5363), .A0N(n5363), .A1N(n4444), .Y(
n2139) );
AO22XLTS U5292 ( .A0(n4468), .A1(FPSENCOS_d_ff1_shift_region_flag_out[0]),
.B0(n4467), .B1(region_flag[0]), .Y(n2137) );
BUFX3TS U5293 ( .A(n4467), .Y(n4469) );
AO22XLTS U5294 ( .A0(n4468), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B0(n4467), .B1(region_flag[1]), .Y(n2136) );
AOI22X1TS U5295 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n4574), .B0(n4447),
.B1(n4449), .Y(n4446) );
NAND2X1TS U5296 ( .A(n4446), .B(n4445), .Y(n2134) );
AOI22X1TS U5297 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n4481), .B0(n4447),
.B1(n4451), .Y(n4448) );
NAND2X1TS U5298 ( .A(n4448), .B(n4455), .Y(n2130) );
AOI22X1TS U5299 ( .A0(n3744), .A1(n4449), .B0(FPSENCOS_d_ff3_LUT_out[7]),
.B1(n4506), .Y(n4450) );
NAND2X1TS U5300 ( .A(n4450), .B(n4458), .Y(n2128) );
AO22XLTS U5301 ( .A0(n3744), .A1(n4441), .B0(n4503), .B1(
FPSENCOS_d_ff3_LUT_out[8]), .Y(n2127) );
AOI22X1TS U5302 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n4506), .B0(n4452),
.B1(n4451), .Y(n4453) );
NAND2BXLTS U5303 ( .AN(n4454), .B(n4453), .Y(n2125) );
OAI221XLTS U5304 ( .A0(n2214), .A1(n5427), .B0(n4506), .B1(n4456), .C0(n4455), .Y(n2124) );
BUFX3TS U5305 ( .A(n2214), .Y(n4500) );
AOI2BB2XLTS U5306 ( .B0(n2214), .B1(n2260), .A0N(FPSENCOS_d_ff3_LUT_out[13]),
.A1N(n4500), .Y(n2123) );
BUFX4TS U5307 ( .A(n2214), .Y(n4491) );
AO22XLTS U5308 ( .A0(n4491), .A1(n4457), .B0(n4574), .B1(
FPSENCOS_d_ff3_LUT_out[19]), .Y(n2121) );
OAI221XLTS U5309 ( .A0(n2214), .A1(n5428), .B0(n4506), .B1(n4459), .C0(n4458), .Y(n2120) );
NOR2XLTS U5310 ( .A(n5525), .B(n4460), .Y(n4462) );
AOI22X1TS U5311 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n4506), .B0(n4462),
.B1(n4461), .Y(n4465) );
AOI32X1TS U5312 ( .A0(n4466), .A1(n4465), .A2(n4464), .B0(n4463), .B1(n4465),
.Y(n2117) );
NAND2BXLTS U5313 ( .AN(FPSENCOS_d_ff3_LUT_out[27]), .B(n4574), .Y(n2115) );
AO22XLTS U5314 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n4469), .B1(
Data_1[0]), .Y(n2114) );
AO22XLTS U5315 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n4469), .B1(
Data_1[1]), .Y(n2113) );
AO22XLTS U5316 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n4467), .B1(
Data_1[2]), .Y(n2112) );
AO22XLTS U5317 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n4467), .B1(
Data_1[3]), .Y(n2111) );
INVX2TS U5318 ( .A(n4467), .Y(n4472) );
AO22XLTS U5319 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n4467), .B1(
Data_1[4]), .Y(n2110) );
AO22XLTS U5320 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n4467), .B1(
Data_1[5]), .Y(n2109) );
AO22XLTS U5321 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n4467), .B1(
Data_1[6]), .Y(n2108) );
AO22XLTS U5322 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n4467), .B1(
Data_1[7]), .Y(n2107) );
AO22XLTS U5323 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n4467), .B1(
Data_1[8]), .Y(n2106) );
AO22XLTS U5324 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n4467), .B1(
Data_1[9]), .Y(n2105) );
AO22XLTS U5325 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n4467), .B1(
Data_1[10]), .Y(n2104) );
AO22XLTS U5326 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n4467), .B1(
Data_1[11]), .Y(n2103) );
AO22XLTS U5327 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n4467), .B1(
Data_1[12]), .Y(n2102) );
AO22XLTS U5328 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n4469), .B1(
Data_1[13]), .Y(n2101) );
AO22XLTS U5329 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n4469), .B1(
Data_1[14]), .Y(n2100) );
AO22XLTS U5330 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n4469), .B1(
Data_1[15]), .Y(n2099) );
AO22XLTS U5331 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n4469), .B1(
Data_1[16]), .Y(n2098) );
AO22XLTS U5332 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n4469), .B1(
Data_1[17]), .Y(n2097) );
AO22XLTS U5333 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n4469), .B1(
Data_1[18]), .Y(n2096) );
AO22XLTS U5334 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n4469), .B1(
Data_1[19]), .Y(n2095) );
INVX2TS U5335 ( .A(n4469), .Y(n4470) );
AO22XLTS U5336 ( .A0(n4470), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n4469), .B1(
Data_1[20]), .Y(n2094) );
AO22XLTS U5337 ( .A0(n4470), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n4469), .B1(
Data_1[21]), .Y(n2093) );
AO22XLTS U5338 ( .A0(n4470), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n4469), .B1(
Data_1[22]), .Y(n2092) );
AO22XLTS U5339 ( .A0(n4470), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n4467), .B1(
Data_1[23]), .Y(n2091) );
AO22XLTS U5340 ( .A0(n4470), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n4469), .B1(
Data_1[24]), .Y(n2090) );
AO22XLTS U5341 ( .A0(n4470), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n4467), .B1(
Data_1[25]), .Y(n2089) );
AO22XLTS U5342 ( .A0(n4470), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n4467), .B1(
Data_1[26]), .Y(n2088) );
AO22XLTS U5343 ( .A0(n4472), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n4467), .B1(
Data_1[27]), .Y(n2087) );
AO22XLTS U5344 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n4467), .B1(
Data_1[28]), .Y(n2086) );
AO22XLTS U5345 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n4467), .B1(
Data_1[29]), .Y(n2085) );
AO22XLTS U5346 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n4467), .B1(
Data_1[30]), .Y(n2084) );
AO22XLTS U5347 ( .A0(n4468), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n4471), .B1(
Data_1[31]), .Y(n2083) );
AO22XLTS U5348 ( .A0(n4573), .A1(result_add_subt[0]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(n2076) );
INVX4TS U5349 ( .A(n4569), .Y(n4475) );
AO22XLTS U5350 ( .A0(n4573), .A1(result_add_subt[1]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(n2073) );
INVX4TS U5351 ( .A(n4474), .Y(n4576) );
CLKBUFX3TS U5352 ( .A(n4474), .Y(n4476) );
BUFX3TS U5353 ( .A(n4569), .Y(n4567) );
AO22XLTS U5354 ( .A0(n4573), .A1(result_add_subt[2]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(n2070) );
INVX2TS U5355 ( .A(n4473), .Y(n4570) );
AO22XLTS U5356 ( .A0(n4570), .A1(result_add_subt[3]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(n2067) );
AO22XLTS U5357 ( .A0(n4573), .A1(result_add_subt[4]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(n2064) );
AO22XLTS U5358 ( .A0(n4573), .A1(result_add_subt[5]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(n2061) );
AO22XLTS U5359 ( .A0(n4570), .A1(result_add_subt[6]), .B0(n4568), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(n2058) );
AO22XLTS U5360 ( .A0(n4570), .A1(result_add_subt[7]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(n2055) );
AO22XLTS U5361 ( .A0(n4570), .A1(result_add_subt[8]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(n2052) );
AO22XLTS U5362 ( .A0(n4570), .A1(result_add_subt[9]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(n2049) );
AO22XLTS U5363 ( .A0(n4570), .A1(result_add_subt[10]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(n2046) );
AO22XLTS U5364 ( .A0(n4570), .A1(result_add_subt[11]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(n2043) );
AO22XLTS U5365 ( .A0(n4573), .A1(result_add_subt[12]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(n2040) );
AO22XLTS U5366 ( .A0(n4573), .A1(result_add_subt[13]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(n2037) );
AO22XLTS U5367 ( .A0(n4573), .A1(result_add_subt[14]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(n2034) );
AO22XLTS U5368 ( .A0(n4573), .A1(result_add_subt[15]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(n2031) );
AO22XLTS U5369 ( .A0(n4573), .A1(result_add_subt[16]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(n2028) );
AO22XLTS U5370 ( .A0(n4573), .A1(result_add_subt[17]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(n2025) );
AO22XLTS U5371 ( .A0(n4573), .A1(result_add_subt[18]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(n2022) );
AO22XLTS U5372 ( .A0(n4573), .A1(result_add_subt[19]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(n2019) );
AO22XLTS U5373 ( .A0(n4573), .A1(result_add_subt[20]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(n2016) );
AO22XLTS U5374 ( .A0(n4573), .A1(result_add_subt[21]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(n2013) );
AO22XLTS U5375 ( .A0(n4570), .A1(result_add_subt[22]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(n2010) );
AO22XLTS U5376 ( .A0(n4571), .A1(result_add_subt[22]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[22]), .Y(n2009) );
AO22XLTS U5377 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n4477), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n4488), .Y(n2007) );
OA22X1TS U5378 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[1]), .B1(n2213), .Y(n2005) );
OA22X1TS U5379 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[2]), .B1(n5512), .Y(n2003) );
OA22X1TS U5380 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[3]), .B1(n5512), .Y(n2001) );
AO22XLTS U5381 ( .A0(n4491), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n2000) );
AO22XLTS U5382 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n4494), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n4488), .Y(n1999) );
OA22X1TS U5383 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[5]), .B1(n5512), .Y(n1997) );
AO22XLTS U5384 ( .A0(n3744), .A1(FPSENCOS_d_ff2_X[5]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1996) );
OA22X1TS U5385 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[6]), .B1(n5512), .Y(n1995) );
OA22X1TS U5386 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[7]), .B1(n5512), .Y(n1993) );
AO22XLTS U5387 ( .A0(n3744), .A1(FPSENCOS_d_ff2_X[7]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1992) );
INVX4TS U5388 ( .A(n2213), .Y(n4493) );
AO22XLTS U5389 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n4493), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n4488), .Y(n1991) );
AO22XLTS U5390 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n4490), .B0(
FPSENCOS_d_ff_Xn[9]), .B1(n4487), .Y(n1989) );
OA22X1TS U5391 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[10]), .B1(n5512), .Y(n1987) );
AO22XLTS U5392 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n4493), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n4487), .Y(n1985) );
BUFX4TS U5393 ( .A(n3744), .Y(n4575) );
AO22XLTS U5394 ( .A0(n4575), .A1(FPSENCOS_d_ff2_X[11]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1984) );
OA22X1TS U5395 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[12]), .B1(n5512), .Y(n1983) );
OA22X1TS U5396 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[13]), .B1(n5512), .Y(n1981) );
AO22XLTS U5397 ( .A0(n4491), .A1(FPSENCOS_d_ff2_X[13]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1980) );
OA22X1TS U5398 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[14]), .B1(n5512), .Y(n1979) );
AO22XLTS U5399 ( .A0(n4491), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1978) );
AO22XLTS U5400 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n4493), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n4487), .Y(n1977) );
AO22XLTS U5401 ( .A0(n4491), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1976) );
OA22X1TS U5402 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[16]), .B1(n5512), .Y(n1975) );
AO22XLTS U5403 ( .A0(n4500), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1974) );
OA22X1TS U5404 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[17]), .B1(n2213), .Y(n1973) );
AO22XLTS U5405 ( .A0(n4491), .A1(FPSENCOS_d_ff2_X[17]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1972) );
AO22XLTS U5406 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n4490), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n4489), .Y(n1971) );
AO22XLTS U5407 ( .A0(n4575), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1970) );
OA22X1TS U5408 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[19]), .B1(n2213), .Y(n1969) );
AO22XLTS U5409 ( .A0(n4491), .A1(FPSENCOS_d_ff2_X[19]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1968) );
OA22X1TS U5410 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[20]), .B1(n2213), .Y(n1967) );
AO22XLTS U5411 ( .A0(n4575), .A1(FPSENCOS_d_ff2_X[20]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1966) );
AO22XLTS U5412 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n4490), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n4488), .Y(n1965) );
AO22XLTS U5413 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n4490), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n4488), .Y(n1963) );
AO22XLTS U5414 ( .A0(n4575), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1962) );
AO22XLTS U5415 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n4490), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n4487), .Y(n1961) );
OA22X1TS U5416 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[24]), .B1(n2213), .Y(n1960) );
OA22X1TS U5417 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[25]), .B1(n5512), .Y(n1959) );
OA22X1TS U5418 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[26]), .B1(n2213), .Y(n1958) );
OA22X1TS U5419 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[27]), .B1(n2213), .Y(n1957) );
OA22X1TS U5420 ( .A0(FPSENCOS_d_ff2_X[28]), .A1(n2213), .B0(
FPSENCOS_d_ff_Xn[28]), .B1(n4505), .Y(n1956) );
OA22X1TS U5421 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n4505), .B0(
FPSENCOS_d_ff2_X[29]), .B1(n2213), .Y(n1955) );
AO22XLTS U5422 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n4490), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n4487), .Y(n1954) );
AO22XLTS U5423 ( .A0(n4503), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n4500),
.B1(intadd_478_SUM_0_), .Y(n1952) );
AO22XLTS U5424 ( .A0(n4503), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n4500),
.B1(intadd_478_SUM_1_), .Y(n1951) );
AO22XLTS U5425 ( .A0(n4503), .A1(FPSENCOS_d_ff3_sh_x_out[26]), .B0(n4500),
.B1(intadd_478_SUM_2_), .Y(n1950) );
NOR2X1TS U5426 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_478_n1), .Y(n4480) );
AOI21X1TS U5427 ( .A0(intadd_478_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4480),
.Y(n4479) );
AOI2BB2XLTS U5428 ( .B0(n2214), .B1(n4479), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n4500), .Y(n1949) );
OR3X1TS U5429 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_478_n1), .Y(n4483) );
OAI21XLTS U5430 ( .A0(n4480), .A1(n5368), .B0(n4483), .Y(n4482) );
AO22XLTS U5431 ( .A0(n4575), .A1(n4482), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1948) );
NOR2X1TS U5432 ( .A(FPSENCOS_d_ff2_X[29]), .B(n4483), .Y(n4485) );
AOI21X1TS U5433 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n4483), .B0(n4485), .Y(
n4484) );
AOI2BB2XLTS U5434 ( .B0(n2214), .B1(n4484), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n4500), .Y(n1947) );
XOR2XLTS U5435 ( .A(FPSENCOS_d_ff2_X[30]), .B(n4485), .Y(n4486) );
AO22XLTS U5436 ( .A0(n4575), .A1(n4486), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1946) );
AO22XLTS U5437 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n4488), .B0(
FPSENCOS_d_ff2_X[31]), .B1(n4493), .Y(n1945) );
AO22XLTS U5438 ( .A0(n4575), .A1(FPSENCOS_d_ff2_X[31]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1944) );
AO22XLTS U5439 ( .A0(n4570), .A1(result_add_subt[31]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(n1911) );
AOI22X1TS U5440 ( .A0(n4571), .A1(n5219), .B0(n5370), .B1(n4474), .Y(n1910)
);
AO22XLTS U5441 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n4487), .Y(n1909) );
AO22XLTS U5442 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1908) );
AO22XLTS U5443 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n4488), .Y(n1907) );
AO22XLTS U5444 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1906) );
AO22XLTS U5445 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n4488), .Y(n1905) );
AO22XLTS U5446 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1904) );
AO22XLTS U5447 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n4488), .Y(n1903) );
AO22XLTS U5448 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1902) );
AO22XLTS U5449 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n4488), .Y(n1901) );
AO22XLTS U5450 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1900) );
AO22XLTS U5451 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n4489), .Y(n1899) );
AO22XLTS U5452 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1898) );
AO22XLTS U5453 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n4489), .Y(n1897) );
AO22XLTS U5454 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1896) );
AO22XLTS U5455 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n4489), .Y(n1895) );
AO22XLTS U5456 ( .A0(n3744), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1894) );
AO22XLTS U5457 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n4489), .Y(n1893) );
AO22XLTS U5458 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[8]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1892) );
AO22XLTS U5459 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n4492), .Y(n1891) );
AO22XLTS U5460 ( .A0(n4500), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1890) );
AO22XLTS U5461 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n4492), .Y(n1889) );
AO22XLTS U5462 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[10]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1888) );
AO22XLTS U5463 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n4492), .Y(n1887) );
AO22XLTS U5464 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1886) );
AO22XLTS U5465 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n4490), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n4492), .Y(n1885) );
AO22XLTS U5466 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[12]), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1884) );
AO22XLTS U5467 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n4492), .Y(n1883) );
AO22XLTS U5468 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1882) );
AO22XLTS U5469 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n4492), .Y(n1881) );
AO22XLTS U5470 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1880) );
AO22XLTS U5471 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n4492), .Y(n1879) );
AO22XLTS U5472 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1878) );
AO22XLTS U5473 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n4492), .Y(n1877) );
AO22XLTS U5474 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1876) );
AO22XLTS U5475 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n4492), .Y(n1875) );
AO22XLTS U5476 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1874) );
AO22XLTS U5477 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n4492), .Y(n1873) );
AO22XLTS U5478 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1872) );
AO22XLTS U5479 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n4492), .Y(n1871) );
AO22XLTS U5480 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1870) );
AO22XLTS U5481 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n4492), .Y(n1869) );
AO22XLTS U5482 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1868) );
AO22XLTS U5483 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n4492), .Y(n1867) );
AO22XLTS U5484 ( .A0(n4491), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1866) );
AO22XLTS U5485 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n4492), .Y(n1865) );
AO22XLTS U5486 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1864) );
AO22XLTS U5487 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n4492), .Y(n1863) );
AO22XLTS U5488 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n4492), .Y(n1862) );
AO22XLTS U5489 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n4492), .Y(n1861) );
AO22XLTS U5490 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n4493), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n4492), .Y(n1860) );
AO22XLTS U5491 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n4494), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n4488), .Y(n1859) );
AO22XLTS U5492 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n4494), .B0(
FPSENCOS_d_ff_Yn[28]), .B1(n4488), .Y(n1858) );
AO22XLTS U5493 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4494), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n4488), .Y(n1857) );
AO22XLTS U5494 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n4494), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n4488), .Y(n1856) );
AO22XLTS U5495 ( .A0(n4575), .A1(intadd_477_SUM_0_), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1854) );
AO22XLTS U5496 ( .A0(n4575), .A1(intadd_477_SUM_1_), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1853) );
AO22XLTS U5497 ( .A0(n4575), .A1(intadd_477_SUM_2_), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1852) );
AOI21X1TS U5498 ( .A0(intadd_477_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n4497),
.Y(n4495) );
AOI2BB2XLTS U5499 ( .B0(n2214), .B1(n4495), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n4500), .Y(n1851) );
NAND2X1TS U5500 ( .A(n4497), .B(n4496), .Y(n4499) );
OAI21XLTS U5501 ( .A0(n4497), .A1(n4496), .B0(n4499), .Y(n4498) );
AO22XLTS U5502 ( .A0(n3744), .A1(n4498), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1850) );
AOI21X1TS U5503 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4499), .B0(n4502), .Y(
n4501) );
AOI2BB2XLTS U5504 ( .B0(n3744), .B1(n4501), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n4500), .Y(n1849) );
AOI2BB2XLTS U5505 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n4502), .A0N(n4502),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n4504) );
AO22XLTS U5506 ( .A0(n3744), .A1(n4504), .B0(n4503), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1848) );
OAI22X1TS U5507 ( .A0(n2213), .A1(n2282), .B0(n5370), .B1(n4505), .Y(n1847)
);
AO22XLTS U5508 ( .A0(n3744), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n4574), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1846) );
AOI22X1TS U5509 ( .A0(Data_2[3]), .A1(n4526), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n4513), .Y(n4508) );
AOI22X1TS U5510 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n4507) );
NAND2X1TS U5511 ( .A(n4545), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n4527) );
AOI22X1TS U5512 ( .A0(Data_2[5]), .A1(n4526), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n4513), .Y(n4512) );
AOI22X1TS U5513 ( .A0(n4510), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n4511) );
NAND2X1TS U5514 ( .A(n4545), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n4521) );
AOI22X1TS U5515 ( .A0(Data_2[7]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n4513), .Y(n4515) );
AOI22X1TS U5516 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n4514) );
NAND2X1TS U5517 ( .A(n4545), .B(n2257), .Y(n4516) );
AOI22X1TS U5518 ( .A0(Data_2[11]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n4538), .Y(n4518) );
AOI22X1TS U5519 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n4517) );
AOI22X1TS U5520 ( .A0(Data_2[13]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n4538), .Y(n4520) );
AOI22X1TS U5521 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n4519) );
NAND2X1TS U5522 ( .A(n4545), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n4532) );
AOI22X1TS U5523 ( .A0(Data_2[14]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n4538), .Y(n4523) );
AOI22X1TS U5524 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n4522) );
AOI22X1TS U5525 ( .A0(Data_2[15]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n4538), .Y(n4525) );
AOI22X1TS U5526 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n4524) );
NAND2X1TS U5527 ( .A(n4545), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n4539) );
AOI22X1TS U5528 ( .A0(Data_2[16]), .A1(n4526), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n4538), .Y(n4529) );
AOI22X1TS U5529 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n4528) );
AOI22X1TS U5530 ( .A0(Data_2[17]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n4538), .Y(n4531) );
AOI22X1TS U5531 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n4530) );
AOI22X1TS U5532 ( .A0(Data_2[18]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n4538), .Y(n4534) );
AOI22X1TS U5533 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n4533) );
AOI22X1TS U5534 ( .A0(Data_2[19]), .A1(n4578), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n4538), .Y(n4537) );
AOI22X1TS U5535 ( .A0(n4535), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n4536) );
NAND2X1TS U5536 ( .A(n4545), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n4542) );
AOI22X1TS U5537 ( .A0(Data_2[20]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n4538), .Y(n4541) );
AOI22X1TS U5538 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n4540) );
AOI22X1TS U5539 ( .A0(Data_2[22]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n4577), .Y(n4544) );
AOI22X1TS U5540 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n4543) );
AOI22X1TS U5541 ( .A0(Data_2[27]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n4577), .Y(n4547) );
AOI22X1TS U5542 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n4546) );
NAND2X1TS U5543 ( .A(n4545), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n4551) );
AOI22X1TS U5544 ( .A0(Data_2[28]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n4577), .Y(n4549) );
AOI22X1TS U5545 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n4548) );
AOI22X1TS U5546 ( .A0(Data_2[29]), .A1(n4550), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n4577), .Y(n4553) );
AOI22X1TS U5547 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n2209),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n4552) );
AOI22X1TS U5548 ( .A0(FPSENCOS_d_ff3_sh_x_out[30]), .A1(n2209), .B0(
FPADDSUB_intDY_EWSW[30]), .B1(n4577), .Y(n4555) );
AOI22X1TS U5549 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n4578),
.B1(Data_2[30]), .Y(n4554) );
NAND2X1TS U5550 ( .A(n4555), .B(n4554), .Y(n1815) );
OAI22X1TS U5551 ( .A0(n4558), .A1(n4557), .B0(n4556), .B1(n5239), .Y(n1814)
);
AOI22X1TS U5552 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n2203), .B0(n4160),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n4565) );
AOI22X1TS U5553 ( .A0(n4563), .A1(n4562), .B0(n4561), .B1(n4560), .Y(n4564)
);
NAND3XLTS U5554 ( .A(n4566), .B(n4565), .C(n4564), .Y(n1789) );
AO22XLTS U5555 ( .A0(n4573), .A1(n2250), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1788) );
AO22XLTS U5556 ( .A0(n4571), .A1(n2250), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[23]), .Y(n1787) );
AO22XLTS U5557 ( .A0(n4582), .A1(n2250), .B0(n4567), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(n1786) );
AO22XLTS U5558 ( .A0(n4573), .A1(result_add_subt[24]), .B0(n4568), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(n1785) );
AO22XLTS U5559 ( .A0(n4571), .A1(result_add_subt[24]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[24]), .Y(n1784) );
AO22XLTS U5560 ( .A0(n4573), .A1(n2249), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1782) );
AO22XLTS U5561 ( .A0(n4571), .A1(n2249), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[25]), .Y(n1781) );
AO22XLTS U5562 ( .A0(n4570), .A1(result_add_subt[26]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(n1779) );
AO22XLTS U5563 ( .A0(n4571), .A1(result_add_subt[26]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[26]), .Y(n1778) );
AO22XLTS U5564 ( .A0(n4573), .A1(result_add_subt[27]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(n1776) );
AO22XLTS U5565 ( .A0(n4571), .A1(result_add_subt[27]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[27]), .Y(n1775) );
AO22XLTS U5566 ( .A0(n4573), .A1(result_add_subt[28]), .B0(n4473), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(n1773) );
AO22XLTS U5567 ( .A0(n4571), .A1(result_add_subt[28]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[28]), .Y(n1772) );
AO22XLTS U5568 ( .A0(n4573), .A1(n2248), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1770) );
AO22XLTS U5569 ( .A0(n4571), .A1(n2248), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[29]), .Y(n1769) );
AO22XLTS U5570 ( .A0(n4573), .A1(result_add_subt[30]), .B0(n4572), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1767) );
AO22XLTS U5571 ( .A0(n4575), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4481), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1734) );
AO22XLTS U5572 ( .A0(n4576), .A1(result_add_subt[30]), .B0(n4474), .B1(
FPSENCOS_d_ff_Yn[30]), .Y(n1732) );
AOI22X1TS U5573 ( .A0(FPSENCOS_d_ff3_sh_x_out[31]), .A1(n2209), .B0(
FPADDSUB_intDY_EWSW[31]), .B1(n4577), .Y(n4581) );
AOI22X1TS U5574 ( .A0(n4300), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n4578),
.B1(Data_2[31]), .Y(n4580) );
NAND2X1TS U5575 ( .A(n4581), .B(n4580), .Y(n1730) );
AOI22X1TS U5576 ( .A0(n4582), .A1(n5219), .B0(n5388), .B1(n4569), .Y(n1729)
);
AO22XLTS U5577 ( .A0(n4588), .A1(Data_2[31]), .B0(n4590), .B1(
FPMULT_Op_MY[31]), .Y(n1696) );
CLKBUFX3TS U5578 ( .A(n4583), .Y(n4811) );
NAND3XLTS U5579 ( .A(n4587), .B(n4586), .C(n4585), .Y(n1692) );
INVX4TS U5580 ( .A(n4591), .Y(n4589) );
AO22XLTS U5581 ( .A0(n4589), .A1(Data_1[10]), .B0(n4590), .B1(
FPMULT_Op_MX[10]), .Y(n1669) );
AO22XLTS U5582 ( .A0(n4589), .A1(Data_1[9]), .B0(n4590), .B1(FPMULT_Op_MX[9]), .Y(n1668) );
AO22XLTS U5583 ( .A0(n4589), .A1(Data_1[8]), .B0(n4590), .B1(FPMULT_Op_MX[8]), .Y(n1667) );
AO22XLTS U5584 ( .A0(n4589), .A1(Data_1[7]), .B0(n4590), .B1(FPMULT_Op_MX[7]), .Y(n1666) );
AO22XLTS U5585 ( .A0(n4589), .A1(Data_1[6]), .B0(n4590), .B1(FPMULT_Op_MX[6]), .Y(n1665) );
AO22XLTS U5586 ( .A0(n4589), .A1(Data_1[4]), .B0(n4590), .B1(FPMULT_Op_MX[4]), .Y(n1663) );
AO22XLTS U5587 ( .A0(n4589), .A1(Data_1[3]), .B0(n4590), .B1(FPMULT_Op_MX[3]), .Y(n1662) );
AO22XLTS U5588 ( .A0(n4589), .A1(Data_1[31]), .B0(n4591), .B1(
FPMULT_Op_MX[31]), .Y(n1658) );
AO22XLTS U5589 ( .A0(n4592), .A1(Data_2[4]), .B0(n4590), .B1(FPMULT_Op_MY[4]), .Y(n1631) );
AO22XLTS U5590 ( .A0(n4592), .A1(Data_2[2]), .B0(n4590), .B1(FPMULT_Op_MY[2]), .Y(n1629) );
NAND4XLTS U5591 ( .A(n4600), .B(n4599), .C(n4598), .D(n4597), .Y(n4611) );
NOR4X1TS U5592 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[23]), .D(FPMULT_Op_MX[25]), .Y(n4602) );
NAND4XLTS U5593 ( .A(n4608), .B(n4607), .C(n4606), .D(n4605), .Y(n4609) );
OA22X1TS U5594 ( .A0(n4612), .A1(n4611), .B0(n4610), .B1(n4609), .Y(n4615)
);
AOI22X1TS U5595 ( .A0(n4616), .A1(n4615), .B0(n4614), .B1(n4613), .Y(n1626)
);
AOI32X1TS U5596 ( .A0(n4618), .A1(n3756), .A2(n4617), .B0(n5380), .B1(n2205),
.Y(n1625) );
AOI2BB2XLTS U5597 ( .B0(n4668), .B1(FPMULT_Sgf_normalized_result[0]), .A0N(
FPMULT_Add_result[0]), .A1N(n4659), .Y(n1624) );
NOR2XLTS U5598 ( .A(n2255), .B(FPMULT_Sgf_normalized_result[0]), .Y(n4619)
);
AOI21X1TS U5599 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n2255), .B0(
n4619), .Y(n4620) );
AOI2BB2XLTS U5600 ( .B0(n4668), .B1(n4620), .A0N(FPMULT_Add_result[1]),
.A1N(n4659), .Y(n1623) );
OR3X1TS U5601 ( .A(FPMULT_Sgf_normalized_result[2]), .B(n2255), .C(
FPMULT_Sgf_normalized_result[0]), .Y(n4622) );
OAI21XLTS U5602 ( .A0(n2255), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
FPMULT_Sgf_normalized_result[2]), .Y(n4621) );
AOI32X1TS U5603 ( .A0(n4622), .A1(n4668), .A2(n4621), .B0(n5379), .B1(n4664),
.Y(n1622) );
NAND2X1TS U5604 ( .A(FPMULT_Sgf_normalized_result[3]), .B(n4622), .Y(n4624)
);
OAI211XLTS U5605 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4622), .B0(
n4659), .C0(n4624), .Y(n4623) );
OAI2BB1X1TS U5606 ( .A0N(FPMULT_Add_result[3]), .A1N(n4664), .B0(n4623), .Y(
n1621) );
NAND2X1TS U5607 ( .A(n5261), .B(n4624), .Y(n4626) );
OAI21XLTS U5608 ( .A0(n4624), .A1(n5261), .B0(n4626), .Y(n4625) );
NAND2X1TS U5609 ( .A(FPMULT_Sgf_normalized_result[5]), .B(n4626), .Y(n4628)
);
OAI211XLTS U5610 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n4626), .B0(
n4659), .C0(n4628), .Y(n4627) );
OAI2BB1X1TS U5611 ( .A0N(FPMULT_Add_result[5]), .A1N(n4664), .B0(n4627), .Y(
n1619) );
AOI21X1TS U5612 ( .A0(n5264), .A1(n4628), .B0(n4630), .Y(n4629) );
NAND2X1TS U5613 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n4630), .Y(n4632)
);
OAI211XLTS U5614 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4630), .B0(
n4659), .C0(n4632), .Y(n4631) );
OAI2BB1X1TS U5615 ( .A0N(FPMULT_Add_result[7]), .A1N(n4664), .B0(n4631), .Y(
n1617) );
AOI21X1TS U5616 ( .A0(n5267), .A1(n4632), .B0(n4634), .Y(n4633) );
NAND2X1TS U5617 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n4634), .Y(n4636)
);
OAI211XLTS U5618 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4634), .B0(
n4659), .C0(n4636), .Y(n4635) );
OAI2BB1X1TS U5619 ( .A0N(FPMULT_Add_result[9]), .A1N(n4664), .B0(n4635), .Y(
n1615) );
AOI21X1TS U5620 ( .A0(n5270), .A1(n4636), .B0(n4638), .Y(n4637) );
NAND2X1TS U5621 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n4638), .Y(n4640)
);
OAI211XLTS U5622 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4638), .B0(
n4659), .C0(n4640), .Y(n4639) );
OAI2BB1X1TS U5623 ( .A0N(FPMULT_Add_result[11]), .A1N(n4664), .B0(n4639),
.Y(n1613) );
AOI21X1TS U5624 ( .A0(n5273), .A1(n4640), .B0(n4642), .Y(n4641) );
NAND2X1TS U5625 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n4642), .Y(n4644)
);
OAI211XLTS U5626 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4642), .B0(
n4659), .C0(n4644), .Y(n4643) );
OAI2BB1X1TS U5627 ( .A0N(FPMULT_Add_result[13]), .A1N(n4664), .B0(n4643),
.Y(n1611) );
AOI21X1TS U5628 ( .A0(n5279), .A1(n4644), .B0(n4647), .Y(n4646) );
NAND2X1TS U5629 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n4647), .Y(n4649)
);
OAI211XLTS U5630 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4647), .B0(
n4659), .C0(n4649), .Y(n4648) );
OAI2BB1X1TS U5631 ( .A0N(FPMULT_Add_result[15]), .A1N(n4664), .B0(n4648),
.Y(n1609) );
AOI21X1TS U5632 ( .A0(n5319), .A1(n4649), .B0(n4651), .Y(n4650) );
NAND2X1TS U5633 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n4651), .Y(n4653)
);
OAI211XLTS U5634 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4651), .B0(
n4659), .C0(n4653), .Y(n4652) );
OAI2BB1X1TS U5635 ( .A0N(FPMULT_Add_result[17]), .A1N(n4664), .B0(n4652),
.Y(n1607) );
AOI21X1TS U5636 ( .A0(n5331), .A1(n4653), .B0(n4655), .Y(n4654) );
NAND2X1TS U5637 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n4655), .Y(n4657)
);
OAI211XLTS U5638 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4655), .B0(
n4659), .C0(n4657), .Y(n4656) );
OAI2BB1X1TS U5639 ( .A0N(FPMULT_Add_result[19]), .A1N(n4664), .B0(n4656),
.Y(n1605) );
AOI21X1TS U5640 ( .A0(n5358), .A1(n4657), .B0(n4660), .Y(n4658) );
NAND2X1TS U5641 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4660), .Y(n4662)
);
OAI211XLTS U5642 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4660), .B0(
n4659), .C0(n4662), .Y(n4661) );
OAI2BB1X1TS U5643 ( .A0N(FPMULT_Add_result[21]), .A1N(n4664), .B0(n4661),
.Y(n1603) );
AOI211XLTS U5644 ( .A0(n5366), .A1(n4662), .B0(n4665), .C0(n4664), .Y(n4663)
);
AO21XLTS U5645 ( .A0(FPMULT_Add_result[22]), .A1(n4664), .B0(n4663), .Y(
n1602) );
AOI21X1TS U5646 ( .A0(n4665), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
n4664), .Y(n4667) );
OAI2BB1X1TS U5647 ( .A0N(FPMULT_Add_result[23]), .A1N(n4664), .B0(n4666),
.Y(n1601) );
AOI2BB1XLTS U5648 ( .A0N(n4659), .A1N(FPMULT_FSM_add_overflow_flag), .B0(
n4667), .Y(n1600) );
BUFX3TS U5649 ( .A(n4671), .Y(n4781) );
BUFX3TS U5650 ( .A(n4671), .Y(n4796) );
ADDHXLTS U5651 ( .A(n4673), .B(n4672), .CO(n4669), .S(n4674) );
ADDHXLTS U5652 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .B(n4675), .CO(
n4672), .S(n4676) );
ADDHXLTS U5653 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .B(n4680), .CO(
n4677), .S(n4681) );
ADDHXLTS U5654 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .B(n4685), .CO(
n4682), .S(n4686) );
CMPR32X2TS U5655 ( .A(n4691), .B(n4690), .C(n4689), .CO(n4687), .S(n4692) );
CMPR32X2TS U5656 ( .A(n4695), .B(n4694), .C(n4693), .CO(n4689), .S(n4696) );
CMPR32X2TS U5657 ( .A(n4703), .B(n4702), .C(n4701), .CO(n4697), .S(n4704) );
CMPR32X2TS U5658 ( .A(n4711), .B(n4710), .C(n4709), .CO(n4705), .S(n4712) );
CMPR32X2TS U5659 ( .A(n4719), .B(n4718), .C(n4717), .CO(n4713), .S(n4720) );
CMPR32X2TS U5660 ( .A(n4727), .B(n4726), .C(n4725), .CO(n4721), .S(n4728) );
CMPR32X2TS U5661 ( .A(n4731), .B(n4730), .C(n4729), .CO(n4725), .S(n4732) );
CMPR32X2TS U5662 ( .A(n4735), .B(n4734), .C(n4733), .CO(n4729), .S(n4736) );
CMPR32X2TS U5663 ( .A(n4739), .B(n4738), .C(n4737), .CO(n4733), .S(n4740) );
CMPR32X2TS U5664 ( .A(n4743), .B(n4742), .C(n4741), .CO(n4737), .S(n4744) );
CMPR32X2TS U5665 ( .A(n4747), .B(n4746), .C(n4745), .CO(n4741), .S(n4748) );
CMPR32X2TS U5666 ( .A(n4751), .B(n4750), .C(n4749), .CO(n4745), .S(n4752) );
AO22XLTS U5667 ( .A0(n4782), .A1(FPMULT_P_Sgf[22]), .B0(n4796), .B1(n4752),
.Y(n1575) );
AO22XLTS U5668 ( .A0(n4782), .A1(FPMULT_P_Sgf[21]), .B0(n4796), .B1(n4756),
.Y(n1574) );
CMPR32X2TS U5669 ( .A(n4759), .B(n4758), .C(n4757), .CO(n4753), .S(n4760) );
AO22XLTS U5670 ( .A0(n4782), .A1(FPMULT_P_Sgf[20]), .B0(n4808), .B1(n4760),
.Y(n1573) );
AO22XLTS U5671 ( .A0(n4782), .A1(FPMULT_P_Sgf[19]), .B0(n4796), .B1(n4764),
.Y(n1572) );
CMPR32X2TS U5672 ( .A(n4767), .B(n4766), .C(n4765), .CO(n4761), .S(n4768) );
AO22XLTS U5673 ( .A0(n4782), .A1(FPMULT_P_Sgf[18]), .B0(n4808), .B1(n4768),
.Y(n1571) );
AO22XLTS U5674 ( .A0(n4782), .A1(FPMULT_P_Sgf[17]), .B0(n4796), .B1(n4772),
.Y(n1570) );
CMPR32X2TS U5675 ( .A(n4775), .B(n4774), .C(n4773), .CO(n4769), .S(n4776) );
AO22XLTS U5676 ( .A0(n4782), .A1(FPMULT_P_Sgf[16]), .B0(n4808), .B1(n4776),
.Y(n1569) );
CMPR32X2TS U5677 ( .A(n4779), .B(n4778), .C(n4777), .CO(n4773), .S(n4780) );
AO22XLTS U5678 ( .A0(n4782), .A1(FPMULT_P_Sgf[15]), .B0(n4781), .B1(n4780),
.Y(n1568) );
CMPR32X2TS U5679 ( .A(n4785), .B(n4784), .C(n4783), .CO(n4777), .S(n4786) );
AO22XLTS U5680 ( .A0(n4809), .A1(FPMULT_P_Sgf[14]), .B0(n4808), .B1(n4786),
.Y(n1567) );
CMPR32X2TS U5681 ( .A(n4789), .B(n4788), .C(n4787), .CO(n4783), .S(n4790) );
AO22XLTS U5682 ( .A0(n4809), .A1(FPMULT_P_Sgf[13]), .B0(n4808), .B1(n4790),
.Y(n1566) );
ADDHXLTS U5683 ( .A(n4792), .B(n4791), .CO(n4787), .S(n4793) );
AO22XLTS U5684 ( .A0(n4809), .A1(FPMULT_P_Sgf[12]), .B0(n4808), .B1(n4793),
.Y(n1565) );
AO22XLTS U5685 ( .A0(n4809), .A1(FPMULT_P_Sgf[11]), .B0(n4808), .B1(n4794),
.Y(n1564) );
AO22XLTS U5686 ( .A0(n4809), .A1(FPMULT_P_Sgf[10]), .B0(n4796), .B1(n4795),
.Y(n1563) );
AO22XLTS U5687 ( .A0(n4809), .A1(FPMULT_P_Sgf[9]), .B0(n4808), .B1(n4797),
.Y(n1562) );
AO22XLTS U5688 ( .A0(n4809), .A1(FPMULT_P_Sgf[8]), .B0(n4808), .B1(n4798),
.Y(n1561) );
AO22XLTS U5689 ( .A0(n4809), .A1(FPMULT_P_Sgf[7]), .B0(n4808), .B1(n4799),
.Y(n1560) );
AO22XLTS U5690 ( .A0(n4809), .A1(FPMULT_P_Sgf[6]), .B0(n4808), .B1(n4800),
.Y(n1559) );
AO22XLTS U5691 ( .A0(n4809), .A1(FPMULT_P_Sgf[5]), .B0(n4808), .B1(n4801),
.Y(n1558) );
AO22XLTS U5692 ( .A0(n4809), .A1(FPMULT_P_Sgf[4]), .B0(n4808), .B1(n4802),
.Y(n1557) );
AO22XLTS U5693 ( .A0(n4809), .A1(FPMULT_P_Sgf[3]), .B0(n4808), .B1(n4803),
.Y(n1556) );
AO22XLTS U5694 ( .A0(n4809), .A1(FPMULT_P_Sgf[2]), .B0(n4808), .B1(n4804),
.Y(n1555) );
INVX2TS U5695 ( .A(n4805), .Y(n4806) );
AO22XLTS U5696 ( .A0(n4809), .A1(FPMULT_P_Sgf[1]), .B0(n4808), .B1(n4806),
.Y(n1554) );
AO22XLTS U5697 ( .A0(n4809), .A1(FPMULT_P_Sgf[0]), .B0(n4808), .B1(n4807),
.Y(n1553) );
INVX2TS U5698 ( .A(n4811), .Y(n4816) );
AO22XLTS U5699 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n4810), .B0(
mult_result[2]), .B1(n4816), .Y(n1513) );
AO22XLTS U5700 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n4810), .B0(
mult_result[4]), .B1(n4816), .Y(n1511) );
AO22XLTS U5701 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n4810), .B0(
mult_result[6]), .B1(n4816), .Y(n1509) );
AO22XLTS U5702 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n4810), .B0(
mult_result[7]), .B1(n4812), .Y(n1508) );
AO22XLTS U5703 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n4810), .B0(
mult_result[8]), .B1(n4816), .Y(n1507) );
AO22XLTS U5704 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4810), .B0(
mult_result[9]), .B1(n4816), .Y(n1506) );
AO22XLTS U5705 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n4810), .B0(
mult_result[10]), .B1(n4816), .Y(n1505) );
AO22XLTS U5706 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4810), .B0(
mult_result[11]), .B1(n4816), .Y(n1504) );
AO22XLTS U5707 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n4810), .B0(
mult_result[12]), .B1(n4812), .Y(n1503) );
AO22XLTS U5708 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4810), .B0(
mult_result[13]), .B1(n4812), .Y(n1502) );
AO22XLTS U5709 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n4810), .B0(
mult_result[14]), .B1(n4812), .Y(n1501) );
AO22XLTS U5710 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4810), .B0(
mult_result[15]), .B1(n4812), .Y(n1500) );
AO22XLTS U5711 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n4810), .B0(
mult_result[16]), .B1(n4812), .Y(n1499) );
AO22XLTS U5712 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4810), .B0(
mult_result[17]), .B1(n4812), .Y(n1498) );
AO22XLTS U5713 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n4810), .B0(
mult_result[18]), .B1(n4812), .Y(n1497) );
AO22XLTS U5714 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4810), .B0(
mult_result[19]), .B1(n4812), .Y(n1496) );
AO22XLTS U5715 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n4810), .B0(
mult_result[20]), .B1(n4812), .Y(n1495) );
AO22XLTS U5716 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4810), .B0(
mult_result[21]), .B1(n4812), .Y(n1494) );
AO22XLTS U5717 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4810), .B0(
mult_result[22]), .B1(n4812), .Y(n1493) );
OA22X1TS U5718 ( .A0(FPMULT_exp_oper_result[0]), .A1(n2296), .B0(n4811),
.B1(mult_result[23]), .Y(n1492) );
OA22X1TS U5719 ( .A0(FPMULT_exp_oper_result[1]), .A1(n2296), .B0(n4811),
.B1(mult_result[24]), .Y(n1491) );
OA22X1TS U5720 ( .A0(FPMULT_exp_oper_result[2]), .A1(n2296), .B0(n4811),
.B1(mult_result[25]), .Y(n1490) );
OA22X1TS U5721 ( .A0(FPMULT_exp_oper_result[3]), .A1(n2296), .B0(n4811),
.B1(mult_result[26]), .Y(n1489) );
OA22X1TS U5722 ( .A0(FPMULT_exp_oper_result[4]), .A1(n2296), .B0(n4811),
.B1(mult_result[27]), .Y(n1488) );
OA22X1TS U5723 ( .A0(FPMULT_exp_oper_result[5]), .A1(n2296), .B0(n4811),
.B1(mult_result[28]), .Y(n1487) );
OA22X1TS U5724 ( .A0(FPMULT_exp_oper_result[6]), .A1(n2296), .B0(n4811),
.B1(mult_result[29]), .Y(n1486) );
OA22X1TS U5725 ( .A0(FPMULT_exp_oper_result[7]), .A1(n2296), .B0(n4811),
.B1(mult_result[30]), .Y(n1485) );
OAI21XLTS U5726 ( .A0(n4814), .A1(underflow_flag_mult), .B0(n4813), .Y(n4815) );
OAI2BB1X1TS U5727 ( .A0N(mult_result[31]), .A1N(n4816), .B0(n4815), .Y(n1483) );
INVX4TS U5728 ( .A(n5123), .Y(n5127) );
NAND2X1TS U5729 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n5243), .Y(n4819) );
NAND2X1TS U5730 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n5359), .Y(n4827) );
INVX2TS U5731 ( .A(n4827), .Y(n4825) );
NOR2X1TS U5732 ( .A(n5199), .B(FPADDSUB_DMP_EXP_EWSW[24]), .Y(n4823) );
OAI22X1TS U5733 ( .A0(n4825), .A1(n4823), .B0(FPADDSUB_DmP_EXP_EWSW[24]),
.B1(n5200), .Y(n4821) );
AOI22X1TS U5734 ( .A0(FPADDSUB_DMP_EXP_EWSW[25]), .A1(n5249), .B0(n4819),
.B1(n4821), .Y(n4829) );
NOR2X1TS U5735 ( .A(n5246), .B(FPADDSUB_DMP_EXP_EWSW[26]), .Y(n4830) );
AOI21X1TS U5736 ( .A0(FPADDSUB_DMP_EXP_EWSW[26]), .A1(n5246), .B0(n4830),
.Y(n4817) );
XNOR2X1TS U5737 ( .A(n4829), .B(n4817), .Y(n4818) );
AO22XLTS U5738 ( .A0(n5127), .A1(n4818), .B0(n5128), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1480) );
INVX4TS U5739 ( .A(n5128), .Y(n5129) );
OAI21XLTS U5740 ( .A0(FPADDSUB_DmP_EXP_EWSW[25]), .A1(n5243), .B0(n4819),
.Y(n4820) );
XNOR2X1TS U5741 ( .A(n4821), .B(n4820), .Y(n4822) );
AO22XLTS U5742 ( .A0(n5129), .A1(n4822), .B0(n5123), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1479) );
AOI21X1TS U5743 ( .A0(FPADDSUB_DMP_EXP_EWSW[24]), .A1(n5199), .B0(n4823),
.Y(n4824) );
XNOR2X1TS U5744 ( .A(n4825), .B(n4824), .Y(n4826) );
AO22XLTS U5745 ( .A0(n5127), .A1(n4826), .B0(n5123), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1478) );
OAI21XLTS U5746 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n5359), .B0(n4827),
.Y(n4828) );
OAI22X1TS U5747 ( .A0(n4830), .A1(n4829), .B0(FPADDSUB_DmP_EXP_EWSW[26]),
.B1(n5248), .Y(n4832) );
XNOR2X1TS U5748 ( .A(FPADDSUB_DmP_EXP_EWSW[27]), .B(
FPADDSUB_DMP_EXP_EWSW[27]), .Y(n4831) );
XOR2XLTS U5749 ( .A(n4832), .B(n4831), .Y(n4833) );
AO22XLTS U5750 ( .A0(n5129), .A1(n4833), .B0(n5123), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1476) );
OAI222X1TS U5751 ( .A0(n2208), .A1(n5247), .B0(n5200), .B1(n4953), .C0(n5183), .C1(n4835), .Y(n1466) );
OAI222X1TS U5752 ( .A0(n4834), .A1(n5365), .B0(n5243), .B1(n4953), .C0(n5198), .C1(n4835), .Y(n1465) );
OAI222X1TS U5753 ( .A0(n4834), .A1(n5364), .B0(n5248), .B1(n4953), .C0(n5197), .C1(n4835), .Y(n1464) );
AO22XLTS U5754 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[23]), .B0(n5123),
.B1(FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1459) );
AO22XLTS U5755 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1458) );
INVX4TS U5756 ( .A(n5163), .Y(n5146) );
AO22XLTS U5757 ( .A0(n5146), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n5131),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1457) );
AO22XLTS U5758 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[23]), .B0(n5513), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1456) );
AO22XLTS U5759 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n5369),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1454) );
AO22XLTS U5760 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1453) );
AO22XLTS U5761 ( .A0(n5146), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n5131),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1452) );
AO22XLTS U5762 ( .A0(n2197), .A1(FPADDSUB_DMP_SFG[24]), .B0(n5513), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1451) );
AO22XLTS U5763 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n5123),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1449) );
AO22XLTS U5764 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1448) );
AO22XLTS U5765 ( .A0(n5146), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n5131),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1447) );
AO22XLTS U5766 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[25]), .B0(n5513), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1446) );
AO22XLTS U5767 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1443) );
AO22XLTS U5768 ( .A0(n5146), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n5131),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1442) );
AO22XLTS U5769 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[26]), .B0(n5513), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1441) );
AO22XLTS U5770 ( .A0(n5185), .A1(FPADDSUB_DMP_EXP_EWSW[27]), .B0(n5123),
.B1(FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1439) );
AO22XLTS U5771 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1438) );
AO22XLTS U5772 ( .A0(n5146), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n5131),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1437) );
BUFX4TS U5773 ( .A(n5513), .Y(n5101) );
AO22XLTS U5774 ( .A0(n2197), .A1(FPADDSUB_DMP_SFG[27]), .B0(n5101), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1436) );
AO22XLTS U5775 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1433) );
AO22XLTS U5776 ( .A0(n5146), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n5131),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1432) );
AO22XLTS U5777 ( .A0(n2197), .A1(FPADDSUB_DMP_SFG[28]), .B0(n5101), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1431) );
AO22XLTS U5778 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1428) );
AO22XLTS U5779 ( .A0(n5146), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n5131),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1427) );
AO22XLTS U5780 ( .A0(n2197), .A1(FPADDSUB_DMP_SFG[29]), .B0(n5101), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1426) );
AO22XLTS U5781 ( .A0(n2216), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n5123),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1424) );
AO22XLTS U5782 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1423) );
AO22XLTS U5783 ( .A0(n5146), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n5131),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1422) );
AO22XLTS U5784 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[30]), .B0(n5101), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1421) );
OAI222X1TS U5785 ( .A0(n4835), .A1(n5247), .B0(n5199), .B1(n4953), .C0(n5183), .C1(n2208), .Y(n1418) );
OAI222X1TS U5786 ( .A0(n4835), .A1(n5365), .B0(n5249), .B1(n4953), .C0(n5198), .C1(n4834), .Y(n1417) );
OAI222X1TS U5787 ( .A0(n4835), .A1(n5364), .B0(n5246), .B1(n4953), .C0(n5197), .C1(n4834), .Y(n1416) );
NOR2XLTS U5788 ( .A(n4850), .B(n5514), .Y(n4837) );
AO21XLTS U5789 ( .A0(underflow_flag_addsubt), .A1(n5514), .B0(n4837), .Y(
n1414) );
NOR2X1TS U5790 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(n5362), .Y(n5094) );
NAND2X1TS U5791 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n5328), .Y(n5088) );
NOR2X1TS U5792 ( .A(FPADDSUB_DMP_SFG[20]), .B(n5345), .Y(n5080) );
NAND2X1TS U5793 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n5275), .Y(n5076) );
NOR2X1TS U5794 ( .A(FPADDSUB_DMP_SFG[18]), .B(n5325), .Y(n5068) );
NAND2X1TS U5795 ( .A(FPADDSUB_DmP_mant_SFG_SWR[19]), .B(n5271), .Y(n5064) );
NOR2X1TS U5796 ( .A(FPADDSUB_DMP_SFG[16]), .B(n5280), .Y(n5054) );
NAND2X1TS U5797 ( .A(FPADDSUB_DmP_mant_SFG_SWR[17]), .B(n5268), .Y(n5050) );
NOR2X1TS U5798 ( .A(FPADDSUB_DMP_SFG[14]), .B(n5272), .Y(n5042) );
NAND2X1TS U5799 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n5262), .Y(n5038) );
NOR2X1TS U5800 ( .A(FPADDSUB_DMP_SFG[12]), .B(n5269), .Y(n5030) );
NAND2X1TS U5801 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n5258), .Y(n5026) );
NOR2X1TS U5802 ( .A(FPADDSUB_DMP_SFG[10]), .B(n5265), .Y(n5018) );
NAND2X1TS U5803 ( .A(FPADDSUB_DmP_mant_SFG_SWR[11]), .B(n5255), .Y(n5014) );
NOR2X1TS U5804 ( .A(FPADDSUB_DMP_SFG[8]), .B(n5260), .Y(n5006) );
NAND2X1TS U5805 ( .A(FPADDSUB_DmP_mant_SFG_SWR[9]), .B(n5253), .Y(n5002) );
NOR2X1TS U5806 ( .A(FPADDSUB_DMP_SFG[6]), .B(n5259), .Y(n4994) );
NAND2X1TS U5807 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n5252), .Y(n4990) );
NOR2X1TS U5808 ( .A(FPADDSUB_DMP_SFG[4]), .B(n5257), .Y(n4982) );
NAND2X1TS U5809 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n5251), .Y(n4978) );
NOR2X1TS U5810 ( .A(FPADDSUB_DMP_SFG[2]), .B(n5256), .Y(n4970) );
CLKINVX1TS U5811 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .Y(n5143) );
NAND2X1TS U5812 ( .A(n5143), .B(n5186), .Y(n4960) );
NAND2X1TS U5813 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(n5250), .Y(n4964) );
AOI22X1TS U5814 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n5204), .B0(n4966), .B1(
n4964), .Y(n4972) );
OAI2BB2X1TS U5815 ( .B0(n4970), .B1(n4972), .A0N(n5256), .A1N(
FPADDSUB_DMP_SFG[2]), .Y(n4977) );
AOI22X1TS U5816 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n5205), .B0(n4978), .B1(
n4977), .Y(n4984) );
OAI2BB2X1TS U5817 ( .B0(n4982), .B1(n4984), .A0N(n5257), .A1N(
FPADDSUB_DMP_SFG[4]), .Y(n4989) );
AOI22X1TS U5818 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n5206), .B0(n4990), .B1(
n4989), .Y(n4996) );
OAI2BB2X1TS U5819 ( .B0(n4994), .B1(n4996), .A0N(n5259), .A1N(
FPADDSUB_DMP_SFG[6]), .Y(n5001) );
AOI22X1TS U5820 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n5207), .B0(n5002), .B1(
n5001), .Y(n5008) );
OAI2BB2X1TS U5821 ( .B0(n5006), .B1(n5008), .A0N(n5260), .A1N(
FPADDSUB_DMP_SFG[8]), .Y(n5013) );
AOI22X1TS U5822 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n5208), .B0(n5014), .B1(
n5013), .Y(n5020) );
OAI2BB2X1TS U5823 ( .B0(n5018), .B1(n5020), .A0N(n5265), .A1N(
FPADDSUB_DMP_SFG[10]), .Y(n5025) );
AOI22X1TS U5824 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n5209), .B0(n5026), .B1(
n5025), .Y(n5032) );
OAI2BB2X1TS U5825 ( .B0(n5030), .B1(n5032), .A0N(n5269), .A1N(
FPADDSUB_DMP_SFG[12]), .Y(n5037) );
AOI22X1TS U5826 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n5210), .B0(n5038), .B1(
n5037), .Y(n5044) );
OAI2BB2X1TS U5827 ( .B0(n5042), .B1(n5044), .A0N(n5272), .A1N(
FPADDSUB_DMP_SFG[14]), .Y(n5049) );
AOI22X1TS U5828 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n5212), .B0(n5050), .B1(
n5049), .Y(n5056) );
OAI2BB2X1TS U5829 ( .B0(n5054), .B1(n5056), .A0N(n5280), .A1N(
FPADDSUB_DMP_SFG[16]), .Y(n5063) );
AOI22X1TS U5830 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n5215), .B0(n5064), .B1(
n5063), .Y(n5070) );
OAI2BB2X1TS U5831 ( .B0(n5068), .B1(n5070), .A0N(n5325), .A1N(
FPADDSUB_DMP_SFG[18]), .Y(n5075) );
AOI22X1TS U5832 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n5216), .B0(n5076), .B1(
n5075), .Y(n5082) );
OAI2BB2X1TS U5833 ( .B0(n5080), .B1(n5082), .A0N(n5345), .A1N(
FPADDSUB_DMP_SFG[20]), .Y(n5087) );
AOI22X1TS U5834 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n5229), .B0(n5088), .B1(
n5087), .Y(n5097) );
AOI21X1TS U5835 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n5362), .B0(n5097),
.Y(n4838) );
AOI222X4TS U5836 ( .A0(n5000), .A1(n5207), .B0(n5000), .B1(n5253), .C0(n5207), .C1(n5253), .Y(n5007) );
AOI222X4TS U5837 ( .A0(n5012), .A1(n5208), .B0(n5012), .B1(n5255), .C0(n5208), .C1(n5255), .Y(n5019) );
AOI222X4TS U5838 ( .A0(n5074), .A1(n5216), .B0(n5074), .B1(n5275), .C0(n5216), .C1(n5275), .Y(n5081) );
AOI222X4TS U5839 ( .A0(n5086), .A1(n5229), .B0(n5086), .B1(n5328), .C0(n5229), .C1(n5328), .Y(n5096) );
XOR2X1TS U5840 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .B(n4839), .Y(n4840) );
AOI22X1TS U5841 ( .A0(n2197), .A1(n4840), .B0(n2222), .B1(n5101), .Y(n1412)
);
NOR2XLTS U5842 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4841) );
NAND2BX2TS U5843 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n4899) );
NAND2X1TS U5844 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n5330), .Y(n4898)
);
OAI22X1TS U5845 ( .A0(n5356), .A1(n4899), .B0(n5239), .B1(n4898), .Y(n4842)
);
NAND3X1TS U5846 ( .A(n2198), .B(FPADDSUB_shift_value_SHT2_EWR[2]), .C(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n4910) );
NOR2XLTS U5847 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4899), .Y(n4844)
);
AOI22X1TS U5848 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n4843), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n5134), .Y(n4847) );
NOR2XLTS U5849 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n4898), .Y(n4845)
);
AND2X4TS U5850 ( .A(n4902), .B(n2198), .Y(n5132) );
AOI22X1TS U5851 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[1]), .B1(n5132), .Y(n4846) );
OAI211X1TS U5852 ( .A0(n4880), .A1(n2198), .B0(n4847), .C0(n4846), .Y(n5141)
);
NAND2X1TS U5853 ( .A(n5142), .B(n4907), .Y(n5177) );
INVX2TS U5854 ( .A(n5177), .Y(n4904) );
NOR2X2TS U5855 ( .A(n4902), .B(n5329), .Y(n4895) );
NOR2XLTS U5856 ( .A(n5140), .B(n4848), .Y(n4849) );
AOI211X1TS U5857 ( .A0(n5176), .A1(n5141), .B0(n4904), .C0(n4849), .Y(n5173)
);
NAND2X1TS U5858 ( .A(n4851), .B(n4850), .Y(n4852) );
OAI22X1TS U5859 ( .A0(n5122), .A1(n5286), .B0(n5173), .B1(n5121), .Y(n1410)
);
AO22XLTS U5860 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n5123),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1408) );
AOI22X1TS U5861 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n4843), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n5134), .Y(n4854) );
AOI22X1TS U5862 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n5132), .Y(n4853) );
OAI211X1TS U5863 ( .A0(n5140), .A1(n2198), .B0(n4854), .C0(n4853), .Y(n4882)
);
NOR2XLTS U5864 ( .A(n4880), .B(n4848), .Y(n4855) );
AOI211X1TS U5865 ( .A0(n5176), .A1(n4882), .B0(n4904), .C0(n4855), .Y(n5162)
);
OAI22X1TS U5866 ( .A0(n2299), .A1(n5287), .B0(n5162), .B1(n5121), .Y(n1407)
);
AO22XLTS U5867 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[15]), .B0(n5123),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1405) );
AOI22X1TS U5868 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n5132), .Y(n4858) );
AOI22X1TS U5869 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n4843), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n5134), .Y(n4857) );
OAI211X1TS U5870 ( .A0(n5104), .A1(n2198), .B0(n4858), .C0(n4857), .Y(n5061)
);
OAI21XLTS U5871 ( .A0(n5241), .A1(n4899), .B0(n4868), .Y(n4859) );
NOR2XLTS U5872 ( .A(n2236), .B(n4848), .Y(n4860) );
AOI211X1TS U5873 ( .A0(n5176), .A1(n5061), .B0(n4904), .C0(n4860), .Y(n5166)
);
OAI22X1TS U5874 ( .A0(n2299), .A1(n5288), .B0(n5166), .B1(n5121), .Y(n1404)
);
AO22XLTS U5875 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[18]), .B0(n5123),
.B1(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1402) );
AOI22X1TS U5876 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n5132), .Y(n4863) );
AOI22X1TS U5877 ( .A0(n2252), .A1(n4843), .B0(FPADDSUB_Data_array_SWR[6]),
.B1(n5134), .Y(n4862) );
OAI211X1TS U5878 ( .A0(n5117), .A1(n2198), .B0(n4863), .C0(n4862), .Y(n5111)
);
NOR2XLTS U5879 ( .A(n5109), .B(n4848), .Y(n4864) );
AOI211X1TS U5880 ( .A0(n5176), .A1(n5111), .B0(n4904), .C0(n4864), .Y(n5171)
);
OAI22X1TS U5881 ( .A0(n2299), .A1(n5289), .B0(n5171), .B1(n5121), .Y(n1401)
);
AO22XLTS U5882 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n5123),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1399) );
AOI22X1TS U5883 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n5132), .Y(n4866) );
AOI22X1TS U5884 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n4843), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n5134), .Y(n4865) );
OAI211X1TS U5885 ( .A0(n2236), .A1(n2198), .B0(n4866), .C0(n4865), .Y(n5106)
);
NOR2XLTS U5886 ( .A(n5104), .B(n4848), .Y(n4867) );
AOI211X1TS U5887 ( .A0(n5176), .A1(n5106), .B0(n4904), .C0(n4867), .Y(n5167)
);
OAI22X1TS U5888 ( .A0(n2299), .A1(n5290), .B0(n5167), .B1(n5121), .Y(n1398)
);
AO22XLTS U5889 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n5123),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1396) );
AOI22X1TS U5890 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[3]), .B1(n5132), .Y(n4871) );
AOI22X1TS U5891 ( .A0(n2251), .A1(n4843), .B0(FPADDSUB_Data_array_SWR[7]),
.B1(n5134), .Y(n4870) );
OAI211X1TS U5892 ( .A0(n4877), .A1(n2198), .B0(n4871), .C0(n4870), .Y(n5114)
);
NOR2XLTS U5893 ( .A(n5112), .B(n4848), .Y(n4872) );
AOI211X1TS U5894 ( .A0(n5176), .A1(n5114), .B0(n4904), .C0(n4872), .Y(n5169)
);
OAI22X1TS U5895 ( .A0(n5122), .A1(n5291), .B0(n5169), .B1(n5121), .Y(n1395)
);
AO22XLTS U5896 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[20]), .B0(n5128),
.B1(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1393) );
AOI22X1TS U5897 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n4843), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n5134), .Y(n4874) );
AOI22X1TS U5898 ( .A0(n2252), .A1(n5133), .B0(FPADDSUB_Data_array_SWR[6]),
.B1(n5132), .Y(n4873) );
OAI211X1TS U5899 ( .A0(n5112), .A1(n2198), .B0(n4874), .C0(n4873), .Y(n4879)
);
AOI211X1TS U5900 ( .A0(n5176), .A1(n4879), .B0(n4904), .C0(n4875), .Y(n5165)
);
OAI22X1TS U5901 ( .A0(n2299), .A1(n5292), .B0(n5165), .B1(n5121), .Y(n1392)
);
AO22XLTS U5902 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[17]), .B0(n5128),
.B1(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1390) );
NOR2XLTS U5903 ( .A(n4877), .B(n4876), .Y(n4878) );
NAND2X1TS U5904 ( .A(n5176), .B(n4907), .Y(n5144) );
INVX2TS U5905 ( .A(n5144), .Y(n5118) );
AOI211X1TS U5906 ( .A0(n5142), .A1(n4879), .B0(n4878), .C0(n5118), .Y(n5151)
);
OAI22X1TS U5907 ( .A0(n2299), .A1(n5293), .B0(n5151), .B1(n5121), .Y(n1389)
);
AO22XLTS U5908 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n5128), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1387) );
NOR2XLTS U5909 ( .A(n4880), .B(n4876), .Y(n4881) );
AOI211X1TS U5910 ( .A0(n5142), .A1(n4882), .B0(n4881), .C0(n5118), .Y(n5153)
);
OAI22X1TS U5911 ( .A0(n5122), .A1(n5294), .B0(n5153), .B1(n5121), .Y(n1386)
);
AO22XLTS U5912 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n5128), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1384) );
AOI21X1TS U5913 ( .A0(n2252), .A1(n5134), .B0(n4907), .Y(n4884) );
AOI22X1TS U5914 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n5132), .Y(n4883) );
OAI211X1TS U5915 ( .A0(n5350), .A1(n4910), .B0(n4884), .C0(n4883), .Y(n4889)
);
INVX2TS U5916 ( .A(n5133), .Y(n4913) );
NOR2X1TS U5917 ( .A(n4907), .B(n4901), .Y(n4912) );
AOI22X1TS U5918 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n5134), .B0(n2251),
.B1(n5132), .Y(n4885) );
OAI211X1TS U5919 ( .A0(n5351), .A1(n4913), .B0(n4912), .C0(n4885), .Y(n4890)
);
AOI22X1TS U5920 ( .A0(n5176), .A1(n4889), .B0(n4890), .B1(n5142), .Y(n5160)
);
OAI22X1TS U5921 ( .A0(n5122), .A1(n5295), .B0(n5160), .B1(n5121), .Y(n1383)
);
AO22XLTS U5922 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n5125),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1381) );
AOI22X1TS U5923 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n4843), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n5134), .Y(n4887) );
AOI22X1TS U5924 ( .A0(n2251), .A1(n5133), .B0(FPADDSUB_Data_array_SWR[7]),
.B1(n5132), .Y(n4886) );
OAI211X1TS U5925 ( .A0(n5109), .A1(n2198), .B0(n4887), .C0(n4886), .Y(n5120)
);
NOR2XLTS U5926 ( .A(n5117), .B(n4848), .Y(n4888) );
AOI211X1TS U5927 ( .A0(n5176), .A1(n5120), .B0(n4904), .C0(n4888), .Y(n5164)
);
OAI22X1TS U5928 ( .A0(n5122), .A1(n5296), .B0(n5164), .B1(n5121), .Y(n1380)
);
AO22XLTS U5929 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n5128),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1378) );
AOI22X1TS U5930 ( .A0(n5176), .A1(n4890), .B0(n4889), .B1(n5142), .Y(n5155)
);
OAI22X1TS U5931 ( .A0(n5122), .A1(n5297), .B0(n5155), .B1(n5121), .Y(n1377)
);
AO22XLTS U5932 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n5128), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1375) );
AOI22X1TS U5933 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[12]), .B1(n5132), .Y(n4892) );
AOI22X1TS U5934 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n5134), .B0(
FPADDSUB_Data_array_SWR[22]), .B1(n4843), .Y(n4891) );
NAND2X1TS U5935 ( .A(n4892), .B(n4891), .Y(n4905) );
AOI22X1TS U5936 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n5132), .Y(n4894) );
AOI22X1TS U5937 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n5134), .B0(
FPADDSUB_Data_array_SWR[23]), .B1(n4843), .Y(n4893) );
NAND2X1TS U5938 ( .A(n4894), .B(n4893), .Y(n4906) );
OAI22X1TS U5939 ( .A0(n5122), .A1(n5298), .B0(n5158), .B1(n5121), .Y(n1374)
);
AO22XLTS U5940 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n5369),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1372) );
AOI22X1TS U5941 ( .A0(FPADDSUB_Data_array_SWR[19]), .A1(n4843), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n5134), .Y(n4897) );
AOI22X1TS U5942 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n5132), .Y(n4896) );
OAI211X1TS U5943 ( .A0(n5174), .A1(n2198), .B0(n4897), .C0(n4896), .Y(n5108)
);
OAI22X1TS U5944 ( .A0(n5357), .A1(n4899), .B0(n5241), .B1(n4898), .Y(n4900)
);
NOR2XLTS U5945 ( .A(n5138), .B(n4848), .Y(n4903) );
AOI211X1TS U5946 ( .A0(n5176), .A1(n5108), .B0(n4904), .C0(n4903), .Y(n5161)
);
OAI22X1TS U5947 ( .A0(n5122), .A1(n5299), .B0(n5161), .B1(n5121), .Y(n1371)
);
AO22XLTS U5948 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n5128),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1369) );
AOI221X1TS U5949 ( .A0(n5176), .A1(n4906), .B0(n5142), .B1(n4905), .C0(n4907), .Y(n5157) );
OAI22X1TS U5950 ( .A0(n5122), .A1(n5300), .B0(n5157), .B1(n5121), .Y(n1368)
);
AO22XLTS U5951 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n5128),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1366) );
AOI21X1TS U5952 ( .A0(n2251), .A1(n5134), .B0(n4907), .Y(n4909) );
AOI22X1TS U5953 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[11]), .B1(n5132), .Y(n4908) );
OAI211X1TS U5954 ( .A0(n5351), .A1(n4910), .B0(n4909), .C0(n4908), .Y(n5115)
);
AOI22X1TS U5955 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n5134), .B0(n2252),
.B1(n5132), .Y(n4911) );
OAI211X1TS U5956 ( .A0(n5350), .A1(n4913), .B0(n4912), .C0(n4911), .Y(n5116)
);
AOI22X1TS U5957 ( .A0(n5176), .A1(n5115), .B0(n5116), .B1(n5142), .Y(n5159)
);
OAI22X1TS U5958 ( .A0(n5122), .A1(n5301), .B0(n5159), .B1(n5121), .Y(n1365)
);
AOI22X1TS U5959 ( .A0(n5237), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n5341), .B1(
FPADDSUB_intDY_EWSW[17]), .Y(n4914) );
AOI22X1TS U5960 ( .A0(n5336), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5344), .B1(
FPADDSUB_intDY_EWSW[15]), .Y(n4915) );
AOI22X1TS U5961 ( .A0(n5236), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n5342), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n4916) );
OAI221XLTS U5962 ( .A0(n5236), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n5342),
.B1(FPADDSUB_intDY_EWSW[13]), .C0(n4916), .Y(n4919) );
AOI22X1TS U5963 ( .A0(n5235), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n5340), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n4917) );
OAI221XLTS U5964 ( .A0(n5235), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n5340),
.B1(FPADDSUB_intDY_EWSW[11]), .C0(n4917), .Y(n4918) );
NOR4X1TS U5965 ( .A(n4921), .B(n4919), .C(n4920), .D(n4918), .Y(n4948) );
AOI22X1TS U5966 ( .A0(n5335), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n5339), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n4922) );
AOI22X1TS U5967 ( .A0(n5240), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n5352), .B1(
FPADDSUB_intDY_EWSW[29]), .Y(n4923) );
OAI221XLTS U5968 ( .A0(n5240), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n5352),
.B1(FPADDSUB_intDY_EWSW[29]), .C0(n4923), .Y(n4928) );
AOI22X1TS U5969 ( .A0(n5353), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n5337), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n4924) );
AOI22X1TS U5970 ( .A0(n5198), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n5338), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n4925) );
OAI221XLTS U5971 ( .A0(n5198), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n5338),
.B1(FPADDSUB_intDY_EWSW[1]), .C0(n4925), .Y(n4926) );
NOR4X1TS U5972 ( .A(n4929), .B(n4928), .C(n4927), .D(n4926), .Y(n4947) );
AOI22X1TS U5973 ( .A0(n5183), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n5347), .B1(
FPADDSUB_intDY_EWSW[23]), .Y(n4930) );
AOI22X1TS U5974 ( .A0(n5238), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n5343), .B1(
FPADDSUB_intDY_EWSW[21]), .Y(n4931) );
OAI221XLTS U5975 ( .A0(n5238), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n5343),
.B1(FPADDSUB_intDY_EWSW[21]), .C0(n4931), .Y(n4944) );
OAI22X1TS U5976 ( .A0(n5334), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n5231), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n4932) );
AOI221X1TS U5977 ( .A0(n5334), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[20]), .B1(n5231), .C0(n4932), .Y(n4933) );
OAI22X1TS U5978 ( .A0(n5349), .A1(FPADDSUB_intDY_EWSW[0]), .B0(n5197), .B1(
FPADDSUB_intDY_EWSW[26]), .Y(n4934) );
AOI221X1TS U5979 ( .A0(n5349), .A1(FPADDSUB_intDY_EWSW[0]), .B0(
FPADDSUB_intDY_EWSW[26]), .B1(n5197), .C0(n4934), .Y(n4941) );
OAI22X1TS U5980 ( .A0(n5333), .A1(FPADDSUB_intDY_EWSW[2]), .B0(n5232), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n4935) );
AOI221X1TS U5981 ( .A0(n5333), .A1(FPADDSUB_intDY_EWSW[2]), .B0(
FPADDSUB_intDY_EWSW[3]), .B1(n5232), .C0(n4935), .Y(n4940) );
OAI22X1TS U5982 ( .A0(n5234), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n5348), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n4936) );
OAI22X1TS U5983 ( .A0(n5233), .A1(FPADDSUB_intDY_EWSW[6]), .B0(n5332), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n4937) );
AOI221X1TS U5984 ( .A0(n5233), .A1(FPADDSUB_intDY_EWSW[6]), .B0(
FPADDSUB_intDY_EWSW[8]), .B1(n5332), .C0(n4937), .Y(n4938) );
NAND4XLTS U5985 ( .A(n4941), .B(n4940), .C(n4939), .D(n4938), .Y(n4942) );
NOR4X1TS U5986 ( .A(n4945), .B(n4944), .C(n4943), .D(n4942), .Y(n4946) );
OAI22X1TS U5987 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(n4951), .B0(n4950), .B1(
n4949), .Y(n4952) );
AOI2BB2XLTS U5988 ( .B0(n4953), .B1(n4952), .A0N(FPADDSUB_SIGN_FLAG_EXP),
.A1N(n4953), .Y(n1364) );
AO22XLTS U5989 ( .A0(n2216), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n5125), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1363) );
AO22XLTS U5990 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n5517), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1362) );
AO22XLTS U5991 ( .A0(n5146), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n5131), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1361) );
AO22XLTS U5992 ( .A0(n5093), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n5101), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1360) );
AO22XLTS U5993 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n4954), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n1359) );
AO22XLTS U5994 ( .A0(n2216), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n5128), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1356) );
INVX4TS U5995 ( .A(n5517), .Y(n5130) );
AO22XLTS U5996 ( .A0(n5130), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n5517), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1355) );
INVX4TS U5997 ( .A(n5163), .Y(n5172) );
AO22XLTS U5998 ( .A0(n2206), .A1(n5098), .B0(n5172), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1354) );
AOI21X1TS U5999 ( .A0(n4956), .A1(n5371), .B0(n5098), .Y(n4957) );
AOI22X1TS U6000 ( .A0(n2197), .A1(n5186), .B0(n5354), .B1(n5101), .Y(n1351)
);
NOR2XLTS U6001 ( .A(n5515), .B(n5186), .Y(n4958) );
OAI32X1TS U6002 ( .A0(n5143), .A1(n5515), .A2(n5186), .B0(
FPADDSUB_DmP_mant_SFG_SWR[1]), .B1(n4958), .Y(n4959) );
AOI22X1TS U6003 ( .A0(n2197), .A1(n4959), .B0(n5222), .B1(n5101), .Y(n1350)
);
NAND2X1TS U6004 ( .A(n5098), .B(n4960), .Y(n4962) );
OAI21XLTS U6005 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(FPADDSUB_DMP_SFG[0]), .B0(n4965), .Y(n4961) );
XNOR2X1TS U6006 ( .A(n4962), .B(n4961), .Y(n4963) );
AOI2BB2XLTS U6007 ( .B0(n2197), .B1(n4963), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[2]), .A1N(n2197), .Y(n1349) );
AOI22X1TS U6008 ( .A0(n5098), .A1(n4966), .B0(n4965), .B1(n5515), .Y(n4967)
);
XNOR2X1TS U6009 ( .A(n4968), .B(n4967), .Y(n4969) );
AOI22X1TS U6010 ( .A0(n2197), .A1(n4969), .B0(n5192), .B1(n5101), .Y(n1348)
);
AOI21X1TS U6011 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(n5256), .B0(n4970), .Y(n4974) );
AOI22X1TS U6012 ( .A0(n5098), .A1(n4972), .B0(n4971), .B1(n5515), .Y(n4973)
);
XNOR2X1TS U6013 ( .A(n4974), .B(n4973), .Y(n4975) );
AOI22X1TS U6014 ( .A0(n2197), .A1(n4975), .B0(n5194), .B1(n5101), .Y(n1347)
);
BUFX3TS U6015 ( .A(n5515), .Y(n5095) );
AOI22X1TS U6016 ( .A0(n5098), .A1(n4977), .B0(n4976), .B1(n5095), .Y(n4980)
);
XNOR2X1TS U6017 ( .A(n4980), .B(n4979), .Y(n4981) );
AOI22X1TS U6018 ( .A0(n2197), .A1(n4981), .B0(n5220), .B1(n5101), .Y(n1346)
);
AOI21X1TS U6019 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(n5257), .B0(n4982), .Y(n4986) );
AOI22X1TS U6020 ( .A0(n5098), .A1(n4984), .B0(n4983), .B1(n5095), .Y(n4985)
);
XNOR2X1TS U6021 ( .A(n4986), .B(n4985), .Y(n4987) );
AOI22X1TS U6022 ( .A0(n2197), .A1(n4987), .B0(n5193), .B1(n5101), .Y(n1345)
);
AOI22X1TS U6023 ( .A0(n5098), .A1(n4989), .B0(n4988), .B1(n5095), .Y(n4992)
);
OAI21XLTS U6024 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n5252), .B0(n4990),
.Y(n4991) );
XNOR2X1TS U6025 ( .A(n4992), .B(n4991), .Y(n4993) );
AOI22X1TS U6026 ( .A0(n2197), .A1(n4993), .B0(n5227), .B1(n5513), .Y(n1344)
);
AOI21X1TS U6027 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(n5259), .B0(n4994), .Y(n4998) );
AOI22X1TS U6028 ( .A0(n5098), .A1(n4996), .B0(n4995), .B1(n5095), .Y(n4997)
);
XNOR2X1TS U6029 ( .A(n4998), .B(n4997), .Y(n4999) );
AOI22X1TS U6030 ( .A0(n2197), .A1(n4999), .B0(n5191), .B1(n5101), .Y(n1343)
);
AOI22X1TS U6031 ( .A0(n5098), .A1(n5001), .B0(n5000), .B1(n5095), .Y(n5004)
);
OAI21XLTS U6032 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n5253), .B0(n5002),
.Y(n5003) );
XNOR2X1TS U6033 ( .A(n5004), .B(n5003), .Y(n5005) );
AOI22X1TS U6034 ( .A0(n2197), .A1(n5005), .B0(n5214), .B1(n5101), .Y(n1342)
);
AOI21X1TS U6035 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(n5260), .B0(n5006), .Y(n5010) );
AOI22X1TS U6036 ( .A0(n5098), .A1(n5008), .B0(n5007), .B1(n5095), .Y(n5009)
);
XNOR2X1TS U6037 ( .A(n5010), .B(n5009), .Y(n5011) );
AOI22X1TS U6038 ( .A0(n5093), .A1(n5011), .B0(n5202), .B1(n5101), .Y(n1341)
);
AOI22X1TS U6039 ( .A0(n2301), .A1(n5013), .B0(n5012), .B1(n5095), .Y(n5016)
);
OAI21XLTS U6040 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n5255), .B0(n5014),
.Y(n5015) );
XNOR2X1TS U6041 ( .A(n5016), .B(n5015), .Y(n5017) );
AOI22X1TS U6042 ( .A0(n5093), .A1(n5017), .B0(n5184), .B1(n5101), .Y(n1340)
);
AOI21X1TS U6043 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(n5265), .B0(n5018), .Y(
n5022) );
AOI22X1TS U6044 ( .A0(n2301), .A1(n5020), .B0(n5019), .B1(n5095), .Y(n5021)
);
XNOR2X1TS U6045 ( .A(n5022), .B(n5021), .Y(n5023) );
AOI22X1TS U6046 ( .A0(n5093), .A1(n5023), .B0(n5196), .B1(n5101), .Y(n1339)
);
AOI22X1TS U6047 ( .A0(n2301), .A1(n5025), .B0(n5024), .B1(n5095), .Y(n5028)
);
OAI21XLTS U6048 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n5258), .B0(n5026),
.Y(n5027) );
XNOR2X1TS U6049 ( .A(n5028), .B(n5027), .Y(n5029) );
AOI22X1TS U6050 ( .A0(n5093), .A1(n5029), .B0(n5203), .B1(n5101), .Y(n1338)
);
AOI21X1TS U6051 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(n5269), .B0(n5030), .Y(
n5034) );
AOI22X1TS U6052 ( .A0(n2301), .A1(n5032), .B0(n5031), .B1(n5095), .Y(n5033)
);
XNOR2X1TS U6053 ( .A(n5034), .B(n5033), .Y(n5035) );
AOI22X1TS U6054 ( .A0(n5093), .A1(n5035), .B0(n5326), .B1(n5513), .Y(n1337)
);
AOI22X1TS U6055 ( .A0(n2301), .A1(n5037), .B0(n5036), .B1(n5515), .Y(n5040)
);
OAI21XLTS U6056 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n5262), .B0(n5038),
.Y(n5039) );
XNOR2X1TS U6057 ( .A(n5040), .B(n5039), .Y(n5041) );
AOI22X1TS U6058 ( .A0(n5093), .A1(n5041), .B0(n5266), .B1(n5513), .Y(n1336)
);
AOI21X1TS U6059 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(n5272), .B0(n5042), .Y(
n5046) );
AOI22X1TS U6060 ( .A0(n2301), .A1(n5044), .B0(n5043), .B1(n5515), .Y(n5045)
);
XNOR2X1TS U6061 ( .A(n5046), .B(n5045), .Y(n5047) );
AOI22X1TS U6062 ( .A0(n5093), .A1(n5047), .B0(n5181), .B1(n5513), .Y(n1335)
);
AOI22X1TS U6063 ( .A0(n2301), .A1(n5049), .B0(n5048), .B1(n5515), .Y(n5052)
);
OAI21XLTS U6064 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n5268), .B0(n5050),
.Y(n5051) );
XNOR2X1TS U6065 ( .A(n5052), .B(n5051), .Y(n5053) );
AOI22X1TS U6066 ( .A0(n5093), .A1(n5053), .B0(n5188), .B1(n5513), .Y(n1334)
);
AOI21X1TS U6067 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(n5280), .B0(n5054), .Y(
n5058) );
AOI22X1TS U6068 ( .A0(n2301), .A1(n5056), .B0(n5055), .B1(n5515), .Y(n5057)
);
XNOR2X1TS U6069 ( .A(n5058), .B(n5057), .Y(n5059) );
AOI22X1TS U6070 ( .A0(n5093), .A1(n5059), .B0(n5315), .B1(n5513), .Y(n1333)
);
NOR2XLTS U6071 ( .A(n2236), .B(n4876), .Y(n5060) );
AOI211X1TS U6072 ( .A0(n5142), .A1(n5061), .B0(n5060), .C0(n5118), .Y(n5150)
);
OAI22X1TS U6073 ( .A0(n5122), .A1(n5302), .B0(n5150), .B1(n5121), .Y(n1331)
);
AO22XLTS U6074 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n5128), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1329) );
AO22XLTS U6075 ( .A0(n2216), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1327) );
BUFX4TS U6076 ( .A(n5517), .Y(n5126) );
AO22XLTS U6077 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1326) );
AO22XLTS U6078 ( .A0(n5131), .A1(FPADDSUB_DMP_SFG[3]), .B0(n5146), .B1(
FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1325) );
AOI22X1TS U6079 ( .A0(n2301), .A1(n5063), .B0(n5062), .B1(n5515), .Y(n5066)
);
OAI21XLTS U6080 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n5271), .B0(n5064),
.Y(n5065) );
XNOR2X1TS U6081 ( .A(n5066), .B(n5065), .Y(n5067) );
AOI2BB2XLTS U6082 ( .B0(n2197), .B1(n5067), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[19]), .A1N(n5093), .Y(n1323) );
AOI21X1TS U6083 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(n5325), .B0(n5068), .Y(
n5072) );
AOI22X1TS U6084 ( .A0(n2301), .A1(n5070), .B0(n5069), .B1(n5515), .Y(n5071)
);
XNOR2X1TS U6085 ( .A(n5072), .B(n5071), .Y(n5073) );
AOI22X1TS U6086 ( .A0(n5093), .A1(n5073), .B0(n5316), .B1(n5513), .Y(n1322)
);
AOI22X1TS U6087 ( .A0(n2301), .A1(n5075), .B0(n5074), .B1(n5515), .Y(n5078)
);
XNOR2X1TS U6088 ( .A(n5078), .B(n5077), .Y(n5079) );
AOI22X1TS U6089 ( .A0(n5093), .A1(n5079), .B0(n5195), .B1(n5513), .Y(n1321)
);
AOI21X1TS U6090 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(n5345), .B0(n5080), .Y(
n5084) );
AOI22X1TS U6091 ( .A0(n2301), .A1(n5082), .B0(n5081), .B1(n5515), .Y(n5083)
);
XNOR2X1TS U6092 ( .A(n5084), .B(n5083), .Y(n5085) );
AOI22X1TS U6093 ( .A0(n5093), .A1(n5085), .B0(n5180), .B1(n5513), .Y(n1319)
);
AOI22X1TS U6094 ( .A0(n2301), .A1(n5087), .B0(n5086), .B1(n5515), .Y(n5090)
);
OAI21XLTS U6095 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n5328), .B0(n5088),
.Y(n5089) );
XNOR2X1TS U6096 ( .A(n5090), .B(n5089), .Y(n5092) );
AOI22X1TS U6097 ( .A0(n5093), .A1(n5092), .B0(n5187), .B1(n5513), .Y(n1318)
);
AOI21X1TS U6098 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n5362), .B0(n5094),
.Y(n5100) );
AOI22X1TS U6099 ( .A0(n5098), .A1(n5097), .B0(n5096), .B1(n5095), .Y(n5099)
);
XNOR2X1TS U6100 ( .A(n5100), .B(n5099), .Y(n5102) );
AOI22X1TS U6101 ( .A0(n2197), .A1(n5102), .B0(n5263), .B1(n5101), .Y(n1317)
);
NOR2XLTS U6102 ( .A(n5104), .B(n4876), .Y(n5105) );
AOI211X1TS U6103 ( .A0(n5142), .A1(n5106), .B0(n5105), .C0(n5118), .Y(n5149)
);
OAI22X1TS U6104 ( .A0(n5122), .A1(n5303), .B0(n5149), .B1(n5121), .Y(n1315)
);
AO22XLTS U6105 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n5128), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1313) );
AO22XLTS U6106 ( .A0(n2216), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1311) );
AO22XLTS U6107 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1310) );
AO22XLTS U6108 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[2]), .B0(n5146), .B1(
FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1309) );
NOR2XLTS U6109 ( .A(n5138), .B(n4876), .Y(n5107) );
AOI211X1TS U6110 ( .A0(n5142), .A1(n5108), .B0(n5107), .C0(n5118), .Y(n5154)
);
OAI22X1TS U6111 ( .A0(n5122), .A1(n5304), .B0(n5154), .B1(n5121), .Y(n1308)
);
AO22XLTS U6112 ( .A0(n2216), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n5128), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1306) );
AO22XLTS U6113 ( .A0(n2216), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1304) );
AO22XLTS U6114 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1303) );
AO22XLTS U6115 ( .A0(n5131), .A1(FPADDSUB_DMP_SFG[7]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1302) );
NOR2XLTS U6116 ( .A(n5109), .B(n4876), .Y(n5110) );
AOI211X1TS U6117 ( .A0(n5142), .A1(n5111), .B0(n5110), .C0(n5118), .Y(n5147)
);
OAI22X1TS U6118 ( .A0(n5122), .A1(n5305), .B0(n5147), .B1(n5121), .Y(n1301)
);
AO22XLTS U6119 ( .A0(n5129), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n5128), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1299) );
AO22XLTS U6120 ( .A0(n5129), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1297) );
AO22XLTS U6121 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1296) );
AO22XLTS U6122 ( .A0(n5131), .A1(FPADDSUB_DMP_SFG[0]), .B0(n5146), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1295) );
NOR2XLTS U6123 ( .A(n5112), .B(n4876), .Y(n5113) );
AOI211X1TS U6124 ( .A0(n5142), .A1(n5114), .B0(n5113), .C0(n5118), .Y(n5148)
);
OAI22X1TS U6125 ( .A0(n5122), .A1(n5306), .B0(n5148), .B1(n5121), .Y(n1294)
);
AO22XLTS U6126 ( .A0(n5129), .A1(FPADDSUB_DmP_EXP_EWSW[1]), .B0(n5128), .B1(
FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1292) );
AO22XLTS U6127 ( .A0(n5129), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n5125), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1290) );
AO22XLTS U6128 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1289) );
AO22XLTS U6129 ( .A0(n5131), .A1(FPADDSUB_DMP_SFG[1]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1288) );
AOI22X1TS U6130 ( .A0(n5176), .A1(n5116), .B0(n5115), .B1(n5142), .Y(n5156)
);
OAI22X1TS U6131 ( .A0(n5122), .A1(n5307), .B0(n5156), .B1(n5121), .Y(n1287)
);
AO22XLTS U6132 ( .A0(n5129), .A1(FPADDSUB_DmP_EXP_EWSW[9]), .B0(n5125), .B1(
FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1285) );
AO22XLTS U6133 ( .A0(n5129), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n5125), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1283) );
AO22XLTS U6134 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n5126), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1282) );
AO22XLTS U6135 ( .A0(n5131), .A1(FPADDSUB_DMP_SFG[9]), .B0(n5146), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1281) );
NOR2XLTS U6136 ( .A(n5117), .B(n4876), .Y(n5119) );
AOI211X1TS U6137 ( .A0(n5142), .A1(n5120), .B0(n5119), .C0(n5118), .Y(n5152)
);
OAI22X1TS U6138 ( .A0(n5122), .A1(n5308), .B0(n5152), .B1(n5121), .Y(n1280)
);
AO22XLTS U6139 ( .A0(n5129), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n5125), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1278) );
AO22XLTS U6140 ( .A0(n5129), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n5125), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1276) );
AO22XLTS U6141 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(n5126), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1275) );
AO22XLTS U6142 ( .A0(n5131), .A1(FPADDSUB_DMP_SFG[5]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1274) );
AO22XLTS U6143 ( .A0(n5129), .A1(FPADDSUB_DmP_EXP_EWSW[12]), .B0(n5125),
.B1(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1272) );
AO22XLTS U6144 ( .A0(n5129), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n5125),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1270) );
AO22XLTS U6145 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1269) );
AO22XLTS U6146 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[12]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1268) );
AO22XLTS U6147 ( .A0(n5129), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n5125),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1266) );
AO22XLTS U6148 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1265) );
AO22XLTS U6149 ( .A0(n5131), .A1(FPADDSUB_DMP_SFG[10]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1264) );
AO22XLTS U6150 ( .A0(n5129), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n5123),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1262) );
AO22XLTS U6151 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1261) );
AO22XLTS U6152 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[14]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1260) );
AO22XLTS U6153 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n5123),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1258) );
AO22XLTS U6154 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1257) );
AO22XLTS U6155 ( .A0(n5131), .A1(FPADDSUB_DMP_SFG[11]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1256) );
AO22XLTS U6156 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n5123), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1254) );
AO22XLTS U6157 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1253) );
AO22XLTS U6158 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[8]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1252) );
AO22XLTS U6159 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n5125),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1250) );
AO22XLTS U6160 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1249) );
AO22XLTS U6161 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[16]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1248) );
AO22XLTS U6162 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n5125),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1246) );
AO22XLTS U6163 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1245) );
AO22XLTS U6164 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[13]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1244) );
AO22XLTS U6165 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n5125), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1242) );
AO22XLTS U6166 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1241) );
AO22XLTS U6167 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[6]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1240) );
AO22XLTS U6168 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n5125), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1238) );
AO22XLTS U6169 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(n5126), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1237) );
AO22XLTS U6170 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[4]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1236) );
AO22XLTS U6171 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n5125),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1234) );
AO22XLTS U6172 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1233) );
AO22XLTS U6173 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[17]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1232) );
AO22XLTS U6174 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n5125),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1230) );
AO22XLTS U6175 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1229) );
AO22XLTS U6176 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[20]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1228) );
AO22XLTS U6177 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n5125),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1226) );
AO22XLTS U6178 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1225) );
AO22XLTS U6179 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[19]), .B0(n5146), .B1(
FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1224) );
AO22XLTS U6180 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n5125),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1222) );
AO22XLTS U6181 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1221) );
AO22XLTS U6182 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[21]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1220) );
AO22XLTS U6183 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n5125),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1218) );
AO22XLTS U6184 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n5126),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1217) );
AO22XLTS U6185 ( .A0(n2206), .A1(FPADDSUB_DMP_SFG[18]), .B0(n5146), .B1(
FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1216) );
AO22XLTS U6186 ( .A0(n5127), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n5128),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1214) );
AO22XLTS U6187 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1213) );
AO22XLTS U6188 ( .A0(n5163), .A1(FPADDSUB_DMP_SFG[15]), .B0(n5172), .B1(
FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1212) );
AO22XLTS U6189 ( .A0(n5129), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n5128),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1210) );
AO22XLTS U6190 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n5517),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1209) );
AO22XLTS U6191 ( .A0(n5131), .A1(FPADDSUB_DMP_SFG[22]), .B0(n5146), .B1(
FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1208) );
AOI22X1TS U6192 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n5133), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n5132), .Y(n5136) );
AOI22X1TS U6193 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n4843), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n5134), .Y(n5135) );
OAI211X1TS U6194 ( .A0(n5138), .A1(n2198), .B0(n5136), .C0(n5135), .Y(n5175)
);
AOI2BB2XLTS U6195 ( .B0(n5142), .B1(n5175), .A0N(n5174), .A1N(n4876), .Y(
n5139) );
INVX2TS U6196 ( .A(n5163), .Y(n5178) );
AOI32X1TS U6197 ( .A0(n5139), .A1(n5178), .A2(n5144), .B0(n5186), .B1(n5163),
.Y(n1207) );
AOI2BB2XLTS U6198 ( .B0(n5142), .B1(n5141), .A0N(n5140), .A1N(n4876), .Y(
n5145) );
AOI32X1TS U6199 ( .A0(n5145), .A1(n5178), .A2(n5144), .B0(n5143), .B1(n5163),
.Y(n1206) );
AOI2BB2XLTS U6200 ( .B0(n5178), .B1(n5147), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[2]), .A1N(n5146), .Y(n1205) );
AOI22X1TS U6201 ( .A0(n5178), .A1(n5148), .B0(n5204), .B1(n2206), .Y(n1204)
);
AOI22X1TS U6202 ( .A0(n5178), .A1(n5149), .B0(n5256), .B1(n2206), .Y(n1203)
);
AOI22X1TS U6203 ( .A0(n5170), .A1(n5150), .B0(n5205), .B1(n2206), .Y(n1202)
);
AOI22X1TS U6204 ( .A0(n5178), .A1(n5151), .B0(n5257), .B1(n2206), .Y(n1201)
);
AOI22X1TS U6205 ( .A0(n5178), .A1(n5152), .B0(n5206), .B1(n2206), .Y(n1200)
);
AOI22X1TS U6206 ( .A0(n5170), .A1(n5153), .B0(n5259), .B1(n2206), .Y(n1199)
);
AOI22X1TS U6207 ( .A0(n5170), .A1(n5154), .B0(n5207), .B1(n2206), .Y(n1198)
);
AOI22X1TS U6208 ( .A0(n5170), .A1(n5155), .B0(n5260), .B1(n2206), .Y(n1197)
);
AOI22X1TS U6209 ( .A0(n5170), .A1(n5156), .B0(n5208), .B1(n2206), .Y(n1196)
);
AOI22X1TS U6210 ( .A0(n5170), .A1(n5157), .B0(n5265), .B1(n2206), .Y(n1195)
);
AOI22X1TS U6211 ( .A0(n5170), .A1(n5158), .B0(n5209), .B1(n2206), .Y(n1194)
);
AOI22X1TS U6212 ( .A0(n5170), .A1(n5159), .B0(n5269), .B1(n5163), .Y(n1193)
);
AOI22X1TS U6213 ( .A0(n5170), .A1(n5160), .B0(n5210), .B1(n5163), .Y(n1192)
);
AOI22X1TS U6214 ( .A0(n5170), .A1(n5161), .B0(n5272), .B1(n5163), .Y(n1191)
);
AOI22X1TS U6215 ( .A0(n5170), .A1(n5162), .B0(n5212), .B1(n5163), .Y(n1190)
);
AOI22X1TS U6216 ( .A0(n5170), .A1(n5164), .B0(n5280), .B1(n5163), .Y(n1189)
);
AOI22X1TS U6217 ( .A0(n5170), .A1(n5165), .B0(n5215), .B1(n5163), .Y(n1188)
);
AOI22X1TS U6218 ( .A0(n5170), .A1(n5166), .B0(n5325), .B1(n5163), .Y(n1187)
);
AOI22X1TS U6219 ( .A0(n5170), .A1(n5167), .B0(n5216), .B1(n5163), .Y(n1186)
);
AOI22X1TS U6220 ( .A0(n5170), .A1(n5169), .B0(n5345), .B1(n5163), .Y(n1185)
);
AOI22X1TS U6221 ( .A0(n5170), .A1(n5171), .B0(n5229), .B1(n5163), .Y(n1184)
);
AOI2BB2XLTS U6222 ( .B0(n5178), .B1(n5173), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[24]), .A1N(n5172), .Y(n1183) );
AOI2BB2XLTS U6223 ( .B0(n5176), .B1(n5175), .A0N(n5174), .A1N(n4848), .Y(
n5179) );
AOI32X1TS U6224 ( .A0(n5179), .A1(n5178), .A2(n5177), .B0(n5371), .B1(n5163),
.Y(n1182) );
endmodule
|
module Example(outA, outB, outC, outD);
parameter OUTPUT = "FOO";
output wire [23:0] outA;
output wire [23:0] outB;
output reg outC, outD;
function automatic [23:0] flip;
input [23:0] inp;
flip = ~inp;
endfunction
generate
if (flip(OUTPUT) == flip("BAR"))
assign outA = OUTPUT;
else
assign outA = 0;
case (flip(OUTPUT))
flip("FOO"): assign outB = OUTPUT;
flip("BAR"): assign outB = 0;
flip("BAZ"): assign outB = "HI";
endcase
genvar i;
initial outC = 0;
for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1)
if (i + 1 == flip(flip("O")))
initial outC = 1;
endgenerate
integer j;
initial begin
outD = 1;
for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1)
if (j + 1 == flip(flip("O")))
outD = 0;
end
endmodule
module top(out);
wire [23:0] a1, a2, a3, a4;
wire [23:0] b1, b2, b3, b4;
wire c1, c2, c3, c4;
wire d1, d2, d3, d4;
Example e1(a1, b1, c1, d1);
Example #("FOO") e2(a2, b2, c2, d2);
Example #("BAR") e3(a3, b3, c3, d3);
Example #("BAZ") e4(a4, b4, c4, d4);
output wire [24 * 8 - 1 + 4 :0] out;
assign out = {
a1, a2, a3, a4,
b1, b2, b3, b4,
c1, c2, c3, c4,
d1, d2, d3, d4};
function signed [31:0] negate;
input integer inp;
negate = ~inp;
endfunction
parameter W = 10;
parameter X = 3;
localparam signed Y = $floor(W / X);
localparam signed Z = negate($floor(W / X));
// `define VERIFY
`ifdef VERIFY
assert property (a1 == 0);
assert property (a2 == 0);
assert property (a3 == "BAR");
assert property (a4 == 0);
assert property (b1 == "FOO");
assert property (b2 == "FOO");
assert property (b3 == 0);
assert property (b4 == "HI");
assert property (c1 == 1);
assert property (c2 == 1);
assert property (c3 == 0);
assert property (c4 == 0);
assert property (d1 == 0);
assert property (d2 == 0);
assert property (d3 == 1);
assert property (d4 == 1);
assert property (Y == 3);
assert property (Z == ~3);
`endif
endmodule
|
/**
* @desc Упрощенный процессор Mu-80
*
* z80asm program/test.asm -o test.bin
*/
module cpu(
input wire clock, // 25 Мгц
input wire [7:0] din, // Входящие данные
output reg [7:0] dout, // Выходные данные
output wire [19:0] address, // Указатель памяти
output reg wren, // Строб записи в память
output wire [3:0] led, // 4 x Светодиода
// Порты
output reg [15:0] port_addr,
output reg [7:0] port_data,
output wire [7:0] port_in,
output reg port_clock
);
assign address = mem ? ap : pc;
assign led = A;
// Модули процессора
// -------------------------------------------------------------------
`include "inc/regs.v" // Объявление регистров
`include "inc/initial.v" // Инициализация
`include "inc/regs_write.v" // Запись в регистр
`include "inc/alu.v" // Арифметико-логическое устройство
`include "inc/decoder.v" // Декодер инструкции
// Процессор работает на прямом фронте _/
// [!] Tip: w_reg = 0/1 на каждом t_state = 0
// w_alu = 0/1 при АЛУ-инструкциях
// -------------------------------------------------------------------
always @(posedge clock) begin
// Как можно проще сделать
case (t_state)
/*
* ДЕКОДЕР: TICK 1
*/
4'h0: begin
// Условия разрешения записи некоторых управляющих битов на
// первом такте.
// Запись в регистр AF из w_r16
w_r16af <= 1'b0;
// Запись в 8-битный регистр (номер w_num)
w_reg <= I_DJNZ |
// Кроме тех, что указывают на (hl)
((I_INCR8 | I_DECR8) & !O_HLMEM_53) |
// Все инструкции, кроме scf / ccf
(I_SSDAA & (o[5:3] < 3'b110)) |
// Загружать в регистр только в том случае, если у операндов нет (hl)
(I_LD & !O_HLMEM_53 & !O_HLMEM_20) |
// В регистр писать на первом такте, если не (hl), и не CP
(I_ALUR8 & !O_HLMEM_20 & (o[5:3] != 3'b111));
// Запись в регистр 16
w_reg16 <= I_ADD_HLR16 | I_INCR16 | I_DECR16 | I_LDSPHL | I_EXDEHL;
// Разрешение на запись флагов
w_flag <= I_ADD_HLR16 | I_SSDAA |
// Записать флаги, кроме (hl)
((I_INCR8 | I_DECR8) & !O_HLMEM_53) |
// Аналогично
(I_ALUR8 & !O_HLMEM_20);
// Установка указателя на память [ap]
mem <= I_LDXXA | I_LDAXX |
// При inc/dec, и операнд указывает на (hl)
(O_HLMEM_53 & (I_INCR8 | I_DECR8)) |
// При ld, один из операндов который указывает на (hl)
(I_LD & ( O_HLMEM_53 | O_HLMEM_20 )) |
// АЛУ-операци с памятью (hl)
(I_ALUR8 & O_HLMEM_20) |
// Указатель на память, есть переход ret/call/jp есть
((I_RET_CCC) & K_JUMP_CCC) |
// Обязательные указатели в память
I_POP16 | I_RET | I_PUSH16 | I_RST | I_EXSPHL;
// Разрешение записи в память
wren <= I_LDXXA | (I_LD & O_HLMEM_53) | I_PUSH16 | I_RST;
// Нужно для того, чтобы знать, писать в ix/iy или нет
postpref <= prefixed;
// Флаг, который указывает, что перед инструкции был IX/IY-префикс (регистр prefix)
// 1. Либо это IX/IY префикс
// 2. Либо CBh - передать префикс далее
prefixed <= (I_PREFIX_IX | I_PREFIX_IY) | (I_BITS & prefixed);
// Сброс защелки порта
port_clock <= 1'b0;
// ------------------------------------------------------
// Выполнение первого такта инструкции
// ------------------------------------------------------
// 00 000 000 nop
if (I_NOP) pc <= pc + 1'b1;
// DD IX префикс
// FD IY префикс
else if (I_PREFIX_IX | I_PREFIX_IY) begin
pc <= pc + 1'b1;
prefix <= I_PREFIX_IY;
end
// 00 001 000 ex af, af`
else if (I_EX_AF) begin
bank_af <= !bank_af;
pc <= pc + 1'b1;
end
// 11 011 001 exx
else if (I_EXX) begin
bank_r <= !bank_r;
pc <= pc + 1'b1;
end
// 11 101 001 jp (hl)
else if (I_JPHL) begin
pc <= HL;
t_state <= 1'b1;
end
// 11 111 001 ld sp, hl
else if (I_LDSPHL) begin
w_r16 <= HL;
w_num16 <= 2'h3;
pc <= pc + 1'b1;
end
// 00 001 0000 djnz *
else if (I_DJNZ) begin
w_num <= `REG_B;
w_r <= B - 1'b1;
// Условие выполнено, далее...
if (B == 1'b1) begin
pc <= pc + 2'h2;
end else begin
pc <= pc + 1'b1;
t_state <= 1'b1;
end
end
// 00 001 1000 jr *
else if (I_JR) begin
t_state <= 1'b1;
pc <= pc + 1'b1;
end
// 00 1cc 000 jr cc, *
else if (I_JR_CC8) begin
// cc = nz, z, nc, c Условие было выполнено
if (f[ o[4] ? `CF : `ZF] == o[3]) begin
t_state <= 1'b1;
pc <= pc + 1'b1;
// Условие не выполнено, пропуск rel8-байта
end else pc <= pc + 2'h2;
end
// 00 xx0 001 ld r16, **
else if (I_LD_R16I) begin
w_num16 <= o[5:4]; // 0=BC, 1=DE, 2=HL, 3=SP
pc <= pc + 1'b1;
t_state <= 1'b1;
end
// 00 xx1 001 ADD HL, <r16>
else if (I_ADD_HLR16) begin
w_r16 <= r_addhl_rr; // Вычисление результата сложения
flags <= f_addhl_rr;
w_num16 <= 2'b10; // Результат записывается в HL
pc <= pc + 1'b1;
end
// 00 0x0 010 ld (bc, de), a
// 00 0x1 010 ld a, (bc,de)
else if (I_LDXXA | I_LDAXX) begin
ap <= o[4] ? DE : BC;
dout <= A;
pc <= pc + 1'b1;
t_state <= 1'b1;
end
// 00 1x0 010 ld (**), (hl,a)
// 00 1x1 010 ld (a,hl), (**)
else if (I_nnnn_HLA) begin
pc <= pc + 1'b1;
t_state <= 1'b1;
end
// 00 xx0 011 inc r16
// 00 xx1 011 dec r16
else if (I_INCR16 | I_DECR16) begin
// Прибавление или вычитание из 16-битного регистра. Флаги не меняются.
w_r16 <= o[5:4] == 2'b00 ? (I_INCR16 ? BC + 1'b1 : BC - 1'b1) :
o[5:4] == 2'b01 ? (I_INCR16 ? DE + 1'b1 : DE - 1'b1) :
o[5:4] == 2'b10 ? (I_INCR16 ? HL + 1'b1 : HL - 1'b1) :
(I_INCR16 ? sp + 1'b1 : sp - 1'b1);
w_num16 <= o[5:4];
pc <= pc + 1'b1;
end
// 00 xxx 100 inc r8
// 00 xxx 101 dec r8
else if (I_INCR8 | I_DECR8) begin
w_r <= r_incdec_r8;
w_num <= {o[5:4], !o[3]};
pc <= pc + 1'b1;
// Если происходит работа с (hl)
if (O_HLMEM_53) begin t_state <= 1'b1; ap <= HL; end
else begin t_state <= 1'b0; flags <= f_incdec_r8; end
end
// 00 xxx 110 ld r8, *
else if (I_LDR8I) begin
pc <= pc + 1'b1;
t_state <= 1'b1;
w_num <= {o[5:4], !o[3]};
end
// 00 xxx 111 = {rlca, rrca, rla, rra, daa, cpl, scf, ccf}
else if (I_SSDAA) begin
w_num <= `REG_A;
pc <= pc + 1'b1;
case (o[5:3])
// [DAA] Вообще не нужная функция. @todo сделать http://www.z80.info/z80syntx.htm#DAA
3'b100: begin w_r <= A; flags <= F[7:0]; end
// CPL
3'b101: begin
// S Z F5 H F3 P/V N C
flags <= { F[7:6], !A[5], 1'b1, !A[3], F[2], 1'b1, F[0]};
w_r <= A ^ 8'hFF;
end
3'b110: flags <= {F[7:5], 1'b0, F[3:2], 1'b0, 1'b1}; // scf
3'b111: flags <= {F[7:5], 1'b0, F[3:2], 1'b0, 1'b0}; // ccf
// rlca, rrca, rla, rra
// Выставление флагов согласовано, как в Z80
default: begin
w_r <= r_gs;
flags <= f_gs_fin;
end
endcase
end
// 01 aaa bbb ld <a>, <b>
else if (I_LD) begin
ap <= HL; // Чтение / Запись в память
w_num <= {o[5:4], !o[3]}; // Для записи в регистр
// HALT - остановить процессор
if (o[5:0] == 6'b110110) begin
// .. и ничего не делать, так и будет тут стоять ..
end
// А. Запись в (hl) 2Т
else if (o[5:3] == 3'b110) begin
dout <= r8_20;
pc <= pc + 1'b1;
t_state <= 1'b1;
end
// B. Чтение из (hl) 2Т
else if (o[2:0] == 3'b110) begin
pc <= pc + 1'b1;
t_state <= 1'b1;
end
// C. Писать из регистра в регистр (1Т)
else begin
w_r <= r8_20;
pc <= pc + 1'b1;
end
end
// 10 aaa rrr <alu> a, r8
else if (I_ALUR8) begin
w_num <= `REG_A;
w_r <= r_alur8[7:0];
flags <= f_alur8;
ap <= HL;
pc <= pc + 1'b1;
// Читать из памяти (hl) операнд
if (O_HLMEM_20) t_state <= 1'b1;
end
// 11 ccc 000 ret <ccc>
// 11 xx0 001 pop r16
// 11 001 001 ret
else if (I_RET_CCC | I_POP16 | I_RET) begin
ap <= sp;
pc <= pc + 1'b1;
t_state <= K_JUMP_CCC | I_POP16 | I_RET;
end
// 11 ccc 010 jp <ccc>
// 11 000 011 jp **
// 11 ccc 100 call <ccc>
else if (I_JP_CCC | I_CALL_CCC | I_JP | I_CALL) begin
// Если Condition не сработал, то пропуск PC + 3
pc <= K_JUMP_CCC | I_JP | I_CALL? pc + 1'b1 : pc + 2'h3;
t_state <= K_JUMP_CCC | I_JP | I_CALL;
end
// 11 xx0 101 push r16
else if (I_PUSH16) begin
// Писать сначала Lo-байт
dout <= o[5:4] == 2'b00 ? C : // BC
o[5:4] == 2'b01 ? E : // DE
o[5:4] == 2'b10 ? L : F; // HL, AF
ap <= sp - 2'h2;
pc <= pc + 1'b1;
t_state <= 1'b1;
end
// 11 aaa 110 <alu> a, *
else if (I_ADDI8) begin
w_num <= `REG_A;
pc <= pc + 1'b1;
t_state <= 1'b1;
end
// 11 aaa 111 rst #
else if (I_RST) begin
ap <= sp - 2'h2;
w_r <= pcn[15:8];
dout <= pcn[7:0];
t_state <= 1'b1;
end
// DI / EI
else if (I_DI | I_EI) begin
pc <= pc + 1'b1;
ie <= I_EI;
end
// EX DE, HL
else if (I_EXDEHL) begin
w_r16 <= HL;
w_num16 <= 2'b01; // Записать HL в DE
ap <= DE;
pc <= pc + 1'b1;
t_state <= 1'b1;
end
// EX (SP), HL
else if (I_EXSPHL) begin
pc <= pc + 1'b1;
ap <= sp;
t_state <= 1'b1;
end
// CB <bit prefix>
else if (I_BITS) begin
t_state <= 1'b1;
ap <= HL;
pc <= pc + 1'b1;
end
// D3 out (*), a
// DB in a, (*)
else if (I_OUT8A | I_INA8) begin
pc <= pc + 1'b1;
t_state <= 2'h1;
end
opc <= din;
end
/* *******************************************************************
* TICK 2
*/
4'h1: begin
// JR, DJNZ, JR cc
if (I_DJNZ || I_JR || I_JR_CC8) begin
pc <= pc + {{8{din[7]}}, din[7:0]} + 1'b1;
t_state <= 1'b0;
end
// LD r16, i16 - lb
else if (I_LD_R16I) begin
w_r16[7:0] <= din;
pc <= pc + 1'b1;
t_state <= 2'h2;
end
// LD (bc, de), a
else if (I_LDXXA) begin
wren <= 1'b0; // Отключить запись в память
mem <= 1'b0; // А также сделать чтение из [PC+1]
t_state <= 1'b0;
end
// LD a, (bc, de)
else if (I_LDAXX) begin
w_reg <= 1'b1; // Запись DIN
w_r <= din; // DIN
w_num <= `REG_A; // в регистр A
mem <= 1'b0;
t_state <= 1'b0;
end
// LD (***) <> [hl | a]
else if (I_nnnn_HLA) begin
ap[7:0] <= din; // Считывание младшего байта смещения
pc <= pc + 1'b1;
t_state <= 2'h2;
end
// INC/DEC (hl)
else if (I_INCR8 | I_DECR8) begin
dout <= r_incdec_r8;
wren <= 1'b1;
t_state <= 2'h2;
w_flag <= 1'b1;
flags <= f_incdec_r8;
end
// LD r8, *
else if (I_LDR8I) begin
// Если данные загружаются в (hl)
if (O_HLMEM_53) begin
ap <= HL;
dout <= din;
mem <= 1'b1;
wren <= 1'b1;
t_state <= 2'h2;
// Либо i8 пишется в регистр
end else begin
w_r <= din;
w_reg <= 1'b1;
t_state <= 1'b0;
end
pc <= pc + 1'b1;
end
// LD (hl), r8 | r8, (HL)
else if (I_LD) begin
// Запись в регистр из памяти
if ((o[2:0] == 3'b110)) begin w_r <= din; w_reg <= 1'b1; end
// Выход
wren <= 1'b0;
mem <= 1'b0;
t_state <= 1'b0;
end
// <ALU> a, (hl)
// <ALU> a, *
else if (I_ALUR8 | I_ADDI8) begin
// CP не писать результат
if (o[5:3] != 3'b111) w_reg <= 1'b1;
w_r <= r_alur8[7:0];
mem <= 1'b0;
w_flag <= 1'b1;
flags <= f_alur8;
t_state <= 1'b0;
if (I_ADDI8) pc <= pc + 1'b1;
end
// RET/RET <ccc>/POP 16
else if (I_RET_CCC | I_POP16 | I_RET) begin
w_r <= din; // Считывание младшего байта
ap <= ap + 1'b1; // К старшему байту
t_state <= 2'h2;
// sp <- sp + 2'h2
w_r16 <= sp + 2'h2;
w_reg16 <= 1'b1;
w_num16 <= 2'h3;
end
// JP **
else if (I_JP_CCC | I_CALL_CCC | I_JP | I_CALL) begin
w_r <= din;
pc <= pc + 1'b1;
t_state <= 2'h2;
end
// JP (HL)
else if (I_JPHL) begin
w_r <= din;
pc <= pc + 1'b1;
t_state <= 2'h2;
end
// PUSH r16
else if (I_PUSH16) begin
// Писать Hi-байт
dout <= o[5:4] == 2'b00 ? B : // BC
o[5:4] == 2'b01 ? D : // DE
o[5:4] == 2'b10 ? H : A; // HL, AF
ap <= ap + 1'b1;
t_state <= 4'h4;
end
// RST #
else if (I_RST) begin
dout <= w_r;
ap <= ap + 1'b1;
pc <= {o[5:3], 3'b000};
t_state <= 4'h4;
end
// EX DE, HL
else if (I_EXDEHL) begin
w_r16 <= ap;
w_num16 <= 2'b10; // Записать DE в HL
t_state <= 1'b0;
end
// EX (SP), HL
else if (I_EXSPHL) begin
w_r16[7:0] <= din;
ap <= ap + 1'b1;
t_state <= 2'h2;
end
// BIT операции
else if (I_BITS) begin
pc <= pc + 1'b1;
opc_cb <= din;
prefixed <= 1'b0;
// Продолжить считывание из (hL)
if (O_HLMEM_20) begin
mem <= 1'b1;
t_state <= 2'h2;
end
// Либо сразу обработать регистр
else begin
t_state <= 1'b0;
w_flag <= gc[7:6] < 2'h2; // Только для ShGrp / BIT
w_reg <= gc[7:6] != 2'b01; // Писать результат всем, кроме bit
w_num <= {gc[2:1], !gc[0]}; // Куда писать
w_r <= r_gs_fin; // Что писать
flags <= f_gs_fin;
end
end
// OUT (*), A -- вывод данных в порт
else if (I_OUT8A) begin
port_addr <= din;
port_data <= A;
port_clock <= 1'b1;
t_state <= 1'b0;
end
end
/* *******************************************************************
* TICK 3
*/
4'h2: begin
// LD r16, i16 - hb
if (I_LD_R16I) begin
w_r16[15:8] <= din;
pc <= pc + 1'b1;
w_reg16 <= 1'b1;
t_state <= 1'b0;
end
// LD (***) <> [hl | a]
else if (I_nnnn_HLA) begin
ap[15:8] <= din;
pc <= pc + 1'b1;
mem <= 1'b1; // Указатель на память (для чтения/записи)
dout <= o[4] ? A : L; // Пишем либо L, либо A
t_state <= 4'h3;
// Начать писать в память в случае ld (**), [hl | a]
if (o[3] == 1'b0) wren <= 1'b1;
end
// INC/DEC (hl), LD (HL), *
else if (I_INCR8 | I_DECR8 | I_LDR8I) begin
wren <= 1'b0;
mem <= 1'b0;
t_state <= 1'b0;
end
// RET/RET <ccc>
else if (I_RET_CCC | I_RET) begin
// Переход на адрес, полученный из стека
pc <= {din[7:0], w_r[7:0]};
mem <= 1'b0;
w_reg16 <= 1'b0;
t_state <= 1'b0;
end
// POP R16
else if (I_POP16) begin
// Полученные из стека данные
w_r16 <= {din[7:0], w_r[7:0]};
w_r16af <= o[5:4] == 2'b11; // Писать в AF при POP AF
w_num16 <= o[5:4]; // Куда писать результат
mem <= 1'b0;
t_state <= 1'b0;
end
// JP (HL), JP, CALL
else if (I_JPHL | I_JP_CCC| I_CALL_CCC | I_JP | I_CALL) begin
w_r <= pcn[15:8]; // hi-байт
dout <= pcn[7:0]; // lo-байт
ap <= sp - 2'h2;
pc <= {din[7:0], w_r[7:0]};
// Сохранение в стек
if (I_CALL_CCC | I_CALL) begin
wren <= 1'b1;
mem <= 1'b1;
t_state <= 4'h3;
end else t_state <= 1'b0;
end
// EX (SP), HL
else if (I_EXSPHL) begin
w_r16[15:8] <= din;
w_reg16 <= 1'b1; // Писать в HL значение из памяти
w_num16 <= 2'h2; // в 2=HL
ap <= ap - 1'b1; // Теперь писать в память что было в HL
dout <= L; // Писать младший байт в память
w_r <= H; // Сохранить прежнее значение HL
wren <= 1'b1;
t_state <= 2'h3;
end
// Битовые операции над HL
else if (I_BITS) begin
t_state <= 3'h4;
w_flag <= gc[7:6] < 2'h2; // Только для ShGrp / BIT
wren <= 1'b1;
w_num <= {gc[2:1], !gc[0]}; // Куда писать
dout <= r_gs_fin; // Что писать
flags <= f_gs_fin;
end
end
/* *******************************************************************
* TICK 4
*/
4'h3: begin
// LD (***) <> [hl | a]
if (I_nnnn_HLA) begin
// Запись из памяти в регистр: o[4] = (L, A)
if (o[3]) begin
w_r <= din;
w_num <= o[4] ? `REG_A : `REG_L; // Читаем также (зависит от o[3])
w_reg <= 1'b1;
// Если записываем в A, то выход из процедуры
if (o[4]) begin
mem <= 1'b0;
t_state <= 1'b0;
// Иначе будем писать H на следующем этапе
end else begin
t_state <= 4'h4;
ap <= ap + 1'b1;
end
// Запись в память из A, H
end else begin
// Если была запись регистра A, отключение записи в память, переход к 0-му состоянию
if (o[4]) begin
mem <= 1'b0;
wren <= 1'b0;
t_state <= 1'b0;
// Иначе пишем H
end else begin
dout <= H;
ap <= ap + 1'b1;
t_state <= 4'h4;
end
end
end
// CALL
else if (I_CALL_CCC | I_CALL) begin
dout <= w_r;
ap <= ap + 1'b1;
t_state <= 4'h4;
end
// EX (SP), HL
else if (I_EXSPHL) begin
dout <= w_r;
ap <= ap + 1'b1;
t_state <= 4'h4;
w_reg16 <= 1'b0;
end
end
/* *******************************************************************
* TICK 5
*/
4'h4: begin
// LD (***) <> [hl | a]
if (I_nnnn_HLA) begin
// Запись в H, и выход
if (o[3]) begin w_num <= `REG_H; w_r <= din; end
// Выход и закрытие сохранении в память
mem <= 1'b0;
wren <= 1'b0;
t_state <= 1'b0;
end
// CALL
else if (I_CALL_CCC | I_CALL | I_PUSH16 | I_RST) begin
wren <= 1'b0;
mem <= 1'b0;
t_state <= 1'b0;
// sp = sp - 2
w_reg16 <= 1'b1;
w_r16 <= sp - 2'h2;
w_num16 <= 3'h3;
end
// EX (SP), HL Просто завершить запись
else if (I_EXSPHL | I_BITS) begin
wren <= 1'b0;
mem <= 1'b0;
t_state <= 1'b0;
end
end
endcase
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO
* ====
*
* Implementation notes:
*
* - Read and write pointers are simple ring counters
*
* - Number of items held in FIFO is recorded in shift register
* (Full/empty flags are most and least-significant bits of register)
*
* - Supports input and/or output registers on FIFO
*
* Examples:
*
* fifo_v #(.fifo_elements_t(int), .size(8)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers.
*
* fifo_v #(.fifo_elements_t(int), .size(8), .output_reg(1)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers with output register
*
* Output Register
* ===============
*
* Instantiate a FIFO of length (size-1) + an output register and bypass logic
*
* output_reg = 0 (default) - no output register
* output_reg = 1 - instantiate a single output register
*
* _
* ______ |\ | |
* _|-[_FIFO_]-->| |__| |__ Out
* |----------->| | |_|
* bypass |/ Reg.
*
*
* Input Register
* ==============
*
* input_reg = 0 (default) - no input register, FIFO receives data directly
* input_reg = 1 - assume **external** input register and bypass logic
* input_reg = 2 - instantiate input register and bypass logic
*
* In case 1. the FIFO is still of length 'size' as it is assumed the external
* input register is always enabled (used when building VC buffers).
*
* _ ______ |\
* | | |-[_FIFO_]-->| |___ Out
* | |__|___________>| |
* |_| |/
* Reg.
*
* Input and Output Registers
* ==========================
*
* Can set input_reg=2, output_reg=1 to create FIFO with both input and output
* registers. FIFO behaviour remains identical at the cycle-level with the
* addition of input/output registers.
*
* InReg OutReg
* _ ______ _
* | |---[_FIFO_]---| |
* | | |____________| |___|\
* |_| | |_| | |__ Out
* |__________________| |
* |/
* FIFO Initialisation
* ===================
*
* init_fifo_contents = 0 - FIFO is empty on reset
* init_fifo_contents = 1 - FIFO is nearly_full on reset (mem[i]=1'b1<<i, mem[size]=0)
* init_fifo_contents = 2 - FIFO is nearly empty on reset (mem[0]=1)
*
*
* ===============================================================================
*/
// other FIFO types: double buffered, two slower FIFOs + output register
// FIFOs with second entry outputs (as required by router)
// pending write input register
//
// - second output with output registers [two output registers?]
//
//`ifdef VCS
//import fifo_package::*;
//`endif
/************************************************************************************
*
* FIFO
*
************************************************************************************/
//typedef flit_t fifo_elements_t;
typedef struct packed
{
logic full, empty, nearly_full, nearly_empty;
} fifov_flags_t;
`include "types.v"
module LAG_fifo_v_ (push, pop, data_in, data_out, flags, clk, rst_n);
// max no. of entries
parameter size = 8;
input push, pop;
output fifov_flags_t flags;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
logic fifo_push, fifo_pop;
fifo_elements_t fifo_data_out, data_out_tmp;
fifo_buffer_ #(.size(size))
fifo_buf (push, pop, data_in, data_out_tmp, clk, rst_n);
assign data_out = flags.empty ? '0 : data_out_tmp;
fifo_flags_ #(.size(size))
gen_flags(push, pop, flags, clk, rst_n);
endmodule // fifo_v
/************************************************************************************
*
* Maintain FIFO flags (full, nearly_full, nearly_empty and empty)
*
* This design uses a shift register to ensure flags are available quickly.
*
************************************************************************************/
module fifo_flags_ (push, pop, flags, clk, rst_n);
input push, pop;
output fifov_flags_t flags;
input clk, rst_n;
parameter size = 8;
reg [size:0] counter; // counter must hold 1..size + empty state
logic was_push, was_pop;
fifov_flags_t flags_reg;
logic add, sub, same;
/*
* maintain flags
*
*
* maintain shift register as counter to determine if FIFO is full or empty
* full=counter[size-1], empty=counter[0], etc..
* init: counter=1'b1;
* (push & !pop): shift left
* (pop & !push): shift right
*/
always@(posedge clk) begin
if (!rst_n) begin
counter<={{size{1'b0}},1'b1};
was_push<=1'b0;
was_pop<=1'b0;
end else begin
if (add) begin
assert (counter!={1'b1,{size{1'b0}}}) else $fatal;
counter <= {counter[size-1:0], 1'b0};
end else if (sub) begin
assert (counter!={{size{1'b0}},1'b1}) else $fatal;
counter <= {1'b0, counter[size:1]};
end
assert (counter!=0) else $fatal;
was_push<=push;
was_pop<=pop;
assert (push!==1'bx) else $fatal;
assert (pop!==1'bx) else $fatal;
end // else: !if(!rst_n)
end
assign add = was_push && !was_pop;
assign sub = was_pop && !was_push;
assign same = !(add || sub);
assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);
assign flags.empty = (counter[0] && !add) || (counter[1] && sub);
assign flags.nearly_full = (counter[size-1:0] && same) || (counter[size] && sub) || (counter[size-2] && add);
assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);
endmodule // fifo_flags
/************************************************************************************
*
* Simple core FIFO module
*
************************************************************************************/
module fifo_buffer_ (push, pop, data_in, data_out, clk, rst_n);
// max no. of entries
parameter int unsigned size = 4;
input push, pop;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
// reg [size-1:0] rd_ptr, wt_ptr;
logic unsigned [size-1:0] rd_ptr, wt_ptr;
fifo_elements_t fifo_mem[0:size-1];
logic select_bypass;
integer i,j;
always@(posedge clk) begin
assert (size>=2) else $fatal();
if (!rst_n) begin
rd_ptr<={{size-1{1'b0}},1'b1};
wt_ptr<={{size-1{1'b0}},1'b1};
end else begin
if (push) begin
// enqueue new data
for (i=0; i<size; i++) begin
if (wt_ptr[i]==1'b1) begin
fifo_mem[i] <= data_in;
end
end
end
if (push) begin
// rotate write pointer
wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};
end
if (pop) begin
// rotate read pointer
rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
/*
*
* FIFO output is item pointed to by read pointer
*
*/
always_comb begin
//
// one bit of read pointer is always set, ensure synthesis tool
// doesn't add logic to force a default
//
data_out = 'x;
for (j=0; j<size; j++) begin
if (rd_ptr[j]==1'b1) begin
// output entry pointed to by read pointer
data_out = fifo_mem[j];
end
end
end
endmodule // fifo_buffer
|
////////////////////////////////////////////////////////////////
// File: measure_position.v
// Author: T. Dotsikas, B. Brown
// About: Locate center (x,y) position of object
////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
module measure_position #(
parameter INPUT_WIDTH = 11,
parameter COLOR_WIDTH = 10,
parameter FRAME_X_MAX = 640,
parameter FRAME_Y_MAX = 480,
parameter COUNT_THRESH = 40
)( //////////// CLOCK //////////
input clk,
//////////// DATA ///////////
input wire [(INPUT_WIDTH-1):0] vga_x,
input wire [(INPUT_WIDTH-1):0] vga_y,
input wire [(COLOR_WIDTH-1):0] delta_frame,
output wire [(INPUT_WIDTH-1):0] x_position,
output wire [(INPUT_WIDTH-1):0] y_position,
output wire xy_valid,
//////////// CONTROL ///////////
input wire aresetn,
input wire enable
);
// Internal Signals (widths determined based on max x and y values)
reg [18:0] total_count;
reg [26:0] x_coordinate_sum;
reg [26:0] y_coordinate_sum;
// Wrappers
reg [(INPUT_WIDTH-1):0] int_x_position;
reg [(INPUT_WIDTH-1):0] int_y_position;
reg int_xy_valid;
assign x_position = int_x_position;
assign y_position = int_y_position;
assign xy_valid = int_xy_valid;
// These are the three values used in the algorithm
always @(posedge clk or negedge aresetn) begin
// Reset
if (~aresetn)
begin
total_count <= 'd0;
x_coordinate_sum <= 'd0;
y_coordinate_sum <= 'd0;
end
// Enable
else if (~enable)
begin
total_count <= 'd0;
x_coordinate_sum <= 'd0;
y_coordinate_sum <= 'd0;
end
// Clear at end of frame
else if (vga_x == FRAME_X_MAX & vga_y == FRAME_Y_MAX)
begin
total_count <= 'd0;
x_coordinate_sum <= 'd0;
y_coordinate_sum <= 'd0;
end
// Check if all bits are 1, if so apply algorithm
else if (&delta_frame)
begin
total_count <= total_count + 1;
x_coordinate_sum <= x_coordinate_sum + vga_x;
y_coordinate_sum <= y_coordinate_sum + vga_y;
end
// Otherwise latch the values
else
begin
total_count <= total_count;
x_coordinate_sum <= x_coordinate_sum;
y_coordinate_sum <= y_coordinate_sum;
end
end
// Generate the algorithm result using the above values
always @(posedge clk or negedge aresetn) begin
// Reset
if (~aresetn)
begin
int_xy_valid <= 1'b0;
int_x_position <= 'd0;
int_y_position <= 'd0;
end
// Enable
else if (~enable)
begin
int_xy_valid <= 1'b0;
int_x_position <= 'd0;
int_y_position <= 'd0;
end
// Pulse result at end of frame
else if (vga_x == FRAME_X_MAX & vga_y == FRAME_Y_MAX)
begin
int_xy_valid <= 1'b1;
// Places a criteria on number of pixels that define an object
if (total_count < COUNT_THRESH)
begin
int_x_position <= {INPUT_WIDTH {1'b1}};
int_y_position <= {INPUT_WIDTH {1'b1}};
end
else
begin
int_x_position <= x_coordinate_sum / total_count;
int_y_position <= y_coordinate_sum / total_count;
end
end
else
begin
int_xy_valid <= 1'b0;
int_x_position <= int_x_position;
int_y_position <= int_y_position;
end
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_counters(
input sys_clk,
input first,
input next,
input [6:0] hmesh_last,
input [6:0] vmesh_last,
output [31:0] r0,
output [31:0] r1,
output reg last
);
reg [6:0] r0r;
assign r0 = {25'd0, r0r};
reg [6:0] r1r;
assign r1 = {25'd0, r1r};
always @(posedge sys_clk) begin
if(first) begin
r0r <= 7'd0;
r1r <= 7'd0;
end else if(next) begin
if(r0r == hmesh_last) begin
r0r <= 7'd0;
r1r <= r1r + 7'd1;
end else
r0r <= r0r + 7'd1;
end
end
/* Having some latency in the generation of "last"
* is not a problem, because DMA is never immediately
* triggered after "first" or "next" has been
* asserted.
*/
always @(posedge sys_clk)
last <= (r0r == hmesh_last) & (r1r == vmesh_last);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:38:07 04/17/2016
// Design Name: Comparator
// Module Name: D:/Documents/College/CalPolyPomona/SeniorProject/hardware-accelerated-dna-matching-and-variation-detection/Hardware/Verilog/Comparator_tf.v
// Project Name: Verilog
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Comparator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Comparator_tf;
// Inputs
reg clock;
reg [63:0] data;
reg [63:0] key;
// Outputs
wire match;
// Instantiate the Unit Under Test (UUT)
Comparator uut (
.clock(clock),
.data(data),
.key(key),
.match(match)
);
initial begin
clock = 0;
repeat (1_000_000)
#1 clock =~ clock;
end
initial begin
// Initialize 64-bit data and a template of the same 64-bit data.
// Expect: match = 1
data = 64'b0010000011000111101000010111011010101010111110100110100111100111;
key = 64'b0010000011000111101000010111011010101010111110100110100111100111;
@(posedge clock);
// Change template to a different 64-bit data.
// Expect: match = 0
@(negedge clock) key = 64'b0010000011000110101000010111011010101010111110100110100111100111;
// Change template to a smaller size.
// Expect: match = 0
@(negedge clock) key = 6'b001000;
// Change data to same size as template and same data.
// Expect: match = 1
@(negedge clock) data = 6'b001000;
// Change the data of same size to different data.
// Expect: match = 0
@(negedge clock) data = 6'b001100;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_64x14.v,v $
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_spram_64x14(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 14;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [1:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [1:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x14 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x14_bist artisan_ssp(
`else
art_hssp_64x14 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x14 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x14_bist vs_ssp(
`else
vs_hdsp_64x14 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({2'b00, di[13:0]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[13:0]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
RAMB16_S18 ramb16_s18(
.CLK(clk),
.SSR(rst),
.ADDR({4'b0000, addr}),
.DI({2'b00, di[13:0]}),
.DIP(2'b00),
.EN(ce),
.WE(we),
.DO({unconnected, doq[13:0]}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
module alu_tb;
wire signed [31:0] Z;
reg signed [31:0] A = 0, B = 0;
wire [31:0] uA = A, uB = B; // Unsigned A, B.
reg [5:0] ALUFun = 0;
reg sign = 1;
alu alu1(.Z (Z),
.A (A),
.B (B),
.ALUFun(ALUFun),
.Sign (sign));
initial begin
#5 $display("ADD: S = A + B.");
ALUFun = 6'b000000;
A = 10; // 1010
B = 3; // 0011
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("SUB: S = A - B.");
ALUFun = 6'b000001;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("AND: S = A & B.");
ALUFun = 6'b011000;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("OR: S = A | B.");
ALUFun = 6'b011110;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("XOR: S = A ^ B.");
ALUFun = 6'b010110;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("NOR: S = ~(A | B).");
ALUFun = 6'b010001;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("\"A\": S = A.");
ALUFun = 6'b011010;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("SLL: S = B << A[4:0].");
ALUFun = 6'b100000;
A = 3;
B = 10;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("SRL: S = B >> A[4:0].");
ALUFun = 6'b100001;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
B = -1;
A = 3;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("SRA: S = B >> A[4:0] 算数移位.");
ALUFun = 6'b100011;
A = 3;
B = 10;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
B = -1;
A = 3;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("EQ: if (A == B) S = 1 else S = 0.");
ALUFun = 6'b110011;
A = 1;
B = 1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 1;
B = 0;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 0;
B = 1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("NEQ: if (A != B) S = 1 else S = 0.");
ALUFun = 6'b110001;
A = 1;
B = 1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 1;
B = 0;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 0;
B = 1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("LT: if (A < B) S = 1 else S = 0.");
ALUFun = 6'b110101;
A = 1;
B = 1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 1;
B = 0;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 0;
B = 1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("Unsigned LT: if (A < B) S = 1 else S = 0.");
sign = 0;
ALUFun = 6'b110101;
A = 1;
B = -1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, uA, uB, ALUFun);
A = 1;
B = 0;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, uA, uB, ALUFun);
A = 1;
B = (1'b1 << 31) + (1'b1 << 30);
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, uA, uB, ALUFun);
sign = 1;
$display("LEZ: if (A <= 0) S = 1 else S = 0.");
ALUFun = 6'b111101;
B = 0;
A = -1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 0;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("GEZ: if (A >= 0) S = 1 else S = 0.");
ALUFun = 6'b111001;
A = -1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 0;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
$display("GTZ: if (A > 0) S = 1 else S = 0.");
ALUFun = 6'b111111;
A = -1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 1;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
A = 0;
#5 $display(" Z: %d, A: %d, B: %d, ALUFun: %b", Z, A, B, ALUFun);
end
endmodule
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module AccumulatorTest;
wire [7:0] w_a;
wire w_n;
wire w_z;
wire w_c;
wire w_v;
reg [7:0] r_a;
reg [7:0] r_m;
reg r_c;
reg r_d;
reg r_s;
reg clk;
MC6502Accumulator dut(
.i_a(r_a),
.i_m(r_m),
.i_c(r_c),
.i_d(r_d),
.i_s(r_s),
.o_a(w_a),
.o_n(w_n),
.o_z(w_z),
.o_c(w_c),
.o_v(w_v));
always #1 clk = !clk;
always @ (posedge clk) begin
$display("result = %04b_%04b, n=%b, z=%b, c=%b, v=%b",
w_a[7:4], w_a[3:0], w_n, w_z, w_c, w_v);
end
initial begin
$dumpfile("Accumulator.vcd");
$dumpvars(0, dut);
clk <= 1'b0;
r_d <= 1'b0;
r_s <= 1'b0;
// From Example 2.1
r_a <= 8'b00001101;
r_m <= 8'b11010011;
r_c <= 1'b1;
#2
// From Example 2.2
r_a <= 8'b11111110;
r_m <= 8'b00000110;
r_c <= 1'b1;
#2
// From Example 2.6
r_a <= 8'b00000101;
r_m <= 8'b00000111;
r_c <= 1'b0;
#2
// From Example 2.7
r_a <= 8'b01111111;
r_m <= 8'b00000010;
r_c <= 1'b1;
#2
// From Example 2.8
r_a <= 8'b00000101;
r_m <= 8'b11111101;
r_c <= 1'b0;
#2
// From Example 2.9
r_a <= 8'b00000101;
r_m <= 8'b11111001;
r_c <= 1'b0;
#2
// From Example 2.10
r_a <= 8'b11111011;
r_m <= 8'b11111001;
r_c <= 1'b0;
#2
// From Example 2.11
r_a <= 8'b10111110;
r_m <= 8'b10111111;
r_c <= 1'b0;
#2
// From Example 2.12
r_a <= 8'b01111001;
r_m <= 8'b00010100;
r_c <= 1'b0;
r_d <= 1'b1;
#2
// From Example 2.13
r_a <= 8'b00000101;
r_m <= 8'b00000011;
r_c <= 1'b1;
r_d <= 1'b0;
r_s <= 1'b1;
#2
// From example 2.14
r_a <= 8'b00000101;
r_m <= 8'b00000110;
r_c <= 1'b1;
#2
// From example 2.18
r_a <= 8'b01000100;
r_m <= 8'b00101001;
r_c <= 1'b1;
r_d <= 1'b1;
#2
$finish;
end
endmodule // AccumulatorTest
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_PP_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A, A, LVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood_pp0_out_A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_1_V
`define SKY130_FD_SC_HS__DLRBN_1_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrbn_1 (
RESET_B,
D ,
GATE_N ,
Q ,
Q_N ,
VPWR ,
VGND
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
output Q_N ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlrbn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q),
.Q_N(Q_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlrbn_1 (
RESET_B,
D ,
GATE_N ,
Q ,
Q_N
);
input RESET_B;
input D ;
input GATE_N ;
output Q ;
output Q_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlrbn base (
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.Q(Q),
.Q_N(Q_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_1_V
|
// DE0_NANO_SOC_QSYS_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 209 at 2014.12.18.15:53:15
`timescale 1 ps / 1 ps
module DE0_NANO_SOC_QSYS_mm_interconnect_0 (
input wire pll_sys_outclk0_clk, // pll_sys_outclk0.clk
input wire nios2_qsys_reset_n_reset_bridge_in_reset_reset, // nios2_qsys_reset_n_reset_bridge_in_reset.reset
input wire onchip_memory2_reset1_reset_bridge_in_reset_reset, // onchip_memory2_reset1_reset_bridge_in_reset.reset
input wire [19:0] nios2_qsys_data_master_address, // nios2_qsys_data_master.address
output wire nios2_qsys_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_qsys_data_master_byteenable, // .byteenable
input wire nios2_qsys_data_master_read, // .read
output wire [31:0] nios2_qsys_data_master_readdata, // .readdata
output wire nios2_qsys_data_master_readdatavalid, // .readdatavalid
input wire nios2_qsys_data_master_write, // .write
input wire [31:0] nios2_qsys_data_master_writedata, // .writedata
input wire nios2_qsys_data_master_debugaccess, // .debugaccess
input wire [19:0] nios2_qsys_instruction_master_address, // nios2_qsys_instruction_master.address
output wire nios2_qsys_instruction_master_waitrequest, // .waitrequest
input wire nios2_qsys_instruction_master_read, // .read
output wire [31:0] nios2_qsys_instruction_master_readdata, // .readdata
output wire nios2_qsys_instruction_master_readdatavalid, // .readdatavalid
output wire [0:0] adc_ltc2308_slave_address, // adc_ltc2308_slave.address
output wire adc_ltc2308_slave_write, // .write
output wire adc_ltc2308_slave_read, // .read
input wire [15:0] adc_ltc2308_slave_readdata, // .readdata
output wire [15:0] adc_ltc2308_slave_writedata, // .writedata
output wire adc_ltc2308_slave_chipselect, // .chipselect
output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address
output wire jtag_uart_avalon_jtag_slave_write, // .write
output wire jtag_uart_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
output wire [8:0] nios2_qsys_jtag_debug_module_address, // nios2_qsys_jtag_debug_module.address
output wire nios2_qsys_jtag_debug_module_write, // .write
output wire nios2_qsys_jtag_debug_module_read, // .read
input wire [31:0] nios2_qsys_jtag_debug_module_readdata, // .readdata
output wire [31:0] nios2_qsys_jtag_debug_module_writedata, // .writedata
output wire [3:0] nios2_qsys_jtag_debug_module_byteenable, // .byteenable
input wire nios2_qsys_jtag_debug_module_waitrequest, // .waitrequest
output wire nios2_qsys_jtag_debug_module_debugaccess, // .debugaccess
output wire [15:0] onchip_memory2_s1_address, // onchip_memory2_s1.address
output wire onchip_memory2_s1_write, // .write
input wire [31:0] onchip_memory2_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_s1_byteenable, // .byteenable
output wire onchip_memory2_s1_chipselect, // .chipselect
output wire onchip_memory2_s1_clken, // .clken
output wire [1:0] sw_s1_address, // sw_s1.address
output wire sw_s1_write, // .write
input wire [31:0] sw_s1_readdata, // .readdata
output wire [31:0] sw_s1_writedata, // .writedata
output wire sw_s1_chipselect, // .chipselect
output wire [0:0] sysid_qsys_control_slave_address, // sysid_qsys_control_slave.address
input wire [31:0] sysid_qsys_control_slave_readdata // .readdata
);
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_instruction_master_agent:av_waitrequest -> nios2_qsys_instruction_master_translator:uav_waitrequest
wire [2:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_instruction_master_translator:uav_burstcount -> nios2_qsys_instruction_master_agent:av_burstcount
wire [31:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_instruction_master_translator:uav_writedata -> nios2_qsys_instruction_master_agent:av_writedata
wire [19:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_instruction_master_translator:uav_address -> nios2_qsys_instruction_master_agent:av_address
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_instruction_master_translator:uav_lock -> nios2_qsys_instruction_master_agent:av_lock
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_instruction_master_translator:uav_write -> nios2_qsys_instruction_master_agent:av_write
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_instruction_master_translator:uav_read -> nios2_qsys_instruction_master_agent:av_read
wire [31:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_instruction_master_agent:av_readdata -> nios2_qsys_instruction_master_translator:uav_readdata
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_instruction_master_translator:uav_debugaccess -> nios2_qsys_instruction_master_agent:av_debugaccess
wire [3:0] nios2_qsys_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_instruction_master_translator:uav_byteenable -> nios2_qsys_instruction_master_agent:av_byteenable
wire nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_instruction_master_agent:av_readdatavalid -> nios2_qsys_instruction_master_translator:uav_readdatavalid
wire nios2_qsys_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_data_master_agent:av_waitrequest -> nios2_qsys_data_master_translator:uav_waitrequest
wire [2:0] nios2_qsys_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_data_master_translator:uav_burstcount -> nios2_qsys_data_master_agent:av_burstcount
wire [31:0] nios2_qsys_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_data_master_translator:uav_writedata -> nios2_qsys_data_master_agent:av_writedata
wire [19:0] nios2_qsys_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_data_master_translator:uav_address -> nios2_qsys_data_master_agent:av_address
wire nios2_qsys_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_data_master_translator:uav_lock -> nios2_qsys_data_master_agent:av_lock
wire nios2_qsys_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_data_master_translator:uav_write -> nios2_qsys_data_master_agent:av_write
wire nios2_qsys_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_data_master_translator:uav_read -> nios2_qsys_data_master_agent:av_read
wire [31:0] nios2_qsys_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_data_master_agent:av_readdata -> nios2_qsys_data_master_translator:uav_readdata
wire nios2_qsys_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_data_master_translator:uav_debugaccess -> nios2_qsys_data_master_agent:av_debugaccess
wire [3:0] nios2_qsys_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_data_master_translator:uav_byteenable -> nios2_qsys_data_master_agent:av_byteenable
wire nios2_qsys_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_data_master_agent:av_readdatavalid -> nios2_qsys_data_master_translator:uav_readdatavalid
wire nios2_qsys_jtag_debug_module_agent_m0_waitrequest; // nios2_qsys_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_jtag_debug_module_agent:m0_waitrequest
wire [2:0] nios2_qsys_jtag_debug_module_agent_m0_burstcount; // nios2_qsys_jtag_debug_module_agent:m0_burstcount -> nios2_qsys_jtag_debug_module_translator:uav_burstcount
wire [31:0] nios2_qsys_jtag_debug_module_agent_m0_writedata; // nios2_qsys_jtag_debug_module_agent:m0_writedata -> nios2_qsys_jtag_debug_module_translator:uav_writedata
wire [19:0] nios2_qsys_jtag_debug_module_agent_m0_address; // nios2_qsys_jtag_debug_module_agent:m0_address -> nios2_qsys_jtag_debug_module_translator:uav_address
wire nios2_qsys_jtag_debug_module_agent_m0_write; // nios2_qsys_jtag_debug_module_agent:m0_write -> nios2_qsys_jtag_debug_module_translator:uav_write
wire nios2_qsys_jtag_debug_module_agent_m0_lock; // nios2_qsys_jtag_debug_module_agent:m0_lock -> nios2_qsys_jtag_debug_module_translator:uav_lock
wire nios2_qsys_jtag_debug_module_agent_m0_read; // nios2_qsys_jtag_debug_module_agent:m0_read -> nios2_qsys_jtag_debug_module_translator:uav_read
wire [31:0] nios2_qsys_jtag_debug_module_agent_m0_readdata; // nios2_qsys_jtag_debug_module_translator:uav_readdata -> nios2_qsys_jtag_debug_module_agent:m0_readdata
wire nios2_qsys_jtag_debug_module_agent_m0_readdatavalid; // nios2_qsys_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_jtag_debug_module_agent:m0_readdatavalid
wire nios2_qsys_jtag_debug_module_agent_m0_debugaccess; // nios2_qsys_jtag_debug_module_agent:m0_debugaccess -> nios2_qsys_jtag_debug_module_translator:uav_debugaccess
wire [3:0] nios2_qsys_jtag_debug_module_agent_m0_byteenable; // nios2_qsys_jtag_debug_module_agent:m0_byteenable -> nios2_qsys_jtag_debug_module_translator:uav_byteenable
wire nios2_qsys_jtag_debug_module_agent_rf_source_endofpacket; // nios2_qsys_jtag_debug_module_agent:rf_source_endofpacket -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_endofpacket
wire nios2_qsys_jtag_debug_module_agent_rf_source_valid; // nios2_qsys_jtag_debug_module_agent:rf_source_valid -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_valid
wire nios2_qsys_jtag_debug_module_agent_rf_source_startofpacket; // nios2_qsys_jtag_debug_module_agent:rf_source_startofpacket -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_startofpacket
wire [96:0] nios2_qsys_jtag_debug_module_agent_rf_source_data; // nios2_qsys_jtag_debug_module_agent:rf_source_data -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_data
wire nios2_qsys_jtag_debug_module_agent_rf_source_ready; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:in_ready -> nios2_qsys_jtag_debug_module_agent:rf_source_ready
wire nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_endofpacket; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> nios2_qsys_jtag_debug_module_agent:rf_sink_endofpacket
wire nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_valid; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_valid -> nios2_qsys_jtag_debug_module_agent:rf_sink_valid
wire nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_startofpacket; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> nios2_qsys_jtag_debug_module_agent:rf_sink_startofpacket
wire [96:0] nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_data; // nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_data -> nios2_qsys_jtag_debug_module_agent:rf_sink_data
wire nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_ready; // nios2_qsys_jtag_debug_module_agent:rf_sink_ready -> nios2_qsys_jtag_debug_module_agent_rsp_fifo:out_ready
wire nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_valid; // nios2_qsys_jtag_debug_module_agent:rdata_fifo_src_valid -> nios2_qsys_jtag_debug_module_agent:rdata_fifo_sink_valid
wire [33:0] nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_data; // nios2_qsys_jtag_debug_module_agent:rdata_fifo_src_data -> nios2_qsys_jtag_debug_module_agent:rdata_fifo_sink_data
wire nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_ready; // nios2_qsys_jtag_debug_module_agent:rdata_fifo_sink_ready -> nios2_qsys_jtag_debug_module_agent:rdata_fifo_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> nios2_qsys_jtag_debug_module_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> nios2_qsys_jtag_debug_module_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> nios2_qsys_jtag_debug_module_agent:cp_startofpacket
wire [95:0] cmd_mux_src_data; // cmd_mux:src_data -> nios2_qsys_jtag_debug_module_agent:cp_data
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> nios2_qsys_jtag_debug_module_agent:cp_channel
wire cmd_mux_src_ready; // nios2_qsys_jtag_debug_module_agent:cp_ready -> cmd_mux:src_ready
wire onchip_memory2_s1_agent_m0_waitrequest; // onchip_memory2_s1_translator:uav_waitrequest -> onchip_memory2_s1_agent:m0_waitrequest
wire [2:0] onchip_memory2_s1_agent_m0_burstcount; // onchip_memory2_s1_agent:m0_burstcount -> onchip_memory2_s1_translator:uav_burstcount
wire [31:0] onchip_memory2_s1_agent_m0_writedata; // onchip_memory2_s1_agent:m0_writedata -> onchip_memory2_s1_translator:uav_writedata
wire [19:0] onchip_memory2_s1_agent_m0_address; // onchip_memory2_s1_agent:m0_address -> onchip_memory2_s1_translator:uav_address
wire onchip_memory2_s1_agent_m0_write; // onchip_memory2_s1_agent:m0_write -> onchip_memory2_s1_translator:uav_write
wire onchip_memory2_s1_agent_m0_lock; // onchip_memory2_s1_agent:m0_lock -> onchip_memory2_s1_translator:uav_lock
wire onchip_memory2_s1_agent_m0_read; // onchip_memory2_s1_agent:m0_read -> onchip_memory2_s1_translator:uav_read
wire [31:0] onchip_memory2_s1_agent_m0_readdata; // onchip_memory2_s1_translator:uav_readdata -> onchip_memory2_s1_agent:m0_readdata
wire onchip_memory2_s1_agent_m0_readdatavalid; // onchip_memory2_s1_translator:uav_readdatavalid -> onchip_memory2_s1_agent:m0_readdatavalid
wire onchip_memory2_s1_agent_m0_debugaccess; // onchip_memory2_s1_agent:m0_debugaccess -> onchip_memory2_s1_translator:uav_debugaccess
wire [3:0] onchip_memory2_s1_agent_m0_byteenable; // onchip_memory2_s1_agent:m0_byteenable -> onchip_memory2_s1_translator:uav_byteenable
wire onchip_memory2_s1_agent_rf_source_endofpacket; // onchip_memory2_s1_agent:rf_source_endofpacket -> onchip_memory2_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_s1_agent_rf_source_valid; // onchip_memory2_s1_agent:rf_source_valid -> onchip_memory2_s1_agent_rsp_fifo:in_valid
wire onchip_memory2_s1_agent_rf_source_startofpacket; // onchip_memory2_s1_agent:rf_source_startofpacket -> onchip_memory2_s1_agent_rsp_fifo:in_startofpacket
wire [96:0] onchip_memory2_s1_agent_rf_source_data; // onchip_memory2_s1_agent:rf_source_data -> onchip_memory2_s1_agent_rsp_fifo:in_data
wire onchip_memory2_s1_agent_rf_source_ready; // onchip_memory2_s1_agent_rsp_fifo:in_ready -> onchip_memory2_s1_agent:rf_source_ready
wire onchip_memory2_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_s1_agent:rf_sink_endofpacket
wire onchip_memory2_s1_agent_rsp_fifo_out_valid; // onchip_memory2_s1_agent_rsp_fifo:out_valid -> onchip_memory2_s1_agent:rf_sink_valid
wire onchip_memory2_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_s1_agent:rf_sink_startofpacket
wire [96:0] onchip_memory2_s1_agent_rsp_fifo_out_data; // onchip_memory2_s1_agent_rsp_fifo:out_data -> onchip_memory2_s1_agent:rf_sink_data
wire onchip_memory2_s1_agent_rsp_fifo_out_ready; // onchip_memory2_s1_agent:rf_sink_ready -> onchip_memory2_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_s1_agent_rdata_fifo_src_valid; // onchip_memory2_s1_agent:rdata_fifo_src_valid -> onchip_memory2_s1_agent:rdata_fifo_sink_valid
wire [33:0] onchip_memory2_s1_agent_rdata_fifo_src_data; // onchip_memory2_s1_agent:rdata_fifo_src_data -> onchip_memory2_s1_agent:rdata_fifo_sink_data
wire onchip_memory2_s1_agent_rdata_fifo_src_ready; // onchip_memory2_s1_agent:rdata_fifo_sink_ready -> onchip_memory2_s1_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> onchip_memory2_s1_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> onchip_memory2_s1_agent:cp_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> onchip_memory2_s1_agent:cp_startofpacket
wire [95:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> onchip_memory2_s1_agent:cp_data
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> onchip_memory2_s1_agent:cp_channel
wire cmd_mux_001_src_ready; // onchip_memory2_s1_agent:cp_ready -> cmd_mux_001:src_ready
wire sysid_qsys_control_slave_agent_m0_waitrequest; // sysid_qsys_control_slave_translator:uav_waitrequest -> sysid_qsys_control_slave_agent:m0_waitrequest
wire [2:0] sysid_qsys_control_slave_agent_m0_burstcount; // sysid_qsys_control_slave_agent:m0_burstcount -> sysid_qsys_control_slave_translator:uav_burstcount
wire [31:0] sysid_qsys_control_slave_agent_m0_writedata; // sysid_qsys_control_slave_agent:m0_writedata -> sysid_qsys_control_slave_translator:uav_writedata
wire [19:0] sysid_qsys_control_slave_agent_m0_address; // sysid_qsys_control_slave_agent:m0_address -> sysid_qsys_control_slave_translator:uav_address
wire sysid_qsys_control_slave_agent_m0_write; // sysid_qsys_control_slave_agent:m0_write -> sysid_qsys_control_slave_translator:uav_write
wire sysid_qsys_control_slave_agent_m0_lock; // sysid_qsys_control_slave_agent:m0_lock -> sysid_qsys_control_slave_translator:uav_lock
wire sysid_qsys_control_slave_agent_m0_read; // sysid_qsys_control_slave_agent:m0_read -> sysid_qsys_control_slave_translator:uav_read
wire [31:0] sysid_qsys_control_slave_agent_m0_readdata; // sysid_qsys_control_slave_translator:uav_readdata -> sysid_qsys_control_slave_agent:m0_readdata
wire sysid_qsys_control_slave_agent_m0_readdatavalid; // sysid_qsys_control_slave_translator:uav_readdatavalid -> sysid_qsys_control_slave_agent:m0_readdatavalid
wire sysid_qsys_control_slave_agent_m0_debugaccess; // sysid_qsys_control_slave_agent:m0_debugaccess -> sysid_qsys_control_slave_translator:uav_debugaccess
wire [3:0] sysid_qsys_control_slave_agent_m0_byteenable; // sysid_qsys_control_slave_agent:m0_byteenable -> sysid_qsys_control_slave_translator:uav_byteenable
wire sysid_qsys_control_slave_agent_rf_source_endofpacket; // sysid_qsys_control_slave_agent:rf_source_endofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_control_slave_agent_rf_source_valid; // sysid_qsys_control_slave_agent:rf_source_valid -> sysid_qsys_control_slave_agent_rsp_fifo:in_valid
wire sysid_qsys_control_slave_agent_rf_source_startofpacket; // sysid_qsys_control_slave_agent:rf_source_startofpacket -> sysid_qsys_control_slave_agent_rsp_fifo:in_startofpacket
wire [96:0] sysid_qsys_control_slave_agent_rf_source_data; // sysid_qsys_control_slave_agent:rf_source_data -> sysid_qsys_control_slave_agent_rsp_fifo:in_data
wire sysid_qsys_control_slave_agent_rf_source_ready; // sysid_qsys_control_slave_agent_rsp_fifo:in_ready -> sysid_qsys_control_slave_agent:rf_source_ready
wire sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_endofpacket -> sysid_qsys_control_slave_agent:rf_sink_endofpacket
wire sysid_qsys_control_slave_agent_rsp_fifo_out_valid; // sysid_qsys_control_slave_agent_rsp_fifo:out_valid -> sysid_qsys_control_slave_agent:rf_sink_valid
wire sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket; // sysid_qsys_control_slave_agent_rsp_fifo:out_startofpacket -> sysid_qsys_control_slave_agent:rf_sink_startofpacket
wire [96:0] sysid_qsys_control_slave_agent_rsp_fifo_out_data; // sysid_qsys_control_slave_agent_rsp_fifo:out_data -> sysid_qsys_control_slave_agent:rf_sink_data
wire sysid_qsys_control_slave_agent_rsp_fifo_out_ready; // sysid_qsys_control_slave_agent:rf_sink_ready -> sysid_qsys_control_slave_agent_rsp_fifo:out_ready
wire sysid_qsys_control_slave_agent_rdata_fifo_src_valid; // sysid_qsys_control_slave_agent:rdata_fifo_src_valid -> sysid_qsys_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] sysid_qsys_control_slave_agent_rdata_fifo_src_data; // sysid_qsys_control_slave_agent:rdata_fifo_src_data -> sysid_qsys_control_slave_agent:rdata_fifo_sink_data
wire sysid_qsys_control_slave_agent_rdata_fifo_src_ready; // sysid_qsys_control_slave_agent:rdata_fifo_sink_ready -> sysid_qsys_control_slave_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sysid_qsys_control_slave_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sysid_qsys_control_slave_agent:cp_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sysid_qsys_control_slave_agent:cp_startofpacket
wire [95:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sysid_qsys_control_slave_agent:cp_data
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sysid_qsys_control_slave_agent:cp_channel
wire cmd_mux_002_src_ready; // sysid_qsys_control_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
wire [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire [19:0] jtag_uart_avalon_jtag_slave_agent_m0_address; // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire jtag_uart_avalon_jtag_slave_agent_m0_write; // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire jtag_uart_avalon_jtag_slave_agent_m0_lock; // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_avalon_jtag_slave_agent_m0_read; // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire [96:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
wire [96:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
wire [95:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_003_src_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux_003:src_ready
wire adc_ltc2308_slave_agent_m0_waitrequest; // adc_ltc2308_slave_translator:uav_waitrequest -> adc_ltc2308_slave_agent:m0_waitrequest
wire [2:0] adc_ltc2308_slave_agent_m0_burstcount; // adc_ltc2308_slave_agent:m0_burstcount -> adc_ltc2308_slave_translator:uav_burstcount
wire [31:0] adc_ltc2308_slave_agent_m0_writedata; // adc_ltc2308_slave_agent:m0_writedata -> adc_ltc2308_slave_translator:uav_writedata
wire [19:0] adc_ltc2308_slave_agent_m0_address; // adc_ltc2308_slave_agent:m0_address -> adc_ltc2308_slave_translator:uav_address
wire adc_ltc2308_slave_agent_m0_write; // adc_ltc2308_slave_agent:m0_write -> adc_ltc2308_slave_translator:uav_write
wire adc_ltc2308_slave_agent_m0_lock; // adc_ltc2308_slave_agent:m0_lock -> adc_ltc2308_slave_translator:uav_lock
wire adc_ltc2308_slave_agent_m0_read; // adc_ltc2308_slave_agent:m0_read -> adc_ltc2308_slave_translator:uav_read
wire [31:0] adc_ltc2308_slave_agent_m0_readdata; // adc_ltc2308_slave_translator:uav_readdata -> adc_ltc2308_slave_agent:m0_readdata
wire adc_ltc2308_slave_agent_m0_readdatavalid; // adc_ltc2308_slave_translator:uav_readdatavalid -> adc_ltc2308_slave_agent:m0_readdatavalid
wire adc_ltc2308_slave_agent_m0_debugaccess; // adc_ltc2308_slave_agent:m0_debugaccess -> adc_ltc2308_slave_translator:uav_debugaccess
wire [3:0] adc_ltc2308_slave_agent_m0_byteenable; // adc_ltc2308_slave_agent:m0_byteenable -> adc_ltc2308_slave_translator:uav_byteenable
wire adc_ltc2308_slave_agent_rf_source_endofpacket; // adc_ltc2308_slave_agent:rf_source_endofpacket -> adc_ltc2308_slave_agent_rsp_fifo:in_endofpacket
wire adc_ltc2308_slave_agent_rf_source_valid; // adc_ltc2308_slave_agent:rf_source_valid -> adc_ltc2308_slave_agent_rsp_fifo:in_valid
wire adc_ltc2308_slave_agent_rf_source_startofpacket; // adc_ltc2308_slave_agent:rf_source_startofpacket -> adc_ltc2308_slave_agent_rsp_fifo:in_startofpacket
wire [96:0] adc_ltc2308_slave_agent_rf_source_data; // adc_ltc2308_slave_agent:rf_source_data -> adc_ltc2308_slave_agent_rsp_fifo:in_data
wire adc_ltc2308_slave_agent_rf_source_ready; // adc_ltc2308_slave_agent_rsp_fifo:in_ready -> adc_ltc2308_slave_agent:rf_source_ready
wire adc_ltc2308_slave_agent_rsp_fifo_out_endofpacket; // adc_ltc2308_slave_agent_rsp_fifo:out_endofpacket -> adc_ltc2308_slave_agent:rf_sink_endofpacket
wire adc_ltc2308_slave_agent_rsp_fifo_out_valid; // adc_ltc2308_slave_agent_rsp_fifo:out_valid -> adc_ltc2308_slave_agent:rf_sink_valid
wire adc_ltc2308_slave_agent_rsp_fifo_out_startofpacket; // adc_ltc2308_slave_agent_rsp_fifo:out_startofpacket -> adc_ltc2308_slave_agent:rf_sink_startofpacket
wire [96:0] adc_ltc2308_slave_agent_rsp_fifo_out_data; // adc_ltc2308_slave_agent_rsp_fifo:out_data -> adc_ltc2308_slave_agent:rf_sink_data
wire adc_ltc2308_slave_agent_rsp_fifo_out_ready; // adc_ltc2308_slave_agent:rf_sink_ready -> adc_ltc2308_slave_agent_rsp_fifo:out_ready
wire adc_ltc2308_slave_agent_rdata_fifo_src_valid; // adc_ltc2308_slave_agent:rdata_fifo_src_valid -> adc_ltc2308_slave_agent:rdata_fifo_sink_valid
wire [33:0] adc_ltc2308_slave_agent_rdata_fifo_src_data; // adc_ltc2308_slave_agent:rdata_fifo_src_data -> adc_ltc2308_slave_agent:rdata_fifo_sink_data
wire adc_ltc2308_slave_agent_rdata_fifo_src_ready; // adc_ltc2308_slave_agent:rdata_fifo_sink_ready -> adc_ltc2308_slave_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> adc_ltc2308_slave_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> adc_ltc2308_slave_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> adc_ltc2308_slave_agent:cp_startofpacket
wire [95:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> adc_ltc2308_slave_agent:cp_data
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> adc_ltc2308_slave_agent:cp_channel
wire cmd_mux_004_src_ready; // adc_ltc2308_slave_agent:cp_ready -> cmd_mux_004:src_ready
wire sw_s1_agent_m0_waitrequest; // sw_s1_translator:uav_waitrequest -> sw_s1_agent:m0_waitrequest
wire [2:0] sw_s1_agent_m0_burstcount; // sw_s1_agent:m0_burstcount -> sw_s1_translator:uav_burstcount
wire [31:0] sw_s1_agent_m0_writedata; // sw_s1_agent:m0_writedata -> sw_s1_translator:uav_writedata
wire [19:0] sw_s1_agent_m0_address; // sw_s1_agent:m0_address -> sw_s1_translator:uav_address
wire sw_s1_agent_m0_write; // sw_s1_agent:m0_write -> sw_s1_translator:uav_write
wire sw_s1_agent_m0_lock; // sw_s1_agent:m0_lock -> sw_s1_translator:uav_lock
wire sw_s1_agent_m0_read; // sw_s1_agent:m0_read -> sw_s1_translator:uav_read
wire [31:0] sw_s1_agent_m0_readdata; // sw_s1_translator:uav_readdata -> sw_s1_agent:m0_readdata
wire sw_s1_agent_m0_readdatavalid; // sw_s1_translator:uav_readdatavalid -> sw_s1_agent:m0_readdatavalid
wire sw_s1_agent_m0_debugaccess; // sw_s1_agent:m0_debugaccess -> sw_s1_translator:uav_debugaccess
wire [3:0] sw_s1_agent_m0_byteenable; // sw_s1_agent:m0_byteenable -> sw_s1_translator:uav_byteenable
wire sw_s1_agent_rf_source_endofpacket; // sw_s1_agent:rf_source_endofpacket -> sw_s1_agent_rsp_fifo:in_endofpacket
wire sw_s1_agent_rf_source_valid; // sw_s1_agent:rf_source_valid -> sw_s1_agent_rsp_fifo:in_valid
wire sw_s1_agent_rf_source_startofpacket; // sw_s1_agent:rf_source_startofpacket -> sw_s1_agent_rsp_fifo:in_startofpacket
wire [96:0] sw_s1_agent_rf_source_data; // sw_s1_agent:rf_source_data -> sw_s1_agent_rsp_fifo:in_data
wire sw_s1_agent_rf_source_ready; // sw_s1_agent_rsp_fifo:in_ready -> sw_s1_agent:rf_source_ready
wire sw_s1_agent_rsp_fifo_out_endofpacket; // sw_s1_agent_rsp_fifo:out_endofpacket -> sw_s1_agent:rf_sink_endofpacket
wire sw_s1_agent_rsp_fifo_out_valid; // sw_s1_agent_rsp_fifo:out_valid -> sw_s1_agent:rf_sink_valid
wire sw_s1_agent_rsp_fifo_out_startofpacket; // sw_s1_agent_rsp_fifo:out_startofpacket -> sw_s1_agent:rf_sink_startofpacket
wire [96:0] sw_s1_agent_rsp_fifo_out_data; // sw_s1_agent_rsp_fifo:out_data -> sw_s1_agent:rf_sink_data
wire sw_s1_agent_rsp_fifo_out_ready; // sw_s1_agent:rf_sink_ready -> sw_s1_agent_rsp_fifo:out_ready
wire sw_s1_agent_rdata_fifo_src_valid; // sw_s1_agent:rdata_fifo_src_valid -> sw_s1_agent:rdata_fifo_sink_valid
wire [33:0] sw_s1_agent_rdata_fifo_src_data; // sw_s1_agent:rdata_fifo_src_data -> sw_s1_agent:rdata_fifo_sink_data
wire sw_s1_agent_rdata_fifo_src_ready; // sw_s1_agent:rdata_fifo_sink_ready -> sw_s1_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sw_s1_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sw_s1_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sw_s1_agent:cp_startofpacket
wire [95:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sw_s1_agent:cp_data
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sw_s1_agent:cp_channel
wire cmd_mux_005_src_ready; // sw_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire nios2_qsys_instruction_master_agent_cp_endofpacket; // nios2_qsys_instruction_master_agent:cp_endofpacket -> router:sink_endofpacket
wire nios2_qsys_instruction_master_agent_cp_valid; // nios2_qsys_instruction_master_agent:cp_valid -> router:sink_valid
wire nios2_qsys_instruction_master_agent_cp_startofpacket; // nios2_qsys_instruction_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [95:0] nios2_qsys_instruction_master_agent_cp_data; // nios2_qsys_instruction_master_agent:cp_data -> router:sink_data
wire nios2_qsys_instruction_master_agent_cp_ready; // router:sink_ready -> nios2_qsys_instruction_master_agent:cp_ready
wire nios2_qsys_data_master_agent_cp_endofpacket; // nios2_qsys_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire nios2_qsys_data_master_agent_cp_valid; // nios2_qsys_data_master_agent:cp_valid -> router_001:sink_valid
wire nios2_qsys_data_master_agent_cp_startofpacket; // nios2_qsys_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire [95:0] nios2_qsys_data_master_agent_cp_data; // nios2_qsys_data_master_agent:cp_data -> router_001:sink_data
wire nios2_qsys_data_master_agent_cp_ready; // router_001:sink_ready -> nios2_qsys_data_master_agent:cp_ready
wire nios2_qsys_jtag_debug_module_agent_rp_endofpacket; // nios2_qsys_jtag_debug_module_agent:rp_endofpacket -> router_002:sink_endofpacket
wire nios2_qsys_jtag_debug_module_agent_rp_valid; // nios2_qsys_jtag_debug_module_agent:rp_valid -> router_002:sink_valid
wire nios2_qsys_jtag_debug_module_agent_rp_startofpacket; // nios2_qsys_jtag_debug_module_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [95:0] nios2_qsys_jtag_debug_module_agent_rp_data; // nios2_qsys_jtag_debug_module_agent:rp_data -> router_002:sink_data
wire nios2_qsys_jtag_debug_module_agent_rp_ready; // router_002:sink_ready -> nios2_qsys_jtag_debug_module_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire [95:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire [5:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire onchip_memory2_s1_agent_rp_endofpacket; // onchip_memory2_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire onchip_memory2_s1_agent_rp_valid; // onchip_memory2_s1_agent:rp_valid -> router_003:sink_valid
wire onchip_memory2_s1_agent_rp_startofpacket; // onchip_memory2_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [95:0] onchip_memory2_s1_agent_rp_data; // onchip_memory2_s1_agent:rp_data -> router_003:sink_data
wire onchip_memory2_s1_agent_rp_ready; // router_003:sink_ready -> onchip_memory2_s1_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [95:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire [5:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire sysid_qsys_control_slave_agent_rp_endofpacket; // sysid_qsys_control_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire sysid_qsys_control_slave_agent_rp_valid; // sysid_qsys_control_slave_agent:rp_valid -> router_004:sink_valid
wire sysid_qsys_control_slave_agent_rp_startofpacket; // sysid_qsys_control_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [95:0] sysid_qsys_control_slave_agent_rp_data; // sysid_qsys_control_slave_agent:rp_data -> router_004:sink_data
wire sysid_qsys_control_slave_agent_rp_ready; // router_004:sink_ready -> sysid_qsys_control_slave_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [95:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire [5:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_005:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_005:sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [95:0] jtag_uart_avalon_jtag_slave_agent_rp_data; // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_005:sink_data
wire jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_005:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire [95:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire adc_ltc2308_slave_agent_rp_endofpacket; // adc_ltc2308_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
wire adc_ltc2308_slave_agent_rp_valid; // adc_ltc2308_slave_agent:rp_valid -> router_006:sink_valid
wire adc_ltc2308_slave_agent_rp_startofpacket; // adc_ltc2308_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [95:0] adc_ltc2308_slave_agent_rp_data; // adc_ltc2308_slave_agent:rp_data -> router_006:sink_data
wire adc_ltc2308_slave_agent_rp_ready; // router_006:sink_ready -> adc_ltc2308_slave_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [95:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire sw_s1_agent_rp_endofpacket; // sw_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire sw_s1_agent_rp_valid; // sw_s1_agent:rp_valid -> router_007:sink_valid
wire sw_s1_agent_rp_startofpacket; // sw_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [95:0] sw_s1_agent_rp_data; // sw_s1_agent:rp_data -> router_007:sink_data
wire sw_s1_agent_rp_ready; // router_007:sink_ready -> sw_s1_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [95:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire [5:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> nios2_qsys_instruction_master_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> nios2_qsys_instruction_master_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> nios2_qsys_instruction_master_limiter:cmd_sink_startofpacket
wire [95:0] router_src_data; // router:src_data -> nios2_qsys_instruction_master_limiter:cmd_sink_data
wire [5:0] router_src_channel; // router:src_channel -> nios2_qsys_instruction_master_limiter:cmd_sink_channel
wire router_src_ready; // nios2_qsys_instruction_master_limiter:cmd_sink_ready -> router:src_ready
wire nios2_qsys_instruction_master_limiter_cmd_src_endofpacket; // nios2_qsys_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_qsys_instruction_master_limiter_cmd_src_startofpacket; // nios2_qsys_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [95:0] nios2_qsys_instruction_master_limiter_cmd_src_data; // nios2_qsys_instruction_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire [5:0] nios2_qsys_instruction_master_limiter_cmd_src_channel; // nios2_qsys_instruction_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire nios2_qsys_instruction_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> nios2_qsys_instruction_master_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_qsys_instruction_master_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_qsys_instruction_master_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_qsys_instruction_master_limiter:rsp_sink_startofpacket
wire [95:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_qsys_instruction_master_limiter:rsp_sink_data
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_qsys_instruction_master_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // nios2_qsys_instruction_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire nios2_qsys_instruction_master_limiter_rsp_src_endofpacket; // nios2_qsys_instruction_master_limiter:rsp_src_endofpacket -> nios2_qsys_instruction_master_agent:rp_endofpacket
wire nios2_qsys_instruction_master_limiter_rsp_src_valid; // nios2_qsys_instruction_master_limiter:rsp_src_valid -> nios2_qsys_instruction_master_agent:rp_valid
wire nios2_qsys_instruction_master_limiter_rsp_src_startofpacket; // nios2_qsys_instruction_master_limiter:rsp_src_startofpacket -> nios2_qsys_instruction_master_agent:rp_startofpacket
wire [95:0] nios2_qsys_instruction_master_limiter_rsp_src_data; // nios2_qsys_instruction_master_limiter:rsp_src_data -> nios2_qsys_instruction_master_agent:rp_data
wire [5:0] nios2_qsys_instruction_master_limiter_rsp_src_channel; // nios2_qsys_instruction_master_limiter:rsp_src_channel -> nios2_qsys_instruction_master_agent:rp_channel
wire nios2_qsys_instruction_master_limiter_rsp_src_ready; // nios2_qsys_instruction_master_agent:rp_ready -> nios2_qsys_instruction_master_limiter:rsp_src_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> nios2_qsys_data_master_limiter:cmd_sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> nios2_qsys_data_master_limiter:cmd_sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> nios2_qsys_data_master_limiter:cmd_sink_startofpacket
wire [95:0] router_001_src_data; // router_001:src_data -> nios2_qsys_data_master_limiter:cmd_sink_data
wire [5:0] router_001_src_channel; // router_001:src_channel -> nios2_qsys_data_master_limiter:cmd_sink_channel
wire router_001_src_ready; // nios2_qsys_data_master_limiter:cmd_sink_ready -> router_001:src_ready
wire nios2_qsys_data_master_limiter_cmd_src_endofpacket; // nios2_qsys_data_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire nios2_qsys_data_master_limiter_cmd_src_startofpacket; // nios2_qsys_data_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire [95:0] nios2_qsys_data_master_limiter_cmd_src_data; // nios2_qsys_data_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire [5:0] nios2_qsys_data_master_limiter_cmd_src_channel; // nios2_qsys_data_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire nios2_qsys_data_master_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> nios2_qsys_data_master_limiter:cmd_src_ready
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_qsys_data_master_limiter:rsp_sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_qsys_data_master_limiter:rsp_sink_valid
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_qsys_data_master_limiter:rsp_sink_startofpacket
wire [95:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_qsys_data_master_limiter:rsp_sink_data
wire [5:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_qsys_data_master_limiter:rsp_sink_channel
wire rsp_mux_001_src_ready; // nios2_qsys_data_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire nios2_qsys_data_master_limiter_rsp_src_endofpacket; // nios2_qsys_data_master_limiter:rsp_src_endofpacket -> nios2_qsys_data_master_agent:rp_endofpacket
wire nios2_qsys_data_master_limiter_rsp_src_valid; // nios2_qsys_data_master_limiter:rsp_src_valid -> nios2_qsys_data_master_agent:rp_valid
wire nios2_qsys_data_master_limiter_rsp_src_startofpacket; // nios2_qsys_data_master_limiter:rsp_src_startofpacket -> nios2_qsys_data_master_agent:rp_startofpacket
wire [95:0] nios2_qsys_data_master_limiter_rsp_src_data; // nios2_qsys_data_master_limiter:rsp_src_data -> nios2_qsys_data_master_agent:rp_data
wire [5:0] nios2_qsys_data_master_limiter_rsp_src_channel; // nios2_qsys_data_master_limiter:rsp_src_channel -> nios2_qsys_data_master_agent:rp_channel
wire nios2_qsys_data_master_limiter_rsp_src_ready; // nios2_qsys_data_master_agent:rp_ready -> nios2_qsys_data_master_limiter:rsp_src_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [95:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [95:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire [5:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire [95:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire [5:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire [95:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire [5:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [95:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
wire [5:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [95:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
wire [5:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [95:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink0_data
wire [5:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_001_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux_001:src4_ready
wire cmd_demux_001_src5_endofpacket; // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_001_src5_valid; // cmd_demux_001:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_001_src5_startofpacket; // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [95:0] cmd_demux_001_src5_data; // cmd_demux_001:src5_data -> cmd_mux_005:sink0_data
wire [5:0] cmd_demux_001_src5_channel; // cmd_demux_001:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_001_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux_001:src5_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [95:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire [95:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire [5:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire [95:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire [95:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire [5:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire [95:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
wire [95:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_001:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
wire [95:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_001:sink4_data
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_001:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux_001:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux_001:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux_001:sink5_startofpacket
wire [95:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux_001:sink5_data
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux_001:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux_001:sink5_ready -> rsp_demux_005:src0_ready
wire [5:0] nios2_qsys_instruction_master_limiter_cmd_valid_data; // nios2_qsys_instruction_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [5:0] nios2_qsys_data_master_limiter_cmd_valid_data; // nios2_qsys_data_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_instruction_master_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_qsys_instruction_master_read), // .read
.av_readdata (nios2_qsys_instruction_master_readdata), // .readdata
.av_readdatavalid (nios2_qsys_instruction_master_readdatavalid), // .readdatavalid
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_data_master_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_qsys_data_master_byteenable), // .byteenable
.av_read (nios2_qsys_data_master_read), // .read
.av_readdata (nios2_qsys_data_master_readdata), // .readdata
.av_readdatavalid (nios2_qsys_data_master_readdatavalid), // .readdatavalid
.av_write (nios2_qsys_data_master_write), // .write
.av_writedata (nios2_qsys_data_master_writedata), // .writedata
.av_debugaccess (nios2_qsys_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_qsys_jtag_debug_module_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_jtag_debug_module_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_qsys_jtag_debug_module_agent_m0_burstcount), // .burstcount
.uav_read (nios2_qsys_jtag_debug_module_agent_m0_read), // .read
.uav_write (nios2_qsys_jtag_debug_module_agent_m0_write), // .write
.uav_waitrequest (nios2_qsys_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_jtag_debug_module_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_jtag_debug_module_agent_m0_readdata), // .readdata
.uav_writedata (nios2_qsys_jtag_debug_module_agent_m0_writedata), // .writedata
.uav_lock (nios2_qsys_jtag_debug_module_agent_m0_lock), // .lock
.uav_debugaccess (nios2_qsys_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_qsys_jtag_debug_module_address), // avalon_anti_slave_0.address
.av_write (nios2_qsys_jtag_debug_module_write), // .write
.av_read (nios2_qsys_jtag_debug_module_read), // .read
.av_readdata (nios2_qsys_jtag_debug_module_readdata), // .readdata
.av_writedata (nios2_qsys_jtag_debug_module_writedata), // .writedata
.av_byteenable (nios2_qsys_jtag_debug_module_byteenable), // .byteenable
.av_waitrequest (nios2_qsys_jtag_debug_module_waitrequest), // .waitrequest
.av_debugaccess (nios2_qsys_jtag_debug_module_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_s1_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_s1_write), // .write
.av_readdata (onchip_memory2_s1_readdata), // .readdata
.av_writedata (onchip_memory2_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_control_slave_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sysid_qsys_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_control_slave_agent_m0_read), // .read
.uav_write (sysid_qsys_control_slave_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) adc_ltc2308_slave_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (adc_ltc2308_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (adc_ltc2308_slave_agent_m0_burstcount), // .burstcount
.uav_read (adc_ltc2308_slave_agent_m0_read), // .read
.uav_write (adc_ltc2308_slave_agent_m0_write), // .write
.uav_waitrequest (adc_ltc2308_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (adc_ltc2308_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (adc_ltc2308_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (adc_ltc2308_slave_agent_m0_readdata), // .readdata
.uav_writedata (adc_ltc2308_slave_agent_m0_writedata), // .writedata
.uav_lock (adc_ltc2308_slave_agent_m0_lock), // .lock
.uav_debugaccess (adc_ltc2308_slave_agent_m0_debugaccess), // .debugaccess
.av_address (adc_ltc2308_slave_address), // avalon_anti_slave_0.address
.av_write (adc_ltc2308_slave_write), // .write
.av_read (adc_ltc2308_slave_read), // .read
.av_readdata (adc_ltc2308_slave_readdata), // .readdata
.av_writedata (adc_ltc2308_slave_writedata), // .writedata
.av_chipselect (adc_ltc2308_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (20),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_s1_translator (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_s1_agent_m0_burstcount), // .burstcount
.uav_read (sw_s1_agent_m0_read), // .read
.uav_write (sw_s1_agent_m0_write), // .write
.uav_waitrequest (sw_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_s1_agent_m0_readdata), // .readdata
.uav_writedata (sw_s1_agent_m0_writedata), // .writedata
.uav_lock (sw_s1_agent_m0_lock), // .lock
.uav_debugaccess (sw_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sw_s1_address), // avalon_anti_slave_0.address
.av_write (sw_s1_write), // .write
.av_readdata (sw_s1_readdata), // .readdata
.av_writedata (sw_s1_writedata), // .writedata
.av_chipselect (sw_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BEGIN_BURST (75),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_THREAD_ID_H (83),
.PKT_THREAD_ID_L (83),
.PKT_CACHE_H (90),
.PKT_CACHE_L (87),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_instruction_master_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_instruction_master_agent_cp_ready), // .ready
.rp_valid (nios2_qsys_instruction_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_qsys_instruction_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_qsys_instruction_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_qsys_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_qsys_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_qsys_instruction_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_BEGIN_BURST (75),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_BURST_TYPE_H (72),
.PKT_BURST_TYPE_L (71),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_TRANS_EXCLUSIVE (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_THREAD_ID_H (83),
.PKT_THREAD_ID_L (83),
.PKT_CACHE_H (90),
.PKT_CACHE_L (87),
.PKT_DATA_SIDEBAND_H (74),
.PKT_DATA_SIDEBAND_L (74),
.PKT_QOS_H (76),
.PKT_QOS_L (76),
.PKT_ADDR_SIDEBAND_H (73),
.PKT_ADDR_SIDEBAND_L (73),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_data_master_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_data_master_agent_cp_ready), // .ready
.rp_valid (nios2_qsys_data_master_limiter_rsp_src_valid), // rp.valid
.rp_data (nios2_qsys_data_master_limiter_rsp_src_data), // .data
.rp_channel (nios2_qsys_data_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (nios2_qsys_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (nios2_qsys_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (nios2_qsys_data_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_jtag_debug_module_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_qsys_jtag_debug_module_agent_m0_address), // m0.address
.m0_burstcount (nios2_qsys_jtag_debug_module_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_qsys_jtag_debug_module_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_qsys_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_qsys_jtag_debug_module_agent_m0_lock), // .lock
.m0_readdata (nios2_qsys_jtag_debug_module_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_qsys_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_qsys_jtag_debug_module_agent_m0_read), // .read
.m0_waitrequest (nios2_qsys_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_qsys_jtag_debug_module_agent_m0_writedata), // .writedata
.m0_write (nios2_qsys_jtag_debug_module_agent_m0_write), // .write
.rp_endofpacket (nios2_qsys_jtag_debug_module_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_qsys_jtag_debug_module_agent_rp_ready), // .ready
.rp_valid (nios2_qsys_jtag_debug_module_agent_rp_valid), // .valid
.rp_data (nios2_qsys_jtag_debug_module_agent_rp_data), // .data
.rp_startofpacket (nios2_qsys_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_qsys_jtag_debug_module_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_qsys_jtag_debug_module_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_qsys_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_qsys_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_qsys_jtag_debug_module_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_qsys_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_qsys_jtag_debug_module_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_qsys_jtag_debug_module_agent_rf_source_data), // in.data
.in_valid (nios2_qsys_jtag_debug_module_agent_rf_source_valid), // .valid
.in_ready (nios2_qsys_jtag_debug_module_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_qsys_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_qsys_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_qsys_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) onchip_memory2_s1_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (onchip_memory2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory2_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_s1_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sysid_qsys_control_slave_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sysid_qsys_control_slave_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_control_slave_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_control_slave_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_control_slave_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_control_slave_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_control_slave_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.rp_data (sysid_qsys_control_slave_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_qsys_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_control_slave_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sysid_qsys_control_slave_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_control_slave_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_avalon_jtag_slave_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) adc_ltc2308_slave_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (adc_ltc2308_slave_agent_m0_address), // m0.address
.m0_burstcount (adc_ltc2308_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (adc_ltc2308_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (adc_ltc2308_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (adc_ltc2308_slave_agent_m0_lock), // .lock
.m0_readdata (adc_ltc2308_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (adc_ltc2308_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (adc_ltc2308_slave_agent_m0_read), // .read
.m0_waitrequest (adc_ltc2308_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (adc_ltc2308_slave_agent_m0_writedata), // .writedata
.m0_write (adc_ltc2308_slave_agent_m0_write), // .write
.rp_endofpacket (adc_ltc2308_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (adc_ltc2308_slave_agent_rp_ready), // .ready
.rp_valid (adc_ltc2308_slave_agent_rp_valid), // .valid
.rp_data (adc_ltc2308_slave_agent_rp_data), // .data
.rp_startofpacket (adc_ltc2308_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (adc_ltc2308_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (adc_ltc2308_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (adc_ltc2308_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (adc_ltc2308_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (adc_ltc2308_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (adc_ltc2308_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (adc_ltc2308_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (adc_ltc2308_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (adc_ltc2308_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (adc_ltc2308_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (adc_ltc2308_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (adc_ltc2308_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (adc_ltc2308_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (adc_ltc2308_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (adc_ltc2308_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (adc_ltc2308_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) adc_ltc2308_slave_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (adc_ltc2308_slave_agent_rf_source_data), // in.data
.in_valid (adc_ltc2308_slave_agent_rf_source_valid), // .valid
.in_ready (adc_ltc2308_slave_agent_rf_source_ready), // .ready
.in_startofpacket (adc_ltc2308_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (adc_ltc2308_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (adc_ltc2308_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (adc_ltc2308_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (adc_ltc2308_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (adc_ltc2308_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (adc_ltc2308_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (75),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (55),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (56),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.PKT_TRANS_READ (59),
.PKT_TRANS_LOCK (60),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_BURSTWRAP_H (67),
.PKT_BURSTWRAP_L (65),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_PROTECTION_H (86),
.PKT_PROTECTION_L (84),
.PKT_RESPONSE_STATUS_H (92),
.PKT_RESPONSE_STATUS_L (91),
.PKT_BURST_SIZE_H (70),
.PKT_BURST_SIZE_L (68),
.PKT_ORI_BURST_SIZE_L (93),
.PKT_ORI_BURST_SIZE_H (95),
.ST_CHANNEL_W (6),
.ST_DATA_W (96),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_s1_agent (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_s1_agent_m0_address), // m0.address
.m0_burstcount (sw_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_s1_agent_m0_lock), // .lock
.m0_readdata (sw_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_s1_agent_m0_read), // .read
.m0_waitrequest (sw_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_s1_agent_m0_writedata), // .writedata
.m0_write (sw_s1_agent_m0_write), // .write
.rp_endofpacket (sw_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_s1_agent_rp_ready), // .ready
.rp_valid (sw_s1_agent_rp_valid), // .valid
.rp_data (sw_s1_agent_rp_data), // .data
.rp_startofpacket (sw_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sw_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sw_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sw_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (97),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_s1_agent_rsp_fifo (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_s1_agent_rf_source_data), // in.data
.in_valid (sw_s1_agent_rf_source_valid), // .valid
.in_ready (sw_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sw_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router router (
.sink_ready (nios2_qsys_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_qsys_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_data_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_data_master_agent_cp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002 router_002 (
.sink_ready (nios2_qsys_jtag_debug_module_agent_rp_ready), // sink.ready
.sink_valid (nios2_qsys_jtag_debug_module_agent_rp_valid), // .valid
.sink_data (nios2_qsys_jtag_debug_module_agent_rp_data), // .data
.sink_startofpacket (nios2_qsys_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_jtag_debug_module_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_002 router_003 (
.sink_ready (onchip_memory2_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004 router_004 (
.sink_ready (sysid_qsys_control_slave_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_control_slave_agent_rp_valid), // .valid
.sink_data (sysid_qsys_control_slave_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004 router_005 (
.sink_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004 router_006 (
.sink_ready (adc_ltc2308_slave_agent_rp_ready), // sink.ready
.sink_valid (adc_ltc2308_slave_agent_rp_valid), // .valid
.sink_data (adc_ltc2308_slave_agent_rp_data), // .data
.sink_startofpacket (adc_ltc2308_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (adc_ltc2308_slave_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_router_004 router_007 (
.sink_ready (sw_s1_agent_rp_ready), // sink.ready
.sink_valid (sw_s1_agent_rp_valid), // .valid
.sink_data (sw_s1_agent_rp_data), // .data
.sink_startofpacket (sw_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_s1_agent_rp_endofpacket), // .endofpacket
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) nios2_qsys_instruction_master_limiter (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_qsys_instruction_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_qsys_instruction_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_qsys_instruction_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_qsys_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_qsys_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_qsys_instruction_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_qsys_instruction_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_qsys_instruction_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_qsys_instruction_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_qsys_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_qsys_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_qsys_instruction_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (82),
.PKT_DEST_ID_L (80),
.PKT_SRC_ID_H (79),
.PKT_SRC_ID_L (77),
.PKT_TRANS_POSTED (57),
.PKT_TRANS_WRITE (58),
.MAX_OUTSTANDING_RESPONSES (1),
.PIPELINED (0),
.ST_DATA_W (96),
.ST_CHANNEL_W (6),
.VALID_WIDTH (6),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (64),
.PKT_BYTE_CNT_L (62),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) nios2_qsys_data_master_limiter (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (nios2_qsys_data_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (nios2_qsys_data_master_limiter_cmd_src_data), // .data
.cmd_src_channel (nios2_qsys_data_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (nios2_qsys_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (nios2_qsys_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (nios2_qsys_data_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (nios2_qsys_data_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (nios2_qsys_data_master_limiter_rsp_src_data), // .data
.rsp_src_channel (nios2_qsys_data_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (nios2_qsys_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (nios2_qsys_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (nios2_qsys_data_master_limiter_cmd_valid_data) // cmd_valid.data
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_demux cmd_demux (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_qsys_instruction_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_qsys_instruction_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_qsys_instruction_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_qsys_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_qsys_instruction_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (nios2_qsys_data_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (nios2_qsys_data_master_limiter_cmd_src_channel), // .channel
.sink_data (nios2_qsys_data_master_limiter_cmd_src_data), // .data
.sink_startofpacket (nios2_qsys_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (nios2_qsys_data_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_demux_001_src4_valid), // .valid
.src4_data (cmd_demux_001_src4_data), // .data
.src4_channel (cmd_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_demux_001_src5_valid), // .valid
.src5_data (cmd_demux_001_src5_data), // .data
.src5_channel (cmd_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux cmd_mux (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src3_valid), // .valid
.sink0_channel (cmd_demux_001_src3_channel), // .channel
.sink0_data (cmd_demux_001_src3_data), // .data
.sink0_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002 cmd_mux_004 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src4_valid), // .valid
.sink0_channel (cmd_demux_001_src4_channel), // .channel
.sink0_data (cmd_demux_001_src4_data), // .data
.sink0_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_cmd_mux_002 cmd_mux_005 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src5_valid), // .valid
.sink0_channel (cmd_demux_001_src5_channel), // .channel
.sink0_data (cmd_demux_001_src5_data), // .data
.sink0_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux rsp_demux (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002 rsp_demux_003 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002 rsp_demux_004 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_demux_002 rsp_demux_005 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (onchip_memory2_reset1_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_mux rsp_mux (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
DE0_NANO_SOC_QSYS_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (pll_sys_outclk0_clk), // clk.clk
.reset (nios2_qsys_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
endmodule
|
//--------------------------------------------------------------------------------
//-- Filename: BAR0_WRAPPER.v
//--
//-- Description: BAR0 WRAPPER Module
//--
//-- The module is a simple warpper to BAR0 module. it provides write
//-- control and byte enable access on BAR0.
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module BAR0_WRAPPER(
clk,
rst_n,
en,
//read and write port
a_i,
wr_en_i,
wr_be_i,
wr_busy_o,
rd_d_o,
rd_be_i,
wr_d_i,
//BAR1 Write Arbiter write port 1
bar1_wr_en1_o,
bar1_addr1_o,
bar1_wr_be1_o,
bar1_wr_d1_o,
bar1_wr_ack1_n_i,
bar1_arbiter_busy_i,
bar1_wr_busy_i,
//response message read port
resp_i,
resp_empty_i,
resp_rd_en_o,
req_compl_i,
mrd_start_i,
mrd_done_i,
compl_done_i,
dma_rd_req_flag_o,
req_queue_av_i,
req_queue_depth_o,
int_cnt_i,
req_cnt_i,
//error report
cpld_malformed_i,
fatal_err_i,
req_unsupported_i,
lba_ofr_err_i,
prp_offset_err_i,
id_ob_err_i,
cont_rdy_o,
//INT ctrl
int_en_o,
int_rd_msk_o,
int_wr_msk_o,
//DMA READ QUEUE
dma_rd_q_wr_en_o,
dma_rd_q_wr_data_o,
dma_rd_q_full_i,
/*************ouyang***************/
//msix interface
msg_lower_addr_o,
msg_upper_addr_o,
msg_data_o,
// the base addr for response queue
response_queue_addr_o,
//count enable for response queue offset
response_queue_addr_offset_cnt_en_i,
interrupt_block_o,
response_queue_cur_offset_reg_o,
response_queue_addr_offset_o,
response_queue_num_i
/**********************************/
);
parameter BAR0_WR_RST = 4'b0001;
parameter BAR0_WR_WAIT = 4'b0010;
parameter BAR0_WR_READ = 4'b0100;
parameter BAR0_WR_WRITE = 4'b1000;
/*************ouyang***************/
input [5:0] response_queue_num_i;
//msix interface
output [31:0] msg_lower_addr_o;
output [31:0] msg_upper_addr_o;
output [31:0] msg_data_o;
// the base addr for response queue
output [31:0] response_queue_addr_o;
//count enable for response queue offset
input response_queue_addr_offset_cnt_en_i;
output interrupt_block_o;
output [31:0] response_queue_cur_offset_reg_o;
output [10:0] response_queue_addr_offset_o;
/*********************************/
input clk , rst_n;
output en;
// read port
//
input [6:0] a_i;
input [3:0] rd_be_i;
output [31:0] rd_d_o;
// write port
//
input wr_en_i;
input [7:0] wr_be_i;
input [31:0] wr_d_i;
output wr_busy_o;
output bar1_wr_en1_o;
output [6:0] bar1_addr1_o;
output [3:0] bar1_wr_be1_o;
output [31:0] bar1_wr_d1_o;
input bar1_wr_ack1_n_i;
input bar1_arbiter_busy_i;
input bar1_wr_busy_i;
input [31:0] resp_i;
input resp_empty_i;
output resp_rd_en_o;
input req_compl_i;
input mrd_start_i;
input mrd_done_i;
input compl_done_i;
output dma_rd_req_flag_o;
input [9:0] req_queue_av_i;
output [15:0] req_queue_depth_o;
input [31:0] int_cnt_i;
input [31:0] req_cnt_i;
input cpld_malformed_i;
input fatal_err_i;
input req_unsupported_i;
input lba_ofr_err_i;
input prp_offset_err_i;
input id_ob_err_i;
output cont_rdy_o;
output int_en_o;
output int_rd_msk_o;
output int_wr_msk_o;
wire [31:0] bar0_rd_data;
reg [6:0] addr_q;
reg [3:0] wr_be_q;
reg [31:0] wr_d_q;
reg wr_busy_o;
output dma_rd_q_wr_en_o;
output [63:0] dma_rd_q_wr_data_o;
input dma_rd_q_full_i;
reg bar0_wr_en;
reg [31:0] pre_wr_data;
reg [31:0] bar0_wr_data;
reg [3:0] bar0_wr_state;
// BAR0 write control state machine
//
always @ ( posedge clk ) begin
if( !rst_n ) begin
bar0_wr_en <= 1'b0;
wr_busy_o <= 1'b0;
addr_q <= 7'b0;
wr_be_q <= 4'b0;
wr_d_q <= 32'b0;
pre_wr_data <= 32'b0;
bar0_wr_data <= 32'b0;
bar0_wr_state <= BAR0_WR_RST;
end
else begin
case ( bar0_wr_state )
BAR0_WR_RST: begin
bar0_wr_en <= 1'b0;
wr_busy_o <= 1'b0;
addr_q <= a_i;
if( wr_en_i ) begin
wr_be_q <= wr_be_i[3:0];
wr_d_q <= wr_d_i;
wr_busy_o <= 1'b1;
bar0_wr_state <= BAR0_WR_WAIT;
end
end
BAR0_WR_WAIT: begin
bar0_wr_state <= BAR0_WR_READ;
end
BAR0_WR_READ: begin
pre_wr_data <= bar0_rd_data;
bar0_wr_state <= BAR0_WR_WRITE;
end
BAR0_WR_WRITE: begin
bar0_wr_en <= 1'b1;
bar0_wr_data <= { { wr_be_q[3] ? wr_d_q[31:24] : pre_wr_data[31:24] } ,
{ wr_be_q[2] ? wr_d_q[23:16] : pre_wr_data[23:16] } ,
{ wr_be_q[1] ? wr_d_q[15:8] : pre_wr_data[15:8] } ,
{ wr_be_q[0] ? wr_d_q[7:0] : pre_wr_data[7:0] }
};
wr_busy_o <= 1'b0;
bar0_wr_state <= BAR0_WR_RST;
end
default: bar0_wr_state <= BAR0_WR_RST;
endcase
end
end
/*
* BAR0 Read Controller
*/
/* Handle Read byte enables */
assign rd_d_o = {{rd_be_i[0] ? bar0_rd_data[07:00] : 8'h0},
{rd_be_i[1] ? bar0_rd_data[15:08] : 8'h0},
{rd_be_i[2] ? bar0_rd_data[23:16] : 8'h0},
{rd_be_i[3] ? bar0_rd_data[31:24] : 8'h0}};
BAR0 bar0 (
.clk(clk),
.rst_n(rst_n),
.en(en),
//read and write port
.a_i(addr_q),
.wr_en_i(bar0_wr_en),
.rd_d_o(bar0_rd_data),
.wr_d_i(bar0_wr_data),
//BAR1 Write Arbiter write port 1
.bar1_wr_en1_o(bar1_wr_en1_o),
.bar1_addr1_o(bar1_addr1_o),
.bar1_wr_be1_o(bar1_wr_be1_o),
.bar1_wr_d1_o(bar1_wr_d1_o),
.bar1_wr_ack1_n_i(bar1_wr_ack1_n_i),
.bar1_arbiter_busy_i(bar1_arbiter_busy_i),
.bar1_wr_busy_i(bar1_wr_busy_i),
//response message read port
.resp_i(resp_i),
.resp_empty_i(resp_empty_i),
.resp_rd_en_o(resp_rd_en_o),
.req_compl_i(req_compl_i),
.mrd_start_i(mrd_start_i),
.mrd_done_i(mrd_done_i),
.compl_done_i(compl_done_i),
.dma_rd_req_flag_o(dma_rd_req_flag_o),
.req_queue_av_i(req_queue_av_i),
.req_queue_depth_o(req_queue_depth_o),
.int_cnt_i(int_cnt_i),
.req_cnt_i(req_cnt_i),
//error report
.cpld_malformed_i(cpld_malformed_i),
.fatal_err_i(fatal_err_i),
.req_unsupported_i(req_unsupported_i),
.lba_ofr_err_i(lba_ofr_err_i),
.prp_offset_err_i(prp_offset_err_i),
.id_ob_err_i(id_ob_err_i),
.cont_rdy_o(cont_rdy_o),
//INT ctrl
.int_en_o(int_en_o),
.int_rd_msk_o(int_rd_msk_o),
.int_wr_msk_o(int_wr_msk_o),
.dma_rd_q_wr_en_o(dma_rd_q_wr_en_o),
.dma_rd_q_wr_data_o(dma_rd_q_wr_data_o),
.dma_rd_q_full_i(dma_rd_q_full_i),
/*************ouyang***************/
//msix interface
.msg_lower_addr_o(msg_lower_addr_o),
.msg_upper_addr_o(msg_upper_addr_o),
.msg_data_o(msg_data_o),
// the base addr for response queue
.response_queue_addr_o(response_queue_addr_o),
//count enable for response queue offset
.response_queue_addr_offset_cnt_en_i(response_queue_addr_offset_cnt_en_i),
.interrupt_block_o(interrupt_block_o),
.response_queue_cur_offset_reg_o(response_queue_cur_offset_reg_o),
.response_queue_addr_offset_o(response_queue_addr_offset_o),
.response_queue_num_i(response_queue_num_i)
/**********************************/
);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 256 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : 1-port synchronous RAM
// FUNCTION: 1-port synchronous RAM
// FILES: RAM256.v -single ported synchronous RAM
// PROPERTIES: 1) Has the volume of 256 data
// 2) RAM is synchronous one, the read datum is outputted in 2 cycles after the address setting
// 3) Can be substituted to any 2-port synchronous RAM
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT256_CONFIG.inc"
module RAM256 ( CLK, ED,WE ,ADDR ,DI ,DO );
`FFT256paramnb
output [nb-1:0] DO ;
reg [nb-1:0] DO ;
input CLK ;
wire CLK ;
input ED;
input WE ;
wire WE ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input [nb-1:0] DI ;
wire [nb-1:0] DI ;
reg [nb-1:0] mem [255:0];
reg [7:0] addrrd;
always @(posedge CLK) begin
if (ED) begin
if (WE) mem[ADDR] <= DI;
addrrd <= ADDR; //storing the address
DO <= mem[addrrd]; // registering the read datum
end
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mi_nios_timer (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register[0];
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_1_V
`define SKY130_FD_SC_HD__NAND4B_1_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4b_1 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4b_1 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31OI_LP_V
`define SKY130_FD_SC_LP__A31OI_LP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_lp (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31oi_lp (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31OI_LP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:01:50 03/29/2015
// Design Name:
// Module Name: aluparam_behav
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu_behav
( output [15:0] Y,
output [15:0] flags,
input [15:0] A,
input [15:0] B,
input [3:0] sel
);
reg [15:0] outreg;
reg [15:0] flagreg;
reg carry;
reg overflow;
always @(A, B, sel) begin
flagreg = 0;
carry = 0;
overflow = 0;
case(sel)
4'b0011: begin // XOR
outreg = A ^ B;
end
4'b0001: begin // AND
outreg = A & B;
end
4'b0010: begin // OR
outreg = A | B;
end
4'b0101: begin // ADD
{carry, outreg} = A + B;
overflow = (($signed(A) >= 0 && $signed(B) >= 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) < 0 && $signed(outreg) >= 0)) ? 1'b1 : 1'b0;
end
4'b1001,
4'b1011: begin // SUB or CMP
{carry, outreg} = A + ~B + 1'b1;
overflow = (($signed(A) >= 0 && $signed(B) < 0 && $signed(outreg) < 0) || ($signed(A) < 0 && $signed(B) >= 0 && $signed(outreg) >= 0)) ? 1'b1 : 1'b0;
end
4'b1101: begin // MOV
outreg = B;
end
4'b1111: begin // Load Upper
outreg = { B[7:0], {(8){1'b0}} };
end
default: begin
outreg = A; // Do nothing
flagreg = 0;
end
endcase
flagreg[0] = carry; // Carry set by ADD and SUB only.
flagreg[2] = (A < B) && (sel == 4'b1011); // Low Flag set by CMP only.
flagreg[5] = overflow; // Overflow set by ADD and SUB only.
flagreg[6] = (outreg == 16'b0) && (sel == 4'b1011); // Zero Flag set by CMP only.
flagreg[7] = outreg[15] && (sel == 4'b1011); // Negative (Sign) Flag set by CMP only.
if(sel == 4'b1011) begin
outreg = A;
end
end
assign Y = outreg;
assign flags = flagreg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_LP_V
`define SKY130_FD_SC_LP__A2111OI_LP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_lp (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111oi_lp (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_LP_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Chris Randall.
interface ifc;
integer value;
modport out_modport (output value);
endinterface
module m
(
input clk_ip, // verilator tag clk_ip
input rst_ip,
output foo_op); // verilator tag foo_op
// This is a comment
typedef struct packed {
logic clk; /* verilator tag this is clk */
logic k; /* verilator lint_off UNUSED */
logic enable; // verilator tag enable
logic data; // verilator tag data
} my_struct; // verilator tag my_struct
// This is a comment
ifc itop();
my_struct this_struct [2]; // verilator tag this_struct
wire [31:0] dotted = itop.value;
function f(input string m);
$display("%s", m);
endfunction
initial begin
// Contains all 256 characters except 0 (null character)
f("\x01\x02\x03\x04\x05\x06\a\x08\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~\x7f\x80\x81\x82\x83\x84\x85\x86\x87\x88\x89\x8a\x8b\x8c\x8d\x8e\x8f\x90\x91\x92\x93\x94\x95\x96\x97\x98\x99\x9a\x9b\x9c\x9d\x9e\x9f\xa0\xa1\xa2\xa3\xa4\xa5\xa6\xa7\xa8\xa9\xaa\xab\xac\xad\xae\xaf\xb0\xb1\xb2\xb3\xb4\xb5\xb6\xb7\xb8\xb9\xba\xbb\xbc\xbd\xbe\xbf\xc0\xc1\xc2\xc3\xc4\xc5\xc6\xc7\xc8\xc9\xca\xcb\xcc\xcd\xce\xcf\xd0\xd1\xd2\xd3\xd4\xd5\xd6\xd7\xd8\xd9\xda\xdb\xdc\xdd\xde\xdf\xe0\xe1\xe2\xe3\xe4\xe5\xe6\xe7\xe8\xe9\xea\xeb\xec\xed\xee\xef\xf0\xf1\xf2\xf3\xf4\xf5\xf6\xf7\xf8\xf9\xfa\xfb\xfc\xfd\xfe\xff");
end
endmodule
|
//-----------------------------------------------------------------------------
// File : wb_slave.v
// Creation date : 30.03.2017
// Creation time : 12:18:42
// Description : Template component for wishbone slave. Address space is assumed to be contiguous.
// Created by : TermosPullo
// Tool : Kactus2 3.4.6 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:ip.hw:wb_slave_template:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/ip.hw/wb_slave_template/1.0/wb_slave_template.1.0.xml
//-----------------------------------------------------------------------------
module wb_slave #(
parameter ADDR_WIDTH = 16, // The width of the address.
parameter DATA_WIDTH = 32, // The width of the both transferred and inputted data.
parameter DATA_COUNT = 8, // How many values there are in the register array.
parameter BASE_ADDRESS = 'h0F00 // The first referred address of the master.
) (
// Interface: wb_slave
// The address of the data.
input [ADDR_WIDTH-1:0] adr_i, // The address of the data.
input cyc_i, // Asserted by master for transfer.
input [DATA_WIDTH-1:0] dat_i, // Data from master to slave.
input stb_i, // Asserted, when this specific slave is selected.
input we_i, // Write = 1, Read = 0.
output reg ack_o, // Slave asserts acknowledge.
output reg [DATA_WIDTH-1:0] dat_o, // Data from slave to master.
output reg err_o, // Indicates abnormal cycle termination.
// Interface: wb_system
// The mandatory clock, as this is synchronous logic.
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
localparam AUB = 8;
localparam AU_IN_DATA = DATA_WIDTH/AUB;
localparam MEMORY_SIZE = DATA_COUNT*4;
reg [AUB-1:0] memory [MEMORY_SIZE-1:0];
// Used to index AUBs to data io.
integer index;
// The state.
reg [0:0] state;
// The available states.
parameter [0:0]
S_WAIT = 1'd0, // Waiting for cyc_i & stb_i
S_DEASSERT = 1'd1; // Deassert acknowledgement.
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
ack_o <= 0; // Obviously, there is nothing to acknowledge by default.
dat_o <= 0; // No output by default.
err_o <= 0; // No error by default.
state <= S_WAIT; // Wait signals from the masters at reset.
end
else begin
if (state == S_WAIT) begin
// Wait signal from the master.
if ( cyc_i == 1 && stb_i == 1 ) begin
// Master ok, check the address.
if (adr_i < BASE_ADDRESS + MEMORY_SIZE && adr_i >= BASE_ADDRESS) begin
// The specified address in accessible -> proceed.
ack_o <= 1;
if ( we_i == 1 ) begin
// Writing: Pick every byte from the input and place them to correct addresses.
for (index = 0; index < AU_IN_DATA; index = index + 1) begin
memory[adr_i - BASE_ADDRESS + index] <= dat_i[(index*AUB)+:AUB];
end
end
else begin
// Reading: Pick every byte from correct addresses and place them to the output.
for (index = 0; index < AU_IN_DATA; index = index + 1) begin
dat_o[(index*AUB)+:AUB] <= memory[adr_i - BASE_ADDRESS + index];
end
end
end
else begin
// The specified address out-of-scope -> error!
err_o <= 1;
end
// Next thing is to deassert.
state <= S_DEASSERT;
end
end
else if (state == S_DEASSERT) begin
// Deassert acknowlegement, get ready to receive next one.
ack_o <= 0;
err_o <= 0;
state <= S_WAIT;
end
else
$display("ERROR: Unkown state: %d", state);
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 11:32:03 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n9973, operation_reg_0_, NaN_reg, ready_add_subt,
overflow_flag_addsubt, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_operation_out, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_zero_flag, FPADDSUB_OP_FLAG_SFG,
FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_intAS,
FPADDSUB_Shift_reg_FLAGS_7_6, FPMULT_Exp_module_Data_S_8_,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1205,
n1206, n1207, n1208, n1209, n1210, n1212, n1213, n1214, n1216, n1217,
n1218, n1220, n1221, n1222, n1224, n1225, n1226, n1228, n1229, n1230,
n1232, n1233, n1234, n1236, n1237, n1238, n1240, n1241, n1242, n1244,
n1245, n1246, n1248, n1249, n1250, n1252, n1253, n1254, n1256, n1257,
n1258, n1260, n1261, n1262, n1264, n1265, n1266, n1268, n1269, n1270,
n1272, n1274, n1275, n1276, n1278, n1281, n1282, n1283, n1285, n1288,
n1289, n1290, n1292, n1295, n1296, n1297, n1299, n1302, n1303, n1304,
n1306, n1309, n1310, n1311, n1313, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1329, n1332, n1333,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353,
n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363,
n1364, n1366, n1369, n1372, n1375, n1378, n1381, n1384, n1387, n1390,
n1393, n1396, n1399, n1402, n1405, n1408, n1411, n1412, n1414, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1468,
n1476, n1477, n1478, n1479, n1480, n1483, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1517, n1518, n1519,
n1521, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1553, n1555, n1556, n1557, n1558, n1560, n1561, n1562, n1563, n1566,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1630, n1631, n1634, n1635, n1636, n1637, n1638, n1643, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1658, n1662, n1663, n1664, n1665, n1666, n1668, n1669, n1670,
n1671, n1672, n1673, n1675, n1677, n1678, n1680, n1681, n1682, n1683,
n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693,
n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703,
n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713,
n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723,
n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733,
n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743,
n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753,
n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763,
n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773,
n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783,
n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793,
n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803,
n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813,
n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823,
n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833,
n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843,
n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913,
n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923,
n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933,
n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943,
n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953,
n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963,
n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983,
n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993,
n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003,
n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013,
n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023,
n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093,
n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103,
n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113,
n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123,
n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133,
n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143,
n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2193,
intadd_733_CI, intadd_733_SUM_2_, intadd_733_SUM_1_,
intadd_733_SUM_0_, intadd_733_n3, intadd_733_n2, intadd_733_n1,
intadd_734_CI, intadd_734_SUM_2_, intadd_734_SUM_1_,
intadd_734_SUM_0_, intadd_734_n3, intadd_734_n2, intadd_734_n1,
add_x_246_A_5_, add_x_246_A_4_, add_x_246_A_3_, add_x_246_A_2_,
add_x_246_A_1_, add_x_246_A_0_, add_x_246_n21, add_x_246_n19,
add_x_246_n6, DP_OP_26J248_126_1325_n28, DP_OP_234J248_129_4955_n1,
add_x_69_n328, add_x_69_n302, add_x_69_n301, add_x_69_n298,
add_x_69_n295, add_x_69_n294, add_x_69_n291, add_x_69_n289,
add_x_69_n286, add_x_69_n285, add_x_69_n283, add_x_69_n113,
add_x_69_n104, add_x_69_n95, add_x_69_n94, add_x_69_n85, add_x_69_n76,
add_x_69_n30, add_x_69_n29, add_x_69_n28, add_x_69_n27, sub_x_17_n251,
sub_x_17_n206, add_x_18_n35, DP_OP_496J248_122_3540_n1516,
DP_OP_496J248_122_3540_n1515, DP_OP_496J248_122_3540_n1514,
DP_OP_496J248_122_3540_n1513, DP_OP_496J248_122_3540_n1512,
DP_OP_496J248_122_3540_n1507, DP_OP_496J248_122_3540_n1504,
DP_OP_496J248_122_3540_n1503, DP_OP_496J248_122_3540_n1502,
DP_OP_496J248_122_3540_n1501, DP_OP_496J248_122_3540_n1500,
DP_OP_496J248_122_3540_n1499, DP_OP_496J248_122_3540_n1494,
DP_OP_496J248_122_3540_n1477, DP_OP_496J248_122_3540_n1476,
DP_OP_496J248_122_3540_n1475, DP_OP_496J248_122_3540_n1469,
DP_OP_496J248_122_3540_n1468, DP_OP_496J248_122_3540_n1467,
DP_OP_496J248_122_3540_n1464, DP_OP_496J248_122_3540_n1462,
DP_OP_496J248_122_3540_n1458, DP_OP_496J248_122_3540_n1383,
DP_OP_496J248_122_3540_n1376, DP_OP_496J248_122_3540_n1207,
DP_OP_496J248_122_3540_n1205, DP_OP_496J248_122_3540_n1203,
DP_OP_496J248_122_3540_n1202, DP_OP_496J248_122_3540_n1148,
DP_OP_496J248_122_3540_n1122, DP_OP_496J248_122_3540_n1118,
DP_OP_496J248_122_3540_n1117, DP_OP_496J248_122_3540_n1107,
DP_OP_496J248_122_3540_n1098, DP_OP_496J248_122_3540_n1064,
DP_OP_496J248_122_3540_n839, DP_OP_496J248_122_3540_n829,
DP_OP_496J248_122_3540_n828, DP_OP_496J248_122_3540_n827,
DP_OP_496J248_122_3540_n788, DP_OP_496J248_122_3540_n778,
DP_OP_496J248_122_3540_n451, DP_OP_496J248_122_3540_n39,
DP_OP_496J248_122_3540_n36, DP_OP_496J248_122_3540_n35,
DP_OP_496J248_122_3540_n4, add_x_254_SUM_22_, add_x_219_n17,
DP_OP_499J248_125_1651_n299, DP_OP_499J248_125_1651_n295,
DP_OP_499J248_125_1651_n293, DP_OP_499J248_125_1651_n291,
DP_OP_499J248_125_1651_n273, DP_OP_499J248_125_1651_n268,
DP_OP_499J248_125_1651_n267, DP_OP_499J248_125_1651_n229,
DP_OP_499J248_125_1651_n228, DP_OP_499J248_125_1651_n227,
DP_OP_499J248_125_1651_n224, DP_OP_499J248_125_1651_n223,
DP_OP_499J248_125_1651_n220, DP_OP_499J248_125_1651_n219,
DP_OP_499J248_125_1651_n216, DP_OP_499J248_125_1651_n215,
DP_OP_499J248_125_1651_n208, DP_OP_499J248_125_1651_n207,
DP_OP_499J248_125_1651_n170, DP_OP_499J248_125_1651_n106,
DP_OP_499J248_125_1651_n105, DP_OP_499J248_125_1651_n104,
DP_OP_497J248_123_1725_n795, DP_OP_497J248_123_1725_n794,
DP_OP_497J248_123_1725_n793, DP_OP_497J248_123_1725_n792,
DP_OP_497J248_123_1725_n791, DP_OP_497J248_123_1725_n782,
DP_OP_497J248_123_1725_n781, DP_OP_497J248_123_1725_n722,
DP_OP_497J248_123_1725_n721, DP_OP_497J248_123_1725_n720,
DP_OP_497J248_123_1725_n718, DP_OP_497J248_123_1725_n717,
DP_OP_497J248_123_1725_n714, DP_OP_497J248_123_1725_n713,
DP_OP_497J248_123_1725_n710, DP_OP_497J248_123_1725_n705,
DP_OP_497J248_123_1725_n704, DP_OP_497J248_123_1725_n702,
DP_OP_497J248_123_1725_n699, DP_OP_497J248_123_1725_n693,
DP_OP_497J248_123_1725_n692, DP_OP_497J248_123_1725_n690,
DP_OP_497J248_123_1725_n687, DP_OP_497J248_123_1725_n686,
DP_OP_497J248_123_1725_n685, DP_OP_497J248_123_1725_n684,
DP_OP_497J248_123_1725_n683, DP_OP_497J248_123_1725_n667,
DP_OP_497J248_123_1725_n666, DP_OP_497J248_123_1725_n638,
DP_OP_497J248_123_1725_n636, DP_OP_497J248_123_1725_n635,
DP_OP_497J248_123_1725_n634, DP_OP_497J248_123_1725_n631,
DP_OP_497J248_123_1725_n624, DP_OP_497J248_123_1725_n623,
DP_OP_497J248_123_1725_n618, DP_OP_497J248_123_1725_n617,
DP_OP_497J248_123_1725_n613, DP_OP_497J248_123_1725_n612,
DP_OP_497J248_123_1725_n610, DP_OP_497J248_123_1725_n609,
DP_OP_497J248_123_1725_n607, DP_OP_497J248_123_1725_n606,
DP_OP_497J248_123_1725_n604, DP_OP_497J248_123_1725_n602,
DP_OP_497J248_123_1725_n600, DP_OP_497J248_123_1725_n599,
DP_OP_497J248_123_1725_n390, DP_OP_497J248_123_1725_n389,
DP_OP_497J248_123_1725_n379, DP_OP_497J248_123_1725_n374,
DP_OP_497J248_123_1725_n367, DP_OP_497J248_123_1725_n357,
DP_OP_497J248_123_1725_n324, DP_OP_497J248_123_1725_n312,
DP_OP_498J248_124_1725_n805, DP_OP_498J248_124_1725_n804,
DP_OP_498J248_124_1725_n801, DP_OP_498J248_124_1725_n799,
DP_OP_498J248_124_1725_n798, DP_OP_498J248_124_1725_n796,
DP_OP_498J248_124_1725_n795, DP_OP_498J248_124_1725_n793,
DP_OP_498J248_124_1725_n792, DP_OP_498J248_124_1725_n791,
DP_OP_498J248_124_1725_n790, DP_OP_498J248_124_1725_n789,
DP_OP_498J248_124_1725_n788, DP_OP_498J248_124_1725_n787,
DP_OP_498J248_124_1725_n786, DP_OP_498J248_124_1725_n785,
DP_OP_498J248_124_1725_n784, DP_OP_498J248_124_1725_n783,
DP_OP_498J248_124_1725_n730, DP_OP_498J248_124_1725_n729,
DP_OP_498J248_124_1725_n728, DP_OP_498J248_124_1725_n727,
DP_OP_498J248_124_1725_n726, DP_OP_498J248_124_1725_n725,
DP_OP_498J248_124_1725_n724, DP_OP_498J248_124_1725_n723,
DP_OP_498J248_124_1725_n722, DP_OP_498J248_124_1725_n721,
DP_OP_498J248_124_1725_n717, DP_OP_498J248_124_1725_n703,
DP_OP_498J248_124_1725_n699, DP_OP_498J248_124_1725_n698,
DP_OP_498J248_124_1725_n694, DP_OP_498J248_124_1725_n645,
DP_OP_498J248_124_1725_n643, DP_OP_498J248_124_1725_n642,
DP_OP_498J248_124_1725_n641, DP_OP_498J248_124_1725_n640,
DP_OP_498J248_124_1725_n639, DP_OP_498J248_124_1725_n638,
DP_OP_498J248_124_1725_n636, DP_OP_498J248_124_1725_n635,
DP_OP_498J248_124_1725_n634, DP_OP_498J248_124_1725_n631,
DP_OP_498J248_124_1725_n630, DP_OP_498J248_124_1725_n618,
DP_OP_498J248_124_1725_n616, DP_OP_498J248_124_1725_n613,
DP_OP_498J248_124_1725_n611, DP_OP_498J248_124_1725_n394,
DP_OP_498J248_124_1725_n392, DP_OP_498J248_124_1725_n390,
DP_OP_498J248_124_1725_n380, n2196, n2202, n2203, n2204, n2205, n2206,
n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216,
n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225, n2226,
n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235, n2236,
n2237, n2238, n2239, n2240, n2241, n2242, n2244, n2245, n2246, n2247,
n2248, n2249, n2250, n2251, n2252, n2254, n2255, n2256, n2257, n2258,
n2259, n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268,
n2269, n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278,
n2279, n2281, n2282, n2287, n2288, n2289, n2290, n2291, n2292, n2293,
n2294, n2296, n2297, n2298, n2312, n2313, n2314, n2315, n2316, n2317,
n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327,
n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337,
n2338, n2339, n2340, n2342, n2343, n2344, n2345, n2346, n2347, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2549, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2974, n2975, n2976,
n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985, n2986,
n2987, n2989, n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997,
n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007,
n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017,
n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027,
n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037,
n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047,
n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057,
n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067,
n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077,
n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087,
n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097,
n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107,
n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117,
n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127,
n3128, n3129, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138,
n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148,
n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158,
n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168,
n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178,
n3179, n3180, n3181, n3182, n3183, n3184, n3186, n3187, n3188, n3189,
n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199,
n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209,
n3210, n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219,
n3220, n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229,
n3230, n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239,
n3240, n3241, n3242, n3243, n3244, n3245, n3246, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3321,
n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331,
n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341,
n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351,
n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361,
n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371,
n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381,
n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391,
n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401,
n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411,
n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421,
n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431,
n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441,
n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451,
n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461,
n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471,
n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481,
n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491,
n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501,
n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511,
n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521,
n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531,
n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541,
n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3550, n3551, n3552,
n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562,
n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572,
n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582,
n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592,
n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602,
n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612,
n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622,
n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632,
n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642,
n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652,
n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662,
n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672,
n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682,
n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692,
n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702,
n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712,
n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722,
n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732,
n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742,
n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752,
n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762,
n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772,
n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782,
n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792,
n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802,
n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812,
n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822,
n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832,
n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842,
n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852,
n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862,
n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872,
n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882,
n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892,
n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902,
n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912,
n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922,
n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932,
n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942,
n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952,
n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962,
n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972,
n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982,
n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992,
n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002,
n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012,
n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022,
n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032,
n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042,
n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052,
n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062,
n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072,
n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082,
n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092,
n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102,
n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112,
n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122,
n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132,
n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142,
n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152,
n4153, n4154, n4155, n4157, n4158, n4159, n4160, n4161, n4162, n4163,
n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173,
n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183,
n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193,
n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203,
n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213,
n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223,
n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233,
n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243,
n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253,
n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263,
n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273,
n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283,
n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293,
n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303,
n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313,
n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323,
n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333,
n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343,
n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353,
n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363,
n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373,
n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383,
n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393,
n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403,
n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413,
n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423,
n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433,
n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443,
n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453,
n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463,
n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473,
n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483,
n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493,
n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503,
n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513,
n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523,
n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533,
n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543,
n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553,
n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563,
n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573,
n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583,
n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593,
n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603,
n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613,
n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623,
n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633,
n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643,
n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653,
n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663,
n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673,
n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683,
n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693,
n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703,
n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713,
n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723,
n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733,
n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743,
n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753,
n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763,
n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773,
n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783,
n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793,
n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803,
n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813,
n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823,
n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833,
n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843,
n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853,
n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863,
n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873,
n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883,
n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893,
n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903,
n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913,
n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923,
n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933,
n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943,
n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953,
n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963,
n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973,
n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983,
n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993,
n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003,
n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013,
n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023,
n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033,
n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043,
n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053,
n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063,
n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073,
n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083,
n5084, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093,
n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103,
n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113,
n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123,
n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133,
n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143,
n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153,
n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163,
n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173,
n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183,
n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193,
n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203,
n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213,
n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223,
n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233,
n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243,
n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253,
n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263,
n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273,
n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283,
n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293,
n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303,
n5304, n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313,
n5314, n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323,
n5324, n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333,
n5334, n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343,
n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353,
n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363,
n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373,
n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383,
n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393,
n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403,
n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413,
n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423,
n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433,
n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443,
n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453,
n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463,
n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473,
n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483,
n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493,
n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503,
n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513,
n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523,
n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533,
n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543,
n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553,
n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563,
n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573,
n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583,
n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593,
n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603,
n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613,
n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623,
n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633,
n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643,
n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653,
n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663,
n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673,
n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683,
n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693,
n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703,
n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713,
n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723,
n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733,
n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743,
n5744, n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753,
n5754, n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763,
n5764, n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773,
n5774, n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783,
n5784, n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793,
n5794, n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803,
n5804, n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813,
n5814, n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823,
n5824, n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833,
n5834, n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843,
n5844, n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853,
n5854, n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863,
n5864, n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873,
n5874, n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883,
n5884, n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893,
n5894, n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903,
n5904, n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913,
n5914, n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923,
n5924, n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933,
n5934, n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943,
n5944, n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953,
n5954, n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963,
n5964, n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973,
n5974, n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983,
n5984, n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993,
n5994, n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003,
n6004, n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013,
n6014, n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023,
n6024, n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033,
n6034, n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043,
n6044, n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053,
n6054, n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063,
n6064, n6065, n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073,
n6074, n6075, n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083,
n6084, n6085, n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093,
n6094, n6095, n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103,
n6104, n6105, n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113,
n6114, n6115, n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123,
n6124, n6125, n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133,
n6134, n6135, n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143,
n6144, n6145, n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153,
n6154, n6155, n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163,
n6164, n6165, n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173,
n6174, n6175, n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183,
n6184, n6185, n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193,
n6194, n6195, n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203,
n6204, n6205, n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213,
n6214, n6215, n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223,
n6224, n6225, n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233,
n6234, n6235, n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243,
n6244, n6245, n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253,
n6254, n6255, n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263,
n6264, n6265, n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273,
n6274, n6275, n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283,
n6284, n6285, n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293,
n6294, n6295, n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303,
n6304, n6305, n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313,
n6314, n6315, n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323,
n6324, n6325, n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333,
n6334, n6335, n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343,
n6344, n6345, n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353,
n6354, n6355, n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363,
n6364, n6365, n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373,
n6374, n6375, n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383,
n6384, n6385, n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393,
n6394, n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403,
n6404, n6405, n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413,
n6414, n6415, n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423,
n6424, n6425, n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433,
n6434, n6435, n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443,
n6444, n6445, n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453,
n6454, n6455, n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463,
n6464, n6465, n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473,
n6474, n6475, n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483,
n6484, n6485, n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493,
n6494, n6495, n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503,
n6504, n6505, n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513,
n6514, n6515, n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523,
n6524, n6525, n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533,
n6534, n6535, n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543,
n6544, n6545, n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553,
n6554, n6555, n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563,
n6564, n6565, n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573,
n6574, n6575, n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583,
n6584, n6585, n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593,
n6594, n6595, n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603,
n6604, n6605, n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613,
n6614, n6615, n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623,
n6624, n6625, n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633,
n6634, n6635, n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643,
n6644, n6645, n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653,
n6654, n6655, n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663,
n6664, n6665, n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673,
n6674, n6675, n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683,
n6684, n6685, n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693,
n6694, n6695, n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703,
n6704, n6705, n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713,
n6714, n6715, n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723,
n6724, n6725, n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733,
n6734, n6735, n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743,
n6744, n6745, n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753,
n6754, n6755, n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763,
n6764, n6765, n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773,
n6774, n6775, n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783,
n6784, n6785, n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793,
n6794, n6795, n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803,
n6804, n6805, n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813,
n6814, n6815, n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823,
n6824, n6825, n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833,
n6834, n6835, n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843,
n6844, n6845, n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853,
n6854, n6855, n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863,
n6864, n6865, n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873,
n6874, n6875, n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883,
n6884, n6885, n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893,
n6894, n6895, n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903,
n6904, n6905, n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913,
n6914, n6915, n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923,
n6924, n6925, n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933,
n6934, n6935, n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943,
n6944, n6945, n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953,
n6954, n6955, n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963,
n6964, n6965, n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973,
n6974, n6975, n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983,
n6984, n6985, n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993,
n6994, n6995, n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003,
n7004, n7005, n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013,
n7014, n7015, n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023,
n7024, n7025, n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033,
n7034, n7035, n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043,
n7044, n7045, n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053,
n7054, n7055, n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063,
n7064, n7065, n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073,
n7074, n7075, n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083,
n7084, n7085, n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093,
n7094, n7095, n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103,
n7104, n7105, n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113,
n7114, n7115, n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123,
n7124, n7125, n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133,
n7134, n7135, n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143,
n7144, n7145, n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153,
n7154, n7155, n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163,
n7164, n7165, n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173,
n7174, n7175, n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183,
n7184, n7185, n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193,
n7194, n7195, n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203,
n7204, n7205, n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213,
n7214, n7215, n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223,
n7224, n7225, n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233,
n7234, n7235, n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243,
n7244, n7245, n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253,
n7254, n7255, n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263,
n7264, n7265, n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273,
n7274, n7275, n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283,
n7284, n7285, n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293,
n7294, n7295, n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303,
n7304, n7305, n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313,
n7314, n7315, n7316, n7317, n7318, n7319, n7320, n7321, n7322, n7323,
n7324, n7325, n7326, n7327, n7328, n7329, n7330, n7331, n7332, n7333,
n7334, n7335, n7336, n7337, n7338, n7339, n7340, n7341, n7342, n7343,
n7344, n7345, n7346, n7347, n7348, n7349, n7350, n7351, n7352, n7353,
n7354, n7355, n7356, n7357, n7358, n7359, n7360, n7361, n7362, n7363,
n7364, n7365, n7366, n7367, n7368, n7369, n7370, n7371, n7372, n7373,
n7374, n7375, n7376, n7377, n7378, n7379, n7380, n7381, n7382, n7383,
n7384, n7385, n7386, n7387, n7388, n7389, n7390, n7391, n7392, n7393,
n7394, n7395, n7396, n7397, n7398, n7399, n7400, n7401, n7402, n7403,
n7404, n7405, n7406, n7407, n7408, n7409, n7410, n7411, n7412, n7413,
n7414, n7415, n7416, n7417, n7418, n7419, n7420, n7421, n7422, n7423,
n7424, n7425, n7426, n7427, n7428, n7429, n7430, n7431, n7432, n7433,
n7434, n7435, n7436, n7437, n7438, n7439, n7440, n7441, n7442, n7443,
n7444, n7445, n7446, n7447, n7448, n7449, n7450, n7451, n7452, n7453,
n7454, n7455, n7456, n7457, n7458, n7459, n7460, n7461, n7462, n7463,
n7464, n7465, n7466, n7467, n7468, n7469, n7470, n7471, n7472, n7473,
n7474, n7475, n7476, n7477, n7478, n7479, n7480, n7481, n7482, n7483,
n7484, n7485, n7486, n7487, n7488, n7489, n7490, n7491, n7492, n7493,
n7494, n7495, n7496, n7497, n7498, n7499, n7500, n7501, n7502, n7503,
n7504, n7505, n7506, n7507, n7508, n7509, n7510, n7511, n7512, n7513,
n7514, n7515, n7516, n7517, n7518, n7519, n7520, n7521, n7522, n7523,
n7524, n7525, n7526, n7527, n7528, n7529, n7530, n7531, n7532, n7533,
n7534, n7535, n7536, n7537, n7538, n7539, n7540, n7541, n7542, n7543,
n7544, n7545, n7546, n7547, n7548, n7549, n7550, n7551, n7552, n7553,
n7554, n7555, n7556, n7557, n7558, n7559, n7560, n7561, n7562, n7563,
n7564, n7565, n7566, n7567, n7568, n7569, n7570, n7571, n7572, n7573,
n7574, n7575, n7576, n7577, n7578, n7579, n7580, n7581, n7582, n7583,
n7584, n7585, n7586, n7587, n7588, n7589, n7590, n7591, n7592, n7593,
n7594, n7595, n7596, n7597, n7598, n7599, n7600, n7601, n7602, n7603,
n7604, n7605, n7606, n7607, n7608, n7609, n7610, n7611, n7612, n7613,
n7614, n7615, n7616, n7617, n7618, n7619, n7620, n7621, n7622, n7623,
n7624, n7625, n7626, n7627, n7628, n7629, n7630, n7631, n7632, n7633,
n7634, n7635, n7636, n7637, n7638, n7639, n7640, n7641, n7642, n7643,
n7644, n7645, n7646, n7647, n7648, n7649, n7650, n7651, n7652, n7653,
n7654, n7655, n7656, n7657, n7658, n7659, n7660, n7661, n7662, n7663,
n7664, n7665, n7666, n7667, n7668, n7669, n7670, n7671, n7672, n7673,
n7674, n7675, n7676, n7677, n7678, n7679, n7680, n7681, n7682, n7683,
n7684, n7685, n7686, n7687, n7688, n7689, n7690, n7691, n7692, n7693,
n7694, n7695, n7696, n7697, n7698, n7699, n7700, n7701, n7702, n7703,
n7704, n7705, n7706, n7707, n7708, n7709, n7710, n7711, n7712, n7713,
n7714, n7715, n7716, n7717, n7718, n7719, n7720, n7721, n7722, n7723,
n7724, n7725, n7726, n7727, n7728, n7729, n7730, n7731, n7732, n7733,
n7734, n7735, n7736, n7737, n7738, n7739, n7740, n7741, n7742, n7743,
n7744, n7745, n7746, n7747, n7748, n7749, n7750, n7751, n7752, n7753,
n7754, n7755, n7756, n7757, n7758, n7759, n7760, n7761, n7762, n7763,
n7764, n7765, n7766, n7767, n7768, n7769, n7770, n7771, n7772, n7773,
n7774, n7775, n7776, n7777, n7778, n7779, n7780, n7781, n7782, n7783,
n7784, n7785, n7786, n7787, n7788, n7789, n7790, n7791, n7792, n7793,
n7794, n7795, n7796, n7797, n7798, n7799, n7800, n7801, n7802, n7803,
n7804, n7805, n7806, n7807, n7808, n7809, n7810, n7811, n7812, n7813,
n7814, n7815, n7816, n7817, n7818, n7819, n7820, n7821, n7822, n7823,
n7824, n7825, n7826, n7827, n7828, n7829, n7830, n7831, n7832, n7833,
n7834, n7835, n7836, n7837, n7838, n7839, n7840, n7841, n7842, n7843,
n7844, n7845, n7846, n7847, n7848, n7849, n7850, n7851, n7852, n7853,
n7854, n7855, n7856, n7857, n7858, n7859, n7860, n7861, n7862, n7863,
n7864, n7865, n7866, n7867, n7868, n7869, n7870, n7871, n7872, n7873,
n7874, n7875, n7876, n7877, n7878, n7879, n7880, n7881, n7882, n7883,
n7884, n7885, n7886, n7887, n7888, n7889, n7890, n7891, n7892, n7893,
n7894, n7895, n7896, n7897, n7898, n7899, n7900, n7901, n7902, n7903,
n7904, n7905, n7906, n7907, n7908, n7909, n7910, n7911, n7912, n7913,
n7914, n7915, n7916, n7917, n7918, n7919, n7920, n7921, n7922, n7923,
n7924, n7925, n7926, n7927, n7928, n7929, n7930, n7931, n7932, n7933,
n7934, n7935, n7936, n7937, n7938, n7939, n7940, n7941, n7942, n7943,
n7944, n7945, n7946, n7947, n7948, n7949, n7950, n7951, n7952, n7953,
n7954, n7955, n7956, n7957, n7958, n7959, n7960, n7961, n7962, n7963,
n7964, n7965, n7966, n7967, n7968, n7969, n7970, n7971, n7972, n7973,
n7974, n7975, n7976, n7977, n7978, n7979, n7980, n7981, n7982, n7983,
n7984, n7985, n7986, n7987, n7988, n7989, n7990, n7991, n7992, n7993,
n7994, n7995, n7996, n7997, n7998, n7999, n8000, n8001, n8002, n8003,
n8004, n8005, n8006, n8007, n8008, n8009, n8010, n8011, n8012, n8013,
n8014, n8015, n8016, n8017, n8018, n8019, n8020, n8021, n8022, n8023,
n8024, n8025, n8026, n8027, n8028, n8029, n8030, n8031, n8032, n8033,
n8034, n8035, n8036, n8037, n8038, n8039, n8040, n8041, n8042, n8043,
n8044, n8045, n8046, n8047, n8048, n8049, n8050, n8051, n8052, n8053,
n8054, n8055, n8056, n8057, n8058, n8059, n8060, n8061, n8062, n8063,
n8064, n8065, n8066, n8067, n8068, n8069, n8070, n8071, n8072, n8073,
n8074, n8075, n8076, n8077, n8078, n8079, n8080, n8081, n8082, n8083,
n8084, n8085, n8086, n8087, n8088, n8089, n8090, n8091, n8092, n8093,
n8094, n8095, n8096, n8097, n8098, n8099, n8100, n8101, n8102, n8103,
n8104, n8105, n8106, n8107, n8108, n8109, n8110, n8111, n8112, n8113,
n8114, n8115, n8116, n8117, n8118, n8119, n8120, n8121, n8122, n8123,
n8124, n8125, n8126, n8127, n8128, n8129, n8130, n8131, n8132, n8133,
n8134, n8135, n8136, n8137, n8138, n8139, n8140, n8141, n8142, n8143,
n8144, n8145, n8146, n8147, n8148, n8149, n8150, n8151, n8152, n8153,
n8154, n8155, n8156, n8157, n8158, n8159, n8160, n8161, n8162, n8163,
n8164, n8165, n8166, n8167, n8168, n8169, n8170, n8171, n8172, n8173,
n8174, n8175, n8176, n8177, n8178, n8179, n8180, n8181, n8182, n8183,
n8184, n8185, n8186, n8187, n8188, n8189, n8190, n8191, n8192, n8193,
n8194, n8195, n8196, n8197, n8198, n8199, n8200, n8201, n8202, n8203,
n8204, n8205, n8206, n8207, n8208, n8209, n8210, n8211, n8212, n8213,
n8214, n8215, n8216, n8217, n8218, n8219, n8220, n8221, n8222, n8223,
n8224, n8225, n8226, n8227, n8228, n8229, n8230, n8231, n8232, n8233,
n8234, n8235, n8236, n8237, n8238, n8239, n8240, n8241, n8242, n8243,
n8244, n8245, n8246, n8247, n8248, n8249, n8250, n8251, n8252, n8253,
n8254, n8255, n8256, n8257, n8258, n8259, n8260, n8261, n8262, n8263,
n8264, n8265, n8266, n8267, n8268, n8269, n8270, n8271, n8272, n8273,
n8274, n8275, n8276, n8277, n8278, n8279, n8280, n8281, n8282, n8283,
n8284, n8285, n8286, n8287, n8288, n8289, n8290, n8291, n8292, n8293,
n8294, n8295, n8296, n8297, n8298, n8299, n8300, n8301, n8302, n8303,
n8304, n8305, n8306, n8307, n8308, n8309, n8310, n8311, n8312, n8313,
n8314, n8315, n8316, n8317, n8318, n8319, n8320, n8321, n8322, n8323,
n8324, n8325, n8326, n8327, n8328, n8329, n8330, n8331, n8332, n8333,
n8334, n8335, n8336, n8337, n8338, n8339, n8340, n8341, n8342, n8343,
n8344, n8345, n8346, n8347, n8348, n8349, n8350, n8351, n8352, n8353,
n8354, n8355, n8356, n8357, n8358, n8359, n8360, n8361, n8362, n8363,
n8364, n8365, n8366, n8367, n8368, n8369, n8370, n8371, n8372, n8373,
n8374, n8375, n8377, n8378, n8379, n8380, n8381, n8382, n8383, n8384,
n8385, n8386, n8387, n8388, n8389, n8390, n8391, n8392, n8393, n8394,
n8395, n8396, n8397, n8398, n8399, n8400, n8401, n8402, n8403, n8404,
n8405, n8406, n8407, n8408, n8409, n8410, n8411, n8412, n8413, n8414,
n8415, n8416, n8417, n8418, n8419, n8420, n8421, n8422, n8423, n8424,
n8425, n8426, n8427, n8428, n8429, n8430, n8431, n8432, n8433, n8434,
n8435, n8436, n8437, n8438, n8439, n8440, n8441, n8442, n8443, n8444,
n8445, n8446, n8447, n8448, n8449, n8450, n8451, n8452, n8453, n8454,
n8455, n8456, n8457, n8458, n8459, n8460, n8461, n8462, n8463, n8464,
n8465, n8466, n8467, n8468, n8469, n8470, n8471, n8472, n8473, n8474,
n8475, n8476, n8477, n8478, n8479, n8480, n8481, n8482, n8483, n8484,
n8485, n8486, n8487, n8488, n8489, n8490, n8491, n8492, n8493, n8494,
n8495, n8496, n8497, n8498, n8499, n8500, n8501, n8502, n8503, n8504,
n8505, n8506, n8507, n8508, n8509, n8510, n8511, n8512, n8513, n8514,
n8515, n8516, n8517, n8518, n8519, n8520, n8521, n8522, n8523, n8524,
n8525, n8526, n8527, n8528, n8529, n8530, n8531, n8532, n8533, n8534,
n8535, n8536, n8537, n8538, n8539, n8540, n8541, n8542, n8543, n8544,
n8545, n8546, n8547, n8548, n8549, n8550, n8551, n8552, n8553, n8554,
n8555, n8556, n8557, n8558, n8559, n8560, n8561, n8562, n8563, n8564,
n8565, n8566, n8567, n8568, n8569, n8570, n8571, n8572, n8573, n8574,
n8575, n8576, n8577, n8578, n8579, n8580, n8581, n8582, n8583, n8584,
n8585, n8586, n8587, n8588, n8589, n8590, n8591, n8592, n8593, n8594,
n8595, n8596, n8597, n8598, n8599, n8600, n8601, n8602, n8603, n8604,
n8606, n8607, n8608, n8609, n8610, n8611, n8612, n8613, n8614, n8615,
n8616, n8617, n8618, n8619, n8620, n8621, n8622, n8623, n8624, n8625,
n8626, n8627, n8628, n8629, n8630, n8631, n8632, n8633, n8634, n8635,
n8636, n8637, n8638, n8639, n8640, n8641, n8642, n8643, n8644, n8645,
n8646, n8647, n8648, n8649, n8650, n8651, n8652, n8653, n8654, n8655,
n8656, n8657, n8658, n8659, n8660, n8661, n8662, n8663, n8664, n8665,
n8666, n8667, n8668, n8669, n8670, n8671, n8672, n8673, n8674, n8675,
n8676, n8677, n8678, n8679, n8680, n8681, n8682, n8683, n8684, n8685,
n8686, n8687, n8688, n8689, n8690, n8691, n8692, n8693, n8694, n8695,
n8696, n8697, n8698, n8699, n8700, n8701, n8702, n8703, n8704, n8705,
n8706, n8707, n8708, n8709, n8710, n8711, n8712, n8713, n8714, n8715,
n8716, n8717, n8718, n8719, n8720, n8721, n8722, n8723, n8724, n8725,
n8726, n8727, n8728, n8729, n8730, n8731, n8732, n8733, n8734, n8735,
n8736, n8737, n8738, n8739, n8740, n8741, n8742, n8743, n8744, n8745,
n8746, n8747, n8748, n8749, n8750, n8751, n8752, n8753, n8754, n8755,
n8756, n8757, n8758, n8759, n8760, n8761, n8762, n8763, n8764, n8765,
n8766, n8767, n8768, n8769, n8770, n8771, n8772, n8773, n8774, n8775,
n8776, n8777, n8778, n8779, n8780, n8781, n8782, n8783, n8784, n8785,
n8786, n8787, n8788, n8789, n8790, n8791, n8792, n8793, n8797, n8798,
n8800, n8803, n8804, n8805, n8806, n8807, n8808, n8809, n8810, n8811,
n8812, n8813, n8814, n8815, n8816, n8817, n8818, n8819, n8820, n8821,
n8822, n8823, n8824, n8825, n8826, n8827, n8828, n8829, n8830, n8831,
n8832, n8833, n8834, n8835, n8836, n8837, n8838, n8839, n8840, n8841,
n8842, n8843, n8844, n8845, n8846, n8847, n8848, n8849, n8850, n8851,
n8852, n8853, n8854, n8855, n8856, n8857, n8858, n8859, n8860, n8861,
n8862, n8863, n8864, n8865, n8866, n8867, n8868, n8869, n8870, n8871,
n8872, n8873, n8874, n8875, n8876, n8877, n8878, n8879, n8880, n8881,
n8882, n8883, n8884, n8885, n8886, n8887, n8888, n8889, n8890, n8891,
n8892, n8893, n8894, n8895, n8896, n8897, n8898, n8899, n8900, n8901,
n8902, n8903, n8904, n8905, n8906, n8907, n8908, n8909, n8910, n8911,
n8912, n8913, n8914, n8915, n8916, n8917, n8918, n8919, n8920, n8921,
n8922, n8923, n8924, n8925, n8926, n8927, n8928, n8929, n8930, n8931,
n8932, n8933, n8934, n8935, n8936, n8937, n8938, n8939, n8940, n8941,
n8942, n8943, n8944, n8945, n8946, n8947, n8948, n8949, n8950, n8951,
n8952, n8953, n8954, n8955, n8956, n8957, n8958, n8959, n8960, n8961,
n8962, n8963, n8964, n8965, n8966, n8967, n8968, n8969, n8970, n8971,
n8972, n8973, n8974, n8975, n8976, n8977, n8978, n8979, n8980, n8981,
n8982, n8983, n8984, n8985, n8986, n8987, n8988, n8989, n8990, n8991,
n8992, n8993, n8994, n8995, n8996, n8997, n8998, n8999, n9000, n9001,
n9002, n9003, n9004, n9005, n9006, n9007, n9008, n9009, n9010, n9011,
n9012, n9013, n9014, n9015, n9016, n9017, n9018, n9019, n9020, n9021,
n9022, n9023, n9024, n9025, n9026, n9027, n9028, n9029, n9030, n9031,
n9032, n9033, n9034, n9035, n9036, n9037, n9038, n9039, n9040, n9041,
n9042, n9043, n9044, n9045, n9046, n9047, n9048, n9049, n9050, n9051,
n9052, n9053, n9054, n9055, n9056, n9057, n9058, n9059, n9060, n9061,
n9062, n9063, n9064, n9065, n9066, n9067, n9068, n9069, n9070, n9071,
n9072, n9073, n9074, n9075, n9076, n9077, n9078, n9079, n9080, n9081,
n9082, n9083, n9084, n9085, n9086, n9087, n9088, n9089, n9090, n9091,
n9092, n9093, n9094, n9095, n9096, n9097, n9098, n9099, n9100, n9101,
n9102, n9103, n9104, n9105, n9106, n9107, n9108, n9109, n9110, n9111,
n9112, n9113, n9114, n9115, n9116, n9117, n9118, n9119, n9120, n9121,
n9122, n9123, n9124, n9125, n9126, n9127, n9128, n9129, n9130, n9131,
n9132, n9133, n9134, n9135, n9136, n9137, n9138, n9139, n9140, n9141,
n9142, n9143, n9144, n9145, n9146, n9147, n9148, n9149, n9150, n9151,
n9152, n9153, n9154, n9155, n9156, n9157, n9158, n9159, n9160, n9161,
n9162, n9163, n9164, n9165, n9166, n9167, n9168, n9169, n9170, n9171,
n9172, n9173, n9174, n9175, n9176, n9177, n9178, n9179, n9180, n9181,
n9182, n9183, n9184, n9185, n9186, n9187, n9188, n9189, n9190, n9191,
n9192, n9193, n9194, n9195, n9196, n9197, n9198, n9199, n9200, n9201,
n9202, n9203, n9204, n9205, n9206, n9207, n9208, n9209, n9210, n9211,
n9212, n9213, n9214, n9215, n9216, n9217, n9218, n9219, n9220, n9221,
n9222, n9223, n9224, n9225, n9226, n9227, n9228, n9229, n9230, n9231,
n9232, n9233, n9234, n9235, n9236, n9237, n9238, n9239, n9240, n9241,
n9242, n9243, n9244, n9245, n9246, n9247, n9248, n9249, n9250, n9251,
n9252, n9253, n9254, n9255, n9256, n9257, n9258, n9259, n9260, n9261,
n9262, n9263, n9264, n9265, n9266, n9267, n9268, n9269, n9270, n9271,
n9272, n9273, n9274, n9275, n9276, n9277, n9278, n9279, n9280, n9281,
n9282, n9283, n9284, n9285, n9286, n9287, n9288, n9289, n9290, n9291,
n9292, n9293, n9294, n9295, n9296, n9297, n9298, n9299, n9300, n9301,
n9302, n9303, n9304, n9305, n9306, n9307, n9308, n9309, n9310, n9311,
n9312, n9313, n9314, n9315, n9316, n9317, n9318, n9319, n9320, n9321,
n9322, n9323, n9324, n9325, n9326, n9327, n9328, n9329, n9330, n9331,
n9332, n9333, n9334, n9335, n9336, n9337, n9338, n9339, n9340, n9341,
n9342, n9343, n9344, n9345, n9346, n9347, n9348, n9349, n9350, n9351,
n9352, n9353, n9354, n9355, n9356, n9357, n9358, n9359, n9360, n9361,
n9362, n9363, n9364, n9365, n9366, n9367, n9368, n9369, n9370, n9371,
n9372, n9373, n9374, n9375, n9376, n9377, n9378, n9379, n9380, n9381,
n9382, n9383, n9384, n9385, n9386, n9387, n9388, n9389, n9390, n9391,
n9392, n9393, n9394, n9395, n9396, n9397, n9398, n9399, n9400, n9401,
n9402, n9403, n9404, n9405, n9406, n9407, n9408, n9409, n9410, n9411,
n9412, n9413, n9414, n9415, n9416, n9417, n9418, n9419, n9420, n9421,
n9422, n9423, n9424, n9425, n9426, n9427, n9428, n9429, n9430, n9431,
n9432, n9433, n9434, n9435, n9436, n9437, n9438, n9439, n9440, n9441,
n9442, n9443, n9444, n9445, n9446, n9447, n9448, n9449, n9450, n9451,
n9452, n9453, n9454, n9455, n9456, n9457, n9458, n9459, n9460, n9461,
n9462, n9463, n9464, n9465, n9466, n9467, n9468, n9469, n9470, n9471,
n9472, n9473, n9474, n9475, n9476, n9477, n9478, n9479, n9480, n9481,
n9482, n9483, n9484, n9485, n9486, n9487, n9488, n9489, n9490, n9491,
n9492, n9493, n9494, n9495, n9496, n9497, n9498, n9499, n9500, n9501,
n9502, n9503, n9504, n9505, n9506, n9507, n9508, n9509, n9510, n9511,
n9512, n9513, n9514, n9515, n9516, n9517, n9518, n9519, n9520, n9521,
n9522, n9523, n9524, n9525, n9526, n9527, n9528, n9529, n9530, n9531,
n9532, n9533, n9534, n9535, n9536, n9537, n9538, n9539, n9540, n9541,
n9542, n9543, n9544, n9545, n9546, n9547, n9548, n9549, n9550, n9551,
n9552, n9553, n9554, n9555, n9556, n9557, n9558, n9559, n9560, n9561,
n9562, n9563, n9564, n9565, n9566, n9567, n9568, n9569, n9570, n9571,
n9572, n9573, n9574, n9575, n9576, n9577, n9578, n9579, n9580, n9581,
n9582, n9583, n9584, n9585, n9586, n9587, n9588, n9589, n9590, n9591,
n9592, n9593, n9594, n9595, n9596, n9597, n9598, n9599, n9600, n9601,
n9602, n9603, n9604, n9605, n9606, n9607, n9608, n9609, n9610, n9611,
n9612, n9613, n9614, n9615, n9616, n9617, n9618, n9619, n9620, n9621,
n9622, n9623, n9624, n9625, n9626, n9627, n9628, n9629, n9630, n9631,
n9632, n9633, n9634, n9635, n9636, n9637, n9638, n9639, n9640, n9641,
n9642, n9643, n9644, n9645, n9646, n9647, n9648, n9649, n9650, n9651,
n9652, n9653, n9654, n9655, n9656, n9657, n9658, n9659, n9660, n9661,
n9662, n9663, n9664, n9665, n9666, n9667, n9668, n9669, n9670, n9671,
n9672, n9673, n9674, n9675, n9676, n9677, n9678, n9679, n9680, n9681,
n9682, n9683, n9684, n9685, n9686, n9687, n9688, n9689, n9690, n9691,
n9692, n9693, n9694, n9695, n9696, n9697, n9698, n9699, n9700, n9701,
n9702, n9703, n9704, n9705, n9706, n9707, n9708, n9709, n9710, n9711,
n9712, n9713, n9714, n9715, n9716, n9717, n9718, n9719, n9720, n9721,
n9722, n9723, n9724, n9725, n9726, n9727, n9728, n9729, n9730, n9731,
n9732, n9733, n9734, n9735, n9736, n9737, n9738, n9739, n9740, n9741,
n9742, n9743, n9744, n9745, n9746, n9747, n9748, n9749, n9750, n9751,
n9752, n9753, n9754, n9755, n9756, n9757, n9758, n9759, n9760, n9761,
n9762, n9763, n9764, n9765, n9766, n9767, n9768, n9769, n9770, n9771,
n9772, n9773, n9774, n9775, n9776, n9777, n9778, n9779, n9780, n9781,
n9782, n9783, n9784, n9785, n9786, n9787, n9788, n9789, n9790, n9791,
n9792, n9793, n9794, n9795, n9796, n9797, n9798, n9799, n9800, n9801,
n9802, n9803, n9804, n9805, n9806, n9807, n9808, n9809, n9810, n9811,
n9812, n9813, n9814, n9815, n9816, n9817, n9818, n9819, n9820, n9821,
n9822, n9823, n9824, n9825, n9826, n9827, n9828, n9829, n9830, n9831,
n9832, n9833, n9834, n9835, n9836, n9837, n9838, n9839, n9840, n9841,
n9842, n9843, n9844, n9845, n9846, n9847, n9848, n9849, n9850, n9851,
n9852, n9853, n9854, n9855, n9856, n9857, n9858, n9859, n9860, n9861,
n9862, n9863, n9864, n9865, n9866, n9867, n9868, n9869, n9870, n9871,
n9872, n9873, n9874, n9875, n9876, n9877, n9878, n9879, n9880, n9881,
n9882, n9883, n9884, n9885, n9886, n9887, n9888, n9889, n9890, n9891,
n9892, n9893, n9894, n9895, n9896, n9897, n9898, n9899, n9900, n9901,
n9902, n9903, n9904, n9905, n9906, n9907, n9908, n9909, n9910, n9911,
n9912, n9913, n9914, n9915, n9916, n9917, n9918, n9919, n9920, n9921,
n9922, n9923, n9924, n9925, n9926, n9927, n9928, n9929, n9930, n9931,
n9932, n9933, n9934, n9935, n9936, n9937, n9938, n9939, n9940, n9941,
n9942, n9943, n9944, n9945, n9946, n9947, n9948, n9949, n9950, n9951,
n9952, n9953, n9954, n9955, n9956, n9957, n9958, n9959, n9960, n9961,
n9962, n9963, n9964, n9965, n9966, n9967, n9968, n9969, n9970, n9971,
n9972;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [17:1] FPMULT_Add_result;
wire [7:0] FPMULT_exp_oper_result;
wire [31:7] FPMULT_Op_MY;
wire [31:4] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [13:0] FPMULT_P_Sgf;
wire [25:0] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:1] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [11:6] FPMULT_Sgf_operation_EVEN1_S_B;
wire [23:22] FPMULT_Sgf_operation_EVEN1_Q_right;
wire [22:0] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [18:3] FPMULT_Adder_M_result_A_adder;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
wire [13:6] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [10:3] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
DFFRX4TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n9815), .Q(
dataA[29]) );
DFFRX4TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n9815), .Q(
dataA[30]) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2143), .CK(clk), .RN(n9816),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n3630) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2142), .CK(clk), .RN(n9814),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n9242) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2141), .CK(clk), .RN(n2911),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n3639) );
DFFRX4TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n9813), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .QN(n9270) );
DFFRX4TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n9813), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n9267) );
DFFRX4TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n9813), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n9268) );
DFFRX4TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2193), .CK(
clk), .RN(n9773), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n9465) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n9808), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2133), .CK(clk), .RN(n9806), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2132), .CK(clk), .RN(n9815), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2130), .CK(clk), .RN(n9777), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2128), .CK(clk), .RN(n9783), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2127), .CK(clk), .RN(n9782), .Q(
FPSENCOS_d_ff3_LUT_out[8]), .QN(n9398) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2126), .CK(clk), .RN(n9780), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2124), .CK(clk), .RN(n9785), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2120), .CK(clk), .RN(n9775), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2119), .CK(clk), .RN(n9776), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2117), .CK(clk), .RN(n9776), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2116), .CK(clk), .RN(n9775), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1855), .CK(clk), .RN(n9776),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1851), .CK(clk), .RN(n9775),
.Q(FPSENCOS_d_ff3_sh_y_out[27]), .QN(n3643) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1848), .CK(clk), .RN(n9789),
.Q(FPSENCOS_d_ff3_sh_y_out[30]), .QN(n9331) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1953), .CK(clk), .RN(n9776),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1950), .CK(clk), .RN(n9775),
.Q(FPSENCOS_d_ff3_sh_x_out[26]), .QN(n2917) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1949), .CK(clk), .RN(n9775),
.Q(FPSENCOS_d_ff3_sh_x_out[27]), .QN(n3645) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1947), .CK(clk), .RN(n9809),
.Q(FPSENCOS_d_ff3_sh_x_out[29]), .QN(n3647) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1946), .CK(clk), .RN(n8973),
.Q(FPSENCOS_d_ff3_sh_x_out[30]), .QN(n9332) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2114), .CK(clk), .RN(n9806), .QN(
n3569) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2113), .CK(clk), .RN(n9807), .QN(
n3584) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2112), .CK(clk), .RN(n9777), .QN(
n3570) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2111), .CK(clk), .RN(n9803), .QN(
n3572) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2110), .CK(clk), .RN(n9781), .QN(
n3587) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2109), .CK(clk), .RN(n9777), .QN(
n3577) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2108), .CK(clk), .RN(n9780), .QN(
n3585) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2107), .CK(clk), .RN(n9782), .QN(
n3593) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2106), .CK(clk), .RN(n9781), .QN(
n3600) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2105), .CK(clk), .RN(n9779), .QN(
n3608) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2104), .CK(clk), .RN(n9779), .QN(
n3573) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2103), .CK(clk), .RN(n9779), .QN(
n3614) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2102), .CK(clk), .RN(n9779), .QN(
n3619) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2101), .CK(clk), .RN(n9779), .QN(
n3622) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2100), .CK(clk), .RN(n9779), .QN(
n3588) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2099), .CK(clk), .RN(n9779), .QN(
n3589) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2098), .CK(clk), .RN(n9779), .QN(
n3578) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2097), .CK(clk), .RN(n9779), .QN(
n3581) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2096), .CK(clk), .RN(n9778), .QN(
n3586) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2095), .CK(clk), .RN(n9778), .QN(
n3576) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2094), .CK(clk), .RN(n9777), .QN(
n3594) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2093), .CK(clk), .RN(n9778), .QN(
n3597) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2092), .CK(clk), .RN(n9774), .QN(
n3601) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2091), .CK(clk), .RN(n9774), .QN(
n3606) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2090), .CK(clk), .RN(n9791), .QN(
n3609) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2089), .CK(clk), .RN(n9791), .QN(
n3610) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2088), .CK(clk), .RN(n9791), .QN(
n3574) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2087), .CK(clk), .RN(n9790), .QN(
n3611) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2086), .CK(clk), .RN(n9790), .QN(
n3615) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2085), .CK(clk), .RN(n9790), .QN(
n3617) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2084), .CK(clk), .RN(n6442), .QN(
n3620) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2083), .CK(clk), .RN(n9777), .QN(
n3621) );
DFFRX1TS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1788), .CK(clk), .RN(n9774), .Q(
FPSENCOS_d_ff_Zn[23]), .QN(n9451) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1787), .CK(clk), .RN(n9788), .Q(
FPSENCOS_d_ff_Yn[23]), .QN(n9441) );
DFFRX4TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1863), .CK(clk), .RN(
n9788), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n9098) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n2843), .Q(
FPSENCOS_d_ff_Xn[23]), .QN(n9410) );
DFFRX4TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1961), .CK(clk), .RN(
n9787), .Q(FPSENCOS_d_ff2_X[23]), .QN(n9099) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n9796),
.Q(cordic_result[23]) );
DFFRX1TS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1785), .CK(clk), .RN(n9791), .Q(
FPSENCOS_d_ff_Zn[24]), .QN(n9450) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1784), .CK(clk), .RN(n9788), .Q(
FPSENCOS_d_ff_Yn[24]), .QN(n9440) );
DFFRX2TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1862), .CK(clk), .RN(
n9788), .Q(FPSENCOS_d_ff2_Y[24]) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1960), .CK(clk), .RN(
n9789), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n9796),
.Q(cordic_result[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1781), .CK(clk), .RN(n9788), .Q(
FPSENCOS_d_ff_Yn[25]), .QN(n9439) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1861), .CK(clk), .RN(
n9788), .Q(FPSENCOS_d_ff2_Y[25]) );
DFFRX2TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n9789), .Q(
FPSENCOS_d_ff_Xn[25]), .QN(n9278) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1959), .CK(clk), .RN(
n9789), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n9796),
.Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1779), .CK(clk), .RN(n9791), .Q(
FPSENCOS_d_ff_Zn[26]), .QN(n9448) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1778), .CK(clk), .RN(n2842), .Q(
FPSENCOS_d_ff_Yn[26]), .QN(n9438) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n9796),
.Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1776), .CK(clk), .RN(n9790), .Q(
FPSENCOS_d_ff_Zn[27]), .QN(n9447) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n2842), .Q(
FPSENCOS_d_ff_Yn[27]), .QN(n9437) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1859), .CK(clk), .RN(
n2843), .Q(FPSENCOS_d_ff2_Y[27]) );
DFFRX2TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n6441), .Q(
FPSENCOS_d_ff_Xn[27]), .QN(n9286) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1957), .CK(clk), .RN(
n2843), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n9796),
.Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1772), .CK(clk), .RN(n9788), .Q(
FPSENCOS_d_ff_Yn[28]), .QN(n9396) );
DFFRX2TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n2842), .Q(
FPSENCOS_d_ff_Xn[28]), .QN(n9277) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n9796),
.Q(cordic_result[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(n9788), .Q(
FPSENCOS_d_ff_Yn[29]), .QN(n9442) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1857), .CK(clk), .RN(
n9789), .Q(FPSENCOS_d_ff2_Y[29]) );
DFFRX2TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n2843), .Q(
FPSENCOS_d_ff_Xn[29]), .QN(n9287) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1955), .CK(clk), .RN(
n2842), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n9796),
.Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1767), .CK(clk), .RN(n9790), .Q(
FPSENCOS_d_ff_Zn[30]), .QN(n9200) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1732), .CK(clk), .RN(n2843), .Q(
FPSENCOS_d_ff_Yn[30]), .QN(n9172) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1731), .CK(clk), .RN(n9789), .Q(
FPSENCOS_d_ff_Xn[30]), .QN(n9171) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n9797),
.Q(cordic_result[30]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1790), .CK(clk), .RN(n2879),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2010), .CK(clk), .RN(n9793), .Q(
FPSENCOS_d_ff_Zn[22]), .QN(n9329) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1865), .CK(clk), .RN(
n9774), .Q(FPSENCOS_d_ff2_Y[22]), .QN(n9129) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1864), .CK(clk), .RN(n9774),
.Q(FPSENCOS_d_ff3_sh_y_out[22]), .QN(n9333) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n9775), .Q(
FPSENCOS_d_ff_Xn[22]), .QN(n9302) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1963), .CK(clk), .RN(
n9775), .Q(FPSENCOS_d_ff2_X[22]), .QN(n9130) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1962), .CK(clk), .RN(n9775),
.Q(FPSENCOS_d_ff3_sh_x_out[22]), .QN(n9334) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1810), .CK(clk), .RN(n2866), .Q(FPADDSUB_Data_array_SWR[21]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2031), .CK(clk), .RN(n9783), .Q(
FPSENCOS_d_ff_Zn[15]), .QN(n9316) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2030), .CK(clk), .RN(n9784), .Q(
FPSENCOS_d_ff_Yn[15]), .QN(n9352) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1879), .CK(clk), .RN(
n9784), .Q(FPSENCOS_d_ff2_Y[15]), .QN(n9419) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1878), .CK(clk), .RN(n9784),
.Q(FPSENCOS_d_ff3_sh_y_out[15]), .QN(n9151) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n9784), .Q(
FPSENCOS_d_ff_Xn[15]), .QN(n9306) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1976), .CK(clk), .RN(n9784),
.Q(FPSENCOS_d_ff3_sh_x_out[15]), .QN(n9337) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1794), .CK(clk), .RN(n2872),
.Q(FPADDSUB_Data_array_SWR[5]), .QN(n9388) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2022), .CK(clk), .RN(n9804), .Q(
FPSENCOS_d_ff_Zn[18]), .QN(n9324) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1873), .CK(clk), .RN(
n9804), .Q(FPSENCOS_d_ff2_Y[18]), .QN(n9424) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1872), .CK(clk), .RN(n9805),
.Q(FPSENCOS_d_ff3_sh_y_out[18]), .QN(n9157) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n9804), .Q(
FPSENCOS_d_ff_Xn[18]), .QN(n9308) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1971), .CK(clk), .RN(
n9804), .Q(FPSENCOS_d_ff2_X[18]), .QN(n9425) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1970), .CK(clk), .RN(n9805),
.Q(FPSENCOS_d_ff3_sh_x_out[18]), .QN(n9158) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1791), .CK(clk), .RN(n9758),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2013), .CK(clk), .RN(n9778), .Q(
FPSENCOS_d_ff_Zn[21]), .QN(n9311) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2012), .CK(clk), .RN(n9793), .Q(
FPSENCOS_d_ff_Yn[21]), .QN(n9366) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1866), .CK(clk), .RN(n9793),
.Q(FPSENCOS_d_ff3_sh_y_out[21]), .QN(n9168) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n9778), .Q(
FPSENCOS_d_ff_Xn[21]), .QN(n9303) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1965), .CK(clk), .RN(
n9778), .Q(FPSENCOS_d_ff2_X[21]), .QN(n9436) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1964), .CK(clk), .RN(n9793),
.Q(FPSENCOS_d_ff3_sh_x_out[21]), .QN(n9169) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1809), .CK(clk), .RN(n2848), .Q(FPADDSUB_Data_array_SWR[20]), .QN(n9393) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2019), .CK(clk), .RN(n9805), .Q(
FPSENCOS_d_ff_Zn[19]), .QN(n9325) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1871), .CK(clk), .RN(
n9805), .Q(FPSENCOS_d_ff2_Y[19]), .QN(n9426) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1870), .CK(clk), .RN(n9805),
.Q(FPSENCOS_d_ff3_sh_y_out[19]), .QN(n9159) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n9805), .Q(
FPSENCOS_d_ff_Xn[19]), .QN(n9297) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1968), .CK(clk), .RN(n9805),
.Q(FPSENCOS_d_ff3_sh_x_out[19]), .QN(n9405) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2016), .CK(clk), .RN(n9777), .Q(
FPSENCOS_d_ff_Zn[20]), .QN(n9310) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2015), .CK(clk), .RN(n9792), .Q(
FPSENCOS_d_ff_Yn[20]), .QN(n9365) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1869), .CK(clk), .RN(
n9792), .Q(FPSENCOS_d_ff2_Y[20]), .QN(n9434) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1868), .CK(clk), .RN(n9792),
.Q(FPSENCOS_d_ff3_sh_y_out[20]), .QN(n9167) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n9778), .Q(
FPSENCOS_d_ff_Xn[20]), .QN(n9280) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1967), .CK(clk), .RN(
n9778), .Q(FPSENCOS_d_ff2_X[20]), .QN(n9126) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1966), .CK(clk), .RN(n9792),
.Q(FPSENCOS_d_ff3_sh_x_out[20]), .QN(n9409) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1808), .CK(clk), .RN(n2926), .Q(FPADDSUB_Data_array_SWR[19]), .QN(n9395) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2025), .CK(clk), .RN(n9801), .Q(
FPSENCOS_d_ff_Zn[17]), .QN(n9320) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1874), .CK(clk), .RN(n9801),
.Q(FPSENCOS_d_ff3_sh_y_out[17]), .QN(n9152) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n9801), .Q(
FPSENCOS_d_ff_Xn[17]), .QN(n9295) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1973), .CK(clk), .RN(
n9801), .Q(FPSENCOS_d_ff2_X[17]), .QN(n9115) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1972), .CK(clk), .RN(n9801),
.Q(FPSENCOS_d_ff3_sh_x_out[17]), .QN(n9400) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1795), .CK(clk), .RN(n2869),
.Q(FPADDSUB_Data_array_SWR[6]), .QN(n9389) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2064), .CK(clk), .RN(n9798), .Q(
FPSENCOS_d_ff_Zn[4]), .QN(n9319) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2063), .CK(clk), .RN(n9774), .Q(
FPSENCOS_d_ff_Yn[4]), .QN(n9355) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1901), .CK(clk), .RN(
n9793), .Q(FPSENCOS_d_ff2_Y[4]), .QN(n9138) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1900), .CK(clk), .RN(n9809),
.Q(FPSENCOS_d_ff3_sh_y_out[4]), .QN(n9344) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n9812), .Q(
FPSENCOS_d_ff_Xn[4]), .QN(n9307) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1999), .CK(clk), .RN(
n9798), .Q(FPSENCOS_d_ff2_X[4]), .QN(n9139) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1998), .CK(clk), .RN(n9798),
.Q(FPSENCOS_d_ff3_sh_x_out[4]), .QN(n9345) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1805), .CK(clk), .RN(n2859), .Q(FPADDSUB_Data_array_SWR[16]), .QN(n9392) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2058), .CK(clk), .RN(n9781), .Q(
FPSENCOS_d_ff_Zn[6]), .QN(n9313) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2057), .CK(clk), .RN(n9781), .Q(
FPSENCOS_d_ff_Yn[6]), .QN(n9349) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1896), .CK(clk), .RN(n9781),
.Q(FPSENCOS_d_ff3_sh_y_out[6]), .QN(n9147) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1994), .CK(clk), .RN(n9781),
.Q(FPSENCOS_d_ff3_sh_x_out[6]), .QN(n9397) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1803), .CK(clk), .RN(n2857), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2037), .CK(clk), .RN(n9801), .Q(
FPSENCOS_d_ff_Zn[13]), .QN(n9321) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2036), .CK(clk), .RN(n9802), .Q(
FPSENCOS_d_ff_Yn[13]), .QN(n9357) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1883), .CK(clk), .RN(
n9802), .Q(FPSENCOS_d_ff2_Y[13]), .QN(n9420) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1882), .CK(clk), .RN(n9802),
.Q(FPSENCOS_d_ff3_sh_y_out[13]), .QN(n9153) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n9802), .Q(
FPSENCOS_d_ff_Xn[13]), .QN(n9282) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1981), .CK(clk), .RN(
n9802), .Q(FPSENCOS_d_ff2_X[13]), .QN(n9122) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1980), .CK(clk), .RN(n9802),
.Q(FPSENCOS_d_ff3_sh_x_out[13]), .QN(n9401) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1796), .CK(clk), .RN(n9767),
.Q(FPADDSUB_Data_array_SWR[7]), .QN(n9299) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2028), .CK(clk), .RN(n9785), .Q(
FPSENCOS_d_ff_Zn[16]), .QN(n9318) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2027), .CK(clk), .RN(n9813), .Q(
FPSENCOS_d_ff_Yn[16]), .QN(n9354) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1876), .CK(clk), .RN(n9800),
.Q(FPSENCOS_d_ff3_sh_y_out[16]), .QN(n9340) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1975), .CK(clk), .RN(
n9785), .Q(FPSENCOS_d_ff2_X[16]), .QN(n9120) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1974), .CK(clk), .RN(n9800),
.Q(FPSENCOS_d_ff3_sh_x_out[16]), .QN(n9341) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2052), .CK(clk), .RN(n9782), .Q(
FPSENCOS_d_ff_Zn[8]), .QN(n9314) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2051), .CK(clk), .RN(n9782), .Q(
FPSENCOS_d_ff_Yn[8]), .QN(n9350) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1893), .CK(clk), .RN(
n9782), .Q(FPSENCOS_d_ff2_Y[8]), .QN(n9416) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1892), .CK(clk), .RN(n9782),
.Q(FPSENCOS_d_ff3_sh_y_out[8]), .QN(n9148) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n9782), .Q(
FPSENCOS_d_ff_Xn[8]), .QN(n9305) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1991), .CK(clk), .RN(
n9782), .Q(FPSENCOS_d_ff2_X[8]), .QN(n9417) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1990), .CK(clk), .RN(n9782),
.Q(FPSENCOS_d_ff3_sh_x_out[8]), .QN(n9149) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1801), .CK(clk), .RN(n2849), .Q(FPADDSUB_Data_array_SWR[12]), .QN(n9300) );
DFFRX1TS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2043), .CK(clk), .RN(n9800), .Q(
FPSENCOS_d_ff_Zn[11]), .QN(n9452) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2042), .CK(clk), .RN(n9800), .Q(
FPSENCOS_d_ff_Yn[11]), .QN(n9443) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1887), .CK(clk), .RN(
n9800), .Q(FPSENCOS_d_ff2_Y[11]), .QN(n9136) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1886), .CK(clk), .RN(n9800),
.Q(FPSENCOS_d_ff3_sh_y_out[11]), .QN(n9342) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n9800), .Q(
FPSENCOS_d_ff_Xn[11]), .QN(n9411) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1985), .CK(clk), .RN(
n9800), .Q(FPSENCOS_d_ff2_X[11]), .QN(n9137) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1984), .CK(clk), .RN(n9800),
.Q(FPSENCOS_d_ff3_sh_x_out[11]), .QN(n9343) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1798), .CK(clk), .RN(n2873),
.Q(FPADDSUB_Data_array_SWR[9]), .QN(n9386) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2034), .CK(clk), .RN(n9802), .Q(
FPSENCOS_d_ff_Zn[14]), .QN(n9322) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2033), .CK(clk), .RN(n9815), .Q(
FPSENCOS_d_ff_Yn[14]), .QN(n9358) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1881), .CK(clk), .RN(
n9815), .Q(FPSENCOS_d_ff2_Y[14]), .QN(n9421) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1880), .CK(clk), .RN(n6442),
.Q(FPSENCOS_d_ff3_sh_y_out[14]), .QN(n9154) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n9802), .Q(
FPSENCOS_d_ff_Xn[14]), .QN(n9296) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1978), .CK(clk), .RN(n9816),
.Q(FPSENCOS_d_ff3_sh_x_out[14]), .QN(n9402) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1802), .CK(clk), .RN(n2859), .Q(FPADDSUB_Data_array_SWR[13]), .QN(n9390) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2046), .CK(clk), .RN(n9810), .Q(
FPSENCOS_d_ff_Zn[10]), .QN(n9413) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1756), .CK(clk), .RN(
n9816), .Q(FPSENCOS_d_ff2_Z[10]), .QN(n2919) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2045), .CK(clk), .RN(n9814), .Q(
FPSENCOS_d_ff_Yn[10]), .QN(n9444) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1888), .CK(clk), .RN(n9803),
.Q(FPSENCOS_d_ff3_sh_y_out[10]), .QN(n9155) );
DFFRX2TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n9815), .Q(
FPSENCOS_d_ff_Xn[10]), .QN(n9288) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1987), .CK(clk), .RN(
n9814), .Q(FPSENCOS_d_ff2_X[10]), .QN(n9123) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1986), .CK(clk), .RN(n9803),
.Q(FPSENCOS_d_ff3_sh_x_out[10]), .QN(n9403) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1800), .CK(clk), .RN(n2858), .Q(FPADDSUB_Data_array_SWR[11]), .QN(n9263) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2040), .CK(clk), .RN(n9784), .Q(
FPSENCOS_d_ff_Zn[12]), .QN(n9317) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2039), .CK(clk), .RN(n9785), .Q(
FPSENCOS_d_ff_Yn[12]), .QN(n9353) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1884), .CK(clk), .RN(n9785),
.Q(FPSENCOS_d_ff3_sh_y_out[12]), .QN(n9338) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n9784), .Q(
FPSENCOS_d_ff_Xn[12]), .QN(n9294) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1983), .CK(clk), .RN(
n9785), .Q(FPSENCOS_d_ff2_X[12]), .QN(n9128) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1982), .CK(clk), .RN(n9785),
.Q(FPSENCOS_d_ff3_sh_x_out[12]), .QN(n9339) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1911), .CK(clk), .RN(n9792), .Q(
FPSENCOS_d_ff_Zn[31]), .QN(n9414) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1735), .CK(clk), .RN(
n9792), .Q(FPSENCOS_d_ff2_Z[31]), .QN(n9170) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1734), .CK(clk), .RN(n9809), .Q(
FPSENCOS_d_ff3_sign_out), .QN(n9453) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(n9809), .Q(
FPSENCOS_d_ff_Yn[31]), .QN(n9412) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1846), .CK(clk), .RN(n9792),
.Q(FPSENCOS_d_ff3_sh_y_out[31]), .QN(n9165) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n9792), .Q(
FPSENCOS_d_ff_Xn[31]), .QN(n9346) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1945), .CK(clk), .RN(
n9792), .Q(FPSENCOS_d_ff2_X[31]), .QN(n9433) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1944), .CK(clk), .RN(n9792),
.Q(FPSENCOS_d_ff3_sh_x_out[31]), .QN(n9166) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2067), .CK(clk), .RN(n9803), .Q(
FPSENCOS_d_ff_Zn[3]), .QN(n9323) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1903), .CK(clk), .RN(
n9804), .Q(FPSENCOS_d_ff2_Y[3]), .QN(n9423) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1902), .CK(clk), .RN(n9804),
.Q(FPSENCOS_d_ff3_sh_y_out[3]), .QN(n9156) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n2001), .CK(clk), .RN(
n9803), .Q(FPSENCOS_d_ff2_X[3]), .QN(n9117) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n2000), .CK(clk), .RN(n9804),
.Q(FPSENCOS_d_ff3_sh_x_out[3]), .QN(n9404) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2070), .CK(clk), .RN(n9806), .Q(
FPSENCOS_d_ff_Zn[2]), .QN(n9326) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2069), .CK(clk), .RN(n9806), .Q(
FPSENCOS_d_ff_Yn[2]), .QN(n9362) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1905), .CK(clk), .RN(
n9806), .Q(FPSENCOS_d_ff2_Y[2]), .QN(n9427) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1904), .CK(clk), .RN(n9806),
.Q(FPSENCOS_d_ff3_sh_y_out[2]), .QN(n9160) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2002), .CK(clk), .RN(n9806),
.Q(FPSENCOS_d_ff3_sh_x_out[2]), .QN(n9406) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2055), .CK(clk), .RN(n9783), .Q(
FPSENCOS_d_ff_Zn[7]), .QN(n9315) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2054), .CK(clk), .RN(n9783), .Q(
FPSENCOS_d_ff_Yn[7]), .QN(n9351) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1895), .CK(clk), .RN(
n9783), .Q(FPSENCOS_d_ff2_Y[7]), .QN(n9418) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1894), .CK(clk), .RN(n9783),
.Q(FPSENCOS_d_ff3_sh_y_out[7]), .QN(n9150) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1993), .CK(clk), .RN(
n9783), .Q(FPSENCOS_d_ff2_X[7]), .QN(n9114) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1992), .CK(clk), .RN(n9783),
.Q(FPSENCOS_d_ff3_sh_x_out[7]), .QN(n9399) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2076), .CK(clk), .RN(n9807), .Q(
FPSENCOS_d_ff_Zn[0]), .QN(n9327) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2075), .CK(clk), .RN(n9807), .Q(
FPSENCOS_d_ff_Yn[0]), .QN(n9330) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1909), .CK(clk), .RN(
n9807), .Q(FPSENCOS_d_ff2_Y[0]), .QN(n9428) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1908), .CK(clk), .RN(n9807),
.Q(FPSENCOS_d_ff3_sh_y_out[0]), .QN(n9161) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2006), .CK(clk), .RN(n9807),
.Q(FPSENCOS_d_ff3_sh_x_out[0]), .QN(n9162) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2073), .CK(clk), .RN(n9807), .Q(
FPSENCOS_d_ff_Zn[1]), .QN(n9328) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2072), .CK(clk), .RN(n9808), .Q(
FPSENCOS_d_ff_Yn[1]), .QN(n9363) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1906), .CK(clk), .RN(n9808),
.Q(FPSENCOS_d_ff3_sh_y_out[1]), .QN(n9163) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2005), .CK(clk), .RN(
n9808), .Q(FPSENCOS_d_ff2_X[1]), .QN(n9119) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2004), .CK(clk), .RN(n9808),
.Q(FPSENCOS_d_ff3_sh_x_out[1]), .QN(n9407) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1807), .CK(clk), .RN(n2873), .Q(FPADDSUB_Data_array_SWR[18]), .QN(n9394) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2049), .CK(clk), .RN(n9779), .Q(
FPSENCOS_d_ff_Zn[9]), .QN(n9312) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2048), .CK(clk), .RN(n9780), .Q(
FPSENCOS_d_ff_Yn[9]), .QN(n9348) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1891), .CK(clk), .RN(
n9780), .Q(FPSENCOS_d_ff2_Y[9]), .QN(n9131) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1890), .CK(clk), .RN(n9780),
.Q(FPSENCOS_d_ff3_sh_y_out[9]), .QN(n9335) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1989), .CK(clk), .RN(
n9780), .Q(FPSENCOS_d_ff2_X[9]), .QN(n9132) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1988), .CK(clk), .RN(n9780),
.Q(FPSENCOS_d_ff3_sh_x_out[9]), .QN(n9336) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n9794),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2061), .CK(clk), .RN(n9777), .Q(
FPSENCOS_d_ff_Zn[5]), .QN(n9309) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2060), .CK(clk), .RN(n9808), .Q(
FPSENCOS_d_ff_Yn[5]), .QN(n9364) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1899), .CK(clk), .RN(
n9808), .Q(FPSENCOS_d_ff2_Y[5]), .QN(n9431) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1898), .CK(clk), .RN(n9809),
.Q(FPSENCOS_d_ff3_sh_y_out[5]), .QN(n9164) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1997), .CK(clk), .RN(
n9777), .Q(FPSENCOS_d_ff2_X[5]), .QN(n9125) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1996), .CK(clk), .RN(n9809),
.Q(FPSENCOS_d_ff3_sh_x_out[5]), .QN(n9408) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1806), .CK(clk), .RN(n9763), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n9797),
.Q(cordic_result[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n9795),
.Q(cordic_result[12]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1799), .CK(clk), .RN(n2871), .Q(FPADDSUB_Data_array_SWR[10]), .QN(n9264) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n9795),
.Q(cordic_result[10]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1797), .CK(clk), .RN(n2875),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n9795),
.Q(cordic_result[14]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n9795),
.Q(cordic_result[11]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n9795),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n9795),
.Q(cordic_result[13]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n9795),
.Q(cordic_result[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n9796),
.Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n9795),
.Q(cordic_result[19]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n9796),
.Q(cordic_result[21]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n9795),
.Q(cordic_result[18]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n9795),
.Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n9796),
.Q(cordic_result[22]) );
DFFRX4TS R_2135 ( .D(n1692), .CK(clk), .RN(n2842), .Q(
FPMULT_FS_Module_state_reg[2]) );
DFFRX4TS R_2134 ( .D(n1695), .CK(clk), .RN(n2842), .Q(
FPMULT_FS_Module_state_reg[3]), .QN(n9204) );
DFFRX4TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1691), .CK(clk), .RN(n9515), .Q(
FPMULT_FSM_selector_A), .QN(n9248) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1687), .CK(clk),
.RN(n9515), .Q(FPMULT_Op_MX[28]), .QN(n9236) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1686), .CK(clk),
.RN(n9515), .Q(FPMULT_Op_MX[27]), .QN(n9223) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1683), .CK(clk),
.RN(n9525), .QN(n9703) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1682), .CK(clk),
.RN(n9525), .QN(n9702) );
DFFRX4TS R_1300 ( .D(n1675), .CK(clk), .RN(n9029), .Q(FPMULT_Op_MX[16]),
.QN(n9699) );
DFFRX4TS R_258 ( .D(n1670), .CK(clk), .RN(n9528), .Q(FPMULT_Op_MX[11]), .QN(
n9643) );
DFFRX4TS R_261 ( .D(n1669), .CK(clk), .RN(n9528), .Q(FPMULT_Op_MX[10]), .QN(
n9689) );
DFFRX4TS R_486 ( .D(n1663), .CK(clk), .RN(n2885), .Q(FPMULT_Op_MX[4]), .QN(
n9711) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1615), .CK(clk), .RN(
n9819), .Q(FPMULT_Add_result[9]), .QN(n9391) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1616), .CK(clk), .RN(
n2796), .Q(FPMULT_Add_result[8]), .QN(n9146) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1617), .CK(clk), .RN(
n2883), .Q(FPMULT_Add_result[7]), .QN(n9203) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1620), .CK(clk), .RN(
n2884), .Q(FPMULT_Add_result[4]), .QN(n9104) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1621), .CK(clk), .RN(
n2884), .Q(FPMULT_Add_result[3]), .QN(n9107) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1622), .CK(clk), .RN(
n9526), .Q(FPMULT_Add_result[2]), .QN(n9105) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1623), .CK(clk), .RN(
n2839), .Q(FPMULT_Add_result[1]), .QN(n9106) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1624), .CK(clk), .RN(
n2883), .QN(n3582) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1656), .CK(clk),
.RN(n9529), .QN(n9712) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1655), .CK(clk),
.RN(n9529), .Q(FPMULT_Op_MY[28]), .QN(n9221) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1654), .CK(clk),
.RN(n9516), .Q(FPMULT_Op_MY[27]), .QN(n9222) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1653), .CK(clk),
.RN(n9515), .Q(FPMULT_Op_MY[26]), .QN(n9215) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1652), .CK(clk),
.RN(n9027), .Q(FPMULT_Op_MY[25]), .QN(n9216) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1650), .CK(clk),
.RN(n2797), .Q(FPMULT_Op_MY[23]), .QN(n9478) );
DFFRX4TS R_270 ( .D(n1638), .CK(clk), .RN(n9532), .Q(FPMULT_Op_MY[11]), .QN(
n9645) );
DFFRX4TS R_1317 ( .D(n1637), .CK(clk), .RN(n9532), .Q(FPMULT_Op_MY[10]),
.QN(n9706) );
DFFRX4TS R_348 ( .D(n1636), .CK(clk), .RN(n9532), .Q(FPMULT_Op_MY[9]), .QN(
n9374) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1566), .CK(clk),
.RN(n9524), .Q(FPMULT_P_Sgf[13]), .QN(n2944) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1557), .CK(clk),
.RN(n9522), .Q(FPMULT_P_Sgf[4]), .QN(n2931) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1556), .CK(clk),
.RN(n9522), .Q(FPMULT_P_Sgf[3]), .QN(n2890) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1555), .CK(clk),
.RN(n9522), .Q(FPMULT_P_Sgf[2]), .QN(n2893) );
DFFRX4TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1550), .CK(clk), .RN(n2885), .Q(
FPMULT_FSM_selector_B[1]) );
DFFRX4TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1549), .CK(clk), .RN(
n2885), .Q(FPMULT_exp_oper_result[0]), .QN(n9211) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1547), .CK(clk), .RN(
n2884), .Q(FPMULT_exp_oper_result[2]), .QN(n3683) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1546), .CK(clk), .RN(
n2863), .Q(FPMULT_exp_oper_result[3]), .QN(n3684) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1535), .CK(
clk), .RN(n2289), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1534), .CK(
clk), .RN(n2289), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1531), .CK(
clk), .RN(n2289), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1530), .CK(
clk), .RN(n2289), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1529), .CK(
clk), .RN(n2289), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1528), .CK(
clk), .RN(n2290), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1527), .CK(
clk), .RN(n2289), .Q(FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1526), .CK(
clk), .RN(n2289), .Q(FPMULT_Sgf_normalized_result[9]) );
DFFRXLTS R_653 ( .D(add_x_246_A_5_), .CK(clk), .RN(n8852), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFRXLTS R_588 ( .D(n1521), .CK(clk), .RN(n2913), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRXLTS R_490 ( .D(add_x_246_A_3_), .CK(clk), .RN(n9028), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFRXLTS R_399 ( .D(n1519), .CK(clk), .RN(n8850), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRXLTS R_400 ( .D(n1518), .CK(clk), .RN(n8851), .Q(
FPMULT_Sgf_normalized_result[1]) );
DFFRX1TS R_401 ( .D(n1517), .CK(clk), .RN(n2278), .Q(
FPMULT_Sgf_normalized_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1515), .CK(clk), .RN(n2279), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1514), .CK(clk), .RN(n2279), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1513), .CK(clk), .RN(n9972), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1512), .CK(clk), .RN(n9972), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1511), .CK(clk), .RN(n9972), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1510), .CK(clk), .RN(n9972), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1509), .CK(clk), .RN(n2797), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1508), .CK(clk), .RN(n2796), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1507), .CK(clk), .RN(n2797), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1506), .CK(clk), .RN(n2797), .Q(mult_result[9]) );
DFFRX1TS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1505), .CK(clk), .RN(n9531), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1503), .CK(clk), .RN(n9821), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1502), .CK(clk), .RN(n9818), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1501), .CK(clk), .RN(n9526), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1500), .CK(clk), .RN(n9531), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1499), .CK(clk), .RN(n9821), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1498), .CK(clk), .RN(n9818), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1497), .CK(clk), .RN(n9526), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1496), .CK(clk), .RN(n9531), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1495), .CK(clk), .RN(n9822), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1494), .CK(clk), .RN(n9822), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1493), .CK(clk), .RN(n9822), .Q(mult_result[22]) );
DFFRX1TS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1492), .CK(clk), .RN(n9822), .Q(mult_result[23]) );
DFFRX1TS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1491), .CK(clk), .RN(n9822), .Q(mult_result[24]) );
DFFRX1TS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1490), .CK(clk), .RN(n9822), .Q(mult_result[25]) );
DFFRX1TS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1489), .CK(clk), .RN(n9822), .Q(mult_result[26]) );
DFFRX1TS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1487), .CK(clk), .RN(n9822), .Q(mult_result[28]) );
DFFRX1TS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1486), .CK(clk), .RN(n9822), .Q(mult_result[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1480), .CK(clk), .RN(
n9769), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]), .QN(n9371) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1479), .CK(clk), .RN(
n9772), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]), .QN(n9370) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1478), .CK(clk), .RN(
n9758), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]), .QN(n9372) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1476), .CK(clk), .RN(
n2871), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]), .QN(n9369) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1459), .CK(clk), .RN(n9757),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1458), .CK(clk), .RN(n9761),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]), .QN(n9199) );
DFFRX2TS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1456), .CK(clk), .RN(
n9761), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1454), .CK(clk), .RN(n9758),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1453), .CK(clk), .RN(n9767),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]), .QN(n9198) );
DFFRX2TS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1451), .CK(clk), .RN(
n9766), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1450), .CK(clk), .RN(
n9763), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX2TS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1446), .CK(clk), .RN(
n9756), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1444), .CK(clk), .RN(n8251),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n2848),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]), .QN(n9197) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1440), .CK(clk), .RN(
n2881), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n9753),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n9753),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]), .QN(n9196) );
DFFRX2TS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1436), .CK(clk), .RN(
n2848), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1435), .CK(clk), .RN(
n9760), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1434), .CK(clk), .RN(n9518),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n2878),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]), .QN(n9195) );
DFFRX2TS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1431), .CK(clk), .RN(
n2847), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1430), .CK(clk), .RN(
n9759), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1429), .CK(clk), .RN(n9768),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1428), .CK(clk), .RN(n2880),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]), .QN(n9194) );
DFFRX2TS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1426), .CK(clk), .RN(
n2870), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1425), .CK(clk), .RN(
n2841), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1424), .CK(clk), .RN(n2862),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRX2TS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1421), .CK(clk), .RN(
n9518), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1420), .CK(clk), .RN(
n9762), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n9094), .CK(clk), .RN(n9764), .Q(overflow_flag_addsubt), .QN(n9471) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1411), .CK(clk), .RN(
n9517), .Q(FPADDSUB_LZD_output_NRM2_EW[1]), .QN(n9214) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n2852), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n2853), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n2872), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n9761), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n9768), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n2926), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]), .QN(n9269) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n2870), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n9770), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n2927), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n2877), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n2869), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n2860), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n2874), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n9754), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRX1TS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n9767), .Q(FPADDSUB_SIGN_FLAG_SHT2), .QN(n9140) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1359), .CK(clk), .RN(
n9764), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRX1TS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n2855), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRX1TS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n9770), .Q(FPADDSUB_OP_FLAG_SHT2), .QN(n9367) );
DFFRX4TS R_1962 ( .D(n1352), .CK(clk), .RN(n2880), .Q(
FPADDSUB_ADD_OVRFLW_NRM2) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1350), .CK(clk), .RN(
n2880), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n9229) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1349), .CK(clk), .RN(
n2841), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]), .QN(n9240) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1347), .CK(clk), .RN(
n9760), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n9301) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1346), .CK(clk), .RN(
n9756), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n9235) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1345), .CK(clk), .RN(
n9756), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n9096) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1344), .CK(clk), .RN(
n2849), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n9093) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(
n9768), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n9237) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1342), .CK(clk), .RN(
n9762), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n9095) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1341), .CK(clk), .RN(
n2869), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n9238) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1340), .CK(clk), .RN(
n2870), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n9226) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1339), .CK(clk), .RN(
n2928), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n9220) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1337), .CK(clk), .RN(
n9772), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n9225) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1332), .CK(clk), .RN(
n9753), .Q(FPADDSUB_LZD_output_NRM2_EW[4]), .QN(n9218) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n2874), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(n2854),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n2855),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]), .QN(n9188) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1324), .CK(clk), .RN(
n2867), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1320), .CK(clk), .RN(
n9763), .Q(FPADDSUB_LZD_output_NRM2_EW[2]), .QN(n9212) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1316), .CK(clk), .RN(
n2852), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n2861), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(n2872),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n9753),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]), .QN(n9189) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n2876), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n9517),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n9762),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]), .QN(n9184) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n9769), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n2849),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n2868),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]), .QN(n9191) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n9753), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(n9760),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n2926),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]), .QN(n9190) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n8252), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n9760), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(n9755),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1272), .CK(clk), .RN(
n2858), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(n9763),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n9754),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]), .QN(n9179) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1266), .CK(clk), .RN(n9767),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n9757),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]), .QN(n9181) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1262), .CK(clk), .RN(n2881),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n9757),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]), .QN(n9177) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n9761),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n9766),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]), .QN(n9180) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1254), .CK(clk), .RN(n2927),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n2849),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]), .QN(n9143) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1246), .CK(clk), .RN(n9753),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1242), .CK(clk), .RN(n2877),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n9756),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]), .QN(n9185) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1238), .CK(clk), .RN(n2855),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n2854),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]), .QN(n9187) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1234), .CK(clk), .RN(n2854),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n2859),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]), .QN(n9142) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1230), .CK(clk), .RN(n9517),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n2849),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]), .QN(n9174) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1226), .CK(clk), .RN(n9762),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n9755),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]), .QN(n9141) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1222), .CK(clk), .RN(n2862),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n2862),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]), .QN(n9192) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1218), .CK(clk), .RN(n2841),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n9768),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]), .QN(n9175) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1214), .CK(clk), .RN(n2849),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n9754),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]), .QN(n9176) );
DFFRX1TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1210), .CK(clk), .RN(n2852),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFSX1TS R_2 ( .D(n9836), .CK(clk), .SN(n6442), .Q(n9746) );
DFFRXLTS R_4 ( .D(n1589), .CK(clk), .RN(n9811), .Q(n9745) );
DFFSX1TS R_8 ( .D(n9835), .CK(clk), .SN(n9799), .Q(n9744) );
DFFSX1TS R_11 ( .D(n9834), .CK(clk), .SN(n9799), .Q(n9743) );
DFFSX1TS R_14 ( .D(n9833), .CK(clk), .SN(n9799), .Q(n9742) );
DFFSX1TS R_17 ( .D(n9828), .CK(clk), .SN(n9523), .Q(n9741) );
DFFSX1TS R_20 ( .D(n9827), .CK(clk), .SN(n9523), .Q(n9740) );
DFFSX1TS R_23 ( .D(n9826), .CK(clk), .SN(n9521), .Q(n9739) );
DFFSX1TS R_26 ( .D(n9832), .CK(clk), .SN(n9799), .Q(n9738) );
DFFSX1TS R_29 ( .D(n9831), .CK(clk), .SN(n9799), .Q(n9737) );
DFFSX1TS R_32 ( .D(n9830), .CK(clk), .SN(n9523), .Q(n9736) );
DFFSX1TS R_35 ( .D(n9829), .CK(clk), .SN(n9523), .Q(n9735) );
DFFRXLTS R_37 ( .D(n1581), .CK(clk), .RN(n9812), .Q(n9734) );
DFFRXLTS R_40 ( .D(n1582), .CK(clk), .RN(n9786), .Q(n9733) );
DFFRXLTS R_43 ( .D(n1584), .CK(clk), .RN(n6442), .Q(n9732) );
DFFRXLTS R_46 ( .D(n1586), .CK(clk), .RN(n9787), .Q(n9731) );
DFFRXLTS R_49 ( .D(n1587), .CK(clk), .RN(n9811), .Q(n9730) );
DFFRXLTS R_52 ( .D(n1588), .CK(clk), .RN(n9811), .Q(n9729) );
DFFRXLTS R_55 ( .D(n1585), .CK(clk), .RN(n9811), .Q(n9728) );
DFFRXLTS R_58 ( .D(n1583), .CK(clk), .RN(n9812), .Q(n9727) );
DFFRXLTS R_83 ( .D(n1573), .CK(clk), .RN(n9520), .Q(n9726) );
DFFRXLTS R_123 ( .D(n1601), .CK(clk), .RN(n2885), .Q(n9725) );
DFFRXLTS R_126 ( .D(n1580), .CK(clk), .RN(n9811), .Q(n9724) );
DFFRXLTS R_129 ( .D(n1578), .CK(clk), .RN(n9811), .Q(n9723) );
DFFRXLTS R_132 ( .D(n1579), .CK(clk), .RN(n9786), .Q(n9722) );
DFFRXLTS R_148 ( .D(n1577), .CK(clk), .RN(n9524), .Q(n9721) );
DFFRXLTS R_185 ( .D(n1600), .CK(clk), .RN(n9817), .Q(n9720) );
DFFRXLTS R_191 ( .D(n1576), .CK(clk), .RN(n2843), .Q(n9719) );
DFFRXLTS R_194 ( .D(n1575), .CK(clk), .RN(n9520), .Q(n9718) );
DFFRXLTS R_198 ( .D(n1602), .CK(clk), .RN(n2863), .Q(n9717) );
DFFRX4TS R_337 ( .D(n1648), .CK(clk), .RN(n9526), .Q(
DP_OP_496J248_122_3540_n1467), .QN(n9273) );
DFFRXLTS R_1189 ( .D(n9700), .CK(clk), .RN(n9530), .QN(n9261) );
DFFRXLTS R_1295 ( .D(n1671), .CK(clk), .RN(n9527), .QN(n9260) );
DFFRXLTS R_1201 ( .D(n6251), .CK(clk), .RN(n2885), .QN(n9144) );
DFFRXLTS R_1266 ( .D(n1673), .CK(clk), .RN(n9527), .QN(n9379) );
DFFRXLTS R_2446 ( .D(n1668), .CK(clk), .RN(n9527), .QN(n9376) );
DFFRXLTS R_421 ( .D(n1574), .CK(clk), .RN(n9520), .Q(n9684) );
DFFRXLTS R_676 ( .D(n9683), .CK(clk), .RN(n9527), .QN(n9378) );
DFFRX4TS R_477 ( .D(n9682), .CK(clk), .RN(n9530), .Q(
DP_OP_496J248_122_3540_n1464), .QN(n9383) );
DFFRXLTS R_1677 ( .D(n1664), .CK(clk), .RN(n9821), .QN(n9377) );
DFFRXLTS R_685 ( .D(n1571), .CK(clk), .RN(n9520), .Q(n9681) );
DFFRXLTS R_800 ( .D(n1572), .CK(clk), .RN(n9520), .Q(n9680) );
DFFRXLTS R_830 ( .D(n1603), .CK(clk), .RN(n2883), .Q(n9679) );
DFFRXLTS R_876 ( .D(n1570), .CK(clk), .RN(n9520), .Q(n9678) );
DFFRXLTS R_974 ( .D(n1604), .CK(clk), .RN(n2886), .Q(n9677) );
DFFRXLTS R_1016 ( .D(n1569), .CK(clk), .RN(n9520), .Q(n9676) );
DFFSX1TS R_1021 ( .D(n9903), .CK(clk), .SN(n2881), .Q(n9675) );
DFFSX1TS R_1039 ( .D(n9900), .CK(clk), .SN(n2877), .Q(n9674) );
DFFSX1TS R_1062 ( .D(n9960), .CK(clk), .SN(n2876), .Q(n9673) );
DFFSX1TS R_1077 ( .D(n9873), .CK(clk), .SN(n2876), .Q(n9672) );
DFFSX1TS R_1081 ( .D(n9897), .CK(clk), .SN(n2849), .Q(n9671) );
DFFSX1TS R_1085 ( .D(n9891), .CK(clk), .SN(n2873), .Q(n9670) );
DFFSX1TS R_1089 ( .D(n9869), .CK(clk), .SN(n9757), .Q(n9669) );
DFFSX1TS R_1093 ( .D(n9882), .CK(clk), .SN(n2869), .Q(n9668) );
DFFSX1TS R_1097 ( .D(n9888), .CK(clk), .SN(n2860), .Q(n9667) );
DFFSX1TS R_1101 ( .D(n9879), .CK(clk), .SN(n9765), .Q(n9666) );
DFFSX1TS R_1109 ( .D(n9884), .CK(clk), .SN(n2869), .Q(n9665) );
DFFSX1TS R_1121 ( .D(n9953), .CK(clk), .SN(n2862), .Q(n9664) );
DFFSX1TS R_1128 ( .D(n9895), .CK(clk), .SN(n2877), .Q(n9663) );
DFFSX1TS R_1138 ( .D(n9875), .CK(clk), .SN(n2877), .Q(n9662) );
DFFSX1TS R_1142 ( .D(n9907), .CK(clk), .SN(n2867), .Q(n9661) );
DFFSX1TS R_1146 ( .D(n9949), .CK(clk), .SN(n9758), .Q(n9660) );
DFFSX1TS R_1150 ( .D(n9893), .CK(clk), .SN(n2874), .Q(n9659) );
DFFSX1TS R_1159 ( .D(n9877), .CK(clk), .SN(n2858), .Q(n9658) );
DFFSX1TS R_1162 ( .D(n9886), .CK(clk), .SN(n2927), .Q(n9657) );
DFFSX1TS R_1165 ( .D(n9867), .CK(clk), .SN(n9755), .Q(n9656) );
DFFSX1TS R_1168 ( .D(n9871), .CK(clk), .SN(n9764), .Q(n9655) );
DFFSX1TS R_1170 ( .D(n9654), .CK(clk), .SN(n9810), .Q(n9966) );
DFFSX2TS R_1172 ( .D(n9652), .CK(clk), .SN(n9799), .Q(n9962) );
DFFSX2TS R_1173 ( .D(n9651), .CK(clk), .SN(n9810), .Q(n9963) );
DFFSX2TS R_1174 ( .D(n9650), .CK(clk), .SN(n9810), .Q(n9964) );
DFFSX2TS R_1175 ( .D(n9649), .CK(clk), .SN(n9815), .Q(n9965) );
DFFSX2TS R_1187 ( .D(n9648), .CK(clk), .SN(n9815), .Q(n9961) );
DFFSX2TS R_1199 ( .D(n2325), .CK(clk), .SN(n2883), .Q(n9646) );
DFFRXLTS R_2384 ( .D(n1678), .CK(clk), .RN(n9817), .QN(n9375) );
DFFRX4TS R_1228 ( .D(n1681), .CK(clk), .RN(n9817), .Q(
DP_OP_496J248_122_3540_n1504), .QN(n9382) );
DFFRX4TS R_1233 ( .D(n1649), .CK(clk), .RN(n2796), .Q(
DP_OP_496J248_122_3540_n1468), .QN(n9262) );
DFFRX4TS R_1273 ( .D(n1643), .CK(clk), .RN(n9529), .Q(
DP_OP_496J248_122_3540_n1462), .QN(n9381) );
DFFRXLTS R_2289 ( .D(n9639), .CK(clk), .RN(n9817), .QN(n9259) );
DFFSX2TS R_1342 ( .D(n9969), .CK(clk), .SN(n8851), .Q(n9637) );
DFFSX2TS R_1343 ( .D(n9843), .CK(clk), .SN(n9028), .Q(n9636) );
DFFSX1TS R_1373 ( .D(n9874), .CK(clk), .SN(n2876), .Q(n9635) );
DFFSX1TS R_1376 ( .D(n9913), .CK(clk), .SN(n2888), .Q(n9634) );
DFFSX1TS R_1379 ( .D(n9862), .CK(clk), .SN(n2876), .Q(n9633) );
DFFSX1TS R_1385 ( .D(n9915), .CK(clk), .SN(n2877), .Q(n9631) );
DFFSX1TS R_1388 ( .D(n9912), .CK(clk), .SN(n2878), .Q(n9630) );
DFFSX1TS R_1391 ( .D(n9922), .CK(clk), .SN(n9755), .Q(n9629) );
DFFSX1TS R_1394 ( .D(n9896), .CK(clk), .SN(n2867), .Q(n9628) );
DFFSX1TS R_1397 ( .D(n9918), .CK(clk), .SN(n9757), .Q(n9627) );
DFFSX1TS R_1400 ( .D(n9887), .CK(clk), .SN(n2928), .Q(n9626) );
DFFSX1TS R_1403 ( .D(n9865), .CK(clk), .SN(n2858), .Q(n9625) );
DFFSX2TS R_1406 ( .D(n9851), .CK(clk), .SN(n2852), .Q(n9624) );
DFFSX1TS R_1409 ( .D(n9914), .CK(clk), .SN(n2849), .Q(n9623) );
DFFSX1TS R_1412 ( .D(n9909), .CK(clk), .SN(n9756), .Q(n9622) );
DFFSX1TS R_1415 ( .D(n9870), .CK(clk), .SN(n9754), .Q(n9621) );
DFFSX1TS R_1418 ( .D(n9880), .CK(clk), .SN(n9765), .Q(n9620) );
DFFSX1TS R_1421 ( .D(n9908), .CK(clk), .SN(n9766), .Q(n9619) );
DFFSX1TS R_1424 ( .D(n9916), .CK(clk), .SN(n2881), .Q(n9618) );
DFFSX1TS R_1433 ( .D(n9910), .CK(clk), .SN(n9760), .Q(n9615) );
DFFSX1TS R_1436 ( .D(n9883), .CK(clk), .SN(n2871), .Q(n9614) );
DFFSX1TS R_1439 ( .D(n9911), .CK(clk), .SN(n2848), .Q(n9613) );
DFFSX1TS R_1442 ( .D(n9917), .CK(clk), .SN(n9764), .Q(n9612) );
DFFSX2TS R_1445 ( .D(n9860), .CK(clk), .SN(n9772), .Q(n9611) );
DFFSX1TS R_1448 ( .D(n9878), .CK(clk), .SN(n2858), .Q(n9610) );
DFFSX1TS R_1451 ( .D(n9864), .CK(clk), .SN(n2873), .Q(n9609) );
DFFSX2TS R_1454 ( .D(n9854), .CK(clk), .SN(n9517), .Q(n9608) );
DFFSX2TS R_1460 ( .D(n9852), .CK(clk), .SN(n2852), .Q(n9606) );
DFFSX1TS R_1463 ( .D(n9890), .CK(clk), .SN(n2873), .Q(n9605) );
DFFSX2TS R_1466 ( .D(n9856), .CK(clk), .SN(n9518), .Q(n9604) );
DFFSX1TS R_1469 ( .D(n9898), .CK(clk), .SN(n2870), .Q(n9603) );
DFFSX1TS R_1472 ( .D(n9863), .CK(clk), .SN(n9768), .Q(n9602) );
DFFSX1TS R_1475 ( .D(n9889), .CK(clk), .SN(n2860), .Q(n9601) );
DFFSX1TS R_1478 ( .D(n9868), .CK(clk), .SN(n2858), .Q(n9600) );
DFFSX1TS R_1484 ( .D(n9923), .CK(clk), .SN(n9754), .Q(n9598) );
DFFSX1TS R_1490 ( .D(n9881), .CK(clk), .SN(n2870), .Q(n9596) );
DFFSX1TS R_1493 ( .D(n9872), .CK(clk), .SN(n2877), .Q(n9595) );
DFFSX1TS R_1496 ( .D(n9885), .CK(clk), .SN(n2927), .Q(n9594) );
DFFSX1TS R_1499 ( .D(n9894), .CK(clk), .SN(n2868), .Q(n9593) );
DFFSX2TS R_1502 ( .D(n9861), .CK(clk), .SN(n2854), .Q(n9592) );
DFFSX1TS R_1505 ( .D(n9901), .CK(clk), .SN(n2876), .Q(n9591) );
DFFSX1TS R_1508 ( .D(n9892), .CK(clk), .SN(n2874), .Q(n9590) );
DFFSX1TS R_1511 ( .D(n9876), .CK(clk), .SN(n2858), .Q(n9589) );
DFFSX2TS R_1517 ( .D(n9858), .CK(clk), .SN(n9759), .Q(n9587) );
DFFSX1TS R_1520 ( .D(n9899), .CK(clk), .SN(n2889), .Q(n9586) );
DFFSX2TS R_1530 ( .D(n9925), .CK(clk), .SN(n2854), .Q(n9583) );
DFFSX2TS R_1537 ( .D(n9950), .CK(clk), .SN(n2862), .Q(n9582) );
DFFSX2TS R_1540 ( .D(n9924), .CK(clk), .SN(n2855), .Q(n9581) );
DFFSX2TS R_1543 ( .D(n9926), .CK(clk), .SN(n2854), .Q(n9580) );
DFFSX2TS R_1546 ( .D(n9927), .CK(clk), .SN(n2847), .Q(n9579) );
DFFSX2TS R_1549 ( .D(n9928), .CK(clk), .SN(n9771), .Q(n9578) );
DFFSX2TS R_1552 ( .D(n9954), .CK(clk), .SN(n2862), .Q(n9577) );
DFFSX2TS R_1555 ( .D(n9955), .CK(clk), .SN(n2867), .Q(n9576) );
DFFSX2TS R_1564 ( .D(n9957), .CK(clk), .SN(n2888), .Q(n9575) );
DFFRXLTS R_1631 ( .D(n9952), .CK(clk), .RN(n2862), .Q(n9574) );
DFFRXLTS R_1708 ( .D(n9951), .CK(clk), .RN(n2862), .Q(n9572) );
DFFSX1TS R_1728 ( .D(n9930), .CK(clk), .SN(n2860), .Q(n9567) );
DFFSX2TS R_1730 ( .D(n2694), .CK(clk), .SN(n2860), .Q(n9566) );
DFFSX1TS R_1746 ( .D(n9929), .CK(clk), .SN(n9765), .Q(n9565) );
DFFSX2TS R_1748 ( .D(n7274), .CK(clk), .SN(n9765), .Q(n9564) );
DFFRX2TS R_1876 ( .D(FPADDSUB_intDX_EWSW[30]), .CK(clk), .RN(n2861), .Q(
n9561) );
DFFRX1TS R_1889 ( .D(n9902), .CK(clk), .RN(n2881), .Q(n9560) );
DFFRX2TS R_1900 ( .D(FPADDSUB_intDX_EWSW[29]), .CK(clk), .RN(n9768), .Q(
n9558) );
DFFRX1TS R_2098 ( .D(FPADDSUB_left_right_SHT2), .CK(clk), .RN(n2880), .Q(
n9543) );
DFFRX1TS R_2099 ( .D(n9112), .CK(clk), .RN(n2881), .Q(n9542) );
DFFRX1TS R_2100 ( .D(n9466), .CK(clk), .RN(n2879), .Q(n9541) );
DFFRX4TS R_2136 ( .D(n9540), .CK(clk), .RN(n2842), .Q(n9838), .QN(n9227) );
DFFSX2TS R_2137 ( .D(n9539), .CK(clk), .SN(n2843), .Q(n9839) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n9766),
.Q(FPADDSUB_DMP_SFG[23]), .QN(n9508) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n9764),
.Q(FPADDSUB_DMP_SFG[24]), .QN(n9507) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n2841),
.Q(FPADDSUB_DMP_SFG[25]), .QN(n9506) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n2928),
.Q(FPADDSUB_DMP_SFG[27]), .QN(n9504) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n9764),
.Q(FPADDSUB_DMP_SFG[28]), .QN(n9503) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n9760),
.Q(FPADDSUB_DMP_SFG[29]), .QN(n9502) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n9756),
.Q(FPADDSUB_DMP_SFG[30]), .QN(n9501) );
DFFRX1TS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n2866),
.Q(FPADDSUB_OP_FLAG_EXP), .QN(n9470) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1477), .CK(clk), .RN(
n2851), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]), .QN(n9368) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n9774), .Q(NaN_flag)
);
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1483), .CK(clk), .RN(n9823), .Q(mult_result[31]), .QN(n9373) );
DFFRXLTS R_2328 ( .D(n1358), .CK(clk), .RN(n2876), .Q(n9537) );
DFFSX2TS R_1721 ( .D(n9904), .CK(clk), .SN(n2867), .Q(n9570) );
DFFRXLTS R_1722 ( .D(n1364), .CK(clk), .RN(n2849), .Q(n9569) );
DFFSX1TS R_2330 ( .D(n9906), .CK(clk), .SN(n2879), .Q(n9536) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1625), .CK(
clk), .RN(n2839), .Q(FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1448), .CK(clk), .RN(n2871),
.QN(n9206) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1449), .CK(clk), .RN(n2875),
.QN(n9469) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n9808), .Q(
FPSENCOS_d_ff_Xn[1]), .QN(n9293) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n9803), .Q(
FPSENCOS_d_ff_Xn[3]), .QN(n9292) );
DFFRXLTS R_1270 ( .D(n1643), .CK(clk), .RN(n2273), .QN(n9708) );
DFFRXLTS R_290 ( .D(DP_OP_497J248_123_1725_n781), .CK(clk), .RN(n9530), .QN(
n9707) );
DFFRXLTS R_313 ( .D(n1645), .CK(clk), .RN(n9530), .QN(n9705) );
DFFRXLTS R_278 ( .D(n1646), .CK(clk), .RN(n9530), .QN(n9704) );
DFFRXLTS R_1222 ( .D(n1681), .CK(clk), .RN(n9817), .QN(n9642) );
DFFRXLTS R_410 ( .D(n1668), .CK(clk), .RN(n9528), .QN(n9690) );
DFFRXLTS R_288 ( .D(n6251), .CK(clk), .RN(n2864), .QN(n9709) );
DFFRXLTS R_315 ( .D(n1671), .CK(clk), .RN(n9527), .QN(n9698) );
DFFRXLTS R_504 ( .D(n1664), .CK(clk), .RN(n9527), .QN(n9715) );
DFFRXLTS R_294 ( .D(n1662), .CK(clk), .RN(n2864), .QN(n9710) );
DFFRXLTS R_1220 ( .D(n1678), .CK(clk), .RN(n9525), .QN(n9691) );
DFFRXLTS R_2142 ( .D(n1677), .CK(clk), .RN(n9525), .Q(FPMULT_Op_MX[18]),
.QN(n9716) );
DFFRXLTS R_326 ( .D(n1673), .CK(clk), .RN(n9528), .QN(n9697) );
DFFRXLTS R_1188 ( .D(n1634), .CK(clk), .RN(n9818), .Q(FPMULT_Op_MY[7]), .QN(
n9384) );
DFFRXLTS R_1209 ( .D(n1635), .CK(clk), .RN(n9532), .Q(FPMULT_Op_MY[8]), .QN(
n9380) );
DFFSX2TS R_2060 ( .D(FPMULT_Adder_M_result_A_adder[18]), .CK(clk), .SN(n9818), .Q(n9550) );
DFFRXLTS R_2061 ( .D(n1606), .CK(clk), .RN(n9819), .Q(n9549) );
DFFRXLTS R_279 ( .D(n6282), .CK(clk), .RN(n9525), .Q(n9749), .QN(n9385) );
DFFSX2TS R_1927_RW_3 ( .D(n9751), .CK(clk), .SN(n9521), .Q(n9553) );
DFFSX2TS R_1891 ( .D(n9850), .CK(clk), .SN(n9759), .Q(n9559) );
DFFSX2TS R_1912 ( .D(n9849), .CK(clk), .SN(n9517), .Q(n9557) );
DFFSX1TS R_1924 ( .D(n9844), .CK(clk), .SN(n2889), .Q(n9555) );
DFFSX1TS R_2300 ( .D(n9845), .CK(clk), .SN(n2887), .Q(n9538) );
DFFSX1TS R_2336 ( .D(n9846), .CK(clk), .SN(n2887), .Q(n9535) );
DFFSX2TS R_2451 ( .D(n9848), .CK(clk), .SN(n9759), .Q(n9533) );
DFFSX1TS R_1874 ( .D(n9842), .CK(clk), .SN(n2912), .Q(n9562) );
DFFRXLTS R_1651 ( .D(n9640), .CK(clk), .RN(n9526), .QN(n9459) );
DFFRXLTS R_1210 ( .D(n1647), .CK(clk), .RN(n9530), .Q(n2941), .QN(n9272) );
DFFRX2TS R_2445 ( .D(n1680), .CK(clk), .RN(n9530), .QN(n9467) );
DFFRXLTS R_1206 ( .D(n9686), .CK(clk), .RN(n9531), .QN(n9460) );
DFFRXLTS R_416 ( .D(n9685), .CK(clk), .RN(n9530), .Q(n2936), .QN(n9201) );
DFFSX2TS R_2096 ( .D(n9866), .CK(clk), .SN(n2879), .Q(n9545) );
DFFSX2TS R_2095 ( .D(n9905), .CK(clk), .SN(n2880), .Q(n9546) );
DFFRXLTS R_1261 ( .D(n9696), .CK(clk), .RN(n9525), .QN(n9454) );
DFFRXLTS R_464 ( .D(n9692), .CK(clk), .RN(n9527), .QN(n9455) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n9798), .Q(
dataB[31]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1538), .CK(
clk), .RN(n2839), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n9797), .Q(
dataA[25]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n9799), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n9798), .Q(
dataB[30]) );
DFFRXLTS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n9799), .Q(
dataB[24]), .QN(n2934) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1858), .CK(clk), .RN(
n9788), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n9247) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1956), .CK(clk), .RN(
n6441), .Q(FPSENCOS_d_ff2_X[28]), .QN(n9102) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1658), .CK(clk),
.RN(n2864), .Q(FPMULT_Op_MX[31]), .QN(n9480) );
DFFSX2TS R_1526 ( .D(n9840), .CK(clk), .SN(n2839), .Q(n9584) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2136), .CK(clk), .RN(n9793),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n9387) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2082), .CK(clk), .RN(n9793),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n9103) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2138), .CK(clk), .RN(n9791),
.Q(FPSENCOS_cont_var_out[1]), .QN(n9464) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1524), .CK(
clk), .RN(n2912), .Q(FPMULT_Sgf_normalized_result[7]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n9813), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .QN(n9239) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n9811), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .QN(n9265) );
CMPR32X2TS intadd_733_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n9242), .C(
intadd_733_CI), .CO(intadd_733_n3), .S(intadd_733_SUM_0_) );
CMPR32X2TS intadd_733_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n3639), .C(
intadd_733_n3), .CO(intadd_733_n2), .S(intadd_733_SUM_1_) );
CMPR32X2TS intadd_733_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n9274), .C(
intadd_733_n2), .CO(intadd_733_n1), .S(intadd_733_SUM_2_) );
CMPR32X2TS intadd_734_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n9242), .C(
intadd_734_CI), .CO(intadd_734_n3), .S(intadd_734_SUM_0_) );
CMPR32X2TS intadd_734_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n3639), .C(
intadd_734_n3), .CO(intadd_734_n2), .S(intadd_734_SUM_1_) );
DFFRX1TS add_x_246_R_654 ( .D(n9085), .CK(clk), .RN(n2864), .Q(add_x_246_n19) );
DFFSX4TS add_x_246_R_1961 ( .D(add_x_246_n6), .CK(clk), .SN(n9529), .Q(n9091) );
DFFSX4TS add_x_246_R_1960 ( .D(FPMULT_Sgf_normalized_result[19]), .CK(clk),
.SN(n9529), .Q(n9090) );
DFFRXLTS add_x_246_R_655 ( .D(n9086), .CK(clk), .RN(n2886), .Q(
FPMULT_Adder_M_result_A_adder[5]) );
DFFRXLTS add_x_246_R_589 ( .D(n9083), .CK(clk), .RN(n2884), .Q(add_x_246_n21) );
DFFRXLTS add_x_246_R_591 ( .D(n1521), .CK(clk), .RN(n2839), .Q(
add_x_246_A_4_) );
DFFRXLTS add_x_246_R_492 ( .D(n9084), .CK(clk), .RN(n2885), .Q(
FPMULT_Adder_M_result_A_adder[3]) );
DFFRXLTS add_x_246_R_403 ( .D(n1519), .CK(clk), .RN(n2279), .Q(
add_x_246_A_2_) );
DFFRXLTS add_x_246_R_346 ( .D(FPMULT_Sgf_normalized_result[23]), .CK(clk),
.RN(n9529), .Q(n9082) );
DFFSX2TS DP_OP_234J248_129_4955_R_1821 ( .D(n2844), .CK(clk), .SN(n2883),
.Q(n9081) );
DFFSX1TS DP_OP_234J248_129_4955_R_1820 ( .D(DP_OP_234J248_129_4955_n1), .CK(
clk), .SN(n2886), .Q(n9080) );
DFFSX2TS add_x_69_R_798 ( .D(n2628), .CK(clk), .SN(n9075), .Q(n9048) );
DFFRXLTS add_x_69_R_2101_RW_1 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[9]), .CK(
clk), .RN(n9079), .Q(n9065) );
DFFRXLTS add_x_69_R_2164 ( .D(n2628), .CK(clk), .RN(n9076), .Q(n9069) );
DFFSX2TS add_x_69_R_2197 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[9]), .CK(clk),
.SN(n9078), .Q(n9070) );
DFFSX2TS add_x_69_R_2198 ( .D(n2244), .CK(clk), .SN(n9079), .Q(n9071) );
DFFSX1TS add_x_69_R_2010 ( .D(add_x_69_n294), .CK(clk), .SN(n9079), .Q(n9058) );
DFFSX2TS add_x_69_R_2009 ( .D(add_x_69_n302), .CK(clk), .SN(n9079), .Q(n9057) );
DFFSX1TS add_x_69_R_2011 ( .D(add_x_69_n295), .CK(clk), .SN(n9079), .Q(n9059) );
DFFSX1TS add_x_69_R_2286 ( .D(add_x_69_n29), .CK(clk), .SN(n9524), .Q(n9073)
);
DFFRXLTS add_x_69_R_2127_RW_2 ( .D(add_x_69_n30), .CK(clk), .RN(n9079), .Q(
n9068) );
DFFSX1TS add_x_69_R_2285 ( .D(add_x_69_n298), .CK(clk), .SN(n9524), .Q(n9072) );
DFFSX2TS add_x_69_R_2126 ( .D(add_x_69_n301), .CK(clk), .SN(n9079), .Q(n9067) );
DFFSX2TS add_x_69_R_2092 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .CK(
clk), .SN(n9074), .Q(n9064) );
DFFSX2TS add_x_69_R_1921 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[22]), .CK(
clk), .SN(n9074), .Q(n9056) );
DFFSX2TS add_x_69_R_2076_RW_1 ( .D(add_x_69_n285), .CK(clk), .SN(n9075), .Q(
n9061) );
DFFSX2TS add_x_69_R_2077_RW_1 ( .D(add_x_69_n291), .CK(clk), .SN(n9075), .Q(
n9062) );
DFFRX1TS add_x_69_R_2078_RW_1 ( .D(add_x_69_n286), .CK(clk), .RN(n9076), .Q(
n9063) );
DFFSX1TS add_x_69_R_1726 ( .D(add_x_69_n28), .CK(clk), .SN(n9078), .Q(n9053)
);
DFFSX1TS add_x_69_R_1674 ( .D(add_x_69_n289), .CK(clk), .SN(n9077), .Q(n9052) );
DFFSX1TS add_x_69_R_1673 ( .D(add_x_69_n328), .CK(clk), .SN(n9077), .Q(n9051) );
DFFSX1TS add_x_69_R_1041_RW_0 ( .D(add_x_69_n27), .CK(clk), .SN(n9075), .Q(
n9049) );
DFFRXLTS add_x_69_R_371_RW_1 ( .D(add_x_69_n104), .CK(clk), .RN(n9076), .Q(
n9046) );
DFFRXLTS add_x_69_R_393 ( .D(add_x_69_n104), .CK(clk), .RN(n9076), .Q(n9047)
);
DFFSX1TS add_x_69_R_81 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .CK(clk),
.SN(n8974), .Q(n9045) );
DFFSX1TS add_x_69_R_77 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[15]), .CK(clk),
.SN(n6420), .Q(n9044) );
DFFSX1TS add_x_69_R_67 ( .D(add_x_69_n113), .CK(clk), .SN(n6420), .Q(n9043)
);
DFFSX1TS add_x_69_R_63 ( .D(add_x_69_n95), .CK(clk), .SN(n6420), .Q(n9042)
);
DFFRX4TS DP_OP_496J248_122_3540_R_2447 ( .D(n9025), .CK(clk), .RN(n2276),
.Q(n8993), .QN(n9033) );
DFFRX4TS DP_OP_496J248_122_3540_R_2448 ( .D(n1680), .CK(clk), .RN(n2276),
.Q(DP_OP_496J248_122_3540_n1503) );
DFFRX4TS DP_OP_496J248_122_3540_R_2449 ( .D(n1668), .CK(clk), .RN(n2276),
.Q(DP_OP_496J248_122_3540_n1516) );
DFFSX1TS DP_OP_496J248_122_3540_R_2417 ( .D(n9017), .CK(clk), .SN(n9029),
.Q(DP_OP_496J248_122_3540_n1202) );
DFFSX4TS DP_OP_496J248_122_3540_R_2422 ( .D(n9010), .CK(clk), .SN(n9029),
.Q(n8984) );
DFFSX4TS DP_OP_496J248_122_3540_R_2421 ( .D(n8989), .CK(clk), .SN(n9029),
.Q(n8983) );
DFFSX4TS DP_OP_496J248_122_3540_R_2398 ( .D(n9021), .CK(clk), .SN(n8852),
.Q(DP_OP_496J248_122_3540_n1064) );
DFFSX4TS DP_OP_496J248_122_3540_R_2393 ( .D(n9020), .CK(clk), .SN(n2913),
.Q(DP_OP_496J248_122_3540_n1148) );
DFFRX4TS DP_OP_496J248_122_3540_R_2334 ( .D(n9019), .CK(clk), .RN(n9027),
.QN(n9037) );
DFFRX4TS DP_OP_496J248_122_3540_R_2293 ( .D(DP_OP_498J248_124_1725_n796),
.CK(clk), .RN(n2275), .Q(DP_OP_496J248_122_3540_n1515) );
DFFRX4TS DP_OP_496J248_122_3540_R_2292 ( .D(n9639), .CK(clk), .RN(n2275),
.Q(DP_OP_496J248_122_3540_n1502) );
DFFRX4TS DP_OP_496J248_122_3540_R_2291 ( .D(n9018), .CK(clk), .RN(n2276),
.Q(n8990), .QN(n9039) );
DFFRXLTS DP_OP_496J248_122_3540_R_2125_RW_2 ( .D(DP_OP_496J248_122_3540_n36),
.CK(clk), .RN(n9519), .Q(n9016) );
DFFRXLTS DP_OP_496J248_122_3540_R_2124_RW_2 ( .D(DP_OP_496J248_122_3540_n35),
.CK(clk), .RN(n9519), .Q(n9015) );
DFFSX1TS DP_OP_496J248_122_3540_R_1818_RW_1 ( .D(DP_OP_496J248_122_3540_n39),
.CK(clk), .SN(n9519), .Q(n9011) );
DFFSX1TS DP_OP_496J248_122_3540_R_1579_RW_2 ( .D(1'b0), .CK(clk), .SN(n9811),
.Q(n9007) );
DFFSX1TS DP_OP_496J248_122_3540_R_1887 ( .D(n9038), .CK(clk), .SN(n9522),
.Q(n9014) );
DFFSX1TS DP_OP_496J248_122_3540_R_1886 ( .D(DP_OP_496J248_122_3540_n35),
.CK(clk), .SN(n9522), .Q(n9013) );
DFFSX1TS DP_OP_496J248_122_3540_R_1819 ( .D(DP_OP_496J248_122_3540_n4), .CK(
clk), .SN(n9811), .Q(n9012) );
DFFSX1TS DP_OP_496J248_122_3540_R_1703 ( .D(n6364), .CK(clk), .SN(n9522),
.Q(n9009) );
DFFSX4TS DP_OP_496J248_122_3540_R_1653 ( .D(n9008), .CK(clk), .SN(n9027),
.Q(DP_OP_496J248_122_3540_n1098), .QN(n9040) );
DFFRX4TS DP_OP_496J248_122_3540_R_1252 ( .D(n1678), .CK(clk), .RN(n9030),
.Q(DP_OP_496J248_122_3540_n1501), .QN(n2645) );
DFFRX4TS DP_OP_496J248_122_3540_R_1251 ( .D(n1666), .CK(clk), .RN(n9030),
.Q(DP_OP_496J248_122_3540_n1514), .QN(n2637) );
DFFRX1TS DP_OP_496J248_122_3540_R_1250 ( .D(n9006), .CK(clk), .RN(n9030),
.Q(DP_OP_496J248_122_3540_n451), .QN(n3631) );
DFFSX4TS DP_OP_496J248_122_3540_R_1240 ( .D(n9004), .CK(clk), .SN(n8850),
.Q(DP_OP_496J248_122_3540_n1117) );
DFFRX1TS DP_OP_496J248_122_3540_R_1212 ( .D(n9001), .CK(clk), .RN(n9027),
.Q(DP_OP_496J248_122_3540_n827) );
DFFRX4TS DP_OP_496J248_122_3540_R_2426 ( .D(n1635), .CK(clk), .RN(n9027),
.Q(DP_OP_496J248_122_3540_n1477) );
DFFRX4TS DP_OP_496J248_122_3540_R_1193 ( .D(n9700), .CK(clk), .RN(n9027),
.Q(DP_OP_496J248_122_3540_n778) );
DFFRX4TS DP_OP_496J248_122_3540_R_1192 ( .D(n1634), .CK(clk), .RN(n9027),
.Q(DP_OP_496J248_122_3540_n1476) );
DFFSX4TS DP_OP_496J248_122_3540_R_1224 ( .D(n8997), .CK(clk), .SN(n9029),
.QN(n9034) );
DFFSX4TS DP_OP_496J248_122_3540_R_511 ( .D(n8837), .CK(clk), .SN(n9027), .Q(
n8987) );
DFFRX4TS DP_OP_496J248_122_3540_R_506 ( .D(n8995), .CK(clk), .RN(n9030), .Q(
n8986), .QN(n9041) );
DFFRX4TS DP_OP_496J248_122_3540_R_507 ( .D(n1664), .CK(clk), .RN(n9030), .Q(
DP_OP_496J248_122_3540_n1512) );
DFFRX4TS DP_OP_496J248_122_3540_R_509 ( .D(n9696), .CK(clk), .RN(n9030), .Q(
DP_OP_496J248_122_3540_n1499) );
DFFRX4TS DP_OP_496J248_122_3540_R_500 ( .D(n1665), .CK(clk), .RN(n2276), .Q(
DP_OP_496J248_122_3540_n1513) );
DFFRX4TS DP_OP_496J248_122_3540_R_499 ( .D(n1677), .CK(clk), .RN(n2275), .Q(
DP_OP_496J248_122_3540_n1500) );
DFFSX4TS DP_OP_496J248_122_3540_R_1225 ( .D(n8988), .CK(clk), .SN(n9029),
.Q(DP_OP_496J248_122_3540_n1207) );
DFFRX2TS DP_OP_496J248_122_3540_R_320 ( .D(n9692), .CK(clk), .RN(n9030), .Q(
DP_OP_496J248_122_3540_n1507) );
DFFSX4TS DP_OP_496J248_122_3540_R_406 ( .D(n8985), .CK(clk), .SN(n9525), .Q(
DP_OP_496J248_122_3540_n1122) );
DFFRX4TS DP_OP_496J248_122_3540_R_306 ( .D(n6269), .CK(clk), .RN(n9528), .Q(
DP_OP_496J248_122_3540_n1458) );
DFFRX4TS DP_OP_496J248_122_3540_R_307 ( .D(n1627), .CK(clk), .RN(n9029), .Q(
DP_OP_496J248_122_3540_n1469) );
DFFRX4TS add_x_219_R_2146 ( .D(n2684), .CK(clk), .RN(n9524), .Q(n8980) );
DFFRX1TS DP_OP_499J248_125_1651_R_2131_RW_2 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .CK(clk),
.RN(n8975), .Q(n8972) );
DFFSX1TS DP_OP_499J248_125_1651_R_1337 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .CK(clk),
.SN(n9074), .Q(n8942) );
DFFSX1TS DP_OP_499J248_125_1651_R_1981 ( .D(DP_OP_499J248_125_1651_n170),
.CK(clk), .SN(n8974), .Q(n8961) );
DFFSX2TS DP_OP_499J248_125_1651_R_1982 ( .D(DP_OP_499J248_125_1651_n105),
.CK(clk), .SN(n8974), .Q(n8962) );
DFFRX1TS DP_OP_499J248_125_1651_R_1616_RW_3 ( .D(DP_OP_499J248_125_1651_n267), .CK(clk), .RN(n8975), .Q(n8948) );
DFFRXLTS DP_OP_499J248_125_1651_R_1617_RW_1 ( .D(DP_OP_499J248_125_1651_n291), .CK(clk), .RN(n8975), .Q(n8949) );
DFFRXLTS DP_OP_499J248_125_1651_R_995_RW_3 ( .D(n3678), .CK(clk), .RN(n8975),
.Q(n8935) );
DFFRXLTS DP_OP_499J248_125_1651_R_998_RW_2 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .CK(clk),
.RN(n8975), .Q(n8936) );
DFFSX1TS DP_OP_499J248_125_1651_R_2017_RW_1 ( .D(DP_OP_499J248_125_1651_n293), .CK(clk), .SN(n8976), .Q(n8964) );
DFFSX1TS DP_OP_499J248_125_1651_R_1334_RW_2 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .CK(clk),
.SN(n8975), .Q(n8940) );
DFFSX1TS DP_OP_499J248_125_1651_R_1365_RW_1 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .CK(clk),
.SN(n8976), .Q(n8945) );
DFFSX1TS DP_OP_499J248_125_1651_R_1350_RW_1 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .CK(clk),
.SN(n8976), .Q(n8943) );
DFFSX2TS DP_OP_499J248_125_1651_R_1336_RW_1 ( .D(DP_OP_499J248_125_1651_n295), .CK(clk), .SN(n8976), .Q(n8941) );
DFFRX1TS DP_OP_499J248_125_1651_R_1615_RW_1 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .CK(clk),
.RN(n9787), .Q(n8947) );
DFFSX1TS DP_OP_499J248_125_1651_R_1115_RW_3 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .CK(clk),
.SN(n8974), .Q(n8938) );
DFFSX2TS DP_OP_499J248_125_1651_R_2025 ( .D(n8933), .CK(clk), .SN(n9075),
.Q(n8968) );
DFFSX1TS DP_OP_499J248_125_1651_R_2022 ( .D(DP_OP_499J248_125_1651_n224),
.CK(clk), .SN(n8974), .Q(n8967) );
DFFSX2TS DP_OP_499J248_125_1651_R_1968 ( .D(DP_OP_499J248_125_1651_n215),
.CK(clk), .SN(n9786), .Q(n8960) );
DFFSX4TS DP_OP_499J248_125_1651_R_1966 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .CK(clk),
.SN(n9074), .Q(n8958) );
DFFSX4TS DP_OP_499J248_125_1651_R_1915 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .CK(clk),
.SN(n8973), .Q(n8955) );
DFFSX1TS DP_OP_499J248_125_1651_R_1853 ( .D(DP_OP_499J248_125_1651_n220),
.CK(clk), .SN(n8973), .Q(n8954) );
DFFRXLTS DP_OP_499J248_125_1651_R_1782_RW_0 ( .D(DP_OP_499J248_125_1651_n105), .CK(clk), .RN(n9523), .Q(n8951) );
DFFSX1TS DP_OP_499J248_125_1651_R_1781 ( .D(DP_OP_499J248_125_1651_n104),
.CK(clk), .SN(n8973), .Q(n8950) );
DFFSX1TS DP_OP_499J248_125_1651_R_1352 ( .D(DP_OP_499J248_125_1651_n208),
.CK(clk), .SN(n9524), .Q(n8944) );
DFFSX1TS DP_OP_499J248_125_1651_R_1055 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .CK(clk),
.SN(n8974), .Q(n8937) );
DFFSX1TS DP_OP_499J248_125_1651_R_984_RW_0 ( .D(n3678), .CK(clk), .SN(n8974),
.Q(n8934) );
DFFRX4TS DP_OP_497J248_123_1725_R_2488 ( .D(n8927), .CK(clk), .RN(n9515),
.Q(DP_OP_497J248_123_1725_n692) );
DFFSX4TS DP_OP_497J248_123_1725_R_2452 ( .D(n8882), .CK(clk), .SN(n9823),
.Q(n8863) );
DFFSX4TS DP_OP_497J248_123_1725_R_2453 ( .D(n8882), .CK(clk), .SN(n9824),
.Q(n8874) );
DFFRXLTS DP_OP_497J248_123_1725_R_2438 ( .D(n8926), .CK(clk), .RN(n9516),
.Q(DP_OP_497J248_123_1725_n667) );
DFFRXLTS DP_OP_497J248_123_1725_R_2437 ( .D(n8925), .CK(clk), .RN(n9515),
.Q(DP_OP_497J248_123_1725_n666) );
DFFRX2TS DP_OP_497J248_123_1725_R_2435 ( .D(n8924), .CK(clk), .RN(n9516),
.Q(DP_OP_497J248_123_1725_n606) );
DFFRX4TS DP_OP_497J248_123_1725_R_2431 ( .D(n8923), .CK(clk), .RN(n9515),
.Q(DP_OP_497J248_123_1725_n702) );
DFFSX4TS DP_OP_497J248_123_1725_R_2416 ( .D(n8922), .CK(clk), .SN(n9824),
.QN(n8932) );
DFFSX4TS DP_OP_497J248_123_1725_R_2404 ( .D(n8921), .CK(clk), .SN(n9824),
.Q(n8915) );
DFFSX4TS DP_OP_497J248_123_1725_R_2396 ( .D(n8920), .CK(clk), .SN(n9823),
.Q(n8904) );
DFFRX4TS DP_OP_497J248_123_1725_R_2385 ( .D(n8917), .CK(clk), .RN(n9528),
.Q(n8878) );
DFFSX4TS R_2520 ( .D(n8918), .CK(clk), .SN(n9028), .Q(
DP_OP_497J248_123_1725_n721), .QN(n2626) );
DFFRX4TS DP_OP_497J248_123_1725_R_2387 ( .D(n1678), .CK(clk), .RN(n6265),
.Q(DP_OP_497J248_123_1725_n705), .QN(n2643) );
DFFRX4TS DP_OP_497J248_123_1725_R_2382 ( .D(n8916), .CK(clk), .RN(n9516),
.Q(DP_OP_497J248_123_1725_n612) );
DFFSX4TS DP_OP_497J248_123_1725_R_2402 ( .D(n8914), .CK(clk), .SN(n8851),
.Q(n8866), .QN(n2600) );
DFFSX4TS DP_OP_497J248_123_1725_R_2434 ( .D(n8911), .CK(clk), .SN(n2271),
.Q(DP_OP_497J248_123_1725_n634) );
DFFSX4TS R_2513 ( .D(n8908), .CK(clk), .SN(n6440), .Q(
DP_OP_497J248_123_1725_n390) );
DFFSX4TS DP_OP_497J248_123_1725_R_2433 ( .D(n8894), .CK(clk), .SN(n6440),
.Q(n8901), .QN(n2661) );
DFFSX4TS R_2514 ( .D(n8903), .CK(clk), .SN(n9823), .Q(
DP_OP_497J248_123_1725_n379) );
DFFRX4TS DP_OP_497J248_123_1725_R_2279 ( .D(n8899), .CK(clk), .RN(n2292),
.Q(DP_OP_497J248_123_1725_n690), .QN(n2660) );
DFFRX4TS DP_OP_497J248_123_1725_R_2276 ( .D(n1673), .CK(clk), .RN(n9821),
.Q(n8876) );
DFFSX4TS R_2518 ( .D(n8898), .CK(clk), .SN(n2913), .Q(
DP_OP_497J248_123_1725_n722) );
DFFSX4TS DP_OP_497J248_123_1725_R_1321 ( .D(n8883), .CK(clk), .SN(n9823),
.Q(n8868), .QN(n3590) );
DFFSX4TS DP_OP_497J248_123_1725_R_1324 ( .D(n8893), .CK(clk), .SN(n9824),
.Q(n8872), .QN(n8930) );
DFFRX4TS DP_OP_497J248_123_1725_R_1302 ( .D(n9685), .CK(clk), .RN(n9528),
.Q(n8875) );
DFFSX4TS DP_OP_497J248_123_1725_R_2414 ( .D(n3632), .CK(clk), .SN(n2913),
.Q(n8873), .QN(n2641) );
DFFRX4TS DP_OP_497J248_123_1725_R_2317 ( .D(n1675), .CK(clk), .RN(n9528),
.Q(DP_OP_497J248_123_1725_n795) );
DFFSX4TS DP_OP_497J248_123_1725_R_2389 ( .D(n8890), .CK(clk), .SN(n8850),
.Q(DP_OP_497J248_123_1725_n638), .QN(n8902) );
DFFRX4TS DP_OP_497J248_123_1725_R_2415 ( .D(n1671), .CK(clk), .RN(n8850),
.Q(DP_OP_497J248_123_1725_n791) );
DFFSX4TS R_2511 ( .D(n3627), .CK(clk), .SN(n9821), .Q(
DP_OP_497J248_123_1725_n720) );
DFFRX4TS DP_OP_497J248_123_1725_R_1284 ( .D(n9639), .CK(clk), .RN(n8929),
.Q(DP_OP_497J248_123_1725_n699) );
DFFRX4TS DP_OP_497J248_123_1725_R_1276 ( .D(n8887), .CK(clk), .RN(n2863),
.Q(DP_OP_497J248_123_1725_n617) );
DFFSX4TS R_2498 ( .D(n8888), .CK(clk), .SN(n8852), .Q(
DP_OP_497J248_123_1725_n631) );
DFFRX4TS DP_OP_497J248_123_1725_R_2314 ( .D(n1643), .CK(clk), .RN(n2273),
.Q(DP_OP_497J248_123_1725_n782) );
DFFSX4TS R_2546 ( .D(n8885), .CK(clk), .SN(n9821), .Q(
DP_OP_497J248_123_1725_n636), .QN(n8900) );
DFFRX4TS DP_OP_497J248_123_1725_R_1268 ( .D(n1673), .CK(clk), .RN(n9526),
.Q(DP_OP_497J248_123_1725_n793) );
DFFSX4TS R_2548 ( .D(n8884), .CK(clk), .SN(n9028), .Q(
DP_OP_497J248_123_1725_n324), .QN(n8931) );
DFFRX4TS DP_OP_497J248_123_1725_R_1243 ( .D(n1680), .CK(clk), .RN(n8929),
.Q(DP_OP_497J248_123_1725_n693) );
DFFSX4TS DP_OP_497J248_123_1725_R_2309 ( .D(n8880), .CK(clk), .SN(n2272),
.Q(DP_OP_497J248_123_1725_n713) );
DFFSX4TS DP_OP_497J248_123_1725_R_2487 ( .D(n8879), .CK(clk), .SN(n2912),
.Q(DP_OP_497J248_123_1725_n718) );
DFFRX4TS DP_OP_497J248_123_1725_R_1230 ( .D(n1681), .CK(clk), .RN(n8929),
.Q(DP_OP_497J248_123_1725_n687) );
DFFSX4TS DP_OP_497J248_123_1725_R_2371 ( .D(n8870), .CK(clk), .SN(n9818),
.QN(n8877) );
DFFRX4TS DP_OP_497J248_123_1725_R_1196 ( .D(n1672), .CK(clk), .RN(n9531),
.Q(DP_OP_497J248_123_1725_n792), .QN(n2676) );
DFFSX4TS DP_OP_497J248_123_1725_R_2486 ( .D(n6267), .CK(clk), .SN(n8851),
.Q(DP_OP_497J248_123_1725_n717) );
DFFRX4TS DP_OP_497J248_123_1725_R_2374 ( .D(n9682), .CK(clk), .RN(n8852),
.Q(DP_OP_497J248_123_1725_n686) );
DFFSX4TS R_2497 ( .D(n6274), .CK(clk), .SN(n2884), .Q(
DP_OP_497J248_123_1725_n635) );
DFFRX4TS DP_OP_497J248_123_1725_R_344 ( .D(n2335), .CK(clk), .RN(n2913), .Q(
DP_OP_497J248_123_1725_n794) );
DFFSX4TS R_2510 ( .D(n8867), .CK(clk), .SN(n2276), .Q(
DP_OP_497J248_123_1725_n714) );
DFFRX4TS DP_OP_497J248_123_1725_R_339 ( .D(n1648), .CK(clk), .RN(n9821), .Q(
DP_OP_497J248_123_1725_n683) );
DFFSX4TS DP_OP_497J248_123_1725_R_2401 ( .D(n8862), .CK(clk), .SN(n9515),
.Q(DP_OP_497J248_123_1725_n389) );
DFFRX4TS DP_OP_497J248_123_1725_R_2436 ( .D(n9700), .CK(clk), .RN(n2885),
.Q(DP_OP_497J248_123_1725_n685) );
DFFSX4TS DP_OP_498J248_124_1725_R_2303 ( .D(n8836), .CK(clk), .SN(n6265),
.Q(n2826), .QN(n8858) );
DFFSX4TS DP_OP_498J248_124_1725_R_2444 ( .D(n8845), .CK(clk), .SN(n9028),
.Q(n8809), .QN(n2654) );
DFFRX4TS DP_OP_498J248_124_1725_R_2410 ( .D(n8841), .CK(clk), .RN(n2863),
.Q(DP_OP_498J248_124_1725_n618) );
DFFSX4TS DP_OP_498J248_124_1725_R_2409 ( .D(n6245), .CK(clk), .SN(n2293),
.Q(DP_OP_498J248_124_1725_n642) );
DFFSX4TS R_2538 ( .D(n8839), .CK(clk), .SN(n2293), .Q(
DP_OP_498J248_124_1725_n729), .QN(n2815) );
DFFSX4TS DP_OP_498J248_124_1725_R_2424 ( .D(n8837), .CK(clk), .SN(n2294),
.Q(DP_OP_498J248_124_1725_n726), .QN(n2814) );
DFFSX4TS R_2534 ( .D(n8834), .CK(clk), .SN(n2290), .Q(
DP_OP_498J248_124_1725_n640), .QN(n8846) );
DFFSX4TS R_2535 ( .D(n8833), .CK(clk), .SN(n2885), .Q(
DP_OP_498J248_124_1725_n639) );
DFFRX4TS DP_OP_498J248_124_1725_R_1650 ( .D(n1627), .CK(clk), .RN(n2883),
.Q(DP_OP_498J248_124_1725_n788), .QN(n2315) );
DFFSX4TS DP_OP_498J248_124_1725_R_1532 ( .D(n8860), .CK(clk), .SN(n9820),
.Q(DP_OP_498J248_124_1725_n394) );
DFFSX4TS DP_OP_498J248_124_1725_R_1534 ( .D(n8854), .CK(clk), .SN(n9820),
.Q(DP_OP_498J248_124_1725_n392) );
DFFRX4TS R_2528 ( .D(n8828), .CK(clk), .RN(n2267), .Q(
DP_OP_498J248_124_1725_n390), .QN(n8859) );
DFFRX4TS DP_OP_498J248_124_1725_R_1531 ( .D(n8827), .CK(clk), .RN(n2268),
.Q(n8803) );
DFFSX4TS DP_OP_498J248_124_1725_R_1318 ( .D(n8825), .CK(clk), .SN(n2294),
.Q(DP_OP_498J248_124_1725_n722), .QN(n2827) );
DFFRX4TS DP_OP_498J248_124_1725_R_1319 ( .D(n1637), .CK(clk), .RN(n8850),
.Q(DP_OP_498J248_124_1725_n786) );
DFFSX4TS DP_OP_498J248_124_1725_R_1313 ( .D(n8823), .CK(clk), .SN(n2886),
.QN(n8857) );
DFFSX4TS R_2540 ( .D(n8822), .CK(clk), .SN(n9820), .QN(n2829) );
DFFSX4TS DP_OP_498J248_124_1725_R_2408 ( .D(n8821), .CK(clk), .SN(n2884),
.Q(DP_OP_498J248_124_1725_n638), .QN(n8848) );
DFFRX4TS DP_OP_498J248_124_1725_R_1290 ( .D(n1628), .CK(clk), .RN(n2886),
.Q(DP_OP_498J248_124_1725_n789) );
DFFRX1TS DP_OP_498J248_124_1725_R_1254 ( .D(n8820), .CK(clk), .RN(n8850),
.Q(DP_OP_498J248_124_1725_n630) );
DFFSX4TS DP_OP_498J248_124_1725_R_1255 ( .D(n6262), .CK(clk), .SN(n2293),
.Q(DP_OP_498J248_124_1725_n634), .QN(n8849) );
DFFRX4TS DP_OP_498J248_124_1725_R_1208 ( .D(n9686), .CK(clk), .RN(n9028),
.Q(DP_OP_498J248_124_1725_n790) );
DFFRX4TS DP_OP_498J248_124_1725_R_1205 ( .D(n1630), .CK(clk), .RN(n8851),
.Q(DP_OP_498J248_124_1725_n791), .QN(n2677) );
DFFSX4TS DP_OP_498J248_124_1725_R_2302 ( .D(n8816), .CK(clk), .SN(n2864),
.Q(DP_OP_498J248_124_1725_n643), .QN(n8847) );
DFFSX4TS DP_OP_498J248_124_1725_R_1315 ( .D(n8815), .CK(clk), .SN(n9820),
.Q(DP_OP_498J248_124_1725_n645) );
DFFSX4TS R_2504 ( .D(n8814), .CK(clk), .SN(n2864), .Q(
DP_OP_498J248_124_1725_n641), .QN(n8855) );
DFFRX4TS DP_OP_498J248_124_1725_R_488 ( .D(n1663), .CK(clk), .RN(n2883), .Q(
DP_OP_498J248_124_1725_n804) );
DFFRX4TS R_2527 ( .D(n8813), .CK(clk), .RN(n2267), .QN(n2564) );
DFFSX4TS R_2491 ( .D(n8812), .CK(clk), .SN(n2289), .Q(
DP_OP_498J248_124_1725_n730), .QN(n2823) );
DFFSX4TS R_2537 ( .D(n8811), .CK(clk), .SN(n2294), .Q(
DP_OP_498J248_124_1725_n724), .QN(n2816) );
DFFRX4TS DP_OP_498J248_124_1725_R_365 ( .D(n1635), .CK(clk), .RN(n2912), .Q(
DP_OP_498J248_124_1725_n784) );
DFFRX4TS DP_OP_498J248_124_1725_R_1360 ( .D(n1666), .CK(clk), .RN(n2268),
.Q(DP_OP_498J248_124_1725_n795) );
DFFRX4TS DP_OP_498J248_124_1725_R_1361 ( .D(n9701), .CK(clk), .RN(n2268),
.Q(DP_OP_498J248_124_1725_n801) );
DFFRX4TS DP_OP_498J248_124_1725_R_350 ( .D(n1636), .CK(clk), .RN(n8852), .Q(
DP_OP_498J248_124_1725_n785), .QN(n2644) );
DFFSX4TS R_2495 ( .D(n8808), .CK(clk), .SN(n2293), .Q(
DP_OP_498J248_124_1725_n725), .QN(n2822) );
DFFRX4TS DP_OP_498J248_124_1725_R_336 ( .D(n1634), .CK(clk), .RN(n8851), .Q(
DP_OP_498J248_124_1725_n783) );
DFFSX4TS DP_OP_498J248_124_1725_R_2301 ( .D(n8807), .CK(clk), .SN(n2912),
.Q(DP_OP_498J248_124_1725_n635) );
DFFRX4TS DP_OP_498J248_124_1725_R_325 ( .D(n1631), .CK(clk), .RN(n9028), .Q(
DP_OP_498J248_124_1725_n792) );
DFFSX4TS DP_OP_498J248_124_1725_R_1643 ( .D(n8806), .CK(clk), .SN(n2294),
.Q(DP_OP_498J248_124_1725_n721), .QN(n2798) );
DFFSX4TS DP_OP_498J248_124_1725_R_1591 ( .D(n8805), .CK(clk), .SN(n2289),
.Q(DP_OP_498J248_124_1725_n728) );
DFFRX4TS DP_OP_498J248_124_1725_R_263 ( .D(n1669), .CK(clk), .RN(n2268), .Q(
DP_OP_498J248_124_1725_n798) );
DFFRX4TS R_2524 ( .D(n1670), .CK(clk), .RN(n2268), .Q(
DP_OP_498J248_124_1725_n799) );
DFFSX4TS R_2494 ( .D(n8804), .CK(clk), .SN(n2290), .Q(
DP_OP_498J248_124_1725_n727) );
DFFSX4TS add_x_219_R_2145 ( .D(add_x_219_n17), .CK(clk), .SN(n9524), .Q(
n8979) );
DFFSX4TS DP_OP_499J248_125_1651_R_1967 ( .D(n3452), .CK(clk), .SN(n9522),
.Q(n8959) );
DFFSX4TS DP_OP_499J248_125_1651_R_2044_RW_1 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .CK(clk),
.SN(n8976), .Q(n8970) );
DFFRX4TS DP_OP_496J248_122_3540_R_2420 ( .D(n9022), .CK(clk), .RN(n9030),
.Q(DP_OP_496J248_122_3540_n1383) );
DFFSX4TS DP_OP_496J248_122_3540_R_1226 ( .D(n8982), .CK(clk), .SN(n9029),
.Q(DP_OP_496J248_122_3540_n1205) );
DFFSX4TS R_2503 ( .D(n8818), .CK(clk), .SN(n2293), .Q(
DP_OP_498J248_124_1725_n636) );
DFFSX4TS DP_OP_497J248_123_1725_R_2370 ( .D(n8865), .CK(clk), .SN(n2863),
.Q(DP_OP_497J248_123_1725_n367), .QN(n2679) );
DFFRX4TS DP_OP_496J248_122_3540_R_2441 ( .D(n9024), .CK(clk), .RN(n6440),
.Q(DP_OP_496J248_122_3540_n1107) );
DFFRX4TS R_2525 ( .D(n1664), .CK(clk), .RN(n2267), .Q(
DP_OP_498J248_124_1725_n805) );
DFFRX2TS DP_OP_498J248_124_1725_R_272 ( .D(n1638), .CK(clk), .RN(n2913), .Q(
DP_OP_498J248_124_1725_n787) );
DFFRX2TS DP_OP_498J248_124_1725_R_2332 ( .D(n8838), .CK(clk), .RN(n8852),
.Q(DP_OP_498J248_124_1725_n703) );
DFFSX4TS DP_OP_499J248_125_1651_R_2043_RW_1 ( .D(DP_OP_499J248_125_1651_n299), .CK(clk), .SN(n8976), .Q(n8969) );
DFFRX4TS DP_OP_496J248_122_3540_R_1236 ( .D(n8991), .CK(clk), .RN(n9516),
.Q(DP_OP_496J248_122_3540_n1118) );
DFFRX4TS DP_OP_496J248_122_3540_R_2128 ( .D(n9002), .CK(clk), .RN(n9029),
.Q(DP_OP_496J248_122_3540_n1203) );
DFFRX4TS DP_OP_496J248_122_3540_R_2490 ( .D(n9026), .CK(clk), .RN(n9515),
.QN(n2657) );
DFFRX2TS DP_OP_496J248_122_3540_R_1249 ( .D(n9005), .CK(clk), .RN(n9030),
.Q(DP_OP_496J248_122_3540_n839) );
DFFRHQX4TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1250), .CK(clk), .RN(
n2887), .Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRHQX2TS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2121), .CK(clk), .RN(n9971), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRHQX1TS R_1652 ( .D(DP_OP_497J248_123_1725_n357), .CK(clk), .RN(n2796),
.Q(FPMULT_Op_MY[17]) );
DFFSX1TS R_1723 ( .D(n7811), .CK(clk), .SN(n2857), .Q(n9568) );
DFFRHQX1TS R_351 ( .D(DP_OP_497J248_123_1725_n781), .CK(clk), .RN(n9972),
.Q(n8800) );
DFFSRHQX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n3580), .CK(
clk), .SN(n2796), .RN(1'b1), .Q(n9841) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1348), .CK(clk), .RN(
n2841), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]) );
DFFRX2TS add_x_246_R_404 ( .D(n1518), .CK(clk), .RN(n2884), .Q(
add_x_246_A_1_) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1338), .CK(clk), .RN(
n2841), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1182), .CK(clk), .RN(
n9764), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(add_x_18_n35) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1455), .CK(clk), .RN(
n2847), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFSHQX4TS operation_dff_Q_reg_1_ ( .D(n9970), .CK(clk), .SN(n9971), .Q(
n9462) );
DFFRHQX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2077), .CK(clk),
.RN(n2888), .Q(FPADDSUB_shift_value_SHT2_EWR[4]) );
DFFRHQX1TS R_1344 ( .D(n6269), .CK(clk), .RN(n2797), .Q(n8798) );
DFFRHQX2TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n2911), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX4TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(n2689), .CK(clk),
.RN(n9971), .Q(n9463), .QN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0])
);
DFFSRHQX8TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1812), .CK(clk), .SN(
1'b1), .RN(n2888), .Q(FPADDSUB_Data_array_SWR[23]) );
DFFSRHQX8TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1793), .CK(clk), .SN(
1'b1), .RN(n2888), .Q(FPADDSUB_Data_array_SWR[4]) );
DFFSRHQX4TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1804), .CK(clk), .SN(
1'b1), .RN(n2889), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRHQX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1693), .CK(clk), .RN(
n9971), .Q(FPMULT_FS_Module_state_reg[1]) );
DFFSX4TS add_x_69_R_1919 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[7]), .CK(clk),
.SN(n9077), .Q(n9055) );
DFFSHQX8TS R_1963 ( .D(n9552), .CK(clk), .SN(n2887), .Q(
DP_OP_26J248_126_1325_n28) );
DFFSHQX4TS DP_OP_498J248_124_1725_R_2411 ( .D(n8819), .CK(clk), .SN(n2797),
.Q(n8817) );
DFFSX4TS DP_OP_498J248_124_1725_R_2412 ( .D(n8829), .CK(clk), .SN(n2797),
.Q(DP_OP_498J248_124_1725_n380), .QN(n8856) );
DFFSHQX8TS DP_OP_498J248_124_1725_R_2331 ( .D(n8810), .CK(clk), .SN(n2796),
.Q(DP_OP_498J248_124_1725_n723) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2147), .CK(clk), .RN(
n9772), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]), .QN(n9127) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n9789), .Q(
FPSENCOS_d_ff_Xn[24]), .QN(n9285) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n9789), .Q(
FPSENCOS_d_ff_Xn[26]), .QN(n9284) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1770), .CK(clk), .RN(n9790), .Q(
FPSENCOS_d_ff_Zn[29]), .QN(n9445) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1977), .CK(clk), .RN(
n9784), .Q(FPSENCOS_d_ff2_X[15]), .QN(n9133) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1867), .CK(clk), .RN(
n9793), .Q(FPSENCOS_d_ff2_Y[21]), .QN(n9435) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1969), .CK(clk), .RN(
n9805), .Q(FPSENCOS_d_ff2_X[19]), .QN(n9118) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1995), .CK(clk), .RN(
n9781), .Q(FPSENCOS_d_ff2_X[6]), .QN(n9113) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1877), .CK(clk), .RN(
n9803), .Q(FPSENCOS_d_ff2_Y[16]), .QN(n9135) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1979), .CK(clk), .RN(
n6442), .Q(FPSENCOS_d_ff2_X[14]), .QN(n9116) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1885), .CK(clk), .RN(
n9785), .Q(FPSENCOS_d_ff2_Y[12]), .QN(n9134) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2066), .CK(clk), .RN(n9804), .Q(
FPSENCOS_d_ff_Yn[3]), .QN(n9359) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2003), .CK(clk), .RN(
n9806), .Q(FPSENCOS_d_ff2_X[2]), .QN(n9124) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2007), .CK(clk), .RN(
n9807), .Q(FPSENCOS_d_ff2_X[0]), .QN(n9429) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n9780), .Q(
FPSENCOS_d_ff_Xn[9]), .QN(n9304) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1504), .CK(clk), .RN(n9821), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1485), .CK(clk), .RN(n9823), .Q(mult_result[30]) );
DFFRX1TS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1441), .CK(clk), .RN(
n9518), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n2868),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]), .QN(n9193) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n2867),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]), .QN(n9178) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n2852),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]), .QN(n9173) );
DFFSX1TS R_1382 ( .D(n9859), .CK(clk), .SN(n9517), .Q(n9632) );
DFFSX1TS R_1430 ( .D(n9857), .CK(clk), .SN(n9759), .Q(n9616) );
DFFSX1TS R_1481 ( .D(n9853), .CK(clk), .SN(n2867), .Q(n9599) );
DFFRXLTS R_1635 ( .D(n1568), .CK(clk), .RN(n9812), .Q(n9573) );
DFFRXLTS R_1714 ( .D(n9111), .CK(clk), .RN(n2871), .Q(n9571) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n9767),
.Q(FPADDSUB_SIGN_FLAG_SFG), .QN(n9477) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n9781), .Q(
FPSENCOS_d_ff_Xn[6]), .QN(n9290) );
DFFSX1TS R_1278_IP ( .D(n3627), .CK(clk), .SN(n2797), .Q(n9641) );
DFFRX4TS DP_OP_498J248_124_1725_R_1316 ( .D(n8824), .CK(clk), .RN(n2912),
.Q(DP_OP_498J248_124_1725_n631) );
DFFRX4TS DP_OP_497J248_123_1725_R_1301 ( .D(n8891), .CK(clk), .RN(n8850),
.Q(DP_OP_497J248_123_1725_n604) );
DFFRX4TS DP_OP_497J248_123_1725_R_2318 ( .D(n8910), .CK(clk), .RN(n2271),
.Q(DP_OP_497J248_123_1725_n602) );
DFFRX4TS DP_OP_497J248_123_1725_R_2297 ( .D(n8905), .CK(clk), .RN(n8929),
.Q(DP_OP_497J248_123_1725_n600) );
DFFRX4TS DP_OP_497J248_123_1725_R_1263 ( .D(n9696), .CK(clk), .RN(n8929),
.Q(DP_OP_497J248_123_1725_n312) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1928), .CK(clk), .RN(
n2875), .Q(FPADDSUB_intDX_EWSW[15]) );
DFFRX4TS DP_OP_498J248_124_1725_R_1592 ( .D(n8830), .CK(clk), .RN(n8850),
.Q(DP_OP_498J248_124_1725_n699) );
DFFRX4TS DP_OP_498J248_124_1725_R_2425 ( .D(n8843), .CK(clk), .RN(n2267),
.Q(DP_OP_498J248_124_1725_n694) );
DFFRX4TS DP_OP_498J248_124_1725_R_1256 ( .D(n9640), .CK(clk), .RN(n2913),
.Q(DP_OP_498J248_124_1725_n793) );
DFFRX4TS DP_OP_497J248_123_1725_R_342 ( .D(n8869), .CK(clk), .RN(n9028), .Q(
DP_OP_497J248_123_1725_n607) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1322), .CK(clk), .RN(
n9760), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n9232) );
DFFRX4TS DP_OP_499J248_125_1651_R_2132_RW_0 ( .D(
FPMULT_Sgf_operation_EVEN1_Q_right[23]), .CK(clk), .RN(n9523), .QN(
n8978) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1942), .CK(clk), .RN(
n2875), .Q(FPADDSUB_intDX_EWSW[1]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1929), .CK(clk), .RN(
n2859), .Q(FPADDSUB_intDX_EWSW[14]) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1335), .CK(clk), .RN(
n9756), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]) );
DFFRX4TS DP_OP_497J248_123_1725_R_2390 ( .D(n8919), .CK(clk), .RN(n2272),
.Q(DP_OP_497J248_123_1725_n624) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1940), .CK(clk), .RN(
n2872), .Q(FPADDSUB_intDX_EWSW[3]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1930), .CK(clk), .RN(
n2927), .Q(FPADDSUB_intDX_EWSW[13]) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(
n9773), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n9097) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1336), .CK(clk), .RN(
n2860), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n9230) );
DFFRX4TS DP_OP_497J248_123_1725_R_1571 ( .D(n8897), .CK(clk), .RN(n9532),
.Q(DP_OP_497J248_123_1725_n704) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1932), .CK(clk), .RN(
n9761), .Q(FPADDSUB_intDX_EWSW[11]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n2887),
.Q(FPADDSUB_DMP_SFG[8]), .QN(n9484) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n2854),
.Q(FPADDSUB_DMP_SFG[5]), .QN(n9482) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1943), .CK(clk), .RN(
n2887), .Q(FPADDSUB_intDX_EWSW[0]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n2853),
.Q(FPADDSUB_DMP_SFG[4]), .QN(n9485) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n2870),
.Q(FPADDSUB_DMP_SFG[16]), .QN(n9472) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2078), .CK(clk), .RN(
n2881), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n9763),
.Q(FPADDSUB_DMP_SFG[0]), .QN(n9489) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n2927),
.Q(FPADDSUB_DMP_SFG[9]), .QN(n9494) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1836), .CK(clk), .RN(
n2851), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1323), .CK(clk), .RN(
n2862), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]), .QN(n9108) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1941), .CK(clk), .RN(
n8252), .Q(FPADDSUB_intDX_EWSW[2]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n2878),
.Q(FPADDSUB_DMP_SFG[1]), .QN(n9483) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1920), .CK(clk), .RN(
n2851), .Q(FPADDSUB_intDX_EWSW[23]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n9771),
.Q(FPADDSUB_DMP_SFG[17]), .QN(n9474) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1934), .CK(clk), .RN(
n9763), .Q(FPADDSUB_intDX_EWSW[9]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n2841),
.Q(FPADDSUB_DMP_SFG[7]), .QN(n9499) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1931), .CK(clk), .RN(
n2857), .Q(FPADDSUB_intDX_EWSW[12]) );
DFFSX4TS DP_OP_499J248_125_1651_R_2020_RW_1 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .CK(clk),
.SN(n8975), .Q(n8965) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1832), .CK(clk), .RN(
n2928), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n3635) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1197), .CK(clk), .RN(
n2875), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n3665) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n2853),
.Q(FPADDSUB_DMP_SFG[3]), .QN(n9493) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n2848),
.Q(FPADDSUB_DMP_SFG[15]), .QN(n9498) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n9761),
.Q(FPADDSUB_DMP_SFG[12]), .QN(n9488) );
DFFRX4TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1694), .CK(clk), .RN(n2842),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n3682) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n9763),
.Q(FPADDSUB_DMP_SFG[11]), .QN(n9492) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n9762),
.Q(FPADDSUB_DMP_SFG[6]), .QN(n9497) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1196), .CK(clk), .RN(
n2848), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n3662) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n2866),
.Q(FPADDSUB_DMP_SFG[13]), .QN(n9487) );
DFFRX4TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1523), .CK(
clk), .RN(n2912), .Q(FPMULT_Sgf_normalized_result[6]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1201), .CK(clk), .RN(
n9763), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n3674) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n2847),
.Q(FPADDSUB_DMP_SFG[2]), .QN(n9486) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1205), .CK(clk), .RN(
n9761), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n3658) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n2926),
.Q(FPADDSUB_DMP_SFG[10]), .QN(n9490) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1200), .CK(clk), .RN(
n9766), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n3672) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1838), .CK(clk), .RN(
n2875), .Q(FPADDSUB_intDY_EWSW[7]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1189), .CK(clk), .RN(
n9754), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n3673) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1835), .CK(clk), .RN(
n2859), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1843), .CK(clk), .RN(
n2848), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1935), .CK(clk), .RN(
n8252), .Q(FPADDSUB_intDX_EWSW[8]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1840), .CK(clk), .RN(
n2879), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n9753),
.Q(FPADDSUB_DMP_SFG[14]), .QN(n9491) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n2866),
.Q(FPADDSUB_DMP_SFG[19]), .QN(n9473) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1188), .CK(clk), .RN(
n9767), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n3675) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n9768),
.Q(FPADDSUB_DMP_SFG[18]), .QN(n9500) );
DFFRX4TS DP_OP_497J248_123_1725_R_1349 ( .D(n8895), .CK(clk), .RN(n9820),
.Q(DP_OP_497J248_123_1725_n610) );
DFFRX2TS DP_OP_498J248_124_1725_R_2443 ( .D(n8844), .CK(clk), .RN(n8851),
.Q(DP_OP_498J248_124_1725_n611) );
DFFRX2TS DP_OP_497J248_123_1725_R_2324 ( .D(n8912), .CK(clk), .RN(n2275),
.Q(DP_OP_497J248_123_1725_n613) );
DFFRX2TS DP_OP_498J248_124_1725_R_1358 ( .D(n8826), .CK(clk), .RN(n2912),
.Q(DP_OP_498J248_124_1725_n698) );
DFFRX2TS DP_OP_496J248_122_3540_R_1191 ( .D(n8999), .CK(clk), .RN(n9027),
.Q(DP_OP_496J248_122_3540_n828) );
DFFRX4TS DP_OP_497J248_123_1725_R_2372 ( .D(n8913), .CK(clk), .RN(n9530),
.Q(DP_OP_497J248_123_1725_n618) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1830), .CK(clk), .RN(
n2857), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n3653) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1207), .CK(clk), .RN(
n2841), .Q(FPADDSUB_DmP_mant_SFG_SWR[0]), .QN(sub_x_17_n206) );
DFFRX4TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2139), .CK(clk), .RN(n9520),
.Q(FPSENCOS_cont_var_out[0]), .QN(n9245) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1922), .CK(clk), .RN(
n9762), .Q(FPADDSUB_intDX_EWSW[21]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2144), .CK(clk), .RN(
n9772), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n9514) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1841), .CK(clk), .RN(
n2868), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1839), .CK(clk), .RN(
n8252), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1829), .CK(clk), .RN(
n9763), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1923), .CK(clk), .RN(
n2874), .Q(FPADDSUB_intDX_EWSW[20]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1925), .CK(clk), .RN(
n2878), .Q(FPADDSUB_intDX_EWSW[18]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1926), .CK(clk), .RN(
n2927), .Q(FPADDSUB_intDX_EWSW[17]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1918), .CK(clk), .RN(
n9771), .Q(FPADDSUB_intDX_EWSW[25]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1917), .CK(clk), .RN(
n9771), .Q(FPADDSUB_intDX_EWSW[26]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1821), .CK(clk), .RN(
n2872), .Q(FPADDSUB_intDY_EWSW[24]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1921), .CK(clk), .RN(
n2861), .Q(FPADDSUB_intDX_EWSW[22]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1818), .CK(clk), .RN(
n2851), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1817), .CK(clk), .RN(
n2880), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1826), .CK(clk), .RN(
n2847), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n3605) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1831), .CK(clk), .RN(
n2859), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n3649) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1833), .CK(clk), .RN(
n2857), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n3650) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2149), .CK(clk), .RN(
n9773), .Q(n2695), .QN(n9825) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n2861),
.Q(FPADDSUB_DMP_SFG[21]), .QN(n9495) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n2874),
.Q(FPADDSUB_DMP_SFG[20]), .QN(n9496) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n2851),
.Q(FPADDSUB_DMP_SFG[22]), .QN(n9509) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1842), .CK(clk), .RN(
n2872), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n3638) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1936), .CK(clk), .RN(
n2875), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n3599) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1822), .CK(clk), .RN(
n9759), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n3598) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1844), .CK(clk), .RN(
n2871), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n3637) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1834), .CK(clk), .RN(
n9757), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n3652) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1837), .CK(clk), .RN(
n8252), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n3634) );
DFFRX4TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2151), .CK(
clk), .RN(n9773), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n9275) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2079), .CK(clk), .RN(
n2875), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n3596) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2081), .CK(clk), .RN(
n2851), .Q(FPADDSUB_bit_shift_SHT2), .QN(n9110) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2140), .CK(clk), .RN(n9813),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n9274) );
ADDFHX2TS intadd_734_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n9274), .CI(
intadd_734_n2), .CO(intadd_734_n1), .S(intadd_734_SUM_2_) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(
n9762), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n3667) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1199), .CK(clk), .RN(
n9767), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n3668) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(
n2881), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n3661) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1814), .CK(clk), .RN(n2928), .Q(FPADDSUB_Data_array_SWR[25]), .QN(n9258) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1811), .CK(clk), .RN(n2851), .Q(FPADDSUB_Data_array_SWR[22]), .QN(n9246) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1203), .CK(clk), .RN(
n9754), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n3677) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1192), .CK(clk), .RN(
n9768), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n3664) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1202), .CK(clk), .RN(
n9757), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n3671) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1193), .CK(clk), .RN(
n2881), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n3663) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1187), .CK(clk), .RN(
n9761), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n3670) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1186), .CK(clk), .RN(
n9757), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n3676) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1351), .CK(clk), .RN(
n2868), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n9511) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1183), .CK(clk), .RN(
n9758), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n3660) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1190), .CK(clk), .RN(
n2928), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n3669) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1198), .CK(clk), .RN(
n9758), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n3666) );
DFFRX4TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1536), .CK(
clk), .RN(n2278), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFSX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n2690), .CK(clk), .SN(
n2888), .Q(sub_x_17_n251), .QN(FPADDSUB_DmP_mant_SFG_SWR[3]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1194), .CK(clk), .RN(
n9755), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n9475) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n9794),
.Q(cordic_result[0]) );
DFFRX4TS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1849), .CK(clk), .RN(n9809),
.Q(FPSENCOS_d_ff3_sh_y_out[29]), .QN(n2696) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n9519), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .QN(n9244) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n9207), .CK(clk),
.RN(n9524), .Q(FPMULT_P_Sgf[12]) );
DFFRX4TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n9797), .Q(
dataA[28]) );
DFFRX4TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1561), .CK(clk),
.RN(n9812), .Q(FPMULT_P_Sgf[8]) );
DFFRX4TS R_357 ( .D(n9701), .CK(clk), .RN(n9527), .QN(n9458) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1730), .CK(clk), .RN(
n9758), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1613), .CK(clk),
.RN(n9819), .Q(FPMULT_Add_result[11]), .QN(n9256) );
DFFRX4TS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1626), .CK(
clk), .RN(n9820), .Q(FPMULT_zero_flag), .QN(n9202) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1792), .CK(clk), .RN(n9758),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRX4TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1789), .CK(clk), .RN(n2866),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1761), .CK(clk), .RN(
n9777), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1744), .CK(clk), .RN(
n9793), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1737), .CK(clk), .RN(
n9790), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRX4TS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1948), .CK(clk), .RN(n9809),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRX4TS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1850), .CK(clk), .RN(n9809),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2145), .CK(clk), .RN(
n9772), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2909) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2150), .CK(clk), .RN(
n9773), .Q(FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n9513) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1924), .CK(clk), .RN(
n9757), .Q(FPADDSUB_intDX_EWSW[19]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1919), .CK(clk), .RN(
n2851), .Q(FPADDSUB_intDX_EWSW[24]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1916), .CK(clk), .RN(
n9771), .Q(FPADDSUB_intDX_EWSW[27]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1927), .CK(clk), .RN(
n9758), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n3592) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1824), .CK(clk), .RN(
n9758), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n3651) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1939), .CK(clk), .RN(
n2868), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n3602) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1825), .CK(clk), .RN(
n9753), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n3654) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1820), .CK(clk), .RN(
n9769), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n3644) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1827), .CK(clk), .RN(
n2848), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n3636) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1828), .CK(clk), .RN(
n2928), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n3655) );
DFFRX4TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n9772),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n9205) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1184), .CK(clk), .RN(
n9766), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n3659) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1185), .CK(clk), .RN(
n9764), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n3657) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2080), .CK(clk), .RN(
n2861), .Q(FPADDSUB_left_right_SHT2), .QN(n9468) );
DFFRX4TS R_2097 ( .D(n9468), .CK(clk), .RN(n2878), .Q(n9544) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1195), .CK(clk), .RN(
n2866), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n9476) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1816), .CK(clk), .RN(
n2878), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n3648) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1915), .CK(clk), .RN(
n9771), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n3591) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1815), .CK(clk), .RN(
n9771), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n3646) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1318), .CK(clk), .RN(
n9773), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]), .QN(n9231) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1819), .CK(clk), .RN(
n9518), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n3656) );
DFFRX4TS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(n2927),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRX4TS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n9797), .Q(
dataA[26]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n9797), .Q(
dataA[23]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1542), .CK(clk), .RN(
n2839), .Q(FPMULT_exp_oper_result[7]), .QN(n3688) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n9798), .Q(
dataB[28]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n9797), .Q(
dataA[24]) );
DFFRX4TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1562), .CK(clk),
.RN(n9812), .Q(FPMULT_P_Sgf[9]) );
DFFRX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n9243), .CK(clk),
.RN(n9523), .Q(FPMULT_P_Sgf[1]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1733), .CK(clk), .RN(
n2878), .Q(FPADDSUB_intAS) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1912), .CK(clk), .RN(
n9753), .Q(FPADDSUB_intDX_EWSW[31]), .QN(n9510) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1563), .CK(clk),
.RN(n9786), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n9208), .CK(clk),
.RN(n9786), .Q(FPMULT_P_Sgf[11]) );
DFFSX2TS R_1427 ( .D(n9920), .CK(clk), .SN(n2872), .Q(n9617) );
DFFSX2TS R_1457 ( .D(n9919), .CK(clk), .SN(n2874), .Q(n9607) );
DFFSX2TS R_1487 ( .D(n9921), .CK(clk), .SN(n2873), .Q(n9597) );
DFFRX1TS R_1525 ( .D(n1541), .CK(clk), .RN(n2278), .Q(n9585) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n9799), .Q(
dataB[26]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n9799), .Q(
dataB[23]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n9233), .CK(clk),
.RN(n9812), .Q(FPMULT_P_Sgf[6]) );
DFFRX4TS DP_OP_499J248_125_1651_R_2054_RW_1 ( .D(
FPMULT_Sgf_operation_EVEN1_Q_left[22]), .CK(clk), .RN(n8973), .QN(
n8977) );
DFFRX4TS DP_OP_498J248_124_1725_R_2406 ( .D(n8840), .CK(clk), .RN(n2913),
.Q(DP_OP_498J248_124_1725_n616), .QN(n2825) );
DFFSX2TS DP_OP_499J248_125_1651_R_1366 ( .D(DP_OP_499J248_125_1651_n207),
.CK(clk), .SN(n8974), .Q(n8946) );
DFFRX4TS DP_OP_497J248_123_1725_R_1355 ( .D(n8896), .CK(clk), .RN(n9817),
.Q(DP_OP_497J248_123_1725_n609) );
DFFRX4TS DP_OP_497J248_123_1725_R_1322 ( .D(n1647), .CK(clk), .RN(n8852),
.Q(DP_OP_497J248_123_1725_n684) );
DFFSX4TS DP_OP_496J248_122_3540_R_2428 ( .D(n9023), .CK(clk), .SN(n9526),
.Q(DP_OP_496J248_122_3540_n788), .QN(n2675) );
DFFRX2TS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1852), .CK(clk), .RN(n9775),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRX2TS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1853), .CK(clk), .RN(n9776),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1743), .CK(clk), .RN(
n9774), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1736), .CK(clk), .RN(
n9790), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1746), .CK(clk), .RN(
n9778), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1755), .CK(clk), .RN(
n9800), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1754), .CK(clk), .RN(
n9784), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1739), .CK(clk), .RN(
n9791), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1738), .CK(clk), .RN(
n9790), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1747), .CK(clk), .RN(
n9805), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1765), .CK(clk), .RN(
n9808), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1764), .CK(clk), .RN(
n9806), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1757), .CK(clk), .RN(
n9780), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1753), .CK(clk), .RN(
n9801), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1748), .CK(clk), .RN(
n9804), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1749), .CK(clk), .RN(
n9801), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1752), .CK(clk), .RN(
n9802), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1763), .CK(clk), .RN(
n9803), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1751), .CK(clk), .RN(
n9784), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1762), .CK(clk), .RN(
n9798), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1760), .CK(clk), .RN(
n9781), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1750), .CK(clk), .RN(
n9785), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1745), .CK(clk), .RN(
n9778), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1741), .CK(clk), .RN(
n9791), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1758), .CK(clk), .RN(
n9782), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1740), .CK(clk), .RN(
n9791), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRX2TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1742), .CK(clk), .RN(
n9780), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRX2TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2118), .CK(clk), .RN(n9776), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n9794),
.Q(cordic_result[6]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n9794),
.Q(cordic_result[8]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n9794),
.Q(cordic_result[1]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n9794),
.Q(cordic_result[7]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n9794),
.Q(cordic_result[5]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n9794),
.Q(cordic_result[4]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n9794),
.Q(cordic_result[2]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n9794),
.Q(cordic_result[3]) );
DFFRX2TS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2122), .CK(clk), .RN(n9776), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRX4TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1539), .CK(
clk), .RN(n2839), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2148), .CK(clk), .RN(
n9773), .Q(n9973), .QN(n9512) );
DFFRX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1558), .CK(clk),
.RN(n9523), .Q(FPMULT_P_Sgf[5]) );
DFFRX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1560), .CK(clk),
.RN(n9812), .Q(FPMULT_P_Sgf[7]) );
DFFRX4TS R_1194 ( .D(n1672), .CK(clk), .RN(n9527), .QN(n9271) );
DFFRX4TS R_1247 ( .D(n1666), .CK(clk), .RN(n9528), .QN(n9694) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1823), .CK(clk), .RN(
n2852), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n3604) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1913), .CK(clk), .RN(
n9771), .Q(FPADDSUB_intDX_EWSW[30]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1938), .CK(clk), .RN(
n9762), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n2647) );
DFFRX2TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1553), .CK(clk),
.RN(n9523), .Q(FPMULT_P_Sgf[0]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1937), .CK(clk), .RN(
n8252), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n3603) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1845), .CK(clk), .RN(
n2880), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX4TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1914), .CK(clk), .RN(
n9771), .Q(FPADDSUB_intDX_EWSW[29]) );
DFFSX4TS DP_OP_499J248_125_1651_R_1851 ( .D(DP_OP_499J248_125_1651_n273),
.CK(clk), .SN(n8973), .Q(n8952) );
DFFRX4TS DP_OP_497J248_123_1725_R_2311 ( .D(n8907), .CK(clk), .RN(n2270),
.Q(DP_OP_497J248_123_1725_n710) );
DFFRX1TS add_x_69_R_2102_RW_1 ( .D(n2258), .CK(clk), .RN(n9079), .Q(n9066)
);
DFFRX1TS add_x_69_R_1893_RW_3 ( .D(n2633), .CK(clk), .RN(n9079), .Q(n9054)
);
DFFRX1TS R_1231 ( .D(n1649), .CK(clk), .RN(n9824), .QN(n9713) );
DFFRXLTS R_1198 ( .D(n1540), .CK(clk), .RN(n2884), .Q(n9647) );
DFFRXLTS R_1926_RW_3 ( .D(n9276), .CK(clk), .RN(n9520), .Q(n9554) );
DFFSX4TS DP_OP_499J248_125_1651_R_2015 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .CK(clk),
.SN(n8974), .Q(n8963) );
DFFSHQX8TS R_2517 ( .D(n8871), .CK(clk), .SN(n2886), .Q(n2608) );
DFFSHQX8TS R_2549 ( .D(n8864), .CK(clk), .SN(n2885), .Q(n2607) );
DFFSHQX8TS DP_OP_497J248_123_1725_R_2373 ( .D(n8870), .CK(clk), .SN(n6440),
.Q(n2604) );
DFFRX4TS DP_OP_497J248_123_1725_R_1296 ( .D(n8889), .CK(clk), .RN(n8851),
.Q(DP_OP_497J248_123_1725_n623) );
DFFSHQX8TS R_2545 ( .D(n8909), .CK(clk), .SN(n2272), .Q(n2601) );
DFFSX2TS DP_OP_499J248_125_1651_R_1852 ( .D(DP_OP_499J248_125_1651_n223),
.CK(clk), .SN(n8973), .Q(n8953) );
DFFSX4TS R_2492 ( .D(n8812), .CK(clk), .SN(n2289), .Q(n4006) );
DFFRX2TS R_2499 ( .D(n2575), .CK(clk), .RN(n2884), .Q(n4384) );
DFFRX4TS R_2502 ( .D(n2574), .CK(clk), .RN(n2913), .Q(n3128) );
DFFRX2TS R_2505 ( .D(n2573), .CK(clk), .RN(n2292), .Q(n4051) );
DFFSX2TS R_2506 ( .D(n6171), .CK(clk), .SN(n2279), .Q(n2572) );
DFFSX2TS R_2507 ( .D(n6170), .CK(clk), .SN(n2279), .Q(n2571) );
DFFSX2TS R_2508 ( .D(n6169), .CK(clk), .SN(n2279), .Q(n2570) );
DFFSX1TS add_x_246_R_1264 ( .D(n1537), .CK(clk), .SN(n9529), .Q(n9089) );
DFFSX2TS R_2509 ( .D(n2569), .CK(clk), .SN(n8852), .Q(n3400) );
DFFRX2TS R_2512 ( .D(n2568), .CK(clk), .RN(n2275), .Q(n4535) );
DFFSX4TS R_2516 ( .D(n8892), .CK(clk), .SN(n9532), .Q(n2605) );
DFFRX4TS R_2515 ( .D(n2567), .CK(clk), .RN(n9532), .Q(n3419) );
DFFSX4TS R_2521 ( .D(n8918), .CK(clk), .SN(n2912), .Q(n3118) );
DFFSX4TS R_2523 ( .D(n8833), .CK(clk), .SN(n2883), .Q(n3002) );
DFFSX4TS R_2526 ( .D(n2565), .CK(clk), .SN(n2268), .Q(n3961), .QN(n2313) );
DFFRX2TS R_2529 ( .D(n2563), .CK(clk), .RN(n2267), .Q(n3566) );
DFFRX4TS R_2530 ( .D(n2562), .CK(clk), .RN(n9029), .Q(n4884) );
DFFSX2TS R_2531 ( .D(n6138), .CK(clk), .SN(n2290), .Q(n2561) );
DFFSX2TS R_2532 ( .D(n6137), .CK(clk), .SN(n2290), .Q(n2560) );
DFFSX2TS R_2533 ( .D(n6136), .CK(clk), .SN(n2290), .Q(n2559) );
DFFRX2TS R_2539 ( .D(n2557), .CK(clk), .RN(n2292), .Q(n3957) );
DFFRX4TS R_2541 ( .D(n1665), .CK(clk), .RN(n9820), .Q(n2582) );
DFFSX2TS R_2542 ( .D(n6135), .CK(clk), .SN(n2290), .Q(n2556) );
DFFSX2TS R_2543 ( .D(n6134), .CK(clk), .SN(n2290), .Q(n2555) );
DFFSX2TS R_2544 ( .D(n6133), .CK(clk), .SN(n2290), .Q(n2554) );
DFFRX2TS R_2547 ( .D(n2553), .CK(clk), .RN(n2270), .Q(n4410) );
DFFSX2TS R_2550 ( .D(n2552), .CK(clk), .SN(n9028), .Q(n2609) );
DFFSX2TS R_2555 ( .D(n9968), .CK(clk), .SN(n2889), .Q(n2547) );
DFFSX2TS R_2556 ( .D(n6649), .CK(clk), .SN(n9524), .Q(n2546) );
DFFSX2TS R_2557 ( .D(n9101), .CK(clk), .SN(n9755), .Q(n2545) );
DFFSX2TS R_2558 ( .D(n9956), .CK(clk), .SN(n2873), .Q(n2544), .QN(n2281) );
DFFSX2TS R_2559 ( .D(n6747), .CK(clk), .SN(n2864), .Q(n2543) );
DFFSX2TS R_2560 ( .D(n6649), .CK(clk), .SN(n9521), .Q(n2542) );
DFFSX2TS R_2561 ( .D(n9752), .CK(clk), .SN(n9521), .Q(n2541) );
DFFSX4TS R_2562 ( .D(DP_OP_499J248_125_1651_n216), .CK(clk), .SN(n8975), .Q(
n2540) );
DFFSX2TS R_2563 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[20]), .CK(clk), .SN(
n9077), .Q(n2539) );
DFFRX2TS R_2564 ( .D(n9941), .CK(clk), .RN(n2869), .Q(n2538) );
DFFRX2TS R_2565 ( .D(n9939), .CK(clk), .RN(n2879), .Q(n2537) );
DFFRX2TS R_2566 ( .D(n9937), .CK(clk), .RN(n8252), .Q(n2536) );
DFFRX2TS R_2567 ( .D(n9936), .CK(clk), .RN(n2860), .Q(n2535) );
DFFRX2TS R_2568 ( .D(n9935), .CK(clk), .RN(n2876), .Q(n2534) );
DFFRX2TS R_2569 ( .D(n9938), .CK(clk), .RN(n2877), .Q(n2533) );
DFFRX2TS R_2570 ( .D(n9945), .CK(clk), .RN(n2853), .Q(n2532) );
DFFRX2TS R_2571 ( .D(n9944), .CK(clk), .RN(n2873), .Q(n2531) );
DFFRX2TS R_2572 ( .D(n9943), .CK(clk), .RN(n2874), .Q(n2530) );
DFFRX2TS R_2573 ( .D(n9946), .CK(clk), .RN(n2867), .Q(n2529) );
DFFRX2TS R_2575 ( .D(n9958), .CK(clk), .RN(n9761), .Q(n2527) );
DFFRX2TS R_2576 ( .D(n9940), .CK(clk), .RN(n2880), .Q(n2526) );
DFFRX2TS R_2577 ( .D(n9932), .CK(clk), .RN(n9755), .Q(n2525) );
DFFRX2TS R_2578 ( .D(n9931), .CK(clk), .RN(n2858), .Q(n2524) );
DFFRX2TS R_2579 ( .D(n9934), .CK(clk), .RN(n2927), .Q(n2523) );
DFFRX2TS R_2580 ( .D(n9933), .CK(clk), .RN(n2888), .Q(n2522) );
DFFSX2TS R_2581 ( .D(n9750), .CK(clk), .SN(n9823), .Q(n2521) );
DFFSX2TS R_2582 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .CK(clk), .SN(
n9078), .Q(n2520) );
DFFSX2TS R_2583 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[8]), .CK(clk), .SN(n9074), .Q(n2519) );
DFFSX2TS R_2584 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[6]), .CK(clk), .SN(n9078), .Q(n2518) );
DFFSX2TS R_2585 ( .D(DP_OP_499J248_125_1651_n106), .CK(clk), .SN(n8973), .Q(
n2517) );
DFFSX2TS R_2586 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[10]), .CK(clk), .SN(
n6420), .Q(n2516) );
DFFRX2TS R_2588 ( .D(n2327), .CK(clk), .RN(n9076), .Q(n2514) );
DFFSX2TS R_2589 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .CK(clk), .SN(
n9074), .Q(n2513) );
DFFRX2TS R_2590 ( .D(n9948), .CK(clk), .RN(n9770), .Q(n2512) );
DFFRX2TS R_2591 ( .D(n9947), .CK(clk), .RN(n2868), .Q(n2511) );
DFFRX2TS R_2592 ( .D(n9942), .CK(clk), .RN(n2870), .Q(n2510) );
DFFSX2TS R_2593 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .CK(clk), .SN(
n9077), .Q(n2509) );
DFFRX2TS R_2594 ( .D(FPADDSUB_intDX_EWSW[15]), .CK(clk), .RN(n2857), .Q(
n2508) );
DFFSX2TS R_2595 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .CK(clk), .SN(
n6420), .Q(n2507) );
DFFSX2TS R_2596 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .CK(clk), .SN(
n9075), .Q(n2506) );
DFFRX2TS R_2597 ( .D(FPADDSUB_intDX_EWSW[1]), .CK(clk), .RN(n2871), .Q(n2505) );
DFFRX2TS R_2598 ( .D(FPADDSUB_intDX_EWSW[14]), .CK(clk), .RN(n2860), .Q(
n2504) );
DFFRX2TS R_2599 ( .D(FPADDSUB_intDX_EWSW[3]), .CK(clk), .RN(n2873), .Q(n2503) );
DFFRX2TS R_2600 ( .D(FPADDSUB_intDX_EWSW[13]), .CK(clk), .RN(n2926), .Q(
n2502) );
DFFRX2TS R_2601 ( .D(FPADDSUB_intDX_EWSW[11]), .CK(clk), .RN(n2870), .Q(
n2501) );
DFFRX2TS R_2602 ( .D(FPADDSUB_intDX_EWSW[0]), .CK(clk), .RN(n2879), .Q(n2500) );
DFFSX2TS R_2603 ( .D(FPMULT_Exp_module_Data_S_8_), .CK(clk), .SN(n2839), .Q(
n2499) );
DFFRX2TS R_2605 ( .D(FPADDSUB_intDX_EWSW[2]), .CK(clk), .RN(n2855), .Q(n2497) );
DFFRX2TS R_2606 ( .D(FPADDSUB_intDX_EWSW[23]), .CK(clk), .RN(n9759), .Q(
n2496) );
DFFRX2TS R_2607 ( .D(FPADDSUB_intDX_EWSW[9]), .CK(clk), .RN(n9756), .Q(n2495) );
DFFRX2TS R_2608 ( .D(add_x_69_n94), .CK(clk), .RN(n9076), .Q(n2494) );
DFFRX2TS R_2609 ( .D(FPADDSUB_intDX_EWSW[12]), .CK(clk), .RN(n2858), .Q(
n2493) );
DFFRX2TS R_2610 ( .D(FPADDSUB_intDY_EWSW[13]), .CK(clk), .RN(n2841), .Q(
n2492) );
DFFRX2TS R_2611 ( .D(FPADDSUB_intDY_EWSW[7]), .CK(clk), .RN(n9767), .Q(n2491) );
DFFRX2TS R_2612 ( .D(FPADDSUB_intDY_EWSW[10]), .CK(clk), .RN(n9763), .Q(
n2490) );
DFFRX2TS R_2613 ( .D(FPADDSUB_intDY_EWSW[2]), .CK(clk), .RN(n2866), .Q(n2489) );
DFFRX2TS R_2614 ( .D(FPADDSUB_intDX_EWSW[8]), .CK(clk), .RN(n2889), .Q(n2488) );
DFFRX2TS R_2615 ( .D(FPADDSUB_intDY_EWSW[5]), .CK(clk), .RN(n9768), .Q(n2487) );
DFFSX2TS R_2616 ( .D(DP_OP_499J248_125_1651_n228), .CK(clk), .SN(n8974), .Q(
n2486) );
DFFSX2TS R_2617 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[11]), .CK(clk), .SN(
n9522), .Q(n2485) );
DFFSX2TS R_2618 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .CK(clk), .SN(
n9074), .Q(n2484) );
DFFSX2TS R_2619 ( .D(n9748), .CK(clk), .SN(n9521), .Q(n2483), .QN(n2482) );
DFFSX2TS R_2620 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .CK(clk), .SN(
n9787), .Q(n2481) );
DFFSX2TS R_2621 ( .D(add_x_69_n283), .CK(clk), .SN(n9078), .Q(n2480) );
DFFSX2TS R_2622 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .CK(clk), .SN(
n9075), .Q(n2479) );
DFFSX2TS R_2623 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .CK(clk), .SN(
n9074), .Q(n2478) );
DFFSX2TS R_2624 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .CK(clk), .SN(
n9076), .Q(n2477) );
DFFSX2TS R_2625 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .CK(clk), .SN(
n9787), .Q(n2476) );
DFFRX2TS R_2626 ( .D(FPADDSUB_intDY_EWSW[15]), .CK(clk), .RN(n2869), .Q(
n2475) );
DFFRX2TS R_2627 ( .D(FPADDSUB_intDX_EWSW[21]), .CK(clk), .RN(n2861), .Q(
n2474) );
DFFSX2TS R_2628 ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]), .CK(clk), .SN(n9765),
.Q(n2473) );
DFFSX2TS R_2629 ( .D(n9514), .CK(clk), .SN(n2876), .Q(n2472) );
DFFRX2TS R_2630 ( .D(FPADDSUB_intDY_EWSW[4]), .CK(clk), .RN(n2853), .Q(n2471) );
DFFRX2TS R_2631 ( .D(FPADDSUB_intDY_EWSW[6]), .CK(clk), .RN(n8252), .Q(n2470) );
DFFRX2TS R_2632 ( .D(FPADDSUB_intDY_EWSW[16]), .CK(clk), .RN(n9766), .Q(
n2469) );
DFFRX2TS R_2633 ( .D(FPADDSUB_intDX_EWSW[20]), .CK(clk), .RN(n2855), .Q(
n2468) );
DFFRX2TS R_2635 ( .D(FPADDSUB_intDX_EWSW[17]), .CK(clk), .RN(n2881), .Q(
n2466) );
DFFRX2TS R_2636 ( .D(FPADDSUB_intDX_EWSW[25]), .CK(clk), .RN(n9517), .Q(
n2465) );
DFFRX2TS R_2637 ( .D(FPADDSUB_intDX_EWSW[26]), .CK(clk), .RN(n9518), .Q(
n2464) );
DFFRX2TS R_2638 ( .D(FPADDSUB_intDY_EWSW[24]), .CK(clk), .RN(n9517), .Q(
n2463) );
DFFRX2TS R_2639 ( .D(FPADDSUB_intDX_EWSW[22]), .CK(clk), .RN(n9759), .Q(
n2462) );
DFFRX2TS R_2640 ( .D(FPADDSUB_intDY_EWSW[27]), .CK(clk), .RN(n9517), .Q(
n2461) );
DFFRX2TS R_2641 ( .D(FPADDSUB_intDX_EWSW[10]), .CK(clk), .RN(n9766), .Q(
n2460) );
DFFRX2TS R_2642 ( .D(FPADDSUB_intDY_EWSW[19]), .CK(clk), .RN(n2847), .Q(
n2459) );
DFFRX2TS R_2643 ( .D(FPADDSUB_intDY_EWSW[14]), .CK(clk), .RN(n2859), .Q(
n2458) );
DFFRX2TS R_2644 ( .D(FPADDSUB_intDY_EWSW[12]), .CK(clk), .RN(n2857), .Q(
n2457) );
DFFRX2TS R_2645 ( .D(FPADDSUB_intDY_EWSW[3]), .CK(clk), .RN(n2872), .Q(n2456) );
DFFRX2TS R_2646 ( .D(FPADDSUB_intDX_EWSW[7]), .CK(clk), .RN(n2928), .Q(n2455) );
DFFRX2TS R_2647 ( .D(FPADDSUB_intDY_EWSW[23]), .CK(clk), .RN(n9759), .Q(
n2454) );
DFFRX2TS R_2648 ( .D(FPADDSUB_intDY_EWSW[1]), .CK(clk), .RN(n9770), .Q(n2453) );
DFFRX2TS R_2650 ( .D(FPADDSUB_intDY_EWSW[8]), .CK(clk), .RN(n2877), .Q(n2451) );
DFFRX2TS R_2651 ( .D(FPADDSUB_intDX_EWSW[19]), .CK(clk), .RN(n9760), .Q(
n2450) );
DFFRX2TS R_2652 ( .D(FPADDSUB_intDX_EWSW[24]), .CK(clk), .RN(n9518), .Q(
n2449) );
DFFRX2TS R_2653 ( .D(FPADDSUB_intDX_EWSW[27]), .CK(clk), .RN(n9518), .Q(
n2448) );
DFFRX2TS R_2654 ( .D(FPADDSUB_intDX_EWSW[16]), .CK(clk), .RN(n9761), .Q(
n2447) );
DFFRX2TS R_2655 ( .D(FPADDSUB_intDY_EWSW[21]), .CK(clk), .RN(n9755), .Q(
n2446) );
DFFRX2TS R_2656 ( .D(FPADDSUB_intDX_EWSW[4]), .CK(clk), .RN(n2853), .Q(n2445) );
DFFRX2TS R_2657 ( .D(FPADDSUB_intDY_EWSW[20]), .CK(clk), .RN(n2847), .Q(
n2444) );
DFFRX2TS R_2658 ( .D(FPADDSUB_intDY_EWSW[25]), .CK(clk), .RN(n9769), .Q(
n2443) );
DFFRX2TS R_2659 ( .D(FPADDSUB_intDY_EWSW[18]), .CK(clk), .RN(n2849), .Q(
n2442) );
DFFRX2TS R_2660 ( .D(FPADDSUB_intDY_EWSW[17]), .CK(clk), .RN(n2926), .Q(
n2441) );
DFFRX2TS R_2661 ( .D(FPADDSUB_intDY_EWSW[26]), .CK(clk), .RN(n2855), .Q(
n2440) );
DFFSX2TS R_2662 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .CK(clk), .SN(
n6441), .Q(n2439) );
DFFRX2TS R_2663 ( .D(n6220), .CK(clk), .RN(n9076), .Q(n2438) );
DFFSX2TS R_2664 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .CK(clk), .SN(
n6420), .Q(n2437) );
DFFSX2TS R_2665 ( .D(n3393), .CK(clk), .SN(n9519), .Q(n2436) );
DFFRX2TS R_2666 ( .D(FPADDSUB_intDY_EWSW[22]), .CK(clk), .RN(n9756), .Q(
n2435) );
DFFRX2TS R_2667 ( .D(FPADDSUB_intDX_EWSW[5]), .CK(clk), .RN(n2879), .Q(n2434) );
DFFSX2TS R_2668 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .CK(clk), .SN(
n6441), .Q(n2433) );
DFFRX2TS R_2669 ( .D(FPADDSUB_intDX_EWSW[6]), .CK(clk), .RN(n9755), .Q(n2432) );
DFFRX2TS R_2670 ( .D(FPADDSUB_intDY_EWSW[0]), .CK(clk), .RN(n2854), .Q(n2431) );
DFFSX2TS R_2671 ( .D(FPMULT_Sgf_operation_EVEN1_Q_right[23]), .CK(clk), .SN(
n9077), .Q(n2430) );
DFFSX2TS R_2672 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[19]), .CK(clk), .SN(
n6420), .Q(n2429) );
DFFSX2TS R_2673 ( .D(add_x_69_n76), .CK(clk), .SN(n9074), .Q(n2428) );
DFFSX2TS R_2674 ( .D(add_x_69_n85), .CK(clk), .SN(n9074), .Q(n2427) );
DFFRX4TS DP_OP_497J248_123_1725_R_2308 ( .D(n8906), .CK(clk), .RN(n8929),
.Q(DP_OP_497J248_123_1725_n599) );
DFFRX4TS R_2493 ( .D(n2577), .CK(clk), .RN(n9525), .Q(n2742) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2115), .CK(clk), .RN(n9775), .Q(
FPSENCOS_d_ff3_LUT_out[27]), .QN(n9289) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1782), .CK(clk), .RN(n9791), .Q(
FPSENCOS_d_ff_Zn[25]), .QN(n9449) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1773), .CK(clk), .RN(n9790), .Q(
FPSENCOS_d_ff_Zn[28]), .QN(n9446) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2009), .CK(clk), .RN(n9774), .Q(
FPSENCOS_d_ff_Yn[22]), .QN(n9347) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2021), .CK(clk), .RN(n9804), .Q(
FPSENCOS_d_ff_Yn[18]), .QN(n9360) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2018), .CK(clk), .RN(n9805), .Q(
FPSENCOS_d_ff_Yn[19]), .QN(n9361) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2024), .CK(clk), .RN(n9801), .Q(
FPSENCOS_d_ff_Yn[17]), .QN(n9356) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1897), .CK(clk), .RN(
n9781), .Q(FPSENCOS_d_ff2_Y[6]), .QN(n9415) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n9785), .Q(
FPSENCOS_d_ff_Xn[16]), .QN(n9281) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1889), .CK(clk), .RN(
n9803), .Q(FPSENCOS_d_ff2_Y[10]), .QN(n9422) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1847), .CK(clk), .RN(
n9797), .Q(FPSENCOS_d_ff2_Y[31]), .QN(n9432) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n9806), .Q(
FPSENCOS_d_ff_Xn[2]), .QN(n9283) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1907), .CK(clk), .RN(
n9808), .Q(FPSENCOS_d_ff2_Y[1]), .QN(n9430) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n9777), .Q(
FPSENCOS_d_ff_Xn[5]), .QN(n9279) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1525), .CK(
clk), .RN(n2886), .Q(FPMULT_Sgf_normalized_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1488), .CK(clk), .RN(n9822), .Q(mult_result[27]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1445), .CK(clk), .RN(
n9767), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n9764), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]), .QN(n9109) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n2926),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]), .QN(n9186) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n2861),
.Q(FPADDSUB_DMP_SFG[26]), .QN(n9505) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n9783), .Q(
FPSENCOS_d_ff_Xn[7]), .QN(n9291) );
DFFRX1TS add_x_69_R_1656_RW_1 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[7]), .CK(
clk), .RN(n9079), .Q(n9050) );
DFFRX1TS DP_OP_496J248_122_3540_R_1211 ( .D(n9000), .CK(clk), .RN(n9027),
.Q(DP_OP_496J248_122_3540_n829) );
DFFSX1TS R_1514 ( .D(n9855), .CK(clk), .SN(n9518), .Q(n9588) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1543), .CK(clk), .RN(
n2278), .Q(FPMULT_exp_oper_result[6]), .QN(n3687) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1854), .CK(clk), .RN(n9776),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1766), .CK(clk), .RN(
n9807), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1759), .CK(clk), .RN(
n9783), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS R_2574 ( .D(n9959), .CK(clk), .RN(n9766), .Q(n2528) );
DFFRXLTS R_2604 ( .D(FPADDSUB_intDY_EWSW[9]), .CK(clk), .RN(n2927), .Q(n2498) );
DFFRXLTS R_2634 ( .D(FPADDSUB_intDX_EWSW[18]), .CK(clk), .RN(n2866), .Q(
n2467) );
DFFRXLTS R_2649 ( .D(FPADDSUB_intDY_EWSW[11]), .CK(clk), .RN(n2868), .Q(
n2452) );
DFFRX4TS R_2519 ( .D(n2566), .CK(clk), .RN(n2885), .Q(n4344) );
DFFRX4TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1548), .CK(clk), .RN(
n2883), .Q(FPMULT_exp_oper_result[1]), .QN(n9210) );
DFFRX4TS DP_OP_498J248_124_1725_R_1850 ( .D(n8835), .CK(clk), .RN(n2863),
.Q(DP_OP_498J248_124_1725_n613) );
DFFRX4TS R_2536 ( .D(n2558), .CK(clk), .RN(n9820), .Q(n3950) );
DFFRX4TS DP_OP_498J248_124_1725_R_1645 ( .D(n8832), .CK(clk), .RN(n9028),
.Q(DP_OP_498J248_124_1725_n717) );
DFFSX2TS DP_OP_498J248_124_1725_R_1595 ( .D(n8831), .CK(clk), .SN(n6265),
.QN(n3583) );
DFFSX2TS add_x_254_R_2139 ( .D(add_x_254_SUM_22_), .CK(clk), .SN(n9786), .Q(
FPMULT_Sgf_operation_EVEN1_Q_right[22]), .QN(n3681) );
DFFRX4TS DP_OP_496J248_122_3540_R_1239 ( .D(n9003), .CK(clk), .RN(n9516),
.Q(DP_OP_496J248_122_3540_n1376) );
DFFSX4TS DP_OP_499J248_125_1651_R_2045_RW_1 ( .D(DP_OP_499J248_125_1651_n229), .CK(clk), .SN(n8976), .Q(n8971) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1321), .CK(clk), .RN(
n2841), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1412), .CK(clk), .RN(
n9754), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n9100) );
DFFRX4TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1317), .CK(clk), .RN(
n9769), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n9241) );
DFFRHQX2TS DP_OP_497J248_123_1725_R_1235 ( .D(n1649), .CK(clk), .RN(n2271),
.Q(n2602) );
DFFRHQX2TS DP_OP_498J248_124_1725_R_2327 ( .D(DP_OP_496J248_122_3540_n1475),
.CK(clk), .RN(n8852), .Q(n2813) );
DFFRHQX2TS DP_OP_497J248_123_1725_R_2144 ( .D(n1677), .CK(clk), .RN(n8929),
.Q(n2261) );
DFFRHQX2TS R_323 ( .D(n1631), .CK(clk), .RN(n9526), .Q(n2807) );
DFFSX2TS DP_OP_497J248_123_1725_R_1271 ( .D(n8886), .CK(clk), .SN(n2273),
.Q(DP_OP_497J248_123_1725_n374), .QN(n2652) );
DFFSHQX4TS DP_OP_497J248_123_1725_R_2377 ( .D(n8881), .CK(clk), .SN(n9532),
.Q(n2799) );
DFFRHQX2TS DP_OP_496J248_122_3540_R_498_IP ( .D(n2692), .CK(clk), .RN(n2796),
.Q(n9035) );
DFFRX2TS R_2496 ( .D(n2576), .CK(clk), .RN(n9820), .Q(n3092), .QN(n2317) );
DFFRX2TS DP_OP_496J248_122_3540_R_319 ( .D(n1671), .CK(clk), .RN(n9030), .Q(
DP_OP_496J248_122_3540_n1494) );
DFFSHQX1TS DP_OP_496J248_122_3540_R_2427_IP ( .D(n8871), .CK(clk), .SN(n9972), .Q(n9036) );
DFFSX2TS R_2587 ( .D(DP_OP_499J248_125_1651_n219), .CK(clk), .SN(n8976), .Q(
n2515) );
DFFSX2TS DP_OP_499J248_125_1651_R_2021_RW_1 ( .D(DP_OP_499J248_125_1651_n227), .CK(clk), .SN(n9519), .Q(n8966) );
DFFRHQX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1334), .CK(clk), .RN(
n2887), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFSX2TS DP_OP_499J248_125_1651_R_1916 ( .D(DP_OP_499J248_125_1651_n268),
.CK(clk), .SN(n8973), .Q(n8956) );
DFFSX1TS DP_OP_499J248_125_1651_R_1917 ( .D(n3384), .CK(clk), .SN(n8973),
.Q(n8957) );
DFFRX1TS DP_OP_499J248_125_1651_R_1154_RW_2 ( .D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .CK(clk),
.RN(n8975), .Q(n8939) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1333), .CK(clk), .RN(
n9771), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n9228) );
DFFSX1TS add_x_246_R_943 ( .D(n2898), .CK(clk), .SN(n9529), .Q(n9088) );
DFFSX1TS add_x_69_R_2031_RW_1 ( .D(n2633), .CK(clk), .SN(n9078), .Q(n9060)
);
DFFSX2TS add_x_246_R_806 ( .D(FPMULT_Sgf_normalized_result[22]), .CK(clk),
.SN(n9529), .Q(n9087) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n2833), .CK(clk),
.RN(n9813), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .QN(n9266)
);
DFFRX2TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1551), .CK(clk), .RN(n2863), .Q(
FPMULT_FSM_selector_B[0]), .QN(n9213) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1651), .CK(clk),
.RN(n9972), .Q(FPMULT_Op_MY[24]), .QN(n9209) );
DFFRX2TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1353), .CK(clk), .RN(n2862),
.Q(FPADDSUB_ADD_OVRFLW_NRM), .QN(n9234) );
DFFRX2TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1690), .CK(clk), .RN(n2278), .Q(
FPMULT_FSM_selector_C), .QN(n9219) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1684), .CK(clk),
.RN(n9515), .Q(FPMULT_Op_MX[25]), .QN(n9217) );
DFFSX4TS R_2554 ( .D(n2325), .CK(clk), .SN(n9521), .QN(n2196) );
DFFSX4TS R_2553 ( .D(n2325), .CK(clk), .SN(n9521), .QN(n2549) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1685), .CK(clk),
.RN(n9516), .Q(FPMULT_Op_MX[26]), .QN(n9224) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1933), .CK(clk), .RN(
n2859), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n3595) );
DFFRX2TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1545), .CK(clk), .RN(
n2886), .Q(FPMULT_exp_oper_result[4]), .QN(n3685) );
DFFRX2TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2137), .CK(clk), .RN(n9793),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n9481) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2146), .CK(clk), .RN(
n9772), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n2648) );
DFFRX2TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n9797), .Q(
dataA[27]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1813), .CK(clk), .RN(n2878), .Q(FPADDSUB_Data_array_SWR[24]), .QN(n9249) );
DFFRX2TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1860), .CK(clk), .RN(
n9788), .Q(FPSENCOS_d_ff2_Y[26]) );
DFFRX2TS R_2290 ( .D(DP_OP_498J248_124_1725_n796), .CK(clk), .RN(n9527),
.QN(n9456) );
DFFRX2TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1544), .CK(clk), .RN(
n2278), .Q(FPMULT_exp_oper_result[5]), .QN(n3686) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1958), .CK(clk), .RN(
n9789), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRHQX1TS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n9971), .Q(
dataA[31]) );
DFFRHQX1TS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1405), .CK(clk),
.RN(n2887), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRX1TS R_497 ( .D(n1665), .CK(clk), .RN(n9528), .QN(n9714) );
DFFRX1TS R_1648 ( .D(n1627), .CK(clk), .RN(n2863), .QN(n9687) );
DFFRX1TS R_1288 ( .D(n1628), .CK(clk), .RN(n2884), .QN(n9644) );
DFFRX2TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n9797),
.Q(operation_reg_0_) );
DFFRX2TS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n9798), .Q(
dataB[29]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1696), .CK(clk),
.RN(n9516), .Q(FPMULT_Op_MY[31]), .QN(n9479) );
DFFRX2TS R_675 ( .D(n2335), .CK(clk), .RN(n9530), .QN(n9457) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1688), .CK(clk),
.RN(n9516), .QN(n9693) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1689), .CK(clk),
.RN(n9516), .QN(n9695) );
DFFRX2TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(clk), .RN(n9772), .Q(ready_add_subt), .QN(n9461) );
DFFRXLTS R_1331 ( .D(n1605), .CK(clk), .RN(n2886), .Q(n9638) );
DFFRX1TS R_1203 ( .D(n1630), .CK(clk), .RN(n9821), .QN(n9747) );
DFFRX1TS R_2325 ( .D(DP_OP_496J248_122_3540_n1475), .CK(clk), .RN(n9531),
.QN(n9688) );
DFFRX2TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1619), .CK(clk), .RN(
n2886), .Q(FPMULT_Add_result[5]), .QN(n9145) );
DFFRXLTS R_1854 ( .D(n1414), .CK(clk), .RN(n2869), .Q(n9563) );
DFFSX1TS R_2400 ( .D(n9847), .CK(clk), .SN(n2889), .Q(n9534) );
DFFRX4TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n2867),
.Q(FPADDSUB_OP_FLAG_SFG), .QN(n9121) );
DFFSHQX1TS reg_dataB_Q_reg_27_ ( .D(n9837), .CK(clk), .SN(n2911), .Q(n9298)
);
DFFSRHQX2TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1618), .CK(clk),
.SN(1'b1), .RN(n9972), .Q(FPMULT_Add_result[6]) );
DFFRXLTS R_1996 ( .D(FPADDSUB_intDY_EWSW[28]), .CK(clk), .RN(n9770), .Q(
n9551) );
DFFRXLTS R_1914 ( .D(FPADDSUB_intDX_EWSW[28]), .CK(clk), .RN(n2847), .Q(
n9556) );
DFFRXLTS R_2082 ( .D(FPADDSUB_intDY_EWSW[30]), .CK(clk), .RN(n2861), .Q(
n9548) );
DFFRXLTS R_2094 ( .D(FPADDSUB_intDY_EWSW[29]), .CK(clk), .RN(n9755), .Q(
n9547) );
DFFRXLTS add_x_246_R_405 ( .D(n1517), .CK(clk), .RN(n2883), .Q(
add_x_246_A_0_), .QN(n9092) );
DFFRHQX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1468), .CK(clk), .RN(
n2887), .Q(n8797) );
DFFSHQX1TS R_1171 ( .D(n9653), .CK(clk), .SN(n9971), .Q(n9967) );
DFFRHQX2TS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2129), .CK(clk), .RN(n2911), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRHQX2TS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1875), .CK(clk),
.RN(n2911), .Q(FPSENCOS_d_ff2_Y[17]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2131), .CK(clk), .RN(n9809), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2125), .CK(clk), .RN(n9803), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRX1TS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1951), .CK(clk), .RN(n9776),
.Q(FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRX1TS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1952), .CK(clk), .RN(n9776),
.Q(FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n9807), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2123), .CK(clk), .RN(n9802), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1856), .CK(clk), .RN(
n2843), .Q(FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1954), .CK(clk), .RN(
n9789), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1612), .CK(clk),
.RN(n6440), .Q(FPMULT_Add_result[12]), .QN(n9255) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1611), .CK(clk),
.RN(n9819), .Q(FPMULT_Add_result[13]), .QN(n9254) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1610), .CK(clk),
.RN(n9819), .Q(FPMULT_Add_result[14]), .QN(n9253) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1607), .CK(clk),
.RN(n9819), .Q(FPMULT_Add_result[17]), .QN(n9250) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1614), .CK(clk),
.RN(n9819), .Q(FPMULT_Add_result[10]), .QN(n9257) );
DFFRX2TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1609), .CK(clk),
.RN(n9819), .Q(FPMULT_Add_result[15]), .QN(n9252) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n2926),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]), .QN(n9182) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n2887),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]), .QN(n9183) );
DFFSRHQX2TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1360), .CK(clk), .SN(
1'b1), .RN(n2889), .Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1608), .CK(clk),
.RN(n9819), .Q(FPMULT_Add_result[16]), .QN(n9251) );
CLKBUFX3TS U2219 ( .A(n6265), .Y(n2913) );
CLKBUFX3TS U2220 ( .A(n6265), .Y(n2912) );
CLKMX2X2TS U2221 ( .A(n8773), .B(FPMULT_P_Sgf[1]), .S0(n9751), .Y(n9243) );
CLKINVX1TS U2222 ( .A(n2269), .Y(n2272) );
CLKINVX1TS U2223 ( .A(n2269), .Y(n2271) );
CLKINVX1TS U2224 ( .A(n2269), .Y(n2273) );
CLKINVX2TS U2225 ( .A(n2274), .Y(n2275) );
CLKINVX3TS U2226 ( .A(n2882), .Y(n2884) );
CLKINVX2TS U2227 ( .A(n2277), .Y(n2279) );
CLKINVX2TS U2228 ( .A(n2266), .Y(n2267) );
CLKINVX3TS U2229 ( .A(n2288), .Y(n2289) );
INVX2TS U2230 ( .A(n2288), .Y(n2290) );
NAND2X6TS U2231 ( .A(n6179), .B(n6178), .Y(DP_OP_499J248_125_1651_n105) );
INVX2TS U2232 ( .A(n2274), .Y(n2276) );
INVX2TS U2233 ( .A(n2266), .Y(n2268) );
INVX2TS U2234 ( .A(n2277), .Y(n2278) );
CLKBUFX3TS U2235 ( .A(n6440), .Y(n9532) );
CLKBUFX3TS U2236 ( .A(n6265), .Y(n8929) );
CLKINVX1TS U2237 ( .A(n2291), .Y(n2292) );
NAND2X1TS U2238 ( .A(n8131), .B(n7220), .Y(n7105) );
BUFX3TS U2239 ( .A(n6440), .Y(n9821) );
INVX2TS U2240 ( .A(n6300), .Y(n6305) );
NAND2X1TS U2241 ( .A(n7308), .B(n7253), .Y(n7162) );
INVX2TS U2242 ( .A(n6418), .Y(n6084) );
INVX2TS U2243 ( .A(n7740), .Y(n9905) );
NOR2X1TS U2244 ( .A(n9248), .B(n6421), .Y(n6433) );
NOR2X1TS U2245 ( .A(n9700), .B(n6282), .Y(n8862) );
BUFX4TS U2246 ( .A(n6635), .Y(n8666) );
NAND2X1TS U2247 ( .A(n6343), .B(n6342), .Y(n6344) );
INVX2TS U2248 ( .A(n1663), .Y(n8814) );
NAND2X1TS U2249 ( .A(n8071), .B(n1582), .Y(n7477) );
NOR2X1TS U2250 ( .A(n7324), .B(n7043), .Y(n4846) );
INVX3TS U2251 ( .A(n8431), .Y(n8412) );
INVX3TS U2252 ( .A(n8431), .Y(n8423) );
INVX3TS U2253 ( .A(n8431), .Y(n8441) );
NAND2X2TS U2254 ( .A(n8217), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n7696) );
INVX4TS U2255 ( .A(n6419), .Y(n6417) );
INVX2TS U2256 ( .A(n8431), .Y(n8438) );
NAND2XLTS U2257 ( .A(n7317), .B(n7082), .Y(n7083) );
INVX2TS U2258 ( .A(n8460), .Y(n8466) );
NAND2X1TS U2259 ( .A(n8131), .B(n8128), .Y(n7221) );
NAND2X1TS U2260 ( .A(n8131), .B(n7226), .Y(n7227) );
NAND2X1TS U2261 ( .A(n7329), .B(n7316), .Y(n7249) );
NAND2X1TS U2262 ( .A(n8131), .B(n7309), .Y(n7310) );
NAND2X1TS U2263 ( .A(n8131), .B(n8130), .Y(n8132) );
NAND2X1TS U2264 ( .A(n8131), .B(n7318), .Y(n7319) );
NAND2X1TS U2265 ( .A(n7329), .B(n7328), .Y(n7330) );
NAND2X6TS U2266 ( .A(n6003), .B(n6242), .Y(add_x_69_n291) );
NAND2X1TS U2267 ( .A(n2335), .B(n9683), .Y(n6414) );
NAND2XLTS U2268 ( .A(n9752), .B(FPMULT_P_Sgf[13]), .Y(n3217) );
OA21XLTS U2269 ( .A0(n8337), .A1(n8336), .B0(n8335), .Y(n8338) );
OR2X4TS U2270 ( .A(n1521), .B(n9083), .Y(n6439) );
CLKBUFX3TS U2271 ( .A(n6992), .Y(n7475) );
NAND2XLTS U2272 ( .A(n8129), .B(n7225), .Y(n7015) );
NAND2XLTS U2273 ( .A(n7760), .B(n1585), .Y(n7491) );
NAND2XLTS U2274 ( .A(n8761), .B(FPMULT_P_Sgf[8]), .Y(n3020) );
CLKBUFX3TS U2275 ( .A(n8460), .Y(n8461) );
BUFX3TS U2276 ( .A(n7811), .Y(n8384) );
BUFX3TS U2277 ( .A(n7811), .Y(n6540) );
BUFX3TS U2278 ( .A(n7811), .Y(n6531) );
BUFX3TS U2279 ( .A(n7811), .Y(n6526) );
BUFX3TS U2280 ( .A(n8554), .Y(n8582) );
INVX4TS U2281 ( .A(add_x_69_n104), .Y(n6017) );
NAND2XLTS U2282 ( .A(n6393), .B(n6392), .Y(n6394) );
INVX2TS U2283 ( .A(n8460), .Y(n6617) );
AOI2BB2X2TS U2284 ( .B0(n7759), .B1(n1588), .A0N(n2916), .A1N(n9256), .Y(
n7762) );
NAND2X4TS U2285 ( .A(n2753), .B(n2751), .Y(n3465) );
NAND2BXLTS U2286 ( .AN(n3054), .B(n3321), .Y(n6369) );
AOI2BB2X2TS U2287 ( .B0(n7317), .B1(n7241), .A0N(n7324), .A1N(n7240), .Y(
n7244) );
INVX2TS U2288 ( .A(n9820), .Y(n2288) );
INVX2TS U2289 ( .A(n8853), .Y(n2266) );
INVX2TS U2290 ( .A(n2838), .Y(n2277) );
INVX2TS U2291 ( .A(n8851), .Y(n2291) );
INVX2TS U2292 ( .A(n9031), .Y(n2274) );
INVX2TS U2293 ( .A(n8928), .Y(n2269) );
NAND2X2TS U2294 ( .A(n8105), .B(n2630), .Y(n8106) );
CLKINVX6TS U2295 ( .A(n8568), .Y(n8545) );
CLKINVX1TS U2296 ( .A(n2622), .Y(n2202) );
BUFX6TS U2297 ( .A(n8326), .Y(n6675) );
INVX1TS U2298 ( .A(n6371), .Y(n6373) );
BUFX3TS U2299 ( .A(n7547), .Y(n7652) );
BUFX3TS U2300 ( .A(n7547), .Y(n8189) );
BUFX3TS U2301 ( .A(n7547), .Y(n7684) );
BUFX3TS U2302 ( .A(n7547), .Y(n8176) );
BUFX3TS U2303 ( .A(n7547), .Y(n8219) );
CLKINVX6TS U2304 ( .A(n7011), .Y(n7308) );
NAND2X2TS U2305 ( .A(n5757), .B(n5756), .Y(n6377) );
NAND2X4TS U2306 ( .A(n5959), .B(n5958), .Y(n6206) );
CLKINVX6TS U2307 ( .A(n8238), .Y(n8789) );
INVX2TS U2308 ( .A(n6173), .Y(n6175) );
INVX2TS U2309 ( .A(n8301), .Y(n8080) );
AND4X1TS U2310 ( .A(n8713), .B(n8699), .C(n7893), .D(n7892), .Y(n7894) );
NAND2X4TS U2311 ( .A(n5811), .B(n5810), .Y(n6155) );
BUFX4TS U2312 ( .A(n8141), .Y(n8227) );
BUFX4TS U2313 ( .A(n8141), .Y(n8667) );
INVX8TS U2314 ( .A(n6243), .Y(add_x_69_n95) );
NAND2X1TS U2315 ( .A(n8093), .B(n1581), .Y(n6436) );
INVX2TS U2316 ( .A(n5960), .Y(n2622) );
NOR2X4TS U2317 ( .A(n9121), .B(n8703), .Y(n6992) );
CLKAND2X2TS U2318 ( .A(n3642), .B(n6240), .Y(n5818) );
NAND2X1TS U2319 ( .A(n6312), .B(n2670), .Y(n6314) );
NAND2X2TS U2320 ( .A(n2634), .B(n8102), .Y(n2753) );
CLKBUFX2TS U2321 ( .A(n9817), .Y(n9031) );
CLKBUFX3TS U2322 ( .A(n2687), .Y(n7322) );
AOI21X1TS U2323 ( .A0(n6297), .A1(n6296), .B0(n6295), .Y(n6299) );
CLKBUFX2TS U2324 ( .A(n9529), .Y(n8928) );
XNOR2X1TS U2325 ( .A(n6081), .B(n6080), .Y(n6354) );
CLKBUFX2TS U2326 ( .A(n9818), .Y(n8853) );
AOI22X1TS U2327 ( .A0(n7101), .A1(FPADDSUB_Raw_mant_NRM_SWR[1]), .B0(n8340),
.B1(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n7089) );
NAND2X4TS U2328 ( .A(n6218), .B(n3482), .Y(n3424) );
NOR2X6TS U2329 ( .A(n3305), .B(n3057), .Y(n3056) );
CLKBUFX3TS U2330 ( .A(n7038), .Y(n7234) );
NAND2X6TS U2331 ( .A(n8103), .B(n3180), .Y(n3451) );
INVX2TS U2332 ( .A(n2892), .Y(n2838) );
BUFX12TS U2333 ( .A(n7044), .Y(n7329) );
NOR2X2TS U2334 ( .A(n6076), .B(n2669), .Y(n6355) );
CLKINVX1TS U2335 ( .A(n6205), .Y(n3447) );
INVX4TS U2336 ( .A(n6005), .Y(n2623) );
NAND2X2TS U2337 ( .A(n3204), .B(n3440), .Y(n3203) );
OR2X4TS U2338 ( .A(n8098), .B(n8097), .Y(n8100) );
NAND2X4TS U2339 ( .A(n2788), .B(n2786), .Y(n2785) );
CLKINVX2TS U2340 ( .A(n2235), .Y(n6313) );
BUFX3TS U2341 ( .A(n8291), .Y(n8286) );
INVX2TS U2342 ( .A(n8295), .Y(n8269) );
NOR2X1TS U2343 ( .A(n8781), .B(n8594), .Y(n6639) );
INVX6TS U2344 ( .A(n2327), .Y(add_x_69_n113) );
BUFX3TS U2345 ( .A(n2298), .Y(n6558) );
AND4X1TS U2346 ( .A(n9201), .B(n8474), .C(n9707), .D(n9708), .Y(n8478) );
INVX2TS U2347 ( .A(n7129), .Y(n7070) );
AND4X1TS U2348 ( .A(n9458), .B(n9709), .C(n9710), .D(n9711), .Y(n8481) );
AND4X1TS U2349 ( .A(n9456), .B(n9690), .C(n9689), .D(n9691), .Y(n8479) );
AND4X1TS U2350 ( .A(n9704), .B(n9705), .C(n9706), .D(n2942), .Y(n8471) );
AND4X1TS U2351 ( .A(n9457), .B(n9698), .C(n9699), .D(n9697), .Y(n8480) );
NAND3X1TS U2352 ( .A(n2561), .B(n2560), .C(n2559), .Y(n1533) );
INVX2TS U2353 ( .A(n6244), .Y(n3506) );
INVX4TS U2354 ( .A(n5814), .Y(n5978) );
AND4X1TS U2355 ( .A(n9642), .B(n9467), .C(n9641), .D(n9643), .Y(n8486) );
NAND2X1TS U2356 ( .A(n6857), .B(n7259), .Y(n7300) );
CLKMX2X2TS U2357 ( .A(n4694), .B(n9717), .S0(n2543), .Y(n1602) );
INVX4TS U2358 ( .A(n3702), .Y(n8075) );
INVX2TS U2359 ( .A(n5801), .Y(n6076) );
NAND2X1TS U2360 ( .A(n1666), .B(n9701), .Y(n8854) );
NAND2XLTS U2361 ( .A(n8093), .B(n1580), .Y(n4982) );
AND4X1TS U2362 ( .A(n9460), .B(n2808), .C(n9687), .D(n9688), .Y(n8476) );
INVX4TS U2363 ( .A(n6086), .Y(n6088) );
INVX4TS U2364 ( .A(n3204), .Y(n2630) );
AO21XLTS U2365 ( .A0(n8387), .A1(r_mode[0]), .B0(r_mode[1]), .Y(n3623) );
INVX2TS U2366 ( .A(n6090), .Y(n3305) );
CLKBUFX2TS U2367 ( .A(n3294), .Y(n2235) );
NAND2X2TS U2368 ( .A(n8692), .B(n6614), .Y(n9843) );
NAND3X1TS U2369 ( .A(n7097), .B(n7096), .C(n7095), .Y(n7208) );
NAND2X6TS U2370 ( .A(n8105), .B(n8103), .Y(n3353) );
INVX4TS U2371 ( .A(n3632), .Y(n9685) );
NAND3X1TS U2372 ( .A(n4836), .B(n4835), .C(n4834), .Y(n7045) );
NAND3X1TS U2373 ( .A(n6926), .B(n6925), .C(n6924), .Y(n7253) );
NAND2X4TS U2374 ( .A(n8098), .B(n8097), .Y(n8099) );
NAND3X1TS U2375 ( .A(n8336), .B(n7161), .C(n7160), .Y(n7316) );
NAND3X1TS U2376 ( .A(n7111), .B(n7110), .C(n7109), .Y(n7263) );
BUFX3TS U2377 ( .A(n9531), .Y(n6265) );
NAND2X4TS U2378 ( .A(n3297), .B(n3462), .Y(n2788) );
NAND2BXLTS U2379 ( .AN(n1601), .B(FPMULT_FSM_selector_C), .Y(n2203) );
CLKXOR2X2TS U2380 ( .A(n6001), .B(n6000), .Y(n6003) );
CLKXOR2X2TS U2381 ( .A(n4960), .B(n3075), .Y(n6205) );
NAND2X6TS U2382 ( .A(n3171), .B(n3321), .Y(n2209) );
INVX2TS U2383 ( .A(n5819), .Y(n5821) );
NAND2X1TS U2384 ( .A(n6329), .B(n6328), .Y(n6396) );
NAND2X1TS U2385 ( .A(n6335), .B(n6334), .Y(n6392) );
NOR2X1TS U2386 ( .A(n6210), .B(n6211), .Y(n6320) );
NAND2X1TS U2387 ( .A(n6323), .B(n6322), .Y(n6404) );
NAND2X1TS U2388 ( .A(n9838), .B(n6182), .Y(n8693) );
NAND2X1TS U2389 ( .A(n6211), .B(n6210), .Y(n6319) );
NAND2XLTS U2390 ( .A(n5790), .B(n5789), .Y(n5791) );
NAND2X1TS U2391 ( .A(n6324), .B(n6325), .Y(n6408) );
OAI21X2TS U2392 ( .A0(n5956), .A1(n5957), .B0(n5955), .Y(n3117) );
NAND2XLTS U2393 ( .A(n5839), .B(n5836), .Y(n4960) );
NOR2X1TS U2394 ( .A(n6333), .B(n6332), .Y(n6381) );
INVX6TS U2395 ( .A(n5991), .Y(n2327) );
CLKMX2X2TS U2396 ( .A(n6019), .B(n9725), .S0(n2521), .Y(n1601) );
NAND2X4TS U2397 ( .A(n5808), .B(n5809), .Y(n6090) );
OAI2BB2XLTS U2398 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n7856), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n3651), .Y(n7867) );
NAND3X1TS U2399 ( .A(n2556), .B(n2555), .C(n2554), .Y(n1532) );
NOR2X6TS U2400 ( .A(n5677), .B(n5678), .Y(n6086) );
CLKMX2X4TS U2401 ( .A(n6270), .B(n2937), .S0(n8445), .Y(n3632) );
NAND2X6TS U2402 ( .A(n5678), .B(n5677), .Y(n3309) );
NAND2X2TS U2403 ( .A(n5887), .B(n5886), .Y(n6308) );
INVX2TS U2404 ( .A(n5912), .Y(n3226) );
AND4X1TS U2405 ( .A(n8635), .B(n8548), .C(n8550), .D(n8552), .Y(n7734) );
NAND2X6TS U2406 ( .A(n2229), .B(n5634), .Y(n5979) );
CLKBUFX2TS U2407 ( .A(n6054), .Y(n2255) );
NOR2X2TS U2408 ( .A(n6322), .B(n6323), .Y(n6405) );
BUFX3TS U2409 ( .A(n3482), .Y(n3462) );
INVX4TS U2410 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .Y(n6302) );
NAND2X1TS U2411 ( .A(n8093), .B(n1579), .Y(n4994) );
NAND2XLTS U2412 ( .A(n7754), .B(n7753), .Y(n7755) );
INVX4TS U2413 ( .A(n3700), .Y(n2908) );
CLKINVX1TS U2414 ( .A(n6181), .Y(n5776) );
NAND2X1TS U2415 ( .A(n6599), .B(n8440), .Y(n6605) );
INVX2TS U2416 ( .A(n8386), .Y(n9969) );
INVX1TS U2417 ( .A(n6654), .Y(n6655) );
INVX12TS U2418 ( .A(n2632), .Y(n2368) );
NAND2X1TS U2419 ( .A(n6333), .B(n6332), .Y(n6385) );
INVX4TS U2420 ( .A(n8091), .Y(n2915) );
BUFX12TS U2421 ( .A(n8507), .Y(n8675) );
NAND2X1TS U2422 ( .A(n6077), .B(n6349), .Y(n6352) );
NAND2XLTS U2423 ( .A(n7282), .B(n7281), .Y(n7283) );
NAND2XLTS U2424 ( .A(n3841), .B(n4759), .Y(n3842) );
AND2X2TS U2425 ( .A(n8692), .B(n6591), .Y(n8460) );
NAND2XLTS U2426 ( .A(n6141), .B(n6140), .Y(n6008) );
NAND2XLTS U2427 ( .A(n5999), .B(n5998), .Y(n6000) );
INVX2TS U2428 ( .A(n3440), .Y(n3679) );
NAND2X6TS U2429 ( .A(n5541), .B(n3171), .Y(n3274) );
NAND2XLTS U2430 ( .A(n7741), .B(n7744), .Y(n7505) );
NAND2X2TS U2431 ( .A(FPSENCOS_cont_var_out[0]), .B(FPSENCOS_cont_var_out[1]),
.Y(n8757) );
INVX3TS U2432 ( .A(n4837), .Y(n4839) );
AOI211X1TS U2433 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n3591), .B0(n7819),
.C0(n7817), .Y(n7870) );
NOR2X1TS U2434 ( .A(n8389), .B(n8382), .Y(n6594) );
NAND2XLTS U2435 ( .A(n7291), .B(n7290), .Y(n7292) );
BUFX6TS U2436 ( .A(n2899), .Y(n8703) );
CLKXOR2X2TS U2437 ( .A(n2845), .B(n6422), .Y(n7897) );
ADDFHX2TS U2438 ( .A(n5769), .B(n5768), .CI(n5767), .CO(n5770), .S(n5759) );
INVX2TS U2439 ( .A(n7273), .Y(n7166) );
OAI21X2TS U2440 ( .A0(n2329), .A1(n5983), .B0(n5982), .Y(n5988) );
CLKMX2X2TS U2441 ( .A(n2499), .B(n9585), .S0(n9584), .Y(n1541) );
INVX6TS U2442 ( .A(n2646), .Y(n7055) );
BUFX6TS U2443 ( .A(n5635), .Y(n2229) );
NOR2X1TS U2444 ( .A(n3712), .B(n9463), .Y(n3713) );
NOR2X1TS U2445 ( .A(n3646), .B(FPADDSUB_intDX_EWSW[30]), .Y(n7819) );
INVX4TS U2446 ( .A(n2584), .Y(n6053) );
NAND2X4TS U2447 ( .A(n3390), .B(n3441), .Y(n3508) );
NAND2X1TS U2448 ( .A(n7760), .B(n1578), .Y(n5009) );
NOR2X1TS U2449 ( .A(n6127), .B(n2514), .Y(n6120) );
NAND2X1TS U2450 ( .A(n6185), .B(n6099), .Y(n6130) );
NAND2X1TS U2451 ( .A(n8071), .B(n1577), .Y(n5020) );
NAND2XLTS U2452 ( .A(n9268), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]),
.Y(n3714) );
INVX2TS U2453 ( .A(n3416), .Y(n5153) );
NAND2X1TS U2454 ( .A(n6200), .B(n6199), .Y(n8294) );
NAND2X2TS U2455 ( .A(n4648), .B(n5152), .Y(n3169) );
CLKINVX6TS U2456 ( .A(n6247), .Y(n9701) );
NOR2X2TS U2457 ( .A(n6126), .B(n2514), .Y(n6121) );
INVX4TS U2458 ( .A(n7260), .Y(n7156) );
INVX4TS U2459 ( .A(n2938), .Y(n2940) );
MXI2X2TS U2460 ( .A(n8531), .B(n9456), .S0(n6260), .Y(
DP_OP_498J248_124_1725_n796) );
NOR2BX2TS U2461 ( .AN(n7743), .B(n2329), .Y(n2732) );
NAND2X6TS U2462 ( .A(n4321), .B(n4320), .Y(n6004) );
NAND2X2TS U2463 ( .A(n3728), .B(n3727), .Y(n8300) );
NOR2X4TS U2464 ( .A(n5887), .B(n5886), .Y(n6307) );
NAND2X2TS U2465 ( .A(n6002), .B(n2250), .Y(n3315) );
CLKINVX6TS U2466 ( .A(n8091), .Y(n2916) );
AND2X4TS U2467 ( .A(n8708), .B(n4829), .Y(n4837) );
INVX4TS U2468 ( .A(n5995), .Y(n3261) );
NAND2XLTS U2469 ( .A(n5161), .B(n5165), .Y(n5162) );
NAND2XLTS U2470 ( .A(n6012), .B(n6011), .Y(n6014) );
XOR2X1TS U2471 ( .A(n6653), .B(n9103), .Y(n6654) );
INVX4TS U2472 ( .A(n2687), .Y(n7264) );
AOI21X2TS U2473 ( .A0(n7749), .A1(n7490), .B0(n3825), .Y(n3826) );
NAND2XLTS U2474 ( .A(n9267), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]),
.Y(n3708) );
NAND2X4TS U2475 ( .A(n2901), .B(n6111), .Y(n6114) );
NAND2X1TS U2476 ( .A(n8594), .B(n6633), .Y(n6678) );
NOR2X2TS U2477 ( .A(n7729), .B(n8710), .Y(n7730) );
OAI2BB2XLTS U2478 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n7835), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n3635), .Y(n7847) );
NOR2X1TS U2479 ( .A(n3660), .B(FPADDSUB_DMP_SFG[22]), .Y(n7396) );
NAND2X1TS U2480 ( .A(n6215), .B(n6214), .Y(n6357) );
NAND2X1TS U2481 ( .A(n8774), .B(FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n4809) );
NOR2X6TS U2482 ( .A(n5537), .B(n5538), .Y(n6368) );
BUFX8TS U2483 ( .A(n3263), .Y(n3091) );
INVX2TS U2484 ( .A(n7742), .Y(n7501) );
NOR2X1TS U2485 ( .A(n3726), .B(n9270), .Y(n3727) );
OR2X2TS U2486 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n7426) );
INVX6TS U2487 ( .A(n3094), .Y(n3317) );
NOR2X2TS U2488 ( .A(n6184), .B(n6021), .Y(n4780) );
OAI21X1TS U2489 ( .A0(FPMULT_FSM_selector_B[1]), .A1(n9221), .B0(n6429), .Y(
n6424) );
NAND2XLTS U2490 ( .A(n8378), .B(n2464), .Y(n6597) );
INVX2TS U2491 ( .A(n6315), .Y(n5867) );
NAND2X2TS U2492 ( .A(n4648), .B(n5150), .Y(n4690) );
INVX3TS U2493 ( .A(n4767), .Y(n7749) );
ADDFHX2TS U2494 ( .A(n5739), .B(n5738), .CI(n5737), .CO(n5740), .S(n5802) );
OR2X2TS U2495 ( .A(n5276), .B(n2330), .Y(n6238) );
NAND2X1TS U2496 ( .A(n5949), .B(n6062), .Y(n5950) );
NOR2X2TS U2497 ( .A(FPSENCOS_cont_iter_out[1]), .B(FPSENCOS_cont_iter_out[3]), .Y(n6633) );
INVX4TS U2498 ( .A(n8301), .Y(n8089) );
MX2X4TS U2499 ( .A(n4993), .B(n9722), .S0(n2287), .Y(n1579) );
NOR2X6TS U2500 ( .A(n2774), .B(n5793), .Y(n2773) );
INVX6TS U2501 ( .A(n5019), .Y(n8092) );
XOR2X2TS U2502 ( .A(n5901), .B(n5900), .Y(n5932) );
INVX4TS U2503 ( .A(n5019), .Y(n8083) );
CMPR32X2TS U2504 ( .A(n5745), .B(n5744), .C(n5743), .CO(n5760), .S(n5753) );
CLKXOR2X2TS U2505 ( .A(n6236), .B(n4313), .Y(n4322) );
INVX6TS U2506 ( .A(n5177), .Y(n3423) );
CLKMX2X4TS U2507 ( .A(n6701), .B(n9718), .S0(n2287), .Y(n1575) );
INVX8TS U2508 ( .A(n4757), .Y(n7743) );
NAND4BX1TS U2509 ( .AN(n8698), .B(n7727), .C(n7726), .D(n7725), .Y(n7729) );
AOI21X1TS U2510 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n8123), .B0(
n7101), .Y(n4829) );
NAND2X1TS U2511 ( .A(n2239), .B(n5170), .Y(n6347) );
INVX2TS U2512 ( .A(n4302), .Y(n3084) );
NAND2X1TS U2513 ( .A(FPSENCOS_cont_iter_out[1]), .B(
FPSENCOS_cont_iter_out[0]), .Y(n8306) );
NAND2X1TS U2514 ( .A(n3671), .B(FPADDSUB_DMP_SFG[3]), .Y(n6828) );
NAND2X1TS U2515 ( .A(n9475), .B(FPADDSUB_DMP_SFG[11]), .Y(n7020) );
INVX6TS U2516 ( .A(n6185), .Y(n6007) );
OR2X2TS U2517 ( .A(n2239), .B(n5170), .Y(n6349) );
NOR2X2TS U2518 ( .A(n6984), .B(n6978), .Y(n6962) );
NAND2X1TS U2519 ( .A(n4779), .B(n2539), .Y(n4770) );
NAND2XLTS U2520 ( .A(n8378), .B(n2440), .Y(n6532) );
AND2X4TS U2521 ( .A(n4776), .B(n6030), .Y(n8091) );
NOR2X2TS U2522 ( .A(sub_x_17_n251), .B(FPADDSUB_DMP_SFG[1]), .Y(n6792) );
NAND2XLTS U2523 ( .A(n4978), .B(n4977), .Y(n4979) );
INVX4TS U2524 ( .A(n7260), .Y(n7101) );
XNOR2X2TS U2525 ( .A(n5749), .B(n5748), .Y(n6298) );
INVX4TS U2526 ( .A(n2640), .Y(n3174) );
NAND2XLTS U2527 ( .A(n4312), .B(n4325), .Y(n4313) );
BUFX3TS U2528 ( .A(n7212), .Y(n8123) );
NOR2X2TS U2529 ( .A(n6059), .B(n6064), .Y(n6067) );
OAI21X1TS U2530 ( .A0(FPMULT_FSM_selector_B[1]), .A1(n9222), .B0(n6429), .Y(
n6425) );
INVX4TS U2531 ( .A(n2196), .Y(n2287) );
INVX4TS U2532 ( .A(n2549), .Y(n2296) );
OR2X2TS U2533 ( .A(n5731), .B(n5730), .Y(n5745) );
CLKINVX3TS U2534 ( .A(n7498), .Y(n7742) );
NOR2X1TS U2535 ( .A(n5164), .B(n5167), .Y(n6077) );
NAND2X1TS U2536 ( .A(n5948), .B(n5947), .Y(n6062) );
NAND2X1TS U2537 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n7378) );
OAI21X2TS U2538 ( .A0(n5167), .A1(n5166), .B0(n5165), .Y(n6350) );
NOR2X2TS U2539 ( .A(n5948), .B(n5947), .Y(n6064) );
INVX2TS U2540 ( .A(n6060), .Y(n5943) );
INVX4TS U2541 ( .A(n6099), .Y(n6126) );
XOR2X1TS U2542 ( .A(n6353), .B(n5130), .Y(n5158) );
NOR2X1TS U2543 ( .A(n7494), .B(n9219), .Y(n4776) );
CLKBUFX2TS U2544 ( .A(n5171), .Y(n2239) );
OR2X4TS U2545 ( .A(n4921), .B(n4920), .Y(n5839) );
OAI21X1TS U2546 ( .A0(n6236), .A1(n4328), .B0(n4327), .Y(n4332) );
NAND2X1TS U2547 ( .A(n2992), .B(n6063), .Y(n5925) );
NOR2X2TS U2548 ( .A(n5729), .B(n5728), .Y(n5748) );
NAND2X2TS U2549 ( .A(n2364), .B(n4288), .Y(n2755) );
OAI21X1TS U2550 ( .A0(FPMULT_FSM_selector_B[1]), .A1(n9215), .B0(n6429), .Y(
n6426) );
AOI21X1TS U2551 ( .A0(n6786), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n4826),
.Y(n4827) );
NAND2XLTS U2552 ( .A(n4289), .B(n4305), .Y(n4291) );
NAND2XLTS U2553 ( .A(n5967), .B(n6230), .Y(n4331) );
NAND2X2TS U2554 ( .A(n5906), .B(n5921), .Y(n5875) );
XNOR2X2TS U2555 ( .A(n5864), .B(n5863), .Y(n5865) );
XOR2X1TS U2556 ( .A(n2846), .B(n6427), .Y(n7891) );
NAND2X1TS U2557 ( .A(n5160), .B(n5159), .Y(n5165) );
OAI2BB1X2TS U2558 ( .A0N(n5393), .A1N(n5392), .B0(n3115), .Y(n5533) );
INVX2TS U2559 ( .A(n5121), .Y(n2779) );
OAI2BB1X2TS U2560 ( .A0N(n5494), .A1N(n3063), .B0(n3062), .Y(n5528) );
AND2X6TS U2561 ( .A(n4293), .B(n4288), .Y(n2662) );
NOR2X2TS U2562 ( .A(n5159), .B(n5160), .Y(n5167) );
NAND2X4TS U2563 ( .A(n2427), .B(n6100), .Y(n6186) );
NAND2X2TS U2564 ( .A(n5924), .B(n5923), .Y(n6063) );
NAND2X2TS U2565 ( .A(n5831), .B(n5827), .Y(n5829) );
NAND2X6TS U2566 ( .A(n5916), .B(n5917), .Y(n3025) );
NOR2X1TS U2567 ( .A(n7494), .B(FPMULT_FSM_selector_C), .Y(n4778) );
NAND2X6TS U2568 ( .A(n2766), .B(n4065), .Y(n5794) );
NAND2X1TS U2569 ( .A(n5862), .B(n5869), .Y(n5863) );
CLKAND2X2TS U2570 ( .A(n5100), .B(n5116), .Y(n2674) );
NAND2X4TS U2571 ( .A(n5339), .B(n5338), .Y(n5936) );
OAI21X1TS U2572 ( .A0(FPMULT_FSM_selector_B[1]), .A1(n9216), .B0(n6429), .Y(
n6427) );
NAND2X2TS U2573 ( .A(n5999), .B(n6012), .Y(n4959) );
NAND2XLTS U2574 ( .A(n5112), .B(n5122), .Y(n5113) );
NAND2XLTS U2575 ( .A(n5129), .B(n5166), .Y(n5130) );
NAND2BX1TS U2576 ( .AN(n4795), .B(n4794), .Y(n4796) );
NAND2X1TS U2577 ( .A(n5128), .B(n5127), .Y(n5166) );
INVX4TS U2578 ( .A(n6328), .Y(n5496) );
INVX1TS U2579 ( .A(n5868), .Y(n5842) );
NOR2XLTS U2580 ( .A(n6758), .B(n4822), .Y(n4823) );
NAND2X2TS U2581 ( .A(n5882), .B(n5881), .Y(n5883) );
OR2X2TS U2582 ( .A(n4954), .B(n4953), .Y(n6012) );
NAND2X2TS U2583 ( .A(n5874), .B(n5873), .Y(n5921) );
NAND2X2TS U2584 ( .A(n5908), .B(n5907), .Y(n5920) );
NOR2X6TS U2585 ( .A(n5924), .B(n5923), .Y(n6059) );
NAND2X2TS U2586 ( .A(n4277), .B(n4276), .Y(n4294) );
INVX2TS U2587 ( .A(n4066), .Y(n3371) );
NOR2X4TS U2588 ( .A(n5907), .B(n5908), .Y(n5922) );
OR2X4TS U2589 ( .A(n4956), .B(n4955), .Y(n5999) );
NOR2X2TS U2590 ( .A(n5971), .B(n3212), .Y(n6229) );
INVX4TS U2591 ( .A(n2844), .Y(n2846) );
INVX2TS U2592 ( .A(n6011), .Y(n5997) );
NAND2X4TS U2593 ( .A(n4646), .B(n4645), .Y(n5150) );
NAND2X4TS U2594 ( .A(n5131), .B(n3514), .Y(n3513) );
INVX3TS U2595 ( .A(n4261), .Y(n3181) );
INVX4TS U2596 ( .A(n3209), .Y(n2754) );
INVX4TS U2597 ( .A(n4288), .Y(n3534) );
NAND2BX2TS U2598 ( .AN(n3137), .B(n5142), .Y(n3122) );
INVX2TS U2599 ( .A(n2328), .Y(n3359) );
NAND2X6TS U2600 ( .A(n5786), .B(n3049), .Y(n2772) );
NAND2X1TS U2601 ( .A(n5138), .B(n5137), .Y(n5139) );
NAND2X2TS U2602 ( .A(n5891), .B(n5890), .Y(n5892) );
NAND2X1TS U2603 ( .A(n4239), .B(n4236), .Y(n4201) );
AND2X4TS U2604 ( .A(n4196), .B(n4262), .Y(n2595) );
OAI21X1TS U2605 ( .A0(n4306), .A1(n4305), .B0(n4304), .Y(n4307) );
NOR2X1TS U2606 ( .A(n4814), .B(n9220), .Y(n6763) );
NAND2X1TS U2607 ( .A(n4330), .B(n4329), .Y(n6230) );
NAND2X1TS U2608 ( .A(n4314), .B(n4315), .Y(n4324) );
NAND2X1TS U2609 ( .A(n5109), .B(n5108), .Y(n5137) );
NOR2X1TS U2610 ( .A(n4330), .B(n4329), .Y(n6226) );
INVX2TS U2611 ( .A(n6340), .Y(n5709) );
NAND2X1TS U2612 ( .A(n2342), .B(n4281), .Y(n4305) );
INVX2TS U2613 ( .A(n4295), .Y(n3211) );
NAND2X1TS U2614 ( .A(n2801), .B(n5110), .Y(n5122) );
INVX2TS U2615 ( .A(n5182), .Y(n5826) );
OR2X6TS U2616 ( .A(n2726), .B(n4157), .Y(n5786) );
NAND2X2TS U2617 ( .A(n5861), .B(n5860), .Y(n5869) );
NAND2X4TS U2618 ( .A(n5840), .B(n3107), .Y(n5870) );
INVX4TS U2619 ( .A(n6329), .Y(n3303) );
NAND2X2TS U2620 ( .A(n5181), .B(n5180), .Y(n3238) );
INVX6TS U2621 ( .A(n5292), .Y(n2403) );
INVX4TS U2622 ( .A(n6325), .Y(n5493) );
INVX2TS U2623 ( .A(n5291), .Y(n3498) );
NAND2X1TS U2624 ( .A(n2954), .B(n2949), .Y(n4304) );
XNOR2X2TS U2625 ( .A(n2580), .B(n5732), .Y(n5660) );
NOR2X4TS U2626 ( .A(n5290), .B(n5289), .Y(n5897) );
NAND2X6TS U2627 ( .A(n3295), .B(n6048), .Y(n3294) );
NOR2X6TS U2628 ( .A(n7276), .B(n7280), .Y(n3823) );
NOR2X2TS U2629 ( .A(n4799), .B(n9225), .Y(n6758) );
NAND2X2TS U2630 ( .A(n4769), .B(n2520), .Y(n6146) );
OAI21X2TS U2631 ( .A0(n4970), .A1(n3765), .B0(n3764), .Y(n3766) );
NOR2X4TS U2632 ( .A(n3231), .B(n5142), .Y(n3229) );
NOR2X6TS U2633 ( .A(n4744), .B(n4760), .Y(n7498) );
NOR2X1TS U2634 ( .A(n2958), .B(n2226), .Y(n4279) );
NOR2X6TS U2635 ( .A(n5861), .B(n5860), .Y(n5871) );
OR2X6TS U2636 ( .A(n4194), .B(n4195), .Y(n4196) );
OR2X6TS U2637 ( .A(n5288), .B(n5287), .Y(n5882) );
NAND2XLTS U2638 ( .A(n5105), .B(n5102), .Y(n4687) );
NAND2X1TS U2639 ( .A(n2226), .B(n2958), .Y(n4278) );
NOR2X1TS U2640 ( .A(n2620), .B(n5107), .Y(n5143) );
INVX2TS U2641 ( .A(n6210), .Y(n5370) );
NAND2X1TS U2642 ( .A(n5107), .B(n2620), .Y(n5144) );
NOR2X6TS U2643 ( .A(n3107), .B(n5840), .Y(n5868) );
INVX2TS U2644 ( .A(n5924), .Y(n5666) );
NOR2X1TS U2645 ( .A(n5573), .B(n5652), .Y(n5659) );
OR2X6TS U2646 ( .A(n3480), .B(n2693), .Y(n6048) );
NAND2X1TS U2647 ( .A(n3567), .B(n4686), .Y(n4644) );
OAI2BB1X2TS U2648 ( .A0N(n3323), .A1N(n6215), .B0(n5309), .Y(n3322) );
NAND2X2TS U2649 ( .A(n5084), .B(n5083), .Y(n5134) );
BUFX3TS U2650 ( .A(n3466), .Y(n2230) );
NAND2XLTS U2651 ( .A(n6744), .B(n9227), .Y(n4699) );
NOR2X6TS U2652 ( .A(n4277), .B(n4276), .Y(n4295) );
NAND2X1TS U2653 ( .A(n3641), .B(n4200), .Y(n4062) );
CLKBUFX2TS U2654 ( .A(n4310), .Y(n2955) );
NAND2X2TS U2655 ( .A(n5352), .B(n5355), .Y(n5843) );
OAI22X2TS U2656 ( .A0(n5729), .A1(n2212), .B0(n2818), .B1(n5728), .Y(n5725)
);
NOR2X4TS U2657 ( .A(n3840), .B(n2476), .Y(n4760) );
AND2X4TS U2658 ( .A(n3307), .B(n5418), .Y(n5515) );
NOR2X2TS U2659 ( .A(n3824), .B(n2481), .Y(n4744) );
NOR2X2TS U2660 ( .A(n4825), .B(n9238), .Y(n6759) );
CLKBUFX2TS U2661 ( .A(n4311), .Y(n2227) );
CLKBUFX2TS U2662 ( .A(n4284), .Y(n2954) );
NOR2X1TS U2663 ( .A(n5584), .B(n5761), .Y(n5667) );
NAND2X2TS U2664 ( .A(n3820), .B(n2477), .Y(n7290) );
AND2X4TS U2665 ( .A(n3495), .B(n3494), .Y(n5549) );
NAND2X2TS U2666 ( .A(n3840), .B(n2476), .Y(n4759) );
NOR2X2TS U2667 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n6430) );
NOR2X2TS U2668 ( .A(n3816), .B(n2437), .Y(n5983) );
XNOR2X2TS U2669 ( .A(n5269), .B(n4946), .Y(n4951) );
CLKAND2X2TS U2670 ( .A(n2688), .B(n4685), .Y(n4608) );
NAND3X6TS U2671 ( .A(n3246), .B(n6049), .C(n3244), .Y(n3295) );
NAND2X4TS U2672 ( .A(n5081), .B(n5082), .Y(n5142) );
CLKINVX2TS U2673 ( .A(n4628), .Y(n2249) );
INVX6TS U2674 ( .A(n2254), .Y(n5953) );
NAND2X2TS U2675 ( .A(n5849), .B(n5850), .Y(n3012) );
CLKXOR2X2TS U2676 ( .A(n4940), .B(n8773), .Y(n4941) );
AO21X1TS U2677 ( .A0(n5554), .A1(n5553), .B0(n5552), .Y(n5580) );
INVX6TS U2678 ( .A(n5873), .Y(n3466) );
INVX4TS U2679 ( .A(n5352), .Y(n5425) );
BUFX4TS U2680 ( .A(n5841), .Y(n3107) );
NAND2X1TS U2681 ( .A(n4741), .B(n4740), .Y(n4742) );
CLKINVX6TS U2682 ( .A(n5916), .Y(n4137) );
NAND2X2TS U2683 ( .A(n4923), .B(n4922), .Y(n4925) );
CLKBUFX2TS U2684 ( .A(n4233), .Y(n2226) );
INVX8TS U2685 ( .A(n3137), .Y(n3138) );
OR2X1TS U2686 ( .A(FPADDSUB_Raw_mant_NRM_SWR[8]), .B(
FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n3607) );
NAND2X1TS U2687 ( .A(n4734), .B(n4732), .Y(n4728) );
CLKBUFX2TS U2688 ( .A(n4234), .Y(n2958) );
NAND3X6TS U2689 ( .A(n5890), .B(n3024), .C(n3023), .Y(n5918) );
NOR2X2TS U2690 ( .A(n5408), .B(n5211), .Y(n3066) );
NOR2X1TS U2691 ( .A(n2379), .B(n5761), .Y(n5607) );
OAI22X2TS U2692 ( .A0(n5498), .A1(n5654), .B0(n5508), .B1(n5653), .Y(n5519)
);
INVX12TS U2693 ( .A(n2369), .Y(n3209) );
NAND2X2TS U2694 ( .A(n5472), .B(n3276), .Y(n3275) );
NAND3X6TS U2695 ( .A(n3538), .B(n4479), .C(n4528), .Y(n3246) );
INVX8TS U2696 ( .A(n5648), .Y(n2242) );
NAND2X1TS U2697 ( .A(n4606), .B(n4607), .Y(n4685) );
INVX6TS U2698 ( .A(n4680), .Y(n3241) );
NAND2X1TS U2699 ( .A(n4683), .B(n4684), .Y(n5102) );
NAND2X1TS U2700 ( .A(n4643), .B(n4642), .Y(n4686) );
NAND2X1TS U2701 ( .A(n4198), .B(n2581), .Y(n4236) );
NAND2X1TS U2702 ( .A(n9070), .B(n9071), .Y(n6729) );
NAND2X1TS U2703 ( .A(n2485), .B(n2430), .Y(n5030) );
NOR2X6TS U2704 ( .A(n5083), .B(n5084), .Y(n5115) );
NAND2X1TS U2705 ( .A(n3758), .B(n2433), .Y(n5014) );
INVX2TS U2706 ( .A(n6214), .Y(n5324) );
NOR2BX1TS U2707 ( .AN(n5412), .B(n5413), .Y(n5993) );
INVX2TS U2708 ( .A(n5655), .Y(n5719) );
INVX3TS U2709 ( .A(n5841), .Y(n5472) );
NAND2X1TS U2710 ( .A(n4060), .B(n4061), .Y(n4200) );
NAND2X1TS U2711 ( .A(n4064), .B(n4063), .Y(n4199) );
NOR2X4TS U2712 ( .A(n2373), .B(n2372), .Y(n5276) );
NAND2X1TS U2713 ( .A(n4754), .B(n4753), .Y(n4755) );
NAND2X1TS U2714 ( .A(n3813), .B(n4703), .Y(n3814) );
NAND2X1TS U2715 ( .A(n3837), .B(n4702), .Y(n3838) );
OAI22X2TS U2716 ( .A0(n5566), .A1(n5250), .B0(n2903), .B1(n5325), .Y(n5322)
);
INVX12TS U2717 ( .A(n3121), .Y(n3137) );
BUFX4TS U2718 ( .A(n5441), .Y(n3432) );
AND2X2TS U2719 ( .A(n5502), .B(n2709), .Y(n5513) );
NOR2X6TS U2720 ( .A(n3760), .B(n2506), .Y(n4968) );
CLKAND2X2TS U2721 ( .A(n5558), .B(n2709), .Y(n5576) );
NAND2X2TS U2722 ( .A(n3760), .B(n2506), .Y(n4989) );
BUFX3TS U2723 ( .A(n5440), .Y(n3431) );
NAND2X6TS U2724 ( .A(n4681), .B(n3509), .Y(n3151) );
NAND2X2TS U2725 ( .A(n3759), .B(n2439), .Y(n5002) );
NAND2BX1TS U2726 ( .AN(n5475), .B(n5353), .Y(n5272) );
NAND2X6TS U2727 ( .A(n4154), .B(n4155), .Y(n3038) );
AO21X1TS U2728 ( .A0(n5598), .A1(n2900), .B0(n5596), .Y(n5642) );
INVX6TS U2729 ( .A(n4709), .Y(n3832) );
INVX2TS U2730 ( .A(n4018), .Y(n2747) );
INVX2TS U2731 ( .A(n5463), .Y(n5606) );
OR2X6TS U2732 ( .A(n4436), .B(n4435), .Y(n4481) );
INVX6TS U2733 ( .A(n5353), .Y(n5648) );
NAND2X6TS U2734 ( .A(n4138), .B(n2781), .Y(n4139) );
NAND2X2TS U2735 ( .A(n5211), .B(n5210), .Y(n5281) );
NAND2X6TS U2736 ( .A(n4603), .B(n4604), .Y(n4682) );
NOR2BX2TS U2737 ( .AN(n5475), .B(n5473), .Y(n5285) );
INVX2TS U2738 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(n4935) );
BUFX16TS U2739 ( .A(n5650), .Y(n5566) );
INVX2TS U2740 ( .A(n4525), .Y(n3154) );
CLKINVX6TS U2741 ( .A(n5879), .Y(n5888) );
NAND2X6TS U2742 ( .A(n2659), .B(n4155), .Y(n3039) );
INVX4TS U2743 ( .A(n5817), .Y(n5274) );
INVX2TS U2744 ( .A(n4745), .Y(n4749) );
NAND2X4TS U2745 ( .A(n2907), .B(n3279), .Y(n3278) );
NOR2X2TS U2746 ( .A(n5259), .B(n5414), .Y(n2373) );
NAND2X4TS U2747 ( .A(n2748), .B(n3175), .Y(n2698) );
NAND2X1TS U2748 ( .A(n4142), .B(n4147), .Y(n4150) );
BUFX16TS U2749 ( .A(n5329), .Y(n2619) );
BUFX8TS U2750 ( .A(n5762), .Y(n5761) );
NOR2X2TS U2751 ( .A(n5230), .B(n5413), .Y(n2372) );
INVX2TS U2752 ( .A(n5356), .Y(n3401) );
NOR2X2TS U2753 ( .A(n3828), .B(n4700), .Y(n3831) );
XNOR2X2TS U2754 ( .A(n5591), .B(n5590), .Y(n5639) );
XNOR2X2TS U2755 ( .A(n5591), .B(n2390), .Y(n2933) );
NAND2BX2TS U2756 ( .AN(n5412), .B(n5559), .Y(n5361) );
INVX6TS U2757 ( .A(n2828), .Y(n5583) );
BUFX3TS U2758 ( .A(n4242), .Y(n2603) );
NAND2X4TS U2759 ( .A(n4720), .B(n4719), .Y(n4747) );
CLKINVX2TS U2760 ( .A(n5856), .Y(n4094) );
OAI2BB1X1TS U2761 ( .A0N(n5097), .A1N(n5096), .B0(n3541), .Y(n5118) );
NAND2X1TS U2762 ( .A(n5306), .B(n5398), .Y(n5307) );
INVX1TS U2763 ( .A(n4701), .Y(n3828) );
OR2X2TS U2764 ( .A(n4727), .B(n4726), .Y(n4734) );
INVX2TS U2765 ( .A(n3119), .Y(n5702) );
NOR2BX1TS U2766 ( .AN(n2906), .B(n5453), .Y(n5784) );
NAND2X6TS U2767 ( .A(n4567), .B(n4569), .Y(n2947) );
NAND2X2TS U2768 ( .A(n4727), .B(n4726), .Y(n4732) );
NAND2X1TS U2769 ( .A(n3772), .B(n3769), .Y(n3754) );
NAND2X6TS U2770 ( .A(n5653), .B(n3613), .Y(n5654) );
INVX2TS U2771 ( .A(n5649), .Y(n2902) );
INVX12TS U2772 ( .A(n3493), .Y(n3279) );
NAND2X4TS U2773 ( .A(n5832), .B(n3528), .Y(n3539) );
NAND2X1TS U2774 ( .A(n5348), .B(n2665), .Y(n5349) );
NAND2X4TS U2775 ( .A(n4565), .B(n4566), .Y(n4605) );
NAND2BX2TS U2776 ( .AN(n5475), .B(n5463), .Y(n5210) );
INVX4TS U2777 ( .A(n5559), .Y(n5652) );
NOR2X1TS U2778 ( .A(n5091), .B(n3458), .Y(n5120) );
NAND2X2TS U2779 ( .A(n5728), .B(n2212), .Y(n5446) );
NAND2X2TS U2780 ( .A(n5459), .B(n2586), .Y(n2393) );
XNOR2X2TS U2781 ( .A(n5412), .B(n5559), .Y(n5359) );
INVX4TS U2782 ( .A(n6213), .Y(n2330) );
NOR2X1TS U2783 ( .A(n4141), .B(n4144), .Y(n4147) );
INVX2TS U2784 ( .A(n5463), .Y(n2259) );
INVX1TS U2785 ( .A(n4942), .Y(n4945) );
BUFX6TS U2786 ( .A(n5598), .Y(n2969) );
NOR2X4TS U2787 ( .A(n4720), .B(n4719), .Y(n4745) );
NOR2X1TS U2788 ( .A(n3113), .B(n4253), .Y(n4271) );
NAND2X4TS U2789 ( .A(n5590), .B(n5447), .Y(n5762) );
OAI21X2TS U2790 ( .A0(n5097), .A1(n5096), .B0(n5095), .Y(n3541) );
NAND2X2TS U2791 ( .A(n4906), .B(n4905), .Y(n4908) );
NAND2X6TS U2792 ( .A(n4511), .B(n4510), .Y(n4567) );
INVX6TS U2793 ( .A(n5828), .Y(n5832) );
CLKINVX2TS U2794 ( .A(n2338), .Y(n5552) );
NAND2X1TS U2795 ( .A(n4215), .B(n3213), .Y(n4143) );
BUFX3TS U2796 ( .A(n4058), .Y(n2422) );
OAI22X1TS U2797 ( .A0(n4215), .A1(n3214), .B0(n3213), .B1(n3212), .Y(n4272)
);
NAND2X6TS U2798 ( .A(n4096), .B(n4095), .Y(n3193) );
OAI22X2TS U2799 ( .A0(n4879), .A1(n5454), .B0(n5453), .B1(n3306), .Y(n4886)
);
NOR2BX1TS U2800 ( .AN(n4521), .B(n4441), .Y(n3536) );
INVX2TS U2801 ( .A(n5651), .Y(n5560) );
INVX2TS U2802 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(n4940) );
INVX2TS U2803 ( .A(n5833), .Y(n4476) );
OR2X1TS U2804 ( .A(n9262), .B(n5358), .Y(n3613) );
NOR2X6TS U2805 ( .A(n3806), .B(n3809), .Y(n4701) );
ADDHX1TS U2806 ( .A(n8936), .B(n4738), .CO(n4739), .S(n4726) );
NAND2X4TS U2807 ( .A(n5357), .B(n5358), .Y(n5559) );
NAND2X2TS U2808 ( .A(n2724), .B(n2723), .Y(n2722) );
XNOR2X2TS U2809 ( .A(n4091), .B(n4090), .Y(n5847) );
INVX1TS U2810 ( .A(n4524), .Y(n3535) );
CLKINVX1TS U2811 ( .A(n5407), .Y(n2246) );
NAND2X1TS U2812 ( .A(n4116), .B(n4115), .Y(n4118) );
INVX6TS U2813 ( .A(n2379), .Y(n5568) );
OR2X6TS U2814 ( .A(n4475), .B(n4474), .Y(n3568) );
NAND2X4TS U2815 ( .A(n3797), .B(n3796), .Y(n3808) );
NOR2X1TS U2816 ( .A(n4251), .B(n4252), .Y(n3214) );
NAND2X4TS U2817 ( .A(n3774), .B(n3773), .Y(n3790) );
BUFX12TS U2818 ( .A(n5591), .Y(n3119) );
NAND2X2TS U2819 ( .A(n5332), .B(n5331), .Y(n5333) );
NOR2X2TS U2820 ( .A(n4215), .B(n4214), .Y(n4144) );
NAND2X1TS U2821 ( .A(n3312), .B(n5300), .Y(n3375) );
XNOR2X1TS U2822 ( .A(n3331), .B(n5458), .Y(n4877) );
XOR2X2TS U2823 ( .A(n5202), .B(n5236), .Y(n5203) );
NOR2BX2TS U2824 ( .AN(n5458), .B(n5597), .Y(n4943) );
BUFX8TS U2825 ( .A(n5374), .Y(n2390) );
NAND2X4TS U2826 ( .A(n2238), .B(n2236), .Y(n4569) );
AND2X4TS U2827 ( .A(n2410), .B(n2665), .Y(n5460) );
AND2X4TS U2828 ( .A(n5233), .B(n5299), .Y(n2265) );
CLKXOR2X4TS U2829 ( .A(n4082), .B(n4081), .Y(n4092) );
OR2X2TS U2830 ( .A(n5454), .B(n3306), .Y(n2598) );
OR2X6TS U2831 ( .A(n4897), .B(n5453), .Y(n2597) );
NAND2X1TS U2832 ( .A(n5049), .B(n3510), .Y(n4517) );
NAND2X4TS U2833 ( .A(n4361), .B(n4360), .Y(n4512) );
NOR2X2TS U2834 ( .A(n4183), .B(n4179), .Y(n4141) );
BUFX12TS U2835 ( .A(n5597), .Y(n2900) );
NOR2X2TS U2836 ( .A(n5049), .B(n3510), .Y(n4518) );
NAND2X6TS U2837 ( .A(n3290), .B(n4283), .Y(n3100) );
INVX6TS U2838 ( .A(n5303), .Y(n5596) );
NAND2XLTS U2839 ( .A(n8993), .B(n5223), .Y(n5222) );
NOR2BX2TS U2840 ( .AN(n5362), .B(n3252), .Y(n3251) );
NAND2X2TS U2841 ( .A(n5347), .B(n5591), .Y(n2665) );
INVX8TS U2842 ( .A(n3750), .Y(n3771) );
AND2X4TS U2843 ( .A(n5366), .B(n2977), .Y(n3162) );
NOR2X6TS U2844 ( .A(n4109), .B(n3405), .Y(n3404) );
NAND2X2TS U2845 ( .A(n5313), .B(n5312), .Y(n5316) );
INVX4TS U2846 ( .A(n3769), .Y(n3770) );
INVX3TS U2847 ( .A(n4510), .Y(n2238) );
ADDFHX2TS U2848 ( .A(n5069), .B(n5070), .CI(n5068), .CO(n5097), .S(n5067) );
INVX4TS U2849 ( .A(n4314), .Y(n4166) );
NAND2XLTS U2850 ( .A(n4448), .B(n4447), .Y(n4450) );
INVX2TS U2851 ( .A(n4330), .Y(n4216) );
INVX2TS U2852 ( .A(n5049), .Y(n5070) );
INVX2TS U2853 ( .A(n4283), .Y(n3099) );
INVX2TS U2854 ( .A(n5071), .Y(n3510) );
AND2X6TS U2855 ( .A(n5825), .B(n2943), .Y(n5182) );
OAI21X2TS U2856 ( .A0(n5246), .A1(n5452), .B0(n5451), .Y(n5248) );
NAND2X4TS U2857 ( .A(n4534), .B(n3407), .Y(n3406) );
NAND2X2TS U2858 ( .A(n4438), .B(n4437), .Y(n3052) );
NAND2X6TS U2859 ( .A(n3744), .B(n3743), .Y(n3750) );
NAND2X6TS U2860 ( .A(n5450), .B(n5453), .Y(n5454) );
BUFX4TS U2861 ( .A(n4283), .Y(n2949) );
NOR2X1TS U2862 ( .A(n5220), .B(n9039), .Y(n5221) );
INVX4TS U2863 ( .A(n4329), .Y(n4208) );
INVX4TS U2864 ( .A(FPMULT_Op_MY[11]), .Y(n5358) );
INVX6TS U2865 ( .A(n3190), .Y(n4109) );
CLKINVX6TS U2866 ( .A(n5398), .Y(n2411) );
NAND2X2TS U2867 ( .A(n5199), .B(n3543), .Y(n5200) );
INVX12TS U2868 ( .A(n5217), .Y(n5413) );
CLKXOR2X4TS U2869 ( .A(n9011), .B(n9012), .Y(n4713) );
NAND2X6TS U2870 ( .A(n2366), .B(n5366), .Y(n3072) );
NAND2X4TS U2871 ( .A(n2222), .B(n2221), .Y(n5371) );
NOR2X2TS U2872 ( .A(n4269), .B(n4213), .Y(n4249) );
CLKAND2X2TS U2873 ( .A(n4442), .B(n4519), .Y(n2653) );
NAND2X2TS U2874 ( .A(n5074), .B(n8931), .Y(n3460) );
XOR2X1TS U2875 ( .A(DP_OP_496J248_122_3540_n788), .B(n5218), .Y(n5219) );
NAND2X1TS U2876 ( .A(n4663), .B(n4670), .Y(n4519) );
OR2X6TS U2877 ( .A(n4383), .B(n4382), .Y(n4438) );
OAI2BB1X2TS U2878 ( .A0N(n2224), .A1N(n2223), .B0(n5243), .Y(n2222) );
CLKINVX6TS U2879 ( .A(n6080), .Y(n6346) );
INVX6TS U2880 ( .A(n5450), .Y(n2337) );
BUFX8TS U2881 ( .A(n5303), .Y(n3331) );
INVX3TS U2882 ( .A(n2587), .Y(n4621) );
OR2X4TS U2883 ( .A(n4084), .B(n4902), .Y(n2667) );
OR2X2TS U2884 ( .A(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4789) );
NAND2X2TS U2885 ( .A(n5184), .B(n3106), .Y(n5300) );
MX2X4TS U2886 ( .A(n2326), .B(n3461), .S0(n3511), .Y(n5052) );
NAND2X4TS U2887 ( .A(n3192), .B(n2946), .Y(n3190) );
NAND2X2TS U2888 ( .A(n2540), .B(n8972), .Y(n3779) );
NOR2X4TS U2889 ( .A(n3252), .B(n5319), .Y(n5366) );
INVX2TS U2890 ( .A(n4516), .Y(n4441) );
NOR2X4TS U2891 ( .A(n5298), .B(n5301), .Y(n3402) );
INVX12TS U2892 ( .A(n5640), .Y(n3487) );
CLKINVX6TS U2893 ( .A(n2970), .Y(n3407) );
NOR2X6TS U2894 ( .A(n3532), .B(n3000), .Y(n4110) );
NAND2X1TS U2895 ( .A(n3511), .B(n2679), .Y(n5071) );
INVX12TS U2896 ( .A(n5188), .Y(n5453) );
NAND2X2TS U2897 ( .A(n3561), .B(n2975), .Y(n3553) );
CLKXOR2X2TS U2898 ( .A(n2352), .B(n2351), .Y(n2350) );
INVX3TS U2899 ( .A(n4437), .Y(n3296) );
NAND2X1TS U2900 ( .A(DP_OP_496J248_122_3540_n1516), .B(
DP_OP_496J248_122_3540_n1503), .Y(n2221) );
ADDFHX2TS U2901 ( .A(n3908), .B(n3907), .CI(n3906), .CO(n3938), .S(n3935) );
BUFX6TS U2902 ( .A(n3904), .Y(n2579) );
AND2X6TS U2903 ( .A(n4097), .B(n4096), .Y(n3360) );
NOR2X1TS U2904 ( .A(n4670), .B(n4663), .Y(n4515) );
NAND2X1TS U2905 ( .A(n4457), .B(n4456), .Y(n4459) );
BUFX4TS U2906 ( .A(n4098), .Y(n3532) );
INVX4TS U2907 ( .A(n2977), .Y(n5212) );
XOR2X1TS U2908 ( .A(DP_OP_496J248_122_3540_n778), .B(
DP_OP_496J248_122_3540_n1476), .Y(n5216) );
NAND2X4TS U2909 ( .A(n2245), .B(n4074), .Y(n4902) );
INVX2TS U2910 ( .A(DP_OP_497J248_123_1725_n324), .Y(n3511) );
INVX2TS U2911 ( .A(n4575), .Y(n4617) );
INVX2TS U2912 ( .A(n5225), .Y(n5251) );
INVX4TS U2913 ( .A(n2800), .Y(n4594) );
CLKINVX2TS U2914 ( .A(n5170), .Y(n2408) );
INVX3TS U2915 ( .A(n2610), .Y(n4583) );
NAND2X2TS U2916 ( .A(n4381), .B(n4380), .Y(n4447) );
AND2X2TS U2917 ( .A(n8849), .B(n8855), .Y(n4131) );
NOR2X2TS U2918 ( .A(n4451), .B(n4443), .Y(n4516) );
NAND2X2TS U2919 ( .A(n5226), .B(n2673), .Y(n5319) );
INVX4TS U2920 ( .A(n3968), .Y(n4268) );
INVX12TS U2921 ( .A(n2245), .Y(n3942) );
OAI22X1TS U2922 ( .A0(n5056), .A1(n4549), .B0(n5057), .B1(n4598), .Y(n4544)
);
NAND2X4TS U2923 ( .A(n3430), .B(n3428), .Y(n3966) );
NOR2X2TS U2924 ( .A(DP_OP_498J248_124_1725_n721), .B(
DP_OP_498J248_124_1725_n728), .Y(n4212) );
CLKINVX6TS U2925 ( .A(n5318), .Y(n3252) );
INVX4TS U2926 ( .A(n5970), .Y(n4251) );
INVX3TS U2927 ( .A(n5591), .Y(n3069) );
INVX6TS U2928 ( .A(n2975), .Y(n3555) );
INVX2TS U2929 ( .A(n2675), .Y(n2256) );
CLKINVX1TS U2930 ( .A(DP_OP_496J248_122_3540_n1503), .Y(n2224) );
CLKINVX1TS U2931 ( .A(DP_OP_496J248_122_3540_n1516), .Y(n2223) );
INVX6TS U2932 ( .A(n5110), .Y(n4589) );
OR2X6TS U2933 ( .A(n3933), .B(n3932), .Y(n4096) );
NOR2X4TS U2934 ( .A(n2824), .B(n4625), .Y(n4443) );
NOR2X4TS U2935 ( .A(n9033), .B(n9039), .Y(n5226) );
INVX4TS U2936 ( .A(n4550), .Y(n4590) );
BUFX3TS U2937 ( .A(n3898), .Y(n2811) );
OR2X4TS U2938 ( .A(n4381), .B(n4380), .Y(n4448) );
NAND2X4TS U2939 ( .A(n3381), .B(n3378), .Y(n2739) );
NAND2X6TS U2940 ( .A(n2251), .B(n3021), .Y(n4556) );
CLKINVX2TS U2941 ( .A(n3379), .Y(n2613) );
NAND2X2TS U2942 ( .A(n5188), .B(DP_OP_496J248_122_3540_n828), .Y(n5207) );
OR2X4TS U2943 ( .A(n4234), .B(n4072), .Y(n3085) );
BUFX12TS U2944 ( .A(n3558), .Y(n2975) );
BUFX4TS U2945 ( .A(DP_OP_498J248_124_1725_n635), .Y(n2215) );
INVX4TS U2946 ( .A(n3865), .Y(n4253) );
BUFX6TS U2947 ( .A(n4048), .Y(n2946) );
NOR2X4TS U2948 ( .A(n2645), .B(n2637), .Y(n5225) );
NOR2X6TS U2949 ( .A(n2354), .B(n2353), .Y(n2352) );
NAND2X2TS U2950 ( .A(n2966), .B(n3899), .Y(n2356) );
NAND2X2TS U2951 ( .A(n3849), .B(n3429), .Y(n3428) );
NAND2X4TS U2952 ( .A(n5450), .B(DP_OP_496J248_122_3540_n827), .Y(n5199) );
OR2X6TS U2953 ( .A(n3930), .B(n3929), .Y(n4116) );
INVX2TS U2954 ( .A(n4115), .Y(n3931) );
INVX8TS U2955 ( .A(n3399), .Y(n5303) );
INVX4TS U2956 ( .A(n5428), .Y(n3469) );
NOR2X2TS U2957 ( .A(n3361), .B(n4031), .Y(n2354) );
NAND2X1TS U2958 ( .A(n8986), .B(n5191), .Y(n4895) );
INVX2TS U2959 ( .A(n4657), .Y(n2824) );
NAND2X4TS U2960 ( .A(n3022), .B(n4496), .Y(n3021) );
BUFX3TS U2961 ( .A(n4076), .Y(n2985) );
INVX4TS U2962 ( .A(n4233), .Y(n3898) );
INVX2TS U2963 ( .A(n4406), .Y(n4484) );
AND2X4TS U2964 ( .A(n3093), .B(n3092), .Y(n2316) );
BUFX2TS U2965 ( .A(DP_OP_496J248_122_3540_n1468), .Y(n2234) );
NAND3X4TS U2966 ( .A(n2804), .B(n2803), .C(n2805), .Y(n4600) );
INVX2TS U2967 ( .A(n3476), .Y(n3471) );
OR2X4TS U2968 ( .A(n3243), .B(n2339), .Y(n3381) );
OR2X2TS U2969 ( .A(n3958), .B(n3961), .Y(n3625) );
INVX3TS U2970 ( .A(n3470), .Y(n2398) );
NAND2X2TS U2971 ( .A(n3478), .B(n2213), .Y(n3477) );
NOR2X2TS U2972 ( .A(DP_OP_498J248_124_1725_n721), .B(
DP_OP_498J248_124_1725_n730), .Y(n4022) );
OAI2BB2X2TS U2973 ( .B0(n3361), .B1(n3989), .A0N(n3867), .A1N(n3848), .Y(
n3890) );
ADDFHX2TS U2974 ( .A(n4373), .B(n4372), .CI(n4371), .CO(n4363), .S(n4380) );
ADDFHX2TS U2975 ( .A(DP_OP_498J248_124_1725_n717), .B(n3957), .CI(n3956),
.CO(n4003), .S(n3975) );
BUFX3TS U2976 ( .A(n4072), .Y(n2821) );
NAND2X2TS U2977 ( .A(n4349), .B(n3083), .Y(n3079) );
NAND2X4TS U2978 ( .A(n2326), .B(n3379), .Y(n3378) );
NOR2X4TS U2979 ( .A(n4205), .B(n3989), .Y(n2353) );
INVX6TS U2980 ( .A(n5057), .Y(n2326) );
INVX2TS U2981 ( .A(n5050), .Y(n3379) );
BUFX4TS U2982 ( .A(n4672), .Y(n2216) );
AND2X6TS U2983 ( .A(n3897), .B(n3896), .Y(n3953) );
NAND2X4TS U2984 ( .A(n3930), .B(n3929), .Y(n4115) );
NOR2X4TS U2985 ( .A(n2660), .B(n2643), .Y(n4623) );
NAND2X6TS U2986 ( .A(n3029), .B(n3028), .Y(n4906) );
OAI2BB1X2TS U2987 ( .A0N(DP_OP_498J248_124_1725_n795), .A1N(n2798), .B0(
n3092), .Y(n3042) );
NOR2X4TS U2988 ( .A(n3928), .B(n3927), .Y(n4078) );
NOR2X2TS U2989 ( .A(n4006), .B(DP_OP_498J248_124_1725_n723), .Y(n3956) );
INVX2TS U2990 ( .A(n3287), .Y(n3288) );
NAND2X2TS U2991 ( .A(n4069), .B(n4070), .Y(n4905) );
BUFX8TS U2992 ( .A(DP_OP_497J248_123_1725_n324), .Y(n3458) );
INVX6TS U2993 ( .A(n4403), .Y(n4358) );
CLKINVX3TS U2994 ( .A(n4349), .Y(n3081) );
NOR2X2TS U2995 ( .A(DP_OP_498J248_124_1725_n636), .B(
DP_OP_498J248_124_1725_n640), .Y(n4104) );
NAND2X2TS U2996 ( .A(n4539), .B(n4540), .Y(n2804) );
CLKINVX2TS U2997 ( .A(n4458), .Y(n3524) );
NAND2X6TS U2998 ( .A(n3429), .B(n3427), .Y(n3560) );
OR2X4TS U2999 ( .A(n2322), .B(n4169), .Y(n2360) );
NAND2X2TS U3000 ( .A(n3343), .B(n3342), .Y(n3341) );
INVX4TS U3001 ( .A(n3624), .Y(n2336) );
INVX6TS U3002 ( .A(n4069), .Y(n3029) );
INVX4TS U3003 ( .A(n4352), .Y(n5050) );
INVX2TS U3004 ( .A(n3200), .Y(n3196) );
INVX6TS U3005 ( .A(n2412), .Y(n2340) );
INVX8TS U3006 ( .A(n4335), .Y(n4672) );
NOR2X2TS U3007 ( .A(n4406), .B(n4405), .Y(n4864) );
OR2X6TS U3008 ( .A(n3017), .B(n4067), .Y(n4913) );
INVX12TS U3009 ( .A(n3867), .Y(n4030) );
INVX6TS U3010 ( .A(n2322), .Y(n3429) );
BUFX16TS U3011 ( .A(n4872), .Y(n5450) );
NOR2X6TS U3012 ( .A(n2425), .B(n3955), .Y(n3954) );
INVX12TS U3013 ( .A(n4632), .Y(n2795) );
INVX1TS U3014 ( .A(n4213), .Y(n2359) );
INVX12TS U3015 ( .A(n3343), .Y(n2581) );
INVX4TS U3016 ( .A(n4347), .Y(n2339) );
INVX4TS U3017 ( .A(n4488), .Y(n5072) );
NAND2X1TS U3018 ( .A(n2313), .B(n3959), .Y(n3852) );
OR2X4TS U3019 ( .A(n2676), .B(n2643), .Y(n2638) );
BUFX8TS U3020 ( .A(n4597), .Y(n2962) );
NOR2X2TS U3021 ( .A(n2608), .B(n2799), .Y(n4537) );
NAND2X2TS U3022 ( .A(n4550), .B(n2820), .Y(n4462) );
NAND2X4TS U3023 ( .A(n2970), .B(n3112), .Y(n4848) );
ADDHX2TS U3024 ( .A(DP_OP_498J248_124_1725_n699), .B(
DP_OP_498J248_124_1725_n694), .CO(n4005), .S(n3952) );
NOR2BX2TS U3025 ( .AN(n8588), .B(n3925), .Y(n4087) );
AND2X2TS U3026 ( .A(n2639), .B(n4347), .Y(n2664) );
OAI22X2TS U3027 ( .A0(n2322), .A1(n4035), .B0(n3624), .B1(n4184), .Y(n3886)
);
NOR2X4TS U3028 ( .A(n2970), .B(n3112), .Y(n4847) );
INVX4TS U3029 ( .A(n4001), .Y(n3287) );
INVX2TS U3030 ( .A(n4607), .Y(n2551) );
INVX2TS U3031 ( .A(n5186), .Y(n3126) );
BUFX3TS U3032 ( .A(n4490), .Y(n3112) );
CLKINVX6TS U3033 ( .A(n3856), .Y(n4254) );
NOR2X2TS U3034 ( .A(n3624), .B(n3964), .Y(n4091) );
NOR2X4TS U3035 ( .A(DP_OP_498J248_124_1725_n725), .B(
DP_OP_498J248_124_1725_n729), .Y(n3896) );
OAI2BB1X2TS U3036 ( .A0N(n4643), .A1N(n4401), .B0(n2680), .Y(n2413) );
CLKAND2X4TS U3037 ( .A(n4344), .B(DP_OP_497J248_123_1725_n704), .Y(n4339) );
INVX2TS U3038 ( .A(n4401), .Y(n2414) );
INVX8TS U3039 ( .A(n4342), .Y(n5055) );
INVX4TS U3040 ( .A(n3854), .Y(n4184) );
NAND2X1TS U3041 ( .A(n2693), .B(n4867), .Y(n4467) );
INVX6TS U3042 ( .A(n4890), .Y(n5403) );
BUFX12TS U3043 ( .A(n4501), .Y(n2970) );
NAND2X4TS U3044 ( .A(n3033), .B(n3031), .Y(n3915) );
INVX4TS U3045 ( .A(n4346), .Y(n4671) );
OR2X4TS U3046 ( .A(n3519), .B(n4548), .Y(n2399) );
NAND2X2TS U3047 ( .A(DP_OP_498J248_124_1725_n799), .B(
DP_OP_498J248_124_1725_n805), .Y(n3959) );
NAND2X6TS U3048 ( .A(n2762), .B(n2761), .Y(n3507) );
INVX4TS U3049 ( .A(n3857), .Y(n4206) );
INVX4TS U3050 ( .A(n4345), .Y(n4619) );
INVX3TS U3051 ( .A(n5405), .Y(n3285) );
NOR2X4TS U3052 ( .A(n2817), .B(n4006), .Y(n3893) );
INVX4TS U3053 ( .A(n3849), .Y(n4213) );
OR3X4TS U3054 ( .A(n3139), .B(n2760), .C(n2764), .Y(n2761) );
NOR2X6TS U3055 ( .A(n4503), .B(n2799), .Y(n4502) );
NAND2X2TS U3056 ( .A(n3867), .B(n3034), .Y(n3033) );
INVX4TS U3057 ( .A(n3958), .Y(n3845) );
CLKAND2X4TS U3058 ( .A(DP_OP_497J248_123_1725_n599), .B(
DP_OP_497J248_123_1725_n618), .Y(n4420) );
INVX2TS U3059 ( .A(n4067), .Y(n4068) );
NAND2X4TS U3060 ( .A(n3355), .B(n2363), .Y(n2589) );
INVX4TS U3061 ( .A(n4061), .Y(n3208) );
OR2X2TS U3062 ( .A(n2650), .B(n2322), .Y(n3031) );
OR2X4TS U3063 ( .A(n3002), .B(DP_OP_498J248_124_1725_n643), .Y(n4067) );
OR2X4TS U3064 ( .A(n2315), .B(n3073), .Y(n2650) );
INVX2TS U3065 ( .A(n2765), .Y(n2763) );
INVX4TS U3066 ( .A(n2578), .Y(n4061) );
INVX4TS U3067 ( .A(n3340), .Y(n3866) );
INVX6TS U3068 ( .A(n4503), .Y(n2625) );
INVX2TS U3069 ( .A(n3964), .Y(n3034) );
NOR2X6TS U3070 ( .A(n3624), .B(n4035), .Y(n3881) );
INVX2TS U3071 ( .A(n4910), .Y(n3883) );
NAND2X2TS U3072 ( .A(n8858), .B(DP_OP_498J248_124_1725_n616), .Y(n2363) );
BUFX12TS U3073 ( .A(n4008), .Y(n2322) );
INVX4TS U3074 ( .A(n3847), .Y(n3989) );
ADDFHX2TS U3075 ( .A(DP_OP_497J248_123_1725_n624), .B(n4386), .CI(n4385),
.CO(n4397), .S(n4392) );
NAND2X4TS U3076 ( .A(n8900), .B(n2417), .Y(n4398) );
BUFX8TS U3077 ( .A(n3045), .Y(n2578) );
CLKINVX2TS U3078 ( .A(n3948), .Y(n3551) );
INVX4TS U3079 ( .A(n3853), .Y(n4035) );
NOR2X4TS U3080 ( .A(DP_OP_497J248_123_1725_n638), .B(n2607), .Y(n4338) );
INVX4TS U3081 ( .A(n2600), .Y(n2592) );
OAI21X2TS U3082 ( .A0(n4389), .A1(n4390), .B0(n4391), .Y(n3255) );
NAND2X4TS U3083 ( .A(DP_OP_498J248_124_1725_n392), .B(n8803), .Y(n3032) );
NOR2X4TS U3084 ( .A(n8868), .B(n8863), .Y(n3518) );
INVX12TS U3085 ( .A(DP_OP_498J248_124_1725_n795), .Y(n3955) );
NOR2X4TS U3086 ( .A(n2604), .B(n2601), .Y(n4390) );
OR2X6TS U3087 ( .A(n3452), .B(n3447), .Y(add_x_69_n286) );
NAND3X8TS U3088 ( .A(n3180), .B(n2767), .C(n8102), .Y(n3450) );
NAND3X8TS U3089 ( .A(n8105), .B(n2767), .C(n8102), .Y(n3354) );
NOR2X4TS U3090 ( .A(n2425), .B(DP_OP_498J248_124_1725_n729), .Y(n4026) );
NAND3X6TS U3091 ( .A(n3206), .B(n8102), .C(n2767), .Y(n3205) );
NOR2X8TS U3092 ( .A(DP_OP_498J248_124_1725_n634), .B(n2324), .Y(n4106) );
OAI21X2TS U3093 ( .A0(n6407), .A1(n6404), .B0(n6408), .Y(n6326) );
CMPR22X2TS U3094 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n6647), .CO(
n6693), .S(n6648) );
CMPR22X2TS U3095 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n8602), .CO(
n6647), .S(n8604) );
AOI2BB2X2TS U3096 ( .B0(FPADDSUB_Data_array_SWR[21]), .B1(n7264), .A0N(n7326), .A1N(n7254), .Y(n7255) );
XOR2X4TS U3097 ( .A(DP_OP_26J248_126_1325_n28), .B(n7712), .Y(n7718) );
OR2X8TS U3098 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n7712) );
AOI2BB2X4TS U3099 ( .B0(n8083), .B1(n1587), .A0N(n2915), .A1N(n9257), .Y(
n7509) );
MX2X6TS U3100 ( .A(n7507), .B(n9730), .S0(n2296), .Y(n1587) );
NAND2X2TS U3101 ( .A(n8071), .B(n8241), .Y(n8072) );
AOI2BB2X2TS U3102 ( .B0(n7329), .B1(n7252), .A0N(n8127), .A1N(n7254), .Y(
n7163) );
BUFX20TS U3103 ( .A(n7042), .Y(n8127) );
BUFX20TS U3104 ( .A(n7042), .Y(n7324) );
INVX16TS U3105 ( .A(n7011), .Y(n7317) );
NAND3X4TS U3106 ( .A(n6119), .B(n6118), .C(n6117), .Y(n1534) );
AOI2BB2X2TS U3107 ( .B0(n7329), .B1(n7263), .A0N(n7326), .A1N(n7209), .Y(
n7217) );
INVX16TS U3108 ( .A(n2651), .Y(n7326) );
OAI21X2TS U3109 ( .A0(n7737), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n9905),
.Y(n9906) );
CLKINVX12TS U3110 ( .A(n9866), .Y(n7737) );
NOR3X4TS U3111 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(
n8115) );
AOI2BB2X4TS U3112 ( .B0(n8092), .B1(n8070), .A0N(n2915), .A1N(n8069), .Y(
n8073) );
BUFX8TS U3113 ( .A(DP_OP_496J248_122_3540_n1515), .Y(n3108) );
NAND2X4TS U3114 ( .A(n6030), .B(n6029), .Y(n6031) );
XNOR2X4TS U3115 ( .A(n6395), .B(n6394), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
OAI21X4TS U3116 ( .A0(n2940), .A1(n4773), .B0(n4772), .Y(n4774) );
NAND3X4TS U3117 ( .A(n8086), .B(n8085), .C(n8084), .Y(n1536) );
INVX6TS U3118 ( .A(n5542), .Y(n6331) );
XNOR2X4TS U3119 ( .A(n3843), .B(n3842), .Y(n3844) );
OAI21X4TS U3120 ( .A0(n2939), .A1(n3827), .B0(n3826), .Y(n3843) );
ADDHX4TS U3121 ( .A(add_x_246_A_5_), .B(n6439), .CO(n9085), .S(n9086) );
NAND3X2TS U3122 ( .A(n8096), .B(n8095), .C(n8094), .Y(n1529) );
NAND2X4TS U3123 ( .A(n8071), .B(n8243), .Y(n6117) );
NOR2X4TS U3124 ( .A(n6184), .B(n2438), .Y(n6164) );
NOR2X4TS U3125 ( .A(n6184), .B(n6022), .Y(n6024) );
XOR2X4TS U3126 ( .A(n4783), .B(n2539), .Y(n4784) );
OAI21X4TS U3127 ( .A0(n2940), .A1(n4782), .B0(n4781), .Y(n4783) );
NAND2X4TS U3128 ( .A(n2420), .B(n4682), .Y(n2419) );
NAND2X6TS U3129 ( .A(n2740), .B(n3241), .Y(n2420) );
OAI2BB1X4TS U3130 ( .A0N(n6101), .A1N(n6190), .B0(n3575), .Y(n6102) );
AOI21X4TS U3131 ( .A0(n6190), .A1(n6024), .B0(n6023), .Y(n6025) );
INVX8TS U3132 ( .A(n6190), .Y(n6006) );
AOI21X4TS U3133 ( .A0(n6190), .A1(n6189), .B0(n6188), .Y(n6191) );
XOR2X4TS U3134 ( .A(n3740), .B(n2517), .Y(n3758) );
NAND2X4TS U3135 ( .A(n8961), .B(n8962), .Y(n3740) );
NOR4X2TS U3136 ( .A(n1575), .B(n1571), .C(n1572), .D(n1570), .Y(n6737) );
NOR2X4TS U3137 ( .A(n3365), .B(n5847), .Y(n3364) );
OAI2BB1X2TS U3138 ( .A0N(n7475), .A1N(n7437), .B0(n7436), .Y(n1317) );
AOI2BB2X2TS U3139 ( .B0(n8083), .B1(n1583), .A0N(n2916), .A1N(n7476), .Y(
n7478) );
MX2X6TS U3140 ( .A(n7294), .B(n9727), .S0(n2287), .Y(n1583) );
INVX6TS U3141 ( .A(n5148), .Y(n4648) );
ADDFHX4TS U3142 ( .A(n4949), .B(n4948), .CI(n4947), .CO(n4934), .S(n4950) );
AOI21X2TS U3143 ( .A0(n5946), .A1(n5906), .B0(n5905), .Y(n5911) );
AOI21X2TS U3144 ( .A0(n6060), .A1(n5946), .B0(n6066), .Y(n5926) );
NOR2X4TS U3145 ( .A(add_x_69_n104), .B(n5813), .Y(add_x_69_n85) );
OAI2BB1X4TS U3146 ( .A0N(n6190), .A1N(n6099), .B0(n6127), .Y(n6128) );
BUFX20TS U3147 ( .A(n6112), .Y(n6190) );
OAI21X2TS U3148 ( .A0(n6744), .A1(n4697), .B0(n6181), .Y(n4698) );
NAND2X8TS U3149 ( .A(add_x_69_n113), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[15]), .Y(add_x_69_n104) );
ADDFHX4TS U3150 ( .A(n8952), .B(n8953), .CI(n8954), .CO(n3773), .S(n3752) );
OAI21X4TS U3151 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n6430), .B0(n6429), .Y(
n6431) );
OAI21X2TS U3152 ( .A0(FPMULT_FSM_selector_B[1]), .A1(n9209), .B0(n6429), .Y(
n6428) );
INVX8TS U3153 ( .A(n8302), .Y(n2844) );
CMPR22X2TS U3154 ( .A(n1533), .B(n6748), .CO(n6750), .S(n6749) );
CMPR22X2TS U3155 ( .A(n1532), .B(n6693), .CO(n6748), .S(n6694) );
NOR2X8TS U3156 ( .A(DP_OP_497J248_123_1725_n714), .B(
DP_OP_497J248_123_1725_n722), .Y(n4340) );
OAI21X4TS U3157 ( .A0(n4704), .A1(n4703), .B0(n4702), .Y(n4705) );
ADDFHX2TS U3158 ( .A(n5766), .B(n5765), .CI(n5764), .CO(n5771), .S(n5768) );
AOI21X2TS U3159 ( .A0(n6388), .A1(n6337), .B0(n6336), .Y(n6338) );
AOI21X2TS U3160 ( .A0(n6388), .A1(n6387), .B0(n6386), .Y(n6389) );
NAND2X4TS U3161 ( .A(n7748), .B(n7743), .Y(n7751) );
OAI21X4TS U3162 ( .A0(n2329), .A1(n6144), .B0(n6143), .Y(n6149) );
INVX6TS U3163 ( .A(n6142), .Y(n6143) );
INVX6TS U3164 ( .A(n5727), .Y(n5749) );
CLKINVX12TS U3165 ( .A(n2844), .Y(n2845) );
OAI2BB1X2TS U3166 ( .A0N(n7416), .A1N(n7415), .B0(n7414), .Y(n1412) );
NAND2X2TS U3167 ( .A(n4771), .B(n6185), .Y(n4773) );
BUFX20TS U3168 ( .A(n4758), .Y(n6185) );
OAI21X4TS U3169 ( .A0(n2939), .A1(n6104), .B0(n6103), .Y(n6105) );
INVX4TS U3170 ( .A(n6102), .Y(n6103) );
XOR2X2TS U3171 ( .A(n2845), .B(n6428), .Y(n6652) );
AOI2BB2X4TS U3172 ( .B0(n2793), .B1(n6164), .A0N(n6186), .A1N(n2438), .Y(
n6165) );
INVX12TS U3173 ( .A(n6006), .Y(n2793) );
NAND3X4TS U3174 ( .A(n7510), .B(n7509), .C(n7508), .Y(n1527) );
NAND2X2TS U3175 ( .A(n8093), .B(n1586), .Y(n7508) );
OAI2BB1X2TS U3176 ( .A0N(n7475), .A1N(n7474), .B0(n7473), .Y(n1321) );
AOI21X2TS U3177 ( .A0(n7749), .A1(n7748), .B0(n7747), .Y(n7750) );
XNOR2X4TS U3178 ( .A(n6194), .B(n4725), .Y(n6195) );
OAI21X4TS U3179 ( .A0(n2939), .A1(n6192), .B0(n6191), .Y(n6194) );
ADDFHX4TS U3180 ( .A(n6306), .B(n6305), .CI(n6304), .CO(
DP_OP_499J248_125_1651_n227), .S(DP_OP_499J248_125_1651_n228) );
XOR2X4TS U3181 ( .A(n2831), .B(n7711), .Y(n7720) );
NOR2X6TS U3182 ( .A(n9214), .B(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n7711) );
ADDFHX4TS U3183 ( .A(n5742), .B(n5741), .CI(n5740), .CO(n5757), .S(n5810) );
ADDFHX4TS U3184 ( .A(n5755), .B(n5754), .CI(n5753), .CO(n5758), .S(n5741) );
OAI21X4TS U3185 ( .A0(n2940), .A1(n6130), .B0(n6129), .Y(n6131) );
INVX4TS U3186 ( .A(n6128), .Y(n6129) );
XNOR2X4TS U3187 ( .A(n2515), .B(n2540), .Y(n2727) );
OAI21X4TS U3188 ( .A0(n4747), .A1(n4721), .B0(n4753), .Y(n4735) );
AOI21X4TS U3189 ( .A0(n4750), .A1(n4730), .B0(n4735), .Y(n4729) );
OAI21X4TS U3190 ( .A0(n7752), .A1(n7744), .B0(n7753), .Y(n4763) );
NOR2X8TS U3191 ( .A(n4762), .B(n2484), .Y(n7752) );
ADDFHX4TS U3192 ( .A(n5760), .B(n5759), .CI(n5758), .CO(n5774), .S(n5756) );
MX2X4TS U3193 ( .A(n8101), .B(FPMULT_P_Sgf[12]), .S0(n9751), .Y(n9207) );
AND2X6TS U3194 ( .A(n8100), .B(n8099), .Y(n8101) );
AOI21X4TS U3195 ( .A0(n4750), .A1(n4737), .B0(n4736), .Y(n4743) );
INVX8TS U3196 ( .A(n3453), .Y(n4961) );
XNOR2X4TS U3197 ( .A(n7284), .B(n7283), .Y(n7285) );
OAI21X4TS U3198 ( .A0(n2329), .A1(n7279), .B0(n7278), .Y(n7284) );
NAND2X4TS U3199 ( .A(n6164), .B(n2901), .Y(n6166) );
CLKINVX12TS U3200 ( .A(n6007), .Y(n2901) );
NAND2X4TS U3201 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .B(add_x_69_n95), .Y(n5813) );
NOR2X6TS U3202 ( .A(n5797), .B(n5990), .Y(n6418) );
XNOR2X4TS U3203 ( .A(n6383), .B(n6382), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
INVX6TS U3204 ( .A(n5990), .Y(n5992) );
NOR2X6TS U3205 ( .A(n5155), .B(n5154), .Y(n5174) );
CLKINVX6TS U3206 ( .A(add_x_69_n291), .Y(add_x_69_n289) );
NOR2X4TS U3207 ( .A(n3220), .B(n5788), .Y(n3219) );
XOR2X4TS U3208 ( .A(n2845), .B(n6431), .Y(n6689) );
NOR2X8TS U3209 ( .A(n5153), .B(n3298), .Y(n3297) );
XOR2X4TS U3210 ( .A(n8979), .B(n8980), .Y(n6193) );
INVX8TS U3211 ( .A(n3282), .Y(n2232) );
INVX6TS U3212 ( .A(n3283), .Y(n2231) );
OAI21X2TS U3213 ( .A0(n6419), .A1(n6083), .B0(n6416), .Y(add_x_69_n295) );
NAND2X4TS U3214 ( .A(n3126), .B(n5187), .Y(n2228) );
INVX4TS U3215 ( .A(n3363), .Y(n3027) );
BUFX12TS U3216 ( .A(n3363), .Y(n3017) );
NAND2X6TS U3217 ( .A(n2209), .B(n3055), .Y(n5823) );
NAND2X4TS U3218 ( .A(n6300), .B(n5783), .Y(n5787) );
NOR2X4TS U3219 ( .A(n6300), .B(n5783), .Y(n5788) );
NOR2BX4TS U3220 ( .AN(n5326), .B(n5356), .Y(n3308) );
CLKINVX6TS U3221 ( .A(n3390), .Y(n2769) );
CLKINVX12TS U3222 ( .A(n2391), .Y(n5462) );
INVX4TS U3223 ( .A(n5861), .Y(n5522) );
NAND2X8TS U3224 ( .A(n3533), .B(n4077), .Y(n4108) );
CLKINVX12TS U3225 ( .A(n2946), .Y(n3533) );
OAI21X2TS U3226 ( .A0(n9004), .A1(n6412), .B0(n8994), .Y(n9003) );
BUFX16TS U3227 ( .A(n4873), .Y(n5597) );
NOR2X4TS U3228 ( .A(add_x_69_n285), .B(n3385), .Y(add_x_69_n283) );
NAND2X8TS U3229 ( .A(n3013), .B(n3012), .Y(n3011) );
NOR2X2TS U3230 ( .A(n3476), .B(n3475), .Y(n3473) );
OAI21X2TS U3231 ( .A0(n4889), .A1(n2402), .B0(n4888), .Y(n2401) );
NOR2X6TS U3232 ( .A(n5339), .B(n5338), .Y(n5935) );
INVX12TS U3233 ( .A(n3377), .Y(n5057) );
OA21X2TS U3234 ( .A0(n3961), .A1(n3960), .B0(n3959), .Y(n3962) );
NOR2X6TS U3235 ( .A(n3566), .B(n3163), .Y(n3963) );
NAND2X4TS U3236 ( .A(n3267), .B(n4160), .Y(n3005) );
NAND3X4TS U3237 ( .A(n4160), .B(n3267), .C(n4196), .Y(n3183) );
CLKXOR2X2TS U3238 ( .A(n3501), .B(n6005), .Y(n2633) );
XOR2X4TS U3239 ( .A(n3449), .B(n2202), .Y(n2258) );
NAND3X8TS U3240 ( .A(n3450), .B(n3451), .C(n2663), .Y(n3449) );
NAND2X8TS U3241 ( .A(n4059), .B(n2698), .Y(n3153) );
NOR2X6TS U3242 ( .A(n4232), .B(n4231), .Y(n2369) );
XOR2X4TS U3243 ( .A(n4197), .B(n3345), .Y(n2961) );
NAND2X8TS U3244 ( .A(n3339), .B(n3866), .Y(n3345) );
MX2X4TS U3245 ( .A(n6031), .B(FPMULT_Sgf_normalized_result[23]), .S0(n8080),
.Y(n1625) );
OAI21X4TS U3246 ( .A0(n3616), .A1(n9033), .B0(n5223), .Y(n5224) );
NAND2X8TS U3247 ( .A(n3108), .B(DP_OP_496J248_122_3540_n1502), .Y(n3616) );
NAND2X4TS U3248 ( .A(n4052), .B(n3198), .Y(n3197) );
OAI21X4TS U3249 ( .A0(n8070), .A1(FPMULT_FSM_selector_C), .B0(n2203), .Y(
n6029) );
NAND2X8TS U3250 ( .A(n2204), .B(n9739), .Y(n8070) );
NAND2X8TS U3251 ( .A(n6028), .B(n2542), .Y(n2204) );
NOR2X8TS U3252 ( .A(n4752), .B(n4751), .Y(n4721) );
XOR2X4TS U3253 ( .A(n2206), .B(n3868), .Y(n4198) );
XOR2X4TS U3254 ( .A(n5550), .B(n2706), .Y(n2263) );
OAI21X4TS U3255 ( .A0(n2939), .A1(n6026), .B0(n6025), .Y(n6027) );
NAND2X4TS U3256 ( .A(n4730), .B(n4734), .Y(n4731) );
AND2X6TS U3257 ( .A(n2654), .B(n8846), .Y(n4050) );
NAND2X6TS U3258 ( .A(n3318), .B(n3317), .Y(n3316) );
NAND2X8TS U3259 ( .A(n3448), .B(n2321), .Y(n2757) );
CLKBUFX2TS U3260 ( .A(DP_OP_498J248_124_1725_n634), .Y(n2205) );
XOR2X4TS U3261 ( .A(n3869), .B(n3870), .Y(n2206) );
NAND2X4TS U3262 ( .A(n4234), .B(n4072), .Y(n3087) );
NAND2X8TS U3263 ( .A(n2208), .B(n2207), .Y(n4234) );
NAND2X2TS U3264 ( .A(n3869), .B(n3870), .Y(n2207) );
OAI21X4TS U3265 ( .A0(n3869), .A1(n3870), .B0(n3868), .Y(n2208) );
INVX16TS U3266 ( .A(n2380), .Y(n3493) );
OAI2BB1X4TS U3267 ( .A0N(n5619), .A1N(n5618), .B0(n2210), .Y(n5636) );
OAI21X4TS U3268 ( .A0(n5619), .A1(n5618), .B0(n5617), .Y(n2210) );
NAND2X8TS U3269 ( .A(n2211), .B(n2371), .Y(n4896) );
NAND2X8TS U3270 ( .A(n2340), .B(n3184), .Y(n2211) );
INVX6TS U3271 ( .A(n4284), .Y(n3994) );
CLKINVX12TS U3272 ( .A(n3184), .Y(n2376) );
INVX8TS U3273 ( .A(n4262), .Y(n2328) );
BUFX6TS U3274 ( .A(n3487), .Y(n2212) );
BUFX6TS U3275 ( .A(n5073), .Y(n2213) );
NOR2X2TS U3276 ( .A(n5091), .B(n4671), .Y(n5053) );
INVX8TS U3277 ( .A(n4528), .Y(n3530) );
BUFX6TS U3278 ( .A(DP_OP_498J248_124_1725_n640), .Y(n2214) );
INVX2TS U3279 ( .A(n4670), .Y(n5054) );
OAI2BB1X4TS U3280 ( .A0N(n2349), .A1N(n2355), .B0(n2217), .Y(n4013) );
OAI21X4TS U3281 ( .A0(n2355), .A1(n2349), .B0(n2351), .Y(n2217) );
INVX8TS U3282 ( .A(n4076), .Y(n3996) );
NAND2X6TS U3283 ( .A(n5786), .B(n5785), .Y(n3090) );
XOR2X4TS U3284 ( .A(n2218), .B(n2659), .Y(n2726) );
NAND2X6TS U3285 ( .A(n2219), .B(n4155), .Y(n2218) );
INVX8TS U3286 ( .A(n4154), .Y(n2219) );
INVX8TS U3287 ( .A(n3290), .Y(n3098) );
NAND2X8TS U3288 ( .A(n2220), .B(n3548), .Y(n4001) );
NAND2X8TS U3289 ( .A(n3103), .B(n3102), .Y(n2220) );
XOR2X4TS U3290 ( .A(n5246), .B(n5452), .Y(n5242) );
XOR2X4TS U3291 ( .A(n5243), .B(n2225), .Y(n5246) );
XOR2X4TS U3292 ( .A(DP_OP_496J248_122_3540_n1516), .B(
DP_OP_496J248_122_3540_n1503), .Y(n2225) );
OAI22X4TS U3293 ( .A0(n5566), .A1(n5648), .B0(n5272), .B1(n5649), .Y(n5295)
);
XOR2X4TS U3294 ( .A(n2228), .B(n4890), .Y(n3125) );
NAND2X8TS U3295 ( .A(n4241), .B(n2252), .Y(n6002) );
OAI22X4TS U3296 ( .A0(n2819), .A1(n3333), .B0(n5729), .B1(n3332), .Y(n5469)
);
NAND2X8TS U3297 ( .A(n2232), .B(n2231), .Y(n2819) );
NAND2X8TS U3298 ( .A(n3437), .B(n3438), .Y(n2717) );
NAND2X8TS U3299 ( .A(DP_OP_496J248_122_3540_n1462), .B(n2807), .Y(n5187) );
INVX8TS U3300 ( .A(n3421), .Y(n3483) );
NAND2X8TS U3301 ( .A(n2233), .B(n2356), .Y(n2355) );
OAI21X4TS U3302 ( .A0(n2966), .A1(n3899), .B0(n3898), .Y(n2233) );
XNOR2X4TS U3303 ( .A(n3516), .B(n3515), .Y(n3363) );
XOR2X4TS U3304 ( .A(n4562), .B(n2237), .Y(n2236) );
XNOR2X4TS U3305 ( .A(n4563), .B(n4564), .Y(n2237) );
ADDFHX4TS U3306 ( .A(n5705), .B(n5706), .CI(n5707), .CO(n5708), .S(n6340) );
NAND3X8TS U3307 ( .A(n3389), .B(n3388), .C(n4296), .Y(n3048) );
AND2X8TS U3308 ( .A(n3950), .B(n3257), .Y(n3988) );
NAND3X6TS U3309 ( .A(n6088), .B(n3304), .C(n6085), .Y(n3253) );
NAND2BX4TS U3310 ( .AN(n3509), .B(n4681), .Y(n2418) );
XNOR2X4TS U3311 ( .A(n3046), .B(n3879), .Y(n3045) );
CLKINVX3TS U3312 ( .A(n3391), .Y(n2240) );
INVX6TS U3313 ( .A(n2240), .Y(n2241) );
NOR2XLTS U3314 ( .A(n3248), .B(n5761), .Y(n5764) );
BUFX20TS U3315 ( .A(n3439), .Y(n6242) );
NOR2X4TS U3316 ( .A(n3370), .B(n3423), .Y(n3053) );
NAND2X6TS U3317 ( .A(n5154), .B(n5155), .Y(n5798) );
NAND3X4TS U3318 ( .A(n3469), .B(n3470), .C(n3468), .Y(n2396) );
OAI22X4TS U3319 ( .A0(n5484), .A1(n2903), .B0(n5483), .B1(n5566), .Y(n5497)
);
NAND2X4TS U3320 ( .A(n6049), .B(n6048), .Y(n6050) );
NAND2X6TS U3321 ( .A(n3480), .B(n2693), .Y(n6049) );
NAND2X6TS U3322 ( .A(n4159), .B(n3565), .Y(n3216) );
NAND2X8TS U3323 ( .A(n2771), .B(n3351), .Y(n3350) );
NAND2X6TS U3324 ( .A(n3209), .B(n4196), .Y(n3464) );
XNOR2X4TS U3325 ( .A(n3449), .B(n2622), .Y(n2244) );
BUFX20TS U3326 ( .A(n4075), .Y(n2245) );
ADDHX4TS U3327 ( .A(n5411), .B(n5410), .CO(n5486), .S(n5439) );
XNOR2X4TS U3328 ( .A(n3250), .B(n2246), .Y(n3248) );
XOR2X4TS U3329 ( .A(n2247), .B(n2949), .Y(n3983) );
XOR2X4TS U3330 ( .A(n3985), .B(n3290), .Y(n2247) );
NAND2X6TS U3331 ( .A(n5427), .B(n5426), .Y(n2383) );
OR2X8TS U3332 ( .A(n3370), .B(n3423), .Y(n2248) );
NOR2X8TS U3333 ( .A(n5176), .B(n5798), .Y(n3370) );
CLKINVX6TS U3334 ( .A(n5149), .Y(n3142) );
INVX8TS U3335 ( .A(n5128), .Y(n4628) );
OAI21X1TS U3336 ( .A0(n6353), .A1(n5164), .B0(n5166), .Y(n5163) );
NAND2X6TS U3337 ( .A(n4123), .B(n2982), .Y(n3016) );
AND2X6TS U3338 ( .A(n2631), .B(n2681), .Y(n2640) );
NAND2X8TS U3339 ( .A(n3564), .B(n4159), .Y(n3136) );
ADDFHX4TS U3340 ( .A(n5595), .B(n5594), .CI(n5593), .CO(n5644), .S(n5602) );
INVX8TS U3341 ( .A(n6224), .Y(n8105) );
OAI21X2TS U3342 ( .A0(n5551), .A1(n2715), .B0(n5550), .Y(n2714) );
NAND3X6TS U3343 ( .A(n3072), .B(n3071), .C(n9643), .Y(n2789) );
OR2X6TS U3344 ( .A(n3071), .B(n9643), .Y(n2790) );
CLKXOR2X2TS U3345 ( .A(n2950), .B(n3424), .Y(n6220) );
OR2X4TS U3346 ( .A(n2252), .B(n4241), .Y(n2250) );
XOR2X4TS U3347 ( .A(n4240), .B(n4280), .Y(n4241) );
NOR2X8TS U3348 ( .A(n2602), .B(DP_OP_497J248_123_1725_n782), .Y(n4548) );
NAND2X8TS U3349 ( .A(n3392), .B(n3149), .Y(n3004) );
AOI21X4TS U3350 ( .A0(n5794), .A1(n3188), .B0(n5793), .Y(n3159) );
NAND2X8TS U3351 ( .A(n4681), .B(n4682), .Y(n3150) );
OR2X4TS U3352 ( .A(n4405), .B(n5107), .Y(n2251) );
NAND2X4TS U3353 ( .A(n2726), .B(n4157), .Y(n5785) );
NAND2X4TS U3354 ( .A(n8102), .B(n5963), .Y(n5965) );
NAND2X6TS U3355 ( .A(n3173), .B(n3153), .Y(n3392) );
NOR2X8TS U3356 ( .A(n2766), .B(n4065), .Y(n5793) );
NAND2X4TS U3357 ( .A(n2662), .B(n2771), .Y(n2756) );
CLKINVX12TS U3358 ( .A(DP_OP_497J248_123_1725_n685), .Y(n4503) );
XOR2X4TS U3359 ( .A(n2345), .B(n2344), .Y(n2252) );
NAND3X8TS U3360 ( .A(n3182), .B(n3183), .C(n3359), .Y(n2345) );
INVX3TS U3361 ( .A(n4596), .Y(n2801) );
INVX8TS U3362 ( .A(n3481), .Y(n5994) );
NOR2X4TS U3363 ( .A(n8806), .B(n8822), .Y(n8832) );
BUFX20TS U3364 ( .A(n3456), .Y(n4632) );
NAND2X6TS U3365 ( .A(n8930), .B(n8874), .Y(n3457) );
NOR2X2TS U3366 ( .A(n5474), .B(n5473), .Y(n3067) );
NAND2X8TS U3367 ( .A(n3080), .B(n3079), .Y(n4504) );
BUFX3TS U3368 ( .A(n6015), .Y(n3446) );
NAND2X4TS U3369 ( .A(n4195), .B(n4194), .Y(n4262) );
INVX4TS U3370 ( .A(n4148), .Y(n4100) );
NAND2X4TS U3371 ( .A(DP_OP_496J248_122_3540_n788), .B(n5254), .Y(n5258) );
AND2X6TS U3372 ( .A(n4153), .B(n4152), .Y(n2254) );
NAND2X6TS U3373 ( .A(n6004), .B(n3441), .Y(n6005) );
INVX12TS U3374 ( .A(n5215), .Y(n5556) );
INVX8TS U3375 ( .A(n3125), .Y(n3502) );
NAND2X6TS U3376 ( .A(n2769), .B(n2368), .Y(n2768) );
ADDFHX4TS U3377 ( .A(n4011), .B(n4010), .CI(n4009), .CO(n4042), .S(n4012) );
XNOR2X4TS U3378 ( .A(n5254), .B(n2256), .Y(n3436) );
NAND2X8TS U3379 ( .A(n3140), .B(n3152), .Y(n3415) );
INVX6TS U3380 ( .A(n5127), .Y(n4618) );
OAI22X2TS U3381 ( .A0(n5712), .A1(n5746), .B0(n5733), .B1(n2806), .Y(n5716)
);
INVX2TS U3382 ( .A(n2635), .Y(n2257) );
XOR2X4TS U3383 ( .A(n3201), .B(n2257), .Y(
FPMULT_Sgf_operation_EVEN1_Q_right[23]) );
INVX16TS U3384 ( .A(n4581), .Y(n2820) );
NOR2X8TS U3385 ( .A(n2607), .B(DP_OP_497J248_123_1725_n636), .Y(n4387) );
INVX6TS U3386 ( .A(n4282), .Y(n2701) );
OAI21X1TS U3387 ( .A0(n6236), .A1(n4323), .B0(n4325), .Y(n4317) );
XOR2X4TS U3388 ( .A(n5646), .B(n2259), .Y(n5308) );
XOR2X4TS U3389 ( .A(n3281), .B(n3284), .Y(n2260) );
INVX8TS U3390 ( .A(n4063), .Y(n3882) );
NOR2X6TS U3391 ( .A(n3624), .B(n3989), .Y(n3922) );
INVX4TS U3392 ( .A(n4909), .Y(n3923) );
CLKINVX6TS U3393 ( .A(DP_OP_496J248_122_3540_n1118), .Y(n2976) );
AND2X4TS U3394 ( .A(DP_OP_497J248_123_1725_n692), .B(n8878), .Y(n2262) );
XOR2X4TS U3395 ( .A(n5551), .B(n2263), .Y(n5542) );
NOR2X4TS U3396 ( .A(DP_OP_498J248_124_1725_n640), .B(
DP_OP_498J248_124_1725_n638), .Y(n2264) );
NAND2XLTS U3397 ( .A(n6331), .B(n6330), .Y(n6400) );
XNOR2X4TS U3398 ( .A(n3546), .B(n2265), .Y(n5647) );
INVX4TS U3399 ( .A(n2882), .Y(n2886) );
INVX4TS U3400 ( .A(n2882), .Y(n2885) );
INVX2TS U3401 ( .A(n2269), .Y(n2270) );
BUFX3TS U3402 ( .A(n6265), .Y(n9028) );
OAI22X2TS U3403 ( .A0(n2241), .A1(n4169), .B0(n4205), .B1(n4213), .Y(n4171)
);
OAI22X2TS U3404 ( .A0(n2241), .A1(n3989), .B0(n2905), .B1(n4031), .Y(n4009)
);
BUFX3TS U3405 ( .A(n6440), .Y(n9526) );
INVX8TS U3406 ( .A(n2281), .Y(n2282) );
INVX2TS U3407 ( .A(n2291), .Y(n2293) );
INVX2TS U3408 ( .A(n2291), .Y(n2294) );
CLKINVX12TS U3409 ( .A(n2544), .Y(n2297) );
INVX16TS U3410 ( .A(n2297), .Y(n2298) );
NAND2X2TS U3411 ( .A(n3429), .B(n3865), .Y(n3562) );
INVX2TS U3412 ( .A(n3461), .Y(n2612) );
OAI22X2TS U3413 ( .A0(n4205), .A1(n4169), .B0(n3361), .B1(n4213), .Y(n4049)
);
NAND2X1TS U3414 ( .A(n5458), .B(DP_OP_496J248_122_3540_n451), .Y(n5194) );
ADDFHX2TS U3415 ( .A(n4046), .B(n3192), .CI(n4045), .CO(n2585) );
OAI22X2TS U3416 ( .A0(n4205), .A1(n4206), .B0(n3361), .B1(n4253), .Y(n4190)
);
NAND2X1TS U3417 ( .A(DP_OP_496J248_122_3540_n778), .B(
DP_OP_496J248_122_3540_n1476), .Y(n5214) );
NAND2X1TS U3418 ( .A(n3458), .B(n2213), .Y(n3459) );
NAND2BX2TS U3419 ( .AN(n2907), .B(n5655), .Y(n5381) );
BUFX3TS U3420 ( .A(n4099), .Y(n3000) );
NOR2BX1TS U3421 ( .AN(n5475), .B(n5761), .Y(n5565) );
NOR2X2TS U3422 ( .A(DP_OP_498J248_124_1725_n723), .B(
DP_OP_498J248_124_1725_n727), .Y(n4180) );
NAND2X1TS U3423 ( .A(n4739), .B(n8934), .Y(n4740) );
BUFX12TS U3424 ( .A(n5703), .Y(n2832) );
NAND2X2TS U3425 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .B(n8711), .Y(
n3008) );
OAI21X2TS U3426 ( .A0(n3829), .A1(n4700), .B0(n4703), .Y(n3830) );
NOR2X2TS U3427 ( .A(n2607), .B(n2604), .Y(n4385) );
NAND2X2TS U3428 ( .A(n5099), .B(n5098), .Y(n5116) );
OA21X2TS U3429 ( .A0(n3926), .A1(n4087), .B0(n4088), .Y(n4081) );
INVX2TS U3430 ( .A(n4251), .Y(n3212) );
NAND2X4TS U3431 ( .A(n5428), .B(n9035), .Y(n2708) );
INVX1TS U3432 ( .A(n8548), .Y(n7725) );
NAND2X1TS U3433 ( .A(n3800), .B(n3808), .Y(n3798) );
NAND2X1TS U3434 ( .A(n9245), .B(FPSENCOS_cont_var_out[1]), .Y(n7485) );
CLKINVX6TS U3435 ( .A(n2329), .Y(n2938) );
NAND2X1TS U3436 ( .A(n6185), .B(n6101), .Y(n6104) );
OR2X1TS U3437 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(
FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n2682) );
NAND2X2TS U3438 ( .A(n3821), .B(n2478), .Y(n7281) );
NOR2X1TS U3439 ( .A(n4815), .B(n6763), .Y(n4816) );
NOR2XLTS U3440 ( .A(n6840), .B(n6859), .Y(n6843) );
NAND2X2TS U3441 ( .A(n4073), .B(n2821), .Y(n4916) );
NOR2XLTS U3442 ( .A(n8621), .B(n8620), .Y(n8622) );
NAND2X4TS U3443 ( .A(n7166), .B(n9542), .Y(n6460) );
BUFX3TS U3444 ( .A(n2899), .Y(n7412) );
NAND4BX1TS U3445 ( .AN(n6758), .B(n4813), .C(n4807), .D(n4806), .Y(n4808) );
BUFX8TS U3446 ( .A(FPMULT_FS_Module_state_reg[1]), .Y(n8690) );
OR2X1TS U3447 ( .A(n7961), .B(n9249), .Y(n7967) );
INVX2TS U3448 ( .A(n5019), .Y(n7759) );
NAND2X1TS U3449 ( .A(n8131), .B(n7301), .Y(n7302) );
OA21XLTS U3450 ( .A0(n6236), .A1(n6235), .B0(n6234), .Y(n2635) );
NOR2X6TS U3451 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n8690), .Y(n6180) );
NOR2XLTS U3452 ( .A(n8125), .B(n7054), .Y(n7061) );
OR2X1TS U3453 ( .A(n8675), .B(n6625), .Y(n6631) );
BUFX3TS U3454 ( .A(n8269), .Y(n8293) );
BUFX3TS U3455 ( .A(n8269), .Y(n8276) );
BUFX3TS U3456 ( .A(n8269), .Y(n8280) );
OR2X8TS U3457 ( .A(n3493), .B(n5476), .Y(n2312) );
AND2X8TS U3458 ( .A(n4906), .B(n4907), .Y(n2314) );
CLKMX2X4TS U3459 ( .A(n6261), .B(n9459), .S0(n6283), .Y(n6262) );
AO21X4TS U3460 ( .A0(n5857), .A1(n2655), .B0(n4094), .Y(n2318) );
OA21X4TS U3461 ( .A0(n5301), .A1(n5300), .B0(n5299), .Y(n2319) );
INVX4TS U3462 ( .A(n2364), .Y(n3369) );
OA21X4TS U3463 ( .A0(n5871), .A1(n5870), .B0(n5869), .Y(n2320) );
NAND2X4TS U3464 ( .A(n4287), .B(n4296), .Y(n4288) );
AND2X8TS U3465 ( .A(n3534), .B(n3369), .Y(n2321) );
AND2X4TS U3466 ( .A(n4345), .B(n2639), .Y(n2680) );
AND2X4TS U3467 ( .A(n2778), .B(n5158), .Y(n2777) );
NAND2X8TS U3468 ( .A(n3547), .B(n5300), .Y(n3546) );
NAND2X8TS U3469 ( .A(n3105), .B(n3178), .Y(n3123) );
OAI21X4TS U3470 ( .A0(n7746), .A1(n7745), .B0(n7744), .Y(n7747) );
NAND2X6TS U3471 ( .A(n2368), .B(n3390), .Y(n3453) );
OAI22X2TS U3472 ( .A0(n5415), .A1(n5413), .B0(n5367), .B1(n5414), .Y(n5410)
);
OAI22X4TS U3473 ( .A0(n2795), .A1(n2339), .B0(n2962), .B1(n5050), .Y(n4557)
);
OAI22X2TS U3474 ( .A0(n5416), .A1(n5554), .B0(n5553), .B1(n5504), .Y(n5499)
);
INVX12TS U3475 ( .A(n5111), .Y(n4596) );
NAND2X8TS U3476 ( .A(n3454), .B(n6355), .Y(n3338) );
NAND2X8TS U3477 ( .A(n6243), .B(n3505), .Y(n3504) );
NAND2X8TS U3478 ( .A(n6242), .B(n3506), .Y(n3505) );
NAND2X6TS U3479 ( .A(n4159), .B(n3153), .Y(n3149) );
XNOR2X2TS U3480 ( .A(n3199), .B(n2589), .Y(n2362) );
NOR2X8TS U3481 ( .A(DP_OP_498J248_124_1725_n645), .B(n8809), .Y(n3515) );
CLKINVX12TS U3482 ( .A(DP_OP_498J248_124_1725_n642), .Y(n2323) );
INVX16TS U3483 ( .A(n2323), .Y(n2324) );
INVX4TS U3484 ( .A(n6370), .Y(n6157) );
NOR2X6TS U3485 ( .A(n3464), .B(n4292), .Y(n3443) );
INVX4TS U3486 ( .A(n3210), .Y(n4298) );
NAND2X6TS U3487 ( .A(n3211), .B(n4287), .Y(n3210) );
NAND2X2TS U3488 ( .A(n8131), .B(n7087), .Y(n7090) );
NAND2X2TS U3489 ( .A(n8093), .B(n8242), .Y(n8084) );
INVX6TS U3490 ( .A(n7011), .Y(n8129) );
INVX12TS U3491 ( .A(n2651), .Y(n8125) );
NAND2X6TS U3492 ( .A(n2403), .B(n3498), .Y(n2365) );
INVX4TS U3493 ( .A(n5914), .Y(n2404) );
NAND2X4TS U3494 ( .A(n8035), .B(n8249), .Y(n8087) );
NAND2X4TS U3495 ( .A(n5891), .B(n5888), .Y(n3023) );
NAND3X1TS U3496 ( .A(n7479), .B(n7478), .C(n7477), .Y(n1523) );
NOR2X6TS U3497 ( .A(n3067), .B(n3066), .Y(n3065) );
NAND2X2TS U3498 ( .A(n7760), .B(n1587), .Y(n7761) );
NAND3X4TS U3499 ( .A(n6438), .B(n6437), .C(n6436), .Y(add_x_246_A_5_) );
NAND2X8TS U3500 ( .A(n4810), .B(n4809), .Y(n4833) );
NOR2X1TS U3501 ( .A(n2391), .B(n5761), .Y(n5763) );
INVX4TS U3502 ( .A(n5881), .Y(n3496) );
NAND2X6TS U3503 ( .A(n8712), .B(n8340), .Y(n4810) );
XOR2X2TS U3504 ( .A(n2731), .B(n2672), .Y(n2730) );
NAND2X2TS U3505 ( .A(n5842), .B(n5870), .Y(n5846) );
INVX4TS U3506 ( .A(n6093), .Y(n6094) );
NAND2X6TS U3507 ( .A(n2810), .B(n4512), .Y(n4568) );
OR2X8TS U3508 ( .A(n6789), .B(n4808), .Y(n8712) );
NAND3X2TS U3509 ( .A(n8695), .B(n8694), .C(n8693), .Y(n1693) );
INVX3TS U3510 ( .A(n4512), .Y(n3526) );
NAND2X6TS U3511 ( .A(n4828), .B(n7259), .Y(n8708) );
NAND3X4TS U3512 ( .A(n5022), .B(n5021), .C(n5020), .Y(n1518) );
NOR2X4TS U3513 ( .A(n6223), .B(n6222), .Y(n3440) );
INVX6TS U3514 ( .A(n3035), .Y(n4151) );
INVX12TS U3515 ( .A(n2392), .Y(n5461) );
ADDFHX2TS U3516 ( .A(n4301), .B(n4300), .CI(n4299), .CO(n4302), .S(n4276) );
BUFX8TS U3517 ( .A(n7603), .Y(n8175) );
BUFX8TS U3518 ( .A(n7602), .Y(n8174) );
BUFX8TS U3519 ( .A(n7601), .Y(n8186) );
BUFX8TS U3520 ( .A(n7602), .Y(n8187) );
OAI2BB1X2TS U3521 ( .A0N(n4275), .A1N(n4274), .B0(n3221), .Y(n4299) );
BUFX8TS U3522 ( .A(n7603), .Y(n8188) );
BUFX8TS U3523 ( .A(n7603), .Y(n8218) );
BUFX8TS U3524 ( .A(n7601), .Y(n8765) );
BUFX8TS U3525 ( .A(n7603), .Y(n8764) );
MX2X2TS U3526 ( .A(n8237), .B(FPMULT_exp_oper_result[5]), .S0(n9840), .Y(
n1544) );
NAND2X4TS U3527 ( .A(n7286), .B(n3823), .Y(n4757) );
BUFX8TS U3528 ( .A(n7603), .Y(n7683) );
BUFX8TS U3529 ( .A(n7601), .Y(n7681) );
NAND2X2TS U3530 ( .A(n5780), .B(n5779), .Y(n5782) );
BUFX8TS U3531 ( .A(n7601), .Y(n8208) );
BUFX8TS U3532 ( .A(n7603), .Y(n8210) );
XNOR2X2TS U3533 ( .A(n4980), .B(n4979), .Y(n4981) );
INVX8TS U3534 ( .A(n8093), .Y(n5008) );
OAI21X2TS U3535 ( .A0(n4274), .A1(n4275), .B0(n4273), .Y(n3221) );
INVX8TS U3536 ( .A(n5007), .Y(n8090) );
CLKMX2X2TS U3537 ( .A(n6694), .B(FPMULT_Add_result[15]), .S0(n8603), .Y(
n1609) );
INVX8TS U3538 ( .A(n6649), .Y(n8761) );
BUFX16TS U3539 ( .A(n5475), .Y(n2907) );
INVX12TS U3540 ( .A(n6649), .Y(n9751) );
XOR2X2TS U3541 ( .A(n5375), .B(n5426), .Y(n5376) );
AO22X2TS U3542 ( .A0(n6688), .A1(FPSENCOS_d_ff_Xn[30]), .B0(
FPSENCOS_d_ff2_X[30]), .B1(n8601), .Y(n1954) );
AO22X2TS U3543 ( .A0(n6688), .A1(FPSENCOS_d_ff_Yn[26]), .B0(
FPSENCOS_d_ff2_Y[26]), .B1(n8601), .Y(n1860) );
BUFX12TS U3544 ( .A(n5209), .Y(n5475) );
ADDFHX2TS U3545 ( .A(n5045), .B(n5044), .CI(n5043), .CO(n5080), .S(n5037) );
INVX4TS U3546 ( .A(n5348), .Y(n5399) );
BUFX16TS U3547 ( .A(n7547), .Y(n8211) );
INVX3TS U3548 ( .A(n5407), .Y(n2586) );
AO22X2TS U3549 ( .A0(n6688), .A1(FPSENCOS_d_ff_Yn[23]), .B0(
FPSENCOS_d_ff2_Y[23]), .B1(n8601), .Y(n1863) );
BUFX8TS U3550 ( .A(n6671), .Y(n8679) );
NAND2X4TS U3551 ( .A(n6785), .B(n9095), .Y(n4793) );
AOI22X4TS U3552 ( .A0(n6759), .A1(n9220), .B0(n4800), .B1(
FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4813) );
INVX2TS U3553 ( .A(n6759), .Y(n6760) );
INVX1TS U3554 ( .A(n2686), .Y(n8677) );
NOR2X4TS U3555 ( .A(n3820), .B(n2477), .Y(n7276) );
NOR2X2TS U3556 ( .A(n8033), .B(n7811), .Y(n9101) );
INVX2TS U3557 ( .A(n6649), .Y(n2325) );
NOR2X4TS U3558 ( .A(n5984), .B(n2479), .Y(n3818) );
NOR2X6TS U3559 ( .A(n4825), .B(n4791), .Y(n6785) );
NOR2BX1TS U3560 ( .AN(n2334), .B(n3627), .Y(n2568) );
NOR2X2TS U3561 ( .A(n5651), .B(n5652), .Y(n5706) );
NAND2X6TS U3562 ( .A(n6656), .B(n6655), .Y(n2686) );
INVX3TS U3563 ( .A(n3243), .Y(n2617) );
NAND2X6TS U3564 ( .A(n3070), .B(n3069), .Y(n5348) );
AND2X2TS U3565 ( .A(n2335), .B(n2809), .Y(n2575) );
BUFX8TS U3566 ( .A(n8591), .Y(n6688) );
INVX4TS U3567 ( .A(n2352), .Y(n2349) );
CLKXOR2X2TS U3568 ( .A(n4062), .B(n4199), .Y(n4066) );
INVX2TS U3569 ( .A(n5412), .Y(n2723) );
BUFX8TS U3570 ( .A(n8141), .Y(n8660) );
NAND2X1TS U3571 ( .A(n6916), .B(n8704), .Y(n6917) );
NAND2X8TS U3572 ( .A(n7482), .B(n7481), .Y(n8309) );
NAND2X8TS U3573 ( .A(n8498), .B(n8300), .Y(n6656) );
NOR2BX2TS U3574 ( .AN(n5412), .B(n5652), .Y(n5501) );
BUFX8TS U3575 ( .A(n8459), .Y(n8469) );
NAND2X2TS U3576 ( .A(n3782), .B(n3789), .Y(n3783) );
MX2X6TS U3577 ( .A(n4692), .B(n9720), .S0(n2521), .Y(n1600) );
BUFX8TS U3578 ( .A(n8459), .Y(n8467) );
NAND2X4TS U3579 ( .A(n2336), .B(n3968), .Y(n3559) );
INVX1TS U3580 ( .A(n7480), .Y(n3732) );
NAND2X6TS U3581 ( .A(n8495), .B(n8349), .Y(n8498) );
NAND2X2TS U3582 ( .A(n5207), .B(n5206), .Y(n5208) );
NAND2X1TS U3583 ( .A(n7897), .B(n7896), .Y(n2384) );
NAND2X6TS U3584 ( .A(n7480), .B(operation[1]), .Y(n7482) );
NAND2X4TS U3585 ( .A(n2336), .B(n2359), .Y(n2358) );
BUFX16TS U3586 ( .A(n3507), .Y(n3361) );
INVX6TS U3587 ( .A(n2646), .Y(n7210) );
NAND2X6TS U3588 ( .A(n8758), .B(n8756), .Y(n7480) );
CLKMX2X3TS U3589 ( .A(n8541), .B(n9458), .S0(n6287), .Y(n6247) );
BUFX8TS U3590 ( .A(n9972), .Y(n9817) );
INVX1TS U3591 ( .A(n7470), .Y(n7461) );
NAND2X4TS U3592 ( .A(n7955), .B(n3698), .Y(n7957) );
INVX12TS U3593 ( .A(n2624), .Y(n4642) );
NOR2X4TS U3594 ( .A(n6756), .B(n4790), .Y(n4798) );
NAND2X2TS U3595 ( .A(n3925), .B(n3924), .Y(n4088) );
INVX1TS U3596 ( .A(n7389), .Y(n7380) );
INVX2TS U3597 ( .A(n7407), .Y(n7386) );
INVX1TS U3598 ( .A(n7346), .Y(n7342) );
INVX2TS U3599 ( .A(n4252), .Y(n3213) );
NAND2X6TS U3600 ( .A(n3719), .B(n3717), .Y(n8758) );
INVX2TS U3601 ( .A(n6886), .Y(n6872) );
INVX2TS U3602 ( .A(n6866), .Y(n6841) );
INVX6TS U3603 ( .A(n2835), .Y(n2837) );
INVX3TS U3604 ( .A(n4254), .Y(n3427) );
INVX4TS U3605 ( .A(n5193), .Y(n5458) );
INVX1TS U3606 ( .A(n7433), .Y(n7427) );
BUFX8TS U3607 ( .A(n3693), .Y(n8047) );
OAI211XLTS U3608 ( .A0(n3638), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n7826), .C0(
n7825), .Y(n7829) );
BUFX8TS U3609 ( .A(n8734), .Y(n8742) );
OR2X2TS U3610 ( .A(FPADDSUB_left_right_SHT2), .B(n8334), .Y(n9466) );
AND2X6TS U3611 ( .A(n7962), .B(n3700), .Y(n7780) );
BUFX8TS U3612 ( .A(n8734), .Y(n8739) );
NOR2X2TS U3613 ( .A(n7708), .B(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n7709) );
INVX4TS U3614 ( .A(n5229), .Y(n5362) );
INVX16TS U3615 ( .A(n7259), .Y(n7212) );
NAND4X1TS U3616 ( .A(n7994), .B(n7993), .C(n7992), .D(n7991), .Y(n8010) );
NAND4X1TS U3617 ( .A(n7998), .B(n7997), .C(n7996), .D(n7995), .Y(n8009) );
NAND4X1TS U3618 ( .A(n8002), .B(n8001), .C(n8000), .D(n7999), .Y(n8008) );
NAND4X1TS U3619 ( .A(n8006), .B(n8005), .C(n8004), .D(n8003), .Y(n8007) );
NAND4X1TS U3620 ( .A(n8014), .B(n8013), .C(n8012), .D(n8011), .Y(n8029) );
NAND4X1TS U3621 ( .A(n8018), .B(n8017), .C(n8016), .D(n8015), .Y(n8028) );
INVX2TS U3622 ( .A(n5218), .Y(n2716) );
NAND4X1TS U3623 ( .A(n8022), .B(n8021), .C(n8020), .D(n8019), .Y(n8027) );
INVX4TS U3624 ( .A(DP_OP_26J248_126_1325_n28), .Y(n7713) );
NAND2X8TS U3625 ( .A(n9838), .B(n3682), .Y(n6181) );
NOR2X2TS U3626 ( .A(n3648), .B(FPADDSUB_intDX_EWSW[29]), .Y(n7817) );
NAND2BX1TS U3627 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n7840) );
INVX6TS U3628 ( .A(n9512), .Y(busy) );
BUFX4TS U3629 ( .A(DP_OP_497J248_123_1725_n631), .Y(n2986) );
NAND2X2TS U3630 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n6979) );
INVX2TS U3631 ( .A(n8797), .Y(n8763) );
INVX2TS U3632 ( .A(DP_OP_498J248_124_1725_n723), .Y(n2783) );
NAND2X2TS U3633 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n6958) );
INVX2TS U3634 ( .A(n2813), .Y(n3073) );
NOR2X2TS U3635 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n6997) );
NOR3X2TS U3636 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n9239),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .Y(n3717) );
NAND2X4TS U3637 ( .A(n9970), .B(operation[1]), .Y(n8299) );
INVX2TS U3638 ( .A(Data_1[12]), .Y(n8527) );
INVX2TS U3639 ( .A(n6220), .Y(add_x_69_n76) );
NAND2X4TS U3640 ( .A(n5799), .B(n3329), .Y(n5800) );
INVX6TS U3641 ( .A(n5787), .Y(n3220) );
INVX2TS U3642 ( .A(n6218), .Y(n2787) );
INVX8TS U3643 ( .A(n2777), .Y(n5995) );
NAND2X6TS U3644 ( .A(n2596), .B(n5537), .Y(n3055) );
NOR2X4TS U3645 ( .A(n6376), .B(n6370), .Y(DP_OP_496J248_122_3540_n35) );
NAND2X2TS U3646 ( .A(n6373), .B(n6372), .Y(n6374) );
INVX2TS U3647 ( .A(n6376), .Y(n6378) );
XNOR2X2TS U3648 ( .A(n6318), .B(n6317), .Y(FPMULT_Sgf_operation_EVEN1_S_B[7]) );
NAND2X4TS U3649 ( .A(n5444), .B(n5445), .Y(n6372) );
NAND3X2TS U3650 ( .A(n7048), .B(n7047), .C(n7046), .Y(n1791) );
OAI21X2TS U3651 ( .A0(n6398), .A1(n6339), .B0(n6338), .Y(n6345) );
XOR2X2TS U3652 ( .A(n6299), .B(n6298), .Y(n6306) );
NAND3X2TS U3653 ( .A(n8064), .B(n8063), .C(n8062), .Y(n1530) );
BUFX12TS U3654 ( .A(n7044), .Y(n8131) );
NAND3X2TS U3655 ( .A(n7493), .B(n7492), .C(n7491), .Y(n1526) );
NAND3X2TS U3656 ( .A(n8074), .B(n8073), .C(n8072), .Y(n1539) );
INVX4TS U3657 ( .A(n3065), .Y(n3063) );
NAND2X2TS U3658 ( .A(n9751), .B(n8249), .Y(n9836) );
INVX2TS U3659 ( .A(n5838), .Y(n3075) );
NAND2X4TS U3660 ( .A(n3007), .B(n3006), .Y(n5878) );
OR2X8TS U3661 ( .A(n4840), .B(n4837), .Y(n7011) );
NOR2X2TS U3662 ( .A(n6381), .B(n6391), .Y(n6337) );
NAND2X4TS U3663 ( .A(n3011), .B(n3008), .Y(n3007) );
NOR2X6TS U3664 ( .A(n4833), .B(n7264), .Y(n4838) );
NAND2X6TS U3665 ( .A(n4833), .B(n2687), .Y(n4840) );
INVX6TS U3666 ( .A(n4529), .Y(n4526) );
INVX3TS U3667 ( .A(n6324), .Y(n5480) );
NAND2X4TS U3668 ( .A(n3434), .B(n3433), .Y(n6324) );
NOR2X6TS U3669 ( .A(n3276), .B(n5472), .Y(n3277) );
BUFX12TS U3670 ( .A(n5722), .Y(n2993) );
XNOR2X2TS U3671 ( .A(n7293), .B(n7292), .Y(n7294) );
AND2X4TS U3672 ( .A(n5276), .B(n2330), .Y(n6237) );
NAND2X4TS U3673 ( .A(n3431), .B(n3432), .Y(n3433) );
NOR2X4TS U3674 ( .A(n3526), .B(n4513), .Y(n3525) );
INVX3TS U3675 ( .A(n5906), .Y(n5919) );
INVX4TS U3676 ( .A(n2938), .Y(n2939) );
INVX4TS U3677 ( .A(n3278), .Y(n3276) );
NAND2X4TS U3678 ( .A(n5182), .B(n5181), .Y(n3418) );
NOR2X4TS U3679 ( .A(n2494), .B(n6126), .Y(n6101) );
INVX6TS U3680 ( .A(n3279), .Y(n2806) );
NAND2X2TS U3681 ( .A(n7743), .B(n7501), .Y(n7503) );
NAND3X2TS U3682 ( .A(n6762), .B(n6761), .C(n6760), .Y(n6918) );
NAND2X4TS U3683 ( .A(n4475), .B(n4474), .Y(n5833) );
NAND2X4TS U3684 ( .A(n2385), .B(n2384), .Y(n6432) );
NAND2X4TS U3685 ( .A(n4797), .B(n4796), .Y(n6789) );
AOI2BB1X2TS U3686 ( .A0N(n2329), .A1N(n7288), .B0(n7287), .Y(n7289) );
INVX8TS U3687 ( .A(n5961), .Y(n6172) );
NAND2X4TS U3688 ( .A(n5960), .B(n5961), .Y(n6223) );
MX2X2TS U3689 ( .A(n8135), .B(FPMULT_exp_oper_result[6]), .S0(n9840), .Y(
n1543) );
AO21X2TS U3690 ( .A0(n5721), .A1(n2331), .B0(n5719), .Y(n5752) );
MX2X2TS U3691 ( .A(n6749), .B(FPMULT_Add_result[16]), .S0(n6747), .Y(n1608)
);
INVX12TS U3692 ( .A(n5008), .Y(n8071) );
INVX12TS U3693 ( .A(n2902), .Y(n2903) );
OA21X2TS U3694 ( .A0(n8337), .A1(n9235), .B0(n8119), .Y(n8120) );
INVX4TS U3695 ( .A(n5008), .Y(n7760) );
ADDFHX2TS U3696 ( .A(n5120), .B(n5119), .CI(n5118), .CO(n5121), .S(n5098) );
CLKXOR2X2TS U3697 ( .A(n5173), .B(n5172), .Y(n2669) );
INVX8TS U3698 ( .A(n5007), .Y(n8081) );
BUFX8TS U3699 ( .A(n8195), .Y(n8767) );
BUFX8TS U3700 ( .A(n8195), .Y(n8220) );
NAND2X4TS U3701 ( .A(n4448), .B(n4449), .Y(n3522) );
NAND2X4TS U3702 ( .A(n4383), .B(n4382), .Y(n4437) );
OAI21X2TS U3703 ( .A0(n5778), .A1(n5781), .B0(n5779), .Y(n5792) );
BUFX8TS U3704 ( .A(n8195), .Y(n8177) );
INVX8TS U3705 ( .A(n6649), .Y(n9752) );
BUFX8TS U3706 ( .A(n8195), .Y(n7653) );
BUFX8TS U3707 ( .A(n8195), .Y(n8190) );
BUFX8TS U3708 ( .A(n8195), .Y(n7685) );
INVX4TS U3709 ( .A(n6649), .Y(n2834) );
NAND2X2TS U3710 ( .A(n5285), .B(n5284), .Y(n5853) );
INVX6TS U3711 ( .A(n5007), .Y(n7758) );
NOR2X4TS U3712 ( .A(n4768), .B(n2509), .Y(n6139) );
NAND2X2TS U3713 ( .A(n4080), .B(n4079), .Y(n4082) );
INVX6TS U3714 ( .A(n3372), .Y(n5720) );
NOR2X4TS U3715 ( .A(n3633), .B(n4941), .Y(n5778) );
BUFX16TS U3716 ( .A(n5239), .Y(n5649) );
INVX2TS U3717 ( .A(n5446), .Y(n3492) );
OA21X2TS U3718 ( .A0(n6353), .A1(n6352), .B0(n6351), .Y(n2684) );
OR2X8TS U3719 ( .A(n6030), .B(FPMULT_FSM_selector_C), .Y(n5019) );
OAI21X1TS U3720 ( .A0(n8892), .A1(n8908), .B0(n8903), .Y(n2567) );
INVX2TS U3721 ( .A(n4308), .Y(n4290) );
CLKMX2X2TS U3722 ( .A(n6648), .B(FPMULT_Add_result[14]), .S0(n8603), .Y(
n1610) );
MXI2X1TS U3723 ( .A(n6613), .B(n9369), .S0(n8431), .Y(n1476) );
OA21X1TS U3724 ( .A0(n3734), .A1(n8347), .B0(n3733), .Y(n2689) );
NAND2X4TS U3725 ( .A(n5348), .B(n2411), .Y(n2410) );
CLKMX2X2TS U3726 ( .A(n8604), .B(FPMULT_Add_result[13]), .S0(n8603), .Y(
n1611) );
AOI22X1TS U3727 ( .A0(n7391), .A1(n7038), .B0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.B1(n2835), .Y(n7392) );
MXI2X1TS U3728 ( .A(n8333), .B(n2696), .S0(n8506), .Y(n1849) );
INVX8TS U3729 ( .A(n2686), .Y(n6676) );
INVX2TS U3730 ( .A(n4078), .Y(n4080) );
AND2X2TS U3731 ( .A(n8033), .B(FPADDSUB_Shift_reg_FLAGS_7_6), .Y(n9956) );
INVX8TS U3732 ( .A(n2686), .Y(n8644) );
OR2X2TS U3733 ( .A(n8883), .B(n8893), .Y(n8892) );
NAND2X8TS U3734 ( .A(n4698), .B(n8690), .Y(n6030) );
BUFX8TS U3735 ( .A(n6671), .Y(n8646) );
BUFX8TS U3736 ( .A(n6671), .Y(n8656) );
INVX8TS U3737 ( .A(n2686), .Y(n8654) );
BUFX8TS U3738 ( .A(n8326), .Y(n8653) );
NAND2X6TS U3739 ( .A(n2597), .B(n2598), .Y(n4889) );
BUFX12TS U3740 ( .A(n7547), .Y(n8766) );
INVX6TS U3741 ( .A(n2948), .Y(n5509) );
NAND2X2TS U3742 ( .A(n9682), .B(n6269), .Y(n8914) );
CLKMX2X2TS U3743 ( .A(n8567), .B(FPMULT_Add_result[12]), .S0(n8603), .Y(
n1612) );
NOR2X1TS U3744 ( .A(n8884), .B(n8888), .Y(n8906) );
NOR2X1TS U3745 ( .A(n8909), .B(n8885), .Y(n2553) );
OAI21X2TS U3746 ( .A0(n4825), .A1(n4824), .B0(n4823), .Y(n4826) );
CLKMX2X2TS U3747 ( .A(n8672), .B(FPSENCOS_d_ff3_sh_x_out[28]), .S0(n8675),
.Y(n1948) );
NAND2X2TS U3748 ( .A(n5145), .B(n5144), .Y(n5147) );
CLKMX2X2TS U3749 ( .A(n8676), .B(FPSENCOS_d_ff3_sh_y_out[28]), .S0(n8675),
.Y(n1850) );
NAND2X4TS U3750 ( .A(n3460), .B(n3459), .Y(n5092) );
XOR2X1TS U3751 ( .A(n5005), .B(n5004), .Y(n5006) );
NAND3X2TS U3752 ( .A(n6037), .B(n6036), .C(n6035), .Y(n7241) );
BUFX8TS U3753 ( .A(n8591), .Y(n8669) );
NOR2X1TS U3754 ( .A(n8807), .B(n8815), .Y(n8824) );
OR2X2TS U3755 ( .A(n5984), .B(n2479), .Y(n5986) );
BUFX8TS U3756 ( .A(n8657), .Y(n8664) );
NOR2X1TS U3757 ( .A(n8804), .B(n8837), .Y(n8843) );
INVX4TS U3758 ( .A(n6267), .Y(n9682) );
NOR2X1TS U3759 ( .A(n8818), .B(n8814), .Y(n2573) );
NOR2X1TS U3760 ( .A(n8834), .B(n8833), .Y(n2558) );
NOR2X1TS U3761 ( .A(n8808), .B(n8805), .Y(n8830) );
NOR2X1TS U3762 ( .A(n8909), .B(n8911), .Y(n8910) );
NAND2X6TS U3763 ( .A(n3087), .B(n3884), .Y(n3086) );
NAND3X2TS U3764 ( .A(n7215), .B(n7214), .C(n7213), .Y(n7268) );
AO21X2TS U3765 ( .A0(n6696), .A1(n5028), .B0(n5027), .Y(n5032) );
INVX6TS U3766 ( .A(n5306), .Y(n5397) );
BUFX8TS U3767 ( .A(n6635), .Y(n8662) );
INVX6TS U3768 ( .A(n5347), .Y(n3070) );
BUFX8TS U3769 ( .A(n6635), .Y(n8590) );
INVX6TS U3770 ( .A(n3072), .Y(n2792) );
INVX4TS U3771 ( .A(n6282), .Y(n8888) );
BUFX8TS U3772 ( .A(n8657), .Y(n8226) );
CLKMX2X2TS U3773 ( .A(n8501), .B(FPMULT_Add_result[11]), .S0(n8603), .Y(
n1613) );
BUFX8TS U3774 ( .A(n8657), .Y(n8147) );
AOI21X2TS U3775 ( .A0(n5105), .A1(n5104), .B0(n5103), .Y(n5146) );
NOR2X1TS U3776 ( .A(n8804), .B(n8808), .Y(n2576) );
AND4X2TS U3777 ( .A(n3705), .B(n3704), .C(n8078), .D(n3703), .Y(n2690) );
CLKMX2X2TS U3778 ( .A(n8509), .B(FPSENCOS_d_ff3_LUT_out[13]), .S0(n8675),
.Y(n2123) );
NAND2X1TS U3779 ( .A(n7055), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n6033) );
CLKMX2X2TS U3780 ( .A(n8464), .B(FPMULT_Add_result[10]), .S0(n8603), .Y(
n1614) );
BUFX16TS U3781 ( .A(n5253), .Y(n5412) );
OAI21X1TS U3782 ( .A0(n8300), .A1(n8299), .B0(n8298), .Y(operation_ready) );
NOR2X1TS U3783 ( .A(n1670), .B(n1664), .Y(n2565) );
NAND2X6TS U3784 ( .A(n8307), .B(n8347), .Y(n3716) );
BUFX8TS U3785 ( .A(n7788), .Y(n8043) );
NAND2X4TS U3786 ( .A(n3709), .B(n6679), .Y(n8657) );
BUFX16TS U3787 ( .A(n8507), .Y(n8783) );
BUFX8TS U3788 ( .A(n8507), .Y(n8790) );
XOR2X1TS U3789 ( .A(n7897), .B(n7896), .Y(n2388) );
INVX2TS U3790 ( .A(n4706), .Y(n3829) );
INVX3TS U3791 ( .A(n3475), .Y(n3472) );
INVX2TS U3792 ( .A(n8375), .Y(n6825) );
NAND2X6TS U3793 ( .A(n3502), .B(n9645), .Y(n5347) );
INVX2TS U3794 ( .A(n1680), .Y(n8881) );
INVX4TS U3795 ( .A(n1648), .Y(n8867) );
INVX4TS U3796 ( .A(n6274), .Y(n2335) );
NAND2X4TS U3797 ( .A(n2406), .B(n2405), .Y(n5075) );
INVX2TS U3798 ( .A(n7897), .Y(n2386) );
MXI2X1TS U3799 ( .A(n9143), .B(n9472), .S0(n8680), .Y(n1248) );
AOI21X4TS U3800 ( .A0(n6908), .A1(n6907), .B0(n6906), .Y(n6909) );
XOR2X1TS U3801 ( .A(n2845), .B(n6424), .Y(n7882) );
MXI2X4TS U3802 ( .A(n6281), .B(n9385), .S0(n8445), .Y(n6282) );
BUFX12TS U3803 ( .A(n5106), .Y(n2620) );
MXI2X1TS U3804 ( .A(n9142), .B(n9474), .S0(n8680), .Y(n1232) );
OR2X6TS U3805 ( .A(n4403), .B(n4402), .Y(n4853) );
INVX2TS U3806 ( .A(n1603), .Y(n4777) );
INVX4TS U3807 ( .A(n6908), .Y(n7147) );
MX2X4TS U3808 ( .A(n8510), .B(n9457), .S0(n6287), .Y(n6274) );
INVX3TS U3809 ( .A(n8773), .Y(n4939) );
BUFX12TS U3810 ( .A(n8053), .Y(n8683) );
NAND2X4TS U3811 ( .A(n4798), .B(n9225), .Y(n6754) );
INVX6TS U3812 ( .A(n4490), .Y(n4542) );
CLKMX2X2TS U3813 ( .A(n8491), .B(FPMULT_zero_flag), .S0(n9843), .Y(n1626) );
BUFX8TS U3814 ( .A(n7038), .Y(n8704) );
MXI2X4TS U3815 ( .A(n8527), .B(n9260), .S0(n6283), .Y(n1671) );
MXI2X4TS U3816 ( .A(n8529), .B(n9379), .S0(n6283), .Y(n1673) );
MXI2X4TS U3817 ( .A(n8512), .B(n9378), .S0(n6260), .Y(n1662) );
MXI2X1TS U3818 ( .A(n9141), .B(n9473), .S0(n8680), .Y(n1224) );
NOR2X4TS U3819 ( .A(n8680), .B(n9468), .Y(n7788) );
NAND2X2TS U3820 ( .A(n3804), .B(n3807), .Y(n3805) );
BUFX16TS U3821 ( .A(n2977), .Y(n2366) );
INVX1TS U3822 ( .A(n7451), .Y(n7447) );
INVX6TS U3823 ( .A(n3702), .Y(n8682) );
INVX2TS U3824 ( .A(n6869), .Y(n6844) );
NAND2X1TS U3825 ( .A(n8047), .B(FPADDSUB_Data_array_SWR[24]), .Y(n7945) );
INVX2TS U3826 ( .A(n8294), .Y(n8297) );
INVX6TS U3827 ( .A(n3702), .Y(n8681) );
BUFX8TS U3828 ( .A(n6747), .Y(n9750) );
BUFX16TS U3829 ( .A(n8447), .Y(n6260) );
AOI222X1TS U3830 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3602), .B0(n7829), .B1(
n7828), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n2647), .Y(n7831) );
INVX2TS U3831 ( .A(n4970), .Y(n5012) );
INVX1TS U3832 ( .A(n7364), .Y(n7362) );
AND2X4TS U3833 ( .A(n4858), .B(n4862), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[1]) );
BUFX8TS U3834 ( .A(n8755), .Y(n8759) );
NAND2X4TS U3835 ( .A(n9969), .B(n8385), .Y(n6592) );
INVX2TS U3836 ( .A(n7030), .Y(n7144) );
CLKMX2X2TS U3837 ( .A(FPADDSUB_DmP_mant_SHT1_SW[15]), .B(n8424), .S0(n8423),
.Y(n1405) );
INVX2TS U3838 ( .A(n8382), .Y(n6593) );
OAI21X2TS U3839 ( .A0(n6895), .A1(n6894), .B0(n6893), .Y(n6908) );
BUFX12TS U3840 ( .A(n4870), .Y(n5452) );
INVX1TS U3841 ( .A(n7138), .Y(n7141) );
NAND2X4TS U3842 ( .A(n8692), .B(n6574), .Y(n6747) );
XOR2X2TS U3843 ( .A(n5313), .B(n5312), .Y(n5503) );
NAND3X2TS U3844 ( .A(n6583), .B(n6582), .C(n9592), .Y(n8382) );
INVX2TS U3845 ( .A(n2835), .Y(n2836) );
NAND2X1TS U3846 ( .A(n2929), .B(n2930), .Y(n8325) );
NAND2X4TS U3847 ( .A(n3812), .B(n3811), .Y(n4703) );
BUFX8TS U3848 ( .A(n7801), .Y(n8049) );
BUFX8TS U3849 ( .A(n7780), .Y(n8039) );
AND2X2TS U3850 ( .A(n7949), .B(n9468), .Y(n9112) );
NOR2X2TS U3851 ( .A(n8320), .B(n8781), .Y(n6644) );
OAI21X2TS U3852 ( .A0(n7024), .A1(n7031), .B0(n7025), .Y(n7138) );
INVX6TS U3853 ( .A(n4643), .Y(n2416) );
XOR2X1TS U3854 ( .A(n8457), .B(n9510), .Y(n8458) );
NOR2X8TS U3855 ( .A(n7484), .B(n9461), .Y(n7238) );
NOR2X4TS U3856 ( .A(n7273), .B(n9541), .Y(n6459) );
INVX8TS U3857 ( .A(n2606), .Y(n2636) );
BUFX8TS U3858 ( .A(n7811), .Y(n8778) );
OR2X4TS U3859 ( .A(n7961), .B(n8334), .Y(n7768) );
NAND2X4TS U3860 ( .A(n3753), .B(n3752), .Y(n3769) );
NAND2X4TS U3861 ( .A(n9035), .B(n5430), .Y(n3470) );
NAND2X1TS U3862 ( .A(n7962), .B(FPADDSUB_Data_array_SWR[22]), .Y(n7800) );
NOR2X2TS U3863 ( .A(n6021), .B(n6020), .Y(n6183) );
INVX3TS U3864 ( .A(n4064), .Y(n3878) );
NAND2X1TS U3865 ( .A(n2649), .B(n9481), .Y(n2930) );
NAND4X1TS U3866 ( .A(n9961), .B(n8618), .C(n8617), .D(n8616), .Y(n8619) );
NOR4X1TS U3867 ( .A(n2895), .B(dataB[28]), .C(dataB[29]), .D(dataB[31]), .Y(
n8625) );
OAI21X1TS U3868 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n3656), .B0(n7813), .Y(
n7872) );
CLKINVX1TS U3869 ( .A(n8115), .Y(n8117) );
INVX2TS U3870 ( .A(n7713), .Y(n2831) );
NOR2X2TS U3871 ( .A(n6941), .B(n6957), .Y(n6901) );
INVX2TS U3872 ( .A(n2638), .Y(n2611) );
INVX4TS U3873 ( .A(DP_OP_496J248_122_3540_n1469), .Y(n2956) );
INVX8TS U3874 ( .A(FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n8554) );
NOR2X4TS U3875 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n6889) );
BUFX4TS U3876 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n8334) );
NOR2X4TS U3877 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n7024) );
NOR2X4TS U3878 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]),
.Y(n7458) );
NAND2X1TS U3879 ( .A(n9229), .B(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n4811) );
NAND2X2TS U3880 ( .A(n9055), .B(n2482), .Y(n6711) );
INVX4TS U3881 ( .A(n8901), .Y(n2417) );
NAND2X2TS U3882 ( .A(n2519), .B(n9069), .Y(n6725) );
INVX6TS U3883 ( .A(n2909), .Y(n2910) );
CLKBUFX2TS U3884 ( .A(cordic_result[12]), .Y(n2922) );
NAND2X8TS U3885 ( .A(n9546), .B(n9545), .Y(n7273) );
NAND2X2TS U3886 ( .A(n2516), .B(FPMULT_Sgf_operation_EVEN1_Q_right[22]), .Y(
n6697) );
CLKBUFX2TS U3887 ( .A(cordic_result[22]), .Y(n2925) );
NAND4X1TS U3888 ( .A(dataA[30]), .B(dataA[28]), .C(dataA[29]), .D(dataA[26]),
.Y(n8614) );
NOR2X2TS U3889 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n6941) );
CLKBUFX2TS U3890 ( .A(cordic_result[13]), .Y(n2923) );
NAND2X2TS U3891 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n7031) );
CLKBUFX2TS U3892 ( .A(cordic_result[9]), .Y(n2921) );
NOR2X4TS U3893 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n6984) );
NOR2X2TS U3894 ( .A(n9476), .B(FPADDSUB_DMP_SFG[10]), .Y(n6954) );
NAND2X1TS U3895 ( .A(n9462), .B(operation_reg_0_), .Y(n8630) );
INVX2TS U3896 ( .A(n2807), .Y(n2808) );
CLKBUFX2TS U3897 ( .A(cordic_result[19]), .Y(n2924) );
NOR2X6TS U3898 ( .A(FPSENCOS_cont_iter_out[2]), .B(FPSENCOS_cont_iter_out[0]), .Y(n8594) );
NOR2X4TS U3899 ( .A(DP_OP_497J248_123_1725_n721), .B(n2608), .Y(n4341) );
INVX2TS U3900 ( .A(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n4818) );
NOR2X4TS U3901 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n6815) );
CLKBUFX2TS U3902 ( .A(dataB[30]), .Y(n2895) );
NAND2X4TS U3903 ( .A(DP_OP_496J248_122_3540_n1512), .B(
DP_OP_496J248_122_3540_n1499), .Y(n5191) );
INVX2TS U3904 ( .A(FPMULT_FS_Module_state_reg[1]), .Y(n6745) );
INVX2TS U3905 ( .A(n9462), .Y(n8624) );
NOR2X4TS U3906 ( .A(DP_OP_497J248_123_1725_n634), .B(
DP_OP_497J248_123_1725_n631), .Y(n4388) );
NOR2X4TS U3907 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n6885) );
NOR2X4TS U3908 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]),
.Y(n7339) );
NOR2X1TS U3909 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n6619) );
NAND2X4TS U3910 ( .A(n4884), .B(DP_OP_496J248_122_3540_n1203), .Y(n3490) );
NOR2X4TS U3911 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]),
.Y(n7131) );
CLKBUFX2TS U3912 ( .A(dataB[25]), .Y(n2896) );
INVX3TS U3913 ( .A(n2609), .Y(n4425) );
INVX2TS U3914 ( .A(Data_1[14]), .Y(n8529) );
NAND2X4TS U3915 ( .A(n3504), .B(n3503), .Y(DP_OP_499J248_125_1651_n215) );
INVX3TS U3916 ( .A(n3384), .Y(FPMULT_Sgf_operation_EVEN1_Q_left[20]) );
NAND2X6TS U3917 ( .A(n3410), .B(n3310), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[21]) );
NAND2X4TS U3918 ( .A(n6017), .B(add_x_69_n95), .Y(add_x_69_n94) );
INVX3TS U3919 ( .A(DP_OP_499J248_125_1651_n293), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[19]) );
INVX6TS U3920 ( .A(n6225), .Y(n3204) );
NAND2X4TS U3921 ( .A(n3330), .B(n3329), .Y(n3328) );
INVX4TS U3922 ( .A(n6206), .Y(n6207) );
INVX6TS U3923 ( .A(n5175), .Y(n3329) );
INVX2TS U3924 ( .A(n3055), .Y(n3054) );
NAND2X6TS U3925 ( .A(n3225), .B(n6308), .Y(n6046) );
INVX6TS U3926 ( .A(n6044), .Y(n3224) );
AO21X2TS U3927 ( .A0(n2651), .A1(n7301), .B0(n6991), .Y(n1813) );
AND2X4TS U3928 ( .A(n5774), .B(n5773), .Y(n6364) );
NOR3X6TS U3929 ( .A(n3230), .B(n3229), .C(n3512), .Y(n3228) );
NAND3BX2TS U3930 ( .AN(n7267), .B(n7266), .C(n7265), .Y(n1804) );
NAND2X2TS U3931 ( .A(n8761), .B(n8245), .Y(n9828) );
OAI21X1TS U3932 ( .A0(n7326), .A1(n6990), .B0(n6858), .Y(n1814) );
NAND2X2TS U3933 ( .A(n8761), .B(n8246), .Y(n9829) );
ADDFHX2TS U3934 ( .A(n5683), .B(n5682), .CI(n5681), .CO(n5804), .S(n5806) );
OAI21X1TS U3935 ( .A0(n5896), .A1(n8761), .B0(n3020), .Y(n1561) );
INVX3TS U3936 ( .A(n5935), .Y(n5937) );
NAND2X2TS U3937 ( .A(n9751), .B(n8243), .Y(n9832) );
XOR3X2TS U3938 ( .A(n5772), .B(n5771), .C(n5770), .Y(n5773) );
NAND2X2TS U3939 ( .A(n9751), .B(n8244), .Y(n9831) );
NAND2X2TS U3940 ( .A(n8242), .B(n8761), .Y(n9830) );
NAND2X2TS U3941 ( .A(n8093), .B(n8247), .Y(n6133) );
INVX6TS U3942 ( .A(n4264), .Y(n3445) );
NAND2X2TS U3943 ( .A(n8761), .B(n8247), .Y(n9834) );
NAND2X2TS U3944 ( .A(n9751), .B(n8248), .Y(n9835) );
AND2X8TS U3945 ( .A(n4838), .B(n4837), .Y(n2651) );
NAND3X2TS U3946 ( .A(n7763), .B(n7762), .C(n7761), .Y(n1528) );
NAND2X2TS U3947 ( .A(n9751), .B(n8250), .Y(n9833) );
NAND2X1TS U3948 ( .A(n6409), .B(n6408), .Y(n6410) );
NAND2X8TS U3949 ( .A(n4838), .B(n4839), .Y(n7042) );
NOR2X8TS U3950 ( .A(n4840), .B(n4839), .Y(n7044) );
NAND2X2TS U3951 ( .A(n7760), .B(n8250), .Y(n6136) );
NAND2X2TS U3952 ( .A(n8761), .B(n8070), .Y(n9826) );
NAND2X2TS U3953 ( .A(n8761), .B(n8241), .Y(n9827) );
NAND2X1TS U3954 ( .A(n6362), .B(n6404), .Y(n6363) );
OAI21X1TS U3955 ( .A0(n6391), .A1(n6385), .B0(n6392), .Y(n6336) );
NAND2X4TS U3956 ( .A(n4120), .B(n4119), .Y(n5879) );
XOR2X2TS U3957 ( .A(n6124), .B(n9044), .Y(n6125) );
INVX2TS U3958 ( .A(n6405), .Y(n6362) );
NAND3X4TS U3959 ( .A(n4984), .B(n4983), .C(n4982), .Y(n1521) );
NAND2X4TS U3960 ( .A(n3545), .B(n3544), .Y(n5714) );
INVX3TS U3961 ( .A(n6335), .Y(n5661) );
MXI2X1TS U3962 ( .A(n6764), .B(n7708), .S0(n8774), .Y(n1324) );
XNOR2X2TS U3963 ( .A(n7506), .B(n7505), .Y(n7507) );
NAND3X1TS U3964 ( .A(n6923), .B(n6922), .C(n6921), .Y(n2078) );
OAI21X2TS U3965 ( .A0(n4151), .A1(n4150), .B0(n4149), .Y(n4152) );
NAND2X6TS U3966 ( .A(n4092), .B(n4093), .Y(n5856) );
NAND2X1TS U3967 ( .A(n8345), .B(n8344), .Y(n2079) );
CMPR22X2TS U3968 ( .A(add_x_246_A_3_), .B(n6435), .CO(n9083), .S(n9084) );
INVX2TS U3969 ( .A(n6016), .Y(n3382) );
INVX4TS U3970 ( .A(n4679), .Y(n3422) );
NAND2X2TS U3971 ( .A(n6185), .B(n6121), .Y(n6123) );
NAND2X6TS U3972 ( .A(n2703), .B(n2312), .Y(n3495) );
NOR2X1TS U3973 ( .A(n6918), .B(n6763), .Y(n6764) );
NOR2X2TS U3974 ( .A(n6790), .B(n6789), .Y(n8339) );
INVX6TS U3975 ( .A(n6323), .Y(n5394) );
NAND4X1TS U3976 ( .A(n7673), .B(n7672), .C(n7671), .D(n7670), .Y(n1932) );
NAND4X1TS U3977 ( .A(n7600), .B(n7599), .C(n7598), .D(n7597), .Y(n1832) );
NAND4X1TS U3978 ( .A(n7554), .B(n7553), .C(n7552), .D(n7551), .Y(n1838) );
NAND3X4TS U3979 ( .A(n4996), .B(n4995), .C(n4994), .Y(add_x_246_A_3_) );
NAND4X1TS U3980 ( .A(n8224), .B(n8223), .C(n8222), .D(n8221), .Y(n1931) );
NAND4X1TS U3981 ( .A(n7584), .B(n7583), .C(n7582), .D(n7581), .Y(n1835) );
NAND4X1TS U3982 ( .A(n8168), .B(n8167), .C(n8166), .D(n8165), .Y(n1934) );
NAND4X1TS U3983 ( .A(n8152), .B(n8151), .C(n8150), .D(n8149), .Y(n1843) );
NAND4X1TS U3984 ( .A(n7643), .B(n7642), .C(n7641), .D(n7640), .Y(n1935) );
NOR2X4TS U3985 ( .A(n6126), .B(n9047), .Y(n6111) );
NAND4X1TS U3986 ( .A(n7657), .B(n7656), .C(n7655), .D(n7654), .Y(n1920) );
NAND4X1TS U3987 ( .A(n7619), .B(n7618), .C(n7617), .D(n7616), .Y(n1840) );
NAND3X2TS U3988 ( .A(n8122), .B(n8121), .C(n8120), .Y(n8341) );
NAND4X1TS U3989 ( .A(n8172), .B(n8171), .C(n8170), .D(n8169), .Y(n1941) );
NAND3X1TS U3990 ( .A(n8770), .B(n8769), .C(n8768), .Y(n1730) );
NAND4X1TS U3991 ( .A(n8156), .B(n8155), .C(n8154), .D(n8153), .Y(n1836) );
NAND4X1TS U3992 ( .A(n7651), .B(n7650), .C(n7649), .D(n7648), .Y(n1928) );
NAND4X1TS U3993 ( .A(n7546), .B(n7545), .C(n7544), .D(n7543), .Y(n1837) );
NAND4X1TS U3994 ( .A(n8185), .B(n8184), .C(n8183), .D(n8182), .Y(n1942) );
NAND4X1TS U3995 ( .A(n7558), .B(n7557), .C(n7556), .D(n7555), .Y(n1938) );
NAND4X1TS U3996 ( .A(n7669), .B(n7668), .C(n7667), .D(n7666), .Y(n1929) );
NAND4X1TS U3997 ( .A(n8164), .B(n8163), .C(n8162), .D(n8161), .Y(n1943) );
NAND4X1TS U3998 ( .A(n7615), .B(n7614), .C(n7613), .D(n7612), .Y(n1940) );
NAND2X2TS U3999 ( .A(n8689), .B(n8688), .Y(n8695) );
NAND4X1TS U4000 ( .A(n7689), .B(n7688), .C(n7687), .D(n7686), .Y(n1930) );
NAND4X1TS U4001 ( .A(n7706), .B(n7705), .C(n7704), .D(n7703), .Y(n1921) );
NAND4X1TS U4002 ( .A(n8207), .B(n8206), .C(n8205), .D(n8204), .Y(n1914) );
NAND2X2TS U4003 ( .A(n7737), .B(FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n9968) );
NAND4X1TS U4004 ( .A(n7542), .B(n7541), .C(n7540), .D(n7539), .Y(n1820) );
NAND4X1TS U4005 ( .A(n7696), .B(n7692), .C(n7691), .D(n7690), .Y(n1825) );
NAND3X4TS U4006 ( .A(n5036), .B(n5035), .C(n5034), .Y(n1517) );
NAND4X1TS U4007 ( .A(n7700), .B(n7699), .C(n7698), .D(n7697), .Y(n1824) );
MX2X2TS U4008 ( .A(n8037), .B(FPMULT_exp_oper_result[7]), .S0(n9840), .Y(
n1542) );
NAND4X1TS U4009 ( .A(n7631), .B(n7630), .C(n7629), .D(n7628), .Y(n1919) );
AND2X2TS U4010 ( .A(n6355), .B(n6354), .Y(n6356) );
NAND4X1TS U4011 ( .A(n7538), .B(n7537), .C(n7536), .D(n7535), .Y(n1819) );
NAND4X1TS U4012 ( .A(n7635), .B(n7634), .C(n7633), .D(n7632), .Y(n1927) );
AOI21X2TS U4013 ( .A0(n8135), .A1(n7898), .B0(n8037), .Y(n9842) );
INVX4TS U4014 ( .A(n6100), .Y(n6127) );
NAND2X1TS U4015 ( .A(n8210), .B(FPSENCOS_d_ff2_X[26]), .Y(n7637) );
NAND3X2TS U4016 ( .A(n6743), .B(n3623), .C(n6742), .Y(n8689) );
NAND2X1TS U4017 ( .A(n8765), .B(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n7571) );
OAI2BB1X2TS U4018 ( .A0N(n3536), .A1N(n3535), .B0(n4523), .Y(n4525) );
MX2X2TS U4019 ( .A(n6751), .B(FPMULT_Add_result[17]), .S0(n6747), .Y(n1607)
);
OAI21X1TS U4020 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[1]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[0]), .B0(n8114), .Y(n6788) );
INVX2TS U4021 ( .A(n4320), .Y(n3047) );
OA21X2TS U4022 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(
overflow_flag_addsubt), .B0(n7740), .Y(n9094) );
CLKMX2X3TS U4023 ( .A(n7892), .B(FPMULT_exp_oper_result[0]), .S0(n9840), .Y(
n1549) );
NAND2X2TS U4024 ( .A(n8071), .B(n1576), .Y(n5034) );
NAND2X2TS U4025 ( .A(n8209), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n7517) );
CLKMX2X3TS U4026 ( .A(n7893), .B(FPMULT_exp_oper_result[1]), .S0(n9840), .Y(
n1548) );
NAND2X4TS U4027 ( .A(n8121), .B(n4827), .Y(n4828) );
BUFX8TS U4028 ( .A(n7601), .Y(n8216) );
BUFX4TS U4029 ( .A(n7601), .Y(n7701) );
BUFX12TS U4030 ( .A(n4962), .Y(n2329) );
OAI2BB1X1TS U4031 ( .A0N(n8232), .A1N(operation[0]), .B0(n8231), .Y(n1733)
);
NAND2X6TS U4032 ( .A(n3522), .B(n4447), .Y(n4439) );
CLKMX2X3TS U4033 ( .A(n8588), .B(FPMULT_P_Sgf[0]), .S0(n9752), .Y(n1553) );
ADDHX2TS U4034 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n6750), .CO(n6434),
.S(n6751) );
BUFX8TS U4035 ( .A(n7601), .Y(n8173) );
BUFX4TS U4036 ( .A(n7603), .Y(n7702) );
INVX3TS U4037 ( .A(n5459), .Y(n5400) );
NOR2X2TS U4038 ( .A(n7732), .B(n7738), .Y(n7733) );
NAND3X1TS U4039 ( .A(n6659), .B(n6658), .C(n6657), .Y(n1728) );
BUFX4TS U4040 ( .A(n8195), .Y(n8232) );
INVX3TS U4041 ( .A(n4085), .Y(n3367) );
NAND2X6TS U4042 ( .A(n6786), .B(n9096), .Y(n8337) );
NAND2X1TS U4043 ( .A(n8861), .B(n2750), .Y(n2563) );
INVX4TS U4044 ( .A(n8091), .Y(n2914) );
NAND4X1TS U4045 ( .A(n7937), .B(n8078), .C(n7936), .D(n7935), .Y(n1206) );
AO22X1TS U4046 ( .A0(n8662), .A1(FPSENCOS_d_ff_Yn[3]), .B0(
FPSENCOS_d_ff2_Y[3]), .B1(n8233), .Y(n1903) );
AO22X2TS U4047 ( .A0(n8662), .A1(FPSENCOS_d_ff_Yn[14]), .B0(
FPSENCOS_d_ff2_Y[14]), .B1(n8233), .Y(n1881) );
AO22X1TS U4048 ( .A0(n6637), .A1(FPSENCOS_d_ff_Yn[19]), .B0(
FPSENCOS_d_ff2_Y[19]), .B1(n8599), .Y(n1871) );
AO22X1TS U4049 ( .A0(n6637), .A1(FPSENCOS_d_ff_Xn[8]), .B0(
FPSENCOS_d_ff2_X[8]), .B1(n6636), .Y(n1991) );
AO22X2TS U4050 ( .A0(n8600), .A1(FPSENCOS_d_ff_Yn[20]), .B0(
FPSENCOS_d_ff2_Y[20]), .B1(n8599), .Y(n1869) );
AO22X2TS U4051 ( .A0(n8600), .A1(FPSENCOS_d_ff_Xn[23]), .B0(
FPSENCOS_d_ff2_X[23]), .B1(n8601), .Y(n1961) );
AO22X2TS U4052 ( .A0(n6634), .A1(FPSENCOS_d_ff_Xn[11]), .B0(
FPSENCOS_d_ff2_X[11]), .B1(n8233), .Y(n1985) );
AO22X1TS U4053 ( .A0(n6637), .A1(FPSENCOS_d_ff_Yn[8]), .B0(
FPSENCOS_d_ff2_Y[8]), .B1(n6636), .Y(n1893) );
NAND2X1TS U4054 ( .A(n8679), .B(FPSENCOS_d_ff_Yn[0]), .Y(n6659) );
AO22X2TS U4055 ( .A0(n6634), .A1(FPSENCOS_d_ff_Yn[4]), .B0(
FPSENCOS_d_ff2_Y[4]), .B1(n8233), .Y(n1901) );
NAND2X1TS U4056 ( .A(n6646), .B(n6645), .Y(n2125) );
OAI2BB1X1TS U4057 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[7]), .B0(n6681), .Y(
n1759) );
AO22X2TS U4058 ( .A0(n8600), .A1(FPSENCOS_d_ff_Xn[31]), .B0(
FPSENCOS_d_ff2_X[31]), .B1(n8599), .Y(n1945) );
AO22X2TS U4059 ( .A0(n6634), .A1(FPSENCOS_d_ff_Xn[4]), .B0(
FPSENCOS_d_ff2_X[4]), .B1(n8233), .Y(n1999) );
OAI2BB1X1TS U4060 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[8]), .B0(n6683), .Y(
n1758) );
NAND2X1TS U4061 ( .A(n6641), .B(n6645), .Y(n2135) );
OAI2BB1X1TS U4062 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[11]), .B0(n8228), .Y(
n1755) );
OAI2BB1X1TS U4063 ( .A0N(n7475), .A1N(n7350), .B0(n7349), .Y(n1323) );
OAI2BB1X1TS U4064 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[5]), .B0(n8665), .Y(
n1761) );
OAI2BB1X1TS U4065 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[22]), .B0(n8668), .Y(
n1744) );
AO22X2TS U4066 ( .A0(n6634), .A1(FPSENCOS_d_ff_Yn[18]), .B0(
FPSENCOS_d_ff2_Y[18]), .B1(n8599), .Y(n1873) );
OAI2BB1X1TS U4067 ( .A0N(n6688), .A1N(FPSENCOS_d_ff_Zn[29]), .B0(n6685), .Y(
n1737) );
NAND2X1TS U4068 ( .A(n8319), .B(n8318), .Y(n2131) );
NAND2X4TS U4069 ( .A(n4768), .B(n2509), .Y(n6140) );
AO22X2TS U4070 ( .A0(n6634), .A1(FPSENCOS_d_ff_Yn[10]), .B0(
FPSENCOS_d_ff2_Y[10]), .B1(n8599), .Y(n1889) );
OAI2BB1X1TS U4071 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[10]), .B0(n8139), .Y(
n1756) );
OAI2BB1X1TS U4072 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[17]), .B0(n8144), .Y(
n1749) );
AO22X1TS U4073 ( .A0(n6637), .A1(FPSENCOS_d_ff_Yn[0]), .B0(
FPSENCOS_d_ff2_Y[0]), .B1(n8592), .Y(n1909) );
OAI2BB1X1TS U4074 ( .A0N(n7475), .A1N(n7368), .B0(n7367), .Y(n1319) );
OAI2BB1X1TS U4075 ( .A0N(n8662), .A1N(FPSENCOS_d_ff_Zn[2]), .B0(n8143), .Y(
n1764) );
OAI2BB1X1TS U4076 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[14]), .B0(n8142), .Y(
n1752) );
OAI2BB1X1TS U4077 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[21]), .B0(n8108), .Y(
n1745) );
OAI2BB1X1TS U4078 ( .A0N(n8662), .A1N(FPSENCOS_d_ff_Zn[0]), .B0(n8140), .Y(
n1766) );
AO22X2TS U4079 ( .A0(n8600), .A1(FPSENCOS_d_ff_Yn[30]), .B0(
FPSENCOS_d_ff2_Y[30]), .B1(n8599), .Y(n1856) );
OAI2BB1X1TS U4080 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[3]), .B0(n8138), .Y(
n1763) );
NAND2X6TS U4081 ( .A(n3523), .B(n4456), .Y(n4449) );
OAI2BB1X1TS U4082 ( .A0N(n8662), .A1N(FPSENCOS_d_ff_Zn[19]), .B0(n8137), .Y(
n1747) );
NAND2X1TS U4083 ( .A(n8828), .B(n8842), .Y(n2750) );
OAI2BB1X1TS U4084 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[15]), .B0(n8113), .Y(
n1751) );
AO22X1TS U4085 ( .A0(n6637), .A1(FPSENCOS_d_ff_Yn[22]), .B0(
FPSENCOS_d_ff2_Y[22]), .B1(n8601), .Y(n1865) );
AO22X2TS U4086 ( .A0(n8600), .A1(FPSENCOS_d_ff_Yn[6]), .B0(
FPSENCOS_d_ff2_Y[6]), .B1(n6636), .Y(n1897) );
OAI2BB1X1TS U4087 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[16]), .B0(n8109), .Y(
n1750) );
OAI2BB1X1TS U4088 ( .A0N(n7475), .A1N(n7455), .B0(n7454), .Y(n1322) );
OAI2BB1X1TS U4089 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[9]), .B0(n8110), .Y(
n1757) );
NAND4X1TS U4090 ( .A(n7926), .B(n7925), .C(n8078), .D(n7924), .Y(n1205) );
BUFX12TS U4091 ( .A(n5720), .Y(n2331) );
OAI2BB1X1TS U4092 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[4]), .B0(n8112), .Y(
n1762) );
OR2X8TS U4093 ( .A(n6030), .B(n9219), .Y(n5007) );
NAND4X1TS U4094 ( .A(n8079), .B(n8078), .C(n8077), .D(n8076), .Y(n1201) );
AO22X2TS U4095 ( .A0(n8662), .A1(FPSENCOS_d_ff_Yn[13]), .B0(
FPSENCOS_d_ff2_Y[13]), .B1(n8233), .Y(n1883) );
OAI2BB1X1TS U4096 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[6]), .B0(n8111), .Y(
n1760) );
AO22X1TS U4097 ( .A0(n6637), .A1(FPSENCOS_d_ff_Yn[9]), .B0(
FPSENCOS_d_ff2_Y[9]), .B1(n6636), .Y(n1891) );
OAI2BB1X1TS U4098 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[1]), .B0(n8148), .Y(
n1765) );
AO22X2TS U4099 ( .A0(n8600), .A1(FPSENCOS_d_ff_Yn[5]), .B0(
FPSENCOS_d_ff2_Y[5]), .B1(n8233), .Y(n1899) );
OAI2BB1X1TS U4100 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[12]), .B0(n8107), .Y(
n1754) );
NAND3X1TS U4101 ( .A(n7775), .B(n7774), .C(n7773), .Y(n1197) );
OAI2BB1X1TS U4102 ( .A0N(n8669), .A1N(FPSENCOS_d_ff_Zn[13]), .B0(n8146), .Y(
n1753) );
AO22X1TS U4103 ( .A0(n6637), .A1(FPSENCOS_d_ff_Yn[2]), .B0(
FPSENCOS_d_ff2_Y[2]), .B1(n8599), .Y(n1905) );
AO22X1TS U4104 ( .A0(n6637), .A1(FPSENCOS_d_ff_Yn[7]), .B0(
FPSENCOS_d_ff2_Y[7]), .B1(n6636), .Y(n1895) );
AO22X2TS U4105 ( .A0(n6634), .A1(FPSENCOS_d_ff_Yn[11]), .B0(
FPSENCOS_d_ff2_Y[11]), .B1(n8233), .Y(n1887) );
AO22X2TS U4106 ( .A0(n6634), .A1(FPSENCOS_d_ff_Yn[15]), .B0(
FPSENCOS_d_ff2_Y[15]), .B1(n6636), .Y(n1879) );
OAI2BB1X1TS U4107 ( .A0N(n8662), .A1N(FPSENCOS_d_ff_Zn[18]), .B0(n8145), .Y(
n1748) );
OAI2BB1X1TS U4108 ( .A0N(n7475), .A1N(n7080), .B0(n7079), .Y(n1335) );
NAND2X1TS U4109 ( .A(n9932), .B(n7772), .Y(n7786) );
NAND2X1TS U4110 ( .A(n9933), .B(n7772), .Y(n7775) );
BUFX12TS U4111 ( .A(n8591), .Y(n8600) );
INVX4TS U4112 ( .A(n8587), .Y(n4936) );
AND2X2TS U4113 ( .A(n4990), .B(n4989), .Y(n4991) );
NAND2X1TS U4114 ( .A(n8611), .B(n8225), .Y(n2124) );
INVX2TS U4115 ( .A(n8813), .Y(n8861) );
NAND4X1TS U4116 ( .A(n8057), .B(n8056), .C(n8055), .D(n8054), .Y(n1188) );
MXI2X1TS U4117 ( .A(n8331), .B(n3647), .S0(n8506), .Y(n1947) );
NOR2X1TS U4118 ( .A(n8819), .B(n8829), .Y(n8842) );
BUFX12TS U4119 ( .A(n8591), .Y(n6634) );
NOR2X1TS U4120 ( .A(n2743), .B(n8992), .Y(n2577) );
NAND2X6TS U4121 ( .A(n2996), .B(n4484), .Y(n2995) );
NAND4X1TS U4122 ( .A(n8046), .B(n8056), .C(n8045), .D(n8044), .Y(n1189) );
BUFX12TS U4123 ( .A(n8591), .Y(n8598) );
NAND4X1TS U4124 ( .A(n8068), .B(n8078), .C(n8067), .D(n8066), .Y(n1200) );
NAND2X1TS U4125 ( .A(n8315), .B(n8323), .Y(n2120) );
BUFX8TS U4126 ( .A(n6635), .Y(n6637) );
NAND2X6TS U4127 ( .A(n5380), .B(n3489), .Y(n5427) );
ADDFHX2TS U4128 ( .A(DP_OP_26J248_126_1325_n28), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .CI(n7715), .CO(n7731), .S(n8715) );
OAI21X1TS U4129 ( .A0(n2836), .A1(n9234), .B0(n6917), .Y(n1353) );
NAND2X1TS U4130 ( .A(n8789), .B(n8609), .Y(n8612) );
NAND2X1TS U4131 ( .A(n9937), .B(n7772), .Y(n8061) );
OAI2BB1X1TS U4132 ( .A0N(n7416), .A1N(n6973), .B0(n6972), .Y(n1338) );
NAND4X1TS U4133 ( .A(n7940), .B(n8056), .C(n7939), .D(n7938), .Y(n1183) );
NAND2BX1TS U4134 ( .AN(n8780), .B(n8240), .Y(n2116) );
NAND2X1TS U4135 ( .A(n8789), .B(n8234), .Y(n6632) );
BUFX16TS U4136 ( .A(n5196), .Y(n5463) );
OAI2BB1X1TS U4137 ( .A0N(n7475), .A1N(n7041), .B0(n7040), .Y(n1336) );
NAND2X1TS U4138 ( .A(n8323), .B(n8235), .Y(n2128) );
NAND2X4TS U4139 ( .A(n4761), .B(n2513), .Y(n7744) );
INVX6TS U4140 ( .A(n5326), .Y(n3337) );
OR2X2TS U4141 ( .A(n8884), .B(n8864), .Y(n2552) );
OAI21X1TS U4142 ( .A0(n6230), .A1(n6229), .B0(n6228), .Y(n6231) );
INVX6TS U4143 ( .A(n4099), .Y(n4189) );
OR2X2TS U4144 ( .A(n8871), .B(n3632), .Y(n8882) );
NOR2X2TS U4145 ( .A(n8238), .B(FPSENCOS_cont_iter_out[3]), .Y(n8780) );
NOR2X1TS U4146 ( .A(n6412), .B(n8998), .Y(n9024) );
NAND2X2TS U4147 ( .A(n4917), .B(n4916), .Y(n4919) );
OAI2BB1X1TS U4148 ( .A0N(n7416), .A1N(n6899), .B0(n6898), .Y(n1341) );
BUFX8TS U4149 ( .A(n8141), .Y(n6636) );
NAND2X2TS U4150 ( .A(n8784), .B(n8583), .Y(n8323) );
BUFX8TS U4151 ( .A(n8141), .Y(n8233) );
BUFX8TS U4152 ( .A(n8141), .Y(n8592) );
NOR2X1TS U4153 ( .A(n8888), .B(n8885), .Y(n8887) );
INVX2TS U4154 ( .A(n8888), .Y(n2809) );
NOR2X1TS U4155 ( .A(n6262), .B(n8815), .Y(n8820) );
AND2X2TS U4156 ( .A(n8871), .B(n3632), .Y(n8893) );
ADDFHX2TS U4157 ( .A(DP_OP_26J248_126_1325_n28), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .CI(n7728), .CO(n7715), .S(n8710) );
NAND3X1TS U4158 ( .A(n7791), .B(n7790), .C(n7789), .Y(n1196) );
OAI21X1TS U4159 ( .A0(n8998), .A1(n8994), .B0(n9032), .Y(n2574) );
AND2X2TS U4160 ( .A(n6267), .B(n8894), .Y(n8920) );
NAND2X1TS U4161 ( .A(n3618), .B(n9032), .Y(n2569) );
BUFX8TS U4162 ( .A(n8141), .Y(n8593) );
NAND2BX1TS U4163 ( .AN(n3632), .B(n1671), .Y(n8922) );
NOR2X1TS U4164 ( .A(n8894), .B(n8911), .Y(n8924) );
NOR2X1TS U4165 ( .A(n8865), .B(n8885), .Y(n8912) );
NAND2X2TS U4166 ( .A(n4235), .B(n4278), .Y(n4240) );
NOR2X1TS U4167 ( .A(n8865), .B(n8890), .Y(n8889) );
NOR2X1TS U4168 ( .A(n3632), .B(n6274), .Y(n8895) );
OAI21X2TS U4169 ( .A0(n8997), .A1(n8988), .B0(n8982), .Y(n9002) );
MX2X2TS U4170 ( .A(n6733), .B(n9684), .S0(n2296), .Y(n1574) );
NAND2X6TS U4171 ( .A(n2792), .B(FPMULT_Op_MX[11]), .Y(n2791) );
BUFX8TS U4172 ( .A(n8141), .Y(n8601) );
NAND2X6TS U4173 ( .A(n3086), .B(n3085), .Y(n3965) );
BUFX16TS U4174 ( .A(n6635), .Y(n8591) );
MXI2X1TS U4175 ( .A(n9930), .B(n9476), .S0(n8683), .Y(n1195) );
INVX8TS U4176 ( .A(n2374), .Y(n5558) );
NAND2X4TS U4177 ( .A(n5237), .B(n5236), .Y(n3326) );
BUFX8TS U4178 ( .A(n8141), .Y(n8599) );
INVX8TS U4179 ( .A(n6656), .Y(n8326) );
NOR2X2TS U4180 ( .A(n6282), .B(n1628), .Y(n8992) );
AND2X2TS U4181 ( .A(n9685), .B(n1675), .Y(n8891) );
NAND2X6TS U4182 ( .A(n4913), .B(n3026), .Y(n4907) );
NAND2X1TS U4183 ( .A(n8314), .B(n8313), .Y(n2140) );
NAND2BX1TS U4184 ( .AN(n8880), .B(n1643), .Y(n8886) );
BUFX6TS U4185 ( .A(n8065), .Y(n7772) );
AND2X2TS U4186 ( .A(n8673), .B(FPSENCOS_d_ff2_Y[29]), .Y(n8332) );
NAND2X1TS U4187 ( .A(n8790), .B(n9289), .Y(n2115) );
NOR2X1TS U4188 ( .A(n8871), .B(n3627), .Y(n8923) );
AND2X2TS U4189 ( .A(n8670), .B(FPSENCOS_d_ff2_X[29]), .Y(n8330) );
NOR2X2TS U4190 ( .A(n8670), .B(FPSENCOS_d_ff2_X[29]), .Y(n8684) );
INVX4TS U4191 ( .A(n6245), .Y(n9683) );
ADDHX1TS U4192 ( .A(n1634), .B(n9700), .CO(n6367), .S(n8999) );
NAND2X2TS U4193 ( .A(n4200), .B(n4199), .Y(n4238) );
INVX4TS U4194 ( .A(n4315), .Y(n4188) );
NAND2X6TS U4195 ( .A(n3344), .B(n3341), .Y(n2966) );
INVX2TS U4196 ( .A(n1671), .Y(n8890) );
NAND2X6TS U4197 ( .A(n2360), .B(n2358), .Y(n3899) );
INVX2TS U4198 ( .A(n4847), .Y(n4849) );
NOR2X2TS U4199 ( .A(n8673), .B(FPSENCOS_d_ff2_Y[29]), .Y(n8686) );
NAND2X6TS U4200 ( .A(n6920), .B(n9226), .Y(n4825) );
BUFX4TS U4201 ( .A(n3709), .Y(n2833) );
NAND2BX1TS U4202 ( .AN(n9639), .B(n8812), .Y(n9018) );
AND2X2TS U4203 ( .A(n9640), .B(DP_OP_497J248_123_1725_n357), .Y(n9019) );
INVX12TS U4204 ( .A(n3709), .Y(n8141) );
BUFX8TS U4205 ( .A(n5379), .Y(n3383) );
OAI2BB1X1TS U4206 ( .A0N(n7416), .A1N(n6643), .B0(n6642), .Y(n1350) );
CLKINVX2TS U4207 ( .A(n8635), .Y(n7726) );
NOR2X6TS U4208 ( .A(n8783), .B(n9242), .Y(n8784) );
INVX2TS U4209 ( .A(n9692), .Y(n8815) );
NOR2X1TS U4210 ( .A(n8865), .B(n6274), .Y(n8869) );
INVX4TS U4211 ( .A(n1600), .Y(n4697) );
INVX2TS U4212 ( .A(n2390), .Y(n2389) );
NOR2X1TS U4213 ( .A(n8871), .B(n8898), .Y(n2566) );
OAI22X2TS U4214 ( .A0(n6595), .A1(n6594), .B0(n8383), .B1(n6593), .Y(n6607)
);
NOR2X1TS U4215 ( .A(n8811), .B(n8839), .Y(n2557) );
AND2X2TS U4216 ( .A(n7954), .B(n7953), .Y(n9930) );
NAND2X2TS U4217 ( .A(n1672), .B(n9701), .Y(n8982) );
AND2X2TS U4218 ( .A(n7950), .B(n7953), .Y(n9929) );
INVX12TS U4219 ( .A(n5197), .Y(n5473) );
NOR2X2TS U4220 ( .A(n1672), .B(n9701), .Y(n8997) );
MXI2X1TS U4221 ( .A(n9184), .B(n9499), .S0(n8682), .Y(n1302) );
NOR2X4TS U4222 ( .A(n8680), .B(n9902), .Y(n3701) );
MXI2X1TS U4223 ( .A(n9190), .B(n9483), .S0(n8682), .Y(n1288) );
NAND2X1TS U4224 ( .A(n3730), .B(n3729), .Y(n8497) );
NAND2X1TS U4225 ( .A(n7981), .B(n2908), .Y(n7960) );
NAND2X1TS U4226 ( .A(n9948), .B(n2908), .Y(n8052) );
INVX4TS U4227 ( .A(n4905), .Y(n4071) );
NOR2X4TS U4228 ( .A(n8680), .B(FPADDSUB_left_right_SHT2), .Y(n8065) );
MXI2X1TS U4229 ( .A(n9182), .B(n9494), .S0(n8681), .Y(n1281) );
MXI2X1TS U4230 ( .A(n9191), .B(n9489), .S0(n8682), .Y(n1295) );
NAND2X1TS U4231 ( .A(n9951), .B(n2908), .Y(n7987) );
MXI2X1TS U4232 ( .A(n9187), .B(n9485), .S0(n8682), .Y(n1236) );
NAND2X1TS U4233 ( .A(n9959), .B(n2908), .Y(n8042) );
MXI2X1TS U4234 ( .A(n9183), .B(n9484), .S0(n8681), .Y(n1252) );
MXI2X1TS U4235 ( .A(n9186), .B(n9482), .S0(n8682), .Y(n1274) );
INVX6TS U4236 ( .A(n4901), .Y(n2332) );
BUFX4TS U4237 ( .A(n6248), .Y(n9692) );
BUFX4TS U4238 ( .A(n6288), .Y(n9696) );
MXI2X1TS U4239 ( .A(FPSENCOS_cont_iter_out[3]), .B(n8788), .S0(n8495), .Y(
n8314) );
BUFX4TS U4240 ( .A(n6264), .Y(n9686) );
INVX4TS U4241 ( .A(n6262), .Y(n9640) );
NAND2X1TS U4242 ( .A(n7260), .B(n6620), .Y(n2081) );
NAND2X1TS U4243 ( .A(n8375), .B(FPSENCOS_cont_var_out[0]), .Y(n6823) );
BUFX6TS U4244 ( .A(n1646), .Y(n9700) );
NAND2X1TS U4245 ( .A(n2646), .B(n6618), .Y(n2080) );
AOI22X1TS U4246 ( .A0(n8343), .A1(FPADDSUB_Shift_amount_SHT1_EWR[2]), .B0(
FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n8342), .Y(n8344) );
MXI2X1TS U4247 ( .A(n9174), .B(n9496), .S0(n8681), .Y(n1228) );
NAND2X2TS U4248 ( .A(n4749), .B(n4747), .Y(n4746) );
BUFX8TS U4249 ( .A(n3716), .Y(n2333) );
MXI2X1TS U4250 ( .A(n9175), .B(n9500), .S0(n8681), .Y(n1216) );
BUFX12TS U4251 ( .A(n8507), .Y(n8506) );
MXI2X1TS U4252 ( .A(n9177), .B(n9491), .S0(n8681), .Y(n1260) );
MXI2X1TS U4253 ( .A(n9181), .B(n9490), .S0(n8681), .Y(n1264) );
MXI2X1TS U4254 ( .A(n9189), .B(n9486), .S0(n8682), .Y(n1309) );
NAND2X2TS U4255 ( .A(n4089), .B(n4088), .Y(n4090) );
MXI2X1TS U4256 ( .A(n9178), .B(n9487), .S0(n8681), .Y(n1244) );
INVX2TS U4257 ( .A(n4091), .Y(n3926) );
MXI2X1TS U4258 ( .A(n9185), .B(n9497), .S0(n8682), .Y(n1240) );
MXI2X1TS U4259 ( .A(n9180), .B(n9492), .S0(n8681), .Y(n1256) );
MXI2X1TS U4260 ( .A(n9179), .B(n9488), .S0(n8681), .Y(n1268) );
MXI2X1TS U4261 ( .A(n9176), .B(n9498), .S0(n8681), .Y(n1212) );
MXI2X1TS U4262 ( .A(n9188), .B(n9493), .S0(n8682), .Y(n1325) );
NAND2X6TS U4263 ( .A(n5304), .B(n5305), .Y(n5398) );
BUFX12TS U4264 ( .A(n8507), .Y(n8503) );
INVX2TS U4265 ( .A(DP_OP_496J248_122_3540_n1475), .Y(n8837) );
NAND2X1TS U4266 ( .A(n7055), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4831) );
OR2X4TS U4267 ( .A(n4940), .B(n4939), .Y(n4949) );
NAND2X2TS U4268 ( .A(n4861), .B(n4860), .Y(n4863) );
BUFX12TS U4269 ( .A(n8507), .Y(n8504) );
NAND2BX2TS U4270 ( .AN(n4864), .B(n4865), .Y(n3300) );
INVX2TS U4271 ( .A(n1636), .Y(n8810) );
INVX2TS U4272 ( .A(n1672), .Y(n8870) );
INVX2TS U4273 ( .A(n5824), .Y(n2943) );
INVX2TS U4274 ( .A(n1631), .Y(n8807) );
INVX2TS U4275 ( .A(n1628), .Y(n8821) );
NOR2X4TS U4276 ( .A(n8680), .B(n9466), .Y(n7795) );
INVX2TS U4277 ( .A(n1669), .Y(n8805) );
INVX2TS U4278 ( .A(n1638), .Y(n8806) );
INVX2TS U4279 ( .A(n1634), .Y(n8808) );
OAI21X1TS U4280 ( .A0(n7070), .A1(n7117), .B0(n7126), .Y(n6961) );
ADDHX1TS U4281 ( .A(n1666), .B(n1678), .CO(n9005), .S(n9006) );
INVX2TS U4282 ( .A(n1665), .Y(n8822) );
NAND2X2TS U4283 ( .A(n4686), .B(n4685), .Y(n5104) );
INVX2TS U4284 ( .A(n1681), .Y(n8879) );
INVX2TS U4285 ( .A(n1678), .Y(n8918) );
INVX6TS U4286 ( .A(n1647), .Y(n8871) );
INVX2TS U4287 ( .A(n1675), .Y(n8911) );
OAI22X1TS U4288 ( .A0(n7260), .A1(n9108), .B0(n7259), .B1(n9269), .Y(n7247)
);
INVX2TS U4289 ( .A(n8867), .Y(n2334) );
INVX2TS U4290 ( .A(n1677), .Y(n8898) );
INVX4TS U4291 ( .A(DP_OP_498J248_124_1725_n796), .Y(n8812) );
NAND2X1TS U4292 ( .A(n8342), .B(FPADDSUB_bit_shift_SHT2), .Y(n6620) );
XOR2X1TS U4293 ( .A(n2846), .B(n6425), .Y(n7885) );
NAND3X2TS U4294 ( .A(n8758), .B(n8494), .C(n9461), .Y(n8375) );
AND2X2TS U4295 ( .A(n5015), .B(n5014), .Y(n5016) );
NAND2X1TS U4296 ( .A(n7211), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n6925) );
MXI2X2TS U4297 ( .A(n6280), .B(n9261), .S0(n6279), .Y(n1646) );
NAND4X2TS U4298 ( .A(n6462), .B(n6461), .C(n6460), .D(n9660), .Y(n8352) );
AOI21X1TS U4299 ( .A0(n6844), .A1(n6860), .B0(n6866), .Y(n6832) );
AOI21X1TS U4300 ( .A0(n7144), .A1(n7135), .B0(n7138), .Y(n7074) );
XOR2X1TS U4301 ( .A(n2846), .B(n6423), .Y(n7879) );
XOR2X1TS U4302 ( .A(n2846), .B(n6426), .Y(n7888) );
NAND4X2TS U4303 ( .A(n7178), .B(n7177), .C(n6460), .D(n9663), .Y(n8350) );
NAND2X2TS U4304 ( .A(n6564), .B(n8442), .Y(n6575) );
NAND3X2TS U4305 ( .A(n7203), .B(n7202), .C(n9658), .Y(n8560) );
NAND4X2TS U4306 ( .A(n6466), .B(n6465), .C(n6460), .D(n9661), .Y(n8353) );
NAND4X2TS U4307 ( .A(n7176), .B(n7175), .C(n7198), .D(n9673), .Y(n8508) );
NAND4X2TS U4308 ( .A(n7188), .B(n7187), .C(n6460), .D(n9666), .Y(n8558) );
NAND4X2TS U4309 ( .A(n7206), .B(n7205), .C(n6460), .D(n9662), .Y(n8555) );
NAND4X2TS U4310 ( .A(n7190), .B(n7189), .C(n7198), .D(n9668), .Y(n8580) );
MXI2X2TS U4311 ( .A(n8524), .B(n9454), .S0(n6287), .Y(n6288) );
INVX8TS U4312 ( .A(n2646), .Y(n8340) );
MXI2X2TS U4313 ( .A(n8542), .B(n9455), .S0(n6287), .Y(n6248) );
NAND4X2TS U4314 ( .A(n7180), .B(n7179), .C(n6460), .D(n9667), .Y(n8492) );
NAND2X4TS U4315 ( .A(n2407), .B(n5058), .Y(n2406) );
NAND4X2TS U4316 ( .A(n7186), .B(n7185), .C(n7198), .D(n9672), .Y(n8581) );
ADDHX2TS U4317 ( .A(n9082), .B(n6018), .CO(n4692), .S(n6019) );
NAND4X2TS U4318 ( .A(n7172), .B(n7171), .C(n6460), .D(n9659), .Y(n8351) );
AND2X2TS U4319 ( .A(n7957), .B(n3699), .Y(n9948) );
NAND4X2TS U4320 ( .A(n7168), .B(n7167), .C(n7198), .D(n9670), .Y(n8565) );
BUFX20TS U4321 ( .A(n3722), .Y(n8507) );
NAND2X1TS U4322 ( .A(n9936), .B(n2908), .Y(n7971) );
INVX3TS U4323 ( .A(n4198), .Y(n3876) );
NAND4X2TS U4324 ( .A(n7174), .B(n7173), .C(n7198), .D(n9674), .Y(n8563) );
INVX1TS U4325 ( .A(n8300), .Y(n3730) );
NAND4X2TS U4326 ( .A(n7170), .B(n7169), .C(n7198), .D(n9671), .Y(n8562) );
NAND3X2TS U4327 ( .A(n7193), .B(n7192), .C(n9655), .Y(n8557) );
MXI2X4TS U4328 ( .A(n6268), .B(n8474), .S0(n8445), .Y(n6269) );
NAND4X2TS U4329 ( .A(n7200), .B(n7199), .C(n7198), .D(n9669), .Y(n8579) );
INVX12TS U4330 ( .A(n2346), .Y(n3391) );
MX2X4TS U4331 ( .A(n8523), .B(n9259), .S0(n6287), .Y(n3627) );
NOR2X6TS U4332 ( .A(n8494), .B(n8306), .Y(n8495) );
NAND3X2TS U4333 ( .A(n7196), .B(n7195), .C(n9657), .Y(n8559) );
MXI2X4TS U4334 ( .A(n8514), .B(n9144), .S0(n6260), .Y(n6251) );
CLKMX2X2TS U4335 ( .A(n8393), .B(FPMULT_Add_result[6]), .S0(n9750), .Y(n1618) );
NOR2X1TS U4336 ( .A(n8756), .B(n8728), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
BUFX6TS U4337 ( .A(n6992), .Y(n7416) );
OAI22X1TS U4338 ( .A0(n2646), .A1(n9093), .B0(n7259), .B1(n9109), .Y(n7262)
);
AND2X4TS U4339 ( .A(n7957), .B(n7934), .Y(n9951) );
NAND3X2TS U4340 ( .A(n7053), .B(n7052), .C(n9656), .Y(n8561) );
MXI2X2TS U4341 ( .A(n6266), .B(n9383), .S0(n6279), .Y(n1645) );
MXI2X4TS U4342 ( .A(n8511), .B(n9377), .S0(n6260), .Y(n1664) );
NAND4X2TS U4343 ( .A(n7182), .B(n7181), .C(n7198), .D(n9675), .Y(n8564) );
INVX12TS U4344 ( .A(n2347), .Y(n4205) );
INVX12TS U4345 ( .A(n7211), .Y(n7260) );
NAND4X2TS U4346 ( .A(n7184), .B(n7183), .C(n6460), .D(n9665), .Y(n8556) );
AND2X2TS U4347 ( .A(n7957), .B(n7956), .Y(n7981) );
NOR2X4TS U4348 ( .A(n3759), .B(n2439), .Y(n5001) );
AND2X2TS U4349 ( .A(n7957), .B(n7807), .Y(n9959) );
NAND2X1TS U4350 ( .A(n6540), .B(n8418), .Y(n9881) );
NAND2X1TS U4351 ( .A(n6526), .B(n8439), .Y(n9872) );
BUFX3TS U4352 ( .A(n8447), .Y(n8448) );
NAND2X1TS U4353 ( .A(n8384), .B(n6610), .Y(n9853) );
NAND2X1TS U4354 ( .A(n6526), .B(n8435), .Y(n9868) );
NAND2X1TS U4355 ( .A(n6540), .B(n8414), .Y(n9885) );
NAND2X1TS U4356 ( .A(n6540), .B(n8416), .Y(n9889) );
NAND2X1TS U4357 ( .A(n6526), .B(n8434), .Y(n9863) );
NAND2X1TS U4358 ( .A(n9944), .B(n2908), .Y(n7913) );
NAND2X1TS U4359 ( .A(n6531), .B(n8399), .Y(n9898) );
NAND2X1TS U4360 ( .A(n8384), .B(n6561), .Y(n9856) );
NAND2X1TS U4361 ( .A(n6540), .B(n8415), .Y(n9890) );
NAND2X1TS U4362 ( .A(n6526), .B(n8437), .Y(n9864) );
NAND2X1TS U4363 ( .A(n6526), .B(n8420), .Y(n9878) );
NAND2X1TS U4364 ( .A(n6540), .B(n8395), .Y(n9894) );
INVX2TS U4365 ( .A(n7126), .Y(n7067) );
NAND2X1TS U4366 ( .A(n8384), .B(n8382), .Y(n9861) );
NAND2X1TS U4367 ( .A(n6531), .B(n8394), .Y(n9901) );
NAND2X1TS U4368 ( .A(n6540), .B(n8397), .Y(n9892) );
OA21XLTS U4369 ( .A0(n7407), .A1(n6914), .B0(n6913), .Y(n6915) );
NAND2X1TS U4370 ( .A(n6526), .B(n8424), .Y(n9876) );
NAND2X1TS U4371 ( .A(n8384), .B(n8553), .Y(n9859) );
OAI2BB2XLTS U4372 ( .B0(n7843), .B1(n7850), .A0N(n7842), .A1N(n7841), .Y(
n7846) );
NAND2X1TS U4373 ( .A(n6531), .B(n8400), .Y(n9899) );
NAND2X1TS U4374 ( .A(n8778), .B(n8410), .Y(n9925) );
NAND2X1TS U4375 ( .A(n8778), .B(n8427), .Y(n9950) );
NAND2X1TS U4376 ( .A(n8778), .B(n8411), .Y(n9924) );
NAND2X1TS U4377 ( .A(n8778), .B(n8413), .Y(n9926) );
BUFX6TS U4378 ( .A(n8447), .Y(n8452) );
NAND2X1TS U4379 ( .A(n8778), .B(n8408), .Y(n9927) );
NAND2X1TS U4380 ( .A(n8778), .B(n8409), .Y(n9928) );
NAND2X1TS U4381 ( .A(n8778), .B(n8430), .Y(n9954) );
NAND2X1TS U4382 ( .A(n8778), .B(n8428), .Y(n9955) );
NAND2X1TS U4383 ( .A(n6540), .B(n8429), .Y(n9957) );
NAND2X4TS U4384 ( .A(n3724), .B(n3728), .Y(n8494) );
NOR2X6TS U4385 ( .A(n8703), .B(FPADDSUB_OP_FLAG_SFG), .Y(n7038) );
NAND2X6TS U4386 ( .A(n3728), .B(n3707), .Y(n3715) );
XNOR2X1TS U4387 ( .A(n8383), .B(n8382), .Y(n6584) );
NOR2X8TS U4388 ( .A(n8774), .B(n9234), .Y(n7211) );
NAND2X1TS U4389 ( .A(n6531), .B(n8536), .Y(n9911) );
NAND2X1TS U4390 ( .A(n6540), .B(n8421), .Y(n9883) );
NAND2X1TS U4391 ( .A(n6531), .B(n8535), .Y(n9910) );
NAND2X1TS U4392 ( .A(n6531), .B(n8396), .Y(n9908) );
NAND2X1TS U4393 ( .A(n6540), .B(n8417), .Y(n9880) );
NAND2X1TS U4394 ( .A(n6526), .B(n8432), .Y(n9870) );
NAND2X1TS U4395 ( .A(n6531), .B(n8401), .Y(n9909) );
MXI2X1TS U4396 ( .A(n8774), .B(n8703), .S0(n8779), .Y(n2145) );
NAND2X1TS U4397 ( .A(n6526), .B(n8436), .Y(n9865) );
NAND2X1TS U4398 ( .A(n7780), .B(FPADDSUB_Data_array_SWR[6]), .Y(n7802) );
NAND2X1TS U4399 ( .A(n6540), .B(n8422), .Y(n9887) );
NAND2X1TS U4400 ( .A(n8384), .B(n6596), .Y(n9855) );
NAND2X1TS U4401 ( .A(n6531), .B(n8398), .Y(n9896) );
NAND2X1TS U4402 ( .A(n6531), .B(n8532), .Y(n9912) );
INVX12TS U4403 ( .A(n8460), .Y(n8468) );
CLKMX2X2TS U4404 ( .A(n4696), .B(n9679), .S0(n2543), .Y(n1603) );
NAND2X1TS U4405 ( .A(n6526), .B(n8433), .Y(n9862) );
NAND2X1TS U4406 ( .A(n6531), .B(n8539), .Y(n9913) );
NOR3X1TS U4407 ( .A(n6756), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .C(n6755),
.Y(n6757) );
NAND2X1TS U4408 ( .A(n6526), .B(n8419), .Y(n9874) );
NAND2X1TS U4409 ( .A(n9942), .B(n8334), .Y(n3696) );
OAI21X2TS U4410 ( .A0(n7407), .A1(n7429), .B0(n7406), .Y(n7431) );
AOI22X1TS U4411 ( .A0(n8038), .A1(FPADDSUB_Data_array_SWR[11]), .B0(
FPADDSUB_Data_array_SWR[15]), .B1(n3693), .Y(n3697) );
NAND2X1TS U4412 ( .A(n8038), .B(FPADDSUB_Data_array_SWR[22]), .Y(n7781) );
NAND2X1TS U4413 ( .A(n8038), .B(FPADDSUB_Data_array_SWR[18]), .Y(n7764) );
NAND2X1TS U4414 ( .A(n8039), .B(FPADDSUB_Data_array_SWR[19]), .Y(n7771) );
INVX1TS U4415 ( .A(n8553), .Y(n6571) );
NAND2X1TS U4416 ( .A(n8048), .B(FPADDSUB_Data_array_SWR[23]), .Y(n7769) );
OR2X2TS U4417 ( .A(n7457), .B(n7401), .Y(n3628) );
NAND2X1TS U4418 ( .A(n8047), .B(FPADDSUB_Data_array_SWR[25]), .Y(n7941) );
INVX6TS U4419 ( .A(n2687), .Y(n8342) );
ADDHX2TS U4420 ( .A(n9087), .B(n4693), .CO(n6018), .S(n4694) );
NAND2X4TS U4421 ( .A(n3719), .B(n3718), .Y(n8756) );
BUFX16TS U4422 ( .A(n8447), .Y(n6283) );
NAND2X1TS U4423 ( .A(n7955), .B(n9249), .Y(n7934) );
AOI22X1TS U4424 ( .A0(n8038), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n3693),
.B1(FPADDSUB_Data_array_SWR[17]), .Y(n7904) );
NAND2X1TS U4425 ( .A(n8048), .B(FPADDSUB_Data_array_SWR[19]), .Y(n7776) );
NAND2X1TS U4426 ( .A(n8039), .B(FPADDSUB_Data_array_SWR[7]), .Y(n3694) );
CLKBUFX3TS U4427 ( .A(n9786), .Y(n6420) );
AND2X2TS U4428 ( .A(n5031), .B(n5030), .Y(n3680) );
NAND2X2TS U4429 ( .A(n5023), .B(n3757), .Y(n4969) );
NAND3X2TS U4430 ( .A(n6567), .B(n6566), .C(n9587), .Y(n8381) );
NAND3X2TS U4431 ( .A(n6533), .B(n6532), .C(n9588), .Y(n6596) );
NAND2X4TS U4432 ( .A(n7166), .B(n9571), .Y(n7198) );
MXI2X1TS U4433 ( .A(n8462), .B(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.S0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR2X4TS U4434 ( .A(n1541), .B(n1540), .Y(n8385) );
INVX4TS U4435 ( .A(n7049), .Y(n7204) );
NAND2X1TS U4436 ( .A(n8302), .B(n9202), .Y(n6204) );
NAND2X1TS U4437 ( .A(n6860), .B(n6865), .Y(n6868) );
NAND2X2TS U4438 ( .A(n6962), .B(n6901), .Y(n7029) );
NOR2X2TS U4439 ( .A(n3758), .B(n2433), .Y(n4997) );
ADDFHX2TS U4440 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
DP_OP_26J248_126_1325_n28), .CI(n7718), .CO(n7719), .S(n8552) );
INVX4TS U4441 ( .A(n7049), .Y(n7191) );
AOI21X2TS U4442 ( .A0(n6798), .A1(n6797), .B0(n6796), .Y(n6869) );
INVX8TS U4443 ( .A(n3521), .Y(n2591) );
NAND2X4TS U4444 ( .A(n8691), .B(n6180), .Y(n9972) );
NOR3X2TS U4445 ( .A(n3723), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]),
.C(n9265), .Y(n3724) );
CLKMX2X2TS U4446 ( .A(n6162), .B(n9677), .S0(n2543), .Y(n1604) );
NOR2X6TS U4447 ( .A(n3726), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.Y(n3719) );
BUFX8TS U4448 ( .A(n7238), .Y(n8762) );
NAND3X6TS U4449 ( .A(n3184), .B(n5429), .C(n9035), .Y(n2707) );
BUFX8TS U4450 ( .A(n7238), .Y(n7275) );
INVX4TS U4451 ( .A(n7768), .Y(n8048) );
NAND2X4TS U4452 ( .A(n3698), .B(FPADDSUB_bit_shift_SHT2), .Y(n7955) );
NAND2X1TS U4453 ( .A(n7439), .B(n7442), .Y(n7445) );
OAI21X1TS U4454 ( .A0(n4812), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n9235),
.Y(n4817) );
BUFX20TS U4455 ( .A(n7212), .Y(n8774) );
AND2X8TS U4456 ( .A(n8775), .B(FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n3702) );
INVX4TS U4457 ( .A(n7768), .Y(n8038) );
INVX4TS U4458 ( .A(n4683), .Y(n4357) );
NAND2X6TS U4459 ( .A(n5429), .B(n3184), .Y(n3468) );
NAND2X4TS U4460 ( .A(n4857), .B(n4856), .Y(n4862) );
NAND4BX1TS U4461 ( .AN(operation_reg_0_), .B(n8626), .C(n8625), .D(n8624),
.Y(n8627) );
NAND2X2TS U4462 ( .A(n7439), .B(n7355), .Y(n7457) );
BUFX8TS U4463 ( .A(n7238), .Y(n7272) );
INVX8TS U4464 ( .A(n5503), .Y(n2338) );
BUFX6TS U4465 ( .A(n8291), .Y(n8274) );
MX2X2TS U4466 ( .A(n6590), .B(n9647), .S0(n9646), .Y(n1540) );
NAND2X1TS U4467 ( .A(n6580), .B(n2465), .Y(n6583) );
NAND2X2TS U4468 ( .A(n6755), .B(n9228), .Y(n4790) );
AOI21X1TS U4469 ( .A0(n4819), .A1(n9231), .B0(FPADDSUB_Raw_mant_NRM_SWR[24]),
.Y(n4820) );
NAND2X4TS U4470 ( .A(n3711), .B(n3710), .Y(n3726) );
NOR2X1TS U4471 ( .A(n8316), .B(FPSENCOS_cont_iter_out[3]), .Y(n8239) );
CLKMX2X3TS U4472 ( .A(n6091), .B(n9638), .S0(n2543), .Y(n1605) );
OAI21X1TS U4473 ( .A0(n7120), .A1(n7119), .B0(n7118), .Y(n7121) );
BUFX8TS U4474 ( .A(n8734), .Y(n8753) );
INVX8TS U4475 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n2835) );
NOR2X2TS U4476 ( .A(n5024), .B(n5029), .Y(n3757) );
INVX12TS U4477 ( .A(n8454), .Y(n8456) );
OA22X2TS U4478 ( .A0(n7273), .A1(n9567), .B0(n2473), .B1(n9566), .Y(n2694)
);
NOR3X1TS U4479 ( .A(n3591), .B(n7817), .C(FPADDSUB_intDY_EWSW[28]), .Y(n7818) );
BUFX16TS U4480 ( .A(n8554), .Y(n8775) );
NOR4X1TS U4481 ( .A(dataB[24]), .B(n2896), .C(dataB[26]), .D(dataB[23]), .Y(
n8626) );
OA22X2TS U4482 ( .A0(n7273), .A1(n9565), .B0(n2473), .B1(n9564), .Y(n7274)
);
NAND2X1TS U4483 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n2691),
.Y(n2929) );
NOR2X2TS U4484 ( .A(n7905), .B(n3596), .Y(n7927) );
INVX6TS U4485 ( .A(n8454), .Y(n8455) );
NAND2X6TS U4486 ( .A(n8691), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6744) );
OAI21X2TS U4487 ( .A0(n8702), .A1(n6766), .B0(n6765), .Y(n6798) );
OAI211X2TS U4488 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n3650), .B0(n7848),
.C0(n7834), .Y(n7850) );
NOR2X2TS U4489 ( .A(n6745), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6614) );
NOR2X1TS U4490 ( .A(n7857), .B(FPADDSUB_intDY_EWSW[16]), .Y(n7858) );
OAI211X2TS U4491 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n3654), .B0(n7868),
.C0(n7853), .Y(n7862) );
INVX3TS U4492 ( .A(n3710), .Y(n3706) );
OAI21X1TS U4493 ( .A0(n6954), .A1(n6953), .B0(n6952), .Y(n6955) );
NOR2X1TS U4494 ( .A(n7871), .B(FPADDSUB_intDY_EWSW[24]), .Y(n7812) );
INVX2TS U4495 ( .A(n8349), .Y(n8583) );
INVX1TS U4496 ( .A(n8757), .Y(n7207) );
OR2X2TS U4497 ( .A(n7961), .B(n9258), .Y(n7930) );
INVX1TS U4498 ( .A(n7896), .Y(n2387) );
OAI21X2TS U4499 ( .A0(n6978), .A1(n6983), .B0(n6979), .Y(n6966) );
NAND3X1TS U4500 ( .A(n2935), .B(dataB[28]), .C(n2895), .Y(n8620) );
INVX8TS U4501 ( .A(n8299), .Y(n8291) );
INVX6TS U4502 ( .A(n6463), .Y(n8281) );
AOI21X2TS U4503 ( .A0(n2436), .A1(n9013), .B0(n9014), .Y(n4718) );
NAND2X2TS U4504 ( .A(n2518), .B(n9054), .Y(n6707) );
INVX2TS U4505 ( .A(FPSENCOS_d_ff2_Y[17]), .Y(n8502) );
OR2X2TS U4506 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n4791) );
OR2X6TS U4507 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n3712) );
NOR2X6TS U4508 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n8691) );
BUFX16TS U4509 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n7259) );
NOR3X4TS U4510 ( .A(FPSENCOS_cont_var_out[0]), .B(n9461), .C(
FPSENCOS_cont_var_out[1]), .Y(n8734) );
NOR2X1TS U4511 ( .A(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n4803) );
INVX8TS U4512 ( .A(n9973), .Y(n8454) );
OR2X1TS U4513 ( .A(FPSENCOS_d_ff1_operation_out), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n2691) );
OR2X1TS U4514 ( .A(n9103), .B(n9387), .Y(n2649) );
NOR2X6TS U4515 ( .A(n2644), .B(n2677), .Y(n3849) );
NAND2X2TS U4516 ( .A(n2428), .B(n2429), .Y(n6021) );
NOR2X6TS U4517 ( .A(n9274), .B(n3639), .Y(n8349) );
XNOR2X1TS U4518 ( .A(FPADDSUB_intDY_EWSW[7]), .B(FPADDSUB_intDX_EWSW[7]),
.Y(n8020) );
XNOR2X1TS U4519 ( .A(FPADDSUB_intDX_EWSW[3]), .B(FPADDSUB_intDY_EWSW[3]),
.Y(n8021) );
NAND2XLTS U4520 ( .A(n2282), .B(n2434), .Y(n8356) );
NOR4X1TS U4521 ( .A(dataA[30]), .B(dataA[28]), .C(dataA[29]), .D(dataA[31]),
.Y(n8616) );
NAND2X1TS U4522 ( .A(n9476), .B(FPADDSUB_DMP_SFG[10]), .Y(n6952) );
XNOR2X1TS U4523 ( .A(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n8022) );
NAND2X2TS U4524 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n7464) );
BUFX16TS U4525 ( .A(n9825), .Y(n8431) );
NOR2X2TS U4526 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n7446) );
XNOR2X1TS U4527 ( .A(FPADDSUB_intDX_EWSW[23]), .B(FPADDSUB_intDY_EWSW[23]),
.Y(n8016) );
NAND2XLTS U4528 ( .A(n2282), .B(n2493), .Y(n8364) );
NAND2X2TS U4529 ( .A(FPADDSUB_DMP_SFG[15]), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n7132) );
NAND2XLTS U4530 ( .A(n2282), .B(n2460), .Y(n8373) );
NAND2X2TS U4531 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n7139) );
NAND2X2TS U4532 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n6813) );
XNOR2X1TS U4533 ( .A(FPADDSUB_intDY_EWSW[14]), .B(FPADDSUB_intDX_EWSW[14]),
.Y(n8014) );
NOR2X4TS U4534 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n7140) );
NAND2XLTS U4535 ( .A(n2282), .B(n2504), .Y(n8354) );
NAND2X2TS U4536 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n7025) );
MX2X1TS U4537 ( .A(FPADDSUB_OP_FLAG_SHT2), .B(FPADDSUB_OP_FLAG_SHT1), .S0(
n9973), .Y(n1355) );
AND4X1TS U4538 ( .A(n9459), .B(n9644), .C(n9747), .D(n9645), .Y(n8477) );
NAND2XLTS U4539 ( .A(n2282), .B(n2455), .Y(n8358) );
NAND2BXLTS U4540 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n7825) );
NOR2X1TS U4541 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n6692) );
MX2X1TS U4542 ( .A(FPADDSUB_SIGN_FLAG_SHT2), .B(FPADDSUB_SIGN_FLAG_SHT1),
.S0(n9973), .Y(n1362) );
NOR4X1TS U4543 ( .A(FPMULT_P_Sgf[12]), .B(FPMULT_P_Sgf[11]), .C(
FPMULT_P_Sgf[10]), .D(FPMULT_P_Sgf[9]), .Y(n6735) );
AND3X2TS U4544 ( .A(n9271), .B(n9702), .C(n9703), .Y(n8483) );
NOR2X1TS U4545 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n6753) );
AND4X2TS U4546 ( .A(n9712), .B(n9273), .C(n9713), .D(n9841), .Y(n8472) );
AND4X1TS U4547 ( .A(n9693), .B(n9454), .C(n9694), .D(n9695), .Y(n8484) );
XOR2X2TS U4548 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(n8457)
);
NAND2X4TS U4549 ( .A(n3590), .B(DP_OP_497J248_123_1725_n379), .Y(n3158) );
NOR4X1TS U4550 ( .A(FPMULT_P_Sgf[8]), .B(FPMULT_P_Sgf[7]), .C(
FPMULT_P_Sgf[0]), .D(FPMULT_P_Sgf[6]), .Y(n6739) );
BUFX3TS U4551 ( .A(FPMULT_Sgf_normalized_result[21]), .Y(n2898) );
OAI2BB1X1TS U4552 ( .A0N(n2647), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n7822) );
INVX12TS U4553 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .Y(n7811) );
NAND2XLTS U4554 ( .A(n2282), .B(n2495), .Y(n8368) );
NOR4X1TS U4555 ( .A(FPMULT_P_Sgf[4]), .B(FPMULT_P_Sgf[3]), .C(
FPMULT_P_Sgf[2]), .D(FPMULT_P_Sgf[1]), .Y(n6738) );
XNOR2X1TS U4556 ( .A(FPADDSUB_intDX_EWSW[1]), .B(FPADDSUB_intDY_EWSW[1]),
.Y(n8024) );
XNOR2X1TS U4557 ( .A(FPADDSUB_intDX_EWSW[30]), .B(FPADDSUB_intDY_EWSW[30]),
.Y(n8025) );
NAND2XLTS U4558 ( .A(n9095), .B(n9237), .Y(n6784) );
NAND2X2TS U4559 ( .A(n3666), .B(FPADDSUB_DMP_SFG[7]), .Y(n6935) );
NAND2X2TS U4560 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n6983) );
INVX6TS U4561 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n3700) );
NAND2XLTS U4562 ( .A(n2282), .B(n2432), .Y(n8362) );
NAND2X4TS U4563 ( .A(DP_OP_496J248_122_3540_n1503), .B(
DP_OP_496J248_122_3540_n1516), .Y(n5223) );
XNOR2X1TS U4564 ( .A(FPADDSUB_intDX_EWSW[18]), .B(FPADDSUB_intDY_EWSW[18]),
.Y(n7991) );
NOR2X6TS U4565 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n7963) );
XNOR2X1TS U4566 ( .A(FPADDSUB_intDX_EWSW[12]), .B(FPADDSUB_intDY_EWSW[12]),
.Y(n7992) );
NAND2X1TS U4567 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n3692) );
NAND2X2TS U4568 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n6887) );
XNOR2X1TS U4569 ( .A(FPADDSUB_intDY_EWSW[19]), .B(FPADDSUB_intDX_EWSW[19]),
.Y(n7994) );
NAND2X2TS U4570 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n7383) );
NOR2X2TS U4571 ( .A(FPADDSUB_DMP_SFG[21]), .B(FPADDSUB_DmP_mant_SFG_SWR[23]),
.Y(n7377) );
NOR2X2TS U4572 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n7361) );
MX2X1TS U4573 ( .A(FPADDSUB_DMP_SHT2_EWSW[20]), .B(
FPADDSUB_DMP_SHT1_EWSW[20]), .S0(n9973), .Y(n1229) );
NAND2BX1TS U4574 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n7814) );
NAND2X4TS U4575 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n7905) );
NAND2X2TS U4576 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n6888) );
NAND2BX2TS U4577 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n7813) );
MX2X1TS U4578 ( .A(FPADDSUB_DMP_SHT2_EWSW[19]), .B(
FPADDSUB_DMP_SHT1_EWSW[19]), .S0(n9973), .Y(n1225) );
NAND2X4TS U4579 ( .A(DP_OP_496J248_122_3540_n1500), .B(
DP_OP_496J248_122_3540_n1513), .Y(n5430) );
NAND2XLTS U4580 ( .A(n2282), .B(n2501), .Y(n8366) );
NOR2X2TS U4581 ( .A(n3665), .B(FPADDSUB_DMP_SFG[8]), .Y(n6936) );
XNOR2X1TS U4582 ( .A(FPADDSUB_intDY_EWSW[28]), .B(FPADDSUB_intDX_EWSW[28]),
.Y(n7999) );
NAND2X2TS U4583 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n7459) );
NAND2XLTS U4584 ( .A(n2282), .B(n2488), .Y(n8360) );
BUFX6TS U4585 ( .A(n2545), .Y(n6580) );
NAND2BX2TS U4586 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n7859) );
INVX2TS U4587 ( .A(FPADDSUB_Data_array_SWR[23]), .Y(n7806) );
XNOR2X1TS U4588 ( .A(FPADDSUB_intDY_EWSW[10]), .B(FPADDSUB_intDX_EWSW[10]),
.Y(n8002) );
XNOR2X1TS U4589 ( .A(FPADDSUB_intDX_EWSW[11]), .B(FPADDSUB_intDY_EWSW[11]),
.Y(n8005) );
XNOR2X1TS U4590 ( .A(FPADDSUB_intDY_EWSW[4]), .B(FPADDSUB_intDX_EWSW[4]),
.Y(n8006) );
XNOR2X1TS U4591 ( .A(FPADDSUB_intDX_EWSW[17]), .B(FPADDSUB_intDY_EWSW[17]),
.Y(n7995) );
NAND2X2TS U4592 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n6963) );
NAND2XLTS U4593 ( .A(n2282), .B(n2502), .Y(n8370) );
CLKBUFX3TS U4594 ( .A(n2911), .Y(n6442) );
INVX2TS U4595 ( .A(Data_1[13]), .Y(n8517) );
INVX2TS U4596 ( .A(Data_1[15]), .Y(n8510) );
INVX2TS U4597 ( .A(Data_2[18]), .Y(n6266) );
INVX2TS U4598 ( .A(Data_1[16]), .Y(n8520) );
INVX2TS U4599 ( .A(Data_1[3]), .Y(n8512) );
INVX2TS U4600 ( .A(Data_1[4]), .Y(n8516) );
INVX2TS U4601 ( .A(Data_1[5]), .Y(n8511) );
INVX2TS U4602 ( .A(Data_1[6]), .Y(n8513) );
INVX2TS U4603 ( .A(Data_1[7]), .Y(n8515) );
INVX2TS U4604 ( .A(Data_1[8]), .Y(n8531) );
INVX2TS U4605 ( .A(Data_1[9]), .Y(n8518) );
INVX2TS U4606 ( .A(Data_2[21]), .Y(n6278) );
INVX2TS U4607 ( .A(Data_1[17]), .Y(n8524) );
INVX2TS U4608 ( .A(Data_1[19]), .Y(n8519) );
INVX2TS U4609 ( .A(Data_1[20]), .Y(n8523) );
NOR2X6TS U4610 ( .A(operation[2]), .B(operation[1]), .Y(n8295) );
INVX2TS U4611 ( .A(Data_1[21]), .Y(n8526) );
INVX2TS U4612 ( .A(Data_1[22]), .Y(n8577) );
INVX2TS U4613 ( .A(Data_1[0]), .Y(n8542) );
INVX2TS U4614 ( .A(Data_1[1]), .Y(n8541) );
INVX2TS U4615 ( .A(Data_1[2]), .Y(n8514) );
INVX2TS U4616 ( .A(Data_2[13]), .Y(n6281) );
INVX2TS U4617 ( .A(Data_2[8]), .Y(n6254) );
INVX2TS U4618 ( .A(Data_2[12]), .Y(n6268) );
INVX2TS U4619 ( .A(Data_2[1]), .Y(n6253) );
INVX2TS U4620 ( .A(Data_2[15]), .Y(n6273) );
INVX2TS U4621 ( .A(Data_2[14]), .Y(n6270) );
INVX2TS U4622 ( .A(Data_2[20]), .Y(n6275) );
INVX2TS U4623 ( .A(Data_2[3]), .Y(n6250) );
INVX2TS U4624 ( .A(Data_2[22]), .Y(n6271) );
OAI21X4TS U4625 ( .A0(n5059), .A1(n5061), .B0(n5060), .Y(n3061) );
CLKBUFX2TS U4626 ( .A(n4282), .Y(n2342) );
NAND2X8TS U4627 ( .A(n3274), .B(n2656), .Y(n3304) );
NAND2X8TS U4628 ( .A(n4160), .B(n3565), .Y(n3564) );
BUFX20TS U4629 ( .A(n2298), .Y(n8378) );
NOR2X2TS U4630 ( .A(n2516), .B(FPMULT_Sgf_operation_EVEN1_Q_right[22]), .Y(
n5024) );
AOI2BB2X2TS U4631 ( .B0(n8092), .B1(n1577), .A0N(n2914), .A1N(n3582), .Y(
n5035) );
NOR2X2TS U4632 ( .A(n8442), .B(n6564), .Y(n6576) );
OAI2BB1X2TS U4633 ( .A0N(n6696), .A1N(n5013), .B0(n4970), .Y(n5017) );
NAND3X2TS U4634 ( .A(n6537), .B(n6536), .C(n9604), .Y(n6561) );
BUFX6TS U4635 ( .A(DP_OP_498J248_124_1725_n638), .Y(n2343) );
NAND2X6TS U4636 ( .A(n3554), .B(n3553), .Y(n4034) );
NOR2X8TS U4637 ( .A(n8809), .B(n2324), .Y(n3951) );
NOR2X6TS U4638 ( .A(n2749), .B(n3223), .Y(n3398) );
OR2X8TS U4639 ( .A(n2631), .B(n2681), .Y(n2749) );
XNOR2X4TS U4640 ( .A(n3095), .B(n2595), .Y(n2631) );
NOR2X8TS U4641 ( .A(n3286), .B(n4241), .Y(n3223) );
XOR2X4TS U4642 ( .A(n2345), .B(n2344), .Y(n3286) );
NOR2X8TS U4643 ( .A(n3181), .B(n2754), .Y(n2344) );
XNOR2X4TS U4644 ( .A(n2355), .B(n2350), .Y(n3979) );
OAI22X4TS U4645 ( .A0(n3391), .A1(n3964), .B0(n2650), .B1(n4205), .Y(n2351)
);
XNOR2X4TS U4646 ( .A(n2957), .B(n3852), .Y(n2346) );
XOR2X4TS U4647 ( .A(n3846), .B(n3963), .Y(n2347) );
OAI2BB1X4TS U4648 ( .A0N(n4028), .A1N(n2362), .B0(n2361), .Y(n4098) );
OAI21X4TS U4649 ( .A0(n2362), .A1(n4028), .B0(n4027), .Y(n2361) );
XOR2X4TS U4650 ( .A(n3200), .B(n4053), .Y(n3199) );
NAND2X4TS U4651 ( .A(n2364), .B(n4287), .Y(n3388) );
AOI21X4TS U4652 ( .A0(n4298), .A1(n2364), .B0(n4297), .Y(n3349) );
NAND2X8TS U4653 ( .A(n3442), .B(n4261), .Y(n2364) );
AOI21X4TS U4654 ( .A0(n2365), .A1(n5915), .B0(n2404), .Y(n5939) );
NAND2X2TS U4655 ( .A(n2365), .B(n5914), .Y(n3497) );
XNOR2X4TS U4656 ( .A(n2367), .B(n5222), .Y(n2948) );
AOI21X4TS U4657 ( .A0(n2366), .A1(n5221), .B0(n2705), .Y(n2367) );
NAND3X8TS U4658 ( .A(n3394), .B(n3396), .C(n2368), .Y(n2770) );
XOR2X4TS U4659 ( .A(n2370), .B(n4244), .Y(n4232) );
XOR2X4TS U4660 ( .A(n4242), .B(n4243), .Y(n2370) );
BUFX6TS U4661 ( .A(n5192), .Y(n2371) );
OAI21X4TS U4662 ( .A0(n9041), .A1(n5192), .B0(n5191), .Y(n5428) );
NAND2X8TS U4663 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .Y(n5192) );
XNOR2X4TS U4664 ( .A(n5558), .B(n2338), .Y(n5416) );
XOR2X4TS U4665 ( .A(n2704), .B(n3251), .Y(n2374) );
NOR2X8TS U4666 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .Y(n2412) );
OAI21X4TS U4667 ( .A0(n2375), .A1(n2412), .B0(n3184), .Y(n2378) );
NAND2X8TS U4668 ( .A(n2657), .B(n3490), .Y(n3184) );
INVX3TS U4669 ( .A(n5192), .Y(n2375) );
NAND2X8TS U4670 ( .A(n2378), .B(n2377), .Y(n5374) );
NAND3X8TS U4671 ( .A(n2376), .B(n2371), .C(n2340), .Y(n2377) );
OR2X8TS U4672 ( .A(n5374), .B(FPMULT_Op_MX[11]), .Y(n5447) );
XNOR2X4TS U4673 ( .A(n5732), .B(n5568), .Y(n5476) );
XOR2X4TS U4674 ( .A(n2381), .B(n5200), .Y(n2379) );
OAI21X4TS U4675 ( .A0(n2718), .A1(n5198), .B0(n5207), .Y(n2381) );
XNOR2X4TS U4676 ( .A(n2383), .B(n2382), .Y(n2380) );
XOR2X4TS U4677 ( .A(n3488), .B(n5728), .Y(n2382) );
OAI2BB1X4TS U4678 ( .A0N(n2387), .A1N(n2386), .B0(n7895), .Y(n2385) );
XOR2X4TS U4679 ( .A(n7895), .B(n2388), .Y(n8037) );
NOR2X8TS U4680 ( .A(n2324), .B(DP_OP_498J248_124_1725_n635), .Y(n4053) );
XOR2X4TS U4681 ( .A(n5374), .B(n2337), .Y(n4897) );
XOR2X4TS U4682 ( .A(n2390), .B(n5596), .Y(n5456) );
NAND2X4TS U4683 ( .A(n5232), .B(n5231), .Y(n5299) );
NOR2X8TS U4684 ( .A(n5232), .B(n5231), .Y(n5301) );
NOR2X8TS U4685 ( .A(n5397), .B(n5399), .Y(n5459) );
XNOR2X4TS U4686 ( .A(n5462), .B(n5463), .Y(n3500) );
OA22X4TS U4687 ( .A0(n5461), .A1(n2393), .B0(n5460), .B1(n5407), .Y(n2391)
);
NAND2X8TS U4688 ( .A(n2319), .B(n3249), .Y(n2392) );
INVX12TS U4689 ( .A(n2394), .Y(n5590) );
XOR2X4TS U4690 ( .A(n2394), .B(n5450), .Y(n5455) );
NAND3X8TS U4691 ( .A(n2397), .B(n2395), .C(n2396), .Y(n2394) );
NAND2BX4TS U4692 ( .AN(n3468), .B(n2398), .Y(n2395) );
NAND2BX4TS U4693 ( .AN(n3469), .B(n2398), .Y(n2397) );
INVX12TS U4694 ( .A(n5073), .Y(n5091) );
NAND2X8TS U4695 ( .A(n2399), .B(n4547), .Y(n5073) );
NOR2X8TS U4696 ( .A(n3420), .B(n2400), .Y(n3519) );
OR2X8TS U4697 ( .A(n3518), .B(n3419), .Y(n2400) );
XNOR2X4TS U4698 ( .A(n2402), .B(n4888), .Y(n2990) );
OAI2BB1X4TS U4699 ( .A0N(n4889), .A1N(n2402), .B0(n2401), .Y(n5433) );
OAI22X4TS U4700 ( .A0(n5598), .A1(n4883), .B0(n2900), .B1(n4894), .Y(n2402)
);
NAND2X6TS U4701 ( .A(n5292), .B(n5291), .Y(n5914) );
OAI21X4TS U4702 ( .A0(n5935), .A1(n5939), .B0(n5936), .Y(n6054) );
OAI21X4TS U4703 ( .A0(n5900), .A1(n5897), .B0(n5898), .Y(n5915) );
NAND2X4TS U4704 ( .A(n5171), .B(n5170), .Y(n2407) );
NAND2BX4TS U4705 ( .AN(n5171), .B(n2408), .Y(n2405) );
XNOR2X4TS U4706 ( .A(n2409), .B(n5058), .Y(n5043) );
XNOR2X4TS U4707 ( .A(n5171), .B(n5170), .Y(n2409) );
NOR2X8TS U4708 ( .A(DP_OP_497J248_123_1725_n718), .B(
DP_OP_497J248_123_1725_n713), .Y(n4659) );
INVX12TS U4709 ( .A(n3068), .Y(n5591) );
XOR2X4TS U4710 ( .A(n3125), .B(n9645), .Y(n5305) );
NOR2X8TS U4711 ( .A(n2604), .B(DP_OP_497J248_123_1725_n631), .Y(n4343) );
OAI2BB1X4TS U4712 ( .A0N(n2416), .A1N(n2414), .B0(n2413), .Y(n4349) );
XNOR2X4TS U4713 ( .A(n2680), .B(n2415), .Y(n4371) );
XOR2X4TS U4714 ( .A(n4401), .B(n2416), .Y(n2415) );
XOR2X4TS U4715 ( .A(n4344), .B(DP_OP_497J248_123_1725_n704), .Y(n4643) );
XNOR2X4TS U4716 ( .A(n2419), .B(n2418), .Y(n4646) );
NOR2X8TS U4717 ( .A(n4641), .B(n4640), .Y(n3509) );
NAND2X8TS U4718 ( .A(n3242), .B(n4605), .Y(n2740) );
AND2X4TS U4719 ( .A(n3516), .B(n3515), .Y(n3871) );
NAND2X8TS U4720 ( .A(n3156), .B(n3155), .Y(n2421) );
CLKINVX6TS U4721 ( .A(n3258), .Y(n3257) );
OR2X8TS U4722 ( .A(n3043), .B(n3935), .Y(n2982) );
AND2X8TS U4723 ( .A(n8847), .B(n8849), .Y(n3280) );
AND2X8TS U4724 ( .A(n2827), .B(n2823), .Y(n4007) );
AND2X8TS U4725 ( .A(n2823), .B(n2814), .Y(n3046) );
INVX4TS U4726 ( .A(n4074), .Y(n2700) );
NOR2X8TS U4727 ( .A(DP_OP_498J248_124_1725_n639), .B(n2324), .Y(n3855) );
NAND2X8TS U4728 ( .A(n3177), .B(n2740), .Y(n3156) );
OAI22X4TS U4729 ( .A0(n2795), .A1(n4619), .B0(n2962), .B1(n4671), .Y(n4486)
);
ADDFHX4TS U4730 ( .A(n4615), .B(n4614), .CI(n4613), .CO(n4678), .S(n4612) );
INVX4TS U4731 ( .A(n2616), .Y(n4614) );
ADDFHX4TS U4732 ( .A(n3979), .B(n3978), .CI(n3977), .CO(n3980), .S(n3937) );
NAND2X4TS U4733 ( .A(n4231), .B(n4232), .Y(n4261) );
ADDFHX4TS U4734 ( .A(n5726), .B(n5725), .CI(n5724), .CO(n5727), .S(n6070) );
CLKINVX12TS U4735 ( .A(DP_OP_498J248_124_1725_n722), .Y(n2424) );
INVX16TS U4736 ( .A(n2424), .Y(n2425) );
NAND2X4TS U4737 ( .A(n3140), .B(n3152), .Y(n2426) );
INVX12TS U4738 ( .A(n3076), .Y(n3140) );
INVX8TS U4739 ( .A(n4633), .Y(n4657) );
ADDFHX4TS U4740 ( .A(DP_OP_497J248_123_1725_n613), .B(n4418), .CI(n4417),
.CO(n4424), .S(n4415) );
NOR2X8TS U4741 ( .A(n5703), .B(n3332), .Y(n4888) );
NOR2X8TS U4742 ( .A(n4402), .B(n4642), .Y(n4491) );
ADDHX4TS U4743 ( .A(DP_OP_497J248_123_1725_n617), .B(
DP_OP_497J248_123_1725_n612), .CO(n4394), .S(n4402) );
ADDFHX4TS U4744 ( .A(n5487), .B(n5486), .CI(n5485), .CO(n6328), .S(n6325) );
BUFX6TS U4745 ( .A(n4002), .Y(n3289) );
OAI22X4TS U4746 ( .A0(n4597), .A1(DP_OP_497J248_123_1725_n312), .B0(n3458),
.B1(n4489), .Y(n4578) );
ADDFHX4TS U4747 ( .A(n5557), .B(n5556), .CI(n5555), .CO(n5579), .S(n5551) );
OAI22X2TS U4748 ( .A0(n2216), .A1(n2636), .B0(n2795), .B1(n2638), .Y(n4506)
);
NOR2X8TS U4749 ( .A(DP_OP_498J248_124_1725_n636), .B(
DP_OP_498J248_124_1725_n645), .Y(n3873) );
BUFX8TS U4750 ( .A(DP_OP_498J248_124_1725_n645), .Y(n2971) );
INVX8TS U4751 ( .A(n4311), .Y(n4046) );
NAND2X4TS U4752 ( .A(n8877), .B(n2661), .Y(n4399) );
NAND3X4TS U4753 ( .A(n5011), .B(n5010), .C(n5009), .Y(n1519) );
NAND2X4TS U4754 ( .A(n8071), .B(n8245), .Y(n4785) );
NOR2X2TS U4755 ( .A(n2425), .B(DP_OP_498J248_124_1725_n727), .Y(n4211) );
ADDHX4TS U4756 ( .A(n4886), .B(n4885), .CO(n5326), .S(n5270) );
NOR2X8TS U4757 ( .A(DP_OP_498J248_124_1725_n635), .B(n3947), .Y(n3949) );
NOR2X4TS U4758 ( .A(n2215), .B(n2214), .Y(n4130) );
NOR2X4TS U4759 ( .A(DP_OP_498J248_124_1725_n635), .B(
DP_OP_498J248_124_1725_n641), .Y(n4105) );
NOR2X2TS U4760 ( .A(n2485), .B(n2430), .Y(n5029) );
NAND2X1TS U4761 ( .A(n6557), .B(n2431), .Y(n6544) );
NAND2X2TS U4762 ( .A(n3816), .B(n2437), .Y(n5982) );
NAND2X1TS U4763 ( .A(n8377), .B(n2440), .Y(n6598) );
NAND2X1TS U4764 ( .A(n6581), .B(n2443), .Y(n6582) );
NAND2X1TS U4765 ( .A(n6557), .B(n2446), .Y(n6554) );
NAND2X1TS U4766 ( .A(n8377), .B(n2448), .Y(n6535) );
NAND2X1TS U4767 ( .A(n8377), .B(n2449), .Y(n6537) );
NAND2X1TS U4768 ( .A(n6557), .B(n2453), .Y(n6550) );
NAND2X1TS U4769 ( .A(n8377), .B(n2454), .Y(n6542) );
NAND2X1TS U4770 ( .A(n6557), .B(n2456), .Y(n6556) );
NAND2X1TS U4771 ( .A(n8377), .B(n2461), .Y(n6609) );
NAND2X1TS U4772 ( .A(n8377), .B(n2463), .Y(n6563) );
NAND2X1TS U4773 ( .A(n8378), .B(n2463), .Y(n6536) );
NAND2X1TS U4774 ( .A(n8377), .B(n2464), .Y(n6533) );
NAND2X1TS U4775 ( .A(n6557), .B(n2471), .Y(n6552) );
NAND2X1TS U4776 ( .A(n6558), .B(n2474), .Y(n6553) );
NAND2X2TS U4777 ( .A(n3824), .B(n2481), .Y(n7489) );
ADDFHX2TS U4778 ( .A(n8963), .B(n2483), .CI(n8964), .CO(n3833), .S(n3810) );
NAND2X1TS U4779 ( .A(n6557), .B(n2489), .Y(n6560) );
NAND2X1TS U4780 ( .A(n8377), .B(n2496), .Y(n6567) );
NAND2BX1TS U4781 ( .AN(n2499), .B(n9562), .Y(n6457) );
NAND2X4TS U4782 ( .A(n3761), .B(n2507), .Y(n4977) );
NAND2X1TS U4783 ( .A(n6459), .B(n2510), .Y(n7183) );
NAND2X1TS U4784 ( .A(n7191), .B(n2511), .Y(n6466) );
NAND2X1TS U4785 ( .A(n6459), .B(n2512), .Y(n6465) );
NAND2X4TS U4786 ( .A(n2540), .B(n2515), .Y(n3778) );
NOR2X2TS U4787 ( .A(n2518), .B(n9060), .Y(n6708) );
NOR2X2TS U4788 ( .A(n2519), .B(n9048), .Y(n6726) );
NAND2X1TS U4789 ( .A(n7191), .B(n2522), .Y(n7196) );
NAND2X1TS U4790 ( .A(n7191), .B(n2523), .Y(n7193) );
NAND2X1TS U4791 ( .A(n7204), .B(n2524), .Y(n7203) );
NAND2X1TS U4792 ( .A(n7191), .B(n2525), .Y(n7053) );
NAND2X1TS U4793 ( .A(n6459), .B(n2526), .Y(n7187) );
NAND2X1TS U4794 ( .A(n7204), .B(n2527), .Y(n6462) );
NAND2X1TS U4795 ( .A(n6459), .B(n2528), .Y(n6461) );
NAND2X1TS U4796 ( .A(n6459), .B(n2529), .Y(n7177) );
NAND2X1TS U4797 ( .A(n7204), .B(n2530), .Y(n7172) );
NAND2X1TS U4798 ( .A(n6459), .B(n2531), .Y(n7171) );
NAND2X1TS U4799 ( .A(n7204), .B(n2532), .Y(n7178) );
NAND2X1TS U4800 ( .A(n6459), .B(n2533), .Y(n7205) );
NAND2X1TS U4801 ( .A(n7191), .B(n2534), .Y(n7180) );
NAND2X1TS U4802 ( .A(n6459), .B(n2535), .Y(n7179) );
NAND2X1TS U4803 ( .A(n7204), .B(n2536), .Y(n7206) );
NAND2X1TS U4804 ( .A(n7191), .B(n2537), .Y(n7188) );
NAND2X1TS U4805 ( .A(n7204), .B(n2538), .Y(n7184) );
NAND2X1TS U4806 ( .A(n7194), .B(n2538), .Y(n7189) );
NAND2X1TS U4807 ( .A(n2539), .B(n9064), .Y(n6020) );
CLKMX2X2TS U4808 ( .A(n6720), .B(n9573), .S0(n2541), .Y(n1568) );
CLKMX2X2TS U4809 ( .A(n6717), .B(n9678), .S0(n2541), .Y(n1570) );
CLKMX2X2TS U4810 ( .A(n6719), .B(n9676), .S0(n2541), .Y(n1569) );
CLKMX2X2TS U4811 ( .A(n9550), .B(n9549), .S0(n2543), .Y(n1606) );
BUFX6TS U4812 ( .A(n2545), .Y(n8377) );
MX2X4TS U4813 ( .A(n4965), .B(n9734), .S0(n2287), .Y(n1581) );
MX2X4TS U4814 ( .A(n5989), .B(n9733), .S0(n2287), .Y(n1582) );
MX2X4TS U4815 ( .A(n4981), .B(n9724), .S0(n2287), .Y(n1580) );
MX2X4TS U4816 ( .A(n5006), .B(n9723), .S0(n2287), .Y(n1578) );
CLKMX2X4TS U4817 ( .A(n5018), .B(n9721), .S0(n2287), .Y(n1577) );
CLKMX2X2TS U4818 ( .A(n5033), .B(n9719), .S0(n2287), .Y(n1576) );
CLKMX2X4TS U4819 ( .A(n6010), .B(n9745), .S0(n2296), .Y(n1589) );
CLKMX2X4TS U4820 ( .A(n7285), .B(n9732), .S0(n2296), .Y(n1584) );
CLKMX2X4TS U4821 ( .A(n3844), .B(n9731), .S0(n2296), .Y(n1586) );
CLKMX2X4TS U4822 ( .A(n7757), .B(n9729), .S0(n2296), .Y(n1588) );
CLKMX2X2TS U4823 ( .A(n6724), .B(n9726), .S0(n2296), .Y(n1573) );
CLKMX2X2TS U4824 ( .A(n6706), .B(n9681), .S0(n2296), .Y(n1571) );
CLKMX2X2TS U4825 ( .A(n6715), .B(n9680), .S0(n2296), .Y(n1572) );
NOR2X8TS U4826 ( .A(n4503), .B(DP_OP_497J248_123_1725_n718), .Y(n4536) );
NOR2X6TS U4827 ( .A(n4503), .B(DP_OP_497J248_123_1725_n722), .Y(n4607) );
NOR2X6TS U4828 ( .A(n4503), .B(DP_OP_497J248_123_1725_n720), .Y(n4354) );
NAND2X8TS U4829 ( .A(n2626), .B(n2625), .Y(n2624) );
NOR2X4TS U4830 ( .A(n2601), .B(DP_OP_497J248_123_1725_n635), .Y(n4421) );
AO22X1TS U4831 ( .A0(n8469), .A1(n1532), .B0(mult_result[15]), .B1(n6617),
.Y(n1500) );
CLKINVX12TS U4832 ( .A(n2582), .Y(n2583) );
AND2X4TS U4833 ( .A(n2822), .B(n2829), .Y(n4064) );
AO22X1TS U4834 ( .A0(n8469), .A1(n1533), .B0(mult_result[16]), .B1(n8468),
.Y(n1499) );
NOR2X1TS U4835 ( .A(n8989), .B(n8996), .Y(n2562) );
NOR2X4TS U4836 ( .A(n3002), .B(n2971), .Y(n8588) );
OR2X4TS U4837 ( .A(DP_OP_497J248_123_1725_n717), .B(
DP_OP_497J248_123_1725_n722), .Y(n2693) );
INVX2TS U4838 ( .A(n8998), .Y(n3618) );
AO22X1TS U4839 ( .A0(n8469), .A1(n1537), .B0(mult_result[20]), .B1(n8468),
.Y(n1495) );
NAND3X2TS U4840 ( .A(n2572), .B(n2571), .C(n2570), .Y(n1537) );
NOR2X6TS U4841 ( .A(DP_OP_498J248_124_1725_n636), .B(n3947), .Y(n3891) );
NOR2X6TS U4842 ( .A(DP_OP_498J248_124_1725_n725), .B(n3955), .Y(n4060) );
NOR2X2TS U4843 ( .A(DP_OP_498J248_124_1725_n721), .B(
DP_OP_498J248_124_1725_n727), .Y(n5970) );
INVX2TS U4844 ( .A(n8981), .Y(n2743) );
NOR2X4TS U4845 ( .A(n4602), .B(n4575), .Y(n4451) );
BUFX12TS U4846 ( .A(n5696), .Y(n2580) );
XOR2X2TS U4847 ( .A(n5461), .B(n5307), .Y(n5696) );
INVX8TS U4848 ( .A(n4197), .Y(n3343) );
OR2X8TS U4849 ( .A(n4319), .B(n4318), .Y(n3390) );
AND2X8TS U4850 ( .A(n5390), .B(n5389), .Y(n2584) );
ADDFHX4TS U4851 ( .A(n3914), .B(n3913), .CI(n3912), .CO(n3905), .S(n3932) );
NOR2X4TS U4852 ( .A(n6224), .B(n6223), .Y(n5963) );
NOR2X6TS U4853 ( .A(n3679), .B(n6224), .Y(n3206) );
NAND2X6TS U4854 ( .A(n4641), .B(n4640), .Y(n4681) );
XOR2X2TS U4855 ( .A(n5332), .B(n5244), .Y(n5245) );
XNOR2X2TS U4856 ( .A(n5588), .B(n3119), .Y(n5467) );
INVX16TS U4857 ( .A(n2639), .Y(n4489) );
AND2X8TS U4858 ( .A(n8866), .B(n3037), .Y(n2639) );
INVX4TS U4859 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .Y(n5927) );
XOR2X4TS U4860 ( .A(n3474), .B(n3477), .Y(n2587) );
XOR2X4TS U4861 ( .A(n4622), .B(n2587), .Y(n3260) );
ADDFHX4TS U4862 ( .A(n5297), .B(n5296), .CI(n5295), .CO(n5369), .S(n5309) );
ADDFHX2TS U4863 ( .A(n3979), .B(n3978), .CI(n3977), .S(n2588) );
OAI2BB1X2TS U4864 ( .A0N(n8858), .A1N(DP_OP_498J248_124_1725_n616), .B0(
n3355), .Y(n4052) );
INVX4TS U4865 ( .A(n1668), .Y(n8839) );
NAND2X4TS U4866 ( .A(n4405), .B(n5107), .Y(n3022) );
NOR2X4TS U4867 ( .A(n2971), .B(n2343), .Y(n4909) );
CLKINVX12TS U4868 ( .A(DP_OP_497J248_123_1725_n389), .Y(n2590) );
NAND2X4TS U4869 ( .A(n3521), .B(n2600), .Y(n2593) );
NAND2X8TS U4870 ( .A(n2591), .B(n2592), .Y(n2594) );
NAND2X8TS U4871 ( .A(n2593), .B(n2594), .Y(n3077) );
NAND2X8TS U4872 ( .A(n2590), .B(DP_OP_497J248_123_1725_n390), .Y(n3521) );
INVX16TS U4873 ( .A(n3077), .Y(n4597) );
NAND2X4TS U4874 ( .A(n2583), .B(DP_OP_498J248_124_1725_n645), .Y(n3346) );
NOR2X4TS U4875 ( .A(DP_OP_498J248_124_1725_n724), .B(n2583), .Y(n3879) );
NOR2X8TS U4876 ( .A(n2583), .B(DP_OP_498J248_124_1725_n726), .Y(n4157) );
XOR2X4TS U4877 ( .A(n3454), .B(n6076), .Y(n3384) );
NOR2X4TS U4878 ( .A(n5591), .B(n2260), .Y(n3283) );
NAND2X6TS U4879 ( .A(n5793), .B(n5796), .Y(n3132) );
ADDFHX4TS U4880 ( .A(n5536), .B(n5535), .CI(n5534), .S(n2596) );
INVX4TS U4881 ( .A(n5907), .Y(n5609) );
XOR2X4TS U4882 ( .A(n2950), .B(n3424), .Y(n2599) );
NAND2X4TS U4883 ( .A(n4463), .B(n4462), .Y(n4464) );
INVX8TS U4884 ( .A(n5185), .Y(n3543) );
NOR2X8TS U4885 ( .A(n5450), .B(DP_OP_496J248_122_3540_n827), .Y(n5185) );
OAI22X4TS U4886 ( .A0(n5408), .A1(n5473), .B0(n5351), .B1(n5211), .Y(n5421)
);
INVX6TS U4887 ( .A(n4625), .Y(n4667) );
NAND2X2TS U4888 ( .A(n4575), .B(n4602), .Y(n4452) );
NOR2X8TS U4889 ( .A(n6224), .B(n6172), .Y(n3180) );
OAI2BB1X4TS U4890 ( .A0N(n4622), .A1N(n4621), .B0(n3259), .Y(n4666) );
INVX4TS U4891 ( .A(n4602), .Y(n4627) );
INVX4TS U4892 ( .A(n5952), .Y(n2952) );
NAND2X4TS U4893 ( .A(n3386), .B(n3387), .Y(n4321) );
INVX12TS U4894 ( .A(n5874), .Y(n3467) );
OR2X8TS U4895 ( .A(n4513), .B(n4514), .Y(n2810) );
CLKXOR2X4TS U4896 ( .A(DP_OP_497J248_123_1725_n792), .B(
DP_OP_497J248_123_1725_n705), .Y(n2606) );
NAND2X8TS U4897 ( .A(n2995), .B(n2994), .Y(n4546) );
ADDFHX4TS U4898 ( .A(n3890), .B(n3889), .CI(n3888), .CO(n3940), .S(n3903) );
INVX6TS U4899 ( .A(n3464), .Y(n4293) );
ADDFHX2TS U4900 ( .A(n4564), .B(n4563), .CI(n4562), .CO(n4565), .S(n4511) );
OAI22X4TS U4901 ( .A0(n5457), .A1(n2900), .B0(n2969), .B1(n5456), .Y(n5470)
);
NOR2X4TS U4902 ( .A(n5091), .B(n2638), .Y(n4669) );
INVX6TS U4903 ( .A(n5159), .Y(n4668) );
NAND2X8TS U4904 ( .A(n2770), .B(n2768), .Y(n3501) );
OAI22X4TS U4905 ( .A0(n5721), .A1(n5719), .B0(n2331), .B1(n5381), .Y(n5396)
);
AOI2BB2X4TS U4906 ( .B0(n2326), .B1(n2611), .A0N(n5056), .A1N(n2636), .Y(
n2610) );
NOR2X6TS U4907 ( .A(n4550), .B(n2820), .Y(n4461) );
NOR2X2TS U4908 ( .A(n4461), .B(n4847), .Y(n3234) );
INVX6TS U4909 ( .A(n4263), .Y(n3444) );
NAND2X4TS U4910 ( .A(n5109), .B(n4501), .Y(n3408) );
NOR2X4TS U4911 ( .A(n3464), .B(n3210), .Y(n3351) );
OAI22X4TS U4912 ( .A0(n5056), .A1(DP_OP_497J248_123_1725_n312), .B0(n3458),
.B1(n5057), .Y(n5076) );
OAI22X4TS U4913 ( .A0(n5057), .A1(n2339), .B0(n2612), .B1(n2613), .Y(n4626)
);
ADDHX4TS U4914 ( .A(DP_OP_497J248_123_1725_n610), .B(
DP_OP_497J248_123_1725_n600), .CO(n4409), .S(n4389) );
NOR2X4TS U4915 ( .A(DP_OP_497J248_123_1725_n324), .B(n8873), .Y(n4417) );
ADDFHX4TS U4916 ( .A(DP_OP_497J248_123_1725_n607), .B(
DP_OP_497J248_123_1725_n602), .CI(n4425), .CO(n4429), .S(n4423) );
NOR2X8TS U4917 ( .A(n5934), .B(n5933), .Y(n6173) );
XNOR2X2TS U4918 ( .A(n5353), .B(n5475), .Y(n5250) );
INVX6TS U4919 ( .A(n5160), .Y(n4654) );
NOR2X8TS U4920 ( .A(n7504), .B(n7752), .Y(n4764) );
AOI21X4TS U4921 ( .A0(n7499), .A1(n4764), .B0(n4763), .Y(n4765) );
ADDFHX4TS U4922 ( .A(n4714), .B(n4713), .CI(n4712), .CO(n4719), .S(n3836) );
NAND2X2TS U4923 ( .A(n3396), .B(n3394), .Y(n2634) );
NAND3X8TS U4924 ( .A(n2757), .B(n2756), .C(n2755), .Y(n4319) );
NAND2X8TS U4925 ( .A(n2632), .B(n3441), .Y(n2752) );
OAI21X4TS U4926 ( .A0(n3953), .A1(n3954), .B0(n3952), .Y(n3110) );
NAND2X6TS U4927 ( .A(n7498), .B(n4764), .Y(n4766) );
ADDFHX4TS U4928 ( .A(n5507), .B(n5506), .CI(n5505), .CO(n5543), .S(n5495) );
INVX4TS U4929 ( .A(n5860), .Y(n5506) );
OAI22X2TS U4930 ( .A0(n4205), .A1(n4035), .B0(n3507), .B1(n4184), .Y(n4011)
);
ADDFHX4TS U4931 ( .A(n4221), .B(n4220), .CI(n4219), .CO(n4245), .S(n4223) );
OAI22X2TS U4932 ( .A0(n3391), .A1(n4206), .B0(n4205), .B1(n4253), .Y(n4220)
);
INVX2TS U4933 ( .A(n4598), .Y(n3478) );
INVX4TS U4934 ( .A(n8589), .Y(n4948) );
NOR2X4TS U4935 ( .A(n3139), .B(n8817), .Y(n3050) );
INVX2TS U4936 ( .A(n3083), .Y(n3082) );
INVX8TS U4937 ( .A(n5647), .Y(n5646) );
INVX6TS U4938 ( .A(n4334), .Y(n4598) );
INVX4TS U4939 ( .A(n4124), .Y(n2981) );
INVX4TS U4940 ( .A(n4462), .Y(n3236) );
OAI22X2TS U4941 ( .A0(n5361), .A1(n5653), .B0(n5654), .B1(n5652), .Y(n5411)
);
NAND2X4TS U4942 ( .A(n5872), .B(n3336), .Y(n3335) );
NOR2X4TS U4943 ( .A(n5868), .B(n5871), .Y(n3336) );
NAND2X4TS U4944 ( .A(n3866), .B(n3867), .Y(n3430) );
INVX2TS U4945 ( .A(n3345), .Y(n3342) );
INVX2TS U4946 ( .A(n3561), .Y(n3556) );
ADDFHX2TS U4947 ( .A(n3902), .B(n3901), .CI(n3900), .CO(n3946), .S(n3906) );
INVX6TS U4948 ( .A(n4073), .Y(n3902) );
INVX4TS U4949 ( .A(n2337), .Y(n5594) );
NAND2X4TS U4950 ( .A(n3197), .B(n3195), .Y(n4101) );
NAND2X2TS U4951 ( .A(n4053), .B(n3196), .Y(n3195) );
OAI22X2TS U4952 ( .A0(n4030), .A1(n2650), .B0(n3361), .B1(n3964), .Y(n3913)
);
OAI21X2TS U4953 ( .A0(n4656), .A1(n2739), .B0(n4655), .Y(n2737) );
NAND2X4TS U4954 ( .A(n2711), .B(n5251), .Y(n2710) );
INVX4TS U4955 ( .A(n5664), .Y(n2967) );
OAI21X2TS U4956 ( .A0(n5582), .A1(n6332), .B0(n5581), .Y(n3486) );
INVX2TS U4957 ( .A(n6333), .Y(n5581) );
BUFX12TS U4958 ( .A(n5502), .Y(n2960) );
ADDFHX2TS U4959 ( .A(n5689), .B(n5688), .CI(n5687), .CO(n5739), .S(n5682) );
CLKINVX6TS U4960 ( .A(n8904), .Y(n3037) );
OAI22X2TS U4961 ( .A0(n5261), .A1(n5473), .B0(n2907), .B1(n5211), .Y(n5279)
);
INVX2TS U4962 ( .A(n5414), .Y(n2724) );
CLKINVX6TS U4963 ( .A(n8875), .Y(n3265) );
INVX4TS U4964 ( .A(n4083), .Y(n4903) );
INVX2TS U4965 ( .A(n5310), .Y(n3323) );
INVX2TS U4966 ( .A(n6063), .Y(n2991) );
AND2X2TS U4967 ( .A(n5362), .B(n9643), .Y(n5363) );
OR2X4TS U4968 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .B(n8711), .Y(
n3006) );
INVX4TS U4969 ( .A(n6002), .Y(n3397) );
NAND2X2TS U4970 ( .A(n6024), .B(n6185), .Y(n6026) );
NOR2X2TS U4971 ( .A(n9204), .B(n8690), .Y(n6574) );
NOR2X2TS U4972 ( .A(n7749), .B(n2732), .Y(n2731) );
INVX8TS U4973 ( .A(n3327), .Y(FPMULT_Sgf_operation_EVEN1_Q_left[17]) );
CLKINVX6TS U4974 ( .A(n2765), .Y(n2760) );
NOR2X4TS U4975 ( .A(n8859), .B(n8817), .Y(n2764) );
INVX6TS U4976 ( .A(n3272), .Y(n3270) );
INVX4TS U4977 ( .A(n3289), .Y(n3293) );
ADDFHX2TS U4978 ( .A(n3882), .B(n3883), .CI(n4064), .CO(n3920), .S(n3921) );
INVX2TS U4979 ( .A(n2618), .Y(n5048) );
INVX2TS U4980 ( .A(n5107), .Y(n4497) );
INVX4TS U4981 ( .A(n2718), .Y(n2719) );
NAND2X2TS U4982 ( .A(n3332), .B(n3331), .Y(n4878) );
INVX2TS U4983 ( .A(n4095), .Y(n3934) );
AOI21X1TS U4984 ( .A0(n4148), .A1(n4126), .B0(n4125), .Y(n4127) );
OAI21X2TS U4985 ( .A0(n5251), .A1(n9039), .B0(n3616), .Y(n2705) );
INVX4TS U4986 ( .A(n3514), .Y(n3231) );
NOR2X6TS U4987 ( .A(n9041), .B(n2412), .Y(n5429) );
NOR2X4TS U4988 ( .A(n5640), .B(n5447), .Y(n3488) );
INVX6TS U4989 ( .A(n5923), .Y(n5665) );
INVX2TS U4990 ( .A(n2615), .Y(n4509) );
NOR2X4TS U4991 ( .A(n4461), .B(n4848), .Y(n3237) );
CLKINVX6TS U4992 ( .A(n8876), .Y(n3264) );
ADDFHX2TS U4993 ( .A(n4574), .B(n4573), .CI(DP_OP_497J248_123_1725_n667),
.CO(n4630), .S(n4599) );
INVX4TS U4994 ( .A(n4287), .Y(n4292) );
NOR2X4TS U4995 ( .A(n5352), .B(n5355), .Y(n5845) );
INVX4TS U4996 ( .A(n4108), .Y(n3405) );
INVX2TS U4997 ( .A(n6322), .Y(n5393) );
INVX2TS U4998 ( .A(n2715), .Y(n2706) );
NAND2X4TS U4999 ( .A(n3612), .B(n5265), .Y(n5313) );
INVX12TS U5000 ( .A(n2712), .Y(n5553) );
INVX4TS U5001 ( .A(n5908), .Y(n5610) );
INVX8TS U5002 ( .A(n3248), .Y(n5750) );
NAND2X2TS U5003 ( .A(n5701), .B(n5700), .Y(n3544) );
INVX2TS U5004 ( .A(n4470), .Y(n4377) );
INVX4TS U5005 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(n4927) );
OAI21X2TS U5006 ( .A0(n2517), .A1(n8950), .B0(n8951), .Y(n3748) );
NOR2X4TS U5007 ( .A(n3773), .B(n3774), .Y(n3785) );
NOR2X4TS U5008 ( .A(n4745), .B(n4721), .Y(n4730) );
OAI21X2TS U5009 ( .A0(n7336), .A1(n7335), .B0(n7334), .Y(n7443) );
NAND2X2TS U5010 ( .A(n5135), .B(n5134), .Y(n2734) );
NAND2X4TS U5011 ( .A(n3241), .B(n4682), .Y(n3319) );
AOI221X1TS U5012 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n3646), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n3648), .C0(n7818), .Y(n7820) );
NOR2X2TS U5013 ( .A(n4985), .B(n4968), .Y(n4973) );
NOR2X2TS U5014 ( .A(n6848), .B(n6851), .Y(n6886) );
INVX4TS U5015 ( .A(n6301), .Y(n8097) );
OAI21X1TS U5016 ( .A0(n7130), .A1(n7457), .B0(n7456), .Y(n7462) );
INVX2TS U5017 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .Y(n6056) );
CLKINVX6TS U5018 ( .A(n5798), .Y(n5175) );
INVX4TS U5019 ( .A(n5827), .Y(n5830) );
INVX6TS U5020 ( .A(n2634), .Y(n8104) );
INVX2TS U5021 ( .A(n2669), .Y(n3409) );
OR2X6TS U5022 ( .A(DP_OP_499J248_125_1651_n273), .B(n3382), .Y(n6416) );
NAND2X4TS U5023 ( .A(n8103), .B(n3206), .Y(n3202) );
MXI2X4TS U5024 ( .A(n6692), .B(n6691), .S0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n8779) );
NOR4X1TS U5025 ( .A(dataA[26]), .B(dataA[27]), .C(dataA[23]), .D(dataA[24]),
.Y(n8618) );
CLKAND2X2TS U5026 ( .A(n5023), .B(n6698), .Y(n5028) );
AOI21X2TS U5027 ( .A0(n7749), .A1(n7501), .B0(n7500), .Y(n7502) );
INVX2TS U5028 ( .A(n6860), .Y(n6840) );
INVX8TS U5029 ( .A(n8431), .Y(n8402) );
NAND2X4TS U5030 ( .A(n4913), .B(n3015), .Y(n3014) );
INVX2TS U5031 ( .A(n4912), .Y(n3015) );
CLKBUFX3TS U5032 ( .A(n2889), .Y(n8251) );
CLKINVX6TS U5033 ( .A(n2651), .Y(n7315) );
NAND2X1TS U5034 ( .A(n9513), .B(n8404), .Y(n9921) );
NAND2X1TS U5035 ( .A(n9513), .B(n8405), .Y(n9920) );
NAND2X1TS U5036 ( .A(n8653), .B(cordic_result[0]), .Y(n6657) );
AOI22X1TS U5037 ( .A0(n8220), .A1(Data_2[12]), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n8219), .Y(n7593) );
AOI22X1TS U5038 ( .A0(n7685), .A1(Data_1[10]), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n7684), .Y(n7662) );
NOR2X4TS U5039 ( .A(n6196), .B(n8691), .Y(n6203) );
NOR2X1TS U5040 ( .A(n6267), .B(n3627), .Y(n8897) );
NOR2X1TS U5041 ( .A(n8909), .B(n8890), .Y(n8919) );
NOR2X1TS U5042 ( .A(n8884), .B(n8894), .Y(n8905) );
INVX2TS U5043 ( .A(n1352), .Y(n9552) );
AND2X2TS U5044 ( .A(n1668), .B(n9683), .Y(n8813) );
INVX4TS U5045 ( .A(n6251), .Y(n8816) );
INVX4TS U5046 ( .A(n9696), .Y(n8884) );
INVX4TS U5047 ( .A(n6269), .Y(n8894) );
INVX4TS U5048 ( .A(n1643), .Y(n8909) );
INVX2TS U5049 ( .A(n6407), .Y(n6409) );
INVX2TS U5050 ( .A(n3517), .Y(n2963) );
CLKINVX6TS U5051 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[21]), .Y(
DP_OP_499J248_125_1651_n291) );
OAI21X2TS U5052 ( .A0(n3538), .A1(n4529), .B0(n3529), .Y(n6051) );
INVX8TS U5053 ( .A(n3385), .Y(add_x_69_n328) );
OAI21X2TS U5054 ( .A0(add_x_69_n301), .A1(n6418), .B0(n6083), .Y(
add_x_69_n298) );
INVX3TS U5055 ( .A(n2697), .Y(n2887) );
INVX2TS U5056 ( .A(n2697), .Y(n2888) );
AOI21X1TS U5057 ( .A0(n3693), .A1(FPADDSUB_Data_array_SWR[22]), .B0(n7949),
.Y(n7765) );
INVX2TS U5058 ( .A(n2697), .Y(n2889) );
CLKBUFX3TS U5059 ( .A(n9769), .Y(n9759) );
NAND2X1TS U5060 ( .A(n9513), .B(n8406), .Y(n9923) );
NAND2X1TS U5061 ( .A(n9513), .B(n8534), .Y(n9916) );
NAND2X1TS U5062 ( .A(n9513), .B(n8537), .Y(n9914) );
INVX2TS U5063 ( .A(n2840), .Y(n2928) );
NAND2X1TS U5064 ( .A(n9513), .B(n8403), .Y(n9922) );
INVX2TS U5065 ( .A(n7289), .Y(n7293) );
INVX2TS U5066 ( .A(n2729), .Y(n2728) );
NOR2BX1TS U5067 ( .AN(n9728), .B(n2549), .Y(n2729) );
BUFX3TS U5068 ( .A(n2871), .Y(n9755) );
INVX2TS U5069 ( .A(n2840), .Y(n2876) );
INVX2TS U5070 ( .A(n2856), .Y(n2874) );
INVX2TS U5071 ( .A(n2850), .Y(n2860) );
INVX2TS U5072 ( .A(n2840), .Y(n2877) );
INVX3TS U5073 ( .A(n2856), .Y(n2927) );
CLKBUFX3TS U5074 ( .A(n2852), .Y(n9762) );
INVX3TS U5075 ( .A(n2840), .Y(n2841) );
CLKBUFX3TS U5076 ( .A(n2855), .Y(n9768) );
INVX2TS U5077 ( .A(n2856), .Y(n2847) );
CLKBUFX3TS U5078 ( .A(n2853), .Y(n9760) );
CLKBUFX3TS U5079 ( .A(n8252), .Y(n9753) );
CLKBUFX3TS U5080 ( .A(n2857), .Y(n9756) );
CLKBUFX3TS U5081 ( .A(n8251), .Y(n9766) );
BUFX3TS U5082 ( .A(n8251), .Y(n9761) );
AOI2BB2X2TS U5083 ( .B0(n8083), .B1(n1578), .A0N(n2914), .A1N(n9106), .Y(
n5021) );
AOI2BB2X2TS U5084 ( .B0(n8092), .B1(n1589), .A0N(n2916), .A1N(n9255), .Y(
n8095) );
NAND2X2TS U5085 ( .A(n8093), .B(n8244), .Y(n6107) );
NAND3X1TS U5086 ( .A(n9750), .B(n9843), .C(FPMULT_FSM_selector_B[1]), .Y(
n8036) );
CLKINVX3TS U5087 ( .A(n2882), .Y(n2883) );
INVX2TS U5088 ( .A(n2865), .Y(n2875) );
BUFX3TS U5089 ( .A(n8251), .Y(n9763) );
INVX2TS U5090 ( .A(n2856), .Y(n2858) );
CLKINVX3TS U5091 ( .A(n2697), .Y(n2849) );
INVX2TS U5092 ( .A(n2865), .Y(n2848) );
INVX2TS U5093 ( .A(n2865), .Y(n2866) );
OA22X2TS U5094 ( .A0(n5057), .A1(n4549), .B0(n2216), .B1(n4598), .Y(n2615)
);
AOI2BB2X4TS U5095 ( .B0(n2617), .B1(n4345), .A0N(n5057), .A1N(n4671), .Y(
n2616) );
ADDHX4TS U5096 ( .A(DP_OP_497J248_123_1725_n793), .B(
DP_OP_497J248_123_1725_n699), .CO(n4346), .S(n4345) );
OA22X2TS U5097 ( .A0(n5056), .A1(n5055), .B0(n5057), .B1(n5072), .Y(n2618)
);
XOR2X4TS U5098 ( .A(n5750), .B(n5606), .Y(n5474) );
NAND2X4TS U5099 ( .A(n3239), .B(n4471), .Y(n5180) );
NAND2X6TS U5100 ( .A(n3001), .B(n5152), .Y(n3144) );
NAND2X4TS U5101 ( .A(n3948), .B(n3949), .Y(n3548) );
INVX4TS U5102 ( .A(n3949), .Y(n3550) );
XOR2X4TS U5103 ( .A(n2725), .B(n3084), .Y(n2621) );
XOR2X4TS U5104 ( .A(n3449), .B(n2622), .Y(DP_OP_499J248_125_1651_n267) );
XOR2X4TS U5105 ( .A(n3501), .B(n2623), .Y(n6219) );
OR2X6TS U5106 ( .A(n6242), .B(n3506), .Y(n3503) );
CLKINVX12TS U5107 ( .A(n2736), .Y(n5074) );
NAND2X6TS U5108 ( .A(n3422), .B(n3165), .Y(n3421) );
OAI22X2TS U5109 ( .A0(n5056), .A1(n5050), .B0(n5091), .B1(n2339), .Y(n5044)
);
INVX6TS U5110 ( .A(n8772), .Y(n5942) );
NAND2X6TS U5111 ( .A(n4136), .B(n4135), .Y(n5916) );
OAI22X2TS U5112 ( .A0(n5438), .A1(n5453), .B0(n5454), .B1(n4897), .Y(n5434)
);
XNOR2X1TS U5113 ( .A(n6014), .B(n6013), .Y(n6016) );
INVX8TS U5114 ( .A(n4084), .Y(n4086) );
ADDFHX4TS U5115 ( .A(n4653), .B(n4652), .CI(n4654), .CO(n5039), .S(n4673) );
NAND3X8TS U5116 ( .A(n3354), .B(n3353), .C(n2630), .Y(n3352) );
NOR2X2TS U5117 ( .A(n6419), .B(n6418), .Y(add_x_69_n294) );
NOR3X6TS U5118 ( .A(DP_OP_497J248_123_1725_n389), .B(n8866), .C(n2605), .Y(
n3420) );
XNOR2X4TS U5119 ( .A(n3446), .B(n2627), .Y(DP_OP_499J248_125_1651_n273) );
AND2X8TS U5120 ( .A(n3317), .B(n3174), .Y(n2627) );
CMPR22X2TS U5121 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n6434), .CO(
add_x_246_n6), .S(FPMULT_Adder_M_result_A_adder[18]) );
NOR2X4TS U5122 ( .A(n5819), .B(n6368), .Y(n5541) );
ADDFHX4TS U5123 ( .A(n5501), .B(n5500), .CI(n5499), .CO(n5518), .S(n5485) );
XNOR2X4TS U5124 ( .A(n3352), .B(n6172), .Y(n2628) );
XNOR2X4TS U5125 ( .A(n3352), .B(n6172), .Y(n2629) );
NAND3X4TS U5126 ( .A(n3389), .B(n2642), .C(n3388), .Y(n3386) );
INVX16TS U5127 ( .A(n3508), .Y(n8102) );
AND2X8TS U5128 ( .A(n4319), .B(n4318), .Y(n2632) );
NOR2BX4TS U5129 ( .AN(n3153), .B(n3173), .Y(n3135) );
INVX8TS U5130 ( .A(n5913), .Y(n3227) );
XOR2X4TS U5131 ( .A(n3439), .B(n3506), .Y(n3314) );
NAND2X4TS U5132 ( .A(n2621), .B(n4322), .Y(n6225) );
NAND2BX4TS U5133 ( .AN(n2620), .B(n4483), .Y(n2994) );
NAND2X8TS U5134 ( .A(n3350), .B(n3349), .Y(n2725) );
NOR2X4TS U5135 ( .A(n2205), .B(n2214), .Y(n4214) );
NAND2X6TS U5136 ( .A(n4264), .B(n4263), .Y(n4296) );
NOR2X2TS U5137 ( .A(n3479), .B(n3463), .Y(n2642) );
OR2X8TS U5138 ( .A(n8774), .B(FPADDSUB_ADD_OVRFLW_NRM), .Y(n2646) );
INVX4TS U5139 ( .A(n3627), .Y(n9639) );
INVX4TS U5140 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n2899) );
INVX2TS U5141 ( .A(n2840), .Y(n2880) );
CLKBUFX3TS U5142 ( .A(n8251), .Y(n9764) );
CLKINVX6TS U5143 ( .A(n3189), .Y(n4142) );
NAND2X6TS U5144 ( .A(n4112), .B(n3190), .Y(n3189) );
AND2X8TS U5145 ( .A(n3365), .B(n5847), .Y(n2655) );
OA21X4TS U5146 ( .A0(n5819), .A1(n3055), .B0(n5820), .Y(n2656) );
XNOR2X2TS U5147 ( .A(n5264), .B(n5312), .Y(n2658) );
AND2X8TS U5148 ( .A(n3040), .B(n4138), .Y(n2659) );
NAND2X4TS U5149 ( .A(n4121), .B(n4122), .Y(n5890) );
INVX4TS U5150 ( .A(n4110), .Y(n4112) );
OR2X4TS U5151 ( .A(n6225), .B(n6172), .Y(n2663) );
AND2X4TS U5152 ( .A(n2639), .B(n3458), .Y(n2666) );
AND2X4TS U5153 ( .A(n9040), .B(n9037), .Y(n2668) );
INVX4TS U5154 ( .A(n2749), .Y(n3094) );
INVX2TS U5155 ( .A(n4479), .Y(n4480) );
INVX2TS U5156 ( .A(n4296), .Y(n3463) );
INVX2TS U5157 ( .A(n5948), .Y(n5700) );
INVX2TS U5158 ( .A(n4867), .Y(FPMULT_Sgf_operation_EVEN1_Q_left[0]) );
NOR2X2TS U5159 ( .A(n6726), .B(n6728), .Y(n5023) );
INVX12TS U5160 ( .A(n3325), .Y(n5451) );
INVX4TS U5161 ( .A(n6368), .Y(n3321) );
OR2X8TS U5162 ( .A(n4609), .B(n4608), .Y(n2670) );
INVX2TS U5163 ( .A(n5946), .Y(n6061) );
AND2X2TS U5164 ( .A(n4285), .B(n4304), .Y(n2671) );
AND2X2TS U5165 ( .A(n7490), .B(n7489), .Y(n2672) );
OR2X4TS U5166 ( .A(DP_OP_496J248_122_3540_n1514), .B(
DP_OP_496J248_122_3540_n1501), .Y(n2673) );
INVX2TS U5167 ( .A(n5652), .Y(n2709) );
INVX2TS U5168 ( .A(n6059), .Y(n2992) );
OR2X2TS U5169 ( .A(n2669), .B(n5801), .Y(n2678) );
INVX8TS U5170 ( .A(n5590), .Y(n5728) );
INVX2TS U5171 ( .A(n3312), .Y(n5298) );
OR2X4TS U5172 ( .A(n5184), .B(n3106), .Y(n3312) );
NOR2X4TS U5173 ( .A(DP_OP_496J248_122_3540_n1476), .B(
DP_OP_496J248_122_3540_n778), .Y(n5218) );
INVX12TS U5174 ( .A(n5193), .Y(n2906) );
INVX12TS U5175 ( .A(n5762), .Y(n5732) );
INVX2TS U5176 ( .A(n6215), .Y(n5311) );
AOI21X4TS U5177 ( .A0(n7129), .A1(n7128), .B0(n7127), .Y(n7130) );
CLKXOR2X2TS U5178 ( .A(n4201), .B(n4238), .Y(n2681) );
OR2X2TS U5179 ( .A(n7430), .B(n7429), .Y(n2683) );
AND2X2TS U5180 ( .A(n4316), .B(n4324), .Y(n2685) );
XOR2X1TS U5181 ( .A(n6241), .B(n6240), .Y(n6244) );
OR2X8TS U5182 ( .A(n8456), .B(n7259), .Y(n2687) );
OR2X2TS U5183 ( .A(n4607), .B(n4606), .Y(n2688) );
OR2X2TS U5184 ( .A(n1677), .B(n1665), .Y(n2692) );
INVX2TS U5185 ( .A(n2856), .Y(n2872) );
CLKINVX3TS U5186 ( .A(n2865), .Y(n2881) );
INVX2TS U5187 ( .A(n2850), .Y(n2873) );
INVX2TS U5188 ( .A(n2856), .Y(n2861) );
CLKINVX3TS U5189 ( .A(n2850), .Y(n2862) );
CLKBUFX3TS U5190 ( .A(n8251), .Y(n9767) );
INVX2TS U5191 ( .A(n2850), .Y(n2851) );
INVX2TS U5192 ( .A(n2882), .Y(n2863) );
INVX2TS U5193 ( .A(n2892), .Y(n2864) );
INVX2TS U5194 ( .A(rst), .Y(n2843) );
INVX2TS U5195 ( .A(rst), .Y(n2842) );
INVX2TS U5196 ( .A(n2865), .Y(n2867) );
INVX2TS U5197 ( .A(n9754), .Y(n2865) );
INVX2TS U5198 ( .A(n9770), .Y(n2850) );
INVX2TS U5199 ( .A(n9765), .Y(n2856) );
NAND2X2TS U5200 ( .A(n8691), .B(n6180), .Y(n2797) );
NAND2X2TS U5201 ( .A(n8691), .B(n6180), .Y(n2796) );
INVX2TS U5202 ( .A(n2892), .Y(n2839) );
INVX2TS U5203 ( .A(n9819), .Y(n2892) );
INVX2TS U5204 ( .A(n9531), .Y(n2882) );
NAND2X2TS U5205 ( .A(n8494), .B(n9774), .Y(n2697) );
CLKBUFX2TS U5206 ( .A(n9773), .Y(n9770) );
INVX2TS U5207 ( .A(n2850), .Y(n2870) );
INVX2TS U5208 ( .A(n2840), .Y(n2869) );
INVX2TS U5209 ( .A(n2697), .Y(n2855) );
INVX2TS U5210 ( .A(n2865), .Y(n2853) );
INVX2TS U5211 ( .A(n2856), .Y(n2871) );
INVX2TS U5212 ( .A(n2850), .Y(n2854) );
INVX2TS U5213 ( .A(n2840), .Y(n2868) );
INVX2TS U5214 ( .A(n2850), .Y(n2852) );
BUFX3TS U5215 ( .A(n9769), .Y(n9771) );
INVX2TS U5216 ( .A(n2856), .Y(n2857) );
INVX2TS U5217 ( .A(n2865), .Y(n2926) );
INVX2TS U5218 ( .A(n2840), .Y(n2859) );
OR2X8TS U5219 ( .A(n3145), .B(n2747), .Y(n4159) );
XNOR2X4TS U5220 ( .A(n3266), .B(n3146), .Y(n3145) );
NOR2X8TS U5221 ( .A(n4059), .B(n2698), .Y(n3173) );
OAI2BB1X4TS U5222 ( .A0N(n3943), .A1N(n2701), .B0(n2699), .Y(n4010) );
OAI21X4TS U5223 ( .A0(n2701), .A1(n3943), .B0(n2700), .Y(n2699) );
XOR2X4TS U5224 ( .A(n2702), .B(n3943), .Y(n3945) );
XOR2X4TS U5225 ( .A(n4282), .B(n4074), .Y(n2702) );
NAND2X8TS U5226 ( .A(n3493), .B(n5446), .Y(n5746) );
XOR2X4TS U5227 ( .A(n3494), .B(n3495), .Y(n5505) );
NAND3BX4TS U5228 ( .AN(n5449), .B(n5446), .C(n3493), .Y(n2703) );
AOI21X4TS U5229 ( .A0(n2366), .A1(n5228), .B0(n5227), .Y(n2704) );
NAND3X8TS U5230 ( .A(n2708), .B(n5430), .C(n2707), .Y(n2977) );
OAI22X4TS U5231 ( .A0(n5554), .A1(n5360), .B0(n5416), .B1(n5553), .Y(n5440)
);
XOR2X4TS U5232 ( .A(n2948), .B(n2338), .Y(n5360) );
XOR2X4TS U5233 ( .A(n5441), .B(n5440), .Y(n3435) );
XNOR2X4TS U5234 ( .A(n2710), .B(n5213), .Y(n5502) );
NAND2X4TS U5235 ( .A(n2366), .B(n2673), .Y(n2711) );
INVX16TS U5236 ( .A(n2713), .Y(n5554) );
OAI22X4TS U5237 ( .A0(n5511), .A1(n5554), .B0(n5552), .B1(n5553), .Y(n5555)
);
NOR2X8TS U5238 ( .A(n2658), .B(n2712), .Y(n2713) );
XNOR2X4TS U5239 ( .A(n5258), .B(n5257), .Y(n2712) );
OAI22X4TS U5240 ( .A0(n5508), .A1(n5654), .B0(n5653), .B1(n5561), .Y(n2715)
);
OAI2BB1X4TS U5241 ( .A0N(n5551), .A1N(n2715), .B0(n2714), .Y(n6332) );
XNOR2X4TS U5242 ( .A(n5558), .B(n5559), .Y(n5508) );
XOR2X4TS U5243 ( .A(n5208), .B(n2718), .Y(n5209) );
INVX8TS U5244 ( .A(n2717), .Y(n2718) );
NAND2X8TS U5245 ( .A(n2717), .B(n2716), .Y(n2720) );
NAND2X8TS U5246 ( .A(n3629), .B(n2719), .Y(n5189) );
XOR2X4TS U5247 ( .A(n5590), .B(n5596), .Y(n5587) );
AOI21X4TS U5248 ( .A0(n3393), .A1(n6157), .B0(n6156), .Y(
DP_OP_496J248_122_3540_n39) );
XNOR2X4TS U5249 ( .A(n3393), .B(n5812), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
NAND3X8TS U5250 ( .A(n3058), .B(n3059), .C(n3056), .Y(n3393) );
NAND2X8TS U5251 ( .A(n2720), .B(n5214), .Y(n5254) );
OAI21X4TS U5252 ( .A0(DP_OP_496J248_122_3540_n1098), .A1(n5187), .B0(n9037),
.Y(n5401) );
NAND2X8TS U5253 ( .A(n2721), .B(n2722), .Y(n5817) );
OR2X8TS U5254 ( .A(n5259), .B(n5413), .Y(n2721) );
XNOR2X4TS U5255 ( .A(n2960), .B(n5556), .Y(n5259) );
XOR2X4TS U5256 ( .A(n5275), .B(n5274), .Y(n2979) );
NOR2X8TS U5257 ( .A(n3256), .B(n4322), .Y(n6224) );
XOR2X4TS U5258 ( .A(n2725), .B(n3084), .Y(n3256) );
XNOR2X4TS U5259 ( .A(n2727), .B(n8940), .Y(n3774) );
OAI21X4TS U5260 ( .A0(n2730), .A1(n2296), .B0(n2728), .Y(n1585) );
OAI21X4TS U5261 ( .A0(n7280), .A1(n7290), .B0(n7281), .Y(n3822) );
XOR2X4TS U5262 ( .A(n2733), .B(n3805), .Y(n3821) );
AOI21X4TS U5263 ( .A0(n3832), .A1(n3800), .B0(n3799), .Y(n2733) );
NOR2X8TS U5264 ( .A(n5174), .B(n5176), .Y(n3416) );
NOR2X8TS U5265 ( .A(n3455), .B(n5156), .Y(n5176) );
XOR2X4TS U5266 ( .A(n2735), .B(n2734), .Y(n3455) );
AOI21X4TS U5267 ( .A0(n3176), .A1(n5131), .B0(n5132), .Y(n2735) );
XNOR2X4TS U5268 ( .A(n3123), .B(n3122), .Y(n5155) );
INVX12TS U5269 ( .A(n5074), .Y(n3243) );
XNOR2X4TS U5270 ( .A(n3520), .B(DP_OP_497J248_123_1725_n367), .Y(n2736) );
OAI2BB1X4TS U5271 ( .A0N(n4656), .A1N(n2739), .B0(n2737), .Y(n5038) );
XOR2X4TS U5272 ( .A(n2738), .B(n4656), .Y(n4676) );
XOR2X4TS U5273 ( .A(n4655), .B(n2739), .Y(n2738) );
XNOR2X4TS U5274 ( .A(n2740), .B(n3319), .Y(n4609) );
INVX6TS U5275 ( .A(n2741), .Y(n4872) );
XOR2X4TS U5276 ( .A(n2742), .B(DP_OP_496J248_122_3540_n1122), .Y(n2741) );
NOR2X8TS U5277 ( .A(n2640), .B(n3223), .Y(n3395) );
XOR2X4TS U5278 ( .A(n2745), .B(n2999), .Y(n5390) );
XNOR2X4TS U5279 ( .A(n2744), .B(n5392), .Y(n2999) );
XOR2X4TS U5280 ( .A(n5391), .B(n6322), .Y(n2744) );
XOR2X4TS U5281 ( .A(n5442), .B(n5443), .Y(n2745) );
OR2X8TS U5282 ( .A(n2746), .B(n5157), .Y(n3482) );
NAND2X4TS U5283 ( .A(n5157), .B(n2746), .Y(n6218) );
XOR2X4TS U5284 ( .A(n5101), .B(n2674), .Y(n2746) );
NOR2X8TS U5285 ( .A(n4158), .B(n3173), .Y(n3267) );
AND2X8TS U5286 ( .A(n3145), .B(n2747), .Y(n4158) );
OAI21X4TS U5287 ( .A0(n4057), .A1(n2422), .B0(n3266), .Y(n2748) );
XOR2X4TS U5288 ( .A(n4389), .B(n4390), .Y(n3537) );
INVX2TS U5289 ( .A(n8103), .Y(n2751) );
NAND2X8TS U5290 ( .A(n2752), .B(n6004), .Y(n8103) );
NAND2X8TS U5291 ( .A(n3394), .B(n3396), .Y(n2767) );
OAI2BB1X4TS U5292 ( .A0N(n4177), .A1N(n2585), .B0(n2758), .Y(n4227) );
OAI21X4TS U5293 ( .A0(n2585), .A1(n4177), .B0(n4176), .Y(n2758) );
XOR2X4TS U5294 ( .A(n2759), .B(n4176), .Y(n4173) );
XOR2X4TS U5295 ( .A(n4177), .B(n4178), .Y(n2759) );
OAI21X4TS U5296 ( .A0(n3139), .A1(n2764), .B0(n2763), .Y(n2762) );
NAND2X8TS U5297 ( .A(n8856), .B(n2564), .Y(n2765) );
NOR2X8TS U5298 ( .A(DP_OP_498J248_124_1725_n643), .B(
DP_OP_498J248_124_1725_n730), .Y(n3139) );
XNOR2X4TS U5299 ( .A(n3216), .B(n3347), .Y(n2766) );
BUFX16TS U5300 ( .A(n3095), .Y(n2771) );
NAND2X4TS U5301 ( .A(n3443), .B(n3095), .Y(n3389) );
NAND2X8TS U5302 ( .A(n3004), .B(n3005), .Y(n3095) );
XOR2X4TS U5303 ( .A(n2773), .B(n3188), .Y(n6300) );
NAND2X8TS U5304 ( .A(n2772), .B(n5785), .Y(n3188) );
OAI21X4TS U5305 ( .A0(n5954), .A1(n5952), .B0(n5953), .Y(n3049) );
INVX8TS U5306 ( .A(n5794), .Y(n2774) );
OAI2BB1X4TS U5307 ( .A0N(n4636), .A1N(n4635), .B0(n2775), .Y(n4664) );
OAI21X4TS U5308 ( .A0(n4635), .A1(n4636), .B0(n4634), .Y(n2775) );
XOR2X4TS U5309 ( .A(n2776), .B(n4634), .Y(n4639) );
XOR2X4TS U5310 ( .A(n4635), .B(n4636), .Y(n2776) );
OR2X8TS U5311 ( .A(n2778), .B(n5158), .Y(n3481) );
XOR2X4TS U5312 ( .A(n3044), .B(n2779), .Y(n2778) );
NOR2X8TS U5313 ( .A(DP_OP_497J248_123_1725_n634), .B(n2607), .Y(n4418) );
OAI21X4TS U5314 ( .A0(n4677), .A1(n4678), .B0(n4676), .Y(n2780) );
OAI2BB1X4TS U5315 ( .A0N(n4677), .A1N(n4678), .B0(n2780), .Y(n5040) );
NAND2X8TS U5316 ( .A(n4140), .B(n2781), .Y(n3040) );
OR2X8TS U5317 ( .A(n3937), .B(n3936), .Y(n2781) );
NAND2X8TS U5318 ( .A(n2782), .B(n3179), .Y(n3242) );
NAND2X8TS U5319 ( .A(n3089), .B(n4567), .Y(n2782) );
XOR2X4TS U5320 ( .A(n2782), .B(n3245), .Y(n3480) );
XNOR2X4TS U5321 ( .A(n5059), .B(n5061), .Y(n3161) );
NOR2BX4TS U5322 ( .AN(n2783), .B(DP_OP_498J248_124_1725_n728), .Y(n4023) );
NOR2X8TS U5323 ( .A(n3947), .B(DP_OP_498J248_124_1725_n638), .Y(n3516) );
XOR2X4TS U5324 ( .A(n2785), .B(n2784), .Y(DP_OP_499J248_125_1651_n293) );
NAND2X1TS U5325 ( .A(n3481), .B(n5995), .Y(n2784) );
AOI21X4TS U5326 ( .A0(n2248), .A1(n3462), .B0(n2787), .Y(n2786) );
XNOR2X4TS U5327 ( .A(n5572), .B(n2338), .Y(n5504) );
NAND3X8TS U5328 ( .A(n2789), .B(n2790), .C(n2791), .Y(n5572) );
OAI22X4TS U5329 ( .A0(n5511), .A1(n5553), .B0(n5554), .B1(n5504), .Y(n5512)
);
INVX12TS U5330 ( .A(n4632), .Y(n2794) );
NAND2X4TS U5331 ( .A(n3091), .B(n5799), .Y(n3330) );
OAI21X4TS U5332 ( .A0(n5922), .A1(n5921), .B0(n5920), .Y(n6066) );
NAND2X4TS U5333 ( .A(n3845), .B(n3960), .Y(n3846) );
NAND2X4TS U5334 ( .A(DP_OP_498J248_124_1725_n798), .B(
DP_OP_498J248_124_1725_n804), .Y(n3960) );
OAI22X2TS U5335 ( .A0(n4030), .A1(n4035), .B0(n2322), .B1(n4184), .Y(n3901)
);
NAND2X6TS U5336 ( .A(n5912), .B(n5913), .Y(n6044) );
AOI2BB2X4TS U5337 ( .B0(n3461), .B1(n4346), .A0N(n5057), .A1N(n4619), .Y(
n2800) );
OR2X8TS U5338 ( .A(n5390), .B(n5389), .Y(n6052) );
NOR2X8TS U5339 ( .A(n3624), .B(n4206), .Y(n3875) );
NAND2X4TS U5340 ( .A(n3099), .B(n3098), .Y(n3097) );
OR2X8TS U5341 ( .A(n3744), .B(n3743), .Y(n3768) );
NAND2X4TS U5342 ( .A(n4707), .B(n4701), .Y(n4710) );
XOR2X4TS U5343 ( .A(n4539), .B(n4538), .Y(n2802) );
XOR2X4TS U5344 ( .A(n4540), .B(n2802), .Y(n4551) );
NAND2X2TS U5345 ( .A(n2262), .B(n4540), .Y(n2803) );
NAND2X2TS U5346 ( .A(n4539), .B(n2262), .Y(n2805) );
ADDHX4TS U5347 ( .A(DP_OP_497J248_123_1725_n692), .B(n8878), .CO(n4538), .S(
n4494) );
OAI22X2TS U5348 ( .A0(n2795), .A1(n4549), .B0(n2962), .B1(n4598), .Y(n4368)
);
INVX8TS U5349 ( .A(n2987), .Y(n3103) );
OAI22X4TS U5350 ( .A0(n5721), .A1(n5489), .B0(n2331), .B1(n5488), .Y(n5507)
);
ADDFHX4TS U5351 ( .A(n5613), .B(n5612), .CI(n5611), .CO(n5618), .S(n5545) );
ADDFHX4TS U5352 ( .A(n5565), .B(n5564), .CI(n3466), .CO(n5614), .S(n5611) );
OAI22X4TS U5353 ( .A0(n5598), .A1(n5437), .B0(n5456), .B1(n2900), .Y(n5466)
);
ADDFHX4TS U5354 ( .A(DP_OP_497J248_123_1725_n604), .B(
DP_OP_497J248_123_1725_n609), .CI(n4410), .CO(n4419), .S(n4412) );
NAND2X6TS U5355 ( .A(n3514), .B(n3138), .Y(n3232) );
ADDFHX4TS U5356 ( .A(n5516), .B(n5515), .CI(n5514), .CO(n5527), .S(n5525) );
OAI22X4TS U5357 ( .A0(n5483), .A1(n2903), .B0(n5419), .B1(n5566), .Y(n5514)
);
NAND2BX2TS U5358 ( .AN(n6089), .B(n6090), .Y(n3517) );
NOR2X4TS U5359 ( .A(n6089), .B(n3309), .Y(n3057) );
INVX6TS U5360 ( .A(n6070), .Y(n5731) );
ADDFHX4TS U5361 ( .A(n4578), .B(n4577), .CI(n4576), .CO(n4616), .S(n4580) );
OAI22X2TS U5362 ( .A0(n2794), .A1(n5055), .B0(n4597), .B1(n5072), .Y(n4576)
);
OAI22X4TS U5363 ( .A0(n5554), .A1(n5552), .B0(n5266), .B1(n5553), .Y(n5294)
);
ADDHX4TS U5364 ( .A(n5294), .B(n5293), .CO(n6210), .S(n6215) );
NAND2X4TS U5365 ( .A(n6417), .B(n6416), .Y(add_x_69_n29) );
XOR2X2TS U5366 ( .A(n4483), .B(n2620), .Y(n2997) );
NAND2X4TS U5367 ( .A(n3174), .B(n6015), .Y(n3318) );
OAI22X2TS U5368 ( .A0(n3507), .A1(n4206), .B0(n3030), .B1(n4253), .Y(n4037)
);
BUFX12TS U5369 ( .A(n5183), .Y(n3106) );
NAND2X8TS U5370 ( .A(n4569), .B(n4568), .Y(n3089) );
ADDFHX4TS U5371 ( .A(n5280), .B(n5817), .CI(n5279), .CO(n5273), .S(n5288) );
INVX4TS U5372 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .Y(n5903) );
NAND2X4TS U5373 ( .A(n4473), .B(n4472), .Y(n5827) );
XOR2X2TS U5374 ( .A(n4866), .B(n3300), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[4]) );
BUFX12TS U5375 ( .A(n5186), .Y(n3127) );
INVX8TS U5376 ( .A(n3170), .Y(n5703) );
XOR2X4TS U5377 ( .A(n3168), .B(n3166), .Y(n2812) );
NAND2X4TS U5378 ( .A(n3167), .B(n5149), .Y(n3166) );
INVX12TS U5379 ( .A(n3436), .Y(n5215) );
ADDFHX2TS U5380 ( .A(n5669), .B(n5670), .CI(n5668), .CO(n5690), .S(n5672) );
NOR2X2TS U5381 ( .A(n5373), .B(n5372), .Y(n5375) );
ADDFHX4TS U5382 ( .A(n5396), .B(n5394), .CI(n5395), .CO(n5494), .S(n5391) );
NAND2XLTS U5383 ( .A(n3454), .B(n6356), .Y(add_x_219_n17) );
OAI22X2TS U5384 ( .A0(n5704), .A1(n5592), .B0(n5639), .B1(n2832), .Y(n5645)
);
OAI21X4TS U5385 ( .A0(n2940), .A1(n6095), .B0(n6094), .Y(n6096) );
NAND2X4TS U5386 ( .A(n3288), .B(n3289), .Y(n3291) );
XOR2X4TS U5387 ( .A(n3357), .B(n2826), .Y(n3356) );
CMPR22X2TS U5388 ( .A(n4168), .B(n4167), .CO(n4221), .S(n4164) );
BUFX20TS U5389 ( .A(n4269), .Y(n3113) );
AND2X8TS U5390 ( .A(n2814), .B(n2815), .Y(n3851) );
ADDFHX4TS U5391 ( .A(n4717), .B(n4716), .CI(n4715), .CO(n4752), .S(n4720) );
NOR2X4TS U5392 ( .A(n6184), .B(n6187), .Y(n6189) );
INVX6TS U5393 ( .A(n2816), .Y(n2817) );
NAND2BX2TS U5394 ( .AN(n4053), .B(n3200), .Y(n3198) );
OR2X8TS U5395 ( .A(n3283), .B(n3282), .Y(n2818) );
INVX8TS U5396 ( .A(n4672), .Y(n3461) );
NAND2X4TS U5397 ( .A(n4605), .B(n3179), .Y(n3245) );
INVX12TS U5398 ( .A(n3373), .Y(n5655) );
ADDFHX4TS U5399 ( .A(n3967), .B(n3966), .CI(n3965), .CO(n3992), .S(n3944) );
NOR2X2TS U5400 ( .A(n3113), .B(n2650), .Y(n4036) );
ADDFHX4TS U5401 ( .A(n4182), .B(n4181), .CI(n4180), .CO(n4210), .S(n4186) );
NOR2X2TS U5402 ( .A(n6127), .B(n9046), .Y(n6110) );
INVX4TS U5403 ( .A(n3848), .Y(n4031) );
ADDFHX4TS U5404 ( .A(n5077), .B(n5076), .CI(n5075), .CO(n5095), .S(n5065) );
OAI22X2TS U5405 ( .A0(n5056), .A1(n5072), .B0(n5091), .B1(n5055), .Y(n5077)
);
CLKINVX6TS U5406 ( .A(n3502), .Y(n5346) );
NAND2X2TS U5407 ( .A(n5246), .B(n5452), .Y(n5247) );
NOR2X6TS U5408 ( .A(DP_OP_498J248_124_1725_n726), .B(
DP_OP_498J248_124_1725_n728), .Y(n3897) );
ADDFHX4TS U5409 ( .A(n3995), .B(n3996), .CI(n3994), .CO(n4032), .S(n3990) );
ADDFHX4TS U5410 ( .A(n4545), .B(n4546), .CI(n4544), .CO(n4591), .S(n4564) );
NOR2X4TS U5411 ( .A(DP_OP_498J248_124_1725_n724), .B(n3955), .Y(n3869) );
OAI22X2TS U5412 ( .A0(n5656), .A1(n5721), .B0(n5698), .B1(n2331), .Y(n5689)
);
INVX6TS U5413 ( .A(n4214), .Y(n4252) );
AOI21X4TS U5414 ( .A0(n5999), .A1(n5997), .B0(n4957), .Y(n4958) );
NAND2X8TS U5415 ( .A(n3358), .B(DP_OP_498J248_124_1725_n611), .Y(n3200) );
NAND2X2TS U5416 ( .A(n2422), .B(n4057), .Y(n3175) );
AND2X8TS U5417 ( .A(n2822), .B(n2823), .Y(n3850) );
INVX12TS U5418 ( .A(n3030), .Y(n3867) );
ADDFHX4TS U5419 ( .A(n2664), .B(n4355), .CI(n4356), .CO(n4487), .S(n4348) );
ADDFHX4TS U5420 ( .A(n5054), .B(n5052), .CI(n5053), .CO(n5066), .S(n5046) );
INVX6TS U5421 ( .A(n6330), .Y(n5544) );
ADDFHX4TS U5422 ( .A(FPMULT_Op_MY[9]), .B(DP_OP_496J248_122_3540_n1467),
.CI(DP_OP_496J248_122_3540_n829), .CO(n5231), .S(n5184) );
NAND3X6TS U5423 ( .A(n3205), .B(n3203), .C(n3202), .Y(n3201) );
ADDFHX4TS U5424 ( .A(n4218), .B(n4217), .CI(n4216), .CO(n4246), .S(n4203) );
INVX4TS U5425 ( .A(n5115), .Y(n5135) );
NAND2X2TS U5426 ( .A(n2227), .B(n2955), .Y(n4325) );
INVX8TS U5427 ( .A(n3191), .Y(n4048) );
OAI22X2TS U5428 ( .A0(n5057), .A1(n2636), .B0(n2216), .B1(n2638), .Y(n4545)
);
AO21X4TS U5429 ( .A0(n5654), .A1(n5653), .B0(n5652), .Y(n5705) );
OAI22X4TS U5430 ( .A0(n5409), .A1(n5653), .B0(n5359), .B1(n5654), .Y(n5441)
);
OAI22X2TS U5431 ( .A0(n5561), .A1(n5654), .B0(n5574), .B1(n5653), .Y(n5575)
);
NAND2X4TS U5432 ( .A(n3269), .B(n3268), .Y(n4014) );
NAND2X4TS U5433 ( .A(n3270), .B(n3942), .Y(n3268) );
ADDFHX4TS U5434 ( .A(n3895), .B(n3894), .CI(n3893), .CO(n3976), .S(n3859) );
ADDFHX2TS U5435 ( .A(n4367), .B(n4366), .CI(n4365), .CO(n4500), .S(n4382) );
NAND2X4TS U5436 ( .A(n5899), .B(n5898), .Y(n5901) );
OAI2BB1X4TS U5437 ( .A0N(n2825), .A1N(n2826), .B0(n3357), .Y(n3355) );
ADDFHX4TS U5438 ( .A(n4060), .B(n4067), .CI(n3878), .CO(n3880), .S(n3919) );
NOR2X6TS U5439 ( .A(n4489), .B(n2636), .Y(n4375) );
OAI22X2TS U5440 ( .A0(n5057), .A1(n5055), .B0(n4672), .B1(n5072), .Y(n4653)
);
ADDFHX4TS U5441 ( .A(n5466), .B(n5465), .CI(n5464), .CO(n5479), .S(n5490) );
CMPR22X2TS U5442 ( .A(n5435), .B(n5434), .CO(n5492), .S(n5431) );
ADDFHX4TS U5443 ( .A(n5878), .B(n5877), .CI(n5876), .CO(n5902), .S(n5866) );
XOR2X4TS U5444 ( .A(n3375), .B(n5302), .Y(n2828) );
NOR2X4TS U5445 ( .A(DP_OP_498J248_124_1725_n723), .B(n3955), .Y(n3894) );
OAI22X4TS U5446 ( .A0(n5562), .A1(n2331), .B0(n5721), .B1(n5488), .Y(n5613)
);
ADDFHX4TS U5447 ( .A(n3988), .B(n3987), .CI(n3986), .CO(n4027), .S(n4000) );
OAI22X2TS U5448 ( .A0(n5698), .A1(n5721), .B0(n2331), .B1(n5719), .Y(n5734)
);
OAI22X4TS U5449 ( .A0(n5587), .A1(n2969), .B0(n2900), .B1(n5596), .Y(n5595)
);
ADDFHX4TS U5450 ( .A(n5604), .B(n5603), .CI(n5602), .CO(n5924), .S(n5907) );
ADDFHX4TS U5451 ( .A(n4584), .B(n4583), .CI(n4582), .CO(n4634), .S(n4587) );
OAI22X2TS U5452 ( .A0(n5091), .A1(n4549), .B0(n3243), .B1(n4598), .Y(n4584)
);
ADDHX4TS U5453 ( .A(DP_OP_497J248_123_1725_n606), .B(n4384), .CO(n4391), .S(
n4393) );
INVX4TS U5454 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .Y(n5877) );
NOR2X4TS U5455 ( .A(n5825), .B(n2943), .Y(n3010) );
NAND2X4TS U5456 ( .A(n3234), .B(n4460), .Y(n3233) );
ADDFHX4TS U5457 ( .A(n3992), .B(n3991), .CI(n3990), .CO(n4039), .S(n3982) );
ADDFHX4TS U5458 ( .A(n5549), .B(n3467), .CI(n5548), .CO(n5582), .S(n5547) );
ADDFHX2TS U5459 ( .A(n5094), .B(n5092), .CI(n5093), .CO(n5119), .S(n5096) );
NOR2X4TS U5460 ( .A(DP_OP_498J248_124_1725_n727), .B(
DP_OP_498J248_124_1725_n724), .Y(n4024) );
ADDFHX4TS U5461 ( .A(n4026), .B(n2316), .CI(n4025), .CO(n4185), .S(n4054) );
OAI22X2TS U5462 ( .A0(n3391), .A1(n2650), .B0(n4269), .B1(n3964), .Y(n3985)
);
ADDFHX4TS U5463 ( .A(n5662), .B(n6334), .CI(n5661), .CO(n5681), .S(n5671) );
ADDFHX4TS U5464 ( .A(n5616), .B(n5615), .CI(n5614), .CO(n5673), .S(n5617) );
OAI22X4TS U5465 ( .A0(n5563), .A1(n5566), .B0(n5567), .B1(n2903), .Y(n5615)
);
OAI22X4TS U5466 ( .A0(n5571), .A1(n2331), .B0(n5562), .B1(n5721), .Y(n5616)
);
NAND2X4TS U5467 ( .A(n4921), .B(n4920), .Y(n5836) );
XNOR2X4TS U5468 ( .A(n5848), .B(n3299), .Y(n4920) );
NOR2X4TS U5469 ( .A(n8809), .B(n3947), .Y(n3872) );
XNOR2X4TS U5470 ( .A(n2830), .B(n2619), .Y(n5344) );
XOR2X4TS U5471 ( .A(n3337), .B(n5356), .Y(n2830) );
INVX4TS U5472 ( .A(n5588), .Y(n3334) );
NOR3X6TS U5473 ( .A(DP_OP_498J248_124_1725_n643), .B(
DP_OP_498J248_124_1725_n730), .C(DP_OP_498J248_124_1725_n380), .Y(
n3163) );
NOR2X4TS U5474 ( .A(n2583), .B(DP_OP_498J248_124_1725_n723), .Y(n3870) );
ADDFHX4TS U5475 ( .A(n4034), .B(n4033), .CI(n4032), .CO(n4192), .S(n4021) );
ADDFHX4TS U5476 ( .A(n4131), .B(n4130), .CI(n4129), .CO(n4215), .S(n4179) );
ADDFHX4TS U5477 ( .A(n4106), .B(n4105), .CI(n4104), .CO(n4129), .S(n4102) );
OAI22X2TS U5478 ( .A0(n4030), .A1(n4268), .B0(n3361), .B1(n4254), .Y(n4168)
);
NOR2X2TS U5479 ( .A(n3113), .B(n4031), .Y(n4167) );
OAI22X1TS U5480 ( .A0(n2322), .A1(n3989), .B0(n3624), .B1(n4031), .Y(n3918)
);
NOR2X4TS U5481 ( .A(n3492), .B(n5761), .Y(n3491) );
OAI22X4TS U5482 ( .A0(n5704), .A1(n5436), .B0(n5468), .B1(n2832), .Y(n5491)
);
OAI22X4TS U5483 ( .A0(n5468), .A1(n5704), .B0(n5467), .B1(n2832), .Y(n5478)
);
CLKBUFX2TS U5484 ( .A(n6440), .Y(n9818) );
INVX2TS U5485 ( .A(n2888), .Y(n2840) );
CLKBUFX3TS U5486 ( .A(n9769), .Y(n9518) );
CLKBUFX2TS U5487 ( .A(n8251), .Y(n9765) );
INVX2TS U5488 ( .A(n2697), .Y(n2878) );
INVX2TS U5489 ( .A(n2865), .Y(n2879) );
OAI21X2TS U5490 ( .A0(n6869), .A1(n6868), .B0(n6867), .Y(n7129) );
INVX2TS U5491 ( .A(n2890), .Y(n2891) );
INVX2TS U5492 ( .A(n2893), .Y(n2894) );
BUFX3TS U5493 ( .A(n9823), .Y(n6440) );
NOR2X2TS U5494 ( .A(n6933), .B(n6936), .Y(n6974) );
NOR2X2TS U5495 ( .A(n6826), .B(n6829), .Y(n6860) );
NOR2X2TS U5496 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6848) );
AOI21X4TS U5497 ( .A0(n6966), .A1(n6901), .B0(n6900), .Y(n7030) );
AOI21X2TS U5498 ( .A0(n6975), .A1(n6956), .B0(n6955), .Y(n7126) );
OAI21X2TS U5499 ( .A0(n7339), .A1(n7344), .B0(n7340), .Y(n7467) );
NAND2X2TS U5500 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n7344) );
OAI22X2TS U5501 ( .A0(n7324), .A1(n6990), .B0(n9249), .B1(n7322), .Y(n6991)
);
NAND2X2TS U5502 ( .A(n4780), .B(n6185), .Y(n4782) );
CLKINVX6TS U5503 ( .A(n4205), .Y(n2904) );
INVX8TS U5504 ( .A(n2904), .Y(n2905) );
OAI22X2TS U5505 ( .A0(n2905), .A1(n4184), .B0(n3391), .B1(n4035), .Y(n4033)
);
XOR2X4TS U5506 ( .A(n2906), .B(DP_OP_496J248_122_3540_n451), .Y(n5201) );
NAND2BX4TS U5507 ( .AN(n2906), .B(n5594), .Y(n4880) );
CLKINVX6TS U5508 ( .A(n2906), .Y(n3332) );
NAND2X8TS U5509 ( .A(n4875), .B(DP_OP_496J248_122_3540_n1207), .Y(n5193) );
NOR2BX4TS U5510 ( .AN(n5475), .B(n5649), .Y(n5268) );
NOR2X4TS U5511 ( .A(n3692), .B(n8334), .Y(n3693) );
CLKINVX3TS U5512 ( .A(rst), .Y(n2911) );
CLKINVX3TS U5513 ( .A(rst), .Y(n9971) );
INVX2TS U5514 ( .A(n2917), .Y(n2918) );
INVX2TS U5515 ( .A(n2919), .Y(n2920) );
OAI21X4TS U5516 ( .A0(n4280), .A1(n4279), .B0(n4278), .Y(n4308) );
NAND4X2TS U5517 ( .A(n7091), .B(n7090), .C(n7089), .D(n7088), .Y(n1789) );
NAND3BX2TS U5518 ( .AN(n7245), .B(n7244), .C(n7243), .Y(n1792) );
OAI22X4TS U5519 ( .A0(n2216), .A1(n4619), .B0(n2795), .B1(n4671), .Y(n4533)
);
NOR3X1TS U5520 ( .A(n1573), .B(n1574), .C(FPMULT_P_Sgf[5]), .Y(n6734) );
OAI22X2TS U5521 ( .A0(n2322), .A1(n4206), .B0(n3624), .B1(n4253), .Y(n3967)
);
INVX2TS U5522 ( .A(n2931), .Y(n2932) );
INVX2TS U5523 ( .A(n2934), .Y(n2935) );
INVX2TS U5524 ( .A(n2936), .Y(n2937) );
ADDFHX2TS U5525 ( .A(n4250), .B(n4249), .CI(n4248), .CO(n4275), .S(n4247) );
ADDFHX4TS U5526 ( .A(n4212), .B(n4211), .CI(n4210), .CO(n5971), .S(n4329) );
INVX2TS U5527 ( .A(n2941), .Y(n2942) );
NOR2X2TS U5528 ( .A(n7333), .B(n7336), .Y(n7439) );
NOR2X2TS U5529 ( .A(n7345), .B(n7339), .Y(n7463) );
NOR2X4TS U5530 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n6957) );
OAI21X4TS U5531 ( .A0(n6851), .A1(n6850), .B0(n6849), .Y(n6892) );
NAND2X2TS U5532 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6850) );
NOR2X4TS U5533 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6851) );
OAI21X2TS U5534 ( .A0(n7021), .A1(n7020), .B0(n7019), .Y(n7123) );
OAI21X2TS U5535 ( .A0(n6829), .A1(n6828), .B0(n6827), .Y(n6866) );
NOR2X4TS U5536 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n6978) );
OAI21X2TS U5537 ( .A0(n6936), .A1(n6935), .B0(n6934), .Y(n6975) );
OAI21X4TS U5538 ( .A0(n4326), .A1(n4325), .B0(n4324), .Y(n6233) );
XNOR2X2TS U5539 ( .A(n5114), .B(n5113), .Y(n5157) );
XNOR2X4TS U5540 ( .A(n5163), .B(n5162), .Y(n5801) );
XOR2X1TS U5541 ( .A(n4470), .B(n4469), .Y(n5824) );
XNOR2X2TS U5542 ( .A(n5792), .B(n5791), .Y(n5797) );
INVX2TS U5543 ( .A(n2944), .Y(n2945) );
NOR2XLTS U5544 ( .A(dataA[25]), .B(operation_reg_0_), .Y(n8617) );
NOR2X4TS U5545 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n6812) );
NAND2X2TS U5546 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n6814) );
AOI21X2TS U5547 ( .A0(n7467), .A1(n6911), .B0(n6910), .Y(n7407) );
AOI21X2TS U5548 ( .A0(n7443), .A1(n7355), .B0(n7354), .Y(n7456) );
NAND2X2TS U5549 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n7425) );
NAND2X2TS U5550 ( .A(n3659), .B(FPADDSUB_DMP_SFG[21]), .Y(n7419) );
NOR2X2TS U5551 ( .A(n3644), .B(FPADDSUB_intDX_EWSW[25]), .Y(n7871) );
NOR2X2TS U5552 ( .A(n3655), .B(FPADDSUB_intDX_EWSW[17]), .Y(n7857) );
OAI21X1TS U5553 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n3651), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n7856) );
OR2X8TS U5554 ( .A(n6807), .B(FPSENCOS_cont_var_out[0]), .Y(n8728) );
NAND2X6TS U5555 ( .A(n9464), .B(FPSENCOS_cont_var_out[0]), .Y(n7484) );
XNOR2X2TS U5556 ( .A(n5591), .B(n5452), .Y(n5468) );
OAI21X4TS U5557 ( .A0(n4244), .A1(n4243), .B0(n2603), .Y(n3164) );
NAND2X8TS U5558 ( .A(n3445), .B(n3444), .Y(n4287) );
OAI22X4TS U5559 ( .A0(n5570), .A1(n2806), .B0(n5569), .B1(n5746), .Y(n5605)
);
NOR2X6TS U5560 ( .A(n4680), .B(n3509), .Y(n3177) );
ADDFHX4TS U5561 ( .A(n4051), .B(n3280), .CI(n4050), .CO(n4103), .S(n4028) );
INVX4TS U5562 ( .A(n4179), .Y(n4209) );
NOR2X6TS U5563 ( .A(n4361), .B(n4360), .Y(n4513) );
ADDFHX4TS U5564 ( .A(n4537), .B(n4536), .CI(n4535), .CO(n4601), .S(n4552) );
XOR2X4TS U5565 ( .A(n2947), .B(n4568), .Y(n3348) );
AOI21X4TS U5566 ( .A0(n5132), .A1(n5135), .B0(n5085), .Y(n5086) );
OAI21X4TS U5567 ( .A0(n3137), .A1(n5141), .B0(n5142), .Y(n5132) );
ADDHX4TS U5568 ( .A(n3858), .B(n3028), .CO(n3874), .S(n3877) );
NOR2X2TS U5569 ( .A(n5091), .B(n5050), .Y(n5069) );
OAI22X2TS U5570 ( .A0(n4030), .A1(n4254), .B0(n2322), .B1(n4268), .Y(n4038)
);
INVX4TS U5571 ( .A(n3866), .Y(n4169) );
XNOR2X4TS U5572 ( .A(n2966), .B(n3899), .Y(n2965) );
BUFX8TS U5573 ( .A(n5141), .Y(n3178) );
OAI22X2TS U5574 ( .A0(n3243), .A1(n4671), .B0(n5091), .B1(n4619), .Y(n4656)
);
NAND2X6TS U5575 ( .A(n3076), .B(n3053), .Y(n2950) );
XOR2X4TS U5576 ( .A(n2951), .B(n5954), .Y(n8236) );
NAND2X4TS U5577 ( .A(n5953), .B(n2952), .Y(n2951) );
ADDFHX4TS U5578 ( .A(n8958), .B(n8959), .CI(n8960), .CO(n3801), .S(n3780) );
AOI21X4TS U5579 ( .A0(n4707), .A1(n4706), .B0(n4705), .Y(n4708) );
XNOR2X4TS U5580 ( .A(n2953), .B(n4534), .Y(n4532) );
XOR2X4TS U5581 ( .A(n2970), .B(n4533), .Y(n2953) );
INVX4TS U5582 ( .A(n4281), .Y(n3941) );
OR2X8TS U5583 ( .A(n5959), .B(n5958), .Y(n6208) );
AOI2BB2X4TS U5584 ( .B0(n8083), .B1(n8246), .A0N(n2915), .A1N(n8082), .Y(
n8085) );
OAI21X4TS U5585 ( .A0(n2940), .A1(n6166), .B0(n6165), .Y(n6167) );
OR2X8TS U5586 ( .A(n4136), .B(n4135), .Y(n5917) );
OAI22X4TS U5587 ( .A0(n4597), .A1(n2339), .B0(n4489), .B1(n5050), .Y(n4483)
);
XOR2X4TS U5588 ( .A(n3475), .B(n3476), .Y(n3474) );
OAI22X4TS U5589 ( .A0(n8931), .A1(n2794), .B0(n4597), .B1(
DP_OP_497J248_123_1725_n324), .Y(n3476) );
ADDFHX4TS U5590 ( .A(n4398), .B(n4642), .CI(n2551), .CO(n4356), .S(n4372) );
OAI22X2TS U5591 ( .A0(n3243), .A1(n2638), .B0(n5091), .B1(n2636), .Y(n4615)
);
ADDFHX4TS U5592 ( .A(n4350), .B(n4399), .CI(n4607), .CO(n4373), .S(n4374) );
ADDHX4TS U5593 ( .A(n4492), .B(n4491), .CO(n4555), .S(n4496) );
NAND2X8TS U5594 ( .A(n4892), .B(n5703), .Y(n5704) );
AND2X8TS U5595 ( .A(n3568), .B(n5831), .Y(n3528) );
INVX16TS U5596 ( .A(n3339), .Y(n3624) );
NAND2BX4TS U5597 ( .AN(DP_OP_496J248_122_3540_n1458), .B(n2956), .Y(n4871)
);
NOR2X6TS U5598 ( .A(n3232), .B(n3178), .Y(n3230) );
NOR2X8TS U5599 ( .A(n4604), .B(n4603), .Y(n4680) );
XNOR2X4TS U5600 ( .A(DP_OP_496J248_122_3540_n1148), .B(
DP_OP_496J248_122_3540_n1383), .Y(n5588) );
INVX12TS U5601 ( .A(n5074), .Y(n5056) );
NAND2X4TS U5602 ( .A(n5205), .B(n5204), .Y(n4937) );
AOI21X2TS U5603 ( .A0(n5792), .A1(n5790), .B0(n4952), .Y(n5996) );
XOR2X4TS U5604 ( .A(n4496), .B(n4405), .Y(n3109) );
OAI21X4TS U5605 ( .A0(n3963), .A1(n3958), .B0(n3960), .Y(n2957) );
OAI22X4TS U5606 ( .A0(n5415), .A1(n5414), .B0(n5577), .B1(n5413), .Y(n5500)
);
XOR2X4TS U5607 ( .A(n5582), .B(n2959), .Y(n5620) );
XNOR2X4TS U5608 ( .A(n6332), .B(n6333), .Y(n2959) );
CLKINVX12TS U5609 ( .A(n5977), .Y(n3485) );
INVX16TS U5610 ( .A(n3347), .Y(n4160) );
XOR2X4TS U5611 ( .A(n3880), .B(n2961), .Y(n3885) );
ADDFHX4TS U5612 ( .A(n4543), .B(n4542), .CI(n4541), .CO(n4595), .S(n4560) );
OAI21X4TS U5613 ( .A0(n4859), .A1(n4862), .B0(n4860), .Y(n4854) );
XOR2X4TS U5614 ( .A(n5835), .B(n5834), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[9]) );
ADDFHX4TS U5615 ( .A(n4005), .B(n4004), .CI(n4003), .CO(n4056), .S(n3997) );
XOR2X4TS U5616 ( .A(n2964), .B(n2963), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
NAND3X6TS U5617 ( .A(n3254), .B(n3309), .C(n3253), .Y(n2964) );
XNOR2X4TS U5618 ( .A(n2811), .B(n2965), .Y(n3907) );
XOR2X4TS U5619 ( .A(n2968), .B(n2967), .Y(n5637) );
XOR2X4TS U5620 ( .A(n5663), .B(n6332), .Y(n2968) );
OAI22X4TS U5621 ( .A0(n3308), .A1(n2619), .B0(n3401), .B1(n5326), .Y(n3307)
);
XNOR2X4TS U5622 ( .A(n2990), .B(n4889), .Y(n5329) );
OAI22X2TS U5623 ( .A0(n5409), .A1(n5654), .B0(n5498), .B1(n5653), .Y(n5487)
);
ADDFHX2TS U5624 ( .A(n4189), .B(n4190), .CI(n4188), .CO(n4202), .S(n4176) );
NOR2X2TS U5625 ( .A(n5697), .B(n5761), .Y(n5735) );
NOR2X6TS U5626 ( .A(n5151), .B(n5150), .Y(n3143) );
NAND2X8TS U5627 ( .A(n3155), .B(n3156), .Y(n3176) );
BUFX6TS U5628 ( .A(n5655), .Y(n2972) );
XOR2X4TS U5629 ( .A(n3896), .B(n3897), .Y(n3860) );
XOR2X4TS U5630 ( .A(n3557), .B(n3993), .Y(n3991) );
AOI21X4TS U5631 ( .A0(n6054), .A1(n6052), .B0(n2584), .Y(n6375) );
XNOR2X4TS U5632 ( .A(n2974), .B(n5617), .Y(n5631) );
XNOR2X4TS U5633 ( .A(n5618), .B(n5619), .Y(n2974) );
NOR2BX4TS U5634 ( .AN(DP_OP_496J248_122_3540_n1107), .B(n2976), .Y(n3129) );
OAI2BB1X4TS U5635 ( .A0N(n5275), .A1N(n5274), .B0(n2978), .Y(n5335) );
OAI21X4TS U5636 ( .A0(n5275), .A1(n5274), .B0(n5273), .Y(n2978) );
XOR2X4TS U5637 ( .A(n2979), .B(n5273), .Y(n5290) );
OAI21X2TS U5638 ( .A0(n5392), .A1(n5393), .B0(n5391), .Y(n3115) );
OAI22X4TS U5639 ( .A0(n5484), .A1(n5566), .B0(n5563), .B1(n2903), .Y(n5612)
);
NOR2BX4TS U5640 ( .AN(n5412), .B(n5553), .Y(n6213) );
XNOR2X4TS U5641 ( .A(n3176), .B(n3240), .Y(n4689) );
OAI22X2TS U5642 ( .A0(n4672), .A1(n2339), .B0(n2794), .B1(n5050), .Y(n4588)
);
ADDFHX4TS U5643 ( .A(n4557), .B(n4558), .CI(n4556), .CO(n4579), .S(n4559) );
OAI2BB1X4TS U5644 ( .A0N(n3017), .A1N(n2578), .B0(n2980), .Y(n3887) );
OAI21X4TS U5645 ( .A0(n2578), .A1(n3017), .B0(n3881), .Y(n2980) );
NAND2X8TS U5646 ( .A(n2982), .B(n2981), .Y(n3207) );
ADDFHX4TS U5647 ( .A(n4421), .B(n4420), .CI(n4419), .CO(n4422), .S(n4414) );
XNOR2X4TS U5648 ( .A(n5946), .B(n5875), .Y(n5904) );
NAND2X8TS U5649 ( .A(n3335), .B(n2320), .Y(n5946) );
NOR2X8TS U5650 ( .A(DP_OP_497J248_123_1725_n713), .B(n3118), .Y(n4540) );
OAI22X2TS U5651 ( .A0(n5455), .A1(n5454), .B0(n2337), .B1(n5453), .Y(n5471)
);
OAI22X2TS U5652 ( .A0(n4030), .A1(n3989), .B0(n2322), .B1(n4031), .Y(n3914)
);
NAND2X8TS U5653 ( .A(n2983), .B(n6312), .Y(n5152) );
NAND2X8TS U5654 ( .A(n2670), .B(n3294), .Y(n2983) );
INVX8TS U5655 ( .A(n4554), .Y(n4581) );
NAND2X8TS U5656 ( .A(n2984), .B(n3042), .Y(n4004) );
NAND2X8TS U5657 ( .A(n2317), .B(n3093), .Y(n2984) );
ADDFHX4TS U5658 ( .A(n4669), .B(n4668), .CI(n4667), .CO(n5047), .S(n4675) );
XOR2X4TS U5659 ( .A(n3258), .B(n3950), .Y(n2987) );
XNOR2X4TS U5660 ( .A(n3111), .B(n3953), .Y(n3974) );
CLKINVX12TS U5661 ( .A(n2989), .Y(n3152) );
NAND2X8TS U5662 ( .A(n3482), .B(n3481), .Y(n2989) );
NOR2X8TS U5663 ( .A(n5117), .B(n5115), .Y(n3514) );
AO21X4TS U5664 ( .A0(n6066), .A1(n2992), .B0(n2991), .Y(n5944) );
ADDHX1TS U5665 ( .A(n5071), .B(n6346), .CO(n5094), .S(n5068) );
NAND2BX4TS U5666 ( .AN(n4483), .B(n2620), .Y(n2996) );
XNOR2X4TS U5667 ( .A(n2997), .B(n4484), .Y(n4508) );
OAI2BB1X4TS U5668 ( .A0N(n5443), .A1N(n5442), .B0(n2998), .Y(n5444) );
OAI21X1TS U5669 ( .A0(n5443), .A1(n5442), .B0(n2999), .Y(n2998) );
NOR2X8TS U5670 ( .A(n2425), .B(n2583), .Y(n3895) );
OAI22X4TS U5671 ( .A0(n5320), .A1(n5414), .B0(n5367), .B1(n5413), .Y(n5384)
);
XOR2X4TS U5672 ( .A(n5572), .B(n5215), .Y(n5367) );
NAND2X6TS U5673 ( .A(n3421), .B(n2421), .Y(n3105) );
ADDFHX4TS U5674 ( .A(n4624), .B(n4623), .CI(DP_OP_497J248_123_1725_n666),
.CO(n4660), .S(n4629) );
INVX8TS U5675 ( .A(n3313), .Y(n6243) );
NOR2X8TS U5676 ( .A(n5148), .B(n5151), .Y(n3001) );
ADDHX4TS U5677 ( .A(n3970), .B(n3969), .CO(n3993), .S(n3943) );
OAI2BB1X4TS U5678 ( .A0N(n4021), .A1N(n4019), .B0(n3003), .Y(n4163) );
OAI21X4TS U5679 ( .A0(n4019), .A1(n4021), .B0(n4020), .Y(n3003) );
INVX16TS U5680 ( .A(DP_OP_498J248_124_1725_n801), .Y(n3947) );
XOR2X4TS U5681 ( .A(n3011), .B(n3009), .Y(n5851) );
XOR2X4TS U5682 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .B(n8711), .Y(
n3009) );
NOR2X8TS U5683 ( .A(n2655), .B(n3364), .Y(n8711) );
NOR2X8TS U5684 ( .A(n5182), .B(n3010), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[6]) );
OAI2BB1X4TS U5685 ( .A0N(n8696), .A1N(FPMULT_Sgf_operation_EVEN1_Q_left[5]),
.B0(n5848), .Y(n3013) );
XOR2X4TS U5686 ( .A(n3014), .B(n4914), .Y(n8589) );
INVX4TS U5687 ( .A(n2629), .Y(DP_OP_499J248_125_1651_n268) );
XOR2X4TS U5688 ( .A(n3016), .B(n4124), .Y(n4136) );
INVX6TS U5689 ( .A(n3018), .Y(n5934) );
XNOR2X4TS U5690 ( .A(n3019), .B(n5956), .Y(n3018) );
XOR2X4TS U5691 ( .A(n5955), .B(n5957), .Y(n3019) );
XOR2X4TS U5692 ( .A(n2318), .B(n5880), .Y(n5896) );
XNOR2X4TS U5693 ( .A(n3025), .B(n5918), .Y(n8772) );
NAND3X6TS U5694 ( .A(n2318), .B(n5891), .C(n5889), .Y(n3024) );
AND2X8TS U5695 ( .A(n8877), .B(n2641), .Y(n4337) );
NOR2X8TS U5696 ( .A(n4071), .B(n2314), .Y(n4918) );
OR2X8TS U5697 ( .A(n4912), .B(n4914), .Y(n3026) );
NAND2X8TS U5698 ( .A(n4910), .B(n4909), .Y(n4914) );
NOR2X8TS U5699 ( .A(n3947), .B(n3002), .Y(n4910) );
NOR2X8TS U5700 ( .A(n3027), .B(n4068), .Y(n4912) );
INVX12TS U5701 ( .A(n4070), .Y(n3028) );
XNOR2X4TS U5702 ( .A(n3032), .B(DP_OP_498J248_124_1725_n394), .Y(n4008) );
XNOR2X4TS U5703 ( .A(DP_OP_498J248_124_1725_n788), .B(n2813), .Y(n3964) );
XNOR2X4TS U5704 ( .A(n3050), .B(DP_OP_498J248_124_1725_n390), .Y(n3030) );
XOR2X4TS U5705 ( .A(n3404), .B(n3035), .Y(n4093) );
NAND3X6TS U5706 ( .A(n3036), .B(n2667), .C(n4085), .Y(n3035) );
NAND3X6TS U5707 ( .A(n4083), .B(n4086), .C(n2332), .Y(n3036) );
AND2X8TS U5708 ( .A(n4555), .B(n2666), .Y(n4577) );
NAND2X8TS U5709 ( .A(n3039), .B(n3038), .Y(n3347) );
NOR2X8TS U5710 ( .A(n3980), .B(n3981), .Y(n4154) );
NAND2X8TS U5711 ( .A(n3981), .B(n3980), .Y(n4155) );
NAND2X6TS U5712 ( .A(n2588), .B(n3936), .Y(n4138) );
XOR2X4TS U5713 ( .A(n3041), .B(n4027), .Y(n3191) );
XOR2X4TS U5714 ( .A(n4029), .B(n4028), .Y(n3041) );
NOR2X8TS U5715 ( .A(n3955), .B(DP_OP_498J248_124_1725_n721), .Y(n3093) );
NAND2X4TS U5716 ( .A(n3043), .B(n3935), .Y(n4123) );
XOR2X4TS U5717 ( .A(n3426), .B(n2579), .Y(n3043) );
XOR2X4TS U5718 ( .A(n3314), .B(n6243), .Y(DP_OP_499J248_125_1651_n216) );
OAI21X4TS U5719 ( .A0(n3513), .A1(n5133), .B0(n3228), .Y(n3044) );
XOR2X4TS U5720 ( .A(n4555), .B(n2666), .Y(n4541) );
AND2X8TS U5721 ( .A(n3046), .B(n3879), .Y(n3868) );
NAND3X8TS U5722 ( .A(n3386), .B(n3047), .C(n3387), .Y(n3441) );
XOR2X4TS U5723 ( .A(n4286), .B(n2671), .Y(n4320) );
NAND2X8TS U5724 ( .A(n3048), .B(n3479), .Y(n3387) );
CLKXOR2X4TS U5725 ( .A(n3090), .B(n3049), .Y(n6301) );
XOR2X4TS U5726 ( .A(n3051), .B(n2653), .Y(n4474) );
OAI21X4TS U5727 ( .A0(n4524), .A1(n4441), .B0(n4440), .Y(n3051) );
XNOR2X4TS U5728 ( .A(n3052), .B(n4439), .Y(n4475) );
NAND3X8TS U5729 ( .A(n3304), .B(n3060), .C(n6085), .Y(n3058) );
NOR2X8TS U5730 ( .A(n5814), .B(n3484), .Y(n6085) );
NAND2X8TS U5731 ( .A(n6087), .B(n3060), .Y(n3059) );
NOR2X8TS U5732 ( .A(n6086), .B(n6089), .Y(n3060) );
NAND2X8TS U5733 ( .A(n3124), .B(n5979), .Y(n6087) );
OAI2BB1X4TS U5734 ( .A0N(n5061), .A1N(n5059), .B0(n3061), .Y(n5081) );
OR2X8TS U5735 ( .A(n5082), .B(n5081), .Y(n3121) );
OAI21X4TS U5736 ( .A0(n5494), .A1(n3063), .B0(n5493), .Y(n3062) );
XNOR2X4TS U5737 ( .A(n3064), .B(n5493), .Y(n5532) );
XOR2X4TS U5738 ( .A(n5494), .B(n3065), .Y(n3064) );
XNOR2X4TS U5739 ( .A(n5722), .B(n5463), .Y(n5408) );
XNOR2X4TS U5740 ( .A(n5350), .B(n5349), .Y(n5722) );
XNOR2X4TS U5741 ( .A(n4891), .B(n2668), .Y(n3068) );
OA21X4TS U5742 ( .A0(n3252), .A1(n5364), .B0(n5362), .Y(n3071) );
XOR2X4TS U5743 ( .A(n8104), .B(n3074), .Y(add_x_69_n27) );
XOR2X4TS U5744 ( .A(n4961), .B(n6205), .Y(n3074) );
OAI21X4TS U5745 ( .A0(n4959), .A1(n5996), .B0(n4958), .Y(n5838) );
AND2X8TS U5746 ( .A(n4911), .B(n4914), .Y(n8773) );
NAND2X8TS U5747 ( .A(n3263), .B(n3416), .Y(n3076) );
XOR2X4TS U5748 ( .A(n4348), .B(n3078), .Y(n4364) );
XOR2X4TS U5749 ( .A(n4349), .B(n3083), .Y(n3078) );
OAI22X4TS U5750 ( .A0(n4597), .A1(n4619), .B0(n4489), .B1(n4671), .Y(n3083)
);
OAI2BB1X4TS U5751 ( .A0N(n3082), .A1N(n3081), .B0(n4348), .Y(n3080) );
XOR2X4TS U5752 ( .A(n3884), .B(n3088), .Y(n3889) );
XOR2X4TS U5753 ( .A(n4234), .B(n4072), .Y(n3088) );
OR2X8TS U5754 ( .A(n4566), .B(n4565), .Y(n3179) );
XOR2X4TS U5755 ( .A(n4000), .B(n3101), .Y(n3096) );
INVX2TS U5756 ( .A(n3263), .Y(n3298) );
NAND2X8TS U5757 ( .A(n3141), .B(n3144), .Y(n3263) );
OAI2BB1X4TS U5758 ( .A0N(n3985), .A1N(n3100), .B0(n3097), .Y(n4041) );
XOR2X4TS U5759 ( .A(n4001), .B(n4002), .Y(n3101) );
NAND2X4TS U5760 ( .A(n3551), .B(n3550), .Y(n3102) );
XOR2X4TS U5761 ( .A(n3103), .B(n3552), .Y(n3971) );
XOR2X4TS U5762 ( .A(n3104), .B(n4245), .Y(n4258) );
XOR2X4TS U5763 ( .A(n4247), .B(n4246), .Y(n3104) );
ADDFHX4TS U5764 ( .A(n5711), .B(n5710), .CI(n5709), .CO(n5717), .S(n5699) );
OAI22X2TS U5765 ( .A0(n4205), .A1(n4254), .B0(n3361), .B1(n4268), .Y(n4218)
);
NOR2BX4TS U5766 ( .AN(DP_OP_496J248_122_3540_n1504), .B(n9689), .Y(n5229) );
OAI22X4TS U5767 ( .A0(n5457), .A1(n2969), .B0(n5587), .B1(n2900), .Y(n5586)
);
OAI21X2TS U5768 ( .A0(n5146), .A1(n5143), .B0(n5144), .Y(n5125) );
OAI22X4TS U5769 ( .A0(n5650), .A1(n5325), .B0(n5354), .B1(n5649), .Y(n5345)
);
NAND2X4TS U5770 ( .A(n5247), .B(n5248), .Y(n5331) );
XOR2X4TS U5771 ( .A(n2264), .B(DP_OP_498J248_124_1725_n611), .Y(n3987) );
XNOR2X4TS U5772 ( .A(n3109), .B(n4497), .Y(n4505) );
ADDFHX4TS U5773 ( .A(DP_OP_498J248_124_1725_n698), .B(
DP_OP_498J248_124_1725_n703), .CI(n4007), .CO(n4025), .S(n3999) );
NOR2X6TS U5774 ( .A(DP_OP_497J248_123_1725_n717), .B(n2799), .Y(n4353) );
ADDHX4TS U5775 ( .A(n4354), .B(n4353), .CO(n4495), .S(n4684) );
NOR2X4TS U5776 ( .A(n4073), .B(n2821), .Y(n4915) );
OAI2BB1X4TS U5777 ( .A0N(n3954), .A1N(n3953), .B0(n3110), .Y(n3998) );
XNOR2X4TS U5778 ( .A(n3952), .B(n3954), .Y(n3111) );
INVX4TS U5779 ( .A(n5174), .Y(n5799) );
OAI2BB1X2TS U5780 ( .A0N(n4246), .A1N(n4247), .B0(n3114), .Y(n4267) );
OAI21X1TS U5781 ( .A0(n4246), .A1(n4247), .B0(n4245), .Y(n3114) );
XNOR2X2TS U5782 ( .A(n2907), .B(n5732), .Y(n5449) );
XNOR2X4TS U5783 ( .A(n3116), .B(n5672), .Y(n5675) );
XNOR2X4TS U5784 ( .A(n5671), .B(n5673), .Y(n3116) );
OR2X8TS U5785 ( .A(DP_OP_496J248_122_3540_n1494), .B(
DP_OP_496J248_122_3540_n1507), .Y(n4875) );
AND2X8TS U5786 ( .A(n3348), .B(n3154), .Y(n4529) );
NAND2X8TS U5787 ( .A(n3207), .B(n4123), .Y(n4140) );
XNOR2X4TS U5788 ( .A(n3136), .B(n3135), .Y(n3134) );
OAI2BB1X2TS U5789 ( .A0N(n5957), .A1N(n5956), .B0(n3117), .Y(n5958) );
NOR2BX4TS U5790 ( .AN(n2906), .B(n2818), .Y(n5464) );
NOR2X8TS U5791 ( .A(n3947), .B(DP_OP_498J248_124_1725_n634), .Y(n3357) );
AOI21X4TS U5792 ( .A0(n8103), .A1(n5963), .B0(n5962), .Y(n5964) );
NOR2X2TS U5793 ( .A(DP_OP_497J248_123_1725_n367), .B(
DP_OP_497J248_123_1725_n634), .Y(n4431) );
INVX4TS U5794 ( .A(n5108), .Y(n4558) );
OAI22X2TS U5795 ( .A0(n5704), .A1(n2933), .B0(n5592), .B1(n2832), .Y(n5604)
);
OAI21X4TS U5796 ( .A0(n4890), .A1(n3127), .B0(n5187), .Y(n4891) );
XOR2X4TS U5797 ( .A(n3120), .B(n3208), .Y(n3917) );
XOR2X4TS U5798 ( .A(n3017), .B(n3881), .Y(n3120) );
XNOR2X2TS U5799 ( .A(n5262), .B(n5256), .Y(n5257) );
INVX4TS U5800 ( .A(n2421), .Y(n5133) );
NAND2BX4TS U5801 ( .AN(DP_OP_496J248_122_3540_n1477), .B(n9036), .Y(n5255)
);
NOR2X8TS U5802 ( .A(n5633), .B(n5632), .Y(n5814) );
NOR2X8TS U5803 ( .A(n5635), .B(n5634), .Y(n3484) );
NOR2X8TS U5804 ( .A(n5809), .B(n5808), .Y(n6089) );
NAND2X8TS U5805 ( .A(n3362), .B(n3485), .Y(n3124) );
NOR2X8TS U5806 ( .A(DP_OP_496J248_122_3540_n1462), .B(n2807), .Y(n5186) );
NOR2X8TS U5807 ( .A(n3129), .B(n3128), .Y(n4890) );
XOR2X4TS U5808 ( .A(n5699), .B(n3131), .Y(n5683) );
XNOR2X4TS U5809 ( .A(n5701), .B(n5948), .Y(n3131) );
OR2X8TS U5810 ( .A(n5305), .B(n5304), .Y(n5306) );
NAND3X8TS U5811 ( .A(n3133), .B(n3132), .C(n5795), .Y(n6015) );
OR2X6TS U5812 ( .A(n3134), .B(n3371), .Y(n5795) );
NAND3X6TS U5813 ( .A(n3188), .B(n5796), .C(n5794), .Y(n3133) );
NAND2X8TS U5814 ( .A(n3134), .B(n3371), .Y(n5796) );
NOR2X8TS U5815 ( .A(n5099), .B(n5098), .Y(n5117) );
NOR2X8TS U5816 ( .A(n3143), .B(n3142), .Y(n3141) );
XOR2X4TS U5817 ( .A(n4058), .B(n4057), .Y(n3146) );
XOR2X4TS U5818 ( .A(n3147), .B(n4020), .Y(n3266) );
XOR2X4TS U5819 ( .A(n4019), .B(n4021), .Y(n3147) );
OAI21X2TS U5820 ( .A0(n3507), .A1(n4169), .B0(n3148), .Y(n3995) );
NAND2BX4TS U5821 ( .AN(n4213), .B(n3867), .Y(n3148) );
NAND3X6TS U5822 ( .A(n3149), .B(n3392), .C(n4196), .Y(n3182) );
NAND2X8TS U5823 ( .A(n3151), .B(n3150), .Y(n3155) );
NAND2X8TS U5824 ( .A(n2248), .B(n3152), .Y(n3413) );
OR2X8TS U5825 ( .A(n3348), .B(n3154), .Y(n4528) );
XNOR2X4TS U5826 ( .A(n3157), .B(n3158), .Y(n4335) );
OAI21X4TS U5827 ( .A0(n8872), .A1(n8915), .B0(n8874), .Y(n3157) );
XOR2X4TS U5828 ( .A(n3160), .B(n3159), .Y(n5990) );
NAND2X2TS U5829 ( .A(n5796), .B(n5795), .Y(n3160) );
OR2X8TS U5830 ( .A(n3165), .B(n3422), .Y(n5141) );
XOR2X4TS U5831 ( .A(n3161), .B(n5060), .Y(n3165) );
XOR2X4TS U5832 ( .A(n5651), .B(n2338), .Y(n5511) );
XNOR2X4TS U5833 ( .A(FPMULT_Op_MY[10]), .B(DP_OP_496J248_122_3540_n1468),
.Y(n5312) );
NOR2X8TS U5834 ( .A(n5365), .B(n3162), .Y(n5651) );
INVX2TS U5835 ( .A(n6332), .Y(n3187) );
OAI2BB1X4TS U5836 ( .A0N(n4243), .A1N(n4244), .B0(n3164), .Y(n4264) );
XNOR2X4TS U5837 ( .A(n3168), .B(n3166), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[15]) );
INVX2TS U5838 ( .A(n5151), .Y(n3167) );
NAND2BX4TS U5839 ( .AN(n4647), .B(n3169), .Y(n3168) );
XNOR2X4TS U5840 ( .A(n3502), .B(n3331), .Y(n3170) );
NOR2X6TS U5841 ( .A(n5444), .B(n5445), .Y(n6371) );
XNOR2X1TS U5842 ( .A(n6369), .B(n3171), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
NAND2X8TS U5843 ( .A(n3403), .B(n6372), .Y(n3171) );
XOR2X4TS U5844 ( .A(n5840), .B(n3172), .Y(n5481) );
XNOR2X4TS U5845 ( .A(n5841), .B(n3278), .Y(n3172) );
OAI2BB1X4TS U5846 ( .A0N(n5664), .A1N(n3187), .B0(n3186), .Y(n5686) );
OAI21X4TS U5847 ( .A0(n5664), .A1(n3187), .B0(n5663), .Y(n3186) );
XOR2X4TS U5848 ( .A(n3487), .B(n5447), .Y(n5426) );
XOR2X4TS U5849 ( .A(n2212), .B(n3119), .Y(n5592) );
INVX12TS U5850 ( .A(n4077), .Y(n3192) );
XNOR2X4TS U5851 ( .A(n4097), .B(n3193), .Y(n4122) );
XNOR2X4TS U5852 ( .A(n3194), .B(n4107), .Y(n4121) );
OAI21X4TS U5853 ( .A0(n3189), .A1(n4151), .B0(n4100), .Y(n3194) );
XNOR2X4TS U5854 ( .A(n3199), .B(n2589), .Y(n4029) );
NOR2X4TS U5855 ( .A(n4153), .B(n4152), .Y(n5952) );
XNOR2X4TS U5856 ( .A(n4215), .B(n3215), .Y(n4248) );
XOR2X4TS U5857 ( .A(n4252), .B(n4251), .Y(n3215) );
OAI21X4TS U5858 ( .A0(n3218), .A1(n9752), .B0(n3217), .Y(n1566) );
XOR2X4TS U5859 ( .A(n3219), .B(n8099), .Y(n3218) );
XOR2X4TS U5860 ( .A(n3222), .B(n4274), .Y(n4266) );
XOR2X4TS U5861 ( .A(n4273), .B(n4275), .Y(n3222) );
AOI21X4TS U5862 ( .A0(n6046), .A1(n6045), .B0(n3224), .Y(n6176) );
OR2X8TS U5863 ( .A(n6310), .B(n6307), .Y(n3225) );
AOI21X4TS U5864 ( .A0(n6317), .A1(n6316), .B0(n5867), .Y(n6310) );
NAND2X8TS U5865 ( .A(n3227), .B(n3226), .Y(n6045) );
NAND2X8TS U5866 ( .A(n3235), .B(n3233), .Y(n3417) );
NOR2X8TS U5867 ( .A(n3237), .B(n3236), .Y(n3235) );
XOR2X4TS U5868 ( .A(n3238), .B(n5826), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[7]) );
XNOR2X4TS U5869 ( .A(n4465), .B(n4464), .Y(n5825) );
OR2X8TS U5870 ( .A(n3239), .B(n4471), .Y(n5181) );
XOR2X4TS U5871 ( .A(n4524), .B(n4454), .Y(n3239) );
NOR2X8TS U5872 ( .A(n4689), .B(n4688), .Y(n5151) );
NAND2X4TS U5873 ( .A(n3421), .B(n5141), .Y(n3240) );
NAND2X1TS U5874 ( .A(n4625), .B(n2824), .Y(n4444) );
NAND2X4TS U5875 ( .A(n4528), .B(n4529), .Y(n3244) );
NAND2X8TS U5876 ( .A(n4481), .B(n4482), .Y(n3538) );
NAND2X8TS U5877 ( .A(n4477), .B(n3539), .Y(n4482) );
XOR2X4TS U5878 ( .A(DP_OP_497J248_123_1725_n599), .B(
DP_OP_497J248_123_1725_n618), .Y(n4408) );
OAI21X4TS U5879 ( .A0(n4621), .A1(n4622), .B0(n4620), .Y(n3259) );
OAI21X4TS U5880 ( .A0(n5400), .A1(n5461), .B0(n5460), .Y(n3250) );
NAND2X8TS U5881 ( .A(n3402), .B(n5302), .Y(n3249) );
NAND2X4TS U5882 ( .A(n6088), .B(n6087), .Y(n3254) );
OAI2BB1X4TS U5883 ( .A0N(n4390), .A1N(n4389), .B0(n3255), .Y(n4413) );
NAND2X8TS U5884 ( .A(n8848), .B(n8855), .Y(n3258) );
XOR2X4TS U5885 ( .A(n4402), .B(n4642), .Y(n4359) );
XNOR2X4TS U5886 ( .A(n3260), .B(n4620), .Y(n4610) );
NAND3X8TS U5887 ( .A(n3413), .B(n3415), .C(n3414), .Y(n3454) );
NOR2X8TS U5888 ( .A(n3262), .B(n3261), .Y(n3414) );
NOR2X8TS U5889 ( .A(n5994), .B(n6218), .Y(n3262) );
NOR2X8TS U5890 ( .A(n3265), .B(n3264), .Y(n4386) );
OAI21X4TS U5891 ( .A0(n3942), .A1(n3270), .B0(n3941), .Y(n3269) );
XNOR2X4TS U5892 ( .A(n3271), .B(n3941), .Y(n3939) );
XOR2X4TS U5893 ( .A(n3942), .B(n3272), .Y(n3271) );
OA21X4TS U5894 ( .A0(n3361), .A1(n4035), .B0(n3273), .Y(n3272) );
OR2X8TS U5895 ( .A(n4030), .B(n4184), .Y(n3273) );
AOI21X4TS U5896 ( .A0(n5978), .A1(n3304), .B0(n3485), .Y(n5981) );
OAI21X4TS U5897 ( .A0(n5840), .A1(n3277), .B0(n3275), .Y(n5521) );
AOI21X4TS U5898 ( .A0(n5403), .A1(n5402), .B0(n5401), .Y(n3281) );
INVX12TS U5899 ( .A(n3282), .Y(n5729) );
AND2X8TS U5900 ( .A(n2260), .B(n5591), .Y(n3282) );
NAND2BX4TS U5901 ( .AN(n3285), .B(n5406), .Y(n3284) );
BUFX20TS U5902 ( .A(n3096), .Y(n3290) );
NAND2X8TS U5903 ( .A(n3292), .B(n3291), .Y(n4077) );
OAI2BB1X4TS U5904 ( .A0N(n3287), .A1N(n3293), .B0(n4000), .Y(n3292) );
OAI22X4TS U5905 ( .A0(n4489), .A1(n2638), .B0(n2962), .B1(n2636), .Y(n4370)
);
AOI21X4TS U5906 ( .A0(n4438), .A1(n4439), .B0(n3296), .Y(n4514) );
XNOR2X4TS U5907 ( .A(n5849), .B(n5850), .Y(n3299) );
OAI2BB1X4TS U5908 ( .A0N(n5527), .A1N(n3303), .B0(n3301), .Y(n5623) );
OAI21X4TS U5909 ( .A0(n5527), .A1(n3303), .B0(n5526), .Y(n3301) );
XOR2X4TS U5910 ( .A(n3302), .B(n5526), .Y(n5535) );
XOR2X4TS U5911 ( .A(n5527), .B(n3303), .Y(n3302) );
XNOR2X4TS U5912 ( .A(n5588), .B(n5450), .Y(n3306) );
XOR2X4TS U5913 ( .A(n3307), .B(n5418), .Y(n5423) );
NAND2X2TS U5914 ( .A(n6088), .B(n3309), .Y(n5679) );
AND2X8TS U5915 ( .A(n3412), .B(n2678), .Y(n3310) );
XOR2X4TS U5916 ( .A(DP_OP_497J248_123_1725_n690), .B(
DP_OP_497J248_123_1725_n705), .Y(n4573) );
OAI2BB1X4TS U5917 ( .A0N(n5673), .A1N(n5671), .B0(n3311), .Y(n5684) );
OAI21X4TS U5918 ( .A0(n5671), .A1(n5673), .B0(n5672), .Y(n3311) );
INVX6TS U5919 ( .A(n8236), .Y(n6057) );
ADDFHX4TS U5920 ( .A(n5594), .B(n5586), .CI(n5585), .CO(n5603), .S(n5601) );
OAI21X4TS U5921 ( .A0(n5461), .A1(n5397), .B0(n5398), .Y(n5350) );
XNOR2X4TS U5922 ( .A(n2993), .B(n5732), .Y(n5712) );
XOR2X4TS U5923 ( .A(n4851), .B(n4850), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
OAI22X4TS U5924 ( .A0(n5419), .A1(n2903), .B0(n5566), .B1(n5354), .Y(n5424)
);
XNOR2X4TS U5925 ( .A(n2580), .B(n2972), .Y(n5562) );
XNOR2X4TS U5926 ( .A(n3316), .B(n3315), .Y(n3439) );
XNOR2X4TS U5927 ( .A(n3091), .B(n5800), .Y(n3313) );
OAI2BB1X4TS U5928 ( .A0N(n5311), .A1N(n5310), .B0(n3322), .Y(n5387) );
XOR2X4TS U5929 ( .A(n5309), .B(n3324), .Y(n5291) );
XOR2X4TS U5930 ( .A(n5311), .B(n5310), .Y(n3324) );
XOR2X4TS U5931 ( .A(n5238), .B(n3326), .Y(n5239) );
XNOR2X4TS U5932 ( .A(n5240), .B(n5451), .Y(n5236) );
XNOR2X4TS U5933 ( .A(n4876), .B(DP_OP_496J248_122_3540_n1207), .Y(n3325) );
XOR2X4TS U5934 ( .A(n3328), .B(n5179), .Y(n3327) );
XOR2X4TS U5935 ( .A(n5303), .B(n3106), .Y(n4874) );
XOR2X4TS U5936 ( .A(n3331), .B(n3333), .Y(n4883) );
INVX12TS U5937 ( .A(n5451), .Y(n3333) );
XNOR2X4TS U5938 ( .A(n3331), .B(n5452), .Y(n4894) );
XOR2X4TS U5939 ( .A(n3331), .B(n3334), .Y(n5437) );
XOR2X4TS U5940 ( .A(n5640), .B(n5596), .Y(n5457) );
NAND2BX4TS U5941 ( .AN(n2619), .B(n3337), .Y(n4923) );
XOR2X4TS U5942 ( .A(n3338), .B(n6082), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[22]) );
OAI2BB1X4TS U5943 ( .A0N(n2581), .A1N(n3345), .B0(n3880), .Y(n3344) );
AND2X8TS U5944 ( .A(n3346), .B(DP_OP_498J248_124_1725_n394), .Y(n3339) );
XNOR2X4TS U5945 ( .A(DP_OP_498J248_124_1725_n785), .B(
DP_OP_498J248_124_1725_n791), .Y(n3340) );
XNOR2X4TS U5946 ( .A(n3356), .B(DP_OP_498J248_124_1725_n616), .Y(n4002) );
NAND2X8TS U5947 ( .A(n2771), .B(n4293), .Y(n3448) );
NOR2X8TS U5948 ( .A(DP_OP_498J248_124_1725_n640), .B(
DP_OP_498J248_124_1725_n638), .Y(n3358) );
NOR2X8TS U5949 ( .A(n3360), .B(n3934), .Y(n4124) );
OAI22X1TS U5950 ( .A0(n4205), .A1(n3964), .B0(n2650), .B1(n3361), .Y(n3908)
);
NAND2X1TS U5951 ( .A(n3362), .B(n5979), .Y(n5980) );
INVX8TS U5952 ( .A(n3484), .Y(n3362) );
NOR2X8TS U5953 ( .A(n3127), .B(DP_OP_496J248_122_3540_n1098), .Y(n5402) );
XNOR2X4TS U5954 ( .A(n3368), .B(n3366), .Y(n3365) );
NAND2BX4TS U5955 ( .AN(n3367), .B(n4086), .Y(n3366) );
OAI21X4TS U5956 ( .A0(n4903), .A1(n4901), .B0(n4902), .Y(n3368) );
OAI22X4TS U5957 ( .A0(n5729), .A1(n3334), .B0(n2389), .B1(n2819), .Y(n5641)
);
NOR2X8TS U5958 ( .A(n5540), .B(n5539), .Y(n5819) );
AND2X8TS U5959 ( .A(n2654), .B(n8847), .Y(n3892) );
INVX16TS U5960 ( .A(n3374), .Y(n5721) );
OAI22X4TS U5961 ( .A0(n5417), .A1(n5721), .B0(n2331), .B1(n5489), .Y(n5516)
);
XNOR2X4TS U5962 ( .A(n5583), .B(n5655), .Y(n5489) );
XOR2X4TS U5963 ( .A(n5427), .B(n5426), .Y(n3373) );
AND2X8TS U5964 ( .A(n5720), .B(n5376), .Y(n3374) );
XNOR2X4TS U5965 ( .A(n5334), .B(n5333), .Y(n3372) );
XOR2X4TS U5966 ( .A(n3376), .B(n4676), .Y(n4650) );
XOR2X4TS U5967 ( .A(n4678), .B(n4677), .Y(n3376) );
XOR2X4TS U5968 ( .A(n3380), .B(n3519), .Y(n3377) );
NAND2BX4TS U5969 ( .AN(n2652), .B(n4351), .Y(n3380) );
NOR2X8TS U5970 ( .A(n3483), .B(n3137), .Y(n5131) );
AND2X8TS U5971 ( .A(DP_OP_499J248_125_1651_n273), .B(n3382), .Y(n6419) );
XOR2X4TS U5972 ( .A(n5374), .B(n9643), .Y(n5379) );
NOR2X8TS U5973 ( .A(n6242), .B(n6003), .Y(n3385) );
NAND2X8TS U5974 ( .A(n3209), .B(n2328), .Y(n3442) );
NAND2BX4TS U5975 ( .AN(n9374), .B(DP_OP_496J248_122_3540_n1467), .Y(n5265)
);
NAND2X8TS U5976 ( .A(n6015), .B(n3395), .Y(n3394) );
NOR2X8TS U5977 ( .A(n3398), .B(n3397), .Y(n3396) );
XOR2X4TS U5978 ( .A(n3400), .B(DP_OP_496J248_122_3540_n1376), .Y(n3399) );
XOR2X4TS U5979 ( .A(n3948), .B(n3949), .Y(n3552) );
OR2X8TS U5980 ( .A(n6375), .B(n6371), .Y(n3403) );
OR2X8TS U5981 ( .A(n4093), .B(n4092), .Y(n5857) );
OAI21X4TS U5982 ( .A0(n4918), .A1(n4915), .B0(n4916), .Y(n4083) );
OAI2BB1X4TS U5983 ( .A0N(n4533), .A1N(n3408), .B0(n3406), .Y(n4593) );
NAND4X4TS U5984 ( .A(n3413), .B(n2426), .C(n3414), .D(n3409), .Y(n3412) );
NAND2X4TS U5985 ( .A(n3411), .B(n3454), .Y(n3410) );
AND2X2TS U5986 ( .A(n2669), .B(n5801), .Y(n3411) );
INVX16TS U5987 ( .A(n3417), .Y(n4524) );
XOR2X4TS U5988 ( .A(n5829), .B(n5828), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[8]) );
AND2X8TS U5989 ( .A(n3418), .B(n5180), .Y(n5828) );
XOR2X4TS U5990 ( .A(n5096), .B(n5097), .Y(n3542) );
OAI2BB1X4TS U5991 ( .A0N(n3905), .A1N(n3904), .B0(n3425), .Y(n3977) );
OAI21X4TS U5992 ( .A0(n3904), .A1(n3905), .B0(n3903), .Y(n3425) );
XOR2X4TS U5993 ( .A(n3903), .B(n3905), .Y(n3426) );
AND2X8TS U5994 ( .A(n3452), .B(n3447), .Y(add_x_69_n285) );
XOR2X4TS U5995 ( .A(n2767), .B(n3453), .Y(n3452) );
OAI21X4TS U5996 ( .A0(n3431), .A1(n3432), .B0(n5439), .Y(n3434) );
XOR2X4TS U5997 ( .A(n5439), .B(n3435), .Y(n6322) );
XOR2X4TS U5998 ( .A(n5560), .B(n5215), .Y(n5415) );
AOI21X4TS U5999 ( .A0(n5401), .A1(n5405), .B0(n5404), .Y(n3437) );
NAND3BX4TS U6000 ( .AN(n3285), .B(n5403), .C(n5402), .Y(n3438) );
OAI22X4TS U6001 ( .A0(n5571), .A1(n5721), .B0(n2331), .B1(n5656), .Y(n5662)
);
XNOR2X4TS U6002 ( .A(n5750), .B(n2972), .Y(n5656) );
XOR2X4TS U6003 ( .A(n4317), .B(n2685), .Y(n5961) );
OAI22X2TS U6004 ( .A0(n3391), .A1(n4031), .B0(n3113), .B1(n3989), .Y(n4047)
);
OAI21X4TS U6005 ( .A0(n4078), .A1(n4081), .B0(n4079), .Y(n4117) );
NAND2X4TS U6006 ( .A(n5156), .B(n3455), .Y(n5177) );
XOR2X4TS U6007 ( .A(n3457), .B(n8915), .Y(n3456) );
NOR2X8TS U6008 ( .A(n3458), .B(n2601), .Y(n4430) );
OAI22X4TS U6009 ( .A0(n4672), .A1(DP_OP_497J248_123_1725_n312), .B0(n2795),
.B1(n3458), .Y(n4658) );
XOR2X4TS U6010 ( .A(n3465), .B(n8106), .Y(n9748) );
NAND2X8TS U6011 ( .A(n3467), .B(n2230), .Y(n5906) );
OAI22X4TS U6012 ( .A0(n3477), .A1(n3473), .B0(n3472), .B1(n3471), .Y(n4655)
);
OAI22X4TS U6013 ( .A0(n2795), .A1(n5072), .B0(n4672), .B1(n5055), .Y(n3475)
);
INVX6TS U6014 ( .A(n4310), .Y(n4045) );
NAND2BX4TS U6015 ( .AN(n4295), .B(n4294), .Y(n3479) );
OAI2BB1X4TS U6016 ( .A0N(n6332), .A1N(n5582), .B0(n3486), .Y(n5638) );
INVX12TS U6017 ( .A(n3499), .Y(n5640) );
OAI21X4TS U6018 ( .A0(n3383), .A1(n5378), .B0(n5377), .Y(n3489) );
OAI2BB1X4TS U6019 ( .A0N(n3493), .A1N(n3491), .B0(n5448), .Y(n3494) );
XNOR2X4TS U6020 ( .A(n3497), .B(n5915), .Y(n5957) );
AOI21X4TS U6021 ( .A0(n5882), .A1(n3571), .B0(n3496), .Y(n5900) );
OAI22X4TS U6022 ( .A0(n5230), .A1(n5414), .B0(n5320), .B1(n5413), .Y(n6214)
);
XOR2X4TS U6023 ( .A(n5558), .B(n5215), .Y(n5320) );
NAND2X8TS U6024 ( .A(n5413), .B(n5219), .Y(n5414) );
XOR2X4TS U6025 ( .A(n5509), .B(n5215), .Y(n5230) );
OAI21X4TS U6026 ( .A0(n5844), .A1(n5845), .B0(n5843), .Y(n5872) );
OAI22X4TS U6027 ( .A0(n5438), .A1(n5454), .B0(n5453), .B1(n5455), .Y(n5465)
);
XNOR2X4TS U6028 ( .A(n5640), .B(n5450), .Y(n5438) );
XOR2X4TS U6029 ( .A(n4896), .B(n4895), .Y(n3499) );
OAI22X4TS U6030 ( .A0(n3500), .A1(n5211), .B0(n5473), .B1(n5606), .Y(n5548)
);
OAI22X4TS U6031 ( .A0(n5474), .A1(n5211), .B0(n5473), .B1(n3500), .Y(n5520)
);
OAI21X4TS U6032 ( .A0(n5134), .A1(n5117), .B0(n5116), .Y(n3512) );
OAI22X4TS U6033 ( .A0(n5746), .A1(n5476), .B0(n5569), .B1(n3493), .Y(n5564)
);
XOR2X4TS U6034 ( .A(n5762), .B(n5583), .Y(n5569) );
OAI21X4TS U6035 ( .A0(n3519), .A1(n4548), .B0(DP_OP_497J248_123_1725_n374),
.Y(n3520) );
OAI22X4TS U6036 ( .A0(n4597), .A1(n5055), .B0(n4489), .B1(n5072), .Y(n4543)
);
NAND2X8TS U6037 ( .A(n6208), .B(n6206), .Y(n3531) );
XNOR2X4TS U6038 ( .A(n3525), .B(n4514), .Y(n4436) );
NAND2BX4TS U6039 ( .AN(n4455), .B(n3524), .Y(n3523) );
XNOR2X4TS U6040 ( .A(n4527), .B(n3527), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[11]) );
NAND2X8TS U6041 ( .A(n3538), .B(n4479), .Y(n3527) );
AOI21X4TS U6042 ( .A0(n4526), .A1(n4480), .B0(n3530), .Y(n3529) );
XNOR2X4TS U6043 ( .A(n3531), .B(n6209), .Y(
FPMULT_Sgf_operation_EVEN1_S_B[11]) );
XOR2X4TS U6044 ( .A(n3537), .B(n4391), .Y(n4395) );
XNOR2X4TS U6045 ( .A(n4446), .B(n3540), .Y(n4473) );
OAI21X4TS U6046 ( .A0(n4524), .A1(n4451), .B0(n4452), .Y(n3540) );
NOR2X8TS U6047 ( .A(n2986), .B(DP_OP_497J248_123_1725_n638), .Y(n4856) );
XOR2X4TS U6048 ( .A(n3542), .B(n5095), .Y(n5089) );
AND2X8TS U6049 ( .A(n3543), .B(n5206), .Y(n3629) );
NAND2X8TS U6050 ( .A(n5633), .B(n5632), .Y(n5977) );
OAI2BB1X4TS U6051 ( .A0N(n5948), .A1N(n5947), .B0(n5699), .Y(n3545) );
NAND2X8TS U6052 ( .A(n5302), .B(n3312), .Y(n3547) );
OAI2BB1X4TS U6053 ( .A0N(n3556), .A1N(n3555), .B0(n3993), .Y(n3554) );
XOR2X4TS U6054 ( .A(n3561), .B(n3558), .Y(n3557) );
NAND2X8TS U6055 ( .A(n3560), .B(n3559), .Y(n3558) );
NAND2X8TS U6056 ( .A(n3563), .B(n3562), .Y(n3561) );
NAND2BX4TS U6057 ( .AN(n4206), .B(n3867), .Y(n3563) );
INVX12TS U6058 ( .A(n4158), .Y(n3565) );
NOR2X2TS U6059 ( .A(n6225), .B(n6223), .Y(n5962) );
OAI21X4TS U6060 ( .A0(n4929), .A1(n4932), .B0(n4930), .Y(n4924) );
AOI21X4TS U6061 ( .A0(n4942), .A1(n4946), .B0(n4882), .Y(n4932) );
ADDFHX4TS U6062 ( .A(n8969), .B(n8970), .CI(n8971), .CO(n3743), .S(n3741) );
ADDFHX4TS U6063 ( .A(n4936), .B(n4935), .CI(n4934), .CO(n4928), .S(n4953) );
ADDFHX4TS U6064 ( .A(n8955), .B(n8956), .CI(n8957), .CO(n4714), .S(n3834) );
ADDFHX4TS U6065 ( .A(n5929), .B(n5927), .CI(n5928), .CO(n5955), .S(n5912) );
ADDFHX4TS U6066 ( .A(n5896), .B(n5895), .CI(n5894), .CO(n5928), .S(n5886) );
XOR2X4TS U6067 ( .A(n4933), .B(n4932), .Y(n4954) );
NAND2X2TS U6068 ( .A(n4931), .B(n4930), .Y(n4933) );
NAND2X4TS U6069 ( .A(n4899), .B(n5843), .Y(n4900) );
ADDFX2TS U6070 ( .A(n7879), .B(n7878), .CI(n7877), .CO(n7895), .S(n8135) );
OR3X6TS U6071 ( .A(n1519), .B(n1518), .C(n1517), .Y(n6435) );
AOI2BB2X2TS U6072 ( .B0(n8083), .B1(n8248), .A0N(n2915), .A1N(n9254), .Y(
n8063) );
INVX4TS U6073 ( .A(add_x_69_n302), .Y(add_x_69_n301) );
OR2X4TS U6074 ( .A(n6364), .B(DP_OP_496J248_122_3540_n36), .Y(n9038) );
OAI2BB1X4TS U6075 ( .A0N(n2546), .A1N(n6150), .B0(n9744), .Y(n8248) );
XOR2X4TS U6076 ( .A(n4718), .B(n9007), .Y(n4724) );
ADDFHX2TS U6077 ( .A(n8938), .B(n3681), .CI(n8977), .CO(n4723), .S(n4715) );
ADDFHX4TS U6078 ( .A(n5580), .B(n5579), .CI(n5578), .CO(n6335), .S(n6333) );
AOI2BB2X2TS U6079 ( .B0(n7759), .B1(n1580), .A0N(n2916), .A1N(n9107), .Y(
n4995) );
NAND2X4TS U6080 ( .A(n5866), .B(n5865), .Y(n6315) );
OR2X6TS U6081 ( .A(n5866), .B(n5865), .Y(n6316) );
NAND2X2TS U6082 ( .A(n6189), .B(n6185), .Y(n6192) );
NOR2X8TS U6083 ( .A(n5811), .B(n5810), .Y(n6370) );
OR2X8TS U6084 ( .A(FPMULT_FSM_selector_B[1]), .B(n9213), .Y(n6429) );
OR2X8TS U6085 ( .A(n3741), .B(n2486), .Y(n3747) );
ADDFHX4TS U6086 ( .A(n8941), .B(n8942), .CI(n3795), .CO(n3796), .S(n3781) );
NAND3X4TS U6087 ( .A(n3779), .B(n8968), .C(n3778), .Y(n3795) );
AOI2BB2X2TS U6088 ( .B0(n6190), .B1(n4771), .A0N(n6186), .A1N(n4770), .Y(
n4772) );
NOR2X4TS U6089 ( .A(n6187), .B(n6186), .Y(n6188) );
NOR2X4TS U6090 ( .A(n6186), .B(n6022), .Y(n6023) );
ADDFHX4TS U6091 ( .A(n5479), .B(n5478), .CI(n5477), .CO(n5873), .S(n5861) );
NOR2X8TS U6092 ( .A(n4968), .B(n4976), .Y(n3763) );
AOI21X4TS U6093 ( .A0(n6359), .A1(n6358), .B0(n6216), .Y(n6321) );
OAI21X2TS U6094 ( .A0(n6237), .A1(n6240), .B0(n6238), .Y(n6359) );
OAI21X2TS U6095 ( .A0(n2940), .A1(n6114), .B0(n6113), .Y(n6115) );
NOR2X8TS U6096 ( .A(n6754), .B(FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n6920) );
OAI21X2TS U6097 ( .A0(n6399), .A1(n6396), .B0(n6400), .Y(n6388) );
NAND3X2TS U6098 ( .A(n8088), .B(n9750), .C(n9843), .Y(n1551) );
NAND2X2TS U6099 ( .A(n8087), .B(FPMULT_FSM_selector_B[0]), .Y(n8088) );
OAI21X2TS U6100 ( .A0(n6398), .A1(n6390), .B0(n6389), .Y(n6395) );
NAND2X2TS U6101 ( .A(n6309), .B(n6308), .Y(n6311) );
OAI22X4TS U6102 ( .A0(n5454), .A1(n4881), .B0(n4879), .B1(n5453), .Y(n4942)
);
ADDFHX2TS U6103 ( .A(n8947), .B(n8948), .CI(n8949), .CO(n4716), .S(n4712) );
ADDFHX4TS U6104 ( .A(n5600), .B(n5601), .CI(n5599), .CO(n5908), .S(n5874) );
NOR2X8TS U6105 ( .A(n4793), .B(n3607), .Y(n6786) );
XNOR2X4TS U6106 ( .A(n2255), .B(n6055), .Y(n6160) );
NAND2X2TS U6107 ( .A(n6052), .B(n6053), .Y(n6055) );
NAND2X4TS U6108 ( .A(n5984), .B(n2479), .Y(n5985) );
AOI21X2TS U6109 ( .A0(n6204), .A1(n6203), .B0(n8303), .Y(n1694) );
ADDFHX4TS U6110 ( .A(DP_OP_498J248_124_1725_n631), .B(n3891), .CI(n3892),
.CO(n3973), .S(n3862) );
INVX4TS U6111 ( .A(n3791), .Y(n3782) );
XOR2X4TS U6112 ( .A(n6345), .B(n6344), .Y(n3678) );
AOI21X2TS U6113 ( .A0(n6703), .A1(n3737), .B0(n3736), .Y(n3738) );
NOR2X8TS U6114 ( .A(n3802), .B(n3803), .Y(n3809) );
NAND2BX4TS U6115 ( .AN(n7735), .B(n7733), .Y(n9866) );
NOR2X2TS U6116 ( .A(n5242), .B(n5241), .Y(n5244) );
OAI21X2TS U6117 ( .A0(n6727), .A1(n4975), .B0(n4974), .Y(n4980) );
NAND2X6TS U6118 ( .A(n4436), .B(n4435), .Y(n4479) );
AOI2BB2X2TS U6119 ( .B0(n7759), .B1(n1579), .A0N(n2914), .A1N(n9105), .Y(
n5010) );
OR2X8TS U6120 ( .A(n3752), .B(n3753), .Y(n3772) );
AOI21X2TS U6121 ( .A0(n6121), .A1(n6190), .B0(n6120), .Y(n6122) );
NOR3X4TS U6122 ( .A(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(
n6755) );
AOI2BB2X4TS U6123 ( .B0(n2793), .B1(n4780), .A0N(n6186), .A1N(n6021), .Y(
n4781) );
ADDFHX4TS U6124 ( .A(n5492), .B(n5491), .CI(n5490), .CO(n5860), .S(n5840) );
NAND2X4TS U6125 ( .A(n5326), .B(n2619), .Y(n4922) );
AOI21X4TS U6126 ( .A0(n3568), .A1(n5830), .B0(n4476), .Y(n4477) );
XNOR2X4TS U6127 ( .A(n6009), .B(n6008), .Y(n6010) );
OAI22X2TS U6128 ( .A0(n5721), .A1(n5382), .B0(n2331), .B1(n5417), .Y(n5395)
);
OAI22X4TS U6129 ( .A0(n5598), .A1(n5596), .B0(n2900), .B1(n4878), .Y(n5271)
);
OAI2BB1X4TS U6130 ( .A0N(n7736), .A1N(n7735), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n7740) );
ADDFHX4TS U6131 ( .A(n5431), .B(n5432), .CI(n5433), .CO(n5841), .S(n5352) );
ADDFHX2TS U6132 ( .A(n5993), .B(n5992), .CI(n2327), .CO(
DP_OP_499J248_125_1651_n223), .S(DP_OP_499J248_125_1651_n224) );
XOR2X4TS U6133 ( .A(n6105), .B(n9045), .Y(n6106) );
AO21X4TS U6134 ( .A0(n4735), .A1(n4734), .B0(n4733), .Y(n4736) );
OAI2BB1X4TS U6135 ( .A0N(n2546), .A1N(n6168), .B0(n9735), .Y(n8246) );
NAND2X4TS U6136 ( .A(n6045), .B(n6044), .Y(n6047) );
ADDFHX4TS U6137 ( .A(n6303), .B(n6302), .CI(n6301), .CO(n6304), .S(n6158) );
NAND2X4TS U6138 ( .A(n4762), .B(n2484), .Y(n7753) );
XNOR2X4TS U6139 ( .A(n6297), .B(n6072), .Y(n6303) );
NAND2X4TS U6140 ( .A(n3532), .B(n3000), .Y(n4111) );
INVX6TS U6141 ( .A(n4966), .Y(n6727) );
AOI21X4TS U6142 ( .A0(n5025), .A1(n3757), .B0(n3756), .Y(n4970) );
OAI21X2TS U6143 ( .A0(n6728), .A1(n6725), .B0(n6729), .Y(n5025) );
ADDFHX4TS U6144 ( .A(n5625), .B(n5624), .CI(n5623), .CO(n5629), .S(n5626) );
NOR2X4TS U6145 ( .A(n7742), .B(n7745), .Y(n7748) );
AOI21X4TS U6146 ( .A0(n6327), .A1(n6361), .B0(n6326), .Y(n6398) );
XOR2X4TS U6147 ( .A(n3777), .B(n3776), .Y(n3816) );
NAND2X2TS U6148 ( .A(n3775), .B(n3790), .Y(n3776) );
NOR2X2TS U6149 ( .A(n3791), .B(n3785), .Y(n3794) );
NOR2X6TS U6150 ( .A(n3781), .B(n3780), .Y(n3791) );
NAND2X4TS U6151 ( .A(n5797), .B(n5990), .Y(n6083) );
OAI21X2TS U6152 ( .A0(n4976), .A1(n4989), .B0(n4977), .Y(n3762) );
ADDFHX2TS U6153 ( .A(n2846), .B(n6433), .CI(n6432), .CO(
DP_OP_234J248_129_4955_n1), .S(FPMULT_Exp_module_Data_S_8_) );
ADDFHX2TS U6154 ( .A(n6690), .B(n2846), .CI(n6689), .CO(n6650), .S(n7892) );
OAI21X4TS U6155 ( .A0(n8099), .A1(n5788), .B0(n5787), .Y(add_x_69_n302) );
ADDFHX4TS U6156 ( .A(n5942), .B(n5940), .CI(n5941), .CO(n6074), .S(n5956) );
XNOR2X4TS U6157 ( .A(n2580), .B(n2242), .Y(n5483) );
XOR2X4TS U6158 ( .A(n6115), .B(n9042), .Y(n6116) );
ADDFHX2TS U6159 ( .A(n4257), .B(n4256), .CI(n4255), .CO(n4273), .S(n4259) );
ADDFHX4TS U6160 ( .A(n4209), .B(n4208), .CI(n4207), .CO(n4255), .S(n4204) );
NOR2X8TS U6161 ( .A(n4704), .B(n4700), .Y(n4707) );
NOR2X8TS U6162 ( .A(n3836), .B(n3835), .Y(n4704) );
NOR2X8TS U6163 ( .A(n3761), .B(n2507), .Y(n4976) );
XOR2X4TS U6164 ( .A(n4711), .B(n9009), .Y(n4717) );
AOI21X2TS U6165 ( .A0(n2436), .A1(n9015), .B0(n9016), .Y(n4711) );
XOR2X4TS U6166 ( .A(n6027), .B(n9056), .Y(n6028) );
NAND2X4TS U6167 ( .A(n5288), .B(n5287), .Y(n5881) );
ADDFHX4TS U6168 ( .A(n4166), .B(n4165), .CI(n4164), .CO(n4224), .S(n4193) );
INVX4TS U6169 ( .A(n4098), .Y(n4165) );
ADDFHX4TS U6170 ( .A(n3923), .B(n3922), .CI(n3921), .CO(n3916), .S(n3928) );
XOR2X4TS U6171 ( .A(n6149), .B(n6148), .Y(n6150) );
ADDFHX2TS U6172 ( .A(n4172), .B(n4171), .CI(n4170), .CO(n4222), .S(n4191) );
ADDFHX2TS U6173 ( .A(n4272), .B(n4271), .CI(n4270), .CO(n4300), .S(n4274) );
NAND2X4TS U6174 ( .A(n4880), .B(n5454), .Y(n5205) );
NAND2X4TS U6175 ( .A(n5978), .B(n5977), .Y(n5815) );
XOR2X4TS U6176 ( .A(n6131), .B(n9043), .Y(n6132) );
AOI21X2TS U6177 ( .A0(n5945), .A1(n5946), .B0(n5944), .Y(n5951) );
ADDHX4TS U6178 ( .A(DP_OP_497J248_123_1725_n686), .B(n2261), .CO(n4574), .S(
n4539) );
ADDFHX4TS U6179 ( .A(n5283), .B(n5282), .CI(n5281), .CO(n5277), .S(n5287) );
ADDFHX4TS U6180 ( .A(n5519), .B(n5518), .CI(n5517), .CO(n6330), .S(n6329) );
ADDFHX4TS U6181 ( .A(n5342), .B(n5341), .CI(n5340), .CO(n5443), .S(n5386) );
ADDFHX4TS U6182 ( .A(n5324), .B(n5323), .CI(n5322), .CO(n5341), .S(n5336) );
OAI22X4TS U6183 ( .A0(n5454), .A1(n2906), .B0(n4881), .B1(n5453), .Y(n5204)
);
XOR2X4TS U6184 ( .A(n4919), .B(n4918), .Y(n8636) );
ADDFHX4TS U6185 ( .A(n5067), .B(n5066), .CI(n5065), .CO(n5090), .S(n5078) );
NAND2X4TS U6186 ( .A(n8118), .B(n8115), .Y(n6756) );
NOR2X4TS U6187 ( .A(n4789), .B(n4788), .Y(n8118) );
NOR2X4TS U6188 ( .A(n6708), .B(n6710), .Y(n3737) );
NOR2X4TS U6189 ( .A(n9050), .B(n2482), .Y(n6710) );
XNOR2X4TS U6190 ( .A(n3749), .B(n3751), .Y(n3760) );
XOR2X4TS U6191 ( .A(n6096), .B(n2428), .Y(n6097) );
OAI22X4TS U6192 ( .A0(n5704), .A1(n5702), .B0(n4898), .B1(n2832), .Y(n5355)
);
OAI22X2TS U6193 ( .A0(n5704), .A1(n5639), .B0(n5702), .B1(n2832), .Y(n5695)
);
OAI22X2TS U6194 ( .A0(n5704), .A1(n5467), .B0(n2933), .B1(n2832), .Y(n5600)
);
AO21X4TS U6195 ( .A0(n5704), .A1(n2832), .B0(n5702), .Y(n5724) );
OAI22X4TS U6196 ( .A0(n5704), .A1(n4893), .B0(n5436), .B1(n2832), .Y(n5432)
);
ADDFHX4TS U6197 ( .A(n5385), .B(n5384), .CI(n5383), .CO(n6323), .S(n6211) );
ADDFHX4TS U6198 ( .A(n5932), .B(n5931), .CI(n5930), .CO(n5933), .S(n5913) );
ADDFHX4TS U6199 ( .A(n5610), .B(n5609), .CI(n5608), .CO(n5663), .S(n5619) );
ADDFHX4TS U6200 ( .A(n5269), .B(n5268), .CI(n2330), .CO(n5310), .S(n5275) );
AOI2BB2X2TS U6201 ( .B0(n8083), .B1(n8242), .A0N(n2915), .A1N(n6098), .Y(
n6108) );
INVX4TS U6202 ( .A(n4399), .Y(n4857) );
NOR2X2TS U6203 ( .A(n5201), .B(DP_OP_496J248_122_3540_n451), .Y(n5202) );
OAI21X2TS U6204 ( .A0(n2940), .A1(n6123), .B0(n6122), .Y(n6124) );
XNOR2X4TS U6205 ( .A(n4332), .B(n4331), .Y(n5960) );
NOR2X4TS U6206 ( .A(n5510), .B(n5652), .Y(n5557) );
OAI21X4TS U6207 ( .A0(n4866), .A1(n4864), .B0(n4865), .Y(n4460) );
ADDFHX4TS U6208 ( .A(n3920), .B(n3919), .CI(n3918), .CO(n3911), .S(n3929) );
NAND2BX4TS U6209 ( .AN(DP_OP_496J248_122_3540_n1464), .B(n8987), .Y(n5405)
);
XNOR2X4TS U6210 ( .A(n4134), .B(n4133), .Y(n4135) );
OAI21X2TS U6211 ( .A0(n4151), .A1(n4128), .B0(n4127), .Y(n4134) );
ADDFHX4TS U6212 ( .A(n5421), .B(n5422), .CI(n5420), .CO(n5524), .S(n5442) );
ADDFHX4TS U6213 ( .A(n5425), .B(n5424), .CI(n5423), .CO(n5482), .S(n5420) );
AOI21X4TS U6214 ( .A0(n7287), .A1(n3823), .B0(n3822), .Y(n4767) );
INVX4TS U6215 ( .A(n3819), .Y(n7287) );
ADDFHX2TS U6216 ( .A(n4038), .B(n4037), .CI(n4036), .CO(n4170), .S(n4043) );
ADDFHX4TS U6217 ( .A(n5903), .B(n5904), .CI(n5902), .CO(n5931), .S(n5887) );
OAI22X4TS U6218 ( .A0(n5729), .A1(n3333), .B0(n2818), .B1(n5589), .Y(n5585)
);
ADDFHX4TS U6219 ( .A(n5039), .B(n5038), .CI(n5037), .CO(n5064), .S(n5061) );
ADDFHX4TS U6220 ( .A(DP_OP_497J248_123_1725_n623), .B(n4387), .CI(n4388),
.CO(n4407), .S(n4396) );
ADDFHX4TS U6221 ( .A(n5638), .B(n5636), .CI(n5637), .CO(n5807), .S(n5674) );
XOR2X4TS U6222 ( .A(DP_OP_496J248_122_3540_n1117), .B(
DP_OP_496J248_122_3540_n1064), .Y(n5183) );
NAND2X4TS U6223 ( .A(n2985), .B(n3290), .Y(n4085) );
OAI21X4TS U6224 ( .A0(n5001), .A1(n5014), .B0(n5002), .Y(n4971) );
XNOR2X4TS U6225 ( .A(n2993), .B(n2972), .Y(n5571) );
XNOR2X4TS U6226 ( .A(n2960), .B(n5559), .Y(n5409) );
ADDFHX4TS U6227 ( .A(n4431), .B(n4430), .CI(n4429), .CO(n5049), .S(n4663) );
NOR2X4TS U6228 ( .A(n2425), .B(DP_OP_498J248_124_1725_n728), .Y(n4181) );
ADDFHX4TS U6229 ( .A(n4580), .B(n4581), .CI(n4579), .CO(n4635), .S(n4586) );
ADDFHX4TS U6230 ( .A(n4561), .B(n4560), .CI(n4559), .CO(n4585), .S(n4563) );
ADDFHX4TS U6231 ( .A(n4487), .B(n4486), .CI(n4485), .CO(n4561), .S(n4507) );
ADDFHX4TS U6232 ( .A(n5692), .B(n5691), .CI(n5690), .CO(n5738), .S(n5685) );
ADDFHX4TS U6233 ( .A(n4049), .B(n4048), .CI(n4047), .CO(n4177), .S(n4040) );
OAI21X2TS U6234 ( .A0(n5859), .A1(n5868), .B0(n5870), .Y(n5864) );
ADDFHX4TS U6235 ( .A(n5048), .B(n5047), .CI(n5046), .CO(n5079), .S(n5042) );
ADDFHX4TS U6236 ( .A(n4532), .B(n4531), .CI(n4530), .CO(n4572), .S(n4510) );
ADDFHX4TS U6237 ( .A(n4509), .B(n4507), .CI(n4508), .CO(n4530), .S(n4360) );
NAND2X4TS U6238 ( .A(n4752), .B(n4751), .Y(n4753) );
ADDFHX4TS U6239 ( .A(n4724), .B(n4723), .CI(n4722), .CO(n4727), .S(n4751) );
ADDFHX4TS U6240 ( .A(n5522), .B(n5520), .CI(n5521), .CO(n5546), .S(n5526) );
ADDFHX4TS U6241 ( .A(n3915), .B(n3916), .CI(n3917), .CO(n3909), .S(n3930) );
ADDFHX4TS U6242 ( .A(n5480), .B(n5481), .CI(n5482), .CO(n5530), .S(n5523) );
ADDFHX4TS U6243 ( .A(n4612), .B(n4611), .CI(n4610), .CO(n4651), .S(n4637) );
OAI21X2TS U6244 ( .A0(n3791), .A1(n3790), .B0(n3789), .Y(n3792) );
NAND2X4TS U6245 ( .A(n3781), .B(n3780), .Y(n3789) );
ADDFHX4TS U6246 ( .A(DP_OP_497J248_123_1725_n693), .B(
DP_OP_497J248_123_1725_n683), .CI(n4659), .CO(n5051), .S(n4662) );
ADDFHX2TS U6247 ( .A(n8939), .B(n8978), .CI(n4725), .CO(n4738), .S(n4722) );
ADDFHX4TS U6248 ( .A(n4341), .B(n4340), .CI(n4339), .CO(n5107), .S(n4683) );
OAI22X4TS U6249 ( .A0(n5234), .A1(n5473), .B0(n5261), .B1(n5211), .Y(n5278)
);
OAI22X4TS U6250 ( .A0(n5308), .A1(n5473), .B0(n5234), .B1(n5211), .Y(n5323)
);
NAND2X4TS U6251 ( .A(n5414), .B(n5260), .Y(n5816) );
NAND2BX2TS U6252 ( .AN(n5412), .B(n5556), .Y(n5260) );
ADDFHX4TS U6253 ( .A(n4506), .B(n4504), .CI(n4505), .CO(n4531), .S(n4499) );
NOR2X4TS U6254 ( .A(n4997), .B(n5001), .Y(n4967) );
ADDFHX4TS U6255 ( .A(n4014), .B(n4013), .CI(n4012), .CO(n4019), .S(n4016) );
ADDFHX4TS U6256 ( .A(n4224), .B(n4223), .CI(n4222), .CO(n4243), .S(n4230) );
ADDFHX4TS U6257 ( .A(n4227), .B(n4226), .CI(n4225), .CO(n4242), .S(n4228) );
ADDFHX4TS U6258 ( .A(n4370), .B(n4369), .CI(n4368), .CO(n4362), .S(n4381) );
ADDFHX4TS U6259 ( .A(n4376), .B(n4375), .CI(n4374), .CO(n4369), .S(n4379) );
ADDFHX4TS U6260 ( .A(n3940), .B(n3939), .CI(n3938), .CO(n4017), .S(n3936) );
ADDFHX4TS U6261 ( .A(n5544), .B(n5543), .CI(n5542), .CO(n5622), .S(n5624) );
XOR2X4TS U6262 ( .A(n4863), .B(n4862), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[2]) );
NOR2X4TS U6263 ( .A(n6184), .B(n4770), .Y(n4771) );
XNOR2X4TS U6264 ( .A(n7714), .B(n7713), .Y(n7735) );
ADDFHX2TS U6265 ( .A(DP_OP_26J248_126_1325_n28), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .CI(n7731), .CO(n7714), .S(n7738) );
ADDFHX4TS U6266 ( .A(n5686), .B(n5685), .CI(n5684), .CO(n5803), .S(n5805) );
ADDFHX4TS U6267 ( .A(DP_OP_498J248_124_1725_n630), .B(n3951), .CI(n3583),
.CO(n3986), .S(n3972) );
XNOR2X4TS U6268 ( .A(n4434), .B(n4433), .Y(n4435) );
OAI21X2TS U6269 ( .A0(n4524), .A1(n4428), .B0(n4427), .Y(n4434) );
ADDFHX4TS U6270 ( .A(n5370), .B(n5369), .CI(n5368), .CO(n5392), .S(n5388) );
OAI22X2TS U6271 ( .A0(n2322), .A1(n3964), .B0(n3624), .B1(n2650), .Y(n3927)
);
NOR2X4TS U6272 ( .A(n3624), .B(n4254), .Y(n3970) );
ADDHX4TS U6273 ( .A(n3875), .B(n3874), .CO(n3969), .S(n3884) );
NOR2X8TS U6274 ( .A(n5757), .B(n5756), .Y(n6376) );
ADDFHX2TS U6275 ( .A(n2337), .B(n5642), .CI(n5641), .CO(n5693), .S(n5643) );
XNOR2X4TS U6276 ( .A(n4855), .B(n4854), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[3]) );
NAND2X4TS U6277 ( .A(n4853), .B(n4852), .Y(n4855) );
OAI21X4TS U6278 ( .A0(n4850), .A1(n4847), .B0(n4848), .Y(n4465) );
INVX4TS U6279 ( .A(n4460), .Y(n4850) );
INVX4TS U6280 ( .A(n5301), .Y(n5233) );
ADDFHX4TS U6281 ( .A(n5530), .B(n5529), .CI(n5528), .CO(n5627), .S(n5534) );
ADDFHX4TS U6282 ( .A(n6075), .B(n6074), .CI(n6073), .CO(n6178), .S(n5959) );
ADDFHX4TS U6283 ( .A(n6058), .B(n6057), .CI(n6056), .CO(n6159), .S(n6073) );
NAND2X4TS U6284 ( .A(n5131), .B(n5135), .Y(n5087) );
ADDFHX4TS U6285 ( .A(n5533), .B(n5532), .CI(n5531), .CO(n5537), .S(n5445) );
ADDFHX4TS U6286 ( .A(n5525), .B(n5524), .CI(n5523), .CO(n5536), .S(n5531) );
OR2X8TS U6287 ( .A(n4122), .B(n4121), .Y(n5891) );
ADDFHX4TS U6288 ( .A(n4596), .B(n4594), .CI(n4595), .CO(n4622), .S(n4592) );
ADDFHX4TS U6289 ( .A(n4628), .B(n4626), .CI(n4627), .CO(n4674), .S(n4620) );
NOR2X4TS U6290 ( .A(n5723), .B(n5761), .Y(n5751) );
ADDFHX4TS U6291 ( .A(n4260), .B(n4259), .CI(n4258), .CO(n4265), .S(n4244) );
ADDHX4TS U6292 ( .A(DP_OP_498J248_124_1725_n618), .B(
DP_OP_498J248_124_1725_n613), .CO(n3948), .S(n3863) );
NAND2X4TS U6293 ( .A(n3836), .B(n3835), .Y(n4702) );
INVX6TS U6294 ( .A(n5109), .Y(n4534) );
XOR2X4TS U6295 ( .A(n5926), .B(n5925), .Y(n5940) );
XNOR2X4TS U6296 ( .A(n2580), .B(n5463), .Y(n5351) );
ADDFHX4TS U6297 ( .A(n5628), .B(n5627), .CI(n5626), .CO(n5632), .S(n5540) );
ADDFHX2TS U6298 ( .A(n5736), .B(n5735), .CI(n5734), .CO(n5743), .S(n5715) );
ADDFHX4TS U6299 ( .A(n5278), .B(n5277), .CI(n5276), .CO(n5337), .S(n5289) );
ADDFHX4TS U6300 ( .A(n3976), .B(n3975), .CI(n3974), .CO(n4284), .S(n4281) );
NAND2X4TS U6301 ( .A(n5290), .B(n5289), .Y(n5898) );
XNOR2X4TS U6302 ( .A(n5646), .B(n5732), .Y(n5570) );
XNOR2X4TS U6303 ( .A(n5646), .B(n5353), .Y(n5419) );
XNOR2X4TS U6304 ( .A(n5646), .B(n5655), .Y(n5488) );
ADDFHX4TS U6305 ( .A(n8965), .B(n8966), .CI(n8967), .CO(n3753), .S(n3744) );
XNOR2X4TS U6306 ( .A(n5373), .B(n5330), .Y(n5334) );
ADDFHX4TS U6307 ( .A(n4055), .B(n4056), .CI(n4054), .CO(n4315), .S(n4310) );
XNOR2X4TS U6308 ( .A(n5237), .B(n5236), .Y(n5196) );
NAND2X6TS U6309 ( .A(n5195), .B(n5194), .Y(n5237) );
NAND2X4TS U6310 ( .A(n5378), .B(n3383), .Y(n5380) );
ADDFHX4TS U6311 ( .A(n4639), .B(n4638), .CI(n4637), .CO(n4640), .S(n4604) );
ADDFHX4TS U6312 ( .A(n4631), .B(n4630), .CI(n4629), .CO(n5160), .S(n5127) );
ADDFHX2TS U6313 ( .A(n5607), .B(n5606), .CI(n5605), .CO(n5669), .S(n5608) );
OAI22X2TS U6314 ( .A0(n5598), .A1(n4894), .B0(n5437), .B1(n2900), .Y(n5435)
);
XNOR2X4TS U6315 ( .A(n4945), .B(n4944), .Y(n5269) );
ADDFHX4TS U6316 ( .A(n4363), .B(n4362), .CI(n4364), .CO(n4498), .S(n4383) );
ADDFHX2TS U6317 ( .A(n5513), .B(n5556), .CI(n5512), .CO(n5550), .S(n5517) );
OAI21X2TS U6318 ( .A0(n6702), .A1(n3739), .B0(n3738), .Y(n4966) );
NAND2X2TS U6319 ( .A(n2480), .B(n3737), .Y(n3739) );
ADDFHX4TS U6320 ( .A(n3873), .B(n3872), .CI(n3871), .CO(n4072), .S(n4069) );
ADDFHX2TS U6321 ( .A(n5471), .B(n5470), .CI(n5469), .CO(n5599), .S(n5477) );
OAI22X2TS U6322 ( .A0(n5567), .A1(n5566), .B0(n2903), .B1(n5648), .Y(n5670)
);
AO21X4TS U6323 ( .A0(n5650), .A1(n2903), .B0(n5648), .Y(n5710) );
NAND2X6TS U6324 ( .A(n5649), .B(n5245), .Y(n5650) );
ADDFHX4TS U6325 ( .A(n4650), .B(n4651), .CI(n4649), .CO(n4679), .S(n4641) );
ADDFHX2TS U6326 ( .A(n4024), .B(n4023), .CI(n4022), .CO(n4187), .S(n4055) );
OAI21X2TS U6327 ( .A0(n3788), .A1(n3787), .B0(n3786), .Y(n3793) );
NAND2X4TS U6328 ( .A(n3772), .B(n3768), .Y(n3788) );
AOI21X4TS U6329 ( .A0(n4966), .A1(n3767), .B0(n3766), .Y(n4962) );
OAI22X4TS U6330 ( .A0(n5598), .A1(n4877), .B0(n2900), .B1(n4883), .Y(n4885)
);
ADDFHX4TS U6331 ( .A(n3861), .B(n3860), .CI(n3859), .CO(n4282), .S(n4233) );
ADDHX4TS U6332 ( .A(n3851), .B(n3850), .CO(n3861), .S(n4197) );
BUFX20TS U6333 ( .A(n5317), .Y(n5653) );
ADDFHX4TS U6334 ( .A(n8945), .B(n8946), .CI(n3810), .CO(n3812), .S(n3803) );
NOR2BX4TS U6335 ( .AN(n5357), .B(DP_OP_496J248_122_3540_n1468), .Y(n5314) );
CLKINVX12TS U6336 ( .A(FPMULT_Op_MY[10]), .Y(n5357) );
NAND2X2TS U6337 ( .A(n3928), .B(n3927), .Y(n4079) );
OR2X8TS U6338 ( .A(n4120), .B(n4119), .Y(n5889) );
XNOR2X4TS U6339 ( .A(n4118), .B(n4117), .Y(n4119) );
ADDFHX4TS U6340 ( .A(n5659), .B(n5658), .CI(n5657), .CO(n6341), .S(n6334) );
ADDHX4TS U6341 ( .A(DP_OP_497J248_123_1725_n795), .B(
DP_OP_497J248_123_1725_n687), .CO(n4488), .S(n4342) );
XNOR2X4TS U6342 ( .A(n5560), .B(n5559), .Y(n5574) );
XNOR2X4TS U6343 ( .A(n5750), .B(n5732), .Y(n5733) );
ADDHX4TS U6344 ( .A(n8857), .B(n3855), .CO(n3864), .S(n4070) );
XNOR2X4TS U6345 ( .A(n5462), .B(n5732), .Y(n5747) );
OAI21X2TS U6346 ( .A0(n2329), .A1(n7503), .B0(n7502), .Y(n7506) );
XNOR2X4TS U6347 ( .A(n7756), .B(n7755), .Y(n7757) );
OAI21X2TS U6348 ( .A0(n2329), .A1(n7751), .B0(n7750), .Y(n7756) );
ADDFHX4TS U6349 ( .A(FPMULT_Op_MX[10]), .B(DP_OP_496J248_122_3540_n1504),
.CI(n5588), .CO(n5378), .S(n5377) );
NOR2X4TS U6350 ( .A(n3797), .B(n3796), .Y(n3806) );
ADDFHX4TS U6351 ( .A(n4495), .B(n4494), .CI(n4493), .CO(n5108), .S(n5106) );
ADDFHX4TS U6352 ( .A(DP_OP_497J248_123_1725_n710), .B(
DP_OP_497J248_123_1725_n702), .CI(n4502), .CO(n4553), .S(n4493) );
XNOR2X4TS U6353 ( .A(n5509), .B(n5559), .Y(n5498) );
INVX4TS U6354 ( .A(n5509), .Y(n5510) );
XNOR2X4TS U6355 ( .A(n3119), .B(n5451), .Y(n5436) );
XNOR2X4TS U6356 ( .A(n5450), .B(n5451), .Y(n4881) );
NOR2X2TS U6357 ( .A(n5451), .B(n5240), .Y(n5235) );
NAND2X2TS U6358 ( .A(n4379), .B(n4378), .Y(n4456) );
NOR2X2TS U6359 ( .A(n4379), .B(n4378), .Y(n4455) );
OAI21X4TS U6360 ( .A0(n3809), .A1(n3808), .B0(n3807), .Y(n4706) );
NAND2X4TS U6361 ( .A(n3803), .B(n3802), .Y(n3807) );
ADDFHX4TS U6362 ( .A(n4500), .B(n4499), .CI(n4498), .CO(n4562), .S(n4361) );
NAND2X6TS U6363 ( .A(n5473), .B(n5203), .Y(n5211) );
XNOR2X4TS U6364 ( .A(n5655), .B(n5568), .Y(n5417) );
ADDFHX4TS U6365 ( .A(n3999), .B(n3998), .CI(n3997), .CO(n4311), .S(n4283) );
ADDFHX4TS U6366 ( .A(n3944), .B(n3945), .CI(n3946), .CO(n3984), .S(n3978) );
XNOR2X4TS U6367 ( .A(n2366), .B(n5252), .Y(n5253) );
ADDFHX4TS U6368 ( .A(n4662), .B(n4661), .CI(n4660), .CO(n5171), .S(n5159) );
ADDFHX2TS U6369 ( .A(DP_OP_497J248_123_1725_n699), .B(
DP_OP_497J248_123_1725_n684), .CI(n3579), .CO(n4661), .S(n4631) );
AO21X4TS U6370 ( .A0(n4116), .A1(n4117), .B0(n3931), .Y(n4097) );
INVX8TS U6371 ( .A(n5556), .Y(n5577) );
ADDFHX4TS U6372 ( .A(n4415), .B(n4416), .CI(n4414), .CO(n4625), .S(n4575) );
XOR2X4TS U6373 ( .A(n4459), .B(n4458), .Y(n4471) );
ADDFHX4TS U6374 ( .A(n4397), .B(n4396), .CI(n4395), .CO(n4550), .S(n4501) );
ADDHX4TS U6375 ( .A(n5328), .B(n5327), .CO(n5356), .S(n5296) );
INVX4TS U6376 ( .A(n5271), .Y(n5328) );
NAND2X4TS U6377 ( .A(n4688), .B(n4689), .Y(n5149) );
NOR2X8TS U6378 ( .A(n3812), .B(n3811), .Y(n4700) );
ADDFHX4TS U6379 ( .A(n8937), .B(n3834), .CI(n3833), .CO(n3835), .S(n3811) );
ADDFHX4TS U6380 ( .A(n4043), .B(n4044), .CI(n4042), .CO(n4174), .S(n4020) );
ADDFHX4TS U6381 ( .A(n4046), .B(n3192), .CI(n4045), .CO(n4178), .S(n4044) );
ADDFHX4TS U6382 ( .A(n4424), .B(n4423), .CI(n4422), .CO(n4670), .S(n4633) );
NOR2X8TS U6383 ( .A(n2985), .B(n3290), .Y(n4084) );
OR2X8TS U6384 ( .A(n4473), .B(n4472), .Y(n5831) );
XNOR2X4TS U6385 ( .A(n4450), .B(n4449), .Y(n4472) );
NOR2X8TS U6386 ( .A(n4074), .B(n2245), .Y(n4901) );
ADDFHX4TS U6387 ( .A(n3973), .B(n3972), .CI(n3971), .CO(n4076), .S(n4075) );
OAI21X2TS U6388 ( .A0(n3777), .A1(n3785), .B0(n3790), .Y(n3784) );
NOR2X4TS U6389 ( .A(DP_OP_497J248_123_1725_n713), .B(n2799), .Y(n4624) );
ADDFHX4TS U6390 ( .A(n4601), .B(n4600), .CI(n4599), .CO(n5128), .S(n5111) );
XNOR2X4TS U6391 ( .A(n5731), .B(n5730), .Y(n5718) );
NAND2X4TS U6392 ( .A(n3933), .B(n3932), .Y(n4095) );
ADDFHX2TS U6393 ( .A(n5577), .B(n5576), .CI(n5575), .CO(n5657), .S(n5578) );
ADDFHX4TS U6394 ( .A(n3864), .B(n3863), .CI(n3862), .CO(n4074), .S(n4073) );
ADDFHX4TS U6395 ( .A(n4187), .B(n4186), .CI(n4185), .CO(n4330), .S(n4314) );
ADDFHX4TS U6396 ( .A(n5645), .B(n5644), .CI(n5643), .CO(n5948), .S(n5923) );
XNOR2X4TS U6397 ( .A(n5462), .B(n2972), .Y(n5698) );
NOR2X8TS U6398 ( .A(DP_OP_497J248_123_1725_n717), .B(n3118), .Y(n4606) );
NOR2X4TS U6399 ( .A(n4761), .B(n2513), .Y(n7504) );
NOR2X4TS U6400 ( .A(n5983), .B(n3818), .Y(n7286) );
AOI2BB1X2TS U6401 ( .A0N(n3818), .A1N(n5982), .B0(n3817), .Y(n3819) );
XNOR2X4TS U6402 ( .A(n5568), .B(n5353), .Y(n5325) );
BUFX20TS U6403 ( .A(n5249), .Y(n5353) );
ADDFHX4TS U6404 ( .A(n3801), .B(n8943), .CI(n8944), .CO(n3802), .S(n3797) );
NOR2X6TS U6405 ( .A(n4769), .B(n2520), .Y(n6145) );
XNOR2X4TS U6406 ( .A(n5572), .B(n5559), .Y(n5561) );
NOR2X8TS U6407 ( .A(DP_OP_498J248_124_1725_n726), .B(n3955), .Y(n4063) );
XOR2X4TS U6408 ( .A(n5591), .B(n5346), .Y(n4892) );
NAND2X4TS U6409 ( .A(n4609), .B(n4608), .Y(n6312) );
NAND2X8TS U6410 ( .A(n2427), .B(n6099), .Y(n6184) );
NOR2X4TS U6411 ( .A(n5919), .B(n5922), .Y(n6060) );
ADDFHX4TS U6412 ( .A(n4572), .B(n4571), .CI(n4570), .CO(n4603), .S(n4566) );
ADDFHX4TS U6413 ( .A(n4586), .B(n4587), .CI(n4585), .CO(n4638), .S(n4570) );
ADDFHX4TS U6414 ( .A(n4593), .B(n4592), .CI(n4591), .CO(n4611), .S(n4571) );
XNOR2X4TS U6415 ( .A(n3742), .B(n3748), .Y(n3759) );
NAND2X4TS U6416 ( .A(n3745), .B(n3747), .Y(n3742) );
NAND2X8TS U6417 ( .A(n4874), .B(n5597), .Y(n5598) );
NOR2X6TS U6418 ( .A(n3821), .B(n2478), .Y(n7280) );
ADDHX4TS U6419 ( .A(DP_OP_498J248_124_1725_n789), .B(
DP_OP_498J248_124_1725_n783), .CO(n3848), .S(n3847) );
ADDFHX4TS U6420 ( .A(n4267), .B(n4266), .CI(n4265), .CO(n4277), .S(n4263) );
ADDHX4TS U6421 ( .A(DP_OP_497J248_123_1725_n794), .B(
DP_OP_497J248_123_1725_n693), .CO(n4352), .S(n4347) );
NOR2X4TS U6422 ( .A(DP_OP_498J248_124_1725_n721), .B(
DP_OP_498J248_124_1725_n729), .Y(n4182) );
XOR2X4TS U6423 ( .A(n5316), .B(n5315), .Y(n5317) );
XNOR2X4TS U6424 ( .A(n5314), .B(n5358), .Y(n5315) );
XNOR2X4TS U6425 ( .A(n4925), .B(n4924), .Y(n4956) );
OR2X2TS U6426 ( .A(n4643), .B(n4642), .Y(n3567) );
ADDFHX4TS U6427 ( .A(n4338), .B(n4337), .CI(n4336), .CO(n4405), .S(n4403) );
ADDFHX4TS U6428 ( .A(n4394), .B(n4393), .CI(n4392), .CO(n4490), .S(n4406) );
XNOR2X4TS U6429 ( .A(n2960), .B(n2338), .Y(n5321) );
XNOR2X4TS U6430 ( .A(n5583), .B(n5353), .Y(n5354) );
XNOR2X4TS U6431 ( .A(n6051), .B(n6050), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[12]) );
XOR2X4TS U6432 ( .A(n4691), .B(n4690), .Y(n5991) );
ADDFHX4TS U6433 ( .A(n4162), .B(n4163), .CI(n4161), .CO(n4195), .S(n4059) );
ADDFHX4TS U6434 ( .A(n4175), .B(n4174), .CI(n4173), .CO(n4229), .S(n4161) );
OAI22X4TS U6435 ( .A0(n5729), .A1(n2389), .B0(n2819), .B1(n2212), .Y(n5726)
);
AO21X4TS U6436 ( .A0(n3626), .A1(n5854), .B0(n5286), .Y(n3571) );
OR2X2TS U6437 ( .A(n6127), .B(n2494), .Y(n3575) );
NOR2X4TS U6438 ( .A(DP_OP_497J248_123_1725_n714), .B(
DP_OP_497J248_123_1725_n718), .Y(n3579) );
CLKMX2X2TS U6439 ( .A(n3735), .B(n9841), .S0(n8452), .Y(n3580) );
OAI21X4TS U6440 ( .A0(FPMULT_Op_MY[9]), .A1(DP_OP_496J248_122_3540_n1467),
.B0(DP_OP_496J248_122_3540_n1477), .Y(n3612) );
OR2X2TS U6441 ( .A(n5285), .B(n5284), .Y(n3626) );
AND2X4TS U6442 ( .A(n4938), .B(n4937), .Y(n3633) );
OR2X2TS U6443 ( .A(n4064), .B(n4063), .Y(n3640) );
OR2X2TS U6444 ( .A(n4060), .B(n4061), .Y(n3641) );
OR2X2TS U6445 ( .A(n5817), .B(n5816), .Y(n3642) );
BUFX3TS U6446 ( .A(n9816), .Y(n9809) );
BUFX3TS U6447 ( .A(n9814), .Y(n9793) );
CLKBUFX2TS U6448 ( .A(n9811), .Y(n9787) );
OAI21X1TS U6449 ( .A0(n7141), .A1(n7140), .B0(n7139), .Y(n7142) );
OAI21X1TS U6450 ( .A0(n7396), .A1(n7419), .B0(n7395), .Y(n7397) );
OAI21X1TS U6451 ( .A0(n7064), .A1(n7115), .B0(n7119), .Y(n7065) );
NAND2X1TS U6452 ( .A(n6349), .B(n6347), .Y(n5172) );
OR2X2TS U6453 ( .A(n7430), .B(n6914), .Y(n7410) );
NOR2X1TS U6454 ( .A(n9205), .B(n9465), .Y(n6691) );
NAND2X1TS U6455 ( .A(n7682), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n7619) );
NAND2X1TS U6456 ( .A(n8217), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n7554) );
NAND2X1TS U6457 ( .A(n6920), .B(n6919), .Y(n6921) );
NAND2X1TS U6458 ( .A(n7682), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n7611) );
NAND2X1TS U6459 ( .A(n8075), .B(FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n7789) );
INVX2TS U6460 ( .A(Data_2[0]), .Y(n6256) );
INVX2TS U6461 ( .A(Data_2[16]), .Y(n6284) );
AOI2BB2X2TS U6462 ( .B0(n8092), .B1(n1586), .A0N(n2916), .A1N(n9391), .Y(
n7492) );
NOR2X1TS U6463 ( .A(n7324), .B(n7314), .Y(n7271) );
NAND2X1TS U6464 ( .A(n8131), .B(n7208), .Y(n7112) );
INVX2TS U6465 ( .A(Data_1[18]), .Y(n8522) );
INVX2TS U6466 ( .A(Data_1[10]), .Y(n8525) );
CLKBUFX3TS U6467 ( .A(n9971), .Y(n6441) );
BUFX3TS U6468 ( .A(n6265), .Y(n8852) );
INVX4TS U6469 ( .A(n1673), .Y(n8885) );
CLKBUFX3TS U6470 ( .A(n9769), .Y(n9517) );
CLKBUFX3TS U6471 ( .A(n9786), .Y(n9524) );
BUFX3TS U6472 ( .A(n9814), .Y(n9794) );
BUFX3TS U6473 ( .A(n9810), .Y(n9777) );
INVX2TS U6474 ( .A(FPMULT_Op_MX[18]), .Y(n3689) );
NOR2X8TS U6475 ( .A(n3682), .B(FPMULT_FS_Module_state_reg[2]), .Y(n8692) );
NAND2X8TS U6476 ( .A(n8692), .B(n6180), .Y(n8447) );
BUFX16TS U6477 ( .A(n8447), .Y(n6287) );
MXI2X4TS U6478 ( .A(n8522), .B(n3689), .S0(n6287), .Y(n1677) );
MXI2X4TS U6479 ( .A(n8513), .B(n9714), .S0(n6260), .Y(n1665) );
NOR2X4TS U6482 ( .A(n3596), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n7962)
);
NAND2X1TS U6483 ( .A(n7962), .B(FPADDSUB_Data_array_SWR[23]), .Y(n3691) );
NAND2X1TS U6484 ( .A(n7963), .B(FPADDSUB_Data_array_SWR[19]), .Y(n3690) );
NAND3X2TS U6485 ( .A(n3691), .B(n3690), .C(n7905), .Y(n9942) );
NAND2X2TS U6486 ( .A(n3596), .B(FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n7961)
);
AND2X4TS U6487 ( .A(n3700), .B(n7963), .Y(n7801) );
NAND2X1TS U6488 ( .A(n7801), .B(FPADDSUB_Data_array_SWR[3]), .Y(n3695) );
NAND4X2TS U6489 ( .A(n3697), .B(n3696), .C(n3695), .D(n3694), .Y(n9947) );
INVX4TS U6490 ( .A(n7963), .Y(n3698) );
NAND2X1TS U6491 ( .A(n7955), .B(n9246), .Y(n3699) );
NAND2X2TS U6492 ( .A(n3700), .B(FPADDSUB_left_right_SHT2), .Y(n9902) );
NOR2X4TS U6493 ( .A(n3700), .B(n9110), .Y(n7949) );
AND2X2TS U6494 ( .A(n7949), .B(FPADDSUB_left_right_SHT2), .Y(n9111) );
INVX12TS U6495 ( .A(n3702), .Y(n8680) );
NAND2X1TS U6496 ( .A(n9947), .B(n8065), .Y(n3705) );
NAND2X1TS U6497 ( .A(n9948), .B(n3701), .Y(n3704) );
NAND2X4TS U6498 ( .A(n9111), .B(n3702), .Y(n8078) );
NAND2X1TS U6499 ( .A(n8075), .B(FPADDSUB_DmP_mant_SFG_SWR[3]), .Y(n3703) );
NOR2X8TS U6501 ( .A(n3712), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.Y(n3728) );
NOR2X4TS U6502 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n3710) );
NOR2X4TS U6503 ( .A(n3706), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.Y(n3707) );
NOR2X8TS U6504 ( .A(n3715), .B(n3708), .Y(n3709) );
NAND2X2TS U6505 ( .A(operation[1]), .B(begin_operation), .Y(n8346) );
INVX2TS U6506 ( .A(n8346), .Y(n3734) );
NOR2X2TS U6507 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n3711) );
NAND2X4TS U6508 ( .A(n3719), .B(n3713), .Y(n8347) );
OR2X4TS U6509 ( .A(n3715), .B(n3714), .Y(n8307) );
INVX8TS U6510 ( .A(n3716), .Y(n8568) );
NOR3X1TS U6511 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n9244),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n3718) );
NOR2X2TS U6512 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n3720) );
NAND2X4TS U6513 ( .A(n9268), .B(n3720), .Y(n3723) );
NOR3X2TS U6514 ( .A(n3723), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]),
.C(n9266), .Y(n3721) );
NAND2X4TS U6515 ( .A(n3721), .B(n3728), .Y(n3722) );
NAND2X1TS U6516 ( .A(n8790), .B(n8494), .Y(n3725) );
NOR2X1TS U6517 ( .A(n3725), .B(n3709), .Y(n3731) );
NAND2X1TS U6518 ( .A(operation[1]), .B(ack_operation), .Y(n3729) );
NAND4X1TS U6519 ( .A(n8568), .B(n3732), .C(n3731), .D(n8497), .Y(n3733) );
INVX2TS U6520 ( .A(Data_2[30]), .Y(n3735) );
AOI21X1TS U6524 ( .A0(n9057), .A1(n9058), .B0(n9059), .Y(n6702) );
OAI21X1TS U6525 ( .A0(n9061), .A1(n9062), .B0(n9063), .Y(n6703) );
OAI21X1TS U6526 ( .A0(n6710), .A1(n6707), .B0(n6711), .Y(n3736) );
NOR2X2TS U6527 ( .A(n9065), .B(n9066), .Y(n6728) );
NAND2X6TS U6528 ( .A(n3741), .B(n2486), .Y(n3745) );
NAND2X1TS U6529 ( .A(n3768), .B(n3750), .Y(n3749) );
INVX2TS U6530 ( .A(n3745), .Y(n3746) );
AOI21X4TS U6531 ( .A0(n3748), .A1(n3747), .B0(n3746), .Y(n3787) );
INVX2TS U6532 ( .A(n3787), .Y(n3751) );
AOI21X4TS U6533 ( .A0(n3751), .A1(n3768), .B0(n3771), .Y(n3755) );
XOR2X4TS U6534 ( .A(n3755), .B(n3754), .Y(n3761) );
NAND2X2TS U6535 ( .A(n4967), .B(n3763), .Y(n3765) );
NOR2X2TS U6536 ( .A(n3765), .B(n4969), .Y(n3767) );
OAI21X1TS U6537 ( .A0(n5029), .A1(n6697), .B0(n5030), .Y(n3756) );
AOI21X4TS U6538 ( .A0(n4971), .A1(n3763), .B0(n3762), .Y(n3764) );
AOI21X4TS U6539 ( .A0(n3772), .A1(n3771), .B0(n3770), .Y(n3786) );
OA21X4TS U6540 ( .A0(n3788), .A1(n3787), .B0(n3786), .Y(n3777) );
INVX2TS U6541 ( .A(n3785), .Y(n3775) );
XNOR2X4TS U6542 ( .A(n3784), .B(n3783), .Y(n5984) );
AOI21X4TS U6543 ( .A0(n3794), .A1(n3793), .B0(n3792), .Y(n4709) );
INVX2TS U6544 ( .A(n3806), .Y(n3800) );
XNOR2X4TS U6545 ( .A(n3832), .B(n3798), .Y(n3820) );
INVX2TS U6546 ( .A(n3808), .Y(n3799) );
INVX2TS U6547 ( .A(n3809), .Y(n3804) );
AOI21X4TS U6548 ( .A0(n3832), .A1(n4701), .B0(n4706), .Y(n3815) );
INVX2TS U6549 ( .A(n4700), .Y(n3813) );
XOR2X4TS U6550 ( .A(n3815), .B(n3814), .Y(n3824) );
INVX2TS U6551 ( .A(n4744), .Y(n7490) );
NAND2X1TS U6552 ( .A(n7743), .B(n7490), .Y(n3827) );
INVX2TS U6553 ( .A(n5985), .Y(n3817) );
INVX2TS U6554 ( .A(n7489), .Y(n3825) );
AOI21X4TS U6555 ( .A0(n3832), .A1(n3831), .B0(n3830), .Y(n3839) );
INVX2TS U6556 ( .A(n4704), .Y(n3837) );
XOR2X4TS U6557 ( .A(n3839), .B(n3838), .Y(n3840) );
INVX2TS U6558 ( .A(n4760), .Y(n3841) );
NOR2X6TS U6559 ( .A(DP_OP_498J248_124_1725_n798), .B(
DP_OP_498J248_124_1725_n804), .Y(n3958) );
CMPR22X2TS U6560 ( .A(DP_OP_498J248_124_1725_n790), .B(
DP_OP_498J248_124_1725_n784), .CO(n3854), .S(n3853) );
INVX4TS U6561 ( .A(n4060), .Y(n3858) );
CMPR22X2TS U6562 ( .A(DP_OP_498J248_124_1725_n792), .B(
DP_OP_498J248_124_1725_n786), .CO(n3865), .S(n3857) );
ADDFHX4TS U6563 ( .A(n3877), .B(n3029), .CI(n3876), .CO(n3900), .S(n3912) );
ADDFHX4TS U6564 ( .A(n3886), .B(n3887), .CI(n3885), .CO(n3888), .S(n3910) );
ADDFHX4TS U6565 ( .A(n3911), .B(n3910), .CI(n3909), .CO(n3904), .S(n3933) );
INVX2TS U6566 ( .A(n4157), .Y(n3925) );
INVX2TS U6567 ( .A(n8588), .Y(n3924) );
OA21X4TS U6568 ( .A0(n3963), .A1(n3625), .B0(n3962), .Y(n4269) );
CMPR22X2TS U6569 ( .A(DP_OP_498J248_124_1725_n793), .B(
DP_OP_498J248_124_1725_n787), .CO(n3968), .S(n3856) );
ADDFHX4TS U6570 ( .A(n3983), .B(n3982), .CI(n3984), .CO(n4058), .S(n4015) );
ADDFHX4TS U6571 ( .A(n4017), .B(n4016), .CI(n4015), .CO(n4018), .S(n3981) );
OAI22X1TS U6572 ( .A0(n3391), .A1(n4184), .B0(n3113), .B1(n4035), .Y(n4172)
);
ADDFHX4TS U6573 ( .A(n4041), .B(n4040), .CI(n4039), .CO(n4175), .S(n4057) );
NAND2X2TS U6574 ( .A(n3640), .B(n4199), .Y(n4065) );
INVX2TS U6575 ( .A(n4087), .Y(n4089) );
OAI21X4TS U6576 ( .A0(n4110), .A1(n4108), .B0(n4111), .Y(n4148) );
ADDFHX4TS U6577 ( .A(n4103), .B(n4102), .CI(n4101), .CO(n4183), .S(n4099) );
INVX2TS U6578 ( .A(n4141), .Y(n4126) );
NAND2X1TS U6579 ( .A(n4183), .B(n4179), .Y(n4145) );
NAND2X1TS U6580 ( .A(n4126), .B(n4145), .Y(n4107) );
OAI21X4TS U6581 ( .A0(n4151), .A1(n4109), .B0(n4108), .Y(n4114) );
NAND2X1TS U6582 ( .A(n4112), .B(n4111), .Y(n4113) );
XNOR2X4TS U6583 ( .A(n4114), .B(n4113), .Y(n4120) );
NAND2X1TS U6584 ( .A(n4142), .B(n4126), .Y(n4128) );
INVX2TS U6585 ( .A(n4145), .Y(n4125) );
INVX2TS U6586 ( .A(n4144), .Y(n4132) );
NAND2X1TS U6587 ( .A(n4132), .B(n4143), .Y(n4133) );
AOI21X4TS U6588 ( .A0(n5917), .A1(n5918), .B0(n4137), .Y(n5954) );
XNOR2X4TS U6589 ( .A(n4139), .B(n4140), .Y(n4153) );
OAI21X1TS U6590 ( .A0(n4145), .A1(n4144), .B0(n4143), .Y(n4146) );
AOI21X1TS U6591 ( .A0(n4148), .A1(n4147), .B0(n4146), .Y(n4149) );
OAI22X1TS U6592 ( .A0(n3391), .A1(n4213), .B0(n3113), .B1(n4169), .Y(n4219)
);
INVX2TS U6593 ( .A(n4183), .Y(n4207) );
NOR2X2TS U6594 ( .A(n3113), .B(n4184), .Y(n4217) );
ADDFHX4TS U6595 ( .A(n4193), .B(n4192), .CI(n4191), .CO(n4225), .S(n4162) );
OR2X2TS U6596 ( .A(n4198), .B(n2581), .Y(n4239) );
ADDFHX4TS U6597 ( .A(n4204), .B(n4203), .CI(n4202), .CO(n4260), .S(n4226) );
OAI22X1TS U6598 ( .A0(n3391), .A1(n4254), .B0(n2905), .B1(n4268), .Y(n4257)
);
OAI22X1TS U6599 ( .A0(n3391), .A1(n4253), .B0(n3113), .B1(n4206), .Y(n4256)
);
INVX2TS U6600 ( .A(n5971), .Y(n4250) );
ADDFHX4TS U6601 ( .A(n4230), .B(n4229), .CI(n4228), .CO(n4231), .S(n4194) );
INVX2TS U6602 ( .A(n4279), .Y(n4235) );
INVX2TS U6603 ( .A(n4236), .Y(n4237) );
AOI21X4TS U6604 ( .A0(n4239), .A1(n4238), .B0(n4237), .Y(n4280) );
OAI22X1TS U6605 ( .A0(n2241), .A1(n4268), .B0(n3113), .B1(n4254), .Y(n4270)
);
NOR2X1TS U6606 ( .A(n3113), .B(n4268), .Y(n4301) );
NOR2X2TS U6607 ( .A(n4281), .B(n2342), .Y(n4303) );
OAI21X1TS U6608 ( .A0(n4290), .A1(n4303), .B0(n4305), .Y(n4286) );
NOR2X2TS U6609 ( .A(n2954), .B(n2949), .Y(n4306) );
INVX2TS U6610 ( .A(n4306), .Y(n4285) );
INVX2TS U6611 ( .A(n4303), .Y(n4289) );
CLKXOR2X2TS U6612 ( .A(n4291), .B(n4290), .Y(n4318) );
OAI21X2TS U6613 ( .A0(n4296), .A1(n4295), .B0(n4294), .Y(n4297) );
NOR2X1TS U6614 ( .A(n4306), .B(n4303), .Y(n4309) );
AOI21X4TS U6615 ( .A0(n4309), .A1(n4308), .B0(n4307), .Y(n6236) );
NOR2X2TS U6616 ( .A(n2955), .B(n2227), .Y(n4323) );
INVX2TS U6617 ( .A(n4323), .Y(n4312) );
NOR2X2TS U6618 ( .A(n4314), .B(n4315), .Y(n4326) );
INVX2TS U6619 ( .A(n4326), .Y(n4316) );
NOR2X2TS U6620 ( .A(n4323), .B(n4326), .Y(n6227) );
INVX2TS U6621 ( .A(n6227), .Y(n4328) );
INVX2TS U6622 ( .A(n6233), .Y(n4327) );
INVX2TS U6623 ( .A(n6226), .Y(n5967) );
OAI22X1TS U6624 ( .A0(n2795), .A1(n2636), .B0(n4597), .B1(n2638), .Y(n4367)
);
INVX4TS U6625 ( .A(n4333), .Y(n4549) );
ADDHX1TS U6626 ( .A(DP_OP_497J248_123_1725_n791), .B(n2261), .CO(n4334), .S(
n4333) );
OAI22X1TS U6627 ( .A0(n2216), .A1(n4549), .B0(n2794), .B1(n4598), .Y(n4365)
);
NOR2X8TS U6628 ( .A(n4489), .B(n5055), .Y(n4492) );
ADDHX4TS U6629 ( .A(n8932), .B(n4343), .CO(n4336), .S(n4401) );
INVX2TS U6630 ( .A(n4684), .Y(n4355) );
INVX2TS U6631 ( .A(n4606), .Y(n4350) );
INVX2TS U6632 ( .A(n4856), .Y(n4376) );
INVX2TS U6633 ( .A(n4548), .Y(n4351) );
ADDFHX4TS U6634 ( .A(n4359), .B(n4357), .CI(n4358), .CO(n4485), .S(n4366) );
OAI22X1TS U6635 ( .A0(n4597), .A1(n4549), .B0(n4489), .B1(n4598), .Y(n4378)
);
NOR2X2TS U6636 ( .A(n4489), .B(n4549), .Y(n4470) );
NAND2BX4TS U6637 ( .AN(n8901), .B(n8902), .Y(n4867) );
NOR2X2TS U6638 ( .A(n2693), .B(n4867), .Y(n4466) );
OA21X2TS U6639 ( .A0(n4377), .A1(n4466), .B0(n4467), .Y(n4458) );
INVX2TS U6640 ( .A(n4398), .Y(n4400) );
NOR2X2TS U6641 ( .A(n4401), .B(n4400), .Y(n4859) );
NAND2X2TS U6642 ( .A(n4401), .B(n4400), .Y(n4860) );
NAND2X2TS U6643 ( .A(n4403), .B(n4402), .Y(n4852) );
INVX2TS U6644 ( .A(n4852), .Y(n4404) );
AOI21X4TS U6645 ( .A0(n4853), .A1(n4854), .B0(n4404), .Y(n4866) );
NAND2X2TS U6646 ( .A(n4406), .B(n4405), .Y(n4865) );
ADDFHX4TS U6647 ( .A(n4409), .B(n4408), .CI(n4407), .CO(n4416), .S(n4411) );
ADDFHX4TS U6648 ( .A(n4413), .B(n4412), .CI(n4411), .CO(n4602), .S(n4554) );
INVX2TS U6649 ( .A(n4515), .Y(n4442) );
NAND2X1TS U6650 ( .A(n4516), .B(n4442), .Y(n4428) );
OAI21X4TS U6651 ( .A0(n4443), .A1(n4452), .B0(n4444), .Y(n4522) );
INVX2TS U6652 ( .A(n4519), .Y(n4426) );
AOI21X1TS U6653 ( .A0(n4522), .A1(n4442), .B0(n4426), .Y(n4427) );
INVX2TS U6654 ( .A(n4518), .Y(n4432) );
NAND2X1TS U6655 ( .A(n4432), .B(n4517), .Y(n4433) );
NAND2X4TS U6656 ( .A(n4481), .B(n4479), .Y(n4478) );
INVX2TS U6657 ( .A(n4522), .Y(n4440) );
INVX2TS U6658 ( .A(n4443), .Y(n4445) );
NAND2X1TS U6659 ( .A(n4445), .B(n4444), .Y(n4446) );
INVX2TS U6660 ( .A(n4451), .Y(n4453) );
NAND2X1TS U6661 ( .A(n4452), .B(n4453), .Y(n4454) );
INVX2TS U6662 ( .A(n4455), .Y(n4457) );
INVX2TS U6663 ( .A(n4461), .Y(n4463) );
INVX2TS U6664 ( .A(n4466), .Y(n4468) );
NAND2X1TS U6665 ( .A(n4468), .B(n4467), .Y(n4469) );
XNOR2X4TS U6666 ( .A(n4478), .B(n4482), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[10]) );
NOR2X1TS U6667 ( .A(n4515), .B(n4518), .Y(n4521) );
OAI21X1TS U6668 ( .A0(n4519), .A1(n4518), .B0(n4517), .Y(n4520) );
AOI21X1TS U6669 ( .A0(n4522), .A1(n4521), .B0(n4520), .Y(n4523) );
NAND2X4TS U6670 ( .A(n4526), .B(n4528), .Y(n4527) );
AND2X2TS U6671 ( .A(DP_OP_497J248_123_1725_n374), .B(
DP_OP_497J248_123_1725_n367), .Y(n4547) );
ADDFHX4TS U6672 ( .A(n4553), .B(n4552), .CI(n4551), .CO(n5110), .S(n5109) );
ADDFHX4TS U6673 ( .A(n4588), .B(n4589), .CI(n4590), .CO(n4613), .S(n4582) );
ADDFHX4TS U6674 ( .A(n4616), .B(n4618), .CI(n4617), .CO(n4677), .S(n4636) );
CLKXOR2X2TS U6675 ( .A(n4644), .B(n4685), .Y(n4645) );
NOR2X4TS U6676 ( .A(n4646), .B(n4645), .Y(n5148) );
INVX2TS U6677 ( .A(n5150), .Y(n4647) );
ADDHX4TS U6678 ( .A(n4658), .B(n4657), .CO(n5045), .S(n4652) );
INVX2TS U6679 ( .A(n4663), .Y(n5058) );
ADDFHX4TS U6680 ( .A(n4666), .B(n4665), .CI(n4664), .CO(n5059), .S(n4649) );
ADDFHX4TS U6681 ( .A(n4674), .B(n4675), .CI(n4673), .CO(n5041), .S(n4665) );
OR2X2TS U6682 ( .A(n4683), .B(n4684), .Y(n5105) );
XNOR2X2TS U6683 ( .A(n4687), .B(n5104), .Y(n4688) );
INVX2TS U6684 ( .A(n5152), .Y(n4691) );
ADDHX1TS U6685 ( .A(n9088), .B(n4695), .CO(n4693), .S(n4696) );
AND2X8TS U6686 ( .A(n4699), .B(n8690), .Y(n8301) );
AOI22X1TS U6687 ( .A0(n8090), .A1(n1602), .B0(n2898), .B1(n8080), .Y(n4787)
);
OAI21X4TS U6688 ( .A0(n4710), .A1(n4709), .B0(n4708), .Y(n4750) );
INVX2TS U6689 ( .A(n6193), .Y(n4725) );
XOR2X4TS U6690 ( .A(n4729), .B(n4728), .Y(n4768) );
INVX2TS U6691 ( .A(n4731), .Y(n4737) );
INVX2TS U6692 ( .A(n4732), .Y(n4733) );
OR2X2TS U6693 ( .A(n4739), .B(n8935), .Y(n4741) );
XOR2X4TS U6694 ( .A(n4743), .B(n4742), .Y(n4769) );
NOR2X8TS U6695 ( .A(n6139), .B(n6145), .Y(n6099) );
INVX2TS U6696 ( .A(n6021), .Y(n4779) );
XNOR2X4TS U6697 ( .A(n4750), .B(n4746), .Y(n4761) );
INVX2TS U6698 ( .A(n4747), .Y(n4748) );
AOI21X4TS U6699 ( .A0(n4750), .A1(n4749), .B0(n4748), .Y(n4756) );
OR2X2TS U6700 ( .A(n4752), .B(n4751), .Y(n4754) );
XOR2X4TS U6701 ( .A(n4756), .B(n4755), .Y(n4762) );
NOR2X4TS U6702 ( .A(n4757), .B(n4766), .Y(n4758) );
OAI21X4TS U6703 ( .A0(n4760), .A1(n7489), .B0(n4759), .Y(n7499) );
OAI21X4TS U6704 ( .A0(n4767), .A1(n4766), .B0(n4765), .Y(n6112) );
OAI21X4TS U6705 ( .A0(n6145), .A1(n6140), .B0(n6146), .Y(n6100) );
XOR2X4TS U6706 ( .A(n4774), .B(n9064), .Y(n4775) );
OAI2BB1X4TS U6707 ( .A0N(n2542), .A1N(n4775), .B0(n9740), .Y(n8241) );
INVX12TS U6708 ( .A(n8301), .Y(n7494) );
AOI2BB2X2TS U6709 ( .B0(n8092), .B1(n8241), .A0N(n2916), .A1N(n4777), .Y(
n4786) );
AND2X8TS U6710 ( .A(n6030), .B(n4778), .Y(n8093) );
OAI2BB1X4TS U6711 ( .A0N(n2542), .A1N(n4784), .B0(n9741), .Y(n8245) );
NAND3X2TS U6712 ( .A(n4787), .B(n4786), .C(n4785), .Y(n1538) );
OR2X2TS U6713 ( .A(FPADDSUB_Raw_mant_NRM_SWR[22]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n4788) );
NOR2X6TS U6714 ( .A(n8337), .B(n2682), .Y(n8114) );
NOR2X2TS U6715 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(
FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n6752) );
INVX2TS U6716 ( .A(n6752), .Y(n4792) );
NAND2X2TS U6717 ( .A(n8114), .B(n4792), .Y(n4797) );
OAI21X1TS U6718 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n9237), .Y(n4795) );
INVX2TS U6719 ( .A(n4793), .Y(n4794) );
INVX2TS U6720 ( .A(n4798), .Y(n4799) );
INVX2TS U6721 ( .A(n6756), .Y(n4800) );
NAND3X1TS U6722 ( .A(n6920), .B(FPADDSUB_Raw_mant_NRM_SWR[11]), .C(n9220),
.Y(n4807) );
NOR3X1TS U6723 ( .A(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(n9230), .Y(n4802) );
NOR2X1TS U6724 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n4801) );
OAI21X1TS U6725 ( .A0(n4802), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(n4801),
.Y(n4804) );
NAND2X1TS U6726 ( .A(n4804), .B(n4803), .Y(n4805) );
NAND3X1TS U6727 ( .A(n4805), .B(n9241), .C(n9100), .Y(n4806) );
AOI21X1TS U6728 ( .A0(n4811), .A1(n9240), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.Y(n4812) );
INVX2TS U6729 ( .A(n4813), .Y(n4815) );
INVX2TS U6730 ( .A(n6920), .Y(n4814) );
OA21X4TS U6731 ( .A0(n8337), .A1(n4817), .B0(n4816), .Y(n8121) );
NAND2X1TS U6732 ( .A(n9095), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4824) );
NAND2X1TS U6733 ( .A(n4818), .B(FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n4821) );
OAI21X1TS U6734 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[21]), .A1(n9232), .B0(n9097),
.Y(n4819) );
OAI22X1TS U6735 ( .A0(n6756), .A1(n4821), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n4820), .Y(n4822) );
NAND2X1TS U6736 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4832) );
NAND2X1TS U6737 ( .A(n8774), .B(FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n4830) );
NAND3X1TS U6738 ( .A(n4832), .B(n4831), .C(n4830), .Y(n7087) );
INVX2TS U6739 ( .A(n7087), .Y(n7043) );
NAND2X1TS U6740 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n4836) );
NAND2X1TS U6741 ( .A(n7055), .B(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n4835) );
NAND2X1TS U6742 ( .A(n8774), .B(FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n4834) );
AOI2BB2X1TS U6743 ( .B0(n7308), .B1(n7045), .A0N(n7315), .A1N(n7089), .Y(
n4845) );
NAND2X1TS U6744 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n4843) );
NAND2X1TS U6745 ( .A(n7055), .B(FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n4842) );
NAND2X1TS U6746 ( .A(n8774), .B(FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n4841) );
NAND3X2TS U6747 ( .A(n4843), .B(n4842), .C(n4841), .Y(n7086) );
AOI22X1TS U6748 ( .A0(n7329), .A1(n7086), .B0(FPADDSUB_Data_array_SWR[1]),
.B1(n8342), .Y(n4844) );
NAND3BX2TS U6749 ( .AN(n4846), .B(n4845), .C(n4844), .Y(n1790) );
NAND2X2TS U6750 ( .A(n4849), .B(n4848), .Y(n4851) );
OR2X2TS U6751 ( .A(n4857), .B(n4856), .Y(n4858) );
INVX2TS U6752 ( .A(n4859), .Y(n4861) );
CLKINVX6TS U6753 ( .A(n8983), .Y(n4868) );
NAND2X4TS U6754 ( .A(n4868), .B(n8984), .Y(n4869) );
XOR2X4TS U6755 ( .A(DP_OP_496J248_122_3540_n1202), .B(n4869), .Y(n4870) );
XNOR2X4TS U6756 ( .A(n5452), .B(n5450), .Y(n4879) );
AND2X8TS U6757 ( .A(n4871), .B(DP_OP_496J248_122_3540_n1122), .Y(n5188) );
XNOR2X4TS U6758 ( .A(n4872), .B(n5183), .Y(n4873) );
NAND2X4TS U6759 ( .A(n9034), .B(DP_OP_496J248_122_3540_n1205), .Y(n4876) );
NOR2X4TS U6760 ( .A(n5270), .B(n5271), .Y(n4929) );
INVX2TS U6761 ( .A(n4937), .Y(n4946) );
NAND2X4TS U6762 ( .A(n4942), .B(n4943), .Y(n5327) );
INVX2TS U6763 ( .A(n5327), .Y(n4882) );
NAND2X2TS U6764 ( .A(n5270), .B(n5271), .Y(n4930) );
INVX2TS U6765 ( .A(n4922), .Y(n4887) );
AOI21X4TS U6766 ( .A0(n4924), .A1(n4923), .B0(n4887), .Y(n5844) );
XNOR2X1TS U6767 ( .A(n5591), .B(n2906), .Y(n4893) );
NAND2BX1TS U6768 ( .AN(n2906), .B(n3119), .Y(n4898) );
INVX2TS U6769 ( .A(n5845), .Y(n4899) );
XOR2X2TS U6770 ( .A(n5844), .B(n4900), .Y(n4921) );
NAND2X1TS U6771 ( .A(n2332), .B(n4902), .Y(n4904) );
XOR2X4TS U6772 ( .A(n4904), .B(n4903), .Y(n8696) );
INVX2TS U6773 ( .A(n8696), .Y(n5850) );
INVX2TS U6774 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n5849) );
XNOR2X4TS U6775 ( .A(n4908), .B(n4907), .Y(n8587) );
OR2X2TS U6776 ( .A(n4910), .B(n4909), .Y(n4911) );
INVX2TS U6777 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(n4947) );
INVX2TS U6778 ( .A(n4915), .Y(n4917) );
INVX2TS U6779 ( .A(n8636), .Y(n4926) );
ADDFHX4TS U6780 ( .A(n4928), .B(n4927), .CI(n4926), .CO(n5848), .S(n4955) );
INVX2TS U6781 ( .A(n4929), .Y(n4931) );
OR2X2TS U6782 ( .A(n5205), .B(n5204), .Y(n4938) );
NAND2X2TS U6783 ( .A(n3633), .B(n4941), .Y(n5779) );
INVX2TS U6784 ( .A(n4943), .Y(n4944) );
OR2X2TS U6785 ( .A(n4951), .B(n4950), .Y(n5790) );
NAND2X2TS U6786 ( .A(n4951), .B(n4950), .Y(n5789) );
INVX2TS U6787 ( .A(n5789), .Y(n4952) );
NAND2X2TS U6788 ( .A(n4954), .B(n4953), .Y(n6011) );
NAND2X2TS U6789 ( .A(n4956), .B(n4955), .Y(n5998) );
INVX2TS U6790 ( .A(n5998), .Y(n4957) );
INVX2TS U6791 ( .A(n5983), .Y(n4963) );
NAND2X1TS U6792 ( .A(n4963), .B(n5982), .Y(n4964) );
XOR2X1TS U6793 ( .A(n2329), .B(n4964), .Y(n4965) );
INVX2TS U6794 ( .A(n4967), .Y(n4985) );
INVX2TS U6795 ( .A(n4968), .Y(n4990) );
INVX2TS U6796 ( .A(n4969), .Y(n5013) );
NAND2X1TS U6797 ( .A(n4973), .B(n5013), .Y(n4975) );
INVX2TS U6798 ( .A(n4971), .Y(n4986) );
OAI21X1TS U6799 ( .A0(n4986), .A1(n4968), .B0(n4989), .Y(n4972) );
AOI21X1TS U6800 ( .A0(n5012), .A1(n4973), .B0(n4972), .Y(n4974) );
INVX2TS U6801 ( .A(n4976), .Y(n4978) );
AOI22X1TS U6802 ( .A0(n8081), .A1(FPMULT_Add_result[5]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n7494), .Y(n4984) );
AOI2BB2X4TS U6803 ( .B0(n8092), .B1(n1581), .A0N(n2915), .A1N(n9104), .Y(
n4983) );
NAND2X1TS U6804 ( .A(n5013), .B(n4967), .Y(n4988) );
AOI21X1TS U6805 ( .A0(n5012), .A1(n4967), .B0(n4971), .Y(n4987) );
OAI21X1TS U6806 ( .A0(n6727), .A1(n4988), .B0(n4987), .Y(n4992) );
XOR2X1TS U6807 ( .A(n4992), .B(n4991), .Y(n4993) );
AOI22X1TS U6808 ( .A0(n8090), .A1(FPMULT_Add_result[4]), .B0(
FPMULT_Sgf_normalized_result[3]), .B1(n7494), .Y(n4996) );
INVX2TS U6809 ( .A(n4997), .Y(n5015) );
NAND2X1TS U6810 ( .A(n5013), .B(n5015), .Y(n5000) );
INVX2TS U6811 ( .A(n5014), .Y(n4998) );
AOI21X1TS U6812 ( .A0(n5012), .A1(n5015), .B0(n4998), .Y(n4999) );
OAI21X1TS U6813 ( .A0(n6727), .A1(n5000), .B0(n4999), .Y(n5005) );
INVX2TS U6814 ( .A(n5001), .Y(n5003) );
AND2X2TS U6815 ( .A(n5003), .B(n5002), .Y(n5004) );
AOI22X1TS U6816 ( .A0(n7758), .A1(FPMULT_Add_result[3]), .B0(
FPMULT_Sgf_normalized_result[2]), .B1(n7494), .Y(n5011) );
INVX2TS U6817 ( .A(n6727), .Y(n6696) );
XOR2X1TS U6818 ( .A(n5017), .B(n5016), .Y(n5018) );
AOI22X1TS U6819 ( .A0(n8081), .A1(FPMULT_Add_result[2]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n7494), .Y(n5022) );
INVX2TS U6820 ( .A(n5024), .Y(n6698) );
INVX2TS U6821 ( .A(n5025), .Y(n6695) );
INVX2TS U6822 ( .A(n6697), .Y(n5026) );
AO21X1TS U6823 ( .A0(n5025), .A1(n6698), .B0(n5026), .Y(n5027) );
INVX2TS U6824 ( .A(n5029), .Y(n5031) );
XOR2X1TS U6825 ( .A(n5032), .B(n3680), .Y(n5033) );
AOI22X1TS U6826 ( .A0(n8090), .A1(FPMULT_Add_result[1]), .B0(
FPMULT_Sgf_normalized_result[0]), .B1(n8089), .Y(n5036) );
ADDFHX4TS U6827 ( .A(n5042), .B(n5041), .CI(n5040), .CO(n5063), .S(n5060) );
ADDFHX4TS U6828 ( .A(DP_OP_497J248_123_1725_n687), .B(n2602), .CI(n5051),
.CO(n6080), .S(n5170) );
ADDFHX4TS U6829 ( .A(n5064), .B(n5063), .CI(n5062), .CO(n5084), .S(n5082) );
NOR2X1TS U6830 ( .A(n5091), .B(n5072), .Y(n5093) );
ADDFHX4TS U6831 ( .A(n5080), .B(n5079), .CI(n5078), .CO(n5088), .S(n5062) );
INVX2TS U6832 ( .A(n5134), .Y(n5085) );
OAI21X4TS U6833 ( .A0(n5133), .A1(n5087), .B0(n5086), .Y(n5101) );
ADDFHX4TS U6834 ( .A(n5090), .B(n5089), .CI(n5088), .CO(n5099), .S(n5083) );
INVX2TS U6835 ( .A(n5117), .Y(n5100) );
INVX2TS U6836 ( .A(n5102), .Y(n5103) );
INVX2TS U6837 ( .A(n5125), .Y(n5140) );
NOR2X2TS U6838 ( .A(n5109), .B(n5108), .Y(n5136) );
OAI21X1TS U6839 ( .A0(n5140), .A1(n5136), .B0(n5137), .Y(n5114) );
NOR2X2TS U6840 ( .A(n2801), .B(n5110), .Y(n5123) );
INVX2TS U6841 ( .A(n5123), .Y(n5112) );
NOR2X1TS U6842 ( .A(n5123), .B(n5136), .Y(n5126) );
OAI21X1TS U6843 ( .A0(n5123), .A1(n5137), .B0(n5122), .Y(n5124) );
AOI21X4TS U6844 ( .A0(n5126), .A1(n5125), .B0(n5124), .Y(n6353) );
NOR2X2TS U6845 ( .A(n5127), .B(n2249), .Y(n5164) );
INVX2TS U6846 ( .A(n5164), .Y(n5129) );
INVX2TS U6847 ( .A(n5136), .Y(n5138) );
CLKXOR2X2TS U6848 ( .A(n5140), .B(n5139), .Y(n5156) );
INVX2TS U6849 ( .A(n5143), .Y(n5145) );
CLKXOR2X2TS U6850 ( .A(n5147), .B(n5146), .Y(n5154) );
INVX2TS U6851 ( .A(n5167), .Y(n5161) );
INVX2TS U6852 ( .A(n6077), .Y(n5169) );
INVX2TS U6853 ( .A(n6350), .Y(n5168) );
OAI21X1TS U6854 ( .A0(n6353), .A1(n5169), .B0(n5168), .Y(n5173) );
INVX2TS U6855 ( .A(n5176), .Y(n5178) );
NAND2X2TS U6856 ( .A(n5178), .B(n5177), .Y(n5179) );
OA21X4TS U6857 ( .A0(n5185), .A1(n5207), .B0(n5199), .Y(n5190) );
NOR2BX4TS U6858 ( .AN(DP_OP_496J248_122_3540_n1464), .B(n8987), .Y(n5404) );
NOR2X8TS U6859 ( .A(n5188), .B(DP_OP_496J248_122_3540_n828), .Y(n5198) );
INVX2TS U6860 ( .A(n5198), .Y(n5206) );
NAND2X8TS U6861 ( .A(n5190), .B(n5189), .Y(n5302) );
AO21X4TS U6862 ( .A0(n5193), .A1(n3631), .B0(n5212), .Y(n5195) );
XNOR2X4TS U6863 ( .A(n5583), .B(n5463), .Y(n5234) );
XNOR2X4TS U6864 ( .A(n5212), .B(n5201), .Y(n5197) );
XNOR2X4TS U6865 ( .A(n5568), .B(n5463), .Y(n5261) );
INVX2TS U6866 ( .A(n5204), .Y(n5283) );
INVX2TS U6867 ( .A(n5205), .Y(n5282) );
NAND2X1TS U6868 ( .A(n8990), .B(n3616), .Y(n5213) );
XNOR2X4TS U6869 ( .A(n2718), .B(n5216), .Y(n5217) );
INVX2TS U6870 ( .A(n2673), .Y(n5220) );
INVX2TS U6871 ( .A(n5319), .Y(n5228) );
AOI21X4TS U6872 ( .A0(n5226), .A1(n5225), .B0(n5224), .Y(n5364) );
INVX2TS U6873 ( .A(n5364), .Y(n5227) );
NAND2BX4TS U6874 ( .AN(DP_OP_496J248_122_3540_n1504), .B(n9689), .Y(n5318)
);
ADDFHX4TS U6875 ( .A(DP_OP_496J248_122_3540_n1515), .B(
DP_OP_496J248_122_3540_n1502), .CI(DP_OP_496J248_122_3540_n839), .CO(
n5243), .S(n5240) );
XNOR2X4TS U6876 ( .A(n5242), .B(n5235), .Y(n5238) );
XOR2X1TS U6877 ( .A(n5452), .B(n5240), .Y(n5241) );
XNOR2X4TS U6878 ( .A(n5377), .B(n5371), .Y(n5332) );
XNOR2X4TS U6879 ( .A(n5332), .B(n5331), .Y(n5249) );
NAND2X2TS U6880 ( .A(n2673), .B(n5251), .Y(n5252) );
XOR2X4TS U6881 ( .A(FPMULT_Op_MY[9]), .B(DP_OP_496J248_122_3540_n1467), .Y(
n5262) );
INVX2TS U6882 ( .A(n5255), .Y(n5256) );
INVX2TS U6883 ( .A(n5816), .Y(n5280) );
XNOR2X1TS U6884 ( .A(n9036), .B(DP_OP_496J248_122_3540_n1467), .Y(n5263) );
NOR2X1TS U6885 ( .A(n5263), .B(n5262), .Y(n5264) );
NAND2BX1TS U6886 ( .AN(n5412), .B(n2338), .Y(n5266) );
XNOR2X1TS U6887 ( .A(n5412), .B(n2338), .Y(n5267) );
OAI22X2TS U6888 ( .A0(n5321), .A1(n5553), .B0(n5554), .B1(n5267), .Y(n5293)
);
INVX2TS U6889 ( .A(n5270), .Y(n5297) );
INVX2TS U6890 ( .A(n5784), .Y(n5284) );
INVX2TS U6891 ( .A(n5993), .Y(n5854) );
INVX2TS U6892 ( .A(n5853), .Y(n5286) );
ADDFHX4TS U6893 ( .A(FPMULT_Op_MY[10]), .B(n2234), .CI(n5303), .CO(n5304),
.S(n5232) );
OAI22X2TS U6894 ( .A0(n5351), .A1(n5473), .B0(n5308), .B1(n5211), .Y(n5368)
);
NOR2BX2TS U6895 ( .AN(n5412), .B(n5653), .Y(n5385) );
OAI22X2TS U6896 ( .A0(n5321), .A1(n5554), .B0(n5360), .B1(n5553), .Y(n5383)
);
INVX2TS U6897 ( .A(n6211), .Y(n5342) );
XOR2X4TS U6898 ( .A(n5379), .B(n5378), .Y(n5373) );
NOR2X2TS U6899 ( .A(n5377), .B(n5371), .Y(n5330) );
NOR2BX1TS U6900 ( .AN(n2907), .B(n5720), .Y(n5343) );
ADDFHX4TS U6901 ( .A(n5337), .B(n5336), .CI(n5335), .CO(n5338), .S(n5292) );
ADDFHX4TS U6902 ( .A(n5345), .B(n5344), .CI(n5343), .CO(n5422), .S(n5340) );
INVX2TS U6903 ( .A(n5355), .Y(n5418) );
OAI21X2TS U6904 ( .A0(n5364), .A1(n3252), .B0(n5363), .Y(n5365) );
XOR2X1TS U6905 ( .A(n5378), .B(n5371), .Y(n5372) );
XNOR2X1TS U6906 ( .A(n5655), .B(n2907), .Y(n5382) );
ADDFHX4TS U6907 ( .A(n5388), .B(n5387), .CI(n5386), .CO(n5389), .S(n5339) );
INVX2TS U6908 ( .A(n5404), .Y(n5406) );
INVX2TS U6909 ( .A(n2260), .Y(n5407) );
NAND2BX1TS U6910 ( .AN(n5475), .B(n5732), .Y(n5448) );
INVX2TS U6911 ( .A(n5452), .Y(n5589) );
XNOR2X4TS U6912 ( .A(n2993), .B(n2242), .Y(n5484) );
XNOR2X4TS U6913 ( .A(n5750), .B(n2242), .Y(n5563) );
ADDFHX4TS U6914 ( .A(n5497), .B(n5496), .CI(n5495), .CO(n5625), .S(n5529) );
ADDFHX4TS U6915 ( .A(n5536), .B(n5535), .CI(n5534), .CO(n5539), .S(n5538) );
NAND2X4TS U6916 ( .A(n5540), .B(n5539), .Y(n5820) );
ADDFHX4TS U6917 ( .A(n5547), .B(n5546), .CI(n5545), .CO(n5621), .S(n5628) );
XNOR2X4TS U6918 ( .A(n5462), .B(n2242), .Y(n5567) );
OAI22X2TS U6919 ( .A0(n5660), .A1(n2806), .B0(n5570), .B1(n5746), .Y(n5668)
);
INVX2TS U6920 ( .A(n5572), .Y(n5573) );
OAI22X4TS U6921 ( .A0(n5574), .A1(n5654), .B0(n5653), .B1(n5652), .Y(n5707)
);
INVX2TS U6922 ( .A(n5707), .Y(n5658) );
INVX2TS U6923 ( .A(n5583), .Y(n5584) );
OAI22X4TS U6924 ( .A0(n5729), .A1(n5589), .B0(n2819), .B1(n3334), .Y(n5593)
);
ADDFHX4TS U6925 ( .A(n5622), .B(n5621), .CI(n5620), .CO(n5676), .S(n5630) );
ADDFHX4TS U6926 ( .A(n5631), .B(n5630), .CI(n5629), .CO(n5634), .S(n5633) );
AOI21X4TS U6927 ( .A0(n3304), .A1(n6085), .B0(n6087), .Y(n5680) );
INVX2TS U6928 ( .A(n5726), .Y(n5694) );
INVX2TS U6929 ( .A(n5947), .Y(n5701) );
NOR2X1TS U6930 ( .A(n5647), .B(n5761), .Y(n5711) );
INVX2TS U6931 ( .A(n6341), .Y(n5688) );
OAI22X1TS U6932 ( .A0(n5712), .A1(n2806), .B0(n5660), .B1(n5746), .Y(n5687)
);
ADDFHX4TS U6933 ( .A(n5667), .B(n5665), .CI(n5666), .CO(n5692), .S(n5664) );
INVX2TS U6934 ( .A(n6334), .Y(n5691) );
ADDFHX4TS U6935 ( .A(n5676), .B(n5675), .CI(n5674), .CO(n5677), .S(n5635) );
XOR2X4TS U6936 ( .A(n5680), .B(n5679), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
ADDFHX4TS U6937 ( .A(n5695), .B(n5694), .CI(n5693), .CO(n6071), .S(n5947) );
INVX2TS U6938 ( .A(n6071), .Y(n5736) );
INVX2TS U6939 ( .A(n2580), .Y(n5697) );
INVX2TS U6940 ( .A(n5708), .Y(n5730) );
ADDFHX2TS U6941 ( .A(n5715), .B(n5714), .CI(n5713), .CO(n5742), .S(n5737) );
ADDFHX2TS U6942 ( .A(n5718), .B(n5717), .CI(n5716), .CO(n5755), .S(n5713) );
INVX2TS U6943 ( .A(n2993), .Y(n5723) );
OAI22X1TS U6944 ( .A0(n5733), .A1(n5746), .B0(n5747), .B1(n2806), .Y(n5744)
);
OAI22X1TS U6945 ( .A0(n5747), .A1(n5746), .B0(n2806), .B1(n5761), .Y(n5769)
);
INVX2TS U6946 ( .A(n5748), .Y(n5766) );
OR2X2TS U6947 ( .A(n5749), .B(n5748), .Y(n5765) );
CMPR32X2TS U6948 ( .A(n5752), .B(n5751), .C(n6298), .CO(n5767), .S(n5754) );
OAI21X4TS U6949 ( .A0(n6155), .A1(n6376), .B0(n6377), .Y(
DP_OP_496J248_122_3540_n36) );
XNOR2X1TS U6950 ( .A(n5763), .B(n5762), .Y(n5772) );
NAND2X4TS U6951 ( .A(n8690), .B(n1600), .Y(n5775) );
NOR2X4TS U6952 ( .A(n6744), .B(n5775), .Y(n5777) );
OR2X8TS U6953 ( .A(n5777), .B(n5776), .Y(n6649) );
INVX2TS U6954 ( .A(n5778), .Y(n5780) );
CLKXOR2X2TS U6955 ( .A(n5782), .B(n5781), .Y(n5783) );
AFHCONX2TS U6956 ( .A(n3924), .B(n4867), .CI(n5784), .CON(n5781), .S(n8098)
);
ADDFHX4TS U6957 ( .A(n5804), .B(n5803), .CI(n5802), .CO(n5811), .S(n5809) );
ADDFHX4TS U6958 ( .A(n5807), .B(n5806), .CI(n5805), .CO(n5808), .S(n5678) );
NAND2X2TS U6959 ( .A(n6157), .B(n6155), .Y(n5812) );
XNOR2X4TS U6960 ( .A(n3304), .B(n5815), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
NAND2X2TS U6961 ( .A(n5817), .B(n5816), .Y(n6240) );
NAND2X4TS U6962 ( .A(n5821), .B(n5820), .Y(n5822) );
XNOR2X4TS U6963 ( .A(n5823), .B(n5822), .Y(n6154) );
NAND2X4TS U6964 ( .A(DP_OP_499J248_125_1651_n219), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .Y(n8933) );
AOI21X4TS U6965 ( .A0(n5832), .A1(n5831), .B0(n5830), .Y(n5835) );
NAND2X2TS U6966 ( .A(n3568), .B(n5833), .Y(n5834) );
INVX2TS U6967 ( .A(n5836), .Y(n5837) );
AOI21X4TS U6968 ( .A0(n5839), .A1(n5838), .B0(n5837), .Y(n6292) );
INVX2TS U6969 ( .A(n5872), .Y(n5859) );
XOR2X4TS U6970 ( .A(n5846), .B(n5859), .Y(n5852) );
NOR2X2TS U6971 ( .A(n5852), .B(n5851), .Y(n6289) );
NAND2X2TS U6972 ( .A(n5852), .B(n5851), .Y(n6290) );
OAI21X4TS U6973 ( .A0(n6292), .A1(n6289), .B0(n6290), .Y(n6317) );
NAND2X1TS U6974 ( .A(n3626), .B(n5853), .Y(n5855) );
XNOR2X1TS U6975 ( .A(n5855), .B(n5854), .Y(n5885) );
NAND2X4TS U6976 ( .A(n5857), .B(n5856), .Y(n5858) );
XNOR2X4TS U6977 ( .A(n5858), .B(n2655), .Y(n8740) );
INVX2TS U6978 ( .A(n8740), .Y(n5884) );
INVX2TS U6979 ( .A(n5871), .Y(n5862) );
NAND2X4TS U6980 ( .A(n5889), .B(n5879), .Y(n5880) );
XNOR2X4TS U6981 ( .A(n5883), .B(n3571), .Y(n5895) );
ADDHX1TS U6982 ( .A(n5885), .B(n5884), .CO(n5894), .S(n5876) );
AOI21X4TS U6983 ( .A0(n2318), .A1(n5889), .B0(n5888), .Y(n5893) );
XOR2X4TS U6984 ( .A(n5893), .B(n5892), .Y(n8771) );
INVX2TS U6985 ( .A(n8771), .Y(n5929) );
INVX2TS U6986 ( .A(n5897), .Y(n5899) );
INVX2TS U6987 ( .A(n5921), .Y(n5905) );
INVX2TS U6988 ( .A(n5922), .Y(n5909) );
NAND2X1TS U6989 ( .A(n5909), .B(n5920), .Y(n5910) );
XOR2X1TS U6990 ( .A(n5911), .B(n5910), .Y(n5930) );
INVX2TS U6991 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .Y(n5941) );
NAND2X4TS U6992 ( .A(n5934), .B(n5933), .Y(n6174) );
OAI21X4TS U6993 ( .A0(n6176), .A1(n6173), .B0(n6174), .Y(n6209) );
NAND2X4TS U6994 ( .A(n5937), .B(n5936), .Y(n5938) );
XOR2X4TS U6995 ( .A(n5939), .B(n5938), .Y(n6075) );
NOR2X4TS U6996 ( .A(n5943), .B(n6059), .Y(n5945) );
INVX2TS U6997 ( .A(n6064), .Y(n5949) );
XOR2X4TS U6998 ( .A(n5951), .B(n5950), .Y(n6058) );
OAI21X4TS U6999 ( .A0(n8104), .A1(n5965), .B0(n5964), .Y(n5976) );
NAND2X1TS U7000 ( .A(n6227), .B(n5967), .Y(n5969) );
INVX2TS U7001 ( .A(n6230), .Y(n5966) );
AOI21X1TS U7002 ( .A0(n6233), .A1(n5967), .B0(n5966), .Y(n5968) );
OAI21X1TS U7003 ( .A0(n6236), .A1(n5969), .B0(n5968), .Y(n5974) );
INVX2TS U7004 ( .A(n6229), .Y(n5972) );
NAND2X1TS U7005 ( .A(n5971), .B(n5970), .Y(n6228) );
NAND2X1TS U7006 ( .A(n5972), .B(n6228), .Y(n5973) );
XNOR2X1TS U7007 ( .A(n5974), .B(n5973), .Y(n5975) );
INVX2TS U7008 ( .A(n5975), .Y(n6222) );
XNOR2X4TS U7009 ( .A(n5976), .B(n6222), .Y(add_x_254_SUM_22_) );
XOR2X4TS U7010 ( .A(n5981), .B(n5980), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
NAND2X1TS U7011 ( .A(n5986), .B(n5985), .Y(n5987) );
XNOR2X1TS U7012 ( .A(n5988), .B(n5987), .Y(n5989) );
INVX2TS U7013 ( .A(n5996), .Y(n6013) );
AOI21X1TS U7014 ( .A0(n6013), .A1(n6012), .B0(n5997), .Y(n6001) );
NAND2X4TS U7015 ( .A(add_x_69_n328), .B(add_x_69_n291), .Y(add_x_69_n28) );
OAI21X4TS U7016 ( .A0(n2329), .A1(n6007), .B0(n6006), .Y(n6009) );
INVX2TS U7017 ( .A(n6183), .Y(n6022) );
INVX2TS U7018 ( .A(n7045), .Y(n7240) );
NOR2X1TS U7019 ( .A(n8125), .B(n7240), .Y(n6043) );
NAND2X1TS U7020 ( .A(n7211), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n6034) );
NAND2X1TS U7021 ( .A(n7212), .B(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n6032) );
NAND3X2TS U7022 ( .A(n6034), .B(n6033), .C(n6032), .Y(n7309) );
NAND2X1TS U7023 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n6037) );
NAND2X1TS U7024 ( .A(n7055), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n6036) );
NAND2X1TS U7025 ( .A(n7212), .B(FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n6035) );
AOI22X1TS U7026 ( .A0(n7317), .A1(n7309), .B0(n7044), .B1(n7241), .Y(n6042)
);
NAND2X1TS U7027 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n6040) );
NAND2X1TS U7028 ( .A(n7055), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n6039) );
NAND2X1TS U7029 ( .A(n8774), .B(FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n6038) );
NAND3X2TS U7030 ( .A(n6040), .B(n6039), .C(n6038), .Y(n7242) );
INVX2TS U7031 ( .A(n7242), .Y(n7306) );
AOI2BB2X1TS U7032 ( .B0(FPADDSUB_Data_array_SWR[4]), .B1(n8342), .A0N(n8127),
.A1N(n7306), .Y(n6041) );
NAND3BX2TS U7033 ( .AN(n6043), .B(n6042), .C(n6041), .Y(n1793) );
XNOR2X4TS U7034 ( .A(n6047), .B(n6046), .Y(FPMULT_Sgf_operation_EVEN1_S_B[9]) );
NAND2X2TS U7035 ( .A(n6060), .B(n6067), .Y(n6069) );
OAI21X1TS U7036 ( .A0(n6064), .A1(n6063), .B0(n6062), .Y(n6065) );
AOI21X2TS U7037 ( .A0(n6067), .A1(n6066), .B0(n6065), .Y(n6068) );
OAI21X4TS U7038 ( .A0(n6069), .A1(n6061), .B0(n6068), .Y(n6297) );
OR2X2TS U7039 ( .A(n6071), .B(n6070), .Y(n6296) );
NAND2X1TS U7040 ( .A(n6071), .B(n6070), .Y(n6294) );
NAND2X1TS U7041 ( .A(n6296), .B(n6294), .Y(n6072) );
INVX2TS U7042 ( .A(n6347), .Y(n6078) );
AOI21X1TS U7043 ( .A0(n6350), .A1(n6349), .B0(n6078), .Y(n6079) );
OAI21X1TS U7044 ( .A0(n6353), .A1(n6352), .B0(n6079), .Y(n6081) );
INVX2TS U7045 ( .A(n6354), .Y(n6082) );
NAND2X4TS U7046 ( .A(n6084), .B(n6083), .Y(add_x_69_n30) );
ADDHX1TS U7047 ( .A(n9090), .B(n9091), .CO(n6161), .S(n6091) );
AOI22X1TS U7048 ( .A0(n8090), .A1(n1605), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n8080), .Y(n6109) );
INVX2TS U7049 ( .A(n6184), .Y(n6092) );
NAND2X1TS U7050 ( .A(n6185), .B(n6092), .Y(n6095) );
OAI2BB1X4TS U7051 ( .A0N(n6190), .A1N(n6092), .B0(n6186), .Y(n6093) );
OAI2BB1X4TS U7052 ( .A0N(n2546), .A1N(n6097), .B0(n9736), .Y(n8242) );
INVX2TS U7053 ( .A(n1606), .Y(n6098) );
OAI2BB1X4TS U7054 ( .A0N(n2546), .A1N(n6106), .B0(n9737), .Y(n8244) );
NAND3X2TS U7055 ( .A(n6109), .B(n6108), .C(n6107), .Y(n1535) );
AOI22X1TS U7056 ( .A0(n7758), .A1(n1606), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n8089), .Y(n6119) );
AOI2BB2X4TS U7057 ( .B0(n8083), .B1(n8244), .A0N(n2916), .A1N(n9250), .Y(
n6118) );
AOI21X1TS U7058 ( .A0(n6112), .A1(n6111), .B0(n6110), .Y(n6113) );
OAI2BB1X4TS U7059 ( .A0N(n2546), .A1N(n6116), .B0(n9738), .Y(n8243) );
AOI22X1TS U7060 ( .A0(n8090), .A1(FPMULT_Add_result[16]), .B0(n1532), .B1(
n8089), .Y(n6135) );
OAI2BB1X4TS U7061 ( .A0N(n2546), .A1N(n6125), .B0(n9742), .Y(n8250) );
AOI2BB2X2TS U7062 ( .B0(n8092), .B1(n8250), .A0N(n2916), .A1N(n9252), .Y(
n6134) );
OAI2BB1X4TS U7063 ( .A0N(n2546), .A1N(n6132), .B0(n9743), .Y(n8247) );
AOI22X1TS U7064 ( .A0(n8081), .A1(FPMULT_Add_result[17]), .B0(n1533), .B1(
n8089), .Y(n6138) );
AOI2BB2X2TS U7065 ( .B0(n8092), .B1(n8243), .A0N(n2916), .A1N(n9251), .Y(
n6137) );
AOI22X1TS U7066 ( .A0(n7758), .A1(FPMULT_Add_result[15]), .B0(
FPMULT_Sgf_normalized_result[14]), .B1(n8089), .Y(n6153) );
AOI2BB2X2TS U7067 ( .B0(n7759), .B1(n8247), .A0N(n2915), .A1N(n9253), .Y(
n6152) );
INVX2TS U7068 ( .A(n6139), .Y(n6141) );
NAND2X1TS U7069 ( .A(n6185), .B(n6141), .Y(n6144) );
OAI2BB1X4TS U7070 ( .A0N(n6190), .A1N(n6141), .B0(n6140), .Y(n6142) );
INVX2TS U7071 ( .A(n6145), .Y(n6147) );
AND2X2TS U7072 ( .A(n6147), .B(n6146), .Y(n6148) );
NAND2X2TS U7073 ( .A(n8071), .B(n8248), .Y(n6151) );
NAND3X2TS U7074 ( .A(n6153), .B(n6152), .C(n6151), .Y(n1531) );
ADDFHX4TS U7075 ( .A(n5818), .B(n2812), .CI(n6154), .CO(
DP_OP_499J248_125_1651_n219), .S(DP_OP_499J248_125_1651_n220) );
INVX2TS U7076 ( .A(n6155), .Y(n6156) );
ADDFHX4TS U7077 ( .A(n6160), .B(n6159), .CI(n6158), .CO(
DP_OP_499J248_125_1651_n229), .S(n6179) );
ADDHX1TS U7078 ( .A(n9089), .B(n6161), .CO(n4695), .S(n6162) );
AOI22X1TS U7079 ( .A0(n7758), .A1(n1603), .B0(n1537), .B1(n8080), .Y(n6171)
);
INVX2TS U7080 ( .A(n1604), .Y(n6163) );
AOI2BB2X2TS U7081 ( .B0(n7759), .B1(n8245), .A0N(n2916), .A1N(n6163), .Y(
n6170) );
XOR2X4TS U7082 ( .A(n6167), .B(n2429), .Y(n6168) );
NAND2X2TS U7083 ( .A(n8071), .B(n8246), .Y(n6169) );
NAND2X4TS U7084 ( .A(n6175), .B(n6174), .Y(n6177) );
XOR2X4TS U7085 ( .A(n6176), .B(n6177), .Y(FPMULT_Sgf_operation_EVEN1_S_B[10]) );
NOR2X8TS U7086 ( .A(n6179), .B(n6178), .Y(DP_OP_499J248_125_1651_n104) );
INVX4TS U7087 ( .A(DP_OP_499J248_125_1651_n104), .Y(
DP_OP_499J248_125_1651_n170) );
NOR2X8TS U7088 ( .A(n6181), .B(n8690), .Y(n8302) );
NOR2X1TS U7089 ( .A(n3682), .B(n8690), .Y(n6182) );
NAND2X2TS U7090 ( .A(n6183), .B(n9056), .Y(n6187) );
OAI2BB1X4TS U7091 ( .A0N(n2542), .A1N(n6195), .B0(n9746), .Y(n8249) );
NOR2X4TS U7092 ( .A(n8693), .B(n8249), .Y(n6196) );
INVX8TS U7093 ( .A(operation[1]), .Y(n7483) );
NAND2X4TS U7094 ( .A(n7483), .B(operation[2]), .Y(n6463) );
INVX2TS U7095 ( .A(begin_operation), .Y(n6197) );
NOR2X1TS U7096 ( .A(n6463), .B(n6197), .Y(n6202) );
INVX2TS U7097 ( .A(ack_operation), .Y(n6198) );
NOR2X1TS U7098 ( .A(n6463), .B(n6198), .Y(n6201) );
NOR2X1TS U7099 ( .A(n9204), .B(FPMULT_FS_Module_state_reg[0]), .Y(n6200) );
NOR2X1TS U7100 ( .A(n9839), .B(n8690), .Y(n6199) );
OAI22X2TS U7101 ( .A0(n9817), .A1(n6202), .B0(n6201), .B1(n8294), .Y(n8303)
);
AOI21X4TS U7102 ( .A0(n6209), .A1(n6208), .B0(n6207), .Y(
DP_OP_499J248_125_1651_n106) );
INVX2TS U7103 ( .A(n6320), .Y(n6212) );
NAND2X1TS U7104 ( .A(n6212), .B(n6319), .Y(n6217) );
OR2X2TS U7105 ( .A(n6215), .B(n6214), .Y(n6358) );
INVX2TS U7106 ( .A(n6357), .Y(n6216) );
XOR2X1TS U7107 ( .A(n6217), .B(n6321), .Y(n6221) );
ADDFHX2TS U7108 ( .A(n6221), .B(n2599), .CI(n6219), .CO(
DP_OP_499J248_125_1651_n207), .S(DP_OP_499J248_125_1651_n208) );
NOR2X1TS U7109 ( .A(n6226), .B(n6229), .Y(n6232) );
NAND2X1TS U7110 ( .A(n6227), .B(n6232), .Y(n6235) );
AOI21X1TS U7111 ( .A0(n6233), .A1(n6232), .B0(n6231), .Y(n6234) );
INVX2TS U7112 ( .A(n6237), .Y(n6239) );
NAND2X1TS U7113 ( .A(n6239), .B(n6238), .Y(n6241) );
MXI2X4TS U7114 ( .A(n8518), .B(n9376), .S0(n6260), .Y(n1668) );
INVX4TS U7115 ( .A(n1662), .Y(n6245) );
INVX2TS U7116 ( .A(Data_2[9]), .Y(n6246) );
MXI2X4TS U7117 ( .A(n6246), .B(n9374), .S0(n6283), .Y(n1636) );
NOR2X1TS U7118 ( .A(n8810), .B(n8839), .Y(n8838) );
MXI2X4TS U7119 ( .A(n8515), .B(n9694), .S0(n6260), .Y(n1666) );
OR2X2TS U7120 ( .A(n1666), .B(n9701), .Y(n8827) );
NAND2X2TS U7121 ( .A(n1665), .B(n9692), .Y(n8860) );
INVX2TS U7122 ( .A(n8827), .Y(n6249) );
OAI21X1TS U7123 ( .A0(n6249), .A1(n8860), .B0(n8854), .Y(n8828) );
BUFX16TS U7124 ( .A(n8447), .Y(n6279) );
MXI2X4TS U7125 ( .A(n6250), .B(n9747), .S0(n6279), .Y(n1630) );
INVX4TS U7126 ( .A(n1630), .Y(n8818) );
OR2X2TS U7127 ( .A(n8818), .B(n8816), .Y(n8831) );
NOR2X1TS U7128 ( .A(n8818), .B(n6245), .Y(n8840) );
INVX2TS U7129 ( .A(Data_2[7]), .Y(n6252) );
MXI2X4TS U7130 ( .A(n6252), .B(n9384), .S0(n6283), .Y(n1634) );
MXI2X4TS U7131 ( .A(n8525), .B(n9689), .S0(n6260), .Y(n1669) );
MXI2X4TS U7132 ( .A(n6253), .B(n9644), .S0(n6279), .Y(n1628) );
NOR2X1TS U7133 ( .A(n8821), .B(n6245), .Y(n8841) );
OR2X2TS U7134 ( .A(n8821), .B(n8816), .Y(n8823) );
MXI2X4TS U7135 ( .A(n6254), .B(n9380), .S0(n6283), .Y(n1635) );
INVX2TS U7136 ( .A(n1635), .Y(n8811) );
NOR2X1TS U7137 ( .A(n8811), .B(n8805), .Y(n8826) );
INVX2TS U7138 ( .A(Data_2[11]), .Y(n6255) );
MXI2X4TS U7139 ( .A(n6255), .B(n9645), .S0(n6283), .Y(n1638) );
MXI2X4TS U7140 ( .A(n8516), .B(n9711), .S0(n6260), .Y(n1663) );
MXI2X4TS U7141 ( .A(n6256), .B(n9687), .S0(n6279), .Y(n1627) );
INVX4TS U7142 ( .A(n1627), .Y(n8833) );
NOR2X1TS U7143 ( .A(n8833), .B(n8814), .Y(n8835) );
INVX2TS U7144 ( .A(Data_2[4]), .Y(n6257) );
MXI2X4TS U7145 ( .A(n6257), .B(n2808), .S0(n6279), .Y(n1631) );
INVX2TS U7146 ( .A(n1664), .Y(n8834) );
INVX2TS U7147 ( .A(Data_2[10]), .Y(n6258) );
MXI2X2TS U7148 ( .A(n6258), .B(n9706), .S0(n6283), .Y(n1637) );
INVX2TS U7149 ( .A(n1637), .Y(n8825) );
CLKBUFX3TS U7150 ( .A(n9972), .Y(n9824) );
CLKBUFX3TS U7151 ( .A(n9824), .Y(n9823) );
INVX2TS U7152 ( .A(Data_2[6]), .Y(n6259) );
MXI2X4TS U7153 ( .A(n6259), .B(n9688), .S0(n6283), .Y(
DP_OP_496J248_122_3540_n1475) );
AND2X2TS U7154 ( .A(n8812), .B(n8816), .Y(n8819) );
NOR2X2TS U7155 ( .A(n1668), .B(n9683), .Y(n8829) );
INVX2TS U7156 ( .A(Data_1[11]), .Y(n8521) );
MXI2X4TS U7157 ( .A(n8521), .B(n9643), .S0(n6260), .Y(n1670) );
INVX2TS U7158 ( .A(n1670), .Y(n8804) );
INVX2TS U7159 ( .A(Data_2[5]), .Y(n6261) );
OR2X2TS U7160 ( .A(n8807), .B(n8816), .Y(n8836) );
INVX2TS U7161 ( .A(Data_2[2]), .Y(n6263) );
MXI2X1TS U7162 ( .A(n6263), .B(n9460), .S0(n6279), .Y(n6264) );
INVX2TS U7163 ( .A(n9686), .Y(n8845) );
NOR2X1TS U7164 ( .A(n8845), .B(n8814), .Y(n8844) );
BUFX3TS U7165 ( .A(n6440), .Y(n9531) );
BUFX3TS U7166 ( .A(n6265), .Y(n8851) );
CLKBUFX3TS U7167 ( .A(n6265), .Y(n8850) );
INVX4TS U7168 ( .A(n1645), .Y(n6267) );
INVX2TS U7169 ( .A(n8798), .Y(n8474) );
BUFX12TS U7170 ( .A(n8447), .Y(n8445) );
MXI2X4TS U7171 ( .A(n8520), .B(n9699), .S0(n6287), .Y(n1675) );
MXI2X4TS U7172 ( .A(n6271), .B(n9262), .S0(n6279), .Y(n1649) );
INVX4TS U7173 ( .A(n1649), .Y(n8880) );
INVX2TS U7174 ( .A(n8800), .Y(n6272) );
MXI2X4TS U7175 ( .A(n6273), .B(n6272), .S0(n8445), .Y(
DP_OP_497J248_123_1725_n781) );
INVX4TS U7176 ( .A(DP_OP_497J248_123_1725_n781), .Y(n8864) );
NOR2X1TS U7177 ( .A(n8864), .B(n6274), .Y(n8896) );
MXI2X4TS U7178 ( .A(n8577), .B(n9382), .S0(n6287), .Y(n1681) );
MXI2X4TS U7179 ( .A(n6275), .B(n9272), .S0(n6279), .Y(n1647) );
NOR2X1TS U7180 ( .A(n8871), .B(n8879), .Y(n8899) );
INVX2TS U7181 ( .A(Data_2[17]), .Y(n6277) );
INVX2TS U7182 ( .A(FPMULT_Op_MY[17]), .Y(n6276) );
MXI2X4TS U7183 ( .A(n6277), .B(n6276), .S0(n8445), .Y(
DP_OP_497J248_123_1725_n357) );
INVX4TS U7184 ( .A(DP_OP_497J248_123_1725_n357), .Y(n8865) );
MXI2X4TS U7185 ( .A(n8517), .B(n9271), .S0(n6283), .Y(n1672) );
NOR2X1TS U7186 ( .A(n8865), .B(n8870), .Y(n8913) );
MXI2X4TS U7187 ( .A(n6278), .B(n9273), .S0(n6279), .Y(n1648) );
OR2X2TS U7188 ( .A(n8867), .B(n8864), .Y(n8903) );
INVX2TS U7189 ( .A(Data_2[19]), .Y(n6280) );
NAND2X2TS U7190 ( .A(n9700), .B(n6282), .Y(n8908) );
MXI2X4TS U7191 ( .A(n6284), .B(n9381), .S0(n8445), .Y(n1643) );
MXI2X4TS U7192 ( .A(n8519), .B(n9375), .S0(n6287), .Y(n1678) );
MXI2X4TS U7193 ( .A(n8526), .B(n9467), .S0(n6287), .Y(n1680) );
NOR2X1TS U7194 ( .A(n8880), .B(n3627), .Y(n6286) );
NOR2X1TS U7195 ( .A(n8867), .B(n8881), .Y(n6285) );
CMPR32X2TS U7196 ( .A(n9700), .B(n6286), .C(n6285), .CO(n8925), .S(n8926) );
AND2X2TS U7197 ( .A(n8864), .B(n8867), .Y(n8883) );
NOR2BX1TS U7198 ( .AN(n2334), .B(n8918), .Y(n8917) );
OA21X2TS U7199 ( .A0(n8862), .A1(n8914), .B0(n8908), .Y(n8921) );
NOR2X1TS U7200 ( .A(n8880), .B(n8898), .Y(n8907) );
NOR2X1TS U7201 ( .A(n8894), .B(n6274), .Y(n8916) );
NOR2X1TS U7202 ( .A(n6267), .B(n8879), .Y(n8927) );
BUFX3TS U7203 ( .A(n9824), .Y(n9529) );
BUFX3TS U7204 ( .A(n2911), .Y(n9815) );
CLKBUFX3TS U7205 ( .A(n9815), .Y(n9812) );
CLKBUFX3TS U7206 ( .A(n9812), .Y(n9786) );
CLKBUFX3TS U7207 ( .A(n9815), .Y(n9810) );
CLKBUFX3TS U7208 ( .A(n9810), .Y(n9798) );
BUFX3TS U7209 ( .A(n9798), .Y(n9813) );
CLKBUFX3TS U7210 ( .A(n9813), .Y(n9519) );
CLKBUFX3TS U7211 ( .A(n9519), .Y(n8975) );
CLKBUFX3TS U7212 ( .A(n9519), .Y(n8976) );
CLKBUFX3TS U7213 ( .A(n9786), .Y(n9522) );
CLKBUFX3TS U7214 ( .A(n9522), .Y(n8974) );
INVX2TS U7215 ( .A(n6289), .Y(n6291) );
NAND2X1TS U7216 ( .A(n6291), .B(n6290), .Y(n6293) );
XOR2X1TS U7217 ( .A(n6293), .B(n6292), .Y(FPMULT_Sgf_operation_EVEN1_S_B[6])
);
INVX2TS U7218 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[17]), .Y(
DP_OP_499J248_125_1651_n295) );
INVX2TS U7219 ( .A(n6294), .Y(n6295) );
INVX2TS U7220 ( .A(n6307), .Y(n6309) );
XOR2X1TS U7221 ( .A(n6311), .B(n6310), .Y(FPMULT_Sgf_operation_EVEN1_S_B[8])
);
CLKXOR2X2TS U7222 ( .A(n6314), .B(n6313), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[13]) );
INVX2TS U7223 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .Y(
DP_OP_499J248_125_1651_n299) );
NAND2X2TS U7224 ( .A(n6316), .B(n6315), .Y(n6318) );
NOR2X2TS U7225 ( .A(n6325), .B(n6324), .Y(n6407) );
NOR2X1TS U7226 ( .A(n6407), .B(n6405), .Y(n6327) );
OAI21X2TS U7227 ( .A0(n6321), .A1(n6320), .B0(n6319), .Y(n6361) );
NOR2X2TS U7228 ( .A(n6329), .B(n6328), .Y(n6397) );
NOR2X2TS U7229 ( .A(n6331), .B(n6330), .Y(n6399) );
NOR2X2TS U7230 ( .A(n6397), .B(n6399), .Y(n6384) );
NOR2X2TS U7231 ( .A(n6335), .B(n6334), .Y(n6391) );
NAND2X1TS U7232 ( .A(n6384), .B(n6337), .Y(n6339) );
OR2X2TS U7233 ( .A(n6341), .B(n6340), .Y(n6343) );
NAND2X1TS U7234 ( .A(n6341), .B(n6340), .Y(n6342) );
BUFX3TS U7235 ( .A(n6441), .Y(n9811) );
CLKBUFX3TS U7236 ( .A(n9787), .Y(n8973) );
NAND2X1TS U7237 ( .A(n6347), .B(n6346), .Y(n6348) );
AOI21X1TS U7238 ( .A0(n6350), .A1(n6349), .B0(n6348), .Y(n6351) );
NAND2X1TS U7239 ( .A(n6358), .B(n6357), .Y(n6360) );
XNOR2X1TS U7240 ( .A(n6360), .B(n6359), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
NAND2X1TS U7241 ( .A(DP_OP_497J248_123_1725_n781), .B(n1630), .Y(n9032) );
NAND2X2TS U7242 ( .A(n6269), .B(n1627), .Y(n8985) );
NAND2X2TS U7243 ( .A(n6282), .B(n1628), .Y(n8981) );
OAI21X2TS U7244 ( .A0(n8992), .A1(n8985), .B0(n8981), .Y(n8991) );
INVX2TS U7245 ( .A(n8991), .Y(n9004) );
INVX2TS U7246 ( .A(n6361), .Y(n6406) );
XOR2X1TS U7247 ( .A(n6406), .B(n6363), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
NAND2X2TS U7248 ( .A(n9685), .B(n9686), .Y(n8994) );
NOR2X2TS U7249 ( .A(n9685), .B(n9686), .Y(n6412) );
NAND2X2TS U7250 ( .A(n1671), .B(n9692), .Y(n8988) );
INVX2TS U7251 ( .A(n9002), .Y(n9017) );
NOR2X2TS U7252 ( .A(n1673), .B(n6251), .Y(n8989) );
NAND2X2TS U7253 ( .A(n1673), .B(n6251), .Y(n9010) );
OAI21X1TS U7254 ( .A0(n9017), .A1(n8989), .B0(n9010), .Y(n9022) );
NOR2X2TS U7255 ( .A(n2335), .B(n9683), .Y(n8996) );
OAI21X1TS U7256 ( .A0(n8996), .A1(n9010), .B0(n6414), .Y(n9026) );
NOR2X2TS U7257 ( .A(DP_OP_497J248_123_1725_n781), .B(n1630), .Y(n8998) );
NOR2X1TS U7258 ( .A(n9640), .B(DP_OP_497J248_123_1725_n357), .Y(n9008) );
BUFX3TS U7259 ( .A(n9526), .Y(n9030) );
INVX2TS U7260 ( .A(n6397), .Y(n6365) );
NAND2X1TS U7261 ( .A(n6365), .B(n6396), .Y(n6366) );
XOR2X1TS U7262 ( .A(n6398), .B(n6366), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
CMPR32X2TS U7263 ( .A(n1635), .B(n1647), .C(n6367), .CO(n9000), .S(n9001) );
XOR2X1TS U7264 ( .A(n6374), .B(n6375), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
NAND2X2TS U7265 ( .A(n6378), .B(n6377), .Y(DP_OP_496J248_122_3540_n4) );
INVX2TS U7267 ( .A(n6384), .Y(n6380) );
INVX2TS U7268 ( .A(n6388), .Y(n6379) );
OAI21X1TS U7269 ( .A0(n6398), .A1(n6380), .B0(n6379), .Y(n6383) );
INVX2TS U7270 ( .A(n6381), .Y(n6387) );
NAND2X1TS U7271 ( .A(n6387), .B(n6385), .Y(n6382) );
NAND2X1TS U7272 ( .A(n6384), .B(n6387), .Y(n6390) );
INVX2TS U7273 ( .A(n6385), .Y(n6386) );
INVX2TS U7274 ( .A(n6391), .Y(n6393) );
OAI21X1TS U7275 ( .A0(n6398), .A1(n6397), .B0(n6396), .Y(n6403) );
INVX2TS U7276 ( .A(n6399), .Y(n6401) );
NAND2X1TS U7277 ( .A(n6401), .B(n6400), .Y(n6402) );
XNOR2X1TS U7278 ( .A(n6403), .B(n6402), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
OAI21X2TS U7279 ( .A0(n6406), .A1(n6405), .B0(n6404), .Y(n6411) );
XNOR2X1TS U7280 ( .A(n6411), .B(n6410), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
NAND2BX1TS U7281 ( .AN(n1680), .B(n8839), .Y(n9025) );
XNOR2X1TS U7282 ( .A(n1635), .B(n1647), .Y(n9023) );
INVX2TS U7283 ( .A(n6412), .Y(n6413) );
NAND2X1TS U7284 ( .A(n6413), .B(n8994), .Y(n9021) );
INVX2TS U7285 ( .A(n8996), .Y(n6415) );
NAND2X1TS U7286 ( .A(n6415), .B(n6414), .Y(n9020) );
OR2X2TS U7287 ( .A(n1664), .B(n9696), .Y(n8995) );
BUFX3TS U7288 ( .A(n9531), .Y(n9027) );
BUFX3TS U7289 ( .A(n9821), .Y(n9029) );
BUFX3TS U7290 ( .A(n9519), .Y(n9079) );
CLKBUFX2TS U7291 ( .A(n6420), .Y(n9075) );
CLKBUFX2TS U7292 ( .A(n9522), .Y(n9077) );
CLKBUFX3TS U7293 ( .A(n6420), .Y(n9076) );
CLKBUFX2TS U7294 ( .A(n9519), .Y(n9078) );
CLKBUFX3TS U7295 ( .A(n6420), .Y(n9074) );
INVX2TS U7296 ( .A(n1541), .Y(n6421) );
NOR3X1TS U7297 ( .A(n9841), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n6422) );
MXI2X2TS U7298 ( .A(n9695), .B(n3688), .S0(FPMULT_FSM_selector_A), .Y(n7896)
);
OAI21X1TS U7299 ( .A0(FPMULT_FSM_selector_B[1]), .A1(n9712), .B0(n6429), .Y(
n6423) );
MXI2X1TS U7300 ( .A(n9693), .B(n3687), .S0(FPMULT_FSM_selector_A), .Y(n7878)
);
MXI2X1TS U7301 ( .A(n9236), .B(n3686), .S0(FPMULT_FSM_selector_A), .Y(n7881)
);
MXI2X1TS U7302 ( .A(n9223), .B(n3685), .S0(FPMULT_FSM_selector_A), .Y(n7884)
);
MXI2X1TS U7303 ( .A(n9224), .B(n3684), .S0(FPMULT_FSM_selector_A), .Y(n7887)
);
MXI2X1TS U7304 ( .A(n9217), .B(n3683), .S0(FPMULT_FSM_selector_A), .Y(n7890)
);
MXI2X1TS U7305 ( .A(n9703), .B(n9210), .S0(FPMULT_FSM_selector_A), .Y(n6651)
);
MXI2X1TS U7306 ( .A(n9702), .B(n9211), .S0(FPMULT_FSM_selector_A), .Y(n6690)
);
AOI22X1TS U7307 ( .A0(n7758), .A1(FPMULT_Add_result[6]), .B0(
FPMULT_Sgf_normalized_result[5]), .B1(n7494), .Y(n6438) );
AOI2BB2X4TS U7308 ( .B0(n8092), .B1(n1582), .A0N(n2915), .A1N(n9145), .Y(
n6437) );
CLKBUFX2TS U7309 ( .A(n9813), .Y(n9521) );
BUFX3TS U7310 ( .A(n6442), .Y(n9790) );
CLKBUFX3TS U7311 ( .A(n9971), .Y(n9814) );
BUFX3TS U7312 ( .A(n9814), .Y(n9774) );
BUFX3TS U7313 ( .A(n2889), .Y(n9773) );
CLKBUFX3TS U7314 ( .A(n9773), .Y(n9769) );
BUFX3TS U7315 ( .A(n6442), .Y(n9789) );
CLKBUFX3TS U7316 ( .A(n2911), .Y(n9816) );
BUFX3TS U7317 ( .A(n9816), .Y(n9775) );
BUFX3TS U7318 ( .A(n9810), .Y(n9776) );
BUFX3TS U7319 ( .A(n6442), .Y(n9779) );
BUFX3TS U7320 ( .A(n9814), .Y(n9795) );
BUFX3TS U7321 ( .A(n9814), .Y(n9796) );
BUFX3TS U7322 ( .A(n9810), .Y(n9782) );
BUFX3TS U7323 ( .A(n6441), .Y(n9800) );
BUFX3TS U7324 ( .A(n9816), .Y(n9806) );
BUFX3TS U7325 ( .A(n6441), .Y(n9802) );
BUFX3TS U7326 ( .A(n9816), .Y(n9807) );
CLKBUFX3TS U7327 ( .A(n2888), .Y(n8252) );
BUFX3TS U7328 ( .A(n9814), .Y(n9792) );
CLKBUFX3TS U7329 ( .A(n9786), .Y(n9523) );
CLKBUFX3TS U7330 ( .A(n6441), .Y(n9801) );
BUFX3TS U7331 ( .A(n9824), .Y(n9820) );
BUFX3TS U7332 ( .A(n6441), .Y(n9778) );
BUFX3TS U7333 ( .A(n9816), .Y(n9805) );
BUFX3TS U7334 ( .A(n9816), .Y(n9804) );
BUFX3TS U7335 ( .A(n9810), .Y(n9784) );
BUFX3TS U7336 ( .A(n9824), .Y(n9822) );
BUFX3TS U7337 ( .A(n9817), .Y(n9515) );
BUFX3TS U7338 ( .A(n6442), .Y(n9791) );
CLKBUFX3TS U7339 ( .A(n9813), .Y(n9520) );
CLKBUFX3TS U7340 ( .A(n9810), .Y(n9799) );
BUFX3TS U7341 ( .A(n9526), .Y(n9528) );
BUFX3TS U7342 ( .A(n9531), .Y(n9530) );
BUFX3TS U7343 ( .A(n9823), .Y(n9527) );
CLKBUFX3TS U7344 ( .A(n9823), .Y(n9525) );
BUFX3TS U7345 ( .A(n6441), .Y(n9803) );
BUFX3TS U7346 ( .A(n9816), .Y(n9808) );
BUFX3TS U7347 ( .A(n9814), .Y(n9797) );
BUFX3TS U7348 ( .A(n6442), .Y(n9788) );
BUFX3TS U7349 ( .A(n9824), .Y(n9819) );
BUFX3TS U7350 ( .A(n9817), .Y(n9516) );
NOR3X1TS U7351 ( .A(Data_2[22]), .B(Data_2[0]), .C(Data_2[1]), .Y(n9652) );
NOR4X1TS U7352 ( .A(Data_2[14]), .B(Data_2[15]), .C(Data_2[16]), .D(
Data_2[17]), .Y(n9653) );
NOR4X1TS U7353 ( .A(Data_2[18]), .B(Data_2[19]), .C(Data_2[20]), .D(
Data_2[21]), .Y(n9654) );
NOR4X1TS U7354 ( .A(Data_2[2]), .B(Data_2[3]), .C(Data_2[4]), .D(Data_2[5]),
.Y(n9649) );
NOR4X1TS U7355 ( .A(Data_2[10]), .B(Data_2[11]), .C(Data_2[12]), .D(
Data_2[13]), .Y(n9651) );
NOR4X1TS U7356 ( .A(Data_2[6]), .B(Data_2[7]), .C(Data_2[8]), .D(Data_2[9]),
.Y(n9650) );
NOR3X1TS U7357 ( .A(Data_1[0]), .B(Data_1[22]), .C(Data_1[21]), .Y(n6445) );
NOR2X1TS U7358 ( .A(Data_1[20]), .B(Data_1[19]), .Y(n6444) );
NOR2X1TS U7359 ( .A(Data_1[18]), .B(Data_1[17]), .Y(n6443) );
NAND3X1TS U7360 ( .A(n6445), .B(n6444), .C(n6443), .Y(n6456) );
NOR2X1TS U7361 ( .A(Data_1[8]), .B(Data_1[7]), .Y(n6449) );
NOR2X1TS U7362 ( .A(Data_1[6]), .B(Data_1[5]), .Y(n6448) );
NOR2X1TS U7363 ( .A(Data_1[4]), .B(Data_1[3]), .Y(n6447) );
NOR2X1TS U7364 ( .A(Data_1[2]), .B(Data_1[1]), .Y(n6446) );
NAND4X1TS U7365 ( .A(n6449), .B(n6448), .C(n6447), .D(n6446), .Y(n6455) );
NOR2X1TS U7366 ( .A(Data_1[16]), .B(Data_1[15]), .Y(n6453) );
NOR2X1TS U7367 ( .A(Data_1[14]), .B(Data_1[13]), .Y(n6452) );
NOR2X1TS U7368 ( .A(Data_1[12]), .B(Data_1[11]), .Y(n6451) );
NOR2X1TS U7369 ( .A(Data_1[10]), .B(Data_1[9]), .Y(n6450) );
NAND4X1TS U7370 ( .A(n6453), .B(n6452), .C(n6451), .D(n6450), .Y(n6454) );
NOR3X1TS U7371 ( .A(n6456), .B(n6455), .C(n6454), .Y(n9648) );
MXI2X2TS U7372 ( .A(n6457), .B(n9637), .S0(n9636), .Y(n8386) );
OAI2BB1X2TS U7373 ( .A0N(n9563), .A1N(n2472), .B0(n2547), .Y(n1414) );
INVX2TS U7374 ( .A(n1414), .Y(n6458) );
MXI2X1TS U7375 ( .A(n6458), .B(n9969), .S0(operation[2]), .Y(underflow_flag)
);
CLKMX2X2TS U7376 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n2910), .Y(n1430) );
CLKMX2X2TS U7377 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n2910), .Y(n1420) );
CLKMX2X2TS U7378 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n2910), .Y(n1425) );
CLKMX2X2TS U7379 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n2910), .Y(n1445) );
CLKMX2X2TS U7380 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n2910), .Y(n1450) );
CLKMX2X2TS U7381 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n2910), .Y(n1435) );
CLKMX2X2TS U7382 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n2910), .Y(n1455) );
CLKMX2X2TS U7383 ( .A(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B(
FPADDSUB_SIGN_FLAG_NRM), .S0(n2910), .Y(n1359) );
CLKMX2X2TS U7384 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n2910), .Y(n1440) );
INVX4TS U7385 ( .A(operation[2]), .Y(n9970) );
OR2X4TS U7386 ( .A(n7273), .B(n9544), .Y(n7049) );
INVX2TS U7387 ( .A(n8352), .Y(n8731) );
BUFX6TS U7388 ( .A(n8291), .Y(n8278) );
BUFX6TS U7389 ( .A(n8281), .Y(n8277) );
AOI22X1TS U7390 ( .A0(cordic_result[21]), .A1(n8278), .B0(n8277), .B1(
mult_result[21]), .Y(n6464) );
OAI21X1TS U7391 ( .A0(n8731), .A1(n8280), .B0(n6464), .Y(op_result[21]) );
INVX2TS U7392 ( .A(n8353), .Y(n8730) );
AOI22X1TS U7393 ( .A0(cordic_result[20]), .A1(n8278), .B0(n8277), .B1(
mult_result[20]), .Y(n6467) );
OAI21X1TS U7394 ( .A0(n8730), .A1(n8280), .B0(n6467), .Y(op_result[20]) );
BUFX6TS U7395 ( .A(n2545), .Y(n6527) );
NAND2X1TS U7396 ( .A(n6527), .B(n2497), .Y(n6469) );
BUFX4TS U7397 ( .A(n2298), .Y(n6528) );
NAND2X1TS U7398 ( .A(n6528), .B(n2489), .Y(n6468) );
NAND3X1TS U7399 ( .A(n6469), .B(n6468), .C(n9603), .Y(n8399) );
NAND2X1TS U7400 ( .A(n6580), .B(n2468), .Y(n6471) );
BUFX4TS U7401 ( .A(n2298), .Y(n6581) );
NAND2X1TS U7402 ( .A(n6581), .B(n2444), .Y(n6470) );
NAND3X1TS U7403 ( .A(n6471), .B(n6470), .C(n9609), .Y(n8437) );
NAND2X1TS U7404 ( .A(n6580), .B(n2495), .Y(n6473) );
NAND2X1TS U7405 ( .A(n6581), .B(n2498), .Y(n6472) );
NAND3X1TS U7406 ( .A(n6473), .B(n6472), .C(n9600), .Y(n8435) );
BUFX6TS U7407 ( .A(n2545), .Y(n6508) );
NAND2X1TS U7408 ( .A(n6508), .B(n2460), .Y(n6475) );
BUFX4TS U7409 ( .A(n2298), .Y(n6509) );
NAND2X1TS U7410 ( .A(n6509), .B(n2490), .Y(n6474) );
NAND3X1TS U7411 ( .A(n6475), .B(n6474), .C(n9605), .Y(n8415) );
NAND2X1TS U7412 ( .A(n6508), .B(n2504), .Y(n6477) );
NAND2X1TS U7413 ( .A(n6509), .B(n2458), .Y(n6476) );
NAND3X1TS U7414 ( .A(n6477), .B(n6476), .C(n9601), .Y(n8416) );
NAND2X1TS U7415 ( .A(n6580), .B(n2508), .Y(n6479) );
NAND2X1TS U7416 ( .A(n6581), .B(n2475), .Y(n6478) );
NAND3X1TS U7417 ( .A(n6479), .B(n6478), .C(n9589), .Y(n8424) );
NAND2X1TS U7418 ( .A(n6580), .B(n2488), .Y(n6481) );
NAND2X1TS U7419 ( .A(n6581), .B(n2451), .Y(n6480) );
NAND3X1TS U7420 ( .A(n6481), .B(n6480), .C(n9595), .Y(n8439) );
NAND2X1TS U7421 ( .A(n6508), .B(n2501), .Y(n6483) );
NAND2X1TS U7422 ( .A(n6509), .B(n2452), .Y(n6482) );
NAND3X1TS U7423 ( .A(n6483), .B(n6482), .C(n9596), .Y(n8418) );
NAND2X1TS U7424 ( .A(n6527), .B(n2505), .Y(n6485) );
NAND2X1TS U7425 ( .A(n6528), .B(n2453), .Y(n6484) );
NAND3X1TS U7426 ( .A(n6485), .B(n6484), .C(n9591), .Y(n8394) );
NAND2X1TS U7427 ( .A(n6580), .B(n2462), .Y(n6487) );
NAND2X1TS U7428 ( .A(n6581), .B(n2435), .Y(n6486) );
NAND3X1TS U7429 ( .A(n6487), .B(n6486), .C(n9602), .Y(n8434) );
NAND2X1TS U7430 ( .A(n6508), .B(n2493), .Y(n6489) );
NAND2X1TS U7431 ( .A(n6509), .B(n2457), .Y(n6488) );
NAND3X1TS U7432 ( .A(n6489), .B(n6488), .C(n9610), .Y(n8420) );
NAND2X1TS U7433 ( .A(n6508), .B(n2445), .Y(n6491) );
NAND2X1TS U7434 ( .A(n6509), .B(n2471), .Y(n6490) );
NAND3X1TS U7435 ( .A(n6491), .B(n6490), .C(n9614), .Y(n8421) );
NAND2X1TS U7436 ( .A(n6508), .B(n2503), .Y(n6493) );
NAND2X1TS U7437 ( .A(n6509), .B(n2456), .Y(n6492) );
NAND3X1TS U7438 ( .A(n6493), .B(n6492), .C(n9590), .Y(n8397) );
NAND2X1TS U7439 ( .A(n6527), .B(n2442), .Y(n6495) );
NAND2X1TS U7440 ( .A(n6528), .B(n2467), .Y(n6494) );
NAND3X1TS U7441 ( .A(n6495), .B(n6494), .C(n9615), .Y(n8535) );
NAND2X1TS U7442 ( .A(n6527), .B(n2500), .Y(n6497) );
NAND2X1TS U7443 ( .A(n6528), .B(n2431), .Y(n6496) );
NAND3X1TS U7444 ( .A(n6497), .B(n6496), .C(n9586), .Y(n8400) );
NAND2X1TS U7445 ( .A(n6508), .B(n2466), .Y(n6499) );
NAND2X1TS U7446 ( .A(n6509), .B(n2441), .Y(n6498) );
NAND3X1TS U7447 ( .A(n6499), .B(n6498), .C(n9594), .Y(n8414) );
NAND2X1TS U7448 ( .A(n6508), .B(n2467), .Y(n6501) );
NAND2X1TS U7449 ( .A(n6509), .B(n2442), .Y(n6500) );
NAND3X1TS U7450 ( .A(n6501), .B(n6500), .C(n9593), .Y(n8395) );
NAND2X1TS U7451 ( .A(n6527), .B(n2441), .Y(n6503) );
NAND2X1TS U7452 ( .A(n6528), .B(n2466), .Y(n6502) );
NAND3X1TS U7453 ( .A(n6503), .B(n6502), .C(n9613), .Y(n8536) );
NAND2X1TS U7454 ( .A(n6508), .B(n2447), .Y(n6505) );
NAND2X1TS U7455 ( .A(n6509), .B(n2469), .Y(n6504) );
NAND3X1TS U7456 ( .A(n6505), .B(n6504), .C(n9620), .Y(n8417) );
NAND2X1TS U7457 ( .A(n6580), .B(n2434), .Y(n6507) );
NAND2X1TS U7458 ( .A(n6581), .B(n2487), .Y(n6506) );
NAND3X1TS U7459 ( .A(n6507), .B(n6506), .C(n9633), .Y(n8433) );
NAND2X1TS U7460 ( .A(n6508), .B(n2502), .Y(n6511) );
NAND2X1TS U7461 ( .A(n6509), .B(n2492), .Y(n6510) );
NAND3X1TS U7462 ( .A(n6511), .B(n6510), .C(n9626), .Y(n8422) );
NAND2X1TS U7463 ( .A(n6580), .B(n2432), .Y(n6513) );
NAND2X1TS U7464 ( .A(n6581), .B(n2470), .Y(n6512) );
NAND3X1TS U7465 ( .A(n6513), .B(n6512), .C(n9621), .Y(n8432) );
NAND2X1TS U7466 ( .A(n6580), .B(n2455), .Y(n6515) );
NAND2X1TS U7467 ( .A(n6581), .B(n2491), .Y(n6514) );
NAND3X1TS U7468 ( .A(n6515), .B(n6514), .C(n9635), .Y(n8419) );
NAND2X1TS U7469 ( .A(n6527), .B(n2475), .Y(n6517) );
NAND2X1TS U7470 ( .A(n6528), .B(n2508), .Y(n6516) );
NAND3X1TS U7471 ( .A(n6517), .B(n6516), .C(n9634), .Y(n8539) );
NAND2X1TS U7472 ( .A(n6527), .B(n2469), .Y(n6519) );
NAND2X1TS U7473 ( .A(n6528), .B(n2447), .Y(n6518) );
NAND3X1TS U7474 ( .A(n6519), .B(n6518), .C(n9630), .Y(n8532) );
NAND2X1TS U7475 ( .A(n6527), .B(n2444), .Y(n6521) );
NAND2X1TS U7476 ( .A(n6528), .B(n2468), .Y(n6520) );
NAND3X1TS U7477 ( .A(n6521), .B(n6520), .C(n9619), .Y(n8396) );
NAND2X1TS U7478 ( .A(n6527), .B(n2450), .Y(n6523) );
NAND2X1TS U7479 ( .A(n6528), .B(n2459), .Y(n6522) );
NAND3X1TS U7480 ( .A(n6523), .B(n6522), .C(n9628), .Y(n8398) );
NAND2X1TS U7481 ( .A(n6580), .B(n2474), .Y(n6525) );
NAND2X1TS U7482 ( .A(n6581), .B(n2446), .Y(n6524) );
NAND3X1TS U7483 ( .A(n6525), .B(n6524), .C(n9625), .Y(n8436) );
NAND2X1TS U7484 ( .A(n6527), .B(n2459), .Y(n6530) );
NAND2X1TS U7485 ( .A(n6528), .B(n2450), .Y(n6529) );
NAND3X1TS U7486 ( .A(n6530), .B(n6529), .C(n9622), .Y(n8401) );
NAND2X1TS U7487 ( .A(n8378), .B(n2461), .Y(n6534) );
NAND3X1TS U7488 ( .A(n6535), .B(n6534), .C(n9599), .Y(n6610) );
BUFX4TS U7489 ( .A(n2545), .Y(n6557) );
NAND2X1TS U7490 ( .A(n6557), .B(n9551), .Y(n6539) );
NAND2X1TS U7491 ( .A(n6558), .B(n9556), .Y(n6538) );
NAND3X1TS U7492 ( .A(n6539), .B(n6538), .C(n9575), .Y(n8429) );
NAND2X1TS U7493 ( .A(n8378), .B(n2496), .Y(n6541) );
NAND3X2TS U7494 ( .A(n6542), .B(n6541), .C(n9632), .Y(n8553) );
NAND2X1TS U7495 ( .A(n6558), .B(n2500), .Y(n6543) );
NAND3X1TS U7496 ( .A(n6544), .B(n6543), .C(n9578), .Y(n8409) );
NAND2X1TS U7497 ( .A(n6557), .B(n9547), .Y(n6546) );
NAND2X1TS U7498 ( .A(n6558), .B(n9558), .Y(n6545) );
NAND3X1TS U7499 ( .A(n6546), .B(n6545), .C(n9576), .Y(n8428) );
NAND2X1TS U7500 ( .A(n6557), .B(n9548), .Y(n6548) );
NAND2X1TS U7501 ( .A(n6558), .B(n9561), .Y(n6547) );
NAND3X1TS U7502 ( .A(n6548), .B(n6547), .C(n9577), .Y(n8430) );
NAND2X1TS U7503 ( .A(n6558), .B(n2505), .Y(n6549) );
NAND3X1TS U7504 ( .A(n6550), .B(n6549), .C(n9579), .Y(n8408) );
NAND2X1TS U7505 ( .A(n6558), .B(n2445), .Y(n6551) );
NAND3X1TS U7506 ( .A(n6552), .B(n6551), .C(n9581), .Y(n8411) );
NAND3X1TS U7507 ( .A(n6554), .B(n6553), .C(n9582), .Y(n8427) );
NAND2X1TS U7508 ( .A(n6558), .B(n2503), .Y(n6555) );
NAND3X1TS U7509 ( .A(n6556), .B(n6555), .C(n9583), .Y(n8410) );
NAND2X1TS U7510 ( .A(n6558), .B(n2497), .Y(n6559) );
NAND3X1TS U7511 ( .A(n6560), .B(n6559), .C(n9580), .Y(n8413) );
INVX2TS U7512 ( .A(n6561), .Y(n6564) );
NAND2X1TS U7513 ( .A(n8378), .B(n2449), .Y(n6562) );
NAND3X2TS U7514 ( .A(n6563), .B(n6562), .C(n9616), .Y(n8442) );
INVX2TS U7515 ( .A(n6576), .Y(n6565) );
NAND2X1TS U7516 ( .A(n6575), .B(n6565), .Y(n6569) );
NAND2X1TS U7517 ( .A(n8378), .B(n2454), .Y(n6566) );
INVX2TS U7518 ( .A(n8381), .Y(n6568) );
NOR2X2TS U7519 ( .A(n8553), .B(n6568), .Y(n6577) );
XNOR2X1TS U7520 ( .A(n6569), .B(n6577), .Y(n6570) );
MXI2X1TS U7521 ( .A(n6570), .B(n9372), .S0(n8431), .Y(n1478) );
NOR2X1TS U7522 ( .A(n6571), .B(n8381), .Y(n6572) );
NOR2X1TS U7523 ( .A(n6577), .B(n6572), .Y(n6573) );
MXI2X1TS U7524 ( .A(n9368), .B(n6573), .S0(n8441), .Y(n1477) );
CLKMX2X2TS U7525 ( .A(FPMULT_Adder_M_result_A_adder[5]), .B(
FPMULT_Add_result[5]), .S0(n9750), .Y(n1619) );
OAI21X1TS U7526 ( .A0(n6577), .A1(n6576), .B0(n6575), .Y(n6595) );
NAND2X1TS U7527 ( .A(n8377), .B(n2443), .Y(n6579) );
NAND2X1TS U7528 ( .A(n8378), .B(n2465), .Y(n6578) );
NAND3X2TS U7529 ( .A(n6579), .B(n6578), .C(n9611), .Y(n8383) );
XNOR2X1TS U7530 ( .A(n6595), .B(n6584), .Y(n6585) );
MXI2X1TS U7531 ( .A(n6585), .B(n9370), .S0(n8431), .Y(n1479) );
ADDHX1TS U7532 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n6586), .CO(n6588),
.S(n6587) );
BUFX8TS U7533 ( .A(n6747), .Y(n8603) );
CLKMX2X2TS U7534 ( .A(n6587), .B(FPMULT_Add_result[7]), .S0(n8603), .Y(n1617) );
CLKMX2X2TS U7535 ( .A(FPMULT_Adder_M_result_A_adder[3]), .B(
FPMULT_Add_result[3]), .S0(n8603), .Y(n1621) );
ADDHX1TS U7536 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n6588), .CO(n6603),
.S(n6589) );
CLKMX2X2TS U7537 ( .A(n6589), .B(FPMULT_Add_result[8]), .S0(n8603), .Y(n1616) );
XNOR2X1TS U7538 ( .A(n9080), .B(n9081), .Y(n6590) );
NOR2X2TS U7539 ( .A(n9204), .B(n6745), .Y(n6591) );
NOR2X6TS U7540 ( .A(n8468), .B(n6592), .Y(n8459) );
AO22X1TS U7541 ( .A0(n8459), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n8468), .Y(n1515) );
INVX2TS U7542 ( .A(n8383), .Y(n8389) );
INVX2TS U7543 ( .A(n6596), .Y(n6599) );
NAND3X2TS U7544 ( .A(n6598), .B(n6597), .C(n9608), .Y(n8440) );
INVX2TS U7545 ( .A(n6605), .Y(n6600) );
NOR2X1TS U7546 ( .A(n8440), .B(n6599), .Y(n6606) );
NOR2X1TS U7547 ( .A(n6600), .B(n6606), .Y(n6601) );
XOR2X1TS U7548 ( .A(n6607), .B(n6601), .Y(n6602) );
MXI2X1TS U7549 ( .A(n6602), .B(n9371), .S0(n8431), .Y(n1480) );
ADDHX1TS U7550 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n6603), .CO(n8463),
.S(n6604) );
CLKMX2X2TS U7551 ( .A(n6604), .B(FPMULT_Add_result[9]), .S0(n8603), .Y(n1615) );
OAI21X1TS U7552 ( .A0(n6607), .A1(n6606), .B0(n6605), .Y(n6612) );
NAND2X1TS U7553 ( .A(n8378), .B(n2448), .Y(n6608) );
NAND3X2TS U7554 ( .A(n6609), .B(n6608), .C(n9606), .Y(n8426) );
XOR2X1TS U7555 ( .A(n8426), .B(n6610), .Y(n6611) );
XOR2X1TS U7556 ( .A(n6612), .B(n6611), .Y(n6613) );
NAND2X1TS U7557 ( .A(n8303), .B(FPMULT_FS_Module_state_reg[2]), .Y(n6616) );
NAND2X1TS U7558 ( .A(n9838), .B(n6745), .Y(n6615) );
NAND4X2TS U7559 ( .A(n6616), .B(n9843), .C(n8468), .D(n6615), .Y(n1692) );
INVX2TS U7560 ( .A(n1692), .Y(n9539) );
AO22X1TS U7561 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[9]), .B0(
mult_result[9]), .B1(n6617), .Y(n1506) );
AO22X1TS U7562 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[7]), .B0(
mult_result[7]), .B1(n6617), .Y(n1508) );
AO22X1TS U7563 ( .A0(n8469), .A1(FPMULT_Sgf_normalized_result[17]), .B0(
mult_result[17]), .B1(n6617), .Y(n1498) );
AO22X1TS U7564 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[3]), .B0(
mult_result[3]), .B1(n8466), .Y(n1512) );
AO22X1TS U7565 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n8466), .Y(n1514) );
AO22X1TS U7566 ( .A0(n8469), .A1(FPMULT_Sgf_normalized_result[12]), .B0(
mult_result[12]), .B1(n6617), .Y(n1503) );
AO22X1TS U7567 ( .A0(n8469), .A1(FPMULT_Sgf_normalized_result[18]), .B0(
mult_result[18]), .B1(n8468), .Y(n1497) );
AO22X1TS U7568 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[6]), .B0(
mult_result[6]), .B1(n8466), .Y(n1509) );
AO22X1TS U7569 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[4]), .B0(
mult_result[4]), .B1(n8466), .Y(n1511) );
AO22X1TS U7570 ( .A0(n8469), .A1(FPMULT_Sgf_normalized_result[14]), .B0(
mult_result[14]), .B1(n6617), .Y(n1501) );
AO22X1TS U7571 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[2]), .B0(
mult_result[2]), .B1(n8466), .Y(n1513) );
AO22X1TS U7572 ( .A0(n8469), .A1(FPMULT_Sgf_normalized_result[13]), .B0(
mult_result[13]), .B1(n6617), .Y(n1502) );
AO22X1TS U7573 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[8]), .B0(
mult_result[8]), .B1(n6617), .Y(n1507) );
AO22X1TS U7574 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[10]), .B0(
mult_result[10]), .B1(n6617), .Y(n1505) );
AO22X1TS U7575 ( .A0(n8469), .A1(FPMULT_Sgf_normalized_result[11]), .B0(
mult_result[11]), .B1(n6617), .Y(n1504) );
OAI21X1TS U7576 ( .A0(n7259), .A1(DP_OP_26J248_126_1325_n28), .B0(n7260),
.Y(n1352) );
NAND2X1TS U7577 ( .A(n8342), .B(FPADDSUB_left_right_SHT2), .Y(n6618) );
NOR2X4TS U7578 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n9275),
.Y(n8311) );
INVX2TS U7579 ( .A(n8311), .Y(n8462) );
NAND2X2TS U7580 ( .A(n6619), .B(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.Y(n8310) );
NAND2X1TS U7581 ( .A(n8462), .B(n8310), .Y(n2193) );
NAND2X1TS U7582 ( .A(n9099), .B(FPSENCOS_cont_iter_out[0]), .Y(intadd_734_CI) );
NOR2X2TS U7583 ( .A(n8783), .B(FPSENCOS_cont_iter_out[0]), .Y(n8584) );
INVX2TS U7584 ( .A(intadd_734_CI), .Y(n6621) );
BUFX12TS U7585 ( .A(n8507), .Y(n8607) );
MXI2X1TS U7586 ( .A(n6621), .B(FPSENCOS_d_ff3_sh_x_out[23]), .S0(n8607), .Y(
n6622) );
OAI2BB1X1TS U7587 ( .A0N(FPSENCOS_d_ff2_X[23]), .A1N(n8584), .B0(n6622), .Y(
n1953) );
NAND2X1TS U7588 ( .A(n9098), .B(FPSENCOS_cont_iter_out[0]), .Y(intadd_733_CI) );
INVX2TS U7589 ( .A(intadd_733_CI), .Y(n6623) );
MXI2X1TS U7590 ( .A(n6623), .B(FPSENCOS_d_ff3_sh_y_out[23]), .S0(n8607), .Y(
n6624) );
OAI2BB1X1TS U7591 ( .A0N(FPSENCOS_d_ff2_Y[23]), .A1N(n8584), .B0(n6624), .Y(
n1855) );
NAND2X1TS U7592 ( .A(n8790), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n6626) );
NOR2X4TS U7593 ( .A(n9274), .B(FPSENCOS_cont_iter_out[2]), .Y(n8781) );
NOR2X2TS U7594 ( .A(n3639), .B(FPSENCOS_cont_iter_out[3]), .Y(n8788) );
NOR2X1TS U7595 ( .A(n8781), .B(n8788), .Y(n6625) );
NAND3X1TS U7596 ( .A(n8323), .B(n6626), .C(n6631), .Y(n2122) );
OR2X4TS U7597 ( .A(n8675), .B(FPSENCOS_cont_iter_out[1]), .Y(n8238) );
NAND2X2TS U7598 ( .A(n8789), .B(n8583), .Y(n6629) );
NAND2X1TS U7599 ( .A(n8783), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n6627) );
NAND3X1TS U7600 ( .A(n6629), .B(n6631), .C(n6627), .Y(n2132) );
INVX2TS U7601 ( .A(n8788), .Y(n6638) );
NAND2X2TS U7602 ( .A(n6639), .B(n6638), .Y(n8234) );
NAND2X2TS U7603 ( .A(n8784), .B(n8234), .Y(n8611) );
NAND2X1TS U7604 ( .A(n8783), .B(FPSENCOS_d_ff3_LUT_out[9]), .Y(n6628) );
NAND3X1TS U7605 ( .A(n6629), .B(n8611), .C(n6628), .Y(n2126) );
NAND2X1TS U7606 ( .A(n8790), .B(FPSENCOS_d_ff3_LUT_out[1]), .Y(n6630) );
NAND3X1TS U7607 ( .A(n6632), .B(n6631), .C(n6630), .Y(n2134) );
AND2X8TS U7608 ( .A(n3709), .B(n6678), .Y(n6635) );
AO22X1TS U7609 ( .A0(n8600), .A1(FPSENCOS_d_ff_Xn[9]), .B0(
FPSENCOS_d_ff2_X[9]), .B1(n6636), .Y(n1989) );
AO22X2TS U7610 ( .A0(n8600), .A1(FPSENCOS_d_ff_Xn[22]), .B0(
FPSENCOS_d_ff2_X[22]), .B1(n8601), .Y(n1963) );
AO22X2TS U7611 ( .A0(n8600), .A1(FPSENCOS_d_ff_Xn[21]), .B0(
FPSENCOS_d_ff2_X[21]), .B1(n6636), .Y(n1965) );
AO22X2TS U7612 ( .A0(n6634), .A1(FPSENCOS_d_ff_Xn[18]), .B0(
FPSENCOS_d_ff2_X[18]), .B1(n8599), .Y(n1971) );
AO22X1TS U7613 ( .A0(n6634), .A1(FPSENCOS_d_ff_Yn[16]), .B0(
FPSENCOS_d_ff2_Y[16]), .B1(n8233), .Y(n1877) );
AO22X1TS U7614 ( .A0(n6634), .A1(FPSENCOS_d_ff_Yn[12]), .B0(
FPSENCOS_d_ff2_Y[12]), .B1(n6636), .Y(n1885) );
AO22X1TS U7615 ( .A0(n6637), .A1(FPSENCOS_d_ff_Xn[0]), .B0(
FPSENCOS_d_ff2_X[0]), .B1(n8599), .Y(n2007) );
AO22X1TS U7616 ( .A0(n6637), .A1(FPSENCOS_d_ff_Xn[15]), .B0(
FPSENCOS_d_ff2_X[15]), .B1(n6636), .Y(n1977) );
AO22X1TS U7617 ( .A0(n8591), .A1(FPSENCOS_d_ff_Yn[1]), .B0(
FPSENCOS_d_ff2_Y[1]), .B1(n8592), .Y(n1907) );
AO22X1TS U7618 ( .A0(n6688), .A1(FPSENCOS_d_ff_Yn[21]), .B0(
FPSENCOS_d_ff2_Y[21]), .B1(n8592), .Y(n1867) );
AO22X1TS U7619 ( .A0(n8591), .A1(FPSENCOS_d_ff_Yn[31]), .B0(
FPSENCOS_d_ff2_Y[31]), .B1(n8599), .Y(n1847) );
AO22X1TS U7620 ( .A0(n8591), .A1(FPSENCOS_d_ff_Yn[25]), .B0(
FPSENCOS_d_ff2_Y[25]), .B1(n8601), .Y(n1861) );
AO22X1TS U7621 ( .A0(n8591), .A1(FPSENCOS_d_ff_Yn[29]), .B0(
FPSENCOS_d_ff2_Y[29]), .B1(n8601), .Y(n1857) );
AO22X1TS U7622 ( .A0(n8591), .A1(FPSENCOS_d_ff_Yn[27]), .B0(
FPSENCOS_d_ff2_Y[27]), .B1(n8601), .Y(n1859) );
AO22X2TS U7623 ( .A0(n8600), .A1(FPSENCOS_d_ff_Yn[24]), .B0(
FPSENCOS_d_ff2_Y[24]), .B1(n8601), .Y(n1862) );
NOR2X1TS U7624 ( .A(n8349), .B(n3630), .Y(n8320) );
NAND2X2TS U7625 ( .A(n6644), .B(n6638), .Y(n8509) );
AOI22X1TS U7626 ( .A0(n8784), .A1(n8509), .B0(FPSENCOS_d_ff3_LUT_out[0]),
.B1(n8790), .Y(n6641) );
INVX2TS U7627 ( .A(n6639), .Y(n6640) );
NAND2X2TS U7628 ( .A(n8789), .B(n6640), .Y(n6645) );
XNOR2X1TS U7629 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(sub_x_17_n206), .Y(
n6643) );
AOI22X1TS U7630 ( .A0(n8704), .A1(FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n8703), .Y(n6642) );
INVX2TS U7631 ( .A(n6644), .Y(n8609) );
AOI22X1TS U7632 ( .A0(n8784), .A1(n8609), .B0(FPSENCOS_d_ff3_LUT_out[10]),
.B1(n8790), .Y(n6646) );
AND2X8TS U7633 ( .A(n2834), .B(n9843), .Y(n9840) );
CMPR32X2TS U7634 ( .A(n6652), .B(n6651), .C(n6650), .CO(n7889), .S(n7893) );
XNOR2X1TS U7635 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[1]), .B(
FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n6653) );
AND2X4TS U7636 ( .A(n6656), .B(n6654), .Y(n6671) );
NAND2X1TS U7637 ( .A(n8654), .B(FPSENCOS_d_ff_Xn[0]), .Y(n6658) );
AOI22X1TS U7638 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[20]), .B0(n6675), .B1(
cordic_result[20]), .Y(n6660) );
OAI2BB1X1TS U7639 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[20]), .B0(n6660), .Y(
n1708) );
AOI22X1TS U7640 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[29]), .B0(n6675), .B1(
cordic_result[29]), .Y(n6661) );
OAI2BB1X1TS U7641 ( .A0N(n8679), .A1N(FPSENCOS_d_ff_Yn[29]), .B0(n6661), .Y(
n1699) );
AOI22X1TS U7642 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[24]), .B0(n6675), .B1(
cordic_result[24]), .Y(n6662) );
OAI2BB1X1TS U7643 ( .A0N(n8679), .A1N(FPSENCOS_d_ff_Yn[24]), .B0(n6662), .Y(
n1704) );
AOI22X1TS U7644 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[26]), .B0(n6675), .B1(
cordic_result[26]), .Y(n6663) );
OAI2BB1X1TS U7645 ( .A0N(n8679), .A1N(FPSENCOS_d_ff_Yn[26]), .B0(n6663), .Y(
n1702) );
AOI22X1TS U7646 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[25]), .B0(n6675), .B1(
cordic_result[25]), .Y(n6664) );
OAI2BB1X1TS U7647 ( .A0N(n8679), .A1N(FPSENCOS_d_ff_Yn[25]), .B0(n6664), .Y(
n1703) );
AOI22X1TS U7648 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[28]), .B0(n6675), .B1(
cordic_result[28]), .Y(n6665) );
OAI2BB1X1TS U7649 ( .A0N(n8679), .A1N(FPSENCOS_d_ff_Yn[28]), .B0(n6665), .Y(
n1700) );
AOI22X1TS U7650 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[27]), .B0(n6675), .B1(
cordic_result[27]), .Y(n6666) );
OAI2BB1X1TS U7651 ( .A0N(n8679), .A1N(FPSENCOS_d_ff_Yn[27]), .B0(n6666), .Y(
n1701) );
AOI22X1TS U7652 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[21]), .B0(n6675), .B1(
cordic_result[21]), .Y(n6667) );
OAI2BB1X1TS U7653 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[21]), .B0(n6667), .Y(
n1707) );
AOI22X1TS U7654 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[23]), .B0(n6675), .B1(
cordic_result[23]), .Y(n6668) );
OAI2BB1X1TS U7655 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[23]), .B0(n6668), .Y(
n1705) );
AOI22X1TS U7656 ( .A0(n8654), .A1(FPSENCOS_d_ff_Xn[3]), .B0(n8653), .B1(
cordic_result[3]), .Y(n6669) );
OAI2BB1X1TS U7657 ( .A0N(n6671), .A1N(FPSENCOS_d_ff_Yn[3]), .B0(n6669), .Y(
n1725) );
AOI22X1TS U7658 ( .A0(n8654), .A1(FPSENCOS_d_ff_Xn[2]), .B0(n8653), .B1(
cordic_result[2]), .Y(n6670) );
OAI2BB1X1TS U7659 ( .A0N(n6671), .A1N(FPSENCOS_d_ff_Yn[2]), .B0(n6670), .Y(
n1726) );
BUFX12TS U7660 ( .A(n8326), .Y(n8643) );
AOI22X1TS U7661 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[13]), .B0(n8643), .B1(
n2923), .Y(n6672) );
OAI2BB1X1TS U7662 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[13]), .B0(n6672), .Y(
n1715) );
AOI22X1TS U7663 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[19]), .B0(n8643), .B1(
n2924), .Y(n6673) );
OAI2BB1X1TS U7664 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[19]), .B0(n6673), .Y(
n1709) );
AOI22X1TS U7665 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[12]), .B0(n8643), .B1(
n2922), .Y(n6674) );
OAI2BB1X1TS U7666 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[12]), .B0(n6674), .Y(
n1716) );
AOI22X1TS U7667 ( .A0(n6676), .A1(FPSENCOS_d_ff_Xn[22]), .B0(n6675), .B1(
n2925), .Y(n6677) );
OAI2BB1X1TS U7668 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[22]), .B0(n6677), .Y(
n1706) );
INVX2TS U7669 ( .A(n6678), .Y(n6679) );
AOI2BB2X1TS U7670 ( .B0(FPSENCOS_d_ff2_Z[28]), .B1(n8660), .A0N(n8664),
.A1N(n3615), .Y(n6680) );
OAI2BB1X1TS U7671 ( .A0N(n6688), .A1N(FPSENCOS_d_ff_Zn[28]), .B0(n6680), .Y(
n1738) );
AOI2BB2X1TS U7672 ( .B0(FPSENCOS_d_ff2_Z[7]), .B1(n8667), .A0N(n8226), .A1N(
n3593), .Y(n6681) );
AOI2BB2X1TS U7673 ( .B0(FPSENCOS_d_ff2_Z[24]), .B1(n8660), .A0N(n8664),
.A1N(n3609), .Y(n6682) );
OAI2BB1X1TS U7674 ( .A0N(n6688), .A1N(FPSENCOS_d_ff_Zn[24]), .B0(n6682), .Y(
n1742) );
AOI2BB2X1TS U7675 ( .B0(FPSENCOS_d_ff2_Z[8]), .B1(n8667), .A0N(n8226), .A1N(
n3600), .Y(n6683) );
AOI2BB2X1TS U7676 ( .B0(FPSENCOS_d_ff2_Z[25]), .B1(n8660), .A0N(n8664),
.A1N(n3610), .Y(n6684) );
OAI2BB1X1TS U7677 ( .A0N(n6688), .A1N(FPSENCOS_d_ff_Zn[25]), .B0(n6684), .Y(
n1741) );
AOI2BB2X1TS U7678 ( .B0(FPSENCOS_d_ff2_Z[29]), .B1(n8660), .A0N(n8664),
.A1N(n3617), .Y(n6685) );
AOI2BB2X1TS U7679 ( .B0(FPSENCOS_d_ff2_Z[27]), .B1(n8667), .A0N(n8664),
.A1N(n3611), .Y(n6686) );
OAI2BB1X1TS U7680 ( .A0N(n6688), .A1N(FPSENCOS_d_ff_Zn[27]), .B0(n6686), .Y(
n1739) );
AOI2BB2X1TS U7681 ( .B0(FPSENCOS_d_ff2_Z[26]), .B1(n8660), .A0N(n8664),
.A1N(n3574), .Y(n6687) );
OAI2BB1X1TS U7682 ( .A0N(n6688), .A1N(FPSENCOS_d_ff_Zn[26]), .B0(n6687), .Y(
n1740) );
MXI2X1TS U7683 ( .A(n8703), .B(n9127), .S0(n8779), .Y(n2146) );
OAI2BB1X1TS U7684 ( .A0N(n6696), .A1N(n5023), .B0(n6695), .Y(n6700) );
NAND2X1TS U7685 ( .A(n6698), .B(n6697), .Y(n6699) );
XNOR2X1TS U7686 ( .A(n6700), .B(n6699), .Y(n6701) );
INVX2TS U7687 ( .A(n6702), .Y(n6718) );
AOI21X1TS U7688 ( .A0(n6718), .A1(n2480), .B0(n6703), .Y(n6709) );
INVX2TS U7689 ( .A(n6708), .Y(n6704) );
NAND2X1TS U7690 ( .A(n6704), .B(n6707), .Y(n6705) );
XOR2X1TS U7691 ( .A(n6709), .B(n6705), .Y(n6706) );
OAI21X1TS U7692 ( .A0(n6709), .A1(n6708), .B0(n6707), .Y(n6714) );
INVX2TS U7693 ( .A(n6710), .Y(n6712) );
NAND2X1TS U7694 ( .A(n6712), .B(n6711), .Y(n6713) );
XNOR2X1TS U7695 ( .A(n6714), .B(n6713), .Y(n6715) );
AOI21X1TS U7696 ( .A0(n6718), .A1(n9051), .B0(n9052), .Y(n6716) );
XOR2X1TS U7697 ( .A(n6716), .B(n9049), .Y(n6717) );
XNOR2X1TS U7698 ( .A(n6718), .B(n9053), .Y(n6719) );
XNOR2X1TS U7699 ( .A(n9072), .B(n9073), .Y(n6720) );
XOR2X1TS U7700 ( .A(n9067), .B(n9068), .Y(n6721) );
CLKMX2X2TS U7701 ( .A(n6721), .B(n9554), .S0(n9553), .Y(n9276) );
INVX2TS U7702 ( .A(n6726), .Y(n6722) );
NAND2X1TS U7703 ( .A(n6722), .B(n6725), .Y(n6723) );
XOR2X1TS U7704 ( .A(n6727), .B(n6723), .Y(n6724) );
OAI21X1TS U7705 ( .A0(n6727), .A1(n6726), .B0(n6725), .Y(n6732) );
INVX2TS U7706 ( .A(n6728), .Y(n6730) );
NAND2X1TS U7707 ( .A(n6730), .B(n6729), .Y(n6731) );
XNOR2X1TS U7708 ( .A(n6732), .B(n6731), .Y(n6733) );
NOR4X1TS U7709 ( .A(n1569), .B(n1568), .C(n9276), .D(n2945), .Y(n6736) );
NAND4X1TS U7710 ( .A(n6737), .B(n6736), .C(n6735), .D(n6734), .Y(n6741) );
NAND2X1TS U7711 ( .A(n6739), .B(n6738), .Y(n6740) );
OR2X2TS U7712 ( .A(n6741), .B(n6740), .Y(n6743) );
CLKXOR2X2TS U7713 ( .A(FPMULT_Op_MX[31]), .B(FPMULT_Op_MY[31]), .Y(n8387) );
OAI21X1TS U7714 ( .A0(n8387), .A1(r_mode[0]), .B0(r_mode[1]), .Y(n6742) );
INVX2TS U7715 ( .A(n6744), .Y(n8688) );
NAND2X1TS U7716 ( .A(n8688), .B(n6745), .Y(n6746) );
OAI21X1TS U7717 ( .A0(n8689), .A1(n6746), .B0(n9219), .Y(n1690) );
NAND3X1TS U7718 ( .A(n8114), .B(n6752), .C(FPADDSUB_Raw_mant_NRM_SWR[1]),
.Y(n6762) );
NOR2X1TS U7719 ( .A(n6754), .B(n6753), .Y(n8116) );
NOR3X1TS U7720 ( .A(n8116), .B(n6757), .C(n6758), .Y(n6761) );
INVX2TS U7721 ( .A(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n7708) );
NAND2X2TS U7722 ( .A(n3661), .B(sub_x_17_n206), .Y(n8702) );
NOR2X1TS U7723 ( .A(n3658), .B(FPADDSUB_DMP_SFG[0]), .Y(n6766) );
NAND2X1TS U7724 ( .A(n3658), .B(FPADDSUB_DMP_SFG[0]), .Y(n6765) );
INVX2TS U7725 ( .A(n6798), .Y(n6776) );
NAND2X2TS U7726 ( .A(sub_x_17_n251), .B(FPADDSUB_DMP_SFG[1]), .Y(n6794) );
OAI21X1TS U7727 ( .A0(n6776), .A1(n6792), .B0(n6794), .Y(n6769) );
INVX2TS U7728 ( .A(n6812), .Y(n6767) );
NAND2X1TS U7729 ( .A(n6767), .B(n6814), .Y(n6770) );
INVX2TS U7730 ( .A(n6770), .Y(n6768) );
XNOR2X1TS U7731 ( .A(n6769), .B(n6768), .Y(n6773) );
NOR2X1TS U7732 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n6777) );
NAND2X1TS U7733 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n8700) );
NAND2X1TS U7734 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n6778) );
OAI21X1TS U7735 ( .A0(n6777), .A1(n8700), .B0(n6778), .Y(n6818) );
INVX2TS U7736 ( .A(n6818), .Y(n6801) );
XOR2X1TS U7737 ( .A(n6801), .B(n6770), .Y(n6771) );
AOI22X1TS U7738 ( .A0(n6771), .A1(n8704), .B0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.B1(n7412), .Y(n6772) );
OAI2BB1X1TS U7739 ( .A0N(n7416), .A1N(n6773), .B0(n6772), .Y(n1347) );
INVX2TS U7740 ( .A(n6792), .Y(n6774) );
NAND2X1TS U7741 ( .A(n6774), .B(n6794), .Y(n6775) );
XOR2X1TS U7742 ( .A(n6776), .B(n6775), .Y(n6783) );
INVX2TS U7743 ( .A(n6777), .Y(n6779) );
NAND2X1TS U7744 ( .A(n6779), .B(n6778), .Y(n6780) );
XOR2X1TS U7745 ( .A(n6780), .B(n8700), .Y(n6781) );
AOI22X1TS U7746 ( .A0(n6781), .A1(n8704), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n7412), .Y(n6782) );
OAI2BB1X1TS U7747 ( .A0N(n7416), .A1N(n6783), .B0(n6782), .Y(n1348) );
AOI22X1TS U7748 ( .A0(n6786), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n6785),
.B1(n6784), .Y(n6787) );
NAND2X1TS U7749 ( .A(n6788), .B(n6787), .Y(n6790) );
OAI21X1TS U7750 ( .A0(n8337), .A1(n9301), .B0(n8339), .Y(n6791) );
CLKMX2X2TS U7751 ( .A(n6791), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .S0(n8123),
.Y(n1332) );
NOR2X1TS U7752 ( .A(n3677), .B(FPADDSUB_DMP_SFG[2]), .Y(n6795) );
NOR2X1TS U7753 ( .A(n6792), .B(n6795), .Y(n6797) );
NAND2X1TS U7754 ( .A(n3677), .B(FPADDSUB_DMP_SFG[2]), .Y(n6793) );
OAI21X1TS U7755 ( .A0(n6795), .A1(n6794), .B0(n6793), .Y(n6796) );
INVX2TS U7756 ( .A(n6815), .Y(n6799) );
NAND2X1TS U7757 ( .A(n6799), .B(n6813), .Y(n6802) );
INVX2TS U7758 ( .A(n6802), .Y(n6800) );
XNOR2X1TS U7759 ( .A(n6844), .B(n6800), .Y(n6806) );
OAI21X1TS U7760 ( .A0(n6801), .A1(n6812), .B0(n6814), .Y(n6803) );
XNOR2X1TS U7761 ( .A(n6803), .B(n6802), .Y(n6804) );
AOI22X1TS U7762 ( .A0(n6804), .A1(n8704), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.B1(n8703), .Y(n6805) );
OAI2BB1X1TS U7763 ( .A0N(n7416), .A1N(n6806), .B0(n6805), .Y(n1346) );
NAND2X2TS U7764 ( .A(FPSENCOS_cont_var_out[1]), .B(ready_add_subt), .Y(n6807) );
NOR2X1TS U7765 ( .A(n3671), .B(FPADDSUB_DMP_SFG[3]), .Y(n6826) );
INVX2TS U7766 ( .A(n6826), .Y(n6809) );
INVX2TS U7767 ( .A(n6828), .Y(n6808) );
AOI21X1TS U7768 ( .A0(n6844), .A1(n6809), .B0(n6808), .Y(n6811) );
INVX2TS U7769 ( .A(n6848), .Y(n6834) );
NAND2X1TS U7770 ( .A(n6834), .B(n6850), .Y(n6819) );
INVX2TS U7771 ( .A(n6819), .Y(n6810) );
XOR2X1TS U7772 ( .A(n6811), .B(n6810), .Y(n6822) );
NOR2X1TS U7773 ( .A(n6812), .B(n6815), .Y(n6817) );
OAI21X1TS U7774 ( .A0(n6815), .A1(n6814), .B0(n6813), .Y(n6816) );
AOI21X1TS U7775 ( .A0(n6818), .A1(n6817), .B0(n6816), .Y(n6895) );
INVX2TS U7776 ( .A(n6895), .Y(n6876) );
XNOR2X1TS U7777 ( .A(n6876), .B(n6819), .Y(n6820) );
AOI22X1TS U7778 ( .A0(n6820), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n7412), .Y(n6821) );
OAI2BB1X1TS U7779 ( .A0N(n6992), .A1N(n6822), .B0(n6821), .Y(n1345) );
NAND2X1TS U7780 ( .A(n6823), .B(FPSENCOS_cont_var_out[1]), .Y(n6824) );
OAI21X1TS U7781 ( .A0(n6825), .A1(n7484), .B0(n6824), .Y(n2138) );
NOR2X1TS U7782 ( .A(n3674), .B(FPADDSUB_DMP_SFG[4]), .Y(n6829) );
NAND2X1TS U7783 ( .A(n3674), .B(FPADDSUB_DMP_SFG[4]), .Y(n6827) );
INVX2TS U7784 ( .A(n6851), .Y(n6830) );
NAND2X2TS U7785 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6849) );
NAND2X1TS U7786 ( .A(n6830), .B(n6849), .Y(n6835) );
INVX2TS U7787 ( .A(n6835), .Y(n6831) );
XOR2X1TS U7788 ( .A(n6832), .B(n6831), .Y(n6839) );
INVX2TS U7789 ( .A(n6850), .Y(n6833) );
AOI21X1TS U7790 ( .A0(n6876), .A1(n6834), .B0(n6833), .Y(n6836) );
XOR2X1TS U7791 ( .A(n6836), .B(n6835), .Y(n6837) );
AOI22X1TS U7792 ( .A0(n6837), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.B1(n7412), .Y(n6838) );
OAI2BB1X1TS U7793 ( .A0N(n7416), .A1N(n6839), .B0(n6838), .Y(n1344) );
NOR2X2TS U7794 ( .A(n3672), .B(FPADDSUB_DMP_SFG[5]), .Y(n6859) );
NAND2X1TS U7795 ( .A(n3672), .B(FPADDSUB_DMP_SFG[5]), .Y(n6862) );
OAI21X1TS U7796 ( .A0(n6841), .A1(n6859), .B0(n6862), .Y(n6842) );
AOI21X1TS U7797 ( .A0(n6844), .A1(n6843), .B0(n6842), .Y(n6847) );
INVX2TS U7798 ( .A(n6885), .Y(n6845) );
NAND2X1TS U7799 ( .A(n6845), .B(n6888), .Y(n6852) );
INVX2TS U7800 ( .A(n6852), .Y(n6846) );
XOR2X1TS U7801 ( .A(n6847), .B(n6846), .Y(n6856) );
AOI21X1TS U7802 ( .A0(n6876), .A1(n6886), .B0(n6892), .Y(n6853) );
XOR2X1TS U7803 ( .A(n6853), .B(n6852), .Y(n6854) );
AOI22X1TS U7804 ( .A0(n6854), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[8]),
.B1(n7412), .Y(n6855) );
OAI2BB1X1TS U7805 ( .A0N(n7416), .A1N(n6856), .B0(n6855), .Y(n1343) );
MXI2X1TS U7806 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[0]), .S0(n7055), .Y(n6857) );
INVX2TS U7807 ( .A(n7300), .Y(n6990) );
AOI21X1TS U7808 ( .A0(FPADDSUB_Data_array_SWR[25]), .A1(n7264), .B0(n7101),
.Y(n6858) );
NOR2X1TS U7809 ( .A(n3668), .B(FPADDSUB_DMP_SFG[6]), .Y(n6863) );
NOR2X1TS U7810 ( .A(n6859), .B(n6863), .Y(n6865) );
NAND2X1TS U7811 ( .A(n3668), .B(FPADDSUB_DMP_SFG[6]), .Y(n6861) );
OAI21X1TS U7812 ( .A0(n6863), .A1(n6862), .B0(n6861), .Y(n6864) );
AOI21X1TS U7813 ( .A0(n6866), .A1(n6865), .B0(n6864), .Y(n6867) );
INVX2TS U7814 ( .A(n6889), .Y(n6870) );
NAND2X1TS U7815 ( .A(n6870), .B(n6887), .Y(n6877) );
INVX2TS U7816 ( .A(n6877), .Y(n6871) );
XOR2X1TS U7817 ( .A(n7070), .B(n6871), .Y(n6881) );
NOR2X1TS U7818 ( .A(n6872), .B(n6885), .Y(n6875) );
INVX2TS U7819 ( .A(n6892), .Y(n6873) );
OAI21X1TS U7820 ( .A0(n6873), .A1(n6885), .B0(n6888), .Y(n6874) );
AOI21X1TS U7821 ( .A0(n6876), .A1(n6875), .B0(n6874), .Y(n6878) );
XOR2X1TS U7822 ( .A(n6878), .B(n6877), .Y(n6879) );
AOI22X1TS U7823 ( .A0(n6879), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[9]),
.B1(n7412), .Y(n6880) );
OAI2BB1X1TS U7824 ( .A0N(n6992), .A1N(n6881), .B0(n6880), .Y(n1342) );
NOR2X1TS U7825 ( .A(n3666), .B(FPADDSUB_DMP_SFG[7]), .Y(n6933) );
OAI21X1TS U7826 ( .A0(n7070), .A1(n6933), .B0(n6935), .Y(n6884) );
INVX2TS U7827 ( .A(n6984), .Y(n6882) );
NAND2X1TS U7828 ( .A(n6882), .B(n6983), .Y(n6896) );
INVX2TS U7829 ( .A(n6896), .Y(n6883) );
XNOR2X1TS U7830 ( .A(n6884), .B(n6883), .Y(n6899) );
NOR2X2TS U7831 ( .A(n6885), .B(n6889), .Y(n6891) );
NAND2X1TS U7832 ( .A(n6886), .B(n6891), .Y(n6894) );
OAI21X1TS U7833 ( .A0(n6889), .A1(n6888), .B0(n6887), .Y(n6890) );
AOI21X1TS U7834 ( .A0(n6892), .A1(n6891), .B0(n6890), .Y(n6893) );
XOR2X1TS U7835 ( .A(n7147), .B(n6896), .Y(n6897) );
AOI22X1TS U7836 ( .A0(n6897), .A1(n8704), .B0(FPADDSUB_Raw_mant_NRM_SWR[10]),
.B1(n8703), .Y(n6898) );
NOR2X2TS U7837 ( .A(n6997), .B(n7024), .Y(n7135) );
NOR2X2TS U7838 ( .A(n7140), .B(n7131), .Y(n6903) );
NAND2X1TS U7839 ( .A(n7135), .B(n6903), .Y(n6905) );
NOR2X1TS U7840 ( .A(n7029), .B(n6905), .Y(n6907) );
OAI21X1TS U7841 ( .A0(n6957), .A1(n6963), .B0(n6958), .Y(n6900) );
OAI21X1TS U7842 ( .A0(n7131), .A1(n7139), .B0(n7132), .Y(n6902) );
AOI21X1TS U7843 ( .A0(n7138), .A1(n6903), .B0(n6902), .Y(n6904) );
OAI21X1TS U7844 ( .A0(n7030), .A1(n6905), .B0(n6904), .Y(n6906) );
NOR2X2TS U7845 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n7345) );
NOR2X2TS U7846 ( .A(n7446), .B(n7458), .Y(n6911) );
NAND2X2TS U7847 ( .A(n7463), .B(n6911), .Y(n7430) );
NOR2X1TS U7848 ( .A(n7361), .B(n7377), .Y(n7404) );
NAND2X1TS U7849 ( .A(n7404), .B(n7426), .Y(n6914) );
NAND2X2TS U7850 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n7340) );
OAI21X1TS U7851 ( .A0(n7458), .A1(n7464), .B0(n7459), .Y(n6910) );
OAI21X1TS U7852 ( .A0(n7377), .A1(n7383), .B0(n7378), .Y(n7405) );
NAND2X1TS U7853 ( .A(n7425), .B(add_x_18_n35), .Y(n6912) );
AOI21X1TS U7854 ( .A0(n7405), .A1(n7426), .B0(n6912), .Y(n6913) );
OAI21X1TS U7855 ( .A0(n6909), .A1(n7410), .B0(n6915), .Y(n6916) );
NAND2X1TS U7856 ( .A(n6918), .B(n8340), .Y(n6923) );
NOR2X2TS U7857 ( .A(n7264), .B(n7259), .Y(n8343) );
AOI22X1TS U7858 ( .A0(n8343), .A1(FPADDSUB_Shift_amount_SHT1_EWR[3]), .B0(
FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n7264), .Y(n6922) );
NAND2X2TS U7859 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[12]), .Y(n7100) );
INVX2TS U7860 ( .A(n7100), .Y(n6919) );
NAND2X1TS U7861 ( .A(n8340), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n6926) );
NAND2X1TS U7862 ( .A(n8123), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n6924) );
INVX2TS U7863 ( .A(n7253), .Y(n7298) );
AOI2BB2X1TS U7864 ( .B0(FPADDSUB_Data_array_SWR[23]), .B1(n8342), .A0N(n7315), .A1N(n7298), .Y(n6932) );
NAND2X1TS U7865 ( .A(n8340), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n6929) );
NAND2X1TS U7866 ( .A(n7101), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n6928) );
NAND2X1TS U7867 ( .A(n8123), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n6927) );
NAND3X2TS U7868 ( .A(n6929), .B(n6928), .C(n6927), .Y(n7301) );
INVX2TS U7869 ( .A(n7301), .Y(n6930) );
AOI2BB2X1TS U7870 ( .B0(n7329), .B1(n7300), .A0N(n8127), .A1N(n6930), .Y(
n6931) );
NAND2X2TS U7871 ( .A(n6932), .B(n6931), .Y(n1812) );
NOR2X1TS U7872 ( .A(n3662), .B(FPADDSUB_DMP_SFG[9]), .Y(n6951) );
INVX2TS U7873 ( .A(n6951), .Y(n6938) );
NAND2X1TS U7874 ( .A(n6974), .B(n6938), .Y(n6940) );
NAND2X1TS U7875 ( .A(n3665), .B(FPADDSUB_DMP_SFG[8]), .Y(n6934) );
NAND2X2TS U7876 ( .A(n3662), .B(FPADDSUB_DMP_SFG[9]), .Y(n6953) );
INVX2TS U7877 ( .A(n6953), .Y(n6937) );
AOI21X1TS U7878 ( .A0(n6975), .A1(n6938), .B0(n6937), .Y(n6939) );
OAI21X1TS U7879 ( .A0(n7070), .A1(n6940), .B0(n6939), .Y(n6943) );
INVX2TS U7880 ( .A(n6941), .Y(n6965) );
NAND2X1TS U7881 ( .A(n6965), .B(n6963), .Y(n6946) );
INVX2TS U7882 ( .A(n6946), .Y(n6942) );
XNOR2X1TS U7883 ( .A(n6943), .B(n6942), .Y(n6950) );
INVX2TS U7884 ( .A(n6962), .Y(n6945) );
INVX2TS U7885 ( .A(n6966), .Y(n6944) );
OAI21X1TS U7886 ( .A0(n7147), .A1(n6945), .B0(n6944), .Y(n6947) );
XNOR2X1TS U7887 ( .A(n6947), .B(n6946), .Y(n6948) );
AOI22X1TS U7888 ( .A0(n6948), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[12]),
.B1(n7412), .Y(n6949) );
OAI2BB1X1TS U7889 ( .A0N(n6992), .A1N(n6950), .B0(n6949), .Y(n1339) );
NOR2X1TS U7890 ( .A(n6951), .B(n6954), .Y(n6956) );
NAND2X1TS U7891 ( .A(n6974), .B(n6956), .Y(n7117) );
INVX2TS U7892 ( .A(n6957), .Y(n6959) );
NAND2X1TS U7893 ( .A(n6959), .B(n6958), .Y(n6969) );
INVX2TS U7894 ( .A(n6969), .Y(n6960) );
XNOR2X1TS U7895 ( .A(n6961), .B(n6960), .Y(n6973) );
NAND2X1TS U7896 ( .A(n6962), .B(n6965), .Y(n6968) );
INVX2TS U7897 ( .A(n6963), .Y(n6964) );
AOI21X1TS U7898 ( .A0(n6966), .A1(n6965), .B0(n6964), .Y(n6967) );
OAI21X1TS U7899 ( .A0(n7147), .A1(n6968), .B0(n6967), .Y(n6970) );
XNOR2X1TS U7900 ( .A(n6970), .B(n6969), .Y(n6971) );
AOI22X1TS U7901 ( .A0(n6971), .A1(n8704), .B0(FPADDSUB_Raw_mant_NRM_SWR[13]),
.B1(n8703), .Y(n6972) );
INVX2TS U7902 ( .A(n6974), .Y(n6977) );
INVX2TS U7903 ( .A(n6975), .Y(n6976) );
OAI21X1TS U7904 ( .A0(n7070), .A1(n6977), .B0(n6976), .Y(n6982) );
INVX2TS U7905 ( .A(n6978), .Y(n6980) );
NAND2X1TS U7906 ( .A(n6980), .B(n6979), .Y(n6985) );
INVX2TS U7907 ( .A(n6985), .Y(n6981) );
XNOR2X1TS U7908 ( .A(n6982), .B(n6981), .Y(n6989) );
OAI21X1TS U7909 ( .A0(n7147), .A1(n6984), .B0(n6983), .Y(n6986) );
XNOR2X1TS U7910 ( .A(n6986), .B(n6985), .Y(n6987) );
AOI22X1TS U7911 ( .A0(n6987), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[11]),
.B1(n7412), .Y(n6988) );
OAI2BB1X1TS U7912 ( .A0N(n6992), .A1N(n6989), .B0(n6988), .Y(n1340) );
INVX2TS U7913 ( .A(n7117), .Y(n7063) );
NOR2X1TS U7914 ( .A(n9475), .B(FPADDSUB_DMP_SFG[11]), .Y(n7018) );
INVX2TS U7915 ( .A(n7018), .Y(n6994) );
NAND2X1TS U7916 ( .A(n7063), .B(n6994), .Y(n6996) );
INVX2TS U7917 ( .A(n7020), .Y(n6993) );
AOI21X1TS U7918 ( .A0(n7067), .A1(n6994), .B0(n6993), .Y(n6995) );
OAI21X1TS U7919 ( .A0(n7070), .A1(n6996), .B0(n6995), .Y(n6999) );
INVX2TS U7920 ( .A(n6997), .Y(n7033) );
NAND2X1TS U7921 ( .A(n7033), .B(n7031), .Y(n7000) );
INVX2TS U7922 ( .A(n7000), .Y(n6998) );
XNOR2X1TS U7923 ( .A(n6999), .B(n6998), .Y(n7004) );
OAI21X1TS U7924 ( .A0(n7147), .A1(n7029), .B0(n7030), .Y(n7001) );
XNOR2X1TS U7925 ( .A(n7001), .B(n7000), .Y(n7002) );
AOI22X1TS U7926 ( .A0(n7002), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[14]),
.B1(n8703), .Y(n7003) );
OAI2BB1X1TS U7927 ( .A0N(n7475), .A1N(n7004), .B0(n7003), .Y(n1337) );
INVX2TS U7928 ( .A(n7309), .Y(n7081) );
OAI22X1TS U7929 ( .A0(n7326), .A1(n7081), .B0(n9299), .B1(n2687), .Y(n7017)
);
NAND2X1TS U7930 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[9]), .Y(n7007) );
NAND2X1TS U7931 ( .A(n7055), .B(FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n7006) );
NAND2X1TS U7932 ( .A(n7212), .B(FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n7005) );
NAND3X2TS U7933 ( .A(n7007), .B(n7006), .C(n7005), .Y(n7082) );
NAND2X1TS U7934 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n7010) );
NAND2X1TS U7935 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n7009) );
NAND2X1TS U7936 ( .A(n7212), .B(FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n7008) );
NAND3X2TS U7937 ( .A(n7010), .B(n7009), .C(n7008), .Y(n7307) );
INVX2TS U7938 ( .A(n7307), .Y(n7054) );
AOI2BB2X1TS U7939 ( .B0(n7329), .B1(n7082), .A0N(n8127), .A1N(n7054), .Y(
n7016) );
NAND2X1TS U7940 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n7014) );
NAND2X1TS U7941 ( .A(n7055), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n7013) );
NAND2X1TS U7942 ( .A(n2909), .B(FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n7012) );
NAND3X2TS U7943 ( .A(n7014), .B(n7013), .C(n7012), .Y(n7225) );
NAND3BX2TS U7944 ( .AN(n7017), .B(n7016), .C(n7015), .Y(n1796) );
NOR2X1TS U7945 ( .A(n3663), .B(FPADDSUB_DMP_SFG[12]), .Y(n7021) );
NOR2X2TS U7946 ( .A(n7018), .B(n7021), .Y(n7116) );
NAND2X1TS U7947 ( .A(n7063), .B(n7116), .Y(n7023) );
NAND2X1TS U7948 ( .A(n3663), .B(FPADDSUB_DMP_SFG[12]), .Y(n7019) );
AOI21X1TS U7949 ( .A0(n7067), .A1(n7116), .B0(n7123), .Y(n7022) );
OAI21X1TS U7950 ( .A0(n7070), .A1(n7023), .B0(n7022), .Y(n7028) );
INVX2TS U7951 ( .A(n7024), .Y(n7026) );
NAND2X1TS U7952 ( .A(n7026), .B(n7025), .Y(n7036) );
INVX2TS U7953 ( .A(n7036), .Y(n7027) );
XNOR2X1TS U7954 ( .A(n7028), .B(n7027), .Y(n7041) );
INVX2TS U7955 ( .A(n7029), .Y(n7137) );
NAND2X1TS U7956 ( .A(n7137), .B(n7033), .Y(n7035) );
INVX2TS U7957 ( .A(n7031), .Y(n7032) );
AOI21X1TS U7958 ( .A0(n7144), .A1(n7033), .B0(n7032), .Y(n7034) );
OAI21X1TS U7959 ( .A0(n7147), .A1(n7035), .B0(n7034), .Y(n7037) );
XNOR2X1TS U7960 ( .A(n7037), .B(n7036), .Y(n7039) );
AOI22X1TS U7961 ( .A0(n7039), .A1(n7038), .B0(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B1(n2648), .Y(n7040) );
INVX2TS U7962 ( .A(n7086), .Y(n7239) );
OA22X2TS U7963 ( .A0(n7239), .A1(n7042), .B0(n7043), .B1(n7315), .Y(n7048)
);
AOI22X1TS U7964 ( .A0(n8129), .A1(n7242), .B0(FPADDSUB_Data_array_SWR[2]),
.B1(n7264), .Y(n7047) );
NAND2X2TS U7965 ( .A(n8131), .B(n7045), .Y(n7046) );
NAND2X1TS U7966 ( .A(n6459), .B(n9572), .Y(n7051) );
NAND2X1TS U7967 ( .A(n7204), .B(n9574), .Y(n7050) );
NAND4X2TS U7968 ( .A(n7051), .B(n7050), .C(n6460), .D(n9664), .Y(n8493) );
INVX2TS U7969 ( .A(n8493), .Y(n8745) );
MXI2X1TS U7970 ( .A(n9347), .B(n8745), .S0(n8762), .Y(n2009) );
OR2X4TS U7971 ( .A(n7273), .B(n9543), .Y(n7165) );
INVX4TS U7972 ( .A(n7165), .Y(n7194) );
NAND2X1TS U7973 ( .A(n7194), .B(n2524), .Y(n7052) );
INVX2TS U7974 ( .A(n8561), .Y(n8729) );
MXI2X1TS U7975 ( .A(n9348), .B(n8729), .S0(n8762), .Y(n2048) );
NAND2X1TS U7976 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n7058) );
NAND2X1TS U7977 ( .A(n7055), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n7057) );
NAND2X1TS U7978 ( .A(n2909), .B(FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n7056) );
NAND3X2TS U7979 ( .A(n7058), .B(n7057), .C(n7056), .Y(n7226) );
AOI22X1TS U7980 ( .A0(n7308), .A1(n7226), .B0(n7044), .B1(n7225), .Y(n7060)
);
INVX2TS U7981 ( .A(n7082), .Y(n7224) );
AOI2BB2X1TS U7982 ( .B0(FPADDSUB_Data_array_SWR[8]), .B1(n7264), .A0N(n7042),
.A1N(n7224), .Y(n7059) );
NAND3BX2TS U7983 ( .AN(n7061), .B(n7060), .C(n7059), .Y(n1797) );
INVX2TS U7984 ( .A(n7116), .Y(n7062) );
NOR2X2TS U7985 ( .A(n3664), .B(FPADDSUB_DMP_SFG[13]), .Y(n7115) );
NOR2X1TS U7986 ( .A(n7062), .B(n7115), .Y(n7066) );
NAND2X1TS U7987 ( .A(n7066), .B(n7063), .Y(n7069) );
INVX2TS U7988 ( .A(n7123), .Y(n7064) );
NAND2X1TS U7989 ( .A(n3664), .B(FPADDSUB_DMP_SFG[13]), .Y(n7119) );
AOI21X1TS U7990 ( .A0(n7067), .A1(n7066), .B0(n7065), .Y(n7068) );
OAI21X1TS U7991 ( .A0(n7070), .A1(n7069), .B0(n7068), .Y(n7073) );
INVX2TS U7992 ( .A(n7140), .Y(n7071) );
NAND2X1TS U7993 ( .A(n7071), .B(n7139), .Y(n7076) );
INVX2TS U7994 ( .A(n7076), .Y(n7072) );
XNOR2X1TS U7995 ( .A(n7073), .B(n7072), .Y(n7080) );
NAND2X1TS U7996 ( .A(n7137), .B(n7135), .Y(n7075) );
OAI21X1TS U7997 ( .A0(n7147), .A1(n7075), .B0(n7074), .Y(n7077) );
XNOR2X1TS U7998 ( .A(n7077), .B(n7076), .Y(n7078) );
AOI22X1TS U7999 ( .A0(n7078), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[16]),
.B1(n2835), .Y(n7079) );
INVX2TS U8000 ( .A(n7241), .Y(n7305) );
OAI22X1TS U8001 ( .A0(n8125), .A1(n7305), .B0(n9389), .B1(n7322), .Y(n7085)
);
AOI2BB2X1TS U8002 ( .B0(n7329), .B1(n7307), .A0N(n8127), .A1N(n7081), .Y(
n7084) );
NAND3BX2TS U8003 ( .AN(n7085), .B(n7084), .C(n7083), .Y(n1795) );
NAND2X1TS U8004 ( .A(n8129), .B(n7086), .Y(n7091) );
AOI22X1TS U8005 ( .A0(n8340), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n7264),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n7088) );
NAND2X1TS U8006 ( .A(n7211), .B(FPADDSUB_Raw_mant_NRM_SWR[12]), .Y(n7094) );
NAND2X1TS U8007 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n7093) );
NAND2X1TS U8008 ( .A(n8123), .B(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n7092) );
NAND3X2TS U8009 ( .A(n7094), .B(n7093), .C(n7092), .Y(n8130) );
INVX2TS U8010 ( .A(n8130), .Y(n7219) );
OAI22X1TS U8011 ( .A0(n7326), .A1(n7219), .B0(n9300), .B1(n2687), .Y(n7107)
);
NAND2X1TS U8012 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n7097) );
NAND2X1TS U8013 ( .A(n7211), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(n7096) );
NAND2X1TS U8014 ( .A(n8123), .B(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n7095) );
NAND2X1TS U8015 ( .A(n7101), .B(FPADDSUB_Raw_mant_NRM_SWR[13]), .Y(n7099) );
NAND2X1TS U8016 ( .A(n8123), .B(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n7098) );
NAND3X2TS U8017 ( .A(n7100), .B(n7099), .C(n7098), .Y(n8128) );
INVX2TS U8018 ( .A(n8128), .Y(n7108) );
AOI2BB2X1TS U8019 ( .B0(n7308), .B1(n7208), .A0N(n7042), .A1N(n7108), .Y(
n7106) );
NAND2X1TS U8020 ( .A(n7101), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n7104) );
NAND2X1TS U8021 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n7103) );
NAND2X1TS U8022 ( .A(n8123), .B(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n7102) );
NAND3X2TS U8023 ( .A(n7104), .B(n7103), .C(n7102), .Y(n7220) );
NAND3BX2TS U8024 ( .AN(n7107), .B(n7106), .C(n7105), .Y(n1801) );
OAI22X1TS U8025 ( .A0(n8125), .A1(n7108), .B0(n9390), .B1(n7322), .Y(n7114)
);
NAND2X1TS U8026 ( .A(n7211), .B(FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n7111) );
NAND2X1TS U8027 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[9]), .Y(n7110) );
NAND2X1TS U8028 ( .A(n2909), .B(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n7109) );
INVX2TS U8029 ( .A(n7220), .Y(n7209) );
AOI2BB2X1TS U8030 ( .B0(n7317), .B1(n7263), .A0N(n8127), .A1N(n7209), .Y(
n7113) );
NAND3BX2TS U8031 ( .AN(n7114), .B(n7113), .C(n7112), .Y(n1802) );
NOR2X1TS U8032 ( .A(n3667), .B(FPADDSUB_DMP_SFG[14]), .Y(n7120) );
NOR2X1TS U8033 ( .A(n7115), .B(n7120), .Y(n7122) );
NAND2X1TS U8034 ( .A(n7116), .B(n7122), .Y(n7125) );
NOR2X1TS U8035 ( .A(n7117), .B(n7125), .Y(n7128) );
NAND2X1TS U8036 ( .A(n3667), .B(FPADDSUB_DMP_SFG[14]), .Y(n7118) );
AOI21X1TS U8037 ( .A0(n7123), .A1(n7122), .B0(n7121), .Y(n7124) );
OAI21X1TS U8038 ( .A0(n7126), .A1(n7125), .B0(n7124), .Y(n7127) );
INVX2TS U8039 ( .A(n7131), .Y(n7133) );
NAND2X1TS U8040 ( .A(n7133), .B(n7132), .Y(n7148) );
INVX2TS U8041 ( .A(n7148), .Y(n7134) );
XOR2X1TS U8042 ( .A(n7130), .B(n7134), .Y(n7152) );
INVX2TS U8043 ( .A(n7135), .Y(n7136) );
NOR2X1TS U8044 ( .A(n7136), .B(n7140), .Y(n7143) );
NAND2X1TS U8045 ( .A(n7143), .B(n7137), .Y(n7146) );
AOI21X1TS U8046 ( .A0(n7144), .A1(n7143), .B0(n7142), .Y(n7145) );
OAI21X1TS U8047 ( .A0(n7147), .A1(n7146), .B0(n7145), .Y(n7149) );
XNOR2X1TS U8048 ( .A(n7149), .B(n7148), .Y(n7150) );
AOI22X1TS U8049 ( .A0(n7150), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n2835), .Y(n7151) );
OAI2BB1X1TS U8050 ( .A0N(n7475), .A1N(n7152), .B0(n7151), .Y(n1334) );
NAND2X1TS U8051 ( .A(n7211), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n7155) );
NAND2X1TS U8052 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n7154) );
NAND2X1TS U8053 ( .A(n8123), .B(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n7153) );
NAND3X2TS U8054 ( .A(n7155), .B(n7154), .C(n7153), .Y(n7318) );
INVX2TS U8055 ( .A(n7318), .Y(n7248) );
OAI22X1TS U8056 ( .A0(n8125), .A1(n7248), .B0(n9393), .B1(n7322), .Y(n7164)
);
NAND2X1TS U8057 ( .A(n7156), .B(FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n7159) );
NAND2X1TS U8058 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n7158) );
NAND2X1TS U8059 ( .A(n2909), .B(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n7157) );
NAND3X2TS U8060 ( .A(n7159), .B(n7158), .C(n7157), .Y(n7252) );
NAND2X2TS U8061 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n8336) );
NAND2X1TS U8062 ( .A(n7211), .B(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n7161) );
NAND2X1TS U8063 ( .A(n7212), .B(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n7160) );
INVX2TS U8064 ( .A(n7316), .Y(n7254) );
NAND3BX2TS U8065 ( .AN(n7164), .B(n7163), .C(n7162), .Y(n1809) );
INVX4TS U8066 ( .A(n7165), .Y(n7201) );
NAND2X1TS U8067 ( .A(n7201), .B(n2530), .Y(n7168) );
NOR2X4TS U8068 ( .A(n7273), .B(n9560), .Y(n7197) );
NAND2X1TS U8069 ( .A(n7197), .B(n2531), .Y(n7167) );
INVX2TS U8070 ( .A(n8565), .Y(n8732) );
MXI2X1TS U8071 ( .A(n9359), .B(n8732), .S0(n7272), .Y(n2066) );
NAND2X1TS U8072 ( .A(n7201), .B(n2532), .Y(n7170) );
NAND2X1TS U8073 ( .A(n7197), .B(n2529), .Y(n7169) );
INVX2TS U8074 ( .A(n8562), .Y(n8744) );
MXI2X1TS U8075 ( .A(n9362), .B(n8744), .S0(n7272), .Y(n2069) );
INVX2TS U8076 ( .A(n8351), .Y(n8747) );
MXI2X1TS U8077 ( .A(n9360), .B(n8747), .S0(n7272), .Y(n2021) );
NAND2X1TS U8078 ( .A(n7194), .B(n2511), .Y(n7174) );
NAND2X1TS U8079 ( .A(n7197), .B(n2512), .Y(n7173) );
INVX2TS U8080 ( .A(n8563), .Y(n8746) );
MXI2X1TS U8081 ( .A(n9363), .B(n8746), .S0(n7272), .Y(n2072) );
NAND2X1TS U8082 ( .A(n7194), .B(n2527), .Y(n7176) );
NAND2X1TS U8083 ( .A(n7197), .B(n2528), .Y(n7175) );
INVX2TS U8084 ( .A(n8508), .Y(n8735) );
MXI2X1TS U8085 ( .A(n9330), .B(n8735), .S0(n7272), .Y(n2075) );
INVX2TS U8086 ( .A(n8350), .Y(n8724) );
MXI2X1TS U8087 ( .A(n9361), .B(n8724), .S0(n7272), .Y(n2018) );
INVX2TS U8088 ( .A(n8492), .Y(n8722) );
MXI2X1TS U8089 ( .A(n9358), .B(n8722), .S0(n7272), .Y(n2033) );
NAND2X1TS U8090 ( .A(n7201), .B(n2537), .Y(n7182) );
NAND2X1TS U8091 ( .A(n7197), .B(n2526), .Y(n7181) );
INVX2TS U8092 ( .A(n8564), .Y(n8733) );
MXI2X1TS U8093 ( .A(n9364), .B(n8733), .S0(n7272), .Y(n2060) );
INVX2TS U8094 ( .A(n8556), .Y(n8727) );
MXI2X1TS U8095 ( .A(n9356), .B(n8727), .S0(n7275), .Y(n2024) );
NAND2X1TS U8096 ( .A(n7194), .B(n2534), .Y(n7186) );
NAND2X1TS U8097 ( .A(n7197), .B(n2535), .Y(n7185) );
INVX2TS U8098 ( .A(n8581), .Y(n8723) );
MXI2X1TS U8099 ( .A(n9351), .B(n8723), .S0(n7275), .Y(n2054) );
INVX2TS U8100 ( .A(n8558), .Y(n8721) );
MXI2X1TS U8101 ( .A(n9354), .B(n8721), .S0(n7275), .Y(n2027) );
NAND2X1TS U8102 ( .A(n7197), .B(n2510), .Y(n7190) );
INVX2TS U8103 ( .A(n8580), .Y(n8719) );
MXI2X1TS U8104 ( .A(n9355), .B(n8719), .S0(n7275), .Y(n2063) );
NAND2X1TS U8105 ( .A(n7201), .B(n2522), .Y(n7192) );
INVX2TS U8106 ( .A(n8557), .Y(n8717) );
MXI2X1TS U8107 ( .A(n9350), .B(n8717), .S0(n7275), .Y(n2051) );
NAND2X1TS U8108 ( .A(n7194), .B(n2523), .Y(n7195) );
INVX2TS U8109 ( .A(n8559), .Y(n8720) );
MXI2X1TS U8110 ( .A(n9357), .B(n8720), .S0(n7275), .Y(n2036) );
NAND2X1TS U8111 ( .A(n7201), .B(n2536), .Y(n7200) );
NAND2X1TS U8112 ( .A(n7197), .B(n2533), .Y(n7199) );
INVX2TS U8113 ( .A(n8579), .Y(n8725) );
MXI2X1TS U8114 ( .A(n9349), .B(n8725), .S0(n7275), .Y(n2057) );
NAND2X1TS U8115 ( .A(n7201), .B(n2525), .Y(n7202) );
INVX2TS U8116 ( .A(n8560), .Y(n8726) );
MXI2X1TS U8117 ( .A(n9353), .B(n8726), .S0(n7275), .Y(n2039) );
INVX2TS U8118 ( .A(n8555), .Y(n8718) );
MXI2X1TS U8119 ( .A(n9352), .B(n8718), .S0(n7275), .Y(n2030) );
OAI21X1TS U8120 ( .A0(n8758), .A1(n7207), .B0(n8675), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
INVX2TS U8121 ( .A(n7208), .Y(n7258) );
NOR2X2TS U8122 ( .A(n7324), .B(n7258), .Y(n7218) );
NAND2X1TS U8123 ( .A(n7210), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n7215) );
NAND2X1TS U8124 ( .A(n7211), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n7214) );
NAND2X1TS U8125 ( .A(n7212), .B(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n7213) );
AOI22X1TS U8126 ( .A0(n7317), .A1(n7268), .B0(FPADDSUB_Data_array_SWR[14]),
.B1(n8342), .Y(n7216) );
NAND3BX1TS U8127 ( .AN(n7218), .B(n7217), .C(n7216), .Y(n1803) );
INVX2TS U8128 ( .A(n7226), .Y(n8126) );
OAI22X1TS U8129 ( .A0(n7326), .A1(n8126), .B0(n9263), .B1(n2687), .Y(n7223)
);
AOI2BB2X1TS U8130 ( .B0(n8129), .B1(n7220), .A0N(n8127), .A1N(n7219), .Y(
n7222) );
NAND3BX2TS U8131 ( .AN(n7223), .B(n7222), .C(n7221), .Y(n1800) );
OAI22X1TS U8132 ( .A0(n8125), .A1(n7224), .B0(n9386), .B1(n7322), .Y(n7229)
);
INVX2TS U8133 ( .A(n7225), .Y(n8124) );
AOI2BB2X1TS U8134 ( .B0(n7308), .B1(n8130), .A0N(n8127), .A1N(n8124), .Y(
n7228) );
NAND3BX2TS U8135 ( .AN(n7229), .B(n7228), .C(n7227), .Y(n1798) );
NOR2X1TS U8136 ( .A(n3669), .B(FPADDSUB_DMP_SFG[15]), .Y(n7333) );
NAND2X1TS U8137 ( .A(n3669), .B(FPADDSUB_DMP_SFG[15]), .Y(n7335) );
OAI21X1TS U8138 ( .A0(n7130), .A1(n7333), .B0(n7335), .Y(n7232) );
INVX2TS U8139 ( .A(n7345), .Y(n7230) );
NAND2X1TS U8140 ( .A(n7230), .B(n7344), .Y(n7233) );
INVX2TS U8141 ( .A(n7233), .Y(n7231) );
XNOR2X1TS U8142 ( .A(n7232), .B(n7231), .Y(n7237) );
XOR2X1TS U8143 ( .A(n6909), .B(n7233), .Y(n7235) );
AOI22X1TS U8144 ( .A0(n7235), .A1(n7234), .B0(FPADDSUB_Raw_mant_NRM_SWR[18]),
.B1(n7412), .Y(n7236) );
OAI2BB1X1TS U8145 ( .A0N(n7416), .A1N(n7237), .B0(n7236), .Y(n1333) );
MXI2X1TS U8146 ( .A(n9365), .B(n8730), .S0(n7238), .Y(n2015) );
MXI2X1TS U8147 ( .A(n9366), .B(n8731), .S0(n7238), .Y(n2012) );
NAND2X2TS U8148 ( .A(n2547), .B(n9534), .Y(n8549) );
INVX2TS U8149 ( .A(n8549), .Y(n8754) );
MXI2X1TS U8150 ( .A(n9440), .B(n8754), .S0(n8762), .Y(n1784) );
NAND2X2TS U8151 ( .A(n2547), .B(n9533), .Y(n8551) );
INVX2TS U8152 ( .A(n8551), .Y(n8743) );
MXI2X1TS U8153 ( .A(n9441), .B(n8743), .S0(n8762), .Y(n1787) );
NAND2X2TS U8154 ( .A(n2547), .B(n9555), .Y(n8697) );
INVX2TS U8155 ( .A(n8697), .Y(n8751) );
MXI2X1TS U8156 ( .A(n9437), .B(n8751), .S0(n8762), .Y(n1775) );
NAND2X2TS U8157 ( .A(n2547), .B(n9535), .Y(n8547) );
INVX2TS U8158 ( .A(n8547), .Y(n8750) );
MXI2X1TS U8159 ( .A(n9439), .B(n8750), .S0(n8762), .Y(n1781) );
NAND2X2TS U8160 ( .A(n2547), .B(n9559), .Y(n8714) );
INVX2TS U8161 ( .A(n8714), .Y(n8748) );
MXI2X1TS U8162 ( .A(n9442), .B(n8748), .S0(n8762), .Y(n1769) );
NAND2X2TS U8163 ( .A(n2547), .B(n9538), .Y(n8634) );
INVX2TS U8164 ( .A(n8634), .Y(n8749) );
MXI2X1TS U8165 ( .A(n9438), .B(n8749), .S0(n8762), .Y(n1778) );
NAND2X2TS U8166 ( .A(n2547), .B(n9557), .Y(n8709) );
INVX2TS U8167 ( .A(n8709), .Y(n8752) );
MXI2X1TS U8168 ( .A(n9396), .B(n8752), .S0(n8762), .Y(n1772) );
NOR2X1TS U8169 ( .A(n8125), .B(n7239), .Y(n7245) );
AOI22X1TS U8170 ( .A0(n7329), .A1(n7242), .B0(FPADDSUB_Data_array_SWR[3]),
.B1(n7264), .Y(n7243) );
NOR2X1TS U8171 ( .A(n2646), .B(n9096), .Y(n7246) );
NOR2X2TS U8172 ( .A(n7247), .B(n7246), .Y(n7313) );
OAI22X1TS U8173 ( .A0(n8125), .A1(n7313), .B0(n9395), .B1(n7322), .Y(n7251)
);
AOI2BB2X1TS U8174 ( .B0(n7308), .B1(n7252), .A0N(n8127), .A1N(n7248), .Y(
n7250) );
NAND3BX2TS U8175 ( .AN(n7251), .B(n7250), .C(n7249), .Y(n1808) );
INVX2TS U8176 ( .A(n7252), .Y(n7299) );
NOR2X2TS U8177 ( .A(n7324), .B(n7299), .Y(n7257) );
AOI22X1TS U8178 ( .A0(n7317), .A1(n7301), .B0(n7044), .B1(n7253), .Y(n7256)
);
NAND3BX1TS U8179 ( .AN(n7257), .B(n7256), .C(n7255), .Y(n1810) );
NOR2X1TS U8180 ( .A(n8125), .B(n7258), .Y(n7267) );
NOR2X1TS U8181 ( .A(n7260), .B(n9228), .Y(n7261) );
NOR2X2TS U8182 ( .A(n7262), .B(n7261), .Y(n7314) );
INVX2TS U8183 ( .A(n7314), .Y(n7328) );
INVX2TS U8184 ( .A(n7263), .Y(n7325) );
AOI2BB2X1TS U8185 ( .B0(n7317), .B1(n7328), .A0N(n7042), .A1N(n7325), .Y(
n7266) );
AOI22X1TS U8186 ( .A0(n7329), .A1(n7268), .B0(FPADDSUB_Data_array_SWR[15]),
.B1(n7264), .Y(n7265) );
INVX2TS U8187 ( .A(n7313), .Y(n7327) );
AOI22X1TS U8188 ( .A0(n7317), .A1(n7318), .B0(n7044), .B1(n7327), .Y(n7270)
);
INVX2TS U8189 ( .A(n7268), .Y(n7323) );
AOI2BB2X1TS U8190 ( .B0(FPADDSUB_Data_array_SWR[17]), .B1(n8342), .A0N(n7326), .A1N(n7323), .Y(n7269) );
NAND3BX2TS U8191 ( .AN(n7271), .B(n7270), .C(n7269), .Y(n1806) );
MXI2X1TS U8192 ( .A(n9444), .B(n2694), .S0(n7272), .Y(n2045) );
OAI2BB1X2TS U8193 ( .A0N(n9537), .A1N(n2472), .B0(n9536), .Y(n1358) );
INVX2TS U8194 ( .A(n1358), .Y(n8760) );
MXI2X1TS U8195 ( .A(n9412), .B(n8760), .S0(n7272), .Y(n1910) );
MXI2X1TS U8196 ( .A(n9443), .B(n7274), .S0(n7275), .Y(n2042) );
INVX2TS U8197 ( .A(n7276), .Y(n7291) );
NAND2X1TS U8198 ( .A(n7286), .B(n7291), .Y(n7279) );
INVX2TS U8199 ( .A(n7290), .Y(n7277) );
AOI21X1TS U8200 ( .A0(n7287), .A1(n7291), .B0(n7277), .Y(n7278) );
INVX2TS U8201 ( .A(n7280), .Y(n7282) );
INVX2TS U8202 ( .A(n7286), .Y(n7288) );
AOI22X1TS U8203 ( .A0(n8081), .A1(FPMULT_Add_result[8]), .B0(
FPMULT_Sgf_normalized_result[7]), .B1(n7494), .Y(n7297) );
AOI2BB2X1TS U8204 ( .B0(n8092), .B1(n1584), .A0N(n2915), .A1N(n9203), .Y(
n7296) );
NAND2X1TS U8205 ( .A(n8071), .B(n1583), .Y(n7295) );
NAND3X1TS U8206 ( .A(n7297), .B(n7296), .C(n7295), .Y(n1524) );
OAI22X1TS U8207 ( .A0(n7324), .A1(n7298), .B0(n9246), .B1(n7322), .Y(n7304)
);
AOI2BB2X1TS U8208 ( .B0(n7317), .B1(n7300), .A0N(n7326), .A1N(n7299), .Y(
n7303) );
NAND3BX2TS U8209 ( .AN(n7304), .B(n7303), .C(n7302), .Y(n1811) );
OAI22X1TS U8210 ( .A0(n7324), .A1(n7305), .B0(n9388), .B1(n7322), .Y(n7312)
);
AOI2BB2X1TS U8211 ( .B0(n7308), .B1(n7307), .A0N(n7326), .A1N(n7306), .Y(
n7311) );
NAND3BX2TS U8212 ( .AN(n7312), .B(n7311), .C(n7310), .Y(n1794) );
OAI22X1TS U8213 ( .A0(n7324), .A1(n7313), .B0(n9394), .B1(n7322), .Y(n7321)
);
AOI2BB2X1TS U8214 ( .B0(n7317), .B1(n7316), .A0N(n7315), .A1N(n7314), .Y(
n7320) );
NAND3BX2TS U8215 ( .AN(n7321), .B(n7320), .C(n7319), .Y(n1807) );
OAI22X1TS U8216 ( .A0(n7324), .A1(n7323), .B0(n9392), .B1(n7322), .Y(n7332)
);
AOI2BB2X1TS U8217 ( .B0(n8129), .B1(n7327), .A0N(n7326), .A1N(n7325), .Y(
n7331) );
NAND3BX2TS U8218 ( .AN(n7332), .B(n7331), .C(n7330), .Y(n1805) );
NOR2X1TS U8219 ( .A(n3673), .B(FPADDSUB_DMP_SFG[16]), .Y(n7336) );
INVX2TS U8220 ( .A(n7439), .Y(n7338) );
NAND2X1TS U8221 ( .A(n3673), .B(FPADDSUB_DMP_SFG[16]), .Y(n7334) );
INVX2TS U8222 ( .A(n7443), .Y(n7337) );
OAI21X1TS U8223 ( .A0(n7130), .A1(n7338), .B0(n7337), .Y(n7343) );
INVX2TS U8224 ( .A(n7339), .Y(n7341) );
NAND2X1TS U8225 ( .A(n7341), .B(n7340), .Y(n7346) );
XNOR2X1TS U8226 ( .A(n7343), .B(n7342), .Y(n7350) );
OAI21X1TS U8227 ( .A0(n6909), .A1(n7345), .B0(n7344), .Y(n7347) );
XNOR2X1TS U8228 ( .A(n7347), .B(n7346), .Y(n7348) );
AOI22X1TS U8229 ( .A0(n7348), .A1(n7038), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n2835), .Y(n7349) );
NOR2X1TS U8230 ( .A(n3675), .B(FPADDSUB_DMP_SFG[17]), .Y(n7438) );
NOR2X1TS U8231 ( .A(n3670), .B(FPADDSUB_DMP_SFG[18]), .Y(n7353) );
NOR2X1TS U8232 ( .A(n7438), .B(n7353), .Y(n7355) );
INVX2TS U8233 ( .A(n7457), .Y(n7351) );
NOR2X1TS U8234 ( .A(n3676), .B(FPADDSUB_DMP_SFG[19]), .Y(n7369) );
INVX2TS U8235 ( .A(n7369), .Y(n7357) );
NAND2X1TS U8236 ( .A(n7351), .B(n7357), .Y(n7360) );
NAND2X1TS U8237 ( .A(n3675), .B(FPADDSUB_DMP_SFG[17]), .Y(n7440) );
NAND2X1TS U8238 ( .A(n3670), .B(FPADDSUB_DMP_SFG[18]), .Y(n7352) );
OAI21X1TS U8239 ( .A0(n7353), .A1(n7440), .B0(n7352), .Y(n7354) );
INVX2TS U8240 ( .A(n7456), .Y(n7358) );
NAND2X1TS U8241 ( .A(n3676), .B(FPADDSUB_DMP_SFG[19]), .Y(n7371) );
INVX2TS U8242 ( .A(n7371), .Y(n7356) );
AOI21X1TS U8243 ( .A0(n7358), .A1(n7357), .B0(n7356), .Y(n7359) );
OAI21X1TS U8244 ( .A0(n7130), .A1(n7360), .B0(n7359), .Y(n7363) );
INVX2TS U8245 ( .A(n7361), .Y(n7385) );
NAND2X1TS U8246 ( .A(n7385), .B(n7383), .Y(n7364) );
XNOR2X1TS U8247 ( .A(n7363), .B(n7362), .Y(n7368) );
OAI21X1TS U8248 ( .A0(n6909), .A1(n7430), .B0(n7407), .Y(n7365) );
XNOR2X1TS U8249 ( .A(n7365), .B(n7364), .Y(n7366) );
AOI22X1TS U8250 ( .A0(n7366), .A1(n7038), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n2835), .Y(n7367) );
NOR2X1TS U8251 ( .A(n3657), .B(FPADDSUB_DMP_SFG[20]), .Y(n7372) );
NOR2X1TS U8252 ( .A(n7369), .B(n7372), .Y(n7394) );
INVX2TS U8253 ( .A(n7394), .Y(n7374) );
NOR2X1TS U8254 ( .A(n7457), .B(n7374), .Y(n7418) );
INVX2TS U8255 ( .A(n7418), .Y(n7376) );
NAND2X1TS U8256 ( .A(n3657), .B(FPADDSUB_DMP_SFG[20]), .Y(n7370) );
OAI21X1TS U8257 ( .A0(n7372), .A1(n7371), .B0(n7370), .Y(n7399) );
INVX2TS U8258 ( .A(n7399), .Y(n7373) );
OAI21X1TS U8259 ( .A0(n7456), .A1(n7374), .B0(n7373), .Y(n7422) );
INVX2TS U8260 ( .A(n7422), .Y(n7375) );
OAI21X1TS U8261 ( .A0(n7130), .A1(n7376), .B0(n7375), .Y(n7381) );
INVX2TS U8262 ( .A(n7377), .Y(n7379) );
NAND2X1TS U8263 ( .A(n7379), .B(n7378), .Y(n7389) );
XNOR2X1TS U8264 ( .A(n7381), .B(n7380), .Y(n7393) );
INVX2TS U8265 ( .A(n7430), .Y(n7382) );
NAND2X1TS U8266 ( .A(n7382), .B(n7385), .Y(n7388) );
INVX2TS U8267 ( .A(n7383), .Y(n7384) );
AOI21X1TS U8268 ( .A0(n7386), .A1(n7385), .B0(n7384), .Y(n7387) );
OAI21X1TS U8269 ( .A0(n6909), .A1(n7388), .B0(n7387), .Y(n7390) );
XNOR2X1TS U8270 ( .A(n7390), .B(n7389), .Y(n7391) );
OAI2BB1X1TS U8271 ( .A0N(n7475), .A1N(n7393), .B0(n7392), .Y(n1318) );
NOR2X1TS U8272 ( .A(n3659), .B(FPADDSUB_DMP_SFG[21]), .Y(n7417) );
NOR2X1TS U8273 ( .A(n7417), .B(n7396), .Y(n7398) );
NAND2X1TS U8274 ( .A(n7394), .B(n7398), .Y(n7401) );
NAND2X1TS U8275 ( .A(n3660), .B(FPADDSUB_DMP_SFG[22]), .Y(n7395) );
AOI21X1TS U8276 ( .A0(n7399), .A1(n7398), .B0(n7397), .Y(n7400) );
OA21XLTS U8277 ( .A0(n7456), .A1(n7401), .B0(n7400), .Y(n7402) );
OAI21X1TS U8278 ( .A0(n7130), .A1(n3628), .B0(n7402), .Y(n7403) );
XNOR2X1TS U8279 ( .A(n7403), .B(add_x_18_n35), .Y(n7415) );
INVX2TS U8280 ( .A(n7404), .Y(n7429) );
INVX2TS U8281 ( .A(n7405), .Y(n7406) );
INVX2TS U8282 ( .A(n7425), .Y(n7408) );
AOI21X1TS U8283 ( .A0(n7431), .A1(n7426), .B0(n7408), .Y(n7409) );
OAI21X1TS U8284 ( .A0(n6909), .A1(n7410), .B0(n7409), .Y(n7411) );
XNOR2X1TS U8285 ( .A(n7411), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n7413) );
AOI22X1TS U8286 ( .A0(n7413), .A1(n8704), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n7412), .Y(n7414) );
INVX2TS U8287 ( .A(n7417), .Y(n7421) );
NAND2X1TS U8288 ( .A(n7418), .B(n7421), .Y(n7424) );
INVX2TS U8289 ( .A(n7419), .Y(n7420) );
AOI21X1TS U8290 ( .A0(n7422), .A1(n7421), .B0(n7420), .Y(n7423) );
OAI21X1TS U8291 ( .A0(n7130), .A1(n7424), .B0(n7423), .Y(n7428) );
NAND2X1TS U8292 ( .A(n7426), .B(n7425), .Y(n7433) );
XNOR2X1TS U8293 ( .A(n7428), .B(n7427), .Y(n7437) );
INVX2TS U8294 ( .A(n7431), .Y(n7432) );
OAI21X1TS U8295 ( .A0(n6909), .A1(n2683), .B0(n7432), .Y(n7434) );
XNOR2X1TS U8296 ( .A(n7434), .B(n7433), .Y(n7435) );
AOI22X1TS U8297 ( .A0(n7435), .A1(n8704), .B0(FPADDSUB_Raw_mant_NRM_SWR[24]),
.B1(n2835), .Y(n7436) );
INVX2TS U8298 ( .A(n7438), .Y(n7442) );
INVX2TS U8299 ( .A(n7440), .Y(n7441) );
AOI21X1TS U8300 ( .A0(n7443), .A1(n7442), .B0(n7441), .Y(n7444) );
OAI21X1TS U8301 ( .A0(n7130), .A1(n7445), .B0(n7444), .Y(n7448) );
INVX2TS U8302 ( .A(n7446), .Y(n7466) );
NAND2X1TS U8303 ( .A(n7466), .B(n7464), .Y(n7451) );
XNOR2X1TS U8304 ( .A(n7448), .B(n7447), .Y(n7455) );
INVX2TS U8305 ( .A(n7463), .Y(n7450) );
INVX2TS U8306 ( .A(n7467), .Y(n7449) );
OAI21X1TS U8307 ( .A0(n6909), .A1(n7450), .B0(n7449), .Y(n7452) );
XNOR2X1TS U8308 ( .A(n7452), .B(n7451), .Y(n7453) );
AOI22X1TS U8309 ( .A0(n7453), .A1(n7038), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n2835), .Y(n7454) );
INVX2TS U8310 ( .A(n7458), .Y(n7460) );
NAND2X1TS U8311 ( .A(n7460), .B(n7459), .Y(n7470) );
XNOR2X1TS U8312 ( .A(n7462), .B(n7461), .Y(n7474) );
NAND2X1TS U8313 ( .A(n7463), .B(n7466), .Y(n7469) );
INVX2TS U8314 ( .A(n7464), .Y(n7465) );
AOI21X1TS U8315 ( .A0(n7467), .A1(n7466), .B0(n7465), .Y(n7468) );
OAI21X1TS U8316 ( .A0(n6909), .A1(n7469), .B0(n7468), .Y(n7471) );
XNOR2X1TS U8317 ( .A(n7471), .B(n7470), .Y(n7472) );
AOI22X1TS U8318 ( .A0(n7472), .A1(n7038), .B0(FPADDSUB_Raw_mant_NRM_SWR[21]),
.B1(n2835), .Y(n7473) );
AOI22X1TS U8319 ( .A0(n8090), .A1(FPMULT_Add_result[7]), .B0(
FPMULT_Sgf_normalized_result[6]), .B1(n7494), .Y(n7479) );
INVX2TS U8320 ( .A(FPMULT_Add_result[6]), .Y(n7476) );
NAND2X4TS U8321 ( .A(n8295), .B(begin_operation), .Y(n7481) );
MXI2X4TS U8322 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n8311),
.S0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n8776) );
NAND2X8TS U8323 ( .A(n8309), .B(n8776), .Y(n7547) );
OR2X8TS U8324 ( .A(n8211), .B(n7483), .Y(n8230) );
NOR2X8TS U8325 ( .A(n8230), .B(n7484), .Y(n7603) );
NAND2X1TS U8326 ( .A(n8210), .B(FPSENCOS_d_ff3_sh_y_out[30]), .Y(n7488) );
NOR2X8TS U8327 ( .A(n8230), .B(n7485), .Y(n7601) );
NAND2X1TS U8328 ( .A(n8208), .B(FPSENCOS_d_ff3_sh_x_out[30]), .Y(n7487) );
NOR2X8TS U8329 ( .A(n8766), .B(operation[1]), .Y(n8195) );
AOI22X1TS U8330 ( .A0(n8767), .A1(Data_2[30]), .B0(FPADDSUB_intDY_EWSW[30]),
.B1(n8211), .Y(n7486) );
NAND3X1TS U8331 ( .A(n7488), .B(n7487), .C(n7486), .Y(n1815) );
AOI22X1TS U8332 ( .A0(n8090), .A1(FPMULT_Add_result[10]), .B0(
FPMULT_Sgf_normalized_result[9]), .B1(n8089), .Y(n7493) );
AOI22X1TS U8333 ( .A0(n7758), .A1(FPMULT_Add_result[9]), .B0(
FPMULT_Sgf_normalized_result[8]), .B1(n7494), .Y(n7497) );
AOI2BB2X1TS U8334 ( .B0(n8083), .B1(n1585), .A0N(n2915), .A1N(n9146), .Y(
n7496) );
NAND2X1TS U8335 ( .A(n8071), .B(n1584), .Y(n7495) );
NAND3X1TS U8336 ( .A(n7497), .B(n7496), .C(n7495), .Y(n1525) );
INVX2TS U8337 ( .A(n7499), .Y(n7746) );
INVX2TS U8338 ( .A(n7746), .Y(n7500) );
INVX2TS U8339 ( .A(n7504), .Y(n7741) );
AOI22X1TS U8340 ( .A0(n8081), .A1(FPMULT_Add_result[11]), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n8089), .Y(n7510) );
NOR2X8TS U8341 ( .A(n8230), .B(n8757), .Y(n7602) );
BUFX8TS U8342 ( .A(n7602), .Y(n8209) );
NAND2X1TS U8343 ( .A(n8208), .B(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n7513) );
NAND2X1TS U8344 ( .A(n8210), .B(FPSENCOS_d_ff3_sh_y_out[22]), .Y(n7512) );
AOI22X1TS U8345 ( .A0(n7653), .A1(Data_2[22]), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n7652), .Y(n7511) );
NAND4X1TS U8346 ( .A(n7517), .B(n7513), .C(n7512), .D(n7511), .Y(n1823) );
NAND2X1TS U8347 ( .A(n8186), .B(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n7516) );
NAND2X1TS U8348 ( .A(n8188), .B(FPSENCOS_d_ff3_sh_y_out[19]), .Y(n7515) );
AOI22X1TS U8349 ( .A0(n8190), .A1(Data_2[19]), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n8189), .Y(n7514) );
NAND4X1TS U8350 ( .A(n7517), .B(n7516), .C(n7515), .D(n7514), .Y(n1826) );
BUFX8TS U8351 ( .A(n7602), .Y(n7682) );
NAND2X2TS U8352 ( .A(n7682), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n7600) );
NAND2X1TS U8353 ( .A(n8186), .B(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n7520) );
NAND2X1TS U8354 ( .A(n8188), .B(FPSENCOS_d_ff3_sh_y_out[18]), .Y(n7519) );
AOI22X1TS U8355 ( .A0(n8190), .A1(Data_2[18]), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n8189), .Y(n7518) );
NAND4X1TS U8356 ( .A(n7600), .B(n7520), .C(n7519), .D(n7518), .Y(n1827) );
NAND2X1TS U8357 ( .A(n8186), .B(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n7523) );
NAND2X1TS U8358 ( .A(n8188), .B(FPSENCOS_d_ff3_sh_y_out[3]), .Y(n7522) );
AOI22X1TS U8359 ( .A0(n8190), .A1(Data_2[3]), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n8189), .Y(n7521) );
NAND4X1TS U8360 ( .A(n7611), .B(n7523), .C(n7522), .D(n7521), .Y(n1842) );
NAND2X1TS U8361 ( .A(n8186), .B(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n7526) );
NAND2X1TS U8362 ( .A(n8188), .B(FPSENCOS_d_ff3_sh_y_out[14]), .Y(n7525) );
AOI22X1TS U8363 ( .A0(n7685), .A1(Data_2[14]), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n7684), .Y(n7524) );
NAND4X1TS U8364 ( .A(n7619), .B(n7526), .C(n7525), .D(n7524), .Y(n1831) );
NAND2X1TS U8365 ( .A(n8173), .B(FPSENCOS_d_ff3_sh_x_out[23]), .Y(n7530) );
NAND2X1TS U8366 ( .A(n8174), .B(FPSENCOS_d_ff3_LUT_out[23]), .Y(n7529) );
NAND2X1TS U8367 ( .A(n8175), .B(FPSENCOS_d_ff3_sh_y_out[23]), .Y(n7528) );
AOI22X1TS U8368 ( .A0(n7653), .A1(Data_2[23]), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n7652), .Y(n7527) );
NAND4X1TS U8369 ( .A(n7530), .B(n7529), .C(n7528), .D(n7527), .Y(n1822) );
NAND2X1TS U8370 ( .A(n8765), .B(FPSENCOS_d_ff3_sh_x_out[1]), .Y(n7534) );
NAND2X1TS U8371 ( .A(n8187), .B(FPSENCOS_d_ff3_LUT_out[1]), .Y(n7533) );
NAND2X1TS U8372 ( .A(n8764), .B(FPSENCOS_d_ff3_sh_y_out[1]), .Y(n7532) );
AOI22X1TS U8373 ( .A0(n8767), .A1(Data_2[1]), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n8766), .Y(n7531) );
NAND4X1TS U8374 ( .A(n7534), .B(n7533), .C(n7532), .D(n7531), .Y(n1844) );
NAND2X1TS U8375 ( .A(n8173), .B(n2918), .Y(n7538) );
NAND2X1TS U8376 ( .A(n8174), .B(FPSENCOS_d_ff3_LUT_out[26]), .Y(n7537) );
NAND2X1TS U8377 ( .A(n8175), .B(FPSENCOS_d_ff3_sh_y_out[26]), .Y(n7536) );
AOI22X1TS U8378 ( .A0(n7653), .A1(Data_2[26]), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n7652), .Y(n7535) );
NAND2X1TS U8379 ( .A(n8173), .B(FPSENCOS_d_ff3_sh_x_out[25]), .Y(n7542) );
NAND2X1TS U8380 ( .A(n8174), .B(FPSENCOS_d_ff3_LUT_out[25]), .Y(n7541) );
NAND2X1TS U8381 ( .A(n8175), .B(FPSENCOS_d_ff3_sh_y_out[25]), .Y(n7540) );
AOI22X1TS U8382 ( .A0(n7653), .A1(Data_2[25]), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n7652), .Y(n7539) );
NAND2X1TS U8383 ( .A(n8216), .B(FPSENCOS_d_ff3_sh_x_out[8]), .Y(n7546) );
BUFX8TS U8384 ( .A(n7602), .Y(n8217) );
NAND2X1TS U8385 ( .A(n8217), .B(FPSENCOS_d_ff3_LUT_out[8]), .Y(n7545) );
NAND2X1TS U8386 ( .A(n8218), .B(FPSENCOS_d_ff3_sh_y_out[8]), .Y(n7544) );
AOI22X1TS U8387 ( .A0(n8177), .A1(Data_2[8]), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n8176), .Y(n7543) );
NAND2X1TS U8388 ( .A(n7681), .B(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n7550) );
NAND2X1TS U8389 ( .A(n7683), .B(FPSENCOS_d_ff3_sh_y_out[11]), .Y(n7549) );
AOI22X1TS U8390 ( .A0(n8220), .A1(Data_2[11]), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n8219), .Y(n7548) );
NAND4X1TS U8391 ( .A(n7554), .B(n7550), .C(n7549), .D(n7548), .Y(n1834) );
NAND2X1TS U8392 ( .A(n8216), .B(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n7553) );
NAND2X1TS U8393 ( .A(n8218), .B(FPSENCOS_d_ff3_sh_y_out[7]), .Y(n7552) );
AOI22X1TS U8394 ( .A0(n8220), .A1(Data_2[7]), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n8176), .Y(n7551) );
NAND2X1TS U8395 ( .A(n8173), .B(FPSENCOS_d_ff2_Y[5]), .Y(n7558) );
NAND2X1TS U8396 ( .A(n8174), .B(FPSENCOS_d_ff2_Z[5]), .Y(n7557) );
NAND2X1TS U8397 ( .A(n8175), .B(FPSENCOS_d_ff2_X[5]), .Y(n7556) );
AOI22X1TS U8398 ( .A0(n8177), .A1(Data_1[5]), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n7652), .Y(n7555) );
NAND2X2TS U8399 ( .A(n8209), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n7576) );
AOI22X1TS U8400 ( .A0(n8767), .A1(Data_2[29]), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n8766), .Y(n7561) );
NAND2X1TS U8401 ( .A(n8765), .B(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n7560) );
NAND2X1TS U8402 ( .A(n8764), .B(FPSENCOS_d_ff3_sh_y_out[29]), .Y(n7559) );
NAND4X1TS U8403 ( .A(n7576), .B(n7561), .C(n7560), .D(n7559), .Y(n1816) );
NAND2X1TS U8404 ( .A(n8216), .B(FPSENCOS_d_ff2_Y[6]), .Y(n7565) );
NAND2X1TS U8405 ( .A(n8174), .B(FPSENCOS_d_ff2_Z[6]), .Y(n7564) );
NAND2X1TS U8406 ( .A(n8218), .B(FPSENCOS_d_ff2_X[6]), .Y(n7563) );
AOI22X1TS U8407 ( .A0(n8177), .A1(Data_1[6]), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n8176), .Y(n7562) );
NAND4X1TS U8408 ( .A(n7565), .B(n7564), .C(n7563), .D(n7562), .Y(n1937) );
NAND2X1TS U8409 ( .A(n8173), .B(FPSENCOS_d_ff3_sh_x_out[24]), .Y(n7569) );
NAND2X1TS U8410 ( .A(n8174), .B(FPSENCOS_d_ff3_LUT_out[24]), .Y(n7568) );
NAND2X1TS U8411 ( .A(n8175), .B(FPSENCOS_d_ff3_sh_y_out[24]), .Y(n7567) );
AOI22X1TS U8412 ( .A0(n7653), .A1(Data_2[24]), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n7652), .Y(n7566) );
NAND4X1TS U8413 ( .A(n7569), .B(n7568), .C(n7567), .D(n7566), .Y(n1821) );
AOI22X1TS U8414 ( .A0(n8767), .A1(Data_2[28]), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n8766), .Y(n7572) );
NAND2X1TS U8415 ( .A(n8764), .B(FPSENCOS_d_ff3_sh_y_out[28]), .Y(n7570) );
NAND4X1TS U8416 ( .A(n7576), .B(n7572), .C(n7571), .D(n7570), .Y(n1817) );
AOI22X1TS U8417 ( .A0(n7653), .A1(Data_2[27]), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n7652), .Y(n7575) );
NAND2X1TS U8418 ( .A(n8173), .B(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n7574) );
NAND2X1TS U8419 ( .A(n8175), .B(FPSENCOS_d_ff3_sh_y_out[27]), .Y(n7573) );
NAND4X1TS U8420 ( .A(n7576), .B(n7575), .C(n7574), .D(n7573), .Y(n1818) );
NAND2X1TS U8421 ( .A(n8173), .B(FPSENCOS_d_ff2_Y[21]), .Y(n7580) );
NAND2X1TS U8422 ( .A(n8174), .B(FPSENCOS_d_ff2_Z[21]), .Y(n7579) );
NAND2X1TS U8423 ( .A(n8175), .B(FPSENCOS_d_ff2_X[21]), .Y(n7578) );
AOI22X1TS U8424 ( .A0(n8177), .A1(Data_1[21]), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n8176), .Y(n7577) );
NAND4X1TS U8425 ( .A(n7580), .B(n7579), .C(n7578), .D(n7577), .Y(n1922) );
NAND2X1TS U8426 ( .A(n8186), .B(FPSENCOS_d_ff3_sh_x_out[10]), .Y(n7584) );
NAND2X1TS U8427 ( .A(n8187), .B(FPSENCOS_d_ff3_LUT_out[10]), .Y(n7583) );
NAND2X1TS U8428 ( .A(n8188), .B(FPSENCOS_d_ff3_sh_y_out[10]), .Y(n7582) );
AOI22X1TS U8429 ( .A0(n7685), .A1(Data_2[10]), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n7684), .Y(n7581) );
NAND2X1TS U8430 ( .A(n8186), .B(FPSENCOS_d_ff2_Y[18]), .Y(n7588) );
NAND2X1TS U8431 ( .A(n8187), .B(FPSENCOS_d_ff2_Z[18]), .Y(n7587) );
NAND2X1TS U8432 ( .A(n8188), .B(FPSENCOS_d_ff2_X[18]), .Y(n7586) );
AOI22X1TS U8433 ( .A0(n8190), .A1(Data_1[18]), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n8189), .Y(n7585) );
NAND4X1TS U8434 ( .A(n7588), .B(n7587), .C(n7586), .D(n7585), .Y(n1925) );
NAND2X1TS U8435 ( .A(n8216), .B(FPSENCOS_d_ff3_sh_x_out[6]), .Y(n7592) );
NAND2X1TS U8436 ( .A(n8217), .B(FPSENCOS_d_ff3_LUT_out[6]), .Y(n7591) );
NAND2X1TS U8437 ( .A(n8218), .B(FPSENCOS_d_ff3_sh_y_out[6]), .Y(n7590) );
AOI22X1TS U8438 ( .A0(n8177), .A1(Data_2[6]), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n8176), .Y(n7589) );
NAND4X1TS U8439 ( .A(n7592), .B(n7591), .C(n7590), .D(n7589), .Y(n1839) );
NAND2X1TS U8440 ( .A(n8216), .B(FPSENCOS_d_ff3_sh_x_out[12]), .Y(n7596) );
NAND2X1TS U8441 ( .A(n8217), .B(FPSENCOS_d_ff3_LUT_out[12]), .Y(n7595) );
NAND2X1TS U8442 ( .A(n8218), .B(FPSENCOS_d_ff3_sh_y_out[12]), .Y(n7594) );
NAND4X1TS U8443 ( .A(n7596), .B(n7595), .C(n7594), .D(n7593), .Y(n1833) );
NAND2X1TS U8444 ( .A(n7681), .B(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n7599) );
NAND2X1TS U8445 ( .A(n7683), .B(FPSENCOS_d_ff3_sh_y_out[13]), .Y(n7598) );
AOI22X1TS U8446 ( .A0(n7685), .A1(Data_2[13]), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n7684), .Y(n7597) );
NAND2X1TS U8447 ( .A(n7701), .B(FPSENCOS_d_ff2_Y[31]), .Y(n7607) );
NAND2X1TS U8448 ( .A(n7602), .B(FPSENCOS_d_ff2_Z[31]), .Y(n7606) );
NAND2X1TS U8449 ( .A(n7702), .B(FPSENCOS_d_ff2_X[31]), .Y(n7605) );
AOI22X1TS U8450 ( .A0(n8767), .A1(Data_1[31]), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n8766), .Y(n7604) );
NAND4X1TS U8451 ( .A(n7607), .B(n7606), .C(n7605), .D(n7604), .Y(n1912) );
NAND2X1TS U8452 ( .A(n7681), .B(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n7610) );
NAND2X1TS U8453 ( .A(n7683), .B(FPSENCOS_d_ff3_sh_y_out[16]), .Y(n7609) );
AOI22X1TS U8454 ( .A0(n8220), .A1(Data_2[16]), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n8219), .Y(n7608) );
NAND4X1TS U8455 ( .A(n7611), .B(n7610), .C(n7609), .D(n7608), .Y(n1829) );
NAND2X1TS U8456 ( .A(n8186), .B(FPSENCOS_d_ff2_Y[3]), .Y(n7615) );
NAND2X1TS U8457 ( .A(n8187), .B(FPSENCOS_d_ff2_Z[3]), .Y(n7614) );
NAND2X1TS U8458 ( .A(n8188), .B(FPSENCOS_d_ff2_X[3]), .Y(n7613) );
AOI22X1TS U8459 ( .A0(n8190), .A1(Data_1[3]), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n7684), .Y(n7612) );
NAND2X1TS U8460 ( .A(n8765), .B(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n7618) );
NAND2X1TS U8461 ( .A(n8764), .B(FPSENCOS_d_ff3_sh_y_out[5]), .Y(n7617) );
AOI22X1TS U8462 ( .A0(n8767), .A1(Data_2[5]), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n8766), .Y(n7616) );
NAND2X1TS U8463 ( .A(n8216), .B(FPSENCOS_d_ff2_Y[7]), .Y(n7623) );
NAND2X1TS U8464 ( .A(n8217), .B(FPSENCOS_d_ff2_Z[7]), .Y(n7622) );
NAND2X1TS U8465 ( .A(n8218), .B(FPSENCOS_d_ff2_X[7]), .Y(n7621) );
AOI22X1TS U8466 ( .A0(n8177), .A1(Data_1[7]), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n8176), .Y(n7620) );
NAND4X1TS U8467 ( .A(n7623), .B(n7622), .C(n7621), .D(n7620), .Y(n1936) );
NAND2X1TS U8468 ( .A(n7681), .B(FPSENCOS_d_ff3_sh_x_out[4]), .Y(n7627) );
NAND2X1TS U8469 ( .A(n7682), .B(FPSENCOS_d_ff3_LUT_out[4]), .Y(n7626) );
NAND2X1TS U8470 ( .A(n7683), .B(FPSENCOS_d_ff3_sh_y_out[4]), .Y(n7625) );
AOI22X1TS U8471 ( .A0(n7685), .A1(Data_2[4]), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n7684), .Y(n7624) );
NAND4X1TS U8472 ( .A(n7627), .B(n7626), .C(n7625), .D(n7624), .Y(n1841) );
NAND2X1TS U8473 ( .A(n8208), .B(FPSENCOS_d_ff2_Y[24]), .Y(n7631) );
NAND2X1TS U8474 ( .A(n8209), .B(FPSENCOS_d_ff2_Z[24]), .Y(n7630) );
NAND2X1TS U8475 ( .A(n8210), .B(FPSENCOS_d_ff2_X[24]), .Y(n7629) );
AOI22X1TS U8476 ( .A0(n7653), .A1(Data_1[24]), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n7652), .Y(n7628) );
NAND2X1TS U8477 ( .A(n7681), .B(FPSENCOS_d_ff2_Y[16]), .Y(n7635) );
NAND2X1TS U8478 ( .A(n8217), .B(FPSENCOS_d_ff2_Z[16]), .Y(n7634) );
NAND2X1TS U8479 ( .A(n7683), .B(FPSENCOS_d_ff2_X[16]), .Y(n7633) );
AOI22X1TS U8480 ( .A0(n8220), .A1(Data_1[16]), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n8219), .Y(n7632) );
NAND2X1TS U8481 ( .A(n8208), .B(FPSENCOS_d_ff2_Y[26]), .Y(n7639) );
NAND2X1TS U8482 ( .A(n8209), .B(FPSENCOS_d_ff2_Z[26]), .Y(n7638) );
AOI22X1TS U8483 ( .A0(n7653), .A1(Data_1[26]), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n8211), .Y(n7636) );
NAND4X1TS U8484 ( .A(n7639), .B(n7638), .C(n7637), .D(n7636), .Y(n1917) );
NAND2X1TS U8485 ( .A(n8216), .B(FPSENCOS_d_ff2_Y[8]), .Y(n7643) );
NAND2X1TS U8486 ( .A(n8217), .B(FPSENCOS_d_ff2_Z[8]), .Y(n7642) );
NAND2X1TS U8487 ( .A(n8218), .B(FPSENCOS_d_ff2_X[8]), .Y(n7641) );
AOI22X1TS U8488 ( .A0(n8177), .A1(Data_1[8]), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n8176), .Y(n7640) );
NAND2X1TS U8489 ( .A(n8208), .B(FPSENCOS_d_ff2_Y[25]), .Y(n7647) );
NAND2X1TS U8490 ( .A(n8209), .B(FPSENCOS_d_ff2_Z[25]), .Y(n7646) );
NAND2X1TS U8491 ( .A(n8210), .B(FPSENCOS_d_ff2_X[25]), .Y(n7645) );
AOI22X1TS U8492 ( .A0(n7653), .A1(Data_1[25]), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n7652), .Y(n7644) );
NAND4X1TS U8493 ( .A(n7647), .B(n7646), .C(n7645), .D(n7644), .Y(n1918) );
NAND2X1TS U8494 ( .A(n8216), .B(FPSENCOS_d_ff2_Y[15]), .Y(n7651) );
NAND2X1TS U8495 ( .A(n8217), .B(FPSENCOS_d_ff2_Z[15]), .Y(n7650) );
NAND2X1TS U8496 ( .A(n8218), .B(FPSENCOS_d_ff2_X[15]), .Y(n7649) );
AOI22X1TS U8497 ( .A0(n8220), .A1(Data_1[15]), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n8219), .Y(n7648) );
NAND2X1TS U8498 ( .A(n8208), .B(FPSENCOS_d_ff2_Y[23]), .Y(n7657) );
NAND2X1TS U8499 ( .A(n8209), .B(FPSENCOS_d_ff2_Z[23]), .Y(n7656) );
NAND2X1TS U8500 ( .A(n8210), .B(FPSENCOS_d_ff2_X[23]), .Y(n7655) );
AOI22X1TS U8501 ( .A0(n7653), .A1(Data_1[23]), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n7652), .Y(n7654) );
NAND2X1TS U8502 ( .A(n7681), .B(FPSENCOS_d_ff2_Y[4]), .Y(n7661) );
NAND2X1TS U8503 ( .A(n7682), .B(FPSENCOS_d_ff2_Z[4]), .Y(n7660) );
NAND2X1TS U8504 ( .A(n7683), .B(FPSENCOS_d_ff2_X[4]), .Y(n7659) );
AOI22X1TS U8505 ( .A0(n7685), .A1(Data_1[4]), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n8219), .Y(n7658) );
NAND4X1TS U8506 ( .A(n7661), .B(n7660), .C(n7659), .D(n7658), .Y(n1939) );
NAND2X1TS U8507 ( .A(n8186), .B(FPSENCOS_d_ff2_Y[10]), .Y(n7665) );
NAND2X1TS U8508 ( .A(n7682), .B(n2920), .Y(n7664) );
NAND2X1TS U8509 ( .A(n8188), .B(FPSENCOS_d_ff2_X[10]), .Y(n7663) );
NAND4X1TS U8510 ( .A(n7665), .B(n7664), .C(n7663), .D(n7662), .Y(n1933) );
NAND2X1TS U8511 ( .A(n8186), .B(FPSENCOS_d_ff2_Y[14]), .Y(n7669) );
NAND2X1TS U8512 ( .A(n7682), .B(FPSENCOS_d_ff2_Z[14]), .Y(n7668) );
NAND2X1TS U8513 ( .A(n8188), .B(FPSENCOS_d_ff2_X[14]), .Y(n7667) );
AOI22X1TS U8514 ( .A0(n7685), .A1(Data_1[14]), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n7684), .Y(n7666) );
NAND2X1TS U8515 ( .A(n7681), .B(FPSENCOS_d_ff2_Y[11]), .Y(n7673) );
NAND2X1TS U8516 ( .A(n7682), .B(FPSENCOS_d_ff2_Z[11]), .Y(n7672) );
NAND2X1TS U8517 ( .A(n7683), .B(FPSENCOS_d_ff2_X[11]), .Y(n7671) );
AOI22X1TS U8518 ( .A0(n8220), .A1(Data_1[11]), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n8219), .Y(n7670) );
NAND2X1TS U8519 ( .A(n7681), .B(FPSENCOS_d_ff2_Y[17]), .Y(n7677) );
NAND2X1TS U8520 ( .A(n7682), .B(FPSENCOS_d_ff2_Z[17]), .Y(n7676) );
NAND2X1TS U8521 ( .A(n7683), .B(FPSENCOS_d_ff2_X[17]), .Y(n7675) );
AOI22X1TS U8522 ( .A0(n7685), .A1(Data_1[17]), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n7684), .Y(n7674) );
NAND4X1TS U8523 ( .A(n7677), .B(n7676), .C(n7675), .D(n7674), .Y(n1926) );
AOI22X1TS U8524 ( .A0(n7685), .A1(Data_2[17]), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n7684), .Y(n7680) );
NAND2X1TS U8525 ( .A(n7681), .B(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n7679) );
NAND2X1TS U8526 ( .A(n7683), .B(FPSENCOS_d_ff3_sh_y_out[17]), .Y(n7678) );
NAND4X1TS U8527 ( .A(n7696), .B(n7680), .C(n7679), .D(n7678), .Y(n1828) );
NAND2X1TS U8528 ( .A(n7681), .B(FPSENCOS_d_ff2_Y[13]), .Y(n7689) );
NAND2X1TS U8529 ( .A(n7682), .B(FPSENCOS_d_ff2_Z[13]), .Y(n7688) );
NAND2X1TS U8530 ( .A(n7683), .B(FPSENCOS_d_ff2_X[13]), .Y(n7687) );
AOI22X1TS U8531 ( .A0(n7685), .A1(Data_1[13]), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n7684), .Y(n7686) );
AOI22X1TS U8532 ( .A0(n8767), .A1(Data_2[20]), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n8766), .Y(n7692) );
NAND2X1TS U8533 ( .A(n7701), .B(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n7691) );
NAND2X1TS U8534 ( .A(n7702), .B(FPSENCOS_d_ff3_sh_y_out[20]), .Y(n7690) );
NAND2X1TS U8535 ( .A(n8216), .B(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n7695) );
NAND2X1TS U8536 ( .A(n8218), .B(FPSENCOS_d_ff3_sh_y_out[15]), .Y(n7694) );
AOI22X1TS U8537 ( .A0(n8220), .A1(Data_2[15]), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n8219), .Y(n7693) );
NAND4X1TS U8538 ( .A(n7696), .B(n7695), .C(n7694), .D(n7693), .Y(n1830) );
NAND2X1TS U8539 ( .A(n7701), .B(FPSENCOS_d_ff3_sh_x_out[21]), .Y(n7700) );
NAND2X1TS U8540 ( .A(n7602), .B(FPSENCOS_d_ff3_LUT_out[21]), .Y(n7699) );
NAND2X1TS U8541 ( .A(n7702), .B(FPSENCOS_d_ff3_sh_y_out[21]), .Y(n7698) );
AOI22X1TS U8542 ( .A0(n8767), .A1(Data_2[21]), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n8766), .Y(n7697) );
NAND2X1TS U8543 ( .A(n7701), .B(FPSENCOS_d_ff2_Y[22]), .Y(n7706) );
NAND2X1TS U8544 ( .A(n7602), .B(FPSENCOS_d_ff2_Z[22]), .Y(n7705) );
NAND2X1TS U8545 ( .A(n7702), .B(FPSENCOS_d_ff2_X[22]), .Y(n7704) );
AOI22X1TS U8546 ( .A0(n8220), .A1(Data_1[22]), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n8219), .Y(n7703) );
NOR2X1TS U8547 ( .A(n9218), .B(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n7707) );
XOR2X1TS U8548 ( .A(DP_OP_26J248_126_1325_n28), .B(n7707), .Y(n7717) );
XOR2X1TS U8549 ( .A(DP_OP_26J248_126_1325_n28), .B(n7709), .Y(n7722) );
NOR2X1TS U8550 ( .A(n9212), .B(FPADDSUB_ADD_OVRFLW_NRM2), .Y(n7710) );
XOR2X1TS U8551 ( .A(DP_OP_26J248_126_1325_n28), .B(n7710), .Y(n7724) );
CMPR32X2TS U8552 ( .A(n7717), .B(FPADDSUB_DMP_exp_NRM2_EW[4]), .C(n7716),
.CO(n7728), .S(n8698) );
CMPR32X2TS U8553 ( .A(n7720), .B(FPADDSUB_DMP_exp_NRM2_EW[1]), .C(n7719),
.CO(n7723), .S(n8550) );
NOR2X1TS U8554 ( .A(n8552), .B(n8550), .Y(n7727) );
CMPR32X2TS U8555 ( .A(n7722), .B(FPADDSUB_DMP_exp_NRM2_EW[3]), .C(n7721),
.CO(n7716), .S(n8635) );
CMPR32X2TS U8556 ( .A(n7724), .B(FPADDSUB_DMP_exp_NRM2_EW[2]), .C(n7723),
.CO(n7721), .S(n8548) );
NAND2BX1TS U8557 ( .AN(n8715), .B(n7730), .Y(n7732) );
AND2X2TS U8558 ( .A(n7734), .B(n8698), .Y(n7736) );
INVX2TS U8559 ( .A(n7738), .Y(n7739) );
OAI22X1TS U8560 ( .A0(n7740), .A1(n7739), .B0(FPADDSUB_Shift_reg_FLAGS_7[0]),
.B1(n8763), .Y(n1468) );
INVX2TS U8561 ( .A(n7741), .Y(n7745) );
INVX2TS U8562 ( .A(n7752), .Y(n7754) );
AOI22X1TS U8563 ( .A0(n7758), .A1(FPMULT_Add_result[12]), .B0(
FPMULT_Sgf_normalized_result[11]), .B1(n8089), .Y(n7763) );
NAND2X1TS U8564 ( .A(n7780), .B(FPADDSUB_Data_array_SWR[14]), .Y(n7767) );
NAND2X1TS U8565 ( .A(n7801), .B(FPADDSUB_Data_array_SWR[10]), .Y(n7766) );
NAND4X2TS U8566 ( .A(n7767), .B(n7766), .C(n7765), .D(n7764), .Y(n9933) );
NAND2X1TS U8567 ( .A(n7801), .B(FPADDSUB_Data_array_SWR[15]), .Y(n7770) );
NOR2X1TS U8568 ( .A(n7927), .B(n7949), .Y(n7782) );
NAND4X2TS U8569 ( .A(n7771), .B(n7770), .C(n7782), .D(n7769), .Y(n9934) );
NAND2X1TS U8570 ( .A(n9934), .B(n8043), .Y(n7774) );
INVX8TS U8571 ( .A(n3702), .Y(n8053) );
NAND2X1TS U8572 ( .A(n8053), .B(FPADDSUB_DmP_mant_SFG_SWR[10]), .Y(n7773) );
NAND2X1TS U8573 ( .A(n7780), .B(FPADDSUB_Data_array_SWR[15]), .Y(n7779) );
NAND2X1TS U8574 ( .A(n7801), .B(FPADDSUB_Data_array_SWR[11]), .Y(n7778) );
AOI21X1TS U8575 ( .A0(n8047), .A1(FPADDSUB_Data_array_SWR[23]), .B0(n7949),
.Y(n7777) );
NAND4X2TS U8576 ( .A(n7779), .B(n7778), .C(n7777), .D(n7776), .Y(n9931) );
NAND2X1TS U8577 ( .A(n7780), .B(FPADDSUB_Data_array_SWR[18]), .Y(n7784) );
NAND2X1TS U8578 ( .A(n7801), .B(FPADDSUB_Data_array_SWR[14]), .Y(n7783) );
NAND4X2TS U8579 ( .A(n7784), .B(n7783), .C(n7782), .D(n7781), .Y(n9932) );
NAND2X1TS U8580 ( .A(n9931), .B(n8043), .Y(n7787) );
INVX2TS U8581 ( .A(n3702), .Y(n8058) );
NAND2X1TS U8582 ( .A(n8058), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n7785) );
NAND3X1TS U8583 ( .A(n7787), .B(n7786), .C(n7785), .Y(n1193) );
NAND2X1TS U8584 ( .A(n9931), .B(n8065), .Y(n7791) );
NAND2X1TS U8585 ( .A(n9932), .B(n7788), .Y(n7790) );
NAND2X1TS U8586 ( .A(n9933), .B(n8043), .Y(n7794) );
NAND2X1TS U8587 ( .A(n9934), .B(n8065), .Y(n7793) );
NAND2X1TS U8588 ( .A(n8058), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n7792) );
NAND3X1TS U8589 ( .A(n7794), .B(n7793), .C(n7792), .Y(n1192) );
NAND2X1TS U8590 ( .A(n9947), .B(n8043), .Y(n7798) );
NAND2X1TS U8591 ( .A(n9948), .B(n7795), .Y(n7797) );
NAND2X4TS U8592 ( .A(n9112), .B(n3702), .Y(n8056) );
NAND2X1TS U8593 ( .A(n8053), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n7796) );
NAND4X1TS U8594 ( .A(n7798), .B(n7797), .C(n8056), .D(n7796), .Y(n1185) );
NAND2X1TS U8595 ( .A(n7963), .B(FPADDSUB_Data_array_SWR[18]), .Y(n7799) );
NAND3X2TS U8596 ( .A(n7800), .B(n7799), .C(n7905), .Y(n9940) );
AOI22X1TS U8597 ( .A0(n8048), .A1(FPADDSUB_Data_array_SWR[10]), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n8047), .Y(n7805) );
NAND2X1TS U8598 ( .A(n9940), .B(n2908), .Y(n7804) );
NAND2X1TS U8599 ( .A(n8049), .B(FPADDSUB_Data_array_SWR[2]), .Y(n7803) );
NAND4X2TS U8600 ( .A(n7805), .B(n7804), .C(n7803), .D(n7802), .Y(n9958) );
NAND2X1TS U8601 ( .A(n7955), .B(n7806), .Y(n7807) );
NAND2X1TS U8602 ( .A(n9958), .B(n7788), .Y(n7810) );
NAND2X1TS U8603 ( .A(n9959), .B(n7795), .Y(n7809) );
NAND2X1TS U8604 ( .A(n8053), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n7808) );
NAND4X1TS U8605 ( .A(n7810), .B(n7809), .C(n8056), .D(n7808), .Y(n1184) );
AOI22X1TS U8606 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n3644), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n7812), .Y(n7816) );
NAND3X1TS U8607 ( .A(n3656), .B(n7813), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n7815) );
OAI211X1TS U8608 ( .A0(n7816), .A1(n7872), .B0(n7815), .C0(n7814), .Y(n7821)
);
AOI2BB2X1TS U8609 ( .B0(n7821), .B1(n7870), .A0N(n7820), .A1N(n7819), .Y(
n7876) );
NAND2BX1TS U8610 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n7838) );
NOR2X1TS U8611 ( .A(n3652), .B(FPADDSUB_intDX_EWSW[11]), .Y(n7836) );
AOI21X1TS U8612 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3595), .B0(n7836), .Y(
n7841) );
OAI211X1TS U8613 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n3634), .B0(n7838), .C0(
n7841), .Y(n7852) );
OAI22X1TS U8614 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n7822), .B0(n2647), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n7833) );
OAI2BB1X1TS U8615 ( .A0N(n3599), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n7823) );
OAI22X1TS U8616 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n7823), .B0(n3599), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n7832) );
OAI21X1TS U8617 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n3637), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n7824) );
OAI2BB2XLTS U8618 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n7824), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n3637), .Y(n7826) );
OAI21X1TS U8619 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n3638), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n7827) );
AOI2BB2X1TS U8620 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n3638), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n7827), .Y(n7828) );
AOI22X1TS U8621 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3599), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n3603), .Y(n7830) );
OAI32X1TS U8622 ( .A0(n7833), .A1(n7832), .A2(n7831), .B0(n7830), .B1(n7832),
.Y(n7851) );
OA22X1TS U8623 ( .A0(n3649), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n3653), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n7848) );
NAND2BX1TS U8624 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n7834) );
OAI21X1TS U8625 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n3635), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n7835) );
NOR2X1TS U8626 ( .A(n7836), .B(FPADDSUB_intDY_EWSW[10]), .Y(n7837) );
AOI22X1TS U8627 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n3652), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n7837), .Y(n7843) );
NAND3X1TS U8628 ( .A(n3634), .B(n7838), .C(FPADDSUB_intDX_EWSW[8]), .Y(n7839) );
AOI21X1TS U8629 ( .A0(n7840), .A1(n7839), .B0(n7850), .Y(n7842) );
OAI21X1TS U8630 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n3653), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n7844) );
OAI2BB2XLTS U8631 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n7844), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n3653), .Y(n7845) );
AOI211X1TS U8632 ( .A0(n7848), .A1(n7847), .B0(n7846), .C0(n7845), .Y(n7849)
);
OAI31X1TS U8633 ( .A0(n7852), .A1(n7851), .A2(n7850), .B0(n7849), .Y(n7855)
);
OA22X2TS U8634 ( .A0(n3604), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n3598), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n7868) );
NAND2BX1TS U8635 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n7853) );
OAI21X1TS U8636 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n3636), .B0(n7859), .Y(
n7863) );
AOI211X1TS U8637 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3592), .B0(n7862),
.C0(n7863), .Y(n7854) );
NAND3BX1TS U8638 ( .AN(n7857), .B(n7855), .C(n7854), .Y(n7875) );
AOI22X1TS U8639 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n3655), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n7858), .Y(n7861) );
AOI32X1TS U8640 ( .A0(n3636), .A1(n7859), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n3605), .Y(n7860) );
OAI32X1TS U8641 ( .A0(n7863), .A1(n7862), .A2(n7861), .B0(n7860), .B1(n7862),
.Y(n7866) );
OAI21X1TS U8642 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n3598), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n7864) );
OAI2BB2XLTS U8643 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n7864), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n3598), .Y(n7865) );
AOI211X1TS U8644 ( .A0(n7868), .A1(n7867), .B0(n7866), .C0(n7865), .Y(n7874)
);
NAND2BX1TS U8645 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n7869) );
NAND4BBX1TS U8646 ( .AN(n7872), .BN(n7871), .C(n7870), .D(n7869), .Y(n7873)
);
AOI32X4TS U8647 ( .A0(n7876), .A1(n7875), .A2(n7874), .B0(n7873), .B1(n7876),
.Y(n8033) );
CMPR32X2TS U8648 ( .A(n7882), .B(n7881), .C(n7880), .CO(n7877), .S(n8237) );
CMPR32X2TS U8649 ( .A(n7885), .B(n7884), .C(n7883), .CO(n7880), .S(n8716) );
CMPR32X2TS U8650 ( .A(n7888), .B(n7887), .C(n7886), .CO(n7883), .S(n8713) );
CMPR32X2TS U8651 ( .A(n7891), .B(n7890), .C(n7889), .CO(n7886), .S(n8699) );
AND3X2TS U8652 ( .A(n8237), .B(n8716), .C(n7894), .Y(n7898) );
NAND2X1TS U8653 ( .A(n7962), .B(FPADDSUB_Data_array_SWR[25]), .Y(n7900) );
NAND2X1TS U8654 ( .A(n7963), .B(FPADDSUB_Data_array_SWR[21]), .Y(n7899) );
NAND3X2TS U8655 ( .A(n7900), .B(n7899), .C(n7905), .Y(n9946) );
NAND2X1TS U8656 ( .A(n9946), .B(n2908), .Y(n7903) );
NAND2X1TS U8657 ( .A(n8049), .B(FPADDSUB_Data_array_SWR[5]), .Y(n7902) );
NAND2X1TS U8658 ( .A(n8039), .B(FPADDSUB_Data_array_SWR[9]), .Y(n7901) );
NAND4X2TS U8659 ( .A(n7904), .B(n7903), .C(n7902), .D(n7901), .Y(n9943) );
NAND2X1TS U8660 ( .A(n7962), .B(FPADDSUB_Data_array_SWR[24]), .Y(n7907) );
NAND2X1TS U8661 ( .A(n7963), .B(FPADDSUB_Data_array_SWR[20]), .Y(n7906) );
NAND3X2TS U8662 ( .A(n7907), .B(n7906), .C(n7905), .Y(n9944) );
NAND2X1TS U8663 ( .A(n9943), .B(n8065), .Y(n7910) );
NAND2X1TS U8664 ( .A(n9944), .B(n3701), .Y(n7909) );
NAND2X1TS U8665 ( .A(n8075), .B(FPADDSUB_DmP_mant_SFG_SWR[5]), .Y(n7908) );
NAND4X1TS U8666 ( .A(n7910), .B(n8078), .C(n7909), .D(n7908), .Y(n1202) );
AOI22X1TS U8667 ( .A0(n8048), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n8047),
.B1(FPADDSUB_Data_array_SWR[16]), .Y(n7914) );
NAND2X1TS U8668 ( .A(n8049), .B(FPADDSUB_Data_array_SWR[4]), .Y(n7912) );
NAND2X1TS U8669 ( .A(n7780), .B(FPADDSUB_Data_array_SWR[8]), .Y(n7911) );
NAND4X2TS U8670 ( .A(n7914), .B(n7913), .C(n7912), .D(n7911), .Y(n9945) );
NAND2X1TS U8671 ( .A(n9945), .B(n7772), .Y(n7917) );
NAND2X1TS U8672 ( .A(n9946), .B(n3701), .Y(n7916) );
NAND2X1TS U8673 ( .A(n8075), .B(FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n7915) );
NAND4X1TS U8674 ( .A(n7917), .B(n8078), .C(n7916), .D(n7915), .Y(n1203) );
NAND2X1TS U8675 ( .A(n9943), .B(n8043), .Y(n7920) );
NAND2X1TS U8676 ( .A(n9944), .B(n7795), .Y(n7919) );
NAND2X1TS U8677 ( .A(n8053), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n7918) );
NAND4X1TS U8678 ( .A(n7920), .B(n8056), .C(n7919), .D(n7918), .Y(n1187) );
NAND2X1TS U8679 ( .A(n9945), .B(n8043), .Y(n7923) );
NAND2X1TS U8680 ( .A(n9946), .B(n7795), .Y(n7922) );
NAND2X1TS U8681 ( .A(n8053), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n7921) );
NAND4X1TS U8682 ( .A(n7923), .B(n8056), .C(n7922), .D(n7921), .Y(n1186) );
NAND2X1TS U8683 ( .A(n9958), .B(n7772), .Y(n7926) );
NAND2X1TS U8684 ( .A(n9959), .B(n3701), .Y(n7925) );
NAND2X1TS U8685 ( .A(n8075), .B(FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n7924) );
INVX2TS U8686 ( .A(n7927), .Y(n7966) );
NAND2X1TS U8687 ( .A(n7962), .B(FPADDSUB_Data_array_SWR[21]), .Y(n7929) );
NAND2X1TS U8688 ( .A(n7963), .B(FPADDSUB_Data_array_SWR[17]), .Y(n7928) );
NAND4X2TS U8689 ( .A(n7930), .B(n7966), .C(n7929), .D(n7928), .Y(n9938) );
AOI22X1TS U8690 ( .A0(n7780), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n8049),
.B1(FPADDSUB_Data_array_SWR[1]), .Y(n7933) );
AOI22X1TS U8691 ( .A0(n8038), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n3693),
.B1(FPADDSUB_Data_array_SWR[13]), .Y(n7932) );
NAND2X1TS U8692 ( .A(n9938), .B(n2908), .Y(n7931) );
NAND3X2TS U8693 ( .A(n7933), .B(n7932), .C(n7931), .Y(n9952) );
NAND2X1TS U8694 ( .A(n9952), .B(n7772), .Y(n7937) );
NAND2X1TS U8695 ( .A(n9951), .B(n3701), .Y(n7936) );
NAND2X1TS U8696 ( .A(n8075), .B(FPADDSUB_DmP_mant_SFG_SWR[1]), .Y(n7935) );
NAND2X1TS U8697 ( .A(n9952), .B(n8043), .Y(n7940) );
NAND2X1TS U8698 ( .A(n9951), .B(n7795), .Y(n7939) );
NAND2X1TS U8699 ( .A(n8680), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n7938) );
NAND2X1TS U8700 ( .A(n8039), .B(FPADDSUB_Data_array_SWR[17]), .Y(n7944) );
NAND2X1TS U8701 ( .A(n7801), .B(FPADDSUB_Data_array_SWR[13]), .Y(n7943) );
NAND2X1TS U8702 ( .A(n8038), .B(FPADDSUB_Data_array_SWR[21]), .Y(n7942) );
NAND4X1TS U8703 ( .A(n7944), .B(n7943), .C(n7942), .D(n7941), .Y(n7951) );
NAND2X1TS U8704 ( .A(n7780), .B(FPADDSUB_Data_array_SWR[16]), .Y(n7948) );
NAND2X1TS U8705 ( .A(n8049), .B(FPADDSUB_Data_array_SWR[12]), .Y(n7947) );
NAND2X1TS U8706 ( .A(n8048), .B(FPADDSUB_Data_array_SWR[20]), .Y(n7946) );
NAND4X1TS U8707 ( .A(n7948), .B(n7947), .C(n7946), .D(n7945), .Y(n7952) );
MXI2X1TS U8708 ( .A(n7951), .B(n7952), .S0(FPADDSUB_left_right_SHT2), .Y(
n7950) );
INVX2TS U8709 ( .A(n7949), .Y(n7953) );
MXI2X1TS U8710 ( .A(n9929), .B(n9475), .S0(n8682), .Y(n1194) );
MXI2X1TS U8711 ( .A(n7952), .B(n7951), .S0(FPADDSUB_left_right_SHT2), .Y(
n7954) );
NAND2X1TS U8712 ( .A(n7955), .B(n9258), .Y(n7956) );
AOI22X1TS U8713 ( .A0(n8048), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n3693),
.B1(FPADDSUB_Data_array_SWR[21]), .Y(n7959) );
AOI22X1TS U8714 ( .A0(n7780), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n8049),
.B1(FPADDSUB_Data_array_SWR[9]), .Y(n7958) );
NAND3X2TS U8715 ( .A(n7960), .B(n7959), .C(n7958), .Y(n9935) );
NAND2X1TS U8716 ( .A(n7962), .B(FPADDSUB_Data_array_SWR[20]), .Y(n7965) );
NAND2X1TS U8717 ( .A(n7963), .B(FPADDSUB_Data_array_SWR[16]), .Y(n7964) );
NAND4X2TS U8718 ( .A(n7967), .B(n7966), .C(n7965), .D(n7964), .Y(n9936) );
NAND2X1TS U8719 ( .A(n9935), .B(n8043), .Y(n7970) );
OAI2BB1X1TS U8720 ( .A0N(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1N(n8075), .B0(
n8056), .Y(n7968) );
AOI21X1TS U8721 ( .A0(n7795), .A1(n9936), .B0(n7968), .Y(n7969) );
NAND2X1TS U8722 ( .A(n7970), .B(n7969), .Y(n1191) );
AOI22X1TS U8723 ( .A0(n8039), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n8049),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n7973) );
AOI22X1TS U8724 ( .A0(n8048), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n8047),
.B1(FPADDSUB_Data_array_SWR[12]), .Y(n7972) );
NAND3X1TS U8725 ( .A(n7973), .B(n7972), .C(n7971), .Y(n7980) );
NAND2X1TS U8726 ( .A(n7980), .B(n8065), .Y(n7976) );
NAND2X1TS U8727 ( .A(n7981), .B(n3701), .Y(n7975) );
NAND2X1TS U8728 ( .A(n8075), .B(FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(n7974) );
NAND4X1TS U8729 ( .A(n7976), .B(n8078), .C(n7975), .D(n7974), .Y(n1207) );
NAND2X1TS U8730 ( .A(n9935), .B(n8065), .Y(n7979) );
OAI2BB1X1TS U8731 ( .A0N(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1N(n8058), .B0(
n8078), .Y(n7977) );
AOI21X1TS U8732 ( .A0(n3701), .A1(n9936), .B0(n7977), .Y(n7978) );
NAND2X1TS U8733 ( .A(n7979), .B(n7978), .Y(n1198) );
NAND2X1TS U8734 ( .A(n7980), .B(n7788), .Y(n7984) );
NAND2X1TS U8735 ( .A(n7981), .B(n7795), .Y(n7983) );
NAND2X1TS U8736 ( .A(n8053), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n7982) );
NAND4X1TS U8737 ( .A(n7984), .B(n8056), .C(n7983), .D(n7982), .Y(n1182) );
AOI22X1TS U8738 ( .A0(n8038), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n8047),
.B1(FPADDSUB_Data_array_SWR[20]), .Y(n7986) );
AOI22X1TS U8739 ( .A0(n8039), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n8049),
.B1(FPADDSUB_Data_array_SWR[8]), .Y(n7985) );
NAND3X2TS U8740 ( .A(n7987), .B(n7986), .C(n7985), .Y(n9937) );
NAND2X1TS U8741 ( .A(n9937), .B(n8043), .Y(n7990) );
OAI2BB1X1TS U8742 ( .A0N(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1N(n8058), .B0(
n8056), .Y(n7988) );
AOI21X1TS U8743 ( .A0(n7795), .A1(n9938), .B0(n7988), .Y(n7989) );
NAND2X1TS U8744 ( .A(n7990), .B(n7989), .Y(n1190) );
XNOR2X1TS U8745 ( .A(FPADDSUB_intDY_EWSW[16]), .B(FPADDSUB_intDX_EWSW[16]),
.Y(n7993) );
XNOR2X1TS U8746 ( .A(FPADDSUB_intDY_EWSW[6]), .B(FPADDSUB_intDX_EWSW[6]),
.Y(n7998) );
XNOR2X1TS U8747 ( .A(FPADDSUB_intDX_EWSW[20]), .B(FPADDSUB_intDY_EWSW[20]),
.Y(n7997) );
XNOR2X1TS U8748 ( .A(FPADDSUB_intDX_EWSW[8]), .B(FPADDSUB_intDY_EWSW[8]),
.Y(n7996) );
XNOR2X1TS U8749 ( .A(FPADDSUB_intDY_EWSW[24]), .B(FPADDSUB_intDX_EWSW[24]),
.Y(n8001) );
XNOR2X1TS U8750 ( .A(FPADDSUB_intDX_EWSW[29]), .B(FPADDSUB_intDY_EWSW[29]),
.Y(n8000) );
XNOR2X1TS U8751 ( .A(FPADDSUB_intDX_EWSW[25]), .B(FPADDSUB_intDY_EWSW[25]),
.Y(n8004) );
XNOR2X1TS U8752 ( .A(FPADDSUB_intDX_EWSW[26]), .B(FPADDSUB_intDY_EWSW[26]),
.Y(n8003) );
NOR4X1TS U8753 ( .A(n8010), .B(n8009), .C(n8008), .D(n8007), .Y(n8031) );
XNOR2X1TS U8754 ( .A(FPADDSUB_intDY_EWSW[22]), .B(FPADDSUB_intDX_EWSW[22]),
.Y(n8013) );
XNOR2X1TS U8755 ( .A(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n8012) );
XNOR2X1TS U8756 ( .A(FPADDSUB_intDY_EWSW[2]), .B(FPADDSUB_intDX_EWSW[2]),
.Y(n8011) );
XNOR2X1TS U8757 ( .A(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n8018) );
XNOR2X1TS U8758 ( .A(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n8017) );
XNOR2X1TS U8759 ( .A(FPADDSUB_intDY_EWSW[5]), .B(FPADDSUB_intDX_EWSW[5]),
.Y(n8015) );
XNOR2X1TS U8760 ( .A(FPADDSUB_intDX_EWSW[15]), .B(FPADDSUB_intDY_EWSW[15]),
.Y(n8019) );
XNOR2X1TS U8761 ( .A(FPADDSUB_intDX_EWSW[0]), .B(FPADDSUB_intDY_EWSW[0]),
.Y(n8023) );
NAND3X1TS U8762 ( .A(n8025), .B(n8024), .C(n8023), .Y(n8026) );
NOR4X1TS U8763 ( .A(n8029), .B(n8028), .C(n8027), .D(n8026), .Y(n8030) );
NAND2X1TS U8764 ( .A(n8031), .B(n8030), .Y(n8032) );
NAND2BX1TS U8765 ( .AN(n8033), .B(n8032), .Y(n8034) );
AOI2BB2X1TS U8766 ( .B0(n8034), .B1(n9510), .A0N(n8033), .A1N(n8457), .Y(
n9904) );
INVX2TS U8767 ( .A(n8693), .Y(n8035) );
NAND2X2TS U8768 ( .A(n8087), .B(n8036), .Y(n1550) );
AOI22X1TS U8769 ( .A0(n8038), .A1(FPADDSUB_Data_array_SWR[15]), .B0(
FPADDSUB_Data_array_SWR[19]), .B1(n3693), .Y(n8041) );
AOI22X1TS U8770 ( .A0(n8039), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n8049),
.B1(FPADDSUB_Data_array_SWR[7]), .Y(n8040) );
NAND3X2TS U8771 ( .A(n8042), .B(n8041), .C(n8040), .Y(n9939) );
NAND2X1TS U8772 ( .A(n9939), .B(n8043), .Y(n8046) );
NAND2X1TS U8773 ( .A(n9940), .B(n7795), .Y(n8045) );
NAND2X1TS U8774 ( .A(n8053), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n8044) );
AOI22X1TS U8775 ( .A0(n8048), .A1(FPADDSUB_Data_array_SWR[14]), .B0(
FPADDSUB_Data_array_SWR[18]), .B1(n8047), .Y(n8051) );
AOI22X1TS U8776 ( .A0(n7780), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n8049),
.B1(FPADDSUB_Data_array_SWR[6]), .Y(n8050) );
NAND3X2TS U8777 ( .A(n8052), .B(n8051), .C(n8050), .Y(n9941) );
NAND2X1TS U8778 ( .A(n9941), .B(n7788), .Y(n8057) );
NAND2X1TS U8779 ( .A(n9942), .B(n7795), .Y(n8055) );
NAND2X1TS U8780 ( .A(n8053), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n8054) );
OAI2BB1X1TS U8781 ( .A0N(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1N(n8058), .B0(
n8078), .Y(n8059) );
AOI21X1TS U8782 ( .A0(n3701), .A1(n9938), .B0(n8059), .Y(n8060) );
NAND2X1TS U8783 ( .A(n8061), .B(n8060), .Y(n1199) );
AOI22X1TS U8784 ( .A0(n8081), .A1(FPMULT_Add_result[14]), .B0(
FPMULT_Sgf_normalized_result[13]), .B1(n8089), .Y(n8064) );
NAND2X1TS U8785 ( .A(n8093), .B(n1589), .Y(n8062) );
NAND2X1TS U8786 ( .A(n9939), .B(n8065), .Y(n8068) );
NAND2X1TS U8787 ( .A(n9940), .B(n3701), .Y(n8067) );
NAND2X1TS U8788 ( .A(n8075), .B(FPADDSUB_DmP_mant_SFG_SWR[7]), .Y(n8066) );
AOI22X1TS U8789 ( .A0(n8081), .A1(n1601), .B0(
FPMULT_Sgf_normalized_result[22]), .B1(n8080), .Y(n8074) );
INVX2TS U8790 ( .A(n1602), .Y(n8069) );
NAND2X1TS U8791 ( .A(n9941), .B(n7772), .Y(n8079) );
NAND2X1TS U8792 ( .A(n9942), .B(n3701), .Y(n8077) );
NAND2X1TS U8793 ( .A(n8075), .B(FPADDSUB_DmP_mant_SFG_SWR[6]), .Y(n8076) );
AOI22X1TS U8794 ( .A0(n8081), .A1(n1604), .B0(
FPMULT_Sgf_normalized_result[19]), .B1(n8080), .Y(n8086) );
INVX2TS U8795 ( .A(n1605), .Y(n8082) );
AOI22X1TS U8796 ( .A0(n8090), .A1(FPMULT_Add_result[13]), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n8089), .Y(n8096) );
NAND2X1TS U8797 ( .A(n8093), .B(n1588), .Y(n8094) );
AOI2BB2X1TS U8798 ( .B0(FPSENCOS_d_ff2_Z[12]), .B1(n8227), .A0N(n8226),
.A1N(n3619), .Y(n8107) );
AOI2BB2X1TS U8799 ( .B0(FPSENCOS_d_ff2_Z[21]), .B1(n8660), .A0N(n8226),
.A1N(n3597), .Y(n8108) );
AOI2BB2X1TS U8800 ( .B0(FPSENCOS_d_ff2_Z[16]), .B1(n8227), .A0N(n8226),
.A1N(n3578), .Y(n8109) );
AOI2BB2X1TS U8801 ( .B0(FPSENCOS_d_ff2_Z[9]), .B1(n8667), .A0N(n8226), .A1N(
n3608), .Y(n8110) );
AOI2BB2X1TS U8802 ( .B0(FPSENCOS_d_ff2_Z[6]), .B1(n8227), .A0N(n8226), .A1N(
n3585), .Y(n8111) );
AOI2BB2X1TS U8803 ( .B0(FPSENCOS_d_ff2_Z[4]), .B1(n8667), .A0N(n8226), .A1N(
n3587), .Y(n8112) );
AOI2BB2X1TS U8804 ( .B0(FPSENCOS_d_ff2_Z[15]), .B1(n8667), .A0N(n8226),
.A1N(n3589), .Y(n8113) );
NAND2X1TS U8805 ( .A(n8114), .B(FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n8122) );
AOI21X1TS U8806 ( .A0(n8118), .A1(n8117), .B0(n8116), .Y(n8119) );
CLKMX2X2TS U8807 ( .A(n8341), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .S0(n8123),
.Y(n1320) );
OAI22X1TS U8808 ( .A0(n8125), .A1(n8124), .B0(n9264), .B1(n2687), .Y(n8134)
);
AOI2BB2X1TS U8809 ( .B0(n8129), .B1(n8128), .A0N(n8127), .A1N(n8126), .Y(
n8133) );
NAND3BX2TS U8810 ( .AN(n8134), .B(n8133), .C(n8132), .Y(n1799) );
XNOR2X1TS U8811 ( .A(add_x_246_A_4_), .B(add_x_246_n21), .Y(n8136) );
CLKMX2X2TS U8812 ( .A(n8136), .B(FPMULT_Add_result[4]), .S0(n9750), .Y(n1620) );
AOI2BB2X1TS U8813 ( .B0(FPSENCOS_d_ff2_Z[19]), .B1(n8227), .A0N(n8147),
.A1N(n3576), .Y(n8137) );
AOI2BB2X1TS U8814 ( .B0(FPSENCOS_d_ff2_Z[3]), .B1(n8227), .A0N(n8147), .A1N(
n3572), .Y(n8138) );
AOI2BB2X1TS U8815 ( .B0(FPSENCOS_d_ff2_Z[10]), .B1(n8227), .A0N(n8147),
.A1N(n3573), .Y(n8139) );
AOI2BB2X1TS U8816 ( .B0(FPSENCOS_d_ff2_Z[0]), .B1(n8227), .A0N(n8147), .A1N(
n3569), .Y(n8140) );
AOI2BB2X1TS U8817 ( .B0(FPSENCOS_d_ff2_Z[14]), .B1(n8593), .A0N(n8147),
.A1N(n3588), .Y(n8142) );
AOI2BB2X1TS U8818 ( .B0(FPSENCOS_d_ff2_Z[2]), .B1(n8660), .A0N(n8147), .A1N(
n3570), .Y(n8143) );
AOI2BB2X1TS U8819 ( .B0(FPSENCOS_d_ff2_Z[17]), .B1(n8593), .A0N(n8147),
.A1N(n3581), .Y(n8144) );
AOI2BB2X1TS U8820 ( .B0(FPSENCOS_d_ff2_Z[18]), .B1(n8227), .A0N(n8147),
.A1N(n3586), .Y(n8145) );
AOI2BB2X1TS U8821 ( .B0(FPSENCOS_d_ff2_Z[13]), .B1(n8227), .A0N(n8147),
.A1N(n3622), .Y(n8146) );
AOI2BB2X1TS U8822 ( .B0(FPSENCOS_d_ff2_Z[1]), .B1(n8660), .A0N(n8147), .A1N(
n3584), .Y(n8148) );
NAND2X1TS U8823 ( .A(n8765), .B(FPSENCOS_d_ff3_sh_x_out[2]), .Y(n8152) );
NAND2X1TS U8824 ( .A(n8187), .B(FPSENCOS_d_ff3_LUT_out[2]), .Y(n8151) );
NAND2X1TS U8825 ( .A(n8764), .B(FPSENCOS_d_ff3_sh_y_out[2]), .Y(n8150) );
AOI22X1TS U8826 ( .A0(n8190), .A1(Data_2[2]), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n8189), .Y(n8149) );
NAND2X1TS U8827 ( .A(n8173), .B(FPSENCOS_d_ff3_sh_x_out[9]), .Y(n8156) );
NAND2X1TS U8828 ( .A(n8174), .B(FPSENCOS_d_ff3_LUT_out[9]), .Y(n8155) );
NAND2X1TS U8829 ( .A(n8175), .B(FPSENCOS_d_ff3_sh_y_out[9]), .Y(n8154) );
AOI22X1TS U8830 ( .A0(n8177), .A1(Data_2[9]), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n8176), .Y(n8153) );
NAND2X1TS U8831 ( .A(n8765), .B(FPSENCOS_d_ff3_sh_x_out[0]), .Y(n8160) );
NAND2X1TS U8832 ( .A(n8187), .B(FPSENCOS_d_ff3_LUT_out[0]), .Y(n8159) );
NAND2X1TS U8833 ( .A(n8764), .B(FPSENCOS_d_ff3_sh_y_out[0]), .Y(n8158) );
AOI22X1TS U8834 ( .A0(n8190), .A1(Data_2[0]), .B0(n8189), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n8157) );
NAND4X1TS U8835 ( .A(n8160), .B(n8159), .C(n8158), .D(n8157), .Y(n1845) );
NAND2X1TS U8836 ( .A(n8765), .B(FPSENCOS_d_ff2_Y[0]), .Y(n8164) );
NAND2X1TS U8837 ( .A(n8187), .B(FPSENCOS_d_ff2_Z[0]), .Y(n8163) );
NAND2X1TS U8838 ( .A(n8764), .B(FPSENCOS_d_ff2_X[0]), .Y(n8162) );
AOI22X1TS U8839 ( .A0(n8190), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n8189), .Y(n8161) );
NAND2X1TS U8840 ( .A(n8173), .B(FPSENCOS_d_ff2_Y[9]), .Y(n8168) );
NAND2X1TS U8841 ( .A(n8174), .B(FPSENCOS_d_ff2_Z[9]), .Y(n8167) );
NAND2X1TS U8842 ( .A(n8175), .B(FPSENCOS_d_ff2_X[9]), .Y(n8166) );
AOI22X1TS U8843 ( .A0(n8177), .A1(Data_1[9]), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n8176), .Y(n8165) );
NAND2X1TS U8844 ( .A(n8765), .B(FPSENCOS_d_ff2_Y[2]), .Y(n8172) );
NAND2X1TS U8845 ( .A(n8187), .B(FPSENCOS_d_ff2_Z[2]), .Y(n8171) );
NAND2X1TS U8846 ( .A(n8764), .B(FPSENCOS_d_ff2_X[2]), .Y(n8170) );
AOI22X1TS U8847 ( .A0(n8190), .A1(Data_1[2]), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n8189), .Y(n8169) );
NAND2X1TS U8848 ( .A(n8173), .B(FPSENCOS_d_ff2_Y[20]), .Y(n8181) );
NAND2X1TS U8849 ( .A(n8174), .B(FPSENCOS_d_ff2_Z[20]), .Y(n8180) );
NAND2X1TS U8850 ( .A(n8175), .B(FPSENCOS_d_ff2_X[20]), .Y(n8179) );
AOI22X1TS U8851 ( .A0(n8177), .A1(Data_1[20]), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n8176), .Y(n8178) );
NAND4X1TS U8852 ( .A(n8181), .B(n8180), .C(n8179), .D(n8178), .Y(n1923) );
NAND2X1TS U8853 ( .A(n8765), .B(FPSENCOS_d_ff2_Y[1]), .Y(n8185) );
NAND2X1TS U8854 ( .A(n8187), .B(FPSENCOS_d_ff2_Z[1]), .Y(n8184) );
NAND2X1TS U8855 ( .A(n8764), .B(FPSENCOS_d_ff2_X[1]), .Y(n8183) );
AOI22X1TS U8856 ( .A0(n8767), .A1(Data_1[1]), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n8189), .Y(n8182) );
NAND2X1TS U8857 ( .A(n8186), .B(FPSENCOS_d_ff2_Y[19]), .Y(n8194) );
NAND2X1TS U8858 ( .A(n8187), .B(FPSENCOS_d_ff2_Z[19]), .Y(n8193) );
NAND2X1TS U8859 ( .A(n8188), .B(FPSENCOS_d_ff2_X[19]), .Y(n8192) );
AOI22X1TS U8860 ( .A0(n8190), .A1(Data_1[19]), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n8189), .Y(n8191) );
NAND4X1TS U8861 ( .A(n8194), .B(n8193), .C(n8192), .D(n8191), .Y(n1924) );
NAND2X1TS U8862 ( .A(n8208), .B(FPSENCOS_d_ff2_Y[28]), .Y(n8199) );
NAND2X1TS U8863 ( .A(n8209), .B(FPSENCOS_d_ff2_Z[28]), .Y(n8198) );
NAND2X1TS U8864 ( .A(n8210), .B(FPSENCOS_d_ff2_X[28]), .Y(n8197) );
AOI22X1TS U8865 ( .A0(n8232), .A1(Data_1[28]), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n8211), .Y(n8196) );
NAND4X1TS U8866 ( .A(n8199), .B(n8198), .C(n8197), .D(n8196), .Y(n1915) );
NAND2X1TS U8867 ( .A(n8208), .B(FPSENCOS_d_ff2_Y[30]), .Y(n8203) );
NAND2X1TS U8868 ( .A(n8209), .B(FPSENCOS_d_ff2_Z[30]), .Y(n8202) );
NAND2X1TS U8869 ( .A(n8210), .B(FPSENCOS_d_ff2_X[30]), .Y(n8201) );
AOI22X1TS U8870 ( .A0(n8232), .A1(Data_1[30]), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n8211), .Y(n8200) );
NAND4X1TS U8871 ( .A(n8203), .B(n8202), .C(n8201), .D(n8200), .Y(n1913) );
NAND2X1TS U8872 ( .A(n8208), .B(FPSENCOS_d_ff2_Y[29]), .Y(n8207) );
NAND2X1TS U8873 ( .A(n8209), .B(FPSENCOS_d_ff2_Z[29]), .Y(n8206) );
NAND2X1TS U8874 ( .A(n8210), .B(FPSENCOS_d_ff2_X[29]), .Y(n8205) );
AOI22X1TS U8875 ( .A0(n8232), .A1(Data_1[29]), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n8211), .Y(n8204) );
NAND2X1TS U8876 ( .A(n8208), .B(FPSENCOS_d_ff2_Y[27]), .Y(n8215) );
NAND2X1TS U8877 ( .A(n8209), .B(FPSENCOS_d_ff2_Z[27]), .Y(n8214) );
NAND2X1TS U8878 ( .A(n8210), .B(FPSENCOS_d_ff2_X[27]), .Y(n8213) );
AOI22X1TS U8879 ( .A0(n8232), .A1(Data_1[27]), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n8211), .Y(n8212) );
NAND4X1TS U8880 ( .A(n8215), .B(n8214), .C(n8213), .D(n8212), .Y(n1916) );
NAND2X1TS U8881 ( .A(n8216), .B(FPSENCOS_d_ff2_Y[12]), .Y(n8224) );
NAND2X1TS U8882 ( .A(n8217), .B(FPSENCOS_d_ff2_Z[12]), .Y(n8223) );
NAND2X1TS U8883 ( .A(n8218), .B(FPSENCOS_d_ff2_X[12]), .Y(n8222) );
AOI22X1TS U8884 ( .A0(n8220), .A1(Data_1[12]), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n8219), .Y(n8221) );
BUFX12TS U8885 ( .A(n8507), .Y(n8499) );
MXI2X1TS U8886 ( .A(n8781), .B(FPSENCOS_d_ff3_LUT_out[12]), .S0(n8499), .Y(
n8225) );
AOI2BB2X1TS U8887 ( .B0(FPSENCOS_d_ff2_Z[11]), .B1(n8227), .A0N(n8226),
.A1N(n3614), .Y(n8228) );
XNOR2X1TS U8888 ( .A(FPSENCOS_cont_var_out[0]), .B(FPSENCOS_d_ff3_sign_out),
.Y(n8229) );
AOI2BB2X1TS U8889 ( .B0(FPADDSUB_intAS), .B1(n8766), .A0N(n8230), .A1N(n8229), .Y(n8231) );
AO22X2TS U8890 ( .A0(n8662), .A1(FPSENCOS_d_ff_Yn[17]), .B0(
FPSENCOS_d_ff2_Y[17]), .B1(n8233), .Y(n1875) );
BUFX12TS U8891 ( .A(n8507), .Y(n8505) );
MXI2X1TS U8892 ( .A(n8234), .B(FPSENCOS_d_ff3_LUT_out[7]), .S0(n8505), .Y(
n8235) );
CLKMX2X2TS U8893 ( .A(n8236), .B(FPMULT_P_Sgf[11]), .S0(n9751), .Y(n9208) );
NOR2X2TS U8894 ( .A(n3639), .B(n3630), .Y(n8316) );
MXI2X1TS U8895 ( .A(n8239), .B(FPSENCOS_d_ff3_LUT_out[26]), .S0(n8607), .Y(
n8240) );
BUFX3TS U8896 ( .A(n9971), .Y(n9780) );
BUFX3TS U8897 ( .A(n2911), .Y(n9785) );
CLKBUFX3TS U8898 ( .A(n8251), .Y(n9754) );
BUFX3TS U8899 ( .A(n8251), .Y(n9758) );
CLKBUFX3TS U8900 ( .A(n8251), .Y(n9757) );
BUFX3TS U8901 ( .A(n9971), .Y(n9781) );
BUFX3TS U8902 ( .A(n2911), .Y(n9783) );
CLKBUFX3TS U8903 ( .A(n9773), .Y(n9772) );
BUFX4TS U8904 ( .A(n8281), .Y(n8296) );
AOI22X1TS U8905 ( .A0(mult_result[28]), .A1(n8296), .B0(cordic_result[28]),
.B1(n8278), .Y(n8253) );
OAI21X1TS U8906 ( .A0(n8752), .A1(n8280), .B0(n8253), .Y(op_result[28]) );
AOI22X1TS U8907 ( .A0(mult_result[29]), .A1(n8296), .B0(cordic_result[29]),
.B1(n8278), .Y(n8254) );
OAI21X1TS U8908 ( .A0(n8748), .A1(n8280), .B0(n8254), .Y(op_result[29]) );
AOI22X1TS U8909 ( .A0(mult_result[24]), .A1(n8296), .B0(cordic_result[24]),
.B1(n8278), .Y(n8255) );
OAI21X1TS U8910 ( .A0(n8754), .A1(n8280), .B0(n8255), .Y(op_result[24]) );
AOI22X1TS U8911 ( .A0(mult_result[23]), .A1(n8296), .B0(cordic_result[23]),
.B1(n8278), .Y(n8256) );
OAI21X1TS U8912 ( .A0(n8743), .A1(n8280), .B0(n8256), .Y(op_result[23]) );
AOI22X1TS U8913 ( .A0(mult_result[26]), .A1(n8296), .B0(cordic_result[26]),
.B1(n8278), .Y(n8257) );
OAI21X1TS U8914 ( .A0(n8749), .A1(n8280), .B0(n8257), .Y(op_result[26]) );
AOI22X1TS U8915 ( .A0(mult_result[27]), .A1(n8296), .B0(cordic_result[27]),
.B1(n8278), .Y(n8258) );
OAI21X1TS U8916 ( .A0(n8751), .A1(n8280), .B0(n8258), .Y(op_result[27]) );
AOI22X1TS U8917 ( .A0(mult_result[25]), .A1(n8296), .B0(cordic_result[25]),
.B1(n8278), .Y(n8259) );
OAI21X1TS U8918 ( .A0(n8750), .A1(n8280), .B0(n8259), .Y(op_result[25]) );
BUFX6TS U8919 ( .A(n8281), .Y(n8290) );
AOI22X1TS U8920 ( .A0(cordic_result[11]), .A1(n8274), .B0(n8290), .B1(
mult_result[11]), .Y(n8260) );
OAI21X1TS U8921 ( .A0(n7274), .A1(n8276), .B0(n8260), .Y(op_result[11]) );
AOI22X1TS U8922 ( .A0(cordic_result[10]), .A1(n8274), .B0(n8290), .B1(
mult_result[10]), .Y(n8261) );
OAI21X1TS U8923 ( .A0(n2694), .A1(n8276), .B0(n8261), .Y(op_result[10]) );
AOI22X1TS U8924 ( .A0(mult_result[31]), .A1(n8296), .B0(cordic_result[31]),
.B1(n8286), .Y(n8262) );
OAI21X1TS U8925 ( .A0(n8760), .A1(n8269), .B0(n8262), .Y(op_result[31]) );
AOI22X1TS U8926 ( .A0(mult_result[30]), .A1(n8296), .B0(cordic_result[30]),
.B1(n8286), .Y(n8263) );
OAI21X1TS U8927 ( .A0(n8763), .A1(n8269), .B0(n8263), .Y(op_result[30]) );
AOI22X1TS U8928 ( .A0(cordic_result[14]), .A1(n8274), .B0(n8277), .B1(
mult_result[14]), .Y(n8264) );
OAI21X1TS U8929 ( .A0(n8722), .A1(n8276), .B0(n8264), .Y(op_result[14]) );
AOI22X1TS U8930 ( .A0(cordic_result[17]), .A1(n8274), .B0(n8277), .B1(
mult_result[17]), .Y(n8265) );
OAI21X1TS U8931 ( .A0(n8727), .A1(n8276), .B0(n8265), .Y(op_result[17]) );
AOI22X1TS U8932 ( .A0(cordic_result[18]), .A1(n8274), .B0(n8277), .B1(
mult_result[18]), .Y(n8266) );
OAI21X1TS U8933 ( .A0(n8747), .A1(n8276), .B0(n8266), .Y(op_result[18]) );
AOI22X1TS U8934 ( .A0(cordic_result[16]), .A1(n8274), .B0(n8277), .B1(
mult_result[16]), .Y(n8267) );
OAI21X1TS U8935 ( .A0(n8721), .A1(n8276), .B0(n8267), .Y(op_result[16]) );
AOI22X1TS U8936 ( .A0(cordic_result[15]), .A1(n8274), .B0(n8277), .B1(
mult_result[15]), .Y(n8268) );
OAI21X1TS U8937 ( .A0(n8718), .A1(n8276), .B0(n8268), .Y(op_result[15]) );
AOI22X1TS U8938 ( .A0(cordic_result[8]), .A1(n8291), .B0(n8290), .B1(
mult_result[8]), .Y(n8270) );
OAI21X1TS U8939 ( .A0(n8717), .A1(n8293), .B0(n8270), .Y(op_result[8]) );
AOI22X1TS U8940 ( .A0(n2921), .A1(n8291), .B0(n8290), .B1(mult_result[9]),
.Y(n8271) );
OAI21X1TS U8941 ( .A0(n8729), .A1(n8293), .B0(n8271), .Y(op_result[9]) );
AOI22X1TS U8942 ( .A0(n2922), .A1(n8274), .B0(n8290), .B1(mult_result[12]),
.Y(n8272) );
OAI21X1TS U8943 ( .A0(n8726), .A1(n8276), .B0(n8272), .Y(op_result[12]) );
AOI22X1TS U8944 ( .A0(n2923), .A1(n8274), .B0(n8277), .B1(mult_result[13]),
.Y(n8273) );
OAI21X1TS U8945 ( .A0(n8720), .A1(n8276), .B0(n8273), .Y(op_result[13]) );
AOI22X1TS U8946 ( .A0(n2924), .A1(n8274), .B0(n8277), .B1(mult_result[19]),
.Y(n8275) );
OAI21X1TS U8947 ( .A0(n8724), .A1(n8276), .B0(n8275), .Y(op_result[19]) );
AOI22X1TS U8948 ( .A0(n2925), .A1(n8278), .B0(n8277), .B1(mult_result[22]),
.Y(n8279) );
OAI21X1TS U8949 ( .A0(n8745), .A1(n8280), .B0(n8279), .Y(op_result[22]) );
AOI22X1TS U8950 ( .A0(cordic_result[1]), .A1(n8286), .B0(n8281), .B1(
mult_result[1]), .Y(n8282) );
OAI21X1TS U8951 ( .A0(n8746), .A1(n8293), .B0(n8282), .Y(op_result[1]) );
AOI22X1TS U8952 ( .A0(cordic_result[5]), .A1(n8291), .B0(n8290), .B1(
mult_result[5]), .Y(n8283) );
OAI21X1TS U8953 ( .A0(n8733), .A1(n8293), .B0(n8283), .Y(op_result[5]) );
AOI22X1TS U8954 ( .A0(cordic_result[0]), .A1(n8286), .B0(n8281), .B1(
mult_result[0]), .Y(n8284) );
OAI21X1TS U8955 ( .A0(n8735), .A1(n8293), .B0(n8284), .Y(op_result[0]) );
AOI22X1TS U8956 ( .A0(cordic_result[3]), .A1(n8291), .B0(n8290), .B1(
mult_result[3]), .Y(n8285) );
OAI21X1TS U8957 ( .A0(n8732), .A1(n8293), .B0(n8285), .Y(op_result[3]) );
AOI22X1TS U8958 ( .A0(cordic_result[2]), .A1(n8286), .B0(n8281), .B1(
mult_result[2]), .Y(n8287) );
OAI21X1TS U8959 ( .A0(n8744), .A1(n8293), .B0(n8287), .Y(op_result[2]) );
AOI22X1TS U8960 ( .A0(cordic_result[7]), .A1(n8291), .B0(n8290), .B1(
mult_result[7]), .Y(n8288) );
OAI21X1TS U8961 ( .A0(n8723), .A1(n8293), .B0(n8288), .Y(op_result[7]) );
AOI22X1TS U8962 ( .A0(cordic_result[6]), .A1(n8291), .B0(n8290), .B1(
mult_result[6]), .Y(n8289) );
OAI21X1TS U8963 ( .A0(n8725), .A1(n8293), .B0(n8289), .Y(op_result[6]) );
AOI22X1TS U8964 ( .A0(cordic_result[4]), .A1(n8291), .B0(n8290), .B1(
mult_result[4]), .Y(n8292) );
OAI21X1TS U8965 ( .A0(n8719), .A1(n8293), .B0(n8292), .Y(op_result[4]) );
AOI22X1TS U8966 ( .A0(n8297), .A1(n8296), .B0(n8295), .B1(ready_add_subt),
.Y(n8298) );
INVX2TS U8967 ( .A(Data_2[27]), .Y(n9837) );
AOI21X1TS U8968 ( .A0(FPMULT_zero_flag), .A1(n8302), .B0(n8301), .Y(n8305)
);
OAI21X1TS U8969 ( .A0(n8303), .A1(n9839), .B0(FPMULT_FS_Module_state_reg[3]),
.Y(n8304) );
NAND2X2TS U8970 ( .A(n8305), .B(n8304), .Y(n1695) );
NOR2X1TS U8971 ( .A(n1695), .B(n9539), .Y(n9540) );
NOR2X1TS U8972 ( .A(n8583), .B(n8306), .Y(n8308) );
OAI21X1TS U8973 ( .A0(n8308), .A1(n8494), .B0(n8307), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
MXI2X1TS U8974 ( .A(n8309), .B(n9465), .S0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n8312) );
OAI21X1TS U8975 ( .A0(n8312), .A1(n8311), .B0(n8310), .Y(n2151) );
INVX2TS U8976 ( .A(n8781), .Y(n8313) );
MXI2X1TS U8977 ( .A(n8509), .B(FPSENCOS_d_ff3_LUT_out[21]), .S0(n8607), .Y(
n8315) );
INVX2TS U8978 ( .A(n8316), .Y(n8317) );
NAND2X1TS U8979 ( .A(n8780), .B(n8317), .Y(n8319) );
AOI22X1TS U8980 ( .A0(n8784), .A1(n3639), .B0(FPSENCOS_d_ff3_LUT_out[4]),
.B1(n8790), .Y(n8318) );
INVX2TS U8981 ( .A(n8320), .Y(n8321) );
AOI22X1TS U8982 ( .A0(n8789), .A1(n8321), .B0(FPSENCOS_d_ff3_LUT_out[24]),
.B1(n8790), .Y(n8322) );
OAI21X1TS U8983 ( .A0(n3630), .A1(n8323), .B0(n8322), .Y(n2118) );
NAND2X1TS U8984 ( .A(n8590), .B(FPSENCOS_d_ff_Yn[28]), .Y(n8324) );
OAI21X1TS U8985 ( .A0(n2833), .A1(n9247), .B0(n8324), .Y(n1858) );
XOR2X1TS U8986 ( .A(n8325), .B(FPSENCOS_d_ff_Xn[31]), .Y(n8329) );
XNOR2X1TS U8987 ( .A(n8325), .B(FPSENCOS_d_ff_Yn[31]), .Y(n8327) );
AOI22X1TS U8988 ( .A0(n8679), .A1(n8327), .B0(n8326), .B1(cordic_result[31]),
.Y(n8328) );
OAI21X1TS U8989 ( .A0(n2686), .A1(n8329), .B0(n8328), .Y(n1697) );
NOR2X2TS U8990 ( .A(intadd_734_n1), .B(FPSENCOS_d_ff2_X[27]), .Y(n8671) );
NAND2X2TS U8991 ( .A(n8671), .B(n9102), .Y(n8670) );
NOR2X1TS U8992 ( .A(n8684), .B(n8330), .Y(n8331) );
NOR2X2TS U8993 ( .A(intadd_733_n1), .B(FPSENCOS_d_ff2_Y[27]), .Y(n8674) );
NAND2X2TS U8994 ( .A(n8674), .B(n9247), .Y(n8673) );
NOR2X1TS U8995 ( .A(n8686), .B(n8332), .Y(n8333) );
AOI22X1TS U8996 ( .A0(n8343), .A1(FPADDSUB_Shift_amount_SHT1_EWR[4]), .B0(
n2908), .B1(n8342), .Y(n8335) );
OAI21X1TS U8997 ( .A0(n8339), .A1(n2646), .B0(n8338), .Y(n2077) );
NAND2X1TS U8998 ( .A(n8341), .B(n8340), .Y(n8345) );
MXI2X1TS U8999 ( .A(n9511), .B(sub_x_17_n206), .S0(n2836), .Y(n1351) );
NAND2X1TS U9000 ( .A(n9843), .B(n9248), .Y(n1691) );
INVX2TS U9001 ( .A(Data_1[31]), .Y(n8578) );
MXI2X1TS U9002 ( .A(n8578), .B(n9480), .S0(n8445), .Y(n1658) );
NOR2X1TS U9003 ( .A(n8347), .B(n8346), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
XNOR2X1TS U9004 ( .A(n8494), .B(FPSENCOS_cont_iter_out[0]), .Y(n2143) );
XNOR2X1TS U9005 ( .A(n8495), .B(n3639), .Y(n2141) );
INVX2TS U9006 ( .A(FPSENCOS_d_ff3_LUT_out[19]), .Y(n8348) );
MXI2X1TS U9007 ( .A(n8349), .B(n8348), .S0(n8607), .Y(n2121) );
NAND2X1TS U9008 ( .A(n9514), .B(n8350), .Y(n9895) );
NAND2X1TS U9009 ( .A(n9514), .B(n8351), .Y(n9893) );
NAND2X1TS U9010 ( .A(n9514), .B(n8352), .Y(n9949) );
NAND2X1TS U9011 ( .A(n9514), .B(n8353), .Y(n9907) );
BUFX4TS U9012 ( .A(n2545), .Y(n8372) );
NAND2X1TS U9013 ( .A(n8372), .B(n2458), .Y(n8355) );
NAND3X1TS U9014 ( .A(n8355), .B(n8354), .C(n9623), .Y(n8537) );
NAND2X1TS U9015 ( .A(n8372), .B(n2487), .Y(n8357) );
NAND3X1TS U9016 ( .A(n8357), .B(n8356), .C(n9598), .Y(n8406) );
NAND2X1TS U9017 ( .A(n8372), .B(n2491), .Y(n8359) );
NAND3X1TS U9018 ( .A(n8359), .B(n8358), .C(n9597), .Y(n8404) );
NAND2X1TS U9019 ( .A(n8372), .B(n2451), .Y(n8361) );
NAND3X1TS U9020 ( .A(n8361), .B(n8360), .C(n9617), .Y(n8405) );
NAND2X1TS U9021 ( .A(n8372), .B(n2470), .Y(n8363) );
NAND3X1TS U9022 ( .A(n8363), .B(n8362), .C(n9629), .Y(n8403) );
NAND2X1TS U9023 ( .A(n8372), .B(n2457), .Y(n8365) );
NAND3X1TS U9024 ( .A(n8365), .B(n8364), .C(n9618), .Y(n8534) );
NAND2X1TS U9025 ( .A(n8372), .B(n2452), .Y(n8367) );
NAND3X1TS U9026 ( .A(n8367), .B(n8366), .C(n9612), .Y(n8538) );
NAND2X1TS U9027 ( .A(n9513), .B(n8538), .Y(n9917) );
NAND2X1TS U9028 ( .A(n8372), .B(n2498), .Y(n8369) );
NAND3X1TS U9029 ( .A(n8369), .B(n8368), .C(n9607), .Y(n8407) );
NAND2X1TS U9030 ( .A(n9513), .B(n8407), .Y(n9919) );
NAND2X1TS U9031 ( .A(n8372), .B(n2492), .Y(n8371) );
NAND3X1TS U9032 ( .A(n8371), .B(n8370), .C(n9631), .Y(n8533) );
NAND2X1TS U9033 ( .A(n9513), .B(n8533), .Y(n9915) );
NAND2X1TS U9034 ( .A(n8372), .B(n2490), .Y(n8374) );
NAND3X1TS U9035 ( .A(n8374), .B(n8373), .C(n9627), .Y(n8540) );
NAND2X1TS U9036 ( .A(n9513), .B(n8540), .Y(n9918) );
XNOR2X1TS U9037 ( .A(n8375), .B(n9245), .Y(n2139) );
MXI2X1TS U9038 ( .A(n8385), .B(n9471), .S0(n9970), .Y(overflow_flag) );
CLKMX2X2TS U9039 ( .A(FPADDSUB_SIGN_FLAG_NRM), .B(FPADDSUB_SIGN_FLAG_SFG),
.S0(n2837), .Y(n1360) );
CLKMX2X2TS U9040 ( .A(FPADDSUB_DMP_exp_NRM_EW[0]), .B(FPADDSUB_DMP_SFG[23]),
.S0(n2836), .Y(n1456) );
CLKMX2X2TS U9041 ( .A(FPADDSUB_DMP_exp_NRM_EW[6]), .B(FPADDSUB_DMP_SFG[29]),
.S0(n2836), .Y(n1426) );
CLKMX2X2TS U9042 ( .A(FPADDSUB_DMP_exp_NRM_EW[7]), .B(FPADDSUB_DMP_SFG[30]),
.S0(n2837), .Y(n1421) );
CLKMX2X2TS U9043 ( .A(FPADDSUB_DMP_exp_NRM_EW[5]), .B(FPADDSUB_DMP_SFG[28]),
.S0(n2837), .Y(n1431) );
CLKMX2X2TS U9044 ( .A(FPADDSUB_DMP_exp_NRM_EW[1]), .B(FPADDSUB_DMP_SFG[24]),
.S0(n2837), .Y(n1451) );
CLKMX2X2TS U9045 ( .A(FPADDSUB_DMP_exp_NRM_EW[2]), .B(FPADDSUB_DMP_SFG[25]),
.S0(n2837), .Y(n1446) );
CLKMX2X2TS U9046 ( .A(FPADDSUB_DMP_exp_NRM_EW[4]), .B(FPADDSUB_DMP_SFG[27]),
.S0(n2837), .Y(n1436) );
CLKMX2X2TS U9047 ( .A(FPADDSUB_DMP_exp_NRM_EW[3]), .B(FPADDSUB_DMP_SFG[26]),
.S0(n2837), .Y(n1441) );
NAND2X1TS U9048 ( .A(n8377), .B(n2435), .Y(n8380) );
NAND2X1TS U9049 ( .A(n8378), .B(n2462), .Y(n8379) );
NAND3X1TS U9050 ( .A(n8380), .B(n8379), .C(n9624), .Y(n8425) );
NAND2X1TS U9051 ( .A(n7811), .B(n8425), .Y(n9851) );
NAND2X1TS U9052 ( .A(n8384), .B(n8426), .Y(n9852) );
NAND2X1TS U9053 ( .A(n8384), .B(n8381), .Y(n9858) );
NAND2X1TS U9054 ( .A(n8384), .B(n8440), .Y(n9854) );
NAND2X1TS U9055 ( .A(n8384), .B(n8442), .Y(n9857) );
NAND2X1TS U9056 ( .A(n8384), .B(n8383), .Y(n9860) );
MXI2X1TS U9057 ( .A(FPMULT_Sgf_normalized_result[0]), .B(n3582), .S0(n9750),
.Y(n1624) );
OAI21X1TS U9058 ( .A0(n8387), .A1(n8386), .B0(n8385), .Y(n8388) );
MXI2X1TS U9059 ( .A(n8388), .B(n9373), .S0(n8468), .Y(n1483) );
MXI2X1TS U9060 ( .A(n9469), .B(n8389), .S0(n8441), .Y(n1449) );
NOR2X1TS U9061 ( .A(add_x_246_A_1_), .B(add_x_246_A_0_), .Y(n8390) );
XOR2X1TS U9062 ( .A(add_x_246_A_2_), .B(n8390), .Y(n8391) );
CLKMX2X2TS U9063 ( .A(n8391), .B(FPMULT_Add_result[2]), .S0(n9750), .Y(n1622) );
AOI2BB2X1TS U9064 ( .B0(add_x_246_A_1_), .B1(n9092), .A0N(n9092), .A1N(
add_x_246_A_1_), .Y(n8392) );
CLKMX2X2TS U9065 ( .A(n8392), .B(FPMULT_Add_result[1]), .S0(n9750), .Y(n1623) );
ADDHX1TS U9066 ( .A(FPMULT_Sgf_normalized_result[6]), .B(add_x_246_n19),
.CO(n6586), .S(n8393) );
CLKMX2X2TS U9067 ( .A(FPADDSUB_DmP_mant_SHT1_SW[1]), .B(n8394), .S0(n8402),
.Y(n1292) );
CLKMX2X2TS U9068 ( .A(FPADDSUB_DmP_mant_SHT1_SW[18]), .B(n8395), .S0(n8402),
.Y(n1402) );
CLKMX2X2TS U9069 ( .A(FPADDSUB_DMP_SHT1_EWSW[20]), .B(n8396), .S0(n8402),
.Y(n1230) );
CLKMX2X2TS U9070 ( .A(FPADDSUB_DmP_mant_SHT1_SW[3]), .B(n8397), .S0(n8402),
.Y(n1329) );
CLKMX2X2TS U9071 ( .A(FPADDSUB_DmP_mant_SHT1_SW[19]), .B(n8398), .S0(n8402),
.Y(n1396) );
CLKMX2X2TS U9072 ( .A(FPADDSUB_DmP_mant_SHT1_SW[2]), .B(n8399), .S0(n8402),
.Y(n1313) );
CLKMX2X2TS U9073 ( .A(FPADDSUB_DmP_mant_SHT1_SW[0]), .B(n8400), .S0(n8402),
.Y(n1299) );
CLKMX2X2TS U9074 ( .A(FPADDSUB_DMP_SHT1_EWSW[19]), .B(n8401), .S0(n8402),
.Y(n1226) );
CLKMX2X2TS U9075 ( .A(FPADDSUB_OP_FLAG_SHT1), .B(FPADDSUB_OP_FLAG_EXP), .S0(
n8402), .Y(n1356) );
CLKMX2X2TS U9076 ( .A(n9570), .B(n9569), .S0(n9568), .Y(n1364) );
CLKMX2X2TS U9077 ( .A(FPADDSUB_SIGN_FLAG_SHT1), .B(n1364), .S0(n8402), .Y(
n1363) );
CLKMX2X2TS U9078 ( .A(FPADDSUB_DMP_SHT1_EWSW[6]), .B(n8403), .S0(n8412), .Y(
n1242) );
CLKMX2X2TS U9079 ( .A(FPADDSUB_DMP_SHT1_EWSW[7]), .B(n8404), .S0(n8412), .Y(
n1304) );
CLKMX2X2TS U9080 ( .A(FPADDSUB_DMP_SHT1_EWSW[8]), .B(n8405), .S0(n8412), .Y(
n1254) );
CLKMX2X2TS U9081 ( .A(FPADDSUB_DMP_SHT1_EWSW[5]), .B(n8406), .S0(n8412), .Y(
n1276) );
CLKMX2X2TS U9082 ( .A(FPADDSUB_DMP_SHT1_EWSW[9]), .B(n8407), .S0(n8412), .Y(
n1283) );
CLKMX2X2TS U9083 ( .A(FPADDSUB_DMP_SHT1_EWSW[1]), .B(n8408), .S0(n8412), .Y(
n1290) );
CLKMX2X2TS U9084 ( .A(FPADDSUB_DMP_SHT1_EWSW[0]), .B(n8409), .S0(n8412), .Y(
n1297) );
CLKMX2X2TS U9085 ( .A(FPADDSUB_DMP_SHT1_EWSW[3]), .B(n8410), .S0(n8412), .Y(
n1327) );
CLKMX2X2TS U9086 ( .A(FPADDSUB_DMP_SHT1_EWSW[4]), .B(n8411), .S0(n8412), .Y(
n1238) );
CLKMX2X2TS U9087 ( .A(FPADDSUB_DMP_SHT1_EWSW[2]), .B(n8413), .S0(n8412), .Y(
n1311) );
CLKMX2X2TS U9088 ( .A(FPADDSUB_DmP_mant_SHT1_SW[17]), .B(n8414), .S0(n8423),
.Y(n1390) );
CLKMX2X2TS U9089 ( .A(FPADDSUB_DmP_mant_SHT1_SW[10]), .B(n8415), .S0(n8423),
.Y(n1366) );
CLKMX2X2TS U9090 ( .A(FPADDSUB_DmP_mant_SHT1_SW[14]), .B(n8416), .S0(n8423),
.Y(n1369) );
CLKMX2X2TS U9091 ( .A(FPADDSUB_DmP_mant_SHT1_SW[16]), .B(n8417), .S0(n8423),
.Y(n1378) );
CLKMX2X2TS U9092 ( .A(FPADDSUB_DmP_mant_SHT1_SW[11]), .B(n8418), .S0(n8423),
.Y(n1372) );
CLKMX2X2TS U9093 ( .A(FPADDSUB_DmP_mant_SHT1_SW[7]), .B(n8419), .S0(n8423),
.Y(n1306) );
CLKMX2X2TS U9094 ( .A(FPADDSUB_DmP_mant_SHT1_SW[12]), .B(n8420), .S0(n8423),
.Y(n1272) );
CLKMX2X2TS U9095 ( .A(FPADDSUB_DmP_mant_SHT1_SW[4]), .B(n8421), .S0(n8423),
.Y(n1387) );
CLKMX2X2TS U9096 ( .A(FPADDSUB_DmP_mant_SHT1_SW[13]), .B(n8422), .S0(n8423),
.Y(n1381) );
CLKMX2X2TS U9097 ( .A(FPADDSUB_DMP_SHT1_EWSW[22]), .B(n8425), .S0(n8441),
.Y(n1210) );
CLKMX2X2TS U9098 ( .A(FPADDSUB_DMP_SHT1_EWSW[27]), .B(n8426), .S0(n8441),
.Y(n1439) );
CLKMX2X2TS U9099 ( .A(FPADDSUB_DMP_SHT1_EWSW[21]), .B(n8427), .S0(n8441),
.Y(n1222) );
CLKMX2X2TS U9100 ( .A(FPADDSUB_DMP_SHT1_EWSW[29]), .B(n8428), .S0(n8441),
.Y(n1429) );
CLKMX2X2TS U9101 ( .A(FPADDSUB_DMP_SHT1_EWSW[28]), .B(n8429), .S0(n8441),
.Y(n1434) );
CLKMX2X2TS U9102 ( .A(FPADDSUB_DMP_SHT1_EWSW[30]), .B(n8430), .S0(n8441),
.Y(n1424) );
CLKMX2X2TS U9103 ( .A(FPADDSUB_DmP_mant_SHT1_SW[6]), .B(n8432), .S0(n8438),
.Y(n1384) );
CLKMX2X2TS U9104 ( .A(FPADDSUB_DmP_mant_SHT1_SW[5]), .B(n8433), .S0(n8438),
.Y(n1278) );
CLKMX2X2TS U9105 ( .A(FPADDSUB_DmP_mant_SHT1_SW[22]), .B(n8434), .S0(n8438),
.Y(n1408) );
CLKMX2X2TS U9106 ( .A(FPADDSUB_DmP_mant_SHT1_SW[9]), .B(n8435), .S0(n8438),
.Y(n1285) );
CLKMX2X2TS U9107 ( .A(FPADDSUB_DmP_mant_SHT1_SW[21]), .B(n8436), .S0(n8438),
.Y(n1399) );
CLKMX2X2TS U9108 ( .A(FPADDSUB_DmP_mant_SHT1_SW[20]), .B(n8437), .S0(n8438),
.Y(n1393) );
CLKMX2X2TS U9109 ( .A(FPADDSUB_DmP_mant_SHT1_SW[8]), .B(n8439), .S0(n8438),
.Y(n1375) );
CLKMX2X2TS U9110 ( .A(FPADDSUB_DMP_SHT1_EWSW[26]), .B(n8440), .S0(n8441),
.Y(n1444) );
CLKMX2X2TS U9111 ( .A(FPADDSUB_DMP_SHT1_EWSW[24]), .B(n8442), .S0(n8441),
.Y(n1454) );
INVX2TS U9112 ( .A(Data_2[23]), .Y(n8443) );
MXI2X1TS U9113 ( .A(n8443), .B(n9478), .S0(n8445), .Y(n1650) );
INVX2TS U9114 ( .A(Data_2[31]), .Y(n8444) );
MXI2X1TS U9115 ( .A(n8444), .B(n9479), .S0(n8445), .Y(n1696) );
INVX2TS U9116 ( .A(Data_2[24]), .Y(n8446) );
MXI2X1TS U9117 ( .A(n8446), .B(n9209), .S0(n8445), .Y(n1651) );
INVX2TS U9118 ( .A(Data_1[28]), .Y(n8574) );
MXI2X1TS U9119 ( .A(n8574), .B(n9236), .S0(n8448), .Y(n1687) );
INVX2TS U9120 ( .A(Data_1[30]), .Y(n8575) );
MXI2X1TS U9121 ( .A(n8575), .B(n9695), .S0(n8448), .Y(n1689) );
INVX2TS U9122 ( .A(Data_1[29]), .Y(n8569) );
MXI2X1TS U9123 ( .A(n8569), .B(n9693), .S0(n8448), .Y(n1688) );
INVX2TS U9124 ( .A(Data_1[27]), .Y(n8572) );
MXI2X1TS U9125 ( .A(n8572), .B(n9223), .S0(n8448), .Y(n1686) );
INVX2TS U9126 ( .A(Data_2[29]), .Y(n8449) );
MXI2X1TS U9127 ( .A(n8449), .B(n9712), .S0(n8452), .Y(n1656) );
INVX2TS U9128 ( .A(Data_1[26]), .Y(n8576) );
MXI2X1TS U9129 ( .A(n8576), .B(n9224), .S0(n8452), .Y(n1685) );
INVX2TS U9130 ( .A(Data_1[23]), .Y(n8570) );
MXI2X1TS U9131 ( .A(n8570), .B(n9702), .S0(n8452), .Y(n1682) );
INVX2TS U9132 ( .A(Data_1[24]), .Y(n8573) );
MXI2X1TS U9133 ( .A(n8573), .B(n9703), .S0(n8452), .Y(n1683) );
INVX2TS U9134 ( .A(Data_1[25]), .Y(n8571) );
MXI2X1TS U9135 ( .A(n8571), .B(n9217), .S0(n8452), .Y(n1684) );
MXI2X1TS U9136 ( .A(n9837), .B(n9222), .S0(n8452), .Y(n1654) );
INVX2TS U9137 ( .A(Data_2[28]), .Y(n8450) );
MXI2X1TS U9138 ( .A(n8450), .B(n9221), .S0(n8452), .Y(n1655) );
INVX2TS U9139 ( .A(Data_2[26]), .Y(n8451) );
MXI2X1TS U9140 ( .A(n8451), .B(n9215), .S0(n8452), .Y(n1653) );
INVX2TS U9141 ( .A(Data_2[25]), .Y(n8453) );
MXI2X1TS U9142 ( .A(n8453), .B(n9216), .S0(n8452), .Y(n1652) );
MXI2X1TS U9143 ( .A(n9206), .B(n9469), .S0(n8456), .Y(n1448) );
CLKMX2X2TS U9144 ( .A(FPADDSUB_DMP_SHT2_EWSW[3]), .B(
FPADDSUB_DMP_SHT1_EWSW[3]), .S0(n8455), .Y(n1326) );
CLKMX2X2TS U9145 ( .A(FPADDSUB_DMP_SHT2_EWSW[0]), .B(
FPADDSUB_DMP_SHT1_EWSW[0]), .S0(n8455), .Y(n1296) );
CLKMX2X2TS U9146 ( .A(FPADDSUB_DMP_SHT2_EWSW[30]), .B(
FPADDSUB_DMP_SHT1_EWSW[30]), .S0(n8455), .Y(n1423) );
CLKMX2X2TS U9147 ( .A(FPADDSUB_DMP_SHT2_EWSW[5]), .B(
FPADDSUB_DMP_SHT1_EWSW[5]), .S0(n8455), .Y(n1275) );
CLKMX2X2TS U9148 ( .A(FPADDSUB_DMP_SHT2_EWSW[1]), .B(
FPADDSUB_DMP_SHT1_EWSW[1]), .S0(n8455), .Y(n1289) );
CLKMX2X2TS U9149 ( .A(FPADDSUB_DMP_SHT2_EWSW[7]), .B(
FPADDSUB_DMP_SHT1_EWSW[7]), .S0(n8455), .Y(n1303) );
CLKMX2X2TS U9150 ( .A(FPADDSUB_DMP_SHT2_EWSW[2]), .B(
FPADDSUB_DMP_SHT1_EWSW[2]), .S0(n8455), .Y(n1310) );
CLKMX2X2TS U9151 ( .A(FPADDSUB_DMP_SHT2_EWSW[6]), .B(
FPADDSUB_DMP_SHT1_EWSW[6]), .S0(n8455), .Y(n1241) );
CLKMX2X2TS U9152 ( .A(FPADDSUB_DMP_SHT2_EWSW[4]), .B(
FPADDSUB_DMP_SHT1_EWSW[4]), .S0(n8455), .Y(n1237) );
CLKMX2X2TS U9153 ( .A(FPADDSUB_DMP_SHT2_EWSW[8]), .B(
FPADDSUB_DMP_SHT1_EWSW[8]), .S0(n8455), .Y(n1253) );
CLKMX2X2TS U9154 ( .A(FPADDSUB_DMP_SHT2_EWSW[21]), .B(
FPADDSUB_DMP_SHT1_EWSW[21]), .S0(n8456), .Y(n1221) );
CLKMX2X2TS U9155 ( .A(FPADDSUB_DMP_SHT2_EWSW[26]), .B(
FPADDSUB_DMP_SHT1_EWSW[26]), .S0(n8456), .Y(n1443) );
CLKMX2X2TS U9156 ( .A(FPADDSUB_DMP_SHT2_EWSW[23]), .B(
FPADDSUB_DMP_SHT1_EWSW[23]), .S0(n8456), .Y(n1458) );
CLKMX2X2TS U9157 ( .A(FPADDSUB_DMP_SHT2_EWSW[22]), .B(
FPADDSUB_DMP_SHT1_EWSW[22]), .S0(n8456), .Y(n1209) );
CLKMX2X2TS U9158 ( .A(FPADDSUB_DMP_SHT2_EWSW[27]), .B(
FPADDSUB_DMP_SHT1_EWSW[27]), .S0(n8456), .Y(n1438) );
CLKMX2X2TS U9159 ( .A(FPADDSUB_DMP_SHT2_EWSW[24]), .B(
FPADDSUB_DMP_SHT1_EWSW[24]), .S0(n8456), .Y(n1453) );
CLKMX2X2TS U9160 ( .A(FPADDSUB_DMP_SHT2_EWSW[28]), .B(
FPADDSUB_DMP_SHT1_EWSW[28]), .S0(n8456), .Y(n1433) );
CLKMX2X2TS U9161 ( .A(FPADDSUB_DMP_SHT2_EWSW[29]), .B(
FPADDSUB_DMP_SHT1_EWSW[29]), .S0(n8456), .Y(n1428) );
MXI2X1TS U9162 ( .A(n9470), .B(n8458), .S0(FPADDSUB_Shift_reg_FLAGS_7_6),
.Y(n1357) );
BUFX8TS U9163 ( .A(n8459), .Y(n8465) );
AOI2BB2X1TS U9164 ( .B0(n8465), .B1(n9211), .A0N(n8461), .A1N(
mult_result[23]), .Y(n1492) );
AOI2BB2X1TS U9165 ( .B0(n8465), .B1(n9210), .A0N(n8461), .A1N(
mult_result[24]), .Y(n1491) );
AOI2BB2X1TS U9166 ( .B0(n8465), .B1(n3684), .A0N(n8461), .A1N(
mult_result[26]), .Y(n1489) );
AOI2BB2X1TS U9167 ( .B0(n8465), .B1(n3688), .A0N(n8461), .A1N(
mult_result[30]), .Y(n1485) );
AOI2BB2X1TS U9168 ( .B0(n8465), .B1(n3683), .A0N(n8461), .A1N(
mult_result[25]), .Y(n1490) );
AOI2BB2X1TS U9169 ( .B0(n8465), .B1(n3686), .A0N(n8461), .A1N(
mult_result[28]), .Y(n1487) );
AOI2BB2X1TS U9170 ( .B0(n8465), .B1(n3687), .A0N(n8461), .A1N(
mult_result[29]), .Y(n1486) );
AOI2BB2X1TS U9171 ( .B0(n8465), .B1(n3685), .A0N(n8461), .A1N(
mult_result[27]), .Y(n1488) );
ADDHX1TS U9172 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n8463), .CO(n8500),
.S(n8464) );
AO22X1TS U9173 ( .A0(n8465), .A1(FPMULT_Sgf_normalized_result[22]), .B0(
mult_result[22]), .B1(n8468), .Y(n1493) );
AO22X1TS U9174 ( .A0(n8465), .A1(n2898), .B0(mult_result[21]), .B1(n8468),
.Y(n1494) );
AO22X1TS U9175 ( .A0(n8467), .A1(FPMULT_Sgf_normalized_result[5]), .B0(
mult_result[5]), .B1(n8466), .Y(n1510) );
AO22X1TS U9176 ( .A0(n8469), .A1(FPMULT_Sgf_normalized_result[19]), .B0(
mult_result[19]), .B1(n8468), .Y(n1496) );
NOR4X1TS U9177 ( .A(FPMULT_Op_MY[25]), .B(FPMULT_Op_MY[26]), .C(
FPMULT_Op_MY[27]), .D(FPMULT_Op_MY[28]), .Y(n8473) );
NOR3X1TS U9178 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[23]), .C(
FPMULT_Op_MY[24]), .Y(n8470) );
NAND4X1TS U9179 ( .A(n8473), .B(n8472), .C(n8471), .D(n8470), .Y(n8490) );
NOR4X1TS U9180 ( .A(FPMULT_Op_MY[8]), .B(n9749), .C(FPMULT_Op_MY[9]), .D(
FPMULT_Op_MY[7]), .Y(n8475) );
NAND4X1TS U9181 ( .A(n8478), .B(n8477), .C(n8476), .D(n8475), .Y(n8489) );
AND4X1TS U9182 ( .A(n9714), .B(n9455), .C(n9715), .D(n9716), .Y(n8482) );
NAND4X1TS U9183 ( .A(n8482), .B(n8481), .C(n8480), .D(n8479), .Y(n8488) );
NOR4X1TS U9184 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[27]), .D(FPMULT_Op_MX[28]), .Y(n8485) );
NAND4X1TS U9185 ( .A(n8486), .B(n8485), .C(n8484), .D(n8483), .Y(n8487) );
OAI22X1TS U9186 ( .A0(n8490), .A1(n8489), .B0(n8488), .B1(n8487), .Y(n8491)
);
NAND2X1TS U9187 ( .A(n8554), .B(n8492), .Y(n9888) );
NAND2X1TS U9188 ( .A(n8554), .B(n8493), .Y(n9953) );
NOR2X1TS U9189 ( .A(n8494), .B(n3630), .Y(n8496) );
AOI2BB1X1TS U9190 ( .A0N(FPSENCOS_cont_iter_out[1]), .A1N(n8496), .B0(n8495),
.Y(n2142) );
NAND2X1TS U9191 ( .A(n8498), .B(n8497), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
MXI2X1TS U9192 ( .A(n9132), .B(n9336), .S0(n8607), .Y(n1988) );
MXI2X1TS U9193 ( .A(n9131), .B(n9335), .S0(n8607), .Y(n1890) );
MXI2X1TS U9194 ( .A(n9129), .B(n9333), .S0(n8783), .Y(n1864) );
MXI2X1TS U9195 ( .A(n9130), .B(n9334), .S0(n8783), .Y(n1962) );
MXI2X1TS U9196 ( .A(n9137), .B(n9343), .S0(n8499), .Y(n1984) );
MXI2X1TS U9197 ( .A(n9139), .B(n9345), .S0(n8499), .Y(n1998) );
MXI2X1TS U9198 ( .A(n9138), .B(n9344), .S0(n8499), .Y(n1900) );
MXI2X1TS U9199 ( .A(n9136), .B(n9342), .S0(n8499), .Y(n1886) );
MXI2X1TS U9200 ( .A(n9135), .B(n9340), .S0(n8499), .Y(n1876) );
MXI2X1TS U9201 ( .A(n9134), .B(n9338), .S0(n8499), .Y(n1884) );
MXI2X1TS U9202 ( .A(n9133), .B(n9337), .S0(n8499), .Y(n1976) );
MXI2X1TS U9203 ( .A(n9120), .B(n9341), .S0(n8499), .Y(n1974) );
MXI2X1TS U9204 ( .A(n9128), .B(n9339), .S0(n8499), .Y(n1982) );
ADDHX1TS U9205 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n8500), .CO(n8566),
.S(n8501) );
MXI2X1TS U9206 ( .A(n9424), .B(n9157), .S0(n8504), .Y(n1872) );
MXI2X1TS U9207 ( .A(n8502), .B(n9152), .S0(n8503), .Y(n1874) );
MXI2X1TS U9208 ( .A(n9122), .B(n9401), .S0(n8503), .Y(n1980) );
MXI2X1TS U9209 ( .A(n9418), .B(n9150), .S0(n8505), .Y(n1894) );
MXI2X1TS U9210 ( .A(n9421), .B(n9154), .S0(n8503), .Y(n1880) );
MXI2X1TS U9211 ( .A(n9118), .B(n9405), .S0(n8504), .Y(n1968) );
MXI2X1TS U9212 ( .A(n9415), .B(n9147), .S0(n8505), .Y(n1896) );
MXI2X1TS U9213 ( .A(n9115), .B(n9400), .S0(n8503), .Y(n1972) );
MXI2X1TS U9214 ( .A(n9428), .B(n9161), .S0(n8504), .Y(n1908) );
MXI2X1TS U9215 ( .A(FPSENCOS_cont_iter_out[2]), .B(n9398), .S0(n8505), .Y(
n2127) );
MXI2X1TS U9216 ( .A(n9430), .B(n9163), .S0(n8504), .Y(n1906) );
MXI2X1TS U9217 ( .A(n9426), .B(n9159), .S0(n8504), .Y(n1870) );
MXI2X1TS U9218 ( .A(n9123), .B(n9403), .S0(n8503), .Y(n1986) );
MXI2X1TS U9219 ( .A(n9429), .B(n9162), .S0(n8504), .Y(n2006) );
MXI2X1TS U9220 ( .A(n9416), .B(n9148), .S0(n8505), .Y(n1892) );
MXI2X1TS U9221 ( .A(n9436), .B(n9169), .S0(n8505), .Y(n1964) );
MXI2X1TS U9222 ( .A(n9417), .B(n9149), .S0(n8505), .Y(n1990) );
MXI2X1TS U9223 ( .A(n9116), .B(n9402), .S0(n8503), .Y(n1978) );
MXI2X1TS U9224 ( .A(n9425), .B(n9158), .S0(n8504), .Y(n1970) );
MXI2X1TS U9225 ( .A(n9422), .B(n9155), .S0(n8503), .Y(n1888) );
MXI2X1TS U9226 ( .A(n9113), .B(n9397), .S0(n8505), .Y(n1994) );
MXI2X1TS U9227 ( .A(n9119), .B(n9407), .S0(n8504), .Y(n2004) );
MXI2X1TS U9228 ( .A(n9117), .B(n9404), .S0(n8503), .Y(n2000) );
MXI2X1TS U9229 ( .A(n9419), .B(n9151), .S0(n8505), .Y(n1878) );
MXI2X1TS U9230 ( .A(n9124), .B(n9406), .S0(n8504), .Y(n2002) );
MXI2X1TS U9231 ( .A(n9420), .B(n9153), .S0(n8503), .Y(n1882) );
MXI2X1TS U9232 ( .A(n9423), .B(n9156), .S0(n8503), .Y(n1902) );
MXI2X1TS U9233 ( .A(n9427), .B(n9160), .S0(n8504), .Y(n1904) );
MXI2X1TS U9234 ( .A(n9114), .B(n9399), .S0(n8505), .Y(n1992) );
MXI2X1TS U9235 ( .A(n9170), .B(n9453), .S0(n8506), .Y(n1734) );
MXI2X1TS U9236 ( .A(n9125), .B(n9408), .S0(n8506), .Y(n1996) );
MXI2X1TS U9237 ( .A(n9431), .B(n9164), .S0(n8506), .Y(n1898) );
MXI2X1TS U9238 ( .A(n9432), .B(n9165), .S0(n8506), .Y(n1846) );
MXI2X1TS U9239 ( .A(n9126), .B(n9409), .S0(n8506), .Y(n1966) );
MXI2X1TS U9240 ( .A(n9434), .B(n9167), .S0(n8506), .Y(n1868) );
MXI2X1TS U9241 ( .A(n9435), .B(n9168), .S0(n8506), .Y(n1866) );
MXI2X1TS U9242 ( .A(n9433), .B(n9166), .S0(n8506), .Y(n1944) );
BUFX4TS U9243 ( .A(n8507), .Y(n8586) );
CLKMX2X2TS U9244 ( .A(intadd_734_SUM_0_), .B(FPSENCOS_d_ff3_sh_x_out[24]),
.S0(n8586), .Y(n1952) );
CLKMX2X2TS U9245 ( .A(intadd_734_SUM_1_), .B(FPSENCOS_d_ff3_sh_x_out[25]),
.S0(n8586), .Y(n1951) );
NAND2X1TS U9246 ( .A(n8775), .B(n8508), .Y(n9960) );
CLKMX2X2TS U9247 ( .A(intadd_733_SUM_1_), .B(FPSENCOS_d_ff3_sh_y_out[25]),
.S0(n8675), .Y(n1853) );
CLKMX2X2TS U9248 ( .A(intadd_733_SUM_0_), .B(FPSENCOS_d_ff3_sh_y_out[24]),
.S0(n8675), .Y(n1854) );
CLKMX2X2TS U9249 ( .A(intadd_734_SUM_2_), .B(FPSENCOS_d_ff3_sh_x_out[26]),
.S0(n8675), .Y(n1950) );
CLKMX2X2TS U9250 ( .A(intadd_733_SUM_2_), .B(FPSENCOS_d_ff3_sh_y_out[26]),
.S0(n8675), .Y(n1852) );
INVX8TS U9251 ( .A(n8568), .Y(n8530) );
MXI2X1TS U9252 ( .A(n3589), .B(n8510), .S0(n8530), .Y(n2099) );
INVX8TS U9253 ( .A(n8568), .Y(n8528) );
MXI2X1TS U9254 ( .A(n3577), .B(n8511), .S0(n8528), .Y(n2109) );
MXI2X1TS U9255 ( .A(n3572), .B(n8512), .S0(n8530), .Y(n2111) );
MXI2X1TS U9256 ( .A(n3585), .B(n8513), .S0(n8530), .Y(n2108) );
MXI2X1TS U9257 ( .A(n3570), .B(n8514), .S0(n8528), .Y(n2112) );
MXI2X1TS U9258 ( .A(n3593), .B(n8515), .S0(n8530), .Y(n2107) );
MXI2X1TS U9259 ( .A(n3587), .B(n8516), .S0(n8530), .Y(n2110) );
MXI2X1TS U9260 ( .A(n3622), .B(n8517), .S0(n8528), .Y(n2101) );
MXI2X1TS U9261 ( .A(n3608), .B(n8518), .S0(n8530), .Y(n2105) );
MXI2X1TS U9262 ( .A(n3576), .B(n8519), .S0(n8528), .Y(n2095) );
MXI2X1TS U9263 ( .A(n3578), .B(n8520), .S0(n8530), .Y(n2098) );
MXI2X1TS U9264 ( .A(n3614), .B(n8521), .S0(n8530), .Y(n2103) );
MXI2X1TS U9265 ( .A(n3586), .B(n8522), .S0(n8528), .Y(n2096) );
MXI2X1TS U9266 ( .A(n3594), .B(n8523), .S0(n8528), .Y(n2094) );
MXI2X1TS U9267 ( .A(n3581), .B(n8524), .S0(n8528), .Y(n2097) );
MXI2X1TS U9268 ( .A(n3573), .B(n8525), .S0(n8528), .Y(n2104) );
MXI2X1TS U9269 ( .A(n3597), .B(n8526), .S0(n8528), .Y(n2093) );
MXI2X1TS U9270 ( .A(n3619), .B(n8527), .S0(n8530), .Y(n2102) );
MXI2X1TS U9271 ( .A(n3588), .B(n8529), .S0(n8528), .Y(n2100) );
MXI2X1TS U9272 ( .A(n3600), .B(n8531), .S0(n8530), .Y(n2106) );
CLKMX2X2TS U9273 ( .A(FPADDSUB_DMP_SHT1_EWSW[16]), .B(n8532), .S0(n2695),
.Y(n1250) );
CLKMX2X2TS U9274 ( .A(FPADDSUB_DMP_SHT1_EWSW[13]), .B(n8533), .S0(n2695),
.Y(n1246) );
CLKMX2X2TS U9275 ( .A(FPADDSUB_DMP_SHT1_EWSW[12]), .B(n8534), .S0(n2695),
.Y(n1270) );
CLKMX2X2TS U9276 ( .A(FPADDSUB_DMP_SHT1_EWSW[18]), .B(n8535), .S0(n2695),
.Y(n1218) );
CLKMX2X2TS U9277 ( .A(FPADDSUB_DMP_SHT1_EWSW[17]), .B(n8536), .S0(n2695),
.Y(n1234) );
CLKMX2X2TS U9278 ( .A(FPADDSUB_DMP_SHT1_EWSW[14]), .B(n8537), .S0(n2695),
.Y(n1262) );
CLKMX2X2TS U9279 ( .A(FPADDSUB_DMP_SHT1_EWSW[11]), .B(n8538), .S0(n2695),
.Y(n1258) );
CLKMX2X2TS U9280 ( .A(FPADDSUB_DMP_SHT1_EWSW[15]), .B(n8539), .S0(n2695),
.Y(n1214) );
CLKMX2X2TS U9281 ( .A(FPADDSUB_DMP_SHT1_EWSW[10]), .B(n8540), .S0(n2695),
.Y(n1266) );
MXI2X1TS U9282 ( .A(n3584), .B(n8541), .S0(n8545), .Y(n2113) );
MXI2X1TS U9283 ( .A(n3569), .B(n8542), .S0(n8545), .Y(n2114) );
INVX2TS U9284 ( .A(region_flag[1]), .Y(n8543) );
MXI2X1TS U9285 ( .A(n9387), .B(n8543), .S0(n8545), .Y(n2136) );
INVX2TS U9286 ( .A(region_flag[0]), .Y(n8544) );
MXI2X1TS U9287 ( .A(n9481), .B(n8544), .S0(n8545), .Y(n2137) );
NAND2X1TS U9288 ( .A(operation[1]), .B(operation[0]), .Y(n8546) );
MXI2X1TS U9289 ( .A(n9103), .B(n8546), .S0(n8545), .Y(n2082) );
MXI2X1TS U9290 ( .A(n8548), .B(n8547), .S0(n8775), .Y(n9846) );
MXI2X1TS U9291 ( .A(n8550), .B(n8549), .S0(n8775), .Y(n9847) );
MXI2X1TS U9292 ( .A(n8552), .B(n8551), .S0(n8775), .Y(n9848) );
CLKMX2X2TS U9293 ( .A(FPADDSUB_DMP_SHT1_EWSW[23]), .B(n8553), .S0(n2695),
.Y(n1459) );
NAND2X1TS U9294 ( .A(n8582), .B(n8555), .Y(n9875) );
NAND2X1TS U9295 ( .A(n8582), .B(n8556), .Y(n9884) );
NAND2X1TS U9296 ( .A(n8582), .B(n8557), .Y(n9871) );
NAND2X1TS U9297 ( .A(n8582), .B(n8558), .Y(n9879) );
NAND2X1TS U9298 ( .A(n8582), .B(n8559), .Y(n9886) );
NAND2X1TS U9299 ( .A(n8582), .B(n8560), .Y(n9877) );
NAND2X1TS U9300 ( .A(n8582), .B(n8561), .Y(n9867) );
NAND2X1TS U9301 ( .A(n9514), .B(n8562), .Y(n9897) );
NAND2X1TS U9302 ( .A(n9514), .B(n8563), .Y(n9900) );
NAND2X1TS U9303 ( .A(n9514), .B(n8564), .Y(n9903) );
NAND2X1TS U9304 ( .A(n9514), .B(n8565), .Y(n9891) );
ADDHX1TS U9305 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n8566), .CO(n8602),
.S(n8567) );
MXI2X1TS U9306 ( .A(n3617), .B(n8569), .S0(n2333), .Y(n2085) );
MXI2X1TS U9307 ( .A(n3606), .B(n8570), .S0(n2333), .Y(n2091) );
MXI2X1TS U9308 ( .A(n3610), .B(n8571), .S0(n2333), .Y(n2089) );
MXI2X1TS U9309 ( .A(n3611), .B(n8572), .S0(n2333), .Y(n2087) );
MXI2X1TS U9310 ( .A(n3609), .B(n8573), .S0(n2333), .Y(n2090) );
MXI2X1TS U9311 ( .A(n3615), .B(n8574), .S0(n2333), .Y(n2086) );
MXI2X1TS U9312 ( .A(n3620), .B(n8575), .S0(n2333), .Y(n2084) );
MXI2X1TS U9313 ( .A(n3574), .B(n8576), .S0(n2333), .Y(n2088) );
MXI2X1TS U9314 ( .A(n3601), .B(n8577), .S0(n2333), .Y(n2092) );
MXI2X1TS U9315 ( .A(n3621), .B(n8578), .S0(n2333), .Y(n2083) );
NAND2X1TS U9316 ( .A(n8582), .B(n8579), .Y(n9869) );
NAND2X1TS U9317 ( .A(n8582), .B(n8580), .Y(n9882) );
NAND2X1TS U9318 ( .A(n8582), .B(n8581), .Y(n9873) );
AOI2BB2X1TS U9319 ( .B0(n6635), .B1(n9278), .A0N(FPSENCOS_d_ff2_X[25]),
.A1N(n2833), .Y(n1959) );
NOR2X1TS U9320 ( .A(n8783), .B(n3630), .Y(n8782) );
MXI2X1TS U9321 ( .A(n8584), .B(n8782), .S0(n8583), .Y(n8585) );
OAI2BB1X1TS U9322 ( .A0N(FPSENCOS_d_ff3_LUT_out[23]), .A1N(n8586), .B0(n8585), .Y(n2119) );
CLKMX2X2TS U9323 ( .A(n8587), .B(n2891), .S0(n9752), .Y(n1556) );
CLKMX2X2TS U9324 ( .A(n8589), .B(n2894), .S0(n9752), .Y(n1555) );
AOI22X1TS U9325 ( .A0(n8590), .A1(n9290), .B0(n9113), .B1(n8593), .Y(n1995)
);
AOI22X1TS U9326 ( .A0(n8590), .A1(n9295), .B0(n9115), .B1(n8592), .Y(n1973)
);
AOI22X1TS U9327 ( .A0(n8590), .A1(n9296), .B0(n9116), .B1(n8593), .Y(n1979)
);
AOI22X1TS U9328 ( .A0(n8590), .A1(n9297), .B0(n9118), .B1(n8592), .Y(n1969)
);
AOI22X1TS U9329 ( .A0(n8590), .A1(n9294), .B0(n9128), .B1(n8592), .Y(n1983)
);
AOI22X1TS U9330 ( .A0(n8590), .A1(n9291), .B0(n9114), .B1(n8592), .Y(n1993)
);
AOI22X1TS U9331 ( .A0(n8590), .A1(n9293), .B0(n9119), .B1(n8593), .Y(n2005)
);
AOI22X1TS U9332 ( .A0(n8590), .A1(n9292), .B0(n9117), .B1(n8592), .Y(n2001)
);
AOI22X1TS U9333 ( .A0(n8590), .A1(n9277), .B0(n9102), .B1(n8593), .Y(n1956)
);
AOI2BB2X1TS U9334 ( .B0(n8598), .B1(n9284), .A0N(FPSENCOS_d_ff2_X[26]),
.A1N(n2833), .Y(n1958) );
AOI22X1TS U9335 ( .A0(n8598), .A1(n9288), .B0(n9123), .B1(n8592), .Y(n1987)
);
AOI22X1TS U9336 ( .A0(n8598), .A1(n9281), .B0(n9120), .B1(n8593), .Y(n1975)
);
AOI22X1TS U9337 ( .A0(n8598), .A1(n9282), .B0(n9122), .B1(n8592), .Y(n1981)
);
AOI22X1TS U9338 ( .A0(n8598), .A1(n9280), .B0(n9126), .B1(n8593), .Y(n1967)
);
AOI22X1TS U9339 ( .A0(n8598), .A1(n9279), .B0(n9125), .B1(n8593), .Y(n1997)
);
AOI2BB2X1TS U9340 ( .B0(n8598), .B1(n9287), .A0N(FPSENCOS_d_ff2_X[29]),
.A1N(n2833), .Y(n1955) );
AOI22X1TS U9341 ( .A0(n8598), .A1(n9283), .B0(n9124), .B1(n8593), .Y(n2003)
);
AOI2BB2X1TS U9342 ( .B0(n8598), .B1(n9286), .A0N(FPSENCOS_d_ff2_X[27]),
.A1N(n2833), .Y(n1957) );
NAND2X1TS U9343 ( .A(n8789), .B(n3639), .Y(n8597) );
MXI2X1TS U9344 ( .A(n8594), .B(FPSENCOS_d_ff3_LUT_out[25]), .S0(n8607), .Y(
n8596) );
NAND3X1TS U9345 ( .A(n8784), .B(FPSENCOS_cont_iter_out[0]), .C(n8788), .Y(
n8595) );
NAND3X1TS U9346 ( .A(n8597), .B(n8596), .C(n8595), .Y(n2117) );
AOI2BB2X1TS U9347 ( .B0(n8598), .B1(n9285), .A0N(FPSENCOS_d_ff2_X[24]),
.A1N(n2833), .Y(n1960) );
CLKMX2X2TS U9348 ( .A(FPADDSUB_DMP_SHT2_EWSW[12]), .B(
FPADDSUB_DMP_SHT1_EWSW[12]), .S0(busy), .Y(n1269) );
CLKMX2X2TS U9349 ( .A(FPADDSUB_DMP_SHT2_EWSW[9]), .B(
FPADDSUB_DMP_SHT1_EWSW[9]), .S0(busy), .Y(n1282) );
CLKMX2X2TS U9350 ( .A(FPADDSUB_DMP_SHT2_EWSW[17]), .B(
FPADDSUB_DMP_SHT1_EWSW[17]), .S0(busy), .Y(n1233) );
CLKMX2X2TS U9351 ( .A(FPADDSUB_DMP_SHT2_EWSW[11]), .B(
FPADDSUB_DMP_SHT1_EWSW[11]), .S0(busy), .Y(n1257) );
CLKMX2X2TS U9352 ( .A(FPADDSUB_DMP_SHT2_EWSW[14]), .B(
FPADDSUB_DMP_SHT1_EWSW[14]), .S0(busy), .Y(n1261) );
CLKMX2X2TS U9353 ( .A(FPADDSUB_DMP_SHT2_EWSW[13]), .B(
FPADDSUB_DMP_SHT1_EWSW[13]), .S0(busy), .Y(n1245) );
CLKMX2X2TS U9354 ( .A(FPADDSUB_DMP_SHT2_EWSW[18]), .B(
FPADDSUB_DMP_SHT1_EWSW[18]), .S0(busy), .Y(n1217) );
CLKMX2X2TS U9355 ( .A(FPADDSUB_DMP_SHT2_EWSW[10]), .B(
FPADDSUB_DMP_SHT1_EWSW[10]), .S0(busy), .Y(n1265) );
CLKMX2X2TS U9356 ( .A(FPADDSUB_DMP_SHT2_EWSW[16]), .B(
FPADDSUB_DMP_SHT1_EWSW[16]), .S0(busy), .Y(n1249) );
CLKMX2X2TS U9357 ( .A(FPADDSUB_DMP_SHT2_EWSW[15]), .B(
FPADDSUB_DMP_SHT1_EWSW[15]), .S0(busy), .Y(n1213) );
AOI21X1TS U9358 ( .A0(intadd_734_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n8671),
.Y(n8606) );
MXI2X1TS U9359 ( .A(n8606), .B(n3645), .S0(n8607), .Y(n1949) );
AOI21X1TS U9360 ( .A0(intadd_733_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n8674),
.Y(n8608) );
MXI2X1TS U9361 ( .A(n8608), .B(n3643), .S0(n8607), .Y(n1851) );
NAND2X1TS U9362 ( .A(n8790), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n8610) );
NAND3X1TS U9363 ( .A(n8612), .B(n8611), .C(n8610), .Y(n2130) );
NAND4X1TS U9364 ( .A(dataA[27]), .B(dataA[23]), .C(dataA[24]), .D(dataA[25]),
.Y(n8613) );
NOR2X1TS U9365 ( .A(n8614), .B(n8613), .Y(n8615) );
NAND2X1TS U9366 ( .A(n9961), .B(n8615), .Y(n8631) );
MXI2X1TS U9367 ( .A(n8631), .B(n8619), .S0(n8624), .Y(n8623) );
NAND4X1TS U9368 ( .A(dataB[29]), .B(n2896), .C(dataB[26]), .D(dataB[23]),
.Y(n8621) );
AOI21X1TS U9369 ( .A0(n8623), .A1(n8622), .B0(n9298), .Y(n8633) );
NAND4X1TS U9370 ( .A(n9965), .B(n9964), .C(n9963), .D(n9962), .Y(n8629) );
OAI21X1TS U9371 ( .A0(n8631), .A1(n8627), .B0(n9298), .Y(n8628) );
NAND4BX1TS U9372 ( .AN(n8629), .B(n8628), .C(n9967), .D(n9966), .Y(n8632) );
OAI22X1TS U9373 ( .A0(n8633), .A1(n8632), .B0(n8631), .B1(n8630), .Y(NaN_reg) );
MXI2X1TS U9374 ( .A(n8635), .B(n8634), .S0(n8775), .Y(n9845) );
CLKMX2X2TS U9375 ( .A(n8636), .B(n2932), .S0(n9752), .Y(n1557) );
AOI22X1TS U9376 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[16]), .B0(n8643), .B1(
cordic_result[16]), .Y(n8637) );
OAI2BB1X1TS U9377 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[16]), .B0(n8637), .Y(
n1712) );
AOI22X1TS U9378 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[10]), .B0(n8643), .B1(
cordic_result[10]), .Y(n8638) );
OAI2BB1X1TS U9379 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[10]), .B0(n8638), .Y(
n1718) );
AOI22X1TS U9380 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[17]), .B0(n8643), .B1(
cordic_result[17]), .Y(n8639) );
OAI2BB1X1TS U9381 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[17]), .B0(n8639), .Y(
n1711) );
AOI22X1TS U9382 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[14]), .B0(n8643), .B1(
cordic_result[14]), .Y(n8640) );
OAI2BB1X1TS U9383 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[14]), .B0(n8640), .Y(
n1714) );
AOI22X1TS U9384 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[11]), .B0(n8643), .B1(
cordic_result[11]), .Y(n8641) );
OAI2BB1X1TS U9385 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[11]), .B0(n8641), .Y(
n1717) );
AOI22X1TS U9386 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[18]), .B0(n8643), .B1(
cordic_result[18]), .Y(n8642) );
OAI2BB1X1TS U9387 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[18]), .B0(n8642), .Y(
n1710) );
AOI22X1TS U9388 ( .A0(n8644), .A1(FPSENCOS_d_ff_Xn[15]), .B0(n8643), .B1(
cordic_result[15]), .Y(n8645) );
OAI2BB1X1TS U9389 ( .A0N(n8646), .A1N(FPSENCOS_d_ff_Yn[15]), .B0(n8645), .Y(
n1713) );
AOI22X1TS U9390 ( .A0(n8654), .A1(FPSENCOS_d_ff_Xn[9]), .B0(n8653), .B1(
n2921), .Y(n8647) );
OAI2BB1X1TS U9391 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[9]), .B0(n8647), .Y(
n1719) );
AOI22X1TS U9392 ( .A0(n8654), .A1(FPSENCOS_d_ff_Xn[4]), .B0(n8653), .B1(
cordic_result[4]), .Y(n8648) );
OAI2BB1X1TS U9393 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[4]), .B0(n8648), .Y(
n1724) );
AOI22X1TS U9394 ( .A0(n8654), .A1(FPSENCOS_d_ff_Xn[5]), .B0(n8653), .B1(
cordic_result[5]), .Y(n8649) );
OAI2BB1X1TS U9395 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[5]), .B0(n8649), .Y(
n1723) );
AOI22X1TS U9396 ( .A0(n8654), .A1(FPSENCOS_d_ff_Xn[7]), .B0(n8653), .B1(
cordic_result[7]), .Y(n8650) );
OAI2BB1X1TS U9397 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[7]), .B0(n8650), .Y(
n1721) );
AOI22X1TS U9398 ( .A0(n8654), .A1(FPSENCOS_d_ff_Xn[1]), .B0(n8653), .B1(
cordic_result[1]), .Y(n8651) );
OAI2BB1X1TS U9399 ( .A0N(n8679), .A1N(FPSENCOS_d_ff_Yn[1]), .B0(n8651), .Y(
n1727) );
AOI22X1TS U9400 ( .A0(n8654), .A1(FPSENCOS_d_ff_Xn[8]), .B0(n8653), .B1(
cordic_result[8]), .Y(n8652) );
OAI2BB1X1TS U9401 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[8]), .B0(n8652), .Y(
n1720) );
AOI22X1TS U9402 ( .A0(n8654), .A1(FPSENCOS_d_ff_Xn[6]), .B0(n8653), .B1(
cordic_result[6]), .Y(n8655) );
OAI2BB1X1TS U9403 ( .A0N(n8656), .A1N(FPSENCOS_d_ff_Yn[6]), .B0(n8655), .Y(
n1722) );
AOI2BB2X1TS U9404 ( .B0(FPSENCOS_d_ff2_Z[31]), .B1(n8660), .A0N(n8657),
.A1N(n3621), .Y(n8658) );
OAI2BB1X1TS U9405 ( .A0N(n8662), .A1N(FPSENCOS_d_ff_Zn[31]), .B0(n8658), .Y(
n1735) );
AOI2BB2X1TS U9406 ( .B0(FPSENCOS_d_ff2_Z[20]), .B1(n8667), .A0N(n8664),
.A1N(n3594), .Y(n8659) );
OAI2BB1X1TS U9407 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[20]), .B0(n8659), .Y(
n1746) );
AOI2BB2X1TS U9408 ( .B0(FPSENCOS_d_ff2_Z[30]), .B1(n8660), .A0N(n8664),
.A1N(n3620), .Y(n8661) );
OAI2BB1X1TS U9409 ( .A0N(n8662), .A1N(FPSENCOS_d_ff_Zn[30]), .B0(n8661), .Y(
n1736) );
AOI2BB2X1TS U9410 ( .B0(FPSENCOS_d_ff2_Z[23]), .B1(n8667), .A0N(n8664),
.A1N(n3606), .Y(n8663) );
OAI2BB1X1TS U9411 ( .A0N(n8666), .A1N(FPSENCOS_d_ff_Zn[23]), .B0(n8663), .Y(
n1743) );
AOI2BB2X1TS U9412 ( .B0(FPSENCOS_d_ff2_Z[5]), .B1(n8667), .A0N(n8664), .A1N(
n3577), .Y(n8665) );
AOI2BB2X1TS U9413 ( .B0(FPSENCOS_d_ff2_Z[22]), .B1(n8667), .A0N(n8657),
.A1N(n3601), .Y(n8668) );
OAI21X1TS U9414 ( .A0(n8671), .A1(n9102), .B0(n8670), .Y(n8672) );
OAI21X1TS U9415 ( .A0(n8674), .A1(n9247), .B0(n8673), .Y(n8676) );
MXI2X1TS U9416 ( .A(n9140), .B(n9477), .S0(n8680), .Y(n1361) );
AOI22X1TS U9417 ( .A0(n8677), .A1(FPSENCOS_d_ff_Xn[30]), .B0(n8326), .B1(
cordic_result[30]), .Y(n8678) );
OAI2BB1X1TS U9418 ( .A0N(n8679), .A1N(FPSENCOS_d_ff_Yn[30]), .B0(n8678), .Y(
n1698) );
MXI2X1TS U9419 ( .A(n9367), .B(n9121), .S0(n8680), .Y(n1354) );
MXI2X1TS U9420 ( .A(n9193), .B(n9501), .S0(n8682), .Y(n1422) );
MXI2X1TS U9421 ( .A(n9192), .B(n9495), .S0(n8683), .Y(n1220) );
MXI2X1TS U9422 ( .A(n9173), .B(n9509), .S0(n8683), .Y(n1208) );
MXI2X1TS U9423 ( .A(n9196), .B(n9504), .S0(n8683), .Y(n1437) );
MXI2X1TS U9424 ( .A(n9199), .B(n9508), .S0(n8683), .Y(n1457) );
MXI2X1TS U9425 ( .A(n9194), .B(n9502), .S0(n8683), .Y(n1427) );
MXI2X1TS U9426 ( .A(n9198), .B(n9507), .S0(n8683), .Y(n1452) );
MXI2X1TS U9427 ( .A(n9197), .B(n9505), .S0(n8683), .Y(n1442) );
MXI2X1TS U9428 ( .A(n9195), .B(n9503), .S0(n8683), .Y(n1432) );
MXI2X1TS U9429 ( .A(n9206), .B(n9506), .S0(n8683), .Y(n1447) );
XNOR2X1TS U9430 ( .A(n8684), .B(FPSENCOS_d_ff2_X[30]), .Y(n8685) );
MXI2X1TS U9431 ( .A(n8685), .B(n9332), .S0(n8783), .Y(n1946) );
XNOR2X1TS U9432 ( .A(n8686), .B(FPSENCOS_d_ff2_Y[30]), .Y(n8687) );
MXI2X1TS U9433 ( .A(n8687), .B(n9331), .S0(n8783), .Y(n1848) );
MXI2X1TS U9434 ( .A(n8692), .B(n8691), .S0(n8690), .Y(n8694) );
CLKMX2X2TS U9435 ( .A(n8696), .B(FPMULT_P_Sgf[5]), .S0(n8761), .Y(n1558) );
MXI2X1TS U9436 ( .A(n8698), .B(n8697), .S0(n8775), .Y(n9844) );
CLKMX2X2TS U9437 ( .A(n8699), .B(FPMULT_exp_oper_result[2]), .S0(n9840), .Y(
n1547) );
OR2X2TS U9438 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n8701) );
AND2X2TS U9439 ( .A(n8701), .B(n8700), .Y(n8705) );
XOR2X1TS U9440 ( .A(n8705), .B(n8702), .Y(n8707) );
AOI22X1TS U9441 ( .A0(n8705), .A1(n8704), .B0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.B1(n8703), .Y(n8706) );
OAI2BB1X1TS U9442 ( .A0N(n6992), .A1N(n8707), .B0(n8706), .Y(n1349) );
OAI2BB1X1TS U9443 ( .A0N(FPADDSUB_LZD_output_NRM2_EW[0]), .A1N(n2909), .B0(
n8708), .Y(n1316) );
MXI2X1TS U9444 ( .A(n8710), .B(n8709), .S0(n8775), .Y(n9849) );
CLKMX2X2TS U9445 ( .A(n8711), .B(FPMULT_P_Sgf[6]), .S0(n9751), .Y(n9233) );
CLKMX2X2TS U9446 ( .A(n8712), .B(FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n2909),
.Y(n1411) );
CLKMX2X2TS U9447 ( .A(n8713), .B(FPMULT_exp_oper_result[3]), .S0(n9840), .Y(
n1546) );
MXI2X1TS U9448 ( .A(n8715), .B(n8714), .S0(n8775), .Y(n9850) );
INVX8TS U9449 ( .A(n8728), .Y(n8755) );
MXI2X1TS U9450 ( .A(n9322), .B(n8722), .S0(n8755), .Y(n2034) );
MXI2X1TS U9451 ( .A(n9323), .B(n8732), .S0(n8755), .Y(n2067) );
MXI2X1TS U9452 ( .A(n9327), .B(n8735), .S0(n8755), .Y(n2076) );
MXI2X1TS U9453 ( .A(n9325), .B(n8724), .S0(n8755), .Y(n2019) );
CLKMX2X2TS U9454 ( .A(n8716), .B(FPMULT_exp_oper_result[4]), .S0(n9840), .Y(
n1545) );
INVX8TS U9455 ( .A(n8728), .Y(n8738) );
MXI2X1TS U9456 ( .A(n9313), .B(n8725), .S0(n8738), .Y(n2058) );
MXI2X1TS U9457 ( .A(n9314), .B(n8717), .S0(n8738), .Y(n2052) );
MXI2X1TS U9458 ( .A(n9318), .B(n8721), .S0(n8738), .Y(n2028) );
MXI2X1TS U9459 ( .A(n9319), .B(n8719), .S0(n8738), .Y(n2064) );
MXI2X1TS U9460 ( .A(n9315), .B(n8723), .S0(n8738), .Y(n2055) );
MXI2X1TS U9461 ( .A(n9316), .B(n8718), .S0(n8738), .Y(n2031) );
MXI2X1TS U9462 ( .A(n9321), .B(n8720), .S0(n8738), .Y(n2037) );
MXI2X1TS U9463 ( .A(n9320), .B(n8727), .S0(n8738), .Y(n2025) );
MXI2X1TS U9464 ( .A(n9317), .B(n8726), .S0(n8738), .Y(n2040) );
MXI2X1TS U9465 ( .A(n9304), .B(n8729), .S0(n8739), .Y(n2047) );
MXI2X1TS U9466 ( .A(n9305), .B(n8717), .S0(n8739), .Y(n2050) );
MXI2X1TS U9467 ( .A(n9308), .B(n8747), .S0(n8742), .Y(n2020) );
MXI2X1TS U9468 ( .A(n9306), .B(n8718), .S0(n8739), .Y(n2029) );
MXI2X1TS U9469 ( .A(n9307), .B(n8719), .S0(n8742), .Y(n2062) );
MXI2X1TS U9470 ( .A(n9303), .B(n8731), .S0(n8739), .Y(n2011) );
MXI2X1TS U9471 ( .A(n9282), .B(n8720), .S0(n8742), .Y(n2035) );
MXI2X1TS U9472 ( .A(n9283), .B(n8744), .S0(n8742), .Y(n2068) );
MXI2X1TS U9473 ( .A(n9280), .B(n8730), .S0(n8739), .Y(n2014) );
MXI2X1TS U9474 ( .A(n9281), .B(n8721), .S0(n8739), .Y(n2026) );
MXI2X1TS U9475 ( .A(n9296), .B(n8722), .S0(n8742), .Y(n2032) );
MXI2X1TS U9476 ( .A(n9291), .B(n8723), .S0(n8739), .Y(n2053) );
MXI2X1TS U9477 ( .A(n9297), .B(n8724), .S0(n8742), .Y(n2017) );
MXI2X1TS U9478 ( .A(n9290), .B(n8725), .S0(n8739), .Y(n2056) );
MXI2X1TS U9479 ( .A(n9294), .B(n8726), .S0(n8739), .Y(n2038) );
MXI2X1TS U9480 ( .A(n9295), .B(n8727), .S0(n8742), .Y(n2023) );
INVX8TS U9481 ( .A(n8728), .Y(n8741) );
MXI2X1TS U9482 ( .A(n9312), .B(n8729), .S0(n8741), .Y(n2049) );
MXI2X1TS U9483 ( .A(n9310), .B(n8730), .S0(n8741), .Y(n2016) );
MXI2X1TS U9484 ( .A(n9309), .B(n8733), .S0(n8741), .Y(n2061) );
MXI2X1TS U9485 ( .A(n9311), .B(n8731), .S0(n8741), .Y(n2013) );
MXI2X1TS U9486 ( .A(n9292), .B(n8732), .S0(n8742), .Y(n2065) );
MXI2X1TS U9487 ( .A(n9293), .B(n8746), .S0(n8742), .Y(n2071) );
MXI2X1TS U9488 ( .A(n9302), .B(n8745), .S0(n8753), .Y(n2008) );
MXI2X1TS U9489 ( .A(n9279), .B(n8733), .S0(n8753), .Y(n2059) );
INVX2TS U9490 ( .A(FPSENCOS_d_ff_Xn[0]), .Y(n8736) );
CLKBUFX2TS U9491 ( .A(n8734), .Y(n8737) );
MXI2X1TS U9492 ( .A(n8736), .B(n8735), .S0(n8737), .Y(n2074) );
MXI2X1TS U9493 ( .A(n9346), .B(n8760), .S0(n8737), .Y(n1729) );
MXI2X1TS U9494 ( .A(n9445), .B(n8748), .S0(n8755), .Y(n1770) );
MXI2X1TS U9495 ( .A(n9200), .B(n8763), .S0(n8755), .Y(n1767) );
MXI2X1TS U9496 ( .A(n9452), .B(n7274), .S0(n8738), .Y(n2043) );
MXI2X1TS U9497 ( .A(n9411), .B(n7274), .S0(n8739), .Y(n2041) );
CLKMX2X2TS U9498 ( .A(n8740), .B(FPMULT_P_Sgf[7]), .S0(n8761), .Y(n1560) );
MXI2X1TS U9499 ( .A(n9451), .B(n8743), .S0(n8741), .Y(n1788) );
MXI2X1TS U9500 ( .A(n9446), .B(n8752), .S0(n8741), .Y(n1773) );
MXI2X1TS U9501 ( .A(n9450), .B(n8754), .S0(n8741), .Y(n1785) );
MXI2X1TS U9502 ( .A(n9449), .B(n8750), .S0(n8741), .Y(n1782) );
MXI2X1TS U9503 ( .A(n9447), .B(n8751), .S0(n8741), .Y(n1776) );
MXI2X1TS U9504 ( .A(n9448), .B(n8749), .S0(n8741), .Y(n1779) );
MXI2X1TS U9505 ( .A(n9288), .B(n2694), .S0(n8742), .Y(n2044) );
MXI2X1TS U9506 ( .A(n9410), .B(n8743), .S0(n8753), .Y(n1786) );
MXI2X1TS U9507 ( .A(n9326), .B(n8744), .S0(n8759), .Y(n2070) );
MXI2X1TS U9508 ( .A(n9329), .B(n8745), .S0(n8759), .Y(n2010) );
MXI2X1TS U9509 ( .A(n9328), .B(n8746), .S0(n8759), .Y(n2073) );
MXI2X1TS U9510 ( .A(n9324), .B(n8747), .S0(n8759), .Y(n2022) );
MXI2X1TS U9511 ( .A(n9171), .B(n8763), .S0(n8753), .Y(n1731) );
MXI2X1TS U9512 ( .A(n9287), .B(n8748), .S0(n8753), .Y(n1768) );
MXI2X1TS U9513 ( .A(n9284), .B(n8749), .S0(n8753), .Y(n1777) );
MXI2X1TS U9514 ( .A(n9278), .B(n8750), .S0(n8753), .Y(n1780) );
MXI2X1TS U9515 ( .A(n9286), .B(n8751), .S0(n8753), .Y(n1774) );
MXI2X1TS U9516 ( .A(n9277), .B(n8752), .S0(n8753), .Y(n1771) );
MXI2X1TS U9517 ( .A(n9285), .B(n8754), .S0(n8753), .Y(n1783) );
OAI22X1TS U9518 ( .A0(n8758), .A1(n8757), .B0(n8756), .B1(n8755), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
MXI2X1TS U9519 ( .A(n9413), .B(n2694), .S0(n8759), .Y(n2046) );
MXI2X1TS U9520 ( .A(n9414), .B(n8760), .S0(n8759), .Y(n1911) );
MXI2X1TS U9521 ( .A(n9172), .B(n8763), .S0(n8762), .Y(n1732) );
NAND2X1TS U9522 ( .A(n8764), .B(FPSENCOS_d_ff3_sh_y_out[31]), .Y(n8770) );
NAND2X1TS U9523 ( .A(n8765), .B(FPSENCOS_d_ff3_sh_x_out[31]), .Y(n8769) );
AOI22X1TS U9524 ( .A0(n8767), .A1(Data_2[31]), .B0(FPADDSUB_intDY_EWSW[31]),
.B1(n8766), .Y(n8768) );
CLKMX2X2TS U9525 ( .A(n8771), .B(FPMULT_P_Sgf[9]), .S0(n9752), .Y(n1562) );
CLKMX2X2TS U9526 ( .A(n8772), .B(FPMULT_P_Sgf[10]), .S0(n9752), .Y(n1563) );
MXI2X1TS U9527 ( .A(n9127), .B(n8454), .S0(n8779), .Y(n2147) );
MXI2X1TS U9528 ( .A(n8775), .B(n8774), .S0(n8779), .Y(n2144) );
CLKINVX1TS U9529 ( .A(n8776), .Y(n8777) );
MXI2X1TS U9530 ( .A(n8778), .B(n8777), .S0(n8779), .Y(n2150) );
MXI2X1TS U9531 ( .A(n9825), .B(n8778), .S0(n8779), .Y(n2149) );
MXI2X1TS U9532 ( .A(n8454), .B(n9825), .S0(n8779), .Y(n2148) );
NAND2X1TS U9533 ( .A(n8780), .B(n3630), .Y(n8787) );
OAI21X1TS U9534 ( .A0(n8784), .A1(n8782), .B0(n8781), .Y(n8786) );
NAND2X1TS U9535 ( .A(n8783), .B(FPSENCOS_d_ff3_LUT_out[6]), .Y(n8785) );
NAND3X1TS U9536 ( .A(n8784), .B(FPSENCOS_cont_iter_out[0]), .C(n3639), .Y(
n8792) );
NAND4X1TS U9537 ( .A(n8787), .B(n8786), .C(n8785), .D(n8792), .Y(n2129) );
NAND2X1TS U9538 ( .A(n8789), .B(n8788), .Y(n8793) );
NAND2X1TS U9539 ( .A(n8790), .B(FPSENCOS_d_ff3_LUT_out[2]), .Y(n8791) );
NAND3X1TS U9540 ( .A(n8793), .B(n8792), .C(n8791), .Y(n2133) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O22A_BEHAVIORAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22A_BEHAVIORAL_PP_V
|
module axis_shifter_v2 #
(
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_IMG_WBITS = 12,
parameter integer C_IMG_HBITS = 12
)
(
input wire clk,
input wire resetn,
input wire fsync,
input wire lsync,
input wire [C_IMG_WBITS-1 : 0] col_idx,
input wire [C_IMG_WBITS-1 : 0] col_idx_next,
input wire col_update,
input wire [C_IMG_HBITS-1 : 0] row_idx,
///input wire [C_IMG_HBITS-1 : 0] row_idx_next,
input wire row_update,
input wire [C_IMG_WBITS-1 : 0] s_win_left,
input wire [C_IMG_HBITS-1 : 0] s_win_top,
input wire [C_IMG_WBITS-1 : 0] s_win_width,
input wire [C_IMG_HBITS-1 : 0] s_win_height,
output wire s_need,
output reg s_eol,
output wire s_sof
);
reg col_need;
reg row_need;
always @ (posedge clk) begin
if (resetn == 1'b0 || lsync)
col_need <= 0;
else if (col_update) begin
if (col_idx == s_win_left + s_win_width)
col_need <= 0;
else if (col_idx == s_win_left)
col_need <= 1;
else
col_need <= col_need;
end
else
col_need <= col_need;
end
always @ (posedge clk) begin
if (resetn == 1'b0 || fsync)
row_need <= 0;
else if (row_update) begin
if (row_idx == s_win_top + s_win_height)
row_need <= 0;
else if (row_idx == s_win_top)
row_need <= 1;
else
row_need <= row_need;
end
else
row_need <= row_need;
end
assign s_need = (col_need && row_need);
reg first_line;
always @ (posedge clk) begin
if (resetn == 1'b0)
first_line <= 0;
else if (row_update)
first_line <= (row_idx == s_win_top);
else
first_line <= first_line;
end
reg first_pixel;
always @ (posedge clk) begin
if (resetn == 1'b0)
first_pixel <= 0;
else if (col_update)
first_pixel <= (col_idx == s_win_left);
else
first_pixel <= first_pixel;
end
assign s_sof = first_line && first_pixel;
always @ (posedge clk) begin
if (resetn == 1'b0)
s_eol <= 0;
else if (col_update)
s_eol <= (col_idx_next == s_win_left + s_win_width);
else
s_eol <= s_eol;
end
endmodule
|
/*
This is a simple SPI slave to GPIO bridge. It has a clock input, a synchronous
reset input, an SPI slave interface which is supposed to be hooked up to an SPI
master and an 8-bit output register. The contents of the output register is
updated by doing a one byte SPI transaction. A bit is registered every time
there is a falling edge on sclk and cs_n is deasserted.
*/
module spi_slave
#(parameter INIT_VALUE = 8'd0)
(
input clk,
input rst,
input sclk_i,
input mosi_i,
output miso_o = 1'b0,
input cs_n_i,
output reg [7:0] gpio_o);
reg sclk_r;
wire sclk_edge = ~cs_n_i & sclk_r & ~sclk_i;
reg [2:0] cnt;
always @(posedge clk) begin
sclk_r <= sclk_i;
if (cs_n_i)
cnt <= 3'd0;
else if (sclk_edge) begin
cnt <= cnt + 1'd1;
gpio_o[cnt] <= mosi_i;
end
if (rst) begin
cnt <= 3'd0;
sclk_r <= 1'd1;
gpio_o <= INIT_VALUE;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_PKG_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_PKG_SN_TB_V
/**
* udp_dlatch$PSa_pp$PKG$sN: Positive level sensitive D-type -latch
* with active low
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_psa_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg SET_ASYNC;
reg SLEEP_B;
reg NOTIFIER_REG;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER_REG = 1'bX;
SET_ASYNC = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER_REG = 1'b0;
#80 SET_ASYNC = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER_REG = 1'b1;
#220 SET_ASYNC = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER_REG = 1'b0;
#360 SET_ASYNC = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 SET_ASYNC = 1'b1;
#520 NOTIFIER_REG = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 SET_ASYNC = 1'bx;
#660 NOTIFIER_REG = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$PSa_pp$PKG$sN dut (.D(D), .SET_ASYNC(SET_ASYNC), .SLEEP_B(SLEEP_B), .NOTIFIER_REG(NOTIFIER_REG), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_PKG_SN_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O31AI_BEHAVIORAL_PP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o31ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31AI_BEHAVIORAL_PP_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:40:17 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.v
// Design : zynq_design_1_auto_pc_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zynq_design_1_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zynq_design_1_auto_pc_1
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [3:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [1:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *) input [11:0]s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [3:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [1:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output [11:0]m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [7:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output [0:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output [3:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output [3:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input [11:0]m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output [11:0]m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input [11:0]m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire [11:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [11:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [11:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [11:0]s_axi_wid;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "0" *)
(* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(s_axi_wid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "0" *) (* C_S_AXI_PROTOCOL = "1" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_axi_protocol_converter" *)
(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *) (* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *) (* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire m_axi_arready;
wire m_axi_awready;
wire [11:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [3:0]s_axi_arlen;
wire [1:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [3:0]s_axi_awlen;
wire [1:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
assign m_axi_araddr[31:0] = s_axi_araddr;
assign m_axi_arburst[1:0] = s_axi_arburst;
assign m_axi_arcache[3:0] = s_axi_arcache;
assign m_axi_arid[11:0] = s_axi_arid;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3:0] = s_axi_arlen;
assign m_axi_arlock[0] = s_axi_arlock[0];
assign m_axi_arprot[2:0] = s_axi_arprot;
assign m_axi_arqos[3:0] = s_axi_arqos;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2:0] = s_axi_arsize;
assign m_axi_aruser[0] = s_axi_aruser;
assign m_axi_arvalid = s_axi_arvalid;
assign m_axi_awaddr[31:0] = s_axi_awaddr;
assign m_axi_awburst[1:0] = s_axi_awburst;
assign m_axi_awcache[3:0] = s_axi_awcache;
assign m_axi_awid[11:0] = s_axi_awid;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3:0] = s_axi_awlen;
assign m_axi_awlock[0] = s_axi_awlock[0];
assign m_axi_awprot[2:0] = s_axi_awprot;
assign m_axi_awqos[3:0] = s_axi_awqos;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2:0] = s_axi_awsize;
assign m_axi_awuser[0] = s_axi_awuser;
assign m_axi_awvalid = s_axi_awvalid;
assign m_axi_bready = s_axi_bready;
assign m_axi_rready = s_axi_rready;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = s_axi_wuser;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_arready = m_axi_arready;
assign s_axi_awready = m_axi_awready;
assign s_axi_bid[11:0] = m_axi_bid;
assign s_axi_bresp[1:0] = m_axi_bresp;
assign s_axi_buser[0] = m_axi_buser;
assign s_axi_bvalid = m_axi_bvalid;
assign s_axi_rdata[31:0] = m_axi_rdata;
assign s_axi_rid[11:0] = m_axi_rid;
assign s_axi_rlast = m_axi_rlast;
assign s_axi_rresp[1:0] = m_axi_rresp;
assign s_axi_ruser[0] = m_axi_ruser;
assign s_axi_rvalid = m_axi_rvalid;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BLACKBOX_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_BLACKBOX_V
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:05:32 EST 2014
//
//
// Ports:
// Name I/O size props
// RDY_iport0_put O 1
// RDY_iport1_put O 1
// oport_get O 153
// RDY_oport_get O 1
// CLK I 1 clock
// RST_N I 1 reset
// iport0_put I 153
// iport1_put I 153
// EN_iport0_put I 1
// EN_iport1_put I 1
// EN_oport_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkPktMerge(CLK,
RST_N,
iport0_put,
EN_iport0_put,
RDY_iport0_put,
iport1_put,
EN_iport1_put,
RDY_iport1_put,
EN_oport_get,
oport_get,
RDY_oport_get);
input CLK;
input RST_N;
// action method iport0_put
input [152 : 0] iport0_put;
input EN_iport0_put;
output RDY_iport0_put;
// action method iport1_put
input [152 : 0] iport1_put;
input EN_iport1_put;
output RDY_iport1_put;
// actionvalue method oport_get
input EN_oport_get;
output [152 : 0] oport_get;
output RDY_oport_get;
// signals for module outputs
wire [152 : 0] oport_get;
wire RDY_iport0_put, RDY_iport1_put, RDY_oport_get;
// register fi0Active
reg fi0Active;
wire fi0Active_D_IN, fi0Active_EN;
// register fi0HasPrio
reg fi0HasPrio;
reg fi0HasPrio_D_IN;
wire fi0HasPrio_EN;
// register fi1Active
reg fi1Active;
wire fi1Active_D_IN, fi1Active_EN;
// ports of submodule fi0
wire [152 : 0] fi0_D_IN, fi0_D_OUT;
wire fi0_CLR, fi0_DEQ, fi0_EMPTY_N, fi0_ENQ, fi0_FULL_N;
// ports of submodule fi1
wire [152 : 0] fi1_D_IN, fi1_D_OUT;
wire fi1_CLR, fi1_DEQ, fi1_EMPTY_N, fi1_ENQ, fi1_FULL_N;
// ports of submodule fo
reg [152 : 0] fo_D_IN;
wire [152 : 0] fo_D_OUT;
wire fo_CLR, fo_DEQ, fo_EMPTY_N, fo_ENQ, fo_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_arbitrate,
WILL_FIRE_RL_fi0_advance,
WILL_FIRE_RL_fi1_advance;
// inputs to muxes for submodule ports
wire [152 : 0] MUX_fo_enq_1__VAL_3;
wire MUX_fi0Active_write_1__SEL_1,
MUX_fi0Active_write_1__VAL_1,
MUX_fi1Active_write_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h900;
wire fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24;
// action method iport0_put
assign RDY_iport0_put = fi0_FULL_N ;
// action method iport1_put
assign RDY_iport1_put = fi1_FULL_N ;
// actionvalue method oport_get
assign oport_get = fo_D_OUT ;
assign RDY_oport_get = fo_EMPTY_N ;
// submodule fi0
arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi0(.CLK(CLK),
.RST_N(RST_N),
.D_IN(fi0_D_IN),
.DEQ(fi0_DEQ),
.ENQ(fi0_ENQ),
.CLR(fi0_CLR),
.D_OUT(fi0_D_OUT),
.EMPTY_N(fi0_EMPTY_N),
.FULL_N(fi0_FULL_N));
// submodule fi1
arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fi1(.CLK(CLK),
.RST_N(RST_N),
.D_IN(fi1_D_IN),
.DEQ(fi1_DEQ),
.ENQ(fi1_ENQ),
.CLR(fi1_CLR),
.D_OUT(fi1_D_OUT),
.EMPTY_N(fi1_EMPTY_N),
.FULL_N(fi1_FULL_N));
// submodule fo
arSRLFIFOD #(.width(32'd153), .l2depth(32'd4)) fo(.CLK(CLK),
.RST_N(RST_N),
.D_IN(fo_D_IN),
.DEQ(fo_DEQ),
.ENQ(fo_ENQ),
.CLR(fo_CLR),
.D_OUT(fo_D_OUT),
.EMPTY_N(fo_EMPTY_N),
.FULL_N(fo_FULL_N));
// rule RL_fi0_advance
assign WILL_FIRE_RL_fi0_advance =
fo_FULL_N && fi0_EMPTY_N && !fi1Active &&
!WILL_FIRE_RL_arbitrate ;
// rule RL_fi1_advance
assign WILL_FIRE_RL_fi1_advance =
fo_FULL_N && fi1_EMPTY_N && !fi0Active &&
!WILL_FIRE_RL_fi0_advance &&
!WILL_FIRE_RL_arbitrate ;
// rule RL_arbitrate
assign WILL_FIRE_RL_arbitrate =
fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24 &&
fi0_EMPTY_N &&
fi1_EMPTY_N &&
!fi0Active &&
!fi1Active ;
// inputs to muxes for submodule ports
assign MUX_fi0Active_write_1__SEL_1 = WILL_FIRE_RL_arbitrate && fi0HasPrio ;
assign MUX_fi1Active_write_1__SEL_1 =
WILL_FIRE_RL_arbitrate && !fi0HasPrio ;
assign MUX_fi0Active_write_1__VAL_1 =
fi0HasPrio ? !fi0_D_OUT[151] : !fi1_D_OUT[151] ;
assign MUX_fo_enq_1__VAL_3 = fi0HasPrio ? fi0_D_OUT : fi1_D_OUT ;
// register fi0Active
assign fi0Active_D_IN =
MUX_fi0Active_write_1__SEL_1 ?
MUX_fi0Active_write_1__VAL_1 :
!fi0_D_OUT[151] ;
assign fi0Active_EN =
WILL_FIRE_RL_arbitrate && fi0HasPrio ||
WILL_FIRE_RL_fi0_advance ;
// register fi0HasPrio
always@(WILL_FIRE_RL_arbitrate or
fi0HasPrio or WILL_FIRE_RL_fi0_advance or WILL_FIRE_RL_fi1_advance)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_arbitrate: fi0HasPrio_D_IN = !fi0HasPrio;
WILL_FIRE_RL_fi0_advance: fi0HasPrio_D_IN = 1'd0;
WILL_FIRE_RL_fi1_advance: fi0HasPrio_D_IN = 1'd1;
default: fi0HasPrio_D_IN = 1'b0 /* unspecified value */ ;
endcase
end
assign fi0HasPrio_EN =
WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance ||
WILL_FIRE_RL_fi1_advance ;
// register fi1Active
assign fi1Active_D_IN =
MUX_fi1Active_write_1__SEL_1 ?
MUX_fi0Active_write_1__VAL_1 :
!fi1_D_OUT[151] ;
assign fi1Active_EN =
WILL_FIRE_RL_arbitrate && !fi0HasPrio ||
WILL_FIRE_RL_fi1_advance ;
// submodule fi0
assign fi0_D_IN = iport0_put ;
assign fi0_DEQ =
WILL_FIRE_RL_arbitrate && fi0HasPrio ||
WILL_FIRE_RL_fi0_advance ;
assign fi0_ENQ = EN_iport0_put ;
assign fi0_CLR = 1'b0 ;
// submodule fi1
assign fi1_D_IN = iport1_put ;
assign fi1_DEQ =
WILL_FIRE_RL_arbitrate && !fi0HasPrio ||
WILL_FIRE_RL_fi1_advance ;
assign fi1_ENQ = EN_iport1_put ;
assign fi1_CLR = 1'b0 ;
// submodule fo
always@(WILL_FIRE_RL_fi0_advance or
fi0_D_OUT or
WILL_FIRE_RL_fi1_advance or
fi1_D_OUT or WILL_FIRE_RL_arbitrate or MUX_fo_enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fi0_advance: fo_D_IN = fi0_D_OUT;
WILL_FIRE_RL_fi1_advance: fo_D_IN = fi1_D_OUT;
WILL_FIRE_RL_arbitrate: fo_D_IN = MUX_fo_enq_1__VAL_3;
default: fo_D_IN =
153'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fo_DEQ = EN_oport_get ;
assign fo_ENQ =
WILL_FIRE_RL_fi0_advance || WILL_FIRE_RL_fi1_advance ||
WILL_FIRE_RL_arbitrate ;
assign fo_CLR = 1'b0 ;
// remaining internal signals
assign fo_RDY_enq_AND_IF_fi0HasPrio_2_THEN_fi0_RDY_de_ETC___d24 =
fo_FULL_N && (fi0HasPrio ? fi0_EMPTY_N : fi1_EMPTY_N) ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fi0Active <= `BSV_ASSIGNMENT_DELAY 1'd0;
fi0HasPrio <= `BSV_ASSIGNMENT_DELAY 1'd1;
fi1Active <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (fi0Active_EN) fi0Active <= `BSV_ASSIGNMENT_DELAY fi0Active_D_IN;
if (fi0HasPrio_EN)
fi0HasPrio <= `BSV_ASSIGNMENT_DELAY fi0HasPrio_D_IN;
if (fi1Active_EN) fi1Active <= `BSV_ASSIGNMENT_DELAY fi1Active_D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fi0Active = 1'h0;
fi0HasPrio = 1'h0;
fi1Active = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_arbitrate)
begin
v__h900 = $time;
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_arbitrate)
$display("[%0d]: %m: Merge from:%d Data:%x",
v__h900,
fi0HasPrio,
fi0HasPrio ? fi0_D_OUT[127:0] : fi1_D_OUT[127:0]);
end
// synopsys translate_on
endmodule // mkPktMerge
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SDFSBP_FUNCTIONAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSBP_FUNCTIONAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description:
// The instruction fetch unit (IFU) contains the icache, ifq and
// fetch dp.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
`include "ifu.h"
`include "lsu.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module sparc_ifu (/*AUTOARG*/
// Outputs
spc_efc_ifuse_data, sparc_sscan_so, mbist_icache_fail, mbist_done,
mbist_dcache_write, mbist_dcache_word, mbist_dcache_way,
mbist_dcache_read, mbist_dcache_index, mbist_dcache_fail,
ifu_tlu_ttype_m, ifu_tlu_trap_m, ifu_tlu_thrid_e, ifu_tlu_thrid_d,
ifu_tlu_sraddr_d_v2, ifu_tlu_sraddr_d, ifu_tlu_sir_inst_m,
ifu_tlu_sftint_m, ifu_tlu_rstint_m, ifu_tlu_rsr_inst_d,
ifu_tlu_retry_inst_d, ifu_tlu_priv_violtn_m, ifu_tlu_pc_oor_e,
ifu_tlu_pc_m, ifu_tlu_npc_m, ifu_tlu_mb_inst_e, ifu_tlu_l2imiss,
ifu_tlu_itlb_done, ifu_tlu_inst_vld_m, ifu_tlu_immu_miss_m,
ifu_tlu_imm_asi_d, ifu_tlu_icmiss_e, ifu_tlu_hwint_m,
ifu_tlu_flush_m, ifu_tlu_flsh_inst_e, ifu_tlu_done_inst_d,
ifu_tlu_alt_space_d, ifu_spu_trap_ack, ifu_spu_nceen,
ifu_spu_inst_vld_w, ifu_mmu_trap_m, ifu_lsu_wsr_inst_d,
ifu_lsu_swap_e, ifu_lsu_st_inst_e, ifu_lsu_sign_ext_e,
ifu_lsu_rd_e, ifu_lsu_pref_inst_e, ifu_lsu_pcxreq_d,
ifu_lsu_pcxpkt_e, ifu_lsu_nceen, ifu_lsu_memref_d,
ifu_lsu_ldxa_tid_w2, ifu_lsu_ldxa_illgl_va_w2,
ifu_lsu_ldxa_data_w2, ifu_lsu_ldxa_data_vld_w2, ifu_lsu_ldstub_e,
ifu_lsu_ldst_size_e, ifu_lsu_ldst_fp_e, ifu_lsu_ldst_dbl_e,
ifu_lsu_ld_inst_e, ifu_lsu_inv_clear, ifu_lsu_imm_asi_vld_d,
ifu_lsu_imm_asi_d, ifu_lsu_ibuf_busy, ifu_lsu_fwd_wr_ack,
ifu_lsu_fwd_data_vld, ifu_lsu_error_inj, ifu_lsu_destid_s,
ifu_lsu_casa_e, ifu_lsu_asi_rd_unc, ifu_lsu_asi_ack,
ifu_lsu_alt_space_d, ifu_ffu_visop_d, ifu_ffu_stfsr_d,
ifu_ffu_quad_op_e, ifu_ffu_mvcnd_m, ifu_ffu_ldxfsr_d,
ifu_ffu_ldst_size_d, ifu_ffu_ldfsr_d, ifu_ffu_inj_frferr,
ifu_ffu_fst_d, ifu_ffu_frs2_d, ifu_ffu_frs1_d, ifu_ffu_frd_d,
ifu_ffu_fpopcode_d, ifu_ffu_fpop2_d, ifu_ffu_fpop1_d,
ifu_ffu_fld_d, ifu_ffu_fcc_num_d, ifu_exu_wsr_inst_d,
ifu_exu_wen_d, ifu_exu_useimm_d, ifu_exu_usecin_d,
ifu_exu_use_rsr_e_l, ifu_exu_tv_d, ifu_exu_ttype_vld_m,
ifu_exu_tid_s2, ifu_exu_tcc_e, ifu_exu_tagop_d, ifu_exu_shiftop_d,
ifu_exu_sethi_inst_d, ifu_exu_setcc_d, ifu_exu_saved_e,
ifu_exu_save_d, ifu_exu_rs3o_vld_d, ifu_exu_rs3e_vld_d,
ifu_exu_rs3_s, ifu_exu_rs2_vld_d, ifu_exu_rs2_s,
ifu_exu_rs1_vld_d, ifu_exu_rs1_s, ifu_exu_return_d,
ifu_exu_restored_e, ifu_exu_restore_d, ifu_exu_ren3_s,
ifu_exu_ren2_s, ifu_exu_ren1_s, ifu_exu_rd_ifusr_e,
ifu_exu_rd_ffusr_e, ifu_exu_rd_exusr_e, ifu_exu_rd_d,
ifu_exu_range_check_other_d, ifu_exu_range_check_jlret_d,
ifu_exu_pcver_e, ifu_exu_pc_d, ifu_exu_nceen_e, ifu_exu_muls_d,
ifu_exu_kill_e, ifu_exu_invert_d, ifu_exu_inst_vld_w,
ifu_exu_inst_vld_e, ifu_exu_inj_irferr, ifu_exu_imm_data_d,
ifu_exu_ialign_d, ifu_exu_flushw_e, ifu_exu_enshift_d,
ifu_exu_ecc_mask, ifu_exu_dontmv_regz1_e, ifu_exu_dontmv_regz0_e,
ifu_exu_disable_ce_e, ifu_exu_dbrinst_d, ifu_exu_casa_d,
ifu_exu_aluop_d, ifu_exu_addr_mask_d, so0, short_so0, short_so1,
ifu_tlu_inst_vld_w, ifu_tlu_flush_w, ifu_lsu_alt_space_e,
ifu_tlu_ttype_vld_m, ifu_exu_muldivop_d, ifu_lsu_thrid_s,
mbist_write_data,
// Inputs
tlu_lsu_redmode, tlu_lsu_pstate_priv, tlu_lsu_pstate_am,
tlu_itlb_wr_vld_g, tlu_itlb_tag_rd_g, tlu_itlb_invalidate_all_g,
tlu_itlb_dmp_vld_g, tlu_itlb_dmp_nctxt_g, tlu_itlb_dmp_actxt_g,
tlu_itlb_data_rd_g, tlu_ifu_trappc_w2, tlu_ifu_trappc_vld_w1,
tlu_ifu_trapnpc_w2, tlu_ifu_trapnpc_vld_w1, tlu_ifu_trap_tid_w1,
tlu_ifu_sftint_vld, tlu_ifu_rstthr_i2, tlu_ifu_rstint_i2,
tlu_ifu_resumint_i2, tlu_ifu_rerr_vld, tlu_ifu_pstate_pef,
tlu_ifu_pstate_ie, tlu_ifu_nukeint_i2, tlu_ifu_hwint_i3,
tlu_ifu_hintp_vld, tlu_ifu_flush_pipe_w, tlu_idtlb_dmp_thrid_g,
tlu_hpstate_priv, tlu_hpstate_ibe, tlu_hpstate_enb, testmode_l,
spu_ifu_unc_err_w1, spu_ifu_ttype_w2, spu_ifu_ttype_vld_w2,
spu_ifu_ttype_tid_w2, spu_ifu_mamem_err_w1, spu_ifu_int_w2,
spu_ifu_err_addr_w2, spu_ifu_corr_err_w2, sehold, se, rclk,
mbist_userdata_mode, mbist_stop_on_next_fail, mbist_stop_on_fail,
mbist_start, mbist_loop_on_address, mbist_loop_mode,
mbist_dcache_data_in, mbist_bisi_mode, lsu_t3_pctxt_state,
lsu_t2_pctxt_state, lsu_t1_pctxt_state, lsu_t0_pctxt_state,
lsu_pid_state3, lsu_pid_state2, lsu_pid_state1, lsu_pid_state0,
lsu_ifu_t3_tlz, lsu_ifu_t2_tlz, lsu_ifu_t1_tlz, lsu_ifu_t0_tlz,
lsu_ifu_stxa_data, lsu_ifu_stbcnt3, lsu_ifu_stbcnt2,
lsu_ifu_stbcnt1, lsu_ifu_stbcnt0, lsu_ifu_stallreq,
lsu_ifu_quad_asi_e, lsu_ifu_pcxpkt_ack_d,
lsu_ifu_ldsta_internal_e, lsu_ifu_ldst_miss_g, lsu_ifu_ldst_cmplt,
lsu_ifu_ld_pcxpkt_vld, lsu_ifu_ld_pcxpkt_tid,
lsu_ifu_ld_icache_index, lsu_ifu_l2_unc_error,
lsu_ifu_l2_corr_error, lsu_ifu_io_error, lsu_ifu_inj_ack,
lsu_ifu_icache_en, lsu_ifu_error_tid, lsu_ifu_err_addr,
lsu_ifu_dtlb_tag_ue, lsu_ifu_dtlb_data_ue, lsu_ifu_dtlb_data_su,
lsu_ifu_direct_map_l1, lsu_ifu_dcache_tag_perror,
lsu_ifu_dcache_data_perror, lsu_ifu_dc_parity_error_w2,
lsu_ifu_cpxpkt_i1, lsu_ifu_asi_vld, lsu_ifu_asi_thrid,
lsu_ifu_asi_state, lsu_ifu_asi_load, lsu_ifu_asi_addr,
lsu_ifu_addr_real_l, grst_l, gdbginit_l, ffu_ifu_tid_w2,
ffu_ifu_stallreq, ffu_ifu_inj_ack, ffu_ifu_fst_ce_w,
ffu_ifu_fpop_done_w2, ffu_ifu_err_synd_w2, ffu_ifu_err_reg_w2,
ffu_ifu_ecc_ue_w2, ffu_ifu_ecc_ce_w2, ffu_ifu_cc_w2,
ffu_ifu_cc_vld_w2, exu_ifu_va_oor_m, exu_ifu_spill_e,
exu_ifu_regz_e, exu_ifu_regn_e, exu_ifu_oddwin_s,
exu_ifu_longop_done_g, exu_ifu_inj_ack, exu_ifu_err_synd_m,
exu_ifu_err_reg_m, exu_ifu_ecc_ue_m, exu_ifu_ecc_ce_m,
exu_ifu_cc_d, exu_ifu_brpc_e, efc_spc_ifuse_dshift,
efc_spc_ifuse_data, efc_spc_ifuse_ashift, efc_spc_fuse_clk2,
efc_spc_fuse_clk1, ctu_tck, ctu_sscan_tid, ctu_sscan_snap,
ctu_sscan_se, const_maskid, const_cpuid, arst_l,
mem_write_disable, mux_drive_disable, exu_tlu_wsr_data_m,
lsu_ictag_mrgn, lsu_idtlb_mrgn, si0, short_si0, short_si1,
tlu_itlb_tte_tag_w2, tlu_itlb_tte_data_w2,
tlu_itlb_rw_index_vld_g, tlu_itlb_rw_index_g, tlu_idtlb_dmp_key_g,
tlu_itlb_dmp_all_g, lsu_sscan_data, tlu_sscan_data
);
input mem_write_disable;
input mux_drive_disable;
input [2:0] exu_tlu_wsr_data_m;
input [3:0] lsu_ictag_mrgn;
input [7:0] lsu_idtlb_mrgn;
// eco 5362
output ifu_exu_addr_mask_d;
// scan ports
input si0, short_si0,short_si1;
output so0,short_so0,short_so1;
output ifu_tlu_inst_vld_w; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_flush_w; // From fcl of sparc_ifu_fcl.v
output ifu_lsu_alt_space_e; // From dec of sparc_ifu_dec.v
output ifu_tlu_ttype_vld_m;// From fcl of sparc_ifu_fcl.v
output [4:0] ifu_exu_muldivop_d;
output [1:0] ifu_lsu_thrid_s;
// itlb inputs
input [58:0] tlu_itlb_tte_tag_w2;
input [42:0] tlu_itlb_tte_data_w2;
input tlu_itlb_rw_index_vld_g;
input [5:0] tlu_itlb_rw_index_g;
input [40:0] tlu_idtlb_dmp_key_g;
input tlu_itlb_dmp_all_g;
// sscan rename
input [15:0] lsu_sscan_data;
input [62:0] tlu_sscan_data;
output [7:0] mbist_write_data; // From mbist of sparc_ifu_mbist.v
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input arst_l; // To swl of sparc_ifu_swl.v, ...
input [3:0] const_cpuid; // To swl of sparc_ifu_swl.v, ...
input [7:0] const_maskid; // To fdp of sparc_ifu_fdp.v
input ctu_sscan_se; // To sscan of sparc_ifu_sscan.v
input ctu_sscan_snap; // To sscan of sparc_ifu_sscan.v
input [3:0] ctu_sscan_tid; // To swl of sparc_ifu_swl.v, ...
input ctu_tck; // To sscan of sparc_ifu_sscan.v
input efc_spc_fuse_clk1; // To icdhdr of cmp_sram_redhdr.v, ...
input efc_spc_fuse_clk2; // To icdhdr of cmp_sram_redhdr.v
input efc_spc_ifuse_ashift; // To icdhdr of cmp_sram_redhdr.v
input efc_spc_ifuse_data; // To icdhdr of cmp_sram_redhdr.v
input efc_spc_ifuse_dshift; // To icdhdr of cmp_sram_redhdr.v
input [47:0] exu_ifu_brpc_e; // To fdp of sparc_ifu_fdp.v
input [7:0] exu_ifu_cc_d; // To dcl of sparc_ifu_dcl.v
input exu_ifu_ecc_ce_m; // To fcl of sparc_ifu_fcl.v, ...
input exu_ifu_ecc_ue_m; // To errctl of sparc_ifu_errctl.v
input [7:0] exu_ifu_err_reg_m; // To errdp of sparc_ifu_errdp.v
input [7:0] exu_ifu_err_synd_m; // To errdp of sparc_ifu_errdp.v
input exu_ifu_inj_ack; // To errctl of sparc_ifu_errctl.v
input [3:0] exu_ifu_longop_done_g; // To swl of sparc_ifu_swl.v
input [3:0] exu_ifu_oddwin_s; // To fcl of sparc_ifu_fcl.v
input exu_ifu_regn_e; // To dcl of sparc_ifu_dcl.v
input exu_ifu_regz_e; // To fcl of sparc_ifu_fcl.v
input exu_ifu_spill_e; // To swl of sparc_ifu_swl.v
input exu_ifu_va_oor_m; // To fcl of sparc_ifu_fcl.v
input [3:0] ffu_ifu_cc_vld_w2; // To dcl of sparc_ifu_dcl.v
input [7:0] ffu_ifu_cc_w2; // To dcl of sparc_ifu_dcl.v
input ffu_ifu_ecc_ce_w2; // To errctl of sparc_ifu_errctl.v
input ffu_ifu_ecc_ue_w2; // To errctl of sparc_ifu_errctl.v
input [5:0] ffu_ifu_err_reg_w2; // To errdp of sparc_ifu_errdp.v
input [13:0] ffu_ifu_err_synd_w2; // To errdp of sparc_ifu_errdp.v
input ffu_ifu_fpop_done_w2; // To swl of sparc_ifu_swl.v
input ffu_ifu_fst_ce_w; // To swl of sparc_ifu_swl.v, ...
input ffu_ifu_inj_ack; // To errctl of sparc_ifu_errctl.v
input ffu_ifu_stallreq; // To fcl of sparc_ifu_fcl.v
input [1:0] ffu_ifu_tid_w2; // To swl of sparc_ifu_swl.v, ...
input gdbginit_l; // To swl of sparc_ifu_swl.v, ...
input grst_l; // To swl of sparc_ifu_swl.v, ...
input [3:0] lsu_ifu_addr_real_l; // To fcl of sparc_ifu_fcl.v
input [17:0] lsu_ifu_asi_addr; // To ifqdp of sparc_ifu_ifqdp.v
input lsu_ifu_asi_load; // To ifqctl of sparc_ifu_ifqctl.v
input [7:0] lsu_ifu_asi_state; // To ifqctl of sparc_ifu_ifqctl.v
input [1:0] lsu_ifu_asi_thrid; // To ifqctl of sparc_ifu_ifqctl.v
input lsu_ifu_asi_vld; // To ifqctl of sparc_ifu_ifqctl.v
input [`CPX_WIDTH-1:0]lsu_ifu_cpxpkt_i1; // To ifqdp of sparc_ifu_ifqdp.v
input lsu_ifu_dc_parity_error_w2;// To swl of sparc_ifu_swl.v, ...
input lsu_ifu_dcache_data_perror;// To errctl of sparc_ifu_errctl.v
input lsu_ifu_dcache_tag_perror;// To errctl of sparc_ifu_errctl.v
input lsu_ifu_direct_map_l1; // To ifqctl of sparc_ifu_ifqctl.v
input lsu_ifu_dtlb_data_su; // To errctl of sparc_ifu_errctl.v
input lsu_ifu_dtlb_data_ue; // To errctl of sparc_ifu_errctl.v
input lsu_ifu_dtlb_tag_ue; // To errctl of sparc_ifu_errctl.v
input [47:4] lsu_ifu_err_addr; // To errdp of sparc_ifu_errdp.v
input [1:0] lsu_ifu_error_tid; // To errctl of sparc_ifu_errctl.v
input [3:0] lsu_ifu_icache_en; // To fcl of sparc_ifu_fcl.v
input [3:0] lsu_ifu_inj_ack; // To errctl of sparc_ifu_errctl.v
input lsu_ifu_io_error; // To errctl of sparc_ifu_errctl.v
input lsu_ifu_l2_corr_error; // To errctl of sparc_ifu_errctl.v
input lsu_ifu_l2_unc_error; // To errctl of sparc_ifu_errctl.v
input [`IC_IDX_HI:5] lsu_ifu_ld_icache_index;// To invctl of sparc_ifu_invctl.v
input [1:0] lsu_ifu_ld_pcxpkt_tid; // To invctl of sparc_ifu_invctl.v
input lsu_ifu_ld_pcxpkt_vld; // To invctl of sparc_ifu_invctl.v
input [3:0] lsu_ifu_ldst_cmplt; // To swl of sparc_ifu_swl.v
input lsu_ifu_ldst_miss_g; // To swl of sparc_ifu_swl.v
input lsu_ifu_ldsta_internal_e;// To dec of sparc_ifu_dec.v, ...
input lsu_ifu_pcxpkt_ack_d; // To ifqctl of sparc_ifu_ifqctl.v
input lsu_ifu_quad_asi_e; // To swl of sparc_ifu_swl.v
input lsu_ifu_stallreq; // To fcl of sparc_ifu_fcl.v
input [3:0] lsu_ifu_stbcnt0; // To swl of sparc_ifu_swl.v
input [3:0] lsu_ifu_stbcnt1; // To swl of sparc_ifu_swl.v
input [3:0] lsu_ifu_stbcnt2; // To swl of sparc_ifu_swl.v
input [3:0] lsu_ifu_stbcnt3; // To swl of sparc_ifu_swl.v
input [47:0] lsu_ifu_stxa_data; // To ifqdp of sparc_ifu_ifqdp.v
input lsu_ifu_t0_tlz; // To fcl of sparc_ifu_fcl.v
input lsu_ifu_t1_tlz; // To fcl of sparc_ifu_fcl.v
input lsu_ifu_t2_tlz; // To fcl of sparc_ifu_fcl.v
input lsu_ifu_t3_tlz; // To fcl of sparc_ifu_fcl.v
input [2:0] lsu_pid_state0; // To fcl of sparc_ifu_fcl.v
input [2:0] lsu_pid_state1; // To fcl of sparc_ifu_fcl.v
input [2:0] lsu_pid_state2; // To fcl of sparc_ifu_fcl.v
input [2:0] lsu_pid_state3; // To fcl of sparc_ifu_fcl.v
input [12:0] lsu_t0_pctxt_state; // To fdp of sparc_ifu_fdp.v
input [12:0] lsu_t1_pctxt_state; // To fdp of sparc_ifu_fdp.v
input [12:0] lsu_t2_pctxt_state; // To fdp of sparc_ifu_fdp.v
input [12:0] lsu_t3_pctxt_state; // To fdp of sparc_ifu_fdp.v
input mbist_bisi_mode; // To mbist of sparc_ifu_mbist.v
input [71:0] mbist_dcache_data_in; // To mbist of sparc_ifu_mbist.v
input mbist_loop_mode; // To mbist of sparc_ifu_mbist.v
input mbist_loop_on_address; // To mbist of sparc_ifu_mbist.v
input mbist_start; // To mbist of sparc_ifu_mbist.v
input mbist_stop_on_fail; // To mbist of sparc_ifu_mbist.v
input mbist_stop_on_next_fail;// To mbist of sparc_ifu_mbist.v
input mbist_userdata_mode; // To mbist of sparc_ifu_mbist.v
input rclk; // To dec of sparc_ifu_dec.v, ...
input se; // To dec of sparc_ifu_dec.v, ...
input sehold; // To fcl of sparc_ifu_fcl.v, ...
input spu_ifu_corr_err_w2; // To errctl of sparc_ifu_errctl.v
input [39:4] spu_ifu_err_addr_w2; // To errdp of sparc_ifu_errdp.v
input spu_ifu_int_w2; // To errctl of sparc_ifu_errctl.v
input spu_ifu_mamem_err_w1; // To errctl of sparc_ifu_errctl.v
input [1:0] spu_ifu_ttype_tid_w2; // To fcl of sparc_ifu_fcl.v, ...
input spu_ifu_ttype_vld_w2; // To fcl of sparc_ifu_fcl.v
input spu_ifu_ttype_w2; // To fcl of sparc_ifu_fcl.v
input spu_ifu_unc_err_w1; // To errctl of sparc_ifu_errctl.v
input testmode_l; // To icdhdr of cmp_sram_redhdr.v
input [3:0] tlu_hpstate_enb; // To fcl of sparc_ifu_fcl.v
input [3:0] tlu_hpstate_ibe; // To swl of sparc_ifu_swl.v
input [3:0] tlu_hpstate_priv; // To fcl of sparc_ifu_fcl.v
input [1:0] tlu_idtlb_dmp_thrid_g; // To fcl of sparc_ifu_fcl.v
input tlu_ifu_flush_pipe_w; // To swl of sparc_ifu_swl.v, ...
input [3:0] tlu_ifu_hintp_vld; // To fcl of sparc_ifu_fcl.v
input [3:0] tlu_ifu_hwint_i3; // To fcl of sparc_ifu_fcl.v
input tlu_ifu_nukeint_i2; // To fcl of sparc_ifu_fcl.v
input [3:0] tlu_ifu_pstate_ie; // To fcl of sparc_ifu_fcl.v
input [3:0] tlu_ifu_pstate_pef; // To swl of sparc_ifu_swl.v
input [3:0] tlu_ifu_rerr_vld; // To fcl of sparc_ifu_fcl.v
input tlu_ifu_resumint_i2; // To fcl of sparc_ifu_fcl.v
input tlu_ifu_rstint_i2; // To fcl of sparc_ifu_fcl.v
input [3:0] tlu_ifu_rstthr_i2; // To fcl of sparc_ifu_fcl.v
input [3:0] tlu_ifu_sftint_vld; // To fcl of sparc_ifu_fcl.v
input [1:0] tlu_ifu_trap_tid_w1; // To swl of sparc_ifu_swl.v, ...
input tlu_ifu_trapnpc_vld_w1; // To fcl of sparc_ifu_fcl.v
input [48:0] tlu_ifu_trapnpc_w2; // To fdp of sparc_ifu_fdp.v
input tlu_ifu_trappc_vld_w1; // To swl of sparc_ifu_swl.v, ...
input [48:0] tlu_ifu_trappc_w2; // To fdp of sparc_ifu_fdp.v
input tlu_itlb_data_rd_g; // To fcl of sparc_ifu_fcl.v
input tlu_itlb_dmp_actxt_g; // To fdp of sparc_ifu_fdp.v
input tlu_itlb_dmp_nctxt_g; // To fdp of sparc_ifu_fdp.v
input tlu_itlb_dmp_vld_g; // To fcl of sparc_ifu_fcl.v
input tlu_itlb_invalidate_all_g;// To fcl of sparc_ifu_fcl.v
input tlu_itlb_tag_rd_g; // To fcl of sparc_ifu_fcl.v
input tlu_itlb_wr_vld_g; // To fcl of sparc_ifu_fcl.v
input [3:0] tlu_lsu_pstate_am; // To fcl of sparc_ifu_fcl.v
input [3:0] tlu_lsu_pstate_priv; // To fcl of sparc_ifu_fcl.v, ...
input [3:0] tlu_lsu_redmode; // To fcl of sparc_ifu_fcl.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2:0] ifu_exu_aluop_d; // From dec of sparc_ifu_dec.v
output ifu_exu_casa_d; // From dec of sparc_ifu_dec.v
output ifu_exu_dbrinst_d; // From dcl of sparc_ifu_dcl.v
output ifu_exu_disable_ce_e; // From fcl of sparc_ifu_fcl.v
output ifu_exu_dontmv_regz0_e; // From dcl of sparc_ifu_dcl.v
output ifu_exu_dontmv_regz1_e; // From dcl of sparc_ifu_dcl.v
output [7:0] ifu_exu_ecc_mask; // From errctl of sparc_ifu_errctl.v
output ifu_exu_enshift_d; // From dec of sparc_ifu_dec.v
output ifu_exu_flushw_e; // From dec of sparc_ifu_dec.v
output ifu_exu_ialign_d; // From dec of sparc_ifu_dec.v
output [31:0] ifu_exu_imm_data_d; // From imd of sparc_ifu_imd.v
output ifu_exu_inj_irferr; // From errctl of sparc_ifu_errctl.v
output ifu_exu_inst_vld_e; // From fcl of sparc_ifu_fcl.v
output ifu_exu_inst_vld_w; // From fcl of sparc_ifu_fcl.v
output ifu_exu_invert_d; // From dec of sparc_ifu_dec.v
output ifu_exu_kill_e; // From dcl of sparc_ifu_dcl.v
output ifu_exu_muls_d; // From dec of sparc_ifu_dec.v
output ifu_exu_nceen_e; // From errctl of sparc_ifu_errctl.v
output [47:0] ifu_exu_pc_d; // From fdp of sparc_ifu_fdp.v
output [63:0] ifu_exu_pcver_e; // From fdp of sparc_ifu_fdp.v
output ifu_exu_range_check_jlret_d;// From dec of sparc_ifu_dec.v
output ifu_exu_range_check_other_d;// From dec of sparc_ifu_dec.v
output [4:0] ifu_exu_rd_d; // From imd of sparc_ifu_imd.v
output ifu_exu_rd_exusr_e; // From dec of sparc_ifu_dec.v
output ifu_exu_rd_ffusr_e; // From dec of sparc_ifu_dec.v
output ifu_exu_rd_ifusr_e; // From dec of sparc_ifu_dec.v
output ifu_exu_ren1_s; // From fcl of sparc_ifu_fcl.v
output ifu_exu_ren2_s; // From fcl of sparc_ifu_fcl.v
output ifu_exu_ren3_s; // From fcl of sparc_ifu_fcl.v
output ifu_exu_restore_d; // From dec of sparc_ifu_dec.v
output ifu_exu_restored_e; // From dec of sparc_ifu_dec.v
output ifu_exu_return_d; // From dec of sparc_ifu_dec.v
output [4:0] ifu_exu_rs1_s; // From fdp of sparc_ifu_fdp.v
output ifu_exu_rs1_vld_d; // From dec of sparc_ifu_dec.v
output [4:0] ifu_exu_rs2_s; // From fdp of sparc_ifu_fdp.v
output ifu_exu_rs2_vld_d; // From dec of sparc_ifu_dec.v
output [4:0] ifu_exu_rs3_s; // From fdp of sparc_ifu_fdp.v
output ifu_exu_rs3e_vld_d; // From dec of sparc_ifu_dec.v
output ifu_exu_rs3o_vld_d; // From dec of sparc_ifu_dec.v
output ifu_exu_save_d; // From dec of sparc_ifu_dec.v
output ifu_exu_saved_e; // From dec of sparc_ifu_dec.v
output ifu_exu_setcc_d; // From dec of sparc_ifu_dec.v
output ifu_exu_sethi_inst_d; // From dec of sparc_ifu_dec.v
output [2:0] ifu_exu_shiftop_d; // From dec of sparc_ifu_dec.v
output ifu_exu_tagop_d; // From dec of sparc_ifu_dec.v
output ifu_exu_tcc_e; // From dcl of sparc_ifu_dcl.v
output [1:0] ifu_exu_tid_s2; // From fcl of sparc_ifu_fcl.v
output ifu_exu_ttype_vld_m; // From fcl of sparc_ifu_fcl.v
output ifu_exu_tv_d; // From dec of sparc_ifu_dec.v
output ifu_exu_use_rsr_e_l; // From dec of sparc_ifu_dec.v
output ifu_exu_usecin_d; // From dec of sparc_ifu_dec.v
output ifu_exu_useimm_d; // From dec of sparc_ifu_dec.v
output ifu_exu_wen_d; // From dec of sparc_ifu_dec.v
output ifu_exu_wsr_inst_d; // From dec of sparc_ifu_dec.v
output [1:0] ifu_ffu_fcc_num_d; // From imd of sparc_ifu_imd.v
output ifu_ffu_fld_d; // From dec of sparc_ifu_dec.v
output ifu_ffu_fpop1_d; // From dec of sparc_ifu_dec.v
output ifu_ffu_fpop2_d; // From dec of sparc_ifu_dec.v
output [8:0] ifu_ffu_fpopcode_d; // From imd of sparc_ifu_imd.v
output [4:0] ifu_ffu_frd_d; // From imd of sparc_ifu_imd.v
output [4:0] ifu_ffu_frs1_d; // From imd of sparc_ifu_imd.v
output [4:0] ifu_ffu_frs2_d; // From imd of sparc_ifu_imd.v
output ifu_ffu_fst_d; // From dec of sparc_ifu_dec.v
output ifu_ffu_inj_frferr; // From errctl of sparc_ifu_errctl.v
output ifu_ffu_ldfsr_d; // From dec of sparc_ifu_dec.v
output ifu_ffu_ldst_size_d; // From dec of sparc_ifu_dec.v
output ifu_ffu_ldxfsr_d; // From dec of sparc_ifu_dec.v
output ifu_ffu_mvcnd_m; // From dcl of sparc_ifu_dcl.v
output ifu_ffu_quad_op_e; // From dec of sparc_ifu_dec.v
output ifu_ffu_stfsr_d; // From dec of sparc_ifu_dec.v
output ifu_ffu_visop_d; // From dec of sparc_ifu_dec.v
output ifu_lsu_alt_space_d; // From dec of sparc_ifu_dec.v
output ifu_lsu_asi_ack; // From ifqctl of sparc_ifu_ifqctl.v
output ifu_lsu_asi_rd_unc; // From errctl of sparc_ifu_errctl.v
output ifu_lsu_casa_e; // From dec of sparc_ifu_dec.v
output [2:0] ifu_lsu_destid_s; // From ifqctl of sparc_ifu_ifqctl.v
output [3:0] ifu_lsu_error_inj; // From errctl of sparc_ifu_errctl.v
output ifu_lsu_fwd_data_vld; // From errctl of sparc_ifu_errctl.v
output ifu_lsu_fwd_wr_ack; // From ifqctl of sparc_ifu_ifqctl.v
output ifu_lsu_ibuf_busy; // From ifqctl of sparc_ifu_ifqctl.v
output [7:0] ifu_lsu_imm_asi_d; // From imd of sparc_ifu_imd.v
output ifu_lsu_imm_asi_vld_d; // From imd of sparc_ifu_imd.v
output ifu_lsu_inv_clear; // From ifqctl of sparc_ifu_ifqctl.v
output ifu_lsu_ld_inst_e; // From dec of sparc_ifu_dec.v
output ifu_lsu_ldst_dbl_e; // From dec of sparc_ifu_dec.v
output ifu_lsu_ldst_fp_e; // From dec of sparc_ifu_dec.v
output [1:0] ifu_lsu_ldst_size_e; // From dec of sparc_ifu_dec.v
output ifu_lsu_ldstub_e; // From dec of sparc_ifu_dec.v
output ifu_lsu_ldxa_data_vld_w2;// From errctl of sparc_ifu_errctl.v
output [63:0] ifu_lsu_ldxa_data_w2; // From errdp of sparc_ifu_errdp.v
output ifu_lsu_ldxa_illgl_va_w2;// From ifqctl of sparc_ifu_ifqctl.v
output [1:0] ifu_lsu_ldxa_tid_w2; // From errctl of sparc_ifu_errctl.v
output ifu_lsu_memref_d; // From dec of sparc_ifu_dec.v
output [3:0] ifu_lsu_nceen; // From errctl of sparc_ifu_errctl.v
output [51:0] ifu_lsu_pcxpkt_e; // From ifqdp of sparc_ifu_ifqdp.v
output ifu_lsu_pcxreq_d; // From ifqctl of sparc_ifu_ifqctl.v
output ifu_lsu_pref_inst_e; // From dec of sparc_ifu_dec.v
output [4:0] ifu_lsu_rd_e; // From imd of sparc_ifu_imd.v
output ifu_lsu_sign_ext_e; // From dec of sparc_ifu_dec.v
output ifu_lsu_st_inst_e; // From dec of sparc_ifu_dec.v
output ifu_lsu_swap_e; // From dec of sparc_ifu_dec.v
output ifu_lsu_wsr_inst_d; // From dec of sparc_ifu_dec.v
output ifu_mmu_trap_m; // From fcl of sparc_ifu_fcl.v
output ifu_spu_inst_vld_w; // From fcl of sparc_ifu_fcl.v
output [3:0] ifu_spu_nceen; // From errctl of sparc_ifu_errctl.v
output ifu_spu_trap_ack; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_alt_space_d; // From dec of sparc_ifu_dec.v
output ifu_tlu_done_inst_d; // From dec of sparc_ifu_dec.v
output ifu_tlu_flsh_inst_e; // From dec of sparc_ifu_dec.v
output ifu_tlu_flush_m; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_hwint_m; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_icmiss_e; // From fcl of sparc_ifu_fcl.v
output [8:0] ifu_tlu_imm_asi_d; // From imd of sparc_ifu_imd.v
output ifu_tlu_immu_miss_m; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_inst_vld_m; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_itlb_done; // From fcl of sparc_ifu_fcl.v
output [3:0] ifu_tlu_l2imiss; // From ifqctl of sparc_ifu_ifqctl.v
output ifu_tlu_mb_inst_e; // From dec of sparc_ifu_dec.v
output [48:0] ifu_tlu_npc_m; // From fdp of sparc_ifu_fdp.v
output [48:0] ifu_tlu_pc_m; // From fdp of sparc_ifu_fdp.v
output ifu_tlu_pc_oor_e; // From fdp of sparc_ifu_fdp.v
output ifu_tlu_priv_violtn_m; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_retry_inst_d; // From dec of sparc_ifu_dec.v
output ifu_tlu_rsr_inst_d; // From dec of sparc_ifu_dec.v
output ifu_tlu_rstint_m; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_sftint_m; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_sir_inst_m; // From dec of sparc_ifu_dec.v
output [6:0] ifu_tlu_sraddr_d; // From imd of sparc_ifu_imd.v
output [6:0] ifu_tlu_sraddr_d_v2; // From imd of sparc_ifu_imd.v
output [1:0] ifu_tlu_thrid_d; // From fcl of sparc_ifu_fcl.v
output [1:0] ifu_tlu_thrid_e; // From fcl of sparc_ifu_fcl.v
output ifu_tlu_trap_m; // From fcl of sparc_ifu_fcl.v
output [8:0] ifu_tlu_ttype_m; // From fcl of sparc_ifu_fcl.v
output mbist_dcache_fail; // From mbist of sparc_ifu_mbist.v
output [6:0] mbist_dcache_index; // From mbist of sparc_ifu_mbist.v
output mbist_dcache_read; // From mbist of sparc_ifu_mbist.v
output [1:0] mbist_dcache_way; // From mbist of sparc_ifu_mbist.v
output mbist_dcache_word; // From mbist of sparc_ifu_mbist.v
output mbist_dcache_write; // From mbist of sparc_ifu_mbist.v
output mbist_done; // From mbist of sparc_ifu_mbist.v
output mbist_icache_fail; // From mbist of sparc_ifu_mbist.v
output sparc_sscan_so; // From sscan of sparc_ifu_sscan.v
output spc_efc_ifuse_data; // From icdhdr of cmp_sram_redhdr.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire dcl_fcl_bcregz0_e; // From dcl of sparc_ifu_dcl.v
wire dcl_fcl_bcregz1_e; // From dcl of sparc_ifu_dcl.v
wire dcl_imd_broff_sel_bcc_d_l;// From dcl of sparc_ifu_dcl.v
wire dcl_imd_broff_sel_bpcc_d_l;// From dcl of sparc_ifu_dcl.v
wire dcl_imd_broff_sel_br_d_l;// From dcl of sparc_ifu_dcl.v
wire dcl_imd_broff_sel_call_d_l;// From dcl of sparc_ifu_dcl.v
wire dcl_imd_immbr_sel_br_d; // From dcl of sparc_ifu_dcl.v
wire dcl_imd_immdata_sel_movcc_d_l;// From dcl of sparc_ifu_dcl.v
wire dcl_imd_immdata_sel_movr_d_l;// From dcl of sparc_ifu_dcl.v
wire dcl_imd_immdata_sel_sethi_d_l;// From dcl of sparc_ifu_dcl.v
wire dcl_imd_immdata_sel_simm13_d_l;// From dcl of sparc_ifu_dcl.v
wire dcl_swl_tcc_done_m; // From dcl of sparc_ifu_dcl.v
wire [2:0] dec_dcl_cctype_d; // From dec of sparc_ifu_dec.v
wire dec_fcl_rdsr_sel_pc_d; // From dec of sparc_ifu_dec.v
wire dec_fcl_rdsr_sel_thr_d; // From dec of sparc_ifu_dec.v
wire dec_imd_call_inst_d; // From dec of sparc_ifu_dec.v
wire dec_swl_allfp_d; // From dec of sparc_ifu_dec.v
wire dec_swl_br_done_d; // From dec of sparc_ifu_dec.v
wire dec_swl_div_inst_d; // From dec of sparc_ifu_dec.v
wire dec_swl_fpop_d; // From dec of sparc_ifu_dec.v
wire dec_swl_frf_lower_d; // From dec of sparc_ifu_dec.v
wire dec_swl_frf_upper_d; // From dec of sparc_ifu_dec.v
wire dec_swl_ld_inst_d; // From dec of sparc_ifu_dec.v
wire dec_swl_ll_done_d; // From dec of sparc_ifu_dec.v
wire dec_swl_mul_inst_d; // From dec of sparc_ifu_dec.v
wire dec_swl_rdsr_sel_thr_d; // From dec of sparc_ifu_dec.v
wire dec_swl_st_inst_d; // From dec of sparc_ifu_dec.v
wire dec_swl_sta_inst_e; // From dec of sparc_ifu_dec.v
wire dec_swl_std_inst_d; // From dec of sparc_ifu_dec.v
wire dec_swl_wrt_tcr_w; // From dec of sparc_ifu_dec.v
wire dec_swl_wrtfprs_w; // From dec of sparc_ifu_dec.v
wire dtu_fcl_br_inst_d; // From dec of sparc_ifu_dec.v
wire dtu_fcl_flush_sonly_e; // From dec of sparc_ifu_dec.v
wire dtu_fcl_fpdis_e; // From dec of sparc_ifu_dec.v
wire dtu_fcl_illinst_e; // From dec of sparc_ifu_dec.v
wire dtu_fcl_imask_hit_e; // From dec of sparc_ifu_dec.v
wire [3:0] dtu_fcl_nextthr_bf; // From swl of sparc_ifu_swl.v
wire dtu_fcl_ntr_s; // From swl of sparc_ifu_swl.v
wire dtu_fcl_privop_e; // From dec of sparc_ifu_dec.v
wire dtu_fcl_retract_d; // From swl of sparc_ifu_swl.v
wire dtu_fcl_rollback_g; // From swl of sparc_ifu_swl.v
wire dtu_fcl_running_s; // From swl of sparc_ifu_swl.v
wire dtu_fcl_sir_inst_e; // From dec of sparc_ifu_dec.v
wire [3:0] dtu_fcl_thr_active; // From swl of sparc_ifu_swl.v
wire [40:0] dtu_fdp_thrconf_e; // From swl of sparc_ifu_swl.v
wire dtu_ifq_kill_latest_d; // From dec of sparc_ifu_dec.v
wire dtu_inst_anull_e; // From dcl of sparc_ifu_dcl.v
wire [31:0] dtu_inst_d; // From imd of sparc_ifu_imd.v
wire dtu_reset; // From swl of sparc_ifu_swl.v
wire erb_dtu_ifeterr_d1; // From errctl of sparc_ifu_errctl.v
wire [38:0] erb_dtu_imask; // From errdp of sparc_ifu_errdp.v
wire [3:0] erb_fcl_ce_trapvec; // From errctl of sparc_ifu_errctl.v
wire [3:0] erb_fcl_ifet_uevec_d1; // From errctl of sparc_ifu_errctl.v
wire erb_fcl_itlb_ce_d1; // From errctl of sparc_ifu_errctl.v
wire [3:0] erb_fcl_spu_uetrap; // From errctl of sparc_ifu_errctl.v
wire [3:0] erb_fcl_ue_trapvec; // From errctl of sparc_ifu_errctl.v
wire erb_ifq_ifeterr_d1; // From errctl of sparc_ifu_errctl.v
wire erb_ifq_itlberr_s1; // From errctl of sparc_ifu_errctl.v
wire erb_reset; // From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_asi_thr_l; // From errctl of sparc_ifu_errctl.v
wire erc_erd_asisrc_sel_err_s_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_asisrc_sel_icd_s_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_asisrc_sel_itlb_s_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_asisrc_sel_misc_s_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_asiway_s1_l; // From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr0_sel_frf_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr0_sel_irf_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr0_sel_itlb_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr0_sel_lsu_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr1_sel_l1pa_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr1_sel_l2pa_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr1_sel_other_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr1_sel_pcd1_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr2_sel_mx0_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr2_sel_mx1_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr2_sel_old_l;// From errctl of sparc_ifu_errctl.v
wire [3:0] erc_erd_eadr2_sel_wrt_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_errasi_sel_addr_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_errasi_sel_en_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_errasi_sel_inj_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_errasi_sel_stat_l;// From errctl of sparc_ifu_errctl.v
wire [1:0] erc_erd_erren_asidata; // From errctl of sparc_ifu_errctl.v
wire [31:0] erc_erd_errinj_asidata; // From errctl of sparc_ifu_errctl.v
wire [22:0] erc_erd_errstat_asidata;// From errctl of sparc_ifu_errctl.v
wire erc_erd_ld_imask; // From errctl of sparc_ifu_errctl.v
wire erc_erd_miscasi_sel_ict_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_miscasi_sel_imask_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_miscasi_sel_other_l;// From errctl of sparc_ifu_errctl.v
wire erc_erd_pgsz_b0; // From errctl of sparc_ifu_errctl.v
wire erc_erd_pgsz_b1; // From errctl of sparc_ifu_errctl.v
wire erd_erc_fetpe_s1; // From errdp of sparc_ifu_errdp.v
wire erd_erc_nirpe_s1; // From errdp of sparc_ifu_errdp.v
wire [3:0] erd_erc_tagpe_s1; // From errdp of sparc_ifu_errdp.v
wire [1:0] erd_erc_tlbd_pe_s1; // From errdp of sparc_ifu_errdp.v
wire [1:0] erd_erc_tlbt_pe_s1; // From errdp of sparc_ifu_errdp.v
wire [2:0] erd_erc_tte_pgsz; // From errdp of sparc_ifu_errdp.v
wire fcl_dcl_regz_e; // From fcl of sparc_ifu_fcl.v
wire fcl_dec_dslot_s; // From fcl of sparc_ifu_fcl.v
wire fcl_dec_intr_vld_d; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_ely_inst_vld_d; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_hprivmode_d; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_hprivmode_w2; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_inst_vld_d; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_inst_vld_e; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_intr_vld_e; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_nuke_thr_w; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_privmode_d; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_resum_thr_w; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_rst_thr_w; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_stall_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_sync_intr_d; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_dtu_thr_f; // From fcl of sparc_ifu_fcl.v
wire fcl_dtu_tlzero_d; // From fcl of sparc_ifu_fcl.v
wire [1:0] fcl_erb_asi_tid_f; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_erb_clear_iferr; // From fcl of sparc_ifu_fcl.v
wire fcl_erb_ievld_s1; // From fcl of sparc_ifu_fcl.v
wire fcl_erb_immuevld_s1; // From fcl of sparc_ifu_fcl.v
wire fcl_erb_inst_issue_d; // From fcl of sparc_ifu_fcl.v
wire fcl_erb_inst_vld_d1; // From fcl of sparc_ifu_fcl.v
wire fcl_erb_itlbrd_data_s; // From fcl of sparc_ifu_fcl.v
wire fcl_erb_itlbrd_vld_s; // From fcl of sparc_ifu_fcl.v
wire fcl_erb_tevld_s1; // From fcl of sparc_ifu_fcl.v
wire fcl_fdp_ctxt_sel_curr_bf_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_ctxt_sel_dmp_bf_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_ctxt_sel_sw_bf_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_dmpthr_l; // From fcl of sparc_ifu_fcl.v
wire fcl_fdp_inst_sel_curr_s_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_inst_sel_nir_s_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_inst_sel_nop_s_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_inst_sel_switch_s_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_mask32b_f; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_next_ctxt_bf_l; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_next_thr_bf_l; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_nextpcs_sel_pcd_f_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_nextpcs_sel_pce_f_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_nextpcs_sel_pcf_f_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_nextpcs_sel_pcs_f_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_nirthr_s1_l; // From fcl of sparc_ifu_fcl.v
wire fcl_fdp_noswpc_sel_inc_l_bf;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_noswpc_sel_old_l_bf;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_noswpc_sel_tnpc_l_bf;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_oddwin_s; // From fcl of sparc_ifu_fcl.v
wire fcl_fdp_pcbf_sel_br_bf_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_pcbf_sel_nosw_bf_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_pcbf_sel_swpc_bf_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_pcoor_f; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_pcoor_vec_f; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_rbinst_sel_inste_s;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_rdsr_sel_pc_e_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_rdsr_sel_thr_e_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_rdsr_sel_ver_e_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_tctxt_sel_prim; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_thr_s1_l; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_thr_s2_l; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_thrtnpc_sel_npcw_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_thrtnpc_sel_old_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_thrtnpc_sel_pcf_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_thrtnpc_sel_tnpc_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_tinst_sel_curr_s_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_tinst_sel_ifq_s_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_tinst_sel_old_s_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_tinst_sel_rb_s_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_tpcbf_sel_brpc_bf_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_tpcbf_sel_old_bf_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_tpcbf_sel_pcp4_bf_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_tpcbf_sel_trap_bf_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_trrbpc_sel_err_bf_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_trrbpc_sel_pcs_bf_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_trrbpc_sel_rb_bf_l;// From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_fdp_trrbpc_sel_trap_bf_l;// From fcl of sparc_ifu_fcl.v
wire fcl_fdp_usenir_sel_nir_s1;// From fcl of sparc_ifu_fcl.v
wire fcl_icd_index_sel_ifq_bf;// From fcl of sparc_ifu_fcl.v
wire fcl_icd_rdreq_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_icd_wrreq_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_ict_wrreq_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_icv_rdreq_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_icv_wrreq_bf; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_ifq_canthr; // From fcl of sparc_ifu_fcl.v
wire fcl_ifq_grant_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_ifq_icache_en_s_l; // From fcl of sparc_ifu_fcl.v
wire fcl_ifq_icmiss_s1; // From fcl of sparc_ifu_fcl.v
wire fcl_ifq_rdreq_s1; // From fcl of sparc_ifu_fcl.v
wire [1:0] fcl_ifq_thr_s1; // From fcl of sparc_ifu_fcl.v
wire fcl_imd_oddwin_d; // From fcl of sparc_ifu_fcl.v
wire fcl_swl_flush_w; // From fcl of sparc_ifu_fcl.v
wire fcl_swl_flush_wake_w; // From fcl of sparc_ifu_fcl.v
wire [3:0] fcl_swl_int_activate_i3;// From fcl of sparc_ifu_fcl.v
wire fcl_swl_swcvld_s; // From fcl of sparc_ifu_fcl.v
wire fcl_swl_swout_f; // From fcl of sparc_ifu_fcl.v
wire [31:0] fdp_dtu_inst_s; // From fdp of sparc_ifu_fdp.v
wire [47:0] fdp_erb_pc_f; // From fdp of sparc_ifu_fdp.v
wire fdp_fcl_ibit_s; // From fdp of sparc_ifu_fdp.v
wire [5:2] fdp_fcl_op3_s; // From fdp of sparc_ifu_fdp.v
wire [1:0] fdp_fcl_op_s; // From fdp of sparc_ifu_fdp.v
wire fdp_fcl_pc_oor_e; // From fdp of sparc_ifu_fdp.v
wire [3:0] fdp_fcl_pc_oor_vec_f; // From fdp of sparc_ifu_fdp.v
wire fdp_fcl_swc_s2; // From fdp of sparc_ifu_fdp.v
wire [11:5] fdp_icv_index_bf; // From fdp of sparc_ifu_fdp.v
wire [1:0] fuse_icd_repair_en; // From icdhdr of cmp_sram_redhdr.v
wire [7:0] fuse_icd_repair_value; // From icdhdr of cmp_sram_redhdr.v
wire [5:0] fuse_icd_rid; // From icdhdr of cmp_sram_redhdr.v
wire fuse_icd_wren; // From icdhdr of cmp_sram_redhdr.v
wire [1:0] icd_fuse_repair_en; // From icd of bw_r_icd.v
wire [7:0] icd_fuse_repair_value; // From icd of bw_r_icd.v
wire [135:0] icd_wsel_fetdata_s1; // From icd of bw_r_icd.v
wire [135:0] icd_wsel_topdata_s1; // From icd of bw_r_icd.v
wire [3:0] icv_itlb_valid_f; // From icv of bw_r_rf16x32.v
wire ifc_ifd_addr_sel_asi_i2_l;// From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_addr_sel_bist_i2_l;// From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_addr_sel_fill_i2_l;// From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_addr_sel_old_i2_l;// From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_errinv_e; // From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_filladdr4_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire [3:0] ifc_ifd_finst_sel_l; // From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_idx_sel_fwd_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_ifqbyp_en_l; // From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_ifqbyp_sel_asi_l;// From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_ifqbyp_sel_fwd_l;// From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_ifqbyp_sel_inq_l;// From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_ifqbyp_sel_lsu_l;// From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_ld_inq_i1; // From ifqctl of sparc_ifu_ifqctl.v
wire [3:0] ifc_ifd_ldmil_sel_new; // From ifqctl of sparc_ifu_ifqctl.v
wire [3:0] ifc_ifd_milfill_sel_i2_l;// From ifqctl of sparc_ifu_ifqctl.v
wire [3:0] ifc_ifd_milreq_sel_d_l; // From ifqctl of sparc_ifu_ifqctl.v
wire [4:2] ifc_ifd_pcxline_adj_d; // From ifqctl of sparc_ifu_ifqctl.v
wire [1:0] ifc_ifd_repway_s; // From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_reqvalid_e; // From ifqctl of sparc_ifu_ifqctl.v
wire [1:0] ifc_ifd_thrid_e; // From ifqctl of sparc_ifu_ifqctl.v
wire ifc_ifd_uncached_e; // From ifqctl of sparc_ifu_ifqctl.v
wire ifc_inv_asireq_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire ifc_inv_ifqadv_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire ifd_ifc_4bpkt_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire ifd_ifc_asi_vachklo_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [3:2] ifd_ifc_asiaddr_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire ifd_ifc_cpxce_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire ifd_ifc_cpxms_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire ifd_ifc_cpxnc_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [`CPX_RQ_SIZE:0]ifd_ifc_cpxreq_i1; // From ifqdp of sparc_ifu_ifqdp.v
wire [3:0] ifd_ifc_cpxreq_nxt; // From ifqdp of sparc_ifu_ifqdp.v
wire [1:0] ifd_ifc_cpxthr_nxt; // From ifqdp of sparc_ifu_ifqdp.v
wire ifd_ifc_cpxue_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire ifd_ifc_cpxvld_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [2:0] ifd_ifc_destid0; // From ifqdp of sparc_ifu_ifqdp.v
wire [2:0] ifd_ifc_destid1; // From ifqdp of sparc_ifu_ifqdp.v
wire [2:0] ifd_ifc_destid2; // From ifqdp of sparc_ifu_ifqdp.v
wire [2:0] ifd_ifc_destid3; // From ifqdp of sparc_ifu_ifqdp.v
wire ifd_ifc_fwd2ic_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [1:0] ifd_ifc_instoffset0; // From ifqdp of sparc_ifu_ifqdp.v
wire [1:0] ifd_ifc_instoffset1; // From ifqdp of sparc_ifu_ifqdp.v
wire [1:0] ifd_ifc_instoffset2; // From ifqdp of sparc_ifu_ifqdp.v
wire [1:0] ifd_ifc_instoffset3; // From ifqdp of sparc_ifu_ifqdp.v
wire ifd_ifc_iobpkt_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [3:0] ifd_ifc_miladdr4_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [3:0] ifd_ifc_milhit_s; // From ifqdp of sparc_ifu_ifqdp.v
wire [2:0] ifd_ifc_newdestid_s; // From ifqdp of sparc_ifu_ifqdp.v
wire [4:2] ifd_ifc_pcxline_d; // From ifqdp of sparc_ifu_ifqdp.v
wire [`CPX_WIDTH-1:0]ifd_inv_ifqop_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [1:0] ifd_inv_wrway_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [3:0] ifq_dtu_pred_rdy; // From ifqctl of sparc_ifu_ifqctl.v
wire [3:0] ifq_dtu_thrrdy; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_asi_erraddr_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_asi_erren_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_asi_errinj_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_asi_errstat_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_asi_imask_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire [47:0] ifq_erb_asidata_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [1:0] ifq_erb_asiway_f; // From invctl of sparc_ifu_invctl.v
wire ifq_erb_asiwr_i2; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_ce_rep; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_fwdrd_bf; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_ifet_ce; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_io_ue; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_l2_ue; // From ifqctl of sparc_ifu_ifqctl.v
wire [1:0] ifq_erb_l2err_tid; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_rdinst_f; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_rdtag_f; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_erb_ue_rep; // From ifqctl of sparc_ifu_ifqctl.v
wire [`IC_IDX_HI:4] ifq_erb_wrindex_f; // From ifqdp of sparc_ifu_ifqdp.v
wire [1:0] ifq_fcl_asi_tid_bf; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_fcl_asird_bf; // From ifqctl of sparc_ifu_ifqctl.v
wire [3:0] ifq_fcl_fill_thr; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_fcl_flush_sonly_e; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_fcl_icd_wrreq_bf; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_fcl_ictv_wrreq_bf; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_fcl_invreq_bf; // From invctl of sparc_ifu_invctl.v
wire ifq_fcl_rdreq_bf; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_fcl_stallreq; // From ifqctl of sparc_ifu_ifqctl.v
wire ifq_fcl_wrreq_bf; // From ifqctl of sparc_ifu_ifqctl.v
wire [32:0] ifq_fdp_fill_inst; // From ifqdp of sparc_ifu_ifqdp.v
wire ifq_icd_data_sel_bist_i2;// From ifqctl of sparc_ifu_ifqctl.v
wire ifq_icd_data_sel_fill_i2;// From ifqctl of sparc_ifu_ifqctl.v
wire ifq_icd_data_sel_old_i2;// From ifqctl of sparc_ifu_ifqctl.v
wire [`IC_IDX_HI:2] ifq_icd_index_bf; // From ifqdp of sparc_ifu_ifqdp.v
wire [3:0] ifq_icd_worden_bf; // From ifqctl of sparc_ifu_ifqctl.v
wire [135:0] ifq_icd_wrdata_i2; // From ifqdp of sparc_ifu_ifqdp.v
wire [1:0] ifq_icd_wrway_bf; // From ifqdp of sparc_ifu_ifqdp.v
wire [3:0] ifq_ict_dec_wrway_bf; // From invctl of sparc_ifu_invctl.v
wire ifq_icv_wrdata_bf; // From ifqctl of sparc_ifu_ifqctl.v
wire [15:0] ifq_icv_wren_bf; // From invctl of sparc_ifu_invctl.v
wire [`IC_IDX_HI:5] ifq_icv_wrindex_bf; // From invctl of sparc_ifu_invctl.v
wire ifq_swl_stallreq; // From ifqctl of sparc_ifu_ifqctl.v
wire imd_dcl_abit_d; // From imd of sparc_ifu_imd.v
wire [3:0] imd_dcl_brcond_d; // From imd of sparc_ifu_imd.v
wire [7:0] imd_dcl_mvcond_d; // From imd of sparc_ifu_imd.v
wire inv_ifc_inv_pending; // From invctl of sparc_ifu_invctl.v
wire [7:0] mbist_icache_index; // From mbist of sparc_ifu_mbist.v
wire mbist_icache_read; // From mbist of sparc_ifu_mbist.v
wire [1:0] mbist_icache_way; // From mbist of sparc_ifu_mbist.v
wire mbist_icache_word; // From mbist of sparc_ifu_mbist.v
wire mbist_icache_write; // From mbist of sparc_ifu_mbist.v
wire mbist_ifq_run_bist; // From mbist of sparc_ifu_mbist.v
wire [3:0] swl_dcl_thr_d; // From swl of sparc_ifu_swl.v
wire [3:0] swl_dcl_thr_w2; // From swl of sparc_ifu_swl.v
wire swl_dec_divbusy_e; // From swl of sparc_ifu_swl.v
wire swl_dec_fp_enable_d; // From swl of sparc_ifu_swl.v
wire swl_dec_fpbusy_e; // From swl of sparc_ifu_swl.v
wire swl_dec_ibe_e; // From swl of sparc_ifu_swl.v
wire swl_dec_mulbusy_e; // From swl of sparc_ifu_swl.v
wire [10:0] swl_sscan_thrstate; // From swl of sparc_ifu_swl.v
wire [33:0] wsel_fdp_fetdata_s1; // From wseldp of sparc_ifu_wseldp.v
wire [33:0] wsel_fdp_topdata_s1; // From wseldp of sparc_ifu_wseldp.v
wire wsr_fixed_inst_w; // From dec of sparc_ifu_dec.v
// End of automatics
// tlb not auto instantiated
wire fcl_itlb_invall_f_l; // From fcl of sparc_ifu_fcl.v
wire itlb_fcl_imiss_s_l; // To fcl of sparc_ifu_fcl.v
wire itlb_fcl_tlbmiss_f_l; // To fcl of sparc_ifu_fcl.v
wire [3:0] itlb_wsel_waysel_s1; // To icd of sparc_ifu_icd.v
wire [39:10] itlb_ifq_paddr_s; // To ifqdp of sparc_ifu_ifqdp.v, ...
wire [42:0] itlb_rd_tte_data; // To errdp of sparc_ifu_errdp.v
wire [58:0] itlb_rd_tte_tag; // To errdp of sparc_ifu_errdp.v
wire fcl_itlb_addr_mask_l; // From fcl of sparc_ifu_fcl.v
wire fcl_itlb_cam_bypass_bf; // From fcl of sparc_ifu_fcl.v
wire [2:0] fcl_itlb_cam_pid_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_itlb_cam_real_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_itlb_cam_vld_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_itlb_data_rd_vld_bf;// From fcl of sparc_ifu_fcl.v
wire fcl_itlb_dmp_vld_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_itlb_dmp_all_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_itlb_tag_rd_vld_bf; // From fcl of sparc_ifu_fcl.v
wire fcl_itlb_wr_vld_bf; // From fcl of sparc_ifu_fcl.v
wire [47:2] fdp_icd_vaddr_bf; // From fdp of sparc_ifu_fdp.v
wire [12:0] fdp_itlb_ctxt_bf; // From fdp of sparc_ifu_fdp.v
wire [32:0] ict_itlb_tag0_f; // From ict of bw_r_idct.v
wire [32:0] ict_itlb_tag1_f; // From ict of bw_r_idct.v
wire [32:0] ict_itlb_tag2_f; // From ict of bw_r_idct.v
wire [32:0] ict_itlb_tag3_f; // From ict of bw_r_idct.v
// sscan rename
wire [3:0] ifq_sscan_data; // From ifqctl of sparc_ifu_ifqctl.v
// bist rename
wire [7:0] mbist_icache_wdata;
// rptr bus for bist read of icache
wire [67:0] wsel_mbist_icache_data;
// bus width mismatch
wire [`IC_TAG_SZ:0] ifq_ict_wrtag_f; // From ifqdp of sparc_ifu_ifqdp.v
// scan wires
wire scan0_1;
wire scan0_2;
wire scan0_3;
wire scan0_4;
wire scan0_5;
wire scan0_6;
wire scan0_7;
wire scan0_8;
wire scan0_9;
wire scan0_10;
wire scan0_11;
wire scan0_12;
wire scan0_13;
wire short_scan1_1;
wire short_scan0_1;
wire short_scan0_2;
//----------------------------------------------------------------------
// Code start here
//----------------------------------------------------------------------
// sparc_ifu_dtu dtu(
// .thr_config_in_w (exu_tlu_wsr_data_w[2:0]),
// /*AUTOINST*/);
// decode
sparc_ifu_dec dec(
.so (scan0_1),
.si (si0),
/*AUTOINST*/
// Outputs
.ifu_exu_aluop_d (ifu_exu_aluop_d[2:0]),
.ifu_exu_invert_d (ifu_exu_invert_d),
.ifu_exu_useimm_d (ifu_exu_useimm_d),
.ifu_exu_usecin_d (ifu_exu_usecin_d),
.ifu_exu_enshift_d (ifu_exu_enshift_d),
.ifu_exu_tagop_d (ifu_exu_tagop_d),
.ifu_exu_tv_d (ifu_exu_tv_d),
.ifu_exu_muls_d (ifu_exu_muls_d),
.ifu_exu_ialign_d (ifu_exu_ialign_d),
.ifu_exu_range_check_jlret_d(ifu_exu_range_check_jlret_d),
.ifu_exu_range_check_other_d(ifu_exu_range_check_other_d),
.ifu_exu_shiftop_d (ifu_exu_shiftop_d[2:0]),
.ifu_exu_muldivop_d(ifu_exu_muldivop_d[4:0]),
.ifu_exu_wen_d (ifu_exu_wen_d),
.ifu_exu_setcc_d (ifu_exu_setcc_d),
.ifu_exu_rd_ifusr_e(ifu_exu_rd_ifusr_e),
.ifu_exu_rd_exusr_e(ifu_exu_rd_exusr_e),
.ifu_exu_rd_ffusr_e(ifu_exu_rd_ffusr_e),
.ifu_exu_rs1_vld_d (ifu_exu_rs1_vld_d),
.ifu_exu_rs2_vld_d (ifu_exu_rs2_vld_d),
.ifu_exu_rs3e_vld_d(ifu_exu_rs3e_vld_d),
.ifu_exu_rs3o_vld_d(ifu_exu_rs3o_vld_d),
.ifu_exu_use_rsr_e_l(ifu_exu_use_rsr_e_l),
.ifu_exu_save_d (ifu_exu_save_d),
.ifu_exu_restore_d (ifu_exu_restore_d),
.ifu_exu_return_d (ifu_exu_return_d),
.ifu_exu_flushw_e (ifu_exu_flushw_e),
.ifu_exu_saved_e (ifu_exu_saved_e),
.ifu_exu_restored_e(ifu_exu_restored_e),
.ifu_tlu_rsr_inst_d(ifu_tlu_rsr_inst_d),
.ifu_lsu_wsr_inst_d(ifu_lsu_wsr_inst_d),
.ifu_exu_wsr_inst_d(ifu_exu_wsr_inst_d),
.ifu_tlu_done_inst_d(ifu_tlu_done_inst_d),
.ifu_tlu_retry_inst_d(ifu_tlu_retry_inst_d),
.ifu_lsu_ld_inst_e (ifu_lsu_ld_inst_e),
.ifu_lsu_st_inst_e (ifu_lsu_st_inst_e),
.ifu_lsu_pref_inst_e(ifu_lsu_pref_inst_e),
.ifu_lsu_alt_space_e(ifu_lsu_alt_space_e),
.ifu_lsu_alt_space_d(ifu_lsu_alt_space_d),
.ifu_tlu_alt_space_d(ifu_tlu_alt_space_d),
.ifu_lsu_memref_d (ifu_lsu_memref_d),
.ifu_lsu_sign_ext_e(ifu_lsu_sign_ext_e),
.ifu_lsu_ldstub_e (ifu_lsu_ldstub_e),
.ifu_lsu_casa_e (ifu_lsu_casa_e),
.ifu_exu_casa_d (ifu_exu_casa_d),
.ifu_lsu_swap_e (ifu_lsu_swap_e),
.ifu_tlu_mb_inst_e (ifu_tlu_mb_inst_e),
.ifu_tlu_sir_inst_m(ifu_tlu_sir_inst_m),
.ifu_tlu_flsh_inst_e(ifu_tlu_flsh_inst_e),
.ifu_lsu_ldst_dbl_e(ifu_lsu_ldst_dbl_e),
.ifu_lsu_ldst_fp_e (ifu_lsu_ldst_fp_e),
.ifu_lsu_ldst_size_e(ifu_lsu_ldst_size_e[1:0]),
.ifu_ffu_fpop1_d (ifu_ffu_fpop1_d),
.ifu_ffu_visop_d (ifu_ffu_visop_d),
.ifu_ffu_fpop2_d (ifu_ffu_fpop2_d),
.ifu_ffu_fld_d (ifu_ffu_fld_d),
.ifu_ffu_fst_d (ifu_ffu_fst_d),
.ifu_ffu_ldst_size_d(ifu_ffu_ldst_size_d),
.ifu_ffu_ldfsr_d (ifu_ffu_ldfsr_d),
.ifu_ffu_ldxfsr_d (ifu_ffu_ldxfsr_d),
.ifu_ffu_stfsr_d (ifu_ffu_stfsr_d),
.ifu_ffu_quad_op_e (ifu_ffu_quad_op_e),
.dec_fcl_rdsr_sel_pc_d(dec_fcl_rdsr_sel_pc_d),
.dec_fcl_rdsr_sel_thr_d(dec_fcl_rdsr_sel_thr_d),
.dec_imd_call_inst_d(dec_imd_call_inst_d),
.dtu_fcl_flush_sonly_e(dtu_fcl_flush_sonly_e),
.dtu_fcl_illinst_e (dtu_fcl_illinst_e),
.dtu_fcl_fpdis_e (dtu_fcl_fpdis_e),
.dtu_fcl_privop_e (dtu_fcl_privop_e),
.dtu_fcl_imask_hit_e(dtu_fcl_imask_hit_e),
.dtu_fcl_br_inst_d (dtu_fcl_br_inst_d),
.dtu_fcl_sir_inst_e(dtu_fcl_sir_inst_e),
.dtu_ifq_kill_latest_d(dtu_ifq_kill_latest_d),
.dec_swl_wrt_tcr_w (dec_swl_wrt_tcr_w),
.dec_swl_wrtfprs_w (dec_swl_wrtfprs_w),
.dec_swl_ll_done_d (dec_swl_ll_done_d),
.dec_swl_br_done_d (dec_swl_br_done_d),
.dec_swl_rdsr_sel_thr_d(dec_swl_rdsr_sel_thr_d),
.dec_swl_ld_inst_d (dec_swl_ld_inst_d),
.dec_swl_sta_inst_e(dec_swl_sta_inst_e),
.dec_swl_std_inst_d(dec_swl_std_inst_d),
.dec_swl_st_inst_d (dec_swl_st_inst_d),
.dec_swl_fpop_d (dec_swl_fpop_d),
.dec_swl_allfp_d (dec_swl_allfp_d),
.dec_swl_frf_upper_d(dec_swl_frf_upper_d),
.dec_swl_frf_lower_d(dec_swl_frf_lower_d),
.dec_swl_div_inst_d(dec_swl_div_inst_d),
.dec_swl_mul_inst_d(dec_swl_mul_inst_d),
.wsr_fixed_inst_w (wsr_fixed_inst_w),
.ifu_exu_sethi_inst_d(ifu_exu_sethi_inst_d),
.dec_dcl_cctype_d (dec_dcl_cctype_d[2:0]),
// Inputs
.rclk (rclk),
.se (se),
.dtu_inst_d (dtu_inst_d[31:0]),
.erb_dtu_imask (erb_dtu_imask[38:0]),
.swl_dec_ibe_e (swl_dec_ibe_e),
.dtu_inst_anull_e (dtu_inst_anull_e),
.lsu_ifu_ldsta_internal_e(lsu_ifu_ldsta_internal_e),
.fcl_dtu_tlzero_d (fcl_dtu_tlzero_d),
.fcl_dtu_privmode_d(fcl_dtu_privmode_d),
.fcl_dtu_hprivmode_d(fcl_dtu_hprivmode_d),
.fcl_dtu_inst_vld_d(fcl_dtu_inst_vld_d),
.fcl_dtu_ely_inst_vld_d(fcl_dtu_ely_inst_vld_d),
.fcl_dec_intr_vld_d(fcl_dec_intr_vld_d),
.fcl_dtu_inst_vld_e(fcl_dtu_inst_vld_e),
.fcl_dec_dslot_s (fcl_dec_dslot_s),
.swl_dec_mulbusy_e (swl_dec_mulbusy_e),
.swl_dec_fpbusy_e (swl_dec_fpbusy_e),
.swl_dec_divbusy_e (swl_dec_divbusy_e),
.swl_dec_fp_enable_d(swl_dec_fp_enable_d));
// Pipeline Control and Switch Logic
sparc_ifu_swl swl(
.so (scan0_2),
.si (scan0_1),
.thr_config_in_m (exu_tlu_wsr_data_m[2:0]),
.extra_longlat_compl(4'b0),
/*AUTOINST*/
// Outputs
.swl_sscan_thrstate(swl_sscan_thrstate[10:0]),
.dtu_reset (dtu_reset),
.swl_dec_mulbusy_e (swl_dec_mulbusy_e),
.swl_dec_divbusy_e (swl_dec_divbusy_e),
.swl_dec_fpbusy_e (swl_dec_fpbusy_e),
.swl_dec_fp_enable_d(swl_dec_fp_enable_d),
.swl_dec_ibe_e (swl_dec_ibe_e),
.dtu_fcl_ntr_s (dtu_fcl_ntr_s),
.dtu_fcl_running_s (dtu_fcl_running_s),
.dtu_fcl_rollback_g(dtu_fcl_rollback_g),
.dtu_fcl_retract_d (dtu_fcl_retract_d),
.dtu_fcl_thr_active(dtu_fcl_thr_active[3:0]),
.dtu_fcl_nextthr_bf(dtu_fcl_nextthr_bf[3:0]),
.swl_dcl_thr_d (swl_dcl_thr_d[3:0]),
.swl_dcl_thr_w2 (swl_dcl_thr_w2[3:0]),
.dtu_fdp_thrconf_e (dtu_fdp_thrconf_e[40:0]),
// Inputs
.rclk (rclk),
.se (se),
.gdbginit_l (gdbginit_l),
.arst_l (arst_l),
.grst_l (grst_l),
.ctu_sscan_tid (ctu_sscan_tid[3:0]),
.ifq_dtu_thrrdy (ifq_dtu_thrrdy[3:0]),
.ifq_dtu_pred_rdy (ifq_dtu_pred_rdy[3:0]),
.ifu_tlu_inst_vld_w(ifu_tlu_inst_vld_w),
.ifu_tlu_ttype_vld_m(ifu_tlu_ttype_vld_m),
.fcl_dtu_hprivmode_d(fcl_dtu_hprivmode_d),
.fcl_dtu_hprivmode_w2(fcl_dtu_hprivmode_w2),
.tlu_ifu_flush_pipe_w(tlu_ifu_flush_pipe_w),
.fcl_swl_flush_w (fcl_swl_flush_w),
.fcl_dtu_sync_intr_d(fcl_dtu_sync_intr_d),
.fcl_dtu_nuke_thr_w(fcl_dtu_nuke_thr_w),
.fcl_dtu_rst_thr_w (fcl_dtu_rst_thr_w),
.fcl_dtu_resum_thr_w(fcl_dtu_resum_thr_w),
.fcl_dtu_thr_f (fcl_dtu_thr_f[3:0]),
.tlu_hpstate_ibe (tlu_hpstate_ibe[3:0]),
.lsu_ifu_ldsta_internal_e(lsu_ifu_ldsta_internal_e),
.tlu_ifu_trappc_vld_w1(tlu_ifu_trappc_vld_w1),
.dec_swl_ll_done_d (dec_swl_ll_done_d),
.dec_swl_br_done_d (dec_swl_br_done_d),
.dec_swl_rdsr_sel_thr_d(dec_swl_rdsr_sel_thr_d),
.dec_swl_std_inst_d(dec_swl_std_inst_d),
.dec_swl_sta_inst_e(dec_swl_sta_inst_e),
.wsr_fixed_inst_w (wsr_fixed_inst_w),
.dec_swl_ld_inst_d (dec_swl_ld_inst_d),
.dec_swl_mul_inst_d(dec_swl_mul_inst_d),
.dec_swl_div_inst_d(dec_swl_div_inst_d),
.dec_swl_fpop_d (dec_swl_fpop_d),
.dec_swl_allfp_d (dec_swl_allfp_d),
.dec_swl_frf_upper_d(dec_swl_frf_upper_d),
.dec_swl_frf_lower_d(dec_swl_frf_lower_d),
.dec_swl_wrtfprs_w (dec_swl_wrtfprs_w),
.dcl_swl_tcc_done_m(dcl_swl_tcc_done_m),
.exu_ifu_longop_done_g(exu_ifu_longop_done_g[3:0]),
.exu_ifu_spill_e (exu_ifu_spill_e),
.lsu_ifu_ldst_cmplt(lsu_ifu_ldst_cmplt[3:0]),
.lsu_ifu_dc_parity_error_w2(lsu_ifu_dc_parity_error_w2),
.lsu_ifu_stbcnt0 (lsu_ifu_stbcnt0[3:0]),
.lsu_ifu_stbcnt1 (lsu_ifu_stbcnt1[3:0]),
.lsu_ifu_stbcnt2 (lsu_ifu_stbcnt2[3:0]),
.lsu_ifu_stbcnt3 (lsu_ifu_stbcnt3[3:0]),
.lsu_ifu_quad_asi_e(lsu_ifu_quad_asi_e),
.ffu_ifu_fpop_done_w2(ffu_ifu_fpop_done_w2),
.ffu_ifu_tid_w2 (ffu_ifu_tid_w2[1:0]),
.ffu_ifu_fst_ce_w (ffu_ifu_fst_ce_w),
.tlu_ifu_trap_tid_w1(tlu_ifu_trap_tid_w1[1:0]),
.tlu_ifu_pstate_pef(tlu_ifu_pstate_pef[3:0]),
.lsu_ifu_ldst_miss_g(lsu_ifu_ldst_miss_g),
.fcl_swl_int_activate_i3(fcl_swl_int_activate_i3[3:0]),
.fcl_swl_flush_wake_w(fcl_swl_flush_wake_w),
.ifq_swl_stallreq (ifq_swl_stallreq),
.fcl_dtu_stall_bf (fcl_dtu_stall_bf),
.fcl_swl_swout_f (fcl_swl_swout_f),
.fcl_swl_swcvld_s (fcl_swl_swcvld_s),
.fdp_fcl_swc_s2 (fdp_fcl_swc_s2),
.fcl_ifq_icmiss_s1 (fcl_ifq_icmiss_s1),
.fcl_dtu_inst_vld_e(fcl_dtu_inst_vld_e),
.fcl_dtu_intr_vld_e(fcl_dtu_intr_vld_e),
.fcl_dtu_inst_vld_d(fcl_dtu_inst_vld_d),
.erb_dtu_ifeterr_d1(erb_dtu_ifeterr_d1),
.dtu_inst_anull_e (dtu_inst_anull_e),
.const_cpuid (const_cpuid[3:0]),
.dec_swl_wrt_tcr_w (dec_swl_wrt_tcr_w),
.dec_swl_st_inst_d (dec_swl_st_inst_d));
// Branch Logic
sparc_ifu_dcl dcl(
.so (scan0_3),
.si (scan0_2),
.dtu_dcl_opf2_d (dtu_inst_d[7]),
.fdp_dcl_op_s (fdp_dtu_inst_s[31:30]),
.fdp_dcl_op3_s (fdp_dtu_inst_s[24:19]),
/*AUTOINST*/
// Outputs
.ifu_exu_kill_e (ifu_exu_kill_e),
.ifu_exu_dontmv_regz0_e(ifu_exu_dontmv_regz0_e),
.ifu_exu_dontmv_regz1_e(ifu_exu_dontmv_regz1_e),
.ifu_exu_tcc_e (ifu_exu_tcc_e),
.ifu_exu_dbrinst_d(ifu_exu_dbrinst_d),
.ifu_ffu_mvcnd_m (ifu_ffu_mvcnd_m),
.dcl_fcl_bcregz0_e(dcl_fcl_bcregz0_e),
.dcl_fcl_bcregz1_e(dcl_fcl_bcregz1_e),
.dtu_inst_anull_e (dtu_inst_anull_e),
.dcl_swl_tcc_done_m(dcl_swl_tcc_done_m),
.dcl_imd_immdata_sel_simm13_d_l(dcl_imd_immdata_sel_simm13_d_l),
.dcl_imd_immdata_sel_movcc_d_l(dcl_imd_immdata_sel_movcc_d_l),
.dcl_imd_immdata_sel_sethi_d_l(dcl_imd_immdata_sel_sethi_d_l),
.dcl_imd_immdata_sel_movr_d_l(dcl_imd_immdata_sel_movr_d_l),
.dcl_imd_broff_sel_call_d_l(dcl_imd_broff_sel_call_d_l),
.dcl_imd_broff_sel_br_d_l(dcl_imd_broff_sel_br_d_l),
.dcl_imd_broff_sel_bcc_d_l(dcl_imd_broff_sel_bcc_d_l),
.dcl_imd_broff_sel_bpcc_d_l(dcl_imd_broff_sel_bpcc_d_l),
.dcl_imd_immbr_sel_br_d(dcl_imd_immbr_sel_br_d),
// Inputs
.rclk (rclk),
.se (se),
.dtu_reset (dtu_reset),
.exu_ifu_cc_d (exu_ifu_cc_d[7:0]),
.fcl_dcl_regz_e (fcl_dcl_regz_e),
.exu_ifu_regn_e (exu_ifu_regn_e),
.ffu_ifu_cc_w2 (ffu_ifu_cc_w2[7:0]),
.ffu_ifu_cc_vld_w2(ffu_ifu_cc_vld_w2[3:0]),
.tlu_ifu_flush_pipe_w(tlu_ifu_flush_pipe_w),
.swl_dcl_thr_d (swl_dcl_thr_d[3:0]),
.swl_dcl_thr_w2 (swl_dcl_thr_w2[3:0]),
.imd_dcl_brcond_d (imd_dcl_brcond_d[3:0]),
.imd_dcl_mvcond_d (imd_dcl_mvcond_d[7:0]),
.imd_dcl_abit_d (imd_dcl_abit_d),
.dec_dcl_cctype_d (dec_dcl_cctype_d[2:0]),
.fcl_dtu_inst_vld_e(fcl_dtu_inst_vld_e),
.fcl_dtu_intr_vld_e(fcl_dtu_intr_vld_e),
.ifu_tlu_flush_w (ifu_tlu_flush_w));
/* sparc_ifu_imd AUTO_TEMPLATE(
.dcl_imd_call_inst_d (dec_imd_call_inst_d),
);
*/
sparc_ifu_imd imd(
.so (scan0_4),
.si (scan0_3),
/*AUTOINST*/
// Outputs
.ifu_exu_imm_data_d(ifu_exu_imm_data_d[31:0]),
.dtu_inst_d (dtu_inst_d[31:0]),
.ifu_exu_rd_d (ifu_exu_rd_d[4:0]),
.ifu_lsu_rd_e (ifu_lsu_rd_e[4:0]),
.ifu_lsu_imm_asi_d(ifu_lsu_imm_asi_d[7:0]),
.ifu_tlu_imm_asi_d(ifu_tlu_imm_asi_d[8:0]),
.ifu_lsu_imm_asi_vld_d(ifu_lsu_imm_asi_vld_d),
.ifu_tlu_sraddr_d (ifu_tlu_sraddr_d[6:0]),
.ifu_tlu_sraddr_d_v2(ifu_tlu_sraddr_d_v2[6:0]),
.imd_dcl_brcond_d (imd_dcl_brcond_d[3:0]),
.imd_dcl_mvcond_d (imd_dcl_mvcond_d[7:0]),
.imd_dcl_abit_d (imd_dcl_abit_d),
.ifu_ffu_frs1_d (ifu_ffu_frs1_d[4:0]),
.ifu_ffu_frs2_d (ifu_ffu_frs2_d[4:0]),
.ifu_ffu_frd_d (ifu_ffu_frd_d[4:0]),
.ifu_ffu_fpopcode_d(ifu_ffu_fpopcode_d[8:0]),
.ifu_ffu_fcc_num_d(ifu_ffu_fcc_num_d[1:0]),
// Inputs
.rclk (rclk),
.se (se),
.fdp_dtu_inst_s (fdp_dtu_inst_s[31:0]),
.fcl_imd_oddwin_d (fcl_imd_oddwin_d),
.dcl_imd_immdata_sel_simm13_d_l(dcl_imd_immdata_sel_simm13_d_l),
.dcl_imd_immdata_sel_movcc_d_l(dcl_imd_immdata_sel_movcc_d_l),
.dcl_imd_immdata_sel_sethi_d_l(dcl_imd_immdata_sel_sethi_d_l),
.dcl_imd_immdata_sel_movr_d_l(dcl_imd_immdata_sel_movr_d_l),
.dcl_imd_broff_sel_call_d_l(dcl_imd_broff_sel_call_d_l),
.dcl_imd_broff_sel_br_d_l(dcl_imd_broff_sel_br_d_l),
.dcl_imd_broff_sel_bcc_d_l(dcl_imd_broff_sel_bcc_d_l),
.dcl_imd_broff_sel_bpcc_d_l(dcl_imd_broff_sel_bpcc_d_l),
.dcl_imd_immbr_sel_br_d(dcl_imd_immbr_sel_br_d),
.dcl_imd_call_inst_d(dec_imd_call_inst_d)); // Templated
sparc_ifu_fdp fdp(
.so (scan0_5),
.si (scan0_4),
.fdp_itlb_ctxt_bf (fdp_itlb_ctxt_bf[12:0]),
.fdp_icd_vaddr_bf (fdp_icd_vaddr_bf[47:2]),
.icd_fdp_fetdata_s1(wsel_fdp_fetdata_s1[32:0]),
.icd_fdp_topdata_s1(wsel_fdp_topdata_s1[32:0]),
// eco 5362
.fcl_fdp_addr_mask_d(ifu_exu_addr_mask_d),
/*AUTOINST*/
// Outputs
.fdp_icv_index_bf (fdp_icv_index_bf[11:5]),
.fdp_erb_pc_f (fdp_erb_pc_f[47:0]),
.fdp_dtu_inst_s (fdp_dtu_inst_s[31:0]),
.ifu_exu_pc_d (ifu_exu_pc_d[47:0]),
.ifu_exu_rs1_s (ifu_exu_rs1_s[4:0]),
.ifu_exu_rs2_s (ifu_exu_rs2_s[4:0]),
.ifu_exu_rs3_s (ifu_exu_rs3_s[4:0]),
.ifu_tlu_pc_m (ifu_tlu_pc_m[48:0]),
.ifu_tlu_npc_m (ifu_tlu_npc_m[48:0]),
.ifu_tlu_pc_oor_e (ifu_tlu_pc_oor_e),
.ifu_exu_pcver_e (ifu_exu_pcver_e[63:0]),
.fdp_fcl_swc_s2 (fdp_fcl_swc_s2),
.fdp_fcl_pc_oor_vec_f(fdp_fcl_pc_oor_vec_f[3:0]),
.fdp_fcl_pc_oor_e (fdp_fcl_pc_oor_e),
.fdp_fcl_op_s (fdp_fcl_op_s[1:0]),
.fdp_fcl_op3_s (fdp_fcl_op3_s[5:2]),
.fdp_fcl_ibit_s (fdp_fcl_ibit_s),
// Inputs
.rclk (rclk),
.se (se),
.const_maskid (const_maskid[7:0]),
.lsu_t0_pctxt_state(lsu_t0_pctxt_state[12:0]),
.lsu_t1_pctxt_state(lsu_t1_pctxt_state[12:0]),
.lsu_t2_pctxt_state(lsu_t2_pctxt_state[12:0]),
.lsu_t3_pctxt_state(lsu_t3_pctxt_state[12:0]),
.exu_ifu_brpc_e (exu_ifu_brpc_e[47:0]),
.tlu_ifu_trappc_w2(tlu_ifu_trappc_w2[48:0]),
.tlu_ifu_trapnpc_w2(tlu_ifu_trapnpc_w2[48:0]),
.tlu_itlb_dmp_nctxt_g(tlu_itlb_dmp_nctxt_g),
.tlu_itlb_dmp_actxt_g(tlu_itlb_dmp_actxt_g),
.tlu_itlb_tte_tag_w2(tlu_itlb_tte_tag_w2[12:0]),
.dtu_fdp_thrconf_e(dtu_fdp_thrconf_e[40:0]),
.ifq_fdp_fill_inst(ifq_fdp_fill_inst[32:0]),
.fcl_fdp_oddwin_s (fcl_fdp_oddwin_s),
.fcl_fdp_pcoor_vec_f(fcl_fdp_pcoor_vec_f[3:0]),
.fcl_fdp_pcoor_f (fcl_fdp_pcoor_f),
.fcl_fdp_mask32b_f(fcl_fdp_mask32b_f),
.fcl_fdp_tctxt_sel_prim(fcl_fdp_tctxt_sel_prim[3:0]),
.fcl_fdp_usenir_sel_nir_s1(fcl_fdp_usenir_sel_nir_s1),
.fcl_fdp_rbinst_sel_inste_s(fcl_fdp_rbinst_sel_inste_s[3:0]),
.fcl_fdp_thrtnpc_sel_tnpc_l(fcl_fdp_thrtnpc_sel_tnpc_l[3:0]),
.fcl_fdp_thrtnpc_sel_npcw_l(fcl_fdp_thrtnpc_sel_npcw_l[3:0]),
.fcl_fdp_thrtnpc_sel_pcf_l(fcl_fdp_thrtnpc_sel_pcf_l[3:0]),
.fcl_fdp_thrtnpc_sel_old_l(fcl_fdp_thrtnpc_sel_old_l[3:0]),
.fcl_fdp_thr_s1_l (fcl_fdp_thr_s1_l[3:0]),
.fcl_fdp_next_thr_bf_l(fcl_fdp_next_thr_bf_l[3:0]),
.fcl_fdp_next_ctxt_bf_l(fcl_fdp_next_ctxt_bf_l[3:0]),
.fcl_fdp_thr_s2_l (fcl_fdp_thr_s2_l[3:0]),
.fcl_fdp_nirthr_s1_l(fcl_fdp_nirthr_s1_l[3:0]),
.fcl_fdp_tpcbf_sel_pcp4_bf_l(fcl_fdp_tpcbf_sel_pcp4_bf_l[3:0]),
.fcl_fdp_tpcbf_sel_brpc_bf_l(fcl_fdp_tpcbf_sel_brpc_bf_l[3:0]),
.fcl_fdp_tpcbf_sel_trap_bf_l(fcl_fdp_tpcbf_sel_trap_bf_l[3:0]),
.fcl_fdp_tpcbf_sel_old_bf_l(fcl_fdp_tpcbf_sel_old_bf_l[3:0]),
.fcl_fdp_pcbf_sel_swpc_bf_l(fcl_fdp_pcbf_sel_swpc_bf_l),
.fcl_fdp_pcbf_sel_nosw_bf_l(fcl_fdp_pcbf_sel_nosw_bf_l),
.fcl_fdp_pcbf_sel_br_bf_l(fcl_fdp_pcbf_sel_br_bf_l),
.fcl_fdp_trrbpc_sel_trap_bf_l(fcl_fdp_trrbpc_sel_trap_bf_l[3:0]),
.fcl_fdp_trrbpc_sel_rb_bf_l(fcl_fdp_trrbpc_sel_rb_bf_l[3:0]),
.fcl_fdp_trrbpc_sel_err_bf_l(fcl_fdp_trrbpc_sel_err_bf_l[3:0]),
.fcl_fdp_trrbpc_sel_pcs_bf_l(fcl_fdp_trrbpc_sel_pcs_bf_l[3:0]),
.fcl_fdp_noswpc_sel_tnpc_l_bf(fcl_fdp_noswpc_sel_tnpc_l_bf),
.fcl_fdp_noswpc_sel_old_l_bf(fcl_fdp_noswpc_sel_old_l_bf),
.fcl_fdp_noswpc_sel_inc_l_bf(fcl_fdp_noswpc_sel_inc_l_bf),
.fcl_fdp_nextpcs_sel_pce_f_l(fcl_fdp_nextpcs_sel_pce_f_l[3:0]),
.fcl_fdp_nextpcs_sel_pcd_f_l(fcl_fdp_nextpcs_sel_pcd_f_l[3:0]),
.fcl_fdp_nextpcs_sel_pcs_f_l(fcl_fdp_nextpcs_sel_pcs_f_l[3:0]),
.fcl_fdp_nextpcs_sel_pcf_f_l(fcl_fdp_nextpcs_sel_pcf_f_l[3:0]),
.fcl_fdp_rdsr_sel_pc_e_l(fcl_fdp_rdsr_sel_pc_e_l),
.fcl_fdp_rdsr_sel_ver_e_l(fcl_fdp_rdsr_sel_ver_e_l),
.fcl_fdp_rdsr_sel_thr_e_l(fcl_fdp_rdsr_sel_thr_e_l),
.fcl_fdp_inst_sel_curr_s_l(fcl_fdp_inst_sel_curr_s_l),
.fcl_fdp_inst_sel_switch_s_l(fcl_fdp_inst_sel_switch_s_l),
.fcl_fdp_inst_sel_nir_s_l(fcl_fdp_inst_sel_nir_s_l),
.fcl_fdp_inst_sel_nop_s_l(fcl_fdp_inst_sel_nop_s_l),
.fcl_fdp_tinst_sel_curr_s_l(fcl_fdp_tinst_sel_curr_s_l[3:0]),
.fcl_fdp_tinst_sel_rb_s_l(fcl_fdp_tinst_sel_rb_s_l[3:0]),
.fcl_fdp_tinst_sel_old_s_l(fcl_fdp_tinst_sel_old_s_l[3:0]),
.fcl_fdp_tinst_sel_ifq_s_l(fcl_fdp_tinst_sel_ifq_s_l[3:0]),
.fcl_fdp_dmpthr_l (fcl_fdp_dmpthr_l[3:0]),
.fcl_fdp_ctxt_sel_dmp_bf_l(fcl_fdp_ctxt_sel_dmp_bf_l),
.fcl_fdp_ctxt_sel_sw_bf_l(fcl_fdp_ctxt_sel_sw_bf_l),
.fcl_fdp_ctxt_sel_curr_bf_l(fcl_fdp_ctxt_sel_curr_bf_l));
sparc_ifu_fcl fcl(
.so (short_scan1_1),
.si (short_si1),
.rst_tri_en (mux_drive_disable),
// keep around in case we need it later
.ifu_reset_l (),
.fdp_fcl_va2_bf (fdp_icd_vaddr_bf[2]),
.itlb_fcl_priv_s1 (itlb_rd_tte_data[`STLB_DATA_P]),
.tlu_fcl_dmp_pid_bf (tlu_itlb_tte_tag_w2[58:56]),
.tlu_fcl_dmp_real_bf (tlu_itlb_tte_tag_w2[55]),
.itlb_fcl_cp_s1 (itlb_rd_tte_data[`STLB_DATA_CP]),
// need these here since itlb is not auto inst'ed
.fcl_itlb_invall_f_l(fcl_itlb_invall_f_l),
.fcl_itlb_cam_vld_bf(fcl_itlb_cam_vld_bf),
.fcl_itlb_cam_bypass_bf(fcl_itlb_cam_bypass_bf),
.fcl_itlb_addr_mask_l(fcl_itlb_addr_mask_l),
.fcl_itlb_cam_real_bf(fcl_itlb_cam_real_bf),
.fcl_itlb_cam_pid_bf(fcl_itlb_cam_pid_bf[2:0]),
.fcl_itlb_wr_vld_bf(fcl_itlb_wr_vld_bf),
.fcl_itlb_dmp_vld_bf(fcl_itlb_dmp_vld_bf),
.fcl_itlb_dmp_all_bf(fcl_itlb_dmp_all_bf),
.fcl_itlb_tag_rd_vld_bf(fcl_itlb_tag_rd_vld_bf),
.fcl_itlb_data_rd_vld_bf(fcl_itlb_data_rd_vld_bf),
// eco 5362
.fcl_fdp_addr_mask_d(ifu_exu_addr_mask_d),
/*AUTOINST*/
// Outputs
.fcl_icd_rdreq_bf (fcl_icd_rdreq_bf),
.fcl_icv_rdreq_bf (fcl_icv_rdreq_bf),
.fcl_icd_wrreq_bf (fcl_icd_wrreq_bf),
.fcl_ict_wrreq_bf (fcl_ict_wrreq_bf),
.fcl_icv_wrreq_bf (fcl_icv_wrreq_bf),
.fcl_icd_index_sel_ifq_bf(fcl_icd_index_sel_ifq_bf),
.fcl_ifq_grant_bf (fcl_ifq_grant_bf),
.fcl_ifq_icmiss_s1 (fcl_ifq_icmiss_s1),
.fcl_ifq_rdreq_s1 (fcl_ifq_rdreq_s1),
.fcl_ifq_icache_en_s_l(fcl_ifq_icache_en_s_l),
.fcl_ifq_thr_s1 (fcl_ifq_thr_s1[1:0]),
.fcl_ifq_canthr (fcl_ifq_canthr[3:0]),
.fcl_erb_ievld_s1 (fcl_erb_ievld_s1),
.fcl_erb_tevld_s1 (fcl_erb_tevld_s1),
.fcl_erb_immuevld_s1(fcl_erb_immuevld_s1),
.ifu_lsu_thrid_s (ifu_lsu_thrid_s[1:0]),
.fcl_erb_asi_tid_f (fcl_erb_asi_tid_f[1:0]),
.fcl_erb_clear_iferr(fcl_erb_clear_iferr[3:0]),
.fcl_erb_itlbrd_vld_s(fcl_erb_itlbrd_vld_s),
.fcl_erb_itlbrd_data_s(fcl_erb_itlbrd_data_s),
.fcl_dec_dslot_s (fcl_dec_dslot_s),
.fcl_dtu_inst_vld_e(fcl_dtu_inst_vld_e),
.fcl_dtu_intr_vld_e(fcl_dtu_intr_vld_e),
.fcl_dtu_inst_vld_d(fcl_dtu_inst_vld_d),
.fcl_dtu_ely_inst_vld_d(fcl_dtu_ely_inst_vld_d),
.fcl_dec_intr_vld_d(fcl_dec_intr_vld_d),
.fcl_erb_inst_issue_d(fcl_erb_inst_issue_d),
.fcl_erb_inst_vld_d1(fcl_erb_inst_vld_d1),
.ifu_tlu_inst_vld_m(ifu_tlu_inst_vld_m),
.ifu_exu_inst_vld_e(ifu_exu_inst_vld_e),
.ifu_exu_inst_vld_w(ifu_exu_inst_vld_w),
.ifu_spu_inst_vld_w(ifu_spu_inst_vld_w),
.ifu_tlu_inst_vld_w(ifu_tlu_inst_vld_w),
.ifu_tlu_flush_w (ifu_tlu_flush_w),
.ifu_tlu_flush_m (ifu_tlu_flush_m),
.fcl_swl_int_activate_i3(fcl_swl_int_activate_i3[3:0]),
.fcl_swl_flush_wake_w(fcl_swl_flush_wake_w),
.fcl_swl_flush_w (fcl_swl_flush_w),
.fcl_dcl_regz_e (fcl_dcl_regz_e),
.ifu_tlu_thrid_e (ifu_tlu_thrid_e[1:0]),
.ifu_tlu_thrid_d (ifu_tlu_thrid_d[1:0]),
.ifu_tlu_immu_miss_m(ifu_tlu_immu_miss_m),
.ifu_tlu_priv_violtn_m(ifu_tlu_priv_violtn_m),
.ifu_tlu_icmiss_e (ifu_tlu_icmiss_e),
.ifu_tlu_ttype_vld_m(ifu_tlu_ttype_vld_m),
.ifu_exu_ttype_vld_m(ifu_exu_ttype_vld_m),
.ifu_mmu_trap_m (ifu_mmu_trap_m),
.ifu_tlu_trap_m (ifu_tlu_trap_m),
.ifu_tlu_ttype_m (ifu_tlu_ttype_m[8:0]),
.ifu_tlu_hwint_m (ifu_tlu_hwint_m),
.ifu_tlu_sftint_m (ifu_tlu_sftint_m),
.ifu_tlu_rstint_m (ifu_tlu_rstint_m),
.fcl_dtu_rst_thr_w (fcl_dtu_rst_thr_w),
.fcl_dtu_resum_thr_w(fcl_dtu_resum_thr_w),
.ifu_tlu_itlb_done (ifu_tlu_itlb_done),
.ifu_spu_trap_ack (ifu_spu_trap_ack),
.ifu_exu_tid_s2 (ifu_exu_tid_s2[1:0]),
.ifu_exu_ren1_s (ifu_exu_ren1_s),
.ifu_exu_ren2_s (ifu_exu_ren2_s),
.ifu_exu_ren3_s (ifu_exu_ren3_s),
.ifu_exu_disable_ce_e(ifu_exu_disable_ce_e),
.fcl_dtu_sync_intr_d(fcl_dtu_sync_intr_d),
.fcl_dtu_tlzero_d (fcl_dtu_tlzero_d),
.fcl_dtu_privmode_d(fcl_dtu_privmode_d),
.fcl_dtu_hprivmode_d(fcl_dtu_hprivmode_d),
.fcl_dtu_hprivmode_w2(fcl_dtu_hprivmode_w2),
.fcl_dtu_nuke_thr_w(fcl_dtu_nuke_thr_w),
.fcl_swl_swout_f (fcl_swl_swout_f),
.fcl_dtu_stall_bf (fcl_dtu_stall_bf),
.fcl_swl_swcvld_s (fcl_swl_swcvld_s),
.fcl_dtu_thr_f (fcl_dtu_thr_f[3:0]),
.fcl_imd_oddwin_d (fcl_imd_oddwin_d),
.fcl_fdp_oddwin_s (fcl_fdp_oddwin_s),
.fcl_fdp_pcoor_vec_f(fcl_fdp_pcoor_vec_f[3:0]),
.fcl_fdp_pcoor_f (fcl_fdp_pcoor_f),
.fcl_fdp_mask32b_f (fcl_fdp_mask32b_f),
.fcl_fdp_tctxt_sel_prim(fcl_fdp_tctxt_sel_prim[3:0]),
.fcl_fdp_usenir_sel_nir_s1(fcl_fdp_usenir_sel_nir_s1),
.fcl_fdp_rbinst_sel_inste_s(fcl_fdp_rbinst_sel_inste_s[3:0]),
.fcl_fdp_thrtnpc_sel_tnpc_l(fcl_fdp_thrtnpc_sel_tnpc_l[3:0]),
.fcl_fdp_thrtnpc_sel_npcw_l(fcl_fdp_thrtnpc_sel_npcw_l[3:0]),
.fcl_fdp_thrtnpc_sel_pcf_l(fcl_fdp_thrtnpc_sel_pcf_l[3:0]),
.fcl_fdp_thrtnpc_sel_old_l(fcl_fdp_thrtnpc_sel_old_l[3:0]),
.fcl_fdp_thr_s1_l (fcl_fdp_thr_s1_l[3:0]),
.fcl_fdp_next_thr_bf_l(fcl_fdp_next_thr_bf_l[3:0]),
.fcl_fdp_next_ctxt_bf_l(fcl_fdp_next_ctxt_bf_l[3:0]),
.fcl_fdp_nirthr_s1_l(fcl_fdp_nirthr_s1_l[3:0]),
.fcl_fdp_thr_s2_l (fcl_fdp_thr_s2_l[3:0]),
.fcl_fdp_tpcbf_sel_pcp4_bf_l(fcl_fdp_tpcbf_sel_pcp4_bf_l[3:0]),
.fcl_fdp_tpcbf_sel_brpc_bf_l(fcl_fdp_tpcbf_sel_brpc_bf_l[3:0]),
.fcl_fdp_tpcbf_sel_trap_bf_l(fcl_fdp_tpcbf_sel_trap_bf_l[3:0]),
.fcl_fdp_tpcbf_sel_old_bf_l(fcl_fdp_tpcbf_sel_old_bf_l[3:0]),
.fcl_fdp_pcbf_sel_nosw_bf_l(fcl_fdp_pcbf_sel_nosw_bf_l),
.fcl_fdp_pcbf_sel_swpc_bf_l(fcl_fdp_pcbf_sel_swpc_bf_l),
.fcl_fdp_pcbf_sel_br_bf_l(fcl_fdp_pcbf_sel_br_bf_l),
.fcl_fdp_trrbpc_sel_trap_bf_l(fcl_fdp_trrbpc_sel_trap_bf_l[3:0]),
.fcl_fdp_trrbpc_sel_rb_bf_l(fcl_fdp_trrbpc_sel_rb_bf_l[3:0]),
.fcl_fdp_trrbpc_sel_err_bf_l(fcl_fdp_trrbpc_sel_err_bf_l[3:0]),
.fcl_fdp_trrbpc_sel_pcs_bf_l(fcl_fdp_trrbpc_sel_pcs_bf_l[3:0]),
.fcl_fdp_noswpc_sel_tnpc_l_bf(fcl_fdp_noswpc_sel_tnpc_l_bf),
.fcl_fdp_noswpc_sel_old_l_bf(fcl_fdp_noswpc_sel_old_l_bf),
.fcl_fdp_noswpc_sel_inc_l_bf(fcl_fdp_noswpc_sel_inc_l_bf),
.fcl_fdp_nextpcs_sel_pce_f_l(fcl_fdp_nextpcs_sel_pce_f_l[3:0]),
.fcl_fdp_nextpcs_sel_pcd_f_l(fcl_fdp_nextpcs_sel_pcd_f_l[3:0]),
.fcl_fdp_nextpcs_sel_pcs_f_l(fcl_fdp_nextpcs_sel_pcs_f_l[3:0]),
.fcl_fdp_nextpcs_sel_pcf_f_l(fcl_fdp_nextpcs_sel_pcf_f_l[3:0]),
.fcl_fdp_inst_sel_curr_s_l(fcl_fdp_inst_sel_curr_s_l),
.fcl_fdp_inst_sel_switch_s_l(fcl_fdp_inst_sel_switch_s_l),
.fcl_fdp_inst_sel_nir_s_l(fcl_fdp_inst_sel_nir_s_l),
.fcl_fdp_inst_sel_nop_s_l(fcl_fdp_inst_sel_nop_s_l),
.fcl_fdp_tinst_sel_curr_s_l(fcl_fdp_tinst_sel_curr_s_l[3:0]),
.fcl_fdp_tinst_sel_rb_s_l(fcl_fdp_tinst_sel_rb_s_l[3:0]),
.fcl_fdp_tinst_sel_old_s_l(fcl_fdp_tinst_sel_old_s_l[3:0]),
.fcl_fdp_tinst_sel_ifq_s_l(fcl_fdp_tinst_sel_ifq_s_l[3:0]),
.fcl_fdp_dmpthr_l (fcl_fdp_dmpthr_l[3:0]),
.fcl_fdp_ctxt_sel_dmp_bf_l(fcl_fdp_ctxt_sel_dmp_bf_l),
.fcl_fdp_ctxt_sel_sw_bf_l(fcl_fdp_ctxt_sel_sw_bf_l),
.fcl_fdp_ctxt_sel_curr_bf_l(fcl_fdp_ctxt_sel_curr_bf_l),
.fcl_fdp_rdsr_sel_pc_e_l(fcl_fdp_rdsr_sel_pc_e_l),
.fcl_fdp_rdsr_sel_thr_e_l(fcl_fdp_rdsr_sel_thr_e_l),
.fcl_fdp_rdsr_sel_ver_e_l(fcl_fdp_rdsr_sel_ver_e_l),
// Inputs
.rclk (rclk),
.grst_l (grst_l),
.arst_l (arst_l),
.se (se),
.sehold (sehold),
.tlu_ifu_flush_pipe_w(tlu_ifu_flush_pipe_w),
.exu_ifu_va_oor_m (exu_ifu_va_oor_m),
.exu_ifu_oddwin_s (exu_ifu_oddwin_s[3:0]),
.spu_ifu_ttype_tid_w2(spu_ifu_ttype_tid_w2[1:0]),
.spu_ifu_ttype_vld_w2(spu_ifu_ttype_vld_w2),
.spu_ifu_ttype_w2 (spu_ifu_ttype_w2),
.erb_fcl_spu_uetrap(erb_fcl_spu_uetrap[3:0]),
.exu_ifu_regz_e (exu_ifu_regz_e),
.dcl_fcl_bcregz0_e (dcl_fcl_bcregz0_e),
.dcl_fcl_bcregz1_e (dcl_fcl_bcregz1_e),
.dtu_fcl_rollback_g(dtu_fcl_rollback_g),
.dtu_fcl_retract_d (dtu_fcl_retract_d),
.dtu_fcl_br_inst_d (dtu_fcl_br_inst_d),
.dtu_fcl_sir_inst_e(dtu_fcl_sir_inst_e),
.dtu_fcl_privop_e (dtu_fcl_privop_e),
.dtu_fcl_fpdis_e (dtu_fcl_fpdis_e),
.dtu_fcl_imask_hit_e(dtu_fcl_imask_hit_e),
.dtu_fcl_illinst_e (dtu_fcl_illinst_e),
.dtu_fcl_thr_active(dtu_fcl_thr_active[3:0]),
.dec_fcl_rdsr_sel_pc_d(dec_fcl_rdsr_sel_pc_d),
.dec_fcl_rdsr_sel_thr_d(dec_fcl_rdsr_sel_thr_d),
.ifq_fcl_wrreq_bf (ifq_fcl_wrreq_bf),
.ifq_fcl_icd_wrreq_bf(ifq_fcl_icd_wrreq_bf),
.ifq_fcl_ictv_wrreq_bf(ifq_fcl_ictv_wrreq_bf),
.ifq_fcl_rdreq_bf (ifq_fcl_rdreq_bf),
.ifq_fcl_asi_tid_bf(ifq_fcl_asi_tid_bf[1:0]),
.ifq_fcl_asird_bf (ifq_fcl_asird_bf),
.ifq_fcl_invreq_bf (ifq_fcl_invreq_bf),
.erb_fcl_itlb_ce_d1(erb_fcl_itlb_ce_d1),
.erb_dtu_ifeterr_d1(erb_dtu_ifeterr_d1),
.erb_fcl_ifet_uevec_d1(erb_fcl_ifet_uevec_d1[3:0]),
.erb_fcl_ue_trapvec(erb_fcl_ue_trapvec[3:0]),
.erb_fcl_ce_trapvec(erb_fcl_ce_trapvec[3:0]),
.dtu_fcl_nextthr_bf(dtu_fcl_nextthr_bf[3:0]),
.dtu_fcl_ntr_s (dtu_fcl_ntr_s),
.dtu_fcl_running_s (dtu_fcl_running_s),
.dtu_fcl_flush_sonly_e(dtu_fcl_flush_sonly_e),
.fdp_fcl_swc_s2 (fdp_fcl_swc_s2),
.itlb_fcl_tlbmiss_f_l(itlb_fcl_tlbmiss_f_l),
.itlb_fcl_imiss_s_l(itlb_fcl_imiss_s_l),
.fdp_fcl_pc_oor_vec_f(fdp_fcl_pc_oor_vec_f[3:0]),
.fdp_fcl_pc_oor_e (fdp_fcl_pc_oor_e),
.fdp_fcl_op_s (fdp_fcl_op_s[1:0]),
.fdp_fcl_op3_s (fdp_fcl_op3_s[5:2]),
.fdp_fcl_ibit_s (fdp_fcl_ibit_s),
.lsu_ifu_stallreq (lsu_ifu_stallreq),
.ffu_ifu_stallreq (ffu_ifu_stallreq),
.ifq_fcl_stallreq (ifq_fcl_stallreq),
.dtu_inst_anull_e (dtu_inst_anull_e),
.ifq_fcl_fill_thr (ifq_fcl_fill_thr[3:0]),
.ifq_fcl_flush_sonly_e(ifq_fcl_flush_sonly_e),
.tlu_ifu_trap_tid_w1(tlu_ifu_trap_tid_w1[1:0]),
.tlu_ifu_trappc_vld_w1(tlu_ifu_trappc_vld_w1),
.tlu_ifu_trapnpc_vld_w1(tlu_ifu_trapnpc_vld_w1),
.tlu_lsu_pstate_priv(tlu_lsu_pstate_priv[3:0]),
.tlu_lsu_pstate_am (tlu_lsu_pstate_am[3:0]),
.tlu_hpstate_priv (tlu_hpstate_priv[3:0]),
.tlu_lsu_redmode (tlu_lsu_redmode[3:0]),
.tlu_hpstate_enb (tlu_hpstate_enb[3:0]),
.lsu_ifu_addr_real_l(lsu_ifu_addr_real_l[3:0]),
.lsu_pid_state0 (lsu_pid_state0[2:0]),
.lsu_pid_state1 (lsu_pid_state1[2:0]),
.lsu_pid_state2 (lsu_pid_state2[2:0]),
.lsu_pid_state3 (lsu_pid_state3[2:0]),
.lsu_ifu_icache_en (lsu_ifu_icache_en[3:0]),
.lsu_ifu_dc_parity_error_w2(lsu_ifu_dc_parity_error_w2),
.lsu_ifu_t0_tlz (lsu_ifu_t0_tlz),
.lsu_ifu_t1_tlz (lsu_ifu_t1_tlz),
.lsu_ifu_t2_tlz (lsu_ifu_t2_tlz),
.lsu_ifu_t3_tlz (lsu_ifu_t3_tlz),
.tlu_ifu_hwint_i3 (tlu_ifu_hwint_i3[3:0]),
.tlu_ifu_pstate_ie (tlu_ifu_pstate_ie[3:0]),
.tlu_ifu_sftint_vld(tlu_ifu_sftint_vld[3:0]),
.tlu_ifu_hintp_vld (tlu_ifu_hintp_vld[3:0]),
.tlu_ifu_rerr_vld (tlu_ifu_rerr_vld[3:0]),
.tlu_ifu_rstthr_i2 (tlu_ifu_rstthr_i2[3:0]),
.tlu_ifu_rstint_i2 (tlu_ifu_rstint_i2),
.tlu_ifu_resumint_i2(tlu_ifu_resumint_i2),
.tlu_ifu_nukeint_i2(tlu_ifu_nukeint_i2),
.tlu_itlb_wr_vld_g (tlu_itlb_wr_vld_g),
.tlu_itlb_dmp_vld_g(tlu_itlb_dmp_vld_g),
.tlu_itlb_dmp_all_g(tlu_itlb_dmp_all_g),
.tlu_itlb_data_rd_g(tlu_itlb_data_rd_g),
.tlu_itlb_tag_rd_g (tlu_itlb_tag_rd_g),
.tlu_itlb_invalidate_all_g(tlu_itlb_invalidate_all_g),
.tlu_idtlb_dmp_thrid_g(tlu_idtlb_dmp_thrid_g[1:0]),
.exu_ifu_ecc_ce_m (exu_ifu_ecc_ce_m),
.ffu_ifu_fst_ce_w (ffu_ifu_fst_ce_w));
// sparc_ifu_itlb itlb(
// .adj (lsu_idtlb_mrgn[7:0]),
// .reset (fcl_itlb_invall_bf),
// .tlu_itlb_dmp_actxt_g(tlu_itlb_dmp_actxt_g),
// .itlb_vaddr_offset_f (fdp_erb_pc_f[`IC_IDX_HI:(`IC_IDX_HI-1)]),
// /*AUTOINST*/
// // Outputs
// .ifu_lsu_tlb_writeable(ifu_lsu_tlb_writeable),
// .itlb_ifq_paddr_s(itlb_ifq_paddr_s[39:10]),
// .itlb_icd_waysel_s1(itlb_icd_waysel_s1[3:0]),
// .itlb_fcl_imiss_s_l(itlb_fcl_imiss_s_l),
// .itlb_fcl_tlbmiss_f_l(itlb_fcl_tlbmiss_f_l),
// .itlb_fcl_priv_s1(itlb_fcl_priv_s1),
// .itlb_rd_tte_data(itlb_rd_tte_data[42:0]),
// .itlb_rd_tte_tag(itlb_rd_tte_tag[58:0]),
// .so (so),
// Inputs
// .clk (clk),
// .se (se),
// .si (si),
// .fdp_icd_vaddr_bf(fdp_icd_vaddr_bf[47:10]),
// .fdp_itlb_ctxt_bf(fdp_itlb_ctxt_bf[12:0]),
// .ict_itlb_tags_f(ict_itlb_tags_f[`IC_TAG_ALL_HI:0]),
// .icv_itlb_valid_f(icv_itlb_valid_f[3:0]),
// .fcl_itlb_cam_vld_bf(fcl_itlb_cam_vld_bf),
// .fcl_itlb_wr_vld_bf(fcl_itlb_wr_vld_bf),
// .fcl_itlb_addr_mask_l(fcl_itlb_addr_mask_l),
// .fcl_itlb_dmp_vld_bf(fcl_itlb_dmp_vld_bf),
// .fcl_itlb_tag_rd_vld_bf(fcl_itlb_tag_rd_vld_bf),
// .fcl_itlb_data_rd_vld_bf(fcl_itlb_data_rd_vld_bf),
// .fcl_itlb_cam_real_bf(fcl_itlb_cam_real_bf),
// .fcl_itlb_cam_pid_bf(fcl_itlb_cam_pid_bf[2:0]),
// .tlu_itlb_tte_tag_w2(tlu_itlb_tte_tag_w2[58:0]),
// .tlu_itlb_tte_data_w2(tlu_itlb_tte_data_w2[42:0]),
// .tlu_itlb_rw_index_vld_g(tlu_itlb_rw_index_vld_g),
// .tlu_itlb_rw_index_g(tlu_itlb_rw_index_g[5:0]),
// .tlu_idtlb_dmp_key_g(tlu_idtlb_dmp_key_g[40:0]),
// .tlu_itlb_dmp_by_ctxt_g(tlu_itlb_dmp_by_ctxt_g),
// .tlu_itlb_dmp_all_g(tlu_itlb_dmp_all_g));
bw_r_tlb itlb(
.tlb_pgnum_crit (),
// Outputs
.tlb_rd_tte_tag (itlb_rd_tte_tag[58:0]), // 2
.tlb_rd_tte_data (itlb_rd_tte_data[42:0]), // 2
.tlb_pgnum (itlb_ifq_paddr_s[`IC_TAG_HI:10]), // 2
.tlb_cam_hit (itlb_fcl_tlbmiss_f_l), // 1
.cache_way_hit (itlb_wsel_waysel_s1[3:0]), // 2
.cache_hit (itlb_fcl_imiss_s_l), // 2
.so (short_scan0_1),
// Inputs
.rclk (rclk),
.rst_tri_en (mem_write_disable),
.tlb_cam_vld (fcl_itlb_cam_vld_bf), // 0
//`ifdef SPARC_HPV_EN
.tlb_cam_key ({fdp_icd_vaddr_bf[47:28], // 0
1'b1,
fdp_icd_vaddr_bf[27:22],
1'b1,
fdp_icd_vaddr_bf[21:16],
1'b1,
fdp_icd_vaddr_bf[15:13],
1'b1,
fcl_itlb_cam_real_bf, // g is the same as r
fcl_itlb_cam_real_bf}),// this is the r bit
//`else // !`ifdef SPARC_HPV_EN
// .tlb_cam_key ({1'b0, // unused // 0
// fdp_icd_vaddr_bf[47:35],
// 1'b1, // v47_22
// fdp_icd_vaddr_bf[34:22],
// fdp_icd_vaddr_bf[21:20],
// 1'b1, // v21_19
// fdp_icd_vaddr_bf[19],
// fdp_icd_vaddr_bf[18:17],
// 1'b1, // v18_16
// fdp_icd_vaddr_bf[16],
// fdp_icd_vaddr_bf[15:14],
// 1'b1, // v15_13
// fdp_icd_vaddr_bf[13], // global bit
// 1'b0}), // all r's are zero
//
// .tlb_cam_real (fcl_itlb_cam_real_bf), // 0
// .tlb_demap_ctxt (tlu_itlb_dmp_by_ctxt_g), // 0
//`endif
.tlb_cam_pid (fcl_itlb_cam_pid_bf[2:0]), // 0
.tlb_demap_key (tlu_idtlb_dmp_key_g[40:0]), // 0
.tlb_addr_mask_l (fcl_itlb_addr_mask_l), // 0
.tlb_ctxt (fdp_itlb_ctxt_bf[12:0]), // 0
.tlb_wr_vld (fcl_itlb_wr_vld_bf), // 0
.tlb_wr_tte_tag (tlu_itlb_tte_tag_w2[58:0]), // 1
.tlb_wr_tte_data(tlu_itlb_tte_data_w2[42:0]), // 1
.tlb_rd_tag_vld (fcl_itlb_tag_rd_vld_bf), // 0
.tlb_rd_data_vld (fcl_itlb_data_rd_vld_bf), // 0
.tlb_rw_index_vld(tlu_itlb_rw_index_vld_g), // 0
.tlb_rw_index (tlu_itlb_rw_index_g[5:0]), // 0
.tlb_demap (fcl_itlb_dmp_vld_bf), // 0
.tlb_demap_all (fcl_itlb_dmp_all_bf), // 0
.tlb_demap_auto (tlu_itlb_dmp_actxt_g),
.cache_ptag_w3 ({ict_itlb_tag3_f[27:0], // 1
fdp_erb_pc_f[`IC_IDX_HI:(`IC_IDX_HI-1)]}),
.cache_ptag_w2 ({ict_itlb_tag2_f[27:0], // 1
fdp_erb_pc_f[`IC_IDX_HI:(`IC_IDX_HI-1)]}),
.cache_ptag_w1 ({ict_itlb_tag1_f[27:0], // 1
fdp_erb_pc_f[`IC_IDX_HI:(`IC_IDX_HI-1)]}),
.cache_ptag_w0 ({ict_itlb_tag0_f[27:0], // 1
fdp_erb_pc_f[`IC_IDX_HI:(`IC_IDX_HI-1)]}),
.cache_set_vld (icv_itlb_valid_f[3:0]), // 1
.tlb_bypass (fcl_itlb_cam_bypass_bf), // 0
.tlb_bypass_va (fdp_icd_vaddr_bf[12:10]), // 0
.si (short_si0),
.se (se),
.hold (sehold),
.adj (lsu_idtlb_mrgn[7:0]),
// tlb expects this to be asynchronous reset!
.arst_l (arst_l),
.rst_soft_l (fcl_itlb_invall_f_l)); // 1
sparc_ifu_wseldp wseldp(
.so (scan0_6),
.si (scan0_5),
.wsel_mbist_icache_data(wsel_mbist_icache_data[67:0]),
/*AUTOINST*/
// Outputs
.wsel_fdp_fetdata_s1(wsel_fdp_fetdata_s1[33:0]),
.wsel_fdp_topdata_s1(wsel_fdp_topdata_s1[33:0]),
// Inputs
.rclk (rclk),
.se (se),
.icd_wsel_fetdata_s1(icd_wsel_fetdata_s1[135:0]),
.icd_wsel_topdata_s1(icd_wsel_topdata_s1[135:0]),
.itlb_wsel_waysel_s1(itlb_wsel_waysel_s1[3:0]),
.ifq_erb_asiway_f(ifq_erb_asiway_f[1:0]));
/* cmp_sram_redhdr AUTO_TEMPLATE(
.fuse_ary_wren(fuse_icd_wren),
.fuse_ary_rid(fuse_icd_rid[5:0]),
.fuse_ary_repair_value(fuse_icd_repair_value[7:0]),
.fuse_ary_repair_en(fuse_icd_repair_en[1:0]),
.spc_efc_xfuse_data(spc_efc_ifuse_data),
.efc_spc_xfuse_data(efc_spc_ifuse_data),
.efc_spc_xfuse_ashift(efc_spc_ifuse_ashift),
.efc_spc_xfuse_dshift(efc_spc_ifuse_dshift),
.ary_fuse_repair_value(icd_fuse_repair_value[7:0]),
.ary_fuse_repair_en(icd_fuse_repair_en[1:0]),
.scanin (scan0_6));
*/
cmp_sram_redhdr icdhdr(
.scanout (scan0_7),
/*AUTOINST*/
// Outputs
.fuse_ary_wren(fuse_icd_wren), // Templated
.fuse_ary_rid (fuse_icd_rid[5:0]), // Templated
.fuse_ary_repair_value(fuse_icd_repair_value[7:0]), // Templated
.fuse_ary_repair_en(fuse_icd_repair_en[1:0]), // Templated
.spc_efc_xfuse_data(spc_efc_ifuse_data), // Templated
// Inputs
.rclk (rclk),
.se (se),
.scanin (scan0_6), // Templated
.arst_l (arst_l),
.testmode_l (testmode_l),
.efc_spc_fuse_clk1(efc_spc_fuse_clk1),
.efc_spc_fuse_clk2(efc_spc_fuse_clk2),
.efc_spc_xfuse_data(efc_spc_ifuse_data), // Templated
.efc_spc_xfuse_ashift(efc_spc_ifuse_ashift), // Templated
.efc_spc_xfuse_dshift(efc_spc_ifuse_dshift), // Templated
.ary_fuse_repair_value(icd_fuse_repair_value[7:0]), // Templated
.ary_fuse_repair_en(icd_fuse_repair_en[1:0])); // Templated
// sparc_ifu_icd icd
bw_r_icd icd(
.so (scan0_8),
.si (scan0_7),
.fdp_icd_index_bf (fdp_icd_vaddr_bf[`IC_IDX_HI:2]),
.ifq_icd_index_bf ({ifq_icd_index_bf[`IC_IDX_HI:2]}),
.bist_ic_data (mbist_icache_wdata[7:0]),
.rst_tri_en (mem_write_disable),
.reset_l (arst_l),
/*AUTOINST*/
// Outputs
.icd_wsel_fetdata_s1 (icd_wsel_fetdata_s1[135:0]),
.icd_wsel_topdata_s1 (icd_wsel_topdata_s1[135:0]),
.icd_fuse_repair_value (icd_fuse_repair_value[7:0]),
.icd_fuse_repair_en (icd_fuse_repair_en[1:0]),
// Inputs
.rclk (rclk),
.se (se),
.sehold (sehold),
.fcl_icd_index_sel_ifq_bf(fcl_icd_index_sel_ifq_bf),
.ifq_icd_wrway_bf (ifq_icd_wrway_bf[1:0]),
.ifq_icd_worden_bf (ifq_icd_worden_bf[3:0]),
.ifq_icd_wrdata_i2 (ifq_icd_wrdata_i2[135:0]),
.fcl_icd_rdreq_bf (fcl_icd_rdreq_bf),
.fcl_icd_wrreq_bf (fcl_icd_wrreq_bf),
.ifq_icd_data_sel_old_i2(ifq_icd_data_sel_old_i2),
.ifq_icd_data_sel_fill_i2(ifq_icd_data_sel_fill_i2),
.ifq_icd_data_sel_bist_i2(ifq_icd_data_sel_bist_i2),
.fuse_icd_wren (fuse_icd_wren),
.fuse_icd_rid (fuse_icd_rid[3:0]),
.fuse_icd_repair_value (fuse_icd_repair_value[7:0]),
.fuse_icd_repair_en (fuse_icd_repair_en[1:0]),
.efc_spc_fuse_clk1 (efc_spc_fuse_clk1));
/* bw_r_idct AUTO_TEMPLATE(
// Inputs
.adj (lsu_ictag_mrgn[3:0]),
.reset_l (arst_l),
.index0_x (fdp_icd_vaddr_bf[`IC_IDX_HI:5]),
.index1_x (ifq_icd_index_bf[`IC_IDX_HI:5]),
.index_sel_x (fcl_icd_index_sel_ifq_bf),
.dec_wrway_x (ifq_ict_dec_wrway_bf[3:0]),
.wrtag_w0_y ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}),
.wrtag_w1_y ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}),
.wrtag_w2_y ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}),
.wrtag_w3_y ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}),
.rdreq_x (fcl_icd_rdreq_bf),
.wrreq_x (fcl_ict_wrreq_bf));
*/
bw_r_idct ict(
.so (short_scan0_2),
.si (short_scan0_1),
.rdtag_w0_y (ict_itlb_tag0_f[32:0]),
.rdtag_w1_y (ict_itlb_tag1_f[32:0]),
.rdtag_w2_y (ict_itlb_tag2_f[32:0]),
.rdtag_w3_y (ict_itlb_tag3_f[32:0]),
.rst_tri_en (mem_write_disable),
/*AUTOINST*/
// Inputs
.rclk (rclk),
.se (se),
.reset_l (arst_l), // Templated
.sehold (sehold),
.index0_x (fdp_icd_vaddr_bf[`IC_IDX_HI:5]), // Templated
.index1_x (ifq_icd_index_bf[`IC_IDX_HI:5]), // Templated
.index_sel_x (fcl_icd_index_sel_ifq_bf), // Templated
.dec_wrway_x (ifq_ict_dec_wrway_bf[3:0]), // Templated
.rdreq_x (fcl_icd_rdreq_bf), // Templated
.wrreq_x (fcl_ict_wrreq_bf), // Templated
.wrtag_w0_y ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}), // Templated
.wrtag_w1_y ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}), // Templated
.wrtag_w2_y ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}), // Templated
.wrtag_w3_y ({4'b0, ifq_ict_wrtag_f[`IC_TAG_SZ:0]}), // Templated
.adj (lsu_ictag_mrgn[3:0])); // Templated
// sparc_ifu_icv icv
/* bw_r_rf16x32 AUTO_TEMPLATE(
// Outputs
.dout (icv_itlb_valid_f[3:0]),
.so (short_so0),
// Inputs
.clk (clk),
.se (se),
.sehold (sehold),
.si (short_scan0_2),
.rst_tri_en (mem_write_disable),
.reset_l (arst_l),
.rd_adr2 (fdp_icv_index_bf[11:5]),
.rd_adr1 (ifq_icv_wrindex_bf[`IC_IDX_HI:5]),
.wr_adr (ifq_icv_wrindex_bf[`IC_IDX_HI:7]),
.rd_adr1_sel (fcl_ifq_grant_bf),
.din (ifq_icv_wrdata_bf),
.bit_wen (ifq_icv_wren_bf[15:0]),
.rd_en (fcl_icv_rdreq_bf),
.wr_en (fcl_icv_wrreq_bf));
*/
bw_r_rf16x32 icv(/*AUTOINST*/
// Outputs
.dout (icv_itlb_valid_f[3:0]), // Templated
.so (short_so0), // Templated
// Inputs
.rclk (rclk),
.se (se), // Templated
.si (short_scan0_2), // Templated
.reset_l (arst_l), // Templated
.sehold (sehold), // Templated
.rst_tri_en (mem_write_disable), // Templated
.rd_adr1 (ifq_icv_wrindex_bf[`IC_IDX_HI:5]), // Templated
.rd_adr2 (fdp_icv_index_bf[11:5]), // Templated
.rd_adr1_sel (fcl_ifq_grant_bf), // Templated
.rd_en (fcl_icv_rdreq_bf), // Templated
.wr_adr (ifq_icv_wrindex_bf[`IC_IDX_HI:7]), // Templated
.wr_en (fcl_icv_wrreq_bf), // Templated
.bit_wen (ifq_icv_wren_bf[15:0]), // Templated
.din (ifq_icv_wrdata_bf)); // Templated
sparc_ifu_ifqdp ifqdp(
.so (short_so1),
.si (short_scan1_1),
.ifq_ict_wrtag_f(ifq_ict_wrtag_f[`IC_TAG_SZ:0]),
.fdp_ifq_paddr_f(fdp_erb_pc_f[9:2]),
/*AUTOINST*/
// Outputs
.ifu_lsu_pcxpkt_e(ifu_lsu_pcxpkt_e[51:0]),
.ifq_fdp_fill_inst(ifq_fdp_fill_inst[32:0]),
.ifq_erb_asidata_i2(ifq_erb_asidata_i2[47:0]),
.ifd_inv_ifqop_i2(ifd_inv_ifqop_i2[`CPX_WIDTH-1:0]),
.ifq_icd_index_bf(ifq_icd_index_bf[`IC_IDX_HI:2]),
.ifq_icd_wrdata_i2(ifq_icd_wrdata_i2[135:0]),
.ifq_erb_wrindex_f(ifq_erb_wrindex_f[`IC_IDX_HI:4]),
.ifq_icd_wrway_bf(ifq_icd_wrway_bf[1:0]),
.ifd_ifc_milhit_s(ifd_ifc_milhit_s[3:0]),
.ifd_ifc_instoffset0(ifd_ifc_instoffset0[1:0]),
.ifd_ifc_instoffset1(ifd_ifc_instoffset1[1:0]),
.ifd_ifc_instoffset2(ifd_ifc_instoffset2[1:0]),
.ifd_ifc_instoffset3(ifd_ifc_instoffset3[1:0]),
.ifd_ifc_cpxthr_nxt(ifd_ifc_cpxthr_nxt[1:0]),
.ifd_ifc_cpxreq_nxt(ifd_ifc_cpxreq_nxt[3:0]),
.ifd_ifc_cpxreq_i1(ifd_ifc_cpxreq_i1[`CPX_RQ_SIZE:0]),
.ifd_ifc_destid0(ifd_ifc_destid0[2:0]),
.ifd_ifc_destid1(ifd_ifc_destid1[2:0]),
.ifd_ifc_destid2(ifd_ifc_destid2[2:0]),
.ifd_ifc_destid3(ifd_ifc_destid3[2:0]),
.ifd_ifc_newdestid_s(ifd_ifc_newdestid_s[2:0]),
.ifd_ifc_pcxline_d(ifd_ifc_pcxline_d[4:2]),
.ifd_ifc_asi_vachklo_i2(ifd_ifc_asi_vachklo_i2),
.ifd_ifc_cpxvld_i2(ifd_ifc_cpxvld_i2),
.ifd_ifc_asiaddr_i2(ifd_ifc_asiaddr_i2[3:2]),
.ifd_ifc_iobpkt_i2(ifd_ifc_iobpkt_i2),
.ifd_ifc_fwd2ic_i2(ifd_ifc_fwd2ic_i2),
.ifd_ifc_4bpkt_i2(ifd_ifc_4bpkt_i2),
.ifd_ifc_cpxnc_i2(ifd_ifc_cpxnc_i2),
.ifd_ifc_cpxce_i2(ifd_ifc_cpxce_i2),
.ifd_ifc_cpxue_i2(ifd_ifc_cpxue_i2),
.ifd_ifc_cpxms_i2(ifd_ifc_cpxms_i2),
.ifd_ifc_miladdr4_i2(ifd_ifc_miladdr4_i2[3:0]),
.ifd_inv_wrway_i2(ifd_inv_wrway_i2[1:0]),
// Inputs
.rclk (rclk),
.se (se),
.lsu_ifu_cpxpkt_i1(lsu_ifu_cpxpkt_i1[`CPX_WIDTH-1:0]),
.lsu_ifu_asi_addr(lsu_ifu_asi_addr[17:0]),
.lsu_ifu_stxa_data(lsu_ifu_stxa_data[47:0]),
.itlb_ifq_paddr_s(itlb_ifq_paddr_s[39:10]),
.ifc_ifd_reqvalid_e(ifc_ifd_reqvalid_e),
.ifc_ifd_filladdr4_i2(ifc_ifd_filladdr4_i2),
.ifc_ifd_repway_s(ifc_ifd_repway_s[1:0]),
.ifc_ifd_uncached_e(ifc_ifd_uncached_e),
.ifc_ifd_thrid_e(ifc_ifd_thrid_e[1:0]),
.ifc_ifd_pcxline_adj_d(ifc_ifd_pcxline_adj_d[4:2]),
.ifc_ifd_errinv_e(ifc_ifd_errinv_e),
.ifc_ifd_ldmil_sel_new(ifc_ifd_ldmil_sel_new[3:0]),
.ifc_ifd_ld_inq_i1(ifc_ifd_ld_inq_i1),
.ifc_ifd_idx_sel_fwd_i2(ifc_ifd_idx_sel_fwd_i2),
.ifc_ifd_milreq_sel_d_l(ifc_ifd_milreq_sel_d_l[3:0]),
.ifc_ifd_milfill_sel_i2_l(ifc_ifd_milfill_sel_i2_l[3:0]),
.ifc_ifd_finst_sel_l(ifc_ifd_finst_sel_l[3:0]),
.ifc_ifd_ifqbyp_sel_fwd_l(ifc_ifd_ifqbyp_sel_fwd_l),
.ifc_ifd_ifqbyp_sel_inq_l(ifc_ifd_ifqbyp_sel_inq_l),
.ifc_ifd_ifqbyp_sel_asi_l(ifc_ifd_ifqbyp_sel_asi_l),
.ifc_ifd_ifqbyp_sel_lsu_l(ifc_ifd_ifqbyp_sel_lsu_l),
.ifc_ifd_ifqbyp_en_l(ifc_ifd_ifqbyp_en_l),
.ifc_ifd_addr_sel_bist_i2_l(ifc_ifd_addr_sel_bist_i2_l),
.ifc_ifd_addr_sel_asi_i2_l(ifc_ifd_addr_sel_asi_i2_l),
.ifc_ifd_addr_sel_old_i2_l(ifc_ifd_addr_sel_old_i2_l),
.ifc_ifd_addr_sel_fill_i2_l(ifc_ifd_addr_sel_fill_i2_l),
.mbist_icache_way(mbist_icache_way[1:0]),
.mbist_icache_word(mbist_icache_word),
.mbist_icache_index(mbist_icache_index[7:0]));
sparc_ifu_ifqctl ifqctl(
.so (scan0_9),
.si (scan0_8),
.ifd_ifc_cpxvalid_i1(lsu_ifu_cpxpkt_i1[`CPX_VLD]),
.lsu_ifu_cpxpkt_wayvld_i1 (lsu_ifu_cpxpkt_i1[`CPX_WYVLD]),
.ifq_sscan_data(ifq_sscan_data[3:0]),
.rst_tri_en (mux_drive_disable),
/*AUTOINST*/
// Outputs
.ifu_lsu_inv_clear(ifu_lsu_inv_clear),
.ifu_lsu_ibuf_busy(ifu_lsu_ibuf_busy),
.ifu_lsu_asi_ack(ifu_lsu_asi_ack),
.ifu_lsu_ldxa_illgl_va_w2(ifu_lsu_ldxa_illgl_va_w2),
.ifu_lsu_fwd_wr_ack(ifu_lsu_fwd_wr_ack),
.ifu_lsu_pcxreq_d(ifu_lsu_pcxreq_d),
.ifu_lsu_destid_s(ifu_lsu_destid_s[2:0]),
.ifu_tlu_l2imiss(ifu_tlu_l2imiss[3:0]),
.ifq_fcl_stallreq(ifq_fcl_stallreq),
.ifq_swl_stallreq(ifq_swl_stallreq),
.ifq_fcl_flush_sonly_e(ifq_fcl_flush_sonly_e),
.ifq_fcl_wrreq_bf(ifq_fcl_wrreq_bf),
.ifq_fcl_rdreq_bf(ifq_fcl_rdreq_bf),
.ifq_fcl_icd_wrreq_bf(ifq_fcl_icd_wrreq_bf),
.ifq_fcl_ictv_wrreq_bf(ifq_fcl_ictv_wrreq_bf),
.ifq_erb_fwdrd_bf(ifq_erb_fwdrd_bf),
.ifq_erb_rdtag_f(ifq_erb_rdtag_f),
.ifq_erb_rdinst_f(ifq_erb_rdinst_f),
.ifq_erb_asi_erren_i2(ifq_erb_asi_erren_i2),
.ifq_erb_asi_errstat_i2(ifq_erb_asi_errstat_i2),
.ifq_erb_asi_errinj_i2(ifq_erb_asi_errinj_i2),
.ifq_erb_asi_erraddr_i2(ifq_erb_asi_erraddr_i2),
.ifq_erb_asi_imask_i2(ifq_erb_asi_imask_i2),
.ifq_erb_asiwr_i2(ifq_erb_asiwr_i2),
.ifq_fcl_asird_bf(ifq_fcl_asird_bf),
.ifq_fcl_asi_tid_bf(ifq_fcl_asi_tid_bf[1:0]),
.ifq_erb_ue_rep(ifq_erb_ue_rep),
.ifq_erb_ce_rep(ifq_erb_ce_rep),
.ifq_erb_l2_ue(ifq_erb_l2_ue),
.ifq_erb_io_ue(ifq_erb_io_ue),
.ifq_erb_ifet_ce(ifq_erb_ifet_ce),
.ifq_erb_l2err_tid(ifq_erb_l2err_tid[1:0]),
.ifq_icv_wrdata_bf(ifq_icv_wrdata_bf),
.ifq_icd_worden_bf(ifq_icd_worden_bf[3:0]),
.ifq_fcl_fill_thr(ifq_fcl_fill_thr[3:0]),
.ifq_dtu_thrrdy(ifq_dtu_thrrdy[3:0]),
.ifq_dtu_pred_rdy(ifq_dtu_pred_rdy[3:0]),
.ifc_ifd_filladdr4_i2(ifc_ifd_filladdr4_i2),
.ifc_ifd_reqvalid_e(ifc_ifd_reqvalid_e),
.ifc_ifd_idx_sel_fwd_i2(ifc_ifd_idx_sel_fwd_i2),
.ifc_ifd_errinv_e(ifc_ifd_errinv_e),
.ifc_ifd_uncached_e(ifc_ifd_uncached_e),
.ifc_ifd_thrid_e(ifc_ifd_thrid_e[1:0]),
.ifc_ifd_pcxline_adj_d(ifc_ifd_pcxline_adj_d[4:2]),
.ifc_inv_asireq_i2(ifc_inv_asireq_i2),
.ifc_ifd_repway_s(ifc_ifd_repway_s[1:0]),
.ifc_ifd_milfill_sel_i2_l(ifc_ifd_milfill_sel_i2_l[3:0]),
.ifc_ifd_finst_sel_l(ifc_ifd_finst_sel_l[3:0]),
.ifc_ifd_milreq_sel_d_l(ifc_ifd_milreq_sel_d_l[3:0]),
.ifc_ifd_ifqbyp_sel_fwd_l(ifc_ifd_ifqbyp_sel_fwd_l),
.ifc_ifd_ifqbyp_sel_inq_l(ifc_ifd_ifqbyp_sel_inq_l),
.ifc_ifd_ifqbyp_sel_asi_l(ifc_ifd_ifqbyp_sel_asi_l),
.ifc_ifd_ifqbyp_sel_lsu_l(ifc_ifd_ifqbyp_sel_lsu_l),
.ifc_ifd_ifqbyp_en_l(ifc_ifd_ifqbyp_en_l),
.ifc_ifd_addr_sel_bist_i2_l(ifc_ifd_addr_sel_bist_i2_l),
.ifc_ifd_addr_sel_asi_i2_l(ifc_ifd_addr_sel_asi_i2_l),
.ifc_ifd_addr_sel_old_i2_l(ifc_ifd_addr_sel_old_i2_l),
.ifc_ifd_addr_sel_fill_i2_l(ifc_ifd_addr_sel_fill_i2_l),
.ifq_icd_data_sel_bist_i2(ifq_icd_data_sel_bist_i2),
.ifq_icd_data_sel_fill_i2(ifq_icd_data_sel_fill_i2),
.ifq_icd_data_sel_old_i2(ifq_icd_data_sel_old_i2),
.ifc_ifd_ldmil_sel_new(ifc_ifd_ldmil_sel_new[3:0]),
.ifc_ifd_ld_inq_i1(ifc_ifd_ld_inq_i1),
.ifc_inv_ifqadv_i2(ifc_inv_ifqadv_i2),
// Inputs
.ifd_ifc_milhit_s(ifd_ifc_milhit_s[3:0]),
.ifd_ifc_instoffset0(ifd_ifc_instoffset0[1:0]),
.ifd_ifc_instoffset1(ifd_ifc_instoffset1[1:0]),
.ifd_ifc_instoffset2(ifd_ifc_instoffset2[1:0]),
.ifd_ifc_instoffset3(ifd_ifc_instoffset3[1:0]),
.ifd_ifc_cpxreq_i1(ifd_ifc_cpxreq_i1[`CPX_RQ_SIZE:0]),
.ifd_ifc_cpxreq_nxt(ifd_ifc_cpxreq_nxt[3:0]),
.ifd_ifc_cpxthr_nxt(ifd_ifc_cpxthr_nxt[1:0]),
.ifd_ifc_cpxvld_i2(ifd_ifc_cpxvld_i2),
.ifd_ifc_iobpkt_i2(ifd_ifc_iobpkt_i2),
.ifd_ifc_4bpkt_i2(ifd_ifc_4bpkt_i2),
.ifd_ifc_cpxnc_i2(ifd_ifc_cpxnc_i2),
.ifd_ifc_fwd2ic_i2(ifd_ifc_fwd2ic_i2),
.ifd_ifc_cpxce_i2(ifd_ifc_cpxce_i2),
.ifd_ifc_cpxue_i2(ifd_ifc_cpxue_i2),
.ifd_ifc_cpxms_i2(ifd_ifc_cpxms_i2),
.ifd_ifc_miladdr4_i2(ifd_ifc_miladdr4_i2[3:0]),
.ifd_ifc_asiaddr_i2(ifd_ifc_asiaddr_i2[3:2]),
.ifd_ifc_asi_vachklo_i2(ifd_ifc_asi_vachklo_i2),
.ifd_ifc_destid0(ifd_ifc_destid0[2:0]),
.ifd_ifc_destid1(ifd_ifc_destid1[2:0]),
.ifd_ifc_destid2(ifd_ifc_destid2[2:0]),
.ifd_ifc_destid3(ifd_ifc_destid3[2:0]),
.ifd_ifc_newdestid_s(ifd_ifc_newdestid_s[2:0]),
.ifd_ifc_pcxline_d(ifd_ifc_pcxline_d[4:2]),
.inv_ifc_inv_pending(inv_ifc_inv_pending),
.fcl_ifq_icmiss_s1(fcl_ifq_icmiss_s1),
.fcl_ifq_rdreq_s1(fcl_ifq_rdreq_s1),
.fcl_ifq_thr_s1(fcl_ifq_thr_s1[1:0]),
.fcl_ifq_canthr(fcl_ifq_canthr[3:0]),
.fcl_ifq_grant_bf(fcl_ifq_grant_bf),
.dtu_ifq_kill_latest_d(dtu_ifq_kill_latest_d),
.erb_ifq_ifeterr_d1(erb_ifq_ifeterr_d1),
.erb_ifq_itlberr_s1(erb_ifq_itlberr_s1),
.lsu_ifu_pcxpkt_ack_d(lsu_ifu_pcxpkt_ack_d),
.lsu_ifu_direct_map_l1(lsu_ifu_direct_map_l1),
.lsu_ifu_asi_vld(lsu_ifu_asi_vld),
.lsu_ifu_asi_state(lsu_ifu_asi_state[7:0]),
.lsu_ifu_asi_load(lsu_ifu_asi_load),
.lsu_ifu_asi_thrid(lsu_ifu_asi_thrid[1:0]),
.fcl_ifq_icache_en_s_l(fcl_ifq_icache_en_s_l),
.mbist_ifq_run_bist(mbist_ifq_run_bist),
.mbist_icache_write(mbist_icache_write),
.mbist_icache_read(mbist_icache_read),
.ctu_sscan_tid(ctu_sscan_tid[3:0]),
.rclk (rclk),
.se (se),
.gdbginit_l (gdbginit_l),
.arst_l (arst_l),
.grst_l (grst_l),
.sehold (sehold));
sparc_ifu_invctl invctl(
.so (scan0_10),
.si (scan0_9),
/*AUTOINST*/
// Outputs
.inv_ifc_inv_pending(inv_ifc_inv_pending),
.ifq_icv_wrindex_bf(ifq_icv_wrindex_bf[`IC_IDX_HI:5]),
.ifq_icv_wren_bf(ifq_icv_wren_bf[15:0]),
.ifq_ict_dec_wrway_bf(ifq_ict_dec_wrway_bf[3:0]),
.ifq_fcl_invreq_bf(ifq_fcl_invreq_bf),
.ifq_erb_asiway_f(ifq_erb_asiway_f[1:0]),
// Inputs
.rclk (rclk),
.se (se),
.const_cpuid (const_cpuid[2:0]),
.mbist_icache_write(mbist_icache_write),
.lsu_ifu_ld_icache_index(lsu_ifu_ld_icache_index[`IC_IDX_HI:5]),
.lsu_ifu_ld_pcxpkt_vld(lsu_ifu_ld_pcxpkt_vld),
.lsu_ifu_ld_pcxpkt_tid(lsu_ifu_ld_pcxpkt_tid[1:0]),
.ifc_inv_ifqadv_i2(ifc_inv_ifqadv_i2),
.ifc_inv_asireq_i2(ifc_inv_asireq_i2),
.ifq_icd_index_bf(ifq_icd_index_bf[`IC_IDX_HI:5]),
.ifd_inv_ifqop_i2(ifd_inv_ifqop_i2[`CPX_WIDTH-1:0]),
.ifd_inv_wrway_i2(ifd_inv_wrway_i2[1:0]));
sparc_ifu_errdp errdp(
.so (scan0_11),
.si (scan0_10),
.ifq_erb_wrtag_f(ifq_ict_wrtag_f[`IC_TAG_SZ-1:0]),
.ict_itlb_tags_f({ict_itlb_tag3_f[28:0],
ict_itlb_tag2_f[28:0],
ict_itlb_tag1_f[28:0],
ict_itlb_tag0_f[28:0]}),
.wsel_erb_asidata_s({wsel_mbist_icache_data[65:64],
wsel_mbist_icache_data[31:0]}),
/*AUTOINST*/
// Outputs
.ifu_lsu_ldxa_data_w2(ifu_lsu_ldxa_data_w2[63:0]),
.erb_dtu_imask(erb_dtu_imask[38:0]),
.erd_erc_tlbt_pe_s1(erd_erc_tlbt_pe_s1[1:0]),
.erd_erc_tlbd_pe_s1(erd_erc_tlbd_pe_s1[1:0]),
.erd_erc_tagpe_s1(erd_erc_tagpe_s1[3:0]),
.erd_erc_nirpe_s1(erd_erc_nirpe_s1),
.erd_erc_fetpe_s1(erd_erc_fetpe_s1),
.erd_erc_tte_pgsz(erd_erc_tte_pgsz[2:0]),
// Inputs
.rclk (rclk),
.se (se),
.erb_reset (erb_reset),
.itlb_rd_tte_data(itlb_rd_tte_data[42:0]),
.itlb_rd_tte_tag(itlb_rd_tte_tag[58:0]),
.itlb_ifq_paddr_s(itlb_ifq_paddr_s[39:10]),
.wsel_fdp_fetdata_s1(wsel_fdp_fetdata_s1[33:0]),
.wsel_fdp_topdata_s1(wsel_fdp_topdata_s1[33:0]),
.icv_itlb_valid_f(icv_itlb_valid_f[3:0]),
.lsu_ifu_err_addr(lsu_ifu_err_addr[47:4]),
.spu_ifu_err_addr_w2(spu_ifu_err_addr_w2[39:4]),
.fdp_erb_pc_f (fdp_erb_pc_f[47:0]),
.exu_ifu_err_reg_m(exu_ifu_err_reg_m[7:0]),
.exu_ifu_err_synd_m(exu_ifu_err_synd_m[7:0]),
.ffu_ifu_err_reg_w2(ffu_ifu_err_reg_w2[5:0]),
.ffu_ifu_err_synd_w2(ffu_ifu_err_synd_w2[13:0]),
.tlu_itlb_rw_index_g(tlu_itlb_rw_index_g[5:0]),
.erc_erd_pgsz_b0(erc_erd_pgsz_b0),
.erc_erd_pgsz_b1(erc_erd_pgsz_b1),
.erc_erd_erren_asidata(erc_erd_erren_asidata[1:0]),
.erc_erd_errstat_asidata(erc_erd_errstat_asidata[22:0]),
.erc_erd_errinj_asidata(erc_erd_errinj_asidata[31:0]),
.ifq_erb_asidata_i2(ifq_erb_asidata_i2[47:0]),
.ifq_erb_wrindex_f(ifq_erb_wrindex_f[`IC_IDX_HI:4]),
.erc_erd_asiway_s1_l(erc_erd_asiway_s1_l[3:0]),
.fcl_erb_itlbrd_data_s(fcl_erb_itlbrd_data_s),
.erc_erd_ld_imask(erc_erd_ld_imask),
.erc_erd_asisrc_sel_icd_s_l(erc_erd_asisrc_sel_icd_s_l),
.erc_erd_asisrc_sel_misc_s_l(erc_erd_asisrc_sel_misc_s_l),
.erc_erd_asisrc_sel_err_s_l(erc_erd_asisrc_sel_err_s_l),
.erc_erd_asisrc_sel_itlb_s_l(erc_erd_asisrc_sel_itlb_s_l),
.erc_erd_errasi_sel_en_l(erc_erd_errasi_sel_en_l),
.erc_erd_errasi_sel_stat_l(erc_erd_errasi_sel_stat_l),
.erc_erd_errasi_sel_inj_l(erc_erd_errasi_sel_inj_l),
.erc_erd_errasi_sel_addr_l(erc_erd_errasi_sel_addr_l),
.erc_erd_miscasi_sel_ict_l(erc_erd_miscasi_sel_ict_l),
.erc_erd_miscasi_sel_imask_l(erc_erd_miscasi_sel_imask_l),
.erc_erd_miscasi_sel_other_l(erc_erd_miscasi_sel_other_l),
.erc_erd_asi_thr_l(erc_erd_asi_thr_l[3:0]),
.erc_erd_eadr0_sel_irf_l(erc_erd_eadr0_sel_irf_l[3:0]),
.erc_erd_eadr0_sel_itlb_l(erc_erd_eadr0_sel_itlb_l[3:0]),
.erc_erd_eadr0_sel_frf_l(erc_erd_eadr0_sel_frf_l[3:0]),
.erc_erd_eadr0_sel_lsu_l(erc_erd_eadr0_sel_lsu_l[3:0]),
.erc_erd_eadr1_sel_pcd1_l(erc_erd_eadr1_sel_pcd1_l[3:0]),
.erc_erd_eadr1_sel_l1pa_l(erc_erd_eadr1_sel_l1pa_l[3:0]),
.erc_erd_eadr1_sel_l2pa_l(erc_erd_eadr1_sel_l2pa_l[3:0]),
.erc_erd_eadr1_sel_other_l(erc_erd_eadr1_sel_other_l[3:0]),
.erc_erd_eadr2_sel_mx1_l(erc_erd_eadr2_sel_mx1_l[3:0]),
.erc_erd_eadr2_sel_wrt_l(erc_erd_eadr2_sel_wrt_l[3:0]),
.erc_erd_eadr2_sel_mx0_l(erc_erd_eadr2_sel_mx0_l[3:0]),
.erc_erd_eadr2_sel_old_l(erc_erd_eadr2_sel_old_l[3:0]));
sparc_ifu_errctl errctl(
.so (scan0_12),
.si (scan0_11),
.ifu_tlu_inst_vld_w(ifu_spu_inst_vld_w),
/*AUTOINST*/
// Outputs
.erc_erd_pgsz_b0(erc_erd_pgsz_b0),
.erc_erd_pgsz_b1(erc_erd_pgsz_b1),
.ifu_lsu_asi_rd_unc(ifu_lsu_asi_rd_unc),
.ifu_lsu_ldxa_tid_w2(ifu_lsu_ldxa_tid_w2[1:0]),
.ifu_lsu_ldxa_data_vld_w2(ifu_lsu_ldxa_data_vld_w2),
.ifu_lsu_fwd_data_vld(ifu_lsu_fwd_data_vld),
.ifu_lsu_error_inj(ifu_lsu_error_inj[3:0]),
.ifu_exu_ecc_mask(ifu_exu_ecc_mask[7:0]),
.ifu_exu_inj_irferr(ifu_exu_inj_irferr),
.ifu_ffu_inj_frferr(ifu_ffu_inj_frferr),
.ifu_exu_nceen_e(ifu_exu_nceen_e),
.ifu_lsu_nceen(ifu_lsu_nceen[3:0]),
.ifu_spu_nceen(ifu_spu_nceen[3:0]),
.erb_fcl_spu_uetrap(erb_fcl_spu_uetrap[3:0]),
.erb_ifq_itlberr_s1(erb_ifq_itlberr_s1),
.erb_ifq_ifeterr_d1(erb_ifq_ifeterr_d1),
.erb_dtu_ifeterr_d1(erb_dtu_ifeterr_d1),
.erb_fcl_itlb_ce_d1(erb_fcl_itlb_ce_d1),
.erb_fcl_ce_trapvec(erb_fcl_ce_trapvec[3:0]),
.erb_fcl_ue_trapvec(erb_fcl_ue_trapvec[3:0]),
.erb_fcl_ifet_uevec_d1(erb_fcl_ifet_uevec_d1[3:0]),
.erc_erd_errstat_asidata(erc_erd_errstat_asidata[22:0]),
.erc_erd_errinj_asidata(erc_erd_errinj_asidata[31:0]),
.erc_erd_erren_asidata(erc_erd_erren_asidata[1:0]),
.erc_erd_eadr0_sel_irf_l(erc_erd_eadr0_sel_irf_l[3:0]),
.erc_erd_eadr0_sel_itlb_l(erc_erd_eadr0_sel_itlb_l[3:0]),
.erc_erd_eadr0_sel_frf_l(erc_erd_eadr0_sel_frf_l[3:0]),
.erc_erd_eadr0_sel_lsu_l(erc_erd_eadr0_sel_lsu_l[3:0]),
.erc_erd_asiway_s1_l(erc_erd_asiway_s1_l[3:0]),
.erc_erd_eadr1_sel_pcd1_l(erc_erd_eadr1_sel_pcd1_l[3:0]),
.erc_erd_eadr1_sel_l1pa_l(erc_erd_eadr1_sel_l1pa_l[3:0]),
.erc_erd_eadr1_sel_l2pa_l(erc_erd_eadr1_sel_l2pa_l[3:0]),
.erc_erd_eadr1_sel_other_l(erc_erd_eadr1_sel_other_l[3:0]),
.erc_erd_eadr2_sel_mx1_l(erc_erd_eadr2_sel_mx1_l[3:0]),
.erc_erd_eadr2_sel_wrt_l(erc_erd_eadr2_sel_wrt_l[3:0]),
.erc_erd_eadr2_sel_mx0_l(erc_erd_eadr2_sel_mx0_l[3:0]),
.erc_erd_eadr2_sel_old_l(erc_erd_eadr2_sel_old_l[3:0]),
.erc_erd_asi_thr_l(erc_erd_asi_thr_l[3:0]),
.erc_erd_asisrc_sel_icd_s_l(erc_erd_asisrc_sel_icd_s_l),
.erc_erd_asisrc_sel_misc_s_l(erc_erd_asisrc_sel_misc_s_l),
.erc_erd_asisrc_sel_err_s_l(erc_erd_asisrc_sel_err_s_l),
.erc_erd_asisrc_sel_itlb_s_l(erc_erd_asisrc_sel_itlb_s_l),
.erc_erd_errasi_sel_en_l(erc_erd_errasi_sel_en_l),
.erc_erd_errasi_sel_stat_l(erc_erd_errasi_sel_stat_l),
.erc_erd_errasi_sel_inj_l(erc_erd_errasi_sel_inj_l),
.erc_erd_errasi_sel_addr_l(erc_erd_errasi_sel_addr_l),
.erc_erd_miscasi_sel_ict_l(erc_erd_miscasi_sel_ict_l),
.erc_erd_miscasi_sel_imask_l(erc_erd_miscasi_sel_imask_l),
.erc_erd_miscasi_sel_other_l(erc_erd_miscasi_sel_other_l),
.erc_erd_ld_imask(erc_erd_ld_imask),
.erb_reset (erb_reset),
// Inputs
.rclk (rclk),
.se (se),
.arst_l (arst_l),
.grst_l (grst_l),
.erd_erc_tte_pgsz(erd_erc_tte_pgsz[2:0]),
.icv_itlb_valid_f(icv_itlb_valid_f[3:0]),
.fcl_erb_ievld_s1(fcl_erb_ievld_s1),
.fcl_erb_tevld_s1(fcl_erb_tevld_s1),
.fcl_erb_immuevld_s1(fcl_erb_immuevld_s1),
.fcl_erb_inst_issue_d(fcl_erb_inst_issue_d),
.fcl_erb_inst_vld_d1(fcl_erb_inst_vld_d1),
.ifu_lsu_thrid_s(ifu_lsu_thrid_s[1:0]),
.fcl_erb_asi_tid_f(fcl_erb_asi_tid_f[1:0]),
.ifq_fcl_asi_tid_bf(ifq_fcl_asi_tid_bf[1:0]),
.fcl_erb_clear_iferr(fcl_erb_clear_iferr[3:0]),
.fcl_erb_itlbrd_vld_s(fcl_erb_itlbrd_vld_s),
.fcl_erb_itlbrd_data_s(fcl_erb_itlbrd_data_s),
.erd_erc_tagpe_s1(erd_erc_tagpe_s1[3:0]),
.erd_erc_nirpe_s1(erd_erc_nirpe_s1),
.erd_erc_fetpe_s1(erd_erc_fetpe_s1),
.erd_erc_tlbt_pe_s1(erd_erc_tlbt_pe_s1[1:0]),
.erd_erc_tlbd_pe_s1(erd_erc_tlbd_pe_s1[1:0]),
.tlu_lsu_pstate_priv(tlu_lsu_pstate_priv[3:0]),
.tlu_hpstate_priv (tlu_hpstate_priv[3:0]),
.lsu_ifu_dtlb_data_su(lsu_ifu_dtlb_data_su),
.lsu_ifu_dtlb_data_ue(lsu_ifu_dtlb_data_ue),
.lsu_ifu_dtlb_tag_ue(lsu_ifu_dtlb_tag_ue),
.lsu_ifu_dcache_data_perror(lsu_ifu_dcache_data_perror),
.lsu_ifu_dcache_tag_perror(lsu_ifu_dcache_tag_perror),
.lsu_ifu_l2_unc_error(lsu_ifu_l2_unc_error),
.lsu_ifu_l2_corr_error(lsu_ifu_l2_corr_error),
.lsu_ifu_io_error(lsu_ifu_io_error),
.lsu_ifu_error_tid(lsu_ifu_error_tid[1:0]),
.spu_ifu_unc_err_w1(spu_ifu_unc_err_w1),
.spu_ifu_mamem_err_w1(spu_ifu_mamem_err_w1),
.spu_ifu_corr_err_w2(spu_ifu_corr_err_w2),
.spu_ifu_int_w2(spu_ifu_int_w2),
.spu_ifu_ttype_tid_w2(spu_ifu_ttype_tid_w2[1:0]),
.lsu_ifu_inj_ack(lsu_ifu_inj_ack[3:0]),
.ffu_ifu_ecc_ce_w2(ffu_ifu_ecc_ce_w2),
.ffu_ifu_ecc_ue_w2(ffu_ifu_ecc_ue_w2),
.ffu_ifu_inj_ack(ffu_ifu_inj_ack),
.ffu_ifu_tid_w2(ffu_ifu_tid_w2[1:0]),
.exu_ifu_ecc_ce_m(exu_ifu_ecc_ce_m),
.exu_ifu_ecc_ue_m(exu_ifu_ecc_ue_m),
.exu_ifu_inj_ack(exu_ifu_inj_ack),
.ifq_erb_ue_rep(ifq_erb_ue_rep),
.ifq_erb_ce_rep(ifq_erb_ce_rep),
.ifq_erb_l2_ue(ifq_erb_l2_ue),
.ifq_erb_io_ue(ifq_erb_io_ue),
.ifq_erb_ifet_ce(ifq_erb_ifet_ce),
.ifq_erb_l2err_tid(ifq_erb_l2err_tid[1:0]),
.ifq_erb_rdtag_f(ifq_erb_rdtag_f),
.ifq_erb_rdinst_f(ifq_erb_rdinst_f),
.ifq_erb_asi_erren_i2(ifq_erb_asi_erren_i2),
.ifq_erb_asi_errstat_i2(ifq_erb_asi_errstat_i2),
.ifq_erb_asi_errinj_i2(ifq_erb_asi_errinj_i2),
.ifq_erb_asi_erraddr_i2(ifq_erb_asi_erraddr_i2),
.ifq_erb_asi_imask_i2(ifq_erb_asi_imask_i2),
.ifq_erb_asiwr_i2(ifq_erb_asiwr_i2),
.ifq_fcl_asird_bf(ifq_fcl_asird_bf),
.ifq_erb_fwdrd_bf(ifq_erb_fwdrd_bf),
.ifq_erb_asidata_i2(ifq_erb_asidata_i2[31:0]),
.ifq_erb_asiway_f(ifq_erb_asiway_f[1:0]));
// BIST Controller
// sparc_ifu_icd_arr_bist bist(// Outputs
// .Test_fdp_icd_index_bf_0 (bist_ic_index[8:0]),
// .Test_ifq_icd_wrway_bf_0 (bist_ic_way),
// .Test_ifq_icd_wrdata_f_0 ({null_data[135:2],
// bist_ic_data[1:0]}),
// .Test_fcl_icd_rdreq_bf_0 (bist_ic_read),
// .Test_fcl_icd_wrreq_bf_0 (bist_ic_write),
// .Test_ifq_icd_worden_bf_0 (bist_ic_worden),
// .tselect (),
// .tst_done (),
// .fail_h (),
// .scan_out (),
// // Inputs
// .clk (clk),
// .diag_clk(1'b0),
// .rst_l (rst_l),
// .test_h (1'b0),
// .debugz (1'b0),
// .hold_l (1'b1),
// .Test_icd_fdp_topdata_s1_0 (icd_fdp_topdata_s1),
// .Test_icd_fdp_fetdata_s1_0 (icd_fdp_fetdata_s1));
sparc_ifu_mbist mbist(
.mbist_icache_data_in(wsel_mbist_icache_data[67:0]),
.mbist_si (scan0_12),
.mbist_se (se),
.mbist_icache_wdata(mbist_icache_wdata[7:0]),
.mbist_dcache_wdata(mbist_write_data[7:0]),
.mbist_so (scan0_13),
.rclk (rclk),
/*AUTOINST*/
// Outputs
.mbist_dcache_read(mbist_dcache_read),
.mbist_dcache_write(mbist_dcache_write),
.mbist_dcache_word(mbist_dcache_word),
.mbist_dcache_index(mbist_dcache_index[6:0]),
.mbist_dcache_way(mbist_dcache_way[1:0]),
.mbist_icache_read(mbist_icache_read),
.mbist_icache_write(mbist_icache_write),
.mbist_icache_index(mbist_icache_index[7:0]),
.mbist_icache_word(mbist_icache_word),
.mbist_icache_way(mbist_icache_way[1:0]),
.mbist_ifq_run_bist(mbist_ifq_run_bist),
.mbist_done (mbist_done),
.mbist_dcache_fail(mbist_dcache_fail),
.mbist_icache_fail(mbist_icache_fail),
// Inputs
.grst_l (grst_l),
.arst_l (arst_l),
.mbist_start (mbist_start),
.mbist_userdata_mode(mbist_userdata_mode),
.mbist_bisi_mode(mbist_bisi_mode),
.mbist_loop_mode(mbist_loop_mode),
.mbist_loop_on_address(mbist_loop_on_address),
.mbist_stop_on_fail(mbist_stop_on_fail),
.mbist_stop_on_next_fail(mbist_stop_on_next_fail),
.mbist_dcache_data_in(mbist_dcache_data_in[71:0]));
sparc_ifu_sscan sscan(
.so (so0),
.si (scan0_13),
.ifq_sscan_test_data(ifq_sscan_data[3:0]),
.lsu_sscan_test_data(lsu_sscan_data[15:0]),
.tlu_sscan_test_data(tlu_sscan_data[62:0]),
/*AUTOINST*/
// Outputs
.sparc_sscan_so(sparc_sscan_so),
// Inputs
.ctu_sscan_snap(ctu_sscan_snap),
.ctu_sscan_se (ctu_sscan_se),
.ctu_tck (ctu_tck),
.se (se),
.swl_sscan_thrstate(swl_sscan_thrstate[10:0]),
.rclk (rclk));
// floating outputs
sink #(4) s0(.in (ict_itlb_tag0_f[32:29]));
sink #(4) s1(.in (ict_itlb_tag1_f[32:29]));
sink #(4) s2(.in (ict_itlb_tag2_f[32:29]));
sink #(4) s3(.in (ict_itlb_tag3_f[32:29]));
sink #(2) s4(.in (fuse_icd_rid[5:4]));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../srams/rtl" "../../../common/rtl")
// End:
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone register
*/
module wb_async_reg #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
// master side
input wire wbm_clk,
input wire wbm_rst,
input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address
input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
input wire wbm_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
input wire wbm_stb_i, // STB_I strobe input
output wire wbm_ack_o, // ACK_O acknowledge output
output wire wbm_err_o, // ERR_O error output
output wire wbm_rty_o, // RTY_O retry output
input wire wbm_cyc_i, // CYC_I cycle input
// slave side
input wire wbs_clk,
input wire wbs_rst,
output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address
input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
output wire wbs_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
output wire wbs_stb_o, // STB_O strobe output
input wire wbs_ack_i, // ACK_I acknowledge input
input wire wbs_err_i, // ERR_I error input
input wire wbs_rty_i, // RTY_I retry input
output wire wbs_cyc_o // CYC_O cycle output
);
reg [ADDR_WIDTH-1:0] wbm_adr_i_reg = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i_reg = 0;
reg [DATA_WIDTH-1:0] wbm_dat_o_reg = 0;
reg wbm_we_i_reg = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i_reg = 0;
reg wbm_stb_i_reg = 0;
reg wbm_ack_o_reg = 0;
reg wbm_err_o_reg = 0;
reg wbm_rty_o_reg = 0;
reg wbm_cyc_i_reg = 0;
reg wbm_done_sync1 = 0;
reg wbm_done_sync2 = 0;
reg wbm_done_sync3 = 0;
reg [ADDR_WIDTH-1:0] wbs_adr_o_reg = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i_reg = 0;
reg [DATA_WIDTH-1:0] wbs_dat_o_reg = 0;
reg wbs_we_o_reg = 0;
reg [SELECT_WIDTH-1:0] wbs_sel_o_reg = 0;
reg wbs_stb_o_reg = 0;
reg wbs_ack_i_reg = 0;
reg wbs_err_i_reg = 0;
reg wbs_rty_i_reg = 0;
reg wbs_cyc_o_reg = 0;
reg wbs_cyc_o_sync1 = 0;
reg wbs_cyc_o_sync2 = 0;
reg wbs_cyc_o_sync3 = 0;
reg wbs_stb_o_sync1 = 0;
reg wbs_stb_o_sync2 = 0;
reg wbs_stb_o_sync3 = 0;
reg wbs_done_reg = 0;
assign wbm_dat_o = wbm_dat_o_reg;
assign wbm_ack_o = wbm_ack_o_reg;
assign wbm_err_o = wbm_err_o_reg;
assign wbm_rty_o = wbm_rty_o_reg;
assign wbs_adr_o = wbs_adr_o_reg;
assign wbs_dat_o = wbs_dat_o_reg;
assign wbs_we_o = wbs_we_o_reg;
assign wbs_sel_o = wbs_sel_o_reg;
assign wbs_stb_o = wbs_stb_o_reg;
assign wbs_cyc_o = wbs_cyc_o_reg;
// master side logic
always @(posedge wbm_clk) begin
if (wbm_rst) begin
wbm_adr_i_reg <= 0;
wbm_dat_i_reg <= 0;
wbm_dat_o_reg <= 0;
wbm_we_i_reg <= 0;
wbm_sel_i_reg <= 0;
wbm_stb_i_reg <= 0;
wbm_ack_o_reg <= 0;
wbm_err_o_reg <= 0;
wbm_rty_o_reg <= 0;
wbm_cyc_i_reg <= 0;
end else begin
if (wbm_cyc_i_reg & wbm_stb_i_reg) begin
// cycle - hold master
if (wbm_done_sync2 & ~wbm_done_sync3) begin
// end of cycle - store slave
wbm_dat_o_reg <= wbs_dat_i_reg;
wbm_ack_o_reg <= wbs_ack_i_reg;
wbm_err_o_reg <= wbs_err_i_reg;
wbm_rty_o_reg <= wbs_rty_i_reg;
wbm_we_i_reg <= 0;
wbm_stb_i_reg <= 0;
end
end else begin
// idle - store master
wbm_adr_i_reg <= wbm_adr_i;
wbm_dat_i_reg <= wbm_dat_i;
wbm_dat_o_reg <= 0;
wbm_we_i_reg <= wbm_we_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
wbm_sel_i_reg <= wbm_sel_i;
wbm_stb_i_reg <= wbm_stb_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
wbm_ack_o_reg <= 0;
wbm_err_o_reg <= 0;
wbm_rty_o_reg <= 0;
wbm_cyc_i_reg <= wbm_cyc_i;
end
end
// synchronize signals
wbm_done_sync1 <= wbs_done_reg;
wbm_done_sync2 <= wbm_done_sync1;
wbm_done_sync3 <= wbm_done_sync2;
end
// slave side logic
always @(posedge wbs_clk) begin
if (wbs_rst) begin
wbs_adr_o_reg <= 0;
wbs_dat_i_reg <= 0;
wbs_dat_o_reg <= 0;
wbs_we_o_reg <= 0;
wbs_sel_o_reg <= 0;
wbs_stb_o_reg <= 0;
wbs_ack_i_reg <= 0;
wbs_err_i_reg <= 0;
wbs_rty_i_reg <= 0;
wbs_cyc_o_reg <= 0;
wbs_done_reg <= 0;
end else begin
if (wbs_ack_i | wbs_err_i | wbs_rty_i) begin
// end of cycle - store slave
wbs_dat_i_reg <= wbs_dat_i;
wbs_ack_i_reg <= wbs_ack_i;
wbs_err_i_reg <= wbs_err_i;
wbs_rty_i_reg <= wbs_rty_i;
wbs_we_o_reg <= 0;
wbs_stb_o_reg <= 0;
wbs_done_reg <= 1;
end else if (wbs_stb_o_sync2 & ~wbs_stb_o_sync3) begin
// beginning of cycle - store master
wbs_adr_o_reg <= wbm_adr_i_reg;
wbs_dat_i_reg <= 0;
wbs_dat_o_reg <= wbm_dat_i_reg;
wbs_we_o_reg <= wbm_we_i_reg;
wbs_sel_o_reg <= wbm_sel_i_reg;
wbs_stb_o_reg <= wbm_stb_i_reg;
wbs_ack_i_reg <= 0;
wbs_err_i_reg <= 0;
wbs_rty_i_reg <= 0;
wbs_cyc_o_reg <= wbm_cyc_i_reg;
wbs_done_reg <= 0;
end else if (~wbs_cyc_o_sync2 & wbs_cyc_o_sync3) begin
// cyc deassert
wbs_adr_o_reg <= 0;
wbs_dat_i_reg <= 0;
wbs_dat_o_reg <= 0;
wbs_we_o_reg <= 0;
wbs_sel_o_reg <= 0;
wbs_stb_o_reg <= 0;
wbs_ack_i_reg <= 0;
wbs_err_i_reg <= 0;
wbs_rty_i_reg <= 0;
wbs_cyc_o_reg <= 0;
wbs_done_reg <= 0;
end
end
// synchronize signals
wbs_cyc_o_sync1 <= wbm_cyc_i_reg;
wbs_cyc_o_sync2 <= wbs_cyc_o_sync1;
wbs_cyc_o_sync3 <= wbs_cyc_o_sync2;
wbs_stb_o_sync1 <= wbm_stb_i_reg;
wbs_stb_o_sync2 <= wbs_stb_o_sync1;
wbs_stb_o_sync3 <= wbs_stb_o_sync2;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_ad9434_pnmon (
// adc interface
adc_clk,
adc_data,
// pn interface
adc_pnseq_sel,
adc_pn_err,
adc_pn_oos);
// adc interface
input adc_clk;
input [47:0] adc_data;
// pn out sync and error
input [ 3:0] adc_pnseq_sel;
output adc_pn_err;
output adc_pn_oos;
// internal registers
reg [47:0] adc_pn_data_pn = 'd0;
// internal signals
wire [47:0] adc_pn_data_pn_s;
wire [47:0] adc_data_inv_s;
// prbs pn9 function
function [47:0] pn9;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[8] ^ din[4];
dout[46] = din[7] ^ din[3];
dout[45] = din[6] ^ din[2];
dout[44] = din[5] ^ din[1];
dout[43] = din[4] ^ din[0];
dout[42] = din[3] ^ din[8] ^ din[4];
dout[41] = din[2] ^ din[7] ^ din[3];
dout[40] = din[1] ^ din[6] ^ din[2];
dout[39] = din[0] ^ din[5] ^ din[1];
dout[38] = din[8] ^ din[0];
dout[37] = din[7] ^ din[8] ^ din[4];
dout[36] = din[6] ^ din[7] ^ din[3];
dout[35] = din[5] ^ din[6] ^ din[2];
dout[34] = din[4] ^ din[5] ^ din[1];
dout[33] = din[3] ^ din[4] ^ din[0];
dout[32] = din[2] ^ din[3] ^ din[8] ^ din[4];
dout[31] = din[1] ^ din[2] ^ din[7] ^ din[3];
dout[30] = din[0] ^ din[1] ^ din[6] ^ din[2];
dout[29] = din[8] ^ din[0] ^ din[4] ^ din[5] ^ din[1];
dout[28] = din[7] ^ din[8] ^ din[3] ^ din[0];
dout[27] = din[6] ^ din[7] ^ din[2] ^ din[8] ^ din[4];
dout[26] = din[5] ^ din[6] ^ din[1] ^ din[7] ^ din[3];
dout[25] = din[4] ^ din[5] ^ din[0] ^ din[6] ^ din[2];
dout[24] = din[3] ^ din[8] ^ din[5] ^ din[1];
dout[23] = din[2] ^ din[4] ^ din[7] ^ din[0];
dout[22] = din[1] ^ din[3] ^ din[6] ^ din[8] ^ din[4];
dout[21] = din[0] ^ din[2] ^ din[5] ^ din[7] ^ din[3];
dout[20] = din[8] ^ din[1] ^ din[6] ^ din[2];
dout[19] = din[7] ^ din[0] ^ din[5] ^ din[1];
dout[18] = din[6] ^ din[8] ^ din[0];
dout[17] = din[5] ^ din[7] ^ din[8] ^ din[4];
dout[16] = din[4] ^ din[6] ^ din[7] ^ din[3];
dout[15] = din[3] ^ din[5] ^ din[6] ^ din[2];
dout[14] = din[2] ^ din[4] ^ din[5] ^ din[1];
dout[13] = din[1] ^ din[3] ^ din[4] ^ din[0];
dout[12] = din[0] ^ din[2] ^ din[3] ^ din[8] ^ din[4];
dout[11] = din[8] ^ din[1] ^ din[2] ^ din[4] ^ din[7] ^ din[3];
dout[10] = din[7] ^ din[0] ^ din[1] ^ din[3] ^ din[6] ^ din[2];
dout[9] = din[6] ^ din[8] ^ din[0] ^ din[2] ^ din[4] ^ din[5] ^ din[1];
dout[8] = din[5] ^ din[7] ^ din[8] ^ din[1] ^ din[3] ^ din[0];
dout[7] = din[6] ^ din[7] ^ din[0] ^ din[2] ^ din[8];
dout[6] = din[5] ^ din[6] ^ din[8] ^ din[1] ^ din[4] ^ din[7];
dout[5] = din[4] ^ din[5] ^ din[7] ^ din[0] ^ din[3] ^ din[6];
dout[4] = din[3] ^ din[6] ^ din[8] ^ din[2] ^ din[5];
dout[3] = din[2] ^ din[4] ^ din[5] ^ din[7] ^ din[1];
dout[2] = din[1] ^ din[4] ^ din[3] ^ din[6] ^ din[0];
dout[1] = din[0] ^ din[3] ^ din[2] ^ din[5] ^ din[8] ^ din[4];
dout[0] = din[8] ^ din[2] ^ din[1] ^ din[7] ^ din[3];
pn9 = dout;
end
endfunction
// prbs pn23 function
function [47:0] pn23;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[22] ^ din[17];
dout[46] = din[21] ^ din[16];
dout[45] = din[20] ^ din[15];
dout[44] = din[19] ^ din[14];
dout[43] = din[18] ^ din[13];
dout[42] = din[17] ^ din[12];
dout[41] = din[16] ^ din[11];
dout[40] = din[15] ^ din[10];
dout[39] = din[14] ^ din[9];
dout[38] = din[13] ^ din[8];
dout[37] = din[12] ^ din[7];
dout[36] = din[11] ^ din[6];
dout[35] = din[10] ^ din[5];
dout[34] = din[9] ^ din[4];
dout[33] = din[8] ^ din[3];
dout[32] = din[7] ^ din[2];
dout[31] = din[6] ^ din[1];
dout[30] = din[5] ^ din[0];
dout[29] = din[4] ^ din[22] ^ din[17];
dout[28] = din[3] ^ din[21] ^ din[16];
dout[27] = din[2] ^ din[20] ^ din[15];
dout[26] = din[1] ^ din[19] ^ din[14];
dout[25] = din[0] ^ din[18] ^ din[13];
dout[24] = din[22] ^ din[12];
dout[23] = din[21] ^ din[11];
dout[22] = din[20] ^ din[10];
dout[21] = din[19] ^ din[9];
dout[20] = din[18] ^ din[8];
dout[19] = din[17] ^ din[7];
dout[18] = din[16] ^ din[6];
dout[17] = din[15] ^ din[5];
dout[16] = din[14] ^ din[4];
dout[15] = din[13] ^ din[3];
dout[14] = din[12] ^ din[2];
dout[13] = din[11] ^ din[1];
dout[12] = din[10] ^ din[0];
dout[11] = din[9] ^ din[22] ^ din[17];
dout[10] = din[8] ^ din[21] ^ din[16];
dout[9] = din[7] ^ din[20] ^ din[15];
dout[8] = din[6] ^ din[19] ^ din[14];
dout[7] = din[5] ^ din[18] ^ din[13];
dout[6] = din[4] ^ din[17] ^ din[12];
dout[5] = din[3] ^ din[16] ^ din[11];
dout[4] = din[2] ^ din[15] ^ din[10];
dout[3] = din[1] ^ din[14] ^ din[9];
dout[2] = din[0] ^ din[13] ^ din[8];
dout[1] = din[22] ^ din[12] ^ din[17] ^ din[7];
dout[0] = din[21] ^ din[11] ^ din[16] ^ din[6];
pn23 = dout;
end
endfunction
// pn sequence selection
assign adc_data_inv_s = {adc_data[11:0], adc_data[23:12], adc_data[35:24], adc_data[47:36]};
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_data_inv_s : adc_pn_data_pn;
always @(posedge adc_clk) begin
if(adc_pnseq_sel == 4'b0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(48)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_data_inv_s),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
|
`define SMV
`define SUBDIR
`ifdef SUBDIR
`include "ovl_always_on_edge.v"
`else
`include "ovl_ported/ovl_always_on_edge.v"
`endif
`define OVL_INIT_REG
/*
* File: ovl_always_on_edge_tb.v
* Test bench for ovl_alwaysZ_on_edge.v
* Includes assertions for verification
* Created: 2013-10-10
*
* Verified for both vlog95/ovl_always_on_edge_logic.v and vlog95/ovl_always_on_edge_logic2.v.
*/
module main();
// Inputs to DUT
reg clk;
reg reset;
reg enable;
reg sampling_event;
reg test_expr;
// Outputs of DUT
//In the DUT module, this width is parameterized by OVL_FIRE_WIDTH-1.
wire [2:0] fire;
ovl_always_on_edge ovl_aoe_t(.clock(clk),
.reset(reset),
.enable(enable),
.sampling_event(sampling_event),
.test_expr(test_expr),
.fire(fire),
.edge_type(1),
.property_type(3),
.clock_edge(1),
.reset_polarity(0),
.gating_type(0),
.severity_level(3));
initial begin
clk = 0;
reset = 1;
enable = 0;
sampling_event = 0;
test_expr = 0;
end
always begin
clk = #5 !clk;
end
endmodule // main
/* ***************** SMV Assertions ******************
//SMV-Assertions
# The ovl_always_on_edge is an assertion module that checks if sampling_event has a rising edge, then test_expr will be high. The spec states that if this check fails, then ovl_always_on_edge will "fire" an event. i.e. "~(pos_edge_sampling_event -> test_expr) -> X(fire)". This can be rewritten "(pos_edge_sampling_event && ~test_expr) -> X(fire)".
# The first set of assertions verify that we correctly understand the semantics of the code. Using the variables in the "if" statement, these assertions verify that fire_2state is triggered exactly under the set of conditions that we expect.
# The code works as we expect. If the conditions of the "if" statement are satisfied, fire_2state is triggered.
\follow_code : assert ~\ovl_aoe_t .\reset_n -> X(G((\ovl_aoe_t .\reset_n && \ovl_aoe_t .\sampling_event && ~\ovl_aoe_t .\test_expr && ~\ovl_aoe_t .\sampling_event_prev && \ovl_aoe_t .\r_reset_n )-> X(\ovl_aoe_t .\fire_2state )));
# The code works as we epxect. fire_2state never fires without a rising edge of sampling event.
\never_fires_wo_rising_sampling_edge : assert ~\ovl_aoe_t .\reset_n -> X(G((\ovl_aoe_t .\sampling_event_prev || ~\ovl_aoe_t .\sampling_event ) -> X(~\ovl_aoe_t .\fire_2state )));
# The code works as we expect. fire_2state never fires without test_expr low.
\never_fires_wo_test_expr : assert ~\ovl_aoe_t .\reset_n -> X(G(\ovl_aoe_t .\test_expr -> X(~\ovl_aoe_t .\fire_2state )));
# The second set of assertions verify the code correctly implements the spec as given by the timing diagram "assert_always_on_edge" for a rising edge, pg 14 of assert_timing_diagram.pdf. These assertions use only the variables appearing in the timing diagram, plus reset.
# test_expr should always be high on a rising edge of sampling_event. If it is not, an event ("fire_2state") is triggered.
\trigger_if_low_test_and_rising_sampling_edge : assert reset -> X(G((~\reset && ~\sampling_event ) -> X((~\reset && \sampling_event && ~\test_expr ) -> X(\fire = 1))));
# Although not given in the spec, we would also like to verify that an event is triggered only when test_expr is low on a rising edge of sampling_event.
# An event is not triggered if there is no rising edge.
\never_fires_wo_rising_sampling_edge1 : assert reset -> X(G((~\sampling_event ) -> X(\fire = 0)));
\never_fires_wo_rising_sampling_edge2 : assert reset -> X(G((\sampling_event ) -> X(X(\fire = 0))));
# An event is not triggered if test_expr is high.
\never_fires_wo_test_expr1 : assert reset -> X(G(\test_expr -> X(\fire = 0)));
//SMV-Assertions
*/
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:38:19 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch2_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, r_mode,
ready_cordic, overflow_flag, underflow_flag, data_output );
input [63:0] data_in;
input [1:0] shift_region_flag;
input [1:0] r_mode;
output [63:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag;
wire d_ff1_operation_out, sel_mux_1_reg, d_ff3_sign_out, sel_mux_3_reg,
data_output2_63_, cordic_FSM_state_next_1_,
add_subt_module_sign_final_result, add_subt_module_intAS,
add_subt_module_FSM_selector_D, add_subt_module_FSM_exp_operation_A_S,
add_subt_module_add_overflow_flag, add_subt_module_FSM_selector_C,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1961, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284,
n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434,
n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444,
n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454,
n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464,
n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474,
n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484,
n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494,
n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, DP_OP_92J138_122_9081_n26,
DP_OP_92J138_122_9081_n25, DP_OP_92J138_122_9081_n24,
DP_OP_92J138_122_9081_n23, DP_OP_92J138_122_9081_n22,
DP_OP_92J138_122_9081_n21, DP_OP_92J138_122_9081_n20,
DP_OP_92J138_122_9081_n19, DP_OP_92J138_122_9081_n18,
DP_OP_92J138_122_9081_n17, DP_OP_92J138_122_9081_n16,
DP_OP_92J138_122_9081_n11, DP_OP_92J138_122_9081_n10,
DP_OP_92J138_122_9081_n9, DP_OP_92J138_122_9081_n8,
DP_OP_92J138_122_9081_n7, DP_OP_92J138_122_9081_n6,
DP_OP_92J138_122_9081_n5, DP_OP_92J138_122_9081_n4,
DP_OP_92J138_122_9081_n3, DP_OP_92J138_122_9081_n2,
DP_OP_92J138_122_9081_n1, DP_OP_95J138_125_7728_n114,
DP_OP_95J138_125_7728_n113, DP_OP_95J138_125_7728_n112,
DP_OP_95J138_125_7728_n111, DP_OP_95J138_125_7728_n110,
DP_OP_95J138_125_7728_n109, DP_OP_95J138_125_7728_n108,
DP_OP_95J138_125_7728_n107, DP_OP_95J138_125_7728_n106,
DP_OP_95J138_125_7728_n105, DP_OP_95J138_125_7728_n104,
DP_OP_95J138_125_7728_n103, DP_OP_95J138_125_7728_n102,
DP_OP_95J138_125_7728_n101, DP_OP_95J138_125_7728_n100,
DP_OP_95J138_125_7728_n99, DP_OP_95J138_125_7728_n98,
DP_OP_95J138_125_7728_n97, DP_OP_95J138_125_7728_n96,
DP_OP_95J138_125_7728_n95, DP_OP_95J138_125_7728_n94,
DP_OP_95J138_125_7728_n93, DP_OP_95J138_125_7728_n92,
DP_OP_95J138_125_7728_n91, DP_OP_95J138_125_7728_n90,
DP_OP_95J138_125_7728_n89, DP_OP_95J138_125_7728_n88,
DP_OP_95J138_125_7728_n87, DP_OP_95J138_125_7728_n86,
DP_OP_95J138_125_7728_n85, DP_OP_95J138_125_7728_n84,
DP_OP_95J138_125_7728_n83, DP_OP_95J138_125_7728_n82,
DP_OP_95J138_125_7728_n81, DP_OP_95J138_125_7728_n80,
DP_OP_95J138_125_7728_n79, DP_OP_95J138_125_7728_n78,
DP_OP_95J138_125_7728_n77, DP_OP_95J138_125_7728_n76,
DP_OP_95J138_125_7728_n75, DP_OP_95J138_125_7728_n74,
DP_OP_95J138_125_7728_n73, DP_OP_95J138_125_7728_n72,
DP_OP_95J138_125_7728_n71, DP_OP_95J138_125_7728_n70,
DP_OP_95J138_125_7728_n69, DP_OP_95J138_125_7728_n68,
DP_OP_95J138_125_7728_n67, DP_OP_95J138_125_7728_n66,
DP_OP_95J138_125_7728_n65, DP_OP_95J138_125_7728_n64,
DP_OP_95J138_125_7728_n63, DP_OP_95J138_125_7728_n62,
DP_OP_95J138_125_7728_n61, DP_OP_95J138_125_7728_n60,
DP_OP_95J138_125_7728_n55, DP_OP_95J138_125_7728_n54,
DP_OP_95J138_125_7728_n53, DP_OP_95J138_125_7728_n52,
DP_OP_95J138_125_7728_n51, DP_OP_95J138_125_7728_n50,
DP_OP_95J138_125_7728_n49, DP_OP_95J138_125_7728_n48,
DP_OP_95J138_125_7728_n47, DP_OP_95J138_125_7728_n46,
DP_OP_95J138_125_7728_n45, DP_OP_95J138_125_7728_n44,
DP_OP_95J138_125_7728_n43, DP_OP_95J138_125_7728_n42,
DP_OP_95J138_125_7728_n41, DP_OP_95J138_125_7728_n40,
DP_OP_95J138_125_7728_n39, DP_OP_95J138_125_7728_n38,
DP_OP_95J138_125_7728_n37, DP_OP_95J138_125_7728_n36,
DP_OP_95J138_125_7728_n35, DP_OP_95J138_125_7728_n34,
DP_OP_95J138_125_7728_n33, DP_OP_95J138_125_7728_n32,
DP_OP_95J138_125_7728_n31, DP_OP_95J138_125_7728_n30,
DP_OP_95J138_125_7728_n29, DP_OP_95J138_125_7728_n28,
DP_OP_95J138_125_7728_n27, DP_OP_95J138_125_7728_n26,
DP_OP_95J138_125_7728_n25, DP_OP_95J138_125_7728_n24,
DP_OP_95J138_125_7728_n23, DP_OP_95J138_125_7728_n22,
DP_OP_95J138_125_7728_n21, DP_OP_95J138_125_7728_n20,
DP_OP_95J138_125_7728_n19, DP_OP_95J138_125_7728_n18,
DP_OP_95J138_125_7728_n17, DP_OP_95J138_125_7728_n16,
DP_OP_95J138_125_7728_n15, DP_OP_95J138_125_7728_n14,
DP_OP_95J138_125_7728_n13, DP_OP_95J138_125_7728_n12,
DP_OP_95J138_125_7728_n11, DP_OP_95J138_125_7728_n10,
DP_OP_95J138_125_7728_n9, DP_OP_95J138_125_7728_n8,
DP_OP_95J138_125_7728_n7, DP_OP_95J138_125_7728_n6,
DP_OP_95J138_125_7728_n5, DP_OP_95J138_125_7728_n4,
DP_OP_95J138_125_7728_n3, DP_OP_95J138_125_7728_n2,
DP_OP_95J138_125_7728_n1, intadd_374_CI, intadd_374_SUM_2_,
intadd_374_SUM_1_, intadd_374_SUM_0_, intadd_374_n3, intadd_374_n2,
intadd_374_n1, intadd_375_CI, intadd_375_SUM_2_, intadd_375_SUM_1_,
intadd_375_SUM_0_, intadd_375_n3, intadd_375_n2, intadd_375_n1, n2950,
n2954, n2955, n2956, n2957, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3055, n3056,
n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065, n3066,
n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075, n3076,
n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085, n3086,
n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095, n3096,
n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105, n3106,
n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115, n3116,
n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125, n3126,
n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135, n3136,
n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145, n3146,
n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155, n3156,
n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165, n3166,
n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175, n3176,
n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185, n3186,
n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195, n3196,
n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205, n3206,
n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215, n3216,
n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225, n3226,
n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235, n3236,
n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245, n3246,
n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255, n3256,
n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265, n3266,
n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275, n3276,
n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285, n3286,
n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295, n3296,
n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305, n3306,
n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315, n3316,
n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325, n3326,
n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335, n3336,
n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345, n3346,
n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355, n3356,
n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365, n3366,
n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375, n3376,
n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385, n3386,
n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395, n3396,
n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405, n3406,
n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415, n3416,
n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425, n3426,
n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435, n3436,
n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445, n3446,
n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455, n3456,
n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465, n3466,
n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475, n3476,
n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485, n3486,
n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495, n3496,
n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505, n3506,
n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515, n3516,
n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525, n3526,
n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535, n3536,
n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545, n3546,
n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555, n3556,
n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565, n3566,
n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575, n3576,
n3577, n3578, n3579, n3580, n3581, n3582, n3584, n3585, n3586, n3587,
n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595, n3596, n3597,
n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605, n3606, n3607,
n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615, n3616, n3617,
n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625, n3626, n3627,
n3628, n3629, n3630, n3632, n3633, n3634, n3635, n3636, n3637, n3638,
n3639, n3640, n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648,
n3649, n3650, n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658,
n3659, n3660, n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668,
n3669, n3670, n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678,
n3679, n3680, n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688,
n3689, n3690, n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698,
n3699, n3700, n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708,
n3709, n3710, n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718,
n3719, n3720, n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728,
n3729, n3730, n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738,
n3739, n3740, n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748,
n3749, n3750, n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758,
n3759, n3760, n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768,
n3769, n3770, n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778,
n3779, n3780, n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788,
n3789, n3790, n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798,
n3799, n3800, n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808,
n3809, n3810, n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818,
n3819, n3820, n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828,
n3829, n3830, n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838,
n3839, n3840, n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848,
n3849, n3850, n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858,
n3859, n3860, n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868,
n3869, n3870, n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878,
n3879, n3880, n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888,
n3889, n3890, n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898,
n3899, n3900, n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908,
n3909, n3910, n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918,
n3919, n3920, n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928,
n3929, n3930, n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938,
n3939, n3940, n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948,
n3949, n3950, n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958,
n3959, n3960, n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968,
n3969, n3970, n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978,
n3979, n3980, n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988,
n3989, n3990, n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998,
n3999, n4000, n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008,
n4009, n4010, n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018,
n4019, n4020, n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028,
n4029, n4030, n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038,
n4039, n4040, n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048,
n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058,
n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068,
n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078,
n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088,
n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098,
n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108,
n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118,
n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128,
n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138,
n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148,
n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158,
n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168,
n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178,
n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188,
n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198,
n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208,
n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218,
n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228,
n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238,
n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248,
n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258,
n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4269,
n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279,
n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289,
n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299,
n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309,
n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319,
n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329,
n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339,
n4340, n4341, n4342, n4343, n4344, n4346, n4347, n4348, n4349, n4350,
n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360,
n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370,
n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380,
n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390,
n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400,
n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410,
n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420,
n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430,
n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440,
n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450,
n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4461,
n4462, n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471,
n4472, n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481,
n4482, n4483, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513,
n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523,
n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533,
n4534, n4535, n4536, n4538, n4539, n4540, n4541, n4542, n4543, n4544,
n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554,
n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564,
n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574,
n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584,
n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594,
n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604,
n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614,
n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624,
n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634,
n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644,
n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654,
n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664,
n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674,
n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684,
n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694,
n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704,
n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714,
n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724,
n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734,
n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744,
n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754,
n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764,
n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774,
n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784,
n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794,
n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804,
n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814,
n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824,
n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834,
n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844,
n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854,
n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864,
n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874,
n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884,
n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894,
n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904,
n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914,
n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924,
n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934,
n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944,
n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954,
n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964,
n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974,
n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984,
n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994,
n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004,
n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014,
n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024,
n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034,
n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044,
n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054,
n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064,
n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074,
n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084,
n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094,
n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104,
n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114,
n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124,
n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134,
n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144,
n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154,
n5155, n5156, n5157, n5158, n5159;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:0] cont_iter_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] d_ff_Yn;
wire [63:0] d_ff_Zn;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [63:0] result_add_subt;
wire [62:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
wire [54:0] add_subt_module_S_A_S_Oper_A;
wire [54:0] add_subt_module_Sgf_normalized_result;
wire [54:0] add_subt_module_Add_Subt_result;
wire [5:0] add_subt_module_LZA_output;
wire [10:0] add_subt_module_S_Oper_A_exp;
wire [10:0] add_subt_module_exp_oper_result;
wire [62:0] add_subt_module_DmP;
wire [62:0] add_subt_module_DMP;
wire [63:0] add_subt_module_intDY;
wire [63:0] add_subt_module_intDX;
wire [1:0] add_subt_module_FSM_selector_B;
wire [3:0] add_subt_module_FS_Module_state_reg;
wire [10:0] add_subt_module_Exp_Operation_Module_Data_S;
wire [54:0] add_subt_module_Add_Subt_Sgf_module_S_to_D;
wire [107:0] add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array;
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(n2917), .CK(clk), .RN(n5158), .Q(d_ff1_Z[62])
);
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(n2916), .CK(clk), .RN(n5158), .Q(d_ff1_Z[61])
);
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(n2915), .CK(clk), .RN(n5158), .Q(d_ff1_Z[60])
);
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(n2914), .CK(clk), .RN(n5158), .Q(d_ff1_Z[59])
);
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(n2913), .CK(clk), .RN(n5158), .Q(d_ff1_Z[58])
);
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(n2912), .CK(clk), .RN(n5158), .Q(d_ff1_Z[57])
);
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(n2911), .CK(clk), .RN(n5158), .Q(d_ff1_Z[56])
);
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(n2910), .CK(clk), .RN(n5158), .Q(d_ff1_Z[55])
);
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(n2909), .CK(clk), .RN(n5158), .Q(d_ff1_Z[54])
);
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(n2908), .CK(clk), .RN(n5157), .Q(d_ff1_Z[53])
);
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(n2907), .CK(clk), .RN(n5157), .Q(d_ff1_Z[52])
);
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(n2906), .CK(clk), .RN(n5157), .Q(d_ff1_Z[51])
);
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(n2905), .CK(clk), .RN(n5157), .Q(d_ff1_Z[50])
);
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(n2904), .CK(clk), .RN(n5157), .Q(d_ff1_Z[49])
);
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(n2903), .CK(clk), .RN(n5157), .Q(d_ff1_Z[48])
);
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(n2902), .CK(clk), .RN(n5157), .Q(d_ff1_Z[47])
);
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(n2901), .CK(clk), .RN(n5157), .Q(d_ff1_Z[46])
);
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(n2900), .CK(clk), .RN(n5157), .Q(d_ff1_Z[45])
);
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(n2899), .CK(clk), .RN(n5157), .Q(d_ff1_Z[44])
);
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(n2898), .CK(clk), .RN(n5157), .Q(d_ff1_Z[43])
);
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(n2897), .CK(clk), .RN(n5157), .Q(d_ff1_Z[42])
);
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(n2896), .CK(clk), .RN(n5156), .Q(d_ff1_Z[41])
);
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(n2895), .CK(clk), .RN(n5156), .Q(d_ff1_Z[40])
);
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(n2894), .CK(clk), .RN(n5156), .Q(d_ff1_Z[39])
);
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(n2893), .CK(clk), .RN(n5156), .Q(d_ff1_Z[38])
);
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(n2892), .CK(clk), .RN(n5156), .Q(d_ff1_Z[37])
);
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(n2891), .CK(clk), .RN(n5156), .Q(d_ff1_Z[36])
);
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(n2890), .CK(clk), .RN(n5156), .Q(d_ff1_Z[35])
);
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(n2889), .CK(clk), .RN(n5156), .Q(d_ff1_Z[34])
);
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(n2888), .CK(clk), .RN(n5156), .Q(d_ff1_Z[33])
);
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(n2887), .CK(clk), .RN(n5156), .Q(d_ff1_Z[32])
);
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n2886), .CK(clk), .RN(n5156), .Q(d_ff1_Z[31])
);
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n2885), .CK(clk), .RN(n5156), .Q(d_ff1_Z[30])
);
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n2884), .CK(clk), .RN(n5155), .Q(d_ff1_Z[29])
);
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n2883), .CK(clk), .RN(n5155), .Q(d_ff1_Z[28])
);
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n2882), .CK(clk), .RN(n5155), .Q(d_ff1_Z[27])
);
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n2881), .CK(clk), .RN(n5155), .Q(d_ff1_Z[26])
);
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n2880), .CK(clk), .RN(n5155), .Q(d_ff1_Z[25])
);
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n2879), .CK(clk), .RN(n5155), .Q(d_ff1_Z[24])
);
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n2878), .CK(clk), .RN(n5155), .Q(d_ff1_Z[23])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n2877), .CK(clk), .RN(n5155), .Q(d_ff1_Z[22])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n2876), .CK(clk), .RN(n5155), .Q(d_ff1_Z[21])
);
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(n2875), .CK(clk), .RN(n5155), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(n2874), .CK(clk), .RN(n5155), .Q(d_ff1_Z[19])
);
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n2873), .CK(clk), .RN(n5155), .Q(d_ff1_Z[18])
);
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n2872), .CK(clk), .RN(n5154), .Q(d_ff1_Z[17])
);
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n2871), .CK(clk), .RN(n5154), .Q(d_ff1_Z[16])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n2870), .CK(clk), .RN(n5154), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n2869), .CK(clk), .RN(n5154), .Q(d_ff1_Z[14])
);
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n2868), .CK(clk), .RN(n5154), .Q(d_ff1_Z[13])
);
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n2867), .CK(clk), .RN(n5154), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n2866), .CK(clk), .RN(n5154), .Q(d_ff1_Z[11])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n2865), .CK(clk), .RN(n5154), .Q(d_ff1_Z[10])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n2864), .CK(clk), .RN(n5154), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n2863), .CK(clk), .RN(n5154), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n2862), .CK(clk), .RN(n5154), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n2861), .CK(clk), .RN(n5154), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n2860), .CK(clk), .RN(n5153), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n2859), .CK(clk), .RN(n5153), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n2858), .CK(clk), .RN(n5153), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n2857), .CK(clk), .RN(n5153), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n2856), .CK(clk), .RN(n5153), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n2855), .CK(clk), .RN(n5153), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(n2854), .CK(clk), .RN(n5153), .Q(d_ff1_Z[63])
);
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(n2850), .CK(clk), .RN(n5153), .Q(
d_ff3_LUT_out[56]) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(n2849), .CK(clk), .RN(n5153), .Q(
d_ff3_LUT_out[55]) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(n2848), .CK(clk), .RN(n5153), .Q(
d_ff3_LUT_out[54]) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(n2847), .CK(clk), .RN(n5153), .Q(
d_ff3_LUT_out[53]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n2846), .CK(clk), .RN(n5153), .Q(
d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(n2845), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[50]) );
DFFRXLTS reg_LUT_Q_reg_49_ ( .D(n2844), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[49]) );
DFFRXLTS reg_LUT_Q_reg_47_ ( .D(n2842), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[47]) );
DFFRXLTS reg_LUT_Q_reg_46_ ( .D(n2841), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[46]) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(n2840), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[45]) );
DFFRXLTS reg_LUT_Q_reg_44_ ( .D(n2839), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[44]) );
DFFRXLTS reg_LUT_Q_reg_43_ ( .D(n2838), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[43]) );
DFFRXLTS reg_LUT_Q_reg_42_ ( .D(n2837), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[42]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(n2836), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[41]) );
DFFRXLTS reg_LUT_Q_reg_40_ ( .D(n2835), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[40]) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(n2834), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_38_ ( .D(n2833), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[38]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(n2832), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_36_ ( .D(n2831), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[36]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(n2830), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[35]) );
DFFRXLTS reg_LUT_Q_reg_34_ ( .D(n2829), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[34]) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(n2828), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[33]), .QN(n5077) );
DFFRXLTS reg_LUT_Q_reg_32_ ( .D(n2827), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[32]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(n2826), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[31]) );
DFFRXLTS reg_LUT_Q_reg_30_ ( .D(n2825), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[30]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(n2824), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[29]) );
DFFRXLTS reg_LUT_Q_reg_28_ ( .D(n2823), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[28]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(n2822), .CK(clk), .RN(n5151), .Q(
d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(n2821), .CK(clk), .RN(n5159), .Q(
d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(n2818), .CK(clk), .RN(n5159), .Q(
d_ff3_LUT_out[23]), .QN(n5074) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(n2817), .CK(clk), .RN(n5118), .Q(
d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n2816), .CK(clk), .RN(n5120), .Q(
d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(n2815), .CK(clk), .RN(n5134), .Q(
d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(n2814), .CK(clk), .RN(n5135), .Q(
d_ff3_LUT_out[19]), .QN(n5078) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(n2813), .CK(clk), .RN(n5136), .Q(
d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(n2812), .CK(clk), .RN(n5118), .Q(
d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(n2811), .CK(clk), .RN(n5137), .Q(
d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(n2810), .CK(clk), .RN(n5138), .Q(
d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(n2809), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(n2808), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n2807), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(n2806), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(n2805), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n2804), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n2803), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[8]), .QN(n5076) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(n2802), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(n2801), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[6]), .QN(n5073) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(n2800), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(n2799), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(n2797), .CK(clk), .RN(n5115), .Q(
d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(n2796), .CK(clk), .RN(n5133), .Q(
d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(n2795), .CK(clk), .RN(n5133), .Q(
d_ff3_LUT_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(n2093), .CK(clk), .RN(n5151), .Q(
d_ff3_sh_y_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(n2094), .CK(clk), .RN(n5158), .Q(
d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(n2095), .CK(clk), .RN(n5114), .Q(
d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(n2096), .CK(clk), .RN(n5131), .Q(
d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(n2097), .CK(clk), .RN(n5132), .Q(
d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(n2099), .CK(clk), .RN(n5117), .Q(
d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(n2100), .CK(clk), .RN(n5139), .Q(
d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(n2101), .CK(clk), .RN(n5140), .Q(
d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(n2102), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(n2103), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(n2772), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(n2773), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(n2774), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(n2775), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(n2776), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(n2777), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(n2778), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[56]), .QN(n5075) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(n2779), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(n2780), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(n2781), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(n2782), .CK(clk), .RN(n5148), .Q(
d_ff3_sh_x_out[52]) );
DFFRXLTS reg_ch_mux_1_Q_reg_0_ ( .D(n2853), .CK(clk), .RN(n5148), .Q(
sel_mux_1_reg), .QN(n5010) );
DFFRXLTS reg_ch_mux_2_Q_reg_0_ ( .D(n2852), .CK(clk), .RN(n5148), .Q(
sel_mux_2_reg[0]), .QN(n4985) );
DFFRXLTS reg_ch_mux_2_Q_reg_1_ ( .D(n2851), .CK(clk), .RN(n5148), .Q(
sel_mux_2_reg[1]), .QN(n4984) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n2668), .CK(clk), .RN(n5148), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(
n2649), .CK(clk), .RN(n3015), .QN(n2967) );
DFFRXLTS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(
n2623), .CK(clk), .RN(n5080), .QN(n2968) );
DFFRXLTS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
n2618), .CK(clk), .RN(n3015), .QN(n2963) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ (
.D(n2592), .CK(clk), .RN(n2961), .Q(add_subt_module_LZA_output[0]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ (
.D(n2589), .CK(clk), .RN(n5105), .Q(add_subt_module_LZA_output[5]),
.QN(n5069) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(n2794), .CK(clk), .RN(n5148), .Q(
d_ff3_sh_x_out[63]) );
DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(n2666), .CK(clk), .RN(n5148), .Q(
d_ff_Yn[63]), .QN(n5072) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(n2091), .CK(clk), .RN(n5147), .Q(
d_ff3_sh_y_out[63]) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(n1961), .CK(clk), .RN(n5147), .Q(
data_output[63]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(n2665), .CK(clk), .RN(n5147), .Q(
d_ff_Zn[63]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(n2533), .CK(clk), .RN(n5147), .Q(
d_ff_Zn[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_62_ ( .D(n2222), .CK(clk), .RN(n5147),
.Q(d_ff2_Z[62]) );
DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(n2532), .CK(clk), .RN(n5147), .Q(
d_ff_Yn[62]), .QN(n5068) );
DFFRXLTS d_ff5_Q_reg_62_ ( .D(n1965), .CK(clk), .RN(n5146), .Q(
sign_inv_out[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(n1964), .CK(clk), .RN(n5146), .Q(
data_output[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(n2529), .CK(clk), .RN(n5146), .Q(
d_ff_Zn[61]) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(n2528), .CK(clk), .RN(n5146), .Q(
d_ff_Yn[61]), .QN(n5067) );
DFFRXLTS d_ff5_Q_reg_61_ ( .D(n1967), .CK(clk), .RN(n5146), .Q(
sign_inv_out[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(n1966), .CK(clk), .RN(n5146), .Q(
data_output[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(n2525), .CK(clk), .RN(n5146), .Q(
d_ff_Zn[60]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(n2224), .CK(clk), .RN(n5145),
.Q(d_ff2_Z[60]) );
DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(n2524), .CK(clk), .RN(n5145), .Q(
d_ff_Yn[60]), .QN(n2982) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_60_ ( .D(n2106), .CK(clk), .RN(n5145),
.Q(d_ff2_Y[60]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_60_ ( .D(n2791), .CK(clk), .RN(n5145),
.Q(d_ff2_X[60]) );
DFFRXLTS d_ff5_Q_reg_60_ ( .D(n1969), .CK(clk), .RN(n5145), .Q(
sign_inv_out[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(n1968), .CK(clk), .RN(n5145), .Q(
data_output[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(n2521), .CK(clk), .RN(n5145), .Q(
d_ff_Zn[59]) );
DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(n2520), .CK(clk), .RN(n5145), .Q(
d_ff_Yn[59]), .QN(n5066) );
DFFRXLTS d_ff5_Q_reg_59_ ( .D(n1971), .CK(clk), .RN(n5144), .Q(
sign_inv_out[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(n1970), .CK(clk), .RN(n5144), .Q(
data_output[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(n2517), .CK(clk), .RN(n5144), .Q(
d_ff_Zn[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(n2226), .CK(clk), .RN(n5144),
.Q(d_ff2_Z[58]) );
DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(n2516), .CK(clk), .RN(n5144), .Q(
d_ff_Yn[58]), .QN(n2981) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_58_ ( .D(n2108), .CK(clk), .RN(n5144),
.Q(d_ff2_Y[58]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_58_ ( .D(n2789), .CK(clk), .RN(n5144),
.Q(d_ff2_X[58]) );
DFFRXLTS d_ff5_Q_reg_58_ ( .D(n1973), .CK(clk), .RN(n5144), .Q(
sign_inv_out[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(n1972), .CK(clk), .RN(n5144), .Q(
data_output[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(n2513), .CK(clk), .RN(n5144), .Q(
d_ff_Zn[57]) );
DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(n2512), .CK(clk), .RN(n5143), .Q(
d_ff_Yn[57]), .QN(n2980) );
DFFRXLTS d_ff5_Q_reg_57_ ( .D(n1975), .CK(clk), .RN(n5143), .Q(
sign_inv_out[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(n1974), .CK(clk), .RN(n5143), .Q(
data_output[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(n2509), .CK(clk), .RN(n5143), .Q(
d_ff_Zn[56]) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(n2508), .CK(clk), .RN(n5143), .Q(
d_ff_Yn[56]), .QN(n5065) );
DFFRXLTS d_ff5_Q_reg_56_ ( .D(n1977), .CK(clk), .RN(n5123), .Q(
sign_inv_out[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(n1976), .CK(clk), .RN(n5118), .Q(
data_output[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(n2505), .CK(clk), .RN(n5138), .Q(
d_ff_Zn[55]) );
DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(n2504), .CK(clk), .RN(n5137), .Q(
d_ff_Yn[55]), .QN(n5064) );
DFFRXLTS d_ff5_Q_reg_55_ ( .D(n1979), .CK(clk), .RN(n5122), .Q(
sign_inv_out[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(n1978), .CK(clk), .RN(n5133), .Q(
data_output[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(n2501), .CK(clk), .RN(n5159), .Q(
d_ff_Zn[54]) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(n2500), .CK(clk), .RN(n5142), .Q(
d_ff_Yn[54]), .QN(n5063) );
DFFRXLTS d_ff5_Q_reg_54_ ( .D(n1981), .CK(clk), .RN(n5142), .Q(
sign_inv_out[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(n1980), .CK(clk), .RN(n5142), .Q(
data_output[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(n2497), .CK(clk), .RN(n5142), .Q(
d_ff_Zn[53]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_53_ ( .D(n2231), .CK(clk), .RN(n5142),
.Q(d_ff2_Z[53]) );
DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(n2496), .CK(clk), .RN(n5142), .Q(
d_ff_Yn[53]), .QN(n5062) );
DFFRXLTS d_ff5_Q_reg_53_ ( .D(n1983), .CK(clk), .RN(n5141), .Q(
sign_inv_out[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(n1982), .CK(clk), .RN(n5141), .Q(
data_output[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(n2493), .CK(clk), .RN(n5141), .Q(
d_ff_Zn[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(n2232), .CK(clk), .RN(n5141),
.Q(d_ff2_Z[52]) );
DFFRXLTS d_ff4_Yn_Q_reg_52_ ( .D(n2492), .CK(clk), .RN(n5141), .Q(
d_ff_Yn[52]), .QN(n5070) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_52_ ( .D(n2114), .CK(clk), .RN(n5141),
.Q(d_ff2_Y[52]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_52_ ( .D(n2783), .CK(clk), .RN(n5141),
.Q(d_ff2_X[52]), .QN(n4937) );
DFFRXLTS d_ff5_Q_reg_52_ ( .D(n1985), .CK(clk), .RN(n5141), .Q(
sign_inv_out[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(n1984), .CK(clk), .RN(n5141), .Q(
data_output[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n2285), .CK(clk), .RN(n5141), .Q(d_ff_Zn[0])
);
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(n2219), .CK(clk), .RN(n5140), .Q(d_ff_Yn[0]),
.QN(n5011) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]),
.CK(clk), .RN(n5095), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(n2489), .CK(clk), .RN(n5140), .Q(
d_ff_Zn[51]) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(n2488), .CK(clk), .RN(n5140), .Q(
d_ff_Yn[51]), .QN(n5061) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(n2115), .CK(clk), .RN(n5140), .Q(
d_ff3_sh_y_out[51]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(n2770), .CK(clk), .RN(n5140), .Q(
d_ff3_sh_x_out[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n2301), .CK(clk), .RN(n5140), .Q(d_ff_Zn[4])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n2280), .CK(clk), .RN(n5139), .Q(
d_ff2_Z[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(n2300), .CK(clk), .RN(n5139), .Q(d_ff_Yn[4]),
.QN(n5015) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n2209), .CK(clk), .RN(n5139), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(n2676), .CK(clk), .RN(n5139), .Q(
d_ff3_sh_x_out[4]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]),
.CK(clk), .RN(n5082), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(n2477), .CK(clk), .RN(n5139), .Q(
d_ff_Zn[48]) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(n2476), .CK(clk), .RN(n5139), .Q(
d_ff_Yn[48]), .QN(n5058) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(n2121), .CK(clk), .RN(n5139), .Q(
d_ff3_sh_y_out[48]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(n2764), .CK(clk), .RN(n5118), .Q(
d_ff3_sh_x_out[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(n1992), .CK(clk), .RN(n5138), .Q(
data_output[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n2293), .CK(clk), .RN(n5118), .Q(d_ff_Zn[2])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n2282), .CK(clk), .RN(n5137), .Q(
d_ff2_Z[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(n2292), .CK(clk), .RN(n5138), .Q(d_ff_Yn[2]),
.QN(n5013) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n2213), .CK(clk), .RN(n5137), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n2672), .CK(clk), .RN(n5138), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]),
.CK(clk), .RN(n5095), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(n2485), .CK(clk), .RN(n5138), .Q(
d_ff_Zn[50]) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(n2484), .CK(clk), .RN(n5138), .Q(
d_ff_Yn[50]), .QN(n5060) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(n2117), .CK(clk), .RN(n5138), .Q(
d_ff3_sh_y_out[50]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(n2768), .CK(clk), .RN(n5138), .Q(
d_ff3_sh_x_out[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(n2473), .CK(clk), .RN(n5138), .Q(
d_ff_Zn[47]) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(n2472), .CK(clk), .RN(n5138), .Q(
d_ff_Yn[47]), .QN(n5057) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(n2123), .CK(clk), .RN(n5137), .Q(
d_ff3_sh_y_out[47]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(n2762), .CK(clk), .RN(n5137), .Q(
d_ff3_sh_x_out[47]) );
DFFRXLTS d_ff5_Q_reg_47_ ( .D(n1995), .CK(clk), .RN(n5137), .Q(
sign_inv_out[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(n1994), .CK(clk), .RN(n5137), .Q(
data_output[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n2297), .CK(clk), .RN(n5137), .Q(d_ff_Zn[3])
);
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(n2296), .CK(clk), .RN(n5137), .Q(d_ff_Yn[3]),
.QN(n5014) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n2211), .CK(clk), .RN(n5137), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n2674), .CK(clk), .RN(n5136), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]),
.CK(clk), .RN(n5089), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n2289), .CK(clk), .RN(n5136), .Q(d_ff_Zn[1])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n2283), .CK(clk), .RN(n5136), .Q(
d_ff2_Z[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(n2288), .CK(clk), .RN(n5136), .Q(d_ff_Yn[1]),
.QN(n5012) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n2215), .CK(clk), .RN(n5136), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n2670), .CK(clk), .RN(n5136), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(n2481), .CK(clk), .RN(n5136), .Q(
d_ff_Zn[49]) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(n2480), .CK(clk), .RN(n5135), .Q(
d_ff_Yn[49]), .QN(n5059) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(n2119), .CK(clk), .RN(n5135), .Q(
d_ff3_sh_y_out[49]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(n2766), .CK(clk), .RN(n5135), .Q(
d_ff3_sh_x_out[49]) );
DFFRXLTS d_ff5_Q_reg_49_ ( .D(n1991), .CK(clk), .RN(n5135), .Q(
sign_inv_out[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(n1990), .CK(clk), .RN(n5135), .Q(
data_output[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(n2469), .CK(clk), .RN(n5135), .Q(
d_ff_Zn[46]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_46_ ( .D(n2238), .CK(clk), .RN(n5135),
.Q(d_ff2_Z[46]) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(n2468), .CK(clk), .RN(n5135), .Q(
d_ff_Yn[46]), .QN(n5056) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(n2125), .CK(clk), .RN(n5134), .Q(
d_ff3_sh_y_out[46]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(n2760), .CK(clk), .RN(n5134), .Q(
d_ff3_sh_x_out[46]) );
DFFRXLTS d_ff5_Q_reg_46_ ( .D(n1997), .CK(clk), .RN(n5134), .Q(
sign_inv_out[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(n1996), .CK(clk), .RN(n5134), .Q(
data_output[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n2349), .CK(clk), .RN(n5134), .Q(
d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n2268), .CK(clk), .RN(n5134),
.Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(n2348), .CK(clk), .RN(n5134), .Q(
d_ff_Yn[16]), .QN(n5027) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n2185), .CK(clk), .RN(n5134), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n2700), .CK(clk), .RN(n5158), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n2321), .CK(clk), .RN(n5114), .Q(d_ff_Zn[9])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n2275), .CK(clk), .RN(n5131), .Q(
d_ff2_Z[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(n2320), .CK(clk), .RN(n5132), .Q(d_ff_Yn[9]),
.QN(n5020) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n2199), .CK(clk), .RN(n5150), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n2686), .CK(clk), .RN(n5132), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(n2461), .CK(clk), .RN(n5156), .Q(
d_ff_Zn[44]) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(n2460), .CK(clk), .RN(n5141), .Q(
d_ff_Yn[44]), .QN(n5054) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(n2129), .CK(clk), .RN(n5136), .Q(
d_ff3_sh_y_out[44]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(n2756), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[44]) );
DFFRXLTS d_ff5_Q_reg_44_ ( .D(n2001), .CK(clk), .RN(n5148), .Q(
sign_inv_out[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(n2000), .CK(clk), .RN(n5147), .Q(
data_output[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n2309), .CK(clk), .RN(n5143), .Q(d_ff_Zn[6])
);
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(n2308), .CK(clk), .RN(n5115), .Q(d_ff_Yn[6]),
.QN(n5017) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n2205), .CK(clk), .RN(n5133), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n2680), .CK(clk), .RN(n5133), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]),
.CK(clk), .RN(n5088), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n2305), .CK(clk), .RN(n5133), .Q(d_ff_Zn[5])
);
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(n2304), .CK(clk), .RN(n5133), .Q(d_ff_Yn[5]),
.QN(n5016) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n2207), .CK(clk), .RN(n5133), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n2678), .CK(clk), .RN(n5152), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(n2465), .CK(clk), .RN(n5151), .Q(
d_ff_Zn[45]) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(n2464), .CK(clk), .RN(n5154), .Q(
d_ff_Yn[45]), .QN(n5055) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(n2127), .CK(clk), .RN(n5156), .Q(
d_ff3_sh_y_out[45]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(n2758), .CK(clk), .RN(n5151), .Q(
d_ff3_sh_x_out[45]) );
DFFRXLTS d_ff5_Q_reg_45_ ( .D(n1999), .CK(clk), .RN(n5150), .Q(
sign_inv_out[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(n1998), .CK(clk), .RN(n5154), .Q(
data_output[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n2365), .CK(clk), .RN(n5155), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(n2364), .CK(clk), .RN(n5132), .Q(
d_ff_Yn[20]), .QN(n5031) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n2177), .CK(clk), .RN(n5132), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n2708), .CK(clk), .RN(n5132), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n2337), .CK(clk), .RN(n5132), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(n2336), .CK(clk), .RN(n5132), .Q(
d_ff_Yn[13]), .QN(n5024) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n2191), .CK(clk), .RN(n5132), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n2694), .CK(clk), .RN(n5131), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n2325), .CK(clk), .RN(n5131), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(n2324), .CK(clk), .RN(n5131), .Q(
d_ff_Yn[10]), .QN(n5021) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n2197), .CK(clk), .RN(n5131), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(n2688), .CK(clk), .RN(n5131), .Q(
d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(n2457), .CK(clk), .RN(n5131), .Q(
d_ff_Zn[43]) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(n2456), .CK(clk), .RN(n5116), .Q(
d_ff_Yn[43]), .QN(n5053) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(n2131), .CK(clk), .RN(n5117), .Q(
d_ff3_sh_y_out[43]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(n2754), .CK(clk), .RN(n5141), .Q(
d_ff3_sh_x_out[43]) );
DFFRXLTS d_ff5_Q_reg_43_ ( .D(n2003), .CK(clk), .RN(n5116), .Q(
sign_inv_out[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(n2002), .CK(clk), .RN(n5130), .Q(
data_output[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n2313), .CK(clk), .RN(n5117), .Q(d_ff_Zn[7])
);
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(n2312), .CK(clk), .RN(n5140), .Q(d_ff_Yn[7]),
.QN(n5018) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n2203), .CK(clk), .RN(n5130), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n2682), .CK(clk), .RN(n5130), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(n2445), .CK(clk), .RN(n5130), .Q(
d_ff_Zn[40]) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(n2444), .CK(clk), .RN(n5130), .Q(
d_ff_Yn[40]), .QN(n5050) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(n2137), .CK(clk), .RN(n5130), .Q(
d_ff3_sh_y_out[40]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(n2748), .CK(clk), .RN(n5116), .Q(
d_ff3_sh_x_out[40]) );
DFFRXLTS d_ff5_Q_reg_40_ ( .D(n2009), .CK(clk), .RN(n5113), .Q(
sign_inv_out[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(n2008), .CK(clk), .RN(n5138), .Q(
data_output[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(n2437), .CK(clk), .RN(n5111), .Q(
d_ff_Zn[38]) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(n2436), .CK(clk), .RN(n5111), .Q(
d_ff_Yn[38]), .QN(n5048) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(n2141), .CK(clk), .RN(n5111), .Q(
d_ff3_sh_y_out[38]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(n2744), .CK(clk), .RN(n5136), .Q(
d_ff3_sh_x_out[38]) );
DFFRXLTS d_ff5_Q_reg_38_ ( .D(n2013), .CK(clk), .RN(n5135), .Q(
sign_inv_out[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(n2012), .CK(clk), .RN(n5129), .Q(
data_output[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n2333), .CK(clk), .RN(n5129), .Q(
d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n2272), .CK(clk), .RN(n5129),
.Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(n2332), .CK(clk), .RN(n5129), .Q(
d_ff_Yn[12]), .QN(n5023) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n2193), .CK(clk), .RN(n5129), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n2692), .CK(clk), .RN(n5129), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n2329), .CK(clk), .RN(n5129), .Q(
d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n2273), .CK(clk), .RN(n5129),
.Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(n2328), .CK(clk), .RN(n5129), .Q(
d_ff_Yn[11]), .QN(n5022) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n2195), .CK(clk), .RN(n5128), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n2690), .CK(clk), .RN(n5128), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(n2453), .CK(clk), .RN(n5128), .Q(
d_ff_Zn[42]) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(n2452), .CK(clk), .RN(n5128), .Q(
d_ff_Yn[42]), .QN(n5052) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(n2133), .CK(clk), .RN(n5128), .Q(
d_ff3_sh_y_out[42]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(n2752), .CK(clk), .RN(n5127), .Q(
d_ff3_sh_x_out[42]) );
DFFRXLTS d_ff5_Q_reg_42_ ( .D(n2005), .CK(clk), .RN(n5127), .Q(
sign_inv_out[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(n2004), .CK(clk), .RN(n5127), .Q(
data_output[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n2317), .CK(clk), .RN(n5127), .Q(d_ff_Zn[8])
);
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n2276), .CK(clk), .RN(n5127), .Q(
d_ff2_Z[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(n2316), .CK(clk), .RN(n5127), .Q(d_ff_Yn[8]),
.QN(n5019) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n2201), .CK(clk), .RN(n5127), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n2684), .CK(clk), .RN(n5127), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(n2449), .CK(clk), .RN(n5127), .Q(
d_ff_Zn[41]) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(n2448), .CK(clk), .RN(n5126), .Q(
d_ff_Yn[41]), .QN(n5051) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(n2135), .CK(clk), .RN(n5126), .Q(
d_ff3_sh_y_out[41]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(n2750), .CK(clk), .RN(n5126), .Q(
d_ff3_sh_x_out[41]) );
DFFRXLTS d_ff5_Q_reg_41_ ( .D(n2007), .CK(clk), .RN(n5126), .Q(
sign_inv_out[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(n2006), .CK(clk), .RN(n5126), .Q(
data_output[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(n2441), .CK(clk), .RN(n5126), .Q(
d_ff_Zn[39]) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(n2440), .CK(clk), .RN(n5126), .Q(
d_ff_Yn[39]), .QN(n5049) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(n2139), .CK(clk), .RN(n5125), .Q(
d_ff3_sh_y_out[39]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(n2746), .CK(clk), .RN(n5125), .Q(
d_ff3_sh_x_out[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(n2433), .CK(clk), .RN(n5125), .Q(
d_ff_Zn[37]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_37_ ( .D(n2247), .CK(clk), .RN(n5125),
.Q(d_ff2_Z[37]) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(n2432), .CK(clk), .RN(n5125), .Q(
d_ff_Yn[37]), .QN(n5047) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(n2143), .CK(clk), .RN(n5125), .Q(
d_ff3_sh_y_out[37]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(n2742), .CK(clk), .RN(n5124), .Q(
d_ff3_sh_x_out[37]) );
DFFRXLTS d_ff5_Q_reg_37_ ( .D(n2015), .CK(clk), .RN(n5124), .Q(
sign_inv_out[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(n2014), .CK(clk), .RN(n5124), .Q(
data_output[37]) );
DFFRXLTS d_ff5_Q_reg_39_ ( .D(n2011), .CK(clk), .RN(n5124), .Q(
sign_inv_out[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(n2010), .CK(clk), .RN(n5124), .Q(
data_output[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n2361), .CK(clk), .RN(n5124), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(n2360), .CK(clk), .RN(n5124), .Q(
d_ff_Yn[19]), .QN(n5030) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n2179), .CK(clk), .RN(n5124), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n2706), .CK(clk), .RN(n5123), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(n2421), .CK(clk), .RN(n5123), .Q(
d_ff_Zn[34]) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(n2420), .CK(clk), .RN(n5123), .Q(
d_ff_Yn[34]), .QN(n5044) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(n2149), .CK(clk), .RN(n5123), .Q(
d_ff3_sh_y_out[34]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(n2736), .CK(clk), .RN(n5123), .Q(
d_ff3_sh_x_out[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n2377), .CK(clk), .RN(n5123), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(n2376), .CK(clk), .RN(n5123), .Q(
d_ff_Yn[23]), .QN(n5034) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(n2171), .CK(clk), .RN(n5122), .Q(
d_ff3_sh_y_out[23]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(n2714), .CK(clk), .RN(n5122), .Q(
d_ff3_sh_x_out[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n2405), .CK(clk), .RN(n5122), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(n2404), .CK(clk), .RN(n5122), .Q(
d_ff_Yn[30]), .QN(n5040) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n2157), .CK(clk), .RN(n5122), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n2728), .CK(clk), .RN(n5121), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(n2425), .CK(clk), .RN(n5121), .Q(
d_ff_Zn[35]) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(n2424), .CK(clk), .RN(n5121), .Q(
d_ff_Yn[35]), .QN(n5045) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(n2147), .CK(clk), .RN(n5121), .Q(
d_ff3_sh_y_out[35]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(n2738), .CK(clk), .RN(n5121), .Q(
d_ff3_sh_x_out[35]) );
DFFRXLTS d_ff5_Q_reg_35_ ( .D(n2019), .CK(clk), .RN(n5121), .Q(
sign_inv_out[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(n2018), .CK(clk), .RN(n5121), .Q(
data_output[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n2345), .CK(clk), .RN(n5121), .Q(
d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n2269), .CK(clk), .RN(n5130),
.Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(n2344), .CK(clk), .RN(n5157), .Q(
d_ff_Yn[15]), .QN(n5026) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n2187), .CK(clk), .RN(n5154), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n2698), .CK(clk), .RN(n5153), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(n2429), .CK(clk), .RN(n5112), .Q(
d_ff_Zn[36]) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(n2428), .CK(clk), .RN(n5152), .Q(
d_ff_Yn[36]), .QN(n5046) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(n2145), .CK(clk), .RN(n5133), .Q(
d_ff3_sh_y_out[36]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(n2740), .CK(clk), .RN(n5120), .Q(
d_ff3_sh_x_out[36]) );
DFFRXLTS d_ff5_Q_reg_36_ ( .D(n2017), .CK(clk), .RN(n5120), .Q(
sign_inv_out[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(n2016), .CK(clk), .RN(n5120), .Q(
data_output[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n2341), .CK(clk), .RN(n5120), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(n2340), .CK(clk), .RN(n5120), .Q(
d_ff_Yn[14]), .QN(n5025) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n2189), .CK(clk), .RN(n5120), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n2696), .CK(clk), .RN(n5119), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n2393), .CK(clk), .RN(n5119), .Q(
d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n2257), .CK(clk), .RN(n5119),
.Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(n2392), .CK(clk), .RN(n5119), .Q(
d_ff_Yn[27]), .QN(n5037) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n2163), .CK(clk), .RN(n5119), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n2722), .CK(clk), .RN(n5119), .Q(
d_ff3_sh_x_out[27]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(n2035), .CK(clk), .RN(n5119), .Q(
sign_inv_out[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n2034), .CK(clk), .RN(n5119), .Q(
data_output[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n2409), .CK(clk), .RN(n5119), .Q(
d_ff_Zn[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(n2408), .CK(clk), .RN(n5118), .Q(
d_ff_Yn[31]), .QN(n5041) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n2155), .CK(clk), .RN(n5118), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n2730), .CK(clk), .RN(n5118), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(n2027), .CK(clk), .RN(n5118), .Q(
sign_inv_out[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n2026), .CK(clk), .RN(n5118), .Q(
data_output[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n2401), .CK(clk), .RN(n5118), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(n2400), .CK(clk), .RN(n5118), .Q(
d_ff_Yn[29]), .QN(n5039) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n2159), .CK(clk), .RN(n5117), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(n2726), .CK(clk), .RN(n5117), .Q(
d_ff3_sh_x_out[29]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(n2031), .CK(clk), .RN(n5117), .Q(
sign_inv_out[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n2030), .CK(clk), .RN(n5117), .Q(
data_output[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n2369), .CK(clk), .RN(n5117), .Q(
d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n2263), .CK(clk), .RN(n5117),
.Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(n2368), .CK(clk), .RN(n5117), .Q(
d_ff_Yn[21]), .QN(n5032) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n2175), .CK(clk), .RN(n5117), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n2710), .CK(clk), .RN(n5116), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n2357), .CK(clk), .RN(n5116), .Q(
d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n2266), .CK(clk), .RN(n5116),
.Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(n2356), .CK(clk), .RN(n5116), .Q(
d_ff_Yn[18]), .QN(n5029) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n2181), .CK(clk), .RN(n5116), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n2704), .CK(clk), .RN(n5116), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n2385), .CK(clk), .RN(n5116), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(n2384), .CK(clk), .RN(n5115), .Q(
d_ff_Yn[25]), .QN(n5071) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n2167), .CK(clk), .RN(n5115), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n2718), .CK(clk), .RN(n5115), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(n2039), .CK(clk), .RN(n5115), .Q(
sign_inv_out[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n2038), .CK(clk), .RN(n5115), .Q(
data_output[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(n2417), .CK(clk), .RN(n5115), .Q(
d_ff_Zn[33]) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(n2416), .CK(clk), .RN(n5115), .Q(
d_ff_Yn[33]), .QN(n5043) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(n2151), .CK(clk), .RN(n5123), .Q(
d_ff3_sh_y_out[33]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(n2734), .CK(clk), .RN(n5123), .Q(
d_ff3_sh_x_out[33]) );
DFFRXLTS d_ff5_Q_reg_33_ ( .D(n2023), .CK(clk), .RN(n5121), .Q(
sign_inv_out[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(n2022), .CK(clk), .RN(n5122), .Q(
data_output[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n2353), .CK(clk), .RN(n5123), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(n2352), .CK(clk), .RN(n5122), .Q(
d_ff_Yn[17]), .QN(n5028) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n2183), .CK(clk), .RN(n5121), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n2702), .CK(clk), .RN(n5114), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(n2413), .CK(clk), .RN(n5114), .Q(
d_ff_Zn[32]) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(n2412), .CK(clk), .RN(n5114), .Q(
d_ff_Yn[32]), .QN(n5042) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(n2153), .CK(clk), .RN(n5114), .Q(
d_ff3_sh_y_out[32]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(n2732), .CK(clk), .RN(n5114), .Q(
d_ff3_sh_x_out[32]) );
DFFRXLTS d_ff5_Q_reg_32_ ( .D(n2025), .CK(clk), .RN(n5114), .Q(
sign_inv_out[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(n2024), .CK(clk), .RN(n5147), .Q(
data_output[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n2381), .CK(clk), .RN(n5148), .Q(
d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n2260), .CK(clk), .RN(n5149),
.Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(n2380), .CK(clk), .RN(n5144), .Q(
d_ff_Yn[24]), .QN(n5035) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n2169), .CK(clk), .RN(n5146), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n2716), .CK(clk), .RN(n5143), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n2373), .CK(clk), .RN(n5148), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(n2372), .CK(clk), .RN(n5147), .Q(
d_ff_Yn[22]), .QN(n5033) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n2173), .CK(clk), .RN(n5113), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n2712), .CK(clk), .RN(n5113), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n2397), .CK(clk), .RN(n5113), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(n2396), .CK(clk), .RN(n5113), .Q(
d_ff_Yn[28]), .QN(n5038) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n2161), .CK(clk), .RN(n5113), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n2724), .CK(clk), .RN(n5149), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(n2033), .CK(clk), .RN(n5144), .Q(
sign_inv_out[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n2032), .CK(clk), .RN(n5145), .Q(
data_output[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n2389), .CK(clk), .RN(n5146), .Q(
d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n2258), .CK(clk), .RN(n5142),
.Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(n2388), .CK(clk), .RN(n5137), .Q(
d_ff_Yn[26]), .QN(n5036) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n2165), .CK(clk), .RN(n5113), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n2720), .CK(clk), .RN(n5146), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(n2037), .CK(clk), .RN(n5142), .Q(
sign_inv_out[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n2036), .CK(clk), .RN(n5127), .Q(
data_output[26]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(n2045), .CK(clk), .RN(n5128), .Q(
sign_inv_out[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n2044), .CK(clk), .RN(n5129), .Q(
data_output[22]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]),
.CK(clk), .RN(n2962), .QN(n2984) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(n2041), .CK(clk), .RN(n5124), .Q(
sign_inv_out[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n2040), .CK(clk), .RN(n5125), .Q(
data_output[24]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(n2055), .CK(clk), .RN(n5126), .Q(
sign_inv_out[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n2054), .CK(clk), .RN(n5121), .Q(
data_output[17]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]),
.CK(clk), .RN(n5085), .QN(n2983) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(n2053), .CK(clk), .RN(n5122), .Q(
sign_inv_out[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n2052), .CK(clk), .RN(n5123), .Q(
data_output[18]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(n2047), .CK(clk), .RN(n5128), .Q(
sign_inv_out[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n2046), .CK(clk), .RN(n5112), .Q(
data_output[21]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(n2061), .CK(clk), .RN(n5127), .Q(
sign_inv_out[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n2060), .CK(clk), .RN(n5112), .Q(
data_output[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(n2059), .CK(clk), .RN(n5112), .Q(
sign_inv_out[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n2058), .CK(clk), .RN(n5112), .Q(
data_output[15]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(n2029), .CK(clk), .RN(n5112), .Q(
sign_inv_out[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n2028), .CK(clk), .RN(n5112), .Q(
data_output[30]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(n2043), .CK(clk), .RN(n5112), .Q(
sign_inv_out[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n2042), .CK(clk), .RN(n5112), .Q(
data_output[23]) );
DFFRXLTS d_ff5_Q_reg_34_ ( .D(n2021), .CK(clk), .RN(n5112), .Q(
sign_inv_out[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(n2020), .CK(clk), .RN(n5112), .Q(
data_output[34]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(n2051), .CK(clk), .RN(n5112), .Q(
sign_inv_out[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n2050), .CK(clk), .RN(n5112), .Q(
data_output[19]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(n2073), .CK(clk), .RN(n5112), .Q(
sign_inv_out[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n2072), .CK(clk), .RN(n5129), .Q(
data_output[8]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(n2067), .CK(clk), .RN(n5124), .Q(
sign_inv_out[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n2066), .CK(clk), .RN(n5125), .Q(
data_output[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(n2065), .CK(clk), .RN(n5126), .Q(
sign_inv_out[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n2064), .CK(clk), .RN(n5121), .Q(
data_output[12]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(n2075), .CK(clk), .RN(n5122), .Q(
sign_inv_out[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n2074), .CK(clk), .RN(n5123), .Q(
data_output[7]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(n2069), .CK(clk), .RN(n5112), .Q(
sign_inv_out[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n2068), .CK(clk), .RN(n5124), .Q(
data_output[10]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(n2063), .CK(clk), .RN(n5125), .Q(
sign_inv_out[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n2062), .CK(clk), .RN(n5126), .Q(
data_output[13]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(n2049), .CK(clk), .RN(n5121), .Q(
sign_inv_out[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n2048), .CK(clk), .RN(n5111), .Q(
data_output[20]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(n2079), .CK(clk), .RN(n5111), .Q(
sign_inv_out[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n2078), .CK(clk), .RN(n5111), .Q(
data_output[5]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]),
.CK(clk), .RN(n2962), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(n2077), .CK(clk), .RN(n5111), .Q(
sign_inv_out[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n2076), .CK(clk), .RN(n5111), .Q(
data_output[6]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(n2071), .CK(clk), .RN(n5111), .Q(
sign_inv_out[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n2070), .CK(clk), .RN(n5111), .Q(
data_output[9]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(n2057), .CK(clk), .RN(n5111), .Q(
sign_inv_out[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n2056), .CK(clk), .RN(n5111), .Q(
data_output[16]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(n2087), .CK(clk), .RN(n5111), .Q(
sign_inv_out[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n2086), .CK(clk), .RN(n5111), .Q(
data_output[1]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]),
.CK(clk), .RN(n5107), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(n2083), .CK(clk), .RN(n5111), .Q(
sign_inv_out[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n2082), .CK(clk), .RN(n5110), .Q(
data_output[3]) );
DFFRXLTS d_ff5_Q_reg_50_ ( .D(n1989), .CK(clk), .RN(n5110), .Q(
sign_inv_out[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(n1988), .CK(clk), .RN(n5110), .Q(
data_output[50]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(n2085), .CK(clk), .RN(n5110), .Q(
sign_inv_out[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n2084), .CK(clk), .RN(n5110), .Q(
data_output[2]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(n2081), .CK(clk), .RN(n5110), .Q(
sign_inv_out[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n2080), .CK(clk), .RN(n5110), .Q(
data_output[4]) );
DFFRXLTS d_ff5_Q_reg_51_ ( .D(n1987), .CK(clk), .RN(n5110), .Q(
sign_inv_out[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(n1986), .CK(clk), .RN(n5110), .Q(
data_output[51]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]),
.CK(clk), .RN(n5088), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(
n2937), .CK(clk), .RN(n5104), .Q(
add_subt_module_Sgf_normalized_result[54]), .QN(n5007) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n2217), .CK(clk), .RN(n5110), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(n2089), .CK(clk), .RN(n5110), .Q(
sign_inv_out[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n2088), .CK(clk), .RN(n5110), .Q(
data_output[0]) );
DFFRXLTS add_subt_module_Sel_D_Q_reg_0_ ( .D(n2663), .CK(clk), .RN(n1959),
.Q(add_subt_module_FSM_selector_D), .QN(n4856) );
DFFRXLTS add_subt_module_YRegister_Q_reg_63_ ( .D(n1946), .CK(clk), .RN(
n5088), .Q(add_subt_module_intDY[63]) );
DFFRXLTS add_subt_module_ASRegister_Q_reg_0_ ( .D(n1944), .CK(clk), .RN(
n5105), .Q(add_subt_module_intAS) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(n1941), .CK(clk), .RN(n5086), .Q(add_subt_module_DmP[62]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(n1940), .CK(clk), .RN(n3015), .Q(add_subt_module_DMP[62]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(n1938), .CK(clk), .RN(n5089), .Q(add_subt_module_DmP[61]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(n1937), .CK(clk), .RN(n5098), .Q(add_subt_module_DMP[61]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(n1935), .CK(clk), .RN(n5105), .Q(add_subt_module_DmP[60]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(n1934), .CK(clk), .RN(n5104), .Q(add_subt_module_DMP[60]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(n1932), .CK(clk), .RN(n5086), .Q(add_subt_module_DmP[59]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(n1931), .CK(clk), .RN(n3015), .Q(add_subt_module_DMP[59]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(n1929), .CK(clk), .RN(n5089), .Q(add_subt_module_DmP[58]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(n1928), .CK(clk), .RN(n3015), .Q(add_subt_module_DMP[58]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(n1926), .CK(clk), .RN(n5086), .Q(add_subt_module_DmP[57]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(n1925), .CK(clk), .RN(n5081), .Q(add_subt_module_DMP[57]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(n1923), .CK(clk), .RN(n5089), .Q(add_subt_module_DmP[56]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(n1922), .CK(clk), .RN(n5108), .Q(add_subt_module_DMP[56]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(n1920), .CK(clk), .RN(n5105), .Q(add_subt_module_DmP[55]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(n1919), .CK(clk), .RN(n5108), .Q(add_subt_module_DMP[55]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(n1917), .CK(clk), .RN(n5104), .Q(add_subt_module_DmP[54]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(n1914), .CK(clk), .RN(n5104), .Q(add_subt_module_DmP[53]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(n1913), .CK(clk), .RN(n5101), .Q(add_subt_module_DMP[53]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(n1911), .CK(clk), .RN(n5107), .Q(add_subt_module_DmP[52]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(n1910), .CK(clk), .RN(n5099), .Q(add_subt_module_DMP[52]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(n1879), .CK(clk), .RN(n5108), .Q(add_subt_module_DmP[49]), .QN(n4978) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(n1875), .CK(clk), .RN(n5108), .Q(add_subt_module_DmP[46]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n1868),
.CK(clk), .RN(n2961), .Q(add_subt_module_DmP[9]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n1858),
.CK(clk), .RN(n5091), .Q(add_subt_module_DmP[5]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n1845), .CK(clk), .RN(n5084), .Q(add_subt_module_DmP[10]), .QN(n4981) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(n1831), .CK(clk), .RN(n5092), .Q(add_subt_module_DmP[38]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(n1814), .CK(clk), .RN(n5109), .Q(add_subt_module_DmP[41]), .QN(n4979) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(n1799), .CK(clk), .RN(n5093), .Q(add_subt_module_DmP[34]) );
DFFRXLTS add_subt_module_YRegister_Q_reg_30_ ( .D(n1794), .CK(clk), .RN(
n5093), .QN(n2970) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n1793), .CK(clk), .RN(n5093), .Q(add_subt_module_DmP[30]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n1786), .CK(clk), .RN(n5106), .Q(add_subt_module_DmP[15]), .QN(n4980) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(n1772), .CK(clk), .RN(n5094), .Q(add_subt_module_DmP[31]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n5094), .Q(add_subt_module_DmP[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n1764), .CK(clk), .RN(n5094), .Q(add_subt_module_DmP[21]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n1750), .CK(clk), .RN(n5095), .Q(add_subt_module_DmP[17]) );
DFFRXLTS add_subt_module_YRegister_Q_reg_32_ ( .D(n1748), .CK(clk), .RN(
n5082), .QN(n2969) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(n1747), .CK(clk), .RN(n5103), .Q(add_subt_module_DmP[32]) );
DFFRXLTS add_subt_module_YRegister_Q_reg_24_ ( .D(n1744), .CK(clk), .RN(
n5099), .QN(n2971) );
DFFRXLTS add_subt_module_YRegister_Q_reg_22_ ( .D(n1741), .CK(clk), .RN(
n5096), .QN(n2965) );
CMPR32X2TS DP_OP_92J138_122_9081_U12 ( .A(add_subt_module_S_Oper_A_exp[0]),
.B(add_subt_module_FSM_exp_operation_A_S), .C(
DP_OP_92J138_122_9081_n26), .CO(DP_OP_92J138_122_9081_n11), .S(
add_subt_module_Exp_Operation_Module_Data_S[0]) );
CMPR32X2TS DP_OP_92J138_122_9081_U11 ( .A(DP_OP_92J138_122_9081_n25), .B(
add_subt_module_S_Oper_A_exp[1]), .C(DP_OP_92J138_122_9081_n11), .CO(
DP_OP_92J138_122_9081_n10), .S(
add_subt_module_Exp_Operation_Module_Data_S[1]) );
CMPR32X2TS DP_OP_92J138_122_9081_U10 ( .A(DP_OP_92J138_122_9081_n24), .B(
add_subt_module_S_Oper_A_exp[2]), .C(DP_OP_92J138_122_9081_n10), .CO(
DP_OP_92J138_122_9081_n9), .S(
add_subt_module_Exp_Operation_Module_Data_S[2]) );
CMPR32X2TS DP_OP_92J138_122_9081_U9 ( .A(DP_OP_92J138_122_9081_n23), .B(
add_subt_module_S_Oper_A_exp[3]), .C(DP_OP_92J138_122_9081_n9), .CO(
DP_OP_92J138_122_9081_n8), .S(
add_subt_module_Exp_Operation_Module_Data_S[3]) );
CMPR32X2TS DP_OP_92J138_122_9081_U8 ( .A(DP_OP_92J138_122_9081_n22), .B(
add_subt_module_S_Oper_A_exp[4]), .C(DP_OP_92J138_122_9081_n8), .CO(
DP_OP_92J138_122_9081_n7), .S(
add_subt_module_Exp_Operation_Module_Data_S[4]) );
CMPR32X2TS DP_OP_92J138_122_9081_U7 ( .A(DP_OP_92J138_122_9081_n21), .B(
add_subt_module_S_Oper_A_exp[5]), .C(DP_OP_92J138_122_9081_n7), .CO(
DP_OP_92J138_122_9081_n6), .S(
add_subt_module_Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS DP_OP_92J138_122_9081_U6 ( .A(DP_OP_92J138_122_9081_n20), .B(
add_subt_module_S_Oper_A_exp[6]), .C(DP_OP_92J138_122_9081_n6), .CO(
DP_OP_92J138_122_9081_n5), .S(
add_subt_module_Exp_Operation_Module_Data_S[6]) );
CMPR32X2TS DP_OP_92J138_122_9081_U5 ( .A(DP_OP_92J138_122_9081_n19), .B(
add_subt_module_S_Oper_A_exp[7]), .C(DP_OP_92J138_122_9081_n5), .CO(
DP_OP_92J138_122_9081_n4), .S(
add_subt_module_Exp_Operation_Module_Data_S[7]) );
CMPR32X2TS DP_OP_92J138_122_9081_U4 ( .A(DP_OP_92J138_122_9081_n18), .B(
add_subt_module_S_Oper_A_exp[8]), .C(DP_OP_92J138_122_9081_n4), .CO(
DP_OP_92J138_122_9081_n3), .S(
add_subt_module_Exp_Operation_Module_Data_S[8]) );
CMPR32X2TS DP_OP_92J138_122_9081_U3 ( .A(DP_OP_92J138_122_9081_n17), .B(
add_subt_module_S_Oper_A_exp[9]), .C(DP_OP_92J138_122_9081_n3), .CO(
DP_OP_92J138_122_9081_n2), .S(
add_subt_module_Exp_Operation_Module_Data_S[9]) );
CMPR32X2TS DP_OP_92J138_122_9081_U2 ( .A(DP_OP_92J138_122_9081_n16), .B(
add_subt_module_S_Oper_A_exp[10]), .C(DP_OP_92J138_122_9081_n2), .CO(
DP_OP_92J138_122_9081_n1), .S(
add_subt_module_Exp_Operation_Module_Data_S[10]) );
CMPR32X2TS DP_OP_95J138_125_7728_U56 ( .A(add_subt_module_S_A_S_Oper_A[0]),
.B(n4021), .C(DP_OP_95J138_125_7728_n114), .CO(
DP_OP_95J138_125_7728_n55), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[0]) );
CMPR32X2TS DP_OP_95J138_125_7728_U55 ( .A(DP_OP_95J138_125_7728_n113), .B(
add_subt_module_S_A_S_Oper_A[1]), .C(DP_OP_95J138_125_7728_n55), .CO(
DP_OP_95J138_125_7728_n54), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[1]) );
CMPR32X2TS DP_OP_95J138_125_7728_U54 ( .A(DP_OP_95J138_125_7728_n112), .B(
add_subt_module_S_A_S_Oper_A[2]), .C(DP_OP_95J138_125_7728_n54), .CO(
DP_OP_95J138_125_7728_n53), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[2]) );
CMPR32X2TS DP_OP_95J138_125_7728_U53 ( .A(DP_OP_95J138_125_7728_n111), .B(
add_subt_module_S_A_S_Oper_A[3]), .C(DP_OP_95J138_125_7728_n53), .CO(
DP_OP_95J138_125_7728_n52), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[3]) );
CMPR32X2TS DP_OP_95J138_125_7728_U52 ( .A(DP_OP_95J138_125_7728_n110), .B(
add_subt_module_S_A_S_Oper_A[4]), .C(DP_OP_95J138_125_7728_n52), .CO(
DP_OP_95J138_125_7728_n51), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[4]) );
CMPR32X2TS DP_OP_95J138_125_7728_U51 ( .A(DP_OP_95J138_125_7728_n109), .B(
add_subt_module_S_A_S_Oper_A[5]), .C(DP_OP_95J138_125_7728_n51), .CO(
DP_OP_95J138_125_7728_n50), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[5]) );
CMPR32X2TS DP_OP_95J138_125_7728_U50 ( .A(DP_OP_95J138_125_7728_n108), .B(
add_subt_module_S_A_S_Oper_A[6]), .C(DP_OP_95J138_125_7728_n50), .CO(
DP_OP_95J138_125_7728_n49), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[6]) );
CMPR32X2TS DP_OP_95J138_125_7728_U49 ( .A(DP_OP_95J138_125_7728_n107), .B(
add_subt_module_S_A_S_Oper_A[7]), .C(DP_OP_95J138_125_7728_n49), .CO(
DP_OP_95J138_125_7728_n48), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[7]) );
CMPR32X2TS DP_OP_95J138_125_7728_U48 ( .A(DP_OP_95J138_125_7728_n106), .B(
add_subt_module_S_A_S_Oper_A[8]), .C(DP_OP_95J138_125_7728_n48), .CO(
DP_OP_95J138_125_7728_n47), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[8]) );
CMPR32X2TS DP_OP_95J138_125_7728_U47 ( .A(DP_OP_95J138_125_7728_n105), .B(
add_subt_module_S_A_S_Oper_A[9]), .C(DP_OP_95J138_125_7728_n47), .CO(
DP_OP_95J138_125_7728_n46), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[9]) );
CMPR32X2TS DP_OP_95J138_125_7728_U46 ( .A(DP_OP_95J138_125_7728_n104), .B(
add_subt_module_S_A_S_Oper_A[10]), .C(DP_OP_95J138_125_7728_n46), .CO(
DP_OP_95J138_125_7728_n45), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[10]) );
CMPR32X2TS DP_OP_95J138_125_7728_U45 ( .A(DP_OP_95J138_125_7728_n103), .B(
add_subt_module_S_A_S_Oper_A[11]), .C(DP_OP_95J138_125_7728_n45), .CO(
DP_OP_95J138_125_7728_n44), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[11]) );
CMPR32X2TS DP_OP_95J138_125_7728_U44 ( .A(DP_OP_95J138_125_7728_n102), .B(
add_subt_module_S_A_S_Oper_A[12]), .C(DP_OP_95J138_125_7728_n44), .CO(
DP_OP_95J138_125_7728_n43), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[12]) );
CMPR32X2TS DP_OP_95J138_125_7728_U43 ( .A(DP_OP_95J138_125_7728_n101), .B(
add_subt_module_S_A_S_Oper_A[13]), .C(DP_OP_95J138_125_7728_n43), .CO(
DP_OP_95J138_125_7728_n42), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[13]) );
CMPR32X2TS DP_OP_95J138_125_7728_U42 ( .A(DP_OP_95J138_125_7728_n100), .B(
add_subt_module_S_A_S_Oper_A[14]), .C(DP_OP_95J138_125_7728_n42), .CO(
DP_OP_95J138_125_7728_n41), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[14]) );
CMPR32X2TS DP_OP_95J138_125_7728_U41 ( .A(DP_OP_95J138_125_7728_n99), .B(
add_subt_module_S_A_S_Oper_A[15]), .C(DP_OP_95J138_125_7728_n41), .CO(
DP_OP_95J138_125_7728_n40), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[15]) );
CMPR32X2TS DP_OP_95J138_125_7728_U40 ( .A(DP_OP_95J138_125_7728_n98), .B(
add_subt_module_S_A_S_Oper_A[16]), .C(DP_OP_95J138_125_7728_n40), .CO(
DP_OP_95J138_125_7728_n39), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[16]) );
CMPR32X2TS DP_OP_95J138_125_7728_U39 ( .A(DP_OP_95J138_125_7728_n97), .B(
add_subt_module_S_A_S_Oper_A[17]), .C(DP_OP_95J138_125_7728_n39), .CO(
DP_OP_95J138_125_7728_n38), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[17]) );
CMPR32X2TS DP_OP_95J138_125_7728_U38 ( .A(DP_OP_95J138_125_7728_n96), .B(
add_subt_module_S_A_S_Oper_A[18]), .C(DP_OP_95J138_125_7728_n38), .CO(
DP_OP_95J138_125_7728_n37), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[18]) );
CMPR32X2TS DP_OP_95J138_125_7728_U37 ( .A(DP_OP_95J138_125_7728_n95), .B(
add_subt_module_S_A_S_Oper_A[19]), .C(DP_OP_95J138_125_7728_n37), .CO(
DP_OP_95J138_125_7728_n36), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[19]) );
CMPR32X2TS DP_OP_95J138_125_7728_U36 ( .A(DP_OP_95J138_125_7728_n94), .B(
add_subt_module_S_A_S_Oper_A[20]), .C(DP_OP_95J138_125_7728_n36), .CO(
DP_OP_95J138_125_7728_n35), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[20]) );
CMPR32X2TS DP_OP_95J138_125_7728_U35 ( .A(DP_OP_95J138_125_7728_n93), .B(
add_subt_module_S_A_S_Oper_A[21]), .C(DP_OP_95J138_125_7728_n35), .CO(
DP_OP_95J138_125_7728_n34), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[21]) );
CMPR32X2TS DP_OP_95J138_125_7728_U34 ( .A(DP_OP_95J138_125_7728_n92), .B(
add_subt_module_S_A_S_Oper_A[22]), .C(DP_OP_95J138_125_7728_n34), .CO(
DP_OP_95J138_125_7728_n33), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[22]) );
CMPR32X2TS DP_OP_95J138_125_7728_U33 ( .A(DP_OP_95J138_125_7728_n91), .B(
add_subt_module_S_A_S_Oper_A[23]), .C(DP_OP_95J138_125_7728_n33), .CO(
DP_OP_95J138_125_7728_n32), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[23]) );
CMPR32X2TS DP_OP_95J138_125_7728_U32 ( .A(DP_OP_95J138_125_7728_n90), .B(
add_subt_module_S_A_S_Oper_A[24]), .C(DP_OP_95J138_125_7728_n32), .CO(
DP_OP_95J138_125_7728_n31), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[24]) );
CMPR32X2TS DP_OP_95J138_125_7728_U31 ( .A(DP_OP_95J138_125_7728_n89), .B(
add_subt_module_S_A_S_Oper_A[25]), .C(DP_OP_95J138_125_7728_n31), .CO(
DP_OP_95J138_125_7728_n30), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[25]) );
CMPR32X2TS DP_OP_95J138_125_7728_U30 ( .A(DP_OP_95J138_125_7728_n88), .B(
add_subt_module_S_A_S_Oper_A[26]), .C(DP_OP_95J138_125_7728_n30), .CO(
DP_OP_95J138_125_7728_n29), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[26]) );
CMPR32X2TS DP_OP_95J138_125_7728_U29 ( .A(DP_OP_95J138_125_7728_n87), .B(
add_subt_module_S_A_S_Oper_A[27]), .C(DP_OP_95J138_125_7728_n29), .CO(
DP_OP_95J138_125_7728_n28), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[27]) );
CMPR32X2TS DP_OP_95J138_125_7728_U28 ( .A(DP_OP_95J138_125_7728_n86), .B(
add_subt_module_S_A_S_Oper_A[28]), .C(DP_OP_95J138_125_7728_n28), .CO(
DP_OP_95J138_125_7728_n27), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[28]) );
CMPR32X2TS DP_OP_95J138_125_7728_U27 ( .A(DP_OP_95J138_125_7728_n85), .B(
add_subt_module_S_A_S_Oper_A[29]), .C(DP_OP_95J138_125_7728_n27), .CO(
DP_OP_95J138_125_7728_n26), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[29]) );
CMPR32X2TS DP_OP_95J138_125_7728_U26 ( .A(DP_OP_95J138_125_7728_n84), .B(
add_subt_module_S_A_S_Oper_A[30]), .C(DP_OP_95J138_125_7728_n26), .CO(
DP_OP_95J138_125_7728_n25), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[30]) );
CMPR32X2TS DP_OP_95J138_125_7728_U25 ( .A(DP_OP_95J138_125_7728_n83), .B(
add_subt_module_S_A_S_Oper_A[31]), .C(DP_OP_95J138_125_7728_n25), .CO(
DP_OP_95J138_125_7728_n24), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[31]) );
CMPR32X2TS DP_OP_95J138_125_7728_U24 ( .A(DP_OP_95J138_125_7728_n82), .B(
add_subt_module_S_A_S_Oper_A[32]), .C(DP_OP_95J138_125_7728_n24), .CO(
DP_OP_95J138_125_7728_n23), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[32]) );
CMPR32X2TS DP_OP_95J138_125_7728_U23 ( .A(DP_OP_95J138_125_7728_n81), .B(
add_subt_module_S_A_S_Oper_A[33]), .C(DP_OP_95J138_125_7728_n23), .CO(
DP_OP_95J138_125_7728_n22), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[33]) );
CMPR32X2TS DP_OP_95J138_125_7728_U22 ( .A(DP_OP_95J138_125_7728_n80), .B(
add_subt_module_S_A_S_Oper_A[34]), .C(DP_OP_95J138_125_7728_n22), .CO(
DP_OP_95J138_125_7728_n21), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[34]) );
CMPR32X2TS DP_OP_95J138_125_7728_U21 ( .A(DP_OP_95J138_125_7728_n79), .B(
add_subt_module_S_A_S_Oper_A[35]), .C(DP_OP_95J138_125_7728_n21), .CO(
DP_OP_95J138_125_7728_n20), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[35]) );
CMPR32X2TS DP_OP_95J138_125_7728_U20 ( .A(DP_OP_95J138_125_7728_n78), .B(
add_subt_module_S_A_S_Oper_A[36]), .C(DP_OP_95J138_125_7728_n20), .CO(
DP_OP_95J138_125_7728_n19), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[36]) );
CMPR32X2TS DP_OP_95J138_125_7728_U19 ( .A(DP_OP_95J138_125_7728_n77), .B(
add_subt_module_S_A_S_Oper_A[37]), .C(DP_OP_95J138_125_7728_n19), .CO(
DP_OP_95J138_125_7728_n18), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[37]) );
CMPR32X2TS DP_OP_95J138_125_7728_U18 ( .A(DP_OP_95J138_125_7728_n76), .B(
add_subt_module_S_A_S_Oper_A[38]), .C(DP_OP_95J138_125_7728_n18), .CO(
DP_OP_95J138_125_7728_n17), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[38]) );
CMPR32X2TS DP_OP_95J138_125_7728_U17 ( .A(DP_OP_95J138_125_7728_n75), .B(
add_subt_module_S_A_S_Oper_A[39]), .C(DP_OP_95J138_125_7728_n17), .CO(
DP_OP_95J138_125_7728_n16), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[39]) );
CMPR32X2TS DP_OP_95J138_125_7728_U16 ( .A(DP_OP_95J138_125_7728_n74), .B(
add_subt_module_S_A_S_Oper_A[40]), .C(DP_OP_95J138_125_7728_n16), .CO(
DP_OP_95J138_125_7728_n15), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[40]) );
CMPR32X2TS DP_OP_95J138_125_7728_U15 ( .A(DP_OP_95J138_125_7728_n73), .B(
add_subt_module_S_A_S_Oper_A[41]), .C(DP_OP_95J138_125_7728_n15), .CO(
DP_OP_95J138_125_7728_n14), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[41]) );
CMPR32X2TS DP_OP_95J138_125_7728_U14 ( .A(DP_OP_95J138_125_7728_n72), .B(
add_subt_module_S_A_S_Oper_A[42]), .C(DP_OP_95J138_125_7728_n14), .CO(
DP_OP_95J138_125_7728_n13), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[42]) );
CMPR32X2TS DP_OP_95J138_125_7728_U13 ( .A(DP_OP_95J138_125_7728_n71), .B(
add_subt_module_S_A_S_Oper_A[43]), .C(DP_OP_95J138_125_7728_n13), .CO(
DP_OP_95J138_125_7728_n12), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[43]) );
CMPR32X2TS DP_OP_95J138_125_7728_U12 ( .A(DP_OP_95J138_125_7728_n70), .B(
add_subt_module_S_A_S_Oper_A[44]), .C(DP_OP_95J138_125_7728_n12), .CO(
DP_OP_95J138_125_7728_n11), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[44]) );
CMPR32X2TS DP_OP_95J138_125_7728_U11 ( .A(DP_OP_95J138_125_7728_n69), .B(
add_subt_module_S_A_S_Oper_A[45]), .C(DP_OP_95J138_125_7728_n11), .CO(
DP_OP_95J138_125_7728_n10), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[45]) );
CMPR32X2TS DP_OP_95J138_125_7728_U10 ( .A(DP_OP_95J138_125_7728_n68), .B(
add_subt_module_S_A_S_Oper_A[46]), .C(DP_OP_95J138_125_7728_n10), .CO(
DP_OP_95J138_125_7728_n9), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[46]) );
CMPR32X2TS DP_OP_95J138_125_7728_U9 ( .A(DP_OP_95J138_125_7728_n67), .B(
add_subt_module_S_A_S_Oper_A[47]), .C(DP_OP_95J138_125_7728_n9), .CO(
DP_OP_95J138_125_7728_n8), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[47]) );
CMPR32X2TS DP_OP_95J138_125_7728_U8 ( .A(DP_OP_95J138_125_7728_n66), .B(
add_subt_module_S_A_S_Oper_A[48]), .C(DP_OP_95J138_125_7728_n8), .CO(
DP_OP_95J138_125_7728_n7), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[48]) );
CMPR32X2TS DP_OP_95J138_125_7728_U7 ( .A(DP_OP_95J138_125_7728_n65), .B(
add_subt_module_S_A_S_Oper_A[49]), .C(DP_OP_95J138_125_7728_n7), .CO(
DP_OP_95J138_125_7728_n6), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[49]) );
CMPR32X2TS DP_OP_95J138_125_7728_U6 ( .A(DP_OP_95J138_125_7728_n64), .B(
add_subt_module_S_A_S_Oper_A[50]), .C(DP_OP_95J138_125_7728_n6), .CO(
DP_OP_95J138_125_7728_n5), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[50]) );
CMPR32X2TS DP_OP_95J138_125_7728_U5 ( .A(DP_OP_95J138_125_7728_n63), .B(
add_subt_module_S_A_S_Oper_A[51]), .C(DP_OP_95J138_125_7728_n5), .CO(
DP_OP_95J138_125_7728_n4), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[51]) );
CMPR32X2TS DP_OP_95J138_125_7728_U4 ( .A(DP_OP_95J138_125_7728_n62), .B(
add_subt_module_S_A_S_Oper_A[52]), .C(DP_OP_95J138_125_7728_n4), .CO(
DP_OP_95J138_125_7728_n3), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[52]) );
CMPR32X2TS DP_OP_95J138_125_7728_U3 ( .A(DP_OP_95J138_125_7728_n61), .B(
add_subt_module_S_A_S_Oper_A[53]), .C(DP_OP_95J138_125_7728_n3), .CO(
DP_OP_95J138_125_7728_n2), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[53]) );
CMPR32X2TS DP_OP_95J138_125_7728_U2 ( .A(DP_OP_95J138_125_7728_n60), .B(
add_subt_module_S_A_S_Oper_A[54]), .C(DP_OP_95J138_125_7728_n2), .CO(
DP_OP_95J138_125_7728_n1), .S(
add_subt_module_Add_Subt_Sgf_module_S_to_D[54]) );
DFFRX1TS add_subt_module_XRegister_Q_reg_63_ ( .D(n1945), .CK(clk), .RN(
n5085), .Q(add_subt_module_intDX[63]), .QN(n5009) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]),
.CK(clk), .RN(n5107), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .QN(
n5006) );
DFFRX2TS add_subt_module_YRegister_Q_reg_51_ ( .D(n1906), .CK(clk), .RN(
n5095), .Q(add_subt_module_intDY[51]), .QN(n5005) );
DFFRX1TS add_subt_module_YRegister_Q_reg_48_ ( .D(n1900), .CK(clk), .RN(
n5107), .Q(add_subt_module_intDY[48]), .QN(n5004) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
n2596), .CK(clk), .RN(n5088), .Q(add_subt_module_Add_Subt_result[0]),
.QN(n5003) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(
n2588), .CK(clk), .RN(n5104), .Q(
add_subt_module_Sgf_normalized_result[53]), .QN(n5001) );
DFFRX1TS add_subt_module_Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(
n1943), .CK(clk), .RN(n5086), .Q(add_subt_module_sign_final_result),
.QN(n5000) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
n2614), .CK(clk), .RN(n5094), .Q(add_subt_module_Add_Subt_result[18]),
.QN(n4999) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ (
.D(n2936), .CK(clk), .RN(n5091), .Q(add_subt_module_add_overflow_flag),
.QN(n4993) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(
n2586), .CK(clk), .RN(n5104), .Q(
add_subt_module_Sgf_normalized_result[51]), .QN(n4992) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(
n2587), .CK(clk), .RN(n5104), .Q(
add_subt_module_Sgf_normalized_result[52]), .QN(n4991) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
n2612), .CK(clk), .RN(n5094), .Q(add_subt_module_Add_Subt_result[16]),
.QN(n4990) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
n2616), .CK(clk), .RN(n5094), .Q(add_subt_module_Add_Subt_result[20]),
.QN(n4989) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(
n2632), .CK(clk), .RN(n5094), .Q(add_subt_module_Add_Subt_result[36]),
.QN(n4988) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(
n2622), .CK(clk), .RN(n5091), .Q(add_subt_module_Add_Subt_result[26]),
.QN(n4987) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(
n2631), .CK(clk), .RN(n5101), .Q(add_subt_module_Add_Subt_result[35]),
.QN(n4986) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
n2597), .CK(clk), .RN(n5107), .Q(add_subt_module_Add_Subt_result[1]),
.QN(n4983) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
n2598), .CK(clk), .RN(n2961), .Q(add_subt_module_Add_Subt_result[2]),
.QN(n4982) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(
n2585), .CK(clk), .RN(n5104), .Q(
add_subt_module_Sgf_normalized_result[50]), .QN(n4977) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(
n2636), .CK(clk), .RN(n5098), .Q(add_subt_module_Add_Subt_result[40]),
.QN(n4976) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
n2602), .CK(clk), .RN(n5096), .Q(add_subt_module_Add_Subt_result[6]),
.QN(n4975) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(
n2628), .CK(clk), .RN(n3015), .Q(add_subt_module_Add_Subt_result[32]),
.QN(n4974) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(
n2645), .CK(clk), .RN(n5103), .Q(add_subt_module_Add_Subt_result[49]),
.QN(n4973) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(
n2642), .CK(clk), .RN(n5096), .Q(add_subt_module_Add_Subt_result[46]),
.QN(n4972) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
n2600), .CK(clk), .RN(n5091), .Q(add_subt_module_Add_Subt_result[4]),
.QN(n4971) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(
n2637), .CK(clk), .RN(n5098), .Q(add_subt_module_Add_Subt_result[41]),
.QN(n4970) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(
n2624), .CK(clk), .RN(n3015), .Q(add_subt_module_Add_Subt_result[28]),
.QN(n4969) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n2926), .CK(clk), .RN(n5159), .Q(
cont_var_out[0]), .QN(n4968) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(
n2583), .CK(clk), .RN(n5103), .Q(
add_subt_module_Sgf_normalized_result[48]), .QN(n4967) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(
n2584), .CK(clk), .RN(n5099), .Q(
add_subt_module_Sgf_normalized_result[49]), .QN(n4966) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
n2605), .CK(clk), .RN(n5091), .Q(add_subt_module_Add_Subt_result[9]),
.QN(n4965) );
DFFRX2TS add_subt_module_XRegister_Q_reg_25_ ( .D(n1760), .CK(clk), .RN(
n5082), .Q(add_subt_module_intDX[25]), .QN(n4964) );
DFFRX2TS add_subt_module_XRegister_Q_reg_35_ ( .D(n1792), .CK(clk), .RN(
n5093), .Q(add_subt_module_intDX[35]), .QN(n4963) );
DFFRX2TS add_subt_module_XRegister_Q_reg_45_ ( .D(n1857), .CK(clk), .RN(
n5096), .Q(add_subt_module_intDX[45]), .QN(n4962) );
DFFRX1TS add_subt_module_YRegister_Q_reg_0_ ( .D(n1958), .CK(clk), .RN(n5107), .Q(add_subt_module_intDY[0]), .QN(n4961) );
DFFRX2TS add_subt_module_XRegister_Q_reg_3_ ( .D(n1887), .CK(clk), .RN(n5090), .Q(add_subt_module_intDX[3]), .QN(n4960) );
DFFRX2TS add_subt_module_XRegister_Q_reg_8_ ( .D(n1819), .CK(clk), .RN(n5092), .Q(add_subt_module_intDX[8]), .QN(n4959) );
DFFRX2TS add_subt_module_XRegister_Q_reg_18_ ( .D(n1763), .CK(clk), .RN(
n5097), .Q(add_subt_module_intDX[18]), .QN(n4958) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(
n2581), .CK(clk), .RN(n5091), .Q(
add_subt_module_Sgf_normalized_result[46]), .QN(n4957) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(
n2582), .CK(clk), .RN(n5096), .Q(
add_subt_module_Sgf_normalized_result[47]), .QN(n4956) );
DFFRX1TS add_subt_module_XRegister_Q_reg_13_ ( .D(n1850), .CK(clk), .RN(
n5096), .Q(add_subt_module_intDX[13]), .QN(n4955) );
DFFRX1TS add_subt_module_XRegister_Q_reg_51_ ( .D(n1907), .CK(clk), .RN(
n5107), .Q(add_subt_module_intDX[51]), .QN(n4954) );
DFFRX1TS add_subt_module_XRegister_Q_reg_48_ ( .D(n1901), .CK(clk), .RN(
n5107), .Q(add_subt_module_intDX[48]), .QN(n4953) );
DFFRX2TS add_subt_module_XRegister_Q_reg_30_ ( .D(n1795), .CK(clk), .RN(
n5093), .Q(add_subt_module_intDX[30]), .QN(n4952) );
DFFRX1TS add_subt_module_XRegister_Q_reg_4_ ( .D(n1904), .CK(clk), .RN(n5107), .Q(add_subt_module_intDX[4]), .QN(n4951) );
DFFRX2TS add_subt_module_XRegister_Q_reg_12_ ( .D(n1829), .CK(clk), .RN(
n5092), .Q(add_subt_module_intDX[12]), .QN(n4950) );
DFFRX1TS add_subt_module_XRegister_Q_reg_32_ ( .D(n1749), .CK(clk), .RN(
n5082), .Q(add_subt_module_intDX[32]), .QN(n4949) );
DFFRX2TS add_subt_module_XRegister_Q_reg_29_ ( .D(n1770), .CK(clk), .RN(
n5101), .Q(add_subt_module_intDX[29]), .QN(n4948) );
DFFRX1TS add_subt_module_YRegister_Q_reg_54_ ( .D(n1949), .CK(clk), .RN(
n3018), .Q(add_subt_module_intDY[54]), .QN(n4947) );
DFFRX1TS add_subt_module_XRegister_Q_reg_2_ ( .D(n1897), .CK(clk), .RN(n5090), .Q(add_subt_module_intDX[2]), .QN(n4946) );
DFFRX2TS add_subt_module_YRegister_Q_reg_61_ ( .D(n1956), .CK(clk), .RN(
n5085), .QN(n4945) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n2939), .CK(clk), .RN(n2961), .Q(
cordic_FSM_state_reg[2]), .QN(n4944) );
DFFRX2TS add_subt_module_XRegister_Q_reg_27_ ( .D(n1778), .CK(clk), .RN(
n5106), .Q(add_subt_module_intDX[27]), .QN(n4943) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(
n2579), .CK(clk), .RN(n5091), .Q(
add_subt_module_Sgf_normalized_result[44]), .QN(n4942) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(
n2580), .CK(clk), .RN(n5103), .Q(
add_subt_module_Sgf_normalized_result[45]), .QN(n4941) );
DFFRX2TS add_subt_module_XRegister_Q_reg_20_ ( .D(n1853), .CK(clk), .RN(
n5099), .Q(add_subt_module_intDX[20]), .QN(n4940) );
DFFRX2TS add_subt_module_XRegister_Q_reg_17_ ( .D(n1752), .CK(clk), .RN(
n5095), .Q(add_subt_module_intDX[17]), .QN(n4939) );
DFFRX2TS add_subt_module_XRegister_Q_reg_21_ ( .D(n1766), .CK(clk), .RN(
n5098), .Q(add_subt_module_intDX[21]), .QN(n4938) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
n2609), .CK(clk), .RN(n5098), .Q(add_subt_module_Add_Subt_result[13]),
.QN(n4936) );
DFFRX2TS add_subt_module_YRegister_Q_reg_13_ ( .D(n1849), .CK(clk), .RN(
n5103), .Q(add_subt_module_intDY[13]), .QN(n4935) );
DFFRX2TS add_subt_module_YRegister_Q_reg_16_ ( .D(n1872), .CK(clk), .RN(
n3015), .Q(add_subt_module_intDY[16]), .QN(n4934) );
DFFRX2TS add_subt_module_XRegister_Q_reg_15_ ( .D(n1788), .CK(clk), .RN(
n5108), .Q(add_subt_module_intDX[15]), .QN(n4933) );
DFFRX2TS add_subt_module_XRegister_Q_reg_49_ ( .D(n1881), .CK(clk), .RN(
n2962), .Q(add_subt_module_intDX[49]), .QN(n4932) );
DFFRX1TS add_subt_module_XRegister_Q_reg_9_ ( .D(n1870), .CK(clk), .RN(n5080), .Q(add_subt_module_intDX[9]), .QN(n4931) );
DFFRX2TS add_subt_module_XRegister_Q_reg_28_ ( .D(n1739), .CK(clk), .RN(
n5091), .Q(add_subt_module_intDX[28]), .QN(n4930) );
DFFRX1TS add_subt_module_XRegister_Q_reg_37_ ( .D(n1809), .CK(clk), .RN(
n5109), .Q(add_subt_module_intDX[37]), .QN(n4929) );
DFFRX1TS add_subt_module_XRegister_Q_reg_40_ ( .D(n1837), .CK(clk), .RN(
n5107), .Q(add_subt_module_intDX[40]), .QN(n4928) );
DFFRX2TS add_subt_module_XRegister_Q_reg_46_ ( .D(n1877), .CK(clk), .RN(
n3015), .Q(add_subt_module_intDX[46]), .QN(n4927) );
DFFRX2TS add_subt_module_YRegister_Q_reg_52_ ( .D(n1947), .CK(clk), .RN(
n5107), .Q(add_subt_module_intDY[52]), .QN(n4926) );
DFFRX1TS add_subt_module_YRegister_Q_reg_56_ ( .D(n1951), .CK(clk), .RN(
n5107), .Q(add_subt_module_intDY[56]), .QN(n4925) );
DFFRX2TS add_subt_module_XRegister_Q_reg_23_ ( .D(n1798), .CK(clk), .RN(
n5093), .Q(add_subt_module_intDX[23]), .QN(n4924) );
DFFRX2TS add_subt_module_XRegister_Q_reg_43_ ( .D(n1844), .CK(clk), .RN(
n2961), .Q(add_subt_module_intDX[43]), .QN(n4923) );
DFFRX1TS add_subt_module_XRegister_Q_reg_1_ ( .D(n1884), .CK(clk), .RN(n5085), .Q(add_subt_module_intDX[1]), .QN(n4922) );
DFFRX1TS add_subt_module_XRegister_Q_reg_16_ ( .D(n1873), .CK(clk), .RN(
n5109), .Q(add_subt_module_intDX[16]), .QN(n4921) );
DFFRX1TS add_subt_module_XRegister_Q_reg_6_ ( .D(n1863), .CK(clk), .RN(n2961), .Q(add_subt_module_intDX[6]), .QN(n4920) );
DFFRX1TS add_subt_module_XRegister_Q_reg_39_ ( .D(n1812), .CK(clk), .RN(
n2962), .Q(add_subt_module_intDX[39]), .QN(n4919) );
DFFRX1TS add_subt_module_XRegister_Q_reg_44_ ( .D(n1867), .CK(clk), .RN(
n2961), .Q(add_subt_module_intDX[44]), .QN(n4918) );
DFFRX1TS add_subt_module_XRegister_Q_reg_47_ ( .D(n1891), .CK(clk), .RN(
n5100), .Q(add_subt_module_intDX[47]), .QN(n4917) );
DFFRX2TS add_subt_module_XRegister_Q_reg_11_ ( .D(n1826), .CK(clk), .RN(
n5092), .Q(add_subt_module_intDX[11]), .QN(n4916) );
DFFRX2TS add_subt_module_XRegister_Q_reg_33_ ( .D(n1756), .CK(clk), .RN(
n5095), .Q(add_subt_module_intDX[33]), .QN(n4915) );
DFFRX2TS add_subt_module_XRegister_Q_reg_36_ ( .D(n1785), .CK(clk), .RN(
n5106), .Q(add_subt_module_intDX[36]), .QN(n4914) );
DFFRX2TS add_subt_module_YRegister_Q_reg_62_ ( .D(n1957), .CK(clk), .RN(
n3021), .Q(add_subt_module_intDY[62]), .QN(n4913) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(
n2577), .CK(clk), .RN(n5102), .Q(
add_subt_module_Sgf_normalized_result[42]), .QN(n4912) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(
n2578), .CK(clk), .RN(n5102), .Q(
add_subt_module_Sgf_normalized_result[43]), .QN(n4911) );
DFFRX2TS add_subt_module_XRegister_Q_reg_41_ ( .D(n1816), .CK(clk), .RN(
n5109), .Q(add_subt_module_intDX[41]), .QN(n4910) );
DFFRX2TS add_subt_module_YRegister_Q_reg_6_ ( .D(n1862), .CK(clk), .RN(n2961), .Q(add_subt_module_intDY[6]), .QN(n4909) );
DFFRX2TS add_subt_module_XRegister_Q_reg_59_ ( .D(n1933), .CK(clk), .RN(
n5105), .Q(add_subt_module_intDX[59]), .QN(n4908) );
DFFRX1TS add_subt_module_XRegister_Q_reg_5_ ( .D(n1860), .CK(clk), .RN(n5084), .Q(add_subt_module_intDX[5]), .QN(n4907) );
DFFRX1TS add_subt_module_XRegister_Q_reg_7_ ( .D(n1840), .CK(clk), .RN(n2961), .Q(add_subt_module_intDX[7]), .QN(n4906) );
DFFRX1TS add_subt_module_YRegister_Q_reg_55_ ( .D(n1950), .CK(clk), .RN(
n3021), .Q(add_subt_module_intDY[55]), .QN(n4905) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(
n2576), .CK(clk), .RN(n5102), .Q(
add_subt_module_Sgf_normalized_result[41]), .QN(n4904) );
DFFRX2TS add_subt_module_YRegister_Q_reg_5_ ( .D(n1859), .CK(clk), .RN(n5084), .Q(add_subt_module_intDY[5]), .QN(n4903) );
DFFRX2TS add_subt_module_YRegister_Q_reg_37_ ( .D(n1808), .CK(clk), .RN(
n5085), .Q(add_subt_module_intDY[37]), .QN(n4902) );
DFFRX2TS add_subt_module_XRegister_Q_reg_57_ ( .D(n1927), .CK(clk), .RN(
n5089), .Q(add_subt_module_intDX[57]), .QN(n4901) );
DFFRX2TS add_subt_module_YRegister_Q_reg_38_ ( .D(n1832), .CK(clk), .RN(
n5081), .Q(add_subt_module_intDY[38]), .QN(n4900) );
DFFRX2TS add_subt_module_YRegister_Q_reg_10_ ( .D(n1846), .CK(clk), .RN(
n5091), .Q(add_subt_module_intDY[10]), .QN(n4899) );
DFFRX2TS add_subt_module_YRegister_Q_reg_44_ ( .D(n1866), .CK(clk), .RN(
n5080), .Q(add_subt_module_intDY[44]), .QN(n4898) );
DFFRX2TS add_subt_module_XRegister_Q_reg_53_ ( .D(n1915), .CK(clk), .RN(
n5105), .Q(add_subt_module_intDX[53]), .QN(n4897) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(
n2574), .CK(clk), .RN(n5102), .Q(
add_subt_module_Sgf_normalized_result[39]), .QN(n4896) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(
n2575), .CK(clk), .RN(n5102), .Q(
add_subt_module_Sgf_normalized_result[40]), .QN(n4895) );
DFFRX1TS add_subt_module_Sel_B_Q_reg_0_ ( .D(n2664), .CK(clk), .RN(n1959),
.Q(add_subt_module_FSM_selector_B[0]), .QN(n4894) );
DFFRX2TS add_subt_module_YRegister_Q_reg_1_ ( .D(n1883), .CK(clk), .RN(n5094), .Q(add_subt_module_intDY[1]), .QN(n4893) );
DFFRX2TS add_subt_module_XRegister_Q_reg_60_ ( .D(n1936), .CK(clk), .RN(
n5105), .Q(add_subt_module_intDX[60]), .QN(n4892) );
DFFRX2TS add_subt_module_XRegister_Q_reg_54_ ( .D(n1918), .CK(clk), .RN(
n5089), .Q(add_subt_module_intDX[54]), .QN(n4891) );
DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n2938), .CK(clk), .RN(n2961), .Q(
cordic_FSM_state_reg[0]), .QN(n4890) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(
n2572), .CK(clk), .RN(n5097), .Q(
add_subt_module_Sgf_normalized_result[37]), .QN(n4889) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(
n2573), .CK(clk), .RN(n5102), .Q(
add_subt_module_Sgf_normalized_result[38]), .QN(n4888) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(
n2570), .CK(clk), .RN(n5098), .Q(
add_subt_module_Sgf_normalized_result[35]), .QN(n4886) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(
n2571), .CK(clk), .RN(n5101), .Q(
add_subt_module_Sgf_normalized_result[36]), .QN(n4885) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_0_ ( .D(n2929), .CK(clk),
.RN(n5080), .Q(add_subt_module_FS_Module_state_reg[0]), .QN(n4884) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(
n2568), .CK(clk), .RN(n5098), .Q(
add_subt_module_Sgf_normalized_result[33]), .QN(n4883) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(
n2569), .CK(clk), .RN(n5101), .Q(
add_subt_module_Sgf_normalized_result[34]), .QN(n4882) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(
n2567), .CK(clk), .RN(n5097), .Q(
add_subt_module_Sgf_normalized_result[32]), .QN(n4881) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
n2621), .CK(clk), .RN(n5091), .Q(add_subt_module_Add_Subt_result[25]),
.QN(n4880) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(
n2565), .CK(clk), .RN(n5093), .Q(
add_subt_module_Sgf_normalized_result[30]), .QN(n4879) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(
n2566), .CK(clk), .RN(n5079), .Q(
add_subt_module_Sgf_normalized_result[31]), .QN(n4878) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(
n2562), .CK(clk), .RN(n5102), .Q(
add_subt_module_Sgf_normalized_result[27]), .QN(n4877) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(
n2563), .CK(clk), .RN(n5106), .Q(
add_subt_module_Sgf_normalized_result[28]), .QN(n4876) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(
n2564), .CK(clk), .RN(n5108), .Q(
add_subt_module_Sgf_normalized_result[29]), .QN(n4875) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(
n2561), .CK(clk), .RN(n5079), .Q(
add_subt_module_Sgf_normalized_result[26]), .QN(n4874) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(
n2559), .CK(clk), .RN(n5094), .Q(
add_subt_module_Sgf_normalized_result[24]), .QN(n4873) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(
n2560), .CK(clk), .RN(n5099), .Q(
add_subt_module_Sgf_normalized_result[25]), .QN(n4872) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(
n2558), .CK(clk), .RN(n3015), .Q(
add_subt_module_Sgf_normalized_result[23]), .QN(n4871) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(
n2629), .CK(clk), .RN(n5094), .Q(add_subt_module_Add_Subt_result[33]),
.QN(n4870) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(
n2556), .CK(clk), .RN(n5097), .Q(
add_subt_module_Sgf_normalized_result[21]), .QN(n4869) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(
n2557), .CK(clk), .RN(n5104), .Q(
add_subt_module_Sgf_normalized_result[22]), .QN(n4868) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(
n2554), .CK(clk), .RN(n5092), .Q(
add_subt_module_Sgf_normalized_result[19]), .QN(n4867) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(
n2552), .CK(clk), .RN(n5079), .Q(
add_subt_module_Sgf_normalized_result[17]), .QN(n4865) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(
n2553), .CK(clk), .RN(n5079), .Q(
add_subt_module_Sgf_normalized_result[18]), .QN(n4864) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(
n2550), .CK(clk), .RN(n5079), .Q(
add_subt_module_Sgf_normalized_result[15]), .QN(n4863) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(
n2551), .CK(clk), .RN(n5092), .Q(
add_subt_module_Sgf_normalized_result[16]), .QN(n4862) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(
n2547), .CK(clk), .RN(n5100), .Q(
add_subt_module_Sgf_normalized_result[12]), .QN(n4860) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(
n2548), .CK(clk), .RN(n5100), .Q(
add_subt_module_Sgf_normalized_result[13]), .QN(n4859) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(
n2545), .CK(clk), .RN(n5090), .Q(
add_subt_module_Sgf_normalized_result[10]), .QN(n4858) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(
n2546), .CK(clk), .RN(n5090), .Q(
add_subt_module_Sgf_normalized_result[11]), .QN(n4857) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(
n2543), .CK(clk), .RN(n5090), .Q(
add_subt_module_Sgf_normalized_result[8]), .QN(n4855) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(
n2544), .CK(clk), .RN(n5100), .Q(
add_subt_module_Sgf_normalized_result[9]), .QN(n4854) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(
n2541), .CK(clk), .RN(n5093), .Q(
add_subt_module_Sgf_normalized_result[6]), .QN(n4853) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(
n2542), .CK(clk), .RN(n5093), .Q(
add_subt_module_Sgf_normalized_result[7]), .QN(n4852) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(
n2540), .CK(clk), .RN(n5102), .Q(
add_subt_module_Sgf_normalized_result[5]), .QN(n4851) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(
n2643), .CK(clk), .RN(n5099), .Q(add_subt_module_Add_Subt_result[47]),
.QN(n4850) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(
n2538), .CK(clk), .RN(n5098), .Q(
add_subt_module_Sgf_normalized_result[3]), .QN(n4849) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(
n2539), .CK(clk), .RN(n5108), .Q(
add_subt_module_Sgf_normalized_result[4]), .QN(n4848) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(
n2537), .CK(clk), .RN(n5098), .Q(
add_subt_module_Sgf_normalized_result[2]), .QN(n4847) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ (
.D(n2386), .CK(clk), .RN(n5088), .Q(result_add_subt[25]), .QN(n4846)
);
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ (
.D(n2933), .CK(clk), .RN(n5081), .Q(result_add_subt[63]), .QN(n4845)
);
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(
n2595), .CK(clk), .RN(n2962), .Q(add_subt_module_Add_Subt_result[54]),
.QN(n4844) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
n2608), .CK(clk), .RN(n5097), .Q(add_subt_module_Add_Subt_result[12]),
.QN(n4843) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
n2607), .CK(clk), .RN(n5101), .Q(add_subt_module_Add_Subt_result[11]),
.QN(n4842) );
DFFRX2TS add_subt_module_YRegister_Q_reg_59_ ( .D(n1954), .CK(clk), .RN(
n2962), .Q(add_subt_module_intDY[59]), .QN(n4841) );
DFFRX2TS add_subt_module_YRegister_Q_reg_60_ ( .D(n1955), .CK(clk), .RN(
n2962), .Q(add_subt_module_intDY[60]), .QN(n4840) );
DFFRX2TS add_subt_module_XRegister_Q_reg_19_ ( .D(n1804), .CK(clk), .RN(
n3015), .Q(add_subt_module_intDX[19]), .QN(n4839) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(
n2633), .CK(clk), .RN(n5094), .Q(add_subt_module_Add_Subt_result[37]),
.QN(n4838) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
n2599), .CK(clk), .RN(n2961), .Q(add_subt_module_Add_Subt_result[3]),
.QN(n4837) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
n2606), .CK(clk), .RN(n5097), .Q(add_subt_module_Add_Subt_result[10]),
.QN(n4836) );
DFFRX1TS add_subt_module_YRegister_Q_reg_53_ ( .D(n1948), .CK(clk), .RN(
n2962), .Q(add_subt_module_intDY[53]), .QN(n4835) );
DFFRX1TS add_subt_module_XRegister_Q_reg_24_ ( .D(n1745), .CK(clk), .RN(
n5091), .Q(add_subt_module_intDX[24]), .QN(n4834) );
DFFRX1TS add_subt_module_XRegister_Q_reg_38_ ( .D(n1833), .CK(clk), .RN(
n5087), .Q(add_subt_module_intDX[38]), .QN(n4833) );
DFFRX2TS add_subt_module_XRegister_Q_reg_34_ ( .D(n1801), .CK(clk), .RN(
n5093), .Q(add_subt_module_intDX[34]), .QN(n4832) );
DFFRX2TS add_subt_module_XRegister_Q_reg_42_ ( .D(n1823), .CK(clk), .RN(
n5092), .Q(add_subt_module_intDX[42]), .QN(n4831) );
DFFRX2TS add_subt_module_XRegister_Q_reg_50_ ( .D(n1894), .CK(clk), .RN(
n5100), .Q(add_subt_module_intDX[50]), .QN(n4830) );
DFFRX2TS add_subt_module_XRegister_Q_reg_26_ ( .D(n1735), .CK(clk), .RN(
n5096), .Q(add_subt_module_intDX[26]), .QN(n4829) );
DFFRX2TS add_subt_module_XRegister_Q_reg_14_ ( .D(n1781), .CK(clk), .RN(
n5108), .Q(add_subt_module_intDX[14]), .QN(n4828) );
DFFRX2TS add_subt_module_XRegister_Q_reg_22_ ( .D(n1742), .CK(clk), .RN(
n5099), .Q(add_subt_module_intDX[22]), .QN(n4827) );
DFFRX2TS add_subt_module_XRegister_Q_reg_31_ ( .D(n1774), .CK(clk), .RN(
n5098), .Q(add_subt_module_intDX[31]), .QN(n4826) );
DFFRX2TS add_subt_module_YRegister_Q_reg_7_ ( .D(n1839), .CK(clk), .RN(n2961), .Q(add_subt_module_intDY[7]), .QN(n4825) );
DFFRX1TS add_subt_module_XRegister_Q_reg_10_ ( .D(n1847), .CK(clk), .RN(
n5099), .Q(add_subt_module_intDX[10]), .QN(n4824) );
DFFRX2TS add_subt_module_XRegister_Q_reg_58_ ( .D(n1930), .CK(clk), .RN(
n5086), .Q(add_subt_module_intDX[58]), .QN(n4823) );
DFFRX2TS add_subt_module_YRegister_Q_reg_4_ ( .D(n1903), .CK(clk), .RN(n5095), .Q(add_subt_module_intDY[4]), .QN(n4822) );
DFFRX2TS add_subt_module_XRegister_Q_reg_55_ ( .D(n1921), .CK(clk), .RN(
n5086), .Q(add_subt_module_intDX[55]), .QN(n4821) );
DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n5080), .Q(cordic_FSM_state_reg[1]), .QN(n4819) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_2_ ( .D(n2927), .CK(clk),
.RN(n2961), .Q(add_subt_module_FS_Module_state_reg[2]), .QN(n4818) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_3_ ( .D(n2930), .CK(clk),
.RN(n2961), .Q(add_subt_module_FS_Module_state_reg[3]), .QN(n4817) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
n2613), .CK(clk), .RN(n5094), .Q(add_subt_module_Add_Subt_result[17]),
.QN(n4815) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(
n2647), .CK(clk), .RN(n5107), .Q(add_subt_module_Add_Subt_result[51]),
.QN(n4814) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
n2610), .CK(clk), .RN(n5101), .Q(add_subt_module_Add_Subt_result[14]),
.QN(n4813) );
DFFRX2TS cordic_FSM_state_reg_reg_3_ ( .D(n2940), .CK(clk), .RN(n5084), .Q(
cordic_FSM_state_reg[3]), .QN(n4812) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_1_ ( .D(n2928), .CK(clk),
.RN(n5084), .Q(add_subt_module_FS_Module_state_reg[1]), .QN(n4811) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(
n2639), .CK(clk), .RN(n5101), .Q(add_subt_module_Add_Subt_result[43]),
.QN(n4810) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(
n2638), .CK(clk), .RN(n5097), .Q(add_subt_module_Add_Subt_result[42]),
.QN(n4809) );
DFFRX2TS add_subt_module_YRegister_Q_reg_3_ ( .D(n1886), .CK(clk), .RN(n5100), .Q(add_subt_module_intDY[3]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_35_ ( .D(n1791), .CK(clk), .RN(
n5093), .Q(add_subt_module_intDY[35]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(
n5101), .Q(add_subt_module_intDY[29]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_33_ ( .D(n1755), .CK(clk), .RN(
n5082), .Q(add_subt_module_intDY[33]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_15_ ( .D(n1787), .CK(clk), .RN(
n5108), .Q(add_subt_module_intDY[15]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_31_ ( .D(n1773), .CK(clk), .RN(
n5097), .Q(add_subt_module_intDY[31]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_21_ ( .D(n1765), .CK(clk), .RN(
n5098), .Q(add_subt_module_intDY[21]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_23_ ( .D(n1797), .CK(clk), .RN(
n5093), .Q(add_subt_module_intDY[23]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_43_ ( .D(n1843), .CK(clk), .RN(
n5084), .Q(add_subt_module_intDY[43]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_41_ ( .D(n1815), .CK(clk), .RN(
n5088), .Q(add_subt_module_intDY[41]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(
n2646), .CK(clk), .RN(n5103), .Q(add_subt_module_Add_Subt_result[50])
);
DFFRX2TS add_subt_module_YRegister_Q_reg_45_ ( .D(n1856), .CK(clk), .RN(
n5099), .Q(add_subt_module_intDY[45]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_18_ ( .D(n1762), .CK(clk), .RN(
n5094), .Q(add_subt_module_intDY[18]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_25_ ( .D(n1759), .CK(clk), .RN(
n5095), .Q(add_subt_module_intDY[25]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(
n2641), .CK(clk), .RN(n5099), .Q(add_subt_module_Add_Subt_result[45])
);
DFFRX2TS add_subt_module_YRegister_Q_reg_49_ ( .D(n1880), .CK(clk), .RN(
n5109), .Q(add_subt_module_intDY[49]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_11_ ( .D(n1825), .CK(clk), .RN(
n5092), .Q(add_subt_module_intDY[11]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_26_ ( .D(n1734), .CK(clk), .RN(
n5091), .Q(add_subt_module_intDY[26]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_50_ ( .D(n1893), .CK(clk), .RN(
n5090), .Q(add_subt_module_intDY[50]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_36_ ( .D(n1784), .CK(clk), .RN(
n5108), .Q(add_subt_module_intDY[36]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_61_ ( .D(n1939), .CK(clk), .RN(
n5089), .Q(add_subt_module_intDX[61]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_19_ ( .D(n1803), .CK(clk), .RN(
n3015), .Q(add_subt_module_intDY[19]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_27_ ( .D(n1777), .CK(clk), .RN(
n5108), .Q(add_subt_module_intDY[27]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(
n2648), .CK(clk), .RN(n5099), .Q(add_subt_module_Add_Subt_result[52])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(
n2625), .CK(clk), .RN(n5104), .Q(add_subt_module_Add_Subt_result[29])
);
DFFRX2TS add_subt_module_YRegister_Q_reg_9_ ( .D(n1869), .CK(clk), .RN(n2961), .Q(add_subt_module_intDY[9]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_47_ ( .D(n1890), .CK(clk), .RN(
n5090), .Q(add_subt_module_intDY[47]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
n2604), .CK(clk), .RN(n5096), .Q(add_subt_module_Add_Subt_result[8])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
n2619), .CK(clk), .RN(n5094), .Q(add_subt_module_Add_Subt_result[23])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(
n2634), .CK(clk), .RN(n5097), .Q(add_subt_module_Add_Subt_result[38])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(
n2630), .CK(clk), .RN(n5098), .Q(add_subt_module_Add_Subt_result[34])
);
DFFRX2TS reg_val_muxY_2stage_Q_reg_56_ ( .D(n2110), .CK(clk), .RN(n5143),
.Q(d_ff2_Y[56]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
n2620), .CK(clk), .RN(n5101), .Q(add_subt_module_Add_Subt_result[24])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
n2601), .CK(clk), .RN(n5091), .Q(add_subt_module_Add_Subt_result[5])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
n2615), .CK(clk), .RN(n5101), .Q(add_subt_module_Add_Subt_result[19])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(
n2635), .CK(clk), .RN(n5101), .Q(add_subt_module_Add_Subt_result[39])
);
DFFRX2TS reg_val_muxX_2stage_Q_reg_56_ ( .D(n2787), .CK(clk), .RN(n5119),
.Q(d_ff2_X[56]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
n2617), .CK(clk), .RN(n5097), .Q(add_subt_module_Add_Subt_result[21])
);
DFFRX2TS add_subt_module_Sel_B_Q_reg_1_ ( .D(n2935), .CK(clk), .RN(n1959),
.Q(add_subt_module_FSM_selector_B[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n2267), .CK(clk), .RN(n5121),
.Q(d_ff2_Z[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_33_ ( .D(n2415), .CK(clk), .RN(n5121), .Q(
d_ff_Xn[33]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]),
.CK(clk), .RN(n5080), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]),
.CK(clk), .RN(n3018), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]),
.CK(clk), .RN(n5083), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_57_ ( .D(n2788), .CK(clk), .RN(n5143),
.Q(d_ff2_X[57]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_59_ ( .D(n2790), .CK(clk), .RN(n5144),
.Q(d_ff2_X[59]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(n2792), .CK(clk), .RN(n5146),
.Q(d_ff2_X[61]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_59_ ( .D(n2107), .CK(clk), .RN(n5145),
.Q(d_ff2_Y[59]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[52]),
.CK(clk), .RN(n5083), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]),
.CK(clk), .RN(n5083), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(
n2535), .CK(clk), .RN(n5088), .Q(
add_subt_module_Sgf_normalized_result[0]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[53]),
.CK(clk), .RN(n5082), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n2925), .CK(clk), .RN(n5159), .Q(
cont_var_out[1]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n2657), .CK(clk), .RN(n5104), .Q(add_subt_module_exp_oper_result[4]) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n2919), .CK(clk), .RN(n5158), .Q(
d_ff1_shift_region_flag_out[0]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n2658), .CK(clk), .RN(n5093), .Q(add_subt_module_exp_oper_result[5]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n2651),
.CK(clk), .RN(n2961), .Q(overflow_flag) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ (
.D(n2494), .CK(clk), .RN(n5081), .Q(result_add_subt[52]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ (
.D(n2418), .CK(clk), .RN(n3021), .Q(result_add_subt[33]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ (
.D(n2426), .CK(clk), .RN(n5089), .Q(result_add_subt[35]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ (
.D(n2318), .CK(clk), .RN(n5088), .Q(result_add_subt[8]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ (
.D(n2438), .CK(clk), .RN(n2961), .Q(result_add_subt[38]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ (
.D(n2314), .CK(clk), .RN(n5080), .Q(result_add_subt[7]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ (
.D(n2326), .CK(clk), .RN(n5084), .Q(result_add_subt[10]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ (
.D(n2306), .CK(clk), .RN(n5088), .Q(result_add_subt[5]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ (
.D(n2310), .CK(clk), .RN(n5088), .Q(result_add_subt[6]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ (
.D(n2322), .CK(clk), .RN(n5088), .Q(result_add_subt[9]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ (
.D(n2482), .CK(clk), .RN(n5083), .Q(result_add_subt[49]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ (
.D(n2290), .CK(clk), .RN(n5083), .Q(result_add_subt[1]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ (
.D(n2298), .CK(clk), .RN(n5083), .Q(result_add_subt[3]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ (
.D(n2294), .CK(clk), .RN(n5095), .Q(result_add_subt[2]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ (
.D(n2302), .CK(clk), .RN(n5082), .Q(result_add_subt[4]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ (
.D(n2490), .CK(clk), .RN(n5095), .Q(result_add_subt[51]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ (
.D(n2286), .CK(clk), .RN(n5095), .Q(result_add_subt[0]) );
DFFRX1TS add_subt_module_YRegister_Q_reg_58_ ( .D(n1953), .CK(clk), .RN(
n2962), .Q(add_subt_module_intDY[58]) );
DFFRX1TS add_subt_module_YRegister_Q_reg_57_ ( .D(n1952), .CK(clk), .RN(
n5088), .Q(add_subt_module_intDY[57]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(n2113), .CK(clk), .RN(n5142),
.Q(d_ff2_Y[53]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(n2785), .CK(clk), .RN(n5142),
.Q(d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_55_ ( .D(n2786), .CK(clk), .RN(n5128),
.Q(d_ff2_X[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(n2112), .CK(clk), .RN(n5142),
.Q(d_ff2_Y[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(n2111), .CK(clk), .RN(n5119),
.Q(d_ff2_Y[55]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_63_ ( .D(n2221), .CK(clk), .RN(n5147),
.Q(d_ff2_Z[63]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_62_ ( .D(n2793), .CK(clk), .RN(n5146),
.Q(d_ff2_X[62]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ (
.D(n2590), .CK(clk), .RN(n5086), .Q(add_subt_module_LZA_output[4]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n2387), .CK(clk), .RN(n5144), .Q(
d_ff_Xn[26]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n2395), .CK(clk), .RN(n5113), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n2379), .CK(clk), .RN(n5142), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_32_ ( .D(n2411), .CK(clk), .RN(n5114), .Q(
d_ff_Xn[32]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n2399), .CK(clk), .RN(n5117), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n2407), .CK(clk), .RN(n5118), .Q(
d_ff_Xn[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n2339), .CK(clk), .RN(n5120), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_36_ ( .D(n2427), .CK(clk), .RN(n5120), .Q(
d_ff_Xn[36]) );
DFFRX1TS d_ff4_Xn_Q_reg_34_ ( .D(n2419), .CK(clk), .RN(n5123), .Q(
d_ff_Xn[34]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n2359), .CK(clk), .RN(n5124), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n2335), .CK(clk), .RN(n5131), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n2391), .CK(clk), .RN(n5119), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n2403), .CK(clk), .RN(n5122), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n2375), .CK(clk), .RN(n5122), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Xn_Q_reg_37_ ( .D(n2431), .CK(clk), .RN(n5125), .Q(
d_ff_Xn[37]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n2383), .CK(clk), .RN(n5115), .Q(
d_ff_Xn[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n2162), .CK(clk), .RN(n5113),
.Q(d_ff2_Y[28]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n2170), .CK(clk), .RN(n5145),
.Q(d_ff2_Y[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n2184), .CK(clk), .RN(n5123),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n2182), .CK(clk), .RN(n5116),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_39_ ( .D(n2140), .CK(clk), .RN(n5125),
.Q(d_ff2_Y[39]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n2202), .CK(clk), .RN(n5127), .Q(
d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_42_ ( .D(n2134), .CK(clk), .RN(n5128),
.Q(d_ff2_Y[42]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n2196), .CK(clk), .RN(n5128),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n2200), .CK(clk), .RN(n5156), .Q(
d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n2186), .CK(clk), .RN(n5134),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_46_ ( .D(n2126), .CK(clk), .RN(n5134),
.Q(d_ff2_Y[46]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n2216), .CK(clk), .RN(n5136), .Q(
d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_47_ ( .D(n2124), .CK(clk), .RN(n5137),
.Q(d_ff2_Y[47]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_50_ ( .D(n2118), .CK(clk), .RN(n5138),
.Q(d_ff2_Y[50]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n2214), .CK(clk), .RN(n5118), .Q(
d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_48_ ( .D(n2122), .CK(clk), .RN(n5139),
.Q(d_ff2_Y[48]) );
DFFRX1TS d_ff4_Xn_Q_reg_58_ ( .D(n2515), .CK(clk), .RN(n5144), .Q(
d_ff_Xn[58]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_41_ ( .D(n2751), .CK(clk), .RN(n5126),
.Q(d_ff2_X[41]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_45_ ( .D(n2759), .CK(clk), .RN(n5152),
.Q(d_ff2_X[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_49_ ( .D(n2767), .CK(clk), .RN(n5135),
.Q(d_ff2_X[49]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n2675), .CK(clk), .RN(n5136), .Q(
d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n2669), .CK(clk), .RN(n5148), .Q(
d_ff2_X[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n2166), .CK(clk), .RN(n5143),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n2174), .CK(clk), .RN(n5113),
.Q(d_ff2_Y[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_33_ ( .D(n2735), .CK(clk), .RN(n5122),
.Q(d_ff2_X[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_33_ ( .D(n2152), .CK(clk), .RN(n5122),
.Q(d_ff2_Y[33]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n2168), .CK(clk), .RN(n5115),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n2176), .CK(clk), .RN(n5117),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n2160), .CK(clk), .RN(n5117),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n2156), .CK(clk), .RN(n5118),
.Q(d_ff2_Y[31]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n2164), .CK(clk), .RN(n5119),
.Q(d_ff2_Y[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n2190), .CK(clk), .RN(n5120),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_36_ ( .D(n2146), .CK(clk), .RN(n5157),
.Q(d_ff2_Y[36]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n2188), .CK(clk), .RN(n5133),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n2172), .CK(clk), .RN(n5122),
.Q(d_ff2_Y[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_34_ ( .D(n2150), .CK(clk), .RN(n5123),
.Q(d_ff2_Y[34]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n2180), .CK(clk), .RN(n5124),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_37_ ( .D(n2144), .CK(clk), .RN(n5125),
.Q(d_ff2_Y[37]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_41_ ( .D(n2136), .CK(clk), .RN(n5126),
.Q(d_ff2_Y[41]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n2194), .CK(clk), .RN(n5129),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_38_ ( .D(n2745), .CK(clk), .RN(n5120),
.Q(d_ff2_X[38]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_38_ ( .D(n2142), .CK(clk), .RN(n5110),
.Q(d_ff2_Y[38]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_40_ ( .D(n2749), .CK(clk), .RN(n5130),
.Q(d_ff2_X[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_40_ ( .D(n2138), .CK(clk), .RN(n5130),
.Q(d_ff2_Y[40]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n2204), .CK(clk), .RN(n5130), .Q(
d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_43_ ( .D(n2132), .CK(clk), .RN(n5130),
.Q(d_ff2_Y[43]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n2192), .CK(clk), .RN(n5132),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n2178), .CK(clk), .RN(n5132),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n2208), .CK(clk), .RN(n5133), .Q(
d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n2206), .CK(clk), .RN(n5133), .Q(
d_ff2_Y[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_44_ ( .D(n2757), .CK(clk), .RN(n5134),
.Q(d_ff2_X[44]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_49_ ( .D(n2120), .CK(clk), .RN(n5135),
.Q(d_ff2_Y[49]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n2212), .CK(clk), .RN(n5137), .Q(
d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n2210), .CK(clk), .RN(n5139), .Q(
d_ff2_Y[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_51_ ( .D(n2771), .CK(clk), .RN(n5140),
.Q(d_ff2_X[51]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_51_ ( .D(n2116), .CK(clk), .RN(n5140),
.Q(d_ff2_Y[51]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n2218), .CK(clk), .RN(n5140), .Q(
d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_63_ ( .D(n2092), .CK(clk), .RN(n5147),
.Q(d_ff2_Y[63]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(
n2652), .CK(clk), .RN(n3015), .Q(add_subt_module_exp_oper_result[10])
);
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n2659), .CK(clk), .RN(n5080), .Q(add_subt_module_exp_oper_result[6]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n2660), .CK(clk), .RN(n5080), .Q(add_subt_module_exp_oper_result[7]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(n2661), .CK(clk), .RN(n5098), .Q(add_subt_module_exp_oper_result[8]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(n2662), .CK(clk), .RN(n5101), .Q(add_subt_module_exp_oper_result[9]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_62_ ( .D(n1942), .CK(clk), .RN(
n5089), .Q(add_subt_module_intDX[62]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_56_ ( .D(n1924), .CK(clk), .RN(
n5089), .Q(add_subt_module_intDX[56]) );
DFFRX1TS reg_LUT_Q_reg_48_ ( .D(n2843), .CK(clk), .RN(n5152), .Q(
d_ff3_LUT_out[48]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_57_ ( .D(n2109), .CK(clk), .RN(n5143),
.Q(d_ff2_Y[57]), .QN(n5008) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n1743), .CK(clk), .RN(n5103), .Q(add_subt_module_DmP[24]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(n1810), .CK(clk), .RN(n5109), .Q(add_subt_module_DmP[39]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n1817),
.CK(clk), .RN(n5109), .Q(add_subt_module_DmP[8]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n1827), .CK(clk), .RN(n5092), .Q(add_subt_module_DmP[12]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(n1835), .CK(clk), .RN(n2961), .Q(add_subt_module_DmP[40]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n1851), .CK(clk), .RN(n5091), .Q(add_subt_module_DmP[20]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n1871), .CK(clk), .RN(n5080), .Q(add_subt_module_DmP[16]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n1882),
.CK(clk), .RN(n5106), .Q(add_subt_module_DmP[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n1902),
.CK(clk), .RN(n5107), .Q(add_subt_module_DmP[4]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(n1905), .CK(clk), .RN(n5107), .Q(add_subt_module_DmP[51]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n1703),
.CK(clk), .RN(n5102), .Q(add_subt_module_DMP[0]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n1718), .CK(clk), .RN(n5092), .Q(add_subt_module_DMP[12]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n1720),
.CK(clk), .RN(n5090), .Q(add_subt_module_DMP[8]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n1724), .CK(clk), .RN(n5097), .Q(add_subt_module_DMP[30]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n1726), .CK(clk), .RN(n5079), .Q(add_subt_module_DMP[14]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n1729), .CK(clk), .RN(n5079), .Q(add_subt_module_DMP[17]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n1730), .CK(clk), .RN(n5106), .Q(add_subt_module_DMP[24]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n1731), .CK(clk), .RN(n3015), .Q(add_subt_module_DMP[22]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n1736), .CK(clk), .RN(n5108), .Q(add_subt_module_DMP[28]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(n1746), .CK(clk), .RN(n5098), .Q(add_subt_module_DMP[32]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(n1806), .CK(clk), .RN(n5102), .Q(add_subt_module_DMP[37]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(n1820), .CK(clk), .RN(n5099), .Q(add_subt_module_DMP[42]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(n1834), .CK(clk), .RN(n5102), .Q(add_subt_module_DMP[40]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(n1898), .CK(clk), .RN(n5104), .Q(add_subt_module_DMP[48]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(
n2555), .CK(clk), .RN(n5097), .Q(
add_subt_module_Sgf_normalized_result[20]), .QN(n4866) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]),
.CK(clk), .RN(n2962), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX1TS reg_shift_y_Q_reg_57_ ( .D(n2098), .CK(clk), .RN(n5153), .Q(
d_ff3_sh_y_out[57]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_17_ ( .D(n1751), .CK(clk), .RN(
n5095), .Q(add_subt_module_intDY[17]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_20_ ( .D(n1852), .CK(clk), .RN(
n5096), .Q(add_subt_module_intDY[20]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_12_ ( .D(n1828), .CK(clk), .RN(
n5092), .Q(add_subt_module_intDY[12]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_46_ ( .D(n1876), .CK(clk), .RN(
n5106), .Q(add_subt_module_intDY[46]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_28_ ( .D(n1738), .CK(clk), .RN(
n5099), .Q(add_subt_module_intDY[28]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_52_ ( .D(n1912), .CK(clk), .RN(
n5107), .Q(add_subt_module_intDX[52]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_39_ ( .D(n1811), .CK(clk), .RN(
n3018), .Q(add_subt_module_intDY[39]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_8_ ( .D(n1818), .CK(clk), .RN(n5092), .Q(add_subt_module_intDY[8]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_42_ ( .D(n1822), .CK(clk), .RN(
n5092), .Q(add_subt_module_intDY[42]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_34_ ( .D(n1800), .CK(clk), .RN(
n5093), .Q(add_subt_module_intDY[34]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_14_ ( .D(n1780), .CK(clk), .RN(
n5079), .Q(add_subt_module_intDY[14]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_40_ ( .D(n1836), .CK(clk), .RN(
n5087), .Q(add_subt_module_intDY[40]) );
DFFRX2TS add_subt_module_YRegister_Q_reg_2_ ( .D(n1896), .CK(clk), .RN(n5090), .Q(add_subt_module_intDY[2]) );
DFFRX2TS add_subt_module_XRegister_Q_reg_0_ ( .D(n1909), .CK(clk), .RN(n5107), .Q(add_subt_module_intDX[0]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(
n2644), .CK(clk), .RN(n5103), .Q(add_subt_module_Add_Subt_result[48])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
n2603), .CK(clk), .RN(n5099), .Q(add_subt_module_Add_Subt_result[7])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(
n2627), .CK(clk), .RN(n3015), .Q(add_subt_module_Add_Subt_result[31])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(
n2640), .CK(clk), .RN(n5097), .Q(add_subt_module_Add_Subt_result[44])
);
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
n2611), .CK(clk), .RN(n5098), .Q(add_subt_module_Add_Subt_result[15])
);
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]),
.CK(clk), .RN(n5086), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]),
.CK(clk), .RN(n5080), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]),
.CK(clk), .RN(n5085), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]),
.CK(clk), .RN(n5105), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]),
.CK(clk), .RN(n2962), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]),
.CK(clk), .RN(n5107), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]),
.CK(clk), .RN(n5088), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]),
.CK(clk), .RN(n5087), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]),
.CK(clk), .RN(n2961), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]),
.CK(clk), .RN(n5087), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]),
.CK(clk), .RN(n5087), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]),
.CK(clk), .RN(n5088), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[54]),
.CK(clk), .RN(n2961), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]),
.CK(clk), .RN(n2962), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(n2105), .CK(clk), .RN(n5146),
.Q(d_ff2_Y[61]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]),
.CK(clk), .RN(n5082), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]),
.CK(clk), .RN(n5083), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(
n2536), .CK(clk), .RN(n2962), .Q(
add_subt_module_Sgf_normalized_result[1]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]),
.CK(clk), .RN(n5088), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]),
.CK(clk), .RN(n3018), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n2655), .CK(clk), .RN(n5107), .Q(add_subt_module_exp_oper_result[2]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n2920), .CK(clk), .RN(n5158), .Q(
d_ff1_operation_out) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]),
.CK(clk), .RN(n5083), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]),
.CK(clk), .RN(n2961), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n2653), .CK(clk), .RN(n5105), .Q(add_subt_module_exp_oper_result[0]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ (
.D(n2534), .CK(clk), .RN(n5081), .Q(result_add_subt[62]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ (
.D(n2530), .CK(clk), .RN(n5081), .Q(result_add_subt[61]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ (
.D(n2526), .CK(clk), .RN(n5081), .Q(result_add_subt[60]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ (
.D(n2522), .CK(clk), .RN(n5081), .Q(result_add_subt[59]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ (
.D(n2518), .CK(clk), .RN(n5081), .Q(result_add_subt[58]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ (
.D(n2514), .CK(clk), .RN(n5081), .Q(result_add_subt[57]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ (
.D(n2510), .CK(clk), .RN(n5081), .Q(result_add_subt[56]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ (
.D(n2506), .CK(clk), .RN(n5081), .Q(result_add_subt[55]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ (
.D(n2502), .CK(clk), .RN(n5081), .Q(result_add_subt[54]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ (
.D(n2498), .CK(clk), .RN(n5081), .Q(result_add_subt[53]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ (
.D(n2478), .CK(clk), .RN(n5095), .Q(result_add_subt[48]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ (
.D(n2486), .CK(clk), .RN(n5082), .Q(result_add_subt[50]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ (
.D(n2474), .CK(clk), .RN(n5083), .Q(result_add_subt[47]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ (
.D(n2470), .CK(clk), .RN(n5083), .Q(result_add_subt[46]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ (
.D(n2350), .CK(clk), .RN(n5088), .Q(result_add_subt[16]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ (
.D(n2462), .CK(clk), .RN(n5088), .Q(result_add_subt[44]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ (
.D(n2466), .CK(clk), .RN(n5088), .Q(result_add_subt[45]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ (
.D(n2366), .CK(clk), .RN(n5088), .Q(result_add_subt[20]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ (
.D(n2338), .CK(clk), .RN(n5080), .Q(result_add_subt[13]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ (
.D(n2458), .CK(clk), .RN(n5084), .Q(result_add_subt[43]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ (
.D(n2446), .CK(clk), .RN(n2961), .Q(result_add_subt[40]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ (
.D(n2334), .CK(clk), .RN(n2961), .Q(result_add_subt[12]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ (
.D(n2330), .CK(clk), .RN(n3021), .Q(result_add_subt[11]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ (
.D(n2454), .CK(clk), .RN(n2962), .Q(result_add_subt[42]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ (
.D(n2450), .CK(clk), .RN(n5085), .Q(result_add_subt[41]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ (
.D(n2442), .CK(clk), .RN(n5107), .Q(result_add_subt[39]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ (
.D(n2434), .CK(clk), .RN(n2962), .Q(result_add_subt[37]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ (
.D(n2362), .CK(clk), .RN(n5089), .Q(result_add_subt[19]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ (
.D(n2422), .CK(clk), .RN(n5086), .Q(result_add_subt[34]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ (
.D(n2378), .CK(clk), .RN(n5105), .Q(result_add_subt[23]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ (
.D(n2406), .CK(clk), .RN(n5089), .Q(result_add_subt[30]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ (
.D(n2346), .CK(clk), .RN(n5086), .Q(result_add_subt[15]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ (
.D(n2430), .CK(clk), .RN(n5105), .Q(result_add_subt[36]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ (
.D(n2342), .CK(clk), .RN(n5087), .Q(result_add_subt[14]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ (
.D(n2394), .CK(clk), .RN(n5087), .Q(result_add_subt[27]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ (
.D(n2410), .CK(clk), .RN(n5087), .Q(result_add_subt[31]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ (
.D(n2402), .CK(clk), .RN(n5087), .Q(result_add_subt[29]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ (
.D(n2370), .CK(clk), .RN(n5087), .Q(result_add_subt[21]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ (
.D(n2358), .CK(clk), .RN(n5087), .Q(result_add_subt[18]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ (
.D(n2354), .CK(clk), .RN(n5088), .Q(result_add_subt[17]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ (
.D(n2414), .CK(clk), .RN(n3018), .Q(result_add_subt[32]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ (
.D(n2382), .CK(clk), .RN(n3021), .Q(result_add_subt[24]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ (
.D(n2374), .CK(clk), .RN(n5085), .Q(result_add_subt[22]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ (
.D(n2398), .CK(clk), .RN(n2962), .Q(result_add_subt[28]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ (
.D(n2390), .CK(clk), .RN(n2962), .Q(result_add_subt[26]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_36_ ( .D(n2248), .CK(clk), .RN(n5133),
.Q(d_ff2_Z[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n2699), .CK(clk), .RN(n5133),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_LUT_Q_reg_24_ ( .D(n2819), .CK(clk), .RN(n5159), .Q(
d_ff3_LUT_out[24]) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n2820), .CK(clk), .RN(n5159), .Q(
d_ff3_LUT_out[25]) );
DFFRX4TS cont_iter_count_reg_3_ ( .D(n2924), .CK(clk), .RN(n5159), .Q(
cont_iter_out[3]), .QN(n4887) );
DFFRX1TS d_ff4_Xn_Q_reg_48_ ( .D(n2475), .CK(clk), .RN(n5137), .Q(
d_ff_Xn[48]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ (
.D(n2591), .CK(clk), .RN(n5104), .Q(add_subt_module_LZA_output[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(n2784), .CK(clk), .RN(n5141),
.Q(d_ff2_X[53]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ (
.D(n2593), .CK(clk), .RN(n5089), .Q(add_subt_module_LZA_output[3]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]),
.CK(clk), .RN(n5107), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX4TS cont_iter_count_reg_1_ ( .D(n2922), .CK(clk), .RN(n5159), .Q(
cont_iter_out[1]), .QN(n4808) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]),
.CK(clk), .RN(n5089), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n2667), .CK(clk), .RN(n5148), .Q(
sel_mux_3_reg) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_63_ ( .D(n2931), .CK(clk), .RN(n5148),
.Q(d_ff2_X[63]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n2220), .CK(clk), .RN(n5147), .Q(
d_ff3_sign_out) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(n1821), .CK(clk), .RN(n5092), .Q(add_subt_module_DmP[42]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(n1855), .CK(clk), .RN(n5099), .Q(add_subt_module_DmP[45]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n1848), .CK(clk), .RN(n5103), .Q(add_subt_module_DmP[13]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n1779), .CK(clk), .RN(n5079), .Q(add_subt_module_DmP[14]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(n1892), .CK(clk), .RN(n5100), .Q(add_subt_module_DmP[50]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(n1889), .CK(clk), .RN(n5090), .Q(add_subt_module_DmP[47]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]),
.CK(clk), .RN(n5080), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(n1916), .CK(clk), .RN(n3015), .Q(add_subt_module_DMP[54]) );
DFFRX2TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n2656), .CK(clk), .RN(n3015), .Q(add_subt_module_exp_oper_result[3]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n1710), .CK(clk), .RN(n5085), .Q(add_subt_module_DMP[16]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n1725), .CK(clk), .RN(n5079), .Q(add_subt_module_DMP[15]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n1713),
.CK(clk), .RN(n5101), .Q(add_subt_module_DMP[5]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n1705),
.CK(clk), .RN(n5106), .Q(add_subt_module_DMP[4]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n1708),
.CK(clk), .RN(n5106), .Q(add_subt_module_DMP[3]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n1706),
.CK(clk), .RN(n5094), .Q(add_subt_module_DMP[2]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n1709),
.CK(clk), .RN(n5097), .Q(add_subt_module_DMP[1]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n1767), .CK(clk), .RN(n5079), .Q(add_subt_module_DMP[29]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n5079), .Q(add_subt_module_DMP[27]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n1732), .CK(clk), .RN(n5085), .Q(add_subt_module_DMP[26]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n1757), .CK(clk), .RN(n5085), .Q(add_subt_module_DMP[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n2277), .CK(clk), .RN(n5139), .Q(
d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_40_ ( .D(n2244), .CK(clk), .RN(n5130),
.Q(d_ff2_Z[40]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n2274), .CK(clk), .RN(n5131),
.Q(d_ff2_Z[10]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_43_ ( .D(n2241), .CK(clk), .RN(n5141),
.Q(d_ff2_Z[43]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n2279), .CK(clk), .RN(n5133), .Q(
d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_45_ ( .D(n2239), .CK(clk), .RN(n5150),
.Q(d_ff2_Z[45]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_44_ ( .D(n2240), .CK(clk), .RN(n5134),
.Q(d_ff2_Z[44]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n2278), .CK(clk), .RN(n5119), .Q(
d_ff2_Z[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n2281), .CK(clk), .RN(n5137), .Q(
d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_49_ ( .D(n2235), .CK(clk), .RN(n5135),
.Q(d_ff2_Z[49]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n2284), .CK(clk), .RN(n5140), .Q(
d_ff2_Z[0]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_51_ ( .D(n2233), .CK(clk), .RN(n5140),
.Q(d_ff2_Z[51]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(
n2626), .CK(clk), .RN(n5102), .Q(add_subt_module_Add_Subt_result[30]),
.QN(n4816) );
DFFRX2TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n2654), .CK(clk), .RN(n5097), .Q(add_subt_module_exp_oper_result[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_59_ ( .D(n2225), .CK(clk), .RN(n5145),
.Q(d_ff2_Z[59]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_57_ ( .D(n2227), .CK(clk), .RN(n5143),
.Q(d_ff2_Z[57]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(n1888), .CK(clk), .RN(n5091), .Q(add_subt_module_DMP[47]) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n2798), .CK(clk), .RN(n5150), .Q(
d_ff3_LUT_out[3]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]),
.CK(clk), .RN(n2961), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]),
.CK(clk), .RN(n5084), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]),
.CK(clk), .RN(n5107), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]),
.CK(clk), .RN(n5088), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRX1TS d_ff5_Q_reg_63_ ( .D(n1963), .CK(clk), .RN(n5147), .Q(
data_output2_63_) );
DFFRX4TS cont_iter_count_reg_2_ ( .D(n2921), .CK(clk), .RN(n5159), .Q(
cont_iter_out[2]), .QN(n4820) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]),
.CK(clk), .RN(n3021), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]),
.CK(clk), .RN(n5089), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]),
.CK(clk), .RN(n5086), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_62_ ( .D(n2104), .CK(clk), .RN(n5147),
.Q(d_ff2_Y[62]) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n2918), .CK(clk), .RN(n5158), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n5002) );
DFFRX1TS d_ff4_Xn_Q_reg_56_ ( .D(n2507), .CK(clk), .RN(n5143), .Q(
d_ff_Xn[56]) );
DFFRX1TS d_ff4_Xn_Q_reg_61_ ( .D(n2527), .CK(clk), .RN(n5146), .Q(
d_ff_Xn[61]) );
DFFRX1TS d_ff4_Xn_Q_reg_35_ ( .D(n2423), .CK(clk), .RN(n5121), .Q(
d_ff_Xn[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_39_ ( .D(n2439), .CK(clk), .RN(n5125), .Q(
d_ff_Xn[39]) );
DFFRX1TS d_ff4_Xn_Q_reg_41_ ( .D(n2447), .CK(clk), .RN(n5126), .Q(
d_ff_Xn[41]) );
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n2315), .CK(clk), .RN(n5127), .Q(d_ff_Xn[8])
);
DFFRX1TS d_ff4_Xn_Q_reg_42_ ( .D(n2451), .CK(clk), .RN(n5128), .Q(
d_ff_Xn[42]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n2327), .CK(clk), .RN(n5128), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n2311), .CK(clk), .RN(n5130), .Q(d_ff_Xn[7])
);
DFFRX1TS d_ff4_Xn_Q_reg_43_ ( .D(n2455), .CK(clk), .RN(n5139), .Q(
d_ff_Xn[43]) );
DFFRX1TS d_ff4_Xn_Q_reg_45_ ( .D(n2463), .CK(clk), .RN(n5153), .Q(
d_ff_Xn[45]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n2307), .CK(clk), .RN(n5133), .Q(d_ff_Xn[6])
);
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n2319), .CK(clk), .RN(n5114), .Q(d_ff_Xn[9])
);
DFFRX1TS d_ff4_Xn_Q_reg_46_ ( .D(n2467), .CK(clk), .RN(n5134), .Q(
d_ff_Xn[46]) );
DFFRX1TS d_ff4_Xn_Q_reg_49_ ( .D(n2479), .CK(clk), .RN(n5135), .Q(
d_ff_Xn[49]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n2295), .CK(clk), .RN(n5136), .Q(d_ff_Xn[3])
);
DFFRX1TS d_ff4_Xn_Q_reg_53_ ( .D(n2495), .CK(clk), .RN(n5142), .Q(
d_ff_Xn[53]) );
DFFRX1TS d_ff4_Xn_Q_reg_54_ ( .D(n2499), .CK(clk), .RN(n5142), .Q(
d_ff_Xn[54]) );
DFFRX1TS d_ff4_Xn_Q_reg_55_ ( .D(n2503), .CK(clk), .RN(n5115), .Q(
d_ff_Xn[55]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n2090), .CK(clk), .RN(n5148), .Q(d_ff_Xn[0])
);
DFFRX1TS d_ff4_Xn_Q_reg_57_ ( .D(n2511), .CK(clk), .RN(n5143), .Q(
d_ff_Xn[57]) );
DFFRX1TS d_ff4_Xn_Q_reg_59_ ( .D(n2519), .CK(clk), .RN(n5145), .Q(
d_ff_Xn[59]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n2371), .CK(clk), .RN(n5113), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n2351), .CK(clk), .RN(n5114), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n2355), .CK(clk), .RN(n5116), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n2367), .CK(clk), .RN(n5116), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n2343), .CK(clk), .RN(n5157), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n2331), .CK(clk), .RN(n5129), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_38_ ( .D(n2435), .CK(clk), .RN(n5110), .Q(
d_ff_Xn[38]) );
DFFRX1TS d_ff4_Xn_Q_reg_40_ ( .D(n2443), .CK(clk), .RN(n5130), .Q(
d_ff_Xn[40]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n2323), .CK(clk), .RN(n5131), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n2363), .CK(clk), .RN(n5132), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n2303), .CK(clk), .RN(n5133), .Q(d_ff_Xn[5])
);
DFFRX1TS d_ff4_Xn_Q_reg_44_ ( .D(n2459), .CK(clk), .RN(n5135), .Q(
d_ff_Xn[44]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n2347), .CK(clk), .RN(n5158), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n2287), .CK(clk), .RN(n5136), .Q(d_ff_Xn[1])
);
DFFRX1TS d_ff4_Xn_Q_reg_47_ ( .D(n2471), .CK(clk), .RN(n5137), .Q(
d_ff_Xn[47]) );
DFFRX1TS d_ff4_Xn_Q_reg_50_ ( .D(n2483), .CK(clk), .RN(n5138), .Q(
d_ff_Xn[50]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n2291), .CK(clk), .RN(n5138), .Q(d_ff_Xn[2])
);
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n2299), .CK(clk), .RN(n5139), .Q(d_ff_Xn[4])
);
DFFRX1TS d_ff4_Xn_Q_reg_51_ ( .D(n2487), .CK(clk), .RN(n5140), .Q(
d_ff_Xn[51]) );
DFFRX1TS d_ff4_Xn_Q_reg_63_ ( .D(n2932), .CK(clk), .RN(n5148), .Q(
d_ff_Xn[63]) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ (
.D(n2594), .CK(clk), .RN(n5095), .Q(add_subt_module_LZA_output[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_35_ ( .D(n2148), .CK(clk), .RN(n5121),
.Q(d_ff2_Y[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_60_ ( .D(n2523), .CK(clk), .RN(n5145), .Q(
d_ff_Xn[60]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n2721), .CK(clk), .RN(n5145),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_28_ ( .D(n2725), .CK(clk), .RN(n5113),
.Q(d_ff2_X[28]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n2717), .CK(clk), .RN(n5127),
.Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_32_ ( .D(n2733), .CK(clk), .RN(n5114),
.Q(d_ff2_X[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n2727), .CK(clk), .RN(n5117),
.Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n2731), .CK(clk), .RN(n5118),
.Q(d_ff2_X[31]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n2697), .CK(clk), .RN(n5120),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_36_ ( .D(n2741), .CK(clk), .RN(n5120),
.Q(d_ff2_X[36]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_48_ ( .D(n2765), .CK(clk), .RN(n5138),
.Q(d_ff2_X[48]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_46_ ( .D(n2761), .CK(clk), .RN(n5134),
.Q(d_ff2_X[46]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n2687), .CK(clk), .RN(n5131), .Q(
d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n2681), .CK(clk), .RN(n5133), .Q(
d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n2695), .CK(clk), .RN(n5131),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_43_ ( .D(n2755), .CK(clk), .RN(n5140),
.Q(d_ff2_X[43]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n2683), .CK(clk), .RN(n5130), .Q(
d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n2691), .CK(clk), .RN(n5128),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_42_ ( .D(n2753), .CK(clk), .RN(n5128),
.Q(d_ff2_X[42]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n2685), .CK(clk), .RN(n5127), .Q(
d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_39_ ( .D(n2747), .CK(clk), .RN(n5125),
.Q(d_ff2_X[39]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n2707), .CK(clk), .RN(n5124),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_34_ ( .D(n2737), .CK(clk), .RN(n5123),
.Q(d_ff2_X[34]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_35_ ( .D(n2739), .CK(clk), .RN(n5121),
.Q(d_ff2_X[35]) );
DFFRX1TS d_ff4_Xn_Q_reg_62_ ( .D(n2531), .CK(clk), .RN(n5147), .Q(
d_ff_Xn[62]) );
DFFRX1TS d_ff4_Xn_Q_reg_52_ ( .D(n2491), .CK(clk), .RN(n5141), .Q(
d_ff_Xn[52]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n2677), .CK(clk), .RN(n5139), .Q(
d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n2673), .CK(clk), .RN(n5118), .Q(
d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_50_ ( .D(n2769), .CK(clk), .RN(n5138),
.Q(d_ff2_X[50]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_47_ ( .D(n2763), .CK(clk), .RN(n5137),
.Q(d_ff2_X[47]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n2671), .CK(clk), .RN(n5136), .Q(
d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n2701), .CK(clk), .RN(n5155),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_44_ ( .D(n2130), .CK(clk), .RN(n5120),
.Q(d_ff2_Y[44]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n2679), .CK(clk), .RN(n5133), .Q(
d_ff2_X[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_45_ ( .D(n2128), .CK(clk), .RN(n5155),
.Q(d_ff2_Y[45]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n2709), .CK(clk), .RN(n5132),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n2198), .CK(clk), .RN(n5131),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n2689), .CK(clk), .RN(n5131),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n2693), .CK(clk), .RN(n5129),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_37_ ( .D(n2743), .CK(clk), .RN(n5125),
.Q(d_ff2_X[37]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n2715), .CK(clk), .RN(n5122),
.Q(d_ff2_X[23]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n2158), .CK(clk), .RN(n5122),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n2729), .CK(clk), .RN(n5122),
.Q(d_ff2_X[30]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n2723), .CK(clk), .RN(n5119),
.Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n2711), .CK(clk), .RN(n5116),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n2705), .CK(clk), .RN(n5116),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n2719), .CK(clk), .RN(n5115),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n2703), .CK(clk), .RN(n5114),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_32_ ( .D(n2154), .CK(clk), .RN(n5114),
.Q(d_ff2_Y[32]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n2713), .CK(clk), .RN(n5113),
.Q(d_ff2_X[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_55_ ( .D(n2229), .CK(clk), .RN(n5129),
.Q(d_ff2_Z[55]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_54_ ( .D(n2230), .CK(clk), .RN(n5142),
.Q(d_ff2_Z[54]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n2264), .CK(clk), .RN(n5132),
.Q(d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n2271), .CK(clk), .RN(n5132),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_38_ ( .D(n2246), .CK(clk), .RN(n5110),
.Q(d_ff2_Z[38]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_41_ ( .D(n2243), .CK(clk), .RN(n5126),
.Q(d_ff2_Z[41]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n2265), .CK(clk), .RN(n5124),
.Q(d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_34_ ( .D(n2250), .CK(clk), .RN(n5123),
.Q(d_ff2_Z[34]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n2261), .CK(clk), .RN(n5123),
.Q(d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n2254), .CK(clk), .RN(n5122),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n2270), .CK(clk), .RN(n5120),
.Q(d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n2253), .CK(clk), .RN(n5118),
.Q(d_ff2_Z[31]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n2255), .CK(clk), .RN(n5118),
.Q(d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n2259), .CK(clk), .RN(n5115),
.Q(d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_33_ ( .D(n2251), .CK(clk), .RN(n5115),
.Q(d_ff2_Z[33]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_32_ ( .D(n2252), .CK(clk), .RN(n5114),
.Q(d_ff2_Z[32]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n2262), .CK(clk), .RN(n5113),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_61_ ( .D(n2223), .CK(clk), .RN(n5146),
.Q(d_ff2_Z[61]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_56_ ( .D(n2228), .CK(clk), .RN(n5143),
.Q(d_ff2_Z[56]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_48_ ( .D(n2236), .CK(clk), .RN(n5139),
.Q(d_ff2_Z[48]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_50_ ( .D(n2234), .CK(clk), .RN(n5138),
.Q(d_ff2_Z[50]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_47_ ( .D(n2237), .CK(clk), .RN(n5138),
.Q(d_ff2_Z[47]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_42_ ( .D(n2242), .CK(clk), .RN(n5128),
.Q(d_ff2_Z[42]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_39_ ( .D(n2245), .CK(clk), .RN(n5126),
.Q(d_ff2_Z[39]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_35_ ( .D(n2249), .CK(clk), .RN(n5121),
.Q(d_ff2_Z[35]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n2256), .CK(clk), .RN(n5113),
.Q(d_ff2_Z[28]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]),
.CK(clk), .RN(n5090), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n1908),
.CK(clk), .RN(n5107), .Q(add_subt_module_DmP[0]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n1895),
.CK(clk), .RN(n5090), .Q(add_subt_module_DmP[2]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n1885),
.CK(clk), .RN(n5109), .Q(add_subt_module_DmP[3]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n1838),
.CK(clk), .RN(n5088), .Q(add_subt_module_DmP[7]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(n1807), .CK(clk), .RN(n2962), .Q(add_subt_module_DmP[37]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(n1754), .CK(clk), .RN(n5082), .Q(add_subt_module_DmP[33]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]),
.CK(clk), .RN(n5090), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]),
.CK(clk), .RN(n5080), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n1733), .CK(clk), .RN(n5081), .Q(add_subt_module_DmP[26]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(n1899), .CK(clk), .RN(n5100), .Q(add_subt_module_DmP[48]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(n1865), .CK(clk), .RN(n5080), .Q(add_subt_module_DmP[44]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n1861),
.CK(clk), .RN(n5084), .Q(add_subt_module_DmP[6]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(n1842), .CK(clk), .RN(n5088), .Q(add_subt_module_DmP[43]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n1824), .CK(clk), .RN(n5092), .Q(add_subt_module_DmP[11]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n1802), .CK(clk), .RN(n5093), .Q(add_subt_module_DmP[19]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n1796), .CK(clk), .RN(n5093), .Q(add_subt_module_DmP[23]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(n1790), .CK(clk), .RN(n5106), .Q(add_subt_module_DmP[35]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(n1783), .CK(clk), .RN(n5106), .Q(add_subt_module_DmP[36]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n1776), .CK(clk), .RN(n5094), .Q(add_subt_module_DmP[27]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n1761), .CK(clk), .RN(n5082), .Q(add_subt_module_DmP[18]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n1758), .CK(clk), .RN(n5095), .Q(add_subt_module_DmP[25]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n1740), .CK(clk), .RN(n5091), .Q(add_subt_module_DmP[22]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n1737), .CK(clk), .RN(n5103), .Q(add_subt_module_DmP[28]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(n1878), .CK(clk), .RN(n5104), .Q(add_subt_module_DMP[49]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(n1864), .CK(clk), .RN(n5099), .Q(add_subt_module_DMP[44]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(n1854), .CK(clk), .RN(n5096), .Q(add_subt_module_DMP[45]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(n1841), .CK(clk), .RN(n5103), .Q(add_subt_module_DMP[43]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(n1830), .CK(clk), .RN(n5102), .Q(add_subt_module_DMP[38]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(n1813), .CK(clk), .RN(n5102), .Q(add_subt_module_DMP[41]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(n1805), .CK(clk), .RN(n5102), .Q(add_subt_module_DMP[39]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(n1789), .CK(clk), .RN(n5101), .Q(add_subt_module_DMP[35]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(n1782), .CK(clk), .RN(n5102), .Q(add_subt_module_DMP[36]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(n1771), .CK(clk), .RN(n5101), .Q(add_subt_module_DMP[31]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(n1753), .CK(clk), .RN(n5097), .Q(add_subt_module_DMP[33]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n1728), .CK(clk), .RN(n5090), .Q(add_subt_module_DMP[18]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n1727), .CK(clk), .RN(n5081), .Q(add_subt_module_DMP[21]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(n1722), .CK(clk), .RN(n5098), .Q(add_subt_module_DMP[34]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n1721), .CK(clk), .RN(n5080), .Q(add_subt_module_DMP[19]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n1719), .CK(clk), .RN(n5100), .Q(add_subt_module_DMP[11]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n1717),
.CK(clk), .RN(n5090), .Q(add_subt_module_DMP[7]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n1716), .CK(clk), .RN(n5090), .Q(add_subt_module_DMP[10]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n1714), .CK(clk), .RN(n3015), .Q(add_subt_module_DMP[20]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n1712),
.CK(clk), .RN(n5100), .Q(add_subt_module_DMP[6]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n1711),
.CK(clk), .RN(n5100), .Q(add_subt_module_DMP[9]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(n1707), .CK(clk), .RN(n5104), .Q(add_subt_module_DMP[50]) );
DFFRX1TS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(n1704), .CK(clk), .RN(n5104), .Q(add_subt_module_DMP[51]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]),
.CK(clk), .RN(n3018), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .QN(
n4997) );
DFFRXLTS add_subt_module_Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n2934),
.CK(clk), .RN(n5084), .Q(underflow_flag), .QN(n4998) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]),
.CK(clk), .RN(n2962), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .QN(
n4996) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]),
.CK(clk), .RN(n5083), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .QN(
n4995) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]),
.CK(clk), .RN(n5095), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .QN(
n4994) );
DFFRXLTS d_ff5_Q_reg_48_ ( .D(n1993), .CK(clk), .RN(n5137), .Q(
sign_inv_out[48]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(
n2549), .CK(clk), .RN(n5092), .Q(
add_subt_module_Sgf_normalized_result[14]), .QN(n4861) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(n1874), .CK(clk), .RN(n5096), .Q(add_subt_module_DMP[46]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n5085), .Q(add_subt_module_DMP[13]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n1723), .CK(clk), .RN(n5089), .Q(add_subt_module_DMP[23]) );
DFFRX4TS add_subt_module_Sel_C_Q_reg_0_ ( .D(n2650), .CK(clk), .RN(n1959),
.Q(add_subt_module_FSM_selector_C), .QN(n2950) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n2923), .CK(clk), .RN(n5159), .Q(
cont_iter_out[0]) );
CMPR32X2TS intadd_375_U4 ( .A(d_ff2_X[53]), .B(n4808), .C(intadd_375_CI),
.CO(intadd_375_n3), .S(intadd_375_SUM_0_) );
CMPR32X2TS intadd_374_U4 ( .A(d_ff2_Y[53]), .B(n4808), .C(intadd_374_CI),
.CO(intadd_374_n3), .S(intadd_374_SUM_0_) );
CMPR32X2TS intadd_375_U3 ( .A(d_ff2_X[54]), .B(n4820), .C(intadd_375_n3),
.CO(intadd_375_n2), .S(intadd_375_SUM_1_) );
CMPR32X2TS intadd_374_U3 ( .A(d_ff2_Y[54]), .B(n4820), .C(intadd_374_n3),
.CO(intadd_374_n2), .S(intadd_374_SUM_1_) );
CMPR32X2TS intadd_374_U2 ( .A(d_ff2_Y[55]), .B(n4887), .C(intadd_374_n2),
.CO(intadd_374_n1), .S(intadd_374_SUM_2_) );
CMPR32X2TS intadd_375_U2 ( .A(d_ff2_X[55]), .B(n4887), .C(intadd_375_n2),
.CO(intadd_375_n1), .S(intadd_375_SUM_2_) );
OR3X4TS U3131 ( .A(cont_var_out[0]), .B(n4435), .C(n4434), .Y(n3000) );
OR2X6TS U3132 ( .A(n4558), .B(n3711), .Y(n3003) );
AOI222X4TS U3133 ( .A0(n4156), .A1(n4155), .B0(n4163), .B1(n4242), .C0(n4168), .C1(n4271), .Y(n4176) );
AOI222X1TS U3134 ( .A0(n4491), .A1(d_ff2_Z[53]), .B0(n3296), .B1(d_ff1_Z[53]), .C0(d_ff_Zn[53]), .C1(n3301), .Y(n3259) );
AOI222X1TS U3135 ( .A0(n3305), .A1(d_ff2_Z[18]), .B0(n3296), .B1(d_ff1_Z[18]), .C0(d_ff_Zn[18]), .C1(n4492), .Y(n3287) );
AOI222X1TS U3136 ( .A0(n4491), .A1(d_ff2_Z[24]), .B0(n3296), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n3301), .Y(n3273) );
AOI222X1TS U3137 ( .A0(n3305), .A1(d_ff2_Z[52]), .B0(n3296), .B1(d_ff1_Z[52]), .C0(d_ff_Zn[52]), .C1(n3301), .Y(n3256) );
AOI222X1TS U3138 ( .A0(n4491), .A1(d_ff2_Z[37]), .B0(n3296), .B1(d_ff1_Z[37]), .C0(d_ff_Zn[37]), .C1(n3301), .Y(n3300) );
AOI222X1TS U3139 ( .A0(n4491), .A1(d_ff2_Z[27]), .B0(n3296), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n3301), .Y(n3263) );
AOI222X1TS U3140 ( .A0(n4491), .A1(d_ff2_Z[26]), .B0(n3296), .B1(d_ff1_Z[26]), .C0(d_ff_Zn[26]), .C1(n3301), .Y(n3261) );
AOI222X1TS U3141 ( .A0(n4491), .A1(d_ff2_Z[62]), .B0(n3296), .B1(d_ff1_Z[62]), .C0(d_ff_Zn[62]), .C1(n4487), .Y(n3265) );
AOI222X1TS U3142 ( .A0(n3305), .A1(d_ff2_Z[58]), .B0(n3258), .B1(d_ff1_Z[58]), .C0(d_ff_Zn[58]), .C1(n4487), .Y(n3231) );
AOI222X1TS U3143 ( .A0(n4491), .A1(d_ff2_Z[16]), .B0(n3296), .B1(d_ff1_Z[16]), .C0(d_ff_Zn[16]), .C1(n4487), .Y(n3277) );
AOI222X1TS U3144 ( .A0(n3308), .A1(d_ff2_Z[59]), .B0(n3258), .B1(d_ff1_Z[59]), .C0(d_ff_Zn[59]), .C1(n3304), .Y(n3251) );
AOI222X1TS U3145 ( .A0(n3305), .A1(d_ff2_Z[15]), .B0(n3296), .B1(d_ff1_Z[15]), .C0(d_ff_Zn[15]), .C1(n3304), .Y(n3276) );
AOI222X1TS U3146 ( .A0(n4404), .A1(d_ff2_Z[21]), .B0(n3296), .B1(d_ff1_Z[21]), .C0(d_ff_Zn[21]), .C1(n3304), .Y(n3294) );
AOI222X1TS U3147 ( .A0(n4404), .A1(d_ff2_Z[4]), .B0(n3258), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n3298), .Y(n3250) );
AOI222X1TS U3148 ( .A0(n3305), .A1(d_ff2_Z[60]), .B0(n3258), .B1(d_ff1_Z[60]), .C0(d_ff_Zn[60]), .C1(n4424), .Y(n3230) );
AOI222X1TS U3149 ( .A0(n4404), .A1(d_ff2_Z[46]), .B0(n3296), .B1(d_ff1_Z[46]), .C0(d_ff_Zn[46]), .C1(n4424), .Y(n3267) );
AOI222X1TS U3150 ( .A0(n3305), .A1(d_ff2_Z[9]), .B0(n3258), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n4424), .Y(n3228) );
AOI211X1TS U3151 ( .A0(n4351), .A1(n4304), .B0(n4427), .C0(n4303), .Y(n4308)
);
NOR2X8TS U3152 ( .A(n4434), .B(n4433), .Y(n4458) );
NAND2X4TS U3153 ( .A(n4427), .B(n4812), .Y(n4337) );
AOI221X4TS U3154 ( .A0(r_mode[1]), .A1(add_subt_module_sign_final_result),
.B0(r_mode[0]), .B1(n5000), .C0(n3743), .Y(n4322) );
OR2X4TS U3155 ( .A(n4310), .B(n4944), .Y(n4305) );
AOI211X2TS U3156 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .A1(
n3141), .B0(n3541), .C0(n3121), .Y(n3616) );
BUFX4TS U3157 ( .A(n3314), .Y(n4115) );
BUFX4TS U3158 ( .A(n3065), .Y(n3325) );
NAND2X4TS U3159 ( .A(n4503), .B(sel_mux_1_reg), .Y(n4502) );
AOI211XLTS U3160 ( .A0(n3858), .A1(n3857), .B0(n3988), .C0(n3856), .Y(n3862)
);
NAND4XLTS U3161 ( .A(n3972), .B(n3831), .C(n4936), .D(n4813), .Y(n4005) );
BUFX6TS U3162 ( .A(n3621), .Y(n3703) );
AND2X6TS U3163 ( .A(n3517), .B(n4558), .Y(n3621) );
AOI21X2TS U3164 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n2964), .Y(n2972) );
AOI21X2TS U3165 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(
n2964), .Y(n2975) );
AOI21X2TS U3166 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(
n2964), .Y(n2979) );
AOI21X2TS U3167 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(
n2964), .Y(n2977) );
AOI21X2TS U3168 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n2964), .Y(n2976) );
INVX6TS U3169 ( .A(n3313), .Y(n4030) );
NAND2X4TS U3170 ( .A(n3618), .B(n3062), .Y(n3057) );
NAND2X4TS U3171 ( .A(n4146), .B(n4141), .Y(n3364) );
INVX6TS U3172 ( .A(n4458), .Y(n2954) );
OR2X4TS U3173 ( .A(n4146), .B(n4141), .Y(n4253) );
BUFX6TS U3174 ( .A(n4422), .Y(n2955) );
NAND2X4TS U3175 ( .A(n4143), .B(n4146), .Y(n3313) );
OR2X4TS U3176 ( .A(n4143), .B(n4146), .Y(n4234) );
BUFX6TS U3177 ( .A(n4477), .Y(n2956) );
CLKINVX3TS U3178 ( .A(n3674), .Y(n3677) );
CLKINVX6TS U3179 ( .A(n4474), .Y(n2957) );
BUFX4TS U3180 ( .A(n3059), .Y(n4149) );
NOR2X4TS U3181 ( .A(n3063), .B(n3089), .Y(n3579) );
BUFX6TS U3182 ( .A(n4525), .Y(n4421) );
INVX6TS U3183 ( .A(n3089), .Y(n3060) );
NOR2X6TS U3184 ( .A(n3103), .B(n3062), .Y(n3053) );
NAND2X4TS U3185 ( .A(n3673), .B(n4320), .Y(n3674) );
NOR2X4TS U3186 ( .A(sel_mux_3_reg), .B(n3147), .Y(n3149) );
BUFX6TS U3187 ( .A(n4305), .Y(n4533) );
INVX4TS U3188 ( .A(n4280), .Y(n3366) );
NAND2BX4TS U3189 ( .AN(n3147), .B(sel_mux_3_reg), .Y(n3152) );
CLKINVX3TS U3190 ( .A(n4026), .Y(n4023) );
CLKAND2X4TS U3191 ( .A(n4313), .B(n4317), .Y(n3517) );
BUFX6TS U3192 ( .A(n3002), .Y(n2960) );
AND3X4TS U3193 ( .A(n4324), .B(n4811), .C(n4818), .Y(n3004) );
BUFX6TS U3194 ( .A(n3020), .Y(n5088) );
BUFX6TS U3195 ( .A(n3020), .Y(n5107) );
BUFX6TS U3196 ( .A(n5085), .Y(n2961) );
CLKINVX2TS U3197 ( .A(n2967), .Y(n2993) );
OR3X6TS U3198 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n4818), .C(
n4811), .Y(n3005) );
NOR2X6TS U3199 ( .A(add_subt_module_FSM_selector_B[1]), .B(
add_subt_module_FSM_selector_B[0]), .Y(n3052) );
CLKINVX6TS U3200 ( .A(n4856), .Y(n4019) );
BUFX6TS U3201 ( .A(n3020), .Y(n2962) );
MX2X1TS U3202 ( .A(add_subt_module_DMP[37]), .B(
add_subt_module_Sgf_normalized_result[39]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[39]) );
MX2X1TS U3203 ( .A(add_subt_module_DMP[32]), .B(
add_subt_module_Sgf_normalized_result[34]), .S0(n3925), .Y(
add_subt_module_S_A_S_Oper_A[34]) );
MX2X1TS U3204 ( .A(add_subt_module_DMP[8]), .B(
add_subt_module_Sgf_normalized_result[10]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[10]) );
MX2X1TS U3205 ( .A(add_subt_module_DMP[28]), .B(
add_subt_module_Sgf_normalized_result[30]), .S0(n3901), .Y(
add_subt_module_S_A_S_Oper_A[30]) );
MX2X1TS U3206 ( .A(add_subt_module_DMP[5]), .B(
add_subt_module_Sgf_normalized_result[7]), .S0(n4020), .Y(
add_subt_module_S_A_S_Oper_A[7]) );
NOR2XLTS U3207 ( .A(n4852), .B(n4020), .Y(n3921) );
MX2X1TS U3208 ( .A(add_subt_module_DMP[46]), .B(
add_subt_module_Sgf_normalized_result[48]), .S0(n4009), .Y(
add_subt_module_S_A_S_Oper_A[48]) );
MX2X1TS U3209 ( .A(add_subt_module_DMP[19]), .B(
add_subt_module_Sgf_normalized_result[21]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[21]) );
NOR2XLTS U3210 ( .A(n4869), .B(n3901), .Y(n3906) );
MX2X1TS U3211 ( .A(add_subt_module_DMP[17]), .B(
add_subt_module_Sgf_normalized_result[19]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[19]) );
NOR2XLTS U3212 ( .A(n4867), .B(n3901), .Y(n3908) );
MX2X1TS U3213 ( .A(add_subt_module_DMP[3]), .B(
add_subt_module_Sgf_normalized_result[5]), .S0(n4020), .Y(
add_subt_module_S_A_S_Oper_A[5]) );
NOR2XLTS U3214 ( .A(n4851), .B(n4020), .Y(n3923) );
MX2X1TS U3215 ( .A(add_subt_module_DMP[36]), .B(
add_subt_module_Sgf_normalized_result[38]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[38]) );
MX2X1TS U3216 ( .A(add_subt_module_DMP[50]), .B(
add_subt_module_Sgf_normalized_result[52]), .S0(n4009), .Y(
add_subt_module_S_A_S_Oper_A[52]) );
MX2X1TS U3217 ( .A(add_subt_module_DMP[43]), .B(
add_subt_module_Sgf_normalized_result[45]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[45]) );
MX2X1TS U3218 ( .A(add_subt_module_DMP[40]), .B(
add_subt_module_Sgf_normalized_result[42]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[42]) );
MX2X1TS U3219 ( .A(add_subt_module_DMP[12]), .B(
add_subt_module_Sgf_normalized_result[14]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[14]) );
NOR2XLTS U3220 ( .A(n4861), .B(n3925), .Y(n3914) );
MX2X1TS U3221 ( .A(add_subt_module_DMP[15]), .B(
add_subt_module_Sgf_normalized_result[17]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[17]) );
NOR2XLTS U3222 ( .A(n4865), .B(n4020), .Y(n3910) );
MX2X1TS U3223 ( .A(add_subt_module_DMP[1]), .B(
add_subt_module_Sgf_normalized_result[3]), .S0(n4020), .Y(
add_subt_module_S_A_S_Oper_A[3]) );
NOR2XLTS U3224 ( .A(n4849), .B(n4020), .Y(n3926) );
MX2X1TS U3225 ( .A(add_subt_module_DMP[9]), .B(
add_subt_module_Sgf_normalized_result[11]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[11]) );
NOR2XLTS U3226 ( .A(n4857), .B(n4020), .Y(n3917) );
MX2X1TS U3227 ( .A(add_subt_module_DMP[31]), .B(
add_subt_module_Sgf_normalized_result[33]), .S0(n3901), .Y(
add_subt_module_S_A_S_Oper_A[33]) );
MX2X1TS U3228 ( .A(add_subt_module_DMP[23]), .B(
add_subt_module_Sgf_normalized_result[25]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[25]) );
MX2X1TS U3229 ( .A(add_subt_module_DMP[42]), .B(
add_subt_module_Sgf_normalized_result[44]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[44]) );
MX2X1TS U3230 ( .A(add_subt_module_DMP[29]), .B(
add_subt_module_Sgf_normalized_result[31]), .S0(n3901), .Y(
add_subt_module_S_A_S_Oper_A[31]) );
MX2X1TS U3231 ( .A(add_subt_module_DMP[21]), .B(
add_subt_module_Sgf_normalized_result[23]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[23]) );
NOR2XLTS U3232 ( .A(n4871), .B(n3901), .Y(n3904) );
MX2X1TS U3233 ( .A(add_subt_module_DMP[6]), .B(
add_subt_module_Sgf_normalized_result[8]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[8]) );
NOR2XLTS U3234 ( .A(n4855), .B(n4020), .Y(n3920) );
MX2X1TS U3235 ( .A(add_subt_module_DMP[48]), .B(
add_subt_module_Sgf_normalized_result[50]), .S0(n4009), .Y(
add_subt_module_S_A_S_Oper_A[50]) );
MX2X1TS U3236 ( .A(add_subt_module_DMP[35]), .B(
add_subt_module_Sgf_normalized_result[37]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[37]) );
MX2X1TS U3237 ( .A(add_subt_module_DMP[10]), .B(
add_subt_module_Sgf_normalized_result[12]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[12]) );
NOR2XLTS U3238 ( .A(n4860), .B(n4020), .Y(n3916) );
MX2X1TS U3239 ( .A(add_subt_module_DMP[45]), .B(
add_subt_module_Sgf_normalized_result[47]), .S0(n4009), .Y(
add_subt_module_S_A_S_Oper_A[47]) );
MX2X1TS U3240 ( .A(add_subt_module_DMP[26]), .B(
add_subt_module_Sgf_normalized_result[28]), .S0(n3901), .Y(
add_subt_module_S_A_S_Oper_A[28]) );
MX2X1TS U3241 ( .A(add_subt_module_DMP[39]), .B(
add_subt_module_Sgf_normalized_result[41]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[41]) );
MX2X1TS U3242 ( .A(add_subt_module_DMP[2]), .B(
add_subt_module_Sgf_normalized_result[4]), .S0(n4020), .Y(
add_subt_module_S_A_S_Oper_A[4]) );
NOR2XLTS U3243 ( .A(n4848), .B(n4020), .Y(n3924) );
CLKAND2X2TS U3244 ( .A(add_subt_module_Sgf_normalized_result[1]), .B(n4020),
.Y(add_subt_module_S_A_S_Oper_A[1]) );
MX2X1TS U3245 ( .A(add_subt_module_DMP[33]), .B(
add_subt_module_Sgf_normalized_result[35]), .S0(n3901), .Y(
add_subt_module_S_A_S_Oper_A[35]) );
MX2X1TS U3246 ( .A(add_subt_module_DMP[24]), .B(
add_subt_module_Sgf_normalized_result[26]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[26]) );
MX2X1TS U3247 ( .A(add_subt_module_DMP[18]), .B(
add_subt_module_Sgf_normalized_result[20]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[20]) );
NOR2XLTS U3248 ( .A(n4866), .B(n3925), .Y(n3907) );
MX2X1TS U3249 ( .A(add_subt_module_DMP[14]), .B(
add_subt_module_Sgf_normalized_result[16]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[16]) );
MX2X1TS U3250 ( .A(add_subt_module_DMP[51]), .B(
add_subt_module_Sgf_normalized_result[53]), .S0(n4009), .Y(
add_subt_module_S_A_S_Oper_A[53]) );
NAND2BXLTS U3251 ( .AN(add_subt_module_intDY[2]), .B(
add_subt_module_intDX[2]), .Y(n3398) );
NAND2BXLTS U3252 ( .AN(add_subt_module_intDY[19]), .B(
add_subt_module_intDX[19]), .Y(n3429) );
NAND2BXLTS U3253 ( .AN(add_subt_module_intDY[27]), .B(
add_subt_module_intDX[27]), .Y(n3384) );
NAND2BXLTS U3254 ( .AN(add_subt_module_intDY[9]), .B(
add_subt_module_intDX[9]), .Y(n3409) );
NAND2BXLTS U3255 ( .AN(add_subt_module_intDY[21]), .B(
add_subt_module_intDX[21]), .Y(n3392) );
NAND2BXLTS U3256 ( .AN(add_subt_module_intDY[47]), .B(
add_subt_module_intDX[47]), .Y(n3460) );
NAND2BXLTS U3257 ( .AN(add_subt_module_intDY[29]), .B(
add_subt_module_intDX[29]), .Y(n3382) );
NAND2BXLTS U3258 ( .AN(n2994), .B(n3850), .Y(n3823) );
NOR2XLTS U3259 ( .A(add_subt_module_Add_Subt_result[41]), .B(n4441), .Y(
n3822) );
CLKAND2X2TS U3260 ( .A(n3854), .B(n4810), .Y(n3952) );
NAND2BXLTS U3261 ( .AN(add_subt_module_intDY[40]), .B(
add_subt_module_intDX[40]), .Y(n3377) );
NAND2BXLTS U3262 ( .AN(add_subt_module_intDY[41]), .B(
add_subt_module_intDX[41]), .Y(n3378) );
NAND2BXLTS U3263 ( .AN(n2997), .B(add_subt_module_intDX[32]), .Y(n3379) );
NAND2BXLTS U3264 ( .AN(add_subt_module_intDX[62]), .B(
add_subt_module_intDY[62]), .Y(n3455) );
AOI222X4TS U3265 ( .A0(n4151), .A1(n4146), .B0(n4139), .B1(n4284), .C0(n4144), .C1(n4288), .Y(n4161) );
MX2X1TS U3266 ( .A(add_subt_module_DMP[13]), .B(
add_subt_module_Sgf_normalized_result[15]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[15]) );
NOR2XLTS U3267 ( .A(n4863), .B(n4020), .Y(n3912) );
MX2X1TS U3268 ( .A(add_subt_module_DMP[22]), .B(
add_subt_module_Sgf_normalized_result[24]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[24]) );
NOR2XLTS U3269 ( .A(n4873), .B(n3925), .Y(n3903) );
MX2X1TS U3270 ( .A(add_subt_module_DMP[27]), .B(
add_subt_module_Sgf_normalized_result[29]), .S0(n3901), .Y(
add_subt_module_S_A_S_Oper_A[29]) );
MX2X1TS U3271 ( .A(add_subt_module_DMP[41]), .B(
add_subt_module_Sgf_normalized_result[43]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[43]) );
MX2X1TS U3272 ( .A(add_subt_module_DMP[49]), .B(
add_subt_module_Sgf_normalized_result[51]), .S0(n4009), .Y(
add_subt_module_S_A_S_Oper_A[51]) );
AO22XLTS U3273 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(
n3053), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(
n3121) );
AO22XLTS U3274 ( .A0(n3141), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(
n3053), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(
n3117) );
AO22XLTS U3275 ( .A0(n3141), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n3053), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(
n3108) );
AOI211X2TS U3276 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(
n3541), .C0(n3104), .Y(n3578) );
AO22XLTS U3277 ( .A0(n3141), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(
n3053), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(
n3104) );
MX2X1TS U3278 ( .A(add_subt_module_DMP[11]), .B(
add_subt_module_Sgf_normalized_result[13]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[13]) );
NOR2XLTS U3279 ( .A(n4859), .B(n4020), .Y(n3915) );
AO21XLTS U3280 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(
n2964), .Y(n2973) );
INVX4TS U3281 ( .A(n4017), .Y(n3608) );
MX2X1TS U3282 ( .A(add_subt_module_DMP[7]), .B(
add_subt_module_Sgf_normalized_result[9]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[9]) );
NOR2XLTS U3283 ( .A(n4854), .B(n4020), .Y(n3919) );
AO21XLTS U3284 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(
n2964), .Y(n2974) );
MX2X1TS U3285 ( .A(add_subt_module_DMP[44]), .B(
add_subt_module_Sgf_normalized_result[46]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[46]) );
MX2X1TS U3286 ( .A(add_subt_module_DMP[47]), .B(
add_subt_module_Sgf_normalized_result[49]), .S0(n4009), .Y(
add_subt_module_S_A_S_Oper_A[49]) );
MX2X1TS U3287 ( .A(add_subt_module_DMP[30]), .B(
add_subt_module_Sgf_normalized_result[32]), .S0(n3925), .Y(
add_subt_module_S_A_S_Oper_A[32]) );
MX2X1TS U3288 ( .A(add_subt_module_DMP[4]), .B(
add_subt_module_Sgf_normalized_result[6]), .S0(n4020), .Y(
add_subt_module_S_A_S_Oper_A[6]) );
NOR2XLTS U3289 ( .A(n4853), .B(n4020), .Y(n3922) );
MX2X1TS U3290 ( .A(add_subt_module_DMP[38]), .B(
add_subt_module_Sgf_normalized_result[40]), .S0(n4008), .Y(
add_subt_module_S_A_S_Oper_A[40]) );
MX2X1TS U3291 ( .A(add_subt_module_DMP[0]), .B(
add_subt_module_Sgf_normalized_result[2]), .S0(n4020), .Y(
add_subt_module_S_A_S_Oper_A[2]) );
MX2X1TS U3292 ( .A(add_subt_module_DMP[34]), .B(
add_subt_module_Sgf_normalized_result[36]), .S0(n3901), .Y(
add_subt_module_S_A_S_Oper_A[36]) );
MX2X1TS U3293 ( .A(add_subt_module_DMP[16]), .B(
add_subt_module_Sgf_normalized_result[18]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[18]) );
NOR2XLTS U3294 ( .A(n4864), .B(n3925), .Y(n3909) );
CLKAND2X2TS U3295 ( .A(add_subt_module_Sgf_normalized_result[0]), .B(n3901),
.Y(add_subt_module_S_A_S_Oper_A[0]) );
CLKINVX3TS U3296 ( .A(n3621), .Y(n4560) );
AO21XLTS U3297 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(
n2964), .Y(n2978) );
OAI211XLTS U3298 ( .A0(n3949), .A1(n3948), .B0(n3947), .C0(n3979), .Y(n3950)
);
AOI32X1TS U3299 ( .A0(add_subt_module_Add_Subt_result[31]), .A1(n2987), .A2(
n4974), .B0(add_subt_module_Add_Subt_result[33]), .B1(n2987), .Y(n3959) );
MX2X1TS U3300 ( .A(add_subt_module_DMP[20]), .B(
add_subt_module_Sgf_normalized_result[22]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[22]) );
MX2X1TS U3301 ( .A(add_subt_module_DMP[25]), .B(
add_subt_module_Sgf_normalized_result[27]), .S0(n4019), .Y(
add_subt_module_S_A_S_Oper_A[27]) );
NAND2X1TS U3302 ( .A(n4359), .B(n4887), .Y(n4355) );
CLKINVX3TS U3303 ( .A(n4421), .Y(n4493) );
AO22XLTS U3304 ( .A0(n4459), .A1(result_add_subt[63]), .B0(n4481), .B1(
d_ff_Xn[63]), .Y(n2932) );
AO22XLTS U3305 ( .A0(n4463), .A1(result_add_subt[59]), .B0(n4481), .B1(
d_ff_Xn[59]), .Y(n2519) );
AO22XLTS U3306 ( .A0(n4463), .A1(result_add_subt[57]), .B0(n4481), .B1(
d_ff_Xn[57]), .Y(n2511) );
AO22XLTS U3307 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[1]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[1]), .Y(n2654)
);
AO22XLTS U3308 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[3]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[3]), .Y(n2656)
);
AO22XLTS U3309 ( .A0(n4007), .A1(n4455), .B0(n4006), .B1(
add_subt_module_LZA_output[3]), .Y(n2593) );
OAI211XLTS U3310 ( .A0(n4005), .A1(n4004), .B0(n4003), .C0(n4002), .Y(n4007)
);
AOI31XLTS U3311 ( .A0(n3862), .A1(n3861), .A2(n4455), .B0(n3860), .Y(n2591)
);
AO22XLTS U3312 ( .A0(n4346), .A1(operation), .B0(n4341), .B1(
d_ff1_operation_out), .Y(n2920) );
AO22XLTS U3313 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[2]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[2]), .Y(n2655)
);
AO22XLTS U3314 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[15]), .A1(
n4025), .B0(n3005), .B1(add_subt_module_Add_Subt_result[15]), .Y(n2611) );
AO22XLTS U3315 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[44]), .A1(
n4023), .B0(n4027), .B1(add_subt_module_Add_Subt_result[44]), .Y(n2640) );
AO22XLTS U3316 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[31]), .A1(
n4025), .B0(n3005), .B1(add_subt_module_Add_Subt_result[31]), .Y(n2627) );
AO22XLTS U3317 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[7]), .A1(
n4023), .B0(n4027), .B1(add_subt_module_Add_Subt_result[7]), .Y(n2603)
);
AO22XLTS U3318 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[48]), .A1(
n4023), .B0(n4027), .B1(add_subt_module_Add_Subt_result[48]), .Y(n2644) );
NAND2BXLTS U3319 ( .AN(d_ff3_LUT_out[48]), .B(n4507), .Y(n2843) );
AO22XLTS U3320 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[9]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[9]), .Y(n2662)
);
AO22XLTS U3321 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[8]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[8]), .Y(n2661)
);
AO22XLTS U3322 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[7]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[7]), .Y(n2660)
);
AO22XLTS U3323 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[6]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[6]), .Y(n2659)
);
AO22XLTS U3324 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[10]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[10]), .Y(n2652) );
AO22XLTS U3325 ( .A0(d_ff_Yn[4]), .A1(n4487), .B0(d_ff2_Y[4]), .B1(n4500),
.Y(n2210) );
AO22XLTS U3326 ( .A0(d_ff_Yn[3]), .A1(n4487), .B0(d_ff2_Y[3]), .B1(n4500),
.Y(n2212) );
AO22XLTS U3327 ( .A0(d_ff_Yn[5]), .A1(n4487), .B0(d_ff2_Y[5]), .B1(n4527),
.Y(n2208) );
AO22XLTS U3328 ( .A0(d_ff_Yn[2]), .A1(n4487), .B0(d_ff2_Y[2]), .B1(n4527),
.Y(n2214) );
AO22XLTS U3329 ( .A0(d_ff_Yn[1]), .A1(n4487), .B0(d_ff2_Y[1]), .B1(n4500),
.Y(n2216) );
AO22XLTS U3330 ( .A0(n4463), .A1(result_add_subt[25]), .B0(n2956), .B1(
d_ff_Xn[25]), .Y(n2383) );
AO22XLTS U3331 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[5]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[5]), .Y(n2658)
);
AO22XLTS U3332 ( .A0(n4343), .A1(shift_region_flag[0]), .B0(n4340), .B1(
d_ff1_shift_region_flag_out[0]), .Y(n2919) );
AO22XLTS U3333 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[4]), .A1(
n3674), .B0(n3677), .B1(add_subt_module_exp_oper_result[4]), .Y(n2657)
);
AO22XLTS U3334 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[21]), .A1(
n4025), .B0(n4028), .B1(add_subt_module_Add_Subt_result[21]), .Y(n2617) );
AO22XLTS U3335 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[39]), .A1(
n4024), .B0(n3005), .B1(add_subt_module_Add_Subt_result[39]), .Y(n2635) );
AO22XLTS U3336 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[19]), .A1(
n4025), .B0(n4028), .B1(add_subt_module_Add_Subt_result[19]), .Y(n2615) );
AO22XLTS U3337 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[5]), .A1(
n4024), .B0(n3005), .B1(add_subt_module_Add_Subt_result[5]), .Y(n2601)
);
AO22XLTS U3338 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[24]), .A1(
n4029), .B0(n4026), .B1(add_subt_module_Add_Subt_result[24]), .Y(n2620) );
AO22XLTS U3339 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[34]), .A1(
n4025), .B0(n4028), .B1(add_subt_module_Add_Subt_result[34]), .Y(n2630) );
AO22XLTS U3340 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[38]), .A1(
n4025), .B0(n3005), .B1(add_subt_module_Add_Subt_result[38]), .Y(n2634) );
AO22XLTS U3341 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[23]), .A1(
n4029), .B0(n4026), .B1(add_subt_module_Add_Subt_result[23]), .Y(n2619) );
AO22XLTS U3342 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[8]), .A1(
n4023), .B0(n4028), .B1(add_subt_module_Add_Subt_result[8]), .Y(n2604)
);
AO22XLTS U3343 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[29]), .A1(
n4029), .B0(n3005), .B1(add_subt_module_Add_Subt_result[29]), .Y(n2625) );
AO22XLTS U3344 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[52]), .A1(
n4024), .B0(n4026), .B1(add_subt_module_Add_Subt_result[52]), .Y(n2648) );
AO22XLTS U3345 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[45]), .A1(
n4023), .B0(n4027), .B1(add_subt_module_Add_Subt_result[45]), .Y(n2641) );
AO22XLTS U3346 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[50]), .A1(
n4024), .B0(n4026), .B1(add_subt_module_Add_Subt_result[50]), .Y(n2646) );
AO22XLTS U3347 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[42]), .A1(
n4024), .B0(n4028), .B1(add_subt_module_Add_Subt_result[42]), .Y(n2638) );
AO22XLTS U3348 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[43]), .A1(
n4023), .B0(n3005), .B1(add_subt_module_Add_Subt_result[43]), .Y(n2639) );
AO22XLTS U3349 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[51]), .A1(
n4024), .B0(n4026), .B1(add_subt_module_Add_Subt_result[51]), .Y(n2647) );
AO22XLTS U3350 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[37]), .A1(
n4025), .B0(n4027), .B1(add_subt_module_Add_Subt_result[37]), .Y(n2633) );
AO22XLTS U3351 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[54]), .A1(
n4024), .B0(n4026), .B1(add_subt_module_Add_Subt_result[54]), .Y(n2595) );
OAI32X1TS U3352 ( .A0(n4470), .A1(overflow_flag), .A2(n3030), .B0(n4462),
.B1(n4845), .Y(n2933) );
AO22XLTS U3353 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[47]), .A1(
n4023), .B0(n4027), .B1(add_subt_module_Add_Subt_result[47]), .Y(n2643) );
AO22XLTS U3354 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[41]), .A1(
n4024), .B0(n4027), .B1(add_subt_module_Add_Subt_result[41]), .Y(n2637) );
AO22XLTS U3355 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[46]), .A1(
n4023), .B0(n4028), .B1(add_subt_module_Add_Subt_result[46]), .Y(n2642) );
AO22XLTS U3356 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[49]), .A1(
n4023), .B0(n3005), .B1(add_subt_module_Add_Subt_result[49]), .Y(n2645) );
AO22XLTS U3357 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[40]), .A1(
n4024), .B0(n3005), .B1(add_subt_module_Add_Subt_result[40]), .Y(n2636) );
AO22XLTS U3358 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[35]), .A1(
n4025), .B0(n4028), .B1(add_subt_module_Add_Subt_result[35]), .Y(n2631) );
AO22XLTS U3359 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[36]), .A1(
n4025), .B0(n4027), .B1(add_subt_module_Add_Subt_result[36]), .Y(n2632) );
AO22XLTS U3360 ( .A0(n4022), .A1(n4024), .B0(
add_subt_module_add_overflow_flag), .B1(n3005), .Y(n2936) );
AO22XLTS U3361 ( .A0(n3004), .A1(n3022), .B0(n4714), .B1(
add_subt_module_intAS), .Y(n1944) );
AO22XLTS U3362 ( .A0(n4468), .A1(d_ff_Yn[26]), .B0(n4485), .B1(
result_add_subt[26]), .Y(n2388) );
AO22XLTS U3363 ( .A0(n4486), .A1(d_ff_Yn[28]), .B0(n4485), .B1(
result_add_subt[28]), .Y(n2396) );
AO22XLTS U3364 ( .A0(n4468), .A1(d_ff_Yn[22]), .B0(n4458), .B1(
result_add_subt[22]), .Y(n2372) );
AO22XLTS U3365 ( .A0(n4468), .A1(d_ff_Yn[24]), .B0(n4476), .B1(
result_add_subt[24]), .Y(n2380) );
AO22XLTS U3366 ( .A0(n4486), .A1(d_ff_Yn[32]), .B0(n4485), .B1(
result_add_subt[32]), .Y(n2412) );
AO22XLTS U3367 ( .A0(n4468), .A1(d_ff_Yn[17]), .B0(n4476), .B1(
result_add_subt[17]), .Y(n2352) );
AO22XLTS U3368 ( .A0(n4486), .A1(d_ff_Yn[33]), .B0(n4485), .B1(
result_add_subt[33]), .Y(n2416) );
AO22XLTS U3369 ( .A0(n2954), .A1(d_ff_Yn[18]), .B0(n4458), .B1(
result_add_subt[18]), .Y(n2356) );
AO22XLTS U3370 ( .A0(n2954), .A1(d_ff_Yn[21]), .B0(n4458), .B1(
result_add_subt[21]), .Y(n2368) );
AO22XLTS U3371 ( .A0(n4486), .A1(d_ff_Yn[29]), .B0(n4485), .B1(
result_add_subt[29]), .Y(n2400) );
AO22XLTS U3372 ( .A0(n4486), .A1(d_ff_Yn[31]), .B0(n4485), .B1(
result_add_subt[31]), .Y(n2408) );
AO22XLTS U3373 ( .A0(n4486), .A1(d_ff_Yn[27]), .B0(n4485), .B1(
result_add_subt[27]), .Y(n2392) );
AO22XLTS U3374 ( .A0(n2954), .A1(d_ff_Yn[14]), .B0(n4485), .B1(
result_add_subt[14]), .Y(n2340) );
AO22XLTS U3375 ( .A0(n4486), .A1(d_ff_Yn[36]), .B0(n4458), .B1(
result_add_subt[36]), .Y(n2428) );
AO22XLTS U3376 ( .A0(n4486), .A1(d_ff_Yn[15]), .B0(n4458), .B1(
result_add_subt[15]), .Y(n2344) );
AO22XLTS U3377 ( .A0(n4486), .A1(d_ff_Yn[35]), .B0(n4485), .B1(
result_add_subt[35]), .Y(n2424) );
AO22XLTS U3378 ( .A0(n4486), .A1(d_ff_Yn[30]), .B0(n4485), .B1(
result_add_subt[30]), .Y(n2404) );
AO22XLTS U3379 ( .A0(n4468), .A1(d_ff_Yn[23]), .B0(n4458), .B1(
result_add_subt[23]), .Y(n2376) );
AO22XLTS U3380 ( .A0(n4486), .A1(d_ff_Yn[34]), .B0(n4485), .B1(
result_add_subt[34]), .Y(n2420) );
AO22XLTS U3381 ( .A0(n4468), .A1(d_ff_Yn[19]), .B0(n4476), .B1(
result_add_subt[19]), .Y(n2360) );
AO22XLTS U3382 ( .A0(n4486), .A1(d_ff_Yn[37]), .B0(n4458), .B1(
result_add_subt[37]), .Y(n2432) );
AO22XLTS U3383 ( .A0(n4486), .A1(d_ff_Yn[39]), .B0(n4485), .B1(
result_add_subt[39]), .Y(n2440) );
AO22XLTS U3384 ( .A0(n4468), .A1(d_ff_Yn[41]), .B0(n4485), .B1(
result_add_subt[41]), .Y(n2448) );
AO22XLTS U3385 ( .A0(n2954), .A1(d_ff_Yn[8]), .B0(n4476), .B1(
result_add_subt[8]), .Y(n2316) );
AO22XLTS U3386 ( .A0(n4468), .A1(d_ff_Yn[42]), .B0(n4485), .B1(
result_add_subt[42]), .Y(n2452) );
AO22XLTS U3387 ( .A0(n2954), .A1(d_ff_Yn[11]), .B0(n4476), .B1(
result_add_subt[11]), .Y(n2328) );
AO22XLTS U3388 ( .A0(n4486), .A1(d_ff_Yn[12]), .B0(n4476), .B1(
result_add_subt[12]), .Y(n2332) );
AO22XLTS U3389 ( .A0(n4486), .A1(d_ff_Yn[38]), .B0(n4458), .B1(
result_add_subt[38]), .Y(n2436) );
AO22XLTS U3390 ( .A0(n4468), .A1(d_ff_Yn[40]), .B0(n4485), .B1(
result_add_subt[40]), .Y(n2444) );
AO22XLTS U3391 ( .A0(n2954), .A1(d_ff_Yn[7]), .B0(n4476), .B1(
result_add_subt[7]), .Y(n2312) );
AO22XLTS U3392 ( .A0(n4468), .A1(d_ff_Yn[43]), .B0(n4485), .B1(
result_add_subt[43]), .Y(n2456) );
AO22XLTS U3393 ( .A0(n2954), .A1(d_ff_Yn[10]), .B0(n4476), .B1(
result_add_subt[10]), .Y(n2324) );
AO22XLTS U3394 ( .A0(n4468), .A1(d_ff_Yn[13]), .B0(n4476), .B1(
result_add_subt[13]), .Y(n2336) );
AO22XLTS U3395 ( .A0(n4468), .A1(d_ff_Yn[20]), .B0(n4464), .B1(
result_add_subt[20]), .Y(n2364) );
AO22XLTS U3396 ( .A0(n4468), .A1(d_ff_Yn[45]), .B0(n4485), .B1(
result_add_subt[45]), .Y(n2464) );
AO22XLTS U3397 ( .A0(n2954), .A1(d_ff_Yn[5]), .B0(n4476), .B1(
result_add_subt[5]), .Y(n2304) );
AO22XLTS U3398 ( .A0(n2954), .A1(d_ff_Yn[6]), .B0(n4476), .B1(
result_add_subt[6]), .Y(n2308) );
AO22XLTS U3399 ( .A0(n4468), .A1(d_ff_Yn[44]), .B0(n4485), .B1(
result_add_subt[44]), .Y(n2460) );
AO22XLTS U3400 ( .A0(n2954), .A1(d_ff_Yn[9]), .B0(n4476), .B1(
result_add_subt[9]), .Y(n2320) );
AO22XLTS U3401 ( .A0(n4468), .A1(d_ff_Yn[16]), .B0(n4458), .B1(
result_add_subt[16]), .Y(n2348) );
AO22XLTS U3402 ( .A0(n2954), .A1(d_ff_Yn[46]), .B0(n4485), .B1(
result_add_subt[46]), .Y(n2468) );
AO22XLTS U3403 ( .A0(n2954), .A1(d_ff_Yn[49]), .B0(n4464), .B1(
result_add_subt[49]), .Y(n2480) );
AO22XLTS U3404 ( .A0(n2954), .A1(d_ff_Yn[1]), .B0(n4458), .B1(
result_add_subt[1]), .Y(n2288) );
AO22XLTS U3405 ( .A0(n2954), .A1(d_ff_Yn[3]), .B0(n4476), .B1(
result_add_subt[3]), .Y(n2296) );
AO22XLTS U3406 ( .A0(n2954), .A1(d_ff_Yn[47]), .B0(n4464), .B1(
result_add_subt[47]), .Y(n2472) );
AO22XLTS U3407 ( .A0(n2954), .A1(d_ff_Yn[50]), .B0(n4464), .B1(
result_add_subt[50]), .Y(n2484) );
AO22XLTS U3408 ( .A0(n2954), .A1(d_ff_Yn[2]), .B0(n4464), .B1(
result_add_subt[2]), .Y(n2292) );
AO22XLTS U3409 ( .A0(n2954), .A1(d_ff_Yn[48]), .B0(n4464), .B1(
result_add_subt[48]), .Y(n2476) );
AO22XLTS U3410 ( .A0(n2954), .A1(d_ff_Yn[4]), .B0(n4476), .B1(
result_add_subt[4]), .Y(n2300) );
AO22XLTS U3411 ( .A0(n2954), .A1(d_ff_Yn[51]), .B0(n4464), .B1(
result_add_subt[51]), .Y(n2488) );
AO22XLTS U3412 ( .A0(n4486), .A1(d_ff_Yn[0]), .B0(n4485), .B1(
result_add_subt[0]), .Y(n2219) );
AO22XLTS U3413 ( .A0(n2954), .A1(d_ff_Yn[52]), .B0(n4464), .B1(
result_add_subt[52]), .Y(n2492) );
AO22XLTS U3414 ( .A0(n2954), .A1(d_ff_Yn[53]), .B0(n4464), .B1(
result_add_subt[53]), .Y(n2496) );
AO22XLTS U3415 ( .A0(n4468), .A1(d_ff_Yn[54]), .B0(n4464), .B1(
result_add_subt[54]), .Y(n2500) );
AO22XLTS U3416 ( .A0(n4468), .A1(d_ff_Yn[55]), .B0(n4464), .B1(
result_add_subt[55]), .Y(n2504) );
AO22XLTS U3417 ( .A0(n4468), .A1(d_ff_Yn[56]), .B0(n4464), .B1(
result_add_subt[56]), .Y(n2508) );
AO22XLTS U3418 ( .A0(n4468), .A1(d_ff_Yn[57]), .B0(n4464), .B1(
result_add_subt[57]), .Y(n2512) );
AO22XLTS U3419 ( .A0(n4468), .A1(d_ff_Yn[58]), .B0(n4458), .B1(
result_add_subt[58]), .Y(n2516) );
AO22XLTS U3420 ( .A0(n4468), .A1(d_ff_Yn[59]), .B0(n4458), .B1(
result_add_subt[59]), .Y(n2520) );
AO22XLTS U3421 ( .A0(n4468), .A1(d_ff_Yn[60]), .B0(n4458), .B1(
result_add_subt[60]), .Y(n2524) );
AO22XLTS U3422 ( .A0(n4468), .A1(d_ff_Yn[61]), .B0(n4464), .B1(
result_add_subt[61]), .Y(n2528) );
NAND2BXLTS U3423 ( .AN(n4455), .B(n5069), .Y(n3837) );
OAI211XLTS U3424 ( .A0(n4452), .A1(n4983), .B0(n4451), .C0(n4450), .Y(n4454)
);
AO22XLTS U3425 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[22]), .A1(
n4025), .B0(n3005), .B1(n2992), .Y(n2618) );
AO22XLTS U3426 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[27]), .A1(
n4029), .B0(n4028), .B1(n2994), .Y(n2623) );
AO22XLTS U3427 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[53]), .A1(
n4024), .B0(n4026), .B1(n2993), .Y(n2649) );
OAI31X1TS U3428 ( .A0(n4818), .A1(n4811), .A2(n3864), .B0(n4205), .Y(n2650)
);
NOR2X4TS U3429 ( .A(n3088), .B(n3060), .Y(n2964) );
OR4X2TS U3430 ( .A(add_subt_module_Add_Subt_result[36]), .B(
add_subt_module_Add_Subt_result[34]), .C(
add_subt_module_Add_Subt_result[35]), .D(n3844), .Y(n2966) );
BUFX3TS U3431 ( .A(n5079), .Y(n5106) );
INVX6TS U3432 ( .A(rst), .Y(n3015) );
BUFX3TS U3433 ( .A(n2960), .Y(n3016) );
OAI221X1TS U3434 ( .A0(n4915), .A1(add_subt_module_intDY[33]), .B0(n4913),
.B1(add_subt_module_intDX[62]), .C0(n3804), .Y(n3807) );
AND3X4TS U3435 ( .A(n4351), .B(n4819), .C(n4890), .Y(n3002) );
NOR2X2TS U3436 ( .A(cont_iter_out[3]), .B(n4369), .Y(n4354) );
AND3X4TS U3437 ( .A(n3031), .B(n4812), .C(n4890), .Y(n3001) );
CLKINVX6TS U3438 ( .A(n3004), .Y(n4714) );
NOR2X2TS U3439 ( .A(n4367), .B(n4507), .Y(n4377) );
AOI22X2TS U3440 ( .A0(cont_iter_out[1]), .A1(n3233), .B0(cont_iter_out[0]),
.B1(n4808), .Y(n4358) );
NOR4X1TS U3441 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(
add_subt_module_add_overflow_flag), .C(n4318), .D(n2950), .Y(n3059) );
NOR2X2TS U3442 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n4884), .Y(
n4324) );
AOI211X2TS U3443 ( .A0(add_subt_module_intDX[44]), .A1(n4898), .B0(n3461),
.C0(n3470), .Y(n3468) );
AOI21X2TS U3444 ( .A0(n4270), .A1(n4971), .B0(n4257), .Y(n4276) );
OAI21X2TS U3445 ( .A0(n4973), .A1(n4280), .B0(n4036), .Y(n4053) );
INVX2TS U3446 ( .A(n2984), .Y(n2985) );
INVX2TS U3447 ( .A(n2983), .Y(n2986) );
NOR2XLTS U3448 ( .A(n4897), .B(add_subt_module_intDY[53]), .Y(n3374) );
NOR4X2TS U3449 ( .A(n3375), .B(n3447), .C(n3459), .D(n3451), .Y(n3504) );
NOR3X2TS U3450 ( .A(n4367), .B(n4364), .C(n3050), .Y(n4375) );
AOI21X2TS U3451 ( .A0(n4149), .A1(n4973), .B0(n4250), .Y(n4272) );
OAI21X2TS U3452 ( .A0(n4972), .A1(n4280), .B0(n4050), .Y(n4064) );
OAI21X2TS U3453 ( .A0(n4836), .A1(n4280), .B0(n4221), .Y(n4239) );
OAI21X2TS U3454 ( .A0(n4975), .A1(n4280), .B0(n4244), .Y(n4264) );
BUFX4TS U3455 ( .A(n4456), .Y(n4479) );
BUFX4TS U3456 ( .A(n3215), .Y(n3221) );
BUFX4TS U3457 ( .A(n3215), .Y(n3206) );
BUFX6TS U3458 ( .A(n3215), .Y(n3217) );
BUFX6TS U3459 ( .A(n4776), .Y(n4804) );
INVX3TS U3460 ( .A(n4457), .Y(n4463) );
INVX6TS U3461 ( .A(n3001), .Y(n4501) );
CLKINVX6TS U3462 ( .A(n3001), .Y(n4500) );
BUFX6TS U3463 ( .A(n4789), .Y(n4773) );
OAI21X1TS U3464 ( .A0(n3089), .A1(n4994), .B0(n3057), .Y(n3058) );
OAI21X1TS U3465 ( .A0(n3089), .A1(n4996), .B0(n3057), .Y(n3071) );
OAI21X1TS U3466 ( .A0(n3089), .A1(n4995), .B0(n3057), .Y(n3084) );
OAI21X1TS U3467 ( .A0(n3089), .A1(n4997), .B0(n3057), .Y(n3090) );
AOI222X4TS U3468 ( .A0(n4156), .A1(n4146), .B0(n4288), .B1(n4145), .C0(n4144), .C1(n4284), .Y(n4166) );
BUFX4TS U3469 ( .A(n3029), .Y(n4462) );
NOR3X1TS U3470 ( .A(n4884), .B(n4817), .C(n4318), .Y(n3029) );
CLKINVX6TS U3471 ( .A(n3016), .Y(n5118) );
AOI222X4TS U3472 ( .A0(n4944), .A1(n4348), .B0(n4944), .B1(n4299), .C0(n4298), .C1(n4297), .Y(n4301) );
AOI211X1TS U3473 ( .A0(cont_var_out[1]), .A1(n4968), .B0(n4331), .C0(n4296),
.Y(n4299) );
AOI222X1TS U3474 ( .A0(n3308), .A1(d_ff2_Z[0]), .B0(n3258), .B1(d_ff1_Z[0]),
.C0(d_ff_Zn[0]), .C1(n3304), .Y(n3243) );
AOI222X1TS U3475 ( .A0(n3308), .A1(d_ff2_Z[3]), .B0(n3258), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n4492), .Y(n3232) );
AOI222X1TS U3476 ( .A0(n4491), .A1(d_ff2_Z[6]), .B0(n3258), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n4424), .Y(n3229) );
AOI222X1TS U3477 ( .A0(n3308), .A1(d_ff2_Z[5]), .B0(n3258), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n3298), .Y(n3242) );
AOI222X1TS U3478 ( .A0(n3308), .A1(d_ff2_Z[10]), .B0(n3258), .B1(d_ff1_Z[10]), .C0(d_ff_Zn[10]), .C1(n3298), .Y(n3248) );
AOI222X1TS U3479 ( .A0(n4404), .A1(d_ff2_Z[7]), .B0(n3258), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n3304), .Y(n3249) );
INVX2TS U3480 ( .A(n2966), .Y(n2987) );
OAI31X4TS U3481 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[3]), .A2(n3033),
.B0(n4495), .Y(n4381) );
AOI21X2TS U3482 ( .A0(n4808), .A1(n3046), .B0(n4360), .Y(n3033) );
AOI211X1TS U3483 ( .A0(n4313), .A1(n4811), .B0(n4321), .C0(n4312), .Y(n4315)
);
NOR4X4TS U3484 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(
add_subt_module_FS_Module_state_reg[2]), .C(n4884), .D(n4817), .Y(
n4321) );
INVX2TS U3485 ( .A(n2978), .Y(n2988) );
INVX2TS U3486 ( .A(n2974), .Y(n2989) );
INVX2TS U3487 ( .A(n2973), .Y(n2990) );
BUFX4TS U3488 ( .A(n3015), .Y(n5079) );
CLKINVX6TS U3489 ( .A(n4341), .Y(n4342) );
BUFX6TS U3490 ( .A(n4344), .Y(n4341) );
BUFX4TS U3491 ( .A(n3020), .Y(n5085) );
BUFX4TS U3492 ( .A(n2962), .Y(n5081) );
BUFX4TS U3493 ( .A(n2962), .Y(n5104) );
BUFX4TS U3494 ( .A(n5088), .Y(n5090) );
BUFX4TS U3495 ( .A(n5107), .Y(n5095) );
BUFX4TS U3496 ( .A(n5079), .Y(n5102) );
BUFX4TS U3497 ( .A(n5079), .Y(n5108) );
BUFX4TS U3498 ( .A(n5108), .Y(n5091) );
BUFX4TS U3499 ( .A(n5079), .Y(n5093) );
BUFX4TS U3500 ( .A(n5109), .Y(n5094) );
BUFX4TS U3501 ( .A(n5109), .Y(n5101) );
BUFX4TS U3502 ( .A(n5109), .Y(n5098) );
BUFX4TS U3503 ( .A(n5109), .Y(n5097) );
BUFX4TS U3504 ( .A(n3015), .Y(n5092) );
AOI21X2TS U3505 ( .A0(n4270), .A1(n4982), .B0(n4269), .Y(n4287) );
AOI21X2TS U3506 ( .A0(n3055), .A1(n2950), .B0(n3608), .Y(n4312) );
BUFX4TS U3507 ( .A(n5085), .Y(n5080) );
OAI21X2TS U3508 ( .A0(n4312), .A1(n3056), .B0(
add_subt_module_add_overflow_flag), .Y(n3088) );
NOR2X2TS U3509 ( .A(n3145), .B(n3088), .Y(n3542) );
BUFX4TS U3510 ( .A(n5108), .Y(n5099) );
BUFX6TS U3511 ( .A(n4482), .Y(n4470) );
BUFX3TS U3512 ( .A(n2960), .Y(n3017) );
AOI211X4TS U3513 ( .A0(n3516), .A1(n3515), .B0(n3514), .C0(n3513), .Y(n4558)
);
CLKINVX6TS U3514 ( .A(n4502), .Y(n4528) );
CLKINVX6TS U3515 ( .A(n4502), .Y(n4497) );
CLKINVX6TS U3516 ( .A(n2960), .Y(n5123) );
CLKINVX6TS U3517 ( .A(n2960), .Y(n5122) );
CLKINVX6TS U3518 ( .A(n2960), .Y(n5121) );
BUFX6TS U3519 ( .A(n3579), .Y(n3597) );
BUFX4TS U3520 ( .A(n3001), .Y(n4503) );
INVX6TS U3521 ( .A(n4503), .Y(n4527) );
NAND2X2TS U3522 ( .A(cont_iter_out[2]), .B(cont_iter_out[1]), .Y(n4336) );
NOR4X4TS U3523 ( .A(cont_iter_out[0]), .B(cont_iter_out[1]), .C(
cont_iter_out[3]), .D(n4820), .Y(n4367) );
OAI22X2TS U3524 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[1]), .B0(n3046),
.B1(n4336), .Y(n4380) );
NAND3X2TS U3525 ( .A(cont_iter_out[1]), .B(cont_iter_out[0]), .C(n4393), .Y(
n4352) );
AOI22X2TS U3526 ( .A0(n4331), .A1(n4429), .B0(cont_var_out[0]), .B1(n4352),
.Y(n4433) );
NAND2X1TS U3527 ( .A(cont_var_out[1]), .B(n4352), .Y(n4435) );
AOI22X4TS U3528 ( .A0(add_subt_module_LZA_output[3]), .A1(n3940), .B0(n3052),
.B1(add_subt_module_exp_oper_result[3]), .Y(n3103) );
NOR2X2TS U3529 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[2]),
.Y(n4351) );
AOI22X4TS U3530 ( .A0(add_subt_module_LZA_output[1]), .A1(n3940), .B0(n3052),
.B1(add_subt_module_exp_oper_result[1]), .Y(n4146) );
OAI21X2TS U3531 ( .A0(n4816), .A1(n4280), .B0(n4124), .Y(n4139) );
OAI21X2TS U3532 ( .A0(n4880), .A1(n4280), .B0(n4150), .Y(n4163) );
AOI222X4TS U3533 ( .A0(n4151), .A1(n4155), .B0(n4160), .B1(n4242), .C0(n4163), .C1(n4271), .Y(n4171) );
AOI211X1TS U3534 ( .A0(n4118), .A1(n4238), .B0(n4113), .C0(n4112), .Y(n4133)
);
AOI21X2TS U3535 ( .A0(n4270), .A1(n4986), .B0(n4102), .Y(n4118) );
CLKINVX6TS U3536 ( .A(n3016), .Y(n5137) );
CLKINVX6TS U3537 ( .A(n3016), .Y(n5138) );
CLKINVX6TS U3538 ( .A(n3003), .Y(n3712) );
CLKINVX6TS U3539 ( .A(n4017), .Y(n3740) );
CLKINVX6TS U3540 ( .A(n4017), .Y(n4016) );
CLKINVX6TS U3541 ( .A(n4502), .Y(n4492) );
INVX4TS U3542 ( .A(n2955), .Y(n4487) );
CLKINVX6TS U3543 ( .A(n3703), .Y(n3699) );
INVX4TS U3544 ( .A(n4502), .Y(n3301) );
INVX4TS U3545 ( .A(n2955), .Y(n3298) );
INVX4TS U3546 ( .A(n2955), .Y(n3304) );
NOR2X4TS U3547 ( .A(n4820), .B(n4887), .Y(n4393) );
NAND2X2TS U3548 ( .A(n4495), .B(n4887), .Y(n3311) );
NAND2X2TS U3549 ( .A(cont_iter_out[0]), .B(n4887), .Y(n3046) );
INVX4TS U3550 ( .A(n3002), .Y(n5159) );
NAND2X6TS U3551 ( .A(n3739), .B(n3145), .Y(n3615) );
NOR2X4TS U3552 ( .A(n3103), .B(n3057), .Y(n3541) );
NAND2X6TS U3553 ( .A(n3601), .B(n3340), .Y(n3742) );
INVX4TS U3554 ( .A(n3517), .Y(n3711) );
INVX6TS U3555 ( .A(n3517), .Y(n3700) );
CLKINVX6TS U3556 ( .A(n3517), .Y(n4564) );
CLKINVX6TS U3557 ( .A(n2960), .Y(n5133) );
BUFX4TS U3558 ( .A(n3258), .Y(n3296) );
BUFX4TS U3559 ( .A(n3258), .Y(n3307) );
BUFX4TS U3560 ( .A(n3258), .Y(n3302) );
BUFX6TS U3561 ( .A(n4645), .Y(n4642) );
CLKINVX6TS U3562 ( .A(n3004), .Y(n4793) );
CLKINVX6TS U3563 ( .A(n3004), .Y(n4799) );
CLKINVX6TS U3564 ( .A(n3004), .Y(n4660) );
INVX6TS U3565 ( .A(n3004), .Y(n4631) );
CLKINVX6TS U3566 ( .A(n3003), .Y(n2991) );
BUFX6TS U3567 ( .A(n4337), .Y(n4344) );
CLKINVX6TS U3568 ( .A(n4344), .Y(n4343) );
INVX3TS U3569 ( .A(n4152), .Y(n4215) );
CLKINVX6TS U3570 ( .A(n4525), .Y(n4523) );
BUFX6TS U3571 ( .A(n3023), .Y(n4525) );
NOR2X4TS U3572 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(n4436), .Y(
n4455) );
INVX6TS U3573 ( .A(n3001), .Y(n3305) );
CLKINVX6TS U3574 ( .A(n3517), .Y(n3714) );
INVX6TS U3575 ( .A(n3517), .Y(n3721) );
INVX6TS U3576 ( .A(n3517), .Y(n3818) );
BUFX6TS U3577 ( .A(n4789), .Y(n4798) );
BUFX4TS U3578 ( .A(n4789), .Y(n4696) );
BUFX4TS U3579 ( .A(n4789), .Y(n4677) );
BUFX6TS U3580 ( .A(n4789), .Y(n4805) );
BUFX6TS U3581 ( .A(n2950), .Y(n4205) );
AOI22X2TS U3582 ( .A0(n4149), .A1(n5003), .B0(n4270), .B1(n4844), .Y(n3617)
);
BUFX6TS U3583 ( .A(n3366), .Y(n4270) );
AOI21X2TS U3584 ( .A0(n4270), .A1(n4850), .B0(n4045), .Y(n4060) );
AOI21X2TS U3585 ( .A0(n4270), .A1(n4990), .B0(n4190), .Y(n4207) );
AOI21X2TS U3586 ( .A0(n4270), .A1(n4965), .B0(n4227), .Y(n4245) );
BUFX6TS U3587 ( .A(n4701), .Y(n4802) );
AOI21X2TS U3588 ( .A0(n3053), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(
n3075), .Y(n3349) );
AOI21X2TS U3589 ( .A0(n3053), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(
n3083), .Y(n3355) );
AOI21X2TS U3590 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .A1(
n3053), .B0(n3058), .Y(n3343) );
AOI21X2TS U3591 ( .A0(n3053), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(
n3090), .Y(n3373) );
AOI211X2TS U3592 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(
n3541), .C0(n3128), .Y(n3606) );
AOI211X2TS U3593 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(
n3541), .C0(n3142), .Y(n3610) );
AOI211X2TS U3594 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
n3541), .C0(n3113), .Y(n3595) );
AOI211X2TS U3595 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(
n3541), .C0(n3117), .Y(n3589) );
NOR2X2TS U3596 ( .A(add_subt_module_Add_Subt_result[15]), .B(n3832), .Y(
n3972) );
INVX2TS U3597 ( .A(n2963), .Y(n2992) );
AOI211X1TS U3598 ( .A0(add_subt_module_Add_Subt_result[44]), .A1(n3841),
.B0(add_subt_module_Add_Subt_result[47]), .C0(
add_subt_module_Add_Subt_result[48]), .Y(n3843) );
NOR4X2TS U3599 ( .A(add_subt_module_Add_Subt_result[46]), .B(
add_subt_module_Add_Subt_result[44]), .C(
add_subt_module_Add_Subt_result[45]), .D(n3997), .Y(n3854) );
NOR3X4TS U3600 ( .A(add_subt_module_Add_Subt_result[8]), .B(
add_subt_module_Add_Subt_result[7]), .C(n3834), .Y(n3955) );
AOI211X1TS U3601 ( .A0(n3830), .A1(n3985), .B0(
add_subt_module_Add_Subt_result[8]), .C0(
add_subt_module_Add_Subt_result[7]), .Y(n3835) );
NOR4X2TS U3602 ( .A(add_subt_module_Add_Subt_result[48]), .B(
add_subt_module_Add_Subt_result[50]), .C(
add_subt_module_Add_Subt_result[49]), .D(n3964), .Y(n4443) );
NOR3X1TS U3603 ( .A(add_subt_module_Add_Subt_result[48]), .B(
add_subt_module_Add_Subt_result[50]), .C(
add_subt_module_Add_Subt_result[49]), .Y(n3965) );
INVX2TS U3604 ( .A(n2968), .Y(n2994) );
AOI221X1TS U3605 ( .A0(n4948), .A1(add_subt_module_intDY[29]), .B0(
add_subt_module_intDX[0]), .B1(n4961), .C0(n3771), .Y(n3774) );
AOI221X1TS U3606 ( .A0(n4964), .A1(add_subt_module_intDY[25]), .B0(
add_subt_module_intDY[2]), .B1(n4946), .C0(n3772), .Y(n3773) );
OAI221XLTS U3607 ( .A0(n4827), .A1(n2995), .B0(n4928), .B1(
add_subt_module_intDY[40]), .C0(n3795), .Y(n3800) );
OAI221XLTS U3608 ( .A0(n4952), .A1(n2996), .B0(n4828), .B1(
add_subt_module_intDY[14]), .C0(n3744), .Y(n3745) );
OAI221X1TS U3609 ( .A0(n4905), .A1(add_subt_module_intDX[55]), .B0(n4832),
.B1(add_subt_module_intDY[34]), .C0(n3794), .Y(n3801) );
INVX2TS U3610 ( .A(n2965), .Y(n2995) );
INVX2TS U3611 ( .A(n2970), .Y(n2996) );
OAI221X1TS U3612 ( .A0(n4831), .A1(add_subt_module_intDY[42]), .B0(n4931),
.B1(add_subt_module_intDY[9]), .C0(n3802), .Y(n3809) );
AOI221X1TS U3613 ( .A0(n4963), .A1(add_subt_module_intDY[35]), .B0(
add_subt_module_intDY[8]), .B1(n4959), .C0(n3770), .Y(n3775) );
OAI221XLTS U3614 ( .A0(n4919), .A1(add_subt_module_intDY[39]), .B0(n4924),
.B1(add_subt_module_intDY[23]), .C0(n3749), .Y(n3755) );
INVX2TS U3615 ( .A(n2969), .Y(n2997) );
AOI211X1TS U3616 ( .A0(add_subt_module_intDX[52]), .A1(n4926), .B0(n3374),
.C0(n3493), .Y(n3495) );
OAI221X1TS U3617 ( .A0(n4916), .A1(add_subt_module_intDY[11]), .B0(n4926),
.B1(add_subt_module_intDX[52]), .C0(n3750), .Y(n3754) );
OAI211X2TS U3618 ( .A0(add_subt_module_intDY[28]), .A1(n4930), .B0(n3391),
.C0(n3382), .Y(n3441) );
OAI221XLTS U3619 ( .A0(n4932), .A1(add_subt_module_intDY[49]), .B0(n4930),
.B1(add_subt_module_intDY[28]), .C0(n3786), .Y(n3792) );
AOI211XLTS U3620 ( .A0(add_subt_module_intDY[46]), .A1(n3474), .B0(n3473),
.C0(n3472), .Y(n3511) );
OAI221XLTS U3621 ( .A0(n4938), .A1(add_subt_module_intDY[21]), .B0(n4927),
.B1(add_subt_module_intDY[46]), .C0(n3797), .Y(n3798) );
OAI211X2TS U3622 ( .A0(add_subt_module_intDY[12]), .A1(n4950), .B0(n3419),
.C0(n3393), .Y(n3423) );
AOI221X1TS U3623 ( .A0(n4950), .A1(add_subt_module_intDY[12]), .B0(
add_subt_module_intDY[18]), .B1(n4958), .C0(n3764), .Y(n3765) );
OAI211X2TS U3624 ( .A0(add_subt_module_intDY[20]), .A1(n4940), .B0(n3438),
.C0(n3392), .Y(n3432) );
OAI221XLTS U3625 ( .A0(n4940), .A1(add_subt_module_intDY[20]), .B0(n4830),
.B1(add_subt_module_intDY[50]), .C0(n3780), .Y(n3781) );
OAI221XLTS U3626 ( .A0(n4933), .A1(add_subt_module_intDY[15]), .B0(n4939),
.B1(add_subt_module_intDY[17]), .C0(n3805), .Y(n3806) );
INVX2TS U3627 ( .A(n2971), .Y(n2998) );
AOI222X4TS U3628 ( .A0(n4714), .A1(add_subt_module_intDY[63]), .B0(n4805),
.B1(d_ff3_sh_x_out[63]), .C0(n4645), .C1(d_ff3_sh_y_out[63]), .Y(n3239) );
NOR4X2TS U3629 ( .A(n3817), .B(n3816), .C(n3815), .D(n3814), .Y(n4559) );
AOI222X4TS U3630 ( .A0(n3305), .A1(d_ff2_Z[2]), .B0(n3258), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n3301), .Y(n3252) );
AOI222X4TS U3631 ( .A0(n3305), .A1(d_ff2_Z[1]), .B0(n3258), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n3301), .Y(n3246) );
AOI222X4TS U3632 ( .A0(n3305), .A1(d_ff2_Z[11]), .B0(n3258), .B1(d_ff1_Z[11]), .C0(d_ff_Zn[11]), .C1(n3301), .Y(n3244) );
AOI222X4TS U3633 ( .A0(n4404), .A1(d_ff2_Z[8]), .B0(n3258), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n3301), .Y(n3247) );
AOI222X4TS U3634 ( .A0(n4404), .A1(d_ff2_Z[12]), .B0(n3258), .B1(d_ff1_Z[12]), .C0(d_ff_Zn[12]), .C1(n3301), .Y(n3245) );
AOI222X1TS U3635 ( .A0(n3305), .A1(d_ff2_Z[36]), .B0(n3296), .B1(d_ff1_Z[36]), .C0(d_ff_Zn[36]), .C1(n3301), .Y(n3272) );
NOR2X2TS U3636 ( .A(n4398), .B(n4363), .Y(n4366) );
AOI31X2TS U3637 ( .A0(n4820), .A1(n4808), .A2(n4887), .B0(n4507), .Y(n4363)
);
NOR2X2TS U3638 ( .A(add_subt_module_Add_Subt_result[18]), .B(n3824), .Y(
n4449) );
AOI31X2TS U3639 ( .A0(n4369), .A1(n3046), .A2(n3035), .B0(n3049), .Y(n4371)
);
BUFX4TS U3640 ( .A(n2962), .Y(n5089) );
OAI21X2TS U3641 ( .A0(n4814), .A1(n4263), .B0(n4262), .Y(n4283) );
OAI21X2TS U3642 ( .A0(n4971), .A1(n4263), .B0(n4031), .Y(n4048) );
OAI21X2TS U3643 ( .A0(n4976), .A1(n4263), .B0(n4199), .Y(n4217) );
OAI21X2TS U3644 ( .A0(n4815), .A1(n4263), .B0(n4093), .Y(n4107) );
OAI21X2TS U3645 ( .A0(n4972), .A1(n4263), .B0(n4232), .Y(n4255) );
OAI21X2TS U3646 ( .A0(n4990), .A1(n4263), .B0(n4087), .Y(n4103) );
OAI21X2TS U3647 ( .A0(n4936), .A1(n4263), .B0(n4073), .Y(n4090) );
OAI21X2TS U3648 ( .A0(n4870), .A1(n4263), .B0(n4167), .Y(n4182) );
OAI21X2TS U3649 ( .A0(n4970), .A1(n4263), .B0(n4206), .Y(n4224) );
OAI21X2TS U3650 ( .A0(n4988), .A1(n4263), .B0(n4181), .Y(n4195) );
OAI21X2TS U3651 ( .A0(n4843), .A1(n4263), .B0(n4068), .Y(n4083) );
OAI21X2TS U3652 ( .A0(n4816), .A1(n4263), .B0(n4154), .Y(n4168) );
OAI21X2TS U3653 ( .A0(n4974), .A1(n4263), .B0(n4162), .Y(n4177) );
OAI21X2TS U3654 ( .A0(n4965), .A1(n4263), .B0(n4055), .Y(n4069) );
OAI21X2TS U3655 ( .A0(n4880), .A1(n4263), .B0(n4129), .Y(n4144) );
OAI21X2TS U3656 ( .A0(n4983), .A1(n4263), .B0(n3365), .Y(n4034) );
INVX4TS U3657 ( .A(n4149), .Y(n4281) );
CLKINVX6TS U3658 ( .A(n4149), .Y(n4263) );
OAI32X1TS U3659 ( .A0(n3868), .A1(n3002), .A2(n4985), .B0(n4433), .B1(n3867),
.Y(n2852) );
OAI32X1TS U3660 ( .A0(n3868), .A1(n3002), .A2(n4984), .B0(n4435), .B1(n3867),
.Y(n2851) );
NOR3X2TS U3661 ( .A(cordic_FSM_state_reg[0]), .B(n4819), .C(n3865), .Y(n3868) );
AOI222X1TS U3662 ( .A0(n3305), .A1(d_ff2_Z[63]), .B0(n3296), .B1(d_ff1_Z[63]), .C0(d_ff_Zn[63]), .C1(n3301), .Y(n3270) );
NAND3X2TS U3663 ( .A(n4313), .B(n4811), .C(n4818), .Y(n1959) );
AOI211X2TS U3664 ( .A0(cont_iter_out[0]), .A1(cont_iter_out[1]), .B0(n4359),
.C0(n3311), .Y(n4385) );
NOR3X4TS U3665 ( .A(cont_iter_out[2]), .B(cont_iter_out[1]), .C(
cont_iter_out[0]), .Y(n4359) );
CLKINVX6TS U3666 ( .A(n3621), .Y(n3702) );
BUFX6TS U3667 ( .A(n3069), .Y(n3613) );
AOI22X2TS U3668 ( .A0(add_subt_module_LZA_output[4]), .A1(n3940), .B0(n3052),
.B1(add_subt_module_exp_oper_result[4]), .Y(n3064) );
CLKINVX6TS U3669 ( .A(n4253), .Y(n4288) );
AOI21X2TS U3670 ( .A0(n3053), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(
n3076), .Y(n3363) );
AOI21X2TS U3671 ( .A0(n3053), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(
n3071), .Y(n3346) );
AOI21X2TS U3672 ( .A0(n3053), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n3084), .Y(n3360) );
NOR2X2TS U3673 ( .A(d_ff2_Y[59]), .B(n4514), .Y(n4517) );
NOR2X2TS U3674 ( .A(d_ff2_X[59]), .B(n4412), .Y(n4415) );
NOR3X2TS U3675 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(intadd_375_n1), .Y(
n4410) );
AOI21X2TS U3676 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .A1(
n3053), .B0(n3061), .Y(n3352) );
AOI211X2TS U3677 ( .A0(n3060), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(
n3541), .C0(n3108), .Y(n3592) );
INVX4TS U3678 ( .A(n2955), .Y(n4424) );
INVX3TS U3679 ( .A(n4152), .Y(n4289) );
INVX4TS U3680 ( .A(n4474), .Y(n4465) );
INVX3TS U3681 ( .A(n4477), .Y(n4459) );
BUFX4TS U3682 ( .A(n4457), .Y(n4477) );
INVX4TS U3683 ( .A(n4341), .Y(n4346) );
BUFX6TS U3684 ( .A(n3109), .Y(n3596) );
CLKINVX6TS U3685 ( .A(n4234), .Y(n4246) );
BUFX6TS U3686 ( .A(n4021), .Y(n3913) );
CLKINVX6TS U3687 ( .A(n4421), .Y(n4510) );
BUFX6TS U3688 ( .A(n4482), .Y(n4469) );
CLKINVX6TS U3689 ( .A(n4458), .Y(n4468) );
NAND2X4TS U3690 ( .A(n3056), .B(add_subt_module_add_overflow_flag), .Y(
add_subt_module_FSM_exp_operation_A_S) );
OAI22X2TS U3691 ( .A0(n4320), .A1(n4817), .B0(n3673), .B1(n2950), .Y(n3056)
);
INVX6TS U3692 ( .A(n3001), .Y(n3308) );
NOR2X2TS U3693 ( .A(add_subt_module_Add_Subt_result[6]), .B(
add_subt_module_Add_Subt_result[5]), .Y(n3830) );
NOR2X2TS U3694 ( .A(add_subt_module_Add_Subt_result[24]), .B(n3845), .Y(
n3963) );
NOR3X2TS U3695 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(intadd_374_n1), .Y(
n4512) );
BUFX6TS U3696 ( .A(n3149), .Y(n3179) );
BUFX6TS U3697 ( .A(n4545), .Y(n4779) );
OAI221X1TS U3698 ( .A0(n4917), .A1(add_subt_module_intDY[47]), .B0(n4824),
.B1(add_subt_module_intDY[10]), .C0(n3785), .Y(n3793) );
OAI32X1TS U3699 ( .A0(add_subt_module_Add_Subt_result[52]), .A1(
add_subt_module_Add_Subt_result[50]), .A2(n4973), .B0(n4814), .B1(
add_subt_module_Add_Subt_result[52]), .Y(n4439) );
AOI32X1TS U3700 ( .A0(n4829), .A1(n3384), .A2(add_subt_module_intDY[26]),
.B0(add_subt_module_intDY[27]), .B1(n4943), .Y(n3385) );
OAI221XLTS U3701 ( .A0(n4906), .A1(add_subt_module_intDY[7]), .B0(n4943),
.B1(add_subt_module_intDY[27]), .C0(n3803), .Y(n3808) );
AOI32X1TS U3702 ( .A0(n4958), .A1(n3429), .A2(add_subt_module_intDY[18]),
.B0(add_subt_module_intDY[19]), .B1(n4839), .Y(n3430) );
OAI221X1TS U3703 ( .A0(n4839), .A1(add_subt_module_intDY[19]), .B0(n4907),
.B1(add_subt_module_intDY[5]), .C0(n3779), .Y(n3782) );
OAI221X1TS U3704 ( .A0(n4922), .A1(add_subt_module_intDY[1]), .B0(n4945),
.B1(add_subt_module_intDX[61]), .C0(n3748), .Y(n3756) );
OAI221X1TS U3705 ( .A0(n4914), .A1(add_subt_module_intDY[36]), .B0(n3788),
.B1(add_subt_module_intDX[58]), .C0(n3787), .Y(n3791) );
OAI221XLTS U3706 ( .A0(n4918), .A1(add_subt_module_intDY[44]), .B0(n4829),
.B1(add_subt_module_intDY[26]), .C0(n3789), .Y(n3790) );
OAI221X1TS U3707 ( .A0(n4920), .A1(add_subt_module_intDY[6]), .B0(n4910),
.B1(add_subt_module_intDY[41]), .C0(n3796), .Y(n3799) );
OAI221X1TS U3708 ( .A0(n4921), .A1(add_subt_module_intDY[16]), .B0(n4923),
.B1(add_subt_module_intDY[43]), .C0(n3777), .Y(n3784) );
OR3X2TS U3709 ( .A(n3103), .B(n3063), .C(n3062), .Y(n2999) );
BUFX6TS U3710 ( .A(n3894), .Y(n4021) );
OAI21XLTS U3711 ( .A0(add_subt_module_intDX[1]), .A1(n4893), .B0(
add_subt_module_intDX[0]), .Y(n3396) );
OAI21XLTS U3712 ( .A0(add_subt_module_intDY[13]), .A1(n4955), .B0(
add_subt_module_intDY[12]), .Y(n3406) );
NOR2XLTS U3713 ( .A(n3496), .B(add_subt_module_intDX[48]), .Y(n3497) );
OAI21XLTS U3714 ( .A0(add_subt_module_intDY[55]), .A1(n4821), .B0(
add_subt_module_intDY[54]), .Y(n3503) );
OAI21XLTS U3715 ( .A0(n2993), .A1(n4439), .B0(n4844), .Y(n4440) );
NOR2XLTS U3716 ( .A(n3494), .B(n3493), .Y(n3507) );
OAI21XLTS U3717 ( .A0(n3471), .A1(n3470), .B0(n3469), .Y(n3473) );
NOR2XLTS U3718 ( .A(add_subt_module_Add_Subt_result[4]), .B(n4837), .Y(n3945) );
NOR3XLTS U3719 ( .A(n3103), .B(n3064), .C(n3063), .Y(n3065) );
OAI211XLTS U3720 ( .A0(add_subt_module_Add_Subt_result[5]), .A1(n3945), .B0(
n3955), .C0(n4975), .Y(n3947) );
NOR2XLTS U3721 ( .A(n4912), .B(n4008), .Y(n3882) );
NOR2XLTS U3722 ( .A(n4858), .B(n4020), .Y(n3918) );
NOR2XLTS U3723 ( .A(n4872), .B(n3901), .Y(n3902) );
INVX2TS U3724 ( .A(n4302), .Y(n3055) );
NOR2XLTS U3725 ( .A(n4904), .B(n4008), .Y(n3883) );
NOR2XLTS U3726 ( .A(n4862), .B(n3901), .Y(n3911) );
NOR2XLTS U3727 ( .A(n4868), .B(n3925), .Y(n3905) );
NOR2XLTS U3728 ( .A(n4977), .B(n4009), .Y(n3874) );
OAI211XLTS U3729 ( .A0(n4014), .A1(n4994), .B0(n3332), .C0(n4012), .Y(n3333)
);
NOR2XLTS U3730 ( .A(n4125), .B(n3364), .Y(n4117) );
OAI21XLTS U3731 ( .A0(n4235), .A1(n3313), .B0(n4218), .Y(n4219) );
NOR3XLTS U3732 ( .A(n4332), .B(n4427), .C(n4523), .Y(n3869) );
AOI31XLTS U3733 ( .A0(add_subt_module_Add_Subt_result[16]), .A1(n4449), .A2(
n4815), .B0(n3859), .Y(n3861) );
OR2X1TS U3734 ( .A(d_ff2_X[56]), .B(intadd_375_n1), .Y(n4407) );
NOR3XLTS U3735 ( .A(cont_iter_out[3]), .B(n4367), .C(n4421), .Y(n4368) );
OAI21XLTS U3736 ( .A0(n3589), .A1(n3742), .B0(n3588), .Y(n2555) );
OAI21XLTS U3737 ( .A0(n2972), .A1(n3742), .B0(n3727), .Y(n2540) );
OAI21XLTS U3738 ( .A0(n3616), .A1(n3742), .B0(n3603), .Y(n2557) );
OAI211XLTS U3739 ( .A0(n3592), .A1(n3615), .B0(n3112), .C0(n3613), .Y(n2568)
);
OAI211XLTS U3740 ( .A0(n3349), .A1(n3615), .B0(n3079), .C0(n3613), .Y(n2576)
);
OAI21XLTS U3741 ( .A0(n3004), .A1(n4913), .B0(n3234), .Y(n1957) );
OAI211XLTS U3742 ( .A0(n3004), .A1(n4945), .B0(n3236), .C0(n3240), .Y(n1956)
);
OAI21XLTS U3743 ( .A0(n4946), .A1(n3702), .B0(n3691), .Y(n1706) );
OAI21XLTS U3744 ( .A0(n4829), .A1(n3699), .B0(n3667), .Y(n1732) );
OAI21XLTS U3745 ( .A0(n4915), .A1(n3699), .B0(n3685), .Y(n1753) );
OAI21XLTS U3746 ( .A0(n4826), .A1(n3699), .B0(n3683), .Y(n1771) );
OAI21XLTS U3747 ( .A0(n4919), .A1(n3702), .B0(n3625), .Y(n1805) );
OAI21XLTS U3748 ( .A0(n4831), .A1(n3003), .B0(n3553), .Y(n1821) );
OAI21XLTS U3749 ( .A0(n4923), .A1(n3003), .B0(n3570), .Y(n1842) );
OAI21XLTS U3750 ( .A0(n4931), .A1(n3657), .B0(n3537), .Y(n1868) );
OAI21XLTS U3751 ( .A0(n4917), .A1(n3725), .B0(n3720), .Y(n1888) );
OAI21XLTS U3752 ( .A0(n4926), .A1(n3725), .B0(n3707), .Y(n1911) );
OAI21XLTS U3753 ( .A0(n3788), .A1(n4560), .B0(n3654), .Y(n1929) );
OAI21XLTS U3754 ( .A0(n4049), .A1(n4091), .B0(n3619), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[51]) );
OAI21XLTS U3755 ( .A0(n4040), .A1(n4091), .B0(n3619), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[53]) );
NOR2XLTS U3756 ( .A(n4300), .B(n4296), .Y(ready_cordic) );
NOR2X2TS U3757 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(n4811), .Y(
n4317) );
NAND2X1TS U3758 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(n4317), .Y(
n4320) );
NOR2X2TS U3759 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(n4818), .Y(
n4323) );
NAND2X1TS U3760 ( .A(n4884), .B(n4817), .Y(n3864) );
INVX2TS U3761 ( .A(n3864), .Y(n4313) );
NAND2X1TS U3762 ( .A(n4323), .B(n4313), .Y(n3673) );
XOR2X1TS U3763 ( .A(DP_OP_92J138_122_9081_n1), .B(
add_subt_module_FSM_exp_operation_A_S), .Y(n3672) );
INVX2TS U3764 ( .A(n3056), .Y(n3006) );
OR4X2TS U3765 ( .A(add_subt_module_Exp_Operation_Module_Data_S[2]), .B(
add_subt_module_Exp_Operation_Module_Data_S[1]), .C(
add_subt_module_Exp_Operation_Module_Data_S[0]), .D(n3006), .Y(n3007)
);
OR4X2TS U3766 ( .A(add_subt_module_Exp_Operation_Module_Data_S[5]), .B(
add_subt_module_Exp_Operation_Module_Data_S[4]), .C(
add_subt_module_Exp_Operation_Module_Data_S[3]), .D(n3007), .Y(n3008)
);
OR4X2TS U3767 ( .A(add_subt_module_Exp_Operation_Module_Data_S[8]), .B(
add_subt_module_Exp_Operation_Module_Data_S[7]), .C(
add_subt_module_Exp_Operation_Module_Data_S[6]), .D(n3008), .Y(n3009)
);
OR4X2TS U3768 ( .A(n3672), .B(
add_subt_module_Exp_Operation_Module_Data_S[10]), .C(
add_subt_module_Exp_Operation_Module_Data_S[9]), .D(n3009), .Y(n3010)
);
OAI21XLTS U3769 ( .A0(n3056), .A1(n4998), .B0(n3010), .Y(n2934) );
BUFX3TS U3770 ( .A(n3005), .Y(n4026) );
INVX4TS U3771 ( .A(n3004), .Y(n4803) );
NOR3XLTS U3772 ( .A(sel_mux_2_reg[1]), .B(n4985), .C(n4803), .Y(n3011) );
CLKBUFX2TS U3773 ( .A(n3011), .Y(n3040) );
BUFX4TS U3774 ( .A(n3040), .Y(n4789) );
NOR3X1TS U3775 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .C(n4714), .Y(
n3037) );
BUFX4TS U3776 ( .A(n3037), .Y(n4645) );
AOI22X1TS U3777 ( .A0(d_ff3_sh_x_out[59]), .A1(n4805), .B0(
d_ff3_sh_y_out[59]), .B1(n4645), .Y(n3013) );
NOR3XLTS U3778 ( .A(sel_mux_2_reg[0]), .B(n4803), .C(n4984), .Y(n3012) );
CLKBUFX2TS U3779 ( .A(n3012), .Y(n4545) );
NAND2X2TS U3780 ( .A(n4545), .B(d_ff3_LUT_out[48]), .Y(n3240) );
OAI211XLTS U3781 ( .A0(n3004), .A1(n4841), .B0(n3013), .C0(n3240), .Y(n1954)
);
NAND2X1TS U3782 ( .A(cordic_FSM_state_reg[2]), .B(n4819), .Y(n4300) );
NAND2X1TS U3783 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.Y(n4296) );
BUFX3TS U3784 ( .A(n3005), .Y(n4028) );
BUFX3TS U3785 ( .A(n3005), .Y(n4027) );
AOI22X1TS U3786 ( .A0(n4677), .A1(d_ff3_sh_x_out[51]), .B0(n4645), .B1(
d_ff3_sh_y_out[51]), .Y(n3014) );
OAI211XLTS U3787 ( .A0(n3004), .A1(n5005), .B0(n3014), .C0(n3240), .Y(n1906)
);
CLKBUFX2TS U3788 ( .A(n3015), .Y(n3020) );
CLKBUFX2TS U3789 ( .A(n3020), .Y(n3021) );
BUFX3TS U3790 ( .A(n5085), .Y(n5084) );
INVX4TS U3791 ( .A(n3002), .Y(n5130) );
INVX4TS U3792 ( .A(n2960), .Y(n5116) );
INVX4TS U3793 ( .A(n2960), .Y(n5113) );
BUFX3TS U3794 ( .A(n2962), .Y(n5086) );
CLKBUFX2TS U3795 ( .A(n3017), .Y(n3019) );
INVX4TS U3796 ( .A(n3019), .Y(n5119) );
CLKBUFX2TS U3797 ( .A(n3020), .Y(n3018) );
BUFX3TS U3798 ( .A(n5085), .Y(n5087) );
INVX4TS U3799 ( .A(n2960), .Y(n5114) );
INVX4TS U3800 ( .A(n2960), .Y(n5131) );
INVX4TS U3801 ( .A(n3017), .Y(n5132) );
INVX4TS U3802 ( .A(n3016), .Y(n5117) );
INVX4TS U3803 ( .A(n3017), .Y(n5149) );
INVX4TS U3804 ( .A(n3017), .Y(n5148) );
INVX4TS U3805 ( .A(n3017), .Y(n5147) );
INVX4TS U3806 ( .A(n2960), .Y(n5158) );
INVX4TS U3807 ( .A(n3002), .Y(n5157) );
INVX4TS U3808 ( .A(n3016), .Y(n5156) );
INVX4TS U3809 ( .A(n2960), .Y(n5154) );
INVX4TS U3810 ( .A(n2960), .Y(n5153) );
INVX4TS U3811 ( .A(n3002), .Y(n5152) );
INVX4TS U3812 ( .A(n3002), .Y(n5151) );
INVX4TS U3813 ( .A(n3017), .Y(n5120) );
INVX4TS U3814 ( .A(n3016), .Y(n5136) );
INVX4TS U3815 ( .A(n2960), .Y(n5135) );
INVX4TS U3816 ( .A(n3017), .Y(n5134) );
INVX4TS U3817 ( .A(n3017), .Y(n5145) );
INVX4TS U3818 ( .A(n2960), .Y(n5144) );
INVX4TS U3819 ( .A(n3017), .Y(n5143) );
INVX4TS U3820 ( .A(n2960), .Y(n5146) );
INVX4TS U3821 ( .A(n3017), .Y(n5142) );
INVX4TS U3822 ( .A(n3016), .Y(n5141) );
INVX4TS U3823 ( .A(n2960), .Y(n5140) );
BUFX3TS U3824 ( .A(n3015), .Y(n5109) );
BUFX3TS U3825 ( .A(n2962), .Y(n5083) );
BUFX3TS U3826 ( .A(n5107), .Y(n5082) );
BUFX3TS U3827 ( .A(n5108), .Y(n5103) );
BUFX3TS U3828 ( .A(n2962), .Y(n5105) );
INVX4TS U3829 ( .A(n3019), .Y(n5129) );
BUFX3TS U3830 ( .A(n5088), .Y(n5100) );
INVX4TS U3831 ( .A(n3002), .Y(n5111) );
BUFX3TS U3832 ( .A(n5108), .Y(n5096) );
INVX4TS U3833 ( .A(n3019), .Y(n5127) );
INVX4TS U3834 ( .A(n2960), .Y(n5124) );
INVX4TS U3835 ( .A(n3002), .Y(n5125) );
INVX4TS U3836 ( .A(n3002), .Y(n5112) );
INVX4TS U3837 ( .A(n3016), .Y(n5126) );
INVX4TS U3838 ( .A(n3019), .Y(n5128) );
INVX4TS U3839 ( .A(n3002), .Y(n5110) );
AOI2BB2XLTS U3840 ( .B0(d_ff3_sign_out), .B1(n4968), .A0N(n4968), .A1N(
d_ff3_sign_out), .Y(n3022) );
INVX2TS U3841 ( .A(cont_iter_out[0]), .Y(n3233) );
NAND2X2TS U3842 ( .A(cont_iter_out[1]), .B(n4820), .Y(n4397) );
NOR2X1TS U3843 ( .A(n3233), .B(n4397), .Y(n3028) );
NAND2X1TS U3844 ( .A(cordic_FSM_state_reg[2]), .B(n4812), .Y(n3865) );
INVX2TS U3845 ( .A(n3865), .Y(n4298) );
NAND3XLTS U3846 ( .A(cordic_FSM_state_reg[0]), .B(n4298), .C(n4819), .Y(
n3023) );
AOI211X1TS U3847 ( .A0(cont_iter_out[2]), .A1(n4808), .B0(n4393), .C0(n4421),
.Y(n3027) );
NAND2X1TS U3848 ( .A(n3027), .B(n4355), .Y(n3024) );
OA22X1TS U3849 ( .A0(n3028), .A1(n3024), .B0(n4510), .B1(d_ff3_LUT_out[10]),
.Y(n2805) );
BUFX3TS U3850 ( .A(n4421), .Y(n4423) );
INVX2TS U3851 ( .A(n4397), .Y(n4360) );
INVX4TS U3852 ( .A(n4525), .Y(n4495) );
OAI2BB1X1TS U3853 ( .A0N(d_ff3_LUT_out[12]), .A1N(n4423), .B0(n4381), .Y(
n2807) );
INVX2TS U3854 ( .A(n4393), .Y(n3025) );
OAI21X1TS U3855 ( .A0(n3025), .A1(n4358), .B0(n4495), .Y(n4401) );
INVX2TS U3856 ( .A(n4336), .Y(n4369) );
NAND2X1TS U3857 ( .A(cont_iter_out[3]), .B(n3233), .Y(n3035) );
NOR2X1TS U3858 ( .A(n3046), .B(n4380), .Y(n3049) );
NOR2X2TS U3859 ( .A(cont_iter_out[0]), .B(cont_iter_out[3]), .Y(n4379) );
NAND2X2TS U3860 ( .A(n4360), .B(n4379), .Y(n4394) );
NAND2X1TS U3861 ( .A(n4371), .B(n4394), .Y(n3026) );
OA22X1TS U3862 ( .A0(n4401), .A1(n3026), .B0(n4510), .B1(d_ff3_LUT_out[27]),
.Y(n2822) );
NAND2X1TS U3863 ( .A(n3027), .B(n4394), .Y(n4365) );
OA22X1TS U3864 ( .A0(n3028), .A1(n4365), .B0(n4510), .B1(d_ff3_LUT_out[31]),
.Y(n2826) );
NAND2BXLTS U3865 ( .AN(n3033), .B(n4887), .Y(n4376) );
OA22X1TS U3866 ( .A0(n4510), .A1(d_ff3_LUT_out[24]), .B0(n4365), .B1(n4376),
.Y(n2819) );
AO22XLTS U3867 ( .A0(n4498), .A1(intadd_375_SUM_1_), .B0(n4525), .B1(
d_ff3_sh_x_out[54]), .Y(n2780) );
AO22XLTS U3868 ( .A0(n4521), .A1(intadd_375_SUM_2_), .B0(n4525), .B1(
d_ff3_sh_x_out[55]), .Y(n2779) );
AO22XLTS U3869 ( .A0(n4498), .A1(intadd_375_SUM_0_), .B0(n4525), .B1(
d_ff3_sh_x_out[53]), .Y(n2781) );
INVX4TS U3870 ( .A(n4421), .Y(n4521) );
NAND3XLTS U3871 ( .A(n4354), .B(n4495), .C(n4394), .Y(n3047) );
OA21XLTS U3872 ( .A0(n4488), .A1(d_ff3_LUT_out[41]), .B0(n3047), .Y(n2836)
);
INVX2TS U3873 ( .A(n4323), .Y(n4318) );
INVX2TS U3874 ( .A(n4462), .Y(n4482) );
NOR2XLTS U3875 ( .A(add_subt_module_sign_final_result), .B(underflow_flag),
.Y(n3030) );
INVX2TS U3876 ( .A(n4300), .Y(n3031) );
BUFX3TS U3877 ( .A(n4502), .Y(n4422) );
OA22X1TS U3878 ( .A0(n3001), .A1(d_ff2_X[7]), .B0(d_ff_Xn[7]), .B1(n4422),
.Y(n2683) );
BUFX4TS U3879 ( .A(n3001), .Y(n4425) );
OA22X1TS U3880 ( .A0(n4425), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n4422),
.Y(n2727) );
OA22X1TS U3881 ( .A0(n4425), .A1(d_ff2_X[26]), .B0(d_ff_Xn[26]), .B1(n4422),
.Y(n2721) );
OA22X1TS U3882 ( .A0(n4503), .A1(d_ff2_X[13]), .B0(d_ff_Xn[13]), .B1(n4422),
.Y(n2695) );
OA22X1TS U3883 ( .A0(n4503), .A1(d_ff2_X[9]), .B0(d_ff_Xn[9]), .B1(n4422),
.Y(n2687) );
OA22X1TS U3884 ( .A0(n4503), .A1(d_ff2_X[19]), .B0(d_ff_Xn[19]), .B1(n4422),
.Y(n2707) );
OA22X1TS U3885 ( .A0(n4503), .A1(d_ff2_X[11]), .B0(d_ff_Xn[11]), .B1(n4422),
.Y(n2691) );
OA22X1TS U3886 ( .A0(n4503), .A1(d_ff2_X[8]), .B0(d_ff_Xn[8]), .B1(n4422),
.Y(n2685) );
OA22X1TS U3887 ( .A0(n3001), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n4422),
.Y(n2717) );
OA22X1TS U3888 ( .A0(n4425), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n4422),
.Y(n2725) );
INVX2TS U3889 ( .A(n4352), .Y(n4331) );
BUFX4TS U3890 ( .A(n4525), .Y(n4507) );
INVX2TS U3891 ( .A(n4380), .Y(n4378) );
OAI21XLTS U3892 ( .A0(n4379), .A1(n4378), .B0(n4394), .Y(n3032) );
NOR3X1TS U3893 ( .A(n4331), .B(n4507), .C(n3032), .Y(n4357) );
AOI21X1TS U3894 ( .A0(n4495), .A1(cont_iter_out[0]), .B0(n4357), .Y(n3034)
);
OA22X1TS U3895 ( .A0(n4510), .A1(d_ff3_LUT_out[0]), .B0(n3034), .B1(n3033),
.Y(n2795) );
OA22X1TS U3896 ( .A0(d_ff_Xn[59]), .A1(n4422), .B0(d_ff2_X[59]), .B1(n4425),
.Y(n2790) );
NOR2XLTS U3897 ( .A(n4336), .B(n3035), .Y(n3036) );
NAND2X1TS U3898 ( .A(n4377), .B(n4371), .Y(n4353) );
OA22X1TS U3899 ( .A0(n4510), .A1(d_ff3_LUT_out[25]), .B0(n3036), .B1(n4353),
.Y(n2820) );
OA22X1TS U3900 ( .A0(n4425), .A1(d_ff2_X[49]), .B0(d_ff_Xn[49]), .B1(n2955),
.Y(n2767) );
OA22X1TS U3901 ( .A0(n4425), .A1(d_ff2_X[53]), .B0(d_ff_Xn[53]), .B1(n2955),
.Y(n2784) );
BUFX4TS U3902 ( .A(n3037), .Y(n4701) );
BUFX4TS U3903 ( .A(n4701), .Y(n4782) );
AOI22X1TS U3904 ( .A0(add_subt_module_intDY[34]), .A1(n4793), .B0(n4782),
.B1(d_ff3_sh_y_out[34]), .Y(n3039) );
BUFX4TS U3905 ( .A(n4545), .Y(n4797) );
AOI22X1TS U3906 ( .A0(d_ff3_LUT_out[34]), .A1(n4797), .B0(n4805), .B1(
d_ff3_sh_x_out[34]), .Y(n3038) );
NAND2X1TS U3907 ( .A(n3039), .B(n3038), .Y(n1800) );
AOI22X1TS U3908 ( .A0(n2996), .A1(n4799), .B0(n4782), .B1(d_ff3_sh_y_out[30]), .Y(n3042) );
BUFX4TS U3909 ( .A(n4545), .Y(n4783) );
AOI22X1TS U3910 ( .A0(d_ff3_LUT_out[30]), .A1(n4783), .B0(n4773), .B1(
d_ff3_sh_x_out[30]), .Y(n3041) );
NAND2X1TS U3911 ( .A(n3042), .B(n3041), .Y(n1794) );
BUFX4TS U3912 ( .A(n4701), .Y(n4786) );
AOI22X1TS U3913 ( .A0(add_subt_module_intDY[35]), .A1(n4793), .B0(n4786),
.B1(d_ff3_sh_y_out[35]), .Y(n3044) );
AOI22X1TS U3914 ( .A0(d_ff3_LUT_out[35]), .A1(n4783), .B0(n4773), .B1(
d_ff3_sh_x_out[35]), .Y(n3043) );
NAND2X1TS U3915 ( .A(n3044), .B(n3043), .Y(n1791) );
OR2X1TS U3916 ( .A(n4354), .B(n4525), .Y(n4374) );
NOR2X2TS U3917 ( .A(cont_iter_out[0]), .B(n3311), .Y(n4398) );
NAND2X1TS U3918 ( .A(n4398), .B(n4820), .Y(n4362) );
NAND2X1TS U3919 ( .A(n4374), .B(n4362), .Y(n4396) );
NOR2X2TS U3920 ( .A(n4385), .B(n4396), .Y(n4364) );
OAI21X1TS U3921 ( .A0(n4359), .A1(n4887), .B0(n4355), .Y(n3050) );
OR2X1TS U3922 ( .A(n3050), .B(n4374), .Y(n4402) );
OAI31X1TS U3923 ( .A0(n4393), .A1(n4379), .A2(n4358), .B0(n4402), .Y(n3045)
);
OA22X1TS U3924 ( .A0(n4364), .A1(n3045), .B0(n4510), .B1(d_ff3_LUT_out[9]),
.Y(n2804) );
INVX2TS U3925 ( .A(n3046), .Y(n4383) );
AO21X1TS U3926 ( .A0(n4820), .A1(n4383), .B0(n4367), .Y(n4399) );
OAI21X1TS U3927 ( .A0(n4393), .A1(n4399), .B0(n4495), .Y(n3310) );
AOI21X1TS U3928 ( .A0(n3310), .A1(n3047), .B0(n4367), .Y(n4392) );
AOI21X1TS U3929 ( .A0(n4377), .A1(n4887), .B0(n4392), .Y(n3048) );
OA22X1TS U3930 ( .A0(n4510), .A1(d_ff3_LUT_out[5]), .B0(n3049), .B1(n3048),
.Y(n2800) );
AO22XLTS U3931 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[6]), .A1(
n4023), .B0(n4027), .B1(add_subt_module_Add_Subt_result[6]), .Y(n2602)
);
BUFX4TS U3932 ( .A(n4421), .Y(n4426) );
AOI21X1TS U3933 ( .A0(n4495), .A1(cont_iter_out[3]), .B0(n4375), .Y(n4361)
);
OAI2BB1X1TS U3934 ( .A0N(d_ff3_LUT_out[34]), .A1N(n4426), .B0(n4361), .Y(
n2829) );
NOR2XLTS U3935 ( .A(add_subt_module_FSM_selector_B[1]), .B(n4894), .Y(n3051)
);
BUFX3TS U3936 ( .A(n3051), .Y(n3940) );
INVX2TS U3937 ( .A(n3064), .Y(n3062) );
NAND2X2TS U3938 ( .A(n3103), .B(n3064), .Y(n3089) );
NOR2X2TS U3939 ( .A(add_subt_module_FS_Module_state_reg[0]), .B(n4817), .Y(
n4302) );
OA21X2TS U3940 ( .A0(n4302), .A1(n4324), .B0(n4323), .Y(n4017) );
INVX2TS U3941 ( .A(n3088), .Y(n3618) );
NOR2X1TS U3942 ( .A(n3608), .B(n4149), .Y(n3068) );
INVX2TS U3943 ( .A(n3068), .Y(n3549) );
INVX4TS U3944 ( .A(n3549), .Y(n3739) );
AO22X2TS U3945 ( .A0(add_subt_module_LZA_output[5]), .A1(n3940), .B0(
add_subt_module_exp_oper_result[5]), .B1(n3052), .Y(n3063) );
INVX4TS U3946 ( .A(n3063), .Y(n3145) );
OR2X2TS U3947 ( .A(n4884), .B(n4281), .Y(n3546) );
INVX4TS U3948 ( .A(n3546), .Y(n3340) );
OAI2BB1X1TS U3949 ( .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .A1N(
n3060), .B0(n3057), .Y(n3061) );
INVX4TS U3950 ( .A(n3063), .Y(n3601) );
AND2X2TS U3951 ( .A(n3103), .B(n3062), .Y(n3141) );
NAND2X1TS U3952 ( .A(n3601), .B(n3141), .Y(n4014) );
INVX2TS U3953 ( .A(n4014), .Y(n3109) );
AOI22X1TS U3954 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]), .A1(
n3579), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .B1(
n3109), .Y(n3067) );
INVX4TS U3955 ( .A(n2999), .Y(n4011) );
AOI22X1TS U3956 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .B0(
n3325), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(
n3066) );
OAI211X1TS U3957 ( .A0(n3145), .A1(n3352), .B0(n3067), .C0(n3066), .Y(n3341)
);
AOI22X1TS U3958 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[46]),
.B0(n3340), .B1(n3341), .Y(n3070) );
NAND2X1TS U3959 ( .A(n3068), .B(n3542), .Y(n3069) );
OAI211XLTS U3960 ( .A0(n3343), .A1(n3615), .B0(n3070), .C0(n3613), .Y(n2581)
);
AOI22X1TS U3961 ( .A0(n4011), .A1(n2985), .B0(n3325), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(
n3073) );
AOI22X1TS U3962 ( .A0(n3597), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(
n3072) );
OAI211X1TS U3963 ( .A0(n3601), .A1(n3346), .B0(n3073), .C0(n3072), .Y(n3344)
);
AOI22X1TS U3964 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[43]),
.B0(n3340), .B1(n3344), .Y(n3074) );
OAI211XLTS U3965 ( .A0(n3346), .A1(n3615), .B0(n3074), .C0(n3613), .Y(n2578)
);
OAI2BB1X1TS U3966 ( .A0N(n3060), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .B0(
n3057), .Y(n3075) );
INVX4TS U3967 ( .A(n3546), .Y(n3612) );
OAI2BB1X1TS U3968 ( .A0N(n3060), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(
n3057), .Y(n3076) );
AOI22X1TS U3969 ( .A0(n3325), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]), .Y(
n3078) );
AOI22X1TS U3970 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(
n3077) );
OAI211X1TS U3971 ( .A0(n3601), .A1(n3363), .B0(n3078), .C0(n3077), .Y(n3347)
);
AOI22X1TS U3972 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[41]),
.B0(n3612), .B1(n3347), .Y(n3079) );
AOI22X1TS U3973 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]), .Y(
n3081) );
AOI22X1TS U3974 ( .A0(n3325), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(
n3080) );
OAI211X1TS U3975 ( .A0(n3601), .A1(n3343), .B0(n3081), .C0(n3080), .Y(n3350)
);
AOI22X1TS U3976 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[40]),
.B0(n3612), .B1(n3350), .Y(n3082) );
OAI211XLTS U3977 ( .A0(n3352), .A1(n3615), .B0(n3082), .C0(n3613), .Y(n2575)
);
OAI2BB1X1TS U3978 ( .A0N(n3060), .A1N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(
n3057), .Y(n3083) );
AOI22X1TS U3979 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]), .Y(
n3086) );
BUFX4TS U3980 ( .A(n3325), .Y(n4010) );
AOI22X1TS U3981 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(
n3085) );
OAI211X1TS U3982 ( .A0(n3601), .A1(n3360), .B0(n3086), .C0(n3085), .Y(n3353)
);
AOI22X1TS U3983 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[42]),
.B0(n3340), .B1(n3353), .Y(n3087) );
OAI211XLTS U3984 ( .A0(n3355), .A1(n3615), .B0(n3087), .C0(n3613), .Y(n2577)
);
AOI22X1TS U3985 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[62]), .Y(
n3092) );
AOI22X1TS U3986 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(
n3091) );
OAI211X1TS U3987 ( .A0(n3145), .A1(n3373), .B0(n3092), .C0(n3091), .Y(n3356)
);
AOI22X1TS U3988 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[47]),
.B0(n3340), .B1(n3356), .Y(n3093) );
OAI211XLTS U3989 ( .A0(n2990), .A1(n3615), .B0(n3093), .C0(n3613), .Y(n2582)
);
AOI22X1TS U3990 ( .A0(n3325), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(
n3095) );
AOI22X1TS U3991 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]), .Y(
n3094) );
OAI211X1TS U3992 ( .A0(n3145), .A1(n3355), .B0(n3095), .C0(n3094), .Y(n3358)
);
AOI22X1TS U3993 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[44]),
.B0(n3340), .B1(n3358), .Y(n3096) );
OAI211XLTS U3994 ( .A0(n3360), .A1(n3615), .B0(n3096), .C0(n3613), .Y(n2579)
);
AOI22X1TS U3995 ( .A0(n4011), .A1(n2986), .B0(n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(
n3098) );
AOI22X1TS U3996 ( .A0(n3325), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]), .Y(
n3097) );
OAI211X1TS U3997 ( .A0(n3145), .A1(n3349), .B0(n3098), .C0(n3097), .Y(n3361)
);
AOI22X1TS U3998 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[45]),
.B0(n3340), .B1(n3361), .Y(n3099) );
OAI211XLTS U3999 ( .A0(n3363), .A1(n3615), .B0(n3099), .C0(n3613), .Y(n2580)
);
AO22XLTS U4000 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[9]), .A1(
n4023), .B0(n4028), .B1(add_subt_module_Add_Subt_result[9]), .Y(n2605)
);
INVX4TS U4001 ( .A(n2999), .Y(n3598) );
AOI22X1TS U4002 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(
n4010), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(
n3101) );
AOI22X1TS U4003 ( .A0(n3597), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(
n3100) );
OAI211X1TS U4004 ( .A0(n3601), .A1(n2990), .B0(n3101), .C0(n3100), .Y(n3371)
);
AOI22X1TS U4005 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[39]),
.B0(n3612), .B1(n3371), .Y(n3102) );
OAI211XLTS U4006 ( .A0(n3373), .A1(n3615), .B0(n3102), .C0(n3613), .Y(n2574)
);
AOI22X1TS U4007 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .B0(
n3109), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(
n3106) );
AOI22X1TS U4008 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(
n3597), .B1(n2986), .Y(n3105) );
OAI211X1TS U4009 ( .A0(n3601), .A1(n2972), .B0(n3106), .C0(n3105), .Y(n3576)
);
AOI22X1TS U4010 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[37]),
.B0(n3612), .B1(n3576), .Y(n3107) );
OAI211XLTS U4011 ( .A0(n3578), .A1(n3615), .B0(n3107), .C0(n3613), .Y(n2572)
);
AOI22X1TS U4012 ( .A0(n3597), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(
n3109), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(
n3111) );
AOI22X1TS U4013 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n4010), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(
n3110) );
OAI211X1TS U4014 ( .A0(n3601), .A1(n2977), .B0(n3111), .C0(n3110), .Y(n3590)
);
AOI22X1TS U4015 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[33]),
.B0(n3612), .B1(n3590), .Y(n3112) );
AO22XLTS U4016 ( .A0(n3141), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(
n3053), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(
n3113) );
AOI22X1TS U4017 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[96]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(
n3115) );
AOI22X1TS U4018 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(
n3597), .B1(n2985), .Y(n3114) );
OAI211X1TS U4019 ( .A0(n3601), .A1(n2975), .B0(n3115), .C0(n3114), .Y(n3593)
);
AOI22X1TS U4020 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[35]),
.B0(n3612), .B1(n3593), .Y(n3116) );
OAI211XLTS U4021 ( .A0(n3595), .A1(n3615), .B0(n3116), .C0(n3613), .Y(n2570)
);
AOI22X1TS U4022 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(
n3119) );
AOI22X1TS U4023 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(
n3118) );
OAI211X1TS U4024 ( .A0(n3601), .A1(n2976), .B0(n3119), .C0(n3118), .Y(n3587)
);
AOI22X1TS U4025 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[34]),
.B0(n3612), .B1(n3587), .Y(n3120) );
OAI211XLTS U4026 ( .A0(n3589), .A1(n3615), .B0(n3120), .C0(n3613), .Y(n2569)
);
AOI22X1TS U4027 ( .A0(n3597), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[55]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(
n3123) );
AOI22X1TS U4028 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(
n4010), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(
n3122) );
OAI211X1TS U4029 ( .A0(n3145), .A1(n3616), .B0(n3123), .C0(n3122), .Y(n3738)
);
AOI22X1TS U4030 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[54]),
.B0(n3340), .B1(n3738), .Y(n3124) );
OAI211XLTS U4031 ( .A0(n2988), .A1(n3615), .B0(n3124), .C0(n3613), .Y(n2937)
);
AOI22X1TS U4032 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[60]), .Y(
n3126) );
AOI22X1TS U4033 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(
n3125) );
OAI211X1TS U4034 ( .A0(n3145), .A1(n3578), .B0(n3126), .C0(n3125), .Y(n3726)
);
AOI22X1TS U4035 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[49]),
.B0(n3340), .B1(n3726), .Y(n3127) );
OAI211XLTS U4036 ( .A0(n2972), .A1(n3615), .B0(n3127), .C0(n3613), .Y(n2584)
);
AO22XLTS U4037 ( .A0(n3141), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n3053), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(
n3128) );
AOI22X1TS U4038 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[59]), .Y(
n3130) );
AOI22X1TS U4039 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(
n3129) );
OAI211X1TS U4040 ( .A0(n3145), .A1(n3606), .B0(n3130), .C0(n3129), .Y(n3730)
);
AOI22X1TS U4041 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[50]),
.B0(n3340), .B1(n3730), .Y(n3131) );
OAI211XLTS U4042 ( .A0(n2979), .A1(n3615), .B0(n3131), .C0(n3613), .Y(n2585)
);
AOI22X1TS U4043 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(
n3325), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(
n3133) );
AOI22X1TS U4044 ( .A0(n3579), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(
n3596), .B1(n2986), .Y(n3132) );
OAI211X1TS U4045 ( .A0(n3145), .A1(n3592), .B0(n3133), .C0(n3132), .Y(n3736)
);
AOI22X1TS U4046 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[53]),
.B0(n3340), .B1(n3736), .Y(n3134) );
OAI211XLTS U4047 ( .A0(n2977), .A1(n3615), .B0(n3134), .C0(n3613), .Y(n2588)
);
AOI22X1TS U4048 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[57]), .Y(
n3136) );
AOI22X1TS U4049 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(
n3135) );
OAI211X1TS U4050 ( .A0(n3145), .A1(n3589), .B0(n3136), .C0(n3135), .Y(n3734)
);
AOI22X1TS U4051 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[52]),
.B0(n3340), .B1(n3734), .Y(n3137) );
OAI211XLTS U4052 ( .A0(n2976), .A1(n3615), .B0(n3137), .C0(n3613), .Y(n2587)
);
AOI22X1TS U4053 ( .A0(n3597), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[58]), .B0(
n3596), .B1(n2985), .Y(n3139) );
AOI22X1TS U4054 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(
n3325), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(
n3138) );
OAI211X1TS U4055 ( .A0(n3145), .A1(n3595), .B0(n3139), .C0(n3138), .Y(n3732)
);
AOI22X1TS U4056 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[51]),
.B0(n3340), .B1(n3732), .Y(n3140) );
OAI211XLTS U4057 ( .A0(n2975), .A1(n3615), .B0(n3140), .C0(n3613), .Y(n2586)
);
AO22XLTS U4058 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .A1(
n3141), .B0(n3053), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(
n3142) );
AOI22X1TS U4059 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(
n3144) );
AOI22X1TS U4060 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[61]), .Y(
n3143) );
OAI211X1TS U4061 ( .A0(n3145), .A1(n3610), .B0(n3144), .C0(n3143), .Y(n3728)
);
AOI22X1TS U4062 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[48]),
.B0(n3340), .B1(n3728), .Y(n3146) );
OAI211XLTS U4063 ( .A0(n2989), .A1(n3615), .B0(n3146), .C0(n3613), .Y(n2583)
);
INVX4TS U4064 ( .A(n3016), .Y(n5150) );
INVX4TS U4065 ( .A(n3019), .Y(n5115) );
INVX4TS U4066 ( .A(n2960), .Y(n5155) );
INVX4TS U4067 ( .A(n3002), .Y(n5139) );
NAND2X1TS U4068 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n4297) );
INVX2TS U4069 ( .A(n4297), .Y(n4348) );
NAND3X1TS U4070 ( .A(n4944), .B(cordic_FSM_state_reg[3]), .C(n4348), .Y(
n3147) );
BUFX4TS U4071 ( .A(n3152), .Y(n3219) );
BUFX4TS U4072 ( .A(n3147), .Y(n3215) );
AOI22X1TS U4073 ( .A0(d_ff_Xn[57]), .A1(n3149), .B0(sign_inv_out[57]), .B1(
n3221), .Y(n3148) );
OAI21XLTS U4074 ( .A0(n2980), .A1(n3219), .B0(n3148), .Y(n1975) );
BUFX4TS U4075 ( .A(n3152), .Y(n3205) );
AOI22X1TS U4076 ( .A0(d_ff_Xn[60]), .A1(n3149), .B0(sign_inv_out[60]), .B1(
n3206), .Y(n3150) );
OAI21XLTS U4077 ( .A0(n2982), .A1(n3205), .B0(n3150), .Y(n1969) );
AOI22X1TS U4078 ( .A0(d_ff_Xn[58]), .A1(n3149), .B0(sign_inv_out[58]), .B1(
n3217), .Y(n3151) );
OAI21XLTS U4079 ( .A0(n2981), .A1(n3219), .B0(n3151), .Y(n1973) );
AOI22X1TS U4080 ( .A0(d_ff_Xn[40]), .A1(n3149), .B0(sign_inv_out[40]), .B1(
n3217), .Y(n3153) );
OAI21XLTS U4081 ( .A0(n5050), .A1(n3152), .B0(n3153), .Y(n2009) );
OAI21X1TS U4082 ( .A0(d_ff2_Y[56]), .A1(intadd_374_n1), .B0(n4495), .Y(n4508) );
AOI22X1TS U4083 ( .A0(n4523), .A1(n4512), .B0(d_ff3_sh_y_out[57]), .B1(n4507), .Y(n3154) );
OAI21XLTS U4084 ( .A0(n5008), .A1(n4508), .B0(n3154), .Y(n2098) );
AOI22X1TS U4085 ( .A0(d_ff_Xn[63]), .A1(n3179), .B0(data_output2_63_), .B1(
n3221), .Y(n3155) );
OAI21XLTS U4086 ( .A0(n5072), .A1(n3205), .B0(n3155), .Y(n1963) );
AOI22X1TS U4087 ( .A0(d_ff_Xn[49]), .A1(n3179), .B0(sign_inv_out[49]), .B1(
n3206), .Y(n3156) );
OAI21XLTS U4088 ( .A0(n5059), .A1(n3219), .B0(n3156), .Y(n1991) );
AOI22X1TS U4089 ( .A0(d_ff_Xn[43]), .A1(n3179), .B0(sign_inv_out[43]), .B1(
n3217), .Y(n3157) );
OAI21XLTS U4090 ( .A0(n5053), .A1(n3152), .B0(n3157), .Y(n2003) );
AOI22X1TS U4091 ( .A0(d_ff_Xn[39]), .A1(n3179), .B0(sign_inv_out[39]), .B1(
n3221), .Y(n3158) );
OAI21XLTS U4092 ( .A0(n5049), .A1(n3152), .B0(n3158), .Y(n2011) );
AOI22X1TS U4093 ( .A0(d_ff_Xn[8]), .A1(n3179), .B0(sign_inv_out[8]), .B1(
n3215), .Y(n3159) );
OAI21XLTS U4094 ( .A0(n5019), .A1(n3205), .B0(n3159), .Y(n2073) );
AOI22X1TS U4095 ( .A0(d_ff_Xn[1]), .A1(n3179), .B0(sign_inv_out[1]), .B1(
n3217), .Y(n3160) );
OAI21XLTS U4096 ( .A0(n5012), .A1(n3205), .B0(n3160), .Y(n2087) );
AOI22X1TS U4097 ( .A0(d_ff_Xn[11]), .A1(n3179), .B0(sign_inv_out[11]), .B1(
n3215), .Y(n3161) );
OAI21XLTS U4098 ( .A0(n5022), .A1(n3205), .B0(n3161), .Y(n2067) );
AOI22X1TS U4099 ( .A0(d_ff_Xn[4]), .A1(n3179), .B0(sign_inv_out[4]), .B1(
n3215), .Y(n3162) );
OAI21XLTS U4100 ( .A0(n5015), .A1(n3205), .B0(n3162), .Y(n2081) );
AOI22X1TS U4101 ( .A0(d_ff_Xn[12]), .A1(n3179), .B0(sign_inv_out[12]), .B1(
n3215), .Y(n3163) );
OAI21XLTS U4102 ( .A0(n5023), .A1(n3205), .B0(n3163), .Y(n2065) );
AOI22X1TS U4103 ( .A0(d_ff_Xn[3]), .A1(n3179), .B0(sign_inv_out[3]), .B1(
n3221), .Y(n3164) );
OAI21XLTS U4104 ( .A0(n5014), .A1(n3205), .B0(n3164), .Y(n2083) );
AOI22X1TS U4105 ( .A0(d_ff_Xn[48]), .A1(n3179), .B0(sign_inv_out[48]), .B1(
n3217), .Y(n3165) );
OAI21XLTS U4106 ( .A0(n5058), .A1(n3219), .B0(n3165), .Y(n1993) );
AOI22X1TS U4107 ( .A0(d_ff_Xn[46]), .A1(n3179), .B0(sign_inv_out[46]), .B1(
n3217), .Y(n3166) );
OAI21XLTS U4108 ( .A0(n5056), .A1(n3152), .B0(n3166), .Y(n1997) );
AOI22X1TS U4109 ( .A0(d_ff_Xn[9]), .A1(n3179), .B0(sign_inv_out[9]), .B1(
n3215), .Y(n3167) );
OAI21XLTS U4110 ( .A0(n5020), .A1(n3205), .B0(n3167), .Y(n2071) );
AOI22X1TS U4111 ( .A0(d_ff_Xn[2]), .A1(n3179), .B0(sign_inv_out[2]), .B1(
n3206), .Y(n3168) );
OAI21XLTS U4112 ( .A0(n5013), .A1(n3205), .B0(n3168), .Y(n2085) );
AOI22X1TS U4113 ( .A0(d_ff_Xn[62]), .A1(n3179), .B0(sign_inv_out[62]), .B1(
n3206), .Y(n3169) );
OAI21XLTS U4114 ( .A0(n5068), .A1(n3205), .B0(n3169), .Y(n1965) );
AOI22X1TS U4115 ( .A0(d_ff_Xn[53]), .A1(n3179), .B0(sign_inv_out[53]), .B1(
n3221), .Y(n3170) );
OAI21XLTS U4116 ( .A0(n5062), .A1(n3219), .B0(n3170), .Y(n1983) );
AOI22X1TS U4117 ( .A0(d_ff_Xn[6]), .A1(n3179), .B0(sign_inv_out[6]), .B1(
n3215), .Y(n3171) );
OAI21XLTS U4118 ( .A0(n5017), .A1(n3205), .B0(n3171), .Y(n2077) );
AOI22X1TS U4119 ( .A0(d_ff_Xn[45]), .A1(n3179), .B0(sign_inv_out[45]), .B1(
n3206), .Y(n3172) );
OAI21XLTS U4120 ( .A0(n5055), .A1(n3152), .B0(n3172), .Y(n1999) );
AOI22X1TS U4121 ( .A0(d_ff_Xn[41]), .A1(n3179), .B0(sign_inv_out[41]), .B1(
n3217), .Y(n3173) );
OAI21XLTS U4122 ( .A0(n5051), .A1(n3152), .B0(n3173), .Y(n2007) );
AOI22X1TS U4123 ( .A0(d_ff_Xn[7]), .A1(n3179), .B0(sign_inv_out[7]), .B1(
n3215), .Y(n3174) );
OAI21XLTS U4124 ( .A0(n5018), .A1(n3205), .B0(n3174), .Y(n2075) );
AOI22X1TS U4125 ( .A0(d_ff_Xn[0]), .A1(n3179), .B0(sign_inv_out[0]), .B1(
n3206), .Y(n3175) );
OAI21XLTS U4126 ( .A0(n5011), .A1(n3205), .B0(n3175), .Y(n2089) );
AOI22X1TS U4127 ( .A0(d_ff_Xn[42]), .A1(n3179), .B0(sign_inv_out[42]), .B1(
n3217), .Y(n3176) );
OAI21XLTS U4128 ( .A0(n5052), .A1(n3152), .B0(n3176), .Y(n2005) );
AOI22X1TS U4129 ( .A0(d_ff_Xn[55]), .A1(n3179), .B0(sign_inv_out[55]), .B1(
n3221), .Y(n3177) );
OAI21XLTS U4130 ( .A0(n5064), .A1(n3219), .B0(n3177), .Y(n1979) );
AOI22X1TS U4131 ( .A0(d_ff_Xn[5]), .A1(n3179), .B0(sign_inv_out[5]), .B1(
n3215), .Y(n3178) );
OAI21XLTS U4132 ( .A0(n5016), .A1(n3205), .B0(n3178), .Y(n2079) );
AOI22X1TS U4133 ( .A0(d_ff_Xn[10]), .A1(n3179), .B0(sign_inv_out[10]), .B1(
n3215), .Y(n3180) );
OAI21XLTS U4134 ( .A0(n5021), .A1(n3205), .B0(n3180), .Y(n2069) );
BUFX4TS U4135 ( .A(n3149), .Y(n3197) );
AOI22X1TS U4136 ( .A0(d_ff_Xn[47]), .A1(n3197), .B0(sign_inv_out[47]), .B1(
n3217), .Y(n3181) );
OAI21XLTS U4137 ( .A0(n5057), .A1(n3152), .B0(n3181), .Y(n1995) );
AOI22X1TS U4138 ( .A0(d_ff_Xn[36]), .A1(n3197), .B0(sign_inv_out[36]), .B1(
n3206), .Y(n3182) );
OAI21XLTS U4139 ( .A0(n5046), .A1(n3152), .B0(n3182), .Y(n2017) );
BUFX3TS U4140 ( .A(n3205), .Y(n3224) );
AOI22X1TS U4141 ( .A0(d_ff_Xn[26]), .A1(n3197), .B0(sign_inv_out[26]), .B1(
n3206), .Y(n3183) );
OAI21XLTS U4142 ( .A0(n5036), .A1(n3224), .B0(n3183), .Y(n2037) );
AOI22X1TS U4143 ( .A0(d_ff_Xn[56]), .A1(n3197), .B0(sign_inv_out[56]), .B1(
n3221), .Y(n3184) );
OAI21XLTS U4144 ( .A0(n5065), .A1(n3219), .B0(n3184), .Y(n1977) );
AOI22X1TS U4145 ( .A0(d_ff_Xn[37]), .A1(n3197), .B0(sign_inv_out[37]), .B1(
n3206), .Y(n3185) );
OAI21XLTS U4146 ( .A0(n5047), .A1(n3152), .B0(n3185), .Y(n2015) );
AOI22X1TS U4147 ( .A0(d_ff_Xn[31]), .A1(n3197), .B0(sign_inv_out[31]), .B1(
n3217), .Y(n3186) );
OAI21XLTS U4148 ( .A0(n5041), .A1(n3224), .B0(n3186), .Y(n2027) );
AOI22X1TS U4149 ( .A0(d_ff_Xn[59]), .A1(n3197), .B0(sign_inv_out[59]), .B1(
n3221), .Y(n3187) );
OAI21XLTS U4150 ( .A0(n5066), .A1(n3219), .B0(n3187), .Y(n1971) );
AOI22X1TS U4151 ( .A0(d_ff_Xn[38]), .A1(n3197), .B0(sign_inv_out[38]), .B1(
n3221), .Y(n3188) );
OAI21XLTS U4152 ( .A0(n5048), .A1(n3152), .B0(n3188), .Y(n2013) );
AOI22X1TS U4153 ( .A0(d_ff_Xn[52]), .A1(n3197), .B0(sign_inv_out[52]), .B1(
n3217), .Y(n3189) );
OAI21XLTS U4154 ( .A0(n5070), .A1(n3219), .B0(n3189), .Y(n1985) );
AOI22X1TS U4155 ( .A0(d_ff_Xn[35]), .A1(n3197), .B0(sign_inv_out[35]), .B1(
n3215), .Y(n3190) );
OAI21XLTS U4156 ( .A0(n5045), .A1(n3224), .B0(n3190), .Y(n2019) );
AOI22X1TS U4157 ( .A0(d_ff_Xn[29]), .A1(n3197), .B0(sign_inv_out[29]), .B1(
n3217), .Y(n3191) );
OAI21XLTS U4158 ( .A0(n5039), .A1(n3224), .B0(n3191), .Y(n2031) );
AOI22X1TS U4159 ( .A0(d_ff_Xn[33]), .A1(n3197), .B0(sign_inv_out[33]), .B1(
n3217), .Y(n3192) );
OAI21XLTS U4160 ( .A0(n5043), .A1(n3224), .B0(n3192), .Y(n2023) );
AOI22X1TS U4161 ( .A0(d_ff_Xn[30]), .A1(n3197), .B0(sign_inv_out[30]), .B1(
n3206), .Y(n3193) );
OAI21XLTS U4162 ( .A0(n5040), .A1(n3224), .B0(n3193), .Y(n2029) );
AOI22X1TS U4163 ( .A0(d_ff_Xn[28]), .A1(n3197), .B0(sign_inv_out[28]), .B1(
n3206), .Y(n3194) );
OAI21XLTS U4164 ( .A0(n5038), .A1(n3224), .B0(n3194), .Y(n2033) );
AOI22X1TS U4165 ( .A0(d_ff_Xn[32]), .A1(n3197), .B0(sign_inv_out[32]), .B1(
n3215), .Y(n3195) );
OAI21XLTS U4166 ( .A0(n5042), .A1(n3224), .B0(n3195), .Y(n2025) );
AOI22X1TS U4167 ( .A0(d_ff_Xn[27]), .A1(n3197), .B0(sign_inv_out[27]), .B1(
n3217), .Y(n3196) );
OAI21XLTS U4168 ( .A0(n5037), .A1(n3224), .B0(n3196), .Y(n2035) );
AOI22X1TS U4169 ( .A0(d_ff_Xn[34]), .A1(n3197), .B0(sign_inv_out[34]), .B1(
n3215), .Y(n3198) );
OAI21XLTS U4170 ( .A0(n5044), .A1(n3224), .B0(n3198), .Y(n2021) );
BUFX4TS U4171 ( .A(n3149), .Y(n3222) );
AOI22X1TS U4172 ( .A0(d_ff_Xn[18]), .A1(n3222), .B0(sign_inv_out[18]), .B1(
n3221), .Y(n3199) );
OAI21XLTS U4173 ( .A0(n5029), .A1(n3219), .B0(n3199), .Y(n2053) );
AOI22X1TS U4174 ( .A0(d_ff_Xn[51]), .A1(n3222), .B0(sign_inv_out[51]), .B1(
n3206), .Y(n3200) );
OAI21XLTS U4175 ( .A0(n5061), .A1(n3219), .B0(n3200), .Y(n1987) );
AOI22X1TS U4176 ( .A0(d_ff_Xn[20]), .A1(n3222), .B0(sign_inv_out[20]), .B1(
n3221), .Y(n3201) );
OAI21XLTS U4177 ( .A0(n5031), .A1(n3219), .B0(n3201), .Y(n2049) );
AOI22X1TS U4178 ( .A0(d_ff_Xn[17]), .A1(n3222), .B0(sign_inv_out[17]), .B1(
n3221), .Y(n3202) );
OAI21XLTS U4179 ( .A0(n5028), .A1(n3152), .B0(n3202), .Y(n2055) );
AOI22X1TS U4180 ( .A0(d_ff_Xn[21]), .A1(n3222), .B0(sign_inv_out[21]), .B1(
n3217), .Y(n3203) );
OAI21XLTS U4181 ( .A0(n5032), .A1(n3152), .B0(n3203), .Y(n2047) );
AOI22X1TS U4182 ( .A0(d_ff_Xn[61]), .A1(n3222), .B0(sign_inv_out[61]), .B1(
n3221), .Y(n3204) );
OAI21XLTS U4183 ( .A0(n5067), .A1(n3205), .B0(n3204), .Y(n1967) );
AOI22X1TS U4184 ( .A0(d_ff_Xn[54]), .A1(n3222), .B0(sign_inv_out[54]), .B1(
n3221), .Y(n3207) );
OAI21XLTS U4185 ( .A0(n5063), .A1(n3219), .B0(n3207), .Y(n1981) );
AOI22X1TS U4186 ( .A0(d_ff_Xn[44]), .A1(n3222), .B0(sign_inv_out[44]), .B1(
n3217), .Y(n3208) );
OAI21XLTS U4187 ( .A0(n5054), .A1(n3152), .B0(n3208), .Y(n2001) );
AOI22X1TS U4188 ( .A0(d_ff_Xn[13]), .A1(n3222), .B0(sign_inv_out[13]), .B1(
n3215), .Y(n3209) );
OAI21XLTS U4189 ( .A0(n5024), .A1(n3224), .B0(n3209), .Y(n2063) );
AOI22X1TS U4190 ( .A0(d_ff_Xn[25]), .A1(n3222), .B0(sign_inv_out[25]), .B1(
n3217), .Y(n3210) );
OAI21XLTS U4191 ( .A0(n5071), .A1(n3224), .B0(n3210), .Y(n2039) );
AOI22X1TS U4192 ( .A0(d_ff_Xn[19]), .A1(n3222), .B0(sign_inv_out[19]), .B1(
n3217), .Y(n3211) );
OAI21XLTS U4193 ( .A0(n5030), .A1(n3152), .B0(n3211), .Y(n2051) );
AOI22X1TS U4194 ( .A0(d_ff_Xn[14]), .A1(n3222), .B0(sign_inv_out[14]), .B1(
n3215), .Y(n3212) );
OAI21XLTS U4195 ( .A0(n5025), .A1(n3219), .B0(n3212), .Y(n2061) );
AOI22X1TS U4196 ( .A0(d_ff_Xn[16]), .A1(n3222), .B0(sign_inv_out[16]), .B1(
n3217), .Y(n3213) );
OAI21XLTS U4197 ( .A0(n5027), .A1(n3219), .B0(n3213), .Y(n2057) );
AOI22X1TS U4198 ( .A0(d_ff_Xn[22]), .A1(n3222), .B0(sign_inv_out[22]), .B1(
n3206), .Y(n3214) );
OAI21XLTS U4199 ( .A0(n5033), .A1(n3219), .B0(n3214), .Y(n2045) );
AOI22X1TS U4200 ( .A0(d_ff_Xn[15]), .A1(n3222), .B0(sign_inv_out[15]), .B1(
n3215), .Y(n3216) );
OAI21XLTS U4201 ( .A0(n5026), .A1(n3152), .B0(n3216), .Y(n2059) );
AOI22X1TS U4202 ( .A0(d_ff_Xn[50]), .A1(n3222), .B0(sign_inv_out[50]), .B1(
n3217), .Y(n3218) );
OAI21XLTS U4203 ( .A0(n5060), .A1(n3219), .B0(n3218), .Y(n1989) );
AOI22X1TS U4204 ( .A0(d_ff_Xn[23]), .A1(n3222), .B0(sign_inv_out[23]), .B1(
n3206), .Y(n3220) );
OAI21XLTS U4205 ( .A0(n5034), .A1(n3152), .B0(n3220), .Y(n2043) );
AOI22X1TS U4206 ( .A0(d_ff_Xn[24]), .A1(n3222), .B0(sign_inv_out[24]), .B1(
n3217), .Y(n3223) );
OAI21XLTS U4207 ( .A0(n5035), .A1(n3224), .B0(n3223), .Y(n2041) );
NAND2X1TS U4208 ( .A(cont_iter_out[0]), .B(n4937), .Y(intadd_375_CI) );
INVX1TS U4209 ( .A(d_ff2_Y[52]), .Y(n4504) );
NAND2X1TS U4210 ( .A(cont_iter_out[0]), .B(n4504), .Y(intadd_374_CI) );
AOI21X1TS U4211 ( .A0(n4808), .A1(n3233), .B0(n4820), .Y(n3226) );
AOI21X1TS U4212 ( .A0(d_ff3_LUT_out[3]), .A1(n4507), .B0(n4398), .Y(n3225)
);
OAI31X1TS U4213 ( .A0(n4359), .A1(n3226), .A2(n4421), .B0(n3225), .Y(n2798)
);
INVX2TS U4214 ( .A(n3311), .Y(n4390) );
OAI21X1TS U4215 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[1]), .B0(n4390),
.Y(n4372) );
OAI211XLTS U4216 ( .A0(n4523), .A1(n5078), .B0(n4372), .C0(n4402), .Y(n2814)
);
INVX4TS U4217 ( .A(n3001), .Y(n4491) );
NOR2XLTS U4218 ( .A(sel_mux_1_reg), .B(n3308), .Y(n3227) );
BUFX4TS U4219 ( .A(n3227), .Y(n3258) );
INVX2TS U4220 ( .A(n3228), .Y(n2275) );
INVX2TS U4221 ( .A(n3229), .Y(n2278) );
INVX2TS U4222 ( .A(n3230), .Y(n2224) );
INVX2TS U4223 ( .A(n3231), .Y(n2226) );
INVX4TS U4224 ( .A(n3001), .Y(n4404) );
INVX2TS U4225 ( .A(n3232), .Y(n2281) );
NAND4X1TS U4226 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n4819), .D(n4944), .Y(n4330) );
INVX2TS U4227 ( .A(n4330), .Y(n4332) );
NAND3BX1TS U4228 ( .AN(n4435), .B(n4968), .C(n4332), .Y(n4307) );
NOR3X2TS U4229 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[0]),
.C(n4819), .Y(n4427) );
NOR2X1TS U4230 ( .A(n3233), .B(n4307), .Y(n4335) );
AOI211XLTS U4231 ( .A0(n3233), .A1(n4307), .B0(n4347), .C0(n4335), .Y(n2923)
);
AOI22X1TS U4232 ( .A0(d_ff3_sh_x_out[62]), .A1(n4696), .B0(
d_ff3_sh_y_out[62]), .B1(n4645), .Y(n3234) );
AOI22X1TS U4233 ( .A0(d_ff3_sh_x_out[60]), .A1(n4677), .B0(
d_ff3_sh_y_out[60]), .B1(n4645), .Y(n3235) );
OAI211XLTS U4234 ( .A0(n3004), .A1(n4840), .B0(n3235), .C0(n3240), .Y(n1955)
);
AOI22X1TS U4235 ( .A0(d_ff3_sh_x_out[61]), .A1(n4798), .B0(
d_ff3_sh_y_out[61]), .B1(n4645), .Y(n3236) );
INVX2TS U4236 ( .A(add_subt_module_intDY[58]), .Y(n3788) );
AOI22X1TS U4237 ( .A0(n4805), .A1(d_ff3_sh_x_out[58]), .B0(n4645), .B1(
d_ff3_sh_y_out[58]), .Y(n3237) );
OAI211XLTS U4238 ( .A0(n3004), .A1(n3788), .B0(n3237), .C0(n3240), .Y(n1953)
);
INVX2TS U4239 ( .A(add_subt_module_intDY[57]), .Y(n3752) );
AOI22X1TS U4240 ( .A0(n4798), .A1(d_ff3_sh_x_out[57]), .B0(n4645), .B1(
d_ff3_sh_y_out[57]), .Y(n3238) );
OAI211XLTS U4241 ( .A0(n3004), .A1(n3752), .B0(n3238), .C0(n3240), .Y(n1952)
);
INVX2TS U4242 ( .A(n3239), .Y(n1946) );
AOI22X1TS U4243 ( .A0(n4696), .A1(d_ff3_sh_x_out[48]), .B0(n4642), .B1(
d_ff3_sh_y_out[48]), .Y(n3241) );
OAI211XLTS U4244 ( .A0(n3004), .A1(n5004), .B0(n3241), .C0(n3240), .Y(n1900)
);
INVX2TS U4245 ( .A(n3242), .Y(n2279) );
INVX2TS U4246 ( .A(n3243), .Y(n2284) );
INVX2TS U4247 ( .A(n3244), .Y(n2273) );
INVX2TS U4248 ( .A(n3245), .Y(n2272) );
INVX2TS U4249 ( .A(n3246), .Y(n2283) );
INVX2TS U4250 ( .A(n3247), .Y(n2276) );
INVX2TS U4251 ( .A(n3248), .Y(n2274) );
INVX2TS U4252 ( .A(n3249), .Y(n2277) );
INVX2TS U4253 ( .A(n3250), .Y(n2280) );
INVX2TS U4254 ( .A(n3251), .Y(n2225) );
INVX2TS U4255 ( .A(n3252), .Y(n2282) );
AOI222X1TS U4256 ( .A0(n3308), .A1(d_ff2_Z[23]), .B0(n3302), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n3301), .Y(n3253) );
INVX2TS U4257 ( .A(n3253), .Y(n2261) );
AOI222X1TS U4258 ( .A0(n3308), .A1(d_ff2_Z[41]), .B0(n3296), .B1(d_ff1_Z[41]), .C0(d_ff_Zn[41]), .C1(n3298), .Y(n3254) );
INVX2TS U4259 ( .A(n3254), .Y(n2243) );
AOI222X1TS U4260 ( .A0(n3308), .A1(d_ff2_Z[49]), .B0(n3302), .B1(d_ff1_Z[49]), .C0(d_ff_Zn[49]), .C1(n4492), .Y(n3255) );
INVX2TS U4261 ( .A(n3255), .Y(n2235) );
INVX2TS U4262 ( .A(n3256), .Y(n2232) );
AOI222X1TS U4263 ( .A0(n3308), .A1(d_ff2_Z[45]), .B0(n3307), .B1(d_ff1_Z[45]), .C0(d_ff_Zn[45]), .C1(n3301), .Y(n3257) );
INVX2TS U4264 ( .A(n3257), .Y(n2239) );
INVX2TS U4265 ( .A(n3259), .Y(n2231) );
AOI222X1TS U4266 ( .A0(n4404), .A1(d_ff2_Z[61]), .B0(n3302), .B1(d_ff1_Z[61]), .C0(d_ff_Zn[61]), .C1(n3304), .Y(n3260) );
INVX2TS U4267 ( .A(n3260), .Y(n2223) );
INVX2TS U4268 ( .A(n3261), .Y(n2258) );
AOI222X1TS U4269 ( .A0(n3308), .A1(d_ff2_Z[32]), .B0(n3307), .B1(d_ff1_Z[32]), .C0(d_ff_Zn[32]), .C1(n3298), .Y(n3262) );
INVX2TS U4270 ( .A(n3262), .Y(n2252) );
INVX2TS U4271 ( .A(n3263), .Y(n2257) );
AOI222X1TS U4272 ( .A0(n3308), .A1(d_ff2_Z[30]), .B0(n3302), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n3304), .Y(n3264) );
INVX2TS U4273 ( .A(n3264), .Y(n2254) );
INVX2TS U4274 ( .A(n3265), .Y(n2222) );
AOI222X1TS U4275 ( .A0(n4491), .A1(d_ff2_Z[33]), .B0(n3307), .B1(d_ff1_Z[33]), .C0(d_ff_Zn[33]), .C1(n3304), .Y(n3266) );
INVX2TS U4276 ( .A(n3266), .Y(n2251) );
INVX2TS U4277 ( .A(n3267), .Y(n2238) );
AOI222X1TS U4278 ( .A0(n3308), .A1(d_ff2_Z[40]), .B0(n3307), .B1(d_ff1_Z[40]), .C0(d_ff_Zn[40]), .C1(n4497), .Y(n3268) );
INVX2TS U4279 ( .A(n3268), .Y(n2244) );
AOI222X1TS U4280 ( .A0(n3308), .A1(d_ff2_Z[54]), .B0(n3307), .B1(d_ff1_Z[54]), .C0(d_ff_Zn[54]), .C1(n3298), .Y(n3269) );
INVX2TS U4281 ( .A(n3269), .Y(n2230) );
INVX2TS U4282 ( .A(n3270), .Y(n2221) );
AOI222X1TS U4283 ( .A0(n3308), .A1(d_ff2_Z[29]), .B0(n3302), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n4492), .Y(n3271) );
INVX2TS U4284 ( .A(n3271), .Y(n2255) );
INVX2TS U4285 ( .A(n3272), .Y(n2248) );
INVX2TS U4286 ( .A(n3273), .Y(n2260) );
AOI222X1TS U4287 ( .A0(n3308), .A1(d_ff2_Z[42]), .B0(n3302), .B1(d_ff1_Z[42]), .C0(d_ff_Zn[42]), .C1(n4492), .Y(n3274) );
INVX2TS U4288 ( .A(n3274), .Y(n2242) );
AOI222X1TS U4289 ( .A0(n3308), .A1(d_ff2_Z[17]), .B0(n3302), .B1(d_ff1_Z[17]), .C0(d_ff_Zn[17]), .C1(n3298), .Y(n3275) );
INVX2TS U4290 ( .A(n3275), .Y(n2267) );
INVX2TS U4291 ( .A(n3276), .Y(n2269) );
INVX2TS U4292 ( .A(n3277), .Y(n2268) );
AOI222X1TS U4293 ( .A0(n3305), .A1(d_ff2_Z[34]), .B0(n3307), .B1(d_ff1_Z[34]), .C0(d_ff_Zn[34]), .C1(n4492), .Y(n3278) );
INVX2TS U4294 ( .A(n3278), .Y(n2250) );
AOI222X1TS U4295 ( .A0(n3308), .A1(d_ff2_Z[39]), .B0(n3307), .B1(d_ff1_Z[39]), .C0(d_ff_Zn[39]), .C1(n3298), .Y(n3279) );
INVX2TS U4296 ( .A(n3279), .Y(n2245) );
AOI222X1TS U4297 ( .A0(n4404), .A1(d_ff2_Z[51]), .B0(n3302), .B1(d_ff1_Z[51]), .C0(d_ff_Zn[51]), .C1(n3304), .Y(n3280) );
INVX2TS U4298 ( .A(n3280), .Y(n2233) );
AOI222X1TS U4299 ( .A0(n4491), .A1(d_ff2_Z[43]), .B0(n3307), .B1(d_ff1_Z[43]), .C0(d_ff_Zn[43]), .C1(n3304), .Y(n3281) );
INVX2TS U4300 ( .A(n3281), .Y(n2241) );
AOI222X1TS U4301 ( .A0(n4404), .A1(d_ff2_Z[35]), .B0(n3302), .B1(d_ff1_Z[35]), .C0(d_ff_Zn[35]), .C1(n3304), .Y(n3282) );
INVX2TS U4302 ( .A(n3282), .Y(n2249) );
AOI222X1TS U4303 ( .A0(n3305), .A1(d_ff2_Z[44]), .B0(n3302), .B1(d_ff1_Z[44]), .C0(d_ff_Zn[44]), .C1(n4528), .Y(n3283) );
INVX2TS U4304 ( .A(n3283), .Y(n2240) );
AOI222X1TS U4305 ( .A0(n3308), .A1(d_ff2_Z[47]), .B0(n3307), .B1(d_ff1_Z[47]), .C0(d_ff_Zn[47]), .C1(n3298), .Y(n3284) );
INVX2TS U4306 ( .A(n3284), .Y(n2237) );
AOI222X1TS U4307 ( .A0(n4491), .A1(d_ff2_Z[57]), .B0(n3302), .B1(d_ff1_Z[57]), .C0(d_ff_Zn[57]), .C1(n3304), .Y(n3285) );
INVX2TS U4308 ( .A(n3285), .Y(n2227) );
AOI222X1TS U4309 ( .A0(n3308), .A1(d_ff2_Z[20]), .B0(n3302), .B1(d_ff1_Z[20]), .C0(d_ff_Zn[20]), .C1(n4492), .Y(n3286) );
INVX2TS U4310 ( .A(n3286), .Y(n2264) );
INVX2TS U4311 ( .A(n3287), .Y(n2266) );
AOI222X1TS U4312 ( .A0(n3308), .A1(d_ff2_Z[31]), .B0(n3307), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n4492), .Y(n3288) );
INVX2TS U4313 ( .A(n3288), .Y(n2253) );
AOI222X1TS U4314 ( .A0(n4404), .A1(d_ff2_Z[19]), .B0(n3307), .B1(d_ff1_Z[19]), .C0(d_ff_Zn[19]), .C1(n3298), .Y(n3289) );
INVX2TS U4315 ( .A(n3289), .Y(n2265) );
AOI222X1TS U4316 ( .A0(n4404), .A1(d_ff2_Z[55]), .B0(n3296), .B1(d_ff1_Z[55]), .C0(d_ff_Zn[55]), .C1(n3304), .Y(n3290) );
INVX2TS U4317 ( .A(n3290), .Y(n2229) );
AOI222X1TS U4318 ( .A0(n3308), .A1(d_ff2_Z[56]), .B0(n3302), .B1(d_ff1_Z[56]), .C0(d_ff_Zn[56]), .C1(n3298), .Y(n3291) );
INVX2TS U4319 ( .A(n3291), .Y(n2228) );
AOI222X1TS U4320 ( .A0(n3305), .A1(d_ff2_Z[25]), .B0(n3302), .B1(d_ff1_Z[25]), .C0(d_ff_Zn[25]), .C1(n4492), .Y(n3292) );
INVX2TS U4321 ( .A(n3292), .Y(n2259) );
AOI222X1TS U4322 ( .A0(n3308), .A1(d_ff2_Z[48]), .B0(n3302), .B1(d_ff1_Z[48]), .C0(d_ff_Zn[48]), .C1(n4497), .Y(n3293) );
INVX2TS U4323 ( .A(n3293), .Y(n2236) );
INVX2TS U4324 ( .A(n3294), .Y(n2263) );
AOI222X1TS U4325 ( .A0(n3308), .A1(d_ff2_Z[38]), .B0(n3307), .B1(d_ff1_Z[38]), .C0(d_ff_Zn[38]), .C1(n4492), .Y(n3295) );
INVX2TS U4326 ( .A(n3295), .Y(n2246) );
AOI222X1TS U4327 ( .A0(n3308), .A1(d_ff2_Z[50]), .B0(n3307), .B1(d_ff1_Z[50]), .C0(d_ff_Zn[50]), .C1(n4487), .Y(n3297) );
INVX2TS U4328 ( .A(n3297), .Y(n2234) );
AOI222X1TS U4329 ( .A0(n3305), .A1(d_ff2_Z[14]), .B0(n3307), .B1(d_ff1_Z[14]), .C0(d_ff_Zn[14]), .C1(n3304), .Y(n3299) );
INVX2TS U4330 ( .A(n3299), .Y(n2270) );
INVX2TS U4331 ( .A(n3300), .Y(n2247) );
AOI222X1TS U4332 ( .A0(n3305), .A1(d_ff2_Z[28]), .B0(n3307), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n3298), .Y(n3303) );
INVX2TS U4333 ( .A(n3303), .Y(n2256) );
AOI222X1TS U4334 ( .A0(n3305), .A1(d_ff2_Z[13]), .B0(n3302), .B1(d_ff1_Z[13]), .C0(d_ff_Zn[13]), .C1(n3298), .Y(n3306) );
INVX2TS U4335 ( .A(n3306), .Y(n2271) );
AOI222X1TS U4336 ( .A0(n3305), .A1(d_ff2_Z[22]), .B0(n3307), .B1(d_ff1_Z[22]), .C0(d_ff_Zn[22]), .C1(n4492), .Y(n3309) );
INVX2TS U4337 ( .A(n3309), .Y(n2262) );
INVX2TS U4338 ( .A(n4359), .Y(n4373) );
OA21XLTS U4339 ( .A0(n3311), .A1(n4373), .B0(n3310), .Y(n4391) );
NAND3XLTS U4340 ( .A(cont_iter_out[1]), .B(cont_iter_out[3]), .C(n4495), .Y(
n4400) );
OAI211XLTS U4341 ( .A0(n4493), .A1(n5077), .B0(n4391), .C0(n4400), .Y(n2828)
);
AOI22X1TS U4342 ( .A0(add_subt_module_LZA_output[2]), .A1(n3940), .B0(n3052),
.B1(add_subt_module_exp_oper_result[2]), .Y(n3314) );
BUFX3TS U4343 ( .A(n4115), .Y(n4152) );
NAND2X1TS U4344 ( .A(n3940), .B(add_subt_module_LZA_output[0]), .Y(n3942) );
INVX2TS U4345 ( .A(n3942), .Y(n3312) );
OAI32X4TS U4346 ( .A0(n3312), .A1(add_subt_module_FSM_selector_B[1]), .A2(
add_subt_module_exp_oper_result[0]), .B0(n4894), .B1(n3312), .Y(n4143)
);
BUFX4TS U4347 ( .A(n4030), .Y(n4271) );
OAI31X4TS U4348 ( .A0(add_subt_module_FS_Module_state_reg[3]), .A1(
add_subt_module_add_overflow_flag), .A2(n4318), .B0(
add_subt_module_FSM_selector_C), .Y(n4280) );
AOI22X1TS U4349 ( .A0(n4271), .A1(n3617), .B0(n3618), .B1(n3313), .Y(n4035)
);
INVX4TS U4350 ( .A(n3314), .Y(n4203) );
NAND2X1TS U4351 ( .A(n3618), .B(n4203), .Y(n3619) );
OAI21XLTS U4352 ( .A0(n4289), .A1(n4035), .B0(n3619), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[54]) );
AOI22X1TS U4353 ( .A0(n3579), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(
n3315) );
INVX2TS U4354 ( .A(n3542), .Y(n4012) );
OAI211XLTS U4355 ( .A0(n2999), .A1(n5006), .B0(n3315), .C0(n4012), .Y(n3316)
);
AOI21X1TS U4356 ( .A0(n3325), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(
n3316), .Y(n3322) );
INVX4TS U4357 ( .A(n3549), .Y(n3602) );
AOI22X1TS U4358 ( .A0(n3597), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(
n3109), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(
n3318) );
AOI22X1TS U4359 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(
n4010), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[102]), .Y(
n3317) );
NAND3XLTS U4360 ( .A(n3318), .B(n3317), .C(n4012), .Y(n3320) );
AOI22X1TS U4361 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[25]),
.B0(n3602), .B1(n3320), .Y(n3319) );
OAI21XLTS U4362 ( .A0(n3322), .A1(n3546), .B0(n3319), .Y(n2560) );
AOI22X1TS U4363 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[29]),
.B0(n3612), .B1(n3320), .Y(n3321) );
OAI21XLTS U4364 ( .A0(n3322), .A1(n3549), .B0(n3321), .Y(n2564) );
AOI22X1TS U4365 ( .A0(n3325), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(
n3579), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(
n3323) );
OAI211XLTS U4366 ( .A0(n4014), .A1(n4995), .B0(n3323), .C0(n4012), .Y(n3324)
);
AOI21X1TS U4367 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(
n3324), .Y(n3331) );
AOI22X1TS U4368 ( .A0(n3325), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(
n3327) );
AOI22X1TS U4369 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(
n3579), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(
n3326) );
NAND3XLTS U4370 ( .A(n3327), .B(n3326), .C(n4012), .Y(n3329) );
AOI22X1TS U4371 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[28]),
.B0(n3612), .B1(n3329), .Y(n3328) );
OAI21XLTS U4372 ( .A0(n3331), .A1(n3549), .B0(n3328), .Y(n2563) );
AOI22X1TS U4373 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[26]),
.B0(n3602), .B1(n3329), .Y(n3330) );
OAI21XLTS U4374 ( .A0(n3331), .A1(n3546), .B0(n3330), .Y(n2561) );
AOI22X1TS U4375 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[107]), .A1(
n4010), .B0(n3579), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(
n3332) );
AOI21X1TS U4376 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(
n3333), .Y(n3339) );
AOI22X1TS U4377 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .A1(
n3579), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .B1(
n3109), .Y(n3335) );
AOI22X1TS U4378 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(
n4010), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(
n3334) );
NAND3XLTS U4379 ( .A(n3335), .B(n3334), .C(n4012), .Y(n3337) );
AOI22X1TS U4380 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[30]),
.B0(n3612), .B1(n3337), .Y(n3336) );
OAI21XLTS U4381 ( .A0(n3339), .A1(n3549), .B0(n3336), .Y(n2565) );
AOI22X1TS U4382 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[24]),
.B0(n3602), .B1(n3337), .Y(n3338) );
OAI21XLTS U4383 ( .A0(n3339), .A1(n3546), .B0(n3338), .Y(n2559) );
AOI22X1TS U4384 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[8]),
.B0(n3739), .B1(n3341), .Y(n3342) );
OAI21XLTS U4385 ( .A0(n3343), .A1(n3742), .B0(n3342), .Y(n2543) );
AOI22X1TS U4386 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[11]),
.B0(n3739), .B1(n3344), .Y(n3345) );
OAI21XLTS U4387 ( .A0(n3346), .A1(n3742), .B0(n3345), .Y(n2546) );
AOI22X1TS U4388 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[13]),
.B0(n3602), .B1(n3347), .Y(n3348) );
OAI21XLTS U4389 ( .A0(n3349), .A1(n3742), .B0(n3348), .Y(n2548) );
AOI22X1TS U4390 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[14]),
.B0(n3602), .B1(n3350), .Y(n3351) );
OAI21XLTS U4391 ( .A0(n3352), .A1(n3742), .B0(n3351), .Y(n2549) );
AOI22X1TS U4392 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[12]),
.B0(n3739), .B1(n3353), .Y(n3354) );
OAI21XLTS U4393 ( .A0(n3355), .A1(n3742), .B0(n3354), .Y(n2547) );
AOI22X1TS U4394 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[7]),
.B0(n3739), .B1(n3356), .Y(n3357) );
OAI21XLTS U4395 ( .A0(n2990), .A1(n3742), .B0(n3357), .Y(n2542) );
AOI22X1TS U4396 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[10]),
.B0(n3739), .B1(n3358), .Y(n3359) );
OAI21XLTS U4397 ( .A0(n3360), .A1(n3742), .B0(n3359), .Y(n2545) );
AOI22X1TS U4398 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[9]),
.B0(n3739), .B1(n3361), .Y(n3362) );
OAI21XLTS U4399 ( .A0(n3363), .A1(n3742), .B0(n3362), .Y(n2544) );
INVX2TS U4400 ( .A(n4143), .Y(n4141) );
INVX2TS U4401 ( .A(n3364), .Y(n4251) );
BUFX4TS U4402 ( .A(n4251), .Y(n4242) );
AOI22X1TS U4403 ( .A0(n2993), .A1(n4270), .B0(add_subt_module_DmP[51]), .B1(
n2950), .Y(n3365) );
BUFX3TS U4404 ( .A(n4149), .Y(n4211) );
AOI222X4TS U4405 ( .A0(n4205), .A1(add_subt_module_DmP[50]), .B0(
add_subt_module_Add_Subt_result[2]), .B1(n4211), .C0(
add_subt_module_Add_Subt_result[52]), .C1(n3366), .Y(n4038) );
INVX4TS U4406 ( .A(n4253), .Y(n4238) );
INVX4TS U4407 ( .A(n4234), .Y(n4284) );
AOI22X1TS U4408 ( .A0(n3617), .A1(n4238), .B0(n4284), .B1(n3618), .Y(n3367)
);
OAI21XLTS U4409 ( .A0(n4038), .A1(n3313), .B0(n3367), .Y(n3368) );
AOI21X1TS U4410 ( .A0(n4242), .A1(n4034), .B0(n3368), .Y(n4044) );
INVX4TS U4411 ( .A(n4152), .Y(n4091) );
OAI21XLTS U4412 ( .A0(n4044), .A1(n4091), .B0(n3619), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[52]) );
AOI222X4TS U4413 ( .A0(n4205), .A1(n4978), .B0(n4814), .B1(n4270), .C0(n4837), .C1(n4211), .Y(n4041) );
AOI22X1TS U4414 ( .A0(n4246), .A1(n3617), .B0(n4238), .B1(n4034), .Y(n3369)
);
OAI21XLTS U4415 ( .A0(n4038), .A1(n3364), .B0(n3369), .Y(n3370) );
AOI21X1TS U4416 ( .A0(n4271), .A1(n4041), .B0(n3370), .Y(n4049) );
AOI22X1TS U4417 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[15]),
.B0(n3602), .B1(n3371), .Y(n3372) );
OAI21XLTS U4418 ( .A0(n3373), .A1(n3742), .B0(n3372), .Y(n2550) );
OAI22X1TS U4419 ( .A0(n4821), .A1(add_subt_module_intDY[55]), .B0(
add_subt_module_intDY[54]), .B1(n4891), .Y(n3493) );
NOR2BX1TS U4420 ( .AN(add_subt_module_intDX[56]), .B(
add_subt_module_intDY[56]), .Y(n3375) );
NOR2X1TS U4421 ( .A(n4901), .B(add_subt_module_intDY[57]), .Y(n3447) );
NAND2BXLTS U4422 ( .AN(add_subt_module_intDY[62]), .B(
add_subt_module_intDX[62]), .Y(n3457) );
NAND2X1TS U4423 ( .A(n4945), .B(add_subt_module_intDX[61]), .Y(n3453) );
OAI211X1TS U4424 ( .A0(add_subt_module_intDY[60]), .A1(n4892), .B0(n3457),
.C0(n3453), .Y(n3459) );
NAND2BXLTS U4425 ( .AN(add_subt_module_intDY[59]), .B(
add_subt_module_intDX[59]), .Y(n3449) );
OAI21X1TS U4426 ( .A0(add_subt_module_intDY[58]), .A1(n4823), .B0(n3449),
.Y(n3451) );
NOR2X1TS U4427 ( .A(n4932), .B(add_subt_module_intDY[49]), .Y(n3496) );
NAND2BXLTS U4428 ( .AN(add_subt_module_intDY[51]), .B(
add_subt_module_intDX[51]), .Y(n3498) );
OAI21X1TS U4429 ( .A0(add_subt_module_intDY[50]), .A1(n4830), .B0(n3498),
.Y(n3502) );
AOI211X1TS U4430 ( .A0(add_subt_module_intDX[48]), .A1(n5004), .B0(n3496),
.C0(n3502), .Y(n3376) );
NAND3X1TS U4431 ( .A(n3495), .B(n3504), .C(n3376), .Y(n3512) );
NOR2BX1TS U4432 ( .AN(add_subt_module_intDX[39]), .B(
add_subt_module_intDY[39]), .Y(n3487) );
AOI21X1TS U4433 ( .A0(add_subt_module_intDX[38]), .A1(n4900), .B0(n3487),
.Y(n3486) );
NAND2X1TS U4434 ( .A(n4902), .B(add_subt_module_intDX[37]), .Y(n3475) );
OAI211X1TS U4435 ( .A0(add_subt_module_intDY[36]), .A1(n4914), .B0(n3486),
.C0(n3475), .Y(n3477) );
NOR2X1TS U4436 ( .A(n4962), .B(add_subt_module_intDY[45]), .Y(n3461) );
OAI21X1TS U4437 ( .A0(add_subt_module_intDY[46]), .A1(n4927), .B0(n3460),
.Y(n3470) );
OA22X1TS U4438 ( .A0(n4831), .A1(add_subt_module_intDY[42]), .B0(n4923),
.B1(add_subt_module_intDY[43]), .Y(n3466) );
NAND4XLTS U4439 ( .A(n3468), .B(n3466), .C(n3378), .D(n3377), .Y(n3510) );
OA22X1TS U4440 ( .A0(n4832), .A1(add_subt_module_intDY[34]), .B0(n4963),
.B1(add_subt_module_intDY[35]), .Y(n3481) );
OAI211XLTS U4441 ( .A0(n4915), .A1(add_subt_module_intDY[33]), .B0(n3379),
.C0(n3481), .Y(n3380) );
NOR4X1TS U4442 ( .A(n3512), .B(n3477), .C(n3510), .D(n3380), .Y(n3516) );
OA22X1TS U4443 ( .A0(n4952), .A1(n2996), .B0(n4826), .B1(
add_subt_module_intDY[31]), .Y(n3391) );
OAI21XLTS U4444 ( .A0(add_subt_module_intDY[29]), .A1(n4948), .B0(
add_subt_module_intDY[28]), .Y(n3381) );
OAI2BB2XLTS U4445 ( .B0(add_subt_module_intDX[28]), .B1(n3381), .A0N(
add_subt_module_intDY[29]), .A1N(n4948), .Y(n3390) );
OAI21X1TS U4446 ( .A0(add_subt_module_intDY[26]), .A1(n4829), .B0(n3384),
.Y(n3442) );
NOR2X1TS U4447 ( .A(n4964), .B(add_subt_module_intDY[25]), .Y(n3439) );
NOR2XLTS U4448 ( .A(n3439), .B(add_subt_module_intDX[24]), .Y(n3383) );
AOI22X1TS U4449 ( .A0(n3383), .A1(n2998), .B0(add_subt_module_intDY[25]),
.B1(n4964), .Y(n3386) );
OAI32X1TS U4450 ( .A0(n3442), .A1(n3441), .A2(n3386), .B0(n3385), .B1(n3441),
.Y(n3389) );
OAI21XLTS U4451 ( .A0(add_subt_module_intDY[31]), .A1(n4826), .B0(n2996),
.Y(n3387) );
OAI2BB2XLTS U4452 ( .B0(add_subt_module_intDX[30]), .B1(n3387), .A0N(
add_subt_module_intDY[31]), .A1N(n4826), .Y(n3388) );
AOI211X1TS U4453 ( .A0(n3391), .A1(n3390), .B0(n3389), .C0(n3388), .Y(n3446)
);
OA22X1TS U4454 ( .A0(n4827), .A1(n2995), .B0(n4924), .B1(
add_subt_module_intDY[23]), .Y(n3438) );
OA22X1TS U4455 ( .A0(n4828), .A1(add_subt_module_intDY[14]), .B0(n4933),
.B1(add_subt_module_intDY[15]), .Y(n3419) );
NAND2BXLTS U4456 ( .AN(add_subt_module_intDY[13]), .B(
add_subt_module_intDX[13]), .Y(n3393) );
OAI2BB1X1TS U4457 ( .A0N(n4903), .A1N(add_subt_module_intDX[5]), .B0(
add_subt_module_intDY[4]), .Y(n3394) );
OAI22X1TS U4458 ( .A0(add_subt_module_intDX[4]), .A1(n3394), .B0(n4903),
.B1(add_subt_module_intDX[5]), .Y(n3405) );
OAI2BB1X1TS U4459 ( .A0N(n4825), .A1N(add_subt_module_intDX[7]), .B0(
add_subt_module_intDY[6]), .Y(n3395) );
OAI22X1TS U4460 ( .A0(add_subt_module_intDX[6]), .A1(n3395), .B0(n4825),
.B1(add_subt_module_intDX[7]), .Y(n3404) );
AOI2BB2XLTS U4461 ( .B0(add_subt_module_intDX[1]), .B1(n4893), .A0N(
add_subt_module_intDY[0]), .A1N(n3396), .Y(n3397) );
OAI211XLTS U4462 ( .A0(n4960), .A1(add_subt_module_intDY[3]), .B0(n3398),
.C0(n3397), .Y(n3401) );
OAI21XLTS U4463 ( .A0(add_subt_module_intDY[3]), .A1(n4960), .B0(
add_subt_module_intDY[2]), .Y(n3399) );
AOI2BB2XLTS U4464 ( .B0(add_subt_module_intDY[3]), .B1(n4960), .A0N(
add_subt_module_intDX[2]), .A1N(n3399), .Y(n3400) );
AOI222X1TS U4465 ( .A0(add_subt_module_intDX[4]), .A1(n4822), .B0(
add_subt_module_intDX[5]), .B1(n4903), .C0(n3401), .C1(n3400), .Y(
n3403) );
AOI22X1TS U4466 ( .A0(add_subt_module_intDX[7]), .A1(n4825), .B0(
add_subt_module_intDX[6]), .B1(n4909), .Y(n3402) );
OAI32X1TS U4467 ( .A0(n3405), .A1(n3404), .A2(n3403), .B0(n3402), .B1(n3404),
.Y(n3422) );
NOR2X1TS U4468 ( .A(n4916), .B(add_subt_module_intDY[11]), .Y(n3407) );
AOI21X1TS U4469 ( .A0(add_subt_module_intDX[10]), .A1(n4899), .B0(n3407),
.Y(n3412) );
OAI211XLTS U4470 ( .A0(add_subt_module_intDY[8]), .A1(n4959), .B0(n3409),
.C0(n3412), .Y(n3421) );
OAI2BB2XLTS U4471 ( .B0(add_subt_module_intDX[12]), .B1(n3406), .A0N(
add_subt_module_intDY[13]), .A1N(n4955), .Y(n3418) );
NOR2XLTS U4472 ( .A(n3407), .B(add_subt_module_intDX[10]), .Y(n3408) );
AOI22X1TS U4473 ( .A0(add_subt_module_intDY[11]), .A1(n4916), .B0(
add_subt_module_intDY[10]), .B1(n3408), .Y(n3414) );
NAND3XLTS U4474 ( .A(n4959), .B(n3409), .C(add_subt_module_intDY[8]), .Y(
n3411) );
NAND2BXLTS U4475 ( .AN(add_subt_module_intDX[9]), .B(
add_subt_module_intDY[9]), .Y(n3410) );
AOI21X1TS U4476 ( .A0(n3411), .A1(n3410), .B0(n3423), .Y(n3413) );
OAI2BB2XLTS U4477 ( .B0(n3414), .B1(n3423), .A0N(n3413), .A1N(n3412), .Y(
n3417) );
OAI21XLTS U4478 ( .A0(add_subt_module_intDY[15]), .A1(n4933), .B0(
add_subt_module_intDY[14]), .Y(n3415) );
OAI2BB2XLTS U4479 ( .B0(add_subt_module_intDX[14]), .B1(n3415), .A0N(
add_subt_module_intDY[15]), .A1N(n4933), .Y(n3416) );
AOI211X1TS U4480 ( .A0(n3419), .A1(n3418), .B0(n3417), .C0(n3416), .Y(n3420)
);
OAI31X1TS U4481 ( .A0(n3423), .A1(n3422), .A2(n3421), .B0(n3420), .Y(n3425)
);
NOR2X1TS U4482 ( .A(n4939), .B(add_subt_module_intDY[17]), .Y(n3427) );
OAI21X1TS U4483 ( .A0(add_subt_module_intDY[18]), .A1(n4958), .B0(n3429),
.Y(n3433) );
AOI211XLTS U4484 ( .A0(add_subt_module_intDX[16]), .A1(n4934), .B0(n3427),
.C0(n3433), .Y(n3424) );
NAND3BXLTS U4485 ( .AN(n3432), .B(n3425), .C(n3424), .Y(n3445) );
OAI21XLTS U4486 ( .A0(add_subt_module_intDY[21]), .A1(n4938), .B0(
add_subt_module_intDY[20]), .Y(n3426) );
OAI2BB2XLTS U4487 ( .B0(add_subt_module_intDX[20]), .B1(n3426), .A0N(
add_subt_module_intDY[21]), .A1N(n4938), .Y(n3437) );
NOR2XLTS U4488 ( .A(n3427), .B(add_subt_module_intDX[16]), .Y(n3428) );
AOI22X1TS U4489 ( .A0(n3428), .A1(add_subt_module_intDY[16]), .B0(
add_subt_module_intDY[17]), .B1(n4939), .Y(n3431) );
OAI32X1TS U4490 ( .A0(n3433), .A1(n3432), .A2(n3431), .B0(n3430), .B1(n3432),
.Y(n3436) );
OAI21XLTS U4491 ( .A0(add_subt_module_intDY[23]), .A1(n4924), .B0(n2995),
.Y(n3434) );
OAI2BB2XLTS U4492 ( .B0(add_subt_module_intDX[22]), .B1(n3434), .A0N(
add_subt_module_intDY[23]), .A1N(n4924), .Y(n3435) );
AOI211X1TS U4493 ( .A0(n3438), .A1(n3437), .B0(n3436), .C0(n3435), .Y(n3444)
);
NOR2BX1TS U4494 ( .AN(add_subt_module_intDX[24]), .B(n2998), .Y(n3440) );
OR4X2TS U4495 ( .A(n3442), .B(n3441), .C(n3440), .D(n3439), .Y(n3443) );
AOI32X1TS U4496 ( .A0(n3446), .A1(n3445), .A2(n3444), .B0(n3443), .B1(n3446),
.Y(n3515) );
NOR2XLTS U4497 ( .A(n3447), .B(add_subt_module_intDX[56]), .Y(n3448) );
AOI22X1TS U4498 ( .A0(add_subt_module_intDY[57]), .A1(n4901), .B0(
add_subt_module_intDY[56]), .B1(n3448), .Y(n3452) );
AOI32X1TS U4499 ( .A0(n4823), .A1(n3449), .A2(add_subt_module_intDY[58]),
.B0(add_subt_module_intDY[59]), .B1(n4908), .Y(n3450) );
OA21XLTS U4500 ( .A0(n3452), .A1(n3451), .B0(n3450), .Y(n3458) );
NAND3XLTS U4501 ( .A(n4892), .B(n3453), .C(add_subt_module_intDY[60]), .Y(
n3454) );
OAI211XLTS U4502 ( .A0(add_subt_module_intDX[61]), .A1(n4945), .B0(n3455),
.C0(n3454), .Y(n3456) );
OAI2BB2XLTS U4503 ( .B0(n3459), .B1(n3458), .A0N(n3457), .A1N(n3456), .Y(
n3514) );
NOR2BX1TS U4504 ( .AN(n3460), .B(add_subt_module_intDX[46]), .Y(n3474) );
NOR2XLTS U4505 ( .A(n3461), .B(add_subt_module_intDX[44]), .Y(n3462) );
AOI22X1TS U4506 ( .A0(add_subt_module_intDY[45]), .A1(n4962), .B0(
add_subt_module_intDY[44]), .B1(n3462), .Y(n3471) );
OAI21XLTS U4507 ( .A0(add_subt_module_intDY[41]), .A1(n4910), .B0(
add_subt_module_intDY[40]), .Y(n3463) );
OAI2BB2XLTS U4508 ( .B0(add_subt_module_intDX[40]), .B1(n3463), .A0N(
add_subt_module_intDY[41]), .A1N(n4910), .Y(n3467) );
OAI21XLTS U4509 ( .A0(add_subt_module_intDY[43]), .A1(n4923), .B0(
add_subt_module_intDY[42]), .Y(n3464) );
OAI2BB2XLTS U4510 ( .B0(add_subt_module_intDX[42]), .B1(n3464), .A0N(
add_subt_module_intDY[43]), .A1N(n4923), .Y(n3465) );
AOI32X1TS U4511 ( .A0(n3468), .A1(n3467), .A2(n3466), .B0(n3465), .B1(n3468),
.Y(n3469) );
NOR2BX1TS U4512 ( .AN(add_subt_module_intDY[47]), .B(
add_subt_module_intDX[47]), .Y(n3472) );
NAND3XLTS U4513 ( .A(n4914), .B(n3475), .C(add_subt_module_intDY[36]), .Y(
n3476) );
OAI21XLTS U4514 ( .A0(add_subt_module_intDX[37]), .A1(n4902), .B0(n3476),
.Y(n3485) );
INVX2TS U4515 ( .A(n3477), .Y(n3483) );
OAI21XLTS U4516 ( .A0(add_subt_module_intDY[33]), .A1(n4915), .B0(n2997),
.Y(n3478) );
OAI2BB2XLTS U4517 ( .B0(add_subt_module_intDX[32]), .B1(n3478), .A0N(
add_subt_module_intDY[33]), .A1N(n4915), .Y(n3482) );
OAI21XLTS U4518 ( .A0(add_subt_module_intDY[35]), .A1(n4963), .B0(
add_subt_module_intDY[34]), .Y(n3479) );
OAI2BB2XLTS U4519 ( .B0(add_subt_module_intDX[34]), .B1(n3479), .A0N(
add_subt_module_intDY[35]), .A1N(n4963), .Y(n3480) );
AOI32X1TS U4520 ( .A0(n3483), .A1(n3482), .A2(n3481), .B0(n3480), .B1(n3483),
.Y(n3484) );
OAI2BB1X1TS U4521 ( .A0N(n3486), .A1N(n3485), .B0(n3484), .Y(n3491) );
NOR2BX1TS U4522 ( .AN(add_subt_module_intDY[39]), .B(
add_subt_module_intDX[39]), .Y(n3490) );
NOR3X1TS U4523 ( .A(n4900), .B(n3487), .C(add_subt_module_intDX[38]), .Y(
n3489) );
INVX2TS U4524 ( .A(n3512), .Y(n3488) );
OAI31X1TS U4525 ( .A0(n3491), .A1(n3490), .A2(n3489), .B0(n3488), .Y(n3509)
);
OAI21XLTS U4526 ( .A0(add_subt_module_intDY[53]), .A1(n4897), .B0(
add_subt_module_intDY[52]), .Y(n3492) );
AOI2BB2XLTS U4527 ( .B0(add_subt_module_intDY[53]), .B1(n4897), .A0N(
add_subt_module_intDX[52]), .A1N(n3492), .Y(n3494) );
INVX2TS U4528 ( .A(n3495), .Y(n3501) );
AOI22X1TS U4529 ( .A0(add_subt_module_intDY[49]), .A1(n4932), .B0(
add_subt_module_intDY[48]), .B1(n3497), .Y(n3500) );
AOI32X1TS U4530 ( .A0(n4830), .A1(n3498), .A2(add_subt_module_intDY[50]),
.B0(add_subt_module_intDY[51]), .B1(n4954), .Y(n3499) );
OAI32X1TS U4531 ( .A0(n3502), .A1(n3501), .A2(n3500), .B0(n3499), .B1(n3501),
.Y(n3506) );
OAI2BB2XLTS U4532 ( .B0(add_subt_module_intDX[54]), .B1(n3503), .A0N(
add_subt_module_intDY[55]), .A1N(n4821), .Y(n3505) );
OAI31X1TS U4533 ( .A0(n3507), .A1(n3506), .A2(n3505), .B0(n3504), .Y(n3508)
);
OAI221XLTS U4534 ( .A0(n3512), .A1(n3511), .B0(n3510), .B1(n3509), .C0(n3508), .Y(n3513) );
AOI22X1TS U4535 ( .A0(n3621), .A1(add_subt_module_intDX[52]), .B0(
add_subt_module_DMP[52]), .B1(n3721), .Y(n3518) );
OAI21XLTS U4536 ( .A0(n4926), .A1(n3003), .B0(n3518), .Y(n1910) );
BUFX4TS U4537 ( .A(n3621), .Y(n3574) );
AOI22X1TS U4538 ( .A0(n3574), .A1(add_subt_module_intDX[56]), .B0(
add_subt_module_DMP[56]), .B1(n3721), .Y(n3519) );
OAI21XLTS U4539 ( .A0(n4925), .A1(n3003), .B0(n3519), .Y(n1922) );
BUFX4TS U4540 ( .A(n3003), .Y(n3659) );
AOI22X1TS U4541 ( .A0(n3574), .A1(add_subt_module_intDX[61]), .B0(
add_subt_module_DMP[61]), .B1(n3700), .Y(n3520) );
OAI21XLTS U4542 ( .A0(n4945), .A1(n3659), .B0(n3520), .Y(n1937) );
AOI22X1TS U4543 ( .A0(n3574), .A1(add_subt_module_intDX[62]), .B0(
add_subt_module_DMP[62]), .B1(n3700), .Y(n3521) );
OAI21XLTS U4544 ( .A0(n4913), .A1(n3659), .B0(n3521), .Y(n1940) );
BUFX4TS U4545 ( .A(n3003), .Y(n3657) );
AOI22X1TS U4546 ( .A0(n3621), .A1(add_subt_module_intDX[60]), .B0(
add_subt_module_DMP[60]), .B1(n3700), .Y(n3522) );
OAI21XLTS U4547 ( .A0(n4840), .A1(n3657), .B0(n3522), .Y(n1934) );
AOI22X1TS U4548 ( .A0(add_subt_module_DmP[6]), .A1(n3721), .B0(
add_subt_module_intDY[6]), .B1(n3703), .Y(n3523) );
OAI21XLTS U4549 ( .A0(n4920), .A1(n3657), .B0(n3523), .Y(n1861) );
AOI22X1TS U4550 ( .A0(n3818), .A1(add_subt_module_DmP[5]), .B0(
add_subt_module_intDY[5]), .B1(n3703), .Y(n3524) );
OAI21XLTS U4551 ( .A0(n4907), .A1(n3657), .B0(n3524), .Y(n1858) );
AOI22X1TS U4552 ( .A0(add_subt_module_DmP[4]), .A1(n3818), .B0(
add_subt_module_intDY[4]), .B1(n3621), .Y(n3525) );
OAI21XLTS U4553 ( .A0(n4951), .A1(n3657), .B0(n3525), .Y(n1902) );
AOI22X1TS U4554 ( .A0(n3621), .A1(add_subt_module_intDX[0]), .B0(
add_subt_module_DMP[0]), .B1(n4564), .Y(n3526) );
OAI21XLTS U4555 ( .A0(n4961), .A1(n3659), .B0(n3526), .Y(n1703) );
AOI22X1TS U4556 ( .A0(n3574), .A1(add_subt_module_intDX[54]), .B0(
add_subt_module_DMP[54]), .B1(n3700), .Y(n3527) );
OAI21XLTS U4557 ( .A0(n4947), .A1(n3659), .B0(n3527), .Y(n1916) );
AOI22X1TS U4558 ( .A0(add_subt_module_DmP[1]), .A1(n3714), .B0(
add_subt_module_intDY[1]), .B1(n3703), .Y(n3528) );
OAI21XLTS U4559 ( .A0(n4922), .A1(n3657), .B0(n3528), .Y(n1882) );
AOI22X1TS U4560 ( .A0(add_subt_module_DmP[16]), .A1(n3714), .B0(
add_subt_module_intDY[16]), .B1(n3574), .Y(n3529) );
OAI21XLTS U4561 ( .A0(n4921), .A1(n3657), .B0(n3529), .Y(n1871) );
AOI22X1TS U4562 ( .A0(add_subt_module_DmP[44]), .A1(n3714), .B0(
add_subt_module_intDY[44]), .B1(n3574), .Y(n3530) );
OAI21XLTS U4563 ( .A0(n4918), .A1(n3657), .B0(n3530), .Y(n1865) );
AOI22X1TS U4564 ( .A0(add_subt_module_DmP[7]), .A1(n3818), .B0(
add_subt_module_intDY[7]), .B1(n3574), .Y(n3531) );
OAI21XLTS U4565 ( .A0(n4906), .A1(n3003), .B0(n3531), .Y(n1838) );
AOI22X1TS U4566 ( .A0(n3574), .A1(add_subt_module_intDX[58]), .B0(
add_subt_module_DMP[58]), .B1(n3818), .Y(n3532) );
OAI21XLTS U4567 ( .A0(n3788), .A1(n3657), .B0(n3532), .Y(n1928) );
AOI22X1TS U4568 ( .A0(n3574), .A1(add_subt_module_intDX[55]), .B0(
add_subt_module_DMP[55]), .B1(n4564), .Y(n3533) );
OAI21XLTS U4569 ( .A0(n4905), .A1(n3003), .B0(n3533), .Y(n1919) );
AOI22X1TS U4570 ( .A0(n3621), .A1(add_subt_module_intDX[53]), .B0(
add_subt_module_DMP[53]), .B1(n3721), .Y(n3534) );
OAI21XLTS U4571 ( .A0(n4835), .A1(n3003), .B0(n3534), .Y(n1913) );
AOI22X1TS U4572 ( .A0(n3721), .A1(add_subt_module_DmP[38]), .B0(
add_subt_module_intDY[38]), .B1(n3574), .Y(n3535) );
OAI21XLTS U4573 ( .A0(n4833), .A1(n3003), .B0(n3535), .Y(n1831) );
AOI22X1TS U4574 ( .A0(n3574), .A1(add_subt_module_intDX[57]), .B0(
add_subt_module_DMP[57]), .B1(n3818), .Y(n3536) );
OAI21XLTS U4575 ( .A0(n3752), .A1(n3003), .B0(n3536), .Y(n1925) );
AOI22X1TS U4576 ( .A0(n3818), .A1(add_subt_module_DmP[9]), .B0(
add_subt_module_intDY[9]), .B1(n3703), .Y(n3537) );
AOI22X1TS U4577 ( .A0(n3714), .A1(add_subt_module_DmP[46]), .B0(
add_subt_module_intDY[46]), .B1(n3703), .Y(n3538) );
OAI21XLTS U4578 ( .A0(n4927), .A1(n3657), .B0(n3538), .Y(n1875) );
AOI22X1TS U4579 ( .A0(n3579), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(
n3539) );
OAI21XLTS U4580 ( .A0(n2999), .A1(n4997), .B0(n3539), .Y(n3540) );
NOR3X1TS U4581 ( .A(n3542), .B(n3541), .C(n3540), .Y(n3550) );
AOI22X1TS U4582 ( .A0(n3597), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(
n3544) );
AOI22X1TS U4583 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(
n4010), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(
n3543) );
NAND3XLTS U4584 ( .A(n3544), .B(n3543), .C(n4012), .Y(n3547) );
AOI22X1TS U4585 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[23]),
.B0(n3602), .B1(n3547), .Y(n3545) );
OAI21XLTS U4586 ( .A0(n3550), .A1(n3546), .B0(n3545), .Y(n2558) );
AOI22X1TS U4587 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[31]),
.B0(n3612), .B1(n3547), .Y(n3548) );
OAI21XLTS U4588 ( .A0(n3550), .A1(n3549), .B0(n3548), .Y(n2566) );
AOI22X1TS U4589 ( .A0(add_subt_module_DmP[47]), .A1(n3818), .B0(
add_subt_module_intDY[47]), .B1(n3621), .Y(n3551) );
OAI21XLTS U4590 ( .A0(n4917), .A1(n3657), .B0(n3551), .Y(n1889) );
AOI22X1TS U4591 ( .A0(n3714), .A1(add_subt_module_DmP[34]), .B0(
add_subt_module_intDY[34]), .B1(n3621), .Y(n3552) );
OAI21XLTS U4592 ( .A0(n4832), .A1(n3659), .B0(n3552), .Y(n1799) );
AOI22X1TS U4593 ( .A0(add_subt_module_DmP[42]), .A1(n3721), .B0(
add_subt_module_intDY[42]), .B1(n3621), .Y(n3553) );
AOI22X1TS U4594 ( .A0(add_subt_module_DmP[22]), .A1(n3818), .B0(n2995), .B1(
n3621), .Y(n3554) );
OAI21XLTS U4595 ( .A0(n4827), .A1(n3659), .B0(n3554), .Y(n1740) );
AOI22X1TS U4596 ( .A0(add_subt_module_DmP[19]), .A1(n3714), .B0(
add_subt_module_intDY[19]), .B1(n3621), .Y(n3555) );
OAI21XLTS U4597 ( .A0(n4839), .A1(n3003), .B0(n3555), .Y(n1802) );
AOI22X1TS U4598 ( .A0(add_subt_module_DmP[39]), .A1(n3721), .B0(
add_subt_module_intDY[39]), .B1(n3621), .Y(n3556) );
OAI21XLTS U4599 ( .A0(n4919), .A1(n3003), .B0(n3556), .Y(n1810) );
AOI22X1TS U4600 ( .A0(add_subt_module_DmP[14]), .A1(n3721), .B0(
add_subt_module_intDY[14]), .B1(n3621), .Y(n3557) );
OAI21XLTS U4601 ( .A0(n4828), .A1(n3657), .B0(n3557), .Y(n1779) );
AOI22X1TS U4602 ( .A0(n3714), .A1(add_subt_module_DmP[30]), .B0(n2996), .B1(
n3621), .Y(n3558) );
OAI21XLTS U4603 ( .A0(n4952), .A1(n3659), .B0(n3558), .Y(n1793) );
AOI22X1TS U4604 ( .A0(add_subt_module_DmP[28]), .A1(n3714), .B0(
add_subt_module_intDY[28]), .B1(n3621), .Y(n3559) );
OAI21XLTS U4605 ( .A0(n4930), .A1(n3659), .B0(n3559), .Y(n1737) );
AOI22X1TS U4606 ( .A0(add_subt_module_DmP[26]), .A1(n3818), .B0(
add_subt_module_intDY[26]), .B1(n3621), .Y(n3560) );
OAI21XLTS U4607 ( .A0(n4829), .A1(n3659), .B0(n3560), .Y(n1733) );
AOI22X1TS U4608 ( .A0(add_subt_module_DmP[36]), .A1(n3721), .B0(
add_subt_module_intDY[36]), .B1(n3621), .Y(n3561) );
OAI21XLTS U4609 ( .A0(n4914), .A1(n3657), .B0(n3561), .Y(n1783) );
AOI22X1TS U4610 ( .A0(add_subt_module_DmP[11]), .A1(n3714), .B0(
add_subt_module_intDY[11]), .B1(n3621), .Y(n3562) );
OAI21XLTS U4611 ( .A0(n4916), .A1(n3003), .B0(n3562), .Y(n1824) );
AOI22X1TS U4612 ( .A0(add_subt_module_DmP[8]), .A1(n3721), .B0(
add_subt_module_intDY[8]), .B1(n3621), .Y(n3563) );
OAI21XLTS U4613 ( .A0(n4959), .A1(n3003), .B0(n3563), .Y(n1817) );
AOI22X1TS U4614 ( .A0(add_subt_module_DmP[12]), .A1(n3721), .B0(
add_subt_module_intDY[12]), .B1(n3621), .Y(n3564) );
OAI21XLTS U4615 ( .A0(n4950), .A1(n3003), .B0(n3564), .Y(n1827) );
AOI22X1TS U4616 ( .A0(add_subt_module_DmP[40]), .A1(n3714), .B0(
add_subt_module_intDY[40]), .B1(n3574), .Y(n3565) );
OAI21XLTS U4617 ( .A0(n4928), .A1(n3003), .B0(n3565), .Y(n1835) );
AOI22X1TS U4618 ( .A0(add_subt_module_DmP[50]), .A1(n3714), .B0(
add_subt_module_intDY[50]), .B1(n3574), .Y(n3566) );
OAI21XLTS U4619 ( .A0(n4830), .A1(n3003), .B0(n3566), .Y(n1892) );
AOI22X1TS U4620 ( .A0(add_subt_module_DmP[2]), .A1(n3818), .B0(
add_subt_module_intDY[2]), .B1(n3574), .Y(n3567) );
OAI21XLTS U4621 ( .A0(n4946), .A1(n3003), .B0(n3567), .Y(n1895) );
AOI22X1TS U4622 ( .A0(add_subt_module_DmP[23]), .A1(n3818), .B0(
add_subt_module_intDY[23]), .B1(n3621), .Y(n3568) );
OAI21XLTS U4623 ( .A0(n4924), .A1(n3659), .B0(n3568), .Y(n1796) );
AOI22X1TS U4624 ( .A0(add_subt_module_DmP[35]), .A1(n3818), .B0(
add_subt_module_intDY[35]), .B1(n3621), .Y(n3569) );
OAI21XLTS U4625 ( .A0(n4963), .A1(n3657), .B0(n3569), .Y(n1790) );
AOI22X1TS U4626 ( .A0(add_subt_module_DmP[43]), .A1(n3721), .B0(
add_subt_module_intDY[43]), .B1(n3574), .Y(n3570) );
AOI22X1TS U4627 ( .A0(n3714), .A1(add_subt_module_DmP[31]), .B0(
add_subt_module_intDY[31]), .B1(n3574), .Y(n3571) );
OAI21XLTS U4628 ( .A0(n4826), .A1(n3659), .B0(n3571), .Y(n1772) );
AOI22X1TS U4629 ( .A0(n3574), .A1(add_subt_module_intDX[59]), .B0(
add_subt_module_DMP[59]), .B1(n4564), .Y(n3572) );
OAI21XLTS U4630 ( .A0(n4841), .A1(n3659), .B0(n3572), .Y(n1931) );
AOI22X1TS U4631 ( .A0(add_subt_module_DmP[20]), .A1(n3818), .B0(
add_subt_module_intDY[20]), .B1(n3703), .Y(n3573) );
OAI21XLTS U4632 ( .A0(n4940), .A1(n3657), .B0(n3573), .Y(n1851) );
AOI22X1TS U4633 ( .A0(add_subt_module_DmP[3]), .A1(n3721), .B0(
add_subt_module_intDY[3]), .B1(n3574), .Y(n3575) );
OAI21XLTS U4634 ( .A0(n4960), .A1(n3657), .B0(n3575), .Y(n1885) );
AOI22X1TS U4635 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[17]),
.B0(n3602), .B1(n3576), .Y(n3577) );
OAI21XLTS U4636 ( .A0(n3578), .A1(n3742), .B0(n3577), .Y(n2552) );
AOI22X1TS U4637 ( .A0(n3579), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(
n3581) );
AOI22X1TS U4638 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[79]), .B0(
n4010), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[95]), .Y(
n3580) );
OAI211X1TS U4639 ( .A0(n3601), .A1(n2979), .B0(n3581), .C0(n3580), .Y(n3604)
);
AOI22X1TS U4640 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[18]),
.B0(n3602), .B1(n3604), .Y(n3582) );
OAI21XLTS U4641 ( .A0(n3606), .A1(n3742), .B0(n3582), .Y(n2553) );
AOI22X1TS U4642 ( .A0(n3325), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[85]), .B1(
n3109), .Y(n3585) );
AOI22X1TS U4643 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(
n3584) );
OAI211X1TS U4644 ( .A0(n3601), .A1(n2989), .B0(n3585), .C0(n3584), .Y(n3607)
);
AOI22X1TS U4645 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[16]),
.B0(n3602), .B1(n3607), .Y(n3586) );
OAI21XLTS U4646 ( .A0(n3610), .A1(n3742), .B0(n3586), .Y(n2551) );
AOI22X1TS U4647 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[20]),
.B0(n3602), .B1(n3587), .Y(n3588) );
AOI22X1TS U4648 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[21]),
.B0(n3602), .B1(n3590), .Y(n3591) );
OAI21XLTS U4649 ( .A0(n3592), .A1(n3742), .B0(n3591), .Y(n2556) );
AOI22X1TS U4650 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[19]),
.B0(n3602), .B1(n3593), .Y(n3594) );
OAI21XLTS U4651 ( .A0(n3595), .A1(n3742), .B0(n3594), .Y(n2554) );
AOI22X1TS U4652 ( .A0(n4010), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(
n3596), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(
n3600) );
AOI22X1TS U4653 ( .A0(n3598), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(
n3597), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(
n3599) );
OAI211X1TS U4654 ( .A0(n3601), .A1(n2988), .B0(n3600), .C0(n3599), .Y(n3611)
);
AOI22X1TS U4655 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[22]),
.B0(n3602), .B1(n3611), .Y(n3603) );
AOI22X1TS U4656 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[36]),
.B0(n3612), .B1(n3604), .Y(n3605) );
OAI211XLTS U4657 ( .A0(n3606), .A1(n3615), .B0(n3605), .C0(n3613), .Y(n2571)
);
AOI22X1TS U4658 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[38]),
.B0(n3612), .B1(n3607), .Y(n3609) );
OAI211XLTS U4659 ( .A0(n3610), .A1(n3615), .B0(n3609), .C0(n3613), .Y(n2573)
);
AOI22X1TS U4660 ( .A0(n3608), .A1(add_subt_module_Sgf_normalized_result[32]),
.B0(n3612), .B1(n3611), .Y(n3614) );
OAI211XLTS U4661 ( .A0(n3616), .A1(n3615), .B0(n3614), .C0(n3613), .Y(n2567)
);
INVX2TS U4662 ( .A(n4146), .Y(n4155) );
AOI222X1TS U4663 ( .A0(n4155), .A1(n3618), .B0(n4242), .B1(n3617), .C0(n4034), .C1(n4271), .Y(n4040) );
INVX4TS U4664 ( .A(n3003), .Y(n3719) );
AOI22X1TS U4665 ( .A0(n3719), .A1(add_subt_module_intDY[37]), .B0(
add_subt_module_DMP[37]), .B1(n3700), .Y(n3620) );
OAI21XLTS U4666 ( .A0(n4929), .A1(n4560), .B0(n3620), .Y(n1806) );
AOI22X1TS U4667 ( .A0(n3719), .A1(add_subt_module_intDY[44]), .B0(
add_subt_module_DMP[44]), .B1(n3818), .Y(n3622) );
OAI21XLTS U4668 ( .A0(n4918), .A1(n3702), .B0(n3622), .Y(n1864) );
AOI22X1TS U4669 ( .A0(n3719), .A1(add_subt_module_intDY[38]), .B0(
add_subt_module_DMP[38]), .B1(n4564), .Y(n3623) );
OAI21XLTS U4670 ( .A0(n4833), .A1(n3702), .B0(n3623), .Y(n1830) );
AOI22X1TS U4671 ( .A0(n3719), .A1(add_subt_module_intDY[40]), .B0(
add_subt_module_DMP[40]), .B1(n3818), .Y(n3624) );
OAI21XLTS U4672 ( .A0(n4928), .A1(n4560), .B0(n3624), .Y(n1834) );
AOI22X1TS U4673 ( .A0(n3719), .A1(add_subt_module_intDY[39]), .B0(
add_subt_module_DMP[39]), .B1(n3711), .Y(n3625) );
AOI22X1TS U4674 ( .A0(n3719), .A1(add_subt_module_intDY[42]), .B0(
add_subt_module_DMP[42]), .B1(n3721), .Y(n3626) );
OAI21XLTS U4675 ( .A0(n4831), .A1(n3699), .B0(n3626), .Y(n1820) );
AOI22X1TS U4676 ( .A0(n3719), .A1(add_subt_module_intDY[45]), .B0(
add_subt_module_DMP[45]), .B1(n3721), .Y(n3627) );
OAI21XLTS U4677 ( .A0(n4962), .A1(n3699), .B0(n3627), .Y(n1854) );
AOI22X1TS U4678 ( .A0(n3719), .A1(add_subt_module_intDY[41]), .B0(
add_subt_module_DMP[41]), .B1(n3700), .Y(n3628) );
OAI21XLTS U4679 ( .A0(n4910), .A1(n3699), .B0(n3628), .Y(n1813) );
AOI22X1TS U4680 ( .A0(n3719), .A1(add_subt_module_intDY[43]), .B0(
add_subt_module_DMP[43]), .B1(n3700), .Y(n3629) );
OAI21XLTS U4681 ( .A0(n4923), .A1(n3699), .B0(n3629), .Y(n1841) );
AOI22X1TS U4682 ( .A0(add_subt_module_DmP[37]), .A1(n3721), .B0(
add_subt_module_intDY[37]), .B1(n3703), .Y(n3630) );
OAI21XLTS U4683 ( .A0(n4929), .A1(n3003), .B0(n3630), .Y(n1807) );
AOI222X1TS U4684 ( .A0(n3719), .A1(add_subt_module_intDX[49]), .B0(
add_subt_module_DmP[49]), .B1(n4564), .C0(add_subt_module_intDY[49]),
.C1(n3703), .Y(n3632) );
INVX2TS U4685 ( .A(n3632), .Y(n1879) );
AOI222X1TS U4686 ( .A0(n3719), .A1(add_subt_module_intDX[10]), .B0(
add_subt_module_DmP[10]), .B1(n3700), .C0(add_subt_module_intDY[10]),
.C1(n3703), .Y(n3633) );
INVX2TS U4687 ( .A(n3633), .Y(n1845) );
AOI222X1TS U4688 ( .A0(n3719), .A1(add_subt_module_intDX[15]), .B0(
add_subt_module_DmP[15]), .B1(n3700), .C0(add_subt_module_intDY[15]),
.C1(n3703), .Y(n3634) );
INVX2TS U4689 ( .A(n3634), .Y(n1786) );
AOI22X1TS U4690 ( .A0(n3712), .A1(add_subt_module_intDY[51]), .B0(
add_subt_module_DMP[51]), .B1(n3711), .Y(n3635) );
OAI21XLTS U4691 ( .A0(n4954), .A1(n3702), .B0(n3635), .Y(n1704) );
INVX4TS U4692 ( .A(n3003), .Y(n3723) );
AOI22X1TS U4693 ( .A0(n3723), .A1(add_subt_module_intDX[60]), .B0(
add_subt_module_DmP[60]), .B1(n4564), .Y(n3636) );
OAI21XLTS U4694 ( .A0(n4840), .A1(n4560), .B0(n3636), .Y(n1935) );
AOI22X1TS U4695 ( .A0(n3723), .A1(add_subt_module_intDX[59]), .B0(
add_subt_module_DmP[59]), .B1(n3721), .Y(n3637) );
OAI21XLTS U4696 ( .A0(n4841), .A1(n4560), .B0(n3637), .Y(n1932) );
AOI22X1TS U4697 ( .A0(add_subt_module_DmP[27]), .A1(n3721), .B0(
add_subt_module_intDY[27]), .B1(n3703), .Y(n3638) );
OAI21XLTS U4698 ( .A0(n4943), .A1(n3659), .B0(n3638), .Y(n1776) );
AOI22X1TS U4699 ( .A0(n2991), .A1(add_subt_module_intDY[10]), .B0(
add_subt_module_DMP[10]), .B1(n3700), .Y(n3639) );
OAI21XLTS U4700 ( .A0(n4824), .A1(n3702), .B0(n3639), .Y(n1716) );
AOI22X1TS U4701 ( .A0(n2991), .A1(add_subt_module_intDY[6]), .B0(
add_subt_module_DMP[6]), .B1(n3721), .Y(n3640) );
OAI21XLTS U4702 ( .A0(n4920), .A1(n3702), .B0(n3640), .Y(n1712) );
AOI22X1TS U4703 ( .A0(n2991), .A1(add_subt_module_intDY[16]), .B0(
add_subt_module_DMP[16]), .B1(n4564), .Y(n3641) );
OAI21XLTS U4704 ( .A0(n4921), .A1(n3702), .B0(n3641), .Y(n1710) );
AOI22X1TS U4705 ( .A0(n2991), .A1(add_subt_module_intDY[7]), .B0(
add_subt_module_DMP[7]), .B1(n3700), .Y(n3642) );
OAI21XLTS U4706 ( .A0(n4906), .A1(n3702), .B0(n3642), .Y(n1717) );
AOI22X1TS U4707 ( .A0(n2991), .A1(add_subt_module_intDY[13]), .B0(
add_subt_module_DMP[13]), .B1(n3711), .Y(n3643) );
OAI21XLTS U4708 ( .A0(n4955), .A1(n3702), .B0(n3643), .Y(n1715) );
AOI22X1TS U4709 ( .A0(n2991), .A1(add_subt_module_intDY[5]), .B0(
add_subt_module_DMP[5]), .B1(n4564), .Y(n3644) );
OAI21XLTS U4710 ( .A0(n4907), .A1(n3702), .B0(n3644), .Y(n1713) );
AOI22X1TS U4711 ( .A0(n2991), .A1(add_subt_module_intDY[4]), .B0(
add_subt_module_DMP[4]), .B1(n3700), .Y(n3645) );
OAI21XLTS U4712 ( .A0(n4951), .A1(n3702), .B0(n3645), .Y(n1705) );
AOI22X1TS U4713 ( .A0(n2991), .A1(add_subt_module_intDY[1]), .B0(
add_subt_module_DMP[1]), .B1(n3818), .Y(n3646) );
OAI21XLTS U4714 ( .A0(n4922), .A1(n3702), .B0(n3646), .Y(n1709) );
AOI22X1TS U4715 ( .A0(add_subt_module_DmP[17]), .A1(n3721), .B0(
add_subt_module_intDY[17]), .B1(n3703), .Y(n3647) );
OAI21XLTS U4716 ( .A0(n4939), .A1(n3659), .B0(n3647), .Y(n1750) );
AOI22X1TS U4717 ( .A0(n3714), .A1(add_subt_module_DmP[32]), .B0(n2997), .B1(
n3703), .Y(n3648) );
OAI21XLTS U4718 ( .A0(n4949), .A1(n3659), .B0(n3648), .Y(n1747) );
AOI22X1TS U4719 ( .A0(add_subt_module_DmP[25]), .A1(n3818), .B0(
add_subt_module_intDY[25]), .B1(n3703), .Y(n3649) );
OAI21XLTS U4720 ( .A0(n4964), .A1(n3659), .B0(n3649), .Y(n1758) );
AOI22X1TS U4721 ( .A0(add_subt_module_DmP[18]), .A1(n3714), .B0(
add_subt_module_intDY[18]), .B1(n3703), .Y(n3650) );
OAI21XLTS U4722 ( .A0(n4958), .A1(n3657), .B0(n3650), .Y(n1761) );
AOI22X1TS U4723 ( .A0(add_subt_module_DmP[24]), .A1(n3714), .B0(n2998), .B1(
n3703), .Y(n3651) );
OAI21XLTS U4724 ( .A0(n4834), .A1(n3659), .B0(n3651), .Y(n1743) );
AOI22X1TS U4725 ( .A0(add_subt_module_DmP[45]), .A1(n3818), .B0(
add_subt_module_intDY[45]), .B1(n3703), .Y(n3652) );
OAI21XLTS U4726 ( .A0(n4962), .A1(n3657), .B0(n3652), .Y(n1855) );
AOI22X1TS U4727 ( .A0(n3723), .A1(add_subt_module_intDX[57]), .B0(
add_subt_module_DmP[57]), .B1(n4564), .Y(n3653) );
OAI21XLTS U4728 ( .A0(n3752), .A1(n4560), .B0(n3653), .Y(n1926) );
AOI22X1TS U4729 ( .A0(n3723), .A1(add_subt_module_intDX[58]), .B0(
add_subt_module_DmP[58]), .B1(n3818), .Y(n3654) );
AOI22X1TS U4730 ( .A0(add_subt_module_DmP[21]), .A1(n3714), .B0(
add_subt_module_intDY[21]), .B1(n3703), .Y(n3655) );
OAI21XLTS U4731 ( .A0(n4938), .A1(n3659), .B0(n3655), .Y(n1764) );
AOI22X1TS U4732 ( .A0(add_subt_module_DmP[29]), .A1(n3818), .B0(
add_subt_module_intDY[29]), .B1(n3703), .Y(n3656) );
OAI21XLTS U4733 ( .A0(n4948), .A1(n3657), .B0(n3656), .Y(n1768) );
AOI22X1TS U4734 ( .A0(add_subt_module_DmP[33]), .A1(n3721), .B0(
add_subt_module_intDY[33]), .B1(n3703), .Y(n3658) );
OAI21XLTS U4735 ( .A0(n4915), .A1(n3659), .B0(n3658), .Y(n1754) );
AOI22X1TS U4736 ( .A0(n3712), .A1(add_subt_module_intDY[14]), .B0(
add_subt_module_DMP[14]), .B1(n3711), .Y(n3660) );
OAI21XLTS U4737 ( .A0(n4828), .A1(n4560), .B0(n3660), .Y(n1726) );
AOI22X1TS U4738 ( .A0(n3712), .A1(add_subt_module_intDY[34]), .B0(
add_subt_module_DMP[34]), .B1(n3700), .Y(n3661) );
OAI21XLTS U4739 ( .A0(n4832), .A1(n3702), .B0(n3661), .Y(n1722) );
AOI22X1TS U4740 ( .A0(n3712), .A1(n2995), .B0(add_subt_module_DMP[22]), .B1(
n3700), .Y(n3662) );
OAI21XLTS U4741 ( .A0(n4827), .A1(n3699), .B0(n3662), .Y(n1731) );
AOI22X1TS U4742 ( .A0(n3712), .A1(add_subt_module_intDY[27]), .B0(
add_subt_module_DMP[27]), .B1(n3711), .Y(n3663) );
OAI21XLTS U4743 ( .A0(n4943), .A1(n3699), .B0(n3663), .Y(n1775) );
AOI22X1TS U4744 ( .A0(n3712), .A1(n2997), .B0(add_subt_module_DMP[32]), .B1(
n3700), .Y(n3664) );
OAI21XLTS U4745 ( .A0(n4949), .A1(n3699), .B0(n3664), .Y(n1746) );
AOI22X1TS U4746 ( .A0(n3712), .A1(add_subt_module_intDY[17]), .B0(
add_subt_module_DMP[17]), .B1(n3711), .Y(n3665) );
OAI21XLTS U4747 ( .A0(n4939), .A1(n3699), .B0(n3665), .Y(n1729) );
AOI22X1TS U4748 ( .A0(n3712), .A1(add_subt_module_intDY[28]), .B0(
add_subt_module_DMP[28]), .B1(n4564), .Y(n3666) );
OAI21XLTS U4749 ( .A0(n4930), .A1(n3699), .B0(n3666), .Y(n1736) );
AOI22X1TS U4750 ( .A0(n3712), .A1(add_subt_module_intDY[26]), .B0(
add_subt_module_DMP[26]), .B1(n4564), .Y(n3667) );
AOI22X1TS U4751 ( .A0(n3712), .A1(add_subt_module_intDY[25]), .B0(
add_subt_module_DMP[25]), .B1(n3711), .Y(n3668) );
OAI21XLTS U4752 ( .A0(n4964), .A1(n3699), .B0(n3668), .Y(n1757) );
AOI22X1TS U4753 ( .A0(n3712), .A1(add_subt_module_intDY[18]), .B0(
add_subt_module_DMP[18]), .B1(n3700), .Y(n3669) );
OAI21XLTS U4754 ( .A0(n4958), .A1(n3699), .B0(n3669), .Y(n1728) );
AOI22X1TS U4755 ( .A0(n3712), .A1(n2998), .B0(add_subt_module_DMP[24]), .B1(
n4564), .Y(n3670) );
OAI21XLTS U4756 ( .A0(n4834), .A1(n3699), .B0(n3670), .Y(n1730) );
AOI22X1TS U4757 ( .A0(n3712), .A1(add_subt_module_intDY[12]), .B0(
add_subt_module_DMP[12]), .B1(n3711), .Y(n3671) );
OAI21XLTS U4758 ( .A0(n4950), .A1(n3699), .B0(n3671), .Y(n1718) );
INVX2TS U4759 ( .A(n3672), .Y(n3681) );
INVX2TS U4760 ( .A(add_subt_module_Exp_Operation_Module_Data_S[10]), .Y(
n3680) );
CLKAND2X2TS U4761 ( .A(add_subt_module_Exp_Operation_Module_Data_S[0]), .B(
n3674), .Y(n3974) );
AND4X1TS U4762 ( .A(add_subt_module_Exp_Operation_Module_Data_S[3]), .B(
add_subt_module_Exp_Operation_Module_Data_S[2]), .C(
add_subt_module_Exp_Operation_Module_Data_S[1]), .D(n3974), .Y(n3675)
);
AND4X1TS U4763 ( .A(add_subt_module_Exp_Operation_Module_Data_S[6]), .B(
add_subt_module_Exp_Operation_Module_Data_S[5]), .C(
add_subt_module_Exp_Operation_Module_Data_S[4]), .D(n3675), .Y(n3676)
);
NAND4XLTS U4764 ( .A(add_subt_module_Exp_Operation_Module_Data_S[9]), .B(
add_subt_module_Exp_Operation_Module_Data_S[8]), .C(
add_subt_module_Exp_Operation_Module_Data_S[7]), .D(n3676), .Y(n3679)
);
NAND2X1TS U4765 ( .A(n3677), .B(overflow_flag), .Y(n3678) );
OAI31X1TS U4766 ( .A0(n3681), .A1(n3680), .A2(n3679), .B0(n3678), .Y(n2651)
);
AOI22X1TS U4767 ( .A0(n3712), .A1(add_subt_module_intDY[23]), .B0(
add_subt_module_DMP[23]), .B1(n4564), .Y(n3682) );
OAI21XLTS U4768 ( .A0(n4924), .A1(n3702), .B0(n3682), .Y(n1723) );
AOI22X1TS U4769 ( .A0(n3712), .A1(add_subt_module_intDY[31]), .B0(
add_subt_module_DMP[31]), .B1(n3711), .Y(n3683) );
AOI22X1TS U4770 ( .A0(n3712), .A1(add_subt_module_intDY[29]), .B0(
add_subt_module_DMP[29]), .B1(n3711), .Y(n3684) );
OAI21XLTS U4771 ( .A0(n4948), .A1(n3699), .B0(n3684), .Y(n1767) );
AOI22X1TS U4772 ( .A0(n3712), .A1(add_subt_module_intDY[33]), .B0(
add_subt_module_DMP[33]), .B1(n3711), .Y(n3685) );
AOI22X1TS U4773 ( .A0(n2991), .A1(add_subt_module_intDX[62]), .B0(
add_subt_module_DmP[62]), .B1(n3700), .Y(n3686) );
OAI21XLTS U4774 ( .A0(n4913), .A1(n4560), .B0(n3686), .Y(n1941) );
AOI22X1TS U4775 ( .A0(n2991), .A1(add_subt_module_intDY[19]), .B0(
add_subt_module_DMP[19]), .B1(n3700), .Y(n3687) );
OAI21XLTS U4776 ( .A0(n4839), .A1(n4560), .B0(n3687), .Y(n1721) );
AOI22X1TS U4777 ( .A0(n3723), .A1(add_subt_module_intDX[61]), .B0(
add_subt_module_DmP[61]), .B1(n3700), .Y(n3688) );
OAI21XLTS U4778 ( .A0(n4945), .A1(n4560), .B0(n3688), .Y(n1938) );
AOI22X1TS U4779 ( .A0(n2991), .A1(add_subt_module_intDY[9]), .B0(
add_subt_module_DMP[9]), .B1(n3711), .Y(n3689) );
OAI21XLTS U4780 ( .A0(n4931), .A1(n3702), .B0(n3689), .Y(n1711) );
AOI22X1TS U4781 ( .A0(n2991), .A1(n2996), .B0(add_subt_module_DMP[30]), .B1(
n3700), .Y(n3690) );
OAI21XLTS U4782 ( .A0(n4952), .A1(n3699), .B0(n3690), .Y(n1724) );
AOI22X1TS U4783 ( .A0(n2991), .A1(add_subt_module_intDY[2]), .B0(
add_subt_module_DMP[2]), .B1(n3721), .Y(n3691) );
AOI22X1TS U4784 ( .A0(n2991), .A1(add_subt_module_intDY[20]), .B0(
add_subt_module_DMP[20]), .B1(n3700), .Y(n3692) );
OAI21XLTS U4785 ( .A0(n4940), .A1(n3702), .B0(n3692), .Y(n1714) );
AOI22X1TS U4786 ( .A0(n2991), .A1(add_subt_module_intDY[50]), .B0(
add_subt_module_DMP[50]), .B1(n4564), .Y(n3693) );
OAI21XLTS U4787 ( .A0(n4830), .A1(n3702), .B0(n3693), .Y(n1707) );
AOI22X1TS U4788 ( .A0(n2991), .A1(add_subt_module_intDY[11]), .B0(
add_subt_module_DMP[11]), .B1(n4564), .Y(n3694) );
OAI21XLTS U4789 ( .A0(n4916), .A1(n3702), .B0(n3694), .Y(n1719) );
AOI22X1TS U4790 ( .A0(n2991), .A1(add_subt_module_intDY[8]), .B0(
add_subt_module_DMP[8]), .B1(n4564), .Y(n3695) );
OAI21XLTS U4791 ( .A0(n4959), .A1(n3699), .B0(n3695), .Y(n1720) );
AOI22X1TS U4792 ( .A0(n2991), .A1(add_subt_module_intDY[15]), .B0(
add_subt_module_DMP[15]), .B1(n3700), .Y(n3696) );
OAI21XLTS U4793 ( .A0(n4933), .A1(n3702), .B0(n3696), .Y(n1725) );
AOI22X1TS U4794 ( .A0(n2991), .A1(add_subt_module_intDY[21]), .B0(
add_subt_module_DMP[21]), .B1(n4564), .Y(n3697) );
OAI21XLTS U4795 ( .A0(n4938), .A1(n3699), .B0(n3697), .Y(n1727) );
AOI22X1TS U4796 ( .A0(add_subt_module_DmP[13]), .A1(n3818), .B0(
add_subt_module_intDX[13]), .B1(n3723), .Y(n3698) );
OAI21XLTS U4797 ( .A0(n4935), .A1(n3699), .B0(n3698), .Y(n1848) );
AOI22X1TS U4798 ( .A0(n2991), .A1(add_subt_module_intDY[3]), .B0(
add_subt_module_DMP[3]), .B1(n4564), .Y(n3701) );
OAI21XLTS U4799 ( .A0(n4960), .A1(n3702), .B0(n3701), .Y(n1708) );
AOI222X1TS U4800 ( .A0(n3723), .A1(add_subt_module_intDX[41]), .B0(
add_subt_module_DmP[41]), .B1(n4564), .C0(add_subt_module_intDY[41]),
.C1(n3703), .Y(n3704) );
INVX2TS U4801 ( .A(n3704), .Y(n1814) );
INVX3TS U4802 ( .A(n3703), .Y(n3725) );
AOI22X1TS U4803 ( .A0(add_subt_module_DmP[51]), .A1(n3818), .B0(
add_subt_module_intDX[51]), .B1(n3723), .Y(n3705) );
OAI21XLTS U4804 ( .A0(n5005), .A1(n3725), .B0(n3705), .Y(n1905) );
AOI22X1TS U4805 ( .A0(n3712), .A1(add_subt_module_intDY[36]), .B0(
add_subt_module_DMP[36]), .B1(n3711), .Y(n3706) );
OAI21XLTS U4806 ( .A0(n4914), .A1(n3725), .B0(n3706), .Y(n1782) );
AOI22X1TS U4807 ( .A0(n3723), .A1(add_subt_module_intDX[52]), .B0(
add_subt_module_DmP[52]), .B1(n3818), .Y(n3707) );
AOI22X1TS U4808 ( .A0(n3723), .A1(add_subt_module_intDY[48]), .B0(
add_subt_module_DMP[48]), .B1(n4564), .Y(n3708) );
OAI21XLTS U4809 ( .A0(n4953), .A1(n3725), .B0(n3708), .Y(n1898) );
AOI22X1TS U4810 ( .A0(n3719), .A1(add_subt_module_intDY[49]), .B0(
add_subt_module_DMP[49]), .B1(n4564), .Y(n3709) );
OAI21XLTS U4811 ( .A0(n4932), .A1(n3725), .B0(n3709), .Y(n1878) );
AOI22X1TS U4812 ( .A0(n3719), .A1(add_subt_module_intDY[46]), .B0(
add_subt_module_DMP[46]), .B1(n3818), .Y(n3710) );
OAI21XLTS U4813 ( .A0(n4927), .A1(n3725), .B0(n3710), .Y(n1874) );
AOI22X1TS U4814 ( .A0(n3712), .A1(add_subt_module_intDY[35]), .B0(
add_subt_module_DMP[35]), .B1(n3711), .Y(n3713) );
OAI21XLTS U4815 ( .A0(n4963), .A1(n3725), .B0(n3713), .Y(n1789) );
AOI22X1TS U4816 ( .A0(add_subt_module_DmP[48]), .A1(n3714), .B0(
add_subt_module_intDX[48]), .B1(n3723), .Y(n3715) );
OAI21XLTS U4817 ( .A0(n5004), .A1(n3725), .B0(n3715), .Y(n1899) );
AOI22X1TS U4818 ( .A0(n3723), .A1(add_subt_module_intDX[56]), .B0(
add_subt_module_DmP[56]), .B1(n3721), .Y(n3716) );
OAI21XLTS U4819 ( .A0(n4925), .A1(n3725), .B0(n3716), .Y(n1923) );
AOI22X1TS U4820 ( .A0(n3723), .A1(add_subt_module_intDX[53]), .B0(
add_subt_module_DmP[53]), .B1(n3818), .Y(n3717) );
OAI21XLTS U4821 ( .A0(n4835), .A1(n3725), .B0(n3717), .Y(n1914) );
AOI22X1TS U4822 ( .A0(n3719), .A1(add_subt_module_intDX[55]), .B0(
add_subt_module_DmP[55]), .B1(n3721), .Y(n3718) );
OAI21XLTS U4823 ( .A0(n4905), .A1(n3725), .B0(n3718), .Y(n1920) );
AOI22X1TS U4824 ( .A0(n3719), .A1(add_subt_module_intDY[47]), .B0(
add_subt_module_DMP[47]), .B1(n3700), .Y(n3720) );
AOI22X1TS U4825 ( .A0(n3723), .A1(add_subt_module_intDX[54]), .B0(
add_subt_module_DmP[54]), .B1(n3700), .Y(n3722) );
OAI21XLTS U4826 ( .A0(n4947), .A1(n3725), .B0(n3722), .Y(n1917) );
AOI22X1TS U4827 ( .A0(add_subt_module_DmP[0]), .A1(n3721), .B0(
add_subt_module_intDX[0]), .B1(n3723), .Y(n3724) );
OAI21XLTS U4828 ( .A0(n4961), .A1(n3725), .B0(n3724), .Y(n1908) );
AOI22X1TS U4829 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[5]),
.B0(n3739), .B1(n3726), .Y(n3727) );
AOI22X1TS U4830 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[6]),
.B0(n3739), .B1(n3728), .Y(n3729) );
OAI21XLTS U4831 ( .A0(n2989), .A1(n3742), .B0(n3729), .Y(n2541) );
AOI22X1TS U4832 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[4]),
.B0(n3739), .B1(n3730), .Y(n3731) );
OAI21XLTS U4833 ( .A0(n2979), .A1(n3742), .B0(n3731), .Y(n2539) );
AOI22X1TS U4834 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[3]),
.B0(n3739), .B1(n3732), .Y(n3733) );
OAI21XLTS U4835 ( .A0(n2975), .A1(n3742), .B0(n3733), .Y(n2538) );
AOI22X1TS U4836 ( .A0(n3740), .A1(add_subt_module_Sgf_normalized_result[2]),
.B0(n3739), .B1(n3734), .Y(n3735) );
OAI21XLTS U4837 ( .A0(n2976), .A1(n3742), .B0(n3735), .Y(n2537) );
AOI22X1TS U4838 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[1]),
.B0(n3739), .B1(n3736), .Y(n3737) );
OAI21XLTS U4839 ( .A0(n2977), .A1(n3742), .B0(n3737), .Y(n2536) );
AOI22X1TS U4840 ( .A0(n4016), .A1(add_subt_module_Sgf_normalized_result[0]),
.B0(n3739), .B1(n3738), .Y(n3741) );
OAI21XLTS U4841 ( .A0(n2988), .A1(n3742), .B0(n3741), .Y(n2535) );
OAI22X1TS U4842 ( .A0(add_subt_module_Sgf_normalized_result[1]), .A1(
add_subt_module_Sgf_normalized_result[0]), .B0(r_mode[1]), .B1(
r_mode[0]), .Y(n3743) );
INVX2TS U4843 ( .A(n4321), .Y(n3821) );
AOI22X1TS U4844 ( .A0(n4952), .A1(n2996), .B0(n4828), .B1(
add_subt_module_intDY[14]), .Y(n3744) );
AOI221X1TS U4845 ( .A0(add_subt_module_intDX[13]), .A1(n4935), .B0(n4955),
.B1(add_subt_module_intDY[13]), .C0(n3745), .Y(n3760) );
OAI22X1TS U4846 ( .A0(n4949), .A1(n2997), .B0(n4833), .B1(
add_subt_module_intDY[38]), .Y(n3746) );
AOI221X1TS U4847 ( .A0(n4949), .A1(n2997), .B0(add_subt_module_intDY[38]),
.B1(n4833), .C0(n3746), .Y(n3759) );
OAI22X1TS U4848 ( .A0(n4951), .A1(add_subt_module_intDY[4]), .B0(n4835),
.B1(add_subt_module_intDX[53]), .Y(n3747) );
AOI221X1TS U4849 ( .A0(n4951), .A1(add_subt_module_intDY[4]), .B0(
add_subt_module_intDX[53]), .B1(n4835), .C0(n3747), .Y(n3758) );
AOI22X1TS U4850 ( .A0(n4922), .A1(add_subt_module_intDY[1]), .B0(n4945),
.B1(add_subt_module_intDX[61]), .Y(n3748) );
AOI22X1TS U4851 ( .A0(n4919), .A1(add_subt_module_intDY[39]), .B0(n4924),
.B1(add_subt_module_intDY[23]), .Y(n3749) );
AOI22X1TS U4852 ( .A0(n4916), .A1(add_subt_module_intDY[11]), .B0(n4926),
.B1(add_subt_module_intDX[52]), .Y(n3750) );
AOI22X1TS U4853 ( .A0(n3752), .A1(add_subt_module_intDX[57]), .B0(n4929),
.B1(add_subt_module_intDY[37]), .Y(n3751) );
OAI221XLTS U4854 ( .A0(n3752), .A1(add_subt_module_intDX[57]), .B0(n4929),
.B1(add_subt_module_intDY[37]), .C0(n3751), .Y(n3753) );
NOR4X1TS U4855 ( .A(n3756), .B(n3755), .C(n3754), .D(n3753), .Y(n3757) );
NAND4XLTS U4856 ( .A(n3760), .B(n3759), .C(n3758), .D(n3757), .Y(n3817) );
OAI22X1TS U4857 ( .A0(n4947), .A1(add_subt_module_intDX[54]), .B0(n4834),
.B1(n2998), .Y(n3761) );
AOI221X1TS U4858 ( .A0(n4947), .A1(add_subt_module_intDX[54]), .B0(n2998),
.B1(n4834), .C0(n3761), .Y(n3768) );
OAI22X1TS U4859 ( .A0(n4962), .A1(add_subt_module_intDY[45]), .B0(n4954),
.B1(add_subt_module_intDY[51]), .Y(n3762) );
AOI221X1TS U4860 ( .A0(n4962), .A1(add_subt_module_intDY[45]), .B0(
add_subt_module_intDY[51]), .B1(n4954), .C0(n3762), .Y(n3767) );
OAI22X1TS U4861 ( .A0(n4841), .A1(add_subt_module_intDX[59]), .B0(n4953),
.B1(add_subt_module_intDY[48]), .Y(n3763) );
AOI221X1TS U4862 ( .A0(n4841), .A1(add_subt_module_intDX[59]), .B0(
add_subt_module_intDY[48]), .B1(n4953), .C0(n3763), .Y(n3766) );
OAI22X1TS U4863 ( .A0(n4950), .A1(add_subt_module_intDY[12]), .B0(n4958),
.B1(add_subt_module_intDY[18]), .Y(n3764) );
NAND4XLTS U4864 ( .A(n3768), .B(n3767), .C(n3766), .D(n3765), .Y(n3816) );
OAI22X1TS U4865 ( .A0(n4840), .A1(add_subt_module_intDX[60]), .B0(n4960),
.B1(add_subt_module_intDY[3]), .Y(n3769) );
AOI221X1TS U4866 ( .A0(n4840), .A1(add_subt_module_intDX[60]), .B0(
add_subt_module_intDY[3]), .B1(n4960), .C0(n3769), .Y(n3776) );
OAI22X1TS U4867 ( .A0(n4963), .A1(add_subt_module_intDY[35]), .B0(n4959),
.B1(add_subt_module_intDY[8]), .Y(n3770) );
OAI22X1TS U4868 ( .A0(n4948), .A1(add_subt_module_intDY[29]), .B0(n4961),
.B1(add_subt_module_intDX[0]), .Y(n3771) );
OAI22X1TS U4869 ( .A0(n4964), .A1(add_subt_module_intDY[25]), .B0(n4946),
.B1(add_subt_module_intDY[2]), .Y(n3772) );
NAND4XLTS U4870 ( .A(n3776), .B(n3775), .C(n3774), .D(n3773), .Y(n3815) );
AOI22X1TS U4871 ( .A0(n4921), .A1(add_subt_module_intDY[16]), .B0(n4923),
.B1(add_subt_module_intDY[43]), .Y(n3777) );
AOI22X1TS U4872 ( .A0(n4826), .A1(add_subt_module_intDY[31]), .B0(n4925),
.B1(add_subt_module_intDX[56]), .Y(n3778) );
OAI221XLTS U4873 ( .A0(n4826), .A1(add_subt_module_intDY[31]), .B0(n4925),
.B1(add_subt_module_intDX[56]), .C0(n3778), .Y(n3783) );
AOI22X1TS U4874 ( .A0(n4839), .A1(add_subt_module_intDY[19]), .B0(n4907),
.B1(add_subt_module_intDY[5]), .Y(n3779) );
AOI22X1TS U4875 ( .A0(n4940), .A1(add_subt_module_intDY[20]), .B0(n4830),
.B1(add_subt_module_intDY[50]), .Y(n3780) );
NOR4X1TS U4876 ( .A(n3784), .B(n3783), .C(n3782), .D(n3781), .Y(n3813) );
AOI22X1TS U4877 ( .A0(n4917), .A1(add_subt_module_intDY[47]), .B0(n4824),
.B1(add_subt_module_intDY[10]), .Y(n3785) );
AOI22X1TS U4878 ( .A0(n4932), .A1(add_subt_module_intDY[49]), .B0(n4930),
.B1(add_subt_module_intDY[28]), .Y(n3786) );
AOI22X1TS U4879 ( .A0(n4914), .A1(add_subt_module_intDY[36]), .B0(n3788),
.B1(add_subt_module_intDX[58]), .Y(n3787) );
AOI22X1TS U4880 ( .A0(n4918), .A1(add_subt_module_intDY[44]), .B0(n4829),
.B1(add_subt_module_intDY[26]), .Y(n3789) );
NOR4X1TS U4881 ( .A(n3793), .B(n3792), .C(n3791), .D(n3790), .Y(n3812) );
AOI22X1TS U4882 ( .A0(n4905), .A1(add_subt_module_intDX[55]), .B0(n4832),
.B1(add_subt_module_intDY[34]), .Y(n3794) );
AOI22X1TS U4883 ( .A0(n4827), .A1(n2995), .B0(n4928), .B1(
add_subt_module_intDY[40]), .Y(n3795) );
AOI22X1TS U4884 ( .A0(n4920), .A1(add_subt_module_intDY[6]), .B0(n4910),
.B1(add_subt_module_intDY[41]), .Y(n3796) );
AOI22X1TS U4885 ( .A0(n4938), .A1(add_subt_module_intDY[21]), .B0(n4927),
.B1(add_subt_module_intDY[46]), .Y(n3797) );
NOR4X1TS U4886 ( .A(n3801), .B(n3800), .C(n3799), .D(n3798), .Y(n3811) );
AOI22X1TS U4887 ( .A0(n4831), .A1(add_subt_module_intDY[42]), .B0(n4931),
.B1(add_subt_module_intDY[9]), .Y(n3802) );
AOI22X1TS U4888 ( .A0(n4906), .A1(add_subt_module_intDY[7]), .B0(n4943),
.B1(add_subt_module_intDY[27]), .Y(n3803) );
AOI22X1TS U4889 ( .A0(n4915), .A1(add_subt_module_intDY[33]), .B0(n4913),
.B1(add_subt_module_intDX[62]), .Y(n3804) );
AOI22X1TS U4890 ( .A0(n4933), .A1(add_subt_module_intDY[15]), .B0(n4939),
.B1(add_subt_module_intDY[17]), .Y(n3805) );
NOR4X1TS U4891 ( .A(n3809), .B(n3808), .C(n3807), .D(n3806), .Y(n3810) );
NAND4XLTS U4892 ( .A(n3813), .B(n3812), .C(n3811), .D(n3810), .Y(n3814) );
XNOR2X1TS U4893 ( .A(add_subt_module_intAS), .B(add_subt_module_intDY[63]),
.Y(n4561) );
XNOR2X1TS U4894 ( .A(n4561), .B(add_subt_module_intDX[63]), .Y(n3863) );
NAND2X1TS U4895 ( .A(n4559), .B(n3863), .Y(n4311) );
NOR2X1TS U4896 ( .A(n3714), .B(n4311), .Y(n4326) );
INVX2TS U4897 ( .A(n3005), .Y(n4029) );
NOR4X1TS U4898 ( .A(n4312), .B(n4326), .C(n4462), .D(n4029), .Y(n3820) );
NOR2X1TS U4899 ( .A(n4297), .B(n3865), .Y(n4295) );
NAND4X1TS U4900 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(
add_subt_module_FS_Module_state_reg[1]), .C(n4302), .D(n4330), .Y(
n4328) );
OAI21X1TS U4901 ( .A0(n4295), .A1(n1959), .B0(n4328), .Y(n4314) );
OAI21XLTS U4902 ( .A0(n4317), .A1(n4314), .B0(
add_subt_module_FS_Module_state_reg[3]), .Y(n3819) );
OAI211XLTS U4903 ( .A0(n4322), .A1(n3821), .B0(n3820), .C0(n3819), .Y(n2930)
);
NOR2X1TS U4904 ( .A(add_subt_module_Add_Subt_result[10]), .B(n4965), .Y(
n3990) );
NOR2X1TS U4905 ( .A(add_subt_module_Add_Subt_result[16]), .B(
add_subt_module_Add_Subt_result[17]), .Y(n3825) );
NOR2X1TS U4906 ( .A(add_subt_module_Add_Subt_result[20]), .B(
add_subt_module_Add_Subt_result[19]), .Y(n3852) );
OR4X2TS U4907 ( .A(add_subt_module_Add_Subt_result[52]), .B(n2993), .C(
add_subt_module_Add_Subt_result[54]), .D(
add_subt_module_Add_Subt_result[51]), .Y(n3964) );
NAND2X1TS U4908 ( .A(n4443), .B(n4850), .Y(n3997) );
NAND2X1TS U4909 ( .A(n4809), .B(n3952), .Y(n3948) );
NOR2X1TS U4910 ( .A(add_subt_module_Add_Subt_result[40]), .B(
add_subt_module_Add_Subt_result[39]), .Y(n3853) );
NAND2BX1TS U4911 ( .AN(n3948), .B(n3853), .Y(n4441) );
NOR2X1TS U4912 ( .A(add_subt_module_Add_Subt_result[37]), .B(
add_subt_module_Add_Subt_result[38]), .Y(n3977) );
NAND2X1TS U4913 ( .A(n3822), .B(n3977), .Y(n3844) );
NAND2X1TS U4914 ( .A(n2987), .B(n4870), .Y(n3967) );
NOR3X1TS U4915 ( .A(add_subt_module_Add_Subt_result[32]), .B(
add_subt_module_Add_Subt_result[31]), .C(n3967), .Y(n4001) );
NAND2X1TS U4916 ( .A(n4001), .B(n4816), .Y(n3961) );
NOR3X1TS U4917 ( .A(add_subt_module_Add_Subt_result[29]), .B(
add_subt_module_Add_Subt_result[28]), .C(n3961), .Y(n3850) );
NOR2X1TS U4918 ( .A(add_subt_module_Add_Subt_result[26]), .B(n3823), .Y(
n3978) );
NAND2X1TS U4919 ( .A(n3978), .B(n4880), .Y(n3845) );
NOR3BX1TS U4920 ( .AN(n3963), .B(add_subt_module_Add_Subt_result[23]), .C(
n2992), .Y(n3946) );
NAND2BX1TS U4921 ( .AN(add_subt_module_Add_Subt_result[21]), .B(n3946), .Y(
n3954) );
INVX2TS U4922 ( .A(n3954), .Y(n3951) );
NAND2X1TS U4923 ( .A(n3852), .B(n3951), .Y(n3824) );
NAND2X1TS U4924 ( .A(n3825), .B(n4449), .Y(n3832) );
NOR2X1TS U4925 ( .A(add_subt_module_Add_Subt_result[12]), .B(
add_subt_module_Add_Subt_result[11]), .Y(n3831) );
INVX2TS U4926 ( .A(n4005), .Y(n3989) );
OAI21X1TS U4927 ( .A0(add_subt_module_Add_Subt_result[13]), .A1(n4843), .B0(
n4813), .Y(n3971) );
NAND2BXLTS U4928 ( .AN(n3971), .B(n3972), .Y(n3957) );
AOI21X1TS U4929 ( .A0(n4936), .A1(n4836), .B0(n3957), .Y(n3827) );
AOI31XLTS U4930 ( .A0(n3825), .A1(n4999), .A2(n4813), .B0(n3824), .Y(n3826)
);
AOI211XLTS U4931 ( .A0(n3990), .A1(n3989), .B0(n3827), .C0(n3826), .Y(n3839)
);
NAND3X1TS U4932 ( .A(n3989), .B(n4965), .C(n4836), .Y(n3834) );
NAND2X1TS U4933 ( .A(n3955), .B(n3830), .Y(n3986) );
NOR3X1TS U4934 ( .A(add_subt_module_Add_Subt_result[4]), .B(
add_subt_module_Add_Subt_result[3]), .C(n3986), .Y(n3828) );
NAND2X1TS U4935 ( .A(n3828), .B(n4982), .Y(n4452) );
NOR3X1TS U4936 ( .A(add_subt_module_Add_Subt_result[1]), .B(n5003), .C(n4452), .Y(n3849) );
INVX2TS U4937 ( .A(n3955), .Y(n3829) );
AOI21X1TS U4938 ( .A0(n3830), .A1(n4982), .B0(n3829), .Y(n3836) );
NAND2X1TS U4939 ( .A(n4971), .B(n4837), .Y(n3985) );
OR4X2TS U4940 ( .A(add_subt_module_Add_Subt_result[13]), .B(
add_subt_module_Add_Subt_result[14]), .C(n3831), .D(n3832), .Y(n3833)
);
NAND2BXLTS U4941 ( .AN(n3832), .B(add_subt_module_Add_Subt_result[15]), .Y(
n4444) );
OAI211X1TS U4942 ( .A0(n3835), .A1(n3834), .B0(n3833), .C0(n4444), .Y(n3859)
);
NAND2X1TS U4943 ( .A(n4302), .B(n4818), .Y(n4436) );
OAI21X1TS U4944 ( .A0(n4983), .A1(n4452), .B0(n4455), .Y(n3982) );
NOR4X1TS U4945 ( .A(n3849), .B(n3836), .C(n3859), .D(n3982), .Y(n3838) );
OAI2BB1X1TS U4946 ( .A0N(n3839), .A1N(n3838), .B0(n3837), .Y(n3840) );
INVX2TS U4947 ( .A(n3840), .Y(n2589) );
NOR2XLTS U4948 ( .A(n2993), .B(add_subt_module_Add_Subt_result[54]), .Y(
n3858) );
NOR2XLTS U4949 ( .A(add_subt_module_Add_Subt_result[46]), .B(
add_subt_module_Add_Subt_result[45]), .Y(n3841) );
NOR2XLTS U4950 ( .A(add_subt_module_Add_Subt_result[51]), .B(
add_subt_module_Add_Subt_result[52]), .Y(n3842) );
OAI31X1TS U4951 ( .A0(add_subt_module_Add_Subt_result[50]), .A1(
add_subt_module_Add_Subt_result[49]), .A2(n3843), .B0(n3842), .Y(n3857) );
NOR2XLTS U4952 ( .A(add_subt_module_Add_Subt_result[32]), .B(
add_subt_module_Add_Subt_result[31]), .Y(n3847) );
INVX2TS U4953 ( .A(n3844), .Y(n4438) );
OAI21XLTS U4954 ( .A0(add_subt_module_Add_Subt_result[36]), .A1(
add_subt_module_Add_Subt_result[35]), .B0(n4438), .Y(n3846) );
NAND2BXLTS U4955 ( .AN(n3845), .B(add_subt_module_Add_Subt_result[24]), .Y(
n3996) );
OAI211XLTS U4956 ( .A0(n3847), .A1(n3967), .B0(n3846), .C0(n3996), .Y(n3848)
);
AOI211X1TS U4957 ( .A0(n3850), .A1(n2994), .B0(n3849), .C0(n3848), .Y(n3851)
);
NAND2X1TS U4958 ( .A(n3963), .B(add_subt_module_Add_Subt_result[23]), .Y(
n3994) );
OAI211X1TS U4959 ( .A0(n3852), .A1(n3954), .B0(n3851), .C0(n3994), .Y(n3988)
);
NAND2BXLTS U4960 ( .AN(n3961), .B(add_subt_module_Add_Subt_result[28]), .Y(
n3968) );
NAND4BXLTS U4961 ( .AN(n3853), .B(n3854), .C(n4809), .D(n4970), .Y(n3855) );
NAND2X1TS U4962 ( .A(add_subt_module_Add_Subt_result[43]), .B(n3854), .Y(
n3992) );
OAI211XLTS U4963 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n3968),
.B0(n3855), .C0(n3992), .Y(n3856) );
INVX2TS U4964 ( .A(n4455), .Y(n4006) );
NOR2BX1TS U4965 ( .AN(n4006), .B(add_subt_module_LZA_output[1]), .Y(n3860)
);
INVX2TS U4966 ( .A(add_subt_module_FSM_selector_D), .Y(n3927) );
CLKINVX6TS U4967 ( .A(n3927), .Y(n4020) );
NOR2BX2TS U4968 ( .AN(n3863), .B(n4009), .Y(n3892) );
BUFX3TS U4969 ( .A(n3892), .Y(n3894) );
INVX2TS U4970 ( .A(n3868), .Y(n3867) );
NAND2X1TS U4971 ( .A(d_ff1_operation_out), .B(d_ff1_shift_region_flag_out[0]), .Y(n4538) );
OAI21XLTS U4972 ( .A0(d_ff1_operation_out), .A1(
d_ff1_shift_region_flag_out[0]), .B0(n4538), .Y(n3866) );
XNOR2X1TS U4973 ( .A(d_ff1_shift_region_flag_out[1]), .B(n3866), .Y(n4429)
);
NOR2X1TS U4974 ( .A(cordic_FSM_state_reg[1]), .B(beg_fsm_cordic), .Y(n4304)
);
AOI22X1TS U4975 ( .A0(cordic_FSM_state_reg[1]), .A1(n4890), .B0(
cordic_FSM_state_reg[0]), .B1(n4819), .Y(n4349) );
OAI31XLTS U4976 ( .A0(cordic_FSM_state_reg[3]), .A1(n4304), .A2(n4349), .B0(
n3869), .Y(cordic_FSM_state_next_1_) );
NOR2BX1TS U4977 ( .AN(add_subt_module_Sgf_normalized_result[54]), .B(n4009),
.Y(n3870) );
XOR2X1TS U4978 ( .A(n3894), .B(n3870), .Y(DP_OP_95J138_125_7728_n60) );
INVX4TS U4979 ( .A(n3927), .Y(n3901) );
NOR2XLTS U4980 ( .A(n5001), .B(n4009), .Y(n3871) );
XOR2X1TS U4981 ( .A(n3894), .B(n3871), .Y(DP_OP_95J138_125_7728_n61) );
NOR2XLTS U4982 ( .A(n4991), .B(n4009), .Y(n3872) );
XOR2X1TS U4983 ( .A(n3894), .B(n3872), .Y(DP_OP_95J138_125_7728_n62) );
NOR2XLTS U4984 ( .A(n4992), .B(n4009), .Y(n3873) );
XOR2X1TS U4985 ( .A(n3894), .B(n3873), .Y(DP_OP_95J138_125_7728_n63) );
XOR2X1TS U4986 ( .A(n3894), .B(n3874), .Y(DP_OP_95J138_125_7728_n64) );
NOR2XLTS U4987 ( .A(n4966), .B(n4009), .Y(n3875) );
XOR2X1TS U4988 ( .A(n3894), .B(n3875), .Y(DP_OP_95J138_125_7728_n65) );
NOR2XLTS U4989 ( .A(n4967), .B(n4009), .Y(n3876) );
XOR2X1TS U4990 ( .A(n3894), .B(n3876), .Y(DP_OP_95J138_125_7728_n66) );
INVX4TS U4991 ( .A(n3927), .Y(n3925) );
NOR2XLTS U4992 ( .A(n4956), .B(n4008), .Y(n3877) );
XOR2X1TS U4993 ( .A(n3894), .B(n3877), .Y(DP_OP_95J138_125_7728_n67) );
NOR2XLTS U4994 ( .A(n4957), .B(n4008), .Y(n3878) );
XOR2X1TS U4995 ( .A(n3894), .B(n3878), .Y(DP_OP_95J138_125_7728_n68) );
INVX6TS U4996 ( .A(n3927), .Y(n4008) );
NOR2XLTS U4997 ( .A(n4941), .B(n4008), .Y(n3879) );
XOR2X1TS U4998 ( .A(n3892), .B(n3879), .Y(DP_OP_95J138_125_7728_n69) );
NOR2XLTS U4999 ( .A(n4942), .B(n4008), .Y(n3880) );
XOR2X1TS U5000 ( .A(n3892), .B(n3880), .Y(DP_OP_95J138_125_7728_n70) );
NOR2XLTS U5001 ( .A(n4911), .B(n4008), .Y(n3881) );
XOR2X1TS U5002 ( .A(n3894), .B(n3881), .Y(DP_OP_95J138_125_7728_n71) );
XOR2X1TS U5003 ( .A(n3913), .B(n3882), .Y(DP_OP_95J138_125_7728_n72) );
XOR2X1TS U5004 ( .A(n3913), .B(n3883), .Y(DP_OP_95J138_125_7728_n73) );
NOR2XLTS U5005 ( .A(n4895), .B(n4008), .Y(n3884) );
XOR2X1TS U5006 ( .A(n3913), .B(n3884), .Y(DP_OP_95J138_125_7728_n74) );
NOR2XLTS U5007 ( .A(n4896), .B(n4008), .Y(n3885) );
XOR2X1TS U5008 ( .A(n3913), .B(n3885), .Y(DP_OP_95J138_125_7728_n75) );
NOR2XLTS U5009 ( .A(n4888), .B(n3925), .Y(n3886) );
XOR2X1TS U5010 ( .A(n3913), .B(n3886), .Y(DP_OP_95J138_125_7728_n76) );
NOR2XLTS U5011 ( .A(n4889), .B(n4008), .Y(n3887) );
XOR2X1TS U5012 ( .A(n3913), .B(n3887), .Y(DP_OP_95J138_125_7728_n77) );
NOR2XLTS U5013 ( .A(n4885), .B(n3901), .Y(n3888) );
XOR2X1TS U5014 ( .A(n3913), .B(n3888), .Y(DP_OP_95J138_125_7728_n78) );
NOR2XLTS U5015 ( .A(n4886), .B(n3925), .Y(n3889) );
XOR2X1TS U5016 ( .A(n3913), .B(n3889), .Y(DP_OP_95J138_125_7728_n79) );
NOR2XLTS U5017 ( .A(n4882), .B(n3901), .Y(n3890) );
XOR2X1TS U5018 ( .A(n4021), .B(n3890), .Y(DP_OP_95J138_125_7728_n80) );
NOR2XLTS U5019 ( .A(n4883), .B(n3925), .Y(n3891) );
XOR2X1TS U5020 ( .A(n3892), .B(n3891), .Y(DP_OP_95J138_125_7728_n81) );
NOR2XLTS U5021 ( .A(n4881), .B(n3925), .Y(n3893) );
XOR2X1TS U5022 ( .A(n3894), .B(n3893), .Y(DP_OP_95J138_125_7728_n82) );
NOR2XLTS U5023 ( .A(n4878), .B(n3925), .Y(n3895) );
XOR2X1TS U5024 ( .A(n4021), .B(n3895), .Y(DP_OP_95J138_125_7728_n83) );
NOR2XLTS U5025 ( .A(n4879), .B(n3925), .Y(n3896) );
XOR2X1TS U5026 ( .A(n4021), .B(n3896), .Y(DP_OP_95J138_125_7728_n84) );
NOR2XLTS U5027 ( .A(n4875), .B(n3925), .Y(n3897) );
XOR2X1TS U5028 ( .A(n3913), .B(n3897), .Y(DP_OP_95J138_125_7728_n85) );
NOR2XLTS U5029 ( .A(n4876), .B(n3901), .Y(n3898) );
XOR2X1TS U5030 ( .A(n3913), .B(n3898), .Y(DP_OP_95J138_125_7728_n86) );
NOR2XLTS U5031 ( .A(n4877), .B(n3925), .Y(n3899) );
XOR2X1TS U5032 ( .A(n3913), .B(n3899), .Y(DP_OP_95J138_125_7728_n87) );
NOR2XLTS U5033 ( .A(n4874), .B(n3925), .Y(n3900) );
XOR2X1TS U5034 ( .A(n3913), .B(n3900), .Y(DP_OP_95J138_125_7728_n88) );
XOR2X1TS U5035 ( .A(n3913), .B(n3902), .Y(DP_OP_95J138_125_7728_n89) );
XOR2X1TS U5036 ( .A(n3913), .B(n3903), .Y(DP_OP_95J138_125_7728_n90) );
XOR2X1TS U5037 ( .A(n3913), .B(n3904), .Y(DP_OP_95J138_125_7728_n91) );
XOR2X1TS U5038 ( .A(n3913), .B(n3905), .Y(DP_OP_95J138_125_7728_n92) );
XOR2X1TS U5039 ( .A(n3913), .B(n3906), .Y(DP_OP_95J138_125_7728_n93) );
XOR2X1TS U5040 ( .A(n3913), .B(n3907), .Y(DP_OP_95J138_125_7728_n94) );
XOR2X1TS U5041 ( .A(n3913), .B(n3908), .Y(DP_OP_95J138_125_7728_n95) );
XOR2X1TS U5042 ( .A(n3913), .B(n3909), .Y(DP_OP_95J138_125_7728_n96) );
INVX6TS U5043 ( .A(n3927), .Y(n4009) );
XOR2X1TS U5044 ( .A(n3913), .B(n3910), .Y(DP_OP_95J138_125_7728_n97) );
XOR2X1TS U5045 ( .A(n3913), .B(n3911), .Y(DP_OP_95J138_125_7728_n98) );
XOR2X1TS U5046 ( .A(n3913), .B(n3912), .Y(DP_OP_95J138_125_7728_n99) );
XOR2X1TS U5047 ( .A(n4021), .B(n3914), .Y(DP_OP_95J138_125_7728_n100) );
XOR2X1TS U5048 ( .A(n4021), .B(n3915), .Y(DP_OP_95J138_125_7728_n101) );
XOR2X1TS U5049 ( .A(n4021), .B(n3916), .Y(DP_OP_95J138_125_7728_n102) );
XOR2X1TS U5050 ( .A(n4021), .B(n3917), .Y(DP_OP_95J138_125_7728_n103) );
XOR2X1TS U5051 ( .A(n4021), .B(n3918), .Y(DP_OP_95J138_125_7728_n104) );
XOR2X1TS U5052 ( .A(n4021), .B(n3919), .Y(DP_OP_95J138_125_7728_n105) );
XOR2X1TS U5053 ( .A(n4021), .B(n3920), .Y(DP_OP_95J138_125_7728_n106) );
XOR2X1TS U5054 ( .A(n4021), .B(n3921), .Y(DP_OP_95J138_125_7728_n107) );
XOR2X1TS U5055 ( .A(n4021), .B(n3922), .Y(DP_OP_95J138_125_7728_n108) );
XOR2X1TS U5056 ( .A(n4021), .B(n3923), .Y(DP_OP_95J138_125_7728_n109) );
XOR2X1TS U5057 ( .A(n4021), .B(n3924), .Y(DP_OP_95J138_125_7728_n110) );
XOR2X1TS U5058 ( .A(n4021), .B(n3926), .Y(DP_OP_95J138_125_7728_n111) );
NAND2X1TS U5059 ( .A(n4847), .B(n3927), .Y(n3928) );
XOR2X1TS U5060 ( .A(n4021), .B(n3928), .Y(DP_OP_95J138_125_7728_n112) );
NOR2BX1TS U5061 ( .AN(add_subt_module_Sgf_normalized_result[1]), .B(n3925),
.Y(n3929) );
XOR2X1TS U5062 ( .A(n4021), .B(n3929), .Y(DP_OP_95J138_125_7728_n113) );
NOR2BX1TS U5063 ( .AN(add_subt_module_Sgf_normalized_result[0]), .B(n4008),
.Y(n3930) );
XOR2X1TS U5064 ( .A(n3892), .B(n3930), .Y(DP_OP_95J138_125_7728_n114) );
CLKAND2X2TS U5065 ( .A(n3052), .B(add_subt_module_DmP[62]), .Y(n3931) );
XOR2X1TS U5066 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3931), .Y(
DP_OP_92J138_122_9081_n16) );
CLKAND2X2TS U5067 ( .A(n3052), .B(add_subt_module_DmP[61]), .Y(n3932) );
XOR2X1TS U5068 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3932), .Y(
DP_OP_92J138_122_9081_n17) );
CLKAND2X2TS U5069 ( .A(n3052), .B(add_subt_module_DmP[60]), .Y(n3933) );
XOR2X1TS U5070 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3933), .Y(
DP_OP_92J138_122_9081_n18) );
CLKAND2X2TS U5071 ( .A(n3052), .B(add_subt_module_DmP[59]), .Y(n3934) );
XOR2X1TS U5072 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3934), .Y(
DP_OP_92J138_122_9081_n19) );
CLKAND2X2TS U5073 ( .A(n3052), .B(add_subt_module_DmP[58]), .Y(n3935) );
XOR2X1TS U5074 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3935), .Y(
DP_OP_92J138_122_9081_n20) );
AO22XLTS U5075 ( .A0(add_subt_module_LZA_output[5]), .A1(n3940), .B0(n3052),
.B1(add_subt_module_DmP[57]), .Y(n3936) );
XOR2X1TS U5076 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3936), .Y(
DP_OP_92J138_122_9081_n21) );
AO22XLTS U5077 ( .A0(add_subt_module_LZA_output[4]), .A1(n3940), .B0(n3052),
.B1(add_subt_module_DmP[56]), .Y(n3937) );
XOR2X1TS U5078 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3937), .Y(
DP_OP_92J138_122_9081_n22) );
AO22XLTS U5079 ( .A0(add_subt_module_LZA_output[3]), .A1(n3940), .B0(n3052),
.B1(add_subt_module_DmP[55]), .Y(n3938) );
XOR2X1TS U5080 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3938), .Y(
DP_OP_92J138_122_9081_n23) );
AO22XLTS U5081 ( .A0(add_subt_module_LZA_output[2]), .A1(n3940), .B0(n3052),
.B1(add_subt_module_DmP[54]), .Y(n3939) );
XOR2X1TS U5082 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3939), .Y(
DP_OP_92J138_122_9081_n24) );
AO22XLTS U5083 ( .A0(add_subt_module_LZA_output[1]), .A1(n3940), .B0(n3052),
.B1(add_subt_module_DmP[53]), .Y(n3941) );
XOR2X1TS U5084 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3941), .Y(
DP_OP_92J138_122_9081_n25) );
NOR2XLTS U5085 ( .A(add_subt_module_DmP[52]), .B(
add_subt_module_FSM_selector_B[1]), .Y(n3943) );
OAI21XLTS U5086 ( .A0(add_subt_module_FSM_selector_B[0]), .A1(n3943), .B0(
n3942), .Y(n3944) );
XOR2X1TS U5087 ( .A(add_subt_module_FSM_exp_operation_A_S), .B(n3944), .Y(
DP_OP_92J138_122_9081_n26) );
AOI21X1TS U5088 ( .A0(add_subt_module_Add_Subt_result[39]), .A1(n4976), .B0(
add_subt_module_Add_Subt_result[41]), .Y(n3949) );
NAND2X1TS U5089 ( .A(add_subt_module_Add_Subt_result[21]), .B(n3946), .Y(
n3979) );
AOI31X1TS U5090 ( .A0(add_subt_module_Add_Subt_result[19]), .A1(n3951), .A2(
n4989), .B0(n3950), .Y(n4451) );
OAI21XLTS U5091 ( .A0(add_subt_module_Add_Subt_result[42]), .A1(
add_subt_module_Add_Subt_result[40]), .B0(n3952), .Y(n3953) );
OAI211X1TS U5092 ( .A0(n3954), .A1(n4989), .B0(n4451), .C0(n3953), .Y(n3956)
);
OAI32X1TS U5093 ( .A0(n3956), .A1(add_subt_module_Add_Subt_result[6]), .A2(
add_subt_module_Add_Subt_result[4]), .B0(n3955), .B1(n3956), .Y(n4003)
);
AOI21X1TS U5094 ( .A0(n2994), .A1(n4969), .B0(
add_subt_module_Add_Subt_result[29]), .Y(n3962) );
AOI21X1TS U5095 ( .A0(n4936), .A1(n4842), .B0(n3957), .Y(n3958) );
AOI211X1TS U5096 ( .A0(add_subt_module_Add_Subt_result[47]), .A1(n4443),
.B0(n3958), .C0(n4006), .Y(n3960) );
OAI211X1TS U5097 ( .A0(n3962), .A1(n3961), .B0(n3960), .C0(n3959), .Y(n4448)
);
NAND2X1TS U5098 ( .A(n3963), .B(n2992), .Y(n3995) );
NAND3XLTS U5099 ( .A(n4988), .B(add_subt_module_Add_Subt_result[34]), .C(
n4438), .Y(n3983) );
OAI22X1TS U5100 ( .A0(add_subt_module_Add_Subt_result[35]), .A1(n3983), .B0(
n3965), .B1(n3964), .Y(n3966) );
AOI2BB1XLTS U5101 ( .A0N(n4974), .A1N(n3967), .B0(n3966), .Y(n3969) );
OAI211XLTS U5102 ( .A0(add_subt_module_Add_Subt_result[23]), .A1(n3995),
.B0(n3969), .C0(n3968), .Y(n3970) );
AOI211XLTS U5103 ( .A0(n3972), .A1(n3971), .B0(n4448), .C0(n3970), .Y(n3973)
);
AOI2BB2XLTS U5104 ( .B0(n4003), .B1(n3973), .A0N(n4455), .A1N(
add_subt_module_LZA_output[2]), .Y(n2594) );
AO21XLTS U5105 ( .A0(n4322), .A1(n4321), .B0(n4009), .Y(n2663) );
MX2X1TS U5106 ( .A(add_subt_module_DMP[62]), .B(
add_subt_module_exp_oper_result[10]), .S0(n4009), .Y(
add_subt_module_S_Oper_A_exp[10]) );
MX2X1TS U5107 ( .A(add_subt_module_DMP[61]), .B(
add_subt_module_exp_oper_result[9]), .S0(n4009), .Y(
add_subt_module_S_Oper_A_exp[9]) );
MX2X1TS U5108 ( .A(add_subt_module_DMP[60]), .B(
add_subt_module_exp_oper_result[8]), .S0(n4009), .Y(
add_subt_module_S_Oper_A_exp[8]) );
MX2X1TS U5109 ( .A(add_subt_module_DMP[59]), .B(
add_subt_module_exp_oper_result[7]), .S0(n4009), .Y(
add_subt_module_S_Oper_A_exp[7]) );
MX2X1TS U5110 ( .A(add_subt_module_DMP[58]), .B(
add_subt_module_exp_oper_result[6]), .S0(n4009), .Y(
add_subt_module_S_Oper_A_exp[6]) );
MX2X1TS U5111 ( .A(add_subt_module_DMP[57]), .B(
add_subt_module_exp_oper_result[5]), .S0(n4009), .Y(
add_subt_module_S_Oper_A_exp[5]) );
MX2X1TS U5112 ( .A(add_subt_module_DMP[56]), .B(
add_subt_module_exp_oper_result[4]), .S0(n4009), .Y(
add_subt_module_S_Oper_A_exp[4]) );
MX2X1TS U5113 ( .A(add_subt_module_DMP[55]), .B(
add_subt_module_exp_oper_result[3]), .S0(n4008), .Y(
add_subt_module_S_Oper_A_exp[3]) );
MX2X1TS U5114 ( .A(add_subt_module_DMP[54]), .B(
add_subt_module_exp_oper_result[2]), .S0(n4008), .Y(
add_subt_module_S_Oper_A_exp[2]) );
MX2X1TS U5115 ( .A(add_subt_module_DMP[53]), .B(
add_subt_module_exp_oper_result[1]), .S0(n4008), .Y(
add_subt_module_S_Oper_A_exp[1]) );
AO21XLTS U5116 ( .A0(n3677), .A1(add_subt_module_exp_oper_result[0]), .B0(
n3974), .Y(n2653) );
MX2X1TS U5117 ( .A(add_subt_module_DMP[52]), .B(
add_subt_module_exp_oper_result[0]), .S0(n4008), .Y(
add_subt_module_S_Oper_A_exp[0]) );
OR2X1TS U5118 ( .A(add_subt_module_Add_Subt_result[29]), .B(
add_subt_module_Add_Subt_result[28]), .Y(n3975) );
OAI31X1TS U5119 ( .A0(n2994), .A1(n3975), .A2(n4987), .B0(n4816), .Y(n4000)
);
OAI31X1TS U5120 ( .A0(add_subt_module_Add_Subt_result[33]), .A1(n3975), .A2(
n4000), .B0(n2987), .Y(n3976) );
OAI31X1TS U5121 ( .A0(add_subt_module_Add_Subt_result[41]), .A1(n3977), .A2(
n4441), .B0(n3976), .Y(n3981) );
NAND2X1TS U5122 ( .A(add_subt_module_Add_Subt_result[25]), .B(n3978), .Y(
n3993) );
NAND3XLTS U5123 ( .A(n3993), .B(n3979), .C(n3995), .Y(n3980) );
NOR4BX1TS U5124 ( .AN(n3983), .B(n3982), .C(n3981), .D(n3980), .Y(n3984) );
OAI31X1TS U5125 ( .A0(n3986), .A1(n3985), .A2(n4982), .B0(n3984), .Y(n3987)
);
OA22X1TS U5126 ( .A0(n3988), .A1(n3987), .B0(n4455), .B1(
add_subt_module_LZA_output[4]), .Y(n2590) );
AOI21X1TS U5127 ( .A0(add_subt_module_Add_Subt_result[8]), .A1(n4965), .B0(
add_subt_module_Add_Subt_result[10]), .Y(n4004) );
OAI211XLTS U5128 ( .A0(n3990), .A1(add_subt_module_Add_Subt_result[7]), .B0(
n3989), .C0(n4004), .Y(n3991) );
NAND4XLTS U5129 ( .A(n3994), .B(n3993), .C(n3992), .D(n3991), .Y(n4453) );
NOR3XLTS U5130 ( .A(add_subt_module_Add_Subt_result[44]), .B(
add_subt_module_Add_Subt_result[46]), .C(
add_subt_module_Add_Subt_result[45]), .Y(n3998) );
OAI211XLTS U5131 ( .A0(n3998), .A1(n3997), .B0(n3996), .C0(n3995), .Y(n3999)
);
AOI211XLTS U5132 ( .A0(n4001), .A1(n4000), .B0(n4453), .C0(n3999), .Y(n4002)
);
NAND2X1TS U5133 ( .A(n5007), .B(n4009), .Y(add_subt_module_S_A_S_Oper_A[54])
);
AOI22X1TS U5134 ( .A0(n4011), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(
n3325), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[104]), .Y(
n4013) );
OAI211XLTS U5135 ( .A0(n4014), .A1(n4996), .B0(n4013), .C0(n4012), .Y(n4015)
);
AOI21X1TS U5136 ( .A0(n3597), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(
n4015), .Y(n4018) );
AOI22X1TS U5137 ( .A0(n4018), .A1(n4017), .B0(n3740), .B1(n4877), .Y(n2562)
);
XOR2X1TS U5138 ( .A(DP_OP_95J138_125_7728_n1), .B(n4021), .Y(n4022) );
INVX4TS U5139 ( .A(n4028), .Y(n4024) );
AO22XLTS U5140 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[0]), .A1(
n4024), .B0(n4027), .B1(add_subt_module_Add_Subt_result[0]), .Y(n2596)
);
AO22XLTS U5141 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[1]), .A1(
n4024), .B0(n4026), .B1(add_subt_module_Add_Subt_result[1]), .Y(n2597)
);
AO22XLTS U5142 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[2]), .A1(
n4024), .B0(n4026), .B1(add_subt_module_Add_Subt_result[2]), .Y(n2598)
);
AO22XLTS U5143 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[3]), .A1(
n4024), .B0(n4026), .B1(add_subt_module_Add_Subt_result[3]), .Y(n2599)
);
AO22XLTS U5144 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[4]), .A1(
n4024), .B0(n4026), .B1(add_subt_module_Add_Subt_result[4]), .Y(n2600)
);
AO22XLTS U5145 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[10]), .A1(
n4023), .B0(n3005), .B1(add_subt_module_Add_Subt_result[10]), .Y(n2606) );
AO22XLTS U5146 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[11]), .A1(
n4024), .B0(n3005), .B1(add_subt_module_Add_Subt_result[11]), .Y(n2607) );
AO22XLTS U5147 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[12]), .A1(
n4024), .B0(n3005), .B1(add_subt_module_Add_Subt_result[12]), .Y(n2608) );
INVX4TS U5148 ( .A(n3005), .Y(n4025) );
AO22XLTS U5149 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[13]), .A1(
n4025), .B0(n3005), .B1(add_subt_module_Add_Subt_result[13]), .Y(n2609) );
AO22XLTS U5150 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[14]), .A1(
n4025), .B0(n3005), .B1(add_subt_module_Add_Subt_result[14]), .Y(n2610) );
AO22XLTS U5151 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[16]), .A1(
n4025), .B0(n4027), .B1(add_subt_module_Add_Subt_result[16]), .Y(n2612) );
AO22XLTS U5152 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[17]), .A1(
n4025), .B0(n4027), .B1(add_subt_module_Add_Subt_result[17]), .Y(n2613) );
AO22XLTS U5153 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[18]), .A1(
n4025), .B0(n4027), .B1(add_subt_module_Add_Subt_result[18]), .Y(n2614) );
AO22XLTS U5154 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[20]), .A1(
n4025), .B0(n4028), .B1(add_subt_module_Add_Subt_result[20]), .Y(n2616) );
AO22XLTS U5155 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[33]), .A1(
n4025), .B0(n3005), .B1(add_subt_module_Add_Subt_result[33]), .Y(n2629) );
AO22XLTS U5156 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[32]), .A1(
n4025), .B0(n4026), .B1(add_subt_module_Add_Subt_result[32]), .Y(n2628) );
AO22XLTS U5157 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[30]), .A1(
n4029), .B0(n4027), .B1(add_subt_module_Add_Subt_result[30]), .Y(n2626) );
AO22XLTS U5158 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[25]), .A1(
n4029), .B0(n4028), .B1(add_subt_module_Add_Subt_result[25]), .Y(n2621) );
AO22XLTS U5159 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[28]), .A1(
n4029), .B0(n4028), .B1(add_subt_module_Add_Subt_result[28]), .Y(n2624) );
AO22XLTS U5160 ( .A0(add_subt_module_Add_Subt_Sgf_module_S_to_D[26]), .A1(
n4029), .B0(n4028), .B1(add_subt_module_Add_Subt_result[26]), .Y(n2622) );
AOI22X1TS U5161 ( .A0(add_subt_module_Add_Subt_result[50]), .A1(n4270), .B0(
add_subt_module_DmP[48]), .B1(n4205), .Y(n4031) );
BUFX3TS U5162 ( .A(n4242), .Y(n4286) );
AOI22X1TS U5163 ( .A0(n4030), .A1(n4048), .B0(n4286), .B1(n4041), .Y(n4032)
);
OAI21XLTS U5164 ( .A0(n4038), .A1(n4253), .B0(n4032), .Y(n4033) );
AOI21X1TS U5165 ( .A0(n4284), .A1(n4034), .B0(n4033), .Y(n4054) );
AOI22X1TS U5166 ( .A0(n4152), .A1(n4054), .B0(n4035), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[50]) );
AOI22X1TS U5167 ( .A0(add_subt_module_Add_Subt_result[5]), .A1(n4149), .B0(
add_subt_module_DmP[47]), .B1(n2950), .Y(n4036) );
AOI22X1TS U5168 ( .A0(n4238), .A1(n4041), .B0(n4030), .B1(n4053), .Y(n4037)
);
OAI21XLTS U5169 ( .A0(n4038), .A1(n4234), .B0(n4037), .Y(n4039) );
AOI21X1TS U5170 ( .A0(n4242), .A1(n4048), .B0(n4039), .Y(n4059) );
AOI22X1TS U5171 ( .A0(n4152), .A1(n4059), .B0(n4040), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[49]) );
AOI222X4TS U5172 ( .A0(n4205), .A1(add_subt_module_DmP[46]), .B0(
add_subt_module_Add_Subt_result[6]), .B1(n4211), .C0(
add_subt_module_Add_Subt_result[48]), .C1(n3366), .Y(n4057) );
AOI22X1TS U5173 ( .A0(n4246), .A1(n4041), .B0(n4286), .B1(n4053), .Y(n4042)
);
OAI21XLTS U5174 ( .A0(n4057), .A1(n3313), .B0(n4042), .Y(n4043) );
AOI21X1TS U5175 ( .A0(n4238), .A1(n4048), .B0(n4043), .Y(n4063) );
AOI22X1TS U5176 ( .A0(n4152), .A1(n4063), .B0(n4044), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]) );
OAI22X1TS U5177 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[45]), .B0(add_subt_module_Add_Subt_result[7]),
.B1(n4281), .Y(n4045) );
AOI22X1TS U5178 ( .A0(n4288), .A1(n4053), .B0(n4030), .B1(n4060), .Y(n4046)
);
OAI21XLTS U5179 ( .A0(n4057), .A1(n3364), .B0(n4046), .Y(n4047) );
AOI21X1TS U5180 ( .A0(n4284), .A1(n4048), .B0(n4047), .Y(n4067) );
AOI22X1TS U5181 ( .A0(n4152), .A1(n4067), .B0(n4049), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]) );
AOI22X1TS U5182 ( .A0(add_subt_module_Add_Subt_result[8]), .A1(n4149), .B0(
add_subt_module_DmP[44]), .B1(n2950), .Y(n4050) );
AOI22X1TS U5183 ( .A0(n4030), .A1(n4064), .B0(n4286), .B1(n4060), .Y(n4051)
);
OAI21XLTS U5184 ( .A0(n4057), .A1(n4253), .B0(n4051), .Y(n4052) );
AOI21X1TS U5185 ( .A0(n4284), .A1(n4053), .B0(n4052), .Y(n4072) );
AOI22X1TS U5186 ( .A0(n4115), .A1(n4072), .B0(n4054), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]) );
AOI22X1TS U5187 ( .A0(add_subt_module_Add_Subt_result[45]), .A1(n4270), .B0(
add_subt_module_DmP[43]), .B1(n2950), .Y(n4055) );
AOI22X1TS U5188 ( .A0(n4030), .A1(n4069), .B0(n4286), .B1(n4064), .Y(n4056)
);
OAI21XLTS U5189 ( .A0(n4057), .A1(n4234), .B0(n4056), .Y(n4058) );
AOI21X1TS U5190 ( .A0(n4288), .A1(n4060), .B0(n4058), .Y(n4077) );
AOI22X1TS U5191 ( .A0(n4152), .A1(n4077), .B0(n4059), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]) );
AOI222X4TS U5192 ( .A0(n4205), .A1(add_subt_module_DmP[42]), .B0(
add_subt_module_Add_Subt_result[10]), .B1(n4211), .C0(
add_subt_module_Add_Subt_result[44]), .C1(n3366), .Y(n4075) );
AOI22X1TS U5193 ( .A0(n4246), .A1(n4060), .B0(n4286), .B1(n4069), .Y(n4061)
);
OAI21XLTS U5194 ( .A0(n4075), .A1(n3313), .B0(n4061), .Y(n4062) );
AOI21X1TS U5195 ( .A0(n4238), .A1(n4064), .B0(n4062), .Y(n4081) );
AOI22X1TS U5196 ( .A0(n4115), .A1(n4081), .B0(n4063), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]) );
AOI222X4TS U5197 ( .A0(n4205), .A1(n4979), .B0(n4810), .B1(n4270), .C0(n4842), .C1(n4211), .Y(n4078) );
AOI22X1TS U5198 ( .A0(n4284), .A1(n4064), .B0(n4238), .B1(n4069), .Y(n4065)
);
OAI21XLTS U5199 ( .A0(n4075), .A1(n3364), .B0(n4065), .Y(n4066) );
AOI21X1TS U5200 ( .A0(n4271), .A1(n4078), .B0(n4066), .Y(n4086) );
AOI22X1TS U5201 ( .A0(n4115), .A1(n4086), .B0(n4067), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]) );
AOI22X1TS U5202 ( .A0(add_subt_module_Add_Subt_result[42]), .A1(n4270), .B0(
add_subt_module_DmP[40]), .B1(n4205), .Y(n4068) );
AOI22X1TS U5203 ( .A0(n4246), .A1(n4069), .B0(n4030), .B1(n4083), .Y(n4070)
);
OAI21XLTS U5204 ( .A0(n4075), .A1(n4253), .B0(n4070), .Y(n4071) );
AOI21X1TS U5205 ( .A0(n4242), .A1(n4078), .B0(n4071), .Y(n4092) );
AOI22X1TS U5206 ( .A0(n4152), .A1(n4092), .B0(n4072), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]) );
AOI22X1TS U5207 ( .A0(add_subt_module_Add_Subt_result[41]), .A1(n4270), .B0(
add_subt_module_DmP[39]), .B1(n4205), .Y(n4073) );
AOI22X1TS U5208 ( .A0(n4238), .A1(n4078), .B0(n4286), .B1(n4083), .Y(n4074)
);
OAI21XLTS U5209 ( .A0(n4075), .A1(n4234), .B0(n4074), .Y(n4076) );
AOI21X1TS U5210 ( .A0(n4271), .A1(n4090), .B0(n4076), .Y(n4097) );
AOI22X1TS U5211 ( .A0(n4152), .A1(n4097), .B0(n4077), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]) );
AOI222X4TS U5212 ( .A0(n4205), .A1(add_subt_module_DmP[38]), .B0(
add_subt_module_Add_Subt_result[14]), .B1(n4211), .C0(
add_subt_module_Add_Subt_result[40]), .C1(n3366), .Y(n4095) );
AOI22X1TS U5213 ( .A0(n4246), .A1(n4078), .B0(n4238), .B1(n4083), .Y(n4079)
);
OAI21XLTS U5214 ( .A0(n4095), .A1(n3313), .B0(n4079), .Y(n4080) );
AOI21X1TS U5215 ( .A0(n4242), .A1(n4090), .B0(n4080), .Y(n4101) );
AOI22X1TS U5216 ( .A0(n4115), .A1(n4101), .B0(n4081), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]) );
OAI22X1TS U5217 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[37]), .B0(add_subt_module_Add_Subt_result[39]),
.B1(n4280), .Y(n4082) );
AOI2BB1X2TS U5218 ( .A0N(n4263), .A1N(add_subt_module_Add_Subt_result[15]),
.B0(n4082), .Y(n4098) );
AOI22X1TS U5219 ( .A0(n4246), .A1(n4083), .B0(n4238), .B1(n4090), .Y(n4084)
);
OAI21XLTS U5220 ( .A0(n4095), .A1(n3364), .B0(n4084), .Y(n4085) );
AOI21X1TS U5221 ( .A0(n4271), .A1(n4098), .B0(n4085), .Y(n4106) );
AOI22X1TS U5222 ( .A0(n4152), .A1(n4106), .B0(n4086), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]) );
AOI22X1TS U5223 ( .A0(add_subt_module_Add_Subt_result[38]), .A1(n4270), .B0(
add_subt_module_DmP[36]), .B1(n4205), .Y(n4087) );
AOI22X1TS U5224 ( .A0(n4030), .A1(n4103), .B0(n4286), .B1(n4098), .Y(n4088)
);
OAI21XLTS U5225 ( .A0(n4095), .A1(n4253), .B0(n4088), .Y(n4089) );
AOI21X1TS U5226 ( .A0(n4284), .A1(n4090), .B0(n4089), .Y(n4110) );
AOI22X1TS U5227 ( .A0(n4115), .A1(n4110), .B0(n4092), .B1(n4091), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]) );
BUFX4TS U5228 ( .A(n4115), .Y(n4226) );
AOI22X1TS U5229 ( .A0(add_subt_module_Add_Subt_result[37]), .A1(n4270), .B0(
add_subt_module_DmP[35]), .B1(n2950), .Y(n4093) );
AOI22X1TS U5230 ( .A0(n4238), .A1(n4098), .B0(n4286), .B1(n4103), .Y(n4094)
);
OAI21XLTS U5231 ( .A0(n4095), .A1(n4234), .B0(n4094), .Y(n4096) );
AOI21X1TS U5232 ( .A0(n4271), .A1(n4107), .B0(n4096), .Y(n4114) );
AOI22X1TS U5233 ( .A0(n4226), .A1(n4114), .B0(n4097), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]) );
AOI222X4TS U5234 ( .A0(n4205), .A1(add_subt_module_DmP[34]), .B0(
add_subt_module_Add_Subt_result[18]), .B1(n4149), .C0(
add_subt_module_Add_Subt_result[36]), .C1(n3366), .Y(n4111) );
AOI22X1TS U5235 ( .A0(n4246), .A1(n4098), .B0(n4251), .B1(n4107), .Y(n4099)
);
OAI21XLTS U5236 ( .A0(n4111), .A1(n3313), .B0(n4099), .Y(n4100) );
AOI21X1TS U5237 ( .A0(n4288), .A1(n4103), .B0(n4100), .Y(n4119) );
AOI22X1TS U5238 ( .A0(n4115), .A1(n4119), .B0(n4101), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]) );
OAI22X1TS U5239 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[33]), .B0(add_subt_module_Add_Subt_result[19]),
.B1(n4281), .Y(n4102) );
AOI22X1TS U5240 ( .A0(n4246), .A1(n4103), .B0(n4238), .B1(n4107), .Y(n4104)
);
OAI21XLTS U5241 ( .A0(n4111), .A1(n3364), .B0(n4104), .Y(n4105) );
AOI21X1TS U5242 ( .A0(n4271), .A1(n4118), .B0(n4105), .Y(n4123) );
AOI22X1TS U5243 ( .A0(n4115), .A1(n4123), .B0(n4106), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]) );
AOI222X4TS U5244 ( .A0(n4205), .A1(add_subt_module_DmP[32]), .B0(
add_subt_module_Add_Subt_result[20]), .B1(n4211), .C0(
add_subt_module_Add_Subt_result[34]), .C1(n3366), .Y(n4120) );
AOI2BB2XLTS U5245 ( .B0(n4284), .B1(n4107), .A0N(n4253), .A1N(n4111), .Y(
n4108) );
OAI21XLTS U5246 ( .A0(n4120), .A1(n3313), .B0(n4108), .Y(n4109) );
AOI21X1TS U5247 ( .A0(n4242), .A1(n4118), .B0(n4109), .Y(n4128) );
AOI22X1TS U5248 ( .A0(n4115), .A1(n4128), .B0(n4110), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]) );
NOR2XLTS U5249 ( .A(n4120), .B(n3364), .Y(n4113) );
AOI222X4TS U5250 ( .A0(n4205), .A1(add_subt_module_DmP[31]), .B0(
add_subt_module_Add_Subt_result[21]), .B1(n4211), .C0(
add_subt_module_Add_Subt_result[33]), .C1(n3366), .Y(n4125) );
OAI22X1TS U5251 ( .A0(n4125), .A1(n3313), .B0(n4111), .B1(n4234), .Y(n4112)
);
AOI22X1TS U5252 ( .A0(n4115), .A1(n4133), .B0(n4114), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]) );
BUFX3TS U5253 ( .A(n4115), .Y(n4292) );
AOI222X4TS U5254 ( .A0(n4205), .A1(add_subt_module_DmP[30]), .B0(n2992),
.B1(n4211), .C0(add_subt_module_Add_Subt_result[32]), .C1(n3366), .Y(
n4130) );
OAI22X1TS U5255 ( .A0(n4120), .A1(n4253), .B0(n4130), .B1(n3313), .Y(n4116)
);
AOI211X1TS U5256 ( .A0(n4118), .A1(n4246), .B0(n4117), .C0(n4116), .Y(n4137)
);
AOI22X1TS U5257 ( .A0(n4292), .A1(n4137), .B0(n4119), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]) );
OAI222X4TS U5258 ( .A0(n4280), .A1(add_subt_module_Add_Subt_result[31]),
.B0(n4281), .B1(add_subt_module_Add_Subt_result[23]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[29]), .Y(
n4135) );
OAI22X1TS U5259 ( .A0(n4130), .A1(n3364), .B0(n3313), .B1(n4135), .Y(n4122)
);
OAI22X1TS U5260 ( .A0(n4120), .A1(n4234), .B0(n4125), .B1(n4253), .Y(n4121)
);
NOR2X1TS U5261 ( .A(n4122), .B(n4121), .Y(n4140) );
AOI22X1TS U5262 ( .A0(n4226), .A1(n4140), .B0(n4123), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]) );
AOI22X1TS U5263 ( .A0(add_subt_module_Add_Subt_result[24]), .A1(n4149), .B0(
add_subt_module_DmP[28]), .B1(n2950), .Y(n4124) );
NOR2XLTS U5264 ( .A(n4130), .B(n4253), .Y(n4127) );
OAI22X1TS U5265 ( .A0(n4125), .A1(n4234), .B0(n4135), .B1(n3364), .Y(n4126)
);
AOI211X1TS U5266 ( .A0(n4271), .A1(n4139), .B0(n4127), .C0(n4126), .Y(n4147)
);
AOI22X1TS U5267 ( .A0(n4292), .A1(n4147), .B0(n4128), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]) );
AOI22X1TS U5268 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n4270), .B0(
add_subt_module_DmP[27]), .B1(n2950), .Y(n4129) );
NOR2XLTS U5269 ( .A(n4253), .B(n4135), .Y(n4132) );
OAI2BB2XLTS U5270 ( .B0(n4130), .B1(n4234), .A0N(n4139), .A1N(n4242), .Y(
n4131) );
AOI211X1TS U5271 ( .A0(n4030), .A1(n4144), .B0(n4132), .C0(n4131), .Y(n4153)
);
AOI22X1TS U5272 ( .A0(n4226), .A1(n4153), .B0(n4133), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]) );
OAI222X1TS U5273 ( .A0(n4280), .A1(add_subt_module_Add_Subt_result[28]),
.B0(n4281), .B1(add_subt_module_Add_Subt_result[26]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[26]), .Y(
n4138) );
INVX2TS U5274 ( .A(n4138), .Y(n4145) );
AOI22X1TS U5275 ( .A0(n4288), .A1(n4139), .B0(n4251), .B1(n4144), .Y(n4134)
);
OAI21XLTS U5276 ( .A0(n4234), .A1(n4135), .B0(n4134), .Y(n4136) );
AOI21X1TS U5277 ( .A0(n4030), .A1(n4145), .B0(n4136), .Y(n4157) );
AOI22X1TS U5278 ( .A0(n4226), .A1(n4157), .B0(n4137), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]) );
AOI22X1TS U5279 ( .A0(add_subt_module_FSM_selector_C), .A1(n2994), .B0(
add_subt_module_DmP[25]), .B1(n4205), .Y(n4142) );
AOI22X1TS U5280 ( .A0(n4143), .A1(n4142), .B0(n4138), .B1(n4141), .Y(n4151)
);
AOI22X1TS U5281 ( .A0(n4226), .A1(n4161), .B0(n4140), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]) );
OAI222X1TS U5282 ( .A0(n4281), .A1(add_subt_module_Add_Subt_result[28]),
.B0(n4280), .B1(add_subt_module_Add_Subt_result[26]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[24]), .Y(
n4148) );
AOI22X1TS U5283 ( .A0(n4143), .A1(n4148), .B0(n4142), .B1(n4141), .Y(n4156)
);
AOI22X1TS U5284 ( .A0(n4226), .A1(n4166), .B0(n4147), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]) );
INVX2TS U5285 ( .A(n4148), .Y(n4160) );
AOI22X1TS U5286 ( .A0(add_subt_module_Add_Subt_result[29]), .A1(n4149), .B0(
add_subt_module_DmP[23]), .B1(n2950), .Y(n4150) );
AOI22X1TS U5287 ( .A0(n4226), .A1(n4171), .B0(n4153), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]) );
AOI22X1TS U5288 ( .A0(add_subt_module_Add_Subt_result[24]), .A1(n4270), .B0(
add_subt_module_DmP[22]), .B1(n4205), .Y(n4154) );
AOI22X1TS U5289 ( .A0(n4226), .A1(n4176), .B0(n4157), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]) );
OAI222X4TS U5290 ( .A0(n4281), .A1(add_subt_module_Add_Subt_result[31]),
.B0(n4280), .B1(add_subt_module_Add_Subt_result[23]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[21]), .Y(
n4174) );
AOI22X1TS U5291 ( .A0(n4288), .A1(n4163), .B0(n4251), .B1(n4168), .Y(n4158)
);
OAI21XLTS U5292 ( .A0(n3313), .A1(n4174), .B0(n4158), .Y(n4159) );
AOI21X1TS U5293 ( .A0(n4284), .A1(n4160), .B0(n4159), .Y(n4180) );
AOI22X1TS U5294 ( .A0(n4226), .A1(n4180), .B0(n4161), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U5295 ( .A0(n2992), .A1(n4270), .B0(add_subt_module_DmP[20]), .B1(
n4205), .Y(n4162) );
AOI22X1TS U5296 ( .A0(n4246), .A1(n4163), .B0(n4238), .B1(n4168), .Y(n4164)
);
OAI21XLTS U5297 ( .A0(n3364), .A1(n4174), .B0(n4164), .Y(n4165) );
AOI21X1TS U5298 ( .A0(n4271), .A1(n4177), .B0(n4165), .Y(n4185) );
AOI22X1TS U5299 ( .A0(n4226), .A1(n4185), .B0(n4166), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]) );
AOI22X1TS U5300 ( .A0(add_subt_module_Add_Subt_result[21]), .A1(n4270), .B0(
add_subt_module_DmP[19]), .B1(n4205), .Y(n4167) );
AOI22X1TS U5301 ( .A0(n4246), .A1(n4168), .B0(n4251), .B1(n4177), .Y(n4169)
);
OAI21XLTS U5302 ( .A0(n4253), .A1(n4174), .B0(n4169), .Y(n4170) );
AOI21X1TS U5303 ( .A0(n4030), .A1(n4182), .B0(n4170), .Y(n4189) );
AOI22X1TS U5304 ( .A0(n4226), .A1(n4189), .B0(n4171), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]) );
AOI22X1TS U5305 ( .A0(add_subt_module_Add_Subt_result[20]), .A1(n4270), .B0(
add_subt_module_DmP[18]), .B1(n2950), .Y(n4172) );
OAI2BB1X1TS U5306 ( .A0N(add_subt_module_Add_Subt_result[34]), .A1N(n4211),
.B0(n4172), .Y(n4186) );
AOI22X1TS U5307 ( .A0(n4288), .A1(n4177), .B0(n4251), .B1(n4182), .Y(n4173)
);
OAI21XLTS U5308 ( .A0(n4234), .A1(n4174), .B0(n4173), .Y(n4175) );
AOI21X1TS U5309 ( .A0(n4030), .A1(n4186), .B0(n4175), .Y(n4194) );
AOI22X1TS U5310 ( .A0(n4226), .A1(n4194), .B0(n4176), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI222X4TS U5311 ( .A0(n4281), .A1(add_subt_module_Add_Subt_result[35]),
.B0(n4280), .B1(add_subt_module_Add_Subt_result[19]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[17]), .Y(
n4192) );
AOI22X1TS U5312 ( .A0(n4246), .A1(n4177), .B0(n4242), .B1(n4186), .Y(n4178)
);
OAI21XLTS U5313 ( .A0(n3313), .A1(n4192), .B0(n4178), .Y(n4179) );
AOI21X1TS U5314 ( .A0(n4288), .A1(n4182), .B0(n4179), .Y(n4198) );
AOI22X1TS U5315 ( .A0(n4226), .A1(n4198), .B0(n4180), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]) );
AOI22X1TS U5316 ( .A0(add_subt_module_Add_Subt_result[18]), .A1(n4270), .B0(
add_subt_module_DmP[16]), .B1(n2950), .Y(n4181) );
AOI22X1TS U5317 ( .A0(n4246), .A1(n4182), .B0(n4030), .B1(n4195), .Y(n4183)
);
OAI21XLTS U5318 ( .A0(n3364), .A1(n4192), .B0(n4183), .Y(n4184) );
AOI21X1TS U5319 ( .A0(n4238), .A1(n4186), .B0(n4184), .Y(n4204) );
AOI22X1TS U5320 ( .A0(n4226), .A1(n4204), .B0(n4185), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]) );
AOI222X4TS U5321 ( .A0(n4205), .A1(n4980), .B0(n4838), .B1(n4211), .C0(n4815), .C1(n3366), .Y(n4200) );
AOI22X1TS U5322 ( .A0(n4246), .A1(n4186), .B0(n4030), .B1(n4200), .Y(n4187)
);
OAI21XLTS U5323 ( .A0(n4253), .A1(n4192), .B0(n4187), .Y(n4188) );
AOI21X1TS U5324 ( .A0(n4242), .A1(n4195), .B0(n4188), .Y(n4210) );
AOI22X1TS U5325 ( .A0(n4292), .A1(n4210), .B0(n4189), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]) );
OAI22X1TS U5326 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[14]), .B0(add_subt_module_Add_Subt_result[38]),
.B1(n4281), .Y(n4190) );
AOI22X1TS U5327 ( .A0(n4288), .A1(n4195), .B0(n4030), .B1(n4207), .Y(n4191)
);
OAI21XLTS U5328 ( .A0(n4234), .A1(n4192), .B0(n4191), .Y(n4193) );
AOI21X1TS U5329 ( .A0(n4242), .A1(n4200), .B0(n4193), .Y(n4216) );
AOI22X1TS U5330 ( .A0(n4226), .A1(n4216), .B0(n4194), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]) );
OAI222X4TS U5331 ( .A0(n4281), .A1(add_subt_module_Add_Subt_result[39]),
.B0(n4280), .B1(add_subt_module_Add_Subt_result[15]), .C0(
add_subt_module_FSM_selector_C), .C1(add_subt_module_DmP[13]), .Y(
n4213) );
AOI22X1TS U5332 ( .A0(n4246), .A1(n4195), .B0(n4251), .B1(n4207), .Y(n4196)
);
OAI21XLTS U5333 ( .A0(n3313), .A1(n4213), .B0(n4196), .Y(n4197) );
AOI21X1TS U5334 ( .A0(n4288), .A1(n4200), .B0(n4197), .Y(n4220) );
AOI22X1TS U5335 ( .A0(n4115), .A1(n4220), .B0(n4198), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]) );
AOI22X1TS U5336 ( .A0(add_subt_module_Add_Subt_result[14]), .A1(n4270), .B0(
add_subt_module_DmP[12]), .B1(n2950), .Y(n4199) );
AOI22X1TS U5337 ( .A0(n4246), .A1(n4200), .B0(n4238), .B1(n4207), .Y(n4201)
);
OAI21XLTS U5338 ( .A0(n3364), .A1(n4213), .B0(n4201), .Y(n4202) );
AOI21X1TS U5339 ( .A0(n4271), .A1(n4217), .B0(n4202), .Y(n4225) );
AOI22X1TS U5340 ( .A0(n4226), .A1(n4225), .B0(n4204), .B1(n4203), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]) );
AOI22X1TS U5341 ( .A0(add_subt_module_Add_Subt_result[13]), .A1(n4270), .B0(
add_subt_module_DmP[11]), .B1(n2950), .Y(n4206) );
AOI22X1TS U5342 ( .A0(n4246), .A1(n4207), .B0(n4030), .B1(n4224), .Y(n4208)
);
OAI21XLTS U5343 ( .A0(n4253), .A1(n4213), .B0(n4208), .Y(n4209) );
AOI21X1TS U5344 ( .A0(n4242), .A1(n4217), .B0(n4209), .Y(n4231) );
AOI22X1TS U5345 ( .A0(n4115), .A1(n4231), .B0(n4210), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]) );
AOI222X4TS U5346 ( .A0(n4205), .A1(n4981), .B0(n4809), .B1(n4211), .C0(n4843), .C1(n3366), .Y(n4228) );
AOI22X1TS U5347 ( .A0(n4288), .A1(n4217), .B0(n4251), .B1(n4224), .Y(n4212)
);
OAI21XLTS U5348 ( .A0(n4234), .A1(n4213), .B0(n4212), .Y(n4214) );
AOI21X1TS U5349 ( .A0(n4271), .A1(n4228), .B0(n4214), .Y(n4237) );
AOI22X1TS U5350 ( .A0(n4226), .A1(n4237), .B0(n4216), .B1(n4215), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI222X4TS U5351 ( .A0(n4205), .A1(add_subt_module_DmP[9]), .B0(
add_subt_module_Add_Subt_result[11]), .B1(n3366), .C0(
add_subt_module_Add_Subt_result[43]), .C1(n4211), .Y(n4235) );
AOI22X1TS U5352 ( .A0(n4246), .A1(n4217), .B0(n4242), .B1(n4228), .Y(n4218)
);
AOI21X1TS U5353 ( .A0(n4238), .A1(n4224), .B0(n4219), .Y(n4243) );
AOI22X1TS U5354 ( .A0(n4115), .A1(n4243), .B0(n4220), .B1(n4289), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U5355 ( .A0(add_subt_module_Add_Subt_result[44]), .A1(n4149), .B0(
add_subt_module_DmP[8]), .B1(n2950), .Y(n4221) );
AOI22X1TS U5356 ( .A0(n4288), .A1(n4228), .B0(n4030), .B1(n4239), .Y(n4222)
);
OAI21XLTS U5357 ( .A0(n4235), .A1(n3364), .B0(n4222), .Y(n4223) );
AOI21X1TS U5358 ( .A0(n4284), .A1(n4224), .B0(n4223), .Y(n4249) );
AOI22X1TS U5359 ( .A0(n4226), .A1(n4249), .B0(n4225), .B1(n4289), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]) );
OAI22X1TS U5360 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[7]), .B0(add_subt_module_Add_Subt_result[45]),
.B1(n4281), .Y(n4227) );
AOI22X1TS U5361 ( .A0(n4246), .A1(n4228), .B0(n4030), .B1(n4245), .Y(n4229)
);
OAI21XLTS U5362 ( .A0(n4235), .A1(n4253), .B0(n4229), .Y(n4230) );
AOI21X1TS U5363 ( .A0(n4242), .A1(n4239), .B0(n4230), .Y(n4256) );
AOI22X1TS U5364 ( .A0(n4115), .A1(n4256), .B0(n4231), .B1(n4289), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U5365 ( .A0(add_subt_module_Add_Subt_result[8]), .A1(n4270), .B0(
add_subt_module_DmP[6]), .B1(n2950), .Y(n4232) );
AOI22X1TS U5366 ( .A0(n4288), .A1(n4239), .B0(n4030), .B1(n4255), .Y(n4233)
);
OAI21XLTS U5367 ( .A0(n4235), .A1(n4234), .B0(n4233), .Y(n4236) );
AOI21X1TS U5368 ( .A0(n4242), .A1(n4245), .B0(n4236), .Y(n4261) );
AOI22X1TS U5369 ( .A0(n4292), .A1(n4261), .B0(n4237), .B1(n4289), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI222X4TS U5370 ( .A0(n4205), .A1(add_subt_module_DmP[5]), .B0(
add_subt_module_Add_Subt_result[7]), .B1(n3366), .C0(
add_subt_module_Add_Subt_result[47]), .C1(n4211), .Y(n4259) );
AOI22X1TS U5371 ( .A0(n4246), .A1(n4239), .B0(n4238), .B1(n4245), .Y(n4240)
);
OAI21XLTS U5372 ( .A0(n4259), .A1(n3313), .B0(n4240), .Y(n4241) );
AOI21X1TS U5373 ( .A0(n4242), .A1(n4255), .B0(n4241), .Y(n4265) );
AOI22X1TS U5374 ( .A0(n4292), .A1(n4265), .B0(n4243), .B1(n4289), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U5375 ( .A0(add_subt_module_Add_Subt_result[48]), .A1(n4149), .B0(
add_subt_module_DmP[4]), .B1(n2950), .Y(n4244) );
AOI22X1TS U5376 ( .A0(n4246), .A1(n4245), .B0(n4030), .B1(n4264), .Y(n4247)
);
OAI21XLTS U5377 ( .A0(n4259), .A1(n3364), .B0(n4247), .Y(n4248) );
AOI21X1TS U5378 ( .A0(n4288), .A1(n4255), .B0(n4248), .Y(n4273) );
AOI22X1TS U5379 ( .A0(n4292), .A1(n4273), .B0(n4249), .B1(n4289), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]) );
OAI22X1TS U5380 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[3]), .B0(add_subt_module_Add_Subt_result[5]), .B1(
n4280), .Y(n4250) );
AOI22X1TS U5381 ( .A0(n4271), .A1(n4272), .B0(n4251), .B1(n4264), .Y(n4252)
);
OAI21XLTS U5382 ( .A0(n4259), .A1(n4253), .B0(n4252), .Y(n4254) );
AOI21X1TS U5383 ( .A0(n4284), .A1(n4255), .B0(n4254), .Y(n4277) );
AOI22X1TS U5384 ( .A0(n4292), .A1(n4277), .B0(n4256), .B1(n4289), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]) );
OAI22X1TS U5385 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[2]), .B0(add_subt_module_Add_Subt_result[50]),
.B1(n4281), .Y(n4257) );
AOI22X1TS U5386 ( .A0(n4288), .A1(n4264), .B0(n4286), .B1(n4272), .Y(n4258)
);
OAI21XLTS U5387 ( .A0(n4259), .A1(n4234), .B0(n4258), .Y(n4260) );
AOI21X1TS U5388 ( .A0(n4271), .A1(n4276), .B0(n4260), .Y(n4290) );
AOI22X1TS U5389 ( .A0(n4292), .A1(n4290), .B0(n4261), .B1(n4289), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U5390 ( .A0(add_subt_module_Add_Subt_result[3]), .A1(n3366), .B0(
add_subt_module_DmP[1]), .B1(n4205), .Y(n4262) );
AOI22X1TS U5391 ( .A0(n4284), .A1(n4264), .B0(n4030), .B1(n4283), .Y(n4267)
);
AOI22X1TS U5392 ( .A0(n4288), .A1(n4272), .B0(n4286), .B1(n4276), .Y(n4266)
);
AOI32X1TS U5393 ( .A0(n4267), .A1(n4292), .A2(n4266), .B0(n4265), .B1(n4289),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U5394 ( .A0(n4288), .A1(n4276), .B0(n4286), .B1(n4283), .Y(n4275)
);
OAI22X1TS U5395 ( .A0(add_subt_module_FSM_selector_C), .A1(
add_subt_module_DmP[0]), .B0(add_subt_module_Add_Subt_result[52]),
.B1(n4281), .Y(n4269) );
AOI22X1TS U5396 ( .A0(n4284), .A1(n4272), .B0(n4271), .B1(n4287), .Y(n4274)
);
AOI32X1TS U5397 ( .A0(n4275), .A1(n4292), .A2(n4274), .B0(n4273), .B1(n4289),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U5398 ( .A0(n4284), .A1(n4276), .B0(n4286), .B1(n4287), .Y(n4279)
);
OAI2BB2X1TS U5399 ( .B0(n4983), .B1(n4280), .A0N(n2993), .A1N(n4149), .Y(
n4285) );
AOI22X1TS U5400 ( .A0(n4288), .A1(n4283), .B0(n4030), .B1(n4285), .Y(n4278)
);
AOI32X1TS U5401 ( .A0(n4279), .A1(n4292), .A2(n4278), .B0(n4277), .B1(n4289),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]) );
OAI22X1TS U5402 ( .A0(n4844), .A1(n4281), .B0(n5003), .B1(n4280), .Y(n4282)
);
AOI22X1TS U5403 ( .A0(n4284), .A1(n4283), .B0(n4030), .B1(n4282), .Y(n4293)
);
AOI22X1TS U5404 ( .A0(n4288), .A1(n4287), .B0(n4286), .B1(n4285), .Y(n4291)
);
AOI32X1TS U5405 ( .A0(n4293), .A1(n4292), .A2(n4291), .B0(n4290), .B1(n4289),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]) );
NAND3X1TS U5406 ( .A(cordic_FSM_state_reg[3]), .B(n4819), .C(n4890), .Y(
n4310) );
OR3X1TS U5407 ( .A(ack_cordic), .B(n4300), .C(n4812), .Y(n4306) );
OAI211XLTS U5408 ( .A0(cordic_FSM_state_reg[1]), .A1(n4331), .B0(
cordic_FSM_state_reg[3]), .C0(n4944), .Y(n4294) );
NAND4BXLTS U5409 ( .AN(n4295), .B(n4310), .C(n4306), .D(n4294), .Y(n2940) );
AOI32X1TS U5410 ( .A0(cordic_FSM_state_reg[0]), .A1(n4301), .A2(ack_cordic),
.B0(n4300), .B1(n4301), .Y(n2939) );
NAND4XLTS U5411 ( .A(add_subt_module_FS_Module_state_reg[2]), .B(
add_subt_module_FS_Module_state_reg[1]), .C(n4302), .D(n4944), .Y(
n4309) );
AOI21X1TS U5412 ( .A0(cordic_FSM_state_reg[3]), .A1(n4309), .B0(
cordic_FSM_state_reg[0]), .Y(n4303) );
BUFX4TS U5413 ( .A(n4305), .Y(n4532) );
NAND4XLTS U5414 ( .A(n4308), .B(n4307), .C(n4532), .D(n4306), .Y(n2938) );
INVX2TS U5415 ( .A(n4436), .Y(n4437) );
AOI2BB2XLTS U5416 ( .B0(n4455), .B1(n4993), .A0N(n4437), .A1N(
add_subt_module_FSM_selector_B[1]), .Y(n2935) );
NOR2X1TS U5417 ( .A(n4310), .B(n4309), .Y(n4432) );
NAND3X1TS U5418 ( .A(n4433), .B(n4432), .C(n4435), .Y(n4457) );
AO22XLTS U5419 ( .A0(d_ff_Xn[63]), .A1(n4497), .B0(d_ff2_X[63]), .B1(n4491),
.Y(n2931) );
OAI211XLTS U5420 ( .A0(add_subt_module_FS_Module_state_reg[3]), .A1(n4311),
.B0(n4317), .C0(n4884), .Y(n4316) );
AOI21X1TS U5421 ( .A0(n4316), .A1(n4315), .B0(n4314), .Y(n2929) );
AO21XLTS U5422 ( .A0(n4324), .A1(n4318), .B0(n4317), .Y(n4319) );
AOI22X1TS U5423 ( .A0(n4322), .A1(n4321), .B0(n4320), .B1(n4319), .Y(n4325)
);
NAND3XLTS U5424 ( .A(n4324), .B(n4323), .C(n4205), .Y(n4327) );
NAND4XLTS U5425 ( .A(n4325), .B(n4328), .C(n4470), .D(n4327), .Y(n2928) );
AOI211XLTS U5426 ( .A0(add_subt_module_FS_Module_state_reg[3]), .A1(n4811),
.B0(n4326), .C0(n3674), .Y(n4329) );
NAND3XLTS U5427 ( .A(n4329), .B(n4328), .C(n4327), .Y(n2927) );
NOR3X1TS U5428 ( .A(n4331), .B(cont_var_out[1]), .C(n4330), .Y(n4334) );
AOI31X1TS U5429 ( .A0(cont_var_out[0]), .A1(n4332), .A2(n4352), .B0(n4523),
.Y(n4333) );
OA21XLTS U5430 ( .A0(cont_var_out[0]), .A1(n4334), .B0(n4333), .Y(n2926) );
AO22XLTS U5431 ( .A0(cont_var_out[0]), .A1(n4334), .B0(cont_var_out[1]),
.B1(n4333), .Y(n2925) );
INVX2TS U5432 ( .A(n4335), .Y(n4338) );
OAI22X1TS U5433 ( .A0(n4346), .A1(n4887), .B0(n4336), .B1(n4338), .Y(n2924)
);
OAI21X1TS U5434 ( .A0(n4808), .A1(n4338), .B0(n4341), .Y(n4339) );
AOI21X1TS U5435 ( .A0(n4808), .A1(n4338), .B0(n4339), .Y(n2922) );
OAI22X1TS U5436 ( .A0(n4820), .A1(n4339), .B0(n4338), .B1(n4397), .Y(n2921)
);
BUFX3TS U5437 ( .A(n4337), .Y(n4340) );
AO22XLTS U5438 ( .A0(n4340), .A1(d_ff1_shift_region_flag_out[1]), .B0(n4342),
.B1(shift_region_flag[1]), .Y(n2918) );
AO22XLTS U5439 ( .A0(n4343), .A1(data_in[62]), .B0(n4340), .B1(d_ff1_Z[62]),
.Y(n2917) );
AO22XLTS U5440 ( .A0(n4343), .A1(data_in[61]), .B0(n4340), .B1(d_ff1_Z[61]),
.Y(n2916) );
AO22XLTS U5441 ( .A0(n4343), .A1(data_in[60]), .B0(n4340), .B1(d_ff1_Z[60]),
.Y(n2915) );
AO22XLTS U5442 ( .A0(n4343), .A1(data_in[59]), .B0(n4340), .B1(d_ff1_Z[59]),
.Y(n2914) );
AO22XLTS U5443 ( .A0(n4343), .A1(data_in[58]), .B0(n4340), .B1(d_ff1_Z[58]),
.Y(n2913) );
AO22XLTS U5444 ( .A0(n4343), .A1(data_in[57]), .B0(n4340), .B1(d_ff1_Z[57]),
.Y(n2912) );
AO22XLTS U5445 ( .A0(n4343), .A1(data_in[56]), .B0(n4340), .B1(d_ff1_Z[56]),
.Y(n2911) );
AO22XLTS U5446 ( .A0(n4343), .A1(data_in[55]), .B0(n4340), .B1(d_ff1_Z[55]),
.Y(n2910) );
AO22XLTS U5447 ( .A0(n4343), .A1(data_in[54]), .B0(n4340), .B1(d_ff1_Z[54]),
.Y(n2909) );
AO22XLTS U5448 ( .A0(n4343), .A1(data_in[53]), .B0(n4340), .B1(d_ff1_Z[53]),
.Y(n2908) );
AO22XLTS U5449 ( .A0(n4343), .A1(data_in[52]), .B0(n4344), .B1(d_ff1_Z[52]),
.Y(n2907) );
AO22XLTS U5450 ( .A0(n4346), .A1(data_in[51]), .B0(n4344), .B1(d_ff1_Z[51]),
.Y(n2906) );
AO22XLTS U5451 ( .A0(n4342), .A1(data_in[50]), .B0(n4344), .B1(d_ff1_Z[50]),
.Y(n2905) );
AO22XLTS U5452 ( .A0(n4342), .A1(data_in[49]), .B0(n4344), .B1(d_ff1_Z[49]),
.Y(n2904) );
AO22XLTS U5453 ( .A0(n4342), .A1(data_in[48]), .B0(n4344), .B1(d_ff1_Z[48]),
.Y(n2903) );
AO22XLTS U5454 ( .A0(n4342), .A1(data_in[47]), .B0(n4344), .B1(d_ff1_Z[47]),
.Y(n2902) );
AO22XLTS U5455 ( .A0(n4342), .A1(data_in[46]), .B0(n4337), .B1(d_ff1_Z[46]),
.Y(n2901) );
AO22XLTS U5456 ( .A0(n4342), .A1(data_in[45]), .B0(n4341), .B1(d_ff1_Z[45]),
.Y(n2900) );
AO22XLTS U5457 ( .A0(n4342), .A1(data_in[44]), .B0(n4341), .B1(d_ff1_Z[44]),
.Y(n2899) );
AO22XLTS U5458 ( .A0(n4342), .A1(data_in[43]), .B0(n4341), .B1(d_ff1_Z[43]),
.Y(n2898) );
AO22XLTS U5459 ( .A0(n4342), .A1(data_in[42]), .B0(n4341), .B1(d_ff1_Z[42]),
.Y(n2897) );
AO22XLTS U5460 ( .A0(n4342), .A1(data_in[41]), .B0(n4341), .B1(d_ff1_Z[41]),
.Y(n2896) );
AO22XLTS U5461 ( .A0(n4342), .A1(data_in[40]), .B0(n4341), .B1(d_ff1_Z[40]),
.Y(n2895) );
AO22XLTS U5462 ( .A0(n4342), .A1(data_in[39]), .B0(n4341), .B1(d_ff1_Z[39]),
.Y(n2894) );
AO22XLTS U5463 ( .A0(n4343), .A1(data_in[38]), .B0(n4341), .B1(d_ff1_Z[38]),
.Y(n2893) );
INVX2TS U5464 ( .A(n4337), .Y(n4347) );
AO22XLTS U5465 ( .A0(n4346), .A1(data_in[37]), .B0(n4341), .B1(d_ff1_Z[37]),
.Y(n2892) );
AO22XLTS U5466 ( .A0(n4346), .A1(data_in[36]), .B0(n4341), .B1(d_ff1_Z[36]),
.Y(n2891) );
AO22XLTS U5467 ( .A0(n4346), .A1(data_in[35]), .B0(n4341), .B1(d_ff1_Z[35]),
.Y(n2890) );
AO22XLTS U5468 ( .A0(n4346), .A1(data_in[34]), .B0(n4341), .B1(d_ff1_Z[34]),
.Y(n2889) );
AO22XLTS U5469 ( .A0(n4347), .A1(data_in[33]), .B0(n4344), .B1(d_ff1_Z[33]),
.Y(n2888) );
AO22XLTS U5470 ( .A0(n4347), .A1(data_in[32]), .B0(n4344), .B1(d_ff1_Z[32]),
.Y(n2887) );
AO22XLTS U5471 ( .A0(n4347), .A1(data_in[31]), .B0(n4344), .B1(d_ff1_Z[31]),
.Y(n2886) );
AO22XLTS U5472 ( .A0(n4347), .A1(data_in[30]), .B0(n4344), .B1(d_ff1_Z[30]),
.Y(n2885) );
AO22XLTS U5473 ( .A0(n4347), .A1(data_in[29]), .B0(n4344), .B1(d_ff1_Z[29]),
.Y(n2884) );
AO22XLTS U5474 ( .A0(n4347), .A1(data_in[28]), .B0(n4344), .B1(d_ff1_Z[28]),
.Y(n2883) );
AO22XLTS U5475 ( .A0(n4343), .A1(data_in[27]), .B0(n4341), .B1(d_ff1_Z[27]),
.Y(n2882) );
AO22XLTS U5476 ( .A0(n4347), .A1(data_in[26]), .B0(n4341), .B1(d_ff1_Z[26]),
.Y(n2881) );
AO22XLTS U5477 ( .A0(n4347), .A1(data_in[25]), .B0(n4341), .B1(d_ff1_Z[25]),
.Y(n2880) );
AO22XLTS U5478 ( .A0(n4343), .A1(data_in[24]), .B0(n4341), .B1(d_ff1_Z[24]),
.Y(n2879) );
AO22XLTS U5479 ( .A0(n4342), .A1(data_in[23]), .B0(n4337), .B1(d_ff1_Z[23]),
.Y(n2878) );
AO22XLTS U5480 ( .A0(n4343), .A1(data_in[22]), .B0(n4337), .B1(d_ff1_Z[22]),
.Y(n2877) );
AO22XLTS U5481 ( .A0(n4342), .A1(data_in[21]), .B0(n4337), .B1(d_ff1_Z[21]),
.Y(n2876) );
AO22XLTS U5482 ( .A0(n4343), .A1(data_in[20]), .B0(n4337), .B1(d_ff1_Z[20]),
.Y(n2875) );
AO22XLTS U5483 ( .A0(n4342), .A1(data_in[19]), .B0(n4337), .B1(d_ff1_Z[19]),
.Y(n2874) );
AO22XLTS U5484 ( .A0(n4343), .A1(data_in[18]), .B0(n4337), .B1(d_ff1_Z[18]),
.Y(n2873) );
AO22XLTS U5485 ( .A0(n4342), .A1(data_in[17]), .B0(n4337), .B1(d_ff1_Z[17]),
.Y(n2872) );
AO22XLTS U5486 ( .A0(n4343), .A1(data_in[16]), .B0(n4337), .B1(d_ff1_Z[16]),
.Y(n2871) );
AO22XLTS U5487 ( .A0(n4342), .A1(data_in[15]), .B0(n4337), .B1(d_ff1_Z[15]),
.Y(n2870) );
AO22XLTS U5488 ( .A0(n4343), .A1(data_in[14]), .B0(n4337), .B1(d_ff1_Z[14]),
.Y(n2869) );
AO22XLTS U5489 ( .A0(n4342), .A1(data_in[13]), .B0(n4337), .B1(d_ff1_Z[13]),
.Y(n2868) );
AO22XLTS U5490 ( .A0(n4343), .A1(data_in[12]), .B0(n4344), .B1(d_ff1_Z[12]),
.Y(n2867) );
AO22XLTS U5491 ( .A0(n4343), .A1(data_in[11]), .B0(n4344), .B1(d_ff1_Z[11]),
.Y(n2866) );
AO22XLTS U5492 ( .A0(n4346), .A1(data_in[10]), .B0(n4344), .B1(d_ff1_Z[10]),
.Y(n2865) );
AO22XLTS U5493 ( .A0(n4346), .A1(data_in[9]), .B0(n4344), .B1(d_ff1_Z[9]),
.Y(n2864) );
AO22XLTS U5494 ( .A0(n4346), .A1(data_in[8]), .B0(n4344), .B1(d_ff1_Z[8]),
.Y(n2863) );
AO22XLTS U5495 ( .A0(n4346), .A1(data_in[7]), .B0(n4344), .B1(d_ff1_Z[7]),
.Y(n2862) );
AO22XLTS U5496 ( .A0(n4346), .A1(data_in[6]), .B0(n4344), .B1(d_ff1_Z[6]),
.Y(n2861) );
AO22XLTS U5497 ( .A0(n4346), .A1(data_in[5]), .B0(n4344), .B1(d_ff1_Z[5]),
.Y(n2860) );
AO22XLTS U5498 ( .A0(n4346), .A1(data_in[4]), .B0(n4344), .B1(d_ff1_Z[4]),
.Y(n2859) );
AO22XLTS U5499 ( .A0(n4346), .A1(data_in[3]), .B0(n4344), .B1(d_ff1_Z[3]),
.Y(n2858) );
AO22XLTS U5500 ( .A0(n4346), .A1(data_in[2]), .B0(n4344), .B1(d_ff1_Z[2]),
.Y(n2857) );
AO22XLTS U5501 ( .A0(n4346), .A1(data_in[1]), .B0(n4341), .B1(d_ff1_Z[1]),
.Y(n2856) );
AO22XLTS U5502 ( .A0(n4346), .A1(data_in[0]), .B0(n4337), .B1(d_ff1_Z[0]),
.Y(n2855) );
AO22XLTS U5503 ( .A0(n4347), .A1(data_in[63]), .B0(n4341), .B1(d_ff1_Z[63]),
.Y(n2854) );
NAND3XLTS U5504 ( .A(n4348), .B(n4351), .C(n4355), .Y(n4350) );
AOI32X1TS U5505 ( .A0(n4351), .A1(n4350), .A2(n4349), .B0(n5010), .B1(n4350),
.Y(n2853) );
INVX4TS U5506 ( .A(n4421), .Y(n4488) );
AO22XLTS U5507 ( .A0(n4493), .A1(n4352), .B0(n4421), .B1(d_ff3_LUT_out[56]),
.Y(n2850) );
OA22X1TS U5508 ( .A0(n4354), .A1(n4353), .B0(n4510), .B1(d_ff3_LUT_out[55]),
.Y(n2849) );
OAI31X1TS U5509 ( .A0(cont_iter_out[0]), .A1(n4887), .A2(n4397), .B0(n4355),
.Y(n4386) );
INVX2TS U5510 ( .A(n4386), .Y(n4356) );
AOI2BB2XLTS U5511 ( .B0(n4357), .B1(n4356), .A0N(n4510), .A1N(
d_ff3_LUT_out[54]), .Y(n2848) );
AO22XLTS U5512 ( .A0(n4521), .A1(n4358), .B0(n4525), .B1(d_ff3_LUT_out[53]),
.Y(n2847) );
INVX4TS U5513 ( .A(n4421), .Y(n4494) );
AO22XLTS U5514 ( .A0(n4496), .A1(cont_iter_out[0]), .B0(n4525), .B1(
d_ff3_LUT_out[52]), .Y(n2846) );
AOI2BB2XLTS U5515 ( .B0(n4390), .B1(n4359), .A0N(n4495), .A1N(
d_ff3_LUT_out[50]), .Y(n2845) );
AO21XLTS U5516 ( .A0(d_ff3_LUT_out[49]), .A1(n4423), .B0(n4363), .Y(n2844)
);
OA21XLTS U5517 ( .A0(n4494), .A1(d_ff3_LUT_out[47]), .B0(n4362), .Y(n2842)
);
AO21XLTS U5518 ( .A0(d_ff3_LUT_out[46]), .A1(n4423), .B0(n4363), .Y(n2841)
);
AOI2BB2XLTS U5519 ( .B0(n4360), .B1(n4390), .A0N(n4495), .A1N(
d_ff3_LUT_out[45]), .Y(n2840) );
AO21XLTS U5520 ( .A0(d_ff3_LUT_out[44]), .A1(n4423), .B0(n4363), .Y(n2839)
);
BUFX3TS U5521 ( .A(n4507), .Y(n4529) );
OAI2BB1X1TS U5522 ( .A0N(d_ff3_LUT_out[43]), .A1N(n4529), .B0(n4361), .Y(
n2838) );
OA21XLTS U5523 ( .A0(n4530), .A1(d_ff3_LUT_out[42]), .B0(n4362), .Y(n2837)
);
OAI2BB1X1TS U5524 ( .A0N(d_ff3_LUT_out[40]), .A1N(n4423), .B0(n4366), .Y(
n2835) );
AOI2BB1XLTS U5525 ( .A0N(n4510), .A1N(d_ff3_LUT_out[39]), .B0(n4385), .Y(
n2834) );
OAI2BB1X1TS U5526 ( .A0N(d_ff3_LUT_out[38]), .A1N(n4518), .B0(n4364), .Y(
n2833) );
AOI2BB2XLTS U5527 ( .B0(cont_iter_out[2]), .B1(n4390), .A0N(n4495), .A1N(
d_ff3_LUT_out[37]), .Y(n2832) );
OAI2BB1X1TS U5528 ( .A0N(d_ff3_LUT_out[36]), .A1N(n4423), .B0(n4366), .Y(
n2831) );
AOI2BB1XLTS U5529 ( .A0N(n4510), .A1N(d_ff3_LUT_out[35]), .B0(n4375), .Y(
n2830) );
OAI2BB1X1TS U5530 ( .A0N(d_ff3_LUT_out[32]), .A1N(n4423), .B0(n4364), .Y(
n2827) );
AO21XLTS U5531 ( .A0(d_ff3_LUT_out[30]), .A1(n4423), .B0(n4396), .Y(n2825)
);
OA21XLTS U5532 ( .A0(n4530), .A1(d_ff3_LUT_out[29]), .B0(n4365), .Y(n2824)
);
OAI2BB1X1TS U5533 ( .A0N(d_ff3_LUT_out[28]), .A1N(n4423), .B0(n4366), .Y(
n2823) );
AOI2BB2XLTS U5534 ( .B0(n4368), .B1(n4378), .A0N(n4510), .A1N(
d_ff3_LUT_out[26]), .Y(n2821) );
NAND2X1TS U5535 ( .A(n4369), .B(n4383), .Y(n4370) );
AOI32X1TS U5536 ( .A0(n4371), .A1(n4498), .A2(n4370), .B0(n5074), .B1(n4421),
.Y(n2818) );
OA21XLTS U5537 ( .A0(n4496), .A1(d_ff3_LUT_out[22]), .B0(n4372), .Y(n2817)
);
AO22XLTS U5538 ( .A0(n4390), .A1(n4373), .B0(d_ff3_LUT_out[21]), .B1(n4423),
.Y(n2816) );
OAI2BB1X1TS U5539 ( .A0N(d_ff3_LUT_out[20]), .A1N(n4423), .B0(n4374), .Y(
n2815) );
AOI2BB2XLTS U5540 ( .B0(n4375), .B1(n4394), .A0N(n4510), .A1N(
d_ff3_LUT_out[18]), .Y(n2813) );
OAI2BB1X1TS U5541 ( .A0N(d_ff3_LUT_out[17]), .A1N(n4423), .B0(n4402), .Y(
n2812) );
INVX4TS U5542 ( .A(n4421), .Y(n4498) );
AO22XLTS U5543 ( .A0(n4496), .A1(n4376), .B0(n4525), .B1(d_ff3_LUT_out[16]),
.Y(n2811) );
OAI211X1TS U5544 ( .A0(n4379), .A1(n4378), .B0(n4377), .C0(n4394), .Y(n4387)
);
OA21XLTS U5545 ( .A0(n4494), .A1(d_ff3_LUT_out[15]), .B0(n4387), .Y(n2810)
);
OAI2BB2XLTS U5546 ( .B0(n4381), .B1(n4380), .A0N(d_ff3_LUT_out[14]), .A1N(
n4421), .Y(n2809) );
NOR2XLTS U5547 ( .A(n4393), .B(n4507), .Y(n4382) );
OAI21XLTS U5548 ( .A0(n4383), .A1(n4397), .B0(n4382), .Y(n4384) );
OAI2BB1X1TS U5549 ( .A0N(d_ff3_LUT_out[13]), .A1N(n4423), .B0(n4384), .Y(
n2808) );
INVX2TS U5550 ( .A(n4385), .Y(n4388) );
AOI211XLTS U5551 ( .A0(n4388), .A1(n4387), .B0(n4399), .C0(n4386), .Y(n4389)
);
AOI2BB1XLTS U5552 ( .A0N(n4510), .A1N(d_ff3_LUT_out[11]), .B0(n4389), .Y(
n2806) );
AOI22X1TS U5553 ( .A0(n5076), .A1(n4421), .B0(n4391), .B1(n4390), .Y(n2803)
);
AOI2BB1XLTS U5554 ( .A0N(n4510), .A1N(d_ff3_LUT_out[7]), .B0(n4392), .Y(
n2802) );
NOR2XLTS U5555 ( .A(n4393), .B(n4399), .Y(n4395) );
AOI32X1TS U5556 ( .A0(n4395), .A1(n4523), .A2(n4394), .B0(n4421), .B1(n5073),
.Y(n2801) );
AO21XLTS U5557 ( .A0(d_ff3_LUT_out[4]), .A1(n4525), .B0(n4396), .Y(n2799) );
AOI2BB2XLTS U5558 ( .B0(n4398), .B1(n4397), .A0N(n4495), .A1N(
d_ff3_LUT_out[2]), .Y(n2797) );
AOI21X1TS U5559 ( .A0(n4401), .A1(n4400), .B0(n4399), .Y(n4403) );
AOI2BB2XLTS U5560 ( .B0(n4403), .B1(n4402), .A0N(n4510), .A1N(
d_ff3_LUT_out[1]), .Y(n2796) );
INVX4TS U5561 ( .A(n4421), .Y(n4530) );
AO22XLTS U5562 ( .A0(n4494), .A1(d_ff2_X[63]), .B0(n4525), .B1(
d_ff3_sh_x_out[63]), .Y(n2794) );
AO22XLTS U5563 ( .A0(d_ff2_X[62]), .A1(n4491), .B0(d_ff_Xn[62]), .B1(n4487),
.Y(n2793) );
OA22X1TS U5564 ( .A0(d_ff_Xn[61]), .A1(n2955), .B0(d_ff2_X[61]), .B1(n3001),
.Y(n2792) );
INVX1TS U5565 ( .A(d_ff2_X[60]), .Y(n4414) );
AOI2BB2XLTS U5566 ( .B0(n4414), .B1(n4491), .A0N(d_ff_Xn[60]), .A1N(n2955),
.Y(n2791) );
INVX1TS U5567 ( .A(d_ff2_X[58]), .Y(n4409) );
AOI2BB2XLTS U5568 ( .B0(n4409), .B1(n4404), .A0N(d_ff_Xn[58]), .A1N(n2955),
.Y(n2789) );
OA22X1TS U5569 ( .A0(d_ff_Xn[57]), .A1(n4502), .B0(d_ff2_X[57]), .B1(n4425),
.Y(n2788) );
OA22X1TS U5570 ( .A0(d_ff_Xn[56]), .A1(n4502), .B0(d_ff2_X[56]), .B1(n4425),
.Y(n2787) );
OA22X1TS U5571 ( .A0(n4425), .A1(d_ff2_X[55]), .B0(d_ff_Xn[55]), .B1(n2955),
.Y(n2786) );
OA22X1TS U5572 ( .A0(n4425), .A1(d_ff2_X[54]), .B0(d_ff_Xn[54]), .B1(n4502),
.Y(n2785) );
AO22XLTS U5573 ( .A0(d_ff2_X[52]), .A1(n4404), .B0(d_ff_Xn[52]), .B1(n4424),
.Y(n2783) );
OAI21XLTS U5574 ( .A0(cont_iter_out[0]), .A1(n4937), .B0(intadd_375_CI), .Y(
n4405) );
AO22XLTS U5575 ( .A0(n4488), .A1(n4405), .B0(n4525), .B1(d_ff3_sh_x_out[52]),
.Y(n2782) );
NAND2X1TS U5576 ( .A(d_ff2_X[56]), .B(intadd_375_n1), .Y(n4406) );
AOI32X1TS U5577 ( .A0(n4407), .A1(n4521), .A2(n4406), .B0(n5075), .B1(n4421),
.Y(n2778) );
AOI21X1TS U5578 ( .A0(d_ff2_X[57]), .A1(n4407), .B0(n4410), .Y(n4408) );
AOI2BB2XLTS U5579 ( .B0(n4523), .B1(n4408), .A0N(d_ff3_sh_x_out[57]), .A1N(
n4498), .Y(n2777) );
NAND2X1TS U5580 ( .A(n4410), .B(n4409), .Y(n4412) );
OAI21XLTS U5581 ( .A0(n4410), .A1(n4409), .B0(n4412), .Y(n4411) );
AO22XLTS U5582 ( .A0(n4493), .A1(n4411), .B0(n4525), .B1(d_ff3_sh_x_out[58]),
.Y(n2776) );
INVX4TS U5583 ( .A(n4421), .Y(n4496) );
AOI21X1TS U5584 ( .A0(d_ff2_X[59]), .A1(n4412), .B0(n4415), .Y(n4413) );
AOI2BB2XLTS U5585 ( .B0(n4521), .B1(n4413), .A0N(d_ff3_sh_x_out[59]), .A1N(
n4530), .Y(n2775) );
NAND2X1TS U5586 ( .A(n4415), .B(n4414), .Y(n4417) );
OAI21XLTS U5587 ( .A0(n4415), .A1(n4414), .B0(n4417), .Y(n4416) );
BUFX4TS U5588 ( .A(n4525), .Y(n4518) );
BUFX3TS U5589 ( .A(n4518), .Y(n4490) );
AO22XLTS U5590 ( .A0(n4498), .A1(n4416), .B0(n4490), .B1(d_ff3_sh_x_out[60]),
.Y(n2774) );
NOR2X1TS U5591 ( .A(d_ff2_X[61]), .B(n4417), .Y(n4419) );
AOI21X1TS U5592 ( .A0(d_ff2_X[61]), .A1(n4417), .B0(n4419), .Y(n4418) );
AOI2BB2XLTS U5593 ( .B0(n4498), .B1(n4418), .A0N(d_ff3_sh_x_out[61]), .A1N(
n4488), .Y(n2773) );
XOR2XLTS U5594 ( .A(d_ff2_X[62]), .B(n4419), .Y(n4420) );
BUFX3TS U5595 ( .A(n4518), .Y(n4499) );
AO22XLTS U5596 ( .A0(n4488), .A1(n4420), .B0(n4499), .B1(d_ff3_sh_x_out[62]),
.Y(n2772) );
AO22XLTS U5597 ( .A0(d_ff_Xn[51]), .A1(n4492), .B0(d_ff2_X[51]), .B1(n4500),
.Y(n2771) );
BUFX3TS U5598 ( .A(n4518), .Y(n4489) );
AO22XLTS U5599 ( .A0(n4496), .A1(d_ff2_X[51]), .B0(n4489), .B1(
d_ff3_sh_x_out[51]), .Y(n2770) );
AO22XLTS U5600 ( .A0(d_ff_Xn[50]), .A1(n4492), .B0(d_ff2_X[50]), .B1(n4500),
.Y(n2769) );
AO22XLTS U5601 ( .A0(n4488), .A1(d_ff2_X[50]), .B0(n4507), .B1(
d_ff3_sh_x_out[50]), .Y(n2768) );
AO22XLTS U5602 ( .A0(n4494), .A1(d_ff2_X[49]), .B0(n4507), .B1(
d_ff3_sh_x_out[49]), .Y(n2766) );
OA22X1TS U5603 ( .A0(n4425), .A1(d_ff2_X[48]), .B0(d_ff_Xn[48]), .B1(n4422),
.Y(n2765) );
AO22XLTS U5604 ( .A0(n4496), .A1(d_ff2_X[48]), .B0(n4421), .B1(
d_ff3_sh_x_out[48]), .Y(n2764) );
AO22XLTS U5605 ( .A0(d_ff_Xn[47]), .A1(n3304), .B0(d_ff2_X[47]), .B1(n4500),
.Y(n2763) );
AO22XLTS U5606 ( .A0(n4496), .A1(d_ff2_X[47]), .B0(n4507), .B1(
d_ff3_sh_x_out[47]), .Y(n2762) );
OA22X1TS U5607 ( .A0(n4425), .A1(d_ff2_X[46]), .B0(d_ff_Xn[46]), .B1(n2955),
.Y(n2761) );
AO22XLTS U5608 ( .A0(n4530), .A1(d_ff2_X[46]), .B0(n4507), .B1(
d_ff3_sh_x_out[46]), .Y(n2760) );
OA22X1TS U5609 ( .A0(n4425), .A1(d_ff2_X[45]), .B0(d_ff_Xn[45]), .B1(n2955),
.Y(n2759) );
AO22XLTS U5610 ( .A0(n4523), .A1(d_ff2_X[45]), .B0(n4507), .B1(
d_ff3_sh_x_out[45]), .Y(n2758) );
AO22XLTS U5611 ( .A0(d_ff_Xn[44]), .A1(n3298), .B0(d_ff2_X[44]), .B1(n4500),
.Y(n2757) );
AO22XLTS U5612 ( .A0(n4523), .A1(d_ff2_X[44]), .B0(n4507), .B1(
d_ff3_sh_x_out[44]), .Y(n2756) );
OA22X1TS U5613 ( .A0(n4425), .A1(d_ff2_X[43]), .B0(d_ff_Xn[43]), .B1(n2955),
.Y(n2755) );
AO22XLTS U5614 ( .A0(n4523), .A1(d_ff2_X[43]), .B0(n4507), .B1(
d_ff3_sh_x_out[43]), .Y(n2754) );
OA22X1TS U5615 ( .A0(n4425), .A1(d_ff2_X[42]), .B0(d_ff_Xn[42]), .B1(n2955),
.Y(n2753) );
AO22XLTS U5616 ( .A0(n4523), .A1(d_ff2_X[42]), .B0(n4507), .B1(
d_ff3_sh_x_out[42]), .Y(n2752) );
OA22X1TS U5617 ( .A0(n4425), .A1(d_ff2_X[41]), .B0(d_ff_Xn[41]), .B1(n2955),
.Y(n2751) );
AO22XLTS U5618 ( .A0(n4523), .A1(d_ff2_X[41]), .B0(n4421), .B1(
d_ff3_sh_x_out[41]), .Y(n2750) );
AO22XLTS U5619 ( .A0(d_ff_Xn[40]), .A1(n3298), .B0(d_ff2_X[40]), .B1(n3305),
.Y(n2749) );
AO22XLTS U5620 ( .A0(n4523), .A1(d_ff2_X[40]), .B0(n4421), .B1(
d_ff3_sh_x_out[40]), .Y(n2748) );
OA22X1TS U5621 ( .A0(n4503), .A1(d_ff2_X[39]), .B0(d_ff_Xn[39]), .B1(n2955),
.Y(n2747) );
AO22XLTS U5622 ( .A0(n4523), .A1(d_ff2_X[39]), .B0(n4525), .B1(
d_ff3_sh_x_out[39]), .Y(n2746) );
AO22XLTS U5623 ( .A0(d_ff_Xn[38]), .A1(n4492), .B0(d_ff2_X[38]), .B1(n4500),
.Y(n2745) );
AO22XLTS U5624 ( .A0(n4523), .A1(d_ff2_X[38]), .B0(n4525), .B1(
d_ff3_sh_x_out[38]), .Y(n2744) );
AO22XLTS U5625 ( .A0(d_ff_Xn[37]), .A1(n3301), .B0(d_ff2_X[37]), .B1(n4500),
.Y(n2743) );
AO22XLTS U5626 ( .A0(n4496), .A1(d_ff2_X[37]), .B0(n4525), .B1(
d_ff3_sh_x_out[37]), .Y(n2742) );
OA22X1TS U5627 ( .A0(n4503), .A1(d_ff2_X[36]), .B0(d_ff_Xn[36]), .B1(n2955),
.Y(n2741) );
AO22XLTS U5628 ( .A0(n4488), .A1(d_ff2_X[36]), .B0(n4525), .B1(
d_ff3_sh_x_out[36]), .Y(n2740) );
OA22X1TS U5629 ( .A0(n4503), .A1(d_ff2_X[35]), .B0(d_ff_Xn[35]), .B1(n2955),
.Y(n2739) );
AO22XLTS U5630 ( .A0(n4530), .A1(d_ff2_X[35]), .B0(n4525), .B1(
d_ff3_sh_x_out[35]), .Y(n2738) );
OA22X1TS U5631 ( .A0(n4503), .A1(d_ff2_X[34]), .B0(d_ff_Xn[34]), .B1(n2955),
.Y(n2737) );
AO22XLTS U5632 ( .A0(n4494), .A1(d_ff2_X[34]), .B0(n4525), .B1(
d_ff3_sh_x_out[34]), .Y(n2736) );
AO22XLTS U5633 ( .A0(d_ff_Xn[33]), .A1(n4528), .B0(d_ff2_X[33]), .B1(n4501),
.Y(n2735) );
AO22XLTS U5634 ( .A0(n4496), .A1(d_ff2_X[33]), .B0(n4525), .B1(
d_ff3_sh_x_out[33]), .Y(n2734) );
OA22X1TS U5635 ( .A0(n4425), .A1(d_ff2_X[32]), .B0(d_ff_Xn[32]), .B1(n2955),
.Y(n2733) );
AO22XLTS U5636 ( .A0(n4488), .A1(d_ff2_X[32]), .B0(n4525), .B1(
d_ff3_sh_x_out[32]), .Y(n2732) );
OA22X1TS U5637 ( .A0(n4425), .A1(d_ff2_X[31]), .B0(d_ff_Xn[31]), .B1(n2955),
.Y(n2731) );
AO22XLTS U5638 ( .A0(n4494), .A1(d_ff2_X[31]), .B0(n4529), .B1(
d_ff3_sh_x_out[31]), .Y(n2730) );
AO22XLTS U5639 ( .A0(d_ff_Xn[30]), .A1(n4492), .B0(d_ff2_X[30]), .B1(n4500),
.Y(n2729) );
AO22XLTS U5640 ( .A0(n4496), .A1(d_ff2_X[30]), .B0(n4529), .B1(
d_ff3_sh_x_out[30]), .Y(n2728) );
AO22XLTS U5641 ( .A0(n4488), .A1(d_ff2_X[29]), .B0(n4529), .B1(
d_ff3_sh_x_out[29]), .Y(n2726) );
AO22XLTS U5642 ( .A0(n4494), .A1(d_ff2_X[28]), .B0(n4529), .B1(
d_ff3_sh_x_out[28]), .Y(n2724) );
AO22XLTS U5643 ( .A0(d_ff_Xn[27]), .A1(n3304), .B0(d_ff2_X[27]), .B1(n4500),
.Y(n2723) );
AO22XLTS U5644 ( .A0(n4496), .A1(d_ff2_X[27]), .B0(n4529), .B1(
d_ff3_sh_x_out[27]), .Y(n2722) );
AO22XLTS U5645 ( .A0(n4488), .A1(d_ff2_X[26]), .B0(n4529), .B1(
d_ff3_sh_x_out[26]), .Y(n2720) );
AO22XLTS U5646 ( .A0(d_ff_Xn[25]), .A1(n4492), .B0(d_ff2_X[25]), .B1(n3305),
.Y(n2719) );
AO22XLTS U5647 ( .A0(n4530), .A1(d_ff2_X[25]), .B0(n4529), .B1(
d_ff3_sh_x_out[25]), .Y(n2718) );
AO22XLTS U5648 ( .A0(n4494), .A1(d_ff2_X[24]), .B0(n4529), .B1(
d_ff3_sh_x_out[24]), .Y(n2716) );
AO22XLTS U5649 ( .A0(d_ff_Xn[23]), .A1(n3298), .B0(d_ff2_X[23]), .B1(n4500),
.Y(n2715) );
AO22XLTS U5650 ( .A0(n4523), .A1(d_ff2_X[23]), .B0(n4426), .B1(
d_ff3_sh_x_out[23]), .Y(n2714) );
AO22XLTS U5651 ( .A0(d_ff_Xn[22]), .A1(n4424), .B0(d_ff2_X[22]), .B1(n4501),
.Y(n2713) );
AO22XLTS U5652 ( .A0(n4523), .A1(d_ff2_X[22]), .B0(n4529), .B1(
d_ff3_sh_x_out[22]), .Y(n2712) );
AO22XLTS U5653 ( .A0(d_ff_Xn[21]), .A1(n4424), .B0(d_ff2_X[21]), .B1(n4500),
.Y(n2711) );
AO22XLTS U5654 ( .A0(n4523), .A1(d_ff2_X[21]), .B0(n4529), .B1(
d_ff3_sh_x_out[21]), .Y(n2710) );
AO22XLTS U5655 ( .A0(d_ff_Xn[20]), .A1(n4424), .B0(d_ff2_X[20]), .B1(n4500),
.Y(n2709) );
AO22XLTS U5656 ( .A0(n4523), .A1(d_ff2_X[20]), .B0(n4426), .B1(
d_ff3_sh_x_out[20]), .Y(n2708) );
AO22XLTS U5657 ( .A0(n4523), .A1(d_ff2_X[19]), .B0(n4426), .B1(
d_ff3_sh_x_out[19]), .Y(n2706) );
AO22XLTS U5658 ( .A0(d_ff_Xn[18]), .A1(n4424), .B0(d_ff2_X[18]), .B1(n4501),
.Y(n2705) );
AO22XLTS U5659 ( .A0(n4523), .A1(d_ff2_X[18]), .B0(n4426), .B1(
d_ff3_sh_x_out[18]), .Y(n2704) );
AO22XLTS U5660 ( .A0(d_ff_Xn[17]), .A1(n4424), .B0(d_ff2_X[17]), .B1(n4500),
.Y(n2703) );
AO22XLTS U5661 ( .A0(n4495), .A1(d_ff2_X[17]), .B0(n4426), .B1(
d_ff3_sh_x_out[17]), .Y(n2702) );
AO22XLTS U5662 ( .A0(d_ff_Xn[16]), .A1(n4424), .B0(d_ff2_X[16]), .B1(n4500),
.Y(n2701) );
AO22XLTS U5663 ( .A0(n4530), .A1(d_ff2_X[16]), .B0(n4426), .B1(
d_ff3_sh_x_out[16]), .Y(n2700) );
AO22XLTS U5664 ( .A0(d_ff_Xn[15]), .A1(n4424), .B0(d_ff2_X[15]), .B1(n4501),
.Y(n2699) );
AO22XLTS U5665 ( .A0(n4495), .A1(d_ff2_X[15]), .B0(n4426), .B1(
d_ff3_sh_x_out[15]), .Y(n2698) );
OA22X1TS U5666 ( .A0(n3001), .A1(d_ff2_X[14]), .B0(d_ff_Xn[14]), .B1(n4422),
.Y(n2697) );
AO22XLTS U5667 ( .A0(n4496), .A1(d_ff2_X[14]), .B0(n4529), .B1(
d_ff3_sh_x_out[14]), .Y(n2696) );
AO22XLTS U5668 ( .A0(n4495), .A1(d_ff2_X[13]), .B0(n4423), .B1(
d_ff3_sh_x_out[13]), .Y(n2694) );
AO22XLTS U5669 ( .A0(d_ff_Xn[12]), .A1(n4424), .B0(d_ff2_X[12]), .B1(n4501),
.Y(n2693) );
AO22XLTS U5670 ( .A0(n4496), .A1(d_ff2_X[12]), .B0(n4426), .B1(
d_ff3_sh_x_out[12]), .Y(n2692) );
AO22XLTS U5671 ( .A0(n4495), .A1(d_ff2_X[11]), .B0(n4529), .B1(
d_ff3_sh_x_out[11]), .Y(n2690) );
AO22XLTS U5672 ( .A0(d_ff_Xn[10]), .A1(n4424), .B0(d_ff2_X[10]), .B1(n4500),
.Y(n2689) );
AO22XLTS U5673 ( .A0(n4488), .A1(d_ff2_X[10]), .B0(n4426), .B1(
d_ff3_sh_x_out[10]), .Y(n2688) );
AO22XLTS U5674 ( .A0(n4510), .A1(d_ff2_X[9]), .B0(n4426), .B1(
d_ff3_sh_x_out[9]), .Y(n2686) );
AO22XLTS U5675 ( .A0(n4521), .A1(d_ff2_X[8]), .B0(n4426), .B1(
d_ff3_sh_x_out[8]), .Y(n2684) );
AO22XLTS U5676 ( .A0(n4510), .A1(d_ff2_X[7]), .B0(n4426), .B1(
d_ff3_sh_x_out[7]), .Y(n2682) );
OA22X1TS U5677 ( .A0(n3001), .A1(d_ff2_X[6]), .B0(d_ff_Xn[6]), .B1(n4502),
.Y(n2681) );
AO22XLTS U5678 ( .A0(n4530), .A1(d_ff2_X[6]), .B0(n4426), .B1(
d_ff3_sh_x_out[6]), .Y(n2680) );
AO22XLTS U5679 ( .A0(d_ff_Xn[5]), .A1(n4424), .B0(d_ff2_X[5]), .B1(n4500),
.Y(n2679) );
AO22XLTS U5680 ( .A0(n4510), .A1(d_ff2_X[5]), .B0(n4426), .B1(
d_ff3_sh_x_out[5]), .Y(n2678) );
AO22XLTS U5681 ( .A0(d_ff_Xn[4]), .A1(n4424), .B0(d_ff2_X[4]), .B1(n4500),
.Y(n2677) );
AO22XLTS U5682 ( .A0(n4494), .A1(d_ff2_X[4]), .B0(n4426), .B1(
d_ff3_sh_x_out[4]), .Y(n2676) );
OA22X1TS U5683 ( .A0(n3001), .A1(d_ff2_X[3]), .B0(d_ff_Xn[3]), .B1(n4502),
.Y(n2675) );
AO22XLTS U5684 ( .A0(n4488), .A1(d_ff2_X[3]), .B0(n4426), .B1(
d_ff3_sh_x_out[3]), .Y(n2674) );
AO22XLTS U5685 ( .A0(d_ff_Xn[2]), .A1(n4424), .B0(d_ff2_X[2]), .B1(n4500),
.Y(n2673) );
AO22XLTS U5686 ( .A0(n4496), .A1(d_ff2_X[2]), .B0(n4426), .B1(
d_ff3_sh_x_out[2]), .Y(n2672) );
AO22XLTS U5687 ( .A0(d_ff_Xn[1]), .A1(n4424), .B0(d_ff2_X[1]), .B1(n4500),
.Y(n2671) );
AO22XLTS U5688 ( .A0(n4498), .A1(d_ff2_X[1]), .B0(n4426), .B1(
d_ff3_sh_x_out[1]), .Y(n2670) );
OA22X1TS U5689 ( .A0(n4425), .A1(d_ff2_X[0]), .B0(d_ff_Xn[0]), .B1(n4502),
.Y(n2669) );
AO22XLTS U5690 ( .A0(n4521), .A1(d_ff2_X[0]), .B0(n4426), .B1(
d_ff3_sh_x_out[0]), .Y(n2668) );
INVX2TS U5691 ( .A(n4427), .Y(n4428) );
NOR2X1TS U5692 ( .A(n4812), .B(n4428), .Y(n4431) );
NAND2X1TS U5693 ( .A(sel_mux_3_reg), .B(n5159), .Y(n4430) );
OAI2BB2XLTS U5694 ( .B0(n4431), .B1(n4430), .A0N(n4431), .A1N(n4429), .Y(
n2667) );
INVX2TS U5695 ( .A(n4432), .Y(n4434) );
OAI22X1TS U5696 ( .A0(n2954), .A1(n4845), .B0(n4458), .B1(n5072), .Y(n2666)
);
CLKBUFX2TS U5697 ( .A(n3000), .Y(n4474) );
AO22XLTS U5698 ( .A0(n4465), .A1(result_add_subt[63]), .B0(n4474), .B1(
d_ff_Zn[63]), .Y(n2665) );
AOI22X1TS U5699 ( .A0(n4437), .A1(add_subt_module_add_overflow_flag), .B0(
n4894), .B1(n4436), .Y(n2664) );
NAND2X1TS U5700 ( .A(n4438), .B(n4988), .Y(n4446) );
OAI31X1TS U5701 ( .A0(add_subt_module_Add_Subt_result[38]), .A1(n4838), .A2(
n4441), .B0(n4440), .Y(n4442) );
AOI31XLTS U5702 ( .A0(n4443), .A1(add_subt_module_Add_Subt_result[45]), .A2(
n4972), .B0(n4442), .Y(n4445) );
OAI211XLTS U5703 ( .A0(n4986), .A1(n4446), .B0(n4445), .C0(n4444), .Y(n4447)
);
AOI211XLTS U5704 ( .A0(add_subt_module_Add_Subt_result[17]), .A1(n4449),
.B0(n4448), .C0(n4447), .Y(n4450) );
OA22X1TS U5705 ( .A0(n4455), .A1(add_subt_module_LZA_output[0]), .B0(n4454),
.B1(n4453), .Y(n2592) );
NAND3BXLTS U5706 ( .AN(overflow_flag), .B(n4462), .C(n4998), .Y(n4456) );
BUFX3TS U5707 ( .A(n4479), .Y(n4466) );
OA22X1TS U5708 ( .A0(n4462), .A1(result_add_subt[62]), .B0(
add_subt_module_exp_oper_result[10]), .B1(n4466), .Y(n2534) );
BUFX4TS U5709 ( .A(n3000), .Y(n4478) );
AO22XLTS U5710 ( .A0(n2957), .A1(result_add_subt[62]), .B0(n4478), .B1(
d_ff_Zn[62]), .Y(n2533) );
AO22XLTS U5711 ( .A0(n2954), .A1(d_ff_Yn[62]), .B0(n4458), .B1(
result_add_subt[62]), .Y(n2532) );
BUFX3TS U5712 ( .A(n4457), .Y(n4471) );
AO22XLTS U5713 ( .A0(n4459), .A1(result_add_subt[62]), .B0(n4477), .B1(
d_ff_Xn[62]), .Y(n2531) );
OA22X1TS U5714 ( .A0(n4462), .A1(result_add_subt[61]), .B0(
add_subt_module_exp_oper_result[9]), .B1(n4466), .Y(n2530) );
BUFX3TS U5715 ( .A(n3000), .Y(n4475) );
AO22XLTS U5716 ( .A0(n4472), .A1(result_add_subt[61]), .B0(n4475), .B1(
d_ff_Zn[61]), .Y(n2529) );
BUFX3TS U5717 ( .A(n4458), .Y(n4464) );
BUFX3TS U5718 ( .A(n4477), .Y(n4481) );
AO22XLTS U5719 ( .A0(n4459), .A1(result_add_subt[61]), .B0(n4481), .B1(
d_ff_Xn[61]), .Y(n2527) );
OA22X1TS U5720 ( .A0(n4462), .A1(result_add_subt[60]), .B0(
add_subt_module_exp_oper_result[8]), .B1(n4466), .Y(n2526) );
AO22XLTS U5721 ( .A0(n4465), .A1(result_add_subt[60]), .B0(n4475), .B1(
d_ff_Zn[60]), .Y(n2525) );
AO22XLTS U5722 ( .A0(n4459), .A1(result_add_subt[60]), .B0(n4481), .B1(
d_ff_Xn[60]), .Y(n2523) );
OA22X1TS U5723 ( .A0(n4462), .A1(result_add_subt[59]), .B0(
add_subt_module_exp_oper_result[7]), .B1(n4466), .Y(n2522) );
AO22XLTS U5724 ( .A0(n2957), .A1(result_add_subt[59]), .B0(n4475), .B1(
d_ff_Zn[59]), .Y(n2521) );
OA22X1TS U5725 ( .A0(n4462), .A1(result_add_subt[58]), .B0(
add_subt_module_exp_oper_result[6]), .B1(n4466), .Y(n2518) );
AO22XLTS U5726 ( .A0(n4472), .A1(result_add_subt[58]), .B0(n4475), .B1(
d_ff_Zn[58]), .Y(n2517) );
AO22XLTS U5727 ( .A0(n4463), .A1(result_add_subt[58]), .B0(n4481), .B1(
d_ff_Xn[58]), .Y(n2515) );
OA22X1TS U5728 ( .A0(n4462), .A1(result_add_subt[57]), .B0(
add_subt_module_exp_oper_result[5]), .B1(n4466), .Y(n2514) );
AO22XLTS U5729 ( .A0(n4465), .A1(result_add_subt[57]), .B0(n4475), .B1(
d_ff_Zn[57]), .Y(n2513) );
OA22X1TS U5730 ( .A0(n4462), .A1(result_add_subt[56]), .B0(
add_subt_module_exp_oper_result[4]), .B1(n4466), .Y(n2510) );
AO22XLTS U5731 ( .A0(n4465), .A1(result_add_subt[56]), .B0(n4475), .B1(
d_ff_Zn[56]), .Y(n2509) );
AO22XLTS U5732 ( .A0(n4463), .A1(result_add_subt[56]), .B0(n4481), .B1(
d_ff_Xn[56]), .Y(n2507) );
OA22X1TS U5733 ( .A0(n4462), .A1(result_add_subt[55]), .B0(
add_subt_module_exp_oper_result[3]), .B1(n4466), .Y(n2506) );
AO22XLTS U5734 ( .A0(n2957), .A1(result_add_subt[55]), .B0(n4475), .B1(
d_ff_Zn[55]), .Y(n2505) );
AO22XLTS U5735 ( .A0(n4463), .A1(result_add_subt[55]), .B0(n4481), .B1(
d_ff_Xn[55]), .Y(n2503) );
OA22X1TS U5736 ( .A0(n4462), .A1(result_add_subt[54]), .B0(
add_subt_module_exp_oper_result[2]), .B1(n4466), .Y(n2502) );
AO22XLTS U5737 ( .A0(n4472), .A1(result_add_subt[54]), .B0(n4475), .B1(
d_ff_Zn[54]), .Y(n2501) );
AO22XLTS U5738 ( .A0(n4463), .A1(result_add_subt[54]), .B0(n4481), .B1(
d_ff_Xn[54]), .Y(n2499) );
OA22X1TS U5739 ( .A0(n4462), .A1(result_add_subt[53]), .B0(
add_subt_module_exp_oper_result[1]), .B1(n4466), .Y(n2498) );
AO22XLTS U5740 ( .A0(n4465), .A1(result_add_subt[53]), .B0(n4475), .B1(
d_ff_Zn[53]), .Y(n2497) );
AO22XLTS U5741 ( .A0(n4463), .A1(result_add_subt[53]), .B0(n4481), .B1(
d_ff_Xn[53]), .Y(n2495) );
OA22X1TS U5742 ( .A0(n4462), .A1(result_add_subt[52]), .B0(
add_subt_module_exp_oper_result[0]), .B1(n4466), .Y(n2494) );
AO22XLTS U5743 ( .A0(n4465), .A1(result_add_subt[52]), .B0(n4475), .B1(
d_ff_Zn[52]), .Y(n2493) );
AO22XLTS U5744 ( .A0(n4463), .A1(result_add_subt[52]), .B0(n4481), .B1(
d_ff_Xn[52]), .Y(n2491) );
BUFX4TS U5745 ( .A(n4479), .Y(n4467) );
OAI2BB2XLTS U5746 ( .B0(n5001), .B1(n4467), .A0N(result_add_subt[51]), .A1N(
n4470), .Y(n2490) );
INVX2TS U5747 ( .A(n4474), .Y(n4472) );
AO22XLTS U5748 ( .A0(n2957), .A1(result_add_subt[51]), .B0(n4475), .B1(
d_ff_Zn[51]), .Y(n2489) );
AO22XLTS U5749 ( .A0(n4463), .A1(result_add_subt[51]), .B0(n4481), .B1(
d_ff_Xn[51]), .Y(n2487) );
OAI2BB2XLTS U5750 ( .B0(n4991), .B1(n4467), .A0N(result_add_subt[50]), .A1N(
n4470), .Y(n2486) );
BUFX3TS U5751 ( .A(n3000), .Y(n4480) );
AO22XLTS U5752 ( .A0(n2957), .A1(result_add_subt[50]), .B0(n4480), .B1(
d_ff_Zn[50]), .Y(n2485) );
AO22XLTS U5753 ( .A0(n4459), .A1(result_add_subt[50]), .B0(n2956), .B1(
d_ff_Xn[50]), .Y(n2483) );
OAI2BB2XLTS U5754 ( .B0(n4992), .B1(n4467), .A0N(result_add_subt[49]), .A1N(
n4470), .Y(n2482) );
AO22XLTS U5755 ( .A0(n2957), .A1(result_add_subt[49]), .B0(n3000), .B1(
d_ff_Zn[49]), .Y(n2481) );
AO22XLTS U5756 ( .A0(n4463), .A1(result_add_subt[49]), .B0(n2956), .B1(
d_ff_Xn[49]), .Y(n2479) );
OAI2BB2XLTS U5757 ( .B0(n4977), .B1(n4467), .A0N(result_add_subt[48]), .A1N(
n4470), .Y(n2478) );
AO22XLTS U5758 ( .A0(n4465), .A1(result_add_subt[48]), .B0(n3000), .B1(
d_ff_Zn[48]), .Y(n2477) );
AO22XLTS U5759 ( .A0(n4459), .A1(result_add_subt[48]), .B0(n2956), .B1(
d_ff_Xn[48]), .Y(n2475) );
OAI2BB2XLTS U5760 ( .B0(n4966), .B1(n4467), .A0N(result_add_subt[47]), .A1N(
n4470), .Y(n2474) );
AO22XLTS U5761 ( .A0(n4472), .A1(result_add_subt[47]), .B0(n4478), .B1(
d_ff_Zn[47]), .Y(n2473) );
AO22XLTS U5762 ( .A0(n4459), .A1(result_add_subt[47]), .B0(n2956), .B1(
d_ff_Xn[47]), .Y(n2471) );
OAI2BB2XLTS U5763 ( .B0(n4967), .B1(n4467), .A0N(result_add_subt[46]), .A1N(
n4470), .Y(n2470) );
AO22XLTS U5764 ( .A0(n4472), .A1(result_add_subt[46]), .B0(n4475), .B1(
d_ff_Zn[46]), .Y(n2469) );
BUFX4TS U5765 ( .A(n4458), .Y(n4485) );
AO22XLTS U5766 ( .A0(n4459), .A1(result_add_subt[46]), .B0(n2956), .B1(
d_ff_Xn[46]), .Y(n2467) );
OAI2BB2XLTS U5767 ( .B0(n4956), .B1(n4467), .A0N(result_add_subt[45]), .A1N(
n4470), .Y(n2466) );
INVX4TS U5768 ( .A(n3000), .Y(n4461) );
AO22XLTS U5769 ( .A0(n4461), .A1(result_add_subt[45]), .B0(n4478), .B1(
d_ff_Zn[45]), .Y(n2465) );
AO22XLTS U5770 ( .A0(n4459), .A1(result_add_subt[45]), .B0(n2956), .B1(
d_ff_Xn[45]), .Y(n2463) );
OAI2BB2XLTS U5771 ( .B0(n4957), .B1(n4467), .A0N(result_add_subt[44]), .A1N(
n4470), .Y(n2462) );
AO22XLTS U5772 ( .A0(n4461), .A1(result_add_subt[44]), .B0(n4478), .B1(
d_ff_Zn[44]), .Y(n2461) );
AO22XLTS U5773 ( .A0(n4459), .A1(result_add_subt[44]), .B0(n2956), .B1(
d_ff_Xn[44]), .Y(n2459) );
OAI2BB2XLTS U5774 ( .B0(n4941), .B1(n4467), .A0N(result_add_subt[43]), .A1N(
n4470), .Y(n2458) );
AO22XLTS U5775 ( .A0(n4461), .A1(result_add_subt[43]), .B0(n4478), .B1(
d_ff_Zn[43]), .Y(n2457) );
AO22XLTS U5776 ( .A0(n4459), .A1(result_add_subt[43]), .B0(n2956), .B1(
d_ff_Xn[43]), .Y(n2455) );
OAI2BB2XLTS U5777 ( .B0(n4942), .B1(n4467), .A0N(result_add_subt[42]), .A1N(
n4470), .Y(n2454) );
AO22XLTS U5778 ( .A0(n4461), .A1(result_add_subt[42]), .B0(n4478), .B1(
d_ff_Zn[42]), .Y(n2453) );
AO22XLTS U5779 ( .A0(n4459), .A1(result_add_subt[42]), .B0(n2956), .B1(
d_ff_Xn[42]), .Y(n2451) );
OAI2BB2XLTS U5780 ( .B0(n4911), .B1(n4467), .A0N(result_add_subt[41]), .A1N(
n4470), .Y(n2450) );
AO22XLTS U5781 ( .A0(n4461), .A1(result_add_subt[41]), .B0(n4478), .B1(
d_ff_Zn[41]), .Y(n2449) );
AO22XLTS U5782 ( .A0(n4459), .A1(result_add_subt[41]), .B0(n2956), .B1(
d_ff_Xn[41]), .Y(n2447) );
OAI2BB2XLTS U5783 ( .B0(n4912), .B1(n4467), .A0N(result_add_subt[40]), .A1N(
n4470), .Y(n2446) );
AO22XLTS U5784 ( .A0(n4461), .A1(result_add_subt[40]), .B0(n4478), .B1(
d_ff_Zn[40]), .Y(n2445) );
AO22XLTS U5785 ( .A0(n4459), .A1(result_add_subt[40]), .B0(n2956), .B1(
d_ff_Xn[40]), .Y(n2443) );
OAI2BB2XLTS U5786 ( .B0(n4904), .B1(n4467), .A0N(result_add_subt[39]), .A1N(
n4469), .Y(n2442) );
AO22XLTS U5787 ( .A0(n4461), .A1(result_add_subt[39]), .B0(n4480), .B1(
d_ff_Zn[39]), .Y(n2441) );
INVX4TS U5788 ( .A(n4458), .Y(n4486) );
INVX4TS U5789 ( .A(n4471), .Y(n4531) );
AO22XLTS U5790 ( .A0(n4531), .A1(result_add_subt[39]), .B0(n4477), .B1(
d_ff_Xn[39]), .Y(n2439) );
BUFX4TS U5791 ( .A(n4479), .Y(n4483) );
OAI2BB2XLTS U5792 ( .B0(n4895), .B1(n4483), .A0N(result_add_subt[38]), .A1N(
n4470), .Y(n2438) );
AO22XLTS U5793 ( .A0(n4461), .A1(result_add_subt[38]), .B0(n4480), .B1(
d_ff_Zn[38]), .Y(n2437) );
INVX4TS U5794 ( .A(n4471), .Y(n4473) );
AO22XLTS U5795 ( .A0(n4473), .A1(result_add_subt[38]), .B0(n4477), .B1(
d_ff_Xn[38]), .Y(n2435) );
OAI2BB2XLTS U5796 ( .B0(n4896), .B1(n4483), .A0N(result_add_subt[37]), .A1N(
n4469), .Y(n2434) );
AO22XLTS U5797 ( .A0(n4461), .A1(result_add_subt[37]), .B0(n4480), .B1(
d_ff_Zn[37]), .Y(n2433) );
AO22XLTS U5798 ( .A0(n4531), .A1(result_add_subt[37]), .B0(n4477), .B1(
d_ff_Xn[37]), .Y(n2431) );
OAI2BB2XLTS U5799 ( .B0(n4888), .B1(n4483), .A0N(result_add_subt[36]), .A1N(
n4469), .Y(n2430) );
AO22XLTS U5800 ( .A0(n4461), .A1(result_add_subt[36]), .B0(n4480), .B1(
d_ff_Zn[36]), .Y(n2429) );
AO22XLTS U5801 ( .A0(n4473), .A1(result_add_subt[36]), .B0(n4477), .B1(
d_ff_Xn[36]), .Y(n2427) );
OAI2BB2XLTS U5802 ( .B0(n4889), .B1(n4483), .A0N(result_add_subt[35]), .A1N(
n4470), .Y(n2426) );
AO22XLTS U5803 ( .A0(n4461), .A1(result_add_subt[35]), .B0(n4480), .B1(
d_ff_Zn[35]), .Y(n2425) );
AO22XLTS U5804 ( .A0(n4531), .A1(result_add_subt[35]), .B0(n4477), .B1(
d_ff_Xn[35]), .Y(n2423) );
OAI2BB2XLTS U5805 ( .B0(n4885), .B1(n4483), .A0N(result_add_subt[34]), .A1N(
n4469), .Y(n2422) );
AO22XLTS U5806 ( .A0(n4461), .A1(result_add_subt[34]), .B0(n4480), .B1(
d_ff_Zn[34]), .Y(n2421) );
AO22XLTS U5807 ( .A0(n4531), .A1(result_add_subt[34]), .B0(n4477), .B1(
d_ff_Xn[34]), .Y(n2419) );
OAI2BB2XLTS U5808 ( .B0(n4886), .B1(n4483), .A0N(result_add_subt[33]), .A1N(
n4470), .Y(n2418) );
AO22XLTS U5809 ( .A0(n4461), .A1(result_add_subt[33]), .B0(n4480), .B1(
d_ff_Zn[33]), .Y(n2417) );
AO22XLTS U5810 ( .A0(n4531), .A1(result_add_subt[33]), .B0(n4477), .B1(
d_ff_Xn[33]), .Y(n2415) );
OAI2BB2XLTS U5811 ( .B0(n4882), .B1(n4483), .A0N(result_add_subt[32]), .A1N(
n4469), .Y(n2414) );
AO22XLTS U5812 ( .A0(n4461), .A1(result_add_subt[32]), .B0(n4480), .B1(
d_ff_Zn[32]), .Y(n2413) );
AO22XLTS U5813 ( .A0(n4531), .A1(result_add_subt[32]), .B0(n4477), .B1(
d_ff_Xn[32]), .Y(n2411) );
OAI2BB2XLTS U5814 ( .B0(n4883), .B1(n4483), .A0N(result_add_subt[31]), .A1N(
n4469), .Y(n2410) );
AO22XLTS U5815 ( .A0(n4461), .A1(result_add_subt[31]), .B0(n4480), .B1(
d_ff_Zn[31]), .Y(n2409) );
AO22XLTS U5816 ( .A0(n4531), .A1(result_add_subt[31]), .B0(n4477), .B1(
d_ff_Xn[31]), .Y(n2407) );
OAI2BB2XLTS U5817 ( .B0(n4881), .B1(n4483), .A0N(result_add_subt[30]), .A1N(
n4469), .Y(n2406) );
AO22XLTS U5818 ( .A0(n4461), .A1(result_add_subt[30]), .B0(n4480), .B1(
d_ff_Zn[30]), .Y(n2405) );
AO22XLTS U5819 ( .A0(n4531), .A1(result_add_subt[30]), .B0(n4477), .B1(
d_ff_Xn[30]), .Y(n2403) );
OAI2BB2XLTS U5820 ( .B0(n4878), .B1(n4483), .A0N(result_add_subt[29]), .A1N(
n4469), .Y(n2402) );
AO22XLTS U5821 ( .A0(n4461), .A1(result_add_subt[29]), .B0(n4480), .B1(
d_ff_Zn[29]), .Y(n2401) );
AO22XLTS U5822 ( .A0(n4531), .A1(result_add_subt[29]), .B0(n4477), .B1(
d_ff_Xn[29]), .Y(n2399) );
OAI2BB2XLTS U5823 ( .B0(n4879), .B1(n4483), .A0N(result_add_subt[28]), .A1N(
n4469), .Y(n2398) );
AO22XLTS U5824 ( .A0(n4461), .A1(result_add_subt[28]), .B0(n3000), .B1(
d_ff_Zn[28]), .Y(n2397) );
AO22XLTS U5825 ( .A0(n4531), .A1(result_add_subt[28]), .B0(n2956), .B1(
d_ff_Xn[28]), .Y(n2395) );
OAI2BB2XLTS U5826 ( .B0(n4875), .B1(n4483), .A0N(result_add_subt[27]), .A1N(
n4469), .Y(n2394) );
AO22XLTS U5827 ( .A0(n4465), .A1(result_add_subt[27]), .B0(n3000), .B1(
d_ff_Zn[27]), .Y(n2393) );
AO22XLTS U5828 ( .A0(n4463), .A1(result_add_subt[27]), .B0(n2956), .B1(
d_ff_Xn[27]), .Y(n2391) );
OAI2BB2XLTS U5829 ( .B0(n4876), .B1(n4483), .A0N(result_add_subt[26]), .A1N(
n4469), .Y(n2390) );
AO22XLTS U5830 ( .A0(n2957), .A1(result_add_subt[26]), .B0(n3000), .B1(
d_ff_Zn[26]), .Y(n2389) );
AO22XLTS U5831 ( .A0(n4463), .A1(result_add_subt[26]), .B0(n2956), .B1(
d_ff_Xn[26]), .Y(n2387) );
OAI22X1TS U5832 ( .A0(n4462), .A1(n4846), .B0(n4877), .B1(n4479), .Y(n2386)
);
AO22XLTS U5833 ( .A0(n4472), .A1(result_add_subt[25]), .B0(n3000), .B1(
d_ff_Zn[25]), .Y(n2385) );
OAI22X1TS U5834 ( .A0(n2954), .A1(n4846), .B0(n4458), .B1(n5071), .Y(n2384)
);
OAI2BB2XLTS U5835 ( .B0(n4874), .B1(n4483), .A0N(result_add_subt[24]), .A1N(
n4469), .Y(n2382) );
AO22XLTS U5836 ( .A0(n4465), .A1(result_add_subt[24]), .B0(n3000), .B1(
d_ff_Zn[24]), .Y(n2381) );
BUFX3TS U5837 ( .A(n4458), .Y(n4476) );
AO22XLTS U5838 ( .A0(n4463), .A1(result_add_subt[24]), .B0(n2956), .B1(
d_ff_Xn[24]), .Y(n2379) );
OAI2BB2XLTS U5839 ( .B0(n4872), .B1(n4467), .A0N(result_add_subt[23]), .A1N(
n4469), .Y(n2378) );
AO22XLTS U5840 ( .A0(n4465), .A1(result_add_subt[23]), .B0(n3000), .B1(
d_ff_Zn[23]), .Y(n2377) );
AO22XLTS U5841 ( .A0(n4531), .A1(result_add_subt[23]), .B0(n2956), .B1(
d_ff_Xn[23]), .Y(n2375) );
OAI2BB2XLTS U5842 ( .B0(n4873), .B1(n4483), .A0N(result_add_subt[22]), .A1N(
n4469), .Y(n2374) );
AO22XLTS U5843 ( .A0(n2957), .A1(result_add_subt[22]), .B0(n3000), .B1(
d_ff_Zn[22]), .Y(n2373) );
AO22XLTS U5844 ( .A0(n4473), .A1(result_add_subt[22]), .B0(n2956), .B1(
d_ff_Xn[22]), .Y(n2371) );
OAI2BB2XLTS U5845 ( .B0(n4871), .B1(n4467), .A0N(result_add_subt[21]), .A1N(
n4469), .Y(n2370) );
AO22XLTS U5846 ( .A0(n4472), .A1(result_add_subt[21]), .B0(n3000), .B1(
d_ff_Zn[21]), .Y(n2369) );
AO22XLTS U5847 ( .A0(n4531), .A1(result_add_subt[21]), .B0(n2956), .B1(
d_ff_Xn[21]), .Y(n2367) );
OAI2BB2XLTS U5848 ( .B0(n4868), .B1(n4483), .A0N(result_add_subt[20]), .A1N(
n4469), .Y(n2366) );
AO22XLTS U5849 ( .A0(n4465), .A1(result_add_subt[20]), .B0(n3000), .B1(
d_ff_Zn[20]), .Y(n2365) );
AO22XLTS U5850 ( .A0(n4473), .A1(result_add_subt[20]), .B0(n2956), .B1(
d_ff_Xn[20]), .Y(n2363) );
OAI2BB2XLTS U5851 ( .B0(n4869), .B1(n4467), .A0N(result_add_subt[19]), .A1N(
n4469), .Y(n2362) );
AO22XLTS U5852 ( .A0(n4465), .A1(result_add_subt[19]), .B0(n3000), .B1(
d_ff_Zn[19]), .Y(n2361) );
AO22XLTS U5853 ( .A0(n4531), .A1(result_add_subt[19]), .B0(n2956), .B1(
d_ff_Xn[19]), .Y(n2359) );
OAI2BB2XLTS U5854 ( .B0(n4866), .B1(n4483), .A0N(result_add_subt[18]), .A1N(
n4469), .Y(n2358) );
AO22XLTS U5855 ( .A0(n2957), .A1(result_add_subt[18]), .B0(n3000), .B1(
d_ff_Zn[18]), .Y(n2357) );
AO22XLTS U5856 ( .A0(n4473), .A1(result_add_subt[18]), .B0(n2956), .B1(
d_ff_Xn[18]), .Y(n2355) );
OAI2BB2XLTS U5857 ( .B0(n4867), .B1(n4467), .A0N(result_add_subt[17]), .A1N(
n4469), .Y(n2354) );
AO22XLTS U5858 ( .A0(n4472), .A1(result_add_subt[17]), .B0(n4478), .B1(
d_ff_Zn[17]), .Y(n2353) );
AO22XLTS U5859 ( .A0(n4531), .A1(result_add_subt[17]), .B0(n4471), .B1(
d_ff_Xn[17]), .Y(n2351) );
OAI2BB2XLTS U5860 ( .B0(n4864), .B1(n4483), .A0N(result_add_subt[16]), .A1N(
n4469), .Y(n2350) );
AO22XLTS U5861 ( .A0(n4465), .A1(result_add_subt[16]), .B0(n4478), .B1(
d_ff_Zn[16]), .Y(n2349) );
AO22XLTS U5862 ( .A0(n4473), .A1(result_add_subt[16]), .B0(n4471), .B1(
d_ff_Xn[16]), .Y(n2347) );
OAI2BB2XLTS U5863 ( .B0(n4865), .B1(n4467), .A0N(result_add_subt[15]), .A1N(
n4469), .Y(n2346) );
AO22XLTS U5864 ( .A0(n2957), .A1(result_add_subt[15]), .B0(n4478), .B1(
d_ff_Zn[15]), .Y(n2345) );
AO22XLTS U5865 ( .A0(n4473), .A1(result_add_subt[15]), .B0(n4471), .B1(
d_ff_Xn[15]), .Y(n2343) );
OAI2BB2XLTS U5866 ( .B0(n4862), .B1(n4466), .A0N(result_add_subt[14]), .A1N(
n4469), .Y(n2342) );
AO22XLTS U5867 ( .A0(n2957), .A1(result_add_subt[14]), .B0(n4478), .B1(
d_ff_Zn[14]), .Y(n2341) );
AO22XLTS U5868 ( .A0(n4473), .A1(result_add_subt[14]), .B0(n4471), .B1(
d_ff_Xn[14]), .Y(n2339) );
OAI2BB2XLTS U5869 ( .B0(n4863), .B1(n4467), .A0N(result_add_subt[13]), .A1N(
n4469), .Y(n2338) );
AO22XLTS U5870 ( .A0(n2957), .A1(result_add_subt[13]), .B0(n4478), .B1(
d_ff_Zn[13]), .Y(n2337) );
AO22XLTS U5871 ( .A0(n4473), .A1(result_add_subt[13]), .B0(n4471), .B1(
d_ff_Xn[13]), .Y(n2335) );
OAI2BB2XLTS U5872 ( .B0(n4861), .B1(n4479), .A0N(result_add_subt[12]), .A1N(
n4469), .Y(n2334) );
AO22XLTS U5873 ( .A0(n2957), .A1(result_add_subt[12]), .B0(n4478), .B1(
d_ff_Zn[12]), .Y(n2333) );
AO22XLTS U5874 ( .A0(n4473), .A1(result_add_subt[12]), .B0(n4471), .B1(
d_ff_Xn[12]), .Y(n2331) );
OAI2BB2XLTS U5875 ( .B0(n4859), .B1(n4479), .A0N(result_add_subt[11]), .A1N(
n4469), .Y(n2330) );
AO22XLTS U5876 ( .A0(n2957), .A1(result_add_subt[11]), .B0(n4478), .B1(
d_ff_Zn[11]), .Y(n2329) );
AO22XLTS U5877 ( .A0(n4473), .A1(result_add_subt[11]), .B0(n4471), .B1(
d_ff_Xn[11]), .Y(n2327) );
OAI2BB2XLTS U5878 ( .B0(n4860), .B1(n4479), .A0N(result_add_subt[10]), .A1N(
n4470), .Y(n2326) );
AO22XLTS U5879 ( .A0(n2957), .A1(result_add_subt[10]), .B0(n4478), .B1(
d_ff_Zn[10]), .Y(n2325) );
AO22XLTS U5880 ( .A0(n4473), .A1(result_add_subt[10]), .B0(n4471), .B1(
d_ff_Xn[10]), .Y(n2323) );
OAI2BB2XLTS U5881 ( .B0(n4857), .B1(n4479), .A0N(result_add_subt[9]), .A1N(
n4470), .Y(n2322) );
AO22XLTS U5882 ( .A0(n2957), .A1(result_add_subt[9]), .B0(n4478), .B1(
d_ff_Zn[9]), .Y(n2321) );
AO22XLTS U5883 ( .A0(n4473), .A1(result_add_subt[9]), .B0(n4471), .B1(
d_ff_Xn[9]), .Y(n2319) );
OAI2BB2XLTS U5884 ( .B0(n4858), .B1(n4479), .A0N(result_add_subt[8]), .A1N(
n4470), .Y(n2318) );
AO22XLTS U5885 ( .A0(n2957), .A1(result_add_subt[8]), .B0(n4478), .B1(
d_ff_Zn[8]), .Y(n2317) );
AO22XLTS U5886 ( .A0(n4473), .A1(result_add_subt[8]), .B0(n4471), .B1(
d_ff_Xn[8]), .Y(n2315) );
OAI2BB2XLTS U5887 ( .B0(n4854), .B1(n4479), .A0N(result_add_subt[7]), .A1N(
n4470), .Y(n2314) );
AO22XLTS U5888 ( .A0(n2957), .A1(result_add_subt[7]), .B0(n4478), .B1(
d_ff_Zn[7]), .Y(n2313) );
AO22XLTS U5889 ( .A0(n4473), .A1(result_add_subt[7]), .B0(n4471), .B1(
d_ff_Xn[7]), .Y(n2311) );
OAI2BB2XLTS U5890 ( .B0(n4855), .B1(n4479), .A0N(result_add_subt[6]), .A1N(
n4482), .Y(n2310) );
AO22XLTS U5891 ( .A0(n4472), .A1(result_add_subt[6]), .B0(n4480), .B1(
d_ff_Zn[6]), .Y(n2309) );
AO22XLTS U5892 ( .A0(n4473), .A1(result_add_subt[6]), .B0(n4477), .B1(
d_ff_Xn[6]), .Y(n2307) );
OAI2BB2XLTS U5893 ( .B0(n4852), .B1(n4479), .A0N(result_add_subt[5]), .A1N(
n4482), .Y(n2306) );
AO22XLTS U5894 ( .A0(n4465), .A1(result_add_subt[5]), .B0(n3000), .B1(
d_ff_Zn[5]), .Y(n2305) );
AO22XLTS U5895 ( .A0(n4473), .A1(result_add_subt[5]), .B0(n4477), .B1(
d_ff_Xn[5]), .Y(n2303) );
OAI2BB2XLTS U5896 ( .B0(n4853), .B1(n4479), .A0N(result_add_subt[4]), .A1N(
n4482), .Y(n2302) );
AO22XLTS U5897 ( .A0(n4465), .A1(result_add_subt[4]), .B0(n4475), .B1(
d_ff_Zn[4]), .Y(n2301) );
AO22XLTS U5898 ( .A0(n4473), .A1(result_add_subt[4]), .B0(n4477), .B1(
d_ff_Xn[4]), .Y(n2299) );
OAI2BB2XLTS U5899 ( .B0(n4851), .B1(n4479), .A0N(result_add_subt[3]), .A1N(
n4482), .Y(n2298) );
AO22XLTS U5900 ( .A0(n2957), .A1(result_add_subt[3]), .B0(n4475), .B1(
d_ff_Zn[3]), .Y(n2297) );
AO22XLTS U5901 ( .A0(n4531), .A1(result_add_subt[3]), .B0(n4477), .B1(
d_ff_Xn[3]), .Y(n2295) );
OAI2BB2XLTS U5902 ( .B0(n4848), .B1(n4479), .A0N(result_add_subt[2]), .A1N(
n4482), .Y(n2294) );
AO22XLTS U5903 ( .A0(n4472), .A1(result_add_subt[2]), .B0(n4478), .B1(
d_ff_Zn[2]), .Y(n2293) );
AO22XLTS U5904 ( .A0(n4531), .A1(result_add_subt[2]), .B0(n2956), .B1(
d_ff_Xn[2]), .Y(n2291) );
OAI2BB2XLTS U5905 ( .B0(n4849), .B1(n4479), .A0N(result_add_subt[1]), .A1N(
n4482), .Y(n2290) );
AO22XLTS U5906 ( .A0(n4465), .A1(result_add_subt[1]), .B0(n4480), .B1(
d_ff_Zn[1]), .Y(n2289) );
AO22XLTS U5907 ( .A0(n4531), .A1(result_add_subt[1]), .B0(n4481), .B1(
d_ff_Xn[1]), .Y(n2287) );
OAI2BB2XLTS U5908 ( .B0(n4847), .B1(n4483), .A0N(result_add_subt[0]), .A1N(
n4482), .Y(n2286) );
AO22XLTS U5909 ( .A0(n4465), .A1(result_add_subt[0]), .B0(n3000), .B1(
d_ff_Zn[0]), .Y(n2285) );
AO22XLTS U5910 ( .A0(n4493), .A1(d_ff2_Z[63]), .B0(n4489), .B1(
d_ff3_sign_out), .Y(n2220) );
AO22XLTS U5911 ( .A0(d_ff_Yn[0]), .A1(n4492), .B0(d_ff2_Y[0]), .B1(n4501),
.Y(n2218) );
AO22XLTS U5912 ( .A0(n4498), .A1(d_ff2_Y[0]), .B0(n4489), .B1(
d_ff3_sh_y_out[0]), .Y(n2217) );
AO22XLTS U5913 ( .A0(n4498), .A1(d_ff2_Y[1]), .B0(n4489), .B1(
d_ff3_sh_y_out[1]), .Y(n2215) );
AO22XLTS U5914 ( .A0(n4521), .A1(d_ff2_Y[2]), .B0(n4489), .B1(
d_ff3_sh_y_out[2]), .Y(n2213) );
AO22XLTS U5915 ( .A0(n4521), .A1(d_ff2_Y[3]), .B0(n4489), .B1(
d_ff3_sh_y_out[3]), .Y(n2211) );
AO22XLTS U5916 ( .A0(n4493), .A1(d_ff2_Y[4]), .B0(n4489), .B1(
d_ff3_sh_y_out[4]), .Y(n2209) );
AO22XLTS U5917 ( .A0(n4488), .A1(d_ff2_Y[5]), .B0(n4489), .B1(
d_ff3_sh_y_out[5]), .Y(n2207) );
AO22XLTS U5918 ( .A0(d_ff_Yn[6]), .A1(n4487), .B0(d_ff2_Y[6]), .B1(n4501),
.Y(n2206) );
AO22XLTS U5919 ( .A0(n4530), .A1(d_ff2_Y[6]), .B0(n4489), .B1(
d_ff3_sh_y_out[6]), .Y(n2205) );
AO22XLTS U5920 ( .A0(d_ff_Yn[7]), .A1(n4487), .B0(d_ff2_Y[7]), .B1(n4501),
.Y(n2204) );
AO22XLTS U5921 ( .A0(n4494), .A1(d_ff2_Y[7]), .B0(n4489), .B1(
d_ff3_sh_y_out[7]), .Y(n2203) );
AO22XLTS U5922 ( .A0(d_ff_Yn[8]), .A1(n4487), .B0(d_ff2_Y[8]), .B1(n4501),
.Y(n2202) );
AO22XLTS U5923 ( .A0(n4496), .A1(d_ff2_Y[8]), .B0(n4489), .B1(
d_ff3_sh_y_out[8]), .Y(n2201) );
AO22XLTS U5924 ( .A0(d_ff_Yn[9]), .A1(n4487), .B0(d_ff2_Y[9]), .B1(n4527),
.Y(n2200) );
AO22XLTS U5925 ( .A0(n4488), .A1(d_ff2_Y[9]), .B0(n4489), .B1(
d_ff3_sh_y_out[9]), .Y(n2199) );
AO22XLTS U5926 ( .A0(d_ff_Yn[10]), .A1(n4487), .B0(d_ff2_Y[10]), .B1(n4527),
.Y(n2198) );
AO22XLTS U5927 ( .A0(n4530), .A1(d_ff2_Y[10]), .B0(n4490), .B1(
d_ff3_sh_y_out[10]), .Y(n2197) );
AO22XLTS U5928 ( .A0(d_ff_Yn[11]), .A1(n4487), .B0(d_ff2_Y[11]), .B1(n4527),
.Y(n2196) );
AO22XLTS U5929 ( .A0(n4494), .A1(d_ff2_Y[11]), .B0(n4490), .B1(
d_ff3_sh_y_out[11]), .Y(n2195) );
AO22XLTS U5930 ( .A0(d_ff_Yn[12]), .A1(n4487), .B0(d_ff2_Y[12]), .B1(n4527),
.Y(n2194) );
AO22XLTS U5931 ( .A0(n4498), .A1(d_ff2_Y[12]), .B0(n4490), .B1(
d_ff3_sh_y_out[12]), .Y(n2193) );
AO22XLTS U5932 ( .A0(d_ff_Yn[13]), .A1(n4528), .B0(d_ff2_Y[13]), .B1(n4527),
.Y(n2192) );
AO22XLTS U5933 ( .A0(n4521), .A1(d_ff2_Y[13]), .B0(n4490), .B1(
d_ff3_sh_y_out[13]), .Y(n2191) );
AO22XLTS U5934 ( .A0(d_ff_Yn[14]), .A1(n4528), .B0(d_ff2_Y[14]), .B1(n4527),
.Y(n2190) );
AO22XLTS U5935 ( .A0(n4493), .A1(d_ff2_Y[14]), .B0(n4490), .B1(
d_ff3_sh_y_out[14]), .Y(n2189) );
AO22XLTS U5936 ( .A0(d_ff_Yn[15]), .A1(n4528), .B0(d_ff2_Y[15]), .B1(n4527),
.Y(n2188) );
AO22XLTS U5937 ( .A0(n4498), .A1(d_ff2_Y[15]), .B0(n4490), .B1(
d_ff3_sh_y_out[15]), .Y(n2187) );
AO22XLTS U5938 ( .A0(d_ff_Yn[16]), .A1(n4497), .B0(d_ff2_Y[16]), .B1(n4527),
.Y(n2186) );
AO22XLTS U5939 ( .A0(n4521), .A1(d_ff2_Y[16]), .B0(n4490), .B1(
d_ff3_sh_y_out[16]), .Y(n2185) );
AO22XLTS U5940 ( .A0(d_ff_Yn[17]), .A1(n4528), .B0(d_ff2_Y[17]), .B1(n4527),
.Y(n2184) );
AO22XLTS U5941 ( .A0(n4493), .A1(d_ff2_Y[17]), .B0(n4490), .B1(
d_ff3_sh_y_out[17]), .Y(n2183) );
AO22XLTS U5942 ( .A0(d_ff_Yn[18]), .A1(n4497), .B0(d_ff2_Y[18]), .B1(n3305),
.Y(n2182) );
AO22XLTS U5943 ( .A0(n4498), .A1(d_ff2_Y[18]), .B0(n4490), .B1(
d_ff3_sh_y_out[18]), .Y(n2181) );
AO22XLTS U5944 ( .A0(d_ff_Yn[19]), .A1(n4497), .B0(d_ff2_Y[19]), .B1(n3305),
.Y(n2180) );
AO22XLTS U5945 ( .A0(n4521), .A1(d_ff2_Y[19]), .B0(n4490), .B1(
d_ff3_sh_y_out[19]), .Y(n2179) );
AO22XLTS U5946 ( .A0(d_ff_Yn[20]), .A1(n4528), .B0(d_ff2_Y[20]), .B1(n4491),
.Y(n2178) );
AO22XLTS U5947 ( .A0(n4494), .A1(d_ff2_Y[20]), .B0(n4490), .B1(
d_ff3_sh_y_out[20]), .Y(n2177) );
AO22XLTS U5948 ( .A0(d_ff_Yn[21]), .A1(n4492), .B0(d_ff2_Y[21]), .B1(n4501),
.Y(n2176) );
AO22XLTS U5949 ( .A0(n4530), .A1(d_ff2_Y[21]), .B0(n4489), .B1(
d_ff3_sh_y_out[21]), .Y(n2175) );
AO22XLTS U5950 ( .A0(d_ff_Yn[22]), .A1(n4497), .B0(d_ff2_Y[22]), .B1(n4501),
.Y(n2174) );
AO22XLTS U5951 ( .A0(n4496), .A1(d_ff2_Y[22]), .B0(n4499), .B1(
d_ff3_sh_y_out[22]), .Y(n2173) );
AO22XLTS U5952 ( .A0(d_ff_Yn[23]), .A1(n4497), .B0(d_ff2_Y[23]), .B1(n4527),
.Y(n2172) );
AO22XLTS U5953 ( .A0(n4488), .A1(d_ff2_Y[23]), .B0(n4490), .B1(
d_ff3_sh_y_out[23]), .Y(n2171) );
AO22XLTS U5954 ( .A0(d_ff_Yn[24]), .A1(n4497), .B0(d_ff2_Y[24]), .B1(n4404),
.Y(n2170) );
AO22XLTS U5955 ( .A0(n4488), .A1(d_ff2_Y[24]), .B0(n4518), .B1(
d_ff3_sh_y_out[24]), .Y(n2169) );
AO22XLTS U5956 ( .A0(d_ff_Yn[25]), .A1(n4492), .B0(d_ff2_Y[25]), .B1(n3305),
.Y(n2168) );
AO22XLTS U5957 ( .A0(n4498), .A1(d_ff2_Y[25]), .B0(n4518), .B1(
d_ff3_sh_y_out[25]), .Y(n2167) );
AO22XLTS U5958 ( .A0(d_ff_Yn[26]), .A1(n4497), .B0(d_ff2_Y[26]), .B1(n4501),
.Y(n2166) );
AO22XLTS U5959 ( .A0(n4521), .A1(d_ff2_Y[26]), .B0(n4518), .B1(
d_ff3_sh_y_out[26]), .Y(n2165) );
AO22XLTS U5960 ( .A0(d_ff_Yn[27]), .A1(n4528), .B0(d_ff2_Y[27]), .B1(n4491),
.Y(n2164) );
AO22XLTS U5961 ( .A0(n4498), .A1(d_ff2_Y[27]), .B0(n4518), .B1(
d_ff3_sh_y_out[27]), .Y(n2163) );
AO22XLTS U5962 ( .A0(d_ff_Yn[28]), .A1(n4497), .B0(d_ff2_Y[28]), .B1(n4527),
.Y(n2162) );
AO22XLTS U5963 ( .A0(n4521), .A1(d_ff2_Y[28]), .B0(n4518), .B1(
d_ff3_sh_y_out[28]), .Y(n2161) );
AO22XLTS U5964 ( .A0(d_ff_Yn[29]), .A1(n4492), .B0(d_ff2_Y[29]), .B1(n4501),
.Y(n2160) );
AO22XLTS U5965 ( .A0(n4494), .A1(d_ff2_Y[29]), .B0(n4489), .B1(
d_ff3_sh_y_out[29]), .Y(n2159) );
AO22XLTS U5966 ( .A0(d_ff_Yn[30]), .A1(n4497), .B0(d_ff2_Y[30]), .B1(n4404),
.Y(n2158) );
AO22XLTS U5967 ( .A0(n4510), .A1(d_ff2_Y[30]), .B0(n4499), .B1(
d_ff3_sh_y_out[30]), .Y(n2157) );
AO22XLTS U5968 ( .A0(d_ff_Yn[31]), .A1(n4492), .B0(d_ff2_Y[31]), .B1(n4404),
.Y(n2156) );
AO22XLTS U5969 ( .A0(n4530), .A1(d_ff2_Y[31]), .B0(n4490), .B1(
d_ff3_sh_y_out[31]), .Y(n2155) );
AO22XLTS U5970 ( .A0(d_ff_Yn[32]), .A1(n4492), .B0(d_ff2_Y[32]), .B1(n4527),
.Y(n2154) );
AO22XLTS U5971 ( .A0(n4510), .A1(d_ff2_Y[32]), .B0(n4499), .B1(
d_ff3_sh_y_out[32]), .Y(n2153) );
AO22XLTS U5972 ( .A0(d_ff_Yn[33]), .A1(n4497), .B0(d_ff2_Y[33]), .B1(n3305),
.Y(n2152) );
AO22XLTS U5973 ( .A0(n4521), .A1(d_ff2_Y[33]), .B0(n4499), .B1(
d_ff3_sh_y_out[33]), .Y(n2151) );
AO22XLTS U5974 ( .A0(d_ff_Yn[34]), .A1(n3301), .B0(d_ff2_Y[34]), .B1(n4501),
.Y(n2150) );
AO22XLTS U5975 ( .A0(n4493), .A1(d_ff2_Y[34]), .B0(n4499), .B1(
d_ff3_sh_y_out[34]), .Y(n2149) );
AO22XLTS U5976 ( .A0(d_ff_Yn[35]), .A1(n4497), .B0(d_ff2_Y[35]), .B1(n4527),
.Y(n2148) );
AO22XLTS U5977 ( .A0(n4498), .A1(d_ff2_Y[35]), .B0(n4499), .B1(
d_ff3_sh_y_out[35]), .Y(n2147) );
AO22XLTS U5978 ( .A0(d_ff_Yn[36]), .A1(n4497), .B0(d_ff2_Y[36]), .B1(n4527),
.Y(n2146) );
AO22XLTS U5979 ( .A0(n4521), .A1(d_ff2_Y[36]), .B0(n4499), .B1(
d_ff3_sh_y_out[36]), .Y(n2145) );
AO22XLTS U5980 ( .A0(d_ff_Yn[37]), .A1(n4528), .B0(d_ff2_Y[37]), .B1(n4527),
.Y(n2144) );
AO22XLTS U5981 ( .A0(n4493), .A1(d_ff2_Y[37]), .B0(n4499), .B1(
d_ff3_sh_y_out[37]), .Y(n2143) );
AO22XLTS U5982 ( .A0(d_ff_Yn[38]), .A1(n4497), .B0(d_ff2_Y[38]), .B1(n4527),
.Y(n2142) );
AO22XLTS U5983 ( .A0(n4498), .A1(d_ff2_Y[38]), .B0(n4499), .B1(
d_ff3_sh_y_out[38]), .Y(n2141) );
AO22XLTS U5984 ( .A0(d_ff_Yn[39]), .A1(n4528), .B0(d_ff2_Y[39]), .B1(n4527),
.Y(n2140) );
AO22XLTS U5985 ( .A0(n4521), .A1(d_ff2_Y[39]), .B0(n4499), .B1(
d_ff3_sh_y_out[39]), .Y(n2139) );
AO22XLTS U5986 ( .A0(d_ff_Yn[40]), .A1(n4497), .B0(d_ff2_Y[40]), .B1(n4501),
.Y(n2138) );
AO22XLTS U5987 ( .A0(n4493), .A1(d_ff2_Y[40]), .B0(n4499), .B1(
d_ff3_sh_y_out[40]), .Y(n2137) );
AO22XLTS U5988 ( .A0(d_ff_Yn[41]), .A1(n4528), .B0(d_ff2_Y[41]), .B1(n4501),
.Y(n2136) );
AO22XLTS U5989 ( .A0(n4494), .A1(d_ff2_Y[41]), .B0(n4518), .B1(
d_ff3_sh_y_out[41]), .Y(n2135) );
AO22XLTS U5990 ( .A0(d_ff_Yn[42]), .A1(n4497), .B0(d_ff2_Y[42]), .B1(n3305),
.Y(n2134) );
AO22XLTS U5991 ( .A0(n4530), .A1(d_ff2_Y[42]), .B0(n4518), .B1(
d_ff3_sh_y_out[42]), .Y(n2133) );
AO22XLTS U5992 ( .A0(d_ff_Yn[43]), .A1(n4528), .B0(d_ff2_Y[43]), .B1(n4501),
.Y(n2132) );
AO22XLTS U5993 ( .A0(n4496), .A1(d_ff2_Y[43]), .B0(n4518), .B1(
d_ff3_sh_y_out[43]), .Y(n2131) );
AO22XLTS U5994 ( .A0(d_ff_Yn[44]), .A1(n4497), .B0(d_ff2_Y[44]), .B1(n4500),
.Y(n2130) );
AO22XLTS U5995 ( .A0(n4488), .A1(d_ff2_Y[44]), .B0(n4518), .B1(
d_ff3_sh_y_out[44]), .Y(n2129) );
AO22XLTS U5996 ( .A0(d_ff_Yn[45]), .A1(n4497), .B0(d_ff2_Y[45]), .B1(n4500),
.Y(n2128) );
AO22XLTS U5997 ( .A0(n4494), .A1(d_ff2_Y[45]), .B0(n4499), .B1(
d_ff3_sh_y_out[45]), .Y(n2127) );
AO22XLTS U5998 ( .A0(d_ff_Yn[46]), .A1(n4497), .B0(d_ff2_Y[46]), .B1(n4501),
.Y(n2126) );
AO22XLTS U5999 ( .A0(n4498), .A1(d_ff2_Y[46]), .B0(n4518), .B1(
d_ff3_sh_y_out[46]), .Y(n2125) );
AO22XLTS U6000 ( .A0(d_ff_Yn[47]), .A1(n4528), .B0(d_ff2_Y[47]), .B1(n4501),
.Y(n2124) );
AO22XLTS U6001 ( .A0(n4493), .A1(d_ff2_Y[47]), .B0(n4518), .B1(
d_ff3_sh_y_out[47]), .Y(n2123) );
AO22XLTS U6002 ( .A0(d_ff_Yn[48]), .A1(n4497), .B0(d_ff2_Y[48]), .B1(n4501),
.Y(n2122) );
AO22XLTS U6003 ( .A0(n4495), .A1(d_ff2_Y[48]), .B0(n4518), .B1(
d_ff3_sh_y_out[48]), .Y(n2121) );
AO22XLTS U6004 ( .A0(d_ff_Yn[49]), .A1(n4528), .B0(d_ff2_Y[49]), .B1(n4501),
.Y(n2120) );
AO22XLTS U6005 ( .A0(n4521), .A1(d_ff2_Y[49]), .B0(n4518), .B1(
d_ff3_sh_y_out[49]), .Y(n2119) );
AO22XLTS U6006 ( .A0(d_ff_Yn[50]), .A1(n4497), .B0(d_ff2_Y[50]), .B1(n4501),
.Y(n2118) );
AO22XLTS U6007 ( .A0(n4488), .A1(d_ff2_Y[50]), .B0(n4518), .B1(
d_ff3_sh_y_out[50]), .Y(n2117) );
AO22XLTS U6008 ( .A0(d_ff_Yn[51]), .A1(n4528), .B0(d_ff2_Y[51]), .B1(n4501),
.Y(n2116) );
AO22XLTS U6009 ( .A0(n4530), .A1(d_ff2_Y[51]), .B0(n4499), .B1(
d_ff3_sh_y_out[51]), .Y(n2115) );
OAI22X1TS U6010 ( .A0(n5070), .A1(n2955), .B0(n4504), .B1(n4503), .Y(n2114)
);
AO22XLTS U6011 ( .A0(d_ff_Yn[53]), .A1(n4528), .B0(d_ff2_Y[53]), .B1(n4501),
.Y(n2113) );
AO22XLTS U6012 ( .A0(d_ff_Yn[54]), .A1(n4528), .B0(d_ff2_Y[54]), .B1(n4501),
.Y(n2112) );
AO22XLTS U6013 ( .A0(d_ff_Yn[55]), .A1(n4528), .B0(d_ff2_Y[55]), .B1(n4527),
.Y(n2111) );
AO22XLTS U6014 ( .A0(d_ff_Yn[56]), .A1(n4528), .B0(d_ff2_Y[56]), .B1(n4527),
.Y(n2110) );
OAI22X1TS U6015 ( .A0(n5008), .A1(n4503), .B0(n2980), .B1(n4502), .Y(n2109)
);
INVX1TS U6016 ( .A(d_ff2_Y[58]), .Y(n4511) );
OAI22X1TS U6017 ( .A0(n4511), .A1(n4503), .B0(n2981), .B1(n4502), .Y(n2108)
);
AO22XLTS U6018 ( .A0(d_ff_Yn[59]), .A1(n4528), .B0(d_ff2_Y[59]), .B1(n4527),
.Y(n2107) );
INVX1TS U6019 ( .A(d_ff2_Y[60]), .Y(n4516) );
OAI22X1TS U6020 ( .A0(n4516), .A1(n4503), .B0(n2982), .B1(n4502), .Y(n2106)
);
AO22XLTS U6021 ( .A0(d_ff_Yn[61]), .A1(n4528), .B0(d_ff2_Y[61]), .B1(n4527),
.Y(n2105) );
AO22XLTS U6022 ( .A0(d_ff_Yn[62]), .A1(n4528), .B0(d_ff2_Y[62]), .B1(n4527),
.Y(n2104) );
OAI21XLTS U6023 ( .A0(cont_iter_out[0]), .A1(n4504), .B0(intadd_374_CI), .Y(
n4506) );
AO22XLTS U6024 ( .A0(n4488), .A1(n4506), .B0(n4507), .B1(d_ff3_sh_y_out[52]),
.Y(n2103) );
AO22XLTS U6025 ( .A0(n4530), .A1(intadd_374_SUM_0_), .B0(n4507), .B1(
d_ff3_sh_y_out[53]), .Y(n2102) );
AO22XLTS U6026 ( .A0(n4494), .A1(intadd_374_SUM_1_), .B0(n4507), .B1(
d_ff3_sh_y_out[54]), .Y(n2101) );
AO22XLTS U6027 ( .A0(n4530), .A1(intadd_374_SUM_2_), .B0(n4518), .B1(
d_ff3_sh_y_out[55]), .Y(n2100) );
AOI21X1TS U6028 ( .A0(d_ff2_Y[56]), .A1(intadd_374_n1), .B0(n4508), .Y(n4509) );
AOI2BB1XLTS U6029 ( .A0N(n4510), .A1N(d_ff3_sh_y_out[56]), .B0(n4509), .Y(
n2099) );
NAND2X1TS U6030 ( .A(n4512), .B(n4511), .Y(n4514) );
OAI21XLTS U6031 ( .A0(n4512), .A1(n4511), .B0(n4514), .Y(n4513) );
AO22XLTS U6032 ( .A0(n4530), .A1(n4513), .B0(n3023), .B1(d_ff3_sh_y_out[58]),
.Y(n2097) );
AOI21X1TS U6033 ( .A0(d_ff2_Y[59]), .A1(n4514), .B0(n4517), .Y(n4515) );
AOI2BB2XLTS U6034 ( .B0(n4523), .B1(n4515), .A0N(d_ff3_sh_y_out[59]), .A1N(
n4494), .Y(n2096) );
NAND2X1TS U6035 ( .A(n4517), .B(n4516), .Y(n4520) );
OAI21XLTS U6036 ( .A0(n4517), .A1(n4516), .B0(n4520), .Y(n4519) );
AO22XLTS U6037 ( .A0(n4494), .A1(n4519), .B0(n4518), .B1(d_ff3_sh_y_out[60]),
.Y(n2095) );
NOR2X1TS U6038 ( .A(d_ff2_Y[61]), .B(n4520), .Y(n4524) );
AOI21X1TS U6039 ( .A0(d_ff2_Y[61]), .A1(n4520), .B0(n4524), .Y(n4522) );
AOI2BB2XLTS U6040 ( .B0(n4523), .B1(n4522), .A0N(d_ff3_sh_y_out[61]), .A1N(
n4496), .Y(n2094) );
XOR2XLTS U6041 ( .A(d_ff2_Y[62]), .B(n4524), .Y(n4526) );
AO22XLTS U6042 ( .A0(n4530), .A1(n4526), .B0(n4525), .B1(d_ff3_sh_y_out[62]),
.Y(n2093) );
AO22XLTS U6043 ( .A0(d_ff_Yn[63]), .A1(n4528), .B0(d_ff2_Y[63]), .B1(n4527),
.Y(n2092) );
AO22XLTS U6044 ( .A0(n4496), .A1(d_ff2_Y[63]), .B0(n4529), .B1(
d_ff3_sh_y_out[63]), .Y(n2091) );
AO22XLTS U6045 ( .A0(n4531), .A1(result_add_subt[0]), .B0(n2956), .B1(
d_ff_Xn[0]), .Y(n2090) );
INVX4TS U6046 ( .A(n4533), .Y(n4536) );
AO22XLTS U6047 ( .A0(n4536), .A1(sign_inv_out[0]), .B0(n4305), .B1(
data_output[0]), .Y(n2088) );
AO22XLTS U6048 ( .A0(n4536), .A1(sign_inv_out[1]), .B0(n4533), .B1(
data_output[1]), .Y(n2086) );
AO22XLTS U6049 ( .A0(n4536), .A1(sign_inv_out[2]), .B0(n4532), .B1(
data_output[2]), .Y(n2084) );
AO22XLTS U6050 ( .A0(n4536), .A1(sign_inv_out[3]), .B0(n4532), .B1(
data_output[3]), .Y(n2082) );
AO22XLTS U6051 ( .A0(n4536), .A1(sign_inv_out[4]), .B0(n4532), .B1(
data_output[4]), .Y(n2080) );
AO22XLTS U6052 ( .A0(n4536), .A1(sign_inv_out[5]), .B0(n4532), .B1(
data_output[5]), .Y(n2078) );
AO22XLTS U6053 ( .A0(n4536), .A1(sign_inv_out[6]), .B0(n4532), .B1(
data_output[6]), .Y(n2076) );
AO22XLTS U6054 ( .A0(n4536), .A1(sign_inv_out[7]), .B0(n4532), .B1(
data_output[7]), .Y(n2074) );
AO22XLTS U6055 ( .A0(n4536), .A1(sign_inv_out[8]), .B0(n4532), .B1(
data_output[8]), .Y(n2072) );
AO22XLTS U6056 ( .A0(n4536), .A1(sign_inv_out[9]), .B0(n4532), .B1(
data_output[9]), .Y(n2070) );
AO22XLTS U6057 ( .A0(n4536), .A1(sign_inv_out[10]), .B0(n4532), .B1(
data_output[10]), .Y(n2068) );
AO22XLTS U6058 ( .A0(n4536), .A1(sign_inv_out[11]), .B0(n4532), .B1(
data_output[11]), .Y(n2066) );
INVX4TS U6059 ( .A(n4533), .Y(n4535) );
CLKBUFX3TS U6060 ( .A(n4305), .Y(n4540) );
AO22XLTS U6061 ( .A0(n4535), .A1(sign_inv_out[12]), .B0(n4540), .B1(
data_output[12]), .Y(n2064) );
AO22XLTS U6062 ( .A0(n4535), .A1(sign_inv_out[13]), .B0(n4532), .B1(
data_output[13]), .Y(n2062) );
AO22XLTS U6063 ( .A0(n4535), .A1(sign_inv_out[14]), .B0(n4305), .B1(
data_output[14]), .Y(n2060) );
AO22XLTS U6064 ( .A0(n4535), .A1(sign_inv_out[15]), .B0(n4532), .B1(
data_output[15]), .Y(n2058) );
AO22XLTS U6065 ( .A0(n4535), .A1(sign_inv_out[16]), .B0(n4532), .B1(
data_output[16]), .Y(n2056) );
AO22XLTS U6066 ( .A0(n4535), .A1(sign_inv_out[17]), .B0(n4532), .B1(
data_output[17]), .Y(n2054) );
AO22XLTS U6067 ( .A0(n4535), .A1(sign_inv_out[18]), .B0(n4532), .B1(
data_output[18]), .Y(n2052) );
AO22XLTS U6068 ( .A0(n4535), .A1(sign_inv_out[19]), .B0(n4532), .B1(
data_output[19]), .Y(n2050) );
AO22XLTS U6069 ( .A0(n4535), .A1(sign_inv_out[20]), .B0(n4532), .B1(
data_output[20]), .Y(n2048) );
AO22XLTS U6070 ( .A0(n4535), .A1(sign_inv_out[21]), .B0(n4532), .B1(
data_output[21]), .Y(n2046) );
AO22XLTS U6071 ( .A0(n4535), .A1(sign_inv_out[22]), .B0(n4532), .B1(
data_output[22]), .Y(n2044) );
AO22XLTS U6072 ( .A0(n4535), .A1(sign_inv_out[23]), .B0(n4533), .B1(
data_output[23]), .Y(n2042) );
INVX4TS U6073 ( .A(n4533), .Y(n4534) );
AO22XLTS U6074 ( .A0(n4534), .A1(sign_inv_out[24]), .B0(n4533), .B1(
data_output[24]), .Y(n2040) );
AO22XLTS U6075 ( .A0(n4534), .A1(sign_inv_out[25]), .B0(n4533), .B1(
data_output[25]), .Y(n2038) );
AO22XLTS U6076 ( .A0(n4534), .A1(sign_inv_out[26]), .B0(n4533), .B1(
data_output[26]), .Y(n2036) );
AO22XLTS U6077 ( .A0(n4534), .A1(sign_inv_out[27]), .B0(n4533), .B1(
data_output[27]), .Y(n2034) );
AO22XLTS U6078 ( .A0(n4534), .A1(sign_inv_out[28]), .B0(n4533), .B1(
data_output[28]), .Y(n2032) );
AO22XLTS U6079 ( .A0(n4534), .A1(sign_inv_out[29]), .B0(n4533), .B1(
data_output[29]), .Y(n2030) );
AO22XLTS U6080 ( .A0(n4534), .A1(sign_inv_out[30]), .B0(n4533), .B1(
data_output[30]), .Y(n2028) );
AO22XLTS U6081 ( .A0(n4534), .A1(sign_inv_out[31]), .B0(n4533), .B1(
data_output[31]), .Y(n2026) );
AO22XLTS U6082 ( .A0(n4534), .A1(sign_inv_out[32]), .B0(n4533), .B1(
data_output[32]), .Y(n2024) );
AO22XLTS U6083 ( .A0(n4534), .A1(sign_inv_out[33]), .B0(n4533), .B1(
data_output[33]), .Y(n2022) );
AO22XLTS U6084 ( .A0(n4534), .A1(sign_inv_out[34]), .B0(n4540), .B1(
data_output[34]), .Y(n2020) );
AO22XLTS U6085 ( .A0(n4534), .A1(sign_inv_out[35]), .B0(n4533), .B1(
data_output[35]), .Y(n2018) );
AO22XLTS U6086 ( .A0(n4536), .A1(sign_inv_out[36]), .B0(n4533), .B1(
data_output[36]), .Y(n2016) );
AO22XLTS U6087 ( .A0(n4534), .A1(sign_inv_out[37]), .B0(n4533), .B1(
data_output[37]), .Y(n2014) );
AO22XLTS U6088 ( .A0(n4535), .A1(sign_inv_out[38]), .B0(n4533), .B1(
data_output[38]), .Y(n2012) );
AO22XLTS U6089 ( .A0(n4536), .A1(sign_inv_out[39]), .B0(n4533), .B1(
data_output[39]), .Y(n2010) );
AO22XLTS U6090 ( .A0(n4534), .A1(sign_inv_out[40]), .B0(n4533), .B1(
data_output[40]), .Y(n2008) );
AO22XLTS U6091 ( .A0(n4535), .A1(sign_inv_out[41]), .B0(n4533), .B1(
data_output[41]), .Y(n2006) );
AO22XLTS U6092 ( .A0(n4536), .A1(sign_inv_out[42]), .B0(n4533), .B1(
data_output[42]), .Y(n2004) );
AO22XLTS U6093 ( .A0(n4534), .A1(sign_inv_out[43]), .B0(n4533), .B1(
data_output[43]), .Y(n2002) );
AO22XLTS U6094 ( .A0(n4535), .A1(sign_inv_out[44]), .B0(n4533), .B1(
data_output[44]), .Y(n2000) );
AO22XLTS U6095 ( .A0(n4536), .A1(sign_inv_out[45]), .B0(n4305), .B1(
data_output[45]), .Y(n1998) );
INVX4TS U6096 ( .A(n4305), .Y(n4542) );
AO22XLTS U6097 ( .A0(n4542), .A1(sign_inv_out[46]), .B0(n4305), .B1(
data_output[46]), .Y(n1996) );
AO22XLTS U6098 ( .A0(n4542), .A1(sign_inv_out[47]), .B0(n4305), .B1(
data_output[47]), .Y(n1994) );
AO22XLTS U6099 ( .A0(n4542), .A1(sign_inv_out[48]), .B0(n4305), .B1(
data_output[48]), .Y(n1992) );
AO22XLTS U6100 ( .A0(n4542), .A1(sign_inv_out[49]), .B0(n4305), .B1(
data_output[49]), .Y(n1990) );
AO22XLTS U6101 ( .A0(n4542), .A1(sign_inv_out[50]), .B0(n4305), .B1(
data_output[50]), .Y(n1988) );
AO22XLTS U6102 ( .A0(n4542), .A1(sign_inv_out[51]), .B0(n4305), .B1(
data_output[51]), .Y(n1986) );
AO22XLTS U6103 ( .A0(n4542), .A1(sign_inv_out[52]), .B0(n4305), .B1(
data_output[52]), .Y(n1984) );
AO22XLTS U6104 ( .A0(n4542), .A1(sign_inv_out[53]), .B0(n4305), .B1(
data_output[53]), .Y(n1982) );
AO22XLTS U6105 ( .A0(n4542), .A1(sign_inv_out[54]), .B0(n4305), .B1(
data_output[54]), .Y(n1980) );
AO22XLTS U6106 ( .A0(n4542), .A1(sign_inv_out[55]), .B0(n4540), .B1(
data_output[55]), .Y(n1978) );
AO22XLTS U6107 ( .A0(n4542), .A1(sign_inv_out[56]), .B0(n4540), .B1(
data_output[56]), .Y(n1976) );
AO22XLTS U6108 ( .A0(n4542), .A1(sign_inv_out[57]), .B0(n4540), .B1(
data_output[57]), .Y(n1974) );
AO22XLTS U6109 ( .A0(n4542), .A1(sign_inv_out[58]), .B0(n4540), .B1(
data_output[58]), .Y(n1972) );
AO22XLTS U6110 ( .A0(n4542), .A1(sign_inv_out[59]), .B0(n4540), .B1(
data_output[59]), .Y(n1970) );
AO22XLTS U6111 ( .A0(n4542), .A1(sign_inv_out[60]), .B0(n4540), .B1(
data_output[60]), .Y(n1968) );
AO22XLTS U6112 ( .A0(n4542), .A1(sign_inv_out[61]), .B0(n4540), .B1(
data_output[61]), .Y(n1966) );
AO22XLTS U6113 ( .A0(n4542), .A1(sign_inv_out[62]), .B0(n4540), .B1(
data_output[62]), .Y(n1964) );
OAI221XLTS U6114 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_shift_region_flag_out[0]), .B0(n5002), .B1(d_ff1_operation_out),
.C0(n4538), .Y(n4539) );
XNOR2X1TS U6115 ( .A(data_output2_63_), .B(n4539), .Y(n4541) );
AO22XLTS U6116 ( .A0(n4542), .A1(n4541), .B0(n4540), .B1(data_output[63]),
.Y(n1961) );
AOI22X1TS U6117 ( .A0(d_ff3_LUT_out[0]), .A1(n4797), .B0(n4802), .B1(
d_ff3_sh_y_out[0]), .Y(n4544) );
AOI22X1TS U6118 ( .A0(add_subt_module_intDY[0]), .A1(n4714), .B0(n4677),
.B1(d_ff3_sh_x_out[0]), .Y(n4543) );
NAND2X1TS U6119 ( .A(n4544), .B(n4543), .Y(n1958) );
AOI22X1TS U6120 ( .A0(add_subt_module_intDY[56]), .A1(n4714), .B0(n4645),
.B1(d_ff3_sh_y_out[56]), .Y(n4547) );
BUFX4TS U6121 ( .A(n4545), .Y(n4776) );
AOI22X1TS U6122 ( .A0(n4677), .A1(d_ff3_sh_x_out[56]), .B0(n4804), .B1(
d_ff3_LUT_out[56]), .Y(n4546) );
NAND2X1TS U6123 ( .A(n4547), .B(n4546), .Y(n1951) );
BUFX4TS U6124 ( .A(n4545), .Y(n4790) );
AOI22X1TS U6125 ( .A0(d_ff3_LUT_out[55]), .A1(n4790), .B0(n4645), .B1(
d_ff3_sh_y_out[55]), .Y(n4549) );
AOI22X1TS U6126 ( .A0(add_subt_module_intDY[55]), .A1(n4660), .B0(n4773),
.B1(d_ff3_sh_x_out[55]), .Y(n4548) );
NAND2X1TS U6127 ( .A(n4549), .B(n4548), .Y(n1950) );
AOI22X1TS U6128 ( .A0(d_ff3_LUT_out[54]), .A1(n4790), .B0(n4645), .B1(
d_ff3_sh_y_out[54]), .Y(n4551) );
AOI22X1TS U6129 ( .A0(add_subt_module_intDY[54]), .A1(n4660), .B0(n4773),
.B1(d_ff3_sh_x_out[54]), .Y(n4550) );
NAND2X1TS U6130 ( .A(n4551), .B(n4550), .Y(n1949) );
AOI22X1TS U6131 ( .A0(n4804), .A1(d_ff3_LUT_out[53]), .B0(n4786), .B1(
d_ff3_sh_y_out[53]), .Y(n4553) );
AOI22X1TS U6132 ( .A0(add_subt_module_intDY[53]), .A1(n4660), .B0(n4696),
.B1(d_ff3_sh_x_out[53]), .Y(n4552) );
NAND2X1TS U6133 ( .A(n4553), .B(n4552), .Y(n1948) );
AOI22X1TS U6134 ( .A0(n4779), .A1(d_ff3_LUT_out[52]), .B0(n4802), .B1(
d_ff3_sh_y_out[52]), .Y(n4555) );
AOI22X1TS U6135 ( .A0(add_subt_module_intDY[52]), .A1(n4660), .B0(n4773),
.B1(d_ff3_sh_x_out[52]), .Y(n4554) );
NAND2X1TS U6136 ( .A(n4555), .B(n4554), .Y(n1947) );
AOI22X1TS U6137 ( .A0(d_ff2_Z[63]), .A1(n4790), .B0(n4645), .B1(d_ff2_X[63]),
.Y(n4557) );
AOI22X1TS U6138 ( .A0(add_subt_module_intDX[63]), .A1(n4660), .B0(n4696),
.B1(d_ff2_Y[63]), .Y(n4556) );
NAND2X1TS U6139 ( .A(n4557), .B(n4556), .Y(n1945) );
OAI21XLTS U6140 ( .A0(n4559), .A1(n4558), .B0(n5009), .Y(n4563) );
OAI21XLTS U6141 ( .A0(n4561), .A1(n3711), .B0(n4560), .Y(n4562) );
AO22XLTS U6142 ( .A0(add_subt_module_sign_final_result), .A1(n3700), .B0(
n4563), .B1(n4562), .Y(n1943) );
AOI22X1TS U6143 ( .A0(d_ff2_X[62]), .A1(n4782), .B0(d_ff2_Y[62]), .B1(n4805),
.Y(n4566) );
AOI22X1TS U6144 ( .A0(add_subt_module_intDX[62]), .A1(n4660), .B0(
d_ff2_Z[62]), .B1(n4790), .Y(n4565) );
NAND2X1TS U6145 ( .A(n4566), .B(n4565), .Y(n1942) );
AOI22X1TS U6146 ( .A0(d_ff2_X[61]), .A1(n4786), .B0(d_ff2_Z[61]), .B1(n4776),
.Y(n4568) );
AOI22X1TS U6147 ( .A0(add_subt_module_intDX[61]), .A1(n4660), .B0(
d_ff2_Y[61]), .B1(n4773), .Y(n4567) );
NAND2X1TS U6148 ( .A(n4568), .B(n4567), .Y(n1939) );
AOI22X1TS U6149 ( .A0(d_ff2_X[60]), .A1(n4786), .B0(d_ff2_Z[60]), .B1(n4776),
.Y(n4570) );
AOI22X1TS U6150 ( .A0(add_subt_module_intDX[60]), .A1(n4660), .B0(
d_ff2_Y[60]), .B1(n4798), .Y(n4569) );
NAND2X1TS U6151 ( .A(n4570), .B(n4569), .Y(n1936) );
BUFX4TS U6152 ( .A(n4701), .Y(n4796) );
AOI22X1TS U6153 ( .A0(d_ff2_X[59]), .A1(n4796), .B0(d_ff2_Z[59]), .B1(n4776),
.Y(n4572) );
AOI22X1TS U6154 ( .A0(add_subt_module_intDX[59]), .A1(n4660), .B0(
d_ff2_Y[59]), .B1(n4773), .Y(n4571) );
NAND2X1TS U6155 ( .A(n4572), .B(n4571), .Y(n1933) );
AOI22X1TS U6156 ( .A0(d_ff2_X[58]), .A1(n4782), .B0(d_ff2_Z[58]), .B1(n4776),
.Y(n4574) );
AOI22X1TS U6157 ( .A0(add_subt_module_intDX[58]), .A1(n4660), .B0(
d_ff2_Y[58]), .B1(n4696), .Y(n4573) );
NAND2X1TS U6158 ( .A(n4574), .B(n4573), .Y(n1930) );
AOI22X1TS U6159 ( .A0(d_ff2_X[57]), .A1(n4802), .B0(d_ff2_Z[57]), .B1(n4776),
.Y(n4576) );
AOI22X1TS U6160 ( .A0(add_subt_module_intDX[57]), .A1(n4660), .B0(
d_ff2_Y[57]), .B1(n4773), .Y(n4575) );
NAND2X1TS U6161 ( .A(n4576), .B(n4575), .Y(n1927) );
AOI22X1TS U6162 ( .A0(add_subt_module_intDX[56]), .A1(n4660), .B0(
d_ff2_X[56]), .B1(n4645), .Y(n4578) );
AOI22X1TS U6163 ( .A0(d_ff2_Y[56]), .A1(n4798), .B0(d_ff2_Z[56]), .B1(n4776),
.Y(n4577) );
NAND2X1TS U6164 ( .A(n4578), .B(n4577), .Y(n1924) );
AOI22X1TS U6165 ( .A0(d_ff2_Z[55]), .A1(n4790), .B0(n4645), .B1(d_ff2_X[55]),
.Y(n4580) );
AOI22X1TS U6166 ( .A0(add_subt_module_intDX[55]), .A1(n4660), .B0(n4798),
.B1(d_ff2_Y[55]), .Y(n4579) );
NAND2X1TS U6167 ( .A(n4580), .B(n4579), .Y(n1921) );
AOI22X1TS U6168 ( .A0(d_ff2_Z[54]), .A1(n4790), .B0(n4802), .B1(d_ff2_X[54]),
.Y(n4582) );
AOI22X1TS U6169 ( .A0(add_subt_module_intDX[54]), .A1(n4660), .B0(n4696),
.B1(d_ff2_Y[54]), .Y(n4581) );
NAND2X1TS U6170 ( .A(n4582), .B(n4581), .Y(n1918) );
AOI22X1TS U6171 ( .A0(n4805), .A1(d_ff2_Y[53]), .B0(n4645), .B1(d_ff2_X[53]),
.Y(n4584) );
AOI22X1TS U6172 ( .A0(add_subt_module_intDX[53]), .A1(n4631), .B0(
d_ff2_Z[53]), .B1(n4776), .Y(n4583) );
NAND2X1TS U6173 ( .A(n4584), .B(n4583), .Y(n1915) );
AOI22X1TS U6174 ( .A0(n4790), .A1(d_ff2_Z[52]), .B0(n4802), .B1(d_ff2_X[52]),
.Y(n4586) );
AOI22X1TS U6175 ( .A0(add_subt_module_intDX[52]), .A1(n4631), .B0(n4798),
.B1(d_ff2_Y[52]), .Y(n4585) );
NAND2X1TS U6176 ( .A(n4586), .B(n4585), .Y(n1912) );
AOI22X1TS U6177 ( .A0(d_ff2_Z[0]), .A1(n4790), .B0(n4802), .B1(d_ff2_X[0]),
.Y(n4588) );
AOI22X1TS U6178 ( .A0(add_subt_module_intDX[0]), .A1(n4660), .B0(n4805),
.B1(d_ff2_Y[0]), .Y(n4587) );
NAND2X1TS U6179 ( .A(n4588), .B(n4587), .Y(n1909) );
AOI22X1TS U6180 ( .A0(d_ff2_Z[51]), .A1(n4790), .B0(n4802), .B1(d_ff2_X[51]),
.Y(n4590) );
AOI22X1TS U6181 ( .A0(add_subt_module_intDX[51]), .A1(n4631), .B0(n4798),
.B1(d_ff2_Y[51]), .Y(n4589) );
NAND2X1TS U6182 ( .A(n4590), .B(n4589), .Y(n1907) );
AOI22X1TS U6183 ( .A0(n4790), .A1(d_ff2_Z[4]), .B0(n4802), .B1(d_ff2_X[4]),
.Y(n4592) );
AOI22X1TS U6184 ( .A0(add_subt_module_intDX[4]), .A1(n4714), .B0(n4677),
.B1(d_ff2_Y[4]), .Y(n4591) );
NAND2X1TS U6185 ( .A(n4592), .B(n4591), .Y(n1904) );
AOI22X1TS U6186 ( .A0(add_subt_module_intDY[4]), .A1(n4631), .B0(n4802),
.B1(d_ff3_sh_y_out[4]), .Y(n4594) );
AOI22X1TS U6187 ( .A0(d_ff3_LUT_out[4]), .A1(n4779), .B0(n4677), .B1(
d_ff3_sh_x_out[4]), .Y(n4593) );
NAND2X1TS U6188 ( .A(n4594), .B(n4593), .Y(n1903) );
AOI22X1TS U6189 ( .A0(n4805), .A1(d_ff2_Y[48]), .B0(n4796), .B1(d_ff2_X[48]),
.Y(n4596) );
AOI22X1TS U6190 ( .A0(add_subt_module_intDX[48]), .A1(n4799), .B0(
d_ff2_Z[48]), .B1(n4776), .Y(n4595) );
NAND2X1TS U6191 ( .A(n4596), .B(n4595), .Y(n1901) );
AOI22X1TS U6192 ( .A0(n4798), .A1(d_ff2_Y[2]), .B0(n4642), .B1(d_ff2_X[2]),
.Y(n4598) );
AOI22X1TS U6193 ( .A0(add_subt_module_intDX[2]), .A1(n4631), .B0(d_ff2_Z[2]),
.B1(n4804), .Y(n4597) );
NAND2X1TS U6194 ( .A(n4598), .B(n4597), .Y(n1897) );
AOI22X1TS U6195 ( .A0(n4696), .A1(d_ff3_sh_x_out[2]), .B0(n4642), .B1(
d_ff3_sh_y_out[2]), .Y(n4600) );
AOI22X1TS U6196 ( .A0(add_subt_module_intDY[2]), .A1(n4631), .B0(n4776),
.B1(d_ff3_LUT_out[2]), .Y(n4599) );
NAND2X1TS U6197 ( .A(n4600), .B(n4599), .Y(n1896) );
AOI22X1TS U6198 ( .A0(n4798), .A1(d_ff2_Y[50]), .B0(n4642), .B1(d_ff2_X[50]),
.Y(n4602) );
AOI22X1TS U6199 ( .A0(add_subt_module_intDX[50]), .A1(n4631), .B0(
d_ff2_Z[50]), .B1(n4804), .Y(n4601) );
NAND2X1TS U6200 ( .A(n4602), .B(n4601), .Y(n1894) );
AOI22X1TS U6201 ( .A0(n4779), .A1(d_ff3_LUT_out[50]), .B0(n4642), .B1(
d_ff3_sh_y_out[50]), .Y(n4604) );
AOI22X1TS U6202 ( .A0(add_subt_module_intDY[50]), .A1(n4660), .B0(n4696),
.B1(d_ff3_sh_x_out[50]), .Y(n4603) );
NAND2X1TS U6203 ( .A(n4604), .B(n4603), .Y(n1893) );
AOI22X1TS U6204 ( .A0(n4696), .A1(d_ff2_Y[47]), .B0(n4642), .B1(d_ff2_X[47]),
.Y(n4606) );
AOI22X1TS U6205 ( .A0(add_subt_module_intDX[47]), .A1(n4631), .B0(
d_ff2_Z[47]), .B1(n4804), .Y(n4605) );
NAND2X1TS U6206 ( .A(n4606), .B(n4605), .Y(n1891) );
AOI22X1TS U6207 ( .A0(add_subt_module_intDY[47]), .A1(n4714), .B0(n4642),
.B1(d_ff3_sh_y_out[47]), .Y(n4608) );
AOI22X1TS U6208 ( .A0(n4798), .A1(d_ff3_sh_x_out[47]), .B0(n4804), .B1(
d_ff3_LUT_out[47]), .Y(n4607) );
NAND2X1TS U6209 ( .A(n4608), .B(n4607), .Y(n1890) );
AOI22X1TS U6210 ( .A0(add_subt_module_intDX[3]), .A1(n4631), .B0(n4642),
.B1(d_ff2_X[3]), .Y(n4610) );
AOI22X1TS U6211 ( .A0(d_ff2_Z[3]), .A1(n4790), .B0(n4805), .B1(d_ff2_Y[3]),
.Y(n4609) );
NAND2X1TS U6212 ( .A(n4610), .B(n4609), .Y(n1887) );
AOI22X1TS U6213 ( .A0(n4779), .A1(d_ff3_LUT_out[3]), .B0(n4642), .B1(
d_ff3_sh_y_out[3]), .Y(n4612) );
AOI22X1TS U6214 ( .A0(add_subt_module_intDY[3]), .A1(n4631), .B0(n4798),
.B1(d_ff3_sh_x_out[3]), .Y(n4611) );
NAND2X1TS U6215 ( .A(n4612), .B(n4611), .Y(n1886) );
AOI22X1TS U6216 ( .A0(n4798), .A1(d_ff2_Y[1]), .B0(n4642), .B1(d_ff2_X[1]),
.Y(n4614) );
AOI22X1TS U6217 ( .A0(add_subt_module_intDX[1]), .A1(n4660), .B0(d_ff2_Z[1]),
.B1(n4776), .Y(n4613) );
NAND2X1TS U6218 ( .A(n4614), .B(n4613), .Y(n1884) );
AOI22X1TS U6219 ( .A0(add_subt_module_intDY[1]), .A1(n4714), .B0(n4642),
.B1(d_ff3_sh_y_out[1]), .Y(n4616) );
AOI22X1TS U6220 ( .A0(d_ff3_LUT_out[1]), .A1(n4790), .B0(n4798), .B1(
d_ff3_sh_x_out[1]), .Y(n4615) );
NAND2X1TS U6221 ( .A(n4616), .B(n4615), .Y(n1883) );
AOI22X1TS U6222 ( .A0(d_ff2_Z[49]), .A1(n4790), .B0(n4642), .B1(d_ff2_X[49]),
.Y(n4618) );
AOI22X1TS U6223 ( .A0(add_subt_module_intDX[49]), .A1(n4631), .B0(n4677),
.B1(d_ff2_Y[49]), .Y(n4617) );
NAND2X1TS U6224 ( .A(n4618), .B(n4617), .Y(n1881) );
AOI22X1TS U6225 ( .A0(n4805), .A1(d_ff3_sh_x_out[49]), .B0(n4642), .B1(
d_ff3_sh_y_out[49]), .Y(n4620) );
AOI22X1TS U6226 ( .A0(add_subt_module_intDY[49]), .A1(n4631), .B0(n4776),
.B1(d_ff3_LUT_out[49]), .Y(n4619) );
NAND2X1TS U6227 ( .A(n4620), .B(n4619), .Y(n1880) );
AOI22X1TS U6228 ( .A0(n4677), .A1(d_ff2_Y[46]), .B0(n4645), .B1(d_ff2_X[46]),
.Y(n4622) );
AOI22X1TS U6229 ( .A0(add_subt_module_intDX[46]), .A1(n4631), .B0(
d_ff2_Z[46]), .B1(n4804), .Y(n4621) );
NAND2X1TS U6230 ( .A(n4622), .B(n4621), .Y(n1877) );
AOI22X1TS U6231 ( .A0(n4798), .A1(d_ff3_sh_x_out[46]), .B0(n4642), .B1(
d_ff3_sh_y_out[46]), .Y(n4624) );
AOI22X1TS U6232 ( .A0(add_subt_module_intDY[46]), .A1(n4631), .B0(n4804),
.B1(d_ff3_LUT_out[46]), .Y(n4623) );
NAND2X1TS U6233 ( .A(n4624), .B(n4623), .Y(n1876) );
AOI22X1TS U6234 ( .A0(n4677), .A1(d_ff2_Y[16]), .B0(n4642), .B1(d_ff2_X[16]),
.Y(n4626) );
AOI22X1TS U6235 ( .A0(add_subt_module_intDX[16]), .A1(n4631), .B0(
d_ff2_Z[16]), .B1(n4804), .Y(n4625) );
NAND2X1TS U6236 ( .A(n4626), .B(n4625), .Y(n1873) );
AOI22X1TS U6237 ( .A0(add_subt_module_intDY[16]), .A1(n4660), .B0(n4802),
.B1(d_ff3_sh_y_out[16]), .Y(n4628) );
AOI22X1TS U6238 ( .A0(n4677), .A1(d_ff3_sh_x_out[16]), .B0(n4804), .B1(
d_ff3_LUT_out[16]), .Y(n4627) );
NAND2X1TS U6239 ( .A(n4628), .B(n4627), .Y(n1872) );
AOI22X1TS U6240 ( .A0(n4805), .A1(d_ff2_Y[9]), .B0(n4642), .B1(d_ff2_X[9]),
.Y(n4630) );
AOI22X1TS U6241 ( .A0(add_subt_module_intDX[9]), .A1(n4631), .B0(d_ff2_Z[9]),
.B1(n4804), .Y(n4629) );
NAND2X1TS U6242 ( .A(n4630), .B(n4629), .Y(n1870) );
AOI22X1TS U6243 ( .A0(n4696), .A1(d_ff3_sh_x_out[9]), .B0(n4642), .B1(
d_ff3_sh_y_out[9]), .Y(n4633) );
AOI22X1TS U6244 ( .A0(add_subt_module_intDY[9]), .A1(n4631), .B0(
d_ff3_LUT_out[9]), .B1(n4804), .Y(n4632) );
NAND2X1TS U6245 ( .A(n4633), .B(n4632), .Y(n1869) );
AOI22X1TS U6246 ( .A0(add_subt_module_intDX[44]), .A1(n4631), .B0(n4642),
.B1(d_ff2_X[44]), .Y(n4635) );
AOI22X1TS U6247 ( .A0(d_ff2_Z[44]), .A1(n4779), .B0(n4677), .B1(d_ff2_Y[44]),
.Y(n4634) );
NAND2X1TS U6248 ( .A(n4635), .B(n4634), .Y(n1867) );
AOI22X1TS U6249 ( .A0(add_subt_module_intDY[44]), .A1(n4660), .B0(n4642),
.B1(d_ff3_sh_y_out[44]), .Y(n4637) );
AOI22X1TS U6250 ( .A0(n4696), .A1(d_ff3_sh_x_out[44]), .B0(n4804), .B1(
d_ff3_LUT_out[44]), .Y(n4636) );
NAND2X1TS U6251 ( .A(n4637), .B(n4636), .Y(n1866) );
AOI22X1TS U6252 ( .A0(d_ff2_Z[6]), .A1(n4779), .B0(n4642), .B1(d_ff2_X[6]),
.Y(n4639) );
AOI22X1TS U6253 ( .A0(add_subt_module_intDX[6]), .A1(n4631), .B0(n4805),
.B1(d_ff2_Y[6]), .Y(n4638) );
NAND2X1TS U6254 ( .A(n4639), .B(n4638), .Y(n1863) );
AOI22X1TS U6255 ( .A0(n4779), .A1(d_ff3_LUT_out[6]), .B0(n4642), .B1(
d_ff3_sh_y_out[6]), .Y(n4641) );
AOI22X1TS U6256 ( .A0(add_subt_module_intDY[6]), .A1(n4660), .B0(n4677),
.B1(d_ff3_sh_x_out[6]), .Y(n4640) );
NAND2X1TS U6257 ( .A(n4641), .B(n4640), .Y(n1862) );
AOI22X1TS U6258 ( .A0(d_ff2_Z[5]), .A1(n4779), .B0(n4642), .B1(d_ff2_X[5]),
.Y(n4644) );
AOI22X1TS U6259 ( .A0(add_subt_module_intDX[5]), .A1(n4631), .B0(n4798),
.B1(d_ff2_Y[5]), .Y(n4643) );
NAND2X1TS U6260 ( .A(n4644), .B(n4643), .Y(n1860) );
AOI22X1TS U6261 ( .A0(add_subt_module_intDY[5]), .A1(n4631), .B0(n4645),
.B1(d_ff3_sh_y_out[5]), .Y(n4647) );
AOI22X1TS U6262 ( .A0(d_ff3_LUT_out[5]), .A1(n4779), .B0(n4805), .B1(
d_ff3_sh_x_out[5]), .Y(n4646) );
NAND2X1TS U6263 ( .A(n4647), .B(n4646), .Y(n1859) );
AOI22X1TS U6264 ( .A0(add_subt_module_intDX[45]), .A1(n4631), .B0(n4802),
.B1(d_ff2_X[45]), .Y(n4649) );
AOI22X1TS U6265 ( .A0(d_ff2_Z[45]), .A1(n4779), .B0(n4805), .B1(d_ff2_Y[45]),
.Y(n4648) );
NAND2X1TS U6266 ( .A(n4649), .B(n4648), .Y(n1857) );
AOI22X1TS U6267 ( .A0(add_subt_module_intDY[45]), .A1(n4793), .B0(n4802),
.B1(d_ff3_sh_y_out[45]), .Y(n4651) );
AOI22X1TS U6268 ( .A0(n4677), .A1(d_ff3_sh_x_out[45]), .B0(n4804), .B1(
d_ff3_LUT_out[45]), .Y(n4650) );
NAND2X1TS U6269 ( .A(n4651), .B(n4650), .Y(n1856) );
AOI22X1TS U6270 ( .A0(d_ff2_Z[20]), .A1(n4779), .B0(n4802), .B1(d_ff2_X[20]),
.Y(n4653) );
AOI22X1TS U6271 ( .A0(add_subt_module_intDX[20]), .A1(n4660), .B0(n4696),
.B1(d_ff2_Y[20]), .Y(n4652) );
NAND2X1TS U6272 ( .A(n4653), .B(n4652), .Y(n1853) );
AOI22X1TS U6273 ( .A0(n4797), .A1(d_ff3_LUT_out[20]), .B0(n4802), .B1(
d_ff3_sh_y_out[20]), .Y(n4655) );
AOI22X1TS U6274 ( .A0(add_subt_module_intDY[20]), .A1(n4631), .B0(n4798),
.B1(d_ff3_sh_x_out[20]), .Y(n4654) );
NAND2X1TS U6275 ( .A(n4655), .B(n4654), .Y(n1852) );
AOI22X1TS U6276 ( .A0(d_ff2_Z[13]), .A1(n4779), .B0(n4802), .B1(d_ff2_X[13]),
.Y(n4657) );
AOI22X1TS U6277 ( .A0(add_subt_module_intDX[13]), .A1(n4793), .B0(n4696),
.B1(d_ff2_Y[13]), .Y(n4656) );
NAND2X1TS U6278 ( .A(n4657), .B(n4656), .Y(n1850) );
AOI22X1TS U6279 ( .A0(n4797), .A1(d_ff3_LUT_out[13]), .B0(n4802), .B1(
d_ff3_sh_y_out[13]), .Y(n4659) );
AOI22X1TS U6280 ( .A0(add_subt_module_intDY[13]), .A1(n4631), .B0(n4798),
.B1(d_ff3_sh_x_out[13]), .Y(n4658) );
NAND2X1TS U6281 ( .A(n4659), .B(n4658), .Y(n1849) );
AOI22X1TS U6282 ( .A0(add_subt_module_intDX[10]), .A1(n4631), .B0(n4802),
.B1(d_ff2_X[10]), .Y(n4662) );
AOI22X1TS U6283 ( .A0(d_ff2_Z[10]), .A1(n4779), .B0(n4805), .B1(d_ff2_Y[10]),
.Y(n4661) );
NAND2X1TS U6284 ( .A(n4662), .B(n4661), .Y(n1847) );
AOI22X1TS U6285 ( .A0(n4696), .A1(d_ff3_sh_x_out[10]), .B0(n4802), .B1(
d_ff3_sh_y_out[10]), .Y(n4664) );
AOI22X1TS U6286 ( .A0(add_subt_module_intDY[10]), .A1(n4803), .B0(n4790),
.B1(d_ff3_LUT_out[10]), .Y(n4663) );
NAND2X1TS U6287 ( .A(n4664), .B(n4663), .Y(n1846) );
AOI22X1TS U6288 ( .A0(d_ff2_Z[43]), .A1(n4779), .B0(n4802), .B1(d_ff2_X[43]),
.Y(n4666) );
AOI22X1TS U6289 ( .A0(add_subt_module_intDX[43]), .A1(n4803), .B0(n4696),
.B1(d_ff2_Y[43]), .Y(n4665) );
NAND2X1TS U6290 ( .A(n4666), .B(n4665), .Y(n1844) );
AOI22X1TS U6291 ( .A0(d_ff3_LUT_out[43]), .A1(n4779), .B0(n4802), .B1(
d_ff3_sh_y_out[43]), .Y(n4668) );
AOI22X1TS U6292 ( .A0(add_subt_module_intDY[43]), .A1(n4803), .B0(n4677),
.B1(d_ff3_sh_x_out[43]), .Y(n4667) );
NAND2X1TS U6293 ( .A(n4668), .B(n4667), .Y(n1843) );
AOI22X1TS U6294 ( .A0(d_ff2_Z[7]), .A1(n4779), .B0(n4802), .B1(d_ff2_X[7]),
.Y(n4670) );
AOI22X1TS U6295 ( .A0(add_subt_module_intDX[7]), .A1(n4803), .B0(n4798),
.B1(d_ff2_Y[7]), .Y(n4669) );
NAND2X1TS U6296 ( .A(n4670), .B(n4669), .Y(n1840) );
AOI22X1TS U6297 ( .A0(add_subt_module_intDY[7]), .A1(n4803), .B0(n4802),
.B1(d_ff3_sh_y_out[7]), .Y(n4672) );
AOI22X1TS U6298 ( .A0(d_ff3_LUT_out[7]), .A1(n4797), .B0(n4805), .B1(
d_ff3_sh_x_out[7]), .Y(n4671) );
NAND2X1TS U6299 ( .A(n4672), .B(n4671), .Y(n1839) );
AOI22X1TS U6300 ( .A0(d_ff2_Z[40]), .A1(n4797), .B0(n4802), .B1(d_ff2_X[40]),
.Y(n4674) );
AOI22X1TS U6301 ( .A0(add_subt_module_intDX[40]), .A1(n4803), .B0(n4805),
.B1(d_ff2_Y[40]), .Y(n4673) );
NAND2X1TS U6302 ( .A(n4674), .B(n4673), .Y(n1837) );
AOI22X1TS U6303 ( .A0(d_ff3_LUT_out[40]), .A1(n4790), .B0(n4701), .B1(
d_ff3_sh_y_out[40]), .Y(n4676) );
AOI22X1TS U6304 ( .A0(add_subt_module_intDY[40]), .A1(n4803), .B0(n4677),
.B1(d_ff3_sh_x_out[40]), .Y(n4675) );
NAND2X1TS U6305 ( .A(n4676), .B(n4675), .Y(n1836) );
AOI22X1TS U6306 ( .A0(add_subt_module_intDX[38]), .A1(n4803), .B0(n4701),
.B1(d_ff2_X[38]), .Y(n4679) );
AOI22X1TS U6307 ( .A0(d_ff2_Z[38]), .A1(n4783), .B0(n4805), .B1(d_ff2_Y[38]),
.Y(n4678) );
NAND2X1TS U6308 ( .A(n4679), .B(n4678), .Y(n1833) );
AOI22X1TS U6309 ( .A0(n4798), .A1(d_ff3_sh_x_out[38]), .B0(n4701), .B1(
d_ff3_sh_y_out[38]), .Y(n4681) );
AOI22X1TS U6310 ( .A0(add_subt_module_intDY[38]), .A1(n4803), .B0(
d_ff3_LUT_out[38]), .B1(n4804), .Y(n4680) );
NAND2X1TS U6311 ( .A(n4681), .B(n4680), .Y(n1832) );
AOI22X1TS U6312 ( .A0(n4783), .A1(d_ff2_Z[12]), .B0(n4701), .B1(d_ff2_X[12]),
.Y(n4683) );
AOI22X1TS U6313 ( .A0(add_subt_module_intDX[12]), .A1(n4803), .B0(n4805),
.B1(d_ff2_Y[12]), .Y(n4682) );
NAND2X1TS U6314 ( .A(n4683), .B(n4682), .Y(n1829) );
AOI22X1TS U6315 ( .A0(n4805), .A1(d_ff3_sh_x_out[12]), .B0(n4701), .B1(
d_ff3_sh_y_out[12]), .Y(n4685) );
AOI22X1TS U6316 ( .A0(add_subt_module_intDY[12]), .A1(n4803), .B0(
d_ff3_LUT_out[12]), .B1(n4804), .Y(n4684) );
NAND2X1TS U6317 ( .A(n4685), .B(n4684), .Y(n1828) );
AOI22X1TS U6318 ( .A0(n4789), .A1(d_ff2_Y[11]), .B0(n4701), .B1(d_ff2_X[11]),
.Y(n4687) );
AOI22X1TS U6319 ( .A0(add_subt_module_intDX[11]), .A1(n4803), .B0(
d_ff2_Z[11]), .B1(n4776), .Y(n4686) );
NAND2X1TS U6320 ( .A(n4687), .B(n4686), .Y(n1826) );
AOI22X1TS U6321 ( .A0(d_ff3_LUT_out[11]), .A1(n4783), .B0(n4701), .B1(
d_ff3_sh_y_out[11]), .Y(n4689) );
AOI22X1TS U6322 ( .A0(add_subt_module_intDY[11]), .A1(n4714), .B0(n4805),
.B1(d_ff3_sh_x_out[11]), .Y(n4688) );
NAND2X1TS U6323 ( .A(n4689), .B(n4688), .Y(n1825) );
AOI22X1TS U6324 ( .A0(n4789), .A1(d_ff2_Y[42]), .B0(n4701), .B1(d_ff2_X[42]),
.Y(n4691) );
AOI22X1TS U6325 ( .A0(add_subt_module_intDX[42]), .A1(n4714), .B0(
d_ff2_Z[42]), .B1(n4804), .Y(n4690) );
NAND2X1TS U6326 ( .A(n4691), .B(n4690), .Y(n1823) );
AOI22X1TS U6327 ( .A0(n4779), .A1(d_ff3_LUT_out[42]), .B0(n4701), .B1(
d_ff3_sh_y_out[42]), .Y(n4693) );
AOI22X1TS U6328 ( .A0(add_subt_module_intDY[42]), .A1(n4714), .B0(n4798),
.B1(d_ff3_sh_x_out[42]), .Y(n4692) );
NAND2X1TS U6329 ( .A(n4693), .B(n4692), .Y(n1822) );
AOI22X1TS U6330 ( .A0(n4789), .A1(d_ff2_Y[8]), .B0(n4701), .B1(d_ff2_X[8]),
.Y(n4695) );
AOI22X1TS U6331 ( .A0(add_subt_module_intDX[8]), .A1(n4714), .B0(d_ff2_Z[8]),
.B1(n4804), .Y(n4694) );
NAND2X1TS U6332 ( .A(n4695), .B(n4694), .Y(n1819) );
AOI22X1TS U6333 ( .A0(d_ff3_LUT_out[8]), .A1(n4797), .B0(n4701), .B1(
d_ff3_sh_y_out[8]), .Y(n4698) );
AOI22X1TS U6334 ( .A0(add_subt_module_intDY[8]), .A1(n4714), .B0(n4677),
.B1(d_ff3_sh_x_out[8]), .Y(n4697) );
NAND2X1TS U6335 ( .A(n4698), .B(n4697), .Y(n1818) );
AOI22X1TS U6336 ( .A0(d_ff2_Z[41]), .A1(n4797), .B0(n4701), .B1(d_ff2_X[41]),
.Y(n4700) );
AOI22X1TS U6337 ( .A0(add_subt_module_intDX[41]), .A1(n4714), .B0(n4773),
.B1(d_ff2_Y[41]), .Y(n4699) );
NAND2X1TS U6338 ( .A(n4700), .B(n4699), .Y(n1816) );
AOI22X1TS U6339 ( .A0(n4779), .A1(d_ff3_LUT_out[41]), .B0(n4701), .B1(
d_ff3_sh_y_out[41]), .Y(n4703) );
AOI22X1TS U6340 ( .A0(add_subt_module_intDY[41]), .A1(n4714), .B0(n4773),
.B1(d_ff3_sh_x_out[41]), .Y(n4702) );
NAND2X1TS U6341 ( .A(n4703), .B(n4702), .Y(n1815) );
AOI22X1TS U6342 ( .A0(n4789), .A1(d_ff2_Y[39]), .B0(n4782), .B1(d_ff2_X[39]),
.Y(n4705) );
AOI22X1TS U6343 ( .A0(add_subt_module_intDX[39]), .A1(n4714), .B0(
d_ff2_Z[39]), .B1(n4776), .Y(n4704) );
NAND2X1TS U6344 ( .A(n4705), .B(n4704), .Y(n1812) );
AOI22X1TS U6345 ( .A0(n4779), .A1(d_ff3_LUT_out[39]), .B0(n4782), .B1(
d_ff3_sh_y_out[39]), .Y(n4707) );
AOI22X1TS U6346 ( .A0(add_subt_module_intDY[39]), .A1(n4714), .B0(n4805),
.B1(d_ff3_sh_x_out[39]), .Y(n4706) );
NAND2X1TS U6347 ( .A(n4707), .B(n4706), .Y(n1811) );
AOI22X1TS U6348 ( .A0(n4783), .A1(d_ff2_Z[37]), .B0(n4782), .B1(d_ff2_X[37]),
.Y(n4709) );
AOI22X1TS U6349 ( .A0(add_subt_module_intDX[37]), .A1(n4714), .B0(n4773),
.B1(d_ff2_Y[37]), .Y(n4708) );
NAND2X1TS U6350 ( .A(n4709), .B(n4708), .Y(n1809) );
AOI22X1TS U6351 ( .A0(add_subt_module_intDY[37]), .A1(n4714), .B0(n4782),
.B1(d_ff3_sh_y_out[37]), .Y(n4711) );
AOI22X1TS U6352 ( .A0(n4789), .A1(d_ff3_sh_x_out[37]), .B0(n4804), .B1(
d_ff3_LUT_out[37]), .Y(n4710) );
NAND2X1TS U6353 ( .A(n4711), .B(n4710), .Y(n1808) );
AOI22X1TS U6354 ( .A0(d_ff2_Z[19]), .A1(n4779), .B0(n4782), .B1(d_ff2_X[19]),
.Y(n4713) );
AOI22X1TS U6355 ( .A0(add_subt_module_intDX[19]), .A1(n4714), .B0(n4773),
.B1(d_ff2_Y[19]), .Y(n4712) );
NAND2X1TS U6356 ( .A(n4713), .B(n4712), .Y(n1804) );
AOI22X1TS U6357 ( .A0(add_subt_module_intDY[19]), .A1(n4714), .B0(n4782),
.B1(d_ff3_sh_y_out[19]), .Y(n4716) );
AOI22X1TS U6358 ( .A0(n4789), .A1(d_ff3_sh_x_out[19]), .B0(n4804), .B1(
d_ff3_LUT_out[19]), .Y(n4715) );
NAND2X1TS U6359 ( .A(n4716), .B(n4715), .Y(n1803) );
AOI22X1TS U6360 ( .A0(d_ff2_Z[34]), .A1(n4790), .B0(n4782), .B1(d_ff2_X[34]),
.Y(n4718) );
AOI22X1TS U6361 ( .A0(add_subt_module_intDX[34]), .A1(n4793), .B0(n4773),
.B1(d_ff2_Y[34]), .Y(n4717) );
NAND2X1TS U6362 ( .A(n4718), .B(n4717), .Y(n1801) );
AOI22X1TS U6363 ( .A0(d_ff2_Z[23]), .A1(n4783), .B0(n4782), .B1(d_ff2_X[23]),
.Y(n4720) );
AOI22X1TS U6364 ( .A0(add_subt_module_intDX[23]), .A1(n4793), .B0(n4773),
.B1(d_ff2_Y[23]), .Y(n4719) );
NAND2X1TS U6365 ( .A(n4720), .B(n4719), .Y(n1798) );
AOI22X1TS U6366 ( .A0(d_ff3_LUT_out[23]), .A1(n4783), .B0(n4782), .B1(
d_ff3_sh_y_out[23]), .Y(n4722) );
AOI22X1TS U6367 ( .A0(add_subt_module_intDY[23]), .A1(n4793), .B0(n4773),
.B1(d_ff3_sh_x_out[23]), .Y(n4721) );
NAND2X1TS U6368 ( .A(n4722), .B(n4721), .Y(n1797) );
AOI22X1TS U6369 ( .A0(d_ff2_Z[30]), .A1(n4783), .B0(n4782), .B1(d_ff2_X[30]),
.Y(n4724) );
AOI22X1TS U6370 ( .A0(add_subt_module_intDX[30]), .A1(n4793), .B0(n4773),
.B1(d_ff2_Y[30]), .Y(n4723) );
NAND2X1TS U6371 ( .A(n4724), .B(n4723), .Y(n1795) );
AOI22X1TS U6372 ( .A0(n4789), .A1(d_ff2_Y[35]), .B0(n4782), .B1(d_ff2_X[35]),
.Y(n4726) );
AOI22X1TS U6373 ( .A0(add_subt_module_intDX[35]), .A1(n4793), .B0(
d_ff2_Z[35]), .B1(n4804), .Y(n4725) );
NAND2X1TS U6374 ( .A(n4726), .B(n4725), .Y(n1792) );
AOI22X1TS U6375 ( .A0(n4783), .A1(d_ff2_Z[15]), .B0(n4786), .B1(d_ff2_X[15]),
.Y(n4728) );
AOI22X1TS U6376 ( .A0(add_subt_module_intDX[15]), .A1(n4793), .B0(n4773),
.B1(d_ff2_Y[15]), .Y(n4727) );
NAND2X1TS U6377 ( .A(n4728), .B(n4727), .Y(n1788) );
AOI22X1TS U6378 ( .A0(d_ff3_LUT_out[15]), .A1(n4779), .B0(n4786), .B1(
d_ff3_sh_y_out[15]), .Y(n4730) );
AOI22X1TS U6379 ( .A0(add_subt_module_intDY[15]), .A1(n4793), .B0(n4773),
.B1(d_ff3_sh_x_out[15]), .Y(n4729) );
NAND2X1TS U6380 ( .A(n4730), .B(n4729), .Y(n1787) );
AOI22X1TS U6381 ( .A0(d_ff2_Z[36]), .A1(n4783), .B0(n4786), .B1(d_ff2_X[36]),
.Y(n4732) );
AOI22X1TS U6382 ( .A0(add_subt_module_intDX[36]), .A1(n4793), .B0(n4773),
.B1(d_ff2_Y[36]), .Y(n4731) );
NAND2X1TS U6383 ( .A(n4732), .B(n4731), .Y(n1785) );
AOI22X1TS U6384 ( .A0(d_ff3_LUT_out[36]), .A1(n4783), .B0(n4786), .B1(
d_ff3_sh_y_out[36]), .Y(n4734) );
AOI22X1TS U6385 ( .A0(add_subt_module_intDY[36]), .A1(n4793), .B0(n4773),
.B1(d_ff3_sh_x_out[36]), .Y(n4733) );
NAND2X1TS U6386 ( .A(n4734), .B(n4733), .Y(n1784) );
AOI22X1TS U6387 ( .A0(add_subt_module_intDX[14]), .A1(n4793), .B0(n4786),
.B1(d_ff2_X[14]), .Y(n4736) );
AOI22X1TS U6388 ( .A0(d_ff2_Z[14]), .A1(n4783), .B0(n4773), .B1(d_ff2_Y[14]),
.Y(n4735) );
NAND2X1TS U6389 ( .A(n4736), .B(n4735), .Y(n1781) );
AOI22X1TS U6390 ( .A0(add_subt_module_intDY[14]), .A1(n4799), .B0(n4786),
.B1(d_ff3_sh_y_out[14]), .Y(n4738) );
AOI22X1TS U6391 ( .A0(d_ff3_LUT_out[14]), .A1(n4783), .B0(n3040), .B1(
d_ff3_sh_x_out[14]), .Y(n4737) );
NAND2X1TS U6392 ( .A(n4738), .B(n4737), .Y(n1780) );
AOI22X1TS U6393 ( .A0(n4783), .A1(d_ff2_Z[27]), .B0(n4786), .B1(d_ff2_X[27]),
.Y(n4740) );
AOI22X1TS U6394 ( .A0(add_subt_module_intDX[27]), .A1(n4799), .B0(n3040),
.B1(d_ff2_Y[27]), .Y(n4739) );
NAND2X1TS U6395 ( .A(n4740), .B(n4739), .Y(n1778) );
AOI22X1TS U6396 ( .A0(d_ff3_LUT_out[27]), .A1(n4783), .B0(n4786), .B1(
d_ff3_sh_y_out[27]), .Y(n4742) );
AOI22X1TS U6397 ( .A0(add_subt_module_intDY[27]), .A1(n4793), .B0(n4773),
.B1(d_ff3_sh_x_out[27]), .Y(n4741) );
NAND2X1TS U6398 ( .A(n4742), .B(n4741), .Y(n1777) );
AOI22X1TS U6399 ( .A0(add_subt_module_intDX[31]), .A1(n4799), .B0(n4786),
.B1(d_ff2_X[31]), .Y(n4744) );
AOI22X1TS U6400 ( .A0(d_ff2_Z[31]), .A1(n4797), .B0(n4798), .B1(d_ff2_Y[31]),
.Y(n4743) );
NAND2X1TS U6401 ( .A(n4744), .B(n4743), .Y(n1774) );
AOI22X1TS U6402 ( .A0(n4779), .A1(d_ff3_LUT_out[31]), .B0(n4786), .B1(
d_ff3_sh_y_out[31]), .Y(n4746) );
AOI22X1TS U6403 ( .A0(add_subt_module_intDY[31]), .A1(n4799), .B0(n3040),
.B1(d_ff3_sh_x_out[31]), .Y(n4745) );
NAND2X1TS U6404 ( .A(n4746), .B(n4745), .Y(n1773) );
AOI22X1TS U6405 ( .A0(add_subt_module_intDX[29]), .A1(n4799), .B0(n4786),
.B1(d_ff2_X[29]), .Y(n4748) );
AOI22X1TS U6406 ( .A0(d_ff2_Z[29]), .A1(n4797), .B0(n4773), .B1(d_ff2_Y[29]),
.Y(n4747) );
NAND2X1TS U6407 ( .A(n4748), .B(n4747), .Y(n1770) );
AOI22X1TS U6408 ( .A0(n4779), .A1(d_ff3_LUT_out[29]), .B0(n4786), .B1(
d_ff3_sh_y_out[29]), .Y(n4750) );
AOI22X1TS U6409 ( .A0(add_subt_module_intDY[29]), .A1(n4799), .B0(n3040),
.B1(d_ff3_sh_x_out[29]), .Y(n4749) );
NAND2X1TS U6410 ( .A(n4750), .B(n4749), .Y(n1769) );
AOI22X1TS U6411 ( .A0(n4797), .A1(d_ff2_Z[21]), .B0(n4796), .B1(d_ff2_X[21]),
.Y(n4752) );
AOI22X1TS U6412 ( .A0(add_subt_module_intDX[21]), .A1(n4793), .B0(n4773),
.B1(d_ff2_Y[21]), .Y(n4751) );
NAND2X1TS U6413 ( .A(n4752), .B(n4751), .Y(n1766) );
AOI22X1TS U6414 ( .A0(n4779), .A1(d_ff3_LUT_out[21]), .B0(n4796), .B1(
d_ff3_sh_y_out[21]), .Y(n4754) );
AOI22X1TS U6415 ( .A0(add_subt_module_intDY[21]), .A1(n4799), .B0(n3040),
.B1(d_ff3_sh_x_out[21]), .Y(n4753) );
NAND2X1TS U6416 ( .A(n4754), .B(n4753), .Y(n1765) );
AOI22X1TS U6417 ( .A0(n4789), .A1(d_ff2_Y[18]), .B0(n4796), .B1(d_ff2_X[18]),
.Y(n4756) );
AOI22X1TS U6418 ( .A0(add_subt_module_intDX[18]), .A1(n4799), .B0(
d_ff2_Z[18]), .B1(n4804), .Y(n4755) );
NAND2X1TS U6419 ( .A(n4756), .B(n4755), .Y(n1763) );
AOI22X1TS U6420 ( .A0(n4789), .A1(d_ff3_sh_x_out[18]), .B0(n4796), .B1(
d_ff3_sh_y_out[18]), .Y(n4758) );
AOI22X1TS U6421 ( .A0(add_subt_module_intDY[18]), .A1(n4799), .B0(
d_ff3_LUT_out[18]), .B1(n4776), .Y(n4757) );
NAND2X1TS U6422 ( .A(n4758), .B(n4757), .Y(n1762) );
AOI22X1TS U6423 ( .A0(add_subt_module_intDX[25]), .A1(n4799), .B0(n4796),
.B1(d_ff2_X[25]), .Y(n4760) );
AOI22X1TS U6424 ( .A0(d_ff2_Z[25]), .A1(n4797), .B0(n4798), .B1(d_ff2_Y[25]),
.Y(n4759) );
NAND2X1TS U6425 ( .A(n4760), .B(n4759), .Y(n1760) );
AOI22X1TS U6426 ( .A0(add_subt_module_intDY[25]), .A1(n4799), .B0(n4796),
.B1(d_ff3_sh_y_out[25]), .Y(n4762) );
AOI22X1TS U6427 ( .A0(d_ff3_LUT_out[25]), .A1(n4797), .B0(n4798), .B1(
d_ff3_sh_x_out[25]), .Y(n4761) );
NAND2X1TS U6428 ( .A(n4762), .B(n4761), .Y(n1759) );
AOI22X1TS U6429 ( .A0(d_ff2_Z[33]), .A1(n4797), .B0(n4796), .B1(d_ff2_X[33]),
.Y(n4764) );
AOI22X1TS U6430 ( .A0(add_subt_module_intDX[33]), .A1(n4793), .B0(n4805),
.B1(d_ff2_Y[33]), .Y(n4763) );
NAND2X1TS U6431 ( .A(n4764), .B(n4763), .Y(n1756) );
AOI22X1TS U6432 ( .A0(add_subt_module_intDY[33]), .A1(n4799), .B0(n4796),
.B1(d_ff3_sh_y_out[33]), .Y(n4766) );
AOI22X1TS U6433 ( .A0(d_ff3_LUT_out[33]), .A1(n4783), .B0(n4696), .B1(
d_ff3_sh_x_out[33]), .Y(n4765) );
NAND2X1TS U6434 ( .A(n4766), .B(n4765), .Y(n1755) );
AOI22X1TS U6435 ( .A0(n4789), .A1(d_ff2_Y[17]), .B0(n4796), .B1(d_ff2_X[17]),
.Y(n4768) );
AOI22X1TS U6436 ( .A0(add_subt_module_intDX[17]), .A1(n4793), .B0(
d_ff2_Z[17]), .B1(n4776), .Y(n4767) );
NAND2X1TS U6437 ( .A(n4768), .B(n4767), .Y(n1752) );
AOI22X1TS U6438 ( .A0(n4789), .A1(d_ff3_sh_x_out[17]), .B0(n4796), .B1(
d_ff3_sh_y_out[17]), .Y(n4770) );
AOI22X1TS U6439 ( .A0(add_subt_module_intDY[17]), .A1(n4799), .B0(n4776),
.B1(d_ff3_LUT_out[17]), .Y(n4769) );
NAND2X1TS U6440 ( .A(n4770), .B(n4769), .Y(n1751) );
AOI22X1TS U6441 ( .A0(d_ff2_Z[32]), .A1(n4797), .B0(n4782), .B1(d_ff2_X[32]),
.Y(n4772) );
AOI22X1TS U6442 ( .A0(add_subt_module_intDX[32]), .A1(n4799), .B0(n4677),
.B1(d_ff2_Y[32]), .Y(n4771) );
NAND2X1TS U6443 ( .A(n4772), .B(n4771), .Y(n1749) );
AOI22X1TS U6444 ( .A0(d_ff3_LUT_out[32]), .A1(n4797), .B0(n4796), .B1(
d_ff3_sh_y_out[32]), .Y(n4775) );
AOI22X1TS U6445 ( .A0(n2997), .A1(n4793), .B0(n4773), .B1(d_ff3_sh_x_out[32]), .Y(n4774) );
NAND2X1TS U6446 ( .A(n4775), .B(n4774), .Y(n1748) );
AOI22X1TS U6447 ( .A0(n4789), .A1(d_ff2_Y[24]), .B0(n4796), .B1(d_ff2_X[24]),
.Y(n4778) );
AOI22X1TS U6448 ( .A0(add_subt_module_intDX[24]), .A1(n4799), .B0(
d_ff2_Z[24]), .B1(n4776), .Y(n4777) );
NAND2X1TS U6449 ( .A(n4778), .B(n4777), .Y(n1745) );
AOI22X1TS U6450 ( .A0(n4779), .A1(d_ff3_LUT_out[24]), .B0(n4796), .B1(
d_ff3_sh_y_out[24]), .Y(n4781) );
AOI22X1TS U6451 ( .A0(n2998), .A1(n4799), .B0(n4696), .B1(d_ff3_sh_x_out[24]), .Y(n4780) );
NAND2X1TS U6452 ( .A(n4781), .B(n4780), .Y(n1744) );
AOI22X1TS U6453 ( .A0(add_subt_module_intDX[22]), .A1(n4799), .B0(n4782),
.B1(d_ff2_X[22]), .Y(n4785) );
AOI22X1TS U6454 ( .A0(d_ff2_Z[22]), .A1(n4783), .B0(n4798), .B1(d_ff2_Y[22]),
.Y(n4784) );
NAND2X1TS U6455 ( .A(n4785), .B(n4784), .Y(n1742) );
AOI22X1TS U6456 ( .A0(n4804), .A1(d_ff3_LUT_out[22]), .B0(n4786), .B1(
d_ff3_sh_y_out[22]), .Y(n4788) );
AOI22X1TS U6457 ( .A0(n2995), .A1(n4799), .B0(n4798), .B1(d_ff3_sh_x_out[22]), .Y(n4787) );
NAND2X1TS U6458 ( .A(n4788), .B(n4787), .Y(n1741) );
AOI22X1TS U6459 ( .A0(n4789), .A1(d_ff2_Y[28]), .B0(n4802), .B1(d_ff2_X[28]),
.Y(n4792) );
AOI22X1TS U6460 ( .A0(add_subt_module_intDX[28]), .A1(n4793), .B0(
d_ff2_Z[28]), .B1(n4790), .Y(n4791) );
NAND2X1TS U6461 ( .A(n4792), .B(n4791), .Y(n1739) );
AOI22X1TS U6462 ( .A0(d_ff3_LUT_out[28]), .A1(n4797), .B0(n4796), .B1(
d_ff3_sh_y_out[28]), .Y(n4795) );
AOI22X1TS U6463 ( .A0(add_subt_module_intDY[28]), .A1(n4793), .B0(n4805),
.B1(d_ff3_sh_x_out[28]), .Y(n4794) );
NAND2X1TS U6464 ( .A(n4795), .B(n4794), .Y(n1738) );
AOI22X1TS U6465 ( .A0(n4797), .A1(d_ff2_Z[26]), .B0(n4796), .B1(d_ff2_X[26]),
.Y(n4801) );
AOI22X1TS U6466 ( .A0(add_subt_module_intDX[26]), .A1(n4799), .B0(n4696),
.B1(d_ff2_Y[26]), .Y(n4800) );
NAND2X1TS U6467 ( .A(n4801), .B(n4800), .Y(n1735) );
AOI22X1TS U6468 ( .A0(add_subt_module_intDY[26]), .A1(n4803), .B0(n4802),
.B1(d_ff3_sh_y_out[26]), .Y(n4807) );
AOI22X1TS U6469 ( .A0(n4805), .A1(d_ff3_sh_x_out[26]), .B0(n4804), .B1(
d_ff3_LUT_out[26]), .Y(n4806) );
NAND2X1TS U6470 ( .A(n4807), .B(n4806), .Y(n1734) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk40.tcl_syn.sdf");
endmodule
|
`timescale 1ns/1ps
module flushMUX(flushIDEX,RegDstin,RegWrin,ALUSrc1in,ALUSrc2in,ALUFunin,Signin,MemWrin,MemRdin,MemtoRegin,
RegDstout,RegWrout,ALUSrc1out,ALUSrc2out,ALUFunout,Signout,MemWrout,MemRdout,MemtoRegout);
input flushIDEX;
input [1:0] RegDstin;
input RegWrin;
input ALUSrc1in;
input ALUSrc2in;
input [5:0] ALUFunin;
input Signin;
input MemWrin;
input MemRdin;
input [1:0] MemtoRegin;
output [1:0] RegDstout;
reg [1:0] RegDstout;
output RegWrout;
reg RegWrout;
output ALUSrc1out;
reg ALUSrc1out;
output ALUSrc2out;
reg ALUSrc2out;
output [5:0] ALUFunout;
reg [5:0] ALUFunout;
output Signout;
reg Signout;
output MemWrout;
reg MemWrout;
output MemRdout;
reg MemRdout;
output [1:0] MemtoRegout;
reg [1:0] MemtoRegout;
always @(*)
begin
if(~flushIDEX)
begin
RegDstout <= RegDstin;
RegWrout <= RegWrin;
ALUSrc1out <= ALUSrc1in;
ALUSrc2out <= ALUSrc2in;
ALUFunout <= ALUFunin;
Signout <= Signin;
MemWrout <= MemWrin;
MemRdout <= MemRdin;
MemtoRegout <= MemtoRegin;
end
else
begin
RegDstout <= 2'b00;
RegWrout <= 0;
ALUSrc1out <= 0;
ALUSrc2out <= 0;
ALUFunout <= 6'h0;
Signout <= 0;
MemWrout <= 0;
MemRdout <= 0;
MemtoRegout <= 2'b00;
end
end
endmodule
|
//======================================================================
//
// siphash_core.v
// --------------
// Verilog 2001 implementation of SipHash.
// This is the internal core with wide interface.
// The core implements the round function as a one cycle, full parallel
// operation. This means chained 64 bit adders.
//
// Note that the module name is siphash_core to allow usage of the
// same TB and wrapper as the default and tiny versions of the core.
//
//
// Copyright (c) 2012, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module siphash_core(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire initalize,
input wire compress,
input wire finalize,
input wire long,
input wire [3 : 0] compression_rounds,
input wire [3 : 0] final_rounds,
input wire [127 : 0] key,
input wire [63 : 0] mi,
output wire ready,
output wire [127 : 0] siphash_word,
output wire siphash_word_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam DP_INIT = 3'h0;
localparam DP_COMP_START = 3'h1;
localparam DP_COMP_END = 3'h2;
localparam DP_FINAL0_START = 3'h3;
localparam DP_FINAL1_START = 3'h4;
localparam DP_SIPROUND = 3'h5;
localparam CTRL_IDLE = 3'h0;
localparam CTRL_COMP_LOOP = 3'h1;
localparam CTRL_COMP_END = 3'h2;
localparam CTRL_FINAL0_LOOP = 3'h3;
localparam CTRL_FINAL0_END = 3'h4;
localparam CTRL_FINAL1_START = 3'h5;
localparam CTRL_FINAL1_LOOP = 3'h6;
localparam CTRL_FINAL1_END = 3'h7;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [63 : 0] v0_reg;
reg [63 : 0] v0_new;
reg v0_we;
reg [63 : 0] v1_reg;
reg [63 : 0] v1_new;
reg v1_we;
reg [63 : 0] v2_reg;
reg [63 : 0] v2_new;
reg v2_we;
reg [63 : 0] v3_reg;
reg [63 : 0] v3_new;
reg v3_we;
reg [63 : 0] mi_reg;
reg mi_we;
reg [3 : 0] loop_ctr_reg;
reg [3 : 0] loop_ctr_new;
reg loop_ctr_we;
reg loop_ctr_inc;
reg loop_ctr_rst;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [63 : 0] siphash_word0_reg;
reg [63 : 0] siphash_word1_reg;
reg [63 : 0] siphash_word_new;
reg siphash_word0_we;
reg siphash_word1_we;
reg siphash_valid_reg;
reg siphash_valid_new;
reg siphash_valid_we;
reg [2 : 0] siphash_ctrl_reg;
reg [2 : 0] siphash_ctrl_new;
reg siphash_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg dp_update;
reg [2 : 0] dp_mode;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_reg;
assign siphash_word = {siphash_word1_reg, siphash_word0_reg};
assign siphash_word_valid = siphash_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with
// synchronous active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin
if (!reset_n)
begin
// Reset all registers to defined values.
v0_reg <= 64'h0;
v1_reg <= 64'h0;
v2_reg <= 64'h0;
v3_reg <= 64'h0;
siphash_word0_reg <= 64'h0;
siphash_word1_reg <= 64'h0;
mi_reg <= 64'h0;
ready_reg <= 1;
siphash_valid_reg <= 0;
loop_ctr_reg <= 4'h0;
siphash_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (siphash_word0_we)
siphash_word0_reg <= siphash_word_new;
if (siphash_word1_we)
siphash_word1_reg <= siphash_word_new;
if (v0_we)
v0_reg <= v0_new;
if (v1_we)
v1_reg <= v1_new;
if (v2_we)
v2_reg <= v2_new;
if (v3_we)
v3_reg <= v3_new;
if (mi_we)
mi_reg <= mi;
if (ready_we)
ready_reg <= ready_new;
if (siphash_valid_we)
siphash_valid_reg <= siphash_valid_new;
if (loop_ctr_we)
loop_ctr_reg <= loop_ctr_new;
if (siphash_ctrl_we)
siphash_ctrl_reg <= siphash_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// datapath_update
// update_logic for the internal datapath with the internal state
// stored in the v0, v1, v2 and v3 registers.
//
// The datapath contains two parallel 64-bit adders with
// operand MUXes to support reuse during processing.
//----------------------------------------------------------------
always @*
begin : datapath_update
reg [63 : 0] add_0_res;
reg [63 : 0] add_1_res;
reg [63 : 0] add_2_res;
reg [63 : 0] add_3_res;
reg [63 : 0] v0_tmp;
reg [63 : 0] v1_tmp;
reg [63 : 0] v2_tmp;
reg [63 : 0] v3_tmp;
add_0_res = 64'h0;
add_1_res = 64'h0;
add_2_res = 64'h0;
add_3_res = 64'h0;
v0_tmp = 64'h0;
v1_tmp = 64'h0;
v2_tmp = 64'h0;
v3_tmp = 64'h0;
v0_new = 64'h0;
v0_we = 0;
v1_new = 64'h0;
v1_we = 0;
v2_new = 64'h0;
v2_we = 0;
v3_new = 64'h0;
v3_we = 0;
siphash_word_new = v0_reg ^ v1_reg ^ v2_reg ^ v3_reg;
if (dp_update)
begin
case (dp_mode)
DP_INIT:
begin
v0_new = key[063 : 000] ^ 64'h736f6d6570736575;
v2_new = key[063 : 000] ^ 64'h6c7967656e657261;
v3_new = key[127 : 064] ^ 64'h7465646279746573;
v0_we = 1;
v1_we = 1;
v2_we = 1;
v3_we = 1;
if (long)
v1_new = key[127 : 064] ^ 64'h646f72616e646f6d ^ 64'hee;
else
v1_new = key[127 : 064] ^ 64'h646f72616e646f6d;
end
DP_COMP_START:
begin
v3_new = v3_reg ^ mi;
v3_we = 1;
end
DP_COMP_END:
begin
v0_new = v0_reg ^ mi_reg;
v0_we = 1;
end
DP_FINAL0_START:
begin
v2_we = 1;
if (long)
v2_new = v2_reg ^ 64'hee;
else
v2_new = v2_reg ^ 64'hff;
end
DP_FINAL1_START:
begin
v1_new = v1_reg ^ 64'hdd;
v1_we = 1;
end
DP_SIPROUND:
begin
add_0_res = v0_reg + v1_reg;
add_1_res = v2_reg + v3_reg;
v0_tmp = {add_0_res[31:0], add_0_res[63:32]};
v1_tmp = {v1_reg[50:0], v1_reg[63:51]} ^ add_0_res;
v2_tmp = add_1_res;
v3_tmp = {v3_reg[47:0], v3_reg[63:48]} ^ add_1_res;
add_2_res = v1_tmp + v2_tmp;
add_3_res = v0_tmp + v3_tmp;
v0_new = add_3_res;
v0_we = 1;
v1_new = {v1_tmp[46:0], v1_tmp[63:47]} ^ add_2_res;
v1_we = 1;
v2_new = {add_2_res[31:0], add_2_res[63:32]};
v2_we = 1;
v3_new = {v3_tmp[42:0], v3_tmp[63:43]} ^ add_3_res;
v3_we = 1;
end
default:
begin
end
endcase // case (dp_state_reg)
end // if (dp_update)
end // block: datapath_update
//----------------------------------------------------------------
// loop_ctr
// Update logic for the loop counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : loop_ctr
loop_ctr_new = 0;
loop_ctr_we = 0;
if (loop_ctr_rst)
loop_ctr_we = 1;
if (loop_ctr_inc)
begin
loop_ctr_new = loop_ctr_reg + 4'h1;
loop_ctr_we = 1;
end
end // loop_ctr
//----------------------------------------------------------------
// siphash_ctrl_fsm
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : siphash_ctrl_fsm
loop_ctr_rst = 0;
loop_ctr_inc = 0;
dp_update = 0;
dp_mode = DP_INIT;
mi_we = 0;
ready_new = 0;
ready_we = 0;
siphash_word0_we = 0;
siphash_word1_we = 0;
siphash_valid_new = 0;
siphash_valid_we = 0;
siphash_ctrl_new = CTRL_IDLE;
siphash_ctrl_we = 0;
case (siphash_ctrl_reg)
CTRL_IDLE:
begin
if (initalize)
begin
dp_update = 1;
dp_mode = DP_INIT;
siphash_valid_new = 0;
siphash_valid_we = 1;
end
else if (compress)
begin
mi_we = 1;
loop_ctr_rst = 1;
ready_new = 0;
ready_we = 1;
dp_update = 1;
dp_mode = DP_COMP_START;
siphash_ctrl_new = CTRL_COMP_LOOP;
siphash_ctrl_we = 1;
end
else if (finalize)
begin
loop_ctr_rst = 1;
ready_new = 0;
ready_we = 1;
dp_update = 1;
dp_mode = DP_FINAL0_START;
siphash_ctrl_new = CTRL_FINAL0_LOOP;
siphash_ctrl_we = 1;
end
end
CTRL_COMP_LOOP:
begin
loop_ctr_inc = 1;
dp_update = 1;
dp_mode = DP_SIPROUND;
if (loop_ctr_reg == (compression_rounds - 1))
begin
siphash_ctrl_new = CTRL_COMP_END;
siphash_ctrl_we = 1;
end
end
CTRL_COMP_END:
begin
ready_new = 1;
ready_we = 1;
dp_update = 1;
dp_mode = DP_COMP_END;
siphash_ctrl_new = CTRL_IDLE;
siphash_ctrl_we = 1;
end
CTRL_FINAL0_LOOP:
begin
loop_ctr_inc = 1;
dp_update = 1;
dp_mode = DP_SIPROUND;
if (loop_ctr_reg == (final_rounds - 1))
begin
if (long)
begin
siphash_ctrl_new = CTRL_FINAL1_START;
siphash_ctrl_we = 1;
end
else
begin
siphash_ctrl_new = CTRL_FINAL0_END;
siphash_ctrl_we = 1;
end
end
end
CTRL_FINAL0_END:
begin
ready_new = 1;
ready_we = 1;
siphash_word0_we = 1;
siphash_valid_new = 1;
siphash_valid_we = 1;
siphash_ctrl_new = CTRL_IDLE;
siphash_ctrl_we = 1;
end
CTRL_FINAL1_START:
begin
siphash_word0_we = 1;
loop_ctr_rst = 1;
dp_update = 1;
dp_mode = DP_FINAL1_START;
siphash_ctrl_new = CTRL_FINAL1_LOOP;
siphash_ctrl_we = 1;
end
CTRL_FINAL1_LOOP:
begin
loop_ctr_inc = 1;
dp_update = 1;
dp_mode = DP_SIPROUND;
if (loop_ctr_reg == (final_rounds - 1))
begin
siphash_ctrl_new = CTRL_FINAL1_END;
siphash_ctrl_we = 1;
end
end
CTRL_FINAL1_END:
begin
ready_new = 1;
ready_we = 1;
siphash_word1_we = 1;
siphash_valid_new = 1;
siphash_valid_we = 1;
siphash_ctrl_new = CTRL_IDLE;
siphash_ctrl_we = 1;
end
default:
begin
end
endcase // case (siphash_ctrl_reg)
end // siphash_ctrl_fsm
endmodule // siphash_core
//======================================================================
// EOF siphash_core.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXTP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFXTP_BLACKBOX_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfxtp (
CLK,
D ,
Q ,
SCD,
SCE
);
input CLK;
input D ;
output Q ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXTP_BLACKBOX_V
|
/* Verilog for cell 'PPGen_wordslice{sch}' from library 'wordlib8' */
/* Created on Mon Nov 04, 2013 20:40:31 */
/* Last revised on Wed Nov 06, 2013 18:23:07 */
/* Written on Wed Nov 06, 2013 18:23:30 by Electric VLSI Design System, version 8.06 */
module muddlib07__and2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire net_1, net_2;
tranif1 nmos_0(net_1, net_2, b);
tranif1 nmos_1(gnd, net_1, a);
tranif1 nmos_2(gnd, y, net_2);
tranif0 pmos_0(net_2, vdd, b);
tranif0 pmos_1(net_2, vdd, a);
tranif0 pmos_2(y, vdd, net_2);
endmodule /* muddlib07__and2_1x */
module muddlib07__xor2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire ab, bb, net_3, net_4, net_7, net_8;
tranif1 nmos_0(gnd, net_3, a);
tranif1 nmos_1(gnd, net_4, ab);
tranif1 nmos_2(net_3, y, b);
tranif1 nmos_3(net_4, y, bb);
tranif1 nmos_4(gnd, bb, b);
tranif1 nmos_5(gnd, ab, a);
tranif0 pmos_0(y, net_7, b);
tranif0 pmos_1(net_7, vdd, ab);
tranif0 pmos_2(y, net_8, bb);
tranif0 pmos_3(net_8, vdd, a);
tranif0 pmos_4(bb, vdd, b);
tranif0 pmos_5(ab, vdd, a);
endmodule /* muddlib07__xor2_1x */
module wordlib8__HalfAdder(A, Cin, Cout, Sum);
input A;
input Cin;
output Cout;
output Sum;
supply1 vdd;
supply0 gnd;
muddlib07__and2_1x and2_1x_0(.a(A), .b(Cin), .y(Cout));
muddlib07__xor2_1x xor2_1x_0(.a(A), .b(Cin), .y(Sum));
endmodule /* wordlib8__HalfAdder */
module muddlib07__inv_1x(a, y);
input a;
output y;
supply1 vdd;
supply0 gnd;
tranif1 nmos_0(gnd, y, a);
tranif0 pmos_0(y, vdd, a);
endmodule /* muddlib07__inv_1x */
module muddlib07__nand2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire net_5;
tranif1 nmos_0(net_5, y, b);
tranif1 nmos_1(gnd, net_5, a);
tranif0 pmos_0(y, vdd, b);
tranif0 pmos_1(y, vdd, a);
endmodule /* muddlib07__nand2_1x */
module muddlib07__nor2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire net_9;
tranif1 nmos_0(gnd, y, a);
tranif1 nmos_1(gnd, y, b);
tranif0 pmos_0(y, net_9, b);
tranif0 pmos_1(net_9, vdd, a);
endmodule /* muddlib07__nor2_1x */
module wordlib8__NAND8_reducer(inY, reduced_AND);
output [7:0] inY;
output reduced_AND;
supply1 vdd;
supply0 gnd;
wire net_0, net_10, net_14, net_2, net_4, net_6, net_8;
muddlib07__inv_1x inv_1x_0(.a(inY[7]), .y(net_14));
muddlib07__nand2_1x nand2_1x_0(.a(net_0), .b(net_2), .y(net_8));
muddlib07__nand2_1x nand2_1x_1(.a(net_4), .b(net_6), .y(net_10));
muddlib07__nor2_1x nor2_1x_0(.a(net_14), .b(inY[6]), .y(net_0));
muddlib07__nor2_1x nor2_1x_1(.a(inY[5]), .b(inY[4]), .y(net_2));
muddlib07__nor2_1x nor2_1x_2(.a(inY[3]), .b(inY[2]), .y(net_4));
muddlib07__nor2_1x nor2_1x_3(.a(inY[1]), .b(inY[0]), .y(net_6));
muddlib07__nor2_1x nor2_1x_8(.a(net_8), .b(net_10), .y(reduced_AND));
endmodule /* wordlib8__NAND8_reducer */
module wordlib8__PPGen_1bit(Double, Negate, Single, Yi, Yi_m1, PPi);
input Double;
input Negate;
input Single;
input Yi;
input Yi_m1;
output PPi;
supply1 vdd;
supply0 gnd;
wire net_0, net_2, net_4;
muddlib07__nand2_1x nand2_1x_0(.a(Single), .b(Yi), .y(net_0));
muddlib07__nand2_1x nand2_1x_1(.a(net_0), .b(net_2), .y(net_4));
muddlib07__nand2_1x nand2_1x_2(.a(Double), .b(Yi_m1), .y(net_2));
muddlib07__xor2_1x xor2_1x_0(.a(net_4), .b(Negate), .y(PPi));
endmodule /* wordlib8__PPGen_1bit */
module muddlib07__nand3_1x(a, b, c, y);
input a;
input b;
input c;
output y;
supply1 vdd;
supply0 gnd;
wire net_15, net_4;
tranif1 nmos_0(net_15, net_4, b);
tranif1 nmos_1(net_4, y, c);
tranif1 nmos_2(gnd, net_15, a);
tranif0 pmos_0(y, vdd, c);
tranif0 pmos_1(y, vdd, b);
tranif0 pmos_2(y, vdd, a);
endmodule /* muddlib07__nand3_1x */
module wordlib8__PPGen_9bits(Double, Negate, Single, Y, PP, Sign);
input Double;
input Negate;
input Single;
input [7:0] Y;
output [8:0] PP;
output Sign;
supply1 vdd;
supply0 gnd;
wire HalfAdde_8_Cout, net_111, net_113, net_168, net_177, net_51, net_52;
wire net_53, net_54, net_55, net_56, net_57, net_58, net_59, net_64, net_69;
wire net_74, net_79, net_84, net_92;
wordlib8__HalfAdder HalfAdde_0(.A(net_58), .Cin(net_59), .Cout(net_113),
.Sum(PP[7]));
wordlib8__HalfAdder HalfAdde_1(.A(net_57), .Cin(net_64), .Cout(net_59),
.Sum(PP[6]));
wordlib8__HalfAdder HalfAdde_2(.A(net_56), .Cin(net_69), .Cout(net_64),
.Sum(PP[5]));
wordlib8__HalfAdder HalfAdde_3(.A(net_55), .Cin(net_74), .Cout(net_69),
.Sum(PP[4]));
wordlib8__HalfAdder HalfAdde_4(.A(net_54), .Cin(net_79), .Cout(net_74),
.Sum(PP[3]));
wordlib8__HalfAdder HalfAdde_5(.A(net_53), .Cin(net_84), .Cout(net_79),
.Sum(PP[2]));
wordlib8__HalfAdder HalfAdde_6(.A(net_52), .Cin(net_92), .Cout(net_84),
.Sum(PP[1]));
wordlib8__HalfAdder HalfAdde_7(.A(net_51), .Cin(Negate), .Cout(net_92),
.Sum(PP[0]));
wordlib8__HalfAdder HalfAdde_8(.A(net_111), .Cin(net_113),
.Cout(HalfAdde_8_Cout), .Sum(PP[8]));
wordlib8__NAND8_reducer NAND8_re_0(.inY(Y[7:0]), .reduced_AND(net_177));
wordlib8__PPGen_1bit PPGen_1b_0(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[7]), .Yi_m1(Y[6]), .PPi(net_58));
wordlib8__PPGen_1bit PPGen_1b_1(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[6]), .Yi_m1(Y[5]), .PPi(net_57));
wordlib8__PPGen_1bit PPGen_1b_2(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[5]), .Yi_m1(Y[4]), .PPi(net_56));
wordlib8__PPGen_1bit PPGen_1b_3(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[4]), .Yi_m1(Y[3]), .PPi(net_55));
wordlib8__PPGen_1bit PPGen_1b_4(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[3]), .Yi_m1(Y[2]), .PPi(net_54));
wordlib8__PPGen_1bit PPGen_1b_5(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[2]), .Yi_m1(Y[1]), .PPi(net_53));
wordlib8__PPGen_1bit PPGen_1b_6(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[1]), .Yi_m1(Y[0]), .PPi(net_52));
wordlib8__PPGen_1bit PPGen_1b_7(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[0]), .Yi_m1(gnd), .PPi(net_51));
wordlib8__PPGen_1bit PPGen_1b_8(.Double(Double), .Negate(Negate),
.Single(Single), .Yi(Y[7]), .Yi_m1(Y[7]), .PPi(net_111));
muddlib07__and2_1x and2_1x_0(.a(net_168), .b(PP[8]), .y(Sign));
muddlib07__nand3_1x nand3_1x_0(.a(net_177), .b(Negate), .c(Double),
.y(net_168));
endmodule /* wordlib8__PPGen_9bits */
module PPGen_wordslice(Double, Negate, Single, Y, PP0, PP1, PP2, PP3, Sign0,
Sign1, Sign2, Sign3);
input [3:0] Double;
input [3:0] Negate;
input [3:0] Single;
input [7:0] Y;
output [8:0] PP0;
output [8:0] PP1;
output [8:0] PP2;
output [8:0] PP3;
output Sign0;
output Sign1;
output Sign2;
output Sign3;
supply1 vdd;
supply0 gnd;
wordlib8__PPGen_9bits PPGen_9b_0(.Double(Double[3]), .Negate(Negate[3]),
.Single(Single[3]), .Y(Y[7:0]), .PP(PP3[8:0]), .Sign(Sign3));
wordlib8__PPGen_9bits PPGen_9b_1(.Double(Double[2]), .Negate(Negate[2]),
.Single(Single[2]), .Y(Y[7:0]), .PP(PP2[8:0]), .Sign(Sign2));
wordlib8__PPGen_9bits PPGen_9b_2(.Double(Double[1]), .Negate(Negate[1]),
.Single(Single[1]), .Y(Y[7:0]), .PP(PP1[8:0]), .Sign(Sign1));
wordlib8__PPGen_9bits PPGen_9b_3(.Double(Double[0]), .Negate(Negate[0]),
.Single(Single[0]), .Y(Y[7:0]), .PP(PP0[8:0]), .Sign(Sign0));
endmodule /* PPGen_wordslice */
|
// USED ONLY TO SELECT VC BLOCKED STATUS
// OPTIMISE FOR XY ROUTING
/* autovdoc@
*
* component@ unary_select_pair
* what@ A sort of mux!
* authors@ Robert Mullins
* date@ 5.3.04
* revised@ 5.3.04
* description@
*
* Takes two unary (one-hot) encoded select signals and selects one bit of the input.
*
* Implements the following:
*
* {\tt selectedbit=datain[binary(sela)*WB+binary(selb)]}
*
* pin@ sel_a, WA, in, select signal A (unary encoded)
* pin@ sel_b, WB, in, select signal B (unary encoded)
* pin@ data_in, WA*WB, in, input data
* pin@ selected_bit, 1, out, selected data bit (see above)
*
* param@ WA, >1, width of select signal A
* param@ WB, >1, width of select signal B
*
* autovdoc@
*/
module unary_select_pair (sel_a, sel_b, data_in, selected_bit);
parameter input_port = 0; // from 'input_port' to 'sel_a' output port
parameter WA = 5; //trunk number
parameter WB = 2; //max. number of links per trunk
parameter integer links[WA][2] = '{'{2,2}, '{2,2}, '{2,2}, '{2,2}, '{2,2} };
input [WA-1:0] sel_a;
input [WB-1:0] sel_b;
input [WA*WB-1:0] data_in;
output selected_bit;
integer i,j;
logic [WA*WB-1:0] selected;
always_comb begin
selected = '0;
for (i=0; i<WA; i=i+1)
for (j=0; j<links[i][OUT]; j=j+1)
selected[i*WB+j] = (LAG_route_valid_turn(input_port, i)) ?
data_in[i*WB+j] & sel_a[i] & sel_b[j] : 1'b0;
end //always_comb
assign selected_bit=|selected;
endmodule // unary_select_pair
|
// ======================================================================
// DES encryption/decryption testbench
// tests according to NIST 800-17 special publication
// Copyright (C) 2012 Torsten Meissner
//-----------------------------------------------------------------------
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
// ======================================================================
`timescale 1ns/1ps
module tb_cbctdes;
// set dumpfile
initial begin
$dumpfile ("tb_cbctdes.vcd");
$dumpvars (0, tb_cbctdes);
end
reg reset;
reg clk = 0;
reg start;
reg mode;
reg [0:63] key1;
reg [0:63] key2;
reg [0:63] key3;
reg [0:63] iv;
reg [0:63] datain;
reg validin;
integer index;
integer outdex;
integer errors;
wire [0:63] dataout;
wire validout;
wire ready;
reg [0:63] test_data [0:18];
reg [0:63] test_answers [0:18];
// read in test data files
initial begin
$readmemh("test_data.txt", test_data);
end
// setup simulation
initial begin
reset = 1;
#1 reset = 0;
#100 reset = 1;
end
// generate clock with 50 mhz
always #10 clk = !clk;
// init the register values
initial
forever @(negedge reset) begin
//disable stimuli;
disable checker;
mode <= 0;
validin <= 0;
key1 <= 0;
key2 <= 0;
key3 <= 0;
datain <= 0;
errors = 0;
end
// stimuli generator process
initial
forever @(negedge reset) begin
index = 0;
wait (reset);
while (index < 19) begin
@(posedge clk)
if (ready) begin
mode <= 0;
validin <= 1;
datain <= test_data[index];
key1 <= 64'h1111111111111111;
key2 <= 64'h5555555555555555;
key3 <= 64'h9999999999999999;
index = index + 1;
@(posedge clk)
validin <= 0;
end
end
index = 0;
while (index < 19) begin
@(posedge clk)
if (ready) begin
mode <= 1;
validin <= 1;
datain <= test_answers[index];
key1 <= 64'h1111111111111111;
key2 <= 64'h5555555555555555;
key3 <= 64'h9999999999999999;
index = index + 1;
@(posedge clk)
validin <= 0;
end
end
@(posedge clk)
validin <= 0;
mode <= 0;
datain <= 0;
key1 <= 0;
key2 <= 0;
key3 <= 0;
end
// checker process
always begin : checker
wait (reset);
outdex = 0;
// encryption tests
outdex = 0;
while (outdex < 19) begin
@(posedge clk)
if (validout) begin
$display ("encrypt test pattern %d", outdex);
test_answers[outdex] = dataout;
outdex = outdex + 1;
end
end
// decryption tests
outdex = 0;
while (outdex < 19) begin
@(posedge clk)
if (validout) begin
$display ("decrypt test pattern %d", outdex);
// detected an error -> print error message
// increment error counter
if (dataout != test_data[outdex]) begin
$display ("error, output was %h - should have been %h", dataout, test_data[outdex]);
errors = errors + 1;
end
outdex = outdex + 1;
end
end
if (errors) begin
$display ("simulation finished, %0d errors detected :(", errors);
end else begin
$display ("simulation tests finished, no errors detected :)");
end
$display ("#############");
@(posedge clk)
$finish;
end
// dut
cbctdes i_cbctdes (
.reset_i(reset),
.clk_i(clk),
.start_i(start),
.mode_i(mode),
.key1_i(key1),
.key2_i(key2),
.key3_i(key3),
.iv_i(iv),
.data_i(datain),
.valid_i(validin),
.data_o(dataout),
.valid_o(validout),
.ready_o(ready)
);
endmodule
|
`include "project_defines.v"
module nh_lcd #(
parameter BUFFER_SIZE = 12
)(
input rst,
input clk,
output [31:0] debug,
//Control Signals
input i_enable,
input i_reset_display,
input i_data_command_mode,
input i_enable_tearing,
input i_cmd_parameter,
input i_cmd_write_stb,
input i_cmd_read_stb,
input [7:0] i_cmd_data,
output [7:0] o_cmd_data,
output o_cmd_finished,
input i_backlight_enable,
input i_write_override,
input i_chip_select,
input [31:0] i_num_pixels,
//FIFO Signals
output [1:0] o_fifo_rdy,
input [1:0] i_fifo_act,
input i_fifo_stb,
output [23:0] o_fifo_size,
input [31:0] i_fifo_data,
//Physical Signals
output o_backlight_enable,
output o_register_data_sel,
output o_write_n,
output o_read_n,
inout [7:0] io_data,
output o_cs_n,
output o_reset_n,
input i_tearing_effect,
output o_display_on
);
//Local Parameters
//Registers/Wires
wire [7:0] w_data_out;
wire [7:0] w_data_in;
wire w_cmd_write;
wire w_cmd_read;
wire [7:0] w_cmd_data;
wire w_cmd_cmd_mode;
wire w_cmd_data_out_en;
wire w_data_dir;
wire w_data_cmd_mode;
wire [7:0] w_data_data;
wire w_data_write;
wire w_data_read;
wire w_data_data_out_en;
//Submodules
nh_lcd_command lcd_commander (
.rst (rst ),
.clk (clk ),
// .debug (debug ),
.i_enable (i_enable ),
.i_cmd_parameter (i_cmd_parameter ),
.i_cmd_write_stb (i_cmd_write_stb ),
.i_cmd_read_stb (i_cmd_read_stb ),
.i_cmd_data (i_cmd_data ),
.o_cmd_data (o_cmd_data ),
//Control Signals
.o_data_out_en (w_cmd_data_out_en ),
.o_cmd_finished (o_cmd_finished ),
.o_cmd_mode (w_cmd_cmd_mode ),
.o_write (w_cmd_write ),
.o_read (w_cmd_read ),
.o_data_out (w_cmd_data ),
.i_data_in (w_data_in )
);
nh_lcd_data_writer #(
.BUFFER_SIZE (BUFFER_SIZE )
)lcd_data_writer(
.rst (rst ),
.clk (clk ),
.debug (debug ),
.i_enable (i_enable ),
.i_enable_tearing (i_enable_tearing ),
.i_num_pixels (i_num_pixels ),
.o_fifo_rdy (o_fifo_rdy ),
.i_fifo_act (i_fifo_act ),
.i_fifo_stb (i_fifo_stb ),
.o_fifo_size (o_fifo_size ),
.i_fifo_data (i_fifo_data ),
.o_cmd_mode (w_data_cmd_mode ),
.o_data_out (w_data_data ),
.i_data_in (w_data_in ),
.o_write (w_data_write ),
.o_read (w_data_read ),
.o_data_out_en (w_data_data_out_en ),
.i_tearing_effect (i_tearing_effect )
);
//Asynchronous Logic
assign o_backlight_enable = i_backlight_enable;
assign o_display_on = i_enable;
assign o_reset_n = ~i_reset_display;
assign o_cs_n = ~i_chip_select;
assign w_data_in = io_data;
//Select control between the Command controller and the Data Controller
assign o_register_data_sel = (i_data_command_mode) ? w_data_cmd_mode : w_cmd_cmd_mode;
assign o_write_n = (i_data_command_mode) ? ~w_data_write : ~w_cmd_write;
assign o_read_n = (i_data_command_mode) ? ~w_data_read : ~w_cmd_read;
assign w_data_dir = (i_data_command_mode) ? w_data_data_out_en : w_cmd_data_out_en;
assign io_data = (w_data_dir) ? (i_data_command_mode) ?
w_data_data : w_cmd_data :
8'hZZ;
/*
assign w_data_dir = (w_data_data_out_en) || (w_cmd_data_out_en); //this doesn't
assign io_data = (w_data_dir) ? w_data_out : 8'hZZ;
assign w_data_in = io_data;
assign w_data_out = (i_data_command_mode) ? w_data_data : w_cmd_data;
assign o_write_n = (i_write_override) ? 0 :
(i_data_command_mode) ? ~w_data_write : ~w_cmd_write;
assign o_read_n = (i_data_command_mode) ? ~w_data_read : ~w_cmd_read;
*/
//Synchronous Logic
endmodule
|
module Final_Lock_sm(clock, reset, program, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, correctLed, incorrectLed);
input clock;
input reset;
input program;
input b0, b1, b2, b3, b4, b5, b6, b7, b8, b9;
output reg correctLed, incorrectLed;
reg [4:0] state, next_state;
reg [9:0] num1, num2, num3, num4;
parameter S0 = 5'b00000,
C1 = 5'b00001,
C2 = 5'b00010,
C3 = 5'b00011,
CORRECT = 5'b00100,
X1 = 5'b00101,
X2 = 5'b00110,
X3 = 5'b00111,
INCORRECT = 5'b01000,
BC1 = 5'b01001,
BC2 = 5'b01010,
BC3 = 5'b01011,
BC4 = 5'b01100,
BX1 = 5'b01101,
BX2 = 5'b01110,
BX3 = 5'b01111,
BX4 = 5'b10000,
//Programming States
P1 = 5'b10001,
P2 = 5'b10010,
P3 = 5'b10011,
P4 = 5'b10100,
BP1 = 5'b10101,
BP2 = 5'b10110,
BP3 = 5'b10111,
BP4 = 5'b11000,
BP5 = 5'b11001;
//Set the default code
initial
begin
num1[9:0] = 10'b1000000000;
num2[9:0] = 10'b0100000000;
num3[9:0] = 10'b0010000000;
num4[9:0] = 10'b0001000000;
end
//Asyncronous Reset
always @ (posedge clock or posedge reset)
begin
if (reset == 1)
state <= S0;
else
state <= next_state;
end
//State Control Function
always @ (posedge clock)
begin
case(state)
S0:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
begin
if({b0,b1,b2,b3,b4,b5,b6,b7,b8,b9} == num1)
next_state <= BC1;
else
next_state <= BX1;
end
else
next_state <= S0;
end
C1:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
begin
if({b0,b1,b2,b3,b4,b5,b6,b7,b8,b9} == num2)
next_state <= BC2;
else
next_state <= BX2;
end
else
next_state <= C1;
end
C2:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
begin
if({b0,b1,b2,b3,b4,b5,b6,b7,b8,b9} == num3)
next_state <= BC3;
else
next_state <= BX3;
end
else
next_state <= C2;
end
C3:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
begin
if({b0,b1,b2,b3,b4,b5,b6,b7,b8,b9} == num4)
next_state <= BC4;
else
next_state <= BX4;
end
else
next_state <= C3;
end
CORRECT: //If the program program button is pressed, go to programming mode
begin
if (program == 1)
next_state <= BP1;
else
next_state <= CORRECT;
end
X1:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BX2;
else
next_state <= X1;
end
X2:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BX3;
else
next_state <= X2;
end
X3:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BX4;
else
next_state <= X3;
end
INCORRECT: ;
BC1:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BC1;
else
next_state <= C1;
end
BC2:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BC2;
else
next_state <= C2;
end
BC3:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BC3;
else
next_state <= C3;
end
BC4:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BC4;
else
next_state <= CORRECT;
end
BX1:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BX1;
else
next_state <= X1;
end
BX2:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BX2;
else
next_state <= X2;
end
BX3:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BX3;
else
next_state <= X3;
end
BX4:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BX4;
else
next_state <= INCORRECT;
end
P1:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
begin
num1 <= {b0,b1,b2,b3,b4,b5,b6,b7,b8,b9};
next_state <= BP2;
end
else
next_state <= P1;
end
P2:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
begin
num2 <= {b0,b1,b2,b3,b4,b5,b6,b7,b8,b9};
next_state <= BP3;
end
else
next_state <= P2;
end
P3:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
begin
num3 <= {b0,b1,b2,b3,b4,b5,b6,b7,b8,b9};
next_state <= BP4;
end
else
next_state <= P3;
end
P4:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
begin
num4 <= {b0,b1,b2,b3,b4,b5,b6,b7,b8,b9};
next_state <= BP5;
end
else
next_state <= P4;
end
BP1:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BP1;
else
next_state <= P1;
end
BP2:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BP2;
else
next_state <= P2;
end
BP3:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BP3;
else
next_state <= P3;
end
BP4:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BP4;
else
next_state <= P4;
end
BP5:
begin
if ((b0|b1|b2|b3|b4|b5|b6|b7|b8|b9) == 1)
next_state <= BP5;
else
next_state <= S0;
end
default: next_state <= S0;
endcase
end
//State Output Function
always @ (posedge clock)
begin
case(state)
CORRECT:
begin
correctLed <= 1;
incorrectLed <= 0;
end
INCORRECT:
begin
correctLed <= 0;
incorrectLed <= 1;
end
default:
begin
correctLed <= 0;
incorrectLed <= 0;
end
endcase
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iob_jbi_rptr_0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module iob_jbi_rptr_0 (/*AUTOARG*/
// Outputs
sig_buf,
// Inputs
sig
);
// this repeater has 164 bits
output [163:0] sig_buf;
input [163:0] sig;
assign sig_buf = sig;
endmodule
|
//wb_artemis_pcie_platform.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_artemis_pcie_platform
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/12/20
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
`include "project_defines.v"
`define CTRL_BIT_ENABLE 0
`define CTRL_BIT_SEND_CONTROL_BLOCK 1
`define CTRL_BIT_CANCEL_SEND_BLOCK 2
`define CTRL_BIT_ENABLE_LOCAL_READ 3
`define CTRL_BIT_ENABLE_EXT_RESET 4
`define CTRL_BIT_MANUAL_USER_RESET 5
`define STS_BIT_PCIE_RESET 0
`define STS_BIT_LINKUP 1
`define STS_BIT_RECEIVED_HOT_RESET 2
`define STS_BITS_PCIE_LINK_STATE 6:4
`define STS_BITS_PCIE_BUS_NUM 15:8
`define STS_BITS_PCIE_DEV_NUM 19:16
`define STS_BITS_PCIE_FUNC_NUM 22:20
`define STS_BITS_LOCAL_MEM_IDLE 24
`define STS_BIT_GTP_PLL_LOCK_DETECT 25
`define STS_BIT_PLL_LOCK_DETECT 26
`define STS_BIT_GTP_RESET_DONE 27
`define STS_BIT_RX_ELEC_IDLE 28
`define STS_BIT_CFG_TO_TURNOFF 29
`define STS_BIT_PCIE_EXT_RESET 30
`define DBG_CORRECTABLE 0
`define DBG_FATAL 1
`define DBG_NON_FATAL 2
`define DBG_UNSUPPORTED 3
`define DBG_BAD_DLLP_STATUS 0
`define DBG_BAD_TLP_LCRC 1
`define DBG_BAD_TLP_SEQ_NUM 2
`define DBG_BAD_TLP_STATUS 3
`define DBG_DL_PROTOCOL_STATUS 4
`define DBG_FC_PROTOCOL_ERR_STATUS 5
`define DBG_MLFMD_LENGTH 6
`define DBG_MLFMD_MPS 7
`define DBG_MLFMD_TCVC 8
`define DBG_MLFMD_TLP_STATUS 9
`define DBG_MLFMD_UNREC_TYPE 10
`define DBG_POISTLPSTATUS 11
`define DBG_RCVR_OVERFLOW_STATUS 12
`define DBG_RPLY_ROLLOVER_STATUS 13
`define DBG_RPLY_TIMEOUT_STATUS 14
`define DBG_UR_NO_BAR_HIT 15
`define DBG_UR_POIS_CFG_WR 16
`define DBG_UR_STATUS 17
`define DBG_UR_UNSUP_MSG 18
`define LOCAL_BUFFER_OFFSET 24'h000100
module wb_artemis_pcie_platform #(
parameter CONTROL_FIFO_DEPTH = 7,
parameter DATA_FIFO_DEPTH = 9
) (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int,
//PCIE Physical Signals
input i_clk_100mhz_gtp_p,
input i_clk_100mhz_gtp_n,
output o_pcie_phy_tx_p,
output o_pcie_phy_tx_n,
input i_pcie_phy_rx_p,
input i_pcie_phy_rx_n,
input i_pcie_reset_n,
output o_pcie_wake_n,
output o_62p5_clk,
output [31:0] o_debug_data
);
//Local Parameters
localparam CONTROL_BUFFER_SIZE = 2 ** CONTROL_FIFO_DEPTH;
localparam CONTROL = 0;
localparam STATUS = 1;
localparam NUM_BLOCK_READ = 2;
localparam LOCAL_BUFFER_SIZE = 3;
localparam PCIE_CLOCK_CNT = 4;
localparam TEST_CLOCK = 5;
localparam TX_DIFF_CTRL = 6;
localparam RX_EQUALIZER_CTRL = 7;
localparam LTSSM_STATE = 8;
localparam TX_PRE_EMPH = 9;
localparam DBG_DATA = 9;
localparam CONFIG_COMMAND = 10;
localparam CONFIG_STATUS = 11;
localparam CONFIG_DCOMMAND = 12;
localparam CONFIG_DSTATUS = 13;
localparam CONFIG_LCOMMAND = 14;
localparam CONFIG_LSTATUS = 15;
localparam DBG_FLAGS = 16;
//Local Registers/Wires
wire [31:0] status;
reg r_enable_pcie;
//reg r_enable_ext_reset;
//reg r_manual_pcie_reset;
reg [31:0] r_clock_1_sec;
reg [31:0] r_clock_count;
reg [31:0] r_host_clock_count;
reg r_1sec_stb_100mhz;
wire w_1sec_stb_65mhz;
// Transaction (TRN) Interface
wire user_lnk_up;
// Flow Control
wire [2:0] fc_sel;
wire [7:0] fc_nph;
wire [11:0] fc_npd;
wire [7:0] fc_ph;
wire [11:0] fc_pd;
wire [7:0] fc_cplh;
wire [11:0] fc_cpld;
// Host (CFG) Interface
wire [31:0] cfg_do;
wire cfg_rd_wr_done;
wire [9:0] cfg_dwaddr;
wire cfg_rd_en;
// Configuration: Error
wire cfg_err_ur;
wire cfg_err_cor;
wire cfg_err_ecrc;
wire cfg_err_cpl_timeout;
wire cfg_err_cpl_abort;
wire cfg_err_posted;
wire cfg_err_locked;
wire [47:0] cfg_err_tlp_cpl_header;
wire cfg_err_cpl_rdy;
// Conifguration: Interrupt
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_do;
wire [7:0] cfg_interrupt_di;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
// Configuration: Power Management
reg cfg_turnoff_ok;
reg trn_pending;
wire cfg_to_turnoff;
wire cfg_pm_wake;
// Configuration: System/Status
wire [2:0] cfg_pcie_link_state;
reg r_cfg_trn_pending;
wire [7:0] cfg_bus_number;
wire [4:0] cfg_device_number;
wire [2:0] cfg_function_number;
wire [15:0] cfg_status;
wire [15:0] cfg_command;
wire [15:0] cfg_dstatus;
wire [15:0] cfg_dcommand;
wire [15:0] cfg_lstatus;
wire [15:0] cfg_lcommand;
// System Interface
wire pcie_reset;
wire pcie_clk;
wire received_hot_reset;
reg r_ppfifo_2_mem_en;
reg r_mem_2_ppfifo_stb;
reg r_cancel_write_stb;
wire [31:0] w_num_reads;
wire w_idle;
wire pll_lock_detect;
wire rx_elec_idle;
wire gtp_pll_lock_detect;
wire gtp_reset_done;
//User Memory Interface
reg r_lcl_mem_we;
wire [CONTROL_FIFO_DEPTH -1: 0] w_lcl_mem_addr;
reg [31:0] r_lcl_mem_din;
wire [31:0] w_lcl_mem_dout;
wire w_lcl_mem_valid;
wire w_lcl_mem_en;
wire w_cmd_in_rd_stb;
wire w_cmd_in_rd_ready;
wire w_cmd_in_rd_activate;
wire [23:0] w_cmd_in_rd_size;
wire [31:0] w_cmd_in_rd_data;
wire [1:0] w_cmd_out_wr_ready;
wire [1:0] w_cmd_out_wr_activate;
wire [23:0] w_cmd_out_wr_size;
wire w_cmd_out_wr_stb;
wire [31:0] w_cmd_out_wr_data;
wire w_data_in_rd_stb;
wire w_data_in_rd_ready;
wire w_data_in_rd_activate;
wire [23:0] w_data_in_rd_size;
wire [31:0] w_data_in_rd_data;
wire [1:0] w_data_out_wr_ready;
wire [1:0] w_data_out_wr_activate;
wire [23:0] w_data_out_wr_size;
wire w_data_out_wr_stb;
wire [31:0] w_data_out_wr_data;
reg [1:0] r_rx_equalizer_ctrl;
reg [3:0] r_tx_diff_ctrl;
reg [2:0] r_tx_pre_emphasis;
wire [4:0] cfg_ltssm_state;
wire dbg_reg_detected_correctable;
wire dbg_reg_detected_fatal;
wire dbg_reg_detected_non_fatal;
wire dbg_reg_detected_unsupported;
reg dbg_correctable;
reg dbg_fatal;
reg dbg_non_fatal;
reg dbg_unsupported;
wire dbg_bad_dllp_status;
wire dbg_bad_tlp_lcrc;
wire dbg_bad_tlp_seq_num;
wire dbg_bad_tlp_status;
wire dbg_dl_protocol_status;
wire dbg_fc_protocol_err_status;
wire dbg_mlfrmd_length;
wire dbg_mlfrmd_mps;
wire dbg_mlfrmd_tcvc;
wire dbg_mlfrmd_tlp_status;
wire dbg_mlfrmd_unrec_type;
wire dbg_poistlpstatus;
wire dbg_rcvr_overflow_status;
wire dbg_rply_rollover_status;
wire dbg_rply_timeout_status;
wire dbg_ur_no_bar_hit;
wire dbg_ur_pois_cfg_wr;
wire dbg_ur_status;
wire dbg_ur_unsup_msg;
reg r_dbg_bad_dllp_status;
reg r_dbg_bad_tlp_lcrc;
reg r_dbg_bad_tlp_seq_num;
reg r_dbg_bad_tlp_status;
reg r_dbg_dl_protocol_status;
reg r_dbg_fc_protocol_err_status;
reg r_dbg_mlfrmd_length;
reg r_dbg_mlfrmd_mps;
reg r_dbg_mlfrmd_tcvc;
reg r_dbg_mlfrmd_tlp_status;
reg r_dbg_mlfrmd_unrec_type;
reg r_dbg_poistlpstatus;
reg r_dbg_rcvr_overflow_status;
reg r_dbg_rply_rollover_status;
reg r_dbg_rply_timeout_status;
reg r_dbg_ur_no_bar_hit;
reg r_dbg_ur_pois_cfg_wr;
reg r_dbg_ur_status;
reg r_dbg_ur_unsup_msg;
//Submodules
artemis_pcie_interface #(
.CONTROL_FIFO_DEPTH (CONTROL_FIFO_DEPTH ),
.DATA_FIFO_DEPTH (DATA_FIFO_DEPTH ),
.SERIAL_NUMBER (64'h000000000000C594 )
)api (
.clk (clk ),
.rst (rst || !r_enable_pcie || !i_pcie_reset_n ),
.gtp_clk_p (i_clk_100mhz_gtp_p ),
.gtp_clk_n (i_clk_100mhz_gtp_n ),
.pci_exp_txp (o_pcie_phy_tx_p ),
.pci_exp_txn (o_pcie_phy_tx_n ),
.pci_exp_rxp (i_pcie_phy_rx_p ),
.pci_exp_rxn (i_pcie_phy_rx_n ),
// Transaction (TRN) Interface
.user_lnk_up (user_lnk_up ),
.pcie_clk (pcie_clk ),
// Flow Control
.fc_sel (fc_sel ),
.fc_nph (fc_nph ),
.fc_npd (fc_npd ),
.fc_ph (fc_ph ),
.fc_pd (fc_pd ),
.fc_cplh (fc_cplh ),
.fc_cpld (fc_cpld ),
// Host (CFG) Interface
.cfg_do (cfg_do ),
.cfg_rd_wr_done (cfg_rd_wr_done ),
.cfg_dwaddr (cfg_dwaddr ),
.cfg_rd_en (cfg_rd_en ),
// Configuration: Error
.cfg_err_ur (cfg_err_ur ),
.cfg_err_cor (cfg_err_cor ),
.cfg_err_ecrc (cfg_err_ecrc ),
.cfg_err_cpl_timeout (cfg_err_cpl_timeout ),
.cfg_err_cpl_abort (cfg_err_cpl_abort ),
.cfg_err_posted (cfg_err_posted ),
.cfg_err_locked (cfg_err_locked ),
.cfg_err_tlp_cpl_header (cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy (cfg_err_cpl_rdy ),
// Conifguration: Interrupt
.cfg_interrupt (cfg_interrupt ),
.cfg_interrupt_rdy (cfg_interrupt_rdy ),
.cfg_interrupt_assert (cfg_interrupt_assert ),
.cfg_interrupt_do (cfg_interrupt_do ),
.cfg_interrupt_di (cfg_interrupt_di ),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable ),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
// Configuration: Power Management
.cfg_turnoff_ok (cfg_turnoff_ok ),
.cfg_to_turnoff (cfg_to_turnoff ),
.cfg_pm_wake (cfg_pm_wake ),
// Configuration: System/Status
.cfg_pcie_link_state (cfg_pcie_link_state ),
.cfg_trn_pending_stb (r_cfg_trn_pending ),
.cfg_bus_number (cfg_bus_number ),
.cfg_device_number (cfg_device_number ),
.cfg_function_number (cfg_function_number ),
.cfg_status (cfg_status ),
.cfg_command (cfg_command ),
.cfg_dstatus (cfg_dstatus ),
.cfg_dcommand (cfg_dcommand ),
.cfg_lstatus (cfg_lstatus ),
.cfg_lcommand (cfg_lcommand ),
// System Interface
.pcie_reset (pcie_reset ),
.received_hot_reset (received_hot_reset ),
.gtp_pll_lock_detect (gtp_pll_lock_detect ),
.gtp_reset_done (gtp_reset_done ),
.pll_lock_detect (pll_lock_detect ),
.rx_elec_idle (rx_elec_idle ),
.i_cmd_in_rd_stb (w_cmd_in_rd_stb ),
.o_cmd_in_rd_ready (w_cmd_in_rd_ready ),
.i_cmd_in_rd_activate (w_cmd_in_rd_activate ),
.o_cmd_in_rd_count (w_cmd_in_rd_size ),
.o_cmd_in_rd_data (w_cmd_in_rd_data ),
.o_cmd_out_wr_ready (w_cmd_out_wr_ready ),
.i_cmd_out_wr_activate (w_cmd_out_wr_activate ),
.o_cmd_out_wr_size (w_cmd_out_wr_size ),
.i_cmd_out_wr_stb (w_cmd_out_wr_stb ),
.i_cmd_out_wr_data (w_cmd_out_wr_data ),
.i_data_in_rd_stb (w_data_in_rd_stb ),
.o_data_in_rd_ready (w_data_in_rd_ready ),
.i_data_in_rd_activate (w_data_in_rd_activate ),
.o_data_in_rd_count (w_data_in_rd_size ),
.o_data_in_rd_data (w_data_in_rd_data ),
.o_data_out_wr_ready (w_data_out_wr_ready ),
.i_data_out_wr_activate (w_data_out_wr_activate ),
.o_data_out_wr_size (w_data_out_wr_size ),
.i_data_out_wr_stb (w_data_out_wr_stb ),
.i_data_out_wr_data (w_data_out_wr_data ),
.rx_equalizer_ctrl (r_rx_equalizer_ctrl ),
.tx_diff_ctrl (r_tx_diff_ctrl ),
.tx_pre_emphasis (r_tx_pre_emphasis ),
.cfg_ltssm_state (cfg_ltssm_state ),
.dbg_reg_detected_correctable (dbg_reg_detected_correctable ),
.dbg_reg_detected_fatal (dbg_reg_detected_fatal ),
.dbg_reg_detected_non_fatal (dbg_reg_detected_non_fatal ),
.dbg_reg_detected_unsupported (dbg_reg_detected_unsupported ),
.dbg_bad_dllp_status (dbg_bad_dllp_status ),
.dbg_bad_tlp_lcrc (dbg_bad_tlp_lcrc ),
.dbg_bad_tlp_seq_num (dbg_bad_tlp_seq_num ),
.dbg_bad_tlp_status (dbg_bad_tlp_status ),
.dbg_dl_protocol_status (dbg_dl_protocol_status ),
.dbg_fc_protocol_err_status (dbg_fc_protocol_err_status ),
.dbg_mlfrmd_length (dbg_mlfrmd_length ),
.dbg_mlfrmd_mps (dbg_mlfrmd_mps ),
.dbg_mlfrmd_tcvc (dbg_mlfrmd_tcvc ),
.dbg_mlfrmd_tlp_status (dbg_mlfrmd_tlp_status ),
.dbg_mlfrmd_unrec_type (dbg_mlfrmd_unrec_type ),
.dbg_poistlpstatus (dbg_poistlpstatus ),
.dbg_rcvr_overflow_status (dbg_rcvr_overflow_status ),
.dbg_rply_rollover_status (dbg_rply_rollover_status ),
.dbg_rply_timeout_status (dbg_rply_timeout_status ),
.dbg_ur_no_bar_hit (dbg_ur_no_bar_hit ),
.dbg_ur_pois_cfg_wr (dbg_ur_pois_cfg_wr ),
.dbg_ur_status (dbg_ur_status ),
.dbg_ur_unsup_msg (dbg_ur_unsup_msg )
);
adapter_dpb_ppfifo #(
.MEM_DEPTH (CONTROL_FIFO_DEPTH ),
.DATA_WIDTH (32 )
)dpb_bridge (
.clk (clk ),
.rst (rst ),
.i_ppfifo_2_mem_en (r_ppfifo_2_mem_en ),
.i_mem_2_ppfifo_stb (r_mem_2_ppfifo_stb ),
.i_cancel_write_stb (r_cancel_write_stb ),
.o_num_reads (w_num_reads ),
.o_idle (w_idle ),
.i_bram_we (r_lcl_mem_we ),
.i_bram_addr (w_lcl_mem_addr ),
.i_bram_din (r_lcl_mem_din ),
.o_bram_dout (w_lcl_mem_dout ),
.o_bram_valid (w_lcl_mem_valid ),
.ppfifo_clk (clk ),
.i_write_ready (w_cmd_out_wr_ready ),
.o_write_activate (w_cmd_out_wr_activate ),
.i_write_size (w_cmd_out_wr_size ),
.o_write_stb (w_cmd_out_wr_stb ),
.o_write_data (w_cmd_out_wr_data ),
.i_read_ready (w_cmd_in_rd_ready ),
.o_read_activate (w_cmd_in_rd_activate ),
.i_read_size (w_cmd_in_rd_size ),
.i_read_data (w_cmd_in_rd_data ),
.o_read_stb (w_cmd_in_rd_stb )
);
cross_clock_strobe clk_stb(
.rst (rst ),
.in_clk (clk ),
.in_stb (r_1sec_stb_100mhz ),
.out_clk (pcie_clk ),
.out_stb (w_1sec_stb_65mhz )
);
//Asynchronous Logic
assign fc_sel = 3'h0;
assign cfg_dwaddr = 10'h0;
assign cfg_rd_en = 1'b0;
assign cfg_err_ur = 0;
assign cfg_err_cor = 0;
assign cfg_err_ecrc = 0;
assign cfg_err_cpl_timeout = 0;
assign cfg_err_cpl_abort = 0;
assign cfg_err_posted = 0;
assign cfg_err_locked = 0;
assign cfg_err_tlp_cpl_header = 0;
assign cfg_interrupt = 0;
assign cfg_interrupt_assert = 0;
assign cfg_interrupt_di = 0;
//assign cfg_turnoff_ok = 0;
assign cfg_pm_wake = 0;
assign w_data_in_rd_activate = 0;
assign w_data_in_rd_stb = 0;
assign w_data_out_wr_activate = 0;
assign w_data_out_wr_stb = 0;
assign w_data_out_wr_data = 0;
assign o_pcie_wake_n = 1;
assign w_lcl_mem_en = ((i_wbs_adr >= `LOCAL_BUFFER_OFFSET) &&
(i_wbs_adr < (`LOCAL_BUFFER_OFFSET + CONTROL_BUFFER_SIZE)));
assign w_lcl_mem_addr = w_lcl_mem_en ? (i_wbs_adr - `LOCAL_BUFFER_OFFSET) : 0;
//assign !i_pcie_reset_n = r_enable_ext_reset ? !i_pcie_reset_n : r_manual_pcie_reset;
//assign !i_pcie_reset_n = i_pcie_reset_n;
assign o_62p5_clk = pcie_clk;
assign o_debug_data = { dbg_reg_detected_correctable,
dbg_reg_detected_fatal,
dbg_reg_detected_non_fatal,
dbg_reg_detected_unsupported,
dbg_bad_dllp_status,
dbg_bad_tlp_lcrc,
dbg_bad_tlp_seq_num,
dbg_bad_tlp_status,
dbg_dl_protocol_status,
dbg_fc_protocol_err_status,
dbg_mlfrmd_length,
dbg_mlfrmd_mps,
dbg_mlfrmd_tcvc,
dbg_mlfrmd_tlp_status,
dbg_mlfrmd_unrec_type,
dbg_poistlpstatus,
dbg_rcvr_overflow_status,
dbg_rply_rollover_status,
dbg_rply_timeout_status,
dbg_ur_no_bar_hit,
dbg_ur_pois_cfg_wr,
dbg_ur_status,
dbg_ur_unsup_msg,
pll_lock_detect,
pcie_reset,
user_lnk_up,
cfg_ltssm_state};
//Synchronous Logic
always @ (posedge pcie_clk) begin
if (!i_pcie_reset_n) begin
r_clock_1_sec <= 0;
r_clock_count <= 0;
dbg_correctable <= 0;
dbg_fatal <= 0;
dbg_non_fatal <= 0;
dbg_unsupported <= 0;
cfg_turnoff_ok <= 0;
trn_pending <= 0;
r_dbg_bad_dllp_status <= 0;
r_dbg_bad_tlp_lcrc <= 0;
r_dbg_bad_tlp_seq_num <= 0;
r_dbg_bad_tlp_status <= 0;
r_dbg_dl_protocol_status <= 0;
r_dbg_fc_protocol_err_status <= 0;
r_dbg_mlfrmd_length <= 0;
r_dbg_mlfrmd_mps <= 0;
r_dbg_mlfrmd_tcvc <= 0;
r_dbg_mlfrmd_tlp_status <= 0;
r_dbg_mlfrmd_unrec_type <= 0;
r_dbg_poistlpstatus <= 0;
r_dbg_rcvr_overflow_status <= 0;
r_dbg_rply_rollover_status <= 0;
r_dbg_rply_timeout_status <= 0;
r_dbg_ur_no_bar_hit <= 0;
r_dbg_ur_pois_cfg_wr <= 0;
r_dbg_ur_status <= 0;
r_dbg_ur_unsup_msg <= 0;
end
else begin
r_clock_count <= r_clock_count + 1;
if (w_1sec_stb_65mhz) begin
r_clock_1_sec <= r_clock_count;
r_clock_count <= 0;
end
if (dbg_reg_detected_correctable) begin
dbg_correctable <= 1;
end
if (dbg_reg_detected_fatal) begin
dbg_fatal <= 1;
end
if (dbg_reg_detected_non_fatal) begin
dbg_non_fatal <= 1;
end
if (dbg_reg_detected_unsupported) begin
dbg_unsupported <= 1;
end
//Power Controller
if (cfg_to_turnoff && !trn_pending) begin
cfg_turnoff_ok <= 1;
end
else begin
cfg_turnoff_ok <= 0;
end
if (dbg_bad_dllp_status) begin
r_dbg_bad_dllp_status <= 1;
end
if (dbg_bad_tlp_lcrc) begin
r_dbg_bad_tlp_lcrc <= 1;
end
if (dbg_bad_tlp_seq_num) begin
r_dbg_bad_tlp_seq_num <= 1;
end
if (dbg_bad_tlp_status) begin
r_dbg_bad_tlp_status <= 1;
end
if (dbg_dl_protocol_status) begin
r_dbg_dl_protocol_status <= 1;
end
if (dbg_fc_protocol_err_status) begin
r_dbg_fc_protocol_err_status <= 1;
end
if (dbg_mlfrmd_length) begin
r_dbg_mlfrmd_length <= 1;
end
if (dbg_mlfrmd_mps) begin
r_dbg_mlfrmd_mps <= 1;
end
if (dbg_mlfrmd_tcvc) begin
r_dbg_mlfrmd_tcvc <= 1;
end
if (dbg_mlfrmd_tlp_status) begin
r_dbg_mlfrmd_tlp_status <= 1;
end
if (dbg_mlfrmd_unrec_type) begin
r_dbg_mlfrmd_unrec_type <= 1;
end
if (dbg_poistlpstatus) begin
r_dbg_poistlpstatus <= 1;
end
if (dbg_rcvr_overflow_status) begin
r_dbg_rcvr_overflow_status <= 1;
end
if (dbg_rply_rollover_status) begin
r_dbg_rply_rollover_status <= 1;
end
if (dbg_rply_timeout_status) begin
r_dbg_rply_timeout_status <= 1;
end
if (dbg_ur_no_bar_hit) begin
r_dbg_ur_no_bar_hit <= 1;
end
if (dbg_ur_pois_cfg_wr) begin
r_dbg_ur_pois_cfg_wr <= 1;
end
if (dbg_ur_status) begin
r_dbg_ur_status <= 1;
end
if (dbg_ur_unsup_msg) begin
r_dbg_ur_unsup_msg <= 1;
end
end
end
always @ (posedge clk) begin
//Deassert Strobes
r_mem_2_ppfifo_stb <= 0;
r_cancel_write_stb <= 0;
r_lcl_mem_we <= 0;
r_1sec_stb_100mhz <= 0;
r_cfg_trn_pending <= 0;
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
r_ppfifo_2_mem_en <= 1;
r_enable_pcie <= 1;
//r_enable_ext_reset <= 1;
//r_manual_pcie_reset <= 0;
r_lcl_mem_din <= 0;
r_host_clock_count <= 0;
r_rx_equalizer_ctrl <= 2'b11;
r_tx_diff_ctrl <= 4'b1001;
r_tx_pre_emphasis <= 3'b00;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
CONTROL: begin
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
r_enable_pcie <= i_wbs_dat[`CTRL_BIT_ENABLE];
r_mem_2_ppfifo_stb <= i_wbs_dat[`CTRL_BIT_SEND_CONTROL_BLOCK];
r_cancel_write_stb <= i_wbs_dat[`CTRL_BIT_CANCEL_SEND_BLOCK];
r_ppfifo_2_mem_en <= i_wbs_dat[`CTRL_BIT_ENABLE_LOCAL_READ];
//r_enable_ext_reset <= i_wbs_dat[`CTRL_BIT_ENABLE_EXT_RESET];
//r_manual_pcie_reset <= i_wbs_dat[`CTRL_BIT_MANUAL_USER_RESET];
end
TX_DIFF_CTRL: begin
r_tx_diff_ctrl <= i_wbs_dat[3:0];
end
TX_DIFF_CTRL: begin
r_tx_pre_emphasis <= i_wbs_dat[2:0];
end
RX_EQUALIZER_CTRL: begin
r_rx_equalizer_ctrl <= i_wbs_dat[1:0];
end
default: begin
if (w_lcl_mem_en) begin
r_lcl_mem_we <= 1;
r_lcl_mem_din <= i_wbs_dat;
end
end
endcase
o_wbs_ack <= 1;
end
else begin
//read request
case (i_wbs_adr)
CONTROL: begin
o_wbs_dat <= 0;
o_wbs_dat[`CTRL_BIT_ENABLE_LOCAL_READ] <= r_ppfifo_2_mem_en;
o_wbs_dat[`CTRL_BIT_ENABLE] <= r_enable_pcie;
//o_wbs_dat[`CTRL_BIT_ENABLE_EXT_RESET] <= r_enable_ext_reset;
//o_wbs_dat[`CTRL_BIT_MANUAL_USER_RESET] <= r_manual_pcie_reset;
end
STATUS: begin
o_wbs_dat <= 0;
o_wbs_dat[`STS_BIT_PCIE_RESET] <= pcie_reset;
o_wbs_dat[`STS_BIT_LINKUP] <= user_lnk_up;
o_wbs_dat[`STS_BIT_RECEIVED_HOT_RESET] <= received_hot_reset;
o_wbs_dat[`STS_BITS_PCIE_LINK_STATE] <= cfg_pcie_link_state;
o_wbs_dat[`STS_BITS_PCIE_BUS_NUM] <= cfg_bus_number;
o_wbs_dat[`STS_BITS_PCIE_DEV_NUM] <= cfg_device_number;
o_wbs_dat[`STS_BITS_PCIE_FUNC_NUM] <= cfg_function_number;
o_wbs_dat[`STS_BIT_GTP_PLL_LOCK_DETECT] <= gtp_pll_lock_detect;
o_wbs_dat[`STS_BIT_PLL_LOCK_DETECT] <= pll_lock_detect;
o_wbs_dat[`STS_BIT_GTP_RESET_DONE] <= gtp_reset_done;
o_wbs_dat[`STS_BIT_RX_ELEC_IDLE] <= rx_elec_idle;
o_wbs_dat[`STS_BIT_CFG_TO_TURNOFF] <= cfg_to_turnoff;
o_wbs_dat[`STS_BIT_PCIE_EXT_RESET] <= !i_pcie_reset_n;
end
NUM_BLOCK_READ: begin
o_wbs_dat <= w_num_reads;
end
LOCAL_BUFFER_SIZE: begin
o_wbs_dat <= CONTROL_BUFFER_SIZE;
end
PCIE_CLOCK_CNT: begin
o_wbs_dat <= r_clock_1_sec;
end
TEST_CLOCK: begin
o_wbs_dat <= r_clock_count;
end
TX_DIFF_CTRL: begin
o_wbs_dat <= 0;
o_wbs_dat[3:0] <= r_tx_diff_ctrl;
end
TX_PRE_EMPH: begin
o_wbs_dat <= 0;
o_wbs_dat[3:0] <= r_tx_pre_emphasis;
end
RX_EQUALIZER_CTRL: begin
o_wbs_dat <= 0;
o_wbs_dat[1:0] <= r_rx_equalizer_ctrl;
end
LTSSM_STATE: begin
o_wbs_dat <= 0;
o_wbs_dat[4:0] <= cfg_ltssm_state;
end
DBG_DATA: begin
o_wbs_dat <= 0;
o_wbs_dat[`DBG_CORRECTABLE ] <= dbg_correctable;
o_wbs_dat[`DBG_FATAL ] <= dbg_fatal;
o_wbs_dat[`DBG_NON_FATAL ] <= dbg_non_fatal;
o_wbs_dat[`DBG_UNSUPPORTED ] <= dbg_unsupported;
end
CONFIG_COMMAND: begin
o_wbs_dat <= 0;
o_wbs_dat <= {16'h0000, cfg_command};
end
CONFIG_STATUS: begin
o_wbs_dat <= 0;
o_wbs_dat <= {16'h0000, cfg_status};
end
CONFIG_DSTATUS: begin
o_wbs_dat <= 0;
o_wbs_dat <= {16'h0000, cfg_dstatus};
end
CONFIG_DCOMMAND: begin
o_wbs_dat <= 0;
o_wbs_dat <= {16'h0000, cfg_dcommand};
end
CONFIG_LSTATUS: begin
o_wbs_dat <= 0;
o_wbs_dat <= {16'h0000, cfg_lstatus};
end
CONFIG_LCOMMAND: begin
o_wbs_dat <= 0;
o_wbs_dat <= {16'h0000, cfg_lcommand};
end
DBG_FLAGS: begin
o_wbs_dat <= 0;
o_wbs_dat[`DBG_BAD_DLLP_STATUS ] <= r_dbg_bad_dllp_status;
o_wbs_dat[`DBG_BAD_TLP_LCRC ] <= r_dbg_bad_tlp_lcrc;
o_wbs_dat[`DBG_BAD_TLP_SEQ_NUM ] <= r_dbg_bad_tlp_seq_num;
o_wbs_dat[`DBG_BAD_TLP_STATUS ] <= r_dbg_bad_tlp_status;
o_wbs_dat[`DBG_DL_PROTOCOL_STATUS ] <= r_dbg_dl_protocol_status;
o_wbs_dat[`DBG_FC_PROTOCOL_ERR_STATUS ] <= r_dbg_fc_protocol_err_status;
o_wbs_dat[`DBG_MLFMD_LENGTH ] <= r_dbg_mlfrmd_length;
o_wbs_dat[`DBG_MLFMD_MPS ] <= r_dbg_mlfrmd_mps;
o_wbs_dat[`DBG_MLFMD_TCVC ] <= r_dbg_mlfrmd_tcvc;
o_wbs_dat[`DBG_MLFMD_TLP_STATUS ] <= r_dbg_mlfrmd_tlp_status;
o_wbs_dat[`DBG_MLFMD_UNREC_TYPE ] <= r_dbg_mlfrmd_unrec_type;
o_wbs_dat[`DBG_POISTLPSTATUS ] <= r_dbg_poistlpstatus;
o_wbs_dat[`DBG_RCVR_OVERFLOW_STATUS ] <= r_dbg_rcvr_overflow_status;
o_wbs_dat[`DBG_RPLY_ROLLOVER_STATUS ] <= r_dbg_rply_rollover_status;
o_wbs_dat[`DBG_RPLY_TIMEOUT_STATUS ] <= r_dbg_rply_timeout_status;
o_wbs_dat[`DBG_UR_NO_BAR_HIT ] <= r_dbg_ur_no_bar_hit;
o_wbs_dat[`DBG_UR_POIS_CFG_WR ] <= r_dbg_ur_pois_cfg_wr;
o_wbs_dat[`DBG_UR_STATUS ] <= r_dbg_ur_status;
o_wbs_dat[`DBG_UR_UNSUP_MSG ] <= r_dbg_ur_unsup_msg;
end
default: begin
if (w_lcl_mem_en) begin
o_wbs_dat <= w_lcl_mem_dout;
end
end
endcase
if (w_lcl_mem_valid) begin
o_wbs_ack <= 1;
end
end
end
end
if (r_host_clock_count < `CLOCK_RATE) begin
r_host_clock_count <= r_host_clock_count + 1;
end
else begin
r_host_clock_count <= 0;
r_1sec_stb_100mhz <= 1;
end
end
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "setup.v"
module gen_capabilities(
output [31:0] capabilities
);
wire memorycard;
wire ac97;
wire pfpu;
wire tmu;
wire ethernet;
wire fmlmeter;
wire videoin;
wire midi;
wire dmx;
wire ir;
wire usb;
wire memtest;
wire aceusb;
wire ps2keyboard;
wire ps2mouse;
assign capabilities = {
17'd0,
ps2mouse,
ps2keyboard,
aceusb,
memtest,
usb,
ir,
dmx,
midi,
videoin,
fmlmeter,
ethernet,
tmu,
pfpu,
ac97,
memorycard
};
`ifdef ENABLE_MEMORYCARD
assign memorycard = 1'b1;
`else
assign memorycard = 1'b0;
`endif
`ifdef ENABLE_AC97
assign ac97 = 1'b1;
`else
assign ac97 = 1'b0;
`endif
`ifdef ENABLE_PFPU
assign pfpu = 1'b1;
`else
assign pfpu = 1'b0;
`endif
`ifdef ENABLE_TMU
assign tmu = 1'b1;
`else
assign tmu = 1'b0;
`endif
`ifdef ENABLE_ETHERNET
assign ethernet = 1'b1;
`else
assign ethernet = 1'b0;
`endif
`ifdef ENABLE_FMLMETER
assign fmlmeter = 1'b1;
`else
assign fmlmeter = 1'b0;
`endif
`ifdef ENABLE_VIDEOIN
assign videoin = 1'b1;
`else
assign videoin = 1'b0;
`endif
`ifdef ENABLE_MIDI
assign midi = 1'b1;
`else
assign midi = 1'b0;
`endif
`ifdef ENABLE_DMX
assign dmx = 1'b1;
`else
assign dmx = 1'b0;
`endif
`ifdef ENABLE_IR
assign ir = 1'b1;
`else
assign ir = 1'b0;
`endif
`ifdef ENABLE_USB
assign usb = 1'b1;
`else
assign usb = 1'b0;
`endif
`ifdef ENABLE_MEMTEST
assign memtest = 1'b1;
`else
assign memtest = 1'b0;
`endif
`ifdef ENABLE_ACEUSB
assign aceusb = 1'b1;
`else
assign aceusb = 1'b0;
`endif
`ifdef ENABLE_PS2_KEYBOARD
assign ps2keyboard = 1'b1;
`else
assign ps2keyboard = 1'b0;
`endif
`ifdef ENABLE_PS2_MOUSE
assign ps2keymouse = 1'b1;
`else
assign ps2keymouse = 1'b0;
`endif
endmodule
|
module thermometer_to_bcd(bcd, thermometer);
output [7:0] bcd;
input [15:0] thermometer;
assign bcd = (thermometer == 16'b0) ? 0 :
(thermometer == 16'b1) ? 1 :
(thermometer == 16'b11) ? 2 :
(thermometer == 16'b111) ? 3 :
(thermometer == 16'b1111) ? 4 :
(thermometer == 16'b11111) ? 5 :
(thermometer == 16'b111111) ? 6 :
(thermometer == 16'b1111111) ? 7 :
(thermometer == 16'b11111111) ? 8 :
(thermometer == 16'b111111111) ? 9 :
(thermometer == 16'b1111111111) ? 9 :
(thermometer == 16'b11111111111) ? {4'd1, 4'd0} :
(thermometer == 16'b111111111111) ? {4'd1, 4'd1} :
(thermometer == 16'b1111111111111) ? {4'd1, 4'd2} :
(thermometer == 16'b11111111111111) ? {4'd1, 4'd3} :
(thermometer == 16'b111111111111111) ? {4'd1, 4'd4} :
(thermometer == 16'b1111111111111111) ? {4'd1, 4'd5} :
{4'd1, 4'd6};
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
`include "ipl_config.vh"
// This core aims to implement a simple, reusable Wishbone B.4 compatible bus
// master (currently in the form of a generic DMA controller). EMPHASIS ON
// SIMPLE -- pipelined mode can get pretty complex if you're not careful.
//
// Masters and slaves designed to work with pipelined Wishbone are rather
// simple to implement overall. You just register the address, the bus command
// (read/write), and if writing, the data. Just make sure CYC_O is asserted
// until all outstanding transactions are completed.
//
// Be careful about edge cases though. If you implement back-to-back cycles to
// two different peripherals, and your pipeline depth is different for each,
// you can get an out-of-order response which leads to read 1 getting read 2's
// data, or worse. Ultimately, since most masters are built to be generic,
// it's up to the intercon to prevent this from happening by forcing STALL_I on
// the master high until order can be preserved. But, this is getting into
// that complexity that I specifically wanted to avoid above. The simpler way
// of preventing this from happening is sticking to one, and only one,
// outstanding transaction per bus cycle: one strobe, one ack, in that order.
// This master is currently built to model a DMA controller. A *pulse* on
// DREQ_I triggers back to back read then write operations. A pulse on DACK_O
// indicates to the slave that its request is *currently* being addressed. (It
// does **not** indicate that the request has been completely serviced yet.)
// __ __ __ __
// CLK_I __/ \__/ \__/ \__/ \__
// _____
// DREQ_I ___/ \________________
// ______
// DACK_O ________/ \__________
// ____________
// CYC_O ________/ \____
// ____________
// STB_O ________/ \____
// ______
// WE_O ______________/ \____
// _____________
// ACK_I ________//// \___
//
// The following timing diagram shows a more traditional timing diagram for
// pipelined Wishbone interconnects:
// __ __ __ __ __ __ __ __
// CLK_I __/ \__/ \__/ \__/ \__/ \__/ \__/ \__/ \__
// _____
// DREQ_I ___/ \________________________________________
// ______
// DACK_O ________/ \__________________________________
// ____________________________________
// CYC_O ________/ \____
// ______ ______
// STB_O ________/ \__________/ \________________
// ______
// WE_O __________________________/ \________________
// ______ _____
// ACK_I _______________/ \________________/ \____
//
//
// Note that DREQ_I is sampled when the DMAC is idle, or when ACK_I is asserted
// on the write cycle. At least on my simulator, it's possible to get
// sustained back-to-back reads and writes with this logic as long as DREQ_I
// and ACK_I remains asserted.
//
// NOTE: This core does not implement a complete Wishbone interface.
// Only the bare minimum needed to illustrate the relevant and core
// logic.
//
// NOTE AGAIN: Notice that this core does not proceed beyond a single
// transaction. As a result, we do not accept a STALL_I input. It doesn't make sense for us.
// However, if you make a core that *does* allow more than one outstanding bus transaction,
// you will absolutely have to support STALL_I.
module master(
input clk_i,
input reset_i,
input dreq_i,
output dack_o,
output [AW:0] adr_o,
output cyc_o,
output stb_o,
output we_o,
input ack_i
);
parameter ADDR_WIDTH = 16;
parameter IPL_READ_ADDR = `IPL_READ_ADDR;
parameter IPL_WRITE_ADDR = `IPL_WRITE_ADDR;
parameter AW = ADDR_WIDTH - 1;
reg [AW:0] adr_o;
reg stb_o;
reg we_o;
reg [AW:0] rd_adr, wr_adr;
reg rd_cyc, wr_cyc;
reg dack_o;
assign cyc_o = rd_cyc | wr_cyc;
always @(posedge clk_i) begin
// Unless otherwise instructed, the following signals assume
// these values on any given clock cycle.
adr_o <= 0;
stb_o <= 0;
we_o <= 0;
rd_cyc <= rd_cyc;
wr_cyc <= wr_cyc;
dack_o <= 0;
// Upon reset, reset internal registers to their power-on
// defaults.
if(reset_i) begin
rd_adr <= IPL_READ_ADDR;
wr_adr <= IPL_WRITE_ADDR;
rd_cyc <= 0;
wr_cyc <= 0;
end
// Otherwise, implement the read/write state machine here.
else begin
// WARNING: THIS CODE IS NOT EXPRESSLY DESIGNED FOR
// SINGLE-CYCLE TRANSACTIONS. Experience on my
// simulator shows that it works in practice; but, I
// offer NO PROMISE that it'll work for you. You'll
// need to explore/experiment on your own.
// If the DMAC isn't doing anything at the moment,
// initiate a read cycle. At this time, we acknowledge
// the request for data to tell the slave that it's
// in-progress.
if(dreq_i && ~cyc_o) begin
adr_o <= rd_adr;
stb_o <= 1;
rd_cyc <= 1;
dack_o <= 1;
end
// If the read cycle is complete, then we kick off the
// write cycle.
if(rd_cyc && ack_i) begin
rd_cyc <= 0;
wr_cyc <= 1;
adr_o <= wr_adr;
stb_o <= 1;
we_o <= 1;
end
// If the write cycle is complete, we sample the DREQ_I
// signal. If it's still asserted, kick off another
// read cycle. Otherwise, revert back to idle
// condition.
if(wr_cyc && ack_i) begin
wr_cyc <= 0;
if(dreq_i) begin
adr_o <= rd_adr;
stb_o <= 1;
rd_cyc <= 1;
dack_o <= 1;
end
end
end
end
endmodule
|
`timescale 1ns/1ns
module sine_table_11bit_float32
(input c,
input [10:0] angle,
output reg [31:0] sine);
always @(posedge c) begin
case (angle)
11'd0: sine = 32'h0;
11'd1: sine = 32'h3b490fc6;
11'd2: sine = 32'h3bc90f88;
11'd3: sine = 32'h3c16cb58;
11'd4: sine = 32'h3c490e90;
11'd5: sine = 32'h3c7b514b;
11'd6: sine = 32'h3c96c9b6;
11'd7: sine = 32'h3cafea69;
11'd8: sine = 32'h3cc90ab0;
11'd9: sine = 32'h3ce22a7a;
11'd10: sine = 32'h3cfb49b9;
11'd11: sine = 32'h3d0a342f;
11'd12: sine = 32'h3d16c32c;
11'd13: sine = 32'h3d2351cb;
11'd14: sine = 32'h3d2fe006;
11'd15: sine = 32'h3d3c6dd5;
11'd16: sine = 32'h3d48fb2f;
11'd17: sine = 32'h3d55880e;
11'd18: sine = 32'h3d621468;
11'd19: sine = 32'h3d6ea038;
11'd20: sine = 32'h3d7b2b74;
11'd21: sine = 32'h3d83db0a;
11'd22: sine = 32'h3d8a2009;
11'd23: sine = 32'h3d9064b3;
11'd24: sine = 32'h3d96a904;
11'd25: sine = 32'h3d9cecf8;
11'd26: sine = 32'h3da3308c;
11'd27: sine = 32'h3da973ba;
11'd28: sine = 32'h3dafb680;
11'd29: sine = 32'h3db5f8da;
11'd30: sine = 32'h3dbc3ac3;
11'd31: sine = 32'h3dc27c38;
11'd32: sine = 32'h3dc8bd36;
11'd33: sine = 32'h3dcefdb7;
11'd34: sine = 32'h3dd53db9;
11'd35: sine = 32'h3ddb7d37;
11'd36: sine = 32'h3de1bc2e;
11'd37: sine = 32'h3de7fa9a;
11'd38: sine = 32'h3dee3876;
11'd39: sine = 32'h3df475c0;
11'd40: sine = 32'h3dfab272;
11'd41: sine = 32'h3e007745;
11'd42: sine = 32'h3e039502;
11'd43: sine = 32'h3e06b26e;
11'd44: sine = 32'h3e09cf86;
11'd45: sine = 32'h3e0cec4a;
11'd46: sine = 32'h3e1008b6;
11'd47: sine = 32'h3e1324ca;
11'd48: sine = 32'h3e164083;
11'd49: sine = 32'h3e195be0;
11'd50: sine = 32'h3e1c76dd;
11'd51: sine = 32'h3e1f917b;
11'd52: sine = 32'h3e22abb5;
11'd53: sine = 32'h3e25c58c;
11'd54: sine = 32'h3e28defc;
11'd55: sine = 32'h3e2bf804;
11'd56: sine = 32'h3e2f10a2;
11'd57: sine = 32'h3e3228d4;
11'd58: sine = 32'h3e354098;
11'd59: sine = 32'h3e3857ec;
11'd60: sine = 32'h3e3b6ecf;
11'd61: sine = 32'h3e3e853e;
11'd62: sine = 32'h3e419b37;
11'd63: sine = 32'h3e44b0b9;
11'd64: sine = 32'h3e47c5c2;
11'd65: sine = 32'h3e4ada4f;
11'd66: sine = 32'h3e4dee5f;
11'd67: sine = 32'h3e5101f1;
11'd68: sine = 32'h3e541501;
11'd69: sine = 32'h3e57278e;
11'd70: sine = 32'h3e5a3997;
11'd71: sine = 32'h3e5d4b19;
11'd72: sine = 32'h3e605c13;
11'd73: sine = 32'h3e636c82;
11'd74: sine = 32'h3e667c65;
11'd75: sine = 32'h3e698bba;
11'd76: sine = 32'h3e6c9a7f;
11'd77: sine = 32'h3e6fa8b2;
11'd78: sine = 32'h3e72b651;
11'd79: sine = 32'h3e75c35a;
11'd80: sine = 32'h3e78cfcc;
11'd81: sine = 32'h3e7bdba4;
11'd82: sine = 32'h3e7ee6e1;
11'd83: sine = 32'h3e80f8c0;
11'd84: sine = 32'h3e827dc0;
11'd85: sine = 32'h3e840270;
11'd86: sine = 32'h3e8586ce;
11'd87: sine = 32'h3e870ada;
11'd88: sine = 32'h3e888e93;
11'd89: sine = 32'h3e8a11f7;
11'd90: sine = 32'h3e8b9507;
11'd91: sine = 32'h3e8d17c0;
11'd92: sine = 32'h3e8e9a22;
11'd93: sine = 32'h3e901c2c;
11'd94: sine = 32'h3e919ddd;
11'd95: sine = 32'h3e931f35;
11'd96: sine = 32'h3e94a031;
11'd97: sine = 32'h3e9620d2;
11'd98: sine = 32'h3e97a117;
11'd99: sine = 32'h3e9920fe;
11'd100: sine = 32'h3e9aa086;
11'd101: sine = 32'h3e9c1faf;
11'd102: sine = 32'h3e9d9e78;
11'd103: sine = 32'h3e9f1cdf;
11'd104: sine = 32'h3ea09ae4;
11'd105: sine = 32'h3ea21887;
11'd106: sine = 32'h3ea395c5;
11'd107: sine = 32'h3ea5129e;
11'd108: sine = 32'h3ea68f12;
11'd109: sine = 32'h3ea80b1f;
11'd110: sine = 32'h3ea986c4;
11'd111: sine = 32'h3eab0200;
11'd112: sine = 32'h3eac7cd3;
11'd113: sine = 32'h3eadf73c;
11'd114: sine = 32'h3eaf713a;
11'd115: sine = 32'h3eb0eacb;
11'd116: sine = 32'h3eb263ef;
11'd117: sine = 32'h3eb3dca5;
11'd118: sine = 32'h3eb554ec;
11'd119: sine = 32'h3eb6ccc3;
11'd120: sine = 32'h3eb84429;
11'd121: sine = 32'h3eb9bb1e;
11'd122: sine = 32'h3ebb31a0;
11'd123: sine = 32'h3ebca7af;
11'd124: sine = 32'h3ebe1d49;
11'd125: sine = 32'h3ebf926e;
11'd126: sine = 32'h3ec1071d;
11'd127: sine = 32'h3ec27b55;
11'd128: sine = 32'h3ec3ef15;
11'd129: sine = 32'h3ec5625c;
11'd130: sine = 32'h3ec6d529;
11'd131: sine = 32'h3ec8477c;
11'd132: sine = 32'h3ec9b953;
11'd133: sine = 32'h3ecb2aae;
11'd134: sine = 32'h3ecc9b8b;
11'd135: sine = 32'h3ece0bea;
11'd136: sine = 32'h3ecf7bca;
11'd137: sine = 32'h3ed0eb2a;
11'd138: sine = 32'h3ed25a09;
11'd139: sine = 32'h3ed3c866;
11'd140: sine = 32'h3ed53641;
11'd141: sine = 32'h3ed6a398;
11'd142: sine = 32'h3ed8106b;
11'd143: sine = 32'h3ed97cb9;
11'd144: sine = 32'h3edae880;
11'd145: sine = 32'h3edc53c0;
11'd146: sine = 32'h3eddbe79;
11'd147: sine = 32'h3edf28a9;
11'd148: sine = 32'h3ee0924f;
11'd149: sine = 32'h3ee1fb6a;
11'd150: sine = 32'h3ee363fa;
11'd151: sine = 32'h3ee4cbfe;
11'd152: sine = 32'h3ee63375;
11'd153: sine = 32'h3ee79a5d;
11'd154: sine = 32'h3ee900b7;
11'd155: sine = 32'h3eea6681;
11'd156: sine = 32'h3eebcbbb;
11'd157: sine = 32'h3eed3063;
11'd158: sine = 32'h3eee9478;
11'd159: sine = 32'h3eeff7fb;
11'd160: sine = 32'h3ef15aea;
11'd161: sine = 32'h3ef2bd43;
11'd162: sine = 32'h3ef41f07;
11'd163: sine = 32'h3ef58034;
11'd164: sine = 32'h3ef6e0ca;
11'd165: sine = 32'h3ef840c8;
11'd166: sine = 32'h3ef9a02c;
11'd167: sine = 32'h3efafef7;
11'd168: sine = 32'h3efc5d27;
11'd169: sine = 32'h3efdbabb;
11'd170: sine = 32'h3eff17b2;
11'd171: sine = 32'h3f003a06;
11'd172: sine = 32'h3f00e7e4;
11'd173: sine = 32'h3f019573;
11'd174: sine = 32'h3f0242b1;
11'd175: sine = 32'h3f02ef9f;
11'd176: sine = 32'h3f039c3d;
11'd177: sine = 32'h3f044889;
11'd178: sine = 32'h3f04f483;
11'd179: sine = 32'h3f05a02c;
11'd180: sine = 32'h3f064b82;
11'd181: sine = 32'h3f06f686;
11'd182: sine = 32'h3f07a136;
11'd183: sine = 32'h3f084b92;
11'd184: sine = 32'h3f08f59a;
11'd185: sine = 32'h3f099f4e;
11'd186: sine = 32'h3f0a48ad;
11'd187: sine = 32'h3f0af1b7;
11'd188: sine = 32'h3f0b9a6b;
11'd189: sine = 32'h3f0c42c9;
11'd190: sine = 32'h3f0cead0;
11'd191: sine = 32'h3f0d9281;
11'd192: sine = 32'h3f0e39da;
11'd193: sine = 32'h3f0ee0db;
11'd194: sine = 32'h3f0f8784;
11'd195: sine = 32'h3f102dd5;
11'd196: sine = 32'h3f10d3cd;
11'd197: sine = 32'h3f11796b;
11'd198: sine = 32'h3f121eb0;
11'd199: sine = 32'h3f12c39a;
11'd200: sine = 32'h3f13682a;
11'd201: sine = 32'h3f140c5f;
11'd202: sine = 32'h3f14b039;
11'd203: sine = 32'h3f1553b7;
11'd204: sine = 32'h3f15f6d9;
11'd205: sine = 32'h3f16999e;
11'd206: sine = 32'h3f173c07;
11'd207: sine = 32'h3f17de12;
11'd208: sine = 32'h3f187fc0;
11'd209: sine = 32'h3f19210f;
11'd210: sine = 32'h3f19c200;
11'd211: sine = 32'h3f1a6292;
11'd212: sine = 32'h3f1b02c5;
11'd213: sine = 32'h3f1ba299;
11'd214: sine = 32'h3f1c420c;
11'd215: sine = 32'h3f1ce11f;
11'd216: sine = 32'h3f1d7fd1;
11'd217: sine = 32'h3f1e1e22;
11'd218: sine = 32'h3f1ebc12;
11'd219: sine = 32'h3f1f599f;
11'd220: sine = 32'h3f1ff6ca;
11'd221: sine = 32'h3f209393;
11'd222: sine = 32'h3f212ff9;
11'd223: sine = 32'h3f21cbfb;
11'd224: sine = 32'h3f226799;
11'd225: sine = 32'h3f2302d3;
11'd226: sine = 32'h3f239da9;
11'd227: sine = 32'h3f243819;
11'd228: sine = 32'h3f24d225;
11'd229: sine = 32'h3f256bca;
11'd230: sine = 32'h3f26050a;
11'd231: sine = 32'h3f269de3;
11'd232: sine = 32'h3f273656;
11'd233: sine = 32'h3f27ce61;
11'd234: sine = 32'h3f286605;
11'd235: sine = 32'h3f28fd41;
11'd236: sine = 32'h3f299414;
11'd237: sine = 32'h3f2a2a80;
11'd238: sine = 32'h3f2ac082;
11'd239: sine = 32'h3f2b561a;
11'd240: sine = 32'h3f2beb49;
11'd241: sine = 32'h3f2c800f;
11'd242: sine = 32'h3f2d1469;
11'd243: sine = 32'h3f2da859;
11'd244: sine = 32'h3f2e3bde;
11'd245: sine = 32'h3f2ecef7;
11'd246: sine = 32'h3f2f61a5;
11'd247: sine = 32'h3f2ff3e6;
11'd248: sine = 32'h3f3085bb;
11'd249: sine = 32'h3f311722;
11'd250: sine = 32'h3f31a81d;
11'd251: sine = 32'h3f3238aa;
11'd252: sine = 32'h3f32c8c9;
11'd253: sine = 32'h3f33587a;
11'd254: sine = 32'h3f33e7bc;
11'd255: sine = 32'h3f34768f;
11'd256: sine = 32'h3f3504f3;
11'd257: sine = 32'h3f3592e7;
11'd258: sine = 32'h3f36206b;
11'd259: sine = 32'h3f36ad7f;
11'd260: sine = 32'h3f373a22;
11'd261: sine = 32'h3f37c655;
11'd262: sine = 32'h3f385215;
11'd263: sine = 32'h3f38dd65;
11'd264: sine = 32'h3f396842;
11'd265: sine = 32'h3f39f2ac;
11'd266: sine = 32'h3f3a7ca4;
11'd267: sine = 32'h3f3b0629;
11'd268: sine = 32'h3f3b8f3b;
11'd269: sine = 32'h3f3c17d9;
11'd270: sine = 32'h3f3ca003;
11'd271: sine = 32'h3f3d27b8;
11'd272: sine = 32'h3f3daef9;
11'd273: sine = 32'h3f3e35c5;
11'd274: sine = 32'h3f3ebc1b;
11'd275: sine = 32'h3f3f41fc;
11'd276: sine = 32'h3f3fc767;
11'd277: sine = 32'h3f404c5c;
11'd278: sine = 32'h3f40d0d9;
11'd279: sine = 32'h3f4154e0;
11'd280: sine = 32'h3f41d870;
11'd281: sine = 32'h3f425b88;
11'd282: sine = 32'h3f42de29;
11'd283: sine = 32'h3f436051;
11'd284: sine = 32'h3f43e200;
11'd285: sine = 32'h3f446337;
11'd286: sine = 32'h3f44e3f5;
11'd287: sine = 32'h3f456439;
11'd288: sine = 32'h3f45e403;
11'd289: sine = 32'h3f466353;
11'd290: sine = 32'h3f46e229;
11'd291: sine = 32'h3f476085;
11'd292: sine = 32'h3f47de65;
11'd293: sine = 32'h3f485bca;
11'd294: sine = 32'h3f48d8b3;
11'd295: sine = 32'h3f495521;
11'd296: sine = 32'h3f49d112;
11'd297: sine = 32'h3f4a4c87;
11'd298: sine = 32'h3f4ac77f;
11'd299: sine = 32'h3f4b41fa;
11'd300: sine = 32'h3f4bbbf7;
11'd301: sine = 32'h3f4c3577;
11'd302: sine = 32'h3f4cae79;
11'd303: sine = 32'h3f4d26fd;
11'd304: sine = 32'h3f4d9f02;
11'd305: sine = 32'h3f4e1688;
11'd306: sine = 32'h3f4e8d90;
11'd307: sine = 32'h3f4f0417;
11'd308: sine = 32'h3f4f7a1f;
11'd309: sine = 32'h3f4fefa7;
11'd310: sine = 32'h3f5064af;
11'd311: sine = 32'h3f50d936;
11'd312: sine = 32'h3f514d3d;
11'd313: sine = 32'h3f51c0c2;
11'd314: sine = 32'h3f5233c6;
11'd315: sine = 32'h3f52a648;
11'd316: sine = 32'h3f531849;
11'd317: sine = 32'h3f5389c7;
11'd318: sine = 32'h3f53fac2;
11'd319: sine = 32'h3f546b3b;
11'd320: sine = 32'h3f54db31;
11'd321: sine = 32'h3f554aa4;
11'd322: sine = 32'h3f55b993;
11'd323: sine = 32'h3f5627fe;
11'd324: sine = 32'h3f5695e5;
11'd325: sine = 32'h3f570347;
11'd326: sine = 32'h3f577025;
11'd327: sine = 32'h3f57dc7f;
11'd328: sine = 32'h3f584853;
11'd329: sine = 32'h3f58b3a1;
11'd330: sine = 32'h3f591e6a;
11'd331: sine = 32'h3f5988ad;
11'd332: sine = 32'h3f59f26a;
11'd333: sine = 32'h3f5a5ba0;
11'd334: sine = 32'h3f5ac450;
11'd335: sine = 32'h3f5b2c79;
11'd336: sine = 32'h3f5b941a;
11'd337: sine = 32'h3f5bfb34;
11'd338: sine = 32'h3f5c61c6;
11'd339: sine = 32'h3f5cc7d1;
11'd340: sine = 32'h3f5d2d53;
11'd341: sine = 32'h3f5d924d;
11'd342: sine = 32'h3f5df6be;
11'd343: sine = 32'h3f5e5aa6;
11'd344: sine = 32'h3f5ebe05;
11'd345: sine = 32'h3f5f20db;
11'd346: sine = 32'h3f5f8327;
11'd347: sine = 32'h3f5fe4e9;
11'd348: sine = 32'h3f604621;
11'd349: sine = 32'h3f60a6cf;
11'd350: sine = 32'h3f6106f2;
11'd351: sine = 32'h3f61668a;
11'd352: sine = 32'h3f61c597;
11'd353: sine = 32'h3f622419;
11'd354: sine = 32'h3f628210;
11'd355: sine = 32'h3f62df7b;
11'd356: sine = 32'h3f633c59;
11'd357: sine = 32'h3f6398ac;
11'd358: sine = 32'h3f63f472;
11'd359: sine = 32'h3f644fac;
11'd360: sine = 32'h3f64aa59;
11'd361: sine = 32'h3f650479;
11'd362: sine = 32'h3f655e0b;
11'd363: sine = 32'h3f65b710;
11'd364: sine = 32'h3f660f87;
11'd365: sine = 32'h3f666771;
11'd366: sine = 32'h3f66becc;
11'd367: sine = 32'h3f671599;
11'd368: sine = 32'h3f676bd7;
11'd369: sine = 32'h3f67c187;
11'd370: sine = 32'h3f6816a8;
11'd371: sine = 32'h3f686b39;
11'd372: sine = 32'h3f68bf3b;
11'd373: sine = 32'h3f6912ae;
11'd374: sine = 32'h3f696591;
11'd375: sine = 32'h3f69b7e4;
11'd376: sine = 32'h3f6a09a6;
11'd377: sine = 32'h3f6a5ad9;
11'd378: sine = 32'h3f6aab7a;
11'd379: sine = 32'h3f6afb8b;
11'd380: sine = 32'h3f6b4b0b;
11'd381: sine = 32'h3f6b99fa;
11'd382: sine = 32'h3f6be858;
11'd383: sine = 32'h3f6c3624;
11'd384: sine = 32'h3f6c835e;
11'd385: sine = 32'h3f6cd007;
11'd386: sine = 32'h3f6d1c1d;
11'd387: sine = 32'h3f6d67a1;
11'd388: sine = 32'h3f6db293;
11'd389: sine = 32'h3f6dfcf2;
11'd390: sine = 32'h3f6e46be;
11'd391: sine = 32'h3f6e8ff7;
11'd392: sine = 32'h3f6ed89e;
11'd393: sine = 32'h3f6f20b0;
11'd394: sine = 32'h3f6f6830;
11'd395: sine = 32'h3f6faf1b;
11'd396: sine = 32'h3f6ff573;
11'd397: sine = 32'h3f703b37;
11'd398: sine = 32'h3f708066;
11'd399: sine = 32'h3f70c501;
11'd400: sine = 32'h3f710908;
11'd401: sine = 32'h3f714c7a;
11'd402: sine = 32'h3f718f57;
11'd403: sine = 32'h3f71d19f;
11'd404: sine = 32'h3f721352;
11'd405: sine = 32'h3f725470;
11'd406: sine = 32'h3f7294f8;
11'd407: sine = 32'h3f72d4eb;
11'd408: sine = 32'h3f731447;
11'd409: sine = 32'h3f73530e;
11'd410: sine = 32'h3f73913f;
11'd411: sine = 32'h3f73ced9;
11'd412: sine = 32'h3f740bdd;
11'd413: sine = 32'h3f74484b;
11'd414: sine = 32'h3f748422;
11'd415: sine = 32'h3f74bf62;
11'd416: sine = 32'h3f74fa0b;
11'd417: sine = 32'h3f75341d;
11'd418: sine = 32'h3f756d97;
11'd419: sine = 32'h3f75a67a;
11'd420: sine = 32'h3f75dec6;
11'd421: sine = 32'h3f76167a;
11'd422: sine = 32'h3f764d97;
11'd423: sine = 32'h3f76841b;
11'd424: sine = 32'h3f76ba07;
11'd425: sine = 32'h3f76ef5b;
11'd426: sine = 32'h3f772417;
11'd427: sine = 32'h3f77583a;
11'd428: sine = 32'h3f778bc5;
11'd429: sine = 32'h3f77beb7;
11'd430: sine = 32'h3f77f110;
11'd431: sine = 32'h3f7822d1;
11'd432: sine = 32'h3f7853f8;
11'd433: sine = 32'h3f788486;
11'd434: sine = 32'h3f78b47b;
11'd435: sine = 32'h3f78e3d6;
11'd436: sine = 32'h3f791298;
11'd437: sine = 32'h3f7940c0;
11'd438: sine = 32'h3f796e4e;
11'd439: sine = 32'h3f799b43;
11'd440: sine = 32'h3f79c79d;
11'd441: sine = 32'h3f79f35e;
11'd442: sine = 32'h3f7a1e84;
11'd443: sine = 32'h3f7a4910;
11'd444: sine = 32'h3f7a7302;
11'd445: sine = 32'h3f7a9c59;
11'd446: sine = 32'h3f7ac515;
11'd447: sine = 32'h3f7aed37;
11'd448: sine = 32'h3f7b14be;
11'd449: sine = 32'h3f7b3bab;
11'd450: sine = 32'h3f7b61fc;
11'd451: sine = 32'h3f7b87b2;
11'd452: sine = 32'h3f7baccd;
11'd453: sine = 32'h3f7bd14d;
11'd454: sine = 32'h3f7bf531;
11'd455: sine = 32'h3f7c187a;
11'd456: sine = 32'h3f7c3b28;
11'd457: sine = 32'h3f7c5d3a;
11'd458: sine = 32'h3f7c7eb0;
11'd459: sine = 32'h3f7c9f8a;
11'd460: sine = 32'h3f7cbfc9;
11'd461: sine = 32'h3f7cdf6c;
11'd462: sine = 32'h3f7cfe73;
11'd463: sine = 32'h3f7d1cdd;
11'd464: sine = 32'h3f7d3aac;
11'd465: sine = 32'h3f7d57de;
11'd466: sine = 32'h3f7d7474;
11'd467: sine = 32'h3f7d906e;
11'd468: sine = 32'h3f7dabcb;
11'd469: sine = 32'h3f7dc68c;
11'd470: sine = 32'h3f7de0b1;
11'd471: sine = 32'h3f7dfa38;
11'd472: sine = 32'h3f7e1323;
11'd473: sine = 32'h3f7e2b72;
11'd474: sine = 32'h3f7e4323;
11'd475: sine = 32'h3f7e5a38;
11'd476: sine = 32'h3f7e70b0;
11'd477: sine = 32'h3f7e868b;
11'd478: sine = 32'h3f7e9bc9;
11'd479: sine = 32'h3f7eb069;
11'd480: sine = 32'h3f7ec46d;
11'd481: sine = 32'h3f7ed7d4;
11'd482: sine = 32'h3f7eea9d;
11'd483: sine = 32'h3f7efcc9;
11'd484: sine = 32'h3f7f0e58;
11'd485: sine = 32'h3f7f1f49;
11'd486: sine = 32'h3f7f2f9d;
11'd487: sine = 32'h3f7f3f54;
11'd488: sine = 32'h3f7f4e6d;
11'd489: sine = 32'h3f7f5ce9;
11'd490: sine = 32'h3f7f6ac7;
11'd491: sine = 32'h3f7f7808;
11'd492: sine = 32'h3f7f84ab;
11'd493: sine = 32'h3f7f90b1;
11'd494: sine = 32'h3f7f9c18;
11'd495: sine = 32'h3f7fa6e3;
11'd496: sine = 32'h3f7fb10f;
11'd497: sine = 32'h3f7fba9e;
11'd498: sine = 32'h3f7fc38f;
11'd499: sine = 32'h3f7fcbe2;
11'd500: sine = 32'h3f7fd397;
11'd501: sine = 32'h3f7fdaaf;
11'd502: sine = 32'h3f7fe129;
11'd503: sine = 32'h3f7fe705;
11'd504: sine = 32'h3f7fec43;
11'd505: sine = 32'h3f7ff0e3;
11'd506: sine = 32'h3f7ff4e6;
11'd507: sine = 32'h3f7ff84a;
11'd508: sine = 32'h3f7ffb11;
11'd509: sine = 32'h3f7ffd39;
11'd510: sine = 32'h3f7ffec4;
11'd511: sine = 32'h3f7fffb1;
11'd512: sine = 32'h3f800000;
11'd513: sine = 32'h3f7fffb1;
11'd514: sine = 32'h3f7ffec4;
11'd515: sine = 32'h3f7ffd39;
11'd516: sine = 32'h3f7ffb11;
11'd517: sine = 32'h3f7ff84a;
11'd518: sine = 32'h3f7ff4e6;
11'd519: sine = 32'h3f7ff0e3;
11'd520: sine = 32'h3f7fec43;
11'd521: sine = 32'h3f7fe705;
11'd522: sine = 32'h3f7fe129;
11'd523: sine = 32'h3f7fdaaf;
11'd524: sine = 32'h3f7fd398;
11'd525: sine = 32'h3f7fcbe2;
11'd526: sine = 32'h3f7fc38f;
11'd527: sine = 32'h3f7fba9e;
11'd528: sine = 32'h3f7fb10f;
11'd529: sine = 32'h3f7fa6e3;
11'd530: sine = 32'h3f7f9c19;
11'd531: sine = 32'h3f7f90b1;
11'd532: sine = 32'h3f7f84ab;
11'd533: sine = 32'h3f7f7808;
11'd534: sine = 32'h3f7f6ac7;
11'd535: sine = 32'h3f7f5ce9;
11'd536: sine = 32'h3f7f4e6d;
11'd537: sine = 32'h3f7f3f54;
11'd538: sine = 32'h3f7f2f9e;
11'd539: sine = 32'h3f7f1f49;
11'd540: sine = 32'h3f7f0e58;
11'd541: sine = 32'h3f7efcc9;
11'd542: sine = 32'h3f7eea9d;
11'd543: sine = 32'h3f7ed7d4;
11'd544: sine = 32'h3f7ec46d;
11'd545: sine = 32'h3f7eb069;
11'd546: sine = 32'h3f7e9bc9;
11'd547: sine = 32'h3f7e868b;
11'd548: sine = 32'h3f7e70b0;
11'd549: sine = 32'h3f7e5a38;
11'd550: sine = 32'h3f7e4323;
11'd551: sine = 32'h3f7e2b72;
11'd552: sine = 32'h3f7e1324;
11'd553: sine = 32'h3f7dfa39;
11'd554: sine = 32'h3f7de0b1;
11'd555: sine = 32'h3f7dc68c;
11'd556: sine = 32'h3f7dabcc;
11'd557: sine = 32'h3f7d906e;
11'd558: sine = 32'h3f7d7475;
11'd559: sine = 32'h3f7d57de;
11'd560: sine = 32'h3f7d3aac;
11'd561: sine = 32'h3f7d1cdd;
11'd562: sine = 32'h3f7cfe73;
11'd563: sine = 32'h3f7cdf6c;
11'd564: sine = 32'h3f7cbfc9;
11'd565: sine = 32'h3f7c9f8b;
11'd566: sine = 32'h3f7c7eb0;
11'd567: sine = 32'h3f7c5d3a;
11'd568: sine = 32'h3f7c3b28;
11'd569: sine = 32'h3f7c187a;
11'd570: sine = 32'h3f7bf531;
11'd571: sine = 32'h3f7bd14d;
11'd572: sine = 32'h3f7baccd;
11'd573: sine = 32'h3f7b87b2;
11'd574: sine = 32'h3f7b61fc;
11'd575: sine = 32'h3f7b3bab;
11'd576: sine = 32'h3f7b14bf;
11'd577: sine = 32'h3f7aed38;
11'd578: sine = 32'h3f7ac516;
11'd579: sine = 32'h3f7a9c59;
11'd580: sine = 32'h3f7a7302;
11'd581: sine = 32'h3f7a4910;
11'd582: sine = 32'h3f7a1e84;
11'd583: sine = 32'h3f79f35e;
11'd584: sine = 32'h3f79c79d;
11'd585: sine = 32'h3f799b43;
11'd586: sine = 32'h3f796e4e;
11'd587: sine = 32'h3f7940c0;
11'd588: sine = 32'h3f791298;
11'd589: sine = 32'h3f78e3d6;
11'd590: sine = 32'h3f78b47b;
11'd591: sine = 32'h3f788486;
11'd592: sine = 32'h3f7853f8;
11'd593: sine = 32'h3f7822d1;
11'd594: sine = 32'h3f77f111;
11'd595: sine = 32'h3f77beb7;
11'd596: sine = 32'h3f778bc5;
11'd597: sine = 32'h3f77583b;
11'd598: sine = 32'h3f772417;
11'd599: sine = 32'h3f76ef5b;
11'd600: sine = 32'h3f76ba07;
11'd601: sine = 32'h3f76841b;
11'd602: sine = 32'h3f764d97;
11'd603: sine = 32'h3f76167a;
11'd604: sine = 32'h3f75dec6;
11'd605: sine = 32'h3f75a67b;
11'd606: sine = 32'h3f756d97;
11'd607: sine = 32'h3f75341d;
11'd608: sine = 32'h3f74fa0b;
11'd609: sine = 32'h3f74bf62;
11'd610: sine = 32'h3f748422;
11'd611: sine = 32'h3f74484b;
11'd612: sine = 32'h3f740bde;
11'd613: sine = 32'h3f73ced9;
11'd614: sine = 32'h3f73913f;
11'd615: sine = 32'h3f73530e;
11'd616: sine = 32'h3f731448;
11'd617: sine = 32'h3f72d4eb;
11'd618: sine = 32'h3f7294f8;
11'd619: sine = 32'h3f725470;
11'd620: sine = 32'h3f721353;
11'd621: sine = 32'h3f71d1a0;
11'd622: sine = 32'h3f718f57;
11'd623: sine = 32'h3f714c7a;
11'd624: sine = 32'h3f710908;
11'd625: sine = 32'h3f70c502;
11'd626: sine = 32'h3f708067;
11'd627: sine = 32'h3f703b37;
11'd628: sine = 32'h3f6ff573;
11'd629: sine = 32'h3f6faf1c;
11'd630: sine = 32'h3f6f6830;
11'd631: sine = 32'h3f6f20b1;
11'd632: sine = 32'h3f6ed89e;
11'd633: sine = 32'h3f6e8ff8;
11'd634: sine = 32'h3f6e46bf;
11'd635: sine = 32'h3f6dfcf2;
11'd636: sine = 32'h3f6db293;
11'd637: sine = 32'h3f6d67a2;
11'd638: sine = 32'h3f6d1c1e;
11'd639: sine = 32'h3f6cd007;
11'd640: sine = 32'h3f6c835f;
11'd641: sine = 32'h3f6c3624;
11'd642: sine = 32'h3f6be858;
11'd643: sine = 32'h3f6b99fb;
11'd644: sine = 32'h3f6b4b0c;
11'd645: sine = 32'h3f6afb8c;
11'd646: sine = 32'h3f6aab7b;
11'd647: sine = 32'h3f6a5ad9;
11'd648: sine = 32'h3f6a09a7;
11'd649: sine = 32'h3f69b7e4;
11'd650: sine = 32'h3f696591;
11'd651: sine = 32'h3f6912ae;
11'd652: sine = 32'h3f68bf3c;
11'd653: sine = 32'h3f686b3a;
11'd654: sine = 32'h3f6816a8;
11'd655: sine = 32'h3f67c188;
11'd656: sine = 32'h3f676bd8;
11'd657: sine = 32'h3f671599;
11'd658: sine = 32'h3f66becd;
11'd659: sine = 32'h3f666771;
11'd660: sine = 32'h3f660f88;
11'd661: sine = 32'h3f65b711;
11'd662: sine = 32'h3f655e0c;
11'd663: sine = 32'h3f650479;
11'd664: sine = 32'h3f64aa59;
11'd665: sine = 32'h3f644fac;
11'd666: sine = 32'h3f63f473;
11'd667: sine = 32'h3f6398ad;
11'd668: sine = 32'h3f633c5a;
11'd669: sine = 32'h3f62df7b;
11'd670: sine = 32'h3f628210;
11'd671: sine = 32'h3f62241a;
11'd672: sine = 32'h3f61c598;
11'd673: sine = 32'h3f61668b;
11'd674: sine = 32'h3f6106f2;
11'd675: sine = 32'h3f60a6cf;
11'd676: sine = 32'h3f604621;
11'd677: sine = 32'h3f5fe4e9;
11'd678: sine = 32'h3f5f8327;
11'd679: sine = 32'h3f5f20db;
11'd680: sine = 32'h3f5ebe06;
11'd681: sine = 32'h3f5e5aa7;
11'd682: sine = 32'h3f5df6be;
11'd683: sine = 32'h3f5d924d;
11'd684: sine = 32'h3f5d2d54;
11'd685: sine = 32'h3f5cc7d1;
11'd686: sine = 32'h3f5c61c7;
11'd687: sine = 32'h3f5bfb35;
11'd688: sine = 32'h3f5b941a;
11'd689: sine = 32'h3f5b2c79;
11'd690: sine = 32'h3f5ac450;
11'd691: sine = 32'h3f5a5ba1;
11'd692: sine = 32'h3f59f26a;
11'd693: sine = 32'h3f5988ae;
11'd694: sine = 32'h3f591e6b;
11'd695: sine = 32'h3f58b3a2;
11'd696: sine = 32'h3f584853;
11'd697: sine = 32'h3f57dc7f;
11'd698: sine = 32'h3f577026;
11'd699: sine = 32'h3f570348;
11'd700: sine = 32'h3f5695e5;
11'd701: sine = 32'h3f5627fe;
11'd702: sine = 32'h3f55b993;
11'd703: sine = 32'h3f554aa4;
11'd704: sine = 32'h3f54db32;
11'd705: sine = 32'h3f546b3c;
11'd706: sine = 32'h3f53fac3;
11'd707: sine = 32'h3f5389c7;
11'd708: sine = 32'h3f531849;
11'd709: sine = 32'h3f52a649;
11'd710: sine = 32'h3f5233c7;
11'd711: sine = 32'h3f51c0c3;
11'd712: sine = 32'h3f514d3d;
11'd713: sine = 32'h3f50d937;
11'd714: sine = 32'h3f5064b0;
11'd715: sine = 32'h3f4fefa8;
11'd716: sine = 32'h3f4f7a20;
11'd717: sine = 32'h3f4f0418;
11'd718: sine = 32'h3f4e8d90;
11'd719: sine = 32'h3f4e1689;
11'd720: sine = 32'h3f4d9f03;
11'd721: sine = 32'h3f4d26fe;
11'd722: sine = 32'h3f4cae7a;
11'd723: sine = 32'h3f4c3578;
11'd724: sine = 32'h3f4bbbf8;
11'd725: sine = 32'h3f4b41fa;
11'd726: sine = 32'h3f4ac780;
11'd727: sine = 32'h3f4a4c88;
11'd728: sine = 32'h3f49d113;
11'd729: sine = 32'h3f495521;
11'd730: sine = 32'h3f48d8b4;
11'd731: sine = 32'h3f485bcb;
11'd732: sine = 32'h3f47de66;
11'd733: sine = 32'h3f476085;
11'd734: sine = 32'h3f46e22a;
11'd735: sine = 32'h3f466354;
11'd736: sine = 32'h3f45e404;
11'd737: sine = 32'h3f456439;
11'd738: sine = 32'h3f44e3f5;
11'd739: sine = 32'h3f446338;
11'd740: sine = 32'h3f43e201;
11'd741: sine = 32'h3f436051;
11'd742: sine = 32'h3f42de29;
11'd743: sine = 32'h3f425b89;
11'd744: sine = 32'h3f41d871;
11'd745: sine = 32'h3f4154e1;
11'd746: sine = 32'h3f40d0da;
11'd747: sine = 32'h3f404c5c;
11'd748: sine = 32'h3f3fc768;
11'd749: sine = 32'h3f3f41fd;
11'd750: sine = 32'h3f3ebc1c;
11'd751: sine = 32'h3f3e35c5;
11'd752: sine = 32'h3f3daefa;
11'd753: sine = 32'h3f3d27b9;
11'd754: sine = 32'h3f3ca003;
11'd755: sine = 32'h3f3c17d9;
11'd756: sine = 32'h3f3b8f3b;
11'd757: sine = 32'h3f3b062a;
11'd758: sine = 32'h3f3a7ca5;
11'd759: sine = 32'h3f39f2ad;
11'd760: sine = 32'h3f396842;
11'd761: sine = 32'h3f38dd65;
11'd762: sine = 32'h3f385216;
11'd763: sine = 32'h3f37c655;
11'd764: sine = 32'h3f373a23;
11'd765: sine = 32'h3f36ad80;
11'd766: sine = 32'h3f36206c;
11'd767: sine = 32'h3f3592e8;
11'd768: sine = 32'h3f3504f4;
11'd769: sine = 32'h3f347690;
11'd770: sine = 32'h3f33e7bd;
11'd771: sine = 32'h3f33587a;
11'd772: sine = 32'h3f32c8ca;
11'd773: sine = 32'h3f3238ab;
11'd774: sine = 32'h3f31a81e;
11'd775: sine = 32'h3f311723;
11'd776: sine = 32'h3f3085bb;
11'd777: sine = 32'h3f2ff3e6;
11'd778: sine = 32'h3f2f61a5;
11'd779: sine = 32'h3f2ecef8;
11'd780: sine = 32'h3f2e3bde;
11'd781: sine = 32'h3f2da85a;
11'd782: sine = 32'h3f2d146a;
11'd783: sine = 32'h3f2c800f;
11'd784: sine = 32'h3f2beb4a;
11'd785: sine = 32'h3f2b561b;
11'd786: sine = 32'h3f2ac082;
11'd787: sine = 32'h3f2a2a80;
11'd788: sine = 32'h3f299415;
11'd789: sine = 32'h3f28fd41;
11'd790: sine = 32'h3f286606;
11'd791: sine = 32'h3f27ce62;
11'd792: sine = 32'h3f273656;
11'd793: sine = 32'h3f269de4;
11'd794: sine = 32'h3f26050b;
11'd795: sine = 32'h3f256bcb;
11'd796: sine = 32'h3f24d225;
11'd797: sine = 32'h3f24381a;
11'd798: sine = 32'h3f239da9;
11'd799: sine = 32'h3f2302d4;
11'd800: sine = 32'h3f22679a;
11'd801: sine = 32'h3f21cbfb;
11'd802: sine = 32'h3f212ff9;
11'd803: sine = 32'h3f209394;
11'd804: sine = 32'h3f1ff6cb;
11'd805: sine = 32'h3f1f59a0;
11'd806: sine = 32'h3f1ebc12;
11'd807: sine = 32'h3f1e1e23;
11'd808: sine = 32'h3f1d7fd2;
11'd809: sine = 32'h3f1ce120;
11'd810: sine = 32'h3f1c420d;
11'd811: sine = 32'h3f1ba299;
11'd812: sine = 32'h3f1b02c6;
11'd813: sine = 32'h3f1a6293;
11'd814: sine = 32'h3f19c201;
11'd815: sine = 32'h3f192110;
11'd816: sine = 32'h3f187fc0;
11'd817: sine = 32'h3f17de13;
11'd818: sine = 32'h3f173c08;
11'd819: sine = 32'h3f16999f;
11'd820: sine = 32'h3f15f6da;
11'd821: sine = 32'h3f1553b8;
11'd822: sine = 32'h3f14b03a;
11'd823: sine = 32'h3f140c60;
11'd824: sine = 32'h3f13682b;
11'd825: sine = 32'h3f12c39b;
11'd826: sine = 32'h3f121eb0;
11'd827: sine = 32'h3f11796c;
11'd828: sine = 32'h3f10d3cd;
11'd829: sine = 32'h3f102dd6;
11'd830: sine = 32'h3f0f8785;
11'd831: sine = 32'h3f0ee0dc;
11'd832: sine = 32'h3f0e39da;
11'd833: sine = 32'h3f0d9281;
11'd834: sine = 32'h3f0cead1;
11'd835: sine = 32'h3f0c42ca;
11'd836: sine = 32'h3f0b9a6c;
11'd837: sine = 32'h3f0af1b8;
11'd838: sine = 32'h3f0a48ae;
11'd839: sine = 32'h3f099f4f;
11'd840: sine = 32'h3f08f59b;
11'd841: sine = 32'h3f084b93;
11'd842: sine = 32'h3f07a136;
11'd843: sine = 32'h3f06f686;
11'd844: sine = 32'h3f064b83;
11'd845: sine = 32'h3f05a02d;
11'd846: sine = 32'h3f04f484;
11'd847: sine = 32'h3f04488a;
11'd848: sine = 32'h3f039c3d;
11'd849: sine = 32'h3f02efa0;
11'd850: sine = 32'h3f0242b2;
11'd851: sine = 32'h3f019573;
11'd852: sine = 32'h3f00e7e5;
11'd853: sine = 32'h3f003a07;
11'd854: sine = 32'h3eff17b4;
11'd855: sine = 32'h3efdbabc;
11'd856: sine = 32'h3efc5d28;
11'd857: sine = 32'h3efafef9;
11'd858: sine = 32'h3ef9a02e;
11'd859: sine = 32'h3ef840ca;
11'd860: sine = 32'h3ef6e0cc;
11'd861: sine = 32'h3ef58036;
11'd862: sine = 32'h3ef41f09;
11'd863: sine = 32'h3ef2bd45;
11'd864: sine = 32'h3ef15aeb;
11'd865: sine = 32'h3eeff7fd;
11'd866: sine = 32'h3eee947a;
11'd867: sine = 32'h3eed3064;
11'd868: sine = 32'h3eebcbbc;
11'd869: sine = 32'h3eea6683;
11'd870: sine = 32'h3ee900b9;
11'd871: sine = 32'h3ee79a5f;
11'd872: sine = 32'h3ee63376;
11'd873: sine = 32'h3ee4cbff;
11'd874: sine = 32'h3ee363fc;
11'd875: sine = 32'h3ee1fb6c;
11'd876: sine = 32'h3ee09250;
11'd877: sine = 32'h3edf28aa;
11'd878: sine = 32'h3eddbe7a;
11'd879: sine = 32'h3edc53c2;
11'd880: sine = 32'h3edae882;
11'd881: sine = 32'h3ed97cba;
11'd882: sine = 32'h3ed8106d;
11'd883: sine = 32'h3ed6a39a;
11'd884: sine = 32'h3ed53643;
11'd885: sine = 32'h3ed3c868;
11'd886: sine = 32'h3ed25a0b;
11'd887: sine = 32'h3ed0eb2c;
11'd888: sine = 32'h3ecf7bcc;
11'd889: sine = 32'h3ece0bec;
11'd890: sine = 32'h3ecc9b8c;
11'd891: sine = 32'h3ecb2aaf;
11'd892: sine = 32'h3ec9b955;
11'd893: sine = 32'h3ec8477e;
11'd894: sine = 32'h3ec6d52b;
11'd895: sine = 32'h3ec5625e;
11'd896: sine = 32'h3ec3ef17;
11'd897: sine = 32'h3ec27b57;
11'd898: sine = 32'h3ec1071f;
11'd899: sine = 32'h3ebf9270;
11'd900: sine = 32'h3ebe1d4b;
11'd901: sine = 32'h3ebca7b1;
11'd902: sine = 32'h3ebb31a2;
11'd903: sine = 32'h3eb9bb20;
11'd904: sine = 32'h3eb8442b;
11'd905: sine = 32'h3eb6ccc5;
11'd906: sine = 32'h3eb554ed;
11'd907: sine = 32'h3eb3dca6;
11'd908: sine = 32'h3eb263f0;
11'd909: sine = 32'h3eb0eacc;
11'd910: sine = 32'h3eaf713b;
11'd911: sine = 32'h3eadf73e;
11'd912: sine = 32'h3eac7cd5;
11'd913: sine = 32'h3eab0202;
11'd914: sine = 32'h3ea986c6;
11'd915: sine = 32'h3ea80b20;
11'd916: sine = 32'h3ea68f14;
11'd917: sine = 32'h3ea512a0;
11'd918: sine = 32'h3ea395c7;
11'd919: sine = 32'h3ea21888;
11'd920: sine = 32'h3ea09ae6;
11'd921: sine = 32'h3e9f1ce1;
11'd922: sine = 32'h3e9d9e79;
11'd923: sine = 32'h3e9c1fb1;
11'd924: sine = 32'h3e9aa088;
11'd925: sine = 32'h3e9920ff;
11'd926: sine = 32'h3e97a118;
11'd927: sine = 32'h3e9620d4;
11'd928: sine = 32'h3e94a033;
11'd929: sine = 32'h3e931f36;
11'd930: sine = 32'h3e919ddf;
11'd931: sine = 32'h3e901c2e;
11'd932: sine = 32'h3e8e9a24;
11'd933: sine = 32'h3e8d17c1;
11'd934: sine = 32'h3e8b9508;
11'd935: sine = 32'h3e8a11f9;
11'd936: sine = 32'h3e888e95;
11'd937: sine = 32'h3e870adc;
11'd938: sine = 32'h3e8586d0;
11'd939: sine = 32'h3e840272;
11'd940: sine = 32'h3e827dc2;
11'd941: sine = 32'h3e80f8c2;
11'd942: sine = 32'h3e7ee6e4;
11'd943: sine = 32'h3e7bdba7;
11'd944: sine = 32'h3e78cfcf;
11'd945: sine = 32'h3e75c35d;
11'd946: sine = 32'h3e72b654;
11'd947: sine = 32'h3e6fa8b5;
11'd948: sine = 32'h3e6c9a82;
11'd949: sine = 32'h3e698bbe;
11'd950: sine = 32'h3e667c69;
11'd951: sine = 32'h3e636c86;
11'd952: sine = 32'h3e605c17;
11'd953: sine = 32'h3e5d4b1d;
11'd954: sine = 32'h3e5a399b;
11'd955: sine = 32'h3e572792;
11'd956: sine = 32'h3e541504;
11'd957: sine = 32'h3e5101f4;
11'd958: sine = 32'h3e4dee63;
11'd959: sine = 32'h3e4ada53;
11'd960: sine = 32'h3e47c5c5;
11'd961: sine = 32'h3e44b0bd;
11'd962: sine = 32'h3e419b3b;
11'd963: sine = 32'h3e3e8541;
11'd964: sine = 32'h3e3b6ed2;
11'd965: sine = 32'h3e3857f0;
11'd966: sine = 32'h3e35409b;
11'd967: sine = 32'h3e3228d7;
11'd968: sine = 32'h3e2f10a5;
11'd969: sine = 32'h3e2bf808;
11'd970: sine = 32'h3e28df00;
11'd971: sine = 32'h3e25c58f;
11'd972: sine = 32'h3e22abb9;
11'd973: sine = 32'h3e1f917e;
11'd974: sine = 32'h3e1c76e1;
11'd975: sine = 32'h3e195be3;
11'd976: sine = 32'h3e164087;
11'd977: sine = 32'h3e1324ce;
11'd978: sine = 32'h3e1008ba;
11'd979: sine = 32'h3e0cec4d;
11'd980: sine = 32'h3e09cf8a;
11'd981: sine = 32'h3e06b271;
11'd982: sine = 32'h3e039506;
11'd983: sine = 32'h3e007749;
11'd984: sine = 32'h3dfab27a;
11'd985: sine = 32'h3df475c7;
11'd986: sine = 32'h3dee387d;
11'd987: sine = 32'h3de7faa1;
11'd988: sine = 32'h3de1bc35;
11'd989: sine = 32'h3ddb7d3e;
11'd990: sine = 32'h3dd53dc0;
11'd991: sine = 32'h3dcefdbe;
11'd992: sine = 32'h3dc8bd3d;
11'd993: sine = 32'h3dc27c40;
11'd994: sine = 32'h3dbc3aca;
11'd995: sine = 32'h3db5f8e1;
11'd996: sine = 32'h3dafb687;
11'd997: sine = 32'h3da973c1;
11'd998: sine = 32'h3da33093;
11'd999: sine = 32'h3d9ced00;
11'd1000: sine = 32'h3d96a90c;
11'd1001: sine = 32'h3d9064bb;
11'd1002: sine = 32'h3d8a2011;
11'd1003: sine = 32'h3d83db11;
11'd1004: sine = 32'h3d7b2b82;
11'd1005: sine = 32'h3d6ea046;
11'd1006: sine = 32'h3d621477;
11'd1007: sine = 32'h3d55881c;
11'd1008: sine = 32'h3d48fb3e;
11'd1009: sine = 32'h3d3c6de3;
11'd1010: sine = 32'h3d2fe015;
11'd1011: sine = 32'h3d2351da;
11'd1012: sine = 32'h3d16c33a;
11'd1013: sine = 32'h3d0a343d;
11'd1014: sine = 32'h3cfb49d6;
11'd1015: sine = 32'h3ce22a97;
11'd1016: sine = 32'h3cc90acc;
11'd1017: sine = 32'h3cafea86;
11'd1018: sine = 32'h3c96c9d2;
11'd1019: sine = 32'h3c7b5185;
11'd1020: sine = 32'h3c490ec9;
11'd1021: sine = 32'h3c16cb92;
11'd1022: sine = 32'h3bc90ffb;
11'd1023: sine = 32'h3b4910ac;
11'd1024: sine = 32'h33662a9a;
11'd1025: sine = 32'hbb490ee0;
11'd1026: sine = 32'hbbc90f15;
11'd1027: sine = 32'hbc16cb1f;
11'd1028: sine = 32'hbc490e56;
11'd1029: sine = 32'hbc7b5112;
11'd1030: sine = 32'hbc96c999;
11'd1031: sine = 32'hbcafea4c;
11'd1032: sine = 32'hbcc90a93;
11'd1033: sine = 32'hbce22a5d;
11'd1034: sine = 32'hbcfb499d;
11'd1035: sine = 32'hbd0a3420;
11'd1036: sine = 32'hbd16c31d;
11'd1037: sine = 32'hbd2351bd;
11'd1038: sine = 32'hbd2fdff8;
11'd1039: sine = 32'hbd3c6dc7;
11'd1040: sine = 32'hbd48fb21;
11'd1041: sine = 32'hbd5587ff;
11'd1042: sine = 32'hbd62145a;
11'd1043: sine = 32'hbd6ea029;
11'd1044: sine = 32'hbd7b2b65;
11'd1045: sine = 32'hbd83db03;
11'd1046: sine = 32'hbd8a2002;
11'd1047: sine = 32'hbd9064ac;
11'd1048: sine = 32'hbd96a8fd;
11'd1049: sine = 32'hbd9cecf1;
11'd1050: sine = 32'hbda33084;
11'd1051: sine = 32'hbda973b3;
11'd1052: sine = 32'hbdafb679;
11'd1053: sine = 32'hbdb5f8d3;
11'd1054: sine = 32'hbdbc3abc;
11'd1055: sine = 32'hbdc27c31;
11'd1056: sine = 32'hbdc8bd2e;
11'd1057: sine = 32'hbdcefdb0;
11'd1058: sine = 32'hbdd53db2;
11'd1059: sine = 32'hbddb7d30;
11'd1060: sine = 32'hbde1bc27;
11'd1061: sine = 32'hbde7fa92;
11'd1062: sine = 32'hbdee386f;
11'd1063: sine = 32'hbdf475b9;
11'd1064: sine = 32'hbdfab26b;
11'd1065: sine = 32'hbe007742;
11'd1066: sine = 32'hbe0394ff;
11'd1067: sine = 32'hbe06b26a;
11'd1068: sine = 32'hbe09cf83;
11'd1069: sine = 32'hbe0cec46;
11'd1070: sine = 32'hbe1008b3;
11'd1071: sine = 32'hbe1324c7;
11'd1072: sine = 32'hbe164080;
11'd1073: sine = 32'hbe195bdc;
11'd1074: sine = 32'hbe1c76da;
11'd1075: sine = 32'hbe1f9177;
11'd1076: sine = 32'hbe22abb2;
11'd1077: sine = 32'hbe25c588;
11'd1078: sine = 32'hbe28def8;
11'd1079: sine = 32'hbe2bf800;
11'd1080: sine = 32'hbe2f109e;
11'd1081: sine = 32'hbe3228d0;
11'd1082: sine = 32'hbe354094;
11'd1083: sine = 32'hbe3857e9;
11'd1084: sine = 32'hbe3b6ecb;
11'd1085: sine = 32'hbe3e853a;
11'd1086: sine = 32'hbe419b34;
11'd1087: sine = 32'hbe44b0b5;
11'd1088: sine = 32'hbe47c5be;
11'd1089: sine = 32'hbe4ada4c;
11'd1090: sine = 32'hbe4dee5c;
11'd1091: sine = 32'hbe5101ed;
11'd1092: sine = 32'hbe5414fd;
11'd1093: sine = 32'hbe57278b;
11'd1094: sine = 32'hbe5a3994;
11'd1095: sine = 32'hbe5d4b16;
11'd1096: sine = 32'hbe605c10;
11'd1097: sine = 32'hbe636c7f;
11'd1098: sine = 32'hbe667c62;
11'd1099: sine = 32'hbe698bb7;
11'd1100: sine = 32'hbe6c9a7b;
11'd1101: sine = 32'hbe6fa8ae;
11'd1102: sine = 32'hbe72b64d;
11'd1103: sine = 32'hbe75c356;
11'd1104: sine = 32'hbe78cfc8;
11'd1105: sine = 32'hbe7bdba0;
11'd1106: sine = 32'hbe7ee6dd;
11'd1107: sine = 32'hbe80f8be;
11'd1108: sine = 32'hbe827dbf;
11'd1109: sine = 32'hbe84026e;
11'd1110: sine = 32'hbe8586cd;
11'd1111: sine = 32'hbe870ad9;
11'd1112: sine = 32'hbe888e91;
11'd1113: sine = 32'hbe8a11f6;
11'd1114: sine = 32'hbe8b9505;
11'd1115: sine = 32'hbe8d17be;
11'd1116: sine = 32'hbe8e9a20;
11'd1117: sine = 32'hbe901c2a;
11'd1118: sine = 32'hbe919ddb;
11'd1119: sine = 32'hbe931f33;
11'd1120: sine = 32'hbe94a030;
11'd1121: sine = 32'hbe9620d1;
11'd1122: sine = 32'hbe97a115;
11'd1123: sine = 32'hbe9920fc;
11'd1124: sine = 32'hbe9aa084;
11'd1125: sine = 32'hbe9c1fad;
11'd1126: sine = 32'hbe9d9e76;
11'd1127: sine = 32'hbe9f1cdd;
11'd1128: sine = 32'hbea09ae3;
11'd1129: sine = 32'hbea21885;
11'd1130: sine = 32'hbea395c3;
11'd1131: sine = 32'hbea5129d;
11'd1132: sine = 32'hbea68f10;
11'd1133: sine = 32'hbea80b1d;
11'd1134: sine = 32'hbea986c2;
11'd1135: sine = 32'hbeab01ff;
11'd1136: sine = 32'hbeac7cd2;
11'd1137: sine = 32'hbeadf73a;
11'd1138: sine = 32'hbeaf7138;
11'd1139: sine = 32'hbeb0eac9;
11'd1140: sine = 32'hbeb263ed;
11'd1141: sine = 32'hbeb3dca3;
11'd1142: sine = 32'hbeb554ea;
11'd1143: sine = 32'hbeb6ccc1;
11'd1144: sine = 32'hbeb84428;
11'd1145: sine = 32'hbeb9bb1c;
11'd1146: sine = 32'hbebb319f;
11'd1147: sine = 32'hbebca7ad;
11'd1148: sine = 32'hbebe1d48;
11'd1149: sine = 32'hbebf926d;
11'd1150: sine = 32'hbec1071c;
11'd1151: sine = 32'hbec27b53;
11'd1152: sine = 32'hbec3ef13;
11'd1153: sine = 32'hbec5625a;
11'd1154: sine = 32'hbec6d528;
11'd1155: sine = 32'hbec8477a;
11'd1156: sine = 32'hbec9b951;
11'd1157: sine = 32'hbecb2aac;
11'd1158: sine = 32'hbecc9b89;
11'd1159: sine = 32'hbece0be8;
11'd1160: sine = 32'hbecf7bc8;
11'd1161: sine = 32'hbed0eb28;
11'd1162: sine = 32'hbed25a07;
11'd1163: sine = 32'hbed3c865;
11'd1164: sine = 32'hbed5363f;
11'd1165: sine = 32'hbed6a397;
11'd1166: sine = 32'hbed8106a;
11'd1167: sine = 32'hbed97cb7;
11'd1168: sine = 32'hbedae87e;
11'd1169: sine = 32'hbedc53bf;
11'd1170: sine = 32'hbeddbe77;
11'd1171: sine = 32'hbedf28a7;
11'd1172: sine = 32'hbee0924d;
11'd1173: sine = 32'hbee1fb68;
11'd1174: sine = 32'hbee363f8;
11'd1175: sine = 32'hbee4cbfc;
11'd1176: sine = 32'hbee63373;
11'd1177: sine = 32'hbee79a5c;
11'd1178: sine = 32'hbee900b5;
11'd1179: sine = 32'hbeea6680;
11'd1180: sine = 32'hbeebcbb9;
11'd1181: sine = 32'hbeed3061;
11'd1182: sine = 32'hbeee9477;
11'd1183: sine = 32'hbeeff7f9;
11'd1184: sine = 32'hbef15ae8;
11'd1185: sine = 32'hbef2bd42;
11'd1186: sine = 32'hbef41f06;
11'd1187: sine = 32'hbef58033;
11'd1188: sine = 32'hbef6e0c9;
11'd1189: sine = 32'hbef840c6;
11'd1190: sine = 32'hbef9a02b;
11'd1191: sine = 32'hbefafef5;
11'd1192: sine = 32'hbefc5d25;
11'd1193: sine = 32'hbefdbab9;
11'd1194: sine = 32'hbeff17b1;
11'd1195: sine = 32'hbf003a05;
11'd1196: sine = 32'hbf00e7e3;
11'd1197: sine = 32'hbf019572;
11'd1198: sine = 32'hbf0242b0;
11'd1199: sine = 32'hbf02ef9e;
11'd1200: sine = 32'hbf039c3c;
11'd1201: sine = 32'hbf044888;
11'd1202: sine = 32'hbf04f483;
11'd1203: sine = 32'hbf05a02b;
11'd1204: sine = 32'hbf064b82;
11'd1205: sine = 32'hbf06f685;
11'd1206: sine = 32'hbf07a135;
11'd1207: sine = 32'hbf084b91;
11'd1208: sine = 32'hbf08f59a;
11'd1209: sine = 32'hbf099f4e;
11'd1210: sine = 32'hbf0a48ad;
11'd1211: sine = 32'hbf0af1b6;
11'd1212: sine = 32'hbf0b9a6a;
11'd1213: sine = 32'hbf0c42c8;
11'd1214: sine = 32'hbf0ceacf;
11'd1215: sine = 32'hbf0d9280;
11'd1216: sine = 32'hbf0e39d9;
11'd1217: sine = 32'hbf0ee0da;
11'd1218: sine = 32'hbf0f8783;
11'd1219: sine = 32'hbf102dd4;
11'd1220: sine = 32'hbf10d3cc;
11'd1221: sine = 32'hbf11796a;
11'd1222: sine = 32'hbf121eaf;
11'd1223: sine = 32'hbf12c39a;
11'd1224: sine = 32'hbf13682a;
11'd1225: sine = 32'hbf140c5f;
11'd1226: sine = 32'hbf14b038;
11'd1227: sine = 32'hbf1553b6;
11'd1228: sine = 32'hbf15f6d8;
11'd1229: sine = 32'hbf16999e;
11'd1230: sine = 32'hbf173c06;
11'd1231: sine = 32'hbf17de11;
11'd1232: sine = 32'hbf187fbf;
11'd1233: sine = 32'hbf19210f;
11'd1234: sine = 32'hbf19c200;
11'd1235: sine = 32'hbf1a6292;
11'd1236: sine = 32'hbf1b02c5;
11'd1237: sine = 32'hbf1ba298;
11'd1238: sine = 32'hbf1c420b;
11'd1239: sine = 32'hbf1ce11e;
11'd1240: sine = 32'hbf1d7fd0;
11'd1241: sine = 32'hbf1e1e21;
11'd1242: sine = 32'hbf1ebc11;
11'd1243: sine = 32'hbf1f599e;
11'd1244: sine = 32'hbf1ff6ca;
11'd1245: sine = 32'hbf209392;
11'd1246: sine = 32'hbf212ff8;
11'd1247: sine = 32'hbf21cbfa;
11'd1248: sine = 32'hbf226798;
11'd1249: sine = 32'hbf2302d2;
11'd1250: sine = 32'hbf239da8;
11'd1251: sine = 32'hbf243819;
11'd1252: sine = 32'hbf24d224;
11'd1253: sine = 32'hbf256bca;
11'd1254: sine = 32'hbf260509;
11'd1255: sine = 32'hbf269de3;
11'd1256: sine = 32'hbf273655;
11'd1257: sine = 32'hbf27ce60;
11'd1258: sine = 32'hbf286604;
11'd1259: sine = 32'hbf28fd40;
11'd1260: sine = 32'hbf299414;
11'd1261: sine = 32'hbf2a2a7f;
11'd1262: sine = 32'hbf2ac081;
11'd1263: sine = 32'hbf2b561a;
11'd1264: sine = 32'hbf2beb49;
11'd1265: sine = 32'hbf2c800e;
11'd1266: sine = 32'hbf2d1469;
11'd1267: sine = 32'hbf2da858;
11'd1268: sine = 32'hbf2e3bdd;
11'd1269: sine = 32'hbf2ecef6;
11'd1270: sine = 32'hbf2f61a4;
11'd1271: sine = 32'hbf2ff3e5;
11'd1272: sine = 32'hbf3085ba;
11'd1273: sine = 32'hbf311722;
11'd1274: sine = 32'hbf31a81c;
11'd1275: sine = 32'hbf3238a9;
11'd1276: sine = 32'hbf32c8c8;
11'd1277: sine = 32'hbf335879;
11'd1278: sine = 32'hbf33e7bb;
11'd1279: sine = 32'hbf34768f;
11'd1280: sine = 32'hbf3504f2;
11'd1281: sine = 32'hbf3592e7;
11'd1282: sine = 32'hbf36206b;
11'd1283: sine = 32'hbf36ad7f;
11'd1284: sine = 32'hbf373a22;
11'd1285: sine = 32'hbf37c654;
11'd1286: sine = 32'hbf385215;
11'd1287: sine = 32'hbf38dd64;
11'd1288: sine = 32'hbf396841;
11'd1289: sine = 32'hbf39f2ac;
11'd1290: sine = 32'hbf3a7ca4;
11'd1291: sine = 32'hbf3b0629;
11'd1292: sine = 32'hbf3b8f3a;
11'd1293: sine = 32'hbf3c17d8;
11'd1294: sine = 32'hbf3ca002;
11'd1295: sine = 32'hbf3d27b7;
11'd1296: sine = 32'hbf3daef8;
11'd1297: sine = 32'hbf3e35c4;
11'd1298: sine = 32'hbf3ebc1b;
11'd1299: sine = 32'hbf3f41fb;
11'd1300: sine = 32'hbf3fc766;
11'd1301: sine = 32'hbf404c5b;
11'd1302: sine = 32'hbf40d0d9;
11'd1303: sine = 32'hbf4154e0;
11'd1304: sine = 32'hbf41d870;
11'd1305: sine = 32'hbf425b88;
11'd1306: sine = 32'hbf42de28;
11'd1307: sine = 32'hbf436050;
11'd1308: sine = 32'hbf43e200;
11'd1309: sine = 32'hbf446336;
11'd1310: sine = 32'hbf44e3f4;
11'd1311: sine = 32'hbf456438;
11'd1312: sine = 32'hbf45e403;
11'd1313: sine = 32'hbf466353;
11'd1314: sine = 32'hbf46e229;
11'd1315: sine = 32'hbf476084;
11'd1316: sine = 32'hbf47de64;
11'd1317: sine = 32'hbf485bc9;
11'd1318: sine = 32'hbf48d8b3;
11'd1319: sine = 32'hbf495520;
11'd1320: sine = 32'hbf49d112;
11'd1321: sine = 32'hbf4a4c86;
11'd1322: sine = 32'hbf4ac77e;
11'd1323: sine = 32'hbf4b41f9;
11'd1324: sine = 32'hbf4bbbf7;
11'd1325: sine = 32'hbf4c3577;
11'd1326: sine = 32'hbf4cae79;
11'd1327: sine = 32'hbf4d26fc;
11'd1328: sine = 32'hbf4d9f02;
11'd1329: sine = 32'hbf4e1688;
11'd1330: sine = 32'hbf4e8d8f;
11'd1331: sine = 32'hbf4f0417;
11'd1332: sine = 32'hbf4f7a1f;
11'd1333: sine = 32'hbf4fefa7;
11'd1334: sine = 32'hbf5064af;
11'd1335: sine = 32'hbf50d936;
11'd1336: sine = 32'hbf514d3c;
11'd1337: sine = 32'hbf51c0c2;
11'd1338: sine = 32'hbf5233c6;
11'd1339: sine = 32'hbf52a648;
11'd1340: sine = 32'hbf531848;
11'd1341: sine = 32'hbf5389c6;
11'd1342: sine = 32'hbf53fac2;
11'd1343: sine = 32'hbf546b3b;
11'd1344: sine = 32'hbf54db31;
11'd1345: sine = 32'hbf554aa3;
11'd1346: sine = 32'hbf55b992;
11'd1347: sine = 32'hbf5627fd;
11'd1348: sine = 32'hbf5695e4;
11'd1349: sine = 32'hbf570347;
11'd1350: sine = 32'hbf577025;
11'd1351: sine = 32'hbf57dc7e;
11'd1352: sine = 32'hbf584852;
11'd1353: sine = 32'hbf58b3a1;
11'd1354: sine = 32'hbf591e6a;
11'd1355: sine = 32'hbf5988ad;
11'd1356: sine = 32'hbf59f269;
11'd1357: sine = 32'hbf5a5ba0;
11'd1358: sine = 32'hbf5ac44f;
11'd1359: sine = 32'hbf5b2c78;
11'd1360: sine = 32'hbf5b941a;
11'd1361: sine = 32'hbf5bfb34;
11'd1362: sine = 32'hbf5c61c6;
11'd1363: sine = 32'hbf5cc7d0;
11'd1364: sine = 32'hbf5d2d53;
11'd1365: sine = 32'hbf5d924c;
11'd1366: sine = 32'hbf5df6be;
11'd1367: sine = 32'hbf5e5aa6;
11'd1368: sine = 32'hbf5ebe05;
11'd1369: sine = 32'hbf5f20da;
11'd1370: sine = 32'hbf5f8326;
11'd1371: sine = 32'hbf5fe4e9;
11'd1372: sine = 32'hbf604621;
11'd1373: sine = 32'hbf60a6ce;
11'd1374: sine = 32'hbf6106f1;
11'd1375: sine = 32'hbf61668a;
11'd1376: sine = 32'hbf61c597;
11'd1377: sine = 32'hbf622419;
11'd1378: sine = 32'hbf62820f;
11'd1379: sine = 32'hbf62df7a;
11'd1380: sine = 32'hbf633c59;
11'd1381: sine = 32'hbf6398ac;
11'd1382: sine = 32'hbf63f472;
11'd1383: sine = 32'hbf644fac;
11'd1384: sine = 32'hbf64aa58;
11'd1385: sine = 32'hbf650478;
11'd1386: sine = 32'hbf655e0b;
11'd1387: sine = 32'hbf65b710;
11'd1388: sine = 32'hbf660f87;
11'd1389: sine = 32'hbf666770;
11'd1390: sine = 32'hbf66becc;
11'd1391: sine = 32'hbf671599;
11'd1392: sine = 32'hbf676bd7;
11'd1393: sine = 32'hbf67c187;
11'd1394: sine = 32'hbf6816a7;
11'd1395: sine = 32'hbf686b39;
11'd1396: sine = 32'hbf68bf3b;
11'd1397: sine = 32'hbf6912ae;
11'd1398: sine = 32'hbf696591;
11'd1399: sine = 32'hbf69b7e3;
11'd1400: sine = 32'hbf6a09a6;
11'd1401: sine = 32'hbf6a5ad8;
11'd1402: sine = 32'hbf6aab7a;
11'd1403: sine = 32'hbf6afb8b;
11'd1404: sine = 32'hbf6b4b0b;
11'd1405: sine = 32'hbf6b99fa;
11'd1406: sine = 32'hbf6be858;
11'd1407: sine = 32'hbf6c3624;
11'd1408: sine = 32'hbf6c835e;
11'd1409: sine = 32'hbf6cd006;
11'd1410: sine = 32'hbf6d1c1d;
11'd1411: sine = 32'hbf6d67a1;
11'd1412: sine = 32'hbf6db293;
11'd1413: sine = 32'hbf6dfcf2;
11'd1414: sine = 32'hbf6e46be;
11'd1415: sine = 32'hbf6e8ff7;
11'd1416: sine = 32'hbf6ed89d;
11'd1417: sine = 32'hbf6f20b0;
11'd1418: sine = 32'hbf6f682f;
11'd1419: sine = 32'hbf6faf1b;
11'd1420: sine = 32'hbf6ff573;
11'd1421: sine = 32'hbf703b36;
11'd1422: sine = 32'hbf708066;
11'd1423: sine = 32'hbf70c501;
11'd1424: sine = 32'hbf710908;
11'd1425: sine = 32'hbf714c7a;
11'd1426: sine = 32'hbf718f57;
11'd1427: sine = 32'hbf71d19f;
11'd1428: sine = 32'hbf721352;
11'd1429: sine = 32'hbf725470;
11'd1430: sine = 32'hbf7294f8;
11'd1431: sine = 32'hbf72d4ea;
11'd1432: sine = 32'hbf731447;
11'd1433: sine = 32'hbf73530e;
11'd1434: sine = 32'hbf73913e;
11'd1435: sine = 32'hbf73ced9;
11'd1436: sine = 32'hbf740bdd;
11'd1437: sine = 32'hbf74484a;
11'd1438: sine = 32'hbf748421;
11'd1439: sine = 32'hbf74bf61;
11'd1440: sine = 32'hbf74fa0a;
11'd1441: sine = 32'hbf75341c;
11'd1442: sine = 32'hbf756d97;
11'd1443: sine = 32'hbf75a67a;
11'd1444: sine = 32'hbf75dec6;
11'd1445: sine = 32'hbf76167a;
11'd1446: sine = 32'hbf764d96;
11'd1447: sine = 32'hbf76841b;
11'd1448: sine = 32'hbf76ba07;
11'd1449: sine = 32'hbf76ef5b;
11'd1450: sine = 32'hbf772417;
11'd1451: sine = 32'hbf77583a;
11'd1452: sine = 32'hbf778bc5;
11'd1453: sine = 32'hbf77beb7;
11'd1454: sine = 32'hbf77f110;
11'd1455: sine = 32'hbf7822d0;
11'd1456: sine = 32'hbf7853f8;
11'd1457: sine = 32'hbf788486;
11'd1458: sine = 32'hbf78b47a;
11'd1459: sine = 32'hbf78e3d6;
11'd1460: sine = 32'hbf791297;
11'd1461: sine = 32'hbf7940c0;
11'd1462: sine = 32'hbf796e4e;
11'd1463: sine = 32'hbf799b43;
11'd1464: sine = 32'hbf79c79d;
11'd1465: sine = 32'hbf79f35e;
11'd1466: sine = 32'hbf7a1e84;
11'd1467: sine = 32'hbf7a4910;
11'd1468: sine = 32'hbf7a7302;
11'd1469: sine = 32'hbf7a9c59;
11'd1470: sine = 32'hbf7ac515;
11'd1471: sine = 32'hbf7aed37;
11'd1472: sine = 32'hbf7b14be;
11'd1473: sine = 32'hbf7b3baa;
11'd1474: sine = 32'hbf7b61fc;
11'd1475: sine = 32'hbf7b87b2;
11'd1476: sine = 32'hbf7baccd;
11'd1477: sine = 32'hbf7bd14d;
11'd1478: sine = 32'hbf7bf531;
11'd1479: sine = 32'hbf7c187a;
11'd1480: sine = 32'hbf7c3b28;
11'd1481: sine = 32'hbf7c5d3a;
11'd1482: sine = 32'hbf7c7eb0;
11'd1483: sine = 32'hbf7c9f8a;
11'd1484: sine = 32'hbf7cbfc9;
11'd1485: sine = 32'hbf7cdf6c;
11'd1486: sine = 32'hbf7cfe72;
11'd1487: sine = 32'hbf7d1cdd;
11'd1488: sine = 32'hbf7d3aac;
11'd1489: sine = 32'hbf7d57de;
11'd1490: sine = 32'hbf7d7474;
11'd1491: sine = 32'hbf7d906e;
11'd1492: sine = 32'hbf7dabcb;
11'd1493: sine = 32'hbf7dc68c;
11'd1494: sine = 32'hbf7de0b1;
11'd1495: sine = 32'hbf7dfa38;
11'd1496: sine = 32'hbf7e1323;
11'd1497: sine = 32'hbf7e2b72;
11'd1498: sine = 32'hbf7e4323;
11'd1499: sine = 32'hbf7e5a38;
11'd1500: sine = 32'hbf7e70b0;
11'd1501: sine = 32'hbf7e868b;
11'd1502: sine = 32'hbf7e9bc8;
11'd1503: sine = 32'hbf7eb069;
11'd1504: sine = 32'hbf7ec46d;
11'd1505: sine = 32'hbf7ed7d4;
11'd1506: sine = 32'hbf7eea9d;
11'd1507: sine = 32'hbf7efcc9;
11'd1508: sine = 32'hbf7f0e58;
11'd1509: sine = 32'hbf7f1f49;
11'd1510: sine = 32'hbf7f2f9d;
11'd1511: sine = 32'hbf7f3f54;
11'd1512: sine = 32'hbf7f4e6d;
11'd1513: sine = 32'hbf7f5ce9;
11'd1514: sine = 32'hbf7f6ac7;
11'd1515: sine = 32'hbf7f7808;
11'd1516: sine = 32'hbf7f84ab;
11'd1517: sine = 32'hbf7f90b1;
11'd1518: sine = 32'hbf7f9c18;
11'd1519: sine = 32'hbf7fa6e3;
11'd1520: sine = 32'hbf7fb10f;
11'd1521: sine = 32'hbf7fba9e;
11'd1522: sine = 32'hbf7fc38f;
11'd1523: sine = 32'hbf7fcbe2;
11'd1524: sine = 32'hbf7fd397;
11'd1525: sine = 32'hbf7fdaaf;
11'd1526: sine = 32'hbf7fe129;
11'd1527: sine = 32'hbf7fe705;
11'd1528: sine = 32'hbf7fec43;
11'd1529: sine = 32'hbf7ff0e3;
11'd1530: sine = 32'hbf7ff4e6;
11'd1531: sine = 32'hbf7ff84a;
11'd1532: sine = 32'hbf7ffb11;
11'd1533: sine = 32'hbf7ffd39;
11'd1534: sine = 32'hbf7ffec4;
11'd1535: sine = 32'hbf7fffb1;
11'd1536: sine = 32'hbf800000;
11'd1537: sine = 32'hbf7fffb1;
11'd1538: sine = 32'hbf7ffec4;
11'd1539: sine = 32'hbf7ffd39;
11'd1540: sine = 32'hbf7ffb11;
11'd1541: sine = 32'hbf7ff84a;
11'd1542: sine = 32'hbf7ff4e6;
11'd1543: sine = 32'hbf7ff0e3;
11'd1544: sine = 32'hbf7fec43;
11'd1545: sine = 32'hbf7fe705;
11'd1546: sine = 32'hbf7fe129;
11'd1547: sine = 32'hbf7fdaaf;
11'd1548: sine = 32'hbf7fd398;
11'd1549: sine = 32'hbf7fcbe2;
11'd1550: sine = 32'hbf7fc38f;
11'd1551: sine = 32'hbf7fba9e;
11'd1552: sine = 32'hbf7fb10f;
11'd1553: sine = 32'hbf7fa6e3;
11'd1554: sine = 32'hbf7f9c19;
11'd1555: sine = 32'hbf7f90b1;
11'd1556: sine = 32'hbf7f84ab;
11'd1557: sine = 32'hbf7f7808;
11'd1558: sine = 32'hbf7f6ac7;
11'd1559: sine = 32'hbf7f5ce9;
11'd1560: sine = 32'hbf7f4e6e;
11'd1561: sine = 32'hbf7f3f54;
11'd1562: sine = 32'hbf7f2f9e;
11'd1563: sine = 32'hbf7f1f49;
11'd1564: sine = 32'hbf7f0e58;
11'd1565: sine = 32'hbf7efcc9;
11'd1566: sine = 32'hbf7eea9d;
11'd1567: sine = 32'hbf7ed7d4;
11'd1568: sine = 32'hbf7ec46d;
11'd1569: sine = 32'hbf7eb06a;
11'd1570: sine = 32'hbf7e9bc9;
11'd1571: sine = 32'hbf7e868b;
11'd1572: sine = 32'hbf7e70b0;
11'd1573: sine = 32'hbf7e5a38;
11'd1574: sine = 32'hbf7e4324;
11'd1575: sine = 32'hbf7e2b72;
11'd1576: sine = 32'hbf7e1324;
11'd1577: sine = 32'hbf7dfa39;
11'd1578: sine = 32'hbf7de0b1;
11'd1579: sine = 32'hbf7dc68d;
11'd1580: sine = 32'hbf7dabcc;
11'd1581: sine = 32'hbf7d906e;
11'd1582: sine = 32'hbf7d7475;
11'd1583: sine = 32'hbf7d57df;
11'd1584: sine = 32'hbf7d3aac;
11'd1585: sine = 32'hbf7d1cde;
11'd1586: sine = 32'hbf7cfe73;
11'd1587: sine = 32'hbf7cdf6c;
11'd1588: sine = 32'hbf7cbfc9;
11'd1589: sine = 32'hbf7c9f8b;
11'd1590: sine = 32'hbf7c7eb0;
11'd1591: sine = 32'hbf7c5d3a;
11'd1592: sine = 32'hbf7c3b28;
11'd1593: sine = 32'hbf7c187b;
11'd1594: sine = 32'hbf7bf532;
11'd1595: sine = 32'hbf7bd14d;
11'd1596: sine = 32'hbf7baccd;
11'd1597: sine = 32'hbf7b87b2;
11'd1598: sine = 32'hbf7b61fc;
11'd1599: sine = 32'hbf7b3bab;
11'd1600: sine = 32'hbf7b14bf;
11'd1601: sine = 32'hbf7aed38;
11'd1602: sine = 32'hbf7ac516;
11'd1603: sine = 32'hbf7a9c59;
11'd1604: sine = 32'hbf7a7302;
11'd1605: sine = 32'hbf7a4911;
11'd1606: sine = 32'hbf7a1e84;
11'd1607: sine = 32'hbf79f35e;
11'd1608: sine = 32'hbf79c79e;
11'd1609: sine = 32'hbf799b43;
11'd1610: sine = 32'hbf796e4f;
11'd1611: sine = 32'hbf7940c0;
11'd1612: sine = 32'hbf791298;
11'd1613: sine = 32'hbf78e3d6;
11'd1614: sine = 32'hbf78b47b;
11'd1615: sine = 32'hbf788486;
11'd1616: sine = 32'hbf7853f8;
11'd1617: sine = 32'hbf7822d1;
11'd1618: sine = 32'hbf77f111;
11'd1619: sine = 32'hbf77beb8;
11'd1620: sine = 32'hbf778bc5;
11'd1621: sine = 32'hbf77583b;
11'd1622: sine = 32'hbf772417;
11'd1623: sine = 32'hbf76ef5c;
11'd1624: sine = 32'hbf76ba08;
11'd1625: sine = 32'hbf76841b;
11'd1626: sine = 32'hbf764d97;
11'd1627: sine = 32'hbf76167b;
11'd1628: sine = 32'hbf75dec7;
11'd1629: sine = 32'hbf75a67b;
11'd1630: sine = 32'hbf756d98;
11'd1631: sine = 32'hbf75341d;
11'd1632: sine = 32'hbf74fa0b;
11'd1633: sine = 32'hbf74bf62;
11'd1634: sine = 32'hbf748422;
11'd1635: sine = 32'hbf74484b;
11'd1636: sine = 32'hbf740bde;
11'd1637: sine = 32'hbf73ceda;
11'd1638: sine = 32'hbf73913f;
11'd1639: sine = 32'hbf73530f;
11'd1640: sine = 32'hbf731448;
11'd1641: sine = 32'hbf72d4eb;
11'd1642: sine = 32'hbf7294f9;
11'd1643: sine = 32'hbf725470;
11'd1644: sine = 32'hbf721353;
11'd1645: sine = 32'hbf71d1a0;
11'd1646: sine = 32'hbf718f58;
11'd1647: sine = 32'hbf714c7b;
11'd1648: sine = 32'hbf710909;
11'd1649: sine = 32'hbf70c502;
11'd1650: sine = 32'hbf708067;
11'd1651: sine = 32'hbf703b37;
11'd1652: sine = 32'hbf6ff574;
11'd1653: sine = 32'hbf6faf1c;
11'd1654: sine = 32'hbf6f6830;
11'd1655: sine = 32'hbf6f20b1;
11'd1656: sine = 32'hbf6ed89e;
11'd1657: sine = 32'hbf6e8ff8;
11'd1658: sine = 32'hbf6e46bf;
11'd1659: sine = 32'hbf6dfcf3;
11'd1660: sine = 32'hbf6db294;
11'd1661: sine = 32'hbf6d67a2;
11'd1662: sine = 32'hbf6d1c1e;
11'd1663: sine = 32'hbf6cd007;
11'd1664: sine = 32'hbf6c835f;
11'd1665: sine = 32'hbf6c3625;
11'd1666: sine = 32'hbf6be859;
11'd1667: sine = 32'hbf6b99fb;
11'd1668: sine = 32'hbf6b4b0c;
11'd1669: sine = 32'hbf6afb8c;
11'd1670: sine = 32'hbf6aab7b;
11'd1671: sine = 32'hbf6a5ad9;
11'd1672: sine = 32'hbf6a09a7;
11'd1673: sine = 32'hbf69b7e4;
11'd1674: sine = 32'hbf696592;
11'd1675: sine = 32'hbf6912af;
11'd1676: sine = 32'hbf68bf3c;
11'd1677: sine = 32'hbf686b3a;
11'd1678: sine = 32'hbf6816a9;
11'd1679: sine = 32'hbf67c188;
11'd1680: sine = 32'hbf676bd8;
11'd1681: sine = 32'hbf67159a;
11'd1682: sine = 32'hbf66becd;
11'd1683: sine = 32'hbf666772;
11'd1684: sine = 32'hbf660f88;
11'd1685: sine = 32'hbf65b711;
11'd1686: sine = 32'hbf655e0c;
11'd1687: sine = 32'hbf650479;
11'd1688: sine = 32'hbf64aa5a;
11'd1689: sine = 32'hbf644fad;
11'd1690: sine = 32'hbf63f473;
11'd1691: sine = 32'hbf6398ad;
11'd1692: sine = 32'hbf633c5a;
11'd1693: sine = 32'hbf62df7c;
11'd1694: sine = 32'hbf628211;
11'd1695: sine = 32'hbf62241a;
11'd1696: sine = 32'hbf61c598;
11'd1697: sine = 32'hbf61668b;
11'd1698: sine = 32'hbf6106f3;
11'd1699: sine = 32'hbf60a6d0;
11'd1700: sine = 32'hbf604622;
11'd1701: sine = 32'hbf5fe4ea;
11'd1702: sine = 32'hbf5f8328;
11'd1703: sine = 32'hbf5f20dc;
11'd1704: sine = 32'hbf5ebe06;
11'd1705: sine = 32'hbf5e5aa7;
11'd1706: sine = 32'hbf5df6bf;
11'd1707: sine = 32'hbf5d924e;
11'd1708: sine = 32'hbf5d2d54;
11'd1709: sine = 32'hbf5cc7d2;
11'd1710: sine = 32'hbf5c61c7;
11'd1711: sine = 32'hbf5bfb35;
11'd1712: sine = 32'hbf5b941b;
11'd1713: sine = 32'hbf5b2c79;
11'd1714: sine = 32'hbf5ac451;
11'd1715: sine = 32'hbf5a5ba1;
11'd1716: sine = 32'hbf59f26b;
11'd1717: sine = 32'hbf5988ae;
11'd1718: sine = 32'hbf591e6b;
11'd1719: sine = 32'hbf58b3a2;
11'd1720: sine = 32'hbf584854;
11'd1721: sine = 32'hbf57dc80;
11'd1722: sine = 32'hbf577026;
11'd1723: sine = 32'hbf570348;
11'd1724: sine = 32'hbf5695e6;
11'd1725: sine = 32'hbf5627ff;
11'd1726: sine = 32'hbf55b994;
11'd1727: sine = 32'hbf554aa5;
11'd1728: sine = 32'hbf54db32;
11'd1729: sine = 32'hbf546b3c;
11'd1730: sine = 32'hbf53fac3;
11'd1731: sine = 32'hbf5389c8;
11'd1732: sine = 32'hbf53184a;
11'd1733: sine = 32'hbf52a649;
11'd1734: sine = 32'hbf5233c7;
11'd1735: sine = 32'hbf51c0c3;
11'd1736: sine = 32'hbf514d3e;
11'd1737: sine = 32'hbf50d937;
11'd1738: sine = 32'hbf5064b0;
11'd1739: sine = 32'hbf4fefa8;
11'd1740: sine = 32'hbf4f7a20;
11'd1741: sine = 32'hbf4f0418;
11'd1742: sine = 32'hbf4e8d91;
11'd1743: sine = 32'hbf4e1689;
11'd1744: sine = 32'hbf4d9f03;
11'd1745: sine = 32'hbf4d26fe;
11'd1746: sine = 32'hbf4cae7a;
11'd1747: sine = 32'hbf4c3578;
11'd1748: sine = 32'hbf4bbbf9;
11'd1749: sine = 32'hbf4b41fb;
11'd1750: sine = 32'hbf4ac780;
11'd1751: sine = 32'hbf4a4c88;
11'd1752: sine = 32'hbf49d113;
11'd1753: sine = 32'hbf495522;
11'd1754: sine = 32'hbf48d8b4;
11'd1755: sine = 32'hbf485bcb;
11'd1756: sine = 32'hbf47de66;
11'd1757: sine = 32'hbf476086;
11'd1758: sine = 32'hbf46e22b;
11'd1759: sine = 32'hbf466355;
11'd1760: sine = 32'hbf45e404;
11'd1761: sine = 32'hbf45643a;
11'd1762: sine = 32'hbf44e3f6;
11'd1763: sine = 32'hbf446338;
11'd1764: sine = 32'hbf43e201;
11'd1765: sine = 32'hbf436052;
11'd1766: sine = 32'hbf42de2a;
11'd1767: sine = 32'hbf425b8a;
11'd1768: sine = 32'hbf41d871;
11'd1769: sine = 32'hbf4154e2;
11'd1770: sine = 32'hbf40d0db;
11'd1771: sine = 32'hbf404c5d;
11'd1772: sine = 32'hbf3fc768;
11'd1773: sine = 32'hbf3f41fd;
11'd1774: sine = 32'hbf3ebc1c;
11'd1775: sine = 32'hbf3e35c6;
11'd1776: sine = 32'hbf3daefa;
11'd1777: sine = 32'hbf3d27b9;
11'd1778: sine = 32'hbf3ca004;
11'd1779: sine = 32'hbf3c17da;
11'd1780: sine = 32'hbf3b8f3c;
11'd1781: sine = 32'hbf3b062a;
11'd1782: sine = 32'hbf3a7ca5;
11'd1783: sine = 32'hbf39f2ae;
11'd1784: sine = 32'hbf396843;
11'd1785: sine = 32'hbf38dd66;
11'd1786: sine = 32'hbf385217;
11'd1787: sine = 32'hbf37c656;
11'd1788: sine = 32'hbf373a24;
11'd1789: sine = 32'hbf36ad81;
11'd1790: sine = 32'hbf36206d;
11'd1791: sine = 32'hbf3592e9;
11'd1792: sine = 32'hbf3504f4;
11'd1793: sine = 32'hbf347690;
11'd1794: sine = 32'hbf33e7bd;
11'd1795: sine = 32'hbf33587b;
11'd1796: sine = 32'hbf32c8ca;
11'd1797: sine = 32'hbf3238ab;
11'd1798: sine = 32'hbf31a81e;
11'd1799: sine = 32'hbf311724;
11'd1800: sine = 32'hbf3085bc;
11'd1801: sine = 32'hbf2ff3e7;
11'd1802: sine = 32'hbf2f61a6;
11'd1803: sine = 32'hbf2ecef8;
11'd1804: sine = 32'hbf2e3bdf;
11'd1805: sine = 32'hbf2da85a;
11'd1806: sine = 32'hbf2d146a;
11'd1807: sine = 32'hbf2c8010;
11'd1808: sine = 32'hbf2beb4b;
11'd1809: sine = 32'hbf2b561c;
11'd1810: sine = 32'hbf2ac083;
11'd1811: sine = 32'hbf2a2a81;
11'd1812: sine = 32'hbf299416;
11'd1813: sine = 32'hbf28fd42;
11'd1814: sine = 32'hbf286606;
11'd1815: sine = 32'hbf27ce62;
11'd1816: sine = 32'hbf273657;
11'd1817: sine = 32'hbf269de5;
11'd1818: sine = 32'hbf26050b;
11'd1819: sine = 32'hbf256bcc;
11'd1820: sine = 32'hbf24d226;
11'd1821: sine = 32'hbf24381b;
11'd1822: sine = 32'hbf239daa;
11'd1823: sine = 32'hbf2302d5;
11'd1824: sine = 32'hbf22679a;
11'd1825: sine = 32'hbf21cbfc;
11'd1826: sine = 32'hbf212ffa;
11'd1827: sine = 32'hbf209394;
11'd1828: sine = 32'hbf1ff6cc;
11'd1829: sine = 32'hbf1f59a1;
11'd1830: sine = 32'hbf1ebc13;
11'd1831: sine = 32'hbf1e1e24;
11'd1832: sine = 32'hbf1d7fd3;
11'd1833: sine = 32'hbf1ce120;
11'd1834: sine = 32'hbf1c420d;
11'd1835: sine = 32'hbf1ba29a;
11'd1836: sine = 32'hbf1b02c7;
11'd1837: sine = 32'hbf1a6294;
11'd1838: sine = 32'hbf19c202;
11'd1839: sine = 32'hbf192111;
11'd1840: sine = 32'hbf187fc1;
11'd1841: sine = 32'hbf17de14;
11'd1842: sine = 32'hbf173c08;
11'd1843: sine = 32'hbf1699a0;
11'd1844: sine = 32'hbf15f6da;
11'd1845: sine = 32'hbf1553b9;
11'd1846: sine = 32'hbf14b03b;
11'd1847: sine = 32'hbf140c61;
11'd1848: sine = 32'hbf13682c;
11'd1849: sine = 32'hbf12c39c;
11'd1850: sine = 32'hbf121eb1;
11'd1851: sine = 32'hbf11796d;
11'd1852: sine = 32'hbf10d3ce;
11'd1853: sine = 32'hbf102dd6;
11'd1854: sine = 32'hbf0f8786;
11'd1855: sine = 32'hbf0ee0dd;
11'd1856: sine = 32'hbf0e39db;
11'd1857: sine = 32'hbf0d9282;
11'd1858: sine = 32'hbf0cead2;
11'd1859: sine = 32'hbf0c42ca;
11'd1860: sine = 32'hbf0b9a6c;
11'd1861: sine = 32'hbf0af1b9;
11'd1862: sine = 32'hbf0a48af;
11'd1863: sine = 32'hbf099f50;
11'd1864: sine = 32'hbf08f59c;
11'd1865: sine = 32'hbf084b94;
11'd1866: sine = 32'hbf07a137;
11'd1867: sine = 32'hbf06f687;
11'd1868: sine = 32'hbf064b84;
11'd1869: sine = 32'hbf05a02e;
11'd1870: sine = 32'hbf04f485;
11'd1871: sine = 32'hbf04488a;
11'd1872: sine = 32'hbf039c3e;
11'd1873: sine = 32'hbf02efa1;
11'd1874: sine = 32'hbf0242b3;
11'd1875: sine = 32'hbf019574;
11'd1876: sine = 32'hbf00e7e6;
11'd1877: sine = 32'hbf003a08;
11'd1878: sine = 32'hbeff17b5;
11'd1879: sine = 32'hbefdbabe;
11'd1880: sine = 32'hbefc5d2a;
11'd1881: sine = 32'hbefafefa;
11'd1882: sine = 32'hbef9a030;
11'd1883: sine = 32'hbef840cb;
11'd1884: sine = 32'hbef6e0cd;
11'd1885: sine = 32'hbef58038;
11'd1886: sine = 32'hbef41f0a;
11'd1887: sine = 32'hbef2bd46;
11'd1888: sine = 32'hbef15aed;
11'd1889: sine = 32'hbeeff7fe;
11'd1890: sine = 32'hbeee947c;
11'd1891: sine = 32'hbeed3066;
11'd1892: sine = 32'hbeebcbbe;
11'd1893: sine = 32'hbeea6684;
11'd1894: sine = 32'hbee900ba;
11'd1895: sine = 32'hbee79a60;
11'd1896: sine = 32'hbee63378;
11'd1897: sine = 32'hbee4cc01;
11'd1898: sine = 32'hbee363fd;
11'd1899: sine = 32'hbee1fb6d;
11'd1900: sine = 32'hbee09252;
11'd1901: sine = 32'hbedf28ac;
11'd1902: sine = 32'hbeddbe7c;
11'd1903: sine = 32'hbedc53c4;
11'd1904: sine = 32'hbedae883;
11'd1905: sine = 32'hbed97cbc;
11'd1906: sine = 32'hbed8106e;
11'd1907: sine = 32'hbed6a39c;
11'd1908: sine = 32'hbed53644;
11'd1909: sine = 32'hbed3c86a;
11'd1910: sine = 32'hbed25a0c;
11'd1911: sine = 32'hbed0eb2d;
11'd1912: sine = 32'hbecf7bcd;
11'd1913: sine = 32'hbece0bed;
11'd1914: sine = 32'hbecc9b8e;
11'd1915: sine = 32'hbecb2ab1;
11'd1916: sine = 32'hbec9b956;
11'd1917: sine = 32'hbec8477f;
11'd1918: sine = 32'hbec6d52d;
11'd1919: sine = 32'hbec5625f;
11'd1920: sine = 32'hbec3ef18;
11'd1921: sine = 32'hbec27b58;
11'd1922: sine = 32'hbec10721;
11'd1923: sine = 32'hbebf9272;
11'd1924: sine = 32'hbebe1d4d;
11'd1925: sine = 32'hbebca7b2;
11'd1926: sine = 32'hbebb31a4;
11'd1927: sine = 32'hbeb9bb21;
11'd1928: sine = 32'hbeb8442d;
11'd1929: sine = 32'hbeb6ccc6;
11'd1930: sine = 32'hbeb554ef;
11'd1931: sine = 32'hbeb3dca8;
11'd1932: sine = 32'hbeb263f2;
11'd1933: sine = 32'hbeb0eace;
11'd1934: sine = 32'hbeaf713d;
11'd1935: sine = 32'hbeadf740;
11'd1936: sine = 32'hbeac7cd7;
11'd1937: sine = 32'hbeab0204;
11'd1938: sine = 32'hbea986c7;
11'd1939: sine = 32'hbea80b22;
11'd1940: sine = 32'hbea68f15;
11'd1941: sine = 32'hbea512a2;
11'd1942: sine = 32'hbea395c8;
11'd1943: sine = 32'hbea2188a;
11'd1944: sine = 32'hbea09ae8;
11'd1945: sine = 32'hbe9f1ce3;
11'd1946: sine = 32'hbe9d9e7b;
11'd1947: sine = 32'hbe9c1fb2;
11'd1948: sine = 32'hbe9aa089;
11'd1949: sine = 32'hbe992101;
11'd1950: sine = 32'hbe97a11a;
11'd1951: sine = 32'hbe9620d6;
11'd1952: sine = 32'hbe94a035;
11'd1953: sine = 32'hbe931f38;
11'd1954: sine = 32'hbe919de1;
11'd1955: sine = 32'hbe901c2f;
11'd1956: sine = 32'hbe8e9a25;
11'd1957: sine = 32'hbe8d17c3;
11'd1958: sine = 32'hbe8b950a;
11'd1959: sine = 32'hbe8a11fb;
11'd1960: sine = 32'hbe888e96;
11'd1961: sine = 32'hbe870ade;
11'd1962: sine = 32'hbe8586d2;
11'd1963: sine = 32'hbe840274;
11'd1964: sine = 32'hbe827dc4;
11'd1965: sine = 32'hbe80f8c4;
11'd1966: sine = 32'hbe7ee6e8;
11'd1967: sine = 32'hbe7bdbab;
11'd1968: sine = 32'hbe78cfd3;
11'd1969: sine = 32'hbe75c361;
11'd1970: sine = 32'hbe72b658;
11'd1971: sine = 32'hbe6fa8b9;
11'd1972: sine = 32'hbe6c9a86;
11'd1973: sine = 32'hbe698bc1;
11'd1974: sine = 32'hbe667c6c;
11'd1975: sine = 32'hbe636c89;
11'd1976: sine = 32'hbe605c1a;
11'd1977: sine = 32'hbe5d4b20;
11'd1978: sine = 32'hbe5a399e;
11'd1979: sine = 32'hbe572795;
11'd1980: sine = 32'hbe541508;
11'd1981: sine = 32'hbe5101f8;
11'd1982: sine = 32'hbe4dee66;
11'd1983: sine = 32'hbe4ada56;
11'd1984: sine = 32'hbe47c5c9;
11'd1985: sine = 32'hbe44b0c0;
11'd1986: sine = 32'hbe419b3e;
11'd1987: sine = 32'hbe3e8545;
11'd1988: sine = 32'hbe3b6ed6;
11'd1989: sine = 32'hbe3857f3;
11'd1990: sine = 32'hbe35409f;
11'd1991: sine = 32'hbe3228db;
11'd1992: sine = 32'hbe2f10a9;
11'd1993: sine = 32'hbe2bf80b;
11'd1994: sine = 32'hbe28df03;
11'd1995: sine = 32'hbe25c593;
11'd1996: sine = 32'hbe22abbc;
11'd1997: sine = 32'hbe1f9182;
11'd1998: sine = 32'hbe1c76e4;
11'd1999: sine = 32'hbe195be7;
11'd2000: sine = 32'hbe16408a;
11'd2001: sine = 32'hbe1324d1;
11'd2002: sine = 32'hbe1008be;
11'd2003: sine = 32'hbe0cec51;
11'd2004: sine = 32'hbe09cf8d;
11'd2005: sine = 32'hbe06b275;
11'd2006: sine = 32'hbe039509;
11'd2007: sine = 32'hbe00774c;
11'd2008: sine = 32'hbdfab281;
11'd2009: sine = 32'hbdf475ce;
11'd2010: sine = 32'hbdee3884;
11'd2011: sine = 32'hbde7faa8;
11'd2012: sine = 32'hbde1bc3c;
11'd2013: sine = 32'hbddb7d45;
11'd2014: sine = 32'hbdd53dc7;
11'd2015: sine = 32'hbdcefdc5;
11'd2016: sine = 32'hbdc8bd44;
11'd2017: sine = 32'hbdc27c47;
11'd2018: sine = 32'hbdbc3ad1;
11'd2019: sine = 32'hbdb5f8e8;
11'd2020: sine = 32'hbdafb68e;
11'd2021: sine = 32'hbda973c8;
11'd2022: sine = 32'hbda3309a;
11'd2023: sine = 32'hbd9ced07;
11'd2024: sine = 32'hbd96a913;
11'd2025: sine = 32'hbd9064c2;
11'd2026: sine = 32'hbd8a2018;
11'd2027: sine = 32'hbd83db19;
11'd2028: sine = 32'hbd7b2b90;
11'd2029: sine = 32'hbd6ea054;
11'd2030: sine = 32'hbd621485;
11'd2031: sine = 32'hbd55882a;
11'd2032: sine = 32'hbd48fb4c;
11'd2033: sine = 32'hbd3c6df2;
11'd2034: sine = 32'hbd2fe023;
11'd2035: sine = 32'hbd2351e8;
11'd2036: sine = 32'hbd16c348;
11'd2037: sine = 32'hbd0a344b;
11'd2038: sine = 32'hbcfb49f3;
11'd2039: sine = 32'hbce22ab4;
11'd2040: sine = 32'hbcc90ae9;
11'd2041: sine = 32'hbcafeaa2;
11'd2042: sine = 32'hbc96c9ef;
11'd2043: sine = 32'hbc7b51be;
11'd2044: sine = 32'hbc490f03;
11'd2045: sine = 32'hbc16cbcb;
11'd2046: sine = 32'hbbc9106e;
11'd2047: sine = 32'hbb491192;
endcase
end
endmodule
|
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