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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_TB_V
`define SKY130_FD_SC_LP__BUFINV_TB_V
/**
* bufinv: Buffer followed by inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__bufinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4B_4_V
`define SKY130_FD_SC_HS__AND4B_4_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4B_4_V
|
// megafunction wizard: %LPM_MUX%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: counter_bus_mux.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module counter_bus_mux (
data0x,
data1x,
sel,
result);
input [3:0] data0x;
input [3:0] data1x;
input sel;
output [3:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
// Retrieval info: USED_PORT: data0x 0 0 4 0 INPUT NODEFVAL "data0x[3..0]"
// Retrieval info: USED_PORT: data1x 0 0 4 0 INPUT NODEFVAL "data1x[3..0]"
// Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL "result[3..0]"
// Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL "sel"
// Retrieval info: CONNECT: @data 0 0 4 0 data0x 0 0 4 0
// Retrieval info: CONNECT: @data 0 0 4 4 data1x 0 0 4 0
// Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
// Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counter_bus_mux_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=64 LPM_WIDTHN=64 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mguik
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [63:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [63:0] remain;
wire [63:0] wire_mgl_prim1_quotient;
wire [63:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 64,
mgl_prim1.lpm_widthn = 64,
mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mguik
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__A222OI_PP_SYMBOL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a222oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
input C2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a32oi (
Y ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_BEHAVIORAL_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : buf_ram_1p_6x85.v
// Author : Yibo FAN
// Created : 2014-04-07
// Description : buf ram for coefficient
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module buf_ram_1p_6x85 (
clk ,
ce ,
we ,
addr ,
data_i ,
data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ********************************************
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk ;
input ce ;
input we ;
input [9:0] addr ;
input [5:0] data_i ;
output [5:0] data_o ;
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
`ifdef RTL_MODEL
ram_1p #(.Addr_Width(10), .Word_Width(6))
u_ram_1p_6x85 (
.clk ( clk ),
.cen_i ( ~ce ),
.oen_i ( 1'b0 ),
.wen_i ( ~we ),
.addr_i ( addr ),
.data_i ( data_i ),
.data_o ( data_o )
);
`endif
`ifdef FPGA_MODEL
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
|
`include "elink_constants.v"
module erx_clocks (/*AUTOARG*/
// Outputs
rx_lclk, rx_lclk_div4, erx_reset, erx_io_reset,
// Inputs
sys_reset, soft_reset, tx_active, sys_clk, rx_clkin
);
`ifdef SIM
parameter RCW = 4; // reset counter width
`else
parameter RCW = 8; // reset counter width
`endif
//Frequency Settings (Mhz)
parameter FREQ_SYSCLK = 100;
parameter FREQ_RXCLK = 300;
parameter FREQ_IDELAY = 200;
parameter RXCLK_PHASE = 0; //270; //-90 deg rxclk phase shift
//VCO multiplers
parameter PLL_VCO_MULT = 4; //RX
//Input clock, reset, config interface
input sys_reset; // por reset (hw)
input soft_reset; // rx enable signal (sw)
input tx_active; // tx active
//Main input clocks
input sys_clk; // always on input clk cclk/TX MMCM
input rx_clkin; // input clk for RX only PLL
//RX Clocks
output rx_lclk; // rx high speed clock for DDR IO
output rx_lclk_div4; // rx slow clock for logic
//Reset
output erx_reset; // reset for rx core logic
output erx_io_reset; // io reset (synced to high speed clock)
//Don't touch these! (derived parameters)
localparam real RXCLK_PERIOD = 1000.000000/FREQ_RXCLK;
localparam integer IREF_DIVIDE = PLL_VCO_MULT*FREQ_RXCLK/FREQ_IDELAY;
localparam integer RXCLK_DIVIDE = PLL_VCO_MULT; //1:1
//############
//# WIRES
//############
//Idelay controller
wire idelay_reset;
wire idelay_ready; //ignore this?
wire idelay_ref_clk;
//pll outputs
wire rx_lclk_pll;
wire rx_lclk_div4_pll;
wire idelay_ref_clk_pll;
//PLL
wire rx_lclk_fb_in;
wire rx_lclk_fb_out;
//###########################
// RESET STATE MACHINE
//###########################
reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
reg heartbeat;
reg pll_locked_reg;
reg pll_locked_sync;
reg [2:0] reset_state;
wire pll_reset;
reg [1:0] reset_pipe_lclkb;
reg [1:0] reset_pipe_lclk_div4b;
//wrap around counter that generates a 1 cycle heartbeat
//free running counter...
always @ (posedge sys_clk)
begin
reset_counter[RCW-1:0] <= reset_counter[RCW-1:0]+1'b1;
heartbeat <= ~(|reset_counter[RCW-1:0]);
end
//two clock synchronizer
always @ (posedge sys_clk)
begin
pll_locked_reg <= pll_locked;
pll_locked_sync <= pll_locked_reg;
end
`define RESET_ALL 3'b000
`define START_PLL 3'b001
`define ACTIVE 3'b010
//Reset sequence state machine
always @ (posedge sys_clk or posedge reset_in)
if(reset_in)
reset_state[2:0] <= `RESET_ALL;
else if(heartbeat)
case(reset_state[2:0])
`RESET_ALL :
if(~soft_reset)
reset_state[2:0] <= `START_PLL;
`START_PLL :
if(pll_locked_sync & idelay_ready)
reset_state[2:0] <= `ACTIVE;
`ACTIVE:
if(soft_reset)
reset_state[2:0] <= `RESET_ALL; //stay there until next reset
endcase // case (reset_state[2:0])
//reset PLL during 'reset' and during quiet time around reset edge
assign reset_in = sys_reset | ~tx_active;
assign pll_reset = (reset_state[2:0]==`RESET_ALL);
assign idelay_reset = (reset_state[2:0]==`RESET_ALL);
//asynch rx reset
assign rx_reset = (reset_state[2:0]!=`ACTIVE);
//#############################
//#RESET SYNC
//#############################
//async assert
//sync deassert
//lclk sync
always @ (posedge rx_lclk or posedge rx_reset)
if(rx_reset)
reset_pipe_lclkb[1:0] <= 2'b00;
else
reset_pipe_lclkb[1:0] <= {reset_pipe_lclkb[0], 1'b1};
assign erx_io_reset = ~reset_pipe_lclkb[1];
//lclkdiv4 sync
always @ (posedge rx_lclk_div4 or posedge rx_reset)
if(rx_reset)
reset_pipe_lclk_div4b[1:0] <= 2'b00;
else
reset_pipe_lclk_div4b[1:0] <= {reset_pipe_lclk_div4b[0],1'b1};
assign erx_reset = ~reset_pipe_lclk_div4b[1];
`ifdef TARGET_XILINX
//###########################
// PLL RX
//###########################
PLLE2_ADV
#(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(PLL_VCO_MULT),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(RXCLK_PERIOD),
.CLKOUT0_DIVIDE(128),
.CLKOUT1_DIVIDE(128),
.CLKOUT2_DIVIDE(128),
.CLKOUT3_DIVIDE(IREF_DIVIDE), // idelay ref clk
.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),//RXCLK_PHASE
.CLKOUT5_PHASE(0.0),//RXCLK_PHASE/4
.DIVCLK_DIVIDE(1.0),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) pll_rx
(
.CLKOUT0(),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(idelay_ref_clk_pll),
.CLKOUT4(rx_lclk_pll),
.CLKOUT5(rx_lclk_div4_pll),
.PWRDWN(1'b0),
.RST(pll_reset),
.CLKFBIN(rx_lclk_fb_in),
.CLKFBOUT(rx_lclk_fb_out),
.CLKIN1(rx_clkin),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.DADDR(7'b0),
.DCLK(1'b0),
.DEN(1'b0),
.DI(16'b0),
.DWE(1'b0),
.DRDY(),
.DO(),
.LOCKED(pll_locked)
);
//Clock network
BUFG rx_lclk_bufg_i (.I(rx_lclk_pll), .O(rx_lclk)); //300Mhz
BUFG rx_lclk_div4_bufg_i (.I(rx_lclk_div4_pll), .O(rx_lclk_div4)); //75 MHz (300/4)
BUFG idelay_ref_bufg_i (.I(idelay_ref_clk_pll), .O(idelay_ref_clk));//idelay ctrl clock
//Feedback buffers
BUFG lclk_fb_bufg_i0(.I(rx_lclk_fb_out),
.O(rx_lclk_fb_in)
);
//###########################
// Idelay controller
//###########################
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
IDELAYCTRL idelayctrl_inst
(
.RDY(idelay_ready), // check ready flag in reset sequence?
.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
.RST(idelay_reset));
`endif // `ifdef TARGET_XILINX
endmodule // eclocks
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
`include "../src/include/block_ram.v"
`include "../src/include/mutex_buffer.v"
`include "../src/include/simple_dpram_sclk.v"
`include "../src/include/simple_fifo.v"
`include "../src/include/fsa_core.v"
`include "../src/include/fsa_detect_header.v"
`include "../src/include/fsa_detect_edge.v"
`include "../src/include/fsa_stream_v2.v"
`include "../src/fsa.v"
`include "../../axis_blender/src/axis_blender.v"
module test_fsa_v2 # (
parameter integer C_PIXEL_WIDTH = 8,
parameter integer C_IMG_HW = 8,
parameter integer C_IMG_WW = 8,
parameter integer BR_DW = 35
) (
);
localparam RANDOMINPUT = 0;
localparam RANDOMOUTPUT = 0;
localparam integer height = 20;
localparam integer width = 40;
localparam integer win_left = 0;
localparam integer win_top = 2;
localparam integer win_width = width;
localparam integer win_height = 16;
localparam integer BR_AW = C_IMG_WW;
localparam integer TEST_BW = 12;
localparam integer GEN_BW = 32;
localparam integer GEN_BV = 32'hFFFF0000;
reg [C_PIXEL_WIDTH-1:0] data[height-1:0][width-1:0];
reg clk;
reg resetn;
reg r0_sof ;
reg r0_rd_en ;
reg [BR_AW-1:0] r0_rd_addr;
wire [BR_DW-1:0] r0_data ;
reg r1_sof ;
reg r1_rd_en ;
reg [BR_AW-1:0] r1_rd_addr;
wire [BR_DW-1:0] r1_data ;
reg [C_PIXEL_WIDTH-1:0] ref_data ;
wire [C_IMG_WW-1:0] lft_v ;
wire [C_IMG_WW-1:0] rt_v ;
reg s_axis_tvalid;
reg [C_PIXEL_WIDTH-1:0] s_axis_tdata ;
reg s_axis_tuser ;
reg s_axis_tlast ;
wire s_axis_tready;
reg fsync;
reg en_axis;
wire m_axis_tvalid;
wire [TEST_BW+GEN_BW-1:0] m_axis_tdata ;
wire m_axis_tuser ;
wire m_axis_tlast ;
wire m_axis_tready;
fsa_v2 # (
.C_TEST(TEST_BW),
.C_OUT_DW(GEN_BW),
.C_OUT_DV(GEN_BV),
.C_PIXEL_WIDTH (C_PIXEL_WIDTH),
.C_IMG_HW (C_IMG_HW),
.C_IMG_WW (C_IMG_WW),
.BR_NUM (4),
.BR_AW (BR_AW), /// same as C_IMG_WW
.BR_DW (BR_DW)
) fsa_inst (
.clk(clk),
.resetn(resetn),
.height(height),
.width (width),
.win_left(win_left),
.win_top(win_top),
.win_width(win_width),
.win_height(win_height),
.r_sof ({r1_sof, r0_sof }),
.r_en ({r1_rd_en, r0_rd_en }),
.r_addr({r1_rd_addr,r0_rd_addr}),
.r_data({r1_data, r0_data }),
.ref_data (ref_data),
.lft_edge (lft_v ),
.rt_edge (rt_v ),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tdata (s_axis_tdata ),
.s_axis_tuser (s_axis_tuser ),
.s_axis_tlast (s_axis_tlast ),
.s_axis_tready(s_axis_tready),
.m_axis_fsync(fsync),
.m_axis_resetn(en_axis),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tdata (m_axis_tdata ),
.m_axis_tuser (m_axis_tuser ),
.m_axis_tlast (m_axis_tlast ),
.m_axis_tready(m_axis_tready)
);
reg s0_valid;
reg [7:0] s0_data;
reg s0_user;
reg s0_last;
wire s0_ready;
wire m_valid ;
wire [23:0] m_data ;
wire m_user ;
wire m_last ;
reg m_ready ;
axis_blender # (
.C_CHN_WIDTH (8 ),
.C_S0_CHN_NUM (1 ),
.C_S1_CHN_NUM (3 ),
.C_ALPHA_WIDTH (8 ),
.C_S1_ENABLE (1 ),
.C_IN_NEED_WIDTH (0 ),
.C_OUT_NEED_WIDTH (0),
.C_M_WIDTH (24 ),
.C_TEST (1 )
) blender_inst (
.clk(clk),
.resetn(resetn),
.s0_axis_tvalid(s0_valid),
.s0_axis_tdata (s0_data),
.s0_axis_tuser (s0_user),
.s0_axis_tlast (s0_last),
.s0_axis_tready(s0_ready),
.s1_enable (en_axis),
.s1_axis_tvalid(m_axis_tvalid),
.s1_axis_tdata (m_axis_tdata ),
.s1_axis_tuser (m_axis_tuser ),
.s1_axis_tlast (m_axis_tlast ),
.s1_axis_tready(m_axis_tready),
.m_axis_tvalid(m_valid ),
.m_axis_tdata (m_data ),
.m_axis_tuser (m_user ),
.m_axis_tlast (m_last ),
.m_axis_tready(m_ready )
);
initial begin
clk <= 1'b1;
forever #2.5 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #5 resetn <= 1'b0;
forever #5 resetn <= 1'b1;
end
integer i, j;
initial begin
for (i = 0; i < height; i=i+1) begin
for (j=0; j < width; j=j+1) begin
if (j <= 17 || j >= 23) begin
if (j <= 14 || j >= 27) begin
if ((i >= 5 && i <= 7) || (i >= 10 && i <= 15)) begin
data[i][j] = 10;
end
else begin
data[i][j] = 128+j;
end
end
else begin
if ((i >= 6 && i <= 7) || (i >= 10 && i <= 13)) begin
data[i][j] = 10;
end
else begin
data[i][j] = 128+j;
end
end
end
else
data[i][j] = 128+j;
end
end
assign ref_data = 128;
end
reg[63:0] clk_cnt;
always @ (posedge clk) begin
if (resetn == 1'b0 || clk_cnt == 2500)
clk_cnt <= 0;
else
clk_cnt <= clk_cnt + 1;
end
reg randominput;
always @ (posedge clk) begin
if (resetn == 1'b0)
randominput <= 1'b0;
else
randominput <= (RANDOMINPUT ? {$random}%2 : 1);
end
always @ (posedge clk) begin
if (resetn == 1'b0)
m_ready <= 1'b0;
else
m_ready <= (RANDOMOUTPUT ? {$random}%2 : 1);
end
/////////////////////////////////////// fs img /////////////////////////////////
reg[C_IMG_WW-1:0] col;
reg[C_IMG_HW-1:0] row;
wire snext;
assign snext = (~s_axis_tvalid | s_axis_tready) && randominput;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
col <= 0;
row <= 0;
end
else if (snext) begin
if (col == width-1)
col <= 0;
else
col <= col + 1;
if (col == width-1) begin
if (row == height - 1)
row <= 0;
else
row <= row + 1;
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s_axis_tuser <= 0;
s_axis_tlast <= 0;
s_axis_tdata <= 0;
s_axis_tvalid <= 0;
end
else if (snext) begin
s_axis_tvalid <= 1;
s_axis_tlast <= (col == width-1);
s_axis_tuser <= (col == 0 && row == 0);
s_axis_tdata <= data[row][col];
end
else if (s_axis_tready) begin
s_axis_tvalid <= 0;
end
end
/////////////////////////////////////// ext img /////////////////////////////////
reg randoms0;
always @ (posedge clk) begin
if (resetn == 1'b0)
randoms0 <= 1'b0;
else
randoms0 <= (RANDOMINPUT ? {$random}%2 : 1);
end
reg[C_IMG_WW-1:0] s0_col;
reg[C_IMG_HW-1:0] s0_row;
wire s0next;
assign s0next = (~s0_valid | s0_ready) && randoms0 && en_axis;
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s0_col <= 0;
s0_row <= 0;
end
else if (s0next) begin
if (s0_col == width-1)
s0_col <= 0;
else
s0_col <= s0_col + 1;
if (s0_col == width-1) begin
if (s0_row == height - 1)
s0_row <= 0;
else
s0_row <= s0_row + 1;
end
end
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
s0_user <= 0;
s0_last <= 0;
s0_data <= 0;
s0_valid <= 0;
end
else if (s0next) begin
s0_valid <= 1;
s0_last <= (s0_col == width-1);
s0_user <= (s0_col == 0 && s0_row == 0);
s0_data <= 0;
end
else if (s0_ready) begin
s0_valid <= 0;
end
end
//////////////////////////////////////////////////////////////////////////////
always @ (posedge clk) begin
if (resetn == 1'b0) begin
fsync <= 0;
en_axis <= 0;
end
else if (clk_cnt[11:0] == 1000) begin
fsync <= 1;
en_axis <= 1;
end
else begin
fsync <= 0;
end
end
generate
if (0) begin
always @ (posedge clk) begin
if (resetn == 1'b0) begin
end
else if (m_valid && m_ready) begin
if (m_user)
$write("\nstart new frame:\n");
/*
if (m_data[GEN_BW-1:0] == GEN_BV)
$write("1");
else
$write("0");
*/
$write("%x ", m_data[23:16]);
//$write("%d ", (m_data/2));
if (m_last)
$write("\n");
end
end
end
else begin
always @ (posedge clk) begin
if (resetn == 1'b0) begin
end
else if (fsync)
$write("\nfsync\n");
else if (m_axis_tvalid && m_axis_tready) begin
if (m_axis_tuser)
$write("\nstart new frame:\n");
/*
if (m_data[GEN_BW-1:0] == GEN_BV)
$write("1");
else
$write("0");
*/
$write("%x ", m_axis_tdata[23:16]);
//$write("%d ", (m_data/2));
if (m_axis_tlast)
$write("\n");
end
end
end
endgenerate
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* COREMARK */
/*---------------------------------------------------------------------------*/
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
`define NO_TIMEOUT
time mclk_start_time, mclk_end_time;
real mclk_period, mclk_frequency;
time coremark_start_time, coremark_end_time;
real coremark_per_sec;
real coremark_per_mhz;
integer Number_Of_Iterations;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
// Disable automatic DMA verification
#10;
dma_verif_on = 0;
repeat(5) @(posedge mclk);
stimulus_done = 0;
//---------------------------------------
// Check CPU configuration
//---------------------------------------
if ((`PMEM_SIZE !== 49152) || (`DMEM_SIZE !== 10240))
begin
$display(" ===============================================");
$display("| SIMULATION ERROR |");
$display("| |");
$display("| Core must be configured for: |");
$display("| - 48kB program memory |");
$display("| - 10kB data memory |");
$display(" ===============================================");
$finish;
end
// Disable watchdog
// (only required because RedHat/TI GCC toolchain doesn't disable watchdog properly at startup)
`ifdef WATCHDOG
force dut.watchdog_0.wdtcnt = 16'h0000;
`endif
//---------------------------------------
// Number of benchmark iteration
// (Must match the C-code value)
//---------------------------------------
Number_Of_Iterations = 1;
//---------------------------------------
// Measure clock period
//---------------------------------------
repeat(100) @(posedge mclk);
$timeformat(-9, 3, " ns", 10);
@(posedge mclk);
mclk_start_time = $time;
@(posedge mclk);
mclk_end_time = $time;
@(posedge mclk);
mclk_period = mclk_end_time-mclk_start_time;
mclk_frequency = 1000/mclk_period;
$display("\nINFO-VERILOG: openMSP430 System clock frequency %f MHz", mclk_frequency);
//---------------------------------------
// Measure CoreMark run time
//---------------------------------------
// Detect beginning of run
@(posedge p2_dout[1]);
coremark_start_time = $time;
$timeformat(-3, 3, " ms", 10);
$display("INFO-VERILOG: CoreMark loop started at %t ", coremark_start_time);
$display("");
$display("INFO-VERILOG: Be patient... there could be up to 90ms to simulate");
$display("");
// Detect end of run
@(negedge p2_dout[1]);
coremark_end_time = $time;
$timeformat(-3, 3, " ms", 10);
$display("INFO-VERILOG: Coremark loop ended at %t ", coremark_end_time);
// Compute results
$timeformat(-9, 3, " ns", 10);
coremark_per_sec = coremark_end_time - coremark_start_time;
coremark_per_sec = 1000000000 / coremark_per_sec;
coremark_per_sec = Number_Of_Iterations*coremark_per_sec;
coremark_per_mhz = coremark_per_sec / mclk_frequency;
// Report results
$display("\INFO-VERILOG: CoreMark ticks : %d", {p6_din, p5_din, p4_din, p3_din});
$display("\INFO-VERILOG: CoreMark per second : %f", coremark_per_sec);
$display("\INFO-VERILOG: CoreMark per MHz : %f\n\n", coremark_per_mhz);
//---------------------------------------
// Wait for the end of C-code execution
//---------------------------------------
@(posedge p2_dout[7]);
stimulus_done = 1;
$display(" ===============================================");
$display("| SIMULATION DONE |");
$display("| (stopped through verilog stimulus) |");
$display(" ===============================================");
$finish;
end
// Display stuff from the C-program
always @(p2_dout[0])
begin
$write("%s", p1_dout);
$fflush();
end
// Display some info to show simulation progress
initial
begin
@(posedge p2_dout[1]);
#1000000;
while (p2_dout[1])
begin
$display("INFO-VERILOG: Simulated time %t ", $time);
#1000000;
end
end
// Time tick counter
always @(negedge mclk or posedge puc_rst)
if (puc_rst) {p6_din, p5_din, p4_din, p3_din} <= 32'h0000_0000;
else if (p2_dout[1]) {p6_din, p5_din, p4_din, p3_din} <= {p6_din, p5_din, p4_din, p3_din} + 32'h1;
|
`default_nettype none
`timescale 1ns / 1ps
`include "../src/error_counter.v"
// ============================================================================
module tb;
// ============================================================================
reg CLK;
initial CLK <= 1'b0;
always #0.5 CLK <= !CLK;
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK) rst_sr <= rst_sr >> 1;
wire RST;
assign RST = rst_sr[0];
// ============================================================================
initial begin
$dumpfile("waveforms.vcd");
$dumpvars;
end
integer cycle_cnt;
initial cycle_cnt <= 0;
always @(posedge CLK)
if (!RST) cycle_cnt <= cycle_cnt + 1;
always @(posedge CLK)
if (!RST && cycle_cnt >= 150)
$finish;
// ============================================================================
wire o_stb;
wire [4*8-1:0] o_dat;
error_counter #
(
.COUNT_WIDTH (8),
.DELAY_TAPS (4)
)
dut
(
.CLK (CLK),
.RST (RST),
.O_STB (o_stb),
.O_DAT (o_dat)
);
always @(posedge CLK)
if (o_stb)
$display("%X", o_dat);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:43:33 03/10/2015
// Design Name:
// Module Name: counter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counter #(
parameter WIDTH = 0,
parameter MODULUS = 0
)(
input clk,
input ce,
input clr,
output [WIDTH - 1:0] out
);
reg[WIDTH - 1:0] mem = 0;
always@(posedge clk)
begin
if(clr)
mem[WIDTH - 1:0] <= 0;
else
begin
if(ce)
mem <= (mem + 1) % MODULUS;
else
mem <= mem;
end
end
assign out = mem;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_ssi.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
//
// Top level Module: jbi_ssi
// Where Instantiated: jbi
// Description: ROM Interface Block
//
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_ssi (/*AUTOARG*/
// Outputs
jbi_io_ssi_mosi, jbi_io_ssi_sck, jbi_iob_spi_vld, jbi_iob_spi_data,
jbi_iob_spi_stall,
// Inputs
clk, rst_l, arst_l, ctu_jbi_ssiclk, io_jbi_ssi_miso,
io_jbi_ext_int_l, iob_jbi_spi_vld, iob_jbi_spi_data,
iob_jbi_spi_stall
);
input clk;
input rst_l;
input arst_l;
input ctu_jbi_ssiclk; // jbus clk divided by 4
// IO Pads
output jbi_io_ssi_mosi; // Master out slave in to pad.
input io_jbi_ssi_miso; // Master in slave out from pad.
output jbi_io_ssi_sck; // Serial clock to pad.
input io_jbi_ext_int_l;
//IOB Interface
input iob_jbi_spi_vld; // Valid packet from IOB.
input [3:0] iob_jbi_spi_data; // Packet data from IOB.
input iob_jbi_spi_stall; // Flow control to stop data.
output jbi_iob_spi_vld; // Valid packet from UCB.
output [3:0] jbi_iob_spi_data; // Packet data from UCB.
output jbi_iob_spi_stall; // Flow control to stop data.
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
//
// Code start here
//
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire sif_ucbif_busy; // From u_sif of jbi_ssi_sif.v
wire sif_ucbif_par_err; // From u_sif of jbi_ssi_sif.v
wire [63:0] sif_ucbif_rdata; // From u_sif of jbi_ssi_sif.v
wire sif_ucbif_rdata_vld; // From u_sif of jbi_ssi_sif.v
wire sif_ucbif_timeout; // From u_sif of jbi_ssi_sif.v
wire sif_ucbif_timeout_rw; // From u_sif of jbi_ssi_sif.v
wire ucb_ucbif_ack_busy; // From u_ucb of ucb_flow_spi.v
wire [`UCB_ADDR_HI-`UCB_ADDR_LO:0]ucb_ucbif_addr_in;// From u_ucb of ucb_flow_spi.v
wire [`UCB_BUF_HI-`UCB_BUF_LO:0]ucb_ucbif_buf_id_in;// From u_ucb of ucb_flow_spi.v
wire [`UCB_DATA_HI-`UCB_DATA_LO:0]ucb_ucbif_data_in;// From u_ucb of ucb_flow_spi.v
wire ucb_ucbif_ifill_req_vld;// From u_ucb of ucb_flow_spi.v
wire ucb_ucbif_int_busy; // From u_ucb of ucb_flow_spi.v
wire ucb_ucbif_rd_req_vld; // From u_ucb of ucb_flow_spi.v
wire [`UCB_SIZE_HI-`UCB_SIZE_LO:0]ucb_ucbif_size_in;// From u_ucb of ucb_flow_spi.v
wire [`UCB_THR_HI-`UCB_THR_LO:0]ucb_ucbif_thr_id_in;// From u_ucb of ucb_flow_spi.v
wire ucb_ucbif_wr_req_vld; // From u_ucb of ucb_flow_spi.v
wire [`JBI_SSI_ADDR_WIDTH-1:0]ucbif_sif_addr; // From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_sif_rdata_accpt; // From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_sif_rw; // From u_ucbif of jbi_ssi_ucbif.v
wire [`JBI_SSI_SZ_WIDTH-1:0]ucbif_sif_size; // From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_sif_timeout_accpt;// From u_ucbif of jbi_ssi_ucbif.v
wire [`JBI_SSI_CSR_TOUT_TIMEVAL_WIDTH-1:0]ucbif_sif_timeval;// From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_sif_vld; // From u_ucbif of jbi_ssi_ucbif.v
wire [63:0] ucbif_sif_wdata; // From u_ucbif of jbi_ssi_ucbif.v
wire [`UCB_BUF_HI-`UCB_BUF_LO:0]ucbif_ucb_buf_id_out;// From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_ucb_data128; // From u_ucbif of jbi_ssi_ucbif.v
wire [63:0] ucbif_ucb_data_out; // From u_ucbif of jbi_ssi_ucbif.v
wire [`UCB_INT_DEV_WIDTH-1:0]ucbif_ucb_dev_id; // From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_ucb_ifill_ack_vld;// From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_ucb_ifill_nack_vld;// From u_ucbif of jbi_ssi_ucbif.v
wire [`UCB_PKT_WIDTH-1:0]ucbif_ucb_int_type; // From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_ucb_int_vld; // From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_ucb_rd_ack_vld; // From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_ucb_rd_nack_vld; // From u_ucbif of jbi_ssi_ucbif.v
wire ucbif_ucb_req_acpted; // From u_ucbif of jbi_ssi_ucbif.v
wire [`UCB_THR_HI-`UCB_THR_LO:0]ucbif_ucb_thr_id_out;// From u_ucbif of jbi_ssi_ucbif.v
// End of automatics
/* ucb_flow_spi AUTO_TEMPLATE (
// system input
.iob_ucb_vld (iob_jbi_spi_vld),
.iob_ucb_data (iob_jbi_spi_data[3:0]),
.ucb_iob_stall (jbi_iob_spi_stall),
.iob_ucb_stall (iob_jbi_spi_stall),
.ucb_iob_vld (jbi_iob_spi_vld),
.ucb_iob_data (jbi_iob_spi_data[3:0]),
.\([a-z_]*\)_req_vld (ucb_ucbif_\1_req_vld),
.\([a-z_]*\)_in (ucb_ucbif_\1_in[]),
.req_acpted (ucbif_ucb_req_acpted),
.\([a-z_]*\)ack_vld (ucbif_ucb_\1ack_vld),
.\([a-z_]*\)_out (ucbif_ucb_\1_out[]),
.data_out (ucbif_ucb_data_out[63:0]),
.data128 (ucbif_ucb_data128),
.ack_busy (ucb_ucbif_ack_busy),
.int_vld (ucbif_ucb_int_vld),
.int_typ (ucbif_ucb_int_type),
.int_thr_id ({`UCB_THR_HI-`UCB_THR_LO+1{1'b0}}),
.dev_id (ucbif_ucb_dev_id),
.int_stat ({`UCB_INT_STAT_HI-`UCB_INT_STAT_LO+1{1'b0}}),
.int_vec ({`UCB_INT_VEC_HI-`UCB_INT_VEC_LO+1{1'b0}}),
.int_busy (ucb_ucbif_int_busy),
);*/
ucb_flow_spi #(4,4) u_ucb (/*AUTOINST*/
// Outputs
.ucb_iob_stall(jbi_iob_spi_stall), // Templated
.rd_req_vld (ucb_ucbif_rd_req_vld), // Templated
.wr_req_vld (ucb_ucbif_wr_req_vld), // Templated
.ifill_req_vld(ucb_ucbif_ifill_req_vld), // Templated
.thr_id_in (ucb_ucbif_thr_id_in[`UCB_THR_HI-`UCB_THR_LO:0]), // Templated
.buf_id_in (ucb_ucbif_buf_id_in[`UCB_BUF_HI-`UCB_BUF_LO:0]), // Templated
.size_in (ucb_ucbif_size_in[`UCB_SIZE_HI-`UCB_SIZE_LO:0]), // Templated
.addr_in (ucb_ucbif_addr_in[`UCB_ADDR_HI-`UCB_ADDR_LO:0]), // Templated
.data_in (ucb_ucbif_data_in[`UCB_DATA_HI-`UCB_DATA_LO:0]), // Templated
.ack_busy (ucb_ucbif_ack_busy), // Templated
.int_busy (ucb_ucbif_int_busy), // Templated
.ucb_iob_vld (jbi_iob_spi_vld), // Templated
.ucb_iob_data(jbi_iob_spi_data[3:0]), // Templated
// Inputs
.clk (clk),
.rst_l (rst_l),
.iob_ucb_vld (iob_jbi_spi_vld), // Templated
.iob_ucb_data(iob_jbi_spi_data[3:0]), // Templated
.req_acpted (ucbif_ucb_req_acpted), // Templated
.rd_ack_vld (ucbif_ucb_rd_ack_vld), // Templated
.rd_nack_vld (ucbif_ucb_rd_nack_vld), // Templated
.ifill_ack_vld(ucbif_ucb_ifill_ack_vld), // Templated
.ifill_nack_vld(ucbif_ucb_ifill_nack_vld), // Templated
.thr_id_out (ucbif_ucb_thr_id_out[`UCB_THR_HI-`UCB_THR_LO:0]), // Templated
.buf_id_out (ucbif_ucb_buf_id_out[`UCB_BUF_HI-`UCB_BUF_LO:0]), // Templated
.data128 (ucbif_ucb_data128), // Templated
.data_out (ucbif_ucb_data_out[63:0]), // Templated
.int_vld (ucbif_ucb_int_vld), // Templated
.int_typ (ucbif_ucb_int_type), // Templated
.int_thr_id ({`UCB_THR_HI-`UCB_THR_LO+1{1'b0}}), // Templated
.dev_id (ucbif_ucb_dev_id), // Templated
.int_stat ({`UCB_INT_STAT_HI-`UCB_INT_STAT_LO+1{1'b0}}), // Templated
.int_vec ({`UCB_INT_VEC_HI-`UCB_INT_VEC_LO+1{1'b0}}), // Templated
.iob_ucb_stall(iob_jbi_spi_stall)); // Templated
jbi_ssi_ucbif u_ucbif (/*AUTOINST*/
// Outputs
.ucbif_ucb_req_acpted(ucbif_ucb_req_acpted),
.ucbif_ucb_rd_ack_vld(ucbif_ucb_rd_ack_vld),
.ucbif_ucb_rd_nack_vld(ucbif_ucb_rd_nack_vld),
.ucbif_ucb_ifill_ack_vld(ucbif_ucb_ifill_ack_vld),
.ucbif_ucb_ifill_nack_vld(ucbif_ucb_ifill_nack_vld),
.ucbif_ucb_thr_id_out(ucbif_ucb_thr_id_out[`UCB_THR_HI-`UCB_THR_LO:0]),
.ucbif_ucb_buf_id_out(ucbif_ucb_buf_id_out[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.ucbif_ucb_data128(ucbif_ucb_data128),
.ucbif_ucb_data_out(ucbif_ucb_data_out[63:0]),
.ucbif_ucb_int_vld(ucbif_ucb_int_vld),
.ucbif_ucb_int_type(ucbif_ucb_int_type[`UCB_PKT_WIDTH-1:0]),
.ucbif_ucb_dev_id(ucbif_ucb_dev_id[`UCB_INT_DEV_WIDTH-1:0]),
.ucbif_sif_vld (ucbif_sif_vld),
.ucbif_sif_rw (ucbif_sif_rw),
.ucbif_sif_size (ucbif_sif_size[`JBI_SSI_SZ_WIDTH-1:0]),
.ucbif_sif_addr (ucbif_sif_addr[`JBI_SSI_ADDR_WIDTH-1:0]),
.ucbif_sif_wdata(ucbif_sif_wdata[63:0]),
.ucbif_sif_rdata_accpt(ucbif_sif_rdata_accpt),
.ucbif_sif_timeout_accpt(ucbif_sif_timeout_accpt),
.ucbif_sif_timeval(ucbif_sif_timeval[`JBI_SSI_CSR_TOUT_TIMEVAL_WIDTH-1:0]),
// Inputs
.clk (clk),
.rst_l (rst_l),
.io_jbi_ext_int_l(io_jbi_ext_int_l),
.ucb_ucbif_rd_req_vld(ucb_ucbif_rd_req_vld),
.ucb_ucbif_ifill_req_vld(ucb_ucbif_ifill_req_vld),
.ucb_ucbif_wr_req_vld(ucb_ucbif_wr_req_vld),
.ucb_ucbif_thr_id_in(ucb_ucbif_thr_id_in[`UCB_THR_HI-`UCB_THR_LO:0]),
.ucb_ucbif_buf_id_in(ucb_ucbif_buf_id_in[`UCB_BUF_HI-`UCB_BUF_LO:0]),
.ucb_ucbif_size_in(ucb_ucbif_size_in[`UCB_SIZE_HI-`UCB_SIZE_LO:0]),
.ucb_ucbif_addr_in(ucb_ucbif_addr_in[`UCB_ADDR_HI-`UCB_ADDR_LO:0]),
.ucb_ucbif_data_in(ucb_ucbif_data_in[`UCB_DATA_HI-`UCB_DATA_LO:0]),
.ucb_ucbif_ack_busy(ucb_ucbif_ack_busy),
.ucb_ucbif_int_busy(ucb_ucbif_int_busy),
.sif_ucbif_busy (sif_ucbif_busy),
.sif_ucbif_rdata(sif_ucbif_rdata[63:0]),
.sif_ucbif_rdata_vld(sif_ucbif_rdata_vld),
.sif_ucbif_timeout(sif_ucbif_timeout),
.sif_ucbif_timeout_rw(sif_ucbif_timeout_rw),
.sif_ucbif_par_err(sif_ucbif_par_err));
jbi_ssi_sif u_sif (/*AUTOINST*/
// Outputs
.sif_ucbif_timeout (sif_ucbif_timeout),
.sif_ucbif_timeout_rw(sif_ucbif_timeout_rw),
.sif_ucbif_par_err (sif_ucbif_par_err),
.sif_ucbif_busy (sif_ucbif_busy),
.sif_ucbif_rdata (sif_ucbif_rdata[63:0]),
.sif_ucbif_rdata_vld (sif_ucbif_rdata_vld),
.jbi_io_ssi_mosi (jbi_io_ssi_mosi),
.jbi_io_ssi_sck (jbi_io_ssi_sck),
// Inputs
.clk (clk),
.rst_l (rst_l),
.arst_l (arst_l),
.ctu_jbi_ssiclk (ctu_jbi_ssiclk),
.ucbif_sif_timeval (ucbif_sif_timeval[`JBI_SSI_CSR_TOUT_TIMEVAL_WIDTH-1:0]),
.ucbif_sif_timeout_accpt(ucbif_sif_timeout_accpt),
.ucbif_sif_vld (ucbif_sif_vld),
.ucbif_sif_rw (ucbif_sif_rw),
.ucbif_sif_size (ucbif_sif_size[`JBI_SSI_SZ_WIDTH-1:0]),
.ucbif_sif_addr (ucbif_sif_addr[`JBI_SSI_ADDR_WIDTH-1:0]),
.ucbif_sif_wdata (ucbif_sif_wdata[63:0]),
.ucbif_sif_rdata_accpt(ucbif_sif_rdata_accpt),
.io_jbi_ssi_miso (io_jbi_ssi_miso));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/rtl/")
// verilog-auto-sense-defines-constant:t
// End:
|
// SPDX-License-Identifier: Apache-2.0
// Copyright 2018 Western Digital Corporation or it's affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//------------------------------------------------------------------------------------
//
// Copyright Western Digital, 2018
// Owner : Anusha Narayanamoorthy
// Description:
// Wrapper module for JTAG_TAP and DMI synchronizer
//
//-------------------------------------------------------------------------------------
module dmi_wrapper(
// JTAG signals
input trst_n, // JTAG reset
input tck, // JTAG clock
input tms, // Test mode select
input tdi, // Test Data Input
output tdo, // Test Data Output
output tdoEnable, // Test Data Output enable
// Processor Signals
input core_rst_n, // Core reset
input core_clk, // Core clock
input [31:1] jtag_id, // JTAG ID
input [31:0] rd_data, // 32 bit Read data from Processor
output [31:0] reg_wr_data, // 32 bit Write data to Processor
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
output reg_en, // 1 bit Read enable to Processor
output reg_wr_en, // 1 bit Write enable to Processor
output dmi_hard_reset
);
//Wire Declaration
wire rd_en;
wire wr_en;
wire dmireset;
//jtag_tap instantiation
rvjtag_tap i_jtag_tap(
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
.tck(tck), // dedicated JTAG TCK pad signal
.tms(tms), // dedicated JTAG TMS pad signal
.tdi(tdi), // dedicated JTAG TDI pad signal
.tdo(tdo), // dedicated JTAG TDO pad signal
.tdoEnable(tdoEnable), // enable for TDO pad
.wr_data(reg_wr_data), // 32 bit Write data
.wr_addr(reg_wr_addr), // 7 bit Write address
.rd_en(rd_en), // 1 bit read enable
.wr_en(wr_en), // 1 bit Write enable
.rd_data(rd_data), // 32 bit Read data
.rd_status(2'b0),
.idle(3'h0), // no need to wait to sample data
.dmi_stat(2'b0), // no need to wait or error possible
.version(4'h1), // debug spec 0.13 compliant
.jtag_id(jtag_id),
.dmi_hard_reset(dmi_hard_reset),
.dmi_reset(dmireset)
);
// dmi_jtag_to_core_sync instantiation
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
.wr_en(wr_en), // 1 bit Write enable
.rd_en(rd_en), // 1 bit Read enable
.rst_n(core_rst_n),
.clk(core_clk),
.reg_en(reg_en), // 1 bit Write interface bit
.reg_wr_en(reg_wr_en) // 1 bit Write enable
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4_4_V
`define SKY130_FD_SC_HD__OR4_4_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or4_4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4_4_V
|
//*****************************************************************************
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Application : MIG
// \ \ Filename : traffic_gen_top.v
// / / Date Last Modified : $Date: 2010/12/13 23:13:50 $
// /___/ /\ Date Created : Fri Mar 26 2010
// \ \ / \
// \___\/\___\
//
//Device : Virtex-7
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : This Traffic Gen supports both nCK_PER_CLK x4 mode and nCK_PER_CLK x2 mode for
// 7series MC UI Interface. The user bus datawidth has a equation: 2*nCK_PER_CLK*DQ_WIDTH.
//
//Reference :
//Revision History : 11/17 Adding CMD_GAP_DELAY to allow control of next command generation after current
// completion of burst command in user interface port.
//*****************************************************************************
`timescale 1ps/1ps
module traffic_gen_top #(
parameter TCQ = 100, // SIMULATION tCQ delay.
parameter SIMULATION = "FALSE",
parameter FAMILY = "VIRTEX7", // "SPARTAN6", "VIRTEX6", "VIRTEX7"
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands:
// "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE"
// "R_W_INSTR_MODE", "RP_WP_INSTR_MODE
// "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE"
// *******************************
// Virtex 6 Available commands:
// "R_W_INSTR_MODE"
// "FIXED_INSTR_R_MODE" - Only Read commands will be generated.
// "FIXED_INSTR_W_MODE" -- Only Write commands will be generated.
// "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated
// with lower 10 bits address in sequential increment.
// This mode is for Read Eye measurement.
parameter BL_WIDTH = 10, // Define User Interface Burst length width.
// For a maximum 128 continuous back_to_back command, set this to 8.
parameter nCK_PER_CLK = 4, // Memory Clock ratio to fabric clock.
parameter NUM_DQ_PINS = 4, // Total number of memory dq pins in the design.
parameter MEM_BURST_LEN = 8, // MEMROY Burst Length
parameter MEM_COL_WIDTH = 10, // Memory component column width.
parameter PORT_MODE = "BI_MODE",
parameter DATA_PATTERN = "DGEN_ALL", // Default is to generate all data pattern circuits.
parameter CMD_PATTERN = "CGEN_ALL", // Default is to generate all commands pattern circuits.
parameter DATA_WIDTH = 32, // User Interface Data Width
parameter ADDR_WIDTH = 32, // Command Address Bus width
parameter MASK_SIZE = DATA_WIDTH/8, //
parameter DATA_MODE = 4'b0010, // Default Data mode is set to Address as Data pattern.
// parameters define the address range
parameter BEGIN_ADDRESS = 32'h00000100,
parameter END_ADDRESS = 32'h000002ff,
parameter PRBS_EADDR_MASK_POS = 32'hfffffc00,
// debug parameters
parameter CMDS_GAP_DELAY = 6'd0, // CMDS_GAP_DELAY is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles
// after the last command.
parameter SEL_VICTIM_LINE = NUM_DQ_PINS, // VICTIM LINE is one of the DQ pins is selected to be always asserted when
// DATA MODE is hammer pattern. No VICTIM_LINE will be selected if
// SEL_VICTIM_LINE = NUM_DQ_PINS.
parameter EYE_TEST = "FALSE"
)
(
input clk,
input rst,
input manual_clear_error,
input memc_init_done,
input memc_cmd_full,
output memc_cmd_en,
output [2:0] memc_cmd_instr,
output [5:0] memc_cmd_bl,
output [31:0] memc_cmd_addr,
output memc_wr_en,
output memc_wr_end,
output [DATA_WIDTH/8 - 1:0] memc_wr_mask,
output [DATA_WIDTH - 1:0] memc_wr_data,
input memc_wr_full,
output memc_rd_en,
input [DATA_WIDTH - 1:0] memc_rd_data,
input memc_rd_empty,
// Signal declarations that can be connected to vio module
input vio_modify_enable,
input [3:0] vio_data_mode_value,
input [2:0] vio_addr_mode_value,
input [3:0] vio_instr_mode_value,
input [1:0] vio_bl_mode_value,
input [BL_WIDTH - 1:0] vio_fixed_bl_value,
input vio_data_mask_gen, // data_mask generation is only supported
// when data mode = address as data .
input [31:0] fixed_addr_i,
// User Specific data pattern interface that used when vio_data_mode vale = 1.4.9.
input [31:0] fixed_data_i,
input [31:0] simple_data0,
input [31:0] simple_data1,
input [31:0] simple_data2,
input [31:0] simple_data3,
input [31:0] simple_data4,
input [31:0] simple_data5,
input [31:0] simple_data6,
input [31:0] simple_data7,
// BRAM interface.
// bram bus formats:
// Only SP6 has been tested.
input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}}
input bram_valid_i,
output bram_rdy_o, //
// status feedback
output [DATA_WIDTH-1:0] cmp_data,
output cmp_data_valid,
output cmp_error,
output error, // asserted whenever the read back data is not correct.
output [64 + (2*DATA_WIDTH - 1):0] error_status
);
//p0 wire declarations
wire tg_run_traffic;
wire [31:0] tg_start_addr;
wire [31:0] tg_end_addr;
wire [31:0] tg_cmd_seed;
wire [31:0] tg_data_seed;
wire tg_load_seed;
wire [2:0] tg_addr_mode;
wire [3:0] tg_instr_mode;
wire [1:0] tg_bl_mode;
wire [3:0] tg_data_mode;
wire tg_mode_load;
wire [BL_WIDTH-1:0] tg_fixed_bl;
wire [2:0] tg_fixed_instr;
wire tg_addr_order;
wire [5:0] cmds_gap_delay_value;
wire tg_memc_wr_en;
wire mem_pattern_init_done;
// reg memc_init_done;
// assign tg_fixed_bl = 64;//{1'b1, {BL_WIDTH-1{1'b0}}} ;//* BURST_LENGTH;
// when in PRBS mode:
// assign tg_fixed_bl = 64;//{1'b1, {BL_WIDTH-1{1'b0}}} ;//* BURST_LENGTH;
// cmds_gap_delay_value is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles after the last command.
assign cmds_gap_delay_value = CMDS_GAP_DELAY;
localparam TG_FAMILY = ((FAMILY == "VIRTEX6") || (FAMILY == "VIRTEX7") || (FAMILY == "7SERIES")
|| (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ) ? "VIRTEX6" : "SPARTAN6";
assign tg_memc_wr_en = (TG_FAMILY == "VIRTEX6") ?memc_cmd_en & ~memc_cmd_full : memc_wr_en ;
// The following 'generate' statement activates the traffic generator for
// init_mem_pattern_ctr module instantiation for Port-0
init_mem_pattern_ctr #
(
.TCQ (TCQ),
.DWIDTH (DATA_WIDTH),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
// .nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.FAMILY (TG_FAMILY),
.BL_WIDTH (BL_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.CMD_SEED_VALUE (32'h56456783),
.DATA_SEED_VALUE (32'h12345678),
.DATA_MODE (DATA_MODE),
.PORT_MODE (PORT_MODE)
)
u_init_mem_pattern_ctr
(
.clk_i (clk),
.rst_i (rst),
.memc_cmd_en_i (memc_cmd_en),
.memc_wr_en_i (tg_memc_wr_en),
.vio_modify_enable (vio_modify_enable),
.vio_instr_mode_value (vio_instr_mode_value),
.vio_data_mode_value (vio_data_mode_value),
.vio_addr_mode_value (vio_addr_mode_value),
.vio_bl_mode_value (vio_bl_mode_value), // always set to PRBS_BL mode
.vio_fixed_bl_value (vio_fixed_bl_value), // always set to 64 in order to run PRBS data pattern
.vio_data_mask_gen (vio_data_mask_gen),
.memc_init_done_i (memc_init_done),
.cmp_error (error),
.run_traffic_o (tg_run_traffic),
.start_addr_o (tg_start_addr),
.end_addr_o (tg_end_addr),
.cmd_seed_o (tg_cmd_seed),
.data_seed_o (tg_data_seed),
.load_seed_o (tg_load_seed),
.addr_mode_o (tg_addr_mode),
.instr_mode_o (tg_instr_mode),
.bl_mode_o (tg_bl_mode),
.data_mode_o (tg_data_mode),
.mode_load_o (tg_mode_load),
.fixed_bl_o (tg_fixed_bl),
.fixed_instr_o (tg_fixed_instr),
.mem_pattern_init_done_o (mem_pattern_init_done)
);
// traffic generator instantiation for Port-0
memc_traffic_gen #
(
.TCQ (TCQ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.nCK_PER_CLK (nCK_PER_CLK),
.PORT_MODE (PORT_MODE),
.DWIDTH (DATA_WIDTH),
.FAMILY (TG_FAMILY),
.SIMULATION (SIMULATION),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN ),
.ADDR_WIDTH (ADDR_WIDTH),
.BL_WIDTH (BL_WIDTH),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.PRBS_SADDR_MASK_POS (BEGIN_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR (BEGIN_ADDRESS),
.PRBS_EADDR (END_ADDRESS),
.EYE_TEST (EYE_TEST)
)
u_memc_traffic_gen
(
.clk_i (clk),
.rst_i (rst),
.run_traffic_i (tg_run_traffic),
.manual_clear_error (manual_clear_error),
.cmds_gap_delay_value (cmds_gap_delay_value),
// runtime parameter
.mem_pattern_init_done_i (mem_pattern_init_done),
.start_addr_i (tg_start_addr),
.end_addr_i (tg_end_addr),
.cmd_seed_i (tg_cmd_seed),
.data_seed_i (tg_data_seed),
.load_seed_i (tg_load_seed),
.addr_mode_i (tg_addr_mode),
.instr_mode_i (tg_instr_mode),
.bl_mode_i (tg_bl_mode),
.data_mode_i (tg_data_mode),
.mode_load_i (tg_mode_load),
.wr_data_mask_gen_i (vio_data_mask_gen),
// fixed pattern inputs interface
.fixed_bl_i (tg_fixed_bl),
.fixed_instr_i (tg_fixed_instr),
.fixed_addr_i (fixed_addr_i),
.fixed_data_i (fixed_data_i),
// BRAM interface.
.bram_cmd_i (bram_cmd_i),
// .bram_addr_i (bram_addr_i ),
// .bram_instr_i ( bram_instr_i),
.bram_valid_i (bram_valid_i),
.bram_rdy_o (bram_rdy_o),
// MCB INTERFACE
.memc_cmd_en_o (memc_cmd_en),
.memc_cmd_instr_o (memc_cmd_instr),
.memc_cmd_bl_o (memc_cmd_bl),
.memc_cmd_addr_o (memc_cmd_addr),
.memc_cmd_full_i (memc_cmd_full),
.memc_wr_en_o (memc_wr_en),
.memc_wr_data_end_o (memc_wr_end),
.memc_wr_mask_o (memc_wr_mask),
.memc_wr_data_o (memc_wr_data),
.memc_wr_full_i (memc_wr_full),
.memc_rd_en_o (memc_rd_en),
.memc_rd_data_i (memc_rd_data),
.memc_rd_empty_i (memc_rd_empty),
.qdr_wr_cmd_o (),
.qdr_rd_cmd_o (),
// status feedback
.counts_rst (rst),
.wr_data_counts (),
.rd_data_counts (),
.error (error), // asserted whenever the read back data is not correct.
.error_status (error_status), // TBD how signals mapped
.cmp_data (cmp_data),
.cmp_data_valid (cmp_data_valid),
.cmp_error (cmp_error),
.mem_rd_data (),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.dq_error_bytelane_cmp (),
.cumlative_dq_lane_error (),
.cumlative_dq_r0_bit_error (),
.cumlative_dq_f0_bit_error (),
.cumlative_dq_r1_bit_error (),
.cumlative_dq_f1_bit_error (),
.dq_r0_bit_error_r (),
.dq_f0_bit_error_r (),
.dq_r1_bit_error_r (),
.dq_f1_bit_error_r (),
.dq_r0_read_bit (),
.dq_f0_read_bit (),
.dq_r1_read_bit (),
.dq_f1_read_bit (),
.dq_r0_expect_bit (),
.dq_f0_expect_bit (),
.dq_r1_expect_bit (),
.dq_f1_expect_bit (),
.error_addr ()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A211OI_BEHAVIORAL_PP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, B1, C1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_BEHAVIORAL_PP_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_auto_pc_2 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// ghrd_10as066n2_emif_hps.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_emif_hps (
input wire global_reset_n, // global_reset_reset_sink.reset_n
input wire [4095:0] hps_to_emif, // hps_emif_conduit_end.hps_to_emif
output wire [4095:0] emif_to_hps, // .emif_to_hps
input wire [1:0] hps_to_emif_gp, // .gp_to_emif
output wire [0:0] emif_to_hps_gp, // .emif_to_gp
output wire [0:0] mem_ck, // mem_conduit_end.mem_ck
output wire [0:0] mem_ck_n, // .mem_ck_n
output wire [16:0] mem_a, // .mem_a
output wire [0:0] mem_act_n, // .mem_act_n
output wire [1:0] mem_ba, // .mem_ba
output wire [0:0] mem_bg, // .mem_bg
output wire [0:0] mem_cke, // .mem_cke
output wire [0:0] mem_cs_n, // .mem_cs_n
output wire [0:0] mem_odt, // .mem_odt
output wire [0:0] mem_reset_n, // .mem_reset_n
output wire [0:0] mem_par, // .mem_par
input wire [0:0] mem_alert_n, // .mem_alert_n
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dbi_n, // .mem_dbi_n
input wire oct_rzqin, // oct_conduit_end.oct_rzqin
input wire pll_ref_clk // pll_ref_clk_clock_sink.clk
);
ghrd_10as066n2_emif_hps_altera_emif_a10_hps_171_or5co3i emif_hps (
.global_reset_n (global_reset_n), // input, width = 1, global_reset_reset_sink.reset_n
.hps_to_emif (hps_to_emif), // input, width = 4096, hps_emif_conduit_end.hps_to_emif
.emif_to_hps (emif_to_hps), // output, width = 4096, .emif_to_hps
.hps_to_emif_gp (hps_to_emif_gp), // input, width = 2, .gp_to_emif
.emif_to_hps_gp (emif_to_hps_gp), // output, width = 1, .emif_to_gp
.mem_ck (mem_ck), // output, width = 1, mem_conduit_end.mem_ck
.mem_ck_n (mem_ck_n), // output, width = 1, .mem_ck_n
.mem_a (mem_a), // output, width = 17, .mem_a
.mem_act_n (mem_act_n), // output, width = 1, .mem_act_n
.mem_ba (mem_ba), // output, width = 2, .mem_ba
.mem_bg (mem_bg), // output, width = 1, .mem_bg
.mem_cke (mem_cke), // output, width = 1, .mem_cke
.mem_cs_n (mem_cs_n), // output, width = 1, .mem_cs_n
.mem_odt (mem_odt), // output, width = 1, .mem_odt
.mem_reset_n (mem_reset_n), // output, width = 1, .mem_reset_n
.mem_par (mem_par), // output, width = 1, .mem_par
.mem_alert_n (mem_alert_n), // input, width = 1, .mem_alert_n
.mem_dqs (mem_dqs), // inout, width = 4, .mem_dqs
.mem_dqs_n (mem_dqs_n), // inout, width = 4, .mem_dqs_n
.mem_dq (mem_dq), // inout, width = 32, .mem_dq
.mem_dbi_n (mem_dbi_n), // inout, width = 4, .mem_dbi_n
.oct_rzqin (oct_rzqin), // input, width = 1, oct_conduit_end.oct_rzqin
.pll_ref_clk (pll_ref_clk) // input, width = 1, pll_ref_clk_clock_sink.clk
);
endmodule
|
//
// usb 3.0 data scrambling lfsr
//
// Copyright (C) 2009 OutputLogic.com
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
module usb3_lfsr (
input wire clock,
input wire reset_n,
input wire [31:0] data_in,
input wire scram_en,
input wire scram_rst,
input wire [15:0] scram_init,
output reg [31:0] data_out,
output reg [31:0] data_out_reg
);
reg [15:0] lfsr_q, lfsr_c;
reg [31:0] data_c;
always @(*) begin
lfsr_c[0] = lfsr_q[0] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[10];
lfsr_c[1] = lfsr_q[1] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[11];
lfsr_c[2] = lfsr_q[2] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[12];
lfsr_c[3] = lfsr_q[3] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[13];
lfsr_c[4] = lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14];
lfsr_c[5] = lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[15];
lfsr_c[6] = lfsr_q[0] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[13] ^ lfsr_q[14];
lfsr_c[7] = lfsr_q[1] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[14] ^ lfsr_q[15];
lfsr_c[8] = lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[12] ^ lfsr_q[15];
lfsr_c[9] = lfsr_q[1] ^ lfsr_q[3] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[13];
lfsr_c[10] = lfsr_q[0] ^ lfsr_q[2] ^ lfsr_q[4] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[14];
lfsr_c[11] = lfsr_q[1] ^ lfsr_q[3] ^ lfsr_q[5] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[15];
lfsr_c[12] = lfsr_q[2] ^ lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14];
lfsr_c[13] = lfsr_q[3] ^ lfsr_q[5] ^ lfsr_q[7] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15];
lfsr_c[14] = lfsr_q[4] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[14] ^ lfsr_q[15];
lfsr_c[15] = lfsr_q[5] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[15];
data_c[0] = data_in[0] ^ lfsr_q[15];
data_c[1] = data_in[1] ^ lfsr_q[14];
data_c[2] = data_in[2] ^ lfsr_q[13];
data_c[3] = data_in[3] ^ lfsr_q[12];
data_c[4] = data_in[4] ^ lfsr_q[11];
data_c[5] = data_in[5] ^ lfsr_q[10];
data_c[6] = data_in[6] ^ lfsr_q[9];
data_c[7] = data_in[7] ^ lfsr_q[8];
data_c[8] = data_in[8] ^ lfsr_q[7];
data_c[9] = data_in[9] ^ lfsr_q[6];
data_c[10] = data_in[10] ^ lfsr_q[5];
data_c[11] = data_in[11] ^ lfsr_q[4] ^ lfsr_q[15];
data_c[12] = data_in[12] ^ lfsr_q[3] ^ lfsr_q[14] ^ lfsr_q[15];
data_c[13] = data_in[13] ^ lfsr_q[2] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15];
data_c[14] = data_in[14] ^ lfsr_q[1] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14];
data_c[15] = data_in[15] ^ lfsr_q[0] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13];
data_c[16] = data_in[16] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[15];
data_c[17] = data_in[17] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[14];
data_c[18] = data_in[18] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[13];
data_c[19] = data_in[19] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[12];
data_c[20] = data_in[20] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[11];
data_c[21] = data_in[21] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[7] ^ lfsr_q[10];
data_c[22] = data_in[22] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[6] ^ lfsr_q[9] ^ lfsr_q[15];
data_c[23] = data_in[23] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[5] ^ lfsr_q[8] ^ lfsr_q[14];
data_c[24] = data_in[24] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[4] ^ lfsr_q[7] ^ lfsr_q[13] ^ lfsr_q[15];
data_c[25] = data_in[25] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[3] ^ lfsr_q[6] ^ lfsr_q[12] ^ lfsr_q[14];
data_c[26] = data_in[26] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[2] ^ lfsr_q[5] ^ lfsr_q[11] ^ lfsr_q[13] ^ lfsr_q[15];
data_c[27] = data_in[27] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[4] ^ lfsr_q[10] ^ lfsr_q[12] ^ lfsr_q[14];
data_c[28] = data_in[28] ^ lfsr_q[0] ^ lfsr_q[3] ^ lfsr_q[9] ^ lfsr_q[11] ^ lfsr_q[13];
data_c[29] = data_in[29] ^ lfsr_q[2] ^ lfsr_q[8] ^ lfsr_q[10] ^ lfsr_q[12];
data_c[30] = data_in[30] ^ lfsr_q[1] ^ lfsr_q[7] ^ lfsr_q[9] ^ lfsr_q[11];
data_c[31] = data_in[31] ^ lfsr_q[0] ^ lfsr_q[6] ^ lfsr_q[8] ^ lfsr_q[10];
//data_out = scram_en ? data_c : data_out;
data_out = data_c;
end
always @(posedge clock) begin
if(~reset_n) begin
lfsr_q <= scram_init;
data_out_reg <= 32'h0;
end else begin
lfsr_q <= scram_rst ? scram_init : scram_en ? lfsr_c : lfsr_q;
data_out_reg <= scram_en ? data_c : data_out_reg;
end
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file blk_mem_gen_v6_2.v when simulating
// the core, blk_mem_gen_v6_2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module blk_mem_gen_v6_2(
clka,
addra,
douta
);
input clka;
input [11 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(1),
.C_DISABLE_WARN_BHV_RANGE(1),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("blk_mem_gen_v6_2.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// File : ../RTL/hostController/sendpacketarbiter.v
// Generated : 11/10/06 05:37:20
// From : ../RTL/hostController/sendpacketarbiter.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// sendpacketarbiter
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbConstants_h.v"
module sendPacketArbiter (HCTxGnt, HCTxReq, HC_PID, HC_SP_WEn, SOFTxGnt, SOFTxReq, SOF_SP_WEn, clk, rst, sendPacketPID, sendPacketWEnable);
input HCTxReq;
input [3:0] HC_PID;
input HC_SP_WEn;
input SOFTxReq;
input SOF_SP_WEn;
input clk;
input rst;
output HCTxGnt;
output SOFTxGnt;
output [3:0] sendPacketPID;
output sendPacketWEnable;
reg HCTxGnt, next_HCTxGnt;
wire HCTxReq;
wire [3:0] HC_PID;
wire HC_SP_WEn;
reg SOFTxGnt, next_SOFTxGnt;
wire SOFTxReq;
wire SOF_SP_WEn;
wire clk;
wire rst;
reg [3:0] sendPacketPID, next_sendPacketPID;
reg sendPacketWEnable, next_sendPacketWEnable;
// diagram signals declarations
reg muxSOFNotHC, next_muxSOFNotHC;
// BINARY ENCODED state machine: sendPktArb
// State codes definitions:
`define HC_ACT 2'b00
`define SOF_ACT 2'b01
`define SARB_WAIT_REQ 2'b10
`define START_SARB 2'b11
reg [1:0] CurrState_sendPktArb;
reg [1:0] NextState_sendPktArb;
// Diagram actions (continuous assignments allowed only: assign ...)
// hostController/SOFTransmit mux
always @(muxSOFNotHC or SOF_SP_WEn or HC_SP_WEn or HC_PID)
begin
if (muxSOFNotHC == 1'b1)
begin
sendPacketWEnable <= SOF_SP_WEn;
sendPacketPID <= `SOF;
end
else
begin
sendPacketWEnable <= HC_SP_WEn;
sendPacketPID <= HC_PID;
end
end
//--------------------------------------------------------------------
// Machine: sendPktArb
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (HCTxReq or SOFTxReq or HCTxGnt or SOFTxGnt or muxSOFNotHC or CurrState_sendPktArb)
begin : sendPktArb_NextState
NextState_sendPktArb <= CurrState_sendPktArb;
// Set default values for outputs and signals
next_HCTxGnt <= HCTxGnt;
next_SOFTxGnt <= SOFTxGnt;
next_muxSOFNotHC <= muxSOFNotHC;
case (CurrState_sendPktArb)
`HC_ACT:
if (HCTxReq == 1'b0)
begin
NextState_sendPktArb <= `SARB_WAIT_REQ;
next_HCTxGnt <= 1'b0;
end
`SOF_ACT:
if (SOFTxReq == 1'b0)
begin
NextState_sendPktArb <= `SARB_WAIT_REQ;
next_SOFTxGnt <= 1'b0;
end
`SARB_WAIT_REQ:
if (SOFTxReq == 1'b1)
begin
NextState_sendPktArb <= `SOF_ACT;
next_SOFTxGnt <= 1'b1;
next_muxSOFNotHC <= 1'b1;
end
else if (HCTxReq == 1'b1)
begin
NextState_sendPktArb <= `HC_ACT;
next_HCTxGnt <= 1'b1;
next_muxSOFNotHC <= 1'b0;
end
`START_SARB:
NextState_sendPktArb <= `SARB_WAIT_REQ;
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : sendPktArb_CurrentState
if (rst)
CurrState_sendPktArb <= `START_SARB;
else
CurrState_sendPktArb <= NextState_sendPktArb;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : sendPktArb_RegOutput
if (rst)
begin
muxSOFNotHC <= 1'b0;
SOFTxGnt <= 1'b0;
HCTxGnt <= 1'b0;
end
else
begin
muxSOFNotHC <= next_muxSOFNotHC;
SOFTxGnt <= next_SOFTxGnt;
HCTxGnt <= next_HCTxGnt;
end
end
endmodule
|
module asr(value1, value2, shift_hex, value_out, EN);
input [31:0] value1, value2;
input [3:0] shift_hex;
output [31:0] value_out;
input EN;
wire or_unary = |value2[31:5];
wire value2_shrink = value2[4:0];
wire [4:0] shift_amt = (value2_shrink== 32'b0) ?
( {1'b0, shift_hex} + 5'b1) : (value2_shrink + {1'b0, shift_hex});
assign value_out = (or_unary==1'b1) ? 32'b0 : (
(shift_amt == 5'b00000) ? value1[31:0] :
(shift_amt == 5'b00001) ? {{01{value1[31]}}, value1[31:01]} :
(shift_amt == 5'b00010) ? {{02{value1[31]}}, value1[31:02]} :
(shift_amt == 5'b00011) ? {{03{value1[31]}}, value1[31:03]} :
(shift_amt == 5'b00100) ? {{04{value1[31]}}, value1[31:04]} :
(shift_amt == 5'b00101) ? {{05{value1[31]}}, value1[31:05]} :
(shift_amt == 5'b00110) ? {{06{value1[31]}}, value1[31:06]} :
(shift_amt == 5'b00111) ? {{07{value1[31]}}, value1[31:07]} :
(shift_amt == 5'b01000) ? {{08{value1[31]}}, value1[31:08]} :
(shift_amt == 5'b01001) ? {{09{value1[31]}}, value1[31:09]} :
(shift_amt == 5'b01010) ? {{10{value1[31]}}, value1[31:10]} :
(shift_amt == 5'b01011) ? {{11{value1[31]}}, value1[31:11]} :
(shift_amt == 5'b01100) ? {{12{value1[31]}}, value1[31:12]} :
(shift_amt == 5'b01101) ? {{13{value1[31]}}, value1[31:13]} :
(shift_amt == 5'b01110) ? {{14{value1[31]}}, value1[31:14]} :
(shift_amt == 5'b01111) ? {{15{value1[31]}}, value1[31:15]} :
(shift_amt == 5'b10000) ? {{16{value1[31]}}, value1[31:16]} :
(shift_amt == 5'b10001) ? {{17{value1[31]}}, value1[31:17]} :
(shift_amt == 5'b10010) ? {{18{value1[31]}}, value1[31:18]} :
(shift_amt == 5'b10011) ? {{19{value1[31]}}, value1[31:19]} :
(shift_amt == 5'b10100) ? {{20{value1[31]}}, value1[31:20]} :
(shift_amt == 5'b10101) ? {{21{value1[31]}}, value1[31:21]} :
(shift_amt == 5'b10110) ? {{22{value1[31]}}, value1[31:22]} :
(shift_amt == 5'b10111) ? {{23{value1[31]}}, value1[31:23]} :
(shift_amt == 5'b11000) ? {{24{value1[31]}}, value1[31:24]} :
(shift_amt == 5'b11001) ? {{25{value1[31]}}, value1[31:25]} :
(shift_amt == 5'b11010) ? {{26{value1[31]}}, value1[31:26]} :
(shift_amt == 5'b11011) ? {{27{value1[31]}}, value1[31:27]} :
(shift_amt == 5'b11100) ? {{28{value1[31]}}, value1[31:28]} :
(shift_amt == 5'b11101) ? {{29{value1[31]}}, value1[31:29]} :
(shift_amt == 5'b11110) ? {{30{value1[31]}}, value1[31:30]} :
(shift_amt == 5'b11111) ? {{31{value1[31]}}, value1[31]} : 32'b0);
endmodule
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// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Module: BIOSROM.v
// Description: Wishbone Compatible BIOS ROM core
// The following is to get rid of the warning about not initializing the ROM
// altera message_off 10030
// --------------------------------------------------------------------
// --------------------------------------------------------------------
module BIOSROM(
input wb_clk_i, // Wishbone slave interface
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
input [ 1:0] wb_sel_i,
output reg wb_ack_o
);
wire ack_o = wb_stb_i & wb_cyc_i;
always @(posedge wb_clk_i) wb_ack_o <= ack_o;
reg [15:0] rom[0:127]; // Instantiate the ROM
initial $readmemh("biosrom.hex", rom);
wire [ 6:0] rom_addr = wb_adr_i[7:1];
wire [15:0] rom_dat = rom[rom_addr];
assign wb_dat_o = rom_dat;
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
// MBT 8-18-2014
//
// Takes num_in_p channels and then
// blocking round robin transmits the words across num_out_p channels.
//
//
// Interface: valid/yumi on input; and ready/valid on output.
//
// Example: 10 byte-wide channels in, and 4 byte-wide channels out.
// 4 byte-wide channels in, and 10 byte-wide channels out.
//
//
// bsg_rr_f2f_input
//
// this takes a number of input channel data and valid signals
// rotates them so that highest priority channel is at position 0
// the next highest at 1, etc. this is the so called "intermediate"
// representation; where channels are reordered accord to round-robin
// priority.
//
// the module also rotates a set of yumi signals from the intermediate
// representation (go_channels_i) back to the input representation
// to facilitate dequeing from those original input channels.
//
//`include "bsg_defines.v"
module bsg_rr_f2f_input #(parameter `BSG_INV_PARAM( width_p )
, parameter num_in_p = 0
, parameter middle_meet_p = 0
, parameter middle_meet_data_lp = middle_meet_p * width_p
, parameter min_in_middle_meet_p = `BSG_MIN(num_in_p,middle_meet_p)
)
(input clk, input reset
// primary input
, input [num_in_p-1:0] valid_i
, input [width_p-1:0] data_i [num_in_p-1:0]
// to intermediate module; only send as many as middle will look at
// note: middle_meet may be < num_in_p because num_out_p < num_in_p
// middle_meet may be > num_in_p because other input modules may have greater num_in_p
, output [width_p-1:0] data_head_o [middle_meet_p-1:0]
, output [middle_meet_p-1:0] valid_head_o
// from intermediate module
, input [min_in_middle_meet_p-1:0] go_channels_i
// may be smaller than middle_meet because any sends are
// limited by how many one's we output
, input [$clog2(min_in_middle_meet_p+1)-1:0] go_cnt_i
// final output
, output [num_in_p-1:0] yumi_o
);
logic [`BSG_SAFE_CLOG2(num_in_p)-1:0] iptr_r, iptr_r_data;
wire [width_p*num_in_p-1:0] data_i_flat = ({ >> {data_i} });
wire [width_p*middle_meet_p-1:0] data_head_o_flat;
// 2D array format converters
//bsg_flatten_2D_array #(.width_p(width_p), .items_p(num_in_p))
//bf2Da (.i(data_i), .o(data_i_flat));
bsg_make_2D_array #(.width_p(width_p), .items_p(middle_meet_p))
bm2Da (.i(data_head_o_flat), .o(data_head_o));
// rotate the valid and data vectors from incoming channel
wire [num_in_p-1:0] valid_head_o_pretrunc;
bsg_rotate_right #(.width_p(num_in_p)) valid_rr (.data_i(valid_i), .rot_i(iptr_r), .o(valid_head_o_pretrunc));
wire [2*width_p*num_in_p-1:0] data_head_o_flat_pretrunc
= { 2 { data_i_flat } } >> (iptr_r_data*width_p);
wire [num_in_p*2-1:0] yumi_intermediate;
// rotate the yumi and valid signal to account for round-robin
if (num_in_p >= middle_meet_p)
begin
assign valid_head_o = valid_head_o_pretrunc [0+:middle_meet_p ];
assign data_head_o_flat = data_head_o_flat_pretrunc[0+:width_p*middle_meet_p];
assign yumi_intermediate = { 2 { num_in_p ' (go_channels_i) } } << iptr_r;
end
else
begin
assign valid_head_o = middle_meet_p ' (valid_head_o_pretrunc [0+:num_in_p ]);
assign data_head_o_flat = middle_meet_data_lp ' (data_head_o_flat_pretrunc[0+:width_p*num_in_p]);
assign yumi_intermediate = { 2 { go_channels_i } } << iptr_r;
end
assign yumi_o = yumi_intermediate[num_in_p +:num_in_p];
bsg_circular_ptr #(.slots_p(num_in_p)
,.max_add_p(min_in_middle_meet_p)
) c_ptr
(.reset_i(reset), .clk(clk)
,.add_i(go_cnt_i)
,.o(iptr_r)
,.n_o()
);
// we duplicate this logic for physical design because control and data do not always belong together
bsg_circular_ptr #(.slots_p(num_in_p)
,.max_add_p(min_in_middle_meet_p)
) c_ptr_data
(.reset_i(reset), .clk(clk)
,.add_i(go_cnt_i)
,.o(iptr_r_data)
,.n_o()
);
endmodule // bsg_rr_f2f_input
// bsg_rr_f2f_output
//
// this takes a number of output channel ready signals and
// rotates them to the intermediate representation (highest = 0)
// according to their priority.
// the intermediate module takes these output ready signals, combines
// with the input channel's valid signals to derive a set of
// "go" intermediate signals. these are shifted by this module
// to align with the output channels.
// the module also takes the input channel data at the intermediate
// representation and shifts it to align with output channels
// according to priority.
module bsg_rr_f2f_output #(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(num_out_p)
,parameter `BSG_INV_PARAM(middle_meet_p)
,parameter min_out_middle_meet_lp = `BSG_MIN(num_out_p,middle_meet_p)
)
(input clk, input reset
// primary input
, input [num_out_p-1:0] ready_i
// out to intermediate module
, output [middle_meet_p-1:0] ready_head_o
// in from intermediate module
, input [min_out_middle_meet_lp-1:0] go_channels_i
, input [$clog2(min_out_middle_meet_lp+1)-1:0] go_cnt_i
, input [width_p-1:0] data_head_i[min_out_middle_meet_lp-1:0]
// final output
, output [num_out_p-1:0] valid_o
, output [width_p-1:0] data_o [num_out_p-1:0]
);
logic [`BSG_SAFE_CLOG2(num_out_p)-1:0] optr_r, optr_r_data;
// instantiate module so we can cluster this logic in physical design
// wire [num_out_p*2-1:0] ready_head_o_pretr = { 2 { ready_i } } >> optr_r;
wire [num_out_p-1:0] ready_head_o_pretr;
bsg_rotate_right #(.width_p(num_out_p)) ready_rr (.data_i(ready_i), .rot_i(optr_r), .o(ready_head_o_pretr));
wire [num_out_p*2-1:0] valid_pretr;
if (num_out_p >= middle_meet_p)
begin
assign ready_head_o = ready_head_o_pretr[0+:middle_meet_p];
assign valid_pretr = { 2 { num_out_p ' (go_channels_i) } } << optr_r;
end
else
begin
assign ready_head_o = middle_meet_p ' (ready_head_o_pretr[0+:num_out_p]);
assign valid_pretr = {2 { go_channels_i } } << optr_r;
end
assign valid_o = valid_pretr[num_out_p+:num_out_p];
genvar i;
wire [width_p-1:0] data_head_double [num_out_p*2-1:0];
for (i = 0; i < num_out_p; i=i+1)
begin
if (i < middle_meet_p)
begin
assign data_head_double[i] = data_head_i[i];
assign data_head_double[i+num_out_p] = data_head_i[i];
end
else
begin
assign data_head_double[i] = width_p ' (0);
assign data_head_double[i+num_out_p] = width_p ' (0);
end
assign data_o[i] = data_head_double[(i+num_out_p)-optr_r_data];
end
bsg_circular_ptr #(.slots_p(num_out_p)
,.max_add_p(min_out_middle_meet_lp)
) c_ptr
(.clk(clk), .reset_i(reset)
,.add_i(go_cnt_i)
,.o(optr_r)
,.n_o()
);
// duplicate logic for physical design
bsg_circular_ptr #(.slots_p(num_out_p)
,.max_add_p(min_out_middle_meet_lp)
) c_ptr_data
(.clk(clk), .reset_i(reset)
,.add_i(go_cnt_i)
,.o(optr_r_data)
,.n_o()
);
endmodule
// bsg_rr_f2f_middle
//
// this intermediate module takes the input valids
// and the output readies and derives the go_channel signals.
// it ensures that only a continuous run of channels are
// selected to "go", ensuring a true rigid round-robin priority
// on both inputs and outputs.
module bsg_rr_f2f_middle #(parameter `BSG_INV_PARAM(width_p)
, parameter middle_meet_p=1
, parameter use_popcount_p=0
)
(input [middle_meet_p-1:0] valid_head_i
, input [middle_meet_p-1:0] ready_head_i
, output [middle_meet_p-1:0] go_channels_o
, output [$clog2(middle_meet_p+1)-1:0] go_cnt_o
);
wire [middle_meet_p-1:0] happy_channels = valid_head_i & ready_head_i;
wire [middle_meet_p-1:0] go_channels_int;
bsg_scan #(.width_p(middle_meet_p)
,.and_p(1)
,.lo_to_hi_p(1)
) and_scan (.i(happy_channels), .o(go_channels_int));
assign go_channels_o = go_channels_int;
// speedfix: this hack helps the critical path but net impact is fairly
// small (.04 ns in tsmc 250)
// it implements a priority encoder based on
// both the original pattern and the scan.
if (0)
// if (middle_meet_p==4)
begin
wire hi11 = &happy_channels[3:2];
wire lo01 = ~happy_channels[1] & happy_channels[0];
wire hi01 = ~happy_channels[3] & happy_channels[2];
assign go_cnt_o[2] = go_channels_int[3];
assign go_cnt_o[1] = ~hi11 & go_channels_int[1];
assign go_cnt_o[0] = lo01 | (go_channels_int[1] & hi01);
end
else
begin
if (use_popcount_p)
bsg_popcount #(.width_p(middle_meet_p)) pop (.i(go_channels_int), .o(go_cnt_o));
else
bsg_thermometer_count #(.width_p(middle_meet_p)) thermo (.i(go_channels_int), .o(go_cnt_o));
end
endmodule
// bsg_round_robin_fifo_to_fifo
//
// at its simplest, this module instantiates the appropriate
// input, intermediate and output modules
// to create a complete round-robin fifo-to-fifo
// transfer engine.
//
// the module also supports variable numbers of input
// and output channels. it does this by using parameter masks to
// specific which input and output modules should be instantiated.
//
// inputs in_top_channel_i and out_top_channel_i allow the number
// of channels to change semi-dynamically (it is advisable to
// empty both inputs and outputs channels before doing so.)
//
module bsg_round_robin_fifo_to_fifo
#(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(num_in_p)
,parameter num_out_p=1
// bitvector; set bit "X" if you want to
// support a mode where a subset X of channels are enabled
// note each bit set adds a couple of shifters
// so this is not free. default is to not support any subsets
,parameter in_channel_count_mask_p = (1 << (num_in_p-1))
,parameter out_channel_count_mask_p = (1 << (num_out_p-1))
)
(input clk, input reset
// input side
, input [num_in_p-1:0] valid_i
, input [width_p-1:0] data_i [num_in_p-1:0]
, output [num_in_p-1:0] yumi_o
// high water mark of how many total channels are activated.
// e.g; if one channel is activated, it would be at 0.
, input [`BSG_MAX($clog2(num_in_p)-1,0):0] in_top_channel_i
, input [`BSG_MAX($clog2(num_out_p)-1,0):0] out_top_channel_i
// output side
, output [num_out_p-1:0] valid_o
, output [width_p-1:0] data_o [num_out_p-1:0]
, input [num_out_p-1:0] ready_i
);
localparam middle_meet_lp= `BSG_MIN(num_in_p,num_out_p);
wire [middle_meet_lp-1:0] go_channels;
wire [middle_meet_lp*width_p-1:0] data_head [num_in_p-1:0];
wire [middle_meet_lp-1:0] valid_head [num_in_p-1:0];
wire [middle_meet_lp-1:0] ready_head [num_out_p-1:0];
wire [num_in_p-1:0] yumi_int_o [num_in_p-1:0];
wire [num_out_p-1:0] valid_int_o[num_out_p-1:0];
wire [width_p*num_out_p-1:0] data_int_o[num_out_p-1:0];
// this is for supporting variable numbers of active
// input and output channels
assign yumi_o = yumi_int_o[in_top_channel_i];
assign valid_o = valid_int_o[out_top_channel_i];
typedef logic [width_p*num_out_p-1:0] bsg_round_robin_fifo_to_fifo_t;
wire [width_p*num_out_p-1:0] data_o_flat = data_int_o[out_top_channel_i];
bsg_round_robin_fifo_to_fifo_t zero_flat;
wire [$clog2(middle_meet_lp+1)-1:0] go_cnt;
assign zero_flat = bsg_round_robin_fifo_to_fifo_t ' (0);
// 2D array format converters
// bsg_flatten_2D_array #(.width_p(width_p), .items_p(num_in_p)) bf2Da (.i(data_i), .o(data_i_flat));
bsg_make_2D_array #(.width_p(width_p), .items_p(num_out_p))
bm2Da (.i(data_o_flat), .o(data_o));
genvar i,j;
// we generate separate input side logic to handle
// different numbers of input channels
for (i = 0; i < num_in_p; i++)
begin: ic
if (in_channel_count_mask_p[i])
begin : in_chan
wire [width_p-1:0] data_head_tmp [middle_meet_lp-1:0];
//bsg_flatten_2D_array #(.width_p(width_p), .items_p(middle_meet_lp))
//bf2Da (.i(data_head_tmp),.o(data_head[i]));
assign data_head[i] = { >> {data_head_tmp} };
// INPUT SIDE (input: valid_i, data_i; middle input; go_channels)
bsg_rr_f2f_input #(.width_p(width_p)
,.num_in_p(i+1)
,.middle_meet_p(middle_meet_lp)
) bsg_rr_ff_in
(.clk(clk), .reset(reset | (in_top_channel_i != i))
, .valid_i(valid_i[i:0]) // inputs
, .data_i(data_i[i:0])
, .data_head_o(data_head_tmp) // back to us
,. valid_head_o(valid_head[i])
, .go_channels_i(go_channels[`BSG_MIN(i+1,middle_meet_lp)-1:0]) // back to them
, .go_cnt_i(go_cnt[$clog2(`BSG_MIN(i+1,middle_meet_lp)+1)-1:0])
, .yumi_o(yumi_int_o[i][i:0]) // final output
);
// MBT: this is redundant with the cast inside bsg_rr_f2f_input
// and results in a synthesis warning
/*
for (j = i+1; j < middle_meet_lp; j=j+1)
begin
assign valid_head[i][j] = 1'b0;
end
*/
for (j = i+1; j < num_in_p; j=j+1)
begin
assign yumi_int_o[i][j] = 1'b0;
end
end // if (in_channel_count_mask_p[i])
end // block: c
// MIDDLE (ties INPUT to OUTPUT)
bsg_rr_f2f_middle #(.width_p(width_p)
,.middle_meet_p(middle_meet_lp)
) brrf2fm
(.valid_head_i(valid_head[in_top_channel_i])
, .ready_head_i(ready_head[out_top_channel_i])
, .go_channels_o(go_channels)
, .go_cnt_o(go_cnt)
);
// OUTPUT SIDE
for (i = 0; i < num_out_p; i++)
begin: oc
if (out_channel_count_mask_p[i])
begin: out_chan
wire [width_p-1:0] data_head_array [`BSG_MIN(i+1,middle_meet_lp)-1:0];
wire [width_p-1:0] data_o_array [i:0];
bsg_make_2D_array #(.width_p(width_p), .items_p(`BSG_MIN(i+1,middle_meet_lp)))
bm2Da (.i( data_head[in_top_channel_i][0+:`BSG_MIN(i+1,middle_meet_lp)*width_p])
,.o(data_head_array));
//bsg_flatten_2D_array #(.width_p(width_p), .items_p(i+1))
//bf2Da (.i(data_o_array), .o(data_int_o[i][width_p*(i+1)-1:0]));
assign data_int_o[i][width_p*(i+1)-1:0] = { >> {data_o_array}};
bsg_rr_f2f_output #(.width_p(width_p)
,.num_out_p(i+1)
,.middle_meet_p(middle_meet_lp)
) bsg_rr_ff_out
(.clk(clk), .reset(reset | (out_top_channel_i != i))
, .ready_i(ready_i[i:0])
, .ready_head_o(ready_head[i]) // back to us
, .go_channels_i(go_channels[`BSG_MIN(i+1,middle_meet_lp)-1:0]) // back to them
, .go_cnt_i(go_cnt[$clog2(`BSG_MIN(i+1,middle_meet_lp)+1)-1:0])
, .data_head_i(data_head_array)
, .valid_o(valid_int_o[i][i:0]) // final outputs
, .data_o(data_o_array)
);
for (j = i+1; j < num_out_p; j=j+1)
begin
assign valid_int_o[i][j] = 1'b0;
end
if (num_out_p - i > 1)
assign data_int_o[i][width_p*num_out_p-1:width_p*(i+1)]
= zero_flat[0+: (width_p*(num_out_p-(i+1)))];
end // block: iff
end // block: c
endmodule // bsg_assembler_out
`BSG_ABSTRACT_MODULE(bsg_round_robin_fifo_to_fifo)
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_m_r_channel.v
// Version : v1.0
// Description: master read channel: Issue read commands based on the cmd
// ram entries.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_7_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_m_r_channel #
(
parameter C_M_AXI_THREAD_ID_WIDTH = 1,
parameter C_M_AXI_ARUSER_WIDTH = 8,
parameter C_ZERO_INVALID = 1,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_ATG_BASIC_AXI4 = 1,
parameter C_ATG_AXI4LITE = 0
) (
// system
input Clk ,
input rst_l ,
//ar
output [C_M_AXI_THREAD_ID_WIDTH-1:0] arid_m ,
output [C_M_AXI_ADDR_WIDTH-1:0] araddr_m ,
output [7:0] arlen_m ,
output [2:0] arsize_m ,
output [1:0] arburst_m ,
output [0:0] arlock_m ,
output [3:0] arcache_m ,
output [2:0] arprot_m ,
output [3:0] arqos_m ,
output [C_M_AXI_ARUSER_WIDTH-1:0] aruser_m ,
output arvalid_m ,
input arready_m ,
//r
input [C_M_AXI_THREAD_ID_WIDTH-1:0] rid_m ,
input rlast_m ,
input [C_M_AXI_DATA_WIDTH-1:0] rdata_m ,
input [1:0] rresp_m ,
input rvalid_m ,
output rready_m ,
//cmd ram
input [127:0] cmd_out_mr , //from paramwrap logic
input [31:0] cmd_out_mr_ext , //from addrram logic
input cmdram_mr_regslice_id_stable ,
//paramram
input param_cmdr_delayop_valid ,
input [23:0] param_cmdr_count ,
input param_cmdr_repeatfixedop_valid,
input param_cmdr_disable_submitincr ,
//masterram
output [10:0] mram_waddr_ff ,
output [C_M_AXI_DATA_WIDTH/8-1:0] mram_we_ff ,
output [C_M_AXI_DATA_WIDTH-1:0] mram_write_data_ff ,
//register block
input reg0_m_enable_ff ,
input [9:0] reg0_mr_ptr_ff ,
input reg0_m_enable_cmdram_mrw_ff ,
input reg0_m_enable_cmdram_mrw ,
input reg0_m_enable_3ff ,
input reg0_loop_en_ff ,
input mwr_done ,
output reg mr_done_ff ,
output mr_fifo_out_resp_bad ,
output reg mr_bad_last_ff ,
output mr_unexp ,
output [9:0] reg0_mr_ptr_update ,
//masterwrite
input [8:0] mwr_complete_ptr_ff ,
output reg [8:0] mrd_complete_ptr_ff ,
//to exeterna modules
output reg [9:0] mar_ptr_new_ff ,
output reg [9:0] mar_ptr_new_2ff ,
output reg mar_fifo_push_ff ,
//debug-capture
output mar_complete_doinc ,
output mar_done ,
output mr_done ,
output reg mar_param_disableincr_ff ,
output mar_fifo_push
);
reg [23:0] mar_cnt_ff;
reg mar_done_ff, mar_block_push_ff;
wire mar_fifo_notfull;
wire mar_fifo0_notfull, mar_fifo1_notfull, mar_fifo2_notfull,
mar_fifo3_notfull;
wire [3:0] martrk_free;
// CR#768069: when the loop is enabled, issue & complete pointers
// cannot be directly compared as the issue pointer roll backs to start
// value after the last command is issued.
// So inc/dec_ptr pulses are used to calculate the complete depth.
reg [8:0] mar_complete_depth;
wire inc_ptr,dec_ptr;
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
mar_complete_depth <= 9'h0;
end else if(inc_ptr & dec_ptr) begin
mar_complete_depth <= mar_complete_depth;
end else if(inc_ptr) begin
mar_complete_depth <= mar_complete_depth+1'b1;
end else if(dec_ptr) begin
mar_complete_depth <= mar_complete_depth-1'b1;
end
end
//wire [8:0] mar_complete_depth = (reg0_mr_ptr_ff[8:0]-mrd_complete_ptr_ff[8:0]);
wire mar_block_push = (mar_complete_depth[8:0] >= 9'h0d);
/////////////////////////////
wire dis_latch;
reg dis_reg;
reg mar_valid_d1;
wire cur_itrn_dis_rcvd; //current iteration disable received
reg cur_itrn_dis_rcvd_d1; //current iteration disable received 1clk delayed
// Push cmd_out_mr into mar_fifo, if rd_depend and wr_depend are met
wire mar_fifo_push_xff;
wire mar_cnt_reload = ~reg0_m_enable_cmdram_mrw_ff || mar_fifo_push_xff || (dis_reg && ~dis_latch);
wire [7:0] mar_cnt_expand = 8'h00;
// ((cmd_out_mr[59:56] == 4'h0) ? 8'h00 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'h1) ? 8'h00 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'h2) ? 8'h01 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'h3) ? 8'h02 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'h4) ? 8'h06 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'h5) ? 8'h09 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'h6) ? 8'h0c : 8'h00) |
// ((cmd_out_mr[59:56] == 4'h7) ? 8'h11 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'h8) ? 8'h18 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'h9) ? 8'h21 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'ha) ? 8'h32 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'hb) ? 8'h45 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'hc) ? 8'h68 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'hd) ? 8'h81 : 8'h00) |
// ((cmd_out_mr[59:56] == 4'he) ? 8'hbe : 8'h00) |
// ((cmd_out_mr[59:56] == 4'hf) ? 8'hff : 8'h00);
wire mar_cnt_is_not0 = (mar_cnt_ff[23:0] != 24'h0);
wire mar_cnt_ok = ~mar_cnt_reload && ~mar_cnt_is_not0;
wire [8:0] mar_wr_depend = cmd_out_mr[85:77];
wire [8:0] mar_rd_depend = cmd_out_mr[94:86];
wire mar_depend_ok = (reg0_loop_en_ff | mwr_done)? 1'b1 :
((mar_rd_depend[8:0] <= mrd_complete_ptr_ff[8:0]) &&
(mar_wr_depend[8:0] <= mwr_complete_ptr_ff[8:0]));
//wire mar_valid = cmd_out_mr[63] && reg0_m_enable_3ff;
// wire mar_valid = (cmd_out_mr[63] && cmdram_mr_regslice_data_stable) && reg0_m_enable_cmdram_mr;
wire mar_valid_i = (cmd_out_mr[63] && cmdram_mr_regslice_id_stable) && reg0_m_enable_cmdram_mrw && reg0_m_enable_3ff;
// reg mar_valid_ff;
// always @(posedge Clk) begin
// mar_valid_ff <= (rst_l) ? mar_valid : 0;
// end
assign dis_latch = (cur_itrn_dis_rcvd == 1'b1) ? 1'b1 : ((mar_valid_i == 1'b1) ? 1'b0 : dis_reg);
always @(posedge Clk) begin
dis_reg <= (rst_l) ? dis_latch : 1'b0;
mar_valid_d1 <= (rst_l) ? mar_valid_i : 1'b0;
end
assign mar_valid = (dis_reg == 1'b1) ? mar_valid_d1 : mar_valid_i;
////////////////////////////
//wire mar_delay_ok = (cmd_out_mr[59:56] == 4'h0) || mar_cnt_ok;
wire mar_delay_ok = (cmd_out_mr[59:56] == 4'h0 &&
~( param_cmdr_delayop_valid || param_cmdr_repeatfixedop_valid)) || mar_cnt_ok;
//flop delay_ok for timing improvement
reg mar_delay_ok_ff;
always @(posedge Clk) begin
mar_delay_ok_ff <= (rst_l) ? mar_delay_ok : 1'b0;
end
wire mar_cnt_do_dec = mar_fifo_notfull && mar_depend_ok &&
mar_fifo0_notfull && mar_fifo1_notfull &&
mar_fifo2_notfull && mar_fifo3_notfull &&
~mar_block_push_ff && (martrk_free[3:0] != 4'h0);
assign mar_fifo_push = mar_valid && mar_cnt_do_dec && mar_delay_ok_ff && ~mar_fifo_push_ff;
axi_traffic_gen_v2_0_7_regslice
#(
.DWIDTH (1 ),
.IDWIDTH (1 ),
.DATADEPTH(`REGSLICE_FIFOPUSH_DATA)
)
marfifopush_regslice
(
.din (mar_fifo_push ),
.dout (mar_fifo_push_xff),
.dout_early ( ),
.idin (1'b0 ),
.idout ( ),
.id_stable ( ),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
// using delayed fifopush, since next cmd takes some cycles before showing up here
wire param_mar_cnt_reload_delayop = param_cmdr_delayop_valid && (~reg0_m_enable_cmdram_mrw_ff || mar_fifo_push_xff);
wire param_mar_cnt_reload_repeatfixedop = param_cmdr_repeatfixedop_valid && (~reg0_m_enable_cmdram_mrw_ff || mar_fifo_push_xff || (dis_reg && ~dis_latch));
/*
wire [23:0] mar_cnt = (param_mar_cnt_reload_delayop) ? param_cmdr_count_ff[23:0] :
(param_mar_cnt_reload_repeatfixedop) ? {12'h0,param_cmdr_count_ff[19:8]} :
(mar_cnt_reload) ? {16'h0,mar_cnt_expand[7:0]} :
(mar_cnt_do_dec) ? mar_cnt_minus1_ff :
mar_cnt_ff[23:0];
*/
reg [23:0] mar_cnt_minus1_ff ;
wire [23:0] mar_cnt_minus1 = mar_cnt_ff[23:0] - { 22'h0, mar_cnt_is_not0 };
wire [23:0] mar_cnt = (param_mar_cnt_reload_delayop) ? param_cmdr_count[23:0] :
(param_mar_cnt_reload_repeatfixedop) ? {12'h0,param_cmdr_count[19:8]} :
//(mar_cnt_reload) ? {16'h0,mar_cnt_expand[7:0]} :
(mar_cnt_do_dec) ? mar_cnt_minus1 :
mar_cnt_ff[23:0];
//CR#768069:
// a.Get the last disable command index.
// b.Generate a pulse to re-start pointers
// commands issued pointers : reg0_mw_ptr_ff
// commandes completed pointers: mwr_complete_ptr_ff
// Latch reg0_mw_ptr_ff when last command received and use that to
// clear mwr_complete_ptr_ff when it reached reg0_mw_ptr_ff latched value.
// c.Validate all these signals when loop is enabled.
// d.Hold generating the complete signal(maw_done) when loop is enabled.
// e.mask dependency when loop is enabled.
assign cur_itrn_dis_rcvd = reg0_m_enable_ff && reg0_m_enable_3ff && reg0_loop_en_ff && (~dis_reg) &&
((~cmd_out_mr[63] && cmdram_mr_regslice_id_stable)|| mar_done_ff);
wire cur_itrn_done;
always @(posedge Clk) begin
cur_itrn_dis_rcvd_d1 <= (rst_l) ? cur_itrn_dis_rcvd : 1'b0;
end
assign cur_itrn_done = cur_itrn_dis_rcvd & ~cur_itrn_dis_rcvd_d1;
assign mar_done = reg0_m_enable_ff && reg0_m_enable_3ff && ~reg0_loop_en_ff &&
((~cmd_out_mr[63] && cmdram_mr_regslice_id_stable) || mar_done_ff);
// increment unless param'd disable incr is set
wire [9:0] mar_ptr_new = (cur_itrn_done)?10'h0:
((mar_fifo_push_ff && ~param_cmdr_disable_submitincr) ? reg0_mr_ptr_ff[9:0] + 10'h1 :
reg0_mr_ptr_ff[9:0]);
//CR#768069:Hold the index where the invalid command received in cmdram set.
reg [9:0] last_cmd_index;
always @(posedge Clk) begin
if(rst_l == 1'b0) begin
last_cmd_index <= 10'h3FF;
end else if(cur_itrn_done) begin
last_cmd_index <= reg0_mr_ptr_ff;
end else begin
last_cmd_index <= last_cmd_index;
end
end
//inc_ptr: pulse when command issued pointer is incremented.
assign inc_ptr = mar_fifo_push_ff && ~param_cmdr_disable_submitincr;
assign reg0_mr_ptr_update[9:0] = mar_ptr_new[9:0];
always @(posedge Clk) begin
mar_done_ff <= (rst_l) ? mar_done : 1'b0;
mar_fifo_push_ff <= (rst_l) ? mar_fifo_push : 1'b0;
mar_block_push_ff <= (rst_l) ? mar_block_push : 1'b0;
mar_cnt_ff[23:0] <= (rst_l) ? mar_cnt[23:0] : 20'h0;
mar_cnt_minus1_ff[23:0] <= (rst_l) ? mar_cnt_minus1[23:0] : 20'h0;
mar_ptr_new_ff <= (rst_l) ? mar_ptr_new : 8'h0;
mar_ptr_new_2ff <= (rst_l) ? mar_ptr_new_ff : 8'h0;
end
//flop mar_fifo_push for timing improvement
reg mar_fifo_push_1ff ;
reg [92:0] cmd_out_mr_1ff ;
reg [48:0] cmd_out_mr_opt_1ff ;
always @(posedge Clk) begin
mar_fifo_push_1ff <= mar_fifo_push;
end
generate if(C_ATG_BASIC_AXI4 == 0) begin : AXI4_AR_BASIC1_YES
always @(posedge Clk) begin
cmd_out_mr_1ff <= { cmd_out_mr[115:100], cmd_out_mr[76:0] };
end
end
endgenerate
// Command Forma:Field: bits: Actual bit location in 128 bit data.
// address 32 31 0
// len 8 39 32
// lock 1 40 40
// reserved 1 41 41
// burst 2 43 42
// size 3 46 44
// id 6 52 47
// prot 3 55 53
// reserved 4 59 56
// last addr 3 62 60
// valid cmd 1 63 63
// mstram index 13 76 64
// other depend 9 85 77
// my depend 9 94 86
// reserved 1 95 95
// expected resp 3 98 96
// reserved 1 99 99
// cache 4 103 100
// user 8 111 104
// qos 4 115 112
// reserved 12 127 116
generate if(C_ATG_BASIC_AXI4 == 1) begin : AXI4_AR_BASIC1_NO
always @(posedge Clk) begin
cmd_out_mr_opt_1ff <= {
cmd_out_mr[52:47], //id
cmd_out_mr[46:44], //size
cmd_out_mr[39:32], //len
cmd_out_mr[31: 0] }; //address
end
end
endgenerate
wire [92:0] mar_fifo_out;
wire [31:0] mar_fifo_out_ext;
wire mar_fifo_valid, mar_fifo_pop;
generate if(C_ATG_BASIC_AXI4 == 0) begin : AXI4_AR_BASIC2_NO
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (93 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.ZERO_INVALID(C_ZERO_INVALID),
.FULL_LEVEL (6 )
) Mar_fifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (cmd_out_mr_1ff ),
.in_push (mar_fifo_push_1ff ),
.in_pop (mar_fifo_pop ),
.out_data (mar_fifo_out[92:0]),
.is_full ( ),
.is_notfull (mar_fifo_notfull ),
.is_empty ( ),
.out_valid (mar_fifo_valid ),
.ex_fifo_dbgout ( )
);
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : AXI4_AR_BASIC2_YES
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (49 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.ZERO_INVALID(C_ZERO_INVALID),
.FULL_LEVEL (6 )
) Mar_fifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (cmd_out_mr_opt_1ff),
.in_push (mar_fifo_push_1ff ),
.in_pop (mar_fifo_pop ),
.out_data (mar_fifo_out[48:0]),
.is_full ( ),
.is_notfull (mar_fifo_notfull ),
.is_empty ( ),
.out_valid (mar_fifo_valid ),
.ex_fifo_dbgout ( )
);
end
endgenerate
generate if(C_M_AXI_ADDR_WIDTH > 32) begin : AXI4_AR_EXT_ADDR
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (32 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.ZERO_INVALID(C_ZERO_INVALID),
.FULL_LEVEL (6 )
) Mar_fifo_ext (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (cmd_out_mr_ext ),
.in_push (mar_fifo_push_1ff ),
.in_pop (mar_fifo_pop ),
.out_data (mar_fifo_out_ext ),
.is_full ( ),
.is_notfull ( ),
.is_empty ( ),
.out_valid ( ),
.ex_fifo_dbgout ( )
);
end
endgenerate
assign mar_fifo_pop = arvalid_m && arready_m;
//Tie to default values to reduce resources.
//generate if(C_ATG_BASIC_AXI4 == 0 && C_M_AXI_ADDR_WIDTH == 32) begin : BASIC_NO_DEFAULT_ADDR
//assign araddr_m[C_M_AXI_ADDR_WIDTH-1:0] = mar_fifo_out[31:0];
//end
//endgenerate
//
//generate if(C_ATG_BASIC_AXI4 == 0 && C_M_AXI_ADDR_WIDTH > 32) begin : BASIC_NO_EXTENDED_ADDR
//assign araddr_m[C_M_AXI_ADDR_WIDTH-1:0] = {mar_fifo_out_ext[C_M_AXI_ADDR_WIDTH-33:0],mar_fifo_out[31:0]};
//end
//endgenerate
//generate if(C_ATG_BASIC_AXI4 == 1 && C_M_AXI_ADDR_WIDTH == 32) begin : BASIC_YES_DEFAULT_ADDR
//assign araddr_m[C_M_AXI_ADDR_WIDTH-1:0] = mar_fifo_out[31:0];
//end
//endgenerate
//
//generate if(C_ATG_BASIC_AXI4 == 1 && C_M_AXI_ADDR_WIDTH > 32) begin : BASIC_YES_EXTENDED_ADDR
//assign araddr_m[C_M_AXI_ADDR_WIDTH-1:0] = {mar_fifo_out_ext[C_M_AXI_ADDR_WIDTH-33:0],mar_fifo_out[31:0]};
//end
//endgenerate
generate if(C_M_AXI_ADDR_WIDTH == 32) begin : AR_DEFAULT_ADDR
assign araddr_m[C_M_AXI_ADDR_WIDTH-1:0] = mar_fifo_out[31:0];
end
endgenerate
generate if(C_M_AXI_ADDR_WIDTH > 32) begin : AR_EXTENDED_ADDR
assign araddr_m[C_M_AXI_ADDR_WIDTH-1:0] = {mar_fifo_out_ext[C_M_AXI_ADDR_WIDTH-33:0],mar_fifo_out[31:0]};
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0) begin : AXI4_AR_BASIC_NO
assign arid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] = mar_fifo_out[52:47];
assign arlen_m[7:0] = mar_fifo_out[39:32];
assign arvalid_m = mar_fifo_valid;
assign arsize_m[2:0] = mar_fifo_out[46:44];
assign arlock_m[0:0] = mar_fifo_out[40:40]; //arlock made 1-bit signal
assign arburst_m[1:0] = mar_fifo_out[43:42];
assign arprot_m[2:0] = mar_fifo_out[55:53];
assign arcache_m[3:0] = mar_fifo_out[80:77];
assign aruser_m[C_M_AXI_ARUSER_WIDTH-1:0] = mar_fifo_out[88:81];
assign arqos_m[3:0] = mar_fifo_out[92:89];
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : AXI4_AR_BASIC_YES
assign arid_m[C_M_AXI_THREAD_ID_WIDTH-1:0] = mar_fifo_out[48:43];
assign arsize_m[2:0] = mar_fifo_out[42:40];
assign arlen_m[7:0] = mar_fifo_out[39:32];
assign arvalid_m = mar_fifo_valid;
assign arlock_m[0:0] = 1'b0;
assign arburst_m[1:0] = 2'h1;
assign arprot_m[2:0] = 3'b000;
assign arcache_m[3:0] = 4'b0011;
assign aruser_m[C_M_AXI_ARUSER_WIDTH-1:0] = {C_M_AXI_ARUSER_WIDTH{1'b0}};
assign arqos_m[3:0] = 4'h0;
end
endgenerate
// grahams : add param tracking through the system
wire [88:0] mar_fifo0_out, mar_fifo1_out, mar_fifo2_out, mar_fifo3_out;
wire [0:0] mar_agen0_user,mar_agen1_user,mar_agen2_user,mar_agen3_user;
wire mar_fifo0_valid, mar_fifo0_pop;
wire mar_fifo1_valid, mar_fifo1_pop;
wire mar_fifo2_valid, mar_fifo2_pop;
wire mar_fifo3_valid, mar_fifo3_pop;
wire mar_agen0_valid, mar_agen1_valid, mar_agen2_valid, mar_agen3_valid;
reg mar_fifo0_valid_ff;
reg mar_fifo1_valid_ff;
reg mar_fifo2_valid_ff;
reg mar_fifo3_valid_ff;
always @(posedge Clk) begin
mar_fifo0_valid_ff <= (rst_l) ? mar_fifo0_valid : 1'b0;
mar_fifo1_valid_ff <= (rst_l) ? mar_fifo1_valid : 1'b0;
mar_fifo2_valid_ff <= (rst_l) ? mar_fifo2_valid : 1'b0;
mar_fifo3_valid_ff <= (rst_l) ? mar_fifo3_valid : 1'b0;
end
wire [3:0] martrk_clear_pos = { ~mar_agen3_valid && ~mar_fifo3_valid_ff,
~mar_agen2_valid && ~mar_fifo2_valid_ff,
~mar_agen1_valid && ~mar_fifo1_valid_ff,
~mar_agen0_valid && ~mar_fifo0_valid_ff };
wire [3:0] martrk_fifo_num, martrk_mr_hit;
wire [C_M_AXI_DATA_WIDTH+C_M_AXI_THREAD_ID_WIDTH +3-1:0] mr_fifo_out;
wire [C_M_AXI_THREAD_ID_WIDTH-1:0] martrk_in_push_id = cmd_out_mr[52:47];
wire [C_M_AXI_THREAD_ID_WIDTH-1:0] martrk_in_search_id =
mr_fifo_out[C_M_AXI_DATA_WIDTH+C_M_AXI_THREAD_ID_WIDTH +3-1:C_M_AXI_DATA_WIDTH+3];
//flop mar_fifo_push for timing improvement
// search should not be flopped, as search_id and search_hit occurs in 1 clock
// cycle.Delaying search, causes to hit a wrong search ID.
reg [C_M_AXI_THREAD_ID_WIDTH-1:0] martrk_in_push_id_1ff;
reg [C_M_AXI_THREAD_ID_WIDTH-1:0] martrk_in_search_id_1ff;
always @(posedge Clk) begin
martrk_in_push_id_1ff <= martrk_in_push_id ;
martrk_in_search_id_1ff <= martrk_in_search_id;
end
wire dis_dis_out_of_order;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_M_R_OOO_YES
assign dis_dis_out_of_order = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_M_R_OOO_NO
assign dis_dis_out_of_order = 1'b1;
end
endgenerate
axi_traffic_gen_v2_0_7_id_track #(
.ID_WIDTH(C_M_AXI_THREAD_ID_WIDTH)
) Mar_track (
.Clk (Clk ),
.rst_l (rst_l ),
.in_push_id (martrk_in_push_id_1ff[C_M_AXI_THREAD_ID_WIDTH-1:0] ),
.in_push (mar_fifo_push_1ff ),
.in_search_id (martrk_in_search_id[C_M_AXI_THREAD_ID_WIDTH-1:0] ),
.in_clear_pos (martrk_clear_pos[3:0] ),
.in_only_entry0(dis_dis_out_of_order ),
.out_push_pos (martrk_fifo_num[3:0] ),
.out_search_hit(martrk_mr_hit[3:0] ),
.out_free (martrk_free[3:0] )
);
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (89),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Mar_fifo0 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data ({param_cmdr_disable_submitincr,
reg0_mr_ptr_ff[7:0],
cmd_out_mr[98:96],
cmd_out_mr[76:0] } ),
.in_push (martrk_fifo_num[0] ),
.in_pop (mar_fifo0_pop ),
.out_data (mar_fifo0_out[88:0] ),
.is_full ( ),
.is_notfull (mar_fifo0_notfull ),
.is_empty ( ),
.out_valid (mar_fifo0_valid ),
.ex_fifo_dbgout ( )
);
wire [15:0] mar_agen0_addr, mar_agen0_id;
wire [C_M_AXI_DATA_WIDTH/8-1:0] mar_agen0_be;
wire [7:0] mar_agen0_tag;
wire mar_agen0_done, mar_agen0_pop;
wire mr_fifo_valid;
//
//add flopping state for timing improvement
//
reg [88:0] mar_fifo0_out_ff;
reg mar_fifo0_pop_ff;
always @(posedge Clk) begin
mar_fifo0_out_ff <= mar_fifo0_out;
mar_fifo0_pop_ff <= mar_fifo0_pop;
end
axi_traffic_gen_v2_0_7_addrgen #(
.USE_ADDR_OFFSET (1) ,
.C_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Mar_agen0 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({ mar_fifo0_out[79:64] } ),
.in_addr_offset({1'b0,mar_fifo0_out[7:0]} ),
.in_id ({ mar_fifo0_out[87:80], 2'b00, mar_fifo0_out[52:47]}),
.in_len (mar_fifo0_out[39:32] ),
.in_size (mar_fifo0_out[46:44] ),
.in_lastaddr ({3'b000,mar_fifo0_out[62:60] } ),
.in_burst (mar_fifo0_out[43:42] ),
.in_push (mar_fifo0_pop ),
.in_pop (mar_agen0_pop ),
.in_user (mar_fifo0_out[88] ),
.out_user (mar_agen0_user[0] ),
.out_addr (mar_agen0_addr[15:0] ),
.out_id (mar_agen0_id[15:0] ),
.out_be (mar_agen0_be[C_M_AXI_DATA_WIDTH/8-1:0] ),
.out_done (mar_agen0_done ),
.out_valid (mar_agen0_valid )
);
reg mar_fifo1_pop_ff;
reg mar_fifo2_pop_ff;
reg mar_fifo3_pop_ff;
wire [15:0] mar_agen1_addr, mar_agen1_id;
wire [15:0] mar_agen2_addr, mar_agen2_id;
wire [15:0] mar_agen3_addr, mar_agen3_id;
wire mar_agen1_done, mar_agen1_pop;
wire mar_agen2_done, mar_agen2_pop;
wire mar_agen3_done, mar_agen3_pop;
wire [C_M_AXI_DATA_WIDTH/8-1:0] mar_agen1_be;
wire [C_M_AXI_DATA_WIDTH/8-1:0] mar_agen2_be;
wire [C_M_AXI_DATA_WIDTH/8-1:0] mar_agen3_be;
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_M_R_OOO_F_NO
assign mar_fifo1_notfull = 1;
assign mar_fifo1_valid = 0;
assign mar_agen1_done = 0;
assign mar_agen1_valid = 0;
assign mar_fifo2_notfull = 1;
assign mar_fifo2_valid = 0;
assign mar_agen2_done = 0;
assign mar_agen2_valid = 0;
assign mar_fifo3_notfull = 1;
assign mar_fifo3_valid = 0;
assign mar_agen3_done = 0;
assign mar_agen3_valid = 0;
always @(posedge Clk) begin
mar_fifo1_pop_ff <= 1'b0;
mar_fifo2_pop_ff <= 1'b0;
mar_fifo3_pop_ff <= 1'b0;
end
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_M_R_OOO_F_YES
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (89),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Mar_fifo1 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data ({param_cmdr_disable_submitincr,
reg0_mr_ptr_ff[7:0],
cmd_out_mr[98:96],
cmd_out_mr[76:0] } ),
.in_push (martrk_fifo_num[1] ),
.in_pop (mar_fifo1_pop ),
.out_data (mar_fifo1_out[88:0] ),
.is_full ( ),
.is_notfull (mar_fifo1_notfull ),
.is_empty ( ),
.out_valid (mar_fifo1_valid ),
.ex_fifo_dbgout ( )
);
//
//add flopping state for timing improvement
//
reg [88:0] mar_fifo1_out_ff;
always @(posedge Clk) begin
mar_fifo1_out_ff <= mar_fifo1_out;
mar_fifo1_pop_ff <= mar_fifo1_pop;
end
axi_traffic_gen_v2_0_7_addrgen #(
.USE_ADDR_OFFSET (1) ,
.C_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Mar_agen1 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({ mar_fifo1_out[79:64] } ),
.in_addr_offset({1'b0,mar_fifo1_out[7:0]} ),
.in_id ({ mar_fifo1_out[87:80], 2'b00, mar_fifo1_out[52:47]} ),
.in_len (mar_fifo1_out[39:32] ),
.in_size (mar_fifo1_out[46:44] ),
.in_lastaddr ({3'b000,mar_fifo1_out[62:60] } ),
.in_burst (mar_fifo1_out[43:42] ),
.in_push (mar_fifo1_pop ),
.in_pop (mar_agen1_pop ),
.in_user (mar_fifo1_out[88] ),
.out_user (mar_agen1_user[0] ),
.out_addr (mar_agen1_addr[15:0] ),
.out_id (mar_agen1_id[15:0] ),
.out_be (mar_agen1_be[C_M_AXI_DATA_WIDTH/8-1:0] ),
.out_done (mar_agen1_done ),
.out_valid (mar_agen1_valid )
);
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (89),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Mar_fifo2 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data ({param_cmdr_disable_submitincr,
reg0_mr_ptr_ff[7:0],
cmd_out_mr[98:96],
cmd_out_mr[76:0] } ),
.in_push (martrk_fifo_num[2] ),
.in_pop (mar_fifo2_pop ),
.out_data (mar_fifo2_out[88:0] ),
.is_full ( ),
.is_notfull (mar_fifo2_notfull ),
.is_empty ( ),
.out_valid (mar_fifo2_valid ),
.ex_fifo_dbgout ( )
);
//
//add flopping state for timing improvement
//
reg [88:0] mar_fifo2_out_ff;
always @(posedge Clk) begin
mar_fifo2_out_ff <= mar_fifo2_out;
mar_fifo2_pop_ff <= mar_fifo2_pop;
end
axi_traffic_gen_v2_0_7_addrgen #(
.USE_ADDR_OFFSET (1) ,
.C_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Mar_agen2 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({ mar_fifo2_out[79:64] } ),
.in_addr_offset({1'b0,mar_fifo2_out[7:0]} ),
.in_id ({ mar_fifo2_out[87:80], 2'b00, mar_fifo2_out[52:47]} ),
.in_len (mar_fifo2_out[39:32] ),
.in_size (mar_fifo2_out[46:44] ),
.in_lastaddr ({3'b000,mar_fifo2_out[62:60] } ),
.in_burst (mar_fifo2_out[43:42] ),
.in_push (mar_fifo2_pop ),
.in_pop (mar_agen2_pop ),
.in_user (mar_fifo2_out[88] ),
.out_user (mar_agen2_user[0] ),
.out_addr (mar_agen2_addr[15:0] ),
.out_id (mar_agen2_id[15:0] ),
.out_be (mar_agen2_be[C_M_AXI_DATA_WIDTH/8-1:0] ),
.out_done (mar_agen2_done ),
.out_valid (mar_agen2_valid )
);
axi_traffic_gen_v2_0_7_ex_fifo #(
.WIDTH (89),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Mar_fifo3 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data ({param_cmdr_disable_submitincr,
reg0_mr_ptr_ff[7:0],
cmd_out_mr[98:96],
cmd_out_mr[76:0] } ),
.in_push (martrk_fifo_num[3] ),
.in_pop (mar_fifo3_pop ),
.out_data (mar_fifo3_out[88:0] ),
.is_full ( ),
.is_notfull (mar_fifo3_notfull ),
.is_empty ( ),
.out_valid (mar_fifo3_valid ),
.ex_fifo_dbgout ( )
);
//
//add flopping state for timing improvement
//
reg [88:0] mar_fifo3_out_ff;
always @(posedge Clk) begin
mar_fifo3_out_ff <= mar_fifo3_out;
mar_fifo3_pop_ff <= mar_fifo3_pop;
end
axi_traffic_gen_v2_0_7_addrgen #(
.USE_ADDR_OFFSET (1) ,
.C_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.IS_READ (1) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Mar_agen3 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({ mar_fifo3_out[79:64] } ),
.in_addr_offset({1'b0,mar_fifo3_out[7:0]} ),
.in_id ({ mar_fifo3_out[87:80], 2'b00, mar_fifo3_out[52:47]} ),
.in_len (mar_fifo3_out[39:32] ),
.in_size (mar_fifo3_out[46:44] ),
.in_lastaddr ({3'b000,mar_fifo3_out[62:60]} ),
.in_burst (mar_fifo3_out[43:42] ),
.in_push (mar_fifo3_pop ),
.in_pop (mar_agen3_pop ),
.in_user (mar_fifo3_out[88] ),
.out_user (mar_agen3_user[0] ),
.out_addr (mar_agen3_addr[15:0] ),
.out_id (mar_agen3_id[15:0] ),
.out_be (mar_agen3_be[C_M_AXI_DATA_WIDTH/8-1:0] ),
.out_done (mar_agen3_done ),
.out_valid (mar_agen3_valid )
);
end
endgenerate
assign mar_fifo0_pop = (~mar_agen0_valid || (mar_agen0_done && mar_agen0_pop)) && mar_fifo0_valid_ff & ~mar_fifo0_pop_ff;
assign mar_fifo1_pop = (~mar_agen1_valid || (mar_agen1_done && mar_agen1_pop)) && mar_fifo1_valid_ff & ~mar_fifo1_pop_ff;
assign mar_fifo2_pop = (~mar_agen2_valid || (mar_agen2_done && mar_agen2_pop)) && mar_fifo2_valid_ff & ~mar_fifo2_pop_ff;
assign mar_fifo3_pop = (~mar_agen3_valid || (mar_agen3_done && mar_agen3_pop)) && mar_fifo3_valid_ff & ~mar_fifo3_pop_ff;
assign mar_agen0_pop = mr_fifo_valid && mar_agen0_valid && martrk_mr_hit[0];
assign mar_agen1_pop = mr_fifo_valid && mar_agen1_valid && martrk_mr_hit[1];
assign mar_agen2_pop = mr_fifo_valid && mar_agen2_valid && martrk_mr_hit[2];
assign mar_agen3_pop = mr_fifo_valid && mar_agen3_valid && martrk_mr_hit[3];
// Receive master data returns
wire mr_fifo_notfull, mr_fifo_pop;
wire [C_M_AXI_THREAD_ID_WIDTH-1:0] mr_id = rid_m[C_M_AXI_THREAD_ID_WIDTH-1:0];
wire [C_M_AXI_DATA_WIDTH+ C_M_AXI_THREAD_ID_WIDTH +3 -1:0] mr_in_data = {
mr_id[C_M_AXI_THREAD_ID_WIDTH-1:0], rlast_m, rresp_m[1:0],rdata_m[C_M_AXI_DATA_WIDTH-1:0] };
axi_traffic_gen_v2_0_7_ex_fifo #(
//.WIDTH (C_M_AXI_DATA_WIDTH+10),
.WIDTH (C_M_AXI_THREAD_ID_WIDTH+C_M_AXI_DATA_WIDTH+3),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Mr_fifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (mr_in_data[C_M_AXI_DATA_WIDTH+C_M_AXI_THREAD_ID_WIDTH+3-1:0] ),
.in_push (rvalid_m && rready_m ),
.in_pop (mr_fifo_pop ),
.out_data (mr_fifo_out[C_M_AXI_DATA_WIDTH+C_M_AXI_THREAD_ID_WIDTH+3-1:0]),
.is_full ( ),
.is_notfull (mr_fifo_notfull ),
.is_empty ( ),
.out_valid (mr_fifo_valid ),
.ex_fifo_dbgout ( )
);
assign mr_fifo_pop = mar_agen0_pop || mar_agen1_pop || mar_agen2_pop ||
mar_agen3_pop;
assign rready_m = mr_fifo_notfull;
wire [15:0] mram_waddr = ((mar_agen0_pop) ? mar_agen0_addr[15:0] : 16'h0) |
((mar_agen1_pop) ? mar_agen1_addr[15:0] : 16'h0) |
((mar_agen2_pop) ? mar_agen2_addr[15:0] : 16'h0) |
((mar_agen3_pop) ? mar_agen3_addr[15:0] : 16'h0);
wire mar_param_disableincr = ((mar_agen0_pop) ? mar_agen0_user[0] : 1'h0) |
((mar_agen1_pop) ? mar_agen1_user[0] : 1'h0) |
((mar_agen2_pop) ? mar_agen2_user[0] : 1'h0) |
((mar_agen3_pop) ? mar_agen3_user[0] : 1'h0);
wire mar_param_disableincr_nxt = ((mar_agen0_pop) ? mar_agen0_user[0] : 1'h0) |
((mar_agen1_pop) ? mar_agen1_user[0] : 1'h0) |
((mar_agen2_pop) ? mar_agen2_user[0] : 1'h0) |
((mar_agen3_pop) ? mar_agen3_user[0] : 1'h0) |
((~mar_agen0_pop && ~mar_agen1_pop && ~mar_agen2_pop && ~mar_agen3_pop) ? mar_param_disableincr_ff : 1'h0);
//reg mar_param_disableincr_2ff;
always @(posedge Clk) begin
mar_param_disableincr_ff <= (rst_l) ? mar_param_disableincr_nxt : 1'b0;
//mar_param_disableincr_2ff <= (rst_l) ? mar_param_disableincr_ff : 1'b0;
end
wire [C_M_AXI_DATA_WIDTH-1:0] mram_dummy_out;
wire [15:0] maw_agen_addr;
wire [C_M_AXI_DATA_WIDTH/8-1:0] mram_we =
((mar_agen0_pop) ? mar_agen0_be[C_M_AXI_DATA_WIDTH/8-1:0] : 'h0) |
((mar_agen1_pop) ? mar_agen1_be[C_M_AXI_DATA_WIDTH/8-1:0] : 'h0) |
((mar_agen2_pop) ? mar_agen2_be[C_M_AXI_DATA_WIDTH/8-1:0] : 'h0) |
((mar_agen3_pop) ? mar_agen3_be[C_M_AXI_DATA_WIDTH/8-1:0] : 'h0);
wire [1:0] mr_fifo_out_resp =
mr_fifo_out[C_M_AXI_DATA_WIDTH+2-1:C_M_AXI_DATA_WIDTH];
wire [2:0] mr_fifo_out_resp_mask =
((mr_fifo_out_resp[1:0] == 2'b00) ? 3'b001 : 3'b000) |
((mr_fifo_out_resp[1:0] == 2'b01) ? 3'b010 : 3'b000) |
((mr_fifo_out_resp[1] == 1'b1) ? 3'b100 : 3'b000);
wire [2:0] mr_fifo_out_resp_allowed = (mram_waddr[15:13] == 3'b000) ? 3'b001 :
mram_waddr[15:13];
wire mr_fifo_out_resp_ok =
((mr_fifo_out_resp_allowed[2:0] & mr_fifo_out_resp_mask[2:0]) !=
3'b000);
assign mr_fifo_out_resp_bad = mr_fifo_pop && ~mr_fifo_out_resp_ok;
wire [C_M_AXI_DATA_WIDTH-1:0] mram_write_data =
mr_fifo_out[C_M_AXI_DATA_WIDTH-1:0];
// adding sram regslice for timing closure
wire [C_M_AXI_DATA_WIDTH*9/8+11-1:0] sram_mramwr_ff;
axi_traffic_gen_v2_0_7_regslice
#(
.DWIDTH (C_M_AXI_DATA_WIDTH*9/8+11),
.IDWIDTH (1 ),
.DATADEPTH(1 )
)
sram_mramwr_regslice
(
.din ({mram_waddr[12:2],mram_we,mram_write_data}),
.dout (sram_mramwr_ff ),
.dout_early ( ),
.idin (1'b0 ),
.idout ( ),
.id_stable ( ),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
assign mram_waddr_ff = sram_mramwr_ff[C_M_AXI_DATA_WIDTH*9/8+11-1:
C_M_AXI_DATA_WIDTH*9/8+1-1];
assign mram_we_ff = sram_mramwr_ff[C_M_AXI_DATA_WIDTH*9/8-1:
C_M_AXI_DATA_WIDTH];
assign mram_write_data_ff = sram_mramwr_ff[C_M_AXI_DATA_WIDTH-1:0];
reg mr_unexp_maybe_ff, mr_unexp_maybe_2ff, mr_unexp_maybe_3ff;
wire mr_exp_last = mr_fifo_out[C_M_AXI_DATA_WIDTH+2];
wire mr_bad_last = (mar_agen0_pop && (mar_agen0_done != mr_exp_last)) ||
(mar_agen1_pop && (mar_agen1_done != mr_exp_last)) ||
(mar_agen2_pop && (mar_agen2_done != mr_exp_last)) ||
(mar_agen3_pop && (mar_agen3_done != mr_exp_last));
wire mr_unexp_maybe = mr_fifo_valid && ~mar_agen0_pop && ~mar_agen1_pop &&
~mar_agen2_pop && ~mar_agen3_pop;
reg rvalid_m_1ff;
reg rvalid_m_2ff;
reg rvalid_m_3ff;
always @(posedge Clk) begin
mr_unexp_maybe_ff <= (rst_l) ? mr_unexp_maybe : 1'b0;
mr_unexp_maybe_2ff <= (rst_l) ? mr_unexp_maybe_ff : 1'b0;
mr_unexp_maybe_3ff <= (rst_l) ? mr_unexp_maybe_2ff : 1'b0;
mr_bad_last_ff <= (rst_l) ? mr_bad_last : 1'b0;
//check for atleast three clock if matching RID comes
rvalid_m_1ff <= (rst_l) ? rvalid_m : 1'b0;
rvalid_m_2ff <= (rst_l) ? rvalid_m_1ff : 1'b0;
rvalid_m_3ff <= (rst_l) ? rvalid_m_2ff : 1'b0;
end
assign mr_unexp = mr_unexp_maybe_ff && mr_unexp_maybe_2ff && mr_unexp_maybe_3ff && rvalid_m_3ff;
//master complete logic
reg [15:0] mar_complete_vec_ff;
wire mar_agen0_complete = mar_agen0_pop && mar_agen0_done;
wire mar_agen1_complete = mar_agen1_pop && mar_agen1_done;
wire mar_agen2_complete = mar_agen2_pop && mar_agen2_done;
wire mar_agen3_complete = mar_agen3_pop && mar_agen3_done;
wire [15:0] mar_agen0_tag_exp = (mar_agen0_complete) ?
(16'h1 << mar_agen0_id[11:8]) : 16'h0;
wire [15:0] mar_agen1_tag_exp = (mar_agen1_complete) ?
(16'h1 << mar_agen1_id[11:8]) : 16'h0;
wire [15:0] mar_agen2_tag_exp = (mar_agen2_complete) ?
(16'h1 << mar_agen2_id[11:8]) : 16'h0;
wire [15:0] mar_agen3_tag_exp = (mar_agen3_complete) ?
(16'h1 << mar_agen3_id[11:8]) : 16'h0;
wire [15:0] mar_complete_next2 = (16'h1 << mrd_complete_ptr_ff[3:0]);
wire [15:0] mar_complete_inc_exp = mar_complete_next2[15:0] &
mar_complete_vec_ff[15:0];
assign mar_complete_doinc = (mar_complete_inc_exp[15:0] != 16'h0);
wire [15:0] mar_complete_vec = //~mar_complete_inc_exp[15:0] &
(mar_agen0_tag_exp[15:0] | mar_agen1_tag_exp[15:0] |
mar_agen2_tag_exp[15:0] | mar_agen3_tag_exp[15:0]); //|
//mar_complete_vec_ff[15:0]);
// using disableincr bit that is tracked for parameterized mode
// CR#768069: Reset complete_ptr when current value equal to latched command
// index.
wire [8:0] mrd_complete_ptr;
wire rst_complete_ptr = (last_cmd_index[8:0] == mrd_complete_ptr_ff ) ;//& reg0_loop_en_ff;
assign mrd_complete_ptr = ((~reg0_m_enable_ff)|(rst_complete_ptr)) ? 9'h0 :
(mar_complete_doinc & ~mar_param_disableincr_ff) ?
mrd_complete_ptr_ff[8:0] + 9'h1 :
mrd_complete_ptr_ff[8:0];
//dec_ptr: pulse when command command pointer is incremented.
assign dec_ptr = mar_complete_doinc & ~mar_param_disableincr_ff;
assign mr_done = (reg0_m_enable_ff && mar_done_ff && (mrd_complete_ptr[8:0] == reg0_mr_ptr_ff[8:0]))?1'b1:
((~reg0_m_enable_ff)?1'b0:mr_done_ff);
always @(posedge Clk) begin
mrd_complete_ptr_ff[8:0] <= (rst_l) ? mrd_complete_ptr[8:0] : 9'h0;
mar_complete_vec_ff[15:0] <= (rst_l) ? mar_complete_vec[15:0] : 16'h0;
mr_done_ff <= (rst_l) ? mr_done : 1'b0;
end
endmodule
|
(** * RecordSub: Subtyping with Records *)
(** In this chapter, we combine two significant extensions of the pure
STLC -- records (from chapter [Records]) and subtyping (from
chapter [Sub]) -- and explore their interactions. Most of the
concepts have already been discussed in those chapters, so the
presentation here is somewhat terse. We just comment where things
are nonstandard. *)
Require Import SfLib.
Require Import Maps.
Require Import MoreStlc.
(* ################################################################# *)
(** * Core Definitions *)
(* ----------------------------------------------------------------- *)
(** *** Syntax *)
Inductive ty : Type :=
(* proper types *)
| TTop : ty
| TBase : id -> ty
| TArrow : ty -> ty -> ty
(* record types *)
| TRNil : ty
| TRCons : id -> ty -> ty -> ty.
Inductive tm : Type :=
(* proper terms *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tproj : tm -> id -> tm
(* record terms *)
| trnil : tm
| trcons : id -> tm -> tm -> tm.
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
(** The syntax of terms and types is a bit too loose, in the sense
that it admits things like a record type whose final "tail" is
[Top] or some arrow type rather than [Nil]. To avoid such cases,
it is useful to assume that all the record types and terms that we
see will obey some simple well-formedness conditions.
[An interesting technical question is whether the basic properties
of the system -- progress and preservation -- remain true if we
drop these conditions. I believe they do, and I would encourage
motivated readers to try to check this by dropping the conditions
from the definitions of typing and subtyping and adjusting the
proofs in the rest of the chapter accordingly. This is not a
trivial exercise (or I'd have done it!), but it should not involve
changing the basic structure of the proofs. If someone does do
it, please let me know. --BCP 5/16.] *)
Inductive record_ty : ty -> Prop :=
| RTnil :
record_ty TRNil
| RTcons : forall i T1 T2,
record_ty (TRCons i T1 T2).
Inductive record_tm : tm -> Prop :=
| rtnil :
record_tm trnil
| rtcons : forall i t1 t2,
record_tm (trcons i t1 t2).
Inductive well_formed_ty : ty -> Prop :=
| wfTTop :
well_formed_ty TTop
| wfTBase : forall i,
well_formed_ty (TBase i)
| wfTArrow : forall T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
well_formed_ty (TArrow T1 T2)
| wfTRNil :
well_formed_ty TRNil
| wfTRCons : forall i T1 T2,
well_formed_ty T1 ->
well_formed_ty T2 ->
record_ty T2 ->
well_formed_ty (TRCons i T1 T2).
Hint Constructors record_ty record_tm well_formed_ty.
(* ----------------------------------------------------------------- *)
(** *** Substitution *)
(** Substitution and reduction are as before. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if beq_id x y then s else t
| tabs y T t1 => tabs y T (if beq_id x y then t1
else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tproj t1 i => tproj (subst x s t1) i
| trnil => trnil
| trcons i t1 tr2 => trcons i (subst x s t1) (subst x s tr2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ----------------------------------------------------------------- *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_rnil : value trnil
| v_rcons : forall i v vr,
value v ->
value vr ->
value (trcons i v vr).
Hint Constructors value.
Fixpoint Tlookup (i:id) (Tr:ty) : option ty :=
match Tr with
| TRCons i' T Tr' =>
if beq_id i i' then Some T else Tlookup i Tr'
| _ => None
end.
Fixpoint tlookup (i:id) (tr:tm) : option tm :=
match tr with
| trcons i' t tr' =>
if beq_id i i' then Some t else tlookup i tr'
| _ => None
end.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
| ST_Proj1 : forall tr tr' i,
tr ==> tr' ->
(tproj tr i) ==> (tproj tr' i)
| ST_ProjRcd : forall tr i vi,
value tr ->
tlookup i tr = Some vi ->
(tproj tr i) ==> vi
| ST_Rcd_Head : forall i t1 t1' tr2,
t1 ==> t1' ->
(trcons i t1 tr2) ==> (trcons i t1' tr2)
| ST_Rcd_Tail : forall i v1 tr2 tr2',
value v1 ->
tr2 ==> tr2' ->
(trcons i v1 tr2) ==> (trcons i v1 tr2')
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
(* ################################################################# *)
(** * Subtyping *)
(** Now we come to the interesting part, where the features we've
added start to interact. We begin by defining the subtyping
relation and developing some of its important technical
properties. *)
(* ================================================================= *)
(** ** Definition *)
(** The definition of subtyping is essentially just what we sketched
in the discussion of record subtyping in chapter [Sub], but we
need to add well-formedness side conditions to some of the rules.
Also, we replace the "n-ary" width, depth, and permutation
subtyping rules by binary rules that deal with just the first
field. *)
Reserved Notation "T '<:' U" (at level 40).
Inductive subtype : ty -> ty -> Prop :=
(* Subtyping between proper types *)
| S_Refl : forall T,
well_formed_ty T ->
T <: T
| S_Trans : forall S U T,
S <: U ->
U <: T ->
S <: T
| S_Top : forall S,
well_formed_ty S ->
S <: TTop
| S_Arrow : forall S1 S2 T1 T2,
T1 <: S1 ->
S2 <: T2 ->
TArrow S1 S2 <: TArrow T1 T2
(* Subtyping between record types *)
| S_RcdWidth : forall i T1 T2,
well_formed_ty (TRCons i T1 T2) ->
TRCons i T1 T2 <: TRNil
| S_RcdDepth : forall i S1 T1 Sr2 Tr2,
S1 <: T1 ->
Sr2 <: Tr2 ->
record_ty Sr2 ->
record_ty Tr2 ->
TRCons i S1 Sr2 <: TRCons i T1 Tr2
| S_RcdPerm : forall i1 i2 T1 T2 Tr3,
well_formed_ty (TRCons i1 T1 (TRCons i2 T2 Tr3)) ->
i1 <> i2 ->
TRCons i1 T1 (TRCons i2 T2 Tr3)
<: TRCons i2 T2 (TRCons i1 T1 Tr3)
where "T '<:' U" := (subtype T U).
Hint Constructors subtype.
(* ================================================================= *)
(** ** Examples *)
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation j := (Id 3).
Notation k := (Id 4).
Notation i := (Id 5).
Notation A := (TBase (Id 6)).
Notation B := (TBase (Id 7)).
Notation C := (TBase (Id 8)).
Definition TRcd_j :=
(TRCons j (TArrow B B) TRNil). (* {j:B->B} *)
Definition TRcd_kj :=
TRCons k (TArrow A A) TRcd_j. (* {k:C->C,j:B->B} *)
Example subtyping_example_0 :
subtype (TArrow C TRcd_kj)
(TArrow C TRNil).
(* C->{k:A->A,j:B->B} <: C->{} *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
unfold TRcd_kj, TRcd_j. apply S_RcdWidth; auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get full
benefit, make sure you also understand how to prove them on
paper! *)
(** **** Exercise: 2 stars *)
Example subtyping_example_1 :
subtype TRcd_kj TRcd_j.
(* {k:A->A,j:B->B} <: {j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_2 :
subtype (TArrow TTop TRcd_kj)
(TArrow (TArrow C C) TRcd_j).
(* Top->{k:A->A,j:B->B} <: (C->C)->{j:B->B} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star *)
Example subtyping_example_3 :
subtype (TArrow TRNil (TRCons j A TRNil))
(TArrow (TRCons k B TRNil) TRNil).
(* {}->{j:A} <: {k:B}->{} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars *)
Example subtyping_example_4 :
subtype (TRCons x A (TRCons y B (TRCons z C TRNil)))
(TRCons z C (TRCons y B (TRCons x A TRNil))).
(* {x:A,y:B,z:C} <: {z:C,y:B,x:A} *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples.
(* ================================================================= *)
(** ** Properties of Subtyping *)
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
(** To get started proving things about subtyping, we need a couple of
technical lemmas that intuitively (1) allow us to extract the
well-formedness assumptions embedded in subtyping derivations
and (2) record the fact that fields of well-formed record types
are themselves well-formed types. *)
Lemma subtype__wf : forall S T,
subtype S T ->
well_formed_ty T /\ well_formed_ty S.
Proof with eauto.
intros S T Hsub.
induction Hsub;
intros; try (destruct IHHsub1; destruct IHHsub2)...
- (* S_RcdPerm *)
split... inversion H. subst. inversion H5... Qed.
Lemma wf_rcd_lookup : forall i T Ti,
well_formed_ty T ->
Tlookup i T = Some Ti ->
well_formed_ty Ti.
Proof with eauto.
intros i T.
induction T; intros; try solve by inversion.
- (* TRCons *)
inversion H. subst. unfold Tlookup in H0.
destruct (beq_id i i0)... inversion H0; subst... Qed.
(* ----------------------------------------------------------------- *)
(** *** Field Lookup *)
(** The record matching lemmas get a little more complicated in the
presence of subtyping, for two reasons. First, record types no
longer necessarily describe the exact structure of the
corresponding terms. And second, reasoning by induction on typing
derivations becomes harder in general, because typing is no longer
syntax directed. *)
Lemma rcd_types_match : forall S T i Ti,
subtype S T ->
Tlookup i T = Some Ti ->
exists Si, Tlookup i S = Some Si /\ subtype Si Ti.
Proof with (eauto using wf_rcd_lookup).
intros S T i Ti Hsub Hget. generalize dependent Ti.
induction Hsub; intros Ti Hget;
try solve by inversion.
- (* S_Refl *)
exists Ti...
- (* S_Trans *)
destruct (IHHsub2 Ti) as [Ui Hui]... destruct Hui.
destruct (IHHsub1 Ui) as [Si Hsi]... destruct Hsi.
exists Si...
- (* S_RcdDepth *)
rename i0 into k.
unfold Tlookup. unfold Tlookup in Hget.
destruct (beq_id i k)...
+ (* i = k -- we're looking up the first field *)
inversion Hget. subst. exists S1...
- (* S_RcdPerm *)
exists Ti. split.
+ (* lookup *)
unfold Tlookup. unfold Tlookup in Hget.
destruct (beq_idP i i1)...
* (* i = i1 -- we're looking up the first field *)
destruct (beq_idP i i2)...
(* i = i2 -- contradictory *)
destruct H0.
subst...
+ (* subtype *)
inversion H. subst. inversion H5. subst... Qed.
(** **** Exercise: 3 stars (rcd_types_match_informal) *)
(** Write a careful informal proof of the [rcd_types_match]
lemma. *)
(* FILL IN HERE *)
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Inversion Lemmas *)
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (TArrow V1 V2) ->
exists U1, exists U2,
(U=(TArrow U1 U2)) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (TArrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Typing *)
Definition context := partial_map ty.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
well_formed_ty T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
well_formed_ty T11 ->
update Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in TArrow T1 T2 ->
Gamma |- t2 \in T1 ->
Gamma |- tapp t1 t2 \in T2
| T_Proj : forall Gamma i t T Ti,
Gamma |- t \in T ->
Tlookup i T = Some Ti ->
Gamma |- tproj t i \in Ti
(* Subsumption *)
| T_Sub : forall Gamma t S T,
Gamma |- t \in S ->
subtype S T ->
Gamma |- t \in T
(* Rules for record terms *)
| T_RNil : forall Gamma,
Gamma |- trnil \in TRNil
| T_RCons : forall Gamma i t T tr Tr,
Gamma |- t \in T ->
Gamma |- tr \in Tr ->
record_ty Tr ->
record_tm tr ->
Gamma |- trcons i t tr \in TRCons i T Tr
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(* ================================================================= *)
(** ** Typing Examples *)
Module Examples2.
Import Examples.
(** **** Exercise: 1 star *)
Definition trcd_kj :=
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil)).
Example typing_example_0 :
has_type empty
(trcons k (tabs z A (tvar z))
(trcons j (tabs z B (tvar z))
trnil))
TRcd_kj.
(* empty |- {k=(\z:A.z), j=(\z:B.z)} : {k:A->A,j:B->B} *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars *)
Example typing_example_1 :
has_type empty
(tapp (tabs x TRcd_j (tproj (tvar x) j))
(trcd_kj))
(TArrow B B).
(* empty |- (\x:{k:A->A,j:B->B}. x.j)
{k=(\z:A.z), j=(\z:B.z)}
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Example typing_example_2 :
has_type empty
(tapp (tabs z (TArrow (TArrow C C) TRcd_j)
(tproj (tapp (tvar z)
(tabs x C (tvar x)))
j))
(tabs z (TArrow C C) trcd_kj))
(TArrow B B).
(* empty |- (\z:(C->C)->{j:B->B}. (z (\x:C.x)).j)
(\z:C->C. {k=(\z:A.z), j=(\z:B.z)})
: B->B *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples2.
(* ================================================================= *)
(** ** Properties of Typing *)
(* ----------------------------------------------------------------- *)
(** *** Well-Formedness *)
Lemma has_type__wf : forall Gamma t T,
has_type Gamma t T -> well_formed_ty T.
Proof with eauto.
intros Gamma t T Htyp.
induction Htyp...
- (* T_App *)
inversion IHHtyp1...
- (* T_Proj *)
eapply wf_rcd_lookup...
- (* T_Sub *)
apply subtype__wf in H.
destruct H...
Qed.
Lemma step_preserves_record_tm : forall tr tr',
record_tm tr ->
tr ==> tr' ->
record_tm tr'.
Proof.
intros tr tr' Hrt Hstp.
inversion Hrt; subst; inversion Hstp; subst; eauto.
Qed.
(* ----------------------------------------------------------------- *)
(** *** Field Lookup *)
Lemma lookup_field_in_value : forall v T i Ti,
value v ->
has_type empty v T ->
Tlookup i T = Some Ti ->
exists vi, tlookup i v = Some vi /\ has_type empty vi Ti.
Proof with eauto.
remember empty as Gamma.
intros t T i Ti Hval Htyp. revert Ti HeqGamma Hval.
induction Htyp; intros; subst; try solve by inversion.
- (* T_Sub *)
apply (rcd_types_match S) in H0...
destruct H0 as [Si [HgetSi Hsub]].
destruct (IHHtyp Si) as [vi [Hget Htyvi]]...
- (* T_RCons *)
simpl in H0. simpl. simpl in H1.
destruct (beq_id i i0).
+ (* i is first *)
inversion H1. subst. exists t...
+ (* i in tail *)
destruct (IHHtyp2 Ti) as [vi [get Htyvi]]...
inversion Hval... Qed.
(* ----------------------------------------------------------------- *)
(** *** Progress *)
(** **** Exercise: 3 stars (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (TArrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tabs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
induction Ht;
intros HeqGamma; subst...
- (* T_Var *)
inversion H.
- (* T_App *)
right.
destruct IHHt1; subst...
+ (* t1 is a value *)
destruct IHHt2; subst...
* (* t2 is a value *)
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists ([x:=t2]t12)...
* (* t2 steps *)
destruct H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
destruct H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_Proj *)
right. destruct IHHt...
+ (* rcd is value *)
destruct (lookup_field_in_value t T i Ti)
as [t' [Hget Ht']]...
+ (* rcd_steps *)
destruct H0 as [t' Hstp]. exists (tproj t' i)...
- (* T_RCons *)
destruct IHHt1...
+ (* head is a value *)
destruct IHHt2...
* (* tail steps *)
right. destruct H2 as [tr' Hstp].
exists (trcons i t tr')...
+ (* head steps *)
right. destruct H1 as [t' Hstp].
exists (trcons i t' tr)... Qed.
(** _Theorem_ : For any term [t] and type [T], if [empty |- t : T]
then [t] is a value or [t ==> t'] for some term [t'].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We
proceed by induction on the given typing derivation.
- The cases where the last step in the typing derivation is
[T_Abs] or [T_RNil] are immediate because abstractions and
[{}] are always values. The case for [T_Var] is vacuous
because variables cannot be typed in the empty context.
- If the last step in the typing derivation is by [T_App], then
there are terms [t1] [t2] and types [T1] [T2] such that [t =
t1 t2], [T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 :
T1].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [t2] is a value or
steps.
- Suppose [t1 ==> t1'] for some term [t1']. Then [t1 t2 ==>
t1' t2] by [ST_App1].
- Otherwise [t1] is a value.
- Suppose [t2 ==> t2'] for some term [t2']. Then [t1 t2 ==>
t1 t2'] by rule [ST_App2] because [t1] is a value.
- Otherwise, [t2] is a value. By Lemma
[canonical_forms_for_arrow_types], [t1 = \x:S1.s2] for
some [x], [S1], and [s2]. But then [(\x:S1.s2) t2 ==>
[x:=t2]s2] by [ST_AppAbs], since [t2] is a value.
- If the last step of the derivation is by [T_Proj], then there
are a term [tr], a type [Tr], and a label [i] such that [t =
tr.i], [empty |- tr : Tr], and [Tlookup i Tr = Some T].
By the IH, either [tr] is a value or it steps. If [tr ==>
tr'] for some term [tr'], then [tr.i ==> tr'.i] by rule
[ST_Proj1].
If [tr] is a value, then Lemma [lookup_field_in_value] yields
that there is a term [ti] such that [tlookup i tr = Some ti].
It follows that [tr.i ==> ti] by rule [ST_ProjRcd].
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
desired result is exactly the induction hypothesis for the
typing subderivation.
- If the final step of the derivation is by [T_RCons], then
there exist some terms [t1] [tr], types [T1 Tr] and a label
[t] such that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm
tr], [record_tm Tr], [empty |- t1 : T1] and [empty |- tr :
Tr].
The induction hypotheses for these typing derivations yield
that [t1] is a value or steps, and that [tr] is a value or
steps. We consider each case:
- Suppose [t1 ==> t1'] for some term [t1']. Then [{i=t1, tr}
==> {i=t1', tr}] by rule [ST_Rcd_Head].
- Otherwise [t1] is a value.
- Suppose [tr ==> tr'] for some term [tr']. Then [{i=t1,
tr} ==> {i=t1, tr'}] by rule [ST_Rcd_Tail], since [t1] is
a value.
- Otherwise, [tr] is also a value. So, [{i=t1, tr}] is a
value by [v_rcons]. *)
(* ----------------------------------------------------------------- *)
(** *** Inversion Lemmas *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tvar x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tvar x) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_Var *)
exists T...
- (* T_Sub *)
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tapp t1 t2) T2 ->
exists T1,
has_type Gamma t1 (TArrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tapp t1 t2) as t.
induction Hty; intros;
inversion Heqt; subst; try solve by inversion.
- (* T_App *)
exists T1...
- (* T_Sub *)
destruct IHHty as [U1 [Hty1 Hty2]]...
assert (Hwf := has_type__wf _ _ _ Hty2).
exists U1... Qed.
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tabs x S1 t2) T ->
(exists S2, subtype (TArrow S1 S2) T
/\ has_type (update Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tabs x S1 t2) as t.
induction H;
inversion Heqt; subst; intros; try solve by inversion.
- (* T_Abs *)
assert (Hwf := has_type__wf _ _ _ H0).
exists T12...
- (* T_Sub *)
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
Lemma typing_inversion_proj : forall Gamma i t1 Ti,
has_type Gamma (tproj t1 i) Ti ->
exists T, exists Si,
Tlookup i T = Some Si /\ subtype Si Ti /\ has_type Gamma t1 T.
Proof with eauto.
intros Gamma i t1 Ti H.
remember (tproj t1 i) as t.
induction H;
inversion Heqt; subst; intros; try solve by inversion.
- (* T_Proj *)
assert (well_formed_ty Ti) as Hwf.
{ (* pf of assertion *)
apply (wf_rcd_lookup i T Ti)...
apply has_type__wf in H... }
exists T. exists Ti...
- (* T_Sub *)
destruct IHhas_type as [U [Ui [Hget [Hsub Hty]]]]...
exists U. exists Ui... Qed.
Lemma typing_inversion_rcons : forall Gamma i ti tr T,
has_type Gamma (trcons i ti tr) T ->
exists Si, exists Sr,
subtype (TRCons i Si Sr) T /\ has_type Gamma ti Si /\
record_tm tr /\ has_type Gamma tr Sr.
Proof with eauto.
intros Gamma i ti tr T Hty.
remember (trcons i ti tr) as t.
induction Hty;
inversion Heqt; subst...
- (* T_Sub *)
apply IHHty in H0.
destruct H0 as [Ri [Rr [HsubRS [HtypRi HtypRr]]]].
exists Ri. exists Rr...
- (* T_RCons *)
assert (well_formed_ty (TRCons i T Tr)) as Hwf.
{ (* pf of assertion *)
apply has_type__wf in Hty1.
apply has_type__wf in Hty2... }
exists T. exists Tr... Qed.
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tabs x S1 s2) (TArrow T1 T2) ->
subtype T1 S1
/\ has_type (update empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ----------------------------------------------------------------- *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_proj : forall x t i,
appears_free_in x t ->
appears_free_in x (tproj t i)
| afi_rhead : forall x i t tr,
appears_free_in x t ->
appears_free_in x (trcons i t tr)
| afi_rtail : forall x i t tr,
appears_free_in x tr ->
appears_free_in x (trcons i t tr).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold update, t_update. destruct (beq_idP x x0)...
- (* T_App *)
apply T_App with T1...
- (* T_RCons *)
apply T_RCons... Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp; subst; inversion Hafi; subst...
- (* T_Abs *)
destruct (IHHtyp H5) as [T Hctx]. exists T.
unfold update, t_update in Hctx.
rewrite false_beq_id in Hctx... Qed.
(* ----------------------------------------------------------------- *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (update Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
induction t; intros; simpl.
- (* tvar *)
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt) as [T [Hctx Hsub]].
unfold update, t_update in Hctx.
destruct (beq_idP x y)...
+ (* x=y *)
subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
destruct (subtype__wf _ _ Hsub)...
- (* tapp *)
destruct (typing_inversion_app _ _ _ _ Htypt)
as [T1 [Htypt1 Htypt2]].
eapply T_App...
- (* tabs *)
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
destruct (subtype__wf _ _ Hsub) as [Hwf1 Hwf2].
inversion Hwf2. subst.
apply T_Sub with (TArrow T1 T2)... apply T_Abs...
destruct (beq_idP x y).
+ (* x=y *)
eapply context_invariance...
subst.
intros x Hafi. unfold update, t_update.
destruct (beq_id y x)...
+ (* x<>y *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold update, t_update.
destruct (beq_idP y z)...
subst. rewrite false_beq_id...
- (* tproj *)
destruct (typing_inversion_proj _ _ _ _ Htypt)
as [T [Ti [Hget [Hsub Htypt1]]]]...
- (* trnil *)
eapply context_invariance...
intros y Hcontra. inversion Hcontra.
- (* trcons *)
destruct (typing_inversion_rcons _ _ _ _ _ Htypt) as
[Ti [Tr [Hsub [HtypTi [Hrcdt2 HtypTr]]]]].
apply T_Sub with (TRCons i Ti Tr)...
apply T_RCons...
+ (* record_ty Tr *)
apply subtype__wf in Hsub. destruct Hsub. inversion H0...
+ (* record_tm ([x:=v]t2) *)
inversion Hrcdt2; subst; simpl... Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
inversion HE; subst...
+ (* ST_AppAbs *)
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
- (* T_Proj *)
destruct (lookup_field_in_value _ _ _ _ H2 HT H)
as [vi [Hget Hty]].
rewrite H4 in Hget. inversion Hget. subst...
- (* T_RCons *)
eauto using step_preserves_record_tm. Qed.
(** _Theorem_: If [t], [t'] are terms and [T] is a type such that
[empty |- t : T] and [t ==> t'], then [empty |- t' : T].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We go
by induction on the structure of this typing derivation, leaving
[t'] general. Cases [T_Abs] and [T_RNil] are vacuous because
abstractions and [{}] don't step. Case [T_Var] is vacuous as well,
since the context is empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then
[t1 = \x:S.t12] for some type [S] and term [t12], and
[t' = [x:=t2]t12].
By Lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by lemma [substitution_preserves_typing] that
[empty |- [x:=t2] t12 : T2] as desired.
- If the final step of the derivation is by [T_Proj], then there
is a term [tr], type [Tr] and label [i] such that [t = tr.i],
[empty |- tr : Tr], and [Tlookup i Tr = Some T].
The IH for the typing derivation gives us that, for any term
[tr'], if [tr ==> tr'] then [empty |- tr' Tr]. Inspection of
the definition of the step relation reveals that there are two
ways a projection can step. Case [ST_Proj1] follows
immediately by the IH.
Instead suppose [tr.i] steps by [ST_ProjRcd]. Then [tr] is a
value and there is some term [vi] such that
[tlookup i tr = Some vi] and [t' = vi]. But by lemma
[lookup_field_in_value], [empty |- vi : Ti] as desired.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub].
- If the final step of the derivation is by [T_RCons], then there
exist some terms [t1] [tr], types [T1 Tr] and a label [t] such
that [t = {i=t1, tr}], [T = {i:T1, Tr}], [record_tm tr],
[record_tm Tr], [empty |- t1 : T1] and [empty |- tr : Tr].
By the definition of the step relation, [t] must have stepped
by [ST_Rcd_Head] or [ST_Rcd_Tail]. In the first case, the
result follows by the IH for [t1]'s typing derivation and
[T_RCons]. In the second case, the result follows by the IH
for [tr]'s typing derivation, [T_RCons], and a use of the
[step_preserves_record_tm] lemma. *)
(** $Date: 2016-05-27 14:19:30 -0400 (Fri, 27 May 2016) $ *)
|
// ======================================================================
// BLE_ADC.v generated from TopDesign.cysch
// 11/19/2016 at 08:39
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4G 2
`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4G_ES 17
`define CYDEV_CHIP_REVISION_4G_ES2 33
`define CYDEV_CHIP_MEMBER_4U 3
`define CYDEV_CHIP_REVISION_4U_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4E 4
`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4O 5
`define CYDEV_CHIP_REVISION_4O_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4N 6
`define CYDEV_CHIP_REVISION_4N_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4D 7
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4J 8
`define CYDEV_CHIP_REVISION_4J_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4K 9
`define CYDEV_CHIP_REVISION_4K_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4H 10
`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 11
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 12
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4F 13
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4M 14
`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4L 15
`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4I 16
`define CYDEV_CHIP_REVISION_4I_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4C 17
`define CYDEV_CHIP_REVISION_4C_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5B 18
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 19
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 13
`define CYDEV_CHIP_REVISION_USED 0
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// Component: cy_analog_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`endif
// Component: Bus_Connect_v2_40
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40\Bus_Connect_v2_40.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40\Bus_Connect_v2_40.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// ADC_SAR_SEQ_P4_v2_40(AdcAClock=4, AdcAdjust=0, AdcAlternateResolution=0, AdcAvgMode=1, AdcAvgSamplesNum=0, AdcBClock=4, AdcCClock=4, AdcChannelsEnConf=1, AdcChannelsModeConf=0, AdcClock=1, AdcClockFrequency=2999988, AdcCompareMode=0, AdcDataFormatJustification=0, AdcDClock=4, AdcDedicatedExtVref=true, AdcDifferentialResultFormat=1, AdcHighLimit=2047, AdcInjChannelEnabled=false, AdcInputBufGain=0, AdcLowLimit=0, AdcMaxResolution=12, AdcSampleMode=0, AdcSarMuxChannelConfig=0, AdcSequencedChannels=1, AdcSingleEndedNegativeInput=0, AdcSingleResultFormat=1, AdcSymbolHasSingleEndedInputChannel=false, AdcTotalChannels=1, AdcVrefSelect=3, AdcVrefVoltage_mV=1024, rm_int=false, SeqChannelsConfigTable=<?xml version="1.0" encoding="utf-16"?><CyChannelsConfigTable xmlns:Version="2_40"><m_channelsConfigTable><CyChannelsConfigTableRow><m_enabled>false</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Diff</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow><CyChannelsConfigTableRow><m_enabled>true</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Single</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow></m_channelsConfigTable></CyChannelsConfigTable>, TermMode_aclk=0, TermMode_eoc=0, TermMode_sdone=0, TermMode_soc=0, TermMode_vinMinus0=0, TermMode_vinMinus1=0, TermMode_vinMinus10=0, TermMode_vinMinus11=0, TermMode_vinMinus12=0, TermMode_vinMinus13=0, TermMode_vinMinus14=0, TermMode_vinMinus15=0, TermMode_vinMinus2=0, TermMode_vinMinus3=0, TermMode_vinMinus4=0, TermMode_vinMinus5=0, TermMode_vinMinus6=0, TermMode_vinMinus7=0, TermMode_vinMinus8=0, TermMode_vinMinus9=0, TermMode_vinMinusINJ=0, TermMode_vinNeg=0, TermMode_vinPlus0=0, TermMode_vinPlus1=0, TermMode_vinPlus10=0, TermMode_vinPlus11=0, TermMode_vinPlus12=0, TermMode_vinPlus13=0, TermMode_vinPlus14=0, TermMode_vinPlus15=0, TermMode_vinPlus2=0, TermMode_vinPlus3=0, TermMode_vinPlus4=0, TermMode_vinPlus5=0, TermMode_vinPlus6=0, TermMode_vinPlus7=0, TermMode_vinPlus8=0, TermMode_vinPlus9=0, TermMode_vinPlusINJ=0, TermMode_Vref=0, TermVisibility_aclk=false, TermVisibility_eoc=true, TermVisibility_sdone=true, TermVisibility_soc=false, TermVisibility_vinMinus0=false, TermVisibility_vinMinus1=false, TermVisibility_vinMinus10=false, TermVisibility_vinMinus11=false, TermVisibility_vinMinus12=false, TermVisibility_vinMinus13=false, TermVisibility_vinMinus14=false, TermVisibility_vinMinus15=false, TermVisibility_vinMinus2=false, TermVisibility_vinMinus3=false, TermVisibility_vinMinus4=false, TermVisibility_vinMinus5=false, TermVisibility_vinMinus6=false, TermVisibility_vinMinus7=false, TermVisibility_vinMinus8=false, TermVisibility_vinMinus9=false, TermVisibility_vinMinusINJ=false, TermVisibility_vinNeg=false, TermVisibility_vinPlus0=true, TermVisibility_vinPlus1=false, TermVisibility_vinPlus10=false, TermVisibility_vinPlus11=false, TermVisibility_vinPlus12=false, TermVisibility_vinPlus13=false, TermVisibility_vinPlus14=false, TermVisibility_vinPlus15=false, TermVisibility_vinPlus2=false, TermVisibility_vinPlus3=false, TermVisibility_vinPlus4=false, TermVisibility_vinPlus5=false, TermVisibility_vinPlus6=false, TermVisibility_vinPlus7=false, TermVisibility_vinPlus8=false, TermVisibility_vinPlus9=false, TermVisibility_vinPlusINJ=false, TermVisibility_Vref=false, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=ADC_SAR_SEQ_P4_v2_40, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=ADC_SAR, CY_INSTANCE_SHORT_NAME=ADC_SAR, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP3, INSTANCE_NAME=ADC_SAR, )
module ADC_SAR_SEQ_P4_v2_40_0 (
soc,
aclk,
Vref,
sdone,
eoc,
vinPlus0);
input soc;
input aclk;
inout Vref;
electrical Vref;
output sdone;
output eoc;
inout vinPlus0;
electrical vinPlus0;
wire Net_3209;
electrical Net_3164;
wire Net_3128;
wire [11:0] Net_3111;
wire Net_3110;
wire [3:0] Net_3109;
wire Net_3108;
electrical Net_3166;
electrical Net_3167;
electrical Net_3168;
electrical Net_3169;
electrical Net_3170;
electrical Net_3171;
electrical Net_3172;
electrical Net_3173;
electrical Net_3174;
electrical Net_3175;
electrical Net_3176;
electrical Net_3177;
electrical Net_3178;
electrical Net_3179;
electrical Net_3180;
electrical muxout_plus;
electrical Net_3181;
electrical muxout_minus;
electrical Net_3227;
electrical Net_3113;
electrical Net_3225;
electrical [16:0] mux_bus_minus;
electrical [16:0] mux_bus_plus;
electrical Net_3226;
wire Net_3103;
wire Net_3104;
wire Net_3105;
wire Net_3106;
wire Net_3107;
electrical Net_3165;
electrical Net_3182;
electrical Net_3183;
electrical Net_3184;
electrical Net_3185;
electrical Net_3186;
electrical Net_3187;
electrical Net_3188;
electrical Net_3189;
electrical Net_3190;
electrical Net_3191;
electrical Net_3192;
electrical Net_3193;
electrical Net_3194;
electrical Net_3195;
electrical Net_3196;
electrical Net_3197;
electrical Net_3198;
electrical Net_3132;
electrical Net_3133;
electrical Net_3134;
electrical Net_3135;
electrical Net_3136;
electrical Net_3137;
electrical Net_3138;
electrical Net_3139;
electrical Net_3140;
electrical Net_3141;
electrical Net_3142;
electrical Net_3143;
electrical Net_3144;
electrical Net_3145;
electrical Net_3146;
electrical Net_3147;
electrical Net_3148;
electrical Net_3149;
electrical Net_3150;
electrical Net_3151;
electrical Net_3152;
electrical Net_3153;
electrical Net_3154;
electrical Net_3159;
electrical Net_3157;
electrical Net_3158;
electrical Net_3160;
electrical Net_3161;
electrical Net_3162;
electrical Net_3163;
electrical Net_3156;
electrical Net_3155;
wire Net_3120;
electrical Net_3119;
electrical Net_3118;
wire Net_3124;
electrical Net_3122;
electrical Net_3117;
electrical Net_3121;
electrical Net_3123;
wire Net_3112;
wire Net_3126;
wire Net_3125;
electrical Net_2793;
electrical Net_2794;
electrical Net_1851;
electrical Net_2580;
electrical [0:0] Net_2375;
electrical [0:0] Net_1450;
electrical Net_3046;
electrical Net_3016;
wire Net_3235;
electrical Net_2099;
wire Net_17;
wire Net_1845;
electrical Net_2020;
electrical Net_124;
electrical Net_2102;
wire [1:0] Net_3207;
electrical Net_8;
electrical Net_43;
ZeroTerminal ZeroTerminal_8 (
.z(Net_3125));
assign Net_3126 = Net_1845 | Net_3125;
cy_isr_v1_0
#(.int_type(2'b10))
IRQ
(.int_signal(Net_3112));
cy_analog_noconnect_v1_0 cy_analog_noconnect_44 (
.noconnect(Net_3123));
cy_analog_noconnect_v1_0 cy_analog_noconnect_40 (
.noconnect(Net_3121));
cy_analog_noconnect_v1_0 cy_analog_noconnect_39 (
.noconnect(Net_3117));
// cy_analog_virtualmux_43 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_43_connect(Net_124, muxout_minus);
defparam cy_analog_virtualmux_43_connect.sig_width = 1;
// cy_analog_virtualmux_42 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_42_connect(Net_2020, muxout_plus);
defparam cy_analog_virtualmux_42_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_38 (
.noconnect(Net_3118));
cy_analog_noconnect_v1_0 cy_analog_noconnect_41 (
.noconnect(Net_3119));
cy_analog_noconnect_v1_0 cy_analog_noconnect_43 (
.noconnect(Net_3122));
// adc_plus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_plus_in_sel_connect(muxout_plus, mux_bus_plus[0]);
defparam adc_plus_in_sel_connect.sig_width = 1;
Bus_Connect_v2_40 Connect_1 (
.in_bus(mux_bus_plus[16:0]),
.out_bus(Net_1450[0:0]));
defparam Connect_1.in_width = 17;
defparam Connect_1.out_width = 1;
// adc_minus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_minus_in_sel_connect(muxout_minus, mux_bus_minus[0]);
defparam adc_minus_in_sel_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_3 (
.noconnect(Net_1851));
// cy_analog_virtualmux_37 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_37_connect(Net_3016, mux_bus_plus[1]);
defparam cy_analog_virtualmux_37_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_21 (
.noconnect(Net_3147));
cy_analog_noconnect_v1_0 cy_analog_noconnect_20 (
.noconnect(Net_3146));
cy_analog_noconnect_v1_0 cy_analog_noconnect_19 (
.noconnect(Net_3145));
cy_analog_noconnect_v1_0 cy_analog_noconnect_18 (
.noconnect(Net_3144));
cy_analog_noconnect_v1_0 cy_analog_noconnect_17 (
.noconnect(Net_3143));
cy_analog_noconnect_v1_0 cy_analog_noconnect_16 (
.noconnect(Net_3142));
cy_analog_noconnect_v1_0 cy_analog_noconnect_15 (
.noconnect(Net_3141));
cy_analog_noconnect_v1_0 cy_analog_noconnect_14 (
.noconnect(Net_3140));
cy_analog_noconnect_v1_0 cy_analog_noconnect_13 (
.noconnect(Net_3139));
cy_analog_noconnect_v1_0 cy_analog_noconnect_12 (
.noconnect(Net_3138));
cy_analog_noconnect_v1_0 cy_analog_noconnect_11 (
.noconnect(Net_3137));
cy_analog_noconnect_v1_0 cy_analog_noconnect_10 (
.noconnect(Net_3136));
cy_analog_noconnect_v1_0 cy_analog_noconnect_9 (
.noconnect(Net_3135));
cy_analog_noconnect_v1_0 cy_analog_noconnect_8 (
.noconnect(Net_3134));
cy_analog_noconnect_v1_0 cy_analog_noconnect_7 (
.noconnect(Net_3133));
cy_analog_noconnect_v1_0 cy_analog_noconnect_6 (
.noconnect(Net_3132));
// cy_analog_virtualmux_36 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_36_connect(Net_3046, mux_bus_minus[1]);
defparam cy_analog_virtualmux_36_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_37 (
.noconnect(Net_3165));
ZeroTerminal ZeroTerminal_5 (
.z(Net_3107));
ZeroTerminal ZeroTerminal_4 (
.z(Net_3106));
ZeroTerminal ZeroTerminal_3 (
.z(Net_3105));
ZeroTerminal ZeroTerminal_2 (
.z(Net_3104));
ZeroTerminal ZeroTerminal_1 (
.z(Net_3103));
cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
.noconnect(Net_3113));
// ext_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vref_sel_connect(Net_43, Net_3227);
defparam ext_vref_sel_connect.sig_width = 1;
Bus_Connect_v2_40 Connect_2 (
.in_bus(mux_bus_minus[16:0]),
.out_bus(Net_2375[0:0]));
defparam Connect_2.in_width = 17;
defparam Connect_2.out_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_35 (
.noconnect(Net_3181));
cy_analog_noconnect_v1_0 cy_analog_noconnect_34 (
.noconnect(Net_3180));
cy_analog_noconnect_v1_0 cy_analog_noconnect_33 (
.noconnect(Net_3179));
cy_analog_noconnect_v1_0 cy_analog_noconnect_32 (
.noconnect(Net_3178));
cy_analog_noconnect_v1_0 cy_analog_noconnect_31 (
.noconnect(Net_3177));
cy_analog_noconnect_v1_0 cy_analog_noconnect_30 (
.noconnect(Net_3176));
cy_analog_noconnect_v1_0 cy_analog_noconnect_29 (
.noconnect(Net_3175));
cy_analog_noconnect_v1_0 cy_analog_noconnect_28 (
.noconnect(Net_3174));
cy_analog_noconnect_v1_0 cy_analog_noconnect_27 (
.noconnect(Net_3173));
cy_analog_noconnect_v1_0 cy_analog_noconnect_26 (
.noconnect(Net_3172));
cy_analog_noconnect_v1_0 cy_analog_noconnect_25 (
.noconnect(Net_3171));
cy_analog_noconnect_v1_0 cy_analog_noconnect_24 (
.noconnect(Net_3170));
cy_analog_noconnect_v1_0 cy_analog_noconnect_23 (
.noconnect(Net_3169));
cy_analog_noconnect_v1_0 cy_analog_noconnect_22 (
.noconnect(Net_3168));
cy_analog_noconnect_v1_0 cy_analog_noconnect_4 (
.noconnect(Net_3167));
cy_analog_noconnect_v1_0 cy_analog_noconnect_2 (
.noconnect(Net_3166));
// int_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 int_vref_sel_connect(Net_8, Net_3113);
defparam int_vref_sel_connect.sig_width = 1;
// clk_src_sel (cy_virtualmux_v1_0)
assign Net_17 = Net_1845;
cy_psoc4_sar_v1_0 cy_psoc4_sar (
.vplus(Net_2020),
.vminus(Net_124),
.vref(Net_8),
.ext_vref(Net_43),
.clock(Net_17),
.sw_negvref(Net_3103),
.cfg_st_sel(Net_3207[1:0]),
.cfg_average(Net_3104),
.cfg_resolution(Net_3105),
.cfg_differential(Net_3106),
.trigger(Net_3235),
.data_hilo_sel(Net_3107),
.sample_done(sdone),
.chan_id_valid(Net_3108),
.chan_id(Net_3109[3:0]),
.data_valid(Net_3110),
.eos_intr(eoc),
.data(Net_3111[11:0]),
.irq(Net_3112));
// ext_vneg_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vneg_sel_connect(Net_2580, Net_1851);
defparam ext_vneg_sel_connect.sig_width = 1;
// VMux_soc (cy_virtualmux_v1_0)
assign Net_3235 = soc;
ZeroTerminal ZeroTerminal_6 (
.z(Net_3207[0]));
ZeroTerminal ZeroTerminal_7 (
.z(Net_3207[1]));
// cy_analog_virtualmux_vplus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus0_connect(mux_bus_plus[0], vinPlus0);
defparam cy_analog_virtualmux_vplus0_connect.sig_width = 1;
// cy_analog_virtualmux_vplus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus1_connect(mux_bus_plus[1], Net_3132);
defparam cy_analog_virtualmux_vplus1_connect.sig_width = 1;
// cy_analog_virtualmux_vplus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus2_connect(mux_bus_plus[2], Net_3133);
defparam cy_analog_virtualmux_vplus2_connect.sig_width = 1;
// cy_analog_virtualmux_vplus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus3_connect(mux_bus_plus[3], Net_3134);
defparam cy_analog_virtualmux_vplus3_connect.sig_width = 1;
// cy_analog_virtualmux_vplus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus4_connect(mux_bus_plus[4], Net_3135);
defparam cy_analog_virtualmux_vplus4_connect.sig_width = 1;
// cy_analog_virtualmux_vplus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus5_connect(mux_bus_plus[5], Net_3136);
defparam cy_analog_virtualmux_vplus5_connect.sig_width = 1;
// cy_analog_virtualmux_vplus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus6_connect(mux_bus_plus[6], Net_3137);
defparam cy_analog_virtualmux_vplus6_connect.sig_width = 1;
// cy_analog_virtualmux_vplus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus7_connect(mux_bus_plus[7], Net_3138);
defparam cy_analog_virtualmux_vplus7_connect.sig_width = 1;
// cy_analog_virtualmux_vplus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus8_connect(mux_bus_plus[8], Net_3139);
defparam cy_analog_virtualmux_vplus8_connect.sig_width = 1;
// cy_analog_virtualmux_vplus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus9_connect(mux_bus_plus[9], Net_3140);
defparam cy_analog_virtualmux_vplus9_connect.sig_width = 1;
// cy_analog_virtualmux_vplus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus10_connect(mux_bus_plus[10], Net_3141);
defparam cy_analog_virtualmux_vplus10_connect.sig_width = 1;
// cy_analog_virtualmux_vplus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus11_connect(mux_bus_plus[11], Net_3142);
defparam cy_analog_virtualmux_vplus11_connect.sig_width = 1;
// cy_analog_virtualmux_vplus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus12_connect(mux_bus_plus[12], Net_3143);
defparam cy_analog_virtualmux_vplus12_connect.sig_width = 1;
// cy_analog_virtualmux_vplus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus13_connect(mux_bus_plus[13], Net_3144);
defparam cy_analog_virtualmux_vplus13_connect.sig_width = 1;
// cy_analog_virtualmux_vplus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus14_connect(mux_bus_plus[14], Net_3145);
defparam cy_analog_virtualmux_vplus14_connect.sig_width = 1;
// cy_analog_virtualmux_vplus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus15_connect(mux_bus_plus[15], Net_3146);
defparam cy_analog_virtualmux_vplus15_connect.sig_width = 1;
// cy_analog_virtualmux_vplus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus_inj_connect(Net_3016, Net_3147);
defparam cy_analog_virtualmux_vplus_inj_connect.sig_width = 1;
// cy_analog_virtualmux_vminus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus0_connect(mux_bus_minus[0], Net_3166);
defparam cy_analog_virtualmux_vminus0_connect.sig_width = 1;
// cy_analog_virtualmux_vminus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus1_connect(mux_bus_minus[1], Net_3167);
defparam cy_analog_virtualmux_vminus1_connect.sig_width = 1;
// cy_analog_virtualmux_vminus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus2_connect(mux_bus_minus[2], Net_3168);
defparam cy_analog_virtualmux_vminus2_connect.sig_width = 1;
// cy_analog_virtualmux_vminus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus3_connect(mux_bus_minus[3], Net_3169);
defparam cy_analog_virtualmux_vminus3_connect.sig_width = 1;
// cy_analog_virtualmux_vminus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus4_connect(mux_bus_minus[4], Net_3170);
defparam cy_analog_virtualmux_vminus4_connect.sig_width = 1;
// cy_analog_virtualmux_vminus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus5_connect(mux_bus_minus[5], Net_3171);
defparam cy_analog_virtualmux_vminus5_connect.sig_width = 1;
// cy_analog_virtualmux_vminus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus6_connect(mux_bus_minus[6], Net_3172);
defparam cy_analog_virtualmux_vminus6_connect.sig_width = 1;
// cy_analog_virtualmux_vminus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus7_connect(mux_bus_minus[7], Net_3173);
defparam cy_analog_virtualmux_vminus7_connect.sig_width = 1;
// cy_analog_virtualmux_vminus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus8_connect(mux_bus_minus[8], Net_3174);
defparam cy_analog_virtualmux_vminus8_connect.sig_width = 1;
// cy_analog_virtualmux_vminus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus9_connect(mux_bus_minus[9], Net_3175);
defparam cy_analog_virtualmux_vminus9_connect.sig_width = 1;
// cy_analog_virtualmux_vminus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus10_connect(mux_bus_minus[10], Net_3176);
defparam cy_analog_virtualmux_vminus10_connect.sig_width = 1;
// cy_analog_virtualmux_vminus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus11_connect(mux_bus_minus[11], Net_3177);
defparam cy_analog_virtualmux_vminus11_connect.sig_width = 1;
// cy_analog_virtualmux_vminus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus12_connect(mux_bus_minus[12], Net_3178);
defparam cy_analog_virtualmux_vminus12_connect.sig_width = 1;
// cy_analog_virtualmux_vminus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus13_connect(mux_bus_minus[13], Net_3179);
defparam cy_analog_virtualmux_vminus13_connect.sig_width = 1;
// cy_analog_virtualmux_vminus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus14_connect(mux_bus_minus[14], Net_3180);
defparam cy_analog_virtualmux_vminus14_connect.sig_width = 1;
// cy_analog_virtualmux_vminus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus15_connect(mux_bus_minus[15], Net_3181);
defparam cy_analog_virtualmux_vminus15_connect.sig_width = 1;
// cy_analog_virtualmux_vminus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus_inj_connect(Net_3046, Net_3165);
defparam cy_analog_virtualmux_vminus_inj_connect.sig_width = 1;
cy_clock_v1_0
#(.id("2c8f831a-eb04-4562-a197-2a3531daa1f2/5c71752a-e182-47ca-942c-9cb20adbdf2f"),
.source_clock_id(""),
.divisor(0),
.period("333334666.672"),
.is_direct(0),
.is_digital(0))
intClock
(.clock_out(Net_1845));
cy_analog_noconnect_v1_0 cy_analog_noconnect_5 (
.noconnect(Net_3227));
endmodule
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// BLE_v3_10(AutopopulateWhitelist=true, EnableExternalPAcontrol=false, EnableExternalPrepWriteBuff=false, EnableL2capLogicalChannels=true, EnableLinkLayerPrivacy=false, GapConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<CyGapConfiguration xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema">\r\n <DevAddress>00A050000000</DevAddress>\r\n <SiliconGeneratedAddress>true</SiliconGeneratedAddress>\r\n <MtuSize>23</MtuSize>\r\n <MaxTxPayloadSize>27</MaxTxPayloadSize>\r\n <MaxRxPayloadSize>27</MaxRxPayloadSize>\r\n <TxPowerLevel>0</TxPowerLevel>\r\n <TxPowerLevelConnection>0</TxPowerLevelConnection>\r\n <TxPowerLevelAdvScan>0</TxPowerLevelAdvScan>\r\n <SecurityConfig>\r\n <SecurityMode>SECURITY_MODE_1</SecurityMode>\r\n <SecurityLevel>NO_SECURITY</SecurityLevel>\r\n <StrictPairing>false</StrictPairing>\r\n <KeypressNotifications>false</KeypressNotifications>\r\n <IOCapability>NO_INPUT_NO_OUTPUT</IOCapability>\r\n <PairingMethod>JUST_WORKS</PairingMethod>\r\n <Bonding>NO_BOND</Bonding>\r\n <MaxBondedDevices>4</MaxBondedDevices>\r\n <AutoPopWhitelistBondedDev>true</AutoPopWhitelistBondedDev>\r\n <MaxWhitelistSize>8</MaxWhitelistSize>\r\n <EnableLinkLayerPrivacy>false</EnableLinkLayerPrivacy>\r\n <MaxResolvableDevices>8</MaxResolvableDevices>\r\n <EncryptionKeySize>16</EncryptionKeySize>\r\n </SecurityConfig>\r\n <AdvertisementConfig>\r\n <AdvScanMode>FAST_CONNECTION</AdvScanMode>\r\n <AdvFastScanInterval>\r\n <Minimum>80</Minimum>\r\n <Maximum>100</Maximum>\r\n </AdvFastScanInterval>\r\n <AdvReducedScanInterval>\r\n <Minimum>1000</Minimum>\r\n <Maximum>10240</Maximum>\r\n </AdvReducedScanInterval>\r\n <AdvDiscoveryMode>GENERAL</AdvDiscoveryMode>\r\n <AdvType>CONNECTABLE_UNDIRECTED</AdvType>\r\n <AdvFilterPolicy>SCAN_REQUEST_ANY_CONNECT_REQUEST_ANY</AdvFilterPolicy>\r\n <AdvChannelMap>ALL</AdvChannelMap>\r\n <AdvFastTimeout>0</AdvFastTimeout>\r\n <AdvReducedTimeout>150</AdvReducedTimeout>\r\n <EnableReducedAdvertising>false</EnableReducedAdvertising>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </AdvertisementConfig>\r\n <ScanConfig>\r\n <ScanFastWindow>30</ScanFastWindow>\r\n <ScanFastInterval>30</ScanFastInterval>\r\n <ScanTimeout>30</ScanTimeout>\r\n <ScanReducedWindow>1125</ScanReducedWindow>\r\n <ScanReducedInterval>1280</ScanReducedInterval>\r\n <ScanReducedTimeout>150</ScanReducedTimeout>\r\n <EnableReducedScan>true</EnableReducedScan>\r\n <ScanDiscoveryMode>GENERAL</ScanDiscoveryMode>\r\n <ScanningState>ACTIVE</ScanningState>\r\n <ScanFilterPolicy>ACCEPT_ALL_ADV_PACKETS</ScanFilterPolicy>\r\n <DuplicateFiltering>false</DuplicateFiltering>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </ScanConfig>\r\n <AdvertisementPacket>\r\n <PacketType>ADVERTISEMENT</PacketType>\r\n <Items>\r\n <CyADStructure>\r\n <ADType>1</ADType>\r\n <ADData>06</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>9</ADType>\r\n <ADData>4D:4D:5F:54:68:65:72:6D:69:73:74:6F:72</ADData>\r\n </CyADStructure>\r\n </Items>\r\n <IncludedServicesServiceUuid />\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </AdvertisementPacket>\r\n <ScanResponsePacket>\r\n <PacketType>SCAN_RESPONSE</PacketType>\r\n <Items />\r\n <IncludedServicesServiceUuid />\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </ScanResponsePacket>\r\n</CyGapConfiguration>, HalBaudRate=115200, ImportFilePath=, KeypressNotifications=false, L2capMpsSize=23, L2capMtuSize=23, L2capNumChannels=1, L2capNumPsm=1, LLMaxRxPayloadSize=27, LLMaxTxPayloadSize=27, MaxAttrNoOfBuffer=1, MaxBondedDevices=4, MaxResolvableDevices=8, MaxWhitelistSize=8, Mode=0, ProfileConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<Profile xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema" ID="1" DisplayName="Custom" Name="Custom" Type="org.bluetooth.profile.custom">\r\n <CyProfileRole ID="2" DisplayName="Server" Name="Server">\r\n <CyService ID="3" DisplayName="Generic Access" Name="Generic Access" Type="org.bluetooth.service.generic_access" UUID="1800">\r\n <CyCharacteristic ID="4" DisplayName="Device Name" Name="Device Name" Type="org.bluetooth.characteristic.gap.device_name" UUID="2A00">\r\n <Field Name="Name">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>13</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>MM_Thermistor</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="5" DisplayName="Appearance" Name="Appearance" Type="org.bluetooth.characteristic.gap.appearance" UUID="2A01">\r\n <Field Name="Category">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>ENUM</ValueType>\r\n <EnumValue>768</EnumValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="6" DisplayName="Peripheral Preferred Connection Parameters" Name="Peripheral Preferred Connection Parameters" Type="org.bluetooth.characteristic.gap.peripheral_preferred_connection_parameters" UUID="2A04">\r\n <Field Name="Minimum Connection Interval">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>6</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x0006</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Maximum Connection Interval">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>6</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x0028</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Slave Latency">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>1000</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Connection Supervision Timeout Multiplier">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>10</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x03E8</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="7" DisplayName="Central Address Resolution" Name="Central Address Resolution" Type="org.bluetooth.characteristic.gap.central_address_resolution" UUID="2AA6">\r\n <Field Name="Central Address Resolution Support">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="8" DisplayName="Generic Attribute" Name="Generic Attribute" Type="org.bluetooth.service.generic_attribute" UUID="1801">\r\n <CyCharacteristic ID="9" DisplayName="Service Changed" Name="Service Changed" Type="org.bluetooth.characteristic.gatt.service_changed" UUID="2A05">\r\n <CyDescriptor ID="10" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Start of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="End of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="INDICATE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>NONE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="11" DisplayName="Thermometer" Name="Custom Service" Type="org.bluetooth.service.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyCharacteristic ID="12" DisplayName="Temperature" Name="Custom Characteristic" Type="org.bluetooth.characteristic.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyDescriptor ID="13" DisplayName="Characteristic User Description" Name="Characteristic User Description" Type="org.bluetooth.descriptor.gatt.characteristic_user_description" UUID="2901">\r\n <Field Name="User Description">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>22</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>Thermistor Temperature</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyDescriptor>\r\n <CyDescriptor ID="14" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>1</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="true" Mandatory="false" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Temperature">\r\n <DataFormat>uint8_array</DataFormat>\r\n <ByteLength>4</ByteLength>\r\n <ValueType>ARRAY</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="BROADCAST" Present="false" Mandatory="false" />\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITE_WITHOUT_RESPONSE" Present="false" Mandatory="false" />\r\n <Property Type="NOTIFY" Present="true" Mandatory="false" />\r\n <Property Type="INDICATE" Present="false" Mandatory="false" />\r\n <Property Type="AUTHENTICATED_SIGNED_WRITES" Present="false" Mandatory="false" />\r\n <Property Type="RELIABLE_WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITABLE_AUXILIARIES" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>PrimarySingleInstance</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <ProfileRoleIndex>0</ProfileRoleIndex>\r\n <RoleType>SERVER</RoleType>\r\n </CyProfileRole>\r\n <GapRole>PERIPHERAL</GapRole>\r\n</Profile>, SharingMode=0, StackMode=3, StrictPairing=false, UseDeepSleep=true, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=BLE_v3_10, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=BLE_v3_10.pdf, CY_FITTER_NAME=BLE, CY_INSTANCE_SHORT_NAME=BLE, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP3, INSTANCE_NAME=BLE, )
module BLE_v3_10_1 (
clk,
pa_en);
output clk;
output pa_en;
wire Net_55;
wire Net_60;
wire Net_53;
wire Net_72;
wire Net_71;
wire Net_70;
wire Net_15;
wire Net_14;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15),
.rf_ext_pa_en(pa_en));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("e1fabf2a-6555-450d-b095-7b11ed8011cc/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_53 | Net_55;
assign Net_55 = 1'h0;
endmodule
// top
module top ;
wire Net_183;
wire Net_182;
wire Net_175;
wire Net_174;
wire Net_173;
wire Net_172;
electrical Net_171;
electrical Net_45;
ADC_SAR_SEQ_P4_v2_40_0 ADC_SAR (
.Vref(Net_171),
.sdone(Net_172),
.eoc(Net_173),
.aclk(1'b0),
.soc(1'b0),
.vinPlus0(Net_45));
wire [0:0] tmpOE__THERMISTOR_net;
wire [0:0] tmpFB_0__THERMISTOR_net;
wire [0:0] tmpIO_0__THERMISTOR_net;
wire [0:0] tmpINTERRUPT_0__THERMISTOR_net;
electrical [0:0] tmpSIOVREF__THERMISTOR_net;
cy_psoc3_pins_v1_10
#(.id("77715107-f8d5-47e5-a629-0fb83101ac6b"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
THERMISTOR
(.oe(tmpOE__THERMISTOR_net),
.y({1'b0}),
.fb({tmpFB_0__THERMISTOR_net[0:0]}),
.analog({Net_45}),
.io({tmpIO_0__THERMISTOR_net[0:0]}),
.siovref(tmpSIOVREF__THERMISTOR_net),
.interrupt({tmpINTERRUPT_0__THERMISTOR_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__THERMISTOR_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
BLE_v3_10_1 BLE (
.clk(Net_182),
.pa_en(Net_183));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_BLACKBOX_V
`define SKY130_FD_SC_LP__FAH_BLACKBOX_V
/**
* fah: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__fah (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_BLACKBOX_V
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module memory_dp_48x4096 (
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [5 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [47 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
input wire clkb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
input wire enb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
input wire [11 : 0] addrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
output wire [47 : 0] doutb;
blk_mem_gen_v8_2 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(1),
.C_BYTE_SIZE(8),
.C_ALGORITHM(0),
.C_PRIM_TYPE(3),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("memory_dp_48x4096.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(6),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(48),
.C_READ_WIDTH_A(48),
.C_WRITE_DEPTH_A(4096),
.C_READ_DEPTH_A(4096),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(1),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(6),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(48),
.C_READ_WIDTH_B(48),
.C_WRITE_DEPTH_B(4096),
.C_READ_DEPTH_B(4096),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("6"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 27.3621 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(),
.clkb(clkb),
.rstb(1'D0),
.enb(enb),
.regceb(1'D0),
.web(6'B0),
.addrb(addrb),
.dinb(48'B0),
.doutb(doutb),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(48'B0),
.s_axi_wstrb(6'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`include "~/ee577b/syn/src/control.h"
/*
*ALU Functions Included (in order coded below):
* ADD
* AND
* NOT
* OR
* XOR
* SUB
* PRM
*
*Other Functions:
* LD (NOP)
* WMV (ADD)
* WST (NOP)
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// Input signals
input [0:127] reg_A;
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
input [0:4] alu_op;
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
// Declare "reg" signals:
reg [0:127] result;
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
integer sgn;
integer i;
integer j;
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ==============================================================
// PRM instruction
`aluwprm:
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__AND4B_BEHAVIORAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__INV_1_V
`define SKY130_FD_SC_HVL__INV_1_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__inv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__INV_1_V
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2014, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//
//-------------------------------------------------------------------
//
// Filename : intra_ctrl.v
// Author : Liu Cong
// Created : 2014-4
//
//-------------------------------------------------------------------
//
// Modified : 2014-07-17 by HLL
// Description : lcu size changed into 64x64 (prediction to 64x64 block remains to be added)
// Modified : 2014-08-23 by HLL
// Description : optional mode for minimal tu size added
// Modified : 2014-08-25 by HLL
// Description : prediction to u added
// Modified : 2014-08-26 by HLL
// Description : prediction to v added
// Modified : 2014-09-10 by HLL
// Description : sel_o modified
// Modified : 2014-09-15 by HLL
// Description : partition supported
// Modified : 2014-10-17 by HLL
// Description : mode_uv supported
// Modified : 2014-10-19 by HLL
// Description : mode_uv fetched from cur_mb
//
// $Id$
//
//-------------------------------------------------------------------
`include "./enc_defines.v"
module intra_ctrl(
clk ,
rst_n ,
// sys if
start_i ,
done_o ,
// pre ctrl if
pre_min_size_i ,
uv_partition_i ,
// mode ram if
md_cena_o ,
md_addr_o ,
md_data_i ,
// intra ref if
ref_start_o ,
ref_done_i ,
ref_ready_i ,
ref_size_o ,
ref_mode_o ,
ref_sel_o ,
ref_position_o ,
// intra pred if
pre_start_o ,
pre_mode_o ,
pre_sel_o ,
pre_size_o ,
pre_i4x4_x_o ,
pre_i4x4_y_o
);
//*** PARAMETER DECLARATION ****************************************************
localparam PIDLE = 'd00 ,
PRE04 = 'd01 ,
PRE08 = 'd02 ,
PRE16 = 'd03 ,
PRE32 = 'd04 ,
PRE08_U = 'd05 ,
PRE08_V = 'd06 ,
PRE16_U = 'd07 ,
PRE16_V = 'd08 ,
PRE32_U = 'd09 ,
PRE32_V = 'd10 ;
//*** INPUT/OUTPUT DECLARATION *************************************************
input clk ;
input rst_n ;
// sys if
input start_i ;
output reg done_o ;
// pre ctrl if
input pre_min_size_i ;
input [20 : 0] uv_partition_i ;
// mode ram if
output reg md_cena_o ;
output reg [9 : 0] md_addr_o ;
input [5 : 0] md_data_i ;
// intra ref if
output reg ref_start_o ;
input ref_done_i ;
input ref_ready_i ;
output reg [1 : 0] ref_size_o ;
output reg [5 : 0] ref_mode_o ;
output reg [1 : 0] ref_sel_o ;
output reg [7 : 0] ref_position_o ;
// intra pred if
output reg pre_start_o ;
output [5 : 0] pre_mode_o ;
output [1 : 0] pre_sel_o ;
output [1 : 0] pre_size_o ;
output reg [3 : 0] pre_i4x4_x_o ;
output reg [3 : 0] pre_i4x4_y_o ;
//************************ REG/WIRE DECLARATION **************************
reg [5 : 0] pre_cnt_r ;
reg mode_valid_r ;
reg [3 : 0] state ;
reg [3 : 0] next_state ;
wire [7 : 0] pre_position ;
reg [1 : 0] next_size_r ;
wire partition_64_w ;
wire [3 : 0] partition_32_w ;
wire [15 : 0] partition_16_w ;
wire is_32_split_w ;
wire is_16_split_w ;
reg [7 : 0] next_uv_position_w ;
//*** MAIN BODY ****************************************************************
//--- State Machine --------------------
// state machine : state
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
state <= PIDLE;
else begin
state <= next_state ;
end
end
// state machine : next_state
always @(*) begin
next_state = PIDLE;
case( state )
PIDLE: begin if( start_i ) begin
if( pre_min_size_i==1'b0 ) next_state = PRE04 ;
else next_state = PRE08 ;
end
else next_state = PIDLE ;
end
PRE04: begin if( ref_done_i ) begin
if( ref_position_o[1:0]==2'b11 ) next_state = PRE08 ;
else next_state = PRE04 ;
end
else next_state = PRE04 ;
end
PRE08: begin if( ref_done_i ) begin
if( ref_position_o[3:0]==4'b1100 ) next_state = PRE16 ;
else begin
if( pre_min_size_i==1'b0 ) next_state = PRE04 ;
else next_state = PRE08 ;
end
end
else next_state = PRE08 ;
end
PRE16: begin if( ref_done_i ) begin
if( ref_position_o[5:0]==6'b110000 ) next_state = PRE32 ;
else begin
if( pre_min_size_i == 1'b0 ) next_state = PRE04 ;
else next_state = PRE08 ;
end
end
else next_state = PRE16 ;
end
PRE32: begin if( ref_done_i ) begin
if( ref_position_o[7:0]==8'b11000000 ) begin
case( next_size_r )
2'b01 : next_state = PRE08_U ;
2'b10 : next_state = PRE16_U ;
2'b11 : next_state = PRE32_U ;
default : next_state = PIDLE ;
endcase
end
else begin
if( pre_min_size_i==1'b0 ) next_state = PRE04 ;
else next_state = PRE08 ;
end
end
else next_state = PRE32 ;
end
PRE08_U: begin if( ref_done_i ) next_state = PRE08_V ;
else begin next_state = PRE08_U ;
end
end
PRE08_V: begin if( ref_done_i ) begin
if( ref_position_o[7:0]==8'b11111100 ) next_state = PIDLE ;
else begin
case( next_size_r )
2'b01 : next_state = PRE08_U ;
2'b10 : next_state = PRE16_U ;
2'b11 : next_state = PRE32_U ;
default : next_state = PIDLE ;
endcase
end
end
else next_state = PRE08_V ;
end
PRE16_U: begin if( ref_done_i ) next_state = PRE16_V ;
else begin next_state = PRE16_U ;
end
end
PRE16_V: begin if( ref_done_i ) begin
if( ref_position_o[7:0]==8'b11110000 ) next_state = PIDLE ;
else begin
case( next_size_r )
2'b01 : next_state = PRE08_U ;
2'b10 : next_state = PRE16_U ;
2'b11 : next_state = PRE32_U ;
default : next_state = PIDLE ;
endcase
end
end
else next_state = PRE16_V ;
end
PRE32_U: begin if( ref_done_i ) next_state = PRE32_V ;
else begin next_state = PRE32_U ;
end
end
PRE32_V: begin if( ref_done_i ) begin
if( ref_position_o[7:0]==8'b11000000 ) next_state = PIDLE ;
else begin
case( next_size_r )
2'b01 : next_state = PRE08_U ;
2'b10 : next_state = PRE16_U ;
2'b11 : next_state = PRE32_U ;
default : next_state = PIDLE ;
endcase
end
end
else next_state = PRE32_V ;
end
endcase
end
//--- Partition Part -------------------
// next_size_r
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
next_size_r <= 'd0 ;
else if( !is_32_split_w )
next_size_r <= 2'b11 ;
else if( !is_16_split_w )
next_size_r <= 2'b10 ;
else begin
next_size_r <= 2'b01 ;
end
end
// is_split_w
assign is_32_split_w = partition_32_w >> ( next_uv_position_w >> 6 ) ;
assign is_16_split_w = partition_16_w >> ( next_uv_position_w >> 4 ) ;
// partition_w
assign { partition_16_w, partition_32_w ,partition_64_w } = uv_partition_i ;
// next_uv_position_w
always @(*) begin
if( ref_sel_o==2'b00 )
next_uv_position_w = 'd0 ;
else begin
case( ref_size_o )
2'b00 : next_uv_position_w = ref_position_o + 'd04 ;
2'b01 : next_uv_position_w = ref_position_o + 'd16 ;
2'b10 : next_uv_position_w = ref_position_o + 'd64 ;
default : next_uv_position_w = 'dx ;
endcase
end
end
//--- System Part ----------------------
// done_o
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
done_o <= 'd0 ;
else if( done_o )
done_o <= 'd0 ;
else if( (ref_done_i) && ( ((state==PRE08_V)&&(ref_position_o[7:0]==8'b11111100)) ||
((state==PRE16_V)&&(ref_position_o[7:0]==8'b11110000)) ||
((state==PRE32_V)&&(ref_position_o[7:0]==8'b11000000)) ||
((state==PRE32 )&&(ref_position_o[7:0]==8'b11000000))&&(next_size_r==2'b00)
)
) begin
done_o <= 'd1 ;
end
end
//--- Mode Part ------------------------
// md_cena_o
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
md_cena_o <= 'd0;
else begin
if( md_cena_o ) begin
md_cena_o <= 'd0;
end
else begin
if( state==PIDLE ) begin
if( start_i ) begin
md_cena_o <= 'd1;
end
end
else begin
if( ref_done_i ) begin
case( state )
PRE08_U ,
PRE16_U ,
PRE32_U : md_cena_o <= 'd0 ;
default : md_cena_o <= 'd1 ;
endcase
end
end
end
end
end
// md_addr_o
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
md_addr_o <= 'd0;
else begin
if( state==PIDLE ) begin
if( start_i ) begin
md_addr_o <= 'd0;
end
end
else begin
if( ref_done_i ) begin
if( (ref_sel_o!=2'b00) || ((state==PRE32)&&(ref_position_o[7:0]==8'b11000000)) )
if( pre_min_size_i==1'b0 )
case( next_size_r )
2'b01 : md_addr_o <= next_uv_position_w[7:6] + next_uv_position_w[7:4] + next_uv_position_w[7:2]*5 + 4 ;
2'b10 : md_addr_o <= next_uv_position_w[7:6] + next_uv_position_w[7:4]*21 + 20;
2'b11 : md_addr_o <= next_uv_position_w[7:6]*85 + 84 ;
endcase
else begin
case( next_size_r )
2'b01 : md_addr_o <= next_uv_position_w[7:6] + next_uv_position_w[7:4] + next_uv_position_w[7:2] ;
2'b10 : md_addr_o <= next_uv_position_w[7:6] + next_uv_position_w[7:4]*5 + 4 ;
2'b11 : md_addr_o <= next_uv_position_w[7:6]*21 + 20;
endcase
end
else begin
md_addr_o <= md_addr_o + 'd1 ;
end
end
end
end
end
//--- Ref Part -------------------------
// ref_start_o
always @(posedge clk or negedge rst_n) begin
if( !rst_n ) begin
ref_start_o <= 'd0 ;
end
else begin
if( ref_start_o ) begin
ref_start_o <= 'd0 ;
end
else begin
if( state==PIDLE ) begin
if( start_i ) begin
ref_start_o <= 'd1 ;
end
end
else begin
if( ref_done_i && ( ! ((state==PRE08_V)&&(ref_position_o[7:0]==8'b11111100)) )
&& ( ! ((state==PRE16_V)&&(ref_position_o[7:0]==8'b11110000)) )
&& ( ! ((state==PRE32_V)&&(ref_position_o[7:0]==8'b11000000)) )
&& ( ! ((state==PRE32 )&&(ref_position_o[7:0]==8'b11000000)&&(next_size_r==2'b00)) )
) begin
ref_start_o <= 'd1 ;
end
end
end
end
end
// ref_size_o
always @(posedge clk or negedge rst_n) begin
if( !rst_n ) begin
ref_size_o <= 2'b00 ;
end
else begin
case( next_state )
PRE04 ,PRE08_U ,PRE08_V : ref_size_o <= 2'b00 ;
PRE08 ,PRE16_U ,PRE16_V : ref_size_o <= 2'b01 ;
PRE16 ,PRE32_U ,PRE32_V : ref_size_o <= 2'b10 ;
PRE32 : ref_size_o <= 2'b11 ;
endcase
end
end
//******************************************************************************
/* FOR DEBUG
// ref_size_r
reg [1:0] ref_size_r ;
wire ref_size_d ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
ref_size_r <= 2'b00 ;
end
else begin
case( state )
PIDLE: begin if( start_i ) begin
if( pre_min_size_i==1'b0 ) ref_size_r <= 2'b00 ;
else ref_size_r <= 2'b01 ;
end
end
PRE04: begin if( ref_done_i )
if( ref_position_o[1:0]==2'b11 ) ref_size_r <= 2'b01 ;
else ref_size_r <= 2'b00 ;
end
PRE08: begin if( ref_done_i ) begin
if( ref_position_o[3:0]==4'b1100 ) ref_size_r <= 2'b10 ;
else begin
if( pre_min_size_i==1'b0 ) ref_size_r <= 2'b00 ;
else ref_size_r <= 2'b01 ;
end
end
end
PRE16: begin if( ref_done_i ) begin
if( ref_position_o[5:0]==6'b110000 ) ref_size_r <= 2'b11 ;
else begin
if( pre_min_size_i==1'b0 ) ref_size_r <= 2'b00 ;
else ref_size_r <= 2'b01 ;
end
end
end
PRE32: begin if( ref_done_i ) begin
if( pre_min_size_i==1'b0 ) ref_size_r <= 2'b00 ;
else ref_size_r <= 2'b01 ;
end
end
endcase
end
end
assign ref_size_d = ref_size_r != ref_size_o ;
*/
//******************************************************************************
// ref_mode_o : mode_valid_r
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
mode_valid_r <= 'd0 ;
else begin
mode_valid_r <= md_cena_o ;
end
end
// ref_mode_o : ref_mode_o
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
ref_mode_o <= 'd0 ;
else begin
if( mode_valid_r ) begin
ref_mode_o <= md_data_i ;
end
end
end
// ref_sel_o
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
ref_sel_o <= 'd0 ;
else begin
case( next_state )
PRE04 ,PRE08 ,PRE16 ,PRE32 : ref_sel_o <= 2'b00 ;
PRE08_U,PRE16_U,PRE32_U : ref_sel_o <= 2'b10 ;
PRE08_V,PRE16_V,PRE32_V : ref_sel_o <= 2'b11 ;
default : ref_sel_o <= 2'b00 ;
endcase
end
end
// ref_position_o
always @(posedge clk or negedge rst_n) begin
if( !rst_n )
ref_position_o <= 'd0 ;
else begin
if( ref_sel_o==2'b00 ) begin
case( state )
PIDLE : begin if( start_i ) ref_position_o <= 'd0 ;
end
PRE04 : begin if( ref_done_i ) begin
if( ref_position_o[1:0]==2'b11 ) ref_position_o <= ref_position_o - 'd03 ;
else ref_position_o <= ref_position_o + 'd01 ;
end
end
PRE08 : begin if( ref_done_i ) begin
if( ref_position_o[3:0]==4'b1100 ) ref_position_o <= ref_position_o - 'd12 ;
else ref_position_o <= ref_position_o + 'd04 ;
end
end
PRE16 : begin if( ref_done_i ) begin
if( ref_position_o[5:0]==6'b110000 ) ref_position_o <= ref_position_o - 'd48 ;
else ref_position_o <= ref_position_o + 'd16 ;
end
end
PRE32 : begin if( ref_done_i ) begin
if( ref_position_o[7:0]==8'b11000000 ) ref_position_o <= 'd0 ;
else ref_position_o <= ref_position_o + 'd64 ;
end
end
endcase
end
else begin
if( ref_done_i ) begin
case( state )
PRE08_V: begin if( ref_position_o[7:0]==8'b11111100 ) ref_position_o <= 'd0 ; // 252
else ref_position_o <= ref_position_o + 'd04 ;
end
PRE16_V: begin if( ref_position_o[7:0]==8'b11110000 ) ref_position_o <= 'd0 ; // 240
else ref_position_o <= ref_position_o + 'd16 ;
end
PRE32_V: begin if( ref_position_o[7:0]==8'b11000000 ) ref_position_o <= 'd0 ; // 192
else ref_position_o <= ref_position_o + 'd64 ;
end
endcase
end
end
end
end
//--- Pre Part -------------------------
// pre_start_o : pre_cnt_r
always @(posedge clk or negedge rst_n) begin
if( !rst_n ) begin
pre_cnt_r <= 'd0 ;
end
else begin
if( ref_ready_i ) begin
pre_cnt_r <= 'd0 ;
end
else begin
if( pre_start_o )
pre_cnt_r <= pre_cnt_r+1 ;
end
end
end
// pre_start_o : pre_start_o
always @(posedge clk or negedge rst_n) begin
if( !rst_n ) begin
pre_start_o <= 'd0 ;
end
else begin
if( ref_ready_i ) begin
pre_start_o <= 'd1 ;
end
else begin
case( state )
PRE04 ,PRE08_U ,PRE08_V: begin if( pre_start_o ) pre_start_o <= 'd0;
end
PRE08 ,PRE16_U ,PRE16_V: begin if( pre_cnt_r=='d3 ) pre_start_o <= 'd0;
end
PRE16 ,PRE32_U ,PRE32_V: begin if( pre_cnt_r=='d15 ) pre_start_o <= 'd0;
end
PRE32: begin if( pre_cnt_r=='d63 ) pre_start_o <= 'd0;
end
endcase
end
end
end
// pre_mode_o
assign pre_mode_o = ref_mode_o ;
// pre_sel_o
assign pre_sel_o = ref_sel_o ;
// pre_size_o
// assign pre_size_o = (ref_sel_o==2'b00) ? ref_size_o : (ref_size_o>>1) ;
assign pre_size_o = ref_size_o ;
// pre_i4x4_x_o, pre_i4x4_y_o : pre_position
assign pre_position = (ref_sel_o==2'b00) ? ref_position_o : (ref_position_o>>2) ;
// pre_i4x4_x_o, pre_i4x4_y_o : pre_i4x4_x_o, pre_i4x4_y_o
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
pre_i4x4_y_o <= 'd0;
pre_i4x4_x_o <= 'd0;
end
else begin
if(ref_ready_i) begin
pre_i4x4_y_o <= {pre_position[7], pre_position[5], pre_position[3], pre_position[1]};
pre_i4x4_x_o <= {pre_position[6], pre_position[4], pre_position[2], pre_position[0]};
end
else begin
if(pre_start_o) begin
case(pre_size_o)
2'b01: begin if(!pre_i4x4_x_o[0]) pre_i4x4_x_o <= pre_i4x4_x_o+1;
else begin pre_i4x4_x_o <= {pre_position[6], pre_position[4], pre_position[2], pre_position[0]};
pre_i4x4_y_o <= pre_i4x4_y_o+1;
end
end
2'b10: begin if(pre_i4x4_x_o[1:0]!=2'b11) pre_i4x4_x_o <= pre_i4x4_x_o+1;
else begin pre_i4x4_x_o <= {pre_position[6], pre_position[4], pre_position[2], pre_position[0]};
pre_i4x4_y_o <= pre_i4x4_y_o+1;
end
end
2'b11: begin if(pre_i4x4_x_o[2:0]!=3'b111) pre_i4x4_x_o <= pre_i4x4_x_o+1;
else begin pre_i4x4_x_o <= {pre_position[6], pre_position[4], pre_position[2], pre_position[0]};
pre_i4x4_y_o <= pre_i4x4_y_o+1;
end
end
endcase
end
end
end
end
endmodule
|
module membus_1_connect(
// unused
input wire clk,
input wire reset,
// Master
input wire m_wr_rs,
input wire m_rq_cyc,
input wire m_rd_rq,
input wire m_wr_rq,
input wire [21:35] m_ma,
input wire [18:21] m_sel,
input wire m_fmc_select,
input wire [0:35] m_mb_write,
output wire m_addr_ack,
output wire m_rd_rs,
output wire [0:35] m_mb_read,
// Slave 0
output wire s0_wr_rs,
output wire s0_rq_cyc,
output wire s0_rd_rq,
output wire s0_wr_rq,
output wire [21:35] s0_ma,
output wire [18:21] s0_sel,
output wire s0_fmc_select,
output wire [0:35] s0_mb_write,
input wire s0_addr_ack,
input wire s0_rd_rs,
input wire [0:35] s0_mb_read
);
wire [0:35] mb_out = m_mb_write | s0_mb_read;
assign m_addr_ack = s0_addr_ack;
assign m_rd_rs = s0_rd_rs;
assign m_mb_read = mb_out;
assign s0_wr_rs = m_wr_rs;
assign s0_rq_cyc = m_rq_cyc;
assign s0_rd_rq = m_rd_rq;
assign s0_wr_rq = m_wr_rq;
assign s0_ma = m_ma;
assign s0_sel = m_sel;
assign s0_fmc_select = m_fmc_select;
assign s0_mb_write = mb_out;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
parameter CHANGE_START = 1'b0;
parameter CHANGE_CHECK = 1'b1;
reg r_change;
reg [width-1:0] r_test_expr;
reg r_state;
integer i;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=CHANGE_START;
r_change=1'b0;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
CHANGE_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (start_event == 1'b1) begin
r_change <= 1'b0;
r_state <= CHANGE_CHECK;
r_test_expr <= test_expr;
i <= num_cks;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
end
CHANGE_CHECK: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// Count clock ticks
if (start_event == 1'b1) begin
if (action_on_new_start == `OVL_IGNORE_NEW_START && i > 0)
i <= i-1;
else if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
r_change <= 1'b0;
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
ovl_cover_t("window_resets covered");
end
end
end
`endif // OVL_COVER_ON
end
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
i <= i-1;
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Start event evaluated TRUE before test expression changed");
`endif // OVL_ASSERT_ON
end
end
else if (i > 0)
i <= i-1;
if (r_test_expr != test_expr && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
r_change <= 1'b1;
end
// go to start state on last check
if (i == 1 && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
r_state <= CHANGE_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_close covered");
end
end
`endif // OVL_COVER_ON
// Check that the property is true
`ifdef OVL_ASSERT_ON
if ((r_change != 1'b1) && (r_test_expr == test_expr)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression did not change value within num_cks cycles after start event");
end
`endif // OVL_ASSERT_ON
end
r_test_expr <= test_expr;
end
endcase
end
else begin
r_state <= CHANGE_START;
r_change <= 1'b0;
i <= 0;
`ifdef OVL_INIT_REG
r_test_expr <= {width{1'b0}};
`endif
end
end // always
`endif // OVL_SHARED_CODE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:02:11 05/12/2016
// Design Name:
// Module Name: fifo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module fifo
#(
parameter B=8, // number of bits in a word
W=2 // number of address bits
)
(
input wire clk, reset,
input wire rd, wr,
input wire [B-1:0] w_data,
output wire empty, full,
output wire [B-1:0] r_data
);
//signal declaration
reg [B-1:0] array_reg [2**W-1:0]; // register array
reg [W-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
reg [W-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
// body
// register file write operation
always @(posedge clk)
if (wr_en)
array_reg[w_ptr_reg] <= w_data;
// register file read operation
assign r_data = array_reg[r_ptr_reg];
// write enabled only when FIFO is not full
assign wr_en = wr & ~full_reg;
// fifo control logic
// register for read and write pointers
always @(posedge clk, posedge reset)
if (reset)
begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end
else
begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
// next-state logic for read and write pointers
always @*
begin
// successive pointer values
w_ptr_succ = w_ptr_reg + 1'b1;
r_ptr_succ = r_ptr_reg + 1'b1;
// default: keep old values
w_ptr_next = w_ptr_reg;
r_ptr_next = r_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({wr, rd})
// 2'b00: no op
2'b01: // read
if (~empty_reg) // not empty
begin
r_ptr_next = r_ptr_succ;
full_next = 1'b0;
if (r_ptr_succ==w_ptr_reg)
empty_next = 1'b1;
end
2'b10: // write
if (~full_reg) // not full
begin
w_ptr_next = w_ptr_succ;
empty_next = 1'b0;
if (w_ptr_succ==r_ptr_reg)
full_next = 1'b1;
end
2'b11: // write and read
begin
w_ptr_next = w_ptr_succ;
r_ptr_next = r_ptr_succ;
end
endcase
end
// output
assign full = full_reg;
assign empty = empty_reg;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_bottom_rptr2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ctu_bottom_rptr2(/*AUTOARG*/
// Outputs
l2_dbgbus_out, enable_01, so,
// Inputs
dbgbus_b0, dbgbus_b1, rclk, si, se
);
output [39:0] l2_dbgbus_out ;
output enable_01;
input [40:0] dbgbus_b0;
input [40:0] dbgbus_b1;
input rclk;
input si, se;
output so;
wire [39:0] l2_dbgbus_out_prev ;
wire enable_01_prev;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
// Row0
mux2ds #(20) mux_dbgmuxb01_row0 (.dout (l2_dbgbus_out_prev[19:0]),
.in0(dbgbus_b0[19:0]),
.in1(dbgbus_b1[19:0]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row0 (.q(l2_dbgbus_out[19:0]),
.din(l2_dbgbus_out_prev[19:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
// Row1
mux2ds #(20) mux_dbgmuxb01_row1 (.dout (l2_dbgbus_out_prev[39:20]),
.in0(dbgbus_b0[39:20]),
.in1(dbgbus_b1[39:20]),
.sel0(dbgbus_b0[40]),
.sel1(~dbgbus_b0[40]));
dff_s #(20) ff_dbgmuxb01_row1 (.q(l2_dbgbus_out[39:20]),
.din(l2_dbgbus_out_prev[39:20]),
.clk(rclk), .se(1'b0), .si(), .so() );
assign enable_01_prev = dbgbus_b0[40] | dbgbus_b1[40] ;
dff_s #(1) ff_valid (.q(enable_01),
.din(enable_01_prev),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Setoid.
Require Import PeanoNat Le Gt Minus Bool Lt.
Set Implicit Arguments.
(* Set Universe Polymorphism. *)
(******************************************************************)
(** * Basics: definition of polymorphic lists and some operations *)
(******************************************************************)
(** The definition of [list] is now in [Init/Datatypes],
as well as the definitions of [length] and [app] *)
Open Scope list_scope.
(** Standard notations for lists.
In a special module to avoid conflicts. *)
Module ListNotations.
Notation "[ ]" := nil (format "[ ]") : list_scope.
Notation "[ x ]" := (cons x nil) : list_scope.
Notation "[ x ; y ; .. ; z ]" := (cons x (cons y .. (cons z nil) ..)) : list_scope.
End ListNotations.
Import ListNotations.
Section Lists.
Variable A : Type.
(** Head and tail *)
Definition hd (default:A) (l:list A) :=
match l with
| [] => default
| x :: _ => x
end.
Definition hd_error (l:list A) :=
match l with
| [] => None
| x :: _ => Some x
end.
Definition tl (l:list A) :=
match l with
| [] => nil
| a :: m => m
end.
(** The [In] predicate *)
Fixpoint In (a:A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end.
End Lists.
Section Facts.
Variable A : Type.
(** *** Generic facts *)
(** Discrimination *)
Theorem nil_cons : forall (x:A) (l:list A), [] <> x :: l.
Proof.
intros; discriminate.
Qed.
(** Destruction *)
Theorem destruct_list : forall l : list A, {x:A & {tl:list A | l = x::tl}}+{l = []}.
Proof.
induction l as [|a tail].
right; reflexivity.
left; exists a, tail; reflexivity.
Qed.
Lemma hd_error_tl_repr : forall l (a:A) r,
hd_error l = Some a /\ tl l = r <-> l = a :: r.
Proof. destruct l as [|x xs].
- unfold hd_error, tl; intros a r. split; firstorder discriminate.
- intros. simpl. split.
* intros (H1, H2). inversion H1. rewrite H2. reflexivity.
* inversion 1. subst. auto.
Qed.
Lemma hd_error_some_nil : forall l (a:A), hd_error l = Some a -> l <> nil.
Proof. unfold hd_error. destruct l; now discriminate. Qed.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l=[].
Proof.
split; [now destruct l | now intros ->].
Qed.
(** *** Head and tail *)
Theorem hd_error_nil : hd_error (@nil A) = None.
Proof.
simpl; reflexivity.
Qed.
Theorem hd_error_cons : forall (l : list A) (x : A), hd_error (x::l) = Some x.
Proof.
intros; simpl; reflexivity.
Qed.
(************************)
(** *** Facts about [In] *)
(************************)
(** Characterization of [In] *)
Theorem in_eq : forall (a:A) (l:list A), In a (a :: l).
Proof.
simpl; auto.
Qed.
Theorem in_cons : forall (a b:A) (l:list A), In b l -> In b (a :: l).
Proof.
simpl; auto.
Qed.
Theorem not_in_cons (x a : A) (l : list A):
~ In x (a::l) <-> x<>a /\ ~ In x l.
Proof.
simpl. intuition.
Qed.
Theorem in_nil : forall a:A, ~ In a [].
Proof.
unfold not; intros a H; inversion_clear H.
Qed.
Theorem in_split : forall x (l:list A), In x l -> exists l1 l2, l = l1++x::l2.
Proof.
induction l; simpl; destruct 1.
subst a; auto.
exists [], l; auto.
destruct (IHl H) as (l1,(l2,H0)).
exists (a::l1), l2; simpl. apply f_equal. auto.
Qed.
(** Inversion *)
Lemma in_inv : forall (a b:A) (l:list A), In b (a :: l) -> a = b \/ In b l.
Proof.
intros a b l H; inversion_clear H; auto.
Qed.
(** Decidability of [In] *)
Theorem in_dec :
(forall x y:A, {x = y} + {x <> y}) ->
forall (a:A) (l:list A), {In a l} + {~ In a l}.
Proof.
intro H; induction l as [| a0 l IHl].
right; apply in_nil.
destruct (H a0 a); simpl; auto.
destruct IHl; simpl; auto.
right; unfold not; intros [Hc1| Hc2]; auto.
Defined.
(**************************)
(** *** Facts about [app] *)
(**************************)
(** Discrimination *)
Theorem app_cons_not_nil : forall (x y:list A) (a:A), [] <> x ++ a :: y.
Proof.
unfold not.
destruct x as [| a l]; simpl; intros.
discriminate H.
discriminate H.
Qed.
(** Concat with [nil] *)
Theorem app_nil_l : forall l:list A, [] ++ l = l.
Proof.
reflexivity.
Qed.
Theorem app_nil_r : forall l:list A, l ++ [] = l.
Proof.
induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_nil_end : forall (l:list A), l = l ++ [].
Proof. symmetry; apply app_nil_r. Qed.
(* end hide *)
(** [app] is associative *)
Theorem app_assoc : forall l m n:list A, l ++ m ++ n = (l ++ m) ++ n.
Proof.
intros l m n; induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_assoc_reverse : forall l m n:list A, (l ++ m) ++ n = l ++ m ++ n.
Proof.
auto using app_assoc.
Qed.
Hint Resolve app_assoc_reverse.
(* end hide *)
(** [app] commutes with [cons] *)
Theorem app_comm_cons : forall (x y:list A) (a:A), a :: (x ++ y) = (a :: x) ++ y.
Proof.
auto.
Qed.
(** Facts deduced from the result of a concatenation *)
Theorem app_eq_nil : forall l l':list A, l ++ l' = [] -> l = [] /\ l' = [].
Proof.
destruct l as [| x l]; destruct l' as [| y l']; simpl; auto.
intro; discriminate.
intros H; discriminate H.
Qed.
Theorem app_eq_unit :
forall (x y:list A) (a:A),
x ++ y = [a] -> x = [] /\ y = [a] \/ x = [a] /\ y = [].
Proof.
destruct x as [| a l]; [ destruct y as [| a l] | destruct y as [| a0 l0] ];
simpl.
intros a H; discriminate H.
left; split; auto.
right; split; auto.
generalize H.
generalize (app_nil_r l); intros E.
rewrite -> E; auto.
intros.
injection H as H H0.
assert ([] = l ++ a0 :: l0) by auto.
apply app_cons_not_nil in H1 as [].
Qed.
Lemma app_inj_tail :
forall (x y:list A) (a b:A), x ++ [a] = y ++ [b] -> x = y /\ a = b.
Proof.
induction x as [| x l IHl];
[ destruct y as [| a l] | destruct y as [| a l0] ];
simpl; auto.
- intros a b H.
injection H.
auto.
- intros a0 b H.
injection H as H1 H0.
apply app_cons_not_nil in H0 as [].
- intros a b H.
injection H as H1 H0.
assert ([] = l ++ [a]) by auto.
apply app_cons_not_nil in H as [].
- intros a0 b H.
injection H as <- H0.
destruct (IHl l0 a0 b H0) as (<-,<-).
split; auto.
Qed.
(** Compatibility with other operations *)
Lemma app_length : forall l l' : list A, length (l++l') = length l + length l'.
Proof.
induction l; simpl; auto.
Qed.
Lemma in_app_or : forall (l m:list A) (a:A), In a (l ++ m) -> In a l \/ In a m.
Proof.
intros l m a.
elim l; simpl; auto.
intros a0 y H H0.
now_show ((a0 = a \/ In a y) \/ In a m).
elim H0; auto.
intro H1.
now_show ((a0 = a \/ In a y) \/ In a m).
elim (H H1); auto.
Qed.
Lemma in_or_app : forall (l m:list A) (a:A), In a l \/ In a m -> In a (l ++ m).
Proof.
intros l m a.
elim l; simpl; intro H.
now_show (In a m).
elim H; auto; intro H0.
now_show (In a m).
elim H0. (* subProof completed *)
intros y H0 H1.
now_show (H = a \/ In a (y ++ m)).
elim H1; auto 4.
intro H2.
now_show (H = a \/ In a (y ++ m)).
elim H2; auto.
Qed.
Lemma in_app_iff : forall l l' (a:A), In a (l++l') <-> In a l \/ In a l'.
Proof.
split; auto using in_app_or, in_or_app.
Qed.
Lemma app_inv_head:
forall l l1 l2 : list A, l ++ l1 = l ++ l2 -> l1 = l2.
Proof.
induction l; simpl; auto; injection 1; auto.
Qed.
Lemma app_inv_tail:
forall l l1 l2 : list A, l1 ++ l = l2 ++ l -> l1 = l2.
Proof.
intros l l1 l2; revert l1 l2 l.
induction l1 as [ | x1 l1]; destruct l2 as [ | x2 l2];
simpl; auto; intros l H.
absurd (length (x2 :: l2 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite <- H; auto with arith.
absurd (length (x1 :: l1 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite H; auto with arith.
injection H as H H0; f_equal; eauto.
Qed.
End Facts.
Hint Resolve app_assoc app_assoc_reverse: datatypes.
Hint Resolve app_comm_cons app_cons_not_nil: datatypes.
Hint Immediate app_eq_nil: datatypes.
Hint Resolve app_eq_unit app_inj_tail: datatypes.
Hint Resolve in_eq in_cons in_inv in_nil in_app_or in_or_app: datatypes.
(*******************************************)
(** * Operations on the elements of a list *)
(*******************************************)
Section Elts.
Variable A : Type.
(*****************************)
(** ** Nth element of a list *)
(*****************************)
Fixpoint nth (n:nat) (l:list A) (default:A) {struct l} : A :=
match n, l with
| O, x :: l' => x
| O, other => default
| S m, [] => default
| S m, x :: t => nth m t default
end.
Fixpoint nth_ok (n:nat) (l:list A) (default:A) {struct l} : bool :=
match n, l with
| O, x :: l' => true
| O, other => false
| S m, [] => false
| S m, x :: t => nth_ok m t default
end.
Lemma nth_in_or_default :
forall (n:nat) (l:list A) (d:A), {In (nth n l d) l} + {nth n l d = d}.
Proof.
intros n l d; revert n; induction l.
- right; destruct n; trivial.
- intros [|n]; simpl.
* left; auto.
* destruct (IHl n); auto.
Qed.
Lemma nth_S_cons :
forall (n:nat) (l:list A) (d a:A),
In (nth n l d) l -> In (nth (S n) (a :: l) d) (a :: l).
Proof.
simpl; auto.
Qed.
Fixpoint nth_error (l:list A) (n:nat) {struct n} : option A :=
match n, l with
| O, x :: _ => Some x
| S n, _ :: l => nth_error l n
| _, _ => None
end.
Definition nth_default (default:A) (l:list A) (n:nat) : A :=
match nth_error l n with
| Some x => x
| None => default
end.
Lemma nth_default_eq :
forall n l (d:A), nth_default d l n = nth n l d.
Proof.
unfold nth_default; induction n; intros [ | ] ?; simpl; auto.
Qed.
(** Results about [nth] *)
Lemma nth_In :
forall (n:nat) (l:list A) (d:A), n < length l -> In (nth n l d) l.
Proof.
unfold lt; induction n as [| n hn]; simpl.
- destruct l; simpl; [ inversion 2 | auto ].
- destruct l; simpl.
* inversion 2.
* intros d ie; right; apply hn; auto with arith.
Qed.
Lemma In_nth l x d : In x l ->
exists n, n < length l /\ nth n l d = x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n & Hn & Hn').
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_overflow : forall l n d, length l <= n -> nth n l d = d.
Proof.
induction l; destruct n; simpl; intros; auto.
- inversion H.
- apply IHl; auto with arith.
Qed.
Lemma nth_indep :
forall l n d d', n < length l -> nth n l d = nth n l d'.
Proof.
induction l.
- inversion 1.
- intros [|n] d d'; simpl; auto with arith.
Qed.
Lemma app_nth1 :
forall l l' d n, n < length l -> nth n (l++l') d = nth n l d.
Proof.
induction l.
- inversion 1.
- intros l' d [|n]; simpl; auto with arith.
Qed.
Lemma app_nth2 :
forall l l' d n, n >= length l -> nth n (l++l') d = nth (n-length l) l' d.
Proof.
induction l; intros l' d [|n]; auto.
- inversion 1.
- intros; simpl; rewrite IHl; auto with arith.
Qed.
Lemma nth_split n l d : n < length l ->
exists l1, exists l2, l = l1 ++ nth n l d :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|a l] H; try easy.
- exists nil; exists l; now simpl.
- destruct (IH l) as (l1 & l2 & Hl & Hl1); auto with arith.
exists (a::l1); exists l2; simpl; split; now f_equal.
Qed.
(** Results about [nth_error] *)
Lemma nth_error_In l n x : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
Lemma In_nth_error l x : In x l -> exists n, nth_error l n = Some x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n,Hn).
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_error_None l n : nth_error l n = None <-> length l <= n.
Proof.
revert n. induction l; destruct n; simpl.
- split; auto.
- split; auto with arith.
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_Some l n : nth_error l n <> None <-> n < length l.
Proof.
revert n. induction l; destruct n; simpl.
- split; [now destruct 1 | inversion 1].
- split; [now destruct 1 | inversion 1].
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_split l n a : nth_error l n = Some a ->
exists l1, exists l2, l = l1 ++ a :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|x l] H; simpl in *; try easy.
- exists nil; exists l. now injection H as ->.
- destruct (IH _ H) as (l1 & l2 & H1 & H2).
exists (x::l1); exists l2; simpl; split; now f_equal.
Qed.
Lemma nth_error_app1 l l' n : n < length l ->
nth_error (l++l') n = nth_error l n.
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
Lemma nth_error_app2 l l' n : length l <= n ->
nth_error (l++l') n = nth_error l' (n-length l).
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
(*****************)
(** ** Remove *)
(*****************)
Hypothesis eq_dec : forall x y : A, {x = y}+{x <> y}.
Fixpoint remove (x : A) (l : list A) : list A :=
match l with
| [] => []
| y::tl => if (eq_dec x y) then remove x tl else y::(remove x tl)
end.
Theorem remove_In : forall (l : list A) (x : A), ~ In x (remove x l).
Proof.
induction l as [|x l]; auto.
intro y; simpl; destruct (eq_dec y x) as [yeqx | yneqx].
apply IHl.
unfold not; intro HF; simpl in HF; destruct HF; auto.
apply (IHl y); assumption.
Qed.
(******************************)
(** ** Last element of a list *)
(******************************)
(** [last l d] returns the last element of the list [l],
or the default value [d] if [l] is empty. *)
Fixpoint last (l:list A) (d:A) : A :=
match l with
| [] => d
| [a] => a
| a :: l => last l d
end.
(** [removelast l] remove the last element of [l] *)
Fixpoint removelast (l:list A) : list A :=
match l with
| [] => []
| [a] => []
| a :: l => a :: removelast l
end.
Lemma app_removelast_last :
forall l d, l <> [] -> l = removelast l ++ [last l d].
Proof.
induction l.
destruct 1; auto.
intros d _.
destruct l; auto.
pattern (a0::l) at 1; rewrite IHl with d; auto; discriminate.
Qed.
Lemma exists_last :
forall l, l <> [] -> { l' : (list A) & { a : A | l = l' ++ [a]}}.
Proof.
induction l.
destruct 1; auto.
intros _.
destruct l.
exists [], a; auto.
destruct IHl as [l' (a',H)]; try discriminate.
rewrite H.
exists (a::l'), a'; auto.
Qed.
Lemma removelast_app :
forall l l', l' <> [] -> removelast (l++l') = l ++ removelast l'.
Proof.
induction l.
simpl; auto.
simpl; intros.
assert (l++l' <> []).
destruct l.
simpl; auto.
simpl; discriminate.
specialize (IHl l' H).
destruct (l++l'); [elim H0; auto|f_equal; auto].
Qed.
(******************************************)
(** ** Counting occurrences of an element *)
(******************************************)
Fixpoint count_occ (l : list A) (x : A) : nat :=
match l with
| [] => 0
| y :: tl =>
let n := count_occ tl x in
if eq_dec y x then S n else n
end.
(** Compatibility of count_occ with operations on list *)
Theorem count_occ_In l x : In x l <-> count_occ l x > 0.
Proof.
induction l as [|y l]; simpl.
- split; [destruct 1 | apply gt_irrefl].
- destruct eq_dec as [->|Hneq]; rewrite IHl; intuition.
Qed.
Theorem count_occ_not_In l x : ~ In x l <-> count_occ l x = 0.
Proof.
rewrite count_occ_In. unfold gt. now rewrite Nat.nlt_ge, Nat.le_0_r.
Qed.
Lemma count_occ_nil x : count_occ [] x = 0.
Proof.
reflexivity.
Qed.
Theorem count_occ_inv_nil l :
(forall x:A, count_occ l x = 0) <-> l = [].
Proof.
split.
- induction l as [|x l]; trivial.
intros H. specialize (H x). simpl in H.
destruct eq_dec as [_|NEQ]; [discriminate|now elim NEQ].
- now intros ->.
Qed.
Lemma count_occ_cons_eq l x y :
x = y -> count_occ (x::l) y = S (count_occ l y).
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
Lemma count_occ_cons_neq l x y :
x <> y -> count_occ (x::l) y = count_occ l y.
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
End Elts.
(*******************************)
(** * Manipulating whole lists *)
(*******************************)
Section ListOps.
Variable A : Type.
(*************************)
(** ** Reverse *)
(*************************)
Fixpoint rev (l:list A) : list A :=
match l with
| [] => []
| x :: l' => rev l' ++ [x]
end.
Lemma rev_app_distr : forall x y:list A, rev (x ++ y) = rev y ++ rev x.
Proof.
induction x as [| a l IHl].
destruct y as [| a l].
simpl.
auto.
simpl.
rewrite app_nil_r; auto.
intro y.
simpl.
rewrite (IHl y).
rewrite app_assoc; trivial.
Qed.
Remark rev_unit : forall (l:list A) (a:A), rev (l ++ [a]) = a :: rev l.
Proof.
intros.
apply (rev_app_distr l [a]); simpl; auto.
Qed.
Lemma rev_involutive : forall l:list A, rev (rev l) = l.
Proof.
induction l as [| a l IHl].
simpl; auto.
simpl.
rewrite (rev_unit (rev l) a).
rewrite IHl; auto.
Qed.
(** Compatibility with other operations *)
Lemma in_rev : forall l x, In x l <-> In x (rev l).
Proof.
induction l.
simpl; intuition.
intros.
simpl.
intuition.
subst.
apply in_or_app; right; simpl; auto.
apply in_or_app; left; firstorder.
destruct (in_app_or _ _ _ H); firstorder.
Qed.
Lemma rev_length : forall l, length (rev l) = length l.
Proof.
induction l;simpl; auto.
rewrite app_length.
rewrite IHl.
simpl.
elim (length l); simpl; auto.
Qed.
Lemma rev_nth : forall l d n, n < length l ->
nth n (rev l) d = nth (length l - S n) l d.
Proof.
induction l.
intros; inversion H.
intros.
simpl in H.
simpl (rev (a :: l)).
simpl (length (a :: l) - S n).
inversion H.
rewrite <- minus_n_n; simpl.
rewrite <- rev_length.
rewrite app_nth2; auto.
rewrite <- minus_n_n; auto.
rewrite app_nth1; auto.
rewrite (minus_plus_simpl_l_reverse (length l) n 1).
replace (1 + length l) with (S (length l)); auto with arith.
rewrite <- minus_Sn_m; auto with arith.
apply IHl ; auto with arith.
rewrite rev_length; auto.
Qed.
(** An alternative tail-recursive definition for reverse *)
Fixpoint rev_append (l l': list A) : list A :=
match l with
| [] => l'
| a::l => rev_append l (a::l')
end.
Definition rev' l : list A := rev_append l [].
Lemma rev_append_rev : forall l l', rev_append l l' = rev l ++ l'.
Proof.
induction l; simpl; auto; intros.
rewrite <- app_assoc; firstorder.
Qed.
Lemma rev_alt : forall l, rev l = rev_append l [].
Proof.
intros; rewrite rev_append_rev.
rewrite app_nil_r; trivial.
Qed.
(*********************************************)
(** Reverse Induction Principle on Lists *)
(*********************************************)
Section Reverse_Induction.
Lemma rev_list_ind :
forall P:list A-> Prop,
P [] ->
(forall (a:A) (l:list A), P (rev l) -> P (rev (a :: l))) ->
forall l:list A, P (rev l).
Proof.
induction l; auto.
Qed.
Theorem rev_ind :
forall P:list A -> Prop,
P [] ->
(forall (x:A) (l:list A), P l -> P (l ++ [x])) -> forall l:list A, P l.
Proof.
intros.
generalize (rev_involutive l).
intros E; rewrite <- E.
apply (rev_list_ind P).
auto.
simpl.
intros.
apply (H0 a (rev l0)).
auto.
Qed.
End Reverse_Induction.
(*************************)
(** ** Concatenation *)
(*************************)
Fixpoint concat (l : list (list A)) : list A :=
match l with
| nil => nil
| cons x l => x ++ concat l
end.
Lemma concat_nil : concat nil = nil.
Proof.
reflexivity.
Qed.
Lemma concat_cons : forall x l, concat (cons x l) = x ++ concat l.
Proof.
reflexivity.
Qed.
Lemma concat_app : forall l1 l2, concat (l1 ++ l2) = concat l1 ++ concat l2.
Proof.
intros l1; induction l1 as [|x l1 IH]; intros l2; simpl.
+ reflexivity.
+ rewrite IH; apply app_assoc.
Qed.
(***********************************)
(** ** Decidable equality on lists *)
(***********************************)
Hypothesis eq_dec : forall (x y : A), {x = y}+{x <> y}.
Lemma list_eq_dec : forall l l':list A, {l = l'} + {l <> l'}.
Proof. decide equality. Defined.
End ListOps.
(***************************************************)
(** * Applying functions to the elements of a list *)
(***************************************************)
(************)
(** ** Map *)
(************)
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Fixpoint map (l:list A) : list B :=
match l with
| [] => []
| a :: t => (f a) :: (map t)
end.
Lemma map_cons (x:A)(l:list A) : map (x::l) = (f x) :: (map l).
Proof.
reflexivity.
Qed.
Lemma in_map :
forall (l:list A) (x:A), In x l -> In (f x) (map l).
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma in_map_iff : forall l y, In y (map l) <-> exists x, f x = y /\ In x l.
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma map_length : forall l, length (map l) = length l.
Proof.
induction l; simpl; auto.
Qed.
Lemma map_nth : forall l d n,
nth n (map l) (f d) = f (nth n l d).
Proof.
induction l; simpl map; destruct n; firstorder.
Qed.
Lemma map_nth_error : forall n l d,
nth_error l n = Some d -> nth_error (map l) n = Some (f d).
Proof.
induction n; intros [ | ] ? Heq; simpl in *; inversion Heq; auto.
Qed.
Lemma map_app : forall l l',
map (l++l') = (map l)++(map l').
Proof.
induction l; simpl; auto.
intros; rewrite IHl; auto.
Qed.
Lemma map_rev : forall l, map (rev l) = rev (map l).
Proof.
induction l; simpl; auto.
rewrite map_app.
rewrite IHl; auto.
Qed.
Lemma map_eq_nil : forall l, map l = [] -> l = [].
Proof.
destruct l; simpl; reflexivity || discriminate.
Qed.
(** [map] and count of occurrences *)
Hypothesis decA: forall x1 x2 : A, {x1 = x2} + {x1 <> x2}.
Hypothesis decB: forall y1 y2 : B, {y1 = y2} + {y1 <> y2}.
Hypothesis Hfinjective: forall x1 x2: A, (f x1) = (f x2) -> x1 = x2.
Theorem count_occ_map x l:
count_occ decA l x = count_occ decB (map l) (f x).
Proof.
revert x. induction l as [| a l' Hrec]; intro x; simpl.
- reflexivity.
- specialize (Hrec x).
destruct (decA a x) as [H1|H1], (decB (f a) (f x)) as [H2|H2].
* rewrite Hrec. reflexivity.
* contradiction H2. rewrite H1. reflexivity.
* specialize (Hfinjective H2). contradiction H1.
* assumption.
Qed.
(** [flat_map] *)
Definition flat_map (f:A -> list B) :=
fix flat_map (l:list A) : list B :=
match l with
| nil => nil
| cons x t => (f x)++(flat_map t)
end.
Lemma in_flat_map : forall (f:A->list B)(l:list A)(y:B),
In y (flat_map f l) <-> exists x, In x l /\ In y (f x).
Proof using A B.
clear Hfinjective.
induction l; simpl; split; intros.
contradiction.
destruct H as (x,(H,_)); contradiction.
destruct (in_app_or _ _ _ H).
exists a; auto.
destruct (IHl y) as (H1,_); destruct (H1 H0) as (x,(H2,H3)).
exists x; auto.
apply in_or_app.
destruct H as (x,(H0,H1)); destruct H0.
subst; auto.
right; destruct (IHl y) as (_,H2); apply H2.
exists x; auto.
Qed.
End Map.
Lemma flat_map_concat_map : forall A B (f : A -> list B) l,
flat_map f l = concat (map f l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite IH; reflexivity.
Qed.
Lemma concat_map : forall A B (f : A -> B) l, map f (concat l) = concat (map (map f) l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite map_app, IH; reflexivity.
Qed.
Lemma map_id : forall (A :Type) (l : list A),
map (fun x => x) l = l.
Proof.
induction l; simpl; auto; rewrite IHl; auto.
Qed.
Lemma map_map : forall (A B C:Type)(f:A->B)(g:B->C) l,
map g (map f l) = map (fun x => g (f x)) l.
Proof.
induction l; simpl; auto.
rewrite IHl; auto.
Qed.
Lemma map_ext_in :
forall (A B : Type)(f g:A->B) l, (forall a, In a l -> f a = g a) -> map f l = map g l.
Proof.
induction l; simpl; auto.
intros; rewrite H by intuition; rewrite IHl; auto.
Qed.
Lemma map_ext :
forall (A B : Type)(f g:A->B), (forall a, f a = g a) -> forall l, map f l = map g l.
Proof.
intros; apply map_ext_in; auto.
Qed.
(************************************)
(** Left-to-right iterator on lists *)
(************************************)
Section Fold_Left_Recursor.
Variables (A : Type) (B : Type).
Variable f : A -> B -> A.
Fixpoint fold_left (l:list B) (a0:A) : A :=
match l with
| nil => a0
| cons b t => fold_left t (f a0 b)
end.
Lemma fold_left_app : forall (l l':list B)(i:A),
fold_left (l++l') i = fold_left l' (fold_left l i).
Proof.
induction l.
simpl; auto.
intros.
simpl.
auto.
Qed.
End Fold_Left_Recursor.
Lemma fold_left_length :
forall (A:Type)(l:list A), fold_left (fun x _ => S x) l 0 = length l.
Proof.
intros A l.
enough (H : forall n, fold_left (fun x _ => S x) l n = n + length l) by exact (H 0).
induction l; simpl; auto.
intros; rewrite IHl.
simpl; auto with arith.
Qed.
(************************************)
(** Right-to-left iterator on lists *)
(************************************)
Section Fold_Right_Recursor.
Variables (A : Type) (B : Type).
Variable f : B -> A -> A.
Variable a0 : A.
Fixpoint fold_right (l:list B) : A :=
match l with
| nil => a0
| cons b t => f b (fold_right t)
end.
End Fold_Right_Recursor.
Lemma fold_right_app : forall (A B:Type)(f:A->B->B) l l' i,
fold_right f i (l++l') = fold_right f (fold_right f i l') l.
Proof.
induction l.
simpl; auto.
simpl; intros.
f_equal; auto.
Qed.
Lemma fold_left_rev_right : forall (A B:Type)(f:A->B->B) l i,
fold_right f i (rev l) = fold_left (fun x y => f y x) l i.
Proof.
induction l.
simpl; auto.
intros.
simpl.
rewrite fold_right_app; simpl; auto.
Qed.
Theorem fold_symmetric :
forall (A : Type) (f : A -> A -> A),
(forall x y z : A, f x (f y z) = f (f x y) z) ->
forall (a0 : A), (forall y : A, f a0 y = f y a0) ->
forall (l : list A), fold_left f l a0 = fold_right f a0 l.
Proof.
intros A f assoc a0 comma0 l.
induction l as [ | a1 l ]; [ simpl; reflexivity | ].
simpl. rewrite <- IHl. clear IHl. revert a1. induction l; [ auto | ].
simpl. intro. rewrite <- assoc. rewrite IHl. rewrite IHl. auto.
Qed.
(** [(list_power x y)] is [y^x], or the set of sequences of elts of [y]
indexed by elts of [x], sorted in lexicographic order. *)
Fixpoint list_power (A B:Type)(l:list A) (l':list B) :
list (list (A * B)) :=
match l with
| nil => cons nil nil
| cons x t =>
flat_map (fun f:list (A * B) => map (fun y:B => cons (x, y) f) l')
(list_power t l')
end.
(*************************************)
(** ** Boolean operations over lists *)
(*************************************)
Section Bool.
Variable A : Type.
Variable f : A -> bool.
(** find whether a boolean function can be satisfied by an
elements of the list. *)
Fixpoint existsb (l:list A) : bool :=
match l with
| nil => false
| a::l => f a || existsb l
end.
Lemma existsb_exists :
forall l, existsb l = true <-> exists x, In x l /\ f x = true.
Proof.
induction l; simpl; intuition.
inversion H.
firstorder.
destruct (orb_prop _ _ H1); firstorder.
firstorder.
subst.
rewrite H2; auto.
Qed.
Lemma existsb_nth : forall l n d, n < length l ->
existsb l = false -> f (nth n l d) = false.
Proof.
induction l.
inversion 1.
simpl; intros.
destruct (orb_false_elim _ _ H0); clear H0; auto.
destruct n ; auto.
rewrite IHl; auto with arith.
Qed.
Lemma existsb_app : forall l1 l2,
existsb (l1++l2) = existsb l1 || existsb l2.
Proof.
induction l1; intros l2; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** find whether a boolean function is satisfied by
all the elements of a list. *)
Fixpoint forallb (l:list A) : bool :=
match l with
| nil => true
| a::l => f a && forallb l
end.
Lemma forallb_forall :
forall l, forallb l = true <-> (forall x, In x l -> f x = true).
Proof.
induction l; simpl; intuition.
destruct (andb_prop _ _ H1).
congruence.
destruct (andb_prop _ _ H1); auto.
assert (forallb l = true).
apply H0; intuition.
rewrite H1; auto.
Qed.
Lemma forallb_app :
forall l1 l2, forallb (l1++l2) = forallb l1 && forallb l2.
Proof.
induction l1; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** [filter] *)
Fixpoint filter (l:list A) : list A :=
match l with
| nil => nil
| x :: l => if f x then x::(filter l) else filter l
end.
Lemma filter_In : forall x l, In x (filter l) <-> In x l /\ f x = true.
Proof.
induction l; simpl.
intuition.
intros.
case_eq (f a); intros; simpl; intuition congruence.
Qed.
(** [find] *)
Fixpoint find (l:list A) : option A :=
match l with
| nil => None
| x :: tl => if f x then Some x else find tl
end.
Lemma find_some l x : find l = Some x -> In x l /\ f x = true.
Proof.
induction l as [|a l IH]; simpl; [easy| ].
case_eq (f a); intros Ha Eq.
* injection Eq as ->; auto.
* destruct (IH Eq); auto.
Qed.
Lemma find_none l : find l = None -> forall x, In x l -> f x = false.
Proof.
induction l as [|a l IH]; simpl; [easy|].
case_eq (f a); intros Ha Eq x IN; [easy|].
destruct IN as [<-|IN]; auto.
Qed.
(** [partition] *)
Fixpoint partition (l:list A) : list A * list A :=
match l with
| nil => (nil, nil)
| x :: tl => let (g,d) := partition tl in
if f x then (x::g,d) else (g,x::d)
end.
Theorem partition_cons1 a l l1 l2:
partition l = (l1, l2) ->
f a = true ->
partition (a::l) = (a::l1, l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_cons2 a l l1 l2:
partition l = (l1, l2) ->
f a=false ->
partition (a::l) = (l1, a::l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_length l l1 l2:
partition l = (l1, l2) ->
length l = length l1 + length l2.
Proof.
revert l1 l2. induction l as [ | a l' Hrec]; intros l1 l2.
- now intros [= <- <- ].
- simpl. destruct (f a), (partition l') as (left, right);
intros [= <- <- ]; simpl; rewrite (Hrec left right); auto.
Qed.
Theorem partition_inv_nil (l : list A):
partition l = ([], []) <-> l = [].
Proof.
split.
- destruct l as [|a l'].
* intuition.
* simpl. destruct (f a), (partition l'); now intros [= -> ->].
- now intros ->.
Qed.
Theorem elements_in_partition l l1 l2:
partition l = (l1, l2) ->
forall x:A, In x l <-> In x l1 \/ In x l2.
Proof.
revert l1 l2. induction l as [| a l' Hrec]; simpl; intros l1 l2 Eq x.
- injection Eq as <- <-. tauto.
- destruct (partition l') as (left, right).
specialize (Hrec left right eq_refl x).
destruct (f a); injection Eq as <- <-; simpl; tauto.
Qed.
End Bool.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables (A : Type) (B : Type).
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (left,right) := split tl in (x::left, y::right)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
induction l.
destruct n; destruct d; simpl; auto.
destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct a; destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
let (l1,l2) := split l in combine l1 l2 = l.
Proof.
induction l.
simpl; auto.
destruct a; simpl.
destruct (split l); simpl in *.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
induction l, l'; simpl; trivial; try discriminate.
now intros [= ->%IHl].
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto; intros.
contradiction.
destruct H.
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
induction l.
simpl; intros; contradiction.
destruct l'; simpl; auto; intros.
destruct H.
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
induction l; destruct l'; intros; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
induction l;
[ simpl; tauto
| simpl; intros; apply in_or_app; destruct H;
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
split; [ | intros; apply in_prod; intuition ].
induction l; simpl; intros.
intuition.
destruct (in_app_or _ _ _ H); clear H.
destruct (in_map_iff (fun y : B => (a, y)) l' (x,y)) as (H1,_).
destruct (H1 H0) as (z,(H2,H3)); clear H0 H1.
injection H2 as -> ->; intuition.
intuition.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
induction l; simpl; auto.
intros.
rewrite app_length.
rewrite map_length.
auto.
Qed.
End ListPairs.
(*****************************************)
(** * Miscellaneous operations on lists *)
(*****************************************)
(******************************)
(** ** Length order of lists *)
(******************************)
Section length_order.
Variable A : Type.
Definition lel (l m:list A) := length l <= length m.
Variables a b : A.
Variables l m n : list A.
Lemma lel_refl : lel l l.
Proof.
unfold lel; auto with arith.
Qed.
Lemma lel_trans : lel l m -> lel m n -> lel l n.
Proof.
unfold lel; intros.
now_show (length l <= length n).
apply le_trans with (length m); auto with arith.
Qed.
Lemma lel_cons_cons : lel l m -> lel (a :: l) (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_cons : lel l m -> lel l (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_tail : lel (a :: l) (b :: m) -> lel l m.
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_nil : forall l':list A, lel l' nil -> nil = l'.
Proof.
intro l'; elim l'; auto with arith.
intros a' y H H0.
now_show (nil = a' :: y).
absurd (S (length y) <= 0); auto with arith.
Qed.
End length_order.
Hint Resolve lel_refl lel_cons_cons lel_cons lel_nil lel_nil nil_cons:
datatypes.
(******************************)
(** ** Set inclusion on list *)
(******************************)
Section SetIncl.
Variable A : Type.
Definition incl (l m:list A) := forall a:A, In a l -> In a m.
Hint Unfold incl.
Lemma incl_refl : forall l:list A, incl l l.
Proof.
auto.
Qed.
Hint Resolve incl_refl.
Lemma incl_tl : forall (a:A) (l m:list A), incl l m -> incl l (a :: m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_tl.
Lemma incl_tran : forall l m n:list A, incl l m -> incl m n -> incl l n.
Proof.
auto.
Qed.
Lemma incl_appl : forall l m n:list A, incl l n -> incl l (n ++ m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appl.
Lemma incl_appr : forall l m n:list A, incl l n -> incl l (m ++ n).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appr.
Lemma incl_cons :
forall (a:A) (l m:list A), In a m -> incl l m -> incl (a :: l) m.
Proof.
unfold incl; simpl; intros a l m H H0 a0 H1.
now_show (In a0 m).
elim H1.
now_show (a = a0 -> In a0 m).
elim H1; auto; intro H2.
now_show (a = a0 -> In a0 m).
elim H2; auto. (* solves subgoal *)
now_show (In a0 l -> In a0 m).
auto.
Qed.
Hint Resolve incl_cons.
Lemma incl_app : forall l m n:list A, incl l n -> incl m n -> incl (l ++ m) n.
Proof.
unfold incl; simpl; intros l m n H H0 a H1.
now_show (In a n).
elim (in_app_or _ _ _ H1); auto.
Qed.
Hint Resolve incl_app.
End SetIncl.
Hint Resolve incl_refl incl_tl incl_tran incl_appl incl_appr incl_cons
incl_app: datatypes.
(**************************************)
(** * Cutting a list at some position *)
(**************************************)
Section Cutting.
Variable A : Type.
Fixpoint firstn (n:nat)(l:list A) : list A :=
match n with
| 0 => nil
| S n => match l with
| nil => nil
| a::l => a::(firstn n l)
end
end.
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. apply Peano.le_S_n in H. f_equal. apply iHk, H.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | destruct l as [|x xs]; simpl].
- auto with arith.
- apply Peano.le_n_S, iHk.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. induction l as [|x xs Hrec].
- simpl. intros n H. apply le_n_0_eq in H. rewrite <- H. now simpl.
- destruct n.
* now simpl.
* simpl. intro H. apply le_S_n in H. now rewrite (Hrec n H).
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* unfold firstn at 2, length. now rewrite 2!app_nil_l, <- minus_n_O.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold firstn at 2. rewrite <- plus_n_O, app_nil_r.
rewrite firstn_app. rewrite <- minus_diag_reverse.
unfold firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. auto with arith.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
auto with arith.
rewrite H0, firstn_all2; [reflexivity | auto with arith].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- destruct i.
* intro. now simpl.
* destruct j.
+ now simpl.
+ simpl. f_equal. apply Hl.
Qed.
Fixpoint skipn (n:nat)(l:list A) : list A :=
match n with
| 0 => l
| S n => match l with
| nil => nil
| a::l => skipn n l
end
end.
Lemma firstn_skipn : forall n l, firstn n l ++ skipn n l = l.
Proof.
induction n.
simpl; auto.
destruct l; simpl; auto.
f_equal; auto.
Qed.
Lemma firstn_length : forall n l, length (firstn n l) = min n (length l).
Proof.
induction n; destruct l; simpl; auto.
Qed.
Lemma removelast_firstn : forall n l, n < length l ->
removelast (firstn (S n) l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (firstn (S (S n)) (a::l)) with ((a::nil)++firstn (S n) l).
change (firstn (S n) (a::l)) with (a::firstn n l).
rewrite removelast_app.
rewrite IHn; auto with arith.
clear IHn; destruct l; simpl in *; try discriminate.
inversion_clear H.
inversion_clear H0.
Qed.
Lemma firstn_removelast : forall n l, n < length l ->
firstn n (removelast l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (removelast (a :: l)) with (removelast ((a::nil)++l)).
rewrite removelast_app.
simpl; f_equal; auto with arith.
intro H0; rewrite H0 in H; inversion_clear H; inversion_clear H1.
Qed.
End Cutting.
(**********************************************************************)
(** ** Predicate for List addition/removal (no need for decidability) *)
(**********************************************************************)
Section Add.
Variable A : Type.
(* [Add a l l'] means that [l'] is exactly [l], with [a] added
once somewhere *)
Inductive Add (a:A) : list A -> list A -> Prop :=
| Add_head l : Add a l (a::l)
| Add_cons x l l' : Add a l l' -> Add a (x::l) (x::l').
Lemma Add_app a l1 l2 : Add a (l1++l2) (l1++a::l2).
Proof.
induction l1; simpl; now constructor.
Qed.
Lemma Add_split a l l' :
Add a l l' -> exists l1 l2, l = l1++l2 /\ l' = l1++a::l2.
Proof.
induction 1.
- exists nil; exists l; split; trivial.
- destruct IHAdd as (l1 & l2 & Hl & Hl').
exists (x::l1); exists l2; split; simpl; f_equal; trivial.
Qed.
Lemma Add_in a l l' : Add a l l' ->
forall x, In x l' <-> In x (a::l).
Proof.
induction 1; intros; simpl in *; rewrite ?IHAdd; tauto.
Qed.
Lemma Add_length a l l' : Add a l l' -> length l' = S (length l).
Proof.
induction 1; simpl; auto with arith.
Qed.
Lemma Add_inv a l : In a l -> exists l', Add a l' l.
Proof.
intro Ha. destruct (in_split _ _ Ha) as (l1 & l2 & ->).
exists (l1 ++ l2). apply Add_app.
Qed.
Lemma incl_Add_inv a l u v :
~In a l -> incl (a::l) v -> Add a u v -> incl l u.
Proof.
intros Ha H AD y Hy.
assert (Hy' : In y (a::u)).
{ rewrite <- (Add_in AD). apply H; simpl; auto. }
destruct Hy'; [ subst; now elim Ha | trivial ].
Qed.
End Add.
(********************************)
(** ** Lists without redundancy *)
(********************************)
Section ReDun.
Variable A : Type.
Inductive NoDup : list A -> Prop :=
| NoDup_nil : NoDup nil
| NoDup_cons : forall x l, ~ In x l -> NoDup l -> NoDup (x::l).
Lemma NoDup_Add a l l' : Add a l l' -> (NoDup l' <-> NoDup l /\ ~In a l).
Proof.
induction 1 as [l|x l l' AD IH].
- split; [ inversion_clear 1; now split | now constructor ].
- split.
+ inversion_clear 1. rewrite IH in *. rewrite (Add_in AD) in *.
simpl in *; split; try constructor; intuition.
+ intros (N,IN). inversion_clear N. constructor.
* rewrite (Add_in AD); simpl in *; intuition.
* apply IH. split; trivial. simpl in *; intuition.
Qed.
Lemma NoDup_remove l l' a :
NoDup (l++a::l') -> NoDup (l++l') /\ ~In a (l++l').
Proof.
apply NoDup_Add. apply Add_app.
Qed.
Lemma NoDup_remove_1 l l' a : NoDup (l++a::l') -> NoDup (l++l').
Proof.
intros. now apply NoDup_remove with a.
Qed.
Lemma NoDup_remove_2 l l' a : NoDup (l++a::l') -> ~In a (l++l').
Proof.
intros. now apply NoDup_remove.
Qed.
Theorem NoDup_cons_iff a l:
NoDup (a::l) <-> ~ In a l /\ NoDup l.
Proof.
split.
+ inversion_clear 1. now split.
+ now constructor.
Qed.
(** Effective computation of a list without duplicates *)
Hypothesis decA: forall x y : A, {x = y} + {x <> y}.
Fixpoint nodup (l : list A) : list A :=
match l with
| [] => []
| x::xs => if in_dec decA x xs then nodup xs else x::(nodup xs)
end.
Lemma nodup_In l x : In x (nodup l) <-> In x l.
Proof.
induction l as [|a l' Hrec]; simpl.
- reflexivity.
- destruct (in_dec decA a l'); simpl; rewrite Hrec.
* intuition; now subst.
* reflexivity.
Qed.
Lemma NoDup_nodup l: NoDup (nodup l).
Proof.
induction l as [|a l' Hrec]; simpl.
- constructor.
- destruct (in_dec decA a l'); simpl.
* assumption.
* constructor; [ now rewrite nodup_In | assumption].
Qed.
Lemma nodup_inv k l a : nodup k = a :: l -> ~ In a l.
Proof.
intros H.
assert (H' : NoDup (a::l)).
{ rewrite <- H. apply NoDup_nodup. }
now inversion_clear H'.
Qed.
Theorem NoDup_count_occ l:
NoDup l <-> (forall x:A, count_occ decA l x <= 1).
Proof.
induction l as [| a l' Hrec].
- simpl; split; auto. constructor.
- rewrite NoDup_cons_iff, Hrec, (count_occ_not_In decA). clear Hrec. split.
+ intros (Ha, H) x. simpl. destruct (decA a x); auto.
subst; now rewrite Ha.
+ split.
* specialize (H a). rewrite count_occ_cons_eq in H; trivial.
now inversion H.
* intros x. specialize (H x). simpl in *. destruct (decA a x); auto.
now apply Nat.lt_le_incl.
Qed.
Theorem NoDup_count_occ' l:
NoDup l <-> (forall x:A, In x l -> count_occ decA l x = 1).
Proof.
rewrite NoDup_count_occ.
setoid_rewrite (count_occ_In decA). unfold gt, lt in *.
split; intros H x; specialize (H x);
set (n := count_occ decA l x) in *; clearbody n.
(* the rest would be solved by omega if we had it here... *)
- now apply Nat.le_antisymm.
- destruct (Nat.le_gt_cases 1 n); trivial.
+ rewrite H; trivial.
+ now apply Nat.lt_le_incl.
Qed.
(** Alternative characterisations of being without duplicates,
thanks to [nth_error] and [nth] *)
Lemma NoDup_nth_error l :
NoDup l <->
(forall i j, i<length l -> nth_error l i = nth_error l j -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. eapply nth_error_In; eauto.
* elim Hal. eapply nth_error_In; eauto.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. apply In_nth_error in Ha. destruct Ha as (n,Hn).
assert (n < length l) by (now rewrite <- nth_error_Some, Hn).
specialize (H 0 (S n)). simpl in H. discriminate H; auto with arith.
* apply IHl.
intros i j Hi E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
Lemma NoDup_nth l d :
NoDup l <->
(forall i j, i<length l -> j<length l ->
nth i l d = nth j l d -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi Hj E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. subst a. apply nth_In; auto with arith.
* elim Hal. subst a. apply nth_In; auto with arith.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. eapply In_nth in Ha. destruct Ha as (n & Hn & Hn').
specialize (H 0 (S n)). simpl in H. discriminate H; eauto with arith.
* apply IHl.
intros i j Hi Hj E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
(** Having [NoDup] hypotheses bring more precise facts about [incl]. *)
Lemma NoDup_incl_length l l' :
NoDup l -> incl l l' -> length l <= length l'.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH]; simpl.
- auto with arith.
- intros l' H.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_length AD). apply le_n_S. apply IH.
now apply incl_Add_inv with a l'.
Qed.
Lemma NoDup_length_incl l l' :
NoDup l -> length l' <= length l -> incl l l' -> incl l' l.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH].
- destruct l'; easy.
- intros l' E H x Hx.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_in AD) in Hx. simpl in Hx.
destruct Hx as [Hx|Hx]; [left; trivial|right].
revert x Hx. apply (IH l''); trivial.
* apply le_S_n. now rewrite <- (Add_length AD).
* now apply incl_Add_inv with a l'.
Qed.
End ReDun.
(** NoDup and map *)
(** NB: the reciprocal result holds only for injective functions,
see FinFun.v *)
Lemma NoDup_map_inv A B (f:A->B) l : NoDup (map f l) -> NoDup l.
Proof.
induction l; simpl; inversion_clear 1; subst; constructor; auto.
intro H. now apply (in_map f) in H.
Qed.
(***********************************)
(** ** Sequence of natural numbers *)
(***********************************)
Section NatSeq.
(** [seq] computes the sequence of [len] contiguous integers
that starts at [start]. For instance, [seq 2 3] is [2::3::4::nil]. *)
Fixpoint seq (start len:nat) : list nat :=
match len with
| 0 => nil
| S len => start :: seq (S start) len
end.
Lemma seq_length : forall len start, length (seq start len) = len.
Proof.
induction len; simpl; auto.
Qed.
Lemma seq_nth : forall len start n d,
n < len -> nth n (seq start len) d = start+n.
Proof.
induction len; intros.
inversion H.
simpl seq.
destruct n; simpl.
auto with arith.
rewrite IHlen;simpl; auto with arith.
Qed.
Lemma seq_shift : forall len start,
map S (seq start len) = seq (S start) len.
Proof.
induction len; simpl; auto.
intros.
rewrite IHlen.
auto with arith.
Qed.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Lemma seq_NoDup len start : NoDup (seq start len).
Proof.
revert start; induction len; simpl; constructor; trivial.
rewrite in_seq. intros (H,_). apply (Lt.lt_irrefl _ H).
Qed.
End NatSeq.
Section Exists_Forall.
(** * Existential and universal predicates over lists *)
Variable A:Type.
Section One_predicate.
Variable P:A->Prop.
Inductive Exists : list A -> Prop :=
| Exists_cons_hd : forall x l, P x -> Exists (x::l)
| Exists_cons_tl : forall x l, Exists l -> Exists (x::l).
Hint Constructors Exists.
Lemma Exists_exists (l:list A) :
Exists l <-> (exists x, In x l /\ P x).
Proof.
split.
- induction 1; firstorder.
- induction l; firstorder; subst; auto.
Qed.
Lemma Exists_nil : Exists nil <-> False.
Proof. split; inversion 1. Qed.
Lemma Exists_cons x l:
Exists (x::l) <-> P x \/ Exists l.
Proof. split; inversion 1; auto. Qed.
Lemma Exists_dec l:
(forall x:A, {P x} + { ~ P x }) ->
{Exists l} + {~ Exists l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- right. abstract now rewrite Exists_nil.
- destruct Hrec as [Hl'|Hl'].
* left. now apply Exists_cons_tl.
* destruct (Pdec a) as [Ha|Ha].
+ left. now apply Exists_cons_hd.
+ right. abstract now inversion 1.
Defined.
Inductive Forall : list A -> Prop :=
| Forall_nil : Forall nil
| Forall_cons : forall x l, P x -> Forall l -> Forall (x::l).
Hint Constructors Forall.
Lemma Forall_forall (l:list A):
Forall l <-> (forall x, In x l -> P x).
Proof.
split.
- induction 1; firstorder; subst; auto.
- induction l; firstorder.
Qed.
Lemma Forall_inv : forall (a:A) l, Forall (a :: l) -> P a.
Proof.
intros; inversion H; trivial.
Qed.
Lemma Forall_rect : forall (Q : list A -> Type),
Q [] -> (forall b l, P b -> Q (b :: l)) -> forall l, Forall l -> Q l.
Proof.
intros Q H H'; induction l; intro; [|eapply H', Forall_inv]; eassumption.
Qed.
Lemma Forall_dec :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A, {Forall l} + {~ Forall l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- left. apply Forall_nil.
- destruct Hrec as [Hl'|Hl'].
+ destruct (Pdec a) as [Ha|Ha].
* left. now apply Forall_cons.
* right. abstract now inversion 1.
+ right. abstract now inversion 1.
Defined.
End One_predicate.
Lemma Forall_Exists_neg (P:A->Prop)(l:list A) :
Forall (fun x => ~ P x) l <-> ~(Exists P l).
Proof.
rewrite Forall_forall, Exists_exists. firstorder.
Qed.
Lemma Exists_Forall_neg (P:A->Prop)(l:list A) :
(forall x, P x \/ ~P x) ->
Exists (fun x => ~ P x) l <-> ~(Forall P l).
Proof.
intro Dec.
split.
- rewrite Forall_forall, Exists_exists; firstorder.
- intros NF.
induction l as [|a l IH].
+ destruct NF. constructor.
+ destruct (Dec a) as [Ha|Ha].
* apply Exists_cons_tl, IH. contradict NF. now constructor.
* now apply Exists_cons_hd.
Qed.
Lemma neg_Forall_Exists_neg (P:A->Prop) (l:list A) :
(forall x:A, {P x} + { ~ P x }) ->
~ Forall P l ->
Exists (fun x => ~ P x) l.
Proof.
intro Dec.
apply Exists_Forall_neg; intros.
destruct (Dec x); auto.
Qed.
Lemma Forall_Exists_dec (P:A->Prop) :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A,
{Forall P l} + {Exists (fun x => ~ P x) l}.
Proof.
intros Pdec l.
destruct (Forall_dec P Pdec l); [left|right]; trivial.
now apply neg_Forall_Exists_neg.
Defined.
Lemma Forall_impl : forall (P Q : A -> Prop), (forall a, P a -> Q a) ->
forall l, Forall P l -> Forall Q l.
Proof.
intros P Q H l. rewrite !Forall_forall. firstorder.
Qed.
End Exists_Forall.
Hint Constructors Exists.
Hint Constructors Forall.
Section Forall2.
(** [Forall2]: stating that elements of two lists are pairwise related. *)
Variables A B : Type.
Variable R : A -> B -> Prop.
Inductive Forall2 : list A -> list B -> Prop :=
| Forall2_nil : Forall2 [] []
| Forall2_cons : forall x y l l',
R x y -> Forall2 l l' -> Forall2 (x::l) (y::l').
Hint Constructors Forall2.
Theorem Forall2_refl : Forall2 [] [].
Proof. intros; apply Forall2_nil. Qed.
Theorem Forall2_app_inv_l : forall l1 l2 l',
Forall2 (l1 ++ l2) l' ->
exists l1' l2', Forall2 l1 l1' /\ Forall2 l2 l2' /\ l' = l1' ++ l2'.
Proof.
induction l1; intros.
exists [], l'; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1 in H4 as (l1' & l2' & Hl1 & Hl2 & ->).
exists (y::l1'), l2'; simpl; auto.
Qed.
Theorem Forall2_app_inv_r : forall l1' l2' l,
Forall2 l (l1' ++ l2') ->
exists l1 l2, Forall2 l1 l1' /\ Forall2 l2 l2' /\ l = l1 ++ l2.
Proof.
induction l1'; intros.
exists [], l; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1' in H4 as (l1 & l2 & Hl1 & Hl2 & ->).
exists (x::l1), l2; simpl; auto.
Qed.
Theorem Forall2_app : forall l1 l2 l1' l2',
Forall2 l1 l1' -> Forall2 l2 l2' -> Forall2 (l1 ++ l2) (l1' ++ l2').
Proof.
intros. induction l1 in l1', H, H0 |- *; inversion H; subst; simpl; auto.
Qed.
End Forall2.
Hint Constructors Forall2.
Section ForallPairs.
(** [ForallPairs] : specifies that a certain relation should
always hold when inspecting all possible pairs of elements of a list. *)
Variable A : Type.
Variable R : A -> A -> Prop.
Definition ForallPairs l :=
forall a b, In a l -> In b l -> R a b.
(** [ForallOrdPairs] : we still check a relation over all pairs
of elements of a list, but now the order of elements matters. *)
Inductive ForallOrdPairs : list A -> Prop :=
| FOP_nil : ForallOrdPairs nil
| FOP_cons : forall a l,
Forall (R a) l -> ForallOrdPairs l -> ForallOrdPairs (a::l).
Hint Constructors ForallOrdPairs.
Lemma ForallOrdPairs_In : forall l,
ForallOrdPairs l ->
forall x y, In x l -> In y l -> x=y \/ R x y \/ R y x.
Proof.
induction 1.
inversion 1.
simpl; destruct 1; destruct 1; subst; auto.
right; left. apply -> Forall_forall; eauto.
right; right. apply -> Forall_forall; eauto.
Qed.
(** [ForallPairs] implies [ForallOrdPairs]. The reverse implication is true
only when [R] is symmetric and reflexive. *)
Lemma ForallPairs_ForallOrdPairs l: ForallPairs l -> ForallOrdPairs l.
Proof.
induction l; auto. intros H.
constructor.
apply <- Forall_forall. intros; apply H; simpl; auto.
apply IHl. red; intros; apply H; simpl; auto.
Qed.
Lemma ForallOrdPairs_ForallPairs :
(forall x, R x x) ->
(forall x y, R x y -> R y x) ->
forall l, ForallOrdPairs l -> ForallPairs l.
Proof.
intros Refl Sym l Hl x y Hx Hy.
destruct (ForallOrdPairs_In Hl _ _ Hx Hy); subst; intuition.
Qed.
End ForallPairs.
(** * Inversion of predicates over lists based on head symbol *)
Ltac is_list_constr c :=
match c with
| nil => idtac
| (_::_) => idtac
| _ => fail
end.
Ltac invlist f :=
match goal with
| H:f ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| _ => idtac
end.
(** * Exporting hints and tactics *)
Hint Rewrite
rev_involutive (* rev (rev l) = l *)
rev_unit (* rev (l ++ a :: nil) = a :: rev l *)
map_nth (* nth n (map f l) (f d) = f (nth n l d) *)
map_length (* length (map f l) = length l *)
seq_length (* length (seq start len) = len *)
app_length (* length (l ++ l') = length l + length l' *)
rev_length (* length (rev l) = length l *)
app_nil_r (* l ++ nil = l *)
: list.
Ltac simpl_list := autorewrite with list.
Ltac ssimpl_list := autorewrite with list using simpl.
(* begin hide *)
(* Compatibility notations after the migration of [list] to [Datatypes] *)
Notation list := list (only parsing).
Notation list_rect := list_rect (only parsing).
Notation list_rec := list_rec (only parsing).
Notation list_ind := list_ind (only parsing).
Notation nil := nil (only parsing).
Notation cons := cons (only parsing).
Notation length := length (only parsing).
Notation app := app (only parsing).
(* Compatibility Names *)
Notation tail := tl (only parsing).
Notation head := hd_error (only parsing).
Notation head_nil := hd_error_nil (only parsing).
Notation head_cons := hd_error_cons (only parsing).
Notation ass_app := app_assoc (only parsing).
Notation app_ass := app_assoc_reverse (only parsing).
Notation In_split := in_split (only parsing).
Notation In_rev := in_rev (only parsing).
Notation In_dec := in_dec (only parsing).
Notation distr_rev := rev_app_distr (only parsing).
Notation rev_acc := rev_append (only parsing).
Notation rev_acc_rev := rev_append_rev (only parsing).
Notation AllS := Forall (only parsing). (* was formerly in TheoryList *)
Hint Resolve app_nil_end : datatypes.
(* end hide *)
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
End Repeat.
(* Unset Universe Polymorphism. *)
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Memory Windows
// File : hbi_mw.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This block implements the memory window read and write caches, and yuv
// conversion.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps
module hbi_mw
(
// from PCI
input hb_clk,
input mclock,
input hb_soft_reset_n,
input frame_n, // PCI FRAME#
input sobn_n, // start of burst
input irdy_n, // PCI IRDY#
input [25:2] hbi_mac, // pci address, from counter
input [31:0] hbi_data_in, // pci data, one flop from pin, swizzled
input [3:0] mw_be, // pci byte enables, one flop, swizzled
input hb_write, // read(0)/write(1) indicator.
// from REGBLOCK
input cs_mem0_n, // decode for window 0
input cs_mem1_n, // decode for window 0
input [24:0] mw0_ctrl_reg, // memory win 0 control reg
input [24:0] mw1_ctrl_reg, // memory win 1 control reg
input [3:0] mw0_sz, // memory win 0 size reg
input [3:0] mw1_sz, // memory win 1 size reg
input [25:12] mw0_org, // memory win 0 origin reg
input [25:12] mw1_org, // memory win 1 origin reg
// from MC
input hst_push, // data strobe to load read cache
input hst_pop, // data strobe to select next location
input [1:0] hst_mw_addr, // Memory window address for RAM
input mc_ready_p, // mc is ready to accept a command
input [127:0] pix_in_dbus, // data bus from mc to read cache
// from CRT
input crt_vertical_intrp_n, // vertical interrupt
input hbi_mwflush, // any memory window ctrl register decode
input cs_de_xy1_n, // 2d trigger register decode
input cs_dl_cntl, // cache flush request from DLP
// to PCI
output [31:0] hb_rcache_dout, // readback data from mc, via read cache
output window0_busy_n, // status for polling
output window1_busy_n, // status for polling
output mw_trdy, // trdy, one flop from the pin
output mw_stop, // stop, one flop from the pin
// to DLP
output mw_dlp_fip, // memory window write cache is dirty
// to DE
output mw_de_fip, // flush initiated by DE trigger
// to MC
output [22:0] linear_origin, // memory address
output [127:0] hb_pdo, // memory data
output [15:0] mem_mask_bus, // byte enables
output read, // memory read=1, write=0
output hb_mc_request_p, // request a memory cycle
output full
);
/*
* wires
*/
wire [3:0] wc_be, wc_be_d;
wire clr_wc0;
wire clr_wc1;
wire ld_wc0;
wire ld_wc1;
wire [2:0] sub_buf_sel;
wire [31:0] pci_data;
wire [7:0] lut_v0_index;
wire [7:0] lut_u0_index;
wire [9:0] lut_v0;
wire [9:0] lut_v1;
wire [9:0] lut_u0;
wire [9:0] lut_u1;
wire [3:0] rcache_sel;
wire rst_rc_ptr;
wire [2:0] mw_dp_mode;
wire wcregs_addr;
wire wcregs_we;
wire mc_done;
wire [1:0] push_count;
wire [3:0] read_addr;
wire yuv_ycrcb;
wire select; // select which half to write 422_32 to
/*
* Memory Window Control
*/
hbi_mw_ctl U_MW_CTL
(
.hb_clk (hb_clk),
.hb_soft_reset_n (hb_soft_reset_n),
.frame_n (frame_n),
.sobn_n (sobn_n),
.irdy_n (irdy_n),
.hbi_mac (hbi_mac),
.mw_be (mw_be),
.hb_write (hb_write),
.cs_mem0_n (cs_mem0_n),
.cs_mem1_n (cs_mem1_n),
.mw0_ctrl_reg (mw0_ctrl_reg),
.mw1_ctrl_reg (mw1_ctrl_reg),
.mw0_sz (mw0_sz),
.mw1_sz (mw1_sz),
.mw0_org (mw0_org),
.mw1_org (mw1_org),
.mc_rdy (mc_ready_p),
.mc_done (mc_done),
.crt_vertical_intrp_n(crt_vertical_intrp_n),
.hbi_mwflush (hbi_mwflush),
.cs_de_xy1_n (cs_de_xy1_n),
.cs_dl_cntl (cs_dl_cntl),
.window0_busy_n (window0_busy_n),
.window1_busy_n (window1_busy_n),
.mw_dlp_fip (mw_dlp_fip),
.mw_de_fip (mw_de_fip),
.mw_trdy (mw_trdy),
.mw_stop (mw_stop),
.linear_origin (linear_origin),
.mc_rw (read),
.mc_req (hb_mc_request_p),
.clr_wc0 (clr_wc0),
.clr_wc1 (clr_wc1),
.ld_wc0 (ld_wc0),
.ld_wc1 (ld_wc1),
.wcregs_addr (wcregs_addr),
.wcregs_we (wcregs_we),
.sub_buf_sel (sub_buf_sel),
.wc_be (wc_be),
.wc_be_d (wc_be_d),
.yuv_ycrcb (yuv_ycrcb),
.mw_dp_mode (mw_dp_mode),
.read_addr (read_addr),
.select_del (select),
.full (full)
);
/*
* Write Cache Registers
*/
hbi_wcregs U_WCREGS
(
.hb_clk (hb_clk),
.hb_soft_reset_n (hb_soft_reset_n),
.pci_data (pci_data),
.wc_be (wc_be),
.wc_be_d (wc_be_d),
.clr_wc0 (clr_wc0),
.clr_wc1 (clr_wc1),
.ld_wc0 (ld_wc0),
.ld_wc1 (ld_wc1),
.wcregs_addr (wcregs_addr),
.wcregs_we (wcregs_we),
.sub_buf_sel (sub_buf_sel),
.mclock (mclock),
.hst_pop (hst_pop),
.hst_push (hst_push),
.hst_mw_addr (hst_mw_addr),
.select (select),
.hb_pdo (hb_pdo),
.hst_md (mem_mask_bus),
.mc_done (mc_done),
.push_count (push_count)
);
/*
* Read Cache Registers
*/
ram_128_32x32_dp U_RCREGS
(
.data (pix_in_dbus),
.wren (hst_push),
.wraddress (push_count),
.wrclock (mclock),
.rdclock (hb_clk),
.rdaddress (read_addr),
.q (hb_rcache_dout)
);
/*
* YUV to RGB Converter. Note bit-blasting of yuv_adr register.
*/
hbi_yuv2rgb U_YUV2RGB
(
.hb_clk (hb_clk),
.hbi_din (hbi_data_in),
.mw_dp_mode (mw_dp_mode),
.lut_v0 (lut_v0),
.lut_v1 (lut_v1),
.lut_u0 (lut_u0),
.lut_u1 (lut_u1),
.ycbcr_sel_n (yuv_ycrcb),
.select (select),
.pci_data (pci_data),
.lut_u0_index (lut_u0_index),
.lut_v0_index (lut_v0_index)
);
/*
* V/Cr look-up table
*/
hbi_lut_v U_LUTV0
(
.hb_clk (hb_clk),
.lut_v_index (lut_v0_index[7:0]),
.lut_v0_dout (lut_v0[9:0]),
.lut_v1_dout (lut_v1[9:0])
);
/*
* U/Cb look-up table
*/
hbi_lut_u U_LUTU0
(
.hb_clk (hb_clk),
.lut_u_index (lut_u0_index[7:0]),
.lut_u0_dout (lut_u0[9:0]),
.lut_u1_dout (lut_u1[9:0])
);
endmodule // HBI_MW
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top level module of qspi_4cs
//
// ====================================================================
module sirv_qspi_4cs_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
output io_tl_i_0_0
);
wire io_tl_r_0_a_ready;
assign i_icb_cmd_ready = io_tl_r_0_a_ready;
wire io_tl_r_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_r_0_a_bits_param = 3'b0;
wire [2:0] io_tl_r_0_a_bits_size = 3'd2;
wire [4:0] io_tl_r_0_a_bits_source = 5'b0;
wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata;
wire io_tl_r_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_tl_r_0_d_bits_opcode;
wire [1:0] io_tl_r_0_d_bits_param;
wire [2:0] io_tl_r_0_d_bits_size;
wire [4:0] io_tl_r_0_d_bits_source;
wire io_tl_r_0_d_bits_sink;
wire [1:0] io_tl_r_0_d_bits_addr_lo;
wire [31:0] io_tl_r_0_d_bits_data;
wire io_tl_r_0_d_bits_error;
wire io_tl_r_0_d_valid;
assign i_icb_rsp_valid = io_tl_r_0_d_valid;
assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data;
// Not used
wire io_tl_r_0_b_ready = 1'b0;
wire io_tl_r_0_b_valid;
wire [2:0] io_tl_r_0_b_bits_opcode;
wire [1:0] io_tl_r_0_b_bits_param;
wire [2:0] io_tl_r_0_b_bits_size;
wire [4:0] io_tl_r_0_b_bits_source;
wire [28:0] io_tl_r_0_b_bits_address;
wire [3:0] io_tl_r_0_b_bits_mask;
wire [31:0] io_tl_r_0_b_bits_data;
// Not used
wire io_tl_r_0_c_ready;
wire io_tl_r_0_c_valid = 1'b0;
wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_r_0_c_bits_param = 3'b0;
wire [2:0] io_tl_r_0_c_bits_size = 3'd2;
wire [4:0] io_tl_r_0_c_bits_source = 5'b0;
wire [28:0] io_tl_r_0_c_bits_address = 29'b0;
wire [31:0] io_tl_r_0_c_bits_data = 32'b0;
wire io_tl_r_0_c_bits_error = 1'b0;
// Not used
wire io_tl_r_0_e_ready;
wire io_tl_r_0_e_valid = 1'b0;
wire io_tl_r_0_e_bits_sink = 1'b0;
sirv_qspi_4cs u_sirv_qspi_4cs(
.clock (clk ),
.reset (~rst_n ),
.io_tl_r_0_a_ready (io_tl_r_0_a_ready ),
.io_tl_r_0_a_valid (io_tl_r_0_a_valid ),
.io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ),
.io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ),
.io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ),
.io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ),
.io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ),
.io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ),
.io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ),
.io_tl_r_0_b_ready (io_tl_r_0_b_ready ),
.io_tl_r_0_b_valid (io_tl_r_0_b_valid ),
.io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ),
.io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ),
.io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ),
.io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ),
.io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ),
.io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ),
.io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ),
.io_tl_r_0_c_ready (io_tl_r_0_c_ready ),
.io_tl_r_0_c_valid (io_tl_r_0_c_valid ),
.io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ),
.io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ),
.io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ),
.io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ),
.io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ),
.io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ),
.io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ),
.io_tl_r_0_d_ready (io_tl_r_0_d_ready ),
.io_tl_r_0_d_valid (io_tl_r_0_d_valid ),
.io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ),
.io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ),
.io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ),
.io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ),
.io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ),
.io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ),
.io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ),
.io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ),
.io_tl_r_0_e_ready (io_tl_r_0_e_ready ),
.io_tl_r_0_e_valid (io_tl_r_0_e_valid ),
.io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ),
.io_port_sck (io_port_sck ),
.io_port_dq_0_i (io_port_dq_0_i ),
.io_port_dq_0_o (io_port_dq_0_o ),
.io_port_dq_0_oe (io_port_dq_0_oe),
.io_port_dq_1_i (io_port_dq_1_i ),
.io_port_dq_1_o (io_port_dq_1_o ),
.io_port_dq_1_oe (io_port_dq_1_oe),
.io_port_dq_2_i (io_port_dq_2_i ),
.io_port_dq_2_o (io_port_dq_2_o ),
.io_port_dq_2_oe (io_port_dq_2_oe),
.io_port_dq_3_i (io_port_dq_3_i ),
.io_port_dq_3_o (io_port_dq_3_o ),
.io_port_dq_3_oe (io_port_dq_3_oe),
.io_port_cs_0 (io_port_cs_0 ),
.io_port_cs_1 (io_port_cs_1 ),
.io_port_cs_2 (io_port_cs_2 ),
.io_port_cs_3 (io_port_cs_3 ),
.io_tl_i_0_0 (io_tl_i_0_0 )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A2BB2O_PP_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_PP_BLACKBOX_V
|
module ControlCore(
input confirmation, continue_button, mode_flag,
input [6 : 0] ID,
output reg enable, allow_write_on_memory, should_fill_channel_b_with_offset,
output reg is_input, is_output,
output reg [2 : 0] control_channel_B_sign_extend_unit, control_load_sign_extend_unit,
output reg [2 : 0] controlRB, controlMAH,
output reg [3 : 0] controlALU, controlBS, specreg_update_mode
);
always @ ( * ) begin
controlALU = 12;
controlBS = 0;
controlRB = 1;
control_channel_B_sign_extend_unit = 0;
control_load_sign_extend_unit = 0;
controlMAH = 0;
allow_write_on_memory = 0;
should_fill_channel_b_with_offset = 0;
enable = 1;
specreg_update_mode = 0;
is_input = 0;
is_output = 0;
case (ID)
1:begin
controlBS=3;
should_fill_channel_b_with_offset=1;
specreg_update_mode = 1;
end
2:begin
controlBS = 4;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 1;
end
3:begin
controlBS = 2;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 1;
end
4:begin
controlALU = 2;
specreg_update_mode = 2;
end
5:begin
controlALU = 5;
specreg_update_mode = 2;
end
6:begin
controlALU = 2;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
7:begin
controlALU = 5;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
8:begin
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 3;
end
9:begin
controlALU = 5;
controlRB = 0;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
10:begin
controlALU = 2;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
11:begin
controlALU = 5;
should_fill_channel_b_with_offset = 1;
specreg_update_mode = 2;
end
12:begin
controlALU = 3;
specreg_update_mode = 3;
end
13:begin
controlALU = 13;
specreg_update_mode = 3;
end
14:begin
controlBS = 3;
specreg_update_mode = 1;
end
15:begin
controlBS = 4;
specreg_update_mode = 1;
end
16:begin
controlBS = 2;
specreg_update_mode = 1;
end
17:begin
controlALU = 1;
specreg_update_mode = 2;
end
18:begin
controlALU = 8;
specreg_update_mode = 2;
end
19:begin
controlBS = 5;
specreg_update_mode = 1;
end
20:begin
controlALU = 14;
specreg_update_mode = 3;
end
21:begin
controlALU = 6;
specreg_update_mode = 2;
end
22:begin
controlALU = 5;
controlRB = 0;
specreg_update_mode = 2;
end
23:begin
controlALU = 2;
controlRB = 0;
specreg_update_mode = 2;
end
24:begin
controlALU = 7;
specreg_update_mode = 3;
end
25:begin
controlALU = 9;
specreg_update_mode = 3;
end
26:begin
controlALU = 4;
specreg_update_mode = 3;
end
27:begin
specreg_update_mode = 3;
end
28:begin
controlALU = 2;
end
29:begin
controlALU = 2;
end
30:begin
controlALU = 2;
controlRB = 0;
end
31:begin
controlALU = 5;
specreg_update_mode = 2;
end
32:begin
controlALU = 5;
controlRB = 0;
specreg_update_mode = 2;
end
33:begin
controlALU = 5;
controlRB = 0;
specreg_update_mode = 2;
end
34:begin
controlALU = 10;
specreg_update_mode = 4;
end
35:begin
//standard
end
36:begin
//standard
end
37:begin
//standard
end
38:begin //BX Register
controlALU = 2;
controlBS = 0;
control_channel_B_sign_extend_unit = 0;
controlRB = 0;
should_fill_channel_b_with_offset = 0;
controlMAH = 4;
end
39:begin
controlALU = 2;
controlBS = 1;
should_fill_channel_b_with_offset = 1;
controlRB = 2;
end
40:begin
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
41:begin
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
42:begin
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
43:begin
controlALU = 2;
control_load_sign_extend_unit = 2;
controlRB = 2;
end
44:begin
controlALU = 2;
controlRB = 2;
end
45:begin
controlALU = 2;
control_load_sign_extend_unit = 3;
controlRB = 2;
end
46:begin
controlALU = 2;
control_load_sign_extend_unit = 4;
controlRB = 2;
end
47:begin
controlALU = 2;
control_load_sign_extend_unit = 1;
controlRB = 2;
end
48:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
49:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlRB = 2;
end
50:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
51:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
control_load_sign_extend_unit = 4;
controlRB = 2;
end
52:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
53:begin
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlRB = 2;
control_load_sign_extend_unit = 3;
end
54:begin
should_fill_channel_b_with_offset = 1;
control_channel_B_sign_extend_unit = 2;
controlALU = 2;
allow_write_on_memory = 1;
controlRB = 0;
end
55:begin
should_fill_channel_b_with_offset =1;
control_channel_B_sign_extend_unit = 2;
controlALU = 2;
controlRB = 2;
end
56:begin
should_fill_channel_b_with_offset = 1;
control_channel_B_sign_extend_unit = 0;
controlBS = 0;
controlALU = 2;
controlRB = 1;
end
57:begin
controlALU = 2;
should_fill_channel_b_with_offset = 1;
end
58:begin // CXPR
controlRB = 5;
end
59:begin
control_channel_B_sign_extend_unit = 1;
end
60:begin
control_channel_B_sign_extend_unit = 2;
end
61:begin
control_channel_B_sign_extend_unit = 3;
end
62:begin
control_channel_B_sign_extend_unit = 4;
end
63:begin
controlBS = 6;
end
64:begin
controlBS = 7;
end
65:begin
controlALU = 11;
specreg_update_mode = 4;
end
66:begin
controlBS = 8;
end
67:begin //PUSH
controlMAH = 1;
allow_write_on_memory = 1;
controlRB = 0;
end
68:begin //POP
controlMAH = 2;
controlRB = 2;
control_load_sign_extend_unit = 0;
end
69:begin // OUTPUT
controlRB = 0;
enable = confirmation;
is_output = 1;
end
70: begin // PAUSE
controlRB = 0;
enable = continue_button;
specreg_update_mode = 0;
is_input = 1;
is_output = 1;
end
71:begin // INPUT
controlBS = 0;
controlRB = 2;
control_channel_B_sign_extend_unit = 0;
control_load_sign_extend_unit = 3;
should_fill_channel_b_with_offset = 0;
allow_write_on_memory = 0;
is_input = 1;
enable = confirmation;
end
72:begin //SWI
specreg_update_mode = 5;
should_fill_channel_b_with_offset = 1;
controlRB = mode_flag ? 4 : 3;
end
73:begin //B immediate
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlBS = 0;
control_channel_B_sign_extend_unit = 2;
controlRB = 0;
controlMAH = 4;
end
74:begin //NOP
controlRB = 0;
end
75:begin //HALT
controlRB = 0;
enable = 0;
specreg_update_mode = 0;
end
76:begin // PXR Paste special register
controlALU = 15;
specreg_update_mode = 2;
controlRB = 0;
end
77:begin //PUSHN
controlMAH = 3;
should_fill_channel_b_with_offset = 1;
controlALU = 5;
controlRB = 0;
end
78:begin //POPN
controlMAH = 3;
should_fill_channel_b_with_offset = 1;
controlALU = 2;
controlRB = 0;
end
79: begin // BL
controlALU = 2;
controlRB = 1;
controlMAH = 4;
end
80:begin // BX
controlRB = 0;
controlMAH = 4;
end
default: controlRB = 0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFRTP_BLACKBOX_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtp (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_SYMBOL_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PR_PP_PG_N_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O22A_BLACKBOX_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o22a (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_BLACKBOX_V
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ledtest_pio_1 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Project Name: CoCo3FPGA Version 3.0
// File Name: coco3vid.v
//
// CoCo3 in an FPGA
//
// Revision: 3.0 08/15/15
////////////////////////////////////////////////////////////////////////////////
//
// CPU section copyrighted by John Kent
// The FDC co-processor copyrighted Daniel Wallner.
//
////////////////////////////////////////////////////////////////////////////////
//
// Color Computer 3 compatible system on a chip
//
// Version : 3.0
//
// Copyright (c) 2008 Gary Becker ([email protected])
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://groups.yahoo.com/group/CoCo3FPGA
//
// File history :
//
// 1.0 Full Release
// 2.0 Partial Release
// 3.0 Full Release
////////////////////////////////////////////////////////////////////////////////
// Gary Becker
// [email protected]
////////////////////////////////////////////////////////////////////////////////
module COCO3VIDEO(
PIX_CLK,
RESET_N,
COLOR,
HSYNC,
SYNC_FLAG,
VSYNC,
HBLANKING,
VBLANKING,
RAM_ADDRESS,
RAM_DATA,
COCO,
V,
BP,
VERT,
VID_CONT,
CSS,
LPF,
VERT_FIN_SCRL,
HLPR,
LPR,
HRES,
CRES,
HVEN,
HOR_OFFSET,
SCRN_START_HSB, // 2 extra bits for 2MB screen start
SCRN_START_MSB,
SCRN_START_LSB,
BLINK,
SWITCH5
);
input PIX_CLK;
input RESET_N;
output [8:0] COLOR;
reg [8:0] COLOR;
output HSYNC;
reg HSYNC;
output SYNC_FLAG;
reg SYNC_FLAG;
output VSYNC;
reg VSYNC;
output HBLANKING;
reg HBLANKING;
output VBLANKING;
reg VBLANKING;
//output [17:0] RAM_ADDRESS; // 512Kb
//reg [17:0] RAM_ADDRESS;
output [19:0] RAM_ADDRESS; // 2MB
reg [19:0] RAM_ADDRESS;
input [15:0] RAM_DATA;
input COCO;
input [2:0] V;
input BP;
input [6:0] VERT;
input [3:0] VID_CONT;
input CSS;
input [1:0] LPF;
input HLPR;
input [2:0] LPR;
input [3:0] VERT_FIN_SCRL;
input [3:0] HRES;
input [1:0] CRES;
input HVEN;
input [6:0] HOR_OFFSET;
input [1:0] SCRN_START_HSB; // extra 2 bits for 2MB
input [7:0] SCRN_START_MSB;
input [7:0] SCRN_START_LSB;
input BLINK;
input SWITCH5;
reg [9:0] LINE;
reg [3:0] VLPR;
reg [3:0] COCO1_VLPR;
reg [9:0] PIXEL_COUNT;
reg [15:0] CHAR_LATCH_0;
reg [15:0] CHAR_LATCH_1;
reg [15:0] CHAR_LATCH_2;
reg [15:0] CHAR_LATCH_3;
`ifndef NEW_SRAM
reg [15:0] CHAR_LATCH_4;
reg [15:0] CHAR_LATCH_5;
reg [15:0] CHAR_LATCH_6;
reg [15:0] CHAR_LATCH_7;
`endif
wire [3:0] PIXEL_ORDER;
reg [7:0] CHARACTER0;
reg [7:0] CHARACTER1;
reg [7:0] CHARACTER2;
wire [7:0] CHARACTER3;
wire [7:0] CHARACTER4;
reg UNDERLINE;
wire MODE_256;
reg [10:0] ROM_ADDRESS;
wire [19:0] RAM_ADDRESS_X; // 17:0 512kb
wire [7:0] ROM_DATA1;
wire [3:0] LINES_ROW;
reg [3:0] NUM_ROW;
wire SIX;
reg SIX_R;
wire [1:0] SG6;
reg [2:0] SG_LINES;
wire [4:0] COCO3_VLPR;
wire [3:0] PIXEL0;
wire [3:0] PIXEL1;
wire [3:0] PIXEL2;
wire [3:0] PIXEL3;
wire [3:0] PIXEL4;
wire [3:0] PIXEL5;
wire [3:0] PIXEL6;
wire [3:0] PIXEL7;
wire [3:0] PIXEL8;
wire [3:0] PIXEL9;
wire [3:0] PIXELA;
wire [3:0] PIXELB;
wire [3:0] PIXELC;
wire [3:0] PIXELD;
wire [3:0] PIXELE;
wire [3:0] PIXELF;
wire [3:0] PIXEL10;
wire [3:0] PIXEL11;
wire [3:0] PIXEL12;
wire [3:0] PIXEL13;
wire [3:0] PIXEL14;
wire [3:0] PIXEL15;
wire [3:0] PIXEL16;
wire [3:0] PIXEL17;
wire [3:0] PIXEL18;
wire [3:0] PIXEL19;
wire [3:0] PIXEL1A;
wire [3:0] PIXEL1B;
wire [3:0] PIXEL1C;
wire [3:0] PIXEL1D;
wire [3:0] PIXEL1E;
wire [3:0] PIXEL1F;
reg [15:0] COLOR0;
reg [15:0] COLOR1;
reg [15:0] COLOR2;
reg [15:0] COLOR3;
reg [15:0] COLOR4;
reg [15:0] COLOR5;
reg [15:0] COLOR6;
reg [15:0] COLOR7;
reg [20:0] ROW_ADD; // 18:0 for 512kb
wire [8:0] ROW_OFFSET;
wire [20:0] SCREEN_OFF; // 18:0 for 512kb
reg VBORDER;
reg HBORDER;
wire [8:0] BORDER;
wire [8:0] CCOLOR;
wire MODE6;
parameter PALETTE0 = 4'h0;
parameter PALETTE1 = 4'h1;
parameter PALETTE2 = 4'h2;
parameter PALETTE3 = 4'h3;
parameter PALETTE4 = 4'h4;
parameter PALETTE5 = 4'h5;
parameter PALETTE6 = 4'h6;
parameter PALETTE7 = 4'h7;
parameter PALETTE8 = 4'h8;
parameter PALETTE9 = 4'h9;
parameter PALETTEA = 4'hA;
parameter PALETTEB = 4'hB;
parameter PALETTEC = 4'hC;
parameter PALETTED = 4'hD;
parameter PALETTEE = 4'hE;
parameter PALETTEF = 4'hF;
// Character generator
COCO3GEN coco3gen(
.address(ROM_ADDRESS[10:0]),
.clock(PIX_CLK),
.q(ROM_DATA1)
);
/*****************************************************************************
* Read RAM
******************************************************************************/
assign RAM_ADDRESS_X = {ROW_ADD[20:1] + ROW_OFFSET};
assign ROW_OFFSET = //9 bits of two byte reads = 1024 max bytes
// CoCo1 low res graphics (64 pixels / 2 bytes)
({COCO,V[0]} == 2'b11) ? {5'b00000, PIXEL_COUNT[9:6]}: //16 bytes / line Read 2 bytes every 64 pixels
// HR Text
//({COCO,BP,HRES[2],CRES[0]}==4'b0000) ? {4'b0000, PIXEL_COUNT[9:5]}: //32 / 40 characters / line Read 2 bytes every 32 pixels
({COCO,BP,HRES[2],CRES[0]}==4'b0001) ? {3'b000, PIXEL_COUNT[9:4]}: //64 / 80 characters / line Read 2 bytes every 16 pixels
({COCO,BP,HRES[2],CRES[0]}==4'b0010) ? {3'b000, PIXEL_COUNT[9:4]}: //64 / 80 characters / line Read 2 bytes every 16 pixels
({COCO,BP,HRES[2],CRES[0]}==4'b0011) ? {2'b00, PIXEL_COUNT[9:3]}: //128/160 characters / line Read 2 bytes every 8 pixels
// HR Graphics
({COCO,BP,HRES}==6'b010000) ? {5'b00000, PIXEL_COUNT[9:6]}: //16 bytes / line
({COCO,BP,HRES}==6'b010001) ? {5'b00000, PIXEL_COUNT[9:6]}: //20 bytes / line
// ({COCO,BP,HRES}==6'b010010) ? {4'b0000, PIXEL_COUNT[9:5]}: //32 bytes / line
// ({COCO,BP,HRES}==6'b010011) ? {4'b0000, PIXEL_COUNT[9:5]}: //40 bytes / line
({COCO,BP,HRES}==6'b010100) ? {3'b000, PIXEL_COUNT[9:4]}: //64 bytes / line
({COCO,BP,HRES}==6'b010101) ? {3'b000, PIXEL_COUNT[9:4]}: //80 bytes / line
({COCO,BP,HRES}==6'b010110) ? {2'b00, PIXEL_COUNT[9:3]}: //128 bytes / line
({COCO,BP,HRES}==6'b010111) ? {2'b00, PIXEL_COUNT[9:3]}: //160 bytes / line
({COCO,BP,HRES}==6'b011000) ? {1'b0, PIXEL_COUNT[9:2]}: //256 bytes / line
({COCO,BP,HRES}==6'b011001) ? {1'b0, PIXEL_COUNT[9:2]}: //320 bytes / line
({COCO,BP,HRES}==6'b011010) ? PIXEL_COUNT[9:1] : //512 bytes / line
({COCO,BP,HRES}==6'b011011) ? PIXEL_COUNT[9:1] : //640 bytes / line
// CoCo1 Text and SEMIGRAPHICS
{4'b0000, PIXEL_COUNT[9:5]}; //32 characters / line
assign COCO3_VLPR = VLPR + 2'b11;
`ifndef NEW_SRAM
always @ (negedge PIX_CLK)
begin
case (PIXEL_COUNT[3:0])
4'b0000:
begin
RAM_ADDRESS <= RAM_ADDRESS_X;
CHAR_LATCH_7 <= RAM_DATA[15:0];
end
4'b0010:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
if(({PIXEL_COUNT[5],PIXEL_COUNT[4]} !=2'b00)
&(({COCO,V[0]}==2'b11) // CoCo1 16 byte / line mode
|({COCO,BP,HRES[3],HRES[2],HRES[1]}==5'b01000))) // CoCo3 16/20 bytes/line
begin
CHAR_LATCH_0 <= {CHAR_LATCH_0[11:8],4'h0,CHAR_LATCH_0[3:0],CHAR_LATCH_0[15:12]}; // Rotate into position on 16/20 bytes/line
end
else
begin
if(PIXEL_COUNT[4]
&((COCO) // All other CoCo1 modes
|({COCO,BP,HRES[3],HRES[2],HRES[1]}==5'b01001))) //CoCo3 32/40 bytes/line ?????? might have to add text differences
begin
CHAR_LATCH_0 <= {8'h00,CHAR_LATCH_0[15:8]};
end
else
begin
CHAR_LATCH_0 <= RAM_DATA[15:0]; // Everything else
end
end
end
4'b0011:
begin
if(!COCO)
ROM_ADDRESS <= {CHAR_LATCH_0[6:0],COCO3_VLPR[3:0]}; // COCO3 Text 1 (40 and 80)
else
begin
if({COCO,VID_CONT[0],CHAR_LATCH_0[6:5]} == 4'b1100)
ROM_ADDRESS <= {2'b11, CHAR_LATCH_0[4:0], COCO1_VLPR}; // COCO1 Text 1 with LC
else
ROM_ADDRESS <= {~CHAR_LATCH_0[5], CHAR_LATCH_0[5:0], COCO1_VLPR}; // COCO1 Text 1 w/o LC
end
end
4'b0100:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
CHAR_LATCH_1 <= RAM_DATA[15:0];
end
4'b0110:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
CHAR_LATCH_2 <= RAM_DATA[15:0];
// Underline
if({COCO,CRES[0],CHAR_LATCH_0[14],UNDERLINE} == 4'b0111) // Removed BP because we ignore characters during BP
CHARACTER0 <= 8'hFF;
// Not Underline
else
CHARACTER0 <= ROM_DATA1;
ROM_ADDRESS <= {CHAR_LATCH_0[14:8],COCO3_VLPR[3:0]}; // COCO3 Text 1 (40 and 80)
end
4'b1000:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
CHAR_LATCH_3 <= RAM_DATA[15:0];
end
4'b1010:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
CHAR_LATCH_4 <= RAM_DATA[15:0];
//XTEXT only, so no underline
CHARACTER1 <= ROM_DATA1;
ROM_ADDRESS <= {CHAR_LATCH_1[6:0],COCO3_VLPR[3:0]}; // COCO3 Text 1 (40 and 80)
end
4'b1100:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
CHAR_LATCH_5 <= RAM_DATA[15:0]; // last read from the previous series
end
4'b1110:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
CHAR_LATCH_6 <= RAM_DATA[15:0]; // First read of this series
// Underline
if({COCO,BP,CRES[0],CHAR_LATCH_1[14],UNDERLINE} == 5'b00111)
CHARACTER2 <= 8'hFF;
else
// Not Underline
CHARACTER2 <= ROM_DATA1;
end
endcase
end
`else
always @ (negedge PIX_CLK)
begin
case (PIXEL_COUNT[3:0])
4'b0000:
begin
RAM_ADDRESS <= RAM_ADDRESS_X;
CHAR_LATCH_3 <= RAM_DATA[15:0];
end
4'b0100:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
if(({PIXEL_COUNT[5],PIXEL_COUNT[4]} !=2'b00)
&(({COCO,V[0]}==2'b11) // CoCo1 16 byte / line mode
|({COCO,BP,HRES[3],HRES[2],HRES[1]}==5'b01000))) // CoCo3 16/20 bytes/line
begin
CHAR_LATCH_0 <= {CHAR_LATCH_0[11:8],4'h0,CHAR_LATCH_0[3:0],CHAR_LATCH_0[15:12]}; // Rotate into position on 16/20 bytes/line
end
else
begin
if(PIXEL_COUNT[4]
&((COCO) // All other CoCo1 modes
|({COCO,BP,HRES[3],HRES[2],HRES[1]}==5'b01001))) //CoCo3 32/40 bytes/line ?????? might have to add text differences
begin
CHAR_LATCH_0 <= {8'h00,CHAR_LATCH_0[15:8]};
end
else
begin
CHAR_LATCH_0 <= RAM_DATA[15:0]; // Everything else
end
end
end
4'b0101:
begin
if(!COCO)
ROM_ADDRESS <= {CHAR_LATCH_0[6:0],COCO3_VLPR[3:0]}; // COCO3 Text 1 (40 and 80)
else
begin
if({COCO,VID_CONT[0],CHAR_LATCH_0[6:5]} == 4'b1100)
ROM_ADDRESS <= {2'b11, CHAR_LATCH_0[4:0], COCO1_VLPR}; // COCO1 Text 1 with LC
else
ROM_ADDRESS <= {~CHAR_LATCH_0[5], CHAR_LATCH_0[5:0], COCO1_VLPR}; // COCO1 Text 1 w/o LC
end
end
4'b1000:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
CHAR_LATCH_1 <= RAM_DATA[15:0];
// Underline
if({COCO,CRES[0],CHAR_LATCH_0[14],UNDERLINE} == 4'b0111) // Removed BP because we ignore characters during BP
CHARACTER0 <= 8'hFF;
// Not Underline
else
CHARACTER0 <= ROM_DATA1;
ROM_ADDRESS <= {CHAR_LATCH_0[14:8],COCO3_VLPR[3:0]}; // COCO3 Text 1 (40 and 80)
end
4'b1010:
begin
//XTEXT only, so no underline
CHARACTER1 <= ROM_DATA1;
ROM_ADDRESS <= {CHAR_LATCH_1[6:0],COCO3_VLPR[3:0]}; // COCO3 Text 1 (40 and 80)
end
4'b1100:
begin
RAM_ADDRESS <= RAM_ADDRESS + 1'b1;
CHAR_LATCH_2 <= RAM_DATA[15:0];
if({COCO,BP,CRES[0],CHAR_LATCH_1[14],UNDERLINE} == 5'b00111)
CHARACTER2 <= 8'hFF;
else
// Not Underline
CHARACTER2 <= ROM_DATA1;
end
endcase
end
`endif
/*****************************************************************************
* Read Character ROM
******************************************************************************/
assign CHARACTER3 = ({COCO,BP,CRES[0],CHAR_LATCH_0[15],BLINK} == 5'b00111) ? 8'h00: // Hires Text blink
({COCO, VID_CONT[1:0], CHAR_LATCH_0[6:5]} == 5'b10000) ? ~CHARACTER0: // Lowres 0-31 Normal UC only (Inverse)
({COCO, VID_CONT[1:0], CHAR_LATCH_0[6:5]} == 5'b10001) ? ~CHARACTER0: // Lowres 32-64 Normal UC only (Inverse)
({COCO, VID_CONT[1:0], CHAR_LATCH_0[6:5]} == 5'b10101) ? ~CHARACTER0: // Lowres 32-64 LC but UC part (Inverse)
({COCO, VID_CONT[1:0], CHAR_LATCH_0[6:5]} == 5'b11010) ? ~CHARACTER0: // Lowres 64-95 Inverse
({COCO, VID_CONT[1:0], CHAR_LATCH_0[6:5]} == 5'b11011) ? ~CHARACTER0: // Lowres 96-128 Inverse
({COCO, VID_CONT[1:0], CHAR_LATCH_0[6:5]} == 5'b11100) ? ~CHARACTER0: // Lowres 0-31 Inverse
({COCO, VID_CONT[1:0], CHAR_LATCH_0[6:5]} == 5'b11110) ? ~CHARACTER0: // Lowres 64-95 Inverse
({COCO, VID_CONT[1:0], CHAR_LATCH_0[6:5]} == 5'b11111) ? ~CHARACTER0: // Lowres 96-128 Inverse
CHARACTER0; // Normal Video
assign CHARACTER4 = ({COCO,BP,CRES[0],CHAR_LATCH_1[15],BLINK} == 5'b00111) ? 8'h00: // Hires Text blink
CHARACTER2; // Normal Video
assign MODE6 = ~VID_CONT[0] ? 1'b0:
(V != 3'b000) ? 1'b0:
~SWITCH5 ? 1'b0:
1'b1;
assign PIXEL0 =
//CoCo1 Text
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[7]} == 5'b10001) ? PALETTEC:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[7]} == 5'b10000) ? PALETTED:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[7]} == 5'b10101) ? PALETTEE:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[7]} == 5'b10100) ? PALETTEF:
//HR Text
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[10:8]}==7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[10:8]}==7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[10:8]}==7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[10:8]}==7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[10:8]}==7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[10:8]}==7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[10:8]}==7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER3[7],CHAR_LATCH_0[10:8]}==7'b0010111) ? PALETTE7:
//XTEXT
({COCO,BP,CRES[0],CHARACTER3[7]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[7]}==4'b0000) ? PALETTED:
//SG4, SG8, SG12, SG24
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7], SIX,CHAR_LATCH_0[1]} == 6'b100110) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[1]} == 9'b100100011) ? PALETTE0:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[1]} == 9'b100100111) ? PALETTE1:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[1]} == 9'b100101011) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[1]} == 9'b100101111) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[1]} == 9'b100110011) ? PALETTE4:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[1]} == 9'b100110111) ? PALETTE5:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[1]} == 9'b100111011) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[1]} == 9'b100111111) ? PALETTE7:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7], SIX,CHAR_LATCH_0[3]} == 6'b100100) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[3]} == 9'b100100001) ? PALETTE0:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[3]} == 9'b100100101) ? PALETTE1:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[3]} == 9'b100101001) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[3]} == 9'b100101101) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[3]} == 9'b100110001) ? PALETTE4:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[3]} == 9'b100110101) ? PALETTE5:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[3]} == 9'b100111001) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[3]} == 9'b100111101) ? PALETTE7:
//SG6
({COCO,VID_CONT[3],MODE6, CHAR_LATCH_0[7], SG6,CHAR_LATCH_0[1]} == 7'b1010100) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[1]} == 9'b101010101) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[1]} == 9'b101011101) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[1]} == 9'b101110101) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[1]} == 9'b101111101) ? PALETTE7:
({COCO,VID_CONT[3],MODE6, CHAR_LATCH_0[7], SG6,CHAR_LATCH_0[3]} == 7'b1010010) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[3]} == 9'b101010011) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[3]} == 9'b101011011) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[3]} == 9'b101110011) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[3]} == 9'b101111011) ? PALETTE7:
({COCO,VID_CONT[3],MODE6, CHAR_LATCH_0[7], SG6,CHAR_LATCH_0[5]} == 7'b1010000) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[5]} == 9'b101010001) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[5]} == 9'b101011001) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[5]} == 9'b101110001) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[5]} == 9'b101111001) ? PALETTE7:
//Lowres graphics
//2 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7]} == 5'b11100) ? PALETTE8:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7]} == 5'b11101) ? PALETTE9:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7]} == 5'b11110) ? PALETTEA:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7]} == 5'b11111) ? PALETTEB:
//4 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7:6]} == 6'b110000) ? PALETTE0:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7:6]} == 6'b110001) ? PALETTE1:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7:6]} == 6'b110010) ? PALETTE2:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7:6]} == 6'b110011) ? PALETTE3:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7:6]} == 6'b110100) ? PALETTE4:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7:6]} == 6'b110101) ? PALETTE5:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7:6]} == 6'b110110) ? PALETTE6:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[7:6]} == 6'b110111) ? PALETTE7:
// Hires GR
//2 color
({COCO,BP,CRES,CHAR_LATCH_0[7]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[7]} == 5'b01001) ? PALETTE1:
//4 Color
({COCO,BP,CRES,CHAR_LATCH_0[7:6]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[7:6]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[7:6]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[7:6]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_0[7:4]} == 8'b01101111) ? PALETTEF:
// 256 color mode
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_0[3:0]:
PALETTE8;
assign PIXEL10 =
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_0[7:4]:
4'h0;
assign PIXEL1 =
//CoCo1 Text
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[6]} == 5'b10001) ? PALETTEC:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[6]} == 5'b10000) ? PALETTED:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[6]} == 5'b10101) ? PALETTEE:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[6]} == 5'b10100) ? PALETTEF:
// HR Text
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[10:8]}==7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[10:8]}==7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[10:8]}==7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[10:8]}==7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[10:8]}==7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[10:8]}==7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[10:8]}==7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER3[6],CHAR_LATCH_0[10:8]}==7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER3[6]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[6]}==4'b0000) ? PALETTED:
//SG4, SG8, SG12, SG24
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7], SIX,CHAR_LATCH_0[0]} == 6'b100110) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[0]} == 9'b100100011) ? PALETTE0:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[0]} == 9'b100100111) ? PALETTE1:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[0]} == 9'b100101011) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[0]} == 9'b100101111) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[0]} == 9'b100110011) ? PALETTE4:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[0]} == 9'b100110111) ? PALETTE5:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[0]} == 9'b100111011) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[0]} == 9'b100111111) ? PALETTE7:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7], SIX,CHAR_LATCH_0[2]} == 6'b100100) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[2]} == 9'b100100001) ? PALETTE0:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[2]} == 9'b100100101) ? PALETTE1:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[2]} == 9'b100101001) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[2]} == 9'b100101101) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[2]} == 9'b100110001) ? PALETTE4:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[2]} == 9'b100110101) ? PALETTE5:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[2]} == 9'b100111001) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CHAR_LATCH_0[7:4],SIX,CHAR_LATCH_0[2]} == 9'b100111101) ? PALETTE7:
//SG6
({COCO,VID_CONT[3],MODE6, CHAR_LATCH_0[7], SG6,CHAR_LATCH_0[0]} == 7'b1010100) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[0]} == 9'b101010101) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[0]} == 9'b101011101) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[0]} == 9'b101110101) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[0]} == 9'b101111101) ? PALETTE7:
({COCO,VID_CONT[3],MODE6, CHAR_LATCH_0[7], SG6,CHAR_LATCH_0[2]} == 7'b1010010) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[2]} == 9'b101010011) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[2]} == 9'b101011011) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[2]} == 9'b101110011) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[2]} == 9'b101111011) ? PALETTE7:
({COCO,VID_CONT[3],MODE6, CHAR_LATCH_0[7], SG6,CHAR_LATCH_0[4]} == 7'b1010000) ? PALETTE8:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[4]} == 9'b101010001) ? PALETTE2:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[4]} == 9'b101011001) ? PALETTE3:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[4]} == 9'b101110001) ? PALETTE6:
({COCO,VID_CONT[3],MODE6,CSS,CHAR_LATCH_0[7:6],SG6,CHAR_LATCH_0[4]} == 9'b101111001) ? PALETTE7:
// Lowres graphics
// 2 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[6]} == 5'b11100) ? PALETTE8:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[6]} == 5'b11101) ? PALETTE9:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[6]} == 5'b11110) ? PALETTEA:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[6]} == 5'b11111) ? PALETTEB:
// 4 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5:4]} == 6'b110000) ? PALETTE0:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5:4]} == 6'b110001) ? PALETTE1:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5:4]} == 6'b110010) ? PALETTE2:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5:4]} == 6'b110011) ? PALETTE3:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5:4]} == 6'b110100) ? PALETTE4:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5:4]} == 6'b110101) ? PALETTE5:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5:4]} == 6'b110110) ? PALETTE6:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5:4]} == 6'b110111) ? PALETTE7:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[6]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[6]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_0[5:4]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[5:4]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[5:4]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[5:4]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_0[3:0]} == 8'b01101111) ? PALETTEF:
// 256 color mode
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_0[11:8]:
PALETTE8;
assign PIXEL11 =
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_0[15:12]:
4'h0;
assign PIXEL2 =
//CoCo1 Text
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[5]} == 5'b10001) ? PALETTEC:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[5]} == 5'b10000) ? PALETTED:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[5]} == 5'b10101) ? PALETTEE:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[5]} == 5'b10100) ? PALETTEF:
// HR Text
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[10:8]}==7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[10:8]}==7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[10:8]}==7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[10:8]}==7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[10:8]}==7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[10:8]}==7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[10:8]}==7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER3[5],CHAR_LATCH_0[10:8]}==7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER3[5]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[5]}==4'b0000) ? PALETTED:
// Lowres graphics
// 2 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5]} == 5'b11100) ? PALETTE8:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5]} == 5'b11101) ? PALETTE9:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5]} == 5'b11110) ? PALETTEA:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[5]} == 5'b11111) ? PALETTEB:
// 4 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3:2]} == 6'b110000) ? PALETTE0:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3:2]} == 6'b110001) ? PALETTE1:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3:2]} == 6'b110010) ? PALETTE2:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3:2]} == 6'b110011) ? PALETTE3:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3:2]} == 6'b110100) ? PALETTE4:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3:2]} == 6'b110101) ? PALETTE5:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3:2]} == 6'b110110) ? PALETTE6:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3:2]} == 6'b110111) ? PALETTE7:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[5]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[5]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_0[3:2]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[3:2]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[3:2]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[3:2]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_0[15:12]} == 8'b01101111) ? PALETTEF:
// 256 color mode
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_1[3:0]:
PALETTE8;
assign PIXEL12 =
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_1[7:4]:
4'h0;
assign PIXEL3 =
//CoCo1 Text
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[4]} == 5'b10001) ? PALETTEC:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[4]} == 5'b10000) ? PALETTED:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[4]} == 5'b10101) ? PALETTEE:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[4]} == 5'b10100) ? PALETTEF:
// HR Text
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[10:8]}==7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[10:8]}==7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[10:8]}==7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[10:8]}==7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[10:8]}==7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[10:8]}==7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[10:8]}==7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER3[4],CHAR_LATCH_0[10:8]}==7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER3[4]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[4]}==4'b0000) ? PALETTED:
// Lowres graphics
// 2 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[4]} == 5'b11100) ? PALETTE8:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[4]} == 5'b11101) ? PALETTE9:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[4]} == 5'b11110) ? PALETTEA:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[4]} == 5'b11111) ? PALETTEB:
// 4 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1:0]} == 6'b110000) ? PALETTE0:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1:0]} == 6'b110001) ? PALETTE1:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1:0]} == 6'b110010) ? PALETTE2:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1:0]} == 6'b110011) ? PALETTE3:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1:0]} == 6'b110100) ? PALETTE4:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1:0]} == 6'b110101) ? PALETTE5:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1:0]} == 6'b110110) ? PALETTE6:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1:0]} == 6'b110111) ? PALETTE7:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[4]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[4]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_0[1:0]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[1:0]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[1:0]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[1:0]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_0[11:8]} == 8'b01101111) ? PALETTEF:
// 256 color mode
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_1[11:8]:
PALETTE8;
assign PIXEL13 =
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_1[15:12]:
4'h0;
assign PIXEL4 =
//CoCo1 Text
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[3]} == 5'b10001) ? PALETTEC:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[3]} == 5'b10000) ? PALETTED:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[3]} == 5'b10101) ? PALETTEE:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[3]} == 5'b10100) ? PALETTEF:
// HR Text
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[10:8]}==7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[10:8]}==7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[10:8]}==7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[10:8]}==7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[10:8]}==7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[10:8]}==7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[10:8]}==7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER3[3],CHAR_LATCH_0[10:8]}==7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER3[3]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[3]}==4'b0000) ? PALETTED:
// Lowres graphics
// 2 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3]} == 5'b11100) ? PALETTE8:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3]} == 5'b11101) ? PALETTE9:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3]} == 5'b11110) ? PALETTEA:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[3]} == 5'b11111) ? PALETTEB:
// 4 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[15:14]} == 6'b110000) ? PALETTE0:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[15:14]} == 6'b110001) ? PALETTE1:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[15:14]} == 6'b110010) ? PALETTE2:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[15:14]} == 6'b110011) ? PALETTE3:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[15:14]} == 6'b110100) ? PALETTE4:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[15:14]} == 6'b110101) ? PALETTE5:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[15:14]} == 6'b110110) ? PALETTE6:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[15:14]} == 6'b110111) ? PALETTE7:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[3]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[3]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_0[15:14]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[15:14]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[15:14]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[15:14]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_1[7:4]} == 8'b01101111) ? PALETTEF:
// 256 color mode
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_2[3:0]:
PALETTE8;
assign PIXEL14 =
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_2[7:4]:
4'h0;
assign PIXEL5 =
//CoCo1 Text
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[2]} == 5'b10001) ? PALETTEC:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[2]} == 5'b10000) ? PALETTED:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[2]} == 5'b10101) ? PALETTEE:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[2]} == 5'b10100) ? PALETTEF:
// HR Text
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[10:8]}==7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[10:8]}==7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[10:8]}==7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[10:8]}==7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[10:8]}==7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[10:8]}==7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[10:8]}==7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER3[2],CHAR_LATCH_0[10:8]}==7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER3[2]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[2]}==4'b0000) ? PALETTED:
// Lowres graphics
// 2 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[2]} == 5'b11100) ? PALETTE8:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[2]} == 5'b11101) ? PALETTE9:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[2]} == 5'b11110) ? PALETTEA:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[2]} == 5'b11111) ? PALETTEB:
// 4 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[13:12]} == 6'b110000) ? PALETTE0:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[13:12]} == 6'b110001) ? PALETTE1:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[13:12]} == 6'b110010) ? PALETTE2:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[13:12]} == 6'b110011) ? PALETTE3:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[13:12]} == 6'b110100) ? PALETTE4:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[13:12]} == 6'b110101) ? PALETTE5:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[13:12]} == 6'b110110) ? PALETTE6:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[13:12]} == 6'b110111) ? PALETTE7:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[2]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[2]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_0[13:12]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[13:12]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[13:12]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[13:12]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_1[3:0]} == 8'b01101111) ? PALETTEF:
// 256 color mode
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_2[11:8]:
PALETTE8;
assign PIXEL15 =
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_2[15:12]:
4'h0;
assign PIXEL6 =
//CoCo1 Text
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[1]} == 5'b10001) ? PALETTEC:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[1]} == 5'b10000) ? PALETTED:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[1]} == 5'b10101) ? PALETTEE:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[1]} == 5'b10100) ? PALETTEF:
// HR Text
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[10:8]}==7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[10:8]}==7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[10:8]}==7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[10:8]}==7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[10:8]}==7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[10:8]}==7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[10:8]}==7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER3[1],CHAR_LATCH_0[10:8]}==7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER3[1]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[1]}==4'b0000) ? PALETTED:
// Lowres graphics
// 2 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1]} == 5'b11100) ? PALETTE8:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1]} == 5'b11101) ? PALETTE9:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1]} == 5'b11110) ? PALETTEA:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[1]} == 5'b11111) ? PALETTEB:
// 4 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[11:10]} == 6'b110000) ? PALETTE0:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[11:10]} == 6'b110001) ? PALETTE1:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[11:10]} == 6'b110010) ? PALETTE2:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[11:10]} == 6'b110011) ? PALETTE3:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[11:10]} == 6'b110100) ? PALETTE4:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[11:10]} == 6'b110101) ? PALETTE5:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[11:10]} == 6'b110110) ? PALETTE6:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[11:10]} == 6'b110111) ? PALETTE7:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[1]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[1]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_0[11:10]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[11:10]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[11:10]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[11:10]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_1[15:12]} == 8'b01101111) ? PALETTEF:
// 256 color mode
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_3[3:0]:
PALETTE8;
assign PIXEL16 =
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_3[7:4]:
4'h0;
assign PIXEL7 =
//CoCo1 Text
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[0]} == 5'b10001) ? PALETTEC:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[0]} == 5'b10000) ? PALETTED:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[0]} == 5'b10101) ? PALETTEE:
({COCO,VID_CONT[3],CSS,CHAR_LATCH_0[7],CHARACTER3[0]} == 5'b10100) ? PALETTEF:
// HR Text
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[10:8]}==7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[10:8]}==7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[10:8]}==7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[10:8]}==7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[10:8]}==7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[10:8]}==7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[10:8]}==7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER3[0],CHAR_LATCH_0[10:8]}==7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER3[0]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER3[0]}==4'b0000) ? PALETTED:
// Lowres graphics
// 2 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[0]} == 5'b11100) ? PALETTE8:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[0]} == 5'b11101) ? PALETTE9:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[0]} == 5'b11110) ? PALETTEA:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[0]} == 5'b11111) ? PALETTEB:
// 4 color
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[9:8]} == 6'b110000) ? PALETTE0:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[9:8]} == 6'b110001) ? PALETTE1:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[9:8]} == 6'b110010) ? PALETTE2:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[9:8]} == 6'b110011) ? PALETTE3:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[9:8]} == 6'b110100) ? PALETTE4:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[9:8]} == 6'b110101) ? PALETTE5:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[9:8]} == 6'b110110) ? PALETTE6:
({COCO,VID_CONT[3],VID_CONT[0],CSS,CHAR_LATCH_0[9:8]} == 6'b110111) ? PALETTE7:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[0]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[0]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_0[9:8]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[9:8]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_0[9:8]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_0[9:8]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_1[11:8]} == 8'b01101111) ? PALETTEF:
// 256 color mode
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_3[11:8]:
PALETTE8;
assign PIXEL17 =
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_3[15:12]:
4'h0;
assign PIXEL8 =
// HR Text
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[10:8]}== 7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[10:8]}== 7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[10:8]}== 7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[10:8]}== 7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[10:8]}== 7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[10:8]}== 7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[10:8]}== 7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER4[7],CHAR_LATCH_1[10:8]}== 7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER1[7]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER1[7]}==4'b0000) ? PALETTED:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[15]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[15]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_1[7:6]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[7:6]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[7:6]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[7:6]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_2[7:4]} == 8'b01101111) ? PALETTEF:
// 256 color mode
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_4[3:0]:
`endif
PALETTE8;
assign PIXEL18 =
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_4[7:4]:
`endif
4'h0;
assign PIXEL9 =
// HR Text
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[10:8]}== 7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[10:8]}== 7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[10:8]}== 7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[10:8]}== 7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[10:8]}== 7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[10:8]}== 7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[10:8]}== 7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER4[6],CHAR_LATCH_1[10:8]}== 7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER1[6]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER1[6]}==4'b0000) ? PALETTED:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[14]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[14]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_1[5:4]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[5:4]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[5:4]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[5:4]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_2[3:0]} == 8'b01101111) ? PALETTEF:
// 256 color mode
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_4[11:8]:
`endif
PALETTE8;
assign PIXEL19 =
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_4[15:12]:
`endif
4'h0;
assign PIXELA =
// HR Text
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[10:8]}== 7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[10:8]}== 7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[10:8]}== 7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[10:8]}== 7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[10:8]}== 7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[10:8]}== 7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[10:8]}== 7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER4[5],CHAR_LATCH_1[10:8]}== 7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER1[5]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER1[5]}==4'b0000) ? PALETTED:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[13]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[13]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_1[3:2]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[3:2]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[3:2]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[3:2]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_2[15:12]} == 8'b01101111) ? PALETTEF:
// 256 color mode
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_5[3:0]:
`endif
PALETTE8;
assign PIXEL1A =
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_5[7:4]:
`endif
4'h0;
assign PIXELB =
// HR Text
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[10:8]}== 7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[10:8]}== 7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[10:8]}== 7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[10:8]}== 7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[10:8]}== 7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[10:8]}== 7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[10:8]}== 7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER4[4],CHAR_LATCH_1[10:8]}== 7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER1[4]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER1[4]}==4'b0000) ? PALETTED:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[12]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[12]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_1[1:0]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[1:0]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[1:0]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[1:0]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_2[11:8]} == 8'b01101111) ? PALETTEF:
// 256 color mode
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_5[11:8]:
`endif
PALETTE8;
assign PIXEL1B =
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_5[15:12]:
`endif
4'h0;
assign PIXELC =
// HR Text
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[10:8]}== 7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[10:8]}== 7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[10:8]}== 7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[10:8]}== 7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[10:8]}== 7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[10:8]}== 7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[10:8]}== 7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER4[3],CHAR_LATCH_1[10:8]}== 7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER1[3]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER1[3]}==4'b0000) ? PALETTED:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[11]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[11]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_1[15:14]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[15:14]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[15:14]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[15:14]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_3[7:4]} == 8'b01101111) ? PALETTEF:
// 256 color mode
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_6[3:0]:
`endif
PALETTE8;
assign PIXEL1C =
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_6[7:4]:
`endif
4'h0;
assign PIXELD =
// HR Text
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[10:8]}== 7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[10:8]}== 7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[10:8]}== 7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[10:8]}== 7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[10:8]}== 7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[10:8]}== 7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[10:8]}== 7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER4[2],CHAR_LATCH_1[10:8]}== 7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER1[2]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER1[2]}==4'b0000) ? PALETTED:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[10]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[10]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_1[13:12]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[13:12]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[13:12]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[13:12]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_3[3:0]} == 8'b01101111) ? PALETTEF:
// 256 color mode
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_6[11:8]:
`endif
PALETTE8;
assign PIXEL1D =
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_6[15:12]:
`endif
4'h0;
assign PIXELE =
// HR Text
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[10:8]}== 7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[10:8]}== 7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[10:8]}== 7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[10:8]}== 7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[10:8]}== 7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[10:8]}== 7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[10:8]}== 7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER4[1],CHAR_LATCH_1[10:8]}== 7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER1[1]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER1[1]}==4'b0000) ? PALETTED:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[9]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[9]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_1[11:10]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[11:10]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[11:10]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[11:10]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_3[15:12]} == 8'b01101111) ? PALETTEF:
// 256 color mode
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_7[3:0]:
`endif
PALETTE8;
assign PIXEL1E =
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_7[7:4]:
`endif
4'h0;
assign PIXELF =
// HR Text
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[13:11]}==7'b0011000) ? PALETTE8:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[13:11]}==7'b0011001) ? PALETTE9:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[13:11]}==7'b0011010) ? PALETTEA:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[13:11]}==7'b0011011) ? PALETTEB:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[13:11]}==7'b0011100) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[13:11]}==7'b0011101) ? PALETTED:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[13:11]}==7'b0011110) ? PALETTEE:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[13:11]}==7'b0011111) ? PALETTEF:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[10:8]}== 7'b0010000) ? PALETTE0:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[10:8]}== 7'b0010001) ? PALETTE1:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[10:8]}== 7'b0010010) ? PALETTE2:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[10:8]}== 7'b0010011) ? PALETTE3:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[10:8]}== 7'b0010100) ? PALETTE4:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[10:8]}== 7'b0010101) ? PALETTE5:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[10:8]}== 7'b0010110) ? PALETTE6:
({COCO,BP,CRES[0],CHARACTER4[0],CHAR_LATCH_1[10:8]}== 7'b0010111) ? PALETTE7:
// XTEXT
({COCO,BP,CRES[0],CHARACTER1[0]}==4'b0001) ? PALETTEC:
({COCO,BP,CRES[0],CHARACTER1[0]}==4'b0000) ? PALETTED:
// Hires GR
// 2 color
({COCO,BP,CRES,CHAR_LATCH_0[8]} == 5'b01000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_0[8]} == 5'b01001) ? PALETTE1:
// 4 Color
({COCO,BP,CRES,CHAR_LATCH_1[9:8]} == 6'b010100) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_1[9:8]} == 6'b010101) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_1[9:8]} == 6'b010110) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_1[9:8]} == 6'b010111) ? PALETTE3:
// 16 color
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01100000) ? PALETTE0:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01100001) ? PALETTE1:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01100010) ? PALETTE2:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01100011) ? PALETTE3:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01100100) ? PALETTE4:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01100101) ? PALETTE5:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01100110) ? PALETTE6:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01100111) ? PALETTE7:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01101000) ? PALETTE8:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01101001) ? PALETTE9:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01101010) ? PALETTEA:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01101011) ? PALETTEB:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01101100) ? PALETTEC:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01101101) ? PALETTED:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01101110) ? PALETTEE:
({COCO,BP,CRES,CHAR_LATCH_3[11:8]} == 8'b01101111) ? PALETTEF:
// 256 color mode
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_7[11:8]:
`endif
PALETTE8;
assign PIXEL1F =
`ifndef NEW_SRAM
({COCO,BP,CRES} == 4'b0111) ? CHAR_LATCH_7[15:12]:
`endif
4'h0;
/*****************************************************************************
* Generate RGB
******************************************************************************/
assign PIXEL_ORDER =
// CoCo1 Text
({COCO,VID_CONT[3],CHAR_LATCH_0[7],CHAR_LATCH_0[7]} == 4'b1000) ? 2'b01: // 2x HR pixels per text pixel
// HR Text
// 32 / 40
({COCO,BP,HRES[2],CRES[0]} == 4'b0001) ? 2'b01: // 2x HR pixels per text pixel
// 64 / 80
({COCO,BP,HRES[2],CRES[0]} == 4'b0011) ? 2'b00: // 1x HR pixel per text pixel
// XTEXT
// 32 / 40
({COCO,BP,HRES[2],CRES[0]} == 4'b0000) ? 2'b01: // 2x HR pixels per text pixel
// 64 / 80
({COCO,BP,HRES[2],CRES[0]} == 4'b0010) ? 2'b00: // 1x HR pixel per text pixel
// SG Modes
// SG4, SG6, SG8, SG12, SG24
({COCO,VID_CONT[3],CHAR_LATCH_0[7]} == 3'b101) ? 2'b11: // 8x HR pixels per SG pixel
// SG6
// ({COCO,VID_CONT[3],VID_CONT[0]} == 3'b101) ? 2'b11: // 8x HR pixels per SG pixel
// Lowres graphics
// 64
({COCO,VID_CONT[3:0]} == 5'b11000) ? 2'b11: // 8x HR pixels per SG pixel
// 128
// ({COCO,VID_CONT[3:0]} == 5'b11001) ? 2'b10: // 4x HR pixels per SG pixel
// ({COCO,VID_CONT[3:0]} == 5'b11010) ? 2'b10: // 4x HR pixels per SG pixel
// ({COCO,VID_CONT[3:0]} == 5'b11011) ? 2'b10: // 4x HR pixels per SG pixel
// ({COCO,VID_CONT[3:0]} == 5'b11100) ? 2'b10: // 4x HR pixels per SG pixel
// ({COCO,VID_CONT[3:0]} == 5'b11101) ? 2'b10: // 4x HR pixels per SG pixel
// ({COCO,VID_CONT[3:0]} == 5'b11110) ? 2'b10: // 4x HR pixels per SG pixel
// 256
({COCO,VID_CONT[3:0]} == 5'b11111) ? 2'b01: // 2x HR pixels per SG pixel
// HR GR
// 16/20 bytes/line 2 color
// ({COCO,BP,HRES[2:1],CRES} == 6'b010000) ? 2'b10: // 4x HR pixels per G pixel
// 16/20 bytes/line 4 color
({COCO,BP,HRES[3:1],CRES} == 7'b0100001) ? 2'b11: // 8x HR pixels per G pixel
// 16/20 bytes/line 16 color, implemented later
// ({COCO,BP,HRES[2:1],CRES} == 6'b010010) ? 2'b00: // 16x HR pixels per G pixel, not implemented
// 16/20 bytes/line 256 color, implemented later
// ({COCO,BP,HRES[2:1],CRES} == 6'b010011) ? 2'b01: // 32x HR pixels per G pixel, not implemented
// 32/40 bytes/line 2 color
({COCO,BP,HRES[3:1],CRES} == 7'b0100100) ? 2'b01: // 2x HR pixels per G pixel
// 32/40 bytes/line 4 color
// ({COCO,BP,HRES[2:1],CRES} == 6'b010101) ? 2'b10: // 4x HR pixels per G pixel
// 32/40 bytes/line 16 color
({COCO,BP,HRES[3:1],CRES} == 7'b0100110) ? 2'b11: // 8x HR pixels per G pixel
// 32/40 bytes/line 256 color
// ({COCO,BP,HRES[2:1],CRES} == 6'b010111) ? 2'b00: // 16x HR pixels per G pixel, not implemented
// 64/80 bytes/line 2 color
({COCO,BP,HRES[3:1],CRES} == 7'b0101000) ? 2'b00: // 1x HR pixels per G pixel
// 64/80 bytes/line 4 color
({COCO,BP,HRES[3:1],CRES} == 7'b0101001) ? 2'b01: // 2x HR pixels per G pixel
// 64/80 bytes/line 16 color
// ({COCO,BP,HRES[2:1],CRES} == 6'b011010) ? 2'b10: // 4x HR pixels per G pixel
// 64/80 bytes/line 256 color
({COCO,BP,HRES[3:1],CRES} == 7'b0101011) ? 2'b11: // 8x HR pixels per G pixel
// 128/160 bytes/line 2 color
// ({COCO,BP,HRES[2:1],CRES} == 6'b011100) ? 2'b11: // 0.5x HR pixels per G pixel, not implemented
// 128/160 bytes/line 4 color
({COCO,BP,HRES[3:1],CRES} == 7'b0101101) ? 2'b00: // 1x HR pixels per G pixel
// 128/160 bytes/line 16 color
({COCO,BP,HRES[3:1],CRES} == 7'b0101110) ? 2'b01: // 2x HR pixels per G pixel
// 128/160 bytes/line 256 color
// ({COCO,BP,HRES[2:1],CRES} == 6'b011111) ? 2'b10: // 4x HR pixels per G pixel
// 256/320 bytes/line 16 color
({COCO,BP,HRES[3:1],CRES} == 7'b0110010) ? 2'b00: // 1x HR pixels per G pixel
// 256/320 bytes/line 256 color
({COCO,BP,HRES[3:1],CRES} == 7'b0110011) ? 2'b01: // 2x HR pixels per G pixel
`ifndef NEW_SRAM
// 512/640 bytes/line 256 color
({COCO,BP,HRES[3:1],CRES} == 7'b0110111) ? 2'b00: // 1x HR pixels per G pixel
`endif
2'b10; // 4x HR pixels per ? pixel, DEFAULT
always @ (negedge PIX_CLK)
begin
if(PIXEL_COUNT[3:0] == 4'b1111)
begin
case (PIXEL_ORDER)
default: // 2'b10 4x pixels
begin
// 7 6 5 4 3 2 1 0
COLOR7[7:0] <= {PIXEL11[3],PIXEL11[3],PIXEL11[3],PIXEL11[3],PIXEL10[3],PIXEL10[3],PIXEL10[3],PIXEL10[3]};
COLOR6[7:0] <= {PIXEL11[2],PIXEL11[2],PIXEL11[2],PIXEL11[2],PIXEL10[2],PIXEL10[2],PIXEL10[2],PIXEL10[2]};
COLOR5[7:0] <= {PIXEL11[1],PIXEL11[1],PIXEL11[1],PIXEL11[1],PIXEL10[1],PIXEL10[1],PIXEL10[1],PIXEL10[1]};
COLOR4[7:0] <= {PIXEL11[0],PIXEL11[0],PIXEL11[0],PIXEL11[0],PIXEL10[0],PIXEL10[0],PIXEL10[0],PIXEL10[0]};
COLOR3[7:0] <= { PIXEL1[3], PIXEL1[3], PIXEL1[3], PIXEL1[3], PIXEL0[3], PIXEL0[3], PIXEL0[3], PIXEL0[3]};
COLOR2[7:0] <= { PIXEL1[2], PIXEL1[2], PIXEL1[2], PIXEL1[2], PIXEL0[2], PIXEL0[2], PIXEL0[2], PIXEL0[2]};
COLOR1[7:0] <= { PIXEL1[1], PIXEL1[1], PIXEL1[1], PIXEL1[1], PIXEL0[1], PIXEL0[1], PIXEL0[1], PIXEL0[1]};
COLOR0[7:0] <= { PIXEL1[0], PIXEL1[0], PIXEL1[0], PIXEL1[0], PIXEL0[0], PIXEL0[0], PIXEL0[0], PIXEL0[0]};
end
2'b00: // 1x pixels
begin
// 7 6 5 4 3 2 1 0
COLOR7[7:0] <= {PIXEL17[3],PIXEL16[3],PIXEL15[3],PIXEL14[3],PIXEL13[3],PIXEL12[3],PIXEL11[3],PIXEL10[3]};
COLOR6[7:0] <= {PIXEL17[2],PIXEL16[2],PIXEL15[2],PIXEL14[2],PIXEL13[2],PIXEL12[2],PIXEL11[2],PIXEL10[2]};
COLOR5[7:0] <= {PIXEL17[1],PIXEL16[1],PIXEL15[1],PIXEL14[1],PIXEL13[1],PIXEL12[1],PIXEL11[1],PIXEL10[1]};
COLOR4[7:0] <= {PIXEL17[0],PIXEL16[0],PIXEL15[0],PIXEL14[0],PIXEL13[0],PIXEL12[0],PIXEL11[0],PIXEL10[0]};
COLOR3[7:0] <= {PIXEL7[3], PIXEL6[3], PIXEL5[3], PIXEL4[3], PIXEL3[3], PIXEL2[3], PIXEL1[3], PIXEL0[3]};
COLOR2[7:0] <= {PIXEL7[2], PIXEL6[2], PIXEL5[2], PIXEL4[2], PIXEL3[2], PIXEL2[2], PIXEL1[2], PIXEL0[2]};
COLOR1[7:0] <= {PIXEL7[1], PIXEL6[1], PIXEL5[1], PIXEL4[1], PIXEL3[1], PIXEL2[1], PIXEL1[1], PIXEL0[1]};
COLOR0[7:0] <= {PIXEL7[0], PIXEL6[0], PIXEL5[0], PIXEL4[0], PIXEL3[0], PIXEL2[0], PIXEL1[0], PIXEL0[0]};
end
2'b01: // 2x pixels
begin
// 7 6 5 4 3 2 1 0
COLOR7[7:0] <= {PIXEL13[3],PIXEL13[3],PIXEL12[3],PIXEL12[3],PIXEL11[3],PIXEL11[3],PIXEL10[3],PIXEL10[3]};
COLOR6[7:0] <= {PIXEL13[2],PIXEL13[2],PIXEL12[2],PIXEL12[2],PIXEL11[2],PIXEL11[2],PIXEL10[2],PIXEL10[2]};
COLOR5[7:0] <= {PIXEL13[1],PIXEL13[1],PIXEL12[1],PIXEL12[1],PIXEL11[1],PIXEL11[1],PIXEL10[1],PIXEL10[1]};
COLOR4[7:0] <= {PIXEL13[0],PIXEL13[0],PIXEL12[0],PIXEL12[0],PIXEL11[0],PIXEL11[0],PIXEL10[0],PIXEL10[0]};
COLOR3[7:0] <= {PIXEL3[3], PIXEL3[3], PIXEL2[3], PIXEL2[3], PIXEL1[3], PIXEL1[3], PIXEL0[3], PIXEL0[3]};
COLOR2[7:0] <= {PIXEL3[2], PIXEL3[2], PIXEL2[2], PIXEL2[2], PIXEL1[2], PIXEL1[2], PIXEL0[2], PIXEL0[2]};
COLOR1[7:0] <= {PIXEL3[1], PIXEL3[1], PIXEL2[1], PIXEL2[1], PIXEL1[1], PIXEL1[1], PIXEL0[1], PIXEL0[1]};
COLOR0[7:0] <= {PIXEL3[0], PIXEL3[0], PIXEL2[0], PIXEL2[0], PIXEL1[0], PIXEL1[0], PIXEL0[0], PIXEL0[0]};
end
2'b11: // 8x pixels
begin
// 7 6 5 4 3 2 1 0
COLOR7[7:0] <= {PIXEL10[3],PIXEL10[3],PIXEL10[3],PIXEL10[3],PIXEL10[3],PIXEL10[3],PIXEL10[3],PIXEL10[3]};
COLOR6[7:0] <= {PIXEL10[2],PIXEL10[2],PIXEL10[2],PIXEL10[2],PIXEL10[2],PIXEL10[2],PIXEL10[2],PIXEL10[2]};
COLOR5[7:0] <= {PIXEL10[1],PIXEL10[1],PIXEL10[1],PIXEL10[1],PIXEL10[1],PIXEL10[1],PIXEL10[1],PIXEL10[1]};
COLOR4[7:0] <= {PIXEL10[0],PIXEL10[0],PIXEL10[0],PIXEL10[0],PIXEL10[0],PIXEL10[0],PIXEL10[0],PIXEL10[0]};
COLOR3[7:0] <= {PIXEL0[3], PIXEL0[3], PIXEL0[3], PIXEL0[3], PIXEL0[3], PIXEL0[3], PIXEL0[3], PIXEL0[3]};
COLOR2[7:0] <= {PIXEL0[2], PIXEL0[2], PIXEL0[2], PIXEL0[2], PIXEL0[2], PIXEL0[2], PIXEL0[2], PIXEL0[2]};
COLOR1[7:0] <= {PIXEL0[1], PIXEL0[1], PIXEL0[1], PIXEL0[1], PIXEL0[1], PIXEL0[1], PIXEL0[1], PIXEL0[1]};
COLOR0[7:0] <= {PIXEL0[0], PIXEL0[0], PIXEL0[0], PIXEL0[0], PIXEL0[0], PIXEL0[0], PIXEL0[0], PIXEL0[0]};
end
endcase
end
else
begin
if(PIXEL_COUNT[3:0] == 4'b0001)
begin
case (PIXEL_ORDER)
default: // 2'b10 4x pixels
begin
// 15 14 13 12 11 10 9 8
COLOR7[15:8] <= {PIXEL13[3],PIXEL13[3],PIXEL13[3],PIXEL13[3],PIXEL12[3],PIXEL12[3],PIXEL12[3],PIXEL12[3]};
COLOR6[15:8] <= {PIXEL13[2],PIXEL13[2],PIXEL13[2],PIXEL13[2],PIXEL12[2],PIXEL12[2],PIXEL12[2],PIXEL12[2]};
COLOR5[15:8] <= {PIXEL13[1],PIXEL13[1],PIXEL13[1],PIXEL13[1],PIXEL12[1],PIXEL12[1],PIXEL12[1],PIXEL12[1]};
COLOR4[15:8] <= {PIXEL13[0],PIXEL13[0],PIXEL13[0],PIXEL13[0],PIXEL12[0],PIXEL12[0],PIXEL12[0],PIXEL12[0]};
COLOR3[15:8] <= {PIXEL3[3], PIXEL3[3], PIXEL3[3], PIXEL3[3], PIXEL2[3], PIXEL2[3], PIXEL2[3], PIXEL2[3]};
COLOR2[15:8] <= {PIXEL3[2], PIXEL3[2], PIXEL3[2], PIXEL3[2], PIXEL2[2], PIXEL2[2], PIXEL2[2], PIXEL2[2]};
COLOR1[15:8] <= {PIXEL3[1], PIXEL3[1], PIXEL3[1], PIXEL3[1], PIXEL2[1], PIXEL2[1], PIXEL2[1], PIXEL2[1]};
COLOR0[15:8] <= {PIXEL3[0], PIXEL3[0], PIXEL3[0], PIXEL3[0], PIXEL2[0], PIXEL2[0], PIXEL2[0], PIXEL2[0]};
end
2'b00: // 1x pixels
begin
// 15 14 13 12 11 10 9 8
COLOR7[15:8] <= {PIXEL1F[3],PIXEL1E[3],PIXEL1D[3],PIXEL1C[3],PIXEL1B[3],PIXEL1A[3],PIXEL19[3],PIXEL18[3]};
COLOR6[15:8] <= {PIXEL1F[2],PIXEL1E[2],PIXEL1D[2],PIXEL1C[2],PIXEL1B[2],PIXEL1A[2],PIXEL19[2],PIXEL18[2]};
COLOR5[15:8] <= {PIXEL1F[1],PIXEL1E[1],PIXEL1D[1],PIXEL1C[1],PIXEL1B[1],PIXEL1A[1],PIXEL19[1],PIXEL18[1]};
COLOR4[15:8] <= {PIXEL1F[0],PIXEL1E[0],PIXEL1D[0],PIXEL1C[0],PIXEL1B[0],PIXEL1A[0],PIXEL19[0],PIXEL18[0]};
COLOR3[15:8] <= {PIXELF[3], PIXELE[3], PIXELD[3], PIXELC[3], PIXELB[3], PIXELA[3], PIXEL9[3], PIXEL8[3]};
COLOR2[15:8] <= {PIXELF[2], PIXELE[2], PIXELD[2], PIXELC[2], PIXELB[2], PIXELA[2], PIXEL9[2], PIXEL8[2]};
COLOR1[15:8] <= {PIXELF[1], PIXELE[1], PIXELD[1], PIXELC[1], PIXELB[1], PIXELA[1], PIXEL9[1], PIXEL8[1]};
COLOR0[15:8] <= {PIXELF[0], PIXELE[0], PIXELD[0], PIXELC[0], PIXELB[0], PIXELA[0], PIXEL9[0], PIXEL8[0]};
end
2'b01: // 2x pixels
begin
// 15 15 13 12 11 10 9 8
COLOR7[15:8] <= {PIXEL17[3],PIXEL17[3],PIXEL16[3],PIXEL16[3],PIXEL15[3],PIXEL15[3],PIXEL14[3],PIXEL14[3]};
COLOR6[15:8] <= {PIXEL17[2],PIXEL17[2],PIXEL16[2],PIXEL16[2],PIXEL15[2],PIXEL15[2],PIXEL14[2],PIXEL14[2]};
COLOR5[15:8] <= {PIXEL17[1],PIXEL17[1],PIXEL16[1],PIXEL16[1],PIXEL15[1],PIXEL15[1],PIXEL14[1],PIXEL14[1]};
COLOR4[15:8] <= {PIXEL17[0],PIXEL17[0],PIXEL16[0],PIXEL16[0],PIXEL15[0],PIXEL15[0],PIXEL14[0],PIXEL14[0]};
COLOR3[15:8] <= {PIXEL7[3], PIXEL7[3], PIXEL6[3], PIXEL6[3], PIXEL5[3], PIXEL5[3], PIXEL4[3], PIXEL4[3]};
COLOR2[15:8] <= {PIXEL7[2], PIXEL7[2], PIXEL6[2], PIXEL6[2], PIXEL5[2], PIXEL5[2], PIXEL4[2], PIXEL4[2]};
COLOR1[15:8] <= {PIXEL7[1], PIXEL7[1], PIXEL6[1], PIXEL6[1], PIXEL5[1], PIXEL5[1], PIXEL4[1], PIXEL4[1]};
COLOR0[15:8] <= {PIXEL7[0], PIXEL7[0], PIXEL6[0], PIXEL6[0], PIXEL5[0], PIXEL5[0], PIXEL4[0], PIXEL4[0]};
end
2'b11: // 8x pixels
begin
// 15 14 13 12
COLOR7[15:8] <= {PIXEL11[3],PIXEL11[3],PIXEL11[3],PIXEL11[3],PIXEL11[3],PIXEL11[3],PIXEL11[3],PIXEL11[3]};
COLOR6[15:8] <= {PIXEL11[2],PIXEL11[2],PIXEL11[2],PIXEL11[2],PIXEL11[2],PIXEL11[2],PIXEL11[2],PIXEL11[2]};
COLOR5[15:8] <= {PIXEL11[1],PIXEL11[1],PIXEL11[1],PIXEL11[1],PIXEL11[1],PIXEL11[1],PIXEL11[1],PIXEL11[1]};
COLOR4[15:8] <= {PIXEL11[0],PIXEL11[0],PIXEL11[0],PIXEL11[0],PIXEL11[0],PIXEL11[0],PIXEL11[0],PIXEL11[0]};
COLOR3[15:8] <= {PIXEL1[3], PIXEL1[3], PIXEL1[3], PIXEL1[3], PIXEL1[3], PIXEL1[3], PIXEL1[3], PIXEL1[3]};
COLOR2[15:8] <= {PIXEL1[2], PIXEL1[2], PIXEL1[2], PIXEL1[2], PIXEL1[2], PIXEL1[2], PIXEL1[2], PIXEL1[2]};
COLOR1[15:8] <= {PIXEL1[1], PIXEL1[1], PIXEL1[1], PIXEL1[1], PIXEL1[1], PIXEL1[1], PIXEL1[1], PIXEL1[1]};
COLOR0[15:8] <= {PIXEL1[0], PIXEL1[0], PIXEL1[0], PIXEL1[0], PIXEL1[0], PIXEL1[0], PIXEL1[0], PIXEL1[0]};
end
endcase
end
end
end
assign BORDER =
({COCO,VID_CONT[3]} == 2'b10) ? 9'h100: //Black
({COCO,VID_CONT[3],VID_CONT[0],CSS} == 4'b1111) ? {5'h00,PALETTEB}:
({COCO,VID_CONT[3],VID_CONT[0],CSS} == 4'b1110) ? {5'h00,PALETTE9}:
({COCO,VID_CONT[3],VID_CONT[0],CSS} == 4'b1101) ? {5'h00,PALETTE4}:
({COCO,VID_CONT[3],VID_CONT[0],CSS} == 4'b1100) ? {5'h00,PALETTE0}:
9'h010; //BDR_PAL
always @ (negedge PIX_CLK)
begin
COLOR <= CCOLOR;
end
assign CCOLOR[8] = ({VBLANKING,HBLANKING} == 2'b00) ? ({COCO,BP,CRES} == 4'b0111): //normal screen area
({(VBORDER&HBORDER),(VBLANKING|HBLANKING)} == 2'b11) ? BORDER[8]: // Border
1'b1; // Retrace
assign CCOLOR[7] = ({VBLANKING,HBLANKING} == 2'b00) ? COLOR7[PIXEL_COUNT[3:0]]: // Normal screeen area
({(VBORDER&HBORDER),(VBLANKING|HBLANKING)} == 2'b11) ? BORDER[7]: // Border
1'b0; // Retrace
assign CCOLOR[6] = ({VBLANKING,HBLANKING} == 2'b00) ? COLOR6[PIXEL_COUNT[3:0]]: // Normal screeen area
({(VBORDER&HBORDER),(VBLANKING|HBLANKING)} == 2'b11) ? BORDER[6]: // Border
1'b0; // Retrace
assign CCOLOR[5] = ({VBLANKING,HBLANKING} == 2'b00) ? COLOR5[PIXEL_COUNT[3:0]]: // Normal screeen area
({(VBORDER&HBORDER),(VBLANKING|HBLANKING)} == 2'b11) ? BORDER[5]: // Border
1'b0; // Retrace
assign CCOLOR[4] = ({VBLANKING,HBLANKING} == 2'b00) ? COLOR4[PIXEL_COUNT[3:0]]: // Normal screeen area
({(VBORDER&HBORDER),(VBLANKING|HBLANKING)} == 2'b11) ? BORDER[4]: // Border
1'b0; // Retrace
assign CCOLOR[3] = ({VBLANKING,HBLANKING} == 2'b00) ? COLOR3[PIXEL_COUNT[3:0]]: // Normal screeen area
({(VBORDER&HBORDER),(VBLANKING|HBLANKING)} == 2'b11) ? BORDER[3]: // Border
1'b0; // Retrace
assign CCOLOR[2] = ({VBLANKING,HBLANKING} == 2'b00) ? COLOR2[PIXEL_COUNT[3:0]]: // Normal screeen area
({(VBORDER&HBORDER),(VBLANKING|HBLANKING)} == 2'b11) ? BORDER[2]: // Border
1'b0; // Retrace
assign CCOLOR[1] = ({VBLANKING,HBLANKING} == 2'b00) ? COLOR1[PIXEL_COUNT[3:0]]: // Normal screeen area
({(VBORDER&HBORDER),(VBLANKING|HBLANKING)} == 2'b11) ? BORDER[1]: // Border
1'b0; // Retrace
assign CCOLOR[0] = ({VBLANKING,HBLANKING} == 2'b00) ? COLOR0[PIXEL_COUNT[3:0]]: // Normal screeen area
({(VBORDER&HBORDER),(VBLANKING|HBLANKING)} == 2'b11) ? BORDER[0]: // Border
1'b0; // Retrace
/*****************************************************************************
* Count pixels across each line
* 32 and 40 character modes use double wide pixels
******************************************************************************/
always @ (negedge PIX_CLK)
begin
case(PIXEL_COUNT)
10'd013:
begin
PIXEL_COUNT <= 10'd014;
HBORDER <= 1'b1; //Turn on border for 640 mode
end
10'd015: // Turn off horizontal blanking so first character can be displayed
begin
HBLANKING <= 1'b0; // Turn off blanking
HBORDER <= 1'b1;
HSYNC <= 1'b1; // Not H Sync
PIXEL_COUNT <= 10'd016; // Next step
end
10'd527: // 512 + 16 -1
begin
HBORDER <= 1'b1;
HSYNC <= 1'b1; // Not H Sync
if(MODE_256) // 512 mode
begin
HBLANKING <= 1'b1; // Turn on blanking
PIXEL_COUNT <= 10'd592; // 528 + 64 = 528 + 128 - 64
end
else // 640 mode
begin
HBLANKING <= 1'b0; // Leave blanking off
PIXEL_COUNT <= 10'd528;
end
end
10'd655: // 640 + 16 - 1
begin
HBLANKING <= 1'b1; // Blanking on
HBORDER <= 1'b1;
HSYNC <= 1'b1; // Not H Sync
PIXEL_COUNT <= 10'd656;
end
10'd657: // 648 + 24 - 1
begin
HBLANKING <= 1'b1;
HBORDER <= 1'b0;
HSYNC <= 1'b1;
// added 6 to make total = 794 instead of 800
PIXEL_COUNT <= 10'd664;
end
10'd671: // 648 + 24 - 1
begin
HBLANKING <= 1'b1;
HBORDER <= 1'b0;
HSYNC <= 1'b0; // Turn on Sync
PIXEL_COUNT <= 10'd672;
end
10'd767: // 672 + 104 - 1
begin
HBLANKING <= 1'b1;
HSYNC <= 1'b1; // SYNC OFF
if(~MODE_256) // 640 mode
PIXEL_COUNT <= 10'd832; // skip 64
else
PIXEL_COUNT <= 10'd768;
end
10'd799:
begin
PIXEL_COUNT <= 10'd800;
HBORDER <= 1'b1; //Turn on Border for 256 pixel mode
end
10'd863: // 864 - 1
begin
PIXEL_COUNT <= 10'd000;
HSYNC <= 1'b1;
SYNC_FLAG <= LINE[0]; // Every other line with the first visable line has sync
// ~SYNC_FLAG;
end
default:
begin
PIXEL_COUNT <= PIXEL_COUNT + 1'b1;
end
endcase
// end
end
/*****************************************************************************
* Switches to set different video modes
******************************************************************************/
assign MODE_256 = (COCO == 1'b1) ? 1'b1:
({COCO, HRES[0]}== 2'b00) ? 1'b1:
1'b0;
/*
00x=one line per row
010=two lines per row
011=eight lines per row
100=nine lines per row
101=ten lines per row
110=eleven lines per row
111=*infinite lines per row
*/
assign LINES_ROW = ({COCO,LPR[2:1]}==3'b000) ? 4'b0000: // 1
({COCO,LPR}== 4'b0010) ? 4'b0001: // 2
({COCO,LPR}== 4'b0011) ? 4'b0111: // 8
({COCO,LPR}== 4'b0100) ? 4'b1000: // 9
({COCO,LPR}== 4'b0101) ? 4'b1001: // 10
({COCO,LPR}== 4'b0110) ? 4'b1010: // 11
({COCO,LPR}== 4'b0111) ? 4'b1111: // Infinite
({COCO, V} == 4'b1001) ? 4'b0010: // 3
({COCO, V} == 4'b1010) ? 4'b0010: // 3
({COCO, V} == 4'b1011) ? 4'b0001: // 2
({COCO, V} == 4'b1100) ? 4'b0001: // 2
({COCO, V} == 4'b1101) ? 4'b0000: // 1
({COCO, V} == 4'b1110) ? 4'b0000: // 1
4'b1011; // 12
assign SIX = (V!=3'b000) ? SIX_R: //SG8, SG12, SG24
(VLPR[3:2] == 2'b00) ? 1'b0: //0-3 SG4 Mode
(VLPR[3:1] == 3'b010) ? 1'b0: //4-5 SG4 Mode
1'b1;
assign SG6 = VLPR[3:2];
/*****************************************************************************
* Calculates the starting address of the row
******************************************************************************/
assign SCREEN_OFF =
// CoCo1 low res graphics (64 pixels / 2 bytes)
({COCO,V[0]} == 2'b11) ? ROW_ADD + 10'd16:
//HR Text
({HVEN,COCO} == 2'b10) ? ROW_ADD + 10'd256:
({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0000000)? ROW_ADD + 10'd32:
({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0000001)? ROW_ADD + 10'd40:
({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0000010)? ROW_ADD + 10'd64:
({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0000011)? ROW_ADD + 10'd80:
({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0000100)? ROW_ADD + 10'd64:
({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0000101)? ROW_ADD + 10'd80:
({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0000110)? ROW_ADD + 10'd128:
({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0000111)? ROW_ADD + 10'd160:
//No text greater than 80 characters / row
//({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0001000)? ROW_ADD + 9'd256:
//({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0001001)? ROW_ADD + 9'd320:
//({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0001010)? ROW_ADD + 9'd512:
//({HVEN,COCO,BP,HRES[3:2],CRES[0],HRES[0]}==6'b0001011)? ROW_ADD + 9'd640:
//HR Graphics
({HVEN,COCO,BP,HRES}==7'b0010000) ? ROW_ADD + 10'd16:
({HVEN,COCO,BP,HRES}==7'b0010001) ? ROW_ADD + 10'd20:
({HVEN,COCO,BP,HRES}==7'b0010010) ? ROW_ADD + 10'd32:
({HVEN,COCO,BP,HRES}==7'b0010011) ? ROW_ADD + 10'd40:
({HVEN,COCO,BP,HRES}==7'b0010100) ? ROW_ADD + 10'd64:
({HVEN,COCO,BP,HRES}==7'b0010101) ? ROW_ADD + 10'd80:
({HVEN,COCO,BP,HRES}==7'b0010110) ? ROW_ADD + 10'd128:
({HVEN,COCO,BP,HRES}==7'b0010111) ? ROW_ADD + 10'd160:
({HVEN,COCO,BP,HRES}==7'b0011000) ? ROW_ADD + 10'd256:
({HVEN,COCO,BP,HRES}==7'b0011001) ? ROW_ADD + 10'd320:
({HVEN,COCO,BP,HRES}==7'b0011010) ? ROW_ADD + 10'd512:
({HVEN,COCO,BP,HRES}==7'b0011011) ? ROW_ADD + 10'd640:
// CoCo1 Text
ROW_ADD + 9'd32;
/*****************************************************************************
* Keeps track of how many lines are in each row.
* There are 2X lines per coco line.
******************************************************************************/
always @ (negedge HSYNC or posedge VBLANKING)
begin
if(VBLANKING)
begin
SIX_R <= 1'b0;
SG_LINES <= 3'b000;
NUM_ROW <= LINES_ROW;
UNDERLINE <= 1'b0;
COCO1_VLPR <= 4'h0;
if(~COCO)
begin
ROW_ADD <= {SCRN_START_HSB,SCRN_START_MSB,SCRN_START_LSB,3'h0} + {HOR_OFFSET, 1'b0};
if(BP) // Vertical Fine Scroll not in graphics modes
begin
VLPR <= 4'h0;
end
else
begin
if(LINES_ROW > VERT_FIN_SCRL)
begin
VLPR <= VERT_FIN_SCRL;
end
else
begin
VLPR <= LINES_ROW;
end
end
end
else
begin
VLPR <= 4'h0;
ROW_ADD <= {SCRN_START_HSB,SCRN_START_MSB[7:5],VERT,SCRN_START_LSB[5:0],3'h0} + {HOR_OFFSET, 1'b0};
end
end
else
begin
if(LINE[0] || HLPR)
begin
if (COCO1_VLPR == 4'HB)
COCO1_VLPR <= 4'H0;
else
COCO1_VLPR <= COCO1_VLPR + 1'b1;
case (VLPR)
4'h0: // Pixel row 1
begin
if(NUM_ROW == 4'b0000) // 1 line
begin
ROW_ADD <= SCREEN_OFF;
if(SG_LINES == 3'b101) // SG24
begin
SIX_R <= !SIX_R;
SG_LINES <= 3'b000;
end
else
begin
SG_LINES <= SG_LINES + 1'b1;
end
end
if((NUM_ROW == 4'b0000) || ({BP, LINES_ROW} == 5'b11111)) // 1 or infinite graphics mode
begin
NUM_ROW <= LINES_ROW;
VLPR <= 4'h0;
end
else
begin
VLPR <= 4'h1;
end
if(NUM_ROW == 4'b0001) // 2 lines per row
UNDERLINE <= 1'b1; // Set underline
else
UNDERLINE <= 1'b0;
end
4'h1: // Pixel row 2
begin
UNDERLINE <= 1'b0;
if(NUM_ROW == 4'b0001) // 2 line per row
begin
NUM_ROW <= LINES_ROW;
ROW_ADD <= SCREEN_OFF;
VLPR <= 4'h0;
if(SG_LINES == 3'b010) // SG12
begin
SIX_R <= !SIX_R;
SG_LINES <= 3'b000;
end
else
begin
SG_LINES <= SG_LINES + 1'b1;
end
end
else
begin
VLPR <= 4'h2;
end
end
4'h2: // Pixel row 3
begin
UNDERLINE <= 1'b0;
if(NUM_ROW == 4'b0010) // 3 line per row
begin
NUM_ROW <= LINES_ROW;
ROW_ADD <= SCREEN_OFF;
VLPR <= 4'h0;
if(SG_LINES == 3'b001) // SG12
begin
SIX_R <= !SIX_R;
SG_LINES <= 3'b000;
end
else
begin
SG_LINES <= SG_LINES + 1'b1;
end
end
else
begin
VLPR <= 4'h3;
end
end
4'h5: // pixel row 6
begin
VLPR <= 4'h6;
end
4'h6: // Pixel Row 7
begin
VLPR <= 4'h7;
if(NUM_ROW == 4'b0111) // 8
UNDERLINE <= 1'b1; // Set underline
else
UNDERLINE <= 1'b0;
end
4'h7: // Pixel Row 8
begin
if(NUM_ROW == 4'b0111) // 8
begin
NUM_ROW <= LINES_ROW;
ROW_ADD <= SCREEN_OFF;
VLPR <= 4'h0;
end
else
begin
VLPR <= 4'h8;
end
if(NUM_ROW == 4'b1000) // 9
UNDERLINE <= 1'b1; // Set underline
else
UNDERLINE <= 1'b0;
end
4'h8: // Pixel Row 9
begin
if(NUM_ROW == 4'b1000) // 9
begin
NUM_ROW <= LINES_ROW;
ROW_ADD <= SCREEN_OFF;
VLPR <= 4'h0;
end
else
begin
VLPR <= 4'h9;
end
if(NUM_ROW == 4'b1001) // 10
UNDERLINE <= 1'b1; // Set underline
else
UNDERLINE <= 1'b0;
end
4'h9: // Pixel Row 10
begin
if(NUM_ROW == 4'b1001) // 10
begin
NUM_ROW <= LINES_ROW;
ROW_ADD <= SCREEN_OFF;
VLPR <= 4'h0;
end
else
begin
VLPR <= 4'hA;
end
if(NUM_ROW == 4'b1010) // 11
UNDERLINE <= 1'b1;
else
UNDERLINE <= 1'b0;
end
4'hA: // Pixel Row 11
begin
VLPR <= 4'hB;
if(NUM_ROW == 4'b1011) // 12
UNDERLINE <= 1'b1;
else
UNDERLINE <= 1'b0;
end
4'hB, // Pixel Row 12
4'hC,
4'hD,
4'hE,
4'hF:
begin
UNDERLINE <= 1'b0;
if(NUM_ROW != 4'b1111) // Infinite
begin
ROW_ADD <= SCREEN_OFF;
NUM_ROW <= LINES_ROW;
VLPR <= 4'h0;
end
end
default:
begin
VLPR <= VLPR + 1'b1;
end
endcase
end
end
end
/* case (VLPR)
4'h0: // Pixel row 1
begin
NUM_ROW <= LINES_ROW;
LINE_NUM <= 4'h1;
SIX <= 1'b0;
if(NUM_ROW == 3'b000) // 1 line
begin
ROW_ADD <= SCREEN_OFF;
end
if((NUM_ROW == 3'b000) || ({BP, LINES_ROW} == 4'b1111)) // 1 or infinite graphics mode
VLPR <= 4'h0;
else
if(NUM_ROW == 3'b010) // 3 lines goto underline
VLPR <= 4'hA;
else
if(NUM_ROW == 3'b001) // 2 lines goto last line
begin
VLPR <= 4'hB;
UNDERLINE <= 1'b1; // Set underline
end
else
VLPR <= 5'd1;
end
4'h5: //Pixel Row 6
begin
LINE_NUM <= 4'h6;
SIX <= 1'b1;
if(NUM_ROW == 3'b011) // 8
begin
VLPR <= 4'hA;
end
else
begin
VLPR <= 4'h6;
end
end
4'h6: // Pixel Row 7
begin
LINE_NUM <= 4'h7;
if(NUM_ROW == 3'b100) // 9
begin
VLPR <= 4'hA;
end
else
begin
VLPR <= 4'h7;
end
end
4'h7: // Pixel Row 8
begin
LINE_NUM <= 4'h8;
if(NUM_ROW == 3'b101) // 10
begin
VLPR <= 4'hA;
end
else
begin
VLPR <= 4'h8;
end
end
4'hA: // Pixel row 11
begin
LINE_NUM <= LINE_NUM + 1'b1;
UNDERLINE <= 1'b1;
VLPR <= 4'hB;
end
4'hB: // Pixel row 12
begin
UNDERLINE <= 1'b0;
SIX <= 1'b0;
if(LINES_ROW != 3'b111) // Infininte
begin
LINE_NUM <= 4'h0;
ROW_ADD <= SCREEN_OFF;
VLPR <= 4'h0;
end
end
default:
begin
LINE_NUM <= LINE_NUM + 1'b1;
VLPR <= VLPR + 1'b1;
end
endcase
*/
/*****************************************************************************
* Keeps track of the real line number, and controls VSYNC and VBlanking.
* Does not keep track of the lines per row
*
* LPR Lines
*
* 00 or COCO =1 192
* 01 200
* 10 210
* 11 225 (25*9)
******************************************************************************/
always @ (negedge HSYNC or negedge RESET_N)
begin
if(~RESET_N)
begin
LINE <= 10'd00;
VBLANKING <= 1'b0;
VSYNC <= 1'b1;
end
else
case (LINE)
// Video
10'd383: // End of 192 line display
begin
LINE <= 10'd384;
if((LPF == 2'b00) || (COCO == 1'b1)) // Standard COCO modes are always 192
begin
VBLANKING <= 1'b1;
end
end
10'd399: // End of 200 line display
begin
LINE <= 10'd400;
if(LPF == 2'b01)
begin
VBLANKING <= 1'b1;
end
end
10'd419: // End of 210 line display
begin
LINE <= 10'd420;
if(LPF == 2'b10)
begin
VBLANKING <= 1'b1;
end
end
10'd449: // End of 225 line display
begin
LINE <= 10'd450;
VBLANKING <= 1'b1;
end
//End of Border, start of porch
10'd467:
begin
VBORDER <= 1'b0;
LINE <= 10'd468;
end
// End of Porch, start of sync
// Start of Sync is a 1 to 0
10'd473:
begin
LINE <= 10'd474;
VSYNC <= 1'b0; // Sync on
end
// End of sync, start of blanking and porch
10'd479:
begin
LINE <= 10'd480;
VSYNC <= 1'b1; // Sync off
end
// End of porch, start of border
10'd505:
begin
LINE <= 10'd506;
VBORDER <= 1'b1;
end
// End of border, start of video, restart state machine
10'd523: // -1
begin
LINE <= 10'd000;
VBLANKING <= 1'b0;
end
default:
begin
LINE <= LINE + 1'b1;
end
endcase
end
endmodule
|
/**
* Hydra - An open source strand lighting controller
* (c) 2013-2014 Jon Evans <[email protected]>
* Released under the MIT License -- see LICENSE.txt for details.
*
* address_generator_tb.v - Testbench for memory address generator module
*/
`timescale 1ns / 1ps
module address_generator_tb;
parameter MEM_ADDR_WIDTH = 24;
parameter STRAND_PARAM_WIDTH = 16;
reg clk = 0;
reg rst_n = 1;
reg [STRAND_PARAM_WIDTH-1:0] strand_offset = 0;
reg [STRAND_PARAM_WIDTH-1:0] strand_idx = 0;
reg [STRAND_PARAM_WIDTH-1:0] strand_length = 100;
wire [MEM_ADDR_WIDTH-1:0] addr;
// UUT
address_generator #(MEM_ADDR_WIDTH) ag_inst (
.clk(clk),
.rst_n(rst_n),
.strand_offset(strand_offset),
.strand_idx(strand_idx),
.strand_length(strand_length),
.addr(addr)
);
// Clock process
always #10 clk = !clk;
// Test process
initial begin
$dumpfile("address_generator_tb.vcd");
$dumpvars(0, address_generator_tb);
#10 rst_n = 0;
#10 rst_n = 1;
#10 strand_offset = 320;
strand_idx = 1;
#20 strand_idx = 50;
#20 strand_idx = 99;
#20 strand_idx = 100;
#20 strand_idx = 101;
#20 strand_offset = 640;
strand_idx = 1;
#20 strand_idx = 50;
#20 strand_idx = 100;
#20 strand_idx = 101;
#500 $finish;
end
endmodule
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Register file
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* RF */
module uparc_reg_file(
clk,
nrst,
rs,
rs_data,
rt,
rt_data,
rd,
rd_data
);
`include "uparc_reg_names.vh"
input wire clk;
input wire nrst;
/* First source register */
input wire [`UPARC_REGNO_WIDTH-1:0] rs;
output reg [`UPARC_REG_WIDTH-1:0] rs_data;
/* Second source register */
input wire [`UPARC_REGNO_WIDTH-1:0] rt;
output reg [`UPARC_REG_WIDTH-1:0] rt_data;
/* Destination register */
input wire [`UPARC_REGNO_WIDTH-1:0] rd;
input wire [`UPARC_REG_WIDTH-1:0] rd_data;
/* Registers */
reg [`UPARC_REG_WIDTH-1:0] r1;
reg [`UPARC_REG_WIDTH-1:0] r2;
reg [`UPARC_REG_WIDTH-1:0] r3;
reg [`UPARC_REG_WIDTH-1:0] r4;
reg [`UPARC_REG_WIDTH-1:0] r5;
reg [`UPARC_REG_WIDTH-1:0] r6;
reg [`UPARC_REG_WIDTH-1:0] r7;
reg [`UPARC_REG_WIDTH-1:0] r8;
reg [`UPARC_REG_WIDTH-1:0] r9;
reg [`UPARC_REG_WIDTH-1:0] r10;
reg [`UPARC_REG_WIDTH-1:0] r11;
reg [`UPARC_REG_WIDTH-1:0] r12;
reg [`UPARC_REG_WIDTH-1:0] r13;
reg [`UPARC_REG_WIDTH-1:0] r14;
reg [`UPARC_REG_WIDTH-1:0] r15;
reg [`UPARC_REG_WIDTH-1:0] r16;
reg [`UPARC_REG_WIDTH-1:0] r17;
reg [`UPARC_REG_WIDTH-1:0] r18;
reg [`UPARC_REG_WIDTH-1:0] r19;
reg [`UPARC_REG_WIDTH-1:0] r20;
reg [`UPARC_REG_WIDTH-1:0] r21;
reg [`UPARC_REG_WIDTH-1:0] r22;
reg [`UPARC_REG_WIDTH-1:0] r23;
reg [`UPARC_REG_WIDTH-1:0] r24;
reg [`UPARC_REG_WIDTH-1:0] r25;
reg [`UPARC_REG_WIDTH-1:0] r26;
reg [`UPARC_REG_WIDTH-1:0] r27;
reg [`UPARC_REG_WIDTH-1:0] r28;
reg [`UPARC_REG_WIDTH-1:0] r29;
reg [`UPARC_REG_WIDTH-1:0] r30;
reg [`UPARC_REG_WIDTH-1:0] r31;
wire [`UPARC_REG_WIDTH-1:0] r0_wire;
wire [`UPARC_REG_WIDTH-1:0] r1_wire;
wire [`UPARC_REG_WIDTH-1:0] r2_wire;
wire [`UPARC_REG_WIDTH-1:0] r3_wire;
wire [`UPARC_REG_WIDTH-1:0] r4_wire;
wire [`UPARC_REG_WIDTH-1:0] r5_wire;
wire [`UPARC_REG_WIDTH-1:0] r6_wire;
wire [`UPARC_REG_WIDTH-1:0] r7_wire;
wire [`UPARC_REG_WIDTH-1:0] r8_wire;
wire [`UPARC_REG_WIDTH-1:0] r9_wire;
wire [`UPARC_REG_WIDTH-1:0] r10_wire;
wire [`UPARC_REG_WIDTH-1:0] r11_wire;
wire [`UPARC_REG_WIDTH-1:0] r12_wire;
wire [`UPARC_REG_WIDTH-1:0] r13_wire;
wire [`UPARC_REG_WIDTH-1:0] r14_wire;
wire [`UPARC_REG_WIDTH-1:0] r15_wire;
wire [`UPARC_REG_WIDTH-1:0] r16_wire;
wire [`UPARC_REG_WIDTH-1:0] r17_wire;
wire [`UPARC_REG_WIDTH-1:0] r18_wire;
wire [`UPARC_REG_WIDTH-1:0] r19_wire;
wire [`UPARC_REG_WIDTH-1:0] r20_wire;
wire [`UPARC_REG_WIDTH-1:0] r21_wire;
wire [`UPARC_REG_WIDTH-1:0] r22_wire;
wire [`UPARC_REG_WIDTH-1:0] r23_wire;
wire [`UPARC_REG_WIDTH-1:0] r24_wire;
wire [`UPARC_REG_WIDTH-1:0] r25_wire;
wire [`UPARC_REG_WIDTH-1:0] r26_wire;
wire [`UPARC_REG_WIDTH-1:0] r27_wire;
wire [`UPARC_REG_WIDTH-1:0] r28_wire;
wire [`UPARC_REG_WIDTH-1:0] r29_wire;
wire [`UPARC_REG_WIDTH-1:0] r30_wire;
wire [`UPARC_REG_WIDTH-1:0] r31_wire;
assign r0_wire = {(`UPARC_REG_WIDTH){1'b0}}; /* Always 0 */
assign r1_wire = (rd == R1 ? rd_data : r1);
assign r2_wire = (rd == R2 ? rd_data : r2);
assign r3_wire = (rd == R3 ? rd_data : r3);
assign r4_wire = (rd == R4 ? rd_data : r4);
assign r5_wire = (rd == R5 ? rd_data : r5);
assign r6_wire = (rd == R6 ? rd_data : r6);
assign r7_wire = (rd == R7 ? rd_data : r7);
assign r8_wire = (rd == R8 ? rd_data : r8);
assign r9_wire = (rd == R9 ? rd_data : r9);
assign r10_wire = (rd == R10 ? rd_data : r10);
assign r11_wire = (rd == R11 ? rd_data : r11);
assign r12_wire = (rd == R12 ? rd_data : r12);
assign r13_wire = (rd == R13 ? rd_data : r13);
assign r14_wire = (rd == R14 ? rd_data : r14);
assign r15_wire = (rd == R15 ? rd_data : r15);
assign r16_wire = (rd == R16 ? rd_data : r16);
assign r17_wire = (rd == R17 ? rd_data : r17);
assign r18_wire = (rd == R18 ? rd_data : r18);
assign r19_wire = (rd == R19 ? rd_data : r19);
assign r20_wire = (rd == R20 ? rd_data : r20);
assign r21_wire = (rd == R21 ? rd_data : r21);
assign r22_wire = (rd == R22 ? rd_data : r22);
assign r23_wire = (rd == R23 ? rd_data : r23);
assign r24_wire = (rd == R24 ? rd_data : r24);
assign r25_wire = (rd == R25 ? rd_data : r25);
assign r26_wire = (rd == R26 ? rd_data : r26);
assign r27_wire = (rd == R27 ? rd_data : r27);
assign r28_wire = (rd == R28 ? rd_data : r28);
assign r29_wire = (rd == R29 ? rd_data : r29);
assign r30_wire = (rd == R30 ? rd_data : r30);
assign r31_wire = (rd == R31 ? rd_data : r31);
always @(*)
begin
case(rs)
R0: rs_data = r0_wire;
R1: rs_data = r1_wire;
R2: rs_data = r2_wire;
R3: rs_data = r3_wire;
R4: rs_data = r4_wire;
R5: rs_data = r5_wire;
R6: rs_data = r6_wire;
R7: rs_data = r7_wire;
R8: rs_data = r8_wire;
R9: rs_data = r9_wire;
R10: rs_data = r10_wire;
R11: rs_data = r11_wire;
R12: rs_data = r12_wire;
R13: rs_data = r13_wire;
R14: rs_data = r14_wire;
R15: rs_data = r15_wire;
R16: rs_data = r16_wire;
R17: rs_data = r17_wire;
R18: rs_data = r18_wire;
R19: rs_data = r19_wire;
R20: rs_data = r20_wire;
R21: rs_data = r21_wire;
R22: rs_data = r22_wire;
R23: rs_data = r23_wire;
R24: rs_data = r24_wire;
R25: rs_data = r25_wire;
R26: rs_data = r26_wire;
R27: rs_data = r27_wire;
R28: rs_data = r28_wire;
R29: rs_data = r29_wire;
R30: rs_data = r30_wire;
R31: rs_data = r31_wire;
endcase
end
always @(*)
begin
case(rt)
R0: rt_data = r0_wire;
R1: rt_data = r1_wire;
R2: rt_data = r2_wire;
R3: rt_data = r3_wire;
R4: rt_data = r4_wire;
R5: rt_data = r5_wire;
R6: rt_data = r6_wire;
R7: rt_data = r7_wire;
R8: rt_data = r8_wire;
R9: rt_data = r9_wire;
R10: rt_data = r10_wire;
R11: rt_data = r11_wire;
R12: rt_data = r12_wire;
R13: rt_data = r13_wire;
R14: rt_data = r14_wire;
R15: rt_data = r15_wire;
R16: rt_data = r16_wire;
R17: rt_data = r17_wire;
R18: rt_data = r18_wire;
R19: rt_data = r19_wire;
R20: rt_data = r20_wire;
R21: rt_data = r21_wire;
R22: rt_data = r22_wire;
R23: rt_data = r23_wire;
R24: rt_data = r24_wire;
R25: rt_data = r25_wire;
R26: rt_data = r26_wire;
R27: rt_data = r27_wire;
R28: rt_data = r28_wire;
R29: rt_data = r29_wire;
R30: rt_data = r30_wire;
R31: rt_data = r31_wire;
endcase
end
always @(posedge clk or negedge nrst)
begin
if (!nrst)
begin
r1 <= {(`UPARC_REG_WIDTH){1'b0}};
r2 <= {(`UPARC_REG_WIDTH){1'b0}};
r3 <= {(`UPARC_REG_WIDTH){1'b0}};
r4 <= {(`UPARC_REG_WIDTH){1'b0}};
r5 <= {(`UPARC_REG_WIDTH){1'b0}};
r6 <= {(`UPARC_REG_WIDTH){1'b0}};
r7 <= {(`UPARC_REG_WIDTH){1'b0}};
r8 <= {(`UPARC_REG_WIDTH){1'b0}};
r9 <= {(`UPARC_REG_WIDTH){1'b0}};
r10 <= {(`UPARC_REG_WIDTH){1'b0}};
r11 <= {(`UPARC_REG_WIDTH){1'b0}};
r12 <= {(`UPARC_REG_WIDTH){1'b0}};
r13 <= {(`UPARC_REG_WIDTH){1'b0}};
r14 <= {(`UPARC_REG_WIDTH){1'b0}};
r15 <= {(`UPARC_REG_WIDTH){1'b0}};
r16 <= {(`UPARC_REG_WIDTH){1'b0}};
r17 <= {(`UPARC_REG_WIDTH){1'b0}};
r18 <= {(`UPARC_REG_WIDTH){1'b0}};
r19 <= {(`UPARC_REG_WIDTH){1'b0}};
r20 <= {(`UPARC_REG_WIDTH){1'b0}};
r21 <= {(`UPARC_REG_WIDTH){1'b0}};
r22 <= {(`UPARC_REG_WIDTH){1'b0}};
r23 <= {(`UPARC_REG_WIDTH){1'b0}};
r24 <= {(`UPARC_REG_WIDTH){1'b0}};
r25 <= {(`UPARC_REG_WIDTH){1'b0}};
r26 <= {(`UPARC_REG_WIDTH){1'b0}};
r27 <= {(`UPARC_REG_WIDTH){1'b0}};
r28 <= {(`UPARC_REG_WIDTH){1'b0}};
r29 <= {(`UPARC_REG_WIDTH){1'b0}};
r30 <= {(`UPARC_REG_WIDTH){1'b0}};
r31 <= {(`UPARC_REG_WIDTH){1'b0}};
end
else
begin
case(rd)
R0: /* ignore */;
R1: r1 <= rd_data;
R2: r2 <= rd_data;
R3: r3 <= rd_data;
R4: r4 <= rd_data;
R5: r5 <= rd_data;
R6: r6 <= rd_data;
R7: r7 <= rd_data;
R8: r8 <= rd_data;
R9: r9 <= rd_data;
R10: r10 <= rd_data;
R11: r11 <= rd_data;
R12: r12 <= rd_data;
R13: r13 <= rd_data;
R14: r14 <= rd_data;
R15: r15 <= rd_data;
R16: r16 <= rd_data;
R17: r17 <= rd_data;
R18: r18 <= rd_data;
R19: r19 <= rd_data;
R20: r20 <= rd_data;
R21: r21 <= rd_data;
R22: r22 <= rd_data;
R23: r23 <= rd_data;
R24: r24 <= rd_data;
R25: r25 <= rd_data;
R26: r26 <= rd_data;
R27: r27 <= rd_data;
R28: r28 <= rd_data;
R29: r29 <= rd_data;
R30: r30 <= rd_data;
R31: r31 <= rd_data;
endcase
end
end
endmodule /* uparc_reg_file */
|
`timescale 1ns / 1ps
module TOP(
input fpga_clk,
input cpu_reset,
output [18:0] sram_adr_o,
inout [15:0] sram_dat_io,
output sram_ce_on,
output sram_we_on,
output sram_oe_on,
output sram_lbe_on,
output sram_ube_on,
output led0,
output led1,
output led2,
input switch0
);
wire iack, istb;
wire [31:0] idat;
wire [63:0] idat_wide, iadr;
wire [63:0] ddati, ddato, dadr;
wire dwe, dcyc, dstb, dsigned, dack;
wire [1:0] dsiz;
wire [63:0] xdato, xdati, xadr;
wire xwe, xcyc, xstb, xsigned, xack;
wire [1:0] xsiz;
wire [15:0] sdato, sdati;
wire [63:0] sadr, sdati_wide;
wire swe, scyc, sstb, ssigned, sack;
wire ssiz;
wire [63:0] wbdato;
wire [7:0] wbsel;
wire [15:0] wbdati;
wire ram_ack, remex_ack, gpia_ack, rom_ack;
wire [15:0] ram_dat_o, remex_dat_o, gpia_dat_o, rom_dat_o;
wire [15:0] gpia_outputs;
assign sdati = sdati_wide[15:0];
// Main clock is 100MHz on icoBoard.
// Reduce it to no more than 25MHz for CPU.
reg [6:0] divider = 0;
reg cpu_clk = 0;
always @(posedge fpga_clk) begin
divider <= divider + 1;
if(divider == 7'd 50) begin
cpu_clk <= ~cpu_clk;
divider <= 0;
end
end
PolarisCPU cpu(
.clk_i(cpu_clk),
.reset_i(cpu_reset),
.fence_o(),
.trap_o(),
.cause_o(),
.mepc_o(),
.mpie_o(),
.mie_o(),
.irq_i(1'b0),
.iack_i(iack),
.idat_i(idat),
.iadr_o(iadr),
.istb_o(istb),
.dack_i(dack),
.ddat_i(ddati),
.ddat_o(ddato),
.dadr_o(dadr),
.dwe_o(dwe),
.dcyc_o(dcyc),
.dstb_o(dstb),
.dsiz_o(dsiz),
.dsigned_o(dsigned),
.cadr_o(),
.coe_o(),
.cwe_o(),
.cvalid_i(1'b0),
.cdat_o(),
.cdat_i(64'd0)
);
// Converge Harvard buses to Von Neumann
assign idat = idat_wide[31:0];
arbiter arb(
.clk_i(cpu_clk),
.reset_i(cpu_reset),
.idat_i(64'd0),
.iadr_i(iadr),
.iwe_i(1'b0),
.icyc_i(istb),
.istb_i(istb),
.isiz_i(2'd2), // Always 32-bit
.isigned_i(1'b0),
.iack_o(iack),
.idat_o(idat_wide),
.ddat_i(ddato),
.dadr_i(dadr),
.dwe_i(dwe),
.dcyc_i(dcyc),
.dstb_i(dstb),
.dsiz_i(dsiz),
.dsigned_i(dsigned),
.dack_o(dack),
.ddat_o(ddati),
.xdat_o(xdato),
.xadr_o(xadr),
.xwe_o(xwe),
.xcyc_o(xcyc),
.xstb_o(xstb),
.xsiz_o(xsiz),
.xsigned_o(xsigned),
.xack_i(xack),
.xdat_i(xdati)
);
// Reduce bus to 16-bits wide.
bottleneck bot(
.clk_i(cpu_clk),
.reset_i(cpu_reset),
.m_adr_i(xadr),
.m_cyc_i(xcyc),
.m_dat_i(xdato),
.m_signed_i(xsigned),
.m_siz_i(xsiz),
.m_stb_i(xstb),
.m_we_i(xwe),
.m_ack_o(xack),
.m_dat_o(xdati),
.m_err_align_o(),
.s_adr_o(sadr),
.s_cyc_o(scyc),
.s_signed_o(ssigned),
.s_siz_o(ssiz),
.s_stb_o(sstb),
.s_we_o(swe),
.s_dat_o(sdato),
.s_ack_i(sack),
.s_dat_i(sdati)
);
// Expose a Wishbone B3 interface.
bridge wb_bridge(
.f_signed_i(ssigned),
.f_siz_i({1'b0, ssiz}),
.f_adr_i({2'b00, sadr[0]}),
.f_dat_i({48'd0, sdato}),
.f_dat_o(sdati_wide),
.wb_sel_o(wbsel),
.wb_dat_o(wbdato),
.wb_dat_i({48'd0, wbdati})
);
wire ram_addr = sadr[23:20] == 4'b0000;
wire gpia_addr = sadr[23:20] == 4'b0001;
wire remex_addr = sadr[23:20] == 4'b0010;
wire rom_addr = sadr[23:20] == 4'b1111;
wire ram_stb = scyc & sstb & ram_addr;
wire gpia_stb = scyc & sstb & gpia_addr;
wire remex_stb = scyc & sstb & remex_addr;
wire rom_stb = scyc & sstb & rom_addr;
// We want sack asserted if we address a non-existent
// region of memory. The data read back will just be 0.
// Remember, this logic only works because of how B3
// defines the relationship between STB and ACK signals.
// If upgrading to Wishbone B4, we'll need to change this.
assign sack = (ram_stb ? ram_ack : 1)
// & (remex_stb ? remex_ack : 1)
& (gpia_stb ? gpia_ack : 1)
& (rom_stb ? rom_ack : 1)
;
assign wbdati = (ram_ack ? ram_dat_o : 0)
// | (remex_ack ? remex_dat_o : 0)
| (gpia_ack ? gpia_dat_o : 0)
| (rom_ack ? rom_dat_o : 0)
;
// Static RAM interface.
sram ram(
.sram_clk(cpu_clk),
.sram_adr_o(sram_adr_o),
.sram_dat_io(sram_dat_io),
.sram_ce_on(sram_ce_on),
.sram_we_on(sram_we_on),
.sram_oe_on(sram_oe_on),
.sram_lbe_on(sram_lbe_on),
.sram_ube_on(sram_ube_on),
.sram_sel_i(wbsel[1:0]),
.sram_we_i(swe),
.sram_adr_i(sadr[19:1]),
.sram_dat_o(ram_dat_o),
.sram_dat_i(wbdato[15:0]),
.sram_stb_i(ram_stb),
.sram_ack_o(ram_ack)
);
// General Purpose I/O Adapter.
GPIA gpia(
.RST_I(cpu_reset),
.CLK_I(cpu_clk),
.PORT_O(gpia_outputs),
.PORT_I({15'd0, switch0}),
.ADR_I(sadr[1]),
.CYC_I(scyc),
.STB_I(gpia_stb),
.WE_I(swe),
.DAT_I(wbdato[15:0]),
.DAT_O(gpia_dat_o),
.ACK_O(gpia_ack)
);
assign led0 = gpia_outputs[0];
assign led1 = gpia_outputs[1];
assign led2 = gpia_outputs[2];
// Bootstrap ROM.
BROM rom(
.adr_i(sadr[7:1]),
.dat_o(rom_dat_o),
.stb_i(rom_stb),
.ack_o(rom_ack)
);
endmodule
|
`timescale 1ns / 1ps
module top_movil_TB;
reg clk;
// reg start;
reg reset;
reg rxd;
// wire [0:76] String;
wire [15:0] ledsOut;
top_movil uut ( .clk(clk), .rxd(rxd), .reset(reset), .ledsOut(ledsOut));
initial begin // Process for clk
forever
begin
#5
clk = 1'b0;
#5
clk = 1'b1;
end
end
/* initial begin
reset=1;
#100
reset=0;
start=0;
#200
reset=1;
#1000
start=1;
#20
reset=0;
#13998680
reset=1;
#200
reset=0;
end*/
initial begin
reset=1;
#200
reset=0;
rxd =1;
#2000
rxd=0; // simulacion de ruido
#40
rxd=1;
#208280
rxd=0; // Bit de Start 1
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1; // Se termina char 0110011
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 2
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1; // Se termina char 0010101
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 3
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0; // Se termina char 1110010
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 4
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0; // Se termina char 0101100
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 5
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0; // Se termina char 1110000
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 6
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1; // Se termina char 0011111
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 7
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0; // Se termina char 0010100
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 8
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1; // Se termina char 0011001
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 9
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0; // Se termina char 1100110
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 10
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0; // Se termina char 1111110
#104160
rxd=0; // Bit de Paridad
#104160
rxd=1; // Bit de Stop
#104160
rxd=0; // Bit de Start 11
#104160
rxd=0;
#104160
rxd=1;
#104160
rxd=1;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0;
#104160
rxd=0; // Se termina char 0110000
#104160
rxd=1; // Bit de Paridad
#104160
rxd=1; // Bit de Stop y queda en 1 como IDLE
end // initial begin
initial begin: TEST_CASE
$dumpfile("top_movil_TB.vcd");
$dumpvars(-1, uut);
#32000000 $finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O221AI_FUNCTIONAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o221ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_FUNCTIONAL_V
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bach_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module bach_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/bachelors_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/bachelors_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bach_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bach_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bach_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bach_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bach_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bach_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
module pll_top ( input ref_clk
, input rst
, output out_clk
, output locked
, input pcie_ready
, output pcie_ready_sync
, input xwopen
, output xwopen_sync
);
wire pll_core_locked;
reg [5:0] lock_reg, lock_next;
assign locked = (lock_reg == '1);
reg [1:0] p_reg, x_reg;
assign pcie_ready_sync = p_reg[1];
assign xwopen_sync = x_reg[1];
// make absolutely sure that the pll_locked signal is stable before taking the ckt out of reset
always_comb begin
lock_next = lock_reg;
if (pll_core_locked) begin
// when pll_core_locked, count upwards w/saturation
if (~locked) begin
lock_next = lock_reg + 1'b1;
end
end else begin
// otherwise, restart count
lock_next = '0;
end
end
always_ff @(posedge out_clk or posedge rst) begin
if (rst) begin
lock_reg <= '0;
p_reg <= '0;
x_reg <= '0;
end else begin
lock_reg <= lock_next;
p_reg <= {p_reg[0],pcie_ready};
x_reg <= {x_reg[0],xwopen};
end
end
pll_core ipll ( .refclk (ref_clk)
, .rst (rst)
, .outclk_0 (out_clk)
, .locked (pll_core_locked)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_int.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - [email protected] (Tadej Markovic) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
`include "uart_defines.v"
`include "uart_testbench_defines.v"
module testcase;
// Testcase INDEPENDENT code - common to all testcases
//#####################################################
// Variables
// Testbench reporting events & signals
event severe_err_event;
event err_event;
event wrn_event;
event msg_event;
event val_event;
event testbench_log_written;
reg [7999: 0] tim;
reg [7999: 0] severe_err_msg;
reg [7999: 0] msg;
integer val;
// Testcase reporting events & signals
event testcase_log_written;
event test_end;
reg [1599: 0] test_name;
reg error_detected;
// Module for writing to log files
uart_log log ();
defparam log.testcase_name = "uart_interrupts";
// Log
initial
fork
begin: init_log
reg ok;
// Delay allows all other blocks in this fork - join block to execute
#1;
log.start_log(ok);
if (ok !== 1'b1)
begin
`SEVERE_ERROR("Failed to open log file(s)!");
disable init_log;
end
testcase_init;
testcase_test;
log.end_log;
# 100;
$finish;
end
begin
forever
begin
@(test_name);
error_detected = 1'b0;
log.report_test_name(test_name);
log.verbose_test_name(test_name);
-> testcase_log_written;
end
end
begin
forever
begin
@(test_end);
if (error_detected)
begin
log.tests_failed = log.tests_failed + 1'b1;
end
else
begin
log.tests_ok = log.tests_ok + 1'b1;
log.report_test_ok;
end
-> testcase_log_written;
end
end
begin
@(severe_err_event);
error_detected = 1'b1;
-> test_end;
@(testcase_log_written);
log.report_test_failed(severe_err_msg);
if (testcase.log.free == 0)
begin
wait (testcase.log.free);
severe_err_msg = "Failed to write to log file(s)!";
end
log.verbose_severe_err(tim, severe_err_msg);
-> testbench_log_written;
# 100; $finish;
end
begin
forever
begin
@(err_event);
error_detected = 1'b1;
-> test_end;
@(testcase_log_written);
log.report_test_failed(msg);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_err(tim, msg);
-> testbench_log_written;
`PROMPT;
end
end
begin
forever
begin
@(wrn_event);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_wrn(tim, msg);
-> testbench_log_written;
end
end
begin
forever
begin
@(msg_event);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_msg(tim, msg);
-> testbench_log_written;
end
end
begin
forever
begin
@(val_event);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_val(tim, msg, val);
-> testbench_log_written;
end
end
join
// Testcase (DEPENDENT) code
//###########################
// Initialization
task testcase_init;
begin:init
test_name = "Initialization of UART.";
@(testcase_log_written);
//
testbench_utilities.do_reset;
testbench_utilities.disable_clk_generators(1, 1, 1, 1);
testbench_utilities.set_device_tx_rx_clk_divisor(32'h1000);
testbench_utilities.set_wb_clock_period(100);
testbench_utilities.enable_clk_generators(1, 1, 1, 1);
#100;
testbench_utilities.release_reset;
//
uart_wb_utilities.write_dlr(16'h1000);
uart_wb_utilities.write_ier(8'h07);
uart_wb_utilities.write_fcr(8'hC0);
uart_wb_utilities.write_lcr(8'h03);
//
uart_device_utilities.set_rx_length(8);
uart_device_utilities.disable_rx_parity;
uart_device_utilities.set_rx_second_stop_bit(0);
//
uart_device_utilities.set_tx_length(8);
uart_device_utilities.disable_tx_parity;
uart_device_utilities.correct_tx_parity;
uart_device_utilities.correct_tx_frame;
uart_device_utilities.generate_tx_glitch(0);
-> test_end;
@(testcase_log_written);
end
endtask // testcase_init
// Testcase
task testcase_test;
begin:test
test_name = "Interrupt test.";
@(testcase_log_written);
fork
begin: test
uart_wb_utilities.write_char(8'hAA);
@(testbench.int_aserted);
`TC_MSG("INT ASSERTED!");
uart_wb_utilities.write_char(8'hAA);
@(testbench.int_released);
`TC_MSG("INT RELEASED!");
@(testbench.int_aserted);
`TC_MSG("INT ASSERTED!");
uart_wb_utilities.read_iir;
@(testbench.int_released);
`TC_MSG("INT RELEASED!");
end
begin: wait_end
@(testbench.i_uart_device.device_received_packet);
@(testbench.i_uart_device.device_received_packet);
repeat(2) @(testbench.i_uart_device.rx_clk);
disable test;
disable wait_clk;
end
begin: wait_clk
testbench_utilities.wait_for_num_of_wb_clk(32'h450000);
disable test;
disable wait_end;
end
join
repeat (4) @(posedge testbench.wb_clk);
# 100;
-> test_end;
@(testcase_log_written);
end
endtask // testcase_test
endmodule
|
//=================================================================
// Copyright(c) Alorium Technology Group Inc., 2016
// ALL RIGHTS RESERVED
// $Id: $
//=================================================================
//
// File name: : xlr8_top.v
// Author : Matt Weber
// Contact : [email protected]
// Description : Simulation model of components on the XLR8
// board that we'd like to simulate, most importantly
// the XLR8 chip, but also various pullups and
// enables
//
//=================================================================
///////////////////////////////////////////////////////////////////
module xlr8_board #(parameter DESIGN_CONFIG = {28'd0, // 31:4: reserved
1'b1, // [3] : 1 = 16K Instruction, 0 = 8K instruction
2'd0, // [2:1]: clock speed[1:0]
1'b1}, // [0] = CFM FACTORY (1), CFM APPLICATION (0)
parameter APP_XB0_ENABLE = 32'hffff_ffff // for APPLICATION design, each bit [i] enables XB[i]
)
(
//Clock and Reset
input Clock, // 16MHz
input RESET_N,
//Arduino I/Os
inout wire SCL,
inout wire SDA,
inout [13:0] Digital, // Name to match names in original testbench
inout [5:0] Ana_Dig // Name to match names in original testbench
);
wire PIN13LED;
// We can disconnect Ana_Dig from ADC inputs if necessary (don't know if it is) by driving
// OE low. Else leave OE as high-Z (don't drive it high).
wire [5:0] DIG_IO;
wire [5:0] DIG_IO_OE;
wire ANA_UP; // Choose ADC ref between AREF pin and regulated 3.3V
wire I2C_ENABLE; // More importantly; disable pullups when doing analog read on A4/A5
// JTAG connector reused as digial IO. On that connector, pin 4 is power, pins 2&10 are ground
// and pin 8 selects between gpio (low) and jtag (high) modes and has a pulldown.
`ifdef JTAG_PIN_SHARE
wire JT9; // external pullup. JTAG function is TDI
wire JT7; // no JTAG function
wire JT6; // no JTAG function
wire JT5; // external pullup. JTAG function is TMS
wire JT3; // JTAG function TDO
wire JT1; // external pulldown, JTAG function is TCK
`else
// For now, we haven't enabled JTAG pin sharing, so JTAGEN is available as a GPIO and JT7 and
// JT6 are the only other pins available
wire JTAGEN; // not being used for JTAG function
wire JT7; // no JTAG function
wire JT6; // no JTAG function
//wire JT67; // Use JT6 and JT7 as differential pair?
`endif // !`ifdef JTAG_PIN_SHARE
// Interface to EEPROM or other device in SOIC-8 spot on the board
wire SOIC7; // WP in the case of an 24AA128SM EEPROM
wire SOIC6; // SCL in the case of an 24AA128SM EEPROM
wire SOIC5; // SDA in the case of an 24AA128SM EEPROM
wire SOIC3; // A2 in the case of an 24AA128SM EEPROM
wire SOIC2; // A1 in the case of an 24AA128SM EEPROM
wire SOIC1; // A0 in the case of an 24AA128SM EEPROM
/* xlr8_top AUTO_TEMPLATE (.D\([0-9]*\) (Digital[\1]),
.TX (Digital[1]),
.RX (Digital[0]),
.A\([0-9]*\) (DIG_IO[\1]),
);*/
xlr8_top #(/*AUTOINSTPARAM*/
// Parameters
.DESIGN_CONFIG (DESIGN_CONFIG),
.APP_XB0_ENABLE (APP_XB0_ENABLE))
xlr8_top_inst (
`ifdef JTAG_PIN_SHARE
.JT9 (JT9),
.JT7 (JT7),
.JT6 (JT6),
.JT5 (JT5),
.JT3 (JT3),
.JT1 (JT1),
`else
.JTAGEN (JTAGEN),
.JT7 (JT7),
.JT6 (JT6),
`endif
/*AUTOINST*/
// Outputs
.PIN13LED (PIN13LED),
.ANA_UP (ANA_UP),
.I2C_ENABLE (I2C_ENABLE),
// Inouts
.SCL (SCL),
.SDA (SDA),
.D13 (Digital[13]), // Templated
.D12 (Digital[12]), // Templated
.D11 (Digital[11]), // Templated
.D10 (Digital[10]), // Templated
.D9 (Digital[9]), // Templated
.D8 (Digital[8]), // Templated
.D7 (Digital[7]), // Templated
.D6 (Digital[6]), // Templated
.D5 (Digital[5]), // Templated
.D4 (Digital[4]), // Templated
.D3 (Digital[3]), // Templated
.D2 (Digital[2]), // Templated
.TX (Digital[1]), // Templated
.RX (Digital[0]), // Templated
.A5 (DIG_IO[5]), // Templated
.A4 (DIG_IO[4]), // Templated
.A3 (DIG_IO[3]), // Templated
.A2 (DIG_IO[2]), // Templated
.A1 (DIG_IO[1]), // Templated
.A0 (DIG_IO[0]), // Templated
.DIG_IO_OE (DIG_IO_OE[5:0]),
.SOIC7 (SOIC7),
.SOIC6 (SOIC6),
.SOIC5 (SOIC5),
.SOIC3 (SOIC3),
.SOIC2 (SOIC2),
.SOIC1 (SOIC1),
// Inputs
.Clock (Clock),
.RESET_N (RESET_N));
// The digital I/Os will likely always have pullups, either
// on the board (current plan) or in the chip (green board
// prototypes).
pullup(Digital[13]);
pullup(Digital[12]);
pullup(Digital[11]);
pullup(Digital[10]);
pullup(Digital[9]);
pullup(Digital[8]);
pullup(Digital[7]);
pullup(Digital[6]);
pullup(Digital[5]);
pullup(Digital[4]);
pullup(Digital[3]);
pullup(Digital[2]);
pullup(Digital[1]);
pullup(Digital[0]);
// The SDA/SCL pullups can be enabled/disabled
// when I2C_ENABLE is high, we should get pullups,
// when it is low, we should just set high-Z on
// SDA/SCL
rnmos Q19a (SDA,1'b1,I2C_ENABLE); // (r)esistive version of nmos
rnmos Q19b (SCL,1'b1,I2C_ENABLE); // should reduce 1'b1 to pull strength
// DIG_IO_OE are used to disconnect the digital I/O
// side of A5..A0 from the analog input side
// When DIG_IO_OE is 0 they are disconnected, when
// it is high-Z they are connected, when it is a
// 1 they are also connected, but bad, or at least
// unintended things, could happen in the circuits
// because the pullups are to 5V
pullup(DIG_IO_OE[5]);
pullup(DIG_IO_OE[4]);
pullup(DIG_IO_OE[3]);
pullup(DIG_IO_OE[2]);
pullup(DIG_IO_OE[1]);
pullup(DIG_IO_OE[0]);
tranif1(Ana_Dig[0],DIG_IO[0],DIG_IO_OE[0]);
tranif1(Ana_Dig[1],DIG_IO[1],DIG_IO_OE[1]);
tranif1(Ana_Dig[2],DIG_IO[2],DIG_IO_OE[2]);
tranif1(Ana_Dig[3],DIG_IO[3],DIG_IO_OE[3]);
tranif1(Ana_Dig[4],DIG_IO[4],DIG_IO_OE[4]);
tranif1(Ana_Dig[5],DIG_IO[5],DIG_IO_OE[5]);
endmodule: xlr8_board
// Local Variables:
// verilog-library-flags:("-y ../../../rtl/")
// End:
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:46 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/select2/select2_sim_netlist.v
// Design : select2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "select2,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module select2
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [11:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [11:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "12" *)
(* C_ADDRB_WIDTH = "12" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.822999 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "select2.mem" *)
(* C_INIT_FILE_NAME = "select2.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2109" *)
(* C_READ_DEPTH_B = "2109" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "2109" *)
(* C_WRITE_DEPTH_B = "2109" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
select2_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[11:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[11:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module select2_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
select2_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[3:0]),
.douta(douta[3:0]),
.wea(wea));
select2_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[11:4]),
.douta(douta[11:4]),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module select2_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [3:0]douta;
input clka;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]douta;
wire [0:0]wea;
select2_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module select2_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
select2_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module select2_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [3:0]douta;
input clka;
input [11:0]addra;
input [3:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [3:0]dina;
wire [3:0]douta;
wire [0:0]wea;
wire [15:4]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0FFFFFF000000000FFFFFF00FFFFFFF0000000000000000000000000FFFFFF00),
.INIT_03(256'h000000000F0000F0000000000000000000000000000000000000000000000000),
.INIT_04(256'h000000000000000000F0000FF00000000F0000FFFF00000FFFFFFFFF00000000),
.INIT_05(256'h0FF00000FFFFFFFFF000000000F0000FF0000FFFFFFFF0000000000000000000),
.INIT_06(256'h0000000000000000000000FFFFFF00000FFF00000F000FFFFFF00000FF000000),
.INIT_07(256'h0000000000F00000000F00000000000000FFFFFFFF0F00000F000FF000000FF0),
.INIT_08(256'h00FF00F00000000FF0000000000000000000000F0000FFFFFFF0000000FFFFF0),
.INIT_09(256'h000F00000000000F00000000000000000000F000000000000000000000F0F000),
.INIT_0A(256'h00000000000F0FF00000F00F000000000FF00000000000000000000FF0000FF0),
.INIT_0B(256'hFFFFFFFFF00000000000F00000000000F00000000000000000000FF000000000),
.INIT_0C(256'hFF00000F00000000000000000000F00F00000FF0F0000000000F00000000000F),
.INIT_0D(256'h0000F0200FFFFFFFF000000FF0000000000000FF000000000000000000000000),
.INIT_0E(256'h0F00000000000000FFF00000FF0000000000000000FFFF00F000000F0FF00000),
.INIT_0F(256'h0F000000FF0F000000000F0000F00000000000000F0000000000000000000000),
.INIT_10(256'h000000000000000000F000000000000000F0000000FF000000000000000FF000),
.INIT_11(256'h000000FF00000F000FF0000000FFFF0000000FF0000F00000000000000000000),
.INIT_12(256'h000000000000000000000000000000000000000000000000000F0000000FFF00),
.INIT_13(256'h0000000000000FF00000FFFFF00000F00FF0000000000FFF0000000FF000F000),
.INIT_14(256'hFFF000000FF00FF000000000000000000000000000000F000000000000F00000),
.INIT_15(256'hF000000FFFFF000000000000000000FFF0000F0FFF00000F0FF000000000000F),
.INIT_16(256'hF0F000000000000000000000000F000FFF000000FF0000F0000000000000000F),
.INIT_17(256'hF0000000000000000FFF0000F000F000000000000F000000FF0000FFF0000000),
.INIT_18(256'h0000000F000000000F0F0000000F0000000000000000F00000FFFFFFFFFFFFFF),
.INIT_19(256'h00000000000000000FF00000000000000000000FFF000FF00000000000FF0000),
.INIT_1A(256'hF0000000000FFF0000000000F00000000FF0F000000FFFF00000000000000F00),
.INIT_1B(256'hFFFFFFFFFFFFFFF00000000000000000000FFFF00000FFF000000000F000000F),
.INIT_1C(256'hF00000000F0000000FFFFFFFFFFFF0FF00000000FF0000000FF00FF0000FF00F),
.INIT_1D(256'hFFF0000FFFFFF000000000000000000000000000000000000000000FF0000F0F),
.INIT_1E(256'h000000000FFFFFF00FFFFFFFFFF000000000000000000000FFFFFFFFFFFFFFFF),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(4),
.WRITE_WIDTH_B(4))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR({addra,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:4],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module select2_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [11:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [11:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h4F4F4F4F4F4F4F000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_01(256'h00000000004F4F000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_02(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F0000000000004F4F4F4F4F4F4F4F4F00),
.INIT_03(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_04(256'h000000000000004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00FFFFFFFFFFFF004F),
.INIT_05(256'h00FFFFFFFFFFFF004F4F4F4F4F4F4F00FFFFFFFFFFFF0000FFFFFFFFFFFFFF00),
.INIT_06(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_07(256'h4F4F4F4F4F4F4F4F00FFF0F0F0F0FF004F4F4F4F00000000000000004F4F4F4F),
.INIT_08(256'h00FFF0F0F0F0FFFFFFFFF0F0F0F0F0FFFFFFFFFFFFFFFFFF0000000000000000),
.INIT_09(256'h4F4F4F4F4F0000000000004F4F4F4F4F0000FFF0F0F0F0FFFF004F4F00000000),
.INIT_0A(256'hFF004F4F00FFFFFFFFFFFFFFFF004F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_0B(256'hF0FFFFF0F0F0F0F0FFFFFFFFFFFFFFFFFF000000000000000000FFF0FFFFF0FF),
.INIT_0C(256'h00FFFFFFF0FFFFF0F0FF000000FFFFFFFFFFFFF0FFFFF0F0FFFFF0F0FFFFFFF0),
.INIT_0D(256'h4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F4F00FFFFFFFFFFFF00000000),
.INIT_0E(256'hF0F0FFFFFFFFFFFFFFFF00FFF0FFFFF0F0FF004F00FFFFF0F0F0F0F0F0FFFF00),
.INIT_0F(256'hF0F0F0F0FFF0FFFFF0F0FFF0FFFFF0FFFFF0F0FFF0FFFFFFF0F0F0F0F0F0F0F0),
.INIT_10(256'h4F4F4F4F4F4F00FFF0F0F0F0FFFFFFFFFFFFFFF0F0F0F0FFFFF0FFFFFFFFFFF0),
.INIT_11(256'hFFF0FFFF0000FFF0F0FFFFFFFFF0F0FFFF004F4F4F4F4F4F4F4F4F4F4F4F4F4F),
.INIT_12(256'hFFFFFFF0FFF0F0FFFFFFFFFFF0FFFFFFFFFFF0F0F0F0F0F0F0F0FF00FFF0F0FF),
.INIT_13(256'hF0F0F0FFF0FFFFFFFFFFF0F0F0F0F0FFF0FFFFFFF0F0F0FFFFFFF0F0F0F0FFFF),
.INIT_14(256'hF0FFFF004F4F4F4F4F4F4F4F4F4F000000000000000000FFFFF0FFFFF0FFFFF0),
.INIT_15(256'hF0FFFFFFFFFFFFFFFFFFF0FF00FFFFF0FFFFF0F0FF0000FFF0FFFFFFF0FFFFF0),
.INIT_16(256'hFFF0FFFFF0F0FFFFFFFFFFFFFFFFF0F0F0F0FFFFF0FFFFF0FFFFFFF0F0FFF0F0),
.INIT_17(256'hFFFFFFFFFFFFFFFFFFF0F0FFFFF0F0F0F0FFFFF0FFF0F0F0FFFFFFFFFFFFFFF0),
.INIT_18(256'hF0FFFFFFF0FFFF00FFF0F0FFFFF0F0FFFFF0F0FF004F4F4F00000000000000FF),
.INIT_19(256'hFFFFF0FFFFF0F0FFF0F0FFFFFFF0F0FFFFF0F0F0FFFFF0F0F0F0F0F0FF0000FF),
.INIT_1A(256'hF0F0FFFFF0F0FFFFF0F0F0F0FFFFF0F0F0F0F0FFFFF0F0FFFFF0F0FFFFF0F0F0),
.INIT_1B(256'hF0FFFFF0FF00234F00FFFFFFFFFFFFFFFFF0F0F0F0F0F0FFFFF0F0FFFFFFFFFF),
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.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module select2_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
select2_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "12" *) (* C_ADDRB_WIDTH = "12" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.822999 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "select2.mem" *)
(* C_INIT_FILE_NAME = "select2.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2109" *) (* C_READ_DEPTH_B = "2109" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "2109" *) (* C_WRITE_DEPTH_B = "2109" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module select2_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [11:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [11:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [11:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [11:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
select2_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module select2_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [11:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
select2_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/03/2014 07:21:44 PM
// Design Name:
// Module Name: seven_seg
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module seven_seg(
input clk,
input signed [5:0] shift_val,
input signed [5:0] vshift_val,
output reg [7:0] anode,
output reg [7:0] segments
);
reg [7:0] anodestate;
reg [7:0] gotostate;
reg [5:0] abs_shift_val;
reg [5:0] abs_vshift_val;
initial begin
anode = {8 {1'b1}};
anodestate = 8'b10111111;
gotostate = 8'b10111111;
end
always @(posedge clk) begin
abs_shift_val = (shift_val[5] ? ~shift_val+1 : shift_val);
abs_vshift_val = (vshift_val[5] ? ~vshift_val+1 : vshift_val);
anode = anodestate;
case (anode)
// vertical shift display
8'b10111111: begin
segments = (vshift_val < 0) ? 8'b1011_1111 : 8'b1111_1111;
gotostate = 8'b11011111;
anodestate = 8'b11111111;
end
8'b11011111: begin
case (abs_vshift_val)
4,
5,
6: segments = 8'b1111_1001; // 1
7,
8: segments = 8'b1010_0100; // 2
9,
10,
11: segments = 8'b1011_0000; // 3
12,
13: segments = 8'b1001_1001; // 4
14,
15: segments = 8'b1001_0010; // 5
16: segments = 8'b1000_0010; // 6
17: segments = 8'b1111_1000; // 7
endcase
//segments = (abs_vshift_val > 9) ? 8'b1111_1001 : 8'b1111_1111;
gotostate = 8'b11101111;
anodestate = 8'b11111111;
end
8'b11101111: begin
case (abs_vshift_val)
0,
9: segments = 8'b1100_0000; // 0
14,
17: segments = 8'b1111_1001; // 1
4,
12: segments = 8'b1010_0100; // 2 // saving donuts for friends
1,
7,
10,
16: segments = 8'b1011_0000; // 3
//: segments = 8'b1001_1001; // 4
//: segments = 8'b1001_0010; // 5
2,
5,
8,
13,
15: segments = 8'b1000_0010; // 6
11: segments = 8'b1111_1000; // 7
3,
6: segments = 8'b1001_0000; // 9
endcase
/*case (abs_vshift_val[2:0])
3'b000: segments = abs_vshift_val[3] ? 8'b1000_0000 : 8'b1100_0000; // 8 and 0
3'b001: segments = abs_vshift_val[3] ? 8'b1001_0000 : 8'b1111_1001; // 9 and 1
3'b010: segments = 8'b1010_0100; // 2
3'b011: segments = 8'b1011_0000; // 3
3'b100: segments = 8'b1001_1001; // 4
3'b101: segments = 8'b1001_0010; // 5
3'b110: segments = 8'b1000_0010; // 6
3'b111: segments = 8'b1111_1000; // 7
default: segments = 8'b1111_1111;
endcase*/
gotostate = 8'b11111011;
anodestate = 8'b11111111;
end
// horizontal shift display
8'b11111011: begin
segments = (shift_val < 0) ? 8'b1011_1111 : 8'b1111_1111;
gotostate = 8'b11111101;
anodestate = 8'b11111111;
end
8'b11111101: begin
case (abs_shift_val)
4,
5,
6: segments = 8'b1111_1001; // 1
7,
8: segments = 8'b1010_0100; // 2
9,
10,
11: segments = 8'b1011_0000; // 3
12,
13: segments = 8'b1001_1001; // 4
14,
15: segments = 8'b1001_0010; // 5
16: segments = 8'b1000_0010; // 6
17: segments = 8'b1111_1000; // 7
endcase
//segments = (abs_shift_val > 9) ? 8'b1111_1001 : 8'b1111_1111;
gotostate = 8'b11111110;
anodestate = 8'b11111111;
end
8'b11111110: begin
case (abs_shift_val)
0,
9: segments = 8'b1100_0000; // 0
14,
17: segments = 8'b1111_1001; // 1
4,
12: segments = 8'b1010_0100; // 2 // saving donuts for friends
1,
7,
10,
16: segments = 8'b1011_0000; // 3
//: segments = 8'b1001_1001; // 4
//: segments = 8'b1001_0010; // 5
2,
5,
8,
13,
15: segments = 8'b1000_0010; // 6
11: segments = 8'b1111_1000; // 7
3,
6: segments = 8'b1001_0000; // 9
endcase
/*case (abs_shift_val[2:0])
3'b000: segments = abs_shift_val[3] ? 8'b1000_0000 : 8'b1100_0000;
3'b001: segments = abs_shift_val[3] ? 8'b1001_0000 : 8'b1111_1001;
3'b010: segments = 8'b1010_0100;
3'b011: segments = 8'b1011_0000;
3'b100: segments = 8'b1001_1001;
3'b101: segments = 8'b1001_0010;
3'b110: segments = 8'b1000_0010;
3'b111: segments = 8'b1111_1000;
default: segments = 8'b1111_1111;
endcase*/
gotostate = 8'b10111111;
anodestate = 8'b11111111;
end
8'b11111111: begin
// clear cathodes between displays
segments = 8'b1111_1111;
anodestate = gotostate;
end
default: begin
segments = 8'b1111_1111;
anodestate = 8'b11111111;
end
endcase
end
endmodule
|
`default_nettype wire
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module CPC2_DE10(
//////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
//////////// HDMI //////////
inout HDMI_I2C_SCL,
inout HDMI_I2C_SDA,
inout HDMI_I2S,
inout HDMI_LRCLK,
inout HDMI_MCLK,
inout HDMI_SCLK,
output HDMI_TX_CLK,
output HDMI_TX_DE,
output [23:0] HDMI_TX_D,
output HDMI_TX_HS,
input HDMI_TX_INT,
output HDMI_TX_VS,
//////////// KEY //////////
input [1:0] KEY,
//////////// LED //////////
output [7:0] LED,
//////////// SW //////////
input [3:0] SW,
//////////// GPIO_0, GPIO connect to GPIO Default //////////
inout [35:0] GPIO_0,
//////////// GPIO_1, GPIO connect to GPIO Default //////////
inout [35:0] GPIO_1,
// UART
inout HPS_UART_RX,
inout HPS_UART_TX,
/*
// SDCARD
inout HPS_SD_CLKIN,
inout HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
*/
// USB
inout HPS_USB_RESET,
inout HPS_USB_CLKOUT,
inout HPS_USB_DIR,
inout HPS_USB_NXT,
inout HPS_USB_STP,
inout [7:0] HPS_USB_DATA,
// DDR3
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N
);
//=======================================================
// REG/WIRE declarations
//=======================================================
// HPS
wire [66:0] loan_in, loan_out, loan_oe;
// MMC
wire mmccmd_oe, mmcdata_oe, usb_oe;
// GPIO
wire [31:0] gpio;
HPS u0 (
.memory_mem_a (HPS_DDR3_ADDR), // memory.mem_a
.memory_mem_ba (HPS_DDR3_BA), // .mem_ba
.memory_mem_ck (HPS_DDR3_CK_P), // .mem_ck
.memory_mem_ck_n (HPS_DDR3_CK_N), // .mem_ck_n
.memory_mem_cke (HPS_DDR3_CKE), // .mem_cke
.memory_mem_cs_n (HPS_DDR3_CS_N), // .mem_cs_n
.memory_mem_ras_n (HPS_DDR3_RAS_N), // .mem_ras_n
.memory_mem_cas_n (HPS_DDR3_CAS_N), // .mem_cas_n
.memory_mem_we_n (HPS_DDR3_WE_N), // .mem_we_n
.memory_mem_reset_n (HPS_DDR3_RESET_N), // .mem_reset_n
.memory_mem_dq (HPS_DDR3_DQ), // .mem_dq
.memory_mem_dqs (HPS_DDR3_DQS_P), // .mem_dqs
.memory_mem_dqs_n (HPS_DDR3_DQS_N), // .mem_dqs_n
.memory_mem_odt (HPS_DDR3_ODT), // .mem_odt
.memory_mem_dm (HPS_DDR3_DM), // .mem_dm
.memory_oct_rzqin (HPS_DDR3_RZQ), // .oct_rzqin
// Uart
.hps_io_hps_io_gpio_inst_LOANIO49 (HPS_UART_RX),
.hps_io_hps_io_gpio_inst_LOANIO50 (HPS_UART_TX),
/*
// SDCARD
.hps_io_hps_io_gpio_inst_LOANIO36 (HPS_SD_CMD), // hps_io.hps_io_gpio_inst_LOANIO36
.hps_io_hps_io_gpio_inst_LOANIO38 (HPS_SD_DATA[0]), // .hps_io_gpio_inst_LOANIO38
.hps_io_hps_io_gpio_inst_LOANIO39 (HPS_SD_DATA[1]), // .hps_io_gpio_inst_LOANIO39
.hps_io_hps_io_gpio_inst_LOANIO44 (HPS_SD_CLKIN), // .hps_io_gpio_inst_LOANIO45
.hps_io_hps_io_gpio_inst_LOANIO45 (HPS_SD_CLK), // .hps_io_gpio_inst_LOANIO45
.hps_io_hps_io_gpio_inst_LOANIO46 (HPS_SD_DATA[2]), // .hps_io_gpio_inst_LOANIO46
.hps_io_hps_io_gpio_inst_LOANIO47 (HPS_SD_DATA[3]), // .hps_io_gpio_inst_LOANIO47
*/
// USB
.hps_io_hps_io_gpio_inst_LOANIO01 (HPS_USB_DATA[0]),
.hps_io_hps_io_gpio_inst_LOANIO02 (HPS_USB_DATA[1]),
.hps_io_hps_io_gpio_inst_LOANIO03 (HPS_USB_DATA[2]),
.hps_io_hps_io_gpio_inst_LOANIO04 (HPS_USB_DATA[3]),
.hps_io_hps_io_gpio_inst_LOANIO05 (HPS_USB_DATA[4]),
.hps_io_hps_io_gpio_inst_LOANIO06 (HPS_USB_DATA[5]),
.hps_io_hps_io_gpio_inst_LOANIO07 (HPS_USB_DATA[6]),
.hps_io_hps_io_gpio_inst_LOANIO08 (HPS_USB_DATA[7]),
.hps_io_hps_io_gpio_inst_LOANIO10 (HPS_USB_CLKOUT),
.hps_io_hps_io_gpio_inst_LOANIO11 (HPS_USB_STP),
.hps_io_hps_io_gpio_inst_LOANIO12 (HPS_USB_DIR),
.hps_io_hps_io_gpio_inst_LOANIO13 (HPS_USB_NXT),
.hps_io_hps_io_gpio_inst_LOANIO42 (HPS_USB_RESET),
// LoanIO
.loanio_in (loan_in), // loanio.in
.loanio_out (loan_out), // .out
.loanio_oe (loan_oe), // .oe
.hps_gp_gp_in(), // hps_gp.gp_in
.hps_gp_gp_out(gpio) // .gp_out
);
// =========== Assign loanIO directions ===========
// UART_TX
assign loan_oe[50] = 1'b1;
// USB Clk
assign loan_oe[10] = 1'b0;
// USB Reset
assign loan_oe[42] = 1'b1;
// USB NXT/DIRections
assign loan_oe[13] = 1'b0;
assign loan_oe[12] = 1'b0;
// USB STP
assign loan_oe[11] = 1'b1;
// USB Data
assign loan_oe[8:1] = {8{usb_oe}};
//=======================================================
// Structural coding
//=======================================================
wire [2:0] dummy1;
assign LED[6:1] = 7'd0;
assign LED[7] = gpio[0];
wire mmc_cmd, mmc_clkinv;
wire [3:0] mmc_data;
assign GPIO_0[4] = (mmccmd_oe) ? mmc_cmd : 1'bz;
assign GPIO_0[3:0] = (mmcdata_oe) ? mmc_data : 4'bzzzz;
assign GPIO_0[5] = ~mmc_clkinv;
assign GPIO_0[13] = mmccmd_oe;
assign GPIO_0[11] = GPIO_0[5];
assign GPIO_0[9] = GPIO_0[4];
CPC2 cpc2_inst (
.CLK_50(FPGA_CLK1_50),
.CLK2_50(FPGA_CLK2_50),
.CLK_12(FPGA_CLK3_50),
// Soft Reset - any key
.reset_i((KEY != 2'b11)|gpio[0]),
// I2C Control Ports
.I2C_SCL(HDMI_I2C_SCL), // INOUT - HDMI
.I2C_SDA(HDMI_I2C_SDA), // INOUT - HDMI
// Disk/activity LED
.LED(GPIO_1[19]),
// Video port - output
.VSYNC(HDMI_TX_VS),
.HSYNC(HDMI_TX_HS),
.VDE(HDMI_TX_DE),
.VCLK(HDMI_TX_CLK),
.R(HDMI_TX_D[23:16]),
.G(HDMI_TX_D[15:8]),
.B(HDMI_TX_D[7:0]),
// Video Audio
.I2S({dummy1,HDMI_I2S}), // 4 bits
.ASCLK(HDMI_SCLK),
.LRCLK(HDMI_LRCLK),
.MCLK(HDMI_MCLK),
// Uart port
.uart_rx_i(loan_in[49]),
.uart_tx_o(loan_out[50]),
// SDCARD
.mmcclk_o(mmc_clkinv),
.mmccmd_i(GPIO_0[4]),
.mmccmd_o(mmc_cmd),
.mmccmd_oe(mmccmd_oe),
.mmcdata_i(GPIO_0[3:0]),
.mmcdata_o(mmc_data),
.mmcdata_oe(mmcdata_oe),
// Hyperram1 Port
.hyper_dq({GPIO_1[10], GPIO_1[13], GPIO_1[15], GPIO_1[18], GPIO_1[17], GPIO_1[16], GPIO_1[12], GPIO_1[14]}),
.hyper_rwds(GPIO_1[7]),
.hyper_csn_o(GPIO_1[8]),
.hyper_ck_o(GPIO_1[11] ),
.hyper_resetn_o(GPIO_1[9] ),
// Hyperram2 Port
.hyper2_dq({GPIO_1[28], GPIO_1[30], GPIO_1[32], GPIO_1[35], GPIO_1[34], GPIO_1[33], GPIO_1[29], GPIO_1[31]}),
.hyper2_rwds(GPIO_1[26]),
.hyper2_csn_o(GPIO_1[25]),
.hyper2_ck_o(GPIO_1[27] ),
.hyper2_resetn_o(GPIO_1[24] ),
// USB port
.usb_clkin(loan_in[10]),
.usb_data_i({loan_in[8],loan_in[7],loan_in[6],loan_in[5],loan_in[4],loan_in[3],loan_in[2],loan_in[1]}),
.usb_data_o({loan_out[8],loan_out[7],loan_out[6],loan_out[5],loan_out[4],loan_out[3],loan_out[2],loan_out[1]}),
.usb_data_oe(usb_oe),
.usb_dir(loan_in[12]),
.usb_nxt(loan_in[13]),
.usb_stp(loan_out[11]),
.usb_reset(loan_out[42])
);
// TODO: Remove DE10 test code
reg [25:0] testled = 0;
always @(posedge FPGA_CLK3_50) testled <= testled + 1'b1;
assign LED[0] = testled<25'd2000000;
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2015 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: ogfx_reg.v
//
// *Module Description:
// Registers for oMSP programming.
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_defines.v"
`endif
module ogfx_reg (
// OUTPUTs
irq_gfx_o, // Graphic Controller interrupt
gpu_data_o, // GPU data
gpu_data_avail_o, // GPU data available
gpu_enable_o, // GPU enable
lt24_reset_n_o, // LT24 Reset (Active Low)
lt24_on_o, // LT24 on/off
lt24_cfg_clk_o, // LT24 Interface clock configuration
lt24_cfg_refr_o, // LT24 Interface refresh configuration
lt24_cfg_refr_sync_en_o, // LT24 Interface refresh sync enable configuration
lt24_cfg_refr_sync_val_o, // LT24 Interface refresh sync value configuration
lt24_cmd_refr_o, // LT24 Interface refresh command
lt24_cmd_val_o, // LT24 Generic command value
lt24_cmd_has_param_o, // LT24 Generic command has parameters
lt24_cmd_param_o, // LT24 Generic command parameter value
lt24_cmd_param_rdy_o, // LT24 Generic command trigger
lt24_cmd_dfill_o, // LT24 Data fill value
lt24_cmd_dfill_wr_o, // LT24 Data fill trigger
display_width_o, // Display width
display_height_o, // Display height
display_size_o, // Display size (number of pixels)
display_y_swap_o, // Display configuration: swap Y axis (horizontal symmetry)
display_x_swap_o, // Display configuration: swap X axis (vertical symmetry)
display_cl_swap_o, // Display configuration: swap column/lines
gfx_mode_o, // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
per_dout_o, // Peripheral data output
refresh_frame_addr_o, // Refresh frame base address
hw_lut_palette_sel_o, // Hardware LUT palette configuration
hw_lut_bgcolor_o, // Hardware LUT background-color selection
hw_lut_fgcolor_o, // Hardware LUT foreground-color selection
sw_lut_enable_o, // Refresh LUT-RAM enable
sw_lut_bank_select_o, // Refresh LUT-RAM bank selection
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_addr_o, // LUT-RAM address
lut_ram_din_o, // LUT-RAM data
lut_ram_wen_o, // LUT-RAM write strobe (active low)
lut_ram_cen_o, // LUT-RAM chip enable (active low)
`endif
vid_ram_addr_o, // Video-RAM address
vid_ram_din_o, // Video-RAM data
vid_ram_wen_o, // Video-RAM write strobe (active low)
vid_ram_cen_o, // Video-RAM chip enable (active low)
// INPUTs
dbg_freeze_i, // Freeze address auto-incr on read
gpu_cmd_done_evt_i, // GPU command done event
gpu_cmd_error_evt_i, // GPU command error event
gpu_dma_busy_i, // GPU DMA execution on going
gpu_get_data_i, // GPU get next data
lt24_status_i, // LT24 FSM Status
lt24_start_evt_i, // LT24 FSM is starting
lt24_done_evt_i, // LT24 FSM is done
mclk, // Main system clock
per_addr_i, // Peripheral address
per_din_i, // Peripheral data input
per_en_i, // Peripheral enable (high active)
per_we_i, // Peripheral write enable (high active)
puc_rst, // Main system reset
`ifdef WITH_PROGRAMMABLE_LUT
lut_ram_dout_i, // LUT-RAM data input
`endif
vid_ram_dout_i // Video-RAM data input
);
// PARAMETERs
//============
parameter [14:0] BASE_ADDR = 15'h0200; // Register base address
// - 7 LSBs must stay cleared: 0x0080, 0x0100,
// 0x0180, 0x0200,
// 0x0280, ...
// OUTPUTs
//============
output irq_gfx_o; // Graphic Controller interrupt
output [15:0] gpu_data_o; // GPU data
output gpu_data_avail_o; // GPU data available
output gpu_enable_o; // GPU enable
output lt24_reset_n_o; // LT24 Reset (Active Low)
output lt24_on_o; // LT24 on/off
output [2:0] lt24_cfg_clk_o; // LT24 Interface clock configuration
output [11:0] lt24_cfg_refr_o; // LT24 Interface refresh configuration
output lt24_cfg_refr_sync_en_o; // LT24 Interface refresh sync configuration
output [9:0] lt24_cfg_refr_sync_val_o; // LT24 Interface refresh sync value configuration
output lt24_cmd_refr_o; // LT24 Interface refresh command
output [7:0] lt24_cmd_val_o; // LT24 Generic command value
output lt24_cmd_has_param_o; // LT24 Generic command has parameters
output [15:0] lt24_cmd_param_o; // LT24 Generic command parameter value
output lt24_cmd_param_rdy_o; // LT24 Generic command trigger
output [15:0] lt24_cmd_dfill_o; // LT24 Data fill value
output lt24_cmd_dfill_wr_o; // LT24 Data fill trigger
output [`LPIX_MSB:0] display_width_o; // Display width
output [`LPIX_MSB:0] display_height_o; // Display height
output [`SPIX_MSB:0] display_size_o; // Display size (number of pixels)
output display_y_swap_o; // Display configuration: swap Y axis (horizontal symmetry)
output display_x_swap_o; // Display configuration: swap X axis (vertical symmetry)
output display_cl_swap_o; // Display configuration: swap column/lines
output [2:0] gfx_mode_o; // Video mode (1xx:16bpp / 011:8bpp / 010:4bpp / 001:2bpp / 000:1bpp)
output [15:0] per_dout_o; // Peripheral data output
output [`APIX_MSB:0] refresh_frame_addr_o; // Refresh frame base address
output [2:0] hw_lut_palette_sel_o; // Hardware LUT palette configuration
output [3:0] hw_lut_bgcolor_o; // Hardware LUT background-color selection
output [3:0] hw_lut_fgcolor_o; // Hardware LUT foreground-color selection
output sw_lut_enable_o; // Refresh LUT-RAM enable
output sw_lut_bank_select_o; // Refresh LUT-RAM bank selection
`ifdef WITH_PROGRAMMABLE_LUT
output [`LRAM_MSB:0] lut_ram_addr_o; // LUT-RAM address
output [15:0] lut_ram_din_o; // LUT-RAM data
output lut_ram_wen_o; // LUT-RAM write strobe (active low)
output lut_ram_cen_o; // LUT-RAM chip enable (active low)
`endif
output [`VRAM_MSB:0] vid_ram_addr_o; // Video-RAM address
output [15:0] vid_ram_din_o; // Video-RAM data
output vid_ram_wen_o; // Video-RAM write strobe (active low)
output vid_ram_cen_o; // Video-RAM chip enable (active low)
// INPUTs
//============
input dbg_freeze_i; // Freeze address auto-incr on read
input gpu_cmd_done_evt_i; // GPU command done event
input gpu_cmd_error_evt_i; // GPU command error event
input gpu_dma_busy_i; // GPU DMA execution on going
input gpu_get_data_i; // GPU get next data
input [4:0] lt24_status_i; // LT24 FSM Status
input lt24_start_evt_i; // LT24 FSM is starting
input lt24_done_evt_i; // LT24 FSM is done
input mclk; // Main system clock
input [13:0] per_addr_i; // Peripheral address
input [15:0] per_din_i; // Peripheral data input
input per_en_i; // Peripheral enable (high active)
input [1:0] per_we_i; // Peripheral write enable (high active)
input puc_rst; // Main system reset
`ifdef WITH_PROGRAMMABLE_LUT
input [15:0] lut_ram_dout_i; // LUT-RAM data input
`endif
input [15:0] vid_ram_dout_i; // Video-RAM data input
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 7;
// Register addresses offset
parameter [DEC_WD-1:0] GFX_CTRL = 'h00, // General control/status/irq
GFX_STATUS = 'h08,
GFX_IRQ = 'h0A,
DISPLAY_WIDTH = 'h10, // Display configuration
DISPLAY_HEIGHT = 'h12,
DISPLAY_SIZE_LO = 'h14,
DISPLAY_SIZE_HI = 'h16,
DISPLAY_CFG = 'h18,
DISPLAY_REFR_CNT = 'h1A,
LT24_CFG = 'h20, // LT24 configuration and Generic command sending
LT24_REFRESH = 'h22,
LT24_REFRESH_SYNC = 'h24,
LT24_CMD = 'h26,
LT24_CMD_PARAM = 'h28,
LT24_CMD_DFILL = 'h2A,
LT24_STATUS = 'h2C,
LUT_CFG = 'h30, // LUT Configuration & Memory Access Gate
LUT_RAM_ADDR = 'h32,
LUT_RAM_DATA = 'h34,
FRAME_SELECT = 'h3E, // Frame pointers and selection
FRAME0_PTR_LO = 'h40,
FRAME0_PTR_HI = 'h42,
FRAME1_PTR_LO = 'h44,
FRAME1_PTR_HI = 'h46,
FRAME2_PTR_LO = 'h48,
FRAME2_PTR_HI = 'h4A,
FRAME3_PTR_LO = 'h4C,
FRAME3_PTR_HI = 'h4E,
VID_RAM0_CFG = 'h50, // First Video Memory Access Gate
VID_RAM0_WIDTH = 'h52,
VID_RAM0_ADDR_LO = 'h54,
VID_RAM0_ADDR_HI = 'h56,
VID_RAM0_DATA = 'h58,
VID_RAM1_CFG = 'h60, // Second Video Memory Access Gate
VID_RAM1_WIDTH = 'h62,
VID_RAM1_ADDR_LO = 'h64,
VID_RAM1_ADDR_HI = 'h66,
VID_RAM1_DATA = 'h68,
GPU_CMD_LO = 'h70, // Graphic Processing Unit
GPU_CMD_HI = 'h72,
GPU_STAT = 'h74;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] GFX_CTRL_D = (BASE_REG << GFX_CTRL ),
GFX_STATUS_D = (BASE_REG << GFX_STATUS ),
GFX_IRQ_D = (BASE_REG << GFX_IRQ ),
DISPLAY_WIDTH_D = (BASE_REG << DISPLAY_WIDTH ),
DISPLAY_HEIGHT_D = (BASE_REG << DISPLAY_HEIGHT ),
DISPLAY_SIZE_LO_D = (BASE_REG << DISPLAY_SIZE_LO ),
DISPLAY_SIZE_HI_D = (BASE_REG << DISPLAY_SIZE_HI ),
DISPLAY_CFG_D = (BASE_REG << DISPLAY_CFG ),
DISPLAY_REFR_CNT_D = (BASE_REG << DISPLAY_REFR_CNT ),
LT24_CFG_D = (BASE_REG << LT24_CFG ),
LT24_REFRESH_D = (BASE_REG << LT24_REFRESH ),
LT24_REFRESH_SYNC_D = (BASE_REG << LT24_REFRESH_SYNC ),
LT24_CMD_D = (BASE_REG << LT24_CMD ),
LT24_CMD_PARAM_D = (BASE_REG << LT24_CMD_PARAM ),
LT24_CMD_DFILL_D = (BASE_REG << LT24_CMD_DFILL ),
LT24_STATUS_D = (BASE_REG << LT24_STATUS ),
LUT_CFG_D = (BASE_REG << LUT_CFG ),
LUT_RAM_ADDR_D = (BASE_REG << LUT_RAM_ADDR ),
LUT_RAM_DATA_D = (BASE_REG << LUT_RAM_DATA ),
FRAME_SELECT_D = (BASE_REG << FRAME_SELECT ),
FRAME0_PTR_LO_D = (BASE_REG << FRAME0_PTR_LO ),
FRAME0_PTR_HI_D = (BASE_REG << FRAME0_PTR_HI ),
FRAME1_PTR_LO_D = (BASE_REG << FRAME1_PTR_LO ),
FRAME1_PTR_HI_D = (BASE_REG << FRAME1_PTR_HI ),
FRAME2_PTR_LO_D = (BASE_REG << FRAME2_PTR_LO ),
FRAME2_PTR_HI_D = (BASE_REG << FRAME2_PTR_HI ),
FRAME3_PTR_LO_D = (BASE_REG << FRAME3_PTR_LO ),
FRAME3_PTR_HI_D = (BASE_REG << FRAME3_PTR_HI ),
VID_RAM0_CFG_D = (BASE_REG << VID_RAM0_CFG ),
VID_RAM0_WIDTH_D = (BASE_REG << VID_RAM0_WIDTH ),
VID_RAM0_ADDR_LO_D = (BASE_REG << VID_RAM0_ADDR_LO ),
VID_RAM0_ADDR_HI_D = (BASE_REG << VID_RAM0_ADDR_HI ),
VID_RAM0_DATA_D = (BASE_REG << VID_RAM0_DATA ),
VID_RAM1_CFG_D = (BASE_REG << VID_RAM1_CFG ),
VID_RAM1_WIDTH_D = (BASE_REG << VID_RAM1_WIDTH ),
VID_RAM1_ADDR_LO_D = (BASE_REG << VID_RAM1_ADDR_LO ),
VID_RAM1_ADDR_HI_D = (BASE_REG << VID_RAM1_ADDR_HI ),
VID_RAM1_DATA_D = (BASE_REG << VID_RAM1_DATA ),
GPU_CMD_LO_D = (BASE_REG << GPU_CMD_LO ),
GPU_CMD_HI_D = (BASE_REG << GPU_CMD_HI ),
GPU_STAT_D = (BASE_REG << GPU_STAT );
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en_i & (per_addr_i[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr_i[DEC_WD-2:0], 1'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (GFX_CTRL_D & {DEC_SZ{(reg_addr == GFX_CTRL )}}) |
(GFX_STATUS_D & {DEC_SZ{(reg_addr == GFX_STATUS )}}) |
(GFX_IRQ_D & {DEC_SZ{(reg_addr == GFX_IRQ )}}) |
(DISPLAY_WIDTH_D & {DEC_SZ{(reg_addr == DISPLAY_WIDTH )}}) |
(DISPLAY_HEIGHT_D & {DEC_SZ{(reg_addr == DISPLAY_HEIGHT )}}) |
(DISPLAY_SIZE_LO_D & {DEC_SZ{(reg_addr == DISPLAY_SIZE_LO )}}) |
(DISPLAY_SIZE_HI_D & {DEC_SZ{(reg_addr == DISPLAY_SIZE_HI )}}) |
(DISPLAY_CFG_D & {DEC_SZ{(reg_addr == DISPLAY_CFG )}}) |
(DISPLAY_REFR_CNT_D & {DEC_SZ{(reg_addr == DISPLAY_REFR_CNT )}}) |
(LT24_CFG_D & {DEC_SZ{(reg_addr == LT24_CFG )}}) |
(LT24_REFRESH_D & {DEC_SZ{(reg_addr == LT24_REFRESH )}}) |
(LT24_REFRESH_SYNC_D & {DEC_SZ{(reg_addr == LT24_REFRESH_SYNC )}}) |
(LT24_CMD_D & {DEC_SZ{(reg_addr == LT24_CMD )}}) |
(LT24_CMD_PARAM_D & {DEC_SZ{(reg_addr == LT24_CMD_PARAM )}}) |
(LT24_CMD_DFILL_D & {DEC_SZ{(reg_addr == LT24_CMD_DFILL )}}) |
(LT24_STATUS_D & {DEC_SZ{(reg_addr == LT24_STATUS )}}) |
(LUT_CFG_D & {DEC_SZ{(reg_addr == LUT_CFG )}}) |
(LUT_RAM_ADDR_D & {DEC_SZ{(reg_addr == LUT_RAM_ADDR )}}) |
(LUT_RAM_DATA_D & {DEC_SZ{(reg_addr == LUT_RAM_DATA )}}) |
(FRAME_SELECT_D & {DEC_SZ{(reg_addr == FRAME_SELECT )}}) |
(FRAME0_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME0_PTR_LO )}}) |
(FRAME0_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME0_PTR_HI )}}) |
(FRAME1_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME1_PTR_LO )}}) |
(FRAME1_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME1_PTR_HI )}}) |
(FRAME2_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME2_PTR_LO )}}) |
(FRAME2_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME2_PTR_HI )}}) |
(FRAME3_PTR_LO_D & {DEC_SZ{(reg_addr == FRAME3_PTR_LO )}}) |
(FRAME3_PTR_HI_D & {DEC_SZ{(reg_addr == FRAME3_PTR_HI )}}) |
(VID_RAM0_CFG_D & {DEC_SZ{(reg_addr == VID_RAM0_CFG )}}) |
(VID_RAM0_WIDTH_D & {DEC_SZ{(reg_addr == VID_RAM0_WIDTH )}}) |
(VID_RAM0_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM0_ADDR_LO )}}) |
(VID_RAM0_ADDR_HI_D & {DEC_SZ{(reg_addr == VID_RAM0_ADDR_HI )}}) |
(VID_RAM0_DATA_D & {DEC_SZ{(reg_addr == VID_RAM0_DATA )}}) |
(VID_RAM1_CFG_D & {DEC_SZ{(reg_addr == VID_RAM1_CFG )}}) |
(VID_RAM1_WIDTH_D & {DEC_SZ{(reg_addr == VID_RAM1_WIDTH )}}) |
(VID_RAM1_ADDR_LO_D & {DEC_SZ{(reg_addr == VID_RAM1_ADDR_LO )}}) |
(VID_RAM1_ADDR_HI_D & {DEC_SZ{(reg_addr == VID_RAM1_ADDR_HI )}}) |
(VID_RAM1_DATA_D & {DEC_SZ{(reg_addr == VID_RAM1_DATA )}}) |
(GPU_CMD_LO_D & {DEC_SZ{(reg_addr == GPU_CMD_LO )}}) |
(GPU_CMD_HI_D & {DEC_SZ{(reg_addr == GPU_CMD_HI )}}) |
(GPU_STAT_D & {DEC_SZ{(reg_addr == GPU_STAT )}});
// Read/Write probes
wire reg_write = |per_we_i & reg_sel;
wire reg_read = ~|per_we_i & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
// Other wire declarations
wire [`APIX_MSB:0] frame0_ptr;
`ifdef WITH_FRAME1_POINTER
wire [`APIX_MSB:0] frame1_ptr;
`endif
`ifdef WITH_FRAME2_POINTER
wire [`APIX_MSB:0] frame2_ptr;
`endif
`ifdef WITH_FRAME3_POINTER
wire [`APIX_MSB:0] frame3_ptr;
`endif
wire [`APIX_MSB:0] vid_ram0_base_addr;
wire [`APIX_MSB:0] vid_ram1_base_addr;
wire refr_cnt_done_evt;
wire gpu_fifo_done_evt;
wire gpu_fifo_ovfl_evt;
//============================================================================
// 3) REGISTERS
//============================================================================
//------------------------------------------------
// GFX_CTRL Register
//------------------------------------------------
reg [15:0] gfx_ctrl;
wire gfx_ctrl_wr = reg_wr[GFX_CTRL];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) gfx_ctrl <= 16'h0000;
else if (gfx_ctrl_wr) gfx_ctrl <= per_din_i;
// Bitfield assignments
wire gfx_irq_refr_done_en = gfx_ctrl[0];
wire gfx_irq_refr_start_en = gfx_ctrl[1];
wire gfx_irq_refr_cnt_done_en = gfx_ctrl[2];
wire gfx_irq_gpu_fifo_done_en = gfx_ctrl[4];
wire gfx_irq_gpu_fifo_ovfl_en = gfx_ctrl[5];
wire gfx_irq_gpu_cmd_done_en = gfx_ctrl[6];
wire gfx_irq_gpu_cmd_error_en = gfx_ctrl[7];
assign gfx_mode_o = gfx_ctrl[10:8]; // 1xx: 16 bits-per-pixel
// 011: 8 bits-per-pixel
// 010: 4 bits-per-pixel
// 001: 2 bits-per-pixel
// 000: 1 bits-per-pixel
wire gpu_enable_o = gfx_ctrl[12];
// Video modes decoding
wire gfx_mode_1_bpp = (gfx_mode_o == 3'b000);
wire gfx_mode_2_bpp = (gfx_mode_o == 3'b001);
wire gfx_mode_4_bpp = (gfx_mode_o == 3'b010);
wire gfx_mode_8_bpp = (gfx_mode_o == 3'b011);
wire gfx_mode_16_bpp = ~(gfx_mode_8_bpp | gfx_mode_4_bpp | gfx_mode_2_bpp | gfx_mode_1_bpp);
//------------------------------------------------
// GFX_STATUS Register
//------------------------------------------------
wire [15:0] gfx_status;
wire gpu_busy;
assign gfx_status[0] = lt24_status_i[2]; // Screen Refresh is busy
assign gfx_status[3:1] = 3'b000;
assign gfx_status[4] = gpu_data_avail_o;
assign gfx_status[5] = 1'b0;
assign gfx_status[6] = gpu_busy;
assign gfx_status[7] = 1'b0;
assign gfx_status[15:8] = 15'h0000;
//------------------------------------------------
// GFX_IRQ Register
//------------------------------------------------
wire [15:0] gfx_irq;
// Clear IRQ when 1 is written. Set IRQ when FSM is done
wire gfx_irq_refr_done_clr = per_din_i[0] & reg_wr[GFX_IRQ];
wire gfx_irq_refr_done_set = lt24_done_evt_i;
wire gfx_irq_refr_start_clr = per_din_i[1] & reg_wr[GFX_IRQ];
wire gfx_irq_refr_start_set = lt24_start_evt_i;
wire gfx_irq_refr_cnt_done_clr = per_din_i[2] & reg_wr[GFX_IRQ];
wire gfx_irq_refr_cnt_done_set = refr_cnt_done_evt;
wire gfx_irq_gpu_fifo_done_clr = per_din_i[4] & reg_wr[GFX_IRQ];
wire gfx_irq_gpu_fifo_done_set = gpu_fifo_done_evt;
wire gfx_irq_gpu_fifo_ovfl_clr = per_din_i[5] & reg_wr[GFX_IRQ];
wire gfx_irq_gpu_fifo_ovfl_set = gpu_fifo_ovfl_evt;
wire gfx_irq_gpu_cmd_done_clr = per_din_i[6] & reg_wr[GFX_IRQ];
wire gfx_irq_gpu_cmd_done_set = gpu_cmd_done_evt_i;
wire gfx_irq_gpu_cmd_error_clr = per_din_i[7] & reg_wr[GFX_IRQ];
wire gfx_irq_gpu_cmd_error_set = gpu_cmd_error_evt_i;
reg gfx_irq_refr_done;
reg gfx_irq_refr_start;
reg gfx_irq_refr_cnt_done;
reg gfx_irq_gpu_fifo_done;
reg gfx_irq_gpu_fifo_ovfl;
reg gfx_irq_gpu_cmd_done;
reg gfx_irq_gpu_cmd_error;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
gfx_irq_refr_done <= 1'b0;
gfx_irq_refr_start <= 1'b0;
gfx_irq_refr_cnt_done <= 1'b0;
gfx_irq_gpu_fifo_done <= 1'b0;
gfx_irq_gpu_fifo_ovfl <= 1'b0;
gfx_irq_gpu_cmd_done <= 1'b0;
gfx_irq_gpu_cmd_error <= 1'b0;
end
else
begin
gfx_irq_refr_done <= (gfx_irq_refr_done_set | (~gfx_irq_refr_done_clr & gfx_irq_refr_done )); // IRQ set has priority over clear
gfx_irq_refr_start <= (gfx_irq_refr_start_set | (~gfx_irq_refr_start_clr & gfx_irq_refr_start )); // IRQ set has priority over clear
gfx_irq_refr_cnt_done <= (gfx_irq_refr_cnt_done_set | (~gfx_irq_refr_cnt_done_clr & gfx_irq_refr_cnt_done)); // IRQ set has priority over clear
gfx_irq_gpu_fifo_done <= (gfx_irq_gpu_fifo_done_set | (~gfx_irq_gpu_fifo_done_clr & gfx_irq_gpu_fifo_done)); // IRQ set has priority over clear
gfx_irq_gpu_fifo_ovfl <= (gfx_irq_gpu_fifo_ovfl_set | (~gfx_irq_gpu_fifo_ovfl_clr & gfx_irq_gpu_fifo_ovfl)); // IRQ set has priority over clear
gfx_irq_gpu_cmd_done <= (gfx_irq_gpu_cmd_done_set | (~gfx_irq_gpu_cmd_done_clr & gfx_irq_gpu_cmd_done )); // IRQ set has priority over clear
gfx_irq_gpu_cmd_error <= (gfx_irq_gpu_cmd_error_set | (~gfx_irq_gpu_cmd_error_clr & gfx_irq_gpu_cmd_error)); // IRQ set has priority over clear
end
assign gfx_irq = {8'h00,
gfx_irq_gpu_cmd_error, gfx_irq_gpu_cmd_done, gfx_irq_gpu_fifo_ovfl, gfx_irq_gpu_fifo_done,
2'h0, gfx_irq_refr_start, gfx_irq_refr_done};
assign irq_gfx_o = (gfx_irq_refr_done & gfx_irq_refr_done_en) |
(gfx_irq_refr_start & gfx_irq_refr_start_en) |
(gfx_irq_refr_cnt_done & gfx_irq_refr_cnt_done_en) |
(gfx_irq_gpu_cmd_error & gfx_irq_gpu_cmd_error_en) |
(gfx_irq_gpu_cmd_done & gfx_irq_gpu_cmd_done_en) |
(gfx_irq_gpu_fifo_ovfl & gfx_irq_gpu_fifo_ovfl_en) |
(gfx_irq_gpu_fifo_done & gfx_irq_gpu_fifo_done_en); // Graphic Controller interrupt
//------------------------------------------------
// DISPLAY_WIDTH Register
//------------------------------------------------
reg [`LPIX_MSB:0] display_width_o;
wire display_width_wr = reg_wr[DISPLAY_WIDTH];
wire [`LPIX_MSB:0] display_w_h_nxt = (|per_din_i[`LPIX_MSB:0]) ? per_din_i[`LPIX_MSB:0] :
{{`LPIX_MSB{1'b0}}, 1'b1};
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_width_o <= {{`LPIX_MSB{1'b0}}, 1'b1};
else if (display_width_wr) display_width_o <= display_w_h_nxt;
wire [16:0] display_width_tmp = {{16-`LPIX_MSB{1'b0}}, display_width_o};
wire [15:0] display_width_rd = display_width_tmp[15:0];
//------------------------------------------------
// DISPLAY_HEIGHT Register
//------------------------------------------------
reg [`LPIX_MSB:0] display_height_o;
wire display_height_wr = reg_wr[DISPLAY_HEIGHT];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_height_o <= {{`LPIX_MSB{1'b0}}, 1'b1};
else if (display_height_wr) display_height_o <= display_w_h_nxt;
wire [16:0] display_height_tmp = {{16-`LPIX_MSB{1'b0}}, display_height_o};
wire [15:0] display_height_rd = display_height_tmp[15:0];
//------------------------------------------------
// DISPLAY_SIZE_HI Register
//------------------------------------------------
`ifdef WITH_DISPLAY_SIZE_HI
reg [`SPIX_HI_MSB:0] display_size_hi;
wire display_size_hi_wr = reg_wr[DISPLAY_SIZE_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_size_hi <= {`SPIX_HI_MSB+1{1'h0}};
else if (display_size_hi_wr) display_size_hi <= per_din_i[`SPIX_HI_MSB:0];
wire [16:0] display_size_hi_tmp = {{16-`SPIX_HI_MSB{1'h0}}, display_size_hi};
wire [15:0] display_size_hi_rd = display_size_hi_tmp[15:0];
`endif
//------------------------------------------------
// DISPLAY_SIZE_LO Register
//------------------------------------------------
reg [`SPIX_LO_MSB:0] display_size_lo;
wire display_size_lo_wr = reg_wr[DISPLAY_SIZE_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_size_lo <= {{`SPIX_LO_MSB{1'h0}}, 1'b1};
else if (display_size_lo_wr) display_size_lo <= per_din_i[`SPIX_LO_MSB:0];
wire [16:0] display_size_lo_tmp = {{16-`SPIX_LO_MSB{1'h0}}, display_size_lo};
wire [15:0] display_size_lo_rd = display_size_lo_tmp[15:0];
`ifdef WITH_DISPLAY_SIZE_HI
assign display_size_o = {display_size_hi, display_size_lo};
`else
assign display_size_o = display_size_lo;
`endif
//------------------------------------------------
// DISPLAY_CFG Register
//------------------------------------------------
reg display_x_swap_o;
reg display_y_swap_o;
reg display_cl_swap_o;
wire display_cfg_wr = reg_wr[DISPLAY_CFG];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
display_cl_swap_o <= 1'b0;
display_y_swap_o <= 1'b0;
display_x_swap_o <= 1'b0;
end
else if (display_cfg_wr)
begin
display_cl_swap_o <= per_din_i[0];
display_y_swap_o <= per_din_i[1];
display_x_swap_o <= per_din_i[2];
end
wire [15:0] display_cfg = {13'h0000,
display_x_swap_o,
display_y_swap_o,
display_cl_swap_o};
//------------------------------------------------
// DISPLAY_REFR_CNT Register
//------------------------------------------------
reg [15:0] display_refr_cnt;
wire display_refr_cnt_wr = reg_wr[DISPLAY_REFR_CNT];
wire display_refr_cnt_dec = gfx_irq_refr_done_set & (display_refr_cnt != 16'h0000);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) display_refr_cnt <= 16'h0000;
else if (display_refr_cnt_wr) display_refr_cnt <= per_din_i;
else if (display_refr_cnt_dec) display_refr_cnt <= display_refr_cnt + 16'hFFFF; // -1
assign refr_cnt_done_evt = (display_refr_cnt==16'h0001) & display_refr_cnt_dec;
//------------------------------------------------
// LT24_CFG Register
//------------------------------------------------
reg [15:0] lt24_cfg;
wire lt24_cfg_wr = reg_wr[LT24_CFG];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cfg <= 16'h0000;
else if (lt24_cfg_wr) lt24_cfg <= per_din_i;
// Bitfield assignments
assign lt24_cfg_clk_o = lt24_cfg[6:4];
assign lt24_reset_n_o = ~lt24_cfg[1];
assign lt24_on_o = lt24_cfg[0];
//------------------------------------------------
// LT24_REFRESH Register
//------------------------------------------------
reg lt24_cmd_refr_o;
reg [11:0] lt24_cfg_refr_o;
wire lt24_refresh_wr = reg_wr[LT24_REFRESH];
wire lt24_cmd_refr_clr = lt24_done_evt_i & lt24_status_i[2] & (lt24_cfg_refr_o==12'h000); // Auto-clear in manual refresh mode when done
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd_refr_o <= 1'h0;
else if (lt24_refresh_wr) lt24_cmd_refr_o <= per_din_i[0];
else if (lt24_cmd_refr_clr) lt24_cmd_refr_o <= 1'h0;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cfg_refr_o <= 12'h000;
else if (lt24_refresh_wr) lt24_cfg_refr_o <= per_din_i[15:4];
wire [15:0] lt24_refresh = {lt24_cfg_refr_o, 3'h0, lt24_cmd_refr_o};
//------------------------------------------------
// LT24_REFRESH_SYNC Register
//------------------------------------------------
reg lt24_cfg_refr_sync_en_o;
reg [9:0] lt24_cfg_refr_sync_val_o;
wire lt24_refresh_sync_wr = reg_wr[LT24_REFRESH_SYNC];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cfg_refr_sync_en_o <= 1'h0;
else if (lt24_refresh_sync_wr) lt24_cfg_refr_sync_en_o <= per_din_i[15];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cfg_refr_sync_val_o <= 10'h000;
else if (lt24_refresh_sync_wr) lt24_cfg_refr_sync_val_o <= per_din_i[9:0];
wire [15:0] lt24_refresh_sync = {lt24_cfg_refr_sync_en_o, 5'h00, lt24_cfg_refr_sync_val_o};
//------------------------------------------------
// LT24_CMD Register
//------------------------------------------------
reg [15:0] lt24_cmd;
wire lt24_cmd_wr = reg_wr[LT24_CMD];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd <= 16'h0000;
else if (lt24_cmd_wr) lt24_cmd <= per_din_i;
assign lt24_cmd_val_o = lt24_cmd[7:0];
assign lt24_cmd_has_param_o = lt24_cmd[8];
//------------------------------------------------
// LT24_CMD_PARAM Register
//------------------------------------------------
reg [15:0] lt24_cmd_param_o;
wire lt24_cmd_param_wr = reg_wr[LT24_CMD_PARAM];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd_param_o <= 16'h0000;
else if (lt24_cmd_param_wr) lt24_cmd_param_o <= per_din_i;
reg lt24_cmd_param_rdy_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd_param_rdy_o <= 1'b0;
else lt24_cmd_param_rdy_o <= lt24_cmd_param_wr;
//------------------------------------------------
// LT24_CMD_DFILL Register
//------------------------------------------------
reg [15:0] lt24_cmd_dfill_o;
assign lt24_cmd_dfill_wr_o = reg_wr[LT24_CMD_DFILL];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lt24_cmd_dfill_o <= 16'h0000;
else if (lt24_cmd_dfill_wr_o) lt24_cmd_dfill_o <= per_din_i;
//------------------------------------------------
// LT24_STATUS Register
//------------------------------------------------
wire [15:0] lt24_status;
assign lt24_status[0] = lt24_status_i[0]; // FSM_BUSY
assign lt24_status[1] = lt24_status_i[1]; // WAIT_PARAM
assign lt24_status[2] = lt24_status_i[2]; // REFRESH_BUSY
assign lt24_status[3] = lt24_status_i[3]; // WAIT_FOR_SCANLINE
assign lt24_status[4] = lt24_status_i[4]; // DATA_FILL_BUSY
assign lt24_status[15:5] = 11'h000;
//------------------------------------------------
// LUT_CFG Register
//------------------------------------------------
wire lut_cfg_wr = reg_wr[LUT_CFG];
`ifdef WITH_PROGRAMMABLE_LUT
reg sw_lut_enable_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sw_lut_enable_o <= 1'b0;
else if (lut_cfg_wr) sw_lut_enable_o <= per_din_i[0]; // Enable software color LUT
reg sw_lut_ram_rmw_mode;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sw_lut_ram_rmw_mode <= 1'b0;
else if (lut_cfg_wr) sw_lut_ram_rmw_mode <= per_din_i[1];
`ifdef WITH_EXTRA_LUT_BANK
reg sw_lut_bank_select_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) sw_lut_bank_select_o <= 1'b0;
else if (lut_cfg_wr) sw_lut_bank_select_o <= per_din_i[2];
`else
assign sw_lut_bank_select_o = 1'b0;
`endif
`else
assign sw_lut_bank_select_o = 1'b0;
assign sw_lut_enable_o = 1'b0;
wire sw_lut_ram_rmw_mode = 1'b0;
`endif
reg [2:0] hw_lut_palette_sel_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) hw_lut_palette_sel_o <= 3'h0;
else if (lut_cfg_wr) hw_lut_palette_sel_o <= per_din_i[6:4];
reg [3:0] hw_lut_bgcolor_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) hw_lut_bgcolor_o <= 4'h0;
else if (lut_cfg_wr) hw_lut_bgcolor_o <= per_din_i[11:8];
reg [3:0] hw_lut_fgcolor_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) hw_lut_fgcolor_o <= 4'hf;
else if (lut_cfg_wr) hw_lut_fgcolor_o <= per_din_i[15:12];
wire [15:0] lut_cfg_rd = {hw_lut_fgcolor_o, hw_lut_bgcolor_o,
1'b0, hw_lut_palette_sel_o,
1'b0, sw_lut_bank_select_o,
sw_lut_ram_rmw_mode, sw_lut_enable_o};
//------------------------------------------------
// LUT_RAM_ADDR Register
//------------------------------------------------
`ifdef WITH_PROGRAMMABLE_LUT
reg [7:0] lut_ram_addr;
wire [8:0] lut_ram_addr_inc;
wire lut_ram_addr_inc_wr;
wire lut_ram_addr_wr = reg_wr[LUT_RAM_ADDR];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_addr <= 8'h00;
else if (lut_ram_addr_wr) lut_ram_addr <= per_din_i[7:0];
else if (lut_ram_addr_inc_wr) lut_ram_addr <= lut_ram_addr_inc[7:0];
`ifdef WITH_EXTRA_LUT_BANK
reg lut_bank_select;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_bank_select <= 1'b0;
else if (lut_ram_addr_wr) lut_bank_select <= per_din_i[8];
else if (lut_ram_addr_inc_wr) lut_bank_select <= lut_ram_addr_inc[8];
`else
wire lut_bank_select = 1'b0;
`endif
assign lut_ram_addr_inc = {lut_bank_select, lut_ram_addr} + 9'h001;
wire [15:0] lut_ram_addr_rd = {7'h00, lut_bank_select, lut_ram_addr};
`ifdef WITH_EXTRA_LUT_BANK
assign lut_ram_addr_o = {lut_bank_select, lut_ram_addr};
`else
assign lut_ram_addr_o = lut_ram_addr;
`endif
`else
wire [15:0] lut_ram_addr_rd = 16'h0000;
`endif
//------------------------------------------------
// LUT_RAM_DATA Register
//------------------------------------------------
`ifdef WITH_PROGRAMMABLE_LUT
// Update the LUT_RAM_DATA register with regular register write access
wire lut_ram_data_wr = reg_wr[LUT_RAM_DATA];
wire lut_ram_data_rd = reg_rd[LUT_RAM_DATA];
reg lut_ram_dout_rdy;
// LUT-RAM data Register
reg [15:0] lut_ram_data;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_data <= 16'h0000;
else if (lut_ram_data_wr) lut_ram_data <= per_din_i;
else if (lut_ram_dout_rdy) lut_ram_data <= lut_ram_dout_i;
// Increment the address after a write or read access to the LUT_RAM_DATA register
// - one clock cycle after a write access
// - with the read access (if not in read-modify-write mode)
assign lut_ram_addr_inc_wr = lut_ram_data_wr | (lut_ram_data_rd & ~dbg_freeze_i & ~sw_lut_ram_rmw_mode);
// Apply peripheral data bus % write strobe during VID_RAMx_DATA write access
assign lut_ram_din_o = per_din_i & {16{lut_ram_data_wr}};
assign lut_ram_wen_o = ~(|per_we_i & lut_ram_data_wr);
// Trigger a LUT-RAM read access immediately after:
// - a LUT-RAM_ADDR register write access
// - a LUT-RAM_DATA register read access
reg lut_ram_addr_wr_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_addr_wr_dly <= 1'b0;
else lut_ram_addr_wr_dly <= lut_ram_addr_wr;
reg lut_ram_data_rd_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_data_rd_dly <= 1'b0;
else lut_ram_data_rd_dly <= lut_ram_data_rd;
// Chip enable.
// Note: we perform a data read access:
// - one cycle after a VID_RAM_DATA register read access (so that the address has been incremented)
// - one cycle after a VID_RAM_ADDR register write
assign lut_ram_cen_o = ~(lut_ram_addr_wr_dly | lut_ram_data_rd_dly | // Read access
lut_ram_data_wr); // Write access
// Update the VRAM_DATA register one cycle after each memory access
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) lut_ram_dout_rdy <= 1'b0;
else lut_ram_dout_rdy <= ~lut_ram_cen_o;
`else
wire [15:0] lut_ram_data = 16'h0000;
`endif
//------------------------------------------------
// FRAME_SELECT Register
//------------------------------------------------
wire frame_select_wr = reg_wr[FRAME_SELECT];
`ifdef WITH_FRAME1_POINTER
`ifdef WITH_FRAME2_POINTER
reg [1:0] refresh_frame_select;
reg [1:0] vid_ram0_frame_select;
reg [1:0] vid_ram1_frame_select;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
refresh_frame_select <= 2'h0;
vid_ram0_frame_select <= 2'h0;
vid_ram1_frame_select <= 2'h0;
end
else if (frame_select_wr)
begin
refresh_frame_select <= per_din_i[1:0];
vid_ram0_frame_select <= per_din_i[9:8];
vid_ram1_frame_select <= per_din_i[13:12];
end
wire [15:0] frame_select = {2'h0, vid_ram1_frame_select, 2'h0, vid_ram0_frame_select, 6'h00, refresh_frame_select};
`else
reg refresh_frame_select;
reg vid_ram0_frame_select;
reg vid_ram1_frame_select;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst)
begin
refresh_frame_select <= 1'h0;
vid_ram0_frame_select <= 1'h0;
vid_ram1_frame_select <= 1'h0;
end
else if (frame_select_wr)
begin
refresh_frame_select <= per_din_i[0];
vid_ram0_frame_select <= per_din_i[8];
vid_ram1_frame_select <= per_din_i[12];
end
wire [15:0] frame_select = {3'h0, vid_ram1_frame_select, 3'h0, vid_ram0_frame_select, 7'h00, refresh_frame_select};
`endif
`else
wire [15:0] frame_select = 16'h0000;
`endif
// Frame pointer selections
`ifdef WITH_FRAME1_POINTER
assign refresh_frame_addr_o = (refresh_frame_select==0) ? frame0_ptr :
`ifdef WITH_FRAME2_POINTER
(refresh_frame_select==1) ? frame1_ptr :
`ifdef WITH_FRAME3_POINTER
(refresh_frame_select==2) ? frame2_ptr :
frame3_ptr ;
`else
frame2_ptr ;
`endif
`else
frame1_ptr ;
`endif
assign vid_ram0_base_addr = (vid_ram0_frame_select==0) ? frame0_ptr :
`ifdef WITH_FRAME2_POINTER
(vid_ram0_frame_select==1) ? frame1_ptr :
`ifdef WITH_FRAME3_POINTER
(vid_ram0_frame_select==2) ? frame2_ptr :
frame3_ptr ;
`else
frame2_ptr ;
`endif
`else
frame1_ptr ;
`endif
assign vid_ram1_base_addr = (vid_ram1_frame_select==0) ? frame0_ptr :
`ifdef WITH_FRAME2_POINTER
(vid_ram1_frame_select==1) ? frame1_ptr :
`ifdef WITH_FRAME3_POINTER
(vid_ram1_frame_select==2) ? frame2_ptr :
frame3_ptr ;
`else
frame2_ptr ;
`endif
`else
frame1_ptr ;
`endif
`else
assign refresh_frame_addr_o = frame0_ptr;
assign vid_ram0_base_addr = frame0_ptr;
assign vid_ram1_base_addr = frame0_ptr;
`endif
//------------------------------------------------
// FRAME0_PTR_HI Register
//------------------------------------------------
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] frame0_ptr_hi;
wire frame0_ptr_hi_wr = reg_wr[FRAME0_PTR_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame0_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
else if (frame0_ptr_hi_wr) frame0_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
wire [16:0] frame0_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}}, frame0_ptr_hi};
wire [15:0] frame0_ptr_hi_rd = frame0_ptr_hi_tmp[15:0];
`endif
//------------------------------------------------
// FRAME0_PTR_LO Register
//------------------------------------------------
reg [`APIX_LO_MSB:0] frame0_ptr_lo;
wire frame0_ptr_lo_wr = reg_wr[FRAME0_PTR_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame0_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
else if (frame0_ptr_lo_wr) frame0_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
`ifdef VRAM_BIGGER_4_KW
assign frame0_ptr = {frame0_ptr_hi[`APIX_HI_MSB:0], frame0_ptr_lo};
wire [15:0] frame0_ptr_lo_rd = frame0_ptr_lo;
`else
assign frame0_ptr = {frame0_ptr_lo[`APIX_LO_MSB:0]};
wire [16:0] frame0_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame0_ptr_lo};
wire [15:0] frame0_ptr_lo_rd = frame0_ptr_lo_tmp[15:0];
`endif
//------------------------------------------------
// FRAME1_PTR_HI Register
//------------------------------------------------
`ifdef WITH_FRAME1_POINTER
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] frame1_ptr_hi;
wire frame1_ptr_hi_wr = reg_wr[FRAME1_PTR_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame1_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
else if (frame1_ptr_hi_wr) frame1_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
wire [16:0] frame1_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}}, frame1_ptr_hi};
wire [15:0] frame1_ptr_hi_rd = frame1_ptr_hi_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME1_PTR_LO Register
//------------------------------------------------
`ifdef WITH_FRAME1_POINTER
reg [`APIX_LO_MSB:0] frame1_ptr_lo;
wire frame1_ptr_lo_wr = reg_wr[FRAME1_PTR_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame1_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
else if (frame1_ptr_lo_wr) frame1_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
`ifdef VRAM_BIGGER_4_KW
assign frame1_ptr = {frame1_ptr_hi[`APIX_HI_MSB:0], frame1_ptr_lo};
wire [15:0] frame1_ptr_lo_rd = frame1_ptr_lo;
`else
assign frame1_ptr = {frame1_ptr_lo[`APIX_LO_MSB:0]};
wire [16:0] frame1_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame1_ptr_lo};
wire [15:0] frame1_ptr_lo_rd = frame1_ptr_lo_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME2_PTR_HI Register
//------------------------------------------------
`ifdef WITH_FRAME2_POINTER
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] frame2_ptr_hi;
wire frame2_ptr_hi_wr = reg_wr[FRAME2_PTR_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame2_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
else if (frame2_ptr_hi_wr) frame2_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
wire [16:0] frame2_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}}, frame2_ptr_hi};
wire [15:0] frame2_ptr_hi_rd = frame2_ptr_hi_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME2_PTR_LO Register
//------------------------------------------------
`ifdef WITH_FRAME2_POINTER
reg [`APIX_LO_MSB:0] frame2_ptr_lo;
wire frame2_ptr_lo_wr = reg_wr[FRAME2_PTR_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame2_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
else if (frame2_ptr_lo_wr) frame2_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
`ifdef VRAM_BIGGER_4_KW
assign frame2_ptr = {frame2_ptr_hi[`APIX_HI_MSB:0], frame2_ptr_lo};
wire [15:0] frame2_ptr_lo_rd = frame2_ptr_lo;
`else
assign frame2_ptr = {frame2_ptr_lo[`APIX_LO_MSB:0]};
wire [16:0] frame2_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame2_ptr_lo};
wire [15:0] frame2_ptr_lo_rd = frame2_ptr_lo_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME3_PTR_HI Register
//------------------------------------------------
`ifdef WITH_FRAME3_POINTER
`ifdef VRAM_BIGGER_4_KW
reg [`APIX_HI_MSB:0] frame3_ptr_hi;
wire frame3_ptr_hi_wr = reg_wr[FRAME3_PTR_HI];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame3_ptr_hi <= {`APIX_HI_MSB+1{1'b0}};
else if (frame3_ptr_hi_wr) frame3_ptr_hi <= per_din_i[`APIX_HI_MSB:0];
wire [16:0] frame3_ptr_hi_tmp = {{16-`APIX_HI_MSB{1'b0}},frame3_ptr_hi};
wire [15:0] frame3_ptr_hi_rd = frame3_ptr_hi_tmp[15:0];
`endif
`endif
//------------------------------------------------
// FRAME3_PTR_LO Register
//------------------------------------------------
`ifdef WITH_FRAME3_POINTER
reg [`APIX_LO_MSB:0] frame3_ptr_lo;
wire frame3_ptr_lo_wr = reg_wr[FRAME3_PTR_LO];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) frame3_ptr_lo <= {`APIX_LO_MSB+1{1'b0}};
else if (frame3_ptr_lo_wr) frame3_ptr_lo <= per_din_i[`APIX_LO_MSB:0];
`ifdef VRAM_BIGGER_4_KW
assign frame3_ptr = {frame3_ptr_hi[`APIX_HI_MSB:0], frame3_ptr_lo};
wire [15:0] frame3_ptr_lo_rd = frame3_ptr_lo;
`else
assign frame3_ptr = {frame3_ptr_lo[`APIX_LO_MSB:0]};
wire [16:0] frame3_ptr_lo_tmp = {{16-`APIX_LO_MSB{1'b0}}, frame3_ptr_lo};
wire [15:0] frame3_ptr_lo_rd = frame3_ptr_lo_tmp[15:0];
`endif
`endif
//------------------------------------------------
// VID_RAM0 Interface
//------------------------------------------------
wire [15:0] vid_ram0_cfg;
wire [15:0] vid_ram0_width;
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram0_addr_hi;
`endif
wire [15:0] vid_ram0_addr_lo;
wire [15:0] vid_ram0_data;
wire vid_ram0_we;
wire vid_ram0_ce;
wire [15:0] vid_ram0_din;
wire [`APIX_MSB:0] vid_ram0_addr_nxt;
wire vid_ram0_access;
ogfx_reg_vram_if ogfx_reg_vram0_if_inst (
// OUTPUTs
.vid_ram_cfg_o ( vid_ram0_cfg ), // VID_RAM0_CFG Register
.vid_ram_width_o ( vid_ram0_width ), // VID_RAM0_WIDTH Register
`ifdef VRAM_BIGGER_4_KW
.vid_ram_addr_hi_o ( vid_ram0_addr_hi ), // VID_RAM0_ADDR_HI Register
`endif
.vid_ram_addr_lo_o ( vid_ram0_addr_lo ), // VID_RAM0_ADDR_LO Register
.vid_ram_data_o ( vid_ram0_data ), // VID_RAM0_DATA Register
.vid_ram_we_o ( vid_ram0_we ), // Video-RAM Write strobe
.vid_ram_ce_o ( vid_ram0_ce ), // Video-RAM Chip enable
.vid_ram_din_o ( vid_ram0_din ), // Video-RAM Data input
.vid_ram_addr_nxt_o ( vid_ram0_addr_nxt ), // Video-RAM Next address
.vid_ram_access_o ( vid_ram0_access ), // Video-RAM Access
// INPUTs
.mclk ( mclk ), // Main system clock
.puc_rst ( puc_rst ), // Main system reset
.vid_ram_cfg_wr_i ( reg_wr[VID_RAM0_CFG] ), // VID_RAM0_CFG Write strobe
.vid_ram_width_wr_i ( reg_wr[VID_RAM0_WIDTH] ), // VID_RAM0_WIDTH Write strobe
.vid_ram_addr_hi_wr_i ( reg_wr[VID_RAM0_ADDR_HI] ), // VID_RAM0_ADDR_HI Write strobe
.vid_ram_addr_lo_wr_i ( reg_wr[VID_RAM0_ADDR_LO] ), // VID_RAM0_ADDR_LO Write strobe
.vid_ram_data_wr_i ( reg_wr[VID_RAM0_DATA] ), // VID_RAM0_DATA Write strobe
.vid_ram_data_rd_i ( reg_rd[VID_RAM0_DATA] ), // VID_RAM0_DATA Read strobe
.dbg_freeze_i ( dbg_freeze_i ), // Freeze auto-increment on read when CPU stopped
.display_width_i ( display_width_o ), // Display width
.gfx_mode_1_bpp_i ( gfx_mode_1_bpp ), // Graphic mode 1 bpp resolution
.gfx_mode_2_bpp_i ( gfx_mode_2_bpp ), // Graphic mode 2 bpp resolution
.gfx_mode_4_bpp_i ( gfx_mode_4_bpp ), // Graphic mode 4 bpp resolution
.gfx_mode_8_bpp_i ( gfx_mode_8_bpp ), // Graphic mode 8 bpp resolution
.gfx_mode_16_bpp_i ( gfx_mode_16_bpp ), // Graphic mode 16 bpp resolution
.per_din_i ( per_din_i ), // Peripheral data input
.vid_ram_base_addr_i ( vid_ram0_base_addr ), // Video-RAM base address
.vid_ram_dout_i ( vid_ram_dout_i ) // Video-RAM data input
);
//------------------------------------------------
// VID_RAM1 Interface
//------------------------------------------------
wire [15:0] vid_ram1_cfg;
wire [15:0] vid_ram1_width;
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram1_addr_hi;
`endif
wire [15:0] vid_ram1_addr_lo;
wire [15:0] vid_ram1_data;
wire vid_ram1_we;
wire vid_ram1_ce;
wire [15:0] vid_ram1_din;
wire [`APIX_MSB:0] vid_ram1_addr_nxt;
wire vid_ram1_access;
ogfx_reg_vram_if ogfx_reg_vram1_if_inst (
// OUTPUTs
.vid_ram_cfg_o ( vid_ram1_cfg ), // VID_RAM1_CFG Register
.vid_ram_width_o ( vid_ram1_width ), // VID_RAM1_WIDTH Register
`ifdef VRAM_BIGGER_4_KW
.vid_ram_addr_hi_o ( vid_ram1_addr_hi ), // VID_RAM1_ADDR_HI Register
`endif
.vid_ram_addr_lo_o ( vid_ram1_addr_lo ), // VID_RAM1_ADDR_LO Register
.vid_ram_data_o ( vid_ram1_data ), // VID_RAM1_DATA Register
.vid_ram_we_o ( vid_ram1_we ), // Video-RAM Write strobe
.vid_ram_ce_o ( vid_ram1_ce ), // Video-RAM Chip enable
.vid_ram_din_o ( vid_ram1_din ), // Video-RAM Data input
.vid_ram_addr_nxt_o ( vid_ram1_addr_nxt ), // Video-RAM Next address
.vid_ram_access_o ( vid_ram1_access ), // Video-RAM Access
// INPUTs
.mclk ( mclk ), // Main system clock
.puc_rst ( puc_rst ), // Main system reset
.vid_ram_cfg_wr_i ( reg_wr[VID_RAM1_CFG] ), // VID_RAM1_CFG Write strobe
.vid_ram_width_wr_i ( reg_wr[VID_RAM1_WIDTH] ), // VID_RAM1_WIDTH Write strobe
.vid_ram_addr_hi_wr_i ( reg_wr[VID_RAM1_ADDR_HI] ), // VID_RAM1_ADDR_HI Write strobe
.vid_ram_addr_lo_wr_i ( reg_wr[VID_RAM1_ADDR_LO] ), // VID_RAM1_ADDR_LO Write strobe
.vid_ram_data_wr_i ( reg_wr[VID_RAM1_DATA] ), // VID_RAM1_DATA Write strobe
.vid_ram_data_rd_i ( reg_rd[VID_RAM1_DATA] ), // VID_RAM1_DATA Read strobe
.dbg_freeze_i ( dbg_freeze_i ), // Freeze auto-increment on read when CPU stopped
.display_width_i ( display_width_o ), // Display width
.gfx_mode_1_bpp_i ( gfx_mode_1_bpp ), // Graphic mode 1 bpp resolution
.gfx_mode_2_bpp_i ( gfx_mode_2_bpp ), // Graphic mode 2 bpp resolution
.gfx_mode_4_bpp_i ( gfx_mode_4_bpp ), // Graphic mode 4 bpp resolution
.gfx_mode_8_bpp_i ( gfx_mode_8_bpp ), // Graphic mode 8 bpp resolution
.gfx_mode_16_bpp_i ( gfx_mode_16_bpp ), // Graphic mode 16 bpp resolution
.per_din_i ( per_din_i ), // Peripheral data input
.vid_ram_base_addr_i ( vid_ram1_base_addr ), // Video-RAM base address
.vid_ram_dout_i ( vid_ram_dout_i ) // Video-RAM data input
);
//------------------------------------------------
// GPU Interface (GPU_CMD/GPU_STAT) Registers
//------------------------------------------------
wire [3:0] gpu_stat_fifo_cnt;
wire [3:0] gpu_stat_fifo_cnt_empty;
wire gpu_stat_fifo_empty;
wire gpu_stat_fifo_full;
wire gpu_stat_fifo_full_less_2;
wire gpu_stat_fifo_full_less_3;
ogfx_reg_fifo ogfx_reg_fifo_gpu_inst (
// OUTPUTs
.fifo_cnt_o ( gpu_stat_fifo_cnt ), // Fifo counter
.fifo_data_o ( gpu_data_o ), // Read data output
.fifo_done_evt_o ( gpu_fifo_done_evt ), // Fifo has been emptied
.fifo_empty_o ( gpu_stat_fifo_empty ), // Fifo is currentely empty
.fifo_empty_cnt_o ( gpu_stat_fifo_cnt_empty ), // Fifo empty words counter
.fifo_full_o ( gpu_stat_fifo_full ), // Fifo is currentely full
.fifo_ovfl_evt_o ( gpu_fifo_ovfl_evt ), // Fifo overflow event
// INPUTs
.mclk ( mclk ), // Main system clock
.puc_rst ( puc_rst ), // Main system reset
.fifo_data_i ( per_din_i ), // Read data input
.fifo_enable_i ( gpu_enable_o ), // Enable fifo (flushed when disabled)
.fifo_pop_i ( gpu_get_data_i ), // Pop data from the fifo
.fifo_push_i ( reg_wr[GPU_CMD_LO] |
reg_wr[GPU_CMD_HI] ) // Push new data to the fifo
);
assign gpu_data_avail_o = ~gpu_stat_fifo_empty;
assign gpu_busy = ~gpu_stat_fifo_empty | gpu_dma_busy_i;
wire [15:0] gpu_stat = {gpu_busy, 2'b00, gpu_dma_busy_i,
2'b00 , gpu_stat_fifo_full, gpu_stat_fifo_empty,
gpu_stat_fifo_cnt, gpu_stat_fifo_cnt_empty};
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] gfx_ctrl_read = gfx_ctrl & {16{reg_rd[GFX_CTRL ]}};
wire [15:0] gfx_status_read = gfx_status & {16{reg_rd[GFX_STATUS ]}};
wire [15:0] gfx_irq_read = gfx_irq & {16{reg_rd[GFX_IRQ ]}};
wire [15:0] display_width_read = display_width_rd & {16{reg_rd[DISPLAY_WIDTH ]}};
wire [15:0] display_height_read = display_height_rd & {16{reg_rd[DISPLAY_HEIGHT ]}};
wire [15:0] display_size_lo_read = display_size_lo_rd & {16{reg_rd[DISPLAY_SIZE_LO ]}};
`ifdef WITH_DISPLAY_SIZE_HI
wire [15:0] display_size_hi_read = display_size_hi_rd & {16{reg_rd[DISPLAY_SIZE_HI ]}};
`endif
wire [15:0] display_cfg_read = display_cfg & {16{reg_rd[DISPLAY_CFG ]}};
wire [15:0] display_refr_cnt_read = display_refr_cnt & {16{reg_rd[DISPLAY_REFR_CNT ]}};
wire [15:0] lt24_cfg_read = lt24_cfg & {16{reg_rd[LT24_CFG ]}};
wire [15:0] lt24_refresh_read = lt24_refresh & {16{reg_rd[LT24_REFRESH ]}};
wire [15:0] lt24_refresh_sync_read = lt24_refresh_sync & {16{reg_rd[LT24_REFRESH_SYNC ]}};
wire [15:0] lt24_cmd_read = lt24_cmd & {16{reg_rd[LT24_CMD ]}};
wire [15:0] lt24_cmd_param_read = lt24_cmd_param_o & {16{reg_rd[LT24_CMD_PARAM ]}};
wire [15:0] lt24_cmd_dfill_read = lt24_cmd_dfill_o & {16{reg_rd[LT24_CMD_DFILL ]}};
wire [15:0] lt24_status_read = lt24_status & {16{reg_rd[LT24_STATUS ]}};
wire [15:0] lut_cfg_read = lut_cfg_rd & {16{reg_rd[LUT_CFG ]}};
wire [15:0] lut_ram_addr_read = lut_ram_addr_rd & {16{reg_rd[LUT_RAM_ADDR ]}};
wire [15:0] lut_ram_data_read = lut_ram_data & {16{reg_rd[LUT_RAM_DATA ]}};
wire [15:0] frame_select_read = frame_select & {16{reg_rd[FRAME_SELECT ]}};
wire [15:0] frame0_ptr_lo_read = frame0_ptr_lo_rd & {16{reg_rd[FRAME0_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame0_ptr_hi_read = frame0_ptr_hi_rd & {16{reg_rd[FRAME0_PTR_HI ]}};
`endif
`ifdef WITH_FRAME1_POINTER
wire [15:0] frame1_ptr_lo_read = frame1_ptr_lo_rd & {16{reg_rd[FRAME1_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame1_ptr_hi_read = frame1_ptr_hi_rd & {16{reg_rd[FRAME1_PTR_HI ]}};
`endif
`endif
`ifdef WITH_FRAME2_POINTER
wire [15:0] frame2_ptr_lo_read = frame2_ptr_lo_rd & {16{reg_rd[FRAME2_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame2_ptr_hi_read = frame2_ptr_hi_rd & {16{reg_rd[FRAME2_PTR_HI ]}};
`endif
`endif
`ifdef WITH_FRAME3_POINTER
wire [15:0] frame3_ptr_lo_read = frame3_ptr_lo_rd & {16{reg_rd[FRAME3_PTR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] frame3_ptr_hi_read = frame3_ptr_hi_rd & {16{reg_rd[FRAME3_PTR_HI ]}};
`endif
`endif
wire [15:0] vid_ram0_cfg_read = vid_ram0_cfg & {16{reg_rd[VID_RAM0_CFG ]}};
wire [15:0] vid_ram0_width_read = vid_ram0_width & {16{reg_rd[VID_RAM0_WIDTH ]}};
wire [15:0] vid_ram0_addr_lo_read = vid_ram0_addr_lo & {16{reg_rd[VID_RAM0_ADDR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram0_addr_hi_read = vid_ram0_addr_hi & {16{reg_rd[VID_RAM0_ADDR_HI ]}};
`endif
wire [15:0] vid_ram0_data_read = vid_ram0_data & {16{reg_rd[VID_RAM0_DATA ]}};
wire [15:0] vid_ram1_cfg_read = vid_ram1_cfg & {16{reg_rd[VID_RAM1_CFG ]}};
wire [15:0] vid_ram1_width_read = vid_ram1_width & {16{reg_rd[VID_RAM1_WIDTH ]}};
wire [15:0] vid_ram1_addr_lo_read = vid_ram1_addr_lo & {16{reg_rd[VID_RAM1_ADDR_LO ]}};
`ifdef VRAM_BIGGER_4_KW
wire [15:0] vid_ram1_addr_hi_read = vid_ram1_addr_hi & {16{reg_rd[VID_RAM1_ADDR_HI ]}};
`endif
wire [15:0] vid_ram1_data_read = vid_ram1_data & {16{reg_rd[VID_RAM1_DATA ]}};
wire [15:0] gpu_cmd_lo_read = 16'h0000 & {16{reg_rd[GPU_CMD_LO ]}};
wire [15:0] gpu_cmd_hi_read = 16'h0000 & {16{reg_rd[GPU_CMD_HI ]}};
wire [15:0] gpu_stat_read = gpu_stat & {16{reg_rd[GPU_STAT ]}};
wire [15:0] per_dout_o = gfx_ctrl_read |
gfx_status_read |
gfx_irq_read |
display_width_read |
display_height_read |
display_size_lo_read |
`ifdef WITH_DISPLAY_SIZE_HI
display_size_hi_read |
`endif
display_cfg_read |
display_refr_cnt_read |
lt24_cfg_read |
lt24_refresh_read |
lt24_refresh_sync_read |
lt24_cmd_read |
lt24_cmd_param_read |
lt24_cmd_dfill_read |
lt24_status_read |
lut_cfg_read |
lut_ram_addr_read |
lut_ram_data_read |
frame_select_read |
frame0_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame0_ptr_hi_read |
`endif
`ifdef WITH_FRAME1_POINTER
frame1_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame1_ptr_hi_read |
`endif
`endif
`ifdef WITH_FRAME2_POINTER
frame2_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame2_ptr_hi_read |
`endif
`endif
`ifdef WITH_FRAME3_POINTER
frame3_ptr_lo_read |
`ifdef VRAM_BIGGER_4_KW
frame3_ptr_hi_read |
`endif
`endif
vid_ram0_cfg_read |
vid_ram0_width_read |
vid_ram0_addr_lo_read |
`ifdef VRAM_BIGGER_4_KW
vid_ram0_addr_hi_read |
`endif
vid_ram0_data_read |
vid_ram1_cfg_read |
vid_ram1_width_read |
vid_ram1_addr_lo_read |
`ifdef VRAM_BIGGER_4_KW
vid_ram1_addr_hi_read |
`endif
vid_ram1_data_read |
gpu_cmd_lo_read |
gpu_cmd_hi_read |
gpu_stat_read;
//============================================================================
// 5) VIDEO MEMORY INTERFACE
//============================================================================
// Write access strobe
assign vid_ram_wen_o = ~(vid_ram0_we | vid_ram1_we );
// Chip enable.
assign vid_ram_cen_o = ~(vid_ram0_ce | vid_ram1_ce );
// Data to be written
assign vid_ram_din_o = (vid_ram0_din | vid_ram1_din );
// Detect memory accesses for ADDR update
wire vid_ram_access = (vid_ram0_access | vid_ram1_access );
// Next Address
wire [`APIX_MSB:0] vid_ram_addr_nxt = (vid_ram0_addr_nxt | vid_ram1_addr_nxt);
// Align according to graphic mode
wire [`VRAM_MSB:0] vid_ram_addr_align = ({`VRAM_AWIDTH{gfx_mode_1_bpp }} & vid_ram_addr_nxt[`APIX_MSB-0:4]) |
({`VRAM_AWIDTH{gfx_mode_2_bpp }} & vid_ram_addr_nxt[`APIX_MSB-1:3]) |
({`VRAM_AWIDTH{gfx_mode_4_bpp }} & vid_ram_addr_nxt[`APIX_MSB-2:2]) |
({`VRAM_AWIDTH{gfx_mode_8_bpp }} & vid_ram_addr_nxt[`APIX_MSB-3:1]) |
({`VRAM_AWIDTH{gfx_mode_16_bpp}} & vid_ram_addr_nxt[`APIX_MSB-4:0]) ;
// Generate Video RAM address
reg [`VRAM_MSB:0] vid_ram_addr_o;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) vid_ram_addr_o <= {`VRAM_AWIDTH{1'b0}};
else if (vid_ram_access) vid_ram_addr_o <= vid_ram_addr_align;
endmodule // ogfx_reg
`ifdef OGFX_NO_INCLUDE
`else
`include "openGFX430_undefines.v"
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__A22OI_PP_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a22oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_PP_SYMBOL_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1422916944 : 0;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module performs colour space conversion from YCrCb to RGB. *
* *
******************************************************************************/
module altera_up_YCrCb_to_RGB_converter (
// Inputs
clk,
clk_en,
reset,
Y,
Cr,
Cb,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
// Bidirectionals
// Outputs
R,
G,
B,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input clk_en;
input reset;
input [ 7: 0] Y;
input [ 7: 0] Cr;
input [ 7: 0] Cb;
input stream_in_startofpacket;
input stream_in_endofpacket;
input stream_in_empty;
input stream_in_valid;
// Bidirectionals
// Outputs
output reg [ 7: 0] R;
output reg [ 7: 0] G;
output reg [ 7: 0] B;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [35: 0] product_0;
wire [35: 0] product_1;
wire [35: 0] product_2;
wire [35: 0] product_3;
wire [35: 0] product_4;
wire [10: 0] R_sum;
wire [10: 0] G_sum;
wire [10: 0] B_sum;
// Internal Registers
reg [10: 0] Y_sub;
reg [10: 0] Cr_sub;
reg [10: 0] Cb_sub;
reg [10: 0] Y_1d1640;
reg [10: 0] Cr_0d813;
reg [10: 0] Cr_1d596;
reg [10: 0] Cb_2d017;
reg [10: 0] Cb_0d392;
reg [ 1: 0] startofpacket_shift_reg;
reg [ 1: 0] endofpacket_shift_reg;
reg [ 1: 0] empty_shift_reg;
reg [ 1: 0] valid_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @ (posedge clk)
begin
if (reset)
begin
R <= 8'h00;
G <= 8'h00;
B <= 8'h00;
end
else if (clk_en)
begin
if (R_sum[10] == 1'b1) // Negative number
R <= 8'h00;
else if ((R_sum[9] | R_sum[8]) == 1'b1) // Number greater than 255
R <= 8'hFF;
else
R <= R_sum[7:0];
if (G_sum[10] == 1'b1) // Negative number
G <= 8'h00;
else if ((G_sum[9] | G_sum[8]) == 1'b1) // Number greater than 255
G <= 8'hFF;
else
G <= G_sum[7:0];
if (B_sum[10] == 1'b1) // Negative number
B <= 8'h00;
else if ((B_sum[9] | B_sum[8]) == 1'b1) // Number greater than 255
B <= 8'hFF;
else
B <= B_sum[7:0];
end
end
always @ (posedge clk)
begin
if (clk_en)
begin
stream_out_startofpacket <= startofpacket_shift_reg[1];
stream_out_endofpacket <= endofpacket_shift_reg[1];
stream_out_empty <= empty_shift_reg[1];
stream_out_valid <= valid_shift_reg[1];
end
end
// Internal Registers
// ---------------------------------------------------------------------------
//
// Offset Y, Cr, and Cb.
// Note: Internal wires are all 11 bits from here out, to allow for
// increasing bit extent due to additions, subtractions, and multiplies
// Note: Signs are not extended when appropriate.
always @ (posedge clk)
begin
if (reset)
begin
Y_sub <= 11'h000;
Cr_sub <= 11'h000;
Cb_sub <= 11'h000;
end
else if (clk_en)
begin
// Y_sub <= ({{3{Y[7]}}, Y} - 'd16); // result always positive
// Cr_sub <= ({{3{Cr[7]}}, Cr} - 'd128); // result is positive or negative
// Cb_sub <= ({{3{Cb[7]}}, Cb} - 'd128); // result is positive or negative
Y_sub <= ({3'b000, Y} - 11'd16); // result always positive
Cr_sub <= ({3'b000, Cr} - 11'd128); // result is positive or negative
Cb_sub <= ({3'b000, Cb} - 11'd128); // result is positive or negative
end
end
always @ (posedge clk)
begin
if (reset)
begin
Y_1d1640 <= 11'h000;
Cr_0d813 <= 11'h000;
Cr_1d596 <= 11'h000;
Cb_2d017 <= 11'h000;
Cb_0d392 <= 11'h000;
end
else if (clk_en)
begin
Y_1d1640 <= product_0[25:15];
Cr_0d813 <= product_1[25:15];
Cr_1d596 <= product_2[25:15];
Cb_2d017 <= product_3[25:15];
Cb_0d392 <= product_4[25:15];
end
end
always @(posedge clk)
begin
if (reset)
begin
startofpacket_shift_reg <= 2'h0;
endofpacket_shift_reg <= 2'h0;
empty_shift_reg <= 2'h0;
valid_shift_reg <= 2'h0;
end
else if (clk_en)
begin
startofpacket_shift_reg[1] <= startofpacket_shift_reg[0];
endofpacket_shift_reg[1] <= endofpacket_shift_reg[0];
empty_shift_reg[1] <= empty_shift_reg[0];
valid_shift_reg[1] <= valid_shift_reg[0];
startofpacket_shift_reg[0] <= stream_in_startofpacket;
endofpacket_shift_reg[0] <= stream_in_endofpacket;
empty_shift_reg[0] <= stream_in_empty;
valid_shift_reg[0] <= stream_in_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
// Internal Assignments
// ---------------------------------------------------------------------------
//
// Sum the proper outputs from the multiply to form R'G'B'
//
assign R_sum = Y_1d1640 + Cr_1d596;
assign G_sum = Y_1d1640 - Cr_0d813 - Cb_0d392;
assign B_sum = Y_1d1640 + Cb_2d017;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
// Formula Set #1
// ---------------------------------------------------------------------------
// R' = 1.164(Y-16) + 1.596(Cr-128)
// G' = 1.164(Y-16) - .813(Cr-128) - .392(Cb-128)
// B' = 1.164(Y-16) + 2.017(Cb-128)
//
// use full precision of multiply to experiment with coefficients
// 1.164 -> I[1:0].F[14:0] .164 X 2^15 = 094FD or 00 1.001 0100 1111 1101
// 0.813 -> I[1:0].F[14:0] .813 X 2^15 = 06810 or 00 0.110 1000 0001 0000
// 1.596 -> I[1:0].F[14:0] .596 X 2^15 = 0CC49 or 00 1.100 1100 0100 1001
// 2.017 -> I[1:0].F[14:0] .017 X 2^15 = 1022D or 01 0.000 0010 0010 1101
// 0.392 -> I[1:0].F[14:0] .392 X 2^15 = 0322D or 00 0.011 0010 0010 1101
lpm_mult lpm_mult_component_0 (
// Inputs
.dataa ({{7{Y_sub[10]}}, Y_sub}),
.datab (18'h094FD),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_0),
.sum (1'b0)
);
defparam
lpm_mult_component_0.lpm_widtha = 18,
lpm_mult_component_0.lpm_widthb = 18,
lpm_mult_component_0.lpm_widthp = 36,
lpm_mult_component_0.lpm_widths = 1,
lpm_mult_component_0.lpm_type = "LPM_MULT",
lpm_mult_component_0.lpm_representation = "SIGNED",
lpm_mult_component_0.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_1 (
// Inputs
.dataa ({{7{Cr_sub[10]}}, Cr_sub}),
.datab (18'h06810),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_1),
.sum (1'b0)
);
defparam
lpm_mult_component_1.lpm_widtha = 18,
lpm_mult_component_1.lpm_widthb = 18,
lpm_mult_component_1.lpm_widthp = 36,
lpm_mult_component_1.lpm_widths = 1,
lpm_mult_component_1.lpm_type = "LPM_MULT",
lpm_mult_component_1.lpm_representation = "SIGNED",
lpm_mult_component_1.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_2 (
// Inputs
.dataa ({{7{Cr_sub[10]}}, Cr_sub}),
.datab (18'h0CC49),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_2),
.sum (1'b0)
);
defparam
lpm_mult_component_2.lpm_widtha = 18,
lpm_mult_component_2.lpm_widthb = 18,
lpm_mult_component_2.lpm_widthp = 36,
lpm_mult_component_2.lpm_widths = 1,
lpm_mult_component_2.lpm_type = "LPM_MULT",
lpm_mult_component_2.lpm_representation = "SIGNED",
lpm_mult_component_2.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_3 (
// Inputs
.dataa ({{7{Cb_sub[10]}}, Cb_sub}),
.datab (18'h1022D),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_3),
.sum (1'b0)
);
defparam
lpm_mult_component_3.lpm_widtha = 18,
lpm_mult_component_3.lpm_widthb = 18,
lpm_mult_component_3.lpm_widthp = 36,
lpm_mult_component_3.lpm_widths = 1,
lpm_mult_component_3.lpm_type = "LPM_MULT",
lpm_mult_component_3.lpm_representation = "SIGNED",
lpm_mult_component_3.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
lpm_mult lpm_mult_component_4 (
// Inputs
.dataa ({{7{Cb_sub[10]}}, Cb_sub}),
.datab (18'h0322D),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
// Bidirectionals
// Outputs
.result (product_4),
.sum (1'b0)
);
defparam
lpm_mult_component_4.lpm_widtha = 18,
lpm_mult_component_4.lpm_widthb = 18,
lpm_mult_component_4.lpm_widthp = 36,
lpm_mult_component_4.lpm_widths = 1,
lpm_mult_component_4.lpm_type = "LPM_MULT",
lpm_mult_component_4.lpm_representation = "SIGNED",
lpm_mult_component_4.lpm_hint = "INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=5";
// Formula Set #2
// ---------------------------------------------------------------------------
// R = Y + 1.402 (Cr-128)
// G = Y - 0.71414 (Cr-128) - 0.34414 (Cb-128)
// B = Y + 1.772 (Cb-128)
//
// use full precision of multiply to experiment with coefficients
// 1.00000 -> I[0].F[16:0] 1.00000 X 2^15 = 08000
// 1.40200 -> I[0].F[16:0] 1.40200 X 2^15 = 0B375
// 0.71414 -> I[0].F[16:0] 0.71414 X 2^15 = 05B69
// 0.34414 -> I[0].F[16:0] 0.34414 X 2^15 = 02C0D
// 1.77200 -> I[0].F[16:0] 1.77200 X 2^15 = 0E2D1
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:12:18 11/19/2016
// Design Name:
// Module Name: bmod
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bmod(
input [2:0] in_row,
output reg [4:0] out_code
);
parameter [4:0] d_0 = 5'b10011; // X XX
parameter [4:0] d_1 = 5'b01011; // X XX
parameter [4:0] d_2 = 5'b00100; // X
parameter [4:0] d_3 = 5'b11010; // XX X
parameter [4:0] d_4 = 5'b11001; // XX X
always @ *
begin
case (in_row)
3'b000:
out_code = d_0;
3'b001:
out_code = d_1;
3'b010:
out_code = d_2;
3'b011:
out_code = d_3;
3'b100:
out_code = d_4;
default:
out_code = 5'b0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_BLACKBOX_V
`define SKY130_FD_SC_HS__A311OI_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_BLACKBOX_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: mux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple multiplexer
// Author: Dustin Richmond (@darichmond)
// TODO: Remove C_CLOG_NUM_INPUTS
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module mux
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32,
parameter C_MUX_TYPE = "SELECT"
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
generate
if(C_MUX_TYPE == "SELECT") begin
mux_select
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_select_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end else if (C_MUX_TYPE == "SHIFT") begin
mux_shift
#(/*AUTOINSTPARAM*/
// Parameters
.C_NUM_INPUTS (C_NUM_INPUTS),
.C_CLOG_NUM_INPUTS (C_CLOG_NUM_INPUTS),
.C_WIDTH (C_WIDTH))
mux_shift_inst
(/*AUTOINST*/
// Outputs
.MUX_OUTPUT (MUX_OUTPUT[C_WIDTH-1:0]),
// Inputs
.MUX_INPUTS (MUX_INPUTS[(C_NUM_INPUTS)*C_WIDTH-1:0]),
.MUX_SELECT (MUX_SELECT[C_CLOG_NUM_INPUTS-1:0]));
end
endgenerate
endmodule
module mux_select
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH-1:0] wMuxInputs[C_NUM_INPUTS-1:0];
assign MUX_OUTPUT = wMuxInputs[MUX_SELECT];
generate
for (i = 0; i < C_NUM_INPUTS ; i = i + 1) begin : gen_muxInputs_array
assign wMuxInputs[i] = MUX_INPUTS[i*C_WIDTH +: C_WIDTH];
end
endgenerate
endmodule
module mux_shift
#(
parameter C_NUM_INPUTS = 4,
parameter C_CLOG_NUM_INPUTS = 2,
parameter C_WIDTH = 32
)
(
input [(C_NUM_INPUTS)*C_WIDTH-1:0] MUX_INPUTS,
input [C_CLOG_NUM_INPUTS-1:0] MUX_SELECT,
output [C_WIDTH-1:0] MUX_OUTPUT
);
genvar i;
wire [C_WIDTH*C_NUM_INPUTS-1:0] wMuxInputs;
assign wMuxInputs = MUX_INPUTS >> MUX_SELECT;
assign MUX_OUTPUT = wMuxInputs[C_WIDTH-1:0];
endmodule
|
`include "registroDesplazable.v"
`include "startStop.v"
`include "i2cSlave.v"
`include "tcpci_cmos_synth.v"
`include "cmos_cells.v"
`include "clock.v"
module test_registros;
wire Start_tHardResetComplete_timer;
wire Request_PHY_to_Send_Hard_Reset;
wire Request_PHY_to_Send_Cable_Reset;
wire Stop_PHY_attempting_to_send_Hard_Reset;
wire Stop_PHY_attempting_to_send_Cable_Reset;
wire Stop_tHardResetComplete_timer;
wire Start_CRCReceiveTimer;
wire Stop_CRCReceiverTimer;
wire MessageIDCounter;
wire MessageID;
wire MessageID_mismatch;
wire SOP_mismatch;
wire MessageID_SOP_match;
wire [7:0] TRANSMIT_BYTE_COUNT;
wire [7:0] TRANSMIT_HEADER_LOW;
wire [7:0] TRANSMIT_HEADER_HIGH;
wire [7:0] TRANSMIT_DATA_OBJECTS;
wire [7:0] I2C_slave_reg_out;
wire [7:0] ALERT_LOW;
reg tHard_Reset_Complete_expires;
reg Hard_Reset_sent;
reg Cable_Reset_sent;
reg tHardResetComplete_expires;
reg PRL_Rx_Message_Discard;
reg Hard_Reset_received;
reg Cable_Reset_received;
reg RetryCounter;
reg CRCReceiveTimer_Timeout;
reg GoodCRC_Response_from_PHY;
reg Message_discarded_bus_Idle;
reg [7:0] I2C_slave_reg_in;
reg [7:0] I2C_slave_reg_addr;
reg I2C_slave_reg_in_enb;
reg reset;
wire clk;
///I2C
/// creacion del i2c, concetar lo que es requerido
wire pull_Down;
wire [2:0] cuenta;
wire [8:0] estado;
wire read_write;
reg ir_ri0_enb, ir_ri1_enb, ir_ri2_enb;
wire [7:0] ow_ri0_out_data, ow_ri1_out_data, ow_ri2_out_data;
reg [7:0] ir_ri0_in_data, ir_ri0_address, ir_ri1_in_data, ir_ri1_address, ir_ri2_in_data, ir_ri2_address;
reg SCL,SDA;
clock c(clk);
tcpci TCPCI(Start_tHardResetComplete_timer, Request_PHY_to_Send_Hard_Reset, Request_PHY_to_Send_Cable_Reset, Stop_PHY_attempting_to_send_Hard_Reset, Stop_PHY_attempting_to_send_Cable_Reset, Stop_tHardResetComplete_timer, Start_CRCReceiveTimer, Stop_CRCReceiverTimer, MessageIDCounter, MessageID, MessageID_mismatch, SOP_mismatch, MessageID_SOP_match, TRANSMIT_BYTE_COUNT, TRANSMIT_HEADER_LOW, TRANSMIT_HEADER_HIGH, TRANSMIT_DATA_OBJECTS, I2C_slave_reg_out, ALERT_LOW, tHard_Reset_Complete_expires, Hard_Reset_sent, Cable_Reset_sent, tHardResetComplete_expires, PRL_Rx_Message_Discard, Hard_Reset_received, Cable_Reset_received, RetryCounter, CRCReceiveTimer_Timeout, GoodCRC_Response_from_PHY, Message_discarded_bus_Idle, I2C_slave_reg_in, I2C_slave_reg_addr, I2C_slave_reg_in_enb, reset, clk);
i2cSlave i2c_Slave(reset,SCL,SDA,pull_Down,ir_ri2_address,ir_ri2_enb,read_write,ow_ri2_out_data,ir_ri2_in_data,estado,cuenta);
initial
begin
$dumpfile("test_registros.vcd");
$dumpvars;
tHard_Reset_Complete_expires=0;
Hard_Reset_sent=0;
Cable_Reset_sent=0;
tHardResetComplete_expires=0;
PRL_Rx_Message_Discard=0;
Hard_Reset_received=0;
Cable_Reset_received=0;
RetryCounter=0;
CRCReceiveTimer_Timeout=0;
GoodCRC_Response_from_PHY=0;
Message_discarded_bus_Idle=0;
I2C_slave_reg_in=0;
I2C_slave_reg_addr=0;
I2C_slave_reg_in_enb=0;
reset=1;
#`PERIODO reset=0;
ir_ri0_enb=1;
ir_ri1_enb=1;
ir_ri0_address=8'h10; //direccion de alert parte alta y baja
ir_ri1_address=8'h11; //
ir_ri0_in_data=8'h00;
ir_ri1_in_data=8'h04; //escribimos la alerta de mensaje recibido
SCL=0; SDA=1;
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
// Poner las transiciones requeridas para la lectura del alert
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
#(3*`PERIODO/4)
SDA=0;#(`PERIODO/2) //Start
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO//dir slave
SDA=0;#`PERIODO//Reg/write
SDA=1;#`PERIODO//ACK
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO //50 la dir de registro
SDA=1;#`PERIODO//ACK
///
SDA=1;#`PERIODO
SDA=0;#`PERIODO//repeated start
///
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //dir slave
SDA=1;#`PERIODO //ACK tercero
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //liberar linea para recibir byte
SDA=0;#`PERIODO //Master hace ACK de recibido de primer byte
SDA=1;#`PERIODO //liberado de linea para recibir segundo byte
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //fin de recepcion de segundo byte
SDA=1;#`PERIODO //NACK
SDA=0;#(`PERIODO/2)
SDA=1;#`PERIODO //y hacer stop
///////////////////////////////////////////////////////////////
////// Lectura de RECEIVE_BYTE_COUNT y RX_BUF_FRAME_TYPE /////
///////////////////////////////////////////////////////////////
SDA=0;#(`PERIODO/2) //hacer start para leer RECEIVE_BYTE_COUNT y RX_BUF_FRAME_TYPE
////Segunda lectura
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO//dir slave
SDA=0;#`PERIODO//Reg/write
SDA=1;#`PERIODO//ACK
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO //50 la dir de registro
SDA=1;#`PERIODO//ACK
///
SDA=1;#`PERIODO
SDA=0;#`PERIODO//repeated start
///
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //dir slave
SDA=1;#`PERIODO //ACK tercero
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //liberar linea para recibir byte
SDA=0;#`PERIODO //Master hace ACK de recibido de primer byte
SDA=1;#`PERIODO //liberado de linea para recibir segundo byte
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //fin de recepcion de segundo byte
SDA=1;#`PERIODO //NACK
SDA=0;#(`PERIODO/2)
SDA=1;#`PERIODO //y hacer stop
///////////////////////////////
////// Lectura de Rxbuff /////
///////////////////////////////
SDA=0;#(`PERIODO/2) //hacer start para leer RX_BUF
////Tercera lectura
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO//dir slave
SDA=0;#`PERIODO//Reg/write
SDA=1;#`PERIODO//ACK
SDA=0;#`PERIODO //inicio dir
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO //fin dir de registro
SDA=1;#`PERIODO //ACK
///
SDA=1;#`PERIODO
SDA=0;#`PERIODO//repeated start
///
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=0;#`PERIODO
SDA=0;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //dir slave
SDA=1;#`PERIODO //ACK tercero
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //liberar linea para recibir byte
SDA=0;#`PERIODO //Master hace ACK de recibido de primer byte
SDA=1;#`PERIODO //liberado de linea para recibir segundo byte
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //fin de recepcion de segundo byte
SDA=0;#`PERIODO //Master hace ACK de recibido de primer byte
SDA=1;#`PERIODO //liberado de linea para recibir segundo byte
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO
SDA=1;#`PERIODO //fin de recepcion de tercer byte
SDA=1;#`PERIODO //NACK
SDA=0;#(`PERIODO/2)
SDA=1;#`PERIODO //y hacer stop
#`PERIODO $finish;
end
always begin #(`PERIODO/2) SCL=!SCL; end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
///////////////////////////////////////////////////////////////////////////////
// Title : Asynchronous FIFO model
// File : async_fifo.v
// Author : Frank Bruno
// Created : 14-May-2009
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module infers an asynchronous FIFO. 1R/1W
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// The file below this point is mdifiable by the licensee:
`timescale 1ns / 10ps
module async_fifo
#
(
parameter WIDTH = 8,
parameter DEPTH = 8,
parameter DLOG2 = 3
)
(
input [WIDTH-1:0] data,
input rdclk,
input rdreq,
input wrclk,
input wrreq,
input aclr,
output reg [WIDTH-1:0] q,
output rd_empty,
output rd_full,
output wr_empty,
output wr_full,
output reg [DLOG2-1:0] wrusedw,
output reg [DLOG2-1:0] rdusedw
);
reg [WIDTH-1:0] mem[DEPTH-1:0];
reg [DLOG2-1:0] wraddr, rdaddr;
reg [DLOG2-1:0] g_wraddr, g_rdaddr;
reg [DLOG2-1:0] sync_g_wraddr, sync_g_rdaddr;
reg [DLOG2-1:0] wraddr_bin, rdaddr_bin;
reg [DLOG2-1:0] wr_diff, rd_diff;
wire [DLOG2-1:0] wraddr_next, rdaddr_next;
integer i, j, k, l;
always @(posedge wrclk, negedge aclr)
if (!aclr) begin
g_wraddr <= 'b0;
sync_g_rdaddr <= 'b0;
wraddr <= 'b0;
wrusedw <= 'b0;
end else begin
sync_g_rdaddr <= g_rdaddr;
wrusedw <= wr_diff;
if (wrreq) begin
mem[wraddr] <= data;
wraddr <= wraddr_next;
g_wraddr[DLOG2-1] <= wraddr_next[DLOG2-1];
for (i = 0; i < DLOG2-1; i = i + 1)
g_wraddr[i] <= wraddr_next[i+1] ^ wraddr_next[i];
end
end
always @* begin
rdaddr_bin[DLOG2-1] = sync_g_rdaddr[DLOG2-1];
for (l = DLOG2-2; l >=0; l = l - 1) begin
rdaddr_bin[l] = rdaddr_bin[l+1] ^ sync_g_rdaddr[l];
end
end
//assign wr_empty = (wrusedw == 0);
//assign wr_full = (wrusedw == DEPTH - 1);
assign wr_empty = (wr_diff == 0);
assign wr_full = (wr_diff == DEPTH - 1);
always @(posedge rdclk, negedge aclr)
if (!aclr) begin
g_rdaddr <= 'b0;
sync_g_wraddr <= 'b0;
rdaddr <= 'b0;
q <= 'b0;
rdusedw <= 'b0;
end else begin
sync_g_wraddr <= g_wraddr;
rdusedw <= rd_diff;
q <= mem[rdaddr];
if (rdreq) begin
rdaddr <= rdaddr_next;
g_rdaddr[DLOG2-1] <= rdaddr_next[DLOG2-1];
for (j = 0; j < DLOG2-1; j = j + 1)
g_rdaddr[j] <= rdaddr_next[j+1] ^ rdaddr_next[j];
end
end
always @* begin
wraddr_bin[DLOG2-1] = sync_g_wraddr[DLOG2-1];
for (k = DLOG2-2; k >=0; k = k - 1) begin
wraddr_bin[k] = wraddr_bin[k+1] ^ sync_g_wraddr[k];
end
end
//assign rd_empty = (rdusedw == 0);
//assign rd_full = (rdusedw == DEPTH - 1);
assign rd_empty = (rd_diff == 0);
assign rd_full = (rd_diff == DEPTH - 1);
assign wraddr_next = wraddr + 1;
assign rdaddr_next = rdaddr + 1;
always @* begin
if (wraddr >= rdaddr_bin)
wr_diff = wraddr - rdaddr_bin;
else
wr_diff = ~(rdaddr_bin - wraddr) + 1;
if (wraddr_bin >= rdaddr)
rd_diff = wraddr_bin - rdaddr;
else
rd_diff = ~(rdaddr - wraddr_bin) + 1;
end
//assign wr_diff = wraddr - rdaddr_bin;
//assign rd_diff = rdaddr - wraddr_bin;
endmodule // async_fifo
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
//parameter csr_addr = 4'h0,
parameter clk_freq = 100000000,
parameter baud = 115200
) (
//cpu_read_write
//wb_input
input [31:0] dat_i,
input [31:0] adr_i,
input we_i,
input stb_i,
//wb_output
output reg [31:0] dat_o,
output ack_o,
input sys_clk,
input sys_rst,
output rx_irq,
output tx_irq,
input uart_rx,
output uart_tx,
input rx_iack
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
wire rx_done, tx_done;
wire tx_busy;
wire full_rx, full_tx, empty_rx, empty_tx;
reg thru = 0;
wire uart_tx_transceiver;
wire [7:0] rx_data_out;
reg fifo_rx_wr = 0;
reg tmpflag = 0;
wire fifo_rx_rd;
reg fifo_rd_once = 0;
wire [7:0] tx_data_out;
wire fifo_tx_rd;
reg tran_tx_wr = 0;
reg fifo_tx_rd_once = 0;
reg fifo_busy;
wire uart_wr;
uart_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.uart_rx(uart_rx),
.uart_tx(uart_tx_transceiver),
.divisor(divisor),
.rx_data(rx_data),
.rx_done(rx_done),
.tx_data(tx_data_out),
.tx_wr(tran_tx_wr & fifo_tx_rd_once),
.tx_done(tx_done),
.tx_busy(tx_busy),
.rx_busy(rx_busy)
);
// always @(posedge sys_clk) begin
// if(rx_done & ~fifo_rx_wr) fifo_rx_wr = 1;
// else if(~rx_done & fifo_rx_wr & ~tmpflag) begin
// fifo_rx_wr = 1;
// tmpflag = 1;
// end
// else if(tmpflag) begin
// fifo_rx_wr = 0;
// tmpflag = 0;
// end
// end
always @(posedge sys_clk) begin
if(rx_done) fifo_rx_wr = 1;
else fifo_rx_wr = 0;
end
assign fifo_rx_rd = rx_wr & ~fifo_rd_once;
always @(posedge sys_clk) begin
if(rx_wr) fifo_rd_once = 1;
else fifo_rd_once = 0;
end
assign rx_irq = full_rx & ~rx_iack;
uart_fifo fifo_rx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(rx_data), // input [7 : 0] din
.wr_en(fifo_rx_wr), // input wr_en
.rd_en(fifo_rx_rd), // input rd_en
.dout(rx_data_out), // output [7 : 0] dout
.full(full_rx), // output full
.empty(empty_rx), // output empty
.data_count() // output [7 : 0] data_count
);
always @(posedge sys_clk) begin
if(tran_tx_wr) fifo_tx_rd_once = 1;
else fifo_tx_rd_once = 0;
end
assign fifo_tx_rd = ~tx_busy & ~empty_tx;
always @(posedge sys_clk) begin
tran_tx_wr = fifo_tx_rd;
end
always @(posedge sys_clk) begin
if(tx_wr) fifo_busy = 1;
else fifo_busy = 0;
end
//assign tx_irq = full_tx;
uart_fifo fifo_tx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(tx_data), // input [7 : 0] din
.wr_en(tx_wr & ~fifo_busy), // input wr_en
.rd_en(tran_tx_wr & fifo_tx_rd_once/*fifo_tx_rd*/), // input rd_en
.dout(tx_data_out), // output [7 : 0] dout
.full(full_tx), // output full
.empty(empty_tx), // output empty
.data_count() // output [7 : 0] data_count
);
assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
/* CSR interface */
//wire csr_selected = csr_a[13:10] == csr_addr;
assign tx_data = dat_i[7:0];
//assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
assign tx_wr = stb_i & ack_o & we_i & (adr_i[1:0] == 2'b00);
assign rx_wr = stb_i & ack_o & ~we_i & (adr_i[1:0] == 2'b00) & ~empty_rx;
parameter default_divisor = clk_freq/baud/16;
assign ack_o = stb_i & (we_i?~full_tx:1) ;//& ((we_i&~full_tx) | (~we_i&~empty_rx));
assign uart_wr = stb_i && ack_o;
always @(posedge sys_clk or posedge sys_rst) begin
if(sys_rst) begin
divisor <= default_divisor;
dat_o <= 32'd0;
end else if(uart_wr) begin
dat_o <= 32'd0;
case(adr_i[1:0])
2'b00: if(rx_wr) begin dat_o <= {23'h0, 1'b1, rx_data_out}; end
2'b01: dat_o <= divisor;
2'b10: dat_o <= thru;
endcase
if(we_i/*csr_we*/) begin
case(adr_i[1:0])
2'b00:; /* handled by transceiver */
2'b01: divisor <= dat_i[15:0];
2'b10: thru <= dat_i[0];
endcase
end
end
end
//always @(posedge sys_clk) begin
// if(sys_rst) begin
// divisor <= default_divisor;
// dat_o <= 32'd0;
// end else begin
// dat_o <= 32'd0;
// if(stb_i && ack_o/*csr_selected*/) begin
// case(adr_i[1:0])
// 2'b00: dat_o <= rx_data;
// 2'b01: dat_o <= divisor;
// 2'b10: dat_o <= thru;
// endcase
// if(we_i/*csr_we*/) begin
// case(adr_i[1:0])
// 2'b00:; /* handled by transceiver */
// 2'b01: divisor <= dat_i[15:0];
// 2'b10: thru <= dat_i[0];
// endcase
// end
// end
// end
//end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// all inputs are 2's complement
`timescale 1ps/1ps
module ad_mac_1 (
// Q0 = S2;
// Q1 = S0*C0 + S1*C1 + S2*C2 + S3*C3 + S4*C4 + S5*C5;
clk,
data_s0,
data_s1,
data_s2,
data_s3,
data_s4,
data_s5,
// outputs
mac_data_0,
mac_data_1);
// parameters
localparam MAC_C0 = 16'h024d; // 0.0180
localparam MAC_C1 = 16'hf155; // -0.1146
localparam MAC_C2 = 16'h4c77; // 0.5974
localparam MAC_C3 = 16'h4c77; // 0.5974
localparam MAC_C4 = 16'hf155; // -0.1146
localparam MAC_C5 = 16'h024d; // 0.0180
// Q0 = S2;
// Q1 = S0*C0 + S1*C1 + S2*C2 + S3*C3 + S4*C4 + S5*C5;
input clk;
input [15:0] data_s0;
input [15:0] data_s1;
input [15:0] data_s2;
input [15:0] data_s3;
input [15:0] data_s4;
input [15:0] data_s5;
// outputs
output [15:0] mac_data_0;
output [15:0] mac_data_1;
// internal registers
reg [15:0] mac_data_0 = 'd0;
reg [15:0] mac_data_1 = 'd0;
reg [15:0] p3_data_0_0 = 'd0;
reg [34:0] p3_data_1_0 = 'd0;
reg [15:0] p2_data_0_0 = 'd0;
reg [33:0] p2_data_1_0 = 'd0;
reg [33:0] p2_data_1_1 = 'd0;
reg [15:0] p1_data_0_0 = 'd0;
reg [32:0] p1_data_1_0 = 'd0;
reg [32:0] p1_data_1_1 = 'd0;
reg [32:0] p1_data_1_2 = 'd0;
// internal signals
wire p3_ovf_s;
wire [31:0] p1_data_0_0_s;
wire [31:0] p1_data_1_0_s;
wire [31:0] p1_data_1_1_s;
wire [31:0] p1_data_1_2_s;
wire [31:0] p1_data_1_3_s;
wire [31:0] p1_data_1_4_s;
wire [31:0] p1_data_1_5_s;
// output registers
assign p3_ovf_s = ((p3_data_1_0[34:30] == 5'h00) || (p3_data_1_0[34:30] == 5'h1f)) ? 1'b0 : 1'b1;
always @(posedge clk) begin
mac_data_0 <= p3_data_0_0;
if (p3_ovf_s == 0) begin
mac_data_1 <= p3_data_1_0[30:15];
end else if (p3_data_1_0[34] == 1'b1) begin
mac_data_1 <= 16'h8001;
end else begin
mac_data_1 <= 16'h7fff;
end
end
// sum of products (stage-3)
always @(posedge clk) begin
p3_data_0_0 <= p2_data_0_0;
p3_data_1_0 <= {p2_data_1_0[33], p2_data_1_0} + {p2_data_1_1[33], p2_data_1_1};
end
// sum of products (stage-2)
always @(posedge clk) begin
p2_data_0_0 <= p1_data_0_0;
p2_data_1_0 <= {p1_data_1_0[32], p1_data_1_0} + {p1_data_1_1[32], p1_data_1_1};
p2_data_1_1 <= {p1_data_1_2[32], p1_data_1_2};
end
// sum of products (stage-1)
always @(posedge clk) begin
p1_data_0_0 <= p1_data_0_0_s[15:0];
p1_data_1_0 <= {p1_data_1_0_s[31], p1_data_1_0_s} + {p1_data_1_1_s[31], p1_data_1_1_s};
p1_data_1_1 <= {p1_data_1_2_s[31], p1_data_1_2_s} + {p1_data_1_3_s[31], p1_data_1_3_s};
p1_data_1_2 <= {p1_data_1_4_s[31], p1_data_1_4_s} + {p1_data_1_5_s[31], p1_data_1_5_s};
end
// sample -0
ad_mul_dsp48_1 i_mul_dsp48_1_0_0 (
.clk (clk),
.a (data_s2),
.b (16'h1),
.p (p1_data_0_0_s));
// sample -1
ad_mul_dsp48_1 i_mul_dsp48_1_1_0 (
.clk (clk),
.a (data_s0),
.b (MAC_C0),
.p (p1_data_1_0_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_1 (
.clk (clk),
.a (data_s1),
.b (MAC_C1),
.p (p1_data_1_1_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_2 (
.clk (clk),
.a (data_s2),
.b (MAC_C2),
.p (p1_data_1_2_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_3 (
.clk (clk),
.a (data_s3),
.b (MAC_C3),
.p (p1_data_1_3_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_4 (
.clk (clk),
.a (data_s4),
.b (MAC_C4),
.p (p1_data_1_4_s));
ad_mul_dsp48_1 i_mul_dsp48_1_1_5 (
.clk (clk),
.a (data_s5),
.b (MAC_C5),
.p (p1_data_1_5_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* A module for reading the first 64 Kib off of the micro SD card
* using an SPI flash interface and writing it to RAM where it can
* be executed.
*
* For more information, see:
* http://elm-chan.org/docs/mmc/mmc_e.html
* http://elm-chan.org/docs/spi_e.html
* http://elm-chan.org/docs/mmc/gfx1/sdinit.png
* http://www.dejazzer.com/ee379/lecture_notes/lec12_sd_card.pdf
* https://learn.sparkfun.com/tutorials/serial-peripheral-interface-spi
*
* @author Robert Fotino, 2016
*/
`include "definitions.vh"
module sdcard_reader
(
input clk,
input calib_done,
input disabled,
input [7:0] program_index,
output reg started,
output reg done,
output reg [7:0] progress,
output reg error,
// Signals for communicating with SD card
output reg sdcard_cs,
output reg sdcard_sclk,
output sdcard_mosi,
input sdcard_miso,
// Signals for writing to RAM
output mem_cmd_en,
output [2:0] mem_cmd_instr,
output [5:0] mem_cmd_bl,
output [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output mem_wr_en,
output [3:0] mem_wr_mask,
output [31:0] mem_wr_data,
input mem_wr_full,
input mem_wr_empty,
input [6:0] mem_wr_count,
input mem_wr_underrun,
input mem_wr_error
);
// Give outputs their initial values
initial begin
started = 0;
done = 0;
progress = 0;
error = 0;
sdcard_cs = 1;
sdcard_sclk = 1;
end
// Divide the clock that we send to the SD card
reg [8:0] sclk_counter = 0;
reg [8:0] sclk_div = 250; // Default to 400 kHz
reg sclk_reset = 0;
reg sclk_posedge = 0;
reg sclk_negedge = 0;
always @ (posedge clk) begin
sclk_posedge <= 0;
sclk_negedge <= 0;
if (sclk_reset || sclk_div - 1 == sclk_counter) begin
sclk_counter <= 0;
if (sdcard_sclk) begin
sclk_negedge <= 1;
end
sdcard_sclk <= 0;
end else begin
sclk_counter <= sclk_counter + 1;
// At the halfway point, switch the serial clock to 1
if ((sclk_div >> 1) - 1 == sclk_counter) begin
sclk_posedge <= 1;
sdcard_sclk <= 1;
end
end
end
// Count whether 1.5 milliseconds have passed before
// establishing communication with the SD card
localparam POWER_COUNTER_MAX = 150000;
reg power_on_done = 0;
reg [$clog2(POWER_COUNTER_MAX)-1:0] power_on_counter = 0;
always @ (posedge clk) begin
if (power_on_counter == POWER_COUNTER_MAX - 1) begin
power_on_done <= 1;
end else begin
power_on_counter <= power_on_counter + 1;
end
end
// Controls for sending 6-byte SPI commands to SD card
localparam CMD_BITS = 48;
reg spi_cmd_send_reset = 0;
reg spi_cmd_send_en = 0;
reg [5:0] spi_cmd_send_index = 0;
reg [31:0] spi_cmd_send_arg = 0;
reg [6:0] spi_cmd_send_crc = 0;
wire [CMD_BITS-1:0] spi_cmd_send_data = {
2'b01, spi_cmd_send_index,
spi_cmd_send_arg, spi_cmd_send_crc, 1'b1
};
wire spi_cmd_send_done;
spi_sender #(.DATA_BITS(CMD_BITS)) spi_cmd_sender_
(
.clk(clk),
.sclk_posedge(sclk_posedge),
.sclk_negedge(sclk_negedge),
.reset(spi_cmd_send_reset),
.en(spi_cmd_send_en),
.data(spi_cmd_send_data),
.out(sdcard_mosi),
.done(spi_cmd_send_done)
);
// Controls for receiving 8-bit R1 responses from SD card
localparam R1_BITS = 8;
reg spi_r1_recv_reset = 0;
reg spi_r1_recv_en = 0;
wire [R1_BITS-1:0] spi_r1_recv_out;
wire spi_r1_recv_done;
spi_receiver #(.DATA_BITS(R1_BITS)) spi_r1_receiver_
(
.clk(clk),
.sclk_posedge(sclk_posedge),
.sclk_negedge(sclk_negedge),
.reset(spi_r1_recv_reset),
.en(spi_r1_recv_en),
.in(sdcard_miso),
.out(spi_r1_recv_out),
.done(spi_r1_recv_done)
);
// Controls for receiving 40-bit R3/R7 responses from SD card
// (R1 followed by 32 bits of data)
localparam R3_R7_BITS = 40;
reg spi_r3_r7_recv_reset = 0;
reg spi_r3_r7_recv_en = 0;
wire [R3_R7_BITS-1:0] spi_r3_r7_recv_out;
wire spi_r3_r7_recv_done;
spi_receiver #(.DATA_BITS(R3_R7_BITS)) spi_r3_r7_receiver_
(
.clk(clk),
.sclk_posedge(sclk_posedge),
.sclk_negedge(sclk_negedge),
.reset(spi_r3_r7_recv_reset),
.en(spi_r3_r7_recv_en),
.in(sdcard_miso),
.out(spi_r3_r7_recv_out),
.done(spi_r3_r7_recv_done)
);
// Module for receiving data blocks and storing them in RAM
reg [6:0] block_addr = 0;
reg spi_data_read_en = 0;
wire spi_data_read_error;
wire spi_data_read_done;
spi_data_reader spi_data_reader_
(
.clk(clk),
.calib_done(calib_done),
.sclk_posedge(sclk_posedge),
.sclk_negedge(sclk_negedge),
.block_addr(block_addr),
.en(spi_data_read_en),
.in(sdcard_miso),
.error(spi_data_read_error),
.done(spi_data_read_done),
.mem_cmd_en(mem_cmd_en),
.mem_cmd_instr(mem_cmd_instr),
.mem_cmd_bl(mem_cmd_bl),
.mem_cmd_byte_addr(mem_cmd_byte_addr),
.mem_cmd_empty(mem_cmd_empty),
.mem_cmd_full(mem_cmd_full),
.mem_wr_en(mem_wr_en),
.mem_wr_mask(mem_wr_mask),
.mem_wr_data(mem_wr_data),
.mem_wr_full(mem_wr_full),
.mem_wr_empty(mem_wr_empty),
.mem_wr_count(mem_wr_count),
.mem_wr_underrun(mem_wr_underrun),
.mem_wr_error(mem_wr_error)
);
// State machine logic for communicating with the SD card
localparam STATE_POWER_ON = 0;
localparam STATE_DUMMY_CLK = 1;
localparam STATE_0xFF_WAIT = 2;
localparam STATE_R1_SEND = 3;
localparam STATE_R3_R7_SEND = 4;
localparam STATE_CMD0_SEND = 5;
localparam STATE_CMD0_RECV = 6;
localparam STATE_CMD8_SEND = 7;
localparam STATE_CMD8_RECV = 8;
localparam STATE_CMD55_SEND = 9;
localparam STATE_CMD55_RECV = 10;
localparam STATE_ACMD41_SEND = 11;
localparam STATE_ACMD41_RECV = 12;
localparam STATE_CMD58_SEND = 13;
localparam STATE_CMD58_RECV = 14;
localparam STATE_CALIB_WAIT = 15;
localparam STATE_CMD17_SEND = 16;
localparam STATE_CMD17_RECV = 17;
localparam STATE_DATA_RECV = 18;
localparam STATE_DONE = 254;
localparam STATE_ERROR = 255;
reg [7:0] state = STATE_POWER_ON;
reg [7:0] next_state;
reg [7:0] dummy_clk_counter = 0;
reg [7:0] miso_ready_counter = 0;
always @ (posedge clk) begin
sclk_reset <= 0;
spi_cmd_send_en <= 0;
spi_cmd_send_reset <= 0;
spi_r1_recv_en <= 0;
spi_r1_recv_reset <= 0;
spi_r3_r7_recv_en <= 0;
spi_r3_r7_recv_reset <= 0;
spi_data_read_en <= 0;
case (state)
// Wait >= 1 millisecond, then send dummy clock
STATE_POWER_ON: begin
sclk_reset <= 1;
sdcard_cs <= 1;
if (power_on_done) begin
state <= STATE_DUMMY_CLK;
end
end
// Send >= 74 pulses with clock between 100kHz and 400kHz. The card
// is ready to receive a command when it drives the MISO signal high
STATE_DUMMY_CLK: begin
sdcard_cs <= 1;
if (sdcard_miso && sclk_negedge && 74 <= dummy_clk_counter) begin
state <= STATE_CMD0_SEND;
end else if (sclk_posedge) begin
dummy_clk_counter <= dummy_clk_counter + 1;
end
end
// Wait until we have seen 0xFF from the card's MISO
STATE_0xFF_WAIT: begin
if (sclk_posedge) begin
if (sdcard_miso) begin
if (7 == miso_ready_counter) begin
miso_ready_counter <= 0;
state <= next_state;
end else begin
miso_ready_counter <= miso_ready_counter + 1;
end
end else begin
miso_ready_counter <= 0;
end
end
end
// Wait for a command with R1 response to be sent
STATE_R1_SEND: begin
if (spi_cmd_send_done) begin
spi_r1_recv_en <= 1;
state <= next_state;
end
end
// Wait for a command with R3/R7 response to be sent
STATE_R3_R7_SEND: begin
if (spi_cmd_send_done) begin
spi_r3_r7_recv_en <= 1;
state <= next_state;
end
end
// Set up the sender module to send CMD0
STATE_CMD0_SEND: begin
// Change to 10 MHz clock
sclk_div <= 10;
// If CS is low for CMD0 we go into SPI mode
sdcard_cs <= 0;
// Setup command packet
spi_cmd_send_index <= 6'd0;
spi_cmd_send_arg <= 32'h00000000;
spi_cmd_send_crc <= 7'b1001010; // hardcoded CRC for CMD0
// Enable sending of command
spi_cmd_send_en <= 1;
state <= STATE_R1_SEND;
next_state <= STATE_CMD0_RECV;
end
// Wait for response from CMD0, then verify
STATE_CMD0_RECV: begin
if (spi_r1_recv_done && !disabled) begin
started <= 1;
// Check that the response is valid
if (8'b1 == spi_r1_recv_out) begin
state <= STATE_0xFF_WAIT;
next_state <= STATE_CMD8_SEND;
end else begin
state <= STATE_ERROR;
end
end
end
// Set up sender module to send CMD8
STATE_CMD8_SEND: begin
// Setup command packet
spi_cmd_send_index <= 6'd8;
spi_cmd_send_arg <= 32'h000001AA;
spi_cmd_send_crc <= 7'b1000011; // hardcoded CRC for CMD8
// Enable sending of command
spi_cmd_send_en <= 1;
state <= STATE_R3_R7_SEND;
next_state <= STATE_CMD8_RECV;
end
// Wait for response from CMD8, then verify that we
// are in the idle state with the voltage echoed back
// correctly
STATE_CMD8_RECV: begin
if (spi_r3_r7_recv_done) begin
if (40'h01000001AA == spi_r3_r7_recv_out) begin
state <= STATE_0xFF_WAIT;
next_state <= STATE_CMD55_SEND;
end else begin
state <= STATE_ERROR;
end
end
end
// Set up sender module to send CMD55
STATE_CMD55_SEND: begin
spi_cmd_send_index <= 6'd55;
spi_cmd_send_arg <= 32'h00000000;
spi_cmd_send_crc <= 7'b0000000; // Shouldn't be checked
spi_cmd_send_en <= 1;
state <= STATE_R1_SEND;
next_state <= STATE_CMD55_RECV;
end
// Wait for response from CMD55 and check for errors
STATE_CMD55_RECV: begin
if (spi_r1_recv_done) begin
if (8'b1 == spi_r1_recv_out) begin
state <= STATE_0xFF_WAIT;
next_state <= STATE_ACMD41_SEND;
end else begin
state <= STATE_ERROR;
end
end
end
// Set up sender module to send ACMD41
STATE_ACMD41_SEND: begin
spi_cmd_send_index <= 6'd41;
spi_cmd_send_arg <= 32'h40000000;
spi_cmd_send_crc <= 7'b0000000; // Shouldn't be checked
spi_cmd_send_en <= 1;
state <= STATE_R1_SEND;
next_state <= STATE_ACMD41_RECV;
end
// Wait for response from ACMD41, check for errors, and start
// back at CMD55 if still in idle state
STATE_ACMD41_RECV: begin
if (spi_r1_recv_done) begin
if (8'b1 == spi_r1_recv_out) begin
state <= STATE_0xFF_WAIT;
next_state <= STATE_CMD55_SEND;
end else if (8'b0 == spi_r1_recv_out) begin
state <= STATE_0xFF_WAIT;
next_state <= STATE_CMD58_SEND;
end else begin
state <= STATE_ERROR;
end
end
end
// Set up sender module to send CMD58
STATE_CMD58_SEND: begin
spi_cmd_send_index <= 6'd58;
spi_cmd_send_arg <= 32'h00000000;
spi_cmd_send_crc <= 7'b0000000; // Shouldn't be checked
spi_cmd_send_en <= 1;
state <= STATE_R3_R7_SEND;
next_state <= STATE_CMD58_RECV;
end
// Wait for response from CMD58, check for errors, and then
// check if the CCS (Card Capacity Status) flag is set. This
// indicates 512-byte block level addressing
STATE_CMD58_RECV: begin
if (spi_r3_r7_recv_done) begin
if (8'b0 == spi_r3_r7_recv_out[39:32] &&
spi_r3_r7_recv_out[30]) begin
state <= STATE_CALIB_WAIT;
end else begin
state <= STATE_ERROR;
end
end
end
// Wait for memory calibration to be done, then start
// reading from SD card and storing in RAM
STATE_CALIB_WAIT: begin
if (calib_done) begin
state <= STATE_0xFF_WAIT;
next_state <= STATE_CMD17_SEND;
end
end
// Send CMD17, single block read
STATE_CMD17_SEND: begin
spi_cmd_send_index <= 6'd17;
spi_cmd_send_arg <= { 17'b0, program_index, block_addr }; // Block address
spi_cmd_send_crc <= 7'b0000000; // Shouldn't be checked
spi_cmd_send_en <= 1;
state <= STATE_R1_SEND;
next_state <= STATE_CMD17_RECV;
end
// Wait for response from CMD17, check for errors, then move
// to handle the incoming data packet
STATE_CMD17_RECV: begin
if (spi_r1_recv_done) begin
if (8'b0 == spi_r1_recv_out) begin
spi_data_read_en <= 1;
state <= STATE_DATA_RECV;
end else begin
state <= STATE_ERROR;
end
end
end
// Handle receiving an incoming data packet, and send to RAM
STATE_DATA_RECV: begin
if (spi_data_read_error) begin
state <= STATE_ERROR;
end else if (spi_data_read_done) begin
progress <= progress + 2;
if (127 == block_addr) begin
state <= STATE_DONE;
end else begin
block_addr <= block_addr + 1;
state <= STATE_0xFF_WAIT;
next_state <= STATE_CMD17_SEND;
end
end
end
// Done reading from the card
STATE_DONE: begin
sclk_reset <= 1;
sdcard_cs <= 1;
done <= 1;
end
// There was an error reading from the SD card
STATE_ERROR: begin
sclk_reset <= 1;
sdcard_cs <= 1;
error <= 1;
end
endcase
end
endmodule
|
module elevator(current_floor,leds,switches,clock);
//output wire [2:0] sd_state; // testing only
//integer test[7:0] = {11,12,13,14,15,16,17,18};
input [9:0] switches;
output reg [9:0] leds;
wire [9:0] is_requested;
wire [9:0] request_clear;
input clock;
output wire [4:0] current_floor;
reg [4:0] request_floor;
reg up;
//module elevator_car_driver(current_floor,direction,destination,clock);
elevator_car_driver cd0(request_clear,current_floor,up,request_floor,clock);
// module sequence_detector(current_state,request,clear,switch,clock);
sequence_detector sd0(is_requested[0],
request_clear[0],switches[0],clock);
sequence_detector sd1(is_requested[1],
request_clear[1],switches[1],clock);
sequence_detector sd2(is_requested[2],
request_clear[2],switches[2],clock);
sequence_detector sd3(is_requested[3],
request_clear[3],switches[3],clock);
sequence_detector sd4(is_requested[4],
request_clear[4],switches[4],clock);
sequence_detector sd5(is_requested[5],
request_clear[5],switches[5],clock);
sequence_detector sd6(is_requested[6],
request_clear[6],switches[6],clock);
sequence_detector sd7(is_requested[7],
request_clear[7],switches[7],clock);
sequence_detector sd8(is_requested[8],
request_clear[8],switches[8],clock);
sequence_detector sd9(is_requested[9],
request_clear[9],switches[9],clock);
always @(posedge clock) begin
if (|is_requested) begin
if (is_requested[0]) begin
leds[0] <= 1;
request_floor <= 0;
if (current_floor > 0)
up <= 0;
end
else
leds[0] <= 0;
if (is_requested[1]) begin
leds[1] <= 1;
request_floor <= 1;
if ( current_floor > 1)
up <= 0;
else
up <= 1;
end
else
leds[1] <= 0;
if (is_requested[2]) begin
leds[2] <= 1;
request_floor <= 2;
if ( current_floor > 2)
up <= 0;
else
up <= 1;
end
else
leds[2] <= 0;
end
else
if ( current_floor < 5 ) begin
request_floor <= 0;
up <= 0;
end
else begin
request_floor <= 9;
up <= 1;
end
end
endmodule
/* "Pluggable" modules
*
*/
module elevator_car_driver(clear,current_floor,direction,destination,clock);
output reg [4:0] current_floor; // 0000 to 1010
output reg [9:0] clear;
input direction; // 0 down, 1 up
input [4:0] destination;
input clock; // Slow clock or implement 2 sec delay here ?
reg [4:0] counter;
// which floor do we start at ?
initial begin
current_floor <= 0;
counter <= 0;
end
always @(posedge clock) begin
current_floor <= counter;
end
// Should I add the "state" indicator (moving/stationary)
always @(posedge clock) begin
if ( counter != destination ) begin
clear[counter] <= 0;
if (direction)
counter = counter + 1;
else
counter = counter - 1;
end
else
clear[counter] <= 1;
//we arrived, clear the request
end
endmodule
module sequence_detector(request,clear,switch,clock);
output reg request;
//output reg [2:0] current_state;
input clear,switch,clock;
reg [1:0] state;
parameter state_a=0, state_b=1,state_c=3;
initial begin
state <= state_a;
end
//always @(posedge clock)
// current_state <= state;
always @(posedge clock) begin
case (state)
state_a:
if (switch) begin
state <= state_b;
end
state_b:
if (!switch) begin
state <= state_c;
end
state_c:
if (clear) begin
request <= 0;
state <= state_a;
end
else
request <= 1;
endcase
end
endmodule
/*
*
*/
/* Test benches
*
*/
module testbench_single_request;
reg tbclock;
reg [9:0] sw;
wire [4:0] cf;
wire [9:0] lights;
//module elevator(current_floor,leds,switches,clock);
elevator ev0(cf,lights,sw,tbclock);
initial
tbclock = 1'b0;
always
#1 tbclock = ~tbclock;
initial begin
$monitor("At time",$time," switches:%b,lights:%b,floor:%d",sw,lights,cf);
#200 $finish;
end
initial begin
#5 sw[2] <= 1;
#1 sw[2] <= 0;
#50 sw[1] <= 1;
#1 sw[1] <= 0;
end
endmodule
//--
module testbench_car_driver;
reg course,tbclock;
reg [9:0] target;
wire [9:0] floor;
// module elevator_car_driver(current_floor,direction,destination,clock);
elevator_car_driver cd0(floor,course,target,tbclock);
initial
tbclock = 1'b0;
always
#1 tbclock = ~tbclock;
initial begin
$monitor("At time",$time," target: %h floor: %h",target,floor);
#200 $finish;
end
initial begin
#5 course <= 1;
#1 target <= 5;
#15 course <= 0;
#1 target <= 3;
#15 course <= 1;
#1 target <= 10;
//#45 target <= 10;
end
endmodule
module sequence_detector_testbench;
reg [9:0] switch_in;
reg tb_clock;
wire [9:0] light_out;
wire [9:0] floor_num;
// Original testbench included state of the sequence detector
// Removed it because it's sufficient to observe state change via LED
//wire [2:0] sd_state;
//module elevator(leds,switches,clock);
elevator e0(floor_num,light_out,switch_in,tb_clock);
initial begin
$monitor("At time",$time," switch is %b and led %b. State %b ",switch_in,light_out); //,sd_state);
#200 $finish;
end
initial begin
// original testing was performed with switch[1] being the request_clear input
switch_in = 0;
#20 switch_in[0] = 1;
#20 switch_in[0] = 0;
#20 switch_in[1] = 1;
#20 switch_in[1] = 0;
#20 switch_in[2] = 1;
end
initial
tb_clock = 1'b0;
always
#1 tb_clock = ~tb_clock;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__ISOBUFSRC_8_V
`define SKY130_FD_SC_HDLL__ISOBUFSRC_8_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for isobufsrc with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_8 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__isobufsrc_8 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__ISOBUFSRC_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__OR2B_PP_SYMBOL_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2B_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_SYMBOL_V
`define SKY130_FD_SC_LP__A2111OI_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2111oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_4_V
`define SKY130_FD_SC_HDLL__O21BAI_4_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21bai_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__o21bai_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A2111OI_PP_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2111oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111OI_PP_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: fifo_69x512_hf.v
// /___/ /\ Timestamp: Thu Nov 8 18:55:23 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_69x512_hf.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_69x512_hf.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_69x512_hf.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_69x512_hf.v
// # of Modules : 1
// Design Name : fifo_69x512_hf
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_69x512_hf (
clk, rd_en, rst, empty, wr_en, full, prog_full, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
input rst;
output empty;
input wr_en;
output full;
output prog_full;
output [68 : 0] dout;
input [68 : 0] din;
// synthesis translate_off
wire N0;
wire N1;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_3 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg_10 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_fifo ;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_q_12 ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ALMOSTEMPTY_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_SBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_DBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_DOP<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_DOP<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_DOP<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<12>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<11>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<10>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<9>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<8>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<12>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<11>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<10>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<9>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<8>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_Q15_UNCONNECTED ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rd_rst_i ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/power_on_wr_rst ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb ;
assign
prog_full = \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_q_12 ;
GND XST_GND (
.G(N0)
);
VCC XST_VCC (
.P(N1)
);
FDPE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [0]),
.D(N0),
.PRE(rst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg_10 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_4 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg_10 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [4])
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_3 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [4]),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [3])
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_2 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [3]),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [2])
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_1 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [2]),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [1])
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_0 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [1]),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [0])
);
FIFO36_72_EXP #(
.ALMOST_FULL_OFFSET ( 9'h100 ),
.SIM_MODE ( "SAFE" ),
.DO_REG ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.EN_SYN ( "TRUE" ),
.FIRST_WORD_FALL_THROUGH ( "FALSE" ),
.ALMOST_EMPTY_OFFSET ( 9'h002 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72 (
.RDEN(rd_en),
.WREN(wr_en),
.RST(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rd_rst_i [0]),
.RDCLKU(clk),
.RDCLKL(clk),
.WRCLKU(clk),
.WRCLKL(clk),
.RDRCLKU(clk),
.RDRCLKL(clk),
.ALMOSTEMPTY
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ALMOSTEMPTY_UNCONNECTED ),
.ALMOSTFULL(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_fifo ),
.EMPTY(empty),
.FULL(full),
.RDERR(\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDERR_UNCONNECTED ),
.WRERR(\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRERR_UNCONNECTED ),
.SBITERR(\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_SBITERR_UNCONNECTED ),
.DBITERR(\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_DBITERR_UNCONNECTED ),
.DI({din[63], din[62], din[61], din[60], din[59], din[58], din[57], din[56], din[55], din[54], din[53], din[52], din[51], din[50], din[49],
din[48], din[47], din[46], din[45], din[44], din[43], din[42], din[41], din[40], din[39], din[38], din[37], din[36], din[35], din[34], din[33],
din[32], din[31], din[30], din[29], din[28], din[27], din[26], din[25], din[24], din[23], din[22], din[21], din[20], din[19], din[18], din[17],
din[16], din[15], din[14], din[13], din[12], din[11], din[10], din[9], din[8], din[7], din[6], din[5], din[4], din[3], din[2], din[1], din[0]}),
.DIP({N0, N0, N0, din[68], din[67], din[66], din[65], din[64]}),
.DO({dout[63], dout[62], dout[61], dout[60], dout[59], dout[58], dout[57], dout[56], dout[55], dout[54], dout[53], dout[52], dout[51], dout[50],
dout[49], dout[48], dout[47], dout[46], dout[45], dout[44], dout[43], dout[42], dout[41], dout[40], dout[39], dout[38], dout[37], dout[36], dout[35],
dout[34], dout[33], dout[32], dout[31], dout[30], dout[29], dout[28], dout[27], dout[26], dout[25], dout[24], dout[23], dout[22], dout[21], dout[20],
dout[19], dout[18], dout[17], dout[16], dout[15], dout[14], dout[13], dout[12], dout[11], dout[10], dout[9], dout[8], dout[7], dout[6], dout[5],
dout[4], dout[3], dout[2], dout[1], dout[0]}),
.DOP({\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_DOP<7>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_DOP<6>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_DOP<5>_UNCONNECTED , dout[68],
dout[67], dout[66], dout[65], dout[64]}),
.RDCOUNT({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<12>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<11>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<10>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<9>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<8>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<7>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<6>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<5>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<4>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<3>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<2>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<1>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_RDCOUNT<0>_UNCONNECTED }),
.WRCOUNT({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<12>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<11>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<10>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<9>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<8>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<7>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<6>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<5>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<4>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<3>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<2>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<1>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_WRCOUNT<0>_UNCONNECTED }),
.ECCPARITY({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<7>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<6>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<5>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<4>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<3>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<2>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<1>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gf72.sngfifo36_72_ECCPARITY<0>_UNCONNECTED })
);
FDC #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_q (
.C(clk),
.CLR(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rd_rst_i [0]),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_fifo ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_q_12 )
);
LUT2 #(
.INIT ( 4'hE ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/RD_RST_I<1>1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg_10 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/power_on_wr_rst [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rd_rst_i [0])
);
SRLC16E #(
.INIT ( 16'h001F ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0 (
.A0(N0),
.A1(N0),
.A2(N1),
.A3(N0),
.CE(N1),
.CLK(clk),
.D(N0),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_3 ),
.Q15(\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/power_on_wr_rst_0 (
.C(clk),
.CE(N1),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_3 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/power_on_wr_rst [0])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: DrawMarioScore
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This module displays mario score, game level and mario lives
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DrawMarioScore(
input wire clk,
input wire rst,
input wire [9:0] hcount_in,
input wire hsync_in,
input wire [9:0] vcount_in,
input wire vsync_in,
input wire [23:0] rgb_in,
input wire blnk_in,
input wire [7:0] char_pixels,
output reg [9:0] hcount_out,
output reg hsync_out,
output reg [9:0] vcount_out,
output reg vsync_out,
output reg [23:0] rgb_out,
output reg blnk_out,
output reg [7:0] char_xy,
output reg [3:0] char_line
);
reg [23:0] rgb_nxt;
localparam XPOS = 40;
localparam YPOS = 50;
localparam WIDTH = 552;
localparam HEIGHT = 16;
always @(posedge clk or posedge rst) begin
if(rst) begin
hcount_out <= #1 0;
vcount_out <= #1 0;
hsync_out <= #1 0;
vsync_out <= #1 0;
rgb_out <= #1 0;
blnk_out <= #1 0;
end
else begin
hcount_out <= #1 hcount_in;
vcount_out <= #1 vcount_in;
hsync_out <= #1 hsync_in;
vsync_out <= #1 vsync_in;
rgb_out <= #1 rgb_nxt;
blnk_out <= #1 blnk_in;
end
end
always @* begin
if ((hcount_in >= XPOS) && (hcount_in < XPOS + WIDTH) && (vcount_in >= YPOS) && (vcount_in < YPOS + HEIGHT) && (char_pixels[(XPOS - hcount_in)]))
begin
if(char_xy == 8'h20)
rgb_nxt = 24'hff_ff_00;
else
rgb_nxt = 24'hff_ff_ff;
end
else begin
rgb_nxt = rgb_in; // pass signal through
end
end
always @* begin
char_xy = (hcount_in - XPOS - 1)>>3;
end
always @* begin
char_line = vcount_in - YPOS;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO.v
// Version : 1.3
//
// Description: Programmed I/O module. Design implements 8 KBytes of programmable
//-- memory space. Host processor can access this memory space using
//-- Memory Read 32 and Memory Write 32 TLPs. Design accepts
//-- 1 Double Word (DW) payload length on Memory Write 32 TLP and
//-- responds to 1 DW length Memory Read 32 TLPs with a Completion
//-- with Data TLP (1DW payload).
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width
parameter TCQ = 1
)(
input user_clk,
input user_reset,
input user_lnk_up,
// AXIS
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_completer_id
); // synthesis syn_hier = "hard"
// Local wires
wire req_compl;
wire compl_done;
wire pio_reset_n = user_lnk_up && !user_reset;
//
// PIO instance
//
PIO_EP #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.TCQ( TCQ )
) PIO_EP_inst (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
.req_compl(req_compl), // O
.compl_done(compl_done), // O
.cfg_completer_id ( cfg_completer_id ) // I [15:0]
);
//
// Turn-Off controller
//
PIO_TO_CTRL #(
.TCQ( TCQ )
) PIO_TO_inst (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.req_compl( req_compl ), // I
.compl_done( compl_done ), // I
.cfg_to_turnoff( cfg_to_turnoff ), // I
.cfg_turnoff_ok( cfg_turnoff_ok ) // O
);
endmodule // PIO
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: block_ram_64x1024.v
// /___/ /\ Timestamp: Thu Nov 8 18:33:08 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/block_ram_64x1024.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/block_ram_64x1024.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/block_ram_64x1024.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/block_ram_64x1024.v
// # of Modules : 1
// Design Name : block_ram_64x1024
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module block_ram_64x1024 (
clka, clkb, douta, doutb, wea, web, addra, addrb, dina, dinb
)/* synthesis syn_black_box syn_noprune=1 */;
input clka;
input clkb;
output [63 : 0] douta;
output [63 : 0] doutb;
input [0 : 0] wea;
input [0 : 0] web;
input [9 : 0] addra;
input [9 : 0] addrb;
input [63 : 0] dina;
input [63 : 0] dinb;
// synthesis translate_off
wire N0;
wire N1;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTLATA_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTLATB_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTREGA_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTREGB_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTLATA_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTLATB_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTREGA_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTREGB_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOA<31>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOA<23>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOA<15>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOA<7>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPA<3>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPA<2>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPA<1>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPA<0>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOB<31>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOB<23>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOB<15>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOB<7>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPB<3>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPB<2>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPB<1>_UNCONNECTED ;
wire \NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPB<0>_UNCONNECTED ;
GND XST_GND (
.G(N0)
);
VCC XST_VCC (
.P(N1)
);
RAMB36_EXP #(
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.READ_WIDTH_A ( 36 ),
.READ_WIDTH_B ( 36 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 36 ),
.WRITE_WIDTH_B ( 36 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
\U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP (
.ENAU(N1),
.ENAL(N1),
.ENBU(N1),
.ENBL(N1),
.SSRAU(N0),
.SSRAL(N0),
.SSRBU(N0),
.SSRBL(N0),
.CLKAU(clka),
.CLKAL(clka),
.CLKBU(clkb),
.CLKBL(clkb),
.REGCLKAU(clka),
.REGCLKAL(clka),
.REGCLKBU(clkb),
.REGCLKBL(clkb),
.REGCEAU(N0),
.REGCEAL(N0),
.REGCEBU(N0),
.REGCEBL(N0),
.CASCADEINLATA(N0),
.CASCADEINLATB(N0),
.CASCADEINREGA(N0),
.CASCADEINREGB(N0),
.CASCADEOUTLATA
(\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTLATA_UNCONNECTED )
,
.CASCADEOUTLATB
(\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTLATB_UNCONNECTED )
,
.CASCADEOUTREGA
(\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTREGA_UNCONNECTED )
,
.CASCADEOUTREGB
(\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTREGB_UNCONNECTED )
,
.DIA({dina[34], dina[33], dina[32], dina[31], dina[30], dina[29], dina[28], dina[27], dina[25], dina[24], dina[23], dina[22], dina[21], dina[20],
dina[19], dina[18], dina[16], dina[15], dina[14], dina[13], dina[12], dina[11], dina[10], dina[9], dina[7], dina[6], dina[5], dina[4], dina[3],
dina[2], dina[1], dina[0]}),
.DIPA({dina[35], dina[26], dina[17], dina[8]}),
.DIB({dinb[34], dinb[33], dinb[32], dinb[31], dinb[30], dinb[29], dinb[28], dinb[27], dinb[25], dinb[24], dinb[23], dinb[22], dinb[21], dinb[20],
dinb[19], dinb[18], dinb[16], dinb[15], dinb[14], dinb[13], dinb[12], dinb[11], dinb[10], dinb[9], dinb[7], dinb[6], dinb[5], dinb[4], dinb[3],
dinb[2], dinb[1], dinb[0]}),
.DIPB({dinb[35], dinb[26], dinb[17], dinb[8]}),
.ADDRAL({N0, addra[9], addra[8], addra[7], addra[6], addra[5], addra[4], addra[3], addra[2], addra[1], addra[0], N0, N0, N0, N0, N0}),
.ADDRAU({addra[9], addra[8], addra[7], addra[6], addra[5], addra[4], addra[3], addra[2], addra[1], addra[0], N0, N0, N0, N0, N0}),
.ADDRBL({N0, addrb[9], addrb[8], addrb[7], addrb[6], addrb[5], addrb[4], addrb[3], addrb[2], addrb[1], addrb[0], N0, N0, N0, N0, N0}),
.ADDRBU({addrb[9], addrb[8], addrb[7], addrb[6], addrb[5], addrb[4], addrb[3], addrb[2], addrb[1], addrb[0], N0, N0, N0, N0, N0}),
.WEAU({wea[0], wea[0], wea[0], wea[0]}),
.WEAL({wea[0], wea[0], wea[0], wea[0]}),
.WEBU({N0, N0, N0, N0, web[0], web[0], web[0], web[0]}),
.WEBL({N0, N0, N0, N0, web[0], web[0], web[0], web[0]}),
.DOA({douta[34], douta[33], douta[32], douta[31], douta[30], douta[29], douta[28], douta[27], douta[25], douta[24], douta[23], douta[22],
douta[21], douta[20], douta[19], douta[18], douta[16], douta[15], douta[14], douta[13], douta[12], douta[11], douta[10], douta[9], douta[7], douta[6]
, douta[5], douta[4], douta[3], douta[2], douta[1], douta[0]}),
.DOPA({douta[35], douta[26], douta[17], douta[8]}),
.DOB({doutb[34], doutb[33], doutb[32], doutb[31], doutb[30], doutb[29], doutb[28], doutb[27], doutb[25], doutb[24], doutb[23], doutb[22],
doutb[21], doutb[20], doutb[19], doutb[18], doutb[16], doutb[15], doutb[14], doutb[13], doutb[12], doutb[11], doutb[10], doutb[9], doutb[7], doutb[6]
, doutb[5], doutb[4], doutb[3], doutb[2], doutb[1], doutb[0]}),
.DOPB({doutb[35], doutb[26], doutb[17], doutb[8]})
);
RAMB36_EXP #(
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.READ_WIDTH_A ( 36 ),
.READ_WIDTH_B ( 36 ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 36 ),
.WRITE_WIDTH_B ( 36 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
\U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP (
.ENAU(N1),
.ENAL(N1),
.ENBU(N1),
.ENBL(N1),
.SSRAU(N0),
.SSRAL(N0),
.SSRBU(N0),
.SSRBL(N0),
.CLKAU(clka),
.CLKAL(clka),
.CLKBU(clkb),
.CLKBL(clkb),
.REGCLKAU(clka),
.REGCLKAL(clka),
.REGCLKBU(clkb),
.REGCLKBL(clkb),
.REGCEAU(N0),
.REGCEAL(N0),
.REGCEBU(N0),
.REGCEBL(N0),
.CASCADEINLATA(N0),
.CASCADEINLATB(N0),
.CASCADEINREGA(N0),
.CASCADEINREGB(N0),
.CASCADEOUTLATA
(\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTLATA_UNCONNECTED )
,
.CASCADEOUTLATB
(\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTLATB_UNCONNECTED )
,
.CASCADEOUTREGA
(\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTREGA_UNCONNECTED )
,
.CASCADEOUTREGB
(\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_CASCADEOUTREGB_UNCONNECTED )
,
.DIA({N0, dina[63], dina[62], dina[61], dina[60], dina[59], dina[58], dina[57], N0, dina[56], dina[55], dina[54], dina[53], dina[52], dina[51],
dina[50], N0, dina[49], dina[48], dina[47], dina[46], dina[45], dina[44], dina[43], N0, dina[42], dina[41], dina[40], dina[39], dina[38], dina[37],
dina[36]}),
.DIPA({N0, N0, N0, N0}),
.DIB({N0, dinb[63], dinb[62], dinb[61], dinb[60], dinb[59], dinb[58], dinb[57], N0, dinb[56], dinb[55], dinb[54], dinb[53], dinb[52], dinb[51],
dinb[50], N0, dinb[49], dinb[48], dinb[47], dinb[46], dinb[45], dinb[44], dinb[43], N0, dinb[42], dinb[41], dinb[40], dinb[39], dinb[38], dinb[37],
dinb[36]}),
.DIPB({N0, N0, N0, N0}),
.ADDRAL({N0, addra[9], addra[8], addra[7], addra[6], addra[5], addra[4], addra[3], addra[2], addra[1], addra[0], N0, N0, N0, N0, N0}),
.ADDRAU({addra[9], addra[8], addra[7], addra[6], addra[5], addra[4], addra[3], addra[2], addra[1], addra[0], N0, N0, N0, N0, N0}),
.ADDRBL({N0, addrb[9], addrb[8], addrb[7], addrb[6], addrb[5], addrb[4], addrb[3], addrb[2], addrb[1], addrb[0], N0, N0, N0, N0, N0}),
.ADDRBU({addrb[9], addrb[8], addrb[7], addrb[6], addrb[5], addrb[4], addrb[3], addrb[2], addrb[1], addrb[0], N0, N0, N0, N0, N0}),
.WEAU({wea[0], wea[0], wea[0], wea[0]}),
.WEAL({wea[0], wea[0], wea[0], wea[0]}),
.WEBU({N0, N0, N0, N0, web[0], web[0], web[0], web[0]}),
.WEBL({N0, N0, N0, N0, web[0], web[0], web[0], web[0]}),
.DOA({
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOA<31>_UNCONNECTED ,
douta[63], douta[62], douta[61], douta[60], douta[59], douta[58], douta[57],
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOA<23>_UNCONNECTED ,
douta[56], douta[55], douta[54], douta[53], douta[52], douta[51], douta[50],
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOA<15>_UNCONNECTED ,
douta[49], douta[48], douta[47], douta[46], douta[45], douta[44], douta[43],
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOA<7>_UNCONNECTED ,
douta[42], douta[41], douta[40], douta[39], douta[38], douta[37], douta[36]}),
.DOPA({
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPA<3>_UNCONNECTED ,
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPA<2>_UNCONNECTED ,
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPA<1>_UNCONNECTED ,
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPA<0>_UNCONNECTED })
,
.DOB({
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOB<31>_UNCONNECTED ,
doutb[63], doutb[62], doutb[61], doutb[60], doutb[59], doutb[58], doutb[57],
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOB<23>_UNCONNECTED ,
doutb[56], doutb[55], doutb[54], doutb[53], doutb[52], doutb[51], doutb[50],
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOB<15>_UNCONNECTED ,
doutb[49], doutb[48], doutb[47], doutb[46], doutb[45], doutb[44], doutb[43],
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOB<7>_UNCONNECTED ,
doutb[42], doutb[41], doutb[40], doutb[39], doutb[38], doutb[37], doutb[36]}),
.DOPB({
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPB<3>_UNCONNECTED ,
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPB<2>_UNCONNECTED ,
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPB<1>_UNCONNECTED ,
\NLW_U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/TRUE_DP.SINGLE_PRIM36.TDP_DOPB<0>_UNCONNECTED })
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog wrapper for dlymetal6s2s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlymetal6s2s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlymetal6s2s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlymetal6s2s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlymetal6s2s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlymetal6s2s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSTP_2_V
`define SKY130_FD_SC_LS__DFSTP_2_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog wrapper for dfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfstp_2 (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfstp_2 (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSTP_2_V
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- This module sequences ARM LDM/STM CISC instructions into simpler RISC --
// -- instructions. Basically LDM -> LDRs and STM -> STRs. Supports a base --
// -- restored abort model. Start instruction carries interrupt information --
// -- so this cannot block interrupts if there is a sequence of these. --
// -- --
// -- Also handles SWAP instruction. --
// -- --
// -- SWAP steps: --
// -- - Read data from [Rn] into DUMMY. - LDR DUMMY0, [Rn] --
// -- - Write data in Rm to [Rn] - STR Rm, [Rn] --
// -- - Copy data from DUMMY to Rd. - MOV Rd, DUMMY0 --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_predecode_mem_fsm
(
// Clock and reset.
input wire i_clk, // ZAP clock.
input wire i_reset, // ZAP reset.
// Instruction information from the fetch.
input wire [34:0] i_instruction,
input wire i_instruction_valid,
// Interrupt information from the fetch.
input wire i_irq,
input wire i_fiq,
// CPSR
input wire i_cpsr_t,
// Pipeline control signals.
input wire i_clear_from_writeback,
input wire i_data_stall,
input wire i_clear_from_alu,
input wire i_stall_from_shifter,
input wire i_issue_stall,
// Instruction output.
output reg [39:0] o_instruction,
output reg o_instruction_valid,
// We generate a stall.
output reg o_stall_from_decode,
// Possibly masked interrupts.
output reg o_irq,
output reg o_fiq
);
///////////////////////////////////////////////////////////////////////////////
`include "zap_defines.vh"
`include "zap_localparams.vh"
`include "zap_functions.vh"
///////////////////////////////////////////////////////////////////////////////
// Instruction breakup
wire [3:0] cc ;
wire [2:0] id ;
wire pre_index ;
wire up ;
wire s_bit ;
wire writeback ;
wire load ;
wire [3:0] base ;
wire [15:0] reglist ;
// Instruction breakup assignment.
assign {cc, id, pre_index, up, s_bit, writeback, load, base, reglist} = i_instruction;
wire store = !load;
wire link = i_instruction[24];
wire [11:0] branch_offset = i_instruction[11:0];
wire [11:0] oc_offset; // Ones counter offset.
reg [4:0] state_ff, state_nxt; // State.
reg [15:0] reglist_ff, reglist_nxt; // Register list.
reg [31:0] const_ff, const_nxt; // For BLX - const reg.
///////////////////////////////////////////////////////////////////////////////
// States.
localparam IDLE = 0;
localparam MEMOP = 1;
localparam WRITE_PC = 2;
localparam SWAP1 = 3;
localparam SWAP2 = 4;
localparam LMULT_BUSY = 5;
localparam BL_S1 = 6;
localparam SWAP3 = 7;
localparam BLX1_ARM_S0 = 8;
localparam BLX1_ARM_S1 = 9;
localparam BLX1_ARM_S2 = 10;
localparam BLX1_ARM_S3 = 11;
localparam BLX1_ARM_S4 = 12;
localparam BLX1_ARM_S5 = 13;
localparam BLX2_ARM_S0 = 14;
localparam LDRD_STRD_S0 = 16;
localparam LDRD_STRD_S1 = 17;
///////////////////////////////////////////////////////////////////////////////
assign oc_offset = ones_counter(i_instruction);
///////////////////////////////////////////////////////////////////////////////
// Next state and output logic.
always @*
begin:blk_a
reg H;
reg [3:0] pri_enc_out;
reg [3:0] rd;
const_nxt = const_ff;
H = 0;
pri_enc_out = 0;
rd = 0;
// Block interrupts by default.
o_irq = 0;
o_fiq = 0;
// Avoid latch inference.
state_nxt = state_ff;
o_instruction = i_instruction;
o_instruction_valid = i_instruction_valid;
reglist_nxt = reglist_ff;
o_stall_from_decode = 1'd0;
case ( state_ff )
BLX1_ARM_S0: // SCONST = ($signed(constant) << 2) + ( H << 1 ))
begin
o_stall_from_decode = 1'd1;
H = i_instruction[24];
const_nxt = ( { {8{i_instruction[23]}} , i_instruction[23:0] } << 2 ) + ( H << 1 );
// MOV DUMMY0, SCONST[7:0] ror 0
o_instruction[31:0] = {AL, 2'b00, 1'b1, MOV, 1'd0, 4'd0, 4'd0, 4'd0, const_nxt[7:0]};
{o_instruction[`DP_RD_EXTEND], o_instruction[`DP_RD]} = ARCH_DUMMY_REG0;
state_nxt = BLX1_ARM_S1;
end
BLX1_ARM_S1:
begin
o_stall_from_decode = 1'd1;
// ORR DUMMY0, DUMMY0, SCONST[15:8] ror 12*2
o_instruction[31:0] = {AL, 2'b00, 1'b1, ORR, 1'd0, 4'd0, 4'd0, 4'd12, const_nxt[15:8]};
{o_instruction[`DP_RD_EXTEND], o_instruction[`DP_RD]} = ARCH_DUMMY_REG0;
{o_instruction[`DP_RA_EXTEND], o_instruction[`DP_RA]} = ARCH_DUMMY_REG0;
state_nxt = BLX1_ARM_S2;
end
BLX1_ARM_S2:
begin
o_stall_from_decode = 1'd1;
// ORR DUMMY0, DUMMY0, SCONST[23:16] ror 8*2
o_instruction[31:0] = {AL, 2'b00, 1'b1, ORR, 1'd0, 4'd0, 4'd0, 4'd8, const_nxt[23:16]};
{o_instruction[`DP_RD_EXTEND], o_instruction[`DP_RD]} = ARCH_DUMMY_REG0;
{o_instruction[`DP_RA_EXTEND], o_instruction[`DP_RA]} = ARCH_DUMMY_REG0;
state_nxt = BLX1_ARM_S3;
end
BLX1_ARM_S3:
begin
o_stall_from_decode = 1'd1;
// ORR DUMMY0, DUMMY0, SCONST[31:24] ror 4*2
o_instruction[31:0] = {AL, 2'b00, 1'b1, ORR, 1'd0, 4'd0, 4'd0, 4'd4, const_nxt[31:24]};
{o_instruction[`DP_RD_EXTEND], o_instruction[`DP_RD]} = ARCH_DUMMY_REG0;
{o_instruction[`DP_RA_EXTEND], o_instruction[`DP_RA]} = ARCH_DUMMY_REG0;
state_nxt = BLX1_ARM_S4;
end
BLX1_ARM_S4:
begin
o_stall_from_decode = 1'd1;
// ORR DUMMY0, DUMMY0, 1 - Needed to indicate a switch
// to Thumb if needed.
o_instruction[31:0] = {AL, 2'b00, 1'b1, ORR, 1'd0, 4'd0, 4'd0, 4'd0, !i_cpsr_t};
{o_instruction[`DP_RD_EXTEND], o_instruction[`DP_RD]} = ARCH_DUMMY_REG0;
{o_instruction[`DP_RA_EXTEND], o_instruction[`DP_RA]} = ARCH_DUMMY_REG0;
state_nxt = BLX1_ARM_S5;
end
BLX1_ARM_S5:
begin
// Remove stall.
o_stall_from_decode = 1'd0;
// BX DUMMY0
o_instruction = 32'hE12FFF10;
{o_instruction[`DP_RB_EXTEND], o_instruction[`DP_RB]} = ARCH_DUMMY_REG0;
state_nxt = IDLE;
end
BLX2_ARM_S0:
begin
// Remove stall.
o_stall_from_decode = 1'd0;
// BX Rm. Just remove the L bit. Conditional is passed
// on.
o_instruction = i_instruction;
o_instruction[5] = 1'd0;
state_nxt = IDLE;
end
LDRD_STRD_S0:
begin
o_stall_from_decode = 1'd0;
o_instruction[31:28] = i_instruction[31:28];
o_instruction[27:26] = 2'b01;
o_instruction[15:12] = i_instruction[15:12] + 1;
o_instruction[24:23] = i_instruction[24:23];
o_instruction[19:16] = i_instruction[19:16];
o_instruction[22] = 1'd0;
// If writeback was specified, generate LDR Rdata, [Raddress, #4] for the next load.
// Make it pre-indexing without writeback in this case.
if ( i_instruction[21] )
begin
o_instruction[11:0] = 32'd4;
o_instruction[25] = 1'd1;
o_instruction[21] = 1'd0;
end
else // No writeback.
begin
if ( i_instruction[22] )
begin
// If no writeback was specified, issue +4 to immediate (for I mode) for the next
// address.
o_instruction[11:0] = o_instruction[11:0] + 32'd4;
o_instruction[25] = 1'd1;
state_nxt = IDLE;
end
else
begin
// If no writeback was specified and in register mode, issue + 4 to the register.
// This requires the register to be temporarily added by 4.
// 1.
// Generate ADDAL ARCH_DUMMY_REG0, Register, #4
o_instruction[31:0] =
{AL, 2'b00, 1'b1, ADD, 1'd0, 4'd0, i_instruction[19:16], 12'd4};
{o_instruction[`DP_RD_EXTEND], o_instruction[`DP_RD]}= ARCH_DUMMY_REG0;
state_nxt = LDRD_STRD_S1;
o_stall_from_decode = 1'd1;
end
end
if ( i_instruction[6:5] == 2'b11 )
o_instruction[20] = 1'd0; // Store
else
o_instruction[20] = 1'd1; // Load
end
LDRD_STRD_S1:
begin
o_stall_from_decode = 1'd0;
o_instruction[31:28] = i_instruction[31:28];
// Use arch dummy reg0 as the base address since it was incremented by 4.
o_instruction[15:12] = i_instruction[15:12] + 1;
o_instruction[27:26] = 2'b01;
o_instruction[25] = 1'd0;
o_instruction[11:0] = i_instruction[3:0];
o_instruction[24:23] = i_instruction[24:23];
o_instruction[22] = 1'd0;
o_instruction[21] = i_instruction[21];
o_instruction[15:12] = i_instruction[15:12];
{o_instruction[`DP_RA_EXTEND], o_instruction[`DP_RA]} = ARCH_DUMMY_REG0;
if ( i_instruction[6:5] == 2'b11 )
o_instruction[20] = 1'd0; // Store
else
o_instruction[20] = 1'd1; // Load
state_nxt = IDLE;
end
IDLE:
begin
// LDRD and STRD (First register should be EVEN)
if ( i_instruction[27:25] == 3'b000 &&
i_instruction[20] == 1'd0 &&
( i_instruction[6:5] == 2'b10 || i_instruction[6:5] == 2'b11 ) &&
i_instruction[12] == 1'd0 &&
i_instruction_valid )
begin
// If writeback is specified, the address of the second load is the writeback value
// with 4 added to it. The written back value holds the result of executing the
// first load.
//
// If writeback is not specified, the address of the second load is 4 more than the
// address of the first load.
o_stall_from_decode = 1'd1;
o_instruction[27:26] = 2'b01; // Make it an ARM classic load-store.
// Specify addressing mode.
if ( i_instruction[22] ) // Immediate.
begin
o_instruction[25] = 1'd1;
o_instruction[11:0] = $signed({i_instruction[11:8], i_instruction[3:0]});
end
else
begin
o_instruction[25] = 1'd0;
o_instruction[11:0] = i_instruction[3:0];
end
o_instruction[24:23] = i_instruction[24:23];
o_instruction[22] = 1'd0;
o_instruction[21] = i_instruction[21];
// Load or Store.
if ( i_instruction[6:5] == 2'b11 )
o_instruction[20] = 1'd0; // Store
else
o_instruction[20] = 1'd1; // Load
o_instruction[19:12] = i_instruction[19:12];
state_nxt = LDRD_STRD_S0;
// Fine to give IRQs.
o_irq = i_irq;
o_fiq = i_fiq;
end
// BLX1 detected. Unconditional!!!
// Immediate Offset.
else if ( i_instruction[31:25] == BLX1[31:25] && i_instruction_valid )
begin
// We must generate a SUBAL LR,PC,4 ROR 0
// This makes LR have the value
// PC+8-4=PC+4 which is the address of
// the next instruction.
o_instruction = {AL, 2'b00, 1'b1, SUB, 1'd0, 4'd14, 4'd15, 12'd4};
// In Thumb mode, we must generate PC+4-2
if ( i_cpsr_t )
begin
o_instruction[11:0] = 12'd2; // Modify the instruction.
end
o_stall_from_decode = 1'd1; // Stall the core.
state_nxt = BLX1_ARM_S0;
o_irq = i_irq;
o_fiq = i_fiq;
end
// BLX2 detected. Register offset. CONDITIONAL.
else if ( i_instruction[27:4] == BLX2[27:4] && i_instruction_valid )
begin
// Write address of next instruction to LR. Now this
// depends on the mode we're in. Mode in the sense
// ARM/Thumb. We need to look at i_cpsr_t.
// We need to generate a SUBcc LR,PC,4 ROR 0
// to store the next instruction address in
// LR.
o_instruction =
{i_instruction[31:28], 2'b00, 1'b1, SUB, 1'd0, 4'd14, 4'd15, 12'd4};
// In Thumb mode, we need to remove 2 from PC
// instead of 4.
if ( i_cpsr_t )
begin
o_instruction[11:0] = 12'd2; // modify instr.
end
o_stall_from_decode = 1'd1; // Stall the core.
state_nxt = BLX2_ARM_S0;
o_irq = i_irq;
o_fiq = i_fiq;
end
// LDM/STM detected...
else if ( id == 3'b100 && i_instruction_valid )
begin
// Backup base register.
// MOV DUMMY0, Base
if ( up )
begin
o_instruction = {cc, 2'b00, 1'b0, MOV,
1'b0, 4'd0, 4'd0, 8'd0, base};
{o_instruction[`DP_RD_EXTEND],
o_instruction[`DP_RD]}
= ARCH_DUMMY_REG0;
end
else
begin
// SUB DUMMY0, BASE, OFFSET
o_instruction = {cc, 2'b00, 1'b1, SUB,
1'd0, base, 4'd0, oc_offset};
{o_instruction[`DP_RD_EXTEND],
o_instruction[`DP_RD]} =
ARCH_DUMMY_REG0;
end
o_instruction_valid = 1'd1;
reglist_nxt = reglist;
state_nxt = MEMOP;
o_stall_from_decode = 1'd1;
// Take interrupt on this.
o_irq = i_irq;
o_fiq = i_fiq;
end
else if ( i_instruction[27:23] == 5'b00010 &&
i_instruction[21:20] == 2'b00 &&
i_instruction[11:4] == 4'b1001 && i_instruction_valid ) // SWAP
begin
o_irq = i_irq;
o_fiq = i_fiq;
// dummy = *(rn) - LDR ARCH_DUMMY_REG0, [rn, #0]
state_nxt = SWAP1;
o_instruction = {cc, 3'b010, 1'd1, 1'd0,
i_instruction[22], 1'd0, 1'd1,
i_instruction[19:16], 4'b0000, 12'd0};
// The 0000 is replaced with dummy0 below.
{o_instruction[`SRCDEST_EXTEND],
o_instruction[`SRCDEST]} = ARCH_DUMMY_REG0;
o_instruction_valid = 1'd1;
o_stall_from_decode = 1'd1;
end
else if ( i_instruction[27:23] == 5'd1 &&
i_instruction[7:4] == 4'b1001 && i_instruction_valid )
begin
// LMULT
state_nxt = LMULT_BUSY;
o_stall_from_decode = 1'd1;
o_irq = i_irq;
o_fiq = i_fiq;
o_instruction = i_instruction;
o_instruction_valid = i_instruction_valid;
end
else if ( i_instruction[27:23] == 5'b00010 &&
i_instruction[22:21] == 2'b10 &&
!i_instruction[20] &&
i_instruction[7] && i_instruction[4] )
begin
// LMULT
state_nxt = LMULT_BUSY;
o_stall_from_decode = 1'd1;
o_irq = i_irq;
o_fiq = i_fiq;
o_instruction = i_instruction;
o_instruction_valid = i_instruction_valid;
end
else if ( i_instruction[27:25] == 3'b101 &&
i_instruction[24] && i_instruction_valid ) // BL.
begin
// Move to new state. In that state, we will
// generate a plain branch.
state_nxt = BL_S1;
// PC will stall preventing the fetch from
// presenting new data.
o_stall_from_decode = 1'd1;
if ( i_cpsr_t == 1'd0 ) // ARM
begin
// PC is 8 bytes ahead.
// Craft a SUB LR, PC, 4.
o_instruction = {i_instruction[31:28],
28'h24FE004};
end
else
begin
// PC is 4 bytes ahead...
// Craft a SUB LR, PC, 1 so that return
// goes to the next 16bit instruction
// and making LSB of LR = 1.
o_instruction = {i_instruction[31:28],
28'h24FE001};
end
// Sell it as a valid instruction
o_instruction_valid = 1;
// Allow interrupts to pass
o_irq = i_irq;
o_fiq = i_fiq;
end
else
begin
// Be transparent.
state_nxt = state_ff;
o_stall_from_decode = 1'd0;
o_instruction = i_instruction;
o_instruction_valid = i_instruction_valid;
reglist_nxt = 16'd0;
// Allow interrupts to pass.
o_irq = i_irq;
o_fiq = i_fiq;
end
end
BL_S1:
begin
// Launch out the original instruction clearing the
// link bit. This is like MOV PC, <Whatever>
o_instruction = i_instruction & ~(1 << 24);
o_instruction_valid = i_instruction_valid;
// Move to IDLE state.
state_nxt = IDLE;
// Free the fetch from your clutches.
o_stall_from_decode = 1'd0;
// Continue to silence interrupts.
o_irq = 0;
o_fiq = 0;
end
LMULT_BUSY:
begin
o_irq = 0;
o_fiq = 0;
o_instruction = {1'd1, i_instruction};
o_instruction_valid = i_instruction_valid;
o_stall_from_decode = 1'd0;
state_nxt = IDLE;
end
SWAP1, SWAP3:
begin
// STR Rm, [Rn, #0]
o_irq = 0;
o_fiq = 0;
// If in SWAP3, end the sequence so get next operation
// in when we move to IDLE.
o_stall_from_decode = state_ff == SWAP3 ? 1'd0 : 1'd1;
o_instruction_valid = 1;
o_instruction = {cc, 3'b010, 1'd1, 1'd0,
i_instruction[22], 1'd0, 1'd0,
i_instruction[19:16],
i_instruction[3:0], 12'd0}; // BUG FIX
state_nxt = state_ff == SWAP3 ? IDLE : SWAP2;
end
SWAP2:
begin:SWP2BLK
// MOV Rd, DUMMY0
rd = i_instruction[15:12];
// Keep waiting. Next we initiate a read to ensure
// write buffer gets flushed.
o_stall_from_decode = 1'd1;
o_instruction_valid = 1'd1;
o_irq = 0;
o_fiq = 0;
o_instruction = {cc, 2'b00, 1'd0, MOV, 1'd0, 4'b0000,
rd, 12'd0}; // ALU src doesn't matter.
{o_instruction[`DP_RB_EXTEND], o_instruction[`DP_RB]}
= ARCH_DUMMY_REG0;
state_nxt = SWAP3;
end
MEMOP:
begin
// Memory operations happen here.
pri_enc_out = pri_enc(reglist_ff);
reglist_nxt = reglist_ff & ~(16'd1 << pri_enc_out);
o_irq = 0;
o_fiq = 0;
// The map function generates a base restore
// instruction if reglist = 0.
o_instruction = map ( i_instruction, pri_enc_out,
reglist_ff );
o_instruction_valid = 1'd1;
if ( reglist_ff == 0 )
begin
if ( i_instruction[ARCH_PC] && load )
begin
o_stall_from_decode = 1'd1;
state_nxt = WRITE_PC;
end
else
begin
o_stall_from_decode = 1'd0;
state_nxt = IDLE;
end
end
else
begin
state_nxt = MEMOP;
o_stall_from_decode = 1'd1;
end
end
// If needed, we finally write to the program counter as
// either a MOV PC, LR or MOVS PC, LR.
WRITE_PC:
begin
// MOV(S) PC, ARCH_DUMMY_REG1
state_nxt = IDLE;
o_stall_from_decode = 1'd0;
o_instruction =
{ cc, 2'b00, 1'd0, MOV, s_bit, 4'd0, ARCH_PC,
8'd0, 4'd0 };
{o_instruction[`DP_RB_EXTEND], o_instruction[`DP_RB]}
= ARCH_DUMMY_REG1;
o_instruction_valid = 1'd1;
o_irq = 0;
o_fiq = 0;
end
endcase
end
///////////////////////////////////////////////////////////////////////////////
function [33:0] map ( input [31:0] instr, input [3:0] enc, input [15:0] list );
// These override the globals within the function scope.
reg [3:0] cc;
reg [2:0] id;
reg pre_index;
reg up;
reg s_bit;
reg writeback;
reg load;
reg [3:0] base;
reg [15:0] reglist;
reg store;
reg restore;
begin
restore = 0;
{cc, id, pre_index, up, s_bit, writeback, load, base, reglist} = instr;
store = !load;
map = instr;
map = map & ~(1<<22); // No byte access.
map = map & ~(1<<25); // Constant Offset (of 4).
map[23] = 1'd1; // Hard wired to increment.
map[11:0] = 12'd4; // Offset
map[27:26] = 2'b01; // Memory instruction.
map[`SRCDEST] = enc;
{map[`BASE_EXTEND],map[`BASE]} = ARCH_DUMMY_REG0;//Use as base register.
// If not up, then DA -> IB and DB -> IA.
if ( !up ) // DA or DB.
begin
map[24] = !map[24]; // Post <---> Pre switch.
end
// Since the indexing has swapped (possibly), we must rethink map[21].
if ( map[24] == 0 ) // Post index.
begin
map[21] = 1'd0; // Writeback is implicit.
end
else // Pre-index - Must specify writeback.
begin
map[21] = 1'd1;
end
if ( list == 0 ) // Catch 0 list here itself...
begin
// Restore base. MOV Rbase, DUMMY0
if ( writeback )
begin
restore = 1;
if ( up ) // Original instruction asked increment.
begin
map =
{ cc, 2'b0, 1'b0, MOV, 1'b0, 4'd0,
base, 8'd0, 4'd0 };
{map[`DP_RB_EXTEND],map[`DP_RB]} =
ARCH_DUMMY_REG0;
end
else
begin // Restore.
// SUB BASE, BASE, #OFFSET
map = {cc, 2'b00, 1'b1, SUB,
1'd0, base, base, oc_offset};
end
end
else
begin
map = 32'd0; // Wasted cycle.
end
end
else if ( (store && s_bit) || (load && s_bit && !list[15]) )
// STR with S bit or LDR with S bit and no PC - force user bank access.
begin
case ( map[`SRCDEST] ) // Force user bank.
8: {map[`SRCDEST_EXTEND],map[`SRCDEST]} = ARCH_USR2_R8;
9: {map[`SRCDEST_EXTEND],map[`SRCDEST]} = ARCH_USR2_R9;
10:{map[`SRCDEST_EXTEND],map[`SRCDEST]} = ARCH_USR2_R10;
11:{map[`SRCDEST_EXTEND],map[`SRCDEST]} = ARCH_USR2_R11;
12:{map[`SRCDEST_EXTEND],map[`SRCDEST]} = ARCH_USR2_R12;
13:{map[`SRCDEST_EXTEND],map[`SRCDEST]} = ARCH_USR2_R13;
14:{map[`SRCDEST_EXTEND],map[`SRCDEST]} = ARCH_USR2_R14;
endcase
end
else if ( load && enc == 15 )
//
// Load with PC in register list. Load to dummy register.
// Will never use user bank.
//
begin
//
// If S = 1, perform an atomic return.
// If S = 0, just write to PC i.e., a jump.
//
// For now, load to ARCH_DUMMY_REG1.
//
{map[`SRCDEST_EXTEND],map[`SRCDEST]} = ARCH_DUMMY_REG1;
end
end
endfunction
///////////////////////////////////////////////////////////////////////////////
always @ (posedge i_clk)
begin
if ( i_reset ) clear;
else if ( i_clear_from_writeback) clear;
else if ( i_data_stall ) begin end // Stall CPU.
else if ( i_clear_from_alu ) clear;
else if ( i_stall_from_shifter ) begin end
else if ( i_issue_stall ) begin end
else
begin
state_ff <= state_nxt;
reglist_ff <= reglist_nxt;
const_ff <= const_nxt;
end
end
///////////////////////////////////////////////////////////////////////////////
// Unit is reset.
task clear;
begin
state_ff <= IDLE;
reglist_ff <= 16'd0;
const_ff <= 32'd0;
end
endtask
// Counts the number of ones and multiplies that by 4 to get final
// address offset.
function [11:0] ones_counter (
input [15:0] i_word // Register list.
);
integer i;
reg [11:0] offset;
begin
offset = 0;
// Counter number of ones.
for(i=0;i<16;i=i+1)
offset = offset + i_word[i];
// Since LDM and STM occur only on 4 byte regions, compute the
// net offset.
offset = (offset << 2); // Multiply by 4.
ones_counter = offset;
end
endfunction
//
// Function to model a 16-bit priority encoder.
//
// Priority encoder.
function [3:0] pri_enc ( input [15:0] in );
begin: priEncFn
casez ( in )
16'b????_????_????_???1: pri_enc = 4'd0;
16'b????_????_????_??10: pri_enc = 4'd1;
16'b????_????_????_?100: pri_enc = 4'd2;
16'b????_????_????_1000: pri_enc = 4'd3;
16'b????_????_???1_0000: pri_enc = 4'd4;
16'b????_????_??10_0000: pri_enc = 4'd5;
16'b????_????_?100_0000: pri_enc = 4'd6;
16'b????_????_1000_0000: pri_enc = 4'd7;
16'b????_???1_0000_0000: pri_enc = 4'd8;
16'b????_??10_0000_0000: pri_enc = 4'd9;
16'b????_?100_0000_0000: pri_enc = 4'hA;
16'b????_1000_0000_0000: pri_enc = 4'hB;
16'b???1_0000_0000_0000: pri_enc = 4'hC;
16'b??10_0000_0000_0000: pri_enc = 4'hD;
16'b?100_0000_0000_0000: pri_enc = 4'hE;
16'b1000_0000_0000_0000: pri_enc = 4'hF;
default: pri_enc = 4'h0;
endcase
end
endfunction
endmodule // zap_predecode_mem_fsm.v
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_TB_V
`define SKY130_FD_SC_HDLL__AND4B_TB_V
/**
* and4b: 4-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and4b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_hdll__and4b dut (.A_N(A_N), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22AI_BEHAVIORAL_PP_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Michael Christen
//
// Create Date: 11:32:43 03/09/2015
// Design Name:
// Module Name: hcsr04
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module hcsr04 #(
parameter TRIGGER_DURATION = 500,
parameter MAX_COUNT = 3000000
)(
input rst,
input clk,
input tclk,
input measure,
input echo,
output reg [15:0] ticks,
output reg valid,
output reg trigger
);
localparam STATE_SIZE = 3,
CTR_SIZE = 16;
localparam STATE_RESET = 3'd0,
STATE_IDLE = 3'd1,
STATE_TRIGGER = 3'd2,
STATE_COUNT = 3'd3,
STATE_COOLDOWN = 3'd4;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [15:0] ticks_d;
reg trigger_d, valid_d;
reg echo_old;
reg echo_chg, echo_pos, echo_neg;
always @(*) begin
echo_chg = echo_old ^ echo;
echo_pos = echo_chg & echo;
echo_neg = echo_chg & (~echo);
ctr_d = ctr_q;
state_d = state_q;
trigger_d = 0;
valid_d = valid;
ticks_d = ticks;
case (state_q)
STATE_RESET: begin
ctr_d = 0;
valid_d = 0;
ticks_d = 0;
state_d = STATE_IDLE;
end
STATE_IDLE: begin
ctr_d = 0;
if(measure) begin
state_d = STATE_TRIGGER;
end else begin
state_d = STATE_IDLE;
end
end
STATE_TRIGGER: begin
if(tclk) begin
ctr_d = ctr_q + 1;
end
trigger_d = 1'b1;
if(ctr_q == TRIGGER_DURATION) begin
state_d = STATE_COUNT;
end
end
STATE_COUNT: begin
if(tclk) begin
ctr_d = ctr_q + 1;
end
if(ctr_q == MAX_COUNT) begin
ticks_d = MAX_COUNT;
state_d = STATE_IDLE;
end else if(echo_neg) begin
ticks_d = ctr_q;
valid_d = 1'b1;
state_d = STATE_IDLE;
end else if(echo_pos) begin
ctr_d = 0;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= STATE_RESET;
ctr_q <= 0;
ticks <= 0;
valid <= 0;
trigger <= 0;
echo_old <= 0;
end else begin
state_q <= state_d;
ctr_q <= ctr_d;
ticks <= ticks_d;
valid <= valid_d;
trigger <= trigger_d;
echo_old <= echo;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CLKINV_PP_BLACKBOX_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_PP_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : v6_pcie_v1_7.v
// Version : 1.7
//--
//-- Description: Virtex6 solution wrapper : Endpoint for PCI Express
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
(* CORE_GENERATION_INFO = "v6_pcie_v1_7,v6_pcie_v1_7,{LINK_CAP_MAX_LINK_SPEED=2,LINK_CAP_MAX_LINK_WIDTH=04,PCIE_CAP_DEVICE_PORT_TYPE=0000,DEV_CAP_MAX_PAYLOAD_SUPPORTED=2,USER_CLK_FREQ=3,REF_CLK_FREQ=2,MSI_CAP_ON=TRUE,MSI_CAP_MULTIMSGCAP=0,MSI_CAP_MULTIMSG_EXTENSION=0,MSIX_CAP_ON=FALSE,TL_TX_RAM_RADDR_LATENCY=0,TL_TX_RAM_RDATA_LATENCY=2,TL_RX_RAM_RADDR_LATENCY=0,TL_RX_RAM_RDATA_LATENCY=2,TL_RX_RAM_WRITE_LATENCY=0,VC0_TX_LASTPACKET=29,VC0_RX_RAM_LIMIT=7FF,VC0_TOTAL_CREDITS_PH=32,VC0_TOTAL_CREDITS_PD=308,VC0_TOTAL_CREDITS_NPH=12,VC0_TOTAL_CREDITS_CH=36,VC0_TOTAL_CREDITS_CD=308,VC0_CPL_INFINITE=TRUE,DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT=0,DEV_CAP_EXT_TAG_SUPPORTED=FALSE,LINK_STATUS_SLOT_CLOCK_CONFIG=FALSE,ENABLE_RX_TD_ECRC_TRIM=FALSE,DISABLE_LANE_REVERSAL=TRUE,DISABLE_SCRAMBLING=FALSE,DSN_CAP_ON=TRUE,PIPE_PIPELINE_STAGES=0,REVISION_ID=02,VC_CAP_ON=FALSE}" *)
module v6_pcie_v1_7 # (
parameter ALLOW_X8_GEN2 = "FALSE",
parameter BAR0 = 32'hFF000000,
parameter BAR1 = 32'hFFFF0000,
parameter BAR2 = 32'h00000000,
parameter BAR3 = 32'h00000000,
parameter BAR4 = 32'h00000000,
parameter BAR5 = 32'h00000000,
parameter CARDBUS_CIS_POINTER = 32'h00000000,
parameter CLASS_CODE = 24'h050000,
parameter CMD_INTX_IMPLEMENTED = "TRUE",
parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE",
parameter CPL_TIMEOUT_RANGES_SUPPORTED = 4'h2,
parameter DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter DEV_CAP_ENDPOINT_L1_LATENCY = 7,
parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE",
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2,
parameter DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0,
parameter DEVICE_ID = 16'h4243,
parameter DISABLE_LANE_REVERSAL = "TRUE",
parameter DISABLE_SCRAMBLING = "FALSE",
parameter DSN_BASE_PTR = 12'h100,
parameter DSN_CAP_NEXTPTR = 12'h000,
parameter DSN_CAP_ON = "TRUE",
parameter ENABLE_MSG_ROUTE = 11'h00000000000,
parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE",
parameter EXPANSION_ROM = 32'h00000000,
parameter EXT_CFG_CAP_PTR = 6'h3F,
parameter EXT_CFG_XP_CAP_PTR = 10'h3FF,
parameter HEADER_TYPE = 8'h00,
parameter INTERRUPT_PIN = 8'h1,
parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE",
parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE",
parameter LINK_CAP_MAX_LINK_SPEED = 4'h2,
parameter LINK_CAP_MAX_LINK_WIDTH = 6'h04,
parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE",
parameter LINK_CTRL2_DEEMPHASIS = "FALSE",
parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE",
parameter LINK_CTRL2_TARGET_LINK_SPEED = 4'h2,
parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE",
parameter LL_ACK_TIMEOUT = 15'h0000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter LL_ACK_TIMEOUT_FUNC = 0,
parameter LL_REPLAY_TIMEOUT = 15'h0026,
parameter LL_REPLAY_TIMEOUT_EN = "TRUE",
parameter LL_REPLAY_TIMEOUT_FUNC = 1,
parameter LTSSM_MAX_LINK_WIDTH = 6'h04,
parameter MSI_CAP_MULTIMSGCAP = 0,
parameter MSI_CAP_MULTIMSG_EXTENSION = 0,
parameter MSI_CAP_ON = "TRUE",
parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "FALSE",
parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE",
parameter MSIX_CAP_ON = "FALSE",
parameter MSIX_CAP_PBA_BIR = 0,
parameter MSIX_CAP_PBA_OFFSET = 29'h0,
parameter MSIX_CAP_TABLE_BIR = 0,
parameter MSIX_CAP_TABLE_OFFSET = 29'h0,
parameter MSIX_CAP_TABLE_SIZE = 11'h000,
parameter PCIE_CAP_DEVICE_PORT_TYPE = 4'b0000,
parameter PCIE_CAP_INT_MSG_NUM = 5'h1,
parameter PCIE_CAP_NEXTPTR = 8'h00,
parameter PCIE_DRP_ENABLE = "FALSE",
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter PM_CAP_DSI = "FALSE",
parameter PM_CAP_D1SUPPORT = "FALSE",
parameter PM_CAP_D2SUPPORT = "FALSE",
parameter PM_CAP_NEXTPTR = 8'h48,
parameter PM_CAP_PMESUPPORT = 5'h0F,
parameter PM_CSR_NOSOFTRST = "TRUE",
parameter PM_DATA_SCALE0 = 2'h0,
parameter PM_DATA_SCALE1 = 2'h0,
parameter PM_DATA_SCALE2 = 2'h0,
parameter PM_DATA_SCALE3 = 2'h0,
parameter PM_DATA_SCALE4 = 2'h0,
parameter PM_DATA_SCALE5 = 2'h0,
parameter PM_DATA_SCALE6 = 2'h0,
parameter PM_DATA_SCALE7 = 2'h0,
parameter PM_DATA0 = 8'h00,
parameter PM_DATA1 = 8'h00,
parameter PM_DATA2 = 8'h00,
parameter PM_DATA3 = 8'h00,
parameter PM_DATA4 = 8'h00,
parameter PM_DATA5 = 8'h00,
parameter PM_DATA6 = 8'h00,
parameter PM_DATA7 = 8'h00,
parameter REF_CLK_FREQ = 2, // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
parameter REVISION_ID = 8'h02,
parameter SPARE_BIT0 = 0,
parameter SUBSYSTEM_ID = 16'h0007,
parameter SUBSYSTEM_VENDOR_ID = 16'h10EE,
parameter TL_RX_RAM_RADDR_LATENCY = 0,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 0,
parameter TL_TX_RAM_RADDR_LATENCY = 0,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 0,
parameter UPCONFIG_CAPABLE = "TRUE",
parameter USER_CLK_FREQ = 3,
parameter VC_BASE_PTR = 12'h0,
parameter VC_CAP_NEXTPTR = 12'h000,
parameter VC_CAP_ON = "FALSE",
parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE",
parameter VC0_CPL_INFINITE = "TRUE",
parameter VC0_RX_RAM_LIMIT = 13'h7FF,
parameter VC0_TOTAL_CREDITS_CD = 308,
parameter VC0_TOTAL_CREDITS_CH = 36,
parameter VC0_TOTAL_CREDITS_NPH = 12,
parameter VC0_TOTAL_CREDITS_PD = 308,
parameter VC0_TOTAL_CREDITS_PH = 32,
parameter VC0_TX_LASTPACKET = 29,
parameter VENDOR_ID = 16'h10EE,
parameter VSEC_BASE_PTR = 12'h0,
parameter VSEC_CAP_NEXTPTR = 12'h000,
parameter VSEC_CAP_ON = "FALSE",
parameter AER_BASE_PTR = 12'h128,
parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter AER_CAP_ID = 16'h0001,
parameter AER_CAP_INT_MSG_NUM_MSI = 5'h0a,
parameter AER_CAP_INT_MSG_NUM_MSIX = 5'h15,
parameter AER_CAP_NEXTPTR = 12'h160,
parameter AER_CAP_ON = "FALSE",
parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE",
parameter AER_CAP_VERSION = 4'h1,
parameter CAPABILITIES_PTR = 8'h40,
parameter CRM_MODULE_RSTS = 7'h00,
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE",
parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE",
parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE",
parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE",
parameter DEV_CAP_RSVD_14_12 = 0,
parameter DEV_CAP_RSVD_17_16 = 0,
parameter DEV_CAP_RSVD_31_29 = 0,
parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE",
parameter DISABLE_ASPM_L1_TIMER = "FALSE",
parameter DISABLE_BAR_FILTERING = "FALSE",
parameter DISABLE_ID_CHECK = "FALSE",
parameter DISABLE_RX_TC_FILTER = "FALSE",
parameter DNSTREAM_LINK_NUM = 8'h00,
parameter DSN_CAP_ID = 16'h0003,
parameter DSN_CAP_VERSION = 4'h1,
parameter ENTER_RVRY_EI_L0 = "TRUE",
parameter INFER_EI = 5'h0c,
parameter IS_SWITCH = "FALSE",
parameter LAST_CONFIG_DWORD = 10'h3FF,
parameter LINK_CAP_ASPM_SUPPORT = 1,
parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE",
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter LINK_CAP_RSVD_23_22 = 0,
parameter LINK_CONTROL_RCB = 0,
parameter MSI_BASE_PTR = 8'h48,
parameter MSI_CAP_ID = 8'h05,
parameter MSI_CAP_NEXTPTR = 8'h60,
parameter MSIX_BASE_PTR = 8'h9c,
parameter MSIX_CAP_ID = 8'h11,
parameter MSIX_CAP_NEXTPTR = 8'h00,
parameter N_FTS_COMCLK_GEN1 = 255,
parameter N_FTS_COMCLK_GEN2 = 254,
parameter N_FTS_GEN1 = 255,
parameter N_FTS_GEN2 = 255,
parameter PCIE_BASE_PTR = 8'h60,
parameter PCIE_CAP_CAPABILITY_ID = 8'h10,
parameter PCIE_CAP_CAPABILITY_VERSION = 4'h2,
parameter PCIE_CAP_ON = "TRUE",
parameter PCIE_CAP_RSVD_15_14 = 0,
parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE",
parameter PCIE_REVISION = 2,
parameter PGL0_LANE = 0,
parameter PGL1_LANE = 1,
parameter PGL2_LANE = 2,
parameter PGL3_LANE = 3,
parameter PGL4_LANE = 4,
parameter PGL5_LANE = 5,
parameter PGL6_LANE = 6,
parameter PGL7_LANE = 7,
parameter PL_AUTO_CONFIG = 0,
parameter PL_FAST_TRAIN = "FALSE",
parameter PM_BASE_PTR = 8'h40,
parameter PM_CAP_AUXCURRENT = 0,
parameter PM_CAP_ID = 8'h01,
parameter PM_CAP_ON = "TRUE",
parameter PM_CAP_PME_CLOCK = "FALSE",
parameter PM_CAP_RSVD_04 = 0,
parameter PM_CAP_VERSION = 3,
parameter PM_CSR_BPCCEN = "FALSE",
parameter PM_CSR_B2B3 = "FALSE",
parameter RECRC_CHK = 0,
parameter RECRC_CHK_TRIM = "FALSE",
parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE",
parameter SELECT_DLL_IF = "FALSE",
parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE",
parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE",
parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE",
parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE",
parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE",
parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE",
parameter SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000,
parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE",
parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE",
parameter SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0,
parameter SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00,
parameter SPARE_BIT1 = 0,
parameter SPARE_BIT2 = 0,
parameter SPARE_BIT3 = 0,
parameter SPARE_BIT4 = 0,
parameter SPARE_BIT5 = 0,
parameter SPARE_BIT6 = 0,
parameter SPARE_BIT7 = 0,
parameter SPARE_BIT8 = 0,
parameter SPARE_BYTE0 = 8'h00,
parameter SPARE_BYTE1 = 8'h00,
parameter SPARE_BYTE2 = 8'h00,
parameter SPARE_BYTE3 = 8'h00,
parameter SPARE_WORD0 = 32'h00000000,
parameter SPARE_WORD1 = 32'h00000000,
parameter SPARE_WORD2 = 32'h00000000,
parameter SPARE_WORD3 = 32'h00000000,
parameter TL_RBYPASS = "FALSE",
parameter TL_TFC_DISABLE = "FALSE",
parameter TL_TX_CHECKS_DISABLE = "FALSE",
parameter EXIT_LOOPBACK_ON_EI = "TRUE",
parameter UPSTREAM_FACING = "TRUE",
parameter UR_INV_REQ = "TRUE",
parameter VC_CAP_ID = 16'h0002,
parameter VC_CAP_VERSION = 4'h1,
parameter VSEC_CAP_HDR_ID = 16'h1234,
parameter VSEC_CAP_HDR_LENGTH = 12'h018,
parameter VSEC_CAP_HDR_REVISION = 4'h1,
parameter VSEC_CAP_ID = 16'h000b,
parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE",
parameter VSEC_CAP_VERSION = 4'h1
)
(
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txp,
output [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_txn,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxp,
input [(LINK_CAP_MAX_LINK_WIDTH - 1):0] pci_exp_rxn,
//-------------------------------------------------------
// 2. Transaction (TRN) Interface
//-------------------------------------------------------
// Common
output trn_clk,
output trn_reset_n,
output trn_lnk_up_n,
// Tx
output [5:0] trn_tbuf_av,
output trn_tcfg_req_n,
output trn_terr_drop_n,
output trn_tdst_rdy_n,
input [63:0] trn_td,
input trn_trem_n,
input trn_tsof_n,
input trn_teof_n,
input trn_tsrc_rdy_n,
input trn_tsrc_dsc_n,
input trn_terrfwd_n,
input trn_tcfg_gnt_n,
input trn_tstr_n,
// Rx
output [63:0] trn_rd,
output trn_rrem_n,
output trn_rsof_n,
output trn_reof_n,
output trn_rsrc_rdy_n,
output trn_rsrc_dsc_n,
output trn_rerrfwd_n,
output [6:0] trn_rbar_hit_n,
input trn_rdst_rdy_n,
input trn_rnp_ok_n,
// Flow Control
output [11:0] trn_fc_cpld,
output [7:0] trn_fc_cplh,
output [11:0] trn_fc_npd,
output [7:0] trn_fc_nph,
output [11:0] trn_fc_pd,
output [7:0] trn_fc_ph,
input [2:0] trn_fc_sel,
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
output [31:0] cfg_do,
output cfg_rd_wr_done_n,
input [31:0] cfg_di,
input [3:0] cfg_byte_en_n,
input [9:0] cfg_dwaddr,
input cfg_wr_en_n,
input cfg_rd_en_n,
input cfg_err_cor_n,
input cfg_err_ur_n,
input cfg_err_ecrc_n,
input cfg_err_cpl_timeout_n,
input cfg_err_cpl_abort_n,
input cfg_err_cpl_unexpect_n,
input cfg_err_posted_n,
input cfg_err_locked_n,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy_n,
input cfg_interrupt_n,
output cfg_interrupt_rdy_n,
input cfg_interrupt_assert_n,
input [7:0] cfg_interrupt_di,
output [7:0] cfg_interrupt_do,
output [2:0] cfg_interrupt_mmenable,
output cfg_interrupt_msienable,
output cfg_interrupt_msixenable,
output cfg_interrupt_msixfm,
input cfg_turnoff_ok_n,
output cfg_to_turnoff_n,
input cfg_trn_pending_n,
input cfg_pm_wake_n,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
output [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state_n,
input [63:0] cfg_dsn,
output cfg_pmcsr_pme_en,
output cfg_pmcsr_pme_status,
output [1:0] cfg_pmcsr_powerstate,
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
output [2:0] pl_initial_link_width,
output [1:0] pl_lane_reversal_mode,
output pl_link_gen2_capable,
output pl_link_partner_gen2_supported,
output pl_link_upcfg_capable,
output [5:0] pl_ltssm_state,
output pl_received_hot_rst,
output pl_sel_link_rate,
output [1:0] pl_sel_link_width,
input pl_directed_link_auton,
input [1:0] pl_directed_link_change,
input pl_directed_link_speed,
input [1:0] pl_directed_link_width,
input pl_upstream_prefer_deemph,
//-------------------------------------------------------
// 5. System (SYS) Interface
//-------------------------------------------------------
input sys_clk,
input sys_reset_n
);
wire rx_func_level_reset_n;
wire cfg_msg_received;
wire cfg_msg_received_pme_to;
wire cfg_cmd_bme;
wire cfg_cmd_intdis;
wire cfg_cmd_io_en;
wire cfg_cmd_mem_en;
wire cfg_cmd_serr_en;
wire cfg_dev_control_aux_power_en ;
wire cfg_dev_control_corr_err_reporting_en ;
wire cfg_dev_control_enable_relaxed_order ;
wire cfg_dev_control_ext_tag_en ;
wire cfg_dev_control_fatal_err_reporting_en ;
wire [2:0] cfg_dev_control_maxpayload ;
wire [2:0] cfg_dev_control_max_read_req ;
wire cfg_dev_control_non_fatal_reporting_en ;
wire cfg_dev_control_nosnoop_en ;
wire cfg_dev_control_phantom_en ;
wire cfg_dev_control_ur_err_reporting_en ;
wire cfg_dev_control2_cpltimeout_dis ;
wire [3:0] cfg_dev_control2_cpltimeout_val ;
wire cfg_dev_status_corr_err_detected ;
wire cfg_dev_status_fatal_err_detected ;
wire cfg_dev_status_nonfatal_err_detected ;
wire cfg_dev_status_ur_detected ;
wire cfg_link_control_auto_bandwidth_int_en ;
wire cfg_link_control_bandwidth_int_en ;
wire cfg_link_control_hw_auto_width_dis ;
wire cfg_link_control_clock_pm_en ;
wire cfg_link_control_extended_sync ;
wire cfg_link_control_common_clock ;
wire cfg_link_control_retrain_link ;
wire cfg_link_control_linkdisable ;
wire cfg_link_control_rcb ;
wire [1:0] cfg_link_control_aspm_control ;
wire cfg_link_status_autobandwidth_status ;
wire cfg_link_status_bandwidth_status ;
wire cfg_link_status_dll_active ;
wire cfg_link_status_link_training ;
wire [3:0] cfg_link_status_negotiated_link_width ;
wire [1:0] cfg_link_status_current_speed ;
wire [15:0] cfg_msg_data;
wire sys_reset_n_d;
wire phy_rdy_n;
wire trn_lnk_up_n_int;
wire trn_lnk_up_n_int1;
wire trn_reset_n_int;
wire trn_reset_n_int1;
wire TxOutClk;
wire TxOutClk_bufg;
reg [7:0] cfg_bus_number_d;
reg [4:0] cfg_device_number_d;
reg [2:0] cfg_function_number_d;
// assigns to outputs
assign cfg_to_turnoff_n = ~cfg_msg_received_pme_to;
assign cfg_status = {16'b0};
assign cfg_command = {5'b0,
cfg_cmd_intdis,
1'b0,
cfg_cmd_serr_en,
5'b0,
cfg_cmd_bme,
cfg_cmd_mem_en,
cfg_cmd_io_en};
assign cfg_dstatus = {10'h0,
~cfg_trn_pending_n,
1'b0,
cfg_dev_status_ur_detected,
cfg_dev_status_fatal_err_detected,
cfg_dev_status_nonfatal_err_detected,
cfg_dev_status_corr_err_detected};
assign cfg_dcommand = {1'b0,
cfg_dev_control_max_read_req,
cfg_dev_control_nosnoop_en,
cfg_dev_control_aux_power_en,
cfg_dev_control_phantom_en,
cfg_dev_control_ext_tag_en,
cfg_dev_control_maxpayload,
cfg_dev_control_enable_relaxed_order,
cfg_dev_control_ur_err_reporting_en,
cfg_dev_control_fatal_err_reporting_en,
cfg_dev_control_non_fatal_reporting_en,
cfg_dev_control_corr_err_reporting_en };
assign cfg_lstatus = {cfg_link_status_autobandwidth_status,
cfg_link_status_bandwidth_status,
cfg_link_status_dll_active,
(LINK_STATUS_SLOT_CLOCK_CONFIG == "TRUE") ? 1'b1 : 1'b0,
cfg_link_status_link_training,
1'b0,
{2'b00, cfg_link_status_negotiated_link_width},
{2'b00, cfg_link_status_current_speed} };
assign cfg_lcommand = {cfg_link_control_auto_bandwidth_int_en,
cfg_link_control_bandwidth_int_en,
cfg_link_control_hw_auto_width_dis,
cfg_link_control_clock_pm_en,
cfg_link_control_extended_sync,
cfg_link_control_common_clock,
cfg_link_control_retrain_link,
cfg_link_control_linkdisable,
cfg_link_control_rcb,
1'b0,
cfg_link_control_aspm_control};
assign cfg_bus_number = cfg_bus_number_d;
assign cfg_device_number = cfg_device_number_d;
assign cfg_function_number = cfg_function_number_d;
assign cfg_dcommand2 = {11'b0,
cfg_dev_control2_cpltimeout_dis,
cfg_dev_control2_cpltimeout_val};
// Capture Bus/Device/Function number
always @(posedge trn_clk) begin
if (trn_lnk_up_n) cfg_bus_number_d <= 8'b0;
else if (~cfg_msg_received) cfg_bus_number_d <= cfg_msg_data[15:8];
end
always @(posedge trn_clk) begin
if (trn_lnk_up_n) cfg_device_number_d <= 5'b0;
else if (~cfg_msg_received) cfg_device_number_d <= cfg_msg_data[7:3];
end
always @(posedge trn_clk) begin
if (trn_lnk_up_n) cfg_function_number_d <= 3'b0;
else if (~cfg_msg_received) cfg_function_number_d <= cfg_msg_data[2:0];
end
// Generate trn_lnk_up_n
FDCP #(
.INIT(1'b1)
) trn_lnk_up_n_i (
.Q (trn_lnk_up_n),
.D (trn_lnk_up_n_int1),
.C (trn_clk),
.CLR (1'b0),
.PRE (1'b0)
);
FDCP #(
.INIT(1'b1)
) trn_lnk_up_n_int_i (
.Q (trn_lnk_up_n_int1),
.D (trn_lnk_up_n_int),
.C (trn_clk),
.CLR (1'b0),
.PRE (1'b0)
);
// Generate trn_reset_n
FDCP #(
.INIT(1'b0)
) trn_reset_n_i (
.Q (trn_reset_n),
.D (trn_reset_n_int1 & ~phy_rdy_n),
.C (trn_clk),
.CLR (~sys_reset_n_d),
.PRE (1'b0)
);
FDCP #(
.INIT(1'b0)
) trn_reset_n_int_i (
.Q (trn_reset_n_int1 ),
.D (trn_reset_n_int & ~phy_rdy_n),
.C (trn_clk),
.CLR (~sys_reset_n_d),
.PRE (1'b0)
);
//-------------------------------------------------------
// PCI Express Reset Delay Module
//-------------------------------------------------------
pcie_reset_delay_v6 #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.REF_CLK_FREQ ( REF_CLK_FREQ )
)
pcie_reset_delay_i (
.ref_clk ( TxOutClk_bufg ),
.sys_reset_n ( sys_reset_n ),
.delayed_sys_reset_n ( sys_reset_n_d )
);
//-------------------------------------------------------
// PCI Express Clocking Module
//-------------------------------------------------------
pcie_clocking_v6 #(
.CAP_LINK_WIDTH(LINK_CAP_MAX_LINK_WIDTH),
.CAP_LINK_SPEED(LINK_CAP_MAX_LINK_SPEED),
.REF_CLK_FREQ(REF_CLK_FREQ),
.USER_CLK_FREQ(USER_CLK_FREQ)
)
pcie_clocking_i (
.sys_clk ( TxOutClk ),
.gt_pll_lock ( gt_pll_lock ),
.sel_lnk_rate ( pl_sel_link_rate ),
.sel_lnk_width ( pl_sel_link_width ),
.sys_clk_bufg ( TxOutClk_bufg ),
.pipe_clk ( pipe_clk ),
.user_clk ( user_clk ),
.block_clk ( block_clk ),
.drp_clk ( drp_clk ),
.clock_locked ( clock_locked )
);
//-------------------------------------------------------
// Virtex6 PCI Express Block Module
//-------------------------------------------------------
pcie_2_0_v6 #(
.REF_CLK_FREQ ( REF_CLK_FREQ ),
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES ),
.AER_BASE_PTR ( AER_BASE_PTR ),
.AER_CAP_ECRC_CHECK_CAPABLE ( AER_CAP_ECRC_CHECK_CAPABLE ),
.AER_CAP_ECRC_GEN_CAPABLE ( AER_CAP_ECRC_GEN_CAPABLE ),
.AER_CAP_ID ( AER_CAP_ID ),
.AER_CAP_INT_MSG_NUM_MSI ( AER_CAP_INT_MSG_NUM_MSI ),
.AER_CAP_INT_MSG_NUM_MSIX ( AER_CAP_INT_MSG_NUM_MSIX ),
.AER_CAP_NEXTPTR ( AER_CAP_NEXTPTR ),
.AER_CAP_ON ( AER_CAP_ON ),
.AER_CAP_PERMIT_ROOTERR_UPDATE ( AER_CAP_PERMIT_ROOTERR_UPDATE ),
.AER_CAP_VERSION ( AER_CAP_VERSION ),
.ALLOW_X8_GEN2 ( ALLOW_X8_GEN2 ),
.BAR0 ( BAR0 ),
.BAR1 ( BAR1 ),
.BAR2 ( BAR2 ),
.BAR3 ( BAR3 ),
.BAR4 ( BAR4 ),
.BAR5 ( BAR5 ),
.CAPABILITIES_PTR ( CAPABILITIES_PTR ),
.CARDBUS_CIS_POINTER ( CARDBUS_CIS_POINTER ),
.CLASS_CODE ( CLASS_CODE ),
.CMD_INTX_IMPLEMENTED ( CMD_INTX_IMPLEMENTED ),
.CPL_TIMEOUT_DISABLE_SUPPORTED ( CPL_TIMEOUT_DISABLE_SUPPORTED ),
.CPL_TIMEOUT_RANGES_SUPPORTED ( CPL_TIMEOUT_RANGES_SUPPORTED ),
.CRM_MODULE_RSTS ( CRM_MODULE_RSTS ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE ),
.DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ( DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE ),
.DEV_CAP_ENDPOINT_L0S_LATENCY ( DEV_CAP_ENDPOINT_L0S_LATENCY ),
.DEV_CAP_ENDPOINT_L1_LATENCY ( DEV_CAP_ENDPOINT_L1_LATENCY ),
.DEV_CAP_EXT_TAG_SUPPORTED ( DEV_CAP_EXT_TAG_SUPPORTED ),
.DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED ( DEV_CAP_MAX_PAYLOAD_SUPPORTED ),
.DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ( DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT ),
.DEV_CAP_ROLE_BASED_ERROR ( DEV_CAP_ROLE_BASED_ERROR ),
.DEV_CAP_RSVD_14_12 ( DEV_CAP_RSVD_14_12 ),
.DEV_CAP_RSVD_17_16 ( DEV_CAP_RSVD_17_16 ),
.DEV_CAP_RSVD_31_29 ( DEV_CAP_RSVD_31_29 ),
.DEV_CONTROL_AUX_POWER_SUPPORTED ( DEV_CONTROL_AUX_POWER_SUPPORTED ),
.DEVICE_ID ( DEVICE_ID ),
.DISABLE_ASPM_L1_TIMER ( DISABLE_ASPM_L1_TIMER ),
.DISABLE_BAR_FILTERING ( DISABLE_BAR_FILTERING ),
.DISABLE_ID_CHECK ( DISABLE_ID_CHECK ),
.DISABLE_LANE_REVERSAL ( DISABLE_LANE_REVERSAL ),
.DISABLE_RX_TC_FILTER ( DISABLE_RX_TC_FILTER ),
.DISABLE_SCRAMBLING ( DISABLE_SCRAMBLING ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.DSN_BASE_PTR ( DSN_BASE_PTR ),
.DSN_CAP_ID ( DSN_CAP_ID ),
.DSN_CAP_NEXTPTR ( DSN_CAP_NEXTPTR ),
.DSN_CAP_ON ( DSN_CAP_ON ),
.DSN_CAP_VERSION ( DSN_CAP_VERSION ),
.ENABLE_MSG_ROUTE ( ENABLE_MSG_ROUTE ),
.ENABLE_RX_TD_ECRC_TRIM ( ENABLE_RX_TD_ECRC_TRIM ),
.ENTER_RVRY_EI_L0 ( ENTER_RVRY_EI_L0 ),
.EXPANSION_ROM ( EXPANSION_ROM ),
.EXT_CFG_CAP_PTR ( EXT_CFG_CAP_PTR ),
.EXT_CFG_XP_CAP_PTR ( EXT_CFG_XP_CAP_PTR ),
.HEADER_TYPE ( HEADER_TYPE ),
.INFER_EI ( INFER_EI ),
.INTERRUPT_PIN ( INTERRUPT_PIN ),
.IS_SWITCH ( IS_SWITCH ),
.LAST_CONFIG_DWORD ( LAST_CONFIG_DWORD ),
.LINK_CAP_ASPM_SUPPORT ( LINK_CAP_ASPM_SUPPORT ),
.LINK_CAP_CLOCK_POWER_MANAGEMENT ( LINK_CAP_CLOCK_POWER_MANAGEMENT ),
.LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ( LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP ),
.LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ( LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN1 ( LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.LINK_CAP_L1_EXIT_LATENCY_GEN2 ( LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ),
.LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ),
.LINK_CAP_RSVD_23_22 ( LINK_CAP_RSVD_23_22 ),
.LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ( LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE ),
.LINK_CONTROL_RCB ( LINK_CONTROL_RCB ),
.LINK_CTRL2_DEEMPHASIS ( LINK_CTRL2_DEEMPHASIS ),
.LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ( LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE ),
.LINK_CTRL2_TARGET_LINK_SPEED ( LINK_CTRL2_TARGET_LINK_SPEED ),
.LINK_STATUS_SLOT_CLOCK_CONFIG ( LINK_STATUS_SLOT_CLOCK_CONFIG ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTSSM_MAX_LINK_WIDTH ( LTSSM_MAX_LINK_WIDTH ),
.MSI_BASE_PTR ( MSI_BASE_PTR ),
.MSI_CAP_ID ( MSI_CAP_ID ),
.MSI_CAP_MULTIMSGCAP ( MSI_CAP_MULTIMSGCAP ),
.MSI_CAP_MULTIMSG_EXTENSION ( MSI_CAP_MULTIMSG_EXTENSION ),
.MSI_CAP_NEXTPTR ( MSI_CAP_NEXTPTR ),
.MSI_CAP_ON ( MSI_CAP_ON ),
.MSI_CAP_PER_VECTOR_MASKING_CAPABLE ( MSI_CAP_PER_VECTOR_MASKING_CAPABLE ),
.MSI_CAP_64_BIT_ADDR_CAPABLE ( MSI_CAP_64_BIT_ADDR_CAPABLE ),
.MSIX_BASE_PTR ( MSIX_BASE_PTR ),
.MSIX_CAP_ID ( MSIX_CAP_ID ),
.MSIX_CAP_NEXTPTR ( MSIX_CAP_NEXTPTR ),
.MSIX_CAP_ON ( MSIX_CAP_ON ),
.MSIX_CAP_PBA_BIR ( MSIX_CAP_PBA_BIR ),
.MSIX_CAP_PBA_OFFSET ( MSIX_CAP_PBA_OFFSET ),
.MSIX_CAP_TABLE_BIR ( MSIX_CAP_TABLE_BIR ),
.MSIX_CAP_TABLE_OFFSET ( MSIX_CAP_TABLE_OFFSET ),
.MSIX_CAP_TABLE_SIZE ( MSIX_CAP_TABLE_SIZE ),
.N_FTS_COMCLK_GEN1 ( N_FTS_COMCLK_GEN1 ),
.N_FTS_COMCLK_GEN2 ( N_FTS_COMCLK_GEN2 ),
.N_FTS_GEN1 ( N_FTS_GEN1 ),
.N_FTS_GEN2 ( N_FTS_GEN2 ),
.PCIE_BASE_PTR ( PCIE_BASE_PTR ),
.PCIE_CAP_CAPABILITY_ID ( PCIE_CAP_CAPABILITY_ID ),
.PCIE_CAP_CAPABILITY_VERSION ( PCIE_CAP_CAPABILITY_VERSION ),
.PCIE_CAP_DEVICE_PORT_TYPE ( PCIE_CAP_DEVICE_PORT_TYPE ),
.PCIE_CAP_INT_MSG_NUM ( PCIE_CAP_INT_MSG_NUM ),
.PCIE_CAP_NEXTPTR ( PCIE_CAP_NEXTPTR ),
.PCIE_CAP_ON ( PCIE_CAP_ON ),
.PCIE_CAP_RSVD_15_14 ( PCIE_CAP_RSVD_15_14 ),
.PCIE_CAP_SLOT_IMPLEMENTED ( PCIE_CAP_SLOT_IMPLEMENTED ),
.PCIE_REVISION ( PCIE_REVISION ),
.PGL0_LANE ( PGL0_LANE ),
.PGL1_LANE ( PGL1_LANE ),
.PGL2_LANE ( PGL2_LANE ),
.PGL3_LANE ( PGL3_LANE ),
.PGL4_LANE ( PGL4_LANE ),
.PGL5_LANE ( PGL5_LANE ),
.PGL6_LANE ( PGL6_LANE ),
.PGL7_LANE ( PGL7_LANE ),
.PL_AUTO_CONFIG ( PL_AUTO_CONFIG ),
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PM_BASE_PTR ( PM_BASE_PTR ),
.PM_CAP_AUXCURRENT ( PM_CAP_AUXCURRENT ),
.PM_CAP_DSI ( PM_CAP_DSI ),
.PM_CAP_D1SUPPORT ( PM_CAP_D1SUPPORT ),
.PM_CAP_D2SUPPORT ( PM_CAP_D2SUPPORT ),
.PM_CAP_ID ( PM_CAP_ID ),
.PM_CAP_NEXTPTR ( PM_CAP_NEXTPTR ),
.PM_CAP_ON ( PM_CAP_ON ),
.PM_CAP_PME_CLOCK ( PM_CAP_PME_CLOCK ),
.PM_CAP_PMESUPPORT ( PM_CAP_PMESUPPORT ),
.PM_CAP_RSVD_04 ( PM_CAP_RSVD_04 ),
.PM_CAP_VERSION ( PM_CAP_VERSION ),
.PM_CSR_BPCCEN ( PM_CSR_BPCCEN ),
.PM_CSR_B2B3 ( PM_CSR_B2B3 ),
.PM_CSR_NOSOFTRST ( PM_CSR_NOSOFTRST ),
.PM_DATA_SCALE0 ( PM_DATA_SCALE0 ),
.PM_DATA_SCALE1 ( PM_DATA_SCALE1 ),
.PM_DATA_SCALE2 ( PM_DATA_SCALE2 ),
.PM_DATA_SCALE3 ( PM_DATA_SCALE3 ),
.PM_DATA_SCALE4 ( PM_DATA_SCALE4 ),
.PM_DATA_SCALE5 ( PM_DATA_SCALE5 ),
.PM_DATA_SCALE6 ( PM_DATA_SCALE6 ),
.PM_DATA_SCALE7 ( PM_DATA_SCALE7 ),
.PM_DATA0 ( PM_DATA0 ),
.PM_DATA1 ( PM_DATA1 ),
.PM_DATA2 ( PM_DATA2 ),
.PM_DATA3 ( PM_DATA3 ),
.PM_DATA4 ( PM_DATA4 ),
.PM_DATA5 ( PM_DATA5 ),
.PM_DATA6 ( PM_DATA6 ),
.PM_DATA7 ( PM_DATA7 ),
.RECRC_CHK ( RECRC_CHK ),
.RECRC_CHK_TRIM ( RECRC_CHK_TRIM ),
.REVISION_ID ( REVISION_ID ),
.ROOT_CAP_CRS_SW_VISIBILITY ( ROOT_CAP_CRS_SW_VISIBILITY ),
.SELECT_DLL_IF ( SELECT_DLL_IF ),
.SLOT_CAP_ATT_BUTTON_PRESENT ( SLOT_CAP_ATT_BUTTON_PRESENT ),
.SLOT_CAP_ATT_INDICATOR_PRESENT ( SLOT_CAP_ATT_INDICATOR_PRESENT ),
.SLOT_CAP_ELEC_INTERLOCK_PRESENT ( SLOT_CAP_ELEC_INTERLOCK_PRESENT ),
.SLOT_CAP_HOTPLUG_CAPABLE ( SLOT_CAP_HOTPLUG_CAPABLE ),
.SLOT_CAP_HOTPLUG_SURPRISE ( SLOT_CAP_HOTPLUG_SURPRISE ),
.SLOT_CAP_MRL_SENSOR_PRESENT ( SLOT_CAP_MRL_SENSOR_PRESENT ),
.SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ( SLOT_CAP_NO_CMD_COMPLETED_SUPPORT ),
.SLOT_CAP_PHYSICAL_SLOT_NUM ( SLOT_CAP_PHYSICAL_SLOT_NUM ),
.SLOT_CAP_POWER_CONTROLLER_PRESENT ( SLOT_CAP_POWER_CONTROLLER_PRESENT ),
.SLOT_CAP_POWER_INDICATOR_PRESENT ( SLOT_CAP_POWER_INDICATOR_PRESENT ),
.SLOT_CAP_SLOT_POWER_LIMIT_SCALE ( SLOT_CAP_SLOT_POWER_LIMIT_SCALE ),
.SLOT_CAP_SLOT_POWER_LIMIT_VALUE ( SLOT_CAP_SLOT_POWER_LIMIT_VALUE ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SUBSYSTEM_ID ( SUBSYSTEM_ID ),
.SUBSYSTEM_VENDOR_ID ( SUBSYSTEM_VENDOR_ID ),
.TL_RBYPASS ( TL_RBYPASS ),
.TL_RX_RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ),
.TL_RX_RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ),
.TL_RX_RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ),
.TL_TFC_DISABLE ( TL_TFC_DISABLE ),
.TL_TX_CHECKS_DISABLE ( TL_TX_CHECKS_DISABLE ),
.TL_TX_RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ),
.TL_TX_RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ),
.TL_TX_RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ),
.UPCONFIG_CAPABLE ( UPCONFIG_CAPABLE ),
.UPSTREAM_FACING ( UPSTREAM_FACING ),
.EXIT_LOOPBACK_ON_EI ( EXIT_LOOPBACK_ON_EI ),
.UR_INV_REQ ( UR_INV_REQ ),
.USER_CLK_FREQ ( USER_CLK_FREQ ),
.VC_BASE_PTR ( VC_BASE_PTR ),
.VC_CAP_ID ( VC_CAP_ID ),
.VC_CAP_NEXTPTR ( VC_CAP_NEXTPTR ),
.VC_CAP_ON ( VC_CAP_ON ),
.VC_CAP_REJECT_SNOOP_TRANSACTIONS ( VC_CAP_REJECT_SNOOP_TRANSACTIONS ),
.VC_CAP_VERSION ( VC_CAP_VERSION ),
.VC0_CPL_INFINITE ( VC0_CPL_INFINITE ),
.VC0_RX_RAM_LIMIT ( VC0_RX_RAM_LIMIT ),
.VC0_TOTAL_CREDITS_CD ( VC0_TOTAL_CREDITS_CD ),
.VC0_TOTAL_CREDITS_CH ( VC0_TOTAL_CREDITS_CH ),
.VC0_TOTAL_CREDITS_NPH ( VC0_TOTAL_CREDITS_NPH ),
.VC0_TOTAL_CREDITS_PD ( VC0_TOTAL_CREDITS_PD ),
.VC0_TOTAL_CREDITS_PH ( VC0_TOTAL_CREDITS_PH ),
.VC0_TX_LASTPACKET ( VC0_TX_LASTPACKET ),
.VENDOR_ID ( VENDOR_ID ),
.VSEC_BASE_PTR ( VSEC_BASE_PTR ),
.VSEC_CAP_HDR_ID ( VSEC_CAP_HDR_ID ),
.VSEC_CAP_HDR_LENGTH ( VSEC_CAP_HDR_LENGTH ),
.VSEC_CAP_HDR_REVISION ( VSEC_CAP_HDR_REVISION ),
.VSEC_CAP_ID ( VSEC_CAP_ID ),
.VSEC_CAP_IS_LINK_VISIBLE ( VSEC_CAP_IS_LINK_VISIBLE ),
.VSEC_CAP_NEXTPTR ( VSEC_CAP_NEXTPTR ),
.VSEC_CAP_ON ( VSEC_CAP_ON ),
.VSEC_CAP_VERSION ( VSEC_CAP_VERSION )
)
pcie_2_0_i (
.PCIEXPRXN( pci_exp_rxn ),
.PCIEXPRXP( pci_exp_rxp ),
.PCIEXPTXN( pci_exp_txn ),
.PCIEXPTXP( pci_exp_txp ),
.SYSCLK( sys_clk ),
.TRNLNKUPN( trn_lnk_up_n_int ),
.TRNCLK( trn_clk ),
.FUNDRSTN (sys_reset_n_d),
.PHYRDYN( phy_rdy_n ),
.LNKCLKEN ( ),
.USERRSTN( trn_reset_n_int ),
.RECEIVEDFUNCLVLRSTN( rx_func_level_reset_n ),
.SYSRSTN( ~phy_rdy_n ),
.PLRSTN( 1'b1 ),
.DLRSTN( 1'b1 ),
.TLRSTN( 1'b1 ),
.FUNCLVLRSTN( 1'b1 ),
.CMRSTN( 1'b1 ),
.CMSTICKYRSTN( 1'b1 ),
.TRNRBARHITN( trn_rbar_hit_n ),
.TRNRD( trn_rd ),
.TRNRECRCERRN( ),
.TRNREOFN( trn_reof_n ),
.TRNRERRFWDN( trn_rerrfwd_n ),
.TRNRREMN( trn_rrem_n ),
.TRNRSOFN( trn_rsof_n ),
.TRNRSRCDSCN( trn_rsrc_dsc_n ),
.TRNRSRCRDYN( trn_rsrc_rdy_n ),
.TRNRDSTRDYN( trn_rdst_rdy_n ),
.TRNRNPOKN( trn_rnp_ok_n ),
.TRNTBUFAV( trn_tbuf_av ),
.TRNTCFGREQN( trn_tcfg_req_n ),
.TRNTDLLPDSTRDYN( ),
.TRNTDSTRDYN( trn_tdst_rdy_n ),
.TRNTERRDROPN( trn_terr_drop_n ),
.TRNTCFGGNTN( trn_tcfg_gnt_n ),
.TRNTD( trn_td ),
.TRNTDLLPDATA( 32'b0 ),
.TRNTDLLPSRCRDYN( 1'b1 ),
.TRNTECRCGENN( 1'b1 ),
.TRNTEOFN( trn_teof_n ),
.TRNTERRFWDN( trn_terrfwd_n ),
.TRNTREMN( trn_trem_n ),
.TRNTSOFN( trn_tsof_n ),
.TRNTSRCDSCN( trn_tsrc_dsc_n ),
.TRNTSRCRDYN( trn_tsrc_rdy_n ),
.TRNTSTRN( trn_tstr_n ),
.TRNFCCPLD( trn_fc_cpld ),
.TRNFCCPLH( trn_fc_cplh ),
.TRNFCNPD( trn_fc_npd ),
.TRNFCNPH( trn_fc_nph ),
.TRNFCPD( trn_fc_pd ),
.TRNFCPH( trn_fc_ph ),
.TRNFCSEL( trn_fc_sel ),
.CFGAERECRCCHECKEN(),
.CFGAERECRCGENEN(),
.CFGCOMMANDBUSMASTERENABLE( cfg_cmd_bme ),
.CFGCOMMANDINTERRUPTDISABLE( cfg_cmd_intdis ),
.CFGCOMMANDIOENABLE( cfg_cmd_io_en ),
.CFGCOMMANDMEMENABLE( cfg_cmd_mem_en ),
.CFGCOMMANDSERREN( cfg_cmd_serr_en ),
.CFGDEVCONTROLAUXPOWEREN( cfg_dev_control_aux_power_en ),
.CFGDEVCONTROLCORRERRREPORTINGEN( cfg_dev_control_corr_err_reporting_en ),
.CFGDEVCONTROLENABLERO( cfg_dev_control_enable_relaxed_order ),
.CFGDEVCONTROLEXTTAGEN( cfg_dev_control_ext_tag_en ),
.CFGDEVCONTROLFATALERRREPORTINGEN( cfg_dev_control_fatal_err_reporting_en ),
.CFGDEVCONTROLMAXPAYLOAD( cfg_dev_control_maxpayload ),
.CFGDEVCONTROLMAXREADREQ( cfg_dev_control_max_read_req ),
.CFGDEVCONTROLNONFATALREPORTINGEN( cfg_dev_control_non_fatal_reporting_en ),
.CFGDEVCONTROLNOSNOOPEN( cfg_dev_control_nosnoop_en ),
.CFGDEVCONTROLPHANTOMEN( cfg_dev_control_phantom_en ),
.CFGDEVCONTROLURERRREPORTINGEN( cfg_dev_control_ur_err_reporting_en ),
.CFGDEVCONTROL2CPLTIMEOUTDIS( cfg_dev_control2_cpltimeout_dis ),
.CFGDEVCONTROL2CPLTIMEOUTVAL( cfg_dev_control2_cpltimeout_val ),
.CFGDEVSTATUSCORRERRDETECTED( cfg_dev_status_corr_err_detected ),
.CFGDEVSTATUSFATALERRDETECTED( cfg_dev_status_fatal_err_detected ),
.CFGDEVSTATUSNONFATALERRDETECTED( cfg_dev_status_nonfatal_err_detected ),
.CFGDEVSTATUSURDETECTED( cfg_dev_status_ur_detected ),
.CFGDO( cfg_do ),
.CFGERRAERHEADERLOGSETN(),
.CFGERRCPLRDYN( cfg_err_cpl_rdy_n ),
.CFGINTERRUPTDO( cfg_interrupt_do ),
.CFGINTERRUPTMMENABLE( cfg_interrupt_mmenable ),
.CFGINTERRUPTMSIENABLE( cfg_interrupt_msienable ),
.CFGINTERRUPTMSIXENABLE( cfg_interrupt_msixenable ),
.CFGINTERRUPTMSIXFM( cfg_interrupt_msixfm ),
.CFGINTERRUPTRDYN( cfg_interrupt_rdy_n ),
.CFGLINKCONTROLRCB( cfg_link_control_rcb ),
.CFGLINKCONTROLASPMCONTROL( cfg_link_control_aspm_control ),
.CFGLINKCONTROLAUTOBANDWIDTHINTEN( cfg_link_control_auto_bandwidth_int_en ),
.CFGLINKCONTROLBANDWIDTHINTEN( cfg_link_control_bandwidth_int_en ),
.CFGLINKCONTROLCLOCKPMEN( cfg_link_control_clock_pm_en ),
.CFGLINKCONTROLCOMMONCLOCK( cfg_link_control_common_clock ),
.CFGLINKCONTROLEXTENDEDSYNC( cfg_link_control_extended_sync ),
.CFGLINKCONTROLHWAUTOWIDTHDIS( cfg_link_control_hw_auto_width_dis ),
.CFGLINKCONTROLLINKDISABLE( cfg_link_control_linkdisable ),
.CFGLINKCONTROLRETRAINLINK( cfg_link_control_retrain_link ),
.CFGLINKSTATUSAUTOBANDWIDTHSTATUS( cfg_link_status_autobandwidth_status ),
.CFGLINKSTATUSBANDWITHSTATUS( cfg_link_status_bandwidth_status ),
.CFGLINKSTATUSCURRENTSPEED( cfg_link_status_current_speed ),
.CFGLINKSTATUSDLLACTIVE( cfg_link_status_dll_active ),
.CFGLINKSTATUSLINKTRAINING( cfg_link_status_link_training ),
.CFGLINKSTATUSNEGOTIATEDWIDTH( cfg_link_status_negotiated_link_width ),
.CFGMSGDATA( cfg_msg_data ),
.CFGMSGRECEIVED( cfg_msg_received ),
.CFGMSGRECEIVEDASSERTINTA(),
.CFGMSGRECEIVEDASSERTINTB(),
.CFGMSGRECEIVEDASSERTINTC(),
.CFGMSGRECEIVEDASSERTINTD(),
.CFGMSGRECEIVEDDEASSERTINTA(),
.CFGMSGRECEIVEDDEASSERTINTB(),
.CFGMSGRECEIVEDDEASSERTINTC(),
.CFGMSGRECEIVEDDEASSERTINTD(),
.CFGMSGRECEIVEDERRCOR(),
.CFGMSGRECEIVEDERRFATAL(),
.CFGMSGRECEIVEDERRNONFATAL(),
.CFGMSGRECEIVEDPMASNAK(),
.CFGMSGRECEIVEDPMETO( cfg_msg_received_pme_to ),
.CFGMSGRECEIVEDPMETOACK(),
.CFGMSGRECEIVEDPMPME(),
.CFGMSGRECEIVEDSETSLOTPOWERLIMIT(),
.CFGMSGRECEIVEDUNLOCK(),
.CFGPCIELINKSTATE( cfg_pcie_link_state_n ),
.CFGPMCSRPMEEN ( cfg_pmcsr_pme_en ),
.CFGPMCSRPMESTATUS ( cfg_pmcsr_pme_status ),
.CFGPMCSRPOWERSTATE ( cfg_pmcsr_powerstate ),
.CFGPMRCVASREQL1N(),
.CFGPMRCVENTERL1N(),
.CFGPMRCVENTERL23N(),
.CFGPMRCVREQACKN(),
.CFGRDWRDONEN( cfg_rd_wr_done_n ),
.CFGSLOTCONTROLELECTROMECHILCTLPULSE(),
.CFGTRANSACTION(),
.CFGTRANSACTIONADDR(),
.CFGTRANSACTIONTYPE(),
.CFGVCTCVCMAP(),
.CFGBYTEENN( cfg_byte_en_n ),
.CFGDI( cfg_di ),
.CFGDSBUSNUMBER( 8'b0 ),
.CFGDSDEVICENUMBER( 5'b0 ),
.CFGDSFUNCTIONNUMBER( 3'b0 ),
.CFGDSN( cfg_dsn ),
.CFGDWADDR( cfg_dwaddr ),
.CFGERRACSN( 1'b1 ),
.CFGERRAERHEADERLOG( 128'h0 ),
.CFGERRCORN( cfg_err_cor_n ),
.CFGERRCPLABORTN( cfg_err_cpl_abort_n ),
.CFGERRCPLTIMEOUTN( cfg_err_cpl_timeout_n ),
.CFGERRCPLUNEXPECTN( cfg_err_cpl_unexpect_n ),
.CFGERRECRCN( cfg_err_ecrc_n ),
.CFGERRLOCKEDN( cfg_err_locked_n ),
.CFGERRPOSTEDN( cfg_err_posted_n ),
.CFGERRTLPCPLHEADER( cfg_err_tlp_cpl_header ),
.CFGERRURN( cfg_err_ur_n ),
.CFGINTERRUPTASSERTN( cfg_interrupt_assert_n ),
.CFGINTERRUPTDI( cfg_interrupt_di ),
.CFGINTERRUPTN( cfg_interrupt_n ),
.CFGPMDIRECTASPML1N( 1'b1 ),
.CFGPMSENDPMACKN( 1'b1 ),
.CFGPMSENDPMETON( 1'b1 ),
.CFGPMSENDPMNAKN( 1'b1 ),
.CFGPMTURNOFFOKN( cfg_turnoff_ok_n ),
.CFGPMWAKEN( cfg_pm_wake_n ),
.CFGPORTNUMBER( 8'h0 ),
.CFGRDENN( cfg_rd_en_n ),
.CFGTRNPENDINGN( cfg_trn_pending_n ),
.CFGWRENN( cfg_wr_en_n ),
.CFGWRREADONLYN( 1'b1 ),
.CFGWRRW1CASRWN( 1'b1 ),
.PLINITIALLINKWIDTH( pl_initial_link_width ),
.PLLANEREVERSALMODE( pl_lane_reversal_mode ),
.PLLINKGEN2CAP( pl_link_gen2_capable ),
.PLLINKPARTNERGEN2SUPPORTED( pl_link_partner_gen2_supported ),
.PLLINKUPCFGCAP( pl_link_upcfg_capable ),
.PLLTSSMSTATE( pl_ltssm_state ),
.PLPHYLNKUPN( ), // Debug
.PLRECEIVEDHOTRST( pl_received_hot_rst ),
.PLRXPMSTATE(), // Debug
.PLSELLNKRATE( pl_sel_link_rate ),
.PLSELLNKWIDTH( pl_sel_link_width ),
.PLTXPMSTATE(), // Debug
.PLDIRECTEDLINKAUTON( pl_directed_link_auton ),
.PLDIRECTEDLINKCHANGE( pl_directed_link_change ),
.PLDIRECTEDLINKSPEED( pl_directed_link_speed ),
.PLDIRECTEDLINKWIDTH( pl_directed_link_width ),
.PLDOWNSTREAMDEEMPHSOURCE( 1'b1 ),
.PLUPSTREAMPREFERDEEMPH( pl_upstream_prefer_deemph ),
.PLTRANSMITHOTRST( 1'b0 ),
.DBGSCLRA(),
.DBGSCLRB(),
.DBGSCLRC(),
.DBGSCLRD(),
.DBGSCLRE(),
.DBGSCLRF(),
.DBGSCLRG(),
.DBGSCLRH(),
.DBGSCLRI(),
.DBGSCLRJ(),
.DBGSCLRK(),
.DBGVECA(),
.DBGVECB(),
.DBGVECC(),
.PLDBGVEC(),
.DBGMODE( 2'b0 ),
.DBGSUBMODE( 1'b0 ),
.PLDBGMODE( 3'b0 ),
.PCIEDRPDO(),
.PCIEDRPDRDY(),
.PCIEDRPCLK(1'b0),
.PCIEDRPDADDR(9'b0),
.PCIEDRPDEN(1'b0),
.PCIEDRPDI(16'b0),
.PCIEDRPDWE(1'b0),
.GTPLLLOCK( gt_pll_lock ),
.PIPECLK( pipe_clk ),
.USERCLK( user_clk ),
.DRPCLK(drp_clk),
.CLOCKLOCKED( clock_locked ),
.TxOutClk(TxOutClk)
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:00:38 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_1/zqynq_lab_1_design_axi_timer_0_1_sim_netlist.v
// Design : zqynq_lab_1_design_axi_timer_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_timer_0_1,axi_timer,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_timer,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_axi_timer_0_1
(capturetrig0,
capturetrig1,
generateout0,
generateout1,
pwm0,
interrupt,
freeze,
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready);
input capturetrig0;
input capturetrig1;
output generateout0;
output generateout1;
output pwm0;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT" *) output interrupt;
input freeze;
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_RST RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [4:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [4:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
wire capturetrig0;
wire capturetrig1;
wire freeze;
wire generateout0;
wire generateout1;
wire interrupt;
wire pwm0;
wire s_axi_aclk;
wire [4:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [4:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
(* C_COUNT_WIDTH = "32" *)
(* C_FAMILY = "zynq" *)
(* C_GEN0_ASSERT = "1'b1" *)
(* C_GEN1_ASSERT = "1'b1" *)
(* C_ONE_TIMER_ONLY = "0" *)
(* C_S_AXI_ADDR_WIDTH = "5" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRIG0_ASSERT = "1'b1" *)
(* C_TRIG1_ASSERT = "1'b1" *)
(* downgradeipidentifiedwarnings = "yes" *)
zqynq_lab_1_design_axi_timer_0_1_axi_timer U0
(.capturetrig0(capturetrig0),
.capturetrig1(capturetrig1),
.freeze(freeze),
.generateout0(generateout0),
.generateout1(generateout1),
.interrupt(interrupt),
.pwm0(pwm0),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module zqynq_lab_1_design_axi_timer_0_1_address_decoder
(\LOAD_REG_GEN[31].LOAD_REG_I ,
\TCSR0_GENERATE[23].TCSR0_FF_I ,
\s_axi_rdata_i_reg[12] ,
\s_axi_rdata_i_reg[13] ,
\s_axi_rdata_i_reg[14] ,
\s_axi_rdata_i_reg[15] ,
\s_axi_rdata_i_reg[16] ,
\s_axi_rdata_i_reg[17] ,
\s_axi_rdata_i_reg[18] ,
\s_axi_rdata_i_reg[19] ,
\s_axi_rdata_i_reg[20] ,
\s_axi_rdata_i_reg[21] ,
\s_axi_rdata_i_reg[22] ,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[24] ,
\s_axi_rdata_i_reg[25] ,
\s_axi_rdata_i_reg[26] ,
\s_axi_rdata_i_reg[27] ,
\s_axi_rdata_i_reg[28] ,
\s_axi_rdata_i_reg[29] ,
\s_axi_rdata_i_reg[30] ,
\s_axi_rdata_i_reg[31] ,
pair0_Select,
s_axi_wready,
s_axi_arready,
D,
\s_axi_rdata_i_reg[11] ,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
\LOAD_REG_GEN[31].LOAD_REG_I_0 ,
\LOAD_REG_GEN[30].LOAD_REG_I ,
\LOAD_REG_GEN[29].LOAD_REG_I ,
\LOAD_REG_GEN[28].LOAD_REG_I ,
\LOAD_REG_GEN[27].LOAD_REG_I ,
\LOAD_REG_GEN[26].LOAD_REG_I ,
\LOAD_REG_GEN[25].LOAD_REG_I ,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\LOAD_REG_GEN[23].LOAD_REG_I ,
\LOAD_REG_GEN[22].LOAD_REG_I ,
\LOAD_REG_GEN[21].LOAD_REG_I ,
\LOAD_REG_GEN[20].LOAD_REG_I ,
\LOAD_REG_GEN[19].LOAD_REG_I ,
\LOAD_REG_GEN[18].LOAD_REG_I ,
\LOAD_REG_GEN[17].LOAD_REG_I ,
\LOAD_REG_GEN[16].LOAD_REG_I ,
\LOAD_REG_GEN[15].LOAD_REG_I ,
\LOAD_REG_GEN[14].LOAD_REG_I ,
\LOAD_REG_GEN[13].LOAD_REG_I ,
\LOAD_REG_GEN[12].LOAD_REG_I ,
\LOAD_REG_GEN[11].LOAD_REG_I ,
\LOAD_REG_GEN[10].LOAD_REG_I ,
\LOAD_REG_GEN[9].LOAD_REG_I ,
\LOAD_REG_GEN[8].LOAD_REG_I ,
\LOAD_REG_GEN[7].LOAD_REG_I ,
\LOAD_REG_GEN[6].LOAD_REG_I ,
\LOAD_REG_GEN[5].LOAD_REG_I ,
\LOAD_REG_GEN[4].LOAD_REG_I ,
\LOAD_REG_GEN[3].LOAD_REG_I ,
\LOAD_REG_GEN[2].LOAD_REG_I ,
\LOAD_REG_GEN[1].LOAD_REG_I ,
D_0,
bus2ip_wrce__0,
bus2ip_wrce,
\LOAD_REG_GEN[31].LOAD_REG_I_1 ,
\LOAD_REG_GEN[30].LOAD_REG_I_0 ,
\LOAD_REG_GEN[29].LOAD_REG_I_0 ,
\LOAD_REG_GEN[28].LOAD_REG_I_0 ,
\LOAD_REG_GEN[27].LOAD_REG_I_0 ,
\LOAD_REG_GEN[26].LOAD_REG_I_0 ,
\LOAD_REG_GEN[25].LOAD_REG_I_0 ,
\LOAD_REG_GEN[24].LOAD_REG_I_0 ,
\LOAD_REG_GEN[23].LOAD_REG_I_0 ,
\LOAD_REG_GEN[22].LOAD_REG_I_0 ,
\LOAD_REG_GEN[21].LOAD_REG_I_0 ,
\LOAD_REG_GEN[20].LOAD_REG_I_0 ,
\LOAD_REG_GEN[19].LOAD_REG_I_0 ,
\LOAD_REG_GEN[18].LOAD_REG_I_0 ,
\LOAD_REG_GEN[17].LOAD_REG_I_0 ,
\LOAD_REG_GEN[16].LOAD_REG_I_0 ,
\LOAD_REG_GEN[15].LOAD_REG_I_0 ,
\LOAD_REG_GEN[14].LOAD_REG_I_0 ,
\LOAD_REG_GEN[13].LOAD_REG_I_0 ,
\LOAD_REG_GEN[12].LOAD_REG_I_0 ,
\LOAD_REG_GEN[11].LOAD_REG_I_0 ,
\LOAD_REG_GEN[10].LOAD_REG_I_0 ,
\LOAD_REG_GEN[9].LOAD_REG_I_0 ,
\LOAD_REG_GEN[8].LOAD_REG_I_0 ,
\LOAD_REG_GEN[7].LOAD_REG_I_0 ,
\LOAD_REG_GEN[6].LOAD_REG_I_0 ,
\LOAD_REG_GEN[5].LOAD_REG_I_0 ,
\LOAD_REG_GEN[4].LOAD_REG_I_0 ,
\LOAD_REG_GEN[3].LOAD_REG_I_0 ,
\LOAD_REG_GEN[2].LOAD_REG_I_0 ,
\LOAD_REG_GEN[1].LOAD_REG_I_0 ,
D_1,
s_axi_rvalid_i_reg,
s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_1,
s_axi_rvalid_i_reg_2,
s_axi_bvalid_i_reg,
\TCSR0_GENERATE[23].TCSR0_FF_I_0 ,
\TCSR1_GENERATE[23].TCSR1_FF_I ,
\s_axi_rdata_i_reg[10] ,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[0]_0 ,
READ_DONE0_I,
READ_DONE1_I,
Q,
s_axi_aclk,
read_Mux_In,
s_axi_aresetn,
state1__2,
s_axi_arvalid_0,
\state_reg[1] ,
s_axi_wdata,
s_axi_arvalid,
is_write_reg,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] ,
s_axi_rready,
s_axi_rvalid_i_reg_3,
s_axi_bready,
s_axi_bvalid_i_reg_0,
bus2ip_rnw_i,
D_2,
read_done1,
\bus2ip_addr_i_reg[4] );
output \LOAD_REG_GEN[31].LOAD_REG_I ;
output \TCSR0_GENERATE[23].TCSR0_FF_I ;
output \s_axi_rdata_i_reg[12] ;
output \s_axi_rdata_i_reg[13] ;
output \s_axi_rdata_i_reg[14] ;
output \s_axi_rdata_i_reg[15] ;
output \s_axi_rdata_i_reg[16] ;
output \s_axi_rdata_i_reg[17] ;
output \s_axi_rdata_i_reg[18] ;
output \s_axi_rdata_i_reg[19] ;
output \s_axi_rdata_i_reg[20] ;
output \s_axi_rdata_i_reg[21] ;
output \s_axi_rdata_i_reg[22] ;
output \s_axi_rdata_i_reg[23] ;
output \s_axi_rdata_i_reg[24] ;
output \s_axi_rdata_i_reg[25] ;
output \s_axi_rdata_i_reg[26] ;
output \s_axi_rdata_i_reg[27] ;
output \s_axi_rdata_i_reg[28] ;
output \s_axi_rdata_i_reg[29] ;
output \s_axi_rdata_i_reg[30] ;
output \s_axi_rdata_i_reg[31] ;
output pair0_Select;
output s_axi_wready;
output s_axi_arready;
output [1:0]D;
output \s_axi_rdata_i_reg[11] ;
output \TCSR0_GENERATE[24].TCSR0_FF_I ;
output \TCSR1_GENERATE[24].TCSR1_FF_I ;
output \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[30].LOAD_REG_I ;
output \LOAD_REG_GEN[29].LOAD_REG_I ;
output \LOAD_REG_GEN[28].LOAD_REG_I ;
output \LOAD_REG_GEN[27].LOAD_REG_I ;
output \LOAD_REG_GEN[26].LOAD_REG_I ;
output \LOAD_REG_GEN[25].LOAD_REG_I ;
output \LOAD_REG_GEN[24].LOAD_REG_I ;
output \LOAD_REG_GEN[23].LOAD_REG_I ;
output \LOAD_REG_GEN[22].LOAD_REG_I ;
output \LOAD_REG_GEN[21].LOAD_REG_I ;
output \LOAD_REG_GEN[20].LOAD_REG_I ;
output \LOAD_REG_GEN[19].LOAD_REG_I ;
output \LOAD_REG_GEN[18].LOAD_REG_I ;
output \LOAD_REG_GEN[17].LOAD_REG_I ;
output \LOAD_REG_GEN[16].LOAD_REG_I ;
output \LOAD_REG_GEN[15].LOAD_REG_I ;
output \LOAD_REG_GEN[14].LOAD_REG_I ;
output \LOAD_REG_GEN[13].LOAD_REG_I ;
output \LOAD_REG_GEN[12].LOAD_REG_I ;
output \LOAD_REG_GEN[11].LOAD_REG_I ;
output \LOAD_REG_GEN[10].LOAD_REG_I ;
output \LOAD_REG_GEN[9].LOAD_REG_I ;
output \LOAD_REG_GEN[8].LOAD_REG_I ;
output \LOAD_REG_GEN[7].LOAD_REG_I ;
output \LOAD_REG_GEN[6].LOAD_REG_I ;
output \LOAD_REG_GEN[5].LOAD_REG_I ;
output \LOAD_REG_GEN[4].LOAD_REG_I ;
output \LOAD_REG_GEN[3].LOAD_REG_I ;
output \LOAD_REG_GEN[2].LOAD_REG_I ;
output \LOAD_REG_GEN[1].LOAD_REG_I ;
output D_0;
output [0:0]bus2ip_wrce__0;
output [1:0]bus2ip_wrce;
output \LOAD_REG_GEN[31].LOAD_REG_I_1 ;
output \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
output D_1;
output s_axi_rvalid_i_reg;
output s_axi_rvalid_i_reg_0;
output s_axi_rvalid_i_reg_1;
output s_axi_rvalid_i_reg_2;
output s_axi_bvalid_i_reg;
output \TCSR0_GENERATE[23].TCSR0_FF_I_0 ;
output \TCSR1_GENERATE[23].TCSR1_FF_I ;
output \s_axi_rdata_i_reg[10] ;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[0]_0 ;
output READ_DONE0_I;
output READ_DONE1_I;
input Q;
input s_axi_aclk;
input [87:0]read_Mux_In;
input s_axi_aresetn;
input state1__2;
input s_axi_arvalid_0;
input [1:0]\state_reg[1] ;
input [31:0]s_axi_wdata;
input s_axi_arvalid;
input is_write_reg;
input is_read;
input [5:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] ;
input s_axi_rready;
input s_axi_rvalid_i_reg_3;
input s_axi_bready;
input s_axi_bvalid_i_reg_0;
input bus2ip_rnw_i;
input D_2;
input read_done1;
input [2:0]\bus2ip_addr_i_reg[4] ;
wire Bus_RNW_reg_i_1_n_0;
wire [1:0]D;
wire D_0;
wire D_1;
wire D_2;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ;
wire [5:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] ;
wire \LOAD_REG_GEN[10].LOAD_REG_I ;
wire \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[11].LOAD_REG_I ;
wire \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[12].LOAD_REG_I ;
wire \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[13].LOAD_REG_I ;
wire \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[14].LOAD_REG_I ;
wire \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[15].LOAD_REG_I ;
wire \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[16].LOAD_REG_I ;
wire \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[17].LOAD_REG_I ;
wire \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[18].LOAD_REG_I ;
wire \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[19].LOAD_REG_I ;
wire \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[1].LOAD_REG_I ;
wire \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[22].LOAD_REG_I ;
wire \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[23].LOAD_REG_I ;
wire \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[25].LOAD_REG_I ;
wire \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[26].LOAD_REG_I ;
wire \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[27].LOAD_REG_I ;
wire \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[28].LOAD_REG_I ;
wire \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[29].LOAD_REG_I ;
wire \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[2].LOAD_REG_I ;
wire \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[30].LOAD_REG_I ;
wire \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_1 ;
wire \LOAD_REG_GEN[3].LOAD_REG_I ;
wire \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[4].LOAD_REG_I ;
wire \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[5].LOAD_REG_I ;
wire \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[6].LOAD_REG_I ;
wire \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[7].LOAD_REG_I ;
wire \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[8].LOAD_REG_I ;
wire \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[9].LOAD_REG_I ;
wire \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
wire Q;
wire READ_DONE0_I;
wire READ_DONE1_I;
wire \TCSR0_GENERATE[23].TCSR0_FF_I ;
wire \TCSR0_GENERATE[23].TCSR0_FF_I_0 ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[23].TCSR1_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire bus2ip_rnw_i;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire ce_expnd_i_5;
wire ce_expnd_i_6;
wire ce_expnd_i_7;
wire cs_ce_clr;
wire eqOp__4;
wire is_read;
wire is_write_reg;
wire pair0_Select;
wire [87:0]read_Mux_In;
wire read_done1;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arready_INST_0_i_4_n_0;
wire s_axi_arvalid;
wire s_axi_arvalid_0;
wire s_axi_bready;
wire s_axi_bvalid_i_reg;
wire s_axi_bvalid_i_reg_0;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[0]_0 ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[11] ;
wire \s_axi_rdata_i_reg[12] ;
wire \s_axi_rdata_i_reg[13] ;
wire \s_axi_rdata_i_reg[14] ;
wire \s_axi_rdata_i_reg[15] ;
wire \s_axi_rdata_i_reg[16] ;
wire \s_axi_rdata_i_reg[17] ;
wire \s_axi_rdata_i_reg[18] ;
wire \s_axi_rdata_i_reg[19] ;
wire \s_axi_rdata_i_reg[20] ;
wire \s_axi_rdata_i_reg[21] ;
wire \s_axi_rdata_i_reg[22] ;
wire \s_axi_rdata_i_reg[23] ;
wire \s_axi_rdata_i_reg[24] ;
wire \s_axi_rdata_i_reg[25] ;
wire \s_axi_rdata_i_reg[26] ;
wire \s_axi_rdata_i_reg[27] ;
wire \s_axi_rdata_i_reg[28] ;
wire \s_axi_rdata_i_reg[29] ;
wire \s_axi_rdata_i_reg[30] ;
wire \s_axi_rdata_i_reg[31] ;
wire s_axi_rready;
wire s_axi_rvalid_i_reg;
wire s_axi_rvalid_i_reg_0;
wire s_axi_rvalid_i_reg_1;
wire s_axi_rvalid_i_reg_2;
wire s_axi_rvalid_i_reg_3;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wready_INST_0_i_1_n_0;
wire s_axi_wready_INST_0_i_2_n_0;
wire state1__2;
wire [1:0]\state_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i),
.I1(Q),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.R(1'b0));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[84]),
.O(\s_axi_rdata_i_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h8))
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\s_axi_rdata_i_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\s_axi_rdata_i_reg[0] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[74]),
.O(\s_axi_rdata_i_reg[21] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[73]),
.O(\s_axi_rdata_i_reg[20] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[72]),
.O(\s_axi_rdata_i_reg[19] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[71]),
.O(\s_axi_rdata_i_reg[18] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[70]),
.O(\s_axi_rdata_i_reg[17] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[69]),
.O(\s_axi_rdata_i_reg[16] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[68]),
.O(\s_axi_rdata_i_reg[15] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[67]),
.O(\s_axi_rdata_i_reg[14] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[66]),
.O(\s_axi_rdata_i_reg[13] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[65]),
.O(\s_axi_rdata_i_reg[12] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[83]),
.O(\s_axi_rdata_i_reg[30] ));
LUT5 #(
.INIT(32'h0777FFFF))
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(read_Mux_In[64]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[87]),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\s_axi_rdata_i_reg[11] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h8))
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\s_axi_rdata_i_reg[10] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[82]),
.O(\s_axi_rdata_i_reg[29] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[81]),
.O(\s_axi_rdata_i_reg[28] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[80]),
.O(\s_axi_rdata_i_reg[27] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[79]),
.O(\s_axi_rdata_i_reg[26] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[78]),
.O(\s_axi_rdata_i_reg[25] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[77]),
.O(\s_axi_rdata_i_reg[24] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[76]),
.O(\s_axi_rdata_i_reg[23] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[75]),
.O(\s_axi_rdata_i_reg[22] ));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_7),
.Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.R(cs_ce_clr));
LUT4 #(
.INIT(16'h1000))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\bus2ip_addr_i_reg[4] [2]),
.I1(\bus2ip_addr_i_reg[4] [1]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [0]),
.O(ce_expnd_i_6));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_6),
.Q(\LOAD_REG_GEN[31].LOAD_REG_I ),
.R(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_5),
.Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.R(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_3),
.Q(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.R(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_2),
.Q(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.R(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_1),
.Q(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hEF))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arready),
.I2(s_axi_aresetn),
.O(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ),
.R(cs_ce_clr));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[0].LOAD_REG_I_i_2
(.I0(s_axi_wdata[31]),
.I1(read_Mux_In[31]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(D_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[0].LOAD_REG_I_i_2__0
(.I0(s_axi_wdata[31]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[63]),
.O(D_1));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
\LOAD_REG_GEN[0].LOAD_REG_I_i_7
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(bus2ip_wrce__0));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[10].LOAD_REG_I_i_1
(.I0(s_axi_wdata[21]),
.I1(read_Mux_In[21]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[10].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[10].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[21]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[53]),
.O(\LOAD_REG_GEN[10].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[11].LOAD_REG_I_i_1
(.I0(s_axi_wdata[20]),
.I1(read_Mux_In[20]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[11].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[11].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[20]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[52]),
.O(\LOAD_REG_GEN[11].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[12].LOAD_REG_I_i_1
(.I0(s_axi_wdata[19]),
.I1(read_Mux_In[19]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[12].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[12].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[19]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[51]),
.O(\LOAD_REG_GEN[12].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[13].LOAD_REG_I_i_1
(.I0(s_axi_wdata[18]),
.I1(read_Mux_In[18]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[13].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[13].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[18]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[50]),
.O(\LOAD_REG_GEN[13].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[14].LOAD_REG_I_i_1
(.I0(s_axi_wdata[17]),
.I1(read_Mux_In[17]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[14].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[14].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[17]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[49]),
.O(\LOAD_REG_GEN[14].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[15].LOAD_REG_I_i_1
(.I0(s_axi_wdata[16]),
.I1(read_Mux_In[16]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[15].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[15].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[16]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[48]),
.O(\LOAD_REG_GEN[15].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[16].LOAD_REG_I_i_1
(.I0(s_axi_wdata[15]),
.I1(read_Mux_In[15]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[16].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[16].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[15]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[47]),
.O(\LOAD_REG_GEN[16].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[17].LOAD_REG_I_i_1
(.I0(s_axi_wdata[14]),
.I1(read_Mux_In[14]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[17].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[17].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[14]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[46]),
.O(\LOAD_REG_GEN[17].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[18].LOAD_REG_I_i_1
(.I0(s_axi_wdata[13]),
.I1(read_Mux_In[13]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[18].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[18].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[13]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[45]),
.O(\LOAD_REG_GEN[18].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[19].LOAD_REG_I_i_1
(.I0(s_axi_wdata[12]),
.I1(read_Mux_In[12]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[19].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[19].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[12]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[44]),
.O(\LOAD_REG_GEN[19].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[1].LOAD_REG_I_i_1
(.I0(s_axi_wdata[30]),
.I1(read_Mux_In[30]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[1].LOAD_REG_I ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[1].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[30]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[62]),
.O(\LOAD_REG_GEN[1].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[20].LOAD_REG_I_i_1
(.I0(s_axi_wdata[11]),
.I1(read_Mux_In[11]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[20].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[20].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[11]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[43]),
.O(\LOAD_REG_GEN[20].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[21].LOAD_REG_I_i_1
(.I0(s_axi_wdata[10]),
.I1(read_Mux_In[10]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[21].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[21].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[10]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[42]),
.O(\LOAD_REG_GEN[21].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[22].LOAD_REG_I_i_1
(.I0(s_axi_wdata[9]),
.I1(read_Mux_In[9]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[22].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[22].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[9]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[41]),
.O(\LOAD_REG_GEN[22].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[23].LOAD_REG_I_i_1
(.I0(s_axi_wdata[8]),
.I1(read_Mux_In[8]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[23].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[23].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[8]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[40]),
.O(\LOAD_REG_GEN[23].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[24].LOAD_REG_I_i_1
(.I0(s_axi_wdata[7]),
.I1(read_Mux_In[7]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[24].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[24].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[7]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[39]),
.O(\LOAD_REG_GEN[24].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[25].LOAD_REG_I_i_1
(.I0(s_axi_wdata[6]),
.I1(read_Mux_In[6]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[25].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[25].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[6]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[38]),
.O(\LOAD_REG_GEN[25].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[26].LOAD_REG_I_i_1
(.I0(s_axi_wdata[5]),
.I1(read_Mux_In[5]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[26].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[26].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[5]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[37]),
.O(\LOAD_REG_GEN[26].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[27].LOAD_REG_I_i_1
(.I0(s_axi_wdata[4]),
.I1(read_Mux_In[4]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[27].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[27].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[4]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[36]),
.O(\LOAD_REG_GEN[27].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[28].LOAD_REG_I_i_1
(.I0(s_axi_wdata[3]),
.I1(read_Mux_In[3]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[28].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[28].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[3]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[35]),
.O(\LOAD_REG_GEN[28].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[29].LOAD_REG_I_i_1
(.I0(s_axi_wdata[2]),
.I1(read_Mux_In[2]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[29].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[29].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[2]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[34]),
.O(\LOAD_REG_GEN[29].LOAD_REG_I_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[2].LOAD_REG_I_i_1
(.I0(s_axi_wdata[29]),
.I1(read_Mux_In[29]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[2].LOAD_REG_I ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[2].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[29]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[61]),
.O(\LOAD_REG_GEN[2].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[30].LOAD_REG_I_i_1
(.I0(s_axi_wdata[1]),
.I1(read_Mux_In[1]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[30].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[30].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[1]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[33]),
.O(\LOAD_REG_GEN[30].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[31].LOAD_REG_I_i_1
(.I0(s_axi_wdata[0]),
.I1(read_Mux_In[0]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[31].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[31].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[0]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[32]),
.O(\LOAD_REG_GEN[31].LOAD_REG_I_1 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[3].LOAD_REG_I_i_1
(.I0(s_axi_wdata[28]),
.I1(read_Mux_In[28]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[3].LOAD_REG_I ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[3].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[28]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[60]),
.O(\LOAD_REG_GEN[3].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[4].LOAD_REG_I_i_1
(.I0(s_axi_wdata[27]),
.I1(read_Mux_In[27]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[4].LOAD_REG_I ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[4].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[27]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[59]),
.O(\LOAD_REG_GEN[4].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[5].LOAD_REG_I_i_1
(.I0(s_axi_wdata[26]),
.I1(read_Mux_In[26]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[5].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[5].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[26]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[58]),
.O(\LOAD_REG_GEN[5].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[6].LOAD_REG_I_i_1
(.I0(s_axi_wdata[25]),
.I1(read_Mux_In[25]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[6].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[6].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[25]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[57]),
.O(\LOAD_REG_GEN[6].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[7].LOAD_REG_I_i_1
(.I0(s_axi_wdata[24]),
.I1(read_Mux_In[24]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[7].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[7].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[24]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[56]),
.O(\LOAD_REG_GEN[7].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[8].LOAD_REG_I_i_1
(.I0(s_axi_wdata[23]),
.I1(read_Mux_In[23]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[8].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[8].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[23]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[55]),
.O(\LOAD_REG_GEN[8].LOAD_REG_I_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[9].LOAD_REG_I_i_1
(.I0(s_axi_wdata[22]),
.I1(read_Mux_In[22]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[9].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[9].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[22]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[54]),
.O(\LOAD_REG_GEN[9].LOAD_REG_I_0 ));
zqynq_lab_1_design_axi_timer_0_1_pselect_f \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_7(ce_expnd_i_7));
zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1 \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_5(ce_expnd_i_5));
zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3 \MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_3(ce_expnd_i_3));
zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4 \MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_2(ce_expnd_i_2));
zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5 \MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_1(ce_expnd_i_1));
zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6 \MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_0(ce_expnd_i_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'hE))
READ_DONE0_I_i_2
(.I0(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I1(D_2),
.O(READ_DONE0_I));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'hE))
READ_DONE1_I_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(read_done1),
.O(READ_DONE1_I));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h2))
\TCSR0_GENERATE[20].TCSR0_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(bus2ip_wrce[1]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h32))
\TCSR0_GENERATE[21].TCSR0_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I2(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.O(pair0_Select));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h20FF))
\TCSR0_GENERATE[23].TCSR0_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I2(s_axi_wdata[8]),
.I3(s_axi_aresetn),
.O(\TCSR0_GENERATE[23].TCSR0_FF_I_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hEFEEEAEE))
\TCSR0_GENERATE[24].TCSR0_FF_I_i_1
(.I0(s_axi_wdata[10]),
.I1(read_Mux_In[86]),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(s_axi_wdata[7]),
.O(\TCSR0_GENERATE[24].TCSR0_FF_I ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h2))
\TCSR1_GENERATE[22].TCSR1_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(bus2ip_wrce[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h20FF))
\TCSR1_GENERATE[23].TCSR1_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I2(s_axi_wdata[8]),
.I3(s_axi_aresetn),
.O(\TCSR1_GENERATE[23].TCSR1_FF_I ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hEFEEEAEE))
\TCSR1_GENERATE[24].TCSR1_FF_I_i_1
(.I0(s_axi_wdata[10]),
.I1(read_Mux_In[85]),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I4(s_axi_wdata[7]),
.O(\TCSR1_GENERATE[24].TCSR1_FF_I ));
LUT6 #(
.INIT(64'hFFFFFEFFFEFFFEFF))
s_axi_arready_INST_0
(.I0(s_axi_rvalid_i_reg),
.I1(s_axi_rvalid_i_reg_0),
.I2(s_axi_rvalid_i_reg_1),
.I3(s_axi_arready_INST_0_i_4_n_0),
.I4(is_read),
.I5(eqOp__4),
.O(s_axi_arready));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
s_axi_arready_INST_0_i_1
(.I0(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(s_axi_rvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h8))
s_axi_arready_INST_0_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(s_axi_rvalid_i_reg_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h8))
s_axi_arready_INST_0_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(s_axi_rvalid_i_reg_1));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00FF01FF))
s_axi_arready_INST_0_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(s_axi_arready_INST_0_i_4_n_0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(\state_reg[1] [1]),
.I2(\state_reg[1] [0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid_i_reg_0),
.O(s_axi_bvalid_i_reg));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid_i_reg_3),
.O(s_axi_rvalid_i_reg_2));
LUT4 #(
.INIT(16'hF777))
s_axi_wready_INST_0
(.I0(s_axi_wready_INST_0_i_1_n_0),
.I1(s_axi_wready_INST_0_i_2_n_0),
.I2(is_write_reg),
.I3(eqOp__4),
.O(s_axi_wready));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hF0F1))
s_axi_wready_INST_0_i_1
(.I0(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(s_axi_wready_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFF00FF01))
s_axi_wready_INST_0_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(s_axi_wready_INST_0_i_2_n_0));
LUT6 #(
.INIT(64'h0000000000000100))
s_axi_wready_INST_0_i_3
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [4]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [2]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [3]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [5]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [0]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [1]),
.O(eqOp__4));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(\state_reg[1] [0]),
.I2(s_axi_arvalid),
.I3(\state_reg[1] [1]),
.I4(s_axi_wready),
.O(D[0]));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(s_axi_arvalid_0),
.I2(\state_reg[1] [1]),
.I3(\state_reg[1] [0]),
.I4(s_axi_arready),
.O(D[1]));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif
(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
\s_axi_rdata_i_reg[12] ,
\s_axi_rdata_i_reg[13] ,
\s_axi_rdata_i_reg[14] ,
\s_axi_rdata_i_reg[15] ,
\s_axi_rdata_i_reg[16] ,
\s_axi_rdata_i_reg[17] ,
\s_axi_rdata_i_reg[18] ,
\s_axi_rdata_i_reg[19] ,
\s_axi_rdata_i_reg[20] ,
\s_axi_rdata_i_reg[21] ,
\s_axi_rdata_i_reg[22] ,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[24] ,
\s_axi_rdata_i_reg[25] ,
\s_axi_rdata_i_reg[26] ,
\s_axi_rdata_i_reg[27] ,
\s_axi_rdata_i_reg[28] ,
\s_axi_rdata_i_reg[29] ,
\s_axi_rdata_i_reg[30] ,
\s_axi_rdata_i_reg[31] ,
pair0_Select,
s_axi_wready,
s_axi_arready,
\s_axi_rdata_i_reg[11] ,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
\LOAD_REG_GEN[31].LOAD_REG_I ,
\LOAD_REG_GEN[30].LOAD_REG_I ,
\LOAD_REG_GEN[29].LOAD_REG_I ,
\LOAD_REG_GEN[28].LOAD_REG_I ,
\LOAD_REG_GEN[27].LOAD_REG_I ,
\LOAD_REG_GEN[26].LOAD_REG_I ,
\LOAD_REG_GEN[25].LOAD_REG_I ,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\LOAD_REG_GEN[23].LOAD_REG_I ,
\LOAD_REG_GEN[22].LOAD_REG_I ,
\LOAD_REG_GEN[21].LOAD_REG_I ,
\LOAD_REG_GEN[20].LOAD_REG_I ,
\LOAD_REG_GEN[19].LOAD_REG_I ,
\LOAD_REG_GEN[18].LOAD_REG_I ,
\LOAD_REG_GEN[17].LOAD_REG_I ,
\LOAD_REG_GEN[16].LOAD_REG_I ,
\LOAD_REG_GEN[15].LOAD_REG_I ,
\LOAD_REG_GEN[14].LOAD_REG_I ,
\LOAD_REG_GEN[13].LOAD_REG_I ,
\LOAD_REG_GEN[12].LOAD_REG_I ,
\LOAD_REG_GEN[11].LOAD_REG_I ,
\LOAD_REG_GEN[10].LOAD_REG_I ,
\LOAD_REG_GEN[9].LOAD_REG_I ,
\LOAD_REG_GEN[8].LOAD_REG_I ,
\LOAD_REG_GEN[7].LOAD_REG_I ,
\LOAD_REG_GEN[6].LOAD_REG_I ,
\LOAD_REG_GEN[5].LOAD_REG_I ,
\LOAD_REG_GEN[4].LOAD_REG_I ,
\LOAD_REG_GEN[3].LOAD_REG_I ,
\LOAD_REG_GEN[2].LOAD_REG_I ,
\LOAD_REG_GEN[1].LOAD_REG_I ,
D_0,
bus2ip_wrce__0,
bus2ip_wrce,
\LOAD_REG_GEN[31].LOAD_REG_I_0 ,
\LOAD_REG_GEN[30].LOAD_REG_I_0 ,
\LOAD_REG_GEN[29].LOAD_REG_I_0 ,
\LOAD_REG_GEN[28].LOAD_REG_I_0 ,
\LOAD_REG_GEN[27].LOAD_REG_I_0 ,
\LOAD_REG_GEN[26].LOAD_REG_I_0 ,
\LOAD_REG_GEN[25].LOAD_REG_I_0 ,
\LOAD_REG_GEN[24].LOAD_REG_I_0 ,
\LOAD_REG_GEN[23].LOAD_REG_I_0 ,
\LOAD_REG_GEN[22].LOAD_REG_I_0 ,
\LOAD_REG_GEN[21].LOAD_REG_I_0 ,
\LOAD_REG_GEN[20].LOAD_REG_I_0 ,
\LOAD_REG_GEN[19].LOAD_REG_I_0 ,
\LOAD_REG_GEN[18].LOAD_REG_I_0 ,
\LOAD_REG_GEN[17].LOAD_REG_I_0 ,
\LOAD_REG_GEN[16].LOAD_REG_I_0 ,
\LOAD_REG_GEN[15].LOAD_REG_I_0 ,
\LOAD_REG_GEN[14].LOAD_REG_I_0 ,
\LOAD_REG_GEN[13].LOAD_REG_I_0 ,
\LOAD_REG_GEN[12].LOAD_REG_I_0 ,
\LOAD_REG_GEN[11].LOAD_REG_I_0 ,
\LOAD_REG_GEN[10].LOAD_REG_I_0 ,
\LOAD_REG_GEN[9].LOAD_REG_I_0 ,
\LOAD_REG_GEN[8].LOAD_REG_I_0 ,
\LOAD_REG_GEN[7].LOAD_REG_I_0 ,
\LOAD_REG_GEN[6].LOAD_REG_I_0 ,
\LOAD_REG_GEN[5].LOAD_REG_I_0 ,
\LOAD_REG_GEN[4].LOAD_REG_I_0 ,
\LOAD_REG_GEN[3].LOAD_REG_I_0 ,
\LOAD_REG_GEN[2].LOAD_REG_I_0 ,
\LOAD_REG_GEN[1].LOAD_REG_I_0 ,
D_1,
s_axi_rvalid_i_reg,
s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_1,
\TCSR0_GENERATE[23].TCSR0_FF_I ,
\TCSR1_GENERATE[23].TCSR1_FF_I ,
\s_axi_rdata_i_reg[10] ,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[0]_0 ,
READ_DONE0_I,
READ_DONE1_I,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
read_Mux_In,
s_axi_aresetn,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_rready,
s_axi_bready,
s_axi_wdata,
D_2,
read_done1,
D);
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output \s_axi_rdata_i_reg[12] ;
output \s_axi_rdata_i_reg[13] ;
output \s_axi_rdata_i_reg[14] ;
output \s_axi_rdata_i_reg[15] ;
output \s_axi_rdata_i_reg[16] ;
output \s_axi_rdata_i_reg[17] ;
output \s_axi_rdata_i_reg[18] ;
output \s_axi_rdata_i_reg[19] ;
output \s_axi_rdata_i_reg[20] ;
output \s_axi_rdata_i_reg[21] ;
output \s_axi_rdata_i_reg[22] ;
output \s_axi_rdata_i_reg[23] ;
output \s_axi_rdata_i_reg[24] ;
output \s_axi_rdata_i_reg[25] ;
output \s_axi_rdata_i_reg[26] ;
output \s_axi_rdata_i_reg[27] ;
output \s_axi_rdata_i_reg[28] ;
output \s_axi_rdata_i_reg[29] ;
output \s_axi_rdata_i_reg[30] ;
output \s_axi_rdata_i_reg[31] ;
output pair0_Select;
output s_axi_wready;
output s_axi_arready;
output \s_axi_rdata_i_reg[11] ;
output \TCSR0_GENERATE[24].TCSR0_FF_I ;
output \TCSR1_GENERATE[24].TCSR1_FF_I ;
output \LOAD_REG_GEN[31].LOAD_REG_I ;
output \LOAD_REG_GEN[30].LOAD_REG_I ;
output \LOAD_REG_GEN[29].LOAD_REG_I ;
output \LOAD_REG_GEN[28].LOAD_REG_I ;
output \LOAD_REG_GEN[27].LOAD_REG_I ;
output \LOAD_REG_GEN[26].LOAD_REG_I ;
output \LOAD_REG_GEN[25].LOAD_REG_I ;
output \LOAD_REG_GEN[24].LOAD_REG_I ;
output \LOAD_REG_GEN[23].LOAD_REG_I ;
output \LOAD_REG_GEN[22].LOAD_REG_I ;
output \LOAD_REG_GEN[21].LOAD_REG_I ;
output \LOAD_REG_GEN[20].LOAD_REG_I ;
output \LOAD_REG_GEN[19].LOAD_REG_I ;
output \LOAD_REG_GEN[18].LOAD_REG_I ;
output \LOAD_REG_GEN[17].LOAD_REG_I ;
output \LOAD_REG_GEN[16].LOAD_REG_I ;
output \LOAD_REG_GEN[15].LOAD_REG_I ;
output \LOAD_REG_GEN[14].LOAD_REG_I ;
output \LOAD_REG_GEN[13].LOAD_REG_I ;
output \LOAD_REG_GEN[12].LOAD_REG_I ;
output \LOAD_REG_GEN[11].LOAD_REG_I ;
output \LOAD_REG_GEN[10].LOAD_REG_I ;
output \LOAD_REG_GEN[9].LOAD_REG_I ;
output \LOAD_REG_GEN[8].LOAD_REG_I ;
output \LOAD_REG_GEN[7].LOAD_REG_I ;
output \LOAD_REG_GEN[6].LOAD_REG_I ;
output \LOAD_REG_GEN[5].LOAD_REG_I ;
output \LOAD_REG_GEN[4].LOAD_REG_I ;
output \LOAD_REG_GEN[3].LOAD_REG_I ;
output \LOAD_REG_GEN[2].LOAD_REG_I ;
output \LOAD_REG_GEN[1].LOAD_REG_I ;
output D_0;
output [0:0]bus2ip_wrce__0;
output [1:0]bus2ip_wrce;
output \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
output D_1;
output s_axi_rvalid_i_reg;
output s_axi_rvalid_i_reg_0;
output s_axi_rvalid_i_reg_1;
output \TCSR0_GENERATE[23].TCSR0_FF_I ;
output \TCSR1_GENERATE[23].TCSR1_FF_I ;
output \s_axi_rdata_i_reg[10] ;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[0]_0 ;
output READ_DONE0_I;
output READ_DONE1_I;
output [31:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input [87:0]read_Mux_In;
input s_axi_aresetn;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_rready;
input s_axi_bready;
input [31:0]s_axi_wdata;
input D_2;
input read_done1;
input [31:0]D;
wire Bus_RNW_reg;
wire [31:0]D;
wire D_0;
wire D_1;
wire D_2;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \LOAD_REG_GEN[10].LOAD_REG_I ;
wire \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[11].LOAD_REG_I ;
wire \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[12].LOAD_REG_I ;
wire \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[13].LOAD_REG_I ;
wire \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[14].LOAD_REG_I ;
wire \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[15].LOAD_REG_I ;
wire \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[16].LOAD_REG_I ;
wire \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[17].LOAD_REG_I ;
wire \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[18].LOAD_REG_I ;
wire \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[19].LOAD_REG_I ;
wire \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[1].LOAD_REG_I ;
wire \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[22].LOAD_REG_I ;
wire \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[23].LOAD_REG_I ;
wire \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[25].LOAD_REG_I ;
wire \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[26].LOAD_REG_I ;
wire \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[27].LOAD_REG_I ;
wire \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[28].LOAD_REG_I ;
wire \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[29].LOAD_REG_I ;
wire \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[2].LOAD_REG_I ;
wire \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[30].LOAD_REG_I ;
wire \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[3].LOAD_REG_I ;
wire \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[4].LOAD_REG_I ;
wire \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[5].LOAD_REG_I ;
wire \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[6].LOAD_REG_I ;
wire \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[7].LOAD_REG_I ;
wire \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[8].LOAD_REG_I ;
wire \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[9].LOAD_REG_I ;
wire \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
wire READ_DONE0_I;
wire READ_DONE1_I;
wire \TCSR0_GENERATE[23].TCSR0_FF_I ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[23].TCSR1_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire bus2ip_reset;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire pair0_Select;
wire [87:0]read_Mux_In;
wire read_done1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[0]_0 ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[11] ;
wire \s_axi_rdata_i_reg[12] ;
wire \s_axi_rdata_i_reg[13] ;
wire \s_axi_rdata_i_reg[14] ;
wire \s_axi_rdata_i_reg[15] ;
wire \s_axi_rdata_i_reg[16] ;
wire \s_axi_rdata_i_reg[17] ;
wire \s_axi_rdata_i_reg[18] ;
wire \s_axi_rdata_i_reg[19] ;
wire \s_axi_rdata_i_reg[20] ;
wire \s_axi_rdata_i_reg[21] ;
wire \s_axi_rdata_i_reg[22] ;
wire \s_axi_rdata_i_reg[23] ;
wire \s_axi_rdata_i_reg[24] ;
wire \s_axi_rdata_i_reg[25] ;
wire \s_axi_rdata_i_reg[26] ;
wire \s_axi_rdata_i_reg[27] ;
wire \s_axi_rdata_i_reg[28] ;
wire \s_axi_rdata_i_reg[29] ;
wire \s_axi_rdata_i_reg[30] ;
wire \s_axi_rdata_i_reg[31] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_reg;
wire s_axi_rvalid_i_reg_0;
wire s_axi_rvalid_i_reg_1;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
zqynq_lab_1_design_axi_timer_0_1_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.D_0(D_0),
.D_1(D_1),
.D_2(D_2),
.\LOAD_REG_GEN[10].LOAD_REG_I (\LOAD_REG_GEN[10].LOAD_REG_I ),
.\LOAD_REG_GEN[10].LOAD_REG_I_0 (\LOAD_REG_GEN[10].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[11].LOAD_REG_I (\LOAD_REG_GEN[11].LOAD_REG_I ),
.\LOAD_REG_GEN[11].LOAD_REG_I_0 (\LOAD_REG_GEN[11].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[12].LOAD_REG_I (\LOAD_REG_GEN[12].LOAD_REG_I ),
.\LOAD_REG_GEN[12].LOAD_REG_I_0 (\LOAD_REG_GEN[12].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[13].LOAD_REG_I (\LOAD_REG_GEN[13].LOAD_REG_I ),
.\LOAD_REG_GEN[13].LOAD_REG_I_0 (\LOAD_REG_GEN[13].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[14].LOAD_REG_I (\LOAD_REG_GEN[14].LOAD_REG_I ),
.\LOAD_REG_GEN[14].LOAD_REG_I_0 (\LOAD_REG_GEN[14].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[15].LOAD_REG_I (\LOAD_REG_GEN[15].LOAD_REG_I ),
.\LOAD_REG_GEN[15].LOAD_REG_I_0 (\LOAD_REG_GEN[15].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[16].LOAD_REG_I (\LOAD_REG_GEN[16].LOAD_REG_I ),
.\LOAD_REG_GEN[16].LOAD_REG_I_0 (\LOAD_REG_GEN[16].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[17].LOAD_REG_I (\LOAD_REG_GEN[17].LOAD_REG_I ),
.\LOAD_REG_GEN[17].LOAD_REG_I_0 (\LOAD_REG_GEN[17].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[18].LOAD_REG_I (\LOAD_REG_GEN[18].LOAD_REG_I ),
.\LOAD_REG_GEN[18].LOAD_REG_I_0 (\LOAD_REG_GEN[18].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[19].LOAD_REG_I (\LOAD_REG_GEN[19].LOAD_REG_I ),
.\LOAD_REG_GEN[19].LOAD_REG_I_0 (\LOAD_REG_GEN[19].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[1].LOAD_REG_I (\LOAD_REG_GEN[1].LOAD_REG_I ),
.\LOAD_REG_GEN[1].LOAD_REG_I_0 (\LOAD_REG_GEN[1].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[20].LOAD_REG_I (\LOAD_REG_GEN[20].LOAD_REG_I ),
.\LOAD_REG_GEN[20].LOAD_REG_I_0 (\LOAD_REG_GEN[20].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[21].LOAD_REG_I (\LOAD_REG_GEN[21].LOAD_REG_I ),
.\LOAD_REG_GEN[21].LOAD_REG_I_0 (\LOAD_REG_GEN[21].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[22].LOAD_REG_I (\LOAD_REG_GEN[22].LOAD_REG_I ),
.\LOAD_REG_GEN[22].LOAD_REG_I_0 (\LOAD_REG_GEN[22].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[23].LOAD_REG_I (\LOAD_REG_GEN[23].LOAD_REG_I ),
.\LOAD_REG_GEN[23].LOAD_REG_I_0 (\LOAD_REG_GEN[23].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[24].LOAD_REG_I (\LOAD_REG_GEN[24].LOAD_REG_I ),
.\LOAD_REG_GEN[24].LOAD_REG_I_0 (\LOAD_REG_GEN[24].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[25].LOAD_REG_I (\LOAD_REG_GEN[25].LOAD_REG_I ),
.\LOAD_REG_GEN[25].LOAD_REG_I_0 (\LOAD_REG_GEN[25].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[26].LOAD_REG_I (\LOAD_REG_GEN[26].LOAD_REG_I ),
.\LOAD_REG_GEN[26].LOAD_REG_I_0 (\LOAD_REG_GEN[26].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[27].LOAD_REG_I (\LOAD_REG_GEN[27].LOAD_REG_I ),
.\LOAD_REG_GEN[27].LOAD_REG_I_0 (\LOAD_REG_GEN[27].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[28].LOAD_REG_I (\LOAD_REG_GEN[28].LOAD_REG_I ),
.\LOAD_REG_GEN[28].LOAD_REG_I_0 (\LOAD_REG_GEN[28].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[29].LOAD_REG_I (\LOAD_REG_GEN[29].LOAD_REG_I ),
.\LOAD_REG_GEN[29].LOAD_REG_I_0 (\LOAD_REG_GEN[29].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[2].LOAD_REG_I (\LOAD_REG_GEN[2].LOAD_REG_I ),
.\LOAD_REG_GEN[2].LOAD_REG_I_0 (\LOAD_REG_GEN[2].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[30].LOAD_REG_I (\LOAD_REG_GEN[30].LOAD_REG_I ),
.\LOAD_REG_GEN[30].LOAD_REG_I_0 (\LOAD_REG_GEN[30].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[31].LOAD_REG_I (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\LOAD_REG_GEN[31].LOAD_REG_I_0 (\LOAD_REG_GEN[31].LOAD_REG_I ),
.\LOAD_REG_GEN[31].LOAD_REG_I_1 (\LOAD_REG_GEN[31].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[3].LOAD_REG_I (\LOAD_REG_GEN[3].LOAD_REG_I ),
.\LOAD_REG_GEN[3].LOAD_REG_I_0 (\LOAD_REG_GEN[3].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[4].LOAD_REG_I (\LOAD_REG_GEN[4].LOAD_REG_I ),
.\LOAD_REG_GEN[4].LOAD_REG_I_0 (\LOAD_REG_GEN[4].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[5].LOAD_REG_I (\LOAD_REG_GEN[5].LOAD_REG_I ),
.\LOAD_REG_GEN[5].LOAD_REG_I_0 (\LOAD_REG_GEN[5].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[6].LOAD_REG_I (\LOAD_REG_GEN[6].LOAD_REG_I ),
.\LOAD_REG_GEN[6].LOAD_REG_I_0 (\LOAD_REG_GEN[6].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[7].LOAD_REG_I (\LOAD_REG_GEN[7].LOAD_REG_I ),
.\LOAD_REG_GEN[7].LOAD_REG_I_0 (\LOAD_REG_GEN[7].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[8].LOAD_REG_I (\LOAD_REG_GEN[8].LOAD_REG_I ),
.\LOAD_REG_GEN[8].LOAD_REG_I_0 (\LOAD_REG_GEN[8].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[9].LOAD_REG_I (\LOAD_REG_GEN[9].LOAD_REG_I ),
.\LOAD_REG_GEN[9].LOAD_REG_I_0 (\LOAD_REG_GEN[9].LOAD_REG_I_0 ),
.READ_DONE0_I(READ_DONE0_I),
.READ_DONE1_I(READ_DONE1_I),
.\TCSR0_GENERATE[23].TCSR0_FF_I (Bus_RNW_reg),
.\TCSR0_GENERATE[23].TCSR0_FF_I_0 (\TCSR0_GENERATE[23].TCSR0_FF_I ),
.\TCSR0_GENERATE[24].TCSR0_FF_I (\TCSR0_GENERATE[24].TCSR0_FF_I ),
.\TCSR1_GENERATE[23].TCSR1_FF_I (\TCSR1_GENERATE[23].TCSR1_FF_I ),
.\TCSR1_GENERATE[24].TCSR1_FF_I (\TCSR1_GENERATE[24].TCSR1_FF_I ),
.bus2ip_reset(bus2ip_reset),
.bus2ip_wrce(bus2ip_wrce),
.bus2ip_wrce__0(bus2ip_wrce__0),
.pair0_Select(pair0_Select),
.read_Mux_In(read_Mux_In),
.read_done1(read_done1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.\s_axi_rdata_i_reg[0]_0 (\s_axi_rdata_i_reg[0] ),
.\s_axi_rdata_i_reg[0]_1 (\s_axi_rdata_i_reg[0]_0 ),
.\s_axi_rdata_i_reg[10]_0 (\s_axi_rdata_i_reg[10] ),
.\s_axi_rdata_i_reg[11]_0 (\s_axi_rdata_i_reg[11] ),
.\s_axi_rdata_i_reg[12]_0 (\s_axi_rdata_i_reg[12] ),
.\s_axi_rdata_i_reg[13]_0 (\s_axi_rdata_i_reg[13] ),
.\s_axi_rdata_i_reg[14]_0 (\s_axi_rdata_i_reg[14] ),
.\s_axi_rdata_i_reg[15]_0 (\s_axi_rdata_i_reg[15] ),
.\s_axi_rdata_i_reg[16]_0 (\s_axi_rdata_i_reg[16] ),
.\s_axi_rdata_i_reg[17]_0 (\s_axi_rdata_i_reg[17] ),
.\s_axi_rdata_i_reg[18]_0 (\s_axi_rdata_i_reg[18] ),
.\s_axi_rdata_i_reg[19]_0 (\s_axi_rdata_i_reg[19] ),
.\s_axi_rdata_i_reg[20]_0 (\s_axi_rdata_i_reg[20] ),
.\s_axi_rdata_i_reg[21]_0 (\s_axi_rdata_i_reg[21] ),
.\s_axi_rdata_i_reg[22]_0 (\s_axi_rdata_i_reg[22] ),
.\s_axi_rdata_i_reg[23]_0 (\s_axi_rdata_i_reg[23] ),
.\s_axi_rdata_i_reg[24]_0 (\s_axi_rdata_i_reg[24] ),
.\s_axi_rdata_i_reg[25]_0 (\s_axi_rdata_i_reg[25] ),
.\s_axi_rdata_i_reg[26]_0 (\s_axi_rdata_i_reg[26] ),
.\s_axi_rdata_i_reg[27]_0 (\s_axi_rdata_i_reg[27] ),
.\s_axi_rdata_i_reg[28]_0 (\s_axi_rdata_i_reg[28] ),
.\s_axi_rdata_i_reg[29]_0 (\s_axi_rdata_i_reg[29] ),
.\s_axi_rdata_i_reg[30]_0 (\s_axi_rdata_i_reg[30] ),
.\s_axi_rdata_i_reg[31]_0 (\s_axi_rdata_i_reg[31] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rvalid_i_reg_0(s_axi_rvalid_i_reg),
.s_axi_rvalid_i_reg_1(s_axi_rvalid_i_reg_0),
.s_axi_rvalid_i_reg_2(s_axi_rvalid_i_reg_1),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* C_COUNT_WIDTH = "32" *) (* C_FAMILY = "zynq" *) (* C_GEN0_ASSERT = "1'b1" *)
(* C_GEN1_ASSERT = "1'b1" *) (* C_ONE_TIMER_ONLY = "0" *) (* C_S_AXI_ADDR_WIDTH = "5" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRIG0_ASSERT = "1'b1" *) (* C_TRIG1_ASSERT = "1'b1" *)
(* ORIG_REF_NAME = "axi_timer" *) (* downgradeipidentifiedwarnings = "yes" *)
module zqynq_lab_1_design_axi_timer_0_1_axi_timer
(capturetrig0,
capturetrig1,
generateout0,
generateout1,
pwm0,
interrupt,
freeze,
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready);
input capturetrig0;
input capturetrig1;
output generateout0;
output generateout1;
output pwm0;
output interrupt;
input freeze;
(* max_fanout = "10000" *) input s_axi_aclk;
(* max_fanout = "10000" *) input s_axi_aresetn;
input [4:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [4:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
wire \<const0> ;
wire AXI4_LITE_I_n_10;
wire AXI4_LITE_I_n_100;
wire AXI4_LITE_I_n_101;
wire AXI4_LITE_I_n_102;
wire AXI4_LITE_I_n_103;
wire AXI4_LITE_I_n_104;
wire AXI4_LITE_I_n_105;
wire AXI4_LITE_I_n_106;
wire AXI4_LITE_I_n_11;
wire AXI4_LITE_I_n_12;
wire AXI4_LITE_I_n_13;
wire AXI4_LITE_I_n_14;
wire AXI4_LITE_I_n_15;
wire AXI4_LITE_I_n_16;
wire AXI4_LITE_I_n_17;
wire AXI4_LITE_I_n_18;
wire AXI4_LITE_I_n_19;
wire AXI4_LITE_I_n_20;
wire AXI4_LITE_I_n_21;
wire AXI4_LITE_I_n_22;
wire AXI4_LITE_I_n_23;
wire AXI4_LITE_I_n_27;
wire AXI4_LITE_I_n_28;
wire AXI4_LITE_I_n_29;
wire AXI4_LITE_I_n_30;
wire AXI4_LITE_I_n_31;
wire AXI4_LITE_I_n_32;
wire AXI4_LITE_I_n_33;
wire AXI4_LITE_I_n_34;
wire AXI4_LITE_I_n_35;
wire AXI4_LITE_I_n_36;
wire AXI4_LITE_I_n_37;
wire AXI4_LITE_I_n_38;
wire AXI4_LITE_I_n_39;
wire AXI4_LITE_I_n_4;
wire AXI4_LITE_I_n_40;
wire AXI4_LITE_I_n_41;
wire AXI4_LITE_I_n_42;
wire AXI4_LITE_I_n_43;
wire AXI4_LITE_I_n_44;
wire AXI4_LITE_I_n_45;
wire AXI4_LITE_I_n_46;
wire AXI4_LITE_I_n_47;
wire AXI4_LITE_I_n_48;
wire AXI4_LITE_I_n_49;
wire AXI4_LITE_I_n_5;
wire AXI4_LITE_I_n_50;
wire AXI4_LITE_I_n_51;
wire AXI4_LITE_I_n_52;
wire AXI4_LITE_I_n_53;
wire AXI4_LITE_I_n_54;
wire AXI4_LITE_I_n_55;
wire AXI4_LITE_I_n_56;
wire AXI4_LITE_I_n_57;
wire AXI4_LITE_I_n_58;
wire AXI4_LITE_I_n_59;
wire AXI4_LITE_I_n_6;
wire AXI4_LITE_I_n_60;
wire AXI4_LITE_I_n_65;
wire AXI4_LITE_I_n_66;
wire AXI4_LITE_I_n_67;
wire AXI4_LITE_I_n_68;
wire AXI4_LITE_I_n_69;
wire AXI4_LITE_I_n_7;
wire AXI4_LITE_I_n_70;
wire AXI4_LITE_I_n_71;
wire AXI4_LITE_I_n_72;
wire AXI4_LITE_I_n_73;
wire AXI4_LITE_I_n_74;
wire AXI4_LITE_I_n_75;
wire AXI4_LITE_I_n_76;
wire AXI4_LITE_I_n_77;
wire AXI4_LITE_I_n_78;
wire AXI4_LITE_I_n_79;
wire AXI4_LITE_I_n_8;
wire AXI4_LITE_I_n_80;
wire AXI4_LITE_I_n_81;
wire AXI4_LITE_I_n_82;
wire AXI4_LITE_I_n_83;
wire AXI4_LITE_I_n_84;
wire AXI4_LITE_I_n_85;
wire AXI4_LITE_I_n_86;
wire AXI4_LITE_I_n_87;
wire AXI4_LITE_I_n_88;
wire AXI4_LITE_I_n_89;
wire AXI4_LITE_I_n_9;
wire AXI4_LITE_I_n_90;
wire AXI4_LITE_I_n_91;
wire AXI4_LITE_I_n_92;
wire AXI4_LITE_I_n_93;
wire AXI4_LITE_I_n_94;
wire AXI4_LITE_I_n_95;
wire AXI4_LITE_I_n_97;
wire AXI4_LITE_I_n_98;
wire AXI4_LITE_I_n_99;
wire \COUNTER_0_I/D ;
wire \GEN_SECOND_TIMER.COUNTER_1_I/D ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \TIMER_CONTROL_I/D ;
wire \TIMER_CONTROL_I/pair0_Select ;
wire \TIMER_CONTROL_I/read_done1 ;
wire bus2ip_reset;
wire [0:4]bus2ip_wrce;
wire [5:5]bus2ip_wrce__0;
wire capturetrig0;
wire capturetrig1;
wire freeze;
wire generateout0;
wire generateout1;
wire interrupt;
wire [0:31]ip2bus_data;
wire pwm0;
wire [20:191]read_Mux_In;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) wire s_axi_aclk;
wire [4:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [4:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
zqynq_lab_1_design_axi_timer_0_1_axi_lite_ipif AXI4_LITE_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.D({ip2bus_data[0],ip2bus_data[1],ip2bus_data[2],ip2bus_data[3],ip2bus_data[4],ip2bus_data[5],ip2bus_data[6],ip2bus_data[7],ip2bus_data[8],ip2bus_data[9],ip2bus_data[10],ip2bus_data[11],ip2bus_data[12],ip2bus_data[13],ip2bus_data[14],ip2bus_data[15],ip2bus_data[16],ip2bus_data[17],ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.D_0(\GEN_SECOND_TIMER.COUNTER_1_I/D ),
.D_1(\COUNTER_0_I/D ),
.D_2(\TIMER_CONTROL_I/D ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\LOAD_REG_GEN[10].LOAD_REG_I (AXI4_LITE_I_n_51),
.\LOAD_REG_GEN[10].LOAD_REG_I_0 (AXI4_LITE_I_n_86),
.\LOAD_REG_GEN[11].LOAD_REG_I (AXI4_LITE_I_n_50),
.\LOAD_REG_GEN[11].LOAD_REG_I_0 (AXI4_LITE_I_n_85),
.\LOAD_REG_GEN[12].LOAD_REG_I (AXI4_LITE_I_n_49),
.\LOAD_REG_GEN[12].LOAD_REG_I_0 (AXI4_LITE_I_n_84),
.\LOAD_REG_GEN[13].LOAD_REG_I (AXI4_LITE_I_n_48),
.\LOAD_REG_GEN[13].LOAD_REG_I_0 (AXI4_LITE_I_n_83),
.\LOAD_REG_GEN[14].LOAD_REG_I (AXI4_LITE_I_n_47),
.\LOAD_REG_GEN[14].LOAD_REG_I_0 (AXI4_LITE_I_n_82),
.\LOAD_REG_GEN[15].LOAD_REG_I (AXI4_LITE_I_n_46),
.\LOAD_REG_GEN[15].LOAD_REG_I_0 (AXI4_LITE_I_n_81),
.\LOAD_REG_GEN[16].LOAD_REG_I (AXI4_LITE_I_n_45),
.\LOAD_REG_GEN[16].LOAD_REG_I_0 (AXI4_LITE_I_n_80),
.\LOAD_REG_GEN[17].LOAD_REG_I (AXI4_LITE_I_n_44),
.\LOAD_REG_GEN[17].LOAD_REG_I_0 (AXI4_LITE_I_n_79),
.\LOAD_REG_GEN[18].LOAD_REG_I (AXI4_LITE_I_n_43),
.\LOAD_REG_GEN[18].LOAD_REG_I_0 (AXI4_LITE_I_n_78),
.\LOAD_REG_GEN[19].LOAD_REG_I (AXI4_LITE_I_n_42),
.\LOAD_REG_GEN[19].LOAD_REG_I_0 (AXI4_LITE_I_n_77),
.\LOAD_REG_GEN[1].LOAD_REG_I (AXI4_LITE_I_n_60),
.\LOAD_REG_GEN[1].LOAD_REG_I_0 (AXI4_LITE_I_n_95),
.\LOAD_REG_GEN[20].LOAD_REG_I (AXI4_LITE_I_n_41),
.\LOAD_REG_GEN[20].LOAD_REG_I_0 (AXI4_LITE_I_n_76),
.\LOAD_REG_GEN[21].LOAD_REG_I (AXI4_LITE_I_n_40),
.\LOAD_REG_GEN[21].LOAD_REG_I_0 (AXI4_LITE_I_n_75),
.\LOAD_REG_GEN[22].LOAD_REG_I (AXI4_LITE_I_n_39),
.\LOAD_REG_GEN[22].LOAD_REG_I_0 (AXI4_LITE_I_n_74),
.\LOAD_REG_GEN[23].LOAD_REG_I (AXI4_LITE_I_n_38),
.\LOAD_REG_GEN[23].LOAD_REG_I_0 (AXI4_LITE_I_n_73),
.\LOAD_REG_GEN[24].LOAD_REG_I (AXI4_LITE_I_n_37),
.\LOAD_REG_GEN[24].LOAD_REG_I_0 (AXI4_LITE_I_n_72),
.\LOAD_REG_GEN[25].LOAD_REG_I (AXI4_LITE_I_n_36),
.\LOAD_REG_GEN[25].LOAD_REG_I_0 (AXI4_LITE_I_n_71),
.\LOAD_REG_GEN[26].LOAD_REG_I (AXI4_LITE_I_n_35),
.\LOAD_REG_GEN[26].LOAD_REG_I_0 (AXI4_LITE_I_n_70),
.\LOAD_REG_GEN[27].LOAD_REG_I (AXI4_LITE_I_n_34),
.\LOAD_REG_GEN[27].LOAD_REG_I_0 (AXI4_LITE_I_n_69),
.\LOAD_REG_GEN[28].LOAD_REG_I (AXI4_LITE_I_n_33),
.\LOAD_REG_GEN[28].LOAD_REG_I_0 (AXI4_LITE_I_n_68),
.\LOAD_REG_GEN[29].LOAD_REG_I (AXI4_LITE_I_n_32),
.\LOAD_REG_GEN[29].LOAD_REG_I_0 (AXI4_LITE_I_n_67),
.\LOAD_REG_GEN[2].LOAD_REG_I (AXI4_LITE_I_n_59),
.\LOAD_REG_GEN[2].LOAD_REG_I_0 (AXI4_LITE_I_n_94),
.\LOAD_REG_GEN[30].LOAD_REG_I (AXI4_LITE_I_n_31),
.\LOAD_REG_GEN[30].LOAD_REG_I_0 (AXI4_LITE_I_n_66),
.\LOAD_REG_GEN[31].LOAD_REG_I (AXI4_LITE_I_n_30),
.\LOAD_REG_GEN[31].LOAD_REG_I_0 (AXI4_LITE_I_n_65),
.\LOAD_REG_GEN[3].LOAD_REG_I (AXI4_LITE_I_n_58),
.\LOAD_REG_GEN[3].LOAD_REG_I_0 (AXI4_LITE_I_n_93),
.\LOAD_REG_GEN[4].LOAD_REG_I (AXI4_LITE_I_n_57),
.\LOAD_REG_GEN[4].LOAD_REG_I_0 (AXI4_LITE_I_n_92),
.\LOAD_REG_GEN[5].LOAD_REG_I (AXI4_LITE_I_n_56),
.\LOAD_REG_GEN[5].LOAD_REG_I_0 (AXI4_LITE_I_n_91),
.\LOAD_REG_GEN[6].LOAD_REG_I (AXI4_LITE_I_n_55),
.\LOAD_REG_GEN[6].LOAD_REG_I_0 (AXI4_LITE_I_n_90),
.\LOAD_REG_GEN[7].LOAD_REG_I (AXI4_LITE_I_n_54),
.\LOAD_REG_GEN[7].LOAD_REG_I_0 (AXI4_LITE_I_n_89),
.\LOAD_REG_GEN[8].LOAD_REG_I (AXI4_LITE_I_n_53),
.\LOAD_REG_GEN[8].LOAD_REG_I_0 (AXI4_LITE_I_n_88),
.\LOAD_REG_GEN[9].LOAD_REG_I (AXI4_LITE_I_n_52),
.\LOAD_REG_GEN[9].LOAD_REG_I_0 (AXI4_LITE_I_n_87),
.READ_DONE0_I(AXI4_LITE_I_n_105),
.READ_DONE1_I(AXI4_LITE_I_n_106),
.\TCSR0_GENERATE[23].TCSR0_FF_I (AXI4_LITE_I_n_100),
.\TCSR0_GENERATE[24].TCSR0_FF_I (AXI4_LITE_I_n_28),
.\TCSR1_GENERATE[23].TCSR1_FF_I (AXI4_LITE_I_n_101),
.\TCSR1_GENERATE[24].TCSR1_FF_I (AXI4_LITE_I_n_29),
.bus2ip_reset(bus2ip_reset),
.bus2ip_wrce({bus2ip_wrce[0],bus2ip_wrce[4]}),
.bus2ip_wrce__0(bus2ip_wrce__0),
.pair0_Select(\TIMER_CONTROL_I/pair0_Select ),
.read_Mux_In({read_Mux_In[20],read_Mux_In[24],read_Mux_In[56],read_Mux_In[64],read_Mux_In[65],read_Mux_In[66],read_Mux_In[67],read_Mux_In[68],read_Mux_In[69],read_Mux_In[70],read_Mux_In[71],read_Mux_In[72],read_Mux_In[73],read_Mux_In[74],read_Mux_In[75],read_Mux_In[76],read_Mux_In[77],read_Mux_In[78],read_Mux_In[79],read_Mux_In[80],read_Mux_In[81],read_Mux_In[82],read_Mux_In[83],read_Mux_In[84],read_Mux_In[128],read_Mux_In[129],read_Mux_In[130],read_Mux_In[131],read_Mux_In[132],read_Mux_In[133],read_Mux_In[134],read_Mux_In[135],read_Mux_In[136],read_Mux_In[137],read_Mux_In[138],read_Mux_In[139],read_Mux_In[140],read_Mux_In[141],read_Mux_In[142],read_Mux_In[143],read_Mux_In[144],read_Mux_In[145],read_Mux_In[146],read_Mux_In[147],read_Mux_In[148],read_Mux_In[149],read_Mux_In[150],read_Mux_In[151],read_Mux_In[152],read_Mux_In[153],read_Mux_In[154],read_Mux_In[155],read_Mux_In[156],read_Mux_In[157],read_Mux_In[158],read_Mux_In[159],read_Mux_In[160],read_Mux_In[161],read_Mux_In[162],read_Mux_In[163],read_Mux_In[164],read_Mux_In[165],read_Mux_In[166],read_Mux_In[167],read_Mux_In[168],read_Mux_In[169],read_Mux_In[170],read_Mux_In[171],read_Mux_In[172],read_Mux_In[173],read_Mux_In[174],read_Mux_In[175],read_Mux_In[176],read_Mux_In[177],read_Mux_In[178],read_Mux_In[179],read_Mux_In[180],read_Mux_In[181],read_Mux_In[182],read_Mux_In[183],read_Mux_In[184],read_Mux_In[185],read_Mux_In[186],read_Mux_In[187],read_Mux_In[188],read_Mux_In[189],read_Mux_In[190],read_Mux_In[191]}),
.read_done1(\TIMER_CONTROL_I/read_done1 ),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[4:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[4:2]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.\s_axi_rdata_i_reg[0] (AXI4_LITE_I_n_103),
.\s_axi_rdata_i_reg[0]_0 (AXI4_LITE_I_n_104),
.\s_axi_rdata_i_reg[10] (AXI4_LITE_I_n_102),
.\s_axi_rdata_i_reg[11] (AXI4_LITE_I_n_27),
.\s_axi_rdata_i_reg[12] (AXI4_LITE_I_n_4),
.\s_axi_rdata_i_reg[13] (AXI4_LITE_I_n_5),
.\s_axi_rdata_i_reg[14] (AXI4_LITE_I_n_6),
.\s_axi_rdata_i_reg[15] (AXI4_LITE_I_n_7),
.\s_axi_rdata_i_reg[16] (AXI4_LITE_I_n_8),
.\s_axi_rdata_i_reg[17] (AXI4_LITE_I_n_9),
.\s_axi_rdata_i_reg[18] (AXI4_LITE_I_n_10),
.\s_axi_rdata_i_reg[19] (AXI4_LITE_I_n_11),
.\s_axi_rdata_i_reg[20] (AXI4_LITE_I_n_12),
.\s_axi_rdata_i_reg[21] (AXI4_LITE_I_n_13),
.\s_axi_rdata_i_reg[22] (AXI4_LITE_I_n_14),
.\s_axi_rdata_i_reg[23] (AXI4_LITE_I_n_15),
.\s_axi_rdata_i_reg[24] (AXI4_LITE_I_n_16),
.\s_axi_rdata_i_reg[25] (AXI4_LITE_I_n_17),
.\s_axi_rdata_i_reg[26] (AXI4_LITE_I_n_18),
.\s_axi_rdata_i_reg[27] (AXI4_LITE_I_n_19),
.\s_axi_rdata_i_reg[28] (AXI4_LITE_I_n_20),
.\s_axi_rdata_i_reg[29] (AXI4_LITE_I_n_21),
.\s_axi_rdata_i_reg[30] (AXI4_LITE_I_n_22),
.\s_axi_rdata_i_reg[31] (AXI4_LITE_I_n_23),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rvalid_i_reg(AXI4_LITE_I_n_97),
.s_axi_rvalid_i_reg_0(AXI4_LITE_I_n_98),
.s_axi_rvalid_i_reg_1(AXI4_LITE_I_n_99),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
zqynq_lab_1_design_axi_timer_0_1_tc_core TC_CORE_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.Bus_RNW_reg_reg(AXI4_LITE_I_n_23),
.Bus_RNW_reg_reg_0(AXI4_LITE_I_n_22),
.Bus_RNW_reg_reg_1(AXI4_LITE_I_n_21),
.Bus_RNW_reg_reg_10(AXI4_LITE_I_n_12),
.Bus_RNW_reg_reg_11(AXI4_LITE_I_n_11),
.Bus_RNW_reg_reg_12(AXI4_LITE_I_n_10),
.Bus_RNW_reg_reg_13(AXI4_LITE_I_n_9),
.Bus_RNW_reg_reg_14(AXI4_LITE_I_n_8),
.Bus_RNW_reg_reg_15(AXI4_LITE_I_n_7),
.Bus_RNW_reg_reg_16(AXI4_LITE_I_n_6),
.Bus_RNW_reg_reg_17(AXI4_LITE_I_n_5),
.Bus_RNW_reg_reg_18(AXI4_LITE_I_n_4),
.Bus_RNW_reg_reg_2(AXI4_LITE_I_n_20),
.Bus_RNW_reg_reg_3(AXI4_LITE_I_n_19),
.Bus_RNW_reg_reg_4(AXI4_LITE_I_n_18),
.Bus_RNW_reg_reg_5(AXI4_LITE_I_n_17),
.Bus_RNW_reg_reg_6(AXI4_LITE_I_n_16),
.Bus_RNW_reg_reg_7(AXI4_LITE_I_n_15),
.Bus_RNW_reg_reg_8(AXI4_LITE_I_n_14),
.Bus_RNW_reg_reg_9(AXI4_LITE_I_n_13),
.D({ip2bus_data[0],ip2bus_data[1],ip2bus_data[2],ip2bus_data[3],ip2bus_data[4],ip2bus_data[5],ip2bus_data[6],ip2bus_data[7],ip2bus_data[8],ip2bus_data[9],ip2bus_data[10],ip2bus_data[11],ip2bus_data[12],ip2bus_data[13],ip2bus_data[14],ip2bus_data[15],ip2bus_data[16],ip2bus_data[17],ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.D_0(\TIMER_CONTROL_I/D ),
.D_1(\COUNTER_0_I/D ),
.D_2(\GEN_SECOND_TIMER.COUNTER_1_I/D ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (AXI4_LITE_I_n_100),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 (AXI4_LITE_I_n_102),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (AXI4_LITE_I_n_95),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (AXI4_LITE_I_n_94),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 (AXI4_LITE_I_n_93),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 (AXI4_LITE_I_n_84),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 (AXI4_LITE_I_n_83),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 (AXI4_LITE_I_n_82),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 (AXI4_LITE_I_n_81),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 (AXI4_LITE_I_n_80),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 (AXI4_LITE_I_n_79),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 (AXI4_LITE_I_n_78),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 (AXI4_LITE_I_n_77),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 (AXI4_LITE_I_n_76),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 (AXI4_LITE_I_n_75),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 (AXI4_LITE_I_n_92),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 (AXI4_LITE_I_n_74),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 (AXI4_LITE_I_n_73),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 (AXI4_LITE_I_n_72),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 (AXI4_LITE_I_n_71),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 (AXI4_LITE_I_n_70),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 (AXI4_LITE_I_n_69),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 (AXI4_LITE_I_n_68),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 (AXI4_LITE_I_n_67),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 (AXI4_LITE_I_n_66),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 (AXI4_LITE_I_n_65),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 (AXI4_LITE_I_n_91),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 (AXI4_LITE_I_n_105),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 (AXI4_LITE_I_n_97),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 (AXI4_LITE_I_n_90),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 (AXI4_LITE_I_n_89),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 (AXI4_LITE_I_n_88),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 (AXI4_LITE_I_n_87),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 (AXI4_LITE_I_n_86),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 (AXI4_LITE_I_n_85),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (AXI4_LITE_I_n_99),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (AXI4_LITE_I_n_101),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (AXI4_LITE_I_n_98),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] (AXI4_LITE_I_n_106),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 (AXI4_LITE_I_n_103),
.\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] (AXI4_LITE_I_n_104),
.\INFERRED_GEN.icount_out_reg[0] ({read_Mux_In[20],read_Mux_In[24],read_Mux_In[56],read_Mux_In[64],read_Mux_In[65],read_Mux_In[66],read_Mux_In[67],read_Mux_In[68],read_Mux_In[69],read_Mux_In[70],read_Mux_In[71],read_Mux_In[72],read_Mux_In[73],read_Mux_In[74],read_Mux_In[75],read_Mux_In[76],read_Mux_In[77],read_Mux_In[78],read_Mux_In[79],read_Mux_In[80],read_Mux_In[81],read_Mux_In[82],read_Mux_In[83],read_Mux_In[84],read_Mux_In[128],read_Mux_In[129],read_Mux_In[130],read_Mux_In[131],read_Mux_In[132],read_Mux_In[133],read_Mux_In[134],read_Mux_In[135],read_Mux_In[136],read_Mux_In[137],read_Mux_In[138],read_Mux_In[139],read_Mux_In[140],read_Mux_In[141],read_Mux_In[142],read_Mux_In[143],read_Mux_In[144],read_Mux_In[145],read_Mux_In[146],read_Mux_In[147],read_Mux_In[148],read_Mux_In[149],read_Mux_In[150],read_Mux_In[151],read_Mux_In[152],read_Mux_In[153],read_Mux_In[154],read_Mux_In[155],read_Mux_In[156],read_Mux_In[157],read_Mux_In[158],read_Mux_In[159],read_Mux_In[160],read_Mux_In[161],read_Mux_In[162],read_Mux_In[163],read_Mux_In[164],read_Mux_In[165],read_Mux_In[166],read_Mux_In[167],read_Mux_In[168],read_Mux_In[169],read_Mux_In[170],read_Mux_In[171],read_Mux_In[172],read_Mux_In[173],read_Mux_In[174],read_Mux_In[175],read_Mux_In[176],read_Mux_In[177],read_Mux_In[178],read_Mux_In[179],read_Mux_In[180],read_Mux_In[181],read_Mux_In[182],read_Mux_In[183],read_Mux_In[184],read_Mux_In[185],read_Mux_In[186],read_Mux_In[187],read_Mux_In[188],read_Mux_In[189],read_Mux_In[190],read_Mux_In[191]}),
.\INFERRED_GEN.icount_out_reg[0]_0 (AXI4_LITE_I_n_30),
.\INFERRED_GEN.icount_out_reg[10] (AXI4_LITE_I_n_40),
.\INFERRED_GEN.icount_out_reg[11] (AXI4_LITE_I_n_41),
.\INFERRED_GEN.icount_out_reg[12] (AXI4_LITE_I_n_42),
.\INFERRED_GEN.icount_out_reg[13] (AXI4_LITE_I_n_43),
.\INFERRED_GEN.icount_out_reg[14] (AXI4_LITE_I_n_44),
.\INFERRED_GEN.icount_out_reg[15] (AXI4_LITE_I_n_45),
.\INFERRED_GEN.icount_out_reg[16] (AXI4_LITE_I_n_46),
.\INFERRED_GEN.icount_out_reg[17] (AXI4_LITE_I_n_47),
.\INFERRED_GEN.icount_out_reg[18] (AXI4_LITE_I_n_48),
.\INFERRED_GEN.icount_out_reg[19] (AXI4_LITE_I_n_49),
.\INFERRED_GEN.icount_out_reg[1] (AXI4_LITE_I_n_31),
.\INFERRED_GEN.icount_out_reg[20] (AXI4_LITE_I_n_50),
.\INFERRED_GEN.icount_out_reg[21] (AXI4_LITE_I_n_51),
.\INFERRED_GEN.icount_out_reg[22] (AXI4_LITE_I_n_52),
.\INFERRED_GEN.icount_out_reg[23] (AXI4_LITE_I_n_53),
.\INFERRED_GEN.icount_out_reg[24] (AXI4_LITE_I_n_54),
.\INFERRED_GEN.icount_out_reg[25] (AXI4_LITE_I_n_55),
.\INFERRED_GEN.icount_out_reg[26] (AXI4_LITE_I_n_56),
.\INFERRED_GEN.icount_out_reg[27] (AXI4_LITE_I_n_57),
.\INFERRED_GEN.icount_out_reg[28] (AXI4_LITE_I_n_58),
.\INFERRED_GEN.icount_out_reg[29] (AXI4_LITE_I_n_59),
.\INFERRED_GEN.icount_out_reg[2] (AXI4_LITE_I_n_32),
.\INFERRED_GEN.icount_out_reg[30] (AXI4_LITE_I_n_60),
.\INFERRED_GEN.icount_out_reg[3] (AXI4_LITE_I_n_33),
.\INFERRED_GEN.icount_out_reg[4] (AXI4_LITE_I_n_34),
.\INFERRED_GEN.icount_out_reg[5] (AXI4_LITE_I_n_35),
.\INFERRED_GEN.icount_out_reg[6] (AXI4_LITE_I_n_36),
.\INFERRED_GEN.icount_out_reg[7] (AXI4_LITE_I_n_37),
.\INFERRED_GEN.icount_out_reg[8] (AXI4_LITE_I_n_38),
.\INFERRED_GEN.icount_out_reg[9] (AXI4_LITE_I_n_39),
.\LOAD_REG_GEN[20].LOAD_REG_I (AXI4_LITE_I_n_27),
.\TCSR0_GENERATE[24].TCSR0_FF_I (AXI4_LITE_I_n_28),
.\TCSR1_GENERATE[24].TCSR1_FF_I (AXI4_LITE_I_n_29),
.bus2ip_reset(bus2ip_reset),
.bus2ip_wrce({bus2ip_wrce[0],bus2ip_wrce[4]}),
.bus2ip_wrce__0(bus2ip_wrce__0),
.capturetrig0(capturetrig0),
.capturetrig1(capturetrig1),
.freeze(freeze),
.generateout0(generateout0),
.generateout1(generateout1),
.interrupt(interrupt),
.pair0_Select(\TIMER_CONTROL_I/pair0_Select ),
.pwm0(pwm0),
.read_done1(\TIMER_CONTROL_I/read_done1 ),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata({s_axi_wdata[11:9],s_axi_wdata[6:0]}));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module zqynq_lab_1_design_axi_timer_0_1_cdc_sync
(captureTrig0_d0,
read_Mux_In,
capturetrig0,
s_axi_aclk);
output captureTrig0_d0;
input [0:0]read_Mux_In;
input capturetrig0;
input s_axi_aclk;
wire CaptureTrig0_int;
wire captureTrig0_d0;
wire capturetrig0;
wire [0:0]read_Mux_In;
wire s_axi_aclk;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(capturetrig0),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(CaptureTrig0_int),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
captureTrig0_d_i_1
(.I0(read_Mux_In),
.I1(CaptureTrig0_int),
.O(captureTrig0_d0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1
(captureTrig1_d0,
read_Mux_In,
capturetrig1,
s_axi_aclk);
output captureTrig1_d0;
input [0:0]read_Mux_In;
input capturetrig1;
input s_axi_aclk;
wire CaptureTrig1_int;
wire captureTrig1_d0;
wire capturetrig1;
wire [0:0]read_Mux_In;
wire s_axi_aclk;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(capturetrig1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(CaptureTrig1_int),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
captureTrig1_d_i_1
(.I0(read_Mux_In),
.I1(CaptureTrig1_int),
.O(captureTrig1_d0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2
(E,
\INFERRED_GEN.icount_out_reg[0] ,
S,
\INFERRED_GEN.icount_out_reg[4] ,
\TCSR0_GENERATE[20].TCSR0_FF_I ,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
counter_TC,
read_Mux_In,
generateOutPre0,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
Load_Counter_Reg030_out,
Load_Counter_Reg031_out,
Load_Counter_Reg0__0,
Load_Counter_Reg028_out,
\INFERRED_GEN.icount_out_reg[1] ,
freeze,
s_axi_aclk);
output [0:0]E;
output [0:0]\INFERRED_GEN.icount_out_reg[0] ;
output [0:0]S;
output [0:0]\INFERRED_GEN.icount_out_reg[4] ;
input \TCSR0_GENERATE[20].TCSR0_FF_I ;
input \TCSR0_GENERATE[24].TCSR0_FF_I ;
input [0:1]counter_TC;
input [7:0]read_Mux_In;
input generateOutPre0;
input \TCSR1_GENERATE[24].TCSR1_FF_I ;
input Load_Counter_Reg030_out;
input Load_Counter_Reg031_out;
input Load_Counter_Reg0__0;
input Load_Counter_Reg028_out;
input [1:0]\INFERRED_GEN.icount_out_reg[1] ;
input freeze;
input s_axi_aclk;
wire Counter_En041_out__2;
wire Counter_En043_out__0;
wire Counter_En045_out__1;
wire Counter_En0__4;
wire [0:0]E;
wire Freeze_int;
wire [0:0]\INFERRED_GEN.icount_out_reg[0] ;
wire [1:0]\INFERRED_GEN.icount_out_reg[1] ;
wire [0:0]\INFERRED_GEN.icount_out_reg[4] ;
wire Load_Counter_Reg028_out;
wire Load_Counter_Reg030_out;
wire Load_Counter_Reg031_out;
wire Load_Counter_Reg0__0;
wire [0:0]S;
wire \TCSR0_GENERATE[20].TCSR0_FF_I ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire [0:1]counter_En;
wire [0:1]counter_TC;
wire freeze;
wire generateOutPre0;
wire [7:0]read_Mux_In;
wire s_axi_aclk;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(freeze),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(Freeze_int),
.R(1'b0));
LUT5 #(
.INIT(32'hFCFFFCAA))
\INFERRED_GEN.icount_out[31]_i_1
(.I0(Load_Counter_Reg030_out),
.I1(Load_Counter_Reg031_out),
.I2(Counter_En043_out__0),
.I3(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.I4(Counter_En041_out__2),
.O(E));
LUT5 #(
.INIT(32'hFCFFFCAA))
\INFERRED_GEN.icount_out[31]_i_1__0
(.I0(Load_Counter_Reg0__0),
.I1(Load_Counter_Reg028_out),
.I2(Counter_En045_out__1),
.I3(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.I4(Counter_En0__4),
.O(\INFERRED_GEN.icount_out_reg[0] ));
LUT5 #(
.INIT(32'h00FB0000))
\INFERRED_GEN.icount_out[31]_i_5
(.I0(read_Mux_In[4]),
.I1(counter_TC[1]),
.I2(read_Mux_In[6]),
.I3(Freeze_int),
.I4(\TCSR0_GENERATE[24].TCSR0_FF_I ),
.O(Counter_En043_out__0));
LUT6 #(
.INIT(64'h4040404040004040))
\INFERRED_GEN.icount_out[31]_i_5__0
(.I0(Freeze_int),
.I1(\TCSR0_GENERATE[24].TCSR0_FF_I ),
.I2(generateOutPre0),
.I3(read_Mux_In[6]),
.I4(counter_TC[1]),
.I5(read_Mux_In[4]),
.O(Counter_En045_out__1));
LUT6 #(
.INIT(64'h4444444444444404))
\INFERRED_GEN.icount_out[31]_i_6
(.I0(Freeze_int),
.I1(\TCSR0_GENERATE[24].TCSR0_FF_I ),
.I2(counter_TC[0]),
.I3(read_Mux_In[7]),
.I4(read_Mux_In[6]),
.I5(read_Mux_In[4]),
.O(Counter_En041_out__2));
LUT6 #(
.INIT(64'h2222222222202222))
\INFERRED_GEN.icount_out[31]_i_6__0
(.I0(\TCSR1_GENERATE[24].TCSR1_FF_I ),
.I1(Freeze_int),
.I2(read_Mux_In[3]),
.I3(read_Mux_In[2]),
.I4(counter_TC[1]),
.I5(read_Mux_In[0]),
.O(Counter_En0__4));
LUT3 #(
.INIT(8'h6A))
icount_out0_carry_i_5
(.I0(\INFERRED_GEN.icount_out_reg[1] [1]),
.I1(counter_En[0]),
.I2(read_Mux_In[5]),
.O(S));
LUT5 #(
.INIT(32'h6A666AAA))
icount_out0_carry_i_5__0
(.I0(\INFERRED_GEN.icount_out_reg[1] [0]),
.I1(counter_En[1]),
.I2(read_Mux_In[5]),
.I3(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.I4(read_Mux_In[1]),
.O(\INFERRED_GEN.icount_out_reg[4] ));
MUXF7 icount_out0_carry_i_6
(.I0(Counter_En041_out__2),
.I1(Counter_En043_out__0),
.O(counter_En[0]),
.S(\TCSR0_GENERATE[20].TCSR0_FF_I ));
MUXF7 icount_out0_carry_i_6__0
(.I0(Counter_En0__4),
.I1(Counter_En045_out__1),
.O(counter_En[1]),
.S(\TCSR0_GENERATE[20].TCSR0_FF_I ));
endmodule
(* ORIG_REF_NAME = "count_module" *)
module zqynq_lab_1_design_axi_timer_0_1_count_module
(\INFERRED_GEN.icount_out_reg[31] ,
read_Mux_In,
generateOutPre0_reg,
counter_TC,
s_axi_aresetn_0,
\TCSR0_GENERATE[27].TCSR0_FF_I ,
D_1,
s_axi_aclk,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ,
S,
load_Counter_Reg,
Q,
E,
s_axi_aresetn);
output [52:0]\INFERRED_GEN.icount_out_reg[31] ;
output [10:0]read_Mux_In;
output generateOutPre0_reg;
output [0:0]counter_TC;
input s_axi_aresetn_0;
input \TCSR0_GENERATE[27].TCSR0_FF_I ;
input D_1;
input s_axi_aclk;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ;
input [0:0]S;
input [0:0]load_Counter_Reg;
input [0:0]Q;
input [0:0]E;
input s_axi_aresetn;
wire D_1;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ;
wire [52:0]\INFERRED_GEN.icount_out_reg[31] ;
wire [0:0]Q;
wire [0:0]S;
wire \TCSR0_GENERATE[27].TCSR0_FF_I ;
wire [0:0]counter_TC;
wire generateOutPre0_reg;
wire [0:0]load_Counter_Reg;
wire [10:0]read_Mux_In;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
zqynq_lab_1_design_axi_timer_0_1_counter_f_3 COUNTER_I
(.E(E),
.\LOAD_REG_GEN[0].LOAD_REG_I (\INFERRED_GEN.icount_out_reg[31] [31:0]),
.\LOAD_REG_GEN[0].LOAD_REG_I_0 (\INFERRED_GEN.icount_out_reg[31] [52:32]),
.Q(Q),
.S(S),
.counter_TC(counter_TC),
.generateOutPre0_reg(generateOutPre0_reg),
.load_Counter_Reg(load_Counter_Reg),
.read_Mux_In(read_Mux_In),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[0].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(D_1),
.Q(\INFERRED_GEN.icount_out_reg[31] [52]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[10].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [42]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[11].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [41]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[12].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [40]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[13].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [39]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[14].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [38]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[15].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [37]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[16].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [36]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[17].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [35]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[18].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [34]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[19].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [33]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[1].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.Q(\INFERRED_GEN.icount_out_reg[31] [51]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[20].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [32]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[21].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ),
.Q(read_Mux_In[10]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[22].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ),
.Q(read_Mux_In[9]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[23].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ),
.Q(read_Mux_In[8]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[24].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ),
.Q(read_Mux_In[7]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[25].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ),
.Q(read_Mux_In[6]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[26].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ),
.Q(read_Mux_In[5]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[27].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ),
.Q(read_Mux_In[4]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[28].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ),
.Q(read_Mux_In[3]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[29].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ),
.Q(read_Mux_In[2]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[2].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [50]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[30].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ),
.Q(read_Mux_In[1]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[31].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ),
.Q(read_Mux_In[0]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[3].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [49]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[4].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [48]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[5].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [47]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[6].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [46]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[7].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [45]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[8].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [44]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[9].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [43]),
.R(s_axi_aresetn_0));
endmodule
(* ORIG_REF_NAME = "count_module" *)
module zqynq_lab_1_design_axi_timer_0_1_count_module_0
(\INFERRED_GEN.icount_out_reg[31] ,
Q,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[1] ,
\s_axi_rdata_i_reg[2] ,
\s_axi_rdata_i_reg[3] ,
\s_axi_rdata_i_reg[4] ,
\s_axi_rdata_i_reg[5] ,
\s_axi_rdata_i_reg[6] ,
\s_axi_rdata_i_reg[7] ,
\s_axi_rdata_i_reg[8] ,
\s_axi_rdata_i_reg[9] ,
\s_axi_rdata_i_reg[10] ,
\s_axi_rdata_i_reg[11] ,
\s_axi_rdata_i_reg[12] ,
\s_axi_rdata_i_reg[13] ,
\s_axi_rdata_i_reg[14] ,
\s_axi_rdata_i_reg[15] ,
\s_axi_rdata_i_reg[16] ,
\s_axi_rdata_i_reg[17] ,
\s_axi_rdata_i_reg[18] ,
\s_axi_rdata_i_reg[19] ,
\s_axi_rdata_i_reg[20] ,
\s_axi_rdata_i_reg[21] ,
\s_axi_rdata_i_reg[22] ,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[24] ,
\s_axi_rdata_i_reg[25] ,
\s_axi_rdata_i_reg[26] ,
\s_axi_rdata_i_reg[27] ,
\s_axi_rdata_i_reg[28] ,
\s_axi_rdata_i_reg[29] ,
\s_axi_rdata_i_reg[30] ,
\s_axi_rdata_i_reg[31] ,
generateOutPre1_reg,
counter_TC,
\TCSR0_GENERATE[20].TCSR0_FF_I ,
D_2,
s_axi_aclk,
\INFERRED_GEN.icount_out_reg[30] ,
\INFERRED_GEN.icount_out_reg[29] ,
\INFERRED_GEN.icount_out_reg[28] ,
\INFERRED_GEN.icount_out_reg[27] ,
\INFERRED_GEN.icount_out_reg[26] ,
\INFERRED_GEN.icount_out_reg[25] ,
\INFERRED_GEN.icount_out_reg[24] ,
\INFERRED_GEN.icount_out_reg[23] ,
\INFERRED_GEN.icount_out_reg[22] ,
\INFERRED_GEN.icount_out_reg[21] ,
\INFERRED_GEN.icount_out_reg[20] ,
\INFERRED_GEN.icount_out_reg[19] ,
\INFERRED_GEN.icount_out_reg[18] ,
\INFERRED_GEN.icount_out_reg[17] ,
\INFERRED_GEN.icount_out_reg[16] ,
\INFERRED_GEN.icount_out_reg[15] ,
\INFERRED_GEN.icount_out_reg[14] ,
\INFERRED_GEN.icount_out_reg[13] ,
\INFERRED_GEN.icount_out_reg[12] ,
\INFERRED_GEN.icount_out_reg[11] ,
\INFERRED_GEN.icount_out_reg[10] ,
\INFERRED_GEN.icount_out_reg[9] ,
\INFERRED_GEN.icount_out_reg[8] ,
\INFERRED_GEN.icount_out_reg[7] ,
\INFERRED_GEN.icount_out_reg[6] ,
\INFERRED_GEN.icount_out_reg[5] ,
\INFERRED_GEN.icount_out_reg[4] ,
\INFERRED_GEN.icount_out_reg[3] ,
\INFERRED_GEN.icount_out_reg[2] ,
\INFERRED_GEN.icount_out_reg[1] ,
\INFERRED_GEN.icount_out_reg[0] ,
S,
load_Counter_Reg,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ,
\INFERRED_GEN.icount_out_reg[31]_0 ,
\counter_TC_Reg_reg[1] ,
E);
output \INFERRED_GEN.icount_out_reg[31] ;
output [31:0]Q;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[1] ;
output \s_axi_rdata_i_reg[2] ;
output \s_axi_rdata_i_reg[3] ;
output \s_axi_rdata_i_reg[4] ;
output \s_axi_rdata_i_reg[5] ;
output \s_axi_rdata_i_reg[6] ;
output \s_axi_rdata_i_reg[7] ;
output \s_axi_rdata_i_reg[8] ;
output \s_axi_rdata_i_reg[9] ;
output \s_axi_rdata_i_reg[10] ;
output \s_axi_rdata_i_reg[11] ;
output \s_axi_rdata_i_reg[12] ;
output \s_axi_rdata_i_reg[13] ;
output \s_axi_rdata_i_reg[14] ;
output \s_axi_rdata_i_reg[15] ;
output \s_axi_rdata_i_reg[16] ;
output \s_axi_rdata_i_reg[17] ;
output \s_axi_rdata_i_reg[18] ;
output \s_axi_rdata_i_reg[19] ;
output \s_axi_rdata_i_reg[20] ;
output \s_axi_rdata_i_reg[21] ;
output \s_axi_rdata_i_reg[22] ;
output \s_axi_rdata_i_reg[23] ;
output \s_axi_rdata_i_reg[24] ;
output \s_axi_rdata_i_reg[25] ;
output \s_axi_rdata_i_reg[26] ;
output \s_axi_rdata_i_reg[27] ;
output \s_axi_rdata_i_reg[28] ;
output \s_axi_rdata_i_reg[29] ;
output \s_axi_rdata_i_reg[30] ;
output \s_axi_rdata_i_reg[31] ;
output generateOutPre1_reg;
output [0:0]counter_TC;
input \TCSR0_GENERATE[20].TCSR0_FF_I ;
input D_2;
input s_axi_aclk;
input \INFERRED_GEN.icount_out_reg[30] ;
input \INFERRED_GEN.icount_out_reg[29] ;
input \INFERRED_GEN.icount_out_reg[28] ;
input \INFERRED_GEN.icount_out_reg[27] ;
input \INFERRED_GEN.icount_out_reg[26] ;
input \INFERRED_GEN.icount_out_reg[25] ;
input \INFERRED_GEN.icount_out_reg[24] ;
input \INFERRED_GEN.icount_out_reg[23] ;
input \INFERRED_GEN.icount_out_reg[22] ;
input \INFERRED_GEN.icount_out_reg[21] ;
input \INFERRED_GEN.icount_out_reg[20] ;
input \INFERRED_GEN.icount_out_reg[19] ;
input \INFERRED_GEN.icount_out_reg[18] ;
input \INFERRED_GEN.icount_out_reg[17] ;
input \INFERRED_GEN.icount_out_reg[16] ;
input \INFERRED_GEN.icount_out_reg[15] ;
input \INFERRED_GEN.icount_out_reg[14] ;
input \INFERRED_GEN.icount_out_reg[13] ;
input \INFERRED_GEN.icount_out_reg[12] ;
input \INFERRED_GEN.icount_out_reg[11] ;
input \INFERRED_GEN.icount_out_reg[10] ;
input \INFERRED_GEN.icount_out_reg[9] ;
input \INFERRED_GEN.icount_out_reg[8] ;
input \INFERRED_GEN.icount_out_reg[7] ;
input \INFERRED_GEN.icount_out_reg[6] ;
input \INFERRED_GEN.icount_out_reg[5] ;
input \INFERRED_GEN.icount_out_reg[4] ;
input \INFERRED_GEN.icount_out_reg[3] ;
input \INFERRED_GEN.icount_out_reg[2] ;
input \INFERRED_GEN.icount_out_reg[1] ;
input \INFERRED_GEN.icount_out_reg[0] ;
input [0:0]S;
input [0:0]load_Counter_Reg;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
input [31:0]\INFERRED_GEN.icount_out_reg[31]_0 ;
input [0:0]\counter_TC_Reg_reg[1] ;
input [0:0]E;
wire D_2;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
wire \INFERRED_GEN.icount_out_reg[0] ;
wire \INFERRED_GEN.icount_out_reg[10] ;
wire \INFERRED_GEN.icount_out_reg[11] ;
wire \INFERRED_GEN.icount_out_reg[12] ;
wire \INFERRED_GEN.icount_out_reg[13] ;
wire \INFERRED_GEN.icount_out_reg[14] ;
wire \INFERRED_GEN.icount_out_reg[15] ;
wire \INFERRED_GEN.icount_out_reg[16] ;
wire \INFERRED_GEN.icount_out_reg[17] ;
wire \INFERRED_GEN.icount_out_reg[18] ;
wire \INFERRED_GEN.icount_out_reg[19] ;
wire \INFERRED_GEN.icount_out_reg[1] ;
wire \INFERRED_GEN.icount_out_reg[20] ;
wire \INFERRED_GEN.icount_out_reg[21] ;
wire \INFERRED_GEN.icount_out_reg[22] ;
wire \INFERRED_GEN.icount_out_reg[23] ;
wire \INFERRED_GEN.icount_out_reg[24] ;
wire \INFERRED_GEN.icount_out_reg[25] ;
wire \INFERRED_GEN.icount_out_reg[26] ;
wire \INFERRED_GEN.icount_out_reg[27] ;
wire \INFERRED_GEN.icount_out_reg[28] ;
wire \INFERRED_GEN.icount_out_reg[29] ;
wire \INFERRED_GEN.icount_out_reg[2] ;
wire \INFERRED_GEN.icount_out_reg[30] ;
wire \INFERRED_GEN.icount_out_reg[31] ;
wire [31:0]\INFERRED_GEN.icount_out_reg[31]_0 ;
wire \INFERRED_GEN.icount_out_reg[3] ;
wire \INFERRED_GEN.icount_out_reg[4] ;
wire \INFERRED_GEN.icount_out_reg[5] ;
wire \INFERRED_GEN.icount_out_reg[6] ;
wire \INFERRED_GEN.icount_out_reg[7] ;
wire \INFERRED_GEN.icount_out_reg[8] ;
wire \INFERRED_GEN.icount_out_reg[9] ;
wire [31:0]Q;
wire [0:0]S;
wire \TCSR0_GENERATE[20].TCSR0_FF_I ;
wire [0:0]counter_TC;
wire [0:0]\counter_TC_Reg_reg[1] ;
wire generateOutPre1_reg;
wire [0:0]load_Counter_Reg;
wire [96:127]read_Mux_In;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[11] ;
wire \s_axi_rdata_i_reg[12] ;
wire \s_axi_rdata_i_reg[13] ;
wire \s_axi_rdata_i_reg[14] ;
wire \s_axi_rdata_i_reg[15] ;
wire \s_axi_rdata_i_reg[16] ;
wire \s_axi_rdata_i_reg[17] ;
wire \s_axi_rdata_i_reg[18] ;
wire \s_axi_rdata_i_reg[19] ;
wire \s_axi_rdata_i_reg[1] ;
wire \s_axi_rdata_i_reg[20] ;
wire \s_axi_rdata_i_reg[21] ;
wire \s_axi_rdata_i_reg[22] ;
wire \s_axi_rdata_i_reg[23] ;
wire \s_axi_rdata_i_reg[24] ;
wire \s_axi_rdata_i_reg[25] ;
wire \s_axi_rdata_i_reg[26] ;
wire \s_axi_rdata_i_reg[27] ;
wire \s_axi_rdata_i_reg[28] ;
wire \s_axi_rdata_i_reg[29] ;
wire \s_axi_rdata_i_reg[2] ;
wire \s_axi_rdata_i_reg[30] ;
wire \s_axi_rdata_i_reg[31] ;
wire \s_axi_rdata_i_reg[3] ;
wire \s_axi_rdata_i_reg[4] ;
wire \s_axi_rdata_i_reg[5] ;
wire \s_axi_rdata_i_reg[6] ;
wire \s_axi_rdata_i_reg[7] ;
wire \s_axi_rdata_i_reg[8] ;
wire \s_axi_rdata_i_reg[9] ;
zqynq_lab_1_design_axi_timer_0_1_counter_f COUNTER_I
(.E(E),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] (\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] (\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.\INFERRED_GEN.icount_out_reg[31]_0 (\INFERRED_GEN.icount_out_reg[31]_0 ),
.Q(Q),
.S(S),
.SR(\INFERRED_GEN.icount_out_reg[31] ),
.counter_TC(counter_TC),
.\counter_TC_Reg_reg[1] (\counter_TC_Reg_reg[1] ),
.generateOutPre1_reg(generateOutPre1_reg),
.load_Counter_Reg(load_Counter_Reg),
.read_Mux_In({read_Mux_In[96],read_Mux_In[97],read_Mux_In[98],read_Mux_In[99],read_Mux_In[100],read_Mux_In[101],read_Mux_In[102],read_Mux_In[103],read_Mux_In[104],read_Mux_In[105],read_Mux_In[106],read_Mux_In[107],read_Mux_In[108],read_Mux_In[109],read_Mux_In[110],read_Mux_In[111],read_Mux_In[112],read_Mux_In[113],read_Mux_In[114],read_Mux_In[115],read_Mux_In[116],read_Mux_In[117],read_Mux_In[118],read_Mux_In[119],read_Mux_In[120],read_Mux_In[121],read_Mux_In[122],read_Mux_In[123],read_Mux_In[124],read_Mux_In[125],read_Mux_In[126],read_Mux_In[127]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.\s_axi_rdata_i_reg[0] (\s_axi_rdata_i_reg[0] ),
.\s_axi_rdata_i_reg[10] (\s_axi_rdata_i_reg[10] ),
.\s_axi_rdata_i_reg[11] (\s_axi_rdata_i_reg[11] ),
.\s_axi_rdata_i_reg[12] (\s_axi_rdata_i_reg[12] ),
.\s_axi_rdata_i_reg[13] (\s_axi_rdata_i_reg[13] ),
.\s_axi_rdata_i_reg[14] (\s_axi_rdata_i_reg[14] ),
.\s_axi_rdata_i_reg[15] (\s_axi_rdata_i_reg[15] ),
.\s_axi_rdata_i_reg[16] (\s_axi_rdata_i_reg[16] ),
.\s_axi_rdata_i_reg[17] (\s_axi_rdata_i_reg[17] ),
.\s_axi_rdata_i_reg[18] (\s_axi_rdata_i_reg[18] ),
.\s_axi_rdata_i_reg[19] (\s_axi_rdata_i_reg[19] ),
.\s_axi_rdata_i_reg[1] (\s_axi_rdata_i_reg[1] ),
.\s_axi_rdata_i_reg[20] (\s_axi_rdata_i_reg[20] ),
.\s_axi_rdata_i_reg[21] (\s_axi_rdata_i_reg[21] ),
.\s_axi_rdata_i_reg[22] (\s_axi_rdata_i_reg[22] ),
.\s_axi_rdata_i_reg[23] (\s_axi_rdata_i_reg[23] ),
.\s_axi_rdata_i_reg[24] (\s_axi_rdata_i_reg[24] ),
.\s_axi_rdata_i_reg[25] (\s_axi_rdata_i_reg[25] ),
.\s_axi_rdata_i_reg[26] (\s_axi_rdata_i_reg[26] ),
.\s_axi_rdata_i_reg[27] (\s_axi_rdata_i_reg[27] ),
.\s_axi_rdata_i_reg[28] (\s_axi_rdata_i_reg[28] ),
.\s_axi_rdata_i_reg[29] (\s_axi_rdata_i_reg[29] ),
.\s_axi_rdata_i_reg[2] (\s_axi_rdata_i_reg[2] ),
.\s_axi_rdata_i_reg[30] (\s_axi_rdata_i_reg[30] ),
.\s_axi_rdata_i_reg[31] (\s_axi_rdata_i_reg[31] ),
.\s_axi_rdata_i_reg[3] (\s_axi_rdata_i_reg[3] ),
.\s_axi_rdata_i_reg[4] (\s_axi_rdata_i_reg[4] ),
.\s_axi_rdata_i_reg[5] (\s_axi_rdata_i_reg[5] ),
.\s_axi_rdata_i_reg[6] (\s_axi_rdata_i_reg[6] ),
.\s_axi_rdata_i_reg[7] (\s_axi_rdata_i_reg[7] ),
.\s_axi_rdata_i_reg[8] (\s_axi_rdata_i_reg[8] ),
.\s_axi_rdata_i_reg[9] (\s_axi_rdata_i_reg[9] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[0].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(D_2),
.Q(read_Mux_In[96]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[10].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[21] ),
.Q(read_Mux_In[106]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[11].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[20] ),
.Q(read_Mux_In[107]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[12].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[19] ),
.Q(read_Mux_In[108]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[13].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[18] ),
.Q(read_Mux_In[109]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[14].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[17] ),
.Q(read_Mux_In[110]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[15].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[16] ),
.Q(read_Mux_In[111]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[16].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[15] ),
.Q(read_Mux_In[112]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[17].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[14] ),
.Q(read_Mux_In[113]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[18].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[13] ),
.Q(read_Mux_In[114]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[19].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[12] ),
.Q(read_Mux_In[115]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[1].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[30] ),
.Q(read_Mux_In[97]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[20].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[11] ),
.Q(read_Mux_In[116]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[21].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[10] ),
.Q(read_Mux_In[117]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[22].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[9] ),
.Q(read_Mux_In[118]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[23].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[8] ),
.Q(read_Mux_In[119]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[24].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[7] ),
.Q(read_Mux_In[120]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[25].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[6] ),
.Q(read_Mux_In[121]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[26].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[5] ),
.Q(read_Mux_In[122]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[27].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[4] ),
.Q(read_Mux_In[123]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[28].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[3] ),
.Q(read_Mux_In[124]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[29].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[2] ),
.Q(read_Mux_In[125]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[2].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[29] ),
.Q(read_Mux_In[98]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[30].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[1] ),
.Q(read_Mux_In[126]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[31].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[0] ),
.Q(read_Mux_In[127]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[3].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[28] ),
.Q(read_Mux_In[99]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[4].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[27] ),
.Q(read_Mux_In[100]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[5].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[26] ),
.Q(read_Mux_In[101]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[6].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[25] ),
.Q(read_Mux_In[102]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[7].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[24] ),
.Q(read_Mux_In[103]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[8].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[23] ),
.Q(read_Mux_In[104]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[9].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[22] ),
.Q(read_Mux_In[105]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
endmodule
(* ORIG_REF_NAME = "counter_f" *)
module zqynq_lab_1_design_axi_timer_0_1_counter_f
(Q,
SR,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[1] ,
\s_axi_rdata_i_reg[2] ,
\s_axi_rdata_i_reg[3] ,
\s_axi_rdata_i_reg[4] ,
\s_axi_rdata_i_reg[5] ,
\s_axi_rdata_i_reg[6] ,
\s_axi_rdata_i_reg[7] ,
\s_axi_rdata_i_reg[8] ,
\s_axi_rdata_i_reg[9] ,
\s_axi_rdata_i_reg[10] ,
\s_axi_rdata_i_reg[11] ,
\s_axi_rdata_i_reg[12] ,
\s_axi_rdata_i_reg[13] ,
\s_axi_rdata_i_reg[14] ,
\s_axi_rdata_i_reg[15] ,
\s_axi_rdata_i_reg[16] ,
\s_axi_rdata_i_reg[17] ,
\s_axi_rdata_i_reg[18] ,
\s_axi_rdata_i_reg[19] ,
\s_axi_rdata_i_reg[20] ,
\s_axi_rdata_i_reg[21] ,
\s_axi_rdata_i_reg[22] ,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[24] ,
\s_axi_rdata_i_reg[25] ,
\s_axi_rdata_i_reg[26] ,
\s_axi_rdata_i_reg[27] ,
\s_axi_rdata_i_reg[28] ,
\s_axi_rdata_i_reg[29] ,
\s_axi_rdata_i_reg[30] ,
\s_axi_rdata_i_reg[31] ,
generateOutPre1_reg,
counter_TC,
S,
read_Mux_In,
load_Counter_Reg,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ,
\INFERRED_GEN.icount_out_reg[31]_0 ,
\counter_TC_Reg_reg[1] ,
E,
s_axi_aclk);
output [31:0]Q;
output [0:0]SR;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[1] ;
output \s_axi_rdata_i_reg[2] ;
output \s_axi_rdata_i_reg[3] ;
output \s_axi_rdata_i_reg[4] ;
output \s_axi_rdata_i_reg[5] ;
output \s_axi_rdata_i_reg[6] ;
output \s_axi_rdata_i_reg[7] ;
output \s_axi_rdata_i_reg[8] ;
output \s_axi_rdata_i_reg[9] ;
output \s_axi_rdata_i_reg[10] ;
output \s_axi_rdata_i_reg[11] ;
output \s_axi_rdata_i_reg[12] ;
output \s_axi_rdata_i_reg[13] ;
output \s_axi_rdata_i_reg[14] ;
output \s_axi_rdata_i_reg[15] ;
output \s_axi_rdata_i_reg[16] ;
output \s_axi_rdata_i_reg[17] ;
output \s_axi_rdata_i_reg[18] ;
output \s_axi_rdata_i_reg[19] ;
output \s_axi_rdata_i_reg[20] ;
output \s_axi_rdata_i_reg[21] ;
output \s_axi_rdata_i_reg[22] ;
output \s_axi_rdata_i_reg[23] ;
output \s_axi_rdata_i_reg[24] ;
output \s_axi_rdata_i_reg[25] ;
output \s_axi_rdata_i_reg[26] ;
output \s_axi_rdata_i_reg[27] ;
output \s_axi_rdata_i_reg[28] ;
output \s_axi_rdata_i_reg[29] ;
output \s_axi_rdata_i_reg[30] ;
output \s_axi_rdata_i_reg[31] ;
output generateOutPre1_reg;
output [0:0]counter_TC;
input [0:0]S;
input [31:0]read_Mux_In;
input [0:0]load_Counter_Reg;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
input [31:0]\INFERRED_GEN.icount_out_reg[31]_0 ;
input [0:0]\counter_TC_Reg_reg[1] ;
input [0:0]E;
input s_axi_aclk;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
wire \INFERRED_GEN.icount_out[0]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[10]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[11]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[12]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[13]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[14]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[15]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[16]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[17]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[18]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[19]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[1]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[20]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[21]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[22]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[23]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[24]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[25]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[26]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[27]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[28]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[29]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[2]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[30]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[31]_i_2_n_0 ;
wire \INFERRED_GEN.icount_out[32]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[3]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[4]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[5]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[6]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[7]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[8]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[9]_i_1_n_0 ;
wire [31:0]\INFERRED_GEN.icount_out_reg[31]_0 ;
wire [31:0]Q;
wire [0:0]S;
wire [0:0]SR;
wire [0:0]counter_TC;
wire [0:0]\counter_TC_Reg_reg[1] ;
wire generateOutPre1_reg;
wire icount_out0_carry__0_i_1_n_0;
wire icount_out0_carry__0_i_2_n_0;
wire icount_out0_carry__0_i_3_n_0;
wire icount_out0_carry__0_i_4_n_0;
wire icount_out0_carry__0_n_0;
wire icount_out0_carry__0_n_1;
wire icount_out0_carry__0_n_2;
wire icount_out0_carry__0_n_3;
wire icount_out0_carry__0_n_4;
wire icount_out0_carry__0_n_5;
wire icount_out0_carry__0_n_6;
wire icount_out0_carry__0_n_7;
wire icount_out0_carry__1_i_1_n_0;
wire icount_out0_carry__1_i_2_n_0;
wire icount_out0_carry__1_i_3_n_0;
wire icount_out0_carry__1_i_4_n_0;
wire icount_out0_carry__1_n_0;
wire icount_out0_carry__1_n_1;
wire icount_out0_carry__1_n_2;
wire icount_out0_carry__1_n_3;
wire icount_out0_carry__1_n_4;
wire icount_out0_carry__1_n_5;
wire icount_out0_carry__1_n_6;
wire icount_out0_carry__1_n_7;
wire icount_out0_carry__2_i_1_n_0;
wire icount_out0_carry__2_i_2_n_0;
wire icount_out0_carry__2_i_3_n_0;
wire icount_out0_carry__2_i_4_n_0;
wire icount_out0_carry__2_n_0;
wire icount_out0_carry__2_n_1;
wire icount_out0_carry__2_n_2;
wire icount_out0_carry__2_n_3;
wire icount_out0_carry__2_n_4;
wire icount_out0_carry__2_n_5;
wire icount_out0_carry__2_n_6;
wire icount_out0_carry__2_n_7;
wire icount_out0_carry__3_i_1_n_0;
wire icount_out0_carry__3_i_2_n_0;
wire icount_out0_carry__3_i_3_n_0;
wire icount_out0_carry__3_i_4_n_0;
wire icount_out0_carry__3_n_0;
wire icount_out0_carry__3_n_1;
wire icount_out0_carry__3_n_2;
wire icount_out0_carry__3_n_3;
wire icount_out0_carry__3_n_4;
wire icount_out0_carry__3_n_5;
wire icount_out0_carry__3_n_6;
wire icount_out0_carry__3_n_7;
wire icount_out0_carry__4_i_1_n_0;
wire icount_out0_carry__4_i_2_n_0;
wire icount_out0_carry__4_i_3_n_0;
wire icount_out0_carry__4_i_4_n_0;
wire icount_out0_carry__4_n_0;
wire icount_out0_carry__4_n_1;
wire icount_out0_carry__4_n_2;
wire icount_out0_carry__4_n_3;
wire icount_out0_carry__4_n_4;
wire icount_out0_carry__4_n_5;
wire icount_out0_carry__4_n_6;
wire icount_out0_carry__4_n_7;
wire icount_out0_carry__5_i_1_n_0;
wire icount_out0_carry__5_i_2_n_0;
wire icount_out0_carry__5_i_3_n_0;
wire icount_out0_carry__5_i_4_n_0;
wire icount_out0_carry__5_n_0;
wire icount_out0_carry__5_n_1;
wire icount_out0_carry__5_n_2;
wire icount_out0_carry__5_n_3;
wire icount_out0_carry__5_n_4;
wire icount_out0_carry__5_n_5;
wire icount_out0_carry__5_n_6;
wire icount_out0_carry__5_n_7;
wire icount_out0_carry__6_i_1_n_0;
wire icount_out0_carry__6_i_2_n_0;
wire icount_out0_carry__6_i_3_n_0;
wire icount_out0_carry__6_i_4_n_0;
wire icount_out0_carry__6_n_1;
wire icount_out0_carry__6_n_2;
wire icount_out0_carry__6_n_3;
wire icount_out0_carry__6_n_4;
wire icount_out0_carry__6_n_5;
wire icount_out0_carry__6_n_6;
wire icount_out0_carry__6_n_7;
wire icount_out0_carry_i_1_n_0;
wire icount_out0_carry_i_2_n_0;
wire icount_out0_carry_i_3_n_0;
wire icount_out0_carry_i_4_n_0;
wire icount_out0_carry_n_0;
wire icount_out0_carry_n_1;
wire icount_out0_carry_n_2;
wire icount_out0_carry_n_3;
wire icount_out0_carry_n_4;
wire icount_out0_carry_n_5;
wire icount_out0_carry_n_6;
wire icount_out0_carry_n_7;
wire [0:0]load_Counter_Reg;
wire [31:0]read_Mux_In;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[11] ;
wire \s_axi_rdata_i_reg[12] ;
wire \s_axi_rdata_i_reg[13] ;
wire \s_axi_rdata_i_reg[14] ;
wire \s_axi_rdata_i_reg[15] ;
wire \s_axi_rdata_i_reg[16] ;
wire \s_axi_rdata_i_reg[17] ;
wire \s_axi_rdata_i_reg[18] ;
wire \s_axi_rdata_i_reg[19] ;
wire \s_axi_rdata_i_reg[1] ;
wire \s_axi_rdata_i_reg[20] ;
wire \s_axi_rdata_i_reg[21] ;
wire \s_axi_rdata_i_reg[22] ;
wire \s_axi_rdata_i_reg[23] ;
wire \s_axi_rdata_i_reg[24] ;
wire \s_axi_rdata_i_reg[25] ;
wire \s_axi_rdata_i_reg[26] ;
wire \s_axi_rdata_i_reg[27] ;
wire \s_axi_rdata_i_reg[28] ;
wire \s_axi_rdata_i_reg[29] ;
wire \s_axi_rdata_i_reg[2] ;
wire \s_axi_rdata_i_reg[30] ;
wire \s_axi_rdata_i_reg[31] ;
wire \s_axi_rdata_i_reg[3] ;
wire \s_axi_rdata_i_reg[4] ;
wire \s_axi_rdata_i_reg[5] ;
wire \s_axi_rdata_i_reg[6] ;
wire \s_axi_rdata_i_reg[7] ;
wire \s_axi_rdata_i_reg[8] ;
wire \s_axi_rdata_i_reg[9] ;
wire [3:3]NLW_icount_out0_carry__6_CO_UNCONNECTED;
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[31]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[31]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [31]),
.O(\s_axi_rdata_i_reg[31] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[21]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[21]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [21]),
.O(\s_axi_rdata_i_reg[21] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[20]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[20]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [20]),
.O(\s_axi_rdata_i_reg[20] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[19]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[19]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [19]),
.O(\s_axi_rdata_i_reg[19] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[18]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[18]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [18]),
.O(\s_axi_rdata_i_reg[18] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[17]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[17]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [17]),
.O(\s_axi_rdata_i_reg[17] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[16]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[16]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [16]),
.O(\s_axi_rdata_i_reg[16] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[15]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[15]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [15]),
.O(\s_axi_rdata_i_reg[15] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[14]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[14]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [14]),
.O(\s_axi_rdata_i_reg[14] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[13]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[13]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [13]),
.O(\s_axi_rdata_i_reg[13] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[12]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[12]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [12]),
.O(\s_axi_rdata_i_reg[12] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[30]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[30]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [30]),
.O(\s_axi_rdata_i_reg[30] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[11]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[11]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [11]),
.O(\s_axi_rdata_i_reg[11] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[10]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[10]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [10]),
.O(\s_axi_rdata_i_reg[10] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[9]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[9]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [9]),
.O(\s_axi_rdata_i_reg[9] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[8]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[8]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [8]),
.O(\s_axi_rdata_i_reg[8] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[7]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[7]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [7]),
.O(\s_axi_rdata_i_reg[7] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[6]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[6]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [6]),
.O(\s_axi_rdata_i_reg[6] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[5]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[5]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [5]),
.O(\s_axi_rdata_i_reg[5] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[4]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[4]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [4]),
.O(\s_axi_rdata_i_reg[4] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[3]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[3]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [3]),
.O(\s_axi_rdata_i_reg[3] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[2]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[2]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [2]),
.O(\s_axi_rdata_i_reg[2] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[29]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[29]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [29]),
.O(\s_axi_rdata_i_reg[29] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[1]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[1]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [1]),
.O(\s_axi_rdata_i_reg[1] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[0]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[0]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [0]),
.O(\s_axi_rdata_i_reg[0] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[28]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[28]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [28]),
.O(\s_axi_rdata_i_reg[28] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[27]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[27]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [27]),
.O(\s_axi_rdata_i_reg[27] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[26]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[26]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [26]),
.O(\s_axi_rdata_i_reg[26] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[25]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[25]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [25]),
.O(\s_axi_rdata_i_reg[25] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[24]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[24]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [24]),
.O(\s_axi_rdata_i_reg[24] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[23]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[23]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [23]),
.O(\s_axi_rdata_i_reg[23] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[22]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[22]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [22]),
.O(\s_axi_rdata_i_reg[22] ));
LUT1 #(
.INIT(2'h1))
GenerateOut0_i_1
(.I0(s_axi_aresetn),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hA3))
\INFERRED_GEN.icount_out[0]_i_1
(.I0(read_Mux_In[0]),
.I1(Q[0]),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[10]_i_1
(.I0(read_Mux_In[10]),
.I1(icount_out0_carry__1_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[11]_i_1
(.I0(read_Mux_In[11]),
.I1(icount_out0_carry__1_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[12]_i_1
(.I0(read_Mux_In[12]),
.I1(icount_out0_carry__1_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[13]_i_1
(.I0(read_Mux_In[13]),
.I1(icount_out0_carry__2_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[14]_i_1
(.I0(read_Mux_In[14]),
.I1(icount_out0_carry__2_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[15]_i_1
(.I0(read_Mux_In[15]),
.I1(icount_out0_carry__2_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[16]_i_1
(.I0(read_Mux_In[16]),
.I1(icount_out0_carry__2_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[17]_i_1
(.I0(read_Mux_In[17]),
.I1(icount_out0_carry__3_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[18]_i_1
(.I0(read_Mux_In[18]),
.I1(icount_out0_carry__3_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[19]_i_1
(.I0(read_Mux_In[19]),
.I1(icount_out0_carry__3_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[1]_i_1
(.I0(read_Mux_In[1]),
.I1(icount_out0_carry_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[20]_i_1
(.I0(read_Mux_In[20]),
.I1(icount_out0_carry__3_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[21]_i_1
(.I0(read_Mux_In[21]),
.I1(icount_out0_carry__4_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[22]_i_1
(.I0(read_Mux_In[22]),
.I1(icount_out0_carry__4_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[23]_i_1
(.I0(read_Mux_In[23]),
.I1(icount_out0_carry__4_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[24]_i_1
(.I0(read_Mux_In[24]),
.I1(icount_out0_carry__4_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[25]_i_1
(.I0(read_Mux_In[25]),
.I1(icount_out0_carry__5_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[26]_i_1
(.I0(read_Mux_In[26]),
.I1(icount_out0_carry__5_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[27]_i_1
(.I0(read_Mux_In[27]),
.I1(icount_out0_carry__5_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[28]_i_1
(.I0(read_Mux_In[28]),
.I1(icount_out0_carry__5_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[29]_i_1
(.I0(read_Mux_In[29]),
.I1(icount_out0_carry__6_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[2]_i_1
(.I0(read_Mux_In[2]),
.I1(icount_out0_carry_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[30]_i_1
(.I0(read_Mux_In[30]),
.I1(icount_out0_carry__6_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[30]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[31]_i_2
(.I0(read_Mux_In[31]),
.I1(icount_out0_carry__6_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[31]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000E200))
\INFERRED_GEN.icount_out[32]_i_1
(.I0(counter_TC),
.I1(E),
.I2(icount_out0_carry__6_n_4),
.I3(s_axi_aresetn),
.I4(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[32]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[3]_i_1
(.I0(read_Mux_In[3]),
.I1(icount_out0_carry_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[4]_i_1
(.I0(read_Mux_In[4]),
.I1(icount_out0_carry_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[5]_i_1
(.I0(read_Mux_In[5]),
.I1(icount_out0_carry__0_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[6]_i_1
(.I0(read_Mux_In[6]),
.I1(icount_out0_carry__0_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[7]_i_1
(.I0(read_Mux_In[7]),
.I1(icount_out0_carry__0_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[8]_i_1
(.I0(read_Mux_In[8]),
.I1(icount_out0_carry__0_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[9]_i_1
(.I0(read_Mux_In[9]),
.I1(icount_out0_carry__1_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[9]_i_1_n_0 ));
FDRE \INFERRED_GEN.icount_out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[0]_i_1_n_0 ),
.Q(Q[0]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[10]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[10]_i_1_n_0 ),
.Q(Q[10]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[11]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[11]_i_1_n_0 ),
.Q(Q[11]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[12]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[12]_i_1_n_0 ),
.Q(Q[12]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[13]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[13]_i_1_n_0 ),
.Q(Q[13]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[14]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[14]_i_1_n_0 ),
.Q(Q[14]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[15]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[15]_i_1_n_0 ),
.Q(Q[15]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[16]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[16]_i_1_n_0 ),
.Q(Q[16]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[17]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[17]_i_1_n_0 ),
.Q(Q[17]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[18]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[18]_i_1_n_0 ),
.Q(Q[18]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[19]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[19]_i_1_n_0 ),
.Q(Q[19]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[1]_i_1_n_0 ),
.Q(Q[1]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[20]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[20]_i_1_n_0 ),
.Q(Q[20]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[21]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[21]_i_1_n_0 ),
.Q(Q[21]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[22]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[22]_i_1_n_0 ),
.Q(Q[22]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[23]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[23]_i_1_n_0 ),
.Q(Q[23]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[24]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[24]_i_1_n_0 ),
.Q(Q[24]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[25]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[25]_i_1_n_0 ),
.Q(Q[25]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[26]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[26]_i_1_n_0 ),
.Q(Q[26]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[27]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[27]_i_1_n_0 ),
.Q(Q[27]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[28]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[28]_i_1_n_0 ),
.Q(Q[28]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[29]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[29]_i_1_n_0 ),
.Q(Q[29]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[2]_i_1_n_0 ),
.Q(Q[2]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[30]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[30]_i_1_n_0 ),
.Q(Q[30]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[31]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[31]_i_2_n_0 ),
.Q(Q[31]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[32]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INFERRED_GEN.icount_out[32]_i_1_n_0 ),
.Q(counter_TC),
.R(1'b0));
FDRE \INFERRED_GEN.icount_out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[3]_i_1_n_0 ),
.Q(Q[3]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[4]_i_1_n_0 ),
.Q(Q[4]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[5]_i_1_n_0 ),
.Q(Q[5]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[6]_i_1_n_0 ),
.Q(Q[6]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[7]_i_1_n_0 ),
.Q(Q[7]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[8]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[8]_i_1_n_0 ),
.Q(Q[8]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[9]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[9]_i_1_n_0 ),
.Q(Q[9]),
.R(SR));
LUT2 #(
.INIT(4'h2))
generateOutPre1_i_1
(.I0(counter_TC),
.I1(\counter_TC_Reg_reg[1] ),
.O(generateOutPre1_reg));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry
(.CI(1'b0),
.CO({icount_out0_carry_n_0,icount_out0_carry_n_1,icount_out0_carry_n_2,icount_out0_carry_n_3}),
.CYINIT(Q[0]),
.DI({Q[3:1],icount_out0_carry_i_1_n_0}),
.O({icount_out0_carry_n_4,icount_out0_carry_n_5,icount_out0_carry_n_6,icount_out0_carry_n_7}),
.S({icount_out0_carry_i_2_n_0,icount_out0_carry_i_3_n_0,icount_out0_carry_i_4_n_0,S}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__0
(.CI(icount_out0_carry_n_0),
.CO({icount_out0_carry__0_n_0,icount_out0_carry__0_n_1,icount_out0_carry__0_n_2,icount_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O({icount_out0_carry__0_n_4,icount_out0_carry__0_n_5,icount_out0_carry__0_n_6,icount_out0_carry__0_n_7}),
.S({icount_out0_carry__0_i_1_n_0,icount_out0_carry__0_i_2_n_0,icount_out0_carry__0_i_3_n_0,icount_out0_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(icount_out0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_2
(.I0(Q[6]),
.I1(Q[7]),
.O(icount_out0_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_3
(.I0(Q[5]),
.I1(Q[6]),
.O(icount_out0_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_4
(.I0(Q[4]),
.I1(Q[5]),
.O(icount_out0_carry__0_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__1
(.CI(icount_out0_carry__0_n_0),
.CO({icount_out0_carry__1_n_0,icount_out0_carry__1_n_1,icount_out0_carry__1_n_2,icount_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI(Q[11:8]),
.O({icount_out0_carry__1_n_4,icount_out0_carry__1_n_5,icount_out0_carry__1_n_6,icount_out0_carry__1_n_7}),
.S({icount_out0_carry__1_i_1_n_0,icount_out0_carry__1_i_2_n_0,icount_out0_carry__1_i_3_n_0,icount_out0_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_1
(.I0(Q[11]),
.I1(Q[12]),
.O(icount_out0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_2
(.I0(Q[10]),
.I1(Q[11]),
.O(icount_out0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_3
(.I0(Q[9]),
.I1(Q[10]),
.O(icount_out0_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_4
(.I0(Q[8]),
.I1(Q[9]),
.O(icount_out0_carry__1_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__2
(.CI(icount_out0_carry__1_n_0),
.CO({icount_out0_carry__2_n_0,icount_out0_carry__2_n_1,icount_out0_carry__2_n_2,icount_out0_carry__2_n_3}),
.CYINIT(1'b0),
.DI(Q[15:12]),
.O({icount_out0_carry__2_n_4,icount_out0_carry__2_n_5,icount_out0_carry__2_n_6,icount_out0_carry__2_n_7}),
.S({icount_out0_carry__2_i_1_n_0,icount_out0_carry__2_i_2_n_0,icount_out0_carry__2_i_3_n_0,icount_out0_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_1
(.I0(Q[15]),
.I1(Q[16]),
.O(icount_out0_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_2
(.I0(Q[14]),
.I1(Q[15]),
.O(icount_out0_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_3
(.I0(Q[13]),
.I1(Q[14]),
.O(icount_out0_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_4
(.I0(Q[12]),
.I1(Q[13]),
.O(icount_out0_carry__2_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__3
(.CI(icount_out0_carry__2_n_0),
.CO({icount_out0_carry__3_n_0,icount_out0_carry__3_n_1,icount_out0_carry__3_n_2,icount_out0_carry__3_n_3}),
.CYINIT(1'b0),
.DI(Q[19:16]),
.O({icount_out0_carry__3_n_4,icount_out0_carry__3_n_5,icount_out0_carry__3_n_6,icount_out0_carry__3_n_7}),
.S({icount_out0_carry__3_i_1_n_0,icount_out0_carry__3_i_2_n_0,icount_out0_carry__3_i_3_n_0,icount_out0_carry__3_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_1
(.I0(Q[19]),
.I1(Q[20]),
.O(icount_out0_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_2
(.I0(Q[18]),
.I1(Q[19]),
.O(icount_out0_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_3
(.I0(Q[17]),
.I1(Q[18]),
.O(icount_out0_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_4
(.I0(Q[16]),
.I1(Q[17]),
.O(icount_out0_carry__3_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__4
(.CI(icount_out0_carry__3_n_0),
.CO({icount_out0_carry__4_n_0,icount_out0_carry__4_n_1,icount_out0_carry__4_n_2,icount_out0_carry__4_n_3}),
.CYINIT(1'b0),
.DI(Q[23:20]),
.O({icount_out0_carry__4_n_4,icount_out0_carry__4_n_5,icount_out0_carry__4_n_6,icount_out0_carry__4_n_7}),
.S({icount_out0_carry__4_i_1_n_0,icount_out0_carry__4_i_2_n_0,icount_out0_carry__4_i_3_n_0,icount_out0_carry__4_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_1
(.I0(Q[23]),
.I1(Q[24]),
.O(icount_out0_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_2
(.I0(Q[22]),
.I1(Q[23]),
.O(icount_out0_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_3
(.I0(Q[21]),
.I1(Q[22]),
.O(icount_out0_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_4
(.I0(Q[20]),
.I1(Q[21]),
.O(icount_out0_carry__4_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__5
(.CI(icount_out0_carry__4_n_0),
.CO({icount_out0_carry__5_n_0,icount_out0_carry__5_n_1,icount_out0_carry__5_n_2,icount_out0_carry__5_n_3}),
.CYINIT(1'b0),
.DI(Q[27:24]),
.O({icount_out0_carry__5_n_4,icount_out0_carry__5_n_5,icount_out0_carry__5_n_6,icount_out0_carry__5_n_7}),
.S({icount_out0_carry__5_i_1_n_0,icount_out0_carry__5_i_2_n_0,icount_out0_carry__5_i_3_n_0,icount_out0_carry__5_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_1
(.I0(Q[27]),
.I1(Q[28]),
.O(icount_out0_carry__5_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_2
(.I0(Q[26]),
.I1(Q[27]),
.O(icount_out0_carry__5_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_3
(.I0(Q[25]),
.I1(Q[26]),
.O(icount_out0_carry__5_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_4
(.I0(Q[24]),
.I1(Q[25]),
.O(icount_out0_carry__5_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__6
(.CI(icount_out0_carry__5_n_0),
.CO({NLW_icount_out0_carry__6_CO_UNCONNECTED[3],icount_out0_carry__6_n_1,icount_out0_carry__6_n_2,icount_out0_carry__6_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Q[30:28]}),
.O({icount_out0_carry__6_n_4,icount_out0_carry__6_n_5,icount_out0_carry__6_n_6,icount_out0_carry__6_n_7}),
.S({icount_out0_carry__6_i_1_n_0,icount_out0_carry__6_i_2_n_0,icount_out0_carry__6_i_3_n_0,icount_out0_carry__6_i_4_n_0}));
LUT1 #(
.INIT(2'h1))
icount_out0_carry__6_i_1
(.I0(Q[31]),
.O(icount_out0_carry__6_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_2
(.I0(Q[30]),
.I1(Q[31]),
.O(icount_out0_carry__6_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_3
(.I0(Q[29]),
.I1(Q[30]),
.O(icount_out0_carry__6_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_4
(.I0(Q[28]),
.I1(Q[29]),
.O(icount_out0_carry__6_i_4_n_0));
LUT1 #(
.INIT(2'h1))
icount_out0_carry_i_1
(.I0(Q[1]),
.O(icount_out0_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_2
(.I0(Q[3]),
.I1(Q[4]),
.O(icount_out0_carry_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_3
(.I0(Q[2]),
.I1(Q[3]),
.O(icount_out0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_4
(.I0(Q[1]),
.I1(Q[2]),
.O(icount_out0_carry_i_4_n_0));
endmodule
(* ORIG_REF_NAME = "counter_f" *)
module zqynq_lab_1_design_axi_timer_0_1_counter_f_3
(\LOAD_REG_GEN[0].LOAD_REG_I ,
generateOutPre0_reg,
counter_TC,
S,
read_Mux_In,
load_Counter_Reg,
\LOAD_REG_GEN[0].LOAD_REG_I_0 ,
Q,
s_axi_aresetn_0,
E,
s_axi_aclk,
s_axi_aresetn);
output [31:0]\LOAD_REG_GEN[0].LOAD_REG_I ;
output generateOutPre0_reg;
output [0:0]counter_TC;
input [0:0]S;
input [10:0]read_Mux_In;
input [0:0]load_Counter_Reg;
input [20:0]\LOAD_REG_GEN[0].LOAD_REG_I_0 ;
input [0:0]Q;
input s_axi_aresetn_0;
input [0:0]E;
input s_axi_aclk;
input s_axi_aresetn;
wire [0:0]E;
wire \INFERRED_GEN.icount_out[32]_i_1_n_0 ;
wire [31:0]\LOAD_REG_GEN[0].LOAD_REG_I ;
wire [20:0]\LOAD_REG_GEN[0].LOAD_REG_I_0 ;
wire [0:0]Q;
wire [0:0]S;
wire [0:0]counter_TC;
wire generateOutPre0_reg;
wire icount_out0_carry__0_i_1__0_n_0;
wire icount_out0_carry__0_i_2__0_n_0;
wire icount_out0_carry__0_i_3__0_n_0;
wire icount_out0_carry__0_i_4__0_n_0;
wire icount_out0_carry__0_n_0;
wire icount_out0_carry__0_n_1;
wire icount_out0_carry__0_n_2;
wire icount_out0_carry__0_n_3;
wire icount_out0_carry__0_n_4;
wire icount_out0_carry__0_n_5;
wire icount_out0_carry__0_n_6;
wire icount_out0_carry__0_n_7;
wire icount_out0_carry__1_i_1__0_n_0;
wire icount_out0_carry__1_i_2__0_n_0;
wire icount_out0_carry__1_i_3__0_n_0;
wire icount_out0_carry__1_i_4__0_n_0;
wire icount_out0_carry__1_n_0;
wire icount_out0_carry__1_n_1;
wire icount_out0_carry__1_n_2;
wire icount_out0_carry__1_n_3;
wire icount_out0_carry__1_n_4;
wire icount_out0_carry__1_n_5;
wire icount_out0_carry__1_n_6;
wire icount_out0_carry__1_n_7;
wire icount_out0_carry__2_i_1__0_n_0;
wire icount_out0_carry__2_i_2__0_n_0;
wire icount_out0_carry__2_i_3__0_n_0;
wire icount_out0_carry__2_i_4__0_n_0;
wire icount_out0_carry__2_n_0;
wire icount_out0_carry__2_n_1;
wire icount_out0_carry__2_n_2;
wire icount_out0_carry__2_n_3;
wire icount_out0_carry__2_n_4;
wire icount_out0_carry__2_n_5;
wire icount_out0_carry__2_n_6;
wire icount_out0_carry__2_n_7;
wire icount_out0_carry__3_i_1__0_n_0;
wire icount_out0_carry__3_i_2__0_n_0;
wire icount_out0_carry__3_i_3__0_n_0;
wire icount_out0_carry__3_i_4__0_n_0;
wire icount_out0_carry__3_n_0;
wire icount_out0_carry__3_n_1;
wire icount_out0_carry__3_n_2;
wire icount_out0_carry__3_n_3;
wire icount_out0_carry__3_n_4;
wire icount_out0_carry__3_n_5;
wire icount_out0_carry__3_n_6;
wire icount_out0_carry__3_n_7;
wire icount_out0_carry__4_i_1__0_n_0;
wire icount_out0_carry__4_i_2__0_n_0;
wire icount_out0_carry__4_i_3__0_n_0;
wire icount_out0_carry__4_i_4__0_n_0;
wire icount_out0_carry__4_n_0;
wire icount_out0_carry__4_n_1;
wire icount_out0_carry__4_n_2;
wire icount_out0_carry__4_n_3;
wire icount_out0_carry__4_n_4;
wire icount_out0_carry__4_n_5;
wire icount_out0_carry__4_n_6;
wire icount_out0_carry__4_n_7;
wire icount_out0_carry__5_i_1__0_n_0;
wire icount_out0_carry__5_i_2__0_n_0;
wire icount_out0_carry__5_i_3__0_n_0;
wire icount_out0_carry__5_i_4__0_n_0;
wire icount_out0_carry__5_n_0;
wire icount_out0_carry__5_n_1;
wire icount_out0_carry__5_n_2;
wire icount_out0_carry__5_n_3;
wire icount_out0_carry__5_n_4;
wire icount_out0_carry__5_n_5;
wire icount_out0_carry__5_n_6;
wire icount_out0_carry__5_n_7;
wire icount_out0_carry__6_i_1__0_n_0;
wire icount_out0_carry__6_i_2__0_n_0;
wire icount_out0_carry__6_i_3__0_n_0;
wire icount_out0_carry__6_i_4__0_n_0;
wire icount_out0_carry__6_n_1;
wire icount_out0_carry__6_n_2;
wire icount_out0_carry__6_n_3;
wire icount_out0_carry__6_n_4;
wire icount_out0_carry__6_n_5;
wire icount_out0_carry__6_n_6;
wire icount_out0_carry__6_n_7;
wire icount_out0_carry_i_1__0_n_0;
wire icount_out0_carry_i_2__0_n_0;
wire icount_out0_carry_i_3__0_n_0;
wire icount_out0_carry_i_4__0_n_0;
wire icount_out0_carry_n_0;
wire icount_out0_carry_n_1;
wire icount_out0_carry_n_2;
wire icount_out0_carry_n_3;
wire icount_out0_carry_n_4;
wire icount_out0_carry_n_5;
wire icount_out0_carry_n_6;
wire icount_out0_carry_n_7;
wire [0:0]load_Counter_Reg;
wire [31:0]p_1_in;
wire [10:0]read_Mux_In;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
wire [3:3]NLW_icount_out0_carry__6_CO_UNCONNECTED;
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'h8B))
\INFERRED_GEN.icount_out[0]_i_1__0
(.I0(read_Mux_In[0]),
.I1(load_Counter_Reg),
.I2(\LOAD_REG_GEN[0].LOAD_REG_I [0]),
.O(p_1_in[0]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[10]_i_1__0
(.I0(read_Mux_In[10]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__1_n_6),
.O(p_1_in[10]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[11]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [0]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__1_n_5),
.O(p_1_in[11]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[12]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [1]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__1_n_4),
.O(p_1_in[12]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[13]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [2]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__2_n_7),
.O(p_1_in[13]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[14]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [3]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__2_n_6),
.O(p_1_in[14]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[15]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [4]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__2_n_5),
.O(p_1_in[15]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[16]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [5]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__2_n_4),
.O(p_1_in[16]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[17]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [6]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__3_n_7),
.O(p_1_in[17]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[18]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [7]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__3_n_6),
.O(p_1_in[18]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[19]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [8]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__3_n_5),
.O(p_1_in[19]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[1]_i_1__0
(.I0(read_Mux_In[1]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry_n_7),
.O(p_1_in[1]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[20]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [9]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__3_n_4),
.O(p_1_in[20]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[21]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [10]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__4_n_7),
.O(p_1_in[21]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[22]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [11]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__4_n_6),
.O(p_1_in[22]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[23]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [12]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__4_n_5),
.O(p_1_in[23]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[24]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [13]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__4_n_4),
.O(p_1_in[24]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[25]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [14]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__5_n_7),
.O(p_1_in[25]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[26]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [15]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__5_n_6),
.O(p_1_in[26]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[27]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [16]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__5_n_5),
.O(p_1_in[27]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[28]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [17]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__5_n_4),
.O(p_1_in[28]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[29]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [18]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__6_n_7),
.O(p_1_in[29]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[2]_i_1__0
(.I0(read_Mux_In[2]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry_n_6),
.O(p_1_in[2]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[30]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [19]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__6_n_6),
.O(p_1_in[30]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[31]_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [20]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__6_n_5),
.O(p_1_in[31]));
LUT5 #(
.INIT(32'h0000E200))
\INFERRED_GEN.icount_out[32]_i_1
(.I0(counter_TC),
.I1(E),
.I2(icount_out0_carry__6_n_4),
.I3(s_axi_aresetn),
.I4(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[32]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[3]_i_1__0
(.I0(read_Mux_In[3]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry_n_5),
.O(p_1_in[3]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[4]_i_1__0
(.I0(read_Mux_In[4]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry_n_4),
.O(p_1_in[4]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[5]_i_1__0
(.I0(read_Mux_In[5]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__0_n_7),
.O(p_1_in[5]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[6]_i_1__0
(.I0(read_Mux_In[6]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__0_n_6),
.O(p_1_in[6]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[7]_i_1__0
(.I0(read_Mux_In[7]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__0_n_5),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[8]_i_1__0
(.I0(read_Mux_In[8]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__0_n_4),
.O(p_1_in[8]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[9]_i_1__0
(.I0(read_Mux_In[9]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__1_n_7),
.O(p_1_in[9]));
FDRE \INFERRED_GEN.icount_out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[0]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [0]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[10]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[10]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [10]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[11]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[11]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [11]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[12]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[12]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [12]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[13]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[13]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [13]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[14]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[14]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [14]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[15]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[15]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [15]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[16]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[16]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [16]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[17]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[17]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [17]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[18]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[18]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [18]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[19]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[19]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [19]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[1]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [1]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[20]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[20]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [20]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[21]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[21]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [21]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[22]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[22]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [22]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[23]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[23]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [23]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[24]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[24]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [24]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[25]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[25]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [25]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[26]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[26]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [26]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[27]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[27]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [27]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[28]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[28]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [28]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[29]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[29]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [29]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[2]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [2]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[30]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[30]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [30]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[31]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[31]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [31]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[32]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INFERRED_GEN.icount_out[32]_i_1_n_0 ),
.Q(counter_TC),
.R(1'b0));
FDRE \INFERRED_GEN.icount_out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[3]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [3]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[4]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [4]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[5]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [5]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[6]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [6]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[7]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [7]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[8]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[8]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [8]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[9]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[9]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [9]),
.R(s_axi_aresetn_0));
LUT2 #(
.INIT(4'h2))
generateOutPre0_i_1
(.I0(counter_TC),
.I1(Q),
.O(generateOutPre0_reg));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry
(.CI(1'b0),
.CO({icount_out0_carry_n_0,icount_out0_carry_n_1,icount_out0_carry_n_2,icount_out0_carry_n_3}),
.CYINIT(\LOAD_REG_GEN[0].LOAD_REG_I [0]),
.DI({\LOAD_REG_GEN[0].LOAD_REG_I [3:1],icount_out0_carry_i_1__0_n_0}),
.O({icount_out0_carry_n_4,icount_out0_carry_n_5,icount_out0_carry_n_6,icount_out0_carry_n_7}),
.S({icount_out0_carry_i_2__0_n_0,icount_out0_carry_i_3__0_n_0,icount_out0_carry_i_4__0_n_0,S}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__0
(.CI(icount_out0_carry_n_0),
.CO({icount_out0_carry__0_n_0,icount_out0_carry__0_n_1,icount_out0_carry__0_n_2,icount_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [7:4]),
.O({icount_out0_carry__0_n_4,icount_out0_carry__0_n_5,icount_out0_carry__0_n_6,icount_out0_carry__0_n_7}),
.S({icount_out0_carry__0_i_1__0_n_0,icount_out0_carry__0_i_2__0_n_0,icount_out0_carry__0_i_3__0_n_0,icount_out0_carry__0_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [7]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [8]),
.O(icount_out0_carry__0_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [6]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [7]),
.O(icount_out0_carry__0_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [5]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [6]),
.O(icount_out0_carry__0_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [4]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [5]),
.O(icount_out0_carry__0_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__1
(.CI(icount_out0_carry__0_n_0),
.CO({icount_out0_carry__1_n_0,icount_out0_carry__1_n_1,icount_out0_carry__1_n_2,icount_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [11:8]),
.O({icount_out0_carry__1_n_4,icount_out0_carry__1_n_5,icount_out0_carry__1_n_6,icount_out0_carry__1_n_7}),
.S({icount_out0_carry__1_i_1__0_n_0,icount_out0_carry__1_i_2__0_n_0,icount_out0_carry__1_i_3__0_n_0,icount_out0_carry__1_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [11]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [12]),
.O(icount_out0_carry__1_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [10]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [11]),
.O(icount_out0_carry__1_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [9]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [10]),
.O(icount_out0_carry__1_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [8]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [9]),
.O(icount_out0_carry__1_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__2
(.CI(icount_out0_carry__1_n_0),
.CO({icount_out0_carry__2_n_0,icount_out0_carry__2_n_1,icount_out0_carry__2_n_2,icount_out0_carry__2_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [15:12]),
.O({icount_out0_carry__2_n_4,icount_out0_carry__2_n_5,icount_out0_carry__2_n_6,icount_out0_carry__2_n_7}),
.S({icount_out0_carry__2_i_1__0_n_0,icount_out0_carry__2_i_2__0_n_0,icount_out0_carry__2_i_3__0_n_0,icount_out0_carry__2_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [15]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [16]),
.O(icount_out0_carry__2_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [14]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [15]),
.O(icount_out0_carry__2_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [13]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [14]),
.O(icount_out0_carry__2_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [12]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [13]),
.O(icount_out0_carry__2_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__3
(.CI(icount_out0_carry__2_n_0),
.CO({icount_out0_carry__3_n_0,icount_out0_carry__3_n_1,icount_out0_carry__3_n_2,icount_out0_carry__3_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [19:16]),
.O({icount_out0_carry__3_n_4,icount_out0_carry__3_n_5,icount_out0_carry__3_n_6,icount_out0_carry__3_n_7}),
.S({icount_out0_carry__3_i_1__0_n_0,icount_out0_carry__3_i_2__0_n_0,icount_out0_carry__3_i_3__0_n_0,icount_out0_carry__3_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [19]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [20]),
.O(icount_out0_carry__3_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [18]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [19]),
.O(icount_out0_carry__3_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [17]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [18]),
.O(icount_out0_carry__3_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [16]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [17]),
.O(icount_out0_carry__3_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__4
(.CI(icount_out0_carry__3_n_0),
.CO({icount_out0_carry__4_n_0,icount_out0_carry__4_n_1,icount_out0_carry__4_n_2,icount_out0_carry__4_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [23:20]),
.O({icount_out0_carry__4_n_4,icount_out0_carry__4_n_5,icount_out0_carry__4_n_6,icount_out0_carry__4_n_7}),
.S({icount_out0_carry__4_i_1__0_n_0,icount_out0_carry__4_i_2__0_n_0,icount_out0_carry__4_i_3__0_n_0,icount_out0_carry__4_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [23]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [24]),
.O(icount_out0_carry__4_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [22]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [23]),
.O(icount_out0_carry__4_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [21]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [22]),
.O(icount_out0_carry__4_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [20]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [21]),
.O(icount_out0_carry__4_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__5
(.CI(icount_out0_carry__4_n_0),
.CO({icount_out0_carry__5_n_0,icount_out0_carry__5_n_1,icount_out0_carry__5_n_2,icount_out0_carry__5_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [27:24]),
.O({icount_out0_carry__5_n_4,icount_out0_carry__5_n_5,icount_out0_carry__5_n_6,icount_out0_carry__5_n_7}),
.S({icount_out0_carry__5_i_1__0_n_0,icount_out0_carry__5_i_2__0_n_0,icount_out0_carry__5_i_3__0_n_0,icount_out0_carry__5_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [27]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [28]),
.O(icount_out0_carry__5_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [26]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [27]),
.O(icount_out0_carry__5_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [25]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [26]),
.O(icount_out0_carry__5_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [24]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [25]),
.O(icount_out0_carry__5_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__6
(.CI(icount_out0_carry__5_n_0),
.CO({NLW_icount_out0_carry__6_CO_UNCONNECTED[3],icount_out0_carry__6_n_1,icount_out0_carry__6_n_2,icount_out0_carry__6_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\LOAD_REG_GEN[0].LOAD_REG_I [30:28]}),
.O({icount_out0_carry__6_n_4,icount_out0_carry__6_n_5,icount_out0_carry__6_n_6,icount_out0_carry__6_n_7}),
.S({icount_out0_carry__6_i_1__0_n_0,icount_out0_carry__6_i_2__0_n_0,icount_out0_carry__6_i_3__0_n_0,icount_out0_carry__6_i_4__0_n_0}));
LUT1 #(
.INIT(2'h1))
icount_out0_carry__6_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [31]),
.O(icount_out0_carry__6_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [30]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [31]),
.O(icount_out0_carry__6_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [29]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [30]),
.O(icount_out0_carry__6_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [28]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [29]),
.O(icount_out0_carry__6_i_4__0_n_0));
LUT1 #(
.INIT(2'h1))
icount_out0_carry_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [1]),
.O(icount_out0_carry_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [3]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [4]),
.O(icount_out0_carry_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [2]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [3]),
.O(icount_out0_carry_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [1]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [2]),
.O(icount_out0_carry_i_4__0_n_0));
endmodule
(* ORIG_REF_NAME = "mux_onehot_f" *)
module zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f
(D,
Bus_RNW_reg_reg,
\INFERRED_GEN.icount_out_reg[31] ,
Bus_RNW_reg_reg_0,
\INFERRED_GEN.icount_out_reg[30] ,
Bus_RNW_reg_reg_1,
\INFERRED_GEN.icount_out_reg[29] ,
Bus_RNW_reg_reg_2,
\INFERRED_GEN.icount_out_reg[28] ,
Bus_RNW_reg_reg_3,
\INFERRED_GEN.icount_out_reg[27] ,
Bus_RNW_reg_reg_4,
\INFERRED_GEN.icount_out_reg[26] ,
Bus_RNW_reg_reg_5,
\INFERRED_GEN.icount_out_reg[25] ,
Bus_RNW_reg_reg_6,
\INFERRED_GEN.icount_out_reg[24] ,
Bus_RNW_reg_reg_7,
\INFERRED_GEN.icount_out_reg[23] ,
Bus_RNW_reg_reg_8,
\INFERRED_GEN.icount_out_reg[22] ,
Bus_RNW_reg_reg_9,
\INFERRED_GEN.icount_out_reg[21] ,
Bus_RNW_reg_reg_10,
\INFERRED_GEN.icount_out_reg[20] ,
Bus_RNW_reg_reg_11,
\INFERRED_GEN.icount_out_reg[19] ,
Bus_RNW_reg_reg_12,
\INFERRED_GEN.icount_out_reg[18] ,
Bus_RNW_reg_reg_13,
\INFERRED_GEN.icount_out_reg[17] ,
Bus_RNW_reg_reg_14,
\INFERRED_GEN.icount_out_reg[16] ,
Bus_RNW_reg_reg_15,
\INFERRED_GEN.icount_out_reg[15] ,
Bus_RNW_reg_reg_16,
\INFERRED_GEN.icount_out_reg[14] ,
Bus_RNW_reg_reg_17,
\INFERRED_GEN.icount_out_reg[13] ,
Bus_RNW_reg_reg_18,
\INFERRED_GEN.icount_out_reg[12] ,
\LOAD_REG_GEN[20].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[11] ,
\LOAD_REG_GEN[21].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[10] ,
\LOAD_REG_GEN[22].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[9] ,
\LOAD_REG_GEN[23].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[8] ,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[7] ,
\LOAD_REG_GEN[25].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[6] ,
\LOAD_REG_GEN[26].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[5] ,
\LOAD_REG_GEN[27].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[4] ,
\LOAD_REG_GEN[28].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[3] ,
\LOAD_REG_GEN[29].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[2] ,
\LOAD_REG_GEN[30].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[1] ,
\LOAD_REG_GEN[31].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[0] );
output [31:0]D;
input Bus_RNW_reg_reg;
input \INFERRED_GEN.icount_out_reg[31] ;
input Bus_RNW_reg_reg_0;
input \INFERRED_GEN.icount_out_reg[30] ;
input Bus_RNW_reg_reg_1;
input \INFERRED_GEN.icount_out_reg[29] ;
input Bus_RNW_reg_reg_2;
input \INFERRED_GEN.icount_out_reg[28] ;
input Bus_RNW_reg_reg_3;
input \INFERRED_GEN.icount_out_reg[27] ;
input Bus_RNW_reg_reg_4;
input \INFERRED_GEN.icount_out_reg[26] ;
input Bus_RNW_reg_reg_5;
input \INFERRED_GEN.icount_out_reg[25] ;
input Bus_RNW_reg_reg_6;
input \INFERRED_GEN.icount_out_reg[24] ;
input Bus_RNW_reg_reg_7;
input \INFERRED_GEN.icount_out_reg[23] ;
input Bus_RNW_reg_reg_8;
input \INFERRED_GEN.icount_out_reg[22] ;
input Bus_RNW_reg_reg_9;
input \INFERRED_GEN.icount_out_reg[21] ;
input Bus_RNW_reg_reg_10;
input \INFERRED_GEN.icount_out_reg[20] ;
input Bus_RNW_reg_reg_11;
input \INFERRED_GEN.icount_out_reg[19] ;
input Bus_RNW_reg_reg_12;
input \INFERRED_GEN.icount_out_reg[18] ;
input Bus_RNW_reg_reg_13;
input \INFERRED_GEN.icount_out_reg[17] ;
input Bus_RNW_reg_reg_14;
input \INFERRED_GEN.icount_out_reg[16] ;
input Bus_RNW_reg_reg_15;
input \INFERRED_GEN.icount_out_reg[15] ;
input Bus_RNW_reg_reg_16;
input \INFERRED_GEN.icount_out_reg[14] ;
input Bus_RNW_reg_reg_17;
input \INFERRED_GEN.icount_out_reg[13] ;
input Bus_RNW_reg_reg_18;
input \INFERRED_GEN.icount_out_reg[12] ;
input \LOAD_REG_GEN[20].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[11] ;
input \LOAD_REG_GEN[21].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[10] ;
input \LOAD_REG_GEN[22].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[9] ;
input \LOAD_REG_GEN[23].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[8] ;
input \LOAD_REG_GEN[24].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[7] ;
input \LOAD_REG_GEN[25].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[6] ;
input \LOAD_REG_GEN[26].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[5] ;
input \LOAD_REG_GEN[27].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[4] ;
input \LOAD_REG_GEN[28].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[3] ;
input \LOAD_REG_GEN[29].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[2] ;
input \LOAD_REG_GEN[30].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[1] ;
input \LOAD_REG_GEN[31].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[0] ;
wire Bus_RNW_reg_reg;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire Bus_RNW_reg_reg_10;
wire Bus_RNW_reg_reg_11;
wire Bus_RNW_reg_reg_12;
wire Bus_RNW_reg_reg_13;
wire Bus_RNW_reg_reg_14;
wire Bus_RNW_reg_reg_15;
wire Bus_RNW_reg_reg_16;
wire Bus_RNW_reg_reg_17;
wire Bus_RNW_reg_reg_18;
wire Bus_RNW_reg_reg_2;
wire Bus_RNW_reg_reg_3;
wire Bus_RNW_reg_reg_4;
wire Bus_RNW_reg_reg_5;
wire Bus_RNW_reg_reg_6;
wire Bus_RNW_reg_reg_7;
wire Bus_RNW_reg_reg_8;
wire Bus_RNW_reg_reg_9;
wire [31:0]D;
wire \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \INFERRED_GEN.icount_out_reg[0] ;
wire \INFERRED_GEN.icount_out_reg[10] ;
wire \INFERRED_GEN.icount_out_reg[11] ;
wire \INFERRED_GEN.icount_out_reg[12] ;
wire \INFERRED_GEN.icount_out_reg[13] ;
wire \INFERRED_GEN.icount_out_reg[14] ;
wire \INFERRED_GEN.icount_out_reg[15] ;
wire \INFERRED_GEN.icount_out_reg[16] ;
wire \INFERRED_GEN.icount_out_reg[17] ;
wire \INFERRED_GEN.icount_out_reg[18] ;
wire \INFERRED_GEN.icount_out_reg[19] ;
wire \INFERRED_GEN.icount_out_reg[1] ;
wire \INFERRED_GEN.icount_out_reg[20] ;
wire \INFERRED_GEN.icount_out_reg[21] ;
wire \INFERRED_GEN.icount_out_reg[22] ;
wire \INFERRED_GEN.icount_out_reg[23] ;
wire \INFERRED_GEN.icount_out_reg[24] ;
wire \INFERRED_GEN.icount_out_reg[25] ;
wire \INFERRED_GEN.icount_out_reg[26] ;
wire \INFERRED_GEN.icount_out_reg[27] ;
wire \INFERRED_GEN.icount_out_reg[28] ;
wire \INFERRED_GEN.icount_out_reg[29] ;
wire \INFERRED_GEN.icount_out_reg[2] ;
wire \INFERRED_GEN.icount_out_reg[30] ;
wire \INFERRED_GEN.icount_out_reg[31] ;
wire \INFERRED_GEN.icount_out_reg[3] ;
wire \INFERRED_GEN.icount_out_reg[4] ;
wire \INFERRED_GEN.icount_out_reg[5] ;
wire \INFERRED_GEN.icount_out_reg[6] ;
wire \INFERRED_GEN.icount_out_reg[7] ;
wire \INFERRED_GEN.icount_out_reg[8] ;
wire \INFERRED_GEN.icount_out_reg[9] ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire \LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[22].LOAD_REG_I ;
wire \LOAD_REG_GEN[23].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[25].LOAD_REG_I ;
wire \LOAD_REG_GEN[26].LOAD_REG_I ;
wire \LOAD_REG_GEN[27].LOAD_REG_I ;
wire \LOAD_REG_GEN[28].LOAD_REG_I ;
wire \LOAD_REG_GEN[29].LOAD_REG_I ;
wire \LOAD_REG_GEN[30].LOAD_REG_I ;
wire \LOAD_REG_GEN[31].LOAD_REG_I ;
wire cyout_1;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[31],cyout_1}),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[31] ,Bus_RNW_reg_reg}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[21],\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[21] ,Bus_RNW_reg_reg_9}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[20],\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[20] ,Bus_RNW_reg_reg_10}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[19],\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[19] ,Bus_RNW_reg_reg_11}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[18],\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[18] ,Bus_RNW_reg_reg_12}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[17],\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[17] ,Bus_RNW_reg_reg_13}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[16],\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[16] ,Bus_RNW_reg_reg_14}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[15],\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[15] ,Bus_RNW_reg_reg_15}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[14],\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[14] ,Bus_RNW_reg_reg_16}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[13],\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[13] ,Bus_RNW_reg_reg_17}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[12],\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[12] ,Bus_RNW_reg_reg_18}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[30],\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[30] ,Bus_RNW_reg_reg_0}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[11],\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[11] ,\LOAD_REG_GEN[20].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[10],\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[10] ,\LOAD_REG_GEN[21].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[9],\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[9] ,\LOAD_REG_GEN[22].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[8],\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[8] ,\LOAD_REG_GEN[23].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[7],\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[7] ,\LOAD_REG_GEN[24].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[6],\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[6] ,\LOAD_REG_GEN[25].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[5],\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[5] ,\LOAD_REG_GEN[26].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[4],\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[4] ,\LOAD_REG_GEN[27].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[3],\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[3] ,\LOAD_REG_GEN[28].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[2],\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[2] ,\LOAD_REG_GEN[29].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[29],\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[29] ,Bus_RNW_reg_reg_1}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[1],\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[1] ,\LOAD_REG_GEN[30].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[0],\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[0] ,\LOAD_REG_GEN[31].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[28],\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[28] ,Bus_RNW_reg_reg_2}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[27],\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[27] ,Bus_RNW_reg_reg_3}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[26],\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[26] ,Bus_RNW_reg_reg_4}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[25],\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[25] ,Bus_RNW_reg_reg_5}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[24],\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[24] ,Bus_RNW_reg_reg_6}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[23],\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[23] ,Bus_RNW_reg_reg_7}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[22],\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[22] ,Bus_RNW_reg_reg_8}));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_1_pselect_f
(ce_expnd_i_7,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_7;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_7;
LUT4 #(
.INIT(16'h0010))
CS
(.I0(\bus2ip_addr_i_reg[4] [2]),
.I1(\bus2ip_addr_i_reg[4] [1]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [0]),
.O(ce_expnd_i_7));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized1
(ce_expnd_i_5,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_5;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_5;
LUT4 #(
.INIT(16'h1000))
CS
(.I0(\bus2ip_addr_i_reg[4] [2]),
.I1(\bus2ip_addr_i_reg[4] [0]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [1]),
.O(ce_expnd_i_5));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized3
(ce_expnd_i_3,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_3;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_3;
LUT4 #(
.INIT(16'h1000))
CS
(.I0(\bus2ip_addr_i_reg[4] [1]),
.I1(\bus2ip_addr_i_reg[4] [0]),
.I2(\bus2ip_addr_i_reg[4] [2]),
.I3(Q),
.O(ce_expnd_i_3));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized4
(ce_expnd_i_2,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_2;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_2;
LUT4 #(
.INIT(16'h4000))
CS
(.I0(\bus2ip_addr_i_reg[4] [1]),
.I1(\bus2ip_addr_i_reg[4] [2]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [0]),
.O(ce_expnd_i_2));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized5
(ce_expnd_i_1,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_1;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_1;
LUT4 #(
.INIT(16'h4000))
CS
(.I0(\bus2ip_addr_i_reg[4] [0]),
.I1(\bus2ip_addr_i_reg[4] [2]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [1]),
.O(ce_expnd_i_1));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_1_pselect_f__parameterized6
(ce_expnd_i_0,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_0;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_0;
LUT4 #(
.INIT(16'h8000))
CS
(.I0(\bus2ip_addr_i_reg[4] [1]),
.I1(\bus2ip_addr_i_reg[4] [0]),
.I2(\bus2ip_addr_i_reg[4] [2]),
.I3(Q),
.O(ce_expnd_i_0));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module zqynq_lab_1_design_axi_timer_0_1_slave_attachment
(\LOAD_REG_GEN[31].LOAD_REG_I ,
\TCSR0_GENERATE[23].TCSR0_FF_I ,
s_axi_rvalid,
s_axi_bvalid,
\s_axi_rdata_i_reg[12]_0 ,
\s_axi_rdata_i_reg[13]_0 ,
\s_axi_rdata_i_reg[14]_0 ,
\s_axi_rdata_i_reg[15]_0 ,
\s_axi_rdata_i_reg[16]_0 ,
\s_axi_rdata_i_reg[17]_0 ,
\s_axi_rdata_i_reg[18]_0 ,
\s_axi_rdata_i_reg[19]_0 ,
\s_axi_rdata_i_reg[20]_0 ,
\s_axi_rdata_i_reg[21]_0 ,
\s_axi_rdata_i_reg[22]_0 ,
\s_axi_rdata_i_reg[23]_0 ,
\s_axi_rdata_i_reg[24]_0 ,
\s_axi_rdata_i_reg[25]_0 ,
\s_axi_rdata_i_reg[26]_0 ,
\s_axi_rdata_i_reg[27]_0 ,
\s_axi_rdata_i_reg[28]_0 ,
\s_axi_rdata_i_reg[29]_0 ,
\s_axi_rdata_i_reg[30]_0 ,
\s_axi_rdata_i_reg[31]_0 ,
pair0_Select,
s_axi_wready,
s_axi_arready,
\s_axi_rdata_i_reg[11]_0 ,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
\LOAD_REG_GEN[31].LOAD_REG_I_0 ,
\LOAD_REG_GEN[30].LOAD_REG_I ,
\LOAD_REG_GEN[29].LOAD_REG_I ,
\LOAD_REG_GEN[28].LOAD_REG_I ,
\LOAD_REG_GEN[27].LOAD_REG_I ,
\LOAD_REG_GEN[26].LOAD_REG_I ,
\LOAD_REG_GEN[25].LOAD_REG_I ,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\LOAD_REG_GEN[23].LOAD_REG_I ,
\LOAD_REG_GEN[22].LOAD_REG_I ,
\LOAD_REG_GEN[21].LOAD_REG_I ,
\LOAD_REG_GEN[20].LOAD_REG_I ,
\LOAD_REG_GEN[19].LOAD_REG_I ,
\LOAD_REG_GEN[18].LOAD_REG_I ,
\LOAD_REG_GEN[17].LOAD_REG_I ,
\LOAD_REG_GEN[16].LOAD_REG_I ,
\LOAD_REG_GEN[15].LOAD_REG_I ,
\LOAD_REG_GEN[14].LOAD_REG_I ,
\LOAD_REG_GEN[13].LOAD_REG_I ,
\LOAD_REG_GEN[12].LOAD_REG_I ,
\LOAD_REG_GEN[11].LOAD_REG_I ,
\LOAD_REG_GEN[10].LOAD_REG_I ,
\LOAD_REG_GEN[9].LOAD_REG_I ,
\LOAD_REG_GEN[8].LOAD_REG_I ,
\LOAD_REG_GEN[7].LOAD_REG_I ,
\LOAD_REG_GEN[6].LOAD_REG_I ,
\LOAD_REG_GEN[5].LOAD_REG_I ,
\LOAD_REG_GEN[4].LOAD_REG_I ,
\LOAD_REG_GEN[3].LOAD_REG_I ,
\LOAD_REG_GEN[2].LOAD_REG_I ,
\LOAD_REG_GEN[1].LOAD_REG_I ,
D_0,
bus2ip_wrce__0,
bus2ip_wrce,
\LOAD_REG_GEN[31].LOAD_REG_I_1 ,
\LOAD_REG_GEN[30].LOAD_REG_I_0 ,
\LOAD_REG_GEN[29].LOAD_REG_I_0 ,
\LOAD_REG_GEN[28].LOAD_REG_I_0 ,
\LOAD_REG_GEN[27].LOAD_REG_I_0 ,
\LOAD_REG_GEN[26].LOAD_REG_I_0 ,
\LOAD_REG_GEN[25].LOAD_REG_I_0 ,
\LOAD_REG_GEN[24].LOAD_REG_I_0 ,
\LOAD_REG_GEN[23].LOAD_REG_I_0 ,
\LOAD_REG_GEN[22].LOAD_REG_I_0 ,
\LOAD_REG_GEN[21].LOAD_REG_I_0 ,
\LOAD_REG_GEN[20].LOAD_REG_I_0 ,
\LOAD_REG_GEN[19].LOAD_REG_I_0 ,
\LOAD_REG_GEN[18].LOAD_REG_I_0 ,
\LOAD_REG_GEN[17].LOAD_REG_I_0 ,
\LOAD_REG_GEN[16].LOAD_REG_I_0 ,
\LOAD_REG_GEN[15].LOAD_REG_I_0 ,
\LOAD_REG_GEN[14].LOAD_REG_I_0 ,
\LOAD_REG_GEN[13].LOAD_REG_I_0 ,
\LOAD_REG_GEN[12].LOAD_REG_I_0 ,
\LOAD_REG_GEN[11].LOAD_REG_I_0 ,
\LOAD_REG_GEN[10].LOAD_REG_I_0 ,
\LOAD_REG_GEN[9].LOAD_REG_I_0 ,
\LOAD_REG_GEN[8].LOAD_REG_I_0 ,
\LOAD_REG_GEN[7].LOAD_REG_I_0 ,
\LOAD_REG_GEN[6].LOAD_REG_I_0 ,
\LOAD_REG_GEN[5].LOAD_REG_I_0 ,
\LOAD_REG_GEN[4].LOAD_REG_I_0 ,
\LOAD_REG_GEN[3].LOAD_REG_I_0 ,
\LOAD_REG_GEN[2].LOAD_REG_I_0 ,
\LOAD_REG_GEN[1].LOAD_REG_I_0 ,
D_1,
s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_1,
s_axi_rvalid_i_reg_2,
\TCSR0_GENERATE[23].TCSR0_FF_I_0 ,
\TCSR1_GENERATE[23].TCSR1_FF_I ,
\s_axi_rdata_i_reg[10]_0 ,
\s_axi_rdata_i_reg[0]_0 ,
\s_axi_rdata_i_reg[0]_1 ,
READ_DONE0_I,
READ_DONE1_I,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
read_Mux_In,
s_axi_aresetn,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_rready,
s_axi_bready,
s_axi_wdata,
D_2,
read_done1,
D);
output \LOAD_REG_GEN[31].LOAD_REG_I ;
output \TCSR0_GENERATE[23].TCSR0_FF_I ;
output s_axi_rvalid;
output s_axi_bvalid;
output \s_axi_rdata_i_reg[12]_0 ;
output \s_axi_rdata_i_reg[13]_0 ;
output \s_axi_rdata_i_reg[14]_0 ;
output \s_axi_rdata_i_reg[15]_0 ;
output \s_axi_rdata_i_reg[16]_0 ;
output \s_axi_rdata_i_reg[17]_0 ;
output \s_axi_rdata_i_reg[18]_0 ;
output \s_axi_rdata_i_reg[19]_0 ;
output \s_axi_rdata_i_reg[20]_0 ;
output \s_axi_rdata_i_reg[21]_0 ;
output \s_axi_rdata_i_reg[22]_0 ;
output \s_axi_rdata_i_reg[23]_0 ;
output \s_axi_rdata_i_reg[24]_0 ;
output \s_axi_rdata_i_reg[25]_0 ;
output \s_axi_rdata_i_reg[26]_0 ;
output \s_axi_rdata_i_reg[27]_0 ;
output \s_axi_rdata_i_reg[28]_0 ;
output \s_axi_rdata_i_reg[29]_0 ;
output \s_axi_rdata_i_reg[30]_0 ;
output \s_axi_rdata_i_reg[31]_0 ;
output pair0_Select;
output s_axi_wready;
output s_axi_arready;
output \s_axi_rdata_i_reg[11]_0 ;
output \TCSR0_GENERATE[24].TCSR0_FF_I ;
output \TCSR1_GENERATE[24].TCSR1_FF_I ;
output \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[30].LOAD_REG_I ;
output \LOAD_REG_GEN[29].LOAD_REG_I ;
output \LOAD_REG_GEN[28].LOAD_REG_I ;
output \LOAD_REG_GEN[27].LOAD_REG_I ;
output \LOAD_REG_GEN[26].LOAD_REG_I ;
output \LOAD_REG_GEN[25].LOAD_REG_I ;
output \LOAD_REG_GEN[24].LOAD_REG_I ;
output \LOAD_REG_GEN[23].LOAD_REG_I ;
output \LOAD_REG_GEN[22].LOAD_REG_I ;
output \LOAD_REG_GEN[21].LOAD_REG_I ;
output \LOAD_REG_GEN[20].LOAD_REG_I ;
output \LOAD_REG_GEN[19].LOAD_REG_I ;
output \LOAD_REG_GEN[18].LOAD_REG_I ;
output \LOAD_REG_GEN[17].LOAD_REG_I ;
output \LOAD_REG_GEN[16].LOAD_REG_I ;
output \LOAD_REG_GEN[15].LOAD_REG_I ;
output \LOAD_REG_GEN[14].LOAD_REG_I ;
output \LOAD_REG_GEN[13].LOAD_REG_I ;
output \LOAD_REG_GEN[12].LOAD_REG_I ;
output \LOAD_REG_GEN[11].LOAD_REG_I ;
output \LOAD_REG_GEN[10].LOAD_REG_I ;
output \LOAD_REG_GEN[9].LOAD_REG_I ;
output \LOAD_REG_GEN[8].LOAD_REG_I ;
output \LOAD_REG_GEN[7].LOAD_REG_I ;
output \LOAD_REG_GEN[6].LOAD_REG_I ;
output \LOAD_REG_GEN[5].LOAD_REG_I ;
output \LOAD_REG_GEN[4].LOAD_REG_I ;
output \LOAD_REG_GEN[3].LOAD_REG_I ;
output \LOAD_REG_GEN[2].LOAD_REG_I ;
output \LOAD_REG_GEN[1].LOAD_REG_I ;
output D_0;
output [0:0]bus2ip_wrce__0;
output [1:0]bus2ip_wrce;
output \LOAD_REG_GEN[31].LOAD_REG_I_1 ;
output \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
output D_1;
output s_axi_rvalid_i_reg_0;
output s_axi_rvalid_i_reg_1;
output s_axi_rvalid_i_reg_2;
output \TCSR0_GENERATE[23].TCSR0_FF_I_0 ;
output \TCSR1_GENERATE[23].TCSR1_FF_I ;
output \s_axi_rdata_i_reg[10]_0 ;
output \s_axi_rdata_i_reg[0]_0 ;
output \s_axi_rdata_i_reg[0]_1 ;
output READ_DONE0_I;
output READ_DONE1_I;
output [31:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input [87:0]read_Mux_In;
input s_axi_aresetn;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_rready;
input s_axi_bready;
input [31:0]s_axi_wdata;
input D_2;
input read_done1;
input [31:0]D;
wire [31:0]D;
wire D_0;
wire D_1;
wire D_2;
wire [5:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire I_DECODER_n_100;
wire I_DECODER_n_101;
wire I_DECODER_n_25;
wire I_DECODER_n_26;
wire \LOAD_REG_GEN[10].LOAD_REG_I ;
wire \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[11].LOAD_REG_I ;
wire \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[12].LOAD_REG_I ;
wire \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[13].LOAD_REG_I ;
wire \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[14].LOAD_REG_I ;
wire \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[15].LOAD_REG_I ;
wire \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[16].LOAD_REG_I ;
wire \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[17].LOAD_REG_I ;
wire \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[18].LOAD_REG_I ;
wire \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[19].LOAD_REG_I ;
wire \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[1].LOAD_REG_I ;
wire \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[22].LOAD_REG_I ;
wire \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[23].LOAD_REG_I ;
wire \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[25].LOAD_REG_I ;
wire \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[26].LOAD_REG_I ;
wire \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[27].LOAD_REG_I ;
wire \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[28].LOAD_REG_I ;
wire \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[29].LOAD_REG_I ;
wire \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[2].LOAD_REG_I ;
wire \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[30].LOAD_REG_I ;
wire \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_1 ;
wire \LOAD_REG_GEN[3].LOAD_REG_I ;
wire \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[4].LOAD_REG_I ;
wire \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[5].LOAD_REG_I ;
wire \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[6].LOAD_REG_I ;
wire \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[7].LOAD_REG_I ;
wire \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[8].LOAD_REG_I ;
wire \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[9].LOAD_REG_I ;
wire \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
wire READ_DONE0_I;
wire READ_DONE1_I;
wire \TCSR0_GENERATE[23].TCSR0_FF_I ;
wire \TCSR0_GENERATE[23].TCSR0_FF_I_0 ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[23].TCSR1_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire [0:2]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[4]_i_1_n_0 ;
wire \bus2ip_addr_i[4]_i_2_n_0 ;
wire bus2ip_reset;
wire bus2ip_rnw_i;
wire bus2ip_rnw_i06_out;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire clear;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire pair0_Select;
wire [5:0]plusOp;
wire [87:0]read_Mux_In;
wire read_done1;
wire rst;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire \s_axi_rdata_i[31]_i_1_n_0 ;
wire \s_axi_rdata_i_reg[0]_0 ;
wire \s_axi_rdata_i_reg[0]_1 ;
wire \s_axi_rdata_i_reg[10]_0 ;
wire \s_axi_rdata_i_reg[11]_0 ;
wire \s_axi_rdata_i_reg[12]_0 ;
wire \s_axi_rdata_i_reg[13]_0 ;
wire \s_axi_rdata_i_reg[14]_0 ;
wire \s_axi_rdata_i_reg[15]_0 ;
wire \s_axi_rdata_i_reg[16]_0 ;
wire \s_axi_rdata_i_reg[17]_0 ;
wire \s_axi_rdata_i_reg[18]_0 ;
wire \s_axi_rdata_i_reg[19]_0 ;
wire \s_axi_rdata_i_reg[20]_0 ;
wire \s_axi_rdata_i_reg[21]_0 ;
wire \s_axi_rdata_i_reg[22]_0 ;
wire \s_axi_rdata_i_reg[23]_0 ;
wire \s_axi_rdata_i_reg[24]_0 ;
wire \s_axi_rdata_i_reg[25]_0 ;
wire \s_axi_rdata_i_reg[26]_0 ;
wire \s_axi_rdata_i_reg[27]_0 ;
wire \s_axi_rdata_i_reg[28]_0 ;
wire \s_axi_rdata_i_reg[29]_0 ;
wire \s_axi_rdata_i_reg[30]_0 ;
wire \s_axi_rdata_i_reg[31]_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_reg_0;
wire s_axi_rvalid_i_reg_1;
wire s_axi_rvalid_i_reg_2;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[1]_i_3_n_0 ;
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h7FFF8000))
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]),
.O(plusOp[4]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [5]),
.O(plusOp[5]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[4]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[5]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [5]),
.R(clear));
zqynq_lab_1_design_axi_timer_0_1_address_decoder I_DECODER
(.D({I_DECODER_n_25,I_DECODER_n_26}),
.D_0(D_0),
.D_1(D_1),
.D_2(D_2),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\LOAD_REG_GEN[10].LOAD_REG_I (\LOAD_REG_GEN[10].LOAD_REG_I ),
.\LOAD_REG_GEN[10].LOAD_REG_I_0 (\LOAD_REG_GEN[10].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[11].LOAD_REG_I (\LOAD_REG_GEN[11].LOAD_REG_I ),
.\LOAD_REG_GEN[11].LOAD_REG_I_0 (\LOAD_REG_GEN[11].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[12].LOAD_REG_I (\LOAD_REG_GEN[12].LOAD_REG_I ),
.\LOAD_REG_GEN[12].LOAD_REG_I_0 (\LOAD_REG_GEN[12].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[13].LOAD_REG_I (\LOAD_REG_GEN[13].LOAD_REG_I ),
.\LOAD_REG_GEN[13].LOAD_REG_I_0 (\LOAD_REG_GEN[13].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[14].LOAD_REG_I (\LOAD_REG_GEN[14].LOAD_REG_I ),
.\LOAD_REG_GEN[14].LOAD_REG_I_0 (\LOAD_REG_GEN[14].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[15].LOAD_REG_I (\LOAD_REG_GEN[15].LOAD_REG_I ),
.\LOAD_REG_GEN[15].LOAD_REG_I_0 (\LOAD_REG_GEN[15].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[16].LOAD_REG_I (\LOAD_REG_GEN[16].LOAD_REG_I ),
.\LOAD_REG_GEN[16].LOAD_REG_I_0 (\LOAD_REG_GEN[16].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[17].LOAD_REG_I (\LOAD_REG_GEN[17].LOAD_REG_I ),
.\LOAD_REG_GEN[17].LOAD_REG_I_0 (\LOAD_REG_GEN[17].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[18].LOAD_REG_I (\LOAD_REG_GEN[18].LOAD_REG_I ),
.\LOAD_REG_GEN[18].LOAD_REG_I_0 (\LOAD_REG_GEN[18].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[19].LOAD_REG_I (\LOAD_REG_GEN[19].LOAD_REG_I ),
.\LOAD_REG_GEN[19].LOAD_REG_I_0 (\LOAD_REG_GEN[19].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[1].LOAD_REG_I (\LOAD_REG_GEN[1].LOAD_REG_I ),
.\LOAD_REG_GEN[1].LOAD_REG_I_0 (\LOAD_REG_GEN[1].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[20].LOAD_REG_I (\LOAD_REG_GEN[20].LOAD_REG_I ),
.\LOAD_REG_GEN[20].LOAD_REG_I_0 (\LOAD_REG_GEN[20].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[21].LOAD_REG_I (\LOAD_REG_GEN[21].LOAD_REG_I ),
.\LOAD_REG_GEN[21].LOAD_REG_I_0 (\LOAD_REG_GEN[21].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[22].LOAD_REG_I (\LOAD_REG_GEN[22].LOAD_REG_I ),
.\LOAD_REG_GEN[22].LOAD_REG_I_0 (\LOAD_REG_GEN[22].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[23].LOAD_REG_I (\LOAD_REG_GEN[23].LOAD_REG_I ),
.\LOAD_REG_GEN[23].LOAD_REG_I_0 (\LOAD_REG_GEN[23].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[24].LOAD_REG_I (\LOAD_REG_GEN[24].LOAD_REG_I ),
.\LOAD_REG_GEN[24].LOAD_REG_I_0 (\LOAD_REG_GEN[24].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[25].LOAD_REG_I (\LOAD_REG_GEN[25].LOAD_REG_I ),
.\LOAD_REG_GEN[25].LOAD_REG_I_0 (\LOAD_REG_GEN[25].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[26].LOAD_REG_I (\LOAD_REG_GEN[26].LOAD_REG_I ),
.\LOAD_REG_GEN[26].LOAD_REG_I_0 (\LOAD_REG_GEN[26].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[27].LOAD_REG_I (\LOAD_REG_GEN[27].LOAD_REG_I ),
.\LOAD_REG_GEN[27].LOAD_REG_I_0 (\LOAD_REG_GEN[27].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[28].LOAD_REG_I (\LOAD_REG_GEN[28].LOAD_REG_I ),
.\LOAD_REG_GEN[28].LOAD_REG_I_0 (\LOAD_REG_GEN[28].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[29].LOAD_REG_I (\LOAD_REG_GEN[29].LOAD_REG_I ),
.\LOAD_REG_GEN[29].LOAD_REG_I_0 (\LOAD_REG_GEN[29].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[2].LOAD_REG_I (\LOAD_REG_GEN[2].LOAD_REG_I ),
.\LOAD_REG_GEN[2].LOAD_REG_I_0 (\LOAD_REG_GEN[2].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[30].LOAD_REG_I (\LOAD_REG_GEN[30].LOAD_REG_I ),
.\LOAD_REG_GEN[30].LOAD_REG_I_0 (\LOAD_REG_GEN[30].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[31].LOAD_REG_I (\LOAD_REG_GEN[31].LOAD_REG_I ),
.\LOAD_REG_GEN[31].LOAD_REG_I_0 (\LOAD_REG_GEN[31].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[31].LOAD_REG_I_1 (\LOAD_REG_GEN[31].LOAD_REG_I_1 ),
.\LOAD_REG_GEN[3].LOAD_REG_I (\LOAD_REG_GEN[3].LOAD_REG_I ),
.\LOAD_REG_GEN[3].LOAD_REG_I_0 (\LOAD_REG_GEN[3].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[4].LOAD_REG_I (\LOAD_REG_GEN[4].LOAD_REG_I ),
.\LOAD_REG_GEN[4].LOAD_REG_I_0 (\LOAD_REG_GEN[4].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[5].LOAD_REG_I (\LOAD_REG_GEN[5].LOAD_REG_I ),
.\LOAD_REG_GEN[5].LOAD_REG_I_0 (\LOAD_REG_GEN[5].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[6].LOAD_REG_I (\LOAD_REG_GEN[6].LOAD_REG_I ),
.\LOAD_REG_GEN[6].LOAD_REG_I_0 (\LOAD_REG_GEN[6].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[7].LOAD_REG_I (\LOAD_REG_GEN[7].LOAD_REG_I ),
.\LOAD_REG_GEN[7].LOAD_REG_I_0 (\LOAD_REG_GEN[7].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[8].LOAD_REG_I (\LOAD_REG_GEN[8].LOAD_REG_I ),
.\LOAD_REG_GEN[8].LOAD_REG_I_0 (\LOAD_REG_GEN[8].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[9].LOAD_REG_I (\LOAD_REG_GEN[9].LOAD_REG_I ),
.\LOAD_REG_GEN[9].LOAD_REG_I_0 (\LOAD_REG_GEN[9].LOAD_REG_I_0 ),
.Q(start2),
.READ_DONE0_I(READ_DONE0_I),
.READ_DONE1_I(READ_DONE1_I),
.\TCSR0_GENERATE[23].TCSR0_FF_I (\TCSR0_GENERATE[23].TCSR0_FF_I ),
.\TCSR0_GENERATE[23].TCSR0_FF_I_0 (\TCSR0_GENERATE[23].TCSR0_FF_I_0 ),
.\TCSR0_GENERATE[24].TCSR0_FF_I (\TCSR0_GENERATE[24].TCSR0_FF_I ),
.\TCSR1_GENERATE[23].TCSR1_FF_I (\TCSR1_GENERATE[23].TCSR1_FF_I ),
.\TCSR1_GENERATE[24].TCSR1_FF_I (\TCSR1_GENERATE[24].TCSR1_FF_I ),
.\bus2ip_addr_i_reg[4] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2]}),
.bus2ip_rnw_i(bus2ip_rnw_i),
.bus2ip_wrce(bus2ip_wrce),
.bus2ip_wrce__0(bus2ip_wrce__0),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.pair0_Select(pair0_Select),
.read_Mux_In(read_Mux_In),
.read_done1(read_done1),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arvalid_0(\state[1]_i_3_n_0 ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid_i_reg(I_DECODER_n_101),
.s_axi_bvalid_i_reg_0(s_axi_bvalid),
.\s_axi_rdata_i_reg[0] (\s_axi_rdata_i_reg[0]_0 ),
.\s_axi_rdata_i_reg[0]_0 (\s_axi_rdata_i_reg[0]_1 ),
.\s_axi_rdata_i_reg[10] (\s_axi_rdata_i_reg[10]_0 ),
.\s_axi_rdata_i_reg[11] (\s_axi_rdata_i_reg[11]_0 ),
.\s_axi_rdata_i_reg[12] (\s_axi_rdata_i_reg[12]_0 ),
.\s_axi_rdata_i_reg[13] (\s_axi_rdata_i_reg[13]_0 ),
.\s_axi_rdata_i_reg[14] (\s_axi_rdata_i_reg[14]_0 ),
.\s_axi_rdata_i_reg[15] (\s_axi_rdata_i_reg[15]_0 ),
.\s_axi_rdata_i_reg[16] (\s_axi_rdata_i_reg[16]_0 ),
.\s_axi_rdata_i_reg[17] (\s_axi_rdata_i_reg[17]_0 ),
.\s_axi_rdata_i_reg[18] (\s_axi_rdata_i_reg[18]_0 ),
.\s_axi_rdata_i_reg[19] (\s_axi_rdata_i_reg[19]_0 ),
.\s_axi_rdata_i_reg[20] (\s_axi_rdata_i_reg[20]_0 ),
.\s_axi_rdata_i_reg[21] (\s_axi_rdata_i_reg[21]_0 ),
.\s_axi_rdata_i_reg[22] (\s_axi_rdata_i_reg[22]_0 ),
.\s_axi_rdata_i_reg[23] (\s_axi_rdata_i_reg[23]_0 ),
.\s_axi_rdata_i_reg[24] (\s_axi_rdata_i_reg[24]_0 ),
.\s_axi_rdata_i_reg[25] (\s_axi_rdata_i_reg[25]_0 ),
.\s_axi_rdata_i_reg[26] (\s_axi_rdata_i_reg[26]_0 ),
.\s_axi_rdata_i_reg[27] (\s_axi_rdata_i_reg[27]_0 ),
.\s_axi_rdata_i_reg[28] (\s_axi_rdata_i_reg[28]_0 ),
.\s_axi_rdata_i_reg[29] (\s_axi_rdata_i_reg[29]_0 ),
.\s_axi_rdata_i_reg[30] (\s_axi_rdata_i_reg[30]_0 ),
.\s_axi_rdata_i_reg[31] (\s_axi_rdata_i_reg[31]_0 ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid_i_reg(s_axi_rvalid_i_reg_0),
.s_axi_rvalid_i_reg_0(s_axi_rvalid_i_reg_1),
.s_axi_rvalid_i_reg_1(s_axi_rvalid_i_reg_2),
.s_axi_rvalid_i_reg_2(I_DECODER_n_100),
.s_axi_rvalid_i_reg_3(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.state1__2(state1__2),
.\state_reg[1] (state));
LUT5 #(
.INIT(32'hFEFF0200))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_arvalid),
.I4(s_axi_awaddr[0]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFEFF0200))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_arvalid),
.I4(s_axi_awaddr[1]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'hFEFF0200))
\bus2ip_addr_i[4]_i_2
(.I0(s_axi_araddr[2]),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_arvalid),
.I4(s_axi_awaddr[2]),
.O(\bus2ip_addr_i[4]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[4]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[2]),
.R(rst));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[4]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[1]),
.R(rst));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[4]_i_1_n_0 ),
.D(\bus2ip_addr_i[4]_i_2_n_0 ),
.Q(bus2ip_addr[0]),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h10))
bus2ip_rnw_i_i_1
(.I0(state[0]),
.I1(state[1]),
.I2(s_axi_arvalid),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[4]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(bus2ip_rnw_i),
.R(rst));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(rst));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(rst));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus2ip_reset),
.Q(rst),
.R(1'b0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_101),
.Q(s_axi_bvalid),
.R(rst));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\s_axi_rdata_i[31]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[0]),
.Q(s_axi_rdata[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[10]),
.Q(s_axi_rdata[10]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[11]),
.Q(s_axi_rdata[11]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[12]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[12]),
.Q(s_axi_rdata[12]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[13]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[13]),
.Q(s_axi_rdata[13]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[14]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[14]),
.Q(s_axi_rdata[14]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[15]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[15]),
.Q(s_axi_rdata[15]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[16]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[16]),
.Q(s_axi_rdata[16]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[17]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[17]),
.Q(s_axi_rdata[17]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[18]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[18]),
.Q(s_axi_rdata[18]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[19]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[19]),
.Q(s_axi_rdata[19]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[1]),
.Q(s_axi_rdata[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[20]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[20]),
.Q(s_axi_rdata[20]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[21]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[21]),
.Q(s_axi_rdata[21]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[22]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[22]),
.Q(s_axi_rdata[22]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[23]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[23]),
.Q(s_axi_rdata[23]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[24]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[24]),
.Q(s_axi_rdata[24]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[25]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[25]),
.Q(s_axi_rdata[25]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[26]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[26]),
.Q(s_axi_rdata[26]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[27]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[27]),
.Q(s_axi_rdata[27]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[28]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[28]),
.Q(s_axi_rdata[28]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[29]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[29]),
.Q(s_axi_rdata[29]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[2]),
.Q(s_axi_rdata[2]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[30]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[30]),
.Q(s_axi_rdata[30]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[31]),
.Q(s_axi_rdata[31]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[3]),
.Q(s_axi_rdata[3]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[4]),
.Q(s_axi_rdata[4]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[5]),
.Q(s_axi_rdata[5]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[6]),
.Q(s_axi_rdata[6]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[7]),
.Q(s_axi_rdata[7]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[8]),
.Q(s_axi_rdata[8]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[9]),
.Q(s_axi_rdata[9]),
.R(rst));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_100),
.Q(s_axi_rvalid),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(rst));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_26),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_25),
.Q(state[1]),
.R(rst));
endmodule
(* ORIG_REF_NAME = "tc_core" *)
module zqynq_lab_1_design_axi_timer_0_1_tc_core
(D,
\INFERRED_GEN.icount_out_reg[0] ,
bus2ip_reset,
generateout0,
generateout1,
interrupt,
D_0,
read_done1,
pwm0,
Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_4,
Bus_RNW_reg_reg_5,
Bus_RNW_reg_reg_6,
Bus_RNW_reg_reg_7,
Bus_RNW_reg_reg_8,
Bus_RNW_reg_reg_9,
Bus_RNW_reg_reg_10,
Bus_RNW_reg_reg_11,
Bus_RNW_reg_reg_12,
Bus_RNW_reg_reg_13,
Bus_RNW_reg_reg_14,
Bus_RNW_reg_reg_15,
Bus_RNW_reg_reg_16,
Bus_RNW_reg_reg_17,
Bus_RNW_reg_reg_18,
\LOAD_REG_GEN[20].LOAD_REG_I ,
D_1,
s_axi_aclk,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ,
D_2,
\INFERRED_GEN.icount_out_reg[30] ,
\INFERRED_GEN.icount_out_reg[29] ,
\INFERRED_GEN.icount_out_reg[28] ,
\INFERRED_GEN.icount_out_reg[27] ,
\INFERRED_GEN.icount_out_reg[26] ,
\INFERRED_GEN.icount_out_reg[25] ,
\INFERRED_GEN.icount_out_reg[24] ,
\INFERRED_GEN.icount_out_reg[23] ,
\INFERRED_GEN.icount_out_reg[22] ,
\INFERRED_GEN.icount_out_reg[21] ,
\INFERRED_GEN.icount_out_reg[20] ,
\INFERRED_GEN.icount_out_reg[19] ,
\INFERRED_GEN.icount_out_reg[18] ,
\INFERRED_GEN.icount_out_reg[17] ,
\INFERRED_GEN.icount_out_reg[16] ,
\INFERRED_GEN.icount_out_reg[15] ,
\INFERRED_GEN.icount_out_reg[14] ,
\INFERRED_GEN.icount_out_reg[13] ,
\INFERRED_GEN.icount_out_reg[12] ,
\INFERRED_GEN.icount_out_reg[11] ,
\INFERRED_GEN.icount_out_reg[10] ,
\INFERRED_GEN.icount_out_reg[9] ,
\INFERRED_GEN.icount_out_reg[8] ,
\INFERRED_GEN.icount_out_reg[7] ,
\INFERRED_GEN.icount_out_reg[6] ,
\INFERRED_GEN.icount_out_reg[5] ,
\INFERRED_GEN.icount_out_reg[4] ,
\INFERRED_GEN.icount_out_reg[3] ,
\INFERRED_GEN.icount_out_reg[2] ,
\INFERRED_GEN.icount_out_reg[1] ,
\INFERRED_GEN.icount_out_reg[0]_0 ,
bus2ip_wrce,
s_axi_wdata,
pair0_Select,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
bus2ip_wrce__0,
freeze,
capturetrig0,
capturetrig1);
output [31:0]D;
output [87:0]\INFERRED_GEN.icount_out_reg[0] ;
output bus2ip_reset;
output generateout0;
output generateout1;
output interrupt;
output D_0;
output read_done1;
output pwm0;
input Bus_RNW_reg_reg;
input Bus_RNW_reg_reg_0;
input Bus_RNW_reg_reg_1;
input Bus_RNW_reg_reg_2;
input Bus_RNW_reg_reg_3;
input Bus_RNW_reg_reg_4;
input Bus_RNW_reg_reg_5;
input Bus_RNW_reg_reg_6;
input Bus_RNW_reg_reg_7;
input Bus_RNW_reg_reg_8;
input Bus_RNW_reg_reg_9;
input Bus_RNW_reg_reg_10;
input Bus_RNW_reg_reg_11;
input Bus_RNW_reg_reg_12;
input Bus_RNW_reg_reg_13;
input Bus_RNW_reg_reg_14;
input Bus_RNW_reg_reg_15;
input Bus_RNW_reg_reg_16;
input Bus_RNW_reg_reg_17;
input Bus_RNW_reg_reg_18;
input \LOAD_REG_GEN[20].LOAD_REG_I ;
input D_1;
input s_axi_aclk;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ;
input D_2;
input \INFERRED_GEN.icount_out_reg[30] ;
input \INFERRED_GEN.icount_out_reg[29] ;
input \INFERRED_GEN.icount_out_reg[28] ;
input \INFERRED_GEN.icount_out_reg[27] ;
input \INFERRED_GEN.icount_out_reg[26] ;
input \INFERRED_GEN.icount_out_reg[25] ;
input \INFERRED_GEN.icount_out_reg[24] ;
input \INFERRED_GEN.icount_out_reg[23] ;
input \INFERRED_GEN.icount_out_reg[22] ;
input \INFERRED_GEN.icount_out_reg[21] ;
input \INFERRED_GEN.icount_out_reg[20] ;
input \INFERRED_GEN.icount_out_reg[19] ;
input \INFERRED_GEN.icount_out_reg[18] ;
input \INFERRED_GEN.icount_out_reg[17] ;
input \INFERRED_GEN.icount_out_reg[16] ;
input \INFERRED_GEN.icount_out_reg[15] ;
input \INFERRED_GEN.icount_out_reg[14] ;
input \INFERRED_GEN.icount_out_reg[13] ;
input \INFERRED_GEN.icount_out_reg[12] ;
input \INFERRED_GEN.icount_out_reg[11] ;
input \INFERRED_GEN.icount_out_reg[10] ;
input \INFERRED_GEN.icount_out_reg[9] ;
input \INFERRED_GEN.icount_out_reg[8] ;
input \INFERRED_GEN.icount_out_reg[7] ;
input \INFERRED_GEN.icount_out_reg[6] ;
input \INFERRED_GEN.icount_out_reg[5] ;
input \INFERRED_GEN.icount_out_reg[4] ;
input \INFERRED_GEN.icount_out_reg[3] ;
input \INFERRED_GEN.icount_out_reg[2] ;
input \INFERRED_GEN.icount_out_reg[1] ;
input \INFERRED_GEN.icount_out_reg[0]_0 ;
input [1:0]bus2ip_wrce;
input [9:0]s_axi_wdata;
input pair0_Select;
input \TCSR0_GENERATE[24].TCSR0_FF_I ;
input \TCSR1_GENERATE[24].TCSR1_FF_I ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input [0:0]bus2ip_wrce__0;
input freeze;
input capturetrig0;
input capturetrig1;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire Bus_RNW_reg_reg_10;
wire Bus_RNW_reg_reg_11;
wire Bus_RNW_reg_reg_12;
wire Bus_RNW_reg_reg_13;
wire Bus_RNW_reg_reg_14;
wire Bus_RNW_reg_reg_15;
wire Bus_RNW_reg_reg_16;
wire Bus_RNW_reg_reg_17;
wire Bus_RNW_reg_reg_18;
wire Bus_RNW_reg_reg_2;
wire Bus_RNW_reg_reg_3;
wire Bus_RNW_reg_reg_4;
wire Bus_RNW_reg_reg_5;
wire Bus_RNW_reg_reg_6;
wire Bus_RNW_reg_reg_7;
wire Bus_RNW_reg_reg_8;
wire Bus_RNW_reg_reg_9;
wire COUNTER_0_I_n_64;
wire [31:0]D;
wire D_0;
wire D_1;
wire D_2;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ;
wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_33 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_34 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_35 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_36 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_37 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_38 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_39 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_40 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_41 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_42 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_43 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_44 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_45 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_46 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_47 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_48 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_49 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_50 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_51 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_52 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_53 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_54 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_55 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_56 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_57 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_58 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_59 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_60 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_61 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_62 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_63 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_64 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_65 ;
wire [87:0]\INFERRED_GEN.icount_out_reg[0] ;
wire \INFERRED_GEN.icount_out_reg[0]_0 ;
wire \INFERRED_GEN.icount_out_reg[10] ;
wire \INFERRED_GEN.icount_out_reg[11] ;
wire \INFERRED_GEN.icount_out_reg[12] ;
wire \INFERRED_GEN.icount_out_reg[13] ;
wire \INFERRED_GEN.icount_out_reg[14] ;
wire \INFERRED_GEN.icount_out_reg[15] ;
wire \INFERRED_GEN.icount_out_reg[16] ;
wire \INFERRED_GEN.icount_out_reg[17] ;
wire \INFERRED_GEN.icount_out_reg[18] ;
wire \INFERRED_GEN.icount_out_reg[19] ;
wire \INFERRED_GEN.icount_out_reg[1] ;
wire \INFERRED_GEN.icount_out_reg[20] ;
wire \INFERRED_GEN.icount_out_reg[21] ;
wire \INFERRED_GEN.icount_out_reg[22] ;
wire \INFERRED_GEN.icount_out_reg[23] ;
wire \INFERRED_GEN.icount_out_reg[24] ;
wire \INFERRED_GEN.icount_out_reg[25] ;
wire \INFERRED_GEN.icount_out_reg[26] ;
wire \INFERRED_GEN.icount_out_reg[27] ;
wire \INFERRED_GEN.icount_out_reg[28] ;
wire \INFERRED_GEN.icount_out_reg[29] ;
wire \INFERRED_GEN.icount_out_reg[2] ;
wire \INFERRED_GEN.icount_out_reg[30] ;
wire \INFERRED_GEN.icount_out_reg[3] ;
wire \INFERRED_GEN.icount_out_reg[4] ;
wire \INFERRED_GEN.icount_out_reg[5] ;
wire \INFERRED_GEN.icount_out_reg[6] ;
wire \INFERRED_GEN.icount_out_reg[7] ;
wire \INFERRED_GEN.icount_out_reg[8] ;
wire \INFERRED_GEN.icount_out_reg[9] ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire R;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire TIMER_CONTROL_I_n_12;
wire TIMER_CONTROL_I_n_13;
wire TIMER_CONTROL_I_n_14;
wire TIMER_CONTROL_I_n_15;
wire TIMER_CONTROL_I_n_16;
wire TIMER_CONTROL_I_n_17;
wire TIMER_CONTROL_I_n_18;
wire TIMER_CONTROL_I_n_19;
wire TIMER_CONTROL_I_n_20;
wire TIMER_CONTROL_I_n_21;
wire TIMER_CONTROL_I_n_22;
wire TIMER_CONTROL_I_n_24;
wire TIMER_CONTROL_I_n_25;
wire TIMER_CONTROL_I_n_26;
wire TIMER_CONTROL_I_n_27;
wire TIMER_CONTROL_I_n_28;
wire TIMER_CONTROL_I_n_29;
wire TIMER_CONTROL_I_n_3;
wire TIMER_CONTROL_I_n_30;
wire TIMER_CONTROL_I_n_4;
wire bus2ip_reset;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire capturetrig0;
wire capturetrig1;
wire [0:1]counter_TC;
wire freeze;
wire generateout0;
wire generateout1;
wire interrupt;
wire [0:1]load_Counter_Reg;
wire pair0_Select;
wire pwm0;
wire [85:95]read_Mux_In;
wire read_done1;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [9:0]s_axi_wdata;
zqynq_lab_1_design_axi_timer_0_1_count_module COUNTER_0_I
(.D_1(D_1),
.E(TIMER_CONTROL_I_n_24),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ),
.\INFERRED_GEN.icount_out_reg[31] (\INFERRED_GEN.icount_out_reg[0] [84:32]),
.Q(TIMER_CONTROL_I_n_3),
.S(TIMER_CONTROL_I_n_27),
.\TCSR0_GENERATE[27].TCSR0_FF_I (TIMER_CONTROL_I_n_28),
.counter_TC(counter_TC[0]),
.generateOutPre0_reg(COUNTER_0_I_n_64),
.load_Counter_Reg(load_Counter_Reg[0]),
.read_Mux_In({read_Mux_In[85],read_Mux_In[86],read_Mux_In[87],read_Mux_In[88],read_Mux_In[89],read_Mux_In[90],read_Mux_In[91],read_Mux_In[92],read_Mux_In[93],read_Mux_In[94],read_Mux_In[95]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(bus2ip_reset));
zqynq_lab_1_design_axi_timer_0_1_count_module_0 \GEN_SECOND_TIMER.COUNTER_1_I
(.D_2(D_2),
.E(TIMER_CONTROL_I_n_25),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] (\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ),
.\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] (\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.\INFERRED_GEN.icount_out_reg[0] (\INFERRED_GEN.icount_out_reg[0]_0 ),
.\INFERRED_GEN.icount_out_reg[10] (\INFERRED_GEN.icount_out_reg[10] ),
.\INFERRED_GEN.icount_out_reg[11] (\INFERRED_GEN.icount_out_reg[11] ),
.\INFERRED_GEN.icount_out_reg[12] (\INFERRED_GEN.icount_out_reg[12] ),
.\INFERRED_GEN.icount_out_reg[13] (\INFERRED_GEN.icount_out_reg[13] ),
.\INFERRED_GEN.icount_out_reg[14] (\INFERRED_GEN.icount_out_reg[14] ),
.\INFERRED_GEN.icount_out_reg[15] (\INFERRED_GEN.icount_out_reg[15] ),
.\INFERRED_GEN.icount_out_reg[16] (\INFERRED_GEN.icount_out_reg[16] ),
.\INFERRED_GEN.icount_out_reg[17] (\INFERRED_GEN.icount_out_reg[17] ),
.\INFERRED_GEN.icount_out_reg[18] (\INFERRED_GEN.icount_out_reg[18] ),
.\INFERRED_GEN.icount_out_reg[19] (\INFERRED_GEN.icount_out_reg[19] ),
.\INFERRED_GEN.icount_out_reg[1] (\INFERRED_GEN.icount_out_reg[1] ),
.\INFERRED_GEN.icount_out_reg[20] (\INFERRED_GEN.icount_out_reg[20] ),
.\INFERRED_GEN.icount_out_reg[21] (\INFERRED_GEN.icount_out_reg[21] ),
.\INFERRED_GEN.icount_out_reg[22] (\INFERRED_GEN.icount_out_reg[22] ),
.\INFERRED_GEN.icount_out_reg[23] (\INFERRED_GEN.icount_out_reg[23] ),
.\INFERRED_GEN.icount_out_reg[24] (\INFERRED_GEN.icount_out_reg[24] ),
.\INFERRED_GEN.icount_out_reg[25] (\INFERRED_GEN.icount_out_reg[25] ),
.\INFERRED_GEN.icount_out_reg[26] (\INFERRED_GEN.icount_out_reg[26] ),
.\INFERRED_GEN.icount_out_reg[27] (\INFERRED_GEN.icount_out_reg[27] ),
.\INFERRED_GEN.icount_out_reg[28] (\INFERRED_GEN.icount_out_reg[28] ),
.\INFERRED_GEN.icount_out_reg[29] (\INFERRED_GEN.icount_out_reg[29] ),
.\INFERRED_GEN.icount_out_reg[2] (\INFERRED_GEN.icount_out_reg[2] ),
.\INFERRED_GEN.icount_out_reg[30] (\INFERRED_GEN.icount_out_reg[30] ),
.\INFERRED_GEN.icount_out_reg[31] (bus2ip_reset),
.\INFERRED_GEN.icount_out_reg[31]_0 (\INFERRED_GEN.icount_out_reg[0] [63:32]),
.\INFERRED_GEN.icount_out_reg[3] (\INFERRED_GEN.icount_out_reg[3] ),
.\INFERRED_GEN.icount_out_reg[4] (\INFERRED_GEN.icount_out_reg[4] ),
.\INFERRED_GEN.icount_out_reg[5] (\INFERRED_GEN.icount_out_reg[5] ),
.\INFERRED_GEN.icount_out_reg[6] (\INFERRED_GEN.icount_out_reg[6] ),
.\INFERRED_GEN.icount_out_reg[7] (\INFERRED_GEN.icount_out_reg[7] ),
.\INFERRED_GEN.icount_out_reg[8] (\INFERRED_GEN.icount_out_reg[8] ),
.\INFERRED_GEN.icount_out_reg[9] (\INFERRED_GEN.icount_out_reg[9] ),
.Q(\INFERRED_GEN.icount_out_reg[0] [31:0]),
.S(TIMER_CONTROL_I_n_30),
.\TCSR0_GENERATE[20].TCSR0_FF_I (TIMER_CONTROL_I_n_29),
.counter_TC(counter_TC[1]),
.\counter_TC_Reg_reg[1] (TIMER_CONTROL_I_n_4),
.generateOutPre1_reg(\GEN_SECOND_TIMER.COUNTER_1_I_n_65 ),
.load_Counter_Reg(load_Counter_Reg[1]),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.\s_axi_rdata_i_reg[0] (\GEN_SECOND_TIMER.COUNTER_1_I_n_33 ),
.\s_axi_rdata_i_reg[10] (\GEN_SECOND_TIMER.COUNTER_1_I_n_43 ),
.\s_axi_rdata_i_reg[11] (\GEN_SECOND_TIMER.COUNTER_1_I_n_44 ),
.\s_axi_rdata_i_reg[12] (\GEN_SECOND_TIMER.COUNTER_1_I_n_45 ),
.\s_axi_rdata_i_reg[13] (\GEN_SECOND_TIMER.COUNTER_1_I_n_46 ),
.\s_axi_rdata_i_reg[14] (\GEN_SECOND_TIMER.COUNTER_1_I_n_47 ),
.\s_axi_rdata_i_reg[15] (\GEN_SECOND_TIMER.COUNTER_1_I_n_48 ),
.\s_axi_rdata_i_reg[16] (\GEN_SECOND_TIMER.COUNTER_1_I_n_49 ),
.\s_axi_rdata_i_reg[17] (\GEN_SECOND_TIMER.COUNTER_1_I_n_50 ),
.\s_axi_rdata_i_reg[18] (\GEN_SECOND_TIMER.COUNTER_1_I_n_51 ),
.\s_axi_rdata_i_reg[19] (\GEN_SECOND_TIMER.COUNTER_1_I_n_52 ),
.\s_axi_rdata_i_reg[1] (\GEN_SECOND_TIMER.COUNTER_1_I_n_34 ),
.\s_axi_rdata_i_reg[20] (\GEN_SECOND_TIMER.COUNTER_1_I_n_53 ),
.\s_axi_rdata_i_reg[21] (\GEN_SECOND_TIMER.COUNTER_1_I_n_54 ),
.\s_axi_rdata_i_reg[22] (\GEN_SECOND_TIMER.COUNTER_1_I_n_55 ),
.\s_axi_rdata_i_reg[23] (\GEN_SECOND_TIMER.COUNTER_1_I_n_56 ),
.\s_axi_rdata_i_reg[24] (\GEN_SECOND_TIMER.COUNTER_1_I_n_57 ),
.\s_axi_rdata_i_reg[25] (\GEN_SECOND_TIMER.COUNTER_1_I_n_58 ),
.\s_axi_rdata_i_reg[26] (\GEN_SECOND_TIMER.COUNTER_1_I_n_59 ),
.\s_axi_rdata_i_reg[27] (\GEN_SECOND_TIMER.COUNTER_1_I_n_60 ),
.\s_axi_rdata_i_reg[28] (\GEN_SECOND_TIMER.COUNTER_1_I_n_61 ),
.\s_axi_rdata_i_reg[29] (\GEN_SECOND_TIMER.COUNTER_1_I_n_62 ),
.\s_axi_rdata_i_reg[2] (\GEN_SECOND_TIMER.COUNTER_1_I_n_35 ),
.\s_axi_rdata_i_reg[30] (\GEN_SECOND_TIMER.COUNTER_1_I_n_63 ),
.\s_axi_rdata_i_reg[31] (\GEN_SECOND_TIMER.COUNTER_1_I_n_64 ),
.\s_axi_rdata_i_reg[3] (\GEN_SECOND_TIMER.COUNTER_1_I_n_36 ),
.\s_axi_rdata_i_reg[4] (\GEN_SECOND_TIMER.COUNTER_1_I_n_37 ),
.\s_axi_rdata_i_reg[5] (\GEN_SECOND_TIMER.COUNTER_1_I_n_38 ),
.\s_axi_rdata_i_reg[6] (\GEN_SECOND_TIMER.COUNTER_1_I_n_39 ),
.\s_axi_rdata_i_reg[7] (\GEN_SECOND_TIMER.COUNTER_1_I_n_40 ),
.\s_axi_rdata_i_reg[8] (\GEN_SECOND_TIMER.COUNTER_1_I_n_41 ),
.\s_axi_rdata_i_reg[9] (\GEN_SECOND_TIMER.COUNTER_1_I_n_42 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
PWM_FF_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(TIMER_CONTROL_I_n_26),
.Q(pwm0),
.R(R));
zqynq_lab_1_design_axi_timer_0_1_mux_onehot_f READ_MUX_I
(.Bus_RNW_reg_reg(Bus_RNW_reg_reg),
.Bus_RNW_reg_reg_0(Bus_RNW_reg_reg_0),
.Bus_RNW_reg_reg_1(Bus_RNW_reg_reg_1),
.Bus_RNW_reg_reg_10(Bus_RNW_reg_reg_10),
.Bus_RNW_reg_reg_11(Bus_RNW_reg_reg_11),
.Bus_RNW_reg_reg_12(Bus_RNW_reg_reg_12),
.Bus_RNW_reg_reg_13(Bus_RNW_reg_reg_13),
.Bus_RNW_reg_reg_14(Bus_RNW_reg_reg_14),
.Bus_RNW_reg_reg_15(Bus_RNW_reg_reg_15),
.Bus_RNW_reg_reg_16(Bus_RNW_reg_reg_16),
.Bus_RNW_reg_reg_17(Bus_RNW_reg_reg_17),
.Bus_RNW_reg_reg_18(Bus_RNW_reg_reg_18),
.Bus_RNW_reg_reg_2(Bus_RNW_reg_reg_2),
.Bus_RNW_reg_reg_3(Bus_RNW_reg_reg_3),
.Bus_RNW_reg_reg_4(Bus_RNW_reg_reg_4),
.Bus_RNW_reg_reg_5(Bus_RNW_reg_reg_5),
.Bus_RNW_reg_reg_6(Bus_RNW_reg_reg_6),
.Bus_RNW_reg_reg_7(Bus_RNW_reg_reg_7),
.Bus_RNW_reg_reg_8(Bus_RNW_reg_reg_8),
.Bus_RNW_reg_reg_9(Bus_RNW_reg_reg_9),
.D(D),
.\INFERRED_GEN.icount_out_reg[0] (\GEN_SECOND_TIMER.COUNTER_1_I_n_33 ),
.\INFERRED_GEN.icount_out_reg[10] (\GEN_SECOND_TIMER.COUNTER_1_I_n_43 ),
.\INFERRED_GEN.icount_out_reg[11] (\GEN_SECOND_TIMER.COUNTER_1_I_n_44 ),
.\INFERRED_GEN.icount_out_reg[12] (\GEN_SECOND_TIMER.COUNTER_1_I_n_45 ),
.\INFERRED_GEN.icount_out_reg[13] (\GEN_SECOND_TIMER.COUNTER_1_I_n_46 ),
.\INFERRED_GEN.icount_out_reg[14] (\GEN_SECOND_TIMER.COUNTER_1_I_n_47 ),
.\INFERRED_GEN.icount_out_reg[15] (\GEN_SECOND_TIMER.COUNTER_1_I_n_48 ),
.\INFERRED_GEN.icount_out_reg[16] (\GEN_SECOND_TIMER.COUNTER_1_I_n_49 ),
.\INFERRED_GEN.icount_out_reg[17] (\GEN_SECOND_TIMER.COUNTER_1_I_n_50 ),
.\INFERRED_GEN.icount_out_reg[18] (\GEN_SECOND_TIMER.COUNTER_1_I_n_51 ),
.\INFERRED_GEN.icount_out_reg[19] (\GEN_SECOND_TIMER.COUNTER_1_I_n_52 ),
.\INFERRED_GEN.icount_out_reg[1] (\GEN_SECOND_TIMER.COUNTER_1_I_n_34 ),
.\INFERRED_GEN.icount_out_reg[20] (\GEN_SECOND_TIMER.COUNTER_1_I_n_53 ),
.\INFERRED_GEN.icount_out_reg[21] (\GEN_SECOND_TIMER.COUNTER_1_I_n_54 ),
.\INFERRED_GEN.icount_out_reg[22] (\GEN_SECOND_TIMER.COUNTER_1_I_n_55 ),
.\INFERRED_GEN.icount_out_reg[23] (\GEN_SECOND_TIMER.COUNTER_1_I_n_56 ),
.\INFERRED_GEN.icount_out_reg[24] (\GEN_SECOND_TIMER.COUNTER_1_I_n_57 ),
.\INFERRED_GEN.icount_out_reg[25] (\GEN_SECOND_TIMER.COUNTER_1_I_n_58 ),
.\INFERRED_GEN.icount_out_reg[26] (\GEN_SECOND_TIMER.COUNTER_1_I_n_59 ),
.\INFERRED_GEN.icount_out_reg[27] (\GEN_SECOND_TIMER.COUNTER_1_I_n_60 ),
.\INFERRED_GEN.icount_out_reg[28] (\GEN_SECOND_TIMER.COUNTER_1_I_n_61 ),
.\INFERRED_GEN.icount_out_reg[29] (\GEN_SECOND_TIMER.COUNTER_1_I_n_62 ),
.\INFERRED_GEN.icount_out_reg[2] (\GEN_SECOND_TIMER.COUNTER_1_I_n_35 ),
.\INFERRED_GEN.icount_out_reg[30] (\GEN_SECOND_TIMER.COUNTER_1_I_n_63 ),
.\INFERRED_GEN.icount_out_reg[31] (\GEN_SECOND_TIMER.COUNTER_1_I_n_64 ),
.\INFERRED_GEN.icount_out_reg[3] (\GEN_SECOND_TIMER.COUNTER_1_I_n_36 ),
.\INFERRED_GEN.icount_out_reg[4] (\GEN_SECOND_TIMER.COUNTER_1_I_n_37 ),
.\INFERRED_GEN.icount_out_reg[5] (\GEN_SECOND_TIMER.COUNTER_1_I_n_38 ),
.\INFERRED_GEN.icount_out_reg[6] (\GEN_SECOND_TIMER.COUNTER_1_I_n_39 ),
.\INFERRED_GEN.icount_out_reg[7] (\GEN_SECOND_TIMER.COUNTER_1_I_n_40 ),
.\INFERRED_GEN.icount_out_reg[8] (\GEN_SECOND_TIMER.COUNTER_1_I_n_41 ),
.\INFERRED_GEN.icount_out_reg[9] (\GEN_SECOND_TIMER.COUNTER_1_I_n_42 ),
.\LOAD_REG_GEN[20].LOAD_REG_I (\LOAD_REG_GEN[20].LOAD_REG_I ),
.\LOAD_REG_GEN[21].LOAD_REG_I (TIMER_CONTROL_I_n_22),
.\LOAD_REG_GEN[22].LOAD_REG_I (TIMER_CONTROL_I_n_21),
.\LOAD_REG_GEN[23].LOAD_REG_I (TIMER_CONTROL_I_n_20),
.\LOAD_REG_GEN[24].LOAD_REG_I (TIMER_CONTROL_I_n_19),
.\LOAD_REG_GEN[25].LOAD_REG_I (TIMER_CONTROL_I_n_18),
.\LOAD_REG_GEN[26].LOAD_REG_I (TIMER_CONTROL_I_n_17),
.\LOAD_REG_GEN[27].LOAD_REG_I (TIMER_CONTROL_I_n_16),
.\LOAD_REG_GEN[28].LOAD_REG_I (TIMER_CONTROL_I_n_15),
.\LOAD_REG_GEN[29].LOAD_REG_I (TIMER_CONTROL_I_n_14),
.\LOAD_REG_GEN[30].LOAD_REG_I (TIMER_CONTROL_I_n_13),
.\LOAD_REG_GEN[31].LOAD_REG_I (TIMER_CONTROL_I_n_12));
zqynq_lab_1_design_axi_timer_0_1_timer_control TIMER_CONTROL_I
(.Bus_RNW_reg(Bus_RNW_reg),
.D_0(D_0),
.E(TIMER_CONTROL_I_n_24),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] (\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.\INFERRED_GEN.icount_out_reg[0] (\INFERRED_GEN.icount_out_reg[0] [87]),
.\INFERRED_GEN.icount_out_reg[0]_0 (TIMER_CONTROL_I_n_25),
.\INFERRED_GEN.icount_out_reg[1] ({\INFERRED_GEN.icount_out_reg[0] [33],\INFERRED_GEN.icount_out_reg[0] [1]}),
.\INFERRED_GEN.icount_out_reg[32] (\GEN_SECOND_TIMER.COUNTER_1_I_n_65 ),
.\INFERRED_GEN.icount_out_reg[32]_0 (COUNTER_0_I_n_64),
.\INFERRED_GEN.icount_out_reg[4] (TIMER_CONTROL_I_n_30),
.\LOAD_REG_GEN[21].LOAD_REG_I ({read_Mux_In[85],read_Mux_In[86],read_Mux_In[87],read_Mux_In[88],read_Mux_In[89],read_Mux_In[90],read_Mux_In[91],read_Mux_In[92],read_Mux_In[93],read_Mux_In[94],read_Mux_In[95]}),
.\LOAD_REG_GEN[24].LOAD_REG_I (TIMER_CONTROL_I_n_28),
.\LOAD_REG_GEN[24].LOAD_REG_I_0 (TIMER_CONTROL_I_n_29),
.PWM_FF_I(TIMER_CONTROL_I_n_26),
.Q({TIMER_CONTROL_I_n_3,TIMER_CONTROL_I_n_4}),
.R(R),
.S(TIMER_CONTROL_I_n_27),
.SR(bus2ip_reset),
.\TCSR0_GENERATE[24].TCSR0_FF_I_0 (\INFERRED_GEN.icount_out_reg[0] [86]),
.\TCSR0_GENERATE[24].TCSR0_FF_I_1 (\TCSR0_GENERATE[24].TCSR0_FF_I ),
.\TCSR1_GENERATE[23].TCSR1_FF_I_0 (\INFERRED_GEN.icount_out_reg[0] [85]),
.\TCSR1_GENERATE[24].TCSR1_FF_I_0 (\TCSR1_GENERATE[24].TCSR1_FF_I ),
.bus2ip_wrce(bus2ip_wrce),
.bus2ip_wrce__0(bus2ip_wrce__0),
.capturetrig0(capturetrig0),
.capturetrig1(capturetrig1),
.counter_TC(counter_TC),
.freeze(freeze),
.generateout0(generateout0),
.generateout1(generateout1),
.interrupt(interrupt),
.load_Counter_Reg(load_Counter_Reg),
.pair0_Select(pair0_Select),
.pwm0(pwm0),
.read_done1(read_done1),
.s_axi_aclk(s_axi_aclk),
.\s_axi_rdata_i_reg[0] (TIMER_CONTROL_I_n_12),
.\s_axi_rdata_i_reg[10] (TIMER_CONTROL_I_n_22),
.\s_axi_rdata_i_reg[1] (TIMER_CONTROL_I_n_13),
.\s_axi_rdata_i_reg[2] (TIMER_CONTROL_I_n_14),
.\s_axi_rdata_i_reg[3] (TIMER_CONTROL_I_n_15),
.\s_axi_rdata_i_reg[4] (TIMER_CONTROL_I_n_16),
.\s_axi_rdata_i_reg[5] (TIMER_CONTROL_I_n_17),
.\s_axi_rdata_i_reg[6] (TIMER_CONTROL_I_n_18),
.\s_axi_rdata_i_reg[7] (TIMER_CONTROL_I_n_19),
.\s_axi_rdata_i_reg[8] (TIMER_CONTROL_I_n_20),
.\s_axi_rdata_i_reg[9] (TIMER_CONTROL_I_n_21),
.s_axi_wdata(s_axi_wdata));
endmodule
(* ORIG_REF_NAME = "timer_control" *)
module zqynq_lab_1_design_axi_timer_0_1_timer_control
(generateout0,
generateout1,
interrupt,
Q,
\INFERRED_GEN.icount_out_reg[0] ,
\TCSR0_GENERATE[24].TCSR0_FF_I_0 ,
\TCSR1_GENERATE[23].TCSR1_FF_I_0 ,
D_0,
read_done1,
load_Counter_Reg,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[1] ,
\s_axi_rdata_i_reg[2] ,
\s_axi_rdata_i_reg[3] ,
\s_axi_rdata_i_reg[4] ,
\s_axi_rdata_i_reg[5] ,
\s_axi_rdata_i_reg[6] ,
\s_axi_rdata_i_reg[7] ,
\s_axi_rdata_i_reg[8] ,
\s_axi_rdata_i_reg[9] ,
\s_axi_rdata_i_reg[10] ,
R,
E,
\INFERRED_GEN.icount_out_reg[0]_0 ,
PWM_FF_I,
S,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\LOAD_REG_GEN[24].LOAD_REG_I_0 ,
\INFERRED_GEN.icount_out_reg[4] ,
SR,
\INFERRED_GEN.icount_out_reg[32] ,
s_axi_aclk,
\INFERRED_GEN.icount_out_reg[32]_0 ,
bus2ip_wrce,
s_axi_wdata,
\LOAD_REG_GEN[21].LOAD_REG_I ,
pair0_Select,
\TCSR0_GENERATE[24].TCSR0_FF_I_1 ,
\TCSR1_GENERATE[24].TCSR1_FF_I_0 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
counter_TC,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ,
pwm0,
\INFERRED_GEN.icount_out_reg[1] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
bus2ip_wrce__0,
freeze,
capturetrig0,
capturetrig1);
output generateout0;
output generateout1;
output interrupt;
output [1:0]Q;
output \INFERRED_GEN.icount_out_reg[0] ;
output \TCSR0_GENERATE[24].TCSR0_FF_I_0 ;
output \TCSR1_GENERATE[23].TCSR1_FF_I_0 ;
output D_0;
output read_done1;
output [0:1]load_Counter_Reg;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[1] ;
output \s_axi_rdata_i_reg[2] ;
output \s_axi_rdata_i_reg[3] ;
output \s_axi_rdata_i_reg[4] ;
output \s_axi_rdata_i_reg[5] ;
output \s_axi_rdata_i_reg[6] ;
output \s_axi_rdata_i_reg[7] ;
output \s_axi_rdata_i_reg[8] ;
output \s_axi_rdata_i_reg[9] ;
output \s_axi_rdata_i_reg[10] ;
output R;
output [0:0]E;
output [0:0]\INFERRED_GEN.icount_out_reg[0]_0 ;
output PWM_FF_I;
output [0:0]S;
output \LOAD_REG_GEN[24].LOAD_REG_I ;
output \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
output [0:0]\INFERRED_GEN.icount_out_reg[4] ;
input [0:0]SR;
input \INFERRED_GEN.icount_out_reg[32] ;
input s_axi_aclk;
input \INFERRED_GEN.icount_out_reg[32]_0 ;
input [1:0]bus2ip_wrce;
input [9:0]s_axi_wdata;
input [10:0]\LOAD_REG_GEN[21].LOAD_REG_I ;
input pair0_Select;
input \TCSR0_GENERATE[24].TCSR0_FF_I_1 ;
input \TCSR1_GENERATE[24].TCSR1_FF_I_0 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input [0:1]counter_TC;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
input pwm0;
input [1:0]\INFERRED_GEN.icount_out_reg[1] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input [0:0]bus2ip_wrce__0;
input freeze;
input capturetrig0;
input capturetrig1;
wire Bus_RNW_reg;
wire D_0;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
wire GenerateOut00;
wire GenerateOut10;
wire \INFERRED_GEN.icount_out_reg[0] ;
wire [0:0]\INFERRED_GEN.icount_out_reg[0]_0 ;
wire [1:0]\INFERRED_GEN.icount_out_reg[1] ;
wire \INFERRED_GEN.icount_out_reg[32] ;
wire \INFERRED_GEN.icount_out_reg[32]_0 ;
wire [0:0]\INFERRED_GEN.icount_out_reg[4] ;
wire Interrupt0;
wire \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0 ;
wire \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0 ;
wire [10:0]\LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
wire Load_Counter_Reg028_out;
wire Load_Counter_Reg030_out;
wire Load_Counter_Reg031_out;
wire Load_Counter_Reg0__0;
wire PWM_FF_I;
wire [1:0]Q;
wire R;
wire READ_DONE0_I_i_3_n_0;
wire READ_DONE1_I_i_1_n_0;
wire READ_DONE1_I_i_3_n_0;
wire R_0;
wire [0:0]S;
wire [0:0]SR;
wire \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0 ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I_0 ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I_1 ;
wire TCSR0_Set2__0;
wire \TCSR1_GENERATE[23].TCSR1_FF_I_0 ;
wire \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0 ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I_0 ;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire captureTrig0_d;
wire captureTrig0_d0;
wire captureTrig0_d2;
wire captureTrig0_pulse_d1;
wire captureTrig0_pulse_d1_i_1_n_0;
wire captureTrig0_pulse_d2;
wire captureTrig1_d;
wire captureTrig1_d0;
wire captureTrig1_d2;
wire capturetrig0;
wire capturetrig1;
wire [0:1]counter_TC;
wire counter_TC_Reg2;
wire freeze;
wire generateOutPre0;
wire generateOutPre1;
wire generateout0;
wire generateout1;
wire interrupt;
wire [0:1]load_Counter_Reg;
wire p_33_in;
wire p_38_in;
wire pair0_Select;
wire pwm0;
wire [21:63]read_Mux_In;
wire read_done1;
wire s_axi_aclk;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[1] ;
wire \s_axi_rdata_i_reg[2] ;
wire \s_axi_rdata_i_reg[3] ;
wire \s_axi_rdata_i_reg[4] ;
wire \s_axi_rdata_i_reg[5] ;
wire \s_axi_rdata_i_reg[6] ;
wire \s_axi_rdata_i_reg[7] ;
wire \s_axi_rdata_i_reg[8] ;
wire \s_axi_rdata_i_reg[9] ;
wire [9:0]s_axi_wdata;
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [10]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[21]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[53]),
.O(\s_axi_rdata_i_reg[10] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [9]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[22]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[54]),
.O(\s_axi_rdata_i_reg[9] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [8]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[23]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[55]),
.O(\s_axi_rdata_i_reg[8] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [7]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(\TCSR0_GENERATE[24].TCSR0_FF_I_0 ),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(\TCSR1_GENERATE[23].TCSR1_FF_I_0 ),
.O(\s_axi_rdata_i_reg[7] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [6]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[25]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[57]),
.O(\s_axi_rdata_i_reg[6] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [5]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[26]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[58]),
.O(\s_axi_rdata_i_reg[5] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [4]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[27]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[59]),
.O(\s_axi_rdata_i_reg[4] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [3]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[28]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[60]),
.O(\s_axi_rdata_i_reg[3] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [2]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[29]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[61]),
.O(\s_axi_rdata_i_reg[2] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [1]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[30]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[62]),
.O(\s_axi_rdata_i_reg[1] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [0]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[31]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[63]),
.O(\s_axi_rdata_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'hB800))
GenerateOut0_i_2
(.I0(generateOutPre1),
.I1(\INFERRED_GEN.icount_out_reg[0] ),
.I2(generateOutPre0),
.I3(read_Mux_In[29]),
.O(GenerateOut00));
FDRE GenerateOut0_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GenerateOut00),
.Q(generateout0),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'h8F808080))
GenerateOut1_i_1
(.I0(generateOutPre0),
.I1(read_Mux_In[29]),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(read_Mux_In[61]),
.I4(generateOutPre1),
.O(GenerateOut10));
FDRE GenerateOut1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GenerateOut10),
.Q(generateout1),
.R(SR));
LUT5 #(
.INIT(32'hAAFEAAAA))
\INFERRED_GEN.icount_out[31]_i_3
(.I0(read_Mux_In[26]),
.I1(read_Mux_In[22]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[31]),
.I4(counter_TC[0]),
.O(Load_Counter_Reg030_out));
LUT6 #(
.INIT(64'hFFFFAAEAAAAAAAEA))
\INFERRED_GEN.icount_out[31]_i_3__0
(.I0(read_Mux_In[58]),
.I1(counter_TC[1]),
.I2(read_Mux_In[59]),
.I3(read_Mux_In[63]),
.I4(read_Mux_In[54]),
.I5(counter_TC[0]),
.O(Load_Counter_Reg0__0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'hFF40))
\INFERRED_GEN.icount_out[31]_i_4
(.I0(read_Mux_In[31]),
.I1(counter_TC[1]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[58]),
.O(Load_Counter_Reg028_out));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'hFF40))
\INFERRED_GEN.icount_out[31]_i_4__0
(.I0(read_Mux_In[31]),
.I1(counter_TC[1]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[26]),
.O(Load_Counter_Reg031_out));
LUT6 #(
.INIT(64'hFF40FFFFFF400000))
\INFERRED_GEN.icount_out[31]_i_7
(.I0(read_Mux_In[31]),
.I1(counter_TC[1]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[58]),
.I4(\INFERRED_GEN.icount_out_reg[0] ),
.I5(Load_Counter_Reg0__0),
.O(load_Counter_Reg[1]));
LUT6 #(
.INIT(64'hFF40FFFFFF400000))
\INFERRED_GEN.icount_out[31]_i_7__0
(.I0(read_Mux_In[31]),
.I1(counter_TC[1]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[26]),
.I4(\INFERRED_GEN.icount_out_reg[0] ),
.I5(Load_Counter_Reg030_out),
.O(load_Counter_Reg[0]));
zqynq_lab_1_design_axi_timer_0_1_cdc_sync INPUT_DOUBLE_REGS
(.captureTrig0_d0(captureTrig0_d0),
.capturetrig0(capturetrig0),
.read_Mux_In(read_Mux_In[28]),
.s_axi_aclk(s_axi_aclk));
zqynq_lab_1_design_axi_timer_0_1_cdc_sync_1 INPUT_DOUBLE_REGS2
(.captureTrig1_d0(captureTrig1_d0),
.capturetrig1(capturetrig1),
.read_Mux_In(read_Mux_In[60]),
.s_axi_aclk(s_axi_aclk));
zqynq_lab_1_design_axi_timer_0_1_cdc_sync_2 INPUT_DOUBLE_REGS3
(.E(E),
.\INFERRED_GEN.icount_out_reg[0] (\INFERRED_GEN.icount_out_reg[0]_0 ),
.\INFERRED_GEN.icount_out_reg[1] (\INFERRED_GEN.icount_out_reg[1] ),
.\INFERRED_GEN.icount_out_reg[4] (\INFERRED_GEN.icount_out_reg[4] ),
.Load_Counter_Reg028_out(Load_Counter_Reg028_out),
.Load_Counter_Reg030_out(Load_Counter_Reg030_out),
.Load_Counter_Reg031_out(Load_Counter_Reg031_out),
.Load_Counter_Reg0__0(Load_Counter_Reg0__0),
.S(S),
.\TCSR0_GENERATE[20].TCSR0_FF_I (\INFERRED_GEN.icount_out_reg[0] ),
.\TCSR0_GENERATE[24].TCSR0_FF_I (\TCSR0_GENERATE[24].TCSR0_FF_I_0 ),
.\TCSR1_GENERATE[24].TCSR1_FF_I (\TCSR1_GENERATE[23].TCSR1_FF_I_0 ),
.counter_TC(counter_TC),
.freeze(freeze),
.generateOutPre0(generateOutPre0),
.read_Mux_In({read_Mux_In[22],read_Mux_In[27],read_Mux_In[30],read_Mux_In[31],read_Mux_In[54],read_Mux_In[59],read_Mux_In[62],read_Mux_In[63]}),
.s_axi_aclk(s_axi_aclk));
LUT4 #(
.INIT(16'hF888))
Interrupt_i_1
(.I0(read_Mux_In[25]),
.I1(read_Mux_In[23]),
.I2(read_Mux_In[57]),
.I3(read_Mux_In[55]),
.O(Interrupt0));
FDRE Interrupt_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Interrupt0),
.Q(interrupt),
.R(SR));
LUT6 #(
.INIT(64'hE000FFFFE000E000))
\LOAD_REG_GEN[0].LOAD_REG_I_i_1
(.I0(read_Mux_In[27]),
.I1(D_0),
.I2(R_0),
.I3(read_Mux_In[31]),
.I4(Bus_RNW_reg),
.I5(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.O(\LOAD_REG_GEN[24].LOAD_REG_I ));
LUT6 #(
.INIT(64'hFFFFFFFFF8080808))
\LOAD_REG_GEN[0].LOAD_REG_I_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0 ),
.I1(p_38_in),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(\LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0 ),
.I4(p_33_in),
.I5(bus2ip_wrce__0),
.O(\LOAD_REG_GEN[24].LOAD_REG_I_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT2 #(
.INIT(4'hE))
\LOAD_REG_GEN[0].LOAD_REG_I_i_3
(.I0(read_Mux_In[59]),
.I1(read_done1),
.O(\LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0 ));
LUT6 #(
.INIT(64'hF4F4F40400000000))
\LOAD_REG_GEN[0].LOAD_REG_I_i_4
(.I0(captureTrig1_d2),
.I1(captureTrig1_d),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(READ_DONE1_I_i_3_n_0),
.I4(READ_DONE0_I_i_3_n_0),
.I5(read_Mux_In[63]),
.O(p_38_in));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT2 #(
.INIT(4'hE))
\LOAD_REG_GEN[0].LOAD_REG_I_i_5
(.I0(read_Mux_In[27]),
.I1(read_done1),
.O(\LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0 ));
LUT6 #(
.INIT(64'hF4F4F40400000000))
\LOAD_REG_GEN[0].LOAD_REG_I_i_6
(.I0(captureTrig1_d2),
.I1(captureTrig1_d),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(READ_DONE1_I_i_3_n_0),
.I4(READ_DONE0_I_i_3_n_0),
.I5(read_Mux_In[31]),
.O(p_33_in));
LUT3 #(
.INIT(8'hAB))
PWM_FF_I_i_1
(.I0(generateout1),
.I1(read_Mux_In[22]),
.I2(read_Mux_In[54]),
.O(R));
LUT2 #(
.INIT(4'hE))
PWM_FF_I_i_2
(.I0(generateout0),
.I1(pwm0),
.O(PWM_FF_I));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
READ_DONE0_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.Q(D_0),
.R(R_0));
LUT6 #(
.INIT(64'hAA00AA00ABFFAA00))
READ_DONE0_I_i_1
(.I0(READ_DONE0_I_i_3_n_0),
.I1(Q[1]),
.I2(counter_TC[0]),
.I3(\INFERRED_GEN.icount_out_reg[0] ),
.I4(captureTrig0_d),
.I5(captureTrig0_d2),
.O(R_0));
LUT3 #(
.INIT(8'hA8))
READ_DONE0_I_i_3
(.I0(counter_TC_Reg2),
.I1(captureTrig0_pulse_d2),
.I2(captureTrig0_pulse_d1),
.O(READ_DONE0_I_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
READ_DONE1_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.Q(read_done1),
.R(READ_DONE1_I_i_1_n_0));
LUT5 #(
.INIT(32'hE0E0EFE0))
READ_DONE1_I_i_1
(.I0(READ_DONE0_I_i_3_n_0),
.I1(READ_DONE1_I_i_3_n_0),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(captureTrig1_d),
.I4(captureTrig1_d2),
.O(READ_DONE1_I_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT4 #(
.INIT(16'h0004))
READ_DONE1_I_i_3
(.I0(captureTrig0_d2),
.I1(captureTrig0_d),
.I2(counter_TC[0]),
.I3(Q[1]),
.O(READ_DONE1_I_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[20].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[9]),
.Q(\INFERRED_GEN.icount_out_reg[0] ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[21].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(pair0_Select),
.D(s_axi_wdata[8]),
.Q(read_Mux_In[21]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[22].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[7]),
.Q(read_Mux_In[22]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[23].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(\TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0 ),
.Q(read_Mux_In[23]),
.R(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFFFF3F2F0F2))
\TCSR0_GENERATE[23].TCSR0_FF_I_i_2
(.I0(generateOutPre0),
.I1(read_Mux_In[31]),
.I2(TCSR0_Set2__0),
.I3(\INFERRED_GEN.icount_out_reg[0] ),
.I4(generateOutPre1),
.I5(read_Mux_In[23]),
.O(\TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0 ));
LUT6 #(
.INIT(64'hA8AAA80000000000))
\TCSR0_GENERATE[23].TCSR0_FF_I_i_3
(.I0(read_Mux_In[31]),
.I1(READ_DONE0_I_i_3_n_0),
.I2(READ_DONE1_I_i_3_n_0),
.I3(\INFERRED_GEN.icount_out_reg[0] ),
.I4(captureTrig0_pulse_d1_i_1_n_0),
.I5(\TCSR0_GENERATE[24].TCSR0_FF_I_0 ),
.O(TCSR0_Set2__0));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[24].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(pair0_Select),
.D(\TCSR0_GENERATE[24].TCSR0_FF_I_1 ),
.Q(\TCSR0_GENERATE[24].TCSR0_FF_I_0 ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[25].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[6]),
.Q(read_Mux_In[25]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[26].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[5]),
.Q(read_Mux_In[26]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[27].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[4]),
.Q(read_Mux_In[27]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[28].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[3]),
.Q(read_Mux_In[28]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[29].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[2]),
.Q(read_Mux_In[29]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[30].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[1]),
.Q(read_Mux_In[30]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[31].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[0]),
.Q(read_Mux_In[31]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[21].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(pair0_Select),
.D(s_axi_wdata[8]),
.Q(read_Mux_In[53]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[22].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[7]),
.Q(read_Mux_In[54]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[23].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(\TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0 ),
.Q(read_Mux_In[55]),
.R(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ));
LUT6 #(
.INIT(64'hFFFFFFFF00008F80))
\TCSR1_GENERATE[23].TCSR1_FF_I_i_2
(.I0(\TCSR1_GENERATE[23].TCSR1_FF_I_0 ),
.I1(READ_DONE1_I_i_1_n_0),
.I2(read_Mux_In[63]),
.I3(generateOutPre1),
.I4(\INFERRED_GEN.icount_out_reg[0] ),
.I5(read_Mux_In[55]),
.O(\TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[24].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(pair0_Select),
.D(\TCSR1_GENERATE[24].TCSR1_FF_I_0 ),
.Q(\TCSR1_GENERATE[23].TCSR1_FF_I_0 ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[25].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[6]),
.Q(read_Mux_In[57]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[26].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[5]),
.Q(read_Mux_In[58]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[27].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[4]),
.Q(read_Mux_In[59]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[28].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[3]),
.Q(read_Mux_In[60]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[29].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[2]),
.Q(read_Mux_In[61]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[30].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[1]),
.Q(read_Mux_In[62]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[31].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[0]),
.Q(read_Mux_In[63]),
.R(SR));
FDRE captureTrig0_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig0_d),
.Q(captureTrig0_d2),
.R(SR));
FDRE captureTrig0_d_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig0_d0),
.Q(captureTrig0_d),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT2 #(
.INIT(4'h2))
captureTrig0_pulse_d1_i_1
(.I0(captureTrig0_d),
.I1(captureTrig0_d2),
.O(captureTrig0_pulse_d1_i_1_n_0));
FDRE captureTrig0_pulse_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig0_pulse_d1_i_1_n_0),
.Q(captureTrig0_pulse_d1),
.R(SR));
FDRE captureTrig0_pulse_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig0_pulse_d1),
.Q(captureTrig0_pulse_d2),
.R(SR));
FDRE captureTrig1_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig1_d),
.Q(captureTrig1_d2),
.R(SR));
FDRE captureTrig1_d_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig1_d0),
.Q(captureTrig1_d),
.R(SR));
FDRE counter_TC_Reg2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Q[1]),
.Q(counter_TC_Reg2),
.R(SR));
FDRE \counter_TC_Reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(counter_TC[0]),
.Q(Q[1]),
.R(SR));
FDRE \counter_TC_Reg_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(counter_TC[1]),
.Q(Q[0]),
.R(SR));
FDRE generateOutPre0_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INFERRED_GEN.icount_out_reg[32]_0 ),
.Q(generateOutPre0),
.R(SR));
FDRE generateOutPre1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INFERRED_GEN.icount_out_reg[32] ),
.Q(generateOutPre1),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V11.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 256
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 13
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 256
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 2500
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 100000
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR11.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 13;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 13;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 8;
parameter gLOCAL_DATA_BITS = 256;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 256;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 2500;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 100000;
parameter REF_CLOCK_TICK_IN_PS = 40000;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 125;
parameter gMEM_IF_TRCD_NS = 13.5;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.5;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
/*
* èäåîïðîöåññîð 640x480 VGA
*/
module video(
input wire clock,
input wire [7:0] d8_chr,
output reg [13:0] addr,
output reg [4:0] r,
output reg [5:0] g,
output reg [4:0] b,
output reg hs,
output reg vs
);
// ---------------------------------------------------------------------------
// äðî http://tinyvga.com/vga-timing/640x480@60Hz
// ---------------------------------------------------------------------------
reg [9:0] x;
reg [9:0] y;
reg [7:0] attr;
reg [7:0] bit8;
reg [7:0] mask;
// ç-çà "îáòåêàíèÿ" ïðèõîäèòñß ââîäèòü ñêðîëëèíã íà 8 ïèêñåëåé
wire [9:0] rx = x - 8'd48;
wire [9:0] ry = y - 8'd48;
wire bitset = mask[ 3'h7 ^ rx[3:1] ];
// Âû÷èñëåíèå òàéìèíãà 800 x 525 íà ïîëíûé ôðåéì VGA
always @(posedge clock) begin
// òñ÷åò êàäðîâ
if (x == 10'd800) begin
x <= 1'b0;
y <= (y == 10'd525) ? 1'b0 : (y + 1'b1);
end else x <= x + 1'b1;
// èãíàëû ñèíõðîíèçàöèè
hs <= (x >= 10'd656 && x <= 10'd751); // [ w=640 ] [front=16] [sync=96] [back=48]
vs <= (y >= 10'd490 && y <= 10'd492); // [ h=480 ] [front=10] [sync=2] [back=33]
// èäèìàÿ îáëàñòü
// ------------------------------------------------
if (x < 10'd640 && y < 10'd480) begin
if (x >= 64 && x < 576 && y >= 48 && y < 432) begin
r <= bitset? 1'b0 : 5'h0F; // ×åðíî-áåëîå ïîêà ÷òî
g <= bitset? 1'b0 : 6'h1F;
b <= bitset? 1'b0 : 5'h0F;
// Öâåò áîðäþðà
end else begin r <= 5'h0F; g <= 6'h1F; b <= 5'h0F; end
// ñòàâèòü ïóñòîå ïðîñòðàíñòâî äëÿ èíèöèàëèçàöèè
end else begin r <= 1'b0; g <= 1'b0; b <= 1'b0; end
// ------------------------------------------------
case (rx[3:0])
// êàçàòåëü íà ñèìâîë: 10y yyyy | yyyx xxxx
4'h0: begin addr <= {2'b10, ry[8:1], rx[8:4]}; end
// êàçàòåëü íà öâåò 101 10yy | yyyx xxxx
4'h1: begin addr <= {5'b10110, ry[8:4], rx[8:4]}; bit8 <= d8_chr; end
// íà÷åíèå öâåòà è ïîëó÷åíèå áèòîâîé ìàñêè
4'hF: begin attr <= d8_chr; mask <= bit8; end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_BLACKBOX_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1n (
X ,
A ,
SLEEP_B
);
output X ;
input A ;
input SLEEP_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_BLACKBOX_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_led_pio (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 9: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] data_out;
wire [ 9: 0] out_port;
wire [ 9: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 15;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[9 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
* instruction_rom.v
* Asynchronous ROM module used for instruction storage
*
* Copyright (C) 2013 James Cowgill
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module instruction_rom(data_out, address);
// Width of instructions stored in the ROM
parameter DATA_WIDTH = 4;
// Width of addresses
parameter ADDR_WIDTH = 8;
// The ROM file to read from
parameter ROM_FILE = "../rom.mif";
// Inputs and outputs
output [DATA_WIDTH - 1:0] data_out; // Data currently at the given address
input [ADDR_WIDTH - 1:0] address; // Address of the byte in use
// ROM Storage
reg [DATA_WIDTH - 1:0] data[0:(1 << ADDR_WIDTH) - 1];
// Output assignment
assign data_out = data[address];
// ROM data loading
initial
begin
$readmemh(ROM_FILE, data);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_1_V
`define SKY130_FD_SC_HDLL__INV_1_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inv_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_1_V
|
module ALUControl(ALUOp, Funct, ALUCtl, Sign);
input [3:0] ALUOp;
input [5:0] Funct;
output reg [4:0] ALUCtl;
output Sign;
parameter aluAND = 5'b00000;
parameter aluOR = 5'b00001;
parameter aluADD = 5'b00010;
parameter aluSUB = 5'b00110;
parameter aluSLT = 5'b00111;
parameter aluNOR = 5'b01100;
parameter aluXOR = 5'b01101;
parameter aluSLL = 5'b10000;
parameter aluSRL = 5'b11000;
parameter aluSRA = 5'b11001;
assign Sign = (ALUOp[2:0] == 3'b010)? ~Funct[0]: ~ALUOp[3];
reg [4:0] aluFunct;
always @(*)
case (Funct)
6'b00_0000: aluFunct <= aluSLL;
6'b00_0010: aluFunct <= aluSRL;
6'b00_0011: aluFunct <= aluSRA;
6'b10_0000: aluFunct <= aluADD;
6'b10_0001: aluFunct <= aluADD;
6'b10_0010: aluFunct <= aluSUB;
6'b10_0011: aluFunct <= aluSUB;
6'b10_0100: aluFunct <= aluAND;
6'b10_0101: aluFunct <= aluOR;
6'b10_0110: aluFunct <= aluXOR;
6'b10_0111: aluFunct <= aluNOR;
6'b10_1010: aluFunct <= aluSLT;
6'b10_1011: aluFunct <= aluSLT;
default: aluFunct <= aluADD;
endcase
always @(*)
case (ALUOp[2:0])
3'b000: ALUCtl <= aluADD;
3'b001: ALUCtl <= aluSUB;
3'b100: ALUCtl <= aluAND;
3'b101: ALUCtl <= aluSLT;
3'b010: ALUCtl <= aluFunct;
default: ALUCtl <= aluADD;
endcase
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// UART ser/des framer for use in SPDR module. Hard coded for 115200,1,1.
//
module spdr_uart_framer
(
input clk_50,
input rst,
output reg tx_busy,
input tx_vld,
input [7:0] tx_data,
output rx_vld,
output [7:0] rx_data,
output reg rx_frame_error,
output uart_tx,
input uart_rx
);
parameter SAMPLE_CLK_DIV = 6'd62; // Value for 115200 @ 50 MHz in
//
// 50 MHz -> sample clock (7 * bit)
//
reg [5:0] sample_cnt;
reg sample_en;
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
sample_cnt <= 6'd0;
sample_en <= 1'b0;
end
else if (sample_cnt == SAMPLE_CLK_DIV)
begin
sample_cnt <= 6'd0;
sample_en <= 1'b1;
end
else
begin
sample_cnt <= sample_cnt + 6'd1;
sample_en <= 1'b0;
end
//
// Rx data sample state machine
//
reg [6:0] rx_sample;
reg [2:0] rx_bitclk_cnt;
reg rx_bitclk_en;
reg [3:0] rx_bit_cnt;
reg rx_busy;
wire rx_falling_clean = (rx_sample[6:0] == 7'b1110000);
wire rx_falling_dirty = (rx_sample[6:4] == 3'b110) && (rx_sample[1:0] == 2'b00);
wire rx_falling = rx_falling_clean || rx_falling_dirty;
wire rx_high = (rx_sample[2:1] == 2'b11);
wire rx_low = (rx_sample[2:1] == 2'b00);
always @ (posedge clk_50 or posedge rst)
if (rst)
rx_sample <= 7'd0;
else if (sample_en)
rx_sample <= {rx_sample[5:0], uart_rx};
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
rx_bitclk_cnt <= 3'd0;
rx_bitclk_en <= 1'b0;
rx_bit_cnt <= 4'd0;
rx_busy <= 1'b0;
end
else if (sample_en)
begin
if (!rx_busy)
begin
rx_bitclk_cnt <= 3'd0;
rx_bitclk_en <= 1'b0;
rx_bit_cnt <= 4'd0;
rx_busy <= (rx_falling) ? 1'b1 : 1'b0;
end
else
begin
rx_busy <= (rx_bit_cnt == 4'd9) ? 1'b0 : 1'b1;
rx_bitclk_en <= (rx_bitclk_cnt == 3'd5) ? 1'b1 : 1'b0;
if (rx_bitclk_cnt == 3'd6)
begin
rx_bitclk_cnt <= 3'd0;
rx_bit_cnt <= rx_bit_cnt + 4'd1;
end
else
begin
rx_bitclk_cnt <= rx_bitclk_cnt + 3'd1;
end
end
end
//
// Rx bit capture and signalling
//
reg [8:0] rx_capture;
reg [8:0] rx_signal_errors;
reg rx_data_done;
reg rx_busy_d1;
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
rx_capture <= 9'd0;
rx_signal_errors <= 9'd0;
end
else if (sample_en && rx_bitclk_en)
begin
rx_capture <= {rx_high && !rx_low, rx_capture[8:1]};
rx_signal_errors <= {!rx_high && !rx_low, rx_signal_errors[8:1]};
end
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
rx_data_done <= 1'b0;
rx_busy_d1 <= 1'b0;
end
else
begin
rx_data_done <= rx_busy_d1 && !rx_busy;
rx_busy_d1 <= rx_busy;
end
assign rx_vld = rx_data_done;
assign rx_data = rx_capture[7:0];
always @ (posedge clk_50)
rx_frame_error <= (rx_signal_errors != 9'd0) || !rx_capture[8];
//
// Tx state machine
//
reg [8:0] tx_shift;
reg [2:0] tx_bitclk_cnt;
reg [3:0] tx_cnt;
assign uart_tx = tx_shift[0];
always @ (posedge clk_50 or posedge rst)
if (rst)
begin
tx_shift <= {9{1'b1}};
tx_bitclk_cnt <= 3'd0;
tx_cnt <= 4'd0;
tx_busy <= 1'b0;
end
else if (!tx_busy && tx_vld)
begin
tx_shift <= {tx_data, 1'b0};
tx_bitclk_cnt <= 3'd0;
tx_cnt <= 4'd0;
tx_busy <= 1'b1;
end
else if (sample_en)
begin
tx_busy <= (tx_cnt == 4'd12) ? 1'b0 : 1'b1;
if (tx_bitclk_cnt == 3'd6)
begin
tx_bitclk_cnt <= 3'd0;
tx_shift <= {1'b1, tx_shift[8:1]};
tx_cnt <= tx_cnt + 4'd1;
end
else
begin
tx_bitclk_cnt <= tx_bitclk_cnt + 3'd1;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 11:33:15 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n286, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414,
n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436,
n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491,
n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513,
n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, Sgf_operation_n109,
Sgf_operation_n108, Sgf_operation_n107, Sgf_operation_n106,
Sgf_operation_n105, Sgf_operation_n104, Sgf_operation_n103,
Sgf_operation_n102, Sgf_operation_n101, Sgf_operation_n100,
Sgf_operation_n99, Sgf_operation_n98, Sgf_operation_n97,
Sgf_operation_n96, Sgf_operation_n95, Sgf_operation_n94,
Sgf_operation_n93, Sgf_operation_n92, Sgf_operation_n91,
Sgf_operation_n90, Sgf_operation_n89, Sgf_operation_n88,
Sgf_operation_n87, Sgf_operation_n86, Sgf_operation_n85,
Sgf_operation_n84, Sgf_operation_n83, Sgf_operation_n82,
Sgf_operation_n81, Sgf_operation_n80, Sgf_operation_n79,
Sgf_operation_n78, Sgf_operation_n77, Sgf_operation_n76,
Sgf_operation_n75, Sgf_operation_n74, Sgf_operation_n73,
Sgf_operation_n72, Sgf_operation_n71, Sgf_operation_n70,
Sgf_operation_n69, Sgf_operation_n68, Sgf_operation_n67,
Sgf_operation_n66, Sgf_operation_n65, Sgf_operation_n64,
Sgf_operation_n63, Sgf_operation_n62, Sgf_operation_n61,
Sgf_operation_n60, Sgf_operation_n59, Sgf_operation_n58,
Sgf_operation_n57, Sgf_operation_n56, Sgf_operation_n55,
Sgf_operation_n54, Sgf_operation_n53, Sgf_operation_n52,
Sgf_operation_n51, Sgf_operation_n50, Sgf_operation_n49,
Sgf_operation_n48, Sgf_operation_n47, Sgf_operation_n46,
Sgf_operation_n45, Sgf_operation_n44, Sgf_operation_n43,
Sgf_operation_n42, Sgf_operation_n41, Sgf_operation_n40,
Sgf_operation_n39, Sgf_operation_n38, Sgf_operation_n37,
Sgf_operation_n36, Sgf_operation_n35, Sgf_operation_n34,
Sgf_operation_n33, Sgf_operation_n32, Sgf_operation_n31,
Sgf_operation_n30, Sgf_operation_n29, Sgf_operation_n28,
Sgf_operation_n27, Sgf_operation_n26, Sgf_operation_n25,
Sgf_operation_n24, Sgf_operation_n23, Sgf_operation_n22,
Sgf_operation_n21, Sgf_operation_n20, Sgf_operation_n19,
Sgf_operation_n18, Sgf_operation_n17, Sgf_operation_n16,
Sgf_operation_n15, Sgf_operation_n14, Sgf_operation_n13,
Sgf_operation_n12, Sgf_operation_n11, Sgf_operation_n10,
Sgf_operation_n9, Sgf_operation_n8, Sgf_operation_n7,
Sgf_operation_n6, Sgf_operation_n5, Sgf_operation_n4,
DP_OP_31J26_122_605_n28, DP_OP_31J26_122_605_n27,
DP_OP_31J26_122_605_n26, DP_OP_31J26_122_605_n25,
DP_OP_31J26_122_605_n24, DP_OP_31J26_122_605_n23,
DP_OP_31J26_122_605_n22, DP_OP_31J26_122_605_n21,
DP_OP_31J26_122_605_n20, DP_OP_31J26_122_605_n19,
DP_OP_31J26_122_605_n18, DP_OP_31J26_122_605_n12,
DP_OP_31J26_122_605_n11, DP_OP_31J26_122_605_n10,
DP_OP_31J26_122_605_n9, DP_OP_31J26_122_605_n8,
DP_OP_31J26_122_605_n7, DP_OP_31J26_122_605_n6,
DP_OP_31J26_122_605_n5, DP_OP_31J26_122_605_n4,
DP_OP_31J26_122_605_n3, DP_OP_31J26_122_605_n2,
DP_OP_31J26_122_605_n1, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683,
n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694,
n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705,
n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716,
n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738,
n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749,
n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760,
n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771,
n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782,
n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793,
n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804,
n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815,
n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826,
n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837,
n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848,
n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859,
n860, n861, n862, n863, n864, n865, n866, n867, n868, n870, n871,
n872, n873, n874, n875, n876, n877, n878, n879, n880, n881, n882,
n883, n884, n885, n886, n887, n888, n889, n890, n891, n892, n893,
n894, n895, n896, n897, n898, n899, n900, n901, n902, n903, n904,
n905, n906, n907, n908, n909, n910, n911, n912, n913, n914, n915,
n916, n917, n918, n919, n920, n921, n922, n923, n924, n925, n926,
n927, n928, n929, n930, n931, n932, n933, n934, n935, n936, n937,
n938, n939, n940, n941, n942, n943, n944, n945, n946, n947, n948,
n949, n950, n951, n952, n953, n954, n955, n956, n957, n958, n959,
n960, n961, n962, n963, n964, n965, n966, n967, n968, n969, n970,
n971, n972, n973, n974, n975, n976, n977, n978, n979, n980, n981,
n982, n983, n984, n985, n986, n987, n988, n989, n990, n991, n992,
n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003,
n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013,
n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023,
n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033,
n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043,
n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053,
n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063,
n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073,
n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083,
n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093,
n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103,
n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113,
n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123,
n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133,
n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143,
n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153,
n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163,
n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173,
n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183,
n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193,
n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203,
n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213,
n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223,
n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233,
n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243,
n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253,
n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263,
n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273,
n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283,
n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293,
n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303,
n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313,
n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323,
n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353,
n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363,
n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373,
n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383,
n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393,
n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403,
n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413,
n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503,
n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513,
n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523,
n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533,
n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543,
n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593,
n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603,
n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613,
n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623,
n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633,
n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643,
n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653,
n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663,
n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673,
n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683,
n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693,
n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703,
n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713,
n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723,
n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733,
n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743,
n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753,
n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763,
n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773,
n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783,
n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793,
n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803,
n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813,
n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823,
n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833,
n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843,
n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913,
n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923,
n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933,
n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943,
n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953,
n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963,
n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983,
n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993,
n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003,
n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013,
n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023,
n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093,
n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103,
n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113,
n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123,
n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133,
n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143,
n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153,
n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163,
n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173,
n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183,
n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193,
n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203,
n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213,
n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223,
n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233,
n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243,
n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253,
n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263,
n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273,
n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283,
n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293,
n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303,
n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313,
n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323,
n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333,
n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343,
n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353,
n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873,
n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883,
n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893,
n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903,
n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913,
n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923,
n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933,
n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943,
n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043,
n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053,
n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253,
n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263,
n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273,
n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283,
n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293,
n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303,
n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313,
n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323,
n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333,
n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343,
n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353,
n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363,
n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373,
n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383,
n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393,
n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403,
n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413,
n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423,
n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433,
n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443,
n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453,
n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463,
n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473,
n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483,
n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493,
n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503,
n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513,
n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523,
n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533,
n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543,
n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553,
n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563,
n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573,
n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583,
n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593,
n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603,
n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613,
n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623,
n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633,
n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643,
n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653,
n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663,
n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673,
n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683,
n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693,
n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703,
n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713,
n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723,
n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733,
n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743,
n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753,
n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763,
n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773,
n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783,
n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793,
n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803,
n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813,
n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823,
n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833,
n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843,
n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853,
n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863,
n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873,
n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883,
n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893,
n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903,
n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913,
n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034,
n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134,
n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144,
n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154,
n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164,
n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174,
n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184,
n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194,
n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204,
n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214,
n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224,
n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234,
n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244,
n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254,
n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264,
n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274,
n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284,
n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294,
n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304,
n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314,
n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324,
n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334,
n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344,
n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354,
n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364,
n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374,
n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384,
n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394,
n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404,
n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414,
n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424,
n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434,
n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444,
n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454,
n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464,
n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474,
n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484,
n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494,
n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504,
n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514,
n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524,
n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534,
n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544,
n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554,
n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564,
n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574,
n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584,
n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594,
n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604,
n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614,
n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624,
n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634,
n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644,
n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654,
n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664,
n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674,
n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684,
n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694,
n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704,
n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714,
n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724,
n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734,
n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744,
n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754,
n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764,
n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774,
n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784,
n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794,
n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804,
n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814,
n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824,
n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834,
n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844,
n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854,
n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864,
n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874,
n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884,
n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894,
n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904,
n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914,
n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924,
n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934,
n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944,
n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954,
n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964,
n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974,
n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984,
n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994,
n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004,
n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014,
n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024,
n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034,
n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044,
n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054,
n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064,
n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074,
n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084,
n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094,
n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104,
n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114,
n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124,
n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134,
n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144,
n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154,
n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164,
n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174,
n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184,
n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194,
n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204,
n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214,
n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224,
n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234,
n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244,
n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254,
n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264,
n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274,
n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284,
n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294,
n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304,
n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314,
n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324,
n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334,
n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344,
n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354,
n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364,
n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374,
n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384,
n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394,
n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404,
n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414,
n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424,
n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434,
n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444,
n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454,
n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464,
n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474,
n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484,
n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494,
n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504,
n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514,
n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524,
n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534,
n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544,
n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554,
n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564,
n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574,
n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584,
n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594,
n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604,
n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614,
n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624,
n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634,
n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644,
n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654,
n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664,
n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674,
n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684,
n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694,
n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704,
n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714,
n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724,
n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734,
n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744,
n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754,
n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764,
n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774,
n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784,
n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794,
n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804,
n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814,
n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824,
n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834,
n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844,
n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854,
n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864,
n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874,
n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884,
n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894,
n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904,
n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914,
n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924,
n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934,
n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944,
n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954,
n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964,
n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974,
n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984,
n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994,
n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004,
n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014,
n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024,
n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034,
n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044,
n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054,
n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064,
n6065, n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074,
n6075, n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084,
n6085, n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094,
n6095, n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104,
n6105, n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114,
n6115, n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124,
n6125, n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134,
n6135, n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144,
n6145, n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154,
n6155, n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164,
n6165, n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174,
n6175, n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184,
n6185, n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194,
n6195, n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204,
n6205, n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214,
n6215, n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224,
n6225, n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234,
n6235, n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244,
n6245, n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254,
n6255, n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264,
n6265, n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274,
n6275, n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284,
n6285, n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294,
n6295, n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304,
n6305, n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314,
n6315, n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324,
n6325, n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334,
n6335, n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344,
n6345, n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354,
n6355, n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364,
n6365, n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374,
n6375, n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384,
n6385, n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394,
n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404,
n6405, n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414,
n6415, n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424,
n6425, n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434,
n6435, n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444,
n6445, n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454,
n6455, n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464,
n6465, n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474,
n6475, n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484,
n6485, n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494,
n6495, n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504,
n6505, n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514,
n6515, n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524,
n6525, n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534,
n6535, n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544,
n6545, n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554,
n6555, n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564,
n6565, n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574,
n6575, n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584,
n6585, n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594,
n6595, n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604,
n6605, n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614,
n6615, n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624,
n6625, n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634,
n6635, n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644,
n6645, n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654,
n6655, n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664,
n6665, n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674,
n6675, n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684,
n6685, n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694,
n6695, n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704,
n6705, n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714,
n6715, n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724,
n6725, n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734,
n6735, n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744,
n6745, n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754,
n6755, n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764,
n6765, n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774,
n6775, n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784,
n6785, n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794,
n6795, n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804,
n6805, n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814,
n6815, n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824,
n6825, n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834,
n6835, n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844,
n6845, n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854,
n6855, n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864,
n6865, n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874,
n6875, n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884,
n6885, n6886, n6887, n6888, n6890, n6891, n6892, n6893, n6894, n6895,
n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905,
n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915,
n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925,
n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935,
n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945,
n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955,
n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965,
n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975,
n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985,
n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995,
n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005,
n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015,
n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025,
n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035,
n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045,
n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055,
n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065,
n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075,
n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085,
n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095,
n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105,
n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115,
n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125,
n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135,
n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145,
n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155,
n7156, n7157, n7158, n7160, n7161, n7162, n7163, n7164, n7165, n7166,
n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175, n7176,
n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185, n7186,
n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195, n7196,
n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205, n7206,
n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215, n7216,
n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225, n7226,
n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235, n7236,
n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245, n7246,
n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255, n7256,
n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265, n7266,
n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275, n7276,
n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285, n7286,
n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295, n7296,
n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305, n7306,
n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315, n7316,
n7317, n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325, n7326,
n7327, n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335, n7336,
n7337, n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345, n7346,
n7347, n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355, n7356,
n7357, n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365, n7366,
n7367, n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375, n7376,
n7377, n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385, n7386,
n7387, n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395, n7396,
n7397, n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405, n7406,
n7407, n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415, n7416,
n7417, n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425, n7426,
n7427, n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435, n7436,
n7437, n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445, n7446,
n7447, n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455, n7456,
n7457, n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465, n7466,
n7467, n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475, n7476,
n7477, n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485, n7486,
n7487, n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495, n7496,
n7497, n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505, n7506,
n7507, n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515, n7516,
n7517, n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525, n7526,
n7527, n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535, n7536,
n7537, n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545, n7546,
n7547, n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555, n7556,
n7557, n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565, n7566,
n7567, n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575, n7576,
n7577, n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585, n7586,
n7587, n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595, n7596,
n7597, n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605, n7606,
n7607, n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615, n7616,
n7617, n7618, n7619, n7620, n7621, n7622, n7623, n7624, n7625, n7626,
n7627, n7628, n7629, n7630, n7631, n7632, n7633, n7634, n7635, n7636,
n7637, n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646,
n7647, n7648, n7649, n7650, n7651, n7652, n7653, n7654, n7655, n7656,
n7657, n7658, n7659, n7660, n7661, n7662, n7663, n7664, n7665, n7666,
n7667, n7668, n7669, n7670, n7671, n7672, n7673, n7674, n7675, n7676,
n7677, n7678, n7679, n7680, n7681, n7682, n7683, n7684, n7685, n7686,
n7687, n7688, n7689, n7690, n7691, n7692, n7693, n7694, n7695, n7696,
n7697, n7698, n7699, n7700, n7701, n7702, n7703, n7704, n7705, n7706,
n7707, n7708, n7709, n7710, n7711, n7712, n7713, n7714, n7715, n7716,
n7717, n7718, n7719, n7720, n7721, n7722, n7723, n7724, n7725, n7726,
n7727, n7728, n7729, n7730, n7731, n7732, n7733, n7734, n7735, n7736,
n7737, n7738, n7739, n7740, n7741, n7742, n7743, n7744, n7745, n7746,
n7747, n7748, n7749, n7750, n7751, n7752, n7753, n7754, n7755, n7756,
n7757, n7758, n7759, n7760, n7761, n7762, n7763, n7764, n7765, n7766,
n7767, n7768, n7769, n7770, n7771, n7772, n7773, n7774, n7775, n7776,
n7777, n7778, n7779, n7780, n7781, n7782, n7783, n7784, n7785, n7786,
n7787, n7788, n7789, n7790, n7791, n7792, n7793, n7794, n7795, n7796,
n7797, n7798, n7799, n7800, n7801, n7802, n7803, n7804, n7805, n7806,
n7807, n7808, n7809, n7810, n7811, n7812, n7813, n7814, n7815, n7816,
n7817, n7818, n7819, n7820, n7821, n7822, n7823, n7824, n7825, n7826,
n7827, n7828, n7829, n7830, n7831, n7832, n7833, n7834, n7835, n7836,
n7837, n7838, n7839, n7840, n7841, n7842, n7843, n7844, n7845, n7846,
n7847, n7848, n7849, n7850, n7851, n7852, n7853, n7854, n7855, n7856,
n7857, n7858, n7859, n7860, n7861, n7862, n7863, n7864, n7865, n7866,
n7867, n7868, n7869, n7870, n7871, n7872, n7873, n7874, n7875, n7876,
n7877, n7878, n7879, n7880, n7881, n7882, n7883, n7884, n7885, n7886,
n7887, n7888, n7889, n7890, n7891, n7892, n7893, n7894, n7895, n7896,
n7897, n7898, n7899, n7900, n7901, n7902, n7903, n7904, n7905, n7906,
n7907, n7908, n7909, n7910, n7911, n7912, n7913, n7914, n7915, n7916,
n7917, n7918, n7919, n7920, n7921, n7922, n7923, n7924, n7925, n7926,
n7927, n7928, n7929, n7930, n7931, n7932, n7933, n7934, n7935, n7936,
n7937, n7938, n7939, n7940, n7941, n7942, n7943, n7944, n7945, n7946,
n7947, n7948, n7949, n7950, n7951, n7952, n7953, n7954, n7955, n7956,
n7957, n7958, n7959, n7960, n7961, n7962, n7963, n7964, n7965, n7966,
n7967, n7968, n7969, n7970, n7971, n7972, n7973, n7974, n7975, n7976,
n7977, n7978, n7979, n7980, n7981, n7982, n7983, n7984, n7985, n7986,
n7987, n7988, n7989, n7990, n7991, n7992, n7993, n7994, n7995, n7996,
n7997, n7998, n7999, n8000, n8001, n8002, n8003, n8004, n8005, n8006,
n8007, n8008, n8009, n8010, n8011, n8012, n8013, n8014, n8015, n8016,
n8017, n8018, n8019, n8020, n8021, n8022, n8023, n8024, n8025, n8026,
n8027, n8028, n8029, n8030, n8031, n8032, n8033, n8034, n8035, n8036,
n8037, n8038, n8039, n8040, n8041, n8042, n8043, n8044, n8045, n8046,
n8047, n8048, n8049, n8050, n8051, n8052, n8053, n8054, n8055, n8056,
n8057, n8058, n8059, n8060, n8061, n8062, n8063, n8064, n8065, n8066,
n8067, n8068, n8069, n8070, n8071, n8072, n8073, n8074, n8075, n8076,
n8077, n8078, n8079, n8080, n8081, n8082, n8083, n8084, n8085, n8086,
n8087, n8088, n8089, n8090, n8091, n8092, n8093, n8094, n8095, n8096,
n8097, n8098, n8099, n8100, n8101, n8102, n8103, n8104, n8105, n8106,
n8107, n8108, n8109, n8110, n8111, n8112, n8113, n8114, n8115, n8116,
n8117, n8118, n8119, n8120, n8121, n8122, n8123, n8124, n8125, n8126,
n8127, n8128, n8129, n8130, n8131, n8132, n8133, n8134, n8135, n8136,
n8137, n8138, n8139, n8140, n8141, n8142, n8143, n8144, n8145, n8146,
n8147, n8148, n8149, n8150, n8151, n8152, n8153, n8154, n8155, n8156,
n8157, n8158, n8159, n8160, n8161, n8162, n8163, n8164, n8165, n8166,
n8167, n8168, n8169, n8170, n8171, n8172, n8173, n8174, n8175, n8176,
n8177, n8178, n8179, n8180, n8181, n8182, n8183, n8184, n8185, n8186,
n8187, n8188, n8189, n8190, n8191, n8192, n8193, n8194, n8195, n8196,
n8197, n8198, n8199, n8200, n8201, n8202, n8203, n8204, n8205, n8206,
n8207, n8208, n8209, n8210, n8211, n8212, n8213, n8214, n8215, n8216,
n8217, n8218, n8219, n8220, n8221, n8222, n8223, n8224, n8225, n8226,
n8227, n8228, n8229, n8230, n8231, n8232, n8233, n8234, n8235, n8236,
n8237, n8238, n8239, n8240, n8241, n8242, n8243, n8244, n8245, n8246,
n8247, n8248, n8249, n8250, n8251, n8252, n8253, n8254, n8255, n8256,
n8257, n8258, n8259, n8260, n8261, n8262, n8263, n8264, n8265, n8266,
n8267, n8268, n8269, n8270, n8271, n8272, n8273, n8274, n8275, n8276,
n8277, n8278, n8279, n8280, n8281, n8282, n8283, n8284, n8285, n8286,
n8287, n8288, n8289, n8290, n8291, n8292, n8293, n8294, n8295, n8296,
n8297, n8298, n8299, n8300, n8301, n8302, n8303, n8304, n8305, n8306,
n8307, n8308, n8309, n8310, n8311, n8312, n8313, n8314, n8315, n8316,
n8317, n8318, n8319, n8320, n8321, n8322, n8323, n8324, n8325, n8326,
n8327, n8328, n8329, n8330, n8331, n8332, n8333, n8334, n8335, n8336,
n8337, n8338, n8339, n8340, n8341, n8342, n8343, n8344, n8345, n8346,
n8347, n8348, n8349, n8350, n8351, n8352, n8353, n8354, n8355, n8356,
n8357, n8358, n8359, n8360, n8361, n8362, n8363, n8364, n8365, n8366,
n8367, n8368, n8369, n8370, n8371, n8372, n8373, n8374, n8375, n8376,
n8377, n8378, n8379, n8380, n8381, n8382, n8383, n8384, n8385, n8386,
n8387, n8388, n8389, n8390, n8391, n8392, n8393, n8394, n8395, n8396,
n8397, n8398, n8399, n8400, n8401, n8402, n8403, n8404, n8405, n8406,
n8407, n8408, n8409, n8410, n8411, n8412, n8413, n8414, n8415, n8416,
n8417, n8418, n8419, n8420, n8421, n8422, n8423, n8424, n8425, n8426,
n8427, n8428, n8429, n8430, n8431, n8432, n8433, n8434, n8435, n8436,
n8437, n8438, n8439, n8440, n8441, n8442, n8443, n8444, n8445, n8446,
n8447, n8448, n8449, n8450, n8451, n8452, n8453, n8454, n8455, n8456,
n8457, n8458, n8459, n8460, n8461, n8462, n8463, n8464, n8465, n8466,
n8467, n8468, n8469, n8470, n8471, n8472, n8473, n8474, n8475, n8476,
n8477, n8478, n8479, n8480, n8481, n8482, n8483, n8484, n8485, n8486,
n8487, n8488, n8489, n8490, n8491, n8492, n8493, n8494, n8495, n8496,
n8497, n8498, n8499, n8500, n8501, n8502, n8503, n8504, n8505, n8506,
n8507, n8508, n8509, n8510, n8511, n8512, n8513, n8514, n8515, n8516,
n8517, n8518, n8519, n8520, n8521, n8522, n8523, n8524, n8525, n8526,
n8527, n8528, n8529, n8530, n8531, n8532, n8533, n8534, n8535, n8536,
n8537, n8538, n8539, n8540, n8541, n8542, n8543, n8544, n8545, n8546,
n8547, n8548, n8549, n8550, n8551, n8552, n8553, n8554, n8555, n8556,
n8557, n8558, n8559, n8560, n8561, n8562, n8563, n8564, n8565, n8566,
n8567, n8568, n8569, n8570, n8571, n8572, n8573, n8574, n8575, n8576,
n8577, n8578, n8579, n8580, n8581, n8582, n8583, n8584, n8585, n8586,
n8587, n8588, n8589, n8590, n8591, n8592, n8593, n8594, n8595, n8596,
n8597, n8598, n8599, n8600, n8601, n8602, n8603, n8604, n8605, n8606,
n8607, n8608, n8609, n8610, n8611, n8612, n8613, n8614, n8615, n8616,
n8617, n8618, n8619, n8620, n8621, n8622, n8623, n8624, n8625, n8626,
n8627, n8628, n8629, n8630, n8631, n8632, n8633, n8634, n8635, n8636,
n8637, n8638, n8639, n8640, n8641, n8642, n8643, n8644, n8645, n8646,
n8647, n8648, n8649, n8650, n8651, n8652, n8653, n8654, n8655, n8656,
n8657, n8658, n8659, n8660, n8661, n8662, n8663, n8664, n8665, n8666,
n8667, n8668, n8669, n8670, n8671, n8672, n8673, n8674, n8675, n8676,
n8677, n8678, n8679, n8680, n8681, n8682, n8683, n8684, n8685, n8686,
n8687, n8688, n8689, n8690, n8691, n8692, n8693, n8694, n8695, n8696,
n8697, n8698, n8699, n8700, n8701, n8702, n8703, n8704, n8705, n8706,
n8707, n8708, n8709, n8710, n8711, n8712, n8713, n8714, n8715, n8716,
n8717, n8718, n8719, n8720, n8721, n8722, n8723, n8724, n8725, n8726,
n8727, n8728, n8729, n8730, n8731, n8732, n8733, n8734, n8735, n8736,
n8737, n8738, n8739, n8740, n8741, n8742, n8743, n8744, n8745, n8746,
n8747, n8748, n8749, n8750, n8751, n8752, n8753, n8754, n8755, n8756,
n8757, n8758, n8759, n8760, n8761, n8762, n8763, n8764, n8765, n8766,
n8767, n8768, n8769, n8770, n8771, n8772, n8773, n8774, n8775, n8776,
n8777, n8778, n8779, n8780, n8781, n8782, n8783, n8784, n8785, n8786,
n8787, n8788, n8789, n8790, n8791, n8792, n8793, n8794, n8795, n8796,
n8797, n8799, n8800, n8801, n8802, n8803, n8804, n8805, n8806, n8807,
n8808, n8809, n8810, n8811, n8812, n8813, n8814, n8815, n8816, n8817,
n8818, n8819, n8820, n8821, n8822, n8823, n8824, n8825, n8826, n8827,
n8828, n8829, n8830, n8831, n8832, n8833, n8834, n8835, n8836, n8837,
n8838, n8839, n8840, n8841, n8842, n8847, n8848, n8849, n8850, n8851,
n8852, n8853, n8854, n8855, n8856, n8857, n8858, n8859, n8860, n8861,
n8862, n8863, n8864, n8865, n8866, n8867, n8868, n8869, n8870, n8871,
n8872, n8873, n8874, n8875, n8876, n8877, n8878, n8879, n8880, n8881,
n8882, n8883, n8884, n8885, n8886, n8887, n8888, n8889, n8890, n8891,
n8892, n8893, n8894, n8895, n8896, n8897, n8898, n8899, n8900, n8901,
n8902, n8903, n8904, n8905, n8906, n8907, n8908, n8909, n8910, n8911,
n8912, n8913, n8914, n8915, n8916, n8917, n8918, n8919, n8920, n8921,
n8922, n8923, n8924, n8925, n8926, n8927, n8928, n8929, n8930, n8931,
n8932, n8933, n8934, n8935, n8936, n8937, n8938, n8939, n8940, n8941,
n8942;
wire [105:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [11:0] S_Oper_A_exp;
wire [52:1] Add_result;
wire [52:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [11:0] Exp_module_Data_S;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_63_ ( .D(n608), .CK(clk), .RN(
n8924), .Q(Op_MY[63]) );
DFFRX4TS FS_Module_state_reg_reg_2_ ( .D(n604), .CK(clk), .RN(n8908), .Q(
FS_Module_state_reg[2]), .QN(n8848) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_51_ ( .D(n590), .CK(clk), .RN(
n8925), .Q(Op_MX[51]), .QN(n875) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_49_ ( .D(n588), .CK(clk), .RN(
n8925), .Q(Op_MX[49]), .QN(n907) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_47_ ( .D(n586), .CK(clk), .RN(
n8925), .Q(Op_MX[47]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_45_ ( .D(n584), .CK(clk), .RN(
n8926), .Q(Op_MX[45]), .QN(n911) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_43_ ( .D(n582), .CK(clk), .RN(
n8926), .Q(Op_MX[43]), .QN(n722) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_42_ ( .D(n581), .CK(clk), .RN(
n8926), .Q(Op_MX[42]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_41_ ( .D(n580), .CK(clk), .RN(
n8926), .Q(Op_MX[41]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_39_ ( .D(n578), .CK(clk), .RN(
n8926), .Q(Op_MX[39]), .QN(n623) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_37_ ( .D(n576), .CK(clk), .RN(
n8926), .Q(Op_MX[37]), .QN(n667) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_36_ ( .D(n575), .CK(clk), .RN(
n8926), .Q(Op_MX[36]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_33_ ( .D(n572), .CK(clk), .RN(
n8927), .Q(Op_MX[33]), .QN(n647) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n570), .CK(clk), .RN(
n8927), .Q(Op_MX[31]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n569), .CK(clk), .RN(
n8927), .Q(Op_MX[30]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n568), .CK(clk), .RN(
n8927), .Q(Op_MX[29]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n566), .CK(clk), .RN(
n8927), .Q(Op_MX[27]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n564), .CK(clk), .RN(
n8928), .Q(Op_MX[25]), .QN(n659) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n562), .CK(clk), .RN(
n8928), .Q(Op_MX[23]), .QN(n663) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n560), .CK(clk), .RN(
n8928), .Q(Op_MX[21]), .QN(n8898) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n559), .CK(clk), .RN(
n8928), .Q(Op_MX[20]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n558), .CK(clk), .RN(
n8928), .Q(Op_MX[19]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n556), .CK(clk), .RN(
n8928), .Q(Op_MX[17]), .QN(n665) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n555), .CK(clk), .RN(
n8928), .Q(Op_MX[16]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n552), .CK(clk), .RN(
n8929), .Q(Op_MX[13]), .QN(n666) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n550), .CK(clk), .RN(
n8929), .Q(Op_MX[11]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n546), .CK(clk), .RN(
n8929), .Q(Op_MX[7]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n544), .CK(clk), .RN(
n8930), .Q(Op_MX[5]), .QN(n664) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n542), .CK(clk), .RN(
n8930), .Q(Op_MX[3]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n540), .CK(clk), .RN(
n8930), .Q(Op_MX[1]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n539), .CK(clk), .RN(
n8930), .Q(Op_MX[0]), .QN(n906) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n471), .CK(clk), .RN(n8935),
.Q(Add_result[1]), .QN(n8893) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n472), .CK(clk), .RN(n8935),
.QN(n8895) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_51_ ( .D(n526), .CK(clk), .RN(
n8937), .Q(Op_MY[51]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_50_ ( .D(n525), .CK(clk), .RN(
n8937), .Q(Op_MY[50]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_49_ ( .D(n524), .CK(clk), .RN(
n8937), .Q(Op_MY[49]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_48_ ( .D(n523), .CK(clk), .RN(
n8937), .Q(Op_MY[48]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_47_ ( .D(n522), .CK(clk), .RN(
n8937), .Q(Op_MY[47]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_46_ ( .D(n521), .CK(clk), .RN(
n8937), .Q(Op_MY[46]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_45_ ( .D(n520), .CK(clk), .RN(
n8937), .Q(Op_MY[45]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_44_ ( .D(n519), .CK(clk), .RN(
n8938), .Q(Op_MY[44]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_43_ ( .D(n518), .CK(clk), .RN(
n8938), .Q(Op_MY[43]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_42_ ( .D(n517), .CK(clk), .RN(
n8938), .Q(Op_MY[42]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_41_ ( .D(n516), .CK(clk), .RN(
n8938), .Q(Op_MY[41]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_40_ ( .D(n515), .CK(clk), .RN(
n8938), .Q(Op_MY[40]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_39_ ( .D(n514), .CK(clk), .RN(
n8938), .Q(Op_MY[39]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_38_ ( .D(n513), .CK(clk), .RN(
n8938), .Q(Op_MY[38]), .QN(n650) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_37_ ( .D(n512), .CK(clk), .RN(
n8938), .Q(Op_MY[37]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_36_ ( .D(n511), .CK(clk), .RN(
n8938), .Q(Op_MY[36]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_35_ ( .D(n510), .CK(clk), .RN(
n8938), .Q(Op_MY[35]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_34_ ( .D(n509), .CK(clk), .RN(
n8174), .Q(Op_MY[34]), .QN(n657) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_33_ ( .D(n508), .CK(clk), .RN(
n8929), .Q(Op_MY[33]), .QN(n621) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_32_ ( .D(n507), .CK(clk), .RN(
n8927), .Q(Op_MY[32]), .QN(n658) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n506), .CK(clk), .RN(
n8910), .Q(Op_MY[31]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n505), .CK(clk), .RN(
n8940), .Q(Op_MY[30]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n504), .CK(clk), .RN(
n8174), .Q(Op_MY[29]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n503), .CK(clk), .RN(
n8940), .Q(Op_MY[28]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n502), .CK(clk), .RN(
n8174), .Q(Op_MY[27]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n501), .CK(clk), .RN(
n8925), .Q(Op_MY[26]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n500), .CK(clk), .RN(
n8939), .Q(Op_MY[25]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n499), .CK(clk), .RN(
n8939), .Q(Op_MY[24]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n498), .CK(clk), .RN(
n8939), .Q(Op_MY[23]), .QN(n648) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n497), .CK(clk), .RN(
n8939), .Q(Op_MY[22]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n496), .CK(clk), .RN(
n8939), .Q(Op_MY[21]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n495), .CK(clk), .RN(
n8939), .Q(Op_MY[20]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n494), .CK(clk), .RN(
n8939), .Q(Op_MY[19]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n493), .CK(clk), .RN(
n8939), .Q(Op_MY[18]), .QN(n668) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n492), .CK(clk), .RN(
n8939), .Q(Op_MY[17]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n491), .CK(clk), .RN(
n8916), .Q(Op_MY[16]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n490), .CK(clk), .RN(
n8909), .Q(Op_MY[15]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n489), .CK(clk), .RN(
n8909), .Q(Op_MY[14]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n488), .CK(clk), .RN(
n8909), .Q(Op_MY[13]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n487), .CK(clk), .RN(
n8909), .Q(Op_MY[12]), .QN(n622) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n486), .CK(clk), .RN(
n8909), .Q(Op_MY[11]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n485), .CK(clk), .RN(
n8909), .Q(Op_MY[10]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n483), .CK(clk), .RN(
n8909), .Q(Op_MY[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n482), .CK(clk), .RN(
n8909), .Q(Op_MY[7]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n481), .CK(clk), .RN(
n8910), .Q(Op_MY[6]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n480), .CK(clk), .RN(
n8910), .Q(Op_MY[5]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n479), .CK(clk), .RN(
n8910), .Q(Op_MY[4]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n478), .CK(clk), .RN(
n8910), .Q(Op_MY[3]), .QN(n645) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n477), .CK(clk), .RN(
n8910), .Q(Op_MY[2]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n476), .CK(clk), .RN(
n8910), .Q(Op_MY[1]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n475), .CK(clk), .RN(
n8910), .Q(Op_MY[0]), .QN(n910) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n418), .CK(clk), .RN(n8910), .Q(
FSM_selector_B[0]), .QN(n8852) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n353), .CK(clk),
.RN(n8917), .Q(Sgf_normalized_result[1]), .QN(n8891) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n352), .CK(clk),
.RN(n8917), .Q(Sgf_normalized_result[0]), .QN(n8892) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_53_ ( .D(Sgf_operation_n56), .CK(clk),
.RN(n8899), .Q(P_Sgf[53]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_52_ ( .D(Sgf_operation_n57), .CK(clk),
.RN(n8899), .QN(n674) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_11_ ( .D(n405), .CK(clk), .RN(n8912),
.Q(exp_oper_result[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n286),
.CK(clk), .RN(n8924), .Q(final_result_ieee[63]), .QN(n8896) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n474), .CK(clk),
.RN(n8924), .Q(zero_flag), .QN(n8894) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n403), .CK(clk),
.RN(n8912), .Q(Sgf_normalized_result[51]), .QN(n8890) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n389), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[37]), .QN(n8889) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n383), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[31]), .QN(n8888) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n385), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[33]), .QN(n8887) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n387), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[35]), .QN(n8886) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n393), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[41]), .QN(n8885) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n355), .CK(clk),
.RN(n8917), .Q(Sgf_normalized_result[3]), .QN(n8884) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n359), .CK(clk),
.RN(n8916), .Q(Sgf_normalized_result[7]), .QN(n8883) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n365), .CK(clk),
.RN(n8916), .Q(Sgf_normalized_result[13]), .QN(n8882) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n367), .CK(clk),
.RN(n8916), .Q(Sgf_normalized_result[15]), .QN(n8881) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n369), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[17]), .QN(n8880) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n371), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[19]), .QN(n8879) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n361), .CK(clk),
.RN(n8916), .Q(Sgf_normalized_result[9]), .QN(n8878) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n363), .CK(clk),
.RN(n8916), .Q(Sgf_normalized_result[11]), .QN(n8877) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n373), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[21]), .QN(n8876) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n375), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[23]), .QN(n8875) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n377), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[25]), .QN(n8874) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n379), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[27]), .QN(n8873) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n381), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[29]), .QN(n8872) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n388), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[36]), .QN(n8870) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n366), .CK(clk),
.RN(n8916), .Q(Sgf_normalized_result[14]), .QN(n8869) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n358), .CK(clk),
.RN(n8917), .Q(Sgf_normalized_result[6]), .QN(n8868) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n364), .CK(clk),
.RN(n8916), .Q(Sgf_normalized_result[12]), .QN(n8867) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n368), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[16]), .QN(n8866) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n370), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[18]), .QN(n8865) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n384), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[32]), .QN(n8864) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n386), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[34]), .QN(n8863) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n374), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[22]), .QN(n8862) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n378), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[26]), .QN(n8861) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n382), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[30]), .QN(n8860) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n360), .CK(clk),
.RN(n8916), .Q(Sgf_normalized_result[8]), .QN(n8859) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n362), .CK(clk),
.RN(n8916), .Q(Sgf_normalized_result[10]), .QN(n8858) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n372), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[20]), .QN(n8857) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n376), .CK(clk),
.RN(n8915), .Q(Sgf_normalized_result[24]), .QN(n8856) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n380), .CK(clk),
.RN(n8914), .Q(Sgf_normalized_result[28]), .QN(n8855) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n392), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[40]), .QN(n8854) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n390), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[38]), .QN(n8853) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n602), .CK(clk), .RN(n8912), .Q(FSM_selector_C),
.QN(n8850) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n350),
.CK(clk), .RN(n8917), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n349),
.CK(clk), .RN(n8917), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n348),
.CK(clk), .RN(n8918), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n347),
.CK(clk), .RN(n8918), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n346),
.CK(clk), .RN(n8918), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n345),
.CK(clk), .RN(n8918), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n344),
.CK(clk), .RN(n8918), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n343),
.CK(clk), .RN(n8918), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n342),
.CK(clk), .RN(n8918), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n341),
.CK(clk), .RN(n8918), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n340),
.CK(clk), .RN(n8918), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n339),
.CK(clk), .RN(n8918), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n338),
.CK(clk), .RN(n8919), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n337),
.CK(clk), .RN(n8919), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n336),
.CK(clk), .RN(n8919), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n335),
.CK(clk), .RN(n8919), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n334),
.CK(clk), .RN(n8919), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n333),
.CK(clk), .RN(n8919), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n332),
.CK(clk), .RN(n8919), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n331),
.CK(clk), .RN(n8919), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n330),
.CK(clk), .RN(n8919), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n329),
.CK(clk), .RN(n8919), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n328),
.CK(clk), .RN(n8920), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n327),
.CK(clk), .RN(n8920), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n326),
.CK(clk), .RN(n8920), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n325),
.CK(clk), .RN(n8920), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n324),
.CK(clk), .RN(n8920), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n323),
.CK(clk), .RN(n8920), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n322),
.CK(clk), .RN(n8920), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n321),
.CK(clk), .RN(n8920), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n320),
.CK(clk), .RN(n8920), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n319),
.CK(clk), .RN(n8920), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n318),
.CK(clk), .RN(n8921), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n317),
.CK(clk), .RN(n8921), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n316),
.CK(clk), .RN(n8921), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n315),
.CK(clk), .RN(n8921), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n314),
.CK(clk), .RN(n8921), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n313),
.CK(clk), .RN(n8921), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n312),
.CK(clk), .RN(n8921), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n311),
.CK(clk), .RN(n8921), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n310),
.CK(clk), .RN(n8921), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n309),
.CK(clk), .RN(n8921), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n308),
.CK(clk), .RN(n8922), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n307),
.CK(clk), .RN(n8922), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n306),
.CK(clk), .RN(n8922), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n305),
.CK(clk), .RN(n8922), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n304),
.CK(clk), .RN(n8922), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n303),
.CK(clk), .RN(n8922), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n302),
.CK(clk), .RN(n8922), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n301),
.CK(clk), .RN(n8922), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n300),
.CK(clk), .RN(n8922), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n299),
.CK(clk), .RN(n8922), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n298),
.CK(clk), .RN(n8923), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n297),
.CK(clk), .RN(n8923), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n296),
.CK(clk), .RN(n8923), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n295),
.CK(clk), .RN(n8923), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n294),
.CK(clk), .RN(n8923), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n293),
.CK(clk), .RN(n8923), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n292),
.CK(clk), .RN(n8923), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n291),
.CK(clk), .RN(n8923), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n290),
.CK(clk), .RN(n8923), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n289),
.CK(clk), .RN(n8923), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n288),
.CK(clk), .RN(n8924), .Q(final_result_ieee[62]) );
CMPR32X2TS DP_OP_31J26_122_605_U13 ( .A(S_Oper_A_exp[0]), .B(n780), .C(
DP_OP_31J26_122_605_n28), .CO(DP_OP_31J26_122_605_n12), .S(
Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_31J26_122_605_U11 ( .A(DP_OP_31J26_122_605_n26), .B(
S_Oper_A_exp[2]), .C(DP_OP_31J26_122_605_n11), .CO(
DP_OP_31J26_122_605_n10), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_31J26_122_605_U9 ( .A(DP_OP_31J26_122_605_n24), .B(
S_Oper_A_exp[4]), .C(DP_OP_31J26_122_605_n9), .CO(
DP_OP_31J26_122_605_n8), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_31J26_122_605_U8 ( .A(DP_OP_31J26_122_605_n23), .B(
S_Oper_A_exp[5]), .C(DP_OP_31J26_122_605_n8), .CO(
DP_OP_31J26_122_605_n7), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_31J26_122_605_U7 ( .A(DP_OP_31J26_122_605_n22), .B(
S_Oper_A_exp[6]), .C(DP_OP_31J26_122_605_n7), .CO(
DP_OP_31J26_122_605_n6), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_31J26_122_605_U5 ( .A(DP_OP_31J26_122_605_n20), .B(
S_Oper_A_exp[8]), .C(DP_OP_31J26_122_605_n5), .CO(
DP_OP_31J26_122_605_n4), .S(Exp_module_Data_S[8]) );
CMPR32X2TS DP_OP_31J26_122_605_U3 ( .A(DP_OP_31J26_122_605_n18), .B(
S_Oper_A_exp[10]), .C(DP_OP_31J26_122_605_n3), .CO(
DP_OP_31J26_122_605_n2), .S(Exp_module_Data_S[10]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n545), .CK(clk), .RN(
n8929), .Q(Op_MX[6]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_38_ ( .D(n577), .CK(clk), .RN(
n8926), .Q(Op_MX[38]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n563), .CK(clk), .RN(
n8928), .Q(Op_MX[24]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n567), .CK(clk), .RN(
n8927), .Q(Op_MX[28]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n557), .CK(clk), .RN(
n8928), .Q(Op_MX[18]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_46_ ( .D(n585), .CK(clk), .RN(
n8925), .Q(Op_MX[46]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n551), .CK(clk), .RN(
n8929), .Q(Op_MX[12]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_50_ ( .D(n589), .CK(clk), .RN(
n8925), .Q(Op_MX[50]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n565), .CK(clk), .RN(
n8927), .Q(Op_MX[26]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_32_ ( .D(n571), .CK(clk), .RN(
n8927), .Q(Op_MX[32]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n549), .CK(clk), .RN(
n8929), .Q(Op_MX[10]), .QN(n876) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_44_ ( .D(n583), .CK(clk), .RN(
n8926), .Q(Op_MX[44]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n553), .CK(clk), .RN(
n8929), .Q(Op_MX[14]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n541), .CK(clk), .RN(
n8930), .Q(Op_MX[2]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_34_ ( .D(n573), .CK(clk), .RN(
n8927), .Q(Op_MX[34]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_40_ ( .D(n579), .CK(clk), .RN(
n8926), .Q(Op_MX[40]), .QN(n877) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n543), .CK(clk), .RN(
n8930), .Q(Op_MX[4]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n561), .CK(clk), .RN(
n8928), .Q(Op_MX[22]), .QN(n670) );
DFFSRX2TS Sel_B_Q_reg_1_ ( .D(n417), .CK(clk), .SN(1'b1), .RN(n8173), .Q(
FSM_selector_B[1]), .QN(n8941) );
DFFSRHQX2TS Sgf_operation_finalreg_Q_reg_50_ ( .D(Sgf_operation_n59), .CK(
clk), .SN(1'b1), .RN(n8942), .Q(P_Sgf[50]) );
DFFRHQX4TS Sgf_operation_finalreg_Q_reg_86_ ( .D(Sgf_operation_n23), .CK(clk), .RN(n8899), .Q(P_Sgf[86]) );
DFFRHQX4TS Sgf_operation_finalreg_Q_reg_97_ ( .D(Sgf_operation_n12), .CK(clk), .RN(n8900), .Q(P_Sgf[97]) );
DFFRHQX4TS Sgf_operation_finalreg_Q_reg_95_ ( .D(Sgf_operation_n14), .CK(clk), .RN(n8900), .Q(P_Sgf[95]) );
DFFRHQX4TS Sgf_operation_finalreg_Q_reg_85_ ( .D(Sgf_operation_n24), .CK(clk), .RN(n8899), .Q(P_Sgf[85]) );
DFFRHQX4TS Sgf_operation_finalreg_Q_reg_77_ ( .D(Sgf_operation_n32), .CK(clk), .RN(n8171), .Q(P_Sgf[77]) );
DFFRHQX4TS Sgf_operation_finalreg_Q_reg_82_ ( .D(Sgf_operation_n27), .CK(clk), .RN(n8908), .Q(P_Sgf[82]) );
DFFRHQX4TS Sgf_operation_finalreg_Q_reg_72_ ( .D(Sgf_operation_n37), .CK(clk), .RN(n8942), .Q(P_Sgf[72]) );
DFFRHQX4TS Sgf_operation_finalreg_Q_reg_75_ ( .D(Sgf_operation_n34), .CK(clk), .RN(n8942), .Q(P_Sgf[75]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n391), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[39]), .QN(n8849) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n605), .CK(clk), .RN(n8908), .Q(
FS_Module_state_reg[1]), .QN(n8851) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n354), .CK(clk),
.RN(n8917), .Q(Sgf_normalized_result[2]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n356), .CK(clk),
.RN(n8917), .Q(Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n357), .CK(clk),
.RN(n8917), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_66_ ( .D(Sgf_operation_n43), .CK(clk),
.RN(n8907), .Q(P_Sgf[66]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_60_ ( .D(Sgf_operation_n49), .CK(clk),
.RN(n8907), .Q(P_Sgf[60]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_62_ ( .D(Sgf_operation_n47), .CK(clk),
.RN(n8907), .Q(P_Sgf[62]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_63_ ( .D(Sgf_operation_n46), .CK(clk),
.RN(n8907), .Q(P_Sgf[63]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_64_ ( .D(Sgf_operation_n45), .CK(clk),
.RN(n8907), .Q(P_Sgf[64]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n394), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[42]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n396), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n398), .CK(clk),
.RN(n8912), .Q(Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n400), .CK(clk),
.RN(n8912), .Q(Sgf_normalized_result[48]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n402), .CK(clk),
.RN(n8912), .Q(Sgf_normalized_result[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n395), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[43]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n397), .CK(clk),
.RN(n8913), .Q(Sgf_normalized_result[45]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n399), .CK(clk),
.RN(n8912), .Q(Sgf_normalized_result[47]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n401), .CK(clk),
.RN(n8912), .Q(Sgf_normalized_result[49]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_59_ ( .D(Sgf_operation_n50), .CK(clk),
.RN(n8907), .Q(P_Sgf[59]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_57_ ( .D(n596), .CK(clk), .RN(
n8909), .Q(Op_MX[57]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_61_ ( .D(n600), .CK(clk), .RN(
n8924), .Q(Op_MX[61]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_62_ ( .D(n601), .CK(clk), .RN(
n8924), .Q(Op_MX[62]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_52_ ( .D(n420), .CK(clk), .RN(n8936),
.Q(Add_result[52]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_52_ ( .D(n591), .CK(clk), .RN(
n8925), .Q(Op_MX[52]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_57_ ( .D(n532), .CK(clk), .RN(
n8936), .Q(Op_MY[57]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_61_ ( .D(n536), .CK(clk), .RN(
n8936), .Q(Op_MY[61]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_62_ ( .D(n537), .CK(clk), .RN(
n8936), .Q(Op_MY[62]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n408), .CK(clk), .RN(n8911),
.Q(exp_oper_result[8]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n409), .CK(clk), .RN(n8911),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n410), .CK(clk), .RN(n8911),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n412), .CK(clk), .RN(n8172),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n413), .CK(clk), .RN(n8172),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n414), .CK(clk), .RN(n8172),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n415), .CK(clk), .RN(n8172),
.Q(exp_oper_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_32_ ( .D(n440), .CK(clk), .RN(n8932),
.Q(Add_result[32]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_33_ ( .D(n439), .CK(clk), .RN(n8932),
.Q(Add_result[33]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_34_ ( .D(n438), .CK(clk), .RN(n8932),
.Q(Add_result[34]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_35_ ( .D(n437), .CK(clk), .RN(n8932),
.Q(Add_result[35]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_36_ ( .D(n436), .CK(clk), .RN(n8932),
.Q(Add_result[36]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_37_ ( .D(n435), .CK(clk), .RN(n8932),
.Q(Add_result[37]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_38_ ( .D(n434), .CK(clk), .RN(n8932),
.Q(Add_result[38]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_39_ ( .D(n433), .CK(clk), .RN(n8931),
.Q(Add_result[39]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_40_ ( .D(n432), .CK(clk), .RN(n8931),
.Q(Add_result[40]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_41_ ( .D(n431), .CK(clk), .RN(n8931),
.Q(Add_result[41]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n419), .CK(clk), .RN(
n8936), .Q(FSM_add_overflow_flag) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_51_ ( .D(n421), .CK(clk), .RN(n8930),
.Q(Add_result[51]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_53_ ( .D(n528), .CK(clk), .RN(
n8937), .Q(Op_MY[53]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_31_ ( .D(n441), .CK(clk), .RN(n8932),
.Q(Add_result[31]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n469), .CK(clk), .RN(n8935),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n466), .CK(clk), .RN(n8935),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n465), .CK(clk), .RN(n8935),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n464), .CK(clk), .RN(n8935),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n463), .CK(clk), .RN(n8935),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n452), .CK(clk), .RN(n8933),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n451), .CK(clk), .RN(n8933),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n450), .CK(clk), .RN(n8933),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n449), .CK(clk), .RN(n8933),
.Q(Add_result[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_24_ ( .D(n448), .CK(clk), .RN(n8933),
.Q(Add_result[24]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_25_ ( .D(n447), .CK(clk), .RN(n8933),
.Q(Add_result[25]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_26_ ( .D(n446), .CK(clk), .RN(n8933),
.Q(Add_result[26]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_27_ ( .D(n445), .CK(clk), .RN(n8933),
.Q(Add_result[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_28_ ( .D(n444), .CK(clk), .RN(n8933),
.Q(Add_result[28]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_29_ ( .D(n443), .CK(clk), .RN(n8933),
.Q(Add_result[29]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_30_ ( .D(n442), .CK(clk), .RN(n8932),
.Q(Add_result[30]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n351), .CK(clk), .RN(n8917),
.Q(underflow_flag), .QN(n8897) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n473), .CK(clk),
.RN(n8912), .Q(Sgf_normalized_result[52]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_31_ ( .D(Sgf_operation_n78), .CK(clk),
.RN(n8905), .Q(P_Sgf[31]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_40_ ( .D(Sgf_operation_n69), .CK(clk),
.RN(n8903), .Q(P_Sgf[40]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_51_ ( .D(Sgf_operation_n58), .CK(clk),
.RN(n8904), .Q(P_Sgf[51]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_49_ ( .D(Sgf_operation_n60), .CK(clk),
.RN(n8905), .Q(P_Sgf[49]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_33_ ( .D(Sgf_operation_n76), .CK(clk),
.RN(n8904), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_3_ ( .D(Sgf_operation_n106), .CK(clk),
.RN(n8906), .Q(P_Sgf[3]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_7_ ( .D(Sgf_operation_n102), .CK(clk),
.RN(n8902), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_8_ ( .D(Sgf_operation_n101), .CK(clk),
.RN(n8903), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_16_ ( .D(Sgf_operation_n93), .CK(clk),
.RN(n8901), .Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_18_ ( .D(Sgf_operation_n91), .CK(clk),
.RN(n8902), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_24_ ( .D(Sgf_operation_n85), .CK(clk),
.RN(n8901), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_28_ ( .D(Sgf_operation_n81), .CK(clk),
.RN(n8905), .Q(P_Sgf[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_63_ ( .D(n538), .CK(clk), .RN(
n8930), .Q(Op_MX[63]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_59_ ( .D(n598), .CK(clk), .RN(
n8924), .Q(Op_MX[59]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_55_ ( .D(n594), .CK(clk), .RN(
n8925), .Q(Op_MX[55]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_60_ ( .D(n599), .CK(clk), .RN(
n8924), .Q(Op_MX[60]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_56_ ( .D(n595), .CK(clk), .RN(
n8932), .Q(Op_MX[56]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_58_ ( .D(n597), .CK(clk), .RN(
n8924), .Q(Op_MX[58]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_54_ ( .D(n593), .CK(clk), .RN(
n8925), .Q(Op_MX[54]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_53_ ( .D(n592), .CK(clk), .RN(
n8925), .Q(Op_MX[53]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_59_ ( .D(n534), .CK(clk), .RN(
n8936), .Q(Op_MY[59]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_55_ ( .D(n530), .CK(clk), .RN(
n8936), .Q(Op_MY[55]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n416), .CK(clk), .RN(n8172),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n411), .CK(clk), .RN(n8172),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_9_ ( .D(n407), .CK(clk), .RN(n8172),
.Q(exp_oper_result[9]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_10_ ( .D(n406), .CK(clk), .RN(n8912),
.Q(exp_oper_result[10]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_60_ ( .D(n535), .CK(clk), .RN(
n8936), .Q(Op_MY[60]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_56_ ( .D(n531), .CK(clk), .RN(
n8936), .Q(Op_MY[56]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_58_ ( .D(n533), .CK(clk), .RN(
n8936), .Q(Op_MY[58]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_54_ ( .D(n529), .CK(clk), .RN(
n8937), .Q(Op_MY[54]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_50_ ( .D(n422), .CK(clk), .RN(n8930),
.Q(Add_result[50]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_49_ ( .D(n423), .CK(clk), .RN(n8930),
.Q(Add_result[49]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_48_ ( .D(n424), .CK(clk), .RN(n8931),
.Q(Add_result[48]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_47_ ( .D(n425), .CK(clk), .RN(n8931),
.Q(Add_result[47]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_46_ ( .D(n426), .CK(clk), .RN(n8931),
.Q(Add_result[46]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_45_ ( .D(n427), .CK(clk), .RN(n8931),
.Q(Add_result[45]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_44_ ( .D(n428), .CK(clk), .RN(n8931),
.Q(Add_result[44]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_43_ ( .D(n429), .CK(clk), .RN(n8931),
.Q(Add_result[43]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_42_ ( .D(n430), .CK(clk), .RN(n8931),
.Q(Add_result[42]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n470), .CK(clk), .RN(n8935),
.Q(Add_result[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n453), .CK(clk), .RN(n8934),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n454), .CK(clk), .RN(n8934),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n455), .CK(clk), .RN(n8934),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n456), .CK(clk), .RN(n8934),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n457), .CK(clk), .RN(n8934),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n458), .CK(clk), .RN(n8934),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n459), .CK(clk), .RN(n8934),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n460), .CK(clk), .RN(n8934),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n461), .CK(clk), .RN(n8934),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n462), .CK(clk), .RN(n8934),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n467), .CK(clk), .RN(n8935),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n468), .CK(clk), .RN(n8935),
.Q(Add_result[4]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_37_ ( .D(Sgf_operation_n72), .CK(clk),
.RN(n8905), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_38_ ( .D(Sgf_operation_n71), .CK(clk),
.RN(n8905), .Q(P_Sgf[38]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_41_ ( .D(Sgf_operation_n68), .CK(clk),
.RN(n8903), .Q(P_Sgf[41]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_6_ ( .D(Sgf_operation_n103), .CK(clk),
.RN(n8904), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_4_ ( .D(Sgf_operation_n105), .CK(clk),
.RN(n8905), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_26_ ( .D(Sgf_operation_n83), .CK(clk),
.RN(n8901), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_25_ ( .D(Sgf_operation_n84), .CK(clk),
.RN(n8902), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_21_ ( .D(Sgf_operation_n88), .CK(clk),
.RN(n8901), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_13_ ( .D(Sgf_operation_n96), .CK(clk),
.RN(n8902), .Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_12_ ( .D(Sgf_operation_n97), .CK(clk),
.RN(n8902), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_5_ ( .D(Sgf_operation_n104), .CK(clk),
.RN(n8905), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_1_ ( .D(Sgf_operation_n108), .CK(clk),
.RN(n8906), .Q(P_Sgf[1]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_27_ ( .D(Sgf_operation_n82), .CK(clk),
.RN(n8901), .Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_22_ ( .D(Sgf_operation_n87), .CK(clk),
.RN(n8901), .Q(P_Sgf[22]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_17_ ( .D(Sgf_operation_n92), .CK(clk),
.RN(n8902), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_15_ ( .D(Sgf_operation_n94), .CK(clk),
.RN(n8902), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_10_ ( .D(Sgf_operation_n99), .CK(clk),
.RN(n8903), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_9_ ( .D(Sgf_operation_n100), .CK(clk),
.RN(n8905), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_2_ ( .D(Sgf_operation_n107), .CK(clk),
.RN(n8906), .Q(P_Sgf[2]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_36_ ( .D(Sgf_operation_n73), .CK(clk),
.RN(n8905), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_23_ ( .D(Sgf_operation_n86), .CK(clk),
.RN(n8901), .Q(P_Sgf[23]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_20_ ( .D(Sgf_operation_n89), .CK(clk),
.RN(n8901), .Q(P_Sgf[20]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_19_ ( .D(Sgf_operation_n90), .CK(clk),
.RN(n8902), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_14_ ( .D(Sgf_operation_n95), .CK(clk),
.RN(n8902), .Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_11_ ( .D(Sgf_operation_n98), .CK(clk),
.RN(n8902), .Q(P_Sgf[11]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_0_ ( .D(Sgf_operation_n109), .CK(clk),
.RN(n8906), .Q(P_Sgf[0]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_30_ ( .D(Sgf_operation_n79), .CK(clk),
.RN(n8904), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_29_ ( .D(Sgf_operation_n80), .CK(clk),
.RN(n8904), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_34_ ( .D(Sgf_operation_n75), .CK(clk),
.RN(n8905), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_32_ ( .D(Sgf_operation_n77), .CK(clk),
.RN(n8904), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_35_ ( .D(Sgf_operation_n74), .CK(clk),
.RN(n8904), .Q(P_Sgf[35]) );
DFFSRX2TS Sel_A_Q_reg_0_ ( .D(n603), .CK(clk), .SN(1'b1), .RN(n624), .Q(
FSM_selector_A), .QN(n8871) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n606), .CK(clk), .RN(n8908), .Q(
FS_Module_state_reg[0]), .QN(n8847) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n404), .CK(clk), .RN(n8910), .Q(
Exp_module_Overflow_flag_A) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_52_ ( .D(n527), .CK(clk), .RN(
n8937), .Q(Op_MY[52]) );
DFFRHQX2TS FS_Module_state_reg_reg_3_ ( .D(n607), .CK(clk), .RN(n831), .Q(
FS_Module_state_reg[3]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_39_ ( .D(Sgf_operation_n70), .CK(clk), .RN(n8904), .Q(P_Sgf[39]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_58_ ( .D(Sgf_operation_n51), .CK(clk), .RN(n8906), .Q(P_Sgf[58]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_54_ ( .D(Sgf_operation_n55), .CK(clk), .RN(n8906), .Q(P_Sgf[54]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_44_ ( .D(Sgf_operation_n65), .CK(clk), .RN(n8903), .Q(P_Sgf[44]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_42_ ( .D(Sgf_operation_n67), .CK(clk), .RN(n8903), .Q(P_Sgf[42]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_45_ ( .D(Sgf_operation_n64), .CK(clk), .RN(n8903), .Q(P_Sgf[45]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_43_ ( .D(Sgf_operation_n66), .CK(clk), .RN(n8903), .Q(P_Sgf[43]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_46_ ( .D(Sgf_operation_n63), .CK(clk), .RN(n8904), .Q(P_Sgf[46]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_65_ ( .D(Sgf_operation_n44), .CK(clk), .RN(n8907), .Q(P_Sgf[65]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_61_ ( .D(Sgf_operation_n48), .CK(clk), .RN(n8907), .Q(P_Sgf[61]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_56_ ( .D(Sgf_operation_n53), .CK(clk), .RN(n8906), .Q(P_Sgf[56]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_57_ ( .D(Sgf_operation_n52), .CK(clk), .RN(n8906), .Q(P_Sgf[57]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_55_ ( .D(Sgf_operation_n54), .CK(clk), .RN(n8906), .Q(P_Sgf[55]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_98_ ( .D(Sgf_operation_n11), .CK(clk), .RN(n8900), .Q(P_Sgf[98]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_100_ ( .D(Sgf_operation_n9), .CK(clk), .RN(n8900), .Q(P_Sgf[100]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_88_ ( .D(Sgf_operation_n21), .CK(clk), .RN(n8899), .Q(P_Sgf[88]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_83_ ( .D(Sgf_operation_n26), .CK(clk), .RN(n8908), .Q(P_Sgf[83]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_101_ ( .D(Sgf_operation_n8), .CK(clk), .RN(n8900), .Q(P_Sgf[101]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_48_ ( .D(Sgf_operation_n61), .CK(clk), .RN(n8903), .Q(P_Sgf[48]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_47_ ( .D(Sgf_operation_n62), .CK(clk), .RN(n8903), .Q(P_Sgf[47]) );
ADDFHX2TS DP_OP_31J26_122_605_U12 ( .A(DP_OP_31J26_122_605_n27), .B(
S_Oper_A_exp[1]), .CI(DP_OP_31J26_122_605_n12), .CO(
DP_OP_31J26_122_605_n11), .S(Exp_module_Data_S[1]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n547), .CK(clk), .RN(
n624), .Q(Op_MX[8]) );
DFFRHQX8TS Operands_load_reg_XMRegister_Q_reg_35_ ( .D(n574), .CK(clk), .RN(
n624), .Q(Op_MX[35]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n484), .CK(clk), .RN(
n8909), .Q(Op_MY[9]) );
ADDFX2TS DP_OP_31J26_122_605_U2 ( .A(n8767), .B(S_Oper_A_exp[11]), .CI(
DP_OP_31J26_122_605_n2), .CO(DP_OP_31J26_122_605_n1), .S(
Exp_module_Data_S[11]) );
DFFRHQX4TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n554), .CK(clk), .RN(
n8929), .Q(n644) );
ADDFHX2TS DP_OP_31J26_122_605_U10 ( .A(DP_OP_31J26_122_605_n25), .B(
S_Oper_A_exp[3]), .CI(DP_OP_31J26_122_605_n10), .CO(
DP_OP_31J26_122_605_n9), .S(Exp_module_Data_S[3]) );
ADDFHX2TS DP_OP_31J26_122_605_U6 ( .A(DP_OP_31J26_122_605_n21), .B(
S_Oper_A_exp[7]), .CI(DP_OP_31J26_122_605_n6), .CO(
DP_OP_31J26_122_605_n5), .S(Exp_module_Data_S[7]) );
DFFRHQX1TS Sgf_operation_finalreg_Q_reg_70_ ( .D(Sgf_operation_n39), .CK(clk), .RN(n8171), .Q(P_Sgf[70]) );
DFFRHQX4TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n548), .CK(clk), .RN(
n8929), .Q(n675) );
DFFRHQX4TS Operands_load_reg_XMRegister_Q_reg_48_ ( .D(n587), .CK(clk), .RN(
n8172), .Q(Op_MX[48]) );
ADDFHX2TS DP_OP_31J26_122_605_U4 ( .A(DP_OP_31J26_122_605_n19), .B(
S_Oper_A_exp[9]), .CI(DP_OP_31J26_122_605_n4), .CO(
DP_OP_31J26_122_605_n3), .S(Exp_module_Data_S[9]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_67_ ( .D(Sgf_operation_n42), .CK(clk), .RN(n831), .Q(P_Sgf[67]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_68_ ( .D(Sgf_operation_n41), .CK(clk), .RN(n8907), .Q(P_Sgf[68]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_79_ ( .D(Sgf_operation_n30), .CK(clk), .RN(n8908), .Q(P_Sgf[79]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_73_ ( .D(Sgf_operation_n36), .CK(clk), .RN(n8942), .Q(P_Sgf[73]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_69_ ( .D(Sgf_operation_n40), .CK(clk), .RN(n8942), .Q(P_Sgf[69]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_71_ ( .D(Sgf_operation_n38), .CK(clk), .RN(n8942), .Q(P_Sgf[71]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_92_ ( .D(Sgf_operation_n17), .CK(clk), .RN(n8900), .Q(P_Sgf[92]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_76_ ( .D(Sgf_operation_n33), .CK(clk), .RN(n8171), .Q(P_Sgf[76]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_74_ ( .D(Sgf_operation_n35), .CK(clk), .RN(n8171), .Q(P_Sgf[74]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_81_ ( .D(Sgf_operation_n28), .CK(clk), .RN(n8908), .Q(P_Sgf[81]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_78_ ( .D(Sgf_operation_n31), .CK(clk), .RN(n8171), .Q(P_Sgf[78]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_80_ ( .D(Sgf_operation_n29), .CK(clk), .RN(n8908), .Q(P_Sgf[80]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_96_ ( .D(Sgf_operation_n13), .CK(clk), .RN(n8900), .Q(P_Sgf[96]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_103_ ( .D(Sgf_operation_n6), .CK(clk), .RN(n8901), .Q(P_Sgf[103]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_91_ ( .D(Sgf_operation_n18), .CK(clk), .RN(n8899), .Q(P_Sgf[91]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_87_ ( .D(Sgf_operation_n22), .CK(clk), .RN(n8899), .Q(P_Sgf[87]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_90_ ( .D(Sgf_operation_n19), .CK(clk), .RN(n8899), .Q(P_Sgf[90]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_84_ ( .D(Sgf_operation_n25), .CK(clk), .RN(n8899), .Q(P_Sgf[84]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_89_ ( .D(Sgf_operation_n20), .CK(clk), .RN(n8899), .Q(P_Sgf[89]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_99_ ( .D(Sgf_operation_n10), .CK(clk), .RN(n8900), .Q(P_Sgf[99]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_94_ ( .D(Sgf_operation_n15), .CK(clk), .RN(n8900), .Q(P_Sgf[94]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_93_ ( .D(Sgf_operation_n16), .CK(clk), .RN(n8900), .Q(P_Sgf[93]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_102_ ( .D(Sgf_operation_n7), .CK(clk), .RN(n8901), .Q(P_Sgf[102]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_104_ ( .D(Sgf_operation_n5), .CK(clk), .RN(n8908), .Q(P_Sgf[104]) );
DFFRHQX2TS Sgf_operation_finalreg_Q_reg_105_ ( .D(Sgf_operation_n4), .CK(clk), .RN(n8906), .Q(P_Sgf[105]) );
CLKMX2X2TS U640 ( .A(Exp_module_Data_S[9]), .B(exp_oper_result[9]), .S0(n693), .Y(n407) );
CLKMX2X2TS U641 ( .A(n8205), .B(P_Sgf[50]), .S0(n774), .Y(Sgf_operation_n59)
);
CLKMX2X2TS U642 ( .A(n7874), .B(P_Sgf[38]), .S0(n774), .Y(Sgf_operation_n71)
);
CLKMX2X2TS U643 ( .A(n8025), .B(P_Sgf[39]), .S0(n775), .Y(Sgf_operation_n70)
);
CLKMX2X2TS U644 ( .A(n8038), .B(P_Sgf[44]), .S0(n777), .Y(Sgf_operation_n65)
);
CLKMX2X2TS U645 ( .A(n7935), .B(P_Sgf[48]), .S0(n8595), .Y(Sgf_operation_n61) );
CLKMX2X2TS U646 ( .A(n7923), .B(P_Sgf[47]), .S0(n8638), .Y(Sgf_operation_n62) );
CLKMX2X2TS U647 ( .A(n8050), .B(P_Sgf[45]), .S0(n8608), .Y(Sgf_operation_n64) );
CLKMX2X2TS U648 ( .A(n8065), .B(P_Sgf[42]), .S0(n776), .Y(Sgf_operation_n67)
);
CLKMX2X2TS U649 ( .A(n8058), .B(P_Sgf[43]), .S0(n7815), .Y(Sgf_operation_n66) );
CLKMX2X2TS U650 ( .A(n8031), .B(P_Sgf[46]), .S0(n726), .Y(Sgf_operation_n63)
);
CLKMX2X2TS U651 ( .A(n8073), .B(P_Sgf[56]), .S0(n776), .Y(Sgf_operation_n53)
);
CLKMX2X2TS U652 ( .A(n7976), .B(P_Sgf[29]), .S0(n777), .Y(Sgf_operation_n80)
);
CLKMX2X2TS U653 ( .A(n7991), .B(P_Sgf[28]), .S0(n8608), .Y(Sgf_operation_n81) );
CLKMX2X2TS U654 ( .A(n7896), .B(P_Sgf[33]), .S0(n725), .Y(Sgf_operation_n76)
);
CLKMX2X2TS U655 ( .A(n7954), .B(P_Sgf[27]), .S0(n728), .Y(Sgf_operation_n82)
);
CLKMX2X2TS U656 ( .A(n7982), .B(P_Sgf[30]), .S0(n725), .Y(Sgf_operation_n79)
);
CLKMX2X2TS U657 ( .A(n8712), .B(P_Sgf[22]), .S0(n8608), .Y(Sgf_operation_n87) );
CLKMX2X2TS U658 ( .A(n8749), .B(P_Sgf[23]), .S0(n725), .Y(Sgf_operation_n86)
);
CLKMX2X2TS U659 ( .A(n7858), .B(P_Sgf[31]), .S0(n725), .Y(Sgf_operation_n78)
);
CLKMX2X2TS U660 ( .A(n7946), .B(P_Sgf[26]), .S0(n727), .Y(Sgf_operation_n83)
);
CLKMX2X2TS U661 ( .A(n8687), .B(P_Sgf[25]), .S0(n8748), .Y(Sgf_operation_n84) );
OAI21X2TS U662 ( .A0(n7339), .A1(n7792), .B0(n7338), .Y(Sgf_operation_n5) );
OAI21X2TS U663 ( .A0(n7602), .A1(n7815), .B0(n7601), .Y(Sgf_operation_n25)
);
OAI21X2TS U664 ( .A0(n7723), .A1(n728), .B0(n7722), .Y(Sgf_operation_n19) );
OAI21X2TS U665 ( .A0(n7563), .A1(n774), .B0(n7562), .Y(Sgf_operation_n28) );
OAI21X2TS U666 ( .A0(n7836), .A1(n7792), .B0(n7835), .Y(Sgf_operation_n44)
);
OAI21X2TS U667 ( .A0(n7350), .A1(n8748), .B0(n7349), .Y(Sgf_operation_n40)
);
OAI21X2TS U668 ( .A0(n7656), .A1(n8748), .B0(n7655), .Y(Sgf_operation_n15)
);
OAI21X2TS U669 ( .A0(n7575), .A1(n776), .B0(n7574), .Y(Sgf_operation_n31) );
OAI21X2TS U670 ( .A0(n7793), .A1(n776), .B0(n7791), .Y(Sgf_operation_n29) );
OAI21X2TS U671 ( .A0(n7405), .A1(n728), .B0(n7404), .Y(Sgf_operation_n22) );
OAI21X2TS U672 ( .A0(n872), .A1(n832), .B0(n871), .Y(Sgf_operation_n43) );
OAI21X2TS U673 ( .A0(n7640), .A1(n832), .B0(n7639), .Y(Sgf_operation_n38) );
OAI21X1TS U674 ( .A0(n7393), .A1(n832), .B0(n7392), .Y(Sgf_operation_n41) );
OAI21X1TS U675 ( .A0(n7529), .A1(n8608), .B0(n7528), .Y(Sgf_operation_n7) );
CLKBUFX3TS U676 ( .A(n8842), .Y(n8840) );
INVX2TS U677 ( .A(n8842), .Y(n8833) );
INVX2TS U678 ( .A(n8842), .Y(n8762) );
INVX2TS U679 ( .A(n8842), .Y(n8764) );
INVX2TS U680 ( .A(n8842), .Y(n8835) );
INVX2TS U681 ( .A(n8839), .Y(n8834) );
INVX2TS U682 ( .A(n8839), .Y(n8836) );
INVX2TS U683 ( .A(n8446), .Y(n8387) );
INVX2TS U684 ( .A(n8446), .Y(n8319) );
INVX2TS U685 ( .A(n671), .Y(n692) );
INVX2TS U686 ( .A(n8841), .Y(n8761) );
INVX2TS U687 ( .A(n8841), .Y(n8763) );
INVX2TS U688 ( .A(n8841), .Y(n8838) );
NAND2X1TS U689 ( .A(n832), .B(P_Sgf[69]), .Y(n7349) );
NAND2X1TS U690 ( .A(n7815), .B(P_Sgf[97]), .Y(n7675) );
NAND2X1TS U691 ( .A(n7792), .B(P_Sgf[104]), .Y(n7338) );
NAND2X1TS U692 ( .A(n7792), .B(P_Sgf[82]), .Y(n7459) );
NAND2X1TS U693 ( .A(n8753), .B(P_Sgf[71]), .Y(n7639) );
NAND2X1TS U694 ( .A(n7815), .B(P_Sgf[93]), .Y(n7814) );
NAND2XLTS U695 ( .A(n7792), .B(P_Sgf[75]), .Y(n7628) );
NAND2XLTS U696 ( .A(n832), .B(P_Sgf[101]), .Y(n7665) );
NAND2XLTS U697 ( .A(n8753), .B(P_Sgf[102]), .Y(n7528) );
NAND2XLTS U698 ( .A(n8753), .B(P_Sgf[96]), .Y(n7487) );
NAND2XLTS U699 ( .A(n7815), .B(P_Sgf[95]), .Y(n7687) );
NAND2XLTS U700 ( .A(n8753), .B(P_Sgf[100]), .Y(n7708) );
NAND2XLTS U701 ( .A(n832), .B(P_Sgf[68]), .Y(n7392) );
NAND2XLTS U702 ( .A(n832), .B(P_Sgf[70]), .Y(n7447) );
NAND2XLTS U703 ( .A(n7792), .B(P_Sgf[79]), .Y(n7781) );
NAND2XLTS U704 ( .A(n8608), .B(P_Sgf[90]), .Y(n7722) );
NAND2XLTS U705 ( .A(n8608), .B(P_Sgf[86]), .Y(n7554) );
NAND2X1TS U706 ( .A(n776), .B(P_Sgf[65]), .Y(n7835) );
NAND2X1TS U707 ( .A(n776), .B(P_Sgf[66]), .Y(n871) );
NAND2X1TS U708 ( .A(n727), .B(P_Sgf[84]), .Y(n7601) );
NAND2XLTS U709 ( .A(n726), .B(P_Sgf[89]), .Y(n7729) );
NAND2XLTS U710 ( .A(n776), .B(P_Sgf[80]), .Y(n7791) );
NAND2XLTS U711 ( .A(n727), .B(P_Sgf[78]), .Y(n7574) );
NAND2XLTS U712 ( .A(n726), .B(P_Sgf[62]), .Y(n7413) );
NAND2XLTS U713 ( .A(n777), .B(P_Sgf[99]), .Y(n7803) );
NAND2X1TS U714 ( .A(n775), .B(P_Sgf[94]), .Y(n7655) );
NAND2XLTS U715 ( .A(n777), .B(P_Sgf[98]), .Y(n7700) );
XOR2X2TS U716 ( .A(n870), .B(n8137), .Y(n872) );
XNOR2X2TS U717 ( .A(n7527), .B(n7526), .Y(n7529) );
XNOR2X2TS U718 ( .A(n7573), .B(n7572), .Y(n7575) );
XNOR2X2TS U719 ( .A(n7790), .B(n7789), .Y(n7793) );
XNOR2X1TS U720 ( .A(n8204), .B(n8203), .Y(n8205) );
XNOR2X2TS U721 ( .A(n7912), .B(n7911), .Y(n7913) );
XNOR2X2TS U722 ( .A(n7486), .B(n7485), .Y(n7488) );
XOR2X2TS U723 ( .A(n7348), .B(n885), .Y(n7350) );
XOR2X2TS U724 ( .A(n7403), .B(n884), .Y(n7405) );
XOR2X2TS U725 ( .A(n7654), .B(n900), .Y(n7656) );
XNOR2X1TS U726 ( .A(n7934), .B(n7933), .Y(n7935) );
XOR2X1TS U727 ( .A(n8092), .B(n8091), .Y(n8093) );
XOR2X2TS U728 ( .A(n8104), .B(n8103), .Y(n8105) );
XOR2X2TS U729 ( .A(n8133), .B(n8132), .Y(n8134) );
XOR2X2TS U730 ( .A(n7616), .B(n879), .Y(n7618) );
CLKXOR2X2TS U731 ( .A(n7638), .B(n902), .Y(n7640) );
XOR2X1TS U732 ( .A(n7892), .B(n7891), .Y(n7893) );
XOR2X1TS U733 ( .A(n7942), .B(n7941), .Y(n7943) );
INVX2TS U734 ( .A(n8457), .Y(n8526) );
BUFX3TS U735 ( .A(n8513), .Y(n8569) );
BUFX3TS U736 ( .A(n8513), .Y(n8441) );
NAND2X1TS U737 ( .A(n649), .B(n8084), .Y(n8085) );
NAND2X1TS U738 ( .A(n7872), .B(n7871), .Y(n7873) );
NAND2X1TS U739 ( .A(n8131), .B(n8130), .Y(n8132) );
NAND2X1TS U740 ( .A(n7890), .B(n8160), .Y(n7891) );
NAND2X1TS U741 ( .A(n7419), .B(n7544), .Y(n7420) );
NAND2X1TS U742 ( .A(n8102), .B(n8101), .Y(n8103) );
NAND2X1TS U743 ( .A(n7940), .B(n7939), .Y(n7941) );
NAND2X1TS U744 ( .A(n7910), .B(n7909), .Y(n7911) );
NAND2X1TS U745 ( .A(n7832), .B(n7831), .Y(n7833) );
NAND2X1TS U746 ( .A(n8202), .B(n8201), .Y(n8203) );
NAND2X1TS U747 ( .A(n8090), .B(n8113), .Y(n8091) );
NAND2X1TS U748 ( .A(n7932), .B(n7931), .Y(n7933) );
NAND2X1TS U749 ( .A(n8124), .B(n8108), .Y(n8109) );
NAND2X1TS U750 ( .A(n8070), .B(n8095), .Y(n8071) );
NAND2X1TS U751 ( .A(n8119), .B(n8118), .Y(n8120) );
NAND2X1TS U752 ( .A(n8047), .B(n8046), .Y(n8048) );
NAND2XLTS U753 ( .A(n8028), .B(n8027), .Y(n8029) );
BUFX3TS U754 ( .A(n728), .Y(n8608) );
NAND2XLTS U755 ( .A(n7920), .B(n7919), .Y(n7921) );
BUFX3TS U756 ( .A(n8839), .Y(n8841) );
AOI21X2TS U757 ( .A0(n7748), .A1(n7696), .B0(n7695), .Y(n7699) );
AOI21X2TS U758 ( .A0(n7748), .A1(n7652), .B0(n7651), .Y(n7654) );
AOI21X2TS U759 ( .A0(n7748), .A1(n7776), .B0(n7775), .Y(n7780) );
AOI21X2TS U760 ( .A0(n710), .A1(n8128), .B0(n8127), .Y(n8133) );
AOI21X2TS U761 ( .A0(n870), .A1(n7524), .B0(n7523), .Y(n7527) );
AOI21X2TS U762 ( .A0(n870), .A1(n7483), .B0(n7482), .Y(n7486) );
AOI21X2TS U763 ( .A0(n7748), .A1(n7763), .B0(n7762), .Y(n7768) );
AOI21X2TS U764 ( .A0(n710), .A1(n8099), .B0(n8098), .Y(n8104) );
AOI21X2TS U765 ( .A0(n710), .A1(n8158), .B0(n7889), .Y(n7892) );
AOI21X2TS U766 ( .A0(n7798), .A1(n7401), .B0(n7400), .Y(n7403) );
AOI21X2TS U767 ( .A0(n7798), .A1(n7725), .B0(n7724), .Y(n7728) );
AOI21X2TS U768 ( .A0(n7748), .A1(n7570), .B0(n7569), .Y(n7573) );
AOI21X2TS U769 ( .A0(n7798), .A1(n7786), .B0(n7785), .Y(n7790) );
AOI21X2TS U770 ( .A0(n7748), .A1(n7344), .B0(n7343), .Y(n7348) );
AOI21X2TS U771 ( .A0(n870), .A1(n7634), .B0(n7633), .Y(n7638) );
AOI21X2TS U772 ( .A0(n8204), .A1(n8201), .B0(n7937), .Y(n7942) );
AOI21X1TS U773 ( .A0(n8020), .A1(n7866), .B0(n7867), .Y(n7864) );
AOI21X1TS U774 ( .A0(n710), .A1(n8089), .B0(n8088), .Y(n8092) );
AOI21X2TS U775 ( .A0(n8204), .A1(n8164), .B0(n8163), .Y(n8169) );
AOI21X1TS U776 ( .A0(n8204), .A1(n7355), .B0(n7354), .Y(n7357) );
AOI21X1TS U777 ( .A0(n8020), .A1(n7882), .B0(n7881), .Y(n7886) );
AOI21X1TS U778 ( .A0(n8020), .A1(n8001), .B0(n8000), .Y(n8004) );
OR2X2TS U779 ( .A(n8192), .B(n8850), .Y(n8446) );
BUFX3TS U780 ( .A(n8924), .Y(n8939) );
INVX2TS U781 ( .A(n8677), .Y(n8742) );
NOR2X1TS U782 ( .A(n8094), .B(n8096), .Y(n8099) );
NOR2X1TS U783 ( .A(n8159), .B(n8161), .Y(n8164) );
NOR2XLTS U784 ( .A(n915), .B(n7374), .Y(n7377) );
NOR2X1TS U785 ( .A(n8123), .B(n7406), .Y(n7409) );
NOR2X1TS U786 ( .A(n7543), .B(n7545), .Y(n7548) );
NOR2X1TS U787 ( .A(n8112), .B(n8115), .Y(n8117) );
NOR2X1TS U788 ( .A(n7794), .B(n7731), .Y(n7327) );
NOR2X1TS U789 ( .A(n7677), .B(n7679), .Y(n7682) );
CLKBUFX2TS U790 ( .A(n8474), .Y(n8404) );
NOR2X1TS U791 ( .A(n8388), .B(n8367), .Y(n8373) );
NOR2X1TS U792 ( .A(n8437), .B(n8420), .Y(n8426) );
INVX2TS U793 ( .A(n7809), .Y(n7724) );
NOR2X1TS U794 ( .A(n8123), .B(n8080), .Y(n8082) );
NOR2X1TS U795 ( .A(n8123), .B(n7353), .Y(n7355) );
OAI21X2TS U796 ( .A0(n7809), .A1(n7716), .B0(n7727), .Y(n7717) );
INVX4TS U797 ( .A(n7847), .Y(n7986) );
OAI21X2TS U798 ( .A0(n8126), .A1(n7363), .B0(n7362), .Y(n7364) );
OAI21X1TS U799 ( .A0(n8097), .A1(n8096), .B0(n8095), .Y(n8098) );
OAI21X1TS U800 ( .A0(n7784), .A1(n7556), .B0(n7787), .Y(n7557) );
OAI21X2TS U801 ( .A0(n8126), .A1(n7353), .B0(n7352), .Y(n7354) );
NOR2X2TS U802 ( .A(n7794), .B(n7799), .Y(n7703) );
OAI21X1TS U803 ( .A0(n8126), .A1(n7406), .B0(n7407), .Y(n7408) );
NAND2X2TS U804 ( .A(n7798), .B(n7806), .Y(n7810) );
AOI21X1TS U805 ( .A0(n7958), .A1(n7957), .B0(n7956), .Y(n7959) );
OAI21X1TS U806 ( .A0(n7375), .A1(n7374), .B0(n7382), .Y(n7376) );
NOR2X2TS U807 ( .A(n7690), .B(n7693), .Y(n7696) );
OAI21X1TS U808 ( .A0(n8126), .A1(n7827), .B0(n7826), .Y(n7828) );
INVX4TS U809 ( .A(n8756), .Y(n725) );
AOI21X1TS U810 ( .A0(n7927), .A1(n7905), .B0(n7904), .Y(n7906) );
INVX2TS U811 ( .A(n8595), .Y(n773) );
OR3X2TS U812 ( .A(n8765), .B(underflow_flag), .C(overflow_flag), .Y(n8839)
);
AND2X2TS U813 ( .A(n8207), .B(n8206), .Y(n8766) );
AOI21X1TS U814 ( .A0(n7927), .A1(n8028), .B0(n7915), .Y(n7916) );
BUFX3TS U815 ( .A(n8390), .Y(n8382) );
BUFX3TS U816 ( .A(n8513), .Y(n8331) );
BUFX3TS U817 ( .A(n8513), .Y(n8381) );
BUFX3TS U818 ( .A(n8390), .Y(n8447) );
BUFX3TS U819 ( .A(n8390), .Y(n8564) );
BUFX3TS U820 ( .A(n8390), .Y(n8505) );
BUFX3TS U821 ( .A(n8504), .Y(n8559) );
BUFX3TS U822 ( .A(n8504), .Y(n8498) );
BUFX3TS U823 ( .A(n8504), .Y(n8565) );
NOR2X1TS U824 ( .A(n7733), .B(n7742), .Y(n7745) );
NAND2X1TS U825 ( .A(n7817), .B(n7819), .Y(n5062) );
NAND2X1TS U826 ( .A(n8074), .B(n8077), .Y(n8080) );
NAND2X1TS U827 ( .A(n7875), .B(n8021), .Y(n7880) );
NAND2X4TS U828 ( .A(n7734), .B(n7310), .Y(n7794) );
NAND2X1TS U829 ( .A(n7578), .B(n7583), .Y(n7619) );
INVX2TS U830 ( .A(n7867), .Y(n8017) );
NAND2X2TS U831 ( .A(n7565), .B(n7481), .Y(n7690) );
INVX2TS U832 ( .A(n8312), .Y(n8358) );
AOI21X2TS U833 ( .A0(n7825), .A1(n7411), .B0(n7361), .Y(n7362) );
NAND2X2TS U834 ( .A(n7565), .B(n7522), .Y(n7758) );
NAND2X2TS U835 ( .A(n7565), .B(n7399), .Y(n7530) );
AOI21X1TS U836 ( .A0(n7825), .A1(n7824), .B0(n7823), .Y(n7826) );
NAND2X2TS U837 ( .A(n7734), .B(n7416), .Y(n7543) );
AOI21X1TS U838 ( .A0(n7878), .A1(n8021), .B0(n7877), .Y(n7879) );
XOR2X1TS U839 ( .A(n8767), .B(n7838), .Y(DP_OP_31J26_122_605_n19) );
INVX2TS U840 ( .A(n7733), .Y(n7416) );
INVX2TS U841 ( .A(n7356), .Y(n8077) );
CLKINVX6TS U842 ( .A(n7406), .Y(n7819) );
NAND2X1TS U843 ( .A(n8517), .B(n8469), .Y(n8483) );
AND2X2TS U844 ( .A(n7711), .B(n7710), .Y(n7712) );
OAI21X2TS U845 ( .A0(n7743), .A1(n7494), .B0(n7493), .Y(n7495) );
NOR2X2TS U846 ( .A(n7733), .B(n7397), .Y(n7399) );
INVX2TS U847 ( .A(n8263), .Y(n8504) );
NOR2X2TS U848 ( .A(n7577), .B(n7580), .Y(n7583) );
NOR2X1TS U849 ( .A(n8413), .B(n8366), .Y(n8378) );
NOR2X1TS U850 ( .A(n8462), .B(n8419), .Y(n8431) );
NAND2X2TS U851 ( .A(n7734), .B(n7710), .Y(n7805) );
OAI21X1TS U852 ( .A0(n7743), .A1(n7397), .B0(n7396), .Y(n7398) );
INVX8TS U853 ( .A(n915), .Y(n7734) );
INVX2TS U854 ( .A(n7817), .Y(n7818) );
CLKINVX2TS U855 ( .A(n7449), .Y(n7431) );
OR2X2TS U856 ( .A(n7743), .B(n7647), .Y(n7648) );
CLKINVX1TS U857 ( .A(n8770), .Y(n8178) );
NOR2X2TS U858 ( .A(n7733), .B(n7714), .Y(n7710) );
AOI21X2TS U859 ( .A0(n7645), .A1(n7476), .B0(n7475), .Y(n7477) );
NAND2X2TS U860 ( .A(n7711), .B(n7646), .Y(n7649) );
NOR2X6TS U861 ( .A(n7733), .B(n7276), .Y(n7310) );
NAND2X2TS U862 ( .A(n7424), .B(n7456), .Y(n7430) );
NAND2X1TS U863 ( .A(n8257), .B(n8263), .Y(n8192) );
NAND3X1TS U864 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[1]), .C(
n8848), .Y(n8770) );
INVX2TS U865 ( .A(FS_Module_state_reg[3]), .Y(n8206) );
NOR2X1TS U866 ( .A(n8462), .B(n8364), .Y(n8407) );
AOI21X1TS U867 ( .A0(n7515), .A1(n7325), .B0(n887), .Y(n7737) );
NOR2X6TS U868 ( .A(n7406), .B(n5265), .Y(n5268) );
NAND2XLTS U869 ( .A(n8190), .B(n8189), .Y(n8191) );
INVX2TS U870 ( .A(n8363), .Y(n8462) );
NAND2X2TS U871 ( .A(n7644), .B(n7641), .Y(n7647) );
NOR2X1TS U872 ( .A(n7799), .B(n7704), .Y(n7514) );
CLKINVX1TS U873 ( .A(n8190), .Y(n8186) );
NOR2X6TS U874 ( .A(n7611), .B(n7613), .Y(n7387) );
NAND2X4TS U875 ( .A(n7817), .B(n5263), .Y(n5265) );
NAND2X4TS U876 ( .A(n5058), .B(n5057), .Y(n7410) );
NAND2X1TS U877 ( .A(n7317), .B(n7316), .Y(n7661) );
NAND2X1TS U878 ( .A(n7319), .B(n7318), .Y(n7759) );
NAND2X1TS U879 ( .A(n7315), .B(n7314), .Y(n7705) );
NAND2X1TS U880 ( .A(n8219), .B(FS_Module_state_reg[3]), .Y(n8190) );
NAND2X2TS U881 ( .A(n5060), .B(n5059), .Y(n7367) );
NAND2X2TS U882 ( .A(n5260), .B(n5259), .Y(n7831) );
NAND2X2TS U883 ( .A(n5042), .B(n5041), .Y(n8101) );
NOR2X4TS U884 ( .A(n7821), .B(n7830), .Y(n5263) );
NAND2X4TS U885 ( .A(n3523), .B(n7926), .Y(n3525) );
BUFX4TS U886 ( .A(n7281), .Y(n7613) );
AOI21X2TS U887 ( .A0(n7209), .A1(n7427), .B0(n7208), .Y(n7210) );
OAI21X2TS U888 ( .A0(n7908), .A1(n7931), .B0(n7909), .Y(n3522) );
CLKINVX6TS U889 ( .A(n7470), .Y(n7808) );
NAND2X6TS U890 ( .A(n8039), .B(n3513), .Y(n8026) );
AOI21X2TS U891 ( .A0(n7510), .A1(n7250), .B0(n7249), .Y(n7251) );
NAND2X4TS U892 ( .A(n3515), .B(n3514), .Y(n8027) );
NAND2X4TS U893 ( .A(n3511), .B(n3510), .Y(n8046) );
CMPR32X2TS U894 ( .A(n7191), .B(n7190), .C(n7189), .CO(n7317), .S(n7314) );
CMPR32X2TS U895 ( .A(n7330), .B(n7329), .C(n7328), .CO(n7335), .S(n7320) );
NOR2X6TS U896 ( .A(n7291), .B(n7290), .Y(n7635) );
NOR2X6TS U897 ( .A(n5159), .B(n5158), .Y(n7821) );
NOR2X6TS U898 ( .A(n5036), .B(n5035), .Y(n8115) );
NOR2X6TS U899 ( .A(n5047), .B(n5048), .Y(n8125) );
NOR2X2TS U900 ( .A(n5025), .B(n5026), .Y(n7936) );
NOR2X4TS U901 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n8219) );
NOR2X4TS U902 ( .A(n5260), .B(n5259), .Y(n7830) );
NAND2X4TS U903 ( .A(n7571), .B(n7778), .Y(n7225) );
NAND2X4TS U904 ( .A(n7261), .B(n7812), .Y(n7474) );
NOR2X4TS U905 ( .A(n8052), .B(n8053), .Y(n8039) );
NAND2X4TS U906 ( .A(n7383), .B(n662), .Y(n7564) );
NAND2X2TS U907 ( .A(n7689), .B(n7698), .Y(n7270) );
OR2X6TS U908 ( .A(n7294), .B(n7295), .Y(n646) );
NAND2X1TS U909 ( .A(n7265), .B(n7264), .Y(n7672) );
NOR2X6TS U910 ( .A(n7230), .B(n7229), .Y(n7545) );
NAND2X2TS U911 ( .A(n7207), .B(n7206), .Y(n7598) );
INVX4TS U912 ( .A(n7374), .Y(n7383) );
INVX4TS U913 ( .A(n7773), .Y(n7571) );
INVX2TS U914 ( .A(n7626), .Y(n7303) );
INVX2TS U915 ( .A(n7559), .Y(n7199) );
INVX2TS U916 ( .A(n7378), .Y(n7216) );
INVX2TS U917 ( .A(n7465), .Y(n7298) );
NAND2X4TS U918 ( .A(n2604), .B(n7983), .Y(n7977) );
NAND2X6TS U919 ( .A(n8001), .B(n836), .Y(n8006) );
INVX4TS U920 ( .A(n7556), .Y(n7788) );
NAND2X4TS U921 ( .A(n7295), .B(n7294), .Y(n7607) );
OR2X2TS U922 ( .A(n2617), .B(n2616), .Y(n8001) );
NOR2X6TS U923 ( .A(n7218), .B(n7219), .Y(n7773) );
OR2X4TS U924 ( .A(n2638), .B(n2637), .Y(n7883) );
NOR2X6TS U925 ( .A(n7205), .B(n7204), .Y(n7593) );
INVX2TS U926 ( .A(n8022), .Y(n7877) );
CLKINVX6TS U927 ( .A(n7466), .Y(n7296) );
NOR2X1TS U928 ( .A(n8254), .B(n8312), .Y(n8306) );
INVX2TS U929 ( .A(n7872), .Y(n2633) );
NOR2X4TS U930 ( .A(n8682), .B(n8732), .Y(n2350) );
OR2X4TS U931 ( .A(n2635), .B(n2636), .Y(n8021) );
INVX2TS U932 ( .A(n8002), .Y(n2620) );
INVX2TS U933 ( .A(n7961), .Y(n2611) );
ADDFHX1TS U934 ( .A(n5273), .B(n5272), .CI(n5271), .CO(n5452), .S(n5362) );
INVX2TS U935 ( .A(n7995), .Y(n2625) );
CMPR32X2TS U936 ( .A(n7099), .B(n7098), .C(n7097), .CO(n7110), .S(n7091) );
OR2X6TS U937 ( .A(n7293), .B(n7292), .Y(n7466) );
CMPR32X2TS U938 ( .A(n7023), .B(n7022), .C(n7021), .CO(n7265), .S(n7262) );
NOR2X4TS U939 ( .A(n2344), .B(n2343), .Y(n8743) );
CLKINVX2TS U940 ( .A(n2630), .Y(n868) );
BUFX3TS U941 ( .A(n8767), .Y(n780) );
NAND2X2TS U942 ( .A(n2638), .B(n2637), .Y(n7884) );
AND2X6TS U943 ( .A(n844), .B(n8667), .Y(n8719) );
MX2X1TS U944 ( .A(Op_MX[52]), .B(exp_oper_result[0]), .S0(n691), .Y(
S_Oper_A_exp[0]) );
NAND2X2TS U945 ( .A(n2346), .B(n2345), .Y(n8733) );
NOR2X4TS U946 ( .A(n2348), .B(n2347), .Y(n8682) );
NAND2X4TS U947 ( .A(n8708), .B(n8714), .Y(n8738) );
ADDFHX2TS U948 ( .A(n5464), .B(n5463), .CI(n5462), .CO(n5547), .S(n5460) );
ADDFHX2TS U949 ( .A(n4866), .B(n4865), .CI(n4864), .CO(n5067), .S(n4957) );
XOR2X2TS U950 ( .A(n8767), .B(n7442), .Y(DP_OP_31J26_122_605_n28) );
CMPR32X2TS U951 ( .A(n6995), .B(n6994), .C(n6993), .CO(n7253), .S(n7247) );
CMPR32X2TS U952 ( .A(n3087), .B(n3086), .C(n3085), .CO(n3484), .S(n3099) );
CMPR32X2TS U953 ( .A(n3820), .B(n3819), .C(n3818), .CO(n3938), .S(n3816) );
CMPR32X2TS U954 ( .A(n7063), .B(n7062), .C(n7061), .CO(n7093), .S(n7088) );
NAND2X1TS U955 ( .A(n2107), .B(n2106), .Y(n8726) );
CLKINVX6TS U956 ( .A(n2619), .Y(n838) );
INVX4TS U957 ( .A(n2618), .Y(n837) );
CMPR32X2TS U958 ( .A(n7132), .B(n7131), .C(n7130), .CO(n7149), .S(n7144) );
BUFX3TS U959 ( .A(FSM_selector_A), .Y(n691) );
NAND2X2TS U960 ( .A(n2103), .B(n2102), .Y(n8667) );
INVX2TS U961 ( .A(n8709), .Y(n2342) );
ADDFHX1TS U962 ( .A(n4700), .B(n4699), .CI(n4698), .CO(n4858), .S(n5012) );
NOR2XLTS U963 ( .A(n8364), .B(n8245), .Y(n8253) );
NOR2X4TS U964 ( .A(n8185), .B(FS_Module_state_reg[1]), .Y(n8767) );
CMPR32X2TS U965 ( .A(n4132), .B(n4131), .C(n4130), .CO(n4137), .S(n4122) );
NOR2X1TS U966 ( .A(n8320), .B(n8854), .Y(n8313) );
NAND2BX2TS U967 ( .AN(n8672), .B(n8668), .Y(n844) );
ADDFX2TS U968 ( .A(n7123), .B(n7122), .CI(n7121), .CO(n7239), .S(n7236) );
NOR2X1TS U969 ( .A(n8252), .B(n8468), .Y(n8363) );
CMPR32X2TS U970 ( .A(n4455), .B(n4454), .C(n4453), .CO(n4855), .S(n4718) );
CMPR32X2TS U971 ( .A(n6601), .B(n6600), .C(n6599), .CO(n6606), .S(n6579) );
CMPR32X2TS U972 ( .A(n3378), .B(n3377), .C(n3376), .CO(n3552), .S(n3438) );
CMPR32X2TS U973 ( .A(n5310), .B(n5309), .C(n5308), .CO(n5399), .S(n5282) );
CMPR32X2TS U974 ( .A(n3423), .B(n3422), .C(n3421), .CO(n3420), .S(n3465) );
CMPR32X2TS U975 ( .A(n2821), .B(n2820), .C(n2819), .CO(n3021), .S(n2902) );
CMPR32X2TS U976 ( .A(n5405), .B(n5404), .C(n5403), .CO(n5483), .S(n5398) );
CMPR32X2TS U977 ( .A(n5138), .B(n5137), .C(n5136), .CO(n5250), .S(n5108) );
CMPR32X2TS U978 ( .A(n5341), .B(n5340), .C(n5339), .CO(n5424), .S(n5280) );
NAND2X1TS U979 ( .A(n1396), .B(n1397), .Y(n655) );
CMPR32X2TS U980 ( .A(n6967), .B(n6966), .C(n6965), .CO(n6998), .S(n6968) );
NAND2X4TS U981 ( .A(n2101), .B(n2100), .Y(n8672) );
OR2X4TS U982 ( .A(n2107), .B(n2106), .Y(n8727) );
NAND2X1TS U983 ( .A(n8251), .B(n8523), .Y(n8468) );
NOR2X6TS U984 ( .A(n8701), .B(n8696), .Y(n2099) );
NAND2X1TS U985 ( .A(n8469), .B(n8248), .Y(n8252) );
OAI21X2TS U986 ( .A0(n8622), .A1(n8624), .B0(n8625), .Y(n2022) );
XOR2X2TS U987 ( .A(n843), .B(n4151), .Y(n4133) );
ADDFHX1TS U988 ( .A(n5359), .B(n5358), .CI(n5357), .CO(n5422), .S(n5336) );
NAND2X1TS U989 ( .A(n8328), .B(n8238), .Y(n8320) );
INVX4TS U990 ( .A(n847), .Y(n8721) );
ADDFHX2TS U991 ( .A(n2519), .B(n2518), .CI(n2517), .CO(n2521), .S(n2571) );
ADDFHX2TS U992 ( .A(n3856), .B(n3855), .CI(n3854), .CO(n4134), .S(n3883) );
ADDFHX2TS U993 ( .A(n3459), .B(n3458), .CI(n3457), .CO(n3464), .S(n3481) );
ADDFHX2TS U994 ( .A(n4757), .B(n4756), .CI(n4755), .CO(n4762), .S(n4972) );
CMPR32X2TS U995 ( .A(n5085), .B(n5084), .C(n5083), .CO(n5184), .S(n5102) );
CMPR32X2TS U996 ( .A(n5553), .B(n5552), .C(n5551), .CO(n5844), .S(n5550) );
CMPR32X2TS U997 ( .A(n4727), .B(n4726), .C(n4725), .CO(n4703), .S(n4753) );
CMPR32X2TS U998 ( .A(n2516), .B(n2515), .C(n2514), .CO(n2519), .S(n2553) );
CMPR32X2TS U999 ( .A(n5353), .B(n5352), .C(n5351), .CO(n5429), .S(n5359) );
CMPR32X2TS U1000 ( .A(n3826), .B(n3825), .C(n3824), .CO(n3940), .S(n3756) );
CMPR32X2TS U1001 ( .A(n2289), .B(n2288), .C(n2287), .CO(n2329), .S(n2337) );
CMPR32X2TS U1002 ( .A(n4359), .B(n4358), .C(n4357), .CO(n4979), .S(n4355) );
CMPR32X2TS U1003 ( .A(n3061), .B(n3060), .C(n3059), .CO(n3440), .S(n3025) );
CMPR32X2TS U1004 ( .A(n6344), .B(n6343), .C(n6342), .CO(n6356), .S(n6451) );
CMPR32X2TS U1005 ( .A(n4512), .B(n4511), .C(n4510), .CO(n4789), .S(n4692) );
NOR2X4TS U1006 ( .A(n2095), .B(n2094), .Y(n8696) );
OAI21X2TS U1007 ( .A0(n4152), .A1(n4153), .B0(n4151), .Y(n842) );
NAND2X2TS U1008 ( .A(n2097), .B(n2096), .Y(n8702) );
NAND2X2TS U1009 ( .A(n2093), .B(n2092), .Y(n8634) );
CMPR32X2TS U1010 ( .A(n5241), .B(n5240), .C(n5239), .CO(n5341), .S(n5165) );
NAND2X4TS U1011 ( .A(n8188), .B(n8847), .Y(n8185) );
NOR2X4TS U1012 ( .A(n2093), .B(n2092), .Y(n8633) );
NAND2X1TS U1013 ( .A(n8250), .B(n8547), .Y(n8523) );
NOR2X1TS U1014 ( .A(n8524), .B(n8249), .Y(n8251) );
NOR2X1TS U1015 ( .A(n8394), .B(n8242), .Y(n8365) );
NOR2X1TS U1016 ( .A(n8443), .B(n8239), .Y(n8418) );
XOR2X2TS U1017 ( .A(n4153), .B(n4152), .Y(n843) );
ADDFHX1TS U1018 ( .A(n4186), .B(n4185), .CI(n4184), .CO(n4282), .S(n4187) );
ADDFHX1TS U1019 ( .A(n5438), .B(n5437), .CI(n5436), .CO(n5515), .S(n5430) );
NOR2X1TS U1020 ( .A(n8494), .B(n8246), .Y(n8469) );
ADDFHX1TS U1021 ( .A(n4238), .B(n4237), .CI(n4236), .CO(n4356), .S(n4233) );
NOR2X1TS U1022 ( .A(n8341), .B(n8237), .Y(n8328) );
CMPR32X2TS U1023 ( .A(n2477), .B(n2476), .C(n2475), .CO(n2472), .S(n2573) );
ADDFHX2TS U1024 ( .A(n5814), .B(n5813), .CI(n5812), .CO(n5900), .S(n5838) );
ADDFHX1TS U1025 ( .A(n5935), .B(n5934), .CI(n5933), .CO(n6002), .S(n6000) );
CMPR32X2TS U1026 ( .A(n5147), .B(n5146), .C(n5145), .CO(n5181), .S(n5099) );
CMPR32X2TS U1027 ( .A(n3742), .B(n3741), .C(n3740), .CO(n3853), .S(n3754) );
ADDFHX2TS U1028 ( .A(n4645), .B(n4644), .CI(n4643), .CO(n4696), .S(n4746) );
ADDFHX2TS U1029 ( .A(n5556), .B(n5555), .CI(n5554), .CO(n5843), .S(n5548) );
ADDFHX2TS U1030 ( .A(n3947), .B(n3946), .CI(n3945), .CO(n4131), .S(n3855) );
ADDFHX2TS U1031 ( .A(n2196), .B(n2195), .CI(n2194), .CO(n2338), .S(n2107) );
CMPR32X2TS U1032 ( .A(n5313), .B(n5312), .C(n5311), .CO(n5405), .S(n5284) );
CMPR32X2TS U1033 ( .A(n3384), .B(n3383), .C(n3382), .CO(n3444), .S(n3439) );
CMPR32X2TS U1034 ( .A(n3396), .B(n3395), .C(n3394), .CO(n3453), .S(n3431) );
CMPR32X2TS U1035 ( .A(n3111), .B(n3110), .C(n3109), .CO(n3624), .S(n3142) );
CMPR32X2TS U1036 ( .A(n5608), .B(n5607), .C(n5606), .CO(n5833), .S(n5618) );
CMPR32X2TS U1037 ( .A(n2954), .B(n2953), .C(n2952), .CO(n2966), .S(n3078) );
CMPR32X2TS U1038 ( .A(n2513), .B(n2512), .C(n2511), .CO(n2530), .S(n2556) );
CMPR32X2TS U1039 ( .A(n4073), .B(n4072), .C(n4071), .CO(n4192), .S(n4046) );
CMPR32X2TS U1040 ( .A(n3372), .B(n3371), .C(n3370), .CO(n3425), .S(n3409) );
CMPR32X2TS U1041 ( .A(n4533), .B(n4532), .C(n4531), .CO(n4509), .S(n4595) );
CMPR32X2TS U1042 ( .A(n3770), .B(n3769), .C(n3768), .CO(n3947), .S(n3799) );
CMPR32X2TS U1043 ( .A(n3249), .B(n3248), .C(n3247), .CO(n3543), .S(n3250) );
CMPR32X2TS U1044 ( .A(n4305), .B(n4304), .C(n4303), .CO(n4736), .S(n4312) );
CMPR32X2TS U1045 ( .A(n4198), .B(n4197), .C(n4196), .CO(n4330), .S(n4195) );
CMPR32X2TS U1046 ( .A(n4035), .B(n4034), .C(n4033), .CO(n4082), .S(n4042) );
CMPR32X2TS U1047 ( .A(n3580), .B(n3579), .C(n3578), .CO(n3713), .S(n3584) );
CMPR32X2TS U1048 ( .A(n4492), .B(n4491), .C(n4490), .CO(n4508), .S(n4599) );
CMPR32X2TS U1049 ( .A(n4517), .B(n4516), .C(n4515), .CO(n4783), .S(n4659) );
CMPR32X2TS U1050 ( .A(n4878), .B(n4877), .C(n4876), .CO(n5137), .S(n4897) );
CMPR32X2TS U1051 ( .A(n4830), .B(n4829), .C(n4828), .CO(n4926), .S(n4825) );
CMPR32X2TS U1052 ( .A(n5125), .B(n5124), .C(n5123), .CO(n5170), .S(n5083) );
CMPR32X2TS U1053 ( .A(n4840), .B(n4839), .C(n4838), .CO(n4898), .S(n4765) );
CMPR32X2TS U1054 ( .A(n6192), .B(n6191), .C(n6190), .CO(n6243), .S(n6197) );
CMPR32X2TS U1055 ( .A(n5082), .B(n5081), .C(n5080), .CO(n5197), .S(n5120) );
CMPR32X2TS U1056 ( .A(n2925), .B(n2924), .C(n2923), .CO(n3058), .S(n2906) );
CMPR32X2TS U1057 ( .A(n3811), .B(n3810), .C(n3809), .CO(n3942), .S(n3751) );
CMPR32X2TS U1058 ( .A(n4241), .B(n4240), .C(n4239), .CO(n4359), .S(n4236) );
NAND2X1TS U1059 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n8547) );
NAND2X1TS U1060 ( .A(Sgf_normalized_result[10]), .B(
Sgf_normalized_result[11]), .Y(n8494) );
CMPR32X2TS U1061 ( .A(n2295), .B(n2294), .C(n2293), .CO(n2561), .S(n2291) );
CMPR32X2TS U1062 ( .A(n4061), .B(n4060), .C(n4059), .CO(n4185), .S(n4106) );
CMPR32X2TS U1063 ( .A(n3670), .B(n3669), .C(n3668), .CO(n3767), .S(n3716) );
NOR2X1TS U1064 ( .A(n8643), .B(n8641), .Y(n1907) );
CMPR32X2TS U1065 ( .A(n5144), .B(n5143), .C(n5142), .CO(n5182), .S(n5121) );
INVX2TS U1066 ( .A(n2102), .Y(n850) );
ADDFX2TS U1067 ( .A(n1273), .B(n1272), .CI(n1271), .CO(n1268), .S(n1537) );
CMPR32X2TS U1068 ( .A(n2712), .B(n2711), .C(n2710), .CO(n2823), .S(n2764) );
ADDFHX2TS U1069 ( .A(n2184), .B(n2183), .CI(n2182), .CO(n2193), .S(n2194) );
ADDFHX1TS U1070 ( .A(n3991), .B(n3990), .CI(n3989), .CO(n4182), .S(n3995) );
ADDFHX1TS U1071 ( .A(n4023), .B(n4022), .CI(n4021), .CO(n4047), .S(n4062) );
ADDFHX1TS U1072 ( .A(n3703), .B(n3702), .CI(n3701), .CO(n3823), .S(n3715) );
CMPR32X2TS U1073 ( .A(n4076), .B(n4075), .C(n4074), .CO(n4191), .S(n3994) );
CMPR32X2TS U1074 ( .A(n4252), .B(n4251), .C(n4250), .CO(n4299), .S(n4237) );
CMPR32X2TS U1075 ( .A(n4089), .B(n4088), .C(n4087), .CO(n4194), .S(n4107) );
ADDFHX1TS U1076 ( .A(n4875), .B(n4874), .CI(n4873), .CO(n5138), .S(n4871) );
ADDFHX1TS U1077 ( .A(n6205), .B(n6204), .CI(n6203), .CO(n6270), .S(n6214) );
ADDFHX1TS U1078 ( .A(n3721), .B(n3720), .CI(n3719), .CO(n3801), .S(n3699) );
ADDFHX1TS U1079 ( .A(n4833), .B(n4832), .CI(n4831), .CO(n4925), .S(n4782) );
ADDFHX1TS U1080 ( .A(n5291), .B(n5290), .CI(n5289), .CO(n5373), .S(n5354) );
CMPR32X2TS U1081 ( .A(n4226), .B(n4225), .C(n4224), .CO(n4362), .S(n4193) );
CMPR32X2TS U1082 ( .A(n3690), .B(n3689), .C(n3688), .CO(n3752), .S(n3714) );
CMPR32X2TS U1083 ( .A(n3617), .B(n3616), .C(n3615), .CO(n3667), .S(n3625) );
ADDFHX1TS U1084 ( .A(n4317), .B(n4316), .CI(n4315), .CO(n4709), .S(n4329) );
CMPR32X2TS U1085 ( .A(n3295), .B(n3294), .C(n3293), .CO(n3568), .S(n3314) );
CMPR32X2TS U1086 ( .A(n4350), .B(n4349), .C(n4348), .CO(n4731), .S(n4297) );
CMPR32X2TS U1087 ( .A(n4053), .B(n4052), .C(n4051), .CO(n4108), .S(n4148) );
CMPR32X2TS U1088 ( .A(n4654), .B(n4653), .C(n4652), .CO(n4596), .S(n4728) );
ADDFX1TS U1089 ( .A(n4467), .B(n4466), .CI(n4465), .CO(n4706), .S(n4732) );
CMPR32X2TS U1090 ( .A(n4464), .B(n4463), .C(n4462), .CO(n4622), .S(n4725) );
ADDFX2TS U1091 ( .A(n3620), .B(n3619), .CI(n3618), .CO(n3666), .S(n3569) );
ADDFX2TS U1092 ( .A(n4904), .B(n4903), .CI(n4902), .CO(n5084), .S(n4929) );
CMPR32X2TS U1093 ( .A(n6241), .B(n6240), .C(n6239), .CO(n6315), .S(n6271) );
CMPR32X2TS U1094 ( .A(n2789), .B(n2788), .C(n2787), .CO(n2847), .S(n2765) );
CMPR32X2TS U1095 ( .A(n1332), .B(n1331), .C(n1330), .CO(n1432), .S(n1338) );
CMPR32X2TS U1096 ( .A(n1380), .B(n1379), .C(n1378), .CO(n1399), .S(n1335) );
CMPR32X2TS U1097 ( .A(n5761), .B(n5760), .C(n5759), .CO(n5831), .S(n5834) );
CMPR32X2TS U1098 ( .A(n2053), .B(n2052), .C(n2051), .CO(n2025), .S(n2054) );
CMPR32X2TS U1099 ( .A(n5650), .B(n5649), .C(n5648), .CO(n5697), .S(n5819) );
CMPR32X2TS U1100 ( .A(n980), .B(n979), .C(n978), .CO(n1128), .S(n1207) );
CMPR32X2TS U1101 ( .A(n2757), .B(n2756), .C(n2755), .CO(n2821), .S(n2773) );
CMPR32X2TS U1102 ( .A(n2468), .B(n2467), .C(n2466), .CO(n2470), .S(n2511) );
CMPR32X2TS U1103 ( .A(n3363), .B(n3362), .C(n3361), .CO(n3345), .S(n3386) );
CMPR32X2TS U1104 ( .A(n6490), .B(n6489), .C(n6488), .CO(n6493), .S(n6542) );
CMPR32X2TS U1105 ( .A(n2911), .B(n2910), .C(n2909), .CO(n2974), .S(n2936) );
CMPR32X2TS U1106 ( .A(n2492), .B(n2491), .C(n2490), .CO(n2542), .S(n2540) );
CMPR32X2TS U1107 ( .A(n2255), .B(n2254), .C(n2253), .CO(n2315), .S(n2284) );
CMPR32X2TS U1108 ( .A(n2252), .B(n2251), .C(n2250), .CO(n2316), .S(n2322) );
CMPR32X2TS U1109 ( .A(n2965), .B(n2964), .C(n2963), .CO(n3370), .S(n2971) );
CMPR32X2TS U1110 ( .A(n5941), .B(n5940), .C(n5939), .CO(n6040), .S(n5967) );
CMPR32X2TS U1111 ( .A(n6432), .B(n6431), .C(n6430), .CO(n6445), .S(n6517) );
CMPR32X2TS U1112 ( .A(n3154), .B(n3153), .C(n3152), .CO(n3397), .S(n3404) );
CMPR32X2TS U1113 ( .A(n3366), .B(n3365), .C(n3364), .CO(n3330), .S(n3385) );
CMPR32X2TS U1114 ( .A(n5418), .B(n5417), .C(n5416), .CO(n5485), .S(n5372) );
NAND2X1TS U1115 ( .A(n1939), .B(n1938), .Y(n8599) );
CMPR32X2TS U1116 ( .A(n3000), .B(n2999), .C(n2998), .CO(n3029), .S(n2935) );
CMPR32X2TS U1117 ( .A(n3357), .B(n3356), .C(n3355), .CO(n3388), .S(n3396) );
CMPR32X2TS U1118 ( .A(n6705), .B(n6704), .C(n6703), .CO(n7083), .S(n7067) );
CMPR32X2TS U1119 ( .A(n2304), .B(n2303), .C(n2302), .CO(n2535), .S(n2292) );
CMPR32X2TS U1120 ( .A(n2423), .B(n2422), .C(n2421), .CO(n2433), .S(n2497) );
CMPR32X2TS U1121 ( .A(n6060), .B(n6059), .C(n6058), .CO(n6590), .S(n6039) );
NAND2X1TS U1122 ( .A(n1905), .B(n1904), .Y(n8644) );
NAND2X1TS U1123 ( .A(n1937), .B(n1936), .Y(n8614) );
CMPR32X2TS U1124 ( .A(n3369), .B(n3368), .C(n3367), .CO(n3426), .S(n3406) );
CMPR32X2TS U1125 ( .A(n6682), .B(n6681), .C(n6680), .CO(n6762), .S(n6754) );
NOR2BX1TS U1126 ( .AN(n3605), .B(n7332), .Y(n3646) );
NAND2X2TS U1127 ( .A(n1903), .B(n1902), .Y(n8640) );
OAI22X1TS U1128 ( .A0(n6071), .A1(n3253), .B0(n4687), .B1(n3613), .Y(n3620)
);
OAI22X1TS U1129 ( .A0(n4243), .A1(n3606), .B0(n4892), .B1(n3640), .Y(n3645)
);
OAI22X2TS U1130 ( .A0(n5191), .A1(n742), .B0(n5190), .B1(n5189), .Y(n5346)
);
OAI22X2TS U1131 ( .A0(n5522), .A1(n4024), .B0(n3987), .B1(n4177), .Y(n4174)
);
OAI22X1TS U1132 ( .A0(n4371), .A1(n3592), .B0(n4370), .B1(n3682), .Y(n3720)
);
OAI22X1TS U1133 ( .A0(n3259), .A1(n3258), .B0(n3840), .B1(n3257), .Y(n3295)
);
OAI22X1TS U1134 ( .A0(n4880), .A1(n4228), .B0(n804), .B1(n4288), .Y(n4307)
);
OAI22X1TS U1135 ( .A0(n4202), .A1(n3217), .B0(n5711), .B1(n3275), .Y(n3268)
);
XOR2X2TS U1136 ( .A(n858), .B(n1855), .Y(n2024) );
OAI22X1TS U1137 ( .A0(n6886), .A1(n4777), .B0(n6021), .B1(n4940), .Y(n4934)
);
ADDFX2TS U1138 ( .A(n2742), .B(n2741), .CI(n2740), .CO(n2771), .S(n2746) );
ADDFHX1TS U1139 ( .A(n2679), .B(n2678), .CI(n2677), .CO(n2766), .S(n2758) );
CMPR32X2TS U1140 ( .A(n1459), .B(n1458), .C(n1457), .CO(n2763), .S(n1398) );
OAI22X1TS U1141 ( .A0(n4443), .A1(n2870), .B0(n2921), .B1(n2922), .Y(n2924)
);
ADDHX1TS U1142 ( .A(n3542), .B(n3541), .CO(n3695), .S(n3545) );
OAI22X1TS U1143 ( .A0(n5724), .A1(n3613), .B0(n4687), .B1(n3671), .Y(n3708)
);
CMPR32X2TS U1144 ( .A(n5914), .B(n5913), .C(n5912), .CO(n5969), .S(n5916) );
ADDFHX1TS U1145 ( .A(n3243), .B(n3242), .CI(n3241), .CO(n3252), .S(n3184) );
XNOR2X1TS U1146 ( .A(n5503), .B(n5892), .Y(n5111) );
ADDFHX1TS U1147 ( .A(n2863), .B(n2862), .CI(n2861), .CO(n2908), .S(n2873) );
ADDFHX1TS U1148 ( .A(n6018), .B(n6017), .CI(n6016), .CO(n6594), .S(n6035) );
CMPR32X2TS U1149 ( .A(n3360), .B(n3359), .C(n3358), .CO(n3387), .S(n3383) );
CMPR32X2TS U1150 ( .A(n5445), .B(n5444), .C(n5443), .CO(n5466), .S(n5401) );
CMPR32X2TS U1151 ( .A(n5951), .B(n5950), .C(n5949), .CO(n6049), .S(n5937) );
ADDFHX1TS U1152 ( .A(n6728), .B(n6727), .CI(n6726), .CO(n6738), .S(n6758) );
XNOR2X1TS U1153 ( .A(n681), .B(n6887), .Y(n6934) );
CMPR32X2TS U1154 ( .A(n5380), .B(n5379), .C(n5378), .CO(n5469), .S(n5400) );
CMPR32X2TS U1155 ( .A(n2854), .B(n2853), .C(n2852), .CO(n2953), .S(n2858) );
CMPR32X2TS U1156 ( .A(n2178), .B(n2177), .C(n2176), .CO(n2186), .S(n2129) );
CMPR32X2TS U1157 ( .A(n1089), .B(n1088), .C(n1087), .CO(n1334), .S(n1162) );
CMPR32X2TS U1158 ( .A(n1449), .B(n1448), .C(n1447), .CO(n2742), .S(n1460) );
CMPR32X2TS U1159 ( .A(n5530), .B(n5529), .C(n5528), .CO(n5610), .S(n5467) );
CMPR32X2TS U1160 ( .A(n1354), .B(n1353), .C(n1352), .CO(n1445), .S(n1328) );
CMPR32X2TS U1161 ( .A(n1198), .B(n1197), .C(n1196), .CO(n1225), .S(n1284) );
CMPR32X2TS U1162 ( .A(n2730), .B(n2729), .C(n2728), .CO(n2859), .S(n2737) );
CMPR32X2TS U1163 ( .A(n1218), .B(n1217), .C(n1216), .CO(n1227), .S(n1287) );
CMPR32X2TS U1164 ( .A(n2141), .B(n2140), .C(n2139), .CO(n2231), .S(n2156) );
BUFX3TS U1165 ( .A(n3832), .Y(n6179) );
CMPR32X2TS U1166 ( .A(n5579), .B(n5578), .C(n5577), .CO(n5654), .S(n5614) );
CMPR32X2TS U1167 ( .A(n1898), .B(n1897), .C(n1896), .CO(n1904), .S(n1903) );
BUFX6TS U1168 ( .A(n6850), .Y(n7185) );
ADDFX2TS U1169 ( .A(n2217), .B(n2216), .CI(n2215), .CO(n2320), .S(n2207) );
BUFX4TS U1170 ( .A(n6644), .Y(n6772) );
OAI22X1TS U1171 ( .A0(n6795), .A1(n3119), .B0(n5388), .B1(n3174), .Y(n3323)
);
OAI22X1TS U1172 ( .A0(n3540), .A1(n3132), .B0(n4002), .B1(n3261), .Y(n3123)
);
BUFX16TS U1173 ( .A(n688), .Y(n7167) );
OAI22X1TS U1174 ( .A0(n4556), .A1(n3117), .B0(n3116), .B1(n3115), .Y(n3365)
);
OAI22X1TS U1175 ( .A0(n7013), .A1(n6123), .B0(n720), .B1(n6199), .Y(n6189)
);
ADDFX2TS U1176 ( .A(n1067), .B(n1066), .CI(n1065), .CO(n1163), .S(n1018) );
OAI22X1TS U1177 ( .A0(n5305), .A1(n5989), .B0(n826), .B1(n712), .Y(n6051) );
OAI22X1TS U1178 ( .A0(n6719), .A1(n6136), .B0(n738), .B1(n6180), .Y(n6164)
);
OAI22X1TS U1179 ( .A0(n688), .A1(n3202), .B0(n3570), .B1(n7173), .Y(n3542)
);
XNOR2X1TS U1180 ( .A(n5874), .B(Op_MY[34]), .Y(n5204) );
OAI22X1TS U1181 ( .A0(n6731), .A1(n6222), .B0(n6663), .B1(n6744), .Y(n6655)
);
OAI22X1TS U1182 ( .A0(n812), .A1(n3862), .B0(n5887), .B1(n4054), .Y(n3966)
);
CMPR32X2TS U1183 ( .A(n1552), .B(n1551), .C(n1550), .CO(n1480), .S(n1597) );
CMPR32X2TS U1184 ( .A(n1646), .B(n1645), .C(n1644), .CO(n1649), .S(n2372) );
CMPR32X2TS U1185 ( .A(n2686), .B(n2685), .C(n2684), .CO(n2788), .S(n2740) );
XNOR2X2TS U1186 ( .A(n695), .B(n820), .Y(n4177) );
CMPR32X2TS U1187 ( .A(n1574), .B(n1573), .C(n1572), .CO(n1599), .S(n1647) );
OAI22X1TS U1188 ( .A0(n5664), .A1(n7752), .B0(n3643), .B1(n7332), .Y(n3743)
);
BUFX8TS U1189 ( .A(n3933), .Y(n5191) );
XNOR2X1TS U1190 ( .A(n3838), .B(n6378), .Y(n3935) );
XNOR2X1TS U1191 ( .A(n3108), .B(n5348), .Y(n3257) );
XNOR2X1TS U1192 ( .A(n749), .B(n4418), .Y(n4335) );
XNOR2X1TS U1193 ( .A(n6054), .B(n4500), .Y(n4604) );
XNOR2X1TS U1194 ( .A(n8809), .B(n1624), .Y(n3606) );
ADDFHX2TS U1195 ( .A(n1673), .B(n1672), .CI(n1671), .CO(n1676), .S(n2404) );
XNOR2X2TS U1196 ( .A(n705), .B(n4176), .Y(n4293) );
XNOR2X1TS U1197 ( .A(n4879), .B(n5986), .Y(n4084) );
XNOR2X1TS U1198 ( .A(n6690), .B(n4406), .Y(n3573) );
XNOR2X1TS U1199 ( .A(n5784), .B(n4418), .Y(n4437) );
XNOR2X1TS U1200 ( .A(n3102), .B(n5440), .Y(n3564) );
XNOR2X1TS U1201 ( .A(n6054), .B(n5413), .Y(n3562) );
XNOR2X1TS U1202 ( .A(n8214), .B(n2378), .Y(n4083) );
XNOR2X1TS U1203 ( .A(n695), .B(n3830), .Y(n3930) );
XNOR2X1TS U1204 ( .A(n796), .B(n3971), .Y(n3275) );
XNOR2X1TS U1205 ( .A(n742), .B(n5526), .Y(n3673) );
XNOR2X1TS U1206 ( .A(n3594), .B(n4480), .Y(n4501) );
CMPR32X2TS U1207 ( .A(n5473), .B(n5472), .C(n5471), .CO(n5617), .S(n5468) );
CMPR32X2TS U1208 ( .A(n2792), .B(n2791), .C(n2790), .CO(n2874), .S(n2752) );
XNOR2X1TS U1209 ( .A(n5990), .B(n8236), .Y(n3571) );
XNOR2X1TS U1210 ( .A(n5990), .B(n3971), .Y(n3729) );
XNOR2X1TS U1211 ( .A(n3611), .B(n5783), .Y(n3686) );
XNOR2X1TS U1212 ( .A(n8217), .B(n4372), .Y(n3806) );
XNOR2X1TS U1213 ( .A(n5874), .B(n6335), .Y(n4842) );
XNOR2X1TS U1214 ( .A(n6660), .B(n643), .Y(n4893) );
XNOR2X1TS U1215 ( .A(n6660), .B(n6056), .Y(n4798) );
XNOR2X1TS U1216 ( .A(n6168), .B(n5792), .Y(n4114) );
XNOR2X1TS U1217 ( .A(n3611), .B(n6131), .Y(n4219) );
XNOR2X1TS U1218 ( .A(n4000), .B(n6131), .Y(n4001) );
XNOR2X2TS U1219 ( .A(n708), .B(n3590), .Y(n3704) );
ADDFX1TS U1220 ( .A(n5593), .B(n5592), .CI(n5591), .CO(n5761), .S(n5558) );
XNOR2X1TS U1221 ( .A(n6166), .B(n8229), .Y(n3836) );
XNOR2X1TS U1222 ( .A(n6383), .B(n6056), .Y(n4503) );
XNOR2X1TS U1223 ( .A(n3786), .B(n5129), .Y(n3687) );
XNOR2X1TS U1224 ( .A(n708), .B(n4841), .Y(n4889) );
XNOR2X1TS U1225 ( .A(n755), .B(n5299), .Y(n4433) );
XNOR2X2TS U1226 ( .A(n636), .B(n4480), .Y(n4011) );
CMPR32X2TS U1227 ( .A(n5596), .B(n5595), .C(n5594), .CO(n5760), .S(n5615) );
CMPR32X2TS U1228 ( .A(n2147), .B(n2146), .C(n2145), .CO(n2208), .S(n2157) );
XNOR2X1TS U1229 ( .A(n3103), .B(n4427), .Y(n4105) );
XNOR2X1TS U1230 ( .A(n5979), .B(n8811), .Y(n5205) );
XNOR2X1TS U1231 ( .A(n8810), .B(n5324), .Y(n4534) );
CMPR32X2TS U1232 ( .A(n5638), .B(n5637), .C(n5636), .CO(n5650), .S(n5757) );
BUFX8TS U1233 ( .A(n6149), .Y(n6225) );
CMPR32X2TS U1234 ( .A(n5494), .B(n5493), .C(n5492), .CO(n5613), .S(n5512) );
CMPR32X2TS U1235 ( .A(n1360), .B(n1359), .C(n1358), .CO(n1415), .S(n1327) );
XNOR2X1TS U1236 ( .A(n3920), .B(n4427), .Y(n3639) );
CMPR32X2TS U1237 ( .A(n2202), .B(n2201), .C(n2200), .CO(n2285), .S(n2223) );
CMPR32X2TS U1238 ( .A(n1901), .B(n1900), .C(n1899), .CO(n1902), .S(n1882) );
XNOR2X1TS U1239 ( .A(n5095), .B(n2878), .Y(n3794) );
XNOR2X1TS U1240 ( .A(n823), .B(n820), .Y(n3561) );
XNOR2X1TS U1241 ( .A(n4415), .B(n4427), .Y(n4336) );
CMPR32X2TS U1242 ( .A(n1977), .B(n1976), .C(n1975), .CO(n2012), .S(n1978) );
CMPR32X2TS U1243 ( .A(n1531), .B(n1530), .C(n1529), .CO(n1548), .S(n1573) );
INVX6TS U1244 ( .A(n6154), .Y(n4883) );
CMPR32X2TS U1245 ( .A(n1076), .B(n1075), .C(n1074), .CO(n1087), .S(n1062) );
CMPR32X2TS U1246 ( .A(n1053), .B(n1052), .C(n1051), .CO(n1152), .S(n1039) );
CMPR32X2TS U1247 ( .A(n1184), .B(n1183), .C(n1182), .CO(n995), .S(n1251) );
CMPR32X2TS U1248 ( .A(n1070), .B(n1069), .C(n1068), .CO(n1089), .S(n979) );
CMPR32X2TS U1249 ( .A(n1733), .B(n1732), .C(n1731), .CO(n2180), .S(n1724) );
BUFX6TS U1250 ( .A(n6177), .Y(n6741) );
INVX6TS U1251 ( .A(n1363), .Y(n5095) );
BUFX3TS U1252 ( .A(n3933), .Y(n5328) );
INVX6TS U1253 ( .A(n6793), .Y(n4500) );
BUFX3TS U1254 ( .A(n6177), .Y(n6827) );
BUFX6TS U1255 ( .A(n699), .Y(n714) );
BUFX4TS U1256 ( .A(n4112), .Y(n6794) );
OAI21X2TS U1257 ( .A0(n1856), .A1(n1855), .B0(n1854), .Y(n857) );
BUFX6TS U1258 ( .A(n6149), .Y(n3577) );
BUFX3TS U1259 ( .A(n3100), .Y(n4556) );
BUFX8TS U1260 ( .A(n6453), .Y(n5410) );
BUFX6TS U1261 ( .A(n6649), .Y(n6443) );
BUFX4TS U1262 ( .A(n4112), .Y(n787) );
BUFX6TS U1263 ( .A(n6149), .Y(n6860) );
NOR2X1TS U1264 ( .A(n1866), .B(n1865), .Y(n8575) );
NAND2X1TS U1265 ( .A(n1866), .B(n1865), .Y(n8576) );
BUFX8TS U1266 ( .A(n786), .Y(n4002) );
NOR2BX1TS U1267 ( .AN(n3605), .B(n2979), .Y(n2723) );
BUFX12TS U1268 ( .A(n3180), .Y(n6019) );
BUFX4TS U1269 ( .A(n6099), .Y(n6309) );
BUFX4TS U1270 ( .A(n6101), .Y(n6988) );
BUFX4TS U1271 ( .A(n6067), .Y(n6891) );
BUFX6TS U1272 ( .A(n3069), .Y(n4371) );
CMPR32X2TS U1273 ( .A(n1658), .B(n1657), .C(n1656), .CO(n1643), .S(n2369) );
INVX4TS U1274 ( .A(n733), .Y(n734) );
BUFX6TS U1275 ( .A(n6646), .Y(n6850) );
BUFX6TS U1276 ( .A(n6666), .Y(n4202) );
BUFX4TS U1277 ( .A(n932), .Y(n4247) );
INVX4TS U1278 ( .A(n6461), .Y(n788) );
BUFX4TS U1279 ( .A(n4581), .Y(n5135) );
INVX4TS U1280 ( .A(n729), .Y(n732) );
BUFX4TS U1281 ( .A(n637), .Y(n6476) );
INVX6TS U1282 ( .A(n729), .Y(n731) );
OAI22X1TS U1283 ( .A0(n4115), .A1(n5479), .B0(n5715), .B1(n5576), .Y(n5595)
);
INVX4TS U1284 ( .A(n6643), .Y(n4480) );
BUFX4TS U1285 ( .A(n4099), .Y(n4846) );
OAI22X1TS U1286 ( .A0(n6055), .A1(n1121), .B0(n826), .B1(n1391), .Y(n1353)
);
OAI22X1TS U1287 ( .A0(n4055), .A1(n5531), .B0(n6677), .B1(n5574), .Y(n5562)
);
OAI22X1TS U1288 ( .A0(n5978), .A1(n5565), .B0(n5564), .B1(n5670), .Y(n5717)
);
BUFX4TS U1289 ( .A(n6666), .Y(n7029) );
OAI22X1TS U1290 ( .A0(n5978), .A1(n5709), .B0(n6387), .B1(n5811), .Y(n5781)
);
BUFX3TS U1291 ( .A(n6715), .Y(n683) );
BUFX6TS U1292 ( .A(n6177), .Y(n6156) );
XNOR2X1TS U1293 ( .A(n8811), .B(Op_MY[33]), .Y(n3261) );
BUFX3TS U1294 ( .A(n628), .Y(n6945) );
OAI22X1TS U1295 ( .A0(n3130), .A1(n2705), .B0(n2704), .B1(n2778), .Y(n2714)
);
OAI22X1TS U1296 ( .A0(n5391), .A1(n2669), .B0(n2668), .B1(n2674), .Y(n2730)
);
BUFX4TS U1297 ( .A(n6099), .Y(n6955) );
XNOR2X1TS U1298 ( .A(n698), .B(Op_MY[32]), .Y(n6124) );
OAI22X1TS U1299 ( .A0(n6104), .A1(n6152), .B0(n6105), .B1(n6984), .Y(n6122)
);
OAI22X1TS U1300 ( .A0(n4436), .A1(n2112), .B0(n758), .B1(n2152), .Y(n2164)
);
XNOR2X1TS U1301 ( .A(n6842), .B(Op_MY[32]), .Y(n6053) );
XNOR2X1TS U1302 ( .A(n4681), .B(Op_MY[34]), .Y(n2864) );
OAI22X1TS U1303 ( .A0(n3211), .A1(n3161), .B0(n3210), .B1(n906), .Y(n3198)
);
ADDFHX1TS U1304 ( .A(n954), .B(n953), .CI(n952), .CO(n996), .S(n1204) );
XNOR2X1TS U1305 ( .A(n764), .B(n5708), .Y(n3219) );
OAI22X1TS U1306 ( .A0(n5978), .A1(n5670), .B0(n6387), .B1(n5709), .Y(n5737)
);
ADDFHX1TS U1307 ( .A(n2050), .B(n2049), .CI(n2048), .CO(n2058), .S(n2075) );
ADDFHX1TS U1308 ( .A(n5641), .B(n5640), .CI(n5639), .CO(n5649), .S(n5727) );
AOI21X2TS U1309 ( .A0(n894), .A1(n8582), .B0(n1861), .Y(n8578) );
BUFX8TS U1310 ( .A(n5206), .Y(n3540) );
CMPR32X2TS U1311 ( .A(n1046), .B(n1045), .C(n1044), .CO(n1063), .S(n994) );
XNOR2X1TS U1312 ( .A(n749), .B(n2878), .Y(n2794) );
XNOR2X1TS U1313 ( .A(n6660), .B(n4843), .Y(n3274) );
XNOR2X1TS U1314 ( .A(n6327), .B(n5207), .Y(n3745) );
XNOR2X2TS U1315 ( .A(n8810), .B(n762), .Y(n4670) );
ADDFHX1TS U1316 ( .A(n1522), .B(n1521), .CI(n1520), .CO(n1484), .S(n1639) );
XNOR2X1TS U1317 ( .A(n6383), .B(n5090), .Y(n3253) );
XNOR2X1TS U1318 ( .A(n2258), .B(n696), .Y(n2279) );
CMPR32X2TS U1319 ( .A(n1061), .B(n1060), .C(n1059), .CO(n1150), .S(n1035) );
XNOR2X1TS U1320 ( .A(n4419), .B(n3877), .Y(n3997) );
XNOR2X1TS U1321 ( .A(n3920), .B(n753), .Y(n2880) );
XNOR2X1TS U1322 ( .A(n3611), .B(n5986), .Y(n3897) );
XNOR2X1TS U1323 ( .A(n8214), .B(n6376), .Y(n6262) );
XNOR2X1TS U1324 ( .A(n4419), .B(n696), .Y(n2879) );
XNOR2X1TS U1325 ( .A(n5784), .B(n627), .Y(n2719) );
XNOR2X1TS U1326 ( .A(n6404), .B(n5662), .Y(n5395) );
ADDFHX1TS U1327 ( .A(n2047), .B(n2046), .CI(n2045), .CO(n2076), .S(n2066) );
BUFX8TS U1328 ( .A(n6482), .Y(n6930) );
CMPR32X2TS U1329 ( .A(n1652), .B(n1651), .C(n1650), .CO(n1646), .S(n2371) );
XNOR2X1TS U1330 ( .A(n4000), .B(n6371), .Y(n3894) );
XNOR2X1TS U1331 ( .A(n3611), .B(n5203), .Y(n3003) );
XNOR2X1TS U1332 ( .A(n705), .B(n5299), .Y(n5411) );
XNOR2X1TS U1333 ( .A(n818), .B(n6131), .Y(n5942) );
XNOR2X1TS U1334 ( .A(n8809), .B(n6951), .Y(n6178) );
XNOR2X1TS U1335 ( .A(n6069), .B(n3590), .Y(n3112) );
XNOR2X1TS U1336 ( .A(n5631), .B(n3971), .Y(n3156) );
XNOR2X1TS U1337 ( .A(n5784), .B(n6371), .Y(n6417) );
XNOR2X1TS U1338 ( .A(n6662), .B(n5602), .Y(n4244) );
CMPR32X2TS U1339 ( .A(n1714), .B(n1713), .C(n1712), .CO(n1723), .S(n1776) );
XNOR2X1TS U1340 ( .A(n5979), .B(n706), .Y(n6065) );
XNOR2X1TS U1341 ( .A(n2929), .B(n5707), .Y(n2885) );
XNOR2X2TS U1342 ( .A(n706), .B(n3147), .Y(n3179) );
XNOR2X2TS U1343 ( .A(n5631), .B(n3833), .Y(n2978) );
CMPR32X2TS U1344 ( .A(n1507), .B(n1506), .C(n1505), .CO(n1566), .S(n1642) );
XOR2X1TS U1345 ( .A(n8217), .B(n645), .Y(n3217) );
XNOR2X1TS U1346 ( .A(n3102), .B(n4420), .Y(n2776) );
XNOR2X1TS U1347 ( .A(n799), .B(n3159), .Y(n2451) );
INVX6TS U1348 ( .A(n5665), .Y(n3920) );
INVX6TS U1349 ( .A(n7178), .Y(n6363) );
BUFX6TS U1350 ( .A(n6177), .Y(n5791) );
BUFX6TS U1351 ( .A(n4407), .Y(n4835) );
INVX6TS U1352 ( .A(n7178), .Y(n7133) );
BUFX6TS U1353 ( .A(n6646), .Y(n6953) );
INVX6TS U1354 ( .A(n5525), .Y(n5207) );
INVX6TS U1355 ( .A(n5988), .Y(n815) );
INVX6TS U1356 ( .A(n737), .Y(n738) );
BUFX6TS U1357 ( .A(n6649), .Y(n6820) );
INVX6TS U1358 ( .A(n5710), .Y(n8217) );
INVX6TS U1359 ( .A(n7160), .Y(n7034) );
INVX6TS U1360 ( .A(n6227), .Y(n3929) );
INVX6TS U1361 ( .A(n6427), .Y(n4415) );
BUFX3TS U1362 ( .A(n4407), .Y(n5796) );
BUFX6TS U1363 ( .A(n6071), .Y(n5724) );
INVX4TS U1364 ( .A(n7331), .Y(n6166) );
BUFX6TS U1365 ( .A(n6138), .Y(n5585) );
INVX8TS U1366 ( .A(n4776), .Y(n4406) );
INVX3TS U1367 ( .A(n663), .Y(n711) );
BUFX4TS U1368 ( .A(n3200), .Y(n6746) );
INVX6TS U1369 ( .A(n7158), .Y(n7142) );
INVX8TS U1370 ( .A(n7158), .Y(n6404) );
BUFX8TS U1371 ( .A(n2979), .Y(n5414) );
BUFX8TS U1372 ( .A(n2979), .Y(n5743) );
INVX4TS U1373 ( .A(n7183), .Y(n6329) );
BUFX8TS U1374 ( .A(n6646), .Y(n5664) );
INVX8TS U1375 ( .A(n7165), .Y(n6378) );
BUFX4TS U1376 ( .A(n5447), .Y(n6387) );
INVX6TS U1377 ( .A(n6985), .Y(n5299) );
BUFX8TS U1378 ( .A(n3879), .Y(n699) );
BUFX6TS U1379 ( .A(n6033), .Y(n5388) );
INVX4TS U1380 ( .A(n1363), .Y(n6143) );
INVX6TS U1381 ( .A(n769), .Y(n770) );
BUFX6TS U1382 ( .A(n4677), .Y(n5522) );
INVX4TS U1383 ( .A(n4258), .Y(n8803) );
INVX6TS U1384 ( .A(n6985), .Y(n6887) );
BUFX8TS U1385 ( .A(n628), .Y(n792) );
INVX6TS U1386 ( .A(n4939), .Y(n4553) );
BUFX4TS U1387 ( .A(n4337), .Y(n5575) );
BUFX8TS U1388 ( .A(n4919), .Y(n5889) );
BUFX8TS U1389 ( .A(n3879), .Y(n4540) );
INVX8TS U1390 ( .A(n719), .Y(n720) );
BUFX6TS U1391 ( .A(n634), .Y(n827) );
BUFX8TS U1392 ( .A(n6716), .Y(n724) );
BUFX4TS U1393 ( .A(n3832), .Y(n6332) );
BUFX12TS U1394 ( .A(n6177), .Y(n6795) );
INVX2TS U1395 ( .A(n650), .Y(n4805) );
BUFX6TS U1396 ( .A(n6101), .Y(n4055) );
BUFX6TS U1397 ( .A(n802), .Y(n3537) );
INVX4TS U1398 ( .A(n733), .Y(n735) );
BUFX6TS U1399 ( .A(n4581), .Y(n5891) );
BUFX4TS U1400 ( .A(n4581), .Y(n4217) );
BUFX4TS U1401 ( .A(n6644), .Y(n7174) );
OAI22X1TS U1402 ( .A0(n6127), .A1(n668), .B0(n5688), .B1(n5860), .Y(n5911)
);
BUFX3TS U1403 ( .A(n4668), .Y(n5887) );
BUFX4TS U1404 ( .A(n955), .Y(n3840) );
BUFX6TS U1405 ( .A(n4407), .Y(n5677) );
BUFX6TS U1406 ( .A(n5706), .Y(n6419) );
INVX12TS U1407 ( .A(n4938), .Y(n6829) );
BUFX4TS U1408 ( .A(n631), .Y(n5981) );
OAI22X1TS U1409 ( .A0(n6125), .A1(n5603), .B0(n7166), .B1(n5627), .Y(n5640)
);
BUFX8TS U1410 ( .A(n6149), .Y(n5978) );
BUFX3TS U1411 ( .A(n928), .Y(n5480) );
BUFX4TS U1412 ( .A(n6651), .Y(n5715) );
BUFX4TS U1413 ( .A(n637), .Y(n5711) );
BUFX6TS U1414 ( .A(n5206), .Y(n5391) );
OAI22X1TS U1415 ( .A0(n2039), .A1(n1607), .B0(n1912), .B1(n1501), .Y(n1656)
);
NOR2BX1TS U1416 ( .AN(n3605), .B(n6365), .Y(n1667) );
BUFX8TS U1417 ( .A(n6644), .Y(n688) );
OAI22X1TS U1418 ( .A0(n6301), .A1(n5527), .B0(n6300), .B1(n5583), .Y(n5598)
);
INVX2TS U1419 ( .A(n729), .Y(n730) );
BUFX4TS U1420 ( .A(n2890), .Y(n5305) );
INVX6TS U1421 ( .A(n4938), .Y(n6984) );
BUFX4TS U1422 ( .A(n5622), .Y(n6459) );
BUFX8TS U1423 ( .A(n3933), .Y(n3259) );
BUFX4TS U1424 ( .A(n6154), .Y(n7752) );
OAI22X1TS U1425 ( .A0(n814), .A1(n1202), .B0(n1241), .B1(n6300), .Y(n1309)
);
BUFX4TS U1426 ( .A(n6666), .Y(n6478) );
BUFX3TS U1427 ( .A(n6154), .Y(n6948) );
BUFX6TS U1428 ( .A(n4085), .Y(n3130) );
BUFX8TS U1429 ( .A(n5622), .Y(n4808) );
XNOR2X1TS U1430 ( .A(n8810), .B(n643), .Y(n5574) );
XNOR2X1TS U1431 ( .A(n5893), .B(n5392), .Y(n5532) );
BUFX4TS U1432 ( .A(n5381), .Y(n785) );
XNOR2X1TS U1433 ( .A(n694), .B(n5660), .Y(n5685) );
XNOR2X1TS U1434 ( .A(n8804), .B(n5689), .Y(n5568) );
XNOR2X1TS U1435 ( .A(n712), .B(n2887), .Y(n2670) );
XNOR2X1TS U1436 ( .A(n5633), .B(n6056), .Y(n5634) );
XNOR2X1TS U1437 ( .A(n698), .B(n5892), .Y(n5774) );
XNOR2X1TS U1438 ( .A(n6064), .B(n5890), .Y(n5786) );
XNOR2X1TS U1439 ( .A(n3724), .B(n8221), .Y(n2786) );
XNOR2X1TS U1440 ( .A(n768), .B(n2259), .Y(n2136) );
XNOR2X1TS U1441 ( .A(n768), .B(n2376), .Y(n2224) );
XNOR2X1TS U1442 ( .A(n8210), .B(n1453), .Y(n1391) );
XNOR2X1TS U1443 ( .A(n8808), .B(n5783), .Y(n5586) );
XNOR2X2TS U1444 ( .A(n3203), .B(n6371), .Y(n3161) );
XNOR2X1TS U1445 ( .A(n6064), .B(n677), .Y(n5476) );
XNOR2X1TS U1446 ( .A(n795), .B(n6400), .Y(n5883) );
BUFX8TS U1447 ( .A(n6149), .Y(n6067) );
ADDHX1TS U1448 ( .A(n1870), .B(n1869), .CO(n1871), .S(n1866) );
XNOR2X1TS U1449 ( .A(n3895), .B(Op_MY[18]), .Y(n1200) );
CMPR32X2TS U1450 ( .A(n1706), .B(n1705), .C(n1704), .CO(n1722), .S(n1761) );
XNOR2X1TS U1451 ( .A(n6660), .B(n3971), .Y(n2661) );
INVX6TS U1452 ( .A(n911), .Y(n6667) );
CMPR32X2TS U1453 ( .A(n1781), .B(n1780), .C(n1779), .CO(n1787), .S(n1811) );
INVX6TS U1454 ( .A(n911), .Y(n5633) );
INVX6TS U1455 ( .A(n6201), .Y(n5342) );
INVX6TS U1456 ( .A(n7051), .Y(n6030) );
INVX6TS U1457 ( .A(n1363), .Y(n5331) );
INVX6TS U1458 ( .A(n6825), .Y(n4797) );
INVX6TS U1459 ( .A(n5688), .Y(n5589) );
BUFX6TS U1460 ( .A(n6071), .Y(n3127) );
BUFX6TS U1461 ( .A(n4407), .Y(n2400) );
BUFX3TS U1462 ( .A(n640), .Y(n2921) );
INVX6TS U1463 ( .A(n7027), .Y(n5986) );
BUFX6TS U1464 ( .A(n4581), .Y(n2149) );
BUFX6TS U1465 ( .A(n3165), .Y(n3228) );
BUFX6TS U1466 ( .A(n4677), .Y(n1663) );
INVX6TS U1467 ( .A(n5601), .Y(n5324) );
BUFX6TS U1468 ( .A(n6071), .Y(n6731) );
INVX6TS U1469 ( .A(n6201), .Y(n5623) );
INVX6TS U1470 ( .A(n629), .Y(n823) );
BUFX6TS U1471 ( .A(n631), .Y(n5228) );
BUFX6TS U1472 ( .A(n5944), .Y(n5625) );
BUFX6TS U1473 ( .A(n6071), .Y(n6487) );
INVX6TS U1474 ( .A(n7139), .Y(n5660) );
BUFX4TS U1475 ( .A(n639), .Y(n4685) );
INVX8TS U1476 ( .A(n7158), .Y(n5990) );
BUFX8TS U1477 ( .A(n6455), .Y(n817) );
BUFX8TS U1478 ( .A(n6033), .Y(n4892) );
BUFX8TS U1479 ( .A(n6099), .Y(n3808) );
BUFX8TS U1480 ( .A(n3933), .Y(n4204) );
INVX4TS U1481 ( .A(n659), .Y(n706) );
CMPR32X2TS U1482 ( .A(n1846), .B(n1845), .C(n1844), .CO(n1842), .S(n2059) );
BUFX4TS U1483 ( .A(n639), .Y(n4295) );
INVX8TS U1484 ( .A(n7011), .Y(n8810) );
BUFX8TS U1485 ( .A(n4099), .Y(n4682) );
INVX8TS U1486 ( .A(n6880), .Y(n4905) );
INVX8TS U1487 ( .A(n6947), .Y(n5708) );
INVX6TS U1488 ( .A(n621), .Y(n6337) );
BUFX8TS U1489 ( .A(n3879), .Y(n4115) );
BUFX8TS U1490 ( .A(n3069), .Y(n3227) );
BUFX6TS U1491 ( .A(n5706), .Y(n2720) );
BUFX6TS U1492 ( .A(n6071), .Y(n781) );
INVX4TS U1493 ( .A(n5533), .Y(n3691) );
BUFX4TS U1494 ( .A(n5381), .Y(n7166) );
BUFX6TS U1495 ( .A(n5706), .Y(n5350) );
INVX4TS U1496 ( .A(n722), .Y(n723) );
INVX6TS U1497 ( .A(n7011), .Y(n6842) );
BUFX4TS U1498 ( .A(n639), .Y(n5720) );
BUFX4TS U1499 ( .A(n2890), .Y(n4606) );
INVX4TS U1500 ( .A(n6954), .Y(n5503) );
INVX4TS U1501 ( .A(n623), .Y(n626) );
INVX6TS U1502 ( .A(n6415), .Y(n5953) );
INVX4TS U1503 ( .A(n7160), .Y(n5684) );
BUFX6TS U1504 ( .A(n6644), .Y(n6125) );
INVX6TS U1505 ( .A(n629), .Y(n824) );
INVX6TS U1506 ( .A(n6416), .Y(n5892) );
INVX8TS U1507 ( .A(n5955), .Y(n8804) );
INVX6TS U1508 ( .A(n6153), .Y(n6056) );
BUFX6TS U1509 ( .A(n4337), .Y(n5667) );
INVX6TS U1510 ( .A(n7015), .Y(n5873) );
BUFX4TS U1511 ( .A(n3596), .Y(n3211) );
INVX6TS U1512 ( .A(n6825), .Y(n6660) );
BUFX6TS U1513 ( .A(n628), .Y(n794) );
INVX4TS U1514 ( .A(n707), .Y(n709) );
INVX4TS U1515 ( .A(n7015), .Y(n5409) );
BUFX6TS U1516 ( .A(n2890), .Y(n761) );
BUFX6TS U1517 ( .A(n4099), .Y(n3782) );
BUFX6TS U1518 ( .A(n3100), .Y(n2783) );
INVX3TS U1519 ( .A(n3832), .Y(n737) );
BUFX12TS U1520 ( .A(n4407), .Y(n4012) );
INVX4TS U1521 ( .A(n6643), .Y(n6652) );
BUFX16TS U1522 ( .A(n6099), .Y(n6482) );
INVX2TS U1523 ( .A(n928), .Y(n6461) );
BUFX4TS U1524 ( .A(n932), .Y(n4434) );
BUFX6TS U1525 ( .A(n634), .Y(n828) );
BUFX3TS U1526 ( .A(n930), .Y(n5390) );
NAND2X1TS U1527 ( .A(n8586), .B(n8585), .Y(n8587) );
INVX4TS U1528 ( .A(n637), .Y(n729) );
BUFX6TS U1529 ( .A(n4337), .Y(n4436) );
INVX4TS U1530 ( .A(n6126), .Y(n6400) );
BUFX4TS U1531 ( .A(n2890), .Y(n2457) );
BUFX3TS U1532 ( .A(n5206), .Y(n5535) );
INVX4TS U1533 ( .A(n5710), .Y(n796) );
INVX4TS U1534 ( .A(n4618), .Y(n717) );
BUFX6TS U1535 ( .A(n802), .Y(n3899) );
BUFX4TS U1536 ( .A(n5944), .Y(n6381) );
BUFX3TS U1537 ( .A(n641), .Y(n2270) );
BUFX6TS U1538 ( .A(n939), .Y(n6453) );
BUFX4TS U1539 ( .A(n6651), .Y(n4499) );
BUFX4TS U1540 ( .A(n3180), .Y(n7141) );
BUFX6TS U1541 ( .A(n2984), .Y(n6138) );
BUFX8TS U1542 ( .A(n3879), .Y(n6716) );
BUFX6TS U1543 ( .A(n5292), .Y(n4322) );
BUFX6TS U1544 ( .A(n5622), .Y(n1518) );
BUFX12TS U1545 ( .A(n6177), .Y(n4243) );
BUFX8TS U1546 ( .A(n5944), .Y(n6463) );
BUFX4TS U1547 ( .A(n634), .Y(n3863) );
BUFX8TS U1548 ( .A(n782), .Y(n3114) );
BUFX4TS U1549 ( .A(n4337), .Y(n809) );
BUFX6TS U1550 ( .A(n4668), .Y(n6986) );
INVX2TS U1551 ( .A(n639), .Y(n733) );
XNOR2X1TS U1552 ( .A(n821), .B(n5602), .Y(n5627) );
XNOR2X1TS U1553 ( .A(n8223), .B(n3992), .Y(n944) );
XNOR2X1TS U1554 ( .A(n765), .B(n4882), .Y(n1734) );
XNOR2X1TS U1555 ( .A(n5784), .B(n4208), .Y(n981) );
XNOR2X1TS U1556 ( .A(n5784), .B(n2132), .Y(n1451) );
XNOR2X1TS U1557 ( .A(n4419), .B(n5526), .Y(n5583) );
XNOR2X1TS U1558 ( .A(n766), .B(n8233), .Y(n1496) );
XNOR2X1TS U1559 ( .A(n694), .B(n4405), .Y(n1191) );
XNOR2X1TS U1560 ( .A(n749), .B(n2132), .Y(n1124) );
XNOR2X1TS U1561 ( .A(n765), .B(n5745), .Y(n1668) );
XNOR2X1TS U1562 ( .A(n3895), .B(n3065), .Y(n1054) );
XNOR2X1TS U1563 ( .A(n2797), .B(n5348), .Y(n991) );
XNOR2X1TS U1564 ( .A(n8794), .B(n5413), .Y(n1664) );
XNOR2X1TS U1565 ( .A(n8229), .B(n5440), .Y(n1094) );
CMPR32X2TS U1566 ( .A(n1818), .B(n1817), .C(n1816), .CO(n1834), .S(n2028) );
BUFX8TS U1567 ( .A(n930), .Y(n786) );
XNOR2X1TS U1568 ( .A(n8208), .B(n4841), .Y(n1369) );
XNOR2X1TS U1569 ( .A(n5567), .B(n2262), .Y(n1512) );
XNOR2X2TS U1570 ( .A(n694), .B(n2259), .Y(n1662) );
XNOR2X1TS U1571 ( .A(n822), .B(n2887), .Y(n1093) );
XNOR2X1TS U1572 ( .A(n3895), .B(n2887), .Y(n1176) );
XNOR2X1TS U1573 ( .A(n1944), .B(n8233), .Y(n1617) );
XNOR2X2TS U1574 ( .A(n8221), .B(n8236), .Y(n2917) );
XNOR2X1TS U1575 ( .A(n694), .B(n5604), .Y(n5661) );
XNOR2X2TS U1576 ( .A(n694), .B(n2376), .Y(n1608) );
XNOR2X1TS U1577 ( .A(n1839), .B(n752), .Y(n1607) );
INVX6TS U1578 ( .A(n6299), .Y(n8813) );
INVX6TS U1579 ( .A(n6841), .Y(n5526) );
INVX6TS U1580 ( .A(n6825), .Y(n638) );
INVX6TS U1581 ( .A(n707), .Y(n708) );
INVX3TS U1582 ( .A(n6744), .Y(n4813) );
INVX6TS U1583 ( .A(n5326), .Y(n3102) );
INVX6TS U1584 ( .A(n6105), .Y(n790) );
BUFX6TS U1585 ( .A(n3069), .Y(n1708) );
INVX6TS U1586 ( .A(n6108), .Y(n818) );
INVX6TS U1587 ( .A(n5092), .Y(n8213) );
INVX8TS U1588 ( .A(n659), .Y(n694) );
INVX6TS U1589 ( .A(n6201), .Y(n6364) );
INVX6TS U1590 ( .A(n6299), .Y(n5874) );
INVX6TS U1591 ( .A(n4294), .Y(n3971) );
INVX6TS U1592 ( .A(n6830), .Y(n5440) );
INVX2TS U1593 ( .A(n5525), .Y(n1491) );
INVX6TS U1594 ( .A(Op_MY[47]), .Y(n7160) );
INVX8TS U1595 ( .A(n659), .Y(n705) );
INVX4TS U1596 ( .A(n5955), .Y(n3138) );
INVX6TS U1597 ( .A(Op_MY[51]), .Y(n7331) );
INVX6TS U1598 ( .A(Op_MY[40]), .Y(n6917) );
INVX6TS U1599 ( .A(n5972), .Y(n3065) );
INVX4TS U1600 ( .A(n6714), .Y(n779) );
INVX4TS U1601 ( .A(n6714), .Y(n4497) );
INVX6TS U1602 ( .A(n621), .Y(n4888) );
BUFX8TS U1603 ( .A(n4608), .Y(n3231) );
INVX4TS U1604 ( .A(n665), .Y(n677) );
INVX8TS U1605 ( .A(n754), .Y(n756) );
INVX8TS U1606 ( .A(n5972), .Y(n5602) );
BUFX4TS U1607 ( .A(n5675), .Y(n3071) );
INVX4TS U1608 ( .A(n664), .Y(n3149) );
INVX4TS U1609 ( .A(n629), .Y(n822) );
INVX4TS U1610 ( .A(n6714), .Y(n6168) );
INVX4TS U1611 ( .A(n6714), .Y(n8805) );
INVX8TS U1612 ( .A(n5861), .Y(n5662) );
INVX8TS U1613 ( .A(n3988), .Y(n3833) );
INVX4TS U1614 ( .A(n6029), .Y(n3147) );
INVX12TS U1615 ( .A(n8215), .Y(n748) );
INVX4TS U1616 ( .A(n658), .Y(n4841) );
NAND2X6TS U1617 ( .A(n2665), .B(n2785), .Y(n6099) );
INVX4TS U1618 ( .A(n5688), .Y(n2887) );
INVX3TS U1619 ( .A(n957), .Y(n2383) );
INVX6TS U1620 ( .A(n4258), .Y(n3726) );
INVX3TS U1621 ( .A(n4939), .Y(n2388) );
INVX6TS U1622 ( .A(n5861), .Y(n3590) );
BUFX8TS U1623 ( .A(n2884), .Y(n2162) );
INVX8TS U1624 ( .A(n4424), .Y(n6414) );
BUFX8TS U1625 ( .A(n4259), .Y(n1912) );
INVX6TS U1626 ( .A(n6237), .Y(n4504) );
BUFX4TS U1627 ( .A(n4345), .Y(n5447) );
INVX8TS U1628 ( .A(n6153), .Y(n4090) );
INVX4TS U1629 ( .A(n5150), .Y(n627) );
BUFX6TS U1630 ( .A(n2884), .Y(n3164) );
BUFX3TS U1631 ( .A(n641), .Y(n783) );
CLKINVX6TS U1632 ( .A(Op_MY[49]), .Y(n7178) );
BUFX6TS U1633 ( .A(n4677), .Y(n687) );
INVX4TS U1634 ( .A(n4776), .Y(n2262) );
BUFX8TS U1635 ( .A(n6154), .Y(n6104) );
BUFX4TS U1636 ( .A(n3100), .Y(n2444) );
BUFX6TS U1637 ( .A(n4099), .Y(n2450) );
INVX6TS U1638 ( .A(n4426), .Y(n3992) );
INVX4TS U1639 ( .A(n7051), .Y(n5604) );
INVX6TS U1640 ( .A(n4175), .Y(n8236) );
INVX4TS U1641 ( .A(n6311), .Y(n3986) );
INVX6TS U1642 ( .A(n5092), .Y(n3786) );
INVX6TS U1643 ( .A(n6108), .Y(n8808) );
INVX6TS U1644 ( .A(n629), .Y(n825) );
INVX4TS U1645 ( .A(n6415), .Y(n3223) );
INVX6TS U1646 ( .A(n1180), .Y(n8210) );
INVX6TS U1647 ( .A(n6311), .Y(n6335) );
INVX4TS U1648 ( .A(n805), .Y(n808) );
INVX6TS U1649 ( .A(n5688), .Y(n3105) );
INVX4TS U1650 ( .A(n5533), .Y(n4916) );
INVX6TS U1651 ( .A(n6108), .Y(n5489) );
INVX2TS U1652 ( .A(n4416), .Y(n3074) );
BUFX6TS U1653 ( .A(n5789), .Y(n6033) );
BUFX6TS U1654 ( .A(n4337), .Y(n1710) );
BUFX16TS U1655 ( .A(n4677), .Y(n6455) );
INVX4TS U1656 ( .A(n6416), .Y(n4671) );
INVX4TS U1657 ( .A(n6108), .Y(n8224) );
INVX6TS U1658 ( .A(n873), .Y(n782) );
BUFX6TS U1659 ( .A(n5944), .Y(n6202) );
BUFX12TS U1660 ( .A(n4407), .Y(n1727) );
INVX6TS U1661 ( .A(Op_MY[43]), .Y(n7015) );
BUFX8TS U1662 ( .A(n924), .Y(n6651) );
INVX4TS U1663 ( .A(n6744), .Y(n6383) );
INVX4TS U1664 ( .A(n6744), .Y(n791) );
INVX4TS U1665 ( .A(n4618), .Y(n718) );
INVX6TS U1666 ( .A(n6108), .Y(n819) );
INVX4TS U1667 ( .A(n4258), .Y(n2929) );
INVX6TS U1668 ( .A(n4441), .Y(n801) );
BUFX4TS U1669 ( .A(n3100), .Y(n3575) );
CLKINVX6TS U1670 ( .A(Op_MY[42]), .Y(n6985) );
CLKINVX6TS U1671 ( .A(Op_MY[46]), .Y(n7139) );
CLKINVX6TS U1672 ( .A(Op_MY[48]), .Y(n7165) );
INVX4TS U1673 ( .A(n932), .Y(n757) );
BUFX4TS U1674 ( .A(n4337), .Y(n3793) );
BUFX12TS U1675 ( .A(n4205), .Y(n7158) );
INVX4TS U1676 ( .A(n5093), .Y(n804) );
INVX4TS U1677 ( .A(n5533), .Y(n3895) );
INVX4TS U1678 ( .A(n805), .Y(n807) );
BUFX8TS U1679 ( .A(n4613), .Y(n3104) );
XNOR2X1TS U1680 ( .A(n765), .B(n3774), .Y(n1616) );
XNOR2X1TS U1681 ( .A(n765), .B(n746), .Y(n1689) );
XNOR2X1TS U1682 ( .A(n686), .B(n1965), .Y(n1952) );
XNOR2X2TS U1683 ( .A(n686), .B(n2241), .Y(n1989) );
BUFX8TS U1684 ( .A(n640), .Y(n4370) );
BUFX6TS U1685 ( .A(n4085), .Y(n2454) );
BUFX8TS U1686 ( .A(n4668), .Y(n7012) );
XNOR2X1TS U1687 ( .A(n3203), .B(n4418), .Y(n1606) );
INVX6TS U1688 ( .A(n629), .Y(n636) );
INVX6TS U1689 ( .A(n5092), .Y(n4412) );
INVX6TS U1690 ( .A(n4425), .Y(n750) );
INVX6TS U1691 ( .A(n1168), .Y(n4607) );
INVX6TS U1692 ( .A(n5533), .Y(n2386) );
INVX6TS U1693 ( .A(n665), .Y(n678) );
AND2X6TS U1694 ( .A(n874), .B(n2984), .Y(n873) );
INVX6TS U1695 ( .A(n629), .Y(n768) );
INVX2TS U1696 ( .A(n910), .Y(n8590) );
INVX6TS U1697 ( .A(Op_MY[30]), .Y(n6237) );
INVX2TS U1698 ( .A(n910), .Y(n1988) );
BUFX6TS U1699 ( .A(n924), .Y(n6715) );
INVX8TS U1700 ( .A(n6227), .Y(n4420) );
INVX6TS U1701 ( .A(n951), .Y(n805) );
INVX4TS U1702 ( .A(n957), .Y(n4218) );
INVX8TS U1703 ( .A(n4071), .Y(n2797) );
INVX4TS U1704 ( .A(n3988), .Y(n2247) );
INVX4TS U1705 ( .A(n666), .Y(n741) );
INVX3TS U1706 ( .A(n5206), .Y(n4618) );
INVX3TS U1707 ( .A(n4258), .Y(n2006) );
INVX4TS U1708 ( .A(n657), .Y(n4427) );
BUFX8TS U1709 ( .A(n3230), .Y(n766) );
CLKINVX6TS U1710 ( .A(Op_MY[26]), .Y(n6152) );
INVX8TS U1711 ( .A(Op_MY[25]), .Y(n6153) );
INVX8TS U1712 ( .A(Op_MY[24]), .Y(n6415) );
INVX6TS U1713 ( .A(n642), .Y(n743) );
CLKINVX6TS U1714 ( .A(Op_MY[27]), .Y(n6105) );
INVX4TS U1715 ( .A(n4175), .Y(n2259) );
BUFX8TS U1716 ( .A(n3230), .Y(n765) );
INVX8TS U1717 ( .A(Op_MY[37]), .Y(n6830) );
INVX4TS U1718 ( .A(n1201), .Y(n3290) );
INVX6TS U1719 ( .A(n769), .Y(n771) );
CLKINVX6TS U1720 ( .A(Op_MY[38]), .Y(n6841) );
BUFX4TS U1721 ( .A(n955), .Y(n2414) );
INVX4TS U1722 ( .A(n4555), .Y(n4000) );
INVX4TS U1723 ( .A(n957), .Y(n3611) );
BUFX4TS U1724 ( .A(n3100), .Y(n2033) );
BUFX6TS U1725 ( .A(n5206), .Y(n1791) );
CLKINVX6TS U1726 ( .A(Op_MY[12]), .Y(n5192) );
INVX12TS U1727 ( .A(n1363), .Y(n6686) );
BUFX12TS U1728 ( .A(n4099), .Y(n4613) );
BUFX3TS U1729 ( .A(n955), .Y(n2868) );
BUFX8TS U1730 ( .A(n802), .Y(n2452) );
INVX4TS U1731 ( .A(n5626), .Y(n2702) );
INVX4TS U1732 ( .A(n4258), .Y(n8212) );
INVX6TS U1733 ( .A(Op_MY[19]), .Y(n5688) );
BUFX3TS U1734 ( .A(n3596), .Y(n2005) );
INVX6TS U1735 ( .A(Op_MY[36]), .Y(n6793) );
BUFX16TS U1736 ( .A(n3230), .Y(n764) );
BUFX4TS U1737 ( .A(n3596), .Y(n2663) );
BUFX6TS U1738 ( .A(n641), .Y(n4608) );
BUFX4TS U1739 ( .A(n1027), .Y(n4259) );
BUFX6TS U1740 ( .A(n2984), .Y(n5292) );
BUFX12TS U1741 ( .A(n3933), .Y(n2281) );
INVX4TS U1742 ( .A(n4294), .Y(n2376) );
CLKINVX6TS U1743 ( .A(Op_MY[39]), .Y(n6880) );
INVX4TS U1744 ( .A(n8223), .Y(n707) );
BUFX16TS U1745 ( .A(n3861), .Y(n4424) );
BUFX6TS U1746 ( .A(n4879), .Y(n798) );
BUFX12TS U1747 ( .A(n1180), .Y(n6427) );
BUFX3TS U1748 ( .A(n640), .Y(n1991) );
BUFX6TS U1749 ( .A(n955), .Y(n5190) );
BUFX12TS U1750 ( .A(n3861), .Y(n6154) );
CLKINVX6TS U1751 ( .A(n8226), .Y(n754) );
XNOR2X1TS U1752 ( .A(n2258), .B(n2866), .Y(n1694) );
BUFX12TS U1753 ( .A(n6201), .Y(n8215) );
BUFX12TS U1754 ( .A(n3200), .Y(n5381) );
BUFX8TS U1755 ( .A(n5326), .Y(n5189) );
INVX6TS U1756 ( .A(n4258), .Y(n1839) );
INVX6TS U1757 ( .A(n4426), .Y(n2866) );
INVX6TS U1758 ( .A(n664), .Y(n1944) );
INVX6TS U1759 ( .A(n3988), .Y(n1984) );
INVX6TS U1760 ( .A(n5093), .Y(n802) );
INVX8TS U1761 ( .A(n5626), .Y(n3207) );
INVX6TS U1762 ( .A(n664), .Y(n751) );
INVX8TS U1763 ( .A(Op_MY[35]), .Y(n6643) );
BUFX8TS U1764 ( .A(n934), .Y(n5675) );
INVX4TS U1765 ( .A(n4416), .Y(n1943) );
CLKINVX6TS U1766 ( .A(Op_MY[29]), .Y(n6227) );
INVX6TS U1767 ( .A(n5525), .Y(n3044) );
INVX8TS U1768 ( .A(Op_MY[28]), .Y(n6126) );
INVX4TS U1769 ( .A(n4441), .Y(n8211) );
INVX6TS U1770 ( .A(n4071), .Y(n3203) );
BUFX8TS U1771 ( .A(n919), .Y(n639) );
INVX6TS U1772 ( .A(n4514), .Y(n8814) );
BUFX3TS U1773 ( .A(n3596), .Y(n1838) );
INVX6TS U1774 ( .A(n6954), .Y(n6690) );
INVX4TS U1775 ( .A(n3969), .Y(n2296) );
INVX4TS U1776 ( .A(n5533), .Y(n4850) );
BUFX4TS U1777 ( .A(n4879), .Y(n800) );
INVX8TS U1778 ( .A(n4071), .Y(n784) );
BUFX3TS U1779 ( .A(n955), .Y(n5327) );
BUFX12TS U1780 ( .A(n4085), .Y(n4880) );
INVX6TS U1781 ( .A(Op_MX[47]), .Y(n4205) );
CLKINVX6TS U1782 ( .A(Op_MY[22]), .Y(n6029) );
INVX6TS U1783 ( .A(n4071), .Y(n8229) );
CLKINVX6TS U1784 ( .A(Op_MY[6]), .Y(n4425) );
BUFX6TS U1785 ( .A(n4879), .Y(n799) );
BUFX6TS U1786 ( .A(n3933), .Y(n2416) );
INVX12TS U1787 ( .A(Op_MX[39]), .Y(n1363) );
INVX3TS U1788 ( .A(n5665), .Y(n8226) );
INVX6TS U1789 ( .A(n839), .Y(n928) );
XOR2X1TS U1790 ( .A(Op_MX[2]), .B(Op_MX[3]), .Y(n972) );
INVX6TS U1791 ( .A(Op_MY[8]), .Y(n4513) );
INVX8TS U1792 ( .A(Op_MX[3]), .Y(n4258) );
INVX4TS U1793 ( .A(n910), .Y(n3067) );
INVX8TS U1794 ( .A(Op_MX[35]), .Y(n6744) );
INVX8TS U1795 ( .A(Op_MY[5]), .Y(n4426) );
INVX6TS U1796 ( .A(n4776), .Y(n2132) );
CLKINVX6TS U1797 ( .A(Op_MY[2]), .Y(n3988) );
INVX8TS U1798 ( .A(Op_MY[10]), .Y(n4939) );
CLKINVX6TS U1799 ( .A(Op_MY[3]), .Y(n4175) );
INVX8TS U1800 ( .A(Op_MY[11]), .Y(n5150) );
INVX8TS U1801 ( .A(n4071), .Y(n8794) );
INVX8TS U1802 ( .A(Op_MY[16]), .Y(n5601) );
INVX8TS U1803 ( .A(Op_MY[1]), .Y(n3969) );
INVX12TS U1804 ( .A(Op_MX[37]), .Y(n6825) );
INVX3TS U1805 ( .A(n959), .Y(n5093) );
INVX12TS U1806 ( .A(n6370), .Y(n5880) );
BUFX16TS U1807 ( .A(n942), .Y(n951) );
INVX6TS U1808 ( .A(Op_MY[14]), .Y(n5439) );
CLKINVX6TS U1809 ( .A(Op_MY[17]), .Y(n5626) );
CLKINVX6TS U1810 ( .A(Op_MY[0]), .Y(n1201) );
INVX4TS U1811 ( .A(n666), .Y(n742) );
BUFX16TS U1812 ( .A(n1027), .Y(n4030) );
INVX6TS U1813 ( .A(n4207), .Y(n7134) );
CLKXOR2X2TS U1814 ( .A(Op_MX[8]), .B(n4404), .Y(n941) );
INVX12TS U1815 ( .A(Op_MX[5]), .Y(n4441) );
INVX12TS U1816 ( .A(Op_MX[23]), .Y(n1180) );
CLKINVX12TS U1817 ( .A(Op_MX[31]), .Y(n6299) );
BUFX8TS U1818 ( .A(n926), .Y(n955) );
INVX8TS U1819 ( .A(n1303), .Y(n5890) );
CLKINVX6TS U1820 ( .A(Op_MX[0]), .Y(n2159) );
CLKINVX6TS U1821 ( .A(Op_MY[13]), .Y(n5347) );
INVX8TS U1822 ( .A(Op_MX[25]), .Y(n6370) );
INVX4TS U1823 ( .A(n8208), .Y(n684) );
BUFX12TS U1824 ( .A(n3861), .Y(n4207) );
INVX12TS U1825 ( .A(Op_MX[51]), .Y(n3861) );
INVX6TS U1826 ( .A(n1168), .Y(n8208) );
INVX12TS U1827 ( .A(n5326), .Y(n3108) );
INVX8TS U1828 ( .A(n675), .Y(n957) );
INVX6TS U1829 ( .A(n4555), .Y(n3230) );
INVX6TS U1830 ( .A(n3969), .Y(n3724) );
XNOR2X1TS U1831 ( .A(n8810), .B(n747), .Y(n4054) );
XNOR2X1TS U1832 ( .A(n755), .B(n4805), .Y(n4077) );
XNOR2X1TS U1833 ( .A(n6329), .B(n801), .Y(n4092) );
XNOR2X1TS U1834 ( .A(n5633), .B(n1624), .Y(n4473) );
XNOR2X1TS U1835 ( .A(n756), .B(n5129), .Y(n4338) );
XNOR2X1TS U1836 ( .A(n8810), .B(n5207), .Y(n4535) );
INVX6TS U1837 ( .A(n7011), .Y(n5631) );
XNOR2X1TS U1838 ( .A(n6166), .B(n8212), .Y(n4031) );
XNOR2X1TS U1839 ( .A(n4412), .B(n5873), .Y(n4056) );
XNOR2X1TS U1840 ( .A(n678), .B(n4500), .Y(n3921) );
XNOR2X1TS U1841 ( .A(n4850), .B(n4805), .Y(n3896) );
XNOR2X2TS U1842 ( .A(n709), .B(n3774), .Y(n3878) );
XNOR2X1TS U1843 ( .A(n6383), .B(n5324), .Y(n3671) );
XNOR2X1TS U1844 ( .A(n3724), .B(n7055), .Y(n3834) );
AOI2BB2X2TS U1845 ( .B0(n3049), .B1(n3048), .A0N(n3145), .A1N(n637), .Y(
n3050) );
XNOR2X1TS U1846 ( .A(n3691), .B(n3985), .Y(n3032) );
XNOR2X1TS U1847 ( .A(n2797), .B(n5873), .Y(n2928) );
XNOR2X1TS U1848 ( .A(n6168), .B(n627), .Y(n2915) );
XNOR2X1TS U1849 ( .A(n3691), .B(n790), .Y(n2674) );
INVX6TS U1850 ( .A(n6126), .Y(n4418) );
XNOR2X1TS U1851 ( .A(n8208), .B(Op_MY[34]), .Y(n2655) );
XNOR2X1TS U1852 ( .A(n3102), .B(n4418), .Y(n2680) );
XNOR2X1TS U1853 ( .A(n686), .B(n4418), .Y(n974) );
INVX8TS U1854 ( .A(n4416), .Y(n4372) );
XNOR2X1TS U1855 ( .A(n766), .B(n753), .Y(n1212) );
INVX6TS U1856 ( .A(n6108), .Y(n6069) );
XNOR2X1TS U1857 ( .A(n791), .B(n4882), .Y(n3288) );
XNOR2X1TS U1858 ( .A(n749), .B(n2378), .Y(n1000) );
XNOR2X1TS U1859 ( .A(n677), .B(n3223), .Y(n2659) );
XNOR2X1TS U1860 ( .A(n8213), .B(n4420), .Y(n1410) );
XNOR2X1TS U1861 ( .A(n3895), .B(n3147), .Y(n1083) );
INVX2TS U1862 ( .A(n805), .Y(n806) );
XNOR2X1TS U1863 ( .A(n784), .B(n4504), .Y(n1498) );
INVX6TS U1864 ( .A(n5972), .Y(n5745) );
OR2X2TS U1865 ( .A(n4103), .B(n4102), .Y(n4212) );
OAI22X1TS U1866 ( .A0(n4057), .A1(n4056), .B0(n803), .B1(n4084), .Y(n4088)
);
OAI22X1TS U1867 ( .A0(n704), .A1(n4025), .B0(n5130), .B1(n4024), .Y(n4073)
);
BUFX6TS U1868 ( .A(n631), .Y(n4687) );
BUFX4TS U1869 ( .A(n5675), .Y(n4661) );
OAI22X1TS U1870 ( .A0(n4012), .A1(n4011), .B0(n4525), .B1(n4118), .Y(n4111)
);
OAI22X2TS U1871 ( .A0(n5522), .A1(n4293), .B0(n5130), .B1(n4428), .Y(n4636)
);
XNOR2X1TS U1872 ( .A(n5893), .B(n762), .Y(n5590) );
XNOR2X1TS U1873 ( .A(n6642), .B(n6403), .Y(n5565) );
INVX6TS U1874 ( .A(n6311), .Y(n820) );
XNOR2X1TS U1875 ( .A(n8809), .B(n6376), .Y(n5668) );
XNOR2X1TS U1876 ( .A(n6642), .B(n6337), .Y(n5811) );
XNOR2X1TS U1877 ( .A(n7016), .B(n5953), .Y(n5862) );
XNOR2X1TS U1878 ( .A(n5874), .B(n5203), .Y(n5349) );
OAI22X1TS U1879 ( .A0(n6127), .A1(n4939), .B0(n5150), .B1(n6829), .Y(n5188)
);
XNOR2X1TS U1880 ( .A(n7016), .B(n5392), .Y(n5306) );
XNOR2X1TS U1881 ( .A(n5132), .B(n5299), .Y(n5235) );
XNOR2X1TS U1882 ( .A(n6667), .B(n5589), .Y(n5112) );
XNOR2X1TS U1883 ( .A(n6842), .B(n6333), .Y(n5777) );
BUFX6TS U1884 ( .A(n6482), .Y(n813) );
BUFX3TS U1885 ( .A(n3200), .Y(n6021) );
BUFX3TS U1886 ( .A(n6715), .Y(n6073) );
INVX4TS U1887 ( .A(n663), .Y(n712) );
INVX8TS U1888 ( .A(n6880), .Y(n6775) );
XNOR2X1TS U1889 ( .A(n6296), .B(n6032), .Y(n6199) );
BUFX8TS U1890 ( .A(n921), .Y(n631) );
BUFX4TS U1891 ( .A(n634), .Y(n829) );
BUFX6TS U1892 ( .A(n3100), .Y(n4610) );
BUFX4TS U1893 ( .A(n637), .Y(n6023) );
XNOR2X1TS U1894 ( .A(n5503), .B(n736), .Y(n3265) );
BUFX8TS U1895 ( .A(n951), .Y(n4680) );
OAI22X1TS U1896 ( .A0(n4610), .A1(n3894), .B0(n2270), .B1(n4001), .Y(n3981)
);
OAI22X1TS U1897 ( .A0(n6264), .A1(n3571), .B0(n5877), .B1(n3729), .Y(n3702)
);
OAI22X1TS U1898 ( .A0(n815), .A1(n3878), .B0(n734), .B1(n3997), .Y(n3978) );
OAI22X1TS U1899 ( .A0(n5978), .A1(n3672), .B0(n5564), .B1(n3794), .Y(n3790)
);
OAI22X1TS U1900 ( .A0(n5664), .A1(n3725), .B0(n3834), .B1(n7332), .Y(n3748)
);
OAI22X1TS U1901 ( .A0(n633), .A1(n2794), .B0(n4116), .B1(n2896), .Y(n2862)
);
ADDFX2TS U1902 ( .A(n3968), .B(n3967), .CI(n3966), .CO(n3996), .S(n3964) );
CLKINVX6TS U1903 ( .A(Op_MY[9]), .Y(n4776) );
OAI22X1TS U1904 ( .A0(n813), .A1(n6954), .B0(n2666), .B1(n2979), .Y(n2688)
);
OAI22X1TS U1905 ( .A0(n1727), .A1(n990), .B0(n3071), .B1(n1091), .Y(n1014)
);
XNOR2X1TS U1906 ( .A(n751), .B(n5745), .Y(n2446) );
BUFX3TS U1907 ( .A(n1027), .Y(n3051) );
XNOR2X1TS U1908 ( .A(n2258), .B(n4208), .Y(n1697) );
BUFX3TS U1909 ( .A(n3596), .Y(n3837) );
INVX6TS U1910 ( .A(n5439), .Y(n713) );
OAI22X1TS U1911 ( .A0(n1791), .A1(n1200), .B0(n5390), .B1(n1176), .Y(n1197)
);
INVX4TS U1912 ( .A(n743), .Y(n625) );
OAI22X1TS U1913 ( .A0(n3540), .A1(n3261), .B0(n4002), .B1(n3260), .Y(n3294)
);
OAI22X1TS U1914 ( .A0(n6067), .A1(n1363), .B0(n1364), .B1(n6890), .Y(n1442)
);
OR2X1TS U1915 ( .A(n1388), .B(n1387), .Y(n1404) );
OAI22X1TS U1916 ( .A0(n2783), .A1(n1369), .B0(n3116), .B1(n1440), .Y(n1465)
);
BUFX8TS U1917 ( .A(n6055), .Y(n6429) );
BUFX6TS U1918 ( .A(n4370), .Y(n3175) );
OAI22X1TS U1919 ( .A0(n1838), .A1(n1498), .B0(n1214), .B1(n1822), .Y(n1308)
);
OAI22X1TS U1920 ( .A0(n1710), .A1(n1623), .B0(n758), .B1(n1511), .Y(n1611)
);
BUFX6TS U1921 ( .A(n4085), .Y(n4057) );
ADDFX2TS U1922 ( .A(n4550), .B(n4549), .CI(n4548), .CO(n4563), .S(n4640) );
OAI22X1TS U1923 ( .A0(n6750), .A1(n5584), .B0(n730), .B1(n5634), .Y(n5637)
);
BUFX6TS U1924 ( .A(n5944), .Y(n702) );
XNOR2X1TS U1925 ( .A(n6404), .B(n820), .Y(n6405) );
OAI22X1TS U1926 ( .A0(n6463), .A1(n5127), .B0(n5480), .B1(n5210), .Y(n5201)
);
INVX4TS U1927 ( .A(n689), .Y(n690) );
OAI22X1TS U1928 ( .A0(n6127), .A1(n5861), .B0(n5972), .B1(n5860), .Y(n6028)
);
OAI22X1TS U1929 ( .A0(n5978), .A1(n5977), .B0(n6387), .B1(n6068), .Y(n6018)
);
BUFX8TS U1930 ( .A(n2943), .Y(n4668) );
BUFX3TS U1931 ( .A(n6101), .Y(n7013) );
INVX6TS U1932 ( .A(n7051), .Y(n6973) );
BUFX4TS U1933 ( .A(n6666), .Y(n6750) );
BUFX4TS U1934 ( .A(n6101), .Y(n6679) );
BUFX3TS U1935 ( .A(n631), .Y(n6745) );
BUFX8TS U1936 ( .A(n6929), .Y(n6254) );
BUFX8TS U1937 ( .A(n2979), .Y(n6480) );
BUFX6TS U1938 ( .A(n6101), .Y(n4780) );
BUFX6TS U1939 ( .A(n6859), .Y(n6145) );
BUFX4TS U1940 ( .A(n631), .Y(n6663) );
BUFX6TS U1941 ( .A(n6646), .Y(n6719) );
OAI22X1TS U1942 ( .A0(n6463), .A1(n3272), .B0(n788), .B1(n3593), .Y(n3559)
);
INVX2TS U1943 ( .A(n757), .Y(n760) );
INVX6TS U1944 ( .A(n4939), .Y(n2137) );
INVX4TS U1945 ( .A(n5093), .Y(n803) );
OAI22X1TS U1946 ( .A0(n4613), .A1(n1715), .B0(n808), .B1(n1684), .Y(n1686)
);
ADDFX2TS U1947 ( .A(n1174), .B(n1173), .CI(n1172), .CO(n1033), .S(n1226) );
ADDHXLTS U1948 ( .A(n2429), .B(n2428), .CO(n2484), .S(n2537) );
OAI22X1TS U1949 ( .A0(n3227), .A1(n2446), .B0(n3175), .B1(n2445), .Y(n2506)
);
ADDFX2TS U1950 ( .A(n2301), .B(n2300), .CI(n2299), .CO(n2536), .S(n2293) );
INVX2TS U1951 ( .A(n757), .Y(n758) );
XNOR2X1TS U1952 ( .A(n686), .B(n1943), .Y(n2030) );
BUFX3TS U1953 ( .A(n930), .Y(n2668) );
ADDFHX2TS U1954 ( .A(n1320), .B(n1319), .CI(n1318), .CO(n1436), .S(n1330) );
NAND2X4TS U1955 ( .A(n7209), .B(n7456), .Y(n7201) );
OAI22X1TS U1956 ( .A0(n6443), .A1(n6405), .B0(n6670), .B1(n6336), .Y(n6346)
);
XNOR2X1TS U1957 ( .A(n6945), .B(n7009), .Y(n6913) );
OAI22X1TS U1958 ( .A0(n4938), .A1(n658), .B0(n621), .B1(n6829), .Y(n6696) );
BUFX6TS U1959 ( .A(n2785), .Y(n6929) );
OAI22X1TS U1960 ( .A0(n6772), .A1(n6262), .B0(n6746), .B1(n6310), .Y(n6295)
);
ADDFX2TS U1961 ( .A(n3545), .B(n3544), .CI(n3543), .CO(n3633), .S(n3548) );
ADDFHX2TS U1962 ( .A(n4189), .B(n4188), .CI(n4187), .CO(n4375), .S(n4274) );
ADDFHX2TS U1963 ( .A(n2848), .B(n2847), .CI(n2846), .CO(n2988), .S(n2897) );
BUFX3TS U1964 ( .A(n951), .Y(n2448) );
ADDHXLTS U1965 ( .A(n1682), .B(n1681), .CO(n2117), .S(n1745) );
BUFX4TS U1966 ( .A(n2884), .Y(n4260) );
XNOR2X1TS U1967 ( .A(n685), .B(n1984), .Y(n1917) );
INVX8TS U1968 ( .A(n4071), .Y(n1948) );
ADDFX2TS U1969 ( .A(n4269), .B(n4268), .CI(n4267), .CO(n4379), .S(n4170) );
ADDFHX2TS U1970 ( .A(n4603), .B(n4602), .CI(n4601), .CO(n4786), .S(n4720) );
AOI21X2TS U1971 ( .A0(n7223), .A1(n7778), .B0(n7222), .Y(n7224) );
INVX4TS U1972 ( .A(n5710), .Y(n795) );
ADDFX2TS U1973 ( .A(n6725), .B(n6724), .CI(n6723), .CO(n6759), .S(n7071) );
ADDFX2TS U1974 ( .A(n3447), .B(n3446), .CI(n3445), .CO(n3450), .S(n3469) );
ADDFX2TS U1975 ( .A(n3664), .B(n3663), .CI(n3662), .CO(n3761), .S(n3654) );
BUFX3TS U1976 ( .A(n640), .Y(n4442) );
ADDFHX2TS U1977 ( .A(n2760), .B(n2759), .CI(n2758), .CO(n2803), .S(n2734) );
NOR2XLTS U1978 ( .A(n8367), .B(n8243), .Y(n8244) );
ADDFHX2TS U1979 ( .A(n5550), .B(n5549), .CI(n5548), .CO(n6089), .S(n5546) );
NOR2X4TS U1980 ( .A(n7908), .B(n7930), .Y(n3523) );
ADDFX2TS U1981 ( .A(n2190), .B(n2189), .CI(n2188), .CO(n2239), .S(n2191) );
NOR2XLTS U1982 ( .A(n8853), .B(n8849), .Y(n8238) );
BUFX3TS U1983 ( .A(n3832), .Y(n7332) );
OAI21X2TS U1984 ( .A0(n7743), .A1(n7520), .B0(n7519), .Y(n7521) );
NOR2X2TS U1985 ( .A(n7733), .B(n7494), .Y(n7496) );
NOR2X6TS U1986 ( .A(n3516), .B(n3517), .Y(n7918) );
ADDFHX2TS U1987 ( .A(n3492), .B(n3491), .CI(n3490), .CO(n3518), .S(n3517) );
ADDFHX2TS U1988 ( .A(n4385), .B(n4384), .CI(n4383), .CO(n5041), .S(n5040) );
INVX4TS U1989 ( .A(n8059), .Y(n3505) );
NAND2X4TS U1990 ( .A(n5044), .B(n8066), .Y(n5046) );
NAND2X1TS U1991 ( .A(n909), .B(n892), .Y(n1942) );
ADDFHX2TS U1992 ( .A(n2591), .B(n2590), .CI(n2589), .CO(n2597), .S(n2596) );
NOR2X4TS U1993 ( .A(n3521), .B(n3520), .Y(n7908) );
NAND2X1TS U1994 ( .A(n8418), .B(n8241), .Y(n8364) );
OAI21XLTS U1995 ( .A0(n7743), .A1(n7742), .B0(n7741), .Y(n7744) );
ADDFX2TS U1996 ( .A(n7126), .B(n7125), .CI(n7124), .CO(n7235), .S(n7233) );
NAND2X1TS U1997 ( .A(n7565), .B(n7433), .Y(n7591) );
BUFX3TS U1998 ( .A(n8390), .Y(n8324) );
ADDFHX2TS U1999 ( .A(n3850), .B(n3849), .CI(n3848), .CO(n5030), .S(n5028) );
NAND2X2TS U2000 ( .A(n3517), .B(n3516), .Y(n7919) );
OR2X1TS U2001 ( .A(n7267), .B(n7266), .Y(n7698) );
NAND2X2TS U2002 ( .A(n917), .B(n7898), .Y(n8052) );
NAND2X2TS U2003 ( .A(n2095), .B(n2094), .Y(n8695) );
NOR2XLTS U2004 ( .A(n8676), .B(n8732), .Y(n8681) );
NOR2XLTS U2005 ( .A(n8015), .B(n7869), .Y(n7870) );
OAI21XLTS U2006 ( .A0(n8697), .A1(n8696), .B0(n8695), .Y(n8698) );
CLKBUFX2TS U2007 ( .A(n7859), .Y(n7860) );
OAI2BB1X1TS U2008 ( .A0N(FSM_add_overflow_flag), .A1N(n8186), .B0(n8185),
.Y(n8187) );
NAND2X1TS U2009 ( .A(n8253), .B(n8363), .Y(n8312) );
NAND2X2TS U2010 ( .A(n5159), .B(n5158), .Y(n7820) );
NOR2X1TS U2011 ( .A(n8123), .B(n7363), .Y(n7365) );
INVX2TS U2012 ( .A(n7443), .Y(n7584) );
OAI21X1TS U2013 ( .A0(n7761), .A1(n7760), .B0(n7759), .Y(n7762) );
OAI21X1TS U2014 ( .A0(n7694), .A1(n7668), .B0(n7667), .Y(n7669) );
NAND2X1TS U2015 ( .A(n7538), .B(n7537), .Y(n7539) );
AND2X2TS U2016 ( .A(n8191), .B(FS_Module_state_reg[1]), .Y(n8263) );
OAI21XLTS U2017 ( .A0(n7986), .A1(n7977), .B0(n7849), .Y(n7981) );
INVX2TS U2018 ( .A(n8665), .Y(n8725) );
AOI21X2TS U2019 ( .A0(n8593), .A1(n893), .B0(n1873), .Y(n8607) );
INVX4TS U2020 ( .A(n7897), .Y(n8061) );
NOR2XLTS U2021 ( .A(n8483), .B(n8869), .Y(n8484) );
OAI21XLTS U2022 ( .A0(n7986), .A1(n7985), .B0(n7984), .Y(n7990) );
INVX4TS U2023 ( .A(n7860), .Y(n8020) );
NOR2X1TS U2024 ( .A(n8413), .B(n8394), .Y(n8401) );
NOR2XLTS U2025 ( .A(n8336), .B(n8853), .Y(n8329) );
BUFX3TS U2026 ( .A(n8474), .Y(n8310) );
AOI21X2TS U2027 ( .A0(n870), .A1(n8135), .B0(n7612), .Y(n7616) );
AOI21X2TS U2028 ( .A0(n7748), .A1(n7558), .B0(n7557), .Y(n7561) );
AOI21X1TS U2029 ( .A0(n870), .A1(n7377), .B0(n7376), .Y(n7379) );
NAND2X1TS U2030 ( .A(n7551), .B(n7550), .Y(n7552) );
BUFX3TS U2031 ( .A(n8513), .Y(n8508) );
NAND2X1TS U2032 ( .A(n8167), .B(n8166), .Y(n8168) );
BUFX8TS U2033 ( .A(n1303), .Y(n5955) );
XNOR2X1TS U2034 ( .A(n7922), .B(n7921), .Y(n7923) );
XOR2X1TS U2035 ( .A(n7886), .B(n7885), .Y(n7887) );
INVX2TS U2036 ( .A(n671), .Y(n693) );
NAND2X1TS U2037 ( .A(n7815), .B(P_Sgf[73]), .Y(n7468) );
CLKXOR2X2TS U2038 ( .A(n7500), .B(n880), .Y(n7502) );
CLKXOR2X2TS U2039 ( .A(n7802), .B(n889), .Y(n7804) );
INVX2TS U2040 ( .A(n8842), .Y(n8765) );
INVX2TS U2041 ( .A(n8446), .Y(n8571) );
INVX2TS U2042 ( .A(n8446), .Y(n8510) );
INVX2TS U2043 ( .A(n8446), .Y(n8563) );
XOR2X1TS U2044 ( .A(n8169), .B(n8168), .Y(n8170) );
INVX4TS U2045 ( .A(n622), .Y(n696) );
INVX8TS U2046 ( .A(n6415), .Y(n8233) );
CLKMX2X2TS U2047 ( .A(n8087), .B(P_Sgf[61]), .S0(n727), .Y(Sgf_operation_n48) );
CLKMX2X2TS U2048 ( .A(n8014), .B(P_Sgf[35]), .S0(n725), .Y(Sgf_operation_n74) );
CLKMX2X2TS U2049 ( .A(n7900), .B(P_Sgf[41]), .S0(n774), .Y(Sgf_operation_n68) );
CLKMX2X2TS U2050 ( .A(Exp_module_Data_S[10]), .B(exp_oper_result[10]), .S0(
n693), .Y(n406) );
CLKMX2X2TS U2051 ( .A(n8737), .B(P_Sgf[24]), .S0(n725), .Y(Sgf_operation_n85) );
OAI21X2TS U2052 ( .A0(n7610), .A1(n777), .B0(n7609), .Y(Sgf_operation_n37)
);
OAI21X2TS U2053 ( .A0(n7782), .A1(n7792), .B0(n7781), .Y(Sgf_operation_n30)
);
OAI21X1TS U2054 ( .A0(n7513), .A1(n727), .B0(n7512), .Y(Sgf_operation_n17)
);
OR2X1TS U2055 ( .A(exp_oper_result[11]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
INVX4TS U2056 ( .A(n658), .Y(n4176) );
NAND2X6TS U2057 ( .A(n921), .B(n920), .Y(n6071) );
BUFX6TS U2058 ( .A(n6649), .Y(n6264) );
INVX6TS U2059 ( .A(n644), .Y(n5533) );
INVX4TS U2060 ( .A(n743), .Y(n744) );
INVX4TS U2061 ( .A(n743), .Y(n745) );
NAND3X4TS U2062 ( .A(n8219), .B(n8206), .C(n8851), .Y(n624) );
AND2X2TS U2063 ( .A(n8207), .B(FS_Module_state_reg[3]), .Y(n8457) );
BUFX3TS U2064 ( .A(n8766), .Y(n8773) );
INVX2TS U2065 ( .A(n8756), .Y(n682) );
CLKINVX3TS U2066 ( .A(n8756), .Y(n728) );
BUFX3TS U2067 ( .A(n682), .Y(n8595) );
CLKINVX3TS U2068 ( .A(n773), .Y(n777) );
INVX2TS U2069 ( .A(n773), .Y(n775) );
INVX4TS U2070 ( .A(n773), .Y(n776) );
INVX4TS U2071 ( .A(n773), .Y(n774) );
CLKINVX3TS U2072 ( .A(n8756), .Y(n8638) );
MX2X2TS U2073 ( .A(n8111), .B(P_Sgf[58]), .S0(n725), .Y(Sgf_operation_n51)
);
MX2X2TS U2074 ( .A(n7893), .B(n772), .S0(n7815), .Y(Sgf_operation_n57) );
MX2X2TS U2075 ( .A(n8005), .B(P_Sgf[34]), .S0(n8608), .Y(Sgf_operation_n75)
);
MX2X2TS U2076 ( .A(n7865), .B(P_Sgf[37]), .S0(n725), .Y(Sgf_operation_n72)
);
CLKMX2X2TS U2077 ( .A(n7965), .B(P_Sgf[32]), .S0(n8638), .Y(
Sgf_operation_n77) );
AOI21X4TS U2078 ( .A0(n7711), .A1(n7522), .B0(n7521), .Y(n7761) );
INVX8TS U2079 ( .A(n7407), .Y(n7825) );
BUFX8TS U2080 ( .A(n5266), .Y(n7407) );
CLKMX2X2TS U2081 ( .A(n8691), .B(P_Sgf[19]), .S0(n682), .Y(Sgf_operation_n90) );
NAND2X6TS U2082 ( .A(n8074), .B(n5056), .Y(n7406) );
NOR2X6TS U2083 ( .A(n8115), .B(n840), .Y(n8066) );
OR2X2TS U2084 ( .A(n5053), .B(n5054), .Y(n649) );
AND2X2TS U2085 ( .A(n7685), .B(n7684), .Y(n895) );
NAND2X2TS U2086 ( .A(n7236), .B(n7235), .Y(n7537) );
NOR2X2TS U2087 ( .A(n7731), .B(n7736), .Y(n7739) );
NAND2X2TS U2088 ( .A(n7258), .B(n7257), .Y(n7684) );
NAND2X2TS U2089 ( .A(n7514), .B(n7325), .Y(n7731) );
ADDFHX2TS U2090 ( .A(n4763), .B(n4762), .CI(n4761), .CO(n5011), .S(n4989) );
ADDFHX2TS U2091 ( .A(n3847), .B(n3846), .CI(n3845), .CO(n3957), .S(n3850) );
ADDFHX2TS U2092 ( .A(n4860), .B(n4859), .CI(n4858), .CO(n4956), .S(n4820) );
INVX2TS U2093 ( .A(n2104), .Y(n848) );
INVX3TS U2094 ( .A(n2103), .Y(n851) );
INVX2TS U2095 ( .A(n7661), .Y(n7323) );
ADDFHX2TS U2096 ( .A(n1831), .B(n1830), .CI(n1829), .CO(n2102), .S(n2101) );
ADDFHX2TS U2097 ( .A(n4108), .B(n4107), .CI(n4106), .CO(n4234), .S(n4070) );
BUFX8TS U2098 ( .A(n8595), .Y(n7815) );
ADDFX2TS U2099 ( .A(n6472), .B(n6471), .CI(n6470), .CO(n6452), .S(n6549) );
ADDFHX2TS U2100 ( .A(n4509), .B(n4508), .CI(n4507), .CO(n4790), .S(n4656) );
INVX2TS U2101 ( .A(n8614), .Y(n8598) );
BUFX8TS U2102 ( .A(n725), .Y(n7792) );
BUFX8TS U2103 ( .A(n682), .Y(n8753) );
ADDFHX2TS U2104 ( .A(n1812), .B(n1811), .CI(n1810), .CO(n1828), .S(n1855) );
NAND2X2TS U2105 ( .A(n728), .B(P_Sgf[85]), .Y(n7422) );
ADDFHX1TS U2106 ( .A(n3876), .B(n3875), .CI(n3874), .CO(n4146), .S(n3889) );
INVX12TS U2107 ( .A(n679), .Y(n630) );
BUFX6TS U2108 ( .A(n8638), .Y(n8748) );
CLKMX2X2TS U2109 ( .A(n8538), .B(Add_result[7]), .S0(n8832), .Y(n465) );
AO21X1TS U2110 ( .A0(n5328), .A1(n5327), .B0(n5326), .Y(n5406) );
AO21X1TS U2111 ( .A0(n6827), .A1(n6826), .B0(n6825), .Y(n6845) );
NAND2X1TS U2112 ( .A(n8313), .B(Sgf_normalized_result[41]), .Y(n8254) );
BUFX12TS U2113 ( .A(n2890), .Y(n6055) );
CLKMX2X2TS U2114 ( .A(Data_MX[47]), .B(n793), .S0(n8751), .Y(n586) );
BUFX8TS U2115 ( .A(n6649), .Y(n5302) );
INVX8TS U2116 ( .A(n873), .Y(n5622) );
NAND2X6TS U2117 ( .A(n918), .B(n639), .Y(n5706) );
INVX6TS U2118 ( .A(n623), .Y(n697) );
NAND2X6TS U2119 ( .A(n945), .B(n641), .Y(n3100) );
INVX2TS U2120 ( .A(n8320), .Y(n8321) );
INVX6TS U2121 ( .A(n737), .Y(n739) );
INVX2TS U2122 ( .A(n8547), .Y(n8553) );
INVX2TS U2123 ( .A(n8494), .Y(n8495) );
CLKINVX2TS U2124 ( .A(n8470), .Y(n8471) );
BUFX6TS U2125 ( .A(n939), .Y(n3928) );
BUFX12TS U2126 ( .A(n997), .Y(n932) );
BUFX12TS U2127 ( .A(n1082), .Y(n930) );
INVX12TS U2128 ( .A(n4205), .Y(n628) );
BUFX20TS U2129 ( .A(n5794), .Y(n629) );
NAND2X4TS U2130 ( .A(n7810), .B(n881), .Y(n7813) );
MX2X2TS U2131 ( .A(n8122), .B(P_Sgf[55]), .S0(n777), .Y(Sgf_operation_n54)
);
MX2X2TS U2132 ( .A(n8105), .B(P_Sgf[57]), .S0(n777), .Y(Sgf_operation_n52)
);
MX2X2TS U2133 ( .A(n7913), .B(P_Sgf[49]), .S0(n8748), .Y(Sgf_operation_n60)
);
XNOR2X1TS U2134 ( .A(n8037), .B(n8036), .Y(n8038) );
OAI21X2TS U2135 ( .A0(n8126), .A1(n5062), .B0(n5061), .Y(n5063) );
BUFX16TS U2136 ( .A(n7373), .Y(n7711) );
INVX6TS U2137 ( .A(n8107), .Y(n8123) );
NOR2X4TS U2138 ( .A(n7733), .B(n7520), .Y(n7522) );
INVX12TS U2139 ( .A(n7479), .Y(n7743) );
NAND2X6TS U2140 ( .A(n7228), .B(n7227), .Y(n7479) );
NOR2X4TS U2141 ( .A(n8026), .B(n3525), .Y(n3499) );
INVX2TS U2142 ( .A(n7452), .Y(n7424) );
NOR2X4TS U2143 ( .A(n7296), .B(n7607), .Y(n7297) );
INVX4TS U2144 ( .A(n7713), .Y(n7645) );
INVX4TS U2145 ( .A(n7714), .Y(n7641) );
AND2X2TS U2146 ( .A(n7383), .B(n7382), .Y(n901) );
INVX2TS U2147 ( .A(n7777), .Y(n7222) );
INVX3TS U2148 ( .A(n7772), .Y(n7223) );
AND2X2TS U2149 ( .A(n7466), .B(n7465), .Y(n913) );
CLKMX2X2TS U2150 ( .A(n8255), .B(Add_result[52]), .S0(n8832), .Y(n420) );
INVX4TS U2151 ( .A(n7787), .Y(n7200) );
NAND2X4TS U2152 ( .A(n5035), .B(n5036), .Y(n8113) );
NAND2X6TS U2153 ( .A(n7213), .B(n7212), .Y(n7382) );
CLKMX2X2TS U2154 ( .A(n8664), .B(P_Sgf[11]), .S0(n725), .Y(Sgf_operation_n98) );
NOR2X4TS U2155 ( .A(n7236), .B(n7235), .Y(n7536) );
AND2X2TS U2156 ( .A(n7673), .B(n7672), .Y(n896) );
INVX4TS U2157 ( .A(n7868), .Y(n2634) );
NAND2X1TS U2158 ( .A(n7884), .B(n7883), .Y(n7885) );
ADDFHX2TS U2159 ( .A(n6637), .B(n6636), .CI(n6635), .CO(n7195), .S(n7221) );
CLKMX2X2TS U2160 ( .A(n8621), .B(P_Sgf[10]), .S0(n774), .Y(Sgf_operation_n99) );
INVX4TS U2161 ( .A(n7894), .Y(n8000) );
ADDFHX2TS U2162 ( .A(n5838), .B(n5837), .CI(n5836), .CO(n5924), .S(n6094) );
ADDFHX2TS U2163 ( .A(n4976), .B(n4975), .CI(n4974), .CO(n4994), .S(n4964) );
AND2X2TS U2164 ( .A(n7801), .B(n7800), .Y(n889) );
AND2X2TS U2165 ( .A(n7706), .B(n7705), .Y(n888) );
ADDFHX2TS U2166 ( .A(n5844), .B(n5843), .CI(n5842), .CO(n6085), .S(n6088) );
AND2X2TS U2167 ( .A(n7336), .B(n7735), .Y(n897) );
AND2X2TS U2168 ( .A(n7324), .B(n7662), .Y(n7325) );
ADDFHX2TS U2169 ( .A(n3938), .B(n3937), .CI(n3936), .CO(n4391), .S(n3958) );
NAND2X2TS U2170 ( .A(n776), .B(P_Sgf[105]), .Y(n7756) );
ADDFX2TS U2171 ( .A(n6526), .B(n6525), .CI(n6524), .CO(n6574), .S(n6637) );
INVX2TS U2172 ( .A(n8660), .Y(n2018) );
NOR2X4TS U2173 ( .A(n2101), .B(n2100), .Y(n8666) );
ADDFX2TS U2174 ( .A(n6616), .B(n6615), .CI(n6614), .CO(n6634), .S(n6627) );
NAND2X2TS U2175 ( .A(n842), .B(n841), .Y(n4162) );
ADDFHX2TS U2176 ( .A(n3601), .B(n3600), .CI(n3599), .CO(n3658), .S(n3553) );
NAND2X2TS U2177 ( .A(n7313), .B(n7312), .Y(n7800) );
NAND2X2TS U2178 ( .A(n4153), .B(n4152), .Y(n841) );
CLKMX2X2TS U2179 ( .A(n8287), .B(Add_result[46]), .S0(n8832), .Y(n426) );
CLKMX2X2TS U2180 ( .A(n8380), .B(Add_result[31]), .S0(n8832), .Y(n441) );
NAND2X2TS U2181 ( .A(n8608), .B(P_Sgf[87]), .Y(n7404) );
CLKMX2X2TS U2182 ( .A(n8473), .B(Add_result[17]), .S0(n716), .Y(n455) );
CLKMX2X2TS U2183 ( .A(n8344), .B(Add_result[37]), .S0(n716), .Y(n435) );
NAND2X2TS U2184 ( .A(n8753), .B(P_Sgf[103]), .Y(n7769) );
ADDFHX1TS U2185 ( .A(n2128), .B(n2127), .CI(n2126), .CO(n2155), .S(n2176) );
CLKMX2X2TS U2186 ( .A(n8479), .B(Add_result[16]), .S0(n716), .Y(n456) );
BUFX8TS U2187 ( .A(n682), .Y(n832) );
CLKMX2X2TS U2188 ( .A(n8445), .B(Add_result[21]), .S0(n716), .Y(n451) );
CLKMX2X2TS U2189 ( .A(n8438), .B(Add_result[22]), .S0(n716), .Y(n450) );
CLKMX2X2TS U2190 ( .A(n8354), .B(Add_result[35]), .S0(n8832), .Y(n437) );
CLKMX2X2TS U2191 ( .A(n8337), .B(Add_result[38]), .S0(n716), .Y(n434) );
NAND3X1TS U2192 ( .A(n8771), .B(n8770), .C(n8769), .Y(n604) );
CLKMX2X2TS U2193 ( .A(n8315), .B(Add_result[41]), .S0(n8832), .Y(n431) );
INVX4TS U2194 ( .A(n8756), .Y(n727) );
INVX4TS U2195 ( .A(n8756), .Y(n726) );
CLKMX2X2TS U2196 ( .A(n8452), .B(Add_result[20]), .S0(n716), .Y(n452) );
ADDHX1TS U2197 ( .A(n1309), .B(n1308), .CO(n1305), .S(n1486) );
NAND2X1TS U2198 ( .A(n8638), .B(P_Sgf[81]), .Y(n7562) );
AO21X1TS U2199 ( .A0(n7333), .A1(n7332), .B0(n875), .Y(n7749) );
AO21X1TS U2200 ( .A0(n6649), .A1(n6019), .B0(n7158), .Y(n7171) );
CLKMX2X2TS U2201 ( .A(n8512), .B(Add_result[11]), .S0(n716), .Y(n461) );
CLKMX2X2TS U2202 ( .A(n8503), .B(Add_result[12]), .S0(n8832), .Y(n460) );
CLKMX2X2TS U2203 ( .A(n8463), .B(Add_result[18]), .S0(n8832), .Y(n454) );
AO21X1TS U2204 ( .A0(n4846), .A1(n4845), .B0(n957), .Y(n4876) );
AO21X1TS U2205 ( .A0(n1710), .A1(n5666), .B0(n5665), .Y(n5747) );
AO21X1TS U2206 ( .A0(n810), .A1(n4259), .B0(n4258), .Y(n4348) );
AO21X1TS U2207 ( .A0(n781), .A1(n6745), .B0(n6744), .Y(n6797) );
OR2X2TS U2208 ( .A(n744), .B(n2242), .Y(n866) );
BUFX8TS U2209 ( .A(n6202), .Y(n633) );
AO21X1TS U2210 ( .A0(n6716), .A1(n6651), .B0(n6714), .Y(n6681) );
INVX2TS U2211 ( .A(n8839), .Y(n8179) );
AO21X1TS U2212 ( .A0(n5956), .A1(n625), .B0(n5955), .Y(n6061) );
INVX2TS U2213 ( .A(n856), .Y(n854) );
AO21X1TS U2214 ( .A0(n7057), .A1(n732), .B0(n911), .Y(n7130) );
AO21X1TS U2215 ( .A0(n812), .A1(n721), .B0(n7011), .Y(n7030) );
CLKMX2X2TS U2216 ( .A(n8519), .B(Add_result[10]), .S0(n716), .Y(n462) );
AO21X1TS U2217 ( .A0(n4443), .A1(n4442), .B0(n4441), .Y(n4589) );
AND2X2TS U2218 ( .A(n8588), .B(n8587), .Y(n8589) );
AO21X1TS U2219 ( .A0(n4556), .A1(n2270), .B0(n4555), .Y(n4665) );
AO21X1TS U2220 ( .A0(n6301), .A1(n6300), .B0(n6299), .Y(n6709) );
AO21X1TS U2221 ( .A0(n5796), .A1(n5795), .B0(n5794), .Y(n5870) );
CLKMX2X2TS U2222 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n8772), .Y(n545) );
CLKMX2X2TS U2223 ( .A(Data_MX[44]), .B(Op_MX[44]), .S0(n8772), .Y(n583) );
CLKMX2X2TS U2224 ( .A(Data_MY[14]), .B(Op_MY[14]), .S0(n8772), .Y(n489) );
CLKMX2X2TS U2225 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(n8772), .Y(n492) );
CLKMX2X2TS U2226 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n8751), .Y(n493) );
CLKMX2X2TS U2227 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n8751), .Y(n498) );
CLKMX2X2TS U2228 ( .A(Data_MY[24]), .B(n8233), .S0(n8751), .Y(n499) );
CLKMX2X2TS U2229 ( .A(Data_MX[11]), .B(n799), .S0(n8772), .Y(n550) );
CLKMX2X2TS U2230 ( .A(Data_MY[52]), .B(Op_MY[52]), .S0(n8772), .Y(n527) );
BUFX8TS U2231 ( .A(n2884), .Y(n2039) );
CLKMX2X2TS U2232 ( .A(Data_MY[56]), .B(Op_MY[56]), .S0(n8751), .Y(n531) );
CLKMX2X2TS U2233 ( .A(Data_MY[58]), .B(Op_MY[58]), .S0(n8772), .Y(n533) );
CLKMX2X2TS U2234 ( .A(Data_MY[61]), .B(Op_MY[61]), .S0(n8751), .Y(n536) );
NAND2X4TS U2235 ( .A(n5162), .B(n8185), .Y(n8756) );
CLKMX2X2TS U2236 ( .A(Data_MX[9]), .B(n8819), .S0(n8772), .Y(n548) );
CLKMX2X2TS U2237 ( .A(Data_MX[45]), .B(n8217), .S0(n8751), .Y(n584) );
CLKMX2X2TS U2238 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n8751), .Y(n484) );
CLKMX2X2TS U2239 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n8772), .Y(n485) );
CLKMX2X2TS U2240 ( .A(Data_MX[39]), .B(n626), .S0(n8222), .Y(n578) );
CLKMX2X2TS U2241 ( .A(Data_MX[48]), .B(Op_MX[48]), .S0(n8751), .Y(n587) );
INVX8TS U2242 ( .A(n684), .Y(n685) );
NAND2BX1TS U2243 ( .AN(n3254), .B(n7142), .Y(n3182) );
NAND2X6TS U2244 ( .A(n3181), .B(n3180), .Y(n6649) );
INVX12TS U2245 ( .A(n7134), .Y(n769) );
INVX4TS U2246 ( .A(n8773), .Y(n8751) );
INVX4TS U2247 ( .A(n8773), .Y(n8772) );
CLKMX2X2TS U2248 ( .A(Data_MY[50]), .B(Op_MY[50]), .S0(n8222), .Y(n525) );
BUFX12TS U2249 ( .A(n7141), .Y(n6778) );
BUFX12TS U2250 ( .A(n8814), .Y(n821) );
NAND2BX1TS U2251 ( .AN(n3254), .B(n638), .Y(n986) );
INVX4TS U2252 ( .A(n8457), .Y(n8832) );
CLKMX2X2TS U2253 ( .A(Op_MX[53]), .B(exp_oper_result[1]), .S0(n691), .Y(
S_Oper_A_exp[1]) );
CLKMX2X2TS U2254 ( .A(Op_MX[54]), .B(exp_oper_result[2]), .S0(n691), .Y(
S_Oper_A_exp[2]) );
INVX4TS U2255 ( .A(n8457), .Y(n716) );
BUFX12TS U2256 ( .A(n3928), .Y(n3987) );
CLKMX2X2TS U2257 ( .A(Op_MX[56]), .B(exp_oper_result[4]), .S0(n691), .Y(
S_Oper_A_exp[4]) );
INVX6TS U2258 ( .A(n7165), .Y(n5689) );
NOR2XLTS U2259 ( .A(n660), .B(n672), .Y(n673) );
INVX12TS U2260 ( .A(n6299), .Y(n8223) );
INVX6TS U2261 ( .A(n5710), .Y(n8806) );
BUFX16TS U2262 ( .A(n4669), .Y(n7011) );
INVX8TS U2263 ( .A(Op_MY[44]), .Y(n7027) );
INVX8TS U2264 ( .A(Op_MX[21]), .Y(n1303) );
INVX12TS U2265 ( .A(Op_MX[19]), .Y(n5794) );
BUFX3TS U2266 ( .A(n831), .Y(n8171) );
OAI21X2TS U2267 ( .A0(n7488), .A1(n8638), .B0(n7487), .Y(Sgf_operation_n13)
);
OAI21X2TS U2268 ( .A0(n7448), .A1(n726), .B0(n7447), .Y(Sgf_operation_n39)
);
XNOR2X2TS U2269 ( .A(n7446), .B(n7445), .Y(n7448) );
XOR2X2TS U2270 ( .A(n7391), .B(n903), .Y(n7393) );
AOI21X2TS U2271 ( .A0(n7798), .A1(n7548), .B0(n7547), .Y(n7553) );
MX2X2TS U2272 ( .A(n8093), .B(P_Sgf[54]), .S0(n775), .Y(Sgf_operation_n55)
);
MX2X2TS U2273 ( .A(n8170), .B(n830), .S0(n776), .Y(Sgf_operation_n56) );
AOI21X2TS U2274 ( .A0(n870), .A1(n7596), .B0(n7595), .Y(n7600) );
MX2X2TS U2275 ( .A(n8134), .B(P_Sgf[59]), .S0(n7792), .Y(Sgf_operation_n50)
);
MX2X2TS U2276 ( .A(n7943), .B(P_Sgf[51]), .S0(n775), .Y(Sgf_operation_n58)
);
OAI21X2TS U2277 ( .A0(n7372), .A1(n8753), .B0(n7371), .Y(Sgf_operation_n46)
);
OAI21X2TS U2278 ( .A0(n7359), .A1(n832), .B0(n7358), .Y(Sgf_operation_n49)
);
BUFX16TS U2279 ( .A(n8138), .Y(n676) );
XNOR2X2TS U2280 ( .A(n7370), .B(n7369), .Y(n7372) );
INVX3TS U2281 ( .A(n7651), .Y(n7680) );
NOR2X4TS U2282 ( .A(n7712), .B(n7715), .Y(n7809) );
BUFX16TS U2283 ( .A(n8138), .Y(n870) );
MX2X2TS U2284 ( .A(n7887), .B(P_Sgf[40]), .S0(n7815), .Y(Sgf_operation_n69)
);
NAND3X4TS U2285 ( .A(n7650), .B(n7649), .C(n7648), .Y(n7651) );
XOR2X1TS U2286 ( .A(n8004), .B(n8003), .Y(n8005) );
XOR2X1TS U2287 ( .A(n8013), .B(n8012), .Y(n8014) );
XNOR2X1TS U2288 ( .A(n8030), .B(n8029), .Y(n8031) );
XNOR2X1TS U2289 ( .A(n8057), .B(n8056), .Y(n8058) );
XOR2X1TS U2290 ( .A(n7998), .B(n7997), .Y(n7999) );
XNOR2X1TS U2291 ( .A(n8049), .B(n8048), .Y(n8050) );
XNOR2X2TS U2292 ( .A(n833), .B(n7873), .Y(n7874) );
XNOR2X1TS U2293 ( .A(n8064), .B(n8063), .Y(n8065) );
XOR2X1TS U2294 ( .A(n7864), .B(n7863), .Y(n7865) );
OAI2BB1X2TS U2295 ( .A0N(n8020), .A1N(n7870), .B0(n834), .Y(n833) );
BUFX20TS U2296 ( .A(n7711), .Y(n632) );
NOR2X4TS U2297 ( .A(n7733), .B(n7471), .Y(n7481) );
INVX2TS U2298 ( .A(n7604), .Y(n7605) );
INVX12TS U2299 ( .A(n915), .Y(n7565) );
BUFX16TS U2300 ( .A(n6641), .Y(n7733) );
CLKMX2X2TS U2301 ( .A(n8716), .B(P_Sgf[21]), .S0(n727), .Y(Sgf_operation_n88) );
CLKMX2X2TS U2302 ( .A(n8671), .B(P_Sgf[18]), .S0(n7792), .Y(
Sgf_operation_n91) );
NAND2X4TS U2303 ( .A(n7307), .B(n7576), .Y(n7309) );
CLKMX2X2TS U2304 ( .A(n8706), .B(P_Sgf[16]), .S0(n8748), .Y(
Sgf_operation_n93) );
AND2X2TS U2305 ( .A(n7411), .B(n7410), .Y(n669) );
AND2X2TS U2306 ( .A(n5160), .B(n7820), .Y(n878) );
CLKMX2X2TS U2307 ( .A(n8652), .B(P_Sgf[15]), .S0(n774), .Y(Sgf_operation_n94) );
CLKMX2X2TS U2308 ( .A(n8675), .B(P_Sgf[17]), .S0(n8595), .Y(
Sgf_operation_n92) );
CLKMX2X2TS U2309 ( .A(n8639), .B(P_Sgf[14]), .S0(n8748), .Y(
Sgf_operation_n95) );
NAND2X6TS U2310 ( .A(n7470), .B(n7272), .Y(n7274) );
INVX2TS U2311 ( .A(n7564), .Y(n7568) );
AND2X2TS U2312 ( .A(n7615), .B(n7614), .Y(n879) );
NOR2X1TS U2313 ( .A(n7880), .B(n8015), .Y(n7882) );
OAI21X1TS U2314 ( .A0(n8725), .A1(n8666), .B0(n8672), .Y(n8670) );
NAND2X6TS U2315 ( .A(n7788), .B(n891), .Y(n7452) );
INVX2TS U2316 ( .A(n8040), .Y(n8041) );
OAI21X1TS U2317 ( .A0(n8725), .A1(n8717), .B0(n8719), .Y(n8690) );
NAND2X4TS U2318 ( .A(n2643), .B(n7866), .Y(n2645) );
OAI21X1TS U2319 ( .A0(n8725), .A1(n8724), .B0(n8723), .Y(n8729) );
AND2X2TS U2320 ( .A(n7587), .B(n7620), .Y(n904) );
CLKMX2X2TS U2321 ( .A(n8656), .B(P_Sgf[13]), .S0(n8748), .Y(
Sgf_operation_n96) );
AND2X2TS U2322 ( .A(n7390), .B(n7389), .Y(n903) );
NAND2X6TS U2323 ( .A(n5026), .B(n5025), .Y(n8202) );
AND2X2TS U2324 ( .A(n7637), .B(n7636), .Y(n902) );
AND2X2TS U2325 ( .A(n7347), .B(n7346), .Y(n885) );
INVX2TS U2326 ( .A(n840), .Y(n8119) );
INVX2TS U2327 ( .A(n646), .Y(n7462) );
CLKMX2X2TS U2328 ( .A(Exp_module_Data_S[11]), .B(exp_oper_result[11]), .S0(
n692), .Y(n405) );
NAND2X6TS U2329 ( .A(n646), .B(n7466), .Y(n7580) );
AND2X2TS U2330 ( .A(n662), .B(n7378), .Y(n899) );
INVX6TS U2331 ( .A(n7621), .Y(n7587) );
AND2X2TS U2332 ( .A(n7607), .B(n646), .Y(n905) );
AND2X2TS U2333 ( .A(n7599), .B(n7598), .Y(n898) );
AND2X2TS U2334 ( .A(n7626), .B(n7625), .Y(n916) );
AND2X2TS U2335 ( .A(n7402), .B(n7531), .Y(n884) );
NAND2X6TS U2336 ( .A(n7278), .B(n7277), .Y(n8136) );
AND2X2TS U2337 ( .A(n7727), .B(n7726), .Y(n882) );
NOR2X1TS U2338 ( .A(n8006), .B(n7992), .Y(n7994) );
NAND2X1TS U2339 ( .A(n7862), .B(n7868), .Y(n7863) );
NAND2X6TS U2340 ( .A(n8021), .B(n7883), .Y(n2641) );
CLKMX2X2TS U2341 ( .A(n8260), .B(Add_result[51]), .S0(n8518), .Y(n421) );
ADDFHX2TS U2342 ( .A(n3632), .B(n3631), .CI(n3630), .CO(n3737), .S(n3529) );
OAI21X2TS U2343 ( .A0(n7536), .A1(n7531), .B0(n7537), .Y(n7237) );
AND2X2TS U2344 ( .A(n7653), .B(n7678), .Y(n900) );
NAND2X6TS U2345 ( .A(n7196), .B(n7195), .Y(n7787) );
NOR2X6TS U2346 ( .A(n8717), .B(n846), .Y(n845) );
CLKMX2X2TS U2347 ( .A(n8629), .B(P_Sgf[12]), .S0(n775), .Y(Sgf_operation_n97) );
AND2X2TS U2348 ( .A(n7499), .B(n7504), .Y(n880) );
ADDFHX2TS U2349 ( .A(n3477), .B(n3476), .CI(n3475), .CO(n3479), .S(n3490) );
NOR2X6TS U2350 ( .A(n7207), .B(n7206), .Y(n7597) );
NOR2X1TS U2351 ( .A(n8693), .B(n8696), .Y(n8699) );
NAND2X4TS U2352 ( .A(n7957), .B(n7962), .Y(n2613) );
NAND2X6TS U2353 ( .A(n8727), .B(n8721), .Y(n846) );
CLKMX2X2TS U2354 ( .A(n8602), .B(P_Sgf[9]), .S0(n8608), .Y(
Sgf_operation_n100) );
ADDFHX2TS U2355 ( .A(n3465), .B(n3464), .CI(n3463), .CO(n3460), .S(n3492) );
AND2X2TS U2356 ( .A(n7510), .B(n7509), .Y(n890) );
NAND2X4TS U2357 ( .A(n7234), .B(n7233), .Y(n7531) );
CLKMX2X2TS U2358 ( .A(n8267), .B(Add_result[50]), .S0(n715), .Y(n422) );
ADDFHX2TS U2359 ( .A(n3474), .B(n3473), .CI(n3472), .CO(n3487), .S(n3498) );
INVX3TS U2360 ( .A(n8668), .Y(n849) );
ADDFHX2TS U2361 ( .A(n4379), .B(n4378), .CI(n4377), .CO(n4963), .S(n4352) );
ADDFHX2TS U2362 ( .A(n7090), .B(n7089), .CI(n7088), .CO(n7229), .S(n7206) );
INVX4TS U2363 ( .A(n8713), .Y(n8707) );
ADDFHX2TS U2364 ( .A(n4988), .B(n4987), .CI(n4986), .CO(n4992), .S(n4961) );
NAND2X2TS U2365 ( .A(n7248), .B(n7247), .Y(n7509) );
OAI21X1TS U2366 ( .A0(n8659), .A1(n8658), .B0(n8657), .Y(n8663) );
ADDFHX2TS U2367 ( .A(n3024), .B(n3023), .CI(n3022), .CO(n3486), .S(n3092) );
CLKMX2X2TS U2368 ( .A(n8617), .B(P_Sgf[8]), .S0(n8748), .Y(
Sgf_operation_n101) );
ADDFHX2TS U2369 ( .A(n6280), .B(n6279), .CI(n6278), .CO(n7207), .S(n7204) );
CLKMX2X2TS U2370 ( .A(n8648), .B(P_Sgf[7]), .S0(n8748), .Y(
Sgf_operation_n102) );
CLKMX2X2TS U2371 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(
n693), .Y(n408) );
ADDFHX2TS U2372 ( .A(n6634), .B(n6633), .CI(n6632), .CO(n6636), .S(n6638) );
CLKMX2X2TS U2373 ( .A(n8272), .B(Add_result[49]), .S0(n716), .Y(n423) );
OAI21X1TS U2374 ( .A0(n8659), .A1(n8623), .B0(n8622), .Y(n8628) );
ADDFHX2TS U2375 ( .A(n6089), .B(n6088), .CI(n6087), .CO(n6090), .S(n6078) );
CLKMX2X2TS U2376 ( .A(n8277), .B(Add_result[48]), .S0(n8396), .Y(n424) );
ADDFHX2TS U2377 ( .A(n5847), .B(n5846), .CI(n5845), .CO(n6095), .S(n6084) );
NAND2X4TS U2378 ( .A(n2617), .B(n2616), .Y(n7894) );
CLKMX2X2TS U2379 ( .A(n8613), .B(P_Sgf[6]), .S0(n8608), .Y(
Sgf_operation_n103) );
ADDFHX2TS U2380 ( .A(n5106), .B(n5105), .CI(n5104), .CO(n5217), .S(n5065) );
ADDFHX2TS U2381 ( .A(n5923), .B(n5922), .CI(n5921), .CO(n5960), .S(n5925) );
ADDFHX2TS U2382 ( .A(n5903), .B(n5902), .CI(n5901), .CO(n5962), .S(n5899) );
ADDFHX2TS U2383 ( .A(n5965), .B(n5964), .CI(n5963), .CO(n6006), .S(n5961) );
ADDFHX2TS U2384 ( .A(n4168), .B(n4167), .CI(n4166), .CO(n4277), .S(n4392) );
NAND2X6TS U2385 ( .A(n851), .B(n850), .Y(n8668) );
ADDFHX2TS U2386 ( .A(n6523), .B(n6522), .CI(n6521), .CO(n6571), .S(n6572) );
ADDFHX2TS U2387 ( .A(n4275), .B(n4274), .CI(n4273), .CO(n4377), .S(n4278) );
ADDFHX2TS U2388 ( .A(n5000), .B(n4999), .CI(n4998), .CO(n5017), .S(n5014) );
AO21X1TS U2389 ( .A0(n7324), .A1(n7323), .B0(n7322), .Y(n887) );
CLKMX2X2TS U2390 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(
n692), .Y(n409) );
ADDFHX2TS U2391 ( .A(n3629), .B(n3628), .CI(n3627), .CO(n3659), .S(n3530) );
ADDFHX2TS U2392 ( .A(n4281), .B(n4280), .CI(n4279), .CO(n4988), .S(n4380) );
ADDFHX2TS U2393 ( .A(n6083), .B(n6082), .CI(n6081), .CO(n6092), .S(n6087) );
ADDFHX2TS U2394 ( .A(n4973), .B(n4972), .CI(n4971), .CO(n4990), .S(n5001) );
ADDFHX2TS U2395 ( .A(n5253), .B(n5252), .CI(n5251), .CO(n5274), .S(n5255) );
CLKMX2X2TS U2396 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(
n692), .Y(n410) );
CLKMX2X2TS U2397 ( .A(n8596), .B(P_Sgf[4]), .S0(n777), .Y(Sgf_operation_n105) );
CLKMX2X2TS U2398 ( .A(n8282), .B(Add_result[47]), .S0(n8518), .Y(n425) );
ADDFHX2TS U2399 ( .A(n4356), .B(n4355), .CI(n4354), .CO(n4976), .S(n4279) );
CLKMX2X2TS U2400 ( .A(n8369), .B(Add_result[33]), .S0(n8396), .Y(n439) );
ADDFHX2TS U2401 ( .A(n4657), .B(n4656), .CI(n4655), .CO(n4860), .S(n4716) );
CLKMX2X2TS U2402 ( .A(n8580), .B(P_Sgf[3]), .S0(n774), .Y(Sgf_operation_n106) );
OAI21X1TS U2403 ( .A0(n7759), .A1(n7764), .B0(n7765), .Y(n7322) );
ADDFHX2TS U2404 ( .A(n3658), .B(n3657), .CI(n3656), .CO(n3845), .S(n3660) );
ADDFHX2TS U2405 ( .A(n5220), .B(n5219), .CI(n5218), .CO(n5276), .S(n5216) );
OAI21X1TS U2406 ( .A0(n8642), .A1(n8641), .B0(n8640), .Y(n8647) );
ADDFHX2TS U2407 ( .A(n4715), .B(n4714), .CI(n4713), .CO(n4721), .S(n4761) );
ADDFHX2TS U2408 ( .A(n3844), .B(n3843), .CI(n3842), .CO(n3936), .S(n3847) );
ADDFHX2TS U2409 ( .A(n5338), .B(n5337), .CI(n5336), .CO(n5364), .S(n5272) );
ADDFHX2TS U2410 ( .A(n2337), .B(n2336), .CI(n2335), .CO(n2345), .S(n2344) );
ADDFHX2TS U2411 ( .A(n2334), .B(n2333), .CI(n2332), .CO(n2347), .S(n2346) );
ADDFHX2TS U2412 ( .A(n3554), .B(n3553), .CI(n3552), .CO(n3734), .S(n3632) );
ADDFHX2TS U2413 ( .A(n1583), .B(n1582), .CI(n1581), .CO(n1584), .S(n1587) );
ADDFHX2TS U2414 ( .A(n5917), .B(n5916), .CI(n5915), .CO(n5964), .S(n5903) );
CLKMX2X2TS U2415 ( .A(n8591), .B(P_Sgf[0]), .S0(n775), .Y(Sgf_operation_n109) );
ADDFHX2TS U2416 ( .A(n2588), .B(n2587), .CI(n2586), .CO(n2589), .S(n2592) );
ADDFHX2TS U2417 ( .A(n2974), .B(n2973), .CI(n2972), .CO(n3428), .S(n2993) );
ADDFHX2TS U2418 ( .A(n6003), .B(n6002), .CI(n6001), .CO(n6577), .S(n6077) );
ADDFHX2TS U2419 ( .A(n2564), .B(n2563), .CI(n2562), .CO(n2584), .S(n2594) );
CLKMX2X2TS U2420 ( .A(n8589), .B(P_Sgf[1]), .S0(n774), .Y(Sgf_operation_n108) );
ADDFHX2TS U2421 ( .A(n5699), .B(n5698), .CI(n5697), .CO(n5902), .S(n5814) );
OAI21X1TS U2422 ( .A0(n8446), .A1(n8893), .B0(n8200), .Y(n353) );
ADDFHX2TS U2423 ( .A(n5767), .B(n5766), .CI(n5765), .CO(n5923), .S(n5816) );
ADDFHX2TS U2424 ( .A(n6000), .B(n5999), .CI(n5998), .CO(n6004), .S(n5929) );
ADDFHX2TS U2425 ( .A(n4793), .B(n4792), .CI(n4791), .CO(n4945), .S(n4785) );
CLKMX2X2TS U2426 ( .A(n8609), .B(P_Sgf[5]), .S0(n8595), .Y(
Sgf_operation_n104) );
ADDFHX2TS U2427 ( .A(n6604), .B(n6603), .CI(n6602), .CO(n6605), .S(n6578) );
CLKMX2X2TS U2428 ( .A(n8584), .B(P_Sgf[2]), .S0(n774), .Y(Sgf_operation_n107) );
AND2X2TS U2429 ( .A(n7698), .B(n7697), .Y(n908) );
ADDFHX2TS U2430 ( .A(n2766), .B(n2765), .CI(n2764), .CO(n2901), .S(n2801) );
ADDFHX2TS U2431 ( .A(n1804), .B(n1803), .CI(n1802), .CO(n2104), .S(n2103) );
CLKMX2X2TS U2432 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(
n693), .Y(n411) );
CLKMX2X2TS U2433 ( .A(n8374), .B(Add_result[32]), .S0(n8518), .Y(n440) );
OAI21X1TS U2434 ( .A0(n8446), .A1(n8895), .B0(n8195), .Y(n352) );
ADDFHX2TS U2435 ( .A(n5732), .B(n5731), .CI(n5730), .CO(n5901), .S(n5817) );
ADDFHX2TS U2436 ( .A(n3279), .B(n3278), .CI(n3277), .CO(n3554), .S(n3379) );
ADDFHX2TS U2437 ( .A(n5510), .B(n5509), .CI(n5508), .CO(n5544), .S(n5464) );
ADDFHX2TS U2438 ( .A(n1679), .B(n1678), .CI(n1677), .CO(n1633), .S(n2523) );
ADDFHX2TS U2439 ( .A(n5103), .B(n5102), .CI(n5101), .CO(n5212), .S(n5105) );
ADDFHX2TS U2440 ( .A(n2074), .B(n2073), .CI(n2072), .CO(n2094), .S(n2093) );
ADDFHX2TS U2441 ( .A(n2026), .B(n2025), .CI(n2024), .CO(n2100), .S(n2097) );
ADDFHX2TS U2442 ( .A(n2056), .B(n2055), .CI(n2054), .CO(n2096), .S(n2095) );
ADDFHX2TS U2443 ( .A(n1774), .B(n1773), .CI(n1772), .CO(n2106), .S(n2105) );
ADDFHX2TS U2444 ( .A(n4195), .B(n4194), .CI(n4193), .CO(n4301), .S(n4267) );
ADDFHX2TS U2445 ( .A(n2540), .B(n2539), .CI(n2538), .CO(n2566), .S(n2564) );
ADDFHX2TS U2446 ( .A(n6520), .B(n6519), .CI(n6518), .CO(n6525), .S(n6629) );
ADDFHX2TS U2447 ( .A(n4754), .B(n4753), .CI(n4752), .CO(n5000), .S(n4973) );
CLKMX2X2TS U2448 ( .A(n8389), .B(Add_result[30]), .S0(n8396), .Y(n442) );
CLKMX2X2TS U2449 ( .A(n8397), .B(Add_result[29]), .S0(n8396), .Y(n443) );
CLKMX2X2TS U2450 ( .A(n8422), .B(Add_result[25]), .S0(n8526), .Y(n447) );
ADDFHX1TS U2451 ( .A(n2689), .B(n2688), .CI(n2687), .CO(n2860), .S(n2787) );
ADDFHX2TS U2452 ( .A(n1751), .B(n1750), .CI(n1749), .CO(n2195), .S(n1773) );
CLKMX2X2TS U2453 ( .A(n8292), .B(Add_result[45]), .S0(n715), .Y(n427) );
OAI21X2TS U2454 ( .A0(n8607), .A1(n8603), .B0(n8604), .Y(n8610) );
ADDFHX2TS U2455 ( .A(n1158), .B(n1157), .CI(n1156), .CO(n1167), .S(n1237) );
ADDFHX2TS U2456 ( .A(n3870), .B(n3869), .CI(n3868), .CO(n4152), .S(n3852) );
ADDFHX2TS U2457 ( .A(n1208), .B(n1207), .CI(n1206), .CO(n1233), .S(n1235) );
ADDFHX2TS U2458 ( .A(n5620), .B(n5619), .CI(n5618), .CO(n6081), .S(n5543) );
ADDFHX2TS U2459 ( .A(n1230), .B(n1229), .CI(n1228), .CO(n1238), .S(n1575) );
ADDFHX2TS U2460 ( .A(n4943), .B(n4942), .CI(n4941), .CO(n5098), .S(n4948) );
ADDFHX2TS U2461 ( .A(n3604), .B(n3603), .CI(n3602), .CO(n3657), .S(n3629) );
ADDFHX2TS U2462 ( .A(n2561), .B(n2560), .CI(n2559), .CO(n2585), .S(n2587) );
CLKMX2X2TS U2463 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(
n692), .Y(n412) );
ADDFHX2TS U2464 ( .A(n2355), .B(n2354), .CI(n2353), .CO(n1677), .S(n2528) );
OAI21X1TS U2465 ( .A0(n8263), .A1(n8891), .B0(n8198), .Y(n8199) );
ADDFHX2TS U2466 ( .A(n3240), .B(n3239), .CI(n3238), .CO(n3547), .S(n3347) );
ADDFHX2TS U2467 ( .A(n3667), .B(n3666), .CI(n3665), .CO(n3758), .S(n3651) );
OAI2BB1X2TS U2468 ( .A0N(n1856), .A1N(n1855), .B0(n857), .Y(n1831) );
ADDFHX2TS U2469 ( .A(n2748), .B(n2747), .CI(n2746), .CO(n2768), .S(n2732) );
ADDFHX2TS U2470 ( .A(n2772), .B(n2771), .CI(n2770), .CO(n2899), .S(n2769) );
ADDFHX2TS U2471 ( .A(n3752), .B(n3751), .CI(n3750), .CO(n3851), .S(n3764) );
ADDFHX2TS U2472 ( .A(n1980), .B(n1979), .CI(n1978), .CO(n2016), .S(n2015) );
OAI211X1TS U2473 ( .A0(n8263), .A1(n8890), .B0(n8262), .C0(n8261), .Y(n8264)
);
ADDFHX2TS U2474 ( .A(n3965), .B(n3964), .CI(n3963), .CO(n4156), .S(n4153) );
OR2X2TS U2475 ( .A(n1937), .B(n1936), .Y(n892) );
CLKMX2X2TS U2476 ( .A(n8330), .B(Add_result[39]), .S0(n8396), .Y(n433) );
CLKMX2X2TS U2477 ( .A(n8427), .B(Add_result[24]), .S0(n8526), .Y(n448) );
CLKMX2X2TS U2478 ( .A(n8402), .B(Add_result[28]), .S0(n8526), .Y(n444) );
CLKMX2X2TS U2479 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(
n692), .Y(n413) );
OAI21X1TS U2480 ( .A0(n8263), .A1(n8892), .B0(n8193), .Y(n8194) );
CLKMX2X2TS U2481 ( .A(n8297), .B(Add_result[44]), .S0(n8396), .Y(n428) );
ADDFHX2TS U2482 ( .A(n2438), .B(n2437), .CI(n2436), .CO(n2474), .S(n2518) );
ADDFHX2TS U2483 ( .A(n3626), .B(n3625), .CI(n3624), .CO(n3650), .S(n3603) );
ADDFHX2TS U2484 ( .A(n3393), .B(n3392), .CI(n3391), .CO(n3376), .S(n3434) );
ADDFHX2TS U2485 ( .A(n1285), .B(n1284), .CI(n1283), .CO(n1272), .S(n1476) );
ADDFHX2TS U2486 ( .A(n4703), .B(n4702), .CI(n4701), .CO(n4717), .S(n4763) );
AO22X1TS U2487 ( .A0(n8763), .A1(Sgf_normalized_result[20]), .B0(
final_result_ieee[20]), .B1(n8764), .Y(n330) );
AO22X1TS U2488 ( .A0(Sgf_normalized_result[51]), .A1(n8838), .B0(
final_result_ieee[51]), .B1(n8837), .Y(n299) );
AO22X1TS U2489 ( .A0(n8761), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[10]), .B1(n8762), .Y(n340) );
AO22X1TS U2490 ( .A0(n8763), .A1(Sgf_normalized_result[21]), .B0(
final_result_ieee[21]), .B1(n8764), .Y(n329) );
AO22X1TS U2491 ( .A0(n8763), .A1(Sgf_normalized_result[16]), .B0(
final_result_ieee[16]), .B1(n8764), .Y(n334) );
ADDFHX1TS U2492 ( .A(n3313), .B(n3312), .CI(n3311), .CO(n3189), .S(n3340) );
AO22X1TS U2493 ( .A0(n8763), .A1(Sgf_normalized_result[15]), .B0(
final_result_ieee[15]), .B1(n8764), .Y(n335) );
AO22X1TS U2494 ( .A0(n8763), .A1(Sgf_normalized_result[17]), .B0(
final_result_ieee[17]), .B1(n8764), .Y(n333) );
AO22X1TS U2495 ( .A0(n8763), .A1(Sgf_normalized_result[14]), .B0(
final_result_ieee[14]), .B1(n8764), .Y(n336) );
AO22X1TS U2496 ( .A0(n8838), .A1(Sgf_normalized_result[22]), .B0(
final_result_ieee[22]), .B1(n8764), .Y(n328) );
AO22X1TS U2497 ( .A0(n8763), .A1(Sgf_normalized_result[18]), .B0(
final_result_ieee[18]), .B1(n8764), .Y(n332) );
AO22X1TS U2498 ( .A0(n8763), .A1(Sgf_normalized_result[13]), .B0(
final_result_ieee[13]), .B1(n8764), .Y(n337) );
ADDFHX2TS U2499 ( .A(n3387), .B(n3386), .CI(n3385), .CO(n3416), .S(n3443) );
AO22X1TS U2500 ( .A0(n8763), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[12]), .B1(n8762), .Y(n338) );
AO22X1TS U2501 ( .A0(n8763), .A1(Sgf_normalized_result[19]), .B0(
final_result_ieee[19]), .B1(n8764), .Y(n331) );
AO22X1TS U2502 ( .A0(n8761), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[11]), .B1(n8762), .Y(n339) );
AO22X1TS U2503 ( .A0(n8761), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n8762), .Y(n347) );
ADDFHX2TS U2504 ( .A(n4082), .B(n4081), .CI(n4080), .CO(n4268), .S(n4141) );
AO22X1TS U2505 ( .A0(n8761), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[7]), .B1(n8762), .Y(n343) );
ADDFHX2TS U2506 ( .A(n4362), .B(n4361), .CI(n4360), .CO(n4978), .S(n4325) );
OAI211X1TS U2507 ( .A0(n8752), .A1(n8894), .B0(n8197), .C0(n8504), .Y(n607)
);
AO22X1TS U2508 ( .A0(n8761), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n8762), .Y(n344) );
CLKMX2X2TS U2509 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(
n692), .Y(n414) );
CLKMX2X2TS U2510 ( .A(n8302), .B(Add_result[43]), .S0(n8518), .Y(n429) );
ADDFHX2TS U2511 ( .A(n4476), .B(n4475), .CI(n4474), .CO(n4454), .S(n4701) );
AO22X1TS U2512 ( .A0(n8761), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[4]), .B1(n8762), .Y(n346) );
AO22X1TS U2513 ( .A0(n8761), .A1(Sgf_normalized_result[5]), .B0(
final_result_ieee[5]), .B1(n8762), .Y(n345) );
CLKMX2X2TS U2514 ( .A(n8323), .B(Add_result[40]), .S0(n8396), .Y(n432) );
CLKMX2X2TS U2515 ( .A(n8349), .B(Add_result[36]), .S0(n715), .Y(n436) );
CLKMX2X2TS U2516 ( .A(n8414), .B(Add_result[26]), .S0(n8526), .Y(n446) );
CLKMX2X2TS U2517 ( .A(n8409), .B(Add_result[27]), .S0(n8526), .Y(n445) );
NOR2X4TS U2518 ( .A(n1905), .B(n1904), .Y(n8643) );
AO22X1TS U2519 ( .A0(n8761), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[8]), .B1(n8762), .Y(n342) );
ADDFHX2TS U2520 ( .A(n1471), .B(n1470), .CI(n1469), .CO(n2743), .S(n1435) );
CLKMX2X2TS U2521 ( .A(n8433), .B(Add_result[23]), .S0(n8518), .Y(n449) );
ADDFHX2TS U2522 ( .A(n1146), .B(n1145), .CI(n1144), .CO(n1337), .S(n1127) );
ADDFHX2TS U2523 ( .A(n3996), .B(n3995), .CI(n3994), .CO(n4188), .S(n4155) );
AO22X1TS U2524 ( .A0(n8761), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[9]), .B1(n8762), .Y(n341) );
XOR2X2TS U2525 ( .A(n2257), .B(n863), .Y(n862) );
AO22X1TS U2526 ( .A0(Sgf_normalized_result[48]), .A1(n8836), .B0(
final_result_ieee[48]), .B1(n8835), .Y(n302) );
AO22X1TS U2527 ( .A0(Sgf_normalized_result[39]), .A1(n8834), .B0(
final_result_ieee[39]), .B1(n8835), .Y(n311) );
CLKMX2X2TS U2528 ( .A(n8497), .B(Add_result[13]), .S0(n8518), .Y(n459) );
AO22X1TS U2529 ( .A0(Sgf_normalized_result[47]), .A1(n8836), .B0(
final_result_ieee[47]), .B1(n8835), .Y(n303) );
AOI2BB1X1TS U2530 ( .A0N(n8219), .A1N(n8218), .B0(n8768), .Y(n606) );
AO22X1TS U2531 ( .A0(Sgf_normalized_result[0]), .A1(n8179), .B0(
final_result_ieee[0]), .B1(n8833), .Y(n350) );
AO22X1TS U2532 ( .A0(Sgf_normalized_result[49]), .A1(n8836), .B0(
final_result_ieee[49]), .B1(n8837), .Y(n301) );
AO22X1TS U2533 ( .A0(Sgf_normalized_result[50]), .A1(n8836), .B0(
final_result_ieee[50]), .B1(n8837), .Y(n300) );
AO22X1TS U2534 ( .A0(Sgf_normalized_result[1]), .A1(n8179), .B0(
final_result_ieee[1]), .B1(n8833), .Y(n349) );
AO22X1TS U2535 ( .A0(Sgf_normalized_result[38]), .A1(n8834), .B0(
final_result_ieee[38]), .B1(n8833), .Y(n312) );
AO21X1TS U2536 ( .A0(Sgf_normalized_result[52]), .A1(n8384), .B0(n8258), .Y(
n473) );
NOR2X1TS U2537 ( .A(n8478), .B(n8866), .Y(n8472) );
AO22X1TS U2538 ( .A0(Sgf_normalized_result[37]), .A1(n8834), .B0(
final_result_ieee[37]), .B1(n8833), .Y(n313) );
ADDHX1TS U2539 ( .A(n3744), .B(n3743), .CO(n3870), .S(n3741) );
CLKMX2X2TS U2540 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(
n693), .Y(n416) );
AO22X1TS U2541 ( .A0(Sgf_normalized_result[34]), .A1(n8834), .B0(
final_result_ieee[34]), .B1(n8833), .Y(n316) );
AO22X1TS U2542 ( .A0(Sgf_normalized_result[42]), .A1(n8836), .B0(
final_result_ieee[42]), .B1(n8835), .Y(n308) );
CLKMX2X2TS U2543 ( .A(Data_MX[51]), .B(n630), .S0(n8232), .Y(n590) );
ADDFHX1TS U2544 ( .A(n5322), .B(n5321), .CI(n5320), .CO(n5427), .S(n5355) );
AO22X1TS U2545 ( .A0(Sgf_normalized_result[41]), .A1(n8836), .B0(
final_result_ieee[41]), .B1(n8835), .Y(n309) );
AO22X1TS U2546 ( .A0(Sgf_normalized_result[43]), .A1(n8836), .B0(
final_result_ieee[43]), .B1(n8835), .Y(n307) );
NOR2X1TS U2547 ( .A(n8348), .B(n8870), .Y(n8343) );
AO22X1TS U2548 ( .A0(Sgf_normalized_result[35]), .A1(n8834), .B0(
final_result_ieee[35]), .B1(n8833), .Y(n315) );
AO22X1TS U2549 ( .A0(Sgf_normalized_result[33]), .A1(n8834), .B0(
final_result_ieee[33]), .B1(n8833), .Y(n317) );
CLKMX2X2TS U2550 ( .A(n8359), .B(Add_result[34]), .S0(n8518), .Y(n438) );
AO22X1TS U2551 ( .A0(Sgf_normalized_result[44]), .A1(n8836), .B0(
final_result_ieee[44]), .B1(n8835), .Y(n306) );
CLKMX2X2TS U2552 ( .A(n8307), .B(Add_result[42]), .S0(n715), .Y(n430) );
CLKMX2X2TS U2553 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(
n693), .Y(n415) );
AO22X1TS U2554 ( .A0(Sgf_normalized_result[36]), .A1(n8834), .B0(
final_result_ieee[36]), .B1(n8837), .Y(n314) );
AO22X1TS U2555 ( .A0(Sgf_normalized_result[45]), .A1(n8836), .B0(
final_result_ieee[45]), .B1(n8835), .Y(n305) );
AO22X1TS U2556 ( .A0(Sgf_normalized_result[32]), .A1(n8834), .B0(
final_result_ieee[32]), .B1(n8833), .Y(n318) );
CLKMX2X2TS U2557 ( .A(n8458), .B(Add_result[19]), .S0(n8518), .Y(n453) );
AO22X1TS U2558 ( .A0(Sgf_normalized_result[40]), .A1(n8834), .B0(
final_result_ieee[40]), .B1(n8835), .Y(n310) );
AO22X1TS U2559 ( .A0(Sgf_normalized_result[31]), .A1(n8834), .B0(
final_result_ieee[31]), .B1(n8833), .Y(n319) );
CLKMX2X2TS U2560 ( .A(n8485), .B(Add_result[15]), .S0(n8832), .Y(n457) );
CLKMX2X2TS U2561 ( .A(n8490), .B(Add_result[14]), .S0(n8396), .Y(n458) );
AO22X1TS U2562 ( .A0(Sgf_normalized_result[46]), .A1(n8836), .B0(
final_result_ieee[46]), .B1(n8835), .Y(n304) );
ADDFHX1TS U2563 ( .A(n5298), .B(n5297), .CI(n5296), .CO(n5402), .S(n5310) );
OR2X2TS U2564 ( .A(n1872), .B(n1871), .Y(n893) );
ADDFHX2TS U2565 ( .A(n4642), .B(n4641), .CI(n4640), .CO(n4602), .S(n4697) );
OAI31XLTS U2566 ( .A0(FS_Module_state_reg[1]), .A1(n8182), .A2(n8847), .B0(
n8157), .Y(n605) );
CLKMX2X2TS U2567 ( .A(n8527), .B(Add_result[9]), .S0(n715), .Y(n463) );
NOR2X4TS U2568 ( .A(FSM_selector_C), .B(n8192), .Y(n8390) );
ADDFHX1TS U2569 ( .A(n2199), .B(n2198), .CI(n2197), .CO(n2286), .S(n2232) );
ADDFHX1TS U2570 ( .A(n3780), .B(n3779), .CI(n3778), .CO(n3890), .S(n3825) );
ADDFHX1TS U2571 ( .A(n1100), .B(n1099), .CI(n1098), .CO(n1149), .S(n1065) );
ADDFHX2TS U2572 ( .A(n4423), .B(n4422), .CI(n4421), .CO(n4510), .S(n4624) );
ADDFHX1TS U2573 ( .A(n5644), .B(n5643), .CI(n5642), .CO(n5648), .S(n5651) );
ADDFHX1TS U2574 ( .A(n3910), .B(n3909), .CI(n3908), .CO(n4142), .S(n3911) );
ADDFHX1TS U2575 ( .A(n4569), .B(n4568), .CI(n4567), .CO(n4826), .S(n4507) );
OR2X2TS U2576 ( .A(n8830), .B(n8756), .Y(n671) );
INVX12TS U2577 ( .A(n771), .Y(n679) );
NOR2X1TS U2578 ( .A(n3127), .B(n1386), .Y(n1388) );
AO21X1TS U2579 ( .A0(n6772), .A1(n7173), .B0(n907), .Y(n7182) );
NOR2X1TS U2580 ( .A(n8462), .B(n8865), .Y(n8456) );
BUFX8TS U2581 ( .A(n2785), .Y(n2979) );
CLKMX2X2TS U2582 ( .A(n8532), .B(Add_result[8]), .S0(n8396), .Y(n464) );
NOR2X1TS U2583 ( .A(n8502), .B(n8867), .Y(n8496) );
BUFX12TS U2584 ( .A(n2884), .Y(n4032) );
CLKMX2X2TS U2585 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n8750), .Y(n497) );
CLKMX2X2TS U2586 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n8235), .Y(n501) );
CLKMX2X2TS U2587 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n8234), .Y(n503) );
CLKMX2X2TS U2588 ( .A(Data_MX[17]), .B(n756), .S0(n8230), .Y(n556) );
CLKMX2X2TS U2589 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n8220), .Y(n500) );
CLKMX2X2TS U2590 ( .A(Data_MX[46]), .B(Op_MX[46]), .S0(n8235), .Y(n585) );
CLKMX2X2TS U2591 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n8220), .Y(n502) );
CLKMX2X2TS U2592 ( .A(Data_MY[54]), .B(Op_MY[54]), .S0(n8228), .Y(n529) );
CLKMX2X2TS U2593 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n8220), .Y(n496) );
CLKMX2X2TS U2594 ( .A(Data_MX[5]), .B(n801), .S0(n8750), .Y(n544) );
CLKMX2X2TS U2595 ( .A(Data_MX[55]), .B(Op_MX[55]), .S0(n8234), .Y(n594) );
CLKMX2X2TS U2596 ( .A(Data_MX[60]), .B(Op_MX[60]), .S0(n8235), .Y(n599) );
CLKMX2X2TS U2597 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n8750), .Y(n541) );
CLKMX2X2TS U2598 ( .A(Data_MX[59]), .B(Op_MX[59]), .S0(n8750), .Y(n598) );
CLKMX2X2TS U2599 ( .A(Data_MX[56]), .B(Op_MX[56]), .S0(n8220), .Y(n595) );
CLKMX2X2TS U2600 ( .A(Data_MX[7]), .B(n686), .S0(n8220), .Y(n546) );
AO22X1TS U2601 ( .A0(n8773), .A1(Data_MX[63]), .B0(n8220), .B1(Op_MX[63]),
.Y(n538) );
CLKMX2X2TS U2602 ( .A(Data_MX[58]), .B(Op_MX[58]), .S0(n8235), .Y(n597) );
CLKMX2X2TS U2603 ( .A(Data_MX[3]), .B(n8212), .S0(n8750), .Y(n542) );
CLKMX2X2TS U2604 ( .A(Data_MX[54]), .B(Op_MX[54]), .S0(n8220), .Y(n593) );
CLKMX2X2TS U2605 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n8234), .Y(n549) );
CLKMX2X2TS U2606 ( .A(n8549), .B(Add_result[5]), .S0(n8518), .Y(n467) );
CLKMX2X2TS U2607 ( .A(Data_MX[53]), .B(Op_MX[53]), .S0(n8228), .Y(n592) );
CLKMX2X2TS U2608 ( .A(Data_MY[33]), .B(Op_MY[33]), .S0(n8220), .Y(n508) );
CLKMX2X2TS U2609 ( .A(Data_MY[59]), .B(Op_MY[59]), .S0(n8232), .Y(n534) );
CLKMX2X2TS U2610 ( .A(Data_MY[32]), .B(Op_MY[32]), .S0(n8228), .Y(n507) );
CLKMX2X2TS U2611 ( .A(Data_MY[55]), .B(Op_MY[55]), .S0(n8228), .Y(n530) );
CLKMX2X2TS U2612 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n8750), .Y(n543) );
CLKMX2X2TS U2613 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n8228), .Y(n506) );
CLKMX2X2TS U2614 ( .A(Data_MX[50]), .B(Op_MX[50]), .S0(n8234), .Y(n589) );
CLKMX2X2TS U2615 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n8220), .Y(n505) );
CLKMX2X2TS U2616 ( .A(Data_MY[60]), .B(Op_MY[60]), .S0(n8228), .Y(n535) );
CLKMX2X2TS U2617 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n8750), .Y(n504) );
CLKMX2X2TS U2618 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n8750), .Y(n486) );
CLKMX2X2TS U2619 ( .A(Data_MX[42]), .B(Op_MX[42]), .S0(n8232), .Y(n581) );
CLKMX2X2TS U2620 ( .A(Data_MX[43]), .B(n8810), .S0(n8235), .Y(n582) );
CLKMX2X2TS U2621 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n8232), .Y(n483) );
CLKMX2X2TS U2622 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n8220), .Y(n482) );
CLKMX2X2TS U2623 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n8750), .Y(n481) );
CLKMX2X2TS U2624 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n8235), .Y(n480) );
CLKMX2X2TS U2625 ( .A(Data_MY[3]), .B(n8236), .S0(n8751), .Y(n478) );
CLKMX2X2TS U2626 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n8772), .Y(n477) );
CLKMX2X2TS U2627 ( .A(Data_MX[49]), .B(n8214), .S0(n8234), .Y(n588) );
CLKMX2X2TS U2628 ( .A(Data_MY[62]), .B(Op_MY[62]), .S0(n8228), .Y(n537) );
BUFX12TS U2629 ( .A(n745), .Y(n4494) );
CLKMX2X2TS U2630 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n8232), .Y(n475) );
CLKMX2X2TS U2631 ( .A(Data_MY[57]), .B(Op_MY[57]), .S0(n8235), .Y(n532) );
CLKMX2X2TS U2632 ( .A(Data_MX[52]), .B(Op_MX[52]), .S0(n8228), .Y(n591) );
OR2X2TS U2633 ( .A(n1860), .B(n1859), .Y(n894) );
AO21X1TS U2634 ( .A0(n8180), .A1(FSM_selector_B[0]), .B0(n8176), .Y(n418) );
CLKMX2X2TS U2635 ( .A(Data_MX[62]), .B(Op_MX[62]), .S0(n8750), .Y(n601) );
CLKMX2X2TS U2636 ( .A(Data_MX[61]), .B(Op_MX[61]), .S0(n8228), .Y(n600) );
CLKMX2X2TS U2637 ( .A(Data_MX[57]), .B(Op_MX[57]), .S0(n8228), .Y(n596) );
CLKMX2X2TS U2638 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n8232), .Y(n547) );
OAI21X1TS U2639 ( .A0(n8526), .A1(Sgf_normalized_result[2]), .B0(n8181), .Y(
n470) );
NOR2X1TS U2640 ( .A(n5228), .B(n1467), .Y(n1387) );
BUFX6TS U2641 ( .A(n5706), .Y(n6301) );
CLKMX2X2TS U2642 ( .A(n8543), .B(Add_result[6]), .S0(n715), .Y(n466) );
CLKMX2X2TS U2643 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(n8235), .Y(n490) );
CLKMX2X2TS U2644 ( .A(Data_MY[53]), .B(Op_MY[53]), .S0(n8234), .Y(n528) );
CLKMX2X2TS U2645 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n8235), .Y(n494) );
CLKMX2X2TS U2646 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n8232), .Y(n491) );
CLKMX2X2TS U2647 ( .A(Data_MY[12]), .B(n696), .S0(n8234), .Y(n487) );
CLKMX2X2TS U2648 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n8232), .Y(n488) );
XOR2X2TS U2649 ( .A(n2132), .B(n686), .Y(n856) );
CLKMX2X2TS U2650 ( .A(Data_MY[47]), .B(Op_MY[47]), .S0(n8225), .Y(n522) );
CLKMX2X2TS U2651 ( .A(Data_MY[34]), .B(Op_MY[34]), .S0(n8231), .Y(n509) );
CLKMX2X2TS U2652 ( .A(Data_MY[35]), .B(Op_MY[35]), .S0(n8231), .Y(n510) );
NAND2BX1TS U2653 ( .AN(n3067), .B(n4000), .Y(n1883) );
BUFX16TS U2654 ( .A(n6456), .Y(n3866) );
CLKMX2X2TS U2655 ( .A(Data_MY[48]), .B(Op_MY[48]), .S0(n8227), .Y(n523) );
CLKMX2X2TS U2656 ( .A(Data_MY[36]), .B(Op_MY[36]), .S0(n8231), .Y(n511) );
CLKMX2X2TS U2657 ( .A(Data_MY[46]), .B(Op_MY[46]), .S0(n8222), .Y(n521) );
CLKMX2X2TS U2658 ( .A(Data_MY[37]), .B(Op_MY[37]), .S0(n8231), .Y(n512) );
CLKMX2X2TS U2659 ( .A(Data_MY[45]), .B(Op_MY[45]), .S0(n8230), .Y(n520) );
CLKMX2X2TS U2660 ( .A(Data_MY[38]), .B(Op_MY[38]), .S0(n8231), .Y(n513) );
CLKMX2X2TS U2661 ( .A(Data_MY[44]), .B(Op_MY[44]), .S0(n8227), .Y(n519) );
CLKMX2X2TS U2662 ( .A(Data_MY[39]), .B(Op_MY[39]), .S0(n8231), .Y(n514) );
NAND2X6TS U2663 ( .A(n3047), .B(n3046), .Y(n6666) );
CLKMX2X2TS U2664 ( .A(Data_MY[40]), .B(Op_MY[40]), .S0(n8231), .Y(n515) );
INVX12TS U2665 ( .A(n754), .Y(n755) );
CLKMX2X2TS U2666 ( .A(Data_MY[42]), .B(Op_MY[42]), .S0(n8231), .Y(n517) );
CLKMX2X2TS U2667 ( .A(Data_MY[43]), .B(Op_MY[43]), .S0(n8231), .Y(n518) );
NOR2X1TS U2668 ( .A(n8542), .B(n8868), .Y(n8537) );
NAND2BX1TS U2669 ( .AN(n3254), .B(n825), .Y(n1680) );
NAND2BX1TS U2670 ( .AN(n3067), .B(n801), .Y(n1876) );
INVX4TS U2671 ( .A(n8773), .Y(n8228) );
NAND2BX1TS U2672 ( .AN(n3254), .B(n8804), .Y(n2121) );
NAND3X1TS U2673 ( .A(n8186), .B(FS_Module_state_reg[1]), .C(
FSM_add_overflow_flag), .Y(n5162) );
CLKMX2X2TS U2674 ( .A(n8558), .B(Add_result[3]), .S0(n715), .Y(n469) );
INVX4TS U2675 ( .A(n8773), .Y(n8232) );
CLKMX2X2TS U2676 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n8225), .Y(n553) );
INVX4TS U2677 ( .A(n8773), .Y(n8750) );
NAND4X1TS U2678 ( .A(n8154), .B(n8153), .C(n8152), .D(n8151), .Y(n8156) );
NAND2BX1TS U2679 ( .AN(n3254), .B(n4681), .Y(n1909) );
INVX4TS U2680 ( .A(n8773), .Y(n8234) );
CLKMX2X2TS U2681 ( .A(Data_MX[32]), .B(Op_MX[32]), .S0(n8225), .Y(n571) );
CLKMX2X2TS U2682 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n8222), .Y(n565) );
CLKMX2X2TS U2683 ( .A(n8554), .B(Add_result[4]), .S0(n715), .Y(n468) );
INVX12TS U2684 ( .A(n7012), .Y(n719) );
CLKMX2X2TS U2685 ( .A(Data_MX[13]), .B(n742), .S0(n8230), .Y(n552) );
CLKMX2X2TS U2686 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n8227), .Y(n555) );
CLKMX2X2TS U2687 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n8222), .Y(n551) );
CLKMX2X2TS U2688 ( .A(Data_MX[19]), .B(n8812), .S0(n8225), .Y(n558) );
CLKMX2X2TS U2689 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n8222), .Y(n557) );
CLKMX2X2TS U2690 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n8227), .Y(n559) );
CLKMX2X2TS U2691 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n8227), .Y(n567) );
CLKMX2X2TS U2692 ( .A(Data_MX[21]), .B(n8804), .S0(n8222), .Y(n560) );
CLKMX2X2TS U2693 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n8230), .Y(n563) );
CLKMX2X2TS U2694 ( .A(Data_MX[38]), .B(Op_MX[38]), .S0(n8222), .Y(n577) );
CLKMX2X2TS U2695 ( .A(Data_MX[23]), .B(n5679), .S0(n8230), .Y(n562) );
CLKMX2X2TS U2696 ( .A(Data_MX[41]), .B(n8221), .S0(n8227), .Y(n580) );
CLKMX2X2TS U2697 ( .A(Data_MX[25]), .B(n694), .S0(n8227), .Y(n564) );
CLKMX2X2TS U2698 ( .A(Data_MX[27]), .B(n5489), .S0(n8225), .Y(n566) );
CLKMX2X2TS U2699 ( .A(Data_MX[29]), .B(n749), .S0(n8225), .Y(n568) );
CLKMX2X2TS U2700 ( .A(Data_MX[37]), .B(n8809), .S0(n8225), .Y(n576) );
CLKMX2X2TS U2701 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n8230), .Y(n569) );
CLKMX2X2TS U2702 ( .A(Data_MX[31]), .B(n5874), .S0(n8222), .Y(n570) );
NAND2BX1TS U2703 ( .AN(n3067), .B(n4850), .Y(n1783) );
AOI2BB2X1TS U2704 ( .B0(n8895), .B1(n8832), .A0N(n715), .A1N(
Sgf_normalized_result[0]), .Y(n472) );
BUFX12TS U2705 ( .A(n6986), .Y(n6677) );
OAI31XLTS U2706 ( .A0(n8830), .A1(n8457), .A2(n8941), .B0(n8180), .Y(n417)
);
CLKMX2X2TS U2707 ( .A(Data_MY[51]), .B(Op_MY[51]), .S0(n8225), .Y(n526) );
AOI2BB2X1TS U2708 ( .B0(n8893), .B1(n8518), .A0N(n715), .A1N(
Sgf_normalized_result[1]), .Y(n471) );
CLKMX2X2TS U2709 ( .A(Data_MX[35]), .B(Op_MX[35]), .S0(n8222), .Y(n574) );
CLKMX2X2TS U2710 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n8227), .Y(n561) );
CLKMX2X2TS U2711 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n8227), .Y(n539) );
CLKMX2X2TS U2712 ( .A(Data_MX[40]), .B(Op_MX[40]), .S0(n8225), .Y(n579) );
CLKMX2X2TS U2713 ( .A(Data_MX[33]), .B(n6168), .S0(n8230), .Y(n572) );
CLKMX2X2TS U2714 ( .A(Data_MX[15]), .B(n4850), .S0(n8225), .Y(n554) );
CLKMX2X2TS U2715 ( .A(Data_MX[34]), .B(Op_MX[34]), .S0(n8227), .Y(n573) );
CLKMX2X2TS U2716 ( .A(Data_MY[49]), .B(Op_MY[49]), .S0(n8230), .Y(n524) );
CLKMX2X2TS U2717 ( .A(Data_MX[1]), .B(n784), .S0(n8230), .Y(n540) );
BUFX12TS U2718 ( .A(n4405), .Y(n736) );
INVX12TS U2719 ( .A(n6154), .Y(n5893) );
INVX12TS U2720 ( .A(n5189), .Y(n4570) );
NOR2X1TS U2721 ( .A(n8553), .B(Sgf_normalized_result[4]), .Y(n8548) );
NAND2BX1TS U2722 ( .AN(n3254), .B(n8221), .Y(n2666) );
BUFX8TS U2723 ( .A(n1055), .Y(n634) );
NAND2BX1TS U2724 ( .AN(n3067), .B(n6931), .Y(n3068) );
INVX4TS U2725 ( .A(n8457), .Y(n8396) );
NAND2BX1TS U2726 ( .AN(n3642), .B(n6987), .Y(n2835) );
NAND2BX1TS U2727 ( .AN(n3254), .B(n678), .Y(n1709) );
CLKMX2X2TS U2728 ( .A(Op_MX[55]), .B(exp_oper_result[3]), .S0(n691), .Y(
S_Oper_A_exp[3]) );
CLKMX2X2TS U2729 ( .A(Op_MX[57]), .B(exp_oper_result[5]), .S0(n691), .Y(
S_Oper_A_exp[5]) );
NAND2BX1TS U2730 ( .AN(n3067), .B(n6069), .Y(n1669) );
NAND2BX1TS U2731 ( .AN(n3254), .B(n779), .Y(n1170) );
NAND2BX1TS U2732 ( .AN(n3067), .B(n4412), .Y(n1967) );
INVX12TS U2733 ( .A(n6427), .Y(n6054) );
NAND2BX1TS U2734 ( .AN(n3605), .B(n6364), .Y(n1510) );
AND2X4TS U2735 ( .A(FS_Module_state_reg[3]), .B(n8178), .Y(n8842) );
NAND2BX1TS U2736 ( .AN(n3067), .B(n5874), .Y(n1262) );
NAND2BX1TS U2737 ( .AN(n3642), .B(n6383), .Y(n971) );
INVX4TS U2738 ( .A(n8457), .Y(n8518) );
BUFX12TS U2739 ( .A(n3928), .Y(n5130) );
NAND2BX1TS U2740 ( .AN(n8769), .B(P_Sgf[105]), .Y(n8180) );
INVX4TS U2741 ( .A(n8457), .Y(n715) );
NAND2BX1TS U2742 ( .AN(n3254), .B(n3203), .Y(n1858) );
CLKMX2X2TS U2743 ( .A(Op_MX[58]), .B(exp_oper_result[6]), .S0(n691), .Y(
S_Oper_A_exp[6]) );
BUFX20TS U2744 ( .A(n4424), .Y(n4938) );
INVX6TS U2745 ( .A(n1168), .Y(n8807) );
INVX2TS U2746 ( .A(n8188), .Y(n8189) );
INVX12TS U2747 ( .A(n6643), .Y(n5203) );
INVX12TS U2748 ( .A(n5533), .Y(n8811) );
INVX12TS U2749 ( .A(n6029), .Y(n3774) );
INVX12TS U2750 ( .A(n5626), .Y(n5392) );
NOR2X1TS U2751 ( .A(n8420), .B(n8240), .Y(n8241) );
INVX12TS U2752 ( .A(n957), .Y(n4404) );
INVX12TS U2753 ( .A(n4669), .Y(n6296) );
INVX12TS U2754 ( .A(n5347), .Y(n2878) );
INVX12TS U2755 ( .A(n4513), .Y(n4405) );
INVX8TS U2756 ( .A(n6105), .Y(n6133) );
INVX12TS U2757 ( .A(n6416), .Y(n3877) );
NOR2X1TS U2758 ( .A(n8470), .B(n8247), .Y(n8248) );
NAND2BX1TS U2759 ( .AN(n3067), .B(n742), .Y(n1821) );
INVX12TS U2760 ( .A(n5347), .Y(n4882) );
INVX12TS U2761 ( .A(n7139), .Y(n6371) );
NOR2X1TS U2762 ( .A(Sgf_normalized_result[4]), .B(Sgf_normalized_result[5]),
.Y(n8250) );
BUFX8TS U2763 ( .A(n3046), .Y(n637) );
INVX12TS U2764 ( .A(Op_MX[13]), .Y(n5326) );
INVX12TS U2765 ( .A(Op_MX[49]), .Y(n4514) );
NOR3X2TS U2766 ( .A(n8847), .B(FS_Module_state_reg[2]), .C(
FS_Module_state_reg[1]), .Y(n8207) );
CLKMX2X2TS U2767 ( .A(Op_MX[62]), .B(exp_oper_result[10]), .S0(
FSM_selector_A), .Y(S_Oper_A_exp[10]) );
CLKMX2X2TS U2768 ( .A(Op_MX[61]), .B(exp_oper_result[9]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[9]) );
INVX8TS U2769 ( .A(n668), .Y(n762) );
CLKMX2X2TS U2770 ( .A(Op_MX[60]), .B(exp_oper_result[8]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[8]) );
CLKMX2X2TS U2771 ( .A(Op_MX[59]), .B(exp_oper_result[7]), .S0(FSM_selector_A), .Y(S_Oper_A_exp[7]) );
INVX12TS U2772 ( .A(Op_MX[41]), .Y(n6954) );
INVX12TS U2773 ( .A(Op_MX[17]), .Y(n5665) );
NOR2X4TS U2774 ( .A(n8848), .B(FS_Module_state_reg[3]), .Y(n8188) );
INVX12TS U2775 ( .A(Op_MY[45]), .Y(n7051) );
BUFX12TS U2776 ( .A(n967), .Y(n640) );
BUFX12TS U2777 ( .A(n950), .Y(n641) );
BUFX8TS U2778 ( .A(n964), .Y(n642) );
INVX6TS U2779 ( .A(n6152), .Y(n643) );
XNOR2X2TS U2780 ( .A(n7168), .B(n779), .Y(n6303) );
NOR2X4TS U2781 ( .A(n7311), .B(n914), .Y(n7795) );
OAI22X2TS U2782 ( .A0(n6125), .A1(n6673), .B0(n6746), .B1(n6747), .Y(n6698)
);
OAI21X2TS U2783 ( .A0(n7807), .A1(n7474), .B0(n7473), .Y(n7475) );
ADDFX2TS U2784 ( .A(n6544), .B(n6543), .CI(n6542), .CO(n6552), .S(n6582) );
ADDFHX2TS U2785 ( .A(n6399), .B(n6398), .CI(n6397), .CO(n7205), .S(n7202) );
ADDFHX2TS U2786 ( .A(n6277), .B(n6276), .CI(n6275), .CO(n6278), .S(n6397) );
ADDFX2TS U2787 ( .A(n6233), .B(n6232), .CI(n6231), .CO(n6280), .S(n6275) );
ADDFHX2TS U2788 ( .A(n5430), .B(n5429), .CI(n5428), .CO(n5537), .S(n5423) );
AOI21X2TS U2789 ( .A0(n7711), .A1(n7568), .B0(n7567), .Y(n7774) );
AOI21X2TS U2790 ( .A0(n7691), .A1(n7698), .B0(n7268), .Y(n7269) );
OAI21X2TS U2791 ( .A0(n7671), .A1(n7667), .B0(n7672), .Y(n7691) );
OAI22X2TS U2792 ( .A0(n4032), .A1(n3835), .B0(n3931), .B1(n4259), .Y(n3914)
);
OAI21X2TS U2793 ( .A0(n8126), .A1(n8125), .B0(n8124), .Y(n8127) );
OAI21X1TS U2794 ( .A0(n8061), .A1(n8034), .B0(n8033), .Y(n8037) );
OAI21X1TS U2795 ( .A0(n8061), .A1(n7917), .B0(n7916), .Y(n7922) );
OAI21X1TS U2796 ( .A0(n8061), .A1(n7929), .B0(n7928), .Y(n7934) );
OAI21X1TS U2797 ( .A0(n8061), .A1(n8060), .B0(n8059), .Y(n8064) );
OAI21X1TS U2798 ( .A0(n8061), .A1(n8026), .B0(n7902), .Y(n8030) );
OAI21X1TS U2799 ( .A0(n8061), .A1(n8044), .B0(n8043), .Y(n8049) );
OAI21X1TS U2800 ( .A0(n8061), .A1(n8052), .B0(n8051), .Y(n8057) );
NAND2X4TS U2801 ( .A(n7897), .B(n3499), .Y(n3527) );
OAI21X2TS U2802 ( .A0(n7709), .A1(n8595), .B0(n7708), .Y(Sgf_operation_n9)
);
OAI21X1TS U2803 ( .A0(n7440), .A1(n8595), .B0(n7439), .Y(Sgf_operation_n26)
);
OAI21X1TS U2804 ( .A0(n7618), .A1(n682), .B0(n7617), .Y(Sgf_operation_n42)
);
OAI21X2TS U2805 ( .A0(n7688), .A1(n682), .B0(n7687), .Y(Sgf_operation_n14)
);
OAI21X4TS U2806 ( .A0(n7666), .A1(n8595), .B0(n7665), .Y(Sgf_operation_n8)
);
OAI31XLTS U2807 ( .A0(FS_Module_state_reg[1]), .A1(n8177), .A2(n8190), .B0(
n8850), .Y(n602) );
OAI22X2TS U2808 ( .A0(n6795), .A1(n8809), .B0(n6794), .B1(n6825), .Y(n6833)
);
AOI21X2TS U2809 ( .A0(n676), .A1(n7327), .B0(n7326), .Y(n7337) );
ADDFHX2TS U2810 ( .A(n4803), .B(n4802), .CI(n4801), .CO(n4928), .S(n4764) );
OAI21X1TS U2811 ( .A0(n7622), .A1(n7621), .B0(n7620), .Y(n7623) );
AOI21X2TS U2812 ( .A0(n7584), .A1(n7583), .B0(n7582), .Y(n7622) );
AOI21X1TS U2813 ( .A0(n7428), .A1(n7456), .B0(n7427), .Y(n7429) );
AOI21X2TS U2814 ( .A0(n7711), .A1(n7496), .B0(n7495), .Y(n7506) );
AOI21X2TS U2815 ( .A0(n710), .A1(n8069), .B0(n8068), .Y(n8072) );
OAI21X1TS U2816 ( .A0(n7542), .A1(n777), .B0(n7541), .Y(Sgf_operation_n21)
);
ADDFHX2TS U2817 ( .A(n4597), .B(n4596), .CI(n4595), .CO(n4603), .S(n4714) );
XNOR2X1TS U2818 ( .A(n6667), .B(n5892), .Y(n5502) );
XNOR2X1TS U2819 ( .A(n1349), .B(n5892), .Y(n1411) );
INVX6TS U2820 ( .A(n6917), .Y(n6823) );
ADDFHX4TS U2821 ( .A(n2522), .B(n2521), .CI(n2520), .CO(n2607), .S(n2606) );
XNOR2X2TS U2822 ( .A(n695), .B(n2247), .Y(n2396) );
INVX8TS U2823 ( .A(n659), .Y(n695) );
ADDFHX2TS U2824 ( .A(n3432), .B(n3431), .CI(n3430), .CO(n3457), .S(n3467) );
OAI22X2TS U2825 ( .A0(n6795), .A1(n2892), .B0(n5388), .B1(n3002), .Y(n2999)
);
ADDFHX2TS U2826 ( .A(n3441), .B(n3440), .CI(n3439), .CO(n3471), .S(n3466) );
ADDFHX2TS U2827 ( .A(n2991), .B(n2990), .CI(n2989), .CO(n3024), .S(n2986) );
ADDFHX2TS U2828 ( .A(n5470), .B(n5469), .CI(n5468), .CO(n5552), .S(n5509) );
ADDFHX2TS U2829 ( .A(n6864), .B(n6863), .CI(n6862), .CO(n6901), .S(n6866) );
NAND2X4TS U2830 ( .A(n7246), .B(n7245), .Y(n7504) );
AOI21X4TS U2831 ( .A0(n7740), .A1(n7518), .B0(n7517), .Y(n7519) );
OAI22X2TS U2832 ( .A0(n7752), .A1(n6793), .B0(n6830), .B1(n6829), .Y(n6864)
);
OAI21X1TS U2833 ( .A0(n7594), .A1(n7593), .B0(n7592), .Y(n7595) );
OAI21X4TS U2834 ( .A0(n7592), .A1(n7597), .B0(n7598), .Y(n7208) );
ADDFHX4TS U2835 ( .A(n3758), .B(n3757), .CI(n3756), .CO(n3951), .S(n3760) );
OAI22X2TS U2836 ( .A0(n5328), .A1(n3564), .B0(n5327), .B1(n3673), .Y(n3670)
);
ADDFHX2TS U2837 ( .A(n2172), .B(n2171), .CI(n2170), .CO(n2173), .S(n2178) );
OAI22X1TS U2838 ( .A0(n1727), .A1(n1725), .B0(n3071), .B1(n2120), .Y(n2172)
);
ADDFHX2TS U2839 ( .A(n1040), .B(n1039), .CI(n1038), .CO(n1158), .S(n1209) );
XNOR2X2TS U2840 ( .A(n6642), .B(n4176), .Y(n5709) );
XNOR2X1TS U2841 ( .A(n6931), .B(Op_MY[32]), .Y(n6475) );
XNOR2X1TS U2842 ( .A(n770), .B(Op_MY[32]), .Y(n6251) );
XNOR2X1TS U2843 ( .A(n703), .B(Op_MY[32]), .Y(n5587) );
ADDFHX2TS U2844 ( .A(n5835), .B(n5834), .CI(n5833), .CO(n5845), .S(n6083) );
ADDFHX2TS U2845 ( .A(n2059), .B(n2058), .CI(n2057), .CO(n2051), .S(n2074) );
ADDFHX2TS U2846 ( .A(n1020), .B(n1019), .CI(n1018), .CO(n1126), .S(n1239) );
ADDFHX2TS U2847 ( .A(n3078), .B(n3077), .CI(n3076), .CO(n3087), .S(n2987) );
ADDFHX4TS U2848 ( .A(n1637), .B(n1636), .CI(n1635), .CO(n1629), .S(n2525) );
ADDFX2TS U2849 ( .A(n1300), .B(n1299), .CI(n1298), .CO(n1543), .S(n1479) );
OAI22X2TS U2850 ( .A0(n6381), .A1(n3125), .B0(n4116), .B1(n3169), .Y(n3362)
);
NOR2X8TS U2851 ( .A(n2097), .B(n2096), .Y(n8701) );
XOR2X2TS U2852 ( .A(n1854), .B(n1856), .Y(n858) );
ADDFHX2TS U2853 ( .A(n2029), .B(n2028), .CI(n2027), .CO(n1854), .S(n2056) );
XNOR2X2TS U2854 ( .A(n766), .B(n3590), .Y(n2442) );
XNOR2X2TS U2855 ( .A(n766), .B(n5873), .Y(n3574) );
XNOR2X1TS U2856 ( .A(n766), .B(n696), .Y(n1683) );
ADDFHX2TS U2857 ( .A(n1064), .B(n1063), .CI(n1062), .CO(n1164), .S(n1157) );
INVX8TS U2858 ( .A(n5439), .Y(n2926) );
INVX8TS U2859 ( .A(n5439), .Y(n5090) );
ADDFHX2TS U2860 ( .A(n2902), .B(n2901), .CI(n2900), .CO(n3088), .S(n2905) );
ADDFHX2TS U2861 ( .A(n5109), .B(n5108), .CI(n5107), .CO(n5220), .S(n5106) );
ADDFHX2TS U2862 ( .A(n5088), .B(n5087), .CI(n5086), .CO(n5238), .S(n5140) );
ADDFHX2TS U2863 ( .A(n5484), .B(n5483), .CI(n5482), .CO(n5549), .S(n5462) );
ADDFHX2TS U2864 ( .A(n6802), .B(n6801), .CI(n6800), .CO(n7242), .S(n7240) );
XNOR2X2TS U2865 ( .A(n6143), .B(n5602), .Y(n4502) );
ADDFHX2TS U2866 ( .A(n2839), .B(n2838), .CI(n2837), .CO(n2940), .S(n2872) );
ADDFHX2TS U2867 ( .A(n4147), .B(n4146), .CI(n4145), .CO(n4158), .S(n4151) );
OAI22X2TS U2868 ( .A0(n3782), .A1(n3781), .B0(n4680), .B1(n3897), .Y(n3876)
);
OAI22X2TS U2869 ( .A0(n5350), .A1(n5204), .B0(n5720), .B1(n5349), .Y(n5322)
);
ADDFHX2TS U2870 ( .A(n2331), .B(n2330), .CI(n2329), .CO(n2593), .S(n2332) );
ADDFX2TS U2871 ( .A(n2292), .B(n2291), .CI(n2290), .CO(n2588), .S(n2330) );
ADDFHX2TS U2872 ( .A(n3336), .B(n3335), .CI(n3334), .CO(n3344), .S(n3401) );
OAI22X2TS U2873 ( .A0(n6156), .A1(n4321), .B0(n6794), .B1(n4459), .Y(n4633)
);
ADDFHX4TS U2874 ( .A(n4123), .B(n4122), .CI(n4121), .CO(n4397), .S(n4390) );
INVX12TS U2875 ( .A(n5988), .Y(n816) );
ADDFHX2TS U2876 ( .A(n4156), .B(n4155), .CI(n4154), .CO(n4275), .S(n4161) );
ADDFHX2TS U2877 ( .A(n4020), .B(n4019), .CI(n4018), .CO(n4271), .S(n4154) );
ADDFHX2TS U2878 ( .A(n3733), .B(n3732), .CI(n3731), .CO(n3815), .S(n3736) );
NOR2X8TS U2879 ( .A(n2597), .B(n2598), .Y(n7949) );
OAI22X2TS U2880 ( .A0(n687), .A1(n2297), .B0(n2397), .B1(n3928), .Y(n2429)
);
ADDFHX2TS U2881 ( .A(n5202), .B(n5201), .CI(n5200), .CO(n5356), .S(n5169) );
ADDFHX2TS U2882 ( .A(n3307), .B(n3306), .CI(n3305), .CO(n3342), .S(n3399) );
ADDFHX2TS U2883 ( .A(n1205), .B(n1204), .CI(n1203), .CO(n1211), .S(n1271) );
OAI22X1TS U2884 ( .A0(n2720), .A1(n949), .B0(n4295), .B1(n948), .Y(n953) );
ADDFHX2TS U2885 ( .A(n5435), .B(n5434), .CI(n5433), .CO(n5495), .S(n5436) );
INVX8TS U2886 ( .A(n6029), .Y(n5792) );
ADDFHX2TS U2887 ( .A(n2763), .B(n2762), .CI(n2761), .CO(n2802), .S(n2731) );
ADDFHX2TS U2888 ( .A(n1462), .B(n1461), .CI(n1460), .CO(n2762), .S(n1400) );
ADDFX2TS U2889 ( .A(n1795), .B(n1794), .CI(n1793), .CO(n1825), .S(n1833) );
NOR2X8TS U2890 ( .A(n3518), .B(n3519), .Y(n7930) );
ADDFHX2TS U2891 ( .A(n3408), .B(n3407), .CI(n3406), .CO(n3446), .S(n3427) );
ADDFHX2TS U2892 ( .A(n3411), .B(n3410), .CI(n3409), .CO(n3445), .S(n3456) );
ADDFHX2TS U2893 ( .A(n2010), .B(n2009), .CI(n2008), .CO(n2078), .S(n2013) );
XNOR2X1TS U2894 ( .A(n8208), .B(n4504), .Y(n1081) );
AOI21X2TS U2895 ( .A0(n676), .A1(n7747), .B0(n7746), .Y(n7755) );
OAI22X2TS U2896 ( .A0(n6177), .A1(n3173), .B0(n5388), .B1(n3274), .Y(n3205)
);
OAI22X2TS U2897 ( .A0(n6795), .A1(n2661), .B0(n5388), .B1(n2796), .Y(n2718)
);
ADDFHX4TS U2898 ( .A(n2769), .B(n2768), .CI(n2767), .CO(n2817), .S(n2804) );
ADDFHX2TS U2899 ( .A(n2775), .B(n2774), .CI(n2773), .CO(n2898), .S(n2767) );
OAI22X1TS U2900 ( .A0(n6463), .A1(n1489), .B0(n1488), .B1(n6365), .Y(n1657)
);
INVX4TS U2901 ( .A(n7996), .Y(n2626) );
ADDFHX2TS U2902 ( .A(n996), .B(n995), .CI(n994), .CO(n1020), .S(n1210) );
ADDFHX2TS U2903 ( .A(n4382), .B(n4381), .CI(n4380), .CO(n4962), .S(n4385) );
ADDFHX2TS U2904 ( .A(n4171), .B(n4170), .CI(n4169), .CO(n4382), .S(n4276) );
ADDFHX2TS U2905 ( .A(n1034), .B(n1033), .CI(n1032), .CO(n1019), .S(n1229) );
ADDFHX2TS U2906 ( .A(n2724), .B(n2723), .CI(n2722), .CO(n2739), .S(n2697) );
ADDFHX2TS U2907 ( .A(n2013), .B(n2012), .CI(n2011), .CO(n2020), .S(n2017) );
OAI22X2TS U2908 ( .A0(n817), .A1(n4501), .B0(n5130), .B1(n4679), .Y(n4517)
);
ADDFHX2TS U2909 ( .A(n4299), .B(n4298), .CI(n4297), .CO(n4740), .S(n4354) );
ADDFHX2TS U2910 ( .A(n5079), .B(n5078), .CI(n5077), .CO(n5198), .S(n5145) );
ADDFX2TS U2911 ( .A(n4936), .B(n4935), .CI(n4934), .CO(n5146), .S(n4942) );
XNOR2X2TS U2912 ( .A(n6401), .B(n1624), .Y(n4777) );
ADDFHX2TS U2913 ( .A(n4192), .B(n4191), .CI(n4190), .CO(n4302), .S(n4269) );
ADDFHX2TS U2914 ( .A(n4333), .B(n4332), .CI(n4331), .CO(n4724), .S(n4328) );
ADDFHX2TS U2915 ( .A(n3471), .B(n3470), .CI(n3469), .CO(n3477), .S(n3488) );
ADDFHX2TS U2916 ( .A(n1615), .B(n1614), .CI(n1613), .CO(n1602), .S(n1675) );
ADDFHX2TS U2917 ( .A(n4691), .B(n4690), .CI(n4689), .CO(n4700), .S(n4751) );
ADDFX2TS U2918 ( .A(n4624), .B(n4623), .CI(n4622), .CO(n4455), .S(n4689) );
ADDFHX2TS U2919 ( .A(n4630), .B(n4629), .CI(n4628), .CO(n4690), .S(n4747) );
OAI2BB1X2TS U2920 ( .A0N(n8756), .A1N(n8755), .B0(n8754), .Y(n404) );
XNOR2X4TS U2921 ( .A(DP_OP_31J26_122_605_n1), .B(n8752), .Y(n8755) );
NOR2X1TS U2922 ( .A(FSM_selector_B[1]), .B(Op_MY[52]), .Y(n7441) );
ADDFHX4TS U2923 ( .A(n3093), .B(n3092), .CI(n3091), .CO(n3497), .S(n3097) );
ADDFHX2TS U2924 ( .A(n3021), .B(n3020), .CI(n3019), .CO(n3091), .S(n3095) );
OAI22X2TS U2925 ( .A0(n4606), .A1(n2671), .B0(n827), .B1(n2670), .Y(n2729)
);
ADDFHX2TS U2926 ( .A(n6607), .B(n6606), .CI(n6605), .CO(n6625), .S(n6620) );
ADDFHX2TS U2927 ( .A(n1801), .B(n1800), .CI(n1799), .CO(n1772), .S(n1802) );
ADDFHX2TS U2928 ( .A(n5582), .B(n5581), .CI(n5580), .CO(n5758), .S(n5616) );
ADDFHX2TS U2929 ( .A(n3569), .B(n3568), .CI(n3567), .CO(n3663), .S(n3556) );
ADDFHX2TS U2930 ( .A(n3715), .B(n3714), .CI(n3713), .CO(n3820), .S(n3662) );
OAI21X1TS U2931 ( .A0(n7795), .A1(n7799), .B0(n7800), .Y(n7702) );
OAI21X1TS U2932 ( .A0(n7795), .A1(n7658), .B0(n7657), .Y(n7659) );
ADDFHX4TS U2933 ( .A(n4952), .B(n4951), .CI(n4950), .CO(n5072), .S(n4944) );
ADDFX2TS U2934 ( .A(n4929), .B(n4928), .CI(n4927), .CO(n5069), .S(n4951) );
XNOR2X1TS U2935 ( .A(n3149), .B(n4427), .Y(n1375) );
XNOR2X1TS U2936 ( .A(n8213), .B(Op_MY[34]), .Y(n3004) );
XNOR2X1TS U2937 ( .A(n3108), .B(Op_MY[34]), .Y(n3143) );
XNOR2X1TS U2938 ( .A(n784), .B(n4427), .Y(n1002) );
ADDFHX2TS U2939 ( .A(n2483), .B(n2482), .CI(n2481), .CO(n2551), .S(n2544) );
ADDFHX4TS U2940 ( .A(n1344), .B(n1343), .CI(n1342), .CO(n1430), .S(n1339) );
ADDFHX2TS U2941 ( .A(n1403), .B(n1402), .CI(n1401), .CO(n2735), .S(n1429) );
ADDFHX2TS U2942 ( .A(n1347), .B(n1346), .CI(n1345), .CO(n1403), .S(n1333) );
ADDFHX2TS U2943 ( .A(n7111), .B(n7110), .CI(n7109), .CO(n7234), .S(n7231) );
ADDFHX2TS U2944 ( .A(n7120), .B(n7119), .CI(n7118), .CO(n7124), .S(n7109) );
XNOR2X2TS U2945 ( .A(n4883), .B(n3833), .Y(n3932) );
XNOR2X1TS U2946 ( .A(n4883), .B(n4406), .Y(n4554) );
XNOR2X1TS U2947 ( .A(n4883), .B(n3992), .Y(n4209) );
ADDFX2TS U2948 ( .A(n4827), .B(n4826), .CI(n4825), .CO(n4955), .S(n4792) );
OAI22X2TS U2949 ( .A0(n4260), .A1(n2420), .B0(n3051), .B1(n2419), .Y(n2502)
);
ADDFHX2TS U2950 ( .A(n5154), .B(n5153), .CI(n5152), .CO(n5215), .S(n5156) );
ADDFHX2TS U2951 ( .A(n4667), .B(n4666), .CI(n4665), .CO(n4795), .S(n4562) );
NAND2X4TS U2952 ( .A(n3519), .B(n3518), .Y(n7931) );
ADDFHX2TS U2953 ( .A(n3429), .B(n3428), .CI(n3427), .CO(n3458), .S(n3454) );
XNOR2X1TS U2954 ( .A(n4916), .B(n5129), .Y(n4100) );
ADDFHX2TS U2955 ( .A(n5188), .B(n5187), .CI(n5186), .CO(n5353), .S(n5245) );
ADDFHX2TS U2956 ( .A(n4212), .B(n4211), .CI(n4210), .CO(n4314), .S(n4221) );
ADDFHX4TS U2957 ( .A(n1335), .B(n1334), .CI(n1333), .CO(n1431), .S(n1340) );
ADDFHX2TS U2958 ( .A(n1436), .B(n1435), .CI(n1434), .CO(n2733), .S(n1433) );
OAI22X1TS U2959 ( .A0(n2400), .A1(n2136), .B0(n3071), .B1(n2224), .Y(n2198)
);
OAI22X2TS U2960 ( .A0(n4610), .A1(n4609), .B0(n783), .B1(n4607), .Y(n4650)
);
XNOR2X2TS U2961 ( .A(n6166), .B(n4607), .Y(n4609) );
ADDFHX2TS U2962 ( .A(n3638), .B(n3637), .CI(n3636), .CO(n3755), .S(n3717) );
XNOR2X2TS U2963 ( .A(n6143), .B(n5792), .Y(n4672) );
NAND2X4TS U2964 ( .A(n7230), .B(n7229), .Y(n7544) );
ADDFHX4TS U2965 ( .A(n7093), .B(n7092), .CI(n7091), .CO(n7232), .S(n7230) );
ADDFHX2TS U2966 ( .A(n2362), .B(n2361), .CI(n2360), .CO(n2366), .S(n2431) );
NOR2X4TS U2967 ( .A(n7530), .B(n7532), .Y(n7535) );
ADDFHX2TS U2968 ( .A(n6628), .B(n6627), .CI(n6626), .CO(n6640), .S(n6623) );
OAI22X2TS U2969 ( .A0(n5625), .A1(n6460), .B0(n789), .B1(n6380), .Y(n6465)
);
ADDFHX2TS U2970 ( .A(n3953), .B(n3952), .CI(n3951), .CO(n4121), .S(n3956) );
OAI22X2TS U2971 ( .A0(n6772), .A1(n4551), .B0(n6437), .B1(n4777), .Y(n4774)
);
ADDFHX2TS U2972 ( .A(n3978), .B(n3977), .CI(n3976), .CO(n4020), .S(n4145) );
ADDFHX4TS U2973 ( .A(n3736), .B(n3735), .CI(n3734), .CO(n3812), .S(n3739) );
ADDFHX4TS U2974 ( .A(n3551), .B(n3550), .CI(n3549), .CO(n3735), .S(n3627) );
ADDFHX2TS U2975 ( .A(n3420), .B(n3419), .CI(n3418), .CO(n3631), .S(n3461) );
ADDFHX2TS U2976 ( .A(n3417), .B(n3416), .CI(n3415), .CO(n3418), .S(n3448) );
ADDFHX2TS U2977 ( .A(n4376), .B(n4375), .CI(n4374), .CO(n4974), .S(n4381) );
ADDFHX2TS U2978 ( .A(n4284), .B(n4283), .CI(n4282), .CO(n4985), .S(n4376) );
ADDFHX2TS U2979 ( .A(n2857), .B(n2856), .CI(n2855), .CO(n2952), .S(n2844) );
OAI22X2TS U2980 ( .A0(n3114), .A1(n2358), .B0(n2357), .B1(n6456), .Y(n2440)
);
ADDFHX4TS U2981 ( .A(n2736), .B(n2735), .CI(n2734), .CO(n2805), .S(n2812) );
ADDFHX2TS U2982 ( .A(n1400), .B(n1399), .CI(n1398), .CO(n2736), .S(n1428) );
AOI21X4TS U2983 ( .A0(n909), .A1(n8598), .B0(n1940), .Y(n1941) );
ADDFHX2TS U2984 ( .A(n1983), .B(n1982), .CI(n1981), .CO(n2014), .S(n1939) );
ADDFHX2TS U2985 ( .A(n5718), .B(n5717), .CI(n5716), .CO(n5764), .S(n5652) );
INVX8TS U2986 ( .A(n5326), .Y(n2258) );
ADDFHX4TS U2987 ( .A(n4824), .B(n4823), .CI(n4822), .CO(n4958), .S(n5021) );
ADDFHX2TS U2988 ( .A(n6356), .B(n6355), .CI(n6354), .CO(n6396), .S(n6522) );
ADDFHX2TS U2989 ( .A(n4141), .B(n4140), .CI(n4139), .CO(n4266), .S(n4168) );
ADDFHX2TS U2990 ( .A(n2131), .B(n2130), .CI(n2129), .CO(n2188), .S(n2196) );
OAI22X2TS U2991 ( .A0(n5956), .A1(n4432), .B0(n744), .B1(n4431), .Y(n4463)
);
ADDFHX2TS U2992 ( .A(n1037), .B(n1036), .CI(n1035), .CO(n1208), .S(n1228) );
ADDHX1TS U2993 ( .A(n947), .B(n946), .CO(n982), .S(n1059) );
OAI22X2TS U2994 ( .A0(n817), .A1(n4177), .B0(n5130), .B1(n4293), .Y(n4290)
);
CLKINVX3TS U2995 ( .A(n7740), .Y(n7275) );
OAI21X2TS U2996 ( .A0(n7683), .A1(n7678), .B0(n7684), .Y(n7259) );
INVX8TS U2997 ( .A(n679), .Y(n681) );
ADDFHX2TS U2998 ( .A(n2899), .B(n2898), .CI(n2897), .CO(n3089), .S(n2816) );
XNOR2X2TS U2999 ( .A(n5784), .B(n763), .Y(n3208) );
OR2X8TS U3000 ( .A(n2624), .B(n2623), .Y(n7996) );
ADDFHX2TS U3001 ( .A(n3246), .B(n3245), .CI(n3244), .CO(n3586), .S(n3251) );
ADDFHX2TS U3002 ( .A(n2833), .B(n2832), .CI(n2831), .CO(n2942), .S(n2840) );
ADDFX2TS U3003 ( .A(n3189), .B(n3188), .CI(n3187), .CO(n3604), .S(n3278) );
ADDFHX2TS U3004 ( .A(n3301), .B(n3300), .CI(n3299), .CO(n3582), .S(n3187) );
OAI22X2TS U3005 ( .A0(n4610), .A1(n3115), .B0(n783), .B1(n3219), .Y(n3313)
);
XNOR2X4TS U3006 ( .A(n7664), .B(n7663), .Y(n7666) );
BUFX12TS U3007 ( .A(n3928), .Y(n3680) );
INVX12TS U3008 ( .A(n6985), .Y(n5783) );
ADDFHX2TS U3009 ( .A(n3330), .B(n3329), .CI(n3328), .CO(n3141), .S(n3391) );
ADDFHX2TS U3010 ( .A(n4302), .B(n4301), .CI(n4300), .CO(n4983), .S(n4374) );
ADDFHX2TS U3011 ( .A(n1598), .B(n1597), .CI(n1596), .CO(n1594), .S(n1679) );
ADDFHX4TS U3012 ( .A(n1580), .B(n1579), .CI(n1578), .CO(n1588), .S(n1590) );
ADDFHX2TS U3013 ( .A(n1543), .B(n1542), .CI(n1541), .CO(n1583), .S(n1579) );
ADDFHX2TS U3014 ( .A(n4591), .B(n4590), .CI(n4589), .CO(n4476), .S(n4711) );
XNOR2X2TS U3015 ( .A(n709), .B(n790), .Y(n4438) );
ADDFHX2TS U3016 ( .A(n4923), .B(n4922), .CI(n4921), .CO(n5104), .S(n4869) );
OAI21X2TS U3017 ( .A0(n8578), .A1(n8575), .B0(n8576), .Y(n8593) );
ADDFHX2TS U3018 ( .A(n1843), .B(n1842), .CI(n1841), .CO(n1856), .S(n2052) );
ADDFHX2TS U3019 ( .A(n2316), .B(n2315), .CI(n2314), .CO(n2563), .S(n2325) );
NAND2X4TS U3020 ( .A(n866), .B(n864), .Y(n863) );
ADDFHX4TS U3021 ( .A(n3884), .B(n3883), .CI(n3882), .CO(n4125), .S(n3954) );
ADDFHX2TS U3022 ( .A(n3764), .B(n3763), .CI(n3762), .CO(n3884), .S(n3759) );
ADDFHX2TS U3023 ( .A(n1537), .B(n1536), .CI(n1535), .CO(n1581), .S(n1591) );
ADDFHX2TS U3024 ( .A(n5820), .B(n5819), .CI(n5818), .CO(n5813), .S(n5841) );
ADDFHX2TS U3025 ( .A(n5826), .B(n5825), .CI(n5824), .CO(n5812), .S(n5839) );
ADDFHX4TS U3026 ( .A(n4790), .B(n4789), .CI(n4788), .CO(n4946), .S(n4787) );
ADDFHX2TS U3027 ( .A(n3919), .B(n3918), .CI(n3917), .CO(n4043), .S(n3912) );
ADDFHX4TS U3028 ( .A(n3817), .B(n3816), .CI(n3815), .CO(n3959), .S(n3813) );
ADDFHX4TS U3029 ( .A(n5185), .B(n5184), .CI(n5183), .CO(n5337), .S(n5214) );
ADDFHX2TS U3030 ( .A(n4955), .B(n4954), .CI(n4953), .CO(n5071), .S(n4866) );
OAI22X1TS U3031 ( .A0(n4938), .A1(n657), .B0(n6643), .B1(n6829), .Y(n6792)
);
NOR2X8TS U3032 ( .A(n2602), .B(n2601), .Y(n7971) );
NAND2X4TS U3033 ( .A(n2602), .B(n2601), .Y(n7972) );
ADDFHX4TS U3034 ( .A(n2573), .B(n2572), .CI(n2571), .CO(n2605), .S(n2602) );
OAI22X2TS U3035 ( .A0(n5664), .A1(n3834), .B0(n6332), .B1(n3932), .Y(n3915)
);
CLKINVX12TS U3036 ( .A(Op_MX[7]), .Y(n1168) );
NOR2X8TS U3037 ( .A(n7593), .B(n7597), .Y(n7209) );
ADDFHX2TS U3038 ( .A(n2480), .B(n2479), .CI(n2478), .CO(n2552), .S(n2545) );
XNOR2X1TS U3039 ( .A(n5990), .B(n750), .Y(n3901) );
ADDFHX2TS U3040 ( .A(n4070), .B(n4069), .CI(n4068), .CO(n4171), .S(n4166) );
INVX12TS U3041 ( .A(n719), .Y(n721) );
ADDFHX2TS U3042 ( .A(n4639), .B(n4638), .CI(n4637), .CO(n4643), .S(n4722) );
ADDFHX2TS U3043 ( .A(n5770), .B(n5769), .CI(n5768), .CO(n5920), .S(n5731) );
XNOR2X2TS U3044 ( .A(n5787), .B(n5207), .Y(n3613) );
INVX12TS U3045 ( .A(n8215), .Y(n749) );
OAI21X1TS U3046 ( .A0(n7546), .A1(n7545), .B0(n7544), .Y(n7547) );
OAI21X1TS U3047 ( .A0(n7743), .A1(n7714), .B0(n7713), .Y(n7715) );
NOR2X4TS U3048 ( .A(n7274), .B(n7714), .Y(n7732) );
NOR2X4TS U3049 ( .A(n7545), .B(n7549), .Y(n7394) );
ADDFHX2TS U3050 ( .A(n6736), .B(n6735), .CI(n6734), .CO(n7076), .S(n7080) );
INVX8TS U3051 ( .A(n684), .Y(n686) );
ADDHX1TS U3052 ( .A(n1809), .B(n1808), .CO(n1812), .S(n1841) );
ADDFHX2TS U3053 ( .A(n3310), .B(n3309), .CI(n3308), .CO(n3315), .S(n3341) );
XNOR2X2TS U3054 ( .A(n708), .B(n3207), .Y(n3286) );
OAI22X2TS U3055 ( .A0(n704), .A1(n3831), .B0(n3987), .B1(n3930), .Y(n3916)
);
BUFX20TS U3056 ( .A(n6455), .Y(n704) );
XNOR2X2TS U3057 ( .A(n5880), .B(n790), .Y(n3831) );
ADDFHX2TS U3058 ( .A(n3697), .B(n3696), .CI(n3695), .CO(n3750), .S(n3634) );
OAI21X2TS U3059 ( .A0(n8643), .A1(n8640), .B0(n8644), .Y(n1906) );
NAND2X4TS U3060 ( .A(n7219), .B(n7218), .Y(n7772) );
ADDFHX4TS U3061 ( .A(n6640), .B(n6639), .CI(n6638), .CO(n7220), .S(n7219) );
ADDFHX2TS U3062 ( .A(n1631), .B(n1630), .CI(n1629), .CO(n1592), .S(n1632) );
ADDFHX4TS U3063 ( .A(n3414), .B(n3413), .CI(n3412), .CO(n3380), .S(n3449) );
ADDFHX4TS U3064 ( .A(n2818), .B(n2817), .CI(n2816), .CO(n3096), .S(n2903) );
ADDFHX2TS U3065 ( .A(n2803), .B(n2802), .CI(n2801), .CO(n2818), .S(n2815) );
ADDFHX2TS U3066 ( .A(n4038), .B(n4037), .CI(n4036), .CO(n4081), .S(n4149) );
XNOR2X2TS U3067 ( .A(n3920), .B(n4678), .Y(n3973) );
OR2X8TS U3068 ( .A(n7215), .B(n7214), .Y(n662) );
INVX4TS U3069 ( .A(n7382), .Y(n7217) );
ADDFHX4TS U3070 ( .A(n6622), .B(n6621), .CI(n6620), .CO(n7214), .S(n7212) );
ADDFHX2TS U3071 ( .A(n6580), .B(n6579), .CI(n6578), .CO(n6622), .S(n6575) );
XNOR2X2TS U3072 ( .A(n6168), .B(n5324), .Y(n3233) );
XNOR2X2TS U3073 ( .A(n6168), .B(n5392), .Y(n3614) );
ADDFHX2TS U3074 ( .A(n6568), .B(n6567), .CI(n6566), .CO(n6573), .S(n6635) );
ADDFX2TS U3075 ( .A(n6550), .B(n6549), .CI(n6548), .CO(n6567), .S(n6633) );
ADDFHX2TS U3076 ( .A(n1103), .B(n1102), .CI(n1101), .CO(n1347), .S(n1148) );
ADDFHX4TS U3077 ( .A(n1394), .B(n1393), .CI(n1392), .CO(n1472), .S(n1395) );
ADDFHX4TS U3078 ( .A(n1338), .B(n1337), .CI(n1336), .CO(n1426), .S(n1393) );
OAI22X2TS U3079 ( .A0(n688), .A1(n6226), .B0(n6746), .B1(n6262), .Y(n6236)
);
AOI21X4TS U3080 ( .A0(n7711), .A1(n7481), .B0(n7480), .Y(n7694) );
OAI22X1TS U3081 ( .A0(n5944), .A1(n5943), .B0(n788), .B1(n6025), .Y(n6059)
);
ADDFHX4TS U3082 ( .A(n5371), .B(n5370), .CI(n5369), .CO(n5461), .S(n5367) );
INVX8TS U3083 ( .A(n6427), .Y(n5132) );
OAI22X2TS U3084 ( .A0(n2720), .A1(n1451), .B0(n4685), .B1(n2664), .Y(n2726)
);
XNOR2X2TS U3085 ( .A(n709), .B(n2137), .Y(n2664) );
ADDFHX2TS U3086 ( .A(n5516), .B(n5515), .CI(n5514), .CO(n5619), .S(n5536) );
XNOR2X2TS U3087 ( .A(n706), .B(n3065), .Y(n3148) );
XNOR2X2TS U3088 ( .A(n4427), .B(n8811), .Y(n3260) );
XNOR2X2TS U3089 ( .A(n822), .B(n4427), .Y(n3905) );
ADDFHX4TS U3090 ( .A(n3655), .B(n3654), .CI(n3653), .CO(n3846), .S(n3661) );
ADDFHX2TS U3091 ( .A(n1465), .B(n1464), .CI(n1463), .CO(n2745), .S(n1462) );
ADDFHX2TS U3092 ( .A(n1443), .B(n1442), .CI(n1441), .CO(n2696), .S(n1414) );
ADDFX2TS U3093 ( .A(n5070), .B(n5069), .CI(n5068), .CO(n5253), .S(n5154) );
ADDFHX2TS U3094 ( .A(n5100), .B(n5099), .CI(n5098), .CO(n5213), .S(n5068) );
ADDFHX2TS U3095 ( .A(n4633), .B(n4632), .CI(n4631), .CO(n4645), .S(n4707) );
OAI22X1TS U3096 ( .A0(n782), .A1(n5490), .B0(n5585), .B1(n5586), .Y(n5578)
);
AOI21X4TS U3097 ( .A0(n7748), .A1(n7703), .B0(n7702), .Y(n7707) );
NOR2X6TS U3098 ( .A(n7853), .B(n7848), .Y(n7957) );
XNOR2X1TS U3099 ( .A(n647), .B(n648), .Y(n4232) );
ADDFHX2TS U3100 ( .A(n4041), .B(n4040), .CI(n4039), .CO(n4080), .S(n3963) );
ADDFHX2TS U3101 ( .A(n5832), .B(n5831), .CI(n5830), .CO(n5815), .S(n5846) );
ADDFHX2TS U3102 ( .A(n4047), .B(n4046), .CI(n4045), .CO(n4270), .S(n4139) );
ADDFX2TS U3103 ( .A(n4979), .B(n4978), .CI(n4977), .CO(n4997), .S(n4975) );
INVX8TS U3104 ( .A(n6880), .Y(n6032) );
XNOR2X2TS U3105 ( .A(n766), .B(n4905), .Y(n3117) );
ADDFHX2TS U3106 ( .A(n3298), .B(n3297), .CI(n3296), .CO(n3583), .S(n3238) );
OAI22X2TS U3107 ( .A0(n3808), .A1(n3265), .B0(n5743), .B1(n3573), .Y(n3622)
);
ADDFHX4TS U3108 ( .A(n3096), .B(n3095), .CI(n3094), .CO(n3508), .S(n3507) );
NAND2X8TS U3109 ( .A(n938), .B(n939), .Y(n4677) );
OAI22X2TS U3110 ( .A0(n817), .A1(n4428), .B0(n5130), .B1(n4481), .Y(n4619)
);
XNOR2X2TS U3111 ( .A(n705), .B(Op_MY[33]), .Y(n4428) );
ADDFHX4TS U3112 ( .A(n4970), .B(n4969), .CI(n4968), .CO(n5002), .S(n4986) );
ADDFHX2TS U3113 ( .A(n4327), .B(n4326), .CI(n4325), .CO(n4969), .S(n4281) );
ADDFHX4TS U3114 ( .A(n4745), .B(n4744), .CI(n4743), .CO(n4966), .S(n4970) );
ADDFHX2TS U3115 ( .A(n2086), .B(n2085), .CI(n2084), .CO(n2092), .S(n2091) );
ADDFHX2TS U3116 ( .A(n3652), .B(n3651), .CI(n3650), .CO(n3842), .S(n3656) );
XNOR2X2TS U3117 ( .A(n3724), .B(n8806), .Y(n3145) );
ADDFHX2TS U3118 ( .A(n4017), .B(n4016), .CI(n4015), .CO(n4186), .S(n4065) );
ADDFHX2TS U3119 ( .A(n2654), .B(n2653), .CI(n2652), .CO(n2755), .S(n2750) );
ADDFHX2TS U3120 ( .A(n3304), .B(n3303), .CI(n3302), .CO(n3581), .S(n3281) );
ADDFHX2TS U3121 ( .A(n3269), .B(n3268), .CI(n3267), .CO(n3533), .S(n3239) );
ADDFHX2TS U3122 ( .A(n4470), .B(n4469), .CI(n4468), .CO(n4705), .S(n4723) );
OAI22X2TS U3123 ( .A0(n6125), .A1(n907), .B0(n3255), .B1(n7173), .Y(n3619)
);
INVX16TS U3124 ( .A(Op_MX[1]), .Y(n4071) );
XNOR2X2TS U3125 ( .A(n2797), .B(n6378), .Y(n3209) );
ADDFHX2TS U3126 ( .A(n3560), .B(n3559), .CI(n3558), .CO(n3718), .S(n3532) );
ADDFHX2TS U3127 ( .A(n4697), .B(n4696), .CI(n4695), .CO(n4698), .S(n4749) );
NOR2X8TS U3128 ( .A(n5051), .B(n5052), .Y(n7356) );
ADDFHX2TS U3129 ( .A(n6396), .B(n6395), .CI(n6394), .CO(n6398), .S(n6569) );
ADDFHX2TS U3130 ( .A(n3215), .B(n3214), .CI(n3213), .CO(n3240), .S(n3235) );
OAI22X1TS U3131 ( .A0(n1663), .A1(n3224), .B0(n5410), .B1(n3271), .Y(n3246)
);
ADDFHX4TS U3132 ( .A(n2733), .B(n2732), .CI(n2731), .CO(n2806), .S(n2807) );
NAND2X8TS U3133 ( .A(Op_MX[1]), .B(n2159), .Y(n3596) );
ADDFHX2TS U3134 ( .A(n2220), .B(n2219), .CI(n2218), .CO(n2336), .S(n2237) );
BUFX12TS U3135 ( .A(n2884), .Y(n810) );
ADDFHX4TS U3136 ( .A(n1128), .B(n1127), .CI(n1126), .CO(n1394), .S(n1232) );
ADDFHX4TS U3137 ( .A(n5015), .B(n5014), .CI(n5013), .CO(n5023), .S(n5007) );
ADDFHX2TS U3138 ( .A(n3749), .B(n3748), .CI(n3747), .CO(n3868), .S(n3800) );
AOI21X1TS U3139 ( .A0(n7867), .A1(n7862), .B0(n2634), .Y(n834) );
NAND2X6TS U3140 ( .A(n7871), .B(n7862), .Y(n8016) );
OAI22X1TS U3141 ( .A0(n4057), .A1(n1175), .B0(n3899), .B1(n961), .Y(n1183)
);
ADDFHX2TS U3142 ( .A(n4010), .B(n4009), .CI(n4008), .CO(n4067), .S(n4143) );
OAI21X2TS U3143 ( .A0(n7743), .A1(n7276), .B0(n7275), .Y(n7311) );
ADDFHX4TS U3144 ( .A(n6571), .B(n6570), .CI(n6569), .CO(n7203), .S(n7198) );
INVX4TS U3145 ( .A(n5710), .Y(n6931) );
AOI21X4TS U3146 ( .A0(n8661), .A1(n2019), .B0(n2018), .Y(n8622) );
ADDFHX4TS U3147 ( .A(n3435), .B(n3434), .CI(n3433), .CO(n3436), .S(n3463) );
ADDFHX4TS U3148 ( .A(n3444), .B(n3443), .CI(n3442), .CO(n3435), .S(n3470) );
ADDFHX2TS U3149 ( .A(n3893), .B(n3892), .CI(n3891), .CO(n4064), .S(n3948) );
XNOR2X2TS U3150 ( .A(n5880), .B(n3985), .Y(n4024) );
ADDFHX2TS U3151 ( .A(n4165), .B(n4164), .CI(n4163), .CO(n4393), .S(n4124) );
ADDFHX2TS U3152 ( .A(n4050), .B(n4049), .CI(n4048), .CO(n4167), .S(n4164) );
AOI21X4TS U3153 ( .A0(n7645), .A1(n7492), .B0(n7491), .Y(n7493) );
INVX8TS U3154 ( .A(n6825), .Y(n8809) );
ADDFHX2TS U3155 ( .A(n4566), .B(n4565), .CI(n4564), .CO(n4827), .S(n4451) );
NOR2X8TS U3156 ( .A(n2621), .B(n2622), .Y(n7992) );
ADDFHX4TS U3157 ( .A(n1592), .B(n1591), .CI(n1590), .CO(n2621), .S(n2619) );
ADDFHX4TS U3158 ( .A(n1589), .B(n1588), .CI(n1587), .CO(n2623), .S(n2622) );
XNOR2X2TS U3159 ( .A(n2383), .B(n4841), .Y(n2657) );
ADDFHX4TS U3160 ( .A(n3959), .B(n3958), .CI(n3957), .CO(n4386), .S(n3960) );
OAI22X1TS U3161 ( .A0(n4012), .A1(n1312), .B0(n3228), .B1(n1292), .Y(n1558)
);
ADDFHX2TS U3162 ( .A(n4458), .B(n4457), .CI(n4456), .CO(n4727), .S(n4708) );
XNOR2X2TS U3163 ( .A(n5880), .B(n4427), .Y(n4481) );
ADDFHX2TS U3164 ( .A(n4162), .B(n4161), .CI(n4160), .CO(n4264), .S(n4394) );
ADDFHX2TS U3165 ( .A(n3791), .B(n3790), .CI(n3789), .CO(n3913), .S(n3766) );
INVX2TS U3166 ( .A(n7888), .Y(n8162) );
NAND2X8TS U3167 ( .A(n962), .B(n1055), .Y(n2890) );
ADDFHX2TS U3168 ( .A(n5279), .B(n5278), .CI(n5277), .CO(n5368), .S(n5275) );
OR2X8TS U3169 ( .A(n2632), .B(n2631), .Y(n7871) );
OAI22X2TS U3170 ( .A0(n4780), .A1(n3264), .B0(n5887), .B1(n3607), .Y(n3623)
);
XNOR2X2TS U3171 ( .A(n5631), .B(n750), .Y(n3264) );
BUFX12TS U3172 ( .A(n5258), .Y(n710) );
ADDFHX4TS U3173 ( .A(n1427), .B(n1426), .CI(n1425), .CO(n2811), .S(n1474) );
ADDFHX4TS U3174 ( .A(n1341), .B(n1340), .CI(n1339), .CO(n1425), .S(n1396) );
OAI22X2TS U3175 ( .A0(n5535), .A1(n1054), .B0(n786), .B1(n1083), .Y(n1073)
);
ADDFHX4TS U3176 ( .A(n3099), .B(n3098), .CI(n3097), .CO(n3510), .S(n3509) );
ADDFHX2TS U3177 ( .A(n3081), .B(n3080), .CI(n3079), .CO(n3086), .S(n3019) );
ADDFHX2TS U3178 ( .A(n4594), .B(n4593), .CI(n4592), .CO(n4642), .S(n4710) );
XNOR2X2TS U3179 ( .A(n8810), .B(n5392), .Y(n4417) );
ADDFHX4TS U3180 ( .A(n2193), .B(n2192), .CI(n2191), .CO(n2340), .S(n2339) );
ADDFHX2TS U3181 ( .A(n3646), .B(n3645), .CI(n3644), .CO(n3740), .S(n3649) );
XNOR2X2TS U3182 ( .A(n6168), .B(n4406), .Y(n2681) );
ADDFHX4TS U3183 ( .A(n4718), .B(n4717), .CI(n4716), .CO(n4823), .S(n5010) );
OAI21X1TS U3184 ( .A0(n7822), .A1(n7821), .B0(n7820), .Y(n7823) );
ADDFHX2TS U3185 ( .A(n1224), .B(n1223), .CI(n1222), .CO(n1230), .S(n1539) );
ADDFHX2TS U3186 ( .A(n1249), .B(n1248), .CI(n1247), .CO(n1223), .S(n1298) );
ADDFHX2TS U3187 ( .A(n1540), .B(n1539), .CI(n1538), .CO(n1576), .S(n1580) );
ADDFHX4TS U3188 ( .A(n1586), .B(n1585), .CI(n1584), .CO(n2629), .S(n2624) );
ADDFHX4TS U3189 ( .A(n1236), .B(n1235), .CI(n1234), .CO(n1316), .S(n1586) );
NOR2X6TS U3190 ( .A(n7532), .B(n7536), .Y(n7238) );
NOR2X8TS U3191 ( .A(n7234), .B(n7233), .Y(n7532) );
ADDFHX4TS U3192 ( .A(n5900), .B(n5899), .CI(n5898), .CO(n5928), .S(n5926) );
ADDFHX4TS U3193 ( .A(n3489), .B(n3488), .CI(n3487), .CO(n3491), .S(n3493) );
ADDFHX2TS U3194 ( .A(n2968), .B(n2967), .CI(n2966), .CO(n3455), .S(n3082) );
ADDFHX2TS U3195 ( .A(n2971), .B(n2970), .CI(n2969), .CO(n3429), .S(n2967) );
OR2X8TS U3196 ( .A(n2340), .B(n2341), .Y(n8708) );
ADDFHX4TS U3197 ( .A(n2239), .B(n2238), .CI(n2237), .CO(n2343), .S(n2341) );
ADDFHX2TS U3198 ( .A(n5424), .B(n5423), .CI(n5422), .CO(n5457), .S(n5363) );
NAND2X4TS U3199 ( .A(n5053), .B(n5054), .Y(n8084) );
ADDFHX4TS U3200 ( .A(n4997), .B(n4996), .CI(n4995), .CO(n5015), .S(n4993) );
OAI22X2TS U3201 ( .A0(n2890), .A1(n1408), .B0(n829), .B1(n2671), .Y(n2653)
);
XNOR2X1TS U3202 ( .A(n8210), .B(n2702), .Y(n1408) );
XNOR2X2TS U3203 ( .A(n8210), .B(Op_MY[18]), .Y(n2671) );
ADDFHX4TS U3204 ( .A(n3498), .B(n3497), .CI(n3496), .CO(n3514), .S(n3511) );
ADDFHX4TS U3205 ( .A(n3486), .B(n3485), .CI(n3484), .CO(n3494), .S(n3496) );
ADDFHX4TS U3206 ( .A(n6086), .B(n6085), .CI(n6084), .CO(n6093), .S(n6091) );
ADDFHX2TS U3207 ( .A(n5841), .B(n5840), .CI(n5839), .CO(n5836), .S(n6086) );
XNOR2X2TS U3208 ( .A(n8813), .B(n5440), .Y(n5527) );
AOI21X4TS U3209 ( .A0(n7798), .A1(n7435), .B0(n7434), .Y(n7438) );
BUFX12TS U3210 ( .A(n8138), .Y(n7798) );
XNOR2X2TS U3211 ( .A(n6404), .B(Op_MY[32]), .Y(n6336) );
XOR2X4TS U3212 ( .A(n4404), .B(n876), .Y(n959) );
INVX16TS U3213 ( .A(Op_MX[11]), .Y(n5092) );
XNOR2X2TS U3214 ( .A(n791), .B(n5792), .Y(n4347) );
ADDFHX4TS U3215 ( .A(n2579), .B(n2578), .CI(n2577), .CO(n2599), .S(n2598) );
ADDFHX4TS U3216 ( .A(n2570), .B(n2569), .CI(n2568), .CO(n2575), .S(n2577) );
INVX16TS U3217 ( .A(n5092), .Y(n4879) );
ADDFHX4TS U3218 ( .A(n5223), .B(n5222), .CI(n5221), .CO(n5279), .S(n5219) );
XNOR2X2TS U3219 ( .A(n6842), .B(n6742), .Y(n6123) );
ADDFHX4TS U3220 ( .A(n4353), .B(n4352), .CI(n4351), .CO(n4960), .S(n4383) );
ADDFHX4TS U3221 ( .A(n4278), .B(n4277), .CI(n4276), .CO(n4351), .S(n4400) );
OAI22X2TS U3222 ( .A0(n4032), .A1(n3931), .B0(n4031), .B1(n4259), .Y(n4037)
);
ADDFHX4TS U3223 ( .A(n2528), .B(n2527), .CI(n2526), .CO(n2609), .S(n2608) );
ADDFHX4TS U3224 ( .A(n2409), .B(n2408), .CI(n2407), .CO(n2524), .S(n2526) );
ADDFHX2TS U3225 ( .A(n2474), .B(n2473), .CI(n2472), .CO(n2527), .S(n2520) );
ADDFHX2TS U3226 ( .A(n2374), .B(n2373), .CI(n2372), .CO(n2409), .S(n2473) );
XNOR2X2TS U3227 ( .A(n6987), .B(n5892), .Y(n5323) );
AOI21X4TS U3228 ( .A0(n7711), .A1(n7450), .B0(n7449), .Y(n7784) );
ADDFHX2TS U3229 ( .A(n3450), .B(n3449), .CI(n3448), .CO(n3462), .S(n3476) );
ADDFHX4TS U3230 ( .A(n3495), .B(n3494), .CI(n3493), .CO(n3516), .S(n3515) );
AOI21X1TS U3231 ( .A0(n7584), .A1(n7576), .B0(n7461), .Y(n7604) );
AOI21X2TS U3232 ( .A0(n7711), .A1(n7433), .B0(n7432), .Y(n7594) );
ADDFHX4TS U3233 ( .A(n2809), .B(n2808), .CI(n2807), .CO(n2813), .S(n2810) );
ADDFHX2TS U3234 ( .A(n1433), .B(n1432), .CI(n1431), .CO(n2808), .S(n1427) );
ADDFHX4TS U3235 ( .A(n4263), .B(n4262), .CI(n4261), .CO(n4384), .S(n4398) );
ADDFHX2TS U3236 ( .A(n4138), .B(n4137), .CI(n4136), .CO(n4263), .S(n4395) );
NAND2X8TS U3237 ( .A(n925), .B(n955), .Y(n3933) );
ADDFHX4TS U3238 ( .A(n6006), .B(n6005), .CI(n6004), .CO(n6576), .S(n6075) );
ADDFHX2TS U3239 ( .A(n6009), .B(n6008), .CI(n6007), .CO(n6580), .S(n6005) );
ADDFHX4TS U3240 ( .A(n6577), .B(n6576), .CI(n6575), .CO(n7213), .S(n7302) );
INVX12TS U3241 ( .A(Op_MX[45]), .Y(n5710) );
NAND2X4TS U3242 ( .A(n2632), .B(n2631), .Y(n7872) );
AO21X1TS U3243 ( .A0(n6955), .A1(n2979), .B0(n6954), .Y(n6981) );
NOR2X8TS U3244 ( .A(n7474), .B(n7270), .Y(n7272) );
AOI21X1TS U3245 ( .A0(n676), .A1(n7418), .B0(n7417), .Y(n7421) );
AOI21X1TS U3246 ( .A0(n676), .A1(n7624), .B0(n7623), .Y(n7627) );
AOI21X1TS U3247 ( .A0(n676), .A1(n7586), .B0(n7585), .Y(n7588) );
AOI21X1TS U3248 ( .A0(n676), .A1(n7454), .B0(n7453), .Y(n7458) );
AOI21X1TS U3249 ( .A0(n676), .A1(n7734), .B0(n632), .Y(n7384) );
NAND2X4TS U3250 ( .A(n8158), .B(n5034), .Y(n8112) );
ADDFHX2TS U3251 ( .A(n5817), .B(n5816), .CI(n5815), .CO(n5898), .S(n5837) );
XNOR2X2TS U3252 ( .A(n6642), .B(n6335), .Y(n5670) );
NOR2X6TS U3253 ( .A(n7388), .B(n7345), .Y(n7287) );
NOR2X8TS U3254 ( .A(n7283), .B(n7282), .Y(n7388) );
ADDFHX2TS U3255 ( .A(n4775), .B(n4774), .CI(n4773), .CO(n4943), .S(n4784) );
OAI21X4TS U3256 ( .A0(n7281), .A1(n8136), .B0(n7614), .Y(n651) );
OAI21X1TS U3257 ( .A0(n7281), .A1(n8136), .B0(n7614), .Y(n7341) );
XNOR2X2TS U3258 ( .A(n8810), .B(n6056), .Y(n5531) );
AOI21X4TS U3259 ( .A0(n7925), .A1(n3523), .B0(n3522), .Y(n3524) );
ADDFHX4TS U3260 ( .A(n6625), .B(n6624), .CI(n6623), .CO(n7218), .S(n7215) );
NAND2X8TS U3261 ( .A(n958), .B(n959), .Y(n4085) );
ADDFHX2TS U3262 ( .A(n4308), .B(n4307), .CI(n4306), .CO(n4735), .S(n4361) );
ADDFHX2TS U3263 ( .A(n4901), .B(n4900), .CI(n4899), .CO(n5085), .S(n4941) );
OAI22X2TS U3264 ( .A0(n6309), .A1(n4778), .B0(n6254), .B1(n4895), .Y(n4901)
);
ADDFHX4TS U3265 ( .A(n4994), .B(n4993), .CI(n4992), .CO(n5008), .S(n5004) );
ADDFHX4TS U3266 ( .A(n4958), .B(n4957), .CI(n4956), .CO(n5155), .S(n4861) );
ADDFHX4TS U3267 ( .A(n4787), .B(n4786), .CI(n4785), .CO(n4868), .S(n4822) );
ADDFHX4TS U3268 ( .A(n4126), .B(n4125), .CI(n4124), .CO(n4396), .S(n4388) );
ADDFHX2TS U3269 ( .A(n4111), .B(n4110), .CI(n4109), .CO(n4238), .S(n4066) );
ADDFHX4TS U3270 ( .A(n3661), .B(n3660), .CI(n3659), .CO(n3849), .S(n3738) );
XNOR2X2TS U3271 ( .A(n2797), .B(n6131), .Y(n3210) );
BUFX12TS U3272 ( .A(n8138), .Y(n7748) );
OAI21X2TS U3273 ( .A0(n7694), .A1(n7693), .B0(n7692), .Y(n7695) );
ADDFHX2TS U3274 ( .A(n4180), .B(n4179), .CI(n4178), .CO(n4285), .S(n4181) );
OAI21X4TS U3275 ( .A0(n8083), .A1(n8075), .B0(n8084), .Y(n5055) );
NOR2X8TS U3276 ( .A(n7564), .B(n7225), .Y(n7450) );
ADDFHX2TS U3277 ( .A(n3037), .B(n3036), .CI(n3035), .CO(n3395), .S(n2973) );
NOR2X8TS U3278 ( .A(n5032), .B(n5031), .Y(n8165) );
ADDFHX4TS U3279 ( .A(n4235), .B(n4234), .CI(n4233), .CO(n4280), .S(n4169) );
ADDFHX2TS U3280 ( .A(n4096), .B(n4095), .CI(n4094), .CO(n4223), .S(n4045) );
NOR2X6TS U3281 ( .A(n8125), .B(n8129), .Y(n8074) );
CLKBUFX2TS U3282 ( .A(n7351), .Y(n8078) );
AOI21X1TS U3283 ( .A0(n7825), .A1(n7817), .B0(n5262), .Y(n5061) );
ADDFHX2TS U3284 ( .A(n4446), .B(n4445), .CI(n4444), .CO(n4452), .S(n4475) );
NAND2X4TS U3285 ( .A(n5049), .B(n5050), .Y(n8130) );
NOR2X6TS U3286 ( .A(n8161), .B(n8165), .Y(n5034) );
ADDFHX4TS U3287 ( .A(n1634), .B(n1633), .CI(n1632), .CO(n2618), .S(n2617) );
NAND2X8TS U3288 ( .A(n963), .B(n642), .Y(n4581) );
ADDFHX2TS U3289 ( .A(n1406), .B(n1405), .CI(n1404), .CO(n2751), .S(n1458) );
INVX12TS U3290 ( .A(n4441), .Y(n3838) );
ADDFHX4TS U3291 ( .A(n3480), .B(n3479), .CI(n3478), .CO(n3520), .S(n3519) );
NAND2X4TS U3292 ( .A(n2608), .B(n2607), .Y(n7854) );
ADDFHX4TS U3293 ( .A(n3381), .B(n3380), .CI(n3379), .CO(n3628), .S(n3437) );
ADDFHX2TS U3294 ( .A(n3348), .B(n3347), .CI(n3346), .CO(n3550), .S(n3419) );
ADDFHX2TS U3295 ( .A(n3237), .B(n3236), .CI(n3235), .CO(n3348), .S(n3412) );
ADDFHX2TS U3296 ( .A(n3252), .B(n3251), .CI(n3250), .CO(n3557), .S(n3346) );
AOI21X2TS U3297 ( .A0(n8088), .A1(n8066), .B0(n8067), .Y(n8097) );
OAI21X1TS U3298 ( .A0(n8115), .A1(n8114), .B0(n8113), .Y(n8116) );
NOR2X4TS U3299 ( .A(n7936), .B(n7938), .Y(n8158) );
NOR2X8TS U3300 ( .A(n8096), .B(n8100), .Y(n5044) );
NOR2X8TS U3301 ( .A(n5042), .B(n5041), .Y(n8100) );
NOR2X8TS U3302 ( .A(n8112), .B(n5046), .Y(n8107) );
AOI21X4TS U3303 ( .A0(n7877), .A1(n7883), .B0(n2639), .Y(n2640) );
XNOR2X2TS U3304 ( .A(n8210), .B(n1491), .Y(n1121) );
ADDFHX2TS U3305 ( .A(n2365), .B(n2364), .CI(n2363), .CO(n2367), .S(n2430) );
INVX6TS U3306 ( .A(n8106), .Y(n8126) );
ADDFHX2TS U3307 ( .A(n3285), .B(n3284), .CI(n3283), .CO(n3316), .S(n3236) );
NOR2X8TS U3308 ( .A(n7489), .B(n7252), .Y(n7470) );
NAND2X6TS U3309 ( .A(n7499), .B(n7510), .Y(n7252) );
NOR2X4TS U3310 ( .A(n7808), .B(n7642), .Y(n7644) );
AOI2BB2X4TS U3311 ( .B0(n2919), .B1(n2918), .A0N(n5414), .A1N(n2980), .Y(
n2920) );
NOR2X6TS U3312 ( .A(n7213), .B(n7212), .Y(n7374) );
ADDFHX2TS U3313 ( .A(n4314), .B(n4313), .CI(n4312), .CO(n4744), .S(n4327) );
ADDFHX2TS U3314 ( .A(n4215), .B(n4214), .CI(n4213), .CO(n4313), .S(n4222) );
AOI21X2TS U3315 ( .A0(n7829), .A1(n710), .B0(n7828), .Y(n7834) );
NOR2X1TS U3316 ( .A(n8123), .B(n7827), .Y(n7829) );
NOR2X1TS U3317 ( .A(n6487), .B(n4101), .Y(n4103) );
ADDFHX4TS U3318 ( .A(n5256), .B(n5255), .CI(n5254), .CO(n5259), .S(n5159) );
ADDFHX4TS U3319 ( .A(n5067), .B(n5066), .CI(n5065), .CO(n5256), .S(n5157) );
OAI21X4TS U3320 ( .A0(n8739), .A1(n8743), .B0(n8744), .Y(n8678) );
ADDHX1TS U3321 ( .A(n2169), .B(n2168), .CO(n2233), .S(n2174) );
ADDFHX4TS U3322 ( .A(n1628), .B(n1627), .CI(n1626), .CO(n1636), .S(n2353) );
ADDFHX4TS U3323 ( .A(n4403), .B(n4402), .CI(n4401), .CO(n5037), .S(n5035) );
ADDFHX4TS U3324 ( .A(n4397), .B(n4396), .CI(n4395), .CO(n4399), .S(n4401) );
NOR2X8TS U3325 ( .A(n7580), .B(n7305), .Y(n7307) );
NAND2X6TS U3326 ( .A(n7587), .B(n7626), .Y(n7305) );
OAI21X4TS U3327 ( .A0(n7533), .A1(n7532), .B0(n7531), .Y(n7534) );
NOR2X8TS U3328 ( .A(n7300), .B(n7299), .Y(n7621) );
ADDFHX4TS U3329 ( .A(n5929), .B(n5928), .CI(n5927), .CO(n7300), .S(n7293) );
NOR2X4TS U3330 ( .A(n7818), .B(n7821), .Y(n7824) );
INVX16TS U3331 ( .A(Op_MX[27]), .Y(n6108) );
XNOR2X2TS U3332 ( .A(n8224), .B(n4888), .Y(n4493) );
XOR2X4TS U3333 ( .A(n8086), .B(n8085), .Y(n8087) );
AOI21X2TS U3334 ( .A0(n710), .A1(n8082), .B0(n8081), .Y(n8086) );
OAI21X1TS U3335 ( .A0(n8126), .A1(n8080), .B0(n8079), .Y(n8081) );
XNOR2X4TS U3336 ( .A(n7540), .B(n7539), .Y(n7542) );
AOI21X4TS U3337 ( .A0(n676), .A1(n7535), .B0(n7534), .Y(n7540) );
XOR2X4TS U3338 ( .A(n7699), .B(n908), .Y(n7701) );
OAI21X2TS U3339 ( .A0(n7701), .A1(n8595), .B0(n7700), .Y(Sgf_operation_n11)
);
XNOR2X4TS U3340 ( .A(n7438), .B(n7437), .Y(n7440) );
XNOR2X2TS U3341 ( .A(n5631), .B(n2866), .Y(n3155) );
XOR2X4TS U3342 ( .A(n7707), .B(n888), .Y(n7709) );
XNOR2X4TS U3343 ( .A(n7834), .B(n7833), .Y(n7836) );
NAND4XLTS U3344 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n8757) );
BUFX12TS U3345 ( .A(n5789), .Y(n4112) );
NOR2X4TS U3346 ( .A(n7277), .B(n7278), .Y(n7611) );
INVX8TS U3347 ( .A(n4425), .Y(n4208) );
INVX2TS U3348 ( .A(n863), .Y(n861) );
NAND2X4TS U3349 ( .A(n7426), .B(n7226), .Y(n7227) );
OR2X4TS U3350 ( .A(n7201), .B(n7451), .Y(n7211) );
NAND2X4TS U3351 ( .A(n8692), .B(n2099), .Y(n853) );
NOR2X6TS U3352 ( .A(n8045), .B(n8035), .Y(n3513) );
NOR2X4TS U3353 ( .A(n3515), .B(n3514), .Y(n7914) );
NOR2X6TS U3354 ( .A(n5028), .B(n5027), .Y(n7938) );
INVX2TS U3355 ( .A(n8618), .Y(n8659) );
NAND2X4TS U3356 ( .A(n2339), .B(n2338), .Y(n8713) );
INVX2TS U3357 ( .A(n8630), .Y(n8700) );
INVX2TS U3358 ( .A(n8523), .Y(n8542) );
AOI21X2TS U3359 ( .A0(n8204), .A1(n5064), .B0(n5063), .Y(n5161) );
AOI21X2TS U3360 ( .A0(n8204), .A1(n7365), .B0(n7364), .Y(n7370) );
AOI21X2TS U3361 ( .A0(n710), .A1(n7409), .B0(n7408), .Y(n7412) );
NOR2X1TS U3362 ( .A(n7340), .B(n7388), .Y(n7344) );
INVX2TS U3363 ( .A(n7613), .Y(n7615) );
AOI21X2TS U3364 ( .A0(n676), .A1(n7578), .B0(n7584), .Y(n7446) );
AOI21X2TS U3365 ( .A0(n676), .A1(n7387), .B0(n7341), .Y(n7391) );
AOI21X2TS U3366 ( .A0(n870), .A1(n7682), .B0(n7681), .Y(n7686) );
OAI21X2TS U3367 ( .A0(n7680), .A1(n7679), .B0(n7678), .Y(n7681) );
OAI21X2TS U3368 ( .A0(n7506), .A1(n7505), .B0(n7504), .Y(n7507) );
NAND2X4TS U3369 ( .A(n7240), .B(n7239), .Y(n7727) );
INVX2TS U3370 ( .A(n8162), .Y(n7889) );
INVX4TS U3371 ( .A(n7178), .Y(n5879) );
XNOR2X1TS U3372 ( .A(n6143), .B(n4671), .Y(n4781) );
XNOR2X1TS U3373 ( .A(n5990), .B(n4406), .Y(n4206) );
NAND2BX1TS U3374 ( .AN(n3254), .B(n7016), .Y(n3255) );
OAI22X1TS U3375 ( .A0(n5350), .A1(n5349), .B0(n5720), .B1(n5441), .Y(n5433)
);
CLKINVX6TS U3376 ( .A(Op_MY[23]), .Y(n6416) );
XNOR2X1TS U3377 ( .A(n5979), .B(n712), .Y(n5876) );
INVX2TS U3378 ( .A(n4936), .Y(n4775) );
OAI22X1TS U3379 ( .A0(n4780), .A1(n5193), .B0(n6677), .B1(n5323), .Y(n5344)
);
XNOR2X1TS U3380 ( .A(n6166), .B(n741), .Y(n5126) );
BUFX3TS U3381 ( .A(n997), .Y(n5475) );
AO21XLTS U3382 ( .A0(n4085), .A1(n803), .B0(n5092), .Y(n5194) );
XNOR2X1TS U3383 ( .A(n1944), .B(n5783), .Y(n3176) );
XNOR2X1TS U3384 ( .A(n5784), .B(n3044), .Y(n3160) );
BUFX3TS U3385 ( .A(n928), .Y(n4116) );
OAI22X1TS U3386 ( .A0(n6795), .A1(n1439), .B0(n4892), .B1(n2661), .Y(n2724)
);
OAI22X1TS U3387 ( .A0(n5535), .A1(n4003), .B0(n4002), .B1(n4100), .Y(n4060)
);
NAND2BXLTS U3388 ( .AN(n3642), .B(n626), .Y(n1364) );
XNOR2X1TS U3389 ( .A(n742), .B(n3774), .Y(n956) );
XNOR2X1TS U3390 ( .A(n4404), .B(n4504), .Y(n1370) );
ADDFX2TS U3391 ( .A(n1326), .B(n1325), .CI(n1324), .CO(n1469), .S(n1320) );
OAI22X1TS U3392 ( .A0(n2663), .A1(n991), .B0(n1094), .B1(n2961), .Y(n1131)
);
ADDFX2TS U3393 ( .A(n3829), .B(n3828), .CI(n3827), .CO(n3950), .S(n3824) );
OAI22X1TS U3394 ( .A0(n6264), .A1(n3729), .B0(n6406), .B1(n3788), .Y(n3769)
);
OAI22X1TS U3395 ( .A0(n1838), .A1(n1003), .B0(n1002), .B1(n1822), .Y(n1174)
);
XNOR2X1TS U3396 ( .A(n767), .B(n2247), .Y(n2120) );
XNOR2X1TS U3397 ( .A(n765), .B(n3044), .Y(n2158) );
XNOR2X1TS U3398 ( .A(n742), .B(n3159), .Y(n1605) );
ADDFX2TS U3399 ( .A(n5600), .B(n5599), .CI(n5598), .CO(n5728), .S(n5611) );
BUFX3TS U3400 ( .A(n3200), .Y(n6437) );
BUFX4TS U3401 ( .A(n6019), .Y(n6406) );
AO21XLTS U3402 ( .A0(n5522), .A1(n3928), .B0(n6370), .Y(n6339) );
OAI22X1TS U3403 ( .A0(n704), .A1(n5661), .B0(n6453), .B1(n5685), .Y(n5749)
);
ADDFHX2TS U3404 ( .A(n5696), .B(n5695), .CI(n5694), .CO(n5915), .S(n5698) );
INVX2TS U3405 ( .A(n6028), .Y(n5976) );
OAI22X1TS U3406 ( .A0(n6820), .A1(n5775), .B0(n6778), .B1(n5878), .Y(n5865)
);
OAI22X1TS U3407 ( .A0(n5206), .A1(n5205), .B0(n5318), .B1(n5534), .Y(n5321)
);
OAI22X1TS U3408 ( .A0(n6750), .A1(n5234), .B0(n731), .B1(n5303), .Y(n5287)
);
ADDFHX2TS U3409 ( .A(n5467), .B(n5466), .CI(n5465), .CO(n5553), .S(n5514) );
AO21X1TS U3410 ( .A0(n6429), .A1(n6428), .B0(n6427), .Y(n6509) );
OAI22X1TS U3411 ( .A0(n6459), .A1(n5942), .B0(n6138), .B1(n6070), .Y(n6060)
);
XNOR2X1TS U3412 ( .A(n8814), .B(n6647), .Y(n6675) );
INVX6TS U3413 ( .A(n1363), .Y(n6642) );
INVX2TS U3414 ( .A(n6122), .Y(n6112) );
OAI22X1TS U3415 ( .A0(n6156), .A1(n6155), .B0(n787), .B1(n6106), .Y(n6111)
);
OAI22X1TS U3416 ( .A0(n6225), .A1(n6150), .B0(n6145), .B1(n6144), .Y(n6182)
);
AO21XLTS U3417 ( .A0(n5625), .A1(n6365), .B0(n6201), .Y(n6239) );
ADDFX2TS U3418 ( .A(n4772), .B(n4771), .CI(n4770), .CO(n4949), .S(n4796) );
OAI22X1TS U3419 ( .A0(n5113), .A1(n4894), .B0(n731), .B1(n5112), .Y(n5115)
);
ADDFHX2TS U3420 ( .A(n3375), .B(n3374), .CI(n3373), .CO(n3392), .S(n3424) );
ADDFX2TS U3421 ( .A(n2977), .B(n2976), .CI(n2975), .CO(n3408), .S(n3057) );
ADDFHX2TS U3422 ( .A(n2698), .B(n2697), .CI(n2696), .CO(n2710), .S(n2748) );
OAI22X1TS U3423 ( .A0(n761), .A1(n2891), .B0(n828), .B1(n3016), .Y(n3000) );
OAI22X1TS U3424 ( .A0(n4556), .A1(n2865), .B0(n3116), .B1(n2931), .Y(n2996)
);
ADDFX2TS U3425 ( .A(n2877), .B(n2876), .CI(n2875), .CO(n3008), .S(n2827) );
ADDFX2TS U3426 ( .A(n4736), .B(n4735), .CI(n4734), .CO(n4981), .S(n4745) );
ADDFX2TS U3427 ( .A(n4183), .B(n4182), .CI(n4181), .CO(n4283), .S(n4189) );
OAI22X1TS U3428 ( .A0(n702), .A1(n1124), .B0(n4487), .B1(n1377), .Y(n1359)
);
OAI22X1TS U3429 ( .A0(n2783), .A1(n1081), .B0(n2031), .B1(n1137), .Y(n1109)
);
ADDFX2TS U3430 ( .A(n3767), .B(n3766), .CI(n3765), .CO(n3856), .S(n3757) );
BUFX3TS U3431 ( .A(n4404), .Y(n4681) );
OAI22X1TS U3432 ( .A0(n761), .A1(n2248), .B0(n827), .B1(n2260), .Y(n2309) );
NAND2BX1TS U3433 ( .AN(n2243), .B(n865), .Y(n864) );
INVX2TS U3434 ( .A(n5956), .Y(n865) );
OAI22X1TS U3435 ( .A0(n2457), .A1(n6427), .B0(n2210), .B1(n6428), .Y(n2251)
);
ADDFX2TS U3436 ( .A(n2165), .B(n2164), .CI(n2163), .CO(n2222), .S(n2144) );
OAI22X1TS U3437 ( .A0(n2281), .A1(n1694), .B0(n2414), .B1(n1697), .Y(n1720)
);
ADDHX1TS U3438 ( .A(n1718), .B(n1717), .CO(n1741), .S(n1769) );
BUFX3TS U3439 ( .A(n932), .Y(n5666) );
BUFX4TS U3440 ( .A(n802), .Y(n2704) );
XNOR2X1TS U3441 ( .A(n2296), .B(n4850), .Y(n1789) );
BUFX6TS U3442 ( .A(n4880), .Y(n4289) );
XNOR2X1TS U3443 ( .A(n1945), .B(n742), .Y(n1847) );
BUFX3TS U3444 ( .A(n930), .Y(n5534) );
ADDFHX2TS U3445 ( .A(n1549), .B(n1548), .CI(n1547), .CO(n1544), .S(n1598) );
ADDFHX2TS U3446 ( .A(n2403), .B(n2402), .CI(n2401), .CO(n2405), .S(n2469) );
ADDFHX2TS U3447 ( .A(n6375), .B(n6374), .CI(n6373), .CO(n6360), .S(n6448) );
ADDFHX2TS U3448 ( .A(n6547), .B(n6546), .CI(n6545), .CO(n6556), .S(n6581) );
ADDFHX2TS U3449 ( .A(n6541), .B(n6540), .CI(n6539), .CO(n6583), .S(n6598) );
ADDFHX2TS U3450 ( .A(n6046), .B(n6045), .CI(n6044), .CO(n6603), .S(n6007) );
INVX4TS U3451 ( .A(n6954), .Y(n6208) );
CLKINVX6TS U3452 ( .A(Op_MY[41]), .Y(n6947) );
OAI22X1TS U3453 ( .A0(n6750), .A1(n6689), .B0(n732), .B1(n6688), .Y(n6727)
);
ADDFHX2TS U3454 ( .A(n6221), .B(n6220), .CI(n6219), .CO(n6273), .S(n6229) );
ADDFHX2TS U3455 ( .A(n6130), .B(n6129), .CI(n6128), .CO(n6228), .S(n6361) );
OAI22X1TS U3456 ( .A0(n6860), .A1(n6250), .B0(n6859), .B1(n6290), .Y(n6285)
);
ADDFX2TS U3457 ( .A(n6295), .B(n6294), .CI(n6293), .CO(n7069), .S(n6282) );
ADDFX2TS U3458 ( .A(n4949), .B(n4948), .CI(n4947), .CO(n5073), .S(n4921) );
ADDFHX2TS U3459 ( .A(n5182), .B(n5181), .CI(n5180), .CO(n5338), .S(n5248) );
ADDFHX2TS U3460 ( .A(n2754), .B(n2753), .CI(n2752), .CO(n2824), .S(n2774) );
ADDFHX2TS U3461 ( .A(n2830), .B(n2829), .CI(n2828), .CO(n3080), .S(n2822) );
ADDFHX2TS U3462 ( .A(n3142), .B(n3141), .CI(n3140), .CO(n3602), .S(n3381) );
ADDFX2TS U3463 ( .A(n3635), .B(n3634), .CI(n3633), .CO(n3844), .S(n3732) );
ADDFX2TS U3464 ( .A(n3557), .B(n3556), .CI(n3555), .CO(n3655), .S(n3549) );
ADDFHX2TS U3465 ( .A(n3887), .B(n3886), .CI(n3885), .CO(n4165), .S(n3882) );
ADDFHX2TS U3466 ( .A(n1211), .B(n1210), .CI(n1209), .CO(n1206), .S(n1577) );
ADDHXLTS U3467 ( .A(n2044), .B(n2043), .CO(n2040), .S(n2077) );
ADDHXLTS U3468 ( .A(n1987), .B(n1986), .CO(n2067), .S(n2008) );
ADDFHX2TS U3469 ( .A(n1161), .B(n1160), .CI(n1159), .CO(n1336), .S(n1166) );
ADDFHX2TS U3470 ( .A(n1787), .B(n1786), .CI(n1785), .CO(n1801), .S(n1827) );
BUFX3TS U3471 ( .A(n951), .Y(n4845) );
INVX6TS U3472 ( .A(n4294), .Y(n1947) );
BUFX3TS U3473 ( .A(n640), .Y(n2150) );
BUFX3TS U3474 ( .A(n3069), .Y(n1993) );
ADDFHX2TS U3475 ( .A(n1483), .B(n1482), .CI(n1481), .CO(n1478), .S(n1637) );
ADDFHX2TS U3476 ( .A(n4946), .B(n4945), .CI(n4944), .CO(n5153), .S(n4867) );
INVX4TS U3477 ( .A(n4514), .Y(n7016) );
ADDFHX2TS U3478 ( .A(n6043), .B(n6042), .CI(n6041), .CO(n6604), .S(n6001) );
ADDFHX2TS U3479 ( .A(n5421), .B(n5420), .CI(n5419), .CO(n5458), .S(n5370) );
ADDFHX2TS U3480 ( .A(n6589), .B(n6588), .CI(n6587), .CO(n6617), .S(n6608) );
ADDFHX2TS U3481 ( .A(n6586), .B(n6585), .CI(n6584), .CO(n6609), .S(n6602) );
AO21XLTS U3482 ( .A0(n6891), .A1(n6890), .B0(n1363), .Y(n6923) );
OAI22X1TS U3483 ( .A0(n6953), .A1(n6888), .B0(n740), .B1(n6934), .Y(n6924)
);
ADDFX2TS U3484 ( .A(n4857), .B(n4856), .CI(n4855), .CO(n4864), .S(n4824) );
ADDFX2TS U3485 ( .A(n4721), .B(n4720), .CI(n4719), .CO(n4821), .S(n5018) );
ADDFHX2TS U3486 ( .A(n5073), .B(n5072), .CI(n5071), .CO(n5252), .S(n5152) );
ADDFHX2TS U3487 ( .A(n5214), .B(n5213), .CI(n5212), .CO(n5271), .S(n5251) );
ADDFHX2TS U3488 ( .A(n4967), .B(n4966), .CI(n4965), .CO(n4998), .S(n5003) );
ADDFX2TS U3489 ( .A(n4266), .B(n4265), .CI(n4264), .CO(n4353), .S(n4262) );
INVX4TS U3490 ( .A(n3969), .Y(n1945) );
ADDFHX2TS U3491 ( .A(n4869), .B(n4868), .CI(n4867), .CO(n5066), .S(n4863) );
OAI21X2TS U3492 ( .A0(n7830), .A1(n7820), .B0(n7831), .Y(n5261) );
NOR2X4TS U3493 ( .A(n7632), .B(n7635), .Y(n7576) );
ADDFHX2TS U3494 ( .A(n5544), .B(n5543), .CI(n5542), .CO(n6080), .S(n5545) );
NOR2X6TS U3495 ( .A(n7201), .B(n7452), .Y(n7226) );
ADDFHX2TS U3496 ( .A(n5962), .B(n5961), .CI(n5960), .CO(n6076), .S(n5927) );
ADDFHX2TS U3497 ( .A(n5365), .B(n5364), .CI(n5363), .CO(n5455), .S(n5366) );
NAND2X2TS U3498 ( .A(n7476), .B(n7641), .Y(n7471) );
ADDFHX2TS U3499 ( .A(n6805), .B(n6804), .CI(n6803), .CO(n6873), .S(n6806) );
ADDFHX2TS U3500 ( .A(n7114), .B(n7113), .CI(n7112), .CO(n6766), .S(n7126) );
NAND2X4TS U3501 ( .A(n7394), .B(n7238), .Y(n7714) );
ADDFHX2TS U3502 ( .A(n5018), .B(n5017), .CI(n5016), .CO(n5019), .S(n5022) );
INVX2TS U3503 ( .A(n7884), .Y(n2639) );
ADDFHX2TS U3504 ( .A(n5003), .B(n5002), .CI(n5001), .CO(n5013), .S(n5005) );
INVX2TS U3505 ( .A(n8814), .Y(n700) );
ADDFHX2TS U3506 ( .A(n3814), .B(n3813), .CI(n3812), .CO(n3961), .S(n3848) );
ADDFHX2TS U3507 ( .A(n2525), .B(n2524), .CI(n2523), .CO(n2616), .S(n2610) );
NOR2X1TS U3508 ( .A(n7901), .B(n7930), .Y(n7905) );
NOR2X6TS U3509 ( .A(n7360), .B(n7366), .Y(n7817) );
NAND2X1TS U3510 ( .A(n7578), .B(n7576), .Y(n7603) );
CLKINVX3TS U3511 ( .A(n7472), .Y(n7807) );
INVX2TS U3512 ( .A(n7902), .Y(n7927) );
INVX2TS U3513 ( .A(n8026), .Y(n7924) );
NAND2X1TS U3514 ( .A(n7565), .B(n7568), .Y(n7771) );
OAI21X1TS U3515 ( .A0(n7581), .A1(n7580), .B0(n7579), .Y(n7582) );
NAND2X2TS U3516 ( .A(n7734), .B(n7646), .Y(n7677) );
NAND2X2TS U3517 ( .A(n7565), .B(n7496), .Y(n7503) );
INVX2TS U3518 ( .A(n5262), .Y(n7822) );
NAND2X1TS U3519 ( .A(n7824), .B(n7819), .Y(n7827) );
INVX2TS U3520 ( .A(n2629), .Y(n867) );
NAND2X1TS U3521 ( .A(n7905), .B(n7924), .Y(n7907) );
INVX2TS U3522 ( .A(n8202), .Y(n7937) );
NAND2X2TS U3523 ( .A(n5028), .B(n5027), .Y(n7939) );
OAI21X1TS U3524 ( .A0(n8017), .A1(n7880), .B0(n7879), .Y(n7881) );
NOR2X1TS U3525 ( .A(n8123), .B(n8125), .Y(n8128) );
AND2X2TS U3526 ( .A(n7734), .B(n7745), .Y(n7747) );
NAND2X1TS U3527 ( .A(n7924), .B(n8028), .Y(n7917) );
INVX2TS U3528 ( .A(n7594), .Y(n7434) );
INVX2TS U3529 ( .A(n8075), .Y(n8076) );
INVX2TS U3530 ( .A(n8112), .Y(n8089) );
NAND2X4TS U3531 ( .A(n5048), .B(n5047), .Y(n8124) );
INVX2TS U3532 ( .A(n7936), .Y(n8201) );
NAND4XLTS U3533 ( .A(n8823), .B(n8822), .C(n8821), .D(n8820), .Y(n8824) );
INVX8TS U3534 ( .A(n5794), .Y(n8812) );
INVX4TS U3535 ( .A(n6954), .Y(n8221) );
INVX4TS U3536 ( .A(n4514), .Y(n8214) );
XNOR2X1TS U3537 ( .A(n7964), .B(n7963), .Y(n7965) );
OAI21X1TS U3538 ( .A0(n7986), .A1(n7960), .B0(n7959), .Y(n7964) );
NAND2X1TS U3539 ( .A(n7973), .B(n7972), .Y(n7974) );
NAND2X1TS U3540 ( .A(n7979), .B(n7978), .Y(n7980) );
MX2X1TS U3541 ( .A(n8730), .B(P_Sgf[20]), .S0(n8638), .Y(Sgf_operation_n89)
);
INVX2TS U3542 ( .A(n8666), .Y(n8673) );
NAND2X1TS U3543 ( .A(n8709), .B(n8708), .Y(n8710) );
NAND2X1TS U3544 ( .A(n7951), .B(n7950), .Y(n7952) );
OR2X1TS U3545 ( .A(n8586), .B(n8585), .Y(n8588) );
NAND2X1TS U3546 ( .A(n7944), .B(n7947), .Y(n7945) );
XOR2X1TS U3547 ( .A(n8061), .B(n7899), .Y(n7900) );
XNOR2X1TS U3548 ( .A(n8020), .B(n7895), .Y(n7896) );
NAND2X1TS U3549 ( .A(n7894), .B(n8001), .Y(n7895) );
XNOR2X1TS U3550 ( .A(n7857), .B(n7856), .Y(n7858) );
NAND2X1TS U3551 ( .A(n7855), .B(n7854), .Y(n7856) );
OAI21X1TS U3552 ( .A0(n7986), .A1(n7852), .B0(n7851), .Y(n7857) );
MX2X1TS U3553 ( .A(n8574), .B(FSM_add_overflow_flag), .S0(n8396), .Y(n419)
);
NAND2X1TS U3554 ( .A(n7368), .B(n7367), .Y(n7369) );
NAND2X1TS U3555 ( .A(n8136), .B(n8135), .Y(n8137) );
NAND2X1TS U3556 ( .A(n726), .B(P_Sgf[72]), .Y(n7609) );
NAND2X1TS U3557 ( .A(n8753), .B(P_Sgf[67]), .Y(n7617) );
NAND2X1TS U3558 ( .A(n7444), .B(n7631), .Y(n7445) );
NAND2X1TS U3559 ( .A(n682), .B(P_Sgf[83]), .Y(n7439) );
NAND2X1TS U3560 ( .A(n7436), .B(n7592), .Y(n7437) );
NAND2X1TS U3561 ( .A(n891), .B(n7559), .Y(n7560) );
NAND2X1TS U3562 ( .A(n7571), .B(n7772), .Y(n7572) );
NAND2X1TS U3563 ( .A(n726), .B(P_Sgf[74]), .Y(n7589) );
NAND2X1TS U3564 ( .A(n727), .B(P_Sgf[76]), .Y(n7385) );
NAND2X1TS U3565 ( .A(n726), .B(P_Sgf[77]), .Y(n7380) );
NAND2X1TS U3566 ( .A(n726), .B(P_Sgf[88]), .Y(n7541) );
NAND2X1TS U3567 ( .A(n727), .B(P_Sgf[91]), .Y(n7501) );
NAND2X1TS U3568 ( .A(n8638), .B(P_Sgf[92]), .Y(n7512) );
CLKAND2X2TS U3569 ( .A(n7720), .B(n7719), .Y(n912) );
XOR2X1TS U3570 ( .A(n8121), .B(n8120), .Y(n8122) );
AOI21X1TS U3571 ( .A0(n710), .A1(n8117), .B0(n8116), .Y(n8121) );
XOR2X1TS U3572 ( .A(n8072), .B(n8071), .Y(n8073) );
XOR2X1TS U3573 ( .A(n8110), .B(n8109), .Y(n8111) );
AOI21X1TS U3574 ( .A0(n710), .A1(n8107), .B0(n8106), .Y(n8110) );
XOR2X1TS U3575 ( .A(n8024), .B(n8023), .Y(n8025) );
AOI21X1TS U3576 ( .A0(n8020), .A1(n8019), .B0(n8018), .Y(n8024) );
MX2X1TS U3577 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n8234), .Y(n476) );
MX2X1TS U3578 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n8234), .Y(n479) );
MX2X1TS U3579 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n8232), .Y(n495) );
MX2X1TS U3580 ( .A(Data_MY[41]), .B(Op_MY[41]), .S0(n8231), .Y(n516) );
MX2X1TS U3581 ( .A(Data_MX[36]), .B(Op_MX[36]), .S0(n8230), .Y(n575) );
XOR2X4TS U3582 ( .A(n1397), .B(n1396), .Y(n652) );
XOR2X4TS U3583 ( .A(n1395), .B(n652), .Y(n2632) );
NAND2X2TS U3584 ( .A(n1397), .B(n1395), .Y(n653) );
NAND2X2TS U3585 ( .A(n1396), .B(n1395), .Y(n654) );
NAND3X4TS U3586 ( .A(n654), .B(n653), .C(n655), .Y(n2636) );
ADDFHX4TS U3587 ( .A(n1233), .B(n1232), .CI(n1231), .CO(n1397), .S(n1315) );
NAND2X4TS U3588 ( .A(n2636), .B(n2635), .Y(n8022) );
OAI22X2TS U3589 ( .A0(n4371), .A1(n3839), .B0(n4370), .B1(n3935), .Y(n3892)
);
INVX2TS U3590 ( .A(n8694), .Y(n8697) );
NOR2X4TS U3591 ( .A(n7679), .B(n7683), .Y(n7261) );
OAI22X1TS U3592 ( .A0(n3596), .A1(n2298), .B0(n2418), .B1(n906), .Y(n2428)
);
ADDFX2TS U3593 ( .A(n2504), .B(n2503), .CI(n2502), .CO(n2498), .S(n2548) );
ADDFHX2TS U3594 ( .A(n2576), .B(n2575), .CI(n2574), .CO(n2601), .S(n2600) );
NAND2X8TS U3595 ( .A(n8011), .B(n7996), .Y(n2628) );
ADDFHX2TS U3596 ( .A(n5729), .B(n5728), .CI(n5727), .CO(n5762), .S(n5759) );
ADDFX2TS U3597 ( .A(n5282), .B(n5281), .CI(n5280), .CO(n5371), .S(n5278) );
ADDFHX2TS U3598 ( .A(n4159), .B(n4158), .CI(n4157), .CO(n4265), .S(n4160) );
ADDFHX4TS U3599 ( .A(n3761), .B(n3760), .CI(n3759), .CO(n3955), .S(n3814) );
OAI22X1TS U3600 ( .A0(n6429), .A1(n4604), .B0(n828), .B1(n4485), .Y(n4533)
);
OAI22X1TS U3601 ( .A0(n6429), .A1(n4804), .B0(n829), .B1(n4918), .Y(n4912)
);
ADDFHX2TS U3602 ( .A(n6452), .B(n6451), .CI(n6450), .CO(n6523), .S(n6568) );
NOR2X8TS U3603 ( .A(n2608), .B(n2607), .Y(n7853) );
NAND2X4TS U3604 ( .A(n2606), .B(n2605), .Y(n7979) );
AOI21X4TS U3605 ( .A0(n917), .A1(n3505), .B0(n3504), .Y(n656) );
AOI21X1TS U3606 ( .A0(n917), .A1(n3505), .B0(n3504), .Y(n8051) );
ADDFHX2TS U3607 ( .A(n3610), .B(n3609), .CI(n3608), .CO(n3648), .S(n3585) );
ADDFHX2TS U3608 ( .A(n3468), .B(n3467), .CI(n3466), .CO(n3489), .S(n3485) );
OAI21X1TS U3609 ( .A0(n7342), .A1(n7388), .B0(n7390), .Y(n7343) );
NAND2X4TS U3610 ( .A(n7387), .B(n7287), .Y(n7630) );
BUFX12TS U3611 ( .A(n5190), .Y(n4408) );
NAND2X4TS U3612 ( .A(n7289), .B(n7288), .Y(n7631) );
ADDFHX4TS U3613 ( .A(n6092), .B(n6091), .CI(n6090), .CO(n7291), .S(n7288) );
ADDFHX4TS U3614 ( .A(n6095), .B(n6094), .CI(n6093), .CO(n7295), .S(n7290) );
ADDFHX2TS U3615 ( .A(n7117), .B(n7116), .CI(n7115), .CO(n7122), .S(n7125) );
NAND2X4TS U3616 ( .A(n2598), .B(n2597), .Y(n7950) );
AND2X4TS U3617 ( .A(n7310), .B(n7373), .Y(n914) );
ADDFHX2TS U3618 ( .A(n6307), .B(n6306), .CI(n6305), .CO(n7089), .S(n6279) );
OAI22X1TS U3619 ( .A0(n6886), .A1(n6310), .B0(n6746), .B1(n6675), .Y(n6736)
);
BUFX12TS U3620 ( .A(n6644), .Y(n6886) );
NAND2X8TS U3621 ( .A(n5381), .B(n3201), .Y(n6644) );
INVX8TS U3622 ( .A(n4207), .Y(n7055) );
INVX4TS U3623 ( .A(n667), .Y(n703) );
NAND2X4TS U3624 ( .A(n2630), .B(n2629), .Y(n7868) );
OR2X1TS U3625 ( .A(Op_MX[47]), .B(Op_MX[41]), .Y(n660) );
INVX4TS U3626 ( .A(n737), .Y(n740) );
OR2X4TS U3627 ( .A(FSM_selector_B[1]), .B(n8852), .Y(n661) );
BUFX3TS U3628 ( .A(n928), .Y(n6365) );
INVX2TS U3629 ( .A(n631), .Y(n689) );
INVX2TS U3630 ( .A(n5189), .Y(n8216) );
INVX2TS U3631 ( .A(n6825), .Y(n6248) );
BUFX8TS U3632 ( .A(n5258), .Y(n8204) );
INVX2TS U3633 ( .A(n7862), .Y(n7869) );
NAND2X6TS U3634 ( .A(n868), .B(n867), .Y(n7862) );
OR2X1TS U3635 ( .A(Op_MX[0]), .B(Op_MX[5]), .Y(n672) );
AOI21X4TS U3636 ( .A0(n8727), .A1(n8720), .B0(n2108), .Y(n2109) );
INVX6TS U3637 ( .A(n4669), .Y(n6987) );
CLKINVX12TS U3638 ( .A(Op_MX[43]), .Y(n4669) );
ADDFX2TS U3639 ( .A(n6435), .B(n6434), .CI(n6433), .CO(n6472), .S(n6516) );
ADDFX2TS U3640 ( .A(n1113), .B(n1112), .CI(n1111), .CO(n1378), .S(n1154) );
ADDFX2TS U3641 ( .A(n1155), .B(n1154), .CI(n1153), .CO(n1343), .S(n1159) );
ADDFHX4TS U3642 ( .A(n5157), .B(n5156), .CI(n5155), .CO(n5158), .S(n5060) );
OAI22X2TS U3643 ( .A0(n7174), .A1(n6124), .B0(n6746), .B1(n6226), .Y(n6188)
);
ADDFX2TS U3644 ( .A(n2651), .B(n2650), .CI(n2649), .CO(n2756), .S(n2749) );
OAI21X1TS U3645 ( .A0(n1807), .A1(n2033), .B0(n855), .Y(n1809) );
NAND2BX1TS U3646 ( .AN(n2031), .B(n856), .Y(n855) );
INVX4TS U3647 ( .A(n679), .Y(n680) );
INVX4TS U3648 ( .A(n8898), .Y(n3103) );
INVX4TS U3649 ( .A(n6917), .Y(n5707) );
INVX6TS U3650 ( .A(n4514), .Y(n698) );
XNOR2X2TS U3651 ( .A(n6401), .B(n6652), .Y(n6310) );
INVX6TS U3652 ( .A(n4514), .Y(n6401) );
INVX2TS U3653 ( .A(n700), .Y(n701) );
OAI22X1TS U3654 ( .A0(n6455), .A1(n5980), .B0(n6065), .B1(n3928), .Y(n6017)
);
INVX6TS U3655 ( .A(n6299), .Y(n5784) );
INVX6TS U3656 ( .A(n5150), .Y(n746) );
INVX6TS U3657 ( .A(n5150), .Y(n747) );
XNOR2X1TS U3658 ( .A(n1944), .B(n5708), .Y(n3150) );
INVX12TS U3659 ( .A(n6152), .Y(n752) );
INVX12TS U3660 ( .A(n6152), .Y(n753) );
INVX4TS U3661 ( .A(n757), .Y(n759) );
INVX6TS U3662 ( .A(n668), .Y(n763) );
XNOR2X2TS U3663 ( .A(n2296), .B(n706), .Y(n2397) );
INVX4TS U3664 ( .A(n629), .Y(n767) );
CLKBUFX3TS U3665 ( .A(n624), .Y(n8175) );
INVX2TS U3666 ( .A(n674), .Y(n772) );
ADDFHX2TS U3667 ( .A(n6236), .B(n6235), .CI(n6234), .CO(n6317), .S(n6266) );
NOR4X1TS U3668 ( .A(Op_MX[44]), .B(Op_MX[38]), .C(Op_MX[14]), .D(Op_MX[8]),
.Y(n8802) );
OAI22X2TS U3669 ( .A0(beg_FSM), .A1(n8939), .B0(ack_FSM), .B1(n8196), .Y(
n8768) );
NOR2X4TS U3670 ( .A(FS_Module_state_reg[3]), .B(n8770), .Y(n8830) );
NOR3XLTS U3671 ( .A(Op_MX[40]), .B(Op_MX[53]), .C(Op_MX[52]), .Y(n8820) );
INVX4TS U3672 ( .A(n8773), .Y(n8220) );
INVX4TS U3673 ( .A(n8766), .Y(n8230) );
INVX4TS U3674 ( .A(n8766), .Y(n8231) );
INVX4TS U3675 ( .A(n8766), .Y(n8222) );
INVX4TS U3676 ( .A(n8766), .Y(n8225) );
INVX4TS U3677 ( .A(n8766), .Y(n8227) );
INVX6TS U3678 ( .A(n6714), .Y(n778) );
INVX6TS U3679 ( .A(n6299), .Y(n4419) );
OAI22X1TS U3680 ( .A0(n6731), .A1(n3776), .B0(n4687), .B1(n3924), .Y(n3872)
);
BUFX3TS U3681 ( .A(n5622), .Y(n6109) );
OAI22X1TS U3682 ( .A0(n4610), .A1(n3783), .B0(n4608), .B1(n3894), .Y(n3875)
);
INVX4TS U3683 ( .A(n6461), .Y(n789) );
BUFX4TS U3684 ( .A(n628), .Y(n793) );
XNOR2X1TS U3685 ( .A(n793), .B(n4553), .Y(n4319) );
XNOR2X1TS U3686 ( .A(n8217), .B(n4405), .Y(n3906) );
XNOR2X1TS U3687 ( .A(n796), .B(n4406), .Y(n4026) );
INVX4TS U3688 ( .A(n6954), .Y(n797) );
XNOR2X1TS U3689 ( .A(n6100), .B(n762), .Y(n4527) );
INVX6TS U3690 ( .A(n6954), .Y(n6100) );
OAI22X1TS U3691 ( .A0(n3104), .A1(n1805), .B0(n808), .B1(n1763), .Y(n1795)
);
OAI22X1TS U3692 ( .A0(n3104), .A1(n2000), .B0(n807), .B1(n1849), .Y(n2049)
);
OAI22X1TS U3693 ( .A0(n4846), .A1(n3134), .B0(n807), .B1(n3221), .Y(n3312)
);
OAI22X1TS U3694 ( .A0(n2162), .A1(n1670), .B0(n3051), .B1(n1607), .Y(n2380)
);
INVX4TS U3695 ( .A(n957), .Y(n811) );
BUFX4TS U3696 ( .A(n6101), .Y(n812) );
OAI22X1TS U3697 ( .A0(n6482), .A1(n4528), .B0(n5414), .B1(n4527), .Y(n4653)
);
CLKINVX12TS U3698 ( .A(n5706), .Y(n5988) );
INVX8TS U3699 ( .A(n5988), .Y(n814) );
OAI22X1TS U3700 ( .A0(n817), .A1(n5690), .B0(n6453), .B1(n5881), .Y(n5909)
);
OAI22X1TS U3701 ( .A0(n5522), .A1(n3930), .B0(n5130), .B1(n4025), .Y(n4038)
);
XNOR2X1TS U3702 ( .A(n6069), .B(n4418), .Y(n4078) );
XNOR2X1TS U3703 ( .A(n5489), .B(n8233), .Y(n3705) );
XNOR2X1TS U3704 ( .A(n703), .B(n4372), .Y(n3002) );
INVX6TS U3705 ( .A(n6825), .Y(n6327) );
XNOR2X1TS U3706 ( .A(n1948), .B(n3986), .Y(n1214) );
XNOR2X1TS U3707 ( .A(n821), .B(n5662), .Y(n5603) );
BUFX6TS U3708 ( .A(n634), .Y(n826) );
OAI22X1TS U3709 ( .A0(n5191), .A1(n3934), .B0(n5190), .B1(n4028), .Y(n4053)
);
OAI22X1TS U3710 ( .A0(n5328), .A1(n3841), .B0(n3840), .B1(n3934), .Y(n3891)
);
NOR4X1TS U3711 ( .A(Op_MY[51]), .B(Op_MY[46]), .C(Op_MY[1]), .D(Op_MY[45]),
.Y(n8782) );
NOR4X1TS U3712 ( .A(Op_MY[41]), .B(Op_MY[16]), .C(Op_MY[9]), .D(Op_MY[6]),
.Y(n8779) );
NOR4X1TS U3713 ( .A(n626), .B(Op_MX[29]), .C(Op_MX[17]), .D(n2797), .Y(n8795) );
OAI22X1TS U3714 ( .A0(n2031), .A1(n1752), .B0(n2033), .B1(n854), .Y(n1781)
);
NOR2X2TS U3715 ( .A(n7335), .B(n7334), .Y(n7736) );
INVX4TS U3716 ( .A(n4424), .Y(n7184) );
NOR3XLTS U3717 ( .A(Op_MY[50]), .B(Op_MY[52]), .C(Op_MY[53]), .Y(n8786) );
NOR4X1TS U3718 ( .A(n630), .B(Op_MX[13]), .C(n8819), .D(Op_MX[62]), .Y(n8821) );
CLKBUFX2TS U3719 ( .A(P_Sgf[53]), .Y(n830) );
NOR2X4TS U3720 ( .A(n8257), .B(FSM_selector_C), .Y(n8513) );
INVX4TS U3721 ( .A(n8773), .Y(n8235) );
NAND2X1TS U3722 ( .A(n682), .B(P_Sgf[64]), .Y(n5163) );
NAND2X1TS U3723 ( .A(n776), .B(P_Sgf[63]), .Y(n7371) );
NAND2X1TS U3724 ( .A(n728), .B(P_Sgf[60]), .Y(n7358) );
BUFX3TS U3725 ( .A(n624), .Y(n8172) );
INVX2TS U3726 ( .A(rst), .Y(n831) );
NAND2X4TS U3727 ( .A(n7280), .B(n7279), .Y(n7614) );
NOR2X8TS U3728 ( .A(n7279), .B(n7280), .Y(n7281) );
NAND2X4TS U3729 ( .A(n2341), .B(n2340), .Y(n8709) );
NAND2X1TS U3730 ( .A(n8002), .B(n836), .Y(n8003) );
NOR2X8TS U3731 ( .A(n2620), .B(n835), .Y(n8007) );
AND2X8TS U3732 ( .A(n8000), .B(n836), .Y(n835) );
NAND2X8TS U3733 ( .A(n838), .B(n837), .Y(n836) );
XOR2X4TS U3734 ( .A(Op_MX[27]), .B(Op_MX[28]), .Y(n839) );
OAI21X4TS U3735 ( .A0(n840), .A1(n8113), .B0(n8118), .Y(n8067) );
NOR2X8TS U3736 ( .A(n5038), .B(n5037), .Y(n840) );
AOI2BB2X4TS U3737 ( .B0(n8665), .B1(n845), .A0N(n8719), .A1N(n846), .Y(n2110) );
NOR2BX4TS U3738 ( .AN(n848), .B(n2105), .Y(n847) );
OR2X8TS U3739 ( .A(n8666), .B(n849), .Y(n8717) );
OAI21X4TS U3740 ( .A0(n8630), .A1(n853), .B0(n852), .Y(n8665) );
AOI21X4TS U3741 ( .A0(n8694), .A1(n2099), .B0(n2098), .Y(n852) );
AOI21X4TS U3742 ( .A0(n2023), .A1(n8618), .B0(n2022), .Y(n8630) );
OAI21X4TS U3743 ( .A0(n8597), .A1(n1942), .B0(n1941), .Y(n8618) );
OAI2BB1X4TS U3744 ( .A0N(n860), .A1N(n2256), .B0(n859), .Y(n2539) );
NAND2BX4TS U3745 ( .AN(n861), .B(n2257), .Y(n859) );
OR2X4TS U3746 ( .A(n863), .B(n2257), .Y(n860) );
XOR2X2TS U3747 ( .A(n2256), .B(n862), .Y(n2314) );
XNOR2X4TS U3748 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n964) );
NAND2X8TS U3749 ( .A(n5269), .B(n5270), .Y(n8138) );
XNOR2X4TS U3750 ( .A(Op_MX[26]), .B(Op_MX[25]), .Y(n2984) );
XNOR2X4TS U3751 ( .A(n6108), .B(Op_MX[26]), .Y(n874) );
XNOR2X1TS U3752 ( .A(n705), .B(n4671), .Y(n3224) );
NAND2X2TS U3753 ( .A(n7734), .B(n7450), .Y(n7783) );
XNOR2X2TS U3754 ( .A(n701), .B(n6337), .Y(n6226) );
OAI22X2TS U3755 ( .A0(n6772), .A1(n3970), .B0(n6021), .B1(n4083), .Y(n3990)
);
NOR2X4TS U3756 ( .A(n7196), .B(n7195), .Y(n7556) );
INVX8TS U3757 ( .A(n6830), .Y(n6672) );
OAI22X1TS U3758 ( .A0(n6948), .A1(n7027), .B0(n7051), .B1(n7184), .Y(n7138)
);
ADDFHX2TS U3759 ( .A(n5911), .B(n5910), .CI(n5909), .CO(n5946), .S(n5913) );
ADDFHX2TS U3760 ( .A(n4991), .B(n4990), .CI(n4989), .CO(n5016), .S(n5009) );
OAI22X1TS U3761 ( .A0(n815), .A1(n3208), .B0(n735), .B1(n3591), .Y(n3617) );
OAI22X2TS U3762 ( .A0(n5664), .A1(n5532), .B0(n6332), .B1(n5590), .Y(n5561)
);
OAI22X1TS U3763 ( .A0(n4581), .A1(n2242), .B0(n744), .B1(n2459), .Y(n2491)
);
NOR2X1TS U3764 ( .A(n7632), .B(n7630), .Y(n7634) );
OAI22X1TS U3765 ( .A0(n6202), .A1(n1488), .B0(n4116), .B1(n1313), .Y(n1521)
);
ADDFX2TS U3766 ( .A(n2994), .B(n2993), .CI(n2992), .CO(n3474), .S(n3023) );
INVX8TS U3767 ( .A(n6105), .Y(n5413) );
XNOR2X2TS U3768 ( .A(n3895), .B(n4905), .Y(n4003) );
NOR2X6TS U3769 ( .A(n7289), .B(n7288), .Y(n7632) );
ADDFHX2TS U3770 ( .A(n1565), .B(n1564), .CI(n1563), .CO(n1485), .S(n1613) );
INVX8TS U3771 ( .A(n6793), .Y(n6647) );
XNOR2X2TS U3772 ( .A(n6329), .B(n8212), .Y(n3931) );
ADDFHX2TS U3773 ( .A(n3859), .B(n3858), .CI(n3857), .CO(n3965), .S(n3869) );
AOI21X2TS U3774 ( .A0(n7740), .A1(n7739), .B0(n7738), .Y(n7741) );
INVX6TS U3775 ( .A(n1180), .Y(n5679) );
OAI22X2TS U3776 ( .A0(n714), .A1(n3880), .B0(n6073), .B1(n3998), .Y(n3977)
);
XNOR2X2TS U3777 ( .A(n6660), .B(n6887), .Y(n6155) );
ADDFHX2TS U3778 ( .A(n3123), .B(n3122), .CI(n3121), .CO(n3188), .S(n3328) );
ADDFHX2TS U3779 ( .A(n5346), .B(n5345), .CI(n5344), .CO(n5437), .S(n5352) );
OAI22X1TS U3780 ( .A0(n4371), .A1(n3682), .B0(n4370), .B1(n3839), .Y(n3779)
);
ADDFHX2TS U3781 ( .A(n4292), .B(n4291), .CI(n4290), .CO(n4626), .S(n4286) );
OAI22X2TS U3782 ( .A0(n4443), .A1(n2244), .B0(n3175), .B1(n2264), .Y(n2257)
);
ADDFHX2TS U3783 ( .A(n1960), .B(n1959), .CI(n1958), .CO(n1996), .S(n1976) );
XNOR2X2TS U3784 ( .A(n5132), .B(n2247), .Y(n2260) );
OAI22X2TS U3785 ( .A0(n2281), .A1(n2280), .B0(n2868), .B1(n2279), .Y(n2300)
);
INVX8TS U3786 ( .A(n7139), .Y(n7009) );
XNOR2X2TS U3787 ( .A(n6064), .B(n6054), .Y(n5989) );
NAND2X8TS U3788 ( .A(n972), .B(n4030), .Y(n2884) );
INVX8TS U3789 ( .A(n7165), .Y(n7054) );
ADDFHX4TS U3790 ( .A(n4863), .B(n4862), .CI(n4861), .CO(n5059), .S(n5058) );
ADDFHX2TS U3791 ( .A(n5232), .B(n5231), .CI(n5230), .CO(n5309), .S(n5236) );
ADDFHX2TS U3792 ( .A(n5399), .B(n5398), .CI(n5397), .CO(n5463), .S(n5369) );
INVX8TS U3793 ( .A(n6841), .Y(n6742) );
ADDFHX4TS U3794 ( .A(n3739), .B(n3738), .CI(n3737), .CO(n5027), .S(n5026) );
OAI22X2TS U3795 ( .A0(n5535), .A1(n3896), .B0(n4002), .B1(n4003), .Y(n3980)
);
ADDFHX4TS U3796 ( .A(n6080), .B(n6079), .CI(n6078), .CO(n7289), .S(n7284) );
ADDFHX4TS U3797 ( .A(n5547), .B(n5546), .CI(n5545), .CO(n6079), .S(n5539) );
ADDFHX4TS U3798 ( .A(n5024), .B(n5023), .CI(n5022), .CO(n5053), .S(n5052) );
ADDFHX2TS U3799 ( .A(n3206), .B(n3205), .CI(n3204), .CO(n3544), .S(n3109) );
ADDFHX2TS U3800 ( .A(n1279), .B(n1278), .CI(n1277), .CO(n1285), .S(n1570) );
ADDFHX2TS U3801 ( .A(n4636), .B(n4635), .CI(n4634), .CO(n4644), .S(n4625) );
ADDFHX2TS U3802 ( .A(n3172), .B(n3171), .CI(n3170), .CO(n3237), .S(n3398) );
ADDFHX2TS U3803 ( .A(n1667), .B(n1666), .CI(n1665), .CO(n1672), .S(n2402) );
ADDFHX2TS U3804 ( .A(n1023), .B(n1022), .CI(n1021), .CO(n1034), .S(n1224) );
ADDFHX2TS U3805 ( .A(n1014), .B(n1013), .CI(n1012), .CO(n1133), .S(n1066) );
ADDFHX4TS U3806 ( .A(n5021), .B(n5020), .CI(n5019), .CO(n5057), .S(n5054) );
ADDFHX4TS U3807 ( .A(n4821), .B(n4820), .CI(n4819), .CO(n4862), .S(n5020) );
OAI22X2TS U3808 ( .A0(n3114), .A1(n2672), .B0(n3866), .B1(n2889), .Y(n2856)
);
ADDFHX2TS U3809 ( .A(n2555), .B(n2554), .CI(n2553), .CO(n2572), .S(n2574) );
XNOR2X2TS U3810 ( .A(n766), .B(n5707), .Y(n3115) );
ADDFHX4TS U3811 ( .A(n2815), .B(n2814), .CI(n2813), .CO(n3502), .S(n3501) );
ADDFHX4TS U3812 ( .A(n2806), .B(n2805), .CI(n2804), .CO(n2904), .S(n2814) );
ADDFHX4TS U3813 ( .A(n5009), .B(n5008), .CI(n5007), .CO(n5051), .S(n5050) );
ADDFHX2TS U3814 ( .A(n3354), .B(n3353), .CI(n3352), .CO(n3185), .S(n3389) );
INVX8TS U3815 ( .A(n4426), .Y(n2241) );
ADDFHX4TS U3816 ( .A(n5455), .B(n5454), .CI(n5453), .CO(n7283), .S(n7279) );
ADDFHX4TS U3817 ( .A(n5368), .B(n5367), .CI(n5366), .CO(n5454), .S(n5450) );
ADDFHX2TS U3818 ( .A(n2727), .B(n2726), .CI(n2725), .CO(n2738), .S(n2741) );
ADDFHX4TS U3819 ( .A(n5541), .B(n5540), .CI(n5539), .CO(n7285), .S(n7282) );
ADDFHX4TS U3820 ( .A(n5461), .B(n5460), .CI(n5459), .CO(n5540), .S(n5453) );
OAI22X2TS U3821 ( .A0(n5350), .A1(n4437), .B0(n5720), .B1(n4505), .Y(n4423)
);
XNOR2X2TS U3822 ( .A(n749), .B(n696), .Y(n2683) );
OAI21X1TS U3823 ( .A0(n7632), .A1(n7443), .B0(n7631), .Y(n7633) );
ADDFHX2TS U3824 ( .A(n3192), .B(n3191), .CI(n3190), .CO(n3282), .S(n3186) );
ADDFHX2TS U3825 ( .A(n5196), .B(n5195), .CI(n5194), .CO(n5351), .S(n5237) );
ADDFHX2TS U3826 ( .A(n4543), .B(n4542), .CI(n4541), .CO(n4641), .S(n4726) );
INVX8TS U3827 ( .A(n5347), .Y(n1624) );
ADDFHX4TS U3828 ( .A(n4400), .B(n4399), .CI(n4398), .CO(n5039), .S(n5038) );
ADDFHX2TS U3829 ( .A(n3324), .B(n3323), .CI(n3322), .CO(n3329), .S(n3374) );
OA21X4TS U3830 ( .A0(n7809), .A1(n7808), .B0(n7807), .Y(n881) );
AND2X2TS U3831 ( .A(n8077), .B(n8075), .Y(n883) );
NAND2X1TS U3832 ( .A(n7812), .B(n7811), .Y(n886) );
OR2X8TS U3833 ( .A(n7198), .B(n7197), .Y(n891) );
OR2X2TS U3834 ( .A(n1939), .B(n1938), .Y(n909) );
OR2X8TS U3835 ( .A(n7630), .B(n7309), .Y(n915) );
OR2X8TS U3836 ( .A(n3503), .B(n3502), .Y(n917) );
INVX2TS U3837 ( .A(n5911), .Y(n5693) );
NOR2XLTS U3838 ( .A(n4071), .B(n2159), .Y(n4051) );
OAI22X1TS U3839 ( .A0(n4055), .A1(n4104), .B0(n5887), .B1(n4230), .Y(n4211)
);
OAI22X1TS U3840 ( .A0(n699), .A1(n4114), .B0(n6073), .B1(n4232), .Y(n4251)
);
OAI22X1TS U3841 ( .A0(n688), .A1(n4318), .B0(n6437), .B1(n4471), .Y(n4458)
);
OAI22X1TS U3842 ( .A0(n6156), .A1(n4459), .B0(n787), .B1(n4496), .Y(n4543)
);
OAI22X2TS U3843 ( .A0(n6127), .A1(n4513), .B0(n4776), .B1(n680), .Y(n4936)
);
BUFX4TS U3844 ( .A(n6651), .Y(n4907) );
OAI22X1TS U3845 ( .A0(n6419), .A1(n6031), .B0(n734), .B1(n6418), .Y(n6498)
);
BUFX8TS U3846 ( .A(n4680), .Y(n3685) );
OAI22X1TS U3847 ( .A0(n4260), .A1(n1500), .B0(n2799), .B1(n1264), .Y(n1529)
);
OAI22X1TS U3848 ( .A0(n5302), .A1(n3292), .B0(n3291), .B1(n6019), .Y(n3308)
);
ADDFHX2TS U3849 ( .A(n6314), .B(n6313), .CI(n6312), .CO(n7079), .S(n6316) );
OAI22X1TS U3850 ( .A0(n1710), .A1(n1690), .B0(n1702), .B1(n5666), .Y(n1755)
);
ADDHX1TS U3851 ( .A(n2395), .B(n2394), .CO(n2403), .S(n2467) );
ADDFHX2TS U3852 ( .A(n5920), .B(n5919), .CI(n5918), .CO(n5963), .S(n5922) );
ADDFHX2TS U3853 ( .A(n6493), .B(n6492), .CI(n6491), .CO(n6520), .S(n6551) );
ADDFHX2TS U3854 ( .A(n1258), .B(n1257), .CI(n1256), .CO(n1273), .S(n1545) );
NOR2X2TS U3855 ( .A(n7425), .B(n7430), .Y(n7433) );
ADDFHX2TS U3856 ( .A(n2328), .B(n2327), .CI(n2326), .CO(n2333), .S(n2335) );
INVX2TS U3857 ( .A(n7866), .Y(n8015) );
INVX2TS U3858 ( .A(n7603), .Y(n7606) );
INVX2TS U3859 ( .A(n7630), .Y(n7578) );
NAND2X1TS U3860 ( .A(n7924), .B(n7926), .Y(n7929) );
INVX2TS U3861 ( .A(n8575), .Y(n8577) );
OAI21X1TS U3862 ( .A0(FSM_selector_B[0]), .A1(n7441), .B0(n661), .Y(n7442)
);
OAI21X2TS U3863 ( .A0(n8061), .A1(n7907), .B0(n7906), .Y(n7912) );
XOR2X4TS U3867 ( .A(Op_MX[30]), .B(n8223), .Y(n918) );
XNOR2X4TS U3868 ( .A(Op_MX[29]), .B(Op_MX[30]), .Y(n919) );
INVX8TS U3869 ( .A(Op_MY[4]), .Y(n4294) );
XNOR2X1TS U3870 ( .A(n8223), .B(n1947), .Y(n948) );
OAI22X1TS U3871 ( .A0(n2720), .A1(n948), .B0(n4685), .B1(n944), .Y(n1011) );
XNOR2X4TS U3872 ( .A(Op_MX[34]), .B(Op_MX[33]), .Y(n921) );
INVX8TS U3873 ( .A(n6744), .Y(n6222) );
XOR2X4TS U3874 ( .A(n6222), .B(Op_MX[34]), .Y(n920) );
INVX4TS U3875 ( .A(n1201), .Y(n3723) );
INVX4TS U3876 ( .A(n6744), .Y(n6662) );
XNOR2X1TS U3877 ( .A(n3723), .B(n6222), .Y(n922) );
XNOR2X1TS U3878 ( .A(n3724), .B(n5787), .Y(n1017) );
OAI22X1TS U3879 ( .A0(n781), .A1(n922), .B0(n1017), .B1(n6745), .Y(n1010) );
INVX16TS U3880 ( .A(Op_MX[33]), .Y(n6714) );
INVX16TS U3881 ( .A(n6714), .Y(n8209) );
XOR2X4TS U3882 ( .A(Op_MX[32]), .B(n8209), .Y(n923) );
XNOR2X4TS U3883 ( .A(Op_MX[32]), .B(Op_MX[31]), .Y(n924) );
NAND2X8TS U3884 ( .A(n923), .B(n6715), .Y(n3879) );
XNOR2X1TS U3885 ( .A(n779), .B(n3833), .Y(n999) );
XNOR2X1TS U3886 ( .A(n8805), .B(n8236), .Y(n940) );
OAI22X1TS U3887 ( .A0(n4115), .A1(n999), .B0(n4499), .B1(n940), .Y(n1009) );
XOR2X4TS U3888 ( .A(Op_MX[12]), .B(n3108), .Y(n925) );
XNOR2X4TS U3889 ( .A(Op_MX[11]), .B(Op_MX[12]), .Y(n926) );
XNOR2X1TS U3890 ( .A(n2258), .B(n3877), .Y(n1015) );
OAI22X1TS U3891 ( .A0(n4204), .A1(n956), .B0(n2414), .B1(n1015), .Y(n937) );
INVX16TS U3892 ( .A(Op_MX[29]), .Y(n6201) );
INVX12TS U3893 ( .A(n6201), .Y(n6379) );
XOR2X4TS U3894 ( .A(n6379), .B(Op_MX[28]), .Y(n927) );
NAND2X8TS U3895 ( .A(n927), .B(n928), .Y(n5944) );
BUFX4TS U3896 ( .A(n928), .Y(n4487) );
INVX8TS U3897 ( .A(Op_MY[7]), .Y(n4416) );
XNOR2X1TS U3898 ( .A(n748), .B(n1943), .Y(n1049) );
OAI22X1TS U3899 ( .A0(n702), .A1(n1000), .B0(n4487), .B1(n1049), .Y(n936) );
XNOR2X1TS U3900 ( .A(n819), .B(n736), .Y(n1008) );
XNOR2X1TS U3901 ( .A(n5489), .B(n2132), .Y(n1050) );
OAI22X1TS U3902 ( .A0(n1518), .A1(n1008), .B0(n4322), .B1(n1050), .Y(n935)
);
XOR2X4TS U3903 ( .A(Op_MX[14]), .B(n8811), .Y(n929) );
XNOR2X4TS U3904 ( .A(Op_MX[14]), .B(Op_MX[13]), .Y(n1082) );
NAND2X8TS U3905 ( .A(n929), .B(n930), .Y(n5206) );
INVX8TS U3906 ( .A(Op_MY[20]), .Y(n5861) );
INVX4TS U3907 ( .A(n5861), .Y(n2912) );
XNOR2X1TS U3908 ( .A(n3895), .B(n2912), .Y(n960) );
INVX8TS U3909 ( .A(Op_MY[21]), .Y(n5972) );
OAI22X1TS U3910 ( .A0(n718), .A1(n960), .B0(n786), .B1(n1054), .Y(n1061) );
INVX8TS U3911 ( .A(n5665), .Y(n1349) );
XOR2X4TS U3912 ( .A(n1349), .B(Op_MX[16]), .Y(n931) );
XNOR2X4TS U3913 ( .A(Op_MX[16]), .B(n644), .Y(n997) );
NAND2X8TS U3914 ( .A(n931), .B(n932), .Y(n4337) );
XNOR2X1TS U3915 ( .A(n1349), .B(Op_MY[18]), .Y(n998) );
XNOR2X1TS U3916 ( .A(n1349), .B(n2887), .Y(n943) );
OAI22X1TS U3917 ( .A0(n3793), .A1(n998), .B0(n4434), .B1(n943), .Y(n1060) );
XOR2X4TS U3918 ( .A(Op_MX[18]), .B(n8812), .Y(n933) );
XNOR2X4TS U3919 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n934) );
NAND2X8TS U3920 ( .A(n933), .B(n5675), .Y(n4407) );
INVX4TS U3921 ( .A(n5601), .Y(n1453) );
XNOR2X1TS U3922 ( .A(n636), .B(n1453), .Y(n1004) );
BUFX6TS U3923 ( .A(n934), .Y(n3165) );
XNOR2X1TS U3924 ( .A(n768), .B(n2702), .Y(n990) );
OAI22X1TS U3925 ( .A0(n1727), .A1(n1004), .B0(n3071), .B1(n990), .Y(n947) );
XNOR2X1TS U3926 ( .A(n1948), .B(n5203), .Y(n992) );
BUFX3TS U3927 ( .A(n2159), .Y(n1822) );
OAI22X1TS U3928 ( .A0(n2663), .A1(n1002), .B0(n992), .B1(n1822), .Y(n946) );
CMPR32X2TS U3929 ( .A(n937), .B(n936), .C(n935), .CO(n980), .S(n1036) );
XOR2X4TS U3930 ( .A(Op_MX[24]), .B(n5880), .Y(n938) );
XNOR2X4TS U3931 ( .A(Op_MX[23]), .B(Op_MX[24]), .Y(n939) );
INVX6TS U3932 ( .A(n6370), .Y(n3594) );
XNOR2X1TS U3933 ( .A(n3594), .B(n746), .Y(n969) );
INVX4TS U3934 ( .A(n5192), .Y(n2385) );
XNOR2X1TS U3935 ( .A(n3594), .B(n2385), .Y(n1084) );
OAI22X1TS U3936 ( .A0(n817), .A1(n969), .B0(n3987), .B1(n1084), .Y(n1070) );
XNOR2X1TS U3937 ( .A(n779), .B(n3971), .Y(n1106) );
OAI22X1TS U3938 ( .A0(n4115), .A1(n940), .B0(n4499), .B1(n1106), .Y(n1069)
);
XNOR2X4TS U3939 ( .A(Op_MX[8]), .B(n8807), .Y(n942) );
NAND2X8TS U3940 ( .A(n941), .B(n951), .Y(n4099) );
XNOR2X1TS U3941 ( .A(n8819), .B(n6133), .Y(n976) );
XNOR2X1TS U3942 ( .A(n4404), .B(n4418), .Y(n1080) );
OAI22X1TS U3943 ( .A0(n4682), .A1(n976), .B0(n808), .B1(n1080), .Y(n1068) );
XNOR2X1TS U3944 ( .A(n1349), .B(n2912), .Y(n1107) );
OAI22X1TS U3945 ( .A0(n3793), .A1(n943), .B0(n4434), .B1(n1107), .Y(n984) );
XNOR2X4TS U3946 ( .A(Op_MX[35]), .B(Op_MX[36]), .Y(n5789) );
BUFX6TS U3947 ( .A(n6033), .Y(n6826) );
NOR2BX1TS U3948 ( .AN(n1988), .B(n6826), .Y(n989) );
OAI22X2TS U3949 ( .A0(n2720), .A1(n944), .B0(n4295), .B1(n981), .Y(n988) );
XOR2X4TS U3950 ( .A(Op_MX[6]), .B(n8807), .Y(n945) );
XNOR2X4TS U3951 ( .A(Op_MX[5]), .B(Op_MX[6]), .Y(n950) );
XNOR2X1TS U3952 ( .A(n8208), .B(n4420), .Y(n973) );
BUFX4TS U3953 ( .A(n641), .Y(n3116) );
OAI22X1TS U3954 ( .A0(n2783), .A1(n973), .B0(n3116), .B1(n1081), .Y(n987) );
XNOR2X1TS U3955 ( .A(n8813), .B(n1984), .Y(n1240) );
INVX6TS U3956 ( .A(n4175), .Y(n1965) );
XNOR2X1TS U3957 ( .A(n708), .B(n1965), .Y(n949) );
OAI22X1TS U3958 ( .A0(n2720), .A1(n1240), .B0(n4295), .B1(n949), .Y(n1190)
);
XNOR2X1TS U3959 ( .A(n3203), .B(n4841), .Y(n1213) );
XNOR2X1TS U3960 ( .A(n784), .B(n4888), .Y(n1003) );
OAI22X1TS U3961 ( .A0(n1838), .A1(n1213), .B0(n1003), .B1(n1822), .Y(n1189)
);
NOR2BX1TS U3962 ( .AN(n1988), .B(n6745), .Y(n954) );
XNOR2X1TS U3963 ( .A(n8208), .B(n5413), .Y(n1169) );
BUFX4TS U3964 ( .A(n641), .Y(n2031) );
OAI22X1TS U3965 ( .A0(n2783), .A1(n1169), .B0(n2031), .B1(n974), .Y(n952) );
INVX4TS U3966 ( .A(n4513), .Y(n2675) );
XNOR2X1TS U3967 ( .A(n694), .B(n2262), .Y(n965) );
OAI22X1TS U3968 ( .A0(n687), .A1(n1191), .B0(n3987), .B1(n965), .Y(n1246) );
XNOR2X1TS U3969 ( .A(n748), .B(n1947), .Y(n1243) );
XNOR2X1TS U3970 ( .A(n748), .B(n3992), .Y(n1001) );
OAI22X1TS U3971 ( .A0(n6463), .A1(n1243), .B0(n4487), .B1(n1001), .Y(n1245)
);
XNOR2X1TS U3972 ( .A(n4218), .B(n8233), .Y(n1219) );
XNOR2X1TS U3973 ( .A(n2383), .B(n4090), .Y(n968) );
OAI22X1TS U3974 ( .A0(n3782), .A1(n1219), .B0(n3685), .B1(n968), .Y(n1244)
);
XNOR2X1TS U3975 ( .A(n4570), .B(n5745), .Y(n1178) );
OAI22X1TS U3976 ( .A0(n4204), .A1(n1178), .B0(n4408), .B1(n956), .Y(n1184)
);
XOR2X4TS U3977 ( .A(n4879), .B(Op_MX[10]), .Y(n958) );
XNOR2X1TS U3978 ( .A(n4879), .B(n3877), .Y(n1175) );
XNOR2X1TS U3979 ( .A(n4412), .B(n8233), .Y(n961) );
OAI22X1TS U3980 ( .A0(n1791), .A1(n1176), .B0(n5390), .B1(n960), .Y(n1182)
);
XNOR2X1TS U3981 ( .A(n798), .B(n4090), .Y(n1047) );
OAI22X1TS U3982 ( .A0(n4057), .A1(n961), .B0(n3899), .B1(n1047), .Y(n1046)
);
XOR2X4TS U3983 ( .A(n5679), .B(Op_MX[22]), .Y(n962) );
XOR2X4TS U3984 ( .A(n5890), .B(n670), .Y(n1055) );
XNOR2X1TS U3985 ( .A(n8210), .B(n2385), .Y(n1007) );
XNOR2X1TS U3986 ( .A(n8210), .B(n2878), .Y(n1056) );
OAI22X1TS U3987 ( .A0(n6055), .A1(n1007), .B0(n3863), .B1(n1056), .Y(n1045)
);
XOR2X4TS U3988 ( .A(n5890), .B(Op_MX[20]), .Y(n963) );
XNOR2X1TS U3989 ( .A(n3138), .B(n713), .Y(n1006) );
INVX12TS U3990 ( .A(Op_MY[15]), .Y(n5525) );
XNOR2X1TS U3991 ( .A(n3138), .B(n1491), .Y(n1058) );
OAI22X1TS U3992 ( .A0(n2149), .A1(n1006), .B0(n745), .B1(n1058), .Y(n1044)
);
XNOR2X1TS U3993 ( .A(n694), .B(n2388), .Y(n970) );
OAI22X1TS U3994 ( .A0(n687), .A1(n965), .B0(n3987), .B1(n970), .Y(n1187) );
XOR2X4TS U3995 ( .A(n3838), .B(Op_MX[4]), .Y(n966) );
XNOR2X4TS U3996 ( .A(Op_MX[4]), .B(Op_MX[3]), .Y(n967) );
NAND2X8TS U3997 ( .A(n966), .B(n640), .Y(n3069) );
XNOR2X1TS U3998 ( .A(n1944), .B(n4420), .Y(n1171) );
XNOR2X1TS U3999 ( .A(n3149), .B(n4504), .Y(n975) );
OAI22X1TS U4000 ( .A0(n1708), .A1(n1171), .B0(n2921), .B1(n975), .Y(n1186)
);
XNOR2X1TS U4001 ( .A(n752), .B(n3611), .Y(n977) );
OAI22X1TS U4002 ( .A0(n3782), .A1(n968), .B0(n3685), .B1(n977), .Y(n1185) );
OAI22X1TS U4003 ( .A0(n704), .A1(n970), .B0(n3987), .B1(n969), .Y(n1053) );
INVX4TS U4004 ( .A(n1201), .Y(n3642) );
OAI22X1TS U4005 ( .A0(n6487), .A1(n6744), .B0(n971), .B1(n6745), .Y(n1052)
);
XNOR2X4TS U4006 ( .A(Op_MX[2]), .B(Op_MX[1]), .Y(n1027) );
XNOR2X1TS U4007 ( .A(n3726), .B(n4841), .Y(n1005) );
BUFX3TS U4008 ( .A(n1027), .Y(n2799) );
XNOR2X1TS U4009 ( .A(n3726), .B(n4888), .Y(n993) );
OAI22X1TS U4010 ( .A0(n4032), .A1(n1005), .B0(n2799), .B1(n993), .Y(n1051)
);
OAI22X1TS U4011 ( .A0(n2783), .A1(n974), .B0(n3116), .B1(n973), .Y(n1043) );
INVX8TS U4012 ( .A(Op_MY[31]), .Y(n6311) );
XNOR2X1TS U4013 ( .A(n3149), .B(n6335), .Y(n1016) );
OAI22X1TS U4014 ( .A0(n1708), .A1(n975), .B0(n1991), .B1(n1016), .Y(n1042)
);
OAI22X1TS U4015 ( .A0(n3782), .A1(n977), .B0(n2448), .B1(n976), .Y(n1041) );
XNOR2X1TS U4016 ( .A(n748), .B(n4405), .Y(n1048) );
OAI22X1TS U4017 ( .A0(n5625), .A1(n1048), .B0(n4487), .B1(n1124), .Y(n1140)
);
XNOR2X1TS U4018 ( .A(n5784), .B(n1943), .Y(n1123) );
OAI22X1TS U4019 ( .A0(n2720), .A1(n981), .B0(n4685), .B1(n1123), .Y(n1139)
);
XNOR2X1TS U4020 ( .A(n3138), .B(n1453), .Y(n1057) );
XNOR2X1TS U4021 ( .A(n3138), .B(n2702), .Y(n1122) );
OAI22X1TS U4022 ( .A0(n2149), .A1(n1057), .B0(n744), .B1(n1122), .Y(n1138)
);
CMPR32X2TS U4023 ( .A(n984), .B(n983), .C(n982), .CO(n1145), .S(n978) );
XOR2X4TS U4024 ( .A(n6248), .B(Op_MX[36]), .Y(n985) );
NAND2X8TS U4025 ( .A(n985), .B(n4112), .Y(n6177) );
INVX4TS U4026 ( .A(n1201), .Y(n3254) );
OAI22X1TS U4027 ( .A0(n4243), .A1(n6825), .B0(n986), .B1(n6826), .Y(n1132)
);
INVX8TS U4028 ( .A(n6793), .Y(n5348) );
BUFX3TS U4029 ( .A(n2159), .Y(n2961) );
ADDFHX2TS U4030 ( .A(n989), .B(n988), .CI(n987), .CO(n1134), .S(n983) );
XNOR2X1TS U4031 ( .A(n636), .B(Op_MY[18]), .Y(n1091) );
OAI22X1TS U4032 ( .A0(n2663), .A1(n992), .B0(n991), .B1(n2961), .Y(n1013) );
XNOR2X1TS U4033 ( .A(n3726), .B(Op_MY[34]), .Y(n1092) );
OAI22X1TS U4034 ( .A0(n2039), .A1(n993), .B0(n2799), .B1(n1092), .Y(n1012)
);
XNOR2X1TS U4035 ( .A(n755), .B(n2702), .Y(n1177) );
OAI22X1TS U4036 ( .A0(n5667), .A1(n1177), .B0(n758), .B1(n998), .Y(n1023) );
XNOR2X1TS U4037 ( .A(n3724), .B(n6168), .Y(n1025) );
OAI22X1TS U4038 ( .A0(n3879), .A1(n1025), .B0(n4499), .B1(n999), .Y(n1022)
);
OAI22X1TS U4039 ( .A0(n633), .A1(n1001), .B0(n4116), .B1(n1000), .Y(n1021)
);
XNOR2X1TS U4040 ( .A(n636), .B(n1491), .Y(n1024) );
OAI22X1TS U4041 ( .A0(n1727), .A1(n1024), .B0(n3071), .B1(n1004), .Y(n1173)
);
XNOR2X1TS U4042 ( .A(n3726), .B(n820), .Y(n1028) );
OAI22X1TS U4043 ( .A0(n2039), .A1(n1028), .B0(n2799), .B1(n1005), .Y(n1172)
);
XNOR2X1TS U4044 ( .A(n3138), .B(n4882), .Y(n1188) );
OAI22X1TS U4045 ( .A0(n2149), .A1(n1188), .B0(n745), .B1(n1006), .Y(n1031)
);
XNOR2X1TS U4046 ( .A(n8210), .B(n747), .Y(n1181) );
OAI22X1TS U4047 ( .A0(n4606), .A1(n1181), .B0(n3863), .B1(n1007), .Y(n1030)
);
XNOR2X1TS U4048 ( .A(n5489), .B(n1943), .Y(n1179) );
OAI22X1TS U4049 ( .A0(n1518), .A1(n1179), .B0(n4322), .B1(n1008), .Y(n1029)
);
CMPR32X2TS U4050 ( .A(n1011), .B(n1010), .C(n1009), .CO(n1067), .S(n1037) );
XNOR2X1TS U4051 ( .A(n8216), .B(n8233), .Y(n1104) );
OAI22X1TS U4052 ( .A0(n4204), .A1(n1015), .B0(n4408), .B1(n1104), .Y(n1100)
);
XNOR2X1TS U4053 ( .A(n3149), .B(n4841), .Y(n1078) );
OAI22X1TS U4054 ( .A0(n1708), .A1(n1016), .B0(n2921), .B1(n1078), .Y(n1099)
);
XNOR2X1TS U4055 ( .A(n4813), .B(n3833), .Y(n1090) );
OAI22X1TS U4056 ( .A0(n781), .A1(n1017), .B0(n4687), .B1(n1090), .Y(n1098)
);
XNOR2X1TS U4057 ( .A(n636), .B(n5090), .Y(n1194) );
OAI22X1TS U4058 ( .A0(n1727), .A1(n1194), .B0(n3071), .B1(n1024), .Y(n1249)
);
XNOR2X1TS U4059 ( .A(n3723), .B(n6168), .Y(n1026) );
OAI22X1TS U4060 ( .A0(n3879), .A1(n1026), .B0(n1025), .B1(n6651), .Y(n1248)
);
XNOR2X1TS U4061 ( .A(n3726), .B(n4504), .Y(n1215) );
BUFX3TS U4062 ( .A(n1027), .Y(n2037) );
OAI22X1TS U4063 ( .A0(n810), .A1(n1215), .B0(n2037), .B1(n1028), .Y(n1247)
);
CMPR32X2TS U4064 ( .A(n1031), .B(n1030), .C(n1029), .CO(n1032), .S(n1222) );
CMPR32X2TS U4065 ( .A(n1043), .B(n1042), .C(n1041), .CO(n1064), .S(n1038) );
XNOR2X1TS U4066 ( .A(n798), .B(n753), .Y(n1079) );
OAI22X1TS U4067 ( .A0(n4057), .A1(n1047), .B0(n3899), .B1(n1079), .Y(n1076)
);
OAI22X1TS U4068 ( .A0(n702), .A1(n1049), .B0(n4487), .B1(n1048), .Y(n1075)
);
XNOR2X1TS U4069 ( .A(n8808), .B(n2137), .Y(n1085) );
OAI22X1TS U4070 ( .A0(n1518), .A1(n1050), .B0(n4322), .B1(n1085), .Y(n1074)
);
XNOR2X1TS U4071 ( .A(n8210), .B(n5090), .Y(n1086) );
OAI22X1TS U4072 ( .A0(n6055), .A1(n1056), .B0(n826), .B1(n1086), .Y(n1072)
);
OAI22X1TS U4073 ( .A0(n2149), .A1(n1058), .B0(n745), .B1(n1057), .Y(n1071)
);
ADDFX2TS U4074 ( .A(n1073), .B(n1072), .CI(n1071), .CO(n1088), .S(n1151) );
XNOR2X1TS U4075 ( .A(n3723), .B(n8809), .Y(n1077) );
XNOR2X1TS U4076 ( .A(n3724), .B(n638), .Y(n1136) );
OAI22X1TS U4077 ( .A0(n4243), .A1(n1077), .B0(n1136), .B1(n6826), .Y(n1116)
);
XNOR2X1TS U4078 ( .A(n3149), .B(n4888), .Y(n1141) );
OAI22X1TS U4079 ( .A0(n1708), .A1(n1078), .B0(n2921), .B1(n1141), .Y(n1115)
);
XNOR2X1TS U4080 ( .A(n3786), .B(n790), .Y(n1130) );
OAI22X1TS U4081 ( .A0(n4057), .A1(n1079), .B0(n2452), .B1(n1130), .Y(n1114)
);
XNOR2X1TS U4082 ( .A(n4404), .B(n4420), .Y(n1129) );
OAI22X1TS U4083 ( .A0(n4682), .A1(n1080), .B0(n806), .B1(n1129), .Y(n1110)
);
XNOR2X1TS U4084 ( .A(n8208), .B(n6335), .Y(n1137) );
XNOR2X1TS U4085 ( .A(n2386), .B(n4671), .Y(n1143) );
OAI22X1TS U4086 ( .A0(n717), .A1(n1083), .B0(n2668), .B1(n1143), .Y(n1108)
);
XNOR2X1TS U4087 ( .A(n3594), .B(n4882), .Y(n1097) );
OAI22X1TS U4088 ( .A0(n6455), .A1(n1084), .B0(n3987), .B1(n1097), .Y(n1113)
);
XNOR2X1TS U4089 ( .A(n8808), .B(n627), .Y(n1125) );
OAI22X1TS U4090 ( .A0(n1518), .A1(n1085), .B0(n4322), .B1(n1125), .Y(n1112)
);
OAI22X1TS U4091 ( .A0(n2457), .A1(n1086), .B0(n828), .B1(n1121), .Y(n1111)
);
XNOR2X1TS U4092 ( .A(n4813), .B(n8236), .Y(n1096) );
OAI22X1TS U4093 ( .A0(n6731), .A1(n1090), .B0(n4687), .B1(n1096), .Y(n1103)
);
OAI22X1TS U4094 ( .A0(n1727), .A1(n1091), .B0(n4661), .B1(n1093), .Y(n1102)
);
XNOR2X1TS U4095 ( .A(n8212), .B(n5203), .Y(n1095) );
OAI22X1TS U4096 ( .A0(n4032), .A1(n1092), .B0(n2799), .B1(n1095), .Y(n1101)
);
XNOR2X1TS U4097 ( .A(n825), .B(n2912), .Y(n1361) );
OAI22X1TS U4098 ( .A0(n1727), .A1(n1093), .B0(n4661), .B1(n1361), .Y(n1383)
);
XNOR2X1TS U4099 ( .A(n3203), .B(n5526), .Y(n1323) );
OAI22X1TS U4100 ( .A0(n2663), .A1(n1094), .B0(n1323), .B1(n2961), .Y(n1382)
);
XNOR2X1TS U4101 ( .A(n3726), .B(n5348), .Y(n1365) );
OAI22X1TS U4102 ( .A0(n3164), .A1(n1095), .B0(n2799), .B1(n1365), .Y(n1381)
);
XNOR2X1TS U4103 ( .A(n4497), .B(n2866), .Y(n1105) );
XNOR2X1TS U4104 ( .A(n778), .B(n4208), .Y(n1385) );
OAI22X1TS U4105 ( .A0(n699), .A1(n1105), .B0(n4499), .B1(n1385), .Y(n1374)
);
XNOR2X1TS U4106 ( .A(n6662), .B(n3971), .Y(n1386) );
OAI22X1TS U4107 ( .A0(n5724), .A1(n1096), .B0(n4687), .B1(n1386), .Y(n1373)
);
XNOR2X1TS U4108 ( .A(n3594), .B(n2926), .Y(n1389) );
OAI22X1TS U4109 ( .A0(n704), .A1(n1097), .B0(n3680), .B1(n1389), .Y(n1372)
);
XNOR2X1TS U4110 ( .A(n3102), .B(n4090), .Y(n1120) );
OAI22X1TS U4111 ( .A0(n4204), .A1(n1104), .B0(n4408), .B1(n1120), .Y(n1119)
);
OAI22X1TS U4112 ( .A0(n3879), .A1(n1106), .B0(n4907), .B1(n1105), .Y(n1118)
);
XNOR2X1TS U4113 ( .A(n1349), .B(n3065), .Y(n1142) );
OAI22X1TS U4114 ( .A0(n4436), .A1(n1107), .B0(n4434), .B1(n1142), .Y(n1117)
);
CMPR32X2TS U4115 ( .A(n1110), .B(n1109), .C(n1108), .CO(n1379), .S(n1155) );
CMPR32X2TS U4116 ( .A(n1116), .B(n1115), .C(n1114), .CO(n1380), .S(n1153) );
CMPR32X2TS U4117 ( .A(n1119), .B(n1118), .C(n1117), .CO(n1329), .S(n1147) );
XNOR2X1TS U4118 ( .A(n2258), .B(n753), .Y(n1384) );
OAI22X1TS U4119 ( .A0(n4204), .A1(n1120), .B0(n4408), .B1(n1384), .Y(n1354)
);
XNOR2X1TS U4120 ( .A(n3138), .B(Op_MY[18]), .Y(n1348) );
OAI22X1TS U4121 ( .A0(n2149), .A1(n1122), .B0(n744), .B1(n1348), .Y(n1352)
);
XNOR2X1TS U4122 ( .A(n5874), .B(n4405), .Y(n1322) );
OAI22X1TS U4123 ( .A0(n2720), .A1(n1123), .B0(n4685), .B1(n1322), .Y(n1360)
);
XNOR2X1TS U4124 ( .A(n5342), .B(n2137), .Y(n1377) );
XNOR2X1TS U4125 ( .A(n6069), .B(n2385), .Y(n1390) );
OAI22X1TS U4126 ( .A0(n1518), .A1(n1125), .B0(n4322), .B1(n1390), .Y(n1358)
);
OAI22X1TS U4127 ( .A0(n4682), .A1(n1129), .B0(n807), .B1(n1370), .Y(n1357)
);
XNOR2X1TS U4128 ( .A(n800), .B(n4418), .Y(n1351) );
OAI22X1TS U4129 ( .A0(n3130), .A1(n1130), .B0(n2704), .B1(n1351), .Y(n1356)
);
ADDHX1TS U4130 ( .A(n1132), .B(n1131), .CO(n1355), .S(n1135) );
CMPR32X2TS U4131 ( .A(n1135), .B(n1134), .C(n1133), .CO(n1331), .S(n1144) );
XNOR2X4TS U4132 ( .A(Op_MX[38]), .B(Op_MX[37]), .Y(n4345) );
BUFX3TS U4133 ( .A(n5447), .Y(n6890) );
NOR2BX1TS U4134 ( .AN(n1988), .B(n6890), .Y(n1326) );
XNOR2X1TS U4135 ( .A(n6327), .B(n3833), .Y(n1376) );
OAI22X1TS U4136 ( .A0(n4243), .A1(n1136), .B0(n4892), .B1(n1376), .Y(n1325)
);
OAI22X1TS U4137 ( .A0(n2783), .A1(n1137), .B0(n3116), .B1(n1369), .Y(n1324)
);
CMPR32X2TS U4138 ( .A(n1140), .B(n1139), .C(n1138), .CO(n1319), .S(n1146) );
OAI22X1TS U4139 ( .A0(n1708), .A1(n1141), .B0(n2921), .B1(n1375), .Y(n1368)
);
XNOR2X1TS U4140 ( .A(n1349), .B(n3147), .Y(n1350) );
OAI22X1TS U4141 ( .A0(n1710), .A1(n1142), .B0(n4434), .B1(n1350), .Y(n1367)
);
XNOR2X1TS U4142 ( .A(n4916), .B(n3223), .Y(n1321) );
OAI22X1TS U4143 ( .A0(n717), .A1(n1143), .B0(n5390), .B1(n1321), .Y(n1366)
);
CMPR32X2TS U4144 ( .A(n1149), .B(n1148), .C(n1147), .CO(n1344), .S(n1161) );
CMPR32X2TS U4145 ( .A(n1152), .B(n1151), .C(n1150), .CO(n1160), .S(n1156) );
CMPR32X2TS U4146 ( .A(n1164), .B(n1163), .C(n1162), .CO(n1341), .S(n1165) );
ADDFHX2TS U4147 ( .A(n1167), .B(n1166), .CI(n1165), .CO(n1392), .S(n1317) );
BUFX12TS U4148 ( .A(n1168), .Y(n4555) );
OAI22X1TS U4149 ( .A0(n3575), .A1(n1212), .B0(n783), .B1(n1169), .Y(n1218)
);
OAI22X1TS U4150 ( .A0(n4115), .A1(n6714), .B0(n1170), .B1(n6651), .Y(n1217)
);
XNOR2X1TS U4151 ( .A(n3149), .B(n4418), .Y(n1242) );
OAI22X1TS U4152 ( .A0(n1708), .A1(n1242), .B0(n2921), .B1(n1171), .Y(n1216)
);
XNOR2X1TS U4153 ( .A(n4412), .B(n3774), .Y(n1199) );
OAI22X1TS U4154 ( .A0(n4057), .A1(n1199), .B0(n3899), .B1(n1175), .Y(n1198)
);
XNOR2X1TS U4155 ( .A(n756), .B(n1453), .Y(n1221) );
OAI22X1TS U4156 ( .A0(n4436), .A1(n1221), .B0(n760), .B1(n1177), .Y(n1196)
);
XNOR2X1TS U4157 ( .A(n742), .B(n3590), .Y(n1192) );
OAI22X1TS U4158 ( .A0(n4204), .A1(n1192), .B0(n4408), .B1(n1178), .Y(n1255)
);
XNOR2X1TS U4159 ( .A(n6069), .B(n2378), .Y(n1193) );
OAI22X1TS U4160 ( .A0(n1518), .A1(n1193), .B0(n4322), .B1(n1179), .Y(n1254)
);
XNOR2X1TS U4161 ( .A(n6054), .B(n2388), .Y(n1195) );
OAI22X1TS U4162 ( .A0(n761), .A1(n1195), .B0(n3863), .B1(n1181), .Y(n1253)
);
CMPR32X2TS U4163 ( .A(n1187), .B(n1186), .C(n1185), .CO(n1040), .S(n1250) );
XNOR2X1TS U4164 ( .A(n3138), .B(n2385), .Y(n1220) );
OAI22X1TS U4165 ( .A0(n4217), .A1(n1220), .B0(n625), .B1(n1188), .Y(n1258)
);
ADDHX1TS U4166 ( .A(n1190), .B(n1189), .CO(n1205), .S(n1257) );
NOR2BX1TS U4167 ( .AN(n1988), .B(n6651), .Y(n1261) );
XNOR2X1TS U4168 ( .A(n695), .B(n4372), .Y(n1301) );
OAI22X1TS U4169 ( .A0(n704), .A1(n1301), .B0(n3987), .B1(n1191), .Y(n1260)
);
XNOR2X1TS U4170 ( .A(n741), .B(n3105), .Y(n1289) );
OAI22X1TS U4171 ( .A0(n2416), .A1(n1289), .B0(n4408), .B1(n1192), .Y(n1259)
);
XNOR2X1TS U4172 ( .A(n8224), .B(n3992), .Y(n1302) );
BUFX8TS U4173 ( .A(n5292), .Y(n6456) );
OAI22X1TS U4174 ( .A0(n1518), .A1(n1302), .B0(n3866), .B1(n1193), .Y(n1279)
);
XNOR2X1TS U4175 ( .A(n636), .B(n2878), .Y(n1292) );
OAI22X1TS U4176 ( .A0(n1727), .A1(n1292), .B0(n3071), .B1(n1194), .Y(n1278)
);
XNOR2X1TS U4177 ( .A(n712), .B(n2262), .Y(n1291) );
OAI22X1TS U4178 ( .A0(n761), .A1(n1291), .B0(n3863), .B1(n1195), .Y(n1277)
);
XNOR2X1TS U4179 ( .A(n4412), .B(n5745), .Y(n1294) );
OAI22X1TS U4180 ( .A0(n4057), .A1(n1294), .B0(n3899), .B1(n1199), .Y(n1307)
);
XNOR2X1TS U4181 ( .A(n3895), .B(n2702), .Y(n1275) );
OAI22X1TS U4182 ( .A0(n1791), .A1(n1275), .B0(n786), .B1(n1200), .Y(n1306)
);
XNOR2X1TS U4183 ( .A(n3290), .B(n4419), .Y(n1202) );
XNOR2X1TS U4184 ( .A(n1945), .B(n8223), .Y(n1241) );
BUFX3TS U4185 ( .A(n639), .Y(n6300) );
XNOR2X1TS U4186 ( .A(n764), .B(n4090), .Y(n1274) );
OAI22X1TS U4187 ( .A0(n3575), .A1(n1274), .B0(n3231), .B1(n1212), .Y(n1297)
);
OAI22X1TS U4188 ( .A0(n1838), .A1(n1214), .B0(n1213), .B1(n1822), .Y(n1296)
);
XNOR2X1TS U4189 ( .A(n3726), .B(n4420), .Y(n1264) );
OAI22X1TS U4190 ( .A0(n2162), .A1(n1264), .B0(n2799), .B1(n1215), .Y(n1295)
);
XNOR2X1TS U4191 ( .A(n3611), .B(n3877), .Y(n1293) );
OAI22X1TS U4192 ( .A0(n3782), .A1(n1293), .B0(n3685), .B1(n1219), .Y(n1267)
);
XNOR2X1TS U4193 ( .A(n3138), .B(n746), .Y(n1304) );
OAI22X1TS U4194 ( .A0(n5956), .A1(n1304), .B0(n745), .B1(n1220), .Y(n1266)
);
XNOR2X1TS U4195 ( .A(n756), .B(n1491), .Y(n1276) );
OAI22X1TS U4196 ( .A0(n3793), .A1(n1276), .B0(n759), .B1(n1221), .Y(n1265)
);
CMPR32X2TS U4197 ( .A(n1227), .B(n1226), .C(n1225), .CO(n1270), .S(n1538) );
CMPR32X2TS U4198 ( .A(n1239), .B(n1238), .C(n1237), .CO(n1231), .S(n1585) );
OAI22X1TS U4199 ( .A0(n816), .A1(n1241), .B0(n4295), .B1(n1240), .Y(n1282)
);
XNOR2X1TS U4200 ( .A(n3149), .B(n5413), .Y(n1290) );
OAI22X1TS U4201 ( .A0(n1708), .A1(n1290), .B0(n1991), .B1(n1242), .Y(n1281)
);
XNOR2X1TS U4202 ( .A(n748), .B(n1965), .Y(n1263) );
OAI22X1TS U4203 ( .A0(n6381), .A1(n1263), .B0(n4116), .B1(n1243), .Y(n1280)
);
CMPR32X2TS U4204 ( .A(n1246), .B(n1245), .C(n1244), .CO(n1203), .S(n1299) );
CMPR32X2TS U4205 ( .A(n1252), .B(n1251), .C(n1250), .CO(n1269), .S(n1542) );
CMPR32X2TS U4206 ( .A(n1255), .B(n1254), .C(n1253), .CO(n1252), .S(n1546) );
CMPR32X2TS U4207 ( .A(n1261), .B(n1260), .C(n1259), .CO(n1256), .S(n1549) );
OAI22X1TS U4208 ( .A0(n816), .A1(n6299), .B0(n1262), .B1(n6300), .Y(n1531)
);
XNOR2X1TS U4209 ( .A(n748), .B(n1984), .Y(n1313) );
OAI22X1TS U4210 ( .A0(n6463), .A1(n1313), .B0(n4116), .B1(n1263), .Y(n1530)
);
XNOR2X1TS U4211 ( .A(n2006), .B(n4418), .Y(n1500) );
CMPR32X2TS U4212 ( .A(n1267), .B(n1266), .C(n1265), .CO(n1286), .S(n1547) );
ADDFHX2TS U4213 ( .A(n1270), .B(n1269), .CI(n1268), .CO(n1236), .S(n1582) );
OAI22X1TS U4214 ( .A0(n3575), .A1(n1496), .B0(n3231), .B1(n1274), .Y(n1528)
);
XNOR2X1TS U4215 ( .A(n3895), .B(n1453), .Y(n1492) );
OAI22X1TS U4216 ( .A0(n1791), .A1(n1492), .B0(n2668), .B1(n1275), .Y(n1527)
);
XNOR2X1TS U4217 ( .A(n756), .B(n713), .Y(n1504) );
OAI22X1TS U4218 ( .A0(n4436), .A1(n1504), .B0(n759), .B1(n1276), .Y(n1526)
);
CMPR32X2TS U4219 ( .A(n1282), .B(n1281), .C(n1280), .CO(n1300), .S(n1569) );
CMPR32X2TS U4220 ( .A(n1288), .B(n1287), .C(n1286), .CO(n1540), .S(n1475) );
XNOR2X1TS U4221 ( .A(n741), .B(n763), .Y(n1310) );
OAI22X1TS U4222 ( .A0(n2416), .A1(n1310), .B0(n4408), .B1(n1289), .Y(n1555)
);
XNOR2X1TS U4223 ( .A(n801), .B(n753), .Y(n1493) );
OAI22X1TS U4224 ( .A0(n3227), .A1(n1493), .B0(n2150), .B1(n1290), .Y(n1554)
);
XNOR2X1TS U4225 ( .A(n712), .B(n2675), .Y(n1502) );
OAI22X1TS U4226 ( .A0(n4606), .A1(n1502), .B0(n3863), .B1(n1291), .Y(n1553)
);
XNOR2X1TS U4227 ( .A(n636), .B(n2385), .Y(n1312) );
XNOR2X1TS U4228 ( .A(n811), .B(n3774), .Y(n1559) );
OAI22X1TS U4229 ( .A0(n3782), .A1(n1559), .B0(n3685), .B1(n1293), .Y(n1557)
);
XNOR2X1TS U4230 ( .A(n8213), .B(n3590), .Y(n1490) );
OAI22X1TS U4231 ( .A0(n4057), .A1(n1490), .B0(n3899), .B1(n1294), .Y(n1556)
);
CMPR32X2TS U4232 ( .A(n1297), .B(n1296), .C(n1295), .CO(n1288), .S(n1550) );
INVX8TS U4233 ( .A(n4425), .Y(n2378) );
XNOR2X1TS U4234 ( .A(n695), .B(n750), .Y(n1311) );
OAI22X1TS U4235 ( .A0(n1663), .A1(n1311), .B0(n3987), .B1(n1301), .Y(n1534)
);
XNOR2X1TS U4236 ( .A(n818), .B(n1947), .Y(n1314) );
OAI22X1TS U4237 ( .A0(n1518), .A1(n1314), .B0(n4322), .B1(n1302), .Y(n1533)
);
XNOR2X1TS U4238 ( .A(n5567), .B(n2388), .Y(n1503) );
OAI22X1TS U4239 ( .A0(n4581), .A1(n1503), .B0(n745), .B1(n1304), .Y(n1532)
);
CMPR32X2TS U4240 ( .A(n1307), .B(n1306), .C(n1305), .CO(n1283), .S(n1482) );
INVX4TS U4241 ( .A(n1201), .Y(n3605) );
NOR2BX1TS U4242 ( .AN(n3605), .B(n6300), .Y(n1565) );
XNOR2X1TS U4243 ( .A(n741), .B(n3207), .Y(n1487) );
OAI22X1TS U4244 ( .A0(n2416), .A1(n1487), .B0(n4408), .B1(n1310), .Y(n1564)
);
XNOR2X1TS U4245 ( .A(n695), .B(n2241), .Y(n1516) );
OAI22X1TS U4246 ( .A0(n687), .A1(n1516), .B0(n3680), .B1(n1311), .Y(n1563)
);
XNOR2X1TS U4247 ( .A(n768), .B(n746), .Y(n1508) );
OAI22X1TS U4248 ( .A0(n2400), .A1(n1508), .B0(n3228), .B1(n1312), .Y(n1522)
);
XNOR2X1TS U4249 ( .A(n1945), .B(n6364), .Y(n1488) );
XNOR2X1TS U4250 ( .A(n818), .B(n1965), .Y(n1517) );
OAI22X1TS U4251 ( .A0(n1518), .A1(n1517), .B0(n3866), .B1(n1314), .Y(n1520)
);
ADDFHX2TS U4252 ( .A(n1317), .B(n1316), .CI(n1315), .CO(n2631), .S(n2630) );
INVX4TS U4253 ( .A(n6153), .Y(n3270) );
XNOR2X1TS U4254 ( .A(n3691), .B(n3270), .Y(n1412) );
OAI22X1TS U4255 ( .A0(n718), .A1(n1321), .B0(n5390), .B1(n1412), .Y(n1471)
);
OAI22X1TS U4256 ( .A0(n2720), .A1(n1322), .B0(n4685), .B1(n1451), .Y(n1438)
);
XNOR2X1TS U4257 ( .A(n2797), .B(n6032), .Y(n1420) );
OAI22X1TS U4258 ( .A0(n2663), .A1(n1323), .B0(n1420), .B1(n2961), .Y(n1437)
);
CMPR32X2TS U4259 ( .A(n1329), .B(n1328), .C(n1327), .CO(n1434), .S(n1342) );
BUFX6TS U4260 ( .A(n642), .Y(n4919) );
INVX6TS U4261 ( .A(n5955), .Y(n4848) );
XNOR2X1TS U4262 ( .A(n4848), .B(n2887), .Y(n1409) );
OAI22X1TS U4263 ( .A0(n2149), .A1(n1348), .B0(n4919), .B1(n1409), .Y(n1424)
);
OAI22X1TS U4264 ( .A0(n5575), .A1(n1350), .B0(n4434), .B1(n1411), .Y(n1423)
);
OAI22X1TS U4265 ( .A0(n3130), .A1(n1351), .B0(n3537), .B1(n1410), .Y(n1422)
);
CMPR32X2TS U4266 ( .A(n1357), .B(n1356), .C(n1355), .CO(n1444), .S(n1332) );
XNOR2X1TS U4267 ( .A(n822), .B(n3065), .Y(n1419) );
OAI22X1TS U4268 ( .A0(n4835), .A1(n1361), .B0(n4661), .B1(n1419), .Y(n1443)
);
XOR2X4TS U4269 ( .A(n6686), .B(Op_MX[38]), .Y(n1362) );
NAND2X8TS U4270 ( .A(n1362), .B(n4345), .Y(n6149) );
XNOR2X1TS U4271 ( .A(n8212), .B(n5440), .Y(n1421) );
OAI22X1TS U4272 ( .A0(n4032), .A1(n1365), .B0(n2799), .B1(n1421), .Y(n1441)
);
CMPR32X2TS U4273 ( .A(n1368), .B(n1367), .C(n1366), .CO(n1413), .S(n1318) );
XNOR2X1TS U4274 ( .A(n8208), .B(n4888), .Y(n1440) );
XNOR2X1TS U4275 ( .A(n8819), .B(n6335), .Y(n1407) );
OAI22X1TS U4276 ( .A0(n4099), .A1(n1370), .B0(n806), .B1(n1407), .Y(n1464)
);
XNOR2X1TS U4277 ( .A(n3723), .B(n626), .Y(n1371) );
XNOR2X1TS U4278 ( .A(n3724), .B(n697), .Y(n1455) );
OAI22X1TS U4279 ( .A0(n6067), .A1(n1371), .B0(n1455), .B1(n6890), .Y(n1463)
);
CMPR32X2TS U4280 ( .A(n1374), .B(n1373), .C(n1372), .CO(n1461), .S(n1345) );
XNOR2X1TS U4281 ( .A(n3149), .B(n5203), .Y(n1456) );
OAI22X1TS U4282 ( .A0(n1708), .A1(n1375), .B0(n2921), .B1(n1456), .Y(n1449)
);
XNOR2X1TS U4283 ( .A(n4797), .B(n8236), .Y(n1439) );
OAI22X1TS U4284 ( .A0(n6795), .A1(n1376), .B0(n4892), .B1(n1439), .Y(n1448)
);
XNOR2X1TS U4285 ( .A(n748), .B(n746), .Y(n1450) );
OAI22X1TS U4286 ( .A0(n5625), .A1(n1377), .B0(n4487), .B1(n1450), .Y(n1447)
);
CMPR32X2TS U4287 ( .A(n1383), .B(n1382), .C(n1381), .CO(n1459), .S(n1346) );
XNOR2X1TS U4288 ( .A(n3102), .B(n790), .Y(n1466) );
OAI22X1TS U4289 ( .A0(n4204), .A1(n1384), .B0(n2414), .B1(n1466), .Y(n1406)
);
XNOR2X1TS U4290 ( .A(n8805), .B(n4372), .Y(n1468) );
OAI22X1TS U4291 ( .A0(n3879), .A1(n1385), .B0(n4907), .B1(n1468), .Y(n1405)
);
XNOR2X1TS U4292 ( .A(n791), .B(n2241), .Y(n1467) );
XNOR2X1TS U4293 ( .A(n3594), .B(n1491), .Y(n1454) );
OAI22X1TS U4294 ( .A0(n687), .A1(n1389), .B0(n3680), .B1(n1454), .Y(n1418)
);
XNOR2X1TS U4295 ( .A(n5489), .B(n1624), .Y(n1452) );
OAI22X1TS U4296 ( .A0(n4808), .A1(n1390), .B0(n4322), .B1(n1452), .Y(n1417)
);
OAI22X1TS U4297 ( .A0(n5305), .A1(n1391), .B0(n828), .B1(n1408), .Y(n1416)
);
OAI22X1TS U4298 ( .A0(n4682), .A1(n1407), .B0(n807), .B1(n2657), .Y(n2654)
);
XNOR2X1TS U4299 ( .A(n4848), .B(n2912), .Y(n2660) );
OAI22X1TS U4300 ( .A0(n2149), .A1(n1409), .B0(n4919), .B1(n2660), .Y(n2652)
);
XNOR2X1TS U4301 ( .A(n4412), .B(n4504), .Y(n2705) );
OAI22X1TS U4302 ( .A0(n3130), .A1(n1410), .B0(n3537), .B1(n2705), .Y(n2651)
);
OAI22X1TS U4303 ( .A0(n4436), .A1(n1411), .B0(n4434), .B1(n2659), .Y(n2650)
);
XNOR2X1TS U4304 ( .A(n2386), .B(n753), .Y(n2669) );
OAI22X1TS U4305 ( .A0(n718), .A1(n1412), .B0(n786), .B1(n2669), .Y(n2649) );
CMPR32X2TS U4306 ( .A(n1415), .B(n1414), .C(n1413), .CO(n2759), .S(n1401) );
CMPR32X2TS U4307 ( .A(n1418), .B(n1417), .C(n1416), .CO(n2679), .S(n1457) );
XNOR2X1TS U4308 ( .A(n823), .B(n3147), .Y(n2707) );
OAI22X1TS U4309 ( .A0(n4835), .A1(n1419), .B0(n4661), .B1(n2707), .Y(n2648)
);
XNOR2X1TS U4310 ( .A(n784), .B(n6823), .Y(n2662) );
OAI22X1TS U4311 ( .A0(n2663), .A1(n1420), .B0(n2662), .B1(n2961), .Y(n2647)
);
XNOR2X1TS U4312 ( .A(n3726), .B(n5526), .Y(n2709) );
OAI22X1TS U4313 ( .A0(n3164), .A1(n1421), .B0(n4259), .B1(n2709), .Y(n2646)
);
ADDFHX2TS U4314 ( .A(n1424), .B(n1423), .CI(n1422), .CO(n2677), .S(n1446) );
ADDFHX2TS U4315 ( .A(n1430), .B(n1429), .CI(n1428), .CO(n2809), .S(n1473) );
ADDHX1TS U4316 ( .A(n1438), .B(n1437), .CO(n2698), .S(n1470) );
XOR2X4TS U4317 ( .A(n697), .B(n877), .Y(n2785) );
OAI22X1TS U4318 ( .A0(n2783), .A1(n1440), .B0(n3116), .B1(n2655), .Y(n2722)
);
ADDFHX2TS U4319 ( .A(n1446), .B(n1445), .CI(n1444), .CO(n2747), .S(n1402) );
OAI22X1TS U4320 ( .A0(n6463), .A1(n1450), .B0(n4487), .B1(n2683), .Y(n2727)
);
XNOR2X1TS U4321 ( .A(n5489), .B(n2926), .Y(n2673) );
OAI22X1TS U4322 ( .A0(n3114), .A1(n1452), .B0(n3866), .B1(n2673), .Y(n2725)
);
XNOR2X1TS U4323 ( .A(n3594), .B(n1453), .Y(n2703) );
OAI22X1TS U4324 ( .A0(n704), .A1(n1454), .B0(n3680), .B1(n2703), .Y(n2686)
);
BUFX8TS U4325 ( .A(n5447), .Y(n5224) );
XNOR2X1TS U4326 ( .A(n5331), .B(n3833), .Y(n2667) );
OAI22X1TS U4327 ( .A0(n6067), .A1(n1455), .B0(n5224), .B1(n2667), .Y(n2685)
);
XNOR2X1TS U4328 ( .A(n801), .B(n5348), .Y(n2706) );
OAI22X1TS U4329 ( .A0(n1708), .A1(n1456), .B0(n2921), .B1(n2706), .Y(n2684)
);
OAI22X1TS U4330 ( .A0(n3259), .A1(n1466), .B0(n2868), .B1(n2680), .Y(n2701)
);
XNOR2X1TS U4331 ( .A(n5787), .B(n4208), .Y(n2656) );
OAI22X1TS U4332 ( .A0(n6487), .A1(n1467), .B0(n4687), .B1(n2656), .Y(n2700)
);
XNOR2X1TS U4333 ( .A(n8209), .B(n2675), .Y(n2682) );
OAI22X1TS U4334 ( .A0(n1468), .A1(n6716), .B0(n4907), .B1(n2682), .Y(n2699)
);
ADDFHX4TS U4335 ( .A(n1474), .B(n1473), .CI(n1472), .CO(n2637), .S(n2635) );
NOR2X8TS U4336 ( .A(n8016), .B(n2641), .Y(n2643) );
CMPR32X2TS U4337 ( .A(n1477), .B(n1476), .C(n1475), .CO(n1536), .S(n1631) );
ADDFHX1TS U4338 ( .A(n1480), .B(n1479), .CI(n1478), .CO(n1535), .S(n1630) );
CMPR32X2TS U4339 ( .A(n1486), .B(n1485), .C(n1484), .CO(n1481), .S(n1628) );
INVX6TS U4340 ( .A(n5601), .Y(n3159) );
OAI22X1TS U4341 ( .A0(n2416), .A1(n1605), .B0(n2414), .B1(n1487), .Y(n1658)
);
XNOR2X1TS U4342 ( .A(n3723), .B(n6364), .Y(n1489) );
XNOR2X1TS U4343 ( .A(n3726), .B(n6133), .Y(n1501) );
XNOR2X1TS U4344 ( .A(n3786), .B(n3105), .Y(n1494) );
OAI22X1TS U4345 ( .A0(n2454), .A1(n1494), .B0(n3899), .B1(n1490), .Y(n1507)
);
XNOR2X1TS U4346 ( .A(n3895), .B(n1491), .Y(n1495) );
OAI22X1TS U4347 ( .A0(n1791), .A1(n1495), .B0(n2668), .B1(n1492), .Y(n1506)
);
XNOR2X1TS U4348 ( .A(n1944), .B(n4090), .Y(n1509) );
OAI22X1TS U4349 ( .A0(n3227), .A1(n1509), .B0(n3175), .B1(n1493), .Y(n1505)
);
XNOR2X1TS U4350 ( .A(n800), .B(n763), .Y(n1622) );
OAI22X1TS U4351 ( .A0(n2454), .A1(n1622), .B0(n3899), .B1(n1494), .Y(n1661)
);
XNOR2X1TS U4352 ( .A(n3895), .B(n713), .Y(n1625) );
OAI22X1TS U4353 ( .A0(n1791), .A1(n1625), .B0(n2668), .B1(n1495), .Y(n1660)
);
XNOR2X1TS U4354 ( .A(n764), .B(n3877), .Y(n1497) );
OAI22X1TS U4355 ( .A0(n3575), .A1(n1616), .B0(n3231), .B1(n1497), .Y(n1562)
);
XNOR2X1TS U4356 ( .A(n2797), .B(n4420), .Y(n1499) );
OAI22X1TS U4357 ( .A0(n1838), .A1(n1606), .B0(n1499), .B1(n1822), .Y(n1561)
);
OAI22X1TS U4358 ( .A0(n3575), .A1(n1497), .B0(n3231), .B1(n1496), .Y(n1525)
);
OAI22X1TS U4359 ( .A0(n1838), .A1(n1499), .B0(n1498), .B1(n1822), .Y(n1524)
);
OAI22X1TS U4360 ( .A0(n2162), .A1(n1501), .B0(n2037), .B1(n1500), .Y(n1523)
);
XNOR2X1TS U4361 ( .A(n5132), .B(n3074), .Y(n1519) );
OAI22X1TS U4362 ( .A0(n6429), .A1(n1519), .B0(n3863), .B1(n1502), .Y(n1515)
);
OAI22X1TS U4363 ( .A0(n5956), .A1(n1512), .B0(n745), .B1(n1503), .Y(n1514)
);
XNOR2X1TS U4364 ( .A(n755), .B(n4882), .Y(n1511) );
OAI22X1TS U4365 ( .A0(n809), .A1(n1511), .B0(n759), .B1(n1504), .Y(n1513) );
XNOR2X1TS U4366 ( .A(n636), .B(n2388), .Y(n1609) );
OAI22X1TS U4367 ( .A0(n2400), .A1(n1609), .B0(n3228), .B1(n1508), .Y(n1652)
);
OAI22X1TS U4368 ( .A0(n3227), .A1(n1617), .B0(n3175), .B1(n1509), .Y(n1651)
);
OAI22X1TS U4369 ( .A0(n633), .A1(n6201), .B0(n1510), .B1(n6365), .Y(n1650)
);
XNOR2X1TS U4370 ( .A(n811), .B(n3590), .Y(n1619) );
XNOR2X1TS U4371 ( .A(n2383), .B(n5745), .Y(n1560) );
OAI22X1TS U4372 ( .A0(n3782), .A1(n1619), .B0(n3685), .B1(n1560), .Y(n1612)
);
XNOR2X1TS U4373 ( .A(n755), .B(n2385), .Y(n1623) );
INVX6TS U4374 ( .A(n8898), .Y(n5567) );
XNOR2X1TS U4375 ( .A(n3103), .B(n2675), .Y(n1621) );
OAI22X1TS U4376 ( .A0(n4581), .A1(n1621), .B0(n625), .B1(n1512), .Y(n1610)
);
CMPR32X2TS U4377 ( .A(n1515), .B(n1514), .C(n1513), .CO(n1567), .S(n1644) );
OAI22X1TS U4378 ( .A0(n1663), .A1(n1608), .B0(n3987), .B1(n1516), .Y(n1655)
);
XNOR2X1TS U4379 ( .A(n818), .B(n1984), .Y(n1618) );
OAI22X1TS U4380 ( .A0(n1518), .A1(n1618), .B0(n3866), .B1(n1517), .Y(n1654)
);
XNOR2X1TS U4381 ( .A(n712), .B(n750), .Y(n1620) );
OAI22X1TS U4382 ( .A0(n6429), .A1(n1620), .B0(n3863), .B1(n1519), .Y(n1653)
);
CMPR32X2TS U4383 ( .A(n1525), .B(n1524), .C(n1523), .CO(n1568), .S(n1638) );
CMPR32X2TS U4384 ( .A(n1528), .B(n1527), .C(n1526), .CO(n1571), .S(n1574) );
CMPR32X2TS U4385 ( .A(n1534), .B(n1533), .C(n1532), .CO(n1483), .S(n1572) );
CMPR32X2TS U4386 ( .A(n1546), .B(n1545), .C(n1544), .CO(n1541), .S(n1595) );
CMPR32X2TS U4387 ( .A(n1555), .B(n1554), .C(n1553), .CO(n1552), .S(n1604) );
CMPR32X2TS U4388 ( .A(n1558), .B(n1557), .C(n1556), .CO(n1551), .S(n1603) );
OAI22X1TS U4389 ( .A0(n3782), .A1(n1560), .B0(n3685), .B1(n1559), .Y(n1615)
);
ADDHX1TS U4390 ( .A(n1562), .B(n1561), .CO(n1614), .S(n1659) );
CMPR32X2TS U4391 ( .A(n1568), .B(n1567), .C(n1566), .CO(n1601), .S(n1626) );
CMPR32X2TS U4392 ( .A(n1571), .B(n1570), .C(n1569), .CO(n1477), .S(n1600) );
ADDFHX2TS U4393 ( .A(n1577), .B(n1576), .CI(n1575), .CO(n1234), .S(n1589) );
INVX4TS U4394 ( .A(n7992), .Y(n8011) );
ADDFHX2TS U4395 ( .A(n1595), .B(n1594), .CI(n1593), .CO(n1578), .S(n1634) );
CMPR32X2TS U4396 ( .A(n1601), .B(n1600), .C(n1599), .CO(n1593), .S(n1678) );
CMPR32X2TS U4397 ( .A(n1604), .B(n1603), .C(n1602), .CO(n1596), .S(n2355) );
XNOR2X1TS U4398 ( .A(n741), .B(n3044), .Y(n2375) );
OAI22X1TS U4399 ( .A0(n2416), .A1(n2375), .B0(n2414), .B1(n1605), .Y(n2382)
);
OAI22X1TS U4400 ( .A0(n1838), .A1(n1664), .B0(n1606), .B1(n1822), .Y(n2381)
);
XNOR2X1TS U4401 ( .A(n1839), .B(n4090), .Y(n1670) );
OAI22X1TS U4402 ( .A0(n4677), .A1(n1662), .B0(n3680), .B1(n1608), .Y(n1666)
);
XNOR2X1TS U4403 ( .A(n767), .B(n2262), .Y(n2359) );
OAI22X1TS U4404 ( .A0(n2400), .A1(n2359), .B0(n3228), .B1(n1609), .Y(n1665)
);
CMPR32X2TS U4405 ( .A(n1612), .B(n1611), .C(n1610), .CO(n1645), .S(n1671) );
OAI22X1TS U4406 ( .A0(n3575), .A1(n1668), .B0(n3231), .B1(n1616), .Y(n2392)
);
XNOR2X1TS U4407 ( .A(n751), .B(n3877), .Y(n2356) );
OAI22X1TS U4408 ( .A0(n3227), .A1(n2356), .B0(n3175), .B1(n1617), .Y(n2391)
);
XNOR2X1TS U4409 ( .A(n1945), .B(n818), .Y(n2357) );
OAI22X1TS U4410 ( .A0(n3114), .A1(n2357), .B0(n3866), .B1(n1618), .Y(n2390)
);
XNOR2X1TS U4411 ( .A(n2383), .B(n3105), .Y(n2384) );
OAI22X1TS U4412 ( .A0(n2450), .A1(n2384), .B0(n3685), .B1(n1619), .Y(n2365)
);
XNOR2X1TS U4413 ( .A(n712), .B(n2866), .Y(n2377) );
OAI22X1TS U4414 ( .A0(n2457), .A1(n2377), .B0(n829), .B1(n1620), .Y(n2364)
);
XNOR2X1TS U4415 ( .A(n3103), .B(n3074), .Y(n2379) );
OAI22X1TS U4416 ( .A0(n4581), .A1(n2379), .B0(n745), .B1(n1621), .Y(n2363)
);
XNOR2X1TS U4417 ( .A(n800), .B(n3207), .Y(n2393) );
OAI22X1TS U4418 ( .A0(n2454), .A1(n2393), .B0(n2452), .B1(n1622), .Y(n2362)
);
XNOR2X1TS U4419 ( .A(n756), .B(n746), .Y(n2389) );
OAI22X1TS U4420 ( .A0(n5667), .A1(n2389), .B0(n758), .B1(n1623), .Y(n2361)
);
XNOR2X1TS U4421 ( .A(n2386), .B(n2878), .Y(n2387) );
OAI22X1TS U4422 ( .A0(n1791), .A1(n2387), .B0(n2668), .B1(n1625), .Y(n2360)
);
CMPR32X2TS U4423 ( .A(n1640), .B(n1639), .C(n1638), .CO(n1648), .S(n2374) );
CMPR32X2TS U4424 ( .A(n1643), .B(n1642), .C(n1641), .CO(n1627), .S(n2373) );
CMPR32X2TS U4425 ( .A(n1649), .B(n1648), .C(n1647), .CO(n1635), .S(n2408) );
CMPR32X2TS U4426 ( .A(n1655), .B(n1654), .C(n1653), .CO(n1640), .S(n2370) );
CMPR32X2TS U4427 ( .A(n1661), .B(n1660), .C(n1659), .CO(n1641), .S(n2406) );
OAI22X1TS U4428 ( .A0(n6455), .A1(n2396), .B0(n3680), .B1(n1662), .Y(n2395)
);
XNOR2X1TS U4429 ( .A(n2797), .B(n752), .Y(n2417) );
OAI22X1TS U4430 ( .A0(n3211), .A1(n2417), .B0(n1664), .B1(n2159), .Y(n2394)
);
OAI22X1TS U4431 ( .A0(n3575), .A1(n2442), .B0(n3231), .B1(n1668), .Y(n2465)
);
OAI22X1TS U4432 ( .A0(n3114), .A1(n6108), .B0(n1669), .B1(n6456), .Y(n2464)
);
XNOR2X1TS U4433 ( .A(n2929), .B(n8233), .Y(n2419) );
OAI22X1TS U4434 ( .A0(n2162), .A1(n2419), .B0(n3051), .B1(n1670), .Y(n2463)
);
ADDFX2TS U4435 ( .A(n1676), .B(n1675), .CI(n1674), .CO(n2354), .S(n2410) );
NOR2X8TS U4436 ( .A(n2628), .B(n8006), .Y(n7866) );
XNOR2X1TS U4437 ( .A(n4404), .B(n747), .Y(n1684) );
XNOR2X1TS U4438 ( .A(n811), .B(n2385), .Y(n2111) );
OAI22X1TS U4439 ( .A0(n3104), .A1(n1684), .B0(n807), .B1(n2111), .Y(n2119)
);
XNOR2X1TS U4440 ( .A(n799), .B(n2132), .Y(n1699) );
XNOR2X1TS U4441 ( .A(n3786), .B(n2137), .Y(n2167) );
OAI22X1TS U4442 ( .A0(n4289), .A1(n1699), .B0(n2704), .B1(n2167), .Y(n2118)
);
BUFX3TS U4443 ( .A(n5675), .Y(n5795) );
OAI22X1TS U4444 ( .A0(n1727), .A1(n5794), .B0(n1680), .B1(n5795), .Y(n1682)
);
XNOR2X1TS U4445 ( .A(n8229), .B(n762), .Y(n1691) );
XNOR2X1TS U4446 ( .A(n8229), .B(n3105), .Y(n1735) );
BUFX3TS U4447 ( .A(n2159), .Y(n2134) );
OAI22X1TS U4448 ( .A0(n3596), .A1(n1691), .B0(n1735), .B1(n2134), .Y(n1681)
);
NOR2BX1TS U4449 ( .AN(n1988), .B(n5795), .Y(n1721) );
OAI22X1TS U4450 ( .A0(n2033), .A1(n1689), .B0(n2031), .B1(n1683), .Y(n1719)
);
OAI22X1TS U4451 ( .A0(n2783), .A1(n1683), .B0(n2031), .B1(n1734), .Y(n1687)
);
XNOR2X1TS U4452 ( .A(n3611), .B(n2137), .Y(n1715) );
XNOR2X1TS U4453 ( .A(n8211), .B(n713), .Y(n1701) );
XNOR2X1TS U4454 ( .A(n801), .B(n3044), .Y(n1688) );
OAI22X1TS U4455 ( .A0(n4443), .A1(n1701), .B0(n2150), .B1(n1688), .Y(n1685)
);
XNOR2X1TS U4456 ( .A(n2296), .B(n8812), .Y(n1725) );
NOR2BX1TS U4457 ( .AN(n8590), .B(n744), .Y(n2171) );
XNOR2X1TS U4458 ( .A(n3102), .B(n1943), .Y(n1696) );
XNOR2X1TS U4459 ( .A(n3102), .B(n4405), .Y(n2133) );
OAI22X1TS U4460 ( .A0(n2281), .A1(n1696), .B0(n2868), .B1(n2133), .Y(n2170)
);
ADDFHX2TS U4461 ( .A(n1687), .B(n1686), .CI(n1685), .CO(n2177), .S(n1743) );
XNOR2X1TS U4462 ( .A(n2386), .B(n2241), .Y(n1698) );
XNOR2X1TS U4463 ( .A(n2386), .B(n750), .Y(n2113) );
OAI22X1TS U4464 ( .A0(n717), .A1(n1698), .B0(n2668), .B1(n2113), .Y(n2128)
);
XNOR2X1TS U4465 ( .A(n801), .B(n3159), .Y(n2122) );
OAI22X1TS U4466 ( .A0(n4443), .A1(n1688), .B0(n2150), .B1(n2122), .Y(n2127)
);
XNOR2X1TS U4467 ( .A(n677), .B(n2259), .Y(n1728) );
XNOR2X1TS U4468 ( .A(n677), .B(n2376), .Y(n2112) );
OAI22X1TS U4469 ( .A0(n809), .A1(n1728), .B0(n760), .B1(n2112), .Y(n2126) );
XNOR2X1TS U4470 ( .A(n685), .B(n2137), .Y(n1752) );
OAI22X1TS U4471 ( .A0(n2033), .A1(n1752), .B0(n2031), .B1(n1689), .Y(n1756)
);
XNOR2X1TS U4472 ( .A(n3290), .B(n678), .Y(n1690) );
XNOR2X1TS U4473 ( .A(n2296), .B(n678), .Y(n1702) );
XNOR2X1TS U4474 ( .A(n1839), .B(n713), .Y(n1765) );
XNOR2X1TS U4475 ( .A(n1839), .B(n3044), .Y(n1692) );
OAI22X1TS U4476 ( .A0(n4260), .A1(n1765), .B0(n1912), .B1(n1692), .Y(n1754)
);
XNOR2X1TS U4477 ( .A(n798), .B(n1943), .Y(n1693) );
XNOR2X1TS U4478 ( .A(n798), .B(n4405), .Y(n1700) );
OAI22X1TS U4479 ( .A0(n4880), .A1(n1693), .B0(n2704), .B1(n1700), .Y(n1706)
);
XNOR2X1TS U4480 ( .A(n8229), .B(n3207), .Y(n1695) );
OAI22X1TS U4481 ( .A0(n3837), .A1(n1695), .B0(n1691), .B1(n2134), .Y(n1705)
);
XNOR2X1TS U4482 ( .A(n1839), .B(n3159), .Y(n1730) );
OAI22X1TS U4483 ( .A0(n4032), .A1(n1692), .B0(n1912), .B1(n1730), .Y(n1704)
);
XNOR2X1TS U4484 ( .A(n736), .B(n811), .Y(n1763) );
XNOR2X1TS U4485 ( .A(n4218), .B(n2132), .Y(n1716) );
OAI22X1TS U4486 ( .A0(n3104), .A1(n1763), .B0(n807), .B1(n1716), .Y(n1771)
);
XNOR2X1TS U4487 ( .A(n800), .B(n2378), .Y(n1768) );
OAI22X1TS U4488 ( .A0(n4289), .A1(n1768), .B0(n2704), .B1(n1693), .Y(n1770)
);
XNOR2X1TS U4489 ( .A(n2258), .B(n1947), .Y(n1753) );
OAI22X1TS U4490 ( .A0(n2281), .A1(n1753), .B0(n2868), .B1(n1694), .Y(n1718)
);
XNOR2X1TS U4491 ( .A(n784), .B(n3159), .Y(n1764) );
OAI22X1TS U4492 ( .A0(n3837), .A1(n1764), .B0(n1695), .B1(n2134), .Y(n1717)
);
OAI22X1TS U4493 ( .A0(n2281), .A1(n1697), .B0(n2868), .B1(n1696), .Y(n1733)
);
XNOR2X1TS U4494 ( .A(n2386), .B(n2376), .Y(n1703) );
BUFX4TS U4495 ( .A(n930), .Y(n3031) );
OAI22X1TS U4496 ( .A0(n717), .A1(n1703), .B0(n3031), .B1(n1698), .Y(n1732)
);
OAI22X1TS U4497 ( .A0(n4289), .A1(n1700), .B0(n2704), .B1(n1699), .Y(n1731)
);
XNOR2X1TS U4498 ( .A(n8211), .B(n2878), .Y(n1707) );
OAI22X1TS U4499 ( .A0(n3069), .A1(n1707), .B0(n2150), .B1(n1701), .Y(n1714)
);
XNOR2X1TS U4500 ( .A(n677), .B(n2247), .Y(n1729) );
OAI22X1TS U4501 ( .A0(n1710), .A1(n1702), .B0(n758), .B1(n1729), .Y(n1713)
);
XNOR2X1TS U4502 ( .A(n2386), .B(n2259), .Y(n1711) );
OAI22X1TS U4503 ( .A0(n718), .A1(n1711), .B0(n2668), .B1(n1703), .Y(n1712)
);
XNOR2X1TS U4504 ( .A(n8211), .B(n696), .Y(n1766) );
OAI22X1TS U4505 ( .A0(n1708), .A1(n1766), .B0(n1991), .B1(n1707), .Y(n1759)
);
OAI22X1TS U4506 ( .A0(n3793), .A1(n5665), .B0(n1709), .B1(n5666), .Y(n1758)
);
XNOR2X1TS U4507 ( .A(n2386), .B(n2247), .Y(n1767) );
OAI22X1TS U4508 ( .A0(n718), .A1(n1767), .B0(n2668), .B1(n1711), .Y(n1757)
);
OAI22X1TS U4509 ( .A0(n3104), .A1(n1716), .B0(n808), .B1(n1715), .Y(n1742)
);
CMPR32X2TS U4510 ( .A(n1721), .B(n1720), .C(n1719), .CO(n1744), .S(n1740) );
CMPR32X2TS U4511 ( .A(n1724), .B(n1723), .C(n1722), .CO(n2184), .S(n1750) );
XNOR2X1TS U4512 ( .A(n3290), .B(n825), .Y(n1726) );
OAI22X1TS U4513 ( .A0(n1727), .A1(n1726), .B0(n1725), .B1(n5795), .Y(n1739)
);
OAI22X1TS U4514 ( .A0(n809), .A1(n1729), .B0(n760), .B1(n1728), .Y(n1738) );
XNOR2X1TS U4515 ( .A(n1839), .B(n3207), .Y(n1736) );
OAI22X1TS U4516 ( .A0(n810), .A1(n1730), .B0(n1912), .B1(n1736), .Y(n1737)
);
XNOR2X1TS U4517 ( .A(n764), .B(n2926), .Y(n2123) );
OAI22X1TS U4518 ( .A0(n2444), .A1(n1734), .B0(n783), .B1(n2123), .Y(n2116)
);
XNOR2X1TS U4519 ( .A(n8794), .B(n3590), .Y(n2135) );
OAI22X1TS U4520 ( .A0(n3837), .A1(n1735), .B0(n2135), .B1(n2134), .Y(n2115)
);
XNOR2X1TS U4521 ( .A(n1839), .B(n763), .Y(n2125) );
OAI22X1TS U4522 ( .A0(n4260), .A1(n1736), .B0(n1912), .B1(n2125), .Y(n2114)
);
CMPR32X2TS U4523 ( .A(n1739), .B(n1738), .C(n1737), .CO(n2181), .S(n1748) );
CMPR32X2TS U4524 ( .A(n1742), .B(n1741), .C(n1740), .CO(n1747), .S(n1775) );
CMPR32X2TS U4525 ( .A(n1745), .B(n1744), .C(n1743), .CO(n2130), .S(n1746) );
CMPR32X2TS U4526 ( .A(n1748), .B(n1747), .C(n1746), .CO(n2182), .S(n1774) );
NOR2BX1TS U4527 ( .AN(n1988), .B(n5666), .Y(n1780) );
XNOR2X1TS U4528 ( .A(n2258), .B(n1965), .Y(n1782) );
OAI22X1TS U4529 ( .A0(n2281), .A1(n1782), .B0(n2414), .B1(n1753), .Y(n1779)
);
CMPR32X2TS U4530 ( .A(n1756), .B(n1755), .C(n1754), .CO(n1762), .S(n1786) );
CMPR32X2TS U4531 ( .A(n1759), .B(n1758), .C(n1757), .CO(n1777), .S(n1785) );
CMPR32X2TS U4532 ( .A(n1762), .B(n1761), .C(n1760), .CO(n1751), .S(n1800) );
XNOR2X1TS U4533 ( .A(n811), .B(n1943), .Y(n1805) );
XNOR2X1TS U4534 ( .A(n784), .B(n3044), .Y(n1778) );
OAI22X1TS U4535 ( .A0(n3596), .A1(n1778), .B0(n1764), .B1(n2134), .Y(n1794)
);
XNOR2X1TS U4536 ( .A(n1839), .B(n1624), .Y(n1784) );
OAI22X1TS U4537 ( .A0(n2162), .A1(n1784), .B0(n1912), .B1(n1765), .Y(n1793)
);
XNOR2X1TS U4538 ( .A(n8211), .B(n747), .Y(n1788) );
OAI22X1TS U4539 ( .A0(n1993), .A1(n1788), .B0(n1991), .B1(n1766), .Y(n1798)
);
OAI22X1TS U4540 ( .A0(n1791), .A1(n1789), .B0(n2668), .B1(n1767), .Y(n1797)
);
XNOR2X1TS U4541 ( .A(n799), .B(n2241), .Y(n1792) );
OAI22X1TS U4542 ( .A0(n4289), .A1(n1792), .B0(n2452), .B1(n1768), .Y(n1796)
);
CMPR32X2TS U4543 ( .A(n1771), .B(n1770), .C(n1769), .CO(n1760), .S(n1823) );
CMPR32X2TS U4544 ( .A(n1777), .B(n1776), .C(n1775), .CO(n1749), .S(n1804) );
XNOR2X1TS U4545 ( .A(n685), .B(n4405), .Y(n1807) );
XNOR2X1TS U4546 ( .A(n3203), .B(n713), .Y(n1836) );
OAI22X1TS U4547 ( .A0(n1838), .A1(n1836), .B0(n1778), .B1(n2134), .Y(n1808)
);
XNOR2X1TS U4548 ( .A(n2258), .B(n1984), .Y(n1806) );
OAI22X1TS U4549 ( .A0(n2281), .A1(n1806), .B0(n2414), .B1(n1782), .Y(n1815)
);
OAI22X1TS U4550 ( .A0(n1791), .A1(n5533), .B0(n1783), .B1(n5534), .Y(n1814)
);
XNOR2X1TS U4551 ( .A(n1839), .B(n696), .Y(n1840) );
OAI22X1TS U4552 ( .A0(n2039), .A1(n1840), .B0(n2037), .B1(n1784), .Y(n1813)
);
XNOR2X1TS U4553 ( .A(n1944), .B(n2137), .Y(n1819) );
OAI22X1TS U4554 ( .A0(n1993), .A1(n1819), .B0(n1991), .B1(n1788), .Y(n1818)
);
XNOR2X1TS U4555 ( .A(n3723), .B(n4850), .Y(n1790) );
OAI22X1TS U4556 ( .A0(n1791), .A1(n1790), .B0(n1789), .B1(n5534), .Y(n1817)
);
XNOR2X1TS U4557 ( .A(n800), .B(n1947), .Y(n1820) );
OAI22X1TS U4558 ( .A0(n4289), .A1(n1820), .B0(n2704), .B1(n1792), .Y(n1816)
);
CMPR32X2TS U4559 ( .A(n1798), .B(n1797), .C(n1796), .CO(n1824), .S(n1832) );
XNOR2X1TS U4560 ( .A(n4218), .B(n750), .Y(n1835) );
OAI22X1TS U4561 ( .A0(n3104), .A1(n1835), .B0(n807), .B1(n1805), .Y(n1843)
);
NOR2BX1TS U4562 ( .AN(n1988), .B(n5534), .Y(n1846) );
OAI22X1TS U4563 ( .A0(n2416), .A1(n1847), .B0(n2414), .B1(n1806), .Y(n1845)
);
OAI22X1TS U4564 ( .A0(n2033), .A1(n2030), .B0(n2031), .B1(n1807), .Y(n1844)
);
CMPR32X2TS U4565 ( .A(n1815), .B(n1814), .C(n1813), .CO(n1810), .S(n2029) );
XNOR2X1TS U4566 ( .A(n751), .B(n2132), .Y(n1850) );
OAI22X1TS U4567 ( .A0(n1993), .A1(n1850), .B0(n1991), .B1(n1819), .Y(n2042)
);
XNOR2X1TS U4568 ( .A(n800), .B(n1965), .Y(n2034) );
OAI22X1TS U4569 ( .A0(n4289), .A1(n2034), .B0(n2452), .B1(n1820), .Y(n2041)
);
OAI22X1TS U4570 ( .A0(n2416), .A1(n5326), .B0(n1821), .B1(n5327), .Y(n2044)
);
XNOR2X1TS U4571 ( .A(n1948), .B(n696), .Y(n2003) );
XNOR2X1TS U4572 ( .A(n8794), .B(n1624), .Y(n1837) );
OAI22X1TS U4573 ( .A0(n1838), .A1(n2003), .B0(n1837), .B1(n1822), .Y(n2043)
);
CMPR32X2TS U4574 ( .A(n1825), .B(n1824), .C(n1823), .CO(n1799), .S(n1830) );
CMPR32X2TS U4575 ( .A(n1828), .B(n1827), .C(n1826), .CO(n1803), .S(n1829) );
CMPR32X2TS U4576 ( .A(n1834), .B(n1833), .C(n1832), .CO(n1826), .S(n2026) );
XNOR2X1TS U4577 ( .A(n4218), .B(n2241), .Y(n1849) );
OAI22X1TS U4578 ( .A0(n3104), .A1(n1849), .B0(n2448), .B1(n1835), .Y(n1853)
);
OAI22X1TS U4579 ( .A0(n1838), .A1(n1837), .B0(n1836), .B1(n2134), .Y(n1852)
);
XNOR2X1TS U4580 ( .A(n1839), .B(n747), .Y(n2036) );
OAI22X1TS U4581 ( .A0(n810), .A1(n2036), .B0(n2037), .B1(n1840), .Y(n1851)
);
XNOR2X1TS U4582 ( .A(n3642), .B(n742), .Y(n1848) );
OAI22X1TS U4583 ( .A0(n2416), .A1(n1848), .B0(n1847), .B1(n5327), .Y(n2050)
);
XNOR2X1TS U4584 ( .A(n3611), .B(n1947), .Y(n2000) );
XNOR2X1TS U4585 ( .A(n751), .B(n736), .Y(n1990) );
OAI22X1TS U4586 ( .A0(n1993), .A1(n1990), .B0(n1991), .B1(n1850), .Y(n2048)
);
CMPR32X2TS U4587 ( .A(n1853), .B(n1852), .C(n1851), .CO(n2053), .S(n2057) );
XNOR2X1TS U4588 ( .A(n1945), .B(n8794), .Y(n1857) );
XNOR2X1TS U4589 ( .A(n784), .B(n1984), .Y(n1862) );
OAI22X1TS U4590 ( .A0(n2663), .A1(n1857), .B0(n1862), .B1(n2134), .Y(n1860)
);
NOR2BX1TS U4591 ( .AN(n8590), .B(n4259), .Y(n1859) );
OAI22X1TS U4592 ( .A0(n2663), .A1(n3290), .B0(n1857), .B1(n2134), .Y(n8586)
);
NAND2X1TS U4593 ( .A(n1858), .B(n2005), .Y(n8585) );
INVX2TS U4594 ( .A(n8587), .Y(n8582) );
NAND2X1TS U4595 ( .A(n1860), .B(n1859), .Y(n8581) );
INVX2TS U4596 ( .A(n8581), .Y(n1861) );
XNOR2X1TS U4597 ( .A(n784), .B(n1965), .Y(n1867) );
BUFX3TS U4598 ( .A(n2159), .Y(n2002) );
OAI22X1TS U4599 ( .A0(n2663), .A1(n1862), .B0(n1867), .B1(n2002), .Y(n1870)
);
XNOR2X1TS U4600 ( .A(n3642), .B(n8212), .Y(n1863) );
XNOR2X1TS U4601 ( .A(n1945), .B(n8212), .Y(n1868) );
OAI22X1TS U4602 ( .A0(n2162), .A1(n1863), .B0(n1868), .B1(n4259), .Y(n1869)
);
NAND2BX1TS U4603 ( .AN(n3067), .B(n8212), .Y(n1864) );
OAI22X1TS U4604 ( .A0(n3164), .A1(n4258), .B0(n1864), .B1(n4259), .Y(n1865)
);
NOR2BX1TS U4605 ( .AN(n8590), .B(n4442), .Y(n1880) );
XNOR2X1TS U4606 ( .A(n3203), .B(n1947), .Y(n1875) );
OAI22X1TS U4607 ( .A0(n2005), .A1(n1867), .B0(n1875), .B1(n2002), .Y(n1879)
);
XNOR2X1TS U4608 ( .A(n2006), .B(n1984), .Y(n1877) );
OAI22X1TS U4609 ( .A0(n3164), .A1(n1868), .B0(n1912), .B1(n1877), .Y(n1878)
);
NAND2X1TS U4610 ( .A(n1872), .B(n1871), .Y(n8592) );
INVX2TS U4611 ( .A(n8592), .Y(n1873) );
XNOR2X1TS U4612 ( .A(n3723), .B(n8211), .Y(n1874) );
XNOR2X1TS U4613 ( .A(n1945), .B(n8211), .Y(n1884) );
OAI22X1TS U4614 ( .A0(n3069), .A1(n1874), .B0(n1884), .B1(n4442), .Y(n1901)
);
XNOR2X1TS U4615 ( .A(n1948), .B(n3992), .Y(n1886) );
OAI22X1TS U4616 ( .A0(n2005), .A1(n1875), .B0(n1886), .B1(n2002), .Y(n1900)
);
OAI22X1TS U4617 ( .A0(n3069), .A1(n4441), .B0(n1876), .B1(n4442), .Y(n1892)
);
XNOR2X1TS U4618 ( .A(n2006), .B(n1965), .Y(n1890) );
OAI22X1TS U4619 ( .A0(n2039), .A1(n1877), .B0(n1912), .B1(n1890), .Y(n1891)
);
CMPR32X2TS U4620 ( .A(n1880), .B(n1879), .C(n1878), .CO(n1881), .S(n1872) );
NOR2X2TS U4621 ( .A(n1882), .B(n1881), .Y(n8603) );
NAND2X1TS U4622 ( .A(n1882), .B(n1881), .Y(n8604) );
OAI22X1TS U4623 ( .A0(n2444), .A1(n4555), .B0(n1883), .B1(n4608), .Y(n1915)
);
XNOR2X1TS U4624 ( .A(n1948), .B(n2378), .Y(n1885) );
XNOR2X1TS U4625 ( .A(n3203), .B(n1943), .Y(n1910) );
OAI22X1TS U4626 ( .A0(n2005), .A1(n1885), .B0(n1910), .B1(n2002), .Y(n1914)
);
NOR2BX1TS U4627 ( .AN(n8590), .B(n783), .Y(n1895) );
XNOR2X1TS U4628 ( .A(n1944), .B(n1984), .Y(n1888) );
OAI22X1TS U4629 ( .A0(n4443), .A1(n1884), .B0(n2150), .B1(n1888), .Y(n1894)
);
OAI22X1TS U4630 ( .A0(n2005), .A1(n1886), .B0(n1885), .B1(n2002), .Y(n1893)
);
XNOR2X1TS U4631 ( .A(n3642), .B(n8208), .Y(n1887) );
XNOR2X1TS U4632 ( .A(n1945), .B(n4607), .Y(n1918) );
OAI22X1TS U4633 ( .A0(n2444), .A1(n1887), .B0(n1918), .B1(n2270), .Y(n1926)
);
XNOR2X1TS U4634 ( .A(n751), .B(n1965), .Y(n1920) );
OAI22X1TS U4635 ( .A0(n1993), .A1(n1888), .B0(n2150), .B1(n1920), .Y(n1925)
);
XNOR2X1TS U4636 ( .A(n2006), .B(n1947), .Y(n1889) );
XNOR2X1TS U4637 ( .A(n2006), .B(n2866), .Y(n1913) );
OAI22X1TS U4638 ( .A0(n2162), .A1(n1889), .B0(n2037), .B1(n1913), .Y(n1924)
);
OAI22X1TS U4639 ( .A0(n810), .A1(n1890), .B0(n1912), .B1(n1889), .Y(n1898)
);
ADDHXLTS U4640 ( .A(n1892), .B(n1891), .CO(n1897), .S(n1899) );
CMPR32X2TS U4641 ( .A(n1895), .B(n1894), .C(n1893), .CO(n1934), .S(n1896) );
NOR2X2TS U4642 ( .A(n1903), .B(n1902), .Y(n8641) );
AOI21X4TS U4643 ( .A0(n8610), .A1(n1907), .B0(n1906), .Y(n8597) );
XNOR2X1TS U4644 ( .A(n3290), .B(n4681), .Y(n1908) );
XNOR2X1TS U4645 ( .A(n1945), .B(n4681), .Y(n1961) );
OAI22X1TS U4646 ( .A0(n2450), .A1(n1908), .B0(n1961), .B1(n4845), .Y(n1957)
);
OAI22X1TS U4647 ( .A0(n2450), .A1(n957), .B0(n1909), .B1(n4845), .Y(n1956)
);
XNOR2X1TS U4648 ( .A(n2006), .B(n750), .Y(n1911) );
XNOR2X1TS U4649 ( .A(n2006), .B(n1943), .Y(n1964) );
OAI22X1TS U4650 ( .A0(n2162), .A1(n1911), .B0(n2037), .B1(n1964), .Y(n1955)
);
XNOR2X1TS U4651 ( .A(n3203), .B(n736), .Y(n1916) );
OAI22X1TS U4652 ( .A0(n2005), .A1(n1910), .B0(n1916), .B1(n2002), .Y(n1929)
);
OAI22X1TS U4653 ( .A0(n4260), .A1(n1913), .B0(n1912), .B1(n1911), .Y(n1928)
);
ADDHXLTS U4654 ( .A(n1915), .B(n1914), .CO(n1927), .S(n1935) );
XNOR2X1TS U4655 ( .A(n1944), .B(n1947), .Y(n1919) );
XNOR2X1TS U4656 ( .A(n751), .B(n2241), .Y(n1954) );
OAI22X1TS U4657 ( .A0(n1993), .A1(n1919), .B0(n1991), .B1(n1954), .Y(n1974)
);
OAI22X1TS U4658 ( .A0(n2033), .A1(n1917), .B0(n4608), .B1(n1952), .Y(n1950)
);
XNOR2X1TS U4659 ( .A(n1948), .B(n2132), .Y(n1963) );
OAI22X1TS U4660 ( .A0(n2005), .A1(n1916), .B0(n1963), .B1(n2002), .Y(n1949)
);
NOR2BX1TS U4661 ( .AN(n8590), .B(n4845), .Y(n1923) );
OAI22X1TS U4662 ( .A0(n2444), .A1(n1918), .B0(n783), .B1(n1917), .Y(n1922)
);
OAI22X1TS U4663 ( .A0(n1993), .A1(n1920), .B0(n2150), .B1(n1919), .Y(n1921)
);
CMPR32X2TS U4664 ( .A(n1923), .B(n1922), .C(n1921), .CO(n1972), .S(n1932) );
CMPR32X2TS U4665 ( .A(n1926), .B(n1925), .C(n1924), .CO(n1931), .S(n1933) );
CMPR32X2TS U4666 ( .A(n1929), .B(n1928), .C(n1927), .CO(n1982), .S(n1930) );
CMPR32X2TS U4667 ( .A(n1932), .B(n1931), .C(n1930), .CO(n1938), .S(n1937) );
CMPR32X2TS U4668 ( .A(n1935), .B(n1934), .C(n1933), .CO(n1936), .S(n1905) );
INVX2TS U4669 ( .A(n8599), .Y(n1940) );
XNOR2X1TS U4670 ( .A(n751), .B(n2378), .Y(n1953) );
XNOR2X1TS U4671 ( .A(n751), .B(n1943), .Y(n1992) );
OAI22X1TS U4672 ( .A0(n1993), .A1(n1953), .B0(n1991), .B1(n1992), .Y(n2010)
);
XNOR2X1TS U4673 ( .A(n3290), .B(n3786), .Y(n1946) );
XNOR2X1TS U4674 ( .A(n1945), .B(n3786), .Y(n1985) );
OAI22X1TS U4675 ( .A0(n2454), .A1(n1946), .B0(n1985), .B1(n804), .Y(n2009)
);
XNOR2X1TS U4676 ( .A(n685), .B(n1947), .Y(n1951) );
OAI22X1TS U4677 ( .A0(n2033), .A1(n1951), .B0(n2031), .B1(n1989), .Y(n1987)
);
XNOR2X1TS U4678 ( .A(n784), .B(n2137), .Y(n1962) );
XNOR2X1TS U4679 ( .A(n2797), .B(n746), .Y(n2004) );
OAI22X1TS U4680 ( .A0(n2005), .A1(n1962), .B0(n2004), .B1(n2002), .Y(n1986)
);
ADDHX1TS U4681 ( .A(n1950), .B(n1949), .CO(n1977), .S(n1973) );
NOR2BX1TS U4682 ( .AN(n1988), .B(n804), .Y(n1960) );
OAI22X1TS U4683 ( .A0(n2033), .A1(n1952), .B0(n4608), .B1(n1951), .Y(n1959)
);
OAI22X1TS U4684 ( .A0(n1993), .A1(n1954), .B0(n2150), .B1(n1953), .Y(n1958)
);
CMPR32X2TS U4685 ( .A(n1957), .B(n1956), .C(n1955), .CO(n1975), .S(n1983) );
XNOR2X1TS U4686 ( .A(n3611), .B(n1984), .Y(n1966) );
OAI22X1TS U4687 ( .A0(n2450), .A1(n1961), .B0(n2448), .B1(n1966), .Y(n1971)
);
OAI22X1TS U4688 ( .A0(n2005), .A1(n1963), .B0(n1962), .B1(n2002), .Y(n1970)
);
XNOR2X1TS U4689 ( .A(n2006), .B(n736), .Y(n1968) );
OAI22X1TS U4690 ( .A0(n810), .A1(n1964), .B0(n2037), .B1(n1968), .Y(n1969)
);
XNOR2X1TS U4691 ( .A(n4218), .B(n1965), .Y(n2001) );
OAI22X1TS U4692 ( .A0(n3104), .A1(n1966), .B0(n2448), .B1(n2001), .Y(n1999)
);
OAI22X1TS U4693 ( .A0(n2454), .A1(n5092), .B0(n1967), .B1(n803), .Y(n1998)
);
XNOR2X1TS U4694 ( .A(n2006), .B(n2132), .Y(n2007) );
OAI22X1TS U4695 ( .A0(n3164), .A1(n1968), .B0(n2037), .B1(n2007), .Y(n1997)
);
CMPR32X2TS U4696 ( .A(n1971), .B(n1970), .C(n1969), .CO(n1995), .S(n1980) );
CMPR32X2TS U4697 ( .A(n1974), .B(n1973), .C(n1972), .CO(n1979), .S(n1981) );
OR2X4TS U4698 ( .A(n2017), .B(n2016), .Y(n8661) );
NOR2X2TS U4699 ( .A(n2015), .B(n2014), .Y(n8658) );
INVX2TS U4700 ( .A(n8658), .Y(n8619) );
NAND2X2TS U4701 ( .A(n8661), .B(n8619), .Y(n8623) );
XNOR2X1TS U4702 ( .A(n800), .B(n1984), .Y(n2035) );
OAI22X1TS U4703 ( .A0(n2454), .A1(n1985), .B0(n2452), .B1(n2035), .Y(n2068)
);
NOR2BX1TS U4704 ( .AN(n1988), .B(n5327), .Y(n2047) );
XNOR2X1TS U4705 ( .A(n685), .B(n4208), .Y(n2032) );
OAI22X1TS U4706 ( .A0(n2033), .A1(n1989), .B0(n783), .B1(n2032), .Y(n2046)
);
OAI22X1TS U4707 ( .A0(n1993), .A1(n1992), .B0(n1991), .B1(n1990), .Y(n2045)
);
CMPR32X2TS U4708 ( .A(n1996), .B(n1995), .C(n1994), .CO(n2088), .S(n2011) );
CMPR32X2TS U4709 ( .A(n1999), .B(n1998), .C(n1997), .CO(n2080), .S(n1994) );
OAI22X1TS U4710 ( .A0(n3104), .A1(n2001), .B0(n2448), .B1(n2000), .Y(n2065)
);
OAI22X1TS U4711 ( .A0(n2005), .A1(n2004), .B0(n2003), .B1(n2002), .Y(n2064)
);
XNOR2X1TS U4712 ( .A(n2006), .B(n2137), .Y(n2038) );
OAI22X1TS U4713 ( .A0(n3164), .A1(n2007), .B0(n2037), .B1(n2038), .Y(n2063)
);
NOR2X4TS U4714 ( .A(n2021), .B(n2020), .Y(n8624) );
NOR2X2TS U4715 ( .A(n8623), .B(n8624), .Y(n2023) );
NAND2X2TS U4716 ( .A(n2015), .B(n2014), .Y(n8657) );
INVX2TS U4717 ( .A(n8657), .Y(n2019) );
NAND2X2TS U4718 ( .A(n2017), .B(n2016), .Y(n8660) );
NAND2X2TS U4719 ( .A(n2021), .B(n2020), .Y(n8625) );
OAI22X1TS U4720 ( .A0(n2033), .A1(n2032), .B0(n2031), .B1(n2030), .Y(n2062)
);
OAI22X1TS U4721 ( .A0(n4289), .A1(n2035), .B0(n2452), .B1(n2034), .Y(n2061)
);
OAI22X1TS U4722 ( .A0(n2162), .A1(n2038), .B0(n2037), .B1(n2036), .Y(n2060)
);
CMPR32X2TS U4723 ( .A(n2042), .B(n2041), .C(n2040), .CO(n2027), .S(n2070) );
CMPR32X2TS U4724 ( .A(n2062), .B(n2061), .C(n2060), .CO(n2071), .S(n2083) );
CMPR32X2TS U4725 ( .A(n2065), .B(n2064), .C(n2063), .CO(n2082), .S(n2079) );
CMPR32X2TS U4726 ( .A(n2068), .B(n2067), .C(n2066), .CO(n2081), .S(n2089) );
CMPR32X2TS U4727 ( .A(n2071), .B(n2070), .C(n2069), .CO(n2055), .S(n2072) );
CMPR32X2TS U4728 ( .A(n2077), .B(n2076), .C(n2075), .CO(n2069), .S(n2086) );
CMPR32X2TS U4729 ( .A(n2080), .B(n2079), .C(n2078), .CO(n2085), .S(n2087) );
CMPR32X2TS U4730 ( .A(n2083), .B(n2082), .C(n2081), .CO(n2073), .S(n2084) );
CMPR32X2TS U4731 ( .A(n2089), .B(n2088), .C(n2087), .CO(n2090), .S(n2021) );
NOR2X2TS U4732 ( .A(n2091), .B(n2090), .Y(n8631) );
NOR2X4TS U4733 ( .A(n8633), .B(n8631), .Y(n8692) );
NAND2X2TS U4734 ( .A(n2091), .B(n2090), .Y(n8653) );
OAI21X4TS U4735 ( .A0(n8633), .A1(n8653), .B0(n8634), .Y(n8694) );
OAI21X4TS U4736 ( .A0(n8701), .A1(n8695), .B0(n8702), .Y(n2098) );
NAND2X2TS U4737 ( .A(n2105), .B(n2104), .Y(n8688) );
INVX2TS U4738 ( .A(n8688), .Y(n8720) );
INVX2TS U4739 ( .A(n8726), .Y(n2108) );
AND2X8TS U4740 ( .A(n2110), .B(n2109), .Y(n8677) );
XNOR2X1TS U4741 ( .A(n2383), .B(n1624), .Y(n2153) );
OAI22X1TS U4742 ( .A0(n4682), .A1(n2111), .B0(n807), .B1(n2153), .Y(n2165)
);
XNOR2X1TS U4743 ( .A(n677), .B(n3992), .Y(n2152) );
XNOR2X1TS U4744 ( .A(n3691), .B(n3074), .Y(n2154) );
OAI22X1TS U4745 ( .A0(n718), .A1(n2113), .B0(n3031), .B1(n2154), .Y(n2163)
);
CMPR32X2TS U4746 ( .A(n2116), .B(n2115), .C(n2114), .CO(n2143), .S(n2179) );
CMPR32X2TS U4747 ( .A(n2119), .B(n2118), .C(n2117), .CO(n2142), .S(n2131) );
OAI22X1TS U4748 ( .A0(n2400), .A1(n2120), .B0(n3071), .B1(n2136), .Y(n2147)
);
OAI22X1TS U4749 ( .A0(n2149), .A1(n5955), .B0(n2121), .B1(n625), .Y(n2146)
);
XNOR2X1TS U4750 ( .A(n8211), .B(n3207), .Y(n2151) );
OAI22X1TS U4751 ( .A0(n3069), .A1(n2122), .B0(n2150), .B1(n2151), .Y(n2145)
);
OAI22X1TS U4752 ( .A0(n2444), .A1(n2123), .B0(n2270), .B1(n2158), .Y(n2141)
);
XNOR2X1TS U4753 ( .A(n3290), .B(n5890), .Y(n2124) );
XNOR2X1TS U4754 ( .A(n2296), .B(n8804), .Y(n2148) );
OAI22X1TS U4755 ( .A0(n2149), .A1(n2124), .B0(n2148), .B1(n625), .Y(n2140)
);
XNOR2X1TS U4756 ( .A(n2929), .B(n3105), .Y(n2161) );
OAI22X1TS U4757 ( .A0(n2039), .A1(n2125), .B0(n3051), .B1(n2161), .Y(n2139)
);
XNOR2X1TS U4758 ( .A(n3102), .B(n2132), .Y(n2138) );
OAI22X1TS U4759 ( .A0(n2281), .A1(n2133), .B0(n2868), .B1(n2138), .Y(n2169)
);
XNOR2X1TS U4760 ( .A(n3203), .B(n5745), .Y(n2160) );
OAI22X1TS U4761 ( .A0(n3596), .A1(n2135), .B0(n2160), .B1(n2134), .Y(n2168)
);
BUFX4TS U4762 ( .A(n634), .Y(n6428) );
NOR2BX1TS U4763 ( .AN(n8590), .B(n6428), .Y(n2199) );
XNOR2X1TS U4764 ( .A(n3102), .B(n2137), .Y(n2209) );
OAI22X1TS U4765 ( .A0(n2281), .A1(n2138), .B0(n2868), .B1(n2209), .Y(n2197)
);
CMPR32X2TS U4766 ( .A(n2144), .B(n2143), .C(n2142), .CO(n2235), .S(n2190) );
XNOR2X1TS U4767 ( .A(n5567), .B(n2247), .Y(n2204) );
OAI22X1TS U4768 ( .A0(n2149), .A1(n2148), .B0(n744), .B1(n2204), .Y(n2217)
);
XNOR2X1TS U4769 ( .A(n8211), .B(n762), .Y(n2211) );
OAI22X1TS U4770 ( .A0(n4443), .A1(n2151), .B0(n2150), .B1(n2211), .Y(n2216)
);
XNOR2X1TS U4771 ( .A(n678), .B(n750), .Y(n2205) );
OAI22X1TS U4772 ( .A0(n3793), .A1(n2152), .B0(n759), .B1(n2205), .Y(n2215)
);
XNOR2X1TS U4773 ( .A(n811), .B(n713), .Y(n2203) );
OAI22X1TS U4774 ( .A0(n2450), .A1(n2153), .B0(n2448), .B1(n2203), .Y(n2214)
);
XNOR2X1TS U4775 ( .A(n3691), .B(n2675), .Y(n2228) );
OAI22X1TS U4776 ( .A0(n717), .A1(n2154), .B0(n3031), .B1(n2228), .Y(n2213)
);
XNOR2X1TS U4777 ( .A(n799), .B(n746), .Y(n2166) );
XNOR2X1TS U4778 ( .A(n799), .B(n696), .Y(n2227) );
OAI22X1TS U4779 ( .A0(n4289), .A1(n2166), .B0(n2704), .B1(n2227), .Y(n2212)
);
CMPR32X2TS U4780 ( .A(n2157), .B(n2156), .C(n2155), .CO(n2220), .S(n2189) );
XNOR2X1TS U4781 ( .A(n764), .B(n3159), .Y(n2229) );
OAI22X1TS U4782 ( .A0(n2444), .A1(n2158), .B0(n2270), .B1(n2229), .Y(n2202)
);
XNOR2X1TS U4783 ( .A(n8794), .B(n3774), .Y(n2230) );
OAI22X1TS U4784 ( .A0(n3837), .A1(n2160), .B0(n2230), .B1(n906), .Y(n2201)
);
XNOR2X1TS U4785 ( .A(n2929), .B(n3590), .Y(n2226) );
OAI22X1TS U4786 ( .A0(n2039), .A1(n2161), .B0(n3051), .B1(n2226), .Y(n2200)
);
OAI22X1TS U4787 ( .A0(n4289), .A1(n2167), .B0(n2704), .B1(n2166), .Y(n2175)
);
CMPR32X2TS U4788 ( .A(n2175), .B(n2174), .C(n2173), .CO(n2221), .S(n2187) );
CMPR32X2TS U4789 ( .A(n2181), .B(n2180), .C(n2179), .CO(n2185), .S(n2183) );
CMPR32X2TS U4790 ( .A(n2187), .B(n2186), .C(n2185), .CO(n2218), .S(n2192) );
OR2X4TS U4791 ( .A(n2339), .B(n2338), .Y(n8714) );
XNOR2X1TS U4792 ( .A(n2383), .B(n3044), .Y(n2245) );
OAI22X1TS U4793 ( .A0(n2450), .A1(n2203), .B0(n2448), .B1(n2245), .Y(n2255)
);
XNOR2X1TS U4794 ( .A(n5567), .B(n2259), .Y(n2243) );
OAI22X1TS U4795 ( .A0(n5956), .A1(n2204), .B0(n744), .B1(n2243), .Y(n2254)
);
XNOR2X1TS U4796 ( .A(n677), .B(n3074), .Y(n2249) );
OAI22X1TS U4797 ( .A0(n4436), .A1(n2205), .B0(n760), .B1(n2249), .Y(n2253)
);
CMPR32X2TS U4798 ( .A(n2208), .B(n2207), .C(n2206), .CO(n2288), .S(n2234) );
XNOR2X1TS U4799 ( .A(n2258), .B(n627), .Y(n2280) );
OAI22X1TS U4800 ( .A0(n2281), .A1(n2209), .B0(n2868), .B1(n2280), .Y(n2252)
);
NAND2BX1TS U4801 ( .AN(n3067), .B(n5132), .Y(n2210) );
XNOR2X1TS U4802 ( .A(n3149), .B(n3105), .Y(n2244) );
OAI22X1TS U4803 ( .A0(n3069), .A1(n2211), .B0(n3175), .B1(n2244), .Y(n2250)
);
CMPR32X2TS U4804 ( .A(n2214), .B(n2213), .C(n2212), .CO(n2321), .S(n2206) );
CMPR32X2TS U4805 ( .A(n2223), .B(n2222), .C(n2221), .CO(n2328), .S(n2219) );
XNOR2X1TS U4806 ( .A(n767), .B(n3992), .Y(n2283) );
OAI22X1TS U4807 ( .A0(n2400), .A1(n2224), .B0(n3228), .B1(n2283), .Y(n2307)
);
XNOR2X1TS U4808 ( .A(n3642), .B(n5132), .Y(n2225) );
XNOR2X1TS U4809 ( .A(n2296), .B(n4415), .Y(n2248) );
OAI22X1TS U4810 ( .A0(n5305), .A1(n2225), .B0(n2248), .B1(n6428), .Y(n2306)
);
XNOR2X1TS U4811 ( .A(n2929), .B(n5745), .Y(n2274) );
OAI22X1TS U4812 ( .A0(n2039), .A1(n2226), .B0(n3051), .B1(n2274), .Y(n2305)
);
XNOR2X1TS U4813 ( .A(n798), .B(n4882), .Y(n2246) );
OAI22X1TS U4814 ( .A0(n3130), .A1(n2227), .B0(n2704), .B1(n2246), .Y(n2313)
);
XNOR2X1TS U4815 ( .A(n3691), .B(n2262), .Y(n2276) );
OAI22X1TS U4816 ( .A0(n718), .A1(n2228), .B0(n3031), .B1(n2276), .Y(n2312)
);
XNOR2X1TS U4817 ( .A(n764), .B(n3207), .Y(n2271) );
OAI22X1TS U4818 ( .A0(n2444), .A1(n2229), .B0(n4608), .B1(n2271), .Y(n2278)
);
XNOR2X1TS U4819 ( .A(n8794), .B(n3877), .Y(n2272) );
OAI22X1TS U4820 ( .A0(n3837), .A1(n2230), .B0(n2272), .B1(n906), .Y(n2277)
);
CMPR32X2TS U4821 ( .A(n2233), .B(n2232), .C(n2231), .CO(n2266), .S(n2236) );
CMPR32X2TS U4822 ( .A(n2236), .B(n2235), .C(n2234), .CO(n2326), .S(n2238) );
NOR2X4TS U4823 ( .A(n8738), .B(n8743), .Y(n8731) );
NAND2BX1TS U4824 ( .AN(n3605), .B(n695), .Y(n2240) );
OAI22X1TS U4825 ( .A0(n687), .A1(n6370), .B0(n2240), .B1(n3928), .Y(n2492)
);
XNOR2X1TS U4826 ( .A(n5567), .B(n2376), .Y(n2242) );
XNOR2X1TS U4827 ( .A(n5567), .B(n2241), .Y(n2459) );
XNOR2X1TS U4828 ( .A(n3691), .B(n2388), .Y(n2275) );
XNOR2X1TS U4829 ( .A(n2386), .B(n746), .Y(n2425) );
OAI22X1TS U4830 ( .A0(n717), .A1(n2275), .B0(n3031), .B1(n2425), .Y(n2490)
);
XNOR2X1TS U4831 ( .A(n3149), .B(n3590), .Y(n2264) );
XNOR2X1TS U4832 ( .A(n811), .B(n3159), .Y(n2261) );
OAI22X1TS U4833 ( .A0(n2450), .A1(n2245), .B0(n2448), .B1(n2261), .Y(n2256)
);
XNOR2X1TS U4834 ( .A(n798), .B(n2926), .Y(n2265) );
OAI22X1TS U4835 ( .A0(n2454), .A1(n2246), .B0(n2452), .B1(n2265), .Y(n2310)
);
XNOR2X1TS U4836 ( .A(n677), .B(n2675), .Y(n2263) );
OAI22X1TS U4837 ( .A0(n809), .A1(n2249), .B0(n759), .B1(n2263), .Y(n2308) );
XNOR2X1TS U4838 ( .A(n2258), .B(n1624), .Y(n2415) );
OAI22X1TS U4839 ( .A0(n3259), .A1(n2279), .B0(n2868), .B1(n2415), .Y(n2501)
);
XNOR2X1TS U4840 ( .A(n4415), .B(n2259), .Y(n2456) );
OAI22X1TS U4841 ( .A0(n6055), .A1(n2260), .B0(n826), .B1(n2456), .Y(n2500)
);
XNOR2X1TS U4842 ( .A(n2929), .B(n3774), .Y(n2273) );
XNOR2X1TS U4843 ( .A(n2929), .B(n3877), .Y(n2420) );
OAI22X1TS U4844 ( .A0(n4032), .A1(n2273), .B0(n3051), .B1(n2420), .Y(n2499)
);
XNOR2X1TS U4845 ( .A(n636), .B(n750), .Y(n2282) );
XNOR2X1TS U4846 ( .A(n767), .B(n3074), .Y(n2399) );
OAI22X1TS U4847 ( .A0(n2400), .A1(n2282), .B0(n3228), .B1(n2399), .Y(n2480)
);
XNOR2X1TS U4848 ( .A(n4218), .B(n3207), .Y(n2449) );
OAI22X1TS U4849 ( .A0(n2450), .A1(n2261), .B0(n2448), .B1(n2449), .Y(n2479)
);
XNOR2X1TS U4850 ( .A(n677), .B(n2262), .Y(n2427) );
OAI22X1TS U4851 ( .A0(n3793), .A1(n2263), .B0(n759), .B1(n2427), .Y(n2478)
);
XNOR2X1TS U4852 ( .A(n765), .B(n763), .Y(n2269) );
XNOR2X1TS U4853 ( .A(n764), .B(n3105), .Y(n2443) );
OAI22X1TS U4854 ( .A0(n2444), .A1(n2269), .B0(n3231), .B1(n2443), .Y(n2483)
);
OAI22X1TS U4855 ( .A0(n3227), .A1(n2264), .B0(n3175), .B1(n2446), .Y(n2482)
);
XNOR2X1TS U4856 ( .A(n799), .B(n3044), .Y(n2453) );
OAI22X1TS U4857 ( .A0(n2454), .A1(n2265), .B0(n2452), .B1(n2453), .Y(n2481)
);
CMPR32X2TS U4858 ( .A(n2268), .B(n2267), .C(n2266), .CO(n2331), .S(n2327) );
OAI22X1TS U4859 ( .A0(n2444), .A1(n2271), .B0(n2270), .B1(n2269), .Y(n2304)
);
XNOR2X1TS U4860 ( .A(n8794), .B(n8233), .Y(n2298) );
OAI22X1TS U4861 ( .A0(n3837), .A1(n2272), .B0(n2298), .B1(n906), .Y(n2303)
);
OAI22X1TS U4862 ( .A0(n3164), .A1(n2274), .B0(n3051), .B1(n2273), .Y(n2302)
);
OAI22X1TS U4863 ( .A0(n718), .A1(n2276), .B0(n3031), .B1(n2275), .Y(n2295)
);
ADDHX1TS U4864 ( .A(n2278), .B(n2277), .CO(n2294), .S(n2311) );
NOR2BX1TS U4865 ( .AN(n8590), .B(n3928), .Y(n2301) );
OAI22X1TS U4866 ( .A0(n2400), .A1(n2283), .B0(n3071), .B1(n2282), .Y(n2299)
);
CMPR32X2TS U4867 ( .A(n2286), .B(n2285), .C(n2284), .CO(n2290), .S(n2289) );
XNOR2X1TS U4868 ( .A(n3290), .B(n695), .Y(n2297) );
XNOR2X1TS U4869 ( .A(n2797), .B(n4090), .Y(n2418) );
CMPR32X2TS U4870 ( .A(n2307), .B(n2306), .C(n2305), .CO(n2319), .S(n2268) );
CMPR32X2TS U4871 ( .A(n2310), .B(n2309), .C(n2308), .CO(n2538), .S(n2318) );
CMPR32X2TS U4872 ( .A(n2313), .B(n2312), .C(n2311), .CO(n2317), .S(n2267) );
CMPR32X2TS U4873 ( .A(n2319), .B(n2318), .C(n2317), .CO(n2559), .S(n2324) );
CMPR32X2TS U4874 ( .A(n2322), .B(n2321), .C(n2320), .CO(n2323), .S(n2287) );
CMPR32X2TS U4875 ( .A(n2325), .B(n2324), .C(n2323), .CO(n2586), .S(n2334) );
NOR2X6TS U4876 ( .A(n2346), .B(n2345), .Y(n8732) );
NAND2X4TS U4877 ( .A(n8731), .B(n2350), .Y(n2352) );
AOI21X4TS U4878 ( .A0(n8708), .A1(n8707), .B0(n2342), .Y(n8739) );
NAND2X2TS U4879 ( .A(n2344), .B(n2343), .Y(n8744) );
NAND2X2TS U4880 ( .A(n2348), .B(n2347), .Y(n8683) );
OAI21X4TS U4881 ( .A0(n8682), .A1(n8733), .B0(n8683), .Y(n2349) );
AOI21X4TS U4882 ( .A0(n8678), .A1(n2350), .B0(n2349), .Y(n2351) );
OAI21X4TS U4883 ( .A0(n8677), .A1(n2352), .B0(n2351), .Y(n7847) );
XNOR2X1TS U4884 ( .A(n1944), .B(n3774), .Y(n2445) );
OAI22X1TS U4885 ( .A0(n3227), .A1(n2445), .B0(n3175), .B1(n2356), .Y(n2441)
);
XNOR2X1TS U4886 ( .A(n3642), .B(n5489), .Y(n2358) );
XNOR2X1TS U4887 ( .A(n768), .B(n2675), .Y(n2398) );
OAI22X1TS U4888 ( .A0(n2400), .A1(n2398), .B0(n3228), .B1(n2359), .Y(n2439)
);
CMPR32X2TS U4889 ( .A(n2368), .B(n2367), .C(n2366), .CO(n1674), .S(n2437) );
CMPR32X2TS U4890 ( .A(n2371), .B(n2370), .C(n2369), .CO(n2412), .S(n2436) );
XNOR2X1TS U4891 ( .A(n741), .B(n713), .Y(n2413) );
OAI22X1TS U4892 ( .A0(n2416), .A1(n2413), .B0(n2414), .B1(n2375), .Y(n2462)
);
XNOR2X1TS U4893 ( .A(n5132), .B(n2376), .Y(n2455) );
OAI22X1TS U4894 ( .A0(n6429), .A1(n2455), .B0(n3863), .B1(n2377), .Y(n2461)
);
XNOR2X1TS U4895 ( .A(n3103), .B(n750), .Y(n2458) );
OAI22X1TS U4896 ( .A0(n4581), .A1(n2458), .B0(n625), .B1(n2379), .Y(n2460)
);
CMPR32X2TS U4897 ( .A(n2382), .B(n2381), .C(n2380), .CO(n1673), .S(n2434) );
XNOR2X1TS U4898 ( .A(n2383), .B(n763), .Y(n2447) );
OAI22X1TS U4899 ( .A0(n2450), .A1(n2447), .B0(n3685), .B1(n2384), .Y(n2423)
);
XNOR2X1TS U4900 ( .A(n2386), .B(n2385), .Y(n2424) );
OAI22X1TS U4901 ( .A0(n3540), .A1(n2424), .B0(n3031), .B1(n2387), .Y(n2422)
);
XNOR2X1TS U4902 ( .A(n677), .B(n2388), .Y(n2426) );
OAI22X1TS U4903 ( .A0(n5667), .A1(n2426), .B0(n760), .B1(n2389), .Y(n2421)
);
CMPR32X2TS U4904 ( .A(n2392), .B(n2391), .C(n2390), .CO(n2368), .S(n2471) );
OAI22X1TS U4905 ( .A0(n2454), .A1(n2451), .B0(n2452), .B1(n2393), .Y(n2468)
);
NOR2BX1TS U4906 ( .AN(n8590), .B(n6456), .Y(n2489) );
OAI22X2TS U4907 ( .A0(n704), .A1(n2397), .B0(n3680), .B1(n2396), .Y(n2488)
);
OAI22X1TS U4908 ( .A0(n2400), .A1(n2399), .B0(n3228), .B1(n2398), .Y(n2487)
);
CMPR32X2TS U4909 ( .A(n2406), .B(n2405), .C(n2404), .CO(n2411), .S(n2475) );
CMPR32X2TS U4910 ( .A(n2412), .B(n2411), .C(n2410), .CO(n2407), .S(n2522) );
OAI22X1TS U4911 ( .A0(n2416), .A1(n2415), .B0(n2414), .B1(n2413), .Y(n2504)
);
OAI22X1TS U4912 ( .A0(n3211), .A1(n2418), .B0(n2417), .B1(n906), .Y(n2503)
);
OAI22X1TS U4913 ( .A0(n717), .A1(n2425), .B0(n3031), .B1(n2424), .Y(n2486)
);
OAI22X1TS U4914 ( .A0(n3793), .A1(n2427), .B0(n759), .B1(n2426), .Y(n2485)
);
CMPR32X2TS U4915 ( .A(n2432), .B(n2431), .C(n2430), .CO(n2438), .S(n2515) );
CMPR32X2TS U4916 ( .A(n2435), .B(n2434), .C(n2433), .CO(n2477), .S(n2514) );
CMPR32X2TS U4917 ( .A(n2441), .B(n2440), .C(n2439), .CO(n2432), .S(n2510) );
OAI22X1TS U4918 ( .A0(n2444), .A1(n2443), .B0(n3231), .B1(n2442), .Y(n2507)
);
OAI22X1TS U4919 ( .A0(n2450), .A1(n2449), .B0(n2448), .B1(n2447), .Y(n2505)
);
OAI22X1TS U4920 ( .A0(n2454), .A1(n2453), .B0(n2452), .B1(n2451), .Y(n2495)
);
OAI22X1TS U4921 ( .A0(n5305), .A1(n2456), .B0(n827), .B1(n2455), .Y(n2494)
);
OAI22X1TS U4922 ( .A0(n5956), .A1(n2459), .B0(n744), .B1(n2458), .Y(n2493)
);
CMPR32X2TS U4923 ( .A(n2462), .B(n2461), .C(n2460), .CO(n2435), .S(n2513) );
CMPR32X2TS U4924 ( .A(n2465), .B(n2464), .C(n2463), .CO(n2401), .S(n2512) );
CMPR32X2TS U4925 ( .A(n2471), .B(n2470), .C(n2469), .CO(n2476), .S(n2529) );
ADDFX2TS U4926 ( .A(n2486), .B(n2485), .CI(n2484), .CO(n2496), .S(n2550) );
ADDFHX2TS U4927 ( .A(n2489), .B(n2488), .CI(n2487), .CO(n2466), .S(n2543) );
ADDFX2TS U4928 ( .A(n2495), .B(n2494), .CI(n2493), .CO(n2508), .S(n2541) );
CMPR32X2TS U4929 ( .A(n2498), .B(n2497), .C(n2496), .CO(n2516), .S(n2532) );
CMPR32X2TS U4930 ( .A(n2501), .B(n2500), .C(n2499), .CO(n2549), .S(n2546) );
CMPR32X2TS U4931 ( .A(n2507), .B(n2506), .C(n2505), .CO(n2509), .S(n2547) );
CMPR32X2TS U4932 ( .A(n2510), .B(n2509), .C(n2508), .CO(n2531), .S(n2557) );
NOR2X4TS U4933 ( .A(n2605), .B(n2606), .Y(n7848) );
OR2X4TS U4934 ( .A(n2610), .B(n2609), .Y(n7962) );
CMPR32X2TS U4935 ( .A(n2531), .B(n2530), .C(n2529), .CO(n2517), .S(n2576) );
ADDFX2TS U4936 ( .A(n2534), .B(n2533), .CI(n2532), .CO(n2555), .S(n2570) );
CMPR32X2TS U4937 ( .A(n2537), .B(n2536), .C(n2535), .CO(n2567), .S(n2560) );
CMPR32X2TS U4938 ( .A(n2543), .B(n2542), .C(n2541), .CO(n2533), .S(n2565) );
CMPR32X2TS U4939 ( .A(n2546), .B(n2545), .C(n2544), .CO(n2582), .S(n2562) );
CMPR32X2TS U4940 ( .A(n2549), .B(n2548), .C(n2547), .CO(n2558), .S(n2581) );
CMPR32X2TS U4941 ( .A(n2552), .B(n2551), .C(n2550), .CO(n2534), .S(n2580) );
CMPR32X2TS U4942 ( .A(n2558), .B(n2557), .C(n2556), .CO(n2554), .S(n2579) );
CMPR32X2TS U4943 ( .A(n2567), .B(n2566), .C(n2565), .CO(n2569), .S(n2583) );
NOR2X6TS U4944 ( .A(n2600), .B(n2599), .Y(n7966) );
NOR2X6TS U4945 ( .A(n7966), .B(n7971), .Y(n2604) );
CMPR32X2TS U4946 ( .A(n2582), .B(n2581), .C(n2580), .CO(n2568), .S(n2591) );
ADDFHX2TS U4947 ( .A(n2585), .B(n2584), .CI(n2583), .CO(n2578), .S(n2590) );
ADDFHX4TS U4948 ( .A(n2594), .B(n2593), .CI(n2592), .CO(n2595), .S(n2348) );
NOR2X4TS U4949 ( .A(n2596), .B(n2595), .Y(n7948) );
NOR2X4TS U4950 ( .A(n7949), .B(n7948), .Y(n7983) );
NOR2X4TS U4951 ( .A(n2613), .B(n7977), .Y(n2615) );
NAND2X4TS U4952 ( .A(n2596), .B(n2595), .Y(n7947) );
OAI21X4TS U4953 ( .A0(n7949), .A1(n7947), .B0(n7950), .Y(n7967) );
NAND2X4TS U4954 ( .A(n2600), .B(n2599), .Y(n7987) );
OAI21X4TS U4955 ( .A0(n7971), .A1(n7987), .B0(n7972), .Y(n2603) );
AOI21X4TS U4956 ( .A0(n2604), .A1(n7967), .B0(n2603), .Y(n7849) );
OAI21X4TS U4957 ( .A0(n7853), .A1(n7979), .B0(n7854), .Y(n7956) );
NAND2X2TS U4958 ( .A(n2610), .B(n2609), .Y(n7961) );
AOI21X4TS U4959 ( .A0(n7956), .A1(n7962), .B0(n2611), .Y(n2612) );
OAI21X4TS U4960 ( .A0(n7849), .A1(n2613), .B0(n2612), .Y(n2614) );
AOI21X4TS U4961 ( .A0(n7847), .A1(n2615), .B0(n2614), .Y(n7859) );
NAND2X2TS U4962 ( .A(n2619), .B(n2618), .Y(n8002) );
NAND2X4TS U4963 ( .A(n2622), .B(n2621), .Y(n8010) );
NAND2X2TS U4964 ( .A(n2624), .B(n2623), .Y(n7995) );
AOI2BB1X4TS U4965 ( .A0N(n2626), .A1N(n8010), .B0(n2625), .Y(n2627) );
OAI21X4TS U4966 ( .A0(n8007), .A1(n2628), .B0(n2627), .Y(n7861) );
AOI21X4TS U4967 ( .A0(n2634), .A1(n7871), .B0(n2633), .Y(n7876) );
OAI21X4TS U4968 ( .A0(n2641), .A1(n7876), .B0(n2640), .Y(n2642) );
AOI21X4TS U4969 ( .A0(n7861), .A1(n2643), .B0(n2642), .Y(n2644) );
OAI21X4TS U4970 ( .A0(n2645), .A1(n7859), .B0(n2644), .Y(n7897) );
CMPR32X2TS U4971 ( .A(n2648), .B(n2647), .C(n2646), .CO(n2757), .S(n2678) );
XNOR2X1TS U4972 ( .A(n4607), .B(n5203), .Y(n2782) );
OAI22X1TS U4973 ( .A0(n2783), .A1(n2655), .B0(n3116), .B1(n2782), .Y(n2692)
);
XNOR2X1TS U4974 ( .A(n6222), .B(n4372), .Y(n2676) );
OAI22X1TS U4975 ( .A0(n5724), .A1(n2656), .B0(n5228), .B1(n2676), .Y(n2691)
);
XNOR2X1TS U4976 ( .A(n811), .B(n4888), .Y(n2784) );
OAI22X1TS U4977 ( .A0(n4682), .A1(n2657), .B0(n808), .B1(n2784), .Y(n2690)
);
XNOR2X1TS U4978 ( .A(n678), .B(n3270), .Y(n2658) );
OAI22X1TS U4979 ( .A0(n1710), .A1(n2658), .B0(n4434), .B1(n2880), .Y(n2857)
);
XNOR2X1TS U4980 ( .A(n819), .B(n3044), .Y(n2672) );
XNOR2X1TS U4981 ( .A(n8224), .B(n3159), .Y(n2889) );
XNOR2X1TS U4982 ( .A(n6054), .B(n2912), .Y(n2891) );
OAI22X1TS U4983 ( .A0(n5305), .A1(n2670), .B0(n827), .B1(n2891), .Y(n2855)
);
OAI22X1TS U4984 ( .A0(n809), .A1(n2659), .B0(n4434), .B1(n2658), .Y(n2695)
);
XNOR2X1TS U4985 ( .A(n4848), .B(n3065), .Y(n2716) );
OAI22X1TS U4986 ( .A0(n5135), .A1(n2660), .B0(n4919), .B1(n2716), .Y(n2694)
);
XNOR2X1TS U4987 ( .A(n703), .B(n2866), .Y(n2796) );
XNOR2X1TS U4988 ( .A(n1948), .B(n5708), .Y(n2798) );
OAI22X1TS U4989 ( .A0(n2663), .A1(n2662), .B0(n2798), .B1(n2961), .Y(n2717)
);
OAI22X1TS U4990 ( .A0(n2720), .A1(n2664), .B0(n4685), .B1(n2719), .Y(n2689)
);
XOR2X4TS U4991 ( .A(n6690), .B(Op_MX[40]), .Y(n2665) );
XNOR2X1TS U4992 ( .A(n5331), .B(n8236), .Y(n2777) );
OAI22X1TS U4993 ( .A0(n3577), .A1(n2667), .B0(n5224), .B1(n2777), .Y(n2687)
);
OAI22X1TS U4994 ( .A0(n3114), .A1(n2673), .B0(n3866), .B1(n2672), .Y(n2728)
);
INVX4TS U4995 ( .A(n6126), .Y(n3830) );
XNOR2X1TS U4996 ( .A(n3691), .B(n3830), .Y(n2871) );
OAI22X1TS U4997 ( .A0(n3540), .A1(n2674), .B0(n3031), .B1(n2871), .Y(n2854)
);
XNOR2X1TS U4998 ( .A(n6662), .B(n4405), .Y(n2893) );
OAI22X1TS U4999 ( .A0(n3127), .A1(n2676), .B0(n5228), .B1(n2893), .Y(n2853)
);
XNOR2X1TS U5000 ( .A(n779), .B(n4553), .Y(n2886) );
OAI22X1TS U5001 ( .A0(n714), .A1(n2681), .B0(n4907), .B1(n2886), .Y(n2852)
);
OAI22X1TS U5002 ( .A0(n3259), .A1(n2680), .B0(n3840), .B1(n2776), .Y(n2781)
);
OAI22X1TS U5003 ( .A0(n4115), .A1(n2682), .B0(n4907), .B1(n2681), .Y(n2780)
);
OAI22X1TS U5004 ( .A0(n6381), .A1(n2683), .B0(n4487), .B1(n2794), .Y(n2779)
);
CMPR32X2TS U5005 ( .A(n2692), .B(n2691), .C(n2690), .CO(n2845), .S(n2712) );
CMPR32X2TS U5006 ( .A(n2695), .B(n2694), .C(n2693), .CO(n2843), .S(n2711) );
CMPR32X2TS U5007 ( .A(n2701), .B(n2700), .C(n2699), .CO(n2754), .S(n2744) );
XNOR2X1TS U5008 ( .A(n3594), .B(n2702), .Y(n2793) );
OAI22X1TS U5009 ( .A0(n1663), .A1(n2703), .B0(n3680), .B1(n2793), .Y(n2715)
);
XNOR2X1TS U5010 ( .A(n4412), .B(n3986), .Y(n2778) );
BUFX4TS U5011 ( .A(n3069), .Y(n4443) );
XNOR2X1TS U5012 ( .A(n801), .B(n5440), .Y(n2795) );
OAI22X1TS U5013 ( .A0(n4443), .A1(n2706), .B0(n2921), .B1(n2795), .Y(n2713)
);
XNOR2X1TS U5014 ( .A(n824), .B(n4671), .Y(n2721) );
OAI22X1TS U5015 ( .A0(n4835), .A1(n2707), .B0(n4661), .B1(n2721), .Y(n2792)
);
XNOR2X1TS U5016 ( .A(n3723), .B(n8221), .Y(n2708) );
OAI22X1TS U5017 ( .A0(n6482), .A1(n2708), .B0(n2786), .B1(n2979), .Y(n2791)
);
XNOR2X1TS U5018 ( .A(n2929), .B(n6775), .Y(n2800) );
OAI22X1TS U5019 ( .A0(n810), .A1(n2709), .B0(n2799), .B1(n2800), .Y(n2790)
);
CMPR32X2TS U5020 ( .A(n2715), .B(n2714), .C(n2713), .CO(n2830), .S(n2753) );
XNOR2X1TS U5021 ( .A(n4848), .B(n3147), .Y(n2895) );
OAI22X1TS U5022 ( .A0(n5135), .A1(n2716), .B0(n4919), .B1(n2895), .Y(n2842)
);
ADDHX1TS U5023 ( .A(n2718), .B(n2717), .CO(n2841), .S(n2693) );
XNOR2X4TS U5024 ( .A(Op_MX[41]), .B(Op_MX[42]), .Y(n2943) );
NOR2BX1TS U5025 ( .AN(n3605), .B(n721), .Y(n2833) );
OAI22X2TS U5026 ( .A0(n2720), .A1(n2719), .B0(n4685), .B1(n2879), .Y(n2832)
);
XNOR2X1TS U5027 ( .A(n825), .B(n3223), .Y(n2894) );
OAI22X1TS U5028 ( .A0(n4835), .A1(n2721), .B0(n4661), .B1(n2894), .Y(n2831)
);
CMPR32X2TS U5029 ( .A(n2739), .B(n2738), .C(n2737), .CO(n2828), .S(n2772) );
CMPR32X2TS U5030 ( .A(n2745), .B(n2744), .C(n2743), .CO(n2770), .S(n2761) );
ADDFX2TS U5031 ( .A(n2751), .B(n2750), .CI(n2749), .CO(n2775), .S(n2760) );
XNOR2X1TS U5032 ( .A(n3102), .B(n4504), .Y(n2869) );
OAI22X1TS U5033 ( .A0(n3259), .A1(n2776), .B0(n3840), .B1(n2869), .Y(n2877)
);
XNOR2X1TS U5034 ( .A(n5331), .B(n3971), .Y(n2867) );
OAI22X1TS U5035 ( .A0(n3577), .A1(n2777), .B0(n5224), .B1(n2867), .Y(n2876)
);
XNOR2X1TS U5036 ( .A(n3786), .B(n4841), .Y(n2881) );
OAI22X1TS U5037 ( .A0(n3130), .A1(n2778), .B0(n3537), .B1(n2881), .Y(n2875)
);
CMPR32X2TS U5038 ( .A(n2781), .B(n2780), .C(n2779), .CO(n2826), .S(n2789) );
XNOR2X1TS U5039 ( .A(n8208), .B(n5348), .Y(n2865) );
OAI22X1TS U5040 ( .A0(n2783), .A1(n2782), .B0(n3116), .B1(n2865), .Y(n2851)
);
OAI22X1TS U5041 ( .A0(n4682), .A1(n2784), .B0(n808), .B1(n2864), .Y(n2850)
);
XNOR2X1TS U5042 ( .A(n6100), .B(n3833), .Y(n2882) );
OAI22X1TS U5043 ( .A0(n813), .A1(n2786), .B0(n5414), .B1(n2882), .Y(n2849)
);
XNOR2X1TS U5044 ( .A(n695), .B(Op_MY[18]), .Y(n2888) );
OAI22X1TS U5045 ( .A0(n5522), .A1(n2793), .B0(n3680), .B1(n2888), .Y(n2863)
);
XNOR2X1TS U5046 ( .A(n749), .B(n2926), .Y(n2896) );
XNOR2X1TS U5047 ( .A(n751), .B(n5526), .Y(n2870) );
OAI22X1TS U5048 ( .A0(n4443), .A1(n2795), .B0(n4442), .B1(n2870), .Y(n2861)
);
XNOR2X1TS U5049 ( .A(n8809), .B(n4208), .Y(n2892) );
OAI22X1TS U5050 ( .A0(n6795), .A1(n2796), .B0(n4892), .B1(n2892), .Y(n2839)
);
XNOR2X1TS U5051 ( .A(n8229), .B(n5783), .Y(n2836) );
OAI22X1TS U5052 ( .A0(n3211), .A1(n2798), .B0(n2836), .B1(n2961), .Y(n2838)
);
OAI22X1TS U5053 ( .A0(n3164), .A1(n2800), .B0(n2799), .B1(n2885), .Y(n2837)
);
ADDFHX4TS U5054 ( .A(n2812), .B(n2811), .CI(n2810), .CO(n3500), .S(n2638) );
NOR2X4TS U5055 ( .A(n3500), .B(n3501), .Y(n8060) );
INVX4TS U5056 ( .A(n8060), .Y(n7898) );
CMPR32X2TS U5057 ( .A(n2824), .B(n2823), .C(n2822), .CO(n3020), .S(n2900) );
CMPR32X2TS U5058 ( .A(n2827), .B(n2826), .C(n2825), .CO(n3081), .S(n2848) );
XOR2X4TS U5059 ( .A(Op_MX[42]), .B(n6296), .Y(n2834) );
NAND2X8TS U5060 ( .A(n2834), .B(n4668), .Y(n6101) );
OAI22X1TS U5061 ( .A0(n4055), .A1(n7011), .B0(n2835), .B1(n720), .Y(n3018)
);
OAI22X1TS U5062 ( .A0(n3211), .A1(n2836), .B0(n2928), .B1(n2961), .Y(n3017)
);
CMPR32X2TS U5063 ( .A(n2842), .B(n2841), .C(n2840), .CO(n2938), .S(n2829) );
CMPR32X2TS U5064 ( .A(n2845), .B(n2844), .C(n2843), .CO(n2937), .S(n2820) );
CMPR32X2TS U5065 ( .A(n2851), .B(n2850), .C(n2849), .CO(n2954), .S(n2825) );
CMPR32X2TS U5066 ( .A(n2860), .B(n2859), .C(n2858), .CO(n3077), .S(n2819) );
OAI22X1TS U5067 ( .A0(n4682), .A1(n2864), .B0(n806), .B1(n3003), .Y(n2997)
);
XNOR2X1TS U5068 ( .A(n4607), .B(n5440), .Y(n2931) );
BUFX6TS U5069 ( .A(n5447), .Y(n5564) );
XNOR2X1TS U5070 ( .A(n5331), .B(n3992), .Y(n2932) );
OAI22X1TS U5071 ( .A0(n3577), .A1(n2867), .B0(n5564), .B1(n2932), .Y(n2995)
);
XNOR2X1TS U5072 ( .A(n3108), .B(n820), .Y(n2916) );
OAI22X1TS U5073 ( .A0(n3259), .A1(n2869), .B0(n2868), .B1(n2916), .Y(n2925)
);
XNOR2X1TS U5074 ( .A(n1944), .B(n6775), .Y(n2922) );
XNOR2X1TS U5075 ( .A(n3691), .B(n3929), .Y(n2949) );
OAI22X1TS U5076 ( .A0(n3540), .A1(n2871), .B0(n4002), .B1(n2949), .Y(n2923)
);
CMPR32X2TS U5077 ( .A(n2874), .B(n2873), .C(n2872), .CO(n2991), .S(n2846) );
XNOR2X1TS U5078 ( .A(n4419), .B(n4882), .Y(n2927) );
OAI22X1TS U5079 ( .A0(n5350), .A1(n2879), .B0(n4685), .B1(n2927), .Y(n3014)
);
XNOR2X1TS U5080 ( .A(n3920), .B(n5413), .Y(n3015) );
OAI22X1TS U5081 ( .A0(n5575), .A1(n2880), .B0(n758), .B1(n3015), .Y(n3013)
);
XNOR2X1TS U5082 ( .A(n8213), .B(n4888), .Y(n3005) );
OAI22X1TS U5083 ( .A0(n3130), .A1(n2881), .B0(n3537), .B1(n3005), .Y(n3012)
);
OAI22X1TS U5084 ( .A0(n3808), .A1(n2882), .B0(n5414), .B1(n2917), .Y(n2948)
);
XNOR2X1TS U5085 ( .A(n3642), .B(n723), .Y(n2883) );
XNOR2X1TS U5086 ( .A(n3724), .B(n6296), .Y(n2944) );
OAI22X1TS U5087 ( .A0(n7013), .A1(n2883), .B0(n2944), .B1(n720), .Y(n2947)
);
XNOR2X1TS U5088 ( .A(n2929), .B(n5708), .Y(n2930) );
OAI22X1TS U5089 ( .A0(n4032), .A1(n2885), .B0(n4030), .B1(n2930), .Y(n2946)
);
OAI22X1TS U5090 ( .A0(n6716), .A1(n2886), .B0(n4907), .B1(n2915), .Y(n2911)
);
XNOR2X1TS U5091 ( .A(n706), .B(n2887), .Y(n2913) );
OAI22X1TS U5092 ( .A0(n5522), .A1(n2888), .B0(n5410), .B1(n2913), .Y(n2910)
);
XNOR2X1TS U5093 ( .A(n819), .B(n3207), .Y(n2951) );
OAI22X1TS U5094 ( .A0(n3114), .A1(n2889), .B0(n3866), .B1(n2951), .Y(n2909)
);
XNOR2X1TS U5095 ( .A(n711), .B(n3065), .Y(n3016) );
XNOR2X1TS U5096 ( .A(n5787), .B(n4406), .Y(n2914) );
OAI22X1TS U5097 ( .A0(n5724), .A1(n2893), .B0(n5228), .B1(n2914), .Y(n2998)
);
XNOR2X1TS U5098 ( .A(n767), .B(n3270), .Y(n2945) );
OAI22X1TS U5099 ( .A0(n4835), .A1(n2894), .B0(n4661), .B1(n2945), .Y(n3011)
);
XNOR2X1TS U5100 ( .A(n4848), .B(n4671), .Y(n2933) );
OAI22X1TS U5101 ( .A0(n5135), .A1(n2895), .B0(n4919), .B1(n2933), .Y(n3010)
);
XNOR2X1TS U5102 ( .A(n748), .B(n3044), .Y(n2950) );
OAI22X1TS U5103 ( .A0(n5944), .A1(n2896), .B0(n4116), .B1(n2950), .Y(n3009)
);
ADDFHX4TS U5104 ( .A(n2905), .B(n2904), .CI(n2903), .CO(n3506), .S(n3503) );
NOR2X8TS U5105 ( .A(n3507), .B(n3506), .Y(n8053) );
CMPR32X2TS U5106 ( .A(n2908), .B(n2907), .C(n2906), .CO(n2994), .S(n3076) );
XNOR2X1TS U5107 ( .A(n705), .B(n2912), .Y(n3066) );
OAI22X1TS U5108 ( .A0(n5522), .A1(n2913), .B0(n5410), .B1(n3066), .Y(n3037)
);
INVX4TS U5109 ( .A(n6744), .Y(n5787) );
XNOR2X1TS U5110 ( .A(n6383), .B(n4553), .Y(n2981) );
OAI22X1TS U5111 ( .A0(n3127), .A1(n2914), .B0(n5228), .B1(n2981), .Y(n3036)
);
INVX6TS U5112 ( .A(n5192), .Y(n4843) );
XNOR2X1TS U5113 ( .A(n779), .B(n4843), .Y(n2959) );
OAI22X1TS U5114 ( .A0(n699), .A1(n2915), .B0(n4907), .B1(n2959), .Y(n3035)
);
XNOR2X1TS U5115 ( .A(n3108), .B(n4841), .Y(n2982) );
OAI22X1TS U5116 ( .A0(n3259), .A1(n2916), .B0(n3840), .B1(n2982), .Y(n3064)
);
INVX2TS U5117 ( .A(n3808), .Y(n2919) );
INVX2TS U5118 ( .A(n2917), .Y(n2918) );
XNOR2X1TS U5119 ( .A(n5503), .B(n3971), .Y(n2980) );
INVX2TS U5120 ( .A(n2920), .Y(n3063) );
XNOR2X1TS U5121 ( .A(n751), .B(n5129), .Y(n3070) );
OAI22X1TS U5122 ( .A0(n4443), .A1(n2922), .B0(n2921), .B1(n3070), .Y(n3062)
);
XNOR2X1TS U5123 ( .A(n8813), .B(n713), .Y(n3045) );
OAI22X1TS U5124 ( .A0(n815), .A1(n2927), .B0(n4295), .B1(n3045), .Y(n2977)
);
XNOR2X1TS U5125 ( .A(n1948), .B(n5986), .Y(n2962) );
OAI22X1TS U5126 ( .A0(n3211), .A1(n2928), .B0(n2962), .B1(n2961), .Y(n2976)
);
XNOR2X1TS U5127 ( .A(n2929), .B(n5783), .Y(n3052) );
OAI22X1TS U5128 ( .A0(n3164), .A1(n2930), .B0(n3051), .B1(n3052), .Y(n2975)
);
XNOR2X1TS U5129 ( .A(n4607), .B(n5526), .Y(n2958) );
OAI22X1TS U5130 ( .A0(n4556), .A1(n2931), .B0(n4608), .B1(n2958), .Y(n2957)
);
XNOR2X1TS U5131 ( .A(n5331), .B(n2378), .Y(n3075) );
OAI22X1TS U5132 ( .A0(n3577), .A1(n2932), .B0(n5224), .B1(n3075), .Y(n2956)
);
XNOR2X1TS U5133 ( .A(n4848), .B(n3223), .Y(n2960) );
OAI22X1TS U5134 ( .A0(n5135), .A1(n2933), .B0(n4919), .B1(n2960), .Y(n2955)
);
CMPR32X2TS U5135 ( .A(n2936), .B(n2935), .C(n2934), .CO(n3084), .S(n2989) );
CMPR32X2TS U5136 ( .A(n2939), .B(n2938), .C(n2937), .CO(n3083), .S(n3079) );
ADDFX2TS U5137 ( .A(n2942), .B(n2941), .CI(n2940), .CO(n2968), .S(n2939) );
XNOR2X4TS U5138 ( .A(Op_MX[44]), .B(Op_MX[43]), .Y(n3046) );
NOR2BX1TS U5139 ( .AN(n3605), .B(n731), .Y(n2965) );
OAI22X1TS U5140 ( .A0(n7013), .A1(n2944), .B0(n7012), .B1(n2978), .Y(n2964)
);
XNOR2X1TS U5141 ( .A(n636), .B(n753), .Y(n3072) );
OAI22X1TS U5142 ( .A0(n4835), .A1(n2945), .B0(n4661), .B1(n3072), .Y(n2963)
);
CMPR32X2TS U5143 ( .A(n2948), .B(n2947), .C(n2946), .CO(n2970), .S(n3006) );
INVX4TS U5144 ( .A(n6237), .Y(n3985) );
OAI22X1TS U5145 ( .A0(n3540), .A1(n2949), .B0(n4002), .B1(n3032), .Y(n3055)
);
XNOR2X1TS U5146 ( .A(n748), .B(n3159), .Y(n2983) );
OAI22X1TS U5147 ( .A0(n6202), .A1(n2950), .B0(n4116), .B1(n2983), .Y(n3054)
);
XNOR2X1TS U5148 ( .A(n819), .B(n763), .Y(n2985) );
OAI22X1TS U5149 ( .A0(n3114), .A1(n2951), .B0(n3866), .B1(n2985), .Y(n3053)
);
CMPR32X2TS U5150 ( .A(n2957), .B(n2956), .C(n2955), .CO(n3411), .S(n3056) );
OAI22X1TS U5151 ( .A0(n4556), .A1(n2958), .B0(n3116), .B1(n3117), .Y(n3327)
);
XNOR2X1TS U5152 ( .A(n3786), .B(n5203), .Y(n3129) );
OAI22X1TS U5153 ( .A0(n3130), .A1(n3004), .B0(n3537), .B1(n3129), .Y(n3326)
);
XNOR2X1TS U5154 ( .A(n4497), .B(n4882), .Y(n3151) );
OAI22X1TS U5155 ( .A0(n724), .A1(n2959), .B0(n4907), .B1(n3151), .Y(n3325)
);
XNOR2X1TS U5156 ( .A(n3138), .B(n3270), .Y(n3139) );
OAI22X1TS U5157 ( .A0(n5135), .A1(n2960), .B0(n4919), .B1(n3139), .Y(n3372)
);
XNOR2X1TS U5158 ( .A(n638), .B(n2675), .Y(n3001) );
XNOR2X1TS U5159 ( .A(n4797), .B(n4406), .Y(n3119) );
OAI22X1TS U5160 ( .A0(n6795), .A1(n3001), .B0(n5388), .B1(n3119), .Y(n3321)
);
XNOR2X1TS U5161 ( .A(n1948), .B(n6030), .Y(n3162) );
OAI22X1TS U5162 ( .A0(n3211), .A1(n2962), .B0(n3162), .B1(n2961), .Y(n3320)
);
XNOR2X1TS U5163 ( .A(n5631), .B(n8236), .Y(n3120) );
OAI22X1TS U5164 ( .A0(n4780), .A1(n2978), .B0(n721), .B1(n3120), .Y(n3351)
);
XNOR2X1TS U5165 ( .A(n6100), .B(n2866), .Y(n3146) );
OAI22X1TS U5166 ( .A0(n3808), .A1(n2980), .B0(n5743), .B1(n3146), .Y(n3350)
);
XNOR2X1TS U5167 ( .A(n4813), .B(n747), .Y(n3126) );
OAI22X1TS U5168 ( .A0(n6731), .A1(n2981), .B0(n5228), .B1(n3126), .Y(n3349)
);
XNOR2X1TS U5169 ( .A(n3108), .B(n4888), .Y(n3144) );
OAI22X1TS U5170 ( .A0(n3259), .A1(n2982), .B0(n3840), .B1(n3144), .Y(n3369)
);
XNOR2X1TS U5171 ( .A(n749), .B(n3207), .Y(n3125) );
OAI22X1TS U5172 ( .A0(n633), .A1(n2983), .B0(n4116), .B1(n3125), .Y(n3368)
);
XNOR2X1TS U5173 ( .A(n818), .B(n3105), .Y(n3113) );
OAI22X1TS U5174 ( .A0(n3114), .A1(n2985), .B0(n5585), .B1(n3113), .Y(n3367)
);
ADDFHX2TS U5175 ( .A(n2988), .B(n2987), .CI(n2986), .CO(n3093), .S(n3090) );
CMPR32X2TS U5176 ( .A(n2997), .B(n2996), .C(n2995), .CO(n3030), .S(n2907) );
OAI22X1TS U5177 ( .A0(n6795), .A1(n3002), .B0(n5388), .B1(n3001), .Y(n3043)
);
XNOR2X1TS U5178 ( .A(n8819), .B(n5348), .Y(n3073) );
OAI22X1TS U5179 ( .A0(n4682), .A1(n3003), .B0(n806), .B1(n3073), .Y(n3042)
);
OAI22X1TS U5180 ( .A0(n3130), .A1(n3005), .B0(n3537), .B1(n3004), .Y(n3041)
);
ADDFHX1TS U5181 ( .A(n3008), .B(n3007), .CI(n3006), .CO(n3026), .S(n2990) );
CMPR32X2TS U5182 ( .A(n3011), .B(n3010), .C(n3009), .CO(n3061), .S(n2934) );
CMPR32X2TS U5183 ( .A(n3014), .B(n3013), .C(n3012), .CO(n3060), .S(n3007) );
XNOR2X1TS U5184 ( .A(n3920), .B(n3830), .Y(n3033) );
OAI22X1TS U5185 ( .A0(n1710), .A1(n3015), .B0(n760), .B1(n3033), .Y(n3040)
);
XNOR2X1TS U5186 ( .A(n711), .B(n3147), .Y(n3034) );
OAI22X1TS U5187 ( .A0(n4606), .A1(n3016), .B0(n829), .B1(n3034), .Y(n3039)
);
ADDHX1TS U5188 ( .A(n3018), .B(n3017), .CO(n3038), .S(n2941) );
CMPR32X2TS U5189 ( .A(n3027), .B(n3026), .C(n3025), .CO(n3468), .S(n3022) );
CMPR32X2TS U5190 ( .A(n3030), .B(n3029), .C(n3028), .CO(n3432), .S(n3027) );
XNOR2X1TS U5191 ( .A(n8811), .B(n820), .Y(n3133) );
OAI22X1TS U5192 ( .A0(n3540), .A1(n3032), .B0(n3031), .B1(n3133), .Y(n3357)
);
XNOR2X1TS U5193 ( .A(n3920), .B(n3929), .Y(n3131) );
OAI22X1TS U5194 ( .A0(n5667), .A1(n3033), .B0(n4247), .B1(n3131), .Y(n3356)
);
XNOR2X1TS U5195 ( .A(n712), .B(n4671), .Y(n3137) );
OAI22X1TS U5196 ( .A0(n761), .A1(n3034), .B0(n827), .B1(n3137), .Y(n3355) );
CMPR32X2TS U5197 ( .A(n3040), .B(n3039), .C(n3038), .CO(n3394), .S(n3059) );
CMPR32X2TS U5198 ( .A(n3043), .B(n3042), .C(n3041), .CO(n3405), .S(n3028) );
OAI22X1TS U5199 ( .A0(n816), .A1(n3045), .B0(n4295), .B1(n3160), .Y(n3154)
);
XOR2X4TS U5200 ( .A(Op_MX[44]), .B(n8806), .Y(n3047) );
BUFX8TS U5201 ( .A(n6666), .Y(n5113) );
INVX2TS U5202 ( .A(n5113), .Y(n3049) );
XOR2X1TS U5203 ( .A(n3723), .B(n796), .Y(n3048) );
INVX2TS U5204 ( .A(n3050), .Y(n3153) );
XNOR2X1TS U5205 ( .A(n8803), .B(n5873), .Y(n3163) );
OAI22X1TS U5206 ( .A0(n4032), .A1(n3052), .B0(n3051), .B1(n3163), .Y(n3152)
);
CMPR32X2TS U5207 ( .A(n3055), .B(n3054), .C(n3053), .CO(n3403), .S(n2969) );
CMPR32X2TS U5208 ( .A(n3058), .B(n3057), .C(n3056), .CO(n3441), .S(n2992) );
CMPR32X2TS U5209 ( .A(n3064), .B(n3063), .C(n3062), .CO(n3384), .S(n2972) );
OAI22X1TS U5210 ( .A0(n1663), .A1(n3066), .B0(n5410), .B1(n3148), .Y(n3360)
);
OAI22X1TS U5211 ( .A0(n5113), .A1(n911), .B0(n3068), .B1(n731), .Y(n3359) );
OAI22X1TS U5212 ( .A0(n4371), .A1(n3070), .B0(n4370), .B1(n3150), .Y(n3358)
);
XNOR2X1TS U5213 ( .A(n824), .B(n6133), .Y(n3124) );
OAI22X1TS U5214 ( .A0(n4835), .A1(n3072), .B0(n3071), .B1(n3124), .Y(n3333)
);
XNOR2X1TS U5215 ( .A(n4681), .B(n5440), .Y(n3135) );
OAI22X1TS U5216 ( .A0(n4846), .A1(n3073), .B0(n808), .B1(n3135), .Y(n3332)
);
XNOR2X1TS U5217 ( .A(n5331), .B(n3074), .Y(n3118) );
OAI22X1TS U5218 ( .A0(n3577), .A1(n3075), .B0(n5564), .B1(n3118), .Y(n3331)
);
ADDFHX2TS U5219 ( .A(n3084), .B(n3083), .CI(n3082), .CO(n3473), .S(n3085) );
ADDFHX2TS U5220 ( .A(n3090), .B(n3089), .CI(n3088), .CO(n3098), .S(n3094) );
NOR2X8TS U5221 ( .A(n3511), .B(n3510), .Y(n8045) );
NOR2X8TS U5222 ( .A(n3508), .B(n3509), .Y(n8035) );
XNOR2X1TS U5223 ( .A(n2383), .B(n5526), .Y(n3134) );
XNOR2X1TS U5224 ( .A(n4404), .B(n6032), .Y(n3221) );
XNOR2X1TS U5225 ( .A(n4412), .B(n5348), .Y(n3128) );
XNOR2X1TS U5226 ( .A(n8213), .B(n5440), .Y(n3222) );
OAI22X1TS U5227 ( .A0(n4085), .A1(n3128), .B0(n3537), .B1(n3222), .Y(n3311)
);
XNOR2X1TS U5228 ( .A(n8811), .B(n4176), .Y(n3132) );
XNOR2X1TS U5229 ( .A(n6069), .B(n5602), .Y(n3107) );
OAI22X1TS U5230 ( .A0(n782), .A1(n3112), .B0(n5585), .B1(n3107), .Y(n3122)
);
XNOR2X1TS U5231 ( .A(n3223), .B(n711), .Y(n3136) );
XNOR2X1TS U5232 ( .A(n711), .B(n3270), .Y(n3101) );
OAI22X1TS U5233 ( .A0(n761), .A1(n3136), .B0(n829), .B1(n3101), .Y(n3121) );
XNOR2X1TS U5234 ( .A(n8210), .B(n643), .Y(n3106) );
OAI22X1TS U5235 ( .A0(n4606), .A1(n3101), .B0(n828), .B1(n3106), .Y(n3301)
);
XNOR2X1TS U5236 ( .A(n8209), .B(n5207), .Y(n3177) );
OAI22X1TS U5237 ( .A0(n699), .A1(n3177), .B0(n4499), .B1(n3233), .Y(n3300)
);
XNOR2X1TS U5238 ( .A(n5623), .B(n3105), .Y(n3168) );
XNOR2X1TS U5239 ( .A(n5623), .B(n3590), .Y(n3272) );
OAI22X1TS U5240 ( .A0(n6381), .A1(n3168), .B0(n789), .B1(n3272), .Y(n3299)
);
OAI22X1TS U5241 ( .A0(n5328), .A1(n3257), .B0(n3840), .B1(n3564), .Y(n3536)
);
XNOR2X1TS U5242 ( .A(n3103), .B(n3830), .Y(n3193) );
XNOR2X1TS U5243 ( .A(n3103), .B(n3929), .Y(n3563) );
OAI22X1TS U5244 ( .A0(n4217), .A1(n3193), .B0(n4494), .B1(n3563), .Y(n3535)
);
XNOR2X1TS U5245 ( .A(n4218), .B(n6823), .Y(n3220) );
XNOR2X1TS U5246 ( .A(n2383), .B(n5708), .Y(n3612) );
OAI22X1TS U5247 ( .A0(n3104), .A1(n3220), .B0(n4680), .B1(n3612), .Y(n3534)
);
XNOR2X1TS U5248 ( .A(n8813), .B(n3105), .Y(n3591) );
OAI22X1TS U5249 ( .A0(n6055), .A1(n3106), .B0(n826), .B1(n3562), .Y(n3616)
);
XNOR2X1TS U5250 ( .A(n3838), .B(n5986), .Y(n3225) );
XNOR2X1TS U5251 ( .A(n3838), .B(n6030), .Y(n3592) );
OAI22X1TS U5252 ( .A0(n4371), .A1(n3225), .B0(n4370), .B1(n3592), .Y(n3615)
);
XNOR2X1TS U5253 ( .A(n818), .B(n3774), .Y(n3234) );
OAI22X1TS U5254 ( .A0(n6109), .A1(n3107), .B0(n5585), .B1(n3234), .Y(n3111)
);
XNOR2X1TS U5255 ( .A(n3108), .B(n5203), .Y(n3258) );
OAI22X1TS U5256 ( .A0(n3259), .A1(n3143), .B0(n3840), .B1(n3258), .Y(n3199)
);
INVX8TS U5257 ( .A(n7160), .Y(n6131) );
XNOR2X4TS U5258 ( .A(Op_MX[47]), .B(Op_MX[48]), .Y(n3200) );
BUFX3TS U5259 ( .A(n3200), .Y(n7173) );
NOR2BX1TS U5260 ( .AN(n3605), .B(n7173), .Y(n3206) );
XNOR2X1TS U5261 ( .A(n638), .B(n747), .Y(n3173) );
OAI22X1TS U5262 ( .A0(n6988), .A1(n3155), .B0(n7012), .B1(n3264), .Y(n3204)
);
OAI22X1TS U5263 ( .A0(n3114), .A1(n3113), .B0(n5585), .B1(n3112), .Y(n3366)
);
XNOR2X1TS U5264 ( .A(n5331), .B(n736), .Y(n3167) );
OAI22X1TS U5265 ( .A0(n3577), .A1(n3118), .B0(n5564), .B1(n3167), .Y(n3364)
);
XNOR2X4TS U5266 ( .A(Op_MX[46]), .B(Op_MX[45]), .Y(n3180) );
NOR2BX1TS U5267 ( .AN(n3605), .B(n6019), .Y(n3324) );
XNOR2X1TS U5268 ( .A(n638), .B(n4553), .Y(n3174) );
OAI22X1TS U5269 ( .A0(n6988), .A1(n3120), .B0(n7012), .B1(n3156), .Y(n3322)
);
XNOR2X1TS U5270 ( .A(n768), .B(n3830), .Y(n3166) );
OAI22X1TS U5271 ( .A0(n4012), .A1(n3124), .B0(n3228), .B1(n3166), .Y(n3363)
);
XNOR2X1TS U5272 ( .A(n749), .B(n763), .Y(n3169) );
XNOR2X1TS U5273 ( .A(n791), .B(n4843), .Y(n3289) );
OAI22X1TS U5274 ( .A0(n3127), .A1(n3126), .B0(n5228), .B1(n3289), .Y(n3361)
);
OAI22X1TS U5275 ( .A0(n3130), .A1(n3129), .B0(n3537), .B1(n3128), .Y(n3336)
);
XNOR2X1TS U5276 ( .A(n3920), .B(n3985), .Y(n3195) );
OAI22X1TS U5277 ( .A0(n5667), .A1(n3131), .B0(n4247), .B1(n3195), .Y(n3335)
);
OAI22X1TS U5278 ( .A0(n3540), .A1(n3133), .B0(n4002), .B1(n3132), .Y(n3334)
);
OAI22X1TS U5279 ( .A0(n4846), .A1(n3135), .B0(n4845), .B1(n3134), .Y(n3339)
);
OAI22X1TS U5280 ( .A0(n761), .A1(n3137), .B0(n827), .B1(n3136), .Y(n3338) );
XNOR2X1TS U5281 ( .A(n3138), .B(n752), .Y(n3197) );
OAI22X1TS U5282 ( .A0(n5135), .A1(n3139), .B0(n4919), .B1(n3197), .Y(n3337)
);
OAI22X1TS U5283 ( .A0(n3259), .A1(n3144), .B0(n3840), .B1(n3143), .Y(n3307)
);
XNOR2X1TS U5284 ( .A(n6931), .B(n3833), .Y(n3157) );
OAI22X1TS U5285 ( .A0(n5113), .A1(n3145), .B0(n5711), .B1(n3157), .Y(n3306)
);
XNOR2X1TS U5286 ( .A(n8221), .B(n2378), .Y(n3158) );
OAI22X1TS U5287 ( .A0(n3808), .A1(n3146), .B0(n5414), .B1(n3158), .Y(n3305)
);
OAI22X1TS U5288 ( .A0(n6455), .A1(n3148), .B0(n5410), .B1(n3179), .Y(n3172)
);
OAI22X1TS U5289 ( .A0(n3227), .A1(n3150), .B0(n3175), .B1(n3176), .Y(n3171)
);
XNOR2X1TS U5290 ( .A(n8805), .B(n2926), .Y(n3178) );
OAI22X1TS U5291 ( .A0(n724), .A1(n3151), .B0(n4499), .B1(n3178), .Y(n3170)
);
OAI22X1TS U5292 ( .A0(n4055), .A1(n3156), .B0(n5887), .B1(n3155), .Y(n3192)
);
OAI22X1TS U5293 ( .A0(n4202), .A1(n3157), .B0(n5711), .B1(n3217), .Y(n3191)
);
XNOR2X1TS U5294 ( .A(n8221), .B(n4372), .Y(n3218) );
OAI22X1TS U5295 ( .A0(n3808), .A1(n3158), .B0(n5743), .B1(n3218), .Y(n3190)
);
XNOR2X1TS U5296 ( .A(n5874), .B(n3159), .Y(n3287) );
OAI22X1TS U5297 ( .A0(n816), .A1(n3160), .B0(n4295), .B1(n3287), .Y(n3354)
);
OAI22X1TS U5298 ( .A0(n3211), .A1(n3162), .B0(n3161), .B1(n906), .Y(n3353)
);
XNOR2X1TS U5299 ( .A(n8803), .B(n5986), .Y(n3183) );
OAI22X1TS U5300 ( .A0(n2162), .A1(n3163), .B0(n4030), .B1(n3183), .Y(n3352)
);
BUFX4TS U5301 ( .A(n5675), .Y(n4525) );
XNOR2X1TS U5302 ( .A(n824), .B(n3929), .Y(n3216) );
OAI22X1TS U5303 ( .A0(n4012), .A1(n3166), .B0(n4525), .B1(n3216), .Y(n3243)
);
XNOR2X1TS U5304 ( .A(n5331), .B(n4406), .Y(n3194) );
OAI22X1TS U5305 ( .A0(n3577), .A1(n3167), .B0(n5564), .B1(n3194), .Y(n3242)
);
OAI22X1TS U5306 ( .A0(n6381), .A1(n3169), .B0(n789), .B1(n3168), .Y(n3241)
);
OAI22X1TS U5307 ( .A0(n6795), .A1(n3174), .B0(n5388), .B1(n3173), .Y(n3285)
);
XNOR2X1TS U5308 ( .A(n3838), .B(n5873), .Y(n3226) );
OAI22X1TS U5309 ( .A0(n3227), .A1(n3176), .B0(n3175), .B1(n3226), .Y(n3284)
);
OAI22X1TS U5310 ( .A0(n6716), .A1(n3178), .B0(n4499), .B1(n3177), .Y(n3283)
);
OAI22X1TS U5311 ( .A0(n687), .A1(n3179), .B0(n5410), .B1(n3224), .Y(n3215)
);
XOR2X4TS U5312 ( .A(n628), .B(Op_MX[46]), .Y(n3181) );
OAI22X1TS U5313 ( .A0(n5302), .A1(n7158), .B0(n3182), .B1(n6019), .Y(n3214)
);
XNOR2X1TS U5314 ( .A(n8803), .B(n6030), .Y(n3212) );
OAI22X1TS U5315 ( .A0(n4260), .A1(n3183), .B0(n4030), .B1(n3212), .Y(n3213)
);
CMPR32X2TS U5316 ( .A(n3186), .B(n3185), .C(n3184), .CO(n3279), .S(n3413) );
XNOR2X1TS U5317 ( .A(n3103), .B(n5413), .Y(n3196) );
OAI22X1TS U5318 ( .A0(n4217), .A1(n3196), .B0(n625), .B1(n3193), .Y(n3304)
);
XNOR2X1TS U5319 ( .A(n5331), .B(n4553), .Y(n3266) );
OAI22X1TS U5320 ( .A0(n3577), .A1(n3194), .B0(n5564), .B1(n3266), .Y(n3303)
);
OAI22X1TS U5321 ( .A0(n6731), .A1(n3288), .B0(n4687), .B1(n3253), .Y(n3302)
);
XNOR2X1TS U5322 ( .A(n3920), .B(n820), .Y(n3263) );
OAI22X1TS U5323 ( .A0(n1710), .A1(n3195), .B0(n760), .B1(n3263), .Y(n3319)
);
OAI22X1TS U5324 ( .A0(n5135), .A1(n3197), .B0(n744), .B1(n3196), .Y(n3318)
);
ADDHX1TS U5325 ( .A(n3199), .B(n3198), .CO(n3110), .S(n3317) );
XOR2X4TS U5326 ( .A(n8814), .B(Op_MX[48]), .Y(n3201) );
XNOR2X1TS U5327 ( .A(n3290), .B(n7016), .Y(n3202) );
XNOR2X1TS U5328 ( .A(n3724), .B(n6401), .Y(n3570) );
XNOR2X1TS U5329 ( .A(n8229), .B(n6363), .Y(n3597) );
OAI22X1TS U5330 ( .A0(n3211), .A1(n3209), .B0(n3597), .B1(n906), .Y(n3541)
);
OAI22X1TS U5331 ( .A0(n815), .A1(n3286), .B0(n4295), .B1(n3208), .Y(n3249)
);
OAI22X1TS U5332 ( .A0(n3211), .A1(n3210), .B0(n3209), .B1(n906), .Y(n3248)
);
XNOR2X1TS U5333 ( .A(n8803), .B(n6371), .Y(n3273) );
OAI22X1TS U5334 ( .A0(n810), .A1(n3212), .B0(n4030), .B1(n3273), .Y(n3247)
);
XNOR2X1TS U5335 ( .A(n824), .B(n3985), .Y(n3229) );
OAI22X1TS U5336 ( .A0(n4012), .A1(n3216), .B0(n4525), .B1(n3229), .Y(n3269)
);
OAI22X1TS U5337 ( .A0(n3808), .A1(n3218), .B0(n5743), .B1(n3265), .Y(n3267)
);
XNOR2X1TS U5338 ( .A(n765), .B(n5783), .Y(n3232) );
OAI22X1TS U5339 ( .A0(n3575), .A1(n3219), .B0(n3231), .B1(n3232), .Y(n3298)
);
OAI22X1TS U5340 ( .A0(n4846), .A1(n3221), .B0(n806), .B1(n3220), .Y(n3297)
);
XNOR2X1TS U5341 ( .A(n3786), .B(n5526), .Y(n3276) );
OAI22X1TS U5342 ( .A0(n4085), .A1(n3222), .B0(n803), .B1(n3276), .Y(n3296)
);
XNOR2X1TS U5343 ( .A(n705), .B(n3223), .Y(n3271) );
OAI22X1TS U5344 ( .A0(n3227), .A1(n3226), .B0(n4370), .B1(n3225), .Y(n3245)
);
XNOR2X1TS U5345 ( .A(n3724), .B(n7142), .Y(n3291) );
BUFX6TS U5346 ( .A(n6019), .Y(n5877) );
XNOR2X1TS U5347 ( .A(n5990), .B(n3833), .Y(n3256) );
OAI22X1TS U5348 ( .A0(n5302), .A1(n3291), .B0(n5877), .B1(n3256), .Y(n3244)
);
OAI22X1TS U5349 ( .A0(n4012), .A1(n3229), .B0(n3228), .B1(n3561), .Y(n3610)
);
XNOR2X1TS U5350 ( .A(n8811), .B(n4480), .Y(n3539) );
OAI22X1TS U5351 ( .A0(n3540), .A1(n3260), .B0(n4002), .B1(n3539), .Y(n3609)
);
XNOR2X1TS U5352 ( .A(n678), .B(n4176), .Y(n3262) );
XNOR2X1TS U5353 ( .A(n3920), .B(Op_MY[33]), .Y(n3566) );
OAI22X1TS U5354 ( .A0(n4436), .A1(n3262), .B0(n4247), .B1(n3566), .Y(n3608)
);
OAI22X1TS U5355 ( .A0(n3575), .A1(n3232), .B0(n3231), .B1(n3574), .Y(n3580)
);
OAI22X1TS U5356 ( .A0(n6716), .A1(n3233), .B0(n4499), .B1(n3614), .Y(n3579)
);
XNOR2X1TS U5357 ( .A(n5489), .B(n3877), .Y(n3565) );
OAI22X1TS U5358 ( .A0(n782), .A1(n3234), .B0(n5585), .B1(n3565), .Y(n3578)
);
OAI22X1TS U5359 ( .A0(n6264), .A1(n3256), .B0(n5877), .B1(n3571), .Y(n3618)
);
OAI22X1TS U5360 ( .A0(n809), .A1(n3263), .B0(n4247), .B1(n3262), .Y(n3293)
);
XNOR2X1TS U5361 ( .A(n5631), .B(n4372), .Y(n3607) );
XNOR2X1TS U5362 ( .A(n5095), .B(n747), .Y(n3576) );
OAI22X1TS U5363 ( .A0(n3577), .A1(n3266), .B0(n5564), .B1(n3576), .Y(n3621)
);
XNOR2X1TS U5364 ( .A(n3594), .B(n3270), .Y(n3595) );
OAI22X1TS U5365 ( .A0(n687), .A1(n3271), .B0(n5410), .B1(n3595), .Y(n3560)
);
XNOR2X1TS U5366 ( .A(n5623), .B(n5745), .Y(n3593) );
XNOR2X1TS U5367 ( .A(n8803), .B(n6131), .Y(n3598) );
OAI22X1TS U5368 ( .A0(n4032), .A1(n3273), .B0(n4030), .B1(n3598), .Y(n3558)
);
OAI22X1TS U5369 ( .A0(n5791), .A1(n3274), .B0(n5388), .B1(n3606), .Y(n3589)
);
XNOR2X1TS U5370 ( .A(n796), .B(n2866), .Y(n3572) );
OAI22X1TS U5371 ( .A0(n4202), .A1(n3275), .B0(n6023), .B1(n3572), .Y(n3588)
);
XNOR2X1TS U5372 ( .A(n8213), .B(n4905), .Y(n3538) );
OAI22X1TS U5373 ( .A0(n4085), .A1(n3276), .B0(n3537), .B1(n3538), .Y(n3587)
);
CMPR32X2TS U5374 ( .A(n3282), .B(n3281), .C(n3280), .CO(n3601), .S(n3277) );
OAI22X1TS U5375 ( .A0(n814), .A1(n3287), .B0(n4295), .B1(n3286), .Y(n3310)
);
OAI22X1TS U5376 ( .A0(n6071), .A1(n3289), .B0(n5228), .B1(n3288), .Y(n3309)
);
XNOR2X1TS U5377 ( .A(n3290), .B(n7142), .Y(n3292) );
CMPR32X2TS U5378 ( .A(n3316), .B(n3315), .C(n3314), .CO(n3600), .S(n3377) );
CMPR32X2TS U5379 ( .A(n3319), .B(n3318), .C(n3317), .CO(n3280), .S(n3393) );
ADDHX1TS U5380 ( .A(n3321), .B(n3320), .CO(n3375), .S(n3371) );
CMPR32X2TS U5381 ( .A(n3327), .B(n3326), .C(n3325), .CO(n3373), .S(n3410) );
CMPR32X2TS U5382 ( .A(n3333), .B(n3332), .C(n3331), .CO(n3402), .S(n3382) );
CMPR32X2TS U5383 ( .A(n3339), .B(n3338), .C(n3337), .CO(n3343), .S(n3400) );
CMPR32X2TS U5384 ( .A(n3342), .B(n3341), .C(n3340), .CO(n3378), .S(n3422) );
CMPR32X2TS U5385 ( .A(n3345), .B(n3344), .C(n3343), .CO(n3140), .S(n3421) );
CMPR32X2TS U5386 ( .A(n3351), .B(n3350), .C(n3349), .CO(n3390), .S(n3407) );
CMPR32X2TS U5387 ( .A(n3390), .B(n3389), .C(n3388), .CO(n3417), .S(n3442) );
CMPR32X2TS U5388 ( .A(n3399), .B(n3398), .C(n3397), .CO(n3414), .S(n3452) );
CMPR32X2TS U5389 ( .A(n3402), .B(n3401), .C(n3400), .CO(n3423), .S(n3451) );
CMPR32X2TS U5390 ( .A(n3405), .B(n3404), .C(n3403), .CO(n3447), .S(n3430) );
CMPR32X2TS U5391 ( .A(n3426), .B(n3425), .C(n3424), .CO(n3415), .S(n3459) );
ADDFHX2TS U5392 ( .A(n3438), .B(n3437), .CI(n3436), .CO(n3630), .S(n3480) );
CMPR32X2TS U5393 ( .A(n3453), .B(n3452), .C(n3451), .CO(n3433), .S(n3483) );
ADDFHX2TS U5394 ( .A(n3456), .B(n3455), .CI(n3454), .CO(n3482), .S(n3472) );
ADDFHX2TS U5395 ( .A(n3462), .B(n3461), .CI(n3460), .CO(n3528), .S(n3478) );
ADDFHX2TS U5396 ( .A(n3483), .B(n3482), .CI(n3481), .CO(n3475), .S(n3495) );
NOR2X8TS U5397 ( .A(n7918), .B(n7914), .Y(n7926) );
NAND2X6TS U5398 ( .A(n3501), .B(n3500), .Y(n8059) );
NAND2X4TS U5399 ( .A(n3503), .B(n3502), .Y(n8062) );
INVX4TS U5400 ( .A(n8062), .Y(n3504) );
NAND2X4TS U5401 ( .A(n3507), .B(n3506), .Y(n8055) );
OAI21X4TS U5402 ( .A0(n656), .A1(n8053), .B0(n8055), .Y(n8032) );
NAND2X4TS U5403 ( .A(n3509), .B(n3508), .Y(n8040) );
OAI21X4TS U5404 ( .A0(n8040), .A1(n8045), .B0(n8046), .Y(n3512) );
AOI21X4TS U5405 ( .A0(n8032), .A1(n3513), .B0(n3512), .Y(n7902) );
OAI21X4TS U5406 ( .A0(n7918), .A1(n8027), .B0(n7919), .Y(n7925) );
NAND2X2TS U5407 ( .A(n3521), .B(n3520), .Y(n7909) );
OA21X4TS U5408 ( .A0(n7902), .A1(n3525), .B0(n3524), .Y(n3526) );
NAND2X8TS U5409 ( .A(n3526), .B(n3527), .Y(n5258) );
ADDFHX4TS U5410 ( .A(n3530), .B(n3529), .CI(n3528), .CO(n5025), .S(n3521) );
CMPR32X2TS U5411 ( .A(n3533), .B(n3532), .C(n3531), .CO(n3733), .S(n3555) );
CMPR32X2TS U5412 ( .A(n3536), .B(n3535), .C(n3534), .CO(n3635), .S(n3626) );
OAI22X1TS U5413 ( .A0(n4085), .A1(n3538), .B0(n3537), .B1(n3687), .Y(n3697)
);
XNOR2X1TS U5414 ( .A(n8811), .B(n4500), .Y(n3692) );
OAI22X1TS U5415 ( .A0(n3540), .A1(n3539), .B0(n4002), .B1(n3692), .Y(n3696)
);
ADDFHX2TS U5416 ( .A(n3548), .B(n3547), .CI(n3546), .CO(n3731), .S(n3551) );
XNOR2X1TS U5417 ( .A(n823), .B(n4176), .Y(n3684) );
OAI22X1TS U5418 ( .A0(n4012), .A1(n3561), .B0(n4525), .B1(n3684), .Y(n3638)
);
XNOR2X1TS U5419 ( .A(n711), .B(n3830), .Y(n3693) );
OAI22X1TS U5420 ( .A0(n761), .A1(n3562), .B0(n3863), .B1(n3693), .Y(n3637)
);
XNOR2X1TS U5421 ( .A(n3103), .B(n3985), .Y(n3694) );
OAI22X1TS U5422 ( .A0(n4217), .A1(n3563), .B0(n4494), .B1(n3694), .Y(n3636)
);
OAI22X1TS U5423 ( .A0(n782), .A1(n3565), .B0(n5585), .B1(n3705), .Y(n3669)
);
OAI22X1TS U5424 ( .A0(n3793), .A1(n3566), .B0(n4247), .B1(n3639), .Y(n3668)
);
XNOR2X1TS U5425 ( .A(n8214), .B(n3833), .Y(n3728) );
OAI22X1TS U5426 ( .A0(n688), .A1(n3570), .B0(n6021), .B1(n3728), .Y(n3703)
);
XNOR2X1TS U5427 ( .A(n8217), .B(n2378), .Y(n3675) );
OAI22X1TS U5428 ( .A0(n4202), .A1(n3572), .B0(n5711), .B1(n3675), .Y(n3701)
);
XNOR2X1TS U5429 ( .A(n6690), .B(n4553), .Y(n3676) );
OAI22X1TS U5430 ( .A0(n3808), .A1(n3573), .B0(n5743), .B1(n3676), .Y(n3690)
);
XNOR2X1TS U5431 ( .A(n4000), .B(n5986), .Y(n3674) );
OAI22X1TS U5432 ( .A0(n3575), .A1(n3574), .B0(n2270), .B1(n3674), .Y(n3689)
);
XNOR2X1TS U5433 ( .A(n5095), .B(n4843), .Y(n3672) );
OAI22X1TS U5434 ( .A0(n3577), .A1(n3576), .B0(n5564), .B1(n3672), .Y(n3688)
);
CMPR32X2TS U5435 ( .A(n3583), .B(n3582), .C(n3581), .CO(n3712), .S(n3599) );
CMPR32X2TS U5436 ( .A(n3586), .B(n3585), .C(n3584), .CO(n3711), .S(n3546) );
CMPR32X2TS U5437 ( .A(n3589), .B(n3588), .C(n3587), .CO(n3700), .S(n3531) );
OAI22X1TS U5438 ( .A0(n814), .A1(n3591), .B0(n734), .B1(n3704), .Y(n3721) );
XNOR2X1TS U5439 ( .A(n3838), .B(n6371), .Y(n3682) );
XNOR2X1TS U5440 ( .A(n5623), .B(n3774), .Y(n3730) );
OAI22X1TS U5441 ( .A0(n6381), .A1(n3593), .B0(n6365), .B1(n3730), .Y(n3719)
);
XNOR2X1TS U5442 ( .A(n3594), .B(n753), .Y(n3681) );
OAI22X1TS U5443 ( .A0(n704), .A1(n3595), .B0(n5410), .B1(n3681), .Y(n3679)
);
INVX8TS U5444 ( .A(Op_MY[50]), .Y(n7183) );
XNOR2X1TS U5445 ( .A(n6329), .B(n8229), .Y(n3683) );
OAI22X1TS U5446 ( .A0(n3837), .A1(n3597), .B0(n3683), .B1(n2159), .Y(n3678)
);
XNOR2X1TS U5447 ( .A(n8803), .B(n6378), .Y(n3727) );
OAI22X1TS U5448 ( .A0(n810), .A1(n3598), .B0(n4030), .B1(n3727), .Y(n3677)
);
XNOR2X4TS U5449 ( .A(Op_MX[50]), .B(Op_MX[49]), .Y(n3832) );
XNOR2X1TS U5450 ( .A(n5090), .B(n6327), .Y(n3640) );
XNOR2X1TS U5451 ( .A(n5631), .B(n736), .Y(n3722) );
OAI22X1TS U5452 ( .A0(n812), .A1(n3607), .B0(n5887), .B1(n3722), .Y(n3644)
);
OAI22X1TS U5453 ( .A0(n3782), .A1(n3612), .B0(n3685), .B1(n3686), .Y(n3709)
);
XNOR2X1TS U5454 ( .A(n4497), .B(n763), .Y(n3706) );
OAI22X1TS U5455 ( .A0(n6716), .A1(n3614), .B0(n4499), .B1(n3706), .Y(n3707)
);
CMPR32X2TS U5456 ( .A(n3623), .B(n3622), .C(n3621), .CO(n3665), .S(n3567) );
XNOR2X1TS U5457 ( .A(n3920), .B(n4480), .Y(n3792) );
OAI22X1TS U5458 ( .A0(n809), .A1(n3639), .B0(n4247), .B1(n3792), .Y(n3742)
);
OAI22X1TS U5459 ( .A0(n4243), .A1(n3640), .B0(n4892), .B1(n3745), .Y(n3744)
);
XOR2X4TS U5460 ( .A(n7055), .B(Op_MX[50]), .Y(n3641) );
NAND2X8TS U5461 ( .A(n3641), .B(n3832), .Y(n6646) );
NAND2BX1TS U5462 ( .AN(n3642), .B(n7055), .Y(n3643) );
CMPR32X2TS U5463 ( .A(n3649), .B(n3648), .C(n3647), .CO(n3753), .S(n3652) );
XNOR2X1TS U5464 ( .A(n6383), .B(n5392), .Y(n3776) );
OAI22X1TS U5465 ( .A0(n781), .A1(n3671), .B0(n4687), .B1(n3776), .Y(n3791)
);
XNOR2X1TS U5466 ( .A(n741), .B(n4905), .Y(n3841) );
OAI22X1TS U5467 ( .A0(n5328), .A1(n3673), .B0(n3840), .B1(n3841), .Y(n3789)
);
XNOR2X1TS U5468 ( .A(n4000), .B(n6030), .Y(n3783) );
OAI22X1TS U5469 ( .A0(n4610), .A1(n3674), .B0(n4608), .B1(n3783), .Y(n3773)
);
OAI22X1TS U5470 ( .A0(n4202), .A1(n3675), .B0(n6023), .B1(n3806), .Y(n3772)
);
XNOR2X1TS U5471 ( .A(n6208), .B(n747), .Y(n3807) );
OAI22X1TS U5472 ( .A0(n3808), .A1(n3676), .B0(n5743), .B1(n3807), .Y(n3771)
);
CMPR32X2TS U5473 ( .A(n3679), .B(n3678), .C(n3677), .CO(n3826), .S(n3698) );
OAI22X1TS U5474 ( .A0(n1663), .A1(n3681), .B0(n3680), .B1(n3831), .Y(n3780)
);
XNOR2X1TS U5475 ( .A(n3838), .B(n6131), .Y(n3839) );
OAI22X1TS U5476 ( .A0(n3837), .A1(n3683), .B0(n3836), .B1(n2159), .Y(n3778)
);
XNOR2X1TS U5477 ( .A(n825), .B(Op_MY[33]), .Y(n3805) );
OAI22X1TS U5478 ( .A0(n4012), .A1(n3684), .B0(n4525), .B1(n3805), .Y(n3829)
);
XNOR2X1TS U5479 ( .A(n3611), .B(n5873), .Y(n3781) );
OAI22X1TS U5480 ( .A0(n3782), .A1(n3686), .B0(n3685), .B1(n3781), .Y(n3828)
);
XNOR2X1TS U5481 ( .A(n8213), .B(n5708), .Y(n3787) );
OAI22X1TS U5482 ( .A0(n4880), .A1(n3687), .B0(n804), .B1(n3787), .Y(n3827)
);
INVX4TS U5483 ( .A(n6830), .Y(n4678) );
XNOR2X1TS U5484 ( .A(n3691), .B(n4678), .Y(n3784) );
OAI22X1TS U5485 ( .A0(n5535), .A1(n3692), .B0(n4002), .B1(n3784), .Y(n3811)
);
XNOR2X1TS U5486 ( .A(n711), .B(n3929), .Y(n3796) );
OAI22X1TS U5487 ( .A0(n2457), .A1(n3693), .B0(n828), .B1(n3796), .Y(n3810)
);
XNOR2X1TS U5488 ( .A(n5567), .B(n3986), .Y(n3777) );
OAI22X1TS U5489 ( .A0(n4217), .A1(n3694), .B0(n625), .B1(n3777), .Y(n3809)
);
CMPR32X2TS U5490 ( .A(n3700), .B(n3699), .C(n3698), .CO(n3763), .S(n3710) );
XNOR2X1TS U5491 ( .A(n5784), .B(n5745), .Y(n3775) );
OAI22X1TS U5492 ( .A0(n816), .A1(n3704), .B0(n734), .B1(n3775), .Y(n3804) );
XNOR2X1TS U5493 ( .A(n8808), .B(n4090), .Y(n3798) );
OAI22X1TS U5494 ( .A0(n782), .A1(n3705), .B0(n5585), .B1(n3798), .Y(n3803)
);
XNOR2X1TS U5495 ( .A(n8209), .B(n5589), .Y(n3795) );
OAI22X1TS U5496 ( .A0(n4115), .A1(n3706), .B0(n6073), .B1(n3795), .Y(n3802)
);
CMPR32X2TS U5497 ( .A(n3709), .B(n3708), .C(n3707), .CO(n3821), .S(n3647) );
CMPR32X2TS U5498 ( .A(n3712), .B(n3711), .C(n3710), .CO(n3817), .S(n3653) );
ADDFHX2TS U5499 ( .A(n3718), .B(n3717), .CI(n3716), .CO(n3819), .S(n3664) );
XNOR2X1TS U5500 ( .A(n5631), .B(n4406), .Y(n3746) );
OAI22X1TS U5501 ( .A0(n6679), .A1(n3722), .B0(n5887), .B1(n3746), .Y(n3749)
);
XNOR2X1TS U5502 ( .A(n3723), .B(n681), .Y(n3725) );
XNOR2X1TS U5503 ( .A(n3726), .B(n6363), .Y(n3835) );
OAI22X1TS U5504 ( .A0(n2039), .A1(n3727), .B0(n4030), .B1(n3835), .Y(n3747)
);
XNOR2X1TS U5505 ( .A(n6401), .B(n8236), .Y(n3785) );
OAI22X1TS U5506 ( .A0(n6125), .A1(n3728), .B0(n6021), .B1(n3785), .Y(n3770)
);
XNOR2X1TS U5507 ( .A(n5990), .B(n3992), .Y(n3788) );
XNOR2X1TS U5508 ( .A(n5623), .B(n3877), .Y(n3797) );
OAI22X1TS U5509 ( .A0(n5944), .A1(n3730), .B0(n788), .B1(n3797), .Y(n3768)
);
NOR2BX1TS U5510 ( .AN(n8590), .B(n681), .Y(n3859) );
XNOR2X2TS U5511 ( .A(n6660), .B(n5324), .Y(n3860) );
OAI22X2TS U5512 ( .A0(n4243), .A1(n3745), .B0(n4892), .B1(n3860), .Y(n3858)
);
XNOR2X1TS U5513 ( .A(n5631), .B(n4553), .Y(n3862) );
OAI22X1TS U5514 ( .A0(n6988), .A1(n3746), .B0(n5887), .B1(n3862), .Y(n3857)
);
ADDFHX2TS U5515 ( .A(n3755), .B(n3754), .CI(n3753), .CO(n3952), .S(n3843) );
CMPR32X2TS U5516 ( .A(n3773), .B(n3772), .C(n3771), .CO(n3946), .S(n3765) );
OAI22X1TS U5517 ( .A0(n814), .A1(n3775), .B0(n734), .B1(n3878), .Y(n3873) );
XNOR2X1TS U5518 ( .A(n6383), .B(n762), .Y(n3924) );
XNOR2X1TS U5519 ( .A(n5567), .B(n4176), .Y(n3881) );
OAI22X1TS U5520 ( .A0(n4217), .A1(n3777), .B0(n4494), .B1(n3881), .Y(n3871)
);
OAI22X1TS U5521 ( .A0(n5535), .A1(n3784), .B0(n5534), .B1(n3896), .Y(n3874)
);
XNOR2X1TS U5522 ( .A(n698), .B(n3971), .Y(n3898) );
OAI22X1TS U5523 ( .A0(n688), .A1(n3785), .B0(n6021), .B1(n3898), .Y(n3927)
);
XNOR2X1TS U5524 ( .A(n4412), .B(n5783), .Y(n3900) );
OAI22X1TS U5525 ( .A0(n4057), .A1(n3787), .B0(n3899), .B1(n3900), .Y(n3926)
);
OAI22X1TS U5526 ( .A0(n6264), .A1(n3788), .B0(n5877), .B1(n3901), .Y(n3925)
);
OAI22X1TS U5527 ( .A0(n5575), .A1(n3792), .B0(n4247), .B1(n3921), .Y(n3919)
);
XNOR2X1TS U5528 ( .A(n6686), .B(n5090), .Y(n3922) );
OAI22X1TS U5529 ( .A0(n6067), .A1(n3794), .B0(n5224), .B1(n3922), .Y(n3918)
);
XNOR2X1TS U5530 ( .A(n778), .B(n5662), .Y(n3880) );
OAI22X1TS U5531 ( .A0(n714), .A1(n3795), .B0(n6073), .B1(n3880), .Y(n3917)
);
XNOR2X1TS U5532 ( .A(n4415), .B(n3985), .Y(n3864) );
OAI22X1TS U5533 ( .A0(n761), .A1(n3796), .B0(n827), .B1(n3864), .Y(n3910) );
XNOR2X1TS U5534 ( .A(n5623), .B(Op_MY[24]), .Y(n3865) );
OAI22X1TS U5535 ( .A0(n5625), .A1(n3797), .B0(n789), .B1(n3865), .Y(n3909)
);
XNOR2X1TS U5536 ( .A(n8224), .B(n753), .Y(n3867) );
OAI22X1TS U5537 ( .A0(n782), .A1(n3798), .B0(n5585), .B1(n3867), .Y(n3908)
);
CMPR32X2TS U5538 ( .A(n3801), .B(n3800), .C(n3799), .CO(n3886), .S(n3818) );
CMPR32X2TS U5539 ( .A(n3804), .B(n3803), .C(n3802), .CO(n3944), .S(n3822) );
OAI22X1TS U5540 ( .A0(n4012), .A1(n3805), .B0(n4525), .B1(n3905), .Y(n3904)
);
OAI22X1TS U5541 ( .A0(n4202), .A1(n3806), .B0(n6023), .B1(n3906), .Y(n3903)
);
XNOR2X1TS U5542 ( .A(n797), .B(n4843), .Y(n3907) );
OAI22X1TS U5543 ( .A0(n3808), .A1(n3807), .B0(n5743), .B1(n3907), .Y(n3902)
);
CMPR32X2TS U5544 ( .A(n3823), .B(n3822), .C(n3821), .CO(n3941), .S(n3762) );
OAI22X1TS U5545 ( .A0(n3837), .A1(n3836), .B0(n1822), .B1(n1948), .Y(n3893)
);
XNOR2X1TS U5546 ( .A(n4570), .B(n5707), .Y(n3934) );
NOR2X8TS U5547 ( .A(n5029), .B(n5030), .Y(n8161) );
ADDFHX2TS U5548 ( .A(n3853), .B(n3852), .CI(n3851), .CO(n4135), .S(n3953) );
XNOR2X1TS U5549 ( .A(n4797), .B(n5392), .Y(n3982) );
OAI22X2TS U5550 ( .A0(n4243), .A1(n3860), .B0(n4892), .B1(n3982), .Y(n3968)
);
OAI22X1TS U5551 ( .A0(n3969), .A1(n6984), .B0(n1201), .B1(n6104), .Y(n3967)
);
XNOR2X1TS U5552 ( .A(n6054), .B(n6335), .Y(n3975) );
OAI22X1TS U5553 ( .A0(n4606), .A1(n3864), .B0(n3863), .B1(n3975), .Y(n4041)
);
XNOR2X1TS U5554 ( .A(n748), .B(n4090), .Y(n3999) );
OAI22X1TS U5555 ( .A0(n5625), .A1(n3865), .B0(n788), .B1(n3999), .Y(n4040)
);
XNOR2X1TS U5556 ( .A(n8224), .B(n6133), .Y(n3974) );
OAI22X1TS U5557 ( .A0(n782), .A1(n3867), .B0(n3866), .B1(n3974), .Y(n4039)
);
CMPR32X2TS U5558 ( .A(n3873), .B(n3872), .C(n3871), .CO(n4147), .S(n3945) );
XNOR2X1TS U5559 ( .A(n4497), .B(n5602), .Y(n3998) );
XNOR2X1TS U5560 ( .A(n3103), .B(Op_MY[33]), .Y(n3984) );
OAI22X1TS U5561 ( .A0(n4217), .A1(n3881), .B0(n4494), .B1(n3984), .Y(n3976)
);
CMPR32X2TS U5562 ( .A(n3890), .B(n3889), .C(n3888), .CO(n4050), .S(n3854) );
XNOR2X1TS U5563 ( .A(n2383), .B(n6030), .Y(n4004) );
OAI22X1TS U5564 ( .A0(n4613), .A1(n3897), .B0(n4680), .B1(n4004), .Y(n3979)
);
XNOR2X1TS U5565 ( .A(n8814), .B(n2866), .Y(n3970) );
OAI22X1TS U5566 ( .A0(n7174), .A1(n3898), .B0(n6437), .B1(n3970), .Y(n4023)
);
OAI22X1TS U5567 ( .A0(n4057), .A1(n3900), .B0(n3899), .B1(n4056), .Y(n4022)
);
XNOR2X1TS U5568 ( .A(n5990), .B(n4372), .Y(n4029) );
OAI22X1TS U5569 ( .A0(n6264), .A1(n3901), .B0(n6406), .B1(n4029), .Y(n4021)
);
CMPR32X2TS U5570 ( .A(n3904), .B(n3903), .C(n3902), .CO(n4144), .S(n3943) );
OAI22X1TS U5571 ( .A0(n4012), .A1(n3905), .B0(n4525), .B1(n4011), .Y(n4010)
);
OAI22X1TS U5572 ( .A0(n4202), .A1(n3906), .B0(n6023), .B1(n4026), .Y(n4009)
);
XNOR2X1TS U5573 ( .A(n8221), .B(n2878), .Y(n4058) );
OAI22X1TS U5574 ( .A0(n813), .A1(n3907), .B0(n5743), .B1(n4058), .Y(n4008)
);
CMPR32X2TS U5575 ( .A(n3913), .B(n3912), .C(n3911), .CO(n4129), .S(n3887) );
CMPR32X2TS U5576 ( .A(n3916), .B(n3915), .C(n3914), .CO(n4044), .S(n3949) );
OAI22X1TS U5577 ( .A0(n1710), .A1(n3921), .B0(n4247), .B1(n3973), .Y(n4035)
);
XNOR2X1TS U5578 ( .A(n5095), .B(n5207), .Y(n4013) );
OAI22X1TS U5579 ( .A0(n6067), .A1(n3922), .B0(n5224), .B1(n4013), .Y(n4034)
);
XNOR2X1TS U5580 ( .A(n6662), .B(n5589), .Y(n4014) );
OAI22X1TS U5581 ( .A0(n3127), .A1(n3924), .B0(n690), .B1(n4014), .Y(n4033)
);
CMPR32X2TS U5582 ( .A(n3927), .B(n3926), .C(n3925), .CO(n4150), .S(n3888) );
XNOR2X1TS U5583 ( .A(n5880), .B(n3929), .Y(n4025) );
XNOR2X1TS U5584 ( .A(n4883), .B(n8236), .Y(n3972) );
OAI22X1TS U5585 ( .A0(n6850), .A1(n3932), .B0(n6332), .B1(n3972), .Y(n4036)
);
XNOR2X1TS U5586 ( .A(n4570), .B(n5708), .Y(n4028) );
XNOR2X1TS U5587 ( .A(n801), .B(n6363), .Y(n3983) );
OAI22X1TS U5588 ( .A0(n4371), .A1(n3935), .B0(n4370), .B1(n3983), .Y(n4052)
);
ADDFX2TS U5589 ( .A(n3941), .B(n3940), .CI(n3939), .CO(n4123), .S(n3937) );
CMPR32X2TS U5590 ( .A(n3944), .B(n3943), .C(n3942), .CO(n4132), .S(n3885) );
CMPR32X2TS U5591 ( .A(n3950), .B(n3949), .C(n3948), .CO(n4130), .S(n3939) );
ADDFHX2TS U5592 ( .A(n3956), .B(n3955), .CI(n3954), .CO(n4389), .S(n3962) );
ADDFHX4TS U5593 ( .A(n3962), .B(n3961), .CI(n3960), .CO(n5031), .S(n5029) );
OAI22X1TS U5594 ( .A0(n3969), .A1(n7752), .B0(n3988), .B1(n6414), .Y(n4173)
);
INVX2TS U5595 ( .A(n4173), .Y(n3991) );
XNOR2X1TS U5596 ( .A(n4883), .B(n3971), .Y(n3993) );
OAI22X1TS U5597 ( .A0(n6850), .A1(n3972), .B0(n6332), .B1(n3993), .Y(n3989)
);
OAI22X1TS U5598 ( .A0(n5667), .A1(n3973), .B0(n5666), .B1(n4077), .Y(n4076)
);
OAI22X1TS U5599 ( .A0(n4808), .A1(n3974), .B0(n4322), .B1(n4078), .Y(n4075)
);
XNOR2X1TS U5600 ( .A(n5132), .B(n4176), .Y(n4079) );
OAI22X1TS U5601 ( .A0(n2457), .A1(n3975), .B0(n828), .B1(n4079), .Y(n4074)
);
CMPR32X2TS U5602 ( .A(n3981), .B(n3980), .C(n3979), .CO(n4019), .S(n4063) );
XNOR2X1TS U5603 ( .A(n8809), .B(n762), .Y(n4113) );
OAI22X1TS U5604 ( .A0(n4243), .A1(n3982), .B0(n4892), .B1(n4113), .Y(n4007)
);
OAI22X1TS U5605 ( .A0(n4371), .A1(n3983), .B0(n4092), .B1(n4442), .Y(n4006)
);
OAI22X1TS U5606 ( .A0(n4217), .A1(n3984), .B0(n4494), .B1(n4105), .Y(n4005)
);
OAI22X1TS U5607 ( .A0(n6104), .A1(n3988), .B0(n4175), .B1(n6414), .Y(n4292)
);
INVX2TS U5608 ( .A(n4292), .Y(n4172) );
XNOR2X1TS U5609 ( .A(n4570), .B(n5783), .Y(n4027) );
XNOR2X1TS U5610 ( .A(n4570), .B(n5873), .Y(n4203) );
OAI22X1TS U5611 ( .A0(n4204), .A1(n4027), .B0(n5190), .B1(n4203), .Y(n4180)
);
OAI22X1TS U5612 ( .A0(n6850), .A1(n3993), .B0(n6179), .B1(n4209), .Y(n4179)
);
OAI22X1TS U5613 ( .A0(n3164), .A1(n8212), .B0(n4030), .B1(n4258), .Y(n4178)
);
XNOR2X1TS U5614 ( .A(n708), .B(n8233), .Y(n4091) );
OAI22X1TS U5615 ( .A0(n815), .A1(n3997), .B0(n734), .B1(n4091), .Y(n4017) );
OAI22X1TS U5616 ( .A0(n4540), .A1(n3998), .B0(n6073), .B1(n4114), .Y(n4016)
);
XNOR2X1TS U5617 ( .A(n749), .B(n752), .Y(n4117) );
OAI22X1TS U5618 ( .A0(n6202), .A1(n3999), .B0(n789), .B1(n4117), .Y(n4015)
);
XNOR2X1TS U5619 ( .A(n4000), .B(n6378), .Y(n4097) );
OAI22X1TS U5620 ( .A0(n4610), .A1(n4001), .B0(n2270), .B1(n4097), .Y(n4061)
);
INVX4TS U5621 ( .A(n6917), .Y(n5129) );
XNOR2X1TS U5622 ( .A(n4218), .B(n6371), .Y(n4098) );
OAI22X1TS U5623 ( .A0(n4613), .A1(n4004), .B0(n4680), .B1(n4098), .Y(n4059)
);
CMPR32X2TS U5624 ( .A(n4007), .B(n4006), .C(n4005), .CO(n4184), .S(n4018) );
XNOR2X1TS U5625 ( .A(n823), .B(n4500), .Y(n4118) );
XNOR2X1TS U5626 ( .A(n5095), .B(n5324), .Y(n4093) );
OAI22X1TS U5627 ( .A0(n6067), .A1(n4013), .B0(n5224), .B1(n4093), .Y(n4110)
);
XNOR2X1TS U5628 ( .A(n791), .B(n5662), .Y(n4101) );
OAI22X1TS U5629 ( .A0(n6731), .A1(n4014), .B0(n690), .B1(n4101), .Y(n4109)
);
XNOR2X1TS U5630 ( .A(n6931), .B(n4553), .Y(n4119) );
OAI22X1TS U5631 ( .A0(n4202), .A1(n4026), .B0(n6023), .B1(n4119), .Y(n4072)
);
OAI22X1TS U5632 ( .A0(n4204), .A1(n4028), .B0(n4408), .B1(n4027), .Y(n4096)
);
XNOR2X1TS U5633 ( .A(n5990), .B(n736), .Y(n4086) );
OAI22X1TS U5634 ( .A0(n6264), .A1(n4029), .B0(n6406), .B1(n4086), .Y(n4095)
);
OAI22X1TS U5635 ( .A0(n810), .A1(n4031), .B0(n4030), .B1(n8212), .Y(n4094)
);
CMPR32X2TS U5636 ( .A(n4044), .B(n4043), .C(n4042), .CO(n4140), .S(n4128) );
XNOR2X1TS U5637 ( .A(Op_MX[43]), .B(n4843), .Y(n4104) );
OAI22X1TS U5638 ( .A0(n4055), .A1(n4054), .B0(n5887), .B1(n4104), .Y(n4089)
);
XNOR2X1TS U5639 ( .A(n6208), .B(n713), .Y(n4120) );
OAI22X1TS U5640 ( .A0(n813), .A1(n4058), .B0(n5414), .B1(n4120), .Y(n4087)
);
ADDFHX1TS U5641 ( .A(n4064), .B(n4063), .CI(n4062), .CO(n4069), .S(n4049) );
CMPR32X2TS U5642 ( .A(n4067), .B(n4066), .C(n4065), .CO(n4272), .S(n4068) );
XNOR2X1TS U5643 ( .A(n755), .B(n6775), .Y(n4248) );
OAI22X1TS U5644 ( .A0(n3793), .A1(n4077), .B0(n4247), .B1(n4248), .Y(n4255)
);
XNOR2X1TS U5645 ( .A(n819), .B(n4420), .Y(n4245) );
OAI22X1TS U5646 ( .A0(n4808), .A1(n4078), .B0(n5292), .B1(n4245), .Y(n4254)
);
XNOR2X1TS U5647 ( .A(n711), .B(Op_MY[33]), .Y(n4200) );
OAI22X1TS U5648 ( .A0(n5305), .A1(n4079), .B0(n827), .B1(n4200), .Y(n4253)
);
XNOR2X1TS U5649 ( .A(n6401), .B(n4372), .Y(n4227) );
OAI22X1TS U5650 ( .A0(n6886), .A1(n4083), .B0(n6437), .B1(n4227), .Y(n4198)
);
XNOR2X1TS U5651 ( .A(n4879), .B(n6030), .Y(n4228) );
OAI22X1TS U5652 ( .A0(n4085), .A1(n4084), .B0(n803), .B1(n4228), .Y(n4197)
);
OAI22X1TS U5653 ( .A0(n6264), .A1(n4086), .B0(n6406), .B1(n4206), .Y(n4196)
);
XNOR2X1TS U5654 ( .A(n8813), .B(n4090), .Y(n4220) );
OAI22X1TS U5655 ( .A0(n816), .A1(n4091), .B0(n735), .B1(n4220), .Y(n4226) );
XNOR2X1TS U5656 ( .A(n6166), .B(n8211), .Y(n4229) );
OAI22X1TS U5657 ( .A0(n4371), .A1(n4092), .B0(n4229), .B1(n4442), .Y(n4225)
);
XNOR2X1TS U5658 ( .A(n5095), .B(n5392), .Y(n4231) );
OAI22X1TS U5659 ( .A0(n6067), .A1(n4093), .B0(n5224), .B1(n4231), .Y(n4224)
);
XNOR2X1TS U5660 ( .A(n4607), .B(n6363), .Y(n4199) );
OAI22X1TS U5661 ( .A0(n4610), .A1(n4097), .B0(n4608), .B1(n4199), .Y(n4215)
);
OAI22X1TS U5662 ( .A0(n4099), .A1(n4098), .B0(n4680), .B1(n4219), .Y(n4214)
);
INVX4TS U5663 ( .A(n6947), .Y(n5226) );
XNOR2X1TS U5664 ( .A(n4916), .B(n5226), .Y(n4256) );
OAI22X1TS U5665 ( .A0(n5391), .A1(n4100), .B0(n5390), .B1(n4256), .Y(n4213)
);
NOR2X1TS U5666 ( .A(n631), .B(n4244), .Y(n4102) );
XNOR2X1TS U5667 ( .A(n6296), .B(n1624), .Y(n4230) );
XNOR2X1TS U5668 ( .A(n5890), .B(n4480), .Y(n4216) );
OAI22X1TS U5669 ( .A0(n4217), .A1(n4105), .B0(n4494), .B1(n4216), .Y(n4210)
);
XNOR2X1TS U5670 ( .A(n703), .B(n5589), .Y(n4242) );
OAI22X1TS U5671 ( .A0(n4243), .A1(n4113), .B0(n787), .B1(n4242), .Y(n4252)
);
XNOR2X1TS U5672 ( .A(n5342), .B(n790), .Y(n4257) );
OAI22X1TS U5673 ( .A0(n6202), .A1(n4117), .B0(n4116), .B1(n4257), .Y(n4250)
);
XNOR2X1TS U5674 ( .A(n824), .B(n4678), .Y(n4246) );
OAI22X1TS U5675 ( .A0(n5796), .A1(n4118), .B0(n4525), .B1(n4246), .Y(n4241)
);
XNOR2X1TS U5676 ( .A(n5633), .B(n747), .Y(n4201) );
OAI22X1TS U5677 ( .A0(n4202), .A1(n4119), .B0(n6023), .B1(n4201), .Y(n4240)
);
XNOR2X1TS U5678 ( .A(n6100), .B(n5207), .Y(n4249) );
OAI22X1TS U5679 ( .A0(n6955), .A1(n4120), .B0(n5414), .B1(n4249), .Y(n4239)
);
CMPR32X2TS U5680 ( .A(n4129), .B(n4128), .C(n4127), .CO(n4138), .S(n4163) );
ADDFHX2TS U5681 ( .A(n4135), .B(n4134), .CI(n4133), .CO(n4136), .S(n4126) );
CMPR32X2TS U5682 ( .A(n4144), .B(n4143), .C(n4142), .CO(n4159), .S(n4048) );
CMPR32X2TS U5683 ( .A(n4150), .B(n4149), .C(n4148), .CO(n4157), .S(n4127) );
CMPR32X2TS U5684 ( .A(n4174), .B(n4173), .C(n4172), .CO(n4287), .S(n4183) );
OAI22X1TS U5685 ( .A0(n875), .A1(n4175), .B0(n4294), .B1(n6414), .Y(n4291)
);
XNOR2X1TS U5686 ( .A(n6329), .B(n4607), .Y(n4334) );
OAI22X1TS U5687 ( .A0(n4610), .A1(n4199), .B0(n4334), .B1(n783), .Y(n4317)
);
OAI22X1TS U5688 ( .A0(n4606), .A1(n4200), .B0(n829), .B1(n4336), .Y(n4316)
);
XNOR2X1TS U5689 ( .A(n5633), .B(n4843), .Y(n4367) );
OAI22X1TS U5690 ( .A0(n4202), .A1(n4201), .B0(n6023), .B1(n4367), .Y(n4315)
);
XNOR2X1TS U5691 ( .A(n4570), .B(n5986), .Y(n4344) );
OAI22X1TS U5692 ( .A0(n4204), .A1(n4203), .B0(n5190), .B1(n4344), .Y(n4333)
);
OAI22X1TS U5693 ( .A0(n6264), .A1(n4206), .B0(n6406), .B1(n4319), .Y(n4332)
);
XNOR2X1TS U5694 ( .A(n630), .B(n2378), .Y(n4373) );
OAI22X1TS U5695 ( .A0(n6850), .A1(n4209), .B0(n6332), .B1(n4373), .Y(n4331)
);
XNOR2X1TS U5696 ( .A(n3103), .B(n4500), .Y(n4324) );
OAI22X1TS U5697 ( .A0(n4217), .A1(n4216), .B0(n4494), .B1(n4324), .Y(n4305)
);
XNOR2X1TS U5698 ( .A(n4218), .B(n6378), .Y(n4339) );
OAI22X1TS U5699 ( .A0(n4613), .A1(n4219), .B0(n4680), .B1(n4339), .Y(n4304)
);
XNOR2X1TS U5700 ( .A(n4419), .B(n753), .Y(n4296) );
OAI22X1TS U5701 ( .A0(n816), .A1(n4220), .B0(n735), .B1(n4296), .Y(n4303) );
CMPR32X2TS U5702 ( .A(n4223), .B(n4222), .C(n4221), .CO(n4326), .S(n4235) );
XNOR2X1TS U5703 ( .A(n7016), .B(n2675), .Y(n4318) );
OAI22X1TS U5704 ( .A0(n6772), .A1(n4227), .B0(n6437), .B1(n4318), .Y(n4308)
);
XNOR2X1TS U5705 ( .A(n4879), .B(n6371), .Y(n4288) );
OAI22X1TS U5706 ( .A0(n4371), .A1(n4229), .B0(n4370), .B1(n8211), .Y(n4306)
);
XNOR2X1TS U5707 ( .A(n8810), .B(n2926), .Y(n4369) );
OAI22X1TS U5708 ( .A0(n6679), .A1(n4230), .B0(n7012), .B1(n4369), .Y(n4365)
);
XNOR2X1TS U5709 ( .A(n5095), .B(n762), .Y(n4346) );
OAI22X1TS U5710 ( .A0(n6067), .A1(n4231), .B0(n5224), .B1(n4346), .Y(n4364)
);
XNOR2X1TS U5711 ( .A(n8209), .B(n5953), .Y(n4320) );
OAI22X1TS U5712 ( .A0(n724), .A1(n4232), .B0(n6073), .B1(n4320), .Y(n4363)
);
XNOR2X1TS U5713 ( .A(n6327), .B(n5662), .Y(n4321) );
OAI22X1TS U5714 ( .A0(n4243), .A1(n4242), .B0(n6794), .B1(n4321), .Y(n4311)
);
OAI22X1TS U5715 ( .A0(n6071), .A1(n4244), .B0(n690), .B1(n4347), .Y(n4310)
);
XNOR2X1TS U5716 ( .A(n5489), .B(n4504), .Y(n4323) );
OAI22X1TS U5717 ( .A0(n4808), .A1(n4245), .B0(n5292), .B1(n4323), .Y(n4309)
);
XNOR2X1TS U5718 ( .A(n825), .B(n4805), .Y(n4366) );
OAI22X1TS U5719 ( .A0(n5796), .A1(n4246), .B0(n5795), .B1(n4366), .Y(n4343)
);
OAI22X1TS U5720 ( .A0(n5667), .A1(n4248), .B0(n4247), .B1(n4338), .Y(n4342)
);
XNOR2X1TS U5721 ( .A(n6208), .B(n5324), .Y(n4368) );
OAI22X1TS U5722 ( .A0(n813), .A1(n4249), .B0(n5414), .B1(n4368), .Y(n4341)
);
CMPR32X2TS U5723 ( .A(n4255), .B(n4254), .C(n4253), .CO(n4298), .S(n4190) );
XNOR2X1TS U5724 ( .A(n4916), .B(n5299), .Y(n4340) );
OAI22X1TS U5725 ( .A0(n717), .A1(n4256), .B0(n786), .B1(n4340), .Y(n4350) );
OAI22X1TS U5726 ( .A0(n6202), .A1(n4257), .B0(n4487), .B1(n4335), .Y(n4349)
);
CMPR32X2TS U5727 ( .A(n4272), .B(n4271), .C(n4270), .CO(n4378), .S(n4273) );
NOR2X8TS U5728 ( .A(n5039), .B(n5040), .Y(n8096) );
CMPR32X2TS U5729 ( .A(n4287), .B(n4286), .C(n4285), .CO(n4742), .S(n4284) );
XNOR2X1TS U5730 ( .A(n3786), .B(n6131), .Y(n4615) );
OAI22X1TS U5731 ( .A0(n4289), .A1(n4288), .B0(n804), .B1(n4615), .Y(n4627)
);
OAI22X1TS U5732 ( .A0(n6104), .A1(n4294), .B0(n4426), .B1(n6414), .Y(n4621)
);
INVX2TS U5733 ( .A(n4621), .Y(n4635) );
OAI22X1TS U5734 ( .A0(n815), .A1(n4296), .B0(n4295), .B1(n4438), .Y(n4634)
);
CMPR32X2TS U5735 ( .A(n4311), .B(n4310), .C(n4309), .CO(n4734), .S(n4358) );
XNOR2X1TS U5736 ( .A(n8214), .B(n4406), .Y(n4471) );
XNOR2X1TS U5737 ( .A(n792), .B(n627), .Y(n4472) );
OAI22X1TS U5738 ( .A0(n6649), .A1(n4319), .B0(n6406), .B1(n4472), .Y(n4457)
);
XNOR2X1TS U5739 ( .A(n6168), .B(n6056), .Y(n4539) );
OAI22X1TS U5740 ( .A0(n699), .A1(n4320), .B0(n6073), .B1(n4539), .Y(n4456)
);
XNOR2X1TS U5741 ( .A(n703), .B(n5602), .Y(n4459) );
XNOR2X1TS U5742 ( .A(n6069), .B(n6335), .Y(n4461) );
OAI22X1TS U5743 ( .A0(n4808), .A1(n4323), .B0(n4322), .B1(n4461), .Y(n4632)
);
BUFX4TS U5744 ( .A(n4581), .Y(n5956) );
XNOR2X1TS U5745 ( .A(n5890), .B(n4678), .Y(n4432) );
OAI22X1TS U5746 ( .A0(n5956), .A1(n4324), .B0(n4494), .B1(n4432), .Y(n4631)
);
CMPR32X2TS U5747 ( .A(n4330), .B(n4329), .C(n4328), .CO(n4760), .S(n4300) );
OAI22X1TS U5748 ( .A0(n4610), .A1(n4334), .B0(n4609), .B1(n2270), .Y(n4470)
);
XNOR2X1TS U5749 ( .A(n5342), .B(n4420), .Y(n4460) );
OAI22X2TS U5750 ( .A0(n702), .A1(n4335), .B0(n5480), .B1(n4460), .Y(n4469)
);
XNOR2X1TS U5751 ( .A(n4415), .B(n4480), .Y(n4605) );
OAI22X1TS U5752 ( .A0(n2457), .A1(n4336), .B0(n829), .B1(n4605), .Y(n4468)
);
XNOR2X1TS U5753 ( .A(n755), .B(n5226), .Y(n4435) );
OAI22X1TS U5754 ( .A0(n809), .A1(n4338), .B0(n5475), .B1(n4435), .Y(n4639)
);
XNOR2X1TS U5755 ( .A(n4218), .B(n6363), .Y(n4612) );
OAI22X1TS U5756 ( .A0(n4613), .A1(n4339), .B0(n4680), .B1(n4612), .Y(n4638)
);
XNOR2X1TS U5757 ( .A(n4916), .B(n5409), .Y(n4617) );
OAI22X1TS U5758 ( .A0(n5535), .A1(n4340), .B0(n786), .B1(n4617), .Y(n4637)
);
CMPR32X2TS U5759 ( .A(n4343), .B(n4342), .C(n4341), .CO(n4733), .S(n4357) );
XNOR2X1TS U5760 ( .A(n4570), .B(n6030), .Y(n4430) );
OAI22X1TS U5761 ( .A0(n5191), .A1(n4344), .B0(n5190), .B1(n4430), .Y(n4467)
);
BUFX12TS U5762 ( .A(n4345), .Y(n6859) );
XNOR2X1TS U5763 ( .A(n6143), .B(n5589), .Y(n4530) );
OAI22X1TS U5764 ( .A0(n6149), .A1(n4346), .B0(n6145), .B1(n4530), .Y(n4466)
);
XNOR2X1TS U5765 ( .A(n6222), .B(n5892), .Y(n4537) );
OAI22X1TS U5766 ( .A0(n781), .A1(n4347), .B0(n690), .B1(n4537), .Y(n4465) );
CMPR32X2TS U5767 ( .A(n4365), .B(n4364), .C(n4363), .CO(n4739), .S(n4360) );
XNOR2X1TS U5768 ( .A(n824), .B(n6775), .Y(n4526) );
OAI22X1TS U5769 ( .A0(n5796), .A1(n4366), .B0(n4525), .B1(n4526), .Y(n4588)
);
OAI22X1TS U5770 ( .A0(n6478), .A1(n4367), .B0(n6023), .B1(n4473), .Y(n4587)
);
XNOR2X1TS U5771 ( .A(n6100), .B(n5392), .Y(n4528) );
OAI22X1TS U5772 ( .A0(n813), .A1(n4368), .B0(n5414), .B1(n4528), .Y(n4586)
);
OAI22X1TS U5773 ( .A0(n4780), .A1(n4369), .B0(n7012), .B1(n4535), .Y(n4648)
);
OAI22X1TS U5774 ( .A0(n4371), .A1(n801), .B0(n4370), .B1(n4441), .Y(n4647)
);
XNOR2X1TS U5775 ( .A(n4883), .B(n4372), .Y(n4440) );
OAI22X1TS U5776 ( .A0(n6850), .A1(n4373), .B0(n6179), .B1(n4440), .Y(n4646)
);
ADDFHX4TS U5777 ( .A(n4388), .B(n4387), .CI(n4386), .CO(n5036), .S(n5032) );
ADDFHX4TS U5778 ( .A(n4391), .B(n4390), .CI(n4389), .CO(n4403), .S(n4387) );
ADDFHX2TS U5779 ( .A(n4394), .B(n4393), .CI(n4392), .CO(n4261), .S(n4402) );
XNOR2X1TS U5780 ( .A(n6329), .B(n811), .Y(n4611) );
XNOR2X1TS U5781 ( .A(n6166), .B(n811), .Y(n4559) );
OAI22X1TS U5782 ( .A0(n4613), .A1(n4611), .B0(n4559), .B1(n4845), .Y(n4446)
);
XNOR2X1TS U5783 ( .A(n4883), .B(n4405), .Y(n4439) );
OAI22X1TS U5784 ( .A0(n6646), .A1(n4439), .B0(n6179), .B1(n4554), .Y(n4445)
);
XNOR2X1TS U5785 ( .A(n823), .B(n6823), .Y(n4524) );
XNOR2X1TS U5786 ( .A(n825), .B(n5226), .Y(n4409) );
OAI22X1TS U5787 ( .A0(n5677), .A1(n4524), .B0(n3165), .B1(n4409), .Y(n4444)
);
XNOR2X1TS U5788 ( .A(n4570), .B(n6131), .Y(n4410) );
XNOR2X1TS U5789 ( .A(n741), .B(n6378), .Y(n4571) );
OAI22X1TS U5790 ( .A0(n5191), .A1(n4410), .B0(n4408), .B1(n4571), .Y(n4566)
);
XNOR2X1TS U5791 ( .A(n4916), .B(n5604), .Y(n4414) );
XNOR2X1TS U5792 ( .A(n4916), .B(n5660), .Y(n4518) );
OAI22X1TS U5793 ( .A0(n5391), .A1(n4414), .B0(n786), .B1(n4518), .Y(n4565)
);
XNOR2X1TS U5794 ( .A(n755), .B(n5409), .Y(n4411) );
INVX4TS U5795 ( .A(n7027), .Y(n5520) );
XNOR2X1TS U5796 ( .A(n756), .B(n5520), .Y(n4580) );
OAI22X1TS U5797 ( .A0(n5667), .A1(n4411), .B0(n5475), .B1(n4580), .Y(n4564)
);
XNOR2X1TS U5798 ( .A(n823), .B(n5299), .Y(n4662) );
OAI22X1TS U5799 ( .A0(n4835), .A1(n4409), .B0(n4661), .B1(n4662), .Y(n4676)
);
XNOR2X1TS U5800 ( .A(n8213), .B(n6363), .Y(n4413) );
XNOR2X1TS U5801 ( .A(n6329), .B(n4879), .Y(n4684) );
OAI22X1TS U5802 ( .A0(n4880), .A1(n4413), .B0(n4684), .B1(n804), .Y(n4675)
);
XNOR2X1TS U5803 ( .A(n5342), .B(n820), .Y(n4486) );
XNOR2X1TS U5804 ( .A(n5342), .B(n4841), .Y(n4573) );
OAI22X1TS U5805 ( .A0(n6381), .A1(n4486), .B0(n5480), .B1(n4573), .Y(n4674)
);
XNOR2X1TS U5806 ( .A(n4570), .B(n6371), .Y(n4429) );
OAI22X1TS U5807 ( .A0(n5191), .A1(n4429), .B0(n5190), .B1(n4410), .Y(n4449)
);
OAI22X1TS U5808 ( .A0(n4436), .A1(n4433), .B0(n4434), .B1(n4411), .Y(n4448)
);
XNOR2X1TS U5809 ( .A(n5567), .B(n4805), .Y(n4431) );
XNOR2X1TS U5810 ( .A(n4848), .B(n6775), .Y(n4495) );
OAI22X1TS U5811 ( .A0(n5956), .A1(n4431), .B0(n4494), .B1(n4495), .Y(n4447)
);
OAI22X1TS U5812 ( .A0(n812), .A1(n4534), .B0(n7012), .B1(n4417), .Y(n4484)
);
XNOR2X1TS U5813 ( .A(n4412), .B(n6378), .Y(n4614) );
OAI22X1TS U5814 ( .A0(n4880), .A1(n4614), .B0(n803), .B1(n4413), .Y(n4483)
);
XNOR2X1TS U5815 ( .A(n4916), .B(n5520), .Y(n4616) );
OAI22X1TS U5816 ( .A0(n5391), .A1(n4616), .B0(n5390), .B1(n4414), .Y(n4482)
);
XNOR2X1TS U5817 ( .A(n6054), .B(n4678), .Y(n4485) );
XNOR2X1TS U5818 ( .A(n5132), .B(n4805), .Y(n4520) );
OAI22X1TS U5819 ( .A0(n6429), .A1(n4485), .B0(n6428), .B1(n4520), .Y(n4512)
);
OAI22X1TS U5820 ( .A0(n6104), .A1(n4425), .B0(n4416), .B1(n6414), .Y(n4585)
);
OAI22X1TS U5821 ( .A0(n875), .A1(n4416), .B0(n4513), .B1(n6414), .Y(n4584)
);
OAI22X2TS U5822 ( .A0(n4780), .A1(n4417), .B0(n7012), .B1(n4670), .Y(n4583)
);
XNOR2X1TS U5823 ( .A(n5874), .B(n4420), .Y(n4505) );
INVX2TS U5824 ( .A(n4585), .Y(n4422) );
OAI22X1TS U5825 ( .A0(n4610), .A1(n4607), .B0(n783), .B1(n4555), .Y(n4421)
);
INVX12TS U5826 ( .A(n4938), .Y(n5860) );
OAI22X1TS U5827 ( .A0(n875), .A1(n4426), .B0(n4425), .B1(n5860), .Y(n4620)
);
OAI22X1TS U5828 ( .A0(n5191), .A1(n4430), .B0(n5190), .B1(n4429), .Y(n4464)
);
OAI22X1TS U5829 ( .A0(n4436), .A1(n4435), .B0(n4434), .B1(n4433), .Y(n4462)
);
OAI22X1TS U5830 ( .A0(n5350), .A1(n4438), .B0(n4685), .B1(n4437), .Y(n4591)
);
OAI22X1TS U5831 ( .A0(n6850), .A1(n4440), .B0(n6179), .B1(n4439), .Y(n4590)
);
CMPR32X2TS U5832 ( .A(n4449), .B(n4448), .C(n4447), .CO(n4694), .S(n4474) );
CMPR32X2TS U5833 ( .A(n4452), .B(n4451), .C(n4450), .CO(n4857), .S(n4453) );
XNOR2X1TS U5834 ( .A(n703), .B(n5792), .Y(n4496) );
XNOR2X1TS U5835 ( .A(n5342), .B(n4504), .Y(n4488) );
OAI22X1TS U5836 ( .A0(n6463), .A1(n4460), .B0(n5480), .B1(n4488), .Y(n4542)
);
XNOR2X1TS U5837 ( .A(n818), .B(n4841), .Y(n4489) );
OAI22X1TS U5838 ( .A0(n4808), .A1(n4461), .B0(n6456), .B1(n4489), .Y(n4541)
);
XNOR2X1TS U5839 ( .A(n7016), .B(n4553), .Y(n4544) );
OAI22X1TS U5840 ( .A0(n6772), .A1(n4471), .B0(n6437), .B1(n4544), .Y(n4479)
);
XNOR2X1TS U5841 ( .A(n792), .B(n4843), .Y(n4545) );
OAI22X1TS U5842 ( .A0(n6264), .A1(n4472), .B0(n6406), .B1(n4545), .Y(n4478)
);
XNOR2X1TS U5843 ( .A(n5633), .B(n2926), .Y(n4547) );
OAI22X1TS U5844 ( .A0(n5113), .A1(n4473), .B0(n5711), .B1(n4547), .Y(n4477)
);
CMPR32X2TS U5845 ( .A(n4479), .B(n4478), .C(n4477), .CO(n4600), .S(n4704) );
OAI22X1TS U5846 ( .A0(n704), .A1(n4481), .B0(n5130), .B1(n4501), .Y(n4492)
);
XNOR2X1TS U5847 ( .A(n6690), .B(n5589), .Y(n4506) );
OAI22X1TS U5848 ( .A0(n6099), .A1(n4527), .B0(n6254), .B1(n4506), .Y(n4491)
);
XNOR2X1TS U5849 ( .A(n6143), .B(n5662), .Y(n4529) );
OAI22X1TS U5850 ( .A0(n6225), .A1(n4529), .B0(n6145), .B1(n4502), .Y(n4490)
);
CMPR32X2TS U5851 ( .A(n4484), .B(n4483), .C(n4482), .CO(n4693), .S(n4598) );
OAI22X1TS U5852 ( .A0(n702), .A1(n4488), .B0(n4487), .B1(n4486), .Y(n4532)
);
OAI22X1TS U5853 ( .A0(n4808), .A1(n4489), .B0(n5292), .B1(n4493), .Y(n4531)
);
XNOR2X1TS U5854 ( .A(n819), .B(Op_MY[34]), .Y(n4519) );
OAI22X1TS U5855 ( .A0(n4808), .A1(n4493), .B0(n6456), .B1(n4519), .Y(n4569)
);
XNOR2X1TS U5856 ( .A(n8805), .B(n790), .Y(n4498) );
XNOR2X1TS U5857 ( .A(n778), .B(n6400), .Y(n4572) );
OAI22X1TS U5858 ( .A0(n4115), .A1(n4498), .B0(n4907), .B1(n4572), .Y(n4568)
);
XNOR2X1TS U5859 ( .A(n4848), .B(n5129), .Y(n4582) );
OAI22X1TS U5860 ( .A0(n5956), .A1(n4495), .B0(n4494), .B1(n4582), .Y(n4567)
);
XNOR2X1TS U5861 ( .A(n4797), .B(n5892), .Y(n4558) );
OAI22X1TS U5862 ( .A0(n6156), .A1(n4496), .B0(n6794), .B1(n4558), .Y(n4523)
);
XNOR2X1TS U5863 ( .A(n4813), .B(n5953), .Y(n4536) );
OAI22X1TS U5864 ( .A0(n6071), .A1(n4536), .B0(n631), .B1(n4503), .Y(n4522)
);
XNOR2X1TS U5865 ( .A(n779), .B(n643), .Y(n4538) );
OAI22X1TS U5866 ( .A0(n4540), .A1(n4538), .B0(n4499), .B1(n4498), .Y(n4521)
);
XNOR2X1TS U5867 ( .A(n5880), .B(n4500), .Y(n4679) );
OAI22X1TS U5868 ( .A0(n6225), .A1(n4502), .B0(n6145), .B1(n4672), .Y(n4516)
);
XNOR2X1TS U5869 ( .A(n6662), .B(n643), .Y(n4688) );
OAI22X1TS U5870 ( .A0(n3127), .A1(n4503), .B0(n690), .B1(n4688), .Y(n4515)
);
XNOR2X1TS U5871 ( .A(n708), .B(n4504), .Y(n4686) );
OAI22X1TS U5872 ( .A0(n5350), .A1(n4505), .B0(n5720), .B1(n4686), .Y(n4576)
);
XNOR2X1TS U5873 ( .A(n5633), .B(n5207), .Y(n4546) );
XNOR2X1TS U5874 ( .A(n5633), .B(n5324), .Y(n4673) );
OAI22X1TS U5875 ( .A0(n5113), .A1(n4546), .B0(n5711), .B1(n4673), .Y(n4575)
);
XNOR2X1TS U5876 ( .A(n5503), .B(n5662), .Y(n4664) );
OAI22X1TS U5877 ( .A0(n813), .A1(n4506), .B0(n6254), .B1(n4664), .Y(n4574)
);
BUFX12TS U5878 ( .A(n6104), .Y(n6127) );
XNOR2X1TS U5879 ( .A(n698), .B(n4843), .Y(n4551) );
XNOR2X1TS U5880 ( .A(n638), .B(n5953), .Y(n4557) );
OAI22X1TS U5881 ( .A0(n6156), .A1(n4557), .B0(n6794), .B1(n4798), .Y(n4773)
);
XNOR2X1TS U5882 ( .A(n4916), .B(n5684), .Y(n4851) );
OAI22X1TS U5883 ( .A0(n5391), .A1(n4518), .B0(n786), .B1(n4851), .Y(n4833)
);
XNOR2X1TS U5884 ( .A(n8224), .B(n5203), .Y(n4807) );
OAI22X1TS U5885 ( .A0(n4808), .A1(n4519), .B0(n5292), .B1(n4807), .Y(n4832)
);
XNOR2X1TS U5886 ( .A(n6054), .B(n6775), .Y(n4804) );
OAI22X1TS U5887 ( .A0(n6429), .A1(n4520), .B0(n829), .B1(n4804), .Y(n4831)
);
CMPR32X2TS U5888 ( .A(n4523), .B(n4522), .C(n4521), .CO(n4660), .S(n4597) );
OAI22X1TS U5889 ( .A0(n5796), .A1(n4526), .B0(n4525), .B1(n4524), .Y(n4654)
);
OAI22X1TS U5890 ( .A0(n6067), .A1(n4530), .B0(n6145), .B1(n4529), .Y(n4652)
);
OAI22X1TS U5891 ( .A0(n4055), .A1(n4535), .B0(n7012), .B1(n4534), .Y(n4594)
);
OAI22X1TS U5892 ( .A0(n6071), .A1(n4537), .B0(n631), .B1(n4536), .Y(n4593)
);
OAI22X1TS U5893 ( .A0(n4540), .A1(n4539), .B0(n6073), .B1(n4538), .Y(n4592)
);
XNOR2X1TS U5894 ( .A(n821), .B(n627), .Y(n4552) );
OAI22X1TS U5895 ( .A0(n7174), .A1(n4544), .B0(n6437), .B1(n4552), .Y(n4550)
);
XNOR2X1TS U5896 ( .A(n792), .B(n4882), .Y(n4560) );
OAI22X1TS U5897 ( .A0(n6443), .A1(n4545), .B0(n6406), .B1(n4560), .Y(n4549)
);
OAI22X1TS U5898 ( .A0(n5113), .A1(n4547), .B0(n5711), .B1(n4546), .Y(n4548)
);
OAI22X1TS U5899 ( .A0(n6886), .A1(n4552), .B0(n6437), .B1(n4551), .Y(n4667)
);
XNOR2X1TS U5900 ( .A(n5893), .B(n4553), .Y(n4683) );
OAI22X1TS U5901 ( .A0(n6850), .A1(n4554), .B0(n6179), .B1(n4683), .Y(n4666)
);
OAI22X1TS U5902 ( .A0(n6156), .A1(n4558), .B0(n6794), .B1(n4557), .Y(n4579)
);
OAI22X1TS U5903 ( .A0(n4613), .A1(n4559), .B0(n4680), .B1(n4681), .Y(n4578)
);
XNOR2X1TS U5904 ( .A(n794), .B(n2926), .Y(n4663) );
OAI22X1TS U5905 ( .A0(n5302), .A1(n4560), .B0(n5877), .B1(n4663), .Y(n4577)
);
CMPR32X2TS U5906 ( .A(n4563), .B(n4562), .C(n4561), .CO(n4793), .S(n4601) );
XNOR2X1TS U5907 ( .A(n4570), .B(n6363), .Y(n4847) );
OAI22X1TS U5908 ( .A0(n5191), .A1(n4571), .B0(n5190), .B1(n4847), .Y(n4830)
);
INVX6TS U5909 ( .A(n6227), .Y(n6333) );
XNOR2X1TS U5910 ( .A(n8209), .B(n6333), .Y(n4815) );
OAI22X1TS U5911 ( .A0(n4540), .A1(n4572), .B0(n5715), .B1(n4815), .Y(n4829)
);
XNOR2X1TS U5912 ( .A(n5342), .B(n4888), .Y(n4812) );
OAI22X1TS U5913 ( .A0(n702), .A1(n4573), .B0(n5480), .B1(n4812), .Y(n4828)
);
CMPR32X2TS U5914 ( .A(n4576), .B(n4575), .C(n4574), .CO(n4769), .S(n4658) );
CMPR32X2TS U5915 ( .A(n4579), .B(n4578), .C(n4577), .CO(n4768), .S(n4561) );
XNOR2X1TS U5916 ( .A(n756), .B(n5604), .Y(n4837) );
OAI22X1TS U5917 ( .A0(n4436), .A1(n4580), .B0(n5475), .B1(n4837), .Y(n4818)
);
XNOR2X1TS U5918 ( .A(n4848), .B(n5226), .Y(n4849) );
OAI22X1TS U5919 ( .A0(n5891), .A1(n4582), .B0(n5889), .B1(n4849), .Y(n4817)
);
CMPR32X2TS U5920 ( .A(n4585), .B(n4584), .C(n4583), .CO(n4816), .S(n4511) );
CMPR32X2TS U5921 ( .A(n4588), .B(n4587), .C(n4586), .CO(n4712), .S(n4738) );
CMPR32X2TS U5922 ( .A(n4600), .B(n4599), .C(n4598), .CO(n4657), .S(n4713) );
OAI22X2TS U5923 ( .A0(n6429), .A1(n4605), .B0(n827), .B1(n4604), .Y(n4651)
);
OAI22X1TS U5924 ( .A0(n4613), .A1(n4612), .B0(n4611), .B1(n4845), .Y(n4649)
);
OAI22X1TS U5925 ( .A0(n4880), .A1(n4615), .B0(n803), .B1(n4614), .Y(n4630)
);
OAI22X1TS U5926 ( .A0(n718), .A1(n4617), .B0(n786), .B1(n4616), .Y(n4629) );
CMPR32X2TS U5927 ( .A(n4621), .B(n4620), .C(n4619), .CO(n4623), .S(n4628) );
CMPR32X2TS U5928 ( .A(n4627), .B(n4626), .C(n4625), .CO(n4748), .S(n4741) );
CMPR32X2TS U5929 ( .A(n4648), .B(n4647), .C(n4646), .CO(n4730), .S(n4737) );
CMPR32X2TS U5930 ( .A(n4651), .B(n4650), .C(n4649), .CO(n4691), .S(n4729) );
CMPR32X2TS U5931 ( .A(n4660), .B(n4659), .C(n4658), .CO(n4854), .S(n4655) );
XNOR2X1TS U5932 ( .A(n8812), .B(n5409), .Y(n4834) );
OAI22X1TS U5933 ( .A0(n4835), .A1(n4662), .B0(n4661), .B1(n4834), .Y(n4772)
);
XNOR2X1TS U5934 ( .A(n792), .B(n5207), .Y(n4799) );
OAI22X1TS U5935 ( .A0(n5302), .A1(n4663), .B0(n5877), .B1(n4799), .Y(n4771)
);
XNOR2X1TS U5936 ( .A(n6100), .B(n5602), .Y(n4778) );
OAI22X1TS U5937 ( .A0(n6309), .A1(n4664), .B0(n6254), .B1(n4778), .Y(n4770)
);
XNOR2X1TS U5938 ( .A(n6987), .B(n5589), .Y(n4779) );
OAI22X1TS U5939 ( .A0(n812), .A1(n4670), .B0(n6677), .B1(n4779), .Y(n4811)
);
OAI22X1TS U5940 ( .A0(n6225), .A1(n4672), .B0(n6145), .B1(n4781), .Y(n4810)
);
XNOR2X1TS U5941 ( .A(n5633), .B(n5392), .Y(n4800) );
OAI22X1TS U5942 ( .A0(n5113), .A1(n4673), .B0(n5711), .B1(n4800), .Y(n4809)
);
CMPR32X2TS U5943 ( .A(n4676), .B(n4675), .C(n4674), .CO(n4766), .S(n4450) );
XNOR2X1TS U5944 ( .A(n705), .B(n4678), .Y(n4806) );
OAI22X1TS U5945 ( .A0(n1663), .A1(n4679), .B0(n5130), .B1(n4806), .Y(n4840)
);
OAI22X1TS U5946 ( .A0(n4682), .A1(n4681), .B0(n4680), .B1(n957), .Y(n4839)
);
XNOR2X1TS U5947 ( .A(n4883), .B(n746), .Y(n4844) );
OAI22X1TS U5948 ( .A0(n6850), .A1(n4683), .B0(n6179), .B1(n4844), .Y(n4838)
);
XNOR2X1TS U5949 ( .A(n6166), .B(n4879), .Y(n4836) );
OAI22X1TS U5950 ( .A0(n4880), .A1(n4684), .B0(n4836), .B1(n804), .Y(n4803)
);
OAI22X1TS U5951 ( .A0(n5350), .A1(n4686), .B0(n4685), .B1(n4842), .Y(n4802)
);
XNOR2X1TS U5952 ( .A(n791), .B(n790), .Y(n4814) );
OAI22X1TS U5953 ( .A0(n6487), .A1(n4688), .B0(n4687), .B1(n4814), .Y(n4801)
);
CMPR32X2TS U5954 ( .A(n4694), .B(n4693), .C(n4692), .CO(n4856), .S(n4699) );
CMPR32X2TS U5955 ( .A(n4706), .B(n4705), .C(n4704), .CO(n4702), .S(n4757) );
CMPR32X2TS U5956 ( .A(n4709), .B(n4708), .C(n4707), .CO(n4756), .S(n4743) );
CMPR32X2TS U5957 ( .A(n4712), .B(n4711), .C(n4710), .CO(n4715), .S(n4755) );
CMPR32X2TS U5958 ( .A(n4724), .B(n4723), .C(n4722), .CO(n4754), .S(n4759) );
CMPR32X2TS U5959 ( .A(n4730), .B(n4729), .C(n4728), .CO(n4695), .S(n4752) );
CMPR32X2TS U5960 ( .A(n4733), .B(n4732), .C(n4731), .CO(n4982), .S(n4758) );
CMPR32X2TS U5961 ( .A(n4739), .B(n4738), .C(n4737), .CO(n4980), .S(n4977) );
CMPR32X2TS U5962 ( .A(n4742), .B(n4741), .C(n4740), .CO(n4967), .S(n4984) );
CMPR32X2TS U5963 ( .A(n4748), .B(n4747), .C(n4746), .CO(n4750), .S(n4965) );
CMPR32X2TS U5964 ( .A(n4751), .B(n4750), .C(n4749), .CO(n4719), .S(n4991) );
CMPR32X2TS U5965 ( .A(n4760), .B(n4759), .C(n4758), .CO(n4971), .S(n4968) );
CMPR32X2TS U5966 ( .A(n4766), .B(n4765), .C(n4764), .CO(n4923), .S(n4852) );
CMPR32X2TS U5967 ( .A(n4769), .B(n4768), .C(n4767), .CO(n4922), .S(n4791) );
OAI22X1TS U5968 ( .A0(n6104), .A1(n4776), .B0(n4939), .B1(n681), .Y(n4935)
);
XNOR2X1TS U5969 ( .A(n698), .B(n5090), .Y(n4940) );
XNOR2X1TS U5970 ( .A(n6100), .B(n5792), .Y(n4895) );
XNOR2X1TS U5971 ( .A(n6987), .B(n5662), .Y(n4881) );
OAI22X1TS U5972 ( .A0(n4055), .A1(n4779), .B0(n6677), .B1(n4881), .Y(n4900)
);
XNOR2X1TS U5973 ( .A(n6143), .B(n5953), .Y(n4890) );
OAI22X1TS U5974 ( .A0(n6225), .A1(n4781), .B0(n6145), .B1(n4890), .Y(n4899)
);
CMPR32X2TS U5975 ( .A(n4784), .B(n4783), .C(n4782), .CO(n4947), .S(n4788) );
CMPR32X2TS U5976 ( .A(n4796), .B(n4795), .C(n4794), .CO(n4952), .S(n4853) );
OAI22X1TS U5977 ( .A0(n6156), .A1(n4798), .B0(n787), .B1(n4893), .Y(n4904)
);
XNOR2X1TS U5978 ( .A(n792), .B(n5324), .Y(n4891) );
OAI22X1TS U5979 ( .A0(n5302), .A1(n4799), .B0(n5877), .B1(n4891), .Y(n4903)
);
XNOR2X1TS U5980 ( .A(n5633), .B(n762), .Y(n4894) );
OAI22X1TS U5981 ( .A0(n5113), .A1(n4800), .B0(n5711), .B1(n4894), .Y(n4902)
);
XNOR2X1TS U5982 ( .A(n6054), .B(n6823), .Y(n4918) );
XNOR2X1TS U5983 ( .A(n5880), .B(n4805), .Y(n4906) );
OAI22X1TS U5984 ( .A0(n1663), .A1(n4806), .B0(n3928), .B1(n4906), .Y(n4911)
);
XNOR2X1TS U5985 ( .A(n8224), .B(n5348), .Y(n4915) );
OAI22X1TS U5986 ( .A0(n4808), .A1(n4807), .B0(n5292), .B1(n4915), .Y(n4910)
);
CMPR32X2TS U5987 ( .A(n4811), .B(n4810), .C(n4809), .CO(n4872), .S(n4794) );
XNOR2X1TS U5988 ( .A(n5342), .B(Op_MY[34]), .Y(n4914) );
OAI22X1TS U5989 ( .A0(n6202), .A1(n4812), .B0(n5480), .B1(n4914), .Y(n4875)
);
XNOR2X1TS U5990 ( .A(n6222), .B(n6400), .Y(n4909) );
OAI22X1TS U5991 ( .A0(n3127), .A1(n4814), .B0(n5228), .B1(n4909), .Y(n4874)
);
INVX6TS U5992 ( .A(n6237), .Y(n6403) );
XNOR2X1TS U5993 ( .A(n4497), .B(n6403), .Y(n4908) );
OAI22X1TS U5994 ( .A0(n4540), .A1(n4815), .B0(n5715), .B1(n4908), .Y(n4873)
);
CMPR32X2TS U5995 ( .A(n4818), .B(n4817), .C(n4816), .CO(n4870), .S(n4767) );
XNOR2X1TS U5996 ( .A(n8812), .B(n5520), .Y(n4937) );
OAI22X1TS U5997 ( .A0(n4835), .A1(n4834), .B0(n3165), .B1(n4937), .Y(n4887)
);
OAI22X1TS U5998 ( .A0(n4880), .A1(n4836), .B0(n804), .B1(n8213), .Y(n4886)
);
XNOR2X1TS U5999 ( .A(n756), .B(n5660), .Y(n4933) );
OAI22X1TS U6000 ( .A0(n809), .A1(n4837), .B0(n5475), .B1(n4933), .Y(n4885)
);
OAI22X1TS U6001 ( .A0(n5350), .A1(n4842), .B0(n5720), .B1(n4889), .Y(n4878)
);
XNOR2X1TS U6002 ( .A(n4883), .B(n4843), .Y(n4884) );
OAI22X1TS U6003 ( .A0(n6850), .A1(n4844), .B0(n6179), .B1(n4884), .Y(n4877)
);
XNOR2X1TS U6004 ( .A(n741), .B(n6329), .Y(n4913) );
OAI22X1TS U6005 ( .A0(n5191), .A1(n4847), .B0(n4913), .B1(n5327), .Y(n4932)
);
XNOR2X1TS U6006 ( .A(n4848), .B(n5299), .Y(n4920) );
OAI22X1TS U6007 ( .A0(n5135), .A1(n4849), .B0(n4919), .B1(n4920), .Y(n4931)
);
XNOR2X1TS U6008 ( .A(n4850), .B(n5689), .Y(n4917) );
OAI22X1TS U6009 ( .A0(n5391), .A1(n4851), .B0(n5390), .B1(n4917), .Y(n4930)
);
CMPR32X2TS U6010 ( .A(n4854), .B(n4853), .C(n4852), .CO(n4865), .S(n4859) );
NOR2X6TS U6011 ( .A(n5057), .B(n5058), .Y(n7360) );
CMPR32X2TS U6012 ( .A(n4872), .B(n4871), .C(n4870), .CO(n5109), .S(n4950) );
OAI22X1TS U6013 ( .A0(n4880), .A1(n8213), .B0(n803), .B1(n5092), .Y(n5076)
);
XNOR2X1TS U6014 ( .A(n6296), .B(n5602), .Y(n5117) );
OAI22X1TS U6015 ( .A0(n7013), .A1(n4881), .B0(n6677), .B1(n5117), .Y(n5075)
);
XNOR2X1TS U6016 ( .A(n4883), .B(n2878), .Y(n5091) );
OAI22X1TS U6017 ( .A0(n6719), .A1(n4884), .B0(n6179), .B1(n5091), .Y(n5074)
);
CMPR32X2TS U6018 ( .A(n4887), .B(n4886), .C(n4885), .CO(n5141), .S(n4924) );
XNOR2X1TS U6019 ( .A(n5784), .B(n4888), .Y(n5094) );
OAI22X1TS U6020 ( .A0(n5350), .A1(n4889), .B0(n5720), .B1(n5094), .Y(n5088)
);
XNOR2X1TS U6021 ( .A(n5095), .B(n6056), .Y(n5096) );
OAI22X1TS U6022 ( .A0(n6225), .A1(n4890), .B0(n6145), .B1(n5096), .Y(n5087)
);
XNOR2X1TS U6023 ( .A(n793), .B(n5392), .Y(n5097) );
OAI22X1TS U6024 ( .A0(n5302), .A1(n4891), .B0(n5877), .B1(n5097), .Y(n5086)
);
XNOR2X1TS U6025 ( .A(n4797), .B(n6133), .Y(n5110) );
OAI22X1TS U6026 ( .A0(n6156), .A1(n4893), .B0(n4892), .B1(n5110), .Y(n5116)
);
OAI22X1TS U6027 ( .A0(n6309), .A1(n4895), .B0(n6254), .B1(n5111), .Y(n5114)
);
CMPR32X2TS U6028 ( .A(n4898), .B(n4897), .C(n4896), .CO(n5103), .S(n4953) );
XNOR2X1TS U6029 ( .A(n706), .B(n6775), .Y(n5131) );
OAI22X1TS U6030 ( .A0(n6455), .A1(n4906), .B0(n5130), .B1(n5131), .Y(n5125)
);
XNOR2X1TS U6031 ( .A(n4497), .B(n3986), .Y(n5118) );
OAI22X1TS U6032 ( .A0(n699), .A1(n4908), .B0(n4907), .B1(n5118), .Y(n5124)
);
XNOR2X1TS U6033 ( .A(n791), .B(n6333), .Y(n5119) );
OAI22X1TS U6034 ( .A0(n781), .A1(n4909), .B0(n5981), .B1(n5119), .Y(n5123)
);
CMPR32X2TS U6035 ( .A(n4912), .B(n4911), .C(n4910), .CO(n5122), .S(n4927) );
OAI22X1TS U6036 ( .A0(n5191), .A1(n4913), .B0(n5126), .B1(n5327), .Y(n5144)
);
XNOR2X1TS U6037 ( .A(n5342), .B(n5203), .Y(n5127) );
OAI22X1TS U6038 ( .A0(n6463), .A1(n4914), .B0(n5480), .B1(n5127), .Y(n5143)
);
XNOR2X1TS U6039 ( .A(n8224), .B(n5440), .Y(n5128) );
OAI22X1TS U6040 ( .A0(n6109), .A1(n4915), .B0(n5292), .B1(n5128), .Y(n5142)
);
XNOR2X1TS U6041 ( .A(n4916), .B(n5879), .Y(n5148) );
OAI22X1TS U6042 ( .A0(n5391), .A1(n4917), .B0(n5390), .B1(n5148), .Y(n5082)
);
XNOR2X1TS U6043 ( .A(n5132), .B(n5226), .Y(n5133) );
OAI22X1TS U6044 ( .A0(n5305), .A1(n4918), .B0(n826), .B1(n5133), .Y(n5081)
);
XNOR2X1TS U6045 ( .A(n8804), .B(n5409), .Y(n5134) );
OAI22X1TS U6046 ( .A0(n5135), .A1(n4920), .B0(n5889), .B1(n5134), .Y(n5080)
);
CMPR32X2TS U6047 ( .A(n4926), .B(n4925), .C(n4924), .CO(n5070), .S(n4954) );
CMPR32X2TS U6048 ( .A(n4932), .B(n4931), .C(n4930), .CO(n5100), .S(n4896) );
XNOR2X1TS U6049 ( .A(n756), .B(n5684), .Y(n5149) );
OAI22X1TS U6050 ( .A0(n809), .A1(n4933), .B0(n5475), .B1(n5149), .Y(n5147)
);
XNOR2X1TS U6051 ( .A(n8812), .B(n5604), .Y(n5151) );
OAI22X1TS U6052 ( .A0(n5677), .A1(n4937), .B0(n3165), .B1(n5151), .Y(n5079)
);
INVX2TS U6053 ( .A(n5188), .Y(n5078) );
XNOR2X1TS U6054 ( .A(n821), .B(n5207), .Y(n5089) );
OAI22X1TS U6055 ( .A0(n6772), .A1(n4940), .B0(n6021), .B1(n5089), .Y(n5077)
);
NOR2X8TS U6056 ( .A(n5059), .B(n5060), .Y(n7366) );
ADDFHX4TS U6057 ( .A(n4961), .B(n4960), .CI(n4959), .CO(n5047), .S(n5042) );
ADDFHX4TS U6058 ( .A(n4964), .B(n4963), .CI(n4962), .CO(n5006), .S(n4959) );
CMPR32X2TS U6059 ( .A(n4982), .B(n4981), .C(n4980), .CO(n4999), .S(n4996) );
ADDFHX2TS U6060 ( .A(n4985), .B(n4984), .CI(n4983), .CO(n4995), .S(n4987) );
ADDFHX4TS U6061 ( .A(n5006), .B(n5005), .CI(n5004), .CO(n5049), .S(n5048) );
NOR2X8TS U6062 ( .A(n5050), .B(n5049), .Y(n8129) );
ADDFHX2TS U6063 ( .A(n5012), .B(n5011), .CI(n5010), .CO(n4819), .S(n5024) );
NOR2X8TS U6064 ( .A(n5054), .B(n5053), .Y(n8083) );
NOR2X6TS U6065 ( .A(n7356), .B(n8083), .Y(n5056) );
NOR2X2TS U6066 ( .A(n8123), .B(n5062), .Y(n5064) );
OAI21X4TS U6067 ( .A0(n7938), .A1(n8202), .B0(n7939), .Y(n7888) );
NAND2X4TS U6068 ( .A(n5030), .B(n5029), .Y(n8160) );
NAND2X4TS U6069 ( .A(n5032), .B(n5031), .Y(n8167) );
OAI21X4TS U6070 ( .A0(n8160), .A1(n8165), .B0(n8167), .Y(n5033) );
AOI21X4TS U6071 ( .A0(n5034), .A1(n7888), .B0(n5033), .Y(n8114) );
NAND2X4TS U6072 ( .A(n5038), .B(n5037), .Y(n8118) );
NAND2X4TS U6073 ( .A(n5040), .B(n5039), .Y(n8095) );
OAI21X4TS U6074 ( .A0(n8100), .A1(n8095), .B0(n8101), .Y(n5043) );
AOI21X4TS U6075 ( .A0(n8067), .A1(n5044), .B0(n5043), .Y(n5045) );
OAI21X4TS U6076 ( .A0(n8114), .A1(n5046), .B0(n5045), .Y(n8106) );
OAI21X4TS U6077 ( .A0(n8129), .A1(n8124), .B0(n8130), .Y(n7351) );
NAND2X4TS U6078 ( .A(n5052), .B(n5051), .Y(n8075) );
AOI21X4TS U6079 ( .A0(n7351), .A1(n5056), .B0(n5055), .Y(n5266) );
OAI21X4TS U6080 ( .A0(n7366), .A1(n7410), .B0(n7367), .Y(n5262) );
CMPR32X2TS U6081 ( .A(n5076), .B(n5075), .C(n5074), .CO(n5199), .S(n5136) );
XNOR2X1TS U6082 ( .A(n698), .B(n5324), .Y(n5178) );
OAI22X1TS U6083 ( .A0(n7174), .A1(n5089), .B0(n6021), .B1(n5178), .Y(n5196)
);
XNOR2X1TS U6084 ( .A(n5893), .B(n5090), .Y(n5208) );
OAI22X1TS U6085 ( .A0(n5664), .A1(n5091), .B0(n6332), .B1(n5208), .Y(n5195)
);
OAI22X1TS U6086 ( .A0(n5350), .A1(n5094), .B0(n5720), .B1(n5204), .Y(n5232)
);
XNOR2X1TS U6087 ( .A(n5095), .B(n752), .Y(n5225) );
OAI22X1TS U6088 ( .A0(n6225), .A1(n5096), .B0(n6145), .B1(n5225), .Y(n5231)
);
XNOR2X1TS U6089 ( .A(n793), .B(n763), .Y(n5175) );
OAI22X1TS U6090 ( .A0(n5302), .A1(n5097), .B0(n5877), .B1(n5175), .Y(n5230)
);
XNOR2X1TS U6091 ( .A(n4797), .B(n6400), .Y(n5174) );
OAI22X1TS U6092 ( .A0(n5791), .A1(n5110), .B0(n5388), .B1(n5174), .Y(n5173)
);
XNOR2X1TS U6093 ( .A(n6690), .B(n5953), .Y(n5176) );
OAI22X2TS U6094 ( .A0(n6309), .A1(n5111), .B0(n6254), .B1(n5176), .Y(n5172)
);
XNOR2X1TS U6095 ( .A(n6667), .B(n5662), .Y(n5234) );
OAI22X1TS U6096 ( .A0(n5113), .A1(n5112), .B0(n730), .B1(n5234), .Y(n5171)
);
CMPR32X2TS U6097 ( .A(n5116), .B(n5115), .C(n5114), .CO(n5166), .S(n5139) );
XNOR2X1TS U6098 ( .A(n6296), .B(n5792), .Y(n5193) );
OAI22X1TS U6099 ( .A0(n6679), .A1(n5117), .B0(n6677), .B1(n5193), .Y(n5241)
);
XNOR2X1TS U6100 ( .A(n4497), .B(Op_MY[32]), .Y(n5211) );
OAI22X1TS U6101 ( .A0(n699), .A1(n5118), .B0(n5715), .B1(n5211), .Y(n5240)
);
XNOR2X1TS U6102 ( .A(n5787), .B(n6403), .Y(n5229) );
OAI22X1TS U6103 ( .A0(n6487), .A1(n5119), .B0(n5981), .B1(n5229), .Y(n5239)
);
CMPR32X2TS U6104 ( .A(n5122), .B(n5121), .C(n5120), .CO(n5222), .S(n5101) );
OAI22X1TS U6105 ( .A0(n5191), .A1(n5126), .B0(n5190), .B1(n742), .Y(n5202)
);
XNOR2X1TS U6106 ( .A(n6364), .B(n5348), .Y(n5210) );
XNOR2X1TS U6107 ( .A(n8224), .B(n5526), .Y(n5209) );
OAI22X1TS U6108 ( .A0(n6109), .A1(n5128), .B0(n6456), .B1(n5209), .Y(n5200)
);
XNOR2X1TS U6109 ( .A(n705), .B(n6823), .Y(n5227) );
OAI22X1TS U6110 ( .A0(n5522), .A1(n5131), .B0(n5130), .B1(n5227), .Y(n5244)
);
OAI22X1TS U6111 ( .A0(n5305), .A1(n5133), .B0(n826), .B1(n5235), .Y(n5243)
);
XNOR2X1TS U6112 ( .A(n8804), .B(n5520), .Y(n5179) );
OAI22X1TS U6113 ( .A0(n5135), .A1(n5134), .B0(n5889), .B1(n5179), .Y(n5242)
);
CMPR32X2TS U6114 ( .A(n5141), .B(n5140), .C(n5139), .CO(n5249), .S(n5107) );
INVX4TS U6115 ( .A(n7183), .Y(n5979) );
OAI22X1TS U6116 ( .A0(n5391), .A1(n5148), .B0(n5205), .B1(n5534), .Y(n5247)
);
XNOR2X1TS U6117 ( .A(n755), .B(n5689), .Y(n5177) );
OAI22X1TS U6118 ( .A0(n1710), .A1(n5149), .B0(n5475), .B1(n5177), .Y(n5246)
);
OAI22X1TS U6119 ( .A0(n6154), .A1(n5150), .B0(n5192), .B1(n5860), .Y(n5187)
);
XNOR2X1TS U6120 ( .A(n8812), .B(n5660), .Y(n5233) );
OAI22X1TS U6121 ( .A0(n5677), .A1(n5151), .B0(n3165), .B1(n5233), .Y(n5186)
);
INVX2TS U6122 ( .A(n7821), .Y(n5160) );
XOR2X4TS U6123 ( .A(n5161), .B(n878), .Y(n5164) );
OAI21X4TS U6124 ( .A0(n5164), .A1(n726), .B0(n5163), .Y(Sgf_operation_n45)
);
CMPR32X2TS U6125 ( .A(n5167), .B(n5166), .C(n5165), .CO(n5335), .S(n5223) );
CMPR32X2TS U6126 ( .A(n5170), .B(n5169), .C(n5168), .CO(n5334), .S(n5221) );
CMPR32X2TS U6127 ( .A(n5173), .B(n5172), .C(n5171), .CO(n5285), .S(n5167) );
XNOR2X1TS U6128 ( .A(n6660), .B(n6333), .Y(n5317) );
OAI22X1TS U6129 ( .A0(n5791), .A1(n5174), .B0(n6033), .B1(n5317), .Y(n5313)
);
XNOR2X1TS U6130 ( .A(n792), .B(n5589), .Y(n5301) );
OAI22X1TS U6131 ( .A0(n5302), .A1(n5175), .B0(n6778), .B1(n5301), .Y(n5312)
);
XNOR2X1TS U6132 ( .A(n5503), .B(n6056), .Y(n5294) );
OAI22X1TS U6133 ( .A0(n6309), .A1(n5176), .B0(n6254), .B1(n5294), .Y(n5311)
);
XNOR2X1TS U6134 ( .A(n755), .B(n5879), .Y(n5319) );
OAI22X1TS U6135 ( .A0(n5667), .A1(n5177), .B0(n5475), .B1(n5319), .Y(n5316)
);
OAI22X1TS U6136 ( .A0(n6772), .A1(n5178), .B0(n6021), .B1(n5306), .Y(n5315)
);
XNOR2X1TS U6137 ( .A(n8804), .B(n5604), .Y(n5330) );
OAI22X1TS U6138 ( .A0(n5891), .A1(n5179), .B0(n5889), .B1(n5330), .Y(n5314)
);
OAI22X2TS U6139 ( .A0(n6104), .A1(n5192), .B0(n5347), .B1(n5860), .Y(n5435)
);
INVX2TS U6140 ( .A(n5435), .Y(n5345) );
CMPR32X2TS U6141 ( .A(n5199), .B(n5198), .C(n5197), .CO(n5358), .S(n5185) );
INVX4TS U6142 ( .A(n7331), .Y(n6064) );
XNOR2X1TS U6143 ( .A(n6064), .B(n8811), .Y(n5318) );
XNOR2X1TS U6144 ( .A(n5893), .B(n5207), .Y(n5325) );
OAI22X1TS U6145 ( .A0(n5664), .A1(n5208), .B0(n6332), .B1(n5325), .Y(n5320)
);
XNOR2X1TS U6146 ( .A(n819), .B(n6032), .Y(n5293) );
OAI22X1TS U6147 ( .A0(n6109), .A1(n5209), .B0(n5292), .B1(n5293), .Y(n5291)
);
XNOR2X1TS U6148 ( .A(n6364), .B(n5440), .Y(n5343) );
OAI22X1TS U6149 ( .A0(n5625), .A1(n5210), .B0(n5480), .B1(n5343), .Y(n5290)
);
XNOR2X1TS U6150 ( .A(n8805), .B(n6337), .Y(n5307) );
OAI22X1TS U6151 ( .A0(n724), .A1(n5211), .B0(n5715), .B1(n5307), .Y(n5289)
);
ADDFHX4TS U6152 ( .A(n5217), .B(n5216), .CI(n5215), .CO(n5361), .S(n5254) );
XNOR2X1TS U6153 ( .A(n6642), .B(n6133), .Y(n5332) );
OAI22X1TS U6154 ( .A0(n6225), .A1(n5225), .B0(n5224), .B1(n5332), .Y(n5298)
);
XNOR2X1TS U6155 ( .A(n705), .B(n5226), .Y(n5300) );
OAI22X1TS U6156 ( .A0(n687), .A1(n5227), .B0(n6453), .B1(n5300), .Y(n5297)
);
XNOR2X1TS U6157 ( .A(n791), .B(n820), .Y(n5295) );
OAI22X1TS U6158 ( .A0(n3127), .A1(n5229), .B0(n5228), .B1(n5295), .Y(n5296)
);
XNOR2X1TS U6159 ( .A(n8812), .B(n5684), .Y(n5329) );
OAI22X1TS U6160 ( .A0(n5677), .A1(n5233), .B0(n3165), .B1(n5329), .Y(n5288)
);
XNOR2X1TS U6161 ( .A(n6667), .B(n5602), .Y(n5303) );
XNOR2X1TS U6162 ( .A(n5679), .B(n5409), .Y(n5304) );
OAI22X1TS U6163 ( .A0(n4606), .A1(n5235), .B0(n828), .B1(n5304), .Y(n5286)
);
CMPR32X2TS U6164 ( .A(n5238), .B(n5237), .C(n5236), .CO(n5281), .S(n5183) );
CMPR32X2TS U6165 ( .A(n5244), .B(n5243), .C(n5242), .CO(n5340), .S(n5168) );
CMPR32X2TS U6166 ( .A(n5247), .B(n5246), .C(n5245), .CO(n5339), .S(n5180) );
CMPR32X2TS U6167 ( .A(n5250), .B(n5249), .C(n5248), .CO(n5277), .S(n5218) );
AND2X8TS U6168 ( .A(n5268), .B(n8107), .Y(n5257) );
NAND2X8TS U6169 ( .A(n5258), .B(n5257), .Y(n5270) );
AOI21X4TS U6170 ( .A0(n5262), .A1(n5263), .B0(n5261), .Y(n5264) );
OAI21X4TS U6171 ( .A0(n5266), .A1(n5265), .B0(n5264), .Y(n5267) );
AOI21X4TS U6172 ( .A0(n8106), .A1(n5268), .B0(n5267), .Y(n5269) );
ADDFHX4TS U6173 ( .A(n5276), .B(n5275), .CI(n5274), .CO(n5451), .S(n5360) );
CMPR32X2TS U6174 ( .A(n5285), .B(n5284), .C(n5283), .CO(n5421), .S(n5333) );
CMPR32X2TS U6175 ( .A(n5288), .B(n5287), .C(n5286), .CO(n5374), .S(n5308) );
XNOR2X1TS U6176 ( .A(n819), .B(n5129), .Y(n5431) );
OAI22X1TS U6177 ( .A0(n6109), .A1(n5293), .B0(n5292), .B1(n5431), .Y(n5418)
);
XNOR2X1TS U6178 ( .A(n6208), .B(n752), .Y(n5415) );
OAI22X1TS U6179 ( .A0(n6309), .A1(n5294), .B0(n6254), .B1(n5415), .Y(n5417)
);
XNOR2X1TS U6180 ( .A(n6662), .B(n4176), .Y(n5384) );
OAI22X1TS U6181 ( .A0(n6487), .A1(n5295), .B0(n5981), .B1(n5384), .Y(n5416)
);
OAI22X1TS U6182 ( .A0(n5522), .A1(n5300), .B0(n5410), .B1(n5411), .Y(n5445)
);
OAI22X1TS U6183 ( .A0(n5302), .A1(n5301), .B0(n6778), .B1(n5395), .Y(n5444)
);
XNOR2X1TS U6184 ( .A(n6667), .B(n5792), .Y(n5412) );
OAI22X1TS U6185 ( .A0(n6750), .A1(n5303), .B0(n732), .B1(n5412), .Y(n5443)
);
XNOR2X1TS U6186 ( .A(n5679), .B(n5520), .Y(n5446) );
OAI22X1TS U6187 ( .A0(n6055), .A1(n5304), .B0(n826), .B1(n5446), .Y(n5380)
);
XNOR2X1TS U6188 ( .A(n821), .B(n762), .Y(n5382) );
OAI22X1TS U6189 ( .A0(n6125), .A1(n5306), .B0(n6021), .B1(n5382), .Y(n5379)
);
INVX6TS U6190 ( .A(n657), .Y(n6376) );
XNOR2X1TS U6191 ( .A(n778), .B(n6376), .Y(n5449) );
OAI22X1TS U6192 ( .A0(n6716), .A1(n5307), .B0(n5715), .B1(n5449), .Y(n5378)
);
CMPR32X2TS U6193 ( .A(n5316), .B(n5315), .C(n5314), .CO(n5404), .S(n5283) );
XNOR2X1TS U6194 ( .A(n6327), .B(n6403), .Y(n5389) );
OAI22X1TS U6195 ( .A0(n5791), .A1(n5317), .B0(n6826), .B1(n5389), .Y(n5387)
);
OAI22X1TS U6196 ( .A0(n5391), .A1(n5318), .B0(n5390), .B1(n4850), .Y(n5386)
);
XNOR2X1TS U6197 ( .A(n5979), .B(n678), .Y(n5383) );
OAI22X1TS U6198 ( .A0(n3793), .A1(n5319), .B0(n5383), .B1(n5666), .Y(n5385)
);
XNOR2X1TS U6199 ( .A(n723), .B(n5953), .Y(n5442) );
OAI22X1TS U6200 ( .A0(n6679), .A1(n5323), .B0(n6677), .B1(n5442), .Y(n5408)
);
XNOR2X1TS U6201 ( .A(n5893), .B(n5324), .Y(n5393) );
OAI22X1TS U6202 ( .A0(n5664), .A1(n5325), .B0(n6332), .B1(n5393), .Y(n5407)
);
XNOR2X1TS U6203 ( .A(n8812), .B(n5689), .Y(n5394) );
OAI22X1TS U6204 ( .A0(n5677), .A1(n5329), .B0(n3165), .B1(n5394), .Y(n5377)
);
XNOR2X1TS U6205 ( .A(n8804), .B(n5660), .Y(n5396) );
OAI22X1TS U6206 ( .A0(n5891), .A1(n5330), .B0(n5889), .B1(n5396), .Y(n5376)
);
XNOR2X1TS U6207 ( .A(n5331), .B(n6400), .Y(n5448) );
OAI22X1TS U6208 ( .A0(n5978), .A1(n5332), .B0(n5564), .B1(n5448), .Y(n5375)
);
CMPR32X2TS U6209 ( .A(n5335), .B(n5334), .C(n5333), .CO(n5365), .S(n5273) );
XNOR2X1TS U6210 ( .A(n5342), .B(n5526), .Y(n5432) );
OAI22X1TS U6211 ( .A0(n6381), .A1(n5343), .B0(n6365), .B1(n5432), .Y(n5438)
);
OAI22X1TS U6212 ( .A0(n6154), .A1(n5347), .B0(n5439), .B1(n5860), .Y(n5434)
);
XNOR2X2TS U6213 ( .A(n4419), .B(n5348), .Y(n5441) );
CMPR32X2TS U6214 ( .A(n5356), .B(n5355), .C(n5354), .CO(n5428), .S(n5357) );
ADDFHX4TS U6215 ( .A(n5362), .B(n5361), .CI(n5360), .CO(n7278), .S(n5260) );
CMPR32X2TS U6216 ( .A(n5374), .B(n5373), .C(n5372), .CO(n5510), .S(n5420) );
CMPR32X2TS U6217 ( .A(n5377), .B(n5376), .C(n5375), .CO(n5470), .S(n5425) );
XNOR2X1TS U6218 ( .A(n821), .B(n5589), .Y(n5474) );
OAI22X1TS U6219 ( .A0(n688), .A1(n5382), .B0(n785), .B1(n5474), .Y(n5473) );
OAI22X1TS U6220 ( .A0(n5575), .A1(n5383), .B0(n5476), .B1(n5666), .Y(n5472)
);
XNOR2X1TS U6221 ( .A(n5787), .B(n6337), .Y(n5524) );
OAI22X1TS U6222 ( .A0(n5724), .A1(n5384), .B0(n5981), .B1(n5524), .Y(n5471)
);
CMPR32X2TS U6223 ( .A(n5387), .B(n5386), .C(n5385), .CO(n5513), .S(n5403) );
XNOR2X1TS U6224 ( .A(n638), .B(n3986), .Y(n5501) );
OAI22X1TS U6225 ( .A0(n5791), .A1(n5389), .B0(n5388), .B1(n5501), .Y(n5494)
);
OAI22X1TS U6226 ( .A0(n5391), .A1(n4850), .B0(n5390), .B1(n5533), .Y(n5493)
);
OAI22X1TS U6227 ( .A0(n5664), .A1(n5393), .B0(n6332), .B1(n5532), .Y(n5492)
);
XNOR2X1TS U6228 ( .A(n825), .B(n5879), .Y(n5478) );
OAI22X1TS U6229 ( .A0(n5677), .A1(n5394), .B0(n3165), .B1(n5478), .Y(n5519)
);
XNOR2X1TS U6230 ( .A(n793), .B(n5602), .Y(n5477) );
OAI22X1TS U6231 ( .A0(n6820), .A1(n5395), .B0(n6778), .B1(n5477), .Y(n5518)
);
XNOR2X1TS U6232 ( .A(n8804), .B(n5684), .Y(n5488) );
OAI22X1TS U6233 ( .A0(n5891), .A1(n5396), .B0(n5889), .B1(n5488), .Y(n5517)
);
CMPR32X2TS U6234 ( .A(n5402), .B(n5401), .C(n5400), .CO(n5484), .S(n5419) );
CMPR32X2TS U6235 ( .A(n5408), .B(n5407), .C(n5406), .CO(n5487), .S(n5426) );
XNOR2X1TS U6236 ( .A(n694), .B(n5409), .Y(n5521) );
OAI22X1TS U6237 ( .A0(n687), .A1(n5411), .B0(n5410), .B1(n5521), .Y(n5500)
);
OAI22X1TS U6238 ( .A0(n6750), .A1(n5412), .B0(n730), .B1(n5502), .Y(n5499)
);
XNOR2X1TS U6239 ( .A(n8221), .B(n5413), .Y(n5504) );
OAI22X1TS U6240 ( .A0(n6309), .A1(n5415), .B0(n5414), .B1(n5504), .Y(n5498)
);
CMPR32X2TS U6241 ( .A(n5427), .B(n5426), .C(n5425), .CO(n5538), .S(n5397) );
XNOR2X1TS U6242 ( .A(n6069), .B(n5708), .Y(n5490) );
OAI22X1TS U6243 ( .A0(n6459), .A1(n5431), .B0(n6138), .B1(n5490), .Y(n5497)
);
XNOR2X1TS U6244 ( .A(n5623), .B(n4905), .Y(n5481) );
OAI22X1TS U6245 ( .A0(n702), .A1(n5432), .B0(n5480), .B1(n5481), .Y(n5496)
);
OAI22X2TS U6246 ( .A0(n6104), .A1(n5439), .B0(n5525), .B1(n5860), .Y(n5600)
);
INVX2TS U6247 ( .A(n5600), .Y(n5530) );
OAI22X2TS U6248 ( .A0(n6301), .A1(n5441), .B0(n5720), .B1(n5527), .Y(n5529)
);
OAI22X1TS U6249 ( .A0(n6679), .A1(n5442), .B0(n6677), .B1(n5531), .Y(n5528)
);
XNOR2X1TS U6250 ( .A(n5679), .B(n5604), .Y(n5491) );
OAI22X1TS U6251 ( .A0(n4606), .A1(n5446), .B0(n827), .B1(n5491), .Y(n5507)
);
XNOR2X1TS U6252 ( .A(n6642), .B(n6333), .Y(n5523) );
OAI22X1TS U6253 ( .A0(n5978), .A1(n5448), .B0(n6387), .B1(n5523), .Y(n5506)
);
XNOR2X1TS U6254 ( .A(n8209), .B(n6652), .Y(n5479) );
OAI22X1TS U6255 ( .A0(n714), .A1(n5449), .B0(n5715), .B1(n5479), .Y(n5505)
);
ADDFHX4TS U6256 ( .A(n5452), .B(n5451), .CI(n5450), .CO(n7280), .S(n7277) );
ADDFHX2TS U6257 ( .A(n5458), .B(n5457), .CI(n5456), .CO(n5541), .S(n5459) );
OAI22X1TS U6258 ( .A0(n7174), .A1(n5474), .B0(n7166), .B1(n5603), .Y(n5582)
);
OAI22X1TS U6259 ( .A0(n5575), .A1(n5476), .B0(n5475), .B1(n678), .Y(n5581)
);
XNOR2X1TS U6260 ( .A(n794), .B(n5792), .Y(n5588) );
OAI22X1TS U6261 ( .A0(n6820), .A1(n5477), .B0(n6778), .B1(n5588), .Y(n5580)
);
XNOR2X1TS U6262 ( .A(n5979), .B(n822), .Y(n5563) );
OAI22X1TS U6263 ( .A0(n5677), .A1(n5478), .B0(n5563), .B1(n5795), .Y(n5596)
);
XNOR2X1TS U6264 ( .A(n8209), .B(n6647), .Y(n5576) );
XNOR2X1TS U6265 ( .A(n5623), .B(n5129), .Y(n5570) );
OAI22X1TS U6266 ( .A0(n6202), .A1(n5481), .B0(n5480), .B1(n5570), .Y(n5594)
);
CMPR32X2TS U6267 ( .A(n5487), .B(n5486), .C(n5485), .CO(n5556), .S(n5482) );
OAI22X1TS U6268 ( .A0(n5891), .A1(n5488), .B0(n5889), .B1(n5568), .Y(n5579)
);
XNOR2X1TS U6269 ( .A(n5679), .B(n5660), .Y(n5597) );
OAI22X1TS U6270 ( .A0(n4606), .A1(n5491), .B0(n829), .B1(n5597), .Y(n5577)
);
CMPR32X2TS U6271 ( .A(n5497), .B(n5496), .C(n5495), .CO(n5612), .S(n5516) );
CMPR32X2TS U6272 ( .A(n5500), .B(n5499), .C(n5498), .CO(n5559), .S(n5486) );
OAI22X1TS U6273 ( .A0(n5791), .A1(n5501), .B0(n6826), .B1(n5587), .Y(n5593)
);
XNOR2X1TS U6274 ( .A(n6667), .B(n5953), .Y(n5584) );
OAI22X1TS U6275 ( .A0(n6750), .A1(n5502), .B0(n730), .B1(n5584), .Y(n5592)
);
XNOR2X1TS U6276 ( .A(n797), .B(n6400), .Y(n5566) );
OAI22X1TS U6277 ( .A0(n813), .A1(n5504), .B0(n5743), .B1(n5566), .Y(n5591)
);
CMPR32X2TS U6278 ( .A(n5507), .B(n5506), .C(n5505), .CO(n5557), .S(n5465) );
CMPR32X2TS U6279 ( .A(n5513), .B(n5512), .C(n5511), .CO(n5620), .S(n5508) );
CMPR32X2TS U6280 ( .A(n5519), .B(n5518), .C(n5517), .CO(n5608), .S(n5511) );
XNOR2X1TS U6281 ( .A(n705), .B(n5520), .Y(n5605) );
OAI22X1TS U6282 ( .A0(n6455), .A1(n5521), .B0(n6453), .B1(n5605), .Y(n5573)
);
OAI22X1TS U6283 ( .A0(n5978), .A1(n5523), .B0(n6387), .B1(n5565), .Y(n5572)
);
XNOR2X1TS U6284 ( .A(n5787), .B(n6376), .Y(n5569) );
OAI22X1TS U6285 ( .A0(n5724), .A1(n5524), .B0(n5981), .B1(n5569), .Y(n5571)
);
OAI22X1TS U6286 ( .A0(n6127), .A1(n5525), .B0(n5601), .B1(n5860), .Y(n5599)
);
AO21X1TS U6287 ( .A0(n5535), .A1(n5534), .B0(n5533), .Y(n5560) );
CMPR32X2TS U6288 ( .A(n5538), .B(n5537), .C(n5536), .CO(n5542), .S(n5456) );
CMPR32X2TS U6289 ( .A(n5559), .B(n5558), .C(n5557), .CO(n5829), .S(n5554) );
ADDFX2TS U6290 ( .A(n5562), .B(n5561), .CI(n5560), .CO(n5653), .S(n5609) );
XNOR2X1TS U6291 ( .A(n6064), .B(n822), .Y(n5676) );
OAI22X1TS U6292 ( .A0(n5677), .A1(n5563), .B0(n5676), .B1(n5795), .Y(n5718)
);
XNOR2X1TS U6293 ( .A(n5503), .B(n6333), .Y(n5635) );
OAI22X1TS U6294 ( .A0(n6482), .A1(n5566), .B0(n6480), .B1(n5635), .Y(n5716)
);
XNOR2X1TS U6295 ( .A(n5567), .B(n5879), .Y(n5678) );
OAI22X1TS U6296 ( .A0(n5891), .A1(n5568), .B0(n5889), .B1(n5678), .Y(n5644)
);
XNOR2X1TS U6297 ( .A(n6662), .B(n6652), .Y(n5723) );
OAI22X1TS U6298 ( .A0(n5724), .A1(n5569), .B0(n5981), .B1(n5723), .Y(n5643)
);
XNOR2X1TS U6299 ( .A(n5623), .B(n5708), .Y(n5624) );
OAI22X1TS U6300 ( .A0(n5944), .A1(n5570), .B0(n789), .B1(n5624), .Y(n5642)
);
CMPR32X2TS U6301 ( .A(n5573), .B(n5572), .C(n5571), .CO(n5656), .S(n5607) );
XNOR2X1TS U6302 ( .A(n6842), .B(n6133), .Y(n5632) );
OAI22X1TS U6303 ( .A0(n6679), .A1(n5574), .B0(n7012), .B1(n5632), .Y(n5659)
);
OAI22X1TS U6304 ( .A0(n5575), .A1(n678), .B0(n997), .B1(n5665), .Y(n5658) );
XNOR2X1TS U6305 ( .A(n779), .B(n6672), .Y(n5726) );
OAI22X1TS U6306 ( .A0(n4540), .A1(n5576), .B0(n5715), .B1(n5726), .Y(n5657)
);
XNOR2X1TS U6307 ( .A(n4419), .B(n6032), .Y(n5721) );
OAI22X1TS U6308 ( .A0(n6301), .A1(n5583), .B0(n5720), .B1(n5721), .Y(n5638)
);
XNOR2X1TS U6309 ( .A(n819), .B(n5873), .Y(n5621) );
OAI22X1TS U6310 ( .A0(n782), .A1(n5586), .B0(n5585), .B1(n5621), .Y(n5636)
);
XNOR2X1TS U6311 ( .A(n638), .B(n6337), .Y(n5669) );
OAI22X1TS U6312 ( .A0(n5791), .A1(n5587), .B0(n6033), .B1(n5669), .Y(n5674)
);
XNOR2X1TS U6313 ( .A(n794), .B(n5892), .Y(n5671) );
OAI22X1TS U6314 ( .A0(n6820), .A1(n5588), .B0(n6778), .B1(n5671), .Y(n5673)
);
XNOR2X1TS U6315 ( .A(n5893), .B(n5589), .Y(n5663) );
OAI22X1TS U6316 ( .A0(n5664), .A1(n5590), .B0(n739), .B1(n5663), .Y(n5672)
);
XNOR2X1TS U6317 ( .A(n5679), .B(n5684), .Y(n5680) );
OAI22X1TS U6318 ( .A0(n5305), .A1(n5597), .B0(n829), .B1(n5680), .Y(n5729)
);
OAI22X1TS U6319 ( .A0(n6104), .A1(n5601), .B0(n5626), .B1(n6414), .Y(n5630)
);
INVX2TS U6320 ( .A(n5630), .Y(n5641) );
OAI22X1TS U6321 ( .A0(n817), .A1(n5605), .B0(n6453), .B1(n5661), .Y(n5639)
);
CMPR32X2TS U6322 ( .A(n5611), .B(n5610), .C(n5609), .CO(n5823), .S(n5606) );
CMPR32X2TS U6323 ( .A(n5614), .B(n5613), .C(n5612), .CO(n5822), .S(n5555) );
CMPR32X2TS U6324 ( .A(n5617), .B(n5616), .C(n5615), .CO(n5821), .S(n5551) );
NOR2X8TS U6325 ( .A(n7285), .B(n7284), .Y(n7345) );
XNOR2X1TS U6326 ( .A(n6069), .B(n5986), .Y(n5754) );
OAI22X1TS U6327 ( .A0(n782), .A1(n5621), .B0(n6138), .B1(n5754), .Y(n5647)
);
XNOR2X1TS U6328 ( .A(n5623), .B(n5783), .Y(n5713) );
OAI22X1TS U6329 ( .A0(n6381), .A1(n5624), .B0(n789), .B1(n5713), .Y(n5646)
);
OAI22X1TS U6330 ( .A0(n6127), .A1(n5626), .B0(n668), .B1(n5860), .Y(n5629)
);
XNOR2X1TS U6331 ( .A(n821), .B(n5792), .Y(n5753) );
OAI22X1TS U6332 ( .A0(n688), .A1(n5627), .B0(n785), .B1(n5753), .Y(n5628) );
CMPR32X2TS U6333 ( .A(n5630), .B(n5629), .C(n5628), .CO(n5696), .S(n5645) );
XNOR2X1TS U6334 ( .A(n4797), .B(n6652), .Y(n5790) );
OAI22X1TS U6335 ( .A0(n5668), .A1(n5791), .B0(n6033), .B1(n5790), .Y(n5692)
);
OAI22X1TS U6336 ( .A0(n5677), .A1(n823), .B0(n3165), .B1(n5794), .Y(n5691)
);
XNOR2X1TS U6337 ( .A(n5631), .B(n6400), .Y(n5742) );
OAI22X1TS U6338 ( .A0(n4055), .A1(n5632), .B0(n5887), .B1(n5742), .Y(n5683)
);
XNOR2X1TS U6339 ( .A(n5633), .B(n752), .Y(n5712) );
OAI22X1TS U6340 ( .A0(n6750), .A1(n5634), .B0(n730), .B1(n5712), .Y(n5682)
);
XNOR2X1TS U6341 ( .A(n8221), .B(n6403), .Y(n5744) );
OAI22X1TS U6342 ( .A0(n813), .A1(n5635), .B0(n6480), .B1(n5744), .Y(n5681)
);
CMPR32X2TS U6343 ( .A(n5647), .B(n5646), .C(n5645), .CO(n5699), .S(n5820) );
CMPR32X2TS U6344 ( .A(n5653), .B(n5652), .C(n5651), .CO(n5818), .S(n5828) );
CMPR32X2TS U6345 ( .A(n5656), .B(n5655), .C(n5654), .CO(n5826), .S(n5827) );
CMPR32X2TS U6346 ( .A(n5659), .B(n5658), .C(n5657), .CO(n5702), .S(n5655) );
XNOR2X1TS U6347 ( .A(n5893), .B(n5662), .Y(n5746) );
OAI22X1TS U6348 ( .A0(n5664), .A1(n5663), .B0(n738), .B1(n5746), .Y(n5748)
);
OAI22X1TS U6349 ( .A0(n5791), .A1(n5669), .B0(n6033), .B1(n5668), .Y(n5738)
);
XNOR2X1TS U6350 ( .A(n794), .B(n5953), .Y(n5755) );
OAI22X1TS U6351 ( .A0(n6820), .A1(n5671), .B0(n6778), .B1(n5755), .Y(n5736)
);
CMPR32X2TS U6352 ( .A(n5674), .B(n5673), .C(n5672), .CO(n5735), .S(n5756) );
OAI22X1TS U6353 ( .A0(n5677), .A1(n5676), .B0(n3165), .B1(n824), .Y(n5705)
);
XNOR2X1TS U6354 ( .A(n5979), .B(n5890), .Y(n5686) );
OAI22X1TS U6355 ( .A0(n5891), .A1(n5678), .B0(n5686), .B1(n625), .Y(n5704)
);
XNOR2X1TS U6356 ( .A(n5679), .B(n5689), .Y(n5687) );
OAI22X1TS U6357 ( .A0(n5305), .A1(n5680), .B0(n828), .B1(n5687), .Y(n5703)
);
CMPR32X2TS U6358 ( .A(n5683), .B(n5682), .C(n5681), .CO(n5694), .S(n5733) );
XNOR2X1TS U6359 ( .A(n5880), .B(n5684), .Y(n5690) );
OAI22X1TS U6360 ( .A0(n5522), .A1(n5685), .B0(n6453), .B1(n5690), .Y(n5741)
);
OAI22X1TS U6361 ( .A0(n5891), .A1(n5686), .B0(n5786), .B1(n625), .Y(n5740)
);
XNOR2X1TS U6362 ( .A(n6054), .B(n5879), .Y(n5779) );
OAI22X1TS U6363 ( .A0(n761), .A1(n5687), .B0(n828), .B1(n5779), .Y(n5739) );
XNOR2X1TS U6364 ( .A(n8805), .B(n6775), .Y(n5714) );
XNOR2X1TS U6365 ( .A(n8805), .B(n5707), .Y(n5907) );
OAI22X1TS U6366 ( .A0(n6716), .A1(n5714), .B0(n5715), .B1(n5907), .Y(n5914)
);
OAI22X1TS U6367 ( .A0(n6127), .A1(n5688), .B0(n5861), .B1(n5860), .Y(n5910)
);
XNOR2X1TS U6368 ( .A(n5880), .B(n5689), .Y(n5881) );
CMPR32X2TS U6369 ( .A(n5693), .B(n5692), .C(n5691), .CO(n5912), .S(n5695) );
CMPR32X2TS U6370 ( .A(n5702), .B(n5701), .C(n5700), .CO(n5732), .S(n5825) );
CMPR32X2TS U6371 ( .A(n5705), .B(n5704), .C(n5703), .CO(n5770), .S(n5734) );
XNOR2X1TS U6372 ( .A(n8813), .B(n6823), .Y(n5719) );
XNOR2X1TS U6373 ( .A(n708), .B(n5708), .Y(n5785) );
OAI22X1TS U6374 ( .A0(n6419), .A1(n5719), .B0(n735), .B1(n5785), .Y(n5782)
);
XNOR2X1TS U6375 ( .A(n795), .B(n5413), .Y(n5776) );
OAI22X1TS U6376 ( .A0(n6750), .A1(n5712), .B0(n5711), .B1(n5776), .Y(n5780)
);
XNOR2X1TS U6377 ( .A(n6379), .B(n5873), .Y(n5809) );
OAI22X1TS U6378 ( .A0(n5625), .A1(n5713), .B0(n789), .B1(n5809), .Y(n5808)
);
XNOR2X1TS U6379 ( .A(n4813), .B(n6647), .Y(n5722) );
XNOR2X1TS U6380 ( .A(n6662), .B(n6672), .Y(n5788) );
OAI22X1TS U6381 ( .A0(n781), .A1(n5722), .B0(n5981), .B1(n5788), .Y(n5807)
);
XNOR2X1TS U6382 ( .A(n8209), .B(n6742), .Y(n5725) );
OAI22X1TS U6383 ( .A0(n724), .A1(n5725), .B0(n5715), .B1(n5714), .Y(n5806)
);
OAI22X1TS U6384 ( .A0(n6301), .A1(n5721), .B0(n5720), .B1(n5719), .Y(n5752)
);
OAI22X1TS U6385 ( .A0(n6487), .A1(n5723), .B0(n5981), .B1(n5722), .Y(n5751)
);
OAI22X1TS U6386 ( .A0(n4540), .A1(n5726), .B0(n6651), .B1(n5725), .Y(n5750)
);
CMPR32X2TS U6387 ( .A(n5735), .B(n5734), .C(n5733), .CO(n5767), .S(n5824) );
CMPR32X2TS U6388 ( .A(n5738), .B(n5737), .C(n5736), .CO(n5799), .S(n5700) );
CMPR32X2TS U6389 ( .A(n5741), .B(n5740), .C(n5739), .CO(n5917), .S(n5798) );
OAI22X1TS U6390 ( .A0(n812), .A1(n5742), .B0(n721), .B1(n5777), .Y(n5773) );
XNOR2X1TS U6391 ( .A(n5503), .B(n820), .Y(n5810) );
OAI22X1TS U6392 ( .A0(n6482), .A1(n5744), .B0(n5743), .B1(n5810), .Y(n5772)
);
XNOR2X1TS U6393 ( .A(n5893), .B(n5745), .Y(n5793) );
OAI22X1TS U6394 ( .A0(n6953), .A1(n5746), .B0(n740), .B1(n5793), .Y(n5771)
);
CMPR32X2TS U6395 ( .A(n5749), .B(n5748), .C(n5747), .CO(n5802), .S(n5701) );
CMPR32X2TS U6396 ( .A(n5752), .B(n5751), .C(n5750), .CO(n5801), .S(n5763) );
OAI22X1TS U6397 ( .A0(n6886), .A1(n5753), .B0(n785), .B1(n5774), .Y(n5805)
);
XNOR2X1TS U6398 ( .A(n5489), .B(n6030), .Y(n5778) );
OAI22X1TS U6399 ( .A0(n6459), .A1(n5754), .B0(n6138), .B1(n5778), .Y(n5804)
);
XNOR2X1TS U6400 ( .A(n5990), .B(n6056), .Y(n5775) );
OAI22X1TS U6401 ( .A0(n6820), .A1(n5755), .B0(n6778), .B1(n5775), .Y(n5803)
);
CMPR32X2TS U6402 ( .A(n5758), .B(n5757), .C(n5756), .CO(n5832), .S(n5835) );
CMPR32X2TS U6403 ( .A(n5764), .B(n5763), .C(n5762), .CO(n5730), .S(n5830) );
CMPR32X2TS U6404 ( .A(n5773), .B(n5772), .C(n5771), .CO(n5853), .S(n5797) );
OAI22X1TS U6405 ( .A0(n7174), .A1(n5774), .B0(n785), .B1(n5862), .Y(n5866)
);
XNOR2X1TS U6406 ( .A(n794), .B(n752), .Y(n5878) );
OAI22X1TS U6407 ( .A0(n6478), .A1(n5776), .B0(n6023), .B1(n5883), .Y(n5864)
);
XNOR2X1TS U6408 ( .A(n6842), .B(n6403), .Y(n5888) );
OAI22X1TS U6409 ( .A0(n4780), .A1(n5777), .B0(n721), .B1(n5888), .Y(n5906)
);
XNOR2X1TS U6410 ( .A(n8808), .B(n6371), .Y(n5882) );
OAI22X1TS U6411 ( .A0(n6459), .A1(n5778), .B0(n6138), .B1(n5882), .Y(n5905)
);
OAI22X1TS U6412 ( .A0(n2457), .A1(n5779), .B0(n5876), .B1(n6428), .Y(n5904)
);
CMPR32X2TS U6413 ( .A(n5782), .B(n5781), .C(n5780), .CO(n5856), .S(n5769) );
XNOR2X1TS U6414 ( .A(n5874), .B(n5783), .Y(n5875) );
OAI22X1TS U6415 ( .A0(n815), .A1(n5785), .B0(n735), .B1(n5875), .Y(n5886) );
OAI22X1TS U6416 ( .A0(n5891), .A1(n5786), .B0(n5889), .B1(n5890), .Y(n5885)
);
XNOR2X1TS U6417 ( .A(n6222), .B(n6742), .Y(n5908) );
OAI22X1TS U6418 ( .A0(n5724), .A1(n5788), .B0(n6745), .B1(n5908), .Y(n5884)
);
XNOR2X1TS U6419 ( .A(n8809), .B(n6647), .Y(n5863) );
OAI22X1TS U6420 ( .A0(n5791), .A1(n5790), .B0(n5789), .B1(n5863), .Y(n5872)
);
XNOR2X1TS U6421 ( .A(n630), .B(n5792), .Y(n5894) );
OAI22X1TS U6422 ( .A0(n6953), .A1(n5793), .B0(n738), .B1(n5894), .Y(n5871)
);
CMPR32X2TS U6423 ( .A(n5799), .B(n5798), .C(n5797), .CO(n5859), .S(n5766) );
CMPR32X2TS U6424 ( .A(n5802), .B(n5801), .C(n5800), .CO(n5858), .S(n5765) );
CMPR32X2TS U6425 ( .A(n5805), .B(n5804), .C(n5803), .CO(n5850), .S(n5800) );
CMPR32X2TS U6426 ( .A(n5808), .B(n5807), .C(n5806), .CO(n5849), .S(n5768) );
XNOR2X1TS U6427 ( .A(n6379), .B(n5986), .Y(n5867) );
OAI22X1TS U6428 ( .A0(n702), .A1(n5809), .B0(n6365), .B1(n5867), .Y(n5897)
);
XNOR2X1TS U6429 ( .A(n6690), .B(Op_MY[32]), .Y(n5868) );
OAI22X1TS U6430 ( .A0(n6482), .A1(n5810), .B0(n6480), .B1(n5868), .Y(n5896)
);
XNOR2X1TS U6431 ( .A(n6642), .B(n6376), .Y(n5869) );
OAI22X1TS U6432 ( .A0(n5978), .A1(n5811), .B0(n6387), .B1(n5869), .Y(n5895)
);
CMPR32X2TS U6433 ( .A(n5823), .B(n5822), .C(n5821), .CO(n5840), .S(n6082) );
CMPR32X2TS U6434 ( .A(n5829), .B(n5828), .C(n5827), .CO(n5847), .S(n5842) );
CMPR32X2TS U6435 ( .A(n5850), .B(n5849), .C(n5848), .CO(n5935), .S(n5857) );
CMPR32X2TS U6436 ( .A(n5853), .B(n5852), .C(n5851), .CO(n5934), .S(n5919) );
CMPR32X2TS U6437 ( .A(n5856), .B(n5855), .C(n5854), .CO(n5933), .S(n5918) );
CMPR32X2TS U6438 ( .A(n5859), .B(n5858), .C(n5857), .CO(n5999), .S(n5921) );
XNOR2X1TS U6439 ( .A(n8814), .B(n6056), .Y(n5973) );
OAI22X2TS U6440 ( .A0(n6886), .A1(n5862), .B0(n785), .B1(n5973), .Y(n5975)
);
XNOR2X1TS U6441 ( .A(n638), .B(n6672), .Y(n5952) );
OAI22X1TS U6442 ( .A0(n6827), .A1(n5863), .B0(n6033), .B1(n5952), .Y(n5974)
);
CMPR32X2TS U6443 ( .A(n5866), .B(n5865), .C(n5864), .CO(n5984), .S(n5852) );
XNOR2X1TS U6444 ( .A(n6379), .B(n6030), .Y(n5943) );
OAI22X1TS U6445 ( .A0(n702), .A1(n5867), .B0(n789), .B1(n5943), .Y(n5959) );
XNOR2X1TS U6446 ( .A(n6690), .B(n6337), .Y(n5996) );
OAI22X1TS U6447 ( .A0(n6482), .A1(n5868), .B0(n6480), .B1(n5996), .Y(n5958)
);
XNOR2X1TS U6448 ( .A(n697), .B(n6652), .Y(n5977) );
OAI22X1TS U6449 ( .A0(n5978), .A1(n5869), .B0(n6387), .B1(n5977), .Y(n5957)
);
CMPR32X2TS U6450 ( .A(n5872), .B(n5871), .C(n5870), .CO(n5968), .S(n5854) );
XNOR2X1TS U6451 ( .A(n5874), .B(n5873), .Y(n5987) );
OAI22X1TS U6452 ( .A0(n814), .A1(n5875), .B0(n735), .B1(n5987), .Y(n5941) );
OAI22X1TS U6453 ( .A0(n6055), .A1(n5876), .B0(n5989), .B1(n6428), .Y(n5940)
);
XNOR2X1TS U6454 ( .A(n6404), .B(n5413), .Y(n5991) );
OAI22X1TS U6455 ( .A0(n6820), .A1(n5878), .B0(n5877), .B1(n5991), .Y(n5939)
);
XNOR2X1TS U6456 ( .A(n5880), .B(n5879), .Y(n5980) );
OAI22X1TS U6457 ( .A0(n1663), .A1(n5881), .B0(n6453), .B1(n5980), .Y(n5994)
);
OAI22X1TS U6458 ( .A0(n6459), .A1(n5882), .B0(n6138), .B1(n5942), .Y(n5993)
);
XNOR2X1TS U6459 ( .A(n796), .B(n6333), .Y(n5997) );
OAI22X1TS U6460 ( .A0(n6478), .A1(n5883), .B0(n6476), .B1(n5997), .Y(n5992)
);
CMPR32X2TS U6461 ( .A(n5886), .B(n5885), .C(n5884), .CO(n5938), .S(n5855) );
XNOR2X1TS U6462 ( .A(n6842), .B(n6335), .Y(n5995) );
OAI22X1TS U6463 ( .A0(n6679), .A1(n5888), .B0(n5887), .B1(n5995), .Y(n5951)
);
OAI22X1TS U6464 ( .A0(n5891), .A1(n5890), .B0(n5889), .B1(n5955), .Y(n5950)
);
XNOR2X1TS U6465 ( .A(n5893), .B(n5892), .Y(n5954) );
OAI22X1TS U6466 ( .A0(n6953), .A1(n5894), .B0(n740), .B1(n5954), .Y(n5949)
);
CMPR32X2TS U6467 ( .A(n5897), .B(n5896), .C(n5895), .CO(n5936), .S(n5848) );
CMPR32X2TS U6468 ( .A(n5906), .B(n5905), .C(n5904), .CO(n5971), .S(n5851) );
INVX6TS U6469 ( .A(n6947), .Y(n6851) );
XNOR2X1TS U6470 ( .A(n8805), .B(n6851), .Y(n5945) );
OAI22X1TS U6471 ( .A0(n724), .A1(n5907), .B0(n683), .B1(n5945), .Y(n5948) );
XNOR2X1TS U6472 ( .A(n791), .B(n4905), .Y(n5982) );
OAI22X1TS U6473 ( .A0(n781), .A1(n5908), .B0(n5981), .B1(n5982), .Y(n5947)
);
ADDFHX4TS U6474 ( .A(n5926), .B(n5925), .CI(n5924), .CO(n7292), .S(n7294) );
CMPR32X2TS U6475 ( .A(n5932), .B(n5931), .C(n5930), .CO(n6003), .S(n5998) );
CMPR32X2TS U6476 ( .A(n5938), .B(n5937), .C(n5936), .CO(n6043), .S(n5930) );
XNOR2X1TS U6477 ( .A(n8808), .B(n6378), .Y(n6070) );
XNOR2X1TS U6478 ( .A(n6379), .B(n6371), .Y(n6025) );
XNOR2X1TS U6479 ( .A(n779), .B(n6887), .Y(n6074) );
OAI22X1TS U6480 ( .A0(n4540), .A1(n5945), .B0(n6073), .B1(n6074), .Y(n6058)
);
CMPR32X2TS U6481 ( .A(n5948), .B(n5947), .C(n5946), .CO(n6038), .S(n5970) );
XNOR2X1TS U6482 ( .A(n6327), .B(n6742), .Y(n6034) );
OAI22X1TS U6483 ( .A0(n6827), .A1(n5952), .B0(n6826), .B1(n6034), .Y(n6063)
);
XNOR2X1TS U6484 ( .A(n770), .B(n5953), .Y(n6057) );
OAI22X1TS U6485 ( .A0(n6953), .A1(n5954), .B0(n738), .B1(n6057), .Y(n6062)
);
CMPR32X2TS U6486 ( .A(n5959), .B(n5958), .C(n5957), .CO(n6047), .S(n5983) );
CMPR32X2TS U6487 ( .A(n5968), .B(n5967), .C(n5966), .CO(n6009), .S(n5931) );
CMPR32X2TS U6488 ( .A(n5971), .B(n5970), .C(n5969), .CO(n6008), .S(n5965) );
OAI22X1TS U6489 ( .A0(n6127), .A1(n5972), .B0(n6029), .B1(n6414), .Y(n6027)
);
XNOR2X1TS U6490 ( .A(n6401), .B(n643), .Y(n6022) );
OAI22X1TS U6491 ( .A0(n6125), .A1(n5973), .B0(n7166), .B1(n6022), .Y(n6026)
);
CMPR32X2TS U6492 ( .A(n5976), .B(n5975), .C(n5974), .CO(n6036), .S(n5985) );
XNOR2X1TS U6493 ( .A(n6642), .B(n6647), .Y(n6068) );
XNOR2X1TS U6494 ( .A(n4813), .B(n5129), .Y(n6072) );
OAI22X1TS U6495 ( .A0(n5724), .A1(n5982), .B0(n5981), .B1(n6072), .Y(n6016)
);
CMPR32X2TS U6496 ( .A(n5985), .B(n5984), .C(n5983), .CO(n6045), .S(n5932) );
XNOR2X1TS U6497 ( .A(n8813), .B(n5986), .Y(n6031) );
OAI22X1TS U6498 ( .A0(n814), .A1(n5987), .B0(n734), .B1(n6031), .Y(n6052) );
XNOR2X1TS U6499 ( .A(n5990), .B(n6400), .Y(n6020) );
OAI22X1TS U6500 ( .A0(n6443), .A1(n5991), .B0(n6406), .B1(n6020), .Y(n6050)
);
CMPR32X2TS U6501 ( .A(n5994), .B(n5993), .C(n5992), .CO(n6011), .S(n5966) );
OAI22X1TS U6502 ( .A0(n4780), .A1(n5995), .B0(n720), .B1(n6053), .Y(n6015)
);
XNOR2X1TS U6503 ( .A(n6100), .B(n6376), .Y(n6066) );
OAI22X1TS U6504 ( .A0(n6482), .A1(n5996), .B0(n6480), .B1(n6066), .Y(n6014)
);
XNOR2X1TS U6505 ( .A(n796), .B(n6403), .Y(n6024) );
OAI22X1TS U6506 ( .A0(n6478), .A1(n5997), .B0(n6476), .B1(n6024), .Y(n6013)
);
CMPR32X2TS U6507 ( .A(n6012), .B(n6011), .C(n6010), .CO(n6601), .S(n6044) );
CMPR32X2TS U6508 ( .A(n6015), .B(n6014), .C(n6013), .CO(n6595), .S(n6010) );
BUFX4TS U6509 ( .A(n6019), .Y(n6670) );
XNOR2X1TS U6510 ( .A(n6404), .B(n6333), .Y(n6442) );
OAI22X1TS U6511 ( .A0(n6443), .A1(n6020), .B0(n6670), .B1(n6442), .Y(n6508)
);
XNOR2X1TS U6512 ( .A(n698), .B(n6133), .Y(n6438) );
OAI22X1TS U6513 ( .A0(n6125), .A1(n6022), .B0(n6021), .B1(n6438), .Y(n6507)
);
XNOR2X1TS U6514 ( .A(n6931), .B(n3986), .Y(n6477) );
OAI22X1TS U6515 ( .A0(n6478), .A1(n6024), .B0(n6023), .B1(n6477), .Y(n6506)
);
XNOR2X1TS U6516 ( .A(n6379), .B(n6131), .Y(n6462) );
OAI22X1TS U6517 ( .A0(n6381), .A1(n6025), .B0(n789), .B1(n6462), .Y(n6541)
);
CMPR32X2TS U6518 ( .A(n6028), .B(n6027), .C(n6026), .CO(n6540), .S(n6037) );
OAI22X1TS U6519 ( .A0(n6127), .A1(n6029), .B0(n6416), .B1(n6414), .Y(n6490)
);
INVX2TS U6520 ( .A(n6490), .Y(n6499) );
XNOR2X1TS U6521 ( .A(n4419), .B(n6030), .Y(n6418) );
XNOR2X1TS U6522 ( .A(n703), .B(n4905), .Y(n6424) );
OAI22X1TS U6523 ( .A0(n6827), .A1(n6034), .B0(n6033), .B1(n6424), .Y(n6497)
);
CMPR32X2TS U6524 ( .A(n6037), .B(n6036), .C(n6035), .CO(n6597), .S(n6046) );
CMPR32X2TS U6525 ( .A(n6040), .B(n6039), .C(n6038), .CO(n6596), .S(n6042) );
CMPR32X2TS U6526 ( .A(n6049), .B(n6048), .C(n6047), .CO(n6586), .S(n6041) );
CMPR32X2TS U6527 ( .A(n6052), .B(n6051), .C(n6050), .CO(n6592), .S(n6012) );
XNOR2X1TS U6528 ( .A(n6842), .B(n6337), .Y(n6474) );
OAI22X1TS U6529 ( .A0(n6679), .A1(n6053), .B0(n720), .B1(n6474), .Y(n6502)
);
OAI22X1TS U6530 ( .A0(n6055), .A1(n5132), .B0(n826), .B1(n6427), .Y(n6501)
);
XNOR2X1TS U6531 ( .A(n680), .B(n6056), .Y(n6426) );
OAI22X1TS U6532 ( .A0(n6953), .A1(n6057), .B0(n739), .B1(n6426), .Y(n6500)
);
CMPR32X2TS U6533 ( .A(n6063), .B(n6062), .C(n6061), .CO(n6559), .S(n6048) );
XNOR2X1TS U6534 ( .A(n6064), .B(n706), .Y(n6454) );
OAI22X1TS U6535 ( .A0(n817), .A1(n6065), .B0(n6454), .B1(n3928), .Y(n6529)
);
XNOR2X1TS U6536 ( .A(n5503), .B(n6652), .Y(n6481) );
OAI22X1TS U6537 ( .A0(n6482), .A1(n6066), .B0(n6480), .B1(n6481), .Y(n6528)
);
XNOR2X1TS U6538 ( .A(n626), .B(n6672), .Y(n6484) );
OAI22X1TS U6539 ( .A0(n6891), .A1(n6068), .B0(n6387), .B1(n6484), .Y(n6527)
);
XNOR2X1TS U6540 ( .A(n818), .B(n6363), .Y(n6458) );
OAI22X1TS U6541 ( .A0(n6459), .A1(n6070), .B0(n6138), .B1(n6458), .Y(n6505)
);
XNOR2X1TS U6542 ( .A(n6383), .B(n6851), .Y(n6486) );
OAI22X1TS U6543 ( .A0(n6731), .A1(n6072), .B0(n6663), .B1(n6486), .Y(n6504)
);
INVX6TS U6544 ( .A(n7015), .Y(n6933) );
XNOR2X1TS U6545 ( .A(n4497), .B(n6933), .Y(n6440) );
OAI22X1TS U6546 ( .A0(n4115), .A1(n6074), .B0(n6073), .B1(n6440), .Y(n6503)
);
ADDFHX4TS U6547 ( .A(n6077), .B(n6076), .CI(n6075), .CO(n7301), .S(n7299) );
OR2X8TS U6548 ( .A(n7302), .B(n7301), .Y(n7626) );
XNOR2X1TS U6549 ( .A(n7016), .B(n6403), .Y(n6334) );
XNOR2X1TS U6550 ( .A(n8214), .B(n3986), .Y(n6096) );
OAI22X1TS U6551 ( .A0(n7174), .A1(n6334), .B0(n6437), .B1(n6096), .Y(n6350)
);
XNOR2X1TS U6552 ( .A(n6404), .B(n6337), .Y(n6097) );
OAI22X1TS U6553 ( .A0(n6443), .A1(n6336), .B0(n6670), .B1(n6097), .Y(n6349)
);
OAI22X1TS U6554 ( .A0(n6459), .A1(n819), .B0(n6138), .B1(n6108), .Y(n6348)
);
OAI22X1TS U6555 ( .A0(n6886), .A1(n6096), .B0(n6746), .B1(n6124), .Y(n6176)
);
XNOR2X1TS U6556 ( .A(n6166), .B(n6364), .Y(n6098) );
OAI22X1TS U6557 ( .A0(n6202), .A1(n6098), .B0(n788), .B1(n6364), .Y(n6175)
);
XNOR2X1TS U6558 ( .A(n6404), .B(n6376), .Y(n6170) );
OAI22X1TS U6559 ( .A0(n6443), .A1(n6097), .B0(n6670), .B1(n6170), .Y(n6174)
);
XNOR2X1TS U6560 ( .A(n6329), .B(n6364), .Y(n6366) );
OAI22X1TS U6561 ( .A0(n702), .A1(n6366), .B0(n6098), .B1(n6365), .Y(n6116)
);
XNOR2X1TS U6562 ( .A(n795), .B(n6376), .Y(n6338) );
XNOR2X1TS U6563 ( .A(n8217), .B(n6652), .Y(n6102) );
OAI22X1TS U6564 ( .A0(n6478), .A1(n6338), .B0(n6476), .B1(n6102), .Y(n6115)
);
XNOR2X1TS U6565 ( .A(n6208), .B(n6742), .Y(n6113) );
XNOR2X1TS U6566 ( .A(n6208), .B(n4905), .Y(n6103) );
OAI22X1TS U6567 ( .A0(n6955), .A1(n6113), .B0(n6480), .B1(n6103), .Y(n6114)
);
XNOR2X1TS U6568 ( .A(n723), .B(n6672), .Y(n6134) );
OAI22X1TS U6569 ( .A0(n4780), .A1(n6134), .B0(n721), .B1(n6123), .Y(n6119)
);
XNOR2X1TS U6570 ( .A(n795), .B(n6647), .Y(n6172) );
OAI22X1TS U6571 ( .A0(n6478), .A1(n6102), .B0(n6476), .B1(n6172), .Y(n6118)
);
XNOR2X1TS U6572 ( .A(n797), .B(n5707), .Y(n6173) );
OAI22X1TS U6573 ( .A0(n6955), .A1(n6103), .B0(n6480), .B1(n6173), .Y(n6117)
);
OAI22X1TS U6574 ( .A0(n4938), .A1(n6105), .B0(n6126), .B1(n6984), .Y(n6121)
);
XNOR2X1TS U6575 ( .A(n6327), .B(n6933), .Y(n6106) );
INVX6TS U6576 ( .A(n7027), .Y(n6951) );
OAI22X1TS U6577 ( .A0(n6156), .A1(n6106), .B0(n6794), .B1(n6178), .Y(n6120)
);
XNOR2X1TS U6578 ( .A(n709), .B(n6378), .Y(n6132) );
XNOR2X1TS U6579 ( .A(n8813), .B(n6363), .Y(n6107) );
OAI22X1TS U6580 ( .A0(n6419), .A1(n6132), .B0(n735), .B1(n6107), .Y(n6110)
);
XNOR2X1TS U6581 ( .A(n6329), .B(n4419), .Y(n6167) );
OAI22X1TS U6582 ( .A0(n6419), .A1(n6107), .B0(n6167), .B1(n6300), .Y(n6165)
);
XNOR2X1TS U6583 ( .A(n770), .B(n6333), .Y(n6136) );
XNOR2X1TS U6584 ( .A(n7055), .B(n6403), .Y(n6180) );
AO21X1TS U6585 ( .A0(n6109), .A1(n6456), .B0(n6108), .Y(n6163) );
CMPR32X2TS U6586 ( .A(n6112), .B(n6111), .C(n6110), .CO(n6129), .S(n6375) );
XNOR2X1TS U6587 ( .A(n6987), .B(n6652), .Y(n6377) );
XNOR2X1TS U6588 ( .A(n6842), .B(n6647), .Y(n6135) );
OAI22X1TS U6589 ( .A0(n4780), .A1(n6377), .B0(n721), .B1(n6135), .Y(n6410)
);
XNOR2X1TS U6590 ( .A(n6100), .B(n6672), .Y(n6385) );
OAI22X1TS U6591 ( .A0(n6955), .A1(n6385), .B0(n2979), .B1(n6113), .Y(n6409)
);
XNOR2X1TS U6592 ( .A(n6143), .B(n6775), .Y(n6386) );
XNOR2X1TS U6593 ( .A(n6143), .B(n5707), .Y(n6151) );
OAI22X1TS U6594 ( .A0(n6891), .A1(n6386), .B0(n6387), .B1(n6151), .Y(n6408)
);
CMPR32X2TS U6595 ( .A(n6116), .B(n6115), .C(n6114), .CO(n6157), .S(n6373) );
CMPR32X2TS U6596 ( .A(n6119), .B(n6118), .C(n6117), .CO(n6230), .S(n6362) );
XNOR2X1TS U6597 ( .A(n6143), .B(n6887), .Y(n6144) );
XNOR2X1TS U6598 ( .A(n6686), .B(n6933), .Y(n6224) );
OAI22X1TS U6599 ( .A0(n6225), .A1(n6144), .B0(n6145), .B1(n6224), .Y(n6221)
);
CMPR32X2TS U6600 ( .A(n6122), .B(n6121), .C(n6120), .CO(n6220), .S(n6130) );
OAI22X1TS U6601 ( .A0(n6127), .A1(n6126), .B0(n6227), .B1(n6984), .Y(n6234)
);
INVX2TS U6602 ( .A(n6234), .Y(n6187) );
XNOR2X1TS U6603 ( .A(n709), .B(n6131), .Y(n6372) );
OAI22X1TS U6604 ( .A0(n6419), .A1(n6372), .B0(n735), .B1(n6132), .Y(n6341)
);
XNOR2X1TS U6605 ( .A(n770), .B(n6133), .Y(n6331) );
XNOR2X1TS U6606 ( .A(n680), .B(n6400), .Y(n6137) );
OAI22X1TS U6607 ( .A0(n6719), .A1(n6331), .B0(n6179), .B1(n6137), .Y(n6340)
);
OAI22X1TS U6608 ( .A0(n6988), .A1(n6135), .B0(n721), .B1(n6134), .Y(n6142)
);
XNOR2X1TS U6609 ( .A(n6383), .B(n6951), .Y(n6139) );
XNOR2X1TS U6610 ( .A(n6222), .B(n6973), .Y(n6146) );
OAI22X1TS U6611 ( .A0(n6731), .A1(n6139), .B0(n6663), .B1(n6146), .Y(n6141)
);
OAI22X1TS U6612 ( .A0(n6719), .A1(n6137), .B0(n740), .B1(n6136), .Y(n6140)
);
XNOR2X1TS U6613 ( .A(n6166), .B(n8808), .Y(n6330) );
OAI22X1TS U6614 ( .A0(n6459), .A1(n6330), .B0(n6138), .B1(n818), .Y(n6390)
);
XNOR2X1TS U6615 ( .A(n5787), .B(n6933), .Y(n6384) );
OAI22X1TS U6616 ( .A0(n781), .A1(n6384), .B0(n6663), .B1(n6139), .Y(n6389)
);
XNOR2X1TS U6617 ( .A(n6168), .B(n6973), .Y(n6382) );
XNOR2X1TS U6618 ( .A(n778), .B(n7009), .Y(n6148) );
OAI22X1TS U6619 ( .A0(n4540), .A1(n6382), .B0(n683), .B1(n6148), .Y(n6388)
);
CMPR32X2TS U6620 ( .A(n6142), .B(n6141), .C(n6140), .CO(n6162), .S(n6343) );
XNOR2X1TS U6621 ( .A(n778), .B(n7034), .Y(n6147) );
XNOR2X1TS U6622 ( .A(n8805), .B(n7054), .Y(n6169) );
OAI22X1TS U6623 ( .A0(n6716), .A1(n6147), .B0(n683), .B1(n6169), .Y(n6183)
);
XNOR2X1TS U6624 ( .A(n6143), .B(n6851), .Y(n6150) );
XNOR2X1TS U6625 ( .A(n4813), .B(n7009), .Y(n6171) );
OAI22X1TS U6626 ( .A0(n781), .A1(n6146), .B0(n6663), .B1(n6171), .Y(n6181)
);
OAI22X1TS U6627 ( .A0(n724), .A1(n6148), .B0(n683), .B1(n6147), .Y(n6353) );
OAI22X1TS U6628 ( .A0(n6860), .A1(n6151), .B0(n6859), .B1(n6150), .Y(n6352)
);
OAI22X1TS U6629 ( .A0(n6948), .A1(n6415), .B0(n6153), .B1(n6984), .Y(n6369)
);
OAI22X1TS U6630 ( .A0(n6154), .A1(n6153), .B0(n6152), .B1(n6984), .Y(n6368)
);
XNOR2X1TS U6631 ( .A(n8809), .B(n6851), .Y(n6328) );
OAI22X1TS U6632 ( .A0(n6156), .A1(n6328), .B0(n787), .B1(n6155), .Y(n6367)
);
CMPR32X2TS U6633 ( .A(n6159), .B(n6158), .C(n6157), .CO(n6186), .S(n6354) );
CMPR32X2TS U6634 ( .A(n6162), .B(n6161), .C(n6160), .CO(n6212), .S(n6355) );
CMPR32X2TS U6635 ( .A(n6165), .B(n6164), .C(n6163), .CO(n6215), .S(n6128) );
XNOR2X1TS U6636 ( .A(n6166), .B(n8813), .Y(n6216) );
OAI22X1TS U6637 ( .A0(n6419), .A1(n6167), .B0(n6216), .B1(n6300), .Y(n6205)
);
XNOR2X1TS U6638 ( .A(n778), .B(n7133), .Y(n6218) );
OAI22X1TS U6639 ( .A0(n4115), .A1(n6169), .B0(n683), .B1(n6218), .Y(n6204)
);
XNOR2X1TS U6640 ( .A(n6404), .B(n6652), .Y(n6217) );
OAI22X1TS U6641 ( .A0(n6443), .A1(n6170), .B0(n6670), .B1(n6217), .Y(n6203)
);
XNOR2X1TS U6642 ( .A(n4813), .B(n7034), .Y(n6223) );
OAI22X1TS U6643 ( .A0(n3127), .A1(n6171), .B0(n6663), .B1(n6223), .Y(n6195)
);
BUFX3TS U6644 ( .A(n6666), .Y(n7057) );
XNOR2X1TS U6645 ( .A(n795), .B(n6672), .Y(n6207) );
OAI22X1TS U6646 ( .A0(n7057), .A1(n6172), .B0(n6476), .B1(n6207), .Y(n6194)
);
XNOR2X1TS U6647 ( .A(n5503), .B(n6851), .Y(n6209) );
OAI22X1TS U6648 ( .A0(n6930), .A1(n6173), .B0(n6929), .B1(n6209), .Y(n6193)
);
CMPR32X2TS U6649 ( .A(n6176), .B(n6175), .C(n6174), .CO(n6198), .S(n6158) );
XNOR2X1TS U6650 ( .A(n703), .B(n6973), .Y(n6206) );
OAI22X1TS U6651 ( .A0(n6741), .A1(n6178), .B0(n6794), .B1(n6206), .Y(n6192)
);
OAI22X1TS U6652 ( .A0(n6463), .A1(n6364), .B0(n788), .B1(n6201), .Y(n6191)
);
XNOR2X1TS U6653 ( .A(n770), .B(n6335), .Y(n6200) );
OAI22X1TS U6654 ( .A0(n6719), .A1(n6180), .B0(n6179), .B1(n6200), .Y(n6190)
);
CMPR32X2TS U6655 ( .A(n6183), .B(n6182), .C(n6181), .CO(n6196), .S(n6161) );
ADDFHX1TS U6656 ( .A(n6186), .B(n6185), .CI(n6184), .CO(n6399), .S(n6394) );
CMPR32X2TS U6657 ( .A(n6189), .B(n6188), .C(n6187), .CO(n6244), .S(n6219) );
CMPR32X2TS U6658 ( .A(n6195), .B(n6194), .C(n6193), .CO(n6242), .S(n6213) );
CMPR32X2TS U6659 ( .A(n6198), .B(n6197), .C(n6196), .CO(n6257), .S(n6210) );
XNOR2X1TS U6660 ( .A(n723), .B(n6823), .Y(n6238) );
OAI22X1TS U6661 ( .A0(n4055), .A1(n6199), .B0(n720), .B1(n6238), .Y(n6241)
);
OAI22X1TS U6662 ( .A0(n6719), .A1(n6200), .B0(n738), .B1(n6251), .Y(n6240)
);
XNOR2X1TS U6663 ( .A(n6660), .B(n7009), .Y(n6249) );
OAI22X1TS U6664 ( .A0(n6741), .A1(n6206), .B0(n6794), .B1(n6249), .Y(n6261)
);
XNOR2X1TS U6665 ( .A(n6931), .B(n6742), .Y(n6253) );
OAI22X1TS U6666 ( .A0(n7057), .A1(n6207), .B0(n731), .B1(n6253), .Y(n6260)
);
XNOR2X1TS U6667 ( .A(n6208), .B(n6887), .Y(n6255) );
OAI22X1TS U6668 ( .A0(n6309), .A1(n6209), .B0(n6254), .B1(n6255), .Y(n6259)
);
CMPR32X2TS U6669 ( .A(n6212), .B(n6211), .C(n6210), .CO(n6276), .S(n6395) );
CMPR32X2TS U6670 ( .A(n6215), .B(n6214), .C(n6213), .CO(n6233), .S(n6211) );
OAI22X1TS U6671 ( .A0(n6419), .A1(n6216), .B0(n735), .B1(n8813), .Y(n6247)
);
XNOR2X1TS U6672 ( .A(n7142), .B(n6647), .Y(n6265) );
OAI22X1TS U6673 ( .A0(n6443), .A1(n6217), .B0(n6670), .B1(n6265), .Y(n6246)
);
INVX4TS U6674 ( .A(n7183), .Y(n7156) );
XNOR2X1TS U6675 ( .A(n7156), .B(n778), .Y(n6263) );
OAI22X1TS U6676 ( .A0(n699), .A1(n6218), .B0(n6263), .B1(n6651), .Y(n6245)
);
XNOR2X1TS U6677 ( .A(n6662), .B(n7054), .Y(n6252) );
OAI22X1TS U6678 ( .A0(n6487), .A1(n6223), .B0(n6663), .B1(n6252), .Y(n6268)
);
XNOR2X1TS U6679 ( .A(n6686), .B(n6951), .Y(n6250) );
OAI22X1TS U6680 ( .A0(n6225), .A1(n6224), .B0(n6859), .B1(n6250), .Y(n6267)
);
OAI22X1TS U6681 ( .A0(n4938), .A1(n6227), .B0(n6237), .B1(n6829), .Y(n6235)
);
CMPR32X2TS U6682 ( .A(n6230), .B(n6229), .C(n6228), .CO(n6231), .S(n6184) );
OAI22X1TS U6683 ( .A0(n6419), .A1(n709), .B0(n734), .B1(n6299), .Y(n6314) );
OAI22X1TS U6684 ( .A0(n4938), .A1(n6237), .B0(n6311), .B1(n6829), .Y(n6734)
);
INVX2TS U6685 ( .A(n6734), .Y(n6313) );
XNOR2X1TS U6686 ( .A(n6987), .B(n6851), .Y(n6297) );
OAI22X1TS U6687 ( .A0(n4780), .A1(n6238), .B0(n6986), .B1(n6297), .Y(n6312)
);
CMPR32X2TS U6688 ( .A(n6244), .B(n6243), .C(n6242), .CO(n6322), .S(n6258) );
CMPR32X2TS U6689 ( .A(n6247), .B(n6246), .C(n6245), .CO(n6320), .S(n6274) );
XNOR2X1TS U6690 ( .A(n4797), .B(n7034), .Y(n6302) );
OAI22X1TS U6691 ( .A0(n6741), .A1(n6249), .B0(n6794), .B1(n6302), .Y(n6286)
);
XNOR2X1TS U6692 ( .A(n6686), .B(n6973), .Y(n6290) );
XNOR2X1TS U6693 ( .A(n770), .B(n6337), .Y(n6298) );
OAI22X1TS U6694 ( .A0(n6719), .A1(n6251), .B0(n739), .B1(n6298), .Y(n6284)
);
XNOR2X1TS U6695 ( .A(n6222), .B(n7133), .Y(n6304) );
OAI22X1TS U6696 ( .A0(n6487), .A1(n6252), .B0(n6663), .B1(n6304), .Y(n6289)
);
XNOR2X1TS U6697 ( .A(n6667), .B(n4905), .Y(n6292) );
OAI22X1TS U6698 ( .A0(n7057), .A1(n6253), .B0(n6476), .B1(n6292), .Y(n6288)
);
XNOR2X1TS U6699 ( .A(n6208), .B(n6933), .Y(n6308) );
OAI22X1TS U6700 ( .A0(n6309), .A1(n6255), .B0(n6254), .B1(n6308), .Y(n6287)
);
CMPR32X2TS U6701 ( .A(n6258), .B(n6257), .C(n6256), .CO(n6306), .S(n6277) );
CMPR32X2TS U6702 ( .A(n6261), .B(n6260), .C(n6259), .CO(n6283), .S(n6269) );
INVX4TS U6703 ( .A(n7331), .Y(n7168) );
OAI22X1TS U6704 ( .A0(n4115), .A1(n6263), .B0(n6303), .B1(n6651), .Y(n6294)
);
XNOR2X1TS U6705 ( .A(n7142), .B(n6672), .Y(n6291) );
OAI22X1TS U6706 ( .A0(n6264), .A1(n6265), .B0(n6670), .B1(n6291), .Y(n6293)
);
CMPR32X2TS U6707 ( .A(n6268), .B(n6267), .C(n6266), .CO(n6281), .S(n6272) );
CMPR32X2TS U6708 ( .A(n6271), .B(n6270), .C(n6269), .CO(n6325), .S(n6256) );
CMPR32X2TS U6709 ( .A(n6274), .B(n6273), .C(n6272), .CO(n6324), .S(n6232) );
CMPR32X2TS U6710 ( .A(n6283), .B(n6282), .C(n6281), .CO(n7087), .S(n6326) );
CMPR32X2TS U6711 ( .A(n6286), .B(n6285), .C(n6284), .CO(n7066), .S(n6319) );
CMPR32X2TS U6712 ( .A(n6289), .B(n6288), .C(n6287), .CO(n7065), .S(n6318) );
XNOR2X1TS U6713 ( .A(n6686), .B(n7009), .Y(n6733) );
OAI22X1TS U6714 ( .A0(n6860), .A1(n6290), .B0(n6859), .B1(n6733), .Y(n6722)
);
XNOR2X1TS U6715 ( .A(n6404), .B(n6742), .Y(n6671) );
OAI22X1TS U6716 ( .A0(n6649), .A1(n6291), .B0(n6019), .B1(n6671), .Y(n6721)
);
XNOR2X1TS U6717 ( .A(n6667), .B(n5707), .Y(n6668) );
OAI22X1TS U6718 ( .A0(n7057), .A1(n6292), .B0(n6476), .B1(n6668), .Y(n6720)
);
XNOR2X1TS U6719 ( .A(n723), .B(n6887), .Y(n6678) );
OAI22X1TS U6720 ( .A0(n6988), .A1(n6297), .B0(n6677), .B1(n6678), .Y(n6711)
);
XNOR2X1TS U6721 ( .A(n770), .B(n6376), .Y(n6718) );
OAI22X1TS U6722 ( .A0(n6719), .A1(n6298), .B0(n739), .B1(n6718), .Y(n6710)
);
XNOR2X1TS U6723 ( .A(n638), .B(n7054), .Y(n6713) );
OAI22X1TS U6724 ( .A0(n6741), .A1(n6302), .B0(n787), .B1(n6713), .Y(n6705)
);
OAI22X1TS U6725 ( .A0(n699), .A1(n6303), .B0(n683), .B1(n8209), .Y(n6704) );
XNOR2X1TS U6726 ( .A(n7156), .B(n4813), .Y(n6730) );
OAI22X1TS U6727 ( .A0(n6731), .A1(n6304), .B0(n6730), .B1(n6745), .Y(n6703)
);
XNOR2X1TS U6728 ( .A(n797), .B(n6951), .Y(n6665) );
OAI22X1TS U6729 ( .A0(n6309), .A1(n6308), .B0(n6929), .B1(n6665), .Y(n7081)
);
OAI22X1TS U6730 ( .A0(n4938), .A1(n6311), .B0(n658), .B1(n6829), .Y(n6735)
);
CMPR32X2TS U6731 ( .A(n6317), .B(n6316), .C(n6315), .CO(n7074), .S(n6323) );
CMPR32X2TS U6732 ( .A(n6320), .B(n6319), .C(n6318), .CO(n7073), .S(n6321) );
CMPR32X2TS U6733 ( .A(n6323), .B(n6322), .C(n6321), .CO(n7062), .S(n6307) );
CMPR32X2TS U6734 ( .A(n6326), .B(n6325), .C(n6324), .CO(n7061), .S(n6305) );
XNOR2X1TS U6735 ( .A(n703), .B(n6823), .Y(n6423) );
OAI22X1TS U6736 ( .A0(n6741), .A1(n6423), .B0(n787), .B1(n6328), .Y(n6435)
);
XNOR2X1TS U6737 ( .A(n6329), .B(n8808), .Y(n6457) );
OAI22X1TS U6738 ( .A0(n6459), .A1(n6457), .B0(n6330), .B1(n6456), .Y(n6434)
);
XNOR2X1TS U6739 ( .A(n770), .B(n752), .Y(n6425) );
OAI22X1TS U6740 ( .A0(n6953), .A1(n6425), .B0(n6332), .B1(n6331), .Y(n6433)
);
XNOR2X1TS U6741 ( .A(n698), .B(n6333), .Y(n6402) );
OAI22X1TS U6742 ( .A0(n6772), .A1(n6402), .B0(n6746), .B1(n6334), .Y(n6347)
);
XNOR2X1TS U6743 ( .A(n8217), .B(n6337), .Y(n6407) );
OAI22X1TS U6744 ( .A0(n6478), .A1(n6407), .B0(n6476), .B1(n6338), .Y(n6345)
);
CMPR32X2TS U6745 ( .A(n6341), .B(n6340), .C(n6339), .CO(n6344), .S(n6470) );
CMPR32X2TS U6746 ( .A(n6347), .B(n6346), .C(n6345), .CO(n6359), .S(n6471) );
CMPR32X2TS U6747 ( .A(n6350), .B(n6349), .C(n6348), .CO(n6159), .S(n6358) );
CMPR32X2TS U6748 ( .A(n6353), .B(n6352), .C(n6351), .CO(n6160), .S(n6357) );
CMPR32X2TS U6749 ( .A(n6359), .B(n6358), .C(n6357), .CO(n6393), .S(n6450) );
CMPR32X2TS U6750 ( .A(n6362), .B(n6361), .C(n6360), .CO(n6185), .S(n6392) );
XNOR2X1TS U6751 ( .A(n6364), .B(n6363), .Y(n6380) );
OAI22X1TS U6752 ( .A0(n633), .A1(n6380), .B0(n6366), .B1(n6365), .Y(n6413)
);
CMPR32X2TS U6753 ( .A(n6369), .B(n6368), .C(n6367), .CO(n6351), .S(n6412) );
INVX2TS U6754 ( .A(n6369), .Y(n6422) );
OAI22X1TS U6755 ( .A0(n1663), .A1(n706), .B0(n6453), .B1(n6370), .Y(n6421)
);
OAI22X1TS U6756 ( .A0(n6419), .A1(n6417), .B0(n735), .B1(n6372), .Y(n6420)
);
XNOR2X1TS U6757 ( .A(n6842), .B(n6376), .Y(n6473) );
OAI22X1TS U6758 ( .A0(n812), .A1(n6473), .B0(n720), .B1(n6377), .Y(n6466) );
XNOR2X1TS U6759 ( .A(n6379), .B(n6378), .Y(n6460) );
XNOR2X1TS U6760 ( .A(n778), .B(n6951), .Y(n6439) );
OAI22X1TS U6761 ( .A0(n724), .A1(n6439), .B0(n683), .B1(n6382), .Y(n6464) );
XNOR2X1TS U6762 ( .A(n5787), .B(n6887), .Y(n6485) );
OAI22X1TS U6763 ( .A0(n3127), .A1(n6485), .B0(n690), .B1(n6384), .Y(n6432)
);
XNOR2X1TS U6764 ( .A(n6100), .B(n6647), .Y(n6479) );
OAI22X1TS U6765 ( .A0(n6955), .A1(n6479), .B0(n6480), .B1(n6385), .Y(n6431)
);
XNOR2X1TS U6766 ( .A(n6642), .B(n6742), .Y(n6483) );
OAI22X1TS U6767 ( .A0(n6891), .A1(n6483), .B0(n6387), .B1(n6386), .Y(n6430)
);
CMPR32X2TS U6768 ( .A(n6390), .B(n6389), .C(n6388), .CO(n6342), .S(n6444) );
ADDFHX2TS U6769 ( .A(n6393), .B(n6392), .CI(n6391), .CO(n6570), .S(n6521) );
OR2X4TS U6770 ( .A(n7203), .B(n7202), .Y(n7456) );
XNOR2X1TS U6771 ( .A(n8214), .B(n6400), .Y(n6436) );
OAI22X1TS U6772 ( .A0(n688), .A1(n6436), .B0(n6746), .B1(n6402), .Y(n6469)
);
XNOR2X1TS U6773 ( .A(n6404), .B(n6403), .Y(n6441) );
OAI22X1TS U6774 ( .A0(n6443), .A1(n6441), .B0(n6406), .B1(n6405), .Y(n6468)
);
OAI22X1TS U6775 ( .A0(n6478), .A1(n6475), .B0(n6476), .B1(n6407), .Y(n6467)
);
CMPR32X2TS U6776 ( .A(n6410), .B(n6409), .C(n6408), .CO(n6374), .S(n6495) );
CMPR32X2TS U6777 ( .A(n6413), .B(n6412), .C(n6411), .CO(n6449), .S(n6494) );
OAI22X1TS U6778 ( .A0(n6948), .A1(n6416), .B0(n6415), .B1(n6414), .Y(n6489)
);
OAI22X1TS U6779 ( .A0(n6419), .A1(n6418), .B0(n734), .B1(n6417), .Y(n6488)
);
CMPR32X2TS U6780 ( .A(n6422), .B(n6421), .C(n6420), .CO(n6411), .S(n6492) );
OAI22X1TS U6781 ( .A0(n6827), .A1(n6424), .B0(n6826), .B1(n6423), .Y(n6511)
);
OAI22X1TS U6782 ( .A0(n6953), .A1(n6426), .B0(n738), .B1(n6425), .Y(n6510)
);
OAI22X1TS U6783 ( .A0(n688), .A1(n6438), .B0(n6437), .B1(n6436), .Y(n6535)
);
OAI22X1TS U6784 ( .A0(n714), .A1(n6440), .B0(n683), .B1(n6439), .Y(n6534) );
OAI22X1TS U6785 ( .A0(n6443), .A1(n6442), .B0(n6670), .B1(n6441), .Y(n6533)
);
CMPR32X2TS U6786 ( .A(n6446), .B(n6445), .C(n6444), .CO(n6447), .S(n6518) );
CMPR32X2TS U6787 ( .A(n6449), .B(n6448), .C(n6447), .CO(n6391), .S(n6524) );
OAI22X1TS U6788 ( .A0(n817), .A1(n6454), .B0(n6453), .B1(n694), .Y(n6514) );
OAI22X1TS U6789 ( .A0(n6459), .A1(n6458), .B0(n6457), .B1(n6456), .Y(n6513)
);
OAI22X1TS U6790 ( .A0(n633), .A1(n6462), .B0(n6365), .B1(n6460), .Y(n6512)
);
CMPR32X2TS U6791 ( .A(n6466), .B(n6465), .C(n6464), .CO(n6446), .S(n6537) );
CMPR32X2TS U6792 ( .A(n6469), .B(n6468), .C(n6467), .CO(n6496), .S(n6536) );
OAI22X1TS U6793 ( .A0(n6988), .A1(n6474), .B0(n720), .B1(n6473), .Y(n6532)
);
OAI22X1TS U6794 ( .A0(n6478), .A1(n6477), .B0(n6476), .B1(n6475), .Y(n6531)
);
OAI22X1TS U6795 ( .A0(n813), .A1(n6481), .B0(n6480), .B1(n6479), .Y(n6530)
);
OAI22X1TS U6796 ( .A0(n6891), .A1(n6484), .B0(n6890), .B1(n6483), .Y(n6544)
);
OAI22X1TS U6797 ( .A0(n6731), .A1(n6486), .B0(n690), .B1(n6485), .Y(n6543)
);
CMPR32X2TS U6798 ( .A(n6496), .B(n6495), .C(n6494), .CO(n6526), .S(n6631) );
CMPR32X2TS U6799 ( .A(n6499), .B(n6498), .C(n6497), .CO(n6547), .S(n6539) );
CMPR32X2TS U6800 ( .A(n6502), .B(n6501), .C(n6500), .CO(n6546), .S(n6591) );
CMPR32X2TS U6801 ( .A(n6505), .B(n6504), .C(n6503), .CO(n6545), .S(n6557) );
CMPR32X2TS U6802 ( .A(n6508), .B(n6507), .C(n6506), .CO(n6562), .S(n6593) );
ADDFHX1TS U6803 ( .A(n6511), .B(n6510), .CI(n6509), .CO(n6491), .S(n6561) );
CMPR32X2TS U6804 ( .A(n6514), .B(n6513), .C(n6512), .CO(n6538), .S(n6560) );
CMPR32X2TS U6805 ( .A(n6517), .B(n6516), .C(n6515), .CO(n6519), .S(n6554) );
CMPR32X2TS U6806 ( .A(n6529), .B(n6528), .C(n6527), .CO(n6565), .S(n6558) );
CMPR32X2TS U6807 ( .A(n6532), .B(n6531), .C(n6530), .CO(n6553), .S(n6564) );
CMPR32X2TS U6808 ( .A(n6535), .B(n6534), .C(n6533), .CO(n6515), .S(n6563) );
ADDFX2TS U6809 ( .A(n6538), .B(n6537), .CI(n6536), .CO(n6550), .S(n6615) );
CMPR32X2TS U6810 ( .A(n6553), .B(n6552), .C(n6551), .CO(n6548), .S(n6619) );
ADDFHX2TS U6811 ( .A(n6556), .B(n6555), .CI(n6554), .CO(n6630), .S(n6618) );
CMPR32X2TS U6812 ( .A(n6559), .B(n6558), .C(n6557), .CO(n6589), .S(n6584) );
CMPR32X2TS U6813 ( .A(n6562), .B(n6561), .C(n6560), .CO(n6555), .S(n6588) );
CMPR32X2TS U6814 ( .A(n6565), .B(n6564), .C(n6563), .CO(n6616), .S(n6587) );
ADDFHX4TS U6815 ( .A(n6574), .B(n6573), .CI(n6572), .CO(n7197), .S(n7196) );
CMPR32X2TS U6816 ( .A(n6583), .B(n6582), .C(n6581), .CO(n6614), .S(n6610) );
CMPR32X2TS U6817 ( .A(n6592), .B(n6591), .C(n6590), .CO(n6613), .S(n6585) );
CMPR32X2TS U6818 ( .A(n6595), .B(n6594), .C(n6593), .CO(n6612), .S(n6600) );
ADDFHX2TS U6819 ( .A(n6598), .B(n6597), .CI(n6596), .CO(n6611), .S(n6599) );
CMPR32X2TS U6820 ( .A(n6610), .B(n6609), .C(n6608), .CO(n6624), .S(n6621) );
CMPR32X2TS U6821 ( .A(n6613), .B(n6612), .C(n6611), .CO(n6628), .S(n6607) );
ADDFHX2TS U6822 ( .A(n6619), .B(n6618), .CI(n6617), .CO(n6632), .S(n6626) );
ADDFHX2TS U6823 ( .A(n6631), .B(n6630), .CI(n6629), .CO(n6566), .S(n6639) );
OR2X4TS U6824 ( .A(n7221), .B(n7220), .Y(n7778) );
NAND2X6TS U6825 ( .A(n7226), .B(n7450), .Y(n6641) );
XNOR2X1TS U6826 ( .A(n6642), .B(n7133), .Y(n6648) );
XNOR2X1TS U6827 ( .A(n7156), .B(n626), .Y(n6774) );
OAI22X1TS U6828 ( .A0(n6860), .A1(n6648), .B0(n6774), .B1(n6890), .Y(n6786)
);
XNOR2X1TS U6829 ( .A(n797), .B(n7034), .Y(n6692) );
XNOR2X1TS U6830 ( .A(n797), .B(n7054), .Y(n6777) );
OAI22X1TS U6831 ( .A0(n6930), .A1(n6692), .B0(n6929), .B1(n6777), .Y(n6785)
);
OAI22X1TS U6832 ( .A0(n7752), .A1(n6643), .B0(n6793), .B1(n6829), .Y(n6791)
);
XNOR2X1TS U6833 ( .A(n6987), .B(n6973), .Y(n6645) );
XNOR2X1TS U6834 ( .A(n723), .B(n7009), .Y(n6796) );
OAI22X1TS U6835 ( .A0(n6679), .A1(n6645), .B0(n6986), .B1(n6796), .Y(n6790)
);
INVX2TS U6836 ( .A(n6792), .Y(n6699) );
XNOR2X1TS U6837 ( .A(n6401), .B(n6742), .Y(n6673) );
XNOR2X1TS U6838 ( .A(n698), .B(n6032), .Y(n6747) );
XNOR2X1TS U6839 ( .A(n6987), .B(n6951), .Y(n6650) );
OAI22X1TS U6840 ( .A0(n6988), .A1(n6650), .B0(n6986), .B1(n6645), .Y(n6697)
);
XNOR2X1TS U6841 ( .A(n7156), .B(n4797), .Y(n6661) );
XNOR2X1TS U6842 ( .A(n7168), .B(n703), .Y(n6740) );
OAI22X1TS U6843 ( .A0(n6741), .A1(n6661), .B0(n6740), .B1(n6826), .Y(n6656)
);
BUFX3TS U6844 ( .A(n6646), .Y(n7333) );
XNOR2X1TS U6845 ( .A(n681), .B(n6647), .Y(n6653) );
XNOR2X1TS U6846 ( .A(n681), .B(n6672), .Y(n6743) );
OAI22X1TS U6847 ( .A0(n7333), .A1(n6653), .B0(n739), .B1(n6743), .Y(n6654)
);
XNOR2X1TS U6848 ( .A(n6686), .B(n7054), .Y(n6687) );
OAI22X1TS U6849 ( .A0(n6860), .A1(n6687), .B0(n6859), .B1(n6648), .Y(n6659)
);
BUFX4TS U6850 ( .A(n6649), .Y(n7143) );
XNOR2X1TS U6851 ( .A(n794), .B(n5707), .Y(n6664) );
XNOR2X1TS U6852 ( .A(n794), .B(n6851), .Y(n6748) );
OAI22X1TS U6853 ( .A0(n7143), .A1(n6664), .B0(n7141), .B1(n6748), .Y(n6658)
);
XNOR2X1TS U6854 ( .A(n6667), .B(n6887), .Y(n6688) );
XNOR2X1TS U6855 ( .A(n795), .B(n6933), .Y(n6749) );
OAI22X1TS U6856 ( .A0(n6750), .A1(n6688), .B0(n731), .B1(n6749), .Y(n6657)
);
XNOR2X1TS U6857 ( .A(n6987), .B(n6933), .Y(n6676) );
OAI22X1TS U6858 ( .A0(n4055), .A1(n6676), .B0(n6986), .B1(n6650), .Y(n6682)
);
XNOR2X1TS U6859 ( .A(n630), .B(n6652), .Y(n6717) );
OAI22X1TS U6860 ( .A0(n6719), .A1(n6717), .B0(n738), .B1(n6653), .Y(n6680)
);
CMPR32X2TS U6861 ( .A(n6656), .B(n6655), .C(n6654), .CO(n6788), .S(n6761) );
CMPR32X2TS U6862 ( .A(n6659), .B(n6658), .C(n6657), .CO(n6787), .S(n6760) );
XNOR2X1TS U6863 ( .A(n6660), .B(n7133), .Y(n6712) );
OAI22X1TS U6864 ( .A0(n6741), .A1(n6712), .B0(n6661), .B1(n6826), .Y(n6685)
);
XNOR2X1TS U6865 ( .A(n7168), .B(n6222), .Y(n6729) );
OAI22X1TS U6866 ( .A0(n5724), .A1(n6729), .B0(n6663), .B1(n6383), .Y(n6684)
);
XNOR2X1TS U6867 ( .A(n793), .B(n6775), .Y(n6669) );
OAI22X1TS U6868 ( .A0(n6649), .A1(n6669), .B0(n6670), .B1(n6664), .Y(n6683)
);
XNOR2X1TS U6869 ( .A(n797), .B(n6973), .Y(n6691) );
OAI22X1TS U6870 ( .A0(n6930), .A1(n6665), .B0(n6929), .B1(n6691), .Y(n6708)
);
XNOR2X1TS U6871 ( .A(n6667), .B(n6851), .Y(n6689) );
OAI22X1TS U6872 ( .A0(n7029), .A1(n6668), .B0(n732), .B1(n6689), .Y(n6707)
);
OAI22X1TS U6873 ( .A0(n6649), .A1(n6671), .B0(n6670), .B1(n6669), .Y(n6706)
);
OAI22X1TS U6874 ( .A0(n7752), .A1(n621), .B0(n657), .B1(n6829), .Y(n6695) );
XNOR2X1TS U6875 ( .A(n6401), .B(n6672), .Y(n6674) );
OAI22X1TS U6876 ( .A0(n6886), .A1(n6674), .B0(n7173), .B1(n6673), .Y(n6694)
);
INVX2TS U6877 ( .A(n6696), .Y(n6702) );
OAI22X1TS U6878 ( .A0(n6886), .A1(n6675), .B0(n6746), .B1(n6674), .Y(n6701)
);
OAI22X1TS U6879 ( .A0(n6679), .A1(n6678), .B0(n6677), .B1(n6676), .Y(n6700)
);
CMPR32X2TS U6880 ( .A(n6685), .B(n6684), .C(n6683), .CO(n6739), .S(n7105) );
XNOR2X1TS U6881 ( .A(n6686), .B(n7034), .Y(n6732) );
OAI22X1TS U6882 ( .A0(n6860), .A1(n6732), .B0(n6859), .B1(n6687), .Y(n6728)
);
XNOR2X1TS U6883 ( .A(n797), .B(n7009), .Y(n6693) );
OAI22X1TS U6884 ( .A0(n6930), .A1(n6691), .B0(n6929), .B1(n6693), .Y(n6726)
);
OAI22X1TS U6885 ( .A0(n6930), .A1(n6693), .B0(n6929), .B1(n6692), .Y(n6753)
);
CMPR32X2TS U6886 ( .A(n6696), .B(n6695), .C(n6694), .CO(n6752), .S(n6756) );
CMPR32X2TS U6887 ( .A(n6699), .B(n6698), .C(n6697), .CO(n6789), .S(n6751) );
CMPR32X2TS U6888 ( .A(n6702), .B(n6701), .C(n6700), .CO(n6755), .S(n7084) );
CMPR32X2TS U6889 ( .A(n6708), .B(n6707), .C(n6706), .CO(n7104), .S(n7082) );
CMPR32X2TS U6890 ( .A(n6711), .B(n6710), .C(n6709), .CO(n7072), .S(n7068) );
OAI22X1TS U6891 ( .A0(n6741), .A1(n6713), .B0(n787), .B1(n6712), .Y(n6725)
);
OAI22X1TS U6892 ( .A0(n4540), .A1(n8805), .B0(n683), .B1(n6714), .Y(n6724)
);
OAI22X1TS U6893 ( .A0(n6719), .A1(n6718), .B0(n740), .B1(n6717), .Y(n6723)
);
CMPR32X2TS U6894 ( .A(n6722), .B(n6721), .C(n6720), .CO(n7070), .S(n7064) );
OAI22X1TS U6895 ( .A0(n6487), .A1(n6730), .B0(n6729), .B1(n6745), .Y(n7078)
);
OAI22X1TS U6896 ( .A0(n6860), .A1(n6733), .B0(n6859), .B1(n6732), .Y(n7077)
);
CMPR32X2TS U6897 ( .A(n6739), .B(n6738), .C(n6737), .CO(n6768), .S(n7116) );
OAI22X1TS U6898 ( .A0(n6741), .A1(n6740), .B0(n787), .B1(n4797), .Y(n6799)
);
XNOR2X1TS U6899 ( .A(n630), .B(n6742), .Y(n6776) );
OAI22X1TS U6900 ( .A0(n7333), .A1(n6743), .B0(n7332), .B1(n6776), .Y(n6798)
);
XNOR2X1TS U6901 ( .A(n821), .B(n5707), .Y(n6773) );
OAI22X1TS U6902 ( .A0(n6125), .A1(n6747), .B0(n6746), .B1(n6773), .Y(n6771)
);
XNOR2X1TS U6903 ( .A(n793), .B(n6887), .Y(n6779) );
OAI22X1TS U6904 ( .A0(n6820), .A1(n6748), .B0(n6778), .B1(n6779), .Y(n6770)
);
XNOR2X1TS U6905 ( .A(n796), .B(n6951), .Y(n6780) );
OAI22X1TS U6906 ( .A0(n6750), .A1(n6749), .B0(n731), .B1(n6780), .Y(n6769)
);
CMPR32X2TS U6907 ( .A(n6753), .B(n6752), .C(n6751), .CO(n6781), .S(n6737) );
CMPR32X2TS U6908 ( .A(n6756), .B(n6755), .C(n6754), .CO(n7114), .S(n7103) );
CMPR32X2TS U6909 ( .A(n6759), .B(n6758), .C(n6757), .CO(n7113), .S(n7106) );
CMPR32X2TS U6910 ( .A(n6762), .B(n6761), .C(n6760), .CO(n6763), .S(n7112) );
CMPR32X2TS U6911 ( .A(n6765), .B(n6764), .C(n6763), .CO(n6802), .S(n7123) );
CMPR32X2TS U6912 ( .A(n6768), .B(n6767), .C(n6766), .CO(n6801), .S(n7121) );
CMPR32X2TS U6913 ( .A(n6771), .B(n6770), .C(n6769), .CO(n6811), .S(n6782) );
XNOR2X1TS U6914 ( .A(n821), .B(n6851), .Y(n6822) );
OAI22X1TS U6915 ( .A0(n7167), .A1(n6773), .B0(n7166), .B1(n6822), .Y(n6814)
);
XNOR2X1TS U6916 ( .A(n7168), .B(n626), .Y(n6818) );
OAI22X1TS U6917 ( .A0(n6860), .A1(n6774), .B0(n6818), .B1(n6890), .Y(n6813)
);
XNOR2X1TS U6918 ( .A(n770), .B(n4905), .Y(n6824) );
OAI22X1TS U6919 ( .A0(n7333), .A1(n6776), .B0(n738), .B1(n6824), .Y(n6812)
);
XNOR2X1TS U6920 ( .A(n6208), .B(n7133), .Y(n6828) );
OAI22X1TS U6921 ( .A0(n6930), .A1(n6777), .B0(n6929), .B1(n6828), .Y(n6817)
);
XNOR2X1TS U6922 ( .A(n6945), .B(n6933), .Y(n6819) );
OAI22X1TS U6923 ( .A0(n6820), .A1(n6779), .B0(n6778), .B1(n6819), .Y(n6816)
);
XNOR2X1TS U6924 ( .A(n8217), .B(n6973), .Y(n6821) );
OAI22X1TS U6925 ( .A0(n7029), .A1(n6780), .B0(n732), .B1(n6821), .Y(n6815)
);
CMPR32X2TS U6926 ( .A(n6783), .B(n6782), .C(n6781), .CO(n6807), .S(n6767) );
CMPR32X2TS U6927 ( .A(n6786), .B(n6785), .C(n6784), .CO(n6805), .S(n6765) );
CMPR32X2TS U6928 ( .A(n6789), .B(n6788), .C(n6787), .CO(n6804), .S(n6764) );
CMPR32X2TS U6929 ( .A(n6792), .B(n6791), .C(n6790), .CO(n6837), .S(n6784) );
INVX2TS U6930 ( .A(n6864), .Y(n6834) );
XNOR2X1TS U6931 ( .A(n723), .B(n7034), .Y(n6831) );
OAI22X1TS U6932 ( .A0(n812), .A1(n6796), .B0(n6986), .B1(n6831), .Y(n6832)
);
CMPR32X2TS U6933 ( .A(n6799), .B(n6798), .C(n6797), .CO(n6835), .S(n6783) );
NOR2X4TS U6934 ( .A(n7239), .B(n7240), .Y(n7716) );
INVX4TS U6935 ( .A(n7716), .Y(n7726) );
CMPR32X2TS U6936 ( .A(n6808), .B(n6807), .C(n6806), .CO(n6872), .S(n6800) );
CMPR32X2TS U6937 ( .A(n6811), .B(n6810), .C(n6809), .CO(n6870), .S(n6808) );
CMPR32X2TS U6938 ( .A(n6814), .B(n6813), .C(n6812), .CO(n6855), .S(n6810) );
CMPR32X2TS U6939 ( .A(n6817), .B(n6816), .C(n6815), .CO(n6854), .S(n6809) );
OAI22X1TS U6940 ( .A0(n6860), .A1(n6818), .B0(n6859), .B1(n626), .Y(n6858)
);
XNOR2X1TS U6941 ( .A(n6945), .B(n6951), .Y(n6848) );
OAI22X1TS U6942 ( .A0(n6820), .A1(n6819), .B0(n7141), .B1(n6848), .Y(n6857)
);
XNOR2X1TS U6943 ( .A(n795), .B(n7009), .Y(n6849) );
OAI22X1TS U6944 ( .A0(n7029), .A1(n6821), .B0(n731), .B1(n6849), .Y(n6856)
);
XNOR2X1TS U6945 ( .A(n821), .B(n6887), .Y(n6844) );
OAI22X1TS U6946 ( .A0(n6886), .A1(n6822), .B0(n7166), .B1(n6844), .Y(n6847)
);
XNOR2X1TS U6947 ( .A(n770), .B(n5707), .Y(n6852) );
OAI22X1TS U6948 ( .A0(n7333), .A1(n6824), .B0(n740), .B1(n6852), .Y(n6846)
);
XNOR2X1TS U6949 ( .A(n7156), .B(n797), .Y(n6861) );
OAI22X1TS U6950 ( .A0(n6930), .A1(n6828), .B0(n6861), .B1(n2979), .Y(n6867)
);
OAI22X1TS U6951 ( .A0(n7752), .A1(n6830), .B0(n6841), .B1(n6829), .Y(n6863)
);
XNOR2X1TS U6952 ( .A(n6296), .B(n7054), .Y(n6843) );
OAI22X1TS U6953 ( .A0(n7013), .A1(n6831), .B0(n6986), .B1(n6843), .Y(n6862)
);
CMPR32X2TS U6954 ( .A(n6834), .B(n6833), .C(n6832), .CO(n6865), .S(n6836) );
CMPR32X2TS U6955 ( .A(n6837), .B(n6836), .C(n6835), .CO(n6838), .S(n6803) );
OR2X4TS U6956 ( .A(n7242), .B(n7241), .Y(n7720) );
NAND2X4TS U6957 ( .A(n7726), .B(n7720), .Y(n7489) );
CMPR32X2TS U6958 ( .A(n6840), .B(n6839), .C(n6838), .CO(n6876), .S(n6868) );
OAI22X1TS U6959 ( .A0(n7752), .A1(n6841), .B0(n6880), .B1(n6984), .Y(n6916)
);
INVX2TS U6960 ( .A(n6916), .Y(n6884) );
XNOR2X1TS U6961 ( .A(n6842), .B(n7133), .Y(n6881) );
OAI22X1TS U6962 ( .A0(n812), .A1(n6843), .B0(n6986), .B1(n6881), .Y(n6883)
);
XNOR2X1TS U6963 ( .A(n701), .B(n6933), .Y(n6885) );
OAI22X1TS U6964 ( .A0(n6125), .A1(n6844), .B0(n785), .B1(n6885), .Y(n6882)
);
CMPR32X2TS U6965 ( .A(n6847), .B(n6846), .C(n6845), .CO(n6893), .S(n6840) );
XNOR2X1TS U6966 ( .A(n6945), .B(n6973), .Y(n6899) );
OAI22X1TS U6967 ( .A0(n7143), .A1(n6848), .B0(n7141), .B1(n6899), .Y(n6897)
);
XNOR2X1TS U6968 ( .A(n796), .B(n7034), .Y(n6900) );
OAI22X1TS U6969 ( .A0(n7029), .A1(n6849), .B0(n731), .B1(n6900), .Y(n6896)
);
XNOR2X1TS U6970 ( .A(n630), .B(n6851), .Y(n6888) );
OAI22X1TS U6971 ( .A0(n7185), .A1(n6852), .B0(n739), .B1(n6888), .Y(n6895)
);
CMPR32X2TS U6972 ( .A(n6855), .B(n6854), .C(n6853), .CO(n6905), .S(n6869) );
CMPR32X2TS U6973 ( .A(n6858), .B(n6857), .C(n6856), .CO(n6879), .S(n6853) );
OAI22X1TS U6974 ( .A0(n6860), .A1(n626), .B0(n6859), .B1(n1363), .Y(n6903)
);
XNOR2X1TS U6975 ( .A(n7168), .B(n5503), .Y(n6898) );
OAI22X1TS U6976 ( .A0(n6930), .A1(n6861), .B0(n6898), .B1(n2979), .Y(n6902)
);
CMPR32X2TS U6977 ( .A(n6867), .B(n6866), .C(n6865), .CO(n6877), .S(n6839) );
CMPR32X2TS U6978 ( .A(n6870), .B(n6869), .C(n6868), .CO(n6874), .S(n6871) );
CMPR32X2TS U6979 ( .A(n6873), .B(n6872), .C(n6871), .CO(n7246), .S(n7241) );
NOR2X4TS U6980 ( .A(n7245), .B(n7246), .Y(n7505) );
INVX4TS U6981 ( .A(n7505), .Y(n7499) );
CMPR32X2TS U6982 ( .A(n6876), .B(n6875), .C(n6874), .CO(n7248), .S(n7245) );
CMPR32X2TS U6983 ( .A(n6879), .B(n6878), .C(n6877), .CO(n6995), .S(n6904) );
OAI22X1TS U6984 ( .A0(n6948), .A1(n6880), .B0(n6917), .B1(n7184), .Y(n6915)
);
XNOR2X1TS U6985 ( .A(n7156), .B(n723), .Y(n6919) );
OAI22X1TS U6986 ( .A0(n812), .A1(n6881), .B0(n6919), .B1(n721), .Y(n6914) );
CMPR32X2TS U6987 ( .A(n6884), .B(n6883), .C(n6882), .CO(n6921), .S(n6894) );
XNOR2X1TS U6988 ( .A(n8214), .B(n6951), .Y(n6918) );
OAI22X1TS U6989 ( .A0(n6772), .A1(n6885), .B0(n7166), .B1(n6918), .Y(n6925)
);
CMPR32X2TS U6990 ( .A(n6894), .B(n6893), .C(n6892), .CO(n6911), .S(n6906) );
CMPR32X2TS U6991 ( .A(n6897), .B(n6896), .C(n6895), .CO(n6909), .S(n6892) );
OAI22X1TS U6992 ( .A0(n6930), .A1(n6898), .B0(n6929), .B1(n797), .Y(n6928)
);
OAI22X1TS U6993 ( .A0(n7143), .A1(n6899), .B0(n7141), .B1(n6913), .Y(n6927)
);
XNOR2X1TS U6994 ( .A(n8217), .B(n7054), .Y(n6932) );
OAI22X1TS U6995 ( .A0(n7029), .A1(n6900), .B0(n732), .B1(n6932), .Y(n6926)
);
CMPR32X2TS U6996 ( .A(n6903), .B(n6902), .C(n6901), .CO(n6907), .S(n6878) );
CMPR32X2TS U6997 ( .A(n6906), .B(n6905), .C(n6904), .CO(n6993), .S(n6875) );
OR2X4TS U6998 ( .A(n7248), .B(n7247), .Y(n7510) );
CMPR32X2TS U6999 ( .A(n6909), .B(n6908), .C(n6907), .CO(n6992), .S(n6910) );
CMPR32X2TS U7000 ( .A(n6912), .B(n6911), .C(n6910), .CO(n6991), .S(n6994) );
XNOR2X1TS U7001 ( .A(n6945), .B(n7034), .Y(n6946) );
OAI22X1TS U7002 ( .A0(n7143), .A1(n6913), .B0(n7141), .B1(n6946), .Y(n6943)
);
CMPR32X2TS U7003 ( .A(n6916), .B(n6915), .C(n6914), .CO(n6942), .S(n6922) );
OAI22X1TS U7004 ( .A0(n6948), .A1(n6917), .B0(n6947), .B1(n6984), .Y(n6980)
);
INVX2TS U7005 ( .A(n6980), .Y(n6958) );
XNOR2X1TS U7006 ( .A(n6401), .B(n6973), .Y(n6949) );
OAI22X1TS U7007 ( .A0(n7167), .A1(n6918), .B0(n7166), .B1(n6949), .Y(n6957)
);
XNOR2X1TS U7008 ( .A(n7168), .B(n723), .Y(n6950) );
OAI22X1TS U7009 ( .A0(n6988), .A1(n6919), .B0(n6950), .B1(n721), .Y(n6956)
);
CMPR32X2TS U7010 ( .A(n6922), .B(n6921), .C(n6920), .CO(n6939), .S(n6912) );
CMPR32X2TS U7011 ( .A(n6925), .B(n6924), .C(n6923), .CO(n6937), .S(n6920) );
CMPR32X2TS U7012 ( .A(n6928), .B(n6927), .C(n6926), .CO(n6936), .S(n6908) );
OAI22X1TS U7013 ( .A0(n6930), .A1(n6208), .B0(n6929), .B1(n6954), .Y(n6961)
);
XNOR2X1TS U7014 ( .A(n795), .B(n7133), .Y(n6944) );
OAI22X1TS U7015 ( .A0(n7029), .A1(n6932), .B0(n732), .B1(n6944), .Y(n6960)
);
XNOR2X1TS U7016 ( .A(n7055), .B(n6933), .Y(n6952) );
OAI22X1TS U7017 ( .A0(n6953), .A1(n6934), .B0(n740), .B1(n6952), .Y(n6959)
);
CMPR32X2TS U7018 ( .A(n6937), .B(n6936), .C(n6935), .CO(n6964), .S(n6938) );
CMPR32X2TS U7019 ( .A(n6940), .B(n6939), .C(n6938), .CO(n6963), .S(n6990) );
CMPR32X2TS U7020 ( .A(n6943), .B(n6942), .C(n6941), .CO(n6970), .S(n6940) );
XNOR2X1TS U7021 ( .A(n7156), .B(n8217), .Y(n6972) );
OAI22X1TS U7022 ( .A0(n7029), .A1(n6944), .B0(n6972), .B1(n637), .Y(n6977)
);
XNOR2X1TS U7023 ( .A(n6945), .B(n7054), .Y(n6971) );
OAI22X1TS U7024 ( .A0(n7143), .A1(n6946), .B0(n7141), .B1(n6971), .Y(n6976)
);
OAI22X1TS U7025 ( .A0(n6948), .A1(n6947), .B0(n6985), .B1(n6984), .Y(n6979)
);
XNOR2X1TS U7026 ( .A(n7016), .B(n7009), .Y(n6989) );
OAI22X1TS U7027 ( .A0(n7167), .A1(n6949), .B0(n785), .B1(n6989), .Y(n6978)
);
OAI22X1TS U7028 ( .A0(n6988), .A1(n6950), .B0(n6986), .B1(n6987), .Y(n6983)
);
XNOR2X1TS U7029 ( .A(n7055), .B(n6951), .Y(n6974) );
OAI22X1TS U7030 ( .A0(n6953), .A1(n6952), .B0(n738), .B1(n6974), .Y(n6982)
);
CMPR32X2TS U7031 ( .A(n6958), .B(n6957), .C(n6956), .CO(n6966), .S(n6941) );
CMPR32X2TS U7032 ( .A(n6961), .B(n6960), .C(n6959), .CO(n6965), .S(n6935) );
NOR2X4TS U7033 ( .A(n7256), .B(n7255), .Y(n7679) );
CMPR32X2TS U7034 ( .A(n6964), .B(n6963), .C(n6962), .CO(n7258), .S(n7255) );
CMPR32X2TS U7035 ( .A(n6970), .B(n6969), .C(n6968), .CO(n6997), .S(n6962) );
XNOR2X1TS U7036 ( .A(n7142), .B(n7133), .Y(n7008) );
OAI22X1TS U7037 ( .A0(n7143), .A1(n6971), .B0(n7141), .B1(n7008), .Y(n7007)
);
XNOR2X1TS U7038 ( .A(n7168), .B(n796), .Y(n7014) );
OAI22X1TS U7039 ( .A0(n7029), .A1(n6972), .B0(n7014), .B1(n732), .Y(n7006)
);
XNOR2X1TS U7040 ( .A(n7055), .B(n6973), .Y(n7010) );
OAI22X1TS U7041 ( .A0(n7185), .A1(n6974), .B0(n740), .B1(n7010), .Y(n7005)
);
CMPR32X2TS U7042 ( .A(n6977), .B(n6976), .C(n6975), .CO(n7003), .S(n6969) );
CMPR32X2TS U7043 ( .A(n6980), .B(n6979), .C(n6978), .CO(n7001), .S(n6975) );
CMPR32X2TS U7044 ( .A(n6983), .B(n6982), .C(n6981), .CO(n7000), .S(n6967) );
OAI22X1TS U7045 ( .A0(n875), .A1(n6985), .B0(n7015), .B1(n6984), .Y(n7038)
);
INVX2TS U7046 ( .A(n7038), .Y(n7020) );
OAI22X1TS U7047 ( .A0(n6988), .A1(n723), .B0(n6986), .B1(n7011), .Y(n7019)
);
XNOR2X1TS U7048 ( .A(n698), .B(n7034), .Y(n7017) );
OAI22X1TS U7049 ( .A0(n7167), .A1(n6989), .B0(n7166), .B1(n7017), .Y(n7018)
);
NOR2X4TS U7050 ( .A(n7258), .B(n7257), .Y(n7683) );
CMPR32X2TS U7051 ( .A(n6992), .B(n6991), .C(n6990), .CO(n7256), .S(n7254) );
NOR2X4TS U7052 ( .A(n7254), .B(n7253), .Y(n7642) );
INVX2TS U7053 ( .A(n7642), .Y(n7812) );
CMPR32X2TS U7054 ( .A(n6998), .B(n6997), .C(n6996), .CO(n7263), .S(n7257) );
CMPR32X2TS U7055 ( .A(n7001), .B(n7000), .C(n6999), .CO(n7023), .S(n7002) );
CMPR32X2TS U7056 ( .A(n7004), .B(n7003), .C(n7002), .CO(n7022), .S(n6996) );
CMPR32X2TS U7057 ( .A(n7007), .B(n7006), .C(n7005), .CO(n7041), .S(n7004) );
XNOR2X1TS U7058 ( .A(n7156), .B(n7142), .Y(n7033) );
OAI22X1TS U7059 ( .A0(n7143), .A1(n7008), .B0(n7033), .B1(n6019), .Y(n7032)
);
XNOR2X1TS U7060 ( .A(n7055), .B(n7009), .Y(n7035) );
OAI22X1TS U7061 ( .A0(n7185), .A1(n7010), .B0(n740), .B1(n7035), .Y(n7031)
);
OAI22X1TS U7062 ( .A0(n7029), .A1(n7014), .B0(n731), .B1(n795), .Y(n7026) );
OAI22X1TS U7063 ( .A0(n875), .A1(n7015), .B0(n7027), .B1(n7184), .Y(n7037)
);
XNOR2X1TS U7064 ( .A(n6401), .B(n7054), .Y(n7028) );
OAI22X1TS U7065 ( .A0(n7167), .A1(n7017), .B0(n7166), .B1(n7028), .Y(n7036)
);
CMPR32X2TS U7066 ( .A(n7020), .B(n7019), .C(n7018), .CO(n7024), .S(n6999) );
NOR2X4TS U7067 ( .A(n7263), .B(n7262), .Y(n7668) );
CMPR32X2TS U7068 ( .A(n7026), .B(n7025), .C(n7024), .CO(n7044), .S(n7039) );
INVX2TS U7069 ( .A(n7138), .Y(n7050) );
XNOR2X1TS U7070 ( .A(n701), .B(n7133), .Y(n7052) );
OAI22X1TS U7071 ( .A0(n7167), .A1(n7028), .B0(n785), .B1(n7052), .Y(n7049)
);
OAI22X1TS U7072 ( .A0(n7029), .A1(n795), .B0(n732), .B1(n911), .Y(n7048) );
CMPR32X2TS U7073 ( .A(n7032), .B(n7031), .C(n7030), .CO(n7059), .S(n7040) );
XNOR2X1TS U7074 ( .A(n7168), .B(n7142), .Y(n7053) );
OAI22X1TS U7075 ( .A0(n7143), .A1(n7033), .B0(n7053), .B1(n6019), .Y(n7047)
);
XNOR2X1TS U7076 ( .A(n7055), .B(n7034), .Y(n7056) );
OAI22X1TS U7077 ( .A0(n7185), .A1(n7035), .B0(n739), .B1(n7056), .Y(n7046)
);
CMPR32X2TS U7078 ( .A(n7038), .B(n7037), .C(n7036), .CO(n7045), .S(n7025) );
CMPR32X2TS U7079 ( .A(n7041), .B(n7040), .C(n7039), .CO(n7042), .S(n7021) );
NOR2X2TS U7080 ( .A(n7265), .B(n7264), .Y(n7671) );
NOR2X2TS U7081 ( .A(n7668), .B(n7671), .Y(n7689) );
CMPR32X2TS U7082 ( .A(n7044), .B(n7043), .C(n7042), .CO(n7267), .S(n7264) );
CMPR32X2TS U7083 ( .A(n7047), .B(n7046), .C(n7045), .CO(n7129), .S(n7058) );
CMPR32X2TS U7084 ( .A(n7050), .B(n7049), .C(n7048), .CO(n7146), .S(n7060) );
OAI22X1TS U7085 ( .A0(n6948), .A1(n7051), .B0(n7139), .B1(n7184), .Y(n7137)
);
XNOR2X1TS U7086 ( .A(n7156), .B(n7016), .Y(n7140) );
OAI22X1TS U7087 ( .A0(n7167), .A1(n7052), .B0(n7140), .B1(n7173), .Y(n7136)
);
OAI22X1TS U7088 ( .A0(n7143), .A1(n7053), .B0(n7141), .B1(n7142), .Y(n7132)
);
XNOR2X1TS U7089 ( .A(n7055), .B(n7054), .Y(n7135) );
OAI22X1TS U7090 ( .A0(n7185), .A1(n7056), .B0(n739), .B1(n7135), .Y(n7131)
);
CMPR32X2TS U7091 ( .A(n7060), .B(n7059), .C(n7058), .CO(n7127), .S(n7043) );
CMPR32X2TS U7092 ( .A(n7066), .B(n7065), .C(n7064), .CO(n7096), .S(n7086) );
CMPR32X2TS U7093 ( .A(n7069), .B(n7068), .C(n7067), .CO(n7095), .S(n7085) );
CMPR32X2TS U7094 ( .A(n7072), .B(n7071), .C(n7070), .CO(n7107), .S(n7094) );
CMPR32X2TS U7095 ( .A(n7075), .B(n7074), .C(n7073), .CO(n7099), .S(n7063) );
CMPR32X2TS U7096 ( .A(n7078), .B(n7077), .C(n7076), .CO(n6757), .S(n7102) );
CMPR32X2TS U7097 ( .A(n7081), .B(n7080), .C(n7079), .CO(n7101), .S(n7075) );
CMPR32X2TS U7098 ( .A(n7084), .B(n7083), .C(n7082), .CO(n7108), .S(n7100) );
CMPR32X2TS U7099 ( .A(n7087), .B(n7086), .C(n7085), .CO(n7097), .S(n7090) );
CMPR32X2TS U7100 ( .A(n7096), .B(n7095), .C(n7094), .CO(n7111), .S(n7092) );
CMPR32X2TS U7101 ( .A(n7102), .B(n7101), .C(n7100), .CO(n7120), .S(n7098) );
CMPR32X2TS U7102 ( .A(n7105), .B(n7104), .C(n7103), .CO(n7117), .S(n7119) );
CMPR32X2TS U7103 ( .A(n7108), .B(n7107), .C(n7106), .CO(n7115), .S(n7118) );
NOR2X6TS U7104 ( .A(n7232), .B(n7231), .Y(n7549) );
INVX4TS U7105 ( .A(n7732), .Y(n7276) );
CMPR32X2TS U7106 ( .A(n7129), .B(n7128), .C(n7127), .CO(n7313), .S(n7266) );
XNOR2X1TS U7107 ( .A(n630), .B(n7133), .Y(n7157) );
OAI22X1TS U7108 ( .A0(n7185), .A1(n7135), .B0(n740), .B1(n7157), .Y(n7155)
);
CMPR32X2TS U7109 ( .A(n7138), .B(n7137), .C(n7136), .CO(n7154), .S(n7145) );
OAI22X1TS U7110 ( .A0(n875), .A1(n7139), .B0(n7160), .B1(n7184), .Y(n7164)
);
INVX2TS U7111 ( .A(n7164), .Y(n7152) );
XNOR2X1TS U7112 ( .A(n7168), .B(n8214), .Y(n7161) );
OAI22X1TS U7113 ( .A0(n7167), .A1(n7140), .B0(n7161), .B1(n7173), .Y(n7151)
);
OAI22X1TS U7114 ( .A0(n7143), .A1(n7142), .B0(n7141), .B1(n7158), .Y(n7150)
);
CMPR32X2TS U7115 ( .A(n7146), .B(n7145), .C(n7144), .CO(n7147), .S(n7128) );
NOR2X2TS U7116 ( .A(n7313), .B(n7312), .Y(n7799) );
CMPR32X2TS U7117 ( .A(n7149), .B(n7148), .C(n7147), .CO(n7315), .S(n7312) );
CMPR32X2TS U7118 ( .A(n7152), .B(n7151), .C(n7150), .CO(n7191), .S(n7153) );
CMPR32X2TS U7119 ( .A(n7155), .B(n7154), .C(n7153), .CO(n7190), .S(n7148) );
XNOR2X1TS U7120 ( .A(n7156), .B(n681), .Y(n7169) );
OAI22X1TS U7121 ( .A0(n7185), .A1(n7157), .B0(n7169), .B1(n7332), .Y(n7172)
);
OAI22X1TS U7122 ( .A0(n6948), .A1(n7160), .B0(n7165), .B1(n7184), .Y(n7163)
);
OAI22X1TS U7123 ( .A0(n7167), .A1(n7161), .B0(n785), .B1(n8214), .Y(n7162)
);
NOR2X2TS U7124 ( .A(n7315), .B(n7314), .Y(n7704) );
CMPR32X2TS U7125 ( .A(n7164), .B(n7163), .C(n7162), .CO(n7194), .S(n7170) );
OAI22X1TS U7126 ( .A0(n6948), .A1(n7165), .B0(n7178), .B1(n7184), .Y(n7188)
);
INVX2TS U7127 ( .A(n7188), .Y(n7177) );
OAI22X1TS U7128 ( .A0(n7167), .A1(n7016), .B0(n7166), .B1(n907), .Y(n7176)
);
XNOR2X1TS U7129 ( .A(n7168), .B(n680), .Y(n7179) );
OAI22X1TS U7130 ( .A0(n7185), .A1(n7169), .B0(n7179), .B1(n7332), .Y(n7175)
);
CMPR32X2TS U7131 ( .A(n7172), .B(n7171), .C(n7170), .CO(n7192), .S(n7189) );
CMPR32X2TS U7132 ( .A(n7177), .B(n7176), .C(n7175), .CO(n7181), .S(n7193) );
OAI22X1TS U7133 ( .A0(n7183), .A1(n7184), .B0(n875), .B1(n7178), .Y(n7187)
);
OAI22X1TS U7134 ( .A0(n7185), .A1(n7179), .B0(n739), .B1(n680), .Y(n7186) );
NOR2X2TS U7135 ( .A(n7319), .B(n7318), .Y(n7760) );
CMPR32X2TS U7136 ( .A(n7182), .B(n7181), .C(n7180), .CO(n7321), .S(n7318) );
OAI22X1TS U7137 ( .A0(n7331), .A1(n7184), .B0(n7183), .B1(n875), .Y(n7750)
);
INVX2TS U7138 ( .A(n7750), .Y(n7330) );
OAI22X1TS U7139 ( .A0(n7185), .A1(n7184), .B0(n739), .B1(n875), .Y(n7329) );
CMPR32X2TS U7140 ( .A(n7188), .B(n7187), .C(n7186), .CO(n7328), .S(n7180) );
NOR2X2TS U7141 ( .A(n7321), .B(n7320), .Y(n7764) );
NOR2X1TS U7142 ( .A(n7760), .B(n7764), .Y(n7324) );
CMPR32X2TS U7143 ( .A(n7194), .B(n7193), .C(n7192), .CO(n7319), .S(n7316) );
NOR2X2TS U7144 ( .A(n7317), .B(n7316), .Y(n7516) );
INVX2TS U7145 ( .A(n7516), .Y(n7662) );
NAND2X4TS U7146 ( .A(n7198), .B(n7197), .Y(n7559) );
AOI21X4TS U7147 ( .A0(n7200), .A1(n891), .B0(n7199), .Y(n7451) );
NAND2X2TS U7148 ( .A(n7203), .B(n7202), .Y(n7455) );
INVX2TS U7149 ( .A(n7455), .Y(n7427) );
NAND2X2TS U7150 ( .A(n7205), .B(n7204), .Y(n7592) );
AND2X8TS U7151 ( .A(n7211), .B(n7210), .Y(n7228) );
NAND2X4TS U7152 ( .A(n7215), .B(n7214), .Y(n7378) );
AOI21X4TS U7153 ( .A0(n7217), .A1(n662), .B0(n7216), .Y(n7566) );
NAND2X2TS U7154 ( .A(n7221), .B(n7220), .Y(n7777) );
OAI21X4TS U7155 ( .A0(n7566), .A1(n7225), .B0(n7224), .Y(n7426) );
NAND2X2TS U7156 ( .A(n7232), .B(n7231), .Y(n7550) );
OAI21X4TS U7157 ( .A0(n7549), .A1(n7544), .B0(n7550), .Y(n7395) );
AOI21X4TS U7158 ( .A0(n7395), .A1(n7238), .B0(n7237), .Y(n7713) );
INVX2TS U7159 ( .A(n7727), .Y(n7244) );
NAND2X2TS U7160 ( .A(n7242), .B(n7241), .Y(n7719) );
INVX2TS U7161 ( .A(n7719), .Y(n7243) );
AOI21X4TS U7162 ( .A0(n7720), .A1(n7244), .B0(n7243), .Y(n7490) );
INVX2TS U7163 ( .A(n7504), .Y(n7250) );
INVX2TS U7164 ( .A(n7509), .Y(n7249) );
OAI21X4TS U7165 ( .A0(n7490), .A1(n7252), .B0(n7251), .Y(n7472) );
NAND2X2TS U7166 ( .A(n7254), .B(n7253), .Y(n7811) );
INVX2TS U7167 ( .A(n7811), .Y(n7260) );
NAND2X2TS U7168 ( .A(n7256), .B(n7255), .Y(n7678) );
AOI21X4TS U7169 ( .A0(n7261), .A1(n7260), .B0(n7259), .Y(n7473) );
NAND2X2TS U7170 ( .A(n7263), .B(n7262), .Y(n7667) );
NAND2X1TS U7171 ( .A(n7267), .B(n7266), .Y(n7697) );
INVX2TS U7172 ( .A(n7697), .Y(n7268) );
OAI21X2TS U7173 ( .A0(n7473), .A1(n7270), .B0(n7269), .Y(n7271) );
AOI21X4TS U7174 ( .A0(n7472), .A1(n7272), .B0(n7271), .Y(n7273) );
OAI21X4TS U7175 ( .A0(n7713), .A1(n7274), .B0(n7273), .Y(n7740) );
NAND2X4TS U7176 ( .A(n7283), .B(n7282), .Y(n7390) );
NAND2X4TS U7177 ( .A(n7285), .B(n7284), .Y(n7346) );
OAI21X4TS U7178 ( .A0(n7390), .A1(n7345), .B0(n7346), .Y(n7286) );
AOI21X4TS U7179 ( .A0(n651), .A1(n7287), .B0(n7286), .Y(n7443) );
NAND2X2TS U7180 ( .A(n7291), .B(n7290), .Y(n7636) );
OAI21X4TS U7181 ( .A0(n7635), .A1(n7631), .B0(n7636), .Y(n7461) );
NAND2X2TS U7182 ( .A(n7293), .B(n7292), .Y(n7465) );
NOR2X8TS U7183 ( .A(n7298), .B(n7297), .Y(n7579) );
NAND2X4TS U7184 ( .A(n7300), .B(n7299), .Y(n7620) );
NAND2X2TS U7185 ( .A(n7302), .B(n7301), .Y(n7625) );
OA21X4TS U7186 ( .A0(n7303), .A1(n7620), .B0(n7625), .Y(n7304) );
OAI21X4TS U7187 ( .A0(n7579), .A1(n7305), .B0(n7304), .Y(n7306) );
AOI21X4TS U7188 ( .A0(n7307), .A1(n7461), .B0(n7306), .Y(n7308) );
OAI21X4TS U7189 ( .A0(n7443), .A1(n7309), .B0(n7308), .Y(n7373) );
OAI21X1TS U7190 ( .A0(n7704), .A1(n7800), .B0(n7705), .Y(n7515) );
NAND2X1TS U7191 ( .A(n7321), .B(n7320), .Y(n7765) );
OAI21X2TS U7192 ( .A0(n7795), .A1(n7731), .B0(n7737), .Y(n7326) );
NAND2X1TS U7193 ( .A(n630), .B(n7331), .Y(n7751) );
INVX2TS U7194 ( .A(n7736), .Y(n7336) );
NAND2X1TS U7195 ( .A(n7335), .B(n7334), .Y(n7735) );
XOR2X4TS U7196 ( .A(n7337), .B(n897), .Y(n7339) );
INVX2TS U7197 ( .A(n7387), .Y(n7340) );
INVX2TS U7198 ( .A(n7341), .Y(n7342) );
INVX2TS U7199 ( .A(n7345), .Y(n7347) );
INVX2TS U7200 ( .A(n8074), .Y(n7353) );
INVX2TS U7201 ( .A(n8078), .Y(n7352) );
XOR2X4TS U7202 ( .A(n7357), .B(n883), .Y(n7359) );
INVX2TS U7203 ( .A(n7360), .Y(n7411) );
NAND2X2TS U7204 ( .A(n7819), .B(n7411), .Y(n7363) );
INVX2TS U7205 ( .A(n7410), .Y(n7361) );
INVX2TS U7206 ( .A(n7366), .Y(n7368) );
INVX2TS U7207 ( .A(n632), .Y(n7375) );
XOR2X4TS U7208 ( .A(n7379), .B(n899), .Y(n7381) );
OAI21X4TS U7209 ( .A0(n7381), .A1(n8753), .B0(n7380), .Y(Sgf_operation_n32)
);
XOR2X4TS U7210 ( .A(n7384), .B(n901), .Y(n7386) );
OAI21X4TS U7211 ( .A0(n7386), .A1(n832), .B0(n7385), .Y(Sgf_operation_n33)
);
INVX2TS U7212 ( .A(n7388), .Y(n7389) );
INVX2TS U7213 ( .A(n7394), .Y(n7397) );
INVX2TS U7214 ( .A(n7530), .Y(n7401) );
INVX2TS U7215 ( .A(n7395), .Y(n7396) );
AOI21X4TS U7216 ( .A0(n632), .A1(n7399), .B0(n7398), .Y(n7533) );
INVX2TS U7217 ( .A(n7533), .Y(n7400) );
INVX2TS U7218 ( .A(n7532), .Y(n7402) );
XOR2X4TS U7219 ( .A(n7412), .B(n669), .Y(n7414) );
OAI21X4TS U7220 ( .A0(n7414), .A1(n728), .B0(n7413), .Y(Sgf_operation_n47)
);
INVX2TS U7221 ( .A(n7543), .Y(n7418) );
INVX2TS U7222 ( .A(n7743), .Y(n7415) );
AOI21X4TS U7223 ( .A0(n632), .A1(n7416), .B0(n7415), .Y(n7546) );
INVX2TS U7224 ( .A(n7546), .Y(n7417) );
INVX2TS U7225 ( .A(n7545), .Y(n7419) );
XNOR2X4TS U7226 ( .A(n7421), .B(n7420), .Y(n7423) );
OAI21X4TS U7227 ( .A0(n7423), .A1(n726), .B0(n7422), .Y(Sgf_operation_n24)
);
INVX2TS U7228 ( .A(n7450), .Y(n7425) );
INVX2TS U7229 ( .A(n7591), .Y(n7435) );
BUFX3TS U7230 ( .A(n7426), .Y(n7449) );
INVX2TS U7231 ( .A(n7451), .Y(n7428) );
OAI21X2TS U7232 ( .A0(n7431), .A1(n7430), .B0(n7429), .Y(n7432) );
INVX2TS U7233 ( .A(n7593), .Y(n7436) );
INVX2TS U7234 ( .A(n7632), .Y(n7444) );
NOR2X2TS U7235 ( .A(n7783), .B(n7452), .Y(n7454) );
OAI21X2TS U7236 ( .A0(n7784), .A1(n7452), .B0(n7451), .Y(n7453) );
NAND2X1TS U7237 ( .A(n7456), .B(n7455), .Y(n7457) );
XNOR2X4TS U7238 ( .A(n7458), .B(n7457), .Y(n7460) );
OAI21X4TS U7239 ( .A0(n7460), .A1(n7792), .B0(n7459), .Y(Sgf_operation_n27)
);
NOR2X2TS U7240 ( .A(n7603), .B(n7462), .Y(n7464) );
OAI21X2TS U7241 ( .A0(n7604), .A1(n7462), .B0(n7607), .Y(n7463) );
AOI21X4TS U7242 ( .A0(n7798), .A1(n7464), .B0(n7463), .Y(n7467) );
XOR2X4TS U7243 ( .A(n7467), .B(n913), .Y(n7469) );
OAI21X4TS U7244 ( .A0(n7469), .A1(n8753), .B0(n7468), .Y(Sgf_operation_n36)
);
NOR2X4TS U7245 ( .A(n7808), .B(n7474), .Y(n7476) );
INVX2TS U7246 ( .A(n7690), .Y(n7483) );
INVX2TS U7247 ( .A(n7471), .Y(n7478) );
OAI2BB1X4TS U7248 ( .A0N(n7479), .A1N(n7478), .B0(n7477), .Y(n7480) );
INVX2TS U7249 ( .A(n7694), .Y(n7482) );
INVX2TS U7250 ( .A(n7668), .Y(n7484) );
NAND2X1TS U7251 ( .A(n7484), .B(n7667), .Y(n7485) );
INVX2TS U7252 ( .A(n7489), .Y(n7492) );
NAND2X2TS U7253 ( .A(n7641), .B(n7492), .Y(n7494) );
INVX2TS U7254 ( .A(n7503), .Y(n7498) );
INVX2TS U7255 ( .A(n7490), .Y(n7491) );
INVX2TS U7256 ( .A(n7506), .Y(n7497) );
AOI21X4TS U7257 ( .A0(n7748), .A1(n7498), .B0(n7497), .Y(n7500) );
OAI21X4TS U7258 ( .A0(n7502), .A1(n7815), .B0(n7501), .Y(Sgf_operation_n18)
);
NOR2X2TS U7259 ( .A(n7503), .B(n7505), .Y(n7508) );
AOI21X4TS U7260 ( .A0(n870), .A1(n7508), .B0(n7507), .Y(n7511) );
XOR2X4TS U7261 ( .A(n7511), .B(n890), .Y(n7513) );
INVX2TS U7262 ( .A(n7514), .Y(n7658) );
NOR2X2TS U7263 ( .A(n7658), .B(n7516), .Y(n7518) );
NAND2X2TS U7264 ( .A(n7732), .B(n7518), .Y(n7520) );
INVX2TS U7265 ( .A(n7758), .Y(n7524) );
INVX2TS U7266 ( .A(n7515), .Y(n7657) );
OAI21X1TS U7267 ( .A0(n7657), .A1(n7516), .B0(n7661), .Y(n7517) );
INVX2TS U7268 ( .A(n7761), .Y(n7523) );
INVX2TS U7269 ( .A(n7760), .Y(n7525) );
NAND2X1TS U7270 ( .A(n7525), .B(n7759), .Y(n7526) );
INVX2TS U7271 ( .A(n7536), .Y(n7538) );
INVX2TS U7272 ( .A(n7549), .Y(n7551) );
XNOR2X4TS U7273 ( .A(n7553), .B(n7552), .Y(n7555) );
OAI21X4TS U7274 ( .A0(n7555), .A1(n727), .B0(n7554), .Y(Sgf_operation_n23)
);
NOR2X2TS U7275 ( .A(n7783), .B(n7556), .Y(n7558) );
XNOR2X4TS U7276 ( .A(n7561), .B(n7560), .Y(n7563) );
INVX2TS U7277 ( .A(n7771), .Y(n7570) );
INVX2TS U7278 ( .A(n7566), .Y(n7567) );
INVX2TS U7279 ( .A(n7774), .Y(n7569) );
INVX2TS U7280 ( .A(n7576), .Y(n7577) );
INVX2TS U7281 ( .A(n7619), .Y(n7586) );
INVX2TS U7282 ( .A(n7461), .Y(n7581) );
INVX2TS U7283 ( .A(n7622), .Y(n7585) );
XOR2X4TS U7284 ( .A(n7588), .B(n904), .Y(n7590) );
OAI21X4TS U7285 ( .A0(n7590), .A1(n8753), .B0(n7589), .Y(Sgf_operation_n35)
);
NOR2X2TS U7286 ( .A(n7591), .B(n7593), .Y(n7596) );
INVX2TS U7287 ( .A(n7597), .Y(n7599) );
XOR2X4TS U7288 ( .A(n7600), .B(n898), .Y(n7602) );
AOI21X4TS U7289 ( .A0(n7798), .A1(n7606), .B0(n7605), .Y(n7608) );
XOR2X4TS U7290 ( .A(n7608), .B(n905), .Y(n7610) );
INVX2TS U7291 ( .A(n7611), .Y(n8135) );
INVX2TS U7292 ( .A(n8136), .Y(n7612) );
NOR2X2TS U7293 ( .A(n7619), .B(n7621), .Y(n7624) );
XOR2X4TS U7294 ( .A(n7627), .B(n916), .Y(n7629) );
OAI21X4TS U7295 ( .A0(n7629), .A1(n728), .B0(n7628), .Y(Sgf_operation_n34)
);
INVX2TS U7296 ( .A(n7635), .Y(n7637) );
NOR2X4TS U7297 ( .A(n7733), .B(n7647), .Y(n7646) );
INVX2TS U7298 ( .A(n7677), .Y(n7652) );
OAI21X1TS U7299 ( .A0(n7807), .A1(n7642), .B0(n7811), .Y(n7643) );
AOI21X2TS U7300 ( .A0(n7645), .A1(n7644), .B0(n7643), .Y(n7650) );
INVX2TS U7301 ( .A(n7679), .Y(n7653) );
NOR2X2TS U7302 ( .A(n7794), .B(n7658), .Y(n7660) );
AOI21X4TS U7303 ( .A0(n870), .A1(n7660), .B0(n7659), .Y(n7664) );
NAND2X1TS U7304 ( .A(n7662), .B(n7661), .Y(n7663) );
NOR2X2TS U7305 ( .A(n7690), .B(n7668), .Y(n7670) );
AOI21X4TS U7306 ( .A0(n7798), .A1(n7670), .B0(n7669), .Y(n7674) );
INVX2TS U7307 ( .A(n7671), .Y(n7673) );
XOR2X4TS U7308 ( .A(n7674), .B(n896), .Y(n7676) );
OAI21X4TS U7309 ( .A0(n7676), .A1(n8748), .B0(n7675), .Y(Sgf_operation_n12)
);
INVX2TS U7310 ( .A(n7683), .Y(n7685) );
XOR2X4TS U7311 ( .A(n7686), .B(n895), .Y(n7688) );
INVX2TS U7312 ( .A(n7689), .Y(n7693) );
INVX2TS U7313 ( .A(n7691), .Y(n7692) );
INVX2TS U7314 ( .A(n7704), .Y(n7706) );
NOR2X2TS U7315 ( .A(n7805), .B(n7716), .Y(n7718) );
AOI21X4TS U7316 ( .A0(n7748), .A1(n7718), .B0(n7717), .Y(n7721) );
XOR2X4TS U7317 ( .A(n7721), .B(n912), .Y(n7723) );
INVX2TS U7318 ( .A(n7805), .Y(n7725) );
XOR2X4TS U7319 ( .A(n7728), .B(n882), .Y(n7730) );
OAI21X4TS U7320 ( .A0(n7730), .A1(n727), .B0(n7729), .Y(Sgf_operation_n20)
);
NAND2X2TS U7321 ( .A(n7732), .B(n7739), .Y(n7742) );
OAI21X1TS U7322 ( .A0(n7737), .A1(n7736), .B0(n7735), .Y(n7738) );
AO21X4TS U7323 ( .A0(n632), .A1(n7745), .B0(n7744), .Y(n7746) );
CMPR32X2TS U7324 ( .A(n7751), .B(n7750), .C(n7749), .CO(n7753), .S(n7334) );
NAND2X1TS U7325 ( .A(n7753), .B(n630), .Y(n7754) );
XNOR2X4TS U7326 ( .A(n7755), .B(n7754), .Y(n7757) );
OAI21X4TS U7327 ( .A0(n7757), .A1(n775), .B0(n7756), .Y(Sgf_operation_n4) );
NOR2X2TS U7328 ( .A(n7758), .B(n7760), .Y(n7763) );
INVX2TS U7329 ( .A(n7764), .Y(n7766) );
NAND2X1TS U7330 ( .A(n7766), .B(n7765), .Y(n7767) );
XNOR2X4TS U7331 ( .A(n7768), .B(n7767), .Y(n7770) );
OAI21X4TS U7332 ( .A0(n7770), .A1(n8638), .B0(n7769), .Y(Sgf_operation_n6)
);
NOR2X2TS U7333 ( .A(n7771), .B(n7773), .Y(n7776) );
OAI21X2TS U7334 ( .A0(n7774), .A1(n7773), .B0(n7772), .Y(n7775) );
NAND2X1TS U7335 ( .A(n7778), .B(n7777), .Y(n7779) );
XNOR2X4TS U7336 ( .A(n7780), .B(n7779), .Y(n7782) );
INVX2TS U7337 ( .A(n7783), .Y(n7786) );
INVX2TS U7338 ( .A(n7784), .Y(n7785) );
NAND2X1TS U7339 ( .A(n7788), .B(n7787), .Y(n7789) );
INVX2TS U7340 ( .A(n7794), .Y(n7797) );
INVX2TS U7341 ( .A(n7795), .Y(n7796) );
AOI21X4TS U7342 ( .A0(n7798), .A1(n7797), .B0(n7796), .Y(n7802) );
INVX2TS U7343 ( .A(n7799), .Y(n7801) );
OAI21X4TS U7344 ( .A0(n7804), .A1(n774), .B0(n7803), .Y(Sgf_operation_n10)
);
NOR2X2TS U7345 ( .A(n7805), .B(n7808), .Y(n7806) );
XOR2X4TS U7346 ( .A(n7813), .B(n886), .Y(n7816) );
OAI21X4TS U7347 ( .A0(n7816), .A1(n832), .B0(n7814), .Y(Sgf_operation_n16)
);
INVX2TS U7348 ( .A(n7830), .Y(n7832) );
NOR3BX1TS U7349 ( .AN(Op_MY[62]), .B(FSM_selector_B[0]), .C(
FSM_selector_B[1]), .Y(n7837) );
XOR2X1TS U7350 ( .A(n780), .B(n7837), .Y(DP_OP_31J26_122_605_n18) );
OAI2BB1X1TS U7351 ( .A0N(Op_MY[61]), .A1N(n8941), .B0(n661), .Y(n7838) );
OAI2BB1X1TS U7352 ( .A0N(Op_MY[60]), .A1N(n8941), .B0(n661), .Y(n7839) );
XOR2X1TS U7353 ( .A(n780), .B(n7839), .Y(DP_OP_31J26_122_605_n20) );
OAI2BB1X1TS U7354 ( .A0N(Op_MY[59]), .A1N(n8941), .B0(n661), .Y(n7840) );
XOR2X1TS U7355 ( .A(n8767), .B(n7840), .Y(DP_OP_31J26_122_605_n21) );
OAI2BB1X1TS U7356 ( .A0N(Op_MY[58]), .A1N(n8941), .B0(n661), .Y(n7841) );
XOR2X1TS U7357 ( .A(n780), .B(n7841), .Y(DP_OP_31J26_122_605_n22) );
OAI2BB1X1TS U7358 ( .A0N(Op_MY[57]), .A1N(n8941), .B0(n661), .Y(n7842) );
XOR2X1TS U7359 ( .A(n8767), .B(n7842), .Y(DP_OP_31J26_122_605_n23) );
OAI2BB1X1TS U7360 ( .A0N(Op_MY[56]), .A1N(n8941), .B0(n661), .Y(n7843) );
XOR2X1TS U7361 ( .A(n780), .B(n7843), .Y(DP_OP_31J26_122_605_n24) );
OAI2BB1X1TS U7362 ( .A0N(Op_MY[55]), .A1N(n8941), .B0(n661), .Y(n7844) );
XOR2X1TS U7363 ( .A(n8767), .B(n7844), .Y(DP_OP_31J26_122_605_n25) );
OAI2BB1X1TS U7364 ( .A0N(Op_MY[54]), .A1N(n8941), .B0(n661), .Y(n7845) );
XOR2X1TS U7365 ( .A(n780), .B(n7845), .Y(DP_OP_31J26_122_605_n26) );
OAI2BB1X1TS U7366 ( .A0N(Op_MY[53]), .A1N(n8941), .B0(n661), .Y(n7846) );
XOR2X1TS U7367 ( .A(n8767), .B(n7846), .Y(DP_OP_31J26_122_605_n27) );
INVX2TS U7368 ( .A(n7977), .Y(n7955) );
INVX2TS U7369 ( .A(n7848), .Y(n7978) );
NAND2X1TS U7370 ( .A(n7955), .B(n7978), .Y(n7852) );
INVX2TS U7371 ( .A(n7849), .Y(n7958) );
INVX2TS U7372 ( .A(n7979), .Y(n7850) );
AOI21X1TS U7373 ( .A0(n7958), .A1(n7978), .B0(n7850), .Y(n7851) );
INVX2TS U7374 ( .A(n7853), .Y(n7855) );
BUFX3TS U7375 ( .A(n7861), .Y(n7867) );
INVX2TS U7376 ( .A(n8016), .Y(n7875) );
INVX2TS U7377 ( .A(n7876), .Y(n7878) );
INVX2TS U7378 ( .A(n8161), .Y(n7890) );
NAND2X1TS U7379 ( .A(n8059), .B(n7898), .Y(n7899) );
INVX2TS U7380 ( .A(n7926), .Y(n7901) );
INVX2TS U7381 ( .A(n7925), .Y(n7903) );
OAI21X1TS U7382 ( .A0(n7903), .A1(n7930), .B0(n7931), .Y(n7904) );
INVX2TS U7383 ( .A(n7908), .Y(n7910) );
INVX2TS U7384 ( .A(n7914), .Y(n8028) );
INVX2TS U7385 ( .A(n8027), .Y(n7915) );
INVX2TS U7386 ( .A(n7918), .Y(n7920) );
AOI21X1TS U7387 ( .A0(n7927), .A1(n7926), .B0(n7925), .Y(n7928) );
INVX2TS U7388 ( .A(n7930), .Y(n7932) );
INVX2TS U7389 ( .A(n7938), .Y(n7940) );
INVX2TS U7390 ( .A(n7948), .Y(n7944) );
XOR2X1TS U7391 ( .A(n7986), .B(n7945), .Y(n7946) );
OAI21X1TS U7392 ( .A0(n7986), .A1(n7948), .B0(n7947), .Y(n7953) );
INVX2TS U7393 ( .A(n7949), .Y(n7951) );
XNOR2X1TS U7394 ( .A(n7953), .B(n7952), .Y(n7954) );
NAND2X1TS U7395 ( .A(n7955), .B(n7957), .Y(n7960) );
NAND2X1TS U7396 ( .A(n7962), .B(n7961), .Y(n7963) );
INVX2TS U7397 ( .A(n7966), .Y(n7988) );
NAND2X1TS U7398 ( .A(n7983), .B(n7988), .Y(n7970) );
INVX2TS U7399 ( .A(n7987), .Y(n7968) );
AOI21X1TS U7400 ( .A0(n7967), .A1(n7988), .B0(n7968), .Y(n7969) );
OAI21X1TS U7401 ( .A0(n7986), .A1(n7970), .B0(n7969), .Y(n7975) );
INVX2TS U7402 ( .A(n7971), .Y(n7973) );
XNOR2X1TS U7403 ( .A(n7975), .B(n7974), .Y(n7976) );
XNOR2X1TS U7404 ( .A(n7981), .B(n7980), .Y(n7982) );
INVX2TS U7405 ( .A(n7983), .Y(n7985) );
INVX2TS U7406 ( .A(n7967), .Y(n7984) );
NAND2X1TS U7407 ( .A(n7988), .B(n7987), .Y(n7989) );
XNOR2X1TS U7408 ( .A(n7990), .B(n7989), .Y(n7991) );
OAI21X1TS U7409 ( .A0(n7992), .A1(n8007), .B0(n8010), .Y(n7993) );
AOI21X2TS U7410 ( .A0(n8020), .A1(n7994), .B0(n7993), .Y(n7998) );
NAND2X1TS U7411 ( .A(n7996), .B(n7995), .Y(n7997) );
CLKMX2X2TS U7412 ( .A(n7999), .B(P_Sgf[36]), .S0(n8638), .Y(
Sgf_operation_n73) );
INVX2TS U7413 ( .A(n8006), .Y(n8009) );
INVX2TS U7414 ( .A(n8007), .Y(n8008) );
AOI21X2TS U7415 ( .A0(n8020), .A1(n8009), .B0(n8008), .Y(n8013) );
NAND2X1TS U7416 ( .A(n8011), .B(n8010), .Y(n8012) );
NOR2X1TS U7417 ( .A(n8015), .B(n8016), .Y(n8019) );
OAI21X1TS U7418 ( .A0(n8017), .A1(n8016), .B0(n7876), .Y(n8018) );
NAND2X1TS U7419 ( .A(n8022), .B(n8021), .Y(n8023) );
INVX2TS U7420 ( .A(n8039), .Y(n8034) );
INVX2TS U7421 ( .A(n8032), .Y(n8033) );
INVX2TS U7422 ( .A(n8035), .Y(n8042) );
NAND2X1TS U7423 ( .A(n8042), .B(n8040), .Y(n8036) );
NAND2X1TS U7424 ( .A(n8039), .B(n8042), .Y(n8044) );
AOI21X1TS U7425 ( .A0(n8032), .A1(n8042), .B0(n8041), .Y(n8043) );
INVX2TS U7426 ( .A(n8045), .Y(n8047) );
INVX2TS U7427 ( .A(n8053), .Y(n8054) );
NAND2X1TS U7428 ( .A(n8055), .B(n8054), .Y(n8056) );
NAND2X1TS U7429 ( .A(n917), .B(n8062), .Y(n8063) );
CLKBUFX2TS U7430 ( .A(n624), .Y(n8940) );
NAND2X2TS U7431 ( .A(n8089), .B(n8066), .Y(n8094) );
INVX2TS U7432 ( .A(n8094), .Y(n8069) );
INVX2TS U7433 ( .A(n8114), .Y(n8088) );
INVX2TS U7434 ( .A(n8097), .Y(n8068) );
INVX2TS U7435 ( .A(n8096), .Y(n8070) );
AOI21X1TS U7436 ( .A0(n8078), .A1(n8077), .B0(n8076), .Y(n8079) );
INVX2TS U7437 ( .A(n8115), .Y(n8090) );
INVX2TS U7438 ( .A(n8100), .Y(n8102) );
INVX2TS U7439 ( .A(n8125), .Y(n8108) );
INVX2TS U7440 ( .A(n8129), .Y(n8131) );
NOR2X1TS U7441 ( .A(n8206), .B(n8848), .Y(n8182) );
CLKXOR2X2TS U7442 ( .A(Op_MX[63]), .B(Op_MY[63]), .Y(n8183) );
NOR4X1TS U7443 ( .A(P_Sgf[3]), .B(P_Sgf[2]), .C(P_Sgf[1]), .D(P_Sgf[0]), .Y(
n8154) );
NOR4X1TS U7444 ( .A(P_Sgf[4]), .B(P_Sgf[9]), .C(P_Sgf[5]), .D(P_Sgf[49]),
.Y(n8153) );
NOR4X1TS U7445 ( .A(P_Sgf[31]), .B(P_Sgf[38]), .C(P_Sgf[37]), .D(P_Sgf[36]),
.Y(n8152) );
OR4X2TS U7446 ( .A(P_Sgf[28]), .B(P_Sgf[34]), .C(P_Sgf[39]), .D(P_Sgf[35]),
.Y(n8150) );
OR4X2TS U7447 ( .A(P_Sgf[30]), .B(P_Sgf[32]), .C(P_Sgf[29]), .D(P_Sgf[33]),
.Y(n8149) );
NOR4X1TS U7448 ( .A(P_Sgf[6]), .B(P_Sgf[51]), .C(P_Sgf[46]), .D(P_Sgf[50]),
.Y(n8142) );
NOR4X1TS U7449 ( .A(P_Sgf[47]), .B(P_Sgf[48]), .C(P_Sgf[44]), .D(P_Sgf[43]),
.Y(n8141) );
NOR4X1TS U7450 ( .A(P_Sgf[45]), .B(P_Sgf[40]), .C(P_Sgf[42]), .D(P_Sgf[41]),
.Y(n8140) );
NOR4X1TS U7451 ( .A(P_Sgf[8]), .B(P_Sgf[10]), .C(P_Sgf[12]), .D(P_Sgf[14]),
.Y(n8139) );
NAND4XLTS U7452 ( .A(n8142), .B(n8141), .C(n8140), .D(n8139), .Y(n8148) );
NOR4X1TS U7453 ( .A(P_Sgf[7]), .B(P_Sgf[15]), .C(P_Sgf[13]), .D(P_Sgf[11]),
.Y(n8146) );
NOR4X1TS U7454 ( .A(P_Sgf[18]), .B(P_Sgf[17]), .C(P_Sgf[25]), .D(P_Sgf[19]),
.Y(n8145) );
NOR4X1TS U7455 ( .A(P_Sgf[16]), .B(P_Sgf[22]), .C(P_Sgf[21]), .D(P_Sgf[20]),
.Y(n8144) );
NOR4X1TS U7456 ( .A(P_Sgf[24]), .B(P_Sgf[27]), .C(P_Sgf[26]), .D(P_Sgf[23]),
.Y(n8143) );
NAND4XLTS U7457 ( .A(n8146), .B(n8145), .C(n8144), .D(n8143), .Y(n8147) );
NOR4X1TS U7458 ( .A(n8150), .B(n8149), .C(n8148), .D(n8147), .Y(n8151) );
MXI2X1TS U7459 ( .A(n8183), .B(round_mode[1]), .S0(round_mode[0]), .Y(n8155)
);
OAI211X1TS U7460 ( .A0(n8183), .A1(round_mode[1]), .B0(n8156), .C0(n8155),
.Y(n8177) );
AOI32X1TS U7461 ( .A0(FS_Module_state_reg[3]), .A1(n8219), .A2(n8177), .B0(
FS_Module_state_reg[1]), .B1(n8219), .Y(n8157) );
INVX2TS U7462 ( .A(n8158), .Y(n8159) );
OAI21X1TS U7463 ( .A0(n8162), .A1(n8161), .B0(n8160), .Y(n8163) );
INVX2TS U7464 ( .A(n8165), .Y(n8166) );
CLKBUFX2TS U7465 ( .A(n624), .Y(n8173) );
BUFX3TS U7466 ( .A(n8911), .Y(n8938) );
BUFX3TS U7467 ( .A(n8911), .Y(n8937) );
INVX2TS U7468 ( .A(rst), .Y(n8942) );
BUFX3TS U7469 ( .A(n831), .Y(n8902) );
BUFX3TS U7470 ( .A(n8173), .Y(n8936) );
BUFX3TS U7471 ( .A(n8911), .Y(n8935) );
BUFX3TS U7472 ( .A(n8171), .Y(n8901) );
BUFX3TS U7473 ( .A(n8173), .Y(n8910) );
CLKBUFX3TS U7474 ( .A(n8171), .Y(n8907) );
BUFX3TS U7475 ( .A(n8171), .Y(n8906) );
BUFX3TS U7476 ( .A(n831), .Y(n8899) );
BUFX3TS U7477 ( .A(n831), .Y(n8905) );
CLKBUFX3TS U7478 ( .A(n831), .Y(n8904) );
BUFX3TS U7479 ( .A(n8171), .Y(n8903) );
BUFX3TS U7480 ( .A(n8175), .Y(n8928) );
CLKBUFX2TS U7481 ( .A(n8172), .Y(n8174) );
BUFX3TS U7482 ( .A(n8940), .Y(n8919) );
BUFX3TS U7483 ( .A(n8175), .Y(n8927) );
BUFX3TS U7484 ( .A(n8174), .Y(n8920) );
BUFX3TS U7485 ( .A(n8911), .Y(n8926) );
BUFX3TS U7486 ( .A(n8173), .Y(n8921) );
BUFX3TS U7487 ( .A(n8911), .Y(n8925) );
BUFX3TS U7488 ( .A(n8173), .Y(n8922) );
BUFX3TS U7489 ( .A(n8911), .Y(n8909) );
BUFX3TS U7490 ( .A(n8173), .Y(n8923) );
BUFX3TS U7491 ( .A(n8171), .Y(n8908) );
BUFX3TS U7492 ( .A(n831), .Y(n8900) );
BUFX3TS U7493 ( .A(n8172), .Y(n8924) );
BUFX3TS U7494 ( .A(n8911), .Y(n8934) );
BUFX3TS U7495 ( .A(n8173), .Y(n8933) );
BUFX3TS U7496 ( .A(n8175), .Y(n8932) );
BUFX3TS U7497 ( .A(n8175), .Y(n8931) );
BUFX3TS U7498 ( .A(n8940), .Y(n8916) );
BUFX3TS U7499 ( .A(n8174), .Y(n8915) );
BUFX3TS U7500 ( .A(n8940), .Y(n8914) );
BUFX3TS U7501 ( .A(n8175), .Y(n8913) );
BUFX3TS U7502 ( .A(n8175), .Y(n8930) );
BUFX3TS U7503 ( .A(n8174), .Y(n8917) );
BUFX3TS U7504 ( .A(n8940), .Y(n8918) );
BUFX3TS U7505 ( .A(n8175), .Y(n8929) );
NAND4X1TS U7506 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[0]),
.C(n8206), .D(n8851), .Y(n8769) );
INVX2TS U7507 ( .A(n8830), .Y(n8828) );
NAND2X1TS U7508 ( .A(n8828), .B(n8526), .Y(n8176) );
OA22X1TS U7509 ( .A0(n8840), .A1(final_result_ieee[60]), .B0(
exp_oper_result[8]), .B1(n8841), .Y(n290) );
OA22X1TS U7510 ( .A0(n8840), .A1(final_result_ieee[53]), .B0(
exp_oper_result[1]), .B1(n8841), .Y(n297) );
OA22X1TS U7511 ( .A0(n8840), .A1(final_result_ieee[58]), .B0(
exp_oper_result[6]), .B1(n8841), .Y(n292) );
OA22X1TS U7512 ( .A0(n8840), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n8841), .Y(n293) );
OA22X1TS U7513 ( .A0(n8840), .A1(final_result_ieee[59]), .B0(
exp_oper_result[7]), .B1(n8841), .Y(n291) );
CLKBUFX3TS U7514 ( .A(n624), .Y(n8911) );
BUFX3TS U7515 ( .A(n624), .Y(n8912) );
NAND2X1TS U7516 ( .A(n8526), .B(Add_result[2]), .Y(n8181) );
NAND3X1TS U7517 ( .A(n8182), .B(n8847), .C(n8851), .Y(n8196) );
INVX2TS U7518 ( .A(n8196), .Y(ready) );
NOR2XLTS U7519 ( .A(n8183), .B(underflow_flag), .Y(n8184) );
OAI32X1TS U7520 ( .A0(n8833), .A1(n8184), .A2(overflow_flag), .B0(n8840),
.B1(n8896), .Y(n286) );
NAND2X2TS U7521 ( .A(n8187), .B(FS_Module_state_reg[1]), .Y(n8257) );
NOR2X4TS U7522 ( .A(n8257), .B(n8850), .Y(n8474) );
BUFX3TS U7523 ( .A(n8474), .Y(n8567) );
AOI22X1TS U7524 ( .A0(n8390), .A1(n772), .B0(n8381), .B1(n830), .Y(n8193) );
AOI21X1TS U7525 ( .A0(n8567), .A1(Add_result[1]), .B0(n8194), .Y(n8195) );
OAI21XLTS U7526 ( .A0(n8848), .A1(n8768), .B0(FS_Module_state_reg[3]), .Y(
n8197) );
AOI22X1TS U7527 ( .A0(n8382), .A1(n830), .B0(n8381), .B1(P_Sgf[54]), .Y(
n8198) );
AOI21X1TS U7528 ( .A0(n8567), .A1(Add_result[2]), .B0(n8199), .Y(n8200) );
INVX2TS U7529 ( .A(n957), .Y(n8819) );
OAI22X1TS U7530 ( .A0(zero_flag), .A1(n8752), .B0(P_Sgf[105]), .B1(n8769),
.Y(n8218) );
NAND2X1TS U7531 ( .A(Sgf_normalized_result[34]), .B(
Sgf_normalized_result[35]), .Y(n8341) );
NAND2X1TS U7532 ( .A(Sgf_normalized_result[36]), .B(
Sgf_normalized_result[37]), .Y(n8237) );
NAND2X1TS U7533 ( .A(Sgf_normalized_result[18]), .B(
Sgf_normalized_result[19]), .Y(n8443) );
NAND2X1TS U7534 ( .A(Sgf_normalized_result[20]), .B(
Sgf_normalized_result[21]), .Y(n8239) );
NAND2X1TS U7535 ( .A(Sgf_normalized_result[22]), .B(
Sgf_normalized_result[23]), .Y(n8420) );
NAND2X1TS U7536 ( .A(Sgf_normalized_result[24]), .B(
Sgf_normalized_result[25]), .Y(n8240) );
NAND2X1TS U7537 ( .A(Sgf_normalized_result[26]), .B(
Sgf_normalized_result[27]), .Y(n8394) );
NAND2X1TS U7538 ( .A(Sgf_normalized_result[28]), .B(
Sgf_normalized_result[29]), .Y(n8242) );
NAND2X1TS U7539 ( .A(Sgf_normalized_result[30]), .B(
Sgf_normalized_result[31]), .Y(n8367) );
NAND2X1TS U7540 ( .A(Sgf_normalized_result[32]), .B(
Sgf_normalized_result[33]), .Y(n8243) );
NAND2X1TS U7541 ( .A(n8365), .B(n8244), .Y(n8245) );
NAND2X1TS U7542 ( .A(Sgf_normalized_result[12]), .B(
Sgf_normalized_result[13]), .Y(n8246) );
NAND2X1TS U7543 ( .A(Sgf_normalized_result[14]), .B(
Sgf_normalized_result[15]), .Y(n8470) );
NAND2X1TS U7544 ( .A(Sgf_normalized_result[16]), .B(
Sgf_normalized_result[17]), .Y(n8247) );
NAND2X1TS U7545 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n8524) );
NAND2X1TS U7546 ( .A(Sgf_normalized_result[8]), .B(Sgf_normalized_result[9]),
.Y(n8249) );
BUFX3TS U7547 ( .A(n8504), .Y(n8384) );
MXI2X1TS U7548 ( .A(P_Sgf[104]), .B(Add_result[52]), .S0(FSM_selector_C),
.Y(n8256) );
AOI21X1TS U7549 ( .A0(n8257), .A1(n8256), .B0(n8565), .Y(n8258) );
AHHCINX2TS U7550 ( .A(Sgf_normalized_result[51]), .CIN(n8259), .S(n8260),
.CO(n8572) );
NAND2X1TS U7551 ( .A(n8310), .B(Add_result[52]), .Y(n8262) );
NAND2X1TS U7552 ( .A(n8390), .B(P_Sgf[103]), .Y(n8261) );
AOI21X1TS U7553 ( .A0(P_Sgf[104]), .A1(n8441), .B0(n8264), .Y(n8265) );
OAI2BB1X1TS U7554 ( .A0N(n8563), .A1N(Add_result[51]), .B0(n8265), .Y(n403)
);
AHHCONX2TS U7555 ( .A(Sgf_normalized_result[50]), .CI(n8266), .CON(n8259),
.S(n8267) );
BUFX3TS U7556 ( .A(n8504), .Y(n8333) );
AOI22X1TS U7557 ( .A0(n8447), .A1(P_Sgf[102]), .B0(P_Sgf[103]), .B1(n8513),
.Y(n8268) );
OAI2BB1X1TS U7558 ( .A0N(Sgf_normalized_result[50]), .A1N(n8333), .B0(n8268),
.Y(n8269) );
AOI21X1TS U7559 ( .A0(n8310), .A1(Add_result[51]), .B0(n8269), .Y(n8270) );
OAI2BB1X1TS U7560 ( .A0N(Add_result[50]), .A1N(n8319), .B0(n8270), .Y(n402)
);
AHHCINX2TS U7561 ( .A(Sgf_normalized_result[49]), .CIN(n8271), .S(n8272),
.CO(n8266) );
AOI22X1TS U7562 ( .A0(n8324), .A1(P_Sgf[101]), .B0(P_Sgf[102]), .B1(n8513),
.Y(n8273) );
OAI2BB1X1TS U7563 ( .A0N(Sgf_normalized_result[49]), .A1N(n8504), .B0(n8273),
.Y(n8274) );
AOI21X1TS U7564 ( .A0(n8310), .A1(Add_result[50]), .B0(n8274), .Y(n8275) );
OAI2BB1X1TS U7565 ( .A0N(Add_result[49]), .A1N(n8319), .B0(n8275), .Y(n401)
);
AHHCONX2TS U7566 ( .A(Sgf_normalized_result[48]), .CI(n8276), .CON(n8271),
.S(n8277) );
AOI22X1TS U7567 ( .A0(n8324), .A1(P_Sgf[100]), .B0(n8331), .B1(P_Sgf[101]),
.Y(n8278) );
OAI2BB1X1TS U7568 ( .A0N(Sgf_normalized_result[48]), .A1N(n8333), .B0(n8278),
.Y(n8279) );
AOI21X1TS U7569 ( .A0(n8310), .A1(Add_result[49]), .B0(n8279), .Y(n8280) );
OAI2BB1X1TS U7570 ( .A0N(Add_result[48]), .A1N(n8319), .B0(n8280), .Y(n400)
);
AHHCINX2TS U7571 ( .A(Sgf_normalized_result[47]), .CIN(n8281), .S(n8282),
.CO(n8276) );
AOI22X1TS U7572 ( .A0(n8324), .A1(P_Sgf[99]), .B0(n8331), .B1(P_Sgf[100]),
.Y(n8283) );
OAI2BB1X1TS U7573 ( .A0N(Sgf_normalized_result[47]), .A1N(n8333), .B0(n8283),
.Y(n8284) );
AOI21X1TS U7574 ( .A0(n8310), .A1(Add_result[48]), .B0(n8284), .Y(n8285) );
OAI2BB1X1TS U7575 ( .A0N(Add_result[47]), .A1N(n8319), .B0(n8285), .Y(n399)
);
AHHCONX2TS U7576 ( .A(Sgf_normalized_result[46]), .CI(n8286), .CON(n8281),
.S(n8287) );
AOI22X1TS U7577 ( .A0(n8324), .A1(P_Sgf[98]), .B0(n8331), .B1(P_Sgf[99]),
.Y(n8288) );
OAI2BB1X1TS U7578 ( .A0N(Sgf_normalized_result[46]), .A1N(n8333), .B0(n8288),
.Y(n8289) );
AOI21X1TS U7579 ( .A0(n8310), .A1(Add_result[47]), .B0(n8289), .Y(n8290) );
OAI2BB1X1TS U7580 ( .A0N(Add_result[46]), .A1N(n8319), .B0(n8290), .Y(n398)
);
AHHCINX2TS U7581 ( .A(Sgf_normalized_result[45]), .CIN(n8291), .S(n8292),
.CO(n8286) );
AOI22X1TS U7582 ( .A0(n8324), .A1(P_Sgf[97]), .B0(n8331), .B1(P_Sgf[98]),
.Y(n8293) );
OAI2BB1X1TS U7583 ( .A0N(Sgf_normalized_result[45]), .A1N(n8333), .B0(n8293),
.Y(n8294) );
AOI21X1TS U7584 ( .A0(n8310), .A1(Add_result[46]), .B0(n8294), .Y(n8295) );
OAI2BB1X1TS U7585 ( .A0N(Add_result[45]), .A1N(n8319), .B0(n8295), .Y(n397)
);
AHHCONX2TS U7586 ( .A(Sgf_normalized_result[44]), .CI(n8296), .CON(n8291),
.S(n8297) );
AOI22X1TS U7587 ( .A0(n8324), .A1(P_Sgf[96]), .B0(n8331), .B1(P_Sgf[97]),
.Y(n8298) );
OAI2BB1X1TS U7588 ( .A0N(Sgf_normalized_result[44]), .A1N(n8333), .B0(n8298),
.Y(n8299) );
AOI21X1TS U7589 ( .A0(n8310), .A1(Add_result[45]), .B0(n8299), .Y(n8300) );
OAI2BB1X1TS U7590 ( .A0N(Add_result[44]), .A1N(n8319), .B0(n8300), .Y(n396)
);
AHHCINX2TS U7591 ( .A(Sgf_normalized_result[43]), .CIN(n8301), .S(n8302),
.CO(n8296) );
AOI22X1TS U7592 ( .A0(n8324), .A1(P_Sgf[95]), .B0(n8331), .B1(P_Sgf[96]),
.Y(n8303) );
OAI2BB1X1TS U7593 ( .A0N(Sgf_normalized_result[43]), .A1N(n8333), .B0(n8303),
.Y(n8304) );
AOI21X1TS U7594 ( .A0(n8310), .A1(Add_result[44]), .B0(n8304), .Y(n8305) );
OAI2BB1X1TS U7595 ( .A0N(Add_result[43]), .A1N(n8319), .B0(n8305), .Y(n395)
);
AHHCONX2TS U7596 ( .A(Sgf_normalized_result[42]), .CI(n8306), .CON(n8301),
.S(n8307) );
AOI22X1TS U7597 ( .A0(n8324), .A1(P_Sgf[94]), .B0(n8331), .B1(P_Sgf[95]),
.Y(n8308) );
OAI2BB1X1TS U7598 ( .A0N(Sgf_normalized_result[42]), .A1N(n8333), .B0(n8308),
.Y(n8309) );
AOI21X1TS U7599 ( .A0(n8310), .A1(Add_result[43]), .B0(n8309), .Y(n8311) );
OAI2BB1X1TS U7600 ( .A0N(Add_result[42]), .A1N(n8319), .B0(n8311), .Y(n394)
);
NAND2X1TS U7601 ( .A(n8358), .B(n8313), .Y(n8314) );
XOR2X1TS U7602 ( .A(n8314), .B(n8885), .Y(n8315) );
AOI22X1TS U7603 ( .A0(n8324), .A1(P_Sgf[93]), .B0(n8331), .B1(P_Sgf[94]),
.Y(n8316) );
OAI2BB1X1TS U7604 ( .A0N(Sgf_normalized_result[41]), .A1N(n8333), .B0(n8316),
.Y(n8317) );
AOI21X1TS U7605 ( .A0(n8474), .A1(Add_result[42]), .B0(n8317), .Y(n8318) );
OAI2BB1X1TS U7606 ( .A0N(Add_result[41]), .A1N(n8319), .B0(n8318), .Y(n393)
);
NAND2X1TS U7607 ( .A(n8358), .B(n8321), .Y(n8322) );
XOR2X1TS U7608 ( .A(n8322), .B(n8854), .Y(n8323) );
AOI22X1TS U7609 ( .A0(n8324), .A1(P_Sgf[92]), .B0(n8331), .B1(P_Sgf[93]),
.Y(n8325) );
OAI2BB1X1TS U7610 ( .A0N(Sgf_normalized_result[40]), .A1N(n8384), .B0(n8325),
.Y(n8326) );
AOI21X1TS U7611 ( .A0(n8474), .A1(Add_result[41]), .B0(n8326), .Y(n8327) );
OAI2BB1X1TS U7612 ( .A0N(Add_result[40]), .A1N(n8387), .B0(n8327), .Y(n392)
);
NAND2X1TS U7613 ( .A(n8358), .B(n8328), .Y(n8336) );
XNOR2X1TS U7614 ( .A(n8329), .B(n8849), .Y(n8330) );
AOI22X1TS U7615 ( .A0(n8382), .A1(P_Sgf[91]), .B0(n8331), .B1(P_Sgf[92]),
.Y(n8332) );
OAI2BB1X1TS U7616 ( .A0N(Sgf_normalized_result[39]), .A1N(n8333), .B0(n8332),
.Y(n8334) );
AOI21X1TS U7617 ( .A0(n8474), .A1(Add_result[40]), .B0(n8334), .Y(n8335) );
OAI2BB1X1TS U7618 ( .A0N(Add_result[39]), .A1N(n8387), .B0(n8335), .Y(n391)
);
XOR2X1TS U7619 ( .A(n8336), .B(n8853), .Y(n8337) );
AOI22X1TS U7620 ( .A0(n8382), .A1(P_Sgf[90]), .B0(n8381), .B1(P_Sgf[91]),
.Y(n8338) );
OAI2BB1X1TS U7621 ( .A0N(Sgf_normalized_result[38]), .A1N(n8384), .B0(n8338),
.Y(n8339) );
AOI21X1TS U7622 ( .A0(n8474), .A1(Add_result[39]), .B0(n8339), .Y(n8340) );
OAI2BB1X1TS U7623 ( .A0N(Add_result[38]), .A1N(n8387), .B0(n8340), .Y(n390)
);
INVX2TS U7624 ( .A(n8341), .Y(n8342) );
NAND2X1TS U7625 ( .A(n8358), .B(n8342), .Y(n8348) );
XNOR2X1TS U7626 ( .A(n8343), .B(n8889), .Y(n8344) );
AOI22X1TS U7627 ( .A0(n8382), .A1(P_Sgf[89]), .B0(n8381), .B1(P_Sgf[90]),
.Y(n8345) );
OAI2BB1X1TS U7628 ( .A0N(Sgf_normalized_result[37]), .A1N(n8384), .B0(n8345),
.Y(n8346) );
AOI21X1TS U7629 ( .A0(n8474), .A1(Add_result[38]), .B0(n8346), .Y(n8347) );
OAI2BB1X1TS U7630 ( .A0N(Add_result[37]), .A1N(n8387), .B0(n8347), .Y(n389)
);
XOR2X1TS U7631 ( .A(n8348), .B(n8870), .Y(n8349) );
AOI22X1TS U7632 ( .A0(n8382), .A1(P_Sgf[88]), .B0(n8381), .B1(P_Sgf[89]),
.Y(n8350) );
OAI2BB1X1TS U7633 ( .A0N(Sgf_normalized_result[36]), .A1N(n8384), .B0(n8350),
.Y(n8351) );
AOI21X1TS U7634 ( .A0(n8404), .A1(Add_result[37]), .B0(n8351), .Y(n8352) );
OAI2BB1X1TS U7635 ( .A0N(Add_result[36]), .A1N(n8387), .B0(n8352), .Y(n388)
);
NAND2X1TS U7636 ( .A(n8358), .B(Sgf_normalized_result[34]), .Y(n8353) );
XOR2X1TS U7637 ( .A(n8353), .B(n8886), .Y(n8354) );
AOI22X1TS U7638 ( .A0(n8382), .A1(P_Sgf[87]), .B0(n8381), .B1(P_Sgf[88]),
.Y(n8355) );
OAI2BB1X1TS U7639 ( .A0N(Sgf_normalized_result[35]), .A1N(n8384), .B0(n8355),
.Y(n8356) );
AOI21X1TS U7640 ( .A0(n8404), .A1(Add_result[36]), .B0(n8356), .Y(n8357) );
OAI2BB1X1TS U7641 ( .A0N(Add_result[35]), .A1N(n8387), .B0(n8357), .Y(n387)
);
XNOR2X1TS U7642 ( .A(n8358), .B(n8863), .Y(n8359) );
AOI22X1TS U7643 ( .A0(n8382), .A1(P_Sgf[86]), .B0(n8381), .B1(P_Sgf[87]),
.Y(n8360) );
OAI2BB1X1TS U7644 ( .A0N(Sgf_normalized_result[34]), .A1N(n8384), .B0(n8360),
.Y(n8361) );
AOI21X1TS U7645 ( .A0(n8404), .A1(Add_result[35]), .B0(n8361), .Y(n8362) );
OAI2BB1X1TS U7646 ( .A0N(Add_result[34]), .A1N(n8387), .B0(n8362), .Y(n386)
);
INVX2TS U7647 ( .A(n8407), .Y(n8413) );
INVX2TS U7648 ( .A(n8365), .Y(n8366) );
INVX2TS U7649 ( .A(n8378), .Y(n8388) );
NAND2X1TS U7650 ( .A(n8373), .B(Sgf_normalized_result[32]), .Y(n8368) );
XOR2X1TS U7651 ( .A(n8368), .B(n8887), .Y(n8369) );
AOI22X1TS U7652 ( .A0(n8382), .A1(P_Sgf[85]), .B0(n8381), .B1(P_Sgf[86]),
.Y(n8370) );
OAI2BB1X1TS U7653 ( .A0N(Sgf_normalized_result[33]), .A1N(n8384), .B0(n8370),
.Y(n8371) );
AOI21X1TS U7654 ( .A0(n8404), .A1(Add_result[34]), .B0(n8371), .Y(n8372) );
OAI2BB1X1TS U7655 ( .A0N(Add_result[33]), .A1N(n8387), .B0(n8372), .Y(n385)
);
XNOR2X1TS U7656 ( .A(n8373), .B(n8864), .Y(n8374) );
AOI22X1TS U7657 ( .A0(n8382), .A1(P_Sgf[84]), .B0(n8381), .B1(P_Sgf[85]),
.Y(n8375) );
OAI2BB1X1TS U7658 ( .A0N(Sgf_normalized_result[32]), .A1N(n8384), .B0(n8375),
.Y(n8376) );
AOI21X1TS U7659 ( .A0(n8404), .A1(Add_result[33]), .B0(n8376), .Y(n8377) );
OAI2BB1X1TS U7660 ( .A0N(Add_result[32]), .A1N(n8387), .B0(n8377), .Y(n384)
);
NAND2X1TS U7661 ( .A(n8378), .B(Sgf_normalized_result[30]), .Y(n8379) );
XOR2X1TS U7662 ( .A(n8379), .B(n8888), .Y(n8380) );
AOI22X1TS U7663 ( .A0(n8382), .A1(P_Sgf[83]), .B0(n8381), .B1(P_Sgf[84]),
.Y(n8383) );
OAI2BB1X1TS U7664 ( .A0N(Sgf_normalized_result[31]), .A1N(n8384), .B0(n8383),
.Y(n8385) );
AOI21X1TS U7665 ( .A0(n8567), .A1(Add_result[32]), .B0(n8385), .Y(n8386) );
OAI2BB1X1TS U7666 ( .A0N(Add_result[31]), .A1N(n8387), .B0(n8386), .Y(n383)
);
XOR2X1TS U7667 ( .A(n8388), .B(n8860), .Y(n8389) );
AOI22X1TS U7668 ( .A0(n8565), .A1(Sgf_normalized_result[30]), .B0(P_Sgf[82]),
.B1(n8505), .Y(n8391) );
OAI2BB1X1TS U7669 ( .A0N(Add_result[31]), .A1N(n8567), .B0(n8391), .Y(n8392)
);
AOI21X1TS U7670 ( .A0(P_Sgf[83]), .A1(n8441), .B0(n8392), .Y(n8393) );
OAI2BB1X1TS U7671 ( .A0N(n8571), .A1N(Add_result[30]), .B0(n8393), .Y(n382)
);
NAND2X1TS U7672 ( .A(n8401), .B(Sgf_normalized_result[28]), .Y(n8395) );
XOR2X1TS U7673 ( .A(n8395), .B(n8872), .Y(n8397) );
AOI22X1TS U7674 ( .A0(n8565), .A1(Sgf_normalized_result[29]), .B0(P_Sgf[81]),
.B1(n8447), .Y(n8398) );
OAI2BB1X1TS U7675 ( .A0N(Add_result[30]), .A1N(n8404), .B0(n8398), .Y(n8399)
);
AOI21X1TS U7676 ( .A0(n8441), .A1(P_Sgf[82]), .B0(n8399), .Y(n8400) );
OAI2BB1X1TS U7677 ( .A0N(n8571), .A1N(Add_result[29]), .B0(n8400), .Y(n381)
);
XNOR2X1TS U7678 ( .A(n8401), .B(n8855), .Y(n8402) );
AOI22X1TS U7679 ( .A0(n8565), .A1(Sgf_normalized_result[28]), .B0(P_Sgf[80]),
.B1(n8447), .Y(n8403) );
OAI2BB1X1TS U7680 ( .A0N(Add_result[29]), .A1N(n8404), .B0(n8403), .Y(n8405)
);
AOI21X1TS U7681 ( .A0(n8441), .A1(P_Sgf[81]), .B0(n8405), .Y(n8406) );
OAI2BB1X1TS U7682 ( .A0N(n8571), .A1N(Add_result[28]), .B0(n8406), .Y(n380)
);
NAND2X1TS U7683 ( .A(n8407), .B(Sgf_normalized_result[26]), .Y(n8408) );
XOR2X1TS U7684 ( .A(n8408), .B(n8873), .Y(n8409) );
BUFX3TS U7685 ( .A(n8474), .Y(n8465) );
AOI22X1TS U7686 ( .A0(n8565), .A1(Sgf_normalized_result[27]), .B0(P_Sgf[79]),
.B1(n8447), .Y(n8410) );
OAI2BB1X1TS U7687 ( .A0N(Add_result[28]), .A1N(n8465), .B0(n8410), .Y(n8411)
);
AOI21X1TS U7688 ( .A0(n8441), .A1(P_Sgf[80]), .B0(n8411), .Y(n8412) );
OAI2BB1X1TS U7689 ( .A0N(n8571), .A1N(Add_result[27]), .B0(n8412), .Y(n379)
);
XOR2X1TS U7690 ( .A(n8413), .B(n8861), .Y(n8414) );
AOI22X1TS U7691 ( .A0(n8565), .A1(Sgf_normalized_result[26]), .B0(P_Sgf[78]),
.B1(n8447), .Y(n8415) );
OAI2BB1X1TS U7692 ( .A0N(Add_result[27]), .A1N(n8465), .B0(n8415), .Y(n8416)
);
AOI21X1TS U7693 ( .A0(n8441), .A1(P_Sgf[79]), .B0(n8416), .Y(n8417) );
OAI2BB1X1TS U7694 ( .A0N(n8571), .A1N(Add_result[26]), .B0(n8417), .Y(n378)
);
INVX2TS U7695 ( .A(n8418), .Y(n8419) );
INVX2TS U7696 ( .A(n8431), .Y(n8437) );
NAND2X1TS U7697 ( .A(n8426), .B(Sgf_normalized_result[24]), .Y(n8421) );
XOR2X1TS U7698 ( .A(n8421), .B(n8874), .Y(n8422) );
AOI22X1TS U7699 ( .A0(n8565), .A1(Sgf_normalized_result[25]), .B0(P_Sgf[77]),
.B1(n8447), .Y(n8423) );
OAI2BB1X1TS U7700 ( .A0N(Add_result[26]), .A1N(n8465), .B0(n8423), .Y(n8424)
);
AOI21X1TS U7701 ( .A0(n8441), .A1(P_Sgf[78]), .B0(n8424), .Y(n8425) );
OAI2BB1X1TS U7702 ( .A0N(n8571), .A1N(Add_result[25]), .B0(n8425), .Y(n377)
);
XNOR2X1TS U7703 ( .A(n8426), .B(n8856), .Y(n8427) );
AOI22X1TS U7704 ( .A0(n8565), .A1(Sgf_normalized_result[24]), .B0(P_Sgf[76]),
.B1(n8447), .Y(n8428) );
OAI2BB1X1TS U7705 ( .A0N(Add_result[25]), .A1N(n8465), .B0(n8428), .Y(n8429)
);
AOI21X1TS U7706 ( .A0(n8441), .A1(P_Sgf[77]), .B0(n8429), .Y(n8430) );
OAI2BB1X1TS U7707 ( .A0N(n8571), .A1N(Add_result[24]), .B0(n8430), .Y(n376)
);
NAND2X1TS U7708 ( .A(n8431), .B(Sgf_normalized_result[22]), .Y(n8432) );
XOR2X1TS U7709 ( .A(n8432), .B(n8875), .Y(n8433) );
AOI22X1TS U7710 ( .A0(n8565), .A1(Sgf_normalized_result[23]), .B0(P_Sgf[75]),
.B1(n8447), .Y(n8434) );
OAI2BB1X1TS U7711 ( .A0N(Add_result[24]), .A1N(n8465), .B0(n8434), .Y(n8435)
);
AOI21X1TS U7712 ( .A0(n8441), .A1(P_Sgf[76]), .B0(n8435), .Y(n8436) );
OAI2BB1X1TS U7713 ( .A0N(n8571), .A1N(Add_result[23]), .B0(n8436), .Y(n375)
);
XOR2X1TS U7714 ( .A(n8437), .B(n8862), .Y(n8438) );
AOI22X1TS U7715 ( .A0(n8498), .A1(Sgf_normalized_result[22]), .B0(P_Sgf[74]),
.B1(n8447), .Y(n8439) );
OAI2BB1X1TS U7716 ( .A0N(Add_result[23]), .A1N(n8465), .B0(n8439), .Y(n8440)
);
AOI21X1TS U7717 ( .A0(n8441), .A1(P_Sgf[75]), .B0(n8440), .Y(n8442) );
OAI2BB1X1TS U7718 ( .A0N(n8571), .A1N(Add_result[22]), .B0(n8442), .Y(n374)
);
NOR2X1TS U7719 ( .A(n8462), .B(n8443), .Y(n8451) );
NAND2X1TS U7720 ( .A(n8451), .B(Sgf_normalized_result[20]), .Y(n8444) );
XOR2X1TS U7721 ( .A(n8444), .B(n8876), .Y(n8445) );
AOI22X1TS U7722 ( .A0(n8498), .A1(Sgf_normalized_result[21]), .B0(P_Sgf[73]),
.B1(n8447), .Y(n8448) );
OAI2BB1X1TS U7723 ( .A0N(Add_result[22]), .A1N(n8465), .B0(n8448), .Y(n8449)
);
AOI21X1TS U7724 ( .A0(n8508), .A1(P_Sgf[74]), .B0(n8449), .Y(n8450) );
OAI2BB1X1TS U7725 ( .A0N(n8510), .A1N(Add_result[21]), .B0(n8450), .Y(n373)
);
XNOR2X1TS U7726 ( .A(n8451), .B(n8857), .Y(n8452) );
AOI22X1TS U7727 ( .A0(n8498), .A1(Sgf_normalized_result[20]), .B0(P_Sgf[72]),
.B1(n8505), .Y(n8453) );
OAI2BB1X1TS U7728 ( .A0N(Add_result[21]), .A1N(n8465), .B0(n8453), .Y(n8454)
);
AOI21X1TS U7729 ( .A0(n8508), .A1(P_Sgf[73]), .B0(n8454), .Y(n8455) );
OAI2BB1X1TS U7730 ( .A0N(n8510), .A1N(Add_result[20]), .B0(n8455), .Y(n372)
);
XNOR2X1TS U7731 ( .A(n8456), .B(n8879), .Y(n8458) );
AOI22X1TS U7732 ( .A0(n8498), .A1(Sgf_normalized_result[19]), .B0(P_Sgf[71]),
.B1(n8505), .Y(n8459) );
OAI2BB1X1TS U7733 ( .A0N(Add_result[20]), .A1N(n8465), .B0(n8459), .Y(n8460)
);
AOI21X1TS U7734 ( .A0(n8508), .A1(P_Sgf[72]), .B0(n8460), .Y(n8461) );
OAI2BB1X1TS U7735 ( .A0N(n8510), .A1N(Add_result[19]), .B0(n8461), .Y(n371)
);
XOR2X1TS U7736 ( .A(n8462), .B(n8865), .Y(n8463) );
AOI22X1TS U7737 ( .A0(n8498), .A1(Sgf_normalized_result[18]), .B0(P_Sgf[70]),
.B1(n8505), .Y(n8464) );
OAI2BB1X1TS U7738 ( .A0N(Add_result[19]), .A1N(n8465), .B0(n8464), .Y(n8466)
);
AOI21X1TS U7739 ( .A0(n8508), .A1(P_Sgf[71]), .B0(n8466), .Y(n8467) );
OAI2BB1X1TS U7740 ( .A0N(n8510), .A1N(Add_result[18]), .B0(n8467), .Y(n370)
);
INVX2TS U7741 ( .A(n8468), .Y(n8517) );
INVX2TS U7742 ( .A(n8483), .Y(n8489) );
NAND2X1TS U7743 ( .A(n8489), .B(n8471), .Y(n8478) );
XNOR2X1TS U7744 ( .A(n8472), .B(n8880), .Y(n8473) );
BUFX3TS U7745 ( .A(n8474), .Y(n8534) );
AOI22X1TS U7746 ( .A0(n8498), .A1(Sgf_normalized_result[17]), .B0(P_Sgf[69]),
.B1(n8505), .Y(n8475) );
OAI2BB1X1TS U7747 ( .A0N(Add_result[18]), .A1N(n8534), .B0(n8475), .Y(n8476)
);
AOI21X1TS U7748 ( .A0(n8508), .A1(P_Sgf[70]), .B0(n8476), .Y(n8477) );
OAI2BB1X1TS U7749 ( .A0N(n8510), .A1N(Add_result[17]), .B0(n8477), .Y(n369)
);
XOR2X1TS U7750 ( .A(n8478), .B(n8866), .Y(n8479) );
AOI22X1TS U7751 ( .A0(n8498), .A1(Sgf_normalized_result[16]), .B0(P_Sgf[68]),
.B1(n8505), .Y(n8480) );
OAI2BB1X1TS U7752 ( .A0N(Add_result[17]), .A1N(n8534), .B0(n8480), .Y(n8481)
);
AOI21X1TS U7753 ( .A0(n8508), .A1(P_Sgf[69]), .B0(n8481), .Y(n8482) );
OAI2BB1X1TS U7754 ( .A0N(n8510), .A1N(Add_result[16]), .B0(n8482), .Y(n368)
);
XNOR2X1TS U7755 ( .A(n8484), .B(n8881), .Y(n8485) );
AOI22X1TS U7756 ( .A0(n8498), .A1(Sgf_normalized_result[15]), .B0(P_Sgf[67]),
.B1(n8505), .Y(n8486) );
OAI2BB1X1TS U7757 ( .A0N(Add_result[16]), .A1N(n8534), .B0(n8486), .Y(n8487)
);
AOI21X1TS U7758 ( .A0(n8508), .A1(P_Sgf[68]), .B0(n8487), .Y(n8488) );
OAI2BB1X1TS U7759 ( .A0N(n8510), .A1N(Add_result[15]), .B0(n8488), .Y(n367)
);
XNOR2X1TS U7760 ( .A(n8489), .B(n8869), .Y(n8490) );
AOI22X1TS U7761 ( .A0(n8498), .A1(Sgf_normalized_result[14]), .B0(P_Sgf[66]),
.B1(n8505), .Y(n8491) );
OAI2BB1X1TS U7762 ( .A0N(Add_result[15]), .A1N(n8534), .B0(n8491), .Y(n8492)
);
AOI21X1TS U7763 ( .A0(n8508), .A1(P_Sgf[67]), .B0(n8492), .Y(n8493) );
OAI2BB1X1TS U7764 ( .A0N(n8510), .A1N(Add_result[14]), .B0(n8493), .Y(n366)
);
NAND2X1TS U7765 ( .A(n8517), .B(n8495), .Y(n8502) );
XNOR2X1TS U7766 ( .A(n8496), .B(n8882), .Y(n8497) );
AOI22X1TS U7767 ( .A0(n8498), .A1(Sgf_normalized_result[13]), .B0(P_Sgf[65]),
.B1(n8505), .Y(n8499) );
OAI2BB1X1TS U7768 ( .A0N(Add_result[14]), .A1N(n8534), .B0(n8499), .Y(n8500)
);
AOI21X1TS U7769 ( .A0(n8508), .A1(P_Sgf[66]), .B0(n8500), .Y(n8501) );
OAI2BB1X1TS U7770 ( .A0N(n8510), .A1N(Add_result[13]), .B0(n8501), .Y(n365)
);
XOR2X1TS U7771 ( .A(n8502), .B(n8867), .Y(n8503) );
AOI22X1TS U7772 ( .A0(n8559), .A1(Sgf_normalized_result[12]), .B0(P_Sgf[64]),
.B1(n8505), .Y(n8506) );
OAI2BB1X1TS U7773 ( .A0N(Add_result[13]), .A1N(n8534), .B0(n8506), .Y(n8507)
);
AOI21X1TS U7774 ( .A0(n8508), .A1(P_Sgf[65]), .B0(n8507), .Y(n8509) );
OAI2BB1X1TS U7775 ( .A0N(n8510), .A1N(Add_result[12]), .B0(n8509), .Y(n364)
);
NAND2X1TS U7776 ( .A(n8517), .B(Sgf_normalized_result[10]), .Y(n8511) );
XOR2X1TS U7777 ( .A(n8511), .B(n8877), .Y(n8512) );
AOI22X1TS U7778 ( .A0(n8559), .A1(Sgf_normalized_result[11]), .B0(P_Sgf[63]),
.B1(n8564), .Y(n8514) );
OAI2BB1X1TS U7779 ( .A0N(Add_result[12]), .A1N(n8534), .B0(n8514), .Y(n8515)
);
AOI21X1TS U7780 ( .A0(n8569), .A1(P_Sgf[64]), .B0(n8515), .Y(n8516) );
OAI2BB1X1TS U7781 ( .A0N(n8563), .A1N(Add_result[11]), .B0(n8516), .Y(n363)
);
XNOR2X1TS U7782 ( .A(n8517), .B(n8858), .Y(n8519) );
AOI22X1TS U7783 ( .A0(n8559), .A1(Sgf_normalized_result[10]), .B0(P_Sgf[62]),
.B1(n8564), .Y(n8520) );
OAI2BB1X1TS U7784 ( .A0N(Add_result[11]), .A1N(n8534), .B0(n8520), .Y(n8521)
);
AOI21X1TS U7785 ( .A0(n8569), .A1(P_Sgf[63]), .B0(n8521), .Y(n8522) );
OAI2BB1X1TS U7786 ( .A0N(n8563), .A1N(Add_result[10]), .B0(n8522), .Y(n362)
);
NOR2X1TS U7787 ( .A(n8542), .B(n8524), .Y(n8531) );
NAND2X1TS U7788 ( .A(n8531), .B(Sgf_normalized_result[8]), .Y(n8525) );
XOR2X1TS U7789 ( .A(n8525), .B(n8878), .Y(n8527) );
AOI22X1TS U7790 ( .A0(n8559), .A1(Sgf_normalized_result[9]), .B0(P_Sgf[61]),
.B1(n8564), .Y(n8528) );
OAI2BB1X1TS U7791 ( .A0N(Add_result[10]), .A1N(n8534), .B0(n8528), .Y(n8529)
);
AOI21X1TS U7792 ( .A0(n8569), .A1(P_Sgf[62]), .B0(n8529), .Y(n8530) );
OAI2BB1X1TS U7793 ( .A0N(n8563), .A1N(Add_result[9]), .B0(n8530), .Y(n361)
);
XNOR2X1TS U7794 ( .A(n8531), .B(n8859), .Y(n8532) );
AOI22X1TS U7795 ( .A0(n8559), .A1(Sgf_normalized_result[8]), .B0(P_Sgf[60]),
.B1(n8564), .Y(n8533) );
OAI2BB1X1TS U7796 ( .A0N(Add_result[9]), .A1N(n8534), .B0(n8533), .Y(n8535)
);
AOI21X1TS U7797 ( .A0(n8569), .A1(P_Sgf[61]), .B0(n8535), .Y(n8536) );
OAI2BB1X1TS U7798 ( .A0N(n8563), .A1N(Add_result[8]), .B0(n8536), .Y(n360)
);
XNOR2X1TS U7799 ( .A(n8537), .B(n8883), .Y(n8538) );
AOI22X1TS U7800 ( .A0(n8559), .A1(Sgf_normalized_result[7]), .B0(P_Sgf[59]),
.B1(n8564), .Y(n8539) );
OAI2BB1X1TS U7801 ( .A0N(Add_result[8]), .A1N(n8567), .B0(n8539), .Y(n8540)
);
AOI21X1TS U7802 ( .A0(n8569), .A1(P_Sgf[60]), .B0(n8540), .Y(n8541) );
OAI2BB1X1TS U7803 ( .A0N(n8563), .A1N(Add_result[7]), .B0(n8541), .Y(n359)
);
XOR2X1TS U7804 ( .A(n8542), .B(n8868), .Y(n8543) );
AOI22X1TS U7805 ( .A0(n8559), .A1(Sgf_normalized_result[6]), .B0(P_Sgf[58]),
.B1(n8564), .Y(n8544) );
OAI2BB1X1TS U7806 ( .A0N(Add_result[7]), .A1N(n8567), .B0(n8544), .Y(n8545)
);
AOI21X1TS U7807 ( .A0(n8569), .A1(P_Sgf[59]), .B0(n8545), .Y(n8546) );
OAI2BB1X1TS U7808 ( .A0N(n8563), .A1N(Add_result[6]), .B0(n8546), .Y(n358)
);
XOR2X1TS U7809 ( .A(n8548), .B(Sgf_normalized_result[5]), .Y(n8549) );
AOI22X1TS U7810 ( .A0(n8559), .A1(Sgf_normalized_result[5]), .B0(P_Sgf[57]),
.B1(n8564), .Y(n8550) );
OAI2BB1X1TS U7811 ( .A0N(Add_result[6]), .A1N(n8567), .B0(n8550), .Y(n8551)
);
AOI21X1TS U7812 ( .A0(n8569), .A1(P_Sgf[58]), .B0(n8551), .Y(n8552) );
OAI2BB1X1TS U7813 ( .A0N(n8563), .A1N(Add_result[5]), .B0(n8552), .Y(n357)
);
XNOR2X1TS U7814 ( .A(n8553), .B(Sgf_normalized_result[4]), .Y(n8554) );
AOI22X1TS U7815 ( .A0(n8559), .A1(Sgf_normalized_result[4]), .B0(P_Sgf[56]),
.B1(n8564), .Y(n8555) );
OAI2BB1X1TS U7816 ( .A0N(Add_result[5]), .A1N(n8567), .B0(n8555), .Y(n8556)
);
AOI21X1TS U7817 ( .A0(n8569), .A1(P_Sgf[57]), .B0(n8556), .Y(n8557) );
OAI2BB1X1TS U7818 ( .A0N(n8563), .A1N(Add_result[4]), .B0(n8557), .Y(n356)
);
XNOR2X1TS U7819 ( .A(n8884), .B(Sgf_normalized_result[2]), .Y(n8558) );
AOI22X1TS U7820 ( .A0(n8559), .A1(Sgf_normalized_result[3]), .B0(P_Sgf[55]),
.B1(n8564), .Y(n8560) );
OAI2BB1X1TS U7821 ( .A0N(Add_result[4]), .A1N(n8567), .B0(n8560), .Y(n8561)
);
AOI21X1TS U7822 ( .A0(n8569), .A1(P_Sgf[56]), .B0(n8561), .Y(n8562) );
OAI2BB1X1TS U7823 ( .A0N(n8563), .A1N(Add_result[3]), .B0(n8562), .Y(n355)
);
AOI22X1TS U7824 ( .A0(n8565), .A1(Sgf_normalized_result[2]), .B0(P_Sgf[54]),
.B1(n8564), .Y(n8566) );
OAI2BB1X1TS U7825 ( .A0N(Add_result[3]), .A1N(n8567), .B0(n8566), .Y(n8568)
);
AOI21X1TS U7826 ( .A0(n8569), .A1(P_Sgf[55]), .B0(n8568), .Y(n8570) );
OAI2BB1X1TS U7827 ( .A0N(n8571), .A1N(Add_result[2]), .B0(n8570), .Y(n354)
);
AHHCONX2TS U7828 ( .A(Sgf_normalized_result[52]), .CI(n8572), .CON(n8573),
.S(n8255) );
INVX2TS U7829 ( .A(n8573), .Y(n8574) );
NAND2X1TS U7830 ( .A(n8577), .B(n8576), .Y(n8579) );
XOR2X1TS U7831 ( .A(n8579), .B(n8578), .Y(n8580) );
NAND2X1TS U7832 ( .A(n894), .B(n8581), .Y(n8583) );
XNOR2X1TS U7833 ( .A(n8583), .B(n8582), .Y(n8584) );
NOR2BX1TS U7834 ( .AN(n8590), .B(n906), .Y(n8591) );
NAND2X1TS U7835 ( .A(n893), .B(n8592), .Y(n8594) );
XNOR2X1TS U7836 ( .A(n8594), .B(n8593), .Y(n8596) );
INVX2TS U7837 ( .A(n8597), .Y(n8616) );
AOI21X1TS U7838 ( .A0(n8616), .A1(n892), .B0(n8598), .Y(n8601) );
NAND2X1TS U7839 ( .A(n909), .B(n8599), .Y(n8600) );
XOR2X1TS U7840 ( .A(n8601), .B(n8600), .Y(n8602) );
INVX2TS U7841 ( .A(n8603), .Y(n8605) );
NAND2X1TS U7842 ( .A(n8605), .B(n8604), .Y(n8606) );
XOR2X1TS U7843 ( .A(n8607), .B(n8606), .Y(n8609) );
INVX2TS U7844 ( .A(n8610), .Y(n8642) );
INVX2TS U7845 ( .A(n8641), .Y(n8611) );
NAND2X1TS U7846 ( .A(n8611), .B(n8640), .Y(n8612) );
XOR2X1TS U7847 ( .A(n8642), .B(n8612), .Y(n8613) );
NAND2X1TS U7848 ( .A(n892), .B(n8614), .Y(n8615) );
XNOR2X1TS U7849 ( .A(n8616), .B(n8615), .Y(n8617) );
NAND2X1TS U7850 ( .A(n8619), .B(n8657), .Y(n8620) );
XOR2X1TS U7851 ( .A(n8659), .B(n8620), .Y(n8621) );
INVX2TS U7852 ( .A(n8624), .Y(n8626) );
NAND2X1TS U7853 ( .A(n8626), .B(n8625), .Y(n8627) );
XNOR2X1TS U7854 ( .A(n8628), .B(n8627), .Y(n8629) );
INVX2TS U7855 ( .A(n8631), .Y(n8654) );
INVX2TS U7856 ( .A(n8653), .Y(n8632) );
AOI21X1TS U7857 ( .A0(n8700), .A1(n8654), .B0(n8632), .Y(n8637) );
INVX2TS U7858 ( .A(n8633), .Y(n8635) );
NAND2X1TS U7859 ( .A(n8635), .B(n8634), .Y(n8636) );
XOR2X1TS U7860 ( .A(n8637), .B(n8636), .Y(n8639) );
INVX2TS U7861 ( .A(n8643), .Y(n8645) );
NAND2X1TS U7862 ( .A(n8645), .B(n8644), .Y(n8646) );
XNOR2X1TS U7863 ( .A(n8647), .B(n8646), .Y(n8648) );
AOI21X1TS U7864 ( .A0(n8700), .A1(n8692), .B0(n8694), .Y(n8651) );
INVX2TS U7865 ( .A(n8696), .Y(n8649) );
NAND2X1TS U7866 ( .A(n8649), .B(n8695), .Y(n8650) );
XOR2X1TS U7867 ( .A(n8651), .B(n8650), .Y(n8652) );
NAND2X1TS U7868 ( .A(n8654), .B(n8653), .Y(n8655) );
XNOR2X1TS U7869 ( .A(n8700), .B(n8655), .Y(n8656) );
NAND2X1TS U7870 ( .A(n8661), .B(n8660), .Y(n8662) );
XNOR2X1TS U7871 ( .A(n8663), .B(n8662), .Y(n8664) );
NAND2X1TS U7872 ( .A(n8668), .B(n8667), .Y(n8669) );
XNOR2X1TS U7873 ( .A(n8670), .B(n8669), .Y(n8671) );
NAND2X1TS U7874 ( .A(n8673), .B(n8672), .Y(n8674) );
XOR2X1TS U7875 ( .A(n8725), .B(n8674), .Y(n8675) );
INVX2TS U7876 ( .A(n8731), .Y(n8676) );
INVX2TS U7877 ( .A(n8678), .Y(n8679) );
OAI21X1TS U7878 ( .A0(n8679), .A1(n8732), .B0(n8733), .Y(n8680) );
AOI21X1TS U7879 ( .A0(n8681), .A1(n8742), .B0(n8680), .Y(n8686) );
INVX2TS U7880 ( .A(n8682), .Y(n8684) );
NAND2X1TS U7881 ( .A(n8684), .B(n8683), .Y(n8685) );
XOR2X1TS U7882 ( .A(n8686), .B(n8685), .Y(n8687) );
NAND2X1TS U7883 ( .A(n8721), .B(n8688), .Y(n8689) );
XNOR2X1TS U7884 ( .A(n8690), .B(n8689), .Y(n8691) );
INVX2TS U7885 ( .A(n8692), .Y(n8693) );
AOI21X1TS U7886 ( .A0(n8700), .A1(n8699), .B0(n8698), .Y(n8705) );
INVX2TS U7887 ( .A(n8701), .Y(n8703) );
NAND2X1TS U7888 ( .A(n8703), .B(n8702), .Y(n8704) );
XOR2X1TS U7889 ( .A(n8705), .B(n8704), .Y(n8706) );
AOI21X1TS U7890 ( .A0(n8742), .A1(n8714), .B0(n8707), .Y(n8711) );
XOR2X1TS U7891 ( .A(n8711), .B(n8710), .Y(n8712) );
NAND2X1TS U7892 ( .A(n8714), .B(n8713), .Y(n8715) );
XNOR2X1TS U7893 ( .A(n8742), .B(n8715), .Y(n8716) );
INVX2TS U7894 ( .A(n8717), .Y(n8718) );
NAND2X1TS U7895 ( .A(n8718), .B(n8721), .Y(n8724) );
INVX2TS U7896 ( .A(n8719), .Y(n8722) );
AOI21X1TS U7897 ( .A0(n8722), .A1(n8721), .B0(n8720), .Y(n8723) );
NAND2X1TS U7898 ( .A(n8727), .B(n8726), .Y(n8728) );
XNOR2X1TS U7899 ( .A(n8729), .B(n8728), .Y(n8730) );
AOI21X1TS U7900 ( .A0(n8742), .A1(n8731), .B0(n8678), .Y(n8736) );
INVX2TS U7901 ( .A(n8732), .Y(n8734) );
NAND2X1TS U7902 ( .A(n8734), .B(n8733), .Y(n8735) );
XOR2X1TS U7903 ( .A(n8736), .B(n8735), .Y(n8737) );
INVX2TS U7904 ( .A(n8738), .Y(n8741) );
INVX2TS U7905 ( .A(n8739), .Y(n8740) );
AOI21X1TS U7906 ( .A0(n8742), .A1(n8741), .B0(n8740), .Y(n8747) );
INVX2TS U7907 ( .A(n8743), .Y(n8745) );
NAND2X1TS U7908 ( .A(n8745), .B(n8744), .Y(n8746) );
XOR2X1TS U7909 ( .A(n8747), .B(n8746), .Y(n8749) );
NAND2X1TS U7910 ( .A(n8828), .B(n8871), .Y(n603) );
NOR2BX1TS U7911 ( .AN(exp_oper_result[11]), .B(n8871), .Y(S_Oper_A_exp[11])
);
INVX2TS U7912 ( .A(n780), .Y(n8752) );
NAND2X1TS U7913 ( .A(n7815), .B(Exp_module_Overflow_flag_A), .Y(n8754) );
NAND4BX1TS U7914 ( .AN(n8757), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n8758) );
NAND4BX1TS U7915 ( .AN(n8758), .B(Exp_module_Data_S[9]), .C(
Exp_module_Data_S[8]), .D(Exp_module_Data_S[7]), .Y(n8759) );
NAND3BX1TS U7916 ( .AN(Exp_module_Data_S[10]), .B(n8830), .C(n8759), .Y(
n8760) );
OAI22X1TS U7917 ( .A0(Exp_module_Data_S[11]), .A1(n8760), .B0(n8830), .B1(
n8897), .Y(n351) );
AO22X1TS U7918 ( .A0(n8761), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n8765), .Y(n348) );
AO22X1TS U7919 ( .A0(n8838), .A1(Sgf_normalized_result[23]), .B0(
final_result_ieee[23]), .B1(n8765), .Y(n327) );
AO22X1TS U7920 ( .A0(n8838), .A1(Sgf_normalized_result[24]), .B0(
final_result_ieee[24]), .B1(n8765), .Y(n326) );
AO22X1TS U7921 ( .A0(n8838), .A1(Sgf_normalized_result[25]), .B0(
final_result_ieee[25]), .B1(n8765), .Y(n325) );
AO22X1TS U7922 ( .A0(n8838), .A1(Sgf_normalized_result[26]), .B0(
final_result_ieee[26]), .B1(n8765), .Y(n324) );
AO22X1TS U7923 ( .A0(n8838), .A1(Sgf_normalized_result[27]), .B0(
final_result_ieee[27]), .B1(n8765), .Y(n323) );
AO22X1TS U7924 ( .A0(n8838), .A1(Sgf_normalized_result[28]), .B0(
final_result_ieee[28]), .B1(n8765), .Y(n322) );
AO22X1TS U7925 ( .A0(n8838), .A1(Sgf_normalized_result[29]), .B0(
final_result_ieee[29]), .B1(n8765), .Y(n321) );
AO22X1TS U7926 ( .A0(n8838), .A1(Sgf_normalized_result[30]), .B0(
final_result_ieee[30]), .B1(n8765), .Y(n320) );
AO22X1TS U7927 ( .A0(n8766), .A1(Data_MY[63]), .B0(n8235), .B1(Op_MY[63]),
.Y(n608) );
AOI21X1TS U7928 ( .A0(FS_Module_state_reg[2]), .A1(n8768), .B0(n8767), .Y(
n8771) );
NOR4X1TS U7929 ( .A(Op_MY[19]), .B(Op_MY[18]), .C(Op_MY[15]), .D(Op_MY[2]),
.Y(n8777) );
NOR4X1TS U7930 ( .A(Op_MY[24]), .B(Op_MY[22]), .C(Op_MY[21]), .D(Op_MY[3]),
.Y(n8776) );
NOR4X1TS U7931 ( .A(Op_MY[14]), .B(Op_MY[8]), .C(Op_MY[7]), .D(Op_MY[4]),
.Y(n8775) );
NOR4X1TS U7932 ( .A(Op_MY[28]), .B(Op_MY[27]), .C(Op_MY[25]), .D(Op_MY[10]),
.Y(n8774) );
NAND4XLTS U7933 ( .A(n8777), .B(n8776), .C(n8775), .D(n8774), .Y(n8793) );
NOR4X1TS U7934 ( .A(Op_MY[36]), .B(Op_MY[29]), .C(Op_MY[17]), .D(n696), .Y(
n8781) );
NOR4X1TS U7935 ( .A(Op_MY[42]), .B(Op_MY[32]), .C(Op_MY[20]), .D(Op_MY[13]),
.Y(n8780) );
NOR4X1TS U7936 ( .A(Op_MY[43]), .B(Op_MY[31]), .C(Op_MY[30]), .D(Op_MY[11]),
.Y(n8778) );
NAND4XLTS U7937 ( .A(n8781), .B(n8780), .C(n8779), .D(n8778), .Y(n8792) );
NOR4X1TS U7938 ( .A(Op_MY[40]), .B(Op_MY[35]), .C(Op_MY[34]), .D(Op_MY[33]),
.Y(n8785) );
NOR4X1TS U7939 ( .A(Op_MY[48]), .B(Op_MY[44]), .C(Op_MY[39]), .D(Op_MY[5]),
.Y(n8784) );
NOR4X1TS U7940 ( .A(Op_MY[49]), .B(Op_MY[47]), .C(Op_MY[38]), .D(Op_MY[37]),
.Y(n8783) );
NAND4XLTS U7941 ( .A(n8785), .B(n8784), .C(n8783), .D(n8782), .Y(n8791) );
NOR4X1TS U7942 ( .A(Op_MY[57]), .B(Op_MY[56]), .C(Op_MY[55]), .D(Op_MY[54]),
.Y(n8789) );
NOR4X1TS U7943 ( .A(Op_MY[61]), .B(Op_MY[60]), .C(Op_MY[59]), .D(Op_MY[58]),
.Y(n8788) );
NOR4X1TS U7944 ( .A(Op_MY[26]), .B(Op_MY[23]), .C(Op_MY[0]), .D(Op_MY[62]),
.Y(n8787) );
NAND4XLTS U7945 ( .A(n8789), .B(n8788), .C(n8787), .D(n8786), .Y(n8790) );
OR4X2TS U7946 ( .A(n8793), .B(n8792), .C(n8791), .D(n8790), .Y(n8831) );
NOR4X1TS U7947 ( .A(Op_MX[36]), .B(Op_MX[24]), .C(Op_MX[18]), .D(Op_MX[12]),
.Y(n8797) );
NOR4X1TS U7948 ( .A(Op_MX[48]), .B(Op_MX[42]), .C(Op_MX[30]), .D(Op_MX[6]),
.Y(n8796) );
NAND4XLTS U7949 ( .A(n8797), .B(n8796), .C(n8795), .D(n673), .Y(n8827) );
NOR4X1TS U7950 ( .A(Op_MX[50]), .B(Op_MX[32]), .C(Op_MX[26]), .D(Op_MX[20]),
.Y(n8801) );
NOR4X1TS U7951 ( .A(Op_MX[34]), .B(Op_MX[28]), .C(Op_MX[16]), .D(Op_MX[4]),
.Y(n8800) );
NOR4X1TS U7952 ( .A(Op_MX[46]), .B(Op_MX[22]), .C(Op_MX[10]), .D(Op_MX[2]),
.Y(n8799) );
NAND4XLTS U7953 ( .A(n8802), .B(n8801), .C(n8800), .D(n8799), .Y(n8826) );
NOR4X1TS U7954 ( .A(n796), .B(n4497), .C(n8804), .D(n8803), .Y(n8818) );
NOR4X1TS U7955 ( .A(n8810), .B(n6660), .C(n8224), .D(n4607), .Y(n8817) );
NOR4X1TS U7956 ( .A(n709), .B(n695), .C(n8812), .D(n8811), .Y(n8816) );
NOR4X1TS U7957 ( .A(n701), .B(Op_MX[35]), .C(n8210), .D(Op_MX[11]), .Y(n8815) );
NAND4XLTS U7958 ( .A(n8818), .B(n8817), .C(n8816), .D(n8815), .Y(n8825) );
NOR4X1TS U7959 ( .A(Op_MX[57]), .B(Op_MX[56]), .C(Op_MX[55]), .D(Op_MX[54]),
.Y(n8823) );
NOR4X1TS U7960 ( .A(Op_MX[61]), .B(Op_MX[60]), .C(Op_MX[59]), .D(Op_MX[58]),
.Y(n8822) );
OR4X2TS U7961 ( .A(n8827), .B(n8826), .C(n8825), .D(n8824), .Y(n8829) );
AOI32X1TS U7962 ( .A0(n8831), .A1(n8830), .A2(n8829), .B0(n8894), .B1(n8828),
.Y(n474) );
INVX2TS U7963 ( .A(n8842), .Y(n8837) );
OA22X1TS U7964 ( .A0(n8840), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n8839), .Y(n298) );
OA22X1TS U7965 ( .A0(n8840), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n8839), .Y(n296) );
OA22X1TS U7966 ( .A0(n8840), .A1(final_result_ieee[55]), .B0(
exp_oper_result[3]), .B1(n8839), .Y(n295) );
OA22X1TS U7967 ( .A0(n8840), .A1(final_result_ieee[56]), .B0(
exp_oper_result[4]), .B1(n8839), .Y(n294) );
OA22X1TS U7968 ( .A0(n8842), .A1(final_result_ieee[61]), .B0(
exp_oper_result[9]), .B1(n8841), .Y(n289) );
OA22X1TS U7969 ( .A0(n8842), .A1(final_result_ieee[62]), .B0(
exp_oper_result[10]), .B1(n8841), .Y(n288) );
initial $sdf_annotate("FPU_Multiplication_Function_DW_1STAGE_syn.sdf");
endmodule
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