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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S2S_1_V
`define SKY130_FD_SC_LS__DLYMETAL6S2S_1_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog wrapper for dlymetal6s2s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlymetal6s2s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlymetal6s2s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlymetal6s2s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlymetal6s2s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlymetal6s2s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S2S_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$P_pp$PG$N (
Q ,
D ,
CLK ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_P_PP_PG_N_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_2_V
`define SKY130_FD_SC_LP__A32O_2_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a32o_2 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_2_V
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Instruction fetch pipeline stage
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* Fetch stage */
module uparc_fetch(
clk,
nrst,
/* CU signals */
i_pc,
i_jump_addr,
i_jump_valid,
i_except_valid,
i_except_haddr,
i_exec_stall,
i_mem_stall,
o_fetch_stall,
i_wait_stall,
o_bus_error,
o_addr_error,
i_nullify,
/* IFU signals */
o_addr,
i_instr_dat,
o_rd_cmd,
i_busy,
i_err_align,
i_err_bus,
/* Fetched instruction */
o_instr,
o_pc
);
localparam [`UPARC_INSTR_WIDTH-1:0] NOP = 32'h0000_0000;
/* Inputs */
input wire clk;
input wire nrst;
/* CU signals */
input wire [`UPARC_ADDR_WIDTH-1:0] i_pc;
input wire [`UPARC_ADDR_WIDTH-1:0] i_jump_addr;
input wire i_jump_valid;
input wire i_except_valid;
input wire [`UPARC_ADDR_WIDTH-1:0] i_except_haddr;
input wire i_exec_stall;
input wire i_mem_stall;
output wire o_fetch_stall;
input wire i_wait_stall;
output wire o_bus_error;
output wire o_addr_error;
input wire i_nullify;
/* IFU interface */
output reg [`UPARC_ADDR_WIDTH-1:0] o_addr;
input wire [`UPARC_INSTR_WIDTH-1:0] i_instr_dat;
output reg o_rd_cmd;
input wire i_busy;
input wire i_err_align;
input wire i_err_bus;
/* Fetched instruction */
output wire [`UPARC_INSTR_WIDTH-1:0] o_instr;
output reg [`UPARC_ADDR_WIDTH-1:0] o_pc;
wire core_stall = i_exec_stall || i_mem_stall || o_fetch_stall || i_wait_stall;
assign o_fetch_stall = i_busy;
assign o_bus_error = i_err_bus | err_bus_r;
assign o_addr_error = i_err_align | err_align_r;
assign o_instr = (!i_jump_valid && !i_nullify && !i_except_valid ? i_instr_dat : NOP);
/** Local wires and registers **/
reg err_bus_r;
reg err_align_r;
wire [`UPARC_ADDR_WIDTH-1:0] new_pc = !i_except_valid ?
(!i_jump_valid ? i_pc : i_jump_addr) : i_except_haddr;
/* IFU operation */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
o_addr <= {(`UPARC_ADDR_WIDTH){1'b0}};
o_pc <= {(`UPARC_ADDR_WIDTH){1'b0}};
o_rd_cmd <= 1'b0;
err_align_r <= 1'b0;
err_bus_r <= 1'b0;
end
else
begin
o_rd_cmd <= 1'b0;
err_bus_r <= err_bus_r | i_err_bus;
err_align_r <= err_align_r | i_err_align;
if(!core_stall)
begin
err_align_r <= 1'b0;
err_bus_r <= 1'b0;
o_addr <= new_pc;
o_pc <= new_pc;
o_rd_cmd <= !i_nullify ? 1'b1 : 1'b0;
end
end
end
endmodule /* uparc_fetch */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_2_V
`define SKY130_FD_SC_HS__NAND2B_2_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2b_2 (
Y ,
A_N ,
B ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2b_2 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_2_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_hdmi_tx #(
parameter ID = 0,
parameter CR_CB_N = 0,
parameter DEVICE_TYPE = 0,
parameter INTERFACE = "16_BIT",
parameter OUT_CLK_POLARITY = 0) (
// hdmi interface
input hdmi_clk,
output hdmi_out_clk,
// 16-bit interface
output hdmi_16_hsync,
output hdmi_16_vsync,
output hdmi_16_data_e,
output [15:0] hdmi_16_data,
output [15:0] hdmi_16_es_data,
// 24-bit interface
output hdmi_24_hsync,
output hdmi_24_vsync,
output hdmi_24_data_e,
output [23:0] hdmi_24_data,
// 36-bit interface
output hdmi_36_hsync,
output hdmi_36_vsync,
output hdmi_36_data_e,
output [35:0] hdmi_36_data,
// vdma interface
input vdma_clk,
input vdma_end_of_frame,
input vdma_valid,
input [63:0] vdma_data,
output vdma_ready,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready);
/* 0 = Launch on rising edge, 1 = Launch on falling edge */
localparam EMBEDDED_SYNC = (INTERFACE == "16_BIT_EMBEDDED_SYNC") ? 1 : 0;
localparam XILINX_7SERIES = 0;
localparam XILINX_ULTRASCALE = 1;
localparam ALTERA_5SERIES = 16;
// reset and clocks
wire up_rstn;
wire up_clk;
wire hdmi_rst;
wire vdma_rst;
// internal signals
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
wire hdmi_csc_bypass_s;
wire hdmi_ss_bypass_s;
wire [ 1:0] hdmi_srcsel_s;
wire [23:0] hdmi_const_rgb_s;
wire [15:0] hdmi_hl_active_s;
wire [15:0] hdmi_hl_width_s;
wire [15:0] hdmi_hs_width_s;
wire [15:0] hdmi_he_max_s;
wire [15:0] hdmi_he_min_s;
wire [15:0] hdmi_vf_active_s;
wire [15:0] hdmi_vf_width_s;
wire [15:0] hdmi_vs_width_s;
wire [15:0] hdmi_ve_max_s;
wire [15:0] hdmi_ve_min_s;
wire [23:0] hdmi_clip_max_s;
wire [23:0] hdmi_clip_min_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
wire hdmi_status_s;
wire vdma_wr_s;
wire [ 8:0] vdma_waddr_s;
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire vdma_tpm_oos_s;
// signal name changes
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// axi interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// processor interface
up_hdmi_tx i_up (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_clip_max (hdmi_clip_max_s),
.hdmi_clip_min (hdmi_clip_min_s),
.hdmi_status (hdmi_status_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_clk_ratio (32'd1),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// vdma interface
axi_hdmi_tx_vdma i_vdma (
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_end_of_frame (vdma_end_of_frame),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s));
// hdmi interface
axi_hdmi_tx_core #(
.CR_CB_N(CR_CB_N),
.EMBEDDED_SYNC(EMBEDDED_SYNC))
i_tx_core (
.hdmi_clk (hdmi_clk),
.hdmi_rst (hdmi_rst),
.hdmi_16_hsync (hdmi_16_hsync),
.hdmi_16_vsync (hdmi_16_vsync),
.hdmi_16_data_e (hdmi_16_data_e),
.hdmi_16_data (hdmi_16_data),
.hdmi_16_es_data (hdmi_16_es_data),
.hdmi_24_hsync (hdmi_24_hsync),
.hdmi_24_vsync (hdmi_24_vsync),
.hdmi_24_data_e (hdmi_24_data_e),
.hdmi_24_data (hdmi_24_data),
.hdmi_36_hsync (hdmi_36_hsync),
.hdmi_36_vsync (hdmi_36_vsync),
.hdmi_36_data_e (hdmi_36_data_e),
.hdmi_36_data (hdmi_36_data),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.hdmi_status (hdmi_status_s),
.vdma_clk (vdma_clk),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s),
.hdmi_hl_width (hdmi_hl_width_s),
.hdmi_hs_width (hdmi_hs_width_s),
.hdmi_he_max (hdmi_he_max_s),
.hdmi_he_min (hdmi_he_min_s),
.hdmi_vf_active (hdmi_vf_active_s),
.hdmi_vf_width (hdmi_vf_width_s),
.hdmi_vs_width (hdmi_vs_width_s),
.hdmi_ve_max (hdmi_ve_max_s),
.hdmi_ve_min (hdmi_ve_min_s),
.hdmi_clip_max (hdmi_clip_max_s),
.hdmi_clip_min (hdmi_clip_min_s));
// hdmi output clock
generate
if (DEVICE_TYPE == XILINX_ULTRASCALE) begin
ODDRE1 #(.SRVAL(1'b0)) i_clk_oddr (
.SR (1'b0),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.Q (hdmi_out_clk));
end
if (DEVICE_TYPE == ALTERA_5SERIES) begin
altddio_out #(.WIDTH(1)) i_clk_oddr (
.aclr (1'b0),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0),
.oe (1'b1),
.outclocken (1'b1),
.datain_h (~OUT_CLK_POLARITY),
.datain_l (OUT_CLK_POLARITY),
.outclock (hdmi_clk),
.oe_out (),
.dataout (hdmi_out_clk));
end
if (DEVICE_TYPE == XILINX_7SERIES) begin
ODDR #(.INIT(1'b0)) i_clk_oddr (
.R (1'b0),
.S (1'b0),
.CE (1'b1),
.D1 (~OUT_CLK_POLARITY),
.D2 (OUT_CLK_POLARITY),
.C (hdmi_clk),
.Q (hdmi_out_clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 15:45:17 04/03/2016
// Design Name:
// Module Name: contador_AD_HH_T_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_HH_T_2dig
(
input wire clk,
input wire reset,
input wire [3:0] en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_HH_T
);
localparam N = 5; // Para definir el número de bits del contador (hasta 23->5 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 5'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 10)
begin
if (enUP)
begin
if (q_act >= 5'd23) q_next = 5'd0;
else q_next = q_act + 5'd1;
end
else if (enDOWN)
begin
if (q_act == 5'd0) q_next = 5'd23;
else q_next = q_act - 5'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
5'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
5'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
5'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
5'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
5'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
5'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
5'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
5'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
5'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
5'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
5'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
5'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
5'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
5'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
5'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
5'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
5'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
5'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
5'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
5'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
5'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
5'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
5'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
5'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_HH_T = {digit1,digit0};
endmodule
|
module hazardcontroller(clk,rsd,rsd2,rtd,rtd2,rse,rse2,rte,rte2,branchd,branchd2,regwritee,regwritee2,memtorege,memtorege2,regwritem,regwritem2,
memtoregm,memtoregm2,regwritew,regwritew2,writerege,writerege2,writeregm,writeregm2,writeregw,writeregw2,stalld,stalld2,
stallf,stallf2,stalle,stalle2,stallm,stallm2,stallw,stallw2,flushe,flushe2,forwardad,forwardad2,forwardbd,forwardbd2,forwardae,forwardae2,forwardbe,forwardbe2,
memwritem,memwritem2,memwritee,memwritee2,hit,hit2,miss,miss2,dirty,dirty2,we2,we2_2,we3,we3_2,multen,multen2,multready,multready2,swstalle,lwstalle,branchstalld);
input clk,branchd,regwritee,regwritem,regwritew,memtorege,memtoregm,hit,miss,dirty,memwritem,memwritee,multen,multready;
input clk,branchd2,regwritee2,regwritem2,regwritew2,memtorege2,memtoregm2,hit2,miss2,dirty2,memwritem2,memwritee2,multen2,multready2;
input [4:0] rsd,rtd,rse,rte,writerege,writeregm,writeregw;
input [4:0] rsd2,rtd2,rse2,rte2,writerege2,writeregm2,writeregw2;
output reg stallf,stalld,stalle,stallm,stallw,flushe,we2,we3;
output reg stallf2,stalld2,stalle2,stallm2,stallw2,flushe2,we2_2,we3_2;
output reg [1:0] forwardad,forwardbd;
output reg [1:0] forwardad2,forwardbd2;
output reg [2:0] forwardae,forwardbe;
output reg [2:0] forwardae2,forwardbe2;
output reg swstalle,lwstalle,branchstalld;
reg lwstalld;
reg[5:0] count = 6'd20; // Used for 20 cycle main memory stall count
initial begin
count<=6'd20;
lwstalld <= 1'b0;
branchstalld <= 1'b0;
flushe <= 1'b0;
stalld <= 1'b0;
stallf <= 1'b0;
stalle <= 1'b0;
stallm <= 1'b0;
stallw <= 1'b0;
lwstalle <= 1'b0;
swstalle <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
forwardad <= 2'b0;
forwardbd <= 2'b0;
forwardae <= 3'b00;
forwardbe <= 3'b00;
flushe2 <= 1'b0;
stalld2 <= 1'b0;
stallf2 <= 1'b0;
stalle2 <= 1'b0;
stallm2 <= 1'b0;
stallw2 <= 1'b0;
we2_2 <= 1'b0;
we3_2 <= 1'b0;
forwardad2 <= 2'b0;
forwardbd2 <= 2'b0;
forwardae2 <= 3'b00;
forwardbe2 <= 3'b00;
end
// forwarding sources to D stage (branch equality)
always @( rsd, rsd2, rtd, rtd2, writeregm, regwritem, writeregm2, regwritem2 ) begin
forwardad <= 2'b00; forwardbd <= 2'b00;
forwardad2 <= 2'b00; forwardbd2 <= 2'b00;
if (rsd !=0 & (rsd == writeregm) & regwritem) // 1-->5
forwardad <= 2'b01;
else if (rtd !=0 & (rtd == writeregm) & regwritem) // 1-->5
forwardbd <= 2'b01;
if (rsd !=0 & (rsd == writeregm2) & regwritem2) // 1-->6
forwardad <= 2'b10;
else if (rtd !=0 & (rtd == writeregm2) & regwritem2) // 1-->6
forwardbd <= 2'b10;
if (rsd2 !=0 & (rsd2 == writeregm) & regwritem) // 2-->5
forwardad2 <= 2'b10;
else if (rtd2 !=0 & (rtd2 == writeregm) & regwritem) // 2-->5
forwardbd2 <= 2'b10;
if (rsd2 !=0 & (rsd2 == writeregm2) & regwritem2) // 2-->6
forwardad2 <= 2'b01;
else if (rtd2 !=0 & (rtd2 == writeregm2) & regwritem2) // 2-->6
forwardbd2 <= 2'b01;
end
// forwarding sources to E stage (ALU)
always @( rse, rse2, rte, rte2, writeregm, regwritem, writeregw, regwritew, regwritee ) begin
forwardae <= 2'b00; forwardbe <= 2'b00;
forwardae2 <= 2'b00; forwardbe2 <= 2'b00;
//if (rse != 0) begin
if ((rse == writeregm2) & regwritem2) // 4-->1
forwardae <= 3'b011;
else if ((rse == writeregm) & regwritem) // 3-->1
forwardae <= 3'b010;
else if ((rse == writeregw2) & regwritew2) // 6-->1
forwardae <= 3'b100;
else if ((rse == writeregw) & regwritew) // 5-->1
forwardae <= 3'b001;
if ((rse2 == writerege) & regwritee) // 1-->2
forwardae2 <= 3'b011;
else if ((rse2 == writeregm2) & regwritem2) // 4-->2
forwardae2 <= 3'b010;
else if ((rse2 == writeregm) & regwritem) // 3-->2
forwardae2 <= 3'b100;
else if ((rse2 == writeregw2) & regwritew2) // 6-->2
forwardae2 <= 3'b001;
else if ((rse2 == writeregw) & regwritew) // 5-->2
forwardae2 <= 3'b101;
//end
//if (rte != 0) begin
if ((rte == writeregm2) & regwritem2) // 4-->1
forwardbe <= 3'b011;
else if ((rte == writeregm) & regwritem) // 3-->1
forwardbe <= 3'b010;
else if ((rte == writeregw2) & regwritew2) // 6-->1
forwardbe <= 3'b100;
else if ((rte == writeregw) & regwritew) // 5-->1
forwardbe <= 3'b001;
if ((rte2 == writerege) & regwritee) // 1-->2
forwardbe2 <= 3'b011;
else if ((rte2 == writeregm2) & regwritem2) // 4-->2
forwardbe2 <= 3'b010;
else if ((rte2 == writeregm) & regwritem) // 3-->2
forwardbe2 <= 3'b100;
else if ((rte2 == writeregw2) & regwritew2) // 6-->2
forwardbe2 <= 3'b001;
else if ((rte2 == writeregw) & regwritew) // 5-->2
forwardbe2 <= 3'b101;
//end
end
// stall for cache
always @(posedge clk, memtoregm, memwritem) begin
if ((memtoregm || memwritem) && count>6'd19) begin
stallm = 1'b1;
count = count - 1;
end
else if ((memtoregm || memwritem) && count>6'd0) begin // Need to wait 1 cycle before valid dirty, hit, miss
if ((((miss || miss2) && dirty) || count>6'd18) || ((!hit || !hit2) && dirty && memtoregm)) begin
stallm = 1'b1;
count = count - 6'b1;
end
else if ((miss || miss2) && count==6'd1) begin
we2 = 1'b1;
count = count - 6'd1;
end
else if ((!hit || !hit2) && count==6'd1) begin
we3 = 1'b1;
count = count - 6'd1;
end
else if ((miss || miss2) || (!hit || !hit2))
count = 6'd0; // No write to main memory needed, just read, so no 20 cycles
end
else begin
we2 = 1'b0;
we3 = 1'b0;
stallm = 1'b0;
count = 6'd20;
end
end
// stalls
always @( memtorege, memwritee, rte, rse, rte, rtd, branchd, regwritee, writerege, rsd, memtoregm, writeregm, stallm,
memtorege2, memwritee2, rte2, rse2, rte2, rtd2, branchd2, regwritee2, writerege2, rsd2, memtoregm2, writeregm2, stallm2) begin
lwstalld = (memtorege && ((rte == rsd) || (rte == rtd))) || (memtorege2 && ((rte2 == rsd2) || (rte2 == rtd2)));
lwstalle = (memtorege && memtorege2 && !memtoregm);
swstalle = (memwritee && memwritee2 && !memwritem);
branchstalld = (branchd && (regwritee && ( (writerege == rsd) || (writerege == rtd) ))) ||
(branchd && (regwritee2 && ( (writerege2 == rsd) || (writerege2 == rtd) ))) ||
(branchd2 && (regwritee && ( (writerege == rsd2) || (writerege == rtd2) ))) ||
(branchd2 && (regwritee2 && ( (writerege2 == rsd2) || (writerege2 == rtd2) )));
stalle = lwstalle || swstalle || stallm || (multen && !multready);
stallw = stallm;
stalld = lwstalld || branchstalld || stalle;
stallf = stalld; // stalling D stalls all previous stages
flushe = branchstalld; // stalling D flushes next stage
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eb_e
//
// Generated
// by: wig
// on: Mon Sep 25 09:53:03 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eb_e.v,v 1.1 2006/09/25 15:14:59 wig Exp $
// $Date: 2006/09/25 15:14:59 $
// $Log: inst_eb_e.v,v $
// Revision 1.1 2006/09/25 15:14:59 wig
// Adding testcase for `foo support
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.93 2006/09/25 08:24:10 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_eb_e
//
// No user `defines in this module
module inst_eb_e
//
// Generated Module inst_eb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_eba
inst_eba_e inst_eba (
);
// End of Generated Instance Port Map for inst_eba
// Generated Instance Port Map for inst_ebb
inst_ebb_e inst_ebb (
);
// End of Generated Instance Port Map for inst_ebb
// Generated Instance Port Map for inst_ebc
inst_ebc_e inst_ebc (
);
// End of Generated Instance Port Map for inst_ebc
endmodule
//
// End of Generated Module rtl of inst_eb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
-- ============================================================================
-- FILE NAME : id_stage.v
-- DESCRIPTION : IDXe[W
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** ÂÊwb_t@C **********/
`include "isa.h"
`include "cpu.h"
/********** W
[ **********/
module id_stage (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** GPRC^tF[X **********/
input wire [`WordDataBus] gpr_rd_data_0, // ÇÝoµf[^ 0
input wire [`WordDataBus] gpr_rd_data_1, // ÇÝoµf[^ 1
output wire [`RegAddrBus] gpr_rd_addr_0, // ÇÝoµAhX 0
output wire [`RegAddrBus] gpr_rd_addr_1, // ÇÝoµAhX 1
/********** tH[fBO **********/
// EXXe[W©çÌtH[fBO
input wire ex_en, // pCvCf[^ÌLø
input wire [`WordDataBus] ex_fwd_data, // tH[fBOf[^
input wire [`RegAddrBus] ex_dst_addr, // «ÝAhX
input wire ex_gpr_we_, // «ÝLø
// MEMXe[W©çÌtH[fBO
input wire [`WordDataBus] mem_fwd_data, // tH[fBOf[^
/********** §äWX^C^tF[X **********/
input wire [`CpuExeModeBus] exe_mode, // Às[h
input wire [`WordDataBus] creg_rd_data, // ÇÝoµf[^
output wire [`RegAddrBus] creg_rd_addr, // ÇÝoµAhX
/********** pCvC§äM **********/
input wire stall, // Xg[
input wire flush, // tbV
output wire [`WordAddrBus] br_addr, // ªòAhX
output wire br_taken, // ªò̬§
output wire ld_hazard, // [hnU[h
/********** IF/IDpCvCWX^ **********/
input wire [`WordAddrBus] if_pc, // vOJE^
input wire [`WordDataBus] if_insn, // ½ß
input wire if_en, // pCvCf[^ÌLø
/********** ID/EXpCvCWX^ **********/
output wire [`WordAddrBus] id_pc, // vOJE^
output wire id_en, // pCvCf[^ÌLø
output wire [`AluOpBus] id_alu_op, // ALUIy[V
output wire [`WordDataBus] id_alu_in_0, // ALUüÍ 0
output wire [`WordDataBus] id_alu_in_1, // ALUüÍ 1
output wire id_br_flag, // ªòtO
output wire [`MemOpBus] id_mem_op, // Iy[V
output wire [`WordDataBus] id_mem_wr_data, // «Ýf[^
output wire [`CtrlOpBus] id_ctrl_op, // §äIy[V
output wire [`RegAddrBus] id_dst_addr, // GPR«ÝAhX
output wire id_gpr_we_, // GPR«ÝLø
output wire [`IsaExpBus] id_exp_code // áOR[h
);
/********** fR[hM **********/
wire [`AluOpBus] alu_op; // ALUIy[V
wire [`WordDataBus] alu_in_0; // ALUüÍ 0
wire [`WordDataBus] alu_in_1; // ALUüÍ 1
wire br_flag; // ªòtO
wire [`MemOpBus] mem_op; // Iy[V
wire [`WordDataBus] mem_wr_data; // «Ýf[^
wire [`CtrlOpBus] ctrl_op; // §äIy[V
wire [`RegAddrBus] dst_addr; // GPR«ÝAhX
wire gpr_we_; // GPR«ÝLø
wire [`IsaExpBus] exp_code; // áOR[h
/********** fR[_ **********/
decoder decoder (
/********** IF/IDpCvCWX^ **********/
.if_pc (if_pc), // vOJE^
.if_insn (if_insn), // ½ß
.if_en (if_en), // pCvCf[^ÌLø
/********** GPRC^tF[X **********/
.gpr_rd_data_0 (gpr_rd_data_0), // ÇÝoµf[^ 0
.gpr_rd_data_1 (gpr_rd_data_1), // ÇÝoµf[^ 1
.gpr_rd_addr_0 (gpr_rd_addr_0), // ÇÝoµAhX 0
.gpr_rd_addr_1 (gpr_rd_addr_1), // ÇÝoµAhX 1
/********** tH[fBO **********/
// IDXe[W©çÌtH[fBO
.id_en (id_en), // pCvCf[^ÌLø
.id_dst_addr (id_dst_addr), // «ÝAhX
.id_gpr_we_ (id_gpr_we_), // «ÝLø
.id_mem_op (id_mem_op), // Iy[V
// EXXe[W©çÌtH[fBO
.ex_en (ex_en), // pCvCf[^ÌLø
.ex_fwd_data (ex_fwd_data), // tH[fBOf[^
.ex_dst_addr (ex_dst_addr), // «ÝAhX
.ex_gpr_we_ (ex_gpr_we_), // «ÝLø
// MEMXe[W©çÌtH[fBO
.mem_fwd_data (mem_fwd_data), // tH[fBOf[^
/********** §äWX^C^tF[X **********/
.exe_mode (exe_mode), // Às[h
.creg_rd_data (creg_rd_data), // ÇÝoµf[^
.creg_rd_addr (creg_rd_addr), // ÇÝoµAhX
/********** fR[hM **********/
.alu_op (alu_op), // ALUIy[V
.alu_in_0 (alu_in_0), // ALUüÍ 0
.alu_in_1 (alu_in_1), // ALUüÍ 1
.br_addr (br_addr), // ªòAhX
.br_taken (br_taken), // ªò̬§
.br_flag (br_flag), // ªòtO
.mem_op (mem_op), // Iy[V
.mem_wr_data (mem_wr_data), // «Ýf[^
.ctrl_op (ctrl_op), // §äIy[V
.dst_addr (dst_addr), // ÄpWX^«ÝAhX
.gpr_we_ (gpr_we_), // ÄpWX^«ÝLø
.exp_code (exp_code), // áOR[h
.ld_hazard (ld_hazard) // [hnU[h
);
/********** pCvCWX^ **********/
id_reg id_reg (
/********** NbN & Zbg **********/
.clk (clk), // NbN
.reset (reset), // ñ¯úZbg
/********** fR[hÊ **********/
.alu_op (alu_op), // ALUIy[V
.alu_in_0 (alu_in_0), // ALUüÍ 0
.alu_in_1 (alu_in_1), // ALUüÍ 1
.br_flag (br_flag), // ªòtO
.mem_op (mem_op), // Iy[V
.mem_wr_data (mem_wr_data), // «Ýf[^
.ctrl_op (ctrl_op), // §äIy[V
.dst_addr (dst_addr), // ÄpWX^«ÝAhX
.gpr_we_ (gpr_we_), // ÄpWX^«ÝLø
.exp_code (exp_code), // áOR[h
/********** pCvC§äM **********/
.stall (stall), // Xg[
.flush (flush), // tbV
/********** IF/IDpCvCWX^ **********/
.if_pc (if_pc), // vOJE^
.if_en (if_en), // pCvCf[^ÌLø
/********** ID/EXpCvCWX^ **********/
.id_pc (id_pc), // vOJE^
.id_en (id_en), // pCvCf[^ÌLø
.id_alu_op (id_alu_op), // ALUIy[V
.id_alu_in_0 (id_alu_in_0), // ALUüÍ 0
.id_alu_in_1 (id_alu_in_1), // ALUüÍ 1
.id_br_flag (id_br_flag), // ªòtO
.id_mem_op (id_mem_op), // Iy[V
.id_mem_wr_data (id_mem_wr_data), // «Ýf[^
.id_ctrl_op (id_ctrl_op), // §äIy[V
.id_dst_addr (id_dst_addr), // ÄpWX^«ÝAhX
.id_gpr_we_ (id_gpr_we_), // ÄpWX^«ÝLø
.id_exp_code (id_exp_code) // áOR[h
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_V
`define SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__ebufn (
Z ,
A ,
TE_B
);
// Module ports
output Z ;
input A ;
input TE_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif0 bufif00 (Z , A, TE_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_V
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/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a buffer that holds characters to be displayed on a *
* VGA or LCD screen. *
* *
******************************************************************************/
module video_character_buffer_with_dma_0 (
// Inputs
clk,
reset,
ctrl_address,
ctrl_byteenable,
ctrl_chipselect,
ctrl_read,
ctrl_write,
ctrl_writedata,
buf_address,
buf_byteenable,
buf_chipselect,
buf_read,
buf_write,
buf_writedata,
stream_ready,
// Bidirectionals
// Outputs
ctrl_readdata,
buf_readdata,
buf_waitrequest,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 8;
parameter ENLARGE_CHAR = 0;
parameter AW = 13;
parameter BUFFER_SIZE = 8192;
parameter PIXELS = 640;
parameter LINES = 480;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input ctrl_address;
input [ 3: 0] ctrl_byteenable;
input ctrl_chipselect;
input ctrl_read;
input ctrl_write;
input [31: 0] ctrl_writedata;
input [(AW-1): 0] buf_address;
input buf_byteenable;
input buf_chipselect;
input buf_read;
input buf_write;
input [ 7: 0] buf_writedata;
input stream_ready;
// Bidirectionals
// Outputs
output reg [31: 0] ctrl_readdata;
output reg [ 7: 0] buf_readdata;
output buf_waitrequest;
output [29: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [ 1: 0] stream_empty;
output stream_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
//localparam NUMBER_OF_BITS_FOR_X_COORD = 10;
//localparam NUMBER_OF_BITS_FOR_Y_COORD = 9;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 1] char_data_to_buffer;
wire [DW: 1] char_data_from_buffer;
wire [AW: 1] cur_char_position;
wire [15: 0] cur_char_for_display;
wire cur_char_data;
wire [ 9: 0] char_red;
wire [ 9: 0] char_green;
wire [ 9: 0] char_blue;
// Internal Registers
reg [31: 0] control_reg;
reg [ 1: 0] delayed_buf_waitrequest;
reg clear_screen;
reg [ 9: 0] x_position;
reg [ 8: 0] y_position;
reg [ 5: 0] delayed_x_position;
reg [ 5: 0] delayed_y_position;
reg [ 3: 0] delayed_startofpacket;
reg [ 3: 0] delayed_endofpacket;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
ctrl_readdata <= 32'h00000000;
else if (ctrl_chipselect & ctrl_read & ctrl_address)
ctrl_readdata <= {16'd60, 16'd80};
else if (ctrl_chipselect & ctrl_read)
ctrl_readdata <= control_reg;
end
always @(posedge clk)
begin
if (reset)
buf_readdata <= 8'h00;
else if (buf_chipselect & buf_read)
buf_readdata <= {1'b0, char_data_from_buffer[7:1]};
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
control_reg <= 32'h00010000;
else if (ctrl_chipselect & ctrl_write & ~ctrl_address)
begin
if (ctrl_byteenable[0])
control_reg[ 7: 0] <= ctrl_writedata[ 7: 0];
if (ctrl_byteenable[1])
control_reg[15: 8] <= ctrl_writedata[15: 8];
if (ctrl_byteenable[2])
control_reg[23:16] <= ctrl_writedata[23:16];
if (ctrl_byteenable[3])
control_reg[31:24] <= ctrl_writedata[31:24];
end
else if (clear_screen & stream_ready &
(x_position == (PIXELS - 1)) && (y_position == (LINES - 1)))
control_reg[16] <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
delayed_buf_waitrequest <= 2'h0;
else if (buf_chipselect & buf_read)
delayed_buf_waitrequest <= {delayed_buf_waitrequest[0], 1'b1};
else
delayed_buf_waitrequest <= 2'h0;
end
always @(posedge clk)
begin
if (reset)
clear_screen <= 1'b1;
else if (~(control_reg[16]))
clear_screen <= 1'b0;
else if ((x_position == 10'h000) && (y_position == 9'h000))
clear_screen <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
x_position <= 10'h000;
else if (stream_ready)
begin
if (x_position == (PIXELS - 1))
x_position <= 10'h000;
else
x_position <= x_position + 10'h001;
end
end
always @(posedge clk)
begin
if (reset)
y_position <= 9'h000;
else if (stream_ready && (x_position == (PIXELS - 1)))
begin
if (y_position == (LINES - 1))
y_position <= 9'h000;
else
y_position <= y_position + 9'h001;
end
end
always @(posedge clk)
begin
if (reset)
begin
delayed_x_position <= 6'h00;
delayed_y_position <= 6'h00;
end
else if (stream_ready)
begin
delayed_x_position <= {delayed_x_position[2:0],
x_position[(ENLARGE_CHAR+2):ENLARGE_CHAR]};
delayed_y_position <= {delayed_y_position[2:0],
y_position[(ENLARGE_CHAR+2):ENLARGE_CHAR]};
end
end
always @(posedge clk)
begin
if (reset)
delayed_startofpacket <= 4'h0;
else if (stream_ready)
begin
delayed_startofpacket[3:1] <= delayed_startofpacket[2:0];
if ((x_position == 10'h000) && (y_position == 9'h000))
delayed_startofpacket[0] <= 1'b1;
else
delayed_startofpacket[0] <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
delayed_endofpacket <= 4'h0;
else if (stream_ready)
begin
delayed_endofpacket[3:1] <= delayed_endofpacket[2:0];
if ((x_position == (PIXELS - 1)) && (y_position == (LINES - 1)))
delayed_endofpacket[0] <= 1'b1;
else
delayed_endofpacket[0] <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign buf_waitrequest =
(buf_chipselect & buf_read) & ~delayed_buf_waitrequest[1];
assign stream_data[29: 0] = {char_red, char_green, char_blue};
assign stream_startofpacket = delayed_startofpacket[3];
assign stream_endofpacket = delayed_endofpacket[3];
assign stream_empty = 2'h0;
assign stream_valid = 1'b1;
// Internal Assignments
assign char_data_to_buffer = {control_reg[(DW-8):0], buf_writedata[6:0]};
assign cur_char_position =
{y_position[8:(3 + ENLARGE_CHAR)], x_position[9:(3 + ENLARGE_CHAR)]};
assign char_red = {10{cur_char_data}};
assign char_green = {10{cur_char_data}};
assign char_blue = {10{cur_char_data}};
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altsyncram Char_Buffer_Memory (
// Inputs
.clock0 (clk),
.address_a (buf_address),
.wren_a (buf_byteenable & buf_chipselect & buf_write),
.data_a (char_data_to_buffer),
.clock1 (clk),
.clocken1 (stream_ready),
.address_b (cur_char_position),
.wren_b (clear_screen),
.data_b ({{(DW - 7){1'b0}}, 7'h20}),
// Bidirectionals
// Outputs
.q_a (char_data_from_buffer),
.q_b (cur_char_for_display),
// Unused
.rden_b (1'b1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.clocken0 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.byteena_a (1'b1),
.byteena_b (1'b1),
.rden_a (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
);
defparam
Char_Buffer_Memory.init_file = "UNUSED",
Char_Buffer_Memory.intended_device_family = "Cyclone II",
Char_Buffer_Memory.lpm_type = "altsyncram",
Char_Buffer_Memory.operation_mode = "BIDIR_DUAL_PORT",
Char_Buffer_Memory.read_during_write_mode_mixed_ports = "DONT_CARE",
Char_Buffer_Memory.power_up_uninitialized = "FALSE",
Char_Buffer_Memory.address_reg_b = "CLOCK1",
Char_Buffer_Memory.indata_reg_b = "CLOCK1",
Char_Buffer_Memory.wrcontrol_wraddress_reg_b = "CLOCK1",
Char_Buffer_Memory.clock_enable_input_a = "BYPASS",
Char_Buffer_Memory.clock_enable_input_b = "NORMAL",
Char_Buffer_Memory.clock_enable_output_a = "BYPASS",
Char_Buffer_Memory.clock_enable_output_b = "NORMAL",
Char_Buffer_Memory.numwords_a = BUFFER_SIZE,
Char_Buffer_Memory.numwords_b = BUFFER_SIZE,
Char_Buffer_Memory.outdata_aclr_a = "NONE",
Char_Buffer_Memory.outdata_aclr_b = "NONE",
Char_Buffer_Memory.outdata_reg_a = "CLOCK0",
Char_Buffer_Memory.outdata_reg_b = "CLOCK1",
Char_Buffer_Memory.widthad_a = AW,
Char_Buffer_Memory.widthad_b = AW,
Char_Buffer_Memory.width_a = DW,
Char_Buffer_Memory.width_b = DW,
Char_Buffer_Memory.width_byteena_a = 1,
Char_Buffer_Memory.width_byteena_b = 1;
altera_up_video_128_character_rom Character_Rom (
// Inputs
.clk (clk),
.clk_en (stream_ready),
.character (cur_char_for_display[ 6: 0]),
.x_coordinate (delayed_x_position[ 5: 3]),
.y_coordinate (delayed_y_position[ 5: 3]),
// Bidirectionals
// Outputs
.character_data (cur_char_data)
);
endmodule
|
// ============================================================================
// Copyright (c) 2014 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email: [email protected]
// ============================================================================
// Modified: Satyen Akolkar and Andrei Usenka
// Date: Feb 25 2017
// ============================================================================
module hps_fpga_system(
///////// ADC /////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
///////// ARDUINO /////////
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
///////// FPGA /////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
///////// GPIO /////////
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
///////// HPS /////////
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout HPS_GSENSOR_INT,
inout HPS_I2C0_SCLK,
inout HPS_I2C0_SDAT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
///////// KEY /////////
input [1:0] KEY,
///////// LED /////////
output [7:0] LED,
///////// SW /////////
input [3:0] SW
);
//=======================================================
// REG/WIRE declarations
//=======================================================
// internal wires and registers declaration
wire [1:0] fpga_debounced_buttons;
wire [7:0] fpga_led_internal;
wire hps_fpga_reset_n;
wire [2:0] hps_reset_req;
wire hps_cold_reset;
wire hps_warm_reset;
wire hps_debug_reset;
wire [27:0] stm_hw_events;
// connection of internal logics
assign stm_hw_events = {{13{1'b0}},SW, fpga_led_internal, fpga_debounced_buttons};
//=======================================================
// Structural coding
//=======================================================
soc_system u0 (
//Clock&Reset
.clk_clk (FPGA_CLK1_50 ), // clk.clk
.reset_reset_n (1'b1 ), // reset.reset_n
//HPS ddr3
.memory_mem_a ( HPS_DDR3_ADDR), // memory.mem_a
.memory_mem_ba ( HPS_DDR3_BA), // .mem_ba
.memory_mem_ck ( HPS_DDR3_CK_P), // .mem_ck
.memory_mem_ck_n ( HPS_DDR3_CK_N), // .mem_ck_n
.memory_mem_cke ( HPS_DDR3_CKE), // .mem_cke
.memory_mem_cs_n ( HPS_DDR3_CS_N), // .mem_cs_n
.memory_mem_ras_n ( HPS_DDR3_RAS_N), // .mem_ras_n
.memory_mem_cas_n ( HPS_DDR3_CAS_N), // .mem_cas_n
.memory_mem_we_n ( HPS_DDR3_WE_N), // .mem_we_n
.memory_mem_reset_n ( HPS_DDR3_RESET_N), // .mem_reset_n
.memory_mem_dq ( HPS_DDR3_DQ), // .mem_dq
.memory_mem_dqs ( HPS_DDR3_DQS_P), // .mem_dqs
.memory_mem_dqs_n ( HPS_DDR3_DQS_N), // .mem_dqs_n
.memory_mem_odt ( HPS_DDR3_ODT), // .mem_odt
.memory_mem_dm ( HPS_DDR3_DM), // .mem_dm
.memory_oct_rzqin ( HPS_DDR3_RZQ), // .oct_rzqin
//HPS ethernet
.hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK), // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
.hps_0_hps_io_hps_io_emac1_inst_TXD0 ( HPS_ENET_TX_DATA[0] ), // .hps_io_emac1_inst_TXD0
.hps_0_hps_io_hps_io_emac1_inst_TXD1 ( HPS_ENET_TX_DATA[1] ), // .hps_io_emac1_inst_TXD1
.hps_0_hps_io_hps_io_emac1_inst_TXD2 ( HPS_ENET_TX_DATA[2] ), // .hps_io_emac1_inst_TXD2
.hps_0_hps_io_hps_io_emac1_inst_TXD3 ( HPS_ENET_TX_DATA[3] ), // .hps_io_emac1_inst_TXD3
.hps_0_hps_io_hps_io_emac1_inst_RXD0 ( HPS_ENET_RX_DATA[0] ), // .hps_io_emac1_inst_RXD0
.hps_0_hps_io_hps_io_emac1_inst_MDIO ( HPS_ENET_MDIO ), // .hps_io_emac1_inst_MDIO
.hps_0_hps_io_hps_io_emac1_inst_MDC ( HPS_ENET_MDC ), // .hps_io_emac1_inst_MDC
.hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV), // .hps_io_emac1_inst_RX_CTL
.hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN), // .hps_io_emac1_inst_TX_CTL
.hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_0_hps_io_hps_io_emac1_inst_RXD1 ( HPS_ENET_RX_DATA[1] ), // .hps_io_emac1_inst_RXD1
.hps_0_hps_io_hps_io_emac1_inst_RXD2 ( HPS_ENET_RX_DATA[2] ), // .hps_io_emac1_inst_RXD2
.hps_0_hps_io_hps_io_emac1_inst_RXD3 ( HPS_ENET_RX_DATA[3] ), // .hps_io_emac1_inst_RXD3
//HPS SD card
.hps_0_hps_io_hps_io_sdio_inst_CMD ( HPS_SD_CMD ), // .hps_io_sdio_inst_CMD
.hps_0_hps_io_hps_io_sdio_inst_D0 ( HPS_SD_DATA[0] ), // .hps_io_sdio_inst_D0
.hps_0_hps_io_hps_io_sdio_inst_D1 ( HPS_SD_DATA[1] ), // .hps_io_sdio_inst_D1
.hps_0_hps_io_hps_io_sdio_inst_CLK ( HPS_SD_CLK ), // .hps_io_sdio_inst_CLK
.hps_0_hps_io_hps_io_sdio_inst_D2 ( HPS_SD_DATA[2] ), // .hps_io_sdio_inst_D2
.hps_0_hps_io_hps_io_sdio_inst_D3 ( HPS_SD_DATA[3] ), // .hps_io_sdio_inst_D3
//HPS USB
.hps_0_hps_io_hps_io_usb1_inst_D0 ( HPS_USB_DATA[0] ), // .hps_io_usb1_inst_D0
.hps_0_hps_io_hps_io_usb1_inst_D1 ( HPS_USB_DATA[1] ), // .hps_io_usb1_inst_D1
.hps_0_hps_io_hps_io_usb1_inst_D2 ( HPS_USB_DATA[2] ), // .hps_io_usb1_inst_D2
.hps_0_hps_io_hps_io_usb1_inst_D3 ( HPS_USB_DATA[3] ), // .hps_io_usb1_inst_D3
.hps_0_hps_io_hps_io_usb1_inst_D4 ( HPS_USB_DATA[4] ), // .hps_io_usb1_inst_D4
.hps_0_hps_io_hps_io_usb1_inst_D5 ( HPS_USB_DATA[5] ), // .hps_io_usb1_inst_D5
.hps_0_hps_io_hps_io_usb1_inst_D6 ( HPS_USB_DATA[6] ), // .hps_io_usb1_inst_D6
.hps_0_hps_io_hps_io_usb1_inst_D7 ( HPS_USB_DATA[7] ), // .hps_io_usb1_inst_D7
.hps_0_hps_io_hps_io_usb1_inst_CLK ( HPS_USB_CLKOUT ), // .hps_io_usb1_inst_CLK
.hps_0_hps_io_hps_io_usb1_inst_STP ( HPS_USB_STP ), // .hps_io_usb1_inst_STP
.hps_0_hps_io_hps_io_usb1_inst_DIR ( HPS_USB_DIR ), // .hps_io_usb1_inst_DIR
.hps_0_hps_io_hps_io_usb1_inst_NXT ( HPS_USB_NXT ), // .hps_io_usb1_inst_NXT
//HPS SPI
.hps_0_hps_io_hps_io_spim1_inst_CLK ( HPS_SPIM_CLK ), // .hps_io_spim1_inst_CLK
.hps_0_hps_io_hps_io_spim1_inst_MOSI ( HPS_SPIM_MOSI ), // .hps_io_spim1_inst_MOSI
.hps_0_hps_io_hps_io_spim1_inst_MISO ( HPS_SPIM_MISO ), // .hps_io_spim1_inst_MISO
.hps_0_hps_io_hps_io_spim1_inst_SS0 ( HPS_SPIM_SS ), // .hps_io_spim1_inst_SS0
//HPS UART
.hps_0_hps_io_hps_io_uart0_inst_RX ( HPS_UART_RX ), // .hps_io_uart0_inst_RX
.hps_0_hps_io_hps_io_uart0_inst_TX ( HPS_UART_TX ), // .hps_io_uart0_inst_TX
//HPS I2C1
.hps_0_hps_io_hps_io_i2c0_inst_SDA ( HPS_I2C0_SDAT ), // .hps_io_i2c0_inst_SDA
.hps_0_hps_io_hps_io_i2c0_inst_SCL ( HPS_I2C0_SCLK ), // .hps_io_i2c0_inst_SCL
//HPS I2C2
.hps_0_hps_io_hps_io_i2c1_inst_SDA ( HPS_I2C1_SDAT ), // .hps_io_i2c1_inst_SDA
.hps_0_hps_io_hps_io_i2c1_inst_SCL ( HPS_I2C1_SCLK ), // .hps_io_i2c1_inst_SCL
//GPIO
.hps_0_hps_io_hps_io_gpio_inst_GPIO09 ( HPS_CONV_USB_N ), // .hps_io_gpio_inst_GPIO09
.hps_0_hps_io_hps_io_gpio_inst_GPIO35 ( HPS_ENET_INT_N ), // .hps_io_gpio_inst_GPIO35
.hps_0_hps_io_hps_io_gpio_inst_GPIO40 ( HPS_LTC_GPIO ), // .hps_io_gpio_inst_GPIO40
.hps_0_hps_io_hps_io_gpio_inst_GPIO53 ( HPS_LED ), // .hps_io_gpio_inst_GPIO53
.hps_0_hps_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY ), // .hps_io_gpio_inst_GPIO54
.hps_0_hps_io_hps_io_gpio_inst_GPIO61 ( HPS_GSENSOR_INT ), // .hps_io_gpio_inst_GPIO61
.hps_0_f2h_stm_hw_events_stm_hwevents (stm_hw_events), // hps_0_f2h_stm_hw_events.stm_hwevents
.hps_0_h2f_reset_reset_n (hps_fpga_reset_n), // hps_0_h2f_reset.reset_n
.hps_0_f2h_warm_reset_req_reset_n (~hps_warm_reset), // hps_0_f2h_warm_reset_req.reset_n
.hps_0_f2h_debug_reset_req_reset_n (~hps_debug_reset), // hps_0_f2h_debug_reset_req.reset_n
.hps_0_f2h_cold_reset_req_reset_n (~hps_cold_reset), // hps_0_f2h_cold_reset_req.reset_n
//7 GREEN LEDS
.leds_pio_0_external_connection_export (LED), // leds_pio_0_external_connection.export
//8 CHANNEL ADC (On-board SPI Interface Controller) Component From Terasic
.adc_ltc2308_0_conduit_end_adc_convst (ADC_CONVST), // adc_ltc2308_0_conduit_end.adc_convst
.adc_ltc2308_0_conduit_end_adc_sck (ADC_SCK), // .adc_sck
.adc_ltc2308_0_conduit_end_adc_sdi (ADC_SDI), // .adc_sdi
.adc_ltc2308_0_conduit_end_adc_sdo (ADC_SDO) // .adc_sdo
);
// Source/Probe megawizard instance
hps_reset hps_reset_inst (
.source_clk (FPGA_CLK1_50),
.source (hps_reset_req)
);
altera_edge_detector pulse_cold_reset (
.clk (FPGA_CLK1_50),
.rst_n (hps_fpga_reset_n),
.signal_in (hps_reset_req[0]),
.pulse_out (hps_cold_reset)
);
defparam pulse_cold_reset.PULSE_EXT = 6;
defparam pulse_cold_reset.EDGE_TYPE = 1;
defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_warm_reset (
.clk (FPGA_CLK1_50),
.rst_n (hps_fpga_reset_n),
.signal_in (hps_reset_req[1]),
.pulse_out (hps_warm_reset)
);
defparam pulse_warm_reset.PULSE_EXT = 2;
defparam pulse_warm_reset.EDGE_TYPE = 1;
defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_debug_reset (
.clk (FPGA_CLK1_50),
.rst_n (hps_fpga_reset_n),
.signal_in (hps_reset_req[2]),
.pulse_out (hps_debug_reset)
);
defparam pulse_debug_reset.PULSE_EXT = 32;
defparam pulse_debug_reset.EDGE_TYPE = 1;
defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__OR4B_FUNCTIONAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_FUNCTIONAL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [89:0] in;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [89:0] out; // From test of Test.v
wire [44:0] line0;
wire [44:0] line1;
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[89:0]),
.line0 (line0[44:0]),
.line1 (line1[44:0]),
// Inputs
.clk (clk),
.in (in[89:0]));
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
`endif
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
end
else if (cyc==10) begin
if (in==out) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$write("*-* Failed!! *-*\n");
$finish;
end
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
line0, line1, out,
// Inputs
clk, in
);
input clk;
input [89:0] in;
output reg [44:0] line0;
output reg [44:0] line1;
output reg [89:0] out;
assign {line0,line1} = in;
always @(posedge clk) begin
out <= {line0,line1};
end
endmodule
|
/* Copyright (C) 2015-2016 by John Cronin
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
// interrupt controller
module irq_ctrl(clk, rst_, data, addr, cs_, oe_, we_, irpts, cpu_int, cpu_int_ack);
input clk;
input rst_;
inout [7:0] data;
input [7:0] addr;
input cs_;
input oe_;
input we_;
input [31:0] irpts;
output reg cpu_int;
input cpu_int_ack;
reg [31:0] irq_mask = 32'd0;
reg [4:0] sirq_num = 5'd0;
reg sirq = 0;
// Read register support
assign data = (~cs_ & ~oe_) ?
((addr == 0) ? { sirq, 2'b0, sirq_num } :
((addr == 4) ? irq_mask[7:0] :
((addr == 5) ? irq_mask[15:8] :
((addr == 6) ? irq_mask[23:16] :
((addr == 7) ? irq_mask[31:24] : 8'b0))))) : 8'bzzzzzzzz;
// Registers
// 0 - in progress
// bits 4:0 - signalled interrupt number
// bit 6:5 - reserved
// bit 8 - interrupt signalled
// 7:4 - interrupt mask (0 = disabled, 1 = enabled)
// 8 - EOI
// write anything to address 8 to signal EOI
always @(posedge clk)
if(~sirq)
casez (irpts & irq_mask)
32'b???????????????????????????????1: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd0 };
32'b??????????????????????????????10: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd1 };
32'b?????????????????????????????100: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd2 };
32'b????????????????????????????1000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd3 };
32'b???????????????????????????10000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd4 };
32'b??????????????????????????100000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd5 };
32'b?????????????????????????1000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd6 };
32'b????????????????????????10000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd7 };
32'b???????????????????????100000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd8 };
32'b??????????????????????1000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd9 };
32'b?????????????????????10000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd10 };
32'b????????????????????100000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd11 };
32'b???????????????????1000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd12 };
32'b??????????????????10000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd13 };
32'b?????????????????100000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd14 };
32'b????????????????1000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd15 };
32'b???????????????10000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd16 };
32'b??????????????100000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd17 };
32'b?????????????1000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd18 };
32'b????????????10000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd19 };
32'b???????????100000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd20 };
32'b??????????1000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd21 };
32'b?????????10000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd22 };
32'b????????100000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd23 };
32'b???????1000000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd24 };
32'b??????10000000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd25 };
32'b?????100000000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd26 };
32'b????1000000000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd27 };
32'b???10000000000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd28 };
32'b??100000000000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd29 };
32'b?1000000000000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd30 };
32'b10000000000000000000000000000000: { cpu_int, sirq, sirq_num } <= { 1'b1, 1'b1, 5'd31 };
default: { cpu_int, sirq, sirq_num } <= { 1'b0, 1'b0, 5'd0 };
endcase
else if(cpu_int_ack) cpu_int <= 0;
else if(~cs_ & ~we_ & addr == 8'd8) { cpu_int, sirq } <= { 1'b0, 1'b0 };
else sirq <= 1'b1;
always @(posedge clk)
if(~cs_ & ~we_)
case (addr)
8'd4: irq_mask[7:0] <= data;
8'd5: irq_mask[15:8] <= data;
8'd6: irq_mask[23:16] <= data;
8'd7: irq_mask[31:24] <= data;
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_1_V
`define SKY130_FD_SC_HDLL__NOR4_1_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_1_V
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: gsu_fmult.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gsu_fmult (
clock,
dataa,
datab,
result);
input clock;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 2,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "2"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_fmult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_fmult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_fmult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_fmult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_fmult_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_fmult_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module alu(
input [31:0] A,
input [31:0] B,
input [2:0] ALU_operation,
output [31:0] res,
output zero,
output reg overflow
);
wire [31:0] res_and,res_or,res_add,res_sub,res_nor,res_slt;
reg [31:0] res_op;
parameter one = 32'h00000001,zero_0=32'h00000000;
assign res_and = A&B;
assign res_or = A|B;
assign res_add = A+B;
assign res_sub = A-B;
assign res_slt = (A<B)?one:zero_0;
assign res = res_op[31:0];
always @(*) begin
overflow = 0;
case(ALU_operation)
3'b000: res_op = res_and;
3'b001: res_op = res_or;
3'b010: begin
res_op = res_add;
if ((A[31:31]&B[31:31]&~res[31:31]) | (~A[31:31]&~B[31:31]&res[31:31]))
overflow = 1;
end
3'b110: begin
res_op = res_sub;
if ((A[31:31]&~B[31:31]&~res[31:31]) | (~A[31:31]&B[31:31]&res[31:31]))
overflow = 1;
end
3'b100: res_op = ~(A|B);
3'b111: res_op = res_slt;
3'b101: res_op = A >> 1;
3'b011: res_op = (~A&B) | (A&~B);
default: res_op=32'hxxxxxxxx;
endcase
end
assign zero = (res==0)?1:0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1P_SYMBOL_V
`define SKY130_FD_SC_LP__INPUTISO1P_SYMBOL_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__inputiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1P_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_BLACKBOX_V
/**
* udp_dff$NR_pp$PKG$sN: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$NR_pp$PKG$sN (
Q ,
D ,
CLK_N ,
RESET ,
SLEEP_B ,
NOTIFIER,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK_N ;
input RESET ;
input SLEEP_B ;
input NOTIFIER;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_SN_BLACKBOX_V
|
// file: ocxo_clk_pll.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______597.520____892.144
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary__________10.000___________0.00100
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "ocxo_clk_pll,clk_wiz_v5_1,{component_name=ocxo_clk_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_ONCHIP,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module ocxo_clk_pll
(
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input resetn,
output locked
);
ocxo_clk_pll_clk_wiz inst
(
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(clk_out1),
// Status and control signals
.resetn(resetn),
.locked(locked)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_BLACKBOX_V
`define SKY130_FD_SC_LS__DFBBN_BLACKBOX_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.72)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Regional Clock Buffer
// /___/ /\ Filename : BUFR.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 04/04/2005 - Add SIM_DEVICE paramter to support Virtex5. CE pin has 4 clock
// latency for Virtex 4 and none for Virtex5
// 07/25/05 - Updated names to Virtex5
// 08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch.
// 05/23/06 - Add count =0 and first_rise=1 when CE = 0 (CR232206).
// 07/19/06 - Add wire declaration for undeclared wire signals.
// 04/01/09 - CR 517236 -- Added VIRTEX6 support
// 11/13/09 - Added VIRTEX7
// 01/20/10 - Change VIRTEX7 to internal_name (CR545223)
// 02/23/10 - Use assign for o_out (CR543271)
// 06/09/10 - Change internal_name to 7_SERIES
// 08/18/10 - Change 7_SERIES to 7SERIES (CR571653)
// 08/09/11 - Add 7SERIES to ce_en logic (CR620544)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/15/12 - Match with hardware (CR 650440)
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFR (O, CE, CLR, I);
output O;
input CE;
input CLR;
input I;
parameter BUFR_DIVIDE = "BYPASS";
parameter SIM_DEVICE = "7SERIES";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
integer count, period_toggle, half_period_toggle;
reg first_rise, half_period_done;
reg notifier;
reg o_out_divide = 0;
wire o_out;
reg ce_enable1, ce_enable2, ce_enable3, ce_enable4;
tri0 GSR = glbl.GSR;
wire i_in, ce_in, clr_in, gsr_in, ce_en, i_ce;
buf buf_i (i_in, I);
buf buf_ce (ce_in, CE);
buf buf_clr (clr_in, CLR);
buf buf_gsr (gsr_in, GSR);
buf buf_o (O, o_out);
initial begin
case (BUFR_DIVIDE)
"BYPASS" : period_toggle = 0;
"1" : begin
period_toggle = 1;
half_period_toggle = 1;
end
"2" : begin
period_toggle = 2;
half_period_toggle = 2;
end
"3" : begin
period_toggle = 4;
half_period_toggle = 2;
end
"4" : begin
period_toggle = 4;
half_period_toggle = 4;
end
"5" : begin
period_toggle = 6;
half_period_toggle = 4;
end
"6" : begin
period_toggle = 6;
half_period_toggle = 6;
end
"7" : begin
period_toggle = 8;
half_period_toggle = 6;
end
"8" : begin
period_toggle = 8;
half_period_toggle = 8;
end
default : begin
$display("Attribute Syntax Error : The attribute BUFR_DIVIDE on BUFR instance %m is set to %s. Legal values for this attribute are BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8.", BUFR_DIVIDE);
#1 $finish;
end
endcase // case(BUFR_DIVIDE)
case (SIM_DEVICE)
"VIRTEX4" : ;
"VIRTEX5" : ;
"VIRTEX6" : ;
"7SERIES" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on BUFR instance %m is set to %s. Legal values for this attribute are VIRTEX4 or VIRTEX5 or VIRTEX6 or 7SERIES.", SIM_DEVICE);
#1 $finish;
end
endcase
end // initial begin
always @(gsr_in or clr_in)
if (gsr_in == 1'b1 || clr_in == 1'b1) begin
assign o_out_divide = 1'b0;
assign count = 0;
assign first_rise = 1'b1;
assign half_period_done = 1'b0;
if (gsr_in == 1'b1) begin
assign ce_enable1 = 1'b0;
assign ce_enable2 = 1'b0;
assign ce_enable3 = 1'b0;
assign ce_enable4 = 1'b0;
end
end
else if (gsr_in == 1'b0 || clr_in == 1'b0) begin
deassign o_out_divide;
deassign count;
deassign first_rise;
deassign half_period_done;
if (gsr_in == 1'b0) begin
deassign ce_enable1;
deassign ce_enable2;
deassign ce_enable3;
deassign ce_enable4;
end
end
always @(negedge i_in)
begin
ce_enable1 <= ce_in;
ce_enable2 <= ce_enable1;
ce_enable3 <= ce_enable2;
ce_enable4 <= ce_enable3;
end
assign ce_en = ((SIM_DEVICE == "VIRTEX5") || (SIM_DEVICE == "VIRTEX6") || (SIM_DEVICE == "7SERIES")) ? ce_in : ce_enable4;
assign i_ce = i_in & ce_en;
generate
case (SIM_DEVICE)
"VIRTEX4" : begin
always @(i_in or ce_en)
if (ce_en == 1'b1) begin
if (i_in == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0)
count = count + 1;
end // if (ce_in == 1'b1)
else begin
count = 0;
first_rise = 1;
end
end
"VIRTEX5","VIRTEX6","7SERIES" : begin
always @(i_ce)
begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0) begin
count = count + 1;
end // if (ce_in == 1'b1)
end
end
endcase
endgenerate
assign o_out = (period_toggle == 0) ? i_in : o_out_divide;
//*** Timing Checks Start here
always @(notifier) begin
o_out_divide <= 1'bx;
end
`ifdef XIL_TIMING
specify
(CLR => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge I, 0:0:0, 0, notifier);
$width (negedge I, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // BUFR
`endcelldefine
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: small_fifo_test.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Stratix II" LPM_NUMWORDS=32 LPM_SHOWAHEAD="OFF" LPM_WIDTH=32 LPM_WIDTHU=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" clock data empty full q rdreq sclr usedw wrreq INTENDED_DEVICE_FAMILY="Stratix II"
//VERSION_BEGIN 10.1SP1 cbx_altdpram 2011:01:19:21:13:40:SJ cbx_altsyncram 2011:01:19:21:13:40:SJ cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_fifo_common 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_counter 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_lpm_mux 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_scfifo 2011:01:19:21:13:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_stratixiii 2011:01:19:21:13:40:SJ cbx_stratixv 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Stratix II" LPM_NUMWORDS=32 LPM_SHOWAHEAD="OFF" lpm_width=32 lpm_widthu=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data empty full q rreq sclr usedw wreq INTENDED_DEVICE_FAMILY="Stratix II"
//VERSION_BEGIN 10.1SP1 cbx_altdpram 2011:01:19:21:13:40:SJ cbx_altsyncram 2011:01:19:21:13:40:SJ cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_fifo_common 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_counter 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_lpm_mux 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_scfifo 2011:01:19:21:13:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_stratixiii 2011:01:19:21:13:40:SJ cbx_stratixv 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ VERSION_END
//a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=32 lpm_widthad=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" aclr clock empty full rreq sclr usedw_out wreq
//VERSION_BEGIN 10.1SP1 cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_fifo_common 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_counter 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ VERSION_END
//lpm_counter DEVICE_FAMILY="Stratix II" lpm_width=5 aclr clock cnt_en q sclr updown
//VERSION_BEGIN 10.1SP1 cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_counter 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ VERSION_END
//synthesis_resources = lut 5 reg 5
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module small_fifo_test_cntr
(
aclr,
clock,
cnt_en,
q,
sclr,
updown) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [4:0] q;
input sclr;
input updown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 cnt_en;
tri0 sclr;
tri1 updown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_counter_comb_bita_0cout;
wire [0:0] wire_counter_comb_bita_1cout;
wire [0:0] wire_counter_comb_bita_2cout;
wire [0:0] wire_counter_comb_bita_3cout;
wire [0:0] wire_counter_comb_bita_0sumout;
wire [0:0] wire_counter_comb_bita_1sumout;
wire [0:0] wire_counter_comb_bita_2sumout;
wire [0:0] wire_counter_comb_bita_3sumout;
wire [0:0] wire_counter_comb_bita_4sumout;
wire [4:0] wire_counter_reg_bit1a_adatasdata;
wire [4:0] wire_counter_reg_bit1a_regout;
wire aclr_actual;
wire clk_en;
wire [4:0] data;
wire external_cin;
wire lsb_cin;
wire [4:0] s_val;
wire [4:0] safe_q;
wire sload;
wire sset;
wire updown_dir;
wire updown_lsb;
wire updown_other_bits;
stratixii_lcell_comb counter_comb_bita_0
(
.cin(lsb_cin),
.combout(),
.cout(wire_counter_comb_bita_0cout[0:0]),
.datad(wire_counter_reg_bit1a_regout[0:0]),
.dataf(updown_lsb),
.shareout(),
.sumout(wire_counter_comb_bita_0sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_0.extended_lut = "off",
counter_comb_bita_0.lut_mask = 64'h000000000000FF00,
counter_comb_bita_0.shared_arith = "off",
counter_comb_bita_0.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_comb counter_comb_bita_1
(
.cin(wire_counter_comb_bita_0cout[0:0]),
.combout(),
.cout(wire_counter_comb_bita_1cout[0:0]),
.datad(wire_counter_reg_bit1a_regout[1:1]),
.dataf(updown_other_bits),
.shareout(),
.sumout(wire_counter_comb_bita_1sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_1.extended_lut = "off",
counter_comb_bita_1.lut_mask = 64'h0000FF000000FF00,
counter_comb_bita_1.shared_arith = "off",
counter_comb_bita_1.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_comb counter_comb_bita_2
(
.cin(wire_counter_comb_bita_1cout[0:0]),
.combout(),
.cout(wire_counter_comb_bita_2cout[0:0]),
.datad(wire_counter_reg_bit1a_regout[2:2]),
.dataf(updown_other_bits),
.shareout(),
.sumout(wire_counter_comb_bita_2sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_2.extended_lut = "off",
counter_comb_bita_2.lut_mask = 64'h0000FF000000FF00,
counter_comb_bita_2.shared_arith = "off",
counter_comb_bita_2.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_comb counter_comb_bita_3
(
.cin(wire_counter_comb_bita_2cout[0:0]),
.combout(),
.cout(wire_counter_comb_bita_3cout[0:0]),
.datad(wire_counter_reg_bit1a_regout[3:3]),
.dataf(updown_other_bits),
.shareout(),
.sumout(wire_counter_comb_bita_3sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_3.extended_lut = "off",
counter_comb_bita_3.lut_mask = 64'h0000FF000000FF00,
counter_comb_bita_3.shared_arith = "off",
counter_comb_bita_3.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_comb counter_comb_bita_4
(
.cin(wire_counter_comb_bita_3cout[0:0]),
.combout(),
.cout(),
.datad(wire_counter_reg_bit1a_regout[4:4]),
.dataf(updown_other_bits),
.shareout(),
.sumout(wire_counter_comb_bita_4sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_4.extended_lut = "off",
counter_comb_bita_4.lut_mask = 64'h0000FF000000FF00,
counter_comb_bita_4.shared_arith = "off",
counter_comb_bita_4.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_ff counter_reg_bit1a_0
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit1a_adatasdata[0:0]),
.clk(clock),
.datain(wire_counter_comb_bita_0sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit1a_regout[0:0]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixii_lcell_ff counter_reg_bit1a_1
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit1a_adatasdata[1:1]),
.clk(clock),
.datain(wire_counter_comb_bita_1sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit1a_regout[1:1]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixii_lcell_ff counter_reg_bit1a_2
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit1a_adatasdata[2:2]),
.clk(clock),
.datain(wire_counter_comb_bita_2sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit1a_regout[2:2]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixii_lcell_ff counter_reg_bit1a_3
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit1a_adatasdata[3:3]),
.clk(clock),
.datain(wire_counter_comb_bita_3sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit1a_regout[3:3]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixii_lcell_ff counter_reg_bit1a_4
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit1a_adatasdata[4:4]),
.clk(clock),
.datain(wire_counter_comb_bita_4sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit1a_regout[4:4]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
assign
wire_counter_reg_bit1a_adatasdata = (({5{sset}} & s_val) | ({5{(~ sset)}} & data));
assign
aclr_actual = aclr,
clk_en = 1'b1,
data = {5{1'b0}},
external_cin = 1'b1,
lsb_cin = 1'b0,
q = safe_q,
s_val = {5{1'b1}},
safe_q = wire_counter_reg_bit1a_regout,
sload = 1'b0,
sset = 1'b0,
updown_dir = updown,
updown_lsb = updown_dir,
updown_other_bits = ((~ external_cin) | updown_dir);
endmodule //small_fifo_test_cntr
//synthesis_resources = lut 5 reg 7
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module small_fifo_test_a_fefifo
(
aclr,
clock,
empty,
full,
rreq,
sclr,
usedw_out,
wreq) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
output empty;
output full;
input rreq;
input sclr;
output [4:0] usedw_out;
input wreq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri0 rreq;
tri0 sclr;
tri0 wreq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg b_full;
reg b_non_empty;
wire [4:0] wire_count_usedw_q;
wire [4:0] equal_af1;
wire [4:0] equal_one;
wire is_almost_empty0;
wire is_almost_empty1;
wire is_almost_empty2;
wire is_almost_empty3;
wire is_almost_empty4;
wire is_almost_full0;
wire is_almost_full1;
wire is_almost_full2;
wire is_almost_full3;
wire is_almost_full4;
wire [4:0] usedw;
wire valid_rreq;
wire valid_wreq;
// synopsys translate_off
initial
b_full = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_full <= 1'b0;
else b_full <= ((b_full & (b_full ^ (sclr | rreq))) | (((~ b_full) & b_non_empty) & ((~ sclr) & ((is_almost_full4 & wreq) & (~ rreq)))));
// synopsys translate_off
initial
b_non_empty = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) b_non_empty <= 1'b0;
else b_non_empty <= (((b_full & (b_full ^ sclr)) | (((~ b_non_empty) & wreq) & (~ sclr))) | (((~ b_full) & b_non_empty) & (((~ b_full) & b_non_empty) ^ (sclr | ((is_almost_empty4 & rreq) & (~ wreq))))));
small_fifo_test_cntr count_usedw
(
.aclr(aclr),
.clock(clock),
.cnt_en((valid_wreq ^ valid_rreq)),
.q(wire_count_usedw_q),
.sclr(sclr),
.updown(valid_wreq));
assign
empty = (~ b_non_empty),
equal_af1 = {5{1'b0}},
equal_one = {{4{1'b1}}, 1'b0},
full = b_full,
is_almost_empty0 = (usedw[0] ^ equal_one[0]),
is_almost_empty1 = ((usedw[1] ^ equal_one[1]) & is_almost_empty0),
is_almost_empty2 = ((usedw[2] ^ equal_one[2]) & is_almost_empty1),
is_almost_empty3 = ((usedw[3] ^ equal_one[3]) & is_almost_empty2),
is_almost_empty4 = ((usedw[4] ^ equal_one[4]) & is_almost_empty3),
is_almost_full0 = (usedw[0] ^ equal_af1[0]),
is_almost_full1 = ((usedw[1] ^ equal_af1[1]) & is_almost_full0),
is_almost_full2 = ((usedw[2] ^ equal_af1[2]) & is_almost_full1),
is_almost_full3 = ((usedw[3] ^ equal_af1[3]) & is_almost_full2),
is_almost_full4 = ((usedw[4] ^ equal_af1[4]) & is_almost_full3),
usedw = wire_count_usedw_q,
usedw_out = usedw,
valid_rreq = (rreq & b_non_empty),
valid_wreq = (wreq & (~ b_full));
endmodule //small_fifo_test_a_fefifo
//altdpram DEVICE_FAMILY="Stratix II" INTENDED_DEVICE_FAMILY="Stratix II" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=32 WIDTHAD=5 data inclock outclock outclocken q rdaddress wraddress wren
//VERSION_BEGIN 10.1SP1 cbx_altdpram 2011:01:19:21:13:40:SJ cbx_altsyncram 2011:01:19:21:13:40:SJ cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_lpm_mux 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_stratixiii 2011:01:19:21:13:40:SJ cbx_stratixv 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ VERSION_END
//altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_B=32 WIDTH_BYTEENA_A=4 WIDTH_BYTEENA_B=4 WIDTHAD_A=5 WIDTHAD_B=5 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
//VERSION_BEGIN 10.1SP1 cbx_altsyncram 2011:01:19:21:13:40:SJ cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_lpm_mux 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ cbx_stratixiii 2011:01:19:21:13:40:SJ cbx_stratixv 2011:01:19:21:13:40:SJ cbx_util_mgl 2011:01:19:21:13:40:SJ VERSION_END
//synthesis_resources = ram_bits (AUTO) 1024
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *)
module small_fifo_test_altsyncram
(
address_a,
address_b,
clock0,
clock1,
clocken1,
data_a,
q_b,
wren_a) /* synthesis synthesis_clearbox=1 */;
input [4:0] address_a;
input [4:0] address_b;
input clock0;
input clock1;
input clocken1;
input [31:0] data_a;
output [31:0] q_b;
input wren_a;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [4:0] address_b;
tri1 clock0;
tri1 clock1;
tri1 clocken1;
tri1 [31:0] data_a;
tri0 wren_a;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_ram_block3a_0portbdataout;
wire [0:0] wire_ram_block3a_1portbdataout;
wire [0:0] wire_ram_block3a_2portbdataout;
wire [0:0] wire_ram_block3a_3portbdataout;
wire [0:0] wire_ram_block3a_4portbdataout;
wire [0:0] wire_ram_block3a_5portbdataout;
wire [0:0] wire_ram_block3a_6portbdataout;
wire [0:0] wire_ram_block3a_7portbdataout;
wire [0:0] wire_ram_block3a_8portbdataout;
wire [0:0] wire_ram_block3a_9portbdataout;
wire [0:0] wire_ram_block3a_10portbdataout;
wire [0:0] wire_ram_block3a_11portbdataout;
wire [0:0] wire_ram_block3a_12portbdataout;
wire [0:0] wire_ram_block3a_13portbdataout;
wire [0:0] wire_ram_block3a_14portbdataout;
wire [0:0] wire_ram_block3a_15portbdataout;
wire [0:0] wire_ram_block3a_16portbdataout;
wire [0:0] wire_ram_block3a_17portbdataout;
wire [0:0] wire_ram_block3a_18portbdataout;
wire [0:0] wire_ram_block3a_19portbdataout;
wire [0:0] wire_ram_block3a_20portbdataout;
wire [0:0] wire_ram_block3a_21portbdataout;
wire [0:0] wire_ram_block3a_22portbdataout;
wire [0:0] wire_ram_block3a_23portbdataout;
wire [0:0] wire_ram_block3a_24portbdataout;
wire [0:0] wire_ram_block3a_25portbdataout;
wire [0:0] wire_ram_block3a_26portbdataout;
wire [0:0] wire_ram_block3a_27portbdataout;
wire [0:0] wire_ram_block3a_28portbdataout;
wire [0:0] wire_ram_block3a_29portbdataout;
wire [0:0] wire_ram_block3a_30portbdataout;
wire [0:0] wire_ram_block3a_31portbdataout;
wire [4:0] address_a_wire;
wire [4:0] address_b_wire;
stratixii_ram_block ram_block3a_0
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[0]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_0.connectivity_checking = "OFF",
ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
ram_block3a_0.operation_mode = "dual_port",
ram_block3a_0.port_a_address_width = 5,
ram_block3a_0.port_a_data_width = 1,
ram_block3a_0.port_a_disable_ce_on_input_registers = "off",
ram_block3a_0.port_a_first_address = 0,
ram_block3a_0.port_a_first_bit_number = 0,
ram_block3a_0.port_a_last_address = 31,
ram_block3a_0.port_a_logical_ram_depth = 32,
ram_block3a_0.port_a_logical_ram_width = 32,
ram_block3a_0.port_b_address_clock = "clock1",
ram_block3a_0.port_b_address_width = 5,
ram_block3a_0.port_b_data_out_clear = "none",
ram_block3a_0.port_b_data_out_clock = "none",
ram_block3a_0.port_b_data_width = 1,
ram_block3a_0.port_b_disable_ce_on_input_registers = "off",
ram_block3a_0.port_b_disable_ce_on_output_registers = "on",
ram_block3a_0.port_b_first_address = 0,
ram_block3a_0.port_b_first_bit_number = 0,
ram_block3a_0.port_b_last_address = 31,
ram_block3a_0.port_b_logical_ram_depth = 32,
ram_block3a_0.port_b_logical_ram_width = 32,
ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_0.ram_block_type = "AUTO",
ram_block3a_0.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_1
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[1]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_1.connectivity_checking = "OFF",
ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
ram_block3a_1.operation_mode = "dual_port",
ram_block3a_1.port_a_address_width = 5,
ram_block3a_1.port_a_data_width = 1,
ram_block3a_1.port_a_disable_ce_on_input_registers = "off",
ram_block3a_1.port_a_first_address = 0,
ram_block3a_1.port_a_first_bit_number = 1,
ram_block3a_1.port_a_last_address = 31,
ram_block3a_1.port_a_logical_ram_depth = 32,
ram_block3a_1.port_a_logical_ram_width = 32,
ram_block3a_1.port_b_address_clock = "clock1",
ram_block3a_1.port_b_address_width = 5,
ram_block3a_1.port_b_data_out_clear = "none",
ram_block3a_1.port_b_data_out_clock = "none",
ram_block3a_1.port_b_data_width = 1,
ram_block3a_1.port_b_disable_ce_on_input_registers = "off",
ram_block3a_1.port_b_disable_ce_on_output_registers = "on",
ram_block3a_1.port_b_first_address = 0,
ram_block3a_1.port_b_first_bit_number = 1,
ram_block3a_1.port_b_last_address = 31,
ram_block3a_1.port_b_logical_ram_depth = 32,
ram_block3a_1.port_b_logical_ram_width = 32,
ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_1.ram_block_type = "AUTO",
ram_block3a_1.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_2
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[2]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_2.connectivity_checking = "OFF",
ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
ram_block3a_2.operation_mode = "dual_port",
ram_block3a_2.port_a_address_width = 5,
ram_block3a_2.port_a_data_width = 1,
ram_block3a_2.port_a_disable_ce_on_input_registers = "off",
ram_block3a_2.port_a_first_address = 0,
ram_block3a_2.port_a_first_bit_number = 2,
ram_block3a_2.port_a_last_address = 31,
ram_block3a_2.port_a_logical_ram_depth = 32,
ram_block3a_2.port_a_logical_ram_width = 32,
ram_block3a_2.port_b_address_clock = "clock1",
ram_block3a_2.port_b_address_width = 5,
ram_block3a_2.port_b_data_out_clear = "none",
ram_block3a_2.port_b_data_out_clock = "none",
ram_block3a_2.port_b_data_width = 1,
ram_block3a_2.port_b_disable_ce_on_input_registers = "off",
ram_block3a_2.port_b_disable_ce_on_output_registers = "on",
ram_block3a_2.port_b_first_address = 0,
ram_block3a_2.port_b_first_bit_number = 2,
ram_block3a_2.port_b_last_address = 31,
ram_block3a_2.port_b_logical_ram_depth = 32,
ram_block3a_2.port_b_logical_ram_width = 32,
ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_2.ram_block_type = "AUTO",
ram_block3a_2.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_3
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[3]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_3.connectivity_checking = "OFF",
ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
ram_block3a_3.operation_mode = "dual_port",
ram_block3a_3.port_a_address_width = 5,
ram_block3a_3.port_a_data_width = 1,
ram_block3a_3.port_a_disable_ce_on_input_registers = "off",
ram_block3a_3.port_a_first_address = 0,
ram_block3a_3.port_a_first_bit_number = 3,
ram_block3a_3.port_a_last_address = 31,
ram_block3a_3.port_a_logical_ram_depth = 32,
ram_block3a_3.port_a_logical_ram_width = 32,
ram_block3a_3.port_b_address_clock = "clock1",
ram_block3a_3.port_b_address_width = 5,
ram_block3a_3.port_b_data_out_clear = "none",
ram_block3a_3.port_b_data_out_clock = "none",
ram_block3a_3.port_b_data_width = 1,
ram_block3a_3.port_b_disable_ce_on_input_registers = "off",
ram_block3a_3.port_b_disable_ce_on_output_registers = "on",
ram_block3a_3.port_b_first_address = 0,
ram_block3a_3.port_b_first_bit_number = 3,
ram_block3a_3.port_b_last_address = 31,
ram_block3a_3.port_b_logical_ram_depth = 32,
ram_block3a_3.port_b_logical_ram_width = 32,
ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_3.ram_block_type = "AUTO",
ram_block3a_3.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_4
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[4]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_4.connectivity_checking = "OFF",
ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
ram_block3a_4.operation_mode = "dual_port",
ram_block3a_4.port_a_address_width = 5,
ram_block3a_4.port_a_data_width = 1,
ram_block3a_4.port_a_disable_ce_on_input_registers = "off",
ram_block3a_4.port_a_first_address = 0,
ram_block3a_4.port_a_first_bit_number = 4,
ram_block3a_4.port_a_last_address = 31,
ram_block3a_4.port_a_logical_ram_depth = 32,
ram_block3a_4.port_a_logical_ram_width = 32,
ram_block3a_4.port_b_address_clock = "clock1",
ram_block3a_4.port_b_address_width = 5,
ram_block3a_4.port_b_data_out_clear = "none",
ram_block3a_4.port_b_data_out_clock = "none",
ram_block3a_4.port_b_data_width = 1,
ram_block3a_4.port_b_disable_ce_on_input_registers = "off",
ram_block3a_4.port_b_disable_ce_on_output_registers = "on",
ram_block3a_4.port_b_first_address = 0,
ram_block3a_4.port_b_first_bit_number = 4,
ram_block3a_4.port_b_last_address = 31,
ram_block3a_4.port_b_logical_ram_depth = 32,
ram_block3a_4.port_b_logical_ram_width = 32,
ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_4.ram_block_type = "AUTO",
ram_block3a_4.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_5
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[5]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_5.connectivity_checking = "OFF",
ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
ram_block3a_5.operation_mode = "dual_port",
ram_block3a_5.port_a_address_width = 5,
ram_block3a_5.port_a_data_width = 1,
ram_block3a_5.port_a_disable_ce_on_input_registers = "off",
ram_block3a_5.port_a_first_address = 0,
ram_block3a_5.port_a_first_bit_number = 5,
ram_block3a_5.port_a_last_address = 31,
ram_block3a_5.port_a_logical_ram_depth = 32,
ram_block3a_5.port_a_logical_ram_width = 32,
ram_block3a_5.port_b_address_clock = "clock1",
ram_block3a_5.port_b_address_width = 5,
ram_block3a_5.port_b_data_out_clear = "none",
ram_block3a_5.port_b_data_out_clock = "none",
ram_block3a_5.port_b_data_width = 1,
ram_block3a_5.port_b_disable_ce_on_input_registers = "off",
ram_block3a_5.port_b_disable_ce_on_output_registers = "on",
ram_block3a_5.port_b_first_address = 0,
ram_block3a_5.port_b_first_bit_number = 5,
ram_block3a_5.port_b_last_address = 31,
ram_block3a_5.port_b_logical_ram_depth = 32,
ram_block3a_5.port_b_logical_ram_width = 32,
ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_5.ram_block_type = "AUTO",
ram_block3a_5.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_6
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[6]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_6.connectivity_checking = "OFF",
ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
ram_block3a_6.operation_mode = "dual_port",
ram_block3a_6.port_a_address_width = 5,
ram_block3a_6.port_a_data_width = 1,
ram_block3a_6.port_a_disable_ce_on_input_registers = "off",
ram_block3a_6.port_a_first_address = 0,
ram_block3a_6.port_a_first_bit_number = 6,
ram_block3a_6.port_a_last_address = 31,
ram_block3a_6.port_a_logical_ram_depth = 32,
ram_block3a_6.port_a_logical_ram_width = 32,
ram_block3a_6.port_b_address_clock = "clock1",
ram_block3a_6.port_b_address_width = 5,
ram_block3a_6.port_b_data_out_clear = "none",
ram_block3a_6.port_b_data_out_clock = "none",
ram_block3a_6.port_b_data_width = 1,
ram_block3a_6.port_b_disable_ce_on_input_registers = "off",
ram_block3a_6.port_b_disable_ce_on_output_registers = "on",
ram_block3a_6.port_b_first_address = 0,
ram_block3a_6.port_b_first_bit_number = 6,
ram_block3a_6.port_b_last_address = 31,
ram_block3a_6.port_b_logical_ram_depth = 32,
ram_block3a_6.port_b_logical_ram_width = 32,
ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_6.ram_block_type = "AUTO",
ram_block3a_6.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_7
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[7]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_7.connectivity_checking = "OFF",
ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
ram_block3a_7.operation_mode = "dual_port",
ram_block3a_7.port_a_address_width = 5,
ram_block3a_7.port_a_data_width = 1,
ram_block3a_7.port_a_disable_ce_on_input_registers = "off",
ram_block3a_7.port_a_first_address = 0,
ram_block3a_7.port_a_first_bit_number = 7,
ram_block3a_7.port_a_last_address = 31,
ram_block3a_7.port_a_logical_ram_depth = 32,
ram_block3a_7.port_a_logical_ram_width = 32,
ram_block3a_7.port_b_address_clock = "clock1",
ram_block3a_7.port_b_address_width = 5,
ram_block3a_7.port_b_data_out_clear = "none",
ram_block3a_7.port_b_data_out_clock = "none",
ram_block3a_7.port_b_data_width = 1,
ram_block3a_7.port_b_disable_ce_on_input_registers = "off",
ram_block3a_7.port_b_disable_ce_on_output_registers = "on",
ram_block3a_7.port_b_first_address = 0,
ram_block3a_7.port_b_first_bit_number = 7,
ram_block3a_7.port_b_last_address = 31,
ram_block3a_7.port_b_logical_ram_depth = 32,
ram_block3a_7.port_b_logical_ram_width = 32,
ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_7.ram_block_type = "AUTO",
ram_block3a_7.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_8
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[8]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_8.connectivity_checking = "OFF",
ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
ram_block3a_8.operation_mode = "dual_port",
ram_block3a_8.port_a_address_width = 5,
ram_block3a_8.port_a_data_width = 1,
ram_block3a_8.port_a_disable_ce_on_input_registers = "off",
ram_block3a_8.port_a_first_address = 0,
ram_block3a_8.port_a_first_bit_number = 8,
ram_block3a_8.port_a_last_address = 31,
ram_block3a_8.port_a_logical_ram_depth = 32,
ram_block3a_8.port_a_logical_ram_width = 32,
ram_block3a_8.port_b_address_clock = "clock1",
ram_block3a_8.port_b_address_width = 5,
ram_block3a_8.port_b_data_out_clear = "none",
ram_block3a_8.port_b_data_out_clock = "none",
ram_block3a_8.port_b_data_width = 1,
ram_block3a_8.port_b_disable_ce_on_input_registers = "off",
ram_block3a_8.port_b_disable_ce_on_output_registers = "on",
ram_block3a_8.port_b_first_address = 0,
ram_block3a_8.port_b_first_bit_number = 8,
ram_block3a_8.port_b_last_address = 31,
ram_block3a_8.port_b_logical_ram_depth = 32,
ram_block3a_8.port_b_logical_ram_width = 32,
ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_8.ram_block_type = "AUTO",
ram_block3a_8.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_9
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[9]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_9.connectivity_checking = "OFF",
ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
ram_block3a_9.operation_mode = "dual_port",
ram_block3a_9.port_a_address_width = 5,
ram_block3a_9.port_a_data_width = 1,
ram_block3a_9.port_a_disable_ce_on_input_registers = "off",
ram_block3a_9.port_a_first_address = 0,
ram_block3a_9.port_a_first_bit_number = 9,
ram_block3a_9.port_a_last_address = 31,
ram_block3a_9.port_a_logical_ram_depth = 32,
ram_block3a_9.port_a_logical_ram_width = 32,
ram_block3a_9.port_b_address_clock = "clock1",
ram_block3a_9.port_b_address_width = 5,
ram_block3a_9.port_b_data_out_clear = "none",
ram_block3a_9.port_b_data_out_clock = "none",
ram_block3a_9.port_b_data_width = 1,
ram_block3a_9.port_b_disable_ce_on_input_registers = "off",
ram_block3a_9.port_b_disable_ce_on_output_registers = "on",
ram_block3a_9.port_b_first_address = 0,
ram_block3a_9.port_b_first_bit_number = 9,
ram_block3a_9.port_b_last_address = 31,
ram_block3a_9.port_b_logical_ram_depth = 32,
ram_block3a_9.port_b_logical_ram_width = 32,
ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_9.ram_block_type = "AUTO",
ram_block3a_9.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_10
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[10]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_10.connectivity_checking = "OFF",
ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
ram_block3a_10.operation_mode = "dual_port",
ram_block3a_10.port_a_address_width = 5,
ram_block3a_10.port_a_data_width = 1,
ram_block3a_10.port_a_disable_ce_on_input_registers = "off",
ram_block3a_10.port_a_first_address = 0,
ram_block3a_10.port_a_first_bit_number = 10,
ram_block3a_10.port_a_last_address = 31,
ram_block3a_10.port_a_logical_ram_depth = 32,
ram_block3a_10.port_a_logical_ram_width = 32,
ram_block3a_10.port_b_address_clock = "clock1",
ram_block3a_10.port_b_address_width = 5,
ram_block3a_10.port_b_data_out_clear = "none",
ram_block3a_10.port_b_data_out_clock = "none",
ram_block3a_10.port_b_data_width = 1,
ram_block3a_10.port_b_disable_ce_on_input_registers = "off",
ram_block3a_10.port_b_disable_ce_on_output_registers = "on",
ram_block3a_10.port_b_first_address = 0,
ram_block3a_10.port_b_first_bit_number = 10,
ram_block3a_10.port_b_last_address = 31,
ram_block3a_10.port_b_logical_ram_depth = 32,
ram_block3a_10.port_b_logical_ram_width = 32,
ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_10.ram_block_type = "AUTO",
ram_block3a_10.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_11
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[11]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_11.connectivity_checking = "OFF",
ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
ram_block3a_11.operation_mode = "dual_port",
ram_block3a_11.port_a_address_width = 5,
ram_block3a_11.port_a_data_width = 1,
ram_block3a_11.port_a_disable_ce_on_input_registers = "off",
ram_block3a_11.port_a_first_address = 0,
ram_block3a_11.port_a_first_bit_number = 11,
ram_block3a_11.port_a_last_address = 31,
ram_block3a_11.port_a_logical_ram_depth = 32,
ram_block3a_11.port_a_logical_ram_width = 32,
ram_block3a_11.port_b_address_clock = "clock1",
ram_block3a_11.port_b_address_width = 5,
ram_block3a_11.port_b_data_out_clear = "none",
ram_block3a_11.port_b_data_out_clock = "none",
ram_block3a_11.port_b_data_width = 1,
ram_block3a_11.port_b_disable_ce_on_input_registers = "off",
ram_block3a_11.port_b_disable_ce_on_output_registers = "on",
ram_block3a_11.port_b_first_address = 0,
ram_block3a_11.port_b_first_bit_number = 11,
ram_block3a_11.port_b_last_address = 31,
ram_block3a_11.port_b_logical_ram_depth = 32,
ram_block3a_11.port_b_logical_ram_width = 32,
ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_11.ram_block_type = "AUTO",
ram_block3a_11.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_12
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[12]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_12.connectivity_checking = "OFF",
ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
ram_block3a_12.operation_mode = "dual_port",
ram_block3a_12.port_a_address_width = 5,
ram_block3a_12.port_a_data_width = 1,
ram_block3a_12.port_a_disable_ce_on_input_registers = "off",
ram_block3a_12.port_a_first_address = 0,
ram_block3a_12.port_a_first_bit_number = 12,
ram_block3a_12.port_a_last_address = 31,
ram_block3a_12.port_a_logical_ram_depth = 32,
ram_block3a_12.port_a_logical_ram_width = 32,
ram_block3a_12.port_b_address_clock = "clock1",
ram_block3a_12.port_b_address_width = 5,
ram_block3a_12.port_b_data_out_clear = "none",
ram_block3a_12.port_b_data_out_clock = "none",
ram_block3a_12.port_b_data_width = 1,
ram_block3a_12.port_b_disable_ce_on_input_registers = "off",
ram_block3a_12.port_b_disable_ce_on_output_registers = "on",
ram_block3a_12.port_b_first_address = 0,
ram_block3a_12.port_b_first_bit_number = 12,
ram_block3a_12.port_b_last_address = 31,
ram_block3a_12.port_b_logical_ram_depth = 32,
ram_block3a_12.port_b_logical_ram_width = 32,
ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_12.ram_block_type = "AUTO",
ram_block3a_12.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_13
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[13]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_13.connectivity_checking = "OFF",
ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
ram_block3a_13.operation_mode = "dual_port",
ram_block3a_13.port_a_address_width = 5,
ram_block3a_13.port_a_data_width = 1,
ram_block3a_13.port_a_disable_ce_on_input_registers = "off",
ram_block3a_13.port_a_first_address = 0,
ram_block3a_13.port_a_first_bit_number = 13,
ram_block3a_13.port_a_last_address = 31,
ram_block3a_13.port_a_logical_ram_depth = 32,
ram_block3a_13.port_a_logical_ram_width = 32,
ram_block3a_13.port_b_address_clock = "clock1",
ram_block3a_13.port_b_address_width = 5,
ram_block3a_13.port_b_data_out_clear = "none",
ram_block3a_13.port_b_data_out_clock = "none",
ram_block3a_13.port_b_data_width = 1,
ram_block3a_13.port_b_disable_ce_on_input_registers = "off",
ram_block3a_13.port_b_disable_ce_on_output_registers = "on",
ram_block3a_13.port_b_first_address = 0,
ram_block3a_13.port_b_first_bit_number = 13,
ram_block3a_13.port_b_last_address = 31,
ram_block3a_13.port_b_logical_ram_depth = 32,
ram_block3a_13.port_b_logical_ram_width = 32,
ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_13.ram_block_type = "AUTO",
ram_block3a_13.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_14
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[14]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_14.connectivity_checking = "OFF",
ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
ram_block3a_14.operation_mode = "dual_port",
ram_block3a_14.port_a_address_width = 5,
ram_block3a_14.port_a_data_width = 1,
ram_block3a_14.port_a_disable_ce_on_input_registers = "off",
ram_block3a_14.port_a_first_address = 0,
ram_block3a_14.port_a_first_bit_number = 14,
ram_block3a_14.port_a_last_address = 31,
ram_block3a_14.port_a_logical_ram_depth = 32,
ram_block3a_14.port_a_logical_ram_width = 32,
ram_block3a_14.port_b_address_clock = "clock1",
ram_block3a_14.port_b_address_width = 5,
ram_block3a_14.port_b_data_out_clear = "none",
ram_block3a_14.port_b_data_out_clock = "none",
ram_block3a_14.port_b_data_width = 1,
ram_block3a_14.port_b_disable_ce_on_input_registers = "off",
ram_block3a_14.port_b_disable_ce_on_output_registers = "on",
ram_block3a_14.port_b_first_address = 0,
ram_block3a_14.port_b_first_bit_number = 14,
ram_block3a_14.port_b_last_address = 31,
ram_block3a_14.port_b_logical_ram_depth = 32,
ram_block3a_14.port_b_logical_ram_width = 32,
ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_14.ram_block_type = "AUTO",
ram_block3a_14.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_15
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[15]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_15.connectivity_checking = "OFF",
ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
ram_block3a_15.operation_mode = "dual_port",
ram_block3a_15.port_a_address_width = 5,
ram_block3a_15.port_a_data_width = 1,
ram_block3a_15.port_a_disable_ce_on_input_registers = "off",
ram_block3a_15.port_a_first_address = 0,
ram_block3a_15.port_a_first_bit_number = 15,
ram_block3a_15.port_a_last_address = 31,
ram_block3a_15.port_a_logical_ram_depth = 32,
ram_block3a_15.port_a_logical_ram_width = 32,
ram_block3a_15.port_b_address_clock = "clock1",
ram_block3a_15.port_b_address_width = 5,
ram_block3a_15.port_b_data_out_clear = "none",
ram_block3a_15.port_b_data_out_clock = "none",
ram_block3a_15.port_b_data_width = 1,
ram_block3a_15.port_b_disable_ce_on_input_registers = "off",
ram_block3a_15.port_b_disable_ce_on_output_registers = "on",
ram_block3a_15.port_b_first_address = 0,
ram_block3a_15.port_b_first_bit_number = 15,
ram_block3a_15.port_b_last_address = 31,
ram_block3a_15.port_b_logical_ram_depth = 32,
ram_block3a_15.port_b_logical_ram_width = 32,
ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_15.ram_block_type = "AUTO",
ram_block3a_15.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_16
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[16]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_16portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_16.connectivity_checking = "OFF",
ram_block3a_16.logical_ram_name = "ALTSYNCRAM",
ram_block3a_16.mixed_port_feed_through_mode = "dont_care",
ram_block3a_16.operation_mode = "dual_port",
ram_block3a_16.port_a_address_width = 5,
ram_block3a_16.port_a_data_width = 1,
ram_block3a_16.port_a_disable_ce_on_input_registers = "off",
ram_block3a_16.port_a_first_address = 0,
ram_block3a_16.port_a_first_bit_number = 16,
ram_block3a_16.port_a_last_address = 31,
ram_block3a_16.port_a_logical_ram_depth = 32,
ram_block3a_16.port_a_logical_ram_width = 32,
ram_block3a_16.port_b_address_clock = "clock1",
ram_block3a_16.port_b_address_width = 5,
ram_block3a_16.port_b_data_out_clear = "none",
ram_block3a_16.port_b_data_out_clock = "none",
ram_block3a_16.port_b_data_width = 1,
ram_block3a_16.port_b_disable_ce_on_input_registers = "off",
ram_block3a_16.port_b_disable_ce_on_output_registers = "on",
ram_block3a_16.port_b_first_address = 0,
ram_block3a_16.port_b_first_bit_number = 16,
ram_block3a_16.port_b_last_address = 31,
ram_block3a_16.port_b_logical_ram_depth = 32,
ram_block3a_16.port_b_logical_ram_width = 32,
ram_block3a_16.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_16.ram_block_type = "AUTO",
ram_block3a_16.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_17
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[17]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_17portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_17.connectivity_checking = "OFF",
ram_block3a_17.logical_ram_name = "ALTSYNCRAM",
ram_block3a_17.mixed_port_feed_through_mode = "dont_care",
ram_block3a_17.operation_mode = "dual_port",
ram_block3a_17.port_a_address_width = 5,
ram_block3a_17.port_a_data_width = 1,
ram_block3a_17.port_a_disable_ce_on_input_registers = "off",
ram_block3a_17.port_a_first_address = 0,
ram_block3a_17.port_a_first_bit_number = 17,
ram_block3a_17.port_a_last_address = 31,
ram_block3a_17.port_a_logical_ram_depth = 32,
ram_block3a_17.port_a_logical_ram_width = 32,
ram_block3a_17.port_b_address_clock = "clock1",
ram_block3a_17.port_b_address_width = 5,
ram_block3a_17.port_b_data_out_clear = "none",
ram_block3a_17.port_b_data_out_clock = "none",
ram_block3a_17.port_b_data_width = 1,
ram_block3a_17.port_b_disable_ce_on_input_registers = "off",
ram_block3a_17.port_b_disable_ce_on_output_registers = "on",
ram_block3a_17.port_b_first_address = 0,
ram_block3a_17.port_b_first_bit_number = 17,
ram_block3a_17.port_b_last_address = 31,
ram_block3a_17.port_b_logical_ram_depth = 32,
ram_block3a_17.port_b_logical_ram_width = 32,
ram_block3a_17.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_17.ram_block_type = "AUTO",
ram_block3a_17.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_18
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[18]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_18portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_18.connectivity_checking = "OFF",
ram_block3a_18.logical_ram_name = "ALTSYNCRAM",
ram_block3a_18.mixed_port_feed_through_mode = "dont_care",
ram_block3a_18.operation_mode = "dual_port",
ram_block3a_18.port_a_address_width = 5,
ram_block3a_18.port_a_data_width = 1,
ram_block3a_18.port_a_disable_ce_on_input_registers = "off",
ram_block3a_18.port_a_first_address = 0,
ram_block3a_18.port_a_first_bit_number = 18,
ram_block3a_18.port_a_last_address = 31,
ram_block3a_18.port_a_logical_ram_depth = 32,
ram_block3a_18.port_a_logical_ram_width = 32,
ram_block3a_18.port_b_address_clock = "clock1",
ram_block3a_18.port_b_address_width = 5,
ram_block3a_18.port_b_data_out_clear = "none",
ram_block3a_18.port_b_data_out_clock = "none",
ram_block3a_18.port_b_data_width = 1,
ram_block3a_18.port_b_disable_ce_on_input_registers = "off",
ram_block3a_18.port_b_disable_ce_on_output_registers = "on",
ram_block3a_18.port_b_first_address = 0,
ram_block3a_18.port_b_first_bit_number = 18,
ram_block3a_18.port_b_last_address = 31,
ram_block3a_18.port_b_logical_ram_depth = 32,
ram_block3a_18.port_b_logical_ram_width = 32,
ram_block3a_18.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_18.ram_block_type = "AUTO",
ram_block3a_18.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_19
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[19]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_19portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_19.connectivity_checking = "OFF",
ram_block3a_19.logical_ram_name = "ALTSYNCRAM",
ram_block3a_19.mixed_port_feed_through_mode = "dont_care",
ram_block3a_19.operation_mode = "dual_port",
ram_block3a_19.port_a_address_width = 5,
ram_block3a_19.port_a_data_width = 1,
ram_block3a_19.port_a_disable_ce_on_input_registers = "off",
ram_block3a_19.port_a_first_address = 0,
ram_block3a_19.port_a_first_bit_number = 19,
ram_block3a_19.port_a_last_address = 31,
ram_block3a_19.port_a_logical_ram_depth = 32,
ram_block3a_19.port_a_logical_ram_width = 32,
ram_block3a_19.port_b_address_clock = "clock1",
ram_block3a_19.port_b_address_width = 5,
ram_block3a_19.port_b_data_out_clear = "none",
ram_block3a_19.port_b_data_out_clock = "none",
ram_block3a_19.port_b_data_width = 1,
ram_block3a_19.port_b_disable_ce_on_input_registers = "off",
ram_block3a_19.port_b_disable_ce_on_output_registers = "on",
ram_block3a_19.port_b_first_address = 0,
ram_block3a_19.port_b_first_bit_number = 19,
ram_block3a_19.port_b_last_address = 31,
ram_block3a_19.port_b_logical_ram_depth = 32,
ram_block3a_19.port_b_logical_ram_width = 32,
ram_block3a_19.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_19.ram_block_type = "AUTO",
ram_block3a_19.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_20
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[20]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_20portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_20.connectivity_checking = "OFF",
ram_block3a_20.logical_ram_name = "ALTSYNCRAM",
ram_block3a_20.mixed_port_feed_through_mode = "dont_care",
ram_block3a_20.operation_mode = "dual_port",
ram_block3a_20.port_a_address_width = 5,
ram_block3a_20.port_a_data_width = 1,
ram_block3a_20.port_a_disable_ce_on_input_registers = "off",
ram_block3a_20.port_a_first_address = 0,
ram_block3a_20.port_a_first_bit_number = 20,
ram_block3a_20.port_a_last_address = 31,
ram_block3a_20.port_a_logical_ram_depth = 32,
ram_block3a_20.port_a_logical_ram_width = 32,
ram_block3a_20.port_b_address_clock = "clock1",
ram_block3a_20.port_b_address_width = 5,
ram_block3a_20.port_b_data_out_clear = "none",
ram_block3a_20.port_b_data_out_clock = "none",
ram_block3a_20.port_b_data_width = 1,
ram_block3a_20.port_b_disable_ce_on_input_registers = "off",
ram_block3a_20.port_b_disable_ce_on_output_registers = "on",
ram_block3a_20.port_b_first_address = 0,
ram_block3a_20.port_b_first_bit_number = 20,
ram_block3a_20.port_b_last_address = 31,
ram_block3a_20.port_b_logical_ram_depth = 32,
ram_block3a_20.port_b_logical_ram_width = 32,
ram_block3a_20.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_20.ram_block_type = "AUTO",
ram_block3a_20.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_21
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[21]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_21portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_21.connectivity_checking = "OFF",
ram_block3a_21.logical_ram_name = "ALTSYNCRAM",
ram_block3a_21.mixed_port_feed_through_mode = "dont_care",
ram_block3a_21.operation_mode = "dual_port",
ram_block3a_21.port_a_address_width = 5,
ram_block3a_21.port_a_data_width = 1,
ram_block3a_21.port_a_disable_ce_on_input_registers = "off",
ram_block3a_21.port_a_first_address = 0,
ram_block3a_21.port_a_first_bit_number = 21,
ram_block3a_21.port_a_last_address = 31,
ram_block3a_21.port_a_logical_ram_depth = 32,
ram_block3a_21.port_a_logical_ram_width = 32,
ram_block3a_21.port_b_address_clock = "clock1",
ram_block3a_21.port_b_address_width = 5,
ram_block3a_21.port_b_data_out_clear = "none",
ram_block3a_21.port_b_data_out_clock = "none",
ram_block3a_21.port_b_data_width = 1,
ram_block3a_21.port_b_disable_ce_on_input_registers = "off",
ram_block3a_21.port_b_disable_ce_on_output_registers = "on",
ram_block3a_21.port_b_first_address = 0,
ram_block3a_21.port_b_first_bit_number = 21,
ram_block3a_21.port_b_last_address = 31,
ram_block3a_21.port_b_logical_ram_depth = 32,
ram_block3a_21.port_b_logical_ram_width = 32,
ram_block3a_21.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_21.ram_block_type = "AUTO",
ram_block3a_21.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_22
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[22]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_22portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_22.connectivity_checking = "OFF",
ram_block3a_22.logical_ram_name = "ALTSYNCRAM",
ram_block3a_22.mixed_port_feed_through_mode = "dont_care",
ram_block3a_22.operation_mode = "dual_port",
ram_block3a_22.port_a_address_width = 5,
ram_block3a_22.port_a_data_width = 1,
ram_block3a_22.port_a_disable_ce_on_input_registers = "off",
ram_block3a_22.port_a_first_address = 0,
ram_block3a_22.port_a_first_bit_number = 22,
ram_block3a_22.port_a_last_address = 31,
ram_block3a_22.port_a_logical_ram_depth = 32,
ram_block3a_22.port_a_logical_ram_width = 32,
ram_block3a_22.port_b_address_clock = "clock1",
ram_block3a_22.port_b_address_width = 5,
ram_block3a_22.port_b_data_out_clear = "none",
ram_block3a_22.port_b_data_out_clock = "none",
ram_block3a_22.port_b_data_width = 1,
ram_block3a_22.port_b_disable_ce_on_input_registers = "off",
ram_block3a_22.port_b_disable_ce_on_output_registers = "on",
ram_block3a_22.port_b_first_address = 0,
ram_block3a_22.port_b_first_bit_number = 22,
ram_block3a_22.port_b_last_address = 31,
ram_block3a_22.port_b_logical_ram_depth = 32,
ram_block3a_22.port_b_logical_ram_width = 32,
ram_block3a_22.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_22.ram_block_type = "AUTO",
ram_block3a_22.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_23
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[23]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_23portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_23.connectivity_checking = "OFF",
ram_block3a_23.logical_ram_name = "ALTSYNCRAM",
ram_block3a_23.mixed_port_feed_through_mode = "dont_care",
ram_block3a_23.operation_mode = "dual_port",
ram_block3a_23.port_a_address_width = 5,
ram_block3a_23.port_a_data_width = 1,
ram_block3a_23.port_a_disable_ce_on_input_registers = "off",
ram_block3a_23.port_a_first_address = 0,
ram_block3a_23.port_a_first_bit_number = 23,
ram_block3a_23.port_a_last_address = 31,
ram_block3a_23.port_a_logical_ram_depth = 32,
ram_block3a_23.port_a_logical_ram_width = 32,
ram_block3a_23.port_b_address_clock = "clock1",
ram_block3a_23.port_b_address_width = 5,
ram_block3a_23.port_b_data_out_clear = "none",
ram_block3a_23.port_b_data_out_clock = "none",
ram_block3a_23.port_b_data_width = 1,
ram_block3a_23.port_b_disable_ce_on_input_registers = "off",
ram_block3a_23.port_b_disable_ce_on_output_registers = "on",
ram_block3a_23.port_b_first_address = 0,
ram_block3a_23.port_b_first_bit_number = 23,
ram_block3a_23.port_b_last_address = 31,
ram_block3a_23.port_b_logical_ram_depth = 32,
ram_block3a_23.port_b_logical_ram_width = 32,
ram_block3a_23.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_23.ram_block_type = "AUTO",
ram_block3a_23.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_24
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[24]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_24portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_24.connectivity_checking = "OFF",
ram_block3a_24.logical_ram_name = "ALTSYNCRAM",
ram_block3a_24.mixed_port_feed_through_mode = "dont_care",
ram_block3a_24.operation_mode = "dual_port",
ram_block3a_24.port_a_address_width = 5,
ram_block3a_24.port_a_data_width = 1,
ram_block3a_24.port_a_disable_ce_on_input_registers = "off",
ram_block3a_24.port_a_first_address = 0,
ram_block3a_24.port_a_first_bit_number = 24,
ram_block3a_24.port_a_last_address = 31,
ram_block3a_24.port_a_logical_ram_depth = 32,
ram_block3a_24.port_a_logical_ram_width = 32,
ram_block3a_24.port_b_address_clock = "clock1",
ram_block3a_24.port_b_address_width = 5,
ram_block3a_24.port_b_data_out_clear = "none",
ram_block3a_24.port_b_data_out_clock = "none",
ram_block3a_24.port_b_data_width = 1,
ram_block3a_24.port_b_disable_ce_on_input_registers = "off",
ram_block3a_24.port_b_disable_ce_on_output_registers = "on",
ram_block3a_24.port_b_first_address = 0,
ram_block3a_24.port_b_first_bit_number = 24,
ram_block3a_24.port_b_last_address = 31,
ram_block3a_24.port_b_logical_ram_depth = 32,
ram_block3a_24.port_b_logical_ram_width = 32,
ram_block3a_24.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_24.ram_block_type = "AUTO",
ram_block3a_24.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_25
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[25]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_25portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_25.connectivity_checking = "OFF",
ram_block3a_25.logical_ram_name = "ALTSYNCRAM",
ram_block3a_25.mixed_port_feed_through_mode = "dont_care",
ram_block3a_25.operation_mode = "dual_port",
ram_block3a_25.port_a_address_width = 5,
ram_block3a_25.port_a_data_width = 1,
ram_block3a_25.port_a_disable_ce_on_input_registers = "off",
ram_block3a_25.port_a_first_address = 0,
ram_block3a_25.port_a_first_bit_number = 25,
ram_block3a_25.port_a_last_address = 31,
ram_block3a_25.port_a_logical_ram_depth = 32,
ram_block3a_25.port_a_logical_ram_width = 32,
ram_block3a_25.port_b_address_clock = "clock1",
ram_block3a_25.port_b_address_width = 5,
ram_block3a_25.port_b_data_out_clear = "none",
ram_block3a_25.port_b_data_out_clock = "none",
ram_block3a_25.port_b_data_width = 1,
ram_block3a_25.port_b_disable_ce_on_input_registers = "off",
ram_block3a_25.port_b_disable_ce_on_output_registers = "on",
ram_block3a_25.port_b_first_address = 0,
ram_block3a_25.port_b_first_bit_number = 25,
ram_block3a_25.port_b_last_address = 31,
ram_block3a_25.port_b_logical_ram_depth = 32,
ram_block3a_25.port_b_logical_ram_width = 32,
ram_block3a_25.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_25.ram_block_type = "AUTO",
ram_block3a_25.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_26
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[26]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_26portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_26.connectivity_checking = "OFF",
ram_block3a_26.logical_ram_name = "ALTSYNCRAM",
ram_block3a_26.mixed_port_feed_through_mode = "dont_care",
ram_block3a_26.operation_mode = "dual_port",
ram_block3a_26.port_a_address_width = 5,
ram_block3a_26.port_a_data_width = 1,
ram_block3a_26.port_a_disable_ce_on_input_registers = "off",
ram_block3a_26.port_a_first_address = 0,
ram_block3a_26.port_a_first_bit_number = 26,
ram_block3a_26.port_a_last_address = 31,
ram_block3a_26.port_a_logical_ram_depth = 32,
ram_block3a_26.port_a_logical_ram_width = 32,
ram_block3a_26.port_b_address_clock = "clock1",
ram_block3a_26.port_b_address_width = 5,
ram_block3a_26.port_b_data_out_clear = "none",
ram_block3a_26.port_b_data_out_clock = "none",
ram_block3a_26.port_b_data_width = 1,
ram_block3a_26.port_b_disable_ce_on_input_registers = "off",
ram_block3a_26.port_b_disable_ce_on_output_registers = "on",
ram_block3a_26.port_b_first_address = 0,
ram_block3a_26.port_b_first_bit_number = 26,
ram_block3a_26.port_b_last_address = 31,
ram_block3a_26.port_b_logical_ram_depth = 32,
ram_block3a_26.port_b_logical_ram_width = 32,
ram_block3a_26.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_26.ram_block_type = "AUTO",
ram_block3a_26.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_27
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[27]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_27portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_27.connectivity_checking = "OFF",
ram_block3a_27.logical_ram_name = "ALTSYNCRAM",
ram_block3a_27.mixed_port_feed_through_mode = "dont_care",
ram_block3a_27.operation_mode = "dual_port",
ram_block3a_27.port_a_address_width = 5,
ram_block3a_27.port_a_data_width = 1,
ram_block3a_27.port_a_disable_ce_on_input_registers = "off",
ram_block3a_27.port_a_first_address = 0,
ram_block3a_27.port_a_first_bit_number = 27,
ram_block3a_27.port_a_last_address = 31,
ram_block3a_27.port_a_logical_ram_depth = 32,
ram_block3a_27.port_a_logical_ram_width = 32,
ram_block3a_27.port_b_address_clock = "clock1",
ram_block3a_27.port_b_address_width = 5,
ram_block3a_27.port_b_data_out_clear = "none",
ram_block3a_27.port_b_data_out_clock = "none",
ram_block3a_27.port_b_data_width = 1,
ram_block3a_27.port_b_disable_ce_on_input_registers = "off",
ram_block3a_27.port_b_disable_ce_on_output_registers = "on",
ram_block3a_27.port_b_first_address = 0,
ram_block3a_27.port_b_first_bit_number = 27,
ram_block3a_27.port_b_last_address = 31,
ram_block3a_27.port_b_logical_ram_depth = 32,
ram_block3a_27.port_b_logical_ram_width = 32,
ram_block3a_27.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_27.ram_block_type = "AUTO",
ram_block3a_27.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_28
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[28]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_28portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_28.connectivity_checking = "OFF",
ram_block3a_28.logical_ram_name = "ALTSYNCRAM",
ram_block3a_28.mixed_port_feed_through_mode = "dont_care",
ram_block3a_28.operation_mode = "dual_port",
ram_block3a_28.port_a_address_width = 5,
ram_block3a_28.port_a_data_width = 1,
ram_block3a_28.port_a_disable_ce_on_input_registers = "off",
ram_block3a_28.port_a_first_address = 0,
ram_block3a_28.port_a_first_bit_number = 28,
ram_block3a_28.port_a_last_address = 31,
ram_block3a_28.port_a_logical_ram_depth = 32,
ram_block3a_28.port_a_logical_ram_width = 32,
ram_block3a_28.port_b_address_clock = "clock1",
ram_block3a_28.port_b_address_width = 5,
ram_block3a_28.port_b_data_out_clear = "none",
ram_block3a_28.port_b_data_out_clock = "none",
ram_block3a_28.port_b_data_width = 1,
ram_block3a_28.port_b_disable_ce_on_input_registers = "off",
ram_block3a_28.port_b_disable_ce_on_output_registers = "on",
ram_block3a_28.port_b_first_address = 0,
ram_block3a_28.port_b_first_bit_number = 28,
ram_block3a_28.port_b_last_address = 31,
ram_block3a_28.port_b_logical_ram_depth = 32,
ram_block3a_28.port_b_logical_ram_width = 32,
ram_block3a_28.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_28.ram_block_type = "AUTO",
ram_block3a_28.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_29
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[29]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_29portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_29.connectivity_checking = "OFF",
ram_block3a_29.logical_ram_name = "ALTSYNCRAM",
ram_block3a_29.mixed_port_feed_through_mode = "dont_care",
ram_block3a_29.operation_mode = "dual_port",
ram_block3a_29.port_a_address_width = 5,
ram_block3a_29.port_a_data_width = 1,
ram_block3a_29.port_a_disable_ce_on_input_registers = "off",
ram_block3a_29.port_a_first_address = 0,
ram_block3a_29.port_a_first_bit_number = 29,
ram_block3a_29.port_a_last_address = 31,
ram_block3a_29.port_a_logical_ram_depth = 32,
ram_block3a_29.port_a_logical_ram_width = 32,
ram_block3a_29.port_b_address_clock = "clock1",
ram_block3a_29.port_b_address_width = 5,
ram_block3a_29.port_b_data_out_clear = "none",
ram_block3a_29.port_b_data_out_clock = "none",
ram_block3a_29.port_b_data_width = 1,
ram_block3a_29.port_b_disable_ce_on_input_registers = "off",
ram_block3a_29.port_b_disable_ce_on_output_registers = "on",
ram_block3a_29.port_b_first_address = 0,
ram_block3a_29.port_b_first_bit_number = 29,
ram_block3a_29.port_b_last_address = 31,
ram_block3a_29.port_b_logical_ram_depth = 32,
ram_block3a_29.port_b_logical_ram_width = 32,
ram_block3a_29.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_29.ram_block_type = "AUTO",
ram_block3a_29.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_30
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[30]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_30portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_30.connectivity_checking = "OFF",
ram_block3a_30.logical_ram_name = "ALTSYNCRAM",
ram_block3a_30.mixed_port_feed_through_mode = "dont_care",
ram_block3a_30.operation_mode = "dual_port",
ram_block3a_30.port_a_address_width = 5,
ram_block3a_30.port_a_data_width = 1,
ram_block3a_30.port_a_disable_ce_on_input_registers = "off",
ram_block3a_30.port_a_first_address = 0,
ram_block3a_30.port_a_first_bit_number = 30,
ram_block3a_30.port_a_last_address = 31,
ram_block3a_30.port_a_logical_ram_depth = 32,
ram_block3a_30.port_a_logical_ram_width = 32,
ram_block3a_30.port_b_address_clock = "clock1",
ram_block3a_30.port_b_address_width = 5,
ram_block3a_30.port_b_data_out_clear = "none",
ram_block3a_30.port_b_data_out_clock = "none",
ram_block3a_30.port_b_data_width = 1,
ram_block3a_30.port_b_disable_ce_on_input_registers = "off",
ram_block3a_30.port_b_disable_ce_on_output_registers = "on",
ram_block3a_30.port_b_first_address = 0,
ram_block3a_30.port_b_first_bit_number = 30,
ram_block3a_30.port_b_last_address = 31,
ram_block3a_30.port_b_logical_ram_depth = 32,
ram_block3a_30.port_b_logical_ram_width = 32,
ram_block3a_30.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_30.ram_block_type = "AUTO",
ram_block3a_30.lpm_type = "stratixii_ram_block";
stratixii_ram_block ram_block3a_31
(
.clk0(clock0),
.clk1(clock1),
.ena0(wren_a),
.ena1(clocken1),
.portaaddr({address_a_wire[4:0]}),
.portadatain({data_a[31]}),
.portadataout(),
.portawe(wren_a),
.portbaddr({address_b_wire[4:0]}),
.portbdataout(wire_ram_block3a_31portbdataout[0:0]),
.portbrewe(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clr0(1'b0),
.clr1(1'b0),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block3a_31.connectivity_checking = "OFF",
ram_block3a_31.logical_ram_name = "ALTSYNCRAM",
ram_block3a_31.mixed_port_feed_through_mode = "dont_care",
ram_block3a_31.operation_mode = "dual_port",
ram_block3a_31.port_a_address_width = 5,
ram_block3a_31.port_a_data_width = 1,
ram_block3a_31.port_a_disable_ce_on_input_registers = "off",
ram_block3a_31.port_a_first_address = 0,
ram_block3a_31.port_a_first_bit_number = 31,
ram_block3a_31.port_a_last_address = 31,
ram_block3a_31.port_a_logical_ram_depth = 32,
ram_block3a_31.port_a_logical_ram_width = 32,
ram_block3a_31.port_b_address_clock = "clock1",
ram_block3a_31.port_b_address_width = 5,
ram_block3a_31.port_b_data_out_clear = "none",
ram_block3a_31.port_b_data_out_clock = "none",
ram_block3a_31.port_b_data_width = 1,
ram_block3a_31.port_b_disable_ce_on_input_registers = "off",
ram_block3a_31.port_b_disable_ce_on_output_registers = "on",
ram_block3a_31.port_b_first_address = 0,
ram_block3a_31.port_b_first_bit_number = 31,
ram_block3a_31.port_b_last_address = 31,
ram_block3a_31.port_b_logical_ram_depth = 32,
ram_block3a_31.port_b_logical_ram_width = 32,
ram_block3a_31.port_b_read_enable_write_enable_clock = "clock1",
ram_block3a_31.ram_block_type = "AUTO",
ram_block3a_31.lpm_type = "stratixii_ram_block";
assign
address_a_wire = address_a,
address_b_wire = address_b,
q_b = {wire_ram_block3a_31portbdataout[0], wire_ram_block3a_30portbdataout[0], wire_ram_block3a_29portbdataout[0], wire_ram_block3a_28portbdataout[0], wire_ram_block3a_27portbdataout[0], wire_ram_block3a_26portbdataout[0], wire_ram_block3a_25portbdataout[0], wire_ram_block3a_24portbdataout[0], wire_ram_block3a_23portbdataout[0], wire_ram_block3a_22portbdataout[0], wire_ram_block3a_21portbdataout[0], wire_ram_block3a_20portbdataout[0], wire_ram_block3a_19portbdataout[0], wire_ram_block3a_18portbdataout[0], wire_ram_block3a_17portbdataout[0], wire_ram_block3a_16portbdataout[0], wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
endmodule //small_fifo_test_altsyncram
//synthesis_resources = ram_bits (AUTO) 1024
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module small_fifo_test_dpram
(
data,
inclock,
outclock,
outclocken,
q,
rdaddress,
wraddress,
wren) /* synthesis synthesis_clearbox=1 */;
input [31:0] data;
input inclock;
input outclock;
input outclocken;
output [31:0] q;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 inclock;
tri1 outclock;
tri1 outclocken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_altsyncram2_q_b;
small_fifo_test_altsyncram altsyncram2
(
.address_a(wraddress),
.address_b(rdaddress),
.clock0(inclock),
.clock1(outclock),
.clocken1(outclocken),
.data_a(data),
.q_b(wire_altsyncram2_q_b),
.wren_a(wren));
assign
q = wire_altsyncram2_q_b;
endmodule //small_fifo_test_dpram
//lpm_counter DEVICE_FAMILY="Stratix II" lpm_direction="UP" lpm_port_updown="PORT_UNUSED" lpm_width=5 aclr clock cnt_en q sclr
//VERSION_BEGIN 10.1SP1 cbx_cycloneii 2011:01:19:21:13:40:SJ cbx_lpm_add_sub 2011:01:19:21:13:40:SJ cbx_lpm_compare 2011:01:19:21:13:40:SJ cbx_lpm_counter 2011:01:19:21:13:40:SJ cbx_lpm_decode 2011:01:19:21:13:40:SJ cbx_mgl 2011:01:19:21:15:40:SJ cbx_stratix 2011:01:19:21:13:40:SJ cbx_stratixii 2011:01:19:21:13:40:SJ VERSION_END
//synthesis_resources = lut 5 reg 5
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module small_fifo_test_cntr1
(
aclr,
clock,
cnt_en,
q,
sclr) /* synthesis synthesis_clearbox=1 */;
input aclr;
input clock;
input cnt_en;
output [4:0] q;
input sclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 cnt_en;
tri0 sclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_counter_comb_bita_0cout;
wire [0:0] wire_counter_comb_bita_1cout;
wire [0:0] wire_counter_comb_bita_2cout;
wire [0:0] wire_counter_comb_bita_3cout;
wire [0:0] wire_counter_comb_bita_0sumout;
wire [0:0] wire_counter_comb_bita_1sumout;
wire [0:0] wire_counter_comb_bita_2sumout;
wire [0:0] wire_counter_comb_bita_3sumout;
wire [0:0] wire_counter_comb_bita_4sumout;
wire [4:0] wire_counter_reg_bit4a_adatasdata;
wire [4:0] wire_counter_reg_bit4a_regout;
wire aclr_actual;
wire clk_en;
wire [4:0] data;
wire external_cin;
wire lsb_cin;
wire [4:0] s_val;
wire [4:0] safe_q;
wire sload;
wire sset;
wire updown_dir;
wire updown_lsb;
wire updown_other_bits;
stratixii_lcell_comb counter_comb_bita_0
(
.cin(lsb_cin),
.combout(),
.cout(wire_counter_comb_bita_0cout[0:0]),
.datad(wire_counter_reg_bit4a_regout[0:0]),
.dataf(updown_lsb),
.shareout(),
.sumout(wire_counter_comb_bita_0sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_0.extended_lut = "off",
counter_comb_bita_0.lut_mask = 64'h000000000000FF00,
counter_comb_bita_0.shared_arith = "off",
counter_comb_bita_0.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_comb counter_comb_bita_1
(
.cin(wire_counter_comb_bita_0cout[0:0]),
.combout(),
.cout(wire_counter_comb_bita_1cout[0:0]),
.datad(wire_counter_reg_bit4a_regout[1:1]),
.dataf(updown_other_bits),
.shareout(),
.sumout(wire_counter_comb_bita_1sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_1.extended_lut = "off",
counter_comb_bita_1.lut_mask = 64'h0000FF000000FF00,
counter_comb_bita_1.shared_arith = "off",
counter_comb_bita_1.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_comb counter_comb_bita_2
(
.cin(wire_counter_comb_bita_1cout[0:0]),
.combout(),
.cout(wire_counter_comb_bita_2cout[0:0]),
.datad(wire_counter_reg_bit4a_regout[2:2]),
.dataf(updown_other_bits),
.shareout(),
.sumout(wire_counter_comb_bita_2sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_2.extended_lut = "off",
counter_comb_bita_2.lut_mask = 64'h0000FF000000FF00,
counter_comb_bita_2.shared_arith = "off",
counter_comb_bita_2.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_comb counter_comb_bita_3
(
.cin(wire_counter_comb_bita_2cout[0:0]),
.combout(),
.cout(wire_counter_comb_bita_3cout[0:0]),
.datad(wire_counter_reg_bit4a_regout[3:3]),
.dataf(updown_other_bits),
.shareout(),
.sumout(wire_counter_comb_bita_3sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_3.extended_lut = "off",
counter_comb_bita_3.lut_mask = 64'h0000FF000000FF00,
counter_comb_bita_3.shared_arith = "off",
counter_comb_bita_3.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_comb counter_comb_bita_4
(
.cin(wire_counter_comb_bita_3cout[0:0]),
.combout(),
.cout(),
.datad(wire_counter_reg_bit4a_regout[4:4]),
.dataf(updown_other_bits),
.shareout(),
.sumout(wire_counter_comb_bita_4sumout[0:0]),
.dataa(1'b0),
.datab(1'b0),
.datac(1'b0),
.datae(1'b0),
.datag(1'b0),
.sharein(1'b0)
);
defparam
counter_comb_bita_4.extended_lut = "off",
counter_comb_bita_4.lut_mask = 64'h0000FF000000FF00,
counter_comb_bita_4.shared_arith = "off",
counter_comb_bita_4.lpm_type = "stratixii_lcell_comb";
stratixii_lcell_ff counter_reg_bit4a_0
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit4a_adatasdata[0:0]),
.clk(clock),
.datain(wire_counter_comb_bita_0sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit4a_regout[0:0]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixii_lcell_ff counter_reg_bit4a_1
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit4a_adatasdata[1:1]),
.clk(clock),
.datain(wire_counter_comb_bita_1sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit4a_regout[1:1]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixii_lcell_ff counter_reg_bit4a_2
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit4a_adatasdata[2:2]),
.clk(clock),
.datain(wire_counter_comb_bita_2sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit4a_regout[2:2]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixii_lcell_ff counter_reg_bit4a_3
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit4a_adatasdata[3:3]),
.clk(clock),
.datain(wire_counter_comb_bita_3sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit4a_regout[3:3]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixii_lcell_ff counter_reg_bit4a_4
(
.aclr(aclr_actual),
.adatasdata(wire_counter_reg_bit4a_adatasdata[4:4]),
.clk(clock),
.datain(wire_counter_comb_bita_4sumout[0:0]),
.ena((clk_en & (((cnt_en | sclr) | sset) | sload))),
.regout(wire_counter_reg_bit4a_regout[4:4]),
.sclr(sclr),
.sload((sset | sload)),
.aload(1'b0)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
assign
wire_counter_reg_bit4a_adatasdata = (({5{sset}} & s_val) | ({5{(~ sset)}} & data));
assign
aclr_actual = aclr,
clk_en = 1'b1,
data = {5{1'b0}},
external_cin = 1'b1,
lsb_cin = 1'b0,
q = safe_q,
s_val = {5{1'b1}},
safe_q = wire_counter_reg_bit4a_regout,
sload = 1'b0,
sset = 1'b0,
updown_dir = 1'b1,
updown_lsb = updown_dir,
updown_other_bits = ((~ external_cin) | updown_dir);
endmodule //small_fifo_test_cntr1
//synthesis_resources = lut 15 ram_bits (AUTO) 1024 reg 17
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module small_fifo_test_a_dpfifo
(
clock,
data,
empty,
full,
q,
rreq,
sclr,
usedw,
wreq) /* synthesis synthesis_clearbox=1 */;
input clock;
input [31:0] data;
output empty;
output full;
output [31:0] q;
input rreq;
input sclr;
output [4:0] usedw;
input wreq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 sclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_fifo_state_empty;
wire wire_fifo_state_full;
wire [4:0] wire_fifo_state_usedw_out;
wire [31:0] wire_FIFOram_q;
wire [4:0] wire_rd_ptr_count_q;
wire [4:0] wire_wr_ptr_q;
wire aclr;
wire [4:0] rd_ptr;
wire valid_rreq;
wire valid_wreq;
small_fifo_test_a_fefifo fifo_state
(
.aclr(aclr),
.clock(clock),
.empty(wire_fifo_state_empty),
.full(wire_fifo_state_full),
.rreq(rreq),
.sclr(sclr),
.usedw_out(wire_fifo_state_usedw_out),
.wreq(wreq));
small_fifo_test_dpram FIFOram
(
.data(data),
.inclock(clock),
.outclock(clock),
.outclocken((valid_rreq | sclr)),
.q(wire_FIFOram_q),
.rdaddress(({5{(~ sclr)}} & rd_ptr)),
.wraddress(wire_wr_ptr_q),
.wren(valid_wreq));
small_fifo_test_cntr1 rd_ptr_count
(
.aclr(aclr),
.clock(clock),
.cnt_en(valid_rreq),
.q(wire_rd_ptr_count_q),
.sclr(sclr));
small_fifo_test_cntr1 wr_ptr
(
.aclr(aclr),
.clock(clock),
.cnt_en(valid_wreq),
.q(wire_wr_ptr_q),
.sclr(sclr));
assign
aclr = 1'b0,
empty = wire_fifo_state_empty,
full = wire_fifo_state_full,
q = wire_FIFOram_q,
rd_ptr = wire_rd_ptr_count_q,
usedw = wire_fifo_state_usedw_out,
valid_rreq = (rreq & (~ wire_fifo_state_empty)),
valid_wreq = (wreq & (~ wire_fifo_state_full));
endmodule //small_fifo_test_a_dpfifo
//synthesis_resources = lut 15 ram_bits (AUTO) 1024 reg 17
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module small_fifo_test_scfifo
(
clock,
data,
empty,
full,
q,
rdreq,
sclr,
usedw,
wrreq) /* synthesis synthesis_clearbox=1 */;
input clock;
input [31:0] data;
output empty;
output full;
output [31:0] q;
input rdreq;
input sclr;
output [4:0] usedw;
input wrreq;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 sclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_dpfifo_empty;
wire wire_dpfifo_full;
wire [31:0] wire_dpfifo_q;
wire [4:0] wire_dpfifo_usedw;
small_fifo_test_a_dpfifo dpfifo
(
.clock(clock),
.data(data),
.empty(wire_dpfifo_empty),
.full(wire_dpfifo_full),
.q(wire_dpfifo_q),
.rreq(rdreq),
.sclr(sclr),
.usedw(wire_dpfifo_usedw),
.wreq(wrreq));
assign
empty = wire_dpfifo_empty,
full = wire_dpfifo_full,
q = wire_dpfifo_q,
usedw = wire_dpfifo_usedw;
endmodule //small_fifo_test_scfifo
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module small_fifo_test (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw)/* synthesis synthesis_clearbox = 1 */;
input clock;
input [31:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [31:0] q;
output [4:0] usedw;
wire [4:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] sub_wire3;
wire [4:0] usedw = sub_wire0[4:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [31:0] q = sub_wire3[31:0];
small_fifo_test_scfifo small_fifo_test_scfifo_component (
.clock (clock),
.sclr (sclr),
.wrreq (wrreq),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: usedw 0 0 5 0 OUTPUT NODEFVAL "usedw[4..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: usedw 0 0 5 0 @usedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL small_fifo_test_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_jesd_align_2 (
// jesd interface
rx_clk,
rx_sof,
rx_eof,
rx_ferr,
rx_fdata,
// aligned data
rx_err,
rx_data);
// jesd interface
input rx_clk;
input [ 3:0] rx_sof;
input [ 3:0] rx_eof;
input [ 3:0] rx_ferr;
input [31:0] rx_fdata;
// aligned data
output rx_err;
output [31:0] rx_data;
reg [ 7:0] rx_fdata_d = 'd0;
reg rx_err = 'd0;
reg [31:0] rx_data = 'd0;
wire [ 3:0] rx_eof_s;
wire rx_err_s;
// error conditions- sof & eof are mutually exclusive - xor should always be 4'b1111.
// if there are frame errors - the xor will result in values other than 4'hf.
assign rx_eof_s = ~rx_eof;
assign rx_err_s = ((rx_sof == rx_eof_s) && (rx_ferr == 4'd0)) ? 1'b0 : 1'b1;
// 2 bytes per frame - so only 2 combinations
always @(posedge rx_clk) begin
rx_fdata_d <= rx_fdata[31:24];
case (rx_sof)
4'b0101: begin
rx_err <= rx_err_s;
rx_data <= rx_fdata;
end
4'b1010: begin
rx_err <= rx_err_s;
rx_data <= {rx_fdata[23:0], rx_fdata_d};
end
default: begin
rx_err <= 1'b1;
rx_data <= 32'hffff;
end
endcase
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_eq.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_eq.v
// Description : PIPE Equalization Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Equalization Module ------------------------------------------
module pcie3_7x_0_pipe_eq #
(
parameter PCIE_SIM_MODE = "FALSE",
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_RXEQ_MODE_GEN3 = 1
)
(
//---------- Input -------------------------------------
input EQ_CLK,
input EQ_RST_N,
input EQ_GEN3,
input [ 1:0] EQ_TXEQ_CONTROL,
input [ 3:0] EQ_TXEQ_PRESET,
input [ 3:0] EQ_TXEQ_PRESET_DEFAULT,
input [ 5:0] EQ_TXEQ_DEEMPH_IN,
input [ 1:0] EQ_RXEQ_CONTROL,
input [ 2:0] EQ_RXEQ_PRESET,
input [ 5:0] EQ_RXEQ_LFFS,
input [ 3:0] EQ_RXEQ_TXPRESET,
input EQ_RXEQ_USER_EN,
input [17:0] EQ_RXEQ_USER_TXCOEFF,
input EQ_RXEQ_USER_MODE,
//---------- Output ------------------------------------
output EQ_TXEQ_DEEMPH,
output [ 4:0] EQ_TXEQ_PRECURSOR,
output [ 6:0] EQ_TXEQ_MAINCURSOR,
output [ 4:0] EQ_TXEQ_POSTCURSOR,
output [17:0] EQ_TXEQ_DEEMPH_OUT,
output EQ_TXEQ_DONE,
output [ 5:0] EQ_TXEQ_FSM,
output [17:0] EQ_RXEQ_NEW_TXCOEFF,
output EQ_RXEQ_LFFS_SEL,
output EQ_RXEQ_ADAPT_DONE,
output EQ_RXEQ_DONE,
output [ 5:0] EQ_RXEQ_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] txeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] txeq_deemph_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rxeq_control_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] rxeq_preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] rxeq_lffs_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] rxeq_txpreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_en_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] rxeq_user_txcoeff_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxeq_user_mode_reg2;
//---------- Internal Signals --------------------------
reg [18:0] txeq_preset = 19'd0;
reg txeq_preset_done = 1'd0;
reg [ 1:0] txeq_txcoeff_cnt = 2'd0;
reg [ 2:0] rxeq_preset = 3'd0;
reg rxeq_preset_valid = 1'd0;
reg [ 3:0] rxeq_txpreset = 4'd0;
reg [17:0] rxeq_txcoeff = 18'd0;
reg [ 2:0] rxeq_cnt = 3'd0;
reg [ 5:0] rxeq_fs = 6'd0;
reg [ 5:0] rxeq_lf = 6'd0;
reg rxeq_new_txcoeff_req = 1'd0;
//---------- Output Registers --------------------------
reg [18:0] txeq_txcoeff = 19'd0;
reg txeq_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg [17:0] rxeq_new_txcoeff = 18'd0;
reg rxeq_lffs_sel = 1'd0;
reg rxeq_adapt_done_reg = 1'd0;
reg rxeq_adapt_done = 1'd0;
reg rxeq_done = 1'd0;
reg [ 5:0] fsm_rx = 6'd0;
//---------- RXEQ Eye Scan Module Output ---------------
wire rxeqscan_lffs_sel;
wire rxeqscan_preset_done;
wire [17:0] rxeqscan_new_txcoeff;
wire rxeqscan_new_txcoeff_done;
wire rxeqscan_adapt_done;
//---------- FSM ---------------------------------------
localparam FSM_TXEQ_IDLE = 6'b000001;
localparam FSM_TXEQ_PRESET = 6'b000010;
localparam FSM_TXEQ_TXCOEFF = 6'b000100;
localparam FSM_TXEQ_REMAP = 6'b001000;
localparam FSM_TXEQ_QUERY = 6'b010000;
localparam FSM_TXEQ_DONE = 6'b100000;
localparam FSM_RXEQ_IDLE = 6'b000001;
localparam FSM_RXEQ_PRESET = 6'b000010;
localparam FSM_RXEQ_TXCOEFF = 6'b000100;
localparam FSM_RXEQ_LF = 6'b001000;
localparam FSM_RXEQ_NEW_TXCOEFF_REQ = 6'b010000;
localparam FSM_RXEQ_DONE = 6'b100000;
//---------- TXEQ Presets Look-up Table ----------------
// TXPRECURSOR = Coefficient range between 0 and 20 units
// TXMAINCURSOR = Coefficient range between 29 and 80 units
// TXPOSTCURSOR = Coefficient range between 0 and 31 units
//------------------------------------------------------
// Actual Full Swing (FS) = 80
// Actual Low Frequency (LF) = 29
// Advertise Full Swing (FS) = 40
// Advertise Low Frequency (LF) = 15
//------------------------------------------------------
// Pre-emphasis = 20 log [80 - (2 * TXPRECURSOR)] / 80], assuming no de-emphasis
// Main-emphasis = 80 - (TXPRECURSOR + TXPOSTCURSOR)
// De-emphasis = 20 log [80 - (2 * TXPOSTCURSOR)] / 80], assuming no pre-emphasis
//------------------------------------------------------
// Note: TXMAINCURSOR calculated internally in GT
//------------------------------------------------------
localparam TXPRECURSOR_00 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_00 = 7'd60;
localparam TXPOSTCURSOR_00 = 6'd20; // -6.0 +/- 1 dB
localparam TXPRECURSOR_01 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_01 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_01 = 6'd13; // -3.5 +/- 1 dB
localparam TXPRECURSOR_02 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_02 = 7'd64;
localparam TXPOSTCURSOR_02 = 6'd16; // -4.4 +/- 1.5 dB
localparam TXPRECURSOR_03 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_03 = 7'd70;
localparam TXPOSTCURSOR_03 = 6'd10; // -2.5 +/- 1 dB
localparam TXPRECURSOR_04 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_04 = 7'd80;
localparam TXPOSTCURSOR_04 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_05 = 6'd8; // -1.9 +/- 1 dB
localparam TXMAINCURSOR_05 = 7'd72;
localparam TXPOSTCURSOR_05 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_06 = 6'd10; // -2.5 +/- 1 dB
localparam TXMAINCURSOR_06 = 7'd70;
localparam TXPOSTCURSOR_06 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_07 = 6'd8; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_07 = 7'd56;
localparam TXPOSTCURSOR_07 = 6'd16; // -6.0 +/- 1 dB
localparam TXPRECURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_08 = 7'd60;
localparam TXPOSTCURSOR_08 = 6'd10; // -3.5 +/- 1 dB
localparam TXPRECURSOR_09 = 6'd13; // -3.5 +/- 1 dB
localparam TXMAINCURSOR_09 = 7'd68; // added 1 to compensate decimal
localparam TXPOSTCURSOR_09 = 6'd0; // 0.0 dB
localparam TXPRECURSOR_10 = 6'd0; // 0.0 dB
localparam TXMAINCURSOR_10 = 7'd56; // added 1 to compensate decimal
localparam TXPOSTCURSOR_10 = 6'd25; // 9.5 +/- 1 dB, updated for coefficient rules
//---------- Input FF ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
txeq_control_reg1 <= 2'd0;
txeq_preset_reg1 <= 4'd0;
txeq_deemph_reg1 <= 6'd1;
rxeq_control_reg1 <= 2'd0;
rxeq_preset_reg1 <= 3'd0;
rxeq_lffs_reg1 <= 6'd0;
rxeq_txpreset_reg1 <= 4'd0;
rxeq_user_en_reg1 <= 1'd0;
rxeq_user_txcoeff_reg1 <= 18'd0;
rxeq_user_mode_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
txeq_control_reg2 <= 2'd0;
txeq_preset_reg2 <= 4'd0;
txeq_deemph_reg2 <= 6'd1;
rxeq_control_reg2 <= 2'd0;
rxeq_preset_reg2 <= 3'd0;
rxeq_lffs_reg2 <= 6'd0;
rxeq_txpreset_reg2 <= 4'd0;
rxeq_user_en_reg2 <= 1'd0;
rxeq_user_txcoeff_reg2 <= 18'd0;
rxeq_user_mode_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= EQ_GEN3;
txeq_control_reg1 <= EQ_TXEQ_CONTROL;
txeq_preset_reg1 <= EQ_TXEQ_PRESET;
txeq_deemph_reg1 <= EQ_TXEQ_DEEMPH_IN;
rxeq_control_reg1 <= EQ_RXEQ_CONTROL;
rxeq_preset_reg1 <= EQ_RXEQ_PRESET;
rxeq_lffs_reg1 <= EQ_RXEQ_LFFS;
rxeq_txpreset_reg1 <= EQ_RXEQ_TXPRESET;
rxeq_user_en_reg1 <= EQ_RXEQ_USER_EN;
rxeq_user_txcoeff_reg1 <= EQ_RXEQ_USER_TXCOEFF;
rxeq_user_mode_reg1 <= EQ_RXEQ_USER_MODE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
txeq_control_reg2 <= txeq_control_reg1;
txeq_preset_reg2 <= txeq_preset_reg1;
txeq_deemph_reg2 <= txeq_deemph_reg1;
rxeq_control_reg2 <= rxeq_control_reg1;
rxeq_preset_reg2 <= rxeq_preset_reg1;
rxeq_lffs_reg2 <= rxeq_lffs_reg1;
rxeq_txpreset_reg2 <= rxeq_txpreset_reg1;
rxeq_user_en_reg2 <= rxeq_user_en_reg1;
rxeq_user_txcoeff_reg2 <= rxeq_user_txcoeff_reg1;
rxeq_user_mode_reg2 <= rxeq_user_mode_reg1;
end
end
//---------- TXEQ Preset -------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
//---------- Select TXEQ Preset ----------------
case (EQ_TXEQ_PRESET_DEFAULT)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd0;
end
else
begin
if (fsm_tx == FSM_TXEQ_PRESET)
begin
//---------- Select TXEQ Preset ----------------
case (txeq_preset_reg2)
4'd0 : txeq_preset <= {TXPOSTCURSOR_00, TXMAINCURSOR_00, TXPRECURSOR_00};
4'd1 : txeq_preset <= {TXPOSTCURSOR_01, TXMAINCURSOR_01, TXPRECURSOR_01};
4'd2 : txeq_preset <= {TXPOSTCURSOR_02, TXMAINCURSOR_02, TXPRECURSOR_02};
4'd3 : txeq_preset <= {TXPOSTCURSOR_03, TXMAINCURSOR_03, TXPRECURSOR_03};
4'd4 : txeq_preset <= {TXPOSTCURSOR_04, TXMAINCURSOR_04, TXPRECURSOR_04};
4'd5 : txeq_preset <= {TXPOSTCURSOR_05, TXMAINCURSOR_05, TXPRECURSOR_05};
4'd6 : txeq_preset <= {TXPOSTCURSOR_06, TXMAINCURSOR_06, TXPRECURSOR_06};
4'd7 : txeq_preset <= {TXPOSTCURSOR_07, TXMAINCURSOR_07, TXPRECURSOR_07};
4'd8 : txeq_preset <= {TXPOSTCURSOR_08, TXMAINCURSOR_08, TXPRECURSOR_08};
4'd9 : txeq_preset <= {TXPOSTCURSOR_09, TXMAINCURSOR_09, TXPRECURSOR_09};
4'd10 : txeq_preset <= {TXPOSTCURSOR_10, TXMAINCURSOR_10, TXPRECURSOR_10};
default : txeq_preset <= 19'd4;
endcase
txeq_preset_done <= 1'd1;
end
else
begin
txeq_preset <= txeq_preset;
txeq_preset_done <= 1'd0;
end
end
end
//---------- TXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ----------------------------
FSM_TXEQ_IDLE :
begin
case (txeq_control_reg2)
//---------- Idle ------------------------------
2'd0 :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Process TXEQ Preset ---------------
2'd1 :
begin
fsm_tx <= FSM_TXEQ_PRESET;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Coefficient -----------------------
2'd2 :
begin
fsm_tx <= FSM_TXEQ_TXCOEFF;
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= 2'd1;
txeq_done <= 1'd0;
end
//---------- Query -----------------------------
2'd3 :
begin
fsm_tx <= FSM_TXEQ_QUERY;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
//---------- Process TXEQ Preset -------------------
FSM_TXEQ_PRESET :
begin
fsm_tx <= (txeq_preset_done ? FSM_TXEQ_DONE : FSM_TXEQ_PRESET);
txeq_txcoeff <= txeq_preset;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Latch Link Partner TX Coefficient -----
FSM_TXEQ_TXCOEFF :
begin
fsm_tx <= ((txeq_txcoeff_cnt == 2'd2) ? FSM_TXEQ_REMAP : FSM_TXEQ_TXCOEFF);
//---------- Shift in extra bit for TXMAINCURSOR
if (txeq_txcoeff_cnt == 2'd1)
txeq_txcoeff <= {1'd0, txeq_deemph_reg2, txeq_txcoeff[18:7]};
else
txeq_txcoeff <= {txeq_deemph_reg2, txeq_txcoeff[18:6]};
txeq_txcoeff_cnt <= txeq_txcoeff_cnt + 2'd1;
txeq_done <= 1'd0;
end
//---------- Remap to GT TX Coefficient ------------
FSM_TXEQ_REMAP :
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff << 1; // Multiply by 2x
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Query TXEQ Coefficient ----------------
FSM_TXEQ_QUERY:
begin
fsm_tx <= FSM_TXEQ_DONE;
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
//---------- Done ----------------------------------
FSM_TXEQ_DONE :
begin
fsm_tx <= ((txeq_control_reg2 == 2'd0) ? FSM_TXEQ_IDLE : FSM_TXEQ_DONE);
txeq_txcoeff <= txeq_txcoeff;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_tx <= FSM_TXEQ_IDLE;
txeq_txcoeff <= 19'd0;
txeq_txcoeff_cnt <= 2'd0;
txeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ FSM ----------------------------------------------------------
always @ (posedge EQ_CLK)
begin
if (!EQ_RST_N)
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ----------------------------
FSM_RXEQ_IDLE :
begin
case (rxeq_control_reg2)
//---------- Process RXEQ Preset ---------------
2'd1 :
begin
fsm_rx <= FSM_RXEQ_PRESET;
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient --------
2'd2 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Phase2/3 Bypass (reuse logic from rxeq_control = 2 ----
2'd3 :
begin
fsm_rx <= FSM_RXEQ_TXCOEFF;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= 3'd1;
rxeq_fs <= rxeq_lffs_reg2;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Default ---------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
//---------- Process RXEQ Preset -------------------
FSM_RXEQ_PRESET :
begin
fsm_rx <= (rxeqscan_preset_done ? FSM_RXEQ_DONE : FSM_RXEQ_PRESET);
rxeq_preset <= rxeq_preset_reg2;
rxeq_preset_valid <= 1'd1;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Shift-in Link Partner TX Coefficient and Preset
FSM_RXEQ_TXCOEFF :
begin
fsm_rx <= ((rxeq_cnt == 3'd2) ? FSM_RXEQ_LF : FSM_RXEQ_TXCOEFF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset_reg2;
rxeq_txcoeff <= {txeq_deemph_reg2, rxeq_txcoeff[17:6]};
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Read Low Frequency (LF) Value ---------
FSM_RXEQ_LF :
begin
fsm_rx <= ((rxeq_cnt == 3'd7) ? FSM_RXEQ_NEW_TXCOEFF_REQ : FSM_RXEQ_LF);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= rxeq_cnt + 2'd1;
rxeq_fs <= rxeq_fs;
rxeq_lf <= ((rxeq_cnt == 3'd7) ? rxeq_lffs_reg2 : rxeq_lf);
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd1;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
//---------- Request New TX Coefficient ------------
FSM_RXEQ_NEW_TXCOEFF_REQ :
begin
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
if (rxeqscan_new_txcoeff_done)
begin
fsm_rx <= FSM_RXEQ_DONE;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeqscan_lffs_sel ? {14'd0, rxeqscan_new_txcoeff[3:0]} : rxeqscan_new_txcoeff;
rxeq_lffs_sel <= rxeqscan_lffs_sel;
rxeq_adapt_done_reg <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeqscan_adapt_done || rxeq_adapt_done_reg;
rxeq_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXEQ_NEW_TXCOEFF_REQ;
rxeq_new_txcoeff_req <= 1'd1;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
end
//---------- RXEQ Done -----------------------------
FSM_RXEQ_DONE :
begin
fsm_rx <= ((rxeq_control_reg2 == 2'd0) ? FSM_RXEQ_IDLE : FSM_RXEQ_DONE);
rxeq_preset <= rxeq_preset;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= rxeq_txpreset;
rxeq_txcoeff <= rxeq_txcoeff;
rxeq_cnt <= 3'd0;
rxeq_fs <= rxeq_fs;
rxeq_lf <= rxeq_lf;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= rxeq_new_txcoeff;
rxeq_lffs_sel <= rxeq_lffs_sel;
rxeq_adapt_done_reg <= rxeq_adapt_done_reg;
rxeq_adapt_done <= rxeq_adapt_done;
rxeq_done <= 1'd1;
end
//---------- Default State -------------------------
default :
begin
fsm_rx <= FSM_RXEQ_IDLE;
rxeq_preset <= 3'd0;
rxeq_preset_valid <= 1'd0;
rxeq_txpreset <= 4'd0;
rxeq_txcoeff <= 18'd0;
rxeq_cnt <= 3'd0;
rxeq_fs <= 6'd0;
rxeq_lf <= 6'd0;
rxeq_new_txcoeff_req <= 1'd0;
rxeq_new_txcoeff <= 18'd0;
rxeq_lffs_sel <= 1'd0;
rxeq_adapt_done_reg <= 1'd0;
rxeq_adapt_done <= 1'd0;
rxeq_done <= 1'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Module ----------------------------------------------
pcie3_7x_0_rxeq_scan #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE),
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3)
)
rxeq_scan_i
(
//---------- Input -------------------------------------
.RXEQSCAN_CLK (EQ_CLK),
.RXEQSCAN_RST_N (EQ_RST_N),
.RXEQSCAN_CONTROL (rxeq_control_reg2),
.RXEQSCAN_FS (rxeq_fs),
.RXEQSCAN_LF (rxeq_lf),
.RXEQSCAN_PRESET (rxeq_preset),
.RXEQSCAN_PRESET_VALID (rxeq_preset_valid),
.RXEQSCAN_TXPRESET (rxeq_txpreset),
.RXEQSCAN_TXCOEFF (rxeq_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_REQ (rxeq_new_txcoeff_req),
//---------- Output ------------------------------------
.RXEQSCAN_PRESET_DONE (rxeqscan_preset_done),
.RXEQSCAN_NEW_TXCOEFF (rxeqscan_new_txcoeff),
.RXEQSCAN_NEW_TXCOEFF_DONE (rxeqscan_new_txcoeff_done),
.RXEQSCAN_LFFS_SEL (rxeqscan_lffs_sel),
.RXEQSCAN_ADAPT_DONE (rxeqscan_adapt_done)
);
//---------- PIPE EQ Output ----------------------------------------------------
assign EQ_TXEQ_DEEMPH = txeq_txcoeff[0];
assign EQ_TXEQ_PRECURSOR = gen3_reg2 ? txeq_txcoeff[ 4: 0] : 5'h00;
assign EQ_TXEQ_MAINCURSOR = gen3_reg2 ? txeq_txcoeff[12: 6] : 7'h00;
assign EQ_TXEQ_POSTCURSOR = gen3_reg2 ? txeq_txcoeff[17:13] : 5'h00;
assign EQ_TXEQ_DEEMPH_OUT = {1'd0, txeq_txcoeff[18:14], txeq_txcoeff[12:7], 1'd0, txeq_txcoeff[5:1]}; // Divide by 2x
assign EQ_TXEQ_DONE = txeq_done;
assign EQ_TXEQ_FSM = fsm_tx;
assign EQ_RXEQ_NEW_TXCOEFF = rxeq_user_en_reg2 ? rxeq_user_txcoeff_reg2 : rxeq_new_txcoeff;
assign EQ_RXEQ_LFFS_SEL = rxeq_user_en_reg2 ? rxeq_user_mode_reg2 : rxeq_lffs_sel;
assign EQ_RXEQ_ADAPT_DONE = rxeq_adapt_done;
assign EQ_RXEQ_DONE = rxeq_done;
assign EQ_RXEQ_FSM = fsm_rx;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:58:39 10/16/2015
// Design Name: DFF
// Module Name: /home/steins;gate/IIIT-Delhi/ELD/Assignments/Verilog/Assignment_1/Assign1/test_DFF.v
// Project Name: Assign1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DFF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_DFF;
// Inputs
reg in_D;
reg clk;
reg reset;
// Outputs
wire out_Q;
wire out_QBar;
// Instantiate the Unit Under Test (UUT)
DFF uut (
in_D,
clk,
reset,
out_Q,
out_QBar
);
initial begin
// Initialize Inputs
in_D = 0;
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always begin
#50 in_D = ~in_D;
end
always begin
#10 clk = ~clk;
end
always begin
#251 reset = 1;
#1 reset = 0;
end
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module minimac_rxfifo(
input sys_clk,
input rx_rst,
input phy_rx_clk,
input [3:0] phy_rx_data,
input phy_dv,
input phy_rx_er,
output empty,
input ack,
output eof,
output [7:0] data,
output reg fifo_full
);
/*
* EOF = 0 frame data
* EOF = 1, data[0] = 0 frame completed without errors
* EOF = 1, data[0] = 1 frame completed with errors
*/
wire [8:0] fifo_out;
assign eof = fifo_out[8];
assign data = fifo_out[7:0];
reg fifo_eof;
reg [3:0] fifo_hi;
reg [3:0] fifo_lo;
wire [8:0] fifo_in = {fifo_eof, fifo_hi, fifo_lo};
reg fifo_we;
wire full;
minimac_asfifo_xilinx #(
.DATA_WIDTH(9),
.ADDRESS_WIDTH(7)
) fifo (
.Data_out(fifo_out),
.Empty_out(empty),
.ReadEn_in(ack),
.RClk(sys_clk),
.Data_in(fifo_in),
.Full_out(full),
.WriteEn_in(fifo_we),
.WClk(phy_rx_clk),
.Clear_in(rx_rst)
);
/* we assume f(sys_clk) > f(phy_rx_clk) */
reg fifo_full1;
always @(posedge sys_clk) begin
fifo_full1 <= full;
fifo_full <= fifo_full1;
end
reg rx_rst1;
reg rx_rst2;
always @(posedge phy_rx_clk) begin
rx_rst1 <= rx_rst;
rx_rst2 <= rx_rst1;
end
reg hi_nibble;
reg abort;
reg phy_dv_r;
always @(posedge phy_rx_clk) begin
if(rx_rst2) begin
fifo_we <= 1'b0;
fifo_eof <= 1'b0;
fifo_hi <= 4'd0;
fifo_lo <= 4'd0;
hi_nibble <= 1'b0;
abort <= 1'b0;
phy_dv_r <= 1'b0;
end else begin
fifo_eof <= 1'b0;
fifo_we <= 1'b0;
/* Transfer data */
if(~abort) begin
if(~hi_nibble) begin
fifo_lo <= phy_rx_data;
if(phy_dv)
hi_nibble <= 1'b1;
end else begin
fifo_hi <= phy_rx_data;
fifo_we <= 1'b1;
hi_nibble <= 1'b0;
end
end
/* Detect error events */
if(phy_dv & phy_rx_er) begin
fifo_eof <= 1'b1;
fifo_hi <= 4'd0;
fifo_lo <= 4'd1;
fifo_we <= 1'b1;
abort <= 1'b1;
hi_nibble <= 1'b0;
end
/* Detect end of frame */
phy_dv_r <= phy_dv;
if(phy_dv_r & ~phy_dv) begin
if(~abort) begin
fifo_eof <= 1'b1;
fifo_hi <= 4'd0;
fifo_lo <= 4'd0;
fifo_we <= 1'b1;
end
abort <= 1'b0;
hi_nibble <= 1'b0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:40:09 05/31/2016
// Design Name:
// Module Name: Contador_AD_Year
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_AD_Year(
input rst,
input [7:0]estado,
input [1:0] en,
input [7:0] Cambio,
input got_data,
input clk,
output reg [(N-1):0] Cuenta
);
parameter N = 5;
parameter X = 31;
always @(posedge clk)
if (rst)
Cuenta <= 1;
else if (en == 2'd0 && estado == 8'h7D)
begin
if (Cambio == 8'h73 && got_data)
begin
if (Cuenta == X)
Cuenta <= 1;
else
Cuenta <= Cuenta + 1'd1;
end
else if (Cambio == 8'h72 && got_data)
begin
if (Cuenta == 1)
Cuenta <= X;
else
Cuenta <= Cuenta - 1'd1;
end
else
Cuenta <= Cuenta;
end
else
Cuenta <= Cuenta;
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_auto_us_2 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_9_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export CoRN.ftc.NthDerivative.
Opaque Min Max.
Section Intervals.
(** printing realline %\ensuremath{\RR}% #(-∞,+∞)# *)
(** printing openl %\ensuremath{(\cdot,+\infty)}% #(⋅,+∞)# *)
(** printing openr %\ensuremath{(-\infty,\cdot)}% #(-∞,⋅)# *)
(** printing closel %\ensuremath{[\cdot,+\infty)}% #[⋅,+∞)# *)
(** printing closer %\ensuremath{(-\infty,\cdot]}% #(-∞,⋅]# *)
(** printing olor %\ensuremath{(\cdot,\cdot)}% #(⋅,⋅)# *)
(** printing clor %\ensuremath{[\cdot,\cdot)}% #[⋅,⋅)# *)
(** printing olcr %\ensuremath{(\cdot,\cdot]}% #(⋅,⋅]# *)
(** printing clcr %\ensuremath{[\cdot,\cdot]}% #[⋅,⋅]# *)
(**
* Generalized Intervals
At this stage we have enough material to begin generalizing our
concepts in preparation for the fundamental theorem of calculus and
the definition of the main (non-polynomial) functions of analysis.
In order to define functions via power series (or any other kind of
series) we need to formalize a notion of convergence more general than
the one we already have on compact intervals. This is necessary for
practical reasons: we want to define a single exponential function
with domain [IR], not several exponential functions defined on compact
intervals which we prove to be the same wherever their domains
overlap. In a similar way, we want to define indefinite integrals on
infinite domains and not only on compact intervals.
Unfortunately, proceeding in a way analogous to how we defined the
concept of global continuity will lead us nowhere; the concept turns
out to be to general, and the behaviour on too small domains
(typically intervals [[a,a']] where [a [=] a'] is neither
provably true nor provably false) will be unsatisfactory.
There is a special family of sets, however, where this problems can be
avoided: intervals. Intervals have some nice properties that allow us
to prove good results, namely the facts that if [a] and [b] are
elements of an interval [I] then so are [Min(a,b)] and
[Max(a,b)] (which is in general not true) and also the
compact interval [[a,b]] is included in [I]. Furthermore, all
intervals are characterized by simple, well defined predicates, and
the nonempty and proper concepts become very easy to define.
** Definitions and Basic Results
We define an inductive type of intervals with nine constructors,
corresponding to the nine basic types of intervals. The reason why so
many constructors are needed is that we do not have a notion of real
line, for many reasons which we will not discuss here. Also it seems
simple to directly define finite intervals than to define then later
as intersections of infinite intervals, as it would only mess things
up.
The compact interval which we will define here is obviously the same
that we have been working with all the way through; why, then, the
different formulation? The reason is simple: if we had worked with
intervals from the beginning we would have had case definitions at
every spot, and our lemmas and proofs would have been very awkward.
Also, it seems more natural to characterize a compact interval by two
real numbers (and a proof) than as a particular case of a more general
concept which doesn't have an intuitive interpretation. Finally, the
definitions we will make here will have the elegant consequence that
from this point on we can work with any kind of intervals in exactly
the same way.
*)
Inductive interval : Type :=
| realline : interval
| openl : IR -> interval
| openr : IR -> interval
| closel : IR -> interval
| closer : IR -> interval
| olor : IR -> IR -> interval
| olcr : IR -> IR -> interval
| clor : IR -> IR -> interval
| clcr : IR -> IR -> interval.
(**
To each interval a predicate (set) is assigned by the following map:
*)
Definition iprop (I : interval) (x : IR) : CProp :=
match I with
| realline => True
| openr b => x [<] b
| openl a => a [<] x
| closer b => x [<=] b
| closel a => a [<=] x
| olor a b => a [<] x and x [<] b
| olcr a b => a [<] x and x [<=] b
| clor a b => a [<=] x and x [<] b
| clcr a b => a [<=] x and x [<=] b
end.
(* begin hide *)
Coercion iprop : interval >-> Funclass.
(* end hide *)
(**
This map is made into a coercion, so that intervals
%\emph{%#<i>#are%}%#</i># really subsets of reals.
We now define what it means for an interval to be nonvoid, proper,
finite and compact in the obvious way.
*)
Definition nonvoid (I : interval) : CProp :=
match I with
| realline => True
| openr b => True
| openl a => True
| closer b => True
| closel a => True
| olor a b => a [<] b
| olcr a b => a [<] b
| clor a b => a [<] b
| clcr a b => a [<=] b
end.
Definition proper (I : interval) : CProp :=
match I with
| realline => True
| openr b => True
| openl a => True
| closer b => True
| closel a => True
| olor a b => a [<] b
| olcr a b => a [<] b
| clor a b => a [<] b
| clcr a b => a [<] b
end.
Definition finite (I : interval) : CProp :=
match I with
| realline => False
| openr b => False
| openl a => False
| closer b => False
| closel a => False
| olor a b => True
| olcr a b => True
| clor a b => True
| clcr a b => True
end.
Definition compact_ (I : interval) : CProp :=
match I with
| realline => False
| openr b => False
| openl a => False
| closer b => False
| closel a => False
| olor a b => False
| olcr a b => False
| clor a b => False
| clcr a b => a [<=] b
end.
(** Finite intervals have a left end and a right end. *)
Definition left_end (I : interval) : finite I -> IR.
Proof.
intro.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; rename X into H.
inversion H.
inversion H.
inversion H.
inversion H.
inversion H.
apply c.
apply c.
apply c.
apply c.
Defined.
Definition right_end (I : interval) : finite I -> IR.
Proof.
intro.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; rename X into H.
inversion H.
inversion H.
inversion H.
inversion H.
inversion H.
apply c0.
apply c0.
apply c0.
apply c0.
Defined.
(**
Some trivia: compact intervals are finite; proper intervals are nonvoid; an interval is nonvoid iff it contains some point.
*)
Lemma compact_finite : forall I : interval, compact_ I -> finite I.
intros; induction I as [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; auto.
Qed.
Lemma proper_nonvoid : forall I : interval, proper I -> nonvoid I.
Proof.
intro.
elim I; simpl in |- *; intros; auto.
apply less_leEq; auto.
Qed.
Lemma nonvoid_point : forall I : interval, nonvoid I -> {x : IR | I x}.
Proof.
intro.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try rename X into H.
exists ZeroR; auto.
exists (c[+][1]); apply less_plusOne.
exists (c[-][1]); apply shift_minus_less; apply less_plusOne.
exists c; apply leEq_reflexive.
exists c; apply leEq_reflexive.
exists (c[+] (c0[-]c) [/]TwoNZ); split.
astepl (c[+][0]); apply plus_resp_less_lft.
apply div_resp_pos.
apply pos_two.
apply shift_less_minus; astepl c; auto.
rstepr (c[+] (c0[-]c)).
apply plus_resp_less_lft.
apply pos_div_two'.
apply shift_less_minus; astepl c; auto.
exists c0; split; auto; apply leEq_reflexive.
exists c; split; auto; apply leEq_reflexive.
exists c; split; [ apply leEq_reflexive | auto ].
Qed.
Lemma nonvoid_char : forall (I : interval) (x : IR), I x -> nonvoid I.
Proof.
intro; induction I; simpl in |- *; intros x H; auto; inversion_clear H.
apply less_transitive_unfolded with x; auto.
apply less_leEq_trans with x; auto.
apply leEq_less_trans with x; auto.
apply leEq_transitive with x; auto.
Qed.
(**
For practical reasons it helps to define left end and right end of compact intervals.
*)
Definition Lend I (H : compact_ I) := left_end I (compact_finite I H).
Definition Rend I (H : compact_ I) := right_end I (compact_finite I H).
(** In a compact interval, the left end is always less than or equal
to the right end.
*)
Lemma Lend_leEq_Rend : forall I cI, Lend I cI [<=] Rend I cI.
Proof.
intro; elim I; simpl in |- *; intros; try inversion cI; auto.
Qed.
(**
Some nice characterizations of inclusion:
*)
Lemma compact_included : forall a b Hab (I : interval),
I a -> I b -> included (compact a b Hab) I.
Proof.
induction I; red in |- *; simpl in |- *; intros X X0 x X1;
try inversion_clear X; try inversion_clear X0; try inversion_clear X1.
auto.
apply less_leEq_trans with a; auto.
apply leEq_less_trans with b; auto.
apply leEq_transitive with a; auto.
apply leEq_transitive with b; auto.
split; [ apply less_leEq_trans with a | apply leEq_less_trans with b ]; auto.
split; [ apply less_leEq_trans with a | apply leEq_transitive with b ]; auto.
split; [ apply leEq_transitive with a | apply leEq_less_trans with b ]; auto.
split; [ apply leEq_transitive with a | apply leEq_transitive with b ]; auto.
Qed.
(** This lemma is almost same as [compact_included] above, except
that it gets rid of the hypothesis [Hab : a [<=] b] *)
Lemma interval_convex:
forall (a b : IR) (I : interval),
I a -> I b -> included (clcr a b) I.
Proof.
intros ? ? ? Ha Hb. unfold included. intros x Hab.
simpl in Hab. destruct Hab as [Hab Habr].
destruct I; simpl in Ha, Hb; simpl; try (split; destruct Ha, Hb);
eauto using leEq_less_trans, leEq_reflexive,
less_leEq_trans, leEq_transitive.
Qed.
(** Classically, this is a trivial consequence of [interval_convex].
However, a constructive proof seems to require a little more work*)
Lemma interval_Min:
forall {a b : IR} {I : interval},
I a -> I b -> I (Min a b).
Proof.
intros ? ? ? Ha Hb.
destruct I; simpl in Ha, Hb; simpl; try (split; destruct Ha, Hb);
eauto using leEq_less_trans, leEq_reflexive,
leEq_transitive,
Min_leEq_lft, less_Min, leEq_Min.
Qed.
Lemma interval_Max:
forall {a b : IR} {I : interval},
I a -> I b -> I (Max a b).
Proof.
intros ? ? ? Ha Hb.
destruct I; simpl in Ha, Hb; simpl; try (split; destruct Ha, Hb);
eauto using less_leEq_trans, leEq_reflexive,
leEq_transitive,
lft_leEq_Max, Max_less, Max_leEq.
Qed.
Lemma included_interval' : forall (I : interval) x y z w, I x -> I y -> I z -> I w ->
forall H, included (compact (Min x z) (Max y w) H) I.
Proof.
intros I x y z w; induction I; simpl in |- *; intros X X0 X1 X2 H; red in |- *; intros t Ht;
inversion_clear Ht; simpl in |- *; try inversion_clear X;
try inversion_clear X0; try inversion_clear X1; try inversion_clear X2; try split.
apply less_leEq_trans with (Min x z); try apply less_Min; auto.
apply leEq_less_trans with (Max y w); try apply Max_less; auto.
apply leEq_transitive with (Min x z); try apply leEq_Min; auto.
apply leEq_transitive with (Max y w); try apply Max_leEq; auto.
apply less_leEq_trans with (Min x z); try apply less_Min; auto.
apply leEq_less_trans with (Max y w); try apply Max_less; auto.
apply less_leEq_trans with (Min x z); try apply less_Min; auto.
apply leEq_transitive with (Max y w); try apply Max_leEq; auto.
apply leEq_transitive with (Min x z); try apply leEq_Min; auto.
apply leEq_less_trans with (Max y w); try apply Max_less; auto.
apply leEq_transitive with (Min x z); try apply leEq_Min; auto.
apply leEq_transitive with (Max y w); try apply Max_leEq; auto.
Qed.
Lemma included_interval : forall (I : interval) x y, I x -> I y ->
forall H, included (compact (Min x y) (Max x y) H) I.
Proof.
intros; apply included_interval'; auto.
Qed.
(**
A weirder inclusion result.
*)
Lemma included3_interval : forall (I : interval) x y z Hxyz, I x -> I y -> I z ->
included (compact (Min (Min x y) z) (Max (Max x y) z) Hxyz) I.
Proof.
intros I x y z Hxyz H H0 H1.
apply included_interval'; auto.
apply (included_interval I x y H H0 (Min_leEq_Max _ _)).
apply compact_inc_lft.
apply (included_interval I x y H H0 (Min_leEq_Max _ _)).
apply compact_inc_rht.
Qed.
(**
Finally, all intervals are characterized by well defined predicates.
*)
Lemma iprop_wd : forall I : interval, pred_wd _ I.
Proof.
induction I; unfold iprop in |- *; red in |- *; intros x y X X0;
try inversion_clear X; try inversion X0.
auto.
astepr x; auto.
astepl x; auto.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
Qed.
End Intervals.
Arguments Lend [I].
Arguments Rend [I].
Section Compact_Constructions.
Section Single_Compact_Interval.
(**
** Constructions with Compact Intervals
Several important constructions are now discussed.
We begin by defining the compact interval [[x,x]].
%\begin{convention}% Let [P:IR->CProp] be well defined, and [x:IR]
such that [P(x)] holds.
%\end{convention}%
*)
Variable P : IR -> CProp.
Hypothesis wdP : pred_wd IR P.
Variable x : IR.
Hypothesis Hx : P x.
Definition compact_single := Compact (leEq_reflexive _ x).
(**
This interval contains [x] and only (elements equal to) [x]; furthermore, for every (well-defined) [P], if $x\in P$#x∈P# then $[x,x]\subseteq P$#[x,x]⊆P#.
*)
Lemma compact_single_prop : compact_single x.
Proof.
split; apply leEq_reflexive.
Qed.
Lemma compact_single_pt : forall y : IR, compact_single y -> x [=] y.
Proof.
intros y H.
inversion_clear H; apply leEq_imp_eq; auto.
Qed.
Lemma compact_single_inc : included compact_single P.
Proof.
red in |- *; intros.
apply wdP with x.
auto.
apply compact_single_pt; auto.
Qed.
End Single_Compact_Interval.
(**
The special case of intervals is worth singling out, as one of the hypothesis becomes a theorem.
*)
Definition compact_single_iprop I := compact_single_inc _ (iprop_wd I).
(**
Now for more interesting and important results.
Let [I] be a proper interval and [x] be a point of [I]. Then there is
a proper compact interval [[a,b]] such that $x\in[a,b]\subseteq
I$#x∈[a,b]⊆I#.
*)
Section Proper_Compact_with_One_or_Two_Points.
(* begin hide *)
Let cip1' : forall c x : IR, c [<=] x -> x[-] (x[-]c) [/]TwoNZ [<=] x.
Proof.
intros.
astepr (x[-][0]).
unfold cg_minus at 1 3 in |- *; apply plus_resp_leEq_lft.
apply inv_resp_leEq; apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl c; auto.
Qed.
Let cip1'' : forall c x : IR, c [<] x -> x[-] (x[-]c) [/]TwoNZ [<] x.
Proof.
intros.
astepr (x[-][0]).
unfold cg_minus at 1 3 in |- *; apply plus_resp_less_lft.
apply inv_resp_less; apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl c; auto.
Qed.
Let cip1''' : forall c0 x : IR, x [<=] c0 -> x [<=] x[+] (c0[-]x) [/]TwoNZ.
Proof.
intros.
astepl (x[+][0]).
apply plus_resp_leEq_lft.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl x; auto.
Qed.
Let cip1'''' : forall c0 x : IR, x [<] c0 -> x [<] x[+] (c0[-]x) [/]TwoNZ.
Proof.
intros.
astepl (x[+][0]).
apply plus_resp_less_lft.
apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl x; auto.
Qed.
Let cip2 :
forall c x x0 : IR, c [<=] x -> x[-] (x[-]c) [/]TwoNZ [<=] x0 -> c [<=] x0.
Proof.
intros.
apply leEq_transitive with (c[+] (x[-]c) [/]TwoNZ).
astepl (c[+][0]); apply plus_resp_leEq_lft.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl c; auto.
eapply leEq_wdl.
apply H0.
rational.
Qed.
Let cip2' : forall c x x0 : IR, c [<] x -> x[-] (x[-]c) [/]TwoNZ [<=] x0 -> c [<] x0.
Proof.
intros c x x0 H H0.
apply less_leEq_trans with (c[+] (x[-]c) [/]TwoNZ).
astepl (c[+][0]); apply plus_resp_less_lft.
apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl c; auto.
eapply leEq_wdl.
apply H0.
rational.
Qed.
Let cip2'' :
forall c x x0 : IR, c [<=] x -> x[-] (x[-]c) [/]TwoNZ [<] x0 -> c [<] x0.
Proof.
intros c x x0 H H0.
apply leEq_less_trans with (c[+] (x[-]c) [/]TwoNZ).
astepl (c[+][0]); apply plus_resp_leEq_lft.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl c; auto.
eapply less_wdl.
apply H0.
rational.
Qed.
Let cip2''' :
forall c x x0 : IR, c [<] x -> x[-] (x[-]c) [/]TwoNZ [<] x0 -> c [<] x0.
Proof.
intros c x x0 H H0.
apply cip2'' with x.
apply less_leEq; auto.
auto.
Qed.
Let cip3 :
forall c0 x x0 : IR, x [<=] c0 -> x0 [<=] x[+] (c0[-]x) [/]TwoNZ -> x0 [<=] c0.
Proof.
intros c0 x x0 H H0.
eapply leEq_transitive.
apply H0.
rstepl (c0[-] (c0[-]x) [/]TwoNZ).
astepr (c0[-][0]); unfold cg_minus at 1 3 in |- *; apply plus_resp_leEq_lft.
apply inv_resp_leEq.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl x; auto.
Qed.
Let cip3' :
forall c0 x x0 : IR, x [<] c0 -> x0 [<=] x[+] (c0[-]x) [/]TwoNZ -> x0 [<] c0.
Proof.
intros c0 x x0 H H0.
eapply leEq_less_trans.
apply H0.
rstepl (c0[-] (c0[-]x) [/]TwoNZ).
astepr (c0[-][0]); unfold cg_minus at 1 3 in |- *; apply plus_resp_less_lft.
apply inv_resp_less.
apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl x; auto.
Qed.
Let cip3'' :
forall c0 x x0 : IR, x [<=] c0 -> x0 [<] x[+] (c0[-]x) [/]TwoNZ -> x0 [<] c0.
Proof.
intros c0 x x0 H H0.
eapply less_leEq_trans.
apply H0.
rstepl (c0[-] (c0[-]x) [/]TwoNZ).
astepr (c0[-][0]); unfold cg_minus at 1 3 in |- *; apply plus_resp_leEq_lft.
apply inv_resp_leEq.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl x; auto.
Qed.
Let cip3''' :
forall c0 x x0 : IR, x [<] c0 -> x0 [<] x[+] (c0[-]x) [/]TwoNZ -> x0 [<] c0.
Proof.
intros c0 x x0 H H0.
apply cip3'' with x; try apply less_leEq; auto.
Qed.
(* end hide *)
Definition compact_in_interval I (pI : proper I) x (Hx : I x) : interval.
Proof.
intros; destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros.
apply (clcr x (x[+][1])).
apply (clcr x (x[+][1])).
apply (clcr (x[-][1]) x).
apply (clcr x (x[+][1])).
apply (clcr (x[-][1]) x).
apply (clcr (x[-] (x[-]c) [/]TwoNZ) (x[+] (c0[-]x) [/]TwoNZ)).
apply (clcr (x[-] (x[-]c) [/]TwoNZ) (x[+] (c0[-]x) [/]TwoNZ)).
apply (clcr (x[-] (x[-]c) [/]TwoNZ) (x[+] (c0[-]x) [/]TwoNZ)).
apply (clcr c c0).
Defined.
Lemma compact_compact_in_interval : forall I pI x Hx,
compact_ (compact_in_interval I pI x Hx).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try apply ts; apply less_leEq.
apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
eapply less_transitive_unfolded; [ apply cip1'' | apply cip1'''' ]; auto.
eapply less_leEq_trans; [ apply cip1'' | apply cip1''' ]; auto.
eapply leEq_less_trans; [ apply cip1' | apply cip1'''' ]; auto.
auto.
Qed.
Lemma proper_compact_in_interval : forall I pI x Hx,
proper (compact_in_interval I pI x Hx).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx.
apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
eapply less_transitive_unfolded; [ apply cip1'' | apply cip1'''' ]; auto.
eapply less_leEq_trans; [ apply cip1'' | apply cip1''' ]; auto.
eapply leEq_less_trans; [ apply cip1' | apply cip1'''' ]; auto.
auto.
Qed.
Lemma proper_compact_in_interval' : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)), Lend H [<] Rend H.
Proof.
do 4 intro.
cut (proper (compact_in_interval I pI x Hx)).
2: apply proper_compact_in_interval.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
simpl in |- *; simpl in H; auto.
Qed.
Lemma included_compact_in_interval : forall I pI x Hx,
included (compact_in_interval I pI x Hx) I.
Proof.
induction I; simpl in |- *; intros X x X0; try inversion_clear Hx; red in |- *;
simpl in |- *; intros x0 X1; try inversion_clear X; try inversion_clear X0;
try inversion_clear X1; auto.
apply less_leEq_trans with x; auto.
apply leEq_less_trans with x; auto.
apply leEq_transitive with x; auto.
apply leEq_transitive with x; auto.
split.
apply cip2' with x; auto.
apply cip3' with x; auto.
split.
apply cip2' with x; auto.
apply cip3 with x; auto.
split.
apply cip2 with x; auto.
apply cip3' with x; auto.
Qed.
Lemma iprop_compact_in_interval : forall I pI x Hx, compact_in_interval I pI x Hx x.
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; split; auto; try apply leEq_reflexive.
apply less_leEq; apply less_plusOne.
apply less_leEq; apply less_plusOne.
apply less_leEq; apply shift_minus_less; apply less_plusOne.
apply less_leEq; apply less_plusOne.
apply less_leEq; apply shift_minus_less; apply less_plusOne.
apply less_leEq; apply cip1''; auto.
apply less_leEq; apply cip1''''; auto.
apply less_leEq; apply cip1''; auto.
apply less_leEq; apply cip1''''; auto.
Qed.
Lemma iprop_compact_in_interval' : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)) H', compact (Lend H) (Rend H) H' x.
Proof.
do 4 intro.
cut (compact_in_interval I pI x Hx x).
2: apply iprop_compact_in_interval.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
simpl in |- *; auto.
Qed.
Lemma iprop_compact_in_interval_inc1 : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)) H',
included (compact (Lend H) (Rend H) H') (compact_in_interval I pI x Hx).
Proof.
do 4 intro.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
unfold compact in |- *; simpl in |- *; Included.
Qed.
Lemma iprop_compact_in_interval_inc2 : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)) H',
included (compact_in_interval I pI x Hx) (compact (Lend H) (Rend H) H').
Proof.
do 4 intro.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
unfold compact in |- *; simpl in |- *; Included.
Qed.
(**
If [x [=] y] then the construction yields the same interval whether we
use [x] or [y] in its definition. This property is required at some
stage, which is why we formalized this result as a functional
definition rather than as an existential formula.
*)
Lemma compact_in_interval_wd1 : forall I pI x Hx y Hy
(H : compact_ (compact_in_interval I pI x Hx))
(H' : compact_ (compact_in_interval I pI y Hy)),
x [=] y -> Lend H [=] Lend H'.
Proof.
intro I; elim I; simpl in |- *; intros; algebra.
Qed.
Lemma compact_in_interval_wd2 : forall I pI x Hx y Hy
(H : compact_ (compact_in_interval I pI x Hx))
(H' : compact_ (compact_in_interval I pI y Hy)),
x [=] y -> Rend H [=] Rend H'.
Proof.
intro I; elim I; simpl in |- *; intros; algebra.
Qed.
(**
We can make an analogous construction for two points.
*)
Definition compact_in_interval2 I (pI : proper I) x y : I x -> I y -> interval.
Proof.
intros.
set (z1 := Min x y) in *.
set (z2 := Max x y) in *.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros.
apply (clcr z1 (z2[+][1])).
apply (clcr z1 (z2[+][1])).
apply (clcr (z1[-][1]) z2).
apply (clcr z1 (z2[+][1])).
apply (clcr (z1[-][1]) z2).
apply (clcr (z1[-] (z1[-]c) [/]TwoNZ) (z2[+] (c0[-]z2) [/]TwoNZ)).
apply (clcr (z1[-] (z1[-]c) [/]TwoNZ) (z2[+] (c0[-]z2) [/]TwoNZ)).
apply (clcr (z1[-] (z1[-]c) [/]TwoNZ) (z2[+] (c0[-]z2) [/]TwoNZ)).
apply (clcr c c0).
Defined.
Lemma compact_compact_in_interval2 : forall I pI x y Hx Hy,
compact_ (compact_in_interval2 I pI x y Hx Hy).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy;
try apply ts; apply less_leEq.
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
eapply less_transitive_unfolded; [ apply cip1''
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply less_Min; try apply Max_less; auto.
eapply less_leEq_trans; [ apply cip1''
| eapply leEq_transitive; [ apply Min_leEq_Max | apply cip1''' ] ];
try apply less_Min; try apply Max_leEq; auto.
eapply leEq_less_trans; [ apply cip1'
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply leEq_Min; try apply Max_less; auto.
auto.
Qed.
Lemma proper_compact_in_interval2 : forall I pI x y Hx Hy,
proper (compact_in_interval2 I pI x y Hx Hy).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy.
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
eapply less_transitive_unfolded; [ apply cip1''
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply less_Min; try apply Max_less; auto.
eapply less_leEq_trans; [ apply cip1''
| eapply leEq_transitive; [ apply Min_leEq_Max | apply cip1''' ] ];
try apply less_Min; try apply Max_leEq; auto.
eapply leEq_less_trans; [ apply cip1'
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply leEq_Min; try apply Max_less; auto.
auto.
Qed.
Lemma proper_compact_in_interval2' : forall I pI x y Hx Hy H,
Lend (I:=compact_in_interval2 I pI x y Hx Hy) H [<]
Rend (I:=compact_in_interval2 I pI x y Hx Hy) H.
Proof.
do 6 intro.
cut (proper (compact_in_interval2 I pI x y Hx Hy)).
2: apply proper_compact_in_interval2.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
simpl in |- *; simpl in H; auto.
Qed.
Lemma included_compact_in_interval2 : forall I pI x y Hx Hy,
included (compact_in_interval2 I pI x y Hx Hy) I.
Proof.
induction I; simpl in |- *; intros; try inversion_clear Hx as (H,H0);
try inversion_clear Hy as (H1,H2); red in |- *; simpl in |- *;
intros x0 X; try inversion_clear X; auto.
apply less_leEq_trans with (Min x y); try apply less_Min; auto.
apply leEq_less_trans with (Max x y); try apply Max_less; auto.
apply leEq_transitive with (Min x y); try apply leEq_Min; auto.
apply leEq_transitive with (Max x y); try apply Max_leEq; auto.
split.
apply cip2' with (Min x y); try apply less_Min; auto.
apply cip3' with (Max x y); try apply Max_less; auto.
split.
apply cip2' with (Min x y); try apply less_Min; auto.
apply cip3 with (Max x y); try apply Max_leEq; auto.
split.
apply cip2 with (Min x y); try apply leEq_Min; auto.
apply cip3' with (Max x y); try apply Max_less; auto.
Qed.
Lemma iprop_compact_in_interval2x : forall I pI x y Hx Hy,
compact_in_interval2 I pI x y Hx Hy x.
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy;
split; auto; try apply Min_leEq_lft; try apply lft_leEq_Max.
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply lft_leEq_Max | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply lft_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with x;
[ apply Min_leEq_lft | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply lft_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with x;
[ apply Min_leEq_lft | apply less_plusOne ].
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_lft ]; try apply less_Min;
auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply lft_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_lft ]; try apply less_Min;
auto.
apply leEq_transitive with (Max x y); [ apply lft_leEq_Max | apply cip1''' ];
try apply Max_leEq; auto.
eapply leEq_transitive; [ apply cip1' | apply Min_leEq_lft ]; try apply leEq_Min; auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply lft_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
Qed.
Lemma iprop_compact_in_interval2y : forall I pI x y Hx Hy,
compact_in_interval2 I pI x y Hx Hy y.
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy;
split; auto; try apply Min_leEq_rht; try apply rht_leEq_Max.
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply rht_leEq_Max | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply rht_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with y;
[ apply Min_leEq_rht | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply rht_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with y;
[ apply Min_leEq_rht | apply less_plusOne ].
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_rht ]; try apply less_Min;
auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply rht_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_rht ]; try apply less_Min;
auto.
apply leEq_transitive with (Max x y); [ apply rht_leEq_Max | apply cip1''' ];
try apply Max_leEq; auto.
eapply leEq_transitive; [ apply cip1' | apply Min_leEq_rht ]; try apply leEq_Min; auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply rht_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
Qed.
Lemma iprop_compact_in_interval2x' : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
compact (Lend H) (Rend H) H' x.
Proof.
do 6 intro.
cut (compact_in_interval2 I pI x y Hx Hy x).
2: apply iprop_compact_in_interval2x.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
simpl in |- *; auto.
Qed.
Lemma iprop_compact_in_interval2y' : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
compact (Lend H) (Rend H) H' y.
Proof.
do 6 intro.
cut (compact_in_interval2 I pI x y Hx Hy y).
2: apply iprop_compact_in_interval2y.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
simpl in |- *; auto.
Qed.
Lemma iprop_compact_in_interval2_inc1 : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
included (compact (Lend H) (Rend H) H') (compact_in_interval2 I pI x y Hx Hy).
Proof.
do 6 intro.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
unfold compact in |- *; unfold iprop in |- *; simpl in |- *; Included.
Qed.
Lemma iprop_compact_in_interval2_inc2 : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
included (compact_in_interval2 I pI x y Hx Hy) (compact (Lend H) (Rend H) H').
Proof.
do 6 intro.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
unfold compact in |- *; unfold iprop in |- *; simpl in |- *; Included.
Qed.
Lemma compact_in_interval_x_lft : forall I pI x y Hx Hy H H',
Lend (I:=compact_in_interval2 I pI x y Hx Hy) H [<=]
Lend (I:=compact_in_interval I pI x Hx) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply minus_resp_leEq;
try apply Min_leEq_lft; try apply leEq_reflexive;
(rstepl (c[+] (Min x y[-]c) [/]TwoNZ); rstepr (c[+] (x[-]c) [/]TwoNZ);
apply plus_resp_leEq_lft; apply div_resp_leEq;
[ apply pos_two | apply minus_resp_leEq; apply Min_leEq_lft ]).
Qed.
Lemma compact_in_interval_y_lft : forall I pI x y Hx Hy H H',
Lend (I:=compact_in_interval2 I pI x y Hx Hy) H [<=]
Lend (I:=compact_in_interval I pI y Hy) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply minus_resp_leEq;
try apply Min_leEq_rht; try apply leEq_reflexive;
(rstepl (c[+] (Min x y[-]c) [/]TwoNZ); rstepr (c[+] (y[-]c) [/]TwoNZ);
apply plus_resp_leEq_lft; apply div_resp_leEq;
[ apply pos_two | apply minus_resp_leEq; apply Min_leEq_rht ]).
Qed.
Lemma compact_in_interval_x_rht : forall I pI x y Hx Hy H H',
Rend (I:=compact_in_interval I pI x Hx) H [<=]
Rend (I:=compact_in_interval2 I pI x y Hx Hy) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply plus_resp_leEq;
try apply lft_leEq_Max; try apply leEq_reflexive;
(rstepl (c0[-] (c0[-]x) [/]TwoNZ); rstepr (c0[-] (c0[-]Max x y) [/]TwoNZ);
unfold cg_minus in |- *; apply plus_resp_leEq_lft; apply inv_resp_leEq; apply div_resp_leEq;
[ apply pos_two | apply plus_resp_leEq_lft; apply inv_resp_leEq; apply lft_leEq_Max ]).
Qed.
Lemma compact_in_interval_y_rht : forall I pI x y Hx Hy H H',
Rend (I:=compact_in_interval I pI y Hy) H [<=]
Rend (I:=compact_in_interval2 I pI x y Hx Hy) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply plus_resp_leEq;
try apply rht_leEq_Max; try apply leEq_reflexive;
(rstepl (c0[-] (c0[-]y) [/]TwoNZ); rstepr (c0[-] (c0[-]Max x y) [/]TwoNZ);
unfold cg_minus in |- *; apply plus_resp_leEq_lft; apply inv_resp_leEq; apply div_resp_leEq;
[ apply pos_two | apply plus_resp_leEq_lft; apply inv_resp_leEq; apply rht_leEq_Max ]).
Qed.
End Proper_Compact_with_One_or_Two_Points.
(**
Compact intervals are exactly compact intervals(!).
*)
Lemma interval_compact_inc : forall I (cI : compact_ I) H,
included I (compact (Lend cI) (Rend cI) H).
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0];intros; try inversion cI.
generalize c c0 cI H; clear H cI c0 c.
simpl in |- *; intros a b Hab Hab'.
intros x H.
simpl in H.
inversion_clear H; split; auto.
Qed.
Lemma compact_interval_inc : forall I (cI : compact_ I) H,
included (compact (Lend cI) (Rend cI) H) I.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI H; clear H cI c0 c.
simpl in |- *; intros a b Hab.
intros H x H0.
inversion_clear H0; split; auto.
Qed.
(**
A generalization of the previous results: if $[a,b]\subseteq J$#[a,b]⊆J#
and [J] is proper, then we can find a proper interval [[a',b']] such that
$[a,b]\subseteq[a',b']\subseteq J$#[a,b]⊆[a',b']⊆J#.
*)
Lemma compact_proper_in_interval : forall (J : interval) a b Hab,
included (compact a b Hab) J -> proper J -> {a' : IR | {b' : IR | {Hab' : _ |
included (compact a' b' (less_leEq _ _ _ Hab')) J |
included (Compact Hab) (Compact (less_leEq _ _ _ Hab'))}}}.
Proof.
intros J a b Hab H H0.
exists (Lend (compact_compact_in_interval2 J H0 a b (H _ (compact_inc_lft _ _ Hab))
(H _ (compact_inc_rht _ _ Hab)))).
exists (Rend (compact_compact_in_interval2 J H0 a b (H _ (compact_inc_lft _ _ Hab))
(H _ (compact_inc_rht _ _ Hab)))).
exists (proper_compact_in_interval2' _ _ _ _ _ _
(compact_compact_in_interval2 J H0 a b (H _ (compact_inc_lft _ _ Hab))
(H _ (compact_inc_rht _ _ Hab)))).
eapply included_trans.
apply compact_interval_inc.
apply included_compact_in_interval2.
apply included_compact.
apply iprop_compact_in_interval2x'.
apply iprop_compact_in_interval2y'.
Qed.
End Compact_Constructions.
Section Functions.
(**
** Properties of Functions in Intervals
We now define notions of continuity, differentiability and so on on
arbitrary intervals. As expected, a function [F] has property [P] in
the (proper) interval [I] iff it has property [P] in every compact
interval included in [I]. We can formalize this in a nice way using
previously defined concepts.
%\begin{convention}% Let [n:nat] and [I:interval].
%\end{convention}%
*)
Variable n : nat.
Variable I : interval.
Definition Continuous F := included I (Dom F) and (forall a b (Hab : a [<=] b),
included (Compact Hab) I -> Continuous_I Hab F).
Definition Derivative (pI : proper I) F G := included I (Dom F) and included I (Dom G) and (forall a b Hab,
included (Compact (less_leEq _ a b Hab)) I -> Derivative_I Hab F G).
Definition Diffble (pI : proper I) F := included I (Dom F) and (forall a b Hab,
included (Compact (less_leEq _ a b Hab)) I -> Diffble_I Hab F).
Definition Derivative_n (pI : proper I) F G := included I (Dom F) and included I (Dom G) and
(forall a b Hab, included (Compact (less_leEq _ a b Hab)) I -> Derivative_I_n Hab n F G).
Definition Diffble_n (pI : proper I) F := included I (Dom F) and (forall a b Hab,
included (Compact (less_leEq _ a b Hab)) I -> Diffble_I_n Hab n F).
End Functions.
Section Reflexivity_Properties.
(**
In the case of compact intervals, this definitions collapse to the old ones.
*)
Lemma Continuous_Int :
forall (I : interval) (cI : compact_ I) H (F : PartIR),
Continuous_I (a:=Lend cI) (b:=Rend cI) H F -> Continuous I F.
Proof.
intros I cI H F H0.
cut (included I (compact (Lend cI) (Rend cI) H)).
2: apply interval_compact_inc; auto.
cut (included (compact (Lend cI) (Rend cI) H) I).
2: apply compact_interval_inc; auto.
generalize cI H H0; clear H0 H cI.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI H H0 X X0; clear X0 X H0 H cI c0 c.
simpl in |- *; intros a b Hab Hab' contF inc1 inc2.
split.
apply included_trans with (Compact Hab'); Included.
intros.
apply included_imp_contin with (Hab := Hab'); Included.
Qed.
Lemma Int_Continuous :
forall (I : interval) (cI : compact_ I) H (F : PartIR),
Continuous I F -> Continuous_I (a:=Lend cI) (b:=Rend cI) H F.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI H F X; clear X F H cI c0 c.
simpl in |- *; intros a b Hab Hab' F contF.
inversion_clear contF.
Contin.
Qed.
Lemma Derivative_Int :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F F' : PartIR),
Derivative_I (a:=Lend cI) (b:=Rend cI) H F F' -> Derivative I pI F F'.
Proof.
do 4 intro.
cut (included I (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H))).
2: apply interval_compact_inc; auto.
cut (included (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H)) I).
2: apply compact_interval_inc; auto.
generalize cI pI H; clear H cI pI.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H X X0 F F' X1; clear X1 F' F X0 X H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' inc1 inc2 F F' derF.
split.
apply included_trans with (Compact (less_leEq _ _ _ Hab')); Included.
split.
apply included_trans with (Compact (less_leEq _ _ _ Hab')); Included.
intros c d Hcd' Hinc.
apply included_imp_deriv with (Hab := Hab'); Included.
Qed.
Lemma Int_Derivative :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F F' : PartIR),
Derivative I pI F F' -> Derivative_I (a:=Lend cI) (b:=Rend cI) H F F'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H F F' X; clear X F' F H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' F F' derF.
elim derF; intros H H0.
elim H0; intros H1 H2.
Included.
Qed.
Lemma Diffble_Int :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F : PartIR),
Diffble_I (a:=Lend cI) (b:=Rend cI) H F -> Diffble I pI F.
Proof.
do 4 intro.
cut (included I (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H))).
2: apply interval_compact_inc; auto.
cut (included (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H)) I).
2: apply compact_interval_inc; auto.
generalize cI pI H; clear H pI cI.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H X X0 F X1; clear X1 F X0 X H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' inc1 inc2 F diffF.
red in |- *; simpl in |- *.
split.
apply included_trans with (Compact (less_leEq _ _ _ Hab')); Included.
intros c d Hcd' Hinc.
apply included_imp_diffble with (Hab := Hab'); auto.
Qed.
Lemma Int_Diffble :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F : PartIR),
Diffble I pI F -> Diffble_I (a:=Lend cI) (b:=Rend cI) H F.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H F X; clear X F H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' F diffF.
inversion_clear diffF.
Included.
Qed.
End Reflexivity_Properties.
Section Lemmas.
(**
Interestingly, inclusion and equality in an interval are also characterizable in a similar way:
*)
Lemma included_imp_inc : forall (J : interval) P,
(forall a b Hab, included (compact a b Hab) J -> included (compact a b Hab) P) -> included J P.
Proof.
intros J P H x H0.
apply (H _ _ (leEq_reflexive _ _) (compact_single_iprop J x H0)).
apply compact_inc_lft.
Qed.
Lemma included_Feq'' : forall I F G, proper I -> (forall a b Hab (Hab':=(less_leEq _ a b Hab)),
included (Compact Hab') I -> Feq (Compact Hab') F G) -> Feq I F G.
Proof.
intros I F G H H0.
apply eq_imp_Feq.
intros x H1.
elim (compact_proper_in_interval I x x (leEq_reflexive _ x)); Included.
2: exact (compact_single_iprop I x H1).
intros a Ha.
elim Ha; clear Ha.
intros b Hb.
elim Hb; clear Hb.
intros Hab H2 H3.
elim (H0 _ _ _ H2); intros.
apply a0; apply H3; apply compact_single_prop.
intros x H1.
elim (compact_proper_in_interval I x x (leEq_reflexive _ x)); Included.
2: exact (compact_single_iprop I x H1).
intros a Ha.
elim Ha; clear Ha.
intros b Hb.
elim Hb; clear Hb.
intros Hab H2 H3.
elim (H0 _ _ _ H2); intros.
inversion_clear b0.
apply X; apply H3; apply compact_single_prop.
intros x H1 Hx Hx'.
elim (compact_proper_in_interval I x x (leEq_reflexive _ x)); Included.
2: exact (compact_single_iprop I x H1).
intros a Ha.
elim Ha; clear Ha.
intros b Hb.
elim Hb; clear Hb.
intros Hab H2 H3.
elim (H0 _ _ _ H2); intros.
inversion_clear b0.
apply H4; apply H3; apply compact_single_prop.
Qed.
Lemma included_Feq' : forall (I : interval) F G,
(forall a b Hab, included (compact a b Hab) I -> Feq (Compact Hab) F G) -> Feq I F G.
Proof.
intros I F G H.
apply eq_imp_Feq.
intros x H0.
elim (H x x (leEq_reflexive _ x) (compact_single_iprop I x H0)); intros.
apply a; apply compact_single_prop.
intros x H0.
elim (H x x (leEq_reflexive _ x) (compact_single_iprop I x H0)); intros.
inversion_clear b.
apply X; apply compact_single_prop.
intros x H0 Hx Hx'.
elim (H x x (leEq_reflexive _ x) (compact_single_iprop I x H0)); intros.
inversion_clear b.
apply H1; apply compact_single_prop.
Qed.
End Lemmas.
Hint Resolve included_interval included_interval' included3_interval
compact_single_inc compact_single_iprop included_compact_in_interval
iprop_compact_in_interval_inc1 iprop_compact_in_interval_inc2
included_compact_in_interval2 iprop_compact_in_interval2_inc1
iprop_compact_in_interval2_inc2 interval_compact_inc compact_interval_inc
iprop_wd: included.
|
//-----------------------------------------------------------------------------
// system_stub.v
//-----------------------------------------------------------------------------
module system_stub
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
xillybus_bus_clk,
xillybus_bus_rst_n,
xillybus_S_AXI_AWADDR,
xillybus_S_AXI_AWVALID,
xillybus_S_AXI_WDATA,
xillybus_S_AXI_WSTRB,
xillybus_S_AXI_WVALID,
xillybus_S_AXI_BREADY,
xillybus_S_AXI_ARADDR,
xillybus_S_AXI_ARVALID,
xillybus_S_AXI_RREADY,
xillybus_S_AXI_ARREADY,
xillybus_S_AXI_RDATA,
xillybus_S_AXI_RRESP,
xillybus_S_AXI_RVALID,
xillybus_S_AXI_WREADY,
xillybus_S_AXI_BRESP,
xillybus_S_AXI_BVALID,
xillybus_S_AXI_AWREADY,
xillybus_M_AXI_ARREADY,
xillybus_M_AXI_ARVALID,
xillybus_M_AXI_ARADDR,
xillybus_M_AXI_ARLEN,
xillybus_M_AXI_ARSIZE,
xillybus_M_AXI_ARBURST,
xillybus_M_AXI_ARPROT,
xillybus_M_AXI_ARCACHE,
xillybus_M_AXI_RREADY,
xillybus_M_AXI_RVALID,
xillybus_M_AXI_RDATA,
xillybus_M_AXI_RRESP,
xillybus_M_AXI_RLAST,
xillybus_M_AXI_AWREADY,
xillybus_M_AXI_AWVALID,
xillybus_M_AXI_AWADDR,
xillybus_M_AXI_AWLEN,
xillybus_M_AXI_AWSIZE,
xillybus_M_AXI_AWBURST,
xillybus_M_AXI_AWPROT,
xillybus_M_AXI_AWCACHE,
xillybus_M_AXI_WREADY,
xillybus_M_AXI_WVALID,
xillybus_M_AXI_WDATA,
xillybus_M_AXI_WSTRB,
xillybus_M_AXI_WLAST,
xillybus_M_AXI_BREADY,
xillybus_M_AXI_BVALID,
xillybus_M_AXI_BRESP,
xillybus_host_interrupt,
xillyvga_0_clk_in,
xillyvga_0_vga_hsync,
xillyvga_0_vga_vsync,
xillyvga_0_vga_de,
xillyvga_0_vga_red,
xillyvga_0_vga_green,
xillyvga_0_vga_blue,
xillyvga_0_vga_clk,
processing_system7_0_GPIO,
processing_system7_0_USB0_VBUS_PWRFAULT,
xillybus_lite_0_user_clk_pin,
xillybus_lite_0_user_wren_pin,
xillybus_lite_0_user_wstrb_pin,
xillybus_lite_0_user_rden_pin,
xillybus_lite_0_user_rd_data_pin,
xillybus_lite_0_user_wr_data_pin,
xillybus_lite_0_user_addr_pin,
xillybus_lite_0_user_irq_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB;
input processing_system7_0_PS_CLK;
input processing_system7_0_PS_PORB;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output xillybus_bus_clk;
output xillybus_bus_rst_n;
output [31:0] xillybus_S_AXI_AWADDR;
output xillybus_S_AXI_AWVALID;
output [31:0] xillybus_S_AXI_WDATA;
output [3:0] xillybus_S_AXI_WSTRB;
output xillybus_S_AXI_WVALID;
output xillybus_S_AXI_BREADY;
output [31:0] xillybus_S_AXI_ARADDR;
output xillybus_S_AXI_ARVALID;
output xillybus_S_AXI_RREADY;
input xillybus_S_AXI_ARREADY;
input [31:0] xillybus_S_AXI_RDATA;
input [1:0] xillybus_S_AXI_RRESP;
input xillybus_S_AXI_RVALID;
input xillybus_S_AXI_WREADY;
input [1:0] xillybus_S_AXI_BRESP;
input xillybus_S_AXI_BVALID;
input xillybus_S_AXI_AWREADY;
output xillybus_M_AXI_ARREADY;
input xillybus_M_AXI_ARVALID;
input [31:0] xillybus_M_AXI_ARADDR;
input [3:0] xillybus_M_AXI_ARLEN;
input [2:0] xillybus_M_AXI_ARSIZE;
input [1:0] xillybus_M_AXI_ARBURST;
input [2:0] xillybus_M_AXI_ARPROT;
input [3:0] xillybus_M_AXI_ARCACHE;
input xillybus_M_AXI_RREADY;
output xillybus_M_AXI_RVALID;
output [31:0] xillybus_M_AXI_RDATA;
output [1:0] xillybus_M_AXI_RRESP;
output xillybus_M_AXI_RLAST;
output xillybus_M_AXI_AWREADY;
input xillybus_M_AXI_AWVALID;
input [31:0] xillybus_M_AXI_AWADDR;
input [3:0] xillybus_M_AXI_AWLEN;
input [2:0] xillybus_M_AXI_AWSIZE;
input [1:0] xillybus_M_AXI_AWBURST;
input [2:0] xillybus_M_AXI_AWPROT;
input [3:0] xillybus_M_AXI_AWCACHE;
output xillybus_M_AXI_WREADY;
input xillybus_M_AXI_WVALID;
input [31:0] xillybus_M_AXI_WDATA;
input [3:0] xillybus_M_AXI_WSTRB;
input xillybus_M_AXI_WLAST;
input xillybus_M_AXI_BREADY;
output xillybus_M_AXI_BVALID;
output [1:0] xillybus_M_AXI_BRESP;
input xillybus_host_interrupt;
input xillyvga_0_clk_in;
output xillyvga_0_vga_hsync;
output xillyvga_0_vga_vsync;
output xillyvga_0_vga_de;
output [7:0] xillyvga_0_vga_red;
output [7:0] xillyvga_0_vga_green;
output [7:0] xillyvga_0_vga_blue;
output xillyvga_0_vga_clk;
inout [55:0] processing_system7_0_GPIO;
input processing_system7_0_USB0_VBUS_PWRFAULT;
output xillybus_lite_0_user_clk_pin;
output xillybus_lite_0_user_wren_pin;
output [3:0] xillybus_lite_0_user_wstrb_pin;
output xillybus_lite_0_user_rden_pin;
input [31:0] xillybus_lite_0_user_rd_data_pin;
output [31:0] xillybus_lite_0_user_wr_data_pin;
output [31:0] xillybus_lite_0_user_addr_pin;
input xillybus_lite_0_user_irq_pin;
(* BOX_TYPE = "user_black_box" *)
system
system_i (
.processing_system7_0_MIO ( processing_system7_0_MIO ),
.processing_system7_0_PS_SRSTB ( processing_system7_0_PS_SRSTB ),
.processing_system7_0_PS_CLK ( processing_system7_0_PS_CLK ),
.processing_system7_0_PS_PORB ( processing_system7_0_PS_PORB ),
.processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),
.processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),
.processing_system7_0_DDR_WEB ( processing_system7_0_DDR_WEB ),
.processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),
.processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),
.processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),
.processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),
.processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),
.xillybus_bus_clk ( xillybus_bus_clk ),
.xillybus_bus_rst_n ( xillybus_bus_rst_n ),
.xillybus_S_AXI_AWADDR ( xillybus_S_AXI_AWADDR ),
.xillybus_S_AXI_AWVALID ( xillybus_S_AXI_AWVALID ),
.xillybus_S_AXI_WDATA ( xillybus_S_AXI_WDATA ),
.xillybus_S_AXI_WSTRB ( xillybus_S_AXI_WSTRB ),
.xillybus_S_AXI_WVALID ( xillybus_S_AXI_WVALID ),
.xillybus_S_AXI_BREADY ( xillybus_S_AXI_BREADY ),
.xillybus_S_AXI_ARADDR ( xillybus_S_AXI_ARADDR ),
.xillybus_S_AXI_ARVALID ( xillybus_S_AXI_ARVALID ),
.xillybus_S_AXI_RREADY ( xillybus_S_AXI_RREADY ),
.xillybus_S_AXI_ARREADY ( xillybus_S_AXI_ARREADY ),
.xillybus_S_AXI_RDATA ( xillybus_S_AXI_RDATA ),
.xillybus_S_AXI_RRESP ( xillybus_S_AXI_RRESP ),
.xillybus_S_AXI_RVALID ( xillybus_S_AXI_RVALID ),
.xillybus_S_AXI_WREADY ( xillybus_S_AXI_WREADY ),
.xillybus_S_AXI_BRESP ( xillybus_S_AXI_BRESP ),
.xillybus_S_AXI_BVALID ( xillybus_S_AXI_BVALID ),
.xillybus_S_AXI_AWREADY ( xillybus_S_AXI_AWREADY ),
.xillybus_M_AXI_ARREADY ( xillybus_M_AXI_ARREADY ),
.xillybus_M_AXI_ARVALID ( xillybus_M_AXI_ARVALID ),
.xillybus_M_AXI_ARADDR ( xillybus_M_AXI_ARADDR ),
.xillybus_M_AXI_ARLEN ( xillybus_M_AXI_ARLEN ),
.xillybus_M_AXI_ARSIZE ( xillybus_M_AXI_ARSIZE ),
.xillybus_M_AXI_ARBURST ( xillybus_M_AXI_ARBURST ),
.xillybus_M_AXI_ARPROT ( xillybus_M_AXI_ARPROT ),
.xillybus_M_AXI_ARCACHE ( xillybus_M_AXI_ARCACHE ),
.xillybus_M_AXI_RREADY ( xillybus_M_AXI_RREADY ),
.xillybus_M_AXI_RVALID ( xillybus_M_AXI_RVALID ),
.xillybus_M_AXI_RDATA ( xillybus_M_AXI_RDATA ),
.xillybus_M_AXI_RRESP ( xillybus_M_AXI_RRESP ),
.xillybus_M_AXI_RLAST ( xillybus_M_AXI_RLAST ),
.xillybus_M_AXI_AWREADY ( xillybus_M_AXI_AWREADY ),
.xillybus_M_AXI_AWVALID ( xillybus_M_AXI_AWVALID ),
.xillybus_M_AXI_AWADDR ( xillybus_M_AXI_AWADDR ),
.xillybus_M_AXI_AWLEN ( xillybus_M_AXI_AWLEN ),
.xillybus_M_AXI_AWSIZE ( xillybus_M_AXI_AWSIZE ),
.xillybus_M_AXI_AWBURST ( xillybus_M_AXI_AWBURST ),
.xillybus_M_AXI_AWPROT ( xillybus_M_AXI_AWPROT ),
.xillybus_M_AXI_AWCACHE ( xillybus_M_AXI_AWCACHE ),
.xillybus_M_AXI_WREADY ( xillybus_M_AXI_WREADY ),
.xillybus_M_AXI_WVALID ( xillybus_M_AXI_WVALID ),
.xillybus_M_AXI_WDATA ( xillybus_M_AXI_WDATA ),
.xillybus_M_AXI_WSTRB ( xillybus_M_AXI_WSTRB ),
.xillybus_M_AXI_WLAST ( xillybus_M_AXI_WLAST ),
.xillybus_M_AXI_BREADY ( xillybus_M_AXI_BREADY ),
.xillybus_M_AXI_BVALID ( xillybus_M_AXI_BVALID ),
.xillybus_M_AXI_BRESP ( xillybus_M_AXI_BRESP ),
.xillybus_host_interrupt ( xillybus_host_interrupt ),
.xillyvga_0_clk_in ( xillyvga_0_clk_in ),
.xillyvga_0_vga_hsync ( xillyvga_0_vga_hsync ),
.xillyvga_0_vga_vsync ( xillyvga_0_vga_vsync ),
.xillyvga_0_vga_de ( xillyvga_0_vga_de ),
.xillyvga_0_vga_red ( xillyvga_0_vga_red ),
.xillyvga_0_vga_green ( xillyvga_0_vga_green ),
.xillyvga_0_vga_blue ( xillyvga_0_vga_blue ),
.xillyvga_0_vga_clk ( xillyvga_0_vga_clk ),
.processing_system7_0_GPIO ( processing_system7_0_GPIO ),
.processing_system7_0_USB0_VBUS_PWRFAULT ( processing_system7_0_USB0_VBUS_PWRFAULT ),
.xillybus_lite_0_user_clk_pin ( xillybus_lite_0_user_clk_pin ),
.xillybus_lite_0_user_wren_pin ( xillybus_lite_0_user_wren_pin ),
.xillybus_lite_0_user_wstrb_pin ( xillybus_lite_0_user_wstrb_pin ),
.xillybus_lite_0_user_rden_pin ( xillybus_lite_0_user_rden_pin ),
.xillybus_lite_0_user_rd_data_pin ( xillybus_lite_0_user_rd_data_pin ),
.xillybus_lite_0_user_wr_data_pin ( xillybus_lite_0_user_wr_data_pin ),
.xillybus_lite_0_user_addr_pin ( xillybus_lite_0_user_addr_pin ),
.xillybus_lite_0_user_irq_pin ( xillybus_lite_0_user_irq_pin )
);
endmodule
module system
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
xillybus_bus_clk,
xillybus_bus_rst_n,
xillybus_S_AXI_AWADDR,
xillybus_S_AXI_AWVALID,
xillybus_S_AXI_WDATA,
xillybus_S_AXI_WSTRB,
xillybus_S_AXI_WVALID,
xillybus_S_AXI_BREADY,
xillybus_S_AXI_ARADDR,
xillybus_S_AXI_ARVALID,
xillybus_S_AXI_RREADY,
xillybus_S_AXI_ARREADY,
xillybus_S_AXI_RDATA,
xillybus_S_AXI_RRESP,
xillybus_S_AXI_RVALID,
xillybus_S_AXI_WREADY,
xillybus_S_AXI_BRESP,
xillybus_S_AXI_BVALID,
xillybus_S_AXI_AWREADY,
xillybus_M_AXI_ARREADY,
xillybus_M_AXI_ARVALID,
xillybus_M_AXI_ARADDR,
xillybus_M_AXI_ARLEN,
xillybus_M_AXI_ARSIZE,
xillybus_M_AXI_ARBURST,
xillybus_M_AXI_ARPROT,
xillybus_M_AXI_ARCACHE,
xillybus_M_AXI_RREADY,
xillybus_M_AXI_RVALID,
xillybus_M_AXI_RDATA,
xillybus_M_AXI_RRESP,
xillybus_M_AXI_RLAST,
xillybus_M_AXI_AWREADY,
xillybus_M_AXI_AWVALID,
xillybus_M_AXI_AWADDR,
xillybus_M_AXI_AWLEN,
xillybus_M_AXI_AWSIZE,
xillybus_M_AXI_AWBURST,
xillybus_M_AXI_AWPROT,
xillybus_M_AXI_AWCACHE,
xillybus_M_AXI_WREADY,
xillybus_M_AXI_WVALID,
xillybus_M_AXI_WDATA,
xillybus_M_AXI_WSTRB,
xillybus_M_AXI_WLAST,
xillybus_M_AXI_BREADY,
xillybus_M_AXI_BVALID,
xillybus_M_AXI_BRESP,
xillybus_host_interrupt,
xillyvga_0_clk_in,
xillyvga_0_vga_hsync,
xillyvga_0_vga_vsync,
xillyvga_0_vga_de,
xillyvga_0_vga_red,
xillyvga_0_vga_green,
xillyvga_0_vga_blue,
xillyvga_0_vga_clk,
processing_system7_0_GPIO,
processing_system7_0_USB0_VBUS_PWRFAULT,
xillybus_lite_0_user_clk_pin,
xillybus_lite_0_user_wren_pin,
xillybus_lite_0_user_wstrb_pin,
xillybus_lite_0_user_rden_pin,
xillybus_lite_0_user_rd_data_pin,
xillybus_lite_0_user_wr_data_pin,
xillybus_lite_0_user_addr_pin,
xillybus_lite_0_user_irq_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB;
input processing_system7_0_PS_CLK;
input processing_system7_0_PS_PORB;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output xillybus_bus_clk;
output xillybus_bus_rst_n;
output [31:0] xillybus_S_AXI_AWADDR;
output xillybus_S_AXI_AWVALID;
output [31:0] xillybus_S_AXI_WDATA;
output [3:0] xillybus_S_AXI_WSTRB;
output xillybus_S_AXI_WVALID;
output xillybus_S_AXI_BREADY;
output [31:0] xillybus_S_AXI_ARADDR;
output xillybus_S_AXI_ARVALID;
output xillybus_S_AXI_RREADY;
input xillybus_S_AXI_ARREADY;
input [31:0] xillybus_S_AXI_RDATA;
input [1:0] xillybus_S_AXI_RRESP;
input xillybus_S_AXI_RVALID;
input xillybus_S_AXI_WREADY;
input [1:0] xillybus_S_AXI_BRESP;
input xillybus_S_AXI_BVALID;
input xillybus_S_AXI_AWREADY;
output xillybus_M_AXI_ARREADY;
input xillybus_M_AXI_ARVALID;
input [31:0] xillybus_M_AXI_ARADDR;
input [3:0] xillybus_M_AXI_ARLEN;
input [2:0] xillybus_M_AXI_ARSIZE;
input [1:0] xillybus_M_AXI_ARBURST;
input [2:0] xillybus_M_AXI_ARPROT;
input [3:0] xillybus_M_AXI_ARCACHE;
input xillybus_M_AXI_RREADY;
output xillybus_M_AXI_RVALID;
output [31:0] xillybus_M_AXI_RDATA;
output [1:0] xillybus_M_AXI_RRESP;
output xillybus_M_AXI_RLAST;
output xillybus_M_AXI_AWREADY;
input xillybus_M_AXI_AWVALID;
input [31:0] xillybus_M_AXI_AWADDR;
input [3:0] xillybus_M_AXI_AWLEN;
input [2:0] xillybus_M_AXI_AWSIZE;
input [1:0] xillybus_M_AXI_AWBURST;
input [2:0] xillybus_M_AXI_AWPROT;
input [3:0] xillybus_M_AXI_AWCACHE;
output xillybus_M_AXI_WREADY;
input xillybus_M_AXI_WVALID;
input [31:0] xillybus_M_AXI_WDATA;
input [3:0] xillybus_M_AXI_WSTRB;
input xillybus_M_AXI_WLAST;
input xillybus_M_AXI_BREADY;
output xillybus_M_AXI_BVALID;
output [1:0] xillybus_M_AXI_BRESP;
input xillybus_host_interrupt;
input xillyvga_0_clk_in;
output xillyvga_0_vga_hsync;
output xillyvga_0_vga_vsync;
output xillyvga_0_vga_de;
output [7:0] xillyvga_0_vga_red;
output [7:0] xillyvga_0_vga_green;
output [7:0] xillyvga_0_vga_blue;
output xillyvga_0_vga_clk;
inout [55:0] processing_system7_0_GPIO;
input processing_system7_0_USB0_VBUS_PWRFAULT;
output xillybus_lite_0_user_clk_pin;
output xillybus_lite_0_user_wren_pin;
output [3:0] xillybus_lite_0_user_wstrb_pin;
output xillybus_lite_0_user_rden_pin;
input [31:0] xillybus_lite_0_user_rd_data_pin;
output [31:0] xillybus_lite_0_user_wr_data_pin;
output [31:0] xillybus_lite_0_user_addr_pin;
input xillybus_lite_0_user_irq_pin;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 21:00:31
// Design Name:
// Module Name: D_ff_with_ce_and_synch_reset_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module D_ff_with_ce_and_synch_reset_behavior_tb(
);
reg D, Clk, reset, ce;
wire Q;
D_ff_with_ce_and_synch_reset_behavior DUT (.D(D), .Clk(Clk), .reset(reset), .ce(ce), .Q(Q));
initial begin
#300 $finish;
end
initial begin
D = 0; Clk = 0; reset = 0; ce = 0;
#10 Clk = 1;
#10 Clk = 0; D = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ce = 1;
#10 Clk = 1;
#10 Clk = 0; ce = 0;
#10 Clk = 1;
#10 Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0; reset = 1;
#10 Clk = 1;
#10 Clk = 0; reset = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ce = 1;
#10 Clk = 1;
#10 Clk = 0; ce = 0;
#10 Clk = 1;
#10 Clk = 0; D = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ce = 1;
#10 Clk = 1;
#10 Clk = 0; ce = 0;
#10 Clk = 1;
#10 Clk = 0;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / RIU_OR
// /___/ /\ Filename : RIU_OR.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RIU_OR #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter SIM_DEVICE = "ULTRASCALE",
parameter real SIM_VERSION = 2.0
)(
output [15:0] RIU_RD_DATA,
output RIU_RD_VALID,
input [15:0] RIU_RD_DATA_LOW,
input [15:0] RIU_RD_DATA_UPP,
input RIU_RD_VALID_LOW,
input RIU_RD_VALID_UPP
);
// define constants
localparam MODULE_NAME = "RIU_OR";
// Parameter encodings and registers
localparam SIM_DEVICE_ULTRASCALE = 0;
localparam SIM_DEVICE_ULTRASCALE_PLUS = 1;
localparam SIM_DEVICE_ULTRASCALE_PLUS_ES1 = 2;
localparam SIM_DEVICE_ULTRASCALE_PLUS_ES2 = 3;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
//`ifdef XIL_DR
// `include "RIU_OR_dr.v"
//`else
localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE;
localparam real SIM_VERSION_REG = SIM_VERSION;
//`endif
wire [1:0] SIM_DEVICE_BIN;
wire [63:0] SIM_VERSION_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire RIU_RD_VALID_out;
wire [15:0] RIU_RD_DATA_out;
wire RIU_RD_VALID_LOW_in;
wire RIU_RD_VALID_UPP_in;
wire [15:0] RIU_RD_DATA_LOW_in;
wire [15:0] RIU_RD_DATA_UPP_in;
assign RIU_RD_DATA = RIU_RD_DATA_out;
assign RIU_RD_VALID = RIU_RD_VALID_out;
assign RIU_RD_DATA_LOW_in = RIU_RD_DATA_LOW;
assign RIU_RD_DATA_UPP_in = RIU_RD_DATA_UPP;
assign RIU_RD_VALID_LOW_in = RIU_RD_VALID_LOW;
assign RIU_RD_VALID_UPP_in = RIU_RD_VALID_UPP;
assign SIM_DEVICE_BIN =
(SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE :
(SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS :
(SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 :
(SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES2") ? SIM_DEVICE_ULTRASCALE_PLUS_ES2 :
SIM_DEVICE_ULTRASCALE;
assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-101] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != 2.0) &&
(SIM_VERSION_REG != 1.0))) begin
$display("Error: [Unisim %s-102] SIM_VERSION attribute is set to %f. Legal values for this attribute are 2.0 or 1.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign RIU_RD_DATA_out = RIU_RD_DATA_UPP_in | RIU_RD_DATA_LOW_in;
assign RIU_RD_VALID_out = RIU_RD_VALID_UPP_in & RIU_RD_VALID_LOW_in;
specify
(RIU_RD_DATA_LOW *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RIU_RD_DATA_UPP *> RIU_RD_DATA) = (0:0:0, 0:0:0);
(RIU_RD_VALID_LOW => RIU_RD_VALID) = (0:0:0, 0:0:0);
(RIU_RD_VALID_UPP => RIU_RD_VALID) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_delta (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter min = 1;
parameter max = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_DELTA";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_delta_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_delta_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_delta_psl_logic.v"
`else
`endmodule // ovl_delta
`endif
|
module scratch_pad_synthesis(clk, in, out, sel);
parameter PORTS = 8;
parameter WIDTH = 64;
parameter FRAGMENT_DEPTH = 512;
parameter REORDER_DEPTH = 32;
parameter FIFO_DEPTH = 32;
parameter REORDER_BITS = log2(REORDER_DEPTH-1) + 1;
parameter DEPTH = FRAGMENT_DEPTH * PORTS;
parameter ADDR_WIDTH = log2(DEPTH-1);
parameter PORTS_ADDR_WIDTH = log2(PORTS-1);
input clk, in, sel;
output reg out;
reg rst;
reg [0:PORTS-1] rd_en;
reg [0:PORTS-1] wr_en;
reg [WIDTH*PORTS-1:0] d;
wire [WIDTH*PORTS-1:0] q;
reg [ADDR_WIDTH*PORTS-1:0] addr;
wire [0:PORTS-1] full;
reg [0:PORTS-1]stall;
wire [0:PORTS-1]valid;
scratch_pad #(PORTS, WIDTH) dut(rst, clk, rd_en, wr_en, d, q, addr, stall, valid, full);
always @(posedge clk) begin
rst <= in;
rd_en[0] <= rst;
rd_en[1:PORTS - 1] <= rd_en[0:PORTS - 2];
wr_en[0] <= rd_en[PORTS - 1];
wr_en[1:PORTS - 1] <= wr_en[0:PORTS - 2];
d[0] <= wr_en[PORTS - 1];
d[WIDTH * PORTS - 1:1] <= d[WIDTH * PORTS - 2:0];
addr[0] <= d[WIDTH * PORTS - 1];
addr[PORTS * ADDR_WIDTH - 1:1] <= addr[PORTS * ADDR_WIDTH - 2:0];
stall[0] <= addr[PORTS * ADDR_WIDTH - 1];
stall[1:PORTS - 1] <= stall[0:PORTS - 2];
end
reg [0:WIDTH * PORTS + 2 * PORTS - 1] output_shift;
always @(posedge clk) begin
if(sel == 1) begin
output_shift[0:PORTS * WIDTH - 1] <= q;
output_shift[PORTS * WIDTH +: PORTS] <= full;
output_shift[PORTS * WIDTH + PORTS +: PORTS] <= valid;
end else begin
output_shift[1:PORTS * WIDTH + 2 * PORTS - 1] <= output_shift[0:PORTS * WIDTH + 2 * PORTS - 2];
out <= output_shift[PORTS * WIDTH + 2 * PORTS - 1];
end
end
`include "common.vh"
endmodule
|
`timescale 1ns / 10ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:28:52 02/12/2015
// Design Name: top
// Module Name: S:/Xilinx/Assignment2/top_tb.v
// Project Name: Assignment2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module alu_tb;
parameter DATA_WIDTH = 8;
parameter OPCODE_LENGTH = 4;
parameter VECTOR_LENGTH = OPCODE_LENGTH + DATA_WIDTH + DATA_WIDTH;
// Inputs
reg [VECTOR_LENGTH-1:0] opcode_inputs;
reg reset;
reg clk;
// Outputs
wire [DATA_WIDTH-1:0] final_output;
wire carry_output, zero_flag;
// Instantiate the Unit Under Test (UUT)
alu alublock (
.final_output(final_output),
.carry_output(carry_output),
.zero_flag(zero_flag),
.opcode_inputs(opcode_inputs),
.reset_in(reset),
.clk(clk)
);
initial begin
// Initialize Inputs
// opcode_inputs = 0;
reset =1;
clk=1;
// Wait 100 ns for global reset to finish
#2 reset = 0; opcode_inputs = 20'b0001_1111_1111_0000_0001; // ADD
// #4 opcode_inputs = 36'b0011_1001_0000_0101_0101_1000_0000_0000_0001; // MULT
// #12 opcode_inputs = 36'b0010_0000_0000_0000_1110_0111_1111_1111_1111; // SUBTRACT
// #4 opcode_inputs = 36'b1001_0000_0000_0000_0000_0000_0000_0000_0000; // ZERO TEST
// #1 opcode_inputs = 36'b1100_0000_0010_0000_0000_0000_0001_1111_1111; // LESS THAN
// #2 opcode_inputs = 36'b1010_0000_0010_0000_0000_0000_0001_1111_1111; // GREATER THAN
// #2 opcode_inputs = 36'b0110_0000_0010_0000_0000_0000_0001_1111_1111; // AND
// #1 opcode_inputs = 36'b0111_0000_0010_0000_0000_0000_0001_1111_1111; // OR
// #2 opcode_inputs = 36'b1011_0000_0010_0000_0000_0000_0001_1111_1111; // EQUAL
// #2 opcode_inputs = 36'b0100_1000_0000_0000_0000_0000_0000_0000_0000; // DIVIDE
#4 $finish;
// Add stimulus here
end
always begin
#1 clk = ~clk; // Toggle clock every 1 ticks
end
endmodule
|
// limbus_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module limbus_mm_interconnect_0 (
input wire clk_100_clk_clk, // clk_100_clk.clk
input wire cpu_reset_reset_bridge_in_reset_reset, // cpu_reset_reset_bridge_in_reset.reset
input wire [21:0] cpu_data_master_address, // cpu_data_master.address
output wire cpu_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_data_master_byteenable, // .byteenable
input wire cpu_data_master_read, // .read
output wire [31:0] cpu_data_master_readdata, // .readdata
input wire cpu_data_master_write, // .write
input wire [31:0] cpu_data_master_writedata, // .writedata
input wire cpu_data_master_debugaccess, // .debugaccess
input wire [21:0] cpu_instruction_master_address, // cpu_instruction_master.address
output wire cpu_instruction_master_waitrequest, // .waitrequest
input wire cpu_instruction_master_read, // .read
output wire [31:0] cpu_instruction_master_readdata, // .readdata
output wire [17:0] cortex_s0_address, // cortex_s0.address
output wire cortex_s0_write, // .write
output wire cortex_s0_read, // .read
input wire [31:0] cortex_s0_readdata, // .readdata
output wire [31:0] cortex_s0_writedata, // .writedata
input wire cortex_s0_readdatavalid, // .readdatavalid
output wire [8:0] cpu_debug_mem_slave_address, // cpu_debug_mem_slave.address
output wire cpu_debug_mem_slave_write, // .write
output wire cpu_debug_mem_slave_read, // .read
input wire [31:0] cpu_debug_mem_slave_readdata, // .readdata
output wire [31:0] cpu_debug_mem_slave_writedata, // .writedata
output wire [3:0] cpu_debug_mem_slave_byteenable, // .byteenable
input wire cpu_debug_mem_slave_waitrequest, // .waitrequest
output wire cpu_debug_mem_slave_debugaccess, // .debugaccess
output wire [1:0] hdmi_tx_int_n_s1_address, // hdmi_tx_int_n_s1.address
output wire hdmi_tx_int_n_s1_write, // .write
input wire [31:0] hdmi_tx_int_n_s1_readdata, // .readdata
output wire [31:0] hdmi_tx_int_n_s1_writedata, // .writedata
output wire hdmi_tx_int_n_s1_chipselect, // .chipselect
output wire [0:0] jtag_uart_0_avalon_jtag_slave_address, // jtag_uart_0_avalon_jtag_slave.address
output wire jtag_uart_0_avalon_jtag_slave_write, // .write
output wire jtag_uart_0_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_0_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_0_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_0_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_0_avalon_jtag_slave_chipselect, // .chipselect
output wire [18:0] sram_uas_address, // sram_uas.address
output wire sram_uas_write, // .write
output wire sram_uas_read, // .read
input wire [15:0] sram_uas_readdata, // .readdata
output wire [15:0] sram_uas_writedata, // .writedata
output wire [1:0] sram_uas_burstcount, // .burstcount
output wire [1:0] sram_uas_byteenable, // .byteenable
input wire sram_uas_readdatavalid, // .readdatavalid
input wire sram_uas_waitrequest, // .waitrequest
output wire sram_uas_lock, // .lock
output wire sram_uas_debugaccess, // .debugaccess
output wire [2:0] timer_0_s1_address, // timer_0_s1.address
output wire timer_0_s1_write, // .write
input wire [15:0] timer_0_s1_readdata, // .readdata
output wire [15:0] timer_0_s1_writedata, // .writedata
output wire timer_0_s1_chipselect, // .chipselect
output wire [2:0] uart_s1_address, // uart_s1.address
output wire uart_s1_write, // .write
output wire uart_s1_read, // .read
input wire [15:0] uart_s1_readdata, // .readdata
output wire [15:0] uart_s1_writedata, // .writedata
output wire uart_s1_begintransfer, // .begintransfer
output wire uart_s1_chipselect // .chipselect
);
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
wire [21:0] cpu_data_master_translator_avalon_universal_master_0_address; // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_read; // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
wire cpu_data_master_translator_avalon_universal_master_0_lock; // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_data_master_agent:rp_valid
wire [97:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_data_master_agent:rp_data
wire rsp_mux_src_ready; // cpu_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_data_master_agent:rp_endofpacket
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
wire [21:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> cpu_instruction_master_agent:rp_valid
wire [97:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> cpu_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // cpu_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [6:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [21:0] jtag_uart_0_avalon_jtag_slave_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [98:0] jtag_uart_0_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_valid
wire [98:0] jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_0_avalon_jtag_slave_agent:cp_valid
wire [97:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_0_avalon_jtag_slave_agent:cp_data
wire cmd_mux_src_ready; // jtag_uart_0_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_0_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_endofpacket
wire [31:0] cpu_debug_mem_slave_agent_m0_readdata; // cpu_debug_mem_slave_translator:uav_readdata -> cpu_debug_mem_slave_agent:m0_readdata
wire cpu_debug_mem_slave_agent_m0_waitrequest; // cpu_debug_mem_slave_translator:uav_waitrequest -> cpu_debug_mem_slave_agent:m0_waitrequest
wire cpu_debug_mem_slave_agent_m0_debugaccess; // cpu_debug_mem_slave_agent:m0_debugaccess -> cpu_debug_mem_slave_translator:uav_debugaccess
wire [21:0] cpu_debug_mem_slave_agent_m0_address; // cpu_debug_mem_slave_agent:m0_address -> cpu_debug_mem_slave_translator:uav_address
wire [3:0] cpu_debug_mem_slave_agent_m0_byteenable; // cpu_debug_mem_slave_agent:m0_byteenable -> cpu_debug_mem_slave_translator:uav_byteenable
wire cpu_debug_mem_slave_agent_m0_read; // cpu_debug_mem_slave_agent:m0_read -> cpu_debug_mem_slave_translator:uav_read
wire cpu_debug_mem_slave_agent_m0_readdatavalid; // cpu_debug_mem_slave_translator:uav_readdatavalid -> cpu_debug_mem_slave_agent:m0_readdatavalid
wire cpu_debug_mem_slave_agent_m0_lock; // cpu_debug_mem_slave_agent:m0_lock -> cpu_debug_mem_slave_translator:uav_lock
wire [31:0] cpu_debug_mem_slave_agent_m0_writedata; // cpu_debug_mem_slave_agent:m0_writedata -> cpu_debug_mem_slave_translator:uav_writedata
wire cpu_debug_mem_slave_agent_m0_write; // cpu_debug_mem_slave_agent:m0_write -> cpu_debug_mem_slave_translator:uav_write
wire [2:0] cpu_debug_mem_slave_agent_m0_burstcount; // cpu_debug_mem_slave_agent:m0_burstcount -> cpu_debug_mem_slave_translator:uav_burstcount
wire cpu_debug_mem_slave_agent_rf_source_valid; // cpu_debug_mem_slave_agent:rf_source_valid -> cpu_debug_mem_slave_agent_rsp_fifo:in_valid
wire [98:0] cpu_debug_mem_slave_agent_rf_source_data; // cpu_debug_mem_slave_agent:rf_source_data -> cpu_debug_mem_slave_agent_rsp_fifo:in_data
wire cpu_debug_mem_slave_agent_rf_source_ready; // cpu_debug_mem_slave_agent_rsp_fifo:in_ready -> cpu_debug_mem_slave_agent:rf_source_ready
wire cpu_debug_mem_slave_agent_rf_source_startofpacket; // cpu_debug_mem_slave_agent:rf_source_startofpacket -> cpu_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire cpu_debug_mem_slave_agent_rf_source_endofpacket; // cpu_debug_mem_slave_agent:rf_source_endofpacket -> cpu_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire cpu_debug_mem_slave_agent_rsp_fifo_out_valid; // cpu_debug_mem_slave_agent_rsp_fifo:out_valid -> cpu_debug_mem_slave_agent:rf_sink_valid
wire [98:0] cpu_debug_mem_slave_agent_rsp_fifo_out_data; // cpu_debug_mem_slave_agent_rsp_fifo:out_data -> cpu_debug_mem_slave_agent:rf_sink_data
wire cpu_debug_mem_slave_agent_rsp_fifo_out_ready; // cpu_debug_mem_slave_agent:rf_sink_ready -> cpu_debug_mem_slave_agent_rsp_fifo:out_ready
wire cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // cpu_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> cpu_debug_mem_slave_agent:rf_sink_startofpacket
wire cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // cpu_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> cpu_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> cpu_debug_mem_slave_agent:cp_valid
wire [97:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> cpu_debug_mem_slave_agent:cp_data
wire cmd_mux_001_src_ready; // cpu_debug_mem_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> cpu_debug_mem_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> cpu_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> cpu_debug_mem_slave_agent:cp_endofpacket
wire [31:0] cortex_s0_agent_m0_readdata; // cortex_s0_translator:uav_readdata -> cortex_s0_agent:m0_readdata
wire cortex_s0_agent_m0_waitrequest; // cortex_s0_translator:uav_waitrequest -> cortex_s0_agent:m0_waitrequest
wire cortex_s0_agent_m0_debugaccess; // cortex_s0_agent:m0_debugaccess -> cortex_s0_translator:uav_debugaccess
wire [21:0] cortex_s0_agent_m0_address; // cortex_s0_agent:m0_address -> cortex_s0_translator:uav_address
wire [3:0] cortex_s0_agent_m0_byteenable; // cortex_s0_agent:m0_byteenable -> cortex_s0_translator:uav_byteenable
wire cortex_s0_agent_m0_read; // cortex_s0_agent:m0_read -> cortex_s0_translator:uav_read
wire cortex_s0_agent_m0_readdatavalid; // cortex_s0_translator:uav_readdatavalid -> cortex_s0_agent:m0_readdatavalid
wire cortex_s0_agent_m0_lock; // cortex_s0_agent:m0_lock -> cortex_s0_translator:uav_lock
wire [31:0] cortex_s0_agent_m0_writedata; // cortex_s0_agent:m0_writedata -> cortex_s0_translator:uav_writedata
wire cortex_s0_agent_m0_write; // cortex_s0_agent:m0_write -> cortex_s0_translator:uav_write
wire [2:0] cortex_s0_agent_m0_burstcount; // cortex_s0_agent:m0_burstcount -> cortex_s0_translator:uav_burstcount
wire cortex_s0_agent_rf_source_valid; // cortex_s0_agent:rf_source_valid -> cortex_s0_agent_rsp_fifo:in_valid
wire [98:0] cortex_s0_agent_rf_source_data; // cortex_s0_agent:rf_source_data -> cortex_s0_agent_rsp_fifo:in_data
wire cortex_s0_agent_rf_source_ready; // cortex_s0_agent_rsp_fifo:in_ready -> cortex_s0_agent:rf_source_ready
wire cortex_s0_agent_rf_source_startofpacket; // cortex_s0_agent:rf_source_startofpacket -> cortex_s0_agent_rsp_fifo:in_startofpacket
wire cortex_s0_agent_rf_source_endofpacket; // cortex_s0_agent:rf_source_endofpacket -> cortex_s0_agent_rsp_fifo:in_endofpacket
wire cortex_s0_agent_rsp_fifo_out_valid; // cortex_s0_agent_rsp_fifo:out_valid -> cortex_s0_agent:rf_sink_valid
wire [98:0] cortex_s0_agent_rsp_fifo_out_data; // cortex_s0_agent_rsp_fifo:out_data -> cortex_s0_agent:rf_sink_data
wire cortex_s0_agent_rsp_fifo_out_ready; // cortex_s0_agent:rf_sink_ready -> cortex_s0_agent_rsp_fifo:out_ready
wire cortex_s0_agent_rsp_fifo_out_startofpacket; // cortex_s0_agent_rsp_fifo:out_startofpacket -> cortex_s0_agent:rf_sink_startofpacket
wire cortex_s0_agent_rsp_fifo_out_endofpacket; // cortex_s0_agent_rsp_fifo:out_endofpacket -> cortex_s0_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> cortex_s0_agent:cp_valid
wire [97:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> cortex_s0_agent:cp_data
wire cmd_mux_002_src_ready; // cortex_s0_agent:cp_ready -> cmd_mux_002:src_ready
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> cortex_s0_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> cortex_s0_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> cortex_s0_agent:cp_endofpacket
wire [31:0] timer_0_s1_agent_m0_readdata; // timer_0_s1_translator:uav_readdata -> timer_0_s1_agent:m0_readdata
wire timer_0_s1_agent_m0_waitrequest; // timer_0_s1_translator:uav_waitrequest -> timer_0_s1_agent:m0_waitrequest
wire timer_0_s1_agent_m0_debugaccess; // timer_0_s1_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
wire [21:0] timer_0_s1_agent_m0_address; // timer_0_s1_agent:m0_address -> timer_0_s1_translator:uav_address
wire [3:0] timer_0_s1_agent_m0_byteenable; // timer_0_s1_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
wire timer_0_s1_agent_m0_read; // timer_0_s1_agent:m0_read -> timer_0_s1_translator:uav_read
wire timer_0_s1_agent_m0_readdatavalid; // timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_agent:m0_readdatavalid
wire timer_0_s1_agent_m0_lock; // timer_0_s1_agent:m0_lock -> timer_0_s1_translator:uav_lock
wire [31:0] timer_0_s1_agent_m0_writedata; // timer_0_s1_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
wire timer_0_s1_agent_m0_write; // timer_0_s1_agent:m0_write -> timer_0_s1_translator:uav_write
wire [2:0] timer_0_s1_agent_m0_burstcount; // timer_0_s1_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
wire timer_0_s1_agent_rf_source_valid; // timer_0_s1_agent:rf_source_valid -> timer_0_s1_agent_rsp_fifo:in_valid
wire [98:0] timer_0_s1_agent_rf_source_data; // timer_0_s1_agent:rf_source_data -> timer_0_s1_agent_rsp_fifo:in_data
wire timer_0_s1_agent_rf_source_ready; // timer_0_s1_agent_rsp_fifo:in_ready -> timer_0_s1_agent:rf_source_ready
wire timer_0_s1_agent_rf_source_startofpacket; // timer_0_s1_agent:rf_source_startofpacket -> timer_0_s1_agent_rsp_fifo:in_startofpacket
wire timer_0_s1_agent_rf_source_endofpacket; // timer_0_s1_agent:rf_source_endofpacket -> timer_0_s1_agent_rsp_fifo:in_endofpacket
wire timer_0_s1_agent_rsp_fifo_out_valid; // timer_0_s1_agent_rsp_fifo:out_valid -> timer_0_s1_agent:rf_sink_valid
wire [98:0] timer_0_s1_agent_rsp_fifo_out_data; // timer_0_s1_agent_rsp_fifo:out_data -> timer_0_s1_agent:rf_sink_data
wire timer_0_s1_agent_rsp_fifo_out_ready; // timer_0_s1_agent:rf_sink_ready -> timer_0_s1_agent_rsp_fifo:out_ready
wire timer_0_s1_agent_rsp_fifo_out_startofpacket; // timer_0_s1_agent_rsp_fifo:out_startofpacket -> timer_0_s1_agent:rf_sink_startofpacket
wire timer_0_s1_agent_rsp_fifo_out_endofpacket; // timer_0_s1_agent_rsp_fifo:out_endofpacket -> timer_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> timer_0_s1_agent:cp_valid
wire [97:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> timer_0_s1_agent:cp_data
wire cmd_mux_003_src_ready; // timer_0_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> timer_0_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> timer_0_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> timer_0_s1_agent:cp_endofpacket
wire [31:0] uart_s1_agent_m0_readdata; // uart_s1_translator:uav_readdata -> uart_s1_agent:m0_readdata
wire uart_s1_agent_m0_waitrequest; // uart_s1_translator:uav_waitrequest -> uart_s1_agent:m0_waitrequest
wire uart_s1_agent_m0_debugaccess; // uart_s1_agent:m0_debugaccess -> uart_s1_translator:uav_debugaccess
wire [21:0] uart_s1_agent_m0_address; // uart_s1_agent:m0_address -> uart_s1_translator:uav_address
wire [3:0] uart_s1_agent_m0_byteenable; // uart_s1_agent:m0_byteenable -> uart_s1_translator:uav_byteenable
wire uart_s1_agent_m0_read; // uart_s1_agent:m0_read -> uart_s1_translator:uav_read
wire uart_s1_agent_m0_readdatavalid; // uart_s1_translator:uav_readdatavalid -> uart_s1_agent:m0_readdatavalid
wire uart_s1_agent_m0_lock; // uart_s1_agent:m0_lock -> uart_s1_translator:uav_lock
wire [31:0] uart_s1_agent_m0_writedata; // uart_s1_agent:m0_writedata -> uart_s1_translator:uav_writedata
wire uart_s1_agent_m0_write; // uart_s1_agent:m0_write -> uart_s1_translator:uav_write
wire [2:0] uart_s1_agent_m0_burstcount; // uart_s1_agent:m0_burstcount -> uart_s1_translator:uav_burstcount
wire uart_s1_agent_rf_source_valid; // uart_s1_agent:rf_source_valid -> uart_s1_agent_rsp_fifo:in_valid
wire [98:0] uart_s1_agent_rf_source_data; // uart_s1_agent:rf_source_data -> uart_s1_agent_rsp_fifo:in_data
wire uart_s1_agent_rf_source_ready; // uart_s1_agent_rsp_fifo:in_ready -> uart_s1_agent:rf_source_ready
wire uart_s1_agent_rf_source_startofpacket; // uart_s1_agent:rf_source_startofpacket -> uart_s1_agent_rsp_fifo:in_startofpacket
wire uart_s1_agent_rf_source_endofpacket; // uart_s1_agent:rf_source_endofpacket -> uart_s1_agent_rsp_fifo:in_endofpacket
wire uart_s1_agent_rsp_fifo_out_valid; // uart_s1_agent_rsp_fifo:out_valid -> uart_s1_agent:rf_sink_valid
wire [98:0] uart_s1_agent_rsp_fifo_out_data; // uart_s1_agent_rsp_fifo:out_data -> uart_s1_agent:rf_sink_data
wire uart_s1_agent_rsp_fifo_out_ready; // uart_s1_agent:rf_sink_ready -> uart_s1_agent_rsp_fifo:out_ready
wire uart_s1_agent_rsp_fifo_out_startofpacket; // uart_s1_agent_rsp_fifo:out_startofpacket -> uart_s1_agent:rf_sink_startofpacket
wire uart_s1_agent_rsp_fifo_out_endofpacket; // uart_s1_agent_rsp_fifo:out_endofpacket -> uart_s1_agent:rf_sink_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> uart_s1_agent:cp_valid
wire [97:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> uart_s1_agent:cp_data
wire cmd_mux_004_src_ready; // uart_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> uart_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> uart_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> uart_s1_agent:cp_endofpacket
wire [31:0] hdmi_tx_int_n_s1_agent_m0_readdata; // hdmi_tx_int_n_s1_translator:uav_readdata -> hdmi_tx_int_n_s1_agent:m0_readdata
wire hdmi_tx_int_n_s1_agent_m0_waitrequest; // hdmi_tx_int_n_s1_translator:uav_waitrequest -> hdmi_tx_int_n_s1_agent:m0_waitrequest
wire hdmi_tx_int_n_s1_agent_m0_debugaccess; // hdmi_tx_int_n_s1_agent:m0_debugaccess -> hdmi_tx_int_n_s1_translator:uav_debugaccess
wire [21:0] hdmi_tx_int_n_s1_agent_m0_address; // hdmi_tx_int_n_s1_agent:m0_address -> hdmi_tx_int_n_s1_translator:uav_address
wire [3:0] hdmi_tx_int_n_s1_agent_m0_byteenable; // hdmi_tx_int_n_s1_agent:m0_byteenable -> hdmi_tx_int_n_s1_translator:uav_byteenable
wire hdmi_tx_int_n_s1_agent_m0_read; // hdmi_tx_int_n_s1_agent:m0_read -> hdmi_tx_int_n_s1_translator:uav_read
wire hdmi_tx_int_n_s1_agent_m0_readdatavalid; // hdmi_tx_int_n_s1_translator:uav_readdatavalid -> hdmi_tx_int_n_s1_agent:m0_readdatavalid
wire hdmi_tx_int_n_s1_agent_m0_lock; // hdmi_tx_int_n_s1_agent:m0_lock -> hdmi_tx_int_n_s1_translator:uav_lock
wire [31:0] hdmi_tx_int_n_s1_agent_m0_writedata; // hdmi_tx_int_n_s1_agent:m0_writedata -> hdmi_tx_int_n_s1_translator:uav_writedata
wire hdmi_tx_int_n_s1_agent_m0_write; // hdmi_tx_int_n_s1_agent:m0_write -> hdmi_tx_int_n_s1_translator:uav_write
wire [2:0] hdmi_tx_int_n_s1_agent_m0_burstcount; // hdmi_tx_int_n_s1_agent:m0_burstcount -> hdmi_tx_int_n_s1_translator:uav_burstcount
wire hdmi_tx_int_n_s1_agent_rf_source_valid; // hdmi_tx_int_n_s1_agent:rf_source_valid -> hdmi_tx_int_n_s1_agent_rsp_fifo:in_valid
wire [98:0] hdmi_tx_int_n_s1_agent_rf_source_data; // hdmi_tx_int_n_s1_agent:rf_source_data -> hdmi_tx_int_n_s1_agent_rsp_fifo:in_data
wire hdmi_tx_int_n_s1_agent_rf_source_ready; // hdmi_tx_int_n_s1_agent_rsp_fifo:in_ready -> hdmi_tx_int_n_s1_agent:rf_source_ready
wire hdmi_tx_int_n_s1_agent_rf_source_startofpacket; // hdmi_tx_int_n_s1_agent:rf_source_startofpacket -> hdmi_tx_int_n_s1_agent_rsp_fifo:in_startofpacket
wire hdmi_tx_int_n_s1_agent_rf_source_endofpacket; // hdmi_tx_int_n_s1_agent:rf_source_endofpacket -> hdmi_tx_int_n_s1_agent_rsp_fifo:in_endofpacket
wire hdmi_tx_int_n_s1_agent_rsp_fifo_out_valid; // hdmi_tx_int_n_s1_agent_rsp_fifo:out_valid -> hdmi_tx_int_n_s1_agent:rf_sink_valid
wire [98:0] hdmi_tx_int_n_s1_agent_rsp_fifo_out_data; // hdmi_tx_int_n_s1_agent_rsp_fifo:out_data -> hdmi_tx_int_n_s1_agent:rf_sink_data
wire hdmi_tx_int_n_s1_agent_rsp_fifo_out_ready; // hdmi_tx_int_n_s1_agent:rf_sink_ready -> hdmi_tx_int_n_s1_agent_rsp_fifo:out_ready
wire hdmi_tx_int_n_s1_agent_rsp_fifo_out_startofpacket; // hdmi_tx_int_n_s1_agent_rsp_fifo:out_startofpacket -> hdmi_tx_int_n_s1_agent:rf_sink_startofpacket
wire hdmi_tx_int_n_s1_agent_rsp_fifo_out_endofpacket; // hdmi_tx_int_n_s1_agent_rsp_fifo:out_endofpacket -> hdmi_tx_int_n_s1_agent:rf_sink_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> hdmi_tx_int_n_s1_agent:cp_valid
wire [97:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> hdmi_tx_int_n_s1_agent:cp_data
wire cmd_mux_005_src_ready; // hdmi_tx_int_n_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> hdmi_tx_int_n_s1_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> hdmi_tx_int_n_s1_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> hdmi_tx_int_n_s1_agent:cp_endofpacket
wire [15:0] sram_uas_agent_m0_readdata; // sram_uas_translator:uav_readdata -> sram_uas_agent:m0_readdata
wire sram_uas_agent_m0_waitrequest; // sram_uas_translator:uav_waitrequest -> sram_uas_agent:m0_waitrequest
wire sram_uas_agent_m0_debugaccess; // sram_uas_agent:m0_debugaccess -> sram_uas_translator:uav_debugaccess
wire [21:0] sram_uas_agent_m0_address; // sram_uas_agent:m0_address -> sram_uas_translator:uav_address
wire [1:0] sram_uas_agent_m0_byteenable; // sram_uas_agent:m0_byteenable -> sram_uas_translator:uav_byteenable
wire sram_uas_agent_m0_read; // sram_uas_agent:m0_read -> sram_uas_translator:uav_read
wire sram_uas_agent_m0_readdatavalid; // sram_uas_translator:uav_readdatavalid -> sram_uas_agent:m0_readdatavalid
wire sram_uas_agent_m0_lock; // sram_uas_agent:m0_lock -> sram_uas_translator:uav_lock
wire [15:0] sram_uas_agent_m0_writedata; // sram_uas_agent:m0_writedata -> sram_uas_translator:uav_writedata
wire sram_uas_agent_m0_write; // sram_uas_agent:m0_write -> sram_uas_translator:uav_write
wire [1:0] sram_uas_agent_m0_burstcount; // sram_uas_agent:m0_burstcount -> sram_uas_translator:uav_burstcount
wire sram_uas_agent_rf_source_valid; // sram_uas_agent:rf_source_valid -> sram_uas_agent_rsp_fifo:in_valid
wire [80:0] sram_uas_agent_rf_source_data; // sram_uas_agent:rf_source_data -> sram_uas_agent_rsp_fifo:in_data
wire sram_uas_agent_rf_source_ready; // sram_uas_agent_rsp_fifo:in_ready -> sram_uas_agent:rf_source_ready
wire sram_uas_agent_rf_source_startofpacket; // sram_uas_agent:rf_source_startofpacket -> sram_uas_agent_rsp_fifo:in_startofpacket
wire sram_uas_agent_rf_source_endofpacket; // sram_uas_agent:rf_source_endofpacket -> sram_uas_agent_rsp_fifo:in_endofpacket
wire sram_uas_agent_rsp_fifo_out_valid; // sram_uas_agent_rsp_fifo:out_valid -> sram_uas_agent:rf_sink_valid
wire [80:0] sram_uas_agent_rsp_fifo_out_data; // sram_uas_agent_rsp_fifo:out_data -> sram_uas_agent:rf_sink_data
wire sram_uas_agent_rsp_fifo_out_ready; // sram_uas_agent:rf_sink_ready -> sram_uas_agent_rsp_fifo:out_ready
wire sram_uas_agent_rsp_fifo_out_startofpacket; // sram_uas_agent_rsp_fifo:out_startofpacket -> sram_uas_agent:rf_sink_startofpacket
wire sram_uas_agent_rsp_fifo_out_endofpacket; // sram_uas_agent_rsp_fifo:out_endofpacket -> sram_uas_agent:rf_sink_endofpacket
wire sram_uas_agent_rdata_fifo_src_valid; // sram_uas_agent:rdata_fifo_src_valid -> sram_uas_agent_rdata_fifo:in_valid
wire [17:0] sram_uas_agent_rdata_fifo_src_data; // sram_uas_agent:rdata_fifo_src_data -> sram_uas_agent_rdata_fifo:in_data
wire sram_uas_agent_rdata_fifo_src_ready; // sram_uas_agent_rdata_fifo:in_ready -> sram_uas_agent:rdata_fifo_src_ready
wire cpu_data_master_agent_cp_valid; // cpu_data_master_agent:cp_valid -> router:sink_valid
wire [97:0] cpu_data_master_agent_cp_data; // cpu_data_master_agent:cp_data -> router:sink_data
wire cpu_data_master_agent_cp_ready; // router:sink_ready -> cpu_data_master_agent:cp_ready
wire cpu_data_master_agent_cp_startofpacket; // cpu_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire cpu_data_master_agent_cp_endofpacket; // cpu_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [97:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [6:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire cpu_instruction_master_agent_cp_valid; // cpu_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [97:0] cpu_instruction_master_agent_cp_data; // cpu_instruction_master_agent:cp_data -> router_001:sink_data
wire cpu_instruction_master_agent_cp_ready; // router_001:sink_ready -> cpu_instruction_master_agent:cp_ready
wire cpu_instruction_master_agent_cp_startofpacket; // cpu_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire cpu_instruction_master_agent_cp_endofpacket; // cpu_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [97:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [6:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [97:0] jtag_uart_0_avalon_jtag_slave_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_uart_0_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [97:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [6:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire cpu_debug_mem_slave_agent_rp_valid; // cpu_debug_mem_slave_agent:rp_valid -> router_003:sink_valid
wire [97:0] cpu_debug_mem_slave_agent_rp_data; // cpu_debug_mem_slave_agent:rp_data -> router_003:sink_data
wire cpu_debug_mem_slave_agent_rp_ready; // router_003:sink_ready -> cpu_debug_mem_slave_agent:rp_ready
wire cpu_debug_mem_slave_agent_rp_startofpacket; // cpu_debug_mem_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire cpu_debug_mem_slave_agent_rp_endofpacket; // cpu_debug_mem_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [97:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [6:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire cortex_s0_agent_rp_valid; // cortex_s0_agent:rp_valid -> router_004:sink_valid
wire [97:0] cortex_s0_agent_rp_data; // cortex_s0_agent:rp_data -> router_004:sink_data
wire cortex_s0_agent_rp_ready; // router_004:sink_ready -> cortex_s0_agent:rp_ready
wire cortex_s0_agent_rp_startofpacket; // cortex_s0_agent:rp_startofpacket -> router_004:sink_startofpacket
wire cortex_s0_agent_rp_endofpacket; // cortex_s0_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [97:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [6:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire timer_0_s1_agent_rp_valid; // timer_0_s1_agent:rp_valid -> router_005:sink_valid
wire [97:0] timer_0_s1_agent_rp_data; // timer_0_s1_agent:rp_data -> router_005:sink_data
wire timer_0_s1_agent_rp_ready; // router_005:sink_ready -> timer_0_s1_agent:rp_ready
wire timer_0_s1_agent_rp_startofpacket; // timer_0_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire timer_0_s1_agent_rp_endofpacket; // timer_0_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [97:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire uart_s1_agent_rp_valid; // uart_s1_agent:rp_valid -> router_006:sink_valid
wire [97:0] uart_s1_agent_rp_data; // uart_s1_agent:rp_data -> router_006:sink_data
wire uart_s1_agent_rp_ready; // router_006:sink_ready -> uart_s1_agent:rp_ready
wire uart_s1_agent_rp_startofpacket; // uart_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire uart_s1_agent_rp_endofpacket; // uart_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [97:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire hdmi_tx_int_n_s1_agent_rp_valid; // hdmi_tx_int_n_s1_agent:rp_valid -> router_007:sink_valid
wire [97:0] hdmi_tx_int_n_s1_agent_rp_data; // hdmi_tx_int_n_s1_agent:rp_data -> router_007:sink_data
wire hdmi_tx_int_n_s1_agent_rp_ready; // router_007:sink_ready -> hdmi_tx_int_n_s1_agent:rp_ready
wire hdmi_tx_int_n_s1_agent_rp_startofpacket; // hdmi_tx_int_n_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire hdmi_tx_int_n_s1_agent_rp_endofpacket; // hdmi_tx_int_n_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [97:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire sram_uas_agent_rp_valid; // sram_uas_agent:rp_valid -> router_008:sink_valid
wire [79:0] sram_uas_agent_rp_data; // sram_uas_agent:rp_data -> router_008:sink_data
wire sram_uas_agent_rp_ready; // router_008:sink_ready -> sram_uas_agent:rp_ready
wire sram_uas_agent_rp_startofpacket; // sram_uas_agent:rp_startofpacket -> router_008:sink_startofpacket
wire sram_uas_agent_rp_endofpacket; // sram_uas_agent:rp_endofpacket -> router_008:sink_endofpacket
wire sram_uas_burst_adapter_source0_valid; // sram_uas_burst_adapter:source0_valid -> sram_uas_agent:cp_valid
wire [79:0] sram_uas_burst_adapter_source0_data; // sram_uas_burst_adapter:source0_data -> sram_uas_agent:cp_data
wire sram_uas_burst_adapter_source0_ready; // sram_uas_agent:cp_ready -> sram_uas_burst_adapter:source0_ready
wire [6:0] sram_uas_burst_adapter_source0_channel; // sram_uas_burst_adapter:source0_channel -> sram_uas_agent:cp_channel
wire sram_uas_burst_adapter_source0_startofpacket; // sram_uas_burst_adapter:source0_startofpacket -> sram_uas_agent:cp_startofpacket
wire sram_uas_burst_adapter_source0_endofpacket; // sram_uas_burst_adapter:source0_endofpacket -> sram_uas_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [97:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [97:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [97:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [97:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [97:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [97:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire [97:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire [6:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [97:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [6:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire [97:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire [6:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_006:sink1_valid
wire [97:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_006:sink1_data
wire cmd_demux_001_src2_ready; // cmd_mux_006:sink1_ready -> cmd_demux_001:src2_ready
wire [6:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_006:sink1_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_006:sink1_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_006:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [97:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [97:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [6:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [97:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire [97:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire [6:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [97:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [97:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [97:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [97:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire [97:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src1_valid; // rsp_demux_006:src1_valid -> rsp_mux_001:sink2_valid
wire [97:0] rsp_demux_006_src1_data; // rsp_demux_006:src1_data -> rsp_mux_001:sink2_data
wire rsp_demux_006_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_006:src1_ready
wire [6:0] rsp_demux_006_src1_channel; // rsp_demux_006:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_006_src1_startofpacket; // rsp_demux_006:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_006_src1_endofpacket; // rsp_demux_006:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire router_008_src_valid; // router_008:src_valid -> sram_uas_rsp_width_adapter:in_valid
wire [79:0] router_008_src_data; // router_008:src_data -> sram_uas_rsp_width_adapter:in_data
wire router_008_src_ready; // sram_uas_rsp_width_adapter:in_ready -> router_008:src_ready
wire [6:0] router_008_src_channel; // router_008:src_channel -> sram_uas_rsp_width_adapter:in_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> sram_uas_rsp_width_adapter:in_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> sram_uas_rsp_width_adapter:in_endofpacket
wire sram_uas_rsp_width_adapter_src_valid; // sram_uas_rsp_width_adapter:out_valid -> rsp_demux_006:sink_valid
wire [97:0] sram_uas_rsp_width_adapter_src_data; // sram_uas_rsp_width_adapter:out_data -> rsp_demux_006:sink_data
wire sram_uas_rsp_width_adapter_src_ready; // rsp_demux_006:sink_ready -> sram_uas_rsp_width_adapter:out_ready
wire [6:0] sram_uas_rsp_width_adapter_src_channel; // sram_uas_rsp_width_adapter:out_channel -> rsp_demux_006:sink_channel
wire sram_uas_rsp_width_adapter_src_startofpacket; // sram_uas_rsp_width_adapter:out_startofpacket -> rsp_demux_006:sink_startofpacket
wire sram_uas_rsp_width_adapter_src_endofpacket; // sram_uas_rsp_width_adapter:out_endofpacket -> rsp_demux_006:sink_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> sram_uas_cmd_width_adapter:in_valid
wire [97:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> sram_uas_cmd_width_adapter:in_data
wire cmd_mux_006_src_ready; // sram_uas_cmd_width_adapter:in_ready -> cmd_mux_006:src_ready
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> sram_uas_cmd_width_adapter:in_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> sram_uas_cmd_width_adapter:in_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> sram_uas_cmd_width_adapter:in_endofpacket
wire sram_uas_cmd_width_adapter_src_valid; // sram_uas_cmd_width_adapter:out_valid -> sram_uas_burst_adapter:sink0_valid
wire [79:0] sram_uas_cmd_width_adapter_src_data; // sram_uas_cmd_width_adapter:out_data -> sram_uas_burst_adapter:sink0_data
wire sram_uas_cmd_width_adapter_src_ready; // sram_uas_burst_adapter:sink0_ready -> sram_uas_cmd_width_adapter:out_ready
wire [6:0] sram_uas_cmd_width_adapter_src_channel; // sram_uas_cmd_width_adapter:out_channel -> sram_uas_burst_adapter:sink0_channel
wire sram_uas_cmd_width_adapter_src_startofpacket; // sram_uas_cmd_width_adapter:out_startofpacket -> sram_uas_burst_adapter:sink0_startofpacket
wire sram_uas_cmd_width_adapter_src_endofpacket; // sram_uas_cmd_width_adapter:out_endofpacket -> sram_uas_burst_adapter:sink0_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_error
wire cpu_debug_mem_slave_agent_rdata_fifo_src_valid; // cpu_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] cpu_debug_mem_slave_agent_rdata_fifo_src_data; // cpu_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire cpu_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> cpu_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> cpu_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> cpu_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // cpu_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> cpu_debug_mem_slave_agent:rdata_fifo_sink_error
wire cortex_s0_agent_rdata_fifo_src_valid; // cortex_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] cortex_s0_agent_rdata_fifo_src_data; // cortex_s0_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire cortex_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> cortex_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> cortex_s0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> cortex_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // cortex_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> cortex_s0_agent:rdata_fifo_sink_error
wire timer_0_s1_agent_rdata_fifo_src_valid; // timer_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] timer_0_s1_agent_rdata_fifo_src_data; // timer_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire timer_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> timer_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> timer_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> timer_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // timer_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> timer_0_s1_agent:rdata_fifo_sink_error
wire uart_s1_agent_rdata_fifo_src_valid; // uart_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] uart_s1_agent_rdata_fifo_src_data; // uart_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire uart_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> uart_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> uart_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> uart_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // uart_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> uart_s1_agent:rdata_fifo_sink_error
wire hdmi_tx_int_n_s1_agent_rdata_fifo_src_valid; // hdmi_tx_int_n_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] hdmi_tx_int_n_s1_agent_rdata_fifo_src_data; // hdmi_tx_int_n_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire hdmi_tx_int_n_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> hdmi_tx_int_n_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> hdmi_tx_int_n_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> hdmi_tx_int_n_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // hdmi_tx_int_n_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> hdmi_tx_int_n_s1_agent:rdata_fifo_sink_error
wire sram_uas_agent_rdata_fifo_out_valid; // sram_uas_agent_rdata_fifo:out_valid -> avalon_st_adapter_006:in_0_valid
wire [17:0] sram_uas_agent_rdata_fifo_out_data; // sram_uas_agent_rdata_fifo:out_data -> avalon_st_adapter_006:in_0_data
wire sram_uas_agent_rdata_fifo_out_ready; // avalon_st_adapter_006:in_0_ready -> sram_uas_agent_rdata_fifo:out_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> sram_uas_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> sram_uas_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // sram_uas_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> sram_uas_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_data_master_translator (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_debug_mem_slave_translator (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (cpu_debug_mem_slave_agent_m0_read), // .read
.uav_write (cpu_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (cpu_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (cpu_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (cpu_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (cpu_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (cpu_debug_mem_slave_write), // .write
.av_read (cpu_debug_mem_slave_read), // .read
.av_readdata (cpu_debug_mem_slave_readdata), // .readdata
.av_writedata (cpu_debug_mem_slave_writedata), // .writedata
.av_byteenable (cpu_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (cpu_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (cpu_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (18),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cortex_s0_translator (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cortex_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cortex_s0_agent_m0_burstcount), // .burstcount
.uav_read (cortex_s0_agent_m0_read), // .read
.uav_write (cortex_s0_agent_m0_write), // .write
.uav_waitrequest (cortex_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cortex_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cortex_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (cortex_s0_agent_m0_readdata), // .readdata
.uav_writedata (cortex_s0_agent_m0_writedata), // .writedata
.uav_lock (cortex_s0_agent_m0_lock), // .lock
.uav_debugaccess (cortex_s0_agent_m0_debugaccess), // .debugaccess
.av_address (cortex_s0_address), // avalon_anti_slave_0.address
.av_write (cortex_s0_write), // .write
.av_read (cortex_s0_read), // .read
.av_readdata (cortex_s0_readdata), // .readdata
.av_writedata (cortex_s0_writedata), // .writedata
.av_readdatavalid (cortex_s0_readdatavalid), // .readdatavalid
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) timer_0_s1_translator (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (timer_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (timer_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (timer_0_s1_agent_m0_read), // .read
.uav_write (timer_0_s1_agent_m0_write), // .write
.uav_waitrequest (timer_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (timer_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (timer_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (timer_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (timer_0_s1_agent_m0_writedata), // .writedata
.uav_lock (timer_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (timer_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (timer_0_s1_address), // avalon_anti_slave_0.address
.av_write (timer_0_s1_write), // .write
.av_readdata (timer_0_s1_readdata), // .readdata
.av_writedata (timer_0_s1_writedata), // .writedata
.av_chipselect (timer_0_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_s1_translator (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_s1_agent_m0_read), // .read
.uav_write (uart_s1_agent_m0_write), // .write
.uav_waitrequest (uart_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_s1_address), // avalon_anti_slave_0.address
.av_write (uart_s1_write), // .write
.av_read (uart_s1_read), // .read
.av_readdata (uart_s1_readdata), // .readdata
.av_writedata (uart_s1_writedata), // .writedata
.av_begintransfer (uart_s1_begintransfer), // .begintransfer
.av_chipselect (uart_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hdmi_tx_int_n_s1_translator (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hdmi_tx_int_n_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hdmi_tx_int_n_s1_agent_m0_burstcount), // .burstcount
.uav_read (hdmi_tx_int_n_s1_agent_m0_read), // .read
.uav_write (hdmi_tx_int_n_s1_agent_m0_write), // .write
.uav_waitrequest (hdmi_tx_int_n_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hdmi_tx_int_n_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hdmi_tx_int_n_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hdmi_tx_int_n_s1_agent_m0_readdata), // .readdata
.uav_writedata (hdmi_tx_int_n_s1_agent_m0_writedata), // .writedata
.uav_lock (hdmi_tx_int_n_s1_agent_m0_lock), // .lock
.uav_debugaccess (hdmi_tx_int_n_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hdmi_tx_int_n_s1_address), // avalon_anti_slave_0.address
.av_write (hdmi_tx_int_n_s1_write), // .write
.av_readdata (hdmi_tx_int_n_s1_readdata), // .readdata
.av_writedata (hdmi_tx_int_n_s1_writedata), // .writedata
.av_chipselect (hdmi_tx_int_n_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (2),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (22),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (1),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_uas_translator (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_uas_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_uas_agent_m0_burstcount), // .burstcount
.uav_read (sram_uas_agent_m0_read), // .read
.uav_write (sram_uas_agent_m0_write), // .write
.uav_waitrequest (sram_uas_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_uas_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_uas_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_uas_agent_m0_readdata), // .readdata
.uav_writedata (sram_uas_agent_m0_writedata), // .writedata
.uav_lock (sram_uas_agent_m0_lock), // .lock
.uav_debugaccess (sram_uas_agent_m0_debugaccess), // .debugaccess
.av_address (sram_uas_address), // avalon_anti_slave_0.address
.av_write (sram_uas_write), // .write
.av_read (sram_uas_read), // .read
.av_readdata (sram_uas_readdata), // .readdata
.av_writedata (sram_uas_writedata), // .writedata
.av_burstcount (sram_uas_burstcount), // .burstcount
.av_byteenable (sram_uas_byteenable), // .byteenable
.av_readdatavalid (sram_uas_readdatavalid), // .readdatavalid
.av_waitrequest (sram_uas_waitrequest), // .waitrequest
.av_lock (sram_uas_lock), // .lock
.av_debugaccess (sram_uas_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (97),
.PKT_ORI_BURST_SIZE_L (95),
.PKT_RESPONSE_STATUS_H (94),
.PKT_RESPONSE_STATUS_L (93),
.PKT_QOS_H (78),
.PKT_QOS_L (78),
.PKT_DATA_SIDEBAND_H (76),
.PKT_DATA_SIDEBAND_L (76),
.PKT_ADDR_SIDEBAND_H (75),
.PKT_ADDR_SIDEBAND_L (75),
.PKT_BURST_TYPE_H (74),
.PKT_BURST_TYPE_L (73),
.PKT_CACHE_H (92),
.PKT_CACHE_L (89),
.PKT_THREAD_ID_H (85),
.PKT_THREAD_ID_L (85),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_TRANS_EXCLUSIVE (63),
.PKT_TRANS_LOCK (62),
.PKT_BEGIN_BURST (77),
.PKT_PROTECTION_H (88),
.PKT_PROTECTION_L (86),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (67),
.PKT_BYTE_CNT_H (66),
.PKT_BYTE_CNT_L (64),
.PKT_ADDR_H (57),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (58),
.PKT_TRANS_POSTED (59),
.PKT_TRANS_WRITE (60),
.PKT_TRANS_READ (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (81),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (84),
.PKT_DEST_ID_L (82),
.ST_DATA_W (98),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_data_master_agent (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (97),
.PKT_ORI_BURST_SIZE_L (95),
.PKT_RESPONSE_STATUS_H (94),
.PKT_RESPONSE_STATUS_L (93),
.PKT_QOS_H (78),
.PKT_QOS_L (78),
.PKT_DATA_SIDEBAND_H (76),
.PKT_DATA_SIDEBAND_L (76),
.PKT_ADDR_SIDEBAND_H (75),
.PKT_ADDR_SIDEBAND_L (75),
.PKT_BURST_TYPE_H (74),
.PKT_BURST_TYPE_L (73),
.PKT_CACHE_H (92),
.PKT_CACHE_L (89),
.PKT_THREAD_ID_H (85),
.PKT_THREAD_ID_L (85),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_TRANS_EXCLUSIVE (63),
.PKT_TRANS_LOCK (62),
.PKT_BEGIN_BURST (77),
.PKT_PROTECTION_H (88),
.PKT_PROTECTION_L (86),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (67),
.PKT_BYTE_CNT_H (66),
.PKT_BYTE_CNT_L (64),
.PKT_ADDR_H (57),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (58),
.PKT_TRANS_POSTED (59),
.PKT_TRANS_WRITE (60),
.PKT_TRANS_READ (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (81),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (84),
.PKT_DEST_ID_L (82),
.ST_DATA_W (98),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_instruction_master_agent (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (97),
.PKT_ORI_BURST_SIZE_L (95),
.PKT_RESPONSE_STATUS_H (94),
.PKT_RESPONSE_STATUS_L (93),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_TRANS_LOCK (62),
.PKT_BEGIN_BURST (77),
.PKT_PROTECTION_H (88),
.PKT_PROTECTION_L (86),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (67),
.PKT_BYTE_CNT_H (66),
.PKT_BYTE_CNT_L (64),
.PKT_ADDR_H (57),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (58),
.PKT_TRANS_POSTED (59),
.PKT_TRANS_WRITE (60),
.PKT_TRANS_READ (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (81),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (84),
.PKT_DEST_ID_L (82),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (98),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) jtag_uart_0_avalon_jtag_slave_agent (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (99),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (97),
.PKT_ORI_BURST_SIZE_L (95),
.PKT_RESPONSE_STATUS_H (94),
.PKT_RESPONSE_STATUS_L (93),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_TRANS_LOCK (62),
.PKT_BEGIN_BURST (77),
.PKT_PROTECTION_H (88),
.PKT_PROTECTION_L (86),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (67),
.PKT_BYTE_CNT_H (66),
.PKT_BYTE_CNT_L (64),
.PKT_ADDR_H (57),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (58),
.PKT_TRANS_POSTED (59),
.PKT_TRANS_WRITE (60),
.PKT_TRANS_READ (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (81),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (84),
.PKT_DEST_ID_L (82),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (98),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) cpu_debug_mem_slave_agent (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (cpu_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (cpu_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (cpu_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (cpu_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (cpu_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (cpu_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (cpu_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (cpu_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (cpu_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (cpu_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (cpu_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (99),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_debug_mem_slave_agent_rsp_fifo (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (cpu_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (cpu_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (cpu_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (97),
.PKT_ORI_BURST_SIZE_L (95),
.PKT_RESPONSE_STATUS_H (94),
.PKT_RESPONSE_STATUS_L (93),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_TRANS_LOCK (62),
.PKT_BEGIN_BURST (77),
.PKT_PROTECTION_H (88),
.PKT_PROTECTION_L (86),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (67),
.PKT_BYTE_CNT_H (66),
.PKT_BYTE_CNT_L (64),
.PKT_ADDR_H (57),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (58),
.PKT_TRANS_POSTED (59),
.PKT_TRANS_WRITE (60),
.PKT_TRANS_READ (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (81),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (84),
.PKT_DEST_ID_L (82),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (98),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) cortex_s0_agent (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (cortex_s0_agent_m0_address), // m0.address
.m0_burstcount (cortex_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (cortex_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cortex_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (cortex_s0_agent_m0_lock), // .lock
.m0_readdata (cortex_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (cortex_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cortex_s0_agent_m0_read), // .read
.m0_waitrequest (cortex_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cortex_s0_agent_m0_writedata), // .writedata
.m0_write (cortex_s0_agent_m0_write), // .write
.rp_endofpacket (cortex_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cortex_s0_agent_rp_ready), // .ready
.rp_valid (cortex_s0_agent_rp_valid), // .valid
.rp_data (cortex_s0_agent_rp_data), // .data
.rp_startofpacket (cortex_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (cortex_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cortex_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cortex_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cortex_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cortex_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cortex_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cortex_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cortex_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cortex_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cortex_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (cortex_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cortex_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cortex_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (99),
.FIFO_DEPTH (129),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cortex_s0_agent_rsp_fifo (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (cortex_s0_agent_rf_source_data), // in.data
.in_valid (cortex_s0_agent_rf_source_valid), // .valid
.in_ready (cortex_s0_agent_rf_source_ready), // .ready
.in_startofpacket (cortex_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cortex_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (cortex_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (cortex_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (cortex_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cortex_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cortex_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (97),
.PKT_ORI_BURST_SIZE_L (95),
.PKT_RESPONSE_STATUS_H (94),
.PKT_RESPONSE_STATUS_L (93),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_TRANS_LOCK (62),
.PKT_BEGIN_BURST (77),
.PKT_PROTECTION_H (88),
.PKT_PROTECTION_L (86),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (67),
.PKT_BYTE_CNT_H (66),
.PKT_BYTE_CNT_L (64),
.PKT_ADDR_H (57),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (58),
.PKT_TRANS_POSTED (59),
.PKT_TRANS_WRITE (60),
.PKT_TRANS_READ (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (81),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (84),
.PKT_DEST_ID_L (82),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (98),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) timer_0_s1_agent (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (timer_0_s1_agent_m0_address), // m0.address
.m0_burstcount (timer_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (timer_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (timer_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (timer_0_s1_agent_m0_lock), // .lock
.m0_readdata (timer_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (timer_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (timer_0_s1_agent_m0_read), // .read
.m0_waitrequest (timer_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (timer_0_s1_agent_m0_writedata), // .writedata
.m0_write (timer_0_s1_agent_m0_write), // .write
.rp_endofpacket (timer_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (timer_0_s1_agent_rp_ready), // .ready
.rp_valid (timer_0_s1_agent_rp_valid), // .valid
.rp_data (timer_0_s1_agent_rp_data), // .data
.rp_startofpacket (timer_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (timer_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (timer_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (timer_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (timer_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (timer_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (timer_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (timer_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (timer_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (timer_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (timer_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (timer_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (timer_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (timer_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (99),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_0_s1_agent_rsp_fifo (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (timer_0_s1_agent_rf_source_data), // in.data
.in_valid (timer_0_s1_agent_rf_source_valid), // .valid
.in_ready (timer_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (timer_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (timer_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (timer_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (timer_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (timer_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (timer_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (timer_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (97),
.PKT_ORI_BURST_SIZE_L (95),
.PKT_RESPONSE_STATUS_H (94),
.PKT_RESPONSE_STATUS_L (93),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_TRANS_LOCK (62),
.PKT_BEGIN_BURST (77),
.PKT_PROTECTION_H (88),
.PKT_PROTECTION_L (86),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (67),
.PKT_BYTE_CNT_H (66),
.PKT_BYTE_CNT_L (64),
.PKT_ADDR_H (57),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (58),
.PKT_TRANS_POSTED (59),
.PKT_TRANS_WRITE (60),
.PKT_TRANS_READ (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (81),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (84),
.PKT_DEST_ID_L (82),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (98),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_s1_agent (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_s1_agent_m0_lock), // .lock
.m0_readdata (uart_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_s1_agent_m0_read), // .read
.m0_waitrequest (uart_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_s1_agent_m0_writedata), // .writedata
.m0_write (uart_s1_agent_m0_write), // .write
.rp_endofpacket (uart_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_s1_agent_rp_ready), // .ready
.rp_valid (uart_s1_agent_rp_valid), // .valid
.rp_data (uart_s1_agent_rp_data), // .data
.rp_startofpacket (uart_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (uart_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (uart_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (99),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_s1_agent_rsp_fifo (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_s1_agent_rf_source_data), // in.data
.in_valid (uart_s1_agent_rf_source_valid), // .valid
.in_ready (uart_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (97),
.PKT_ORI_BURST_SIZE_L (95),
.PKT_RESPONSE_STATUS_H (94),
.PKT_RESPONSE_STATUS_L (93),
.PKT_BURST_SIZE_H (72),
.PKT_BURST_SIZE_L (70),
.PKT_TRANS_LOCK (62),
.PKT_BEGIN_BURST (77),
.PKT_PROTECTION_H (88),
.PKT_PROTECTION_L (86),
.PKT_BURSTWRAP_H (69),
.PKT_BURSTWRAP_L (67),
.PKT_BYTE_CNT_H (66),
.PKT_BYTE_CNT_L (64),
.PKT_ADDR_H (57),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (58),
.PKT_TRANS_POSTED (59),
.PKT_TRANS_WRITE (60),
.PKT_TRANS_READ (61),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (81),
.PKT_SRC_ID_L (79),
.PKT_DEST_ID_H (84),
.PKT_DEST_ID_L (82),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (98),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hdmi_tx_int_n_s1_agent (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hdmi_tx_int_n_s1_agent_m0_address), // m0.address
.m0_burstcount (hdmi_tx_int_n_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hdmi_tx_int_n_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hdmi_tx_int_n_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hdmi_tx_int_n_s1_agent_m0_lock), // .lock
.m0_readdata (hdmi_tx_int_n_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hdmi_tx_int_n_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hdmi_tx_int_n_s1_agent_m0_read), // .read
.m0_waitrequest (hdmi_tx_int_n_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hdmi_tx_int_n_s1_agent_m0_writedata), // .writedata
.m0_write (hdmi_tx_int_n_s1_agent_m0_write), // .write
.rp_endofpacket (hdmi_tx_int_n_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hdmi_tx_int_n_s1_agent_rp_ready), // .ready
.rp_valid (hdmi_tx_int_n_s1_agent_rp_valid), // .valid
.rp_data (hdmi_tx_int_n_s1_agent_rp_data), // .data
.rp_startofpacket (hdmi_tx_int_n_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (hdmi_tx_int_n_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hdmi_tx_int_n_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hdmi_tx_int_n_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hdmi_tx_int_n_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hdmi_tx_int_n_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hdmi_tx_int_n_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hdmi_tx_int_n_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hdmi_tx_int_n_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hdmi_tx_int_n_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hdmi_tx_int_n_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (hdmi_tx_int_n_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hdmi_tx_int_n_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hdmi_tx_int_n_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (99),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hdmi_tx_int_n_s1_agent_rsp_fifo (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hdmi_tx_int_n_s1_agent_rf_source_data), // in.data
.in_valid (hdmi_tx_int_n_s1_agent_rf_source_valid), // .valid
.in_ready (hdmi_tx_int_n_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hdmi_tx_int_n_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hdmi_tx_int_n_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hdmi_tx_int_n_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hdmi_tx_int_n_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hdmi_tx_int_n_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hdmi_tx_int_n_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hdmi_tx_int_n_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (79),
.PKT_ORI_BURST_SIZE_L (77),
.PKT_RESPONSE_STATUS_H (76),
.PKT_RESPONSE_STATUS_L (75),
.PKT_BURST_SIZE_H (54),
.PKT_BURST_SIZE_L (52),
.PKT_TRANS_LOCK (44),
.PKT_BEGIN_BURST (59),
.PKT_PROTECTION_H (70),
.PKT_PROTECTION_L (68),
.PKT_BURSTWRAP_H (51),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_ADDR_H (39),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_POSTED (41),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (63),
.PKT_SRC_ID_L (61),
.PKT_DEST_ID_H (66),
.PKT_DEST_ID_L (64),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (7),
.ST_DATA_W (80),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sram_uas_agent (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_uas_agent_m0_address), // m0.address
.m0_burstcount (sram_uas_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_uas_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_uas_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_uas_agent_m0_lock), // .lock
.m0_readdata (sram_uas_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_uas_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_uas_agent_m0_read), // .read
.m0_waitrequest (sram_uas_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_uas_agent_m0_writedata), // .writedata
.m0_write (sram_uas_agent_m0_write), // .write
.rp_endofpacket (sram_uas_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_uas_agent_rp_ready), // .ready
.rp_valid (sram_uas_agent_rp_valid), // .valid
.rp_data (sram_uas_agent_rp_data), // .data
.rp_startofpacket (sram_uas_agent_rp_startofpacket), // .startofpacket
.cp_ready (sram_uas_burst_adapter_source0_ready), // cp.ready
.cp_valid (sram_uas_burst_adapter_source0_valid), // .valid
.cp_data (sram_uas_burst_adapter_source0_data), // .data
.cp_startofpacket (sram_uas_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sram_uas_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sram_uas_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sram_uas_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_uas_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_uas_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_uas_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_uas_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_uas_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_uas_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_uas_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_uas_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_uas_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (sram_uas_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_uas_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_uas_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (81),
.FIFO_DEPTH (4),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_uas_agent_rsp_fifo (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_uas_agent_rf_source_data), // in.data
.in_valid (sram_uas_agent_rf_source_valid), // .valid
.in_ready (sram_uas_agent_rf_source_ready), // .ready
.in_startofpacket (sram_uas_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_uas_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_uas_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_uas_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_uas_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_uas_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_uas_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (4),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_uas_agent_rdata_fifo (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_uas_agent_rdata_fifo_src_data), // in.data
.in_valid (sram_uas_agent_rdata_fifo_src_valid), // .valid
.in_ready (sram_uas_agent_rdata_fifo_src_ready), // .ready
.out_data (sram_uas_agent_rdata_fifo_out_data), // out.data
.out_valid (sram_uas_agent_rdata_fifo_out_valid), // .valid
.out_ready (sram_uas_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
limbus_mm_interconnect_0_router router (
.sink_ready (cpu_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_agent_cp_valid), // .valid
.sink_data (cpu_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_router_001 router_001 (
.sink_ready (cpu_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_router_002 router_003 (
.sink_ready (cpu_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (cpu_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (cpu_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (cpu_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_router_004 router_004 (
.sink_ready (cortex_s0_agent_rp_ready), // sink.ready
.sink_valid (cortex_s0_agent_rp_valid), // .valid
.sink_data (cortex_s0_agent_rp_data), // .data
.sink_startofpacket (cortex_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cortex_s0_agent_rp_endofpacket), // .endofpacket
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_router_004 router_005 (
.sink_ready (timer_0_s1_agent_rp_ready), // sink.ready
.sink_valid (timer_0_s1_agent_rp_valid), // .valid
.sink_data (timer_0_s1_agent_rp_data), // .data
.sink_startofpacket (timer_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (timer_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_router_004 router_006 (
.sink_ready (uart_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_s1_agent_rp_valid), // .valid
.sink_data (uart_s1_agent_rp_data), // .data
.sink_startofpacket (uart_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_router_004 router_007 (
.sink_ready (hdmi_tx_int_n_s1_agent_rp_ready), // sink.ready
.sink_valid (hdmi_tx_int_n_s1_agent_rp_valid), // .valid
.sink_data (hdmi_tx_int_n_s1_agent_rp_data), // .data
.sink_startofpacket (hdmi_tx_int_n_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hdmi_tx_int_n_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_router_008 router_008 (
.sink_ready (sram_uas_agent_rp_ready), // sink.ready
.sink_valid (sram_uas_agent_rp_valid), // .valid
.sink_data (sram_uas_agent_rp_data), // .data
.sink_startofpacket (sram_uas_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_uas_agent_rp_endofpacket), // .endofpacket
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (39),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (59),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (46),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (54),
.PKT_BURST_SIZE_L (52),
.PKT_BURST_TYPE_H (56),
.PKT_BURST_TYPE_L (55),
.PKT_BURSTWRAP_H (51),
.PKT_BURSTWRAP_L (49),
.PKT_TRANS_COMPRESSED_READ (40),
.PKT_TRANS_WRITE (42),
.PKT_TRANS_READ (43),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (80),
.ST_CHANNEL_W (7),
.OUT_BYTE_CNT_H (47),
.OUT_BURSTWRAP_H (51),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3),
.ADAPTER_VERSION ("13.1")
) sram_uas_burst_adapter (
.clk (clk_100_clk_clk), // cr0.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (sram_uas_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (sram_uas_cmd_width_adapter_src_data), // .data
.sink0_channel (sram_uas_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (sram_uas_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (sram_uas_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (sram_uas_cmd_width_adapter_src_ready), // .ready
.source0_valid (sram_uas_burst_adapter_source0_valid), // source0.valid
.source0_data (sram_uas_burst_adapter_source0_data), // .data
.source0_channel (sram_uas_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sram_uas_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sram_uas_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sram_uas_burst_adapter_source0_ready) // .ready
);
limbus_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_cmd_mux_002 cmd_mux_004 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_cmd_mux_002 cmd_mux_005 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_rsp_demux_002 rsp_demux_003 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_rsp_demux_002 rsp_demux_004 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_rsp_demux_002 rsp_demux_005 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_rsp_demux rsp_demux_006 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sram_uas_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sram_uas_rsp_width_adapter_src_channel), // .channel
.sink_data (sram_uas_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sram_uas_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sram_uas_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sram_uas_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_006_src1_ready), // src1.ready
.src1_valid (rsp_demux_006_src1_valid), // .valid
.src1_data (rsp_demux_006_src1_data), // .data
.src1_channel (rsp_demux_006_src1_channel), // .channel
.src1_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_006_src1_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
limbus_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_006_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_006_src1_valid), // .valid
.sink2_channel (rsp_demux_006_src1_channel), // .channel
.sink2_data (rsp_demux_006_src1_data), // .data
.sink2_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_006_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (39),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (48),
.IN_PKT_BYTE_CNT_L (46),
.IN_PKT_TRANS_COMPRESSED_READ (40),
.IN_PKT_TRANS_WRITE (42),
.IN_PKT_BURSTWRAP_H (51),
.IN_PKT_BURSTWRAP_L (49),
.IN_PKT_BURST_SIZE_H (54),
.IN_PKT_BURST_SIZE_L (52),
.IN_PKT_RESPONSE_STATUS_H (76),
.IN_PKT_RESPONSE_STATUS_L (75),
.IN_PKT_TRANS_EXCLUSIVE (45),
.IN_PKT_BURST_TYPE_H (56),
.IN_PKT_BURST_TYPE_L (55),
.IN_PKT_ORI_BURST_SIZE_L (77),
.IN_PKT_ORI_BURST_SIZE_H (79),
.IN_ST_DATA_W (80),
.OUT_PKT_ADDR_H (57),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (66),
.OUT_PKT_BYTE_CNT_L (64),
.OUT_PKT_TRANS_COMPRESSED_READ (58),
.OUT_PKT_BURST_SIZE_H (72),
.OUT_PKT_BURST_SIZE_L (70),
.OUT_PKT_RESPONSE_STATUS_H (94),
.OUT_PKT_RESPONSE_STATUS_L (93),
.OUT_PKT_TRANS_EXCLUSIVE (63),
.OUT_PKT_BURST_TYPE_H (74),
.OUT_PKT_BURST_TYPE_L (73),
.OUT_PKT_ORI_BURST_SIZE_L (95),
.OUT_PKT_ORI_BURST_SIZE_H (97),
.OUT_ST_DATA_W (98),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sram_uas_rsp_width_adapter (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_008_src_valid), // sink.valid
.in_channel (router_008_src_channel), // .channel
.in_startofpacket (router_008_src_startofpacket), // .startofpacket
.in_endofpacket (router_008_src_endofpacket), // .endofpacket
.in_ready (router_008_src_ready), // .ready
.in_data (router_008_src_data), // .data
.out_endofpacket (sram_uas_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sram_uas_rsp_width_adapter_src_data), // .data
.out_channel (sram_uas_rsp_width_adapter_src_channel), // .channel
.out_valid (sram_uas_rsp_width_adapter_src_valid), // .valid
.out_ready (sram_uas_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sram_uas_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (57),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (66),
.IN_PKT_BYTE_CNT_L (64),
.IN_PKT_TRANS_COMPRESSED_READ (58),
.IN_PKT_TRANS_WRITE (60),
.IN_PKT_BURSTWRAP_H (69),
.IN_PKT_BURSTWRAP_L (67),
.IN_PKT_BURST_SIZE_H (72),
.IN_PKT_BURST_SIZE_L (70),
.IN_PKT_RESPONSE_STATUS_H (94),
.IN_PKT_RESPONSE_STATUS_L (93),
.IN_PKT_TRANS_EXCLUSIVE (63),
.IN_PKT_BURST_TYPE_H (74),
.IN_PKT_BURST_TYPE_L (73),
.IN_PKT_ORI_BURST_SIZE_L (95),
.IN_PKT_ORI_BURST_SIZE_H (97),
.IN_ST_DATA_W (98),
.OUT_PKT_ADDR_H (39),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (48),
.OUT_PKT_BYTE_CNT_L (46),
.OUT_PKT_TRANS_COMPRESSED_READ (40),
.OUT_PKT_BURST_SIZE_H (54),
.OUT_PKT_BURST_SIZE_L (52),
.OUT_PKT_RESPONSE_STATUS_H (76),
.OUT_PKT_RESPONSE_STATUS_L (75),
.OUT_PKT_TRANS_EXCLUSIVE (45),
.OUT_PKT_BURST_TYPE_H (56),
.OUT_PKT_BURST_TYPE_L (55),
.OUT_PKT_ORI_BURST_SIZE_L (77),
.OUT_PKT_ORI_BURST_SIZE_H (79),
.OUT_ST_DATA_W (80),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sram_uas_cmd_width_adapter (
.clk (clk_100_clk_clk), // clk.clk
.reset (cpu_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_006_src_valid), // sink.valid
.in_channel (cmd_mux_006_src_channel), // .channel
.in_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_006_src_ready), // .ready
.in_data (cmd_mux_006_src_data), // .data
.out_endofpacket (sram_uas_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sram_uas_cmd_width_adapter_src_data), // .data
.out_channel (sram_uas_cmd_width_adapter_src_channel), // .channel
.out_valid (sram_uas_cmd_width_adapter_src_valid), // .valid
.out_ready (sram_uas_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sram_uas_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
limbus_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (clk_100_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
limbus_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (clk_100_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (cpu_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (cpu_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (cpu_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
limbus_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (clk_100_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (cortex_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (cortex_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (cortex_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
limbus_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (clk_100_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (timer_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (timer_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (timer_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
limbus_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (clk_100_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
limbus_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (clk_100_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hdmi_tx_int_n_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hdmi_tx_int_n_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hdmi_tx_int_n_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
limbus_mm_interconnect_0_avalon_st_adapter_006 #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (clk_100_clk_clk), // in_clk_0.clk
.in_rst_0_reset (cpu_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sram_uas_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (sram_uas_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (sram_uas_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ecb_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ecb_e.v,v 1.1 2004/04/06 10:50:51 wig Exp $
// $Date: 2004/04/06 10:50:51 $
// $Log: inst_ecb_e.v,v $
// Revision 1.1 2004/04/06 10:50:51 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ecb_e
//
// No `defines in this module
module inst_ecb_e
//
// Generated module inst_ecb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ecb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// Generated by PCI Express Compiler 10.1 [Altera, IP Toolbench 1.3.0 Build 197]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module pcie_hip_s4gx_gen2_x4_128_core (
AvlClk_i,
CraAddress_i,
CraByteEnable_i,
CraChipSelect_i,
CraRead,
CraWrite,
CraWriteData_i,
Rstn_i,
RxmIrqNum_i,
RxmIrq_i,
RxmReadDataValid_i,
RxmReadData_i,
RxmWaitRequest_i,
TxsAddress_i,
TxsBurstCount_i,
TxsByteEnable_i,
TxsChipSelect_i,
TxsRead_i,
TxsWriteData_i,
TxsWrite_i,
aer_msi_num,
app_int_sts,
app_msi_num,
app_msi_req,
app_msi_tc,
core_clk_in,
cpl_err,
cpl_pending,
crst,
hpg_ctrler,
lmi_addr,
lmi_din,
lmi_rden,
lmi_wren,
npor,
pclk_central,
pclk_ch0,
pex_msi_num,
pld_clk,
pll_fixed_clk,
pm_auxpwr,
pm_data,
pm_event,
pme_to_cr,
rc_areset,
rc_inclk_eq_125mhz,
rc_pll_locked,
rc_rx_pll_locked_one,
rx_st_mask0,
rx_st_ready0,
srst,
test_in,
tx_st_data0,
tx_st_data0_p1,
tx_st_eop0,
tx_st_eop0_p1,
tx_st_err0,
tx_st_sop0,
tx_st_sop0_p1,
tx_st_valid0,
phystatus0_ext,
rxdata0_ext,
rxdatak0_ext,
rxelecidle0_ext,
rxstatus0_ext,
rxvalid0_ext,
phystatus1_ext,
rxdata1_ext,
rxdatak1_ext,
rxelecidle1_ext,
rxstatus1_ext,
rxvalid1_ext,
phystatus2_ext,
rxdata2_ext,
rxdatak2_ext,
rxelecidle2_ext,
rxstatus2_ext,
rxvalid2_ext,
phystatus3_ext,
rxdata3_ext,
rxdatak3_ext,
rxelecidle3_ext,
rxstatus3_ext,
rxvalid3_ext,
CraIrq_o,
CraReadData_o,
CraWaitRequest_o,
RxmAddress_o,
RxmBurstCount_o,
RxmByteEnable_o,
RxmRead_o,
RxmWriteData_o,
RxmWrite_o,
TxsReadDataValid_o,
TxsReadData_o,
TxsWaitRequest_o,
app_int_ack,
app_msi_ack,
avs_pcie_reconfig_readdata,
avs_pcie_reconfig_readdatavalid,
avs_pcie_reconfig_waitrequest,
core_clk_out,
derr_cor_ext_rcv0,
derr_cor_ext_rpl,
derr_rpl,
dl_ltssm,
dlup_exit,
eidle_infer_sel,
ev_128ns,
ev_1us,
hip_extraclkout,
hotrst_exit,
int_status,
l2_exit,
lane_act,
lmi_ack,
lmi_dout,
npd_alloc_1cred_vc0,
npd_cred_vio_vc0,
nph_alloc_1cred_vc0,
nph_cred_vio_vc0,
pme_to_sr,
r2c_err0,
rate_ext,
rc_gxb_powerdown,
rc_rx_analogreset,
rc_rx_digitalreset,
rc_tx_digitalreset,
reset_status,
rx_fifo_empty0,
rx_fifo_full0,
rx_st_bardec0,
rx_st_be0,
rx_st_be0_p1,
rx_st_data0,
rx_st_data0_p1,
rx_st_eop0,
rx_st_eop0_p1,
rx_st_err0,
rx_st_sop0,
rx_st_sop0_p1,
rx_st_valid0,
serr_out,
suc_spd_neg,
swdn_wake,
swup_hotrst,
test_out,
tl_cfg_add,
tl_cfg_ctl,
tl_cfg_ctl_wr,
tl_cfg_sts,
tl_cfg_sts_wr,
tx_cred0,
tx_deemph,
tx_fifo_empty0,
tx_fifo_full0,
tx_fifo_rdptr0,
tx_fifo_wrptr0,
tx_margin,
tx_st_ready0,
use_pcie_reconfig,
wake_oen,
powerdown0_ext,
rxpolarity0_ext,
txcompl0_ext,
txdata0_ext,
txdatak0_ext,
txdetectrx0_ext,
txelecidle0_ext,
powerdown1_ext,
rxpolarity1_ext,
txcompl1_ext,
txdata1_ext,
txdatak1_ext,
txdetectrx1_ext,
txelecidle1_ext,
powerdown2_ext,
rxpolarity2_ext,
txcompl2_ext,
txdata2_ext,
txdatak2_ext,
txdetectrx2_ext,
txelecidle2_ext,
powerdown3_ext,
rxpolarity3_ext,
txcompl3_ext,
txdata3_ext,
txdatak3_ext,
txdetectrx3_ext,
txelecidle3_ext);
input AvlClk_i;
input [11:0] CraAddress_i;
input [3:0] CraByteEnable_i;
input CraChipSelect_i;
input CraRead;
input CraWrite;
input [31:0] CraWriteData_i;
input Rstn_i;
input [5:0] RxmIrqNum_i;
input RxmIrq_i;
input RxmReadDataValid_i;
input [63:0] RxmReadData_i;
input RxmWaitRequest_i;
input [16:0] TxsAddress_i;
input [9:0] TxsBurstCount_i;
input [7:0] TxsByteEnable_i;
input TxsChipSelect_i;
input TxsRead_i;
input [63:0] TxsWriteData_i;
input TxsWrite_i;
input [4:0] aer_msi_num;
input app_int_sts;
input [4:0] app_msi_num;
input app_msi_req;
input [2:0] app_msi_tc;
input core_clk_in;
input [6:0] cpl_err;
input cpl_pending;
input crst;
input [4:0] hpg_ctrler;
input [11:0] lmi_addr;
input [31:0] lmi_din;
input lmi_rden;
input lmi_wren;
input npor;
input pclk_central;
input pclk_ch0;
input [4:0] pex_msi_num;
input pld_clk;
input pll_fixed_clk;
input pm_auxpwr;
input [9:0] pm_data;
input pm_event;
input pme_to_cr;
input rc_areset;
input rc_inclk_eq_125mhz;
input rc_pll_locked;
input rc_rx_pll_locked_one;
input rx_st_mask0;
input rx_st_ready0;
input srst;
input [39:0] test_in;
input [63:0] tx_st_data0;
input [63:0] tx_st_data0_p1;
input tx_st_eop0;
input tx_st_eop0_p1;
input tx_st_err0;
input tx_st_sop0;
input tx_st_sop0_p1;
input tx_st_valid0;
input phystatus0_ext;
input [7:0] rxdata0_ext;
input rxdatak0_ext;
input rxelecidle0_ext;
input [2:0] rxstatus0_ext;
input rxvalid0_ext;
input phystatus1_ext;
input [7:0] rxdata1_ext;
input rxdatak1_ext;
input rxelecidle1_ext;
input [2:0] rxstatus1_ext;
input rxvalid1_ext;
input phystatus2_ext;
input [7:0] rxdata2_ext;
input rxdatak2_ext;
input rxelecidle2_ext;
input [2:0] rxstatus2_ext;
input rxvalid2_ext;
input phystatus3_ext;
input [7:0] rxdata3_ext;
input rxdatak3_ext;
input rxelecidle3_ext;
input [2:0] rxstatus3_ext;
input rxvalid3_ext;
output CraIrq_o;
output [31:0] CraReadData_o;
output CraWaitRequest_o;
output [31:0] RxmAddress_o;
output [9:0] RxmBurstCount_o;
output [7:0] RxmByteEnable_o;
output RxmRead_o;
output [63:0] RxmWriteData_o;
output RxmWrite_o;
output TxsReadDataValid_o;
output [63:0] TxsReadData_o;
output TxsWaitRequest_o;
output app_int_ack;
output app_msi_ack;
output [15:0] avs_pcie_reconfig_readdata;
output avs_pcie_reconfig_readdatavalid;
output avs_pcie_reconfig_waitrequest;
output core_clk_out;
output derr_cor_ext_rcv0;
output derr_cor_ext_rpl;
output derr_rpl;
output [4:0] dl_ltssm;
output dlup_exit;
output [23:0] eidle_infer_sel;
output ev_128ns;
output ev_1us;
output [1:0] hip_extraclkout;
output hotrst_exit;
output [3:0] int_status;
output l2_exit;
output [3:0] lane_act;
output lmi_ack;
output [31:0] lmi_dout;
output npd_alloc_1cred_vc0;
output npd_cred_vio_vc0;
output nph_alloc_1cred_vc0;
output nph_cred_vio_vc0;
output pme_to_sr;
output r2c_err0;
output rate_ext;
output rc_gxb_powerdown;
output rc_rx_analogreset;
output rc_rx_digitalreset;
output rc_tx_digitalreset;
output reset_status;
output rx_fifo_empty0;
output rx_fifo_full0;
output [7:0] rx_st_bardec0;
output [7:0] rx_st_be0;
output [7:0] rx_st_be0_p1;
output [63:0] rx_st_data0;
output [63:0] rx_st_data0_p1;
output rx_st_eop0;
output rx_st_eop0_p1;
output rx_st_err0;
output rx_st_sop0;
output rx_st_sop0_p1;
output rx_st_valid0;
output serr_out;
output suc_spd_neg;
output swdn_wake;
output swup_hotrst;
output [63:0] test_out;
output [3:0] tl_cfg_add;
output [31:0] tl_cfg_ctl;
output tl_cfg_ctl_wr;
output [52:0] tl_cfg_sts;
output tl_cfg_sts_wr;
output [35:0] tx_cred0;
output [7:0] tx_deemph;
output tx_fifo_empty0;
output tx_fifo_full0;
output [3:0] tx_fifo_rdptr0;
output [3:0] tx_fifo_wrptr0;
output [23:0] tx_margin;
output tx_st_ready0;
output use_pcie_reconfig;
output wake_oen;
output [1:0] powerdown0_ext;
output rxpolarity0_ext;
output txcompl0_ext;
output [7:0] txdata0_ext;
output txdatak0_ext;
output txdetectrx0_ext;
output txelecidle0_ext;
output [1:0] powerdown1_ext;
output rxpolarity1_ext;
output txcompl1_ext;
output [7:0] txdata1_ext;
output txdatak1_ext;
output txdetectrx1_ext;
output txelecidle1_ext;
output [1:0] powerdown2_ext;
output rxpolarity2_ext;
output txcompl2_ext;
output [7:0] txdata2_ext;
output txdatak2_ext;
output txdetectrx2_ext;
output txelecidle2_ext;
output [1:0] powerdown3_ext;
output rxpolarity3_ext;
output txcompl3_ext;
output [7:0] txdata3_ext;
output txdatak3_ext;
output txdetectrx3_ext;
output txelecidle3_ext;
wire [7:0] signal_wire0 = 8'b0;
wire signal_wire1 = 1'b0;
wire signal_wire2 = 1'b0;
wire signal_wire3 = 1'b0;
wire signal_wire4 = 1'b0;
wire signal_wire5 = 1'b0;
wire [15:0] signal_wire6 = 16'b0;
wire [1:0] signal_wire7 = 2'b0;
wire [2:0] signal_wire8 = 3'b0;
wire [6:0] signal_wire9 = 7'b0;
wire signal_wire10 = 1'b1;
wire signal_wire11 = 1'b0;
wire signal_wire12 = 1'b0;
wire [12:0] signal_wire13 = 13'b0;
wire [11:0] signal_wire14 = 12'b0;
wire [7:0] signal_wire15 = 8'b0;
wire signal_wire16 = 1'b0;
wire [2:0] signal_wire17 = 3'b0;
wire [3:0] signal_wire18 = 4'b0;
wire [3:0] signal_wire19 = 4'b0;
wire signal_wire20 = 1'b0;
wire signal_wire21 = 1'b0;
wire signal_wire22 = 1'b0;
wire signal_wire23 = 1'b0;
wire signal_wire24 = 1'b0;
wire [2:0] signal_wire25 = 3'b0;
wire signal_wire26 = 1'b0;
wire [1:0] signal_wire27 = 2'b0;
wire [7:0] signal_wire28 = 8'b0;
wire [23:0] signal_wire29 = 24'b0;
wire [2:0] signal_wire30 = 3'b0;
wire signal_wire31 = 1'b0;
wire signal_wire32 = 1'b0;
wire [63:0] signal_wire33 = 64'b0;
wire [63:0] signal_wire34 = 64'b0;
wire signal_wire35 = 1'b0;
wire signal_wire36 = 1'b0;
wire signal_wire37 = 1'b0;
wire signal_wire38 = 1'b0;
wire signal_wire39 = 1'b0;
wire signal_wire40 = 1'b0;
wire signal_wire41 = 1'b0;
wire [7:0] signal_wire42 = 8'b0;
wire signal_wire43 = 1'b0;
wire signal_wire44 = 1'b0;
wire [2:0] signal_wire45 = 3'b0;
wire signal_wire46 = 1'b0;
wire signal_wire47 = 1'b0;
wire [7:0] signal_wire48 = 8'b0;
wire signal_wire49 = 1'b0;
wire signal_wire50 = 1'b0;
wire [2:0] signal_wire51 = 3'b0;
wire signal_wire52 = 1'b0;
wire signal_wire53 = 1'b0;
wire [7:0] signal_wire54 = 8'b0;
wire signal_wire55 = 1'b0;
wire signal_wire56 = 1'b0;
wire [2:0] signal_wire57 = 3'b0;
wire signal_wire58 = 1'b0;
wire signal_wire59 = 1'b0;
wire [7:0] signal_wire60 = 8'b0;
wire signal_wire61 = 1'b0;
wire signal_wire62 = 1'b0;
wire [2:0] signal_wire63 = 3'b0;
wire signal_wire64 = 1'b0;
altpcie_hip_pipen1b altpcie_hip_pipen1b_inst(
.AvlClk_i(AvlClk_i),
.CraAddress_i(CraAddress_i),
.CraByteEnable_i(CraByteEnable_i),
.CraChipSelect_i(CraChipSelect_i),
.CraRead(CraRead),
.CraWrite(CraWrite),
.CraWriteData_i(CraWriteData_i),
.Rstn_i(Rstn_i),
.RxmIrqNum_i(RxmIrqNum_i),
.RxmIrq_i(RxmIrq_i),
.RxmReadDataValid_i(RxmReadDataValid_i),
.RxmReadData_i(RxmReadData_i),
.RxmWaitRequest_i(RxmWaitRequest_i),
.TxsAddress_i(TxsAddress_i),
.TxsBurstCount_i(TxsBurstCount_i),
.TxsByteEnable_i(TxsByteEnable_i),
.TxsChipSelect_i(TxsChipSelect_i),
.TxsRead_i(TxsRead_i),
.TxsWriteData_i(TxsWriteData_i),
.TxsWrite_i(TxsWrite_i),
.aer_msi_num(aer_msi_num),
.app_int_sts(app_int_sts),
.app_msi_num(app_msi_num),
.app_msi_req(app_msi_req),
.app_msi_tc(app_msi_tc),
.avs_pcie_reconfig_address(signal_wire0),
.avs_pcie_reconfig_chipselect(signal_wire1),
.avs_pcie_reconfig_clk(signal_wire2),
.avs_pcie_reconfig_read(signal_wire3),
.avs_pcie_reconfig_rstn(signal_wire4),
.avs_pcie_reconfig_write(signal_wire5),
.avs_pcie_reconfig_writedata(signal_wire6),
.core_clk_in(core_clk_in),
.cpl_err(cpl_err),
.cpl_pending(cpl_pending),
.crst(crst),
.hpg_ctrler(hpg_ctrler),
.lmi_addr(lmi_addr),
.lmi_din(lmi_din),
.lmi_rden(lmi_rden),
.lmi_wren(lmi_wren),
.mode(signal_wire7),
.npor(npor),
.pclk_central(pclk_central),
.pclk_ch0(pclk_ch0),
.pex_msi_num(pex_msi_num),
.pld_clk(pld_clk),
.pll_fixed_clk(pll_fixed_clk),
.pm_auxpwr(pm_auxpwr),
.pm_data(pm_data),
.pm_event(pm_event),
.pme_to_cr(pme_to_cr),
.rc_areset(rc_areset),
.rc_inclk_eq_125mhz(rc_inclk_eq_125mhz),
.rc_pll_locked(rc_pll_locked),
.rc_rx_pll_locked_one(rc_rx_pll_locked_one),
.rx_st_mask0(rx_st_mask0),
.rx_st_ready0(rx_st_ready0),
.srst(srst),
.swdn_in(signal_wire8),
.swup_in(signal_wire9),
.test_in(test_in),
.tl_slotclk_cfg(signal_wire10),
.tlbp_dl_aspm_cr0(signal_wire11),
.tlbp_dl_comclk_reg(signal_wire12),
.tlbp_dl_ctrl_link2(signal_wire13),
.tlbp_dl_data_upfc(signal_wire14),
.tlbp_dl_hdr_upfc(signal_wire15),
.tlbp_dl_inh_dllp(signal_wire16),
.tlbp_dl_maxpload_dcr(signal_wire17),
.tlbp_dl_req_phycfg(signal_wire18),
.tlbp_dl_req_phypm(signal_wire19),
.tlbp_dl_req_upfc(signal_wire20),
.tlbp_dl_req_wake(signal_wire21),
.tlbp_dl_rx_ecrcchk(signal_wire22),
.tlbp_dl_snd_upfc(signal_wire23),
.tlbp_dl_tx_reqpm(signal_wire24),
.tlbp_dl_tx_typpm(signal_wire25),
.tlbp_dl_txcfg_extsy(signal_wire26),
.tlbp_dl_typ_upfc(signal_wire27),
.tlbp_dl_vc_ctrl(signal_wire28),
.tlbp_dl_vcid_map(signal_wire29),
.tlbp_dl_vcid_upfc(signal_wire30),
.tx_st_data0(tx_st_data0),
.tx_st_data0_p1(tx_st_data0_p1),
.tx_st_eop0(tx_st_eop0),
.tx_st_eop0_p1(tx_st_eop0_p1),
.tx_st_err0(tx_st_err0),
.tx_st_sop0(tx_st_sop0),
.tx_st_sop0_p1(tx_st_sop0_p1),
.tx_st_valid0(tx_st_valid0),
.rx_st_mask1(signal_wire31),
.rx_st_ready1(signal_wire32),
.tx_st_data1(signal_wire33),
.tx_st_data1_p1(signal_wire34),
.tx_st_eop1(signal_wire35),
.tx_st_eop1_p1(signal_wire36),
.tx_st_err1(signal_wire37),
.tx_st_sop1(signal_wire38),
.tx_st_sop1_p1(signal_wire39),
.tx_st_valid1(signal_wire40),
.phystatus0_ext(phystatus0_ext),
.rxdata0_ext(rxdata0_ext),
.rxdatak0_ext(rxdatak0_ext),
.rxelecidle0_ext(rxelecidle0_ext),
.rxstatus0_ext(rxstatus0_ext),
.rxvalid0_ext(rxvalid0_ext),
.phystatus1_ext(phystatus1_ext),
.rxdata1_ext(rxdata1_ext),
.rxdatak1_ext(rxdatak1_ext),
.rxelecidle1_ext(rxelecidle1_ext),
.rxstatus1_ext(rxstatus1_ext),
.rxvalid1_ext(rxvalid1_ext),
.phystatus2_ext(phystatus2_ext),
.rxdata2_ext(rxdata2_ext),
.rxdatak2_ext(rxdatak2_ext),
.rxelecidle2_ext(rxelecidle2_ext),
.rxstatus2_ext(rxstatus2_ext),
.rxvalid2_ext(rxvalid2_ext),
.phystatus3_ext(phystatus3_ext),
.rxdata3_ext(rxdata3_ext),
.rxdatak3_ext(rxdatak3_ext),
.rxelecidle3_ext(rxelecidle3_ext),
.rxstatus3_ext(rxstatus3_ext),
.rxvalid3_ext(rxvalid3_ext),
.phystatus4_ext(signal_wire41),
.rxdata4_ext(signal_wire42),
.rxdatak4_ext(signal_wire43),
.rxelecidle4_ext(signal_wire44),
.rxstatus4_ext(signal_wire45),
.rxvalid4_ext(signal_wire46),
.phystatus5_ext(signal_wire47),
.rxdata5_ext(signal_wire48),
.rxdatak5_ext(signal_wire49),
.rxelecidle5_ext(signal_wire50),
.rxstatus5_ext(signal_wire51),
.rxvalid5_ext(signal_wire52),
.phystatus6_ext(signal_wire53),
.rxdata6_ext(signal_wire54),
.rxdatak6_ext(signal_wire55),
.rxelecidle6_ext(signal_wire56),
.rxstatus6_ext(signal_wire57),
.rxvalid6_ext(signal_wire58),
.phystatus7_ext(signal_wire59),
.rxdata7_ext(signal_wire60),
.rxdatak7_ext(signal_wire61),
.rxelecidle7_ext(signal_wire62),
.rxstatus7_ext(signal_wire63),
.rxvalid7_ext(signal_wire64),
.CraIrq_o(CraIrq_o),
.CraReadData_o(CraReadData_o),
.CraWaitRequest_o(CraWaitRequest_o),
.RxmAddress_o(RxmAddress_o),
.RxmBurstCount_o(RxmBurstCount_o),
.RxmByteEnable_o(RxmByteEnable_o),
.RxmRead_o(RxmRead_o),
.RxmWriteData_o(RxmWriteData_o),
.RxmWrite_o(RxmWrite_o),
.TxsReadDataValid_o(TxsReadDataValid_o),
.TxsReadData_o(TxsReadData_o),
.TxsWaitRequest_o(TxsWaitRequest_o),
.app_int_ack(app_int_ack),
.app_msi_ack(app_msi_ack),
.avs_pcie_reconfig_readdata(avs_pcie_reconfig_readdata),
.avs_pcie_reconfig_readdatavalid(avs_pcie_reconfig_readdatavalid),
.avs_pcie_reconfig_waitrequest(avs_pcie_reconfig_waitrequest),
.core_clk_out(core_clk_out),
.derr_cor_ext_rcv0(derr_cor_ext_rcv0),
.derr_cor_ext_rpl(derr_cor_ext_rpl),
.derr_rpl(derr_rpl),
.dl_ltssm(dl_ltssm),
.dlup_exit(dlup_exit),
.eidle_infer_sel(eidle_infer_sel),
.ev_128ns(ev_128ns),
.ev_1us(ev_1us),
.hip_extraclkout(hip_extraclkout),
.hotrst_exit(hotrst_exit),
.int_status(int_status),
.l2_exit(l2_exit),
.lane_act(lane_act),
.lmi_ack(lmi_ack),
.lmi_dout(lmi_dout),
.npd_alloc_1cred_vc0(npd_alloc_1cred_vc0),
.npd_cred_vio_vc0(npd_cred_vio_vc0),
.nph_alloc_1cred_vc0(nph_alloc_1cred_vc0),
.nph_cred_vio_vc0(nph_cred_vio_vc0),
.pme_to_sr(pme_to_sr),
.r2c_err0(r2c_err0),
.rate_ext(rate_ext),
.rc_gxb_powerdown(rc_gxb_powerdown),
.rc_rx_analogreset(rc_rx_analogreset),
.rc_rx_digitalreset(rc_rx_digitalreset),
.rc_tx_digitalreset(rc_tx_digitalreset),
.reset_status(reset_status),
.rx_fifo_empty0(rx_fifo_empty0),
.rx_fifo_full0(rx_fifo_full0),
.rx_st_bardec0(rx_st_bardec0),
.rx_st_be0(rx_st_be0),
.rx_st_be0_p1(rx_st_be0_p1),
.rx_st_data0(rx_st_data0),
.rx_st_data0_p1(rx_st_data0_p1),
.rx_st_eop0(rx_st_eop0),
.rx_st_eop0_p1(rx_st_eop0_p1),
.rx_st_err0(rx_st_err0),
.rx_st_sop0(rx_st_sop0),
.rx_st_sop0_p1(rx_st_sop0_p1),
.rx_st_valid0(rx_st_valid0),
.serr_out(serr_out),
.suc_spd_neg(suc_spd_neg),
.swdn_wake(swdn_wake),
.swup_hotrst(swup_hotrst),
.test_out(test_out),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_ctl_wr(tl_cfg_ctl_wr),
.tl_cfg_sts(tl_cfg_sts),
.tl_cfg_sts_wr(tl_cfg_sts_wr),
.tlbp_dl_ack_phypm(),
.tlbp_dl_ack_requpfc(),
.tlbp_dl_ack_sndupfc(),
.tlbp_dl_current_deemp(),
.tlbp_dl_currentspeed(),
.tlbp_dl_dll_req(),
.tlbp_dl_err_dll(),
.tlbp_dl_errphy(),
.tlbp_dl_link_autobdw_status(),
.tlbp_dl_link_bdwmng_status(),
.tlbp_dl_rpbuf_emp(),
.tlbp_dl_rst_enter_comp_bit(),
.tlbp_dl_rst_tx_margin_field(),
.tlbp_dl_rx_typ_pm(),
.tlbp_dl_rx_valpm(),
.tlbp_dl_tx_ackpm(),
.tlbp_dl_up(),
.tlbp_dl_vc_status(),
.tlbp_link_up(),
.tx_cred0(tx_cred0),
.tx_deemph(tx_deemph),
.tx_fifo_empty0(tx_fifo_empty0),
.tx_fifo_full0(tx_fifo_full0),
.tx_fifo_rdptr0(tx_fifo_rdptr0),
.tx_fifo_wrptr0(tx_fifo_wrptr0),
.tx_margin(tx_margin),
.tx_st_ready0(tx_st_ready0),
.use_pcie_reconfig(use_pcie_reconfig),
.wake_oen(wake_oen),
.derr_cor_ext_rcv1(),
.npd_alloc_1cred_vc1(),
.npd_cred_vio_vc1(),
.nph_alloc_1cred_vc1(),
.nph_cred_vio_vc1(),
.r2c_err1(),
.rx_fifo_empty1(),
.rx_fifo_full1(),
.rx_st_bardec1(),
.rx_st_be1(),
.rx_st_be1_p1(),
.rx_st_data1(),
.rx_st_data1_p1(),
.rx_st_eop1(),
.rx_st_eop1_p1(),
.rx_st_err1(),
.rx_st_sop1(),
.rx_st_sop1_p1(),
.rx_st_valid1(),
.tx_cred1(),
.tx_fifo_empty1(),
.tx_fifo_full1(),
.tx_fifo_rdptr1(),
.tx_fifo_wrptr1(),
.tx_st_ready1(),
.powerdown0_ext(powerdown0_ext),
.rxpolarity0_ext(rxpolarity0_ext),
.txcompl0_ext(txcompl0_ext),
.txdata0_ext(txdata0_ext),
.txdatak0_ext(txdatak0_ext),
.txdetectrx0_ext(txdetectrx0_ext),
.txelecidle0_ext(txelecidle0_ext),
.powerdown1_ext(powerdown1_ext),
.rxpolarity1_ext(rxpolarity1_ext),
.txcompl1_ext(txcompl1_ext),
.txdata1_ext(txdata1_ext),
.txdatak1_ext(txdatak1_ext),
.txdetectrx1_ext(txdetectrx1_ext),
.txelecidle1_ext(txelecidle1_ext),
.powerdown2_ext(powerdown2_ext),
.rxpolarity2_ext(rxpolarity2_ext),
.txcompl2_ext(txcompl2_ext),
.txdata2_ext(txdata2_ext),
.txdatak2_ext(txdatak2_ext),
.txdetectrx2_ext(txdetectrx2_ext),
.txelecidle2_ext(txelecidle2_ext),
.powerdown3_ext(powerdown3_ext),
.rxpolarity3_ext(rxpolarity3_ext),
.txcompl3_ext(txcompl3_ext),
.txdata3_ext(txdata3_ext),
.txdatak3_ext(txdatak3_ext),
.txdetectrx3_ext(txdetectrx3_ext),
.txelecidle3_ext(txelecidle3_ext),
.powerdown4_ext(),
.rxpolarity4_ext(),
.txcompl4_ext(),
.txdata4_ext(),
.txdatak4_ext(),
.txdetectrx4_ext(),
.txelecidle4_ext(),
.powerdown5_ext(),
.rxpolarity5_ext(),
.txcompl5_ext(),
.txdata5_ext(),
.txdatak5_ext(),
.txdetectrx5_ext(),
.txelecidle5_ext(),
.powerdown6_ext(),
.rxpolarity6_ext(),
.txcompl6_ext(),
.txdata6_ext(),
.txdatak6_ext(),
.txdetectrx6_ext(),
.txelecidle6_ext(),
.powerdown7_ext(),
.rxpolarity7_ext(),
.txcompl7_ext(),
.txdata7_ext(),
.txdatak7_ext(),
.txdetectrx7_ext(),
.txelecidle7_ext());
defparam
altpcie_hip_pipen1b_inst.p_pcie_hip_type = "0",
altpcie_hip_pipen1b_inst.retry_buffer_last_active_address = "2047",
altpcie_hip_pipen1b_inst.advanced_errors = "false",
altpcie_hip_pipen1b_inst.bar0_io_space = "false",
altpcie_hip_pipen1b_inst.bar0_64bit_mem_space = "false",
altpcie_hip_pipen1b_inst.bar0_prefetchable = "false",
altpcie_hip_pipen1b_inst.bar0_size_mask = 24,
altpcie_hip_pipen1b_inst.bar1_io_space = "false",
altpcie_hip_pipen1b_inst.bar1_64bit_mem_space = "false",
altpcie_hip_pipen1b_inst.bar1_prefetchable = "false",
altpcie_hip_pipen1b_inst.bar1_size_mask = 16,
altpcie_hip_pipen1b_inst.enable_ecrc_check = "false",
altpcie_hip_pipen1b_inst.enable_ecrc_gen = "false",
altpcie_hip_pipen1b_inst.enable_l1_aspm = "false",
altpcie_hip_pipen1b_inst.l01_entry_latency = 31,
altpcie_hip_pipen1b_inst.pcie_mode = "SHARED_MODE",
altpcie_hip_pipen1b_inst.extend_tag_field = "false",
altpcie_hip_pipen1b_inst.bypass_cdc = "false",
altpcie_hip_pipen1b_inst.vc_arbitration = 0,
altpcie_hip_pipen1b_inst.no_soft_reset = "true",
altpcie_hip_pipen1b_inst.enable_ch0_pclk_out = "false",
altpcie_hip_pipen1b_inst.core_clk_divider = 2,
altpcie_hip_pipen1b_inst.millisecond_cycle_count = 250000,
altpcie_hip_pipen1b_inst.max_link_width = 4,
altpcie_hip_pipen1b_inst.lane_mask = 8'b11110000,
altpcie_hip_pipen1b_inst.single_rx_detect = 4,
altpcie_hip_pipen1b_inst.enable_adapter_half_rate_mode = "true",
altpcie_hip_pipen1b_inst.enable_coreclk_out_half_rate = "true",
altpcie_hip_pipen1b_inst.enable_gen2_core = "true",
altpcie_hip_pipen1b_inst.gen2_lane_rate_mode = "true",
altpcie_hip_pipen1b_inst.vendor_id = 4334,
altpcie_hip_pipen1b_inst.device_id = 16963,
altpcie_hip_pipen1b_inst.revision_id = 17,
altpcie_hip_pipen1b_inst.class_code = 327680,
altpcie_hip_pipen1b_inst.subsystem_vendor_id = 4334,
altpcie_hip_pipen1b_inst.subsystem_device_id = 7,
altpcie_hip_pipen1b_inst.port_link_number = 1,
altpcie_hip_pipen1b_inst.max_payload_size = 1,
altpcie_hip_pipen1b_inst.msi_function_count = 2,
altpcie_hip_pipen1b_inst.endpoint_l0_latency = 0,
altpcie_hip_pipen1b_inst.endpoint_l1_latency = 0,
altpcie_hip_pipen1b_inst.diffclock_nfts_count = 255,
altpcie_hip_pipen1b_inst.sameclock_nfts_count = 255,
altpcie_hip_pipen1b_inst.l1_exit_latency_sameclock = 7,
altpcie_hip_pipen1b_inst.l1_exit_latency_diffclock = 7,
altpcie_hip_pipen1b_inst.l0_exit_latency_sameclock = 7,
altpcie_hip_pipen1b_inst.l0_exit_latency_diffclock = 7,
altpcie_hip_pipen1b_inst.enable_msi_64bit_addressing = "true",
altpcie_hip_pipen1b_inst.gen2_diffclock_nfts_count = 255,
altpcie_hip_pipen1b_inst.gen2_sameclock_nfts_count = 255,
altpcie_hip_pipen1b_inst.enable_function_msix_support = "false",
altpcie_hip_pipen1b_inst.credit_buffer_allocation_aux = "BALANCED",
altpcie_hip_pipen1b_inst.eie_before_nfts_count = 4,
altpcie_hip_pipen1b_inst.completion_timeout = "NONE",
altpcie_hip_pipen1b_inst.enable_completion_timeout_disable = "true",
altpcie_hip_pipen1b_inst.msix_pba_bir = 0,
altpcie_hip_pipen1b_inst.msix_pba_offset = 0,
altpcie_hip_pipen1b_inst.msix_table_bir = 0,
altpcie_hip_pipen1b_inst.msix_table_offset = 0,
altpcie_hip_pipen1b_inst.msix_table_size = 0,
altpcie_hip_pipen1b_inst.use_crc_forwarding = "false",
altpcie_hip_pipen1b_inst.RX_BUF = 11,
altpcie_hip_pipen1b_inst.RH_NUM = 8,
altpcie_hip_pipen1b_inst.G_TAG_NUM0 = 32;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSBP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDFSBP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSBP_BLACKBOX_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module combines two video streams by overlaying one onto the *
* other using alpha blending. The foreground image must include alpha *
* bits to be used in the blending formula: Cn = (a < 0.5) ? Cb : Cf; *
* Cn - new color *
* a - alpha *
* Cb - background colour *
* Cf - foreground colour *
* *
******************************************************************************/
module altera_up_video_alpha_blender_simple (
// Inputs
background_data,
foreground_data,
// Bidirectionals
// Outputs
new_red,
new_green,
new_blue
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [29: 0] background_data;
input [39: 0] foreground_data;
// Bidirectionals
// Outputs
output [ 9: 0] new_red;
output [ 9: 0] new_green;
output [ 9: 0] new_blue;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign new_red =
(({10{foreground_data[39]}} & foreground_data[29:20]) |
({10{~foreground_data[39]}} & background_data[29:20]));
assign new_green =
(({10{foreground_data[39]}} & foreground_data[19:10]) |
({10{~foreground_data[39]}} & background_data[19:10]));
assign new_blue =
(({10{foreground_data[39]}} & foreground_data[ 9: 0]) |
({10{~foreground_data[39]}} & background_data[ 9: 0]));
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_1_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_1_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv3sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv3sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd1_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkdlyinv3sd1 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd1_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkdlyinv3sd1 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_1_V
|
//From the Mojo Base Project (embeddedmicro.com/tutorials/mojo)
//Used under the terms of the GPLv3
module spi_slave(
input clk,
input rst,
input ss,
input mosi,
output miso,
input sck,
output done,
input [15:0] din,
output [15:0] dout
);
reg mosi_d, mosi_q;
reg ss_d, ss_q;
reg sck_d, sck_q;
reg sck_old_d, sck_old_q;
reg [15:0] data_d, data_q;
reg done_d, done_q;
reg [3:0] bit_ct_d, bit_ct_q;
reg [15:0] dout_d, dout_q;
reg miso_d, miso_q;
assign miso = miso_q;
assign done = done_q;
assign dout = dout_q;
//TODO Document that chip select needs to be asserted at least 1/65Mhz before sck due to metastability concerns
always @(*) begin
ss_d = ss;
mosi_d = mosi;
miso_d = miso_q;
sck_d = sck;
sck_old_d = sck_q;
data_d = data_q;
done_d = 1'b0;
bit_ct_d = bit_ct_q;
dout_d = dout_q;
if (ss_q) begin
bit_ct_d = 4'b0;
data_d = din;
miso_d = data_q[15];
end else begin
if (!sck_old_q && sck_q) begin // rising edge
data_d = {data_q[14:0], mosi_q};
bit_ct_d = bit_ct_q + 1'b1;
if (bit_ct_q == 4'b1111) begin
dout_d = {data_q[14:0], mosi_q};
done_d = 1'b1;
data_d = din;
end
end else if (sck_old_q && !sck_q) begin // falling edge
miso_d = data_q[15];
end
end
end
always @(posedge clk) begin
if (rst) begin
done_q <= 1'b0;
bit_ct_q <= 4'b0;
dout_q <= 16'b0;
miso_q <= 1'b1;
end else begin
done_q <= done_d;
bit_ct_q <= bit_ct_d;
dout_q <= dout_d;
miso_q <= miso_d;
end
sck_q <= sck_d;
mosi_q <= mosi_d;
ss_q <= ss_d;
data_q <= data_d;
sck_old_q <= sck_old_d;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
reg [2:0] value;
reg [31:0] rglobal;
reg [31:0] vec [1:0];
reg [31:0] n;
initial begin
rglobal = 1;
value = 2;
if (add(value) != 3'd3) $stop;
if (rglobal != 2) $stop;
if (add(add(3'd1)) != 3'd3) $stop;
if (rglobal != 4) $stop;
if (munge4(4'b0010) != 4'b1011) $stop;
if (toint(2) != 3) $stop;
if (rglobal != 5) $stop;
setit;
incr(rglobal,rglobal,32'h10);
if (rglobal != 32'h17) $stop;
nop(32'h11);
empty;
empty();
rglobal = 32'h00000001;
flipupperbit(rglobal,4'd4);
flipupperbit(rglobal,4'd12);
if (rglobal !== 32'h10100001) $stop;
if (nil_func(32'h12,32'h12) != 32'h24) $stop;
nil_task(32'h012,32'h112,rglobal);
if (rglobal !== 32'h124) $stop;
vec[0] = 32'h333;
vec[1] = 32'habc;
incr(vec[1],vec[0],vec[1]);
if (vec[0] != 32'h333) $stop;
if (vec[1] != 32'hdef) $stop;
// verilator lint_off SELRANGE
incr(vec[2],vec[0],vec[2]); // Reading/Writing past end of vector!
// verilator lint_on SELRANGE
n=1;
nil();
if (n !== 10) $stop;
// Functions called as tasks
// verilator lint_off IGNOREDRETURN
rglobal = 32'h4;
if (inc_and_return(32'h2) != 32'h6) $stop;
if (rglobal !== 32'h6) $stop;
rglobal = 32'h6;
inc_and_return(32'h3);
if (rglobal !== 32'h9) $stop;
// verilator lint_on IGNOREDRETURN
$write("*-* All Finished *-*\n");
$finish;
end
function [2:0] add;
input [2:0] fromv;
begin
add = fromv + 3'd1;
begin : named
reg [31:0] flocal;
flocal = 1;
rglobal = rglobal + flocal;
end : named // SystemVerilog end labels
end
endfunction
function [3:0] munge4;
input [3:0] fromv; // Different fromv than the 'fromv' signal above
reg one;
begin : named
reg [1:0] flocal;
// Function calling a function
one = 1'b1;
munge4 = {one, add(fromv[2:0])};
end
endfunction
task setit;
reg [31:0] temp;
begin
temp = rglobal + 32'h1;
rglobal = temp + 32'h1;
end
endtask
task incr (
// Check a V2K style input/output list
output [31:0] z,
input [31:0] a, inc
);
z = a + inc;
endtask
task nop;
input [31:0] a;
begin
end
endtask
task empty;
endtask
task flipupperbit;
inout [31:0] vector;
input [3:0] bitnum;
reg [4:0] bitnum2;
begin
bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation
vector[bitnum2] = vector[bitnum2] ^ 1'b1;
end
endtask
task nil_task;
input [31:0] a;
input [31:0] b;
output [31:0] q;
// verilator no_inline_task
q = nil_func(a, b);
endtask
function void nil;
n = 10;
endfunction
function [31:0] nil_func;
input [31:0] fa;
input [31:0] fb;
// verilator no_inline_task
nil_func = fa + fb;
endfunction
function integer toint;
input integer fa;
toint = fa + 32'h1;
endfunction
function [31:0] inc_and_return;
input [31:0] inc;
rglobal = rglobal + inc;
return rglobal;
endfunction
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:32:43 09/11/2015
// Design Name: WB_intercon
// Module Name: Z:/share/ISE/CPUFly/tests/WB_intercon_test.v
// Project Name: CPUFly
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: WB_intercon
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module WB_intercon_test;
// Inputs
reg master_STB;
reg [31:0] master_DAT_I;
reg master_WE;
reg [31:0] master_ADDR;
reg [15:0] slave_ACK;
reg [511:0] slave_DAT_I;
// Outputs
wire [31:0] master_DAT_O;
wire master_ACK;
wire [15:0] slave_STB;
wire slave_WE;
wire [31:0] slave_DAT_O;
wire [31:0] slave_ADDR;
// Instantiate the Unit Under Test (UUT)
WB_intercon uut (
.master_STB(master_STB),
.master_DAT_I(master_DAT_I),
.master_DAT_O(master_DAT_O),
.master_ACK(master_ACK),
.master_WE(master_WE),
.master_ADDR(master_ADDR),
.slave_STB(slave_STB),
.slave_ACK(slave_ACK),
.slave_WE(slave_WE),
.slave_DAT_I(slave_DAT_I),
.slave_DAT_O(slave_DAT_O),
.slave_ADDR(slave_ADDR)
);
initial begin
// Initialize Inputs
master_STB = 0;
master_DAT_I = 0;
master_WE = 0;
master_ADDR = 0;
slave_ACK = 0;
slave_DAT_I = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
master_STB = 1;
master_DAT_I = 16'h2333;
master_WE = 1;
master_ADDR = 32'h10000000;
slave_ACK = 1;
slave_DAT_I = 32'h00002333;
end
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Set Universe Polymorphism.
Definition crelation (A : Type) := A -> A -> Type.
Definition arrow (A B : Type) := A -> B.
Definition flip {A B C : Type} (f : A -> B -> C) := fun x y => f y x.
Definition iffT (A B : Type) := ((A -> B) * (B -> A))%type.
(** We allow to unfold the [crelation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind crelational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : crelation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : crelation A) : crelation A :=
fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement iffT.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : crelation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : crelation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : crelation A) :=
asymmetry : forall {x y}, R x y -> (complement R y x : Type).
Class Transitive (R : crelation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : crelation A) := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : crelation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence crelation is Symmetric and Transitive. *)
Class PER (R : crelation A) := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence crelations. *)
Class Equivalence (R : crelation A) := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(Equivalence R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence crelation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : crelation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : crelation A) :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric crelation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros x y H'. red in H'. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite crelation on a given support: declares a crelation as a rewrite
crelation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
crelations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : crelation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite crelation. *)
Global Instance equivalence_rewrite_crelation `(Equivalence eqA) : RewriteRelation eqA.
Defined.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence crelation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite crelations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Defined.
Instance: RewriteRelation iff.
Defined.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for crelations. *)
Ltac solve_crelation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_crelation : crelations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_crelation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_crelation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence crelation. *)
Program Instance iff_equivalence : Equivalence iff.
Program Instance arrow_Reflexive : Reflexive arrow.
Program Instance arrow_Transitive : Transitive arrow.
Instance iffT_Reflexive : Reflexive iffT.
Proof. firstorder. Defined.
Instance iffT_Symmetric : Symmetric iffT.
Proof. firstorder. Defined.
Instance iffT_Transitive : Transitive iffT.
Proof. firstorder. Defined.
(** We now develop a generalization of results on crelations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary crelations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(** We define the various operations which define the algebra on binary crelations *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : crelation (crelation A) :=
fun R R' => forall x y, iffT (R x y) (R' x y).
Global Instance: RewriteRelation relation_equivalence.
Defined.
Definition relation_conjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => prod (R x y) (R' x y).
Definition relation_disjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => sum (R x y) (R' x y).
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof.
split; red; unfold relation_equivalence, iffT.
- firstorder.
- firstorder.
- intros. specialize (X x0 y0). specialize (X0 x0 y0). firstorder.
Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. firstorder. Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence crelation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
apply H. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof.
unfold flip; constructor; unfold flip.
- intros. apply H. apply symmetry. apply X.
- unfold relation_conjunction. intros [H1 H2]. apply H. constructor; assumption.
Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and crelation equivalence. *)
(* Program Instance subrelation_partial_order : *)
(* ! PartialOrder (crelation A) relation_equivalence subrelation. *)
(* Obligation Tactic := idtac. *)
(* Next Obligation. *)
(* Proof. *)
(* intros x. refine (fun x => x). *)
(* Qed. *)
Typeclasses Opaque relation_equivalence.
|
`include "hi_read_tx.v"
/*
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
shallow_modulation - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_read_tx;
reg pck0;
reg [7:0] adc_d;
reg shallow_modulation;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_read_tx #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.shallow_modulation(shallow_modulation)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
//crank DUT
task crank_dut;
begin
@(posedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
adc_d = 0;
ssp_dout=0;
// shallow modulation off
shallow_modulation=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
shallow_modulation=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_TB_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dlatch_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_TB_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_ultrascale.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXC Engine takes unformatted completions, formats
// these packets into AXI-style packets. These packets must meet max-request,
// max-payload, and payload termination requirements (see Read Completion
// Boundary). The TXC Engine does not check these requirements during operation,
// but may do so during simulation.
//
// This Engine is capable of operating at "line rate".
//
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "ultrascale.vh"
module txc_engine_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_DEPTH_PACKETS = 10,
parameter C_MAX_PAYLOAD_DWORDS = 256
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY
);
`include "functions.vh"
localparam C_VENDOR = "XILINX";
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = 128; // It's really 96... But it gets trimmed
localparam C_MAX_HDR_DWORDS = C_MAX_HDR_WIDTH/32;
localparam C_MAX_ALIGN_DWORDS = 0;
localparam C_MAX_NONPAY_DWORDS = C_MAX_HDR_DWORDS + C_MAX_ALIGN_DWORDS;
//
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
wire wTxDataReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wTxDataWordReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktValid;
wire wTxcPktReady;
txc_formatter_ultrascale
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH))
txc_formatter_inst
(
// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
tx_engine
#(
.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txc_engine_inst
(
// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXC_DATA_READY),
.TX_PKT (wTxcPkt[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (wTxcPktStartFlag),
.TX_PKT_START_OFFSET (wTxcPktStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (wTxcPktEndFlag),
.TX_PKT_END_OFFSET (wTxcPktEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (wTxcPktValid),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXC_DATA_VALID),
.TX_DATA (TXC_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (wTxcPktReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
txc_translation_layer
#(
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT)
/*AUTOINSTPARAM*/)
txc_trans_inst
(
// Outputs
.TXC_PKT_READY (wTxcPktReady),
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.TXC_PKT (wTxcPkt),
.TXC_PKT_VALID (wTxcPktValid),
.TXC_PKT_START_FLAG (wTxcPktStartFlag),
.TXC_PKT_START_OFFSET (wTxcPktStartOffset),
.TXC_PKT_END_FLAG (wTxcPktEndFlag),
.TXC_PKT_END_OFFSET (wTxcPktEndOffset),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY)
/*AUTOINST*/);
endmodule // txc_engine_ultrascale
module txc_formatter_ultrascale
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_HDR_WIDTH = `UPKT_TXC_MAXHDR_W
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
`include "functions.vh"
wire [`UPKT_TXC_MAXHDR_W-1:0] wHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
// Generic Header Fields
// ATYPE Should be copied from the request parameters, but we only use 0
assign wHdr[`UPKT_TXC_ADDRLOW_R] = TXC_META_ADDR;
assign wHdr[`UPKT_TXC_RSVD0_R] = `UPKT_TXC_RSVD0_W'd0;
assign wHdr[`UPKT_TXC_ATYPE_R] = `UPKT_TXC_ATYPE_W'd0;
assign wHdr[`UPKT_TXC_RSVD1_R] = `UPKT_TXC_RSVD1_W'd0;
assign wHdr[`UPKT_TXC_BYTECNT_R] = {1'b0,TXC_META_BYTE_COUNT};
assign wHdr[`UPKT_TXC_LOCKED_R] = `UPKT_TXC_LOCKED_W'd0;
assign wHdr[`UPKT_TXC_RSVD2_R] = `UPKT_TXC_RSVD2_W'd0;
assign wHdr[`UPKT_TXC_LENGTH_R] = {1'b0, TXC_META_LENGTH};
assign wHdr[`UPKT_TXC_STATUS_R] = `UPKT_TXC_STATUS_W'd0;
assign wHdr[`UPKT_TXC_EP_R] = TXC_META_EP;
assign wHdr[`UPKT_TXC_RSVD3_R] = `UPKT_TXC_RSVD3_W'd0;
assign wHdr[`UPKT_TXC_REQID_R] = TXC_META_REQUESTER_ID;
assign wHdr[`UPKT_TXC_TAG_R] = TXC_META_TAG;
assign wHdr[`UPKT_TXC_CPLID_R] = CONFIG_COMPLETER_ID;
assign wHdr[`UPKT_TXC_CPLIDEN_R] = 1'b0;
assign wHdr[`UPKT_TXC_TC_R] = TXC_META_TC;
assign wHdr[`UPKT_TXC_ATTR_R] = TXC_META_ATTR;
assign wHdr[`UPKT_TXC_TD_R] = `UPKT_TXC_TD_W'd0;
assign wTxHdrNopayload = ~wTxType[`TRLS_TYPE_PAY_I];
assign wTxHdrNonpayLen = 3;
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`UPKT_TXC_LENGTH_I +: `SIG_LEN_W];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH + `SIG_TYPE_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(
// Outputs
.WR_DATA_READY (TXC_META_READY),
.RD_DATA ({wTxHdr,wTxType}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({32'b0,wHdr,TXC_META_TYPE}),
.WR_DATA_VALID (TXC_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txc_translation_layer
#(
parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: TXC Classic
output TXC_PKT_READY,
input [C_PCI_DATA_WIDTH-1:0] TXC_PKT,
input TXC_PKT_VALID,
input TXC_PKT_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_START_OFFSET,
input TXC_PKT_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_PKT_END_OFFSET,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER
);
`include "functions.vh"
localparam C_INPUT_STAGES = C_PIPELINE_INPUT != 0? 1:0;
localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT != 0? 1:0;
wire wTxcPktReady;
wire [C_PCI_DATA_WIDTH-1:0] wTxcPkt;
wire wTxcPktValid;
wire wTxcPktStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktStartOffset;
wire wTxcPktEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcPktEndOffset;
wire wSAxisCcTReady;
wire wSAxisCcTValid;
wire wSAxisCcTLast;
wire [C_PCI_DATA_WIDTH-1:0] wSAxisCcTData;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wSAxisCcTKeep;
wire [`SIG_CC_TUSER_W-1:0] wSAxisCcTUser;
/*ASSIGN TXC -> CC*/
assign wTxcPktReady = wSAxisCcTReady;
assign wSAxisCcTValid = wTxcPktValid;
assign wSAxisCcTLast = wTxcPktEndFlag;
assign wSAxisCcTData = wTxcPkt;
assign S_AXIS_CC_TUSER = `SIG_CC_TUSER_W'd0; // Do not enable parity bits, and no discontinues
pipeline
#(
// Parameters
.C_DEPTH (C_INPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 2*(1+clog2s(C_PCI_DATA_WIDTH/32))),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(
// Outputs
.WR_DATA_READY (TXC_PKT_READY),
.RD_DATA ({wTxcPkt,wTxcPktStartFlag,wTxcPktStartOffset,wTxcPktEndFlag,wTxcPktEndOffset}),
.RD_DATA_VALID (wTxcPktValid),
// Inputs
.WR_DATA ({TXC_PKT,TXC_PKT_START_FLAG,TXC_PKT_START_OFFSET,
TXC_PKT_END_FLAG,TXC_PKT_END_OFFSET}),
.WR_DATA_VALID (TXC_PKT_VALID),
.RD_DATA_READY (wTxcPktReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
offset_to_mask
#(
// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
otom_inst
(
// Outputs
.MASK (wSAxisCcTKeep),
// Inputs
.OFFSET_ENABLE (wTxcPktEndFlag),
.OFFSET (wTxcPktEndOffset)
/*AUTOINST*/);
pipeline
#(
// Parameters
.C_DEPTH (C_OUTPUT_STAGES),
.C_WIDTH (C_PCI_DATA_WIDTH + 1 + (C_PCI_DATA_WIDTH/32)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wSAxisCcTReady),
.RD_DATA ({S_AXIS_CC_TDATA,S_AXIS_CC_TLAST,S_AXIS_CC_TKEEP}),
.RD_DATA_VALID (S_AXIS_CC_TVALID),
// Inputs
.WR_DATA ({wSAxisCcTData,wSAxisCcTLast,wSAxisCcTKeep}),
.WR_DATA_VALID (wSAxisCcTValid),
.RD_DATA_READY (S_AXIS_CC_TREADY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:54:16 03/16/2014
// Design Name:
// Module Name: Core
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Core(
input clk,
input nrst,
output instr,
output IFID_instr,
output IDEX_instr,
output EXMEM_instr,
output MEMWB_instr,
//output reg[31:0] iaddr,
output daddr,
output dout,
output MEMWB_dout,
output wr,
output EXMEM_wr,
output pc,
output IFID_pc,
output IDEX_pc,
output EXMEM_pc,
output reg_din,
output reg_raddr1,
output reg_dout1,
output IDEX_reg_dout1,
output reg_raddr2,
output reg_dout2,
output IDEX_reg_dout2,
output EXMEM_reg_dout2,
output wr_reg,
output EXMEM_wr_reg,
output MEMWB_wr_reg,
output reg_wr_addr,
output ALUOut,
output EXMEM_ALUOut,
output MEMWB_ALUOut,
output ALUOp,
output ALUSrc,
output ALUIn2,
output MemToReg,
output EXMEM_MemToReg,
output MEMWB_MemToReg,
output RegDst,
output EXMEM_RegDst,
output MEMWB_RegDst,
output PCSrc,
output wire[31:0] ram1,
output wire[31:0] ram2,
output wire[31:0] ram3,
output Zero,
output Branch,
output Jump,
output M3_Select,
output M2_Select,
output M7_Select,
output F4F8,
output F2F6,
output F1F5,
output F3F7,
output F9,
output F10,
output IFID_RegisterRd,
output IFID_RegisterRt,
output IFID_RegisterRs,
output IDEX_RegisterRd,
output IDEX_RegisterRt,
output IDEX_RegisterRs,
output EXMEM_RegisterRd,
output EXMEM_RegisterRt,
output EXMEM_RegisterRs,
output MEMWB_RegisterRd,
output MEMWB_RegisterRt,
output MEMWB_RegisterRs
);
wire[31:0] instr;
reg[31:0] IFID_instr;
reg[31:0] IDEX_instr;
reg[31:0] EXMEM_instr;
reg[31:0] MEMWB_instr;
reg[5:0] daddr;
wire[31:0] dout;
reg[31:0] MEMWB_dout;
reg[3:0] wr;
reg[3:0] EXMEM_wr;
reg[31:0] pc;
reg[31:0] IFID_pc;
reg[31:0] IDEX_pc;
reg[31:0] EXMEM_pc;
wire[31:0] reg_din;
reg[4:0] reg_raddr1;
wire[31:0] reg_dout1;
reg[31:0] IDEX_reg_dout1;
reg[4:0] reg_raddr2;
wire[31:0] reg_dout2;
reg[31:0] IDEX_reg_dout2;
reg[31:0] EXMEM_reg_dout2;
reg wr_reg;
reg EXMEM_wr_reg;
reg MEMWB_wr_reg;
reg[4:0] reg_wr_addr;
reg[31:0] ALUOut;
reg[31:0] EXMEM_ALUOut;
reg[31:0] MEMWB_ALUOut;
reg[3:0] ALUOp;
reg ALUSrc;
reg[31:0] ALUIn2;
reg MemToReg;
reg EXMEM_MemToReg;
reg MEMWB_MemToReg;
reg RegDst;
reg EXMEM_RegDst;
reg MEMWB_RegDst;
reg PCSrc;
reg Zero;
reg Branch;
reg Jump;
wire[31:0] F10;
wire[31:0] F4F8;
wire[31:0] F2F6;
wire[31:0] F1F5;
wire[31:0] F3F7;
wire[31:0] F9;
reg[1:0] M3_Select;
reg[1:0] M2_Select;
reg M7_Select;
reg[4:0] IFID_RegisterRd;
reg[4:0] IFID_RegisterRt;
reg[4:0] IFID_RegisterRs;
reg[4:0] IDEX_RegisterRd;
reg[4:0] IDEX_RegisterRt;
reg[4:0] IDEX_RegisterRs;
reg[4:0] EXMEM_RegisterRd;
reg[4:0] EXMEM_RegisterRt;
reg[4:0] EXMEM_RegisterRs;
reg[4:0] MEMWB_RegisterRd;
reg[4:0] MEMWB_RegisterRt;
reg[4:0] MEMWB_RegisterRs;
//Wires & Regs definitions
//wire[31:0] instr; ->moved to module inputs for debug purposes
//reg[31:0] ALUOut;
//reg[3:0] ALUOp;
//reg ALUSrc;
reg Carry;
//reg RegDst;
//reg MemToReg;
//reg[31:0] ALUIn2;
wire[7:0] din[0:3];
//reg[7:0] pc = 8'b00000000;
//reg[31:0] immediate_extended;
reg[31:0] next_pc;
reg[31:0] j_pc;
reg[31:0] shifted_pc;
reg[4:0] shamt;
/*
reg[4:0] reg_raddr1;
wire[31:0] reg_dout1;
reg[4:0] reg_raddr2;
wire[31:0] reg_dout2;
wire wr_reg;
reg[4:0] reg_wr_addr;
reg[31:0] reg_din;
moved to module outputs for debug purposes
*/
wire nclk;
assign nclk = !(clk);
regfile registers(
clk,
reg_raddr1,
reg_dout1,
reg_raddr2,
reg_dout2,
MEMWB_wr_reg,
reg_wr_addr,
reg_din,
nrst,
ram1,
ram2,
ram3
);
//Memory instantiations
wire[31:0] dina; //not used since we don't write to imem
//wire[31:0] tmp_instr;
wire z;
assign z = 0;
IMem imem (
nclk, // input clka
z, // input [0 : 0] wea
pc[7:2], // input [5 : 0] addra
dina, // input [31 : 0] dina
instr // output [31 : 0] douta
);
DMem dmem_0 (
clk, // input clka
EXMEM_wr[0], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[7:0], // input [7 : 0] dina
dout[7:0] // output [7 : 0] douta
);
DMem dmem_1 (
clk, // input clka
EXMEM_wr[1], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[15:8], // input [7 : 0] dina
dout[15:8] // output [7 : 0] douta
);
DMem dmem_2 (
clk, // input clka
EXMEM_wr[2], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[23:16], // input [7 : 0] dina
dout[23:16] // output [7 : 0] douta
);
DMem dmem_3 (
clk, // input clka
EXMEM_wr[3], // input [0 : 0] wea
daddr[5:0], // input [5 : 0] addra
EXMEM_reg_dout2[31:24], // input [7 : 0] dina
dout[31:24] // output [7 : 0] douta
);
reg[31:0] JDest;
reg JR;
always @*
begin
//PCSrc Mux & Jump
//4'b0000 because our memory real pc is 8 bits and 4 MSBs are always 0 in our case
JDest <= JR ? (IDEX_reg_dout1 << 2) : {4'b0000, IDEX_instr[25:0], 2'b00};
j_pc <= Jump ? JDest : pc + 32'b100;
shifted_pc <= (({{16{IDEX_instr[15]}}, IDEX_instr[15:0]}) << 2) + (IDEX_pc + 32'b100);
PCSrc <= Branch & Zero;
next_pc <= PCSrc ? shifted_pc : j_pc;
//RegDst Mux
reg_wr_addr <= MEMWB_RegDst ? MEMWB_instr[15:11] : MEMWB_instr[20:16];
reg_raddr1 <= IFID_instr[25:21];
reg_raddr2 <= IFID_instr[20:16];
IFID_RegisterRd <= IFID_instr[31:26] == 6'b001000 ? IFID_instr[20:16] : IFID_instr[15:11];//IFID_instr[31:26] == 6'b100011) ? IFID_instr[20:16] : IFID_instr[15:11]; //LW : else
IFID_RegisterRt <= IFID_instr[20:16];
IFID_RegisterRs <= IFID_instr[25:21];
//ALUSrc Mux
ALUIn2 <= ALUSrc ? {{16{IDEX_instr[15]}}, IDEX_instr[15:0]} : IDEX_reg_dout2; //sign extended
end
//MemToReg Mux
assign reg_din = MEMWB_MemToReg ? MEMWB_dout : MEMWB_ALUOut;
//Forwarding Wires
assign F4F8 = EXMEM_ALUOut;
assign F2F6 = EXMEM_ALUOut;
assign F1F5 = EXMEM_ALUOut;
assign F3F7 = EXMEM_ALUOut;
assign F9 = dout;
assign F10 = dout;
//PC
always @(posedge clk)
begin
if (~nrst)
begin
pc = 32'b0;
Branch <= 0;
Jump <= 0;
//ALUOut <= 32'b0;
end
else
begin
pc = next_pc;
end
end
//Decode
always @(posedge clk)
begin
if (IFID_instr[31:26] == 6'b001000)
ALUOp = 4'b0000;
case (IFID_instr[31:26])
6'b000000 :
begin
//func
case (IFID_instr[10:0])
11'b00000100000 : //Add
begin
ALUOp = 4'b0000;
end
11'b00000100100 : //And
begin
ALUOp = 4'b0001;
end
11'b00000100010 : //Sub
begin
ALUOp = 4'b0100;
end
11'b00000100101: // OR
begin
ALUOp = 4'b0010;
end
11'b00000100110: // XOR
begin
ALUOp = 4'b0111;
end
11'b00000011010, 11'b00000011011 : // Div, Divu
begin
ALUOp = 4'b0101;
end
11'b00000011000, 11'b00000011001 : // Mult, Multu
begin
ALUOp = 4'b0110;
end
default :
begin
/*case(IFID_instr[5:0])
6'b000000 : //SLL
begin
ALUOp = 4'b0011;
end
endcase*/
end
endcase
end
6'b001101 : //ORI
ALUOp = 4'b0010;
6'b001110 : //XORI
ALUOp = 4'b0111;
6'b001100 : //ANDI
ALUOp = 4'b0000;
6'b001000 , 6'b001001 :
ALUOp = 4'b0000; // ADDI
6'b000100, 6'b000001, 6'b000111, 6'b000110, 6'b000001, 6'b000101 : // BEQ, BGEZ, BGEZAL, BGTZ, BLEZ, BLTZ, BLTZAL, BNE
ALUOp = 4'b0100; // (uses Sub)
6'b100000 : // LB
ALUOp = 4'b0000;
6'b001111 : // LUI
ALUOp = 4'b0000;
6'b100011 : // LW
ALUOp = 4'b0000;
6'b101000 : // SB
ALUOp = 4'b0000;
6'b101011 : // SW
ALUOp = 4'b0000;
/*6'b000011 : //JAL (Save ret addr in $31) Needs Fix
begin
//reg_din <= pc + 3'b100;
//reg_wr_addr = 5'b11111;
wr_reg <= 1;
end*/
default :
//6'b000010 : // Jump
//Nothing (we don't need the alu)
;
endcase
end
//Control
always @(posedge clk)
begin
if (IFID_instr == 32'b0) //NOP
begin
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 0;
Branch <= 0;
end
else
begin
case (IFID_instr[31:26])
6'b000000 :
begin
//func
case (IFID_instr[10:0])
11'b00000100000, 11'b00000100001, 11'b00000100010, 00000100011, 11'b00000100100, 11'b00000100101, 11'b00000100110 : //Add, Addu, Sub, Subu , And, Or, XOR
/*(Note: ALL arithmetic immediate values are sign-extended. After that, they are handled as
signed or unsigned 32 bit numbers, depending upon the instruction. The only difference between
signed and unsigned instructions is that signed instructions can generate an overflow exception
and unsigned instructions can not. )
*/
begin
RegDst <= 1;
ALUSrc <= 0;
//reg_raddr1 <= instr[25:21];
//reg_raddr2 <= instr[20:16];
//reg_wr_addr <<= instr[15:11];
wr_reg <= 1;
MemToReg <= 0;
Branch <= 0;
Jump <= 0;
end
11'b00000000000 : //???????????????
case(IFID_instr[5:0])
6'b000000 : //SLL
begin
RegDst <= 1;
ALUSrc <= 0;
wr_reg <= 1;
MemToReg <= 0;
Branch <= 0;
Jump <= 0;
shamt <= IDEX_instr[10:6];
end
endcase
11'b00000001000 : //JR
if (IFID_instr[20:0] == 21'b1000)
begin
reg_raddr1 <= instr[25:21];
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 1;
//JR <= 1;
end
default:
;
endcase
end
6'b001000, 6'b001001, 6'b001100, 6'b001101, 6'b001101 : //Addi, Addiu, Andi, Ori, Xori
begin
RegDst <= 0;
ALUSrc <= 1; //immediate
//reg_wr_addr <= instr[20:16];
wr_reg <= 1;
MemToReg <= 0;
Branch <= 0;
Jump <= 0;
end
6'b000100 : //BEQ
begin
Branch <= 1;
Jump <= 0;
MemToReg <= 0;
wr_reg <= 0;
wr <= 0;
ALUSrc <= 0;
end
//======================= MEMORY ==========================
6'b100000 : // LB
begin
RegDst <= 0;
ALUSrc <= 1; // immediate
wr[0] <= 0;
wr[1] <= 0;
wr[2] <= 0;
wr[3] <= 0;
//daddr[5:0] <= ALUOut[5:0];
//reg_wr_addr <= instr[20:16];
wr_reg <= 1;
MemToReg <= 1;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b100011 : // LW
begin
RegDst <= 0;
ALUSrc <= 1; //if i=2
wr[0] <= 0;
wr[1] <= 0;
wr[2] <= 0;
wr[3] <= 0;
//daddr[5:0] <= ALUOut[5:0];
//reg_wr_addr <= instr[20:16];
wr_reg <= 1;
MemToReg <= 1;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b101000 : // SB
begin
ALUSrc <= 1; // immediate
wr[0] <= 1;
wr[1] <= 0;
wr[2] <= 0;
wr[3] <= 0;
reg_raddr2 <= IFID_instr[20:16];
wr_reg <= 0;
MemToReg <= 0;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b101011 : // SW
begin
ALUSrc <= 1; // immediate
wr[0] <= 1;
wr[1] <= 1;
wr[2] <= 1;
wr[3] <= 1;
reg_raddr2 <= IFID_instr[20:16];
wr_reg <= 0;
MemToReg <= 0;
PCSrc <= 0;
Branch <= 0;
Jump <= 0;
end
6'b000010 : // Jump
begin
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 1;
JR <= 0;
end
/*6'b000011 : // JAL
begin
wr_reg <= 0;
wr <= 4'b0000;
Branch <= 0;
Jump <= 1;
JR <= 0;
end*/
default :
;
endcase
end
end
//Pipeline
always @(posedge clk)
begin
if (nrst)
begin
MEMWB_instr <= EXMEM_instr;
EXMEM_instr <= IDEX_instr;
IDEX_instr <= IFID_instr;
IFID_instr <= instr;
EXMEM_pc <= IDEX_pc;
IDEX_pc <= IFID_pc;
IFID_pc <= pc;
MEMWB_ALUOut <= EXMEM_ALUOut;
EXMEM_ALUOut <= ALUOut;
//Moved to forwarding mux
//IDEX_reg_dout1 <= reg_dout1;
//EXMEM_reg_dout2 <= IDEX_reg_dout2;
//IDEX_reg_dout2 <= reg_dout2;
MEMWB_wr_reg <= EXMEM_wr_reg;
EXMEM_wr_reg <= wr_reg;
MEMWB_MemToReg <= EXMEM_MemToReg;
EXMEM_MemToReg <= MemToReg;
MEMWB_RegDst <= EXMEM_RegDst;
EXMEM_RegDst <= RegDst;
daddr[5:0] <= ALUOut[5:0];
MEMWB_dout <= dout;
EXMEM_wr <= wr;
MEMWB_RegisterRd <= EXMEM_RegisterRd;
EXMEM_RegisterRd <= IDEX_RegisterRd;
IDEX_RegisterRd <= IFID_RegisterRd;
MEMWB_RegisterRt <= EXMEM_RegisterRt;
EXMEM_RegisterRt <= IDEX_RegisterRt;
IDEX_RegisterRt <= IFID_RegisterRt;
MEMWB_RegisterRs <= EXMEM_RegisterRs;
EXMEM_RegisterRs <= IDEX_RegisterRs;
IDEX_RegisterRs <= IFID_RegisterRs;
end
end
//Forwarding Multiplexers
always @(negedge clk)
begin
case (M3_Select)
2'b00 :
IDEX_reg_dout2 <= reg_dout2;
//2'b01 :
//IDEX_reg_dout2 <= F10;
2'b10 :
IDEX_reg_dout2 <= F4F8;
2'b11 :
IDEX_reg_dout2 <= F2F6;
default :
IDEX_reg_dout2 <= reg_dout2;
endcase
case (M2_Select)
2'b00 :
IDEX_reg_dout1 <= F1F5;
2'b01 :
IDEX_reg_dout1 <= F3F7;
2'b10 :
IDEX_reg_dout1 <= F9;
2'b11 :
IDEX_reg_dout1 <= reg_dout1;
default :
IDEX_reg_dout1 <= reg_dout1;
endcase
//M7_Select
EXMEM_reg_dout2 <= M7_Select ? F10 : IDEX_reg_dout2;
end
//Forwarding Unit
always @(*)
begin
M2_Select <= 2'b11;
M3_Select <= 2'b00;
M7_Select <= 0;
if ((MEMWB_RegisterRt == EXMEM_RegisterRt) && (MEMWB_instr[31:26] == 6'b100011))
M7_Select <= 1;
if (EXMEM_wr_reg && (EXMEM_RegisterRd != 0))
begin
if (EXMEM_RegisterRd == IDEX_RegisterRs)
//forward A
M2_Select <= 2'b00;
else
M2_Select <= 2'b11;
if (EXMEM_RegisterRd == IDEX_RegisterRt)
//forward B
M3_Select <= 2'b11;
else
M3_Select <= 2'b00;
end
if ((MEMWB_RegisterRt == IDEX_RegisterRs) && (MEMWB_instr[31:26] == 6'b100011))
M2_Select <= 2'b10;
if ((MEMWB_wr_reg && (MEMWB_RegisterRd != 0)) && !(EXMEM_wr_reg && (EXMEM_RegisterRd != 0) && ((EXMEM_RegisterRd == IDEX_RegisterRs))))
begin
if (MEMWB_RegisterRd == IDEX_RegisterRs)
//forward A
M2_Select <= 2'b01;
else
M2_Select <= 2'b11;
end
if ((MEMWB_wr_reg && (MEMWB_RegisterRd != 0)) && !(EXMEM_wr_reg && (EXMEM_RegisterRd != 0) && (EXMEM_RegisterRd == IDEX_RegisterRt)))
begin
if (MEMWB_RegisterRd == IDEX_RegisterRt)
//forward B
M3_Select <= 2'b10;
else
M3_Select <= 2'b00;
end
end
//ALU
//reg[32:0] tmp; //used in add, to compute carry
always @(*)
begin
/*
0000 : add/i/ui/u
0001 : and/i
0010 : or
0011 : sll
0100 : Sub/u
0101 : Div
0110 : Mult
0111 : xor/i
: sllv
: sra
: srl
: srlv
*/
case (ALUOp)
4'b0000 : //Add
begin
ALUOut <= ALUIn2 + IDEX_reg_dout1;
//tmp <= ALUIn2 + reg_dout1;
//ALUOut <= tmp[31:0];
//Carry = tmp[32];
//Set Carry flag if signed!
end
4'b0001 : //And
begin
ALUOut <= IDEX_reg_dout1 & ALUIn2;
end
4'b0010 : // OR
begin
ALUOut <= IDEX_reg_dout1 | ALUIn2;
end
4'b0011 : // SLL
begin
ALUOut <= ALUIn2 << shamt;
end
4'b0100 : // Sub
begin
ALUOut <= IDEX_reg_dout1 - ALUIn2;
Zero <= (ALUOut == 32'b0) ? 1 : 0;
end
/*4'b0101 : // Div, Divu
begin
HI <= reg_dout1 / ALUIn2;
LO <= reg_dout1 % ALUIn2;
end*/
/*4'b0110 : // Mult, Multu
begin
{HI, LO} <= reg_dout1 * ALUIn2;
end*/
4'b0111 : // Xor, Xori
begin
ALUOut <= IDEX_reg_dout1 ^ ALUIn2;
end
default :
;
endcase
end
endmodule
|
/*
Copyright (c) 2014-2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
output wire [1:0] led_user_grn,
output wire [1:0] led_user_red,
output wire [3:0] led_qsfp,
/*
* Ethernet: QSFP28
*/
input wire qsfp0_tx_clk_1,
input wire qsfp0_tx_rst_1,
output wire [63:0] qsfp0_txd_1,
output wire [7:0] qsfp0_txc_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [63:0] qsfp0_rxd_1,
input wire [7:0] qsfp0_rxc_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [63:0] qsfp0_txd_2,
output wire [7:0] qsfp0_txc_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [63:0] qsfp0_rxd_2,
input wire [7:0] qsfp0_rxc_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [63:0] qsfp0_txd_3,
output wire [7:0] qsfp0_txc_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [63:0] qsfp0_rxd_3,
input wire [7:0] qsfp0_rxc_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [63:0] qsfp0_txd_4,
output wire [7:0] qsfp0_txc_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [63:0] qsfp0_rxd_4,
input wire [7:0] qsfp0_rxc_4,
input wire qsfp1_tx_clk_1,
input wire qsfp1_tx_rst_1,
output wire [63:0] qsfp1_txd_1,
output wire [7:0] qsfp1_txc_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [63:0] qsfp1_rxd_1,
input wire [7:0] qsfp1_rxc_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [63:0] qsfp1_txd_2,
output wire [7:0] qsfp1_txc_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [63:0] qsfp1_rxd_2,
input wire [7:0] qsfp1_rxc_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [63:0] qsfp1_txd_3,
output wire [7:0] qsfp1_txc_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [63:0] qsfp1_rxd_3,
input wire [7:0] qsfp1_rxc_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [63:0] qsfp1_txd_4,
output wire [7:0] qsfp1_txc_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [63:0] qsfp1_rxd_4,
input wire [7:0] qsfp1_rxc_4,
input wire qsfp2_tx_clk_1,
input wire qsfp2_tx_rst_1,
output wire [63:0] qsfp2_txd_1,
output wire [7:0] qsfp2_txc_1,
input wire qsfp2_rx_clk_1,
input wire qsfp2_rx_rst_1,
input wire [63:0] qsfp2_rxd_1,
input wire [7:0] qsfp2_rxc_1,
input wire qsfp2_tx_clk_2,
input wire qsfp2_tx_rst_2,
output wire [63:0] qsfp2_txd_2,
output wire [7:0] qsfp2_txc_2,
input wire qsfp2_rx_clk_2,
input wire qsfp2_rx_rst_2,
input wire [63:0] qsfp2_rxd_2,
input wire [7:0] qsfp2_rxc_2,
input wire qsfp2_tx_clk_3,
input wire qsfp2_tx_rst_3,
output wire [63:0] qsfp2_txd_3,
output wire [7:0] qsfp2_txc_3,
input wire qsfp2_rx_clk_3,
input wire qsfp2_rx_rst_3,
input wire [63:0] qsfp2_rxd_3,
input wire [7:0] qsfp2_rxc_3,
input wire qsfp2_tx_clk_4,
input wire qsfp2_tx_rst_4,
output wire [63:0] qsfp2_txd_4,
output wire [7:0] qsfp2_txc_4,
input wire qsfp2_rx_clk_4,
input wire qsfp2_rx_rst_4,
input wire [63:0] qsfp2_rxd_4,
input wire [7:0] qsfp2_rxc_4,
input wire qsfp3_tx_clk_1,
input wire qsfp3_tx_rst_1,
output wire [63:0] qsfp3_txd_1,
output wire [7:0] qsfp3_txc_1,
input wire qsfp3_rx_clk_1,
input wire qsfp3_rx_rst_1,
input wire [63:0] qsfp3_rxd_1,
input wire [7:0] qsfp3_rxc_1,
input wire qsfp3_tx_clk_2,
input wire qsfp3_tx_rst_2,
output wire [63:0] qsfp3_txd_2,
output wire [7:0] qsfp3_txc_2,
input wire qsfp3_rx_clk_2,
input wire qsfp3_rx_rst_2,
input wire [63:0] qsfp3_rxd_2,
input wire [7:0] qsfp3_rxc_2,
input wire qsfp3_tx_clk_3,
input wire qsfp3_tx_rst_3,
output wire [63:0] qsfp3_txd_3,
output wire [7:0] qsfp3_txc_3,
input wire qsfp3_rx_clk_3,
input wire qsfp3_rx_rst_3,
input wire [63:0] qsfp3_rxd_3,
input wire [7:0] qsfp3_rxc_3,
input wire qsfp3_tx_clk_4,
input wire qsfp3_tx_rst_4,
output wire [63:0] qsfp3_txd_4,
output wire [7:0] qsfp3_txc_4,
input wire qsfp3_rx_clk_4,
input wire qsfp3_rx_rst_4,
input wire [63:0] qsfp3_rxd_4,
input wire [7:0] qsfp3_rxc_4
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid && !valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign led_user_grn = led_reg;
assign led_user_red = 0;
assign led_qsfp = 0;
assign qsfp0_txd_2 = 64'h0707070707070707;
assign qsfp0_txc_2 = 8'hff;
assign qsfp0_txd_3 = 64'h0707070707070707;
assign qsfp0_txc_3 = 8'hff;
assign qsfp0_txd_4 = 64'h0707070707070707;
assign qsfp0_txc_4 = 8'hff;
assign qsfp1_txd_1 = 64'h0707070707070707;
assign qsfp1_txc_1 = 8'hff;
assign qsfp1_txd_2 = 64'h0707070707070707;
assign qsfp1_txc_2 = 8'hff;
assign qsfp1_txd_3 = 64'h0707070707070707;
assign qsfp1_txc_3 = 8'hff;
assign qsfp1_txd_4 = 64'h0707070707070707;
assign qsfp1_txc_4 = 8'hff;
assign qsfp2_txd_1 = 64'h0707070707070707;
assign qsfp2_txc_1 = 8'hff;
assign qsfp2_txd_2 = 64'h0707070707070707;
assign qsfp2_txc_2 = 8'hff;
assign qsfp2_txd_3 = 64'h0707070707070707;
assign qsfp2_txc_3 = 8'hff;
assign qsfp2_txd_4 = 64'h0707070707070707;
assign qsfp2_txc_4 = 8'hff;
assign qsfp3_txd_1 = 64'h0707070707070707;
assign qsfp3_txc_1 = 8'hff;
assign qsfp3_txd_2 = 64'h0707070707070707;
assign qsfp3_txc_2 = 8'hff;
assign qsfp3_txd_3 = 64'h0707070707070707;
assign qsfp3_txc_3 = 8'hff;
assign qsfp3_txd_4 = 64'h0707070707070707;
assign qsfp3_txc_4 = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(qsfp0_rx_clk_1),
.rx_rst(qsfp0_rx_rst_1),
.tx_clk(qsfp0_tx_clk_1),
.tx_rst(qsfp0_tx_rst_1),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(qsfp0_rxd_1),
.xgmii_rxc(qsfp0_rxc_1),
.xgmii_txd(qsfp0_txd_1),
.xgmii_txc(qsfp0_txc_1),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__HA_FUNCTIONAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire xor0_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4B_SYMBOL_V
`define SKY130_FD_SC_LP__OR4B_SYMBOL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4B_SYMBOL_V
|
// usb_ft232.v
`timescale 1 ns / 1 ps
module usb_ft232
(
input clk,
input reset,
// FT232 interface
output wr_n,
output rd_n,
output oe_n,
inout [7:0]data,
input txe_n,
input rxf_n,
output siwu_n,
// tx fifo interface
output tx_read,
input [15:0]tx_data,
input [1:0]tx_mask,
input tx_ready,
// rx fifo interface
output reg rx_write,
output reg [15:0]rx_data,
output reg rx_mask,
input rx_ready
);
// === transmitter ========================================================
wire tx_ena;
wire tx_wait;
wire tx_skip;
reg tx_upper;
wire tx_is_send = tx_ready && !tx_mask[0];
wire tx_is_16bit = tx_ready && tx_mask[1];
// tx_data -> data transfer; flow control with tx_ena & tx_wait
wire wr = !txe_n && tx_ready && tx_ena && !tx_is_send;
assign wr_n = !wr;
assign oe_n = !wr_n;
assign tx_read = (wr && !tx_wait) || tx_skip;
assign data = oe_n ? (tx_upper ? tx_data[15:8] : tx_data[7:0]) : 8'hzz;
assign tx_skip = tx_is_send;
// 16 bit transfer
always @(posedge clk or posedge reset)
begin
if (reset) tx_upper <= 0;
else if (wr) tx_upper = tx_is_16bit && !tx_upper;
end
assign tx_wait = tx_is_16bit && !tx_upper;
// send immediate
reg tx_si;
reg tx_siwu;
reg [4:0]send_delay;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
tx_si <= 0;
tx_siwu <= 0;
send_delay <= 0;
end
else
begin
if (tx_is_send && !tx_si) tx_si <= 1;
if (tx_si && (send_delay == 0)) tx_siwu <= 1;
if (tx_si && (send_delay == 16))
begin
tx_si <= 0;
tx_siwu <= 0;
end
if (tx_si || !(send_delay == 5'd0)) send_delay = send_delay + 5'b1;
end
end
assign siwu_n = !tx_siwu;
// === receiver ===========================================================
wire rx_ena;
wire rx_rd = !rxf_n && rx_ready && rx_ena;
reg rx_upper;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
rx_upper <= 0;
rx_mask <= 0;
rx_write <= 0;
rx_data <= 0;
end
else if (rx_ready)
begin
rx_upper <= !rx_upper && rx_rd;
rx_mask <= rx_upper && rx_rd;
rx_write <= rx_upper;
if (rx_rd && !rx_upper) rx_data[7:0] <= data;
if (rx_rd && rx_upper) rx_data[15:8] <= data;
end
end
assign rd_n = !rx_rd;
// === priority logic =====================================================
assign tx_ena = !tx_si;
assign rx_ena = !(tx_ready && !txe_n);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:54 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/title2_1/title2_sim_netlist.v
// Design : title2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "title2,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module title2
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [13:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [13:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [13:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "14" *)
(* C_ADDRB_WIDTH = "14" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "4" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 6.227751 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "title2.mem" *)
(* C_INIT_FILE_NAME = "title2.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "10404" *)
(* C_READ_DEPTH_B = "10404" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "10404" *)
(* C_WRITE_DEPTH_B = "10404" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
title2_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[13:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[13:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "bindec" *)
module title2_bindec
(ena_array,
addra);
output [0:0]ena_array;
input [1:0]addra;
wire [1:0]addra;
wire [0:0]ena_array;
LUT2 #(
.INIT(4'h1))
\/i_
(.I0(addra[1]),
.I1(addra[0]),
.O(ena_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module title2_blk_mem_gen_generic_cstr
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [13:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]ena_array;
wire \ramloop[2].ram.r_n_0 ;
wire \ramloop[2].ram.r_n_1 ;
wire \ramloop[2].ram.r_n_2 ;
wire \ramloop[2].ram.r_n_3 ;
wire \ramloop[2].ram.r_n_4 ;
wire \ramloop[2].ram.r_n_5 ;
wire \ramloop[2].ram.r_n_6 ;
wire \ramloop[2].ram.r_n_7 ;
wire \ramloop[2].ram.r_n_8 ;
wire \ramloop[3].ram.r_n_0 ;
wire \ramloop[3].ram.r_n_1 ;
wire \ramloop[3].ram.r_n_2 ;
wire \ramloop[3].ram.r_n_3 ;
wire \ramloop[3].ram.r_n_4 ;
wire \ramloop[3].ram.r_n_5 ;
wire \ramloop[3].ram.r_n_6 ;
wire \ramloop[3].ram.r_n_7 ;
wire \ramloop[3].ram.r_n_8 ;
wire \ramloop[4].ram.r_n_0 ;
wire \ramloop[4].ram.r_n_1 ;
wire \ramloop[4].ram.r_n_2 ;
wire \ramloop[4].ram.r_n_3 ;
wire \ramloop[4].ram.r_n_4 ;
wire \ramloop[4].ram.r_n_5 ;
wire \ramloop[4].ram.r_n_6 ;
wire \ramloop[4].ram.r_n_7 ;
wire \ramloop[4].ram.r_n_8 ;
wire [0:0]wea;
title2_bindec \bindec_a.bindec_inst_a
(.addra(addra[13:12]),
.ena_array(ena_array));
title2_blk_mem_gen_mux \has_mux_a.A
(.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 (\ramloop[4].ram.r_n_8 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 (\ramloop[2].ram.r_n_8 ),
.DOADO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }),
.DOPADOP(\ramloop[3].ram.r_n_8 ),
.addra(addra[13:12]),
.clka(clka),
.douta(douta[11:3]));
title2_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[0]),
.douta(douta[0]),
.wea(wea));
title2_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[2:1]),
.douta(douta[2:1]),
.wea(wea));
title2_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r
(.addra(addra[11:0]),
.clka(clka),
.dina(dina[11:3]),
.\douta[10] ({\ramloop[2].ram.r_n_0 ,\ramloop[2].ram.r_n_1 ,\ramloop[2].ram.r_n_2 ,\ramloop[2].ram.r_n_3 ,\ramloop[2].ram.r_n_4 ,\ramloop[2].ram.r_n_5 ,\ramloop[2].ram.r_n_6 ,\ramloop[2].ram.r_n_7 }),
.\douta[11] (\ramloop[2].ram.r_n_8 ),
.ena_array(ena_array),
.wea(wea));
title2_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r
(.DOADO({\ramloop[3].ram.r_n_0 ,\ramloop[3].ram.r_n_1 ,\ramloop[3].ram.r_n_2 ,\ramloop[3].ram.r_n_3 ,\ramloop[3].ram.r_n_4 ,\ramloop[3].ram.r_n_5 ,\ramloop[3].ram.r_n_6 ,\ramloop[3].ram.r_n_7 }),
.DOPADOP(\ramloop[3].ram.r_n_8 ),
.addra(addra),
.clka(clka),
.dina(dina[11:3]),
.wea(wea));
title2_blk_mem_gen_prim_width__parameterized3 \ramloop[4].ram.r
(.addra(addra),
.clka(clka),
.dina(dina[11:3]),
.\douta[10] ({\ramloop[4].ram.r_n_0 ,\ramloop[4].ram.r_n_1 ,\ramloop[4].ram.r_n_2 ,\ramloop[4].ram.r_n_3 ,\ramloop[4].ram.r_n_4 ,\ramloop[4].ram.r_n_5 ,\ramloop[4].ram.r_n_6 ,\ramloop[4].ram.r_n_7 }),
.\douta[11] (\ramloop[4].ram.r_n_8 ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module title2_blk_mem_gen_mux
(douta,
addra,
clka,
DOADO,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ,
DOPADOP,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 );
output [8:0]douta;
input [1:0]addra;
input clka;
input [7:0]DOADO;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
input [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ;
input [0:0]DOPADOP;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ;
input [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram ;
wire [7:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 ;
wire [7:0]DOADO;
wire [0:0]DOPADOP;
wire [1:0]addra;
wire clka;
wire [8:0]douta;
wire [1:0]sel_pipe;
wire [1:0]sel_pipe_d1;
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[10]_INST_0
(.I0(DOADO[7]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [7]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [7]),
.I4(sel_pipe_d1[0]),
.O(douta[7]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[11]_INST_0
(.I0(DOPADOP),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1 ),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2 ),
.I4(sel_pipe_d1[0]),
.O(douta[8]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[3]_INST_0
(.I0(DOADO[0]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [0]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [0]),
.I4(sel_pipe_d1[0]),
.O(douta[0]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[4]_INST_0
(.I0(DOADO[1]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [1]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [1]),
.I4(sel_pipe_d1[0]),
.O(douta[1]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[5]_INST_0
(.I0(DOADO[2]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [2]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [2]),
.I4(sel_pipe_d1[0]),
.O(douta[2]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[6]_INST_0
(.I0(DOADO[3]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [3]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [3]),
.I4(sel_pipe_d1[0]),
.O(douta[3]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[7]_INST_0
(.I0(DOADO[4]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [4]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [4]),
.I4(sel_pipe_d1[0]),
.O(douta[4]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[8]_INST_0
(.I0(DOADO[5]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [5]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [5]),
.I4(sel_pipe_d1[0]),
.O(douta[5]));
LUT5 #(
.INIT(32'h0A0ACFC0))
\douta[9]_INST_0
(.I0(DOADO[6]),
.I1(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram [6]),
.I2(sel_pipe_d1[1]),
.I3(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0 [6]),
.I4(sel_pipe_d1[0]),
.O(douta[6]));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[0]),
.Q(sel_pipe_d1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]
(.C(clka),
.CE(1'b1),
.D(sel_pipe[1]),
.Q(sel_pipe_d1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]
(.C(clka),
.CE(1'b1),
.D(addra[0]),
.Q(sel_pipe[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]
(.C(clka),
.CE(1'b1),
.D(addra[1]),
.Q(sel_pipe[1]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module title2_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [0:0]douta;
input clka;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [0:0]dina;
wire [0:0]douta;
wire [0:0]wea;
title2_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module title2_blk_mem_gen_prim_width__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [1:0]douta;
input clka;
input [13:0]addra;
input [1:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [1:0]dina;
wire [1:0]douta;
wire [0:0]wea;
title2_blk_mem_gen_prim_wrapper_init__parameterized0 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module title2_blk_mem_gen_prim_width__parameterized1
(\douta[10] ,
\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[10] ;
output [0:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [8:0]dina;
wire [7:0]\douta[10] ;
wire [0:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
title2_blk_mem_gen_prim_wrapper_init__parameterized1 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.\douta[10] (\douta[10] ),
.\douta[11] (\douta[11] ),
.ena_array(ena_array),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module title2_blk_mem_gen_prim_width__parameterized2
(DOADO,
DOPADOP,
clka,
addra,
dina,
wea);
output [7:0]DOADO;
output [0:0]DOPADOP;
input clka;
input [13:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [7:0]DOADO;
wire [0:0]DOPADOP;
wire [13:0]addra;
wire clka;
wire [8:0]dina;
wire [0:0]wea;
title2_blk_mem_gen_prim_wrapper_init__parameterized2 \prim_init.ram
(.DOADO(DOADO),
.DOPADOP(DOPADOP),
.addra(addra),
.clka(clka),
.dina(dina),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module title2_blk_mem_gen_prim_width__parameterized3
(\douta[10] ,
\douta[11] ,
clka,
addra,
dina,
wea);
output [7:0]\douta[10] ;
output [0:0]\douta[11] ;
input clka;
input [13:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [8:0]dina;
wire [7:0]\douta[10] ;
wire [0:0]\douta[11] ;
wire [0:0]wea;
title2_blk_mem_gen_prim_wrapper_init__parameterized3 \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.\douta[10] (\douta[10] ),
.\douta[11] (\douta[11] ),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module title2_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [0:0]douta;
input clka;
input [13:0]addra;
input [0:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [0:0]dina;
wire [0:0]douta;
wire [0:0]wea;
wire [15:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED ;
wire [15:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000004000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(1),
.READ_WIDTH_B(1),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(1),
.WRITE_WIDTH_B(1))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram
(.ADDRARDADDR(addra),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED [15:1],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module title2_blk_mem_gen_prim_wrapper_init__parameterized0
(douta,
clka,
addra,
dina,
wea);
output [1:0]douta;
input clka;
input [13:0]addra;
input [1:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [1:0]dina;
wire [1:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000003000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(2),
.READ_WIDTH_B(2),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(2),
.WRITE_WIDTH_B(2))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:2],douta}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module title2_blk_mem_gen_prim_wrapper_init__parameterized1
(\douta[10] ,
\douta[11] ,
clka,
ena_array,
addra,
dina,
wea);
output [7:0]\douta[10] ;
output [0:0]\douta[11] ;
input clka;
input [0:0]ena_array;
input [11:0]addra;
input [8:0]dina;
input [0:0]wea;
wire [11:0]addra;
wire clka;
wire [8:0]dina;
wire [7:0]\douta[10] ;
wire [0:0]\douta[11] ;
wire [0:0]ena_array;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000060000000000000000000000000800000000000000),
.INITP_01(256'h00000078001F80000000000000000001800078000000000000000000040001E0),
.INITP_02(256'h00000C00000000000003E001FC0000300000000000001F0007E0000000000000),
.INITP_03(256'h0000000FF00FF80007E00000000000003F803FE0000F80000000000000FC007F),
.INITP_04(256'hFC03FFC0000000000000FFC0FFE003FE00000000000003FE03FF8007F8000000),
.INITP_05(256'h00000001FFE7FFE0FFFC00000000000007FF0FFF80FFF00000000000001FF83F),
.INITP_06(256'hFFFFFFF00000000000001FFFFFFFFFFFC00000000000007FFDFFFC3FFF000000),
.INITP_07(256'h0001F0007FFFFFFFFFFF00078000070001FFFFFFFFFFFC00070000200007FFFF),
.INITP_08(256'hFFFFFFFE0FFC00001FF807FFFFFFFFFFF00FF000007F801FFFFFFFFFFFC00FE0),
.INITP_09(256'h00003FFFCFFFFFFFFFFFFFFFC00000FFF87FFFFFFFFFFF8FFF000003FF81FFFF),
.INITP_0A(256'hFFFFFFFFFFFC000001FFFFFFFFFFFFFFFFFFF8000007FFFBFFFFFFFFFFFFFFF0),
.INITP_0B(256'h000001FFF9FFFFFFFFFFFFFFC000000FFFE7FFFFFFFFFFFFFF0000007FFFFFFF),
.INITP_0C(256'hFFFFFFFFFFFC0000001FFF3FFFFFFFFFFFFFF00000007FFE7FFFFFFFFFFFFFE0),
.INITP_0D(256'h0000001FFCFF8EFFFFFFFFFF80000000FFFBFFFFFFFFFFFFFF00000003FFC7FE),
.INITP_0E(256'hF79FFFFFFFFFFC000001FFDFF79CFFFFFFFFFFC0000007FF3FE1BFFFFFFFFFE0),
.INITP_0F(256'hFFFF03FFFE3FE3F9BFFFFFFFFFFFF003FFF9FF1FC7FFFFFFFFFFFF0001FFF7FC),
.INIT_00(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_01(256'h9E9E9E9EE09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_02(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_03(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_04(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_05(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E09E),
.INIT_06(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_07(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_08(256'h9E9E9E9E9EE09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E09E9E9E9E9E),
.INIT_09(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_0A(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_0B(256'hE09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E09E9E9E9E9E9E9E9E9E9E9E),
.INIT_0C(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0),
.INIT_0D(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_0E(256'h9E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_0F(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E09E9E9E),
.INIT_10(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_11(256'h9E9E00009EE0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_12(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E09E9E9E9E9E9E9E9E),
.INIT_13(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_14(256'hE0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E09E9E9E9E),
.INIT_15(256'h9E9E9E9E9E9E9E9E9E9E009E9E9EE0E0E0E0E09E9E9E9E9E9E9E9E9E000000E0),
.INIT_16(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_17(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E09E9E9E9E9E9E9E9E9E9E),
.INIT_18(256'h9E9E9E9E00009E9EE0E0E0E0E0E09E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0),
.INIT_19(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_1A(256'h9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_1B(256'h0000E0E0E0E0E0E0E09E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E09E9E9E9E9E),
.INIT_1C(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000),
.INIT_1D(256'h9E9E9E9E9EE0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_1E(256'hE0E0E0E09E9E9E9E9E000000E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E),
.INIT_1F(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0),
.INIT_20(256'hE0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_21(256'h9E9E9E000000E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9EE0E0E0),
.INIT_22(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E09E),
.INIT_23(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_24(256'hE0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E09E),
.INIT_25(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E0E09E9E9E000000),
.INIT_26(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_27(256'hE0E0E0E0E0E09E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E),
.INIT_28(256'h9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E09E9E000000E0E0E0E0E0E0),
.INIT_29(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_2A(256'hE09E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_2B(256'h9E00000000E0E0E0E0E0E0E0E0E0E0E09E000000E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_2C(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_2D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_2E(256'hE0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E),
.INIT_2F(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0),
.INIT_30(256'hE0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_31(256'hE0E0E0E0E0E000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9EE0E0E0E0E0E0),
.INIT_32(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0),
.INIT_33(256'hE0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_34(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_35(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_36(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_37(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E),
.INIT_38(256'h9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_39(256'h9E9E9E9E9EE0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE09E9E9E9E9E),
.INIT_3A(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E),
.INIT_3B(256'h9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_3C(256'hE09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E09E9E9E9E9E9E9E9E),
.INIT_3D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0),
.INIT_3E(256'h00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_3F(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E09E9E9E9E9E9E9E9E9E000000),
.INIT_40(256'hE0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E09E9E9E9E9E),
.INIT_41(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_42(256'h9E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E09E9E9E9E9E9E00000000E0E0E0E0E0),
.INIT_43(256'hE0E0E0E09E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_44(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_45(256'h9E9E9EE0E0E0E0E0E0E0E0E0E09E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0),
.INIT_46(256'h9E9E9E9EE0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00),
.INIT_47(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E),
.INIT_48(256'hE0E0E0E0E0E0E0E0E09E9E9E000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_49(256'hE0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0),
.INIT_4A(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9EE0E0E0E0),
.INIT_4B(256'hE0E0E0E0E09E000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_4C(256'hE0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0),
.INIT_4D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_4E(256'hE0E00000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_4F(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_50(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E),
.INIT_51(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_52(256'h9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000E0E0),
.INIT_53(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E),
.INIT_54(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_55(256'h9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0FEE0E0E0E0E0E0),
.INIT_56(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_57(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_58(256'h00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0FEFEE0E0E0E0E0E0E0E0E0E0E0),
.INIT_59(256'hE0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000),
.INIT_5A(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_5B(256'hE0E0E0E0E0E0E0E0E0E0E00000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_5C(256'hE0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0),
.INIT_5D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_5E(256'hE0E0E0E0E00000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_5F(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0),
.INIT_60(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E),
.INIT_61(256'h00FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_62(256'h9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E000),
.INIT_63(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_64(256'hE0E0E0E0E0E0E0FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_65(256'h9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEFEE0E0),
.INIT_66(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_67(256'hE0FEFEE0FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_68(256'h9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEE0E0E0E0E0E0E0E000),
.INIT_69(256'hE0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_6A(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_6B(256'hE0E0E0E0E0E0E0E0E0E0E0E0E000FEFEFEE0E0E0E0E0E0E0E0FEFEFEFEFEFEFE),
.INIT_6C(256'hE09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000),
.INIT_6D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_6E(256'hE0E0E0E0E0E00000FEFEFEE0E0E0E0E0E0000000FEFEFE00FEFEE0E0E0E0E0E0),
.INIT_6F(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0),
.INIT_70(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E),
.INIT_71(256'h0000FEFEFEE0E0E0E0E0E000000000FEFE00FEFEE0E0FEFEE0E0E0E0E0E0E0E0),
.INIT_72(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0),
.INIT_73(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E),
.INIT_74(256'hE0E0E0E000FEFEFEFE0000FEFEFE0000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_75(256'h9E9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E000FEFEFEFEE0),
.INIT_76(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E),
.INIT_77(256'hFEFEFEFE00FEFEE0E00000FEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_78(256'h9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0E0E000FEFEFEE0E0E0E0E0E00000),
.INIT_79(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E),
.INIT_7A(256'hFEFE000000FEFEE0E0FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_7B(256'hE0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEE0E0E0E0E0E0000000FEFEFEFEFE),
.INIT_7C(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9EE0E0),
.INIT_7D(256'hFE00FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_7E(256'hE0E0E0E0E0E0E0000000FEFEE0E0E0E0E0E0E0000000FEFEFEFEFEE0E00000FE),
.INIT_7F(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[10] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\douta[11] }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module title2_blk_mem_gen_prim_wrapper_init__parameterized2
(DOADO,
DOPADOP,
clka,
addra,
dina,
wea);
output [7:0]DOADO;
output [0:0]DOPADOP;
input clka;
input [13:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0 ;
wire [7:0]DOADO;
wire [0:0]DOPADOP;
wire [13:0]addra;
wire clka;
wire [8:0]dina;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h7BFF5FFFFFFFFFFF80FFFFFFFFC7F1FFFFFFFFFFFFC3FFFFDFFC3EEFFFFFFFFF),
.INITP_01(256'hFFF001FFFF7FF3F98F7FFFFFFFFFE00FFFFFFF8DE7F3FFFFFFFFFFC03FFFFFFE),
.INITP_02(256'hC7C7E7F3FFFFFFF80007FFF1FF3F9FDFEFFFFFFFF0003FFFCFFCDE63FFFFFFFF),
.INITP_03(256'hFF000007FFFFCE7CE7FFBFFFFFFC00003FFFFFF9F39EFEFFFFFFFC0001FFFE7F),
.INITP_04(256'h1FFE79F0FFCFFFC000003FFFFCFFF1E787FF7FFF000001FFFFF3FE3DBEFFFFFF),
.INITP_05(256'hFFFE00007FFFF8E71FFFDCFCFFFFC00001FFFFE719EFFE7FF3FFFC000007FFFF),
.INITP_06(256'hFFC79BFC7EE3FFFFFC001FFFFFFE3C7DFBE13FFFFFC0003FFFFFF8E1EFE70FFF),
.INITP_07(256'hFFFFFC01FFFFFFFE19C7CFF3C7FFFFF803FFFFFFF9E77F3FFC7FFFFF8007FFFF),
.INITP_08(256'hFFFFEFFF33CFFFFFFE003FFFFFFFFF3FFCEF3F9FFFFC007FFFFFFFC6F9F3CCF0),
.INITP_09(256'hFFF80007FFFFFFFFFFFFF73C7FFFFC000FFFFFFFFFF9FF8CF1FFFFFC001FFFFF),
.INITP_0A(256'hFFFFFFFF3FCFFFF800003FFFFFFFFFFFFE7FFFDFFC0001FFFFFFFFFFFFF9CF9F),
.INITP_0B(256'hFFFC0000007FFFFFFFFFF8F8EFFFE000000FFFFFFFFFFFC7F7FFFF0000007FFF),
.INITP_0C(256'hFFFFFFFFFCFF3FFFF0000000FFFFFFFFFFF3FCFFFF80000007FFFFFFFFFE1E33),
.INITP_0D(256'h3FFFFC000003FFFFFFFFFFFFF8FFFFC000000FFFFFFFFFFFFFC3FFFE0000003F),
.INITP_0E(256'hFFFFFFFFFFFFF1FFFFF000007FFFFFFFFFFFFFCFFFFF000001FFFFFFFFFFFFFF),
.INITP_0F(256'hFFFFFFF00001FFFFFFFFFFFFFFBFFFFFC00007FFFFFFFFFFFFFE7FFFFC00001F),
.INIT_00(256'hE0FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_01(256'hE0E000E0E0E0E0E0E0E0E0E0E0FE00000000FEFEFEFEE000FEE0FE00FEFEFEFE),
.INIT_02(256'hE0E0E0E0E0E0E0E0E0E09E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_03(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_04(256'hE0E0E0E0E0E0E0E0FEFE000000FEFEFEFEFEFEFE000000FEFEFEFEFEFEE0E0E0),
.INIT_05(256'hE09E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_06(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_07(256'h00FEFEFEFE00FEFEFEFEFEFEFEFEFEFE00FE00FEFEFEFEFEE0E0E0E0E0E0E0E0),
.INIT_08(256'h9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000),
.INIT_09(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E),
.INIT_0A(256'hFEFEFE0000FEFEFEFEFEFEE00000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_0B(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0FEE0E0E0E0E0E0E0E0000000FEFE00FE),
.INIT_0C(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0009E9E9E9E9E9E9E00E0E0E0E0),
.INIT_0D(256'hFE000000FEFEFEFE00FEE0E0E0E0E0E0E0FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_0E(256'hE0E0E0E0E0E0E0E000E0FEFEFEE0E0E0E0E0E0E00000FEFEFEFEFEFEFE0000FE),
.INIT_0F(256'hE0E0E0E0E0E0E0E0E0E0E0E000009E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0),
.INIT_10(256'hFEFEFEE0E0E0E0E0E0E0E0E0FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_11(256'hE0E00000FEFEFEE0E0E0E0E0E0E00000FEFE00FEFEFEE00000FEFE000000FEFE),
.INIT_12(256'hE0E0E0E000009E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_13(256'hE0E0E000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_14(256'hFEE0E0E0E0E0E0E00000FEFEFEFEFEE0E00000FEFEFEFEFEFEFE00FEFEFEE0E0),
.INIT_15(256'h9E9E9E9E9E9E00000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FE),
.INIT_16(256'hFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0009E9E),
.INIT_17(256'hFEE0000000FEFEFEFEE0000000FEFEFEFEFEFE0000FEFEFEE0E0E0E00000FEFE),
.INIT_18(256'h9E000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0),
.INIT_19(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000009E9E9E9E9E9E9E9E),
.INIT_1A(256'hFEFEFEE00000FEFEFE0000FEFEFEFE00FEFEE0E0E0E0E000FEFEFEE0E0E0E0E0),
.INIT_1B(256'h0000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0FEFE0000FE),
.INIT_1C(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E000009E9E9E9E9E9E9E9E9E9E9E9E00000000),
.INIT_1D(256'hFEFEFE0000FEFEFEFEFEFEFEE0E0E0FEFE00FEFEE0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_1E(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFE0000FEFEFEFEE00000),
.INIT_1F(256'hE0E0E0E0E0E0E0E0009E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000E0E0E0),
.INIT_20(256'hFE00FEFEFEFEE000E0FEFEFEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_21(256'hE0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEFEFEFEFEFEE0000000FEFEFEFE00FE),
.INIT_22(256'h00009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000E0E0E0E0E0E0E0E0E0),
.INIT_23(256'hE000000000FEFEFEE0E0E0E0E0E0E0E000E0E0FEE0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_24(256'hE0E0E0E0E0E00000FEFEFEFEFEFEFEFEE0E0FEFE000000FEFEFEFE0000FEFEE0),
.INIT_25(256'h9E9E9E9E9E9E9E9E9E9E9E9E000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_26(256'hFEFEFEFEE0E0E0E0E0E00000FEFEFEE0E0E0E0E0E0E0E0E0E0E0009E9E9E9E9E),
.INIT_27(256'h000000FEFEFEFEFEFEFEFEE0FEFEFE0000FEFEFEFE0000FEFEE0E0E000000000),
.INIT_28(256'h9E9E9E9E9E9E9E000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_29(256'hE0E0FEE00000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E),
.INIT_2A(256'h000000FEFE0000FEFEFEFE00FEFEFEFEFEFEFEE0E0E0E00000FEFEFEFEFEFEFE),
.INIT_2B(256'h9E9E0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFE),
.INIT_2C(256'hFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_2D(256'h000000FEFEFEFEFEFEFEFEFEFEE0E0E0E0E000FEFEFE0000FEFEFEE0FEFE0000),
.INIT_2E(256'h00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000E0E0E00000FEFEFE),
.INIT_2F(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E00000000),
.INIT_30(256'hFEFEFE00FEFEFEE0E0E0E00000FEFEE000000000FEFEFEFEFEFEFEFEE0E0E0E0),
.INIT_31(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFE00000000FE),
.INIT_32(256'hE0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0),
.INIT_33(256'hFEE0E0E0E000FEFEFEFEE000000000FE0000FEFEFEFEE0E0E0E0E0E0E0E0E0E0),
.INIT_34(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFEE0000000FEFEFEFEFE00FE),
.INIT_35(256'hE0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_36(256'h00FEFEE0E0E0E000E0E0FE000000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_37(256'hE0E0E0E0E0E0E0E0E0E0000000FEFEE0E00000FEFE00FEFEFEFEE0E0E0E00000),
.INIT_38(256'hE09E9E9E9E9E9E9E9E9E9E9E00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_39(256'hE0E0E0E0FEFE000000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_3A(256'hE0E0E0E0E00000FEFEFEFE0000FEFEFE00FEFEFEFEE0E0E00000FEFEFEE0E0E0),
.INIT_3B(256'h9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_3C(256'hE0E0000000FEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E),
.INIT_3D(256'h000000FEFE0000FEFEE0000000E0FEE0E0E00000FEFEFEE0E0E0FEFE0000FEFE),
.INIT_3E(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000),
.INIT_3F(256'hFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9EE0),
.INIT_40(256'hFEFEFEE0E00000E0E0E0E0E00000FEFEE0E00000FEFE0000FEFEFEE000000000),
.INIT_41(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEE000),
.INIT_42(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E00E0E0E0E0E0E0E0),
.INIT_43(256'hE0E0E0E0E0E00000FEFEE000FEFEFEFE0000FEFEFEE0E0E0E00000E0E0E0E0E0),
.INIT_44(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEE0E0E0),
.INIT_45(256'hE0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_46(256'h0000FEFE0000FEFEFEFE0000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_47(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000FEFEFEE0E0E0E0E0E0E0E0E0),
.INIT_48(256'h00009E9E9E9E9E9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_49(256'hFEFEE0E0000000FEFEE0E0FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000),
.INIT_4A(256'hE0E0E0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0E0E0E0000000FEFE0000),
.INIT_4B(256'h9E9E9E9EE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_4C(256'h00FEFEFEFEFEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E000000000009E9E9E9E9E),
.INIT_4D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E000FEFEFE0000FEFEE0E00000),
.INIT_4E(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_4F(256'hFEFEFEE0E0E0E0E0E0E0E0E0E000000000009E9E9E9E9E9E9E9E9E9E9EE0E0E0),
.INIT_50(256'hE0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEE00000E0E0E0E0E00000FEFEFEFEFE),
.INIT_51(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_52(256'hE0E0E0E0E0E00000000000009E9E9E9E9E9E9E9E9E9E00E0E0E0E0E0E0E0E0E0),
.INIT_53(256'hE0E0E0E0E0E0E00000FEFEE0E0E0E0E0E0E0E0FEFEFEFEFEFEFE00E0E0E0E0E0),
.INIT_54(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_55(256'h00009E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_56(256'h0000FEFEFEE0E0E0E0E00000FEFEFEFEFEFEE0E0E0E0E0E0E0E0E0E0E0000000),
.INIT_57(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_58(256'h9E9E9E9E9E9E9E9E000000000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_59(256'hE0E0E0E000FEFEFEFEFEFEFEE0E0E0E0E0E0E0E0E0E0E0E00000009E9E9E9E9E),
.INIT_5A(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFE),
.INIT_5B(256'h9E9E00000000000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_5C(256'hFEFEFE00FEFEFEE0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_5D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFEFEE0000000),
.INIT_5E(256'h000000000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_5F(256'hFEE0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000),
.INIT_60(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E000000000FEFEFEE0000000E0FE0000FEFE),
.INIT_61(256'h0000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_62(256'hE0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000000000),
.INIT_63(256'hE0E0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0E00000FEFEFEE0E0E0E0E0),
.INIT_64(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_65(256'hE0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000000000000000),
.INIT_66(256'hE0E0E0E0E0E00000E0E0E0E0E0E0E0E00000FEFEFEFEE0E0E0E0E0E0E0E0E0E0),
.INIT_67(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_68(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000000000E0E0E0E0E0E0),
.INIT_69(256'hE0E0E0E0E0E0E0E0E0E000000000FEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E),
.INIT_6A(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_6B(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_6C(256'hE0E0E0E0E0000000FEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E),
.INIT_6D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_6E(256'h9E9E9E9E9E9E9E9E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_6F(256'h0000FEFEFEE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E),
.INIT_70(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_71(256'h9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_72(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_73(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEFEFEE0),
.INIT_74(256'h00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_75(256'hE0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00),
.INIT_76(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000FEFEFEE0E0E0E0E0E0),
.INIT_77(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_78(256'hE0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0E0),
.INIT_79(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E00000FEE0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_7A(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_7B(256'hE0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0E0E0E0E0E0E0E0),
.INIT_7C(256'hE0E0E0E0E0E0E0E0E000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_7D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_7E(256'h9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_7F(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],DOADO}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],DOPADOP}),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0 ),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0
(.I0(addra[12]),
.I1(addra[13]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module title2_blk_mem_gen_prim_wrapper_init__parameterized3
(\douta[10] ,
\douta[11] ,
clka,
addra,
dina,
wea);
output [7:0]\douta[10] ;
output [0:0]\douta[11] ;
input clka;
input [13:0]addra;
input [8:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ;
wire [13:0]addra;
wire clka;
wire [8:0]dina;
wire [7:0]\douta[10] ;
wire [0:0]\douta[11] ;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'hFFFFFFFFFFFFFFFF000000003FFFFFFFFFFFFFFFF8000000007FFFFFFFFFFFFF),
.INITP_01(256'hFFFE00000000FE0FFFFFFFFFFFFFF000000003FE7FFFFFFFFFFFFFC00000000F),
.INITP_02(256'h003FFF1FFFFFFFFFF00000001E00FFFFFFFFFFFFFF800000007C03FFFFFFFFFF),
.INITP_03(256'hC07FE00000000003FFC1FFFFFF87FF80000000000FFF87FFFFFEFFFC00000000),
.INITP_04(256'h000FE001FF07FC001F00000000003FE007FE3FF003FC0000000000FFE03FFCFF),
.INITP_05(256'hE000000000000000F80007E01FC000480000000003E0003F80FF0000E0000000),
.INITP_06(256'h000000000C000C0000000000000008000038003800000000000000380001F003),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_01(256'h9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_02(256'hE0E0E0E0E000000000000000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_03(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_04(256'h0000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_05(256'h00000000000000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_06(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_07(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_08(256'h0000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000E0E0E0E0),
.INIT_09(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000000000),
.INIT_0A(256'h00E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_0B(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E000),
.INIT_0C(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000000000000000000000),
.INIT_0D(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_0E(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E00000000000E0E0E0E0),
.INIT_0F(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_10(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_11(256'h9E9E9E9E9E9E9E0000E0E0E0E0E00000000000000000E0E0E0E0E0E0E0E0E0E0),
.INIT_12(256'hE0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_13(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_14(256'h9E0000E0E0E0E0000000000000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_15(256'hE0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_16(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_17(256'h0000009E9E9E00000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0000000E0E0E0E0E0),
.INIT_18(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E0000000000),
.INIT_19(256'hE0E0E0E0E0E0E0E0E0E0E0E0E0E0E000E0E0E0E0E0E0E0E0E0E0E0E0E0E09E9E),
.INIT_1A(256'h9E000000E0E0E0E0E0E0E0E0E0E0E0E0E000000000E0E0E0E0E0E0E0E0E0E0E0),
.INIT_1B(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000009E9E9E9E),
.INIT_1C(256'hE0E0E0E0E0E0E0E0E000000000E0E0E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E),
.INIT_1D(256'hE0E0E0E0E0E0E0E0E0E00000000000E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0E0),
.INIT_1E(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E9E9E9E9E9E000000E0E0),
.INIT_1F(256'hE0E000000000000000E0E0E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_20(256'hE0E0E000000000000000E0E0E0E0E0E0E0E0E0E0E0E00000E0E0E0E0E0E0E0E0),
.INIT_21(256'h9E9E9E9E9E9E9E9E0000009E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0),
.INIT_22(256'h000000000000E0E0E0E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_23(256'h0000000000E0E0E0E0E0E0E0E0E0E0000000E0E0E0E0E0E0E0E0E0E000000000),
.INIT_24(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E0E0E000009E0000),
.INIT_25(256'h000000E0E0E0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_26(256'hE0E0E0E0E0E0E0E00000000000E0E0E0E0E0E0E0E0E000000000000000000000),
.INIT_27(256'h9E9E9E9E9E9E9E9E9E000000E0E0E0E0E0E0E000009E9E9E00000000000000E0),
.INIT_28(256'hE0E0E09E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_29(256'hE000000000000000E0E0E0E0E0E0E0E09E9E0000000000000000000000000000),
.INIT_2A(256'h9E9E9E000000E0E0E0E0E0000000009E9E9E9E00000000000000E0E0E0E0E0E0),
.INIT_2B(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_2C(256'h000000E0E0E0E0E0E0E09E9E9E9E0000000000000000000000FF9E9EE09E9E9E),
.INIT_2D(256'hE0E0E0E0E000009E9E9E9E9E9E9E9E000000000000E0E0E0E0E0E09E9E000000),
.INIT_2E(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000),
.INIT_2F(256'hE0E0E09E9E9E9E9E9E00000000000000000000009E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_30(256'h9E9E9E9E9E9E9E9E9E000000000000E0E0E0E0E09E9E9E00000000000000E0E0),
.INIT_31(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E0E0E000009E),
.INIT_32(256'h9E9E9E9E9E9E0000000000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_33(256'h9E9E9E9E9E0000000000E0E0E09E9E9E9E9E0000000000000000E0E0E09E9E9E),
.INIT_34(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000E000009E9E9E9E9E9E9E9E9E),
.INIT_35(256'h9E9E9E0000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_36(256'h00000000E0E09E9E9E9E9E9E9E00000000000000E0E09E9E9E9E9E9E9E9E9E9E),
.INIT_37(256'h9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00),
.INIT_38(256'h9E9E009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_39(256'h9E9E9E9E9E9E9E9E0000000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_3A(256'h9E9E9E9E9E0000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E000000000000),
.INIT_3B(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_3C(256'h9E9E9E00000000009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_3D(256'h009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00000000009E9E9E9E9E9E9E),
.INIT_3E(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00),
.INIT_3F(256'h00009E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_40(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E00009E9E9E9E9E9E9E9E9E9E9E9E9E0000),
.INIT_41(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_42(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_43(256'h9E9E9E9E9E9E9E9E9E00009E9E9E9E9E9E9E9E9E9E9E9E9E0000009E9E9E9E9E),
.INIT_44(256'h9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E9E),
.INIT_45(256'h000000000000000000000000000000000000000000000000000000009E9E9E9E),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra[11:0],1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,dina[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:8],\douta[10] }),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:1],\douta[11] }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1
(.I0(addra[13]),
.I1(addra[12]),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_i_1_n_0 ));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module title2_blk_mem_gen_top
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [13:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
title2_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "14" *) (* C_ADDRB_WIDTH = "14" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "4" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 6.227751 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "title2.mem" *)
(* C_INIT_FILE_NAME = "title2.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "10404" *) (* C_READ_DEPTH_B = "10404" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "10404" *) (* C_WRITE_DEPTH_B = "10404" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module title2_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [13:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [13:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [13:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [13:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[13] = \<const0> ;
assign rdaddrecc[12] = \<const0> ;
assign rdaddrecc[11] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[13] = \<const0> ;
assign s_axi_rdaddrecc[12] = \<const0> ;
assign s_axi_rdaddrecc[11] = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
title2_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module title2_blk_mem_gen_v8_3_5_synth
(douta,
addra,
clka,
dina,
wea);
output [11:0]douta;
input [13:0]addra;
input clka;
input [11:0]dina;
input [0:0]wea;
wire [13:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
title2_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
/**
* lpflow_inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_BEHAVIORAL_V
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions: YCbCr to RGB Color Doamin Converter.
// ( 10 Bits Resolution )
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Johnny Chen :| 05/09/05 :| Initial Revision
// --------------------------------------------------------------------
module YCbCr2RGB
(
// input data
iY,
iCb,
iCr,
// output data
Red,
Green,
Blue,
// controller
oDVAL,
iDVAL,
iRESET,
iCLK
);
// Input
input [7:0] iY,iCb,iCr;
input iDVAL,iRESET,iCLK;
// Output
output [9:0] Red,Green,Blue;
output reg oDVAL;
// Internal Registers/Wires
reg [9:0] oRed,oGreen,oBlue;
reg [3:0] oDVAL_d;
reg [19:0] X_OUT,Y_OUT,Z_OUT;
wire [26:0] X,Y,Z;
assign Red = oRed;
assign Green= oGreen;
assign Blue = oBlue;
always@(posedge iCLK)
begin
if(iRESET)
begin
oDVAL<=0;
oDVAL_d<=0;
oRed<=0;
oGreen<=0;
oBlue<=0;
end
else
begin
// Red
if(X_OUT[19])
oRed<=0;
else if(X_OUT[18:0]>1023)
oRed<=1023;
else
oRed<=X_OUT[9:0];
// Green
if(Y_OUT[19])
oGreen<=0;
else if(Y_OUT[18:0]>1023)
oGreen<=1023;
else
oGreen<=Y_OUT[9:0];
// Blue
if(Z_OUT[19])
oBlue<=0;
else if(Z_OUT[18:0]>1023)
oBlue<=1023;
else
oBlue<=Z_OUT[9:0];
// Control
{oDVAL,oDVAL_d}<={oDVAL_d,iDVAL};
end
end
always@(posedge iCLK)
begin
if(iRESET)
begin
X_OUT<=0;
Y_OUT<=0;
Z_OUT<=0;
end
else
begin
X_OUT<=( X - 114131 ) >>7;
Y_OUT<=( Y + 69370 ) >>7;
Z_OUT<=( Z - 141787 ) >>7;
end
end
// Y 596, 0, 817
MAC_3 u0( iY, iCb, iCr,
17'h00254, 17'h00000, 17'h00331,
X, iRESET, iCLK);
// Cb 596, -200, -416
MAC_3 u1( iY, iCb, iCr,
17'h00254, 17'h3FF38, 17'h3FE60,
Y, iRESET, iCLK);
// Cr 596, 1033, 0
MAC_3 u2( iY, iCb, iCr,
17'h00254, 17'h00409, 17'h00000,
Z, iRESET, iCLK);
endmodule
|
module s400 (
TEST,
FM,
blif_clk_net,
CLR,
blif_reset_net,
YLW1,
RED2,
GRN1,
RED1,
YLW2,
GRN2);
// Start PIs
input TEST;
input FM;
input blif_clk_net;
input CLR;
input blif_reset_net;
// Start POs
output YLW1;
output RED2;
output GRN1;
output RED1;
output YLW2;
output GRN2;
// Start wires
wire net_166;
wire net_107;
wire net_47;
wire net_179;
wire GRN1;
wire net_176;
wire net_159;
wire net_61;
wire net_137;
wire net_132;
wire net_54;
wire net_105;
wire net_62;
wire net_6;
wire net_129;
wire net_119;
wire net_98;
wire net_23;
wire net_117;
wire net_12;
wire net_151;
wire net_74;
wire net_53;
wire net_93;
wire net_210;
wire net_205;
wire net_168;
wire net_135;
wire net_130;
wire net_147;
wire net_127;
wire net_14;
wire net_113;
wire net_26;
wire net_76;
wire blif_clk_net;
wire net_101;
wire net_32;
wire net_187;
wire net_111;
wire net_90;
wire net_40;
wire net_100;
wire net_85;
wire net_69;
wire net_124;
wire net_161;
wire CLR;
wire net_141;
wire net_160;
wire net_83;
wire net_115;
wire RED1;
wire net_4;
wire net_95;
wire net_17;
wire net_173;
wire net_78;
wire net_27;
wire net_164;
wire net_56;
wire net_87;
wire net_0;
wire net_155;
wire net_35;
wire net_191;
wire net_16;
wire net_22;
wire net_181;
wire net_193;
wire net_39;
wire net_157;
wire net_144;
wire net_102;
wire net_2;
wire net_59;
wire net_9;
wire net_42;
wire net_120;
wire net_201;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_162;
wire YLW1;
wire FM;
wire net_96;
wire net_66;
wire net_38;
wire net_44;
wire net_167;
wire net_207;
wire net_199;
wire net_136;
wire net_134;
wire net_19;
wire net_89;
wire net_45;
wire net_126;
wire net_185;
wire net_34;
wire net_108;
wire net_183;
wire TEST;
wire net_178;
wire net_208;
wire net_150;
wire net_63;
wire net_212;
wire net_152;
wire net_30;
wire net_116;
wire net_189;
wire net_175;
wire net_91;
wire net_24;
wire net_55;
wire net_99;
wire net_106;
wire net_186;
wire net_46;
wire net_140;
wire net_118;
wire net_148;
wire net_104;
wire net_146;
wire net_72;
wire net_122;
wire net_25;
wire net_7;
wire net_70;
wire net_194;
wire net_172;
wire net_5;
wire net_52;
wire net_165;
wire net_128;
wire net_138;
wire net_13;
wire net_184;
wire net_94;
wire net_11;
wire net_18;
wire net_123;
wire net_131;
wire net_114;
wire net_196;
wire net_170;
wire net_29;
wire net_68;
wire net_214;
wire net_149;
wire net_142;
wire net_77;
wire net_20;
wire net_31;
wire net_36;
wire net_49;
wire net_158;
wire net_15;
wire net_41;
wire net_57;
wire net_198;
wire net_71;
wire net_209;
wire net_153;
wire net_156;
wire net_3;
wire net_84;
wire net_174;
wire net_154;
wire net_1;
wire net_92;
wire net_112;
wire net_103;
wire net_213;
wire net_139;
wire net_43;
wire YLW2;
wire net_10;
wire net_180;
wire net_28;
wire net_169;
wire net_21;
wire net_51;
wire net_171;
wire net_79;
wire net_143;
wire net_97;
wire net_190;
wire net_88;
wire net_182;
wire net_192;
wire net_145;
wire net_60;
wire net_197;
wire net_204;
wire net_81;
wire RED2;
wire net_163;
wire net_58;
wire GRN2;
wire net_67;
wire net_82;
wire net_64;
wire net_202;
wire net_37;
wire net_188;
wire net_110;
wire net_121;
wire net_73;
wire net_200;
wire net_48;
wire net_33;
wire net_177;
wire net_8;
wire net_75;
wire net_86;
wire net_211;
wire net_133;
wire net_206;
wire net_203;
wire net_195;
wire net_125;
// Start cells
AND4_X4 inst_145 ( .ZN(net_86), .A1(net_80), .A4(net_73), .A2(net_47), .A3(net_37) );
INV_X2 inst_103 ( .A(net_136), .ZN(net_135) );
DFFR_X2 inst_125 ( .RN(net_118), .D(net_43), .QN(net_6), .CK(net_209) );
CLKBUF_X2 inst_207 ( .A(net_172), .Z(net_201) );
DFFR_X1 inst_138 ( .RN(net_118), .D(net_97), .QN(RED2), .CK(net_177) );
CLKBUF_X2 inst_159 ( .A(net_152), .Z(net_153) );
CLKBUF_X2 inst_218 ( .A(net_211), .Z(net_212) );
NOR3_X2 inst_15 ( .A1(net_132), .A2(net_112), .ZN(net_75), .A3(net_54) );
CLKBUF_X2 inst_197 ( .A(net_190), .Z(net_191) );
DFFR_X1 inst_134 ( .RN(net_118), .D(net_72), .Q(YLW2), .CK(net_200) );
CLKBUF_X2 inst_179 ( .A(net_172), .Z(net_173) );
NOR2_X4 inst_24 ( .A1(net_130), .ZN(net_100), .A2(net_29) );
INV_X2 inst_114 ( .ZN(net_15), .A(net_10) );
XNOR2_X1 inst_6 ( .ZN(net_101), .A(net_100), .B(net_99) );
CLKBUF_X2 inst_194 ( .A(net_187), .Z(net_188) );
DFFR_X2 inst_131 ( .RN(net_118), .D(net_103), .QN(net_12), .CK(net_173) );
NAND2_X2 inst_76 ( .A1(net_141), .ZN(net_110), .A2(net_109) );
CLKBUF_X2 inst_214 ( .A(net_207), .Z(net_208) );
CLKBUF_X2 inst_180 ( .A(net_145), .Z(net_174) );
CLKBUF_X2 inst_160 ( .A(net_153), .Z(net_154) );
CLKBUF_X2 inst_150 ( .A(blif_clk_net), .Z(net_144) );
NOR2_X2 inst_33 ( .A1(net_126), .A2(net_76), .ZN(net_69) );
CLKBUF_X2 inst_172 ( .A(net_165), .Z(net_166) );
INV_X4 inst_83 ( .ZN(net_16), .A(net_0) );
NAND3_X2 inst_47 ( .ZN(net_102), .A1(net_100), .A2(net_99), .A3(net_66) );
NOR3_X2 inst_19 ( .ZN(net_105), .A3(net_104), .A1(net_90), .A2(net_83) );
INV_X1 inst_123 ( .ZN(net_118), .A(blif_reset_net) );
INV_X2 inst_121 ( .A(net_100), .ZN(net_93) );
XNOR2_X2 inst_2 ( .ZN(net_54), .A(net_53), .B(net_40) );
OR3_X2 inst_8 ( .A2(net_66), .ZN(net_50), .A1(net_49), .A3(net_48) );
INV_X2 inst_118 ( .ZN(net_33), .A(net_32) );
INV_X4 inst_86 ( .ZN(net_29), .A(net_16) );
CLKBUF_X2 inst_153 ( .A(net_145), .Z(net_147) );
NOR3_X2 inst_20 ( .ZN(net_106), .A3(net_104), .A1(net_94), .A2(net_89) );
NOR2_X2 inst_27 ( .ZN(net_80), .A1(net_2), .A2(CLR) );
NOR2_X2 inst_38 ( .A2(net_129), .ZN(net_92), .A1(net_56) );
INV_X4 inst_100 ( .ZN(net_112), .A(net_109) );
NAND2_X4 inst_52 ( .ZN(net_136), .A1(net_131), .A2(net_70) );
INV_X4 inst_90 ( .ZN(net_58), .A(net_19) );
DFFR_X1 inst_140 ( .RN(net_118), .D(net_107), .QN(net_9), .CK(net_160) );
CLKBUF_X2 inst_209 ( .A(net_202), .Z(net_203) );
CLKBUF_X2 inst_211 ( .A(net_189), .Z(net_205) );
NOR2_X1 inst_40 ( .A2(net_90), .ZN(net_89), .A1(net_88) );
CLKBUF_X2 inst_162 ( .A(net_155), .Z(net_156) );
CLKBUF_X2 inst_167 ( .A(net_155), .Z(net_161) );
INV_X4 inst_93 ( .ZN(net_99), .A(net_1) );
INV_X4 inst_81 ( .ZN(net_70), .A(net_12) );
INV_X4 inst_95 ( .A(net_57), .ZN(net_45) );
XNOR2_X2 inst_1 ( .A(net_51), .ZN(net_30), .B(FM) );
NAND2_X2 inst_72 ( .A2(net_128), .ZN(net_104), .A1(net_45) );
DFFR_X1 inst_139 ( .RN(net_118), .D(net_96), .QN(YLW1), .CK(net_146) );
CLKBUF_X2 inst_155 ( .A(net_148), .Z(net_149) );
NAND2_X2 inst_59 ( .ZN(net_48), .A1(net_16), .A2(net_1) );
DFFR_X1 inst_135 ( .RN(net_118), .D(net_79), .Q(RED1), .CK(net_193) );
CLKBUF_X2 inst_196 ( .A(net_189), .Z(net_190) );
NAND3_X2 inst_44 ( .A3(net_80), .A2(net_58), .A1(net_51), .ZN(net_41) );
NAND2_X4 inst_55 ( .A1(net_125), .ZN(net_98), .A2(net_28) );
CLKBUF_X2 inst_174 ( .A(net_167), .Z(net_168) );
INV_X2 inst_115 ( .ZN(net_88), .A(net_10) );
NOR2_X2 inst_37 ( .A1(net_130), .ZN(net_125), .A2(net_1) );
CLKBUF_X2 inst_210 ( .A(net_203), .Z(net_204) );
AND2_X2 inst_148 ( .ZN(net_53), .A2(net_34), .A1(net_26) );
CLKBUF_X2 inst_164 ( .A(net_157), .Z(net_158) );
CLKBUF_X2 inst_191 ( .A(net_184), .Z(net_185) );
XNOR2_X2 inst_5 ( .ZN(net_108), .A(net_102), .B(net_58) );
CLKBUF_X2 inst_157 ( .A(net_150), .Z(net_151) );
INV_X4 inst_84 ( .ZN(net_66), .A(net_2) );
NAND2_X4 inst_51 ( .A2(net_140), .ZN(net_137), .A1(net_131) );
DFFR_X1 inst_142 ( .RN(net_118), .D(net_114), .QN(net_0), .CK(net_154) );
INV_X4 inst_80 ( .ZN(net_49), .A(net_5) );
CLKBUF_X2 inst_173 ( .A(net_166), .Z(net_167) );
INV_X2 inst_105 ( .A(net_133), .ZN(net_132) );
CLKBUF_X2 inst_213 ( .A(net_206), .Z(net_207) );
NAND2_X2 inst_68 ( .ZN(net_84), .A1(net_81), .A2(net_67) );
CLKBUF_X2 inst_216 ( .A(net_195), .Z(net_210) );
INV_X4 inst_78 ( .ZN(net_87), .A(net_9) );
NAND4_X2 inst_42 ( .A1(net_66), .ZN(net_63), .A4(net_62), .A2(net_51), .A3(net_17) );
CLKBUF_X2 inst_175 ( .A(net_168), .Z(net_169) );
NAND2_X4 inst_53 ( .A2(net_137), .A1(net_136), .ZN(net_119) );
CLKBUF_X2 inst_205 ( .A(net_156), .Z(net_199) );
CLKBUF_X2 inst_177 ( .A(net_170), .Z(net_171) );
CLKBUF_X2 inst_183 ( .A(net_176), .Z(net_177) );
DFFR_X2 inst_133 ( .RN(net_118), .D(net_106), .QN(net_10), .CK(net_164) );
NOR2_X2 inst_26 ( .ZN(net_81), .A1(net_5), .A2(CLR) );
CLKBUF_X2 inst_151 ( .A(net_144), .Z(net_145) );
INV_X2 inst_112 ( .ZN(net_13), .A(net_11) );
NAND2_X2 inst_64 ( .ZN(net_55), .A2(net_41), .A1(net_39) );
INV_X2 inst_107 ( .A(net_129), .ZN(net_128) );
NAND2_X2 inst_67 ( .ZN(net_73), .A2(net_65), .A1(net_49) );
CLKBUF_X2 inst_181 ( .A(net_165), .Z(net_175) );
DFFR_X2 inst_127 ( .RN(net_118), .D(net_78), .QN(net_8), .CK(net_198) );
NAND2_X2 inst_70 ( .ZN(net_91), .A2(net_84), .A1(net_63) );
CLKBUF_X2 inst_186 ( .A(net_179), .Z(net_180) );
DFFR_X2 inst_129 ( .QN(net_124), .RN(net_118), .D(net_77), .CK(net_196) );
INV_X4 inst_92 ( .A(net_29), .ZN(net_28) );
NOR2_X2 inst_29 ( .A2(net_34), .ZN(net_27), .A1(net_26) );
CLKBUF_X2 inst_189 ( .A(net_182), .Z(net_183) );
NOR3_X2 inst_17 ( .ZN(net_78), .A3(net_76), .A1(net_53), .A2(net_27) );
NOR3_X2 inst_11 ( .ZN(net_64), .A1(net_51), .A3(net_48), .A2(net_19) );
AND3_X2 inst_146 ( .A3(net_122), .ZN(net_114), .A1(net_111), .A2(net_109) );
CLKBUF_X2 inst_188 ( .A(net_167), .Z(net_182) );
NOR3_X2 inst_14 ( .ZN(net_72), .A3(net_60), .A1(net_33), .A2(net_21) );
CLKBUF_X2 inst_202 ( .A(net_195), .Z(net_196) );
CLKBUF_X2 inst_206 ( .A(net_199), .Z(net_200) );
CLKBUF_X2 inst_187 ( .A(net_180), .Z(net_181) );
INV_X1 inst_122 ( .ZN(net_26), .A(net_8) );
NOR2_X2 inst_31 ( .ZN(net_44), .A1(net_42), .A2(net_30) );
NOR2_X2 inst_25 ( .A2(net_127), .A1(net_124), .ZN(net_34) );
DFFR_X2 inst_126 ( .QN(net_127), .RN(net_118), .D(net_69), .CK(net_204) );
CLKBUF_X2 inst_158 ( .A(net_150), .Z(net_152) );
DFFR_X1 inst_141 ( .RN(net_118), .D(net_117), .QN(net_1), .CK(net_156) );
NAND2_X2 inst_62 ( .A2(net_133), .ZN(net_76), .A1(net_45) );
CLKBUF_X2 inst_200 ( .A(net_174), .Z(net_194) );
INV_X2 inst_110 ( .ZN(net_139), .A(net_125) );
NAND2_X2 inst_74 ( .ZN(net_96), .A1(net_95), .A2(net_85) );
NAND2_X2 inst_57 ( .ZN(net_140), .A2(net_11), .A1(net_10) );
NOR2_X2 inst_35 ( .A1(net_136), .ZN(net_90), .A2(net_11) );
INV_X4 inst_99 ( .A(net_66), .ZN(net_31) );
NAND3_X2 inst_48 ( .A2(net_139), .A1(net_138), .ZN(net_121), .A3(net_93) );
NAND2_X2 inst_69 ( .ZN(net_85), .A1(net_84), .A2(net_68) );
NAND3_X2 inst_46 ( .A2(net_109), .ZN(net_79), .A1(net_50), .A3(net_46) );
INV_X4 inst_82 ( .ZN(net_17), .A(CLR) );
DFFR_X1 inst_136 ( .RN(net_118), .D(net_82), .Q(GRN2), .CK(net_191) );
NOR2_X2 inst_30 ( .ZN(net_43), .A1(net_42), .A2(net_22) );
INV_X4 inst_102 ( .ZN(net_115), .A(net_111) );
INV_X2 inst_108 ( .ZN(net_143), .A(net_128) );
CLKBUF_X2 inst_165 ( .A(net_158), .Z(net_159) );
NOR2_X2 inst_32 ( .ZN(net_61), .A2(net_60), .A1(net_57) );
NOR3_X2 inst_22 ( .A1(net_115), .ZN(net_113), .A2(net_112), .A3(net_108) );
DFFR_X1 inst_144 ( .RN(net_118), .D(net_113), .QN(net_3), .CK(net_174) );
NOR2_X2 inst_34 ( .A2(net_131), .ZN(net_71), .A1(net_70) );
NOR3_X2 inst_12 ( .A2(net_58), .ZN(net_52), .A3(net_38), .A1(net_18) );
CLKBUF_X2 inst_195 ( .A(net_188), .Z(net_189) );
NAND2_X4 inst_56 ( .A1(net_121), .ZN(net_111), .A2(net_36) );
NAND2_X2 inst_71 ( .ZN(net_95), .A2(net_91), .A1(net_88) );
NOR3_X2 inst_21 ( .A3(net_143), .A1(net_142), .A2(net_112), .ZN(net_107) );
INV_X2 inst_104 ( .A(net_136), .ZN(net_134) );
NAND2_X2 inst_60 ( .A1(net_51), .ZN(net_37), .A2(net_36) );
CLKBUF_X2 inst_215 ( .A(net_208), .Z(net_209) );
CLKBUF_X2 inst_169 ( .A(net_162), .Z(net_163) );
CLKBUF_X2 inst_168 ( .A(net_161), .Z(net_162) );
INV_X4 inst_97 ( .ZN(net_35), .A(net_28) );
CLKBUF_X2 inst_161 ( .A(net_144), .Z(net_155) );
DFFR_X2 inst_124 ( .RN(net_118), .D(net_44), .QN(net_4), .CK(net_214) );
NOR3_X2 inst_18 ( .A1(net_134), .A3(net_104), .ZN(net_103), .A2(net_71) );
NOR3_X2 inst_16 ( .ZN(net_77), .A3(net_76), .A1(net_34), .A2(net_24) );
CLKBUF_X2 inst_208 ( .A(net_201), .Z(net_202) );
INV_X4 inst_88 ( .ZN(net_18), .A(net_17) );
CLKBUF_X2 inst_220 ( .A(net_213), .Z(net_214) );
XNOR2_X2 inst_3 ( .ZN(net_142), .A(net_94), .B(net_87) );
CLKBUF_X2 inst_156 ( .A(net_149), .Z(net_150) );
OR2_X4 inst_9 ( .ZN(net_60), .A1(net_35), .A2(net_1) );
INV_X2 inst_113 ( .ZN(net_14), .A(CLR) );
CLKBUF_X2 inst_170 ( .A(net_163), .Z(net_164) );
CLKBUF_X2 inst_198 ( .A(net_158), .Z(net_192) );
NAND2_X4 inst_50 ( .A1(net_133), .ZN(net_131), .A2(net_6) );
DFFR_X1 inst_137 ( .RN(net_118), .D(net_86), .Q(GRN1), .CK(net_181) );
CLKBUF_X2 inst_199 ( .A(net_192), .Z(net_193) );
NOR2_X1 inst_41 ( .ZN(net_122), .A2(net_100), .A1(net_92) );
DFFR_X2 inst_130 ( .RN(net_118), .D(net_91), .QN(net_5), .CK(net_186) );
INV_X4 inst_91 ( .A(net_58), .ZN(net_36) );
DFFR_X2 inst_132 ( .RN(net_118), .D(net_105), .QN(net_11), .CK(net_169) );
DFFR_X1 inst_143 ( .RN(net_118), .D(net_116), .QN(net_2), .CK(net_151) );
CLKBUF_X2 inst_176 ( .A(net_146), .Z(net_170) );
CLKBUF_X2 inst_152 ( .A(net_145), .Z(net_146) );
NAND2_X2 inst_58 ( .ZN(net_38), .A1(net_29), .A2(net_1) );
NOR2_X2 inst_36 ( .A2(net_135), .ZN(net_83), .A1(net_13) );
AND2_X4 inst_147 ( .ZN(net_32), .A2(net_14), .A1(net_2) );
INV_X4 inst_87 ( .ZN(net_57), .A(net_17) );
NAND2_X2 inst_61 ( .ZN(net_39), .A2(net_32), .A1(net_23) );
CLKBUF_X2 inst_203 ( .A(net_179), .Z(net_197) );
NAND3_X2 inst_45 ( .ZN(net_46), .A3(net_31), .A1(net_25), .A2(net_20) );
INV_X4 inst_96 ( .A(net_36), .ZN(net_25) );
CLKBUF_X2 inst_212 ( .A(net_205), .Z(net_206) );
INV_X4 inst_101 ( .ZN(net_62), .A(net_38) );
XOR2_X2 inst_0 ( .Z(net_22), .B(net_6), .A(TEST) );
CLKBUF_X2 inst_184 ( .A(net_174), .Z(net_178) );
NOR4_X2 inst_10 ( .ZN(net_82), .A1(net_81), .A3(net_80), .A2(net_61), .A4(net_59) );
XNOR2_X2 inst_4 ( .ZN(net_141), .A(net_98), .B(net_66) );
NAND2_X2 inst_65 ( .ZN(net_67), .A1(net_66), .A2(net_64) );
CLKBUF_X2 inst_178 ( .A(net_171), .Z(net_172) );
INV_X4 inst_89 ( .A(net_49), .ZN(net_20) );
NOR2_X2 inst_28 ( .A2(net_126), .A1(net_123), .ZN(net_24) );
INV_X2 inst_111 ( .A(net_124), .ZN(net_123) );
NAND2_X2 inst_66 ( .ZN(net_68), .A1(net_62), .A2(net_55) );
INV_X2 inst_117 ( .A(net_58), .ZN(net_23) );
INV_X4 inst_98 ( .A(net_109), .ZN(net_42) );
CLKBUF_X2 inst_190 ( .A(net_183), .Z(net_184) );
NAND2_X2 inst_63 ( .A2(net_62), .A1(net_51), .ZN(net_47) );
OR3_X4 inst_7 ( .A2(net_81), .A1(net_80), .ZN(net_74), .A3(net_52) );
CLKBUF_X2 inst_204 ( .A(net_162), .Z(net_198) );
CLKBUF_X2 inst_185 ( .A(net_178), .Z(net_179) );
CLKBUF_X2 inst_182 ( .A(net_175), .Z(net_176) );
NAND2_X4 inst_49 ( .ZN(net_133), .A1(net_120), .A2(net_40) );
INV_X2 inst_120 ( .ZN(net_65), .A(net_64) );
CLKBUF_X2 inst_154 ( .A(net_147), .Z(net_148) );
NOR3_X2 inst_13 ( .ZN(net_59), .A1(net_58), .A2(net_57), .A3(net_56) );
INV_X2 inst_119 ( .ZN(net_56), .A(net_35) );
NAND2_X2 inst_75 ( .ZN(net_97), .A2(net_95), .A1(net_74) );
CLKBUF_X2 inst_192 ( .A(net_185), .Z(net_186) );
CLKBUF_X2 inst_166 ( .A(net_159), .Z(net_160) );
INV_X2 inst_116 ( .ZN(net_21), .A(net_20) );
CLKBUF_X2 inst_163 ( .A(net_155), .Z(net_157) );
INV_X4 inst_85 ( .ZN(net_40), .A(net_7) );
NAND2_X4 inst_54 ( .ZN(net_130), .A1(net_119), .A2(net_87) );
INV_X4 inst_79 ( .ZN(net_19), .A(net_3) );
INV_X2 inst_109 ( .A(net_127), .ZN(net_126) );
INV_X2 inst_106 ( .A(net_130), .ZN(net_129) );
CLKBUF_X2 inst_219 ( .A(net_212), .Z(net_213) );
CLKBUF_X2 inst_201 ( .A(net_194), .Z(net_195) );
CLKBUF_X2 inst_193 ( .A(net_170), .Z(net_187) );
AND2_X2 inst_149 ( .ZN(net_94), .A2(net_90), .A1(net_15) );
NAND3_X2 inst_43 ( .A2(net_127), .A3(net_124), .ZN(net_120), .A1(net_8) );
NOR2_X2 inst_39 ( .ZN(net_116), .A2(net_115), .A1(net_110) );
DFFR_X2 inst_128 ( .RN(net_118), .D(net_75), .QN(net_7), .CK(net_197) );
NAND2_X2 inst_73 ( .ZN(net_138), .A1(net_129), .A2(net_66) );
CLKBUF_X2 inst_217 ( .A(net_210), .Z(net_211) );
NOR3_X2 inst_23 ( .ZN(net_117), .A1(net_115), .A2(net_112), .A3(net_101) );
CLKBUF_X2 inst_171 ( .A(net_163), .Z(net_165) );
INV_X4 inst_77 ( .ZN(net_51), .A(net_4) );
INV_X4 inst_94 ( .ZN(net_109), .A(net_57) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DFRTN_PP_SYMBOL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_PP_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:38:41 03/22/2015
// Design Name: register32bit
// Module Name: C:/Users/Joseph/Documents/Xilinx/HW1/register32bit_test.v
// Project Name: HW1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: register32bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module register32bit_test;
// Inputs
reg [31:0] data_in;
reg clk;
reg reset;
reg en;
// Outputs
wire [31:0] data_out;
// Instantiate the Unit Under Test (UUT)
register32bit uut (
.data_out(data_out),
.data_in(data_in),
.clk(clk),
.reset(reset),
.en(en)
);
// Clock
always
begin
clk <= 1;
#10 clk <= 0;
#10;
end
initial begin
// Initialize Inputs
data_in = 0;
clk = 0;
reset = 0;
en = 1;
#10 reset = 1;
#210 reset = 0;
#10 reset = 1;
#80 en = 0;
#60 en = 1;
end
always @(negedge clk)
begin
data_in = $random % 1000 + 1000;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRDLSTP_PP_BLACKBOX_V
/**
* srdlstp: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlstp (
Q ,
SET_B ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input SET_B ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLSTP_PP_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: phy_init.v
// /___/ /\ Date Last Modified: $Date: 2011/01/08 11:34:37 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has an interface for providing control/address and write
// data to the PHY Control Block during initialization/calibration.
// Once initialization and calibration are complete, control is passed to the MC.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: phy_init.v,v 1.12.4.1 2011/01/08 11:34:37 karthip Exp $
**$Date: 2011/01/08 11:34:37 $
**$Author: karthip $
**$Revision: 1.12.4.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_1/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/phy_init.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_init #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 4, // # of memory clocks per CLK
parameter CLK_PERIOD = 3000, // Logic (internal) clk period (in ps)
parameter PRBS_WIDTH = 64, // PRBS sequence = 2^PRBS_WIDTH
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter nCS_PER_RANK = 1, // # of CS bits per rank e.g. for
// component I/F with CS_WIDTH=1,
// nCS_PER_RANK=# of components
parameter DQ_WIDTH = 64,
parameter DQS_WIDTH = 8,
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter ROW_WIDTH = 14,
parameter CS_WIDTH = 1,
parameter RANKS = 1, // # of memory ranks in the interface
parameter CKE_WIDTH = 1, // # of cke outputs
parameter DRAM_TYPE = "DDR3",
parameter REG_CTRL = "ON",
// calibration Address
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
// parameter nAL = 0, // Additive latency (in clk cyc)
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay (in ps)
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter RTT_NOM = "60", // Nominal ODT termination value
parameter RTT_WR = "60", // Write ODT termination value
parameter WRLVL = "ON", // Enable write leveling
// parameter PHASE_DETECT = "ON", // Enable read phase detector
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter nSLOTS = 1, // Number of DIMM SLOTs in the system
parameter SIM_INIT_OPTION = "NONE", // "NONE", "SKIP_PU_DLY", "SKIP_INIT"
parameter SIM_CAL_OPTION = "NONE" // "NONE", "FAST_CAL", "SKIP_CAL"
)
(
input clk,
input rst,
input [PRBS_WIDTH-1:0] prbs_o,
input pi_phaselocked,
input pi_phase_locked_all,
input pi_dqs_found_done,
// output [DQS_CNT_WIDTH:0] pi_phaselock_calib_cnt,
output pi_calib_done,
input phy_if_empty,
// input ck_addr_cmd_delay_done,
input dqs_dly_done,
// Read/write calibration interface
input wrlvl_done,
input wrlvl_rank_done,
input done_dqs_tap_inc,
input [5:0] rd_data_offset,
input [6*RANKS-1:0] rd_data_offset_ranks,
input pi_dqs_found_rank_done,
input wrcal_done,
input wrcal_prech_req,
input [7:0] slot_0_present,
input [7:0] slot_1_present,
output reg wl_sm_start,
output reg wr_lvl_start,
output reg wrcal_start,
input rdlvl_stg1_done,
input rdlvl_stg1_rank_done,
output reg rdlvl_stg1_start,
output reg pi_dqs_found_start,
output reg detect_pi_found_dqs,
// rdlvl stage 1 precharge requested after each DQS
input rdlvl_prech_req,
input wrcal_resume,
// Signals shared btw multiple calibration stages
output reg prech_done,
// Data select / status
output reg init_calib_complete,
// PHY address/control
// 2 commands to PHY Control Block per div 2 clock in 2:1 mode
// 4 commands to PHY Control Block per div 4 clock in 4:1 mode
output reg [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,
output reg [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,
output reg [nCK_PER_CLK-1:0] phy_ras_n,
output reg [nCK_PER_CLK-1:0] phy_cas_n,
output reg [nCK_PER_CLK-1:0] phy_we_n,
output reg phy_reset_n,
// output reg [CKE_WIDTH-1:0] phy_cke,
output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,
// output phy_init_data_sel,
// Hard PHY Interface signals
input phy_ctl_ready,
input phy_ctl_full,
input phy_cmd_full,
input phy_data_full,
output reg calib_ctl_wren,
output reg calib_cmd_wren,
output reg [1:0] calib_seq,
output reg write_calib,
output reg read_calib,
// PHY_Ctl_Wd
output reg [2:0] calib_cmd,
// ODT bus width is fixed to 4 for up to 4 ranks support
// For single rank only calib_aux_out0 used
output reg [3:0] calib_aux_out0,
output reg [3:0] calib_aux_out1,
output [1:0] calib_rank_cnt,
// output reg [2:0] calib_bank_cnt,
output reg [5:0] calib_data_offset,
// PHY OUT_FIFO
output reg calib_wrdata_en,
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_wrdata,
// PHY Read
output phy_rddata_en,
output phy_rddata_valid
// // PHY sideband signals
// output reg [0:0] phy_ioconfig,
// output reg phy_ioconfig_en
);
//*****************************************************************************
// Assertions to be added
//*****************************************************************************
// The phy_ctl_full signal must never be asserted in synchronous mode of
// operation either 4:1 or 2:1
//
// The RANKS parameter must never be set to '0' by the user
// valid values: 1 to 4
//
//*****************************************************************************
// Number of Read level stage 1 writes limited to a SDRAM row
// The address of Read Level stage 1 reads must also be limited
// to a single SDRAM row
// (2^COL_WIDTH)/BURST_MODE = (2^10)/8 = 128
localparam NUM_STG1_WR_RD = (BURST_MODE == "8") ? 128 :
(BURST_MODE == "4") ? 256 : 128;
localparam ADDR_INC = (BURST_MODE == "8") ? 8 :
(BURST_MODE == "4") ? 4 : 8;
// In a 2 slot dual rank per system RTT_NOM values
// for Rank2 and Rank3 default to 40 ohms
localparam RTT_NOM2 = "40";
localparam RTT_NOM3 = "40";
// Specifically for use with half-frequency controller (nCK_PER_CLK=2)
// = 1 if burst length = 4, = 0 if burst length = 8. Determines how
// often row command needs to be issued during read-leveling
// For DDR3 the burst length is fixed during calibration
localparam BURST4_FLAG = (DRAM_TYPE == "DDR3")? 1'b0 :
(BURST_MODE == "8") ? 1'b0 :
((BURST_MODE == "4") ? 1'b1 : 1'b0);
//***************************************************************************
// Counter values used to determine bus timing
// NOTE on all counter terminal counts - these can/should be one less than
// the actual delay to take into account extra clock cycle delay in
// generating the corresponding "done" signal
//***************************************************************************
localparam CLK_MEM_PERIOD = CLK_PERIOD / nCK_PER_CLK;
// Calculate initial delay required in number of CLK clock cycles
// to delay initially. The counter is clocked by [CLK/1024] - which
// is approximately division by 1000 - note that the formulas below will
// result in more than the minimum wait time because of this approximation.
// NOTE: For DDR3 JEDEC specifies to delay reset
// by 200us, and CKE by an additional 500us after power-up
// For DDR2 CKE is delayed by 200us after power up.
localparam DDR3_RESET_DELAY_NS = 200000;
localparam DDR3_CKE_DELAY_NS = 500000 + DDR3_RESET_DELAY_NS;
localparam DDR2_CKE_DELAY_NS = 200000;
localparam PWRON_RESET_DELAY_CNT =
((DDR3_RESET_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD);
localparam PWRON_CKE_DELAY_CNT = (DRAM_TYPE == "DDR3") ?
(((DDR3_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD)) :
(((DDR2_CKE_DELAY_NS+CLK_PERIOD-1)/CLK_PERIOD));
// FOR DDR2 -1 taken out. With -1 not getting 200us. The equation
// needs to be reworked.
localparam DDR2_INIT_PRE_DELAY_PS = 400000;
localparam DDR2_INIT_PRE_CNT =
((DDR2_INIT_PRE_DELAY_PS+CLK_PERIOD-1)/CLK_PERIOD)-1;
// Calculate tXPR time: reset from CKE HIGH to valid command after power-up
// tXPR = (max(5nCK, tRFC(min)+10ns). Add a few (blah, messy) more clock
// cycles because this counter actually starts up before CKE is asserted
// to memory.
localparam TXPR_DELAY_CNT =
(5*CLK_MEM_PERIOD > tRFC+10000) ?
(((5+nCK_PER_CLK-1)/nCK_PER_CLK)-1)+11 :
(((tRFC+10000+CLK_PERIOD-1)/CLK_PERIOD)-1)+11;
// tDLLK/tZQINIT time = 512*tCK = 256*tCLKDIV
localparam TDLLK_TZQINIT_DELAY_CNT = 255;
// TWR values in ns. Both DDR2 and DDR3 have the same value.
// 15000ns/tCK
localparam TWR_CYC = ((15000) % CLK_MEM_PERIOD) ?
(15000/CLK_MEM_PERIOD) + 1 : 15000/CLK_MEM_PERIOD;
// time to wait between consecutive commands in PHY_INIT - this is a
// generic number, and must be large enough to account for worst case
// timing parameter (tRFC - refresh-to-active) across all memory speed
// grades and operating frequencies. Expressed in clk
// (Divided by 4 or Divided by 2) clock cycles.
localparam CNTNEXT_CMD = (nCK_PER_CLK == 4) ? 7'b1100110 : 7'b1111111;
// Counter values to keep track of which MR register to load during init
// Set value of INIT_CNT_MR_DONE to equal value of counter for last mode
// register configured during initialization.
// NOTE: Reserve more bits for DDR2 - more MR accesses for DDR2 init
localparam INIT_CNT_MR2 = 2'b00;
localparam INIT_CNT_MR3 = 2'b01;
localparam INIT_CNT_MR1 = 2'b10;
localparam INIT_CNT_MR0 = 2'b11;
localparam INIT_CNT_MR_DONE = 2'b11;
// Register chip programmable values for DDR3
// The register chip for the registered DIMM needs to be programmed
// before the initialization of the registered DIMM.
// Address for the control word is in : DBA2, DA2, DA1, DA0
// Data for the control word is in: DBA1 DBA0, DA4, DA3
// The values will be stored in the local param in the following format
// {DBA[2:0], DA[4:0]}
// RC0 is global features control word. Address == 000
localparam REG_RC0 = 8'b00000000;
// RC1 Clock driver enable control word. Enables or disables the four
// output clocks in the register chip. For single rank and dual rank
// two clocks will be enabled and for quad rank all the four clocks
// will be enabled. Address == 000. Data = 0110 for single and dual rank.
// = 0000 for quad rank
localparam REG_RC1 = (RANKS <= 2) ? 8'b00110001 : 8'b00000001;
// RC2 timing control word. Set in 1T timing mode
// Address = 010. Data = 0000
localparam REG_RC2 = 8'b00000010;
// RC3 timing control word. Setting the data to 0000
localparam REG_RC3 = 8'b00000011;
// RC4 timing control work. Setting the data to 0000
localparam REG_RC4 = 8'b00000100;
// RC5 timing control work. Setting the data to 0000
localparam REG_RC5 = 8'b00000101;
// For non-zero AL values
localparam nAL = (AL == "CL-1") ? nCL - 1 : 0;
// Adding the register dimm latency to write latency
localparam CWL_M = (REG_CTRL == "ON") ? nCWL + nAL + 1 : nCWL + nAL;
// Master state machine encoding
localparam INIT_IDLE = 6'b000000; //0
localparam INIT_WAIT_CKE_EXIT = 6'b000001; //1
localparam INIT_LOAD_MR = 6'b000010; //2
localparam INIT_LOAD_MR_WAIT = 6'b000011; //3
localparam INIT_ZQCL = 6'b000100; //4
localparam INIT_WAIT_DLLK_ZQINIT = 6'b000101; //5
localparam INIT_WRLVL_START = 6'b000110; //6
localparam INIT_WRLVL_WAIT = 6'b000111; //7
localparam INIT_WRLVL_LOAD_MR = 6'b001000; //8
localparam INIT_WRLVL_LOAD_MR_WAIT = 6'b001001; //9
localparam INIT_WRLVL_LOAD_MR2 = 6'b001010; //A
localparam INIT_WRLVL_LOAD_MR2_WAIT = 6'b001011; //B
localparam INIT_RDLVL_ACT = 6'b001100; //C
localparam INIT_RDLVL_ACT_WAIT = 6'b001101; //D
localparam INIT_RDLVL_STG1_WRITE = 6'b001110; //E
localparam INIT_RDLVL_STG1_WRITE_READ = 6'b001111; //F
localparam INIT_RDLVL_STG1_READ = 6'b010000; //10
localparam INIT_RDLVL_STG2_READ = 6'b010001; //11
localparam INIT_RDLVL_STG2_READ_WAIT = 6'b010010; //12
localparam INIT_PRECHARGE_PREWAIT = 6'b010011; //13
localparam INIT_PRECHARGE = 6'b010100; //14
localparam INIT_PRECHARGE_WAIT = 6'b010101; //15
localparam INIT_DONE = 6'b010110; //16
localparam INIT_DDR2_PRECHARGE = 6'b010111; //17
localparam INIT_DDR2_PRECHARGE_WAIT = 6'b011000; //18
localparam INIT_REFRESH = 6'b011001; //19
localparam INIT_REFRESH_WAIT = 6'b011010; //1A
localparam INIT_REG_WRITE = 6'b011011; //1B
localparam INIT_REG_WRITE_WAIT = 6'b011100; //1C
localparam INIT_DDR2_MULTI_RANK = 6'b011101; //1D
localparam INIT_DDR2_MULTI_RANK_WAIT = 6'b011110; //1E
localparam INIT_WRCAL_ACT = 6'b011111; //1F
localparam INIT_WRCAL_ACT_WAIT = 6'b100000; //20
localparam INIT_WRCAL_WRITE = 6'b100001; //21
localparam INIT_WRCAL_WRITE_READ = 6'b100010; //22
localparam INIT_WRCAL_READ = 6'b100011; //23
localparam INIT_WRCAL_READ_WAIT = 6'b100100; //24
localparam INIT_PI_PHASELOCK_READS = 6'b100101; //25
integer i, j, k, l, m, n, p;
reg stg1_wr_done;
reg pi_dqs_found_done_r1;
reg pi_dqs_found_rank_done_r;
reg dqs_dly_done_r1;
reg read_calib_int;
reg read_calib_r;
reg pi_calib_done_r;
reg burst_addr_r;
reg [1:0] chip_cnt_r;
reg [6:0] cnt_cmd_r;
reg cnt_cmd_done_r;
reg [7:0] cnt_dllk_zqinit_r;
reg cnt_dllk_zqinit_done_r;
reg cnt_init_af_done_r;
reg [1:0] cnt_init_af_r;
reg [1:0] cnt_init_data_r;
reg [1:0] cnt_init_mr_r;
reg cnt_init_mr_done_r;
reg cnt_init_pre_wait_done_r;
reg [7:0] cnt_init_pre_wait_r;
reg [9:0] cnt_pwron_ce_r;
reg cnt_pwron_cke_done_r;
reg cnt_pwron_cke_done_r1;
reg [8:0] cnt_pwron_r;
reg cnt_pwron_reset_done_r;
reg cnt_txpr_done_r;
reg [7:0] cnt_txpr_r;
reg ddr2_pre_flag_r;
reg ddr2_refresh_flag_r;
reg ddr3_lm_done_r;
reg [4:0] enable_wrlvl_cnt;
reg init_complete_r;
reg init_complete_r1;
reg init_complete_r2;
reg [5:0] init_next_state;
reg [5:0] init_state_r;
reg [5:0] init_state_r1;
wire [15:0] load_mr0;
wire [15:0] load_mr1;
wire [15:0] load_mr2;
wire [15:0] load_mr3;
reg mem_init_done_r;
reg [1:0] mr2_r [0:3];
reg [2:0] mr1_r [0:3];
reg new_burst_r;
reg [15:0] wrcal_start_dly_r;
wire wrcal_start_pre;
// Only one ODT signal per rank in PHY Control Block
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r;
reg [nCK_PER_CLK-1:0] phy_tmp_odt_r1;
reg [CS_WIDTH*nCS_PER_RANK-1:0] phy_tmp_cs1_r;
reg [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_int_cs_n;
wire prech_done_pre;
reg [15:0] prech_done_dly_r;
reg prech_pending_r;
reg prech_req_posedge_r;
reg prech_req_r;
reg pwron_ce_r;
reg phy_wrdata_en;
reg phy_wrdata_en_r1;
reg phy_wrdata_en_r2;
reg phy_wrdata_en_r3;
reg [ROW_WIDTH-1:0] address_w;
reg [BANK_WIDTH-1:0] bank_w;
reg rdlvl_stg1_start_int;
reg [15:0] rdlvl_start_dly0_r;
wire rdlvl_start_pre;
wire rdlvl_rd;
wire rdlvl_wr;
reg rdlvl_wr_r;
wire rdlvl_wr_rd;
reg [2:0] reg_ctrl_cnt_r;
reg [1:0] tmp_mr2_r [0:3];
reg [2:0] tmp_mr1_r [0:3];
reg wrlvl_done_r;
reg wrlvl_done_r1;
reg wrlvl_rank_done_r1;
reg wrlvl_rank_done_r2;
reg wrlvl_rank_done_r3;
reg [2:0] wrlvl_rank_cntr;
reg wrlvl_odt;
reg wrlvl_active;
reg wrlvl_active_r1;
reg [1:0] num_reads;
reg [8:0] stg1_wr_rd_cnt;
reg wr_level_dqs_asrt;
reg wr_level_dqs_asrt_r1;
reg [1:0] dqs_asrt_cnt;
// reg pi_calib_start;
reg [PRBS_WIDTH-1:0] prbs_r1;
reg [PRBS_WIDTH-1:0] prbs_r2;
reg [PRBS_WIDTH-1:0] prbs_r3;
reg [PRBS_WIDTH-1:0] prbs_r4;
reg [PRBS_WIDTH-1:0] prbs_r5;
reg [PRBS_WIDTH-1:0] prbs_r6;
reg [PRBS_WIDTH-1:0] prbs_r7;
//***************************************************************************
// Debug
//***************************************************************************
//synthesis translate_off
always @(posedge mem_init_done_r) begin
if (!rst)
$display ("PHY_INIT: Memory Initialization completed at %t", $time);
end
always @(posedge wrlvl_done) begin
if (!rst && (WRLVL == "ON"))
$display ("PHY_INIT: Write Leveling completed at %t", $time);
end
always @(posedge rdlvl_stg1_done) begin
if (!rst)
$display ("PHY_INIT: Read Leveling Stage 1 completed at %t", $time);
end
always @(posedge pi_calib_done_r) begin
if (!rst)
$display ("PHY_INIT: Phaser_In Phase Locked at %t", $time);
end
always @(posedge pi_dqs_found_done) begin
if (!rst)
$display ("PHY_INIT: Phaser_In DQSFOUND completed at %t", $time);
end
always @(posedge wrcal_done) begin
if (!rst && (WRLVL == "ON"))
$display ("PHY_INIT: Write Calibration completed at %t", $time);
end
//synthesis translate_on
//***************************************************************************
// DQS count to be sent to hard PHY during Phaser_IN Phase Locking stage
//***************************************************************************
// assign pi_phaselock_calib_cnt = dqs_cnt_r;
assign pi_calib_done = pi_calib_done_r;
//***************************************************************************
// Signal PHY completion when calibration is finished
// Signal assertion is delayed by four clock cycles to account for the
// multi cycle path constraint to (phy_init_data_sel) signal.
//***************************************************************************
always @(posedge clk)
if (rst) begin
init_complete_r <= #TCQ 1'b0;
init_complete_r1 <= #TCQ 1'b0;
init_complete_r2 <= #TCQ 1'b0;
init_calib_complete <= #TCQ 1'b0;
end else begin
if (init_state_r == INIT_DONE)
init_complete_r <= #TCQ 1'b1;
init_complete_r1 <= #TCQ init_complete_r;
init_complete_r2 <= #TCQ init_complete_r1;
init_calib_complete <= #TCQ init_complete_r2;
end
//***************************************************************************
// Instantiate FF for the phy_init_data_sel signal. A multi cycle path
// constraint will be assigned to this signal. This signal will only be
// used within the PHY
//***************************************************************************
// FDRSE u_ff_phy_init_data_sel
// (
// .Q (phy_init_data_sel),
// .C (clk),
// .CE (1'b1),
// .D (init_complete_r),
// .R (1'b0),
// .S (1'b0)
// ) /* synthesis syn_preserve=1 */
// /* synthesis syn_replicate = 0 */;
//***************************************************************************
// Mode register programming
//***************************************************************************
//*****************************************************************
// DDR3 Load mode reg0
// Mode Register (MR0):
// [15:13] - unused - 000
// [12] - Precharge Power-down DLL usage - 0 (DLL frozen, slow-exit),
// 1 (DLL maintained)
// [11:9] - write recovery for Auto Precharge (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4],[2] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [1:0] - Burst Length - BURST_LEN
// DDR2 Load mode register
// Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - Power-down mode - 0 (normal)
// [11:9] - write recovery - write recovery for Auto Precharge
// (tWR/tCK = 6)
// [8] - DLL reset - 0 or 1
// [7] - Test Mode - 0 (normal)
// [6:4] - CAS latency - CAS_LAT
// [3] - Burst Type - BURST_TYPE
// [2:0] - Burst Length - BURST_LEN
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr0_DDR3
assign load_mr0[1:0] = (BURST_MODE == "8") ? 2'b00 :
(BURST_MODE == "OTF") ? 2'b01 :
(BURST_MODE == "4") ? 2'b10 : 2'b11;
assign load_mr0[2] = (nCL >= 12) ? 1'b1 : 1'b0; // LSb of CAS latency
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = ((nCL == 5) || (nCL == 13)) ? 3'b001 :
((nCL == 6) || (nCL == 14)) ? 3'b010 :
(nCL == 7) ? 3'b011 :
(nCL == 8) ? 3'b100 :
(nCL == 9) ? 3'b101 :
(nCL == 10) ? 3'b110 :
(nCL == 11) ? 3'b111 :
(nCL == 12) ? 3'b000 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 5) ? 3'b001 :
(TWR_CYC == 6) ? 3'b010 :
(TWR_CYC == 7) ? 3'b011 :
(TWR_CYC == 8) ? 3'b100 :
(TWR_CYC == 9) ? 3'b101 :
(TWR_CYC == 10) ? 3'b101 :
(TWR_CYC == 11) ? 3'b110 :
(TWR_CYC == 12) ? 3'b110 :
(TWR_CYC == 13) ? 3'b111 :
(TWR_CYC == 14) ? 3'b111 :
(TWR_CYC == 15) ? 3'b000 :
(TWR_CYC == 16) ? 3'b000 : 3'b010;
assign load_mr0[12] = 1'b0; // Precharge Power-Down DLL 'slow-exit'
assign load_mr0[15:13] = 3'b000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr0_DDR2 // block: gen
assign load_mr0[2:0] = (BURST_MODE == "8") ? 3'b011 :
(BURST_MODE == "4") ? 3'b010 : 3'b111;
assign load_mr0[3] = (BURST_TYPE == "SEQ") ? 1'b0 : 1'b1;
assign load_mr0[6:4] = (nCL == 3) ? 3'b011 :
(nCL == 4) ? 3'b100 :
(nCL == 5) ? 3'b101 :
(nCL == 6) ? 3'b110 : 3'b111;
assign load_mr0[7] = 1'b0;
assign load_mr0[8] = 1'b1; // Reset DLL (init only)
assign load_mr0[11:9] = (TWR_CYC == 2) ? 3'b001 :
(TWR_CYC == 3) ? 3'b010 :
(TWR_CYC == 4) ? 3'b011 :
(TWR_CYC == 5) ? 3'b100 :
(TWR_CYC == 6) ? 3'b101 : 3'b010;
assign load_mr0[15:12]= 4'b0000; // Reserved
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg1
// Mode Register (MR1):
// [15:13] - unused - 00
// [12] - output enable - 0 (enabled for DQ, DQS, DQS#)
// [11] - TDQS enable - 0 (TDQS disabled and DM enabled)
// [10] - reserved - 0 (must be '0')
// [9] - RTT[2] - 0
// [8] - reserved - 0 (must be '0')
// [7] - write leveling - 0 (disabled), 1 (enabled)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5] - Output driver impedance[1] - 0 (RZQ/6 and RZQ/7)
// [4:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output driver impedance[0] - 0(RZQ/6), or 1 (RZQ/7)
// [0] - DLL enable - 0 (normal)
// DDR2 ext mode register
// Extended Mode Register (MR):
// [15:14] - unused - 00
// [13] - reserved - 0
// [12] - output enable - 0 (enabled)
// [11] - RDQS enable - 0 (disabled)
// [10] - DQS# enable - 0 (enabled)
// [9:7] - OCD Program - 111 or 000 (first 111, then 000 during init)
// [6] - RTT[1] - RTT[1:0] = 0(no ODT), 1(75), 2(150), 3(50)
// [5:3] - Additive CAS - ADDITIVE_CAS
// [2] - RTT[0]
// [1] - Output drive - REDUCE_DRV (= 0(full), = 1 (reduced)
// [0] - DLL enable - 0 (normal)
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr1_DDR3
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b0 : 1'b1;
assign load_mr1[2] = ((RTT_NOM == "30") || (RTT_NOM == "40") ||
(RTT_NOM == "60")) ? 1'b1 : 1'b0;
assign load_mr1[4:3] = (AL == "0") ? 2'b00 :
(AL == "CL-1") ? 2'b01 :
(AL == "CL-2") ? 2'b10 : 2'b11;
assign load_mr1[5] = 1'b0;
assign load_mr1[6] = ((RTT_NOM == "40") || (RTT_NOM == "120")) ?
1'b1 : 1'b0;
assign load_mr1[7] = 1'b0; // Enable write lvl after init sequence
assign load_mr1[8] = 1'b0;
assign load_mr1[9] = ((RTT_NOM == "20") || (RTT_NOM == "30")) ?
1'b1 : 1'b0;
assign load_mr1[10] = 1'b0;
assign load_mr1[15:11] = 5'b00000;
end else if (DRAM_TYPE == "DDR2") begin: gen_load_mr1_DDR2
assign load_mr1[0] = 1'b0; // DLL enabled during Imitialization
assign load_mr1[1] = (OUTPUT_DRV == "LOW") ? 1'b1 : 1'b0;
assign load_mr1[2] = ((RTT_NOM == "75") || (RTT_NOM == "50")) ?
1'b1 : 1'b0;
assign load_mr1[5:3] = (AL == "0") ? 3'b000 :
(AL == "1") ? 3'b001 :
(AL == "2") ? 3'b010 :
(AL == "3") ? 3'b011 :
(AL == "4") ? 3'b100 : 3'b111;
assign load_mr1[6] = ((RTT_NOM == "50") ||
(RTT_NOM == "150")) ? 1'b1 : 1'b0;
assign load_mr1[9:7] = 3'b000;
assign load_mr1[10] = (DDR2_DQSN_ENABLE == "YES") ? 1'b0 : 1'b1;
assign load_mr1[15:11] = 5'b00000;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg2
// Mode Register (MR2):
// [15:11] - unused - 00
// [10:9] - RTT_WR - 00 (Dynamic ODT off)
// [8] - reserved - 0 (must be '0')
// [7] - self-refresh temperature range -
// 0 (normal), 1 (extended)
// [6] - Auto Self-Refresh - 0 (manual), 1(auto)
// [5:3] - CAS Write Latency (CWL) -
// 000 (5 for 400 MHz device),
// 001 (6 for 400 MHz to 533 MHz devices),
// 010 (7 for 533 MHz to 667 MHz devices),
// 011 (8 for 667 MHz to 800 MHz)
// [2:0] - Partial Array Self-Refresh (Optional) -
// 000 (full array)
// Not used for DDR2
//*****************************************************************
generate
if(DRAM_TYPE == "DDR3") begin: gen_load_mr2_DDR3
assign load_mr2[2:0] = 3'b000;
assign load_mr2[5:3] = (nCWL == 5) ? 3'b000 :
(nCWL == 6) ? 3'b001 :
(nCWL == 7) ? 3'b010 :
(nCWL == 8) ? 3'b011 :
(nCWL == 9) ? 3'b100 :
(nCWL == 10) ? 3'b101 :
(nCWL == 11) ? 3'b110 : 3'b111;
assign load_mr2[6] = 1'b0;
assign load_mr2[7] = 1'b0;
assign load_mr2[8] = 1'b0;
// Dynamic ODT disabled
assign load_mr2[10:9] = 2'b00;
assign load_mr2[15:11] = 5'b00000;
end else begin: gen_load_mr2_DDR2
assign load_mr2[15:0] = 16'd0;
end
endgenerate
//*****************************************************************
// DDR3 Load mode reg3
// Mode Register (MR3):
// [15:3] - unused - All zeros
// [2] - MPR Operation - 0(normal operation), 1(data flow from MPR)
// [1:0] - MPR location - 00 (Predefined pattern)
//*****************************************************************
assign load_mr3[1:0] = 2'b00;
assign load_mr3[2] = 1'b0;
assign load_mr3[15:3] = 13'b0000000000000;
// For multi-rank systems the rank being accessed during writes in
// Read Leveling must be sent to phy_write for the bitslip logic
assign calib_rank_cnt = chip_cnt_r;
//***************************************************************************
// Logic to begin initial calibration, and to handle precharge requests
// during read-leveling (to avoid tRAS violations if individual read
// levelling calibration stages take more than max{tRAS) to complete).
//***************************************************************************
// Assert when readback for each stage of read-leveling begins. However,
// note this indicates only when the read command is issued and when
// Phaser_IN has phase aligned FREQ_REF clock to read DQS. It does not
// indicate when the read data is present on the bus (when this happens
// after the read command is issued depends on CAS LATENCY) - there will
// need to be some delay before valid data is present on the bus.
// assign rdlvl_start_pre = (init_state_r == INIT_PI_PHASELOCK_READS);
// Assert when read back for write calibration begins
assign wrcal_start_pre = (init_state_r == INIT_WRCAL_READ);
// Common precharge signal done signal - pulses only when there has been
// a precharge issued as a result of a PRECH_REQ pulse. Note also a common
// PRECH_DONE signal is used for all blocks
assign prech_done_pre = (((init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ)) &&
prech_pending_r &&
!prech_req_posedge_r);
// Delay start of each calibration by 16 clock cycles to ensure that when
// calibration logic begins, read data is already appearing on the bus.
// Each circuit should synthesize using an SRL16. Assume that reset is
// long enough to clear contents of SRL16.
always @(posedge clk) begin
// rdlvl_start_dly0_r <= #TCQ {rdlvl_start_dly0_r[14:0],
// rdlvl_start_pre};
wrcal_start_dly_r <= #TCQ {wrcal_start_dly_r[14:0],
wrcal_start_pre};
prech_done_dly_r <= #TCQ {prech_done_dly_r[14:0],
prech_done_pre};
end
always @(posedge clk)
prech_done <= #TCQ prech_done_dly_r[15];
// Generate latched signals for start of write and read leveling
always @(posedge clk)
if (rst) begin
// pi_calib_start <= #TCQ 1'b0;
rdlvl_stg1_start <= #TCQ 1'b0;
rdlvl_stg1_start_int <= #TCQ 1'b0;
pi_dqs_found_start <= #TCQ 1'b0;
wrcal_start <= #TCQ 1'b0;
end else begin
if (!pi_dqs_found_done && init_state_r == INIT_RDLVL_STG2_READ)
pi_dqs_found_start <= #TCQ 1'b1;
if (pi_dqs_found_done && cnt_cmd_done_r &&
(init_state_r == INIT_RDLVL_ACT_WAIT))
rdlvl_stg1_start_int <= #TCQ 1'b1;
if (pi_dqs_found_done &&
(init_state_r == INIT_RDLVL_STG1_READ))
rdlvl_stg1_start <= #TCQ 1'b1;
if (wrcal_start_dly_r[5])
wrcal_start <= #TCQ 1'b1;
end // else: !if(rst)
always @(posedge clk)
if (rst)
pi_dqs_found_done_r1 <= #TCQ 1'b0;
else if (pi_dqs_found_done)
pi_dqs_found_done_r1 <= #TCQ 1'b1;
// Constantly enable DQS while write leveling is enabled in the memory
// This is more to get rid of warnings in simulation, can later change
// this code to only enable WRLVL_ACTIVE when WRLVL_START is asserted
generate
if (nCK_PER_CLK == 4) begin: en_cnt_div4
always @ (posedge clk)
if (rst || wrlvl_rank_done)
enable_wrlvl_cnt <= #TCQ 5'd0;
else if ((init_state_r == INIT_WRLVL_START) ||
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
enable_wrlvl_cnt <= #TCQ 5'd12;
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
// ODT stays asserted as long as write_calib
// signal is asserted
always @(posedge clk)
if (rst || wrlvl_rank_done || done_dqs_tap_inc)
wrlvl_odt <= #TCQ 1'b0;
else if (enable_wrlvl_cnt == 5'd1)
wrlvl_odt <= #TCQ 1'b1;
end else begin: en_cnt_div2
always @ (posedge clk)
if (rst)
enable_wrlvl_cnt <= #TCQ 5'd0;
else if ((init_state_r == INIT_WRLVL_START) ||
(wrlvl_odt && (enable_wrlvl_cnt == 5'd0)))
enable_wrlvl_cnt <= #TCQ 5'd21;
else if ((enable_wrlvl_cnt > 5'd0) && ~(phy_ctl_full || phy_cmd_full))
enable_wrlvl_cnt <= #TCQ enable_wrlvl_cnt - 1;
// ODT stays asserted as long as write_calib
// signal is asserted
always @(posedge clk)
if (rst || wrlvl_rank_done || done_dqs_tap_inc)
wrlvl_odt <= #TCQ 1'b0;
else if (enable_wrlvl_cnt == 5'd1)
wrlvl_odt <= #TCQ 1'b1;
end
endgenerate
always @(posedge clk)
if (rst || wrlvl_rank_done || done_dqs_tap_inc)
wrlvl_active <= #TCQ 1'b0;
else if ((enable_wrlvl_cnt == 5'd1) && wrlvl_odt && !wrlvl_active)
wrlvl_active <= #TCQ 1'b1;
// signal used to assert DQS for write leveling.
// the DQS will be asserted once every 16 clock cycles.
always @(posedge clk)begin
if(rst || (enable_wrlvl_cnt != 5'd1)) begin
wr_level_dqs_asrt <= #TCQ 1'd0;
end else if ((enable_wrlvl_cnt == 5'd1) && (wrlvl_active_r1)) begin
wr_level_dqs_asrt <= #TCQ 1'd1;
end
end
always @ (posedge clk) begin
if (rst)
dqs_asrt_cnt <= #TCQ 2'd0;
else if (wr_level_dqs_asrt && dqs_asrt_cnt != 2'd3)
dqs_asrt_cnt <= #TCQ (dqs_asrt_cnt + 1);
end
always @ (posedge clk) begin
if (rst || ~wrlvl_active)
wr_lvl_start <= #TCQ 1'd0;
else if (dqs_asrt_cnt == 2'd3)
wr_lvl_start <= #TCQ 1'd1;
end
always @(posedge clk) begin
if (rst)
wl_sm_start <= #TCQ 1'b0;
else
wl_sm_start <= #TCQ wr_level_dqs_asrt_r1;
end
always @(posedge clk) begin
wrlvl_active_r1 <= #TCQ wrlvl_active;
wr_level_dqs_asrt_r1 <= #TCQ wr_level_dqs_asrt;
wrlvl_done_r <= #TCQ wrlvl_done;
wrlvl_done_r1 <= #TCQ wrlvl_done_r;
wrlvl_rank_done_r1 <= #TCQ wrlvl_rank_done;
wrlvl_rank_done_r2 <= #TCQ wrlvl_rank_done_r1;
wrlvl_rank_done_r3 <= #TCQ wrlvl_rank_done_r2;
end
always @ (posedge clk) begin
if (rst)
wrlvl_rank_cntr <= #TCQ 3'd0;
else if (wrlvl_rank_done)
wrlvl_rank_cntr <= #TCQ wrlvl_rank_cntr + 1'b1;
end
//*****************************************************************
// Precharge request logic - those calibration logic blocks
// that require greater than tRAS(max) to finish must break up
// their calibration into smaller units of time, with precharges
// issued in between. This is done using the XXX_PRECH_REQ and
// PRECH_DONE handshaking between PHY_INIT and those blocks
//*****************************************************************
// Shared request from multiple sources
assign prech_req = rdlvl_prech_req | wrcal_prech_req;
// Handshaking logic to force precharge during read leveling, and to
// notify read leveling logic when precharge has been initiated and
// it's okay to proceed with leveling again
always @(posedge clk)
if (rst) begin
prech_req_r <= #TCQ 1'b0;
prech_req_posedge_r <= #TCQ 1'b0;
prech_pending_r <= #TCQ 1'b0;
end else begin
prech_req_r <= #TCQ prech_req;
prech_req_posedge_r <= #TCQ prech_req & ~prech_req_r;
if (prech_req_posedge_r)
prech_pending_r <= #TCQ 1'b1;
// Clear after we've finished with the precharge and have
// returned to issuing read leveling calibration reads
else if (prech_done_pre)
prech_pending_r <= #TCQ 1'b0;
end
//***************************************************************************
// Various timing counters
//***************************************************************************
//*****************************************************************
// Generic delay for various states that require it (e.g. for turnaround
// between read and write). Make this a sufficiently large number of clock
// cycles to cover all possible frequencies and memory components)
// Requirements for this counter:
// 1. Greater than tMRD
// 2. tRFC (refresh-active) for DDR2
// 3. (list the other requirements, slacker...)
//*****************************************************************
always @(posedge clk) begin
case (init_state_r)
INIT_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR_WAIT,
INIT_WRLVL_LOAD_MR2_WAIT,
INIT_RDLVL_ACT_WAIT,
INIT_RDLVL_STG1_WRITE_READ,
INIT_RDLVL_STG2_READ_WAIT,
INIT_WRCAL_ACT_WAIT,
INIT_WRCAL_WRITE_READ,
INIT_WRCAL_READ_WAIT,
INIT_PRECHARGE_PREWAIT,
INIT_PRECHARGE_WAIT,
INIT_DDR2_PRECHARGE_WAIT,
INIT_REG_WRITE_WAIT,
INIT_REFRESH_WAIT: begin
if (phy_ctl_full || phy_cmd_full)
cnt_cmd_r <= #TCQ cnt_cmd_r;
else
cnt_cmd_r <= #TCQ cnt_cmd_r + 1;
end
INIT_WRLVL_WAIT:
cnt_cmd_r <= #TCQ 'b0;
default:
cnt_cmd_r <= #TCQ 'b0;
endcase
end
// pulse when count reaches terminal count
always @(posedge clk)
cnt_cmd_done_r <= #TCQ (cnt_cmd_r == CNTNEXT_CMD);
always @(posedge clk) begin
if (rst)
detect_pi_found_dqs <= #TCQ 1'b0;
else if ((cnt_cmd_r == CNTNEXT_CMD) &&
(init_state_r == INIT_RDLVL_STG2_READ_WAIT))
detect_pi_found_dqs <= #TCQ 1'b1;
else
detect_pi_found_dqs <= #TCQ 1'b0;
end
//*****************************************************************
// Initial delay after power-on for RESET, CKE
// NOTE: Could reduce power consumption by turning off these counters
// after initial power-up (at expense of more logic)
// NOTE: Likely can combine multiple counters into single counter
//*****************************************************************
// Create divided by 1024 version of clock
always @(posedge clk)
if (rst) begin
cnt_pwron_ce_r <= #TCQ 10'h000;
pwron_ce_r <= #TCQ 1'b0;
end else begin
cnt_pwron_ce_r <= #TCQ cnt_pwron_ce_r + 1;
pwron_ce_r <= #TCQ (cnt_pwron_ce_r == 10'h3FF);
end
// "Main" power-on counter - ticks every CLKDIV/1024 cycles
always @(posedge clk)
if (rst)
cnt_pwron_r <= #TCQ 'b0;
else if (pwron_ce_r)
cnt_pwron_r <= #TCQ cnt_pwron_r + 1;
always @(posedge clk)
if (rst || ~phy_ctl_ready) begin
cnt_pwron_reset_done_r <= #TCQ 1'b0;
cnt_pwron_cke_done_r <= #TCQ 1'b0;
end else begin
// skip power-up count for simulation purposes only
if ((SIM_INIT_OPTION == "SKIP_PU_DLY") ||
(SIM_INIT_OPTION == "SKIP_INIT")) begin
cnt_pwron_reset_done_r <= #TCQ 1'b1;
cnt_pwron_cke_done_r <= #TCQ 1'b1;
end else begin
// otherwise, create latched version of done signal for RESET, CKE
if (DRAM_TYPE == "DDR3") begin
if (!cnt_pwron_reset_done_r)
cnt_pwron_reset_done_r
<= #TCQ (cnt_pwron_r == PWRON_RESET_DELAY_CNT);
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end else begin // DDR2
cnt_pwron_reset_done_r <= #TCQ 1'b1; // not needed
if (!cnt_pwron_cke_done_r)
cnt_pwron_cke_done_r
<= #TCQ (cnt_pwron_r == PWRON_CKE_DELAY_CNT);
end
end
end // else: !if(rst || ~phy_ctl_ready)
always @(posedge clk)
cnt_pwron_cke_done_r1 <= #TCQ cnt_pwron_cke_done_r;
// Keep RESET asserted and CKE deasserted until after power-on delay
always @(posedge clk) begin
phy_reset_n <= #TCQ cnt_pwron_reset_done_r;
// phy_cke <= #TCQ {CKE_WIDTH{cnt_pwron_cke_done_r}};
end
//*****************************************************************
// Counter for tXPR (pronouned "Tax-Payer") - wait time after
// CKE deassertion before first MRS command can be asserted
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_txpr_r <= #TCQ 'b0;
cnt_txpr_done_r <= #TCQ 1'b0;
end else begin
cnt_txpr_r <= #TCQ cnt_txpr_r + 1;
if (!cnt_txpr_done_r)
cnt_txpr_done_r <= #TCQ (cnt_txpr_r == TXPR_DELAY_CNT);
end
//*****************************************************************
// Counter for the initial 400ns wait for issuing precharge all
// command after CKE assertion. Only for DDR2.
//*****************************************************************
always @(posedge clk)
if (!cnt_pwron_cke_done_r) begin
cnt_init_pre_wait_r <= #TCQ 'b0;
cnt_init_pre_wait_done_r <= #TCQ 1'b0;
end else begin
cnt_init_pre_wait_r <= #TCQ cnt_init_pre_wait_r + 1;
if (!cnt_init_pre_wait_done_r)
cnt_init_pre_wait_done_r
<= #TCQ (cnt_init_pre_wait_r >= DDR2_INIT_PRE_CNT);
end
//*****************************************************************
// Wait for both DLL to lock (tDLLK) and ZQ calibration to finish
// (tZQINIT). Both take the same amount of time (512*tCK)
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_ZQCL) begin
cnt_dllk_zqinit_r <= #TCQ 'b0;
cnt_dllk_zqinit_done_r <= #TCQ 1'b0;
end else if (~(phy_ctl_full || phy_cmd_full)) begin
cnt_dllk_zqinit_r <= #TCQ cnt_dllk_zqinit_r + 1;
if (!cnt_dllk_zqinit_done_r)
cnt_dllk_zqinit_done_r
<= #TCQ (cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT);
end
//*****************************************************************
// Keep track of which MRS counter needs to be programmed during
// memory initialization
// The counter and the done signal are reset an additional time
// for DDR2. The same signals are used for the additional DDR2
// initialization sequence.
//*****************************************************************
always @(posedge clk)
if ((init_state_r == INIT_IDLE)||
((init_state_r == INIT_REFRESH)
&& (~mem_init_done_r))) begin
cnt_init_mr_r <= #TCQ 'b0;
cnt_init_mr_done_r <= #TCQ 1'b0;
end else if (init_state_r == INIT_LOAD_MR) begin
cnt_init_mr_r <= #TCQ cnt_init_mr_r + 1;
cnt_init_mr_done_r <= #TCQ (cnt_init_mr_r == INIT_CNT_MR_DONE);
end
//*****************************************************************
// Flag to tell if the first precharge for DDR2 init sequence is
// done
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_pre_flag_r<= #TCQ 'b0;
else if (init_state_r == INIT_LOAD_MR)
ddr2_pre_flag_r<= #TCQ 1'b1;
// reset the flag for multi rank case
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_pre_flag_r <= #TCQ 'b0;
//*****************************************************************
// Flag to tell if the refresh stat for DDR2 init sequence is
// reached
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
ddr2_refresh_flag_r<= #TCQ 'b0;
else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))
// reset the flag for multi rank case
ddr2_refresh_flag_r<= #TCQ 1'b1;
else if ((ddr2_refresh_flag_r) &&
(init_state_r == INIT_LOAD_MR_WAIT)&&
(cnt_cmd_done_r) && (cnt_init_mr_done_r))
ddr2_refresh_flag_r <= #TCQ 'b0;
//*****************************************************************
// Keep track of the number of auto refreshes for DDR2
// initialization. The spec asks for a minimum of two refreshes.
// Four refreshes are performed here. The two extra refreshes is to
// account for the 200 clock cycle wait between step h and l.
// Without the two extra refreshes we would have to have a
// wait state.
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE) begin
cnt_init_af_r <= #TCQ 'b0;
cnt_init_af_done_r <= #TCQ 1'b0;
end else if ((init_state_r == INIT_REFRESH) && (~mem_init_done_r))begin
cnt_init_af_r <= #TCQ cnt_init_af_r + 1;
cnt_init_af_done_r <= #TCQ (cnt_init_af_r == 2'b11);
end
//*****************************************************************
// Keep track of the register control word programming for
// DDR3 RDIMM
//*****************************************************************
always @(posedge clk)
if (init_state_r == INIT_IDLE)
reg_ctrl_cnt_r <= #TCQ 'b0;
else if (init_state_r == INIT_REG_WRITE)
reg_ctrl_cnt_r <= #TCQ reg_ctrl_cnt_r + 1;
always @(posedge clk)
if (init_state_r == INIT_IDLE)
stg1_wr_done <= #TCQ 1'b0;
else if (init_state_r == INIT_RDLVL_STG1_WRITE_READ)
stg1_wr_done <= #TCQ 1'b1;
//***************************************************************************
// Initialization state machine
//***************************************************************************
//*****************************************************************
// Next-state logic
//*****************************************************************
always @(posedge clk)
if (rst)begin
init_state_r <= #TCQ INIT_IDLE;
init_state_r1 <= #TCQ INIT_IDLE;
end else begin
init_state_r <= #TCQ init_next_state;
init_state_r1 <= #TCQ init_state_r;
end
always @(burst_addr_r or chip_cnt_r or cnt_cmd_done_r
or cnt_dllk_zqinit_done_r or cnt_init_af_done_r
or cnt_init_mr_done_r or phy_ctl_ready or phy_ctl_full
or phy_cmd_full or num_reads or dqs_dly_done or stg1_wr_done
// or ck_addr_cmd_delay_done
or cnt_init_pre_wait_done_r or cnt_pwron_cke_done_r
or cnt_txpr_done_r or ddr2_pre_flag_r
or ddr2_refresh_flag_r or ddr3_lm_done_r
or init_state_r or mem_init_done_r
or prech_req_posedge_r or wrcal_done or wrcal_resume
or rdlvl_stg1_done or rdlvl_stg1_rank_done or rdlvl_stg1_start_int
or stg1_wr_rd_cnt or read_calib_int or read_calib_r or pi_calib_done_r
or pi_dqs_found_done or pi_dqs_found_rank_done or pi_dqs_found_start
or reg_ctrl_cnt_r or wrlvl_done_r1 or wrlvl_rank_done_r3) begin
init_next_state = init_state_r;
(* full_case, parallel_case *) case (init_state_r)
//*******************************************************
// DRAM initialization
//*******************************************************
// Initial state - wait for:
// 1. Power-on delays to pass
// 2. PHY Control Block to assert phy_ctl_ready
// 3. PHY Control FIFO must not be FULL
// 4. Read path initialization to finish
INIT_IDLE:
if (cnt_pwron_cke_done_r && phy_ctl_ready
&& ~(phy_ctl_full || phy_cmd_full) && dqs_dly_done) begin
//&& ck_addr_cmd_delay_done) begin
// If skipping memory initialization (simulation only)
if (SIM_INIT_OPTION == "SKIP_INIT")
if (WRLVL == "ON")
// Proceed to write leveling
init_next_state = INIT_WRLVL_START;
else //if (SIM_CAL_OPTION != "SKIP_CAL")
// Proceed to Phaser_In phase lock
init_next_state = INIT_RDLVL_ACT;
// else
// Skip read leveling
//init_next_state = INIT_DONE;
else
init_next_state = INIT_WAIT_CKE_EXIT;
end
// Wait minimum of Reset CKE exit time (tXPR = max(tXS,
INIT_WAIT_CKE_EXIT:
if ((cnt_txpr_done_r) && (DRAM_TYPE == "DDR3")
&& ~(phy_ctl_full || phy_cmd_full)) begin
if((REG_CTRL == "ON") && ((nCS_PER_RANK > 1) ||
(RANKS > 1)))
//register write for reg dimm. Some register chips
// have the register chip in a pre-programmed state
// in that case the nCS_PER_RANK == 1 && RANKS == 1
init_next_state = INIT_REG_WRITE;
else
// Load mode register - this state is repeated multiple times
init_next_state = INIT_LOAD_MR;
end else if ((cnt_init_pre_wait_done_r) && (DRAM_TYPE == "DDR2")
&& ~(phy_ctl_full || phy_cmd_full))
// DDR2 start with a precharge all command
init_next_state = INIT_DDR2_PRECHARGE;
INIT_REG_WRITE:
init_next_state = INIT_REG_WRITE_WAIT;
INIT_REG_WRITE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if(reg_ctrl_cnt_r == 3'd5)
init_next_state = INIT_LOAD_MR;
else
init_next_state = INIT_REG_WRITE;
end
INIT_LOAD_MR:
init_next_state = INIT_LOAD_MR_WAIT;
// After loading MR, wait at least tMRD
INIT_LOAD_MR_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
// If finished loading all mode registers, proceed to next step
if(rdlvl_stg1_done && pi_dqs_found_done)
// for ddr3 when the correct burst length is writtern at end
init_next_state = INIT_PRECHARGE;
else if (cnt_init_mr_done_r)begin
if(DRAM_TYPE == "DDR3")
init_next_state = INIT_ZQCL;
else begin //DDR2
if(ddr2_refresh_flag_r)begin
// memory initialization per rank for multi-rank case
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
init_next_state = INIT_DDR2_MULTI_RANK;
else
init_next_state = INIT_RDLVL_ACT;
// ddr2 initialization done.load mode state after refresh
end else
init_next_state = INIT_DDR2_PRECHARGE;
end
end else
init_next_state = INIT_LOAD_MR;
end // if (cnt_cmd_done_r)
// DDR2 multi rank transition state
INIT_DDR2_MULTI_RANK:
init_next_state = INIT_DDR2_MULTI_RANK_WAIT;
INIT_DDR2_MULTI_RANK_WAIT:
init_next_state = INIT_DDR2_PRECHARGE;
// Initial ZQ calibration
INIT_ZQCL:
init_next_state = INIT_WAIT_DLLK_ZQINIT;
// Wait until both DLL have locked, and ZQ calibration done
INIT_WAIT_DLLK_ZQINIT:
if (cnt_dllk_zqinit_done_r && ~(phy_ctl_full || phy_cmd_full))
// memory initialization per rank for multi-rank case
if (!mem_init_done_r && (chip_cnt_r <= RANKS-1))
init_next_state = INIT_LOAD_MR;
else if (WRLVL == "ON")
init_next_state = INIT_WRLVL_START;
else
// skip write-leveling (e.g. for DDR2 interface)
init_next_state = INIT_RDLVL_ACT;
// Initial precharge for DDR2
INIT_DDR2_PRECHARGE:
init_next_state = INIT_DDR2_PRECHARGE_WAIT;
INIT_DDR2_PRECHARGE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if(ddr2_pre_flag_r)
init_next_state = INIT_REFRESH;
else// from precharge state initally go to load mode
init_next_state = INIT_LOAD_MR;
end
INIT_REFRESH:
init_next_state = INIT_REFRESH_WAIT;
INIT_REFRESH_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))begin
if(cnt_init_af_done_r && (~mem_init_done_r))
// go to lm state as part of DDR2 init sequence
init_next_state = INIT_LOAD_MR;
else if (((rdlvl_stg1_done && pi_dqs_found_done) && (WRLVL == "ON"))
&& mem_init_done_r)
init_next_state = INIT_WRCAL_ACT;
else if (mem_init_done_r)
init_next_state = INIT_RDLVL_ACT;
else // to DDR2 init state as part of DDR2 init sequence
init_next_state = INIT_REFRESH;
end
//******************************************************
// Write Leveling
//*******************************************************
// Enable write leveling in MR1 and start write leveling
// for current rank
INIT_WRLVL_START:
init_next_state = INIT_WRLVL_WAIT;
// Wait for both MR load and write leveling to complete
// (write leveling should take much longer than MR load..)
INIT_WRLVL_WAIT:
if (wrlvl_rank_done_r3 && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRLVL_LOAD_MR;
// Disable write leveling in MR1 for current rank
INIT_WRLVL_LOAD_MR:
init_next_state = INIT_WRLVL_LOAD_MR_WAIT;
INIT_WRLVL_LOAD_MR_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRLVL_LOAD_MR2;
// Load MR2 to set ODT: Dynamic ODT for single rank case
// And ODTs for multi-rank case as well
INIT_WRLVL_LOAD_MR2:
init_next_state = INIT_WRLVL_LOAD_MR2_WAIT;
// Wait tMRD before proceeding
INIT_WRLVL_LOAD_MR2_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if (~wrlvl_done_r1)
init_next_state = INIT_WRLVL_START;
else if (SIM_CAL_OPTION == "SKIP_CAL")
// If skip rdlvl, then we're done
init_next_state = INIT_DONE;
else
// Otherwise, proceed to read leveling
init_next_state = INIT_RDLVL_ACT;
end
//*******************************************************
// Read Leveling
//*******************************************************
// single row activate. All subsequent read leveling writes and
// read will take place in this row
INIT_RDLVL_ACT:
init_next_state = INIT_RDLVL_ACT_WAIT;
// hang out for awhile before issuing subsequent column commands
// it's also possible to reach this state at various points
// during read leveling - determine what the current stage is
INIT_RDLVL_ACT_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
// Just finished an activate. Now either write, read, or precharge
// depending on where we are in the training sequence
if (read_calib_int && !read_calib_r)
init_next_state = INIT_PI_PHASELOCK_READS;
else if (!pi_dqs_found_done)
// (!pi_dqs_found_start || pi_dqs_found_rank_done))
init_next_state = INIT_RDLVL_STG2_READ;
else if (!rdlvl_stg1_done && ~stg1_wr_done)
// (!rdlvl_stg1_start_int || rdlvl_stg1_rank_done))
// Case 1: If in stage 1, and entering for first then, then
// write training pattern to memory
//init_next_state = INIT_IOCONFIG_WR;
init_next_state = INIT_RDLVL_STG1_WRITE;
else if (!rdlvl_stg1_done && rdlvl_stg1_start_int)
// Case 2: If in stage 1, and just precharged after training
// previous byte, then continue reading
init_next_state = INIT_RDLVL_STG1_READ;
else
// Otherwise, if we're finished with calibration, then precharge
// the row - silly, because we just opened it - possible to take
// this out by adding logic to avoid the ACT in first place. Make
// sure that cnt_cmd_done will handle tRAS(min)
init_next_state = INIT_PRECHARGE_PREWAIT;
end
//**************************************************
// Back-to-back reads for Phaser_IN Phase locking
// DQS to FREQ_REF clock
//**************************************************
INIT_PI_PHASELOCK_READS:
if (pi_calib_done_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// Stage 1 read-leveling (write and continuous read)
//*********************************************
// Write training pattern for stage 1
// PRBS pattern of TBD length
INIT_RDLVL_STG1_WRITE:
// 4:1 DDR3 BL8 will require all 8 words in 1 DIV4 clock cycle
// 2:1 DDR2/DDR3 BL8 will require 2 DIV2 clock cycles for 8 words
// 2:1 DDR2 BL4 will require 1 DIV2 clock cycle for 4 words
// An entire row worth of writes issued before proceeding to reads
// The number of write is (2^column width)/burst length to accomodate
// PRBS pattern for window detection.
if (stg1_wr_rd_cnt == 9'd1)
init_next_state = INIT_RDLVL_STG1_WRITE_READ;
// Write-read turnaround
INIT_RDLVL_STG1_WRITE_READ:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_RDLVL_STG1_READ;
// Continuous read, where interruptible by precharge request from
// calibration logic. Also precharges when stage 1 is complete
// No precharges when reads provided to Phaser_IN for phase locking
// FREQ_REF to read DQS since data integrity is not important.
INIT_RDLVL_STG1_READ:
if (rdlvl_stg1_rank_done || rdlvl_stg1_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
//*********************************************
// Stage 2 read-leveling (alternate writes and set of 4 reads)
//*********************************************
// Read of training data. Note that Stage 2 is not a constant read,
// instead there is a large gap between each set of back-to-back reads
INIT_RDLVL_STG2_READ:
// 4 read commands issued back-to-back
//if (burst_addr_r == 1'b1)
if (num_reads == 'b1)
init_next_state = INIT_RDLVL_STG2_READ_WAIT;
// Wait before issuing the next set of reads. If a precharge request
// comes in then handle it
INIT_RDLVL_STG2_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if (pi_dqs_found_rank_done ||
pi_dqs_found_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
else if (cnt_cmd_done_r)
init_next_state = INIT_RDLVL_STG2_READ;
end
//*********************************************
// Write calibration
//*********************************************
// single row activate
INIT_WRCAL_ACT:
init_next_state = INIT_WRCAL_ACT_WAIT;
// hang out for awhile before issuing subsequent column command
INIT_WRCAL_ACT_WAIT:
if (cnt_cmd_done_r)
init_next_state = INIT_WRCAL_WRITE;
// Write training pattern for write calibration
INIT_WRCAL_WRITE:
// Once we've issued enough commands for 8 words - proceed to reads
if (burst_addr_r == 1'b1)
init_next_state = INIT_WRCAL_WRITE_READ;
// Write-read turnaround
INIT_WRCAL_WRITE_READ:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_WRCAL_READ;
INIT_WRCAL_READ:
if (burst_addr_r == 1'b1)
init_next_state = INIT_WRCAL_READ_WAIT;
INIT_WRCAL_READ_WAIT:
if (~(phy_ctl_full || phy_cmd_full)) begin
if (wrcal_resume)
init_next_state = INIT_WRCAL_WRITE;
else if (wrcal_done || prech_req_posedge_r)
init_next_state = INIT_PRECHARGE_PREWAIT;
// else if (cnt_cmd_done_r)
// init_next_state = INIT_WRCAL_READ;
end
//*********************************************
// Handling of precharge during and in between read-level stages
//*********************************************
// Make sure we aren't violating any timing specs by precharging
// immediately
INIT_PRECHARGE_PREWAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full))
init_next_state = INIT_PRECHARGE;
// Initiate precharge
INIT_PRECHARGE:
init_next_state = INIT_PRECHARGE_WAIT;
INIT_PRECHARGE_WAIT:
if (cnt_cmd_done_r && ~(phy_ctl_full || phy_cmd_full)) begin
if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done &&
pi_dqs_found_done && ((ddr3_lm_done_r) || (DRAM_TYPE == "DDR2")))
// If read leveling and phase detection calibration complete,
// and programing the correct burst length then we're finished
init_next_state = INIT_DONE;
else if ((wrcal_done || (WRLVL == "OFF")) && rdlvl_stg1_done
&& pi_dqs_found_done)
// after all calibration program the correct burst length
init_next_state = INIT_LOAD_MR;
else if (rdlvl_stg1_done && pi_dqs_found_done && (WRLVL == "ON"))
// If read leveling finished, proceed to write calibration
init_next_state = INIT_REFRESH;
else
// Otherwise, open row for read-leveling purposes
init_next_state = INIT_REFRESH;
end
//*******************************************************
// Initialization/Calibration done. Take a long rest, relax
//*******************************************************
INIT_DONE:
init_next_state = INIT_DONE;
endcase
end
//*****************************************************************
// Initialization done signal - asserted before leveling starts
//*****************************************************************
always @(posedge clk)
if (rst)
mem_init_done_r <= #TCQ 1'b0;
else if ((!cnt_dllk_zqinit_done_r &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT) &&
(chip_cnt_r == RANKS-1) && (DRAM_TYPE == "DDR3"))
|| ( (init_state_r == INIT_LOAD_MR_WAIT) &&
(ddr2_refresh_flag_r) && (chip_cnt_r == RANKS-1)
&& (cnt_init_mr_done_r) && (DRAM_TYPE == "DDR2")))
mem_init_done_r <= #TCQ 1'b1;
//*****************************************************************
// Write Calibration signal to PHY Control Block - asserted before
// Write Leveling starts
//*****************************************************************
always @(posedge clk) begin
if (rst || done_dqs_tap_inc)
write_calib <= #TCQ 1'b0;
else if (wrlvl_active_r1)
write_calib <= #TCQ 1'b1;
end
//*****************************************************************
// Read Calibration signal to PHY Control Block - asserted after
// Write Leveling during PHASER_IN phase locking stage.
// Must be de-asserted before Read Leveling
//*****************************************************************
always @(posedge clk) begin
if (rst || pi_calib_done_r)
read_calib_int <= #TCQ 1'b0;
else if (~pi_calib_done_r && (init_state_r == INIT_RDLVL_ACT_WAIT) &&
(cnt_cmd_r == CNTNEXT_CMD))
read_calib_int <= #TCQ 1'b1;
end
always @(posedge clk)
read_calib_r <= #TCQ read_calib_int;
always @(posedge clk) begin
if (rst || pi_calib_done_r)
read_calib <= #TCQ 1'b0;
else if (~pi_calib_done_r && (init_state_r == INIT_PI_PHASELOCK_READS))
read_calib <= #TCQ 1'b1;
end
always @(posedge clk)
if (rst)
pi_calib_done_r <= #TCQ 1'b0;
else if (pi_phase_locked_all)
pi_calib_done_r <= #TCQ 1'b1;
//*****************************************************************
// DDR3 final burst length programming done. For DDR3 during
// calibration the burst length is fixed to BL8. After calibration
// the correct burst length is programmed.
//*****************************************************************
always @(posedge clk)
if (rst)
ddr3_lm_done_r <= #TCQ 1'b0;
else if ((init_state_r == INIT_LOAD_MR_WAIT) &&
(chip_cnt_r == RANKS-1) && wrcal_done)
ddr3_lm_done_r <= #TCQ 1'b1;
always @(posedge clk)
pi_dqs_found_rank_done_r <= #TCQ pi_dqs_found_rank_done;
//***************************************************************************
// Logic for deep memory (multi-rank) configurations
//
//***************************************************************************
// For DDR3 asserted when
always @(posedge clk)
if (rst || (wrlvl_done_r &&
(init_state_r==INIT_WRLVL_LOAD_MR2_WAIT)))begin
chip_cnt_r <= #TCQ 2'b00;
end else if ((((init_state_r == INIT_WAIT_DLLK_ZQINIT) &&
(cnt_dllk_zqinit_r == TDLLK_TZQINIT_DELAY_CNT)) ||
((init_state_r!=INIT_WRLVL_LOAD_MR2_WAIT) &&
(init_next_state==INIT_WRLVL_LOAD_MR2_WAIT)) &&
(DRAM_TYPE == "DDR3")) ||
rdlvl_stg1_rank_done ||
(pi_dqs_found_rank_done && ~pi_dqs_found_rank_done_r) ||
((init_state_r == INIT_LOAD_MR_WAIT)&& cnt_cmd_done_r
&& wrcal_done) ||
((init_state_r == INIT_DDR2_MULTI_RANK)
&& (DRAM_TYPE == "DDR2"))) begin
if ((~mem_init_done_r || ~rdlvl_stg1_done || ~pi_dqs_found_done ||
// condition to increment chip_cnt during
// final burst length programming for DDR3
wrcal_done)
&& (chip_cnt_r != RANKS-1))
chip_cnt_r <= #TCQ chip_cnt_r + 1;
else
chip_cnt_r <= #TCQ 2'b00;
end
generate
if (DRAM_TYPE == "DDR3") begin: DDR3
always @(posedge clk)
if (rst)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
else if (RANKS == 1)
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}};
else begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
case (chip_cnt_r)
2'b00:begin
for (n = 0; n < nCS_PER_RANK*nCK_PER_CLK*2; n = n + (nCS_PER_RANK*2)) begin
phy_int_cs_n[n+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
end
end
2'b01:begin
for (p = nCS_PER_RANK; p < nCS_PER_RANK*nCK_PER_CLK*2; p = p + (nCS_PER_RANK*2)) begin
phy_int_cs_n[p+:nCS_PER_RANK] <= #TCQ {nCS_PER_RANK{1'b0}};
end
end
endcase
end
end else begin: DDR2
always @(posedge clk)
if (rst) begin
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end else begin
if (init_state_r == INIT_REG_WRITE) begin
// All ranks selected simultaneously
phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b0}};
end else if ((wrlvl_odt) ||
(init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH)) begin
// phy_int_cs_n <= #TCQ phy_tmp_cs1_r;
phy_int_cs_n[0] <= #TCQ 1'b0;
end
else phy_int_cs_n <= #TCQ {CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK{1'b1}};
end // else: !if(rst)
end // block: DDR2
endgenerate
assign phy_cs_n = phy_int_cs_n;
//***************************************************************************
// Write/read burst logic for calibration
//***************************************************************************
assign rdlvl_wr = (init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE);
assign rdlvl_rd = (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ);
assign rdlvl_wr_rd = rdlvl_wr | rdlvl_rd;
// keep track of current address - need this if burst length < 8 for
// calibration reads and writes. Make sure value always gets initialized
// to 0 before we enter write/read state. Used to keep track of when
// another burst must be issued on command/address bus
// Least significant two bits of address bus are always 2'b00 when
// command issued. Only bit[3] will vary depending on the burst length
// LS 3-bits of address to DRAM = {burst_addr, 2'b00}. This can be expanded
// for more bits if the training sequence is longer than 8 words
generate
if (nCK_PER_CLK == 4) begin:DIV4
always @(posedge clk)
if (rst || wrcal_done)
burst_addr_r <= #TCQ 1'b0;
else if ((init_state_r == INIT_WRCAL_ACT_WAIT) ||
(init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE_READ) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_WRCAL_READ_WAIT))
burst_addr_r <= #TCQ 1'b1;
else if (rdlvl_wr_rd)
burst_addr_r <= #TCQ ~burst_addr_r;
else
burst_addr_r <= #TCQ 1'b0;
end else begin: DIV2
always @(posedge clk)
// Address increments by
if (rdlvl_wr_rd)
burst_addr_r <= #TCQ ~burst_addr_r;
else
burst_addr_r <= #TCQ 1'b0;
end
endgenerate
// Read Level Stage 1 requires writes to the entire row since
// a PRBS pattern is being written. This counter keeps track
// of the number of writes which depends on the column width
// The (stg1_wr_rd_cnt==9'd0) condition was added so the col
// address wraps around during stage1 reads
always @(posedge clk)
if (rst || (init_state_r == INIT_RDLVL_STG1_WRITE_READ) ||
rdlvl_stg1_done || (stg1_wr_rd_cnt==9'd0))
stg1_wr_rd_cnt <= #TCQ NUM_STG1_WR_RD;
else if (init_state_r == INIT_RDLVL_STG1_WRITE)// ||
// (init_state_r == INIT_RDLVL_STG1_READ))
stg1_wr_rd_cnt <= #TCQ stg1_wr_rd_cnt - 1;
// 4 back-to-back reads with gaps for
// read data_offset calibration (rdlvl stage 2)
always @(posedge clk)
if (rst || (init_state_r == INIT_RDLVL_STG2_READ_WAIT))
num_reads <= #TCQ 2'b00;
else if ((num_reads > 2'b00) && ~(phy_ctl_full || phy_cmd_full))
num_reads <= #TCQ num_reads - 1;
else if ((init_state_r == INIT_RDLVL_STG2_READ) || phy_ctl_full || phy_cmd_full)
num_reads <= #TCQ 2'b11;
// determine how often to issue row command during read leveling writes
// and reads
always @(posedge clk)
if (rdlvl_wr_rd) begin
// if (BURST4_FLAG)
// new_burst_r <= #TCQ 1'b1;
// else
// new_burst_r <= #TCQ ~new_burst_r;
// end else
new_burst_r <= #TCQ 1'b1;
end
// indicate when a write is occurring. PHY_WRDATA_EN must be asserted
// simultaneous with the corresponding command/address for CWL = 5,6
always @(posedge clk) begin
rdlvl_wr_r <= #TCQ rdlvl_wr;
calib_wrdata_en <= #TCQ phy_wrdata_en;
end
generate
if ((nCK_PER_CLK == 4) || (BURST_MODE == "4")) begin: wrdqen_div4
// Write data enable asserted for one DIV4 clock cycle
// Only BL8 supported with DIV4. DDR2 BL4 will use DIV2.
always @(rst or phy_data_full or init_state_r) begin
//always @(posedge clk) begin
if (rst)
phy_wrdata_en = 1'b0;
else if (~phy_data_full && ((init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)))
phy_wrdata_en = 1'b1;
else
phy_wrdata_en = 1'b0;
end
end else begin: wrdqen_div2
// For DDR2 BL8 when DIV2 mode is used phy_wrdata_en must be asserted for
// 2 DIV2 clock cycles because 4 words are output per DIV2 clock cycle.
always @(rdlvl_wr or rdlvl_wr_r)
phy_wrdata_en = rdlvl_wr | rdlvl_wr_r;
end
endgenerate
// indicate when a write is occurring. PHY_RDDATA_EN must be asserted
// simultaneous with the corresponding command/address. PHY_RDDATA_EN
// is used during read-leveling to determine read latency
assign phy_rddata_en = ~phy_if_empty;
// Read data valid generation for MC and User Interface after calibration is
// complete
assign phy_rddata_valid = (init_complete_r1) ? phy_rddata_en : 1'b0;
//***************************************************************************
// Generate training data written at start of each read-leveling stage
// For every stage of read leveling, 8 words are written into memory
// The format is as follows (shown as {rise,fall}):
// Stage 1: 0xF, 0x0, 0xF, 0x0, 0xF, 0x0, 0xF, 0x0
// Stage 2: 0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6
//***************************************************************************
always @(posedge clk)
if ((init_state_r == INIT_IDLE) ||
(init_state_r == INIT_RDLVL_STG1_WRITE))
cnt_init_data_r <= #TCQ 2'b00;
else if (phy_wrdata_en)
cnt_init_data_r <= #TCQ cnt_init_data_r + 1;
else if (init_state_r == INIT_WRCAL_WRITE)
cnt_init_data_r <= #TCQ 2'b10;
always @(posedge clk) begin
prbs_r1 <= #TCQ prbs_o;
prbs_r2 <= #TCQ prbs_r1;
prbs_r3 <= #TCQ prbs_r2;
prbs_r4 <= #TCQ prbs_r3;
prbs_r5 <= #TCQ prbs_r4;
prbs_r6 <= #TCQ prbs_r5;
prbs_r7 <= #TCQ prbs_r6;
end
generate
if (nCK_PER_CLK == 4) begin: wrdq_div4_bl8
always @(posedge clk)
if (phy_wrdata_en && (!rdlvl_stg1_done)) //phy_wrdata_en
// Replace with PRBS pattern
phy_wrdata <= #TCQ {prbs_o[DQ_WIDTH-1:0],prbs_r1[DQ_WIDTH-1:0],
prbs_r2[DQ_WIDTH-1:0],prbs_r3[DQ_WIDTH-1:0],
prbs_r4[DQ_WIDTH-1:0],prbs_r5[DQ_WIDTH-1:0],
prbs_r6[DQ_WIDTH-1:0],prbs_r7[DQ_WIDTH-1:0]};
else if (phy_wrdata_en && rdlvl_stg1_done) //phy_wrdata_en
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}},
{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
end else begin: wrdq_div2_bl4_8
always @(posedge clk)
(* full_case, parallel_case *) case (cnt_init_data_r)
// Replace with PRBS pattern
2'b00:
phy_wrdata <= #TCQ {prbs_o[DQ_WIDTH-1:0],prbs_r1[DQ_WIDTH-1:0],
prbs_r2[DQ_WIDTH-1:0],prbs_r3[DQ_WIDTH-1:0]};
// Replace with PRBS pattern
2'b01:
phy_wrdata <= #TCQ {prbs_r4[DQ_WIDTH-1:0],prbs_r5[DQ_WIDTH-1:0],
prbs_r6[DQ_WIDTH-1:0],prbs_r7[DQ_WIDTH-1:0]};
2'b10:
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h5}},{DQ_WIDTH/4{4'hA}},
{DQ_WIDTH/4{4'h0}},{DQ_WIDTH/4{4'hF}}};
2'b11:
phy_wrdata <= #TCQ {{DQ_WIDTH/4{4'h6}},{DQ_WIDTH/4{4'h9}},
{DQ_WIDTH/4{4'hA}},{DQ_WIDTH/4{4'h5}}};
endcase
end
endgenerate
//***************************************************************************
// Memory control/address
//***************************************************************************
generate
if (nCK_PER_CLK == 4) begin: div_4
// Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging
// (4) auto refresh
if (!(CWL_M % 2)) begin: even_cwl
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n[0] <= #TCQ 1'b0;
phy_ras_n[1] <= #TCQ 1'b1;
phy_ras_n[2] <= #TCQ 1'b1;
phy_ras_n[3] <= #TCQ 1'b1;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
phy_ras_n[2] <= #TCQ 1'b1;
phy_ras_n[3] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b0;
phy_cas_n[1] <= #TCQ 1'b1;
phy_cas_n[2] <= #TCQ 1'b1;
phy_cas_n[3] <= #TCQ 1'b1;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
phy_cas_n[2] <= #TCQ 1'b1;
phy_cas_n[3] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b0;
phy_we_n[1] <= #TCQ 1'b1;
phy_we_n[2] <= #TCQ 1'b1;
phy_we_n[3] <= #TCQ 1'b1;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
phy_we_n[2] <= #TCQ 1'b1;
phy_we_n[3] <= #TCQ 1'b1;
end
end // even_cwl
end else begin: odd_cwl
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b0;
phy_ras_n[2] <= #TCQ 1'b1;
phy_ras_n[3] <= #TCQ 1'b1;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
phy_ras_n[2] <= #TCQ 1'b1;
phy_ras_n[3] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b0;
phy_cas_n[2] <= #TCQ 1'b1;
phy_cas_n[3] <= #TCQ 1'b1;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
phy_cas_n[2] <= #TCQ 1'b1;
phy_cas_n[3] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b0;
phy_we_n[2] <= #TCQ 1'b1;
phy_we_n[3] <= #TCQ 1'b1;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
phy_we_n[2] <= #TCQ 1'b1;
phy_we_n[3] <= #TCQ 1'b1;
end
end
end // even_cwl
end else begin: div_2
// Assert RAS when: (1) Loading MRS, (2) Activating Row, (3) Precharging
// (4) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE) ||
(init_state_r == INIT_REFRESH))begin
phy_ras_n[0] <= #TCQ 1'b0;
phy_ras_n[1] <= #TCQ 1'b0;
end else begin
phy_ras_n[0] <= #TCQ 1'b1;
phy_ras_n[1] <= #TCQ 1'b1;
end
end
// Assert CAS when: (1) Loading MRS, (2) Issuing Read/Write command
// (3) auto refresh
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_REFRESH) ||
(rdlvl_wr_rd && new_burst_r))begin
phy_cas_n[0] <= #TCQ 1'b0;
phy_cas_n[1] <= #TCQ 1'b0;
end else begin
phy_cas_n[0] <= #TCQ 1'b1;
phy_cas_n[1] <= #TCQ 1'b1;
end
end
// Assert WE when: (1) Loading MRS, (2) Issuing Write command (only
// occur during read leveling), (3) Issuing ZQ Long Calib command,
// (4) Precharge
always @(posedge clk) begin
if ((init_state_r == INIT_LOAD_MR) ||
(init_state_r == INIT_REG_WRITE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_WRLVL_START) ||
// ((init_state_r == INIT_WRLVL_WAIT) && wr_level_dqs_asrt) ||
(init_state_r == INIT_WRLVL_LOAD_MR) ||
(init_state_r == INIT_WRLVL_LOAD_MR2) ||
(init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_DDR2_PRECHARGE)||
(rdlvl_wr && new_burst_r))begin
phy_we_n[0] <= #TCQ 1'b0;
phy_we_n[1] <= #TCQ 1'b0;
end else begin
phy_we_n[0] <= #TCQ 1'b1;
phy_we_n[1] <= #TCQ 1'b1;
end
end
end
endgenerate
// Assign calib_cmd for the command field in PHY_Ctl_Word
always @(posedge clk) begin
if (wr_level_dqs_asrt) begin
// Request to toggle DQS during write leveling
calib_cmd <= #TCQ 3'b001;
if (CWL_M % 2) // odd write latency
calib_data_offset <= #TCQ CWL_M + 3;
else // even write latency
calib_data_offset <= #TCQ CWL_M + 2;
end else if (rdlvl_wr && new_burst_r) begin
// Write Command
calib_cmd <= #TCQ 3'b001;
if (CWL_M % 2) // odd write latency
calib_data_offset <= #TCQ CWL_M + 3;
else // even write latency
calib_data_offset <= #TCQ CWL_M + 2;
end else if (rdlvl_rd && new_burst_r) begin
// Read Command
calib_cmd <= #TCQ 3'b011;
if (~pi_calib_done_r)
calib_data_offset <= #TCQ 6'd0;
else if (~pi_dqs_found_done_r1)
calib_data_offset <= #TCQ rd_data_offset;
else
calib_data_offset <= #TCQ rd_data_offset_ranks[6*chip_cnt_r+:6];
end else begin
// Non-Data Commands like NOP, MRS, ZQ Long Cal, Precharge,
// Active, Refresh
calib_cmd <= #TCQ 3'b100;
calib_data_offset <= #TCQ 6'd0;
end
end
// Write Enable to PHY_Control FIFO always asserted
// No danger of this FIFO being Full with 4:1 sync clock ratio
// This is also the write enable to the command OUT_FIFO
always @(posedge clk) begin
if (rst) begin
calib_ctl_wren <= #TCQ 1'b0;
calib_cmd_wren <= #TCQ 1'b0;
calib_seq <= #TCQ 2'b00;
end else if (cnt_pwron_cke_done_r && phy_ctl_ready
&& ~(phy_ctl_full || phy_cmd_full)) begin
// && ck_addr_cmd_delay_done) begin
calib_ctl_wren <= #TCQ 1'b1;
calib_cmd_wren <= #TCQ 1'b1;
calib_seq <= #TCQ calib_seq + 1;
end else begin
calib_ctl_wren <= #TCQ 1'b0;
calib_cmd_wren <= #TCQ 1'b0;
calib_seq <= #TCQ calib_seq;
end
end
generate
genvar rnk_i;
for (rnk_i = 0; rnk_i < 4; rnk_i = rnk_i + 1) begin: gen_rnk
always @(posedge clk) begin
if (rst) begin
mr2_r[rnk_i] <= #TCQ 2'b00;
mr1_r[rnk_i] <= #TCQ 3'b000;
end else begin
mr2_r[rnk_i] <= #TCQ tmp_mr2_r[rnk_i];
mr1_r[rnk_i] <= #TCQ tmp_mr1_r[rnk_i];
end
end
end
endgenerate
// ODT assignment based on slot config and slot present
// For single slot systems slot_1_present input will be ignored
// Assuming component interfaces to be single slot systems
generate
if (nSLOTS == 1) begin: gen_single_slot_odt
always @(posedge clk) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt_r <= #TCQ 4'b0000;
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
case ({slot_0_present[0],slot_0_present[1],
slot_0_present[2],slot_0_present[3]})
// Single slot configuration with quad rank
// Assuming same behavior as single slot dual rank for now
// DDR2 does not have quad rank parts
4'b1111: begin
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
phy_tmp_odt_r <= #TCQ 4'b0001;
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
end
// Single slot configuration with single rank
4'b1000: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
if ((REG_CTRL == "ON") && (nCS_PER_RANK > 1)) begin
phy_tmp_cs1_r[chip_cnt_r] <= #TCQ 1'b0;
end else begin
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
end
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Single slot configuration with dual rank
4'b1100: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
// Chip Select assignments
phy_tmp_cs1_r[((chip_cnt_r*nCS_PER_RANK)
) +: nCS_PER_RANK] <= #TCQ 'b0;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
default: begin
phy_tmp_odt_r <= #TCQ 4'b0001;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
endcase // case({slot_0_present[0],slot_0_present[1],...
end
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
always @ (posedge clk) begin
tmp_mr2_r[1] <= #TCQ 2'b00;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
tmp_mr1_r[1] <= #TCQ 3'b000;
tmp_mr1_r[2] <= #TCQ 3'b000;
tmp_mr1_r[3] <= #TCQ 3'b000;
phy_tmp_odt_r <= #TCQ 4'b0000;
phy_tmp_cs1_r <= #TCQ {CS_WIDTH*nCS_PER_RANK{1'b1}};
phy_tmp_odt_r1 <= #TCQ phy_tmp_odt_r;
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
// Two slot configuration, one slot present, single rank
4'b10_00: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b00_10: begin
//Rank1 ODT enabled
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
phy_tmp_cs1_r <= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one slot present, dual rank
4'b00_11: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
4'b11_00: begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
// odt turned on only during write
phy_tmp_odt_r <= #TCQ 4'b0001;
end
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank1 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end
end
// Two slot configuration, one rank per slot
4'b10_10: begin
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r == 2'b00)begin
phy_tmp_odt_r
<= #TCQ 4'b0010; //bit0 for rank0
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001; //bit0 for rank0
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
phy_tmp_odt_r
<= #TCQ 4'b0011; //bit0 for rank0
end else if ((init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ)) begin
if (chip_cnt_r == 2'b00) begin
phy_tmp_odt_r
<= #TCQ 4'b0010;
end else if (chip_cnt_r == 2'b01) begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end
end // else: !if(DRAM_TYPE == "DDR2")
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
end
end
// Two Slots - One slot with dual rank and the other with single rank
4'b10_11: begin
//Rank3 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[2] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 :
(RTT_NOM3 == "120") ? 3'b010 :
(RTT_NOM3 == "20") ? 3'b100 :
(RTT_NOM3 == "30") ? 3'b101 :
3'b011;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ 3'b000;
end
//Slot1 Rank1 or Rank3 is being written
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r == 2'b00)begin
phy_tmp_odt_r
<= #TCQ 4'b0010;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0011;
//Slot0 Rank0 is being written
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0101; // ODT for ranks 0 and 2 aserted
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ)
|| (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ))begin
if (chip_cnt_r == 2'b00) begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end
end
end // else: !if(DRAM_TYPE == "DDR2")
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - One slot with dual rank and the other with single rank
4'b11_10: begin
//Rank2 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
3'b011;
tmp_mr2_r[2] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end // else: !if((RTT_WR == "OFF") ||...
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt_r <=
#TCQ 4'b0001;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100; // rank 2 ODT asserted
end
end else begin
if (// wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0110;
end else begin
phy_tmp_odt_r <=
#TCQ 4'b0101;
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ)
|| (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ)) begin
if (chip_cnt_r[1] == 1'b1) begin
phy_tmp_odt_r[(1*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ 4'b0010;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end
end // if (init_state_r == INIT_IOCONFIG_RD)
end // else: !if(DRAM_TYPE == "DDR2")
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
// Two Slots - two ranks per slot
4'b11_11: begin
//Rank2 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[2] <= #TCQ (RTT_NOM2 == "60") ? 3'b001 :
(RTT_NOM2 == "120") ? 3'b010 :
(RTT_NOM2 == "20") ? 3'b100 :
(RTT_NOM2 == "30") ? 3'b101 :
3'b011;
//Rank3 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[3] <= #TCQ (RTT_NOM3 == "60") ? 3'b001 :
(RTT_NOM3 == "120") ? 3'b010 :
(RTT_NOM3 == "20") ? 3'b100 :
(RTT_NOM3 == "30") ? 3'b101 :
3'b011;
tmp_mr2_r[2] <= #TCQ 2'b00;
tmp_mr2_r[3] <= #TCQ 2'b00;
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done &&
(wrlvl_rank_cntr==3'd0))) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM
tmp_mr1_r[1] <= #TCQ 3'b000;
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM
tmp_mr1_r[0] <= #TCQ 3'b000;
end // else: !if((RTT_WR == "OFF") ||...
if(DRAM_TYPE == "DDR2")begin
if(chip_cnt_r[1] == 1'b1)begin
phy_tmp_odt_r
<= #TCQ 4'b0001;
end else begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
end
end else begin
if (//wrlvl_odt ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)) begin
//Slot1 Rank1 or Rank3 is being written
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0110;
//Slot0 Rank0 or Rank2 is being written
end else begin
phy_tmp_odt_r
<= #TCQ 4'b1001;
end
end else if ((init_state_r == INIT_RDLVL_STG1_READ)
|| (init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG2_READ) ||
(init_state_r == INIT_WRCAL_READ))begin
//Slot1 Rank1 or Rank3 is being read
if (chip_cnt_r[0] == 1'b1) begin
phy_tmp_odt_r
<= #TCQ 4'b0100;
//Slot0 Rank0 or Rank2 is being read
end else begin
phy_tmp_odt_r
<= #TCQ 4'b1000;
end
end // if (init_state_r == INIT_IOCONFIG_RD)
end // else: !if(DRAM_TYPE == "DDR2")
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
end
default: begin
phy_tmp_odt_r <= #TCQ 4'b1111;
// Chip Select assignments
phy_tmp_cs1_r[(chip_cnt_r*nCS_PER_RANK) +: nCS_PER_RANK]
<= #TCQ {nCS_PER_RANK{1'b0}};
if ((RTT_WR == "OFF") ||
((WRLVL=="ON") && ~wrlvl_done)) begin
//Rank0 Dynamic ODT disabled
tmp_mr2_r[0] <= #TCQ 2'b00;
//Rank0 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
//Rank1 Dynamic ODT disabled
tmp_mr2_r[1] <= #TCQ 2'b00;
//Rank1 Rtt_NOM defaults to 120 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "40") ? 3'b011 :
(RTT_NOM == "60") ? 3'b001 :
3'b010;
end else begin
//Rank0 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[0] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank0 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[0] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
//Rank1 Dynamic ODT defaults to 120 ohms
tmp_mr2_r[1] <= #TCQ (RTT_WR == "60") ? 2'b01 :
2'b10;
//Rank1 Rtt_NOM defaults to 40 ohms
tmp_mr1_r[1] <= #TCQ (RTT_NOM == "60") ? 3'b001 :
(RTT_NOM == "120") ? 3'b010 :
(RTT_NOM == "20") ? 3'b100 :
(RTT_NOM == "30") ? 3'b101 :
3'b011;
end
end
endcase
end
end
endgenerate
// ODT (calib_aux_out) bus width is fixed to 4 for up to 4 ranks support
// CKE is also part of the calib_aux_out bus
// For single rank calib_aux_out0[1] used for ODT and calib_aux_out0[0]
// used for CKE.
// For dual rank I/Fs calib_aux_out0[1]&[3] used for ODT and
// calib_aux_out0[0] & [2] used for CKE.
// For 4 rank I/Fs calib_aux_out0[3:0] used for ODT and calib_aux_out1[3:0]
// used for CKE.
generate
if ((nSLOTS == 1) && (RANKS > 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out0 <= #TCQ 4'b0000;
calib_aux_out1 <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)
calib_aux_out1 <= #TCQ {CKE_WIDTH{1'b1}};
else
calib_aux_out1 <= #TCQ {CKE_WIDTH{1'b0}};
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3"))
calib_aux_out0 <= #TCQ 4'b0000;
else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)))
// Quad rank in a single slot
calib_aux_out0 <= #TCQ phy_tmp_odt_r;
else
calib_aux_out0 <= #TCQ 4'b0000;
end
end else if ((nSLOTS == 1) && (RANKS <= 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out0 <= #TCQ 4'b0000;
calib_aux_out1 <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out0[0] <= #TCQ 1'b1;
calib_aux_out0[2] <= #TCQ 1'b1;
end else begin
calib_aux_out0[0] <= #TCQ 1'b0;
calib_aux_out0[2] <= #TCQ 1'b0;
end
calib_aux_out1 <= #TCQ 4'b0000;
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out0[1] <= #TCQ 1'b0;
calib_aux_out0[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE))) begin
// Quad rank in a single slot
calib_aux_out0[1] <= #TCQ phy_tmp_odt_r[0];
calib_aux_out0[3] <= #TCQ phy_tmp_odt_r[1];
end else begin
calib_aux_out0[1] <= #TCQ 1'b0;
calib_aux_out0[3] <= #TCQ 1'b0;
end
end
end else if ((nSLOTS == 2) && (RANKS > 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out0 <= #TCQ 4'b0000;
calib_aux_out1 <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)
calib_aux_out1 <= #TCQ {CKE_WIDTH{1'b1}};
else
calib_aux_out1 <= #TCQ {CKE_WIDTH{1'b0}};
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3"))
calib_aux_out0 <= #TCQ 4'b0000;
else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE)))
// Quad rank in a single slot
calib_aux_out0 <= #TCQ phy_tmp_odt_r | phy_tmp_odt_r1;
else
calib_aux_out0 <= #TCQ 4'b0000;
end
end else if ((nSLOTS == 2) && (RANKS <= 2)) begin
always @(posedge clk)
if (rst) begin
calib_aux_out0 <= #TCQ 4'b0000;
calib_aux_out1 <= #TCQ 4'b0000;
end else begin
if (cnt_pwron_cke_done_r && ~cnt_pwron_cke_done_r1)begin
calib_aux_out0[0] <= #TCQ 1'b1;
calib_aux_out0[2] <= #TCQ 1'b1;
end else begin
calib_aux_out0[0] <= #TCQ 1'b0;
calib_aux_out0[2] <= #TCQ 1'b0;
end
calib_aux_out1 <= #TCQ 4'b0000;
if ((((RTT_NOM == "DISABLED") && (RTT_WR == "OFF")) ||
wrlvl_rank_done || wrlvl_rank_done_r1 ||
(wrlvl_done && !wrlvl_done_r)) && (DRAM_TYPE == "DDR3")) begin
calib_aux_out0[1] <= #TCQ 1'b0;
calib_aux_out0[3] <= #TCQ 1'b0;
end else if (((DRAM_TYPE == "DDR3")
||((RTT_NOM != "DISABLED") && (DRAM_TYPE == "DDR2")))
&& (((init_state_r == INIT_WRLVL_WAIT) && wrlvl_odt) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_WRCAL_WRITE))) begin
// Quad rank in a single slot
calib_aux_out0[1] <= #TCQ phy_tmp_odt_r[0] | phy_tmp_odt_r1[0];
calib_aux_out0[3] <= #TCQ phy_tmp_odt_r[1] | phy_tmp_odt_r1[1];
end else begin
calib_aux_out0[1] <= #TCQ 1'b0;
calib_aux_out0[3] <= #TCQ 1'b0;
end
end
end
endgenerate
//*****************************************************************
// memory address during init
//*****************************************************************
always @(burst_addr_r or cnt_init_mr_r or chip_cnt_r
or ddr2_refresh_flag_r or init_state_r or load_mr0
or load_mr1 or load_mr2 or load_mr3 or mr1_r[chip_cnt_r][0]
or mr1_r[chip_cnt_r][1] or mr1_r[chip_cnt_r][2] or mr2_r[chip_cnt_r]
or rdlvl_stg1_done or pi_dqs_found_done or rdlvl_wr_rd
or reg_ctrl_cnt_r)begin
// Bus 0 for address/bank never used
address_w = 'b0;
bank_w = 'b0;
if ((init_state_r == INIT_PRECHARGE) ||
(init_state_r == INIT_ZQCL) ||
(init_state_r == INIT_DDR2_PRECHARGE)) begin
// Set A10=1 for ZQ long calibration or Precharge All
address_w = 'b0;
address_w[10] = 1'b1;
bank_w = 'b0;
end else if (init_state_r == INIT_WRLVL_START) begin
// Enable wrlvl in MR1
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[7] = 1'b1;
end else if (init_state_r == INIT_WRLVL_LOAD_MR) begin
// Finished with write leveling, disable wrlvl in MR1
// For single rank disable Rtt_Nom
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end else if (init_state_r == INIT_WRLVL_LOAD_MR2) begin
// Set RTT_WR in MR2 after write leveling disabled
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end else if ((init_state_r == INIT_REG_WRITE)&
(DRAM_TYPE == "DDR3"))begin
// bank_w is assigned a 3 bit value. In some
// DDR2 cases there will be only two bank bits.
//Qualifying the condition with DDR3
bank_w = 'b0;
address_w = 'b0;
case (reg_ctrl_cnt_r)
REG_RC0[2:0]: address_w[4:0] = REG_RC0[4:0];
REG_RC1[2:0]:begin
address_w[4:0] = REG_RC1[4:0];
bank_w = REG_RC1[7:5];
end
REG_RC2[2:0]: address_w[4:0] = REG_RC2[4:0];
REG_RC3[2:0]: address_w[4:0] = REG_RC3[4:0];
REG_RC4[2:0]: address_w[4:0] = REG_RC4[4:0];
REG_RC5[2:0]: address_w[4:0] = REG_RC5[4:0];
endcase
end else if (init_state_r == INIT_LOAD_MR) begin
// If loading mode register, look at cnt_init_mr to determine
// which MR is currently being programmed
address_w = 'b0;
bank_w = 'b0;
if(DRAM_TYPE == "DDR3")begin
if(rdlvl_stg1_done && pi_dqs_found_done)begin
// end of the calibration programming correct
// burst length
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0; //Don't reset DLL
end else begin
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
address_w[10:9] = mr2_r[chip_cnt_r];
end
INIT_CNT_MR3: begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[2] = mr1_r[chip_cnt_r][0];
address_w[6] = mr1_r[chip_cnt_r][1];
address_w[9] = mr1_r[chip_cnt_r][2];
end
INIT_CNT_MR0: begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
// fixing it to BL8 for calibration
address_w[1:0] = 2'b00;
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase // case(cnt_init_mr_r)
end // else: !if(rdlvl_stg1_done && rdlvl_stg2_done)
end else begin // DDR2
case (cnt_init_mr_r)
INIT_CNT_MR2: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b10;
address_w = load_mr2[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL
end
end
INIT_CNT_MR3: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b11;
address_w = load_mr3[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
address_w[8]= 1'b0;
//MRS command without resetting DLL. Repeted again
// because there is an extra state.
end
end
INIT_CNT_MR1: begin
bank_w[1:0] = 2'b01;
if(~ddr2_refresh_flag_r)begin
address_w = load_mr1[ROW_WIDTH-1:0];
end else begin // second set of lm commands
address_w = load_mr1[ROW_WIDTH-1:0];
address_w[9:7] = 3'b111;
//OCD default state
end
end
INIT_CNT_MR0: begin
if(~ddr2_refresh_flag_r)begin
bank_w[1:0] = 2'b00;
address_w = load_mr0[ROW_WIDTH-1:0];
end else begin // second set of lm commands
bank_w[1:0] = 2'b01;
address_w = load_mr1[ROW_WIDTH-1:0];
if((chip_cnt_r == 2'd1) || (chip_cnt_r == 2'd3))begin
// always disable odt for rank 1 and rank 3 as per SPEC
address_w[2] = 'b0;
address_w[6] = 'b0;
end
//OCD exit
end
end
default: begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
endcase // case(cnt_init_mr_r)
end
end else if ((init_state_r == INIT_PI_PHASELOCK_READS) ||
(init_state_r == INIT_RDLVL_STG1_WRITE) ||
(init_state_r == INIT_RDLVL_STG1_READ)) begin
// Writing and reading PRBS pattern for read leveling stage 1
// Need to support burst length 4 or 8. PRBS pattern will be
// written to entire row and read back from the same row repeatedly
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
if (stg1_wr_rd_cnt == NUM_STG1_WR_RD)
address_w[COL_WIDTH-1:0] = {COL_WIDTH{1'b0}};
else if (stg1_wr_rd_cnt >= 9'd0)
address_w[COL_WIDTH-1:0] = phy_address[COL_WIDTH-1:0] + ADDR_INC;
end else if ((init_state_r == INIT_WRCAL_WRITE) ||
(init_state_r == INIT_WRCAL_READ) ||
(init_state_r == INIT_RDLVL_STG2_READ)) begin
// when writing or reading back training pattern for read leveling stage2
// need to support burst length of 4 or 8. This may mean issuing
// multiple commands to cover the entire range of addresses accessed
// during read leveling.
// Hard coding A[12] to 1 so that it will always be burst length of 8
// for DDR3. Does not have any effect on DDR2.
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w[ROW_WIDTH-1:COL_WIDTH] = {ROW_WIDTH-COL_WIDTH{1'b0}};
address_w[COL_WIDTH-1:0] =
{CALIB_COL_ADD[COL_WIDTH-1:3],burst_addr_r, 3'b000};
address_w[12] = 1'b1;
end else if ((init_state_r == INIT_RDLVL_ACT) ||
(init_state_r == INIT_WRCAL_ACT)) begin
bank_w = CALIB_BA_ADD[BANK_WIDTH-1:0];
address_w = CALIB_ROW_ADD[ROW_WIDTH-1:0];
end else begin
bank_w = {BANK_WIDTH{1'bx}};
address_w = {ROW_WIDTH{1'bx}};
end
end
// registring before sending out
always @(posedge clk) begin
for (i = 0; i < nCK_PER_CLK; i = i + 1) begin: div_clk_loop
phy_address[(i*ROW_WIDTH) +: ROW_WIDTH] <= #TCQ address_w;
phy_bank[(i*BANK_WIDTH) +: BANK_WIDTH] <= #TCQ bank_w;
end
end
/* always @(posedge clk) begin
if (rst)
calib_bank_cnt <= #TCQ 3'd0;
else
calib_bank_cnt <= #TCQ bank_w;
end*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DIODE_FUNCTIONAL_PP_V
/**
* diode: Antenna tie-down diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_FUNCTIONAL_PP_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:27:00 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n5871, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_d_ff1_operation_out, FPMULT_FSM_selector_C,
FPMULT_FSM_selector_A, FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag,
FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_intAS, FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1483, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718,
n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758,
n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768,
n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778,
n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788,
n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798,
n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808,
n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818,
n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828,
n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838,
n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848,
n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858,
n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868,
n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878,
n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888,
n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898,
n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908,
n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918,
n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928,
n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938,
n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948,
n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958,
n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968,
n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978,
n1979, n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988,
n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998,
n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008,
n2009, n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018,
n2019, n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028,
n2029, n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038,
n2039, n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048,
n2049, n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058,
n2059, n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068,
n2069, n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078,
n2079, n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088,
n2089, n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098,
n2099, n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108,
n2109, n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118,
n2119, n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128,
n2129, n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138,
n2139, n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148,
n2149, n2151, n2193, DP_OP_26J208_123_9022_n18,
DP_OP_26J208_123_9022_n17, DP_OP_26J208_123_9022_n16,
DP_OP_26J208_123_9022_n15, DP_OP_26J208_123_9022_n14,
DP_OP_26J208_123_9022_n8, DP_OP_26J208_123_9022_n7,
DP_OP_26J208_123_9022_n6, DP_OP_26J208_123_9022_n5,
DP_OP_26J208_123_9022_n4, DP_OP_26J208_123_9022_n3,
DP_OP_26J208_123_9022_n2, DP_OP_26J208_123_9022_n1,
DP_OP_234J208_126_8543_n22, DP_OP_234J208_126_8543_n21,
DP_OP_234J208_126_8543_n20, DP_OP_234J208_126_8543_n19,
DP_OP_234J208_126_8543_n18, DP_OP_234J208_126_8543_n17,
DP_OP_234J208_126_8543_n16, DP_OP_234J208_126_8543_n15,
DP_OP_234J208_126_8543_n9, DP_OP_234J208_126_8543_n8,
DP_OP_234J208_126_8543_n7, DP_OP_234J208_126_8543_n6,
DP_OP_234J208_126_8543_n5, DP_OP_234J208_126_8543_n4,
DP_OP_234J208_126_8543_n3, DP_OP_234J208_126_8543_n2,
DP_OP_234J208_126_8543_n1, intadd_473_CI, intadd_473_SUM_2_,
intadd_473_SUM_1_, intadd_473_SUM_0_, intadd_473_n3, intadd_473_n2,
intadd_473_n1, intadd_474_CI, intadd_474_SUM_2_, intadd_474_SUM_1_,
intadd_474_SUM_0_, intadd_474_n3, intadd_474_n2, intadd_474_n1,
DP_OP_453J208_122_681_n2102, DP_OP_453J208_122_681_n2101,
DP_OP_453J208_122_681_n2082, DP_OP_453J208_122_681_n1812,
DP_OP_453J208_122_681_n1802, DP_OP_453J208_122_681_n1796,
DP_OP_453J208_122_681_n1766, DP_OP_453J208_122_681_n1764,
DP_OP_453J208_122_681_n1760, DP_OP_453J208_122_681_n1756,
DP_OP_453J208_122_681_n1748, DP_OP_453J208_122_681_n1722,
DP_OP_453J208_122_681_n1721, DP_OP_453J208_122_681_n1601,
DP_OP_453J208_122_681_n854, DP_OP_453J208_122_681_n853,
DP_OP_453J208_122_681_n851, DP_OP_453J208_122_681_n849,
DP_OP_453J208_122_681_n847, DP_OP_453J208_122_681_n846,
DP_OP_453J208_122_681_n845, DP_OP_453J208_122_681_n844,
DP_OP_453J208_122_681_n843, DP_OP_453J208_122_681_n842,
DP_OP_453J208_122_681_n841, DP_OP_453J208_122_681_n840,
DP_OP_453J208_122_681_n839, DP_OP_453J208_122_681_n838,
DP_OP_453J208_122_681_n837, DP_OP_453J208_122_681_n836,
DP_OP_453J208_122_681_n835, DP_OP_453J208_122_681_n834,
DP_OP_453J208_122_681_n833, DP_OP_453J208_122_681_n832,
DP_OP_453J208_122_681_n831, DP_OP_453J208_122_681_n830,
DP_OP_453J208_122_681_n829, DP_OP_453J208_122_681_n828,
DP_OP_453J208_122_681_n827, DP_OP_453J208_122_681_n826,
DP_OP_453J208_122_681_n825, DP_OP_453J208_122_681_n824,
DP_OP_453J208_122_681_n823, DP_OP_453J208_122_681_n822,
DP_OP_453J208_122_681_n821, DP_OP_453J208_122_681_n820,
DP_OP_453J208_122_681_n815, DP_OP_453J208_122_681_n583,
DP_OP_453J208_122_681_n582, DP_OP_453J208_122_681_n581,
DP_OP_453J208_122_681_n580, DP_OP_453J208_122_681_n579,
DP_OP_453J208_122_681_n578, DP_OP_453J208_122_681_n577,
DP_OP_453J208_122_681_n576, DP_OP_453J208_122_681_n575,
DP_OP_453J208_122_681_n574, DP_OP_453J208_122_681_n573,
DP_OP_453J208_122_681_n572, DP_OP_453J208_122_681_n571,
DP_OP_453J208_122_681_n570, DP_OP_453J208_122_681_n568,
DP_OP_453J208_122_681_n567, DP_OP_453J208_122_681_n566,
DP_OP_453J208_122_681_n565, DP_OP_453J208_122_681_n564,
DP_OP_453J208_122_681_n563, DP_OP_453J208_122_681_n562,
DP_OP_453J208_122_681_n561, DP_OP_453J208_122_681_n560,
DP_OP_453J208_122_681_n559, DP_OP_453J208_122_681_n558,
DP_OP_453J208_122_681_n557, DP_OP_453J208_122_681_n556,
DP_OP_453J208_122_681_n555, DP_OP_453J208_122_681_n554,
DP_OP_453J208_122_681_n551, DP_OP_453J208_122_681_n550,
DP_OP_453J208_122_681_n549, DP_OP_453J208_122_681_n548,
DP_OP_453J208_122_681_n547, DP_OP_453J208_122_681_n546,
DP_OP_453J208_122_681_n545, DP_OP_453J208_122_681_n544,
DP_OP_453J208_122_681_n543, DP_OP_453J208_122_681_n538,
DP_OP_453J208_122_681_n537, DP_OP_453J208_122_681_n536,
DP_OP_453J208_122_681_n534, DP_OP_453J208_122_681_n533,
DP_OP_453J208_122_681_n532, DP_OP_453J208_122_681_n531,
DP_OP_453J208_122_681_n530, DP_OP_453J208_122_681_n529,
DP_OP_453J208_122_681_n528, DP_OP_453J208_122_681_n527,
DP_OP_453J208_122_681_n526, DP_OP_453J208_122_681_n525,
DP_OP_453J208_122_681_n521, DP_OP_453J208_122_681_n520,
DP_OP_453J208_122_681_n519, DP_OP_453J208_122_681_n518,
DP_OP_453J208_122_681_n517, DP_OP_453J208_122_681_n515,
DP_OP_453J208_122_681_n514, DP_OP_453J208_122_681_n513,
DP_OP_453J208_122_681_n512, DP_OP_453J208_122_681_n508,
DP_OP_453J208_122_681_n507, DP_OP_453J208_122_681_n506,
DP_OP_453J208_122_681_n505, DP_OP_453J208_122_681_n504,
DP_OP_453J208_122_681_n503, DP_OP_453J208_122_681_n501,
DP_OP_453J208_122_681_n500, DP_OP_453J208_122_681_n499,
DP_OP_453J208_122_681_n498, DP_OP_453J208_122_681_n497,
DP_OP_453J208_122_681_n495, DP_OP_453J208_122_681_n494,
DP_OP_453J208_122_681_n493, DP_OP_453J208_122_681_n492,
DP_OP_453J208_122_681_n491, DP_OP_453J208_122_681_n488,
DP_OP_453J208_122_681_n487, DP_OP_453J208_122_681_n485,
DP_OP_453J208_122_681_n484, DP_OP_453J208_122_681_n483,
DP_OP_453J208_122_681_n480, DP_OP_453J208_122_681_n472,
DP_OP_453J208_122_681_n471, DP_OP_453J208_122_681_n470,
DP_OP_453J208_122_681_n469, DP_OP_453J208_122_681_n468,
DP_OP_453J208_122_681_n467, DP_OP_453J208_122_681_n466,
DP_OP_453J208_122_681_n465, DP_OP_453J208_122_681_n464,
DP_OP_453J208_122_681_n463, DP_OP_453J208_122_681_n462,
DP_OP_453J208_122_681_n461, DP_OP_453J208_122_681_n460,
DP_OP_453J208_122_681_n459, DP_OP_453J208_122_681_n458,
DP_OP_453J208_122_681_n457, DP_OP_453J208_122_681_n456,
DP_OP_453J208_122_681_n455, DP_OP_453J208_122_681_n454,
DP_OP_453J208_122_681_n453, DP_OP_453J208_122_681_n452,
DP_OP_453J208_122_681_n450, DP_OP_453J208_122_681_n448,
DP_OP_453J208_122_681_n447, DP_OP_453J208_122_681_n445,
DP_OP_453J208_122_681_n444, DP_OP_453J208_122_681_n443,
DP_OP_453J208_122_681_n441, DP_OP_453J208_122_681_n440,
DP_OP_453J208_122_681_n439, DP_OP_453J208_122_681_n438,
DP_OP_453J208_122_681_n437, DP_OP_453J208_122_681_n436,
DP_OP_453J208_122_681_n435, DP_OP_453J208_122_681_n434,
DP_OP_453J208_122_681_n433, DP_OP_453J208_122_681_n432,
DP_OP_453J208_122_681_n431, DP_OP_453J208_122_681_n430,
DP_OP_453J208_122_681_n429, DP_OP_453J208_122_681_n428,
DP_OP_453J208_122_681_n427, DP_OP_453J208_122_681_n426,
DP_OP_453J208_122_681_n425, DP_OP_453J208_122_681_n424,
DP_OP_453J208_122_681_n423, DP_OP_453J208_122_681_n422,
DP_OP_453J208_122_681_n421, DP_OP_453J208_122_681_n420,
DP_OP_453J208_122_681_n419, DP_OP_453J208_122_681_n418,
DP_OP_453J208_122_681_n417, DP_OP_453J208_122_681_n416,
DP_OP_453J208_122_681_n415, DP_OP_453J208_122_681_n414,
DP_OP_453J208_122_681_n412, DP_OP_453J208_122_681_n411,
DP_OP_453J208_122_681_n410, DP_OP_453J208_122_681_n409,
DP_OP_453J208_122_681_n408, DP_OP_453J208_122_681_n407,
DP_OP_453J208_122_681_n406, DP_OP_453J208_122_681_n405,
DP_OP_453J208_122_681_n404, DP_OP_453J208_122_681_n403,
DP_OP_453J208_122_681_n402, DP_OP_453J208_122_681_n401,
DP_OP_453J208_122_681_n400, DP_OP_453J208_122_681_n399,
DP_OP_453J208_122_681_n398, DP_OP_453J208_122_681_n397,
DP_OP_453J208_122_681_n396, DP_OP_453J208_122_681_n395,
DP_OP_453J208_122_681_n394, DP_OP_453J208_122_681_n392,
DP_OP_453J208_122_681_n391, DP_OP_453J208_122_681_n390,
DP_OP_453J208_122_681_n389, DP_OP_453J208_122_681_n388,
DP_OP_453J208_122_681_n387, DP_OP_453J208_122_681_n386,
DP_OP_453J208_122_681_n385, DP_OP_453J208_122_681_n384,
DP_OP_453J208_122_681_n383, DP_OP_453J208_122_681_n382,
DP_OP_453J208_122_681_n381, DP_OP_453J208_122_681_n380,
DP_OP_453J208_122_681_n379, DP_OP_453J208_122_681_n378,
DP_OP_453J208_122_681_n377, DP_OP_453J208_122_681_n376,
DP_OP_453J208_122_681_n375, DP_OP_453J208_122_681_n374,
DP_OP_453J208_122_681_n373, DP_OP_453J208_122_681_n371,
DP_OP_453J208_122_681_n370, DP_OP_453J208_122_681_n369,
DP_OP_453J208_122_681_n368, DP_OP_453J208_122_681_n367,
DP_OP_453J208_122_681_n366, DP_OP_453J208_122_681_n365,
DP_OP_453J208_122_681_n364, DP_OP_453J208_122_681_n363,
DP_OP_453J208_122_681_n362, DP_OP_453J208_122_681_n361,
DP_OP_453J208_122_681_n360, DP_OP_453J208_122_681_n359,
DP_OP_453J208_122_681_n358, DP_OP_453J208_122_681_n357,
DP_OP_453J208_122_681_n356, DP_OP_453J208_122_681_n355,
DP_OP_453J208_122_681_n354, DP_OP_453J208_122_681_n353,
DP_OP_453J208_122_681_n352, DP_OP_453J208_122_681_n351,
DP_OP_453J208_122_681_n350, DP_OP_453J208_122_681_n349,
DP_OP_453J208_122_681_n348, DP_OP_453J208_122_681_n347,
DP_OP_453J208_122_681_n346, DP_OP_453J208_122_681_n345,
DP_OP_453J208_122_681_n344, DP_OP_453J208_122_681_n343,
DP_OP_453J208_122_681_n342, DP_OP_453J208_122_681_n341,
DP_OP_453J208_122_681_n340, DP_OP_453J208_122_681_n339,
DP_OP_453J208_122_681_n338, DP_OP_453J208_122_681_n337,
DP_OP_453J208_122_681_n336, DP_OP_453J208_122_681_n335,
DP_OP_453J208_122_681_n334, DP_OP_453J208_122_681_n333,
DP_OP_453J208_122_681_n332, DP_OP_453J208_122_681_n331,
DP_OP_453J208_122_681_n330, DP_OP_453J208_122_681_n329,
DP_OP_453J208_122_681_n328, DP_OP_453J208_122_681_n327,
DP_OP_453J208_122_681_n326, DP_OP_453J208_122_681_n325,
DP_OP_453J208_122_681_n324, DP_OP_453J208_122_681_n323,
DP_OP_453J208_122_681_n322, DP_OP_453J208_122_681_n321,
DP_OP_453J208_122_681_n320, DP_OP_453J208_122_681_n319,
DP_OP_453J208_122_681_n318, DP_OP_453J208_122_681_n317,
DP_OP_453J208_122_681_n316, DP_OP_453J208_122_681_n315,
DP_OP_453J208_122_681_n314, DP_OP_453J208_122_681_n313,
DP_OP_453J208_122_681_n312, DP_OP_453J208_122_681_n311,
DP_OP_453J208_122_681_n310, DP_OP_453J208_122_681_n309,
DP_OP_453J208_122_681_n308, DP_OP_453J208_122_681_n307,
DP_OP_453J208_122_681_n306, DP_OP_453J208_122_681_n305,
DP_OP_453J208_122_681_n304, DP_OP_453J208_122_681_n303,
DP_OP_453J208_122_681_n302, DP_OP_453J208_122_681_n301,
DP_OP_453J208_122_681_n300, DP_OP_453J208_122_681_n299,
DP_OP_453J208_122_681_n298, DP_OP_453J208_122_681_n297,
DP_OP_453J208_122_681_n296, DP_OP_453J208_122_681_n295,
DP_OP_453J208_122_681_n294, DP_OP_453J208_122_681_n293,
DP_OP_453J208_122_681_n292, DP_OP_453J208_122_681_n291,
DP_OP_453J208_122_681_n290, DP_OP_453J208_122_681_n289,
DP_OP_453J208_122_681_n288, DP_OP_453J208_122_681_n287,
DP_OP_453J208_122_681_n286, DP_OP_453J208_122_681_n285,
DP_OP_453J208_122_681_n284, DP_OP_453J208_122_681_n283,
DP_OP_453J208_122_681_n282, DP_OP_453J208_122_681_n281,
DP_OP_453J208_122_681_n280, DP_OP_453J208_122_681_n279,
DP_OP_453J208_122_681_n278, DP_OP_453J208_122_681_n277,
DP_OP_453J208_122_681_n276, DP_OP_453J208_122_681_n275,
DP_OP_453J208_122_681_n274, DP_OP_453J208_122_681_n273,
DP_OP_453J208_122_681_n272, DP_OP_453J208_122_681_n271,
DP_OP_453J208_122_681_n270, DP_OP_453J208_122_681_n269,
DP_OP_453J208_122_681_n268, DP_OP_453J208_122_681_n267,
DP_OP_453J208_122_681_n266, DP_OP_453J208_122_681_n265,
DP_OP_453J208_122_681_n264, DP_OP_453J208_122_681_n263,
DP_OP_453J208_122_681_n262, DP_OP_453J208_122_681_n261,
DP_OP_453J208_122_681_n260, DP_OP_453J208_122_681_n259,
DP_OP_453J208_122_681_n258, DP_OP_453J208_122_681_n257,
DP_OP_453J208_122_681_n256, DP_OP_453J208_122_681_n255,
DP_OP_453J208_122_681_n254, DP_OP_453J208_122_681_n253,
DP_OP_453J208_122_681_n252, DP_OP_453J208_122_681_n251,
DP_OP_453J208_122_681_n250, DP_OP_453J208_122_681_n249,
DP_OP_453J208_122_681_n248, DP_OP_453J208_122_681_n247,
DP_OP_453J208_122_681_n246, DP_OP_453J208_122_681_n245,
DP_OP_453J208_122_681_n244, DP_OP_453J208_122_681_n243,
DP_OP_453J208_122_681_n242, DP_OP_453J208_122_681_n241,
DP_OP_453J208_122_681_n240, DP_OP_453J208_122_681_n239,
DP_OP_453J208_122_681_n238, DP_OP_453J208_122_681_n237,
DP_OP_453J208_122_681_n235, DP_OP_453J208_122_681_n234,
DP_OP_453J208_122_681_n233, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763,
n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773,
n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783,
n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793,
n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803,
n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813,
n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823,
n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833,
n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843,
n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853,
n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863,
n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873,
n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883,
n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893,
n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903,
n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913,
n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923,
n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933,
n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943,
n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953,
n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963,
n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973,
n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983,
n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993,
n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003,
n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013,
n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023,
n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033,
n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043,
n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053,
n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063,
n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073,
n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083,
n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103,
n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113,
n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123,
n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133,
n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143,
n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153,
n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163,
n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173,
n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183,
n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193,
n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203,
n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213,
n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223,
n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233,
n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243,
n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253,
n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263,
n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273,
n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283,
n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293,
n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303,
n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313,
n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323,
n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333,
n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343,
n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353,
n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363,
n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373,
n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383,
n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393,
n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403,
n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413,
n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423,
n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433,
n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443,
n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453,
n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463,
n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473,
n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483,
n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493,
n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503,
n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513,
n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523,
n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533,
n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543,
n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553,
n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563,
n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573,
n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583,
n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593,
n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603,
n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613,
n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623,
n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633,
n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643,
n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653,
n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663,
n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673,
n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683,
n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693,
n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703,
n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713,
n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723,
n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733,
n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743,
n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753,
n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763,
n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773,
n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783,
n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793,
n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803,
n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813,
n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823,
n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833,
n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843,
n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853,
n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863,
n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873,
n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883,
n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893,
n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903,
n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913,
n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923,
n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933,
n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943,
n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953,
n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963,
n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973,
n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983,
n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993,
n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003,
n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013,
n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023,
n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033,
n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4594, n4595, n4596,
n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606,
n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616,
n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626,
n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636,
n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646,
n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656,
n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666,
n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676,
n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686,
n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696,
n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706,
n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716,
n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726,
n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736,
n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746,
n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756,
n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766,
n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776,
n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, n4786,
n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796,
n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, n4806,
n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815, n4816,
n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825, n4826,
n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835, n4836,
n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845, n4846,
n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855, n4856,
n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865, n4866,
n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, n4876,
n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885, n4886,
n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895, n4896,
n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905, n4906,
n4907, n4908, n4909, n4910, n4911, n4912, n4914, n4915, n4916, n4917,
n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925, n4926, n4927,
n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935, n4937, n4938,
n4939, n4940, n4941, n4942, n4943, n4944, n4945, n4946, n4947, n4948,
n4949, n4950, n4951, n4952, n4953, n4954, n4955, n4956, n4957, n4958,
n4959, n4960, n4961, n4962, n4963, n4964, n4965, n4966, n4967, n4968,
n4969, n4970, n4971, n4972, n4973, n4974, n4975, n4976, n4977, n4978,
n4979, n4980, n4981, n4982, n4983, n4984, n4985, n4986, n4987, n4988,
n4989, n4990, n4991, n4992, n4993, n4994, n4995, n4996, n4997, n4998,
n4999, n5000, n5001, n5002, n5003, n5004, n5005, n5006, n5007, n5008,
n5009, n5010, n5011, n5012, n5013, n5014, n5015, n5016, n5017, n5018,
n5019, n5020, n5021, n5022, n5023, n5024, n5025, n5026, n5027, n5028,
n5029, n5030, n5031, n5032, n5033, n5034, n5035, n5036, n5037, n5038,
n5039, n5040, n5041, n5042, n5043, n5044, n5045, n5046, n5047, n5048,
n5049, n5050, n5051, n5052, n5053, n5054, n5055, n5056, n5057, n5058,
n5059, n5060, n5061, n5062, n5063, n5064, n5065, n5066, n5067, n5068,
n5069, n5070, n5071, n5072, n5073, n5074, n5075, n5076, n5077, n5078,
n5079, n5080, n5081, n5082, n5083, n5084, n5085, n5086, n5087, n5088,
n5089, n5090, n5091, n5092, n5093, n5094, n5095, n5096, n5097, n5098,
n5099, n5100, n5101, n5102, n5103, n5104, n5105, n5106, n5107, n5108,
n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116, n5117, n5118,
n5119, n5120, n5121, n5122, n5123, n5124, n5125, n5126, n5127, n5128,
n5129, n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5137, n5138,
n5139, n5140, n5141, n5142, n5143, n5144, n5145, n5146, n5147, n5148,
n5149, n5150, n5151, n5152, n5153, n5154, n5155, n5156, n5157, n5158,
n5159, n5160, n5161, n5162, n5163, n5164, n5165, n5166, n5167, n5168,
n5169, n5170, n5171, n5172, n5173, n5174, n5175, n5176, n5177, n5178,
n5179, n5180, n5181, n5182, n5183, n5184, n5185, n5186, n5187, n5188,
n5189, n5190, n5192, n5193, n5194, n5195, n5196, n5197, n5198, n5199,
n5200, n5201, n5202, n5203, n5204, n5205, n5206, n5207, n5208, n5209,
n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217, n5218, n5219,
n5220, n5221, n5222, n5223, n5224, n5225, n5226, n5227, n5228, n5229,
n5230, n5231, n5232, n5233, n5234, n5235, n5236, n5237, n5238, n5239,
n5240, n5241, n5242, n5243, n5244, n5245, n5246, n5247, n5248, n5249,
n5250, n5251, n5252, n5253, n5254, n5255, n5256, n5257, n5258, n5259,
n5260, n5261, n5262, n5263, n5264, n5265, n5266, n5267, n5268, n5269,
n5270, n5271, n5272, n5273, n5274, n5275, n5276, n5277, n5278, n5279,
n5280, n5281, n5282, n5283, n5284, n5285, n5286, n5287, n5288, n5289,
n5290, n5291, n5292, n5293, n5294, n5295, n5297, n5298, n5299, n5300,
n5301, n5302, n5303, n5304, n5305, n5306, n5307, n5308, n5309, n5310,
n5311, n5312, n5313, n5314, n5315, n5316, n5317, n5318, n5319, n5320,
n5321, n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329, n5330,
n5331, n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339, n5340,
n5341, n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350,
n5351, n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360,
n5361, n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370,
n5371, n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380,
n5381, n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390,
n5391, n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400,
n5401, n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410,
n5411, n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420,
n5421, n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430,
n5431, n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440,
n5441, n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450,
n5451, n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460,
n5461, n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470,
n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481,
n5482, n5484, n5485, n5486, n5487, n5489, n5490, n5491, n5492, n5493,
n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503,
n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513,
n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5523, n5524,
n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534,
n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544,
n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554,
n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564,
n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574,
n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584,
n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594,
n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604,
n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614,
n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624,
n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634,
n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644,
n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654,
n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664,
n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674,
n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684,
n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694,
n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704,
n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714,
n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724,
n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734,
n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744,
n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754,
n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764,
n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774,
n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784,
n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794,
n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804,
n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814,
n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824,
n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834,
n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844,
n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854,
n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5864, n5865,
n5866, n5867, n5868, n5869, n5870;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [30:3] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:1] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:1] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [20:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [6:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n5821), .Q(
dataA[25]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n5821), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n5821), .Q(
dataA[27]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n5821), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n5821), .Q(
dataB[23]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n5835), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n5818), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n5814), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n5835), .Q(
dataB[28]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n5818), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n5817), .Q(
dataB[31]) );
DFFRXLTS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n5862), .CK(clk), .RN(n5785), .Q(
ready_add_subt), .QN(n5586) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2141), .CK(clk), .RN(n5831),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n2446) );
DFFRXLTS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n5833), .QN(
n2231) );
DFFRXLTS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n5861), .CK(clk),
.RN(n5834), .QN(n2230) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2132), .CK(clk), .RN(n5820), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n5762) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2129), .CK(clk), .RN(n5820), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2127), .CK(clk), .RN(n5829), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2126), .CK(clk), .RN(n5833), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n5761) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2124), .CK(clk), .RN(n5820), .Q(
FPSENCOS_d_ff3_LUT_out[12]), .QN(n5757) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2123), .CK(clk), .RN(n5829), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2122), .CK(clk), .RN(n5834), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n5763) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2121), .CK(clk), .RN(n5832), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2120), .CK(clk), .RN(n5833), .Q(
FPSENCOS_d_ff3_LUT_out[21]), .QN(n5758) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2115), .CK(clk), .RN(n5820), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1854), .CK(clk), .RN(n5834),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1853), .CK(clk), .RN(n5833),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1852), .CK(clk), .RN(n5834),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1851), .CK(clk), .RN(n5831),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1850), .CK(clk), .RN(n5831),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1849), .CK(clk), .RN(n5833),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1848), .CK(clk), .RN(n5830),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1953), .CK(clk), .RN(n5820),
.Q(FPSENCOS_d_ff3_sh_x_out[23]), .QN(n5760) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1952), .CK(clk), .RN(n5829),
.Q(FPSENCOS_d_ff3_sh_x_out[24]), .QN(n5774) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1951), .CK(clk), .RN(n5820),
.Q(FPSENCOS_d_ff3_sh_x_out[25]), .QN(n5775) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1950), .CK(clk), .RN(n5832),
.Q(FPSENCOS_d_ff3_sh_x_out[26]), .QN(n5776) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1949), .CK(clk), .RN(n5832),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1948), .CK(clk), .RN(n5820),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1947), .CK(clk), .RN(n5834),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1946), .CK(clk), .RN(n5832),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2114), .CK(clk), .RN(n5817), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2113), .CK(clk), .RN(n5822), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2112), .CK(clk), .RN(n5819), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2111), .CK(clk), .RN(n5847), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2110), .CK(clk), .RN(n5846), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2109), .CK(clk), .RN(n5815), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2108), .CK(clk), .RN(n2314), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2107), .CK(clk), .RN(n5848), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2106), .CK(clk), .RN(n5845), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2105), .CK(clk), .RN(n5822), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2104), .CK(clk), .RN(n5815), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2103), .CK(clk), .RN(n2314), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2102), .CK(clk), .RN(n5848), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2101), .CK(clk), .RN(n5845), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2100), .CK(clk), .RN(n5822), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2099), .CK(clk), .RN(n5819), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2098), .CK(clk), .RN(n5847), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2097), .CK(clk), .RN(n5846), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2096), .CK(clk), .RN(n5815), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2095), .CK(clk), .RN(n2314), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2094), .CK(clk), .RN(n5848), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2093), .CK(clk), .RN(n5845), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2092), .CK(clk), .RN(n5819), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2091), .CK(clk), .RN(n5847), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2090), .CK(clk), .RN(n5846), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2089), .CK(clk), .RN(n5815), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2088), .CK(clk), .RN(n2314), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2087), .CK(clk), .RN(n5848), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2086), .CK(clk), .RN(n5845), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2085), .CK(clk), .RN(n5822), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2084), .CK(clk), .RN(n5819), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2083), .CK(clk), .RN(n5847), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1788), .CK(clk), .RN(n5846), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1743), .CK(clk), .RN(
n5847), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1787), .CK(clk), .RN(n5846), .QN(
n2216) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n5815), .QN(
n2283) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1785), .CK(clk), .RN(n5848), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1742), .CK(clk), .RN(
n5845), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n5822), .QN(
n2286) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1782), .CK(clk), .RN(n5841), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1741), .CK(clk), .RN(
n5844), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1781), .CK(clk), .RN(n5841), .QN(
n2281) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n5840), .QN(
n2214) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1779), .CK(clk), .RN(n5842), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1740), .CK(clk), .RN(
n5841), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n5839), .QN(
n2287) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1776), .CK(clk), .RN(n5842), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1739), .CK(clk), .RN(
n5841), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n5840), .QN(
n2288) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1773), .CK(clk), .RN(n5844), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1738), .CK(clk), .RN(
n5842), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1770), .CK(clk), .RN(n5840), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1737), .CK(clk), .RN(
n5842), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(n5840), .QN(
n2282) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n5842), .QN(
n2215) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1767), .CK(clk), .RN(n5839), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1736), .CK(clk), .RN(
n5844), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1732), .CK(clk), .RN(n5839), .QN(
n2217) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1731), .CK(clk), .RN(n5839), .QN(
n2284) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2010), .CK(clk), .RN(n5844), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1744), .CK(clk), .RN(
n5839), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1865), .CK(clk), .RN(
n5844), .Q(FPSENCOS_d_ff2_Y[22]), .QN(n5749) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1864), .CK(clk), .RN(n5843),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1963), .CK(clk), .RN(
n5823), .QN(n2276) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1962), .CK(clk), .RN(n5823),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2031), .CK(clk), .RN(n5843), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1751), .CK(clk), .RN(
n5844), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1879), .CK(clk), .RN(
n5843), .Q(FPSENCOS_d_ff2_Y[15]), .QN(n5742) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1878), .CK(clk), .RN(n5823),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1977), .CK(clk), .RN(
n5823), .QN(n2274) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1976), .CK(clk), .RN(n5839),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1794), .CK(clk), .RN(n5800),
.QN(n2249) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2022), .CK(clk), .RN(n5844), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1748), .CK(clk), .RN(
n5840), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1873), .CK(clk), .RN(
n5823), .Q(FPSENCOS_d_ff2_Y[18]), .QN(n5745) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1872), .CK(clk), .RN(n5841),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1971), .CK(clk), .RN(
n5843), .QN(n2275) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1970), .CK(clk), .RN(n5839),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2013), .CK(clk), .RN(n5823), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1745), .CK(clk), .RN(
n5839), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1867), .CK(clk), .RN(
n5841), .Q(FPSENCOS_d_ff2_Y[21]), .QN(n5748) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1866), .CK(clk), .RN(n5817),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1965), .CK(clk), .RN(
n5842), .QN(n2279) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1964), .CK(clk), .RN(n5824),
.Q(FPSENCOS_d_ff3_sh_x_out[21]), .QN(n5773) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2019), .CK(clk), .RN(n5828), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1747), .CK(clk), .RN(
n4038), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1871), .CK(clk), .RN(
n4038), .Q(FPSENCOS_d_ff2_Y[19]), .QN(n5746) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1870), .CK(clk), .RN(n4038),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1969), .CK(clk), .RN(
n4038), .QN(n2268) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1968), .CK(clk), .RN(n4038),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2016), .CK(clk), .RN(n5828), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1746), .CK(clk), .RN(
n5828), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1869), .CK(clk), .RN(
n5816), .Q(FPSENCOS_d_ff2_Y[20]), .QN(n5747) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1868), .CK(clk), .RN(n5826),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1967), .CK(clk), .RN(
n5824), .QN(n2269) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1966), .CK(clk), .RN(n5825),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2025), .CK(clk), .RN(n5818), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1749), .CK(clk), .RN(
n5814), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1875), .CK(clk), .RN(
n5834), .Q(FPSENCOS_d_ff2_Y[17]), .QN(n5744) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1874), .CK(clk), .RN(n5816),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1973), .CK(clk), .RN(
n5825), .QN(n2285) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1972), .CK(clk), .RN(n5821),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2064), .CK(clk), .RN(n5821), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1762), .CK(clk), .RN(
n5821), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1901), .CK(clk), .RN(
n5821), .Q(FPSENCOS_d_ff2_Y[4]), .QN(n5731) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1900), .CK(clk), .RN(n5817),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1998), .CK(clk), .RN(n5814),
.Q(FPSENCOS_d_ff3_sh_x_out[4]), .QN(n5767) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2058), .CK(clk), .RN(n5835), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1760), .CK(clk), .RN(
n5818), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1897), .CK(clk), .RN(
n5830), .Q(FPSENCOS_d_ff2_Y[6]), .QN(n5733) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1896), .CK(clk), .RN(n5829),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1995), .CK(clk), .RN(
n5829), .QN(n2271) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1994), .CK(clk), .RN(n5834),
.Q(FPSENCOS_d_ff3_sh_x_out[6]), .QN(n5768) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1803), .CK(clk), .RN(n5788), .QN(n2251) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2037), .CK(clk), .RN(n5834), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1753), .CK(clk), .RN(
n5829), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1883), .CK(clk), .RN(
n5832), .Q(FPSENCOS_d_ff2_Y[13]), .QN(n5740) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1882), .CK(clk), .RN(n5831),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1981), .CK(clk), .RN(
n5834), .QN(n2266) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1980), .CK(clk), .RN(n5819),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2028), .CK(clk), .RN(n5847), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1750), .CK(clk), .RN(
n5846), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1877), .CK(clk), .RN(
n5815), .Q(FPSENCOS_d_ff2_Y[16]), .QN(n5743) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1876), .CK(clk), .RN(n2314),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1975), .CK(clk), .RN(
n5848), .QN(n2267) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1974), .CK(clk), .RN(n5845),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1804), .CK(clk), .RN(n5812), .QN(n2245) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2052), .CK(clk), .RN(n5822), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1758), .CK(clk), .RN(
n5819), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1893), .CK(clk), .RN(
n5818), .Q(FPSENCOS_d_ff2_Y[8]), .QN(n5735) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1892), .CK(clk), .RN(n5814),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1990), .CK(clk), .RN(n5835),
.Q(FPSENCOS_d_ff3_sh_x_out[8]), .QN(n5769) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2043), .CK(clk), .RN(n5817), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1755), .CK(clk), .RN(
n5814), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1887), .CK(clk), .RN(
n5835), .Q(FPSENCOS_d_ff2_Y[11]), .QN(n5738) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1886), .CK(clk), .RN(n5818),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1984), .CK(clk), .RN(n5817),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1798), .CK(clk), .RN(n5808),
.QN(n2250) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2034), .CK(clk), .RN(n5814), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1752), .CK(clk), .RN(
n5835), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1881), .CK(clk), .RN(
n5818), .Q(FPSENCOS_d_ff2_Y[14]), .QN(n5741) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1880), .CK(clk), .RN(n5817),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1978), .CK(clk), .RN(n5814),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2046), .CK(clk), .RN(n5835), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1756), .CK(clk), .RN(
n5818), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1889), .CK(clk), .RN(
n5816), .Q(FPSENCOS_d_ff2_Y[10]), .QN(n5737) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1888), .CK(clk), .RN(n5816),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1987), .CK(clk), .RN(
n5816), .QN(n2272) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1986), .CK(clk), .RN(n5816),
.Q(FPSENCOS_d_ff3_sh_x_out[10]), .QN(n5771) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1800), .CK(clk), .RN(n5807), .QN(n2246) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2040), .CK(clk), .RN(n5816), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1754), .CK(clk), .RN(
n5816), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1885), .CK(clk), .RN(
n5816), .Q(FPSENCOS_d_ff2_Y[12]), .QN(n5739) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1884), .CK(clk), .RN(n5816),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1983), .CK(clk), .RN(
n5845), .QN(n2273) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1982), .CK(clk), .RN(n5819),
.Q(FPSENCOS_d_ff3_sh_x_out[12]), .QN(n5772) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1911), .CK(clk), .RN(n5847), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1734), .CK(clk), .RN(n2314), .QN(
n2256) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1847), .CK(clk), .RN(
n5846), .Q(FPSENCOS_d_ff2_Y[31]), .QN(n2503) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1846), .CK(clk), .RN(n5815),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n5848), .Q(
FPSENCOS_d_ff_Xn[31]), .QN(n5725) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1945), .CK(clk), .RN(
n5845), .QN(n2280) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1944), .CK(clk), .RN(n5822),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2067), .CK(clk), .RN(n5819), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1763), .CK(clk), .RN(
n5814), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1903), .CK(clk), .RN(
n5835), .Q(FPSENCOS_d_ff2_Y[3]), .QN(n5730) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1902), .CK(clk), .RN(n5818),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n2000), .CK(clk), .RN(n5817),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n5814),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2070), .CK(clk), .RN(n5835), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1764), .CK(clk), .RN(
n5818), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1905), .CK(clk), .RN(
n5817), .Q(FPSENCOS_d_ff2_Y[2]), .QN(n5729) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1904), .CK(clk), .RN(n5833),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2003), .CK(clk), .RN(
n5829), .QN(n2270) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2002), .CK(clk), .RN(n5830),
.Q(FPSENCOS_d_ff3_sh_x_out[2]), .QN(n5766) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n5830),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2055), .CK(clk), .RN(n5832), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1759), .CK(clk), .RN(
n5833), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1895), .CK(clk), .RN(
n5831), .Q(FPSENCOS_d_ff2_Y[7]), .QN(n5734) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1894), .CK(clk), .RN(n5820),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1993), .CK(clk), .RN(
n5834), .QN(n2265) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1992), .CK(clk), .RN(n5833),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2076), .CK(clk), .RN(n5834), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1766), .CK(clk), .RN(
n5829), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1909), .CK(clk), .RN(
n5832), .Q(FPSENCOS_d_ff2_Y[0]), .QN(n5727) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1908), .CK(clk), .RN(n5830),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2007), .CK(clk), .RN(
n5829), .QN(n2277) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2006), .CK(clk), .RN(n5820),
.Q(FPSENCOS_d_ff3_sh_x_out[0]), .QN(n5764) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n5828),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2073), .CK(clk), .RN(n5828), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1765), .CK(clk), .RN(
n5828), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1907), .CK(clk), .RN(
n5828), .Q(FPSENCOS_d_ff2_Y[1]), .QN(n5728) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1906), .CK(clk), .RN(n5828),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2005), .CK(clk), .RN(
n5828), .QN(n2213) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2004), .CK(clk), .RN(n5828),
.Q(FPSENCOS_d_ff3_sh_x_out[1]), .QN(n5765) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n5828),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2049), .CK(clk), .RN(n5828), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1757), .CK(clk), .RN(
n5828), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1891), .CK(clk), .RN(
n5827), .Q(FPSENCOS_d_ff2_Y[9]), .QN(n5736) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1890), .CK(clk), .RN(n5827),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1989), .CK(clk), .RN(
n5827), .QN(n2278) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1988), .CK(clk), .RN(n5827),
.Q(FPSENCOS_d_ff3_sh_x_out[9]), .QN(n5770) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2061), .CK(clk), .RN(n5827), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1761), .CK(clk), .RN(
n5827), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1899), .CK(clk), .RN(
n5827), .Q(FPSENCOS_d_ff2_Y[5]), .QN(n5732) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1898), .CK(clk), .RN(n5827),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1997), .CK(clk), .RN(
n5826), .QN(n2264) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1996), .CK(clk), .RN(n5826),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n5826),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n5825),
.Q(cordic_result[4]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1696), .CK(clk),
.RN(n4037), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1689), .CK(clk),
.RN(n5859), .QN(n2248) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1687), .CK(clk),
.RN(n4037), .QN(n2209) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1685), .CK(clk),
.RN(n4037), .QN(n2238) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1684), .CK(clk),
.RN(n4037), .QN(n2207) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1682), .CK(clk),
.RN(n4037), .QN(n2201) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1676), .CK(clk),
.RN(n5857), .Q(FPMULT_Op_MX[17]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1675), .CK(clk),
.RN(n5860), .Q(FPMULT_Op_MX[16]), .QN(n2496) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1674), .CK(clk),
.RN(n5860), .Q(FPMULT_Op_MX[15]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1673), .CK(clk),
.RN(n5850), .Q(FPMULT_Op_MX[14]), .QN(n2478) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1672), .CK(clk),
.RN(n5860), .Q(FPMULT_Op_MX[13]), .QN(n2475) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1669), .CK(clk),
.RN(n5860), .Q(FPMULT_Op_MX[10]), .QN(n2447) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1668), .CK(clk),
.RN(n5850), .Q(FPMULT_Op_MX[9]), .QN(n2486) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1667), .CK(clk),
.RN(n5860), .Q(FPMULT_Op_MX[8]), .QN(n2487) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1666), .CK(clk),
.RN(n5850), .Q(FPMULT_Op_MX[7]), .QN(n2489) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1665), .CK(clk),
.RN(n5860), .Q(FPMULT_Op_MX[6]), .QN(n2455) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1664), .CK(clk),
.RN(n5850), .Q(FPMULT_Op_MX[5]), .QN(n2463) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1663), .CK(clk),
.RN(n5857), .Q(FPMULT_Op_MX[4]), .QN(n2464) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1662), .CK(clk),
.RN(n5859), .Q(FPMULT_Op_MX[3]), .QN(n2481) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1661), .CK(clk),
.RN(n5857), .Q(FPMULT_Op_MX[2]), .QN(n2491) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1660), .CK(clk),
.RN(n5854), .Q(FPMULT_Op_MX[1]), .QN(n2495) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1659), .CK(clk),
.RN(n5859), .Q(FPMULT_Op_MX[0]), .QN(n2460) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1658), .CK(clk),
.RN(n5857), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1608), .CK(clk),
.RN(n5852), .QN(n2261) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1609), .CK(clk),
.RN(n5858), .QN(n2255) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1610), .CK(clk),
.RN(n5852), .QN(n2260) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1611), .CK(clk),
.RN(n5858), .QN(n2254) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1612), .CK(clk),
.RN(n5852), .QN(n2259) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1613), .CK(clk),
.RN(n5858), .QN(n2253) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1614), .CK(clk),
.RN(n5852), .QN(n2258) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1615), .CK(clk), .RN(
n5858), .QN(n2257) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1616), .CK(clk), .RN(
n5852), .QN(n2289) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1618), .CK(clk), .RN(
n5858), .QN(n2262) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1620), .CK(clk), .RN(
n5858), .QN(n2263) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1623), .CK(clk), .RN(
n5859), .QN(n2212) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1624), .CK(clk), .RN(
n5857), .Q(FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1601), .CK(clk),
.RN(n5849), .Q(FPMULT_Add_result[23]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1657), .CK(clk),
.RN(n5859), .QN(n2210) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1656), .CK(clk),
.RN(n5857), .QN(n2243) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1655), .CK(clk),
.RN(n5857), .QN(n2202) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1653), .CK(clk),
.RN(n5859), .QN(n2208) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1652), .CK(clk),
.RN(n5856), .QN(n2233) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1639), .CK(clk),
.RN(n5855), .Q(FPMULT_Op_MY[12]), .QN(n2224) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n1584), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[31]), .QN(n2516) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1575), .CK(clk),
.RN(n5840), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1563), .CK(clk),
.RN(n5843), .Q(FPMULT_P_Sgf[10]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1559), .CK(clk),
.RN(n5844), .Q(FPMULT_P_Sgf[6]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1557), .CK(clk),
.RN(n5843), .Q(FPMULT_P_Sgf[4]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1554), .CK(clk),
.RN(n5844), .Q(FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1553), .CK(clk),
.RN(n5843), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Sel_B_Q_reg_0_ ( .D(n1551), .CK(clk), .RN(n5854), .Q(
FPMULT_FSM_selector_B[0]), .QN(n5633) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1548), .CK(clk), .RN(
n5854), .QN(n2234) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1545), .CK(clk), .RN(
n5855), .QN(n2239) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1543), .CK(clk), .RN(
n5855), .QN(n2244) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1519), .CK(
clk), .RN(n5851), .QN(n2226) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1518), .CK(
clk), .RN(n5855), .QN(n2204) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1515), .CK(clk), .RN(n5851), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1514), .CK(clk), .RN(n5855), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1513), .CK(clk), .RN(n5851), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1512), .CK(clk), .RN(n5855), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1511), .CK(clk), .RN(n5851), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1510), .CK(clk), .RN(n5855), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1509), .CK(clk), .RN(n5851), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1508), .CK(clk), .RN(n5855), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1507), .CK(clk), .RN(n5850), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1506), .CK(clk), .RN(n5860), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1505), .CK(clk), .RN(n5850), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1504), .CK(clk), .RN(n5860), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1503), .CK(clk), .RN(n5850), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1502), .CK(clk), .RN(n5860), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1501), .CK(clk), .RN(n5850), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1500), .CK(clk), .RN(n5860), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1499), .CK(clk), .RN(n5850), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1498), .CK(clk), .RN(n5860), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1497), .CK(clk), .RN(n5850), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1496), .CK(clk), .RN(n5860), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1495), .CK(clk), .RN(n5849), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1494), .CK(clk), .RN(n5849), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1493), .CK(clk), .RN(n5849), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1492), .CK(clk), .RN(n5849), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1491), .CK(clk), .RN(n5849), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1490), .CK(clk), .RN(n5849), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1489), .CK(clk), .RN(n5849), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1488), .CK(clk), .RN(n5849), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1487), .CK(clk), .RN(n5849), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1486), .CK(clk), .RN(n5849), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1485), .CK(clk), .RN(n5849), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1483), .CK(clk), .RN(n5849), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1480), .CK(clk), .RN(
n4039), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1479), .CK(clk), .RN(
n5785), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1478), .CK(clk), .RN(
n5797), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1477), .CK(clk), .RN(
n2316), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1476), .CK(clk), .RN(
n5791), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1463), .CK(clk), .RN(n5789),
.QN(n2252) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1462), .CK(clk), .RN(n5809),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1461), .CK(clk), .RN(n5808),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1460), .CK(clk), .RN(n5807),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1459), .CK(clk), .RN(n5805),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1458), .CK(clk), .RN(n5804),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n5805),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1456), .CK(clk), .RN(
n5812), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1454), .CK(clk), .RN(n5789),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1453), .CK(clk), .RN(n5790),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n5790),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1451), .CK(clk), .RN(
n5792), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1449), .CK(clk), .RN(n5787),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1448), .CK(clk), .RN(n4039),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n5790),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1446), .CK(clk), .RN(
n5811), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1444), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n5809),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1441), .CK(clk), .RN(
n5788), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n4039),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n5802),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n5792),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1436), .CK(clk), .RN(
n5812), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1434), .CK(clk), .RN(n5811),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n5788),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n5812),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1431), .CK(clk), .RN(
n5792), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1429), .CK(clk), .RN(n5784),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1428), .CK(clk), .RN(n5785),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n5813),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1426), .CK(clk), .RN(
n5811), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1424), .CK(clk), .RN(n5810),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n5792),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n5811),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1421), .CK(clk), .RN(
n5812), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1414), .CK(clk), .RN(n5787), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1413), .CK(clk), .RN(n5785), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1411), .CK(clk), .RN(
n5810), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1409), .CK(clk), .RN(n5796),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n5793), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1406), .CK(clk), .RN(n5797),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n5795), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1403), .CK(clk), .RN(n2315),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n5794), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1400), .CK(clk), .RN(n4045),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n5787), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1397), .CK(clk), .RN(n5796),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n5793), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1394), .CK(clk), .RN(n5797),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n5795), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1391), .CK(clk), .RN(n5796),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n5793), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1388), .CK(clk), .RN(n5797),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n5795), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1385), .CK(clk), .RN(n2315),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n5794), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1382), .CK(clk), .RN(n5796),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n5793), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1379), .CK(clk), .RN(n5796),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n2315), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1376), .CK(clk), .RN(n5794),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n5793), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1373), .CK(clk), .RN(n5797),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n5795), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1370), .CK(clk), .RN(n4045),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n5787), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1367), .CK(clk), .RN(n5797),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n5795), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1364), .CK(clk), .RN(n4045),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n5787), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n2315), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n5794),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1360), .CK(clk), .RN(n5796),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1359), .CK(clk), .RN(
n5784), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n5793),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n5797), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n5795), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n2315),
.Q(FPADDSUB_OP_FLAG_SFG), .QN(n5712) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1332), .CK(clk), .RN(
n5788), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1330), .CK(clk), .RN(n5786),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n5801), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n5786),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(n5786),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n5798),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1324), .CK(clk), .RN(
n5811), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1320), .CK(clk), .RN(
n5792), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1316), .CK(clk), .RN(
n5810), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1314), .CK(clk), .RN(n5786),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n5801), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n5801),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(n5798),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n5801),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1307), .CK(clk), .RN(n5801),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n5799), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n5800),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n5798),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n5798),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1300), .CK(clk), .RN(n5799),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n5800), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n5800),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n5798),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n5799),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1293), .CK(clk), .RN(n5800),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n5799), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n5803),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(n5798),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n5799),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1286), .CK(clk), .RN(n5800),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n5798), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n5803),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(n5803),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n5802),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1279), .CK(clk), .RN(n5802),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n5803), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n5799),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(n5802),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n5786),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1273), .CK(clk), .RN(n5800),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1272), .CK(clk), .RN(
n5802), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n5801),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(n5799),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n5786),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1267), .CK(clk), .RN(n5786),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1266), .CK(clk), .RN(n5801),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1263), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1262), .CK(clk), .RN(n2316),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n5805),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1259), .CK(clk), .RN(n5804),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1255), .CK(clk), .RN(n5789),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1254), .CK(clk), .RN(n5809),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n5808),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1251), .CK(clk), .RN(n5807),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1250), .CK(clk), .RN(n2316),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n5805),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1247), .CK(clk), .RN(n5804),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1246), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1243), .CK(clk), .RN(n5789),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1242), .CK(clk), .RN(n5809),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n5789),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1239), .CK(clk), .RN(n5809),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1238), .CK(clk), .RN(n5804),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1235), .CK(clk), .RN(n5808),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1234), .CK(clk), .RN(n5807),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1231), .CK(clk), .RN(n2316),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1230), .CK(clk), .RN(n5805),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1227), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1226), .CK(clk), .RN(n5789),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n5809),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1223), .CK(clk), .RN(n5808),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1222), .CK(clk), .RN(n5807),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n5805),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1219), .CK(clk), .RN(n5804),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1218), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n5808),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1215), .CK(clk), .RN(n5807),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1214), .CK(clk), .RN(n5805),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n5804),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1211), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1210), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n2316),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1203), .CK(clk), .RN(
n5806), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n2221) );
CMPR32X2TS DP_OP_234J208_126_8543_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n4031), .C(DP_OP_234J208_126_8543_n22), .CO(DP_OP_234J208_126_8543_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J208_126_8543_U9 ( .A(DP_OP_234J208_126_8543_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J208_126_8543_n9), .CO(
DP_OP_234J208_126_8543_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J208_126_8543_U8 ( .A(DP_OP_234J208_126_8543_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J208_126_8543_n8), .CO(
DP_OP_234J208_126_8543_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J208_126_8543_U7 ( .A(DP_OP_234J208_126_8543_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J208_126_8543_n7), .CO(
DP_OP_234J208_126_8543_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J208_126_8543_U6 ( .A(DP_OP_234J208_126_8543_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J208_126_8543_n6), .CO(
DP_OP_234J208_126_8543_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J208_126_8543_U5 ( .A(DP_OP_234J208_126_8543_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J208_126_8543_n5), .CO(
DP_OP_234J208_126_8543_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J208_126_8543_U4 ( .A(DP_OP_234J208_126_8543_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J208_126_8543_n4), .CO(
DP_OP_234J208_126_8543_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J208_126_8543_U3 ( .A(DP_OP_234J208_126_8543_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J208_126_8543_n3), .CO(
DP_OP_234J208_126_8543_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_234J208_126_8543_U2 ( .A(n4031), .B(FPMULT_S_Oper_A_exp[8]),
.C(DP_OP_234J208_126_8543_n2), .CO(DP_OP_234J208_126_8543_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
CMPR32X2TS intadd_473_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n5623), .C(
intadd_473_CI), .CO(intadd_473_n3), .S(intadd_473_SUM_0_) );
CMPR32X2TS intadd_473_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n4915), .C(
intadd_473_n3), .CO(intadd_473_n2), .S(intadd_473_SUM_1_) );
DFFRX1TS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1626), .CK(
clk), .RN(n5859), .Q(FPMULT_zero_flag), .QN(n5759) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n1582), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[29]), .QN(n5756) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n1583), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[30]), .QN(n5755) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1577), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[24]), .QN(n5754) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n1578), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[25]), .QN(n5753) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n1579), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[26]), .QN(n5752) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n1580), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[27]), .QN(n5751) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n1581), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[28]), .QN(n5750) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1622), .CK(clk), .RN(
n5859), .Q(FPMULT_Add_result[2]), .QN(n5723) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1860), .CK(clk), .RN(
n5823), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n5722) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1861), .CK(clk), .RN(
n5843), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n5721) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1862), .CK(clk), .RN(
n5847), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n5720) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1516), .CK(clk), .RN(
n5851), .Q(underflow_flag_mult), .QN(n5719) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1856), .CK(clk), .RN(
n5844), .Q(FPSENCOS_d_ff2_Y[30]), .QN(n5717) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1859), .CK(clk), .RN(
n5842), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n5716) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1857), .CK(clk), .RN(
n5823), .Q(FPSENCOS_d_ff2_Y[29]), .QN(n5715) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1182), .CK(clk), .RN(
n5813), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n5714) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(n5848), .Q(
FPSENCOS_d_ff_Yn[31]), .QN(n5713) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1956), .CK(clk), .RN(
n5844), .Q(FPSENCOS_d_ff2_X[28]), .QN(n5710) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1820), .CK(clk), .RN(
n5792), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n5708) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1819), .CK(clk), .RN(
n5811), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n5707) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1539), .CK(
clk), .RN(n5853), .Q(FPMULT_Sgf_normalized_result[22]), .QN(n5706) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n5804),
.Q(FPADDSUB_DMP_SFG[22]), .QN(n5704) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2137), .CK(clk), .RN(n5834),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n5703) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1467), .CK(clk), .RN(n5789),
.Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n5702) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1537), .CK(
clk), .RN(n5853), .Q(FPMULT_Sgf_normalized_result[20]), .QN(n5701) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1809), .CK(clk), .RN(n5797), .Q(FPADDSUB_Data_array_SWR[15]), .QN(n5700) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1810), .CK(clk), .RN(n5802), .Q(FPADDSUB_Data_array_SWR[16]), .QN(n5699) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1351), .CK(clk), .RN(
n5796), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]), .QN(n5697) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1913), .CK(clk), .RN(
n5785), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n5695) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1812), .CK(clk), .RN(n5790), .Q(FPADDSUB_Data_array_SWR[18]), .QN(n5694) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1811), .CK(clk), .RN(n4045), .Q(FPADDSUB_Data_array_SWR[17]), .QN(n5693) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_SFG[21]), .QN(n5692) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1185), .CK(clk), .RN(
n5785), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n5691) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1943), .CK(clk), .RN(
n5808), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n5690) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1535), .CK(
clk), .RN(n5853), .Q(FPMULT_Sgf_normalized_result[18]), .QN(n5687) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n5804),
.Q(FPADDSUB_DMP_SFG[19]), .QN(n5685) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1928), .CK(clk), .RN(
n5799), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n5684) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1922), .CK(clk), .RN(
n5793), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n5683) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1930), .CK(clk), .RN(
n5788), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n5682) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1926), .CK(clk), .RN(
n5795), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n5681) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1932), .CK(clk), .RN(
n5789), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n5680) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1934), .CK(clk), .RN(
n5807), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n5679) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1942), .CK(clk), .RN(
n5793), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n5678) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1916), .CK(clk), .RN(
n5788), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n5677) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1187), .CK(clk), .RN(
n5784), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n5676) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1924), .CK(clk), .RN(
n5795), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n5673) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1941), .CK(clk), .RN(
n5801), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n5672) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1935), .CK(clk), .RN(
n5809), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n5671) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1472), .CK(clk), .RN(
n5784), .Q(result_add_subt[26]), .QN(n5670) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1474), .CK(clk), .RN(
n5785), .Q(result_add_subt[24]), .QN(n5669) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1471), .CK(clk), .RN(
n5813), .Q(result_add_subt[27]), .QN(n5668) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1470), .CK(clk), .RN(
n5810), .Q(result_add_subt[28]), .QN(n5667) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1280), .CK(clk), .RN(
n5798), .Q(result_add_subt[5]), .QN(n5666) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1287), .CK(clk), .RN(
n5799), .Q(result_add_subt[9]), .QN(n5665) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1294), .CK(clk), .RN(
n5798), .Q(result_add_subt[1]), .QN(n5664) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1301), .CK(clk), .RN(
n5801), .Q(result_add_subt[0]), .QN(n5663) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1308), .CK(clk), .RN(
n5800), .Q(result_add_subt[7]), .QN(n5662) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1315), .CK(clk), .RN(
n5801), .Q(result_add_subt[2]), .QN(n5661) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1331), .CK(clk), .RN(
n5786), .Q(result_add_subt[3]), .QN(n5660) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1365), .CK(clk), .RN(
n5793), .Q(result_add_subt[12]), .QN(n5659) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1368), .CK(clk), .RN(
n5796), .Q(result_add_subt[10]), .QN(n5658) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1371), .CK(clk), .RN(
n5797), .Q(result_add_subt[14]), .QN(n5657) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1374), .CK(clk), .RN(
n5793), .Q(result_add_subt[11]), .QN(n5656) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1377), .CK(clk), .RN(
n5794), .Q(result_add_subt[8]), .QN(n5655) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1380), .CK(clk), .RN(
n5796), .Q(result_add_subt[16]), .QN(n5654) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1383), .CK(clk), .RN(
n5787), .Q(result_add_subt[13]), .QN(n5653) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(
n4045), .Q(result_add_subt[6]), .QN(n5652) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(
n5795), .Q(result_add_subt[4]), .QN(n5651) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1392), .CK(clk), .RN(
n5793), .Q(result_add_subt[17]), .QN(n5650) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1395), .CK(clk), .RN(
n5795), .Q(result_add_subt[20]), .QN(n5649) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1398), .CK(clk), .RN(
n5797), .Q(result_add_subt[19]), .QN(n5648) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1401), .CK(clk), .RN(
n2315), .Q(result_add_subt[21]), .QN(n5647) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1404), .CK(clk), .RN(
n2315), .Q(result_add_subt[18]), .QN(n5646) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1407), .CK(clk), .RN(
n5795), .Q(result_add_subt[15]), .QN(n5645) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1410), .CK(clk), .RN(
n5794), .Q(result_add_subt[22]), .QN(n5644) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2079), .CK(clk), .RN(
n5786), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n5643) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2081), .CK(clk), .RN(
n5803), .Q(FPADDSUB_bit_shift_SHT2), .QN(n5641) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n2316),
.Q(FPADDSUB_DMP_SFG[17]), .QN(n5640) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1189), .CK(clk), .RN(
n5811), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n5639) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1533), .CK(
clk), .RN(n5853), .Q(FPMULT_Sgf_normalized_result[16]), .QN(n5638) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1337), .CK(clk), .RN(
n5801), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n5636) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(
n5792), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n5635) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_SFG[15]), .QN(n5634) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1816), .CK(clk), .RN(
n5812), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n5632) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1531), .CK(
clk), .RN(n5852), .Q(FPMULT_Sgf_normalized_result[14]), .QN(n5629) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n5829), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n5628) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1322), .CK(clk), .RN(
n5798), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n5626) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1333), .CK(clk), .RN(
n5803), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n5625) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1193), .CK(clk), .RN(
n5812), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n5624) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_SFG[13]), .QN(n5614) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1529), .CK(
clk), .RN(n5858), .Q(FPMULT_Sgf_normalized_result[12]), .QN(n5613) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2193), .CK(
clk), .RN(n5812), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n5612) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1195), .CK(clk), .RN(
n5791), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n5608) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n5805),
.Q(FPADDSUB_DMP_SFG[11]), .QN(n5607) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n5786),
.Q(FPADDSUB_DMP_SFG[9]), .QN(n5606) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1527), .CK(
clk), .RN(n5852), .Q(FPMULT_Sgf_normalized_result[10]), .QN(n5605) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1197), .CK(clk), .RN(
n5806), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n5604) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1198), .CK(clk), .RN(
n5789), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n5603) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1525), .CK(
clk), .RN(n5858), .Q(FPMULT_Sgf_normalized_result[8]), .QN(n5602) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1523), .CK(
clk), .RN(n5852), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n5601) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1199), .CK(clk), .RN(
n5809), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n5600) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1200), .CK(clk), .RN(
n5808), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n5599) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1521), .CK(
clk), .RN(n5858), .Q(FPMULT_Sgf_normalized_result[4]), .QN(n5598) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1336), .CK(clk), .RN(
n5799), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n5597) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1201), .CK(clk), .RN(
n5805), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n5594) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1202), .CK(clk), .RN(
n5807), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n5593) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n5798),
.Q(FPADDSUB_DMP_SFG[0]), .QN(n5592) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1417), .CK(clk), .RN(n5787),
.Q(FPADDSUB_DmP_EXP_EWSW[25]), .QN(n5591) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1464), .CK(clk), .RN(n5808),
.Q(FPADDSUB_DMP_EXP_EWSW[26]), .QN(n5590) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1416), .CK(clk), .RN(n4045),
.Q(FPADDSUB_DmP_EXP_EWSW[26]), .QN(n5588) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1541), .CK(clk), .RN(
n5853), .Q(FPMULT_exp_oper_result[8]), .QN(n5587) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1338), .CK(clk), .RN(
n5801), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n5585) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1341), .CK(clk), .RN(
n5802), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n5584) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1465), .CK(clk), .RN(n5807),
.Q(FPADDSUB_DMP_EXP_EWSW[25]), .QN(n5583) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2136), .CK(clk), .RN(n5831),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n5582) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1813), .CK(clk), .RN(n4045), .Q(FPADDSUB_Data_array_SWR[19]), .QN(n5581) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1814), .CK(clk), .RN(n5804), .Q(FPADDSUB_Data_array_SWR[20]), .QN(n5580) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1914), .CK(clk), .RN(
n5813), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n5578) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1921), .CK(clk), .RN(
n5798), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n5577) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1925), .CK(clk), .RN(
n5803), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n5576) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1929), .CK(clk), .RN(
n5791), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n5575) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1931), .CK(clk), .RN(
n5790), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n5574) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1940), .CK(clk), .RN(
n5805), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n5571) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1923), .CK(clk), .RN(
n4045), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n5570) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1863), .CK(clk), .RN(
n2314), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n5567) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1358), .CK(clk), .RN(
n5797), .Q(result_add_subt[31]), .QN(n5566) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1344), .CK(clk), .RN(
n5793), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n5564) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n5829), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .QN(n5563) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1339), .CK(clk), .RN(
n5786), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n5562) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1815), .CK(clk), .RN(
n5803), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n5561) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1321), .CK(clk), .RN(
n5786), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n5560) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1350), .CK(clk), .RN(
n5787), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n5558) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n5829), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n5557) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1192), .CK(clk), .RN(
n5788), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n5556) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1346), .CK(clk), .RN(
n5795), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n5555) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1196), .CK(clk), .RN(
n5804), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n5548) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1342), .CK(clk), .RN(
n5794), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n5547) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n5800),
.Q(FPADDSUB_DMP_SFG[7]), .QN(n5545) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n5800),
.Q(FPADDSUB_DMP_SFG[5]), .QN(n5544) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1334), .CK(clk), .RN(
n5801), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]), .QN(n5543) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2149), .CK(clk), .RN(
n5788), .Q(n2211), .QN(n5711) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1466), .CK(clk), .RN(n5809),
.Q(FPADDSUB_DMP_EXP_EWSW[24]), .QN(n5540) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1418), .CK(clk), .RN(n5792),
.Q(FPADDSUB_DmP_EXP_EWSW[24]), .QN(n5539) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1340), .CK(clk), .RN(
n5786), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n5538) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1918), .CK(clk), .RN(
n5792), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n5537) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1917), .CK(clk), .RN(
n5810), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n5536) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1345), .CK(clk), .RN(
n5797), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n5534) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(
n5796), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n5531) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1919), .CK(clk), .RN(
n5811), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n5527) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n5814), .Q(NaN_flag)
);
CMPR42X2TS DP_OP_453J208_122_681_U330 ( .A(DP_OP_453J208_122_681_n480), .B(
DP_OP_453J208_122_681_n443), .C(DP_OP_453J208_122_681_n582), .D(
DP_OP_453J208_122_681_n440), .ICI(DP_OP_453J208_122_681_n472), .S(
DP_OP_453J208_122_681_n438), .ICO(DP_OP_453J208_122_681_n436), .CO(
DP_OP_453J208_122_681_n437) );
CMPR42X2TS DP_OP_453J208_122_681_U325 ( .A(DP_OP_453J208_122_681_n567), .B(
DP_OP_453J208_122_681_n434), .C(DP_OP_453J208_122_681_n430), .D(
DP_OP_453J208_122_681_n470), .ICI(DP_OP_453J208_122_681_n427), .S(
DP_OP_453J208_122_681_n424), .ICO(DP_OP_453J208_122_681_n422), .CO(
DP_OP_453J208_122_681_n423) );
CMPR42X2TS DP_OP_453J208_122_681_U322 ( .A(DP_OP_453J208_122_681_n421), .B(
DP_OP_453J208_122_681_n426), .C(DP_OP_453J208_122_681_n469), .D(
DP_OP_453J208_122_681_n422), .ICI(DP_OP_453J208_122_681_n419), .S(
DP_OP_453J208_122_681_n416), .ICO(DP_OP_453J208_122_681_n414), .CO(
DP_OP_453J208_122_681_n415) );
CMPR42X2TS DP_OP_453J208_122_681_U319 ( .A(DP_OP_453J208_122_681_n565), .B(
DP_OP_453J208_122_681_n420), .C(DP_OP_453J208_122_681_n847), .D(
DP_OP_453J208_122_681_n417), .ICI(DP_OP_453J208_122_681_n578), .S(
DP_OP_453J208_122_681_n409), .ICO(DP_OP_453J208_122_681_n407), .CO(
DP_OP_453J208_122_681_n408) );
CMPR42X2TS DP_OP_453J208_122_681_U318 ( .A(DP_OP_453J208_122_681_n411), .B(
DP_OP_453J208_122_681_n418), .C(DP_OP_453J208_122_681_n468), .D(
DP_OP_453J208_122_681_n414), .ICI(DP_OP_453J208_122_681_n409), .S(
DP_OP_453J208_122_681_n406), .ICO(DP_OP_453J208_122_681_n404), .CO(
DP_OP_453J208_122_681_n405) );
CMPR42X2TS DP_OP_453J208_122_681_U315 ( .A(DP_OP_453J208_122_681_n403), .B(
DP_OP_453J208_122_681_n408), .C(DP_OP_453J208_122_681_n400), .D(
DP_OP_453J208_122_681_n404), .ICI(DP_OP_453J208_122_681_n467), .S(
DP_OP_453J208_122_681_n397), .ICO(DP_OP_453J208_122_681_n395), .CO(
DP_OP_453J208_122_681_n396) );
CMPR42X2TS DP_OP_453J208_122_681_U311 ( .A(DP_OP_453J208_122_681_n392), .B(
DP_OP_453J208_122_681_n399), .C(DP_OP_453J208_122_681_n466), .D(
DP_OP_453J208_122_681_n389), .ICI(DP_OP_453J208_122_681_n395), .S(
DP_OP_453J208_122_681_n386), .ICO(DP_OP_453J208_122_681_n384), .CO(
DP_OP_453J208_122_681_n385) );
CMPR42X2TS DP_OP_453J208_122_681_U308 ( .A(DP_OP_453J208_122_681_n841), .B(
DP_OP_453J208_122_681_n549), .C(DP_OP_453J208_122_681_n575), .D(
DP_OP_453J208_122_681_n387), .ICI(DP_OP_453J208_122_681_n391), .S(
DP_OP_453J208_122_681_n378), .ICO(DP_OP_453J208_122_681_n376), .CO(
DP_OP_453J208_122_681_n377) );
CMPR42X2TS DP_OP_453J208_122_681_U307 ( .A(DP_OP_453J208_122_681_n381), .B(
DP_OP_453J208_122_681_n388), .C(DP_OP_453J208_122_681_n465), .D(
DP_OP_453J208_122_681_n378), .ICI(DP_OP_453J208_122_681_n384), .S(
DP_OP_453J208_122_681_n375), .ICO(DP_OP_453J208_122_681_n373), .CO(
DP_OP_453J208_122_681_n374) );
CMPR42X2TS DP_OP_453J208_122_681_U298 ( .A(DP_OP_453J208_122_681_n356), .B(
DP_OP_453J208_122_681_n364), .C(DP_OP_453J208_122_681_n353), .D(
DP_OP_453J208_122_681_n360), .ICI(DP_OP_453J208_122_681_n463), .S(
DP_OP_453J208_122_681_n350), .ICO(DP_OP_453J208_122_681_n348), .CO(
DP_OP_453J208_122_681_n349) );
DFFSX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n2458), .CK(clk),
.SN(n5858), .Q(DP_OP_453J208_122_681_n2082), .QN(FPMULT_Op_MY[22]) );
DFFSX4TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2467), .CK(clk), .SN(
n5813), .Q(n2457), .QN(n5783) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1645), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[18]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1637), .CK(clk),
.RN(n5855), .Q(FPMULT_Op_MY[10]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1647), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[20]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1646), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[19]), .QN(DP_OP_453J208_122_681_n2101) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1205), .CK(clk), .RN(
n5807), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n5792),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n5530) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1691), .CK(clk), .RN(n5859), .Q(
FPMULT_FSM_selector_A), .QN(n5709) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2148), .CK(clk), .RN(
n5811), .Q(n5871), .QN(n5864) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1550), .CK(clk), .RN(n5854), .Q(
FPMULT_FSM_selector_B[1]), .QN(n5637) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1348), .CK(clk), .RN(
n2315), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n5533) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2142), .CK(clk), .RN(n5838),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n5623) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2139), .CK(clk), .RN(n5831),
.Q(FPSENCOS_cont_var_out[0]), .QN(n5705) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2140), .CK(clk), .RN(n5830),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n5546) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1184), .CK(clk), .RN(
n5812), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n5579) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1186), .CK(clk), .RN(
n5784), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n5569) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1188), .CK(clk), .RN(
n5813), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n5565) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1694), .CK(clk), .RN(n5845),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n5618) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1692), .CK(clk), .RN(n5822),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n5532) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1842), .CK(clk), .RN(
n4039), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n5615) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1844), .CK(clk), .RN(
n5809), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n5611) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1915), .CK(clk), .RN(
n5784), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n5696) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1823), .CK(clk), .RN(
n5798), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n5616) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1825), .CK(clk), .RN(
n5794), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n5617) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1826), .CK(clk), .RN(
n2315), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n5559) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1827), .CK(clk), .RN(
n5786), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n5630) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1831), .CK(clk), .RN(
n5804), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n5609) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1832), .CK(clk), .RN(
n5792), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n5619) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1834), .CK(clk), .RN(
n5791), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n5621) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1838), .CK(clk), .RN(
n5790), .Q(FPADDSUB_intDY_EWSW[7]), .QN(n5686) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1828), .CK(clk), .RN(
n5794), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n5622) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1830), .CK(clk), .RN(
n5798), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n5549) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1821), .CK(clk), .RN(
n5792), .Q(FPADDSUB_intDY_EWSW[24]), .QN(n5589) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1822), .CK(clk), .RN(
n5811), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n5552) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1824), .CK(clk), .RN(
n5800), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n5627) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1833), .CK(clk), .RN(
n2316), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n5610) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1837), .CK(clk), .RN(
n5811), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n5620) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1695), .CK(clk), .RN(n5841),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n5554) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1937), .CK(clk), .RN(
n5788), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n5572) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1939), .CK(clk), .RN(
n5812), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n5573) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1927), .CK(clk), .RN(
n5784), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n5675) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1933), .CK(clk), .RN(
n2316), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n5674) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1936), .CK(clk), .RN(
n5787), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n5698) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1938), .CK(clk), .RN(
n4039), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n5689) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1920), .CK(clk), .RN(
n5788), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n5642) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1335), .CK(clk), .RN(
n5800), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n5529) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1627), .CK(clk),
.RN(n5854), .Q(FPMULT_Op_MY[0]) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n5848), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .QN(n5631) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1625), .CK(
clk), .RN(n5860), .Q(FPMULT_Sgf_normalized_result[23]), .QN(n5724) );
DFFSX1TS R_4 ( .D(n5779), .CK(clk), .SN(n5817), .Q(n5866) );
DFFRX1TS R_12 ( .D(n5777), .CK(clk), .RN(n5818), .Q(n5867) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1638), .CK(clk),
.RN(n5855), .Q(FPMULT_Op_MY[11]), .QN(DP_OP_453J208_122_681_n1721) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2138), .CK(clk), .RN(n5833),
.Q(FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1840), .CK(clk), .RN(
n5808), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1839), .CK(clk), .RN(
n5785), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1829), .CK(clk), .RN(
n5813), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1835), .CK(clk), .RN(
n5806), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1843), .CK(clk), .RN(
n5787), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1818), .CK(clk), .RN(
n5788), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1517), .CK(
clk), .RN(n5851), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2078), .CK(clk), .RN(
n5803), .Q(FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1845), .CK(clk), .RN(
n2315), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1183), .CK(clk), .RN(
n5810), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n5789),
.Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n2316),
.Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n5809),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n5808),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n5804),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n5791),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n5805),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n5806),
.Q(FPADDSUB_DMP_SFG[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n5803),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n5802),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1323), .CK(clk), .RN(
n5801), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1806), .CK(clk), .RN(n5802), .Q(FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1805), .CK(clk), .RN(n5810), .Q(FPADDSUB_Data_array_SWR[11]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1807), .CK(clk), .RN(n5791), .Q(FPADDSUB_Data_array_SWR[13]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1808), .CK(clk), .RN(n2315), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1802), .CK(clk), .RN(n5805), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1801), .CK(clk), .RN(n5804), .Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1349), .CK(clk), .RN(
n5793), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1957), .CK(clk), .RN(
n5842), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1469), .CK(clk), .RN(
n5792), .Q(result_add_subt[29]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1473), .CK(clk), .RN(
n5811), .Q(result_add_subt[25]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1475), .CK(clk), .RN(
n5788), .Q(result_add_subt[23]) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1468), .CK(clk), .RN(
n5812), .Q(result_add_subt[30]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1528), .CK(
clk), .RN(n5858), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1530), .CK(
clk), .RN(n5852), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1532), .CK(
clk), .RN(n5853), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1534), .CK(
clk), .RN(n5853), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1526), .CK(
clk), .RN(n5858), .Q(FPMULT_Sgf_normalized_result[9]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1536), .CK(
clk), .RN(n5853), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1524), .CK(
clk), .RN(n5852), .Q(FPMULT_Sgf_normalized_result[7]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n5830), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n5837), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1538), .CK(
clk), .RN(n5853), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1520), .CK(
clk), .RN(n5858), .Q(FPMULT_Sgf_normalized_result[3]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1522), .CK(
clk), .RN(n5852), .Q(FPMULT_Sgf_normalized_result[5]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1317), .CK(clk), .RN(
n5802), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n5596) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(
n5854), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1955), .CK(clk), .RN(
n5841), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1961), .CK(clk), .RN(
n5819), .Q(FPSENCOS_d_ff2_X[23]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1912), .CK(clk), .RN(
n4039), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n5801),
.Q(FPADDSUB_DMP_SFG[1]), .QN(n2218) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n5800),
.Q(FPADDSUB_DMP_SFG[3]), .QN(n2220) );
DFFRX1TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1353), .CK(clk), .RN(n5794),
.Q(FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1412), .CK(clk), .RN(
n5796), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n2227) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1958), .CK(clk), .RN(
n5842), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1959), .CK(clk), .RN(
n5841), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1960), .CK(clk), .RN(
n5845), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2151), .CK(
clk), .RN(n5813), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n5551) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1190), .CK(clk), .RN(
n5810), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n2198) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1796), .CK(clk), .RN(n5812),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1795), .CK(clk), .RN(n5787),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n1585), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[32]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1419), .CK(clk), .RN(n5811),
.Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1686), .CK(clk),
.RN(n4037), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1688), .CK(clk),
.RN(n4037), .Q(FPMULT_Op_MX[29]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1735), .CK(clk), .RN(
n5815), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n5836),
.Q(operation_reg[0]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1617), .CK(clk), .RN(
n5858), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1954), .CK(clk), .RN(
n5841), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n1586), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n1587), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n1588), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n1589), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n1590), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n1591), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n1592), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[39]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n1593), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n1594), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n1595), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n1596), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n1597), .CK(clk),
.RN(n5826), .Q(FPMULT_P_Sgf[44]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n1598), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[45]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1621), .CK(clk), .RN(
n5858), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1619), .CK(clk), .RN(
n5852), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1542), .CK(clk), .RN(
n5853), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n5835),
.Q(operation_reg[1]) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1600), .CK(clk),
.RN(n5857), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n5826), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n5828), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n5831), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n5832), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n5838), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n5816), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n5816), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n5837), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n5822), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n5833), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n5820), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n5827), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n5829), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n5826), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n5843), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n1552), .CK(clk),
.RN(n2314), .Q(FPMULT_P_Sgf[47]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n5827), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n5830), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n5837), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n5837), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n5838), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n5814), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n5823), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n5839), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n5843), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1683), .CK(clk),
.RN(n4037), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1544), .CK(clk), .RN(
n5854), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1546), .CK(clk), .RN(
n5854), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1547), .CK(clk), .RN(
n5854), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1549), .CK(clk), .RN(
n5854), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2060), .CK(clk), .RN(n5827), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2048), .CK(clk), .RN(n5827), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2072), .CK(clk), .RN(n5828), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2075), .CK(clk), .RN(n5829), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2054), .CK(clk), .RN(n5820), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2069), .CK(clk), .RN(n5837), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2066), .CK(clk), .RN(n5836), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2039), .CK(clk), .RN(n5816), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2045), .CK(clk), .RN(n5816), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2033), .CK(clk), .RN(n5836), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2042), .CK(clk), .RN(n5837), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2051), .CK(clk), .RN(n5848), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2027), .CK(clk), .RN(n5815), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2036), .CK(clk), .RN(n5820), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2057), .CK(clk), .RN(n5837), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2063), .CK(clk), .RN(n5836), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2024), .CK(clk), .RN(n5814), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2015), .CK(clk), .RN(n5833), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2018), .CK(clk), .RN(n5827), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2012), .CK(clk), .RN(n5839), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2021), .CK(clk), .RN(n5840), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2030), .CK(clk), .RN(n5841), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2009), .CK(clk), .RN(n5843), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1772), .CK(clk), .RN(n5840), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n5839), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1778), .CK(clk), .RN(n5843), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1784), .CK(clk), .RN(n5822), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1654), .CK(clk),
.RN(n5859), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2147), .CK(clk), .RN(
n5810), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1602), .CK(clk),
.RN(n5860), .Q(FPMULT_Add_result[22]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1603), .CK(clk),
.RN(n5857), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1604), .CK(clk),
.RN(n5852), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1605), .CK(clk),
.RN(n5859), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1606), .CK(clk),
.RN(n5857), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1607), .CK(clk),
.RN(n5852), .Q(FPMULT_Add_result[17]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1678), .CK(clk),
.RN(n5859), .Q(FPMULT_Op_MX[19]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1558), .CK(clk),
.RN(n5840), .Q(FPMULT_P_Sgf[5]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1730), .CK(clk), .RN(
n5797), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1420), .CK(clk), .RN(
n5788), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1425), .CK(clk), .RN(
n5812), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1430), .CK(clk), .RN(
n5784), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1435), .CK(clk), .RN(
n5785), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1440), .CK(clk), .RN(
n5813), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1445), .CK(clk), .RN(
n5810), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1450), .CK(clk), .RN(
n5792), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1455), .CK(clk), .RN(
n5811), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1567), .CK(clk),
.RN(n5847), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1571), .CK(clk),
.RN(n5819), .Q(FPMULT_P_Sgf[18]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1817), .CK(clk), .RN(
n5812), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n5826),
.Q(cordic_result[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1576), .CK(clk),
.RN(n5825), .Q(FPMULT_P_Sgf[23]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n5836), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n5837), .Q(
dataA[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n1599), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[46]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1792), .CK(clk), .RN(n5797),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1791), .CK(clk), .RN(n5802),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1790), .CK(clk), .RN(n5800),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRX1TS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1855), .CK(clk), .RN(n5832),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2118), .CK(clk), .RN(n5834), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2125), .CK(clk), .RN(n5820), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2131), .CK(clk), .RN(n5834), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2130), .CK(clk), .RN(n5833), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2116), .CK(clk), .RN(n5834), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2133), .CK(clk), .RN(n5833), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n5820), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1681), .CK(clk),
.RN(n5849), .Q(FPMULT_Op_MX[22]), .QN(DP_OP_453J208_122_681_n1796) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1677), .CK(clk),
.RN(n5857), .Q(FPMULT_Op_MX[18]), .QN(DP_OP_453J208_122_681_n1812) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1680), .CK(clk),
.RN(n4037), .Q(FPMULT_Op_MX[21]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1841), .CK(clk), .RN(
n5796), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1836), .CK(clk), .RN(
n5790), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1670), .CK(clk),
.RN(n5860), .Q(FPMULT_Op_MX[11]), .QN(DP_OP_453J208_122_681_n1601) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1318), .CK(clk), .RN(
n5786), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]), .QN(n2205) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1799), .CK(clk), .RN(n5784), .Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1797), .CK(clk), .RN(n5796),
.Q(FPADDSUB_Data_array_SWR[7]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1319), .CK(clk), .RN(
n5803), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n5542) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1648), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[21]), .QN(n2499) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1634), .CK(clk),
.RN(n5855), .Q(FPMULT_Op_MY[7]), .QN(n2461) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1632), .CK(clk),
.RN(n5851), .Q(FPMULT_Op_MY[5]), .QN(n2485) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1630), .CK(clk),
.RN(n5855), .Q(FPMULT_Op_MY[3]), .QN(n2468) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1628), .CK(clk),
.RN(n5854), .Q(FPMULT_Op_MY[1]), .QN(n2469) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1640), .CK(clk),
.RN(n5851), .Q(FPMULT_Op_MY[13]), .QN(n2483) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1793), .CK(clk), .RN(n5806),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1979), .CK(clk), .RN(
n5838), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n2001), .CK(clk), .RN(
n5838), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1985), .CK(clk), .RN(
n5837), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1999), .CK(clk), .RN(
n5836), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1991), .CK(clk), .RN(
n5838), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1650), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1651), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1636), .CK(clk),
.RN(n5855), .Q(FPMULT_Op_MY[9]), .QN(DP_OP_453J208_122_681_n1722) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(
n5785), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n5553) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1555), .CK(clk),
.RN(n5846), .Q(FPMULT_P_Sgf[2]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1574), .CK(clk),
.RN(n5815), .Q(FPMULT_P_Sgf[21]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1573), .CK(clk),
.RN(n5848), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1572), .CK(clk),
.RN(n5819), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1570), .CK(clk),
.RN(n5847), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1569), .CK(clk),
.RN(n2314), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1568), .CK(clk),
.RN(n5846), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2146), .CK(clk), .RN(
n5784), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n5726) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1562), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[9]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(
n5805), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n2219) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1347), .CK(clk), .RN(
n4045), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n5535) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1733), .CK(clk), .RN(
n5790), .Q(FPADDSUB_intAS) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1858), .CK(clk), .RN(
n5823), .Q(FPSENCOS_d_ff2_Y[28]), .QN(n2247) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n5833), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2117), .CK(clk), .RN(n5829), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n5821), .Q(
dataA[30]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2119), .CK(clk), .RN(n5833), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1415), .CK(clk), .RN(n4045),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n5821), .Q(
dataA[28]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1789), .CK(clk), .RN(n5807),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n5821), .Q(
dataA[23]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n5821), .Q(
dataB[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1561), .CK(clk),
.RN(n5824), .Q(FPMULT_P_Sgf[8]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2128), .CK(clk), .RN(n5831), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1560), .CK(clk),
.RN(n5840), .Q(FPMULT_P_Sgf[7]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1556), .CK(clk),
.RN(n5839), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n5821), .Q(
dataA[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1566), .CK(clk),
.RN(n5844), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1565), .CK(clk),
.RN(n5844), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1564), .CK(clk),
.RN(n5839), .Q(FPMULT_P_Sgf[11]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n2314),
.Q(cordic_result[23]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n5843),
.Q(cordic_result[24]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n5844),
.Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n5843),
.Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n5842),
.Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n5843),
.Q(cordic_result[28]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n5839),
.Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n5844),
.Q(cordic_result[30]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n5830),
.Q(cordic_result[7]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n5827),
.Q(cordic_result[9]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n5826),
.Q(cordic_result[12]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n5826),
.Q(cordic_result[10]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n5826),
.Q(cordic_result[14]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n5826),
.Q(cordic_result[11]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n5826),
.Q(cordic_result[8]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n5826),
.Q(cordic_result[16]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n5826),
.Q(cordic_result[13]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n5816),
.Q(cordic_result[6]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n5827),
.Q(cordic_result[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n5818),
.Q(cordic_result[20]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n5820),
.Q(cordic_result[19]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n5814),
.Q(cordic_result[21]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n5842),
.Q(cordic_result[18]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n5822),
.Q(cordic_result[15]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n5840),
.Q(cordic_result[22]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1671), .CK(clk),
.RN(n5850), .Q(n2200), .QN(n2476) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1679), .CK(clk),
.RN(n4037), .Q(FPMULT_Op_MX[20]), .QN(DP_OP_453J208_122_681_n1802) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1643), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[16]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1641), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[14]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1635), .CK(clk),
.RN(n5851), .Q(FPMULT_Op_MY[8]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1633), .CK(clk),
.RN(n5855), .Q(FPMULT_Op_MY[6]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1631), .CK(clk),
.RN(n5851), .Q(FPMULT_Op_MY[4]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1629), .CK(clk),
.RN(n5855), .Q(FPMULT_Op_MY[2]) );
DFFSX1TS R_1 ( .D(n5782), .CK(clk), .SN(n5814), .Q(n5869) );
DFFSX1TS R_2 ( .D(n5781), .CK(clk), .SN(n5818), .Q(n5870) );
DFFSX1TS R_3 ( .D(n5780), .CK(clk), .SN(n5817), .Q(n5865) );
DFFSX1TS R_11 ( .D(n5778), .CK(clk), .SN(n5821), .Q(n5868) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1207), .CK(clk), .RN(
n5805), .QN(n5528) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1194), .CK(clk), .RN(
n2316), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n5550) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1204), .CK(clk), .RN(
n5806), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n5595) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1690), .CK(clk), .RN(n5853), .Q(
FPMULT_FSM_selector_C), .QN(n5688) );
CMPR42X1TS DP_OP_453J208_122_681_U289 ( .A(DP_OP_453J208_122_681_n492), .B(
DP_OP_453J208_122_681_n505), .C(DP_OP_453J208_122_681_n333), .D(
DP_OP_453J208_122_681_n557), .ICI(DP_OP_453J208_122_681_n531), .S(
DP_OP_453J208_122_681_n323), .ICO(DP_OP_453J208_122_681_n321), .CO(
DP_OP_453J208_122_681_n322) );
DFFRXLTS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2082), .CK(clk), .RN(n5846),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n5541) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n1642), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[15]), .QN(n2462) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1644), .CK(clk),
.RN(n5856), .Q(FPMULT_Op_MY[17]), .QN(DP_OP_453J208_122_681_n2102) );
CMPR42X1TS DP_OP_453J208_122_681_U326 ( .A(DP_OP_453J208_122_681_n554), .B(
DP_OP_453J208_122_681_n851), .C(DP_OP_453J208_122_681_n429), .D(
DP_OP_453J208_122_681_n433), .ICI(DP_OP_453J208_122_681_n580), .S(
DP_OP_453J208_122_681_n427), .ICO(DP_OP_453J208_122_681_n425), .CO(
DP_OP_453J208_122_681_n426) );
CMPR42X1TS DP_OP_453J208_122_681_U309 ( .A(DP_OP_453J208_122_681_n536), .B(
DP_OP_453J208_122_681_n842), .C(DP_OP_453J208_122_681_n383), .D(
DP_OP_453J208_122_681_n390), .ICI(DP_OP_453J208_122_681_n562), .S(
DP_OP_453J208_122_681_n381), .ICO(DP_OP_453J208_122_681_n379), .CO(
DP_OP_453J208_122_681_n380) );
CMPR42X1TS DP_OP_453J208_122_681_U301 ( .A(DP_OP_453J208_122_681_n495), .B(
DP_OP_453J208_122_681_n521), .C(DP_OP_453J208_122_681_n508), .D(
DP_OP_453J208_122_681_n371), .ICI(DP_OP_453J208_122_681_n838), .S(
DP_OP_453J208_122_681_n359), .ICO(DP_OP_453J208_122_681_n357), .CO(
DP_OP_453J208_122_681_n358) );
CMPR42X1TS DP_OP_453J208_122_681_U304 ( .A(DP_OP_453J208_122_681_n382), .B(
DP_OP_453J208_122_681_n840), .C(DP_OP_453J208_122_681_n548), .D(
DP_OP_453J208_122_681_n839), .ICI(DP_OP_453J208_122_681_n574), .S(
DP_OP_453J208_122_681_n368), .ICO(DP_OP_453J208_122_681_n366), .CO(
DP_OP_453J208_122_681_n367) );
CMPR42X1TS DP_OP_453J208_122_681_U293 ( .A(DP_OP_453J208_122_681_n493), .B(
DP_OP_453J208_122_681_n571), .C(DP_OP_453J208_122_681_n506), .D(
DP_OP_453J208_122_681_n345), .ICI(DP_OP_453J208_122_681_n519), .S(
DP_OP_453J208_122_681_n335), .ICO(DP_OP_453J208_122_681_n333), .CO(
DP_OP_453J208_122_681_n334) );
CMPR42X1TS DP_OP_453J208_122_681_U295 ( .A(DP_OP_453J208_122_681_n559), .B(
DP_OP_453J208_122_681_n354), .C(DP_OP_453J208_122_681_n351), .D(
DP_OP_453J208_122_681_n347), .ICI(DP_OP_453J208_122_681_n355), .S(
DP_OP_453J208_122_681_n341), .ICO(DP_OP_453J208_122_681_n339), .CO(
DP_OP_453J208_122_681_n340) );
CMPR42X1TS DP_OP_453J208_122_681_U288 ( .A(DP_OP_453J208_122_681_n518), .B(
DP_OP_453J208_122_681_n1764), .C(DP_OP_453J208_122_681_n834), .D(
DP_OP_453J208_122_681_n831), .ICI(DP_OP_453J208_122_681_n334), .S(
DP_OP_453J208_122_681_n320), .ICO(DP_OP_453J208_122_681_n318), .CO(
DP_OP_453J208_122_681_n319) );
CMPR42X1TS DP_OP_453J208_122_681_U280 ( .A(DP_OP_453J208_122_681_n503), .B(
DP_OP_453J208_122_681_n1760), .C(DP_OP_453J208_122_681_n827), .D(
DP_OP_453J208_122_681_n529), .ICI(DP_OP_453J208_122_681_n306), .S(
DP_OP_453J208_122_681_n297), .ICO(DP_OP_453J208_122_681_n295), .CO(
DP_OP_453J208_122_681_n296) );
CMPR42X1TS DP_OP_453J208_122_681_U286 ( .A(DP_OP_453J208_122_681_n327), .B(
DP_OP_453J208_122_681_n460), .C(DP_OP_453J208_122_681_n328), .D(
DP_OP_453J208_122_681_n317), .ICI(DP_OP_453J208_122_681_n324), .S(
DP_OP_453J208_122_681_n314), .ICO(DP_OP_453J208_122_681_n312), .CO(
DP_OP_453J208_122_681_n313) );
CMPR42X1TS DP_OP_453J208_122_681_U282 ( .A(DP_OP_453J208_122_681_n308), .B(
DP_OP_453J208_122_681_n316), .C(DP_OP_453J208_122_681_n305), .D(
DP_OP_453J208_122_681_n459), .ICI(DP_OP_453J208_122_681_n312), .S(
DP_OP_453J208_122_681_n302), .ICO(DP_OP_453J208_122_681_n300), .CO(
DP_OP_453J208_122_681_n301) );
CMPR42X1TS DP_OP_453J208_122_681_U278 ( .A(DP_OP_453J208_122_681_n303), .B(
DP_OP_453J208_122_681_n304), .C(DP_OP_453J208_122_681_n458), .D(
DP_OP_453J208_122_681_n294), .ICI(DP_OP_453J208_122_681_n300), .S(
DP_OP_453J208_122_681_n291), .ICO(DP_OP_453J208_122_681_n289), .CO(
DP_OP_453J208_122_681_n290) );
CMPR42X1TS DP_OP_453J208_122_681_U272 ( .A(DP_OP_453J208_122_681_n527), .B(
DP_OP_453J208_122_681_n514), .C(DP_OP_453J208_122_681_n287), .D(
DP_OP_453J208_122_681_n281), .ICI(DP_OP_453J208_122_681_n277), .S(
DP_OP_453J208_122_681_n274), .ICO(DP_OP_453J208_122_681_n272), .CO(
DP_OP_453J208_122_681_n273) );
CMPR42X1TS DP_OP_453J208_122_681_U271 ( .A(DP_OP_453J208_122_681_n285), .B(
DP_OP_453J208_122_681_n274), .C(DP_OP_453J208_122_681_n282), .D(
DP_OP_453J208_122_681_n456), .ICI(DP_OP_453J208_122_681_n278), .S(
DP_OP_453J208_122_681_n271), .ICO(DP_OP_453J208_122_681_n269), .CO(
DP_OP_453J208_122_681_n270) );
DFFRX4TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1693), .CK(clk), .RN(n5832),
.Q(FPMULT_FS_Module_state_reg[1]) );
CMPR32X2TS DP_OP_26J208_123_9022_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n5553), .C(DP_OP_26J208_123_9022_n18), .CO(DP_OP_26J208_123_9022_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_26J208_123_9022_U8 ( .A(DP_OP_26J208_123_9022_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J208_123_9022_n8), .CO(
DP_OP_26J208_123_9022_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2145), .CK(clk), .RN(
n5788), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2456) );
CMPR32X2TS DP_OP_26J208_123_9022_U7 ( .A(DP_OP_26J208_123_9022_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J208_123_9022_n7), .CO(
DP_OP_26J208_123_9022_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2143), .CK(clk), .RN(n5817),
.Q(n2197), .QN(n5568) );
CMPR32X2TS DP_OP_26J208_123_9022_U6 ( .A(DP_OP_26J208_123_9022_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J208_123_9022_n6), .CO(
DP_OP_26J208_123_9022_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J208_123_9022_U5 ( .A(DP_OP_26J208_123_9022_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J208_123_9022_n5), .CO(
DP_OP_26J208_123_9022_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J208_123_9022_U4 ( .A(n5553), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J208_123_9022_n4), .CO(
DP_OP_26J208_123_9022_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J208_123_9022_U3 ( .A(n5553), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J208_123_9022_n3), .CO(
DP_OP_26J208_123_9022_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J208_123_9022_U2 ( .A(n5553), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J208_123_9022_n2), .CO(
DP_OP_26J208_123_9022_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS intadd_474_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n5623), .C(
intadd_474_CI), .CO(intadd_474_n3), .S(intadd_474_SUM_0_) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2144), .CK(clk), .RN(
n5813), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]), .QN(n5718) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2077), .CK(clk), .RN(
n4045), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2196) );
CMPR32X2TS intadd_473_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n5546), .C(
intadd_473_n2), .CO(intadd_473_n1), .S(intadd_473_SUM_2_) );
CMPR32X2TS intadd_474_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n4915), .C(
intadd_474_n3), .CO(intadd_474_n2), .S(intadd_474_SUM_1_) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2080), .CK(clk), .RN(
n5797), .Q(FPADDSUB_left_right_SHT2), .QN(n2412) );
CMPR32X2TS intadd_474_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n5546), .C(
intadd_474_n2), .CO(intadd_474_n1), .S(intadd_474_SUM_2_) );
CLKMX2X2TS U2219 ( .A(FPMULT_P_Sgf[40]), .B(n3935), .S0(n4820), .Y(n1593) );
AO22X1TS U2220 ( .A0(n5414), .A1(n5302), .B0(n5726), .B1(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n1353) );
AOI222X1TS U2221 ( .A0(n4341), .A1(cordic_result[2]), .B0(n4286), .B1(
FPSENCOS_d_ff_Yn[2]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[2]), .Y(n4338)
);
AOI222X1TS U2222 ( .A0(n4341), .A1(cordic_result[4]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[4]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[4]), .Y(n4289)
);
AOI222X1TS U2223 ( .A0(n4341), .A1(cordic_result[0]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[0]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[0]), .Y(n4333)
);
AOI222X1TS U2224 ( .A0(n4341), .A1(cordic_result[3]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[3]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[3]), .Y(n4288)
);
AOI222X1TS U2225 ( .A0(n4341), .A1(cordic_result[5]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[5]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[5]), .Y(n4290)
);
AOI222X1TS U2226 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n4971), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n4240) );
AOI222X1TS U2227 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n4971), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n4241) );
AOI222X1TS U2228 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n2306), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n4248) );
AOI222X1TS U2229 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n2306), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n4247) );
AOI222X1TS U2230 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n2306), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n4238) );
AOI222X1TS U2231 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n2306), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n4231) );
AOI222X1TS U2232 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n2306), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n4232) );
AOI222X1TS U2233 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n2306), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n4234) );
AOI222X1TS U2234 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n2306), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n4230) );
AOI222X1TS U2235 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n2306), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n4226) );
AOI222X1TS U2236 ( .A0(n4341), .A1(cordic_result[1]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[1]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[1]), .Y(n4314)
);
AOI222X1TS U2237 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n4971), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n4229) );
AOI222X1TS U2238 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n4971), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n4221) );
AOI222X1TS U2239 ( .A0(n4978), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n4211), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n4977), .Y(n4136)
);
AOI222X1TS U2240 ( .A0(n4978), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n4977), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n4125)
);
AOI222X1TS U2241 ( .A0(n4978), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4977), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n4127)
);
AOI222X1TS U2242 ( .A0(n4978), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4977), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n4128), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n4129)
);
AOI222X1TS U2243 ( .A0(n4978), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4977), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n4124)
);
AOI222X1TS U2244 ( .A0(n4978), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4977), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n4126)
);
AOI222X1TS U2245 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n4223) );
AOI222X1TS U2246 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n4222) );
AOI222X1TS U2247 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n4228) );
AOI222X1TS U2248 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n4220) );
AOI222X1TS U2249 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n4224) );
AOI222X1TS U2250 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n4128), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n4242)
);
AOI222X1TS U2251 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n4128), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n4246) );
AOI222X1TS U2252 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n4227) );
AOI222X1TS U2253 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n4239) );
AOI222X1TS U2254 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n4128), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n4243) );
AOI222X1TS U2255 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n4210)
);
AOI222X1TS U2256 ( .A0(n4245), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n4225)
);
AOI222X1TS U2257 ( .A0(n4978), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4244), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n4211), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n4212)
);
BUFX3TS U2258 ( .A(n4549), .Y(n4631) );
NAND2X4TS U2259 ( .A(n4047), .B(n4036), .Y(n4037) );
CLKINVX6TS U2260 ( .A(n5045), .Y(n4569) );
AOI21X1TS U2261 ( .A0(n4017), .A1(n4016), .B0(n4015), .Y(n4025) );
BUFX3TS U2262 ( .A(n4468), .Y(n4903) );
BUFX3TS U2263 ( .A(n4469), .Y(n4902) );
NAND2X4TS U2264 ( .A(n3888), .B(n3887), .Y(n4014) );
NAND2X1TS U2265 ( .A(n4550), .B(n5045), .Y(n4652) );
NAND2X1TS U2266 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n5139), .Y(n5141)
);
NOR2X1TS U2267 ( .A(n5046), .B(n4645), .Y(n4549) );
NOR3X1TS U2268 ( .A(FPSENCOS_cont_var_out[1]), .B(n5705), .C(n4354), .Y(
n4376) );
BUFX3TS U2269 ( .A(n4347), .Y(n4341) );
NAND2X1TS U2270 ( .A(n4001), .B(n4000), .Y(n4012) );
CLKXOR2X2TS U2271 ( .A(n3877), .B(n3876), .Y(n3888) );
AOI211X2TS U2272 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n4910), .B0(
n4683), .C0(n2298), .Y(n4645) );
NAND2X1TS U2273 ( .A(n3612), .B(n3611), .Y(n3852) );
AO22X1TS U2274 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[1]), .A1(n5295), .B0(
n4623), .B1(n4682), .Y(n4550) );
XOR2X1TS U2275 ( .A(n3842), .B(n3841), .Y(n3850) );
NAND2X1TS U2276 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n5133), .Y(n5136)
);
NOR2X1TS U2277 ( .A(n2508), .B(n3986), .Y(n4000) );
AOI21X1TS U2278 ( .A0(n3865), .A1(n3864), .B0(n3863), .Y(n3877) );
NAND2X1TS U2279 ( .A(n3823), .B(n3822), .Y(n4816) );
XOR2X1TS U2280 ( .A(n3580), .B(n3579), .Y(n3612) );
NAND2X1TS U2281 ( .A(n3975), .B(n3974), .Y(n3986) );
OAI211X1TS U2282 ( .A0(n5538), .A1(n4547), .B0(n4546), .C0(n4545), .Y(n4682)
);
NAND2X1TS U2283 ( .A(DP_OP_453J208_122_681_n239), .B(
DP_OP_453J208_122_681_n235), .Y(n3860) );
AO22X1TS U2284 ( .A0(operation[1]), .A1(n3533), .B0(begin_operation), .B1(
n4906), .Y(n4118) );
XOR2X1TS U2285 ( .A(n3813), .B(n3812), .Y(n3823) );
NAND2X1TS U2286 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n5129), .Y(n5131)
);
NOR2X1TS U2287 ( .A(n2506), .B(n3961), .Y(n3974) );
AOI22X1TS U2288 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(n5565), .B0(n5411), .B1(
n5410), .Y(n5418) );
NAND2X1TS U2289 ( .A(n3950), .B(n3949), .Y(n3961) );
NAND2X1TS U2290 ( .A(n3828), .B(n3836), .Y(n3859) );
NOR2X1TS U2291 ( .A(n4912), .B(n4894), .Y(n4283) );
NAND2X1TS U2292 ( .A(n3805), .B(n3804), .Y(n4809) );
OAI2BB2X1TS U2293 ( .B0(n5401), .B1(n5403), .A0N(n5639), .A1N(
FPADDSUB_DMP_SFG[16]), .Y(n5410) );
AOI21X1TS U2294 ( .A0(n3837), .A1(n3836), .B0(n3835), .Y(n3862) );
OAI21X1TS U2295 ( .A0(n4516), .A1(n4519), .B0(n4515), .Y(n4541) );
NOR2X1TS U2296 ( .A(n3827), .B(n3834), .Y(n3836) );
NAND2X1TS U2297 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n5125), .Y(n5127)
);
NOR2X1TS U2298 ( .A(n2504), .B(n3936), .Y(n3949) );
AOI22X1TS U2299 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n2198), .B0(n5397), .B1(
n5396), .Y(n5403) );
CMPR32X2TS U2300 ( .A(n3869), .B(n3867), .C(n3866), .CO(n3873), .S(
DP_OP_453J208_122_681_n237) );
NAND2X1TS U2301 ( .A(n3925), .B(n3924), .Y(n3936) );
NAND2X1TS U2302 ( .A(n2519), .B(n2521), .Y(n3834) );
OAI2BB2X1TS U2303 ( .B0(n5389), .B1(n5391), .A0N(n5635), .A1N(
FPADDSUB_DMP_SFG[14]), .Y(n5396) );
NAND2X1TS U2304 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n5121), .Y(n5123)
);
NAND2X1TS U2305 ( .A(n4532), .B(n5534), .Y(n4496) );
AOI22X1TS U2306 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n5556), .B0(n5385), .B1(
n5384), .Y(n5391) );
NAND2X1TS U2307 ( .A(DP_OP_453J208_122_681_n262), .B(
DP_OP_453J208_122_681_n270), .Y(n3623) );
NAND2X1TS U2308 ( .A(DP_OP_453J208_122_681_n253), .B(
DP_OP_453J208_122_681_n246), .Y(n3811) );
OAI2BB2X1TS U2309 ( .B0(n5377), .B1(n5379), .A0N(n5624), .A1N(
FPADDSUB_DMP_SFG[12]), .Y(n5384) );
NAND2X1TS U2310 ( .A(DP_OP_453J208_122_681_n271), .B(
DP_OP_453J208_122_681_n279), .Y(n3793) );
NOR2X1TS U2311 ( .A(DP_OP_453J208_122_681_n271), .B(
DP_OP_453J208_122_681_n279), .Y(n3620) );
NAND2X1TS U2312 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n5117), .Y(n5119)
);
AOI21X1TS U2313 ( .A0(n3571), .A1(n3771), .B0(n3570), .Y(n3572) );
NOR3BX1TS U2314 ( .AN(n4533), .B(FPADDSUB_Raw_mant_NRM_SWR[12]), .C(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n4518) );
NAND2X1TS U2315 ( .A(DP_OP_453J208_122_681_n291), .B(
DP_OP_453J208_122_681_n301), .Y(n3772) );
NAND2X1TS U2316 ( .A(DP_OP_453J208_122_681_n280), .B(
DP_OP_453J208_122_681_n290), .Y(n3779) );
XOR2X1TS U2317 ( .A(DP_OP_453J208_122_681_n447), .B(n3740), .Y(n3741) );
NAND2X1TS U2318 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n5113), .Y(n5115)
);
XNOR2X1TS U2319 ( .A(n3776), .B(n3744), .Y(n3749) );
CMPR32X2TS U2320 ( .A(n3993), .B(n2571), .C(n2570), .CO(
DP_OP_453J208_122_681_n258), .S(DP_OP_453J208_122_681_n259) );
CMPR32X2TS U2321 ( .A(n2542), .B(n2541), .C(n2540), .CO(
DP_OP_453J208_122_681_n250), .S(DP_OP_453J208_122_681_n251) );
NOR2X2TS U2322 ( .A(DP_OP_453J208_122_681_n302), .B(
DP_OP_453J208_122_681_n313), .Y(n3754) );
NOR2X2TS U2323 ( .A(DP_OP_453J208_122_681_n291), .B(
DP_OP_453J208_122_681_n301), .Y(n3773) );
NAND2X1TS U2324 ( .A(DP_OP_453J208_122_681_n314), .B(
DP_OP_453J208_122_681_n325), .Y(n3751) );
NAND2X1TS U2325 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n5109), .Y(n5111)
);
NOR2X2TS U2326 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n4494), .Y(n4537) );
CMPR32X2TS U2327 ( .A(n2613), .B(n2612), .C(n2611), .CO(
DP_OP_453J208_122_681_n287), .S(DP_OP_453J208_122_681_n288) );
CMPR32X2TS U2328 ( .A(n2545), .B(n2544), .C(n2543), .CO(n4008), .S(n3993) );
NOR2X1TS U2329 ( .A(DP_OP_453J208_122_681_n314), .B(
DP_OP_453J208_122_681_n325), .Y(n3743) );
CMPR32X2TS U2330 ( .A(n3326), .B(n3325), .C(n3324), .CO(n3982), .S(
DP_OP_453J208_122_681_n1756) );
CMPR32X2TS U2331 ( .A(DP_OP_453J208_122_681_n1796), .B(n3316), .C(n3315),
.CO(n4021), .S(n4007) );
CMPR32X2TS U2332 ( .A(n3329), .B(n3328), .C(n3327), .CO(n3994), .S(n3981) );
CMPR32X2TS U2333 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[19]), .C(n3317),
.CO(n3329), .S(n3326) );
CMPR32X2TS U2334 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[21]), .C(n2539),
.CO(n3315), .S(n2544) );
CMPR32X2TS U2335 ( .A(n2624), .B(n2623), .C(n2622), .CO(
DP_OP_453J208_122_681_n298), .S(DP_OP_453J208_122_681_n299) );
CMPR32X2TS U2336 ( .A(n3323), .B(n3322), .C(n3321), .CO(n3327), .S(n3324) );
NAND2X1TS U2337 ( .A(DP_OP_453J208_122_681_n338), .B(
DP_OP_453J208_122_681_n349), .Y(n3732) );
CMPR32X2TS U2338 ( .A(DP_OP_453J208_122_681_n1802), .B(n2548), .C(n2547),
.CO(n2543), .S(n3328) );
NAND2X1TS U2339 ( .A(FPMULT_Sgf_normalized_result[5]), .B(n5105), .Y(n5107)
);
XNOR2X1TS U2340 ( .A(n3646), .B(n3645), .Y(n3711) );
CMPR32X2TS U2341 ( .A(n3354), .B(n3353), .C(n3352), .CO(n3968), .S(n3956) );
NAND2X1TS U2342 ( .A(n3707), .B(n3706), .Y(n4722) );
NOR2X1TS U2343 ( .A(n4530), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4505) );
CMPR32X2TS U2344 ( .A(n3351), .B(n3350), .C(n3349), .CO(n3957), .S(
DP_OP_453J208_122_681_n1760) );
CMPR32X2TS U2345 ( .A(n3348), .B(n3347), .C(n3346), .CO(n3352), .S(n3349) );
CMPR32X2TS U2346 ( .A(n3333), .B(n3332), .C(n3331), .CO(n3325), .S(n3353) );
XOR2X1TS U2347 ( .A(n3651), .B(n3650), .Y(n3708) );
CMPR32X2TS U2348 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[17]), .C(n3334),
.CO(n3332), .S(n3348) );
CMPR32X2TS U2349 ( .A(DP_OP_453J208_122_681_n1812), .B(n3320), .C(n3319),
.CO(n3321), .S(n3331) );
CMPR32X2TS U2350 ( .A(n3338), .B(n3337), .C(n3336), .CO(n3354), .S(n3346) );
NOR2X1TS U2351 ( .A(n3702), .B(n3701), .Y(n4711) );
CMPR32X2TS U2352 ( .A(n3369), .B(n3368), .C(n3367), .CO(n3943), .S(n3932) );
CMPR32X2TS U2353 ( .A(n3366), .B(n3365), .C(n3364), .CO(n3350), .S(n3367) );
CMPR32X2TS U2354 ( .A(n3404), .B(n3403), .C(n3402), .CO(
DP_OP_453J208_122_681_n1764), .S(n3900) );
CMPR32X2TS U2355 ( .A(n3386), .B(n3385), .C(n3384), .CO(n3931), .S(n3918) );
CLKXOR2X2TS U2356 ( .A(n3230), .B(n3229), .Y(n3702) );
CMPR32X2TS U2357 ( .A(n3383), .B(n3382), .C(n3381), .CO(n3368), .S(n3384) );
CMPR32X2TS U2358 ( .A(n3401), .B(n3400), .C(n3399), .CO(n3385), .S(n3402) );
CMPR32X2TS U2359 ( .A(n3372), .B(n3371), .C(n3370), .CO(n3369), .S(n3386) );
CMPR32X2TS U2360 ( .A(n2496), .B(n3341), .C(n3340), .CO(n3347), .S(n3366) );
CMPR32X2TS U2361 ( .A(n3345), .B(n3344), .C(n3343), .CO(n3351), .S(n3364) );
NAND2X1TS U2362 ( .A(n3697), .B(n3696), .Y(n4702) );
CMPR32X2TS U2363 ( .A(n3422), .B(n3421), .C(n3420), .CO(
DP_OP_453J208_122_681_n1766), .S(n3883) );
CMPR32X2TS U2364 ( .A(n3407), .B(n3406), .C(n3405), .CO(n3399), .S(n3422) );
CMPR32X2TS U2365 ( .A(n3410), .B(n3409), .C(n3408), .CO(n3403), .S(n3421) );
CMPR32X2TS U2366 ( .A(n3389), .B(n3388), .C(n3387), .CO(n3381), .S(n3404) );
CMPR32X2TS U2367 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[15]), .C(n3356),
.CO(n3343), .S(n3370) );
CMPR32X2TS U2368 ( .A(n3361), .B(n3360), .C(n3359), .CO(n3365), .S(n3382) );
CMPR32X2TS U2369 ( .A(n3377), .B(n3376), .C(n3375), .CO(n3383), .S(n3400) );
CMPR32X2TS U2370 ( .A(n2654), .B(n2653), .C(n2652), .CO(
DP_OP_453J208_122_681_n369), .S(DP_OP_453J208_122_681_n370) );
NAND2X1TS U2371 ( .A(DP_OP_453J208_122_681_n406), .B(
DP_OP_453J208_122_681_n415), .Y(n3657) );
CMPR32X2TS U2372 ( .A(FPMULT_Op_MX[13]), .B(n2478), .C(n3363), .CO(n3371),
.S(n3388) );
NAND2X1TS U2373 ( .A(n3164), .B(n3163), .Y(n3218) );
CMPR32X2TS U2374 ( .A(n3394), .B(n3393), .C(n3392), .CO(n3401), .S(n3409) );
CMPR32X2TS U2375 ( .A(n3178), .B(n3177), .C(n3176), .CO(n3185), .S(n3169) );
CMPR32X2TS U2376 ( .A(n3148), .B(n3147), .C(n3146), .CO(n3170), .S(n3167) );
NAND2X1TS U2377 ( .A(n3694), .B(n3693), .Y(n4697) );
CMPR32X2TS U2378 ( .A(n2475), .B(n3380), .C(n2483), .CO(n3387), .S(n3405) );
AOI21X2TS U2379 ( .A0(n3231), .A1(n3162), .B0(n3161), .Y(n3214) );
CMPR32X2TS U2380 ( .A(n3441), .B(n3440), .C(n3439), .CO(n3882), .S(n3845) );
CMPR32X2TS U2381 ( .A(n3438), .B(n3437), .C(n3436), .CO(n3420), .S(n3439) );
CMPR32X2TS U2382 ( .A(n3458), .B(n3457), .C(n3456), .CO(n3844), .S(n3608) );
CMPR32X2TS U2383 ( .A(n3139), .B(n3138), .C(n3137), .CO(n3168), .S(n3165) );
CMPR32X2TS U2384 ( .A(n2663), .B(n2662), .C(n2661), .CO(
DP_OP_453J208_122_681_n382), .S(DP_OP_453J208_122_681_n383) );
CMPR32X2TS U2385 ( .A(n3425), .B(n3424), .C(n3423), .CO(n3408), .S(n3441) );
CMPR32X2TS U2386 ( .A(n3152), .B(n3151), .C(n3150), .CO(n3176), .S(n3146) );
CMPR32X2TS U2387 ( .A(n3128), .B(n3127), .C(n3126), .CO(n3166), .S(n3163) );
CMPR32X2TS U2388 ( .A(n3473), .B(n3472), .C(n3471), .CO(n3607), .S(n3604) );
NOR2X1TS U2389 ( .A(n3233), .B(n3226), .Y(n3162) );
NOR2X2TS U2390 ( .A(n3238), .B(n3240), .Y(n3232) );
OAI21X2TS U2391 ( .A0(n3240), .A1(n3245), .B0(n3241), .Y(n3231) );
CLKXOR2X2TS U2392 ( .A(n3258), .B(n3257), .Y(n3692) );
CMPR32X2TS U2393 ( .A(n3455), .B(n3454), .C(n3453), .CO(n3440), .S(n3456) );
CMPR32X2TS U2394 ( .A(n2674), .B(n2673), .C(n2672), .CO(
DP_OP_453J208_122_681_n410), .S(DP_OP_453J208_122_681_n411) );
NAND2X1TS U2395 ( .A(DP_OP_453J208_122_681_n424), .B(
DP_OP_453J208_122_681_n431), .Y(n3665) );
CMPR32X2TS U2396 ( .A(n3136), .B(n3135), .C(n3134), .CO(n3137), .S(n3126) );
CMPR32X2TS U2397 ( .A(n3470), .B(n3469), .C(n3468), .CO(n3457), .S(n3471) );
CMPR32X2TS U2398 ( .A(n3415), .B(n3414), .C(n3413), .CO(n3410), .S(n3437) );
CMPR32X2TS U2399 ( .A(n2200), .B(n3398), .C(n3397), .CO(n3406), .S(n3423) );
CMPR32X2TS U2400 ( .A(n3144), .B(n3143), .C(n3142), .CO(n3147), .S(n3138) );
NAND2X1TS U2401 ( .A(n3156), .B(n3155), .Y(n3241) );
NAND2X1TS U2402 ( .A(n3158), .B(n3157), .Y(n3234) );
NAND2X1TS U2403 ( .A(DP_OP_453J208_122_681_n432), .B(
DP_OP_453J208_122_681_n437), .Y(n3669) );
CMPR32X2TS U2404 ( .A(n3444), .B(n3443), .C(n3442), .CO(n3436), .S(n3458) );
NOR2X2TS U2405 ( .A(n3156), .B(n3155), .Y(n3240) );
NAND2X1TS U2406 ( .A(n3689), .B(n3688), .Y(n4748) );
NOR2X2TS U2407 ( .A(n3158), .B(n3157), .Y(n3233) );
CMPR32X2TS U2408 ( .A(n3491), .B(n3490), .C(n3489), .CO(n3603), .S(n3602) );
CLKXOR2X2TS U2409 ( .A(n2727), .B(n2726), .Y(n2822) );
CMPR32X2TS U2410 ( .A(n3488), .B(n3487), .C(n3486), .CO(n3472), .S(n3489) );
CMPR32X2TS U2411 ( .A(n3485), .B(n3484), .C(n3483), .CO(n3468), .S(n3490) );
CMPR32X2TS U2412 ( .A(n3461), .B(n3460), .C(n3459), .CO(n3454), .S(n3473) );
CMPR32X2TS U2413 ( .A(n3100), .B(n3099), .C(n3098), .CO(n3160), .S(n3157) );
CMPR32X2TS U2414 ( .A(n3115), .B(n3114), .C(n3113), .CO(n3164), .S(n3159) );
CMPR32X2TS U2415 ( .A(n3435), .B(n3434), .C(n3433), .CO(n3438), .S(n3453) );
NAND2X1TS U2416 ( .A(n3154), .B(n3153), .Y(n3245) );
CMPR32X2TS U2417 ( .A(n3448), .B(n3447), .C(n3446), .CO(n3455), .S(n3469) );
CMPR32X2TS U2418 ( .A(n3131), .B(n3130), .C(n3129), .CO(n3139), .S(n3134) );
CMPR32X2TS U2419 ( .A(n3083), .B(n3082), .C(n3081), .CO(n3158), .S(n3156) );
CMPR32X2TS U2420 ( .A(n2685), .B(n2684), .C(n2683), .CO(
DP_OP_453J208_122_681_n420), .S(DP_OP_453J208_122_681_n421) );
CLKXOR2X2TS U2421 ( .A(n3272), .B(n3271), .Y(n4746) );
CMPR32X2TS U2422 ( .A(n3506), .B(n3505), .C(n3504), .CO(n3601), .S(n3597) );
CMPR32X2TS U2423 ( .A(n3503), .B(n3502), .C(n3501), .CO(n3491), .S(n3504) );
CMPR32X2TS U2424 ( .A(n3112), .B(n3111), .C(n3110), .CO(n3113), .S(n3099) );
CMPR32X2TS U2425 ( .A(n3494), .B(n3493), .C(n3492), .CO(n3486), .S(n3506) );
CMPR32X2TS U2426 ( .A(n3097), .B(n3096), .C(n3095), .CO(n3098), .S(n3081) );
CMPR32X2TS U2427 ( .A(n3121), .B(n3120), .C(n3119), .CO(n3127), .S(n3114) );
NOR2X1TS U2428 ( .A(n3154), .B(n3153), .Y(n3238) );
CMPR32X2TS U2429 ( .A(n3518), .B(n3517), .C(n3516), .CO(n3596), .S(n3595) );
NOR2X1TS U2430 ( .A(DP_OP_453J208_122_681_n1721), .B(n2487), .Y(n3152) );
OAI21X2TS U2431 ( .A0(n2568), .A1(n2567), .B0(n2566), .Y(n2722) );
NOR2X1TS U2432 ( .A(n2723), .B(n2621), .Y(n2717) );
CMPR32X2TS U2433 ( .A(n3080), .B(n3079), .C(n3078), .CO(n3155), .S(n3154) );
CMPR32X2TS U2434 ( .A(n3107), .B(n3106), .C(n3105), .CO(n3120), .S(n3112) );
CMPR32X2TS U2435 ( .A(n3090), .B(n3089), .C(n3088), .CO(n3111), .S(n3097) );
CMPR32X2TS U2436 ( .A(n3515), .B(n3514), .C(n3513), .CO(n3505), .S(n3516) );
CMPR32X2TS U2437 ( .A(n3086), .B(n3085), .C(n3084), .CO(n3100), .S(n3095) );
CMPR32X2TS U2438 ( .A(n3521), .B(n3520), .C(n3519), .CO(n3594), .S(n3591) );
NAND2X1TS U2439 ( .A(n3034), .B(n3033), .Y(n3262) );
CMPR32X2TS U2440 ( .A(n3118), .B(n3117), .C(n3116), .CO(n3128), .S(n3119) );
CMPR32X2TS U2441 ( .A(n3103), .B(n3102), .C(n3101), .CO(n3115), .S(n3110) );
NOR2X2TS U2442 ( .A(n3036), .B(n3035), .Y(n3254) );
CLKXOR2X2TS U2443 ( .A(n2600), .B(n2599), .Y(n2828) );
CLKXOR2X2TS U2444 ( .A(n2589), .B(n2588), .Y(n2830) );
CMPR32X2TS U2445 ( .A(n2709), .B(n2708), .C(n2707), .CO(
DP_OP_453J208_122_681_n439), .S(DP_OP_453J208_122_681_n440) );
CMPR32X2TS U2446 ( .A(n3067), .B(n3066), .C(n3065), .CO(n3082), .S(n3078) );
ADDHXLTS U2447 ( .A(n3500), .B(n3499), .CO(n3501), .S(n3513) );
CMPR32X2TS U2448 ( .A(n3061), .B(n3060), .C(n3059), .CO(n3153), .S(n3036) );
CMPR32X2TS U2449 ( .A(n3512), .B(n3511), .C(n3510), .CO(n3517), .S(n3519) );
CMPR32X2TS U2450 ( .A(n3524), .B(n3523), .C(n3522), .CO(n3590), .S(n3589) );
NAND2X1TS U2451 ( .A(n2560), .B(n2559), .Y(n2601) );
NOR2X1TS U2452 ( .A(n2596), .B(n2563), .Y(n2565) );
NOR2X1TS U2453 ( .A(n2396), .B(n2437), .Y(n2621) );
BUFX4TS U2454 ( .A(n3428), .Y(n2422) );
OAI22X1TS U2455 ( .A0(n3509), .A1(DP_OP_453J208_122_681_n2101), .B0(n2400),
.B1(n3498), .Y(n3514) );
CMPR32X2TS U2456 ( .A(n2919), .B(n2918), .C(n2917), .CO(n3031), .S(n3030) );
CMPR32X2TS U2457 ( .A(n2902), .B(n2901), .C(n2900), .CO(n3033), .S(n3032) );
CMPR32X2TS U2458 ( .A(n3043), .B(n3042), .C(n3041), .CO(n3080), .S(n3061) );
CMPR32X2TS U2459 ( .A(n3046), .B(n3045), .C(n3044), .CO(n3079), .S(n3059) );
ADDHXLTS U2460 ( .A(n2710), .B(n3582), .CO(DP_OP_453J208_122_681_n441), .S(
n2708) );
CMPR32X2TS U2461 ( .A(n2885), .B(n2884), .C(n2883), .CO(n3035), .S(n3034) );
CMPR32X2TS U2462 ( .A(n3072), .B(n3071), .C(n3070), .CO(n3096), .S(n3066) );
ADDHXLTS U2463 ( .A(n2682), .B(n2681), .CO(n3520), .S(n3522) );
CMPR32X2TS U2464 ( .A(n3064), .B(n3063), .C(n3062), .CO(n3083), .S(n3065) );
CMPR32X2TS U2465 ( .A(n3527), .B(n3526), .C(n3525), .CO(n3588), .S(n3587) );
CMPR32X2TS U2466 ( .A(n3551), .B(n3550), .C(n3549), .CO(
DP_OP_453J208_122_681_n448), .S(n3557) );
CMPR32X2TS U2467 ( .A(n2916), .B(n2915), .C(n2914), .CO(n2901), .S(n2917) );
CMPR32X2TS U2468 ( .A(n2899), .B(n2898), .C(n2897), .CO(n2884), .S(n2900) );
CMPR32X2TS U2469 ( .A(n2868), .B(n2867), .C(n2866), .CO(n3044), .S(n2885) );
ADDHXLTS U2470 ( .A(n3540), .B(n3539), .CO(DP_OP_453J208_122_681_n450), .S(
n3551) );
CMPR32X2TS U2471 ( .A(n3077), .B(n3076), .C(n3075), .CO(n3084), .S(n3062) );
CMPR32X2TS U2472 ( .A(n3057), .B(n3056), .C(n3055), .CO(n3063), .S(n3042) );
CMPR32X2TS U2473 ( .A(n3049), .B(n3048), .C(n3047), .CO(n3067), .S(n3045) );
NAND2X1TS U2474 ( .A(n2488), .B(n2490), .Y(n3004) );
NAND2X4TS U2475 ( .A(n2668), .B(n2292), .Y(n3497) );
NOR2X2TS U2476 ( .A(FPMULT_Op_MY[19]), .B(n2302), .Y(n2596) );
NOR2X2TS U2477 ( .A(n3024), .B(n3023), .Y(n3283) );
CLKXOR2X2TS U2478 ( .A(n2647), .B(n2646), .Y(n2838) );
CMPR32X2TS U2479 ( .A(n2882), .B(n2881), .C(n2880), .CO(n3060), .S(n2883) );
CLKXOR2X2TS U2480 ( .A(n2642), .B(n2641), .Y(n2836) );
CMPR32X2TS U2481 ( .A(n2888), .B(n2887), .C(n2886), .CO(n2880), .S(n2902) );
CMPR32X2TS U2482 ( .A(n2856), .B(n2855), .C(n2854), .CO(n3046), .S(n2881) );
CMPR32X2TS U2483 ( .A(n2896), .B(n2895), .C(n2894), .CO(n2899), .S(n2914) );
CMPR32X2TS U2484 ( .A(n2874), .B(n2873), .C(n2872), .CO(n2882), .S(n2898) );
NAND2X1TS U2485 ( .A(n2438), .B(n2301), .Y(n2590) );
CMPR32X2TS U2486 ( .A(n3056), .B(n2865), .C(n2469), .CO(n3041), .S(n2866) );
CMPR32X2TS U2487 ( .A(n3019), .B(n3018), .C(n3017), .CO(n3025), .S(n3024) );
CMPR32X2TS U2488 ( .A(n2864), .B(n2863), .C(n2862), .CO(n2867), .S(n2886) );
ADDFX2TS U2489 ( .A(n2931), .B(n2930), .CI(n2929), .CO(n2918), .S(n3005) );
CMPR32X2TS U2490 ( .A(n2922), .B(n2921), .C(n2920), .CO(n2915), .S(n3007) );
NAND2X1TS U2491 ( .A(n2999), .B(n2998), .Y(n3293) );
CMPR32X2TS U2492 ( .A(n3016), .B(n3015), .C(n3014), .CO(n3006), .S(n3017) );
NOR2X1TS U2493 ( .A(n2962), .B(n2961), .Y(n3307) );
INVX4TS U2494 ( .A(n2818), .Y(n3556) );
NOR2X1TS U2495 ( .A(n2438), .B(n2301), .Y(n2583) );
NAND2X2TS U2496 ( .A(n2964), .B(n2963), .Y(n3303) );
OAI21X1TS U2497 ( .A0(n2647), .A1(n2643), .B0(n2644), .Y(n2614) );
CMPR32X2TS U2498 ( .A(n2910), .B(n2909), .C(n2908), .CO(n2916), .S(n2930) );
CMPR32X2TS U2499 ( .A(n3010), .B(n3009), .C(n3008), .CO(n2929), .S(n3019) );
CMPR32X2TS U2500 ( .A(n2958), .B(n2957), .C(n2956), .CO(n2963), .S(n2962) );
CLKBUFX2TS U2501 ( .A(FPMULT_Op_MY[17]), .Y(n2438) );
NAND2X1TS U2502 ( .A(n2385), .B(FPMULT_Op_MY[15]), .Y(n2639) );
NOR2X1TS U2503 ( .A(DP_OP_453J208_122_681_n1721), .B(n2495), .Y(n3077) );
NAND2XLTS U2504 ( .A(n2484), .B(n2648), .Y(n2650) );
CLKBUFX2TS U2505 ( .A(n3479), .Y(n2427) );
NAND2X1TS U2506 ( .A(n2454), .B(n2625), .Y(n2738) );
CMPR32X2TS U2507 ( .A(n2994), .B(n2993), .C(n2992), .CO(n3000), .S(n2999) );
ADDFX2TS U2508 ( .A(n2941), .B(n2940), .CI(n2939), .CO(n2965), .S(n2964) );
OAI21X1TS U2509 ( .A0(n3545), .A1(n3554), .B0(n3546), .Y(n3313) );
ADDFHX1TS U2510 ( .A(n2997), .B(n2996), .CI(n2995), .CO(n2998), .S(n2966) );
ADDFX2TS U2511 ( .A(n3022), .B(n3021), .CI(n3020), .CO(n3023), .S(n3001) );
CMPR32X2TS U2512 ( .A(n2988), .B(n2987), .C(n2986), .CO(n2993), .S(n2995) );
CMPR32X2TS U2513 ( .A(n2991), .B(n2990), .C(n2989), .CO(n3021), .S(n2992) );
CMPR32X2TS U2514 ( .A(n3013), .B(n3012), .C(n3011), .CO(n3018), .S(n3020) );
CMPR32X2TS U2515 ( .A(n2971), .B(n2970), .C(n2969), .CO(n3014), .S(n3022) );
BUFX3TS U2516 ( .A(FPMULT_Op_MY[9]), .Y(n2437) );
NAND2X1TS U2517 ( .A(n2954), .B(n2953), .Y(n3312) );
OAI22X1TS U2518 ( .A0(n3093), .A1(n2485), .B0(n2430), .B1(n2936), .Y(n2940)
);
CLKBUFX2TS U2519 ( .A(FPMULT_Op_MY[9]), .Y(n2436) );
INVX4TS U2520 ( .A(n2386), .Y(n2301) );
INVX4TS U2521 ( .A(FPMULT_Op_MY[0]), .Y(n3555) );
NAND2X1TS U2522 ( .A(n2396), .B(n2437), .Y(n2719) );
AOI21X1TS U2523 ( .A0(n2595), .A1(n2591), .B0(n2584), .Y(n2589) );
CLKXOR2X2TS U2524 ( .A(n2558), .B(n2557), .Y(n2826) );
NOR2XLTS U2525 ( .A(DP_OP_453J208_122_681_n1721), .B(n2491), .Y(n3057) );
ADDHXLTS U2526 ( .A(n2656), .B(n2655), .CO(DP_OP_453J208_122_681_n371), .S(
n2652) );
XNOR2X1TS U2527 ( .A(n2826), .B(n2415), .Y(n2829) );
NOR2XLTS U2528 ( .A(n2483), .B(n2224), .Y(n3398) );
ADDHXLTS U2529 ( .A(n2676), .B(n2675), .CO(DP_OP_453J208_122_681_n412), .S(
n2672) );
CLKBUFX2TS U2530 ( .A(n2399), .Y(n2292) );
ADDHXLTS U2531 ( .A(n3418), .B(n3417), .CO(n3425), .S(n3443) );
CMPR42X1TS U2532 ( .A(DP_OP_453J208_122_681_n532), .B(
DP_OP_453J208_122_681_n1766), .C(DP_OP_453J208_122_681_n833), .D(
DP_OP_453J208_122_681_n558), .ICI(DP_OP_453J208_122_681_n346), .S(
DP_OP_453J208_122_681_n332), .ICO(DP_OP_453J208_122_681_n330), .CO(
DP_OP_453J208_122_681_n331) );
CMPR42X1TS U2533 ( .A(DP_OP_453J208_122_681_n561), .B(
DP_OP_453J208_122_681_n370), .C(DP_OP_453J208_122_681_n379), .D(
DP_OP_453J208_122_681_n376), .ICI(DP_OP_453J208_122_681_n380), .S(
DP_OP_453J208_122_681_n365), .ICO(DP_OP_453J208_122_681_n363), .CO(
DP_OP_453J208_122_681_n364) );
CMPR42X1TS U2534 ( .A(DP_OP_453J208_122_681_n545), .B(
DP_OP_453J208_122_681_n342), .C(DP_OP_453J208_122_681_n335), .D(
DP_OP_453J208_122_681_n343), .ICI(DP_OP_453J208_122_681_n339), .S(
DP_OP_453J208_122_681_n329), .ICO(DP_OP_453J208_122_681_n327), .CO(
DP_OP_453J208_122_681_n328) );
OAI22X1TS U2535 ( .A0(n3497), .A1(DP_OP_453J208_122_681_n2102), .B0(n2292),
.B1(n2680), .Y(n3523) );
CMPR42X1TS U2536 ( .A(DP_OP_453J208_122_681_n568), .B(
DP_OP_453J208_122_681_n439), .C(DP_OP_453J208_122_681_n436), .D(
DP_OP_453J208_122_681_n435), .ICI(DP_OP_453J208_122_681_n471), .S(
DP_OP_453J208_122_681_n432), .ICO(DP_OP_453J208_122_681_n430), .CO(
DP_OP_453J208_122_681_n431) );
XOR3X1TS U2537 ( .A(n3873), .B(n3872), .C(DP_OP_453J208_122_681_n233), .Y(
n3874) );
ADDHXLTS U2538 ( .A(n2879), .B(n2878), .CO(n2887), .S(n2903) );
NAND2X1TS U2539 ( .A(n3038), .B(n3260), .Y(n3040) );
OAI21XLTS U2540 ( .A0(n3214), .A1(n3217), .B0(n3218), .Y(n3206) );
OAI21XLTS U2541 ( .A0(n3223), .A1(n3233), .B0(n3234), .Y(n3224) );
NAND2X1TS U2542 ( .A(n3883), .B(n3882), .Y(n3912) );
NAND2X1TS U2543 ( .A(DP_OP_453J208_122_681_n240), .B(
DP_OP_453J208_122_681_n245), .Y(n3829) );
OR2X1TS U2544 ( .A(n3185), .B(n3184), .Y(n2448) );
NAND2X1TS U2545 ( .A(DP_OP_453J208_122_681_n302), .B(
DP_OP_453J208_122_681_n313), .Y(n3755) );
NOR2XLTS U2546 ( .A(n4199), .B(FPADDSUB_intDY_EWSW[24]), .Y(n4140) );
OAI21XLTS U2547 ( .A0(n3816), .A1(n3815), .B0(n3814), .Y(n3821) );
NOR2XLTS U2548 ( .A(n4108), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n4109) );
OAI21XLTS U2549 ( .A0(n3651), .A1(n3647), .B0(n3648), .Y(n3646) );
NOR2XLTS U2550 ( .A(n3278), .B(n3283), .Y(n3028) );
OR2X1TS U2551 ( .A(n3982), .B(n3981), .Y(n2509) );
OR2X1TS U2552 ( .A(n3932), .B(n3931), .Y(n2505) );
NOR2X1TS U2553 ( .A(n3850), .B(n3849), .Y(n3889) );
XOR2X1TS U2554 ( .A(n3734), .B(n3727), .Y(n3730) );
OAI21XLTS U2555 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n4528), .B0(n2227),
.Y(n4529) );
AOI21X2TS U2556 ( .A0(n3277), .A1(n3028), .B0(n3027), .Y(n3249) );
NAND2X1TS U2557 ( .A(n3001), .B(n3000), .Y(n3290) );
NOR2X1TS U2558 ( .A(n3697), .B(n3696), .Y(n4701) );
NAND2X1TS U2559 ( .A(n3702), .B(n3701), .Y(n4712) );
NOR2XLTS U2560 ( .A(n4013), .B(n3961), .Y(n3952) );
NOR2X1TS U2561 ( .A(n3612), .B(n3611), .Y(n3853) );
OR2X1TS U2562 ( .A(n3802), .B(n3801), .Y(n2517) );
NAND2X1TS U2563 ( .A(n2219), .B(n5528), .Y(n5305) );
NAND2X1TS U2564 ( .A(n3749), .B(n3748), .Y(n4779) );
OR2X1TS U2565 ( .A(n3767), .B(n3766), .Y(n2223) );
OR2X1TS U2566 ( .A(n4502), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n4494) );
NAND2X1TS U2567 ( .A(n2962), .B(n2961), .Y(n3308) );
OR2X1TS U2568 ( .A(n3709), .B(n3708), .Y(n2452) );
OR2X1TS U2569 ( .A(n4645), .B(n4652), .Y(n2229) );
OAI21X2TS U2570 ( .A0(n4701), .A1(n4704), .B0(n4702), .Y(n4708) );
NOR2X1TS U2571 ( .A(n4458), .B(n3535), .Y(n3536) );
INVX2TS U2572 ( .A(n5188), .Y(n4116) );
BUFX3TS U2573 ( .A(n4468), .Y(n4487) );
OAI21XLTS U2574 ( .A0(n5532), .A1(n4671), .B0(FPMULT_FS_Module_state_reg[3]),
.Y(n4139) );
INVX2TS U2575 ( .A(operation[1]), .Y(n4458) );
XNOR2X1TS U2576 ( .A(n3301), .B(n3300), .Y(n4753) );
OAI211XLTS U2577 ( .A0(n4598), .A1(n4646), .B0(n4591), .C0(n4590), .Y(n1793)
);
OAI211XLTS U2578 ( .A0(n4582), .A1(n4646), .B0(n4581), .C0(n4580), .Y(n1797)
);
OAI211XLTS U2579 ( .A0(n5054), .A1(n4648), .B0(n4559), .C0(n4558), .Y(n1790)
);
OAI211XLTS U2580 ( .A0(n4588), .A1(n4646), .B0(n4578), .C0(n4577), .Y(n1795)
);
OAI211XLTS U2581 ( .A0(n4622), .A1(n4646), .B0(n4621), .C0(n4620), .Y(n1801)
);
OAI211XLTS U2582 ( .A0(n4448), .A1(n5764), .B0(n4357), .C0(n4356), .Y(n1845)
);
OAI211XLTS U2583 ( .A0(n4445), .A1(n5737), .B0(n4425), .C0(n4424), .Y(n1933)
);
OAI211XLTS U2584 ( .A0(n4448), .A1(n5720), .B0(n4419), .C0(n4418), .Y(n1919)
);
OAI21XLTS U2585 ( .A0(n5862), .A1(n5566), .B0(n4117), .Y(n1358) );
OAI211XLTS U2586 ( .A0(n4456), .A1(n5745), .B0(n4401), .C0(n4400), .Y(n1925)
);
OAI211XLTS U2587 ( .A0(n4445), .A1(n5735), .B0(n4387), .C0(n4386), .Y(n1935)
);
OAI211XLTS U2588 ( .A0(n4448), .A1(n5716), .B0(n4375), .C0(n4374), .Y(n1916)
);
OAI21XLTS U2589 ( .A0(n5047), .A1(n4652), .B0(n4651), .Y(n1812) );
OAI21XLTS U2590 ( .A0(n5674), .A1(n4306), .B0(n4302), .Y(n1267) );
OAI21XLTS U2591 ( .A0(n5686), .A1(n4274), .B0(n4259), .Y(n1305) );
OAI21XLTS U2592 ( .A0(n5571), .A1(n4304), .B0(n4298), .Y(n1328) );
OAI21XLTS U2593 ( .A0(n5674), .A1(n4274), .B0(n4264), .Y(n1367) );
OAI21XLTS U2594 ( .A0(n5572), .A1(n4274), .B0(n4263), .Y(n1385) );
OAI21XLTS U2595 ( .A0(n5576), .A1(n5174), .B0(n4213), .Y(n1403) );
OAI211XLTS U2596 ( .A0(n4096), .A1(n4098), .B0(n4089), .C0(n4672), .Y(n1693)
);
OAI211XLTS U2597 ( .A0(n4614), .A1(n4646), .B0(n4608), .C0(n4607), .Y(n1803)
);
NAND2X8TS U2598 ( .A(n3891), .B(n3890), .Y(n4016) );
INVX1TS U2599 ( .A(n3889), .Y(n3851) );
NOR2X2TS U2600 ( .A(n3742), .B(n3741), .Y(n4783) );
MX2X1TS U2601 ( .A(FPMULT_P_Sgf[19]), .B(n4720), .S0(n4751), .Y(n1572) );
MX2X1TS U2602 ( .A(FPMULT_P_Sgf[18]), .B(n4716), .S0(n4751), .Y(n1571) );
NOR2X2TS U2603 ( .A(n3773), .B(n3778), .Y(n3571) );
INVX2TS U2604 ( .A(n3743), .Y(n3753) );
OAI211XLTS U2605 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n5133), .B0(
n5138), .C0(n5136), .Y(n5134) );
AOI21X1TS U2606 ( .A0(n3967), .A1(n2507), .B0(n3966), .Y(n3980) );
AO22XLTS U2607 ( .A0(n5148), .A1(n5128), .B0(n5143), .B1(n2333), .Y(n1608)
);
XOR2X1TS U2608 ( .A(n3955), .B(n3945), .Y(n3950) );
INVX1TS U2609 ( .A(n3925), .Y(n3921) );
AO22XLTS U2610 ( .A0(n5148), .A1(n5124), .B0(n5143), .B1(n2332), .Y(n1610)
);
XOR2X1TS U2611 ( .A(n3930), .B(n3920), .Y(n3925) );
XOR2X1TS U2612 ( .A(n3903), .B(n3902), .Y(n3924) );
OAI21XLTS U2613 ( .A0(n5673), .A1(n5175), .B0(n4281), .Y(n1227) );
OAI21XLTS U2614 ( .A0(n5570), .A1(n5175), .B0(n4280), .Y(n1231) );
OAI21XLTS U2615 ( .A0(n5576), .A1(n5175), .B0(n4275), .Y(n1219) );
NAND3BXLTS U2616 ( .AN(FPMULT_Exp_module_Data_S[7]), .B(n5094), .C(n4686),
.Y(n4687) );
OAI21XLTS U2617 ( .A0(n5683), .A1(n5175), .B0(n4276), .Y(n1223) );
OAI21XLTS U2618 ( .A0(n5573), .A1(n4306), .B0(n4292), .Y(n1239) );
OAI21XLTS U2619 ( .A0(n5684), .A1(n5175), .B0(n4279), .Y(n1215) );
OAI21XLTS U2620 ( .A0(n5675), .A1(n4306), .B0(n4291), .Y(n1251) );
OAI21XLTS U2621 ( .A0(n5681), .A1(n5175), .B0(n4278), .Y(n1235) );
OAI21XLTS U2622 ( .A0(n5572), .A1(n4306), .B0(n4294), .Y(n1243) );
OAI21XLTS U2623 ( .A0(n5682), .A1(n4306), .B0(n4277), .Y(n1247) );
NAND2X2TS U2624 ( .A(n3232), .B(n3162), .Y(n3213) );
BUFX3TS U2625 ( .A(n4376), .Y(n4442) );
OAI21XLTS U2626 ( .A0(n5679), .A1(n4306), .B0(n4258), .Y(n1284) );
OAI2BB2X1TS U2627 ( .B0(n5364), .B1(n5366), .A0N(n5608), .A1N(
FPADDSUB_DMP_SFG[10]), .Y(n5371) );
OAI21XLTS U2628 ( .A0(n5679), .A1(n4254), .B0(n4252), .Y(n1286) );
OAI21XLTS U2629 ( .A0(n5678), .A1(n4306), .B0(n4207), .Y(n1291) );
OAI21XLTS U2630 ( .A0(n5671), .A1(n4306), .B0(n4208), .Y(n1255) );
OAI21XLTS U2631 ( .A0(n5575), .A1(n4306), .B0(n4256), .Y(n1263) );
OAI21XLTS U2632 ( .A0(n5577), .A1(n4306), .B0(n4257), .Y(n1211) );
OAI21XLTS U2633 ( .A0(n5680), .A1(n4306), .B0(n4206), .Y(n1259) );
OAI21XLTS U2634 ( .A0(n5574), .A1(n4254), .B0(n4237), .Y(n1273) );
OAI21XLTS U2635 ( .A0(n5689), .A1(n4306), .B0(n4305), .Y(n1277) );
OAI21XLTS U2636 ( .A0(n5689), .A1(n4254), .B0(n4253), .Y(n1279) );
OAI21XLTS U2637 ( .A0(n5678), .A1(n4254), .B0(n4236), .Y(n1293) );
OAI21XLTS U2638 ( .A0(n5690), .A1(n4304), .B0(n4209), .Y(n1298) );
OAI21XLTS U2639 ( .A0(n5690), .A1(n4254), .B0(n4251), .Y(n1300) );
CLKAND2X2TS U2640 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n4113), .Y(n4115)
);
INVX3TS U2641 ( .A(n4255), .Y(n4274) );
INVX1TS U2642 ( .A(n3979), .Y(n3969) );
INVX1TS U2643 ( .A(n3954), .Y(n3944) );
NOR2X2TS U2644 ( .A(n3160), .B(n3159), .Y(n3226) );
OAI21X2TS U2645 ( .A0(n3310), .A1(n3307), .B0(n3308), .Y(n3296) );
NAND2BXLTS U2646 ( .AN(n4931), .B(n4930), .Y(n2125) );
NOR2X2TS U2647 ( .A(n3164), .B(n3163), .Y(n3217) );
INVX3TS U2648 ( .A(n4265), .Y(n5175) );
NAND2BXLTS U2649 ( .AN(FPSENCOS_d_ff3_LUT_out[27]), .B(n4959), .Y(n2115) );
INVX3TS U2650 ( .A(n4973), .Y(n4976) );
INVX3TS U2651 ( .A(n4947), .Y(n4943) );
NAND4BXLTS U2652 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n4107), .C(n4688),
.D(n4106), .Y(n4108) );
INVX3TS U2653 ( .A(n4992), .Y(n4959) );
INVX3TS U2654 ( .A(n4992), .Y(n4988) );
INVX3TS U2655 ( .A(n4992), .Y(n4991) );
INVX3TS U2656 ( .A(n4973), .Y(n4972) );
INVX3TS U2657 ( .A(n4947), .Y(n4949) );
INVX3TS U2658 ( .A(n2445), .Y(n5150) );
ADDHX1TS U2659 ( .A(n3529), .B(n3528), .CO(n3586), .S(n3584) );
INVX3TS U2660 ( .A(n5146), .Y(n5138) );
BUFX3TS U2661 ( .A(n4926), .Y(n4986) );
INVX3TS U2662 ( .A(n4524), .Y(n5049) );
INVX2TS U2663 ( .A(n4043), .Y(n4926) );
OAI21XLTS U2664 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n4083), .Y(n4084) );
BUFX3TS U2665 ( .A(n3179), .Y(n2402) );
XOR2X1TS U2666 ( .A(n2396), .B(FPMULT_Op_MY[20]), .Y(n2538) );
INVX2TS U2667 ( .A(n5718), .Y(n5862) );
INVX2TS U2668 ( .A(n4895), .Y(n4073) );
OAI21XLTS U2669 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[23]), .A1(n5692), .B0(n5439),
.Y(n5440) );
AO22XLTS U2670 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n4898),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
NOR2X4TS U2671 ( .A(operation[1]), .B(n4898), .Y(n4469) );
INVX2TS U2672 ( .A(operation[2]), .Y(n4898) );
XOR2X1TS U2673 ( .A(n3934), .B(n2504), .Y(n3935) );
XOR2X1TS U2674 ( .A(n4025), .B(n2441), .Y(n4026) );
OAI21X2TS U2675 ( .A0(n4776), .A1(n4773), .B0(n4774), .Y(n4771) );
CLKMX2X2TS U2676 ( .A(FPMULT_P_Sgf[20]), .B(n4726), .S0(n4751), .Y(n1573) );
INVX2TS U2677 ( .A(n3859), .Y(n3839) );
NAND2X1TS U2678 ( .A(n3753), .B(n3751), .Y(n3744) );
NAND2X1TS U2679 ( .A(n3726), .B(n3732), .Y(n3727) );
INVX4TS U2680 ( .A(n2228), .Y(n2310) );
INVX2TS U2681 ( .A(n3833), .Y(n3574) );
INVX4TS U2682 ( .A(n2228), .Y(n2311) );
INVX4TS U2683 ( .A(n2229), .Y(n2312) );
XOR2X1TS U2684 ( .A(n3656), .B(n3655), .Y(n3706) );
OR2X2TS U2685 ( .A(n3704), .B(n3703), .Y(n2513) );
OAI21X1TS U2686 ( .A0(n3955), .A1(n3954), .B0(n3953), .Y(n3967) );
XOR2X1TS U2687 ( .A(n3664), .B(n3663), .Y(n3701) );
NAND2X1TS U2688 ( .A(n3654), .B(n3653), .Y(n3655) );
INVX2TS U2689 ( .A(n3697), .Y(DP_OP_453J208_122_681_n459) );
XOR2X1TS U2690 ( .A(n3942), .B(n3933), .Y(n2504) );
OR2X2TS U2691 ( .A(n3699), .B(n3698), .Y(n2497) );
XOR2X1TS U2692 ( .A(n3672), .B(n3671), .Y(n3696) );
INVX2TS U2693 ( .A(n4743), .Y(DP_OP_453J208_122_681_n465) );
AOI21X1TS U2694 ( .A0(n3276), .A1(n3274), .B0(n3267), .Y(n3272) );
INVX2TS U2695 ( .A(n3213), .Y(n3216) );
INVX2TS U2696 ( .A(n3214), .Y(n3215) );
NAND2X1TS U2697 ( .A(n3242), .B(n3241), .Y(n3243) );
NAND2X1TS U2698 ( .A(n3263), .B(n3262), .Y(n3264) );
OAI22X1TS U2699 ( .A0(n2784), .A1(n2797), .B0(n2416), .B1(n2689), .Y(n2623)
);
INVX2TS U2700 ( .A(n3965), .Y(n3966) );
AND2X2TS U2701 ( .A(n2450), .B(n2449), .Y(n2442) );
INVX2TS U2702 ( .A(n3900), .Y(DP_OP_453J208_122_681_n833) );
INVX2TS U2703 ( .A(n3604), .Y(DP_OP_453J208_122_681_n841) );
INVX2TS U2704 ( .A(n3943), .Y(DP_OP_453J208_122_681_n827) );
INVX2TS U2705 ( .A(n3931), .Y(DP_OP_453J208_122_681_n830) );
INVX2TS U2706 ( .A(n3957), .Y(DP_OP_453J208_122_681_n825) );
INVX4TS U2707 ( .A(n4355), .Y(n4995) );
OAI22X1TS U2708 ( .A0(n2775), .A1(n2781), .B0(n2777), .B1(n2783), .Y(n2653)
);
INVX2TS U2709 ( .A(n3607), .Y(DP_OP_453J208_122_681_n840) );
XNOR2X1TS U2710 ( .A(n2832), .B(n2419), .Y(n2791) );
NOR2X4TS U2711 ( .A(n3026), .B(n3025), .Y(n3278) );
NAND2X2TS U2712 ( .A(n3024), .B(n3023), .Y(n3284) );
OAI22X1TS U2713 ( .A0(n2792), .A1(n2798), .B0(n2677), .B1(n2797), .Y(n2673)
);
INVX2TS U2714 ( .A(n3868), .Y(n2816) );
INVX4TS U2715 ( .A(n2307), .Y(n4971) );
AOI21X1TS U2716 ( .A0(n2595), .A1(n2594), .B0(n2593), .Y(n2600) );
AOI21X1TS U2717 ( .A0(n2595), .A1(n2555), .B0(n2554), .Y(n2558) );
XNOR2X1TS U2718 ( .A(n2836), .B(n2419), .Y(n2792) );
ADDHX1TS U2719 ( .A(n2691), .B(n2690), .CO(DP_OP_453J208_122_681_n428), .S(
DP_OP_453J208_122_681_n429) );
AOI21X1TS U2720 ( .A0(n2722), .A1(n2717), .B0(n2716), .Y(n2718) );
XNOR2X1TS U2721 ( .A(n3747), .B(n3746), .Y(n3748) );
AOI21X1TS U2722 ( .A0(n2722), .A1(n2721), .B0(n2720), .Y(n2727) );
OAI21X1TS U2723 ( .A0(n2642), .A1(n2638), .B0(n2639), .Y(n2619) );
NOR2X2TS U2724 ( .A(n4508), .B(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n4533) );
OAI22X1TS U2725 ( .A0(n2561), .A1(n2737), .B0(n2736), .B1(n2739), .Y(
DP_OP_453J208_122_681_n493) );
OAI22X1TS U2726 ( .A0(n3543), .A1(n2304), .B0(n3541), .B1(n3556), .Y(n3550)
);
NAND2XLTS U2727 ( .A(n4021), .B(DP_OP_453J208_122_681_n1748), .Y(n4022) );
OAI22X1TS U2728 ( .A0(n3497), .A1(n2679), .B0(n2678), .B1(n2292), .Y(n3524)
);
BUFX4TS U2729 ( .A(n4029), .Y(n4990) );
AO21X1TS U2730 ( .A0(n2813), .A1(n2414), .B0(n2800), .Y(
DP_OP_453J208_122_681_n556) );
AO21X1TS U2731 ( .A0(n3123), .A1(n2432), .B0(n2461), .Y(n3136) );
INVX3TS U2732 ( .A(n4952), .Y(n5059) );
NAND2X1TS U2733 ( .A(n2591), .B(n2590), .Y(n2592) );
INVX4TS U2734 ( .A(n5152), .Y(n5149) );
OAI22X1TS U2735 ( .A0(n3052), .A1(n2853), .B0(n2844), .B1(n2423), .Y(n2865)
);
NAND2X1TS U2736 ( .A(n2565), .B(n2594), .Y(n2567) );
INVX4TS U2737 ( .A(n4524), .Y(n4623) );
OAI22X1TS U2738 ( .A0(n3482), .A1(n3379), .B0(n2428), .B1(n2395), .Y(n3380)
);
INVX3TS U2739 ( .A(n4952), .Y(n5056) );
NAND4X1TS U2740 ( .A(n5543), .B(n5529), .C(n5597), .D(n4505), .Y(n4502) );
OAI22X1TS U2741 ( .A0(n3180), .A1(DP_OP_453J208_122_681_n1721), .B0(n3179),
.B1(n2877), .Y(n2904) );
NAND2X4TS U2742 ( .A(n2546), .B(n2400), .Y(n3509) );
NAND2X1TS U2743 ( .A(n2721), .B(n2719), .Y(n2569) );
CLKBUFX3TS U2744 ( .A(n2199), .Y(n4952) );
INVX3TS U2745 ( .A(n5069), .Y(n4957) );
INVX2TS U2746 ( .A(n2596), .Y(n2598) );
OAI22X1TS U2747 ( .A0(n3180), .A1(n3074), .B0(n2402), .B1(n3094), .Y(n3085)
);
INVX3TS U2748 ( .A(n5069), .Y(n5070) );
INVX3TS U2749 ( .A(n5523), .Y(n5475) );
OAI22X1TS U2750 ( .A0(n3180), .A1(n2859), .B0(n2402), .B1(n3053), .Y(n3047)
);
NAND2X1TS U2751 ( .A(n2630), .B(n2629), .Y(n2631) );
XNOR2X1TS U2752 ( .A(n2301), .B(FPMULT_Op_MX[6]), .Y(n2890) );
XNOR2X1TS U2753 ( .A(n2297), .B(FPMULT_Op_MX[10]), .Y(n2889) );
NAND2X1TS U2754 ( .A(n2604), .B(n2603), .Y(n2605) );
NAND2X1TS U2755 ( .A(n2635), .B(n2627), .Y(n2530) );
NAND2X1TS U2756 ( .A(n2705), .B(n2704), .Y(n2575) );
INVX2TS U2757 ( .A(n2222), .Y(n2400) );
NAND2X4TS U2758 ( .A(n2538), .B(n2397), .Y(n3465) );
BUFX3TS U2759 ( .A(n4552), .Y(n5295) );
XNOR2X1TS U2760 ( .A(n2301), .B(FPMULT_Op_MX[4]), .Y(n2976) );
NAND2BXLTS U2761 ( .AN(n2393), .B(n2396), .Y(n3464) );
XNOR2X1TS U2762 ( .A(n2607), .B(n2602), .Y(n2606) );
XNOR2X1TS U2763 ( .A(n2437), .B(FPMULT_Op_MX[5]), .Y(n2860) );
XNOR2X1TS U2764 ( .A(n2437), .B(FPMULT_Op_MX[4]), .Y(n2861) );
XNOR2X1TS U2765 ( .A(n2577), .B(n2572), .Y(n2576) );
XNOR2X1TS U2766 ( .A(n2633), .B(n2628), .Y(n2632) );
INVX4TS U2767 ( .A(n5421), .Y(n5453) );
XNOR2X1TS U2768 ( .A(n2700), .B(n2697), .Y(n2699) );
XNOR2X1TS U2769 ( .A(n2437), .B(FPMULT_Op_MX[3]), .Y(n2871) );
INVX4TS U2770 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4552) );
NOR2X1TS U2771 ( .A(n4164), .B(FPADDSUB_intDY_EWSW[10]), .Y(n4165) );
NOR2X1TS U2772 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[7]), .Y(n2527) );
XNOR2X1TS U2773 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[4]), .Y(n3053) );
NOR2X1TS U2774 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[15]), .Y(n2572) );
XOR2X1TS U2775 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .Y(n2577) );
NOR2X1TS U2776 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MX[17]), .Y(n2628) );
XNOR2X1TS U2777 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[3]), .Y(n2859) );
NOR2X1TS U2778 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .Y(n2697) );
XOR2X1TS U2779 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .Y(n2700) );
INVX2TS U2780 ( .A(n2476), .Y(n2393) );
OAI21X1TS U2781 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n5549), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n4172) );
CLKMX2X2TS U2782 ( .A(FPMULT_P_Sgf[41]), .B(n3948), .S0(n4820), .Y(n1594) );
CLKMX2X2TS U2783 ( .A(FPMULT_P_Sgf[44]), .B(n3985), .S0(n4794), .Y(n1597) );
CLKMX2X2TS U2784 ( .A(FPMULT_P_Sgf[39]), .B(n3923), .S0(n4820), .Y(n1592) );
CLKMX2X2TS U2785 ( .A(FPMULT_P_Sgf[45]), .B(n3999), .S0(n4794), .Y(n1598) );
CLKMX2X2TS U2786 ( .A(FPMULT_P_Sgf[42]), .B(n3960), .S0(n4820), .Y(n1595) );
CLKMX2X2TS U2787 ( .A(FPMULT_P_Sgf[46]), .B(n4011), .S0(n4794), .Y(n1599) );
CLKMX2X2TS U2788 ( .A(FPMULT_P_Sgf[38]), .B(n3905), .S0(n4820), .Y(n1591) );
CLKMX2X2TS U2789 ( .A(FPMULT_P_Sgf[43]), .B(n3973), .S0(n4820), .Y(n1596) );
XOR2X1TS U2790 ( .A(n4010), .B(n2500), .Y(n4011) );
CLKMX2X2TS U2791 ( .A(FPMULT_P_Sgf[37]), .B(n3893), .S0(n4820), .Y(n1590) );
CLKMX2X2TS U2792 ( .A(FPMULT_P_Sgf[36]), .B(n3855), .S0(n4820), .Y(n1589) );
CLKMX2X2TS U2793 ( .A(FPMULT_P_Sgf[35]), .B(n3826), .S0(n4820), .Y(n1588) );
CLKMX2X2TS U2794 ( .A(FPMULT_P_Sgf[34]), .B(n4821), .S0(n4820), .Y(n1587) );
CLKMX2X2TS U2795 ( .A(FPMULT_P_Sgf[33]), .B(n4811), .S0(n4820), .Y(n1586) );
CLKMX2X2TS U2796 ( .A(FPMULT_P_Sgf[32]), .B(n4803), .S0(n4820), .Y(n1585) );
CLKMX2X2TS U2797 ( .A(FPMULT_P_Sgf[31]), .B(n4768), .S0(n4794), .Y(n1584) );
CLKMX2X2TS U2798 ( .A(FPMULT_P_Sgf[30]), .B(n4762), .S0(n4794), .Y(n1583) );
CLKMX2X2TS U2799 ( .A(FPMULT_P_Sgf[29]), .B(n4772), .S0(n4794), .Y(n1582) );
CLKMX2X2TS U2800 ( .A(FPMULT_P_Sgf[28]), .B(n4778), .S0(n4794), .Y(n1581) );
CLKMX2X2TS U2801 ( .A(FPMULT_P_Sgf[27]), .B(n4782), .S0(n4794), .Y(n1580) );
CLKMX2X2TS U2802 ( .A(FPMULT_P_Sgf[26]), .B(n4788), .S0(n4794), .Y(n1579) );
CLKMX2X2TS U2803 ( .A(FPMULT_P_Sgf[25]), .B(n4035), .S0(n4794), .Y(n1578) );
CLKMX2X2TS U2804 ( .A(FPMULT_P_Sgf[24]), .B(n4795), .S0(n4794), .Y(n1577) );
CLKMX2X2TS U2805 ( .A(FPMULT_P_Sgf[23]), .B(n4799), .S0(n4820), .Y(n1576) );
CLKMX2X2TS U2806 ( .A(FPMULT_P_Sgf[22]), .B(n4739), .S0(n4751), .Y(n1575) );
CLKMX2X2TS U2807 ( .A(FPMULT_P_Sgf[21]), .B(n4730), .S0(n4751), .Y(n1574) );
NOR2X1TS U2808 ( .A(n4014), .B(n4012), .Y(n4002) );
NOR2X1TS U2809 ( .A(n4013), .B(n4012), .Y(n4003) );
NOR2X1TS U2810 ( .A(n4014), .B(n3937), .Y(n3938) );
NOR2X1TS U2811 ( .A(n4014), .B(n3986), .Y(n3976) );
NOR2X1TS U2812 ( .A(n4014), .B(n3906), .Y(n3907) );
NOR2X1TS U2813 ( .A(n4014), .B(n3962), .Y(n3963) );
NOR2X1TS U2814 ( .A(n4013), .B(n3987), .Y(n3989) );
NOR2X1TS U2815 ( .A(n4013), .B(n3986), .Y(n3977) );
NOR2X1TS U2816 ( .A(n4013), .B(n3906), .Y(n3908) );
NOR2X1TS U2817 ( .A(n4014), .B(n3987), .Y(n3988) );
NOR2X1TS U2818 ( .A(n4013), .B(n3936), .Y(n3927) );
NOR2X1TS U2819 ( .A(n4014), .B(n3961), .Y(n3951) );
NOR2X1TS U2820 ( .A(n4013), .B(n3962), .Y(n3964) );
NOR2X1TS U2821 ( .A(n4014), .B(n3936), .Y(n3926) );
NOR2X1TS U2822 ( .A(n4013), .B(n3937), .Y(n3939) );
NAND2X2TS U2823 ( .A(n3850), .B(n3849), .Y(n3890) );
OR2X2TS U2824 ( .A(n3805), .B(n3804), .Y(n2518) );
NOR2X4TS U2825 ( .A(n3888), .B(n3887), .Y(n4013) );
XOR2X1TS U2826 ( .A(n3758), .B(n3757), .Y(n3765) );
NOR2X4TS U2827 ( .A(n3724), .B(n3723), .Y(n4789) );
OR2X2TS U2828 ( .A(n3730), .B(n2474), .Y(n2443) );
NAND2X2TS U2829 ( .A(n3730), .B(n2474), .Y(n4032) );
OR2X2TS U2830 ( .A(n3714), .B(n3713), .Y(n2453) );
NOR2X2TS U2831 ( .A(n3712), .B(n3711), .Y(n4734) );
INVX4TS U2832 ( .A(n3632), .Y(n3776) );
OR2X2TS U2833 ( .A(n2500), .B(n4012), .Y(n2525) );
OAI21X1TS U2834 ( .A0(n3862), .A1(n3861), .B0(n3860), .Y(n3863) );
OAI21X1TS U2835 ( .A0(n3808), .A1(n3576), .B0(n3575), .Y(n3577) );
NOR2X1TS U2836 ( .A(n3859), .B(n3861), .Y(n3864) );
NOR2X1TS U2837 ( .A(n3807), .B(n3576), .Y(n3578) );
OAI21X1TS U2838 ( .A0(n3774), .A1(n3773), .B0(n3772), .Y(n3775) );
AOI2BB1X1TS U2839 ( .A0N(n5148), .A1N(FPMULT_FSM_add_overflow_flag), .B0(
n5147), .Y(n1600) );
OAI21X1TS U2840 ( .A0(n3808), .A1(n3827), .B0(n3833), .Y(n3809) );
NOR2X1TS U2841 ( .A(n3770), .B(n3773), .Y(n3777) );
NOR2X1TS U2842 ( .A(n3807), .B(n3827), .Y(n3810) );
AO21X1TS U2843 ( .A0(FPMULT_Add_result[22]), .A1(n5143), .B0(n5142), .Y(
n1602) );
OAI211X1TS U2844 ( .A0(n4587), .A1(n4648), .B0(n4572), .C0(n4571), .Y(n1800)
);
OAI211X1TS U2845 ( .A0(n4624), .A1(n4648), .B0(n4601), .C0(n4600), .Y(n1810)
);
NAND3X1TS U2846 ( .A(n5054), .B(n5053), .C(n5052), .Y(n1789) );
OAI211X1TS U2847 ( .A0(n4649), .A1(n4646), .B0(n4643), .C0(n4642), .Y(n1811)
);
OAI21X1TS U2848 ( .A0(n4647), .A1(n4648), .B0(n4548), .Y(n1813) );
OAI211X1TS U2849 ( .A0(n4624), .A1(n4646), .B0(n4605), .C0(n4604), .Y(n1809)
);
OAI211X1TS U2850 ( .A0(n4587), .A1(n4646), .B0(n4586), .C0(n4585), .Y(n1799)
);
OAI211X1TS U2851 ( .A0(n4564), .A1(n4646), .B0(n4557), .C0(n4556), .Y(n1791)
);
OAI211X1TS U2852 ( .A0(n4639), .A1(n4648), .B0(n4633), .C0(n4632), .Y(n1806)
);
OAI211X1TS U2853 ( .A0(n4614), .A1(n4648), .B0(n4613), .C0(n4612), .Y(n1804)
);
OAI211X1TS U2854 ( .A0(n4582), .A1(n4648), .B0(n4568), .C0(n4567), .Y(n1798)
);
OAI211X1TS U2855 ( .A0(n4598), .A1(n4648), .B0(n4597), .C0(n4596), .Y(n1794)
);
XOR2X1TS U2856 ( .A(n4006), .B(n3996), .Y(n4001) );
OAI211X1TS U2857 ( .A0(n4639), .A1(n4646), .B0(n4638), .C0(n4637), .Y(n1805)
);
OAI211X1TS U2858 ( .A0(n4564), .A1(n4648), .B0(n4563), .C0(n4562), .Y(n1792)
);
OAI211X1TS U2859 ( .A0(n4588), .A1(n4648), .B0(n4575), .C0(n4574), .Y(n1796)
);
OAI21X1TS U2860 ( .A0(n3834), .A1(n3833), .B0(n3832), .Y(n3835) );
OAI211X1TS U2861 ( .A0(n4622), .A1(n4648), .B0(n4616), .C0(n4615), .Y(n1802)
);
OAI211X1TS U2862 ( .A0(n4630), .A1(n4648), .B0(n4629), .C0(n4628), .Y(n1808)
);
OAI211X1TS U2863 ( .A0(n4630), .A1(n4646), .B0(n4626), .C0(n4625), .Y(n1807)
);
NOR2X2TS U2864 ( .A(n3707), .B(n3706), .Y(n4721) );
NOR2X2TS U2865 ( .A(n3622), .B(n3620), .Y(n3828) );
OAI211X1TS U2866 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n5139), .B0(
n5138), .C0(n5141), .Y(n5140) );
AOI21X1TS U2867 ( .A0(n3992), .A1(n2509), .B0(n3991), .Y(n4006) );
AO22X1TS U2868 ( .A0(n5148), .A1(n5137), .B0(n5143), .B1(
FPMULT_Add_result[20]), .Y(n1604) );
XOR2X1TS U2869 ( .A(n3992), .B(n3983), .Y(n2508) );
AOI2BB2X1TS U2870 ( .B0(n5453), .B1(n5415), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[19]), .A1N(n5414), .Y(n1323) );
OAI21X2TS U2871 ( .A0(n3656), .A1(n3652), .B0(n3653), .Y(n3641) );
OAI21X1TS U2872 ( .A0(n3980), .A1(n3979), .B0(n3978), .Y(n3992) );
NOR2X1TS U2873 ( .A(n3642), .B(n3647), .Y(n3564) );
AO22X1TS U2874 ( .A0(n5148), .A1(n5132), .B0(n5143), .B1(
FPMULT_Add_result[18]), .Y(n1606) );
OAI21X1TS U2875 ( .A0(n3642), .A1(n3648), .B0(n3643), .Y(n3563) );
OR2X2TS U2876 ( .A(DP_OP_453J208_122_681_n362), .B(
DP_OP_453J208_122_681_n374), .Y(n2515) );
OR2X2TS U2877 ( .A(DP_OP_453J208_122_681_n253), .B(
DP_OP_453J208_122_681_n246), .Y(n2519) );
OR2X2TS U2878 ( .A(n4551), .B(n4652), .Y(n2228) );
NOR2X6TS U2879 ( .A(n4551), .B(n5046), .Y(n4554) );
XOR2X1TS U2880 ( .A(n3967), .B(n3958), .Y(n2506) );
AOI21X1TS U2881 ( .A0(n3942), .A1(n2505), .B0(n3941), .Y(n3955) );
OR2X2TS U2882 ( .A(DP_OP_453J208_122_681_n234), .B(n3874), .Y(n2520) );
OAI21X1TS U2883 ( .A0(n4513), .A1(n4910), .B0(n4512), .Y(n1324) );
XOR2X2TS U2884 ( .A(n3265), .B(n3264), .Y(n3689) );
OAI21X1TS U2885 ( .A0(n4501), .A1(n4524), .B0(n4499), .Y(n2079) );
OAI21X1TS U2886 ( .A0(n4910), .A1(n4501), .B0(n4500), .Y(n1320) );
CLKXOR2X2TS U2887 ( .A(n3212), .B(n3211), .Y(n3707) );
OAI21X1TS U2888 ( .A0(n4526), .A1(n4910), .B0(n4523), .Y(n1332) );
XOR2X2TS U2889 ( .A(n3244), .B(n3243), .Y(n3697) );
OAI21X1TS U2890 ( .A0(n4526), .A1(n4524), .B0(n4525), .Y(n2077) );
OAI21X1TS U2891 ( .A0(n4513), .A1(n4524), .B0(n4511), .Y(n2078) );
XNOR2X2TS U2892 ( .A(n3276), .B(n3275), .Y(n4744) );
AOI21X1TS U2893 ( .A0(n2524), .A1(n3917), .B0(n2523), .Y(n3930) );
OAI21X2TS U2894 ( .A0(n3668), .A1(n3671), .B0(n3669), .Y(n3666) );
XNOR2X1TS U2895 ( .A(n3821), .B(n3820), .Y(n3822) );
XNOR2X1TS U2896 ( .A(n3917), .B(n3610), .Y(n3611) );
OAI211X1TS U2897 ( .A0(n4445), .A1(n5731), .B0(n4429), .C0(n4428), .Y(n1939)
);
OAI211X1TS U2898 ( .A0(n4456), .A1(n5743), .B0(n4437), .C0(n4436), .Y(n1927)
);
OAI211X1TS U2899 ( .A0(n4445), .A1(n5734), .B0(n4433), .C0(n4432), .Y(n1936)
);
OAI211X1TS U2900 ( .A0(n4445), .A1(n5776), .B0(n4444), .C0(n4443), .Y(n1819)
);
OAI211X1TS U2901 ( .A0(n4445), .A1(n5732), .B0(n4431), .C0(n4430), .Y(n1938)
);
OAI211X1TS U2902 ( .A0(n4448), .A1(n5769), .B0(n4415), .C0(n4414), .Y(n1837)
);
OAI211X1TS U2903 ( .A0(n4456), .A1(n5746), .B0(n4397), .C0(n4396), .Y(n1924)
);
OAI211X1TS U2904 ( .A0(n4448), .A1(n5721), .B0(n4423), .C0(n4422), .Y(n1918)
);
OAI211X1TS U2905 ( .A0(n4456), .A1(n5567), .B0(n4441), .C0(n4440), .Y(n1920)
);
OAI211X1TS U2906 ( .A0(n4456), .A1(n5741), .B0(n4411), .C0(n4410), .Y(n1929)
);
OAI211X1TS U2907 ( .A0(n4448), .A1(n5775), .B0(n4447), .C0(n4446), .Y(n1820)
);
OAI211X1TS U2908 ( .A0(n4445), .A1(n5772), .B0(n4382), .C0(n4381), .Y(n1833)
);
OAI211X1TS U2909 ( .A0(n4456), .A1(n5747), .B0(n4407), .C0(n4406), .Y(n1923)
);
OAI211X1TS U2910 ( .A0(n4456), .A1(n5748), .B0(n4384), .C0(n4383), .Y(n1922)
);
OAI211X1TS U2911 ( .A0(n4448), .A1(n5770), .B0(n4378), .C0(n4377), .Y(n1836)
);
OAI211X1TS U2912 ( .A0(n4456), .A1(n5740), .B0(n4409), .C0(n4408), .Y(n1930)
);
OAI21X1TS U2913 ( .A0(n4311), .A1(n4312), .B0(n4310), .Y(n1697) );
OAI211X1TS U2914 ( .A0(n4456), .A1(n5742), .B0(n4403), .C0(n4402), .Y(n1928)
);
OAI211X1TS U2915 ( .A0(n4445), .A1(n5733), .B0(n4427), .C0(n4426), .Y(n1937)
);
OAI211X1TS U2916 ( .A0(n4456), .A1(n5744), .B0(n4399), .C0(n4398), .Y(n1926)
);
OAI211X1TS U2917 ( .A0(n4456), .A1(n5773), .B0(n4450), .C0(n4449), .Y(n1824)
);
OAI211X1TS U2918 ( .A0(n4456), .A1(n5760), .B0(n4455), .C0(n4454), .Y(n1822)
);
NAND3X1TS U2919 ( .A(n5038), .B(n5037), .C(n5040), .Y(n1817) );
INVX1TS U2920 ( .A(n4519), .Y(n4510) );
OAI211X1TS U2921 ( .A0(n4456), .A1(n5774), .B0(n4452), .C0(n4451), .Y(n1821)
);
OAI21X1TS U2922 ( .A0(n3843), .A1(n3878), .B0(n3880), .Y(n3848) );
XNOR2X1TS U2923 ( .A(n3675), .B(n3674), .Y(n3693) );
NAND3X1TS U2924 ( .A(n5014), .B(n5013), .C(n5012), .Y(n1829) );
OAI211X1TS U2925 ( .A0(n4445), .A1(n5771), .B0(n4380), .C0(n4379), .Y(n1835)
);
NAND3X1TS U2926 ( .A(n5035), .B(n5034), .C(n5040), .Y(n1818) );
NAND3X1TS U2927 ( .A(n5042), .B(n5041), .C(n5040), .Y(n1816) );
NAND3X1TS U2928 ( .A(n5016), .B(n5015), .C(n5026), .Y(n1828) );
NAND3X1TS U2929 ( .A(n5004), .B(n5003), .C(n5002), .Y(n1834) );
OAI211X1TS U2930 ( .A0(n4456), .A1(n5749), .B0(n4413), .C0(n4412), .Y(n1921)
);
NAND3X1TS U2931 ( .A(n5023), .B(n5022), .C(n5029), .Y(n1826) );
NAND3X1TS U2932 ( .A(n5001), .B(n5000), .C(n5002), .Y(n1838) );
NAND3X1TS U2933 ( .A(n5028), .B(n5027), .C(n5026), .Y(n1825) );
NAND3X1TS U2934 ( .A(n5011), .B(n5010), .C(n5026), .Y(n1830) );
NAND3X1TS U2935 ( .A(n5031), .B(n5030), .C(n5029), .Y(n1823) );
NAND3X1TS U2936 ( .A(n5006), .B(n5005), .C(n5017), .Y(n1832) );
NAND3X1TS U2937 ( .A(n5009), .B(n5008), .C(n5007), .Y(n1831) );
NAND3X1TS U2938 ( .A(n5019), .B(n5018), .C(n5017), .Y(n1827) );
OAI21X1TS U2939 ( .A0(n3214), .A1(n3200), .B0(n3199), .Y(n3201) );
OAI211X1TS U2940 ( .A0(n4448), .A1(n2247), .B0(n4369), .C0(n4368), .Y(n1915)
);
OAI211X1TS U2941 ( .A0(n4445), .A1(n5736), .B0(n4389), .C0(n4388), .Y(n1934)
);
OAI211X1TS U2942 ( .A0(n4445), .A1(n5728), .B0(n4395), .C0(n4394), .Y(n1942)
);
OAI211X1TS U2943 ( .A0(n4448), .A1(n5767), .B0(n4361), .C0(n4360), .Y(n1841)
);
OAI211X1TS U2944 ( .A0(n4448), .A1(n5766), .B0(n4359), .C0(n4358), .Y(n1843)
);
OAI211X1TS U2945 ( .A0(n4448), .A1(n5765), .B0(n4365), .C0(n4364), .Y(n1844)
);
NAND3X1TS U2946 ( .A(n4998), .B(n4997), .C(n5007), .Y(n1840) );
NOR2X1TS U2947 ( .A(n3213), .B(n3173), .Y(n3175) );
NOR2X1TS U2948 ( .A(n3222), .B(n3233), .Y(n3225) );
OAI211X1TS U2949 ( .A0(n4445), .A1(n5738), .B0(n4405), .C0(n4404), .Y(n1932)
);
OAI21X1TS U2950 ( .A0(n3214), .A1(n3173), .B0(n3172), .Y(n3174) );
NAND3X1TS U2951 ( .A(n4994), .B(n4993), .C(n5012), .Y(n1842) );
NOR2X1TS U2952 ( .A(n3213), .B(n3200), .Y(n3202) );
OAI211X1TS U2953 ( .A0(n4445), .A1(n5727), .B0(n4421), .C0(n4420), .Y(n1943)
);
NOR2X1TS U2954 ( .A(n3213), .B(n3217), .Y(n3207) );
XOR2X1TS U2955 ( .A(n3679), .B(n2472), .Y(n3691) );
OAI21X1TS U2956 ( .A0(n3897), .A1(n3909), .B0(n3912), .Y(n3898) );
OAI211X1TS U2957 ( .A0(n4448), .A1(n5722), .B0(n4371), .C0(n4370), .Y(n1917)
);
OAI211X1TS U2958 ( .A0(n4445), .A1(n5730), .B0(n4417), .C0(n4416), .Y(n1940)
);
OAI211X1TS U2959 ( .A0(n4456), .A1(n5739), .B0(n4391), .C0(n4390), .Y(n1931)
);
NOR2X1TS U2960 ( .A(n3213), .B(n3191), .Y(n3193) );
OAI21X1TS U2961 ( .A0(n4116), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n5189),
.Y(n4117) );
OAI211X1TS U2962 ( .A0(n4448), .A1(n5717), .B0(n4367), .C0(n4366), .Y(n1913)
);
AOI21X1TS U2963 ( .A0(n3617), .A1(n3606), .B0(n3605), .Y(n3843) );
OAI21X1TS U2964 ( .A0(n3214), .A1(n3191), .B0(n3190), .Y(n3192) );
NOR2X1TS U2965 ( .A(n3896), .B(n3909), .Y(n3899) );
OAI211X1TS U2966 ( .A0(n4445), .A1(n5729), .B0(n4393), .C0(n4392), .Y(n1941)
);
OAI211X1TS U2967 ( .A0(n4448), .A1(n5715), .B0(n4373), .C0(n4372), .Y(n1914)
);
NAND2X4TS U2968 ( .A(n5189), .B(n5188), .Y(n5190) );
AO21X1TS U2969 ( .A0(n3916), .A1(n3915), .B0(n3914), .Y(n2523) );
OAI21X1TS U2970 ( .A0(n3306), .A1(n3302), .B0(n3303), .Y(n3301) );
NOR2X1TS U2971 ( .A(n5188), .B(n5718), .Y(n5176) );
INVX1TS U2972 ( .A(n3915), .Y(n3897) );
AOI21X2TS U2973 ( .A0(n3038), .A1(n3259), .B0(n3037), .Y(n3039) );
NAND2X1TS U2974 ( .A(n3270), .B(n3269), .Y(n3271) );
NAND2X1TS U2975 ( .A(n3246), .B(n3245), .Y(n3247) );
OAI21X1TS U2976 ( .A0(n5571), .A1(n4274), .B0(n4273), .Y(n1330) );
OAI21X1TS U2977 ( .A0(n5575), .A1(n4274), .B0(n4267), .Y(n1370) );
OAI21X1TS U2978 ( .A0(n5577), .A1(n5174), .B0(n4216), .Y(n1409) );
AOI21X1TS U2979 ( .A0(n3198), .A1(n2450), .B0(n3189), .Y(n3190) );
OAI21X1TS U2980 ( .A0(n5698), .A1(n4274), .B0(n4262), .Y(n1307) );
AO21X1TS U2981 ( .A0(n3189), .A1(n2449), .B0(n3171), .Y(n2465) );
OAI21X1TS U2982 ( .A0(n5573), .A1(n4274), .B0(n4261), .Y(n1388) );
AOI21X2TS U2983 ( .A0(n2488), .A1(n3289), .B0(n3002), .Y(n3003) );
OAI21X1TS U2984 ( .A0(n5683), .A1(n5174), .B0(n4215), .Y(n1400) );
OAI21X1TS U2985 ( .A0(n5672), .A1(n4274), .B0(n4270), .Y(n1314) );
OAI21X1TS U2986 ( .A0(n5680), .A1(n4274), .B0(n4268), .Y(n1373) );
OAI21X1TS U2987 ( .A0(n5684), .A1(n5174), .B0(n4217), .Y(n1406) );
OAI21X1TS U2988 ( .A0(n5671), .A1(n4274), .B0(n4271), .Y(n1376) );
OAI21X1TS U2989 ( .A0(n5673), .A1(n5174), .B0(n4219), .Y(n1397) );
INVX2TS U2990 ( .A(n3198), .Y(n3199) );
OAI21X1TS U2991 ( .A0(n5675), .A1(n4274), .B0(n4260), .Y(n1379) );
OAI21X1TS U2992 ( .A0(n5682), .A1(n4274), .B0(n4266), .Y(n1382) );
OAI21X1TS U2993 ( .A0(n5570), .A1(n5174), .B0(n4218), .Y(n1394) );
OAI21X1TS U2994 ( .A0(n5681), .A1(n4274), .B0(n4269), .Y(n1391) );
OAI21X1TS U2995 ( .A0(n3913), .A1(n3912), .B0(n3911), .Y(n3914) );
OAI21X1TS U2996 ( .A0(n5677), .A1(n5174), .B0(n4214), .Y(n1415) );
OAI21X1TS U2997 ( .A0(n3785), .A1(n3784), .B0(n3783), .Y(n3790) );
OAI21X1TS U2998 ( .A0(n3234), .A1(n3226), .B0(n3227), .Y(n3161) );
INVX2TS U2999 ( .A(n3296), .Y(n3306) );
INVX2TS U3000 ( .A(n3290), .Y(n3002) );
NOR2X2TS U3001 ( .A(n3883), .B(n3882), .Y(n3909) );
OAI21X1TS U3002 ( .A0(n5696), .A1(n4304), .B0(n4300), .Y(n1462) );
XNOR2X1TS U3003 ( .A(n2816), .B(n2415), .Y(n2821) );
OAI21X1TS U3004 ( .A0(n5574), .A1(n4306), .B0(n4297), .Y(n1271) );
OAI21X1TS U3005 ( .A0(n5672), .A1(n4304), .B0(n4303), .Y(n1312) );
INVX2TS U3006 ( .A(n3918), .Y(DP_OP_453J208_122_681_n831) );
AO21X1TS U3007 ( .A0(n5534), .A1(n5564), .B0(n4514), .Y(n4515) );
OAI21X1TS U3008 ( .A0(n5677), .A1(n5175), .B0(n4301), .Y(n1463) );
INVX2TS U3009 ( .A(n3956), .Y(DP_OP_453J208_122_681_n826) );
OR2X2TS U3010 ( .A(n3957), .B(n3956), .Y(n2507) );
XNOR2X1TS U3011 ( .A(n2822), .B(n2415), .Y(n2825) );
XNOR2X1TS U3012 ( .A(n2830), .B(n2425), .Y(n2746) );
INVX2TS U3013 ( .A(n3608), .Y(DP_OP_453J208_122_681_n839) );
XNOR2X1TS U3014 ( .A(n2830), .B(n2424), .Y(n2776) );
XNOR2X1TS U3015 ( .A(n2826), .B(n2419), .Y(n2788) );
XNOR2X1TS U3016 ( .A(n2828), .B(n2424), .Y(n2774) );
XNOR2X1TS U3017 ( .A(n2816), .B(n2419), .Y(n2784) );
OAI21X1TS U3018 ( .A0(n5695), .A1(n4304), .B0(n4296), .Y(n1460) );
OAI21X2TS U3019 ( .A0(n3208), .A1(n3218), .B0(n3209), .Y(n3198) );
OAI21X1TS U3020 ( .A0(n5578), .A1(n4304), .B0(n4295), .Y(n1461) );
XNOR2X1TS U3021 ( .A(n2822), .B(n2419), .Y(n2786) );
INVX2TS U3022 ( .A(n3883), .Y(DP_OP_453J208_122_681_n835) );
AOI21X1TS U3023 ( .A0(n3593), .A1(n3636), .B0(n3592), .Y(n3627) );
XNOR2X1TS U3024 ( .A(n2828), .B(n2425), .Y(n2745) );
XNOR2X1TS U3025 ( .A(n2820), .B(n2415), .Y(n2823) );
XNOR2X1TS U3026 ( .A(n2828), .B(n2419), .Y(n2789) );
INVX2TS U3027 ( .A(n3844), .Y(DP_OP_453J208_122_681_n838) );
XNOR2X1TS U3028 ( .A(n2822), .B(n2417), .Y(n2803) );
NOR2X1TS U3029 ( .A(n3868), .B(n2561), .Y(n3871) );
NOR2X2TS U3030 ( .A(n3166), .B(n3165), .Y(n3208) );
XNOR2X1TS U3031 ( .A(n2824), .B(n2415), .Y(n2827) );
XNOR2X1TS U3032 ( .A(n2834), .B(n2426), .Y(n2766) );
XNOR2X1TS U3033 ( .A(n2832), .B(n2426), .Y(n2763) );
NAND2BX1TS U3034 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(n4109), .Y(n4110)
);
OAI21XLTS U3035 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n4942), .B0(n4078),
.Y(n2116) );
INVX2TS U3036 ( .A(n3603), .Y(DP_OP_453J208_122_681_n842) );
OAI21XLTS U3037 ( .A0(n5568), .A1(n4933), .B0(n4102), .Y(n2118) );
NAND3X1TS U3038 ( .A(n4518), .B(n5547), .C(n5531), .Y(n4514) );
CLKXOR2X2TS U3039 ( .A(n2718), .B(FPMULT_Op_MY[11]), .Y(n2820) );
NAND3X1TS U3040 ( .A(FPSENCOS_cont_var_out[1]), .B(n3536), .C(n5705), .Y(
n4355) );
OR2X2TS U3041 ( .A(n3595), .B(n3594), .Y(n2510) );
XNOR2X1TS U3042 ( .A(n2824), .B(n2417), .Y(n2804) );
XNOR2X1TS U3043 ( .A(n2834), .B(n2424), .Y(n2777) );
XNOR2X1TS U3044 ( .A(n2832), .B(n2424), .Y(n2775) );
XNOR2X1TS U3045 ( .A(n2824), .B(n2419), .Y(n2787) );
BUFX4TS U3046 ( .A(n4128), .Y(n4211) );
INVX4TS U3047 ( .A(n2306), .Y(n2307) );
XNOR2X1TS U3048 ( .A(n2832), .B(n2425), .Y(n2747) );
NAND2X1TS U3049 ( .A(n3168), .B(n3167), .Y(n3203) );
XNOR2X1TS U3050 ( .A(n2836), .B(n2424), .Y(n2779) );
NOR2X4TS U3051 ( .A(operation[1]), .B(n3535), .Y(n5025) );
NAND3X1TS U3052 ( .A(n4533), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n5547),
.Y(n4534) );
OAI21XLTS U3053 ( .A0(n4932), .A1(n4940), .B0(n4074), .Y(n2119) );
OAI21X1TS U3054 ( .A0(n4121), .A1(n4120), .B0(n4119), .Y(n2151) );
OR2X2TS U3055 ( .A(n3170), .B(n3169), .Y(n2449) );
OAI31X1TS U3056 ( .A0(n4919), .A1(FPSENCOS_cont_var_out[1]), .A2(n5705),
.B0(n4653), .Y(n2138) );
XNOR2X1TS U3057 ( .A(n2836), .B(n2425), .Y(n2750) );
AOI21X2TS U3058 ( .A0(n2722), .A1(n2717), .B0(n2498), .Y(n3868) );
OAI211XLTS U3059 ( .A0(n4807), .A1(n2516), .B0(n4806), .C0(n4805), .Y(n4808)
);
NAND2X2TS U3060 ( .A(n4123), .B(n4990), .Y(n4122) );
ADDFHX2TS U3061 ( .A(n2905), .B(n2904), .CI(n2903), .CO(n2897), .S(n2919) );
NOR2X6TS U3062 ( .A(rst), .B(n4914), .Y(n4045) );
NAND3BX1TS U3063 ( .AN(n4185), .B(n4183), .C(n4182), .Y(n4203) );
XNOR2X1TS U3064 ( .A(n2425), .B(n2838), .Y(n2751) );
OAI221X2TS U3065 ( .A0(n5049), .A1(n2227), .B0(n4524), .B1(n5697), .C0(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4644) );
NOR2X1TS U3066 ( .A(n4671), .B(n4135), .Y(n1694) );
NAND3X1TS U3067 ( .A(n4673), .B(n4679), .C(n4672), .Y(n1692) );
OAI211X1TS U3068 ( .A0(n4679), .A1(n5759), .B0(n4855), .C0(n4139), .Y(n1695)
);
OR4X4TS U3069 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .C(underflow_flag_mult), .D(n5149), .Y(
n2445) );
AO21X1TS U3070 ( .A0(n3141), .A1(n2434), .B0(DP_OP_453J208_122_681_n1722),
.Y(n3148) );
NOR2X4TS U3071 ( .A(n4820), .B(n5094), .Y(n4677) );
AO21X1TS U3072 ( .A0(n2753), .A1(n2421), .B0(n3857), .Y(n3866) );
OAI22X1TS U3073 ( .A0(n3141), .A1(n3132), .B0(n2434), .B1(
DP_OP_453J208_122_681_n1722), .Y(n3143) );
AO21X1TS U3074 ( .A0(n2764), .A1(n2420), .B0(n2754), .Y(n2542) );
AO21X1TS U3075 ( .A0(n2783), .A1(n2418), .B0(n2768), .Y(
DP_OP_453J208_122_681_n526) );
AOI211X1TS U3076 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(n4671), .B0(n5094), .C0(n5152), .Y(n4673) );
AO21X1TS U3077 ( .A0(n2797), .A1(n2416), .B0(n2689), .Y(n2613) );
NOR2X4TS U3078 ( .A(FPMULT_FSM_selector_C), .B(n4053), .Y(n4070) );
OR2X1TS U3079 ( .A(n5688), .B(n4053), .Y(n2235) );
NOR2XLTS U3080 ( .A(n5467), .B(n5186), .Y(n5228) );
NOR2XLTS U3081 ( .A(n2317), .B(n5186), .Y(n5206) );
NOR2XLTS U3082 ( .A(n5459), .B(n5186), .Y(n5203) );
NOR2XLTS U3083 ( .A(n5217), .B(n5186), .Y(n5215) );
NOR2BX1TS U3084 ( .AN(n2304), .B(n2739), .Y(DP_OP_453J208_122_681_n495) );
NOR2X1TS U3085 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n4107) );
NOR2XLTS U3086 ( .A(n5462), .B(n5186), .Y(n5212) );
NOR2XLTS U3087 ( .A(n5459), .B(n5216), .Y(n5460) );
NOR2XLTS U3088 ( .A(n5462), .B(n5216), .Y(n5463) );
NAND2BXLTS U3089 ( .AN(n2304), .B(n2425), .Y(n2626) );
NOR2BX1TS U3090 ( .AN(n2304), .B(n3858), .Y(n2662) );
NOR2XLTS U3091 ( .A(n2318), .B(n5216), .Y(n5407) );
NAND2BXLTS U3092 ( .AN(n2304), .B(n2426), .Y(n2658) );
CLKINVX3TS U3093 ( .A(n2240), .Y(n2387) );
OAI22X1TS U3094 ( .A0(n3180), .A1(n2876), .B0(n2402), .B1(n2875), .Y(n2905)
);
NOR2XLTS U3095 ( .A(n2318), .B(n5186), .Y(n5199) );
INVX2TS U3096 ( .A(n2415), .Y(DP_OP_453J208_122_681_n571) );
NOR2XLTS U3097 ( .A(n5486), .B(n5186), .Y(n5187) );
NOR2XLTS U3098 ( .A(n5484), .B(n5186), .Y(n5244) );
NOR2XLTS U3099 ( .A(n5220), .B(n5186), .Y(n5194) );
NAND2BXLTS U3100 ( .AN(n2303), .B(n2419), .Y(n2688) );
XNOR2X2TS U3101 ( .A(n3856), .B(FPMULT_Op_MX[22]), .Y(
DP_OP_453J208_122_681_n1748) );
OR2X2TS U3102 ( .A(n3856), .B(FPMULT_Op_MX[22]), .Y(n3869) );
NAND2BXLTS U3103 ( .AN(n2304), .B(n2424), .Y(n2667) );
NOR2XLTS U3104 ( .A(n2317), .B(n5216), .Y(n5454) );
NAND2X1TS U3105 ( .A(n2640), .B(n2639), .Y(n2641) );
AOI21X2TS U3106 ( .A0(n2484), .A1(n2649), .B0(n2549), .Y(n2647) );
OAI21XLTS U3107 ( .A0(n4491), .A1(n5669), .B0(n4490), .Y(op_result[24]) );
OAI21XLTS U3108 ( .A0(n4491), .A1(n5644), .B0(n4489), .Y(op_result[22]) );
OAI21XLTS U3109 ( .A0(n4491), .A1(n5647), .B0(n4471), .Y(op_result[21]) );
OAI21XLTS U3110 ( .A0(n4491), .A1(n5566), .B0(n4459), .Y(op_result[31]) );
OAI21XLTS U3111 ( .A0(n4491), .A1(n5667), .B0(n4480), .Y(op_result[28]) );
OAI21XLTS U3112 ( .A0(n4491), .A1(n5668), .B0(n4466), .Y(op_result[27]) );
OAI21XLTS U3113 ( .A0(n4491), .A1(n5670), .B0(n4467), .Y(op_result[26]) );
OAI21XLTS U3114 ( .A0(n4491), .A1(n5649), .B0(n4484), .Y(op_result[20]) );
OAI21XLTS U3115 ( .A0(n4491), .A1(n5648), .B0(n4483), .Y(op_result[19]) );
NOR2X2TS U3116 ( .A(n2583), .B(n2585), .Y(n2594) );
AND2X2TS U3117 ( .A(n3412), .B(n2422), .Y(n3856) );
NOR2XLTS U3118 ( .A(n5467), .B(n5216), .Y(n5469) );
OR2X2TS U3119 ( .A(n2716), .B(FPMULT_Op_MY[11]), .Y(n2498) );
OR2X4TS U3120 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n5295), .Y(n4524) );
OR2X1TS U3121 ( .A(n5097), .B(n5688), .Y(n2240) );
NOR2XLTS U3122 ( .A(n5484), .B(n5216), .Y(n5456) );
OAI22X1TS U3123 ( .A0(n3465), .A1(n3463), .B0(n3462), .B1(n2397), .Y(n3488)
);
OAI22X1TS U3124 ( .A0(n3465), .A1(n2499), .B0(n3464), .B1(n2397), .Y(n3487)
);
NOR2XLTS U3125 ( .A(n5220), .B(n5216), .Y(n5221) );
NOR2BX1TS U3126 ( .AN(n2393), .B(n2400), .Y(n3512) );
NOR2XLTS U3127 ( .A(n5217), .B(n5216), .Y(n5218) );
NAND2X4TS U3128 ( .A(n2819), .B(n3556), .Y(n3543) );
OAI211X1TS U3129 ( .A0(n4144), .A1(n4200), .B0(n4143), .C0(n4142), .Y(n4149)
);
OAI21XLTS U3130 ( .A0(n4491), .A1(n5661), .B0(n4460), .Y(op_result[2]) );
OAI21XLTS U3131 ( .A0(n4457), .A1(n5645), .B0(n4473), .Y(op_result[15]) );
OAI21XLTS U3132 ( .A0(n4457), .A1(n5664), .B0(n4464), .Y(op_result[1]) );
OAI21XLTS U3133 ( .A0(n4491), .A1(n5663), .B0(n4465), .Y(op_result[0]) );
OAI21XLTS U3134 ( .A0(n4491), .A1(n5654), .B0(n4472), .Y(op_result[16]) );
OAI21XLTS U3135 ( .A0(n4491), .A1(n5650), .B0(n4470), .Y(op_result[17]) );
OAI21XLTS U3136 ( .A0(n4457), .A1(n5659), .B0(n4476), .Y(op_result[12]) );
OAI21XLTS U3137 ( .A0(n4457), .A1(n5656), .B0(n4477), .Y(op_result[11]) );
OAI21XLTS U3138 ( .A0(n4457), .A1(n5658), .B0(n4478), .Y(op_result[10]) );
OAI21XLTS U3139 ( .A0(n4457), .A1(n5665), .B0(n4488), .Y(op_result[9]) );
OAI21XLTS U3140 ( .A0(n4457), .A1(n5655), .B0(n4481), .Y(op_result[8]) );
OAI21XLTS U3141 ( .A0(n4457), .A1(n5653), .B0(n4475), .Y(op_result[13]) );
OAI21XLTS U3142 ( .A0(n4457), .A1(n5662), .B0(n4479), .Y(op_result[7]) );
OAI21XLTS U3143 ( .A0(n4457), .A1(n5652), .B0(n4485), .Y(op_result[6]) );
OAI21XLTS U3144 ( .A0(n4491), .A1(n5666), .B0(n4461), .Y(op_result[5]) );
OAI21XLTS U3145 ( .A0(n4457), .A1(n5651), .B0(n4462), .Y(op_result[4]) );
OAI21XLTS U3146 ( .A0(n4457), .A1(n5657), .B0(n4474), .Y(op_result[14]) );
OAI21XLTS U3147 ( .A0(n4457), .A1(n5660), .B0(n4463), .Y(op_result[3]) );
OAI21XLTS U3148 ( .A0(n4491), .A1(n5646), .B0(n4482), .Y(op_result[18]) );
NAND3BX1TS U3149 ( .AN(n4042), .B(n2377), .C(n4041), .Y(n4043) );
NAND2X1TS U3150 ( .A(n2587), .B(n2586), .Y(n2588) );
XNOR2X1TS U3151 ( .A(FPMULT_Op_MX[11]), .B(n2302), .Y(n3108) );
INVX3TS U3152 ( .A(n2738), .Y(n2304) );
BUFX3TS U3153 ( .A(n4953), .Y(n2199) );
NAND3X1TS U3154 ( .A(n4088), .B(FPMULT_FS_Module_state_reg[1]), .C(
FPMULT_FSM_add_overflow_flag), .Y(n3825) );
NAND2X1TS U3155 ( .A(n2617), .B(n2616), .Y(n2618) );
XOR2X1TS U3156 ( .A(n2579), .B(n2630), .Y(n2580) );
NAND2X1TS U3157 ( .A(n2556), .B(n2562), .Y(n2557) );
INVX3TS U3158 ( .A(n5251), .Y(n5182) );
NAND2X1TS U3159 ( .A(n2817), .B(n2477), .Y(n2698) );
XNOR2X1TS U3160 ( .A(n2385), .B(FPMULT_Op_MX[7]), .Y(n2911) );
NOR2X4TS U3161 ( .A(n4030), .B(FPMULT_FS_Module_state_reg[1]), .Y(n4031) );
XNOR2X1TS U3162 ( .A(n2301), .B(FPMULT_Op_MX[5]), .Y(n2907) );
NAND2BXLTS U3163 ( .AN(FPMULT_Op_MX[0]), .B(n2301), .Y(n2936) );
XNOR2X1TS U3164 ( .A(n2297), .B(FPMULT_Op_MX[9]), .Y(n2906) );
XNOR2X1TS U3165 ( .A(n2297), .B(FPMULT_Op_MX[7]), .Y(n2979) );
XNOR2X1TS U3166 ( .A(n2302), .B(FPMULT_Op_MX[5]), .Y(n2870) );
XNOR2X1TS U3167 ( .A(n2300), .B(FPMULT_Op_MX[3]), .Y(n2982) );
CLKINVX3TS U3168 ( .A(n5472), .Y(n5229) );
XNOR2X1TS U3169 ( .A(n2302), .B(FPMULT_Op_MX[4]), .Y(n2892) );
XNOR2X1TS U3170 ( .A(n2385), .B(FPMULT_Op_MX[8]), .Y(n2891) );
NAND2X4TS U3171 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(n5718), .Y(n5510) );
NAND2X4TS U3172 ( .A(n2196), .B(n2305), .Y(n5186) );
XNOR2X1TS U3173 ( .A(n2391), .B(FPMULT_Op_MX[3]), .Y(n2912) );
XNOR2X1TS U3174 ( .A(n2302), .B(FPMULT_Op_MX[6]), .Y(n2849) );
NAND2BXLTS U3175 ( .AN(n2389), .B(n2302), .Y(n2974) );
CLKBUFX3TS U3176 ( .A(n5063), .Y(n5069) );
XNOR2X1TS U3177 ( .A(n2385), .B(FPMULT_Op_MX[9]), .Y(n2869) );
OA21X2TS U3178 ( .A0(n4088), .A1(n4051), .B0(FPMULT_FS_Module_state_reg[1]),
.Y(n4052) );
XNOR2X1TS U3179 ( .A(FPMULT_Op_MX[11]), .B(n2297), .Y(n2852) );
NAND2X1TS U3180 ( .A(n2645), .B(n2644), .Y(n2646) );
XNOR2X1TS U3181 ( .A(n2385), .B(FPMULT_Op_MX[6]), .Y(n2928) );
XNOR2X1TS U3182 ( .A(n2391), .B(FPMULT_Op_MX[2]), .Y(n2977) );
XNOR2X1TS U3183 ( .A(n2302), .B(FPMULT_Op_MX[7]), .Y(n2858) );
NAND2X4TS U3184 ( .A(n2847), .B(n3179), .Y(n3180) );
XNOR2X1TS U3185 ( .A(n2302), .B(FPMULT_Op_MX[8]), .Y(n3050) );
XNOR2X1TS U3186 ( .A(n2385), .B(FPMULT_Op_MX[10]), .Y(n2853) );
XNOR2X1TS U3187 ( .A(n2297), .B(FPMULT_Op_MX[8]), .Y(n2927) );
NOR4X1TS U3188 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .D(n2377), .Y(n2206) );
XNOR2X1TS U3189 ( .A(n2436), .B(FPMULT_Op_MX[1]), .Y(n2923) );
XNOR2X1TS U3190 ( .A(n2437), .B(FPMULT_Op_MX[11]), .Y(n3132) );
NAND2BXLTS U3191 ( .AN(n2200), .B(n2395), .Y(n2695) );
XNOR2X1TS U3192 ( .A(FPMULT_Op_MX[21]), .B(n2382), .Y(n3431) );
XNOR2X1TS U3193 ( .A(n2435), .B(FPMULT_Op_MX[10]), .Y(n3145) );
XNOR2X1TS U3194 ( .A(FPMULT_Op_MX[20]), .B(n2382), .Y(n3466) );
NAND3X1TS U3195 ( .A(n5707), .B(n4141), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n4143) );
XNOR2X1TS U3196 ( .A(n2435), .B(FPMULT_Op_MX[11]), .Y(n3149) );
XOR2X1TS U3197 ( .A(n2460), .B(n2817), .Y(n2819) );
XNOR2X1TS U3198 ( .A(FPMULT_Op_MX[22]), .B(n2395), .Y(n3379) );
XNOR2X1TS U3199 ( .A(n2436), .B(FPMULT_Op_MX[2]), .Y(n2893) );
NAND2BXLTS U3200 ( .AN(n2392), .B(n2382), .Y(n2714) );
NAND3X1TS U3201 ( .A(FPSENCOS_cont_iter_out[1]), .B(n2197), .C(n4094), .Y(
n4894) );
NOR2X1TS U3202 ( .A(n5618), .B(FPMULT_FS_Module_state_reg[1]), .Y(n2526) );
XNOR2X1TS U3203 ( .A(FPMULT_Op_MX[22]), .B(n2440), .Y(n3335) );
NAND2X4TS U3204 ( .A(FPADDSUB_left_right_SHT2), .B(n2196), .Y(n5216) );
NOR2X1TS U3205 ( .A(n2608), .B(n2607), .Y(n2609) );
NOR2X1TS U3206 ( .A(n2578), .B(n2577), .Y(n2579) );
NAND2BXLTS U3207 ( .AN(n2200), .B(n2440), .Y(n3498) );
NAND2BXLTS U3208 ( .AN(n2389), .B(n2436), .Y(n2913) );
XNOR2X1TS U3209 ( .A(FPMULT_Op_MX[22]), .B(n2382), .Y(n3426) );
XNOR2X1TS U3210 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MX[18]), .Y(n3429) );
XNOR2X1TS U3211 ( .A(FPMULT_Op_MX[19]), .B(n2382), .Y(n3476) );
OAI211X1TS U3212 ( .A0(n4540), .A1(n4539), .B0(n2205), .C0(n5542), .Y(n4543)
);
NAND3X1TS U3213 ( .A(n4867), .B(n4866), .C(n4865), .Y(n5777) );
OAI21X1TS U3214 ( .A0(FPMULT_Op_MX[4]), .A1(FPMULT_Op_MX[16]), .B0(
FPMULT_Op_MX[15]), .Y(n2582) );
XOR2X1TS U3215 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[10]), .Y(n2607) );
NAND2XLTS U3216 ( .A(n5547), .B(n5531), .Y(n4517) );
XNOR2X1TS U3217 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[5]), .Y(n3074) );
OAI21X1TS U3218 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n5552), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n4192) );
NAND4X1TS U3219 ( .A(n2227), .B(n5596), .C(n2205), .D(n5542), .Y(n4495) );
XOR2X1TS U3220 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[6]), .Y(n2633) );
NOR2X1TS U3221 ( .A(FPADDSUB_Raw_mant_NRM_SWR[25]), .B(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4544) );
NAND2BX1TS U3222 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n4162) );
NAND2BX1TS U3223 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n4197) );
INVX1TS U3224 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n5357) );
OAI21X1TS U3225 ( .A0(FPMULT_Op_MX[18]), .A1(FPMULT_Op_MX[6]), .B0(
FPMULT_Op_MX[17]), .Y(n2529) );
XNOR2X1TS U3226 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[2]), .Y(n2850) );
INVX4TS U3227 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n5375) );
OAI21X1TS U3228 ( .A0(FPMULT_Op_MX[20]), .A1(FPMULT_Op_MX[8]), .B0(
FPMULT_Op_MX[7]), .Y(n2537) );
OR2X1TS U3229 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n4133) );
INVX4TS U3230 ( .A(n5783), .Y(n4205) );
NAND2BX1TS U3231 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n4141) );
XNOR2X1TS U3232 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[9]), .Y(n3133) );
NAND2BXLTS U3233 ( .AN(FPMULT_Op_MX[0]), .B(FPMULT_Op_MY[11]), .Y(n2877) );
BUFX4TS U3234 ( .A(FPMULT_Op_MY[19]), .Y(n2440) );
NAND2BX1TS U3235 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n4142) );
OAI21X1TS U3236 ( .A0(FPMULT_Op_MX[2]), .A1(FPMULT_Op_MX[14]), .B0(
FPMULT_Op_MX[13]), .Y(n2574) );
OAI32X1TS U3237 ( .A0(n4898), .A1(FPMULT_exp_oper_result[8]), .A2(
FPMULT_Exp_module_Overflow_flag_A), .B0(overflow_flag_addsubt), .B1(
operation[2]), .Y(n4328) );
NOR2X1TS U3238 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n5180) );
CLKBUFX2TS U3239 ( .A(ready_add_subt), .Y(n2381) );
XNOR2X1TS U3240 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[1]), .Y(n2875) );
XNOR2X1TS U3241 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[8]), .Y(n3124) );
NAND2BX1TS U3242 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n4181) );
NOR2XLTS U3243 ( .A(n5587), .B(n5709), .Y(FPMULT_S_Oper_A_exp[8]) );
NAND2BX1TS U3244 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n4187) );
XNOR2X1TS U3245 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[7]), .Y(n3104) );
OAI21X1TS U3246 ( .A0(FPMULT_Op_MX[22]), .A1(FPMULT_Op_MX[10]), .B0(
FPMULT_Op_MX[9]), .Y(n2560) );
XNOR2X1TS U3247 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[6]), .Y(n3094) );
INVX4TS U3248 ( .A(n4906), .Y(n4457) );
NOR2X4TS U3249 ( .A(n4458), .B(operation[2]), .Y(n4468) );
OAI2BB2X2TS U3250 ( .B0(n5416), .B1(n5418), .A0N(n5676), .A1N(
FPADDSUB_DMP_SFG[18]), .Y(n5424) );
OA21X4TS U3251 ( .A0(n4760), .A1(n4757), .B0(n4758), .Y(n4766) );
NOR2X2TS U3252 ( .A(n3765), .B(n3764), .Y(n4773) );
AO21X4TS U3253 ( .A0(n2517), .A1(n4801), .B0(n3803), .Y(n2466) );
OAI21X4TS U3254 ( .A0(n4766), .A1(n4763), .B0(n4764), .Y(n4801) );
OAI21X4TS U3255 ( .A0(n4734), .A1(n4737), .B0(n4735), .Y(n4797) );
AOI21X4TS U3256 ( .A0(n2223), .A1(n4771), .B0(n3768), .Y(n4760) );
AOI21X4TS U3257 ( .A0(n4781), .A1(n2480), .B0(n3750), .Y(n4776) );
OA21X4TS U3258 ( .A0(n3853), .A1(n2522), .B0(n3852), .Y(n2459) );
OA21X4TS U3259 ( .A0(n4818), .A1(n4815), .B0(n4816), .Y(n2522) );
XNOR2X4TS U3260 ( .A(FPMULT_Op_MY[2]), .B(n2296), .Y(n3051) );
OAI22X1TS U3261 ( .A0(n2735), .A1(n2739), .B0(n2561), .B1(n2736), .Y(
DP_OP_453J208_122_681_n492) );
OAI21X2TS U3262 ( .A0(n3278), .A1(n3284), .B0(n3279), .Y(n3027) );
NOR2X1TS U3263 ( .A(DP_OP_453J208_122_681_n1721), .B(n2481), .Y(n3076) );
NAND2X1TS U3264 ( .A(n2725), .B(n2724), .Y(n2726) );
INVX2TS U3265 ( .A(n2723), .Y(n2725) );
INVX2TS U3266 ( .A(n3596), .Y(DP_OP_453J208_122_681_n846) );
ADDHX1TS U3267 ( .A(n2665), .B(n2664), .CO(n2661), .S(
DP_OP_453J208_122_681_n394) );
OAI22X1TS U3268 ( .A0(n2764), .A1(n2754), .B0(n2767), .B1(n2658), .Y(n2665)
);
XOR2X1TS U3269 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[4]), .Y(n2578) );
XOR2X1TS U3270 ( .A(n2636), .B(n2635), .Y(n2637) );
NOR2X1TS U3271 ( .A(n2634), .B(n2633), .Y(n2636) );
OAI22X1TS U3272 ( .A0(n2981), .A1(n2889), .B0(n2852), .B1(n3555), .Y(n2879)
);
NOR2X2TS U3273 ( .A(n3254), .B(n3261), .Y(n3038) );
NOR2X1TS U3274 ( .A(DP_OP_453J208_122_681_n1721), .B(n2464), .Y(n3107) );
INVX2TS U3275 ( .A(n2836), .Y(n2735) );
INVX4TS U3276 ( .A(n2778), .Y(n2424) );
XNOR2X1TS U3277 ( .A(n2437), .B(FPMULT_Op_MX[9]), .Y(n3109) );
XNOR2X1TS U3278 ( .A(n2437), .B(FPMULT_Op_MX[7]), .Y(n3073) );
INVX2TS U3279 ( .A(DP_OP_453J208_122_681_n1766), .Y(
DP_OP_453J208_122_681_n834) );
OAI22X1TS U3280 ( .A0(n2620), .A1(n2739), .B0(n2734), .B1(n2561), .Y(n2624)
);
XOR2X1TS U3281 ( .A(n2702), .B(n2705), .Y(n2703) );
XOR2X1TS U3282 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[2]), .Y(n2701) );
INVX4TS U3283 ( .A(n2499), .Y(n2396) );
INVX2TS U3284 ( .A(n3699), .Y(DP_OP_453J208_122_681_n458) );
XOR2X1TS U3285 ( .A(FPMULT_Op_MY[4]), .B(n2300), .Y(n2845) );
XOR2X1TS U3286 ( .A(n2299), .B(FPMULT_Op_MY[2]), .Y(n2843) );
INVX2TS U3287 ( .A(n4756), .Y(DP_OP_453J208_122_681_n466) );
NOR2X1TS U3288 ( .A(n3735), .B(n3733), .Y(n3569) );
OAI21X1TS U3289 ( .A0(n3735), .A1(n3732), .B0(n3736), .Y(n3568) );
OAI21X2TS U3290 ( .A0(n3297), .A1(n3303), .B0(n3298), .Y(n2967) );
INVX2TS U3291 ( .A(n3843), .Y(n3917) );
INVX2TS U3292 ( .A(n3240), .Y(n3242) );
OAI21X1TS U3293 ( .A0(n3930), .A1(n3929), .B0(n3928), .Y(n3942) );
INVX2TS U3294 ( .A(n3733), .Y(n3726) );
OR2X4TS U3295 ( .A(n2459), .B(n3889), .Y(n3891) );
INVX2TS U3296 ( .A(n2840), .Y(n2737) );
INVX2TS U3297 ( .A(n2585), .Y(n2587) );
INVX4TS U3298 ( .A(n2762), .Y(n2426) );
INVX2TS U3299 ( .A(n2828), .Y(n2732) );
INVX2TS U3300 ( .A(n2834), .Y(n2734) );
XNOR2X1TS U3301 ( .A(n2826), .B(n2425), .Y(n2744) );
INVX2TS U3302 ( .A(n2832), .Y(n2620) );
XNOR2X1TS U3303 ( .A(n2437), .B(FPMULT_Op_MX[10]), .Y(n3125) );
NOR2X1TS U3304 ( .A(DP_OP_453J208_122_681_n1721), .B(n2455), .Y(n3131) );
INVX2TS U3305 ( .A(n2638), .Y(n2640) );
OAI22X1TS U3306 ( .A0(n3123), .A1(n2858), .B0(n2432), .B1(n3050), .Y(n3048)
);
XNOR2X1TS U3307 ( .A(n2437), .B(FPMULT_Op_MX[6]), .Y(n3054) );
OAI22X1TS U3308 ( .A0(n3180), .A1(n2850), .B0(n2402), .B1(n2859), .Y(n2854)
);
OAI22X1TS U3309 ( .A0(n3123), .A1(n2849), .B0(n2432), .B1(n2858), .Y(n2855)
);
XNOR2X1TS U3310 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MX[19]), .Y(n3411) );
XNOR2X1TS U3311 ( .A(n2440), .B(FPMULT_Op_MX[18]), .Y(n3391) );
XNOR2X1TS U3312 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MX[21]), .Y(n3373) );
XNOR2X1TS U3313 ( .A(n2440), .B(FPMULT_Op_MX[19]), .Y(n3374) );
XNOR2X1TS U3314 ( .A(n2440), .B(FPMULT_Op_MX[20]), .Y(n3358) );
XNOR2X1TS U3315 ( .A(n2440), .B(FPMULT_Op_MX[17]), .Y(n3416) );
XNOR2X1TS U3316 ( .A(n2396), .B(FPMULT_Op_MX[15]), .Y(n3419) );
OAI22X1TS U3317 ( .A0(n3426), .A1(n3478), .B0(n2224), .B1(n2382), .Y(n3418)
);
XNOR2X1TS U3318 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MX[16]), .Y(n3430) );
XNOR2X1TS U3319 ( .A(n2396), .B(FPMULT_Op_MX[14]), .Y(n3445) );
XNOR2X1TS U3320 ( .A(n2824), .B(n2425), .Y(n2743) );
XNOR2X1TS U3321 ( .A(n2822), .B(n2425), .Y(n2742) );
XNOR2X1TS U3322 ( .A(n2816), .B(n2426), .Y(n2755) );
XNOR2X1TS U3323 ( .A(n2820), .B(n2419), .Y(n2785) );
XNOR2X1TS U3324 ( .A(n2824), .B(n2424), .Y(n2772) );
XNOR2X1TS U3325 ( .A(n2822), .B(n2424), .Y(n2771) );
INVX2TS U3326 ( .A(DP_OP_453J208_122_681_n1764), .Y(
DP_OP_453J208_122_681_n832) );
XNOR2X1TS U3327 ( .A(n2820), .B(n2426), .Y(n2756) );
XOR2X1TS U3328 ( .A(n2534), .B(n2604), .Y(n2535) );
XNOR2X1TS U3329 ( .A(n2820), .B(n2424), .Y(n2770) );
XNOR2X1TS U3330 ( .A(n2816), .B(n2424), .Y(n2769) );
OAI22X1TS U3331 ( .A0(n2981), .A1(n2852), .B0(n2469), .B1(n3555), .Y(n2863)
);
OAI22X1TS U3332 ( .A0(n3180), .A1(n2875), .B0(n3179), .B1(n2850), .Y(n2872)
);
OAI22X1TS U3333 ( .A0(n3123), .A1(n2870), .B0(n2432), .B1(n2849), .Y(n2873)
);
OAI22X1TS U3334 ( .A0(n3180), .A1(n3094), .B0(n2402), .B1(n3104), .Y(n3101)
);
OAI22X1TS U3335 ( .A0(n3180), .A1(n3104), .B0(n2402), .B1(n3124), .Y(n3121)
);
XNOR2X1TS U3336 ( .A(n2396), .B(FPMULT_Op_MX[21]), .Y(n3330) );
OAI22X1TS U3337 ( .A0(n3509), .A1(n2440), .B0(n2401), .B1(
DP_OP_453J208_122_681_n2101), .Y(n3320) );
OAI22X1TS U3338 ( .A0(n3509), .A1(n3335), .B0(n2401), .B1(n2440), .Y(n3334)
);
XNOR2X1TS U3339 ( .A(n2396), .B(FPMULT_Op_MX[17]), .Y(n3378) );
XNOR2X1TS U3340 ( .A(n2396), .B(FPMULT_Op_MX[18]), .Y(n3362) );
XNOR2X1TS U3341 ( .A(n2396), .B(FPMULT_Op_MX[19]), .Y(n3355) );
AOI21X1TS U3342 ( .A0(n2565), .A1(n2593), .B0(n2564), .Y(n2566) );
XNOR2X1TS U3343 ( .A(n2396), .B(n2393), .Y(n3463) );
ADDHX1TS U3344 ( .A(n2926), .B(n2925), .CO(n2931), .S(n3015) );
OAI22X1TS U3345 ( .A0(n2981), .A1(n2927), .B0(n2906), .B1(n3555), .Y(n2926)
);
INVX2TS U3346 ( .A(n3152), .Y(n3144) );
OAI22X1TS U3347 ( .A0(n3180), .A1(n3133), .B0(n2402), .B1(n3145), .Y(n3142)
);
XNOR2X1TS U3348 ( .A(n2440), .B(FPMULT_Op_MX[13]), .Y(n3507) );
OAI22X1TS U3349 ( .A0(n3478), .A1(n2670), .B0(n3477), .B1(n2224), .Y(n3511)
);
ADDHX1TS U3350 ( .A(n2985), .B(n2984), .CO(n3011), .S(n2994) );
NOR2X1TS U3351 ( .A(DP_OP_453J208_122_681_n1721), .B(n2486), .Y(n3151) );
OAI22X1TS U3352 ( .A0(n3180), .A1(n3145), .B0(n2402), .B1(n3149), .Y(n3150)
);
INVX4TS U3353 ( .A(n2225), .Y(n2398) );
INVX4TS U3354 ( .A(n2561), .Y(n2739) );
NAND2X4TS U3355 ( .A(n2601), .B(FPMULT_Op_MX[11]), .Y(n2561) );
CMPR42X1TS U3356 ( .A(DP_OP_453J208_122_681_n247), .B(
DP_OP_453J208_122_681_n243), .C(DP_OP_453J208_122_681_n248), .D(
DP_OP_453J208_122_681_n244), .ICI(DP_OP_453J208_122_681_n452), .S(
DP_OP_453J208_122_681_n240), .ICO(DP_OP_453J208_122_681_n238), .CO(
DP_OP_453J208_122_681_n239) );
INVX2TS U3357 ( .A(n3714), .Y(DP_OP_453J208_122_681_n452) );
CMPR42X1TS U3358 ( .A(DP_OP_453J208_122_681_n255), .B(
DP_OP_453J208_122_681_n249), .C(DP_OP_453J208_122_681_n256), .D(
DP_OP_453J208_122_681_n252), .ICI(DP_OP_453J208_122_681_n453), .S(
DP_OP_453J208_122_681_n246), .ICO(DP_OP_453J208_122_681_n244), .CO(
DP_OP_453J208_122_681_n245) );
INVX2TS U3359 ( .A(n3712), .Y(DP_OP_453J208_122_681_n453) );
CMPR42X1TS U3360 ( .A(DP_OP_453J208_122_681_n267), .B(
DP_OP_453J208_122_681_n257), .C(DP_OP_453J208_122_681_n264), .D(
DP_OP_453J208_122_681_n260), .ICI(DP_OP_453J208_122_681_n454), .S(
DP_OP_453J208_122_681_n254), .ICO(DP_OP_453J208_122_681_n252), .CO(
DP_OP_453J208_122_681_n253) );
INVX2TS U3361 ( .A(n3709), .Y(DP_OP_453J208_122_681_n454) );
OAI21X1TS U3362 ( .A0(n3627), .A1(n3600), .B0(n3599), .Y(n3617) );
NAND2X1TS U3363 ( .A(n2511), .B(n2510), .Y(n3600) );
AOI21X1TS U3364 ( .A0(n2511), .A1(n3628), .B0(n3598), .Y(n3599) );
INVX2TS U3365 ( .A(n3629), .Y(n3598) );
OAI22X1TS U3366 ( .A0(n3478), .A1(n2696), .B0(n2692), .B1(n2224), .Y(n3529)
);
INVX2TS U3367 ( .A(n4746), .Y(DP_OP_453J208_122_681_n463) );
OAI22X1TS U3368 ( .A0(n3478), .A1(n2692), .B0(n2686), .B1(n2224), .Y(n3526)
);
NOR2BX1TS U3369 ( .AN(n2200), .B(n2292), .Y(n3527) );
OAI21X1TS U3370 ( .A0(n3762), .A1(n3759), .B0(n3760), .Y(n3636) );
OAI22X1TS U3371 ( .A0(n2981), .A1(n2979), .B0(n2927), .B1(n3555), .Y(n2970)
);
INVX2TS U3372 ( .A(n3704), .Y(DP_OP_453J208_122_681_n456) );
OAI22X1TS U3373 ( .A0(n3497), .A1(n2678), .B0(n3496), .B1(n2399), .Y(n3521)
);
OAI21X2TS U3374 ( .A0(n3664), .A1(n3660), .B0(n3661), .Y(n3658) );
INVX2TS U3375 ( .A(n3183), .Y(n3178) );
OAI22X1TS U3376 ( .A0(n3180), .A1(n3149), .B0(n2402), .B1(
DP_OP_453J208_122_681_n1721), .Y(n3177) );
AOI21X1TS U3377 ( .A0(n3198), .A1(n2442), .B0(n2465), .Y(n3172) );
INVX2TS U3378 ( .A(n3828), .Y(n3807) );
NOR2X2TS U3379 ( .A(DP_OP_453J208_122_681_n254), .B(
DP_OP_453J208_122_681_n261), .Y(n3827) );
INVX2TS U3380 ( .A(n3751), .Y(n3752) );
ADDHX1TS U3381 ( .A(n2960), .B(n2959), .CO(n2961), .S(n2954) );
NAND2X1TS U3382 ( .A(n3170), .B(n3169), .Y(n3194) );
NAND2X1TS U3383 ( .A(n3197), .B(n2450), .Y(n3191) );
NAND2X1TS U3384 ( .A(n3571), .B(n3769), .Y(n3573) );
NAND2X1TS U3385 ( .A(n3210), .B(n3209), .Y(n3211) );
INVX2TS U3386 ( .A(n3208), .Y(n3210) );
NAND2X1TS U3387 ( .A(n3228), .B(n3227), .Y(n3229) );
INVX2TS U3388 ( .A(n3226), .Y(n3228) );
NAND2X1TS U3389 ( .A(n3256), .B(n3255), .Y(n3257) );
AOI21X1TS U3390 ( .A0(n3276), .A1(n3253), .B0(n3252), .Y(n3258) );
INVX2TS U3391 ( .A(n3254), .Y(n3256) );
INVX2TS U3392 ( .A(n3940), .Y(n3941) );
CLKAND2X2TS U3393 ( .A(n3916), .B(n3910), .Y(n2524) );
NOR2X1TS U3394 ( .A(n3913), .B(n3909), .Y(n3916) );
NOR2X2TS U3395 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(n4514), .Y(n4532) );
INVX2TS U3396 ( .A(n3277), .Y(n3287) );
NAND2X1TS U3397 ( .A(n3644), .B(n3643), .Y(n3645) );
INVX2TS U3398 ( .A(n3642), .Y(n3644) );
INVX2TS U3399 ( .A(n4707), .Y(n3700) );
INVX2TS U3400 ( .A(n4748), .Y(n3690) );
NOR2X2TS U3401 ( .A(n5687), .B(n5131), .Y(n5133) );
AOI21X2TS U3402 ( .A0(n2518), .A1(n2466), .B0(n3806), .Y(n4818) );
INVX2TS U3403 ( .A(n4809), .Y(n3806) );
NOR2X1TS U3404 ( .A(n3823), .B(n3822), .Y(n4815) );
INVX2TS U3405 ( .A(n4032), .Y(n3731) );
NAND2X2TS U3406 ( .A(n3742), .B(n3741), .Y(n4784) );
AOI21X2TS U3407 ( .A0(n2453), .A1(n4797), .B0(n3715), .Y(n4793) );
INVX2TS U3408 ( .A(n4796), .Y(n3715) );
NAND2X2TS U3409 ( .A(n3724), .B(n3723), .Y(n4790) );
NAND2X2TS U3410 ( .A(n3712), .B(n3711), .Y(n4735) );
NAND2X1TS U3411 ( .A(n5598), .B(n5103), .Y(n5105) );
NOR2X2TS U3412 ( .A(n5605), .B(n5115), .Y(n5117) );
NOR2X2TS U3413 ( .A(n5613), .B(n5119), .Y(n5121) );
NOR2X2TS U3414 ( .A(n5629), .B(n5123), .Y(n5125) );
NOR2X2TS U3415 ( .A(n5638), .B(n5127), .Y(n5129) );
INVX2TS U3416 ( .A(n2590), .Y(n2584) );
INVX2TS U3417 ( .A(n2583), .Y(n2591) );
OAI21X1TS U3418 ( .A0(n2553), .A1(n2596), .B0(n2597), .Y(n2554) );
NOR2X1TS U3419 ( .A(n2552), .B(n2596), .Y(n2555) );
INVX2TS U3420 ( .A(n2594), .Y(n2552) );
INVX2TS U3421 ( .A(n2568), .Y(n2595) );
INVX2TS U3422 ( .A(n2614), .Y(n2642) );
XNOR2X1TS U3423 ( .A(n2301), .B(FPMULT_Op_MX[10]), .Y(n3058) );
INVX2TS U3424 ( .A(n3077), .Y(n3056) );
XNOR2X1TS U3425 ( .A(n2301), .B(FPMULT_Op_MX[9]), .Y(n2857) );
INVX2TS U3426 ( .A(n2625), .Y(n2649) );
INVX2TS U3427 ( .A(n2648), .Y(n2549) );
NOR2X1TS U3428 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[14]), .Y(n2643) );
NAND2X1TS U3429 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[14]), .Y(n2644) );
INVX2TS U3430 ( .A(n2719), .Y(n2720) );
INVX2TS U3431 ( .A(n2621), .Y(n2721) );
NAND2X1TS U3432 ( .A(FPMULT_Op_MY[19]), .B(n2302), .Y(n2597) );
NAND2X1TS U3433 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n2562) );
NOR2X2TS U3434 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n2585) );
NOR2X2TS U3435 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n2615) );
NAND2X1TS U3436 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[4]), .Y(n2616) );
XNOR2X1TS U3437 ( .A(n2834), .B(n2425), .Y(n2748) );
XNOR2X1TS U3438 ( .A(n2836), .B(n2426), .Y(n2765) );
XNOR2X1TS U3439 ( .A(n2425), .B(n2840), .Y(n2752) );
XNOR2X1TS U3440 ( .A(n2828), .B(n2426), .Y(n2760) );
XNOR2X1TS U3441 ( .A(n2830), .B(n2426), .Y(n2761) );
INVX2TS U3442 ( .A(n2838), .Y(n2736) );
XNOR2X1TS U3443 ( .A(n2838), .B(n2426), .Y(n2657) );
XNOR2X1TS U3444 ( .A(n2426), .B(n2840), .Y(n2659) );
NAND2X1TS U3445 ( .A(n2582), .B(n2581), .Y(n2629) );
NAND2X1TS U3446 ( .A(FPMULT_Op_MX[4]), .B(FPMULT_Op_MX[16]), .Y(n2581) );
NAND2X1TS U3447 ( .A(n2574), .B(n2573), .Y(n2704) );
NAND2X1TS U3448 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[14]), .Y(n2573) );
XNOR2X2TS U3449 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MX[17]), .Y(n2630) );
NAND2X1TS U3450 ( .A(n2529), .B(n2528), .Y(n2627) );
XNOR2X1TS U3451 ( .A(n2826), .B(n2426), .Y(n2759) );
XNOR2X2TS U3452 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[7]), .Y(n2635) );
XNOR2X1TS U3453 ( .A(n2301), .B(FPMULT_Op_MX[7]), .Y(n2851) );
XNOR2X1TS U3454 ( .A(n2301), .B(FPMULT_Op_MX[8]), .Y(n2848) );
XNOR2X1TS U3455 ( .A(n2437), .B(FPMULT_Op_MX[8]), .Y(n3091) );
INVX2TS U3456 ( .A(n3107), .Y(n3090) );
NOR2X1TS U3457 ( .A(DP_OP_453J208_122_681_n1721), .B(n2463), .Y(n3106) );
XNOR2X2TS U3458 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[15]), .Y(n2705) );
CLKAND2X2TS U3459 ( .A(n2389), .B(n2392), .Y(n2477) );
XNOR2X2TS U3460 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .Y(n2817) );
XNOR2X1TS U3461 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[17]), .Y(n3357) );
XNOR2X1TS U3462 ( .A(n2440), .B(FPMULT_Op_MX[21]), .Y(n3342) );
NAND2X1TS U3463 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n2724) );
NOR2X2TS U3464 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n2723) );
NOR2X2TS U3465 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[8]), .Y(n2563) );
OAI21X1TS U3466 ( .A0(n2563), .A1(n2597), .B0(n2562), .Y(n2564) );
OAI21X2TS U3467 ( .A0(n2585), .A1(n2590), .B0(n2586), .Y(n2593) );
AOI21X2TS U3468 ( .A0(n2614), .A1(n2551), .B0(n2550), .Y(n2568) );
OAI21X1TS U3469 ( .A0(n2615), .A1(n2639), .B0(n2616), .Y(n2550) );
NOR2X1TS U3470 ( .A(n2615), .B(n2638), .Y(n2551) );
XNOR2X1TS U3471 ( .A(n2396), .B(FPMULT_Op_MX[16]), .Y(n3396) );
OAI2BB1X1TS U3472 ( .A0N(n3316), .A1N(n2476), .B0(n3412), .Y(n3434) );
OAI22X1TS U3473 ( .A0(n3497), .A1(n3429), .B0(n3411), .B1(n2399), .Y(n3435)
);
INVX2TS U3474 ( .A(n2824), .Y(n2729) );
OAI22X1TS U3475 ( .A0(n3426), .A1(n2224), .B0(n3478), .B1(n3431), .Y(n3448)
);
OAI22X1TS U3476 ( .A0(n3482), .A1(n3432), .B0(n3427), .B1(n2428), .Y(n3447)
);
XNOR2X1TS U3477 ( .A(n2820), .B(n2425), .Y(n2741) );
INVX2TS U3478 ( .A(n3994), .Y(n2571) );
OAI22X1TS U3479 ( .A0(n2731), .A1(n2561), .B0(n2729), .B1(n2739), .Y(n2570)
);
XNOR2X1TS U3480 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MX[17]), .Y(n3449) );
XNOR2X1TS U3481 ( .A(n2440), .B(FPMULT_Op_MX[15]), .Y(n3450) );
ADDHXLTS U3482 ( .A(n3452), .B(n3451), .CO(n3459), .S(n3483) );
OAI22X1TS U3483 ( .A0(n3478), .A1(n3466), .B0(n3431), .B1(n2224), .Y(n3452)
);
XNOR2X1TS U3484 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MX[13]), .Y(n3462) );
OAI22X1TS U3485 ( .A0(n2732), .A1(n2561), .B0(n2731), .B1(n2739), .Y(
DP_OP_453J208_122_681_n487) );
XNOR2X1TS U3486 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MX[16]), .Y(n3474) );
XNOR2X1TS U3487 ( .A(n2440), .B(FPMULT_Op_MX[14]), .Y(n3475) );
XNOR2X1TS U3488 ( .A(n2816), .B(n2417), .Y(n2801) );
XNOR2X1TS U3489 ( .A(n2826), .B(n2424), .Y(n2773) );
XNOR2X1TS U3490 ( .A(n2820), .B(n2417), .Y(n2802) );
CMPR42X1TS U3491 ( .A(DP_OP_453J208_122_681_n494), .B(
DP_OP_453J208_122_681_n507), .C(DP_OP_453J208_122_681_n520), .D(
DP_OP_453J208_122_681_n357), .ICI(DP_OP_453J208_122_681_n572), .S(
DP_OP_453J208_122_681_n347), .ICO(DP_OP_453J208_122_681_n345), .CO(
DP_OP_453J208_122_681_n346) );
OAI22X1TS U3492 ( .A0(n2561), .A1(n2738), .B0(n2739), .B1(n2737), .Y(
DP_OP_453J208_122_681_n494) );
OAI22X1TS U3493 ( .A0(n2821), .A1(n3543), .B0(DP_OP_453J208_122_681_n571),
.B1(n3556), .Y(DP_OP_453J208_122_681_n572) );
XNOR2X1TS U3494 ( .A(n2830), .B(n2419), .Y(n2790) );
XNOR2X1TS U3495 ( .A(n2824), .B(n2426), .Y(n2757) );
INVX2TS U3496 ( .A(DP_OP_453J208_122_681_n1760), .Y(
DP_OP_453J208_122_681_n828) );
XNOR2X1TS U3497 ( .A(n2822), .B(n2426), .Y(n2758) );
CMPR42X1TS U3498 ( .A(DP_OP_453J208_122_681_n488), .B(
DP_OP_453J208_122_681_n1756), .C(DP_OP_453J208_122_681_n501), .D(
DP_OP_453J208_122_681_n823), .ICI(DP_OP_453J208_122_681_n284), .S(
DP_OP_453J208_122_681_n277), .ICO(DP_OP_453J208_122_681_n275), .CO(
DP_OP_453J208_122_681_n276) );
OAI22X1TS U3499 ( .A0(n2733), .A1(n2561), .B0(n2732), .B1(n2739), .Y(
DP_OP_453J208_122_681_n488) );
INVX2TS U3500 ( .A(n3968), .Y(DP_OP_453J208_122_681_n823) );
CMPR42X1TS U3501 ( .A(DP_OP_453J208_122_681_n556), .B(
DP_OP_453J208_122_681_n491), .C(DP_OP_453J208_122_681_n504), .D(
DP_OP_453J208_122_681_n517), .ICI(DP_OP_453J208_122_681_n830), .S(
DP_OP_453J208_122_681_n311), .ICO(DP_OP_453J208_122_681_n309), .CO(
DP_OP_453J208_122_681_n310) );
OAI22X1TS U3502 ( .A0(n2734), .A1(n2739), .B0(n2735), .B1(n2561), .Y(
DP_OP_453J208_122_681_n491) );
OAI22X1TS U3503 ( .A0(n2733), .A1(n2739), .B0(n2620), .B1(n2561), .Y(n2612)
);
XNOR2X1TS U3504 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MX[15]), .Y(n3495) );
OAI22X1TS U3505 ( .A0(n3478), .A1(n3477), .B0(n3476), .B1(n2224), .Y(n3500)
);
OAI22X1TS U3506 ( .A0(n3123), .A1(n2892), .B0(n2432), .B1(n2870), .Y(n2895)
);
NAND2BXLTS U3507 ( .AN(n2303), .B(n2417), .Y(n2799) );
INVX2TS U3508 ( .A(n3131), .Y(n3118) );
OAI22X1TS U3509 ( .A0(n3123), .A1(n3108), .B0(n2432), .B1(n2461), .Y(n3117)
);
NOR2X1TS U3510 ( .A(DP_OP_453J208_122_681_n1721), .B(n2489), .Y(n3130) );
CMPR42X1TS U3511 ( .A(DP_OP_453J208_122_681_n854), .B(
DP_OP_453J208_122_681_n555), .C(DP_OP_453J208_122_681_n441), .D(
DP_OP_453J208_122_681_n853), .ICI(DP_OP_453J208_122_681_n581), .S(
DP_OP_453J208_122_681_n435), .ICO(DP_OP_453J208_122_681_n433), .CO(
DP_OP_453J208_122_681_n434) );
CMPR42X1TS U3512 ( .A(DP_OP_453J208_122_681_n428), .B(
DP_OP_453J208_122_681_n849), .C(DP_OP_453J208_122_681_n566), .D(
DP_OP_453J208_122_681_n425), .ICI(DP_OP_453J208_122_681_n579), .S(
DP_OP_453J208_122_681_n419), .ICO(DP_OP_453J208_122_681_n417), .CO(
DP_OP_453J208_122_681_n418) );
INVX2TS U3513 ( .A(n3591), .Y(DP_OP_453J208_122_681_n849) );
XNOR2X1TS U3514 ( .A(n2396), .B(FPMULT_Op_MX[22]), .Y(n3318) );
OAI22X1TS U3515 ( .A0(n3509), .A1(n3342), .B0(n3335), .B1(n2401), .Y(n3340)
);
OAI22X1TS U3516 ( .A0(n3497), .A1(FPMULT_Op_MY[17]), .B0(n2399), .B1(
DP_OP_453J208_122_681_n2102), .Y(n3341) );
OAI22X1TS U3517 ( .A0(n3509), .A1(n3416), .B0(n2401), .B1(n3391), .Y(n3414)
);
OAI22X1TS U3518 ( .A0(n3509), .A1(n3391), .B0(n2401), .B1(n3374), .Y(n3393)
);
OAI22X1TS U3519 ( .A0(n3509), .A1(n3374), .B0(n2401), .B1(n3358), .Y(n3376)
);
OAI22X1TS U3520 ( .A0(n3497), .A1(n3373), .B0(n3357), .B1(n2399), .Y(n3377)
);
OAI22X1TS U3521 ( .A0(n3509), .A1(n3358), .B0(n2401), .B1(n3342), .Y(n3360)
);
OAI22X1TS U3522 ( .A0(n3497), .A1(n3357), .B0(n2399), .B1(FPMULT_Op_MY[17]),
.Y(n3361) );
XNOR2X1TS U3523 ( .A(n2816), .B(n2425), .Y(n2740) );
INVX2TS U3524 ( .A(n2822), .Y(n2730) );
INVX2TS U3525 ( .A(n4007), .Y(n2541) );
INVX2TS U3526 ( .A(n4008), .Y(n2540) );
OAI21X1TS U3527 ( .A0(n2723), .A1(n2719), .B0(n2724), .Y(n2716) );
OAI22X1TS U3528 ( .A0(n3465), .A1(n3396), .B0(n3378), .B1(n2398), .Y(n3407)
);
OAI22X1TS U3529 ( .A0(n3465), .A1(n3419), .B0(n3396), .B1(n2398), .Y(n3424)
);
OAI22X1TS U3530 ( .A0(n3465), .A1(n3445), .B0(n3419), .B1(n2398), .Y(n3442)
);
CMPR42X1TS U3531 ( .A(DP_OP_453J208_122_681_n820), .B(
DP_OP_453J208_122_681_n251), .C(DP_OP_453J208_122_681_n485), .D(
DP_OP_453J208_122_681_n258), .ICI(DP_OP_453J208_122_681_n498), .S(
DP_OP_453J208_122_681_n249), .ICO(DP_OP_453J208_122_681_n247), .CO(
DP_OP_453J208_122_681_n248) );
INVX2TS U3532 ( .A(n3993), .Y(DP_OP_453J208_122_681_n820) );
OAI22X1TS U3533 ( .A0(n2730), .A1(n2739), .B0(n2729), .B1(n2561), .Y(
DP_OP_453J208_122_681_n485) );
OAI22X1TS U3534 ( .A0(n3509), .A1(n3450), .B0(n2400), .B1(n3430), .Y(n3460)
);
OAI22X1TS U3535 ( .A0(n3497), .A1(n3449), .B0(n3429), .B1(n2399), .Y(n3461)
);
OAI22X1TS U3536 ( .A0(n3465), .A1(n3462), .B0(n3445), .B1(n2398), .Y(n3470)
);
CMPR42X1TS U3537 ( .A(DP_OP_453J208_122_681_n512), .B(
DP_OP_453J208_122_681_n259), .C(DP_OP_453J208_122_681_n266), .D(
DP_OP_453J208_122_681_n499), .ICI(DP_OP_453J208_122_681_n263), .S(
DP_OP_453J208_122_681_n257), .ICO(DP_OP_453J208_122_681_n255), .CO(
DP_OP_453J208_122_681_n256) );
OAI22X1TS U3538 ( .A0(n3509), .A1(n3475), .B0(n2400), .B1(n3450), .Y(n3484)
);
OAI22X1TS U3539 ( .A0(n3497), .A1(n3474), .B0(n3449), .B1(n2399), .Y(n3485)
);
CMPR42X1TS U3540 ( .A(DP_OP_453J208_122_681_n513), .B(
DP_OP_453J208_122_681_n500), .C(DP_OP_453J208_122_681_n275), .D(
DP_OP_453J208_122_681_n272), .ICI(DP_OP_453J208_122_681_n276), .S(
DP_OP_453J208_122_681_n265), .ICO(DP_OP_453J208_122_681_n263), .CO(
DP_OP_453J208_122_681_n264) );
CMPR42X1TS U3541 ( .A(DP_OP_453J208_122_681_n526), .B(
DP_OP_453J208_122_681_n822), .C(DP_OP_453J208_122_681_n487), .D(
DP_OP_453J208_122_681_n821), .ICI(DP_OP_453J208_122_681_n824), .S(
DP_OP_453J208_122_681_n268), .ICO(DP_OP_453J208_122_681_n266), .CO(
DP_OP_453J208_122_681_n267) );
INVX2TS U3542 ( .A(DP_OP_453J208_122_681_n1756), .Y(
DP_OP_453J208_122_681_n824) );
INVX2TS U3543 ( .A(n3982), .Y(DP_OP_453J208_122_681_n821) );
OAI22X1TS U3544 ( .A0(n3509), .A1(n3507), .B0(n2401), .B1(n3475), .Y(n3502)
);
OAI22X1TS U3545 ( .A0(n3497), .A1(n3495), .B0(n3474), .B1(n2399), .Y(n3503)
);
NOR2BX1TS U3546 ( .AN(n2393), .B(n2397), .Y(n3494) );
OAI22X1TS U3547 ( .A0(n3478), .A1(n3476), .B0(n3466), .B1(n2224), .Y(n3493)
);
CMPR42X1TS U3548 ( .A(DP_OP_453J208_122_681_n546), .B(
DP_OP_453J208_122_681_n533), .C(DP_OP_453J208_122_681_n836), .D(
DP_OP_453J208_122_681_n835), .ICI(DP_OP_453J208_122_681_n358), .S(
DP_OP_453J208_122_681_n344), .ICO(DP_OP_453J208_122_681_n342), .CO(
DP_OP_453J208_122_681_n343) );
CMPR42X1TS U3549 ( .A(DP_OP_453J208_122_681_n534), .B(
DP_OP_453J208_122_681_n369), .C(DP_OP_453J208_122_681_n547), .D(
DP_OP_453J208_122_681_n837), .ICI(DP_OP_453J208_122_681_n359), .S(
DP_OP_453J208_122_681_n356), .ICO(DP_OP_453J208_122_681_n354), .CO(
DP_OP_453J208_122_681_n355) );
INVX2TS U3550 ( .A(n3845), .Y(DP_OP_453J208_122_681_n837) );
CMPR42X1TS U3551 ( .A(DP_OP_453J208_122_681_n573), .B(
DP_OP_453J208_122_681_n560), .C(DP_OP_453J208_122_681_n366), .D(
DP_OP_453J208_122_681_n363), .ICI(DP_OP_453J208_122_681_n367), .S(
DP_OP_453J208_122_681_n353), .ICO(DP_OP_453J208_122_681_n351), .CO(
DP_OP_453J208_122_681_n352) );
OAI22X1TS U3552 ( .A0(n2823), .A1(n3543), .B0(n2821), .B1(n3556), .Y(
DP_OP_453J208_122_681_n573) );
CMPR42X1TS U3553 ( .A(DP_OP_453J208_122_681_n544), .B(
DP_OP_453J208_122_681_n330), .C(DP_OP_453J208_122_681_n323), .D(
DP_OP_453J208_122_681_n331), .ICI(DP_OP_453J208_122_681_n320), .S(
DP_OP_453J208_122_681_n317), .ICO(DP_OP_453J208_122_681_n315), .CO(
DP_OP_453J208_122_681_n316) );
CMPR42X1TS U3554 ( .A(DP_OP_453J208_122_681_n832), .B(
DP_OP_453J208_122_681_n829), .C(DP_OP_453J208_122_681_n543), .D(
DP_OP_453J208_122_681_n530), .ICI(DP_OP_453J208_122_681_n322), .S(
DP_OP_453J208_122_681_n308), .ICO(DP_OP_453J208_122_681_n306), .CO(
DP_OP_453J208_122_681_n307) );
CMPR42X1TS U3555 ( .A(DP_OP_453J208_122_681_n321), .B(
DP_OP_453J208_122_681_n318), .C(DP_OP_453J208_122_681_n311), .D(
DP_OP_453J208_122_681_n319), .ICI(DP_OP_453J208_122_681_n315), .S(
DP_OP_453J208_122_681_n305), .ICO(DP_OP_453J208_122_681_n303), .CO(
DP_OP_453J208_122_681_n304) );
NAND2BXLTS U3556 ( .AN(n2393), .B(FPMULT_Op_MY[17]), .Y(n2680) );
NOR2BX1TS U3557 ( .AN(FPMULT_Op_MX[0]), .B(n3179), .Y(n2910) );
OAI22X1TS U3558 ( .A0(n2981), .A1(n2906), .B0(n2889), .B1(n3555), .Y(n2909)
);
CMPR42X1TS U3559 ( .A(DP_OP_453J208_122_681_n525), .B(
DP_OP_453J208_122_681_n538), .C(DP_OP_453J208_122_681_n551), .D(
DP_OP_453J208_122_681_n846), .ICI(DP_OP_453J208_122_681_n410), .S(
DP_OP_453J208_122_681_n403), .ICO(DP_OP_453J208_122_681_n401), .CO(
DP_OP_453J208_122_681_n402) );
CMPR42X1TS U3560 ( .A(DP_OP_453J208_122_681_n412), .B(
DP_OP_453J208_122_681_n845), .C(DP_OP_453J208_122_681_n407), .D(
DP_OP_453J208_122_681_n564), .ICI(DP_OP_453J208_122_681_n577), .S(
DP_OP_453J208_122_681_n400), .ICO(DP_OP_453J208_122_681_n398), .CO(
DP_OP_453J208_122_681_n399) );
INVX2TS U3561 ( .A(n3597), .Y(DP_OP_453J208_122_681_n845) );
CMPR42X1TS U3562 ( .A(DP_OP_453J208_122_681_n537), .B(
DP_OP_453J208_122_681_n394), .C(DP_OP_453J208_122_681_n550), .D(
DP_OP_453J208_122_681_n844), .ICI(DP_OP_453J208_122_681_n563), .S(
DP_OP_453J208_122_681_n392), .ICO(DP_OP_453J208_122_681_n390), .CO(
DP_OP_453J208_122_681_n391) );
CMPR42X1TS U3563 ( .A(DP_OP_453J208_122_681_n843), .B(
DP_OP_453J208_122_681_n401), .C(DP_OP_453J208_122_681_n576), .D(
DP_OP_453J208_122_681_n398), .ICI(DP_OP_453J208_122_681_n402), .S(
DP_OP_453J208_122_681_n389), .ICO(DP_OP_453J208_122_681_n387), .CO(
DP_OP_453J208_122_681_n388) );
OAI22X1TS U3564 ( .A0(n2829), .A1(n3543), .B0(n2827), .B1(n3556), .Y(
DP_OP_453J208_122_681_n576) );
INVX2TS U3565 ( .A(n3602), .Y(DP_OP_453J208_122_681_n843) );
CMPR42X1TS U3566 ( .A(DP_OP_453J208_122_681_n309), .B(
DP_OP_453J208_122_681_n299), .C(DP_OP_453J208_122_681_n310), .D(
DP_OP_453J208_122_681_n307), .ICI(DP_OP_453J208_122_681_n297), .S(
DP_OP_453J208_122_681_n294), .ICO(DP_OP_453J208_122_681_n292), .CO(
DP_OP_453J208_122_681_n293) );
CMPR42X1TS U3567 ( .A(DP_OP_453J208_122_681_n528), .B(
DP_OP_453J208_122_681_n298), .C(DP_OP_453J208_122_681_n288), .D(
DP_OP_453J208_122_681_n296), .ICI(DP_OP_453J208_122_681_n286), .S(
DP_OP_453J208_122_681_n283), .ICO(DP_OP_453J208_122_681_n281), .CO(
DP_OP_453J208_122_681_n282) );
OAI22X1TS U3568 ( .A0(n3478), .A1(n2686), .B0(n2670), .B1(n2224), .Y(n2682)
);
NAND2X1TS U3569 ( .A(FPMULT_Op_MY[0]), .B(FPMULT_Op_MY[12]), .Y(n2625) );
NOR2X1TS U3570 ( .A(DP_OP_453J208_122_681_n1721), .B(n2447), .Y(n3183) );
NAND2X1TS U3571 ( .A(n3197), .B(n2442), .Y(n3173) );
CMPR42X1TS U3572 ( .A(DP_OP_453J208_122_681_n450), .B(
DP_OP_453J208_122_681_n447), .C(DP_OP_453J208_122_681_n570), .D(
DP_OP_453J208_122_681_n583), .ICI(DP_OP_453J208_122_681_n448), .S(
DP_OP_453J208_122_681_n445), .ICO(DP_OP_453J208_122_681_n443), .CO(
DP_OP_453J208_122_681_n444) );
OAI22X1TS U3573 ( .A0(n3465), .A1(FPMULT_Op_MY[21]), .B0(n2398), .B1(n2499),
.Y(n2547) );
OAI22X1TS U3574 ( .A0(n3412), .A1(FPMULT_Op_MX[21]), .B0(n2422), .B1(
FPMULT_Op_MX[22]), .Y(n2548) );
OAI22X1TS U3575 ( .A0(n3465), .A1(n3318), .B0(n2398), .B1(n2396), .Y(n3322)
);
AO21X1TS U3576 ( .A0(n3509), .A1(n2401), .B0(DP_OP_453J208_122_681_n2101),
.Y(n3317) );
OAI22X1TS U3577 ( .A0(n3412), .A1(FPMULT_Op_MX[18]), .B0(n2422), .B1(
FPMULT_Op_MX[19]), .Y(n3337) );
AO21X1TS U3578 ( .A0(n3497), .A1(n2399), .B0(DP_OP_453J208_122_681_n2102),
.Y(n3338) );
OAI22X1TS U3579 ( .A0(n3465), .A1(n3355), .B0(n3339), .B1(n2398), .Y(n3344)
);
OAI22X1TS U3580 ( .A0(n3465), .A1(n3378), .B0(n3362), .B1(n2398), .Y(n3389)
);
OAI22X1TS U3581 ( .A0(n3465), .A1(n3362), .B0(n3355), .B1(n2398), .Y(n3372)
);
INVX2TS U3582 ( .A(n2820), .Y(n2728) );
CMPR42X1TS U3583 ( .A(DP_OP_453J208_122_681_n1748), .B(
DP_OP_453J208_122_681_n815), .C(DP_OP_453J208_122_681_n250), .D(
DP_OP_453J208_122_681_n497), .ICI(DP_OP_453J208_122_681_n484), .S(
DP_OP_453J208_122_681_n243), .ICO(DP_OP_453J208_122_681_n241), .CO(
DP_OP_453J208_122_681_n242) );
INVX2TS U3584 ( .A(n4021), .Y(DP_OP_453J208_122_681_n815) );
OAI22X1TS U3585 ( .A0(n2730), .A1(n2561), .B0(n2728), .B1(n2739), .Y(
DP_OP_453J208_122_681_n484) );
INVX2TS U3586 ( .A(DP_OP_453J208_122_681_n1748), .Y(n3867) );
AOI21X1TS U3587 ( .A0(n3831), .A1(n2521), .B0(n3830), .Y(n3832) );
INVX2TS U3588 ( .A(n3829), .Y(n3830) );
INVX2TS U3589 ( .A(n3811), .Y(n3831) );
INVX2TS U3590 ( .A(n3837), .Y(n3808) );
CMPR42X1TS U3591 ( .A(DP_OP_453J208_122_681_n268), .B(
DP_OP_453J208_122_681_n273), .C(DP_OP_453J208_122_681_n265), .D(
DP_OP_453J208_122_681_n455), .ICI(DP_OP_453J208_122_681_n269), .S(
DP_OP_453J208_122_681_n262), .ICO(DP_OP_453J208_122_681_n260), .CO(
DP_OP_453J208_122_681_n261) );
INVX2TS U3592 ( .A(n3707), .Y(DP_OP_453J208_122_681_n455) );
CMPR42X1TS U3593 ( .A(DP_OP_453J208_122_681_n332), .B(
DP_OP_453J208_122_681_n340), .C(DP_OP_453J208_122_681_n461), .D(
DP_OP_453J208_122_681_n329), .ICI(DP_OP_453J208_122_681_n336), .S(
DP_OP_453J208_122_681_n326), .ICO(DP_OP_453J208_122_681_n324), .CO(
DP_OP_453J208_122_681_n325) );
INVX2TS U3594 ( .A(n3692), .Y(DP_OP_453J208_122_681_n461) );
NAND2X1TS U3595 ( .A(n3720), .B(n2515), .Y(n3567) );
OA21XLTS U3596 ( .A0(n3565), .A1(n3716), .B0(n3719), .Y(n3566) );
CMPR42X1TS U3597 ( .A(DP_OP_453J208_122_681_n344), .B(
DP_OP_453J208_122_681_n352), .C(DP_OP_453J208_122_681_n462), .D(
DP_OP_453J208_122_681_n341), .ICI(DP_OP_453J208_122_681_n348), .S(
DP_OP_453J208_122_681_n338), .ICO(DP_OP_453J208_122_681_n336), .CO(
DP_OP_453J208_122_681_n337) );
INVX2TS U3598 ( .A(n3689), .Y(DP_OP_453J208_122_681_n462) );
AOI21X1TS U3599 ( .A0(n3564), .A1(n3641), .B0(n3563), .Y(n3639) );
CMPR42X1TS U3600 ( .A(DP_OP_453J208_122_681_n368), .B(
DP_OP_453J208_122_681_n377), .C(DP_OP_453J208_122_681_n464), .D(
DP_OP_453J208_122_681_n365), .ICI(DP_OP_453J208_122_681_n373), .S(
DP_OP_453J208_122_681_n362), .ICO(DP_OP_453J208_122_681_n360), .CO(
DP_OP_453J208_122_681_n361) );
NAND2BXLTS U3601 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n4168) );
NAND3XLTS U3602 ( .A(n5620), .B(n4166), .C(FPADDSUB_intDX_EWSW[8]), .Y(n4167) );
XNOR2X1TS U3603 ( .A(n2301), .B(FPMULT_Op_MX[2]), .Y(n2983) );
OAI22X1TS U3604 ( .A0(n2981), .A1(n2934), .B0(n2980), .B1(n3555), .Y(n2987)
);
ADDHX1TS U3605 ( .A(n2938), .B(n2937), .CO(n2996), .S(n2939) );
OAI22X1TS U3606 ( .A0(n2981), .A1(n2942), .B0(n2934), .B1(n3555), .Y(n2938)
);
OAI22X1TS U3607 ( .A0(n3123), .A1(n2461), .B0(n2431), .B1(n2974), .Y(n2990)
);
OAI22X1TS U3608 ( .A0(n3123), .A1(n2912), .B0(n2432), .B1(n2892), .Y(n2921)
);
OAI22X1TS U3609 ( .A0(n3123), .A1(n2977), .B0(n2431), .B1(n2912), .Y(n3009)
);
OAI22X1TS U3610 ( .A0(n3123), .A1(n2978), .B0(n2431), .B1(n2977), .Y(n3012)
);
NOR2X2TS U3611 ( .A(n3217), .B(n3208), .Y(n3197) );
INVX2TS U3612 ( .A(n3203), .Y(n3189) );
OAI21X1TS U3613 ( .A0(n3254), .A1(n3262), .B0(n3255), .Y(n3037) );
CMPR42X1TS U3614 ( .A(DP_OP_453J208_122_681_n292), .B(
DP_OP_453J208_122_681_n293), .C(DP_OP_453J208_122_681_n283), .D(
DP_OP_453J208_122_681_n457), .ICI(DP_OP_453J208_122_681_n289), .S(
DP_OP_453J208_122_681_n280), .ICO(DP_OP_453J208_122_681_n278), .CO(
DP_OP_453J208_122_681_n279) );
INVX2TS U3615 ( .A(n3702), .Y(DP_OP_453J208_122_681_n457) );
OAI21X1TS U3616 ( .A0(n3778), .A1(n3772), .B0(n3779), .Y(n3570) );
OAI21X1TS U3617 ( .A0(n3786), .A1(n3783), .B0(n3787), .Y(n3592) );
OAI22X1TS U3618 ( .A0(n3509), .A1(n3508), .B0(n2401), .B1(n3507), .Y(n3518)
);
NOR2X1TS U3619 ( .A(n3030), .B(n3029), .Y(n3266) );
NOR2X1TS U3620 ( .A(n3557), .B(n4741), .Y(n3680) );
NOR2X2TS U3621 ( .A(n3034), .B(n3033), .Y(n3261) );
OAI21X2TS U3622 ( .A0(n3268), .A1(n3273), .B0(n3269), .Y(n3259) );
NOR2X2TS U3623 ( .A(n3268), .B(n3266), .Y(n3260) );
NAND2X1TS U3624 ( .A(DP_OP_453J208_122_681_n438), .B(
DP_OP_453J208_122_681_n444), .Y(n3673) );
OAI21X1TS U3625 ( .A0(n3676), .A1(n2472), .B0(n3677), .Y(n3674) );
INVX2TS U3626 ( .A(n3238), .Y(n3246) );
INVX2TS U3627 ( .A(n3245), .Y(n3239) );
NAND2X1TS U3628 ( .A(n3166), .B(n3165), .Y(n3209) );
AOI21X2TS U3629 ( .A0(n3658), .A1(n2514), .B0(n3562), .Y(n3656) );
NOR2X1TS U3630 ( .A(DP_OP_453J208_122_681_n397), .B(
DP_OP_453J208_122_681_n405), .Y(n3652) );
NAND2X1TS U3631 ( .A(DP_OP_453J208_122_681_n397), .B(
DP_OP_453J208_122_681_n405), .Y(n3653) );
XOR3X1TS U3632 ( .A(n3183), .B(n3182), .C(n3181), .Y(n3184) );
NOR2X1TS U3633 ( .A(DP_OP_453J208_122_681_n1721), .B(
DP_OP_453J208_122_681_n1601), .Y(n3182) );
AO21XLTS U3634 ( .A0(n3180), .A1(n2402), .B0(DP_OP_453J208_122_681_n1721),
.Y(n3181) );
INVX2TS U3635 ( .A(n3232), .Y(n3222) );
NAND2X1TS U3636 ( .A(n3160), .B(n3159), .Y(n3227) );
AOI21X2TS U3637 ( .A0(n3666), .A1(n2512), .B0(n3561), .Y(n3664) );
NOR2X1TS U3638 ( .A(DP_OP_453J208_122_681_n416), .B(
DP_OP_453J208_122_681_n423), .Y(n3660) );
NAND2X1TS U3639 ( .A(DP_OP_453J208_122_681_n416), .B(
DP_OP_453J208_122_681_n423), .Y(n3661) );
OAI21X1TS U3640 ( .A0(n3251), .A1(n3261), .B0(n3262), .Y(n3252) );
INVX2TS U3641 ( .A(n3259), .Y(n3251) );
NOR2X1TS U3642 ( .A(n3250), .B(n3261), .Y(n3253) );
INVX2TS U3643 ( .A(n3260), .Y(n3250) );
NAND2X1TS U3644 ( .A(n3036), .B(n3035), .Y(n3255) );
NOR2X1TS U3645 ( .A(DP_OP_453J208_122_681_n445), .B(n3559), .Y(n3676) );
NOR2X1TS U3646 ( .A(n3412), .B(FPMULT_Op_MX[22]), .Y(n2539) );
AO21X1TS U3647 ( .A0(n3465), .A1(n2398), .B0(n2499), .Y(n2545) );
NOR2X2TS U3648 ( .A(n3900), .B(DP_OP_453J208_122_681_n1766), .Y(n3913) );
NAND2X1TS U3649 ( .A(n3900), .B(DP_OP_453J208_122_681_n1766), .Y(n3911) );
CMPR42X1TS U3650 ( .A(DP_OP_453J208_122_681_n237), .B(
DP_OP_453J208_122_681_n483), .C(DP_OP_453J208_122_681_n241), .D(
DP_OP_453J208_122_681_n242), .ICI(DP_OP_453J208_122_681_n238), .S(
DP_OP_453J208_122_681_n235), .ICO(DP_OP_453J208_122_681_n233), .CO(
DP_OP_453J208_122_681_n234) );
OAI22X1TS U3651 ( .A0(n2728), .A1(n2561), .B0(n3868), .B1(n2739), .Y(
DP_OP_453J208_122_681_n483) );
OAI21X2TS U3652 ( .A0(n3881), .A1(n3880), .B0(n3879), .Y(n3915) );
NOR2X2TS U3653 ( .A(n3881), .B(n3878), .Y(n3910) );
NOR2X2TS U3654 ( .A(DP_OP_453J208_122_681_n239), .B(
DP_OP_453J208_122_681_n235), .Y(n3861) );
INVX2TS U3655 ( .A(n3862), .Y(n3838) );
NOR2X2TS U3656 ( .A(n3845), .B(n3844), .Y(n3881) );
NOR2X1TS U3657 ( .A(n3817), .B(n3815), .Y(n3606) );
OAI21X1TS U3658 ( .A0(n3817), .A1(n3814), .B0(n3818), .Y(n3605) );
NAND2X1TS U3659 ( .A(n3845), .B(n3844), .Y(n3879) );
NAND2X1TS U3660 ( .A(n3614), .B(n2519), .Y(n3576) );
AOI21X1TS U3661 ( .A0(n3574), .A1(n2519), .B0(n3831), .Y(n3575) );
NOR2X2TS U3662 ( .A(n3608), .B(n3607), .Y(n3878) );
NAND2X1TS U3663 ( .A(n3608), .B(n3607), .Y(n3880) );
NOR2X2TS U3664 ( .A(n3604), .B(n3603), .Y(n3817) );
NAND2X1TS U3665 ( .A(n3604), .B(n3603), .Y(n3818) );
INVX2TS U3666 ( .A(n3827), .Y(n3614) );
NAND2X2TS U3667 ( .A(DP_OP_453J208_122_681_n254), .B(
DP_OP_453J208_122_681_n261), .Y(n3833) );
OAI21X2TS U3668 ( .A0(n3622), .A1(n3793), .B0(n3623), .Y(n3837) );
NOR2X2TS U3669 ( .A(n3602), .B(n3601), .Y(n3815) );
NAND2X1TS U3670 ( .A(n3602), .B(n3601), .Y(n3814) );
INVX2TS U3671 ( .A(n3617), .Y(n3816) );
INVX2TS U3672 ( .A(n3793), .Y(n3621) );
NOR2X2TS U3673 ( .A(DP_OP_453J208_122_681_n262), .B(
DP_OP_453J208_122_681_n270), .Y(n3622) );
NAND2X1TS U3674 ( .A(n3597), .B(n3596), .Y(n3629) );
INVX2TS U3675 ( .A(n3796), .Y(n3628) );
NOR2X1TS U3676 ( .A(n3587), .B(n3586), .Y(n3759) );
NAND2X1TS U3677 ( .A(n3587), .B(n3586), .Y(n3760) );
NOR2X2TS U3678 ( .A(DP_OP_453J208_122_681_n326), .B(
DP_OP_453J208_122_681_n337), .Y(n3735) );
NAND2X1TS U3679 ( .A(DP_OP_453J208_122_681_n326), .B(
DP_OP_453J208_122_681_n337), .Y(n3736) );
INVX2TS U3680 ( .A(n3725), .Y(n3734) );
NOR2X2TS U3681 ( .A(DP_OP_453J208_122_681_n338), .B(
DP_OP_453J208_122_681_n349), .Y(n3733) );
NAND2X1TS U3682 ( .A(DP_OP_453J208_122_681_n350), .B(
DP_OP_453J208_122_681_n361), .Y(n3719) );
INVX2TS U3683 ( .A(n3565), .Y(n3720) );
NAND2X1TS U3684 ( .A(DP_OP_453J208_122_681_n362), .B(
DP_OP_453J208_122_681_n374), .Y(n3716) );
INVX2TS U3685 ( .A(n3639), .Y(n3718) );
NOR2X2TS U3686 ( .A(DP_OP_453J208_122_681_n280), .B(
DP_OP_453J208_122_681_n290), .Y(n3778) );
INVX2TS U3687 ( .A(n3771), .Y(n3774) );
INVX2TS U3688 ( .A(n3769), .Y(n3770) );
NOR2X2TS U3689 ( .A(n3591), .B(n3590), .Y(n3786) );
NAND2X1TS U3690 ( .A(n3591), .B(n3590), .Y(n3787) );
OAI21X2TS U3691 ( .A0(n3754), .A1(n3751), .B0(n3755), .Y(n3771) );
NOR2X2TS U3692 ( .A(n3754), .B(n3743), .Y(n3769) );
NAND2X1TS U3693 ( .A(n3589), .B(n3588), .Y(n3783) );
NAND2BXLTS U3694 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n4166) );
NAND2X4TS U3695 ( .A(n2297), .B(n3555), .Y(n2981) );
ADDFX2TS U3696 ( .A(n3007), .B(n3006), .CI(n3005), .CO(n3029), .S(n3026) );
NOR2X2TS U3697 ( .A(DP_OP_453J208_122_681_n375), .B(
DP_OP_453J208_122_681_n385), .Y(n3642) );
NOR2X2TS U3698 ( .A(DP_OP_453J208_122_681_n386), .B(
DP_OP_453J208_122_681_n396), .Y(n3647) );
NAND2X2TS U3699 ( .A(DP_OP_453J208_122_681_n386), .B(
DP_OP_453J208_122_681_n396), .Y(n3648) );
NAND2X1TS U3700 ( .A(DP_OP_453J208_122_681_n375), .B(
DP_OP_453J208_122_681_n385), .Y(n3643) );
INVX2TS U3701 ( .A(n3620), .Y(n3794) );
INVX2TS U3702 ( .A(n3627), .Y(n3798) );
NAND2X1TS U3703 ( .A(n3595), .B(n3594), .Y(n3796) );
INVX2TS U3704 ( .A(n4645), .Y(n4551) );
NAND2X1TS U3705 ( .A(n3030), .B(n3029), .Y(n3273) );
XOR2X1TS U3706 ( .A(FPMULT_Op_MX[0]), .B(n2392), .Y(n2818) );
INVX2TS U3707 ( .A(n3266), .Y(n3274) );
INVX2TS U3708 ( .A(n3273), .Y(n3267) );
NAND2X1TS U3709 ( .A(n3032), .B(n3031), .Y(n3269) );
NOR2X2TS U3710 ( .A(n3032), .B(n3031), .Y(n3268) );
INVX2TS U3711 ( .A(n3249), .Y(n3276) );
XNOR2X1TS U3712 ( .A(n3667), .B(n3666), .Y(n3698) );
NAND2X1TS U3713 ( .A(n2512), .B(n3665), .Y(n3667) );
CLKXOR2X2TS U3714 ( .A(n3237), .B(n3236), .Y(n3699) );
INVX2TS U3715 ( .A(n3233), .Y(n3235) );
XNOR2X1TS U3716 ( .A(n3659), .B(n3658), .Y(n3703) );
NAND2X1TS U3717 ( .A(n2514), .B(n3657), .Y(n3659) );
CLKXOR2X2TS U3718 ( .A(n3221), .B(n3220), .Y(n3704) );
NAND2X1TS U3719 ( .A(n3219), .B(n3218), .Y(n3220) );
INVX2TS U3720 ( .A(n3217), .Y(n3219) );
NAND2X1TS U3721 ( .A(n3649), .B(n3648), .Y(n3650) );
INVX2TS U3722 ( .A(n3647), .Y(n3649) );
CLKXOR2X2TS U3723 ( .A(n3205), .B(n3204), .Y(n3709) );
NAND2X1TS U3724 ( .A(n2450), .B(n3203), .Y(n3204) );
XNOR2X1TS U3725 ( .A(n3718), .B(n3640), .Y(n3713) );
NAND2X1TS U3726 ( .A(n2515), .B(n3716), .Y(n3640) );
CLKXOR2X2TS U3727 ( .A(n3188), .B(n3187), .Y(n3714) );
NAND2X1TS U3728 ( .A(n2448), .B(n3186), .Y(n3187) );
NAND2X1TS U3729 ( .A(n3185), .B(n3184), .Y(n3186) );
NAND2X1TS U3730 ( .A(n4008), .B(n4007), .Y(n4018) );
OAI21X1TS U3731 ( .A0(n4006), .A1(n4005), .B0(n4004), .Y(n4020) );
INVX2TS U3732 ( .A(n4000), .Y(n3987) );
INVX2TS U3733 ( .A(n3990), .Y(n3991) );
NOR2X1TS U3734 ( .A(n3994), .B(n3993), .Y(n4005) );
NAND2X1TS U3735 ( .A(n3994), .B(n3993), .Y(n4004) );
NAND2X1TS U3736 ( .A(n3982), .B(n3981), .Y(n3990) );
INVX2TS U3737 ( .A(n3974), .Y(n3962) );
NOR2X1TS U3738 ( .A(n3968), .B(DP_OP_453J208_122_681_n1756), .Y(n3979) );
NAND2X1TS U3739 ( .A(n3968), .B(DP_OP_453J208_122_681_n1756), .Y(n3978) );
NAND2X1TS U3740 ( .A(n3957), .B(n3956), .Y(n3965) );
INVX2TS U3741 ( .A(n3949), .Y(n3937) );
NOR2X1TS U3742 ( .A(n3943), .B(DP_OP_453J208_122_681_n1760), .Y(n3954) );
NAND2X1TS U3743 ( .A(n3943), .B(DP_OP_453J208_122_681_n1760), .Y(n3953) );
NAND2X1TS U3744 ( .A(n3932), .B(n3931), .Y(n3940) );
NOR2X1TS U3745 ( .A(n3918), .B(DP_OP_453J208_122_681_n1764), .Y(n3929) );
NAND2X1TS U3746 ( .A(n3918), .B(DP_OP_453J208_122_681_n1764), .Y(n3928) );
NAND2X1TS U3747 ( .A(n3901), .B(n3911), .Y(n3902) );
AOI21X1TS U3748 ( .A0(n3899), .A1(n3917), .B0(n3898), .Y(n3903) );
NAND2X1TS U3749 ( .A(n2520), .B(n3875), .Y(n3876) );
NAND2X1TS U3750 ( .A(DP_OP_453J208_122_681_n234), .B(n3874), .Y(n3875) );
CLKXOR2X2TS U3751 ( .A(n3886), .B(n3885), .Y(n3887) );
NAND2X1TS U3752 ( .A(n3884), .B(n3912), .Y(n3885) );
AOI21X1TS U3753 ( .A0(n3917), .A1(n3910), .B0(n3915), .Y(n3886) );
INVX2TS U3754 ( .A(n3909), .Y(n3884) );
NAND2X1TS U3755 ( .A(n3840), .B(n3860), .Y(n3841) );
AOI21X1TS U3756 ( .A0(n3865), .A1(n3839), .B0(n3838), .Y(n3842) );
INVX2TS U3757 ( .A(n3861), .Y(n3840) );
XNOR2X1TS U3758 ( .A(n3848), .B(n3847), .Y(n3849) );
NAND2X1TS U3759 ( .A(n3846), .B(n3879), .Y(n3847) );
INVX2TS U3760 ( .A(n3881), .Y(n3846) );
NAND2X1TS U3761 ( .A(n2521), .B(n3829), .Y(n3579) );
AOI21X1TS U3762 ( .A0(n3865), .A1(n3578), .B0(n3577), .Y(n3580) );
NAND2X1TS U3763 ( .A(n3609), .B(n3880), .Y(n3610) );
INVX2TS U3764 ( .A(n3878), .Y(n3609) );
NAND2X1TS U3765 ( .A(n2519), .B(n3811), .Y(n3812) );
NAND2X1TS U3766 ( .A(n3819), .B(n3818), .Y(n3820) );
INVX2TS U3767 ( .A(n3817), .Y(n3819) );
XOR2X1TS U3768 ( .A(n3616), .B(n3615), .Y(n3805) );
NAND2X1TS U3769 ( .A(n3614), .B(n3833), .Y(n3615) );
AOI21X1TS U3770 ( .A0(n3865), .A1(n3828), .B0(n3837), .Y(n3616) );
XOR2X1TS U3771 ( .A(n3816), .B(n3619), .Y(n3804) );
NAND2X1TS U3772 ( .A(n3618), .B(n3814), .Y(n3619) );
INVX2TS U3773 ( .A(n3815), .Y(n3618) );
XOR2X1TS U3774 ( .A(n3626), .B(n3625), .Y(n3802) );
NAND2X1TS U3775 ( .A(n3624), .B(n3623), .Y(n3625) );
AOI21X1TS U3776 ( .A0(n3865), .A1(n3794), .B0(n3621), .Y(n3626) );
INVX2TS U3777 ( .A(n3622), .Y(n3624) );
XOR2X1TS U3778 ( .A(n3631), .B(n3630), .Y(n3801) );
NAND2X1TS U3779 ( .A(n2511), .B(n3629), .Y(n3630) );
AOI21X1TS U3780 ( .A0(n3798), .A1(n2510), .B0(n3628), .Y(n3631) );
AO21XLTS U3781 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n5243), .B0(n5198),
.Y(n2236) );
OAI21XLTS U3782 ( .A0(n5581), .A1(n5240), .B0(n5208), .Y(n5198) );
NAND2X1TS U3783 ( .A(n3756), .B(n3755), .Y(n3757) );
AOI21X1TS U3784 ( .A0(n3776), .A1(n3753), .B0(n3752), .Y(n3758) );
XOR2X1TS U3785 ( .A(n3763), .B(n3762), .Y(n3764) );
XNOR2X2TS U3786 ( .A(n3739), .B(n3738), .Y(n3742) );
NAND2X1TS U3787 ( .A(n3737), .B(n3736), .Y(n3738) );
OAI21X1TS U3788 ( .A0(n3734), .A1(n3733), .B0(n3732), .Y(n3739) );
INVX2TS U3789 ( .A(n3735), .Y(n3737) );
CLKAND2X2TS U3790 ( .A(n2473), .B(n3740), .Y(n2474) );
NOR2BX2TS U3791 ( .AN(n2200), .B(n2224), .Y(n3723) );
CLKXOR2X2TS U3792 ( .A(n3722), .B(n3721), .Y(n3724) );
NAND2X1TS U3793 ( .A(n3720), .B(n3719), .Y(n3721) );
AOI21X1TS U3794 ( .A0(n3718), .A1(n2515), .B0(n3717), .Y(n3722) );
INVX2TS U3795 ( .A(n3716), .Y(n3717) );
XOR2X1TS U3796 ( .A(n3782), .B(n3781), .Y(n3792) );
NAND2X1TS U3797 ( .A(n3780), .B(n3779), .Y(n3781) );
AOI21X1TS U3798 ( .A0(n3777), .A1(n3776), .B0(n3775), .Y(n3782) );
INVX2TS U3799 ( .A(n3778), .Y(n3780) );
XNOR2X1TS U3800 ( .A(n3790), .B(n3789), .Y(n3791) );
NAND2X1TS U3801 ( .A(n3788), .B(n3787), .Y(n3789) );
XOR2X1TS U3802 ( .A(n3635), .B(n3634), .Y(n3767) );
NAND2X1TS U3803 ( .A(n3633), .B(n3772), .Y(n3634) );
AOI21X1TS U3804 ( .A0(n3776), .A1(n3769), .B0(n3771), .Y(n3635) );
INVX2TS U3805 ( .A(n3773), .Y(n3633) );
XOR2X1TS U3806 ( .A(n3785), .B(n3638), .Y(n3766) );
AO21XLTS U3807 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n5243), .B0(n5195),
.Y(n2237) );
OAI21XLTS U3808 ( .A0(n5580), .A1(n5240), .B0(n5208), .Y(n5195) );
OAI32X1TS U3809 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n5626), .B0(n5542), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4528) );
AOI211X1TS U3810 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n4537), .B0(n4538), .C0(n4493), .Y(n4535) );
INVX2TS U3811 ( .A(n4537), .Y(n4508) );
NAND2X1TS U3812 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n4533), .Y(n4506) );
AOI211X1TS U3813 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n5696), .B0(n4147),
.C0(n4145), .Y(n4198) );
CLKXOR2X2TS U3814 ( .A(n3196), .B(n3195), .Y(n3712) );
NAND2X1TS U3815 ( .A(n2449), .B(n3194), .Y(n3195) );
XNOR2X1TS U3816 ( .A(n3865), .B(n3795), .Y(n3800) );
NAND2X1TS U3817 ( .A(n3794), .B(n3793), .Y(n3795) );
XNOR2X1TS U3818 ( .A(n3798), .B(n3797), .Y(n3799) );
NAND3XLTS U3819 ( .A(n2376), .B(n3530), .C(n2206), .Y(n4282) );
NOR2X1TS U3820 ( .A(n4341), .B(n4287), .Y(n4315) );
BUFX3TS U3821 ( .A(n4350), .Y(n4347) );
INVX4TS U3822 ( .A(n4312), .Y(n4349) );
NAND2X1TS U3823 ( .A(n3274), .B(n3273), .Y(n3275) );
XNOR2X1TS U3824 ( .A(n3314), .B(n3313), .Y(n4027) );
XNOR2X1TS U3825 ( .A(n3295), .B(n3294), .Y(n4754) );
NAND2X1TS U3826 ( .A(n2490), .B(n3293), .Y(n3294) );
XOR2X1TS U3827 ( .A(n3292), .B(n3291), .Y(n4755) );
INVX2TS U3828 ( .A(n3536), .Y(n4354) );
XOR2X1TS U3829 ( .A(n3287), .B(n3286), .Y(n4756) );
NAND2X1TS U3830 ( .A(n3285), .B(n3284), .Y(n3286) );
NAND2X1TS U3831 ( .A(n3699), .B(n3698), .Y(n4707) );
NAND2X1TS U3832 ( .A(n3704), .B(n3703), .Y(n4717) );
NAND2X1TS U3833 ( .A(n3709), .B(n3708), .Y(n4727) );
AOI22X1TS U3834 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(n5569), .B0(n5425), .B1(
n5424), .Y(n5431) );
XOR2X1TS U3835 ( .A(n4020), .B(n4009), .Y(n2500) );
NAND2X1TS U3836 ( .A(n3714), .B(n3713), .Y(n4796) );
INVX2TS U3837 ( .A(n4315), .Y(n4312) );
XOR2X1TS U3838 ( .A(n3306), .B(n3305), .Y(n4733) );
NOR2X1TS U3839 ( .A(n4013), .B(n2525), .Y(n4017) );
NOR2X1TS U3840 ( .A(n4014), .B(n2525), .Y(n4015) );
AOI21X1TS U3841 ( .A0(n4020), .A1(n2501), .B0(n4019), .Y(n4024) );
NAND2X1TS U3842 ( .A(n3995), .B(n4004), .Y(n3996) );
NAND2X1TS U3843 ( .A(n2509), .B(n3990), .Y(n3983) );
XOR2X1TS U3844 ( .A(n3980), .B(n3970), .Y(n3975) );
NAND2X1TS U3845 ( .A(n3969), .B(n3978), .Y(n3970) );
NAND2X1TS U3846 ( .A(n2507), .B(n3965), .Y(n3958) );
NAND2X1TS U3847 ( .A(n3944), .B(n3953), .Y(n3945) );
NAND2X1TS U3848 ( .A(n2505), .B(n3940), .Y(n3933) );
NAND2X1TS U3849 ( .A(n3919), .B(n3928), .Y(n3920) );
INVX2TS U3850 ( .A(n3924), .Y(n3906) );
INVX2TS U3851 ( .A(n4013), .Y(n3895) );
INVX2TS U3852 ( .A(n4800), .Y(n3803) );
NAND2X1TS U3853 ( .A(n3802), .B(n3801), .Y(n4800) );
AOI22X1TS U3854 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n5579), .B0(n5439), .B1(
n5437), .Y(n5447) );
AO21XLTS U3855 ( .A0(n4902), .A1(begin_operation), .B0(n4037), .Y(n4132) );
AOI22X1TS U3856 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n4121), .B0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n5530),
.Y(n3534) );
AOI222X2TS U3857 ( .A0(n2380), .A1(FPADDSUB_DMP_SFG[2]), .B0(n2380), .B1(
n5316), .C0(FPADDSUB_DMP_SFG[2]), .C1(n5316), .Y(n5321) );
NAND2X4TS U3858 ( .A(n3534), .B(n4118), .Y(n3535) );
BUFX4TS U3859 ( .A(n3535), .Y(n4434) );
BUFX4TS U3860 ( .A(n4385), .Y(n5033) );
INVX2TS U3861 ( .A(n4779), .Y(n3750) );
NAND2X1TS U3862 ( .A(n3765), .B(n3764), .Y(n4774) );
INVX2TS U3863 ( .A(n4769), .Y(n3768) );
NOR2X1TS U3864 ( .A(n3792), .B(n3791), .Y(n4757) );
NAND2X1TS U3865 ( .A(n3792), .B(n3791), .Y(n4758) );
NAND2X1TS U3866 ( .A(n3767), .B(n3766), .Y(n4769) );
AOI2BB2X1TS U3867 ( .B0(n4149), .B1(n4198), .A0N(n4148), .A1N(n4147), .Y(
n4204) );
XOR2X1TS U3868 ( .A(n3311), .B(n3310), .Y(n4732) );
XNOR2X2TS U3869 ( .A(n3282), .B(n3281), .Y(n4743) );
NAND2X1TS U3870 ( .A(n3280), .B(n3279), .Y(n3281) );
OAI21X1TS U3871 ( .A0(n3287), .A1(n3283), .B0(n3284), .Y(n3282) );
NOR2X1TS U3872 ( .A(n3800), .B(n3799), .Y(n4763) );
NAND2X1TS U3873 ( .A(n3800), .B(n3799), .Y(n4764) );
BUFX4TS U3874 ( .A(n4680), .Y(n4794) );
INVX4TS U3875 ( .A(n4312), .Y(n4345) );
BUFX4TS U3876 ( .A(n4971), .Y(n4977) );
NOR3X1TS U3877 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n5628),
.C(n4892), .Y(n4029) );
INVX4TS U3878 ( .A(n4554), .Y(n4648) );
BUFX3TS U3879 ( .A(n4977), .Y(n4244) );
INVX4TS U3880 ( .A(n4990), .Y(n4249) );
CLKBUFX2TS U3881 ( .A(n4990), .Y(n4973) );
AOI222X1TS U3882 ( .A0(n4350), .A1(cordic_result[22]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[22]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[22]), .Y(n4325) );
AOI222X1TS U3883 ( .A0(n4350), .A1(cordic_result[15]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[15]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[15]), .Y(n4343) );
AOI222X1TS U3884 ( .A0(n4350), .A1(cordic_result[18]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[18]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[18]), .Y(n4344) );
AOI222X1TS U3885 ( .A0(n4284), .A1(cordic_result[21]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[21]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[21]), .Y(n4323) );
AOI222X1TS U3886 ( .A0(n4350), .A1(cordic_result[19]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[19]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[19]), .Y(n4317) );
AOI222X1TS U3887 ( .A0(n4284), .A1(cordic_result[20]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[20]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[20]), .Y(n4322) );
AOI222X1TS U3888 ( .A0(n4350), .A1(cordic_result[17]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[17]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[17]), .Y(n4351) );
AOI222X1TS U3889 ( .A0(n4341), .A1(cordic_result[6]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[6]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[6]), .Y(n4334)
);
AOI222X1TS U3890 ( .A0(n4347), .A1(cordic_result[13]), .B0(n4286), .B1(
FPSENCOS_d_ff_Yn[13]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[13]), .Y(n4337) );
AOI222X1TS U3891 ( .A0(n4350), .A1(cordic_result[16]), .B0(n4286), .B1(
FPSENCOS_d_ff_Yn[16]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[16]), .Y(n4339) );
AOI222X1TS U3892 ( .A0(n4341), .A1(cordic_result[8]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[8]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[8]), .Y(n4340)
);
AOI222X1TS U3893 ( .A0(n4347), .A1(cordic_result[11]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[11]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[11]), .Y(n4332) );
AOI222X1TS U3894 ( .A0(n4347), .A1(cordic_result[14]), .B0(n4286), .B1(
FPSENCOS_d_ff_Yn[14]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[14]), .Y(n4336) );
AOI222X1TS U3895 ( .A0(n4347), .A1(cordic_result[10]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[10]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[10]), .Y(n4346) );
AOI222X1TS U3896 ( .A0(n4347), .A1(cordic_result[12]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[12]), .C0(n4349), .C1(FPSENCOS_d_ff_Xn[12]), .Y(n4348) );
AOI222X1TS U3897 ( .A0(n4341), .A1(cordic_result[9]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[9]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[9]), .Y(n4342)
);
AOI222X1TS U3898 ( .A0(n4341), .A1(cordic_result[7]), .B0(n4331), .B1(
FPSENCOS_d_ff_Yn[7]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[7]), .Y(n4335)
);
AOI222X1TS U3899 ( .A0(n4284), .A1(cordic_result[30]), .B0(n4326), .B1(n2326), .C0(n4345), .C1(n2324), .Y(n4320) );
AOI222X1TS U3900 ( .A0(n4284), .A1(cordic_result[29]), .B0(n4326), .B1(n2327), .C0(n4345), .C1(n2337), .Y(n4321) );
AOI222X1TS U3901 ( .A0(n4350), .A1(cordic_result[28]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[28]), .C0(n4345), .C1(FPSENCOS_d_ff_Xn[28]), .Y(n4318) );
AOI222X1TS U3902 ( .A0(n4350), .A1(cordic_result[27]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[27]), .C0(n4349), .C1(n2334), .Y(n4327) );
AOI222X1TS U3903 ( .A0(n4350), .A1(cordic_result[26]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[26]), .C0(n4349), .C1(n2335), .Y(n4319) );
AOI222X1TS U3904 ( .A0(n4350), .A1(cordic_result[25]), .B0(n4326), .B1(n2328), .C0(n4349), .C1(n2338), .Y(n4313) );
AOI222X1TS U3905 ( .A0(n4350), .A1(cordic_result[24]), .B0(n4326), .B1(
FPSENCOS_d_ff_Yn[24]), .C0(n4315), .C1(n2336), .Y(n4316) );
AOI222X1TS U3906 ( .A0(n4347), .A1(cordic_result[23]), .B0(n4326), .B1(n2329), .C0(n4349), .C1(n2325), .Y(n4324) );
MX2X1TS U3907 ( .A(FPMULT_P_Sgf[11]), .B(n4744), .S0(n4751), .Y(n1564) );
MX2X1TS U3908 ( .A(FPMULT_P_Sgf[12]), .B(n2493), .S0(n4751), .Y(n1565) );
MX2X1TS U3909 ( .A(FPMULT_P_Sgf[13]), .B(n4752), .S0(n4751), .Y(n1566) );
AO22XLTS U3910 ( .A0(n4909), .A1(n5414), .B0(n4911), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2146) );
MX2X1TS U3911 ( .A(FPMULT_P_Sgf[15]), .B(n4700), .S0(n4680), .Y(n1568) );
MX2X1TS U3912 ( .A(FPMULT_P_Sgf[16]), .B(n4706), .S0(n4680), .Y(n1569) );
XOR2X1TS U3913 ( .A(n4705), .B(n4704), .Y(n4706) );
MX2X1TS U3914 ( .A(FPMULT_P_Sgf[17]), .B(n4710), .S0(n4680), .Y(n1570) );
XNOR2X1TS U3915 ( .A(n4709), .B(n4708), .Y(n4710) );
NAND2X1TS U3916 ( .A(n2497), .B(n4707), .Y(n4709) );
XNOR2X1TS U3917 ( .A(n4719), .B(n4718), .Y(n4720) );
NAND2X1TS U3918 ( .A(n2513), .B(n4717), .Y(n4719) );
XOR2X1TS U3919 ( .A(n4725), .B(n4724), .Y(n4726) );
NAND2X1TS U3920 ( .A(n4723), .B(n4722), .Y(n4725) );
XNOR2X1TS U3921 ( .A(n4729), .B(n4728), .Y(n4730) );
NAND2X1TS U3922 ( .A(n2452), .B(n4727), .Y(n4729) );
AOI21X1TS U3923 ( .A0(n4003), .A1(n4016), .B0(n4002), .Y(n4010) );
XNOR2X1TS U3924 ( .A(n4798), .B(n4797), .Y(n4799) );
NAND2X1TS U3925 ( .A(n2453), .B(n4796), .Y(n4798) );
XOR2X1TS U3926 ( .A(n4715), .B(n4714), .Y(n4716) );
NAND2X1TS U3927 ( .A(n4713), .B(n4712), .Y(n4715) );
MX2X1TS U3928 ( .A(FPMULT_P_Sgf[14]), .B(n4696), .S0(n4680), .Y(n1567) );
XOR2X1TS U3929 ( .A(n4695), .B(n4694), .Y(n4696) );
AO22XLTS U3930 ( .A0(n4911), .A1(busy), .B0(n4909), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2147) );
AO22XLTS U3931 ( .A0(n5057), .A1(result_add_subt[24]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[24]), .Y(n1784) );
AO22XLTS U3932 ( .A0(n5057), .A1(result_add_subt[26]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[26]), .Y(n1778) );
AO22XLTS U3933 ( .A0(n5057), .A1(result_add_subt[27]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[27]), .Y(n1775) );
AO22XLTS U3934 ( .A0(n5057), .A1(result_add_subt[28]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[28]), .Y(n1772) );
AO22XLTS U3935 ( .A0(n5057), .A1(result_add_subt[22]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[22]), .Y(n2009) );
AO22XLTS U3936 ( .A0(n5062), .A1(result_add_subt[15]), .B0(n4955), .B1(
FPSENCOS_d_ff_Yn[15]), .Y(n2030) );
AO22XLTS U3937 ( .A0(n5057), .A1(result_add_subt[18]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[18]), .Y(n2021) );
AO22XLTS U3938 ( .A0(n5057), .A1(result_add_subt[21]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[21]), .Y(n2012) );
AO22XLTS U3939 ( .A0(n5057), .A1(result_add_subt[19]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[19]), .Y(n2018) );
AO22XLTS U3940 ( .A0(n5057), .A1(result_add_subt[20]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[20]), .Y(n2015) );
AO22XLTS U3941 ( .A0(n5062), .A1(result_add_subt[17]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[17]), .Y(n2024) );
AO22XLTS U3942 ( .A0(n4951), .A1(result_add_subt[4]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[4]), .Y(n2063) );
AO22XLTS U3943 ( .A0(n5062), .A1(result_add_subt[6]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[6]), .Y(n2057) );
AO22XLTS U3944 ( .A0(n5062), .A1(result_add_subt[13]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[13]), .Y(n2036) );
AO22XLTS U3945 ( .A0(n5062), .A1(result_add_subt[16]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[16]), .Y(n2027) );
AO22XLTS U3946 ( .A0(n5062), .A1(result_add_subt[8]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[8]), .Y(n2051) );
AO22XLTS U3947 ( .A0(n5062), .A1(result_add_subt[11]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[11]), .Y(n2042) );
AO22XLTS U3948 ( .A0(n5062), .A1(result_add_subt[14]), .B0(n4955), .B1(
FPSENCOS_d_ff_Yn[14]), .Y(n2033) );
AO22XLTS U3949 ( .A0(n5062), .A1(result_add_subt[10]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[10]), .Y(n2045) );
AO22XLTS U3950 ( .A0(n5062), .A1(result_add_subt[12]), .B0(n5061), .B1(
FPSENCOS_d_ff_Yn[12]), .Y(n2039) );
AO22XLTS U3951 ( .A0(n4951), .A1(result_add_subt[3]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[3]), .Y(n2066) );
AO22XLTS U3952 ( .A0(n4951), .A1(result_add_subt[2]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[2]), .Y(n2069) );
AO22XLTS U3953 ( .A0(n5062), .A1(result_add_subt[7]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[7]), .Y(n2054) );
AO22XLTS U3954 ( .A0(n5057), .A1(result_add_subt[0]), .B0(n4955), .B1(
FPSENCOS_d_ff_Yn[0]), .Y(n2075) );
AO22XLTS U3955 ( .A0(n4951), .A1(result_add_subt[1]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[1]), .Y(n2072) );
AO22XLTS U3956 ( .A0(n5062), .A1(result_add_subt[9]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[9]), .Y(n2048) );
AO22XLTS U3957 ( .A0(n5062), .A1(result_add_subt[5]), .B0(n4958), .B1(
FPSENCOS_d_ff_Yn[5]), .Y(n2060) );
AO22XLTS U3958 ( .A0(n5070), .A1(result_add_subt[22]), .B0(n5069), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(n2008) );
AO22XLTS U3959 ( .A0(n4957), .A1(result_add_subt[15]), .B0(n5063), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(n2029) );
AO22XLTS U3960 ( .A0(n5070), .A1(result_add_subt[18]), .B0(n5063), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(n2020) );
AO22XLTS U3961 ( .A0(n5070), .A1(result_add_subt[21]), .B0(n5063), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(n2011) );
AO22XLTS U3962 ( .A0(n4957), .A1(result_add_subt[4]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(n2062) );
AO22XLTS U3963 ( .A0(n4957), .A1(result_add_subt[8]), .B0(n5063), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(n2050) );
AO22XLTS U3964 ( .A0(n4957), .A1(result_add_subt[11]), .B0(n5063), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(n2041) );
AO22XLTS U3965 ( .A0(n4950), .A1(result_add_subt[0]), .B0(n5069), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(n2074) );
AO22XLTS U3966 ( .A0(n4957), .A1(result_add_subt[9]), .B0(n5063), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(n2047) );
AO22XLTS U3967 ( .A0(n5070), .A1(result_add_subt[28]), .B0(n5063), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(n1771) );
AO22XLTS U3968 ( .A0(n5070), .A1(result_add_subt[19]), .B0(n5063), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(n2017) );
AO22XLTS U3969 ( .A0(n5070), .A1(result_add_subt[20]), .B0(n5055), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(n2014) );
AO22XLTS U3970 ( .A0(n4957), .A1(result_add_subt[17]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(n2023) );
AO22XLTS U3971 ( .A0(n4957), .A1(result_add_subt[6]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(n2056) );
AO22XLTS U3972 ( .A0(n4957), .A1(result_add_subt[13]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(n2035) );
AO22XLTS U3973 ( .A0(n4957), .A1(result_add_subt[16]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(n2026) );
AO22XLTS U3974 ( .A0(n4957), .A1(result_add_subt[14]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(n2032) );
AO22XLTS U3975 ( .A0(n4957), .A1(result_add_subt[10]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(n2044) );
AO22XLTS U3976 ( .A0(n4957), .A1(result_add_subt[12]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(n2038) );
AO22XLTS U3977 ( .A0(n4950), .A1(result_add_subt[3]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(n2065) );
AO22XLTS U3978 ( .A0(n4950), .A1(result_add_subt[2]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(n2068) );
AO22XLTS U3979 ( .A0(n4957), .A1(result_add_subt[7]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(n2053) );
AO22XLTS U3980 ( .A0(n4950), .A1(result_add_subt[1]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(n2071) );
AO22XLTS U3981 ( .A0(n4957), .A1(result_add_subt[5]), .B0(n4956), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(n2059) );
MX2X1TS U3982 ( .A(FPMULT_Exp_module_Data_S[7]), .B(
FPMULT_exp_oper_result[7]), .S0(n4677), .Y(n1542) );
XOR2X1TS U3983 ( .A(n3998), .B(n3997), .Y(n3999) );
INVX2TS U3984 ( .A(n4001), .Y(n3997) );
AOI21X1TS U3985 ( .A0(n3989), .A1(n4016), .B0(n3988), .Y(n3998) );
XOR2X1TS U3986 ( .A(n3984), .B(n2508), .Y(n3985) );
AOI21X1TS U3987 ( .A0(n3977), .A1(n4016), .B0(n3976), .Y(n3984) );
XOR2X1TS U3988 ( .A(n3972), .B(n3971), .Y(n3973) );
AOI21X1TS U3989 ( .A0(n3964), .A1(n4016), .B0(n3963), .Y(n3972) );
XOR2X1TS U3990 ( .A(n3959), .B(n2506), .Y(n3960) );
AOI21X1TS U3991 ( .A0(n3952), .A1(n4016), .B0(n3951), .Y(n3959) );
XOR2X1TS U3992 ( .A(n3947), .B(n3946), .Y(n3948) );
INVX2TS U3993 ( .A(n3950), .Y(n3946) );
AOI21X1TS U3994 ( .A0(n3939), .A1(n4016), .B0(n3938), .Y(n3947) );
AOI21X1TS U3995 ( .A0(n3927), .A1(n4016), .B0(n3926), .Y(n3934) );
XOR2X1TS U3996 ( .A(n3922), .B(n3921), .Y(n3923) );
AOI21X1TS U3997 ( .A0(n3908), .A1(n4016), .B0(n3907), .Y(n3922) );
XOR2X1TS U3998 ( .A(n3904), .B(n3906), .Y(n3905) );
AOI21X1TS U3999 ( .A0(n4016), .A1(n3895), .B0(n3894), .Y(n3904) );
INVX2TS U4000 ( .A(n4014), .Y(n3894) );
XNOR2X1TS U4001 ( .A(n3892), .B(n4016), .Y(n3893) );
NAND2X1TS U4002 ( .A(n3895), .B(n4014), .Y(n3892) );
XOR2X1TS U4003 ( .A(n3854), .B(n2459), .Y(n3855) );
NAND2X1TS U4004 ( .A(n3851), .B(n3890), .Y(n3854) );
XOR2X1TS U4005 ( .A(n3824), .B(n2522), .Y(n3826) );
INVX2TS U4006 ( .A(n3853), .Y(n3613) );
XOR2X1TS U4007 ( .A(n4819), .B(n4818), .Y(n4821) );
NAND2X1TS U4008 ( .A(n4817), .B(n4816), .Y(n4819) );
INVX2TS U4009 ( .A(n4815), .Y(n4817) );
XNOR2X1TS U4010 ( .A(n4810), .B(n2466), .Y(n4811) );
NAND2X1TS U4011 ( .A(n2518), .B(n4809), .Y(n4810) );
XNOR2X1TS U4012 ( .A(n4802), .B(n4801), .Y(n4803) );
NAND2X1TS U4013 ( .A(n2517), .B(n4800), .Y(n4802) );
MX2X1TS U4014 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(n4681), .S0(n4680),
.Y(n1540) );
AO22XLTS U4015 ( .A0(n5189), .A1(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B0(n5718),
.B1(result_add_subt[30]), .Y(n1468) );
OAI21XLTS U4016 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n5640), .B0(n5411),
.Y(n5412) );
NAND3XLTS U4017 ( .A(n4887), .B(n4939), .C(n4897), .Y(n4888) );
OAI21XLTS U4018 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n5685), .B0(n5425),
.Y(n5426) );
MX2X1TS U4019 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_exp_oper_result[8]), .S0(n4677), .Y(n1541) );
AOI2BB2XLTS U4020 ( .B0(n5718), .B1(n5667), .A0N(n4690), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n1470) );
AOI2BB2XLTS U4021 ( .B0(n5718), .B1(n5668), .A0N(n4690), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(n1471) );
AOI2BB2XLTS U4022 ( .B0(n5718), .B1(n5669), .A0N(n4690), .A1N(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n1474) );
XOR2X1TS U4023 ( .A(n4777), .B(n4776), .Y(n4778) );
NAND2X1TS U4024 ( .A(n4775), .B(n4774), .Y(n4777) );
INVX2TS U4025 ( .A(n4773), .Y(n4775) );
NAND2X1TS U4026 ( .A(n2480), .B(n4779), .Y(n4780) );
XOR2X1TS U4027 ( .A(n4787), .B(n4786), .Y(n4788) );
NAND2X1TS U4028 ( .A(n4785), .B(n4784), .Y(n4786) );
INVX2TS U4029 ( .A(n4783), .Y(n4785) );
XNOR2X1TS U4030 ( .A(n4034), .B(n4033), .Y(n4035) );
XOR2X1TS U4031 ( .A(n4793), .B(n4792), .Y(n4795) );
NAND2X1TS U4032 ( .A(n4791), .B(n4790), .Y(n4792) );
INVX2TS U4033 ( .A(n4789), .Y(n4791) );
XOR2X1TS U4034 ( .A(n4761), .B(n4760), .Y(n4762) );
NAND2X1TS U4035 ( .A(n4759), .B(n4758), .Y(n4761) );
INVX2TS U4036 ( .A(n4757), .Y(n4759) );
XNOR2X1TS U4037 ( .A(n4771), .B(n4770), .Y(n4772) );
NAND2X1TS U4038 ( .A(n2223), .B(n4769), .Y(n4770) );
AO21XLTS U4039 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n4910), .B0(n4683),
.Y(n1316) );
AOI31XLTS U4040 ( .A0(n5290), .A1(n5289), .A2(n5288), .B0(n5291), .Y(n5292)
);
MX2X1TS U4041 ( .A(n4682), .B(FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n4910),
.Y(n1411) );
XOR2X1TS U4042 ( .A(n4738), .B(n4737), .Y(n4739) );
NAND2X1TS U4043 ( .A(n4736), .B(n4735), .Y(n4738) );
XOR2X1TS U4044 ( .A(n4767), .B(n4766), .Y(n4768) );
NAND2X1TS U4045 ( .A(n4765), .B(n4764), .Y(n4767) );
INVX2TS U4046 ( .A(n4763), .Y(n4765) );
AO22XLTS U4047 ( .A0(n5148), .A1(n5104), .B0(n5143), .B1(n2366), .Y(n1620)
);
AO22XLTS U4048 ( .A0(n5148), .A1(n5108), .B0(n5143), .B1(n2370), .Y(n1618)
);
AO22XLTS U4049 ( .A0(n5148), .A1(n5112), .B0(n5143), .B1(n2341), .Y(n1616)
);
AO22XLTS U4050 ( .A0(n5148), .A1(n5116), .B0(n5143), .B1(n2330), .Y(n1614)
);
AO22XLTS U4051 ( .A0(n5148), .A1(n5120), .B0(n5143), .B1(n2331), .Y(n1612)
);
AO22XLTS U4052 ( .A0(n4988), .A1(FPSENCOS_d_ff3_sh_x_out[9]), .B0(n4960),
.B1(n2346), .Y(n1988) );
AO22XLTS U4053 ( .A0(n4959), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n4960),
.B1(n2352), .Y(n2004) );
AO22XLTS U4054 ( .A0(n4959), .A1(FPSENCOS_d_ff3_sh_x_out[0]), .B0(n4960),
.B1(n2347), .Y(n2006) );
AO22XLTS U4055 ( .A0(n4959), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n4960),
.B1(n2353), .Y(n2002) );
AO22XLTS U4056 ( .A0(n4988), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n4960),
.B1(n2354), .Y(n1982) );
AO22XLTS U4057 ( .A0(n4988), .A1(FPSENCOS_d_ff3_sh_x_out[10]), .B0(n4960),
.B1(n2355), .Y(n1986) );
AO22XLTS U4058 ( .A0(n4988), .A1(FPSENCOS_d_ff3_sh_x_out[8]), .B0(n4960),
.B1(FPSENCOS_d_ff2_X[8]), .Y(n1990) );
AO22XLTS U4059 ( .A0(n4988), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n4960),
.B1(n2356), .Y(n1994) );
AO22XLTS U4060 ( .A0(n4959), .A1(FPSENCOS_d_ff3_sh_x_out[4]), .B0(n4960),
.B1(FPSENCOS_d_ff2_X[4]), .Y(n1998) );
AO22XLTS U4061 ( .A0(n4988), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n4984),
.B1(n2348), .Y(n1964) );
BUFX4TS U4062 ( .A(n5847), .Y(n5843) );
AO22XLTS U4063 ( .A0(n5070), .A1(result_add_subt[27]), .B0(n5063), .B1(n2334), .Y(n1774) );
AO22XLTS U4064 ( .A0(n5070), .A1(result_add_subt[26]), .B0(n5063), .B1(n2335), .Y(n1777) );
AO22XLTS U4065 ( .A0(n5070), .A1(result_add_subt[24]), .B0(n5055), .B1(n2336), .Y(n1783) );
AO22XLTS U4066 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n4948), .B1(
Data_1[31]), .Y(n2083) );
AO22XLTS U4067 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n4947), .B1(
Data_1[30]), .Y(n2084) );
AO22XLTS U4068 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n4947), .B1(
Data_1[29]), .Y(n2085) );
AO22XLTS U4069 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n4946), .B1(
Data_1[28]), .Y(n2086) );
AO22XLTS U4070 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n4947), .B1(
Data_1[27]), .Y(n2087) );
AO22XLTS U4071 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n4944), .B1(
Data_1[19]), .Y(n2095) );
AO22XLTS U4072 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n4944), .B1(
Data_1[18]), .Y(n2096) );
AO22XLTS U4073 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n4944), .B1(
Data_1[17]), .Y(n2097) );
AO22XLTS U4074 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n4944), .B1(
Data_1[16]), .Y(n2098) );
AO22XLTS U4075 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n4944), .B1(
Data_1[15]), .Y(n2099) );
AO22XLTS U4076 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n4944), .B1(
Data_1[14]), .Y(n2100) );
AO22XLTS U4077 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n4944), .B1(
Data_1[13]), .Y(n2101) );
AO22XLTS U4078 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n4946), .B1(
Data_1[12]), .Y(n2102) );
AO22XLTS U4079 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n4946), .B1(
Data_1[11]), .Y(n2103) );
AO22XLTS U4080 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n4946), .B1(
Data_1[10]), .Y(n2104) );
AO22XLTS U4081 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n4946), .B1(
Data_1[9]), .Y(n2105) );
AO22XLTS U4082 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n4946), .B1(
Data_1[8]), .Y(n2106) );
AO22XLTS U4083 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n4946), .B1(
Data_1[7]), .Y(n2107) );
AO22XLTS U4084 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n4946), .B1(
Data_1[6]), .Y(n2108) );
AO22XLTS U4085 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n4946), .B1(
Data_1[5]), .Y(n2109) );
AO22XLTS U4086 ( .A0(n4949), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n4946), .B1(
Data_1[4]), .Y(n2110) );
AO22XLTS U4087 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n4946), .B1(
Data_1[3]), .Y(n2111) );
AO22XLTS U4088 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n4946), .B1(
Data_1[2]), .Y(n2112) );
AO22XLTS U4089 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n4947), .B1(
Data_1[1]), .Y(n2113) );
AO22XLTS U4090 ( .A0(n4943), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n4947), .B1(
Data_1[0]), .Y(n2114) );
OAI211XLTS U4091 ( .A0(n4986), .A1(n5763), .B0(n4933), .C0(n4920), .Y(n2122)
);
INVX4TS U4092 ( .A(n2384), .Y(n2385) );
INVX2TS U4093 ( .A(FPMULT_Op_MY[3]), .Y(n2384) );
XOR2X1TS U4094 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[15]), .Y(n2203) );
BUFX3TS U4095 ( .A(n5711), .Y(n5476) );
INVX2TS U4096 ( .A(FPMULT_Op_MY[5]), .Y(n2386) );
INVX4TS U4097 ( .A(n2203), .Y(n2399) );
CLKXOR2X2TS U4098 ( .A(n2438), .B(FPMULT_Op_MY[18]), .Y(n2222) );
CLKXOR2X2TS U4099 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MY[20]), .Y(n2225) );
OA21XLTS U4100 ( .A0(n5555), .A1(n4524), .B0(n4602), .Y(n2232) );
NAND2X1TS U4101 ( .A(n5243), .B(n2196), .Y(n2241) );
OR2X1TS U4102 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n5240), .Y(n2242)
);
BUFX3TS U4103 ( .A(n4045), .Y(n5790) );
INVX2TS U4104 ( .A(n2241), .Y(n2290) );
INVX2TS U4105 ( .A(n2241), .Y(n2291) );
INVX2TS U4106 ( .A(n2242), .Y(n2293) );
INVX2TS U4107 ( .A(n2242), .Y(n2294) );
INVX2TS U4108 ( .A(FPMULT_Op_MY[1]), .Y(n2295) );
INVX2TS U4109 ( .A(n2295), .Y(n2296) );
INVX4TS U4110 ( .A(n2295), .Y(n2297) );
INVX2TS U4111 ( .A(n4611), .Y(n2298) );
INVX2TS U4112 ( .A(n2384), .Y(n2299) );
INVX2TS U4113 ( .A(n2386), .Y(n2300) );
INVX4TS U4114 ( .A(n2390), .Y(n2302) );
XNOR2X1TS U4115 ( .A(n2302), .B(FPMULT_Op_MX[10]), .Y(n3087) );
XNOR2X1TS U4116 ( .A(n2302), .B(FPMULT_Op_MX[9]), .Y(n3069) );
XOR2X1TS U4117 ( .A(FPMULT_Op_MY[6]), .B(n2391), .Y(n2846) );
INVX2TS U4118 ( .A(n2390), .Y(n2391) );
INVX2TS U4119 ( .A(FPMULT_Op_MY[7]), .Y(n2390) );
INVX2TS U4120 ( .A(n2738), .Y(n2303) );
INVX2TS U4121 ( .A(n2413), .Y(n2305) );
INVX2TS U4122 ( .A(n4122), .Y(n2306) );
INVX2TS U4123 ( .A(n2235), .Y(n2308) );
INVX3TS U4124 ( .A(n2235), .Y(n2309) );
INVX4TS U4125 ( .A(n2229), .Y(n2313) );
OAI221X1TS U4126 ( .A0(n5696), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n5677),
.B1(FPADDSUB_intDY_EWSW[27]), .C0(n5266), .Y(n5269) );
NOR4X1TS U4127 ( .A(FPMULT_P_Sgf[13]), .B(FPMULT_P_Sgf[11]), .C(
FPMULT_P_Sgf[12]), .D(FPMULT_P_Sgf[10]), .Y(n4080) );
OAI21X1TS U4128 ( .A0(n5694), .A1(n5240), .B0(n5208), .Y(n5209) );
AOI222X4TS U4129 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n5592), .B0(
FPADDSUB_DmP_mant_SFG_SWR[2]), .B1(n5305), .C0(n5592), .C1(n5305), .Y(
n5311) );
OAI31XLTS U4130 ( .A0(n2197), .A1(FPSENCOS_cont_iter_out[3]), .A2(n4942),
.B0(n4093), .Y(n2129) );
AOI2BB1X1TS U4131 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1N(n4539), .B0(
n4495), .Y(n4498) );
OAI21XLTS U4132 ( .A0(n4354), .A1(n4353), .B0(n4352), .Y(n1733) );
BUFX4TS U4133 ( .A(n5146), .Y(n5143) );
BUFX3TS U4134 ( .A(n5135), .Y(n5146) );
NOR2X2TS U4135 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n4983), .Y(n4987) );
NOR4BX2TS U4136 ( .AN(n4535), .B(n4503), .C(n4498), .D(n4497), .Y(n4501) );
NAND3X2TS U4137 ( .A(n4669), .B(FPMULT_FS_Module_state_reg[0]), .C(n4051),
.Y(n4672) );
NOR4X1TS U4138 ( .A(FPMULT_P_Sgf[9]), .B(FPMULT_P_Sgf[7]), .C(
FPMULT_P_Sgf[8]), .D(FPMULT_P_Sgf[6]), .Y(n4079) );
AOI21X2TS U4139 ( .A0(n5243), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n5236),
.Y(n5520) );
AOI211X2TS U4140 ( .A0(n5243), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n5242),
.C0(n5181), .Y(n5220) );
AOI211X2TS U4141 ( .A0(n5243), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n5242),
.C0(n5241), .Y(n5484) );
NOR2X2TS U4142 ( .A(n5643), .B(n5208), .Y(n5242) );
BUFX4TS U4143 ( .A(n4037), .Y(n5849) );
AOI22X1TS U4144 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(n5548), .B0(n5360), .B1(
n5359), .Y(n5366) );
AOI22X1TS U4145 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n5599), .B0(n5335), .B1(
n5334), .Y(n5341) );
AOI22X1TS U4146 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(n5603), .B0(n5347), .B1(
n5346), .Y(n5353) );
NOR4X1TS U4147 ( .A(FPMULT_Op_MX[2]), .B(FPMULT_Op_MX[0]), .C(
FPMULT_Op_MX[13]), .D(n2393), .Y(n5085) );
NOR4X1TS U4148 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[18]), .C(
FPMULT_Op_MX[16]), .D(FPMULT_Op_MX[14]), .Y(n5082) );
NOR4X1TS U4149 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[21]), .C(
FPMULT_Op_MY[20]), .D(FPMULT_Op_MY[14]), .Y(n5074) );
BUFX3TS U4150 ( .A(n4045), .Y(n4039) );
BUFX4TS U4151 ( .A(n5814), .Y(n5816) );
NOR4X1TS U4152 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[7]), .C(
FPMULT_Op_MX[5]), .D(FPMULT_Op_MX[1]), .Y(n5087) );
BUFX4TS U4153 ( .A(n5815), .Y(n5839) );
BUFX4TS U4154 ( .A(n5846), .Y(n5844) );
BUFX3TS U4155 ( .A(n4038), .Y(n4040) );
BUFX4TS U4156 ( .A(n4038), .Y(n5827) );
BUFX4TS U4157 ( .A(n4038), .Y(n5828) );
BUFX4TS U4158 ( .A(n5839), .Y(n5826) );
BUFX3TS U4159 ( .A(n5831), .Y(n2314) );
BUFX4TS U4160 ( .A(n5835), .Y(n5824) );
BUFX4TS U4161 ( .A(n2199), .Y(n5058) );
BUFX4TS U4162 ( .A(n5476), .Y(n5207) );
BUFX4TS U4163 ( .A(n5818), .Y(n5825) );
AOI21X2TS U4164 ( .A0(n5243), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n5236),
.Y(n5486) );
BUFX4TS U4165 ( .A(n5180), .Y(n5243) );
BUFX4TS U4166 ( .A(n4040), .Y(n5829) );
BUFX4TS U4167 ( .A(n4040), .Y(n5833) );
BUFX4TS U4168 ( .A(n4040), .Y(n5834) );
BUFX4TS U4169 ( .A(n4040), .Y(n5820) );
AOI21X2TS U4170 ( .A0(n5243), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n5236),
.Y(n5459) );
BUFX4TS U4171 ( .A(n5810), .Y(n5801) );
BUFX4TS U4172 ( .A(n5796), .Y(n5798) );
BUFX4TS U4173 ( .A(n5805), .Y(n5786) );
BUFX4TS U4174 ( .A(n4039), .Y(n5800) );
BUFX3TS U4175 ( .A(n5784), .Y(n2315) );
BUFX4TS U4176 ( .A(n4039), .Y(n5797) );
BUFX4TS U4177 ( .A(n5794), .Y(n5793) );
BUFX4TS U4178 ( .A(n4045), .Y(n5796) );
BUFX4TS U4179 ( .A(n5804), .Y(n5795) );
BUFX3TS U4180 ( .A(n5804), .Y(n2316) );
BUFX4TS U4181 ( .A(n5793), .Y(n5791) );
BUFX4TS U4182 ( .A(n5812), .Y(n5804) );
BUFX4TS U4183 ( .A(n5813), .Y(n5805) );
BUFX4TS U4184 ( .A(n5790), .Y(n5806) );
BUFX4TS U4185 ( .A(n5859), .Y(n5858) );
BUFX4TS U4186 ( .A(n5859), .Y(n5852) );
BUFX4TS U4187 ( .A(n4980), .Y(n4960) );
INVX2TS U4188 ( .A(n2237), .Y(n2317) );
INVX2TS U4189 ( .A(n2236), .Y(n2318) );
BUFX4TS U4190 ( .A(n4955), .Y(n5061) );
OAI21X2TS U4191 ( .A0(n2205), .A1(n4524), .B0(n4555), .Y(n5050) );
OAI21X2TS U4192 ( .A0(n4094), .A1(n5568), .B0(n4100), .Y(n4928) );
BUFX3TS U4193 ( .A(n5818), .Y(n5817) );
BUFX3TS U4194 ( .A(n4040), .Y(n5835) );
BUFX4TS U4195 ( .A(n4037), .Y(n5857) );
BUFX4TS U4196 ( .A(n4037), .Y(n5859) );
OAI22X1TS U4197 ( .A0(n3465), .A1(n3339), .B0(n3330), .B1(n2398), .Y(n3336)
);
OAI22X1TS U4198 ( .A0(n3497), .A1(n3390), .B0(n3373), .B1(n2399), .Y(n3394)
);
OAI22X1TS U4199 ( .A0(n3497), .A1(n3411), .B0(n3390), .B1(n2292), .Y(n3415)
);
NAND2X1TS U4200 ( .A(n2537), .B(n2536), .Y(n2603) );
BUFX4TS U4201 ( .A(n5857), .Y(n5855) );
NOR2X1TS U4202 ( .A(n2533), .B(n2532), .Y(n2534) );
XNOR2X1TS U4203 ( .A(n2532), .B(n2527), .Y(n2531) );
OAI32X1TS U4204 ( .A0(n4917), .A1(n4912), .A2(n5568), .B0(n5623), .B1(n4917),
.Y(n2142) );
NOR3X4TS U4205 ( .A(n4912), .B(n5623), .C(n5568), .Y(n4917) );
INVX2TS U4206 ( .A(n2256), .Y(n2319) );
INVX2TS U4207 ( .A(n2257), .Y(n2320) );
INVX2TS U4208 ( .A(n2253), .Y(n2321) );
INVX2TS U4209 ( .A(n2254), .Y(n2322) );
INVX2TS U4210 ( .A(n2255), .Y(n2323) );
INVX2TS U4211 ( .A(n2284), .Y(n2324) );
INVX2TS U4212 ( .A(n2283), .Y(n2325) );
INVX2TS U4213 ( .A(n2217), .Y(n2326) );
INVX2TS U4214 ( .A(n2282), .Y(n2327) );
INVX2TS U4215 ( .A(n2281), .Y(n2328) );
INVX2TS U4216 ( .A(n2216), .Y(n2329) );
INVX2TS U4217 ( .A(n2258), .Y(n2330) );
INVX2TS U4218 ( .A(n2259), .Y(n2331) );
INVX2TS U4219 ( .A(n2260), .Y(n2332) );
INVX2TS U4220 ( .A(n2261), .Y(n2333) );
BUFX4TS U4221 ( .A(n5788), .Y(n5792) );
BUFX4TS U4222 ( .A(n5795), .Y(n5811) );
BUFX4TS U4223 ( .A(n5790), .Y(n5788) );
BUFX4TS U4224 ( .A(n4039), .Y(n5812) );
INVX2TS U4225 ( .A(n2288), .Y(n2334) );
INVX2TS U4226 ( .A(n2287), .Y(n2335) );
INVX2TS U4227 ( .A(n2286), .Y(n2336) );
INVX2TS U4228 ( .A(n2215), .Y(n2337) );
INVX2TS U4229 ( .A(n2214), .Y(n2338) );
INVX2TS U4230 ( .A(n2208), .Y(n2339) );
INVX2TS U4231 ( .A(n2233), .Y(n2340) );
NOR4X1TS U4232 ( .A(FPMULT_Op_MY[27]), .B(n2339), .C(n2340), .D(
FPMULT_Op_MY[24]), .Y(n5073) );
INVX2TS U4233 ( .A(n2289), .Y(n2341) );
NOR3XLTS U4234 ( .A(n2435), .B(FPMULT_Op_MY[12]), .C(FPMULT_Op_MY[23]), .Y(
n5076) );
INVX2TS U4235 ( .A(n2244), .Y(n2342) );
INVX2TS U4236 ( .A(n2239), .Y(n2343) );
INVX2TS U4237 ( .A(n2234), .Y(n2344) );
INVX2TS U4238 ( .A(n2280), .Y(n2345) );
INVX2TS U4239 ( .A(n2278), .Y(n2346) );
INVX2TS U4240 ( .A(n2277), .Y(n2347) );
INVX2TS U4241 ( .A(n2279), .Y(n2348) );
INVX2TS U4242 ( .A(n2275), .Y(n2349) );
INVX2TS U4243 ( .A(n2274), .Y(n2350) );
INVX2TS U4244 ( .A(n2276), .Y(n2351) );
INVX2TS U4245 ( .A(n2213), .Y(n2352) );
INVX2TS U4246 ( .A(n2270), .Y(n2353) );
INVX2TS U4247 ( .A(n2273), .Y(n2354) );
INVX2TS U4248 ( .A(n2272), .Y(n2355) );
INVX2TS U4249 ( .A(n2271), .Y(n2356) );
INVX2TS U4250 ( .A(n2264), .Y(n2357) );
INVX2TS U4251 ( .A(n2265), .Y(n2358) );
INVX2TS U4252 ( .A(n2267), .Y(n2359) );
INVX2TS U4253 ( .A(n2266), .Y(n2360) );
INVX2TS U4254 ( .A(n2285), .Y(n2361) );
INVX2TS U4255 ( .A(n2269), .Y(n2362) );
INVX2TS U4256 ( .A(n2268), .Y(n2363) );
INVX2TS U4257 ( .A(n2202), .Y(n2364) );
INVX2TS U4258 ( .A(n2243), .Y(n2365) );
INVX2TS U4259 ( .A(n2263), .Y(n2366) );
INVX2TS U4260 ( .A(n2210), .Y(n2367) );
INVX2TS U4261 ( .A(n2252), .Y(n2368) );
INVX2TS U4262 ( .A(n2212), .Y(n2369) );
INVX2TS U4263 ( .A(n2262), .Y(n2370) );
INVX2TS U4264 ( .A(n2201), .Y(n2371) );
INVX2TS U4265 ( .A(n2209), .Y(n2372) );
INVX2TS U4266 ( .A(n2238), .Y(n2373) );
INVX2TS U4267 ( .A(n2248), .Y(n2374) );
INVX2TS U4268 ( .A(n2207), .Y(n2375) );
INVX2TS U4269 ( .A(n2231), .Y(n2376) );
INVX2TS U4270 ( .A(n2230), .Y(n2377) );
INVX2TS U4271 ( .A(n2249), .Y(n2378) );
INVX2TS U4272 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .Y(n2379) );
INVX2TS U4273 ( .A(n2379), .Y(n2380) );
INVX4TS U4274 ( .A(n5473), .Y(n5458) );
INVX4TS U4275 ( .A(n5472), .Y(n5477) );
BUFX4TS U4276 ( .A(FPMULT_Op_MY[13]), .Y(n2382) );
XNOR2X1TS U4277 ( .A(n2382), .B(FPMULT_Op_MX[15]), .Y(n2692) );
NAND2X4TS U4278 ( .A(n2382), .B(n2224), .Y(n3478) );
XNOR2X1TS U4279 ( .A(n2382), .B(FPMULT_Op_MX[14]), .Y(n2696) );
INVX2TS U4280 ( .A(n2232), .Y(n2383) );
INVX3TS U4281 ( .A(n2240), .Y(n2388) );
INVX2TS U4282 ( .A(n2460), .Y(n2389) );
INVX2TS U4283 ( .A(n2476), .Y(n2392) );
BUFX4TS U4284 ( .A(FPMULT_Op_MY[15]), .Y(n2395) );
XNOR2X1TS U4285 ( .A(n2395), .B(FPMULT_Op_MX[19]), .Y(n3432) );
XNOR2X1TS U4286 ( .A(n2395), .B(FPMULT_Op_MX[17]), .Y(n3480) );
XNOR2X1TS U4287 ( .A(n2395), .B(FPMULT_Op_MX[16]), .Y(n3481) );
XNOR2X1TS U4288 ( .A(n2395), .B(FPMULT_Op_MX[14]), .Y(n2687) );
XNOR2X1TS U4289 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MX[15]), .Y(n2671) );
NOR2X2TS U4290 ( .A(n2299), .B(FPMULT_Op_MY[15]), .Y(n2638) );
NOR2BX1TS U4291 ( .AN(FPMULT_Op_MX[0]), .B(DP_OP_453J208_122_681_n1721), .Y(
n2864) );
INVX2TS U4292 ( .A(n2225), .Y(n2397) );
INVX4TS U4293 ( .A(n2222), .Y(n2401) );
INVX2TS U4294 ( .A(n2226), .Y(n2403) );
INVX2TS U4295 ( .A(n2246), .Y(n2404) );
INVX2TS U4296 ( .A(n2250), .Y(n2405) );
INVX2TS U4297 ( .A(n2245), .Y(n2406) );
INVX2TS U4298 ( .A(n2251), .Y(n2407) );
XNOR2X1TS U4299 ( .A(FPMULT_Op_MX[11]), .B(n2385), .Y(n2844) );
XNOR2X1TS U4300 ( .A(FPMULT_Op_MX[11]), .B(n2301), .Y(n3068) );
XOR2X1TS U4301 ( .A(n2609), .B(FPMULT_Op_MX[11]), .Y(n2610) );
INVX2TS U4302 ( .A(n2204), .Y(n2408) );
OAI221X1TS U4303 ( .A0(n5674), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n5679),
.B1(FPADDSUB_intDY_EWSW[9]), .C0(n5264), .Y(n5271) );
AOI222X1TS U4304 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n5573), .B0(n4157), .B1(
n4156), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n5689), .Y(n4159) );
AOI221X1TS U4305 ( .A0(n5573), .A1(FPADDSUB_intDY_EWSW[4]), .B0(
FPADDSUB_intDY_EWSW[5]), .B1(n5689), .C0(n5278), .Y(n5281) );
XNOR2X2TS U4306 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MX[9]), .Y(n2604) );
NOR2X1TS U4307 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MX[9]), .Y(n2602) );
XNOR2X1TS U4308 ( .A(FPMULT_Op_MX[21]), .B(n2395), .Y(n3395) );
NAND2X1TS U4309 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[6]), .Y(n2528) );
XNOR2X1TS U4310 ( .A(FPMULT_Op_MX[18]), .B(n2382), .Y(n3477) );
XOR2X1TS U4311 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[5]), .Y(n2634) );
XNOR2X1TS U4312 ( .A(n2395), .B(FPMULT_Op_MX[18]), .Y(n3467) );
XNOR2X1TS U4313 ( .A(n2396), .B(FPMULT_Op_MX[20]), .Y(n3339) );
XNOR2X1TS U4314 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MX[20]), .Y(n3390) );
XNOR2X1TS U4315 ( .A(n2395), .B(FPMULT_Op_MX[20]), .Y(n3427) );
XOR2X1TS U4316 ( .A(FPMULT_Op_MX[19]), .B(FPMULT_Op_MX[20]), .Y(n2533) );
NAND2X1TS U4317 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[8]), .Y(n2536) );
XOR2X1TS U4318 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[8]), .Y(n2532) );
XOR2X1TS U4319 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[21]), .Y(n2608) );
INVX2TS U4320 ( .A(n5871), .Y(n2409) );
INVX2TS U4321 ( .A(n5871), .Y(n2410) );
BUFX3TS U4322 ( .A(n5190), .Y(n2411) );
OAI221X1TS U4323 ( .A0(n5527), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n5642),
.B1(FPADDSUB_intDY_EWSW[23]), .C0(n5272), .Y(n5287) );
OAI221X1TS U4324 ( .A0(n5576), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n5681),
.B1(FPADDSUB_intDY_EWSW[17]), .C0(n5256), .Y(n5263) );
NOR4X2TS U4325 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .C(n5554), .D(n5532), .Y(n4905) );
XOR2XLTS U4326 ( .A(FPSENCOS_d_ff_Yn[31]), .B(n4308), .Y(n4309) );
OAI33X4TS U4327 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .A2(n5703), .B0(n5541), .B1(
n5582), .B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n4308) );
XNOR2X1TS U4328 ( .A(n3871), .B(n3870), .Y(n3872) );
NOR2X2TS U4329 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_473_n1), .Y(n4981) );
NOR4X1TS U4330 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_P_Sgf[3]), .C(
FPMULT_P_Sgf[5]), .D(FPMULT_P_Sgf[4]), .Y(n4082) );
NOR4X1TS U4331 ( .A(FPMULT_Op_MX[21]), .B(FPMULT_Op_MX[19]), .C(
FPMULT_Op_MX[17]), .D(FPMULT_Op_MX[15]), .Y(n5083) );
BUFX4TS U4332 ( .A(n4947), .Y(n4946) );
AOI21X2TS U4333 ( .A0(n5243), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n5236),
.Y(n5462) );
NOR2X2TS U4334 ( .A(n4937), .B(n4928), .Y(n4934) );
INVX2TS U4335 ( .A(n4937), .Y(n4099) );
NOR2X2TS U4336 ( .A(FPSENCOS_cont_iter_out[3]), .B(n4915), .Y(n4937) );
BUFX4TS U4337 ( .A(n4986), .Y(n4974) );
OAI211X2TS U4338 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n5610), .B0(n4176),
.C0(n4162), .Y(n4178) );
OAI211X2TS U4339 ( .A0(n2197), .A1(n4916), .B0(n4099), .C0(n4100), .Y(n4925)
);
AOI211X1TS U4340 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5675), .B0(n4190),
.C0(n4191), .Y(n4182) );
OAI211X2TS U4341 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n5617), .B0(n4196),
.C0(n4181), .Y(n4190) );
BUFX4TS U4342 ( .A(n5357), .Y(n5435) );
BUFX4TS U4343 ( .A(n5852), .Y(n5860) );
BUFX4TS U4344 ( .A(n4469), .Y(n4486) );
INVX2TS U4345 ( .A(n2412), .Y(n2413) );
AOI211X1TS U4346 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5487), .B0(n5245),
.C0(n5187), .Y(n5519) );
AOI221X1TS U4347 ( .A0(n2413), .A1(n5246), .B0(n2412), .B1(n5247), .C0(n5248), .Y(n5505) );
AOI221X1TS U4348 ( .A0(n2413), .A1(n5247), .B0(n2412), .B1(n5246), .C0(n5248), .Y(n5504) );
BUFX4TS U4349 ( .A(n4040), .Y(n5821) );
BUFX4TS U4350 ( .A(n5845), .Y(n5814) );
BUFX4TS U4351 ( .A(n4040), .Y(n5818) );
AOI222X1TS U4352 ( .A0(n4249), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4977), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n4233), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n4250) );
AOI222X1TS U4353 ( .A0(n4329), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DmP_EXP_EWSW[23]), .B1(n5298), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n4235), .Y(n4330) );
AOI21X1TS U4354 ( .A0(n3248), .A1(n3193), .B0(n3192), .Y(n3196) );
AOI21X1TS U4355 ( .A0(n3248), .A1(n3175), .B0(n3174), .Y(n3188) );
AOI21X1TS U4356 ( .A0(n3248), .A1(n3207), .B0(n3206), .Y(n3212) );
AOI21X1TS U4357 ( .A0(n3248), .A1(n3202), .B0(n3201), .Y(n3205) );
AOI21X1TS U4358 ( .A0(n3248), .A1(n3225), .B0(n3224), .Y(n3230) );
AOI21X1TS U4359 ( .A0(n3248), .A1(n3216), .B0(n3215), .Y(n3221) );
AOI21X1TS U4360 ( .A0(n3248), .A1(n3246), .B0(n3239), .Y(n3244) );
AOI21X1TS U4361 ( .A0(n3248), .A1(n3232), .B0(n3231), .Y(n3237) );
XNOR2X2TS U4362 ( .A(n3248), .B(n3247), .Y(n3694) );
INVX4TS U4363 ( .A(n5476), .Y(n5474) );
OAI21X2TS U4364 ( .A0(n5533), .A1(n4524), .B0(n4599), .Y(n4640) );
AOI22X1TS U4365 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n5593), .B0(n5323), .B1(
n5322), .Y(n5329) );
AOI22X1TS U4366 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(n5595), .B0(n5311), .B1(
n5309), .Y(n5317) );
OAI211XLTS U4367 ( .A0(n4448), .A1(n2503), .B0(n4363), .C0(n4362), .Y(n1912)
);
NOR3XLTS U4368 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n5149), .Y(n5153) );
NAND2X1TS U4369 ( .A(FPMULT_Sgf_normalized_result[3]), .B(n5101), .Y(n5103)
);
NAND2BX1TS U4370 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n4028),
.Y(n4892) );
OAI211XLTS U4371 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n5129), .B0(
n5138), .C0(n5131), .Y(n5130) );
OAI211XLTS U4372 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n5125), .B0(
n5138), .C0(n5127), .Y(n5126) );
OAI211XLTS U4373 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n5121), .B0(
n5138), .C0(n5123), .Y(n5122) );
OAI211XLTS U4374 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n5117), .B0(
n5138), .C0(n5119), .Y(n5118) );
CLKBUFX2TS U4375 ( .A(n2815), .Y(n2414) );
OAI22X1TS U4376 ( .A0(n2802), .A1(n2813), .B0(n2801), .B1(n2414), .Y(
DP_OP_453J208_122_681_n558) );
OAI22X1TS U4377 ( .A0(n2801), .A1(n2813), .B0(n2414), .B1(n2800), .Y(
DP_OP_453J208_122_681_n557) );
OAI22X1TS U4378 ( .A0(n2803), .A1(n2813), .B0(n2802), .B1(n2414), .Y(
DP_OP_453J208_122_681_n559) );
OAI22X1TS U4379 ( .A0(n2803), .A1(n2815), .B0(n2804), .B1(n2813), .Y(
DP_OP_453J208_122_681_n560) );
NAND2X4TS U4380 ( .A(n2815), .B(n2703), .Y(n2813) );
AOI21X2TS U4381 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n5243), .B0(n5209),
.Y(n5217) );
AOI21X2TS U4382 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n5243), .B0(n5200),
.Y(n5467) );
XOR2X1TS U4383 ( .A(n2817), .B(n2477), .Y(n3542) );
INVX4TS U4384 ( .A(n3542), .Y(n2415) );
XNOR2X1TS U4385 ( .A(n2828), .B(n2415), .Y(n2831) );
XNOR2X1TS U4386 ( .A(n2836), .B(n2415), .Y(n2839) );
CLKBUFX2TS U4387 ( .A(n2798), .Y(n2416) );
OAI22X1TS U4388 ( .A0(n2786), .A1(n2797), .B0(n2785), .B1(n2416), .Y(
DP_OP_453J208_122_681_n544) );
OAI22X1TS U4389 ( .A0(n2786), .A1(n2416), .B0(n2787), .B1(n2797), .Y(
DP_OP_453J208_122_681_n545) );
OAI22X1TS U4390 ( .A0(n2785), .A1(n2797), .B0(n2784), .B1(n2798), .Y(
DP_OP_453J208_122_681_n543) );
OAI22X1TS U4391 ( .A0(n2788), .A1(n2797), .B0(n2787), .B1(n2798), .Y(
DP_OP_453J208_122_681_n546) );
OAI22X1TS U4392 ( .A0(n2789), .A1(n2797), .B0(n2788), .B1(n2798), .Y(
DP_OP_453J208_122_681_n547) );
OAI22X1TS U4393 ( .A0(n2790), .A1(n2797), .B0(n2789), .B1(n2798), .Y(
DP_OP_453J208_122_681_n548) );
OAI22X1TS U4394 ( .A0(n2791), .A1(n2798), .B0(n2793), .B1(n2797), .Y(
DP_OP_453J208_122_681_n550) );
NAND2X4TS U4395 ( .A(n2798), .B(n2580), .Y(n2797) );
XOR2X1TS U4396 ( .A(n2705), .B(n2704), .Y(n2810) );
INVX4TS U4397 ( .A(n2810), .Y(n2417) );
XNOR2X1TS U4398 ( .A(n2828), .B(n2417), .Y(n2806) );
XNOR2X1TS U4399 ( .A(n2826), .B(n2417), .Y(n2805) );
XNOR2X1TS U4400 ( .A(n2832), .B(n2417), .Y(n2808) );
XNOR2X1TS U4401 ( .A(n2834), .B(n2417), .Y(n2809) );
INVX2TS U4402 ( .A(n2417), .Y(n2800) );
XNOR2X1TS U4403 ( .A(n2836), .B(n2417), .Y(n2811) );
CLKBUFX2TS U4404 ( .A(n2781), .Y(n2418) );
OAI22X1TS U4405 ( .A0(n2769), .A1(n2783), .B0(n2418), .B1(n2768), .Y(
DP_OP_453J208_122_681_n527) );
OAI22X1TS U4406 ( .A0(n2770), .A1(n2783), .B0(n2769), .B1(n2418), .Y(
DP_OP_453J208_122_681_n528) );
OAI22X1TS U4407 ( .A0(n2771), .A1(n2781), .B0(n2772), .B1(n2783), .Y(
DP_OP_453J208_122_681_n530) );
OAI22X1TS U4408 ( .A0(n2773), .A1(n2783), .B0(n2772), .B1(n2418), .Y(
DP_OP_453J208_122_681_n531) );
OAI22X1TS U4409 ( .A0(n2771), .A1(n2783), .B0(n2770), .B1(n2781), .Y(
DP_OP_453J208_122_681_n529) );
OAI22X1TS U4410 ( .A0(n2774), .A1(n2783), .B0(n2773), .B1(n2781), .Y(
DP_OP_453J208_122_681_n532) );
OAI22X1TS U4411 ( .A0(n2776), .A1(n2783), .B0(n2774), .B1(n2781), .Y(
DP_OP_453J208_122_681_n533) );
OAI22X1TS U4412 ( .A0(n2776), .A1(n2781), .B0(n2775), .B1(n2783), .Y(
DP_OP_453J208_122_681_n534) );
OAI22X1TS U4413 ( .A0(n2777), .A1(n2781), .B0(n2779), .B1(n2783), .Y(
DP_OP_453J208_122_681_n536) );
OAI22X1TS U4414 ( .A0(n2783), .A1(n2782), .B0(n2781), .B1(n2780), .Y(
DP_OP_453J208_122_681_n538) );
NAND2X4TS U4415 ( .A(n2781), .B(n2637), .Y(n2783) );
AOI222X2TS U4416 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(
FPADDSUB_DMP_SFG[12]), .B0(FPADDSUB_DmP_mant_SFG_SWR[14]), .B1(n5378),
.C0(FPADDSUB_DMP_SFG[12]), .C1(n5378), .Y(n5383) );
AOI222X2TS U4417 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(
FPADDSUB_DMP_SFG[10]), .B0(FPADDSUB_DmP_mant_SFG_SWR[12]), .B1(n5365),
.C0(FPADDSUB_DMP_SFG[10]), .C1(n5365), .Y(n5370) );
AOI222X2TS U4418 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[16]), .A1(
FPADDSUB_DMP_SFG[14]), .B0(FPADDSUB_DmP_mant_SFG_SWR[16]), .B1(n5390),
.C0(FPADDSUB_DMP_SFG[14]), .C1(n5390), .Y(n5395) );
AOI222X2TS U4419 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(
FPADDSUB_DMP_SFG[8]), .B0(FPADDSUB_DmP_mant_SFG_SWR[10]), .B1(n5352),
.C0(FPADDSUB_DMP_SFG[8]), .C1(n5352), .Y(n5358) );
AOI222X2TS U4420 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[18]), .A1(
FPADDSUB_DMP_SFG[16]), .B0(FPADDSUB_DmP_mant_SFG_SWR[18]), .B1(n5402),
.C0(FPADDSUB_DMP_SFG[16]), .C1(n5402), .Y(n5409) );
AOI222X2TS U4421 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(
FPADDSUB_DMP_SFG[6]), .B0(FPADDSUB_DmP_mant_SFG_SWR[8]), .B1(n5340),
.C0(FPADDSUB_DMP_SFG[6]), .C1(n5340), .Y(n5345) );
AOI222X2TS U4422 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(
FPADDSUB_DMP_SFG[4]), .B0(FPADDSUB_DmP_mant_SFG_SWR[6]), .B1(n5328),
.C0(FPADDSUB_DMP_SFG[4]), .C1(n5328), .Y(n5333) );
AOI222X2TS U4423 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(
FPADDSUB_DMP_SFG[20]), .B0(FPADDSUB_DmP_mant_SFG_SWR[22]), .B1(n5430),
.C0(FPADDSUB_DMP_SFG[20]), .C1(n5430), .Y(n5436) );
AOI222X2TS U4424 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(
FPADDSUB_DMP_SFG[18]), .B0(FPADDSUB_DmP_mant_SFG_SWR[20]), .B1(n5417),
.C0(FPADDSUB_DMP_SFG[18]), .C1(n5417), .Y(n5423) );
AOI222X2TS U4425 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(
FPADDSUB_DMP_SFG[22]), .B0(FPADDSUB_DmP_mant_SFG_SWR[24]), .B1(n5446),
.C0(FPADDSUB_DMP_SFG[22]), .C1(n5446), .Y(n5301) );
AOI32X1TS U4426 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n5045), .A2(
n4910), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n4569), .Y(n4511)
);
BUFX4TS U4427 ( .A(n2794), .Y(n2419) );
XNOR2X1TS U4428 ( .A(n2834), .B(n2419), .Y(n2793) );
INVX2TS U4429 ( .A(n2419), .Y(n2689) );
XNOR2X1TS U4430 ( .A(n2630), .B(n2629), .Y(n2794) );
CLKBUFX2TS U4431 ( .A(n2767), .Y(n2420) );
OAI22X1TS U4432 ( .A0(n2755), .A1(n2764), .B0(n2420), .B1(n2754), .Y(
DP_OP_453J208_122_681_n512) );
OAI22X1TS U4433 ( .A0(n2756), .A1(n2764), .B0(n2755), .B1(n2420), .Y(
DP_OP_453J208_122_681_n513) );
OAI22X1TS U4434 ( .A0(n2758), .A1(n2764), .B0(n2756), .B1(n2420), .Y(
DP_OP_453J208_122_681_n514) );
OAI22X1TS U4435 ( .A0(n2758), .A1(n2767), .B0(n2757), .B1(n2764), .Y(
DP_OP_453J208_122_681_n515) );
OAI22X1TS U4436 ( .A0(n2759), .A1(n2764), .B0(n2757), .B1(n2767), .Y(n2622)
);
OAI22X1TS U4437 ( .A0(n2761), .A1(n2767), .B0(n2763), .B1(n2764), .Y(
DP_OP_453J208_122_681_n519) );
OAI22X1TS U4438 ( .A0(n2760), .A1(n2764), .B0(n2759), .B1(n2767), .Y(
DP_OP_453J208_122_681_n517) );
OAI22X1TS U4439 ( .A0(n2761), .A1(n2764), .B0(n2760), .B1(n2767), .Y(
DP_OP_453J208_122_681_n518) );
OAI22X1TS U4440 ( .A0(n2763), .A1(n2767), .B0(n2766), .B1(n2764), .Y(
DP_OP_453J208_122_681_n520) );
OAI22X1TS U4441 ( .A0(n2766), .A1(n2767), .B0(n2765), .B1(n2764), .Y(
DP_OP_453J208_122_681_n521) );
OAI22X1TS U4442 ( .A0(n2765), .A1(n2767), .B0(n2764), .B1(n2657), .Y(n2656)
);
NOR2BX1TS U4443 ( .AN(n2304), .B(n2767), .Y(DP_OP_453J208_122_681_n525) );
OAI22X1TS U4444 ( .A0(n2764), .A1(n2659), .B0(n2767), .B1(n2657), .Y(n2663)
);
OAI22X1TS U4445 ( .A0(n2764), .A1(n2660), .B0(n2767), .B1(n2659), .Y(n2664)
);
NAND2X4TS U4446 ( .A(n2767), .B(n2535), .Y(n2764) );
CLKBUFX2TS U4447 ( .A(n3858), .Y(n2421) );
OAI22X1TS U4448 ( .A0(n2741), .A1(n2753), .B0(n2740), .B1(n2421), .Y(
DP_OP_453J208_122_681_n498) );
OAI22X1TS U4449 ( .A0(n2740), .A1(n2753), .B0(n2421), .B1(n3857), .Y(
DP_OP_453J208_122_681_n497) );
OAI22X1TS U4450 ( .A0(n2742), .A1(n2753), .B0(n2741), .B1(n2421), .Y(
DP_OP_453J208_122_681_n499) );
OAI22X1TS U4451 ( .A0(n2742), .A1(n3858), .B0(n2743), .B1(n2753), .Y(
DP_OP_453J208_122_681_n500) );
OAI22X1TS U4452 ( .A0(n2744), .A1(n2753), .B0(n2743), .B1(n3858), .Y(
DP_OP_453J208_122_681_n501) );
OAI22X1TS U4453 ( .A0(n2745), .A1(n2753), .B0(n2744), .B1(n3858), .Y(n2611)
);
OAI22X1TS U4454 ( .A0(n2746), .A1(n3858), .B0(n2753), .B1(n2747), .Y(
DP_OP_453J208_122_681_n504) );
OAI22X1TS U4455 ( .A0(n2746), .A1(n2753), .B0(n2745), .B1(n3858), .Y(
DP_OP_453J208_122_681_n503) );
OAI22X1TS U4456 ( .A0(n2753), .A1(n2748), .B0(n2747), .B1(n3858), .Y(
DP_OP_453J208_122_681_n505) );
OAI22X1TS U4457 ( .A0(n2753), .A1(n2750), .B0(n2748), .B1(n3858), .Y(
DP_OP_453J208_122_681_n506) );
OAI22X1TS U4458 ( .A0(n2753), .A1(n2751), .B0(n3858), .B1(n2750), .Y(
DP_OP_453J208_122_681_n507) );
OAI22X1TS U4459 ( .A0(n2753), .A1(n2752), .B0(n3858), .B1(n2751), .Y(
DP_OP_453J208_122_681_n508) );
OAI22X1TS U4460 ( .A0(n2753), .A1(n3857), .B0(n3858), .B1(n2626), .Y(n2654)
);
OAI22X1TS U4461 ( .A0(n2753), .A1(n2651), .B0(n3858), .B1(n2752), .Y(n2655)
);
NAND2X4TS U4462 ( .A(n3858), .B(n2610), .Y(n2753) );
OAI22X1TS U4463 ( .A0(n3412), .A1(FPMULT_Op_MX[20]), .B0(n2422), .B1(
FPMULT_Op_MX[21]), .Y(n3323) );
OAI22X1TS U4464 ( .A0(n3412), .A1(FPMULT_Op_MX[19]), .B0(n2422), .B1(
FPMULT_Op_MX[20]), .Y(n3319) );
OAI22X1TS U4465 ( .A0(n3412), .A1(FPMULT_Op_MX[16]), .B0(n2422), .B1(
FPMULT_Op_MX[17]), .Y(n3359) );
OAI22X1TS U4466 ( .A0(n3412), .A1(FPMULT_Op_MX[17]), .B0(n2422), .B1(
FPMULT_Op_MX[18]), .Y(n3345) );
OAI22X1TS U4467 ( .A0(n3412), .A1(FPMULT_Op_MX[15]), .B0(n2422), .B1(
FPMULT_Op_MX[16]), .Y(n3375) );
OAI22X1TS U4468 ( .A0(n3412), .A1(FPMULT_Op_MX[14]), .B0(n2422), .B1(
FPMULT_Op_MX[15]), .Y(n3392) );
OAI22X1TS U4469 ( .A0(n3412), .A1(FPMULT_Op_MX[13]), .B0(n2422), .B1(
FPMULT_Op_MX[14]), .Y(n3413) );
OAI22X1TS U4470 ( .A0(n3412), .A1(n2393), .B0(n2422), .B1(FPMULT_Op_MX[13]),
.Y(n3433) );
NOR2BX1TS U4471 ( .AN(n2200), .B(n2422), .Y(n3446) );
NAND2X4TS U4472 ( .A(n2422), .B(DP_OP_453J208_122_681_n2082), .Y(n3412) );
XNOR2X1TS U4473 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[21]), .Y(n3428) );
BUFX3TS U4474 ( .A(n3051), .Y(n2423) );
AO21X1TS U4475 ( .A0(n3052), .A1(n2423), .B0(n2468), .Y(n3071) );
OAI22X1TS U4476 ( .A0(n3052), .A1(n2844), .B0(n2423), .B1(n2468), .Y(n3055)
);
OAI22X1TS U4477 ( .A0(n3052), .A1(n2891), .B0(n2869), .B1(n2423), .Y(n2896)
);
OAI22X1TS U4478 ( .A0(n3052), .A1(n2869), .B0(n2853), .B1(n2423), .Y(n2862)
);
OAI22X1TS U4479 ( .A0(n3052), .A1(n2935), .B0(n2973), .B1(n2423), .Y(n2986)
);
OAI22X1TS U4480 ( .A0(n3052), .A1(n2973), .B0(n2972), .B1(n2423), .Y(n2991)
);
OAI22X1TS U4481 ( .A0(n3052), .A1(n2928), .B0(n2911), .B1(n3051), .Y(n3010)
);
OAI22X1TS U4482 ( .A0(n3052), .A1(n2972), .B0(n2928), .B1(n2423), .Y(n2969)
);
NAND2X4TS U4483 ( .A(n2843), .B(n3051), .Y(n3052) );
XOR2X1TS U4484 ( .A(n2635), .B(n2627), .Y(n2778) );
INVX2TS U4485 ( .A(n2424), .Y(n2768) );
XNOR2X1TS U4486 ( .A(n2838), .B(n2424), .Y(n2780) );
XNOR2X1TS U4487 ( .A(n2424), .B(n2840), .Y(n2782) );
BUFX4TS U4488 ( .A(n2749), .Y(n2425) );
INVX2TS U4489 ( .A(n2425), .Y(n3857) );
XNOR2X1TS U4490 ( .A(n2425), .B(n2304), .Y(n2651) );
XNOR2X1TS U4491 ( .A(n2601), .B(FPMULT_Op_MX[11]), .Y(n2749) );
XOR2X1TS U4492 ( .A(n2604), .B(n2603), .Y(n2762) );
INVX2TS U4493 ( .A(n2426), .Y(n2754) );
XNOR2X1TS U4494 ( .A(n2426), .B(n2304), .Y(n2660) );
OR3X1TS U4495 ( .A(n2403), .B(n2408), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n5101) );
BUFX3TS U4496 ( .A(n3479), .Y(n2428) );
AO21X1TS U4497 ( .A0(n3482), .A1(n2428), .B0(n2462), .Y(n3356) );
OAI22X1TS U4498 ( .A0(n3482), .A1(n2395), .B0(n2428), .B1(n2462), .Y(n3363)
);
OAI22X1TS U4499 ( .A0(n3482), .A1(n3395), .B0(n3379), .B1(n2428), .Y(n3397)
);
OAI22X1TS U4500 ( .A0(n3482), .A1(n3480), .B0(n3467), .B1(n2428), .Y(n3492)
);
OAI22X1TS U4501 ( .A0(n3482), .A1(n3481), .B0(n3480), .B1(n2428), .Y(n3499)
);
OAI22X1TS U4502 ( .A0(n3482), .A1(n3467), .B0(n3432), .B1(n2428), .Y(n3451)
);
OAI22X1TS U4503 ( .A0(n3482), .A1(n2671), .B0(n3481), .B1(n2428), .Y(n3510)
);
OAI22X1TS U4504 ( .A0(n3482), .A1(n2687), .B0(n2671), .B1(n2427), .Y(n2681)
);
OAI22X1TS U4505 ( .A0(n3482), .A1(n2694), .B0(n2693), .B1(n2427), .Y(n3528)
);
NAND2X4TS U4506 ( .A(n2669), .B(n2427), .Y(n3482) );
XNOR2X1TS U4507 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[13]), .Y(n3479) );
NOR2XLTS U4508 ( .A(n4185), .B(FPADDSUB_intDY_EWSW[16]), .Y(n4186) );
OAI221X1TS U4509 ( .A0(n5675), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5684),
.B1(FPADDSUB_intDY_EWSW[15]), .C0(n5257), .Y(n5262) );
CLKBUFX2TS U4510 ( .A(n3092), .Y(n2429) );
BUFX3TS U4511 ( .A(n3092), .Y(n2430) );
AO21X1TS U4512 ( .A0(n3093), .A1(n2430), .B0(n2485), .Y(n3102) );
OAI22X1TS U4513 ( .A0(n3093), .A1(n3058), .B0(n2430), .B1(n3068), .Y(n3075)
);
OAI22X1TS U4514 ( .A0(n3093), .A1(n3068), .B0(n2430), .B1(n2485), .Y(n3089)
);
OAI22X1TS U4515 ( .A0(n3093), .A1(n2857), .B0(n2430), .B1(n3058), .Y(n3049)
);
OAI22X1TS U4516 ( .A0(n3093), .A1(n2851), .B0(n2430), .B1(n2848), .Y(n2874)
);
OAI22X1TS U4517 ( .A0(n3093), .A1(n2890), .B0(n2430), .B1(n2851), .Y(n2878)
);
OAI22X1TS U4518 ( .A0(n3093), .A1(n2982), .B0(n2429), .B1(n2976), .Y(n3013)
);
OAI22X1TS U4519 ( .A0(n3093), .A1(n2933), .B0(n2429), .B1(n2932), .Y(n2937)
);
OAI22X1TS U4520 ( .A0(n3093), .A1(n2983), .B0(n2429), .B1(n2982), .Y(n2984)
);
OAI22X1TS U4521 ( .A0(n3093), .A1(n2976), .B0(n2429), .B1(n2907), .Y(n2925)
);
OAI22X1TS U4522 ( .A0(n3093), .A1(n2907), .B0(n2429), .B1(n2890), .Y(n2908)
);
NAND2X4TS U4523 ( .A(n2845), .B(n2429), .Y(n3093) );
XNOR2X1TS U4524 ( .A(FPMULT_Op_MY[4]), .B(n2299), .Y(n3092) );
CLKBUFX2TS U4525 ( .A(n3122), .Y(n2431) );
BUFX3TS U4526 ( .A(n3122), .Y(n2432) );
OAI22X1TS U4527 ( .A0(n3123), .A1(n3087), .B0(n3108), .B1(n2432), .Y(n3105)
);
OAI22X1TS U4528 ( .A0(n3123), .A1(n3069), .B0(n2432), .B1(n3087), .Y(n3088)
);
OAI22X1TS U4529 ( .A0(n3123), .A1(n3050), .B0(n2432), .B1(n3069), .Y(n3072)
);
OAI22X1TS U4530 ( .A0(n3123), .A1(n2975), .B0(n2432), .B1(n2978), .Y(n2989)
);
NOR2BX1TS U4531 ( .AN(FPMULT_Op_MX[0]), .B(n2431), .Y(n2988) );
NAND2X4TS U4532 ( .A(n2846), .B(n2431), .Y(n3123) );
XNOR2X1TS U4533 ( .A(FPMULT_Op_MY[6]), .B(n2300), .Y(n3122) );
CLKBUFX2TS U4534 ( .A(n3140), .Y(n2433) );
BUFX3TS U4535 ( .A(n3140), .Y(n2434) );
OAI22X1TS U4536 ( .A0(n3141), .A1(n3125), .B0(n3132), .B1(n2434), .Y(n3129)
);
OAI22X1TS U4537 ( .A0(n3141), .A1(n3109), .B0(n2434), .B1(n3125), .Y(n3116)
);
OAI22X1TS U4538 ( .A0(n3141), .A1(n3054), .B0(n2434), .B1(n3073), .Y(n3064)
);
OAI22X1TS U4539 ( .A0(n3141), .A1(n3091), .B0(n2434), .B1(n3109), .Y(n3103)
);
OAI22X1TS U4540 ( .A0(n3141), .A1(n3073), .B0(n2434), .B1(n3091), .Y(n3086)
);
OAI22X1TS U4541 ( .A0(n3141), .A1(n2860), .B0(n2434), .B1(n3054), .Y(n3043)
);
OAI22X1TS U4542 ( .A0(n3141), .A1(n2871), .B0(n2434), .B1(n2861), .Y(n2888)
);
OAI22X1TS U4543 ( .A0(n3141), .A1(n2861), .B0(n2434), .B1(n2860), .Y(n2868)
);
OAI22X1TS U4544 ( .A0(n3141), .A1(n2893), .B0(n2433), .B1(n2871), .Y(n2894)
);
OAI22X1TS U4545 ( .A0(n3141), .A1(n2923), .B0(n2433), .B1(n2893), .Y(n2920)
);
OAI22X1TS U4546 ( .A0(n3141), .A1(n2924), .B0(n2433), .B1(n2923), .Y(n3016)
);
OAI22X1TS U4547 ( .A0(n3141), .A1(DP_OP_453J208_122_681_n1722), .B0(n2433),
.B1(n2913), .Y(n3008) );
NOR2BX1TS U4548 ( .AN(FPMULT_Op_MX[0]), .B(n2433), .Y(n2971) );
NAND2X4TS U4549 ( .A(n2842), .B(n2433), .Y(n3141) );
XNOR2X1TS U4550 ( .A(n2391), .B(FPMULT_Op_MY[8]), .Y(n3140) );
CLKBUFX2TS U4551 ( .A(FPMULT_Op_MY[11]), .Y(n2435) );
XOR2X1TS U4552 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MY[10]), .Y(n2847) );
XNOR2X1TS U4553 ( .A(FPMULT_Op_MY[11]), .B(FPMULT_Op_MX[0]), .Y(n2876) );
XOR2X1TS U4554 ( .A(n2436), .B(FPMULT_Op_MY[8]), .Y(n2842) );
XNOR2X1TS U4555 ( .A(n2436), .B(FPMULT_Op_MX[0]), .Y(n2924) );
XOR2X1TS U4556 ( .A(n2438), .B(FPMULT_Op_MY[16]), .Y(n2668) );
XOR2X1TS U4557 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MY[18]), .Y(n2546) );
XNOR2X1TS U4558 ( .A(n4024), .B(n4023), .Y(n2441) );
AND2X2TS U4559 ( .A(n4047), .B(n2526), .Y(n2444) );
INVX2TS U4560 ( .A(n4915), .Y(n4916) );
BUFX4TS U4561 ( .A(n4986), .Y(n4980) );
OR2X2TS U4562 ( .A(n3168), .B(n3167), .Y(n2450) );
OR2X1TS U4563 ( .A(n3689), .B(n3688), .Y(n2451) );
OR2X1TS U4564 ( .A(FPMULT_Op_MY[0]), .B(FPMULT_Op_MY[12]), .Y(n2454) );
BUFX4TS U4565 ( .A(n4284), .Y(n4350) );
MXI2X1TS U4566 ( .A(Data_2[22]), .B(FPMULT_Op_MY[22]), .S0(n4676), .Y(n2458)
);
AOI22X1TS U4567 ( .A0(n4909), .A1(n5783), .B0(n4911), .B1(n3534), .Y(n2467)
);
OR2X1TS U4568 ( .A(n3584), .B(n3583), .Y(n2470) );
OR2X1TS U4569 ( .A(DP_OP_453J208_122_681_n438), .B(
DP_OP_453J208_122_681_n444), .Y(n2471) );
OA21XLTS U4570 ( .A0(n3680), .A1(n3558), .B0(n3681), .Y(n2472) );
OR2X1TS U4571 ( .A(n3729), .B(n3728), .Y(n2473) );
OR2X1TS U4572 ( .A(n3694), .B(n3693), .Y(n2479) );
OR2X2TS U4573 ( .A(n3749), .B(n3748), .Y(n2480) );
OAI22X1TS U4574 ( .A0(n3478), .A1(n2715), .B0(n2696), .B1(n2224), .Y(n3581)
);
INVX2TS U4575 ( .A(n3581), .Y(n2713) );
OR2X1TS U4576 ( .A(n2954), .B(n2953), .Y(n2482) );
OR2X1TS U4577 ( .A(n2296), .B(FPMULT_Op_MY[13]), .Y(n2484) );
OR2X2TS U4578 ( .A(n3001), .B(n3000), .Y(n2488) );
OR2X2TS U4579 ( .A(n2999), .B(n2998), .Y(n2490) );
OR2X1TS U4580 ( .A(n4746), .B(n4745), .Y(n2492) );
CLKAND2X2TS U4581 ( .A(n2492), .B(n4747), .Y(n2493) );
OR2X1TS U4582 ( .A(n3553), .B(n3552), .Y(n2494) );
BUFX3TS U4583 ( .A(n5510), .Y(n5523) );
INVX2TS U4584 ( .A(n2422), .Y(n3316) );
OR2X1TS U4585 ( .A(n4008), .B(n4007), .Y(n2501) );
OR2X1TS U4586 ( .A(n4021), .B(DP_OP_453J208_122_681_n1748), .Y(n2502) );
BUFX3TS U4587 ( .A(n4235), .Y(n4255) );
AND2X2TS U4588 ( .A(n5783), .B(n5291), .Y(n4265) );
OR2X2TS U4589 ( .A(n3597), .B(n3596), .Y(n2511) );
OR2X1TS U4590 ( .A(DP_OP_453J208_122_681_n424), .B(
DP_OP_453J208_122_681_n431), .Y(n2512) );
OR2X1TS U4591 ( .A(DP_OP_453J208_122_681_n406), .B(
DP_OP_453J208_122_681_n415), .Y(n2514) );
OR2X2TS U4592 ( .A(DP_OP_453J208_122_681_n240), .B(
DP_OP_453J208_122_681_n245), .Y(n2521) );
INVX2TS U4593 ( .A(n2593), .Y(n2553) );
INVX2TS U4594 ( .A(n2563), .Y(n2556) );
NAND2X1TS U4595 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[6]), .Y(n2586) );
NAND2X1TS U4596 ( .A(n2296), .B(FPMULT_Op_MY[13]), .Y(n2648) );
NAND2X1TS U4597 ( .A(n2598), .B(n2597), .Y(n2599) );
NAND2X1TS U4598 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MX[10]), .Y(n2559) );
NOR2X1TS U4599 ( .A(n2701), .B(n2700), .Y(n2702) );
INVX2TS U4600 ( .A(n2830), .Y(n2733) );
OAI22X1TS U4601 ( .A0(n3093), .A1(n2848), .B0(n2430), .B1(n2857), .Y(n2856)
);
OAI22X1TS U4602 ( .A0(n3180), .A1(n3053), .B0(n3179), .B1(n3074), .Y(n3070)
);
XNOR2X1TS U4603 ( .A(n2834), .B(n2415), .Y(n2837) );
OAI22X1TS U4604 ( .A0(n2783), .A1(n2768), .B0(n2781), .B1(n2667), .Y(n2676)
);
INVX2TS U4605 ( .A(n3194), .Y(n3171) );
INVX2TS U4606 ( .A(n2826), .Y(n2731) );
OAI22X1TS U4607 ( .A0(n3482), .A1(n3427), .B0(n3395), .B1(n2428), .Y(n3417)
);
XOR2X1TS U4608 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[14]), .Y(n2669) );
INVX2TS U4609 ( .A(n3882), .Y(DP_OP_453J208_122_681_n836) );
INVX2TS U4610 ( .A(n3932), .Y(DP_OP_453J208_122_681_n829) );
OAI22X1TS U4611 ( .A0(n2837), .A1(n3556), .B0(n2839), .B1(n3543), .Y(
DP_OP_453J208_122_681_n581) );
OAI22X1TS U4612 ( .A0(n3180), .A1(n3124), .B0(n2402), .B1(n3133), .Y(n3135)
);
OAI22X1TS U4613 ( .A0(n2805), .A1(n2813), .B0(n2804), .B1(n2815), .Y(
DP_OP_453J208_122_681_n561) );
OAI22X1TS U4614 ( .A0(n3497), .A1(n3496), .B0(n3495), .B1(n2292), .Y(n3515)
);
INVX2TS U4615 ( .A(n3981), .Y(DP_OP_453J208_122_681_n822) );
OAI22X1TS U4616 ( .A0(n3509), .A1(n3430), .B0(n2400), .B1(n3416), .Y(n3444)
);
INVX2TS U4617 ( .A(n3694), .Y(DP_OP_453J208_122_681_n460) );
INVX2TS U4618 ( .A(n4744), .Y(DP_OP_453J208_122_681_n464) );
OAI22X1TS U4619 ( .A0(n3482), .A1(n2693), .B0(n2687), .B1(n2427), .Y(n3525)
);
CMPR42X1TS U4620 ( .A(DP_OP_453J208_122_681_n826), .B(
DP_OP_453J208_122_681_n825), .C(DP_OP_453J208_122_681_n828), .D(
DP_OP_453J208_122_681_n515), .ICI(DP_OP_453J208_122_681_n295), .S(
DP_OP_453J208_122_681_n286), .ICO(DP_OP_453J208_122_681_n284), .CO(
DP_OP_453J208_122_681_n285) );
OAI22X1TS U4621 ( .A0(n3465), .A1(n3330), .B0(n3318), .B1(n2398), .Y(n3333)
);
NOR2X2TS U4622 ( .A(DP_OP_453J208_122_681_n350), .B(
DP_OP_453J208_122_681_n361), .Y(n3565) );
INVX2TS U4623 ( .A(n4731), .Y(n3559) );
INVX2TS U4624 ( .A(n3231), .Y(n3223) );
INVX2TS U4625 ( .A(n3197), .Y(n3200) );
NOR2X1TS U4626 ( .A(n3786), .B(n3784), .Y(n3593) );
NAND2X1TS U4627 ( .A(n3581), .B(n2711), .Y(n3582) );
OAI21X2TS U4628 ( .A0(n3639), .A1(n3567), .B0(n3566), .Y(n3725) );
INVX2TS U4629 ( .A(n3754), .Y(n3756) );
XNOR2X1TS U4630 ( .A(n2297), .B(FPMULT_Op_MX[3]), .Y(n2948) );
OAI22X1TS U4631 ( .A0(n2981), .A1(n2980), .B0(n2979), .B1(n3555), .Y(n2985)
);
OAI22X1TS U4632 ( .A0(n3052), .A1(n2911), .B0(n2891), .B1(n3051), .Y(n2922)
);
INVX2TS U4633 ( .A(n3261), .Y(n3263) );
INVX2TS U4634 ( .A(n3673), .Y(n3560) );
INVX2TS U4635 ( .A(n3665), .Y(n3561) );
INVX2TS U4636 ( .A(n3657), .Y(n3562) );
NOR2X2TS U4637 ( .A(n3589), .B(n3588), .Y(n3784) );
OAI21X1TS U4638 ( .A0(n2713), .A1(n3740), .B0(n3582), .Y(n3746) );
OAI211XLTS U4639 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n5620), .B0(n4166), .C0(
n4169), .Y(n4180) );
AOI21X1TS U4640 ( .A0(n3276), .A1(n3260), .B0(n3259), .Y(n3265) );
NAND2X1TS U4641 ( .A(n3235), .B(n3234), .Y(n3236) );
INVX2TS U4642 ( .A(n3641), .Y(n3651) );
NAND2X1TS U4643 ( .A(n2510), .B(n3796), .Y(n3797) );
AOI21X1TS U4644 ( .A0(n3865), .A1(n3810), .B0(n3809), .Y(n3813) );
NOR2X4TS U4645 ( .A(n2966), .B(n2965), .Y(n3297) );
AOI22X1TS U4646 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(n5550), .B0(n5372), .B1(
n5371), .Y(n5379) );
OAI21XLTS U4647 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4662), .B0(n4661), .Y(
n4663) );
INVX2TS U4648 ( .A(n3307), .Y(n3309) );
NAND2X1TS U4649 ( .A(n3026), .B(n3025), .Y(n3279) );
INVX2TS U4650 ( .A(n4721), .Y(n4723) );
OAI21XLTS U4651 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n5545), .B0(n5347),
.Y(n5348) );
OAI21XLTS U4652 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n5607), .B0(n5372),
.Y(n5373) );
NAND2X1TS U4653 ( .A(n2443), .B(n4032), .Y(n4033) );
NAND2X1TS U4654 ( .A(n2451), .B(n4748), .Y(n4750) );
OAI21X2TS U4655 ( .A0(n4721), .A1(n4724), .B0(n4722), .Y(n4728) );
NAND2X1TS U4656 ( .A(n3613), .B(n3852), .Y(n3824) );
INVX2TS U4657 ( .A(n3975), .Y(n3971) );
NOR2X2TS U4658 ( .A(n5602), .B(n5111), .Y(n5113) );
OAI211XLTS U4659 ( .A0(n4508), .A1(n5562), .B0(n4507), .C0(n4506), .Y(n4509)
);
BUFX3TS U4660 ( .A(n4995), .Y(n5032) );
NAND2X1TS U4661 ( .A(n5033), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n5026) );
NAND2BX1TS U4662 ( .AN(n4550), .B(n5045), .Y(n5046) );
XNOR2X1TS U4663 ( .A(n4781), .B(n4780), .Y(n4782) );
OAI21XLTS U4664 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n5702), .B0(n5167),
.Y(n5168) );
OAI21XLTS U4665 ( .A0(n5144), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
n5147), .Y(n5145) );
OAI211XLTS U4666 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n5113), .B0(
n5138), .C0(n5115), .Y(n5114) );
BUFX3TS U4667 ( .A(n4947), .Y(n4944) );
AOI211XLTS U4668 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n4939), .B0(n4092),
.C0(n4091), .Y(n4093) );
NOR2X4TS U4669 ( .A(operation[1]), .B(operation[2]), .Y(n4906) );
INVX2TS U4670 ( .A(n4282), .Y(n4908) );
OAI21XLTS U4671 ( .A0(n4073), .A1(n4896), .B0(n4959), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
OAI211XLTS U4672 ( .A0(n4804), .A1(n5755), .B0(n4069), .C0(n4068), .Y(n1523)
);
NOR2XLTS U4673 ( .A(n4897), .B(n4952), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
OAI33X4TS U4674 ( .A0(n5612), .A1(n5530), .A2(n5551), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n4909) );
INVX2TS U4675 ( .A(n4909), .Y(n4911) );
NOR2X2TS U4676 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n5551),
.Y(n4121) );
NOR2X2TS U4677 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n4047) );
INVX4TS U4678 ( .A(n2444), .Y(n4676) );
CLKXOR2X4TS U4679 ( .A(n2531), .B(n2530), .Y(n2767) );
XNOR2X4TS U4680 ( .A(n2722), .B(n2569), .Y(n2824) );
CLKXOR2X4TS U4681 ( .A(n2576), .B(n2575), .Y(n2798) );
XNOR2X4TS U4682 ( .A(n2595), .B(n2592), .Y(n2832) );
CLKXOR2X4TS U4683 ( .A(n2606), .B(n2605), .Y(n3858) );
INVX2TS U4684 ( .A(n2615), .Y(n2617) );
XNOR2X4TS U4685 ( .A(n2619), .B(n2618), .Y(n2834) );
CLKXOR2X4TS U4686 ( .A(n2632), .B(n2631), .Y(n2781) );
INVX2TS U4687 ( .A(n2643), .Y(n2645) );
XNOR2X4TS U4688 ( .A(n2650), .B(n2649), .Y(n2840) );
XNOR2X1TS U4689 ( .A(n2424), .B(n2304), .Y(n2666) );
OAI22X1TS U4690 ( .A0(n2783), .A1(n2666), .B0(n2781), .B1(n2782), .Y(n2674)
);
XNOR2X1TS U4691 ( .A(n2838), .B(n2419), .Y(n2677) );
XNOR2X1TS U4692 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MX[13]), .Y(n2678) );
XNOR2X1TS U4693 ( .A(n2438), .B(FPMULT_Op_MX[14]), .Y(n3496) );
XNOR2X1TS U4694 ( .A(n2382), .B(FPMULT_Op_MX[16]), .Y(n2686) );
XNOR2X1TS U4695 ( .A(n2382), .B(FPMULT_Op_MX[17]), .Y(n2670) );
INVX2TS U4696 ( .A(n3594), .Y(n2675) );
XNOR2X1TS U4697 ( .A(n2840), .B(n2419), .Y(n2795) );
OAI22X1TS U4698 ( .A0(n2677), .A1(n2798), .B0(n2797), .B1(n2795), .Y(n2685)
);
NOR2BX1TS U4699 ( .AN(n2304), .B(n2781), .Y(n2684) );
XNOR2X1TS U4700 ( .A(n2438), .B(n2393), .Y(n2679) );
INVX2TS U4701 ( .A(n3590), .Y(n2683) );
XNOR2X1TS U4702 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MX[13]), .Y(n2693) );
INVX2TS U4703 ( .A(n3588), .Y(n2691) );
OAI22X1TS U4704 ( .A0(n2797), .A1(n2689), .B0(n2798), .B1(n2688), .Y(n2690)
);
XNOR2X1TS U4705 ( .A(n2395), .B(n2393), .Y(n2694) );
INVX2TS U4706 ( .A(n3584), .Y(n2709) );
OAI22X2TS U4707 ( .A0(n3482), .A1(n2462), .B0(n2427), .B1(n2695), .Y(n3583)
);
INVX2TS U4708 ( .A(n3583), .Y(n2710) );
XNOR2X1TS U4709 ( .A(n2382), .B(FPMULT_Op_MX[13]), .Y(n2715) );
NOR2BX1TS U4710 ( .AN(n2200), .B(n2427), .Y(n2711) );
CLKXOR2X4TS U4711 ( .A(n2699), .B(n2698), .Y(n2815) );
XNOR2X1TS U4712 ( .A(n2417), .B(n2303), .Y(n2706) );
XNOR2X1TS U4713 ( .A(n2840), .B(n2417), .Y(n2812) );
OAI22X1TS U4714 ( .A0(n2813), .A1(n2706), .B0(n2815), .B1(n2812), .Y(n2707)
);
INVX2TS U4715 ( .A(n2711), .Y(n2712) );
XNOR2X2TS U4716 ( .A(n2713), .B(n2712), .Y(DP_OP_453J208_122_681_n447) );
NAND2X1TS U4717 ( .A(n2714), .B(n3478), .Y(n3729) );
INVX2TS U4718 ( .A(n3729), .Y(n3540) );
OAI22X2TS U4719 ( .A0(n3478), .A1(n2200), .B0(n2715), .B1(n2224), .Y(n3728)
);
INVX2TS U4720 ( .A(n3728), .Y(n3539) );
OAI22X1TS U4721 ( .A0(n2779), .A1(n2781), .B0(n2783), .B1(n2780), .Y(
DP_OP_453J208_122_681_n537) );
OAI22X1TS U4722 ( .A0(n2790), .A1(n2798), .B0(n2791), .B1(n2797), .Y(
DP_OP_453J208_122_681_n549) );
OAI22X1TS U4723 ( .A0(n2793), .A1(n2798), .B0(n2792), .B1(n2797), .Y(
DP_OP_453J208_122_681_n551) );
XNOR2X1TS U4724 ( .A(n2419), .B(n2303), .Y(n2796) );
OAI22X1TS U4725 ( .A0(n2797), .A1(n2796), .B0(n2798), .B1(n2795), .Y(
DP_OP_453J208_122_681_n554) );
NOR2BX1TS U4726 ( .AN(n2303), .B(n2798), .Y(DP_OP_453J208_122_681_n555) );
OAI22X1TS U4727 ( .A0(n2813), .A1(n2800), .B0(n2815), .B1(n2799), .Y(
DP_OP_453J208_122_681_n480) );
OAI22X1TS U4728 ( .A0(n2806), .A1(n2813), .B0(n2805), .B1(n2815), .Y(
DP_OP_453J208_122_681_n562) );
XNOR2X1TS U4729 ( .A(n2830), .B(n2417), .Y(n2807) );
OAI22X1TS U4730 ( .A0(n2807), .A1(n2813), .B0(n2806), .B1(n2815), .Y(
DP_OP_453J208_122_681_n563) );
OAI22X1TS U4731 ( .A0(n2807), .A1(n2815), .B0(n2808), .B1(n2813), .Y(
DP_OP_453J208_122_681_n564) );
OAI22X1TS U4732 ( .A0(n2808), .A1(n2815), .B0(n2809), .B1(n2813), .Y(
DP_OP_453J208_122_681_n565) );
OAI22X1TS U4733 ( .A0(n2809), .A1(n2815), .B0(n2811), .B1(n2813), .Y(
DP_OP_453J208_122_681_n566) );
XNOR2X1TS U4734 ( .A(n2838), .B(n2417), .Y(n2814) );
OAI22X1TS U4735 ( .A0(n2811), .A1(n2815), .B0(n2814), .B1(n2813), .Y(
DP_OP_453J208_122_681_n567) );
OAI22X1TS U4736 ( .A0(n2814), .A1(n2815), .B0(n2813), .B1(n2812), .Y(
DP_OP_453J208_122_681_n568) );
NOR2BX1TS U4737 ( .AN(n2303), .B(n2815), .Y(DP_OP_453J208_122_681_n570) );
OAI22X1TS U4738 ( .A0(n2825), .A1(n3543), .B0(n2823), .B1(n3556), .Y(
DP_OP_453J208_122_681_n574) );
OAI22X1TS U4739 ( .A0(n2825), .A1(n3556), .B0(n2827), .B1(n3543), .Y(
DP_OP_453J208_122_681_n575) );
OAI22X1TS U4740 ( .A0(n2831), .A1(n3543), .B0(n2829), .B1(n3556), .Y(
DP_OP_453J208_122_681_n577) );
XNOR2X1TS U4741 ( .A(n2830), .B(n2415), .Y(n2833) );
OAI22X1TS U4742 ( .A0(n2833), .A1(n3543), .B0(n2831), .B1(n3556), .Y(
DP_OP_453J208_122_681_n578) );
XNOR2X1TS U4743 ( .A(n2832), .B(n2415), .Y(n2835) );
OAI22X1TS U4744 ( .A0(n2833), .A1(n3556), .B0(n2835), .B1(n3543), .Y(
DP_OP_453J208_122_681_n579) );
OAI22X1TS U4745 ( .A0(n2835), .A1(n3556), .B0(n2837), .B1(n3543), .Y(
DP_OP_453J208_122_681_n580) );
XNOR2X1TS U4746 ( .A(n2838), .B(n2415), .Y(n2841) );
OAI22X1TS U4747 ( .A0(n2839), .A1(n3556), .B0(n2841), .B1(n3543), .Y(
DP_OP_453J208_122_681_n582) );
XNOR2X1TS U4748 ( .A(n2840), .B(n2415), .Y(n3541) );
OAI22X1TS U4749 ( .A0(n2841), .A1(n3556), .B0(n3543), .B1(n3541), .Y(
DP_OP_453J208_122_681_n583) );
XNOR2X4TS U4750 ( .A(FPMULT_Op_MY[10]), .B(n2436), .Y(n3179) );
XNOR2X1TS U4751 ( .A(n2385), .B(FPMULT_Op_MX[5]), .Y(n2972) );
XNOR2X1TS U4752 ( .A(n2300), .B(FPMULT_Op_MX[1]), .Y(n2932) );
OAI22X1TS U4753 ( .A0(n3093), .A1(n2932), .B0(n2430), .B1(n2983), .Y(n2997)
);
XNOR2X1TS U4754 ( .A(n2297), .B(FPMULT_Op_MX[4]), .Y(n2942) );
XNOR2X1TS U4755 ( .A(n2297), .B(FPMULT_Op_MX[5]), .Y(n2934) );
XNOR2X1TS U4756 ( .A(n2301), .B(FPMULT_Op_MX[0]), .Y(n2933) );
XNOR2X1TS U4757 ( .A(n2297), .B(FPMULT_Op_MX[6]), .Y(n2980) );
XNOR2X1TS U4758 ( .A(n2385), .B(FPMULT_Op_MX[3]), .Y(n2935) );
XNOR2X1TS U4759 ( .A(n2385), .B(FPMULT_Op_MX[4]), .Y(n2973) );
XNOR2X1TS U4760 ( .A(n2385), .B(FPMULT_Op_MX[2]), .Y(n2943) );
OAI22X1TS U4761 ( .A0(n3052), .A1(n2943), .B0(n2935), .B1(n2423), .Y(n2941)
);
NOR2BX1TS U4762 ( .AN(FPMULT_Op_MX[0]), .B(n2430), .Y(n2958) );
OAI22X1TS U4763 ( .A0(n2981), .A1(n2948), .B0(n2942), .B1(n3555), .Y(n2957)
);
XNOR2X1TS U4764 ( .A(n2299), .B(FPMULT_Op_MX[1]), .Y(n2950) );
OAI22X1TS U4765 ( .A0(n3052), .A1(n2950), .B0(n2943), .B1(n2423), .Y(n2956)
);
NOR2X4TS U4766 ( .A(n2964), .B(n2963), .Y(n3302) );
NOR2X2TS U4767 ( .A(n3297), .B(n3302), .Y(n2968) );
XNOR2X1TS U4768 ( .A(n2296), .B(FPMULT_Op_MX[1]), .Y(n2945) );
XNOR2X1TS U4769 ( .A(n2296), .B(FPMULT_Op_MX[2]), .Y(n2949) );
OAI22X1TS U4770 ( .A0(n2981), .A1(n2945), .B0(n2949), .B1(n3555), .Y(n2947)
);
NOR2BX1TS U4771 ( .AN(n2389), .B(n3051), .Y(n2946) );
NOR2X1TS U4772 ( .A(n2947), .B(n2946), .Y(n3545) );
NAND2BXLTS U4773 ( .AN(n2389), .B(n2297), .Y(n2944) );
NAND2X1TS U4774 ( .A(n2944), .B(n2981), .Y(n3553) );
OAI22X1TS U4775 ( .A0(n2981), .A1(n2389), .B0(n2945), .B1(n3555), .Y(n3552)
);
NAND2X1TS U4776 ( .A(n3553), .B(n3552), .Y(n3554) );
NAND2X1TS U4777 ( .A(n2947), .B(n2946), .Y(n3546) );
OAI22X1TS U4778 ( .A0(n2981), .A1(n2949), .B0(n2948), .B1(n3555), .Y(n2960)
);
XNOR2X1TS U4779 ( .A(n2299), .B(n2389), .Y(n2951) );
OAI22X1TS U4780 ( .A0(n3052), .A1(n2951), .B0(n2950), .B1(n3051), .Y(n2959)
);
NAND2BXLTS U4781 ( .AN(n2389), .B(n2385), .Y(n2952) );
OAI22X1TS U4782 ( .A0(n3052), .A1(n2468), .B0(n3051), .B1(n2952), .Y(n2953)
);
INVX2TS U4783 ( .A(n3312), .Y(n2955) );
AOI21X2TS U4784 ( .A0(n3313), .A1(n2482), .B0(n2955), .Y(n3310) );
NAND2X2TS U4785 ( .A(n2966), .B(n2965), .Y(n3298) );
AOI21X4TS U4786 ( .A0(n2968), .A1(n3296), .B0(n2967), .Y(n3288) );
XNOR2X1TS U4787 ( .A(n2302), .B(FPMULT_Op_MX[0]), .Y(n2975) );
XNOR2X1TS U4788 ( .A(n2302), .B(FPMULT_Op_MX[1]), .Y(n2978) );
INVX2TS U4789 ( .A(n3293), .Y(n3289) );
OAI21X4TS U4790 ( .A0(n3288), .A1(n3004), .B0(n3003), .Y(n3277) );
OAI21X4TS U4791 ( .A0(n3040), .A1(n3249), .B0(n3039), .Y(n3248) );
INVX2TS U4792 ( .A(n3268), .Y(n3270) );
INVX2TS U4793 ( .A(n3278), .Y(n3280) );
INVX2TS U4794 ( .A(n3283), .Y(n3285) );
INVX2TS U4795 ( .A(n3288), .Y(n3295) );
AOI21X1TS U4796 ( .A0(n3295), .A1(n2490), .B0(n3289), .Y(n3292) );
NAND2X1TS U4797 ( .A(n2488), .B(n3290), .Y(n3291) );
INVX2TS U4798 ( .A(n4755), .Y(DP_OP_453J208_122_681_n467) );
INVX2TS U4799 ( .A(n4754), .Y(DP_OP_453J208_122_681_n468) );
INVX2TS U4800 ( .A(n3297), .Y(n3299) );
NAND2X1TS U4801 ( .A(n3299), .B(n3298), .Y(n3300) );
INVX2TS U4802 ( .A(n4753), .Y(DP_OP_453J208_122_681_n469) );
INVX2TS U4803 ( .A(n3302), .Y(n3304) );
NAND2X1TS U4804 ( .A(n3304), .B(n3303), .Y(n3305) );
INVX2TS U4805 ( .A(n4733), .Y(DP_OP_453J208_122_681_n470) );
NAND2X1TS U4806 ( .A(n3309), .B(n3308), .Y(n3311) );
INVX2TS U4807 ( .A(n4732), .Y(DP_OP_453J208_122_681_n471) );
NAND2X1TS U4808 ( .A(n2482), .B(n3312), .Y(n3314) );
INVX2TS U4809 ( .A(n4027), .Y(DP_OP_453J208_122_681_n472) );
INVX2TS U4810 ( .A(n3601), .Y(DP_OP_453J208_122_681_n844) );
XNOR2X1TS U4811 ( .A(n2440), .B(n2393), .Y(n3508) );
INVX2TS U4812 ( .A(n3595), .Y(DP_OP_453J208_122_681_n847) );
INVX2TS U4813 ( .A(n3589), .Y(DP_OP_453J208_122_681_n851) );
INVX2TS U4814 ( .A(n3587), .Y(DP_OP_453J208_122_681_n853) );
INVX2TS U4815 ( .A(n3586), .Y(DP_OP_453J208_122_681_n854) );
NAND2X4TS U4816 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4611) );
OAI21XLTS U4817 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(n5553), .B0(n4611),
.Y(n1352) );
NOR4X1TS U4818 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5779) );
NOR4X1TS U4819 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5780) );
NOR4X1TS U4820 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n5782) );
NOR4X1TS U4821 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n5781) );
INVX2TS U4822 ( .A(FPSENCOS_cont_iter_out[2]), .Y(n4915) );
NOR3X1TS U4823 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3530) );
AOI21X1TS U4824 ( .A0(operation[1]), .A1(ack_operation), .B0(n4282), .Y(
n4889) );
NOR2BX1TS U4825 ( .AN(n2206), .B(n2376), .Y(n4028) );
NAND4X2TS U4826 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n4028),
.C(n5557), .D(n5628), .Y(n4912) );
NOR2X2TS U4827 ( .A(n5546), .B(n2446), .Y(n4094) );
OR2X1TS U4828 ( .A(n4889), .B(n4283), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
OR4X2TS U4829 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n3531) );
NOR4X1TS U4830 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n3531),
.Y(n5778) );
OR4X2TS U4831 ( .A(n2376), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n4042) );
NOR2X1TS U4832 ( .A(n2377), .B(n4042), .Y(n3532) );
NAND4X2TS U4833 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n3532),
.C(n5563), .D(n5631), .Y(n4897) );
NOR2BX1TS U4834 ( .AN(n3532), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n4137) );
NAND3X2TS U4835 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n4137),
.C(n5631), .Y(n4896) );
NAND2X1TS U4836 ( .A(n4897), .B(n4896), .Y(n3533) );
BUFX4TS U4837 ( .A(n5025), .Y(n5020) );
BUFX3TS U4838 ( .A(n4434), .Y(n4999) );
AOI22X1TS U4839 ( .A0(Data_2[6]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n4999), .Y(n3538) );
BUFX3TS U4840 ( .A(n4376), .Y(n4996) );
NAND2X1TS U4841 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n4895) );
NOR2X2TS U4842 ( .A(n4354), .B(n4895), .Y(n4385) );
BUFX3TS U4843 ( .A(n4385), .Y(n4453) );
AOI22X1TS U4844 ( .A0(n4996), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n3537) );
OAI211XLTS U4845 ( .A0(n4355), .A1(n5768), .B0(n3538), .C0(n3537), .Y(n1839)
);
NAND2BX1TS U4846 ( .AN(n2303), .B(n2415), .Y(n3544) );
NAND2X1TS U4847 ( .A(n3544), .B(n3543), .Y(n3549) );
NOR2X2TS U4848 ( .A(DP_OP_453J208_122_681_n432), .B(
DP_OP_453J208_122_681_n437), .Y(n3668) );
INVX2TS U4849 ( .A(n3545), .Y(n3547) );
NAND2X1TS U4850 ( .A(n3547), .B(n3546), .Y(n3548) );
XOR2X1TS U4851 ( .A(n3548), .B(n3554), .Y(n4731) );
NAND2X1TS U4852 ( .A(n2494), .B(n3554), .Y(n4741) );
NOR2BX1TS U4853 ( .AN(FPMULT_Op_MX[0]), .B(n3555), .Y(n4740) );
INVX2TS U4854 ( .A(n4740), .Y(n3687) );
INVX2TS U4855 ( .A(n3723), .Y(n3686) );
NOR2BX1TS U4856 ( .AN(n2304), .B(n3556), .Y(n3685) );
INVX2TS U4857 ( .A(n3683), .Y(n3558) );
NAND2X1TS U4858 ( .A(n3557), .B(n4741), .Y(n3681) );
NAND2X1TS U4859 ( .A(DP_OP_453J208_122_681_n445), .B(n3559), .Y(n3677) );
AOI21X2TS U4860 ( .A0(n2471), .A1(n3674), .B0(n3560), .Y(n3671) );
AOI21X4TS U4861 ( .A0(n3569), .A1(n3725), .B0(n3568), .Y(n3632) );
OAI21X4TS U4862 ( .A0(n3573), .A1(n3632), .B0(n3572), .Y(n3865) );
NAND2X1TS U4863 ( .A(n3729), .B(n3728), .Y(n3740) );
NAND2X1TS U4864 ( .A(n3584), .B(n3583), .Y(n3745) );
INVX2TS U4865 ( .A(n3745), .Y(n3585) );
AOI21X1TS U4866 ( .A0(n3746), .A1(n2470), .B0(n3585), .Y(n3762) );
INVX2TS U4867 ( .A(n3636), .Y(n3785) );
INVX2TS U4868 ( .A(n3784), .Y(n3637) );
NAND2X1TS U4869 ( .A(n3637), .B(n3783), .Y(n3638) );
INVX2TS U4870 ( .A(n3652), .Y(n3654) );
INVX2TS U4871 ( .A(n3660), .Y(n3662) );
NAND2X1TS U4872 ( .A(n3662), .B(n3661), .Y(n3663) );
INVX2TS U4873 ( .A(n3668), .Y(n3670) );
NAND2X1TS U4874 ( .A(n3670), .B(n3669), .Y(n3672) );
NAND2X1TS U4875 ( .A(n2471), .B(n3673), .Y(n3675) );
INVX2TS U4876 ( .A(n3676), .Y(n3678) );
NAND2X1TS U4877 ( .A(n3678), .B(n3677), .Y(n3679) );
NOR2X2TS U4878 ( .A(n3692), .B(n3691), .Y(n4691) );
INVX2TS U4879 ( .A(n3680), .Y(n3682) );
NAND2X1TS U4880 ( .A(n3682), .B(n3681), .Y(n3684) );
XNOR2X1TS U4881 ( .A(n3684), .B(n3683), .Y(n3688) );
CMPR32X2TS U4882 ( .A(n3687), .B(n3686), .C(n3685), .CO(n3683), .S(n4745) );
NAND2X2TS U4883 ( .A(n4746), .B(n4745), .Y(n4747) );
INVX2TS U4884 ( .A(n4747), .Y(n4749) );
AOI21X4TS U4885 ( .A0(n2451), .A1(n4749), .B0(n3690), .Y(n4694) );
NAND2X2TS U4886 ( .A(n3692), .B(n3691), .Y(n4692) );
OAI21X4TS U4887 ( .A0(n4691), .A1(n4694), .B0(n4692), .Y(n4698) );
INVX2TS U4888 ( .A(n4697), .Y(n3695) );
AOI21X4TS U4889 ( .A0(n2479), .A1(n4698), .B0(n3695), .Y(n4704) );
AOI21X4TS U4890 ( .A0(n2497), .A1(n4708), .B0(n3700), .Y(n4714) );
OAI21X4TS U4891 ( .A0(n4711), .A1(n4714), .B0(n4712), .Y(n4718) );
INVX2TS U4892 ( .A(n4717), .Y(n3705) );
AOI21X4TS U4893 ( .A0(n2513), .A1(n4718), .B0(n3705), .Y(n4724) );
INVX2TS U4894 ( .A(n4727), .Y(n3710) );
AOI21X4TS U4895 ( .A0(n2452), .A1(n4728), .B0(n3710), .Y(n4737) );
OAI21X4TS U4896 ( .A0(n4793), .A1(n4789), .B0(n4790), .Y(n4034) );
AOI21X4TS U4897 ( .A0(n4034), .A1(n2443), .B0(n3731), .Y(n4787) );
OAI21X4TS U4898 ( .A0(n4787), .A1(n4783), .B0(n4784), .Y(n4781) );
NAND2X1TS U4899 ( .A(n2470), .B(n3745), .Y(n3747) );
INVX2TS U4900 ( .A(n3759), .Y(n3761) );
NAND2X1TS U4901 ( .A(n3761), .B(n3760), .Y(n3763) );
INVX2TS U4902 ( .A(n3786), .Y(n3788) );
NOR2X2TS U4903 ( .A(n4133), .B(n5554), .Y(n4088) );
NOR3X1TS U4904 ( .A(n5532), .B(FPMULT_FS_Module_state_reg[3]), .C(
FPMULT_FS_Module_state_reg[0]), .Y(n4050) );
INVX2TS U4905 ( .A(n4050), .Y(n4030) );
NAND2X2TS U4906 ( .A(n3825), .B(n4030), .Y(n4680) );
BUFX4TS U4907 ( .A(n4680), .Y(n4820) );
INVX2TS U4908 ( .A(n3869), .Y(n3870) );
INVX2TS U4909 ( .A(n3910), .Y(n3896) );
INVX2TS U4910 ( .A(n3913), .Y(n3901) );
INVX2TS U4911 ( .A(n3929), .Y(n3919) );
INVX2TS U4912 ( .A(n4005), .Y(n3995) );
NAND2X1TS U4913 ( .A(n2501), .B(n4018), .Y(n4009) );
INVX2TS U4914 ( .A(n4018), .Y(n4019) );
NAND2X1TS U4915 ( .A(n2502), .B(n4022), .Y(n4023) );
CLKMX2X2TS U4916 ( .A(FPMULT_P_Sgf[47]), .B(n4026), .S0(n4820), .Y(n1552) );
BUFX4TS U4917 ( .A(n4680), .Y(n4751) );
MX2X1TS U4918 ( .A(FPMULT_P_Sgf[3]), .B(n4027), .S0(n4751), .Y(n1556) );
BUFX3TS U4919 ( .A(n4973), .Y(n5861) );
INVX2TS U4920 ( .A(rst), .Y(n4038) );
INVX1TS U4921 ( .A(n4912), .Y(n4914) );
BUFX3TS U4922 ( .A(n5813), .Y(n5807) );
BUFX3TS U4923 ( .A(n2314), .Y(n5823) );
CLKBUFX2TS U4924 ( .A(n4040), .Y(n5838) );
CLKBUFX2TS U4925 ( .A(n5835), .Y(n5836) );
NOR2XLTS U4926 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n4036) );
BUFX3TS U4927 ( .A(n5859), .Y(n5856) );
BUFX3TS U4928 ( .A(n5857), .Y(n5851) );
BUFX3TS U4929 ( .A(n5857), .Y(n5850) );
BUFX3TS U4930 ( .A(n4040), .Y(n5841) );
BUFX3TS U4931 ( .A(n5831), .Y(n5840) );
BUFX3TS U4932 ( .A(n5830), .Y(n5819) );
BUFX3TS U4933 ( .A(n5790), .Y(n5813) );
BUFX3TS U4934 ( .A(n4040), .Y(n5832) );
BUFX3TS U4935 ( .A(n4040), .Y(n5831) );
BUFX3TS U4936 ( .A(n4040), .Y(n5830) );
CLKBUFX3TS U4937 ( .A(n5823), .Y(n5837) );
BUFX3TS U4938 ( .A(n5832), .Y(n5848) );
BUFX3TS U4939 ( .A(n4040), .Y(n5847) );
BUFX3TS U4940 ( .A(n5831), .Y(n5846) );
BUFX3TS U4941 ( .A(n5830), .Y(n5842) );
BUFX3TS U4942 ( .A(n5830), .Y(n5845) );
BUFX3TS U4943 ( .A(n5789), .Y(n5802) );
BUFX3TS U4944 ( .A(n2314), .Y(n5822) );
BUFX3TS U4945 ( .A(n2316), .Y(n5808) );
BUFX3TS U4946 ( .A(n5857), .Y(n5854) );
BUFX3TS U4947 ( .A(n5849), .Y(n5853) );
BUFX3TS U4948 ( .A(n5796), .Y(n5784) );
BUFX3TS U4949 ( .A(n5832), .Y(n5815) );
BUFX3TS U4950 ( .A(n5790), .Y(n5794) );
BUFX3TS U4951 ( .A(n5793), .Y(n5787) );
BUFX3TS U4952 ( .A(n5799), .Y(n5810) );
BUFX3TS U4953 ( .A(n5785), .Y(n5803) );
BUFX3TS U4954 ( .A(n4039), .Y(n5799) );
BUFX3TS U4955 ( .A(n4039), .Y(n5789) );
BUFX3TS U4956 ( .A(n4039), .Y(n5785) );
BUFX3TS U4957 ( .A(n5799), .Y(n5809) );
INVX2TS U4958 ( .A(n4121), .Y(n4885) );
NAND3XLTS U4959 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n5530),
.C(n5551), .Y(n4119) );
NAND2X1TS U4960 ( .A(n4885), .B(n4119), .Y(n2193) );
NOR3X1TS U4961 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n4041) );
BUFX4TS U4962 ( .A(n4980), .Y(n4992) );
BUFX3TS U4963 ( .A(n4992), .Y(n4984) );
AO22XLTS U4964 ( .A0(n4988), .A1(FPSENCOS_d_ff3_sh_x_out[26]), .B0(n4984),
.B1(intadd_474_SUM_2_), .Y(n1950) );
AO22XLTS U4965 ( .A0(n4988), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n4984),
.B1(intadd_474_SUM_1_), .Y(n1951) );
AO22XLTS U4966 ( .A0(n4988), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n4984),
.B1(intadd_474_SUM_0_), .Y(n1952) );
NAND2X2TS U4967 ( .A(FPSENCOS_cont_iter_out[3]), .B(n4915), .Y(n4100) );
NAND2X2TS U4968 ( .A(n4980), .B(FPSENCOS_cont_iter_out[1]), .Y(n4935) );
INVX2TS U4969 ( .A(n4935), .Y(n4929) );
NAND2X1TS U4970 ( .A(n4929), .B(n4925), .Y(n4923) );
OAI221XLTS U4971 ( .A0(n4980), .A1(n5757), .B0(n4959), .B1(n4100), .C0(n4923), .Y(n2124) );
BUFX3TS U4972 ( .A(n2409), .Y(n5300) );
INVX4TS U4973 ( .A(n5300), .Y(busy) );
NAND2X2TS U4974 ( .A(n5295), .B(n5300), .Y(n5045) );
OAI21XLTS U4975 ( .A0(n5045), .A1(n5641), .B0(n4611), .Y(n2081) );
OAI21XLTS U4976 ( .A0(n5045), .A1(n2305), .B0(n4524), .Y(n2080) );
INVX2TS U4977 ( .A(FPMULT_FS_Module_state_reg[1]), .Y(n4669) );
NOR2X1TS U4978 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n5532), .Y(n4051) );
NOR2BX1TS U4979 ( .AN(FPMULT_P_Sgf[47]), .B(n4672), .Y(n4048) );
NAND4X1TS U4980 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[0]), .C(n5532), .D(n4669), .Y(n5135) );
NOR2X1TS U4981 ( .A(n5618), .B(n4669), .Y(n4046) );
NAND2X1TS U4982 ( .A(n4047), .B(n4046), .Y(n5092) );
OAI211XLTS U4983 ( .A0(n4048), .A1(n5633), .B0(n5146), .C0(n5092), .Y(n1551)
);
INVX2TS U4984 ( .A(n5092), .Y(n5094) );
INVX3TS U4985 ( .A(n5146), .Y(n5148) );
INVX2TS U4986 ( .A(n4048), .Y(n4049) );
OAI31X1TS U4987 ( .A0(n5094), .A1(n5148), .A2(n5637), .B0(n4049), .Y(n1550)
);
AOI32X4TS U4988 ( .A0(FPMULT_FSM_add_overflow_flag), .A1(
FPMULT_FS_Module_state_reg[1]), .A2(n4088), .B0(n4050), .B1(
FPMULT_FS_Module_state_reg[1]), .Y(n5097) );
OR2X2TS U4989 ( .A(n5097), .B(FPMULT_FSM_selector_C), .Y(n4804) );
INVX3TS U4990 ( .A(n4052), .Y(n5095) );
AOI22X1TS U4991 ( .A0(n2403), .A1(n5095), .B0(n2388), .B1(
FPMULT_Add_result[3]), .Y(n4055) );
NAND2X1TS U4992 ( .A(n4052), .B(n5097), .Y(n4053) );
BUFX3TS U4993 ( .A(n4070), .Y(n4859) );
AOI22X1TS U4994 ( .A0(n4859), .A1(FPMULT_P_Sgf[25]), .B0(n2308), .B1(
FPMULT_Add_result[2]), .Y(n4054) );
OAI211XLTS U4995 ( .A0(n4804), .A1(n5752), .B0(n4055), .C0(n4054), .Y(n1519)
);
AOI22X1TS U4996 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n5095), .B0(
n2388), .B1(n2369), .Y(n4057) );
AOI22X1TS U4997 ( .A0(n4859), .A1(FPMULT_P_Sgf[23]), .B0(n2308), .B1(
FPMULT_Add_result[0]), .Y(n4056) );
OAI211XLTS U4998 ( .A0(n4804), .A1(n5754), .B0(n4057), .C0(n4056), .Y(n1517)
);
AOI22X1TS U4999 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n5095), .B0(
n2388), .B1(n2366), .Y(n4059) );
AOI22X1TS U5000 ( .A0(n4859), .A1(FPMULT_P_Sgf[26]), .B0(n2308), .B1(
FPMULT_Add_result[3]), .Y(n4058) );
OAI211XLTS U5001 ( .A0(n4804), .A1(n5751), .B0(n4059), .C0(n4058), .Y(n1520)
);
AOI22X1TS U5002 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n5095), .B0(
n2370), .B1(n2388), .Y(n4061) );
AOI22X1TS U5003 ( .A0(n4859), .A1(FPMULT_P_Sgf[28]), .B0(n2308), .B1(
FPMULT_Add_result[5]), .Y(n4060) );
OAI211XLTS U5004 ( .A0(n4804), .A1(n5756), .B0(n4061), .C0(n4060), .Y(n1522)
);
AOI22X1TS U5005 ( .A0(n2408), .A1(n5095), .B0(n2388), .B1(
FPMULT_Add_result[2]), .Y(n4063) );
AOI22X1TS U5006 ( .A0(n4859), .A1(FPMULT_P_Sgf[24]), .B0(n2308), .B1(n2369),
.Y(n4062) );
OAI211XLTS U5007 ( .A0(n4804), .A1(n5753), .B0(n4063), .C0(n4062), .Y(n1518)
);
AOI22X1TS U5008 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n5095), .B0(
n2388), .B1(FPMULT_Add_result[5]), .Y(n4065) );
AOI22X1TS U5009 ( .A0(n4859), .A1(FPMULT_P_Sgf[27]), .B0(n2308), .B1(n2366),
.Y(n4064) );
OAI211XLTS U5010 ( .A0(n4804), .A1(n5750), .B0(n4065), .C0(n4064), .Y(n1521)
);
AOI22X1TS U5011 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n5095), .B0(
n2341), .B1(n2388), .Y(n4067) );
AOI22X1TS U5012 ( .A0(FPMULT_Add_result[7]), .A1(n2308), .B0(n4859), .B1(
FPMULT_P_Sgf[30]), .Y(n4066) );
OAI211XLTS U5013 ( .A0(n4804), .A1(n2516), .B0(n4067), .C0(n4066), .Y(n1524)
);
AOI22X1TS U5014 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n5095), .B0(
FPMULT_Add_result[7]), .B1(n2388), .Y(n4069) );
AOI22X1TS U5015 ( .A0(n2370), .A1(n2308), .B0(n4859), .B1(FPMULT_P_Sgf[29]),
.Y(n4068) );
AOI22X1TS U5016 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n5688), .Y(n5096) );
INVX3TS U5017 ( .A(n4052), .Y(n4855) );
AOI22X1TS U5018 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n4855), .B0(
FPMULT_Add_result[22]), .B1(n2308), .Y(n4072) );
NAND2X1TS U5019 ( .A(n4070), .B(FPMULT_P_Sgf[45]), .Y(n4071) );
OAI211XLTS U5020 ( .A0(n5097), .A1(n5096), .B0(n4072), .C0(n4071), .Y(n1539)
);
NAND3X1TS U5021 ( .A(FPSENCOS_cont_var_out[1]), .B(n2381), .C(n5705), .Y(
n4953) );
INVX2TS U5022 ( .A(n4094), .Y(n4932) );
NAND2X1TS U5023 ( .A(n4980), .B(n5568), .Y(n4940) );
INVX3TS U5024 ( .A(n4980), .Y(n4939) );
AOI32X1TS U5025 ( .A0(n2197), .A1(n4926), .A2(n4932), .B0(
FPSENCOS_d_ff3_LUT_out[23]), .B1(n4939), .Y(n4074) );
NAND2X1TS U5026 ( .A(n2197), .B(n5567), .Y(intadd_473_CI) );
INVX2TS U5027 ( .A(n4940), .Y(n4076) );
AOI22X1TS U5028 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4076), .B0(
FPSENCOS_d_ff3_sh_y_out[23]), .B1(n4959), .Y(n4075) );
OAI21XLTS U5029 ( .A0(n4939), .A1(intadd_473_CI), .B0(n4075), .Y(n1855) );
OR2X1TS U5030 ( .A(FPSENCOS_d_ff2_X[23]), .B(n5568), .Y(intadd_474_CI) );
AOI22X1TS U5031 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n4076), .B0(
FPSENCOS_d_ff3_sh_x_out[23]), .B1(n4959), .Y(n4077) );
OAI21XLTS U5032 ( .A0(n4939), .A1(intadd_474_CI), .B0(n4077), .Y(n1953) );
NAND2X2TS U5033 ( .A(n4980), .B(n5623), .Y(n4942) );
AOI21X1TS U5034 ( .A0(n2197), .A1(n4916), .B0(FPSENCOS_cont_iter_out[3]),
.Y(n4103) );
AOI22X1TS U5035 ( .A0(n4926), .A1(n4103), .B0(FPSENCOS_d_ff3_LUT_out[26]),
.B1(n4959), .Y(n4078) );
NOR4X1TS U5036 ( .A(FPMULT_P_Sgf[14]), .B(FPMULT_P_Sgf[15]), .C(
FPMULT_P_Sgf[16]), .D(FPMULT_P_Sgf[17]), .Y(n4087) );
NOR4X1TS U5037 ( .A(FPMULT_P_Sgf[18]), .B(FPMULT_P_Sgf[19]), .C(
FPMULT_P_Sgf[20]), .D(FPMULT_P_Sgf[21]), .Y(n4086) );
NOR3XLTS U5038 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[0]), .C(
FPMULT_P_Sgf[1]), .Y(n4081) );
AND4X1TS U5039 ( .A(n4082), .B(n4081), .C(n4080), .D(n4079), .Y(n4085) );
XOR2X1TS U5040 ( .A(FPMULT_Op_MX[31]), .B(FPMULT_Op_MY[31]), .Y(n5154) );
MXI2X1TS U5041 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n5154), .Y(n4083) );
AOI31X1TS U5042 ( .A0(n4087), .A1(n4086), .A2(n4085), .B0(n4084), .Y(n4096)
);
INVX2TS U5043 ( .A(n4088), .Y(n4098) );
OAI221XLTS U5044 ( .A0(FPMULT_FS_Module_state_reg[0]), .A1(
FPMULT_FS_Module_state_reg[1]), .B0(n5618), .B1(n4669), .C0(n5532),
.Y(n4089) );
NOR3X1TS U5045 ( .A(n4916), .B(n5568), .C(n4935), .Y(n4091) );
AOI21X1TS U5046 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n4959), .B0(n4091),
.Y(n4090) );
OAI21XLTS U5047 ( .A0(n4942), .A1(n4099), .B0(n4090), .Y(n2133) );
AOI211XLTS U5048 ( .A0(n5623), .A1(n5568), .B0(n4939), .C0(n4100), .Y(n4092)
);
AOI211X1TS U5049 ( .A0(n2197), .A1(n5546), .B0(n4916), .C0(n4942), .Y(n4931)
);
AOI21X1TS U5050 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n4959), .B0(n4931),
.Y(n4095) );
OAI21XLTS U5051 ( .A0(n4934), .A1(n4935), .B0(n4095), .Y(n2135) );
INVX2TS U5052 ( .A(n4096), .Y(n4097) );
OAI31X1TS U5053 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(n4098), .A2(n4097),
.B0(n5688), .Y(n1690) );
NAND2X1TS U5054 ( .A(n4929), .B(n4932), .Y(n4933) );
OAI2BB1X1TS U5055 ( .A0N(n4100), .A1N(n4099), .B0(n4980), .Y(n4920) );
INVX2TS U5056 ( .A(n4942), .Y(n4922) );
NAND2X1TS U5057 ( .A(n2197), .B(n4932), .Y(n4101) );
AOI22X1TS U5058 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n4939), .B0(n4922),
.B1(n4101), .Y(n4102) );
AOI22X1TS U5059 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n4939), .B0(n4922),
.B1(n4103), .Y(n4104) );
OAI21XLTS U5060 ( .A0(n4916), .A1(n4935), .B0(n4104), .Y(n2131) );
NAND2X1TS U5061 ( .A(n4922), .B(n4932), .Y(n4105) );
OAI211XLTS U5062 ( .A0(n4986), .A1(n5762), .B0(n4105), .C0(n4920), .Y(n2132)
);
OAI211XLTS U5063 ( .A0(n4986), .A1(n5761), .B0(n4923), .C0(n4105), .Y(n2126)
);
XNOR2X1TS U5064 ( .A(DP_OP_26J208_123_9022_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n4114) );
INVX2TS U5065 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n4688) );
INVX2TS U5066 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n4106) );
NOR2X1TS U5067 ( .A(n4110), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n4111) );
NAND2BX2TS U5068 ( .AN(n4114), .B(n4111), .Y(n5188) );
AND4X1TS U5069 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n4112) );
AND4X1TS U5070 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n4112), .Y(n4113) );
OAI2BB1X1TS U5071 ( .A0N(n4115), .A1N(n4114), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n4684) );
INVX2TS U5072 ( .A(n4684), .Y(n5189) );
AOI22X1TS U5073 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n5612), .B0(n4118), .B1(n5530), .Y(n4120) );
INVX3TS U5074 ( .A(n4990), .Y(n4978) );
NAND4X1TS U5075 ( .A(n5623), .B(n5568), .C(n5546), .D(n4915), .Y(n4123) );
NOR2X2TS U5076 ( .A(n4249), .B(n4123), .Y(n4128) );
INVX2TS U5077 ( .A(n4124), .Y(n1764) );
INVX2TS U5078 ( .A(n4125), .Y(n1762) );
INVX2TS U5079 ( .A(n4126), .Y(n1765) );
INVX2TS U5080 ( .A(n4127), .Y(n1760) );
INVX2TS U5081 ( .A(n4129), .Y(n1763) );
OAI2BB1X1TS U5082 ( .A0N(ack_operation), .A1N(n4469), .B0(n4905), .Y(n4131)
);
NAND2X1TS U5083 ( .A(n4132), .B(n4131), .Y(n4671) );
INVX2TS U5084 ( .A(n4031), .Y(n4679) );
OAI21XLTS U5085 ( .A0(n4672), .A1(FPMULT_P_Sgf[47]), .B0(n4133), .Y(n4134)
);
AOI2BB1XLTS U5086 ( .A0N(n4679), .A1N(FPMULT_zero_flag), .B0(n4134), .Y(
n4135) );
INVX2TS U5087 ( .A(n4136), .Y(n1766) );
NAND3X1TS U5088 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n4137),
.C(n5563), .Y(n4890) );
OAI31X1TS U5089 ( .A0(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .A1(n5557),
.A2(n4892), .B0(n4890), .Y(n4948) );
BUFX3TS U5090 ( .A(n4948), .Y(n4947) );
INVX2TS U5091 ( .A(operation[0]), .Y(n4138) );
OAI32X1TS U5092 ( .A0(n4943), .A1(n4138), .A2(n4458), .B0(n5541), .B1(n4947),
.Y(n2082) );
NOR2X1TS U5093 ( .A(n5708), .B(FPADDSUB_intDX_EWSW[25]), .Y(n4199) );
AOI22X1TS U5094 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n5708), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n4140), .Y(n4144) );
OAI21X1TS U5095 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n5707), .B0(n4141), .Y(
n4200) );
NOR2X1TS U5096 ( .A(n5561), .B(FPADDSUB_intDX_EWSW[30]), .Y(n4147) );
NOR2X1TS U5097 ( .A(n5632), .B(FPADDSUB_intDX_EWSW[29]), .Y(n4145) );
NOR3X1TS U5098 ( .A(n5696), .B(n4145), .C(FPADDSUB_intDY_EWSW[28]), .Y(n4146) );
AOI221X1TS U5099 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n5561), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n5632), .C0(n4146), .Y(n4148) );
NOR2X1TS U5100 ( .A(n5622), .B(FPADDSUB_intDX_EWSW[17]), .Y(n4185) );
NOR2X1TS U5101 ( .A(n5621), .B(FPADDSUB_intDX_EWSW[11]), .Y(n4164) );
AOI21X1TS U5102 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n5674), .B0(n4164), .Y(
n4169) );
OAI2BB1X1TS U5103 ( .A0N(n5689), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n4150) );
OAI22X1TS U5104 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4150), .B0(n5689), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n4161) );
OAI2BB1X1TS U5105 ( .A0N(n5698), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n4151) );
OAI22X1TS U5106 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n4151), .B0(n5698), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n4160) );
OAI21XLTS U5107 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n5611), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n4152) );
OAI2BB2XLTS U5108 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n4152), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n5611), .Y(n4154) );
NAND2BXLTS U5109 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n4153) );
OAI211XLTS U5110 ( .A0(n5615), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n4154), .C0(
n4153), .Y(n4157) );
OAI21XLTS U5111 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n5615), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n4155) );
AOI2BB2XLTS U5112 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n5615), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n4155), .Y(n4156) );
AOI22X1TS U5113 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n5698), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n5572), .Y(n4158) );
OAI32X1TS U5114 ( .A0(n4161), .A1(n4160), .A2(n4159), .B0(n4158), .B1(n4160),
.Y(n4179) );
OA22X1TS U5115 ( .A0(n5609), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n5549), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n4176) );
OAI21XLTS U5116 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n5619), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n4163) );
OAI2BB2XLTS U5117 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n4163), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n5619), .Y(n4175) );
AOI22X1TS U5118 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n5621), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n4165), .Y(n4171) );
AOI21X1TS U5119 ( .A0(n4168), .A1(n4167), .B0(n4178), .Y(n4170) );
OAI2BB2XLTS U5120 ( .B0(n4171), .B1(n4178), .A0N(n4170), .A1N(n4169), .Y(
n4174) );
OAI2BB2XLTS U5121 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n4172), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n5549), .Y(n4173) );
AOI211X1TS U5122 ( .A0(n4176), .A1(n4175), .B0(n4174), .C0(n4173), .Y(n4177)
);
OAI31X1TS U5123 ( .A0(n4180), .A1(n4179), .A2(n4178), .B0(n4177), .Y(n4183)
);
OA22X1TS U5124 ( .A0(n5616), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n5552), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n4196) );
OAI21X1TS U5125 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n5630), .B0(n4187), .Y(
n4191) );
OAI21XLTS U5126 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n5627), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n4184) );
OAI2BB2XLTS U5127 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n4184), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n5627), .Y(n4195) );
AOI22X1TS U5128 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n5622), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n4186), .Y(n4189) );
AOI32X1TS U5129 ( .A0(n5630), .A1(n4187), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n5559), .Y(n4188) );
OAI32X1TS U5130 ( .A0(n4191), .A1(n4190), .A2(n4189), .B0(n4188), .B1(n4190),
.Y(n4194) );
OAI2BB2XLTS U5131 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n4192), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n5552), .Y(n4193) );
AOI211X1TS U5132 ( .A0(n4196), .A1(n4195), .B0(n4194), .C0(n4193), .Y(n4202)
);
NAND4BBX1TS U5133 ( .AN(n4200), .BN(n4199), .C(n4198), .D(n4197), .Y(n4201)
);
AOI32X4TS U5134 ( .A0(n4204), .A1(n4203), .A2(n4202), .B0(n4201), .B1(n4204),
.Y(n5291) );
INVX3TS U5135 ( .A(n4265), .Y(n4306) );
NOR2X4TS U5136 ( .A(n4205), .B(n5291), .Y(n4235) );
BUFX4TS U5137 ( .A(n4205), .Y(n4299) );
BUFX4TS U5138 ( .A(n4299), .Y(n5298) );
AOI22X1TS U5139 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n4255), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n5298), .Y(n4206) );
AOI22X1TS U5140 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n4255), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n5298), .Y(n4207) );
AOI22X1TS U5141 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n4255), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n4205), .Y(n4208) );
INVX2TS U5142 ( .A(n4265), .Y(n4304) );
AOI22X1TS U5143 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n4255), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n5298), .Y(n4209) );
INVX3TS U5144 ( .A(n4990), .Y(n4245) );
INVX2TS U5145 ( .A(n4210), .Y(n1759) );
INVX2TS U5146 ( .A(n4212), .Y(n1761) );
INVX4TS U5147 ( .A(n4255), .Y(n5174) );
BUFX3TS U5148 ( .A(n4265), .Y(n4329) );
AOI22X1TS U5149 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n4329), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n4299), .Y(n4213) );
AOI22X1TS U5150 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n4329), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n4299), .Y(n4214) );
AOI22X1TS U5151 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n4329), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n4299), .Y(n4215) );
AOI22X1TS U5152 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n4329), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n4299), .Y(n4216) );
AOI22X1TS U5153 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n4329), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n4299), .Y(n4217) );
AOI22X1TS U5154 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n4265), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n4299), .Y(n4218) );
AOI22X1TS U5155 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n4329), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n4299), .Y(n4219) );
BUFX4TS U5156 ( .A(n4211), .Y(n4233) );
INVX2TS U5157 ( .A(n4220), .Y(n1753) );
INVX2TS U5158 ( .A(n4221), .Y(n1749) );
INVX2TS U5159 ( .A(n4222), .Y(n1748) );
INVX2TS U5160 ( .A(n4223), .Y(n1751) );
INVX2TS U5161 ( .A(n4224), .Y(n1750) );
INVX2TS U5162 ( .A(n4225), .Y(n1757) );
INVX2TS U5163 ( .A(n4226), .Y(n1745) );
INVX2TS U5164 ( .A(n4227), .Y(n1752) );
INVX2TS U5165 ( .A(n4228), .Y(n1747) );
INVX2TS U5166 ( .A(n4229), .Y(n1746) );
INVX2TS U5167 ( .A(n4230), .Y(n1744) );
INVX2TS U5168 ( .A(n4231), .Y(n1741) );
INVX2TS U5169 ( .A(n4232), .Y(n1742) );
INVX2TS U5170 ( .A(n4234), .Y(n1743) );
INVX2TS U5171 ( .A(n4235), .Y(n4254) );
BUFX4TS U5172 ( .A(n4265), .Y(n4272) );
AOI22X1TS U5173 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n5298), .Y(n4236) );
AOI22X1TS U5174 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n5298), .Y(n4237) );
INVX2TS U5175 ( .A(n4238), .Y(n1738) );
INVX2TS U5176 ( .A(n4239), .Y(n1756) );
INVX2TS U5177 ( .A(n4240), .Y(n1736) );
INVX2TS U5178 ( .A(n4241), .Y(n1737) );
INVX2TS U5179 ( .A(n4242), .Y(n1758) );
INVX2TS U5180 ( .A(n4243), .Y(n1754) );
INVX2TS U5181 ( .A(n4246), .Y(n1755) );
INVX2TS U5182 ( .A(n4247), .Y(n1740) );
INVX2TS U5183 ( .A(n4248), .Y(n1739) );
INVX2TS U5184 ( .A(n4250), .Y(n1735) );
AOI22X1TS U5185 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n5298), .Y(n4251) );
AOI22X1TS U5186 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n5298), .Y(n4252) );
AOI22X1TS U5187 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n5298), .Y(n4253) );
AOI22X1TS U5188 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n4255), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n5298), .Y(n4256) );
AOI22X1TS U5189 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n4255), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n2457), .Y(n4257) );
AOI22X1TS U5190 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n4255), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n5298), .Y(n4258) );
AOI22X1TS U5191 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n4272), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n2457), .Y(n4259) );
AOI22X1TS U5192 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4265), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n2457), .Y(n4260) );
AOI22X1TS U5193 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4329), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n4299), .Y(n4261) );
AOI22X1TS U5194 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n2457), .Y(n4262) );
AOI22X1TS U5195 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n4329), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n4299), .Y(n4263) );
AOI22X1TS U5196 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n2457), .Y(n4264) );
AOI22X1TS U5197 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n4265), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n2457), .Y(n4266) );
AOI22X1TS U5198 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n2457), .Y(n4267) );
AOI22X1TS U5199 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n2457), .Y(n4268) );
AOI22X1TS U5200 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n4299), .Y(n4269) );
AOI22X1TS U5201 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n2457), .Y(n4270) );
AOI22X1TS U5202 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n2457), .Y(n4271) );
AOI22X1TS U5203 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n4272), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n2457), .Y(n4273) );
BUFX3TS U5204 ( .A(n4255), .Y(n4293) );
AOI22X1TS U5205 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n4205), .Y(n4275) );
AOI22X1TS U5206 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n4205), .Y(n4276) );
AOI22X1TS U5207 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n4205), .Y(n4277) );
AOI22X1TS U5208 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n4205), .Y(n4278) );
AOI22X1TS U5209 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n4205), .Y(n4279) );
AOI22X1TS U5210 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n4205), .Y(n4280) );
AOI22X1TS U5211 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n4205), .Y(n4281) );
NOR2X2TS U5212 ( .A(n4908), .B(n4283), .Y(n4284) );
XNOR2X1TS U5213 ( .A(FPSENCOS_d_ff1_operation_out), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n4285) );
XNOR2X1TS U5214 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n4285),
.Y(n4287) );
NOR2BX2TS U5215 ( .AN(n4287), .B(n4341), .Y(n4286) );
BUFX4TS U5216 ( .A(n4286), .Y(n4331) );
INVX2TS U5217 ( .A(n4288), .Y(n1725) );
INVX2TS U5218 ( .A(n4289), .Y(n1724) );
INVX2TS U5219 ( .A(n4290), .Y(n1723) );
AOI22X1TS U5220 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n4205), .Y(n4291) );
AOI22X1TS U5221 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n4205), .Y(n4292) );
AOI22X1TS U5222 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n4293), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n4205), .Y(n4294) );
AOI22X1TS U5223 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n4235), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n4299), .Y(n4295) );
AOI22X1TS U5224 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n4235), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n4299), .Y(n4296) );
AOI22X1TS U5225 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n4235), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n5298), .Y(n4297) );
AOI22X1TS U5226 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n4235), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n2457), .Y(n4298) );
AOI22X1TS U5227 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n4235), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n4299), .Y(n4300) );
AOI22X1TS U5228 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n4235), .B0(n2368), .B1(
n2457), .Y(n4301) );
AOI22X1TS U5229 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n4235), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n5298), .Y(n4302) );
AOI22X1TS U5230 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n4235), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n2457), .Y(n4303) );
AOI22X1TS U5231 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n4255), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n5298), .Y(n4305) );
AOI222X1TS U5232 ( .A0(n4255), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DMP_EXP_EWSW[23]), .B1(n2457), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n4329), .Y(n4307) );
INVX2TS U5233 ( .A(n4307), .Y(n1467) );
XNOR2X1TS U5234 ( .A(n4308), .B(FPSENCOS_d_ff_Xn[31]), .Y(n4311) );
BUFX4TS U5235 ( .A(n4331), .Y(n4326) );
AOI22X1TS U5236 ( .A0(n4350), .A1(cordic_result[31]), .B0(n4326), .B1(n4309),
.Y(n4310) );
INVX2TS U5237 ( .A(n4313), .Y(n1703) );
INVX2TS U5238 ( .A(n4314), .Y(n1727) );
INVX2TS U5239 ( .A(n4316), .Y(n1704) );
INVX2TS U5240 ( .A(n4317), .Y(n1709) );
INVX2TS U5241 ( .A(n4318), .Y(n1700) );
INVX2TS U5242 ( .A(n4319), .Y(n1702) );
INVX2TS U5243 ( .A(n4320), .Y(n1698) );
INVX2TS U5244 ( .A(n4321), .Y(n1699) );
INVX2TS U5245 ( .A(n4322), .Y(n1708) );
INVX2TS U5246 ( .A(n4323), .Y(n1707) );
INVX2TS U5247 ( .A(n4324), .Y(n1705) );
INVX2TS U5248 ( .A(n4325), .Y(n1706) );
INVX2TS U5249 ( .A(n4327), .Y(n1701) );
INVX2TS U5250 ( .A(n4328), .Y(overflow_flag) );
INVX2TS U5251 ( .A(n4330), .Y(n1419) );
INVX2TS U5252 ( .A(n4332), .Y(n1717) );
INVX2TS U5253 ( .A(n4333), .Y(n1728) );
INVX2TS U5254 ( .A(n4334), .Y(n1722) );
INVX2TS U5255 ( .A(n4335), .Y(n1721) );
INVX2TS U5256 ( .A(n4336), .Y(n1714) );
INVX2TS U5257 ( .A(n4337), .Y(n1715) );
INVX2TS U5258 ( .A(n4338), .Y(n1726) );
INVX2TS U5259 ( .A(n4339), .Y(n1712) );
INVX2TS U5260 ( .A(n4340), .Y(n1720) );
INVX2TS U5261 ( .A(n4342), .Y(n1719) );
INVX2TS U5262 ( .A(n4343), .Y(n1713) );
INVX2TS U5263 ( .A(n4344), .Y(n1710) );
INVX2TS U5264 ( .A(n4346), .Y(n1718) );
INVX2TS U5265 ( .A(n4348), .Y(n1716) );
INVX2TS U5266 ( .A(n4351), .Y(n1711) );
AOI2BB2XLTS U5267 ( .B0(n2319), .B1(n5705), .A0N(n5705), .A1N(n2319), .Y(
n4353) );
BUFX4TS U5268 ( .A(n4434), .Y(n5064) );
AOI22X1TS U5269 ( .A0(operation[0]), .A1(n5020), .B0(FPADDSUB_intAS), .B1(
n5064), .Y(n4352) );
INVX4TS U5270 ( .A(n4995), .Y(n4448) );
BUFX4TS U5271 ( .A(n5025), .Y(n5039) );
AOI22X1TS U5272 ( .A0(Data_2[0]), .A1(n5039), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n4999), .Y(n4357) );
BUFX3TS U5273 ( .A(n4385), .Y(n4438) );
AOI22X1TS U5274 ( .A0(n4996), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n4438),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n4356) );
AOI22X1TS U5275 ( .A0(Data_2[2]), .A1(n5039), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n4999), .Y(n4359) );
AOI22X1TS U5276 ( .A0(n4996), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n4358) );
AOI22X1TS U5277 ( .A0(Data_2[4]), .A1(n5039), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n4999), .Y(n4361) );
AOI22X1TS U5278 ( .A0(n4996), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n4360) );
AOI22X1TS U5279 ( .A0(Data_1[31]), .A1(n5039), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n4999), .Y(n4363) );
AOI22X1TS U5280 ( .A0(n4996), .A1(n2345), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n4362) );
AOI22X1TS U5281 ( .A0(Data_2[1]), .A1(n5039), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n4999), .Y(n4365) );
AOI22X1TS U5282 ( .A0(n4996), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n4364) );
AOI22X1TS U5283 ( .A0(Data_1[30]), .A1(n5039), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n4999), .Y(n4367) );
AOI22X1TS U5284 ( .A0(n4996), .A1(FPSENCOS_d_ff2_X[30]), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n4366) );
AOI22X1TS U5285 ( .A0(Data_1[28]), .A1(n5039), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n3535), .Y(n4369) );
AOI22X1TS U5286 ( .A0(n4996), .A1(FPSENCOS_d_ff2_X[28]), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n4368) );
AOI22X1TS U5287 ( .A0(Data_1[26]), .A1(n5039), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n3535), .Y(n4371) );
AOI22X1TS U5288 ( .A0(n4996), .A1(FPSENCOS_d_ff2_X[26]), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n4370) );
AOI22X1TS U5289 ( .A0(Data_1[29]), .A1(n5039), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n4999), .Y(n4373) );
AOI22X1TS U5290 ( .A0(n4996), .A1(FPSENCOS_d_ff2_X[29]), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n4372) );
AOI22X1TS U5291 ( .A0(Data_1[27]), .A1(n5039), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n3535), .Y(n4375) );
AOI22X1TS U5292 ( .A0(n4996), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n4374) );
BUFX4TS U5293 ( .A(n4434), .Y(n5024) );
AOI22X1TS U5294 ( .A0(Data_2[9]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n5024), .Y(n4378) );
BUFX4TS U5295 ( .A(n4442), .Y(n5021) );
AOI22X1TS U5296 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n4377) );
INVX4TS U5297 ( .A(n4995), .Y(n4445) );
AOI22X1TS U5298 ( .A0(Data_2[10]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n5024), .Y(n4380) );
AOI22X1TS U5299 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n4379) );
AOI22X1TS U5300 ( .A0(Data_2[12]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n5024), .Y(n4382) );
AOI22X1TS U5301 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n4381) );
INVX4TS U5302 ( .A(n4995), .Y(n4456) );
BUFX4TS U5303 ( .A(n5025), .Y(n5036) );
AOI22X1TS U5304 ( .A0(Data_1[21]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n4999), .Y(n4384) );
BUFX3TS U5305 ( .A(n4442), .Y(n4439) );
AOI22X1TS U5306 ( .A0(n4439), .A1(n2348), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n4383) );
BUFX4TS U5307 ( .A(n5025), .Y(n5065) );
AOI22X1TS U5308 ( .A0(Data_1[8]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n4434), .Y(n4387) );
AOI22X1TS U5309 ( .A0(n4442), .A1(FPSENCOS_d_ff2_X[8]), .B0(n5033), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n4386) );
AOI22X1TS U5310 ( .A0(Data_1[9]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n4434), .Y(n4389) );
BUFX3TS U5311 ( .A(n4385), .Y(n4435) );
AOI22X1TS U5312 ( .A0(n4442), .A1(n2346), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n4388) );
AOI22X1TS U5313 ( .A0(Data_1[12]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n4434), .Y(n4391) );
AOI22X1TS U5314 ( .A0(n4442), .A1(n2354), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n4390) );
AOI22X1TS U5315 ( .A0(Data_1[2]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n5064), .Y(n4393) );
AOI22X1TS U5316 ( .A0(n4442), .A1(n2353), .B0(n5033), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n4392) );
AOI22X1TS U5317 ( .A0(Data_1[1]), .A1(n5020), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n5024), .Y(n4395) );
AOI22X1TS U5318 ( .A0(n4442), .A1(n2352), .B0(n5033), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n4394) );
AOI22X1TS U5319 ( .A0(Data_1[19]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n3535), .Y(n4397) );
AOI22X1TS U5320 ( .A0(n4439), .A1(n2363), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n4396) );
AOI22X1TS U5321 ( .A0(Data_1[17]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n5024), .Y(n4399) );
AOI22X1TS U5322 ( .A0(n4439), .A1(n2361), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n4398) );
AOI22X1TS U5323 ( .A0(Data_1[18]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n3535), .Y(n4401) );
AOI22X1TS U5324 ( .A0(n4439), .A1(n2349), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n4400) );
AOI22X1TS U5325 ( .A0(Data_1[15]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n4434), .Y(n4403) );
AOI22X1TS U5326 ( .A0(n4439), .A1(n2350), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n4402) );
AOI22X1TS U5327 ( .A0(Data_1[11]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n4434), .Y(n4405) );
AOI22X1TS U5328 ( .A0(n4442), .A1(FPSENCOS_d_ff2_X[11]), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n4404) );
AOI22X1TS U5329 ( .A0(Data_1[20]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n3535), .Y(n4407) );
AOI22X1TS U5330 ( .A0(n4439), .A1(n2362), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n4406) );
AOI22X1TS U5331 ( .A0(Data_1[13]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n4434), .Y(n4409) );
AOI22X1TS U5332 ( .A0(n4439), .A1(n2360), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n4408) );
AOI22X1TS U5333 ( .A0(Data_1[14]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n4434), .Y(n4411) );
AOI22X1TS U5334 ( .A0(n4439), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n4410) );
AOI22X1TS U5335 ( .A0(Data_1[22]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n3535), .Y(n4413) );
AOI22X1TS U5336 ( .A0(n4439), .A1(n2351), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n4412) );
AOI22X1TS U5337 ( .A0(Data_2[8]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n4999), .Y(n4415) );
AOI22X1TS U5338 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n4414) );
AOI22X1TS U5339 ( .A0(Data_1[3]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n5064), .Y(n4417) );
AOI22X1TS U5340 ( .A0(n4442), .A1(FPSENCOS_d_ff2_X[3]), .B0(n5033), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n4416) );
AOI22X1TS U5341 ( .A0(Data_1[24]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n3535), .Y(n4419) );
AOI22X1TS U5342 ( .A0(n4439), .A1(FPSENCOS_d_ff2_X[24]), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n4418) );
AOI22X1TS U5343 ( .A0(n5036), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n5064), .Y(n4421) );
AOI22X1TS U5344 ( .A0(n4442), .A1(n2347), .B0(FPSENCOS_d_ff2_Z[0]), .B1(
n5033), .Y(n4420) );
AOI22X1TS U5345 ( .A0(Data_1[25]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n3535), .Y(n4423) );
AOI22X1TS U5346 ( .A0(n4439), .A1(FPSENCOS_d_ff2_X[25]), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n4422) );
AOI22X1TS U5347 ( .A0(Data_1[10]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n4434), .Y(n4425) );
AOI22X1TS U5348 ( .A0(n5021), .A1(n2355), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n4424) );
AOI22X1TS U5349 ( .A0(Data_1[6]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n4434), .Y(n4427) );
AOI22X1TS U5350 ( .A0(n5066), .A1(n2356), .B0(n5033), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n4426) );
AOI22X1TS U5351 ( .A0(Data_1[4]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n5024), .Y(n4429) );
AOI22X1TS U5352 ( .A0(n5066), .A1(FPSENCOS_d_ff2_X[4]), .B0(n5033), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n4428) );
AOI22X1TS U5353 ( .A0(Data_1[5]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n4434), .Y(n4431) );
AOI22X1TS U5354 ( .A0(n5021), .A1(n2357), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n4430) );
AOI22X1TS U5355 ( .A0(Data_1[7]), .A1(n5065), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n4434), .Y(n4433) );
AOI22X1TS U5356 ( .A0(n5066), .A1(n2358), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n4432) );
AOI22X1TS U5357 ( .A0(Data_1[16]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n4434), .Y(n4437) );
AOI22X1TS U5358 ( .A0(n4439), .A1(n2359), .B0(n4435), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n4436) );
AOI22X1TS U5359 ( .A0(Data_1[23]), .A1(n5036), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n3535), .Y(n4441) );
AOI22X1TS U5360 ( .A0(n4439), .A1(FPSENCOS_d_ff2_X[23]), .B0(n4438), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n4440) );
AOI22X1TS U5361 ( .A0(Data_2[26]), .A1(n5025), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n5064), .Y(n4444) );
BUFX4TS U5362 ( .A(n4442), .Y(n5066) );
AOI22X1TS U5363 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n4443) );
AOI22X1TS U5364 ( .A0(Data_2[25]), .A1(n5025), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n5064), .Y(n4447) );
AOI22X1TS U5365 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n4446) );
AOI22X1TS U5366 ( .A0(Data_2[21]), .A1(n5039), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n5064), .Y(n4450) );
AOI22X1TS U5367 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n4449) );
AOI22X1TS U5368 ( .A0(Data_2[24]), .A1(n5025), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n5064), .Y(n4452) );
AOI22X1TS U5369 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n4451) );
AOI22X1TS U5370 ( .A0(Data_2[23]), .A1(n5025), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n5064), .Y(n4455) );
AOI22X1TS U5371 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n4453),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n4454) );
BUFX4TS U5372 ( .A(n4457), .Y(n4491) );
AOI22X1TS U5373 ( .A0(cordic_result[31]), .A1(n4903), .B0(n4902), .B1(
mult_result[31]), .Y(n4459) );
AOI22X1TS U5374 ( .A0(n4468), .A1(cordic_result[2]), .B0(n4469), .B1(
mult_result[2]), .Y(n4460) );
AOI22X1TS U5375 ( .A0(n4468), .A1(cordic_result[5]), .B0(n4469), .B1(
mult_result[5]), .Y(n4461) );
AOI22X1TS U5376 ( .A0(n4468), .A1(cordic_result[4]), .B0(n4469), .B1(
mult_result[4]), .Y(n4462) );
AOI22X1TS U5377 ( .A0(n4468), .A1(cordic_result[3]), .B0(n4469), .B1(
mult_result[3]), .Y(n4463) );
AOI22X1TS U5378 ( .A0(n4468), .A1(cordic_result[1]), .B0(n4469), .B1(
mult_result[1]), .Y(n4464) );
AOI22X1TS U5379 ( .A0(n4468), .A1(cordic_result[0]), .B0(n4469), .B1(
mult_result[0]), .Y(n4465) );
AOI22X1TS U5380 ( .A0(cordic_result[27]), .A1(n4903), .B0(n4902), .B1(
mult_result[27]), .Y(n4466) );
AOI22X1TS U5381 ( .A0(cordic_result[26]), .A1(n4903), .B0(n4902), .B1(
mult_result[26]), .Y(n4467) );
AOI22X1TS U5382 ( .A0(cordic_result[17]), .A1(n4487), .B0(n4486), .B1(
mult_result[17]), .Y(n4470) );
AOI22X1TS U5383 ( .A0(cordic_result[21]), .A1(n4903), .B0(n4902), .B1(
mult_result[21]), .Y(n4471) );
AOI22X1TS U5384 ( .A0(cordic_result[16]), .A1(n4487), .B0(n4486), .B1(
mult_result[16]), .Y(n4472) );
AOI22X1TS U5385 ( .A0(cordic_result[15]), .A1(n4487), .B0(n4486), .B1(
mult_result[15]), .Y(n4473) );
AOI22X1TS U5386 ( .A0(cordic_result[14]), .A1(n4487), .B0(n4486), .B1(
mult_result[14]), .Y(n4474) );
AOI22X1TS U5387 ( .A0(cordic_result[13]), .A1(n4487), .B0(n4486), .B1(
mult_result[13]), .Y(n4475) );
AOI22X1TS U5388 ( .A0(cordic_result[12]), .A1(n4487), .B0(n4486), .B1(
mult_result[12]), .Y(n4476) );
AOI22X1TS U5389 ( .A0(cordic_result[11]), .A1(n4487), .B0(n4486), .B1(
mult_result[11]), .Y(n4477) );
AOI22X1TS U5390 ( .A0(cordic_result[10]), .A1(n4487), .B0(n4486), .B1(
mult_result[10]), .Y(n4478) );
AOI22X1TS U5391 ( .A0(cordic_result[7]), .A1(n4487), .B0(n4486), .B1(
mult_result[7]), .Y(n4479) );
AOI22X1TS U5392 ( .A0(cordic_result[28]), .A1(n4903), .B0(n4902), .B1(
mult_result[28]), .Y(n4480) );
AOI22X1TS U5393 ( .A0(cordic_result[8]), .A1(n4487), .B0(n4486), .B1(
mult_result[8]), .Y(n4481) );
AOI22X1TS U5394 ( .A0(cordic_result[18]), .A1(n4487), .B0(n4486), .B1(
mult_result[18]), .Y(n4482) );
AOI22X1TS U5395 ( .A0(cordic_result[19]), .A1(n4903), .B0(n4486), .B1(
mult_result[19]), .Y(n4483) );
AOI22X1TS U5396 ( .A0(cordic_result[20]), .A1(n4903), .B0(n4902), .B1(
mult_result[20]), .Y(n4484) );
AOI22X1TS U5397 ( .A0(cordic_result[6]), .A1(n4487), .B0(n4486), .B1(
mult_result[6]), .Y(n4485) );
AOI22X1TS U5398 ( .A0(cordic_result[9]), .A1(n4487), .B0(n4486), .B1(
mult_result[9]), .Y(n4488) );
AOI22X1TS U5399 ( .A0(cordic_result[22]), .A1(n4903), .B0(n4902), .B1(
mult_result[22]), .Y(n4489) );
AOI22X1TS U5400 ( .A0(cordic_result[24]), .A1(n4903), .B0(n4902), .B1(
mult_result[24]), .Y(n4490) );
OR4X2TS U5401 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .D(
n4495), .Y(n4530) );
OAI22X1TS U5402 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n4506), .B0(n5625),
.B1(n4530), .Y(n4538) );
AOI32X1TS U5403 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n5533), .A2(n5558),
.B0(FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n5533), .Y(n4492) );
AOI211X1TS U5404 ( .A0(n5535), .A1(n4492), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C0(n4496), .Y(n4493) );
AOI21X1TS U5405 ( .A0(n5585), .A1(n5538), .B0(n4494), .Y(n4503) );
NAND2X1TS U5406 ( .A(n5560), .B(n5626), .Y(n4539) );
INVX2TS U5407 ( .A(n4496), .Y(n4522) );
NAND3X2TS U5408 ( .A(n4522), .B(n5555), .C(n5535), .Y(n4519) );
OAI22X1TS U5409 ( .A0(n5555), .A1(n4496), .B0(n4519), .B1(n5533), .Y(n4497)
);
BUFX4TS U5410 ( .A(n4552), .Y(n4910) );
AOI32X1TS U5411 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n5045), .A2(
n4910), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n4569), .Y(n4499)
);
NAND2X1TS U5412 ( .A(n4910), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n4500)
);
NOR2X1TS U5413 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n4516) );
NAND3XLTS U5414 ( .A(n5543), .B(n5529), .C(n5597), .Y(n4504) );
NOR2X2TS U5415 ( .A(n5636), .B(n4502), .Y(n4542) );
AOI211X1TS U5416 ( .A0(n4505), .A1(n4504), .B0(n4542), .C0(n4503), .Y(n4507)
);
AOI31X1TS U5417 ( .A0(n4510), .A1(n4516), .A2(FPADDSUB_Raw_mant_NRM_SWR[1]),
.B0(n4509), .Y(n4513) );
NAND2X1TS U5418 ( .A(n4910), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n4512)
);
AOI22X1TS U5419 ( .A0(n4532), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n4518),
.B1(n4517), .Y(n4520) );
AOI32X1TS U5420 ( .A0(n5558), .A1(n4520), .A2(n5697), .B0(n4519), .B1(n4520),
.Y(n4521) );
AOI211X1TS U5421 ( .A0(n4522), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n4541),
.C0(n4521), .Y(n4526) );
NAND2X1TS U5422 ( .A(n4910), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n4523)
);
AOI32X1TS U5423 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n5045), .A2(
n4910), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n4569), .Y(n4525)
);
INVX2TS U5424 ( .A(n4611), .Y(n4527) );
AOI222X4TS U5425 ( .A0(n5295), .A1(FPADDSUB_DmP_mant_SHT1_SW[22]), .B0(n5049), .B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .C0(FPADDSUB_Raw_mant_NRM_SWR[24]), .C1(
n4527), .Y(n4647) );
OAI31X1TS U5426 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n5529), .A2(n4530),
.B0(n4529), .Y(n4531) );
AOI211X1TS U5427 ( .A0(n4532), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n4542),
.C0(n4531), .Y(n4536) );
AOI31X1TS U5428 ( .A0(n4536), .A1(n4535), .A2(n4534), .B0(n4910), .Y(n4683)
);
NAND2X1TS U5429 ( .A(n4537), .B(n5562), .Y(n4547) );
INVX2TS U5430 ( .A(n4538), .Y(n4546) );
AOI31XLTS U5431 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n5543), .A2(n5529),
.B0(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n4540) );
AOI211X1TS U5432 ( .A0(n4544), .A1(n4543), .B0(n4542), .C0(n4541), .Y(n4545)
);
AOI22X1TS U5433 ( .A0(n4569), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n4631),
.B1(n4644), .Y(n4548) );
AOI222X4TS U5434 ( .A0(n5295), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n4527), .C0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .C1(n4623), .Y(n4564) );
INVX4TS U5435 ( .A(n4549), .Y(n4646) );
AOI22X1TS U5436 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[21]), .A1(n5049), .B0(
FPADDSUB_DmP_mant_SHT1_SW[2]), .B1(n4552), .Y(n4553) );
OAI21X2TS U5437 ( .A0(n5535), .A1(n4611), .B0(n4553), .Y(n4589) );
AOI22X1TS U5438 ( .A0(n4569), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2310),
.B1(n4589), .Y(n4557) );
AOI22X1TS U5439 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[2]), .A1(n2298), .B0(
FPADDSUB_DmP_mant_SHT1_SW[0]), .B1(n5295), .Y(n4555) );
AOI222X4TS U5440 ( .A0(n5295), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n2298), .C0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C1(n4623), .Y(n4598) );
INVX2TS U5441 ( .A(n4598), .Y(n4560) );
AOI22X1TS U5442 ( .A0(n4554), .A1(n5050), .B0(n2312), .B1(n4560), .Y(n4556)
);
AOI22X1TS U5443 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n5049), .B0(n4527),
.B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n5054) );
INVX2TS U5444 ( .A(n4564), .Y(n5051) );
AOI22X1TS U5445 ( .A0(n4569), .A1(FPADDSUB_Data_array_SWR[1]), .B0(n2310),
.B1(n5051), .Y(n4559) );
AOI22X1TS U5446 ( .A0(n4631), .A1(n5050), .B0(n2312), .B1(n4589), .Y(n4558)
);
AOI22X1TS U5447 ( .A0(n4569), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2310),
.B1(n4560), .Y(n4563) );
AOI22X1TS U5448 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n5049), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n4552), .Y(n4561) );
OAI21X2TS U5449 ( .A0(n5534), .A1(n4611), .B0(n4561), .Y(n4595) );
AOI22X1TS U5450 ( .A0(n4631), .A1(n4589), .B0(n2312), .B1(n4595), .Y(n4562)
);
AOI222X4TS U5451 ( .A0(n5295), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n4527), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n4623), .Y(n4582) );
AOI222X4TS U5452 ( .A0(n4552), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[11]), .B1(n2298), .C0(
FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n4623), .Y(n4587) );
INVX2TS U5453 ( .A(n4587), .Y(n4579) );
AOI22X1TS U5454 ( .A0(n4569), .A1(n2405), .B0(n2311), .B1(n4579), .Y(n4568)
);
AOI22X1TS U5455 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n5049), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n4552), .Y(n4565) );
OAI21X2TS U5456 ( .A0(n5584), .A1(n4611), .B0(n4565), .Y(n4584) );
AOI22X1TS U5457 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n5049), .B0(
FPADDSUB_DmP_mant_SHT1_SW[10]), .B1(n4552), .Y(n4566) );
OAI21X2TS U5458 ( .A0(n5562), .A1(n4611), .B0(n4566), .Y(n4619) );
AOI22X1TS U5459 ( .A0(n4631), .A1(n4584), .B0(n2313), .B1(n4619), .Y(n4567)
);
BUFX4TS U5460 ( .A(n4569), .Y(n5048) );
AOI222X4TS U5461 ( .A0(n4552), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .B1(n4623), .C0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .C1(n2298), .Y(n4622) );
INVX2TS U5462 ( .A(n4622), .Y(n4583) );
AOI22X1TS U5463 ( .A0(n5048), .A1(n2404), .B0(n2311), .B1(n4583), .Y(n4572)
);
AOI22X1TS U5464 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n5049), .B0(
FPADDSUB_DmP_mant_SHT1_SW[12]), .B1(n4552), .Y(n4570) );
OAI21X2TS U5465 ( .A0(n5636), .A1(n4611), .B0(n4570), .Y(n4617) );
AOI22X1TS U5466 ( .A0(n4631), .A1(n4619), .B0(n2313), .B1(n4617), .Y(n4571)
);
AOI222X4TS U5467 ( .A0(n4552), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n2298), .C0(
FPADDSUB_Raw_mant_NRM_SWR[18]), .C1(n4623), .Y(n4588) );
INVX2TS U5468 ( .A(n4582), .Y(n4576) );
AOI22X1TS U5469 ( .A0(n4569), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2310),
.B1(n4576), .Y(n4575) );
AOI22X1TS U5470 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n5049), .B0(
FPADDSUB_DmP_mant_SHT1_SW[6]), .B1(n4552), .Y(n4573) );
OAI21X2TS U5471 ( .A0(n5531), .A1(n4611), .B0(n4573), .Y(n4594) );
AOI22X1TS U5472 ( .A0(n4631), .A1(n4594), .B0(n2312), .B1(n4584), .Y(n4574)
);
AOI22X1TS U5473 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n2310),
.B1(n4594), .Y(n4578) );
AOI22X1TS U5474 ( .A0(n4554), .A1(n4595), .B0(n2312), .B1(n4576), .Y(n4577)
);
AOI22X1TS U5475 ( .A0(n4569), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2310),
.B1(n4584), .Y(n4581) );
AOI22X1TS U5476 ( .A0(n4554), .A1(n4594), .B0(n2312), .B1(n4579), .Y(n4580)
);
AOI22X1TS U5477 ( .A0(n4569), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n2310),
.B1(n4619), .Y(n4586) );
AOI22X1TS U5478 ( .A0(n4554), .A1(n4584), .B0(n2312), .B1(n4583), .Y(n4585)
);
AOI22X1TS U5479 ( .A0(n4569), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2310),
.B1(n4595), .Y(n4591) );
INVX2TS U5480 ( .A(n4588), .Y(n4592) );
AOI22X1TS U5481 ( .A0(n4554), .A1(n4589), .B0(n2312), .B1(n4592), .Y(n4590)
);
AOI22X1TS U5482 ( .A0(n4569), .A1(n2378), .B0(n2310), .B1(n4592), .Y(n4597)
);
AOI22X1TS U5483 ( .A0(n4631), .A1(n4595), .B0(n2312), .B1(n4594), .Y(n4596)
);
AOI222X4TS U5484 ( .A0(n5295), .A1(FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[4]), .B1(n4623), .C0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .C1(n4527), .Y(n4624) );
AOI222X4TS U5485 ( .A0(n5295), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n4623), .C0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .C1(n4527), .Y(n4649) );
INVX2TS U5486 ( .A(n4649), .Y(n4603) );
AOI22X1TS U5487 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n2311),
.B1(n4603), .Y(n4601) );
AOI22X1TS U5488 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[22]), .A1(n2298), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n2456), .Y(n4599) );
INVX2TS U5489 ( .A(n4647), .Y(n4641) );
AOI22X1TS U5490 ( .A0(n4631), .A1(n4640), .B0(n2313), .B1(n4641), .Y(n4600)
);
AOI22X1TS U5491 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2311),
.B1(n4640), .Y(n4605) );
AOI22X1TS U5492 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[20]), .A1(n2298), .B0(
FPADDSUB_DmP_mant_SHT1_SW[18]), .B1(n2456), .Y(n4602) );
AOI22X1TS U5493 ( .A0(n4554), .A1(n2383), .B0(n2313), .B1(n4603), .Y(n4604)
);
AOI222X4TS U5494 ( .A0(n4552), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n4623), .C0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n2298), .Y(n4614) );
AOI22X1TS U5495 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n5049), .B0(
FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(n4552), .Y(n4606) );
OAI21X2TS U5496 ( .A0(n5529), .A1(n4611), .B0(n4606), .Y(n4636) );
AOI22X1TS U5497 ( .A0(n5048), .A1(n2407), .B0(n2311), .B1(n4636), .Y(n4608)
);
AOI222X4TS U5498 ( .A0(n5295), .A1(FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[8]), .B1(n5049), .C0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .C1(n4527), .Y(n4639) );
INVX2TS U5499 ( .A(n4639), .Y(n4609) );
AOI22X1TS U5500 ( .A0(n4554), .A1(n4617), .B0(n2313), .B1(n4609), .Y(n4607)
);
AOI22X1TS U5501 ( .A0(n5048), .A1(n2406), .B0(n2311), .B1(n4609), .Y(n4613)
);
AOI22X1TS U5502 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n5049), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n4552), .Y(n4610) );
OAI21X2TS U5503 ( .A0(n5625), .A1(n4611), .B0(n4610), .Y(n4634) );
AOI22X1TS U5504 ( .A0(n4631), .A1(n4636), .B0(n2313), .B1(n4634), .Y(n4612)
);
INVX2TS U5505 ( .A(n4614), .Y(n4618) );
AOI22X1TS U5506 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2310),
.B1(n4618), .Y(n4616) );
AOI22X1TS U5507 ( .A0(n4631), .A1(n4617), .B0(n2312), .B1(n4636), .Y(n4615)
);
AOI22X1TS U5508 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2310),
.B1(n4617), .Y(n4621) );
AOI22X1TS U5509 ( .A0(n4554), .A1(n4619), .B0(n2312), .B1(n4618), .Y(n4620)
);
AOI222X4TS U5510 ( .A0(n5295), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[6]), .B1(n4623), .C0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .C1(n4527), .Y(n4630) );
AOI22X1TS U5511 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n2311),
.B1(n2383), .Y(n4626) );
INVX2TS U5512 ( .A(n4624), .Y(n4627) );
AOI22X1TS U5513 ( .A0(n4554), .A1(n4634), .B0(n2313), .B1(n4627), .Y(n4625)
);
AOI22X1TS U5514 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2311),
.B1(n4627), .Y(n4629) );
AOI22X1TS U5515 ( .A0(n4631), .A1(n2383), .B0(n2313), .B1(n4640), .Y(n4628)
);
INVX2TS U5516 ( .A(n4630), .Y(n4635) );
AOI22X1TS U5517 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2311),
.B1(n4635), .Y(n4633) );
AOI22X1TS U5518 ( .A0(n4631), .A1(n4634), .B0(n2313), .B1(n2383), .Y(n4632)
);
AOI22X1TS U5519 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2311),
.B1(n4634), .Y(n4638) );
AOI22X1TS U5520 ( .A0(n4554), .A1(n4636), .B0(n2313), .B1(n4635), .Y(n4637)
);
AOI22X1TS U5521 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n4554),
.B1(n4640), .Y(n4643) );
AOI22X1TS U5522 ( .A0(n2311), .A1(n4641), .B0(n2313), .B1(n4644), .Y(n4642)
);
AOI21X1TS U5523 ( .A0(n4645), .A1(n4644), .B0(n4527), .Y(n5047) );
OAI22X1TS U5524 ( .A0(n4649), .A1(n4648), .B0(n4647), .B1(n4646), .Y(n4650)
);
AOI21X1TS U5525 ( .A0(n5048), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n4650),
.Y(n4651) );
NAND2X1TS U5526 ( .A(n4896), .B(n4912), .Y(n4886) );
NOR2X2TS U5527 ( .A(n2381), .B(n4886), .Y(n4919) );
OAI21XLTS U5528 ( .A0(n4919), .A1(n5705), .B0(FPSENCOS_cont_var_out[1]), .Y(
n4653) );
INVX4TS U5529 ( .A(n2444), .Y(n4674) );
MX2X1TS U5530 ( .A(Data_1[0]), .B(n2389), .S0(n4674), .Y(n1659) );
NOR3BX1TS U5531 ( .AN(n2367), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n4654) );
XOR2X1TS U5532 ( .A(n4031), .B(n4654), .Y(DP_OP_234J208_126_8543_n15) );
OR2X2TS U5533 ( .A(FPMULT_FSM_selector_B[1]), .B(n5633), .Y(n4661) );
OAI2BB1X1TS U5534 ( .A0N(n2365), .A1N(n5637), .B0(n4661), .Y(n4655) );
XOR2X1TS U5535 ( .A(n4031), .B(n4655), .Y(DP_OP_234J208_126_8543_n16) );
OAI2BB1X1TS U5536 ( .A0N(n2364), .A1N(n5637), .B0(n4661), .Y(n4656) );
XOR2X1TS U5537 ( .A(n4031), .B(n4656), .Y(DP_OP_234J208_126_8543_n17) );
OAI2BB1X1TS U5538 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5637), .B0(n4661), .Y(
n4657) );
XOR2X1TS U5539 ( .A(n4031), .B(n4657), .Y(DP_OP_234J208_126_8543_n18) );
OAI2BB1X1TS U5540 ( .A0N(n2339), .A1N(n5637), .B0(n4661), .Y(n4658) );
XOR2X1TS U5541 ( .A(n4031), .B(n4658), .Y(DP_OP_234J208_126_8543_n19) );
OAI2BB1X1TS U5542 ( .A0N(n2340), .A1N(n5637), .B0(n4661), .Y(n4659) );
XOR2X1TS U5543 ( .A(n4031), .B(n4659), .Y(DP_OP_234J208_126_8543_n20) );
OAI2BB1X1TS U5544 ( .A0N(FPMULT_Op_MY[24]), .A1N(n5637), .B0(n4661), .Y(
n4660) );
XOR2X1TS U5545 ( .A(n4031), .B(n4660), .Y(DP_OP_234J208_126_8543_n21) );
NOR2XLTS U5546 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n4662) );
XOR2X1TS U5547 ( .A(n4031), .B(n4663), .Y(DP_OP_234J208_126_8543_n22) );
NOR2BX1TS U5548 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4664) );
XOR2X1TS U5549 ( .A(n5553), .B(n4664), .Y(DP_OP_26J208_123_9022_n14) );
NOR2BX1TS U5550 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4665) );
XOR2X1TS U5551 ( .A(n5553), .B(n4665), .Y(DP_OP_26J208_123_9022_n15) );
NOR2BX1TS U5552 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4666) );
XOR2X1TS U5553 ( .A(n5553), .B(n4666), .Y(DP_OP_26J208_123_9022_n16) );
NOR2BX1TS U5554 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4667) );
XOR2X1TS U5555 ( .A(n5553), .B(n4667), .Y(DP_OP_26J208_123_9022_n17) );
OR2X1TS U5556 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n4668) );
XOR2X1TS U5557 ( .A(n5553), .B(n4668), .Y(DP_OP_26J208_123_9022_n18) );
NOR4X1TS U5558 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n5554), .C(n5618),
.D(n4669), .Y(n4670) );
BUFX3TS U5559 ( .A(n4670), .Y(n5152) );
MX2X1TS U5560 ( .A(Data_1[11]), .B(FPMULT_Op_MX[11]), .S0(n4674), .Y(n1670)
);
MX2X1TS U5561 ( .A(Data_1[10]), .B(FPMULT_Op_MX[10]), .S0(n4674), .Y(n1669)
);
MX2X1TS U5562 ( .A(Data_1[9]), .B(FPMULT_Op_MX[9]), .S0(n4674), .Y(n1668) );
MX2X1TS U5563 ( .A(Data_1[8]), .B(FPMULT_Op_MX[8]), .S0(n4674), .Y(n1667) );
MX2X1TS U5564 ( .A(Data_1[7]), .B(FPMULT_Op_MX[7]), .S0(n4674), .Y(n1666) );
MX2X1TS U5565 ( .A(Data_1[6]), .B(FPMULT_Op_MX[6]), .S0(n4674), .Y(n1665) );
MX2X1TS U5566 ( .A(Data_1[5]), .B(FPMULT_Op_MX[5]), .S0(n4674), .Y(n1664) );
MX2X1TS U5567 ( .A(Data_1[4]), .B(FPMULT_Op_MX[4]), .S0(n4674), .Y(n1663) );
MX2X1TS U5568 ( .A(Data_1[3]), .B(FPMULT_Op_MX[3]), .S0(n4674), .Y(n1662) );
MX2X1TS U5569 ( .A(Data_1[2]), .B(FPMULT_Op_MX[2]), .S0(n4674), .Y(n1661) );
MX2X1TS U5570 ( .A(Data_1[1]), .B(FPMULT_Op_MX[1]), .S0(n4674), .Y(n1660) );
MX2X1TS U5571 ( .A(Data_1[22]), .B(FPMULT_Op_MX[22]), .S0(n4674), .Y(n1681)
);
INVX4TS U5572 ( .A(n2444), .Y(n4675) );
MX2X1TS U5573 ( .A(Data_1[21]), .B(FPMULT_Op_MX[21]), .S0(n4675), .Y(n1680)
);
MX2X1TS U5574 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n4675), .Y(n1679)
);
MX2X1TS U5575 ( .A(Data_1[19]), .B(FPMULT_Op_MX[19]), .S0(n4675), .Y(n1678)
);
MX2X1TS U5576 ( .A(Data_1[18]), .B(FPMULT_Op_MX[18]), .S0(n4675), .Y(n1677)
);
MX2X1TS U5577 ( .A(Data_1[17]), .B(FPMULT_Op_MX[17]), .S0(n4675), .Y(n1676)
);
MX2X1TS U5578 ( .A(Data_1[16]), .B(FPMULT_Op_MX[16]), .S0(n4675), .Y(n1675)
);
MX2X1TS U5579 ( .A(Data_1[15]), .B(FPMULT_Op_MX[15]), .S0(n4675), .Y(n1674)
);
MX2X1TS U5580 ( .A(Data_1[14]), .B(FPMULT_Op_MX[14]), .S0(n4675), .Y(n1673)
);
MX2X1TS U5581 ( .A(Data_1[13]), .B(FPMULT_Op_MX[13]), .S0(n4675), .Y(n1672)
);
MX2X1TS U5582 ( .A(Data_1[12]), .B(n2200), .S0(n4675), .Y(n1671) );
MX2X1TS U5583 ( .A(Data_2[11]), .B(n2435), .S0(n4675), .Y(n1638) );
MX2X1TS U5584 ( .A(Data_2[10]), .B(FPMULT_Op_MY[10]), .S0(n4675), .Y(n1637)
);
MX2X1TS U5585 ( .A(Data_2[9]), .B(n2437), .S0(n4675), .Y(n1636) );
MX2X1TS U5586 ( .A(Data_2[8]), .B(FPMULT_Op_MY[8]), .S0(n4676), .Y(n1635) );
MX2X1TS U5587 ( .A(Data_2[7]), .B(n2302), .S0(n4676), .Y(n1634) );
MX2X1TS U5588 ( .A(Data_2[6]), .B(FPMULT_Op_MY[6]), .S0(n4676), .Y(n1633) );
MX2X1TS U5589 ( .A(Data_2[5]), .B(n2301), .S0(n4676), .Y(n1632) );
MX2X1TS U5590 ( .A(Data_2[4]), .B(FPMULT_Op_MY[4]), .S0(n4676), .Y(n1631) );
MX2X1TS U5591 ( .A(Data_2[3]), .B(n2385), .S0(n4676), .Y(n1630) );
MX2X1TS U5592 ( .A(Data_2[2]), .B(FPMULT_Op_MY[2]), .S0(n4676), .Y(n1629) );
MX2X1TS U5593 ( .A(Data_2[1]), .B(n2297), .S0(n4676), .Y(n1628) );
MX2X1TS U5594 ( .A(Data_2[0]), .B(FPMULT_Op_MY[0]), .S0(n4676), .Y(n1627) );
MX2X1TS U5595 ( .A(Data_2[21]), .B(FPMULT_Op_MY[21]), .S0(n4676), .Y(n1648)
);
MX2X1TS U5596 ( .A(Data_2[20]), .B(FPMULT_Op_MY[20]), .S0(n4676), .Y(n1647)
);
MX2X1TS U5597 ( .A(Data_2[19]), .B(n2440), .S0(n4676), .Y(n1646) );
INVX4TS U5598 ( .A(n2444), .Y(n4678) );
MX2X1TS U5599 ( .A(Data_2[18]), .B(FPMULT_Op_MY[18]), .S0(n4678), .Y(n1645)
);
MX2X1TS U5600 ( .A(Data_2[17]), .B(FPMULT_Op_MY[17]), .S0(n4678), .Y(n1644)
);
MX2X1TS U5601 ( .A(Data_2[16]), .B(FPMULT_Op_MY[16]), .S0(n4678), .Y(n1643)
);
MX2X1TS U5602 ( .A(Data_2[15]), .B(n2395), .S0(n4678), .Y(n1642) );
MX2X1TS U5603 ( .A(Data_2[14]), .B(FPMULT_Op_MY[14]), .S0(n4678), .Y(n1641)
);
MX2X1TS U5604 ( .A(Data_2[13]), .B(n2382), .S0(n4678), .Y(n1640) );
MX2X1TS U5605 ( .A(Data_2[12]), .B(FPMULT_Op_MY[12]), .S0(n4678), .Y(n1639)
);
NAND2X1TS U5606 ( .A(n5092), .B(n5709), .Y(n1691) );
MX2X1TS U5607 ( .A(Data_1[30]), .B(n2374), .S0(n4678), .Y(n1689) );
MX2X1TS U5608 ( .A(n2374), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
MX2X1TS U5609 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n4678), .Y(n1688)
);
MX2X1TS U5610 ( .A(FPMULT_Exp_module_Data_S[6]), .B(n2342), .S0(n4677), .Y(
n1543) );
MX2X1TS U5611 ( .A(FPMULT_Op_MX[29]), .B(n2342), .S0(FPMULT_FSM_selector_A),
.Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U5612 ( .A(Data_1[28]), .B(n2372), .S0(n4678), .Y(n1687) );
MX2X1TS U5613 ( .A(FPMULT_Exp_module_Data_S[5]), .B(
FPMULT_exp_oper_result[5]), .S0(n4677), .Y(n1544) );
MX2X1TS U5614 ( .A(n2372), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U5615 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n4678), .Y(n1686)
);
MX2X1TS U5616 ( .A(FPMULT_Exp_module_Data_S[4]), .B(n2343), .S0(n4677), .Y(
n1545) );
MX2X1TS U5617 ( .A(FPMULT_Op_MX[27]), .B(n2343), .S0(FPMULT_FSM_selector_A),
.Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U5618 ( .A(Data_1[26]), .B(n2373), .S0(n4678), .Y(n1685) );
MX2X1TS U5619 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_exp_oper_result[3]), .S0(n4677), .Y(n1546) );
MX2X1TS U5620 ( .A(n2373), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U5621 ( .A(Data_1[25]), .B(n2375), .S0(n4678), .Y(n1684) );
MX2X1TS U5622 ( .A(FPMULT_Exp_module_Data_S[2]), .B(
FPMULT_exp_oper_result[2]), .S0(n4677), .Y(n1547) );
MX2X1TS U5623 ( .A(n2375), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
INVX3TS U5624 ( .A(n2444), .Y(n5071) );
MX2X1TS U5625 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n5071), .Y(n1683)
);
MX2X1TS U5626 ( .A(FPMULT_Exp_module_Data_S[1]), .B(n2344), .S0(n4677), .Y(
n1548) );
MX2X1TS U5627 ( .A(FPMULT_Op_MX[24]), .B(n2344), .S0(FPMULT_FSM_selector_A),
.Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U5628 ( .A(Data_1[23]), .B(n2371), .S0(n5071), .Y(n1682) );
MX2X1TS U5629 ( .A(FPMULT_Exp_module_Data_S[0]), .B(
FPMULT_exp_oper_result[0]), .S0(n4677), .Y(n1549) );
MX2X1TS U5630 ( .A(n2371), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U5631 ( .A(Data_2[30]), .B(n2367), .S0(n5071), .Y(n1657) );
MX2X1TS U5632 ( .A(Data_2[29]), .B(n2365), .S0(n5071), .Y(n1656) );
MX2X1TS U5633 ( .A(Data_2[28]), .B(n2364), .S0(n5071), .Y(n1655) );
MX2X1TS U5634 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n5071), .Y(n1654)
);
MX2X1TS U5635 ( .A(Data_2[26]), .B(n2339), .S0(n5071), .Y(n1653) );
MX2X1TS U5636 ( .A(Data_2[25]), .B(n2340), .S0(n5071), .Y(n1652) );
MX2X1TS U5637 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n5071), .Y(n1651)
);
MX2X1TS U5638 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n5071), .Y(n1650)
);
XNOR2X1TS U5639 ( .A(DP_OP_234J208_126_8543_n1), .B(n4679), .Y(n4681) );
MX2X1TS U5640 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1420) );
MX2X1TS U5641 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1425) );
MX2X1TS U5642 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1430) );
MX2X1TS U5643 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1435) );
MX2X1TS U5644 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1440) );
MX2X1TS U5645 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1445) );
MX2X1TS U5646 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1450) );
MX2X1TS U5647 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(
n1455) );
OA21XLTS U5648 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(
overflow_flag_addsubt), .B0(n4684), .Y(n1413) );
NAND4XLTS U5649 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n4685) );
NAND4BXLTS U5650 ( .AN(n4685), .B(FPMULT_Exp_module_Data_S[6]), .C(
FPMULT_Exp_module_Data_S[5]), .D(FPMULT_Exp_module_Data_S[4]), .Y(
n4686) );
OAI22X1TS U5651 ( .A0(FPMULT_Exp_module_Data_S[8]), .A1(n4687), .B0(n5094),
.B1(n5719), .Y(n1516) );
NAND2X2TS U5652 ( .A(n5188), .B(FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(n4690) );
OA22X1TS U5653 ( .A0(n4690), .A1(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(result_add_subt[29]), .Y(n1469) );
INVX2TS U5654 ( .A(n4690), .Y(n4689) );
AOI22X1TS U5655 ( .A0(n4689), .A1(n4688), .B0(n5718), .B1(n5670), .Y(n1472)
);
OA22X1TS U5656 ( .A0(n4690), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(result_add_subt[25]), .Y(n1473) );
OA22X1TS U5657 ( .A0(n4690), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(
FPADDSUB_Shift_reg_FLAGS_7[0]), .B1(result_add_subt[23]), .Y(n1475) );
INVX2TS U5658 ( .A(n4691), .Y(n4693) );
NAND2X1TS U5659 ( .A(n4693), .B(n4692), .Y(n4695) );
NAND2X1TS U5660 ( .A(n2479), .B(n4697), .Y(n4699) );
XNOR2X1TS U5661 ( .A(n4699), .B(n4698), .Y(n4700) );
INVX2TS U5662 ( .A(n4701), .Y(n4703) );
NAND2X1TS U5663 ( .A(n4703), .B(n4702), .Y(n4705) );
INVX2TS U5664 ( .A(n4711), .Y(n4713) );
MX2X1TS U5665 ( .A(FPMULT_P_Sgf[2]), .B(n4731), .S0(n4751), .Y(n1555) );
MX2X1TS U5666 ( .A(FPMULT_P_Sgf[4]), .B(n4732), .S0(n4751), .Y(n1557) );
MX2X1TS U5667 ( .A(FPMULT_P_Sgf[5]), .B(n4733), .S0(n4751), .Y(n1558) );
INVX2TS U5668 ( .A(n4734), .Y(n4736) );
MX2X1TS U5669 ( .A(FPMULT_P_Sgf[0]), .B(n4740), .S0(n4751), .Y(n1553) );
INVX2TS U5670 ( .A(n4741), .Y(n4742) );
MX2X1TS U5671 ( .A(FPMULT_P_Sgf[1]), .B(n4742), .S0(n4751), .Y(n1554) );
MX2X1TS U5672 ( .A(FPMULT_P_Sgf[10]), .B(n4743), .S0(n4751), .Y(n1563) );
XNOR2X1TS U5673 ( .A(n4750), .B(n4749), .Y(n4752) );
MX2X1TS U5674 ( .A(FPMULT_P_Sgf[6]), .B(n4753), .S0(n4794), .Y(n1559) );
MX2X1TS U5675 ( .A(FPMULT_P_Sgf[7]), .B(n4754), .S0(n4794), .Y(n1560) );
MX2X1TS U5676 ( .A(FPMULT_P_Sgf[8]), .B(n4755), .S0(n4794), .Y(n1561) );
MX2X1TS U5677 ( .A(FPMULT_P_Sgf[9]), .B(n4756), .S0(n4794), .Y(n1562) );
INVX2TS U5678 ( .A(n4070), .Y(n4807) );
AOI22X1TS U5679 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n5095), .B0(
n2320), .B1(n2387), .Y(n4806) );
INVX3TS U5680 ( .A(n4804), .Y(n4857) );
NAND2X1TS U5681 ( .A(n4857), .B(FPMULT_P_Sgf[32]), .Y(n4805) );
AO21XLTS U5682 ( .A0(n2309), .A1(n2341), .B0(n4808), .Y(n1525) );
AOI22X1TS U5683 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n5095), .B0(
n2330), .B1(n2387), .Y(n4812) );
OAI2BB1X1TS U5684 ( .A0N(FPMULT_P_Sgf[33]), .A1N(n4857), .B0(n4812), .Y(
n4813) );
AOI21X1TS U5685 ( .A0(n4070), .A1(FPMULT_P_Sgf[32]), .B0(n4813), .Y(n4814)
);
OAI2BB1X1TS U5686 ( .A0N(n2309), .A1N(n2320), .B0(n4814), .Y(n1526) );
AOI22X1TS U5687 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n5095), .B0(
n2321), .B1(n2387), .Y(n4822) );
OAI2BB1X1TS U5688 ( .A0N(FPMULT_P_Sgf[34]), .A1N(n4857), .B0(n4822), .Y(
n4823) );
AOI21X1TS U5689 ( .A0(n4070), .A1(FPMULT_P_Sgf[33]), .B0(n4823), .Y(n4824)
);
OAI2BB1X1TS U5690 ( .A0N(n2309), .A1N(n2330), .B0(n4824), .Y(n1527) );
AOI22X1TS U5691 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n5095), .B0(
n2331), .B1(n2387), .Y(n4825) );
OAI2BB1X1TS U5692 ( .A0N(FPMULT_P_Sgf[35]), .A1N(n4857), .B0(n4825), .Y(
n4826) );
AOI21X1TS U5693 ( .A0(n4070), .A1(FPMULT_P_Sgf[34]), .B0(n4826), .Y(n4827)
);
OAI2BB1X1TS U5694 ( .A0N(n2309), .A1N(n2321), .B0(n4827), .Y(n1528) );
AOI22X1TS U5695 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n4855), .B0(
n2322), .B1(n2387), .Y(n4828) );
OAI2BB1X1TS U5696 ( .A0N(FPMULT_P_Sgf[36]), .A1N(n4857), .B0(n4828), .Y(
n4829) );
AOI21X1TS U5697 ( .A0(n4070), .A1(FPMULT_P_Sgf[35]), .B0(n4829), .Y(n4830)
);
OAI2BB1X1TS U5698 ( .A0N(n2309), .A1N(n2331), .B0(n4830), .Y(n1529) );
AOI22X1TS U5699 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n4855), .B0(
n2332), .B1(n2387), .Y(n4831) );
OAI2BB1X1TS U5700 ( .A0N(FPMULT_P_Sgf[37]), .A1N(n4857), .B0(n4831), .Y(
n4832) );
AOI21X1TS U5701 ( .A0(n4070), .A1(FPMULT_P_Sgf[36]), .B0(n4832), .Y(n4833)
);
OAI2BB1X1TS U5702 ( .A0N(n2309), .A1N(n2322), .B0(n4833), .Y(n1530) );
AOI22X1TS U5703 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n4855), .B0(
n2323), .B1(n2387), .Y(n4834) );
OAI2BB1X1TS U5704 ( .A0N(FPMULT_P_Sgf[38]), .A1N(n4857), .B0(n4834), .Y(
n4835) );
AOI21X1TS U5705 ( .A0(n4070), .A1(FPMULT_P_Sgf[37]), .B0(n4835), .Y(n4836)
);
OAI2BB1X1TS U5706 ( .A0N(n2309), .A1N(n2332), .B0(n4836), .Y(n1531) );
AOI22X1TS U5707 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n4855), .B0(
n2333), .B1(n2387), .Y(n4837) );
OAI2BB1X1TS U5708 ( .A0N(FPMULT_P_Sgf[39]), .A1N(n4857), .B0(n4837), .Y(
n4838) );
AOI21X1TS U5709 ( .A0(n4070), .A1(FPMULT_P_Sgf[38]), .B0(n4838), .Y(n4839)
);
OAI2BB1X1TS U5710 ( .A0N(n2309), .A1N(n2323), .B0(n4839), .Y(n1532) );
AOI22X1TS U5711 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n4855), .B0(
FPMULT_Add_result[17]), .B1(n2387), .Y(n4840) );
OAI2BB1X1TS U5712 ( .A0N(FPMULT_P_Sgf[40]), .A1N(n4857), .B0(n4840), .Y(
n4841) );
AOI21X1TS U5713 ( .A0(n4070), .A1(FPMULT_P_Sgf[39]), .B0(n4841), .Y(n4842)
);
OAI2BB1X1TS U5714 ( .A0N(n2309), .A1N(n2333), .B0(n4842), .Y(n1533) );
AOI22X1TS U5715 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n4855), .B0(
FPMULT_Add_result[18]), .B1(n2387), .Y(n4843) );
OAI2BB1X1TS U5716 ( .A0N(FPMULT_P_Sgf[41]), .A1N(n4857), .B0(n4843), .Y(
n4844) );
AOI21X1TS U5717 ( .A0(n4859), .A1(FPMULT_P_Sgf[40]), .B0(n4844), .Y(n4845)
);
OAI2BB1X1TS U5718 ( .A0N(n2309), .A1N(FPMULT_Add_result[17]), .B0(n4845),
.Y(n1534) );
AOI22X1TS U5719 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n4855), .B0(
FPMULT_Add_result[19]), .B1(n2388), .Y(n4846) );
OAI2BB1X1TS U5720 ( .A0N(FPMULT_P_Sgf[42]), .A1N(n4857), .B0(n4846), .Y(
n4847) );
AOI21X1TS U5721 ( .A0(n4859), .A1(FPMULT_P_Sgf[41]), .B0(n4847), .Y(n4848)
);
OAI2BB1X1TS U5722 ( .A0N(n2309), .A1N(FPMULT_Add_result[18]), .B0(n4848),
.Y(n1535) );
AOI22X1TS U5723 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4855), .B0(
FPMULT_Add_result[20]), .B1(n2388), .Y(n4849) );
OAI2BB1X1TS U5724 ( .A0N(FPMULT_P_Sgf[43]), .A1N(n4857), .B0(n4849), .Y(
n4850) );
AOI21X1TS U5725 ( .A0(n4859), .A1(FPMULT_P_Sgf[42]), .B0(n4850), .Y(n4851)
);
OAI2BB1X1TS U5726 ( .A0N(n2309), .A1N(FPMULT_Add_result[19]), .B0(n4851),
.Y(n1536) );
AOI22X1TS U5727 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n4855), .B0(
FPMULT_Add_result[21]), .B1(n2388), .Y(n4852) );
OAI2BB1X1TS U5728 ( .A0N(FPMULT_P_Sgf[44]), .A1N(n4857), .B0(n4852), .Y(
n4853) );
AOI21X1TS U5729 ( .A0(n4859), .A1(FPMULT_P_Sgf[43]), .B0(n4853), .Y(n4854)
);
OAI2BB1X1TS U5730 ( .A0N(n2309), .A1N(FPMULT_Add_result[20]), .B0(n4854),
.Y(n1537) );
AOI22X1TS U5731 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n4855), .B0(
FPMULT_Add_result[22]), .B1(n2388), .Y(n4856) );
OAI2BB1X1TS U5732 ( .A0N(FPMULT_P_Sgf[45]), .A1N(n4857), .B0(n4856), .Y(
n4858) );
AOI21X1TS U5733 ( .A0(n4859), .A1(FPMULT_P_Sgf[44]), .B0(n4858), .Y(n4860)
);
OAI2BB1X1TS U5734 ( .A0N(n2309), .A1N(FPMULT_Add_result[21]), .B0(n4860),
.Y(n1538) );
NOR4X1TS U5735 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n4867) );
NOR4X1TS U5736 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n4866) );
NOR4X1TS U5737 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n4864) );
NOR3XLTS U5738 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n4863) );
NOR4X1TS U5739 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n4862) );
NOR4X1TS U5740 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n4861) );
AND4X1TS U5741 ( .A(n4864), .B(n4863), .C(n4862), .D(n4861), .Y(n4865) );
NAND4XLTS U5742 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4869) );
NAND4XLTS U5743 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4868) );
NOR3X1TS U5744 ( .A(n5867), .B(n4869), .C(n4868), .Y(n4874) );
NOR4X1TS U5745 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[28]), .D(dataB[23]),
.Y(n4871) );
NOR3XLTS U5746 ( .A(dataB[26]), .B(dataB[29]), .C(dataB[25]), .Y(n4870) );
NAND4XLTS U5747 ( .A(n4874), .B(operation_reg[1]), .C(n4871), .D(n4870), .Y(
n4872) );
NOR3XLTS U5748 ( .A(operation_reg[0]), .B(dataB[31]), .C(n4872), .Y(n4873)
);
OAI211XLTS U5749 ( .A0(dataB[27]), .A1(n4873), .B0(n5866), .C0(n5865), .Y(
n4884) );
NOR4X1TS U5750 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[28]), .D(dataA[26]),
.Y(n4877) );
NOR4BX1TS U5751 ( .AN(operation_reg[1]), .B(dataA[31]), .C(dataA[24]), .D(
dataA[25]), .Y(n4876) );
NOR4X1TS U5752 ( .A(n5867), .B(dataA[30]), .C(operation_reg[0]), .D(
dataA[27]), .Y(n4875) );
NOR2BX1TS U5753 ( .AN(n4874), .B(operation_reg[1]), .Y(n4882) );
AOI31XLTS U5754 ( .A0(n4877), .A1(n4876), .A2(n4875), .B0(n4882), .Y(n4880)
);
NAND3XLTS U5755 ( .A(dataB[23]), .B(dataB[28]), .C(dataB[25]), .Y(n4879) );
NAND4XLTS U5756 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n4878) );
OAI31X1TS U5757 ( .A0(n4880), .A1(n4879), .A2(n4878), .B0(dataB[27]), .Y(
n4881) );
NAND4XLTS U5758 ( .A(n5870), .B(n5869), .C(n5868), .D(n4881), .Y(n4883) );
OAI2BB2XLTS U5759 ( .B0(n4884), .B1(n4883), .A0N(n4882), .A1N(
operation_reg[0]), .Y(NaN_reg) );
AOI22X1TS U5760 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n4885), .B1(n5530),
.Y(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
NOR3XLTS U5761 ( .A(n4990), .B(n4944), .C(n4886), .Y(n4887) );
CLKAND2X2TS U5762 ( .A(begin_operation), .B(operation[1]), .Y(n4891) );
OAI22X1TS U5763 ( .A0(n4889), .A1(n4888), .B0(n4891), .B1(n4890), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U5764 ( .AN(n4891), .B(n4890), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
NOR3XLTS U5765 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n5557),
.C(n4892), .Y(n4893) );
AO21XLTS U5766 ( .A0(n4914), .A1(n4894), .B0(n4893), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
OAI22X1TS U5767 ( .A0(n5059), .A1(n4897), .B0(n4896), .B1(n4895), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
AOI22X1TS U5768 ( .A0(cordic_result[30]), .A1(n4903), .B0(n4902), .B1(
mult_result[30]), .Y(n4899) );
OAI2BB1X1TS U5769 ( .A0N(n4906), .A1N(result_add_subt[30]), .B0(n4899), .Y(
op_result[30]) );
AOI22X1TS U5770 ( .A0(cordic_result[29]), .A1(n4903), .B0(n4902), .B1(
mult_result[29]), .Y(n4900) );
OAI2BB1X1TS U5771 ( .A0N(n4906), .A1N(result_add_subt[29]), .B0(n4900), .Y(
op_result[29]) );
AOI22X1TS U5772 ( .A0(cordic_result[25]), .A1(n4903), .B0(n4902), .B1(
mult_result[25]), .Y(n4901) );
OAI2BB1X1TS U5773 ( .A0N(n4906), .A1N(result_add_subt[25]), .B0(n4901), .Y(
op_result[25]) );
AOI22X1TS U5774 ( .A0(cordic_result[23]), .A1(n4903), .B0(n4902), .B1(
mult_result[23]), .Y(n4904) );
OAI2BB1X1TS U5775 ( .A0N(n4906), .A1N(result_add_subt[23]), .B0(n4904), .Y(
op_result[23]) );
AOI22X1TS U5776 ( .A0(n4906), .A1(n2381), .B0(n4469), .B1(n4905), .Y(n4907)
);
OAI2BB1X1TS U5777 ( .A0N(n4908), .A1N(n4468), .B0(n4907), .Y(operation_ready) );
BUFX3TS U5778 ( .A(n5711), .Y(n5294) );
BUFX3TS U5779 ( .A(n5294), .Y(n5473) );
AOI22X1TS U5780 ( .A0(n4911), .A1(n4205), .B0(n5473), .B1(n4909), .Y(n2149)
);
AOI22X1TS U5781 ( .A0(n4911), .A1(n5473), .B0(n2410), .B1(n4909), .Y(n2148)
);
INVX2TS U5782 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n5421) );
INVX3TS U5783 ( .A(n5421), .Y(n5414) );
AOI22X1TS U5784 ( .A0(n4911), .A1(n5375), .B0(n4910), .B1(n4909), .Y(n2145)
);
AOI22X1TS U5785 ( .A0(n4911), .A1(n4910), .B0(n5718), .B1(n4909), .Y(n2144)
);
AOI22X1TS U5786 ( .A0(n4914), .A1(n2197), .B0(n5568), .B1(n4912), .Y(n2143)
);
AOI2BB2XLTS U5787 ( .B0(n4916), .B1(n4917), .A0N(n4917), .A1N(n4916), .Y(
n2141) );
NAND2X1TS U5788 ( .A(n4916), .B(n4917), .Y(n4918) );
XNOR2X1TS U5789 ( .A(FPSENCOS_cont_iter_out[3]), .B(n4918), .Y(n2140) );
AOI2BB2XLTS U5790 ( .B0(n4919), .B1(n5705), .A0N(n5705), .A1N(n4919), .Y(
n2139) );
AO22XLTS U5791 ( .A0(n4943), .A1(FPSENCOS_d_ff1_shift_region_flag_out[0]),
.B0(n4944), .B1(region_flag[0]), .Y(n2137) );
AO22XLTS U5792 ( .A0(n4943), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B0(n4947), .B1(region_flag[1]), .Y(n2136) );
AOI22X1TS U5793 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n4939), .B0(n4922),
.B1(n4925), .Y(n4921) );
NAND2X1TS U5794 ( .A(n4921), .B(n4920), .Y(n2134) );
AOI22X1TS U5795 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n4939), .B0(n4922),
.B1(n4928), .Y(n4924) );
NAND2X1TS U5796 ( .A(n4924), .B(n4923), .Y(n2130) );
AOI22X1TS U5797 ( .A0(n4926), .A1(n4925), .B0(FPSENCOS_d_ff3_LUT_out[7]),
.B1(n4939), .Y(n4927) );
NAND2X1TS U5798 ( .A(n4927), .B(n4933), .Y(n2128) );
AO22XLTS U5799 ( .A0(n4926), .A1(n4915), .B0(n4988), .B1(
FPSENCOS_d_ff3_LUT_out[8]), .Y(n2127) );
AOI22X1TS U5800 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n4939), .B0(n4929),
.B1(n4928), .Y(n4930) );
AOI2BB2XLTS U5801 ( .B0(n4980), .B1(n4934), .A0N(FPSENCOS_d_ff3_LUT_out[13]),
.A1N(n4984), .Y(n2123) );
INVX4TS U5802 ( .A(n4980), .Y(n5060) );
AO22XLTS U5803 ( .A0(n4974), .A1(n4932), .B0(n5060), .B1(
FPSENCOS_d_ff3_LUT_out[19]), .Y(n2121) );
OAI221XLTS U5804 ( .A0(n4980), .A1(n5758), .B0(n4959), .B1(n4934), .C0(n4933), .Y(n2120) );
NOR2XLTS U5805 ( .A(n5568), .B(n4935), .Y(n4938) );
AOI22X1TS U5806 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n4939), .B0(n4938),
.B1(n4937), .Y(n4941) );
AOI32X1TS U5807 ( .A0(n4942), .A1(n4941), .A2(n4940), .B0(n4916), .B1(n4941),
.Y(n2117) );
INVX2TS U5808 ( .A(n4947), .Y(n4945) );
AO22XLTS U5809 ( .A0(n4945), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n4944), .B1(
Data_1[20]), .Y(n2094) );
AO22XLTS U5810 ( .A0(n4945), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n4944), .B1(
Data_1[21]), .Y(n2093) );
AO22XLTS U5811 ( .A0(n4945), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n4944), .B1(
Data_1[22]), .Y(n2092) );
AO22XLTS U5812 ( .A0(n4945), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n4946), .B1(
Data_1[23]), .Y(n2091) );
AO22XLTS U5813 ( .A0(n4945), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n4944), .B1(
Data_1[24]), .Y(n2090) );
AO22XLTS U5814 ( .A0(n4945), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n4946), .B1(
Data_1[25]), .Y(n2089) );
AO22XLTS U5815 ( .A0(n4945), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n4946), .B1(
Data_1[26]), .Y(n2088) );
AO22XLTS U5816 ( .A0(n5056), .A1(result_add_subt[0]), .B0(n4952), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(n2076) );
OR3X2TS U5817 ( .A(FPSENCOS_cont_var_out[1]), .B(n5705), .C(n5586), .Y(n4955) );
INVX3TS U5818 ( .A(n4955), .Y(n5057) );
OR3X1TS U5819 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n5586), .Y(n5055) );
BUFX3TS U5820 ( .A(n5055), .Y(n5063) );
INVX2TS U5821 ( .A(n5069), .Y(n4950) );
AO22XLTS U5822 ( .A0(n5056), .A1(result_add_subt[1]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(n2073) );
INVX2TS U5823 ( .A(n4955), .Y(n4951) );
BUFX3TS U5824 ( .A(n4955), .Y(n4958) );
BUFX3TS U5825 ( .A(n5055), .Y(n4956) );
AO22XLTS U5826 ( .A0(n5056), .A1(result_add_subt[2]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(n2070) );
AO22XLTS U5827 ( .A0(n5056), .A1(result_add_subt[3]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(n2067) );
AO22XLTS U5828 ( .A0(n5056), .A1(result_add_subt[4]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(n2064) );
AO22XLTS U5829 ( .A0(n5056), .A1(result_add_subt[5]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(n2061) );
INVX3TS U5830 ( .A(n4955), .Y(n5062) );
AO22XLTS U5831 ( .A0(n5056), .A1(result_add_subt[6]), .B0(n4953), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(n2058) );
INVX2TS U5832 ( .A(n4952), .Y(n4954) );
AO22XLTS U5833 ( .A0(n4954), .A1(result_add_subt[7]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(n2055) );
AO22XLTS U5834 ( .A0(n4954), .A1(result_add_subt[8]), .B0(n4952), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(n2052) );
AO22XLTS U5835 ( .A0(n4954), .A1(result_add_subt[9]), .B0(n4952), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(n2049) );
AO22XLTS U5836 ( .A0(n4954), .A1(result_add_subt[10]), .B0(n4952), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(n2046) );
AO22XLTS U5837 ( .A0(n4954), .A1(result_add_subt[11]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(n2043) );
AO22XLTS U5838 ( .A0(n5059), .A1(result_add_subt[12]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(n2040) );
AO22XLTS U5839 ( .A0(n5059), .A1(result_add_subt[13]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(n2037) );
AO22XLTS U5840 ( .A0(n5059), .A1(result_add_subt[14]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(n2034) );
AO22XLTS U5841 ( .A0(n5059), .A1(result_add_subt[15]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(n2031) );
AO22XLTS U5842 ( .A0(n5059), .A1(result_add_subt[16]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(n2028) );
AO22XLTS U5843 ( .A0(n5059), .A1(result_add_subt[17]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(n2025) );
AO22XLTS U5844 ( .A0(n5059), .A1(result_add_subt[18]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(n2022) );
AO22XLTS U5845 ( .A0(n5059), .A1(result_add_subt[19]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(n2019) );
AO22XLTS U5846 ( .A0(n5059), .A1(result_add_subt[20]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(n2016) );
AO22XLTS U5847 ( .A0(n5056), .A1(result_add_subt[21]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(n2013) );
AO22XLTS U5848 ( .A0(n5056), .A1(result_add_subt[22]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(n2010) );
AO22XLTS U5849 ( .A0(n2347), .A1(n4978), .B0(FPSENCOS_d_ff_Xn[0]), .B1(n4977), .Y(n2007) );
OA22X1TS U5850 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n4122), .B0(n2352), .B1(n4990), .Y(n2005) );
OA22X1TS U5851 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n2307), .B0(n2353), .B1(n5861), .Y(n2003) );
OA22X1TS U5852 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n4122), .B0(
FPSENCOS_d_ff2_X[3]), .B1(n5861), .Y(n2001) );
INVX3TS U5853 ( .A(n4986), .Y(n4963) );
AO22XLTS U5854 ( .A0(n4984), .A1(FPSENCOS_d_ff2_X[3]), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n2000) );
AO22XLTS U5855 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n4978), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n4977), .Y(n1999) );
OA22X1TS U5856 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n2307), .B0(n2357), .B1(n5861), .Y(n1997) );
AO22XLTS U5857 ( .A0(n4960), .A1(n2357), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1996) );
OA22X1TS U5858 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n2307), .B0(n2356), .B1(n5861), .Y(n1995) );
OA22X1TS U5859 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n4122), .B0(n2358), .B1(n5861), .Y(n1993) );
AO22XLTS U5860 ( .A0(n4960), .A1(n2358), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1992) );
INVX2TS U5861 ( .A(n4973), .Y(n4969) );
BUFX3TS U5862 ( .A(n4971), .Y(n4970) );
AO22XLTS U5863 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n4969), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n4970), .Y(n1991) );
AO22XLTS U5864 ( .A0(n2346), .A1(n4969), .B0(FPSENCOS_d_ff_Xn[9]), .B1(n4970), .Y(n1989) );
OA22X1TS U5865 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n4122), .B0(n2355), .B1(
n5861), .Y(n1987) );
AO22XLTS U5866 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n4969), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n4970), .Y(n1985) );
AO22XLTS U5867 ( .A0(n4986), .A1(FPSENCOS_d_ff2_X[11]), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1984) );
OA22X1TS U5868 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n4122), .B0(n2354), .B1(
n5861), .Y(n1983) );
OA22X1TS U5869 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n4122), .B0(n2360), .B1(
n5861), .Y(n1981) );
AO22XLTS U5870 ( .A0(n4960), .A1(n2360), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1980) );
OA22X1TS U5871 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n2307), .B0(
FPSENCOS_d_ff2_X[14]), .B1(n5861), .Y(n1979) );
AO22XLTS U5872 ( .A0(n4960), .A1(FPSENCOS_d_ff2_X[14]), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1978) );
AO22XLTS U5873 ( .A0(n2350), .A1(n4969), .B0(FPSENCOS_d_ff_Xn[15]), .B1(
n4970), .Y(n1977) );
AO22XLTS U5874 ( .A0(n4960), .A1(n2350), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1976) );
OA22X1TS U5875 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n4122), .B0(n2359), .B1(
n5861), .Y(n1975) );
AO22XLTS U5876 ( .A0(n4984), .A1(n2359), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1974) );
OA22X1TS U5877 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n2307), .B0(n2361), .B1(
n4990), .Y(n1973) );
AO22XLTS U5878 ( .A0(n4984), .A1(n2361), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1972) );
AO22XLTS U5879 ( .A0(n2349), .A1(n4969), .B0(FPSENCOS_d_ff_Xn[18]), .B1(
n4970), .Y(n1971) );
AO22XLTS U5880 ( .A0(n4986), .A1(n2349), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1970) );
OA22X1TS U5881 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n4122), .B0(n2363), .B1(
n4990), .Y(n1969) );
AO22XLTS U5882 ( .A0(n4960), .A1(n2363), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1968) );
OA22X1TS U5883 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n2307), .B0(n2362), .B1(
n4990), .Y(n1967) );
AO22XLTS U5884 ( .A0(n4926), .A1(n2362), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1966) );
AO22XLTS U5885 ( .A0(n2348), .A1(n4969), .B0(FPSENCOS_d_ff_Xn[21]), .B1(
n4970), .Y(n1965) );
AO22XLTS U5886 ( .A0(n2351), .A1(n4972), .B0(FPSENCOS_d_ff_Xn[22]), .B1(
n4970), .Y(n1963) );
AO22XLTS U5887 ( .A0(n4926), .A1(n2351), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1962) );
AO22XLTS U5888 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n4969), .B0(n2325), .B1(
n4970), .Y(n1961) );
OA22X1TS U5889 ( .A0(n2336), .A1(n2307), .B0(FPSENCOS_d_ff2_X[24]), .B1(
n4990), .Y(n1960) );
OA22X1TS U5890 ( .A0(n2338), .A1(n2307), .B0(FPSENCOS_d_ff2_X[25]), .B1(
n5861), .Y(n1959) );
OA22X1TS U5891 ( .A0(n2335), .A1(n2307), .B0(FPSENCOS_d_ff2_X[26]), .B1(
n4990), .Y(n1958) );
OA22X1TS U5892 ( .A0(n2334), .A1(n2307), .B0(FPSENCOS_d_ff2_X[27]), .B1(
n4990), .Y(n1957) );
OA22X1TS U5893 ( .A0(FPSENCOS_d_ff2_X[28]), .A1(n4973), .B0(
FPSENCOS_d_ff_Xn[28]), .B1(n2307), .Y(n1956) );
OA22X1TS U5894 ( .A0(n2337), .A1(n2307), .B0(FPSENCOS_d_ff2_X[29]), .B1(
n4973), .Y(n1955) );
AO22XLTS U5895 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n4969), .B0(n2324), .B1(
n4970), .Y(n1954) );
NOR2X1TS U5896 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_474_n1), .Y(n4962) );
AOI21X1TS U5897 ( .A0(intadd_474_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4962),
.Y(n4961) );
AOI2BB2XLTS U5898 ( .B0(n4980), .B1(n4961), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n4984), .Y(n1949) );
OR3X1TS U5899 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_474_n1), .Y(n4965) );
OAI21XLTS U5900 ( .A0(n4962), .A1(n5710), .B0(n4965), .Y(n4964) );
AO22XLTS U5901 ( .A0(n4926), .A1(n4964), .B0(n4963), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1948) );
NOR2X1TS U5902 ( .A(FPSENCOS_d_ff2_X[29]), .B(n4965), .Y(n4967) );
AOI21X1TS U5903 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n4965), .B0(n4967), .Y(
n4966) );
AOI2BB2XLTS U5904 ( .B0(n4980), .B1(n4966), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n4984), .Y(n1947) );
XOR2XLTS U5905 ( .A(FPSENCOS_d_ff2_X[30]), .B(n4967), .Y(n4968) );
AO22XLTS U5906 ( .A0(n4992), .A1(n4968), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1946) );
AO22XLTS U5907 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n4977), .B0(n2345), .B1(
n4969), .Y(n1945) );
AO22XLTS U5908 ( .A0(n4992), .A1(n2345), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1944) );
AO22XLTS U5909 ( .A0(n5056), .A1(result_add_subt[31]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(n1911) );
AOI22X1TS U5910 ( .A0(n5057), .A1(n5566), .B0(n5713), .B1(n5061), .Y(n1910)
);
AO22XLTS U5911 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n4970), .Y(n1909) );
AO22XLTS U5912 ( .A0(n4992), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1908) );
BUFX3TS U5913 ( .A(n4971), .Y(n4975) );
AO22XLTS U5914 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n4970), .Y(n1907) );
AO22XLTS U5915 ( .A0(n4992), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1906) );
AO22XLTS U5916 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n4970), .Y(n1905) );
AO22XLTS U5917 ( .A0(n4926), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1904) );
AO22XLTS U5918 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n4970), .Y(n1903) );
AO22XLTS U5919 ( .A0(n4986), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1902) );
AO22XLTS U5920 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n4970), .Y(n1901) );
AO22XLTS U5921 ( .A0(n4986), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1900) );
AO22XLTS U5922 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n4975), .Y(n1899) );
AO22XLTS U5923 ( .A0(n4980), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1898) );
AO22XLTS U5924 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n4971), .Y(n1897) );
AO22XLTS U5925 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1896) );
AO22XLTS U5926 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n4971), .Y(n1895) );
AO22XLTS U5927 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1894) );
AO22XLTS U5928 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n4971), .Y(n1893) );
AO22XLTS U5929 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[8]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1892) );
AO22XLTS U5930 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n4971), .Y(n1891) );
AO22XLTS U5931 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1890) );
AO22XLTS U5932 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n4971), .Y(n1889) );
AO22XLTS U5933 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[10]), .B0(n5060), .B1(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1888) );
AO22XLTS U5934 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n4971), .Y(n1887) );
AO22XLTS U5935 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1886) );
AO22XLTS U5936 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n4972), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n4971), .Y(n1885) );
AO22XLTS U5937 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[12]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1884) );
AO22XLTS U5938 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n4971), .Y(n1883) );
AO22XLTS U5939 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1882) );
AO22XLTS U5940 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n4975), .Y(n1881) );
AO22XLTS U5941 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1880) );
AO22XLTS U5942 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n4975), .Y(n1879) );
AO22XLTS U5943 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1878) );
AO22XLTS U5944 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n4975), .Y(n1877) );
AO22XLTS U5945 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1876) );
AO22XLTS U5946 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n4975), .Y(n1875) );
AO22XLTS U5947 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1874) );
AO22XLTS U5948 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n4975), .Y(n1873) );
AO22XLTS U5949 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1872) );
AO22XLTS U5950 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n4975), .Y(n1871) );
AO22XLTS U5951 ( .A0(n4984), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1870) );
AO22XLTS U5952 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n4975), .Y(n1869) );
AO22XLTS U5953 ( .A0(n4986), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n4988), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1868) );
AO22XLTS U5954 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n4975), .Y(n1867) );
AO22XLTS U5955 ( .A0(n4974), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1866) );
AO22XLTS U5956 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n4975), .Y(n1865) );
AO22XLTS U5957 ( .A0(n4992), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n4988), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1864) );
AO22XLTS U5958 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4976), .B0(n2329), .B1(
n4975), .Y(n1863) );
AO22XLTS U5959 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n4975), .Y(n1862) );
AO22XLTS U5960 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n4976), .B0(n2328), .B1(
n4975), .Y(n1861) );
AO22XLTS U5961 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n4976), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n4975), .Y(n1860) );
AO22XLTS U5962 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n4978), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n4977), .Y(n1859) );
AO22XLTS U5963 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n4978), .B0(
FPSENCOS_d_ff_Yn[28]), .B1(n4977), .Y(n1858) );
AO22XLTS U5964 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4978), .B0(n2327), .B1(
n4977), .Y(n1857) );
AO22XLTS U5965 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n4978), .B0(n2326), .B1(
n4977), .Y(n1856) );
AO22XLTS U5966 ( .A0(n4992), .A1(intadd_473_SUM_0_), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1854) );
AO22XLTS U5967 ( .A0(n4984), .A1(intadd_473_SUM_1_), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1853) );
AO22XLTS U5968 ( .A0(n4992), .A1(intadd_473_SUM_2_), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1852) );
AOI21X1TS U5969 ( .A0(intadd_473_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n4981),
.Y(n4979) );
AOI2BB2XLTS U5970 ( .B0(n4980), .B1(n4979), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n4984), .Y(n1851) );
NAND2X1TS U5971 ( .A(n4981), .B(n2247), .Y(n4983) );
OAI21XLTS U5972 ( .A0(n4981), .A1(n2247), .B0(n4983), .Y(n4982) );
AO22XLTS U5973 ( .A0(n4992), .A1(n4982), .B0(n4988), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1850) );
AOI21X1TS U5974 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4983), .B0(n4987), .Y(
n4985) );
AOI2BB2XLTS U5975 ( .B0(n4986), .B1(n4985), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n4984), .Y(n1849) );
AOI2BB2XLTS U5976 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n4987), .A0N(n4987),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n4989) );
AO22XLTS U5977 ( .A0(n4992), .A1(n4989), .B0(n4988), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1848) );
OAI22X1TS U5978 ( .A0(n4990), .A1(n2503), .B0(n5713), .B1(n2307), .Y(n1847)
);
AO22XLTS U5979 ( .A0(n4992), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n4991), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1846) );
AOI22X1TS U5980 ( .A0(Data_2[3]), .A1(n5039), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n4999), .Y(n4994) );
AOI22X1TS U5981 ( .A0(n4996), .A1(FPSENCOS_d_ff3_sh_y_out[3]), .B0(n4995),
.B1(FPSENCOS_d_ff3_sh_x_out[3]), .Y(n4993) );
NAND2X1TS U5982 ( .A(n5033), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n5012) );
AOI22X1TS U5983 ( .A0(Data_2[5]), .A1(n5039), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n4999), .Y(n4998) );
AOI22X1TS U5984 ( .A0(n4996), .A1(FPSENCOS_d_ff3_sh_y_out[5]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[5]), .Y(n4997) );
NAND2X1TS U5985 ( .A(n5033), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n5007) );
AOI22X1TS U5986 ( .A0(Data_2[7]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n4999), .Y(n5001) );
AOI22X1TS U5987 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[7]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[7]), .Y(n5000) );
NAND2X1TS U5988 ( .A(n5033), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n5002) );
AOI22X1TS U5989 ( .A0(Data_2[11]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n5024), .Y(n5004) );
AOI22X1TS U5990 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[11]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[11]), .Y(n5003) );
AOI22X1TS U5991 ( .A0(Data_2[13]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n5024), .Y(n5006) );
AOI22X1TS U5992 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[13]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[13]), .Y(n5005) );
NAND2X1TS U5993 ( .A(n5033), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n5017) );
AOI22X1TS U5994 ( .A0(Data_2[14]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n5024), .Y(n5009) );
AOI22X1TS U5995 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[14]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[14]), .Y(n5008) );
AOI22X1TS U5996 ( .A0(Data_2[15]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n5024), .Y(n5011) );
AOI22X1TS U5997 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[15]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[15]), .Y(n5010) );
AOI22X1TS U5998 ( .A0(Data_2[16]), .A1(n5039), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n5024), .Y(n5014) );
AOI22X1TS U5999 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[16]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[16]), .Y(n5013) );
AOI22X1TS U6000 ( .A0(Data_2[17]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n5024), .Y(n5016) );
AOI22X1TS U6001 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[17]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[17]), .Y(n5015) );
AOI22X1TS U6002 ( .A0(Data_2[18]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n5024), .Y(n5019) );
AOI22X1TS U6003 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[18]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[18]), .Y(n5018) );
AOI22X1TS U6004 ( .A0(Data_2[19]), .A1(n5020), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n5024), .Y(n5023) );
AOI22X1TS U6005 ( .A0(n5021), .A1(FPSENCOS_d_ff3_sh_y_out[19]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[19]), .Y(n5022) );
NAND2X1TS U6006 ( .A(n5033), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n5029) );
AOI22X1TS U6007 ( .A0(Data_2[20]), .A1(n5025), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n5024), .Y(n5028) );
AOI22X1TS U6008 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[20]), .B0(n4995),
.B1(FPSENCOS_d_ff3_sh_x_out[20]), .Y(n5027) );
AOI22X1TS U6009 ( .A0(Data_2[22]), .A1(n5065), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n5064), .Y(n5031) );
AOI22X1TS U6010 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[22]), .B0(n4995),
.B1(FPSENCOS_d_ff3_sh_x_out[22]), .Y(n5030) );
AOI22X1TS U6011 ( .A0(Data_2[27]), .A1(n5065), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n5064), .Y(n5035) );
AOI22X1TS U6012 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[27]), .B0(n5032),
.B1(FPSENCOS_d_ff3_sh_x_out[27]), .Y(n5034) );
NAND2X1TS U6013 ( .A(n5033), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n5040) );
AOI22X1TS U6014 ( .A0(Data_2[28]), .A1(n5036), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n5064), .Y(n5038) );
AOI22X1TS U6015 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[28]), .B0(n4995),
.B1(FPSENCOS_d_ff3_sh_x_out[28]), .Y(n5037) );
AOI22X1TS U6016 ( .A0(Data_2[29]), .A1(n5039), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n5064), .Y(n5042) );
AOI22X1TS U6017 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[29]), .B0(n4995),
.B1(FPSENCOS_d_ff3_sh_x_out[29]), .Y(n5041) );
AOI22X1TS U6018 ( .A0(FPSENCOS_d_ff3_sh_x_out[30]), .A1(n5032), .B0(
FPADDSUB_intDY_EWSW[30]), .B1(n5064), .Y(n5044) );
AOI22X1TS U6019 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[30]), .B0(n5065),
.B1(Data_2[30]), .Y(n5043) );
NAND2X1TS U6020 ( .A(n5044), .B(n5043), .Y(n1815) );
OAI22X1TS U6021 ( .A0(n5047), .A1(n5046), .B0(n5045), .B1(n5580), .Y(n1814)
);
AOI22X1TS U6022 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n5049), .B0(n5048),
.B1(FPADDSUB_Data_array_SWR[0]), .Y(n5053) );
AOI22X1TS U6023 ( .A0(n2313), .A1(n5051), .B0(n2311), .B1(n5050), .Y(n5052)
);
AO22XLTS U6024 ( .A0(n5056), .A1(result_add_subt[23]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1788) );
AO22XLTS U6025 ( .A0(n5057), .A1(result_add_subt[23]), .B0(n5061), .B1(n2329), .Y(n1787) );
AO22XLTS U6026 ( .A0(n5070), .A1(result_add_subt[23]), .B0(n4956), .B1(n2325), .Y(n1786) );
AO22XLTS U6027 ( .A0(n5056), .A1(result_add_subt[24]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(n1785) );
AO22XLTS U6028 ( .A0(n5056), .A1(result_add_subt[25]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1782) );
AO22XLTS U6029 ( .A0(n5057), .A1(result_add_subt[25]), .B0(n5061), .B1(n2328), .Y(n1781) );
AO22XLTS U6030 ( .A0(n5070), .A1(result_add_subt[25]), .B0(n5069), .B1(n2338), .Y(n1780) );
AO22XLTS U6031 ( .A0(n5056), .A1(result_add_subt[26]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(n1779) );
AO22XLTS U6032 ( .A0(n5059), .A1(result_add_subt[27]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(n1776) );
AO22XLTS U6033 ( .A0(n5059), .A1(result_add_subt[28]), .B0(n2199), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(n1773) );
AO22XLTS U6034 ( .A0(n5059), .A1(result_add_subt[29]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1770) );
AO22XLTS U6035 ( .A0(n5057), .A1(result_add_subt[29]), .B0(n5061), .B1(n2327), .Y(n1769) );
AO22XLTS U6036 ( .A0(n5070), .A1(result_add_subt[29]), .B0(n5063), .B1(n2337), .Y(n1768) );
AO22XLTS U6037 ( .A0(n5059), .A1(result_add_subt[30]), .B0(n5058), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1767) );
AO22XLTS U6038 ( .A0(n4992), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n5060), .B1(
n2319), .Y(n1734) );
AO22XLTS U6039 ( .A0(n5062), .A1(result_add_subt[30]), .B0(n5061), .B1(n2326), .Y(n1732) );
AO22XLTS U6040 ( .A0(n5070), .A1(result_add_subt[30]), .B0(n5063), .B1(n2324), .Y(n1731) );
AOI22X1TS U6041 ( .A0(FPSENCOS_d_ff3_sh_x_out[31]), .A1(n4995), .B0(
FPADDSUB_intDY_EWSW[31]), .B1(n5064), .Y(n5068) );
AOI22X1TS U6042 ( .A0(n5066), .A1(FPSENCOS_d_ff3_sh_y_out[31]), .B0(n5065),
.B1(Data_2[31]), .Y(n5067) );
NAND2X1TS U6043 ( .A(n5068), .B(n5067), .Y(n1730) );
AOI22X1TS U6044 ( .A0(n5070), .A1(n5566), .B0(n5725), .B1(n5069), .Y(n1729)
);
AO22XLTS U6045 ( .A0(n2444), .A1(Data_2[31]), .B0(n5071), .B1(
FPMULT_Op_MY[31]), .Y(n1696) );
AO22XLTS U6046 ( .A0(n2444), .A1(Data_1[31]), .B0(n5071), .B1(
FPMULT_Op_MX[31]), .Y(n1658) );
NOR4X1TS U6047 ( .A(n2440), .B(FPMULT_Op_MY[18]), .C(FPMULT_Op_MY[16]), .D(
n2395), .Y(n5075) );
NOR4X1TS U6048 ( .A(FPMULT_Op_MY[17]), .B(n2367), .C(n2365), .D(n2364), .Y(
n5072) );
NAND4XLTS U6049 ( .A(n5075), .B(n5074), .C(n5073), .D(n5072), .Y(n5091) );
NOR4X1TS U6050 ( .A(FPMULT_Op_MY[8]), .B(n2302), .C(FPMULT_Op_MY[6]), .D(
n2301), .Y(n5079) );
NOR4X1TS U6051 ( .A(FPMULT_Op_MY[10]), .B(n2385), .C(FPMULT_Op_MY[2]), .D(
n2297), .Y(n5078) );
NOR4X1TS U6052 ( .A(n2437), .B(FPMULT_Op_MY[4]), .C(n2382), .D(
FPMULT_Op_MY[0]), .Y(n5077) );
NAND4XLTS U6053 ( .A(n5079), .B(n5078), .C(n5077), .D(n5076), .Y(n5090) );
NOR4X1TS U6054 ( .A(FPMULT_Op_MX[27]), .B(n2373), .C(n2375), .D(n2371), .Y(
n5081) );
NOR4X1TS U6055 ( .A(FPMULT_Op_MX[22]), .B(n2374), .C(FPMULT_Op_MX[29]), .D(
n2372), .Y(n5080) );
NAND4XLTS U6056 ( .A(n5083), .B(n5082), .C(n5081), .D(n5080), .Y(n5089) );
NOR4X1TS U6057 ( .A(FPMULT_Op_MX[10]), .B(FPMULT_Op_MX[8]), .C(
FPMULT_Op_MX[6]), .D(FPMULT_Op_MX[4]), .Y(n5086) );
NOR3XLTS U6058 ( .A(FPMULT_Op_MX[11]), .B(FPMULT_Op_MX[3]), .C(
FPMULT_Op_MX[24]), .Y(n5084) );
NAND4XLTS U6059 ( .A(n5087), .B(n5086), .C(n5085), .D(n5084), .Y(n5088) );
OA22X1TS U6060 ( .A0(n5091), .A1(n5090), .B0(n5089), .B1(n5088), .Y(n5093)
);
AOI22X1TS U6061 ( .A0(n5094), .A1(n5093), .B0(n5759), .B1(n5092), .Y(n1626)
);
AOI32X1TS U6062 ( .A0(n5097), .A1(n4052), .A2(n5096), .B0(n5724), .B1(n5095),
.Y(n1625) );
AOI2BB2XLTS U6063 ( .B0(n5138), .B1(FPMULT_Sgf_normalized_result[0]), .A0N(
FPMULT_Add_result[0]), .A1N(n5148), .Y(n1624) );
NOR2XLTS U6064 ( .A(n2408), .B(FPMULT_Sgf_normalized_result[0]), .Y(n5098)
);
AOI21X1TS U6065 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n2408), .B0(
n5098), .Y(n5099) );
AOI2BB2XLTS U6066 ( .B0(n5138), .B1(n5099), .A0N(n2369), .A1N(n5148), .Y(
n1623) );
OAI21XLTS U6067 ( .A0(n2408), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
n2403), .Y(n5100) );
AOI32X1TS U6068 ( .A0(n5101), .A1(n5138), .A2(n5100), .B0(n5723), .B1(n5146),
.Y(n1622) );
OAI211XLTS U6069 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n5101), .B0(
n5138), .C0(n5103), .Y(n5102) );
OAI2BB1X1TS U6070 ( .A0N(FPMULT_Add_result[3]), .A1N(n5143), .B0(n5102), .Y(
n1621) );
OAI21XLTS U6071 ( .A0(n5103), .A1(n5598), .B0(n5105), .Y(n5104) );
OAI211XLTS U6072 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n5105), .B0(
n5138), .C0(n5107), .Y(n5106) );
OAI2BB1X1TS U6073 ( .A0N(FPMULT_Add_result[5]), .A1N(n5143), .B0(n5106), .Y(
n1619) );
NOR2X2TS U6074 ( .A(n5601), .B(n5107), .Y(n5109) );
AOI21X1TS U6075 ( .A0(n5601), .A1(n5107), .B0(n5109), .Y(n5108) );
OAI211XLTS U6076 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n5109), .B0(
n5138), .C0(n5111), .Y(n5110) );
OAI2BB1X1TS U6077 ( .A0N(FPMULT_Add_result[7]), .A1N(n5143), .B0(n5110), .Y(
n1617) );
AOI21X1TS U6078 ( .A0(n5602), .A1(n5111), .B0(n5113), .Y(n5112) );
OAI2BB1X1TS U6079 ( .A0N(n2320), .A1N(n5146), .B0(n5114), .Y(n1615) );
AOI21X1TS U6080 ( .A0(n5605), .A1(n5115), .B0(n5117), .Y(n5116) );
OAI2BB1X1TS U6081 ( .A0N(n2321), .A1N(n5146), .B0(n5118), .Y(n1613) );
AOI21X1TS U6082 ( .A0(n5613), .A1(n5119), .B0(n5121), .Y(n5120) );
OAI2BB1X1TS U6083 ( .A0N(n2322), .A1N(n5146), .B0(n5122), .Y(n1611) );
AOI21X1TS U6084 ( .A0(n5629), .A1(n5123), .B0(n5125), .Y(n5124) );
OAI2BB1X1TS U6085 ( .A0N(n2323), .A1N(n5143), .B0(n5126), .Y(n1609) );
AOI21X1TS U6086 ( .A0(n5638), .A1(n5127), .B0(n5129), .Y(n5128) );
OAI2BB1X1TS U6087 ( .A0N(FPMULT_Add_result[17]), .A1N(n5135), .B0(n5130),
.Y(n1607) );
AOI21X1TS U6088 ( .A0(n5687), .A1(n5131), .B0(n5133), .Y(n5132) );
OAI2BB1X1TS U6089 ( .A0N(FPMULT_Add_result[19]), .A1N(n5135), .B0(n5134),
.Y(n1605) );
NOR2X2TS U6090 ( .A(n5701), .B(n5136), .Y(n5139) );
AOI21X1TS U6091 ( .A0(n5701), .A1(n5136), .B0(n5139), .Y(n5137) );
OAI2BB1X1TS U6092 ( .A0N(FPMULT_Add_result[21]), .A1N(n5143), .B0(n5140),
.Y(n1603) );
NOR2X2TS U6093 ( .A(n5706), .B(n5141), .Y(n5144) );
AOI211X1TS U6094 ( .A0(n5706), .A1(n5141), .B0(n5144), .C0(n5146), .Y(n5142)
);
AOI21X1TS U6095 ( .A0(n5144), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
n5146), .Y(n5147) );
OAI2BB1X1TS U6096 ( .A0N(FPMULT_Add_result[23]), .A1N(n5146), .B0(n5145),
.Y(n1601) );
AO22XLTS U6097 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n5150), .B0(
mult_result[0]), .B1(n5149), .Y(n1515) );
BUFX3TS U6098 ( .A(n5149), .Y(n5156) );
AO22XLTS U6099 ( .A0(n2408), .A1(n5150), .B0(mult_result[1]), .B1(n5156),
.Y(n1514) );
AO22XLTS U6100 ( .A0(n2403), .A1(n5150), .B0(mult_result[2]), .B1(n5156),
.Y(n1513) );
AO22XLTS U6101 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n5150), .B0(
mult_result[3]), .B1(n5156), .Y(n1512) );
AO22XLTS U6102 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n5150), .B0(
mult_result[4]), .B1(n5156), .Y(n1511) );
AO22XLTS U6103 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n5150), .B0(
mult_result[5]), .B1(n5156), .Y(n1510) );
AO22XLTS U6104 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n5150), .B0(
mult_result[6]), .B1(n5156), .Y(n1509) );
AO22XLTS U6105 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n5150), .B0(
mult_result[7]), .B1(n5156), .Y(n1508) );
AO22XLTS U6106 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n5150), .B0(
mult_result[8]), .B1(n5156), .Y(n1507) );
AO22XLTS U6107 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n5150), .B0(
mult_result[9]), .B1(n5156), .Y(n1506) );
AO22XLTS U6108 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n5150), .B0(
mult_result[10]), .B1(n5156), .Y(n1505) );
AO22XLTS U6109 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n5150), .B0(
mult_result[11]), .B1(n5156), .Y(n1504) );
AO22XLTS U6110 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n5150), .B0(
mult_result[12]), .B1(n5149), .Y(n1503) );
INVX2TS U6111 ( .A(n2445), .Y(n5151) );
AO22XLTS U6112 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n5151), .B0(
mult_result[13]), .B1(n5149), .Y(n1502) );
AO22XLTS U6113 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n5151), .B0(
mult_result[14]), .B1(n5149), .Y(n1501) );
AO22XLTS U6114 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n5151), .B0(
mult_result[15]), .B1(n5149), .Y(n1500) );
AO22XLTS U6115 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n5151), .B0(
mult_result[16]), .B1(n5149), .Y(n1499) );
AO22XLTS U6116 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n5151), .B0(
mult_result[17]), .B1(n5149), .Y(n1498) );
AO22XLTS U6117 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n5151), .B0(
mult_result[18]), .B1(n5149), .Y(n1497) );
AO22XLTS U6118 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n5151), .B0(
mult_result[19]), .B1(n5149), .Y(n1496) );
AO22XLTS U6119 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n5151), .B0(
mult_result[20]), .B1(n5149), .Y(n1495) );
AO22XLTS U6120 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n5151), .B0(
mult_result[21]), .B1(n5149), .Y(n1494) );
AO22XLTS U6121 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n5151), .B0(
mult_result[22]), .B1(n5149), .Y(n1493) );
OA22X1TS U6122 ( .A0(FPMULT_exp_oper_result[0]), .A1(n2445), .B0(n5152),
.B1(mult_result[23]), .Y(n1492) );
OA22X1TS U6123 ( .A0(n2344), .A1(n2445), .B0(n5152), .B1(mult_result[24]),
.Y(n1491) );
OA22X1TS U6124 ( .A0(FPMULT_exp_oper_result[2]), .A1(n2445), .B0(n5152),
.B1(mult_result[25]), .Y(n1490) );
OA22X1TS U6125 ( .A0(FPMULT_exp_oper_result[3]), .A1(n2445), .B0(n5152),
.B1(mult_result[26]), .Y(n1489) );
OA22X1TS U6126 ( .A0(n2343), .A1(n2445), .B0(n5152), .B1(mult_result[27]),
.Y(n1488) );
OA22X1TS U6127 ( .A0(FPMULT_exp_oper_result[5]), .A1(n2445), .B0(n5152),
.B1(mult_result[28]), .Y(n1487) );
OA22X1TS U6128 ( .A0(n2342), .A1(n2445), .B0(n5152), .B1(mult_result[29]),
.Y(n1486) );
OA22X1TS U6129 ( .A0(FPMULT_exp_oper_result[7]), .A1(n2445), .B0(n5152),
.B1(mult_result[30]), .Y(n1485) );
OAI21XLTS U6130 ( .A0(n5154), .A1(underflow_flag_mult), .B0(n5153), .Y(n5155) );
OAI2BB1X1TS U6131 ( .A0N(mult_result[31]), .A1N(n5156), .B0(n5155), .Y(n1483) );
NAND2X1TS U6132 ( .A(FPADDSUB_DmP_EXP_EWSW[25]), .B(n5583), .Y(n5159) );
NAND2X1TS U6133 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n5702), .Y(n5167) );
INVX2TS U6134 ( .A(n5167), .Y(n5165) );
NOR2X1TS U6135 ( .A(n5539), .B(FPADDSUB_DMP_EXP_EWSW[24]), .Y(n5163) );
OAI22X1TS U6136 ( .A0(n5165), .A1(n5163), .B0(FPADDSUB_DmP_EXP_EWSW[24]),
.B1(n5540), .Y(n5161) );
AOI22X1TS U6137 ( .A0(FPADDSUB_DMP_EXP_EWSW[25]), .A1(n5591), .B0(n5159),
.B1(n5161), .Y(n5169) );
NOR2X1TS U6138 ( .A(n5588), .B(FPADDSUB_DMP_EXP_EWSW[26]), .Y(n5170) );
AOI21X1TS U6139 ( .A0(FPADDSUB_DMP_EXP_EWSW[26]), .A1(n5588), .B0(n5170),
.Y(n5157) );
XNOR2X1TS U6140 ( .A(n5169), .B(n5157), .Y(n5158) );
AO22XLTS U6141 ( .A0(n5474), .A1(n5158), .B0(n5294), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1480) );
OAI21XLTS U6142 ( .A0(FPADDSUB_DmP_EXP_EWSW[25]), .A1(n5583), .B0(n5159),
.Y(n5160) );
XNOR2X1TS U6143 ( .A(n5161), .B(n5160), .Y(n5162) );
AO22XLTS U6144 ( .A0(n2211), .A1(n5162), .B0(n5207), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1479) );
AOI21X1TS U6145 ( .A0(FPADDSUB_DMP_EXP_EWSW[24]), .A1(n5539), .B0(n5163),
.Y(n5164) );
XNOR2X1TS U6146 ( .A(n5165), .B(n5164), .Y(n5166) );
AO22XLTS U6147 ( .A0(n2211), .A1(n5166), .B0(n5207), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1478) );
AO22XLTS U6148 ( .A0(n2211), .A1(n5168), .B0(n5207), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1477) );
OAI22X1TS U6149 ( .A0(n5170), .A1(n5169), .B0(FPADDSUB_DmP_EXP_EWSW[26]),
.B1(n5590), .Y(n5172) );
XNOR2X1TS U6150 ( .A(FPADDSUB_DmP_EXP_EWSW[27]), .B(n2368), .Y(n5171) );
XOR2XLTS U6151 ( .A(n5172), .B(n5171), .Y(n5173) );
AO22XLTS U6152 ( .A0(n2211), .A1(n5173), .B0(n5207), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1476) );
OAI222X1TS U6153 ( .A0(n5174), .A1(n5589), .B0(n5540), .B1(n5783), .C0(n5527), .C1(n5175), .Y(n1466) );
OAI222X1TS U6154 ( .A0(n5174), .A1(n5708), .B0(n5583), .B1(n5783), .C0(n5537), .C1(n5175), .Y(n1465) );
OAI222X1TS U6155 ( .A0(n5174), .A1(n5707), .B0(n5590), .B1(n5783), .C0(n5536), .C1(n5175), .Y(n1464) );
AO22XLTS U6156 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[23]), .B0(n5711),
.B1(FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1459) );
AO22XLTS U6157 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n5300),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1458) );
BUFX3TS U6158 ( .A(n5510), .Y(n5499) );
INVX3TS U6159 ( .A(n5499), .Y(n5479) );
AO22XLTS U6160 ( .A0(n5479), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n5499),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1457) );
AO22XLTS U6161 ( .A0(n5414), .A1(FPADDSUB_DMP_SFG[23]), .B0(n5375), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1456) );
AO22XLTS U6162 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n5711),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1454) );
AO22XLTS U6163 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n2409),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1453) );
AO22XLTS U6164 ( .A0(n5479), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n5499),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1452) );
AO22XLTS U6165 ( .A0(n5414), .A1(FPADDSUB_DMP_SFG[24]), .B0(n5375), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1451) );
AO22XLTS U6166 ( .A0(n5458), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n5207),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1449) );
AO22XLTS U6167 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n2409),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1448) );
AO22XLTS U6168 ( .A0(n5479), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n5499),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1447) );
AO22XLTS U6169 ( .A0(n5414), .A1(FPADDSUB_DMP_SFG[25]), .B0(n5375), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1446) );
AO22XLTS U6170 ( .A0(n5458), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n5207),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1444) );
AO22XLTS U6171 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n2409),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1443) );
AO22XLTS U6172 ( .A0(n5479), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n5499),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1442) );
AO22XLTS U6173 ( .A0(n5414), .A1(FPADDSUB_DMP_SFG[26]), .B0(n5375), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1441) );
AO22XLTS U6174 ( .A0(n5458), .A1(n2368), .B0(n5207), .B1(
FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1439) );
AO22XLTS U6175 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n5864),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1438) );
AO22XLTS U6176 ( .A0(n5479), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n5499),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1437) );
BUFX4TS U6177 ( .A(n5375), .Y(n5451) );
AO22XLTS U6178 ( .A0(n5414), .A1(FPADDSUB_DMP_SFG[27]), .B0(n5451), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1436) );
AO22XLTS U6179 ( .A0(n5229), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n5207),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1434) );
AO22XLTS U6180 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n2410),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1433) );
AO22XLTS U6181 ( .A0(n5479), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n5499),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1432) );
AO22XLTS U6182 ( .A0(n5414), .A1(FPADDSUB_DMP_SFG[28]), .B0(n5451), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1431) );
AO22XLTS U6183 ( .A0(n5229), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n5207),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1429) );
AO22XLTS U6184 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n2409),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1428) );
AO22XLTS U6185 ( .A0(n5479), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n5499),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1427) );
AO22XLTS U6186 ( .A0(n5414), .A1(FPADDSUB_DMP_SFG[29]), .B0(n5451), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1426) );
BUFX3TS U6187 ( .A(n5294), .Y(n5472) );
AO22XLTS U6188 ( .A0(n5229), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n5207),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1424) );
AO22XLTS U6189 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n5300),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1423) );
AO22XLTS U6190 ( .A0(n5479), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n5499),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1422) );
AO22XLTS U6191 ( .A0(n5414), .A1(FPADDSUB_DMP_SFG[30]), .B0(n5451), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1421) );
OAI222X1TS U6192 ( .A0(n5175), .A1(n5589), .B0(n5539), .B1(n5783), .C0(n5527), .C1(n5174), .Y(n1418) );
OAI222X1TS U6193 ( .A0(n5175), .A1(n5708), .B0(n5591), .B1(n5783), .C0(n5537), .C1(n5174), .Y(n1417) );
OAI222X1TS U6194 ( .A0(n5175), .A1(n5707), .B0(n5588), .B1(n5783), .C0(n5536), .C1(n5174), .Y(n1416) );
AO21XLTS U6195 ( .A0(underflow_flag_addsubt), .A1(n5718), .B0(n5176), .Y(
n1414) );
NOR2X1TS U6196 ( .A(FPADDSUB_DmP_mant_SFG_SWR[24]), .B(n5704), .Y(n5444) );
NAND2X1TS U6197 ( .A(FPADDSUB_DmP_mant_SFG_SWR[23]), .B(n5692), .Y(n5439) );
NOR2X1TS U6198 ( .A(FPADDSUB_DMP_SFG[20]), .B(n5691), .Y(n5429) );
NAND2X1TS U6199 ( .A(FPADDSUB_DmP_mant_SFG_SWR[21]), .B(n5685), .Y(n5425) );
NOR2X1TS U6200 ( .A(FPADDSUB_DMP_SFG[18]), .B(n5676), .Y(n5416) );
NAND2X1TS U6201 ( .A(FPADDSUB_DmP_mant_SFG_SWR[19]), .B(n5640), .Y(n5411) );
NOR2X1TS U6202 ( .A(FPADDSUB_DMP_SFG[16]), .B(n5639), .Y(n5401) );
NAND2X1TS U6203 ( .A(FPADDSUB_DmP_mant_SFG_SWR[17]), .B(n5634), .Y(n5397) );
NOR2X1TS U6204 ( .A(FPADDSUB_DMP_SFG[14]), .B(n5635), .Y(n5389) );
NAND2X1TS U6205 ( .A(FPADDSUB_DmP_mant_SFG_SWR[15]), .B(n5614), .Y(n5385) );
NOR2X1TS U6206 ( .A(FPADDSUB_DMP_SFG[12]), .B(n5624), .Y(n5377) );
NAND2X1TS U6207 ( .A(FPADDSUB_DmP_mant_SFG_SWR[13]), .B(n5607), .Y(n5372) );
NOR2X1TS U6208 ( .A(FPADDSUB_DMP_SFG[10]), .B(n5608), .Y(n5364) );
NAND2X1TS U6209 ( .A(FPADDSUB_DmP_mant_SFG_SWR[11]), .B(n5606), .Y(n5360) );
NOR2X1TS U6210 ( .A(FPADDSUB_DMP_SFG[8]), .B(n5604), .Y(n5351) );
NAND2X1TS U6211 ( .A(FPADDSUB_DmP_mant_SFG_SWR[9]), .B(n5545), .Y(n5347) );
NOR2X1TS U6212 ( .A(FPADDSUB_DMP_SFG[6]), .B(n5600), .Y(n5339) );
NAND2X1TS U6213 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n5544), .Y(n5335) );
NOR2X1TS U6214 ( .A(FPADDSUB_DMP_SFG[4]), .B(n5594), .Y(n5327) );
NAND2X1TS U6215 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n2220), .Y(n5323) );
NOR2X1TS U6216 ( .A(FPADDSUB_DMP_SFG[2]), .B(n2221), .Y(n5315) );
NAND2X1TS U6217 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(n2218), .Y(n5309) );
OAI2BB2X1TS U6218 ( .B0(n5315), .B1(n5317), .A0N(n2221), .A1N(
FPADDSUB_DMP_SFG[2]), .Y(n5322) );
OAI2BB2X1TS U6219 ( .B0(n5327), .B1(n5329), .A0N(n5594), .A1N(
FPADDSUB_DMP_SFG[4]), .Y(n5334) );
OAI2BB2X1TS U6220 ( .B0(n5339), .B1(n5341), .A0N(n5600), .A1N(
FPADDSUB_DMP_SFG[6]), .Y(n5346) );
OAI2BB2X1TS U6221 ( .B0(n5351), .B1(n5353), .A0N(n5604), .A1N(
FPADDSUB_DMP_SFG[8]), .Y(n5359) );
OAI2BB2X1TS U6222 ( .B0(n5429), .B1(n5431), .A0N(n5691), .A1N(
FPADDSUB_DMP_SFG[20]), .Y(n5437) );
AOI21X1TS U6223 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n5704), .B0(n5447),
.Y(n5177) );
NAND2X1TS U6224 ( .A(FPADDSUB_DmP_mant_SFG_SWR[2]), .B(FPADDSUB_DMP_SFG[0]),
.Y(n5310) );
AOI222X4TS U6225 ( .A0(n5595), .A1(n2218), .B0(n5595), .B1(n5310), .C0(n2218), .C1(n5310), .Y(n5316) );
AOI222X4TS U6226 ( .A0(n5321), .A1(n5593), .B0(n5321), .B1(n2220), .C0(n5593), .C1(n2220), .Y(n5328) );
AOI222X4TS U6227 ( .A0(n5333), .A1(n5599), .B0(n5333), .B1(n5544), .C0(n5599), .C1(n5544), .Y(n5340) );
AOI222X4TS U6228 ( .A0(n5345), .A1(n5603), .B0(n5345), .B1(n5545), .C0(n5603), .C1(n5545), .Y(n5352) );
AOI222X4TS U6229 ( .A0(n5358), .A1(n5548), .B0(n5358), .B1(n5606), .C0(n5548), .C1(n5606), .Y(n5365) );
AOI222X4TS U6230 ( .A0(n5370), .A1(n5550), .B0(n5370), .B1(n5607), .C0(n5550), .C1(n5607), .Y(n5378) );
AOI222X4TS U6231 ( .A0(n5383), .A1(n5556), .B0(n5383), .B1(n5614), .C0(n5556), .C1(n5614), .Y(n5390) );
AOI222X4TS U6232 ( .A0(n5395), .A1(n2198), .B0(n5395), .B1(n5634), .C0(n2198), .C1(n5634), .Y(n5402) );
AOI222X4TS U6233 ( .A0(n5409), .A1(n5565), .B0(n5409), .B1(n5640), .C0(n5565), .C1(n5640), .Y(n5417) );
AOI222X4TS U6234 ( .A0(n5423), .A1(n5569), .B0(n5423), .B1(n5685), .C0(n5569), .C1(n5685), .Y(n5430) );
AOI222X4TS U6235 ( .A0(n5436), .A1(n5579), .B0(n5436), .B1(n5692), .C0(n5579), .C1(n5692), .Y(n5446) );
INVX4TS U6236 ( .A(n5357), .Y(n5448) );
OAI32X1TS U6237 ( .A0(n5435), .A1(n5444), .A2(n5177), .B0(n5301), .B1(n5448),
.Y(n5178) );
XOR2X1TS U6238 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .B(n5178), .Y(n5179) );
AOI22X1TS U6239 ( .A0(n5453), .A1(n5179), .B0(n2227), .B1(n5451), .Y(n1412)
);
NAND2X2TS U6240 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n5208) );
NAND2BX2TS U6241 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n5240) );
NAND2X1TS U6242 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n5643), .Y(n5239)
);
OAI22X1TS U6243 ( .A0(n5699), .A1(n5240), .B0(n5580), .B1(n5239), .Y(n5181)
);
NAND3X1TS U6244 ( .A(n2196), .B(FPADDSUB_shift_value_SHT2_EWR[2]), .C(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n5251) );
AOI22X1TS U6245 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n5182), .B0(n2378),
.B1(n2294), .Y(n5185) );
NOR2XLTS U6246 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n5239), .Y(n5183)
);
BUFX4TS U6247 ( .A(n5183), .Y(n5480) );
AOI22X1TS U6248 ( .A0(n2405), .A1(n5480), .B0(FPADDSUB_Data_array_SWR[1]),
.B1(n2291), .Y(n5184) );
OAI211X1TS U6249 ( .A0(n5220), .A1(n2196), .B0(n5185), .C0(n5184), .Y(n5487)
);
NOR2X4TS U6250 ( .A(n2196), .B(n5641), .Y(n5248) );
NAND2X1TS U6251 ( .A(n2305), .B(n5248), .Y(n5524) );
INVX2TS U6252 ( .A(n5524), .Y(n5245) );
NOR2X2TS U6253 ( .A(n5243), .B(n5641), .Y(n5236) );
OAI22X1TS U6254 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5644), .B0(n5519),
.B1(n5190), .Y(n1410) );
AO22XLTS U6255 ( .A0(n5229), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n5207),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1408) );
INVX4TS U6256 ( .A(n5718), .Y(n5255) );
AOI22X1TS U6257 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n5182), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n2293), .Y(n5193) );
AOI22X1TS U6258 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n5480), .B0(
FPADDSUB_Data_array_SWR[7]), .B1(n2290), .Y(n5192) );
OAI211X1TS U6259 ( .A0(n5486), .A1(n2196), .B0(n5193), .C0(n5192), .Y(n5222)
);
AOI211X1TS U6260 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5222), .B0(n5245),
.C0(n5194), .Y(n5509) );
OAI22X1TS U6261 ( .A0(n5255), .A1(n5645), .B0(n5509), .B1(n5190), .Y(n1407)
);
AO22XLTS U6262 ( .A0(n5229), .A1(FPADDSUB_DmP_EXP_EWSW[15]), .B0(n5207),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1405) );
AOI22X1TS U6263 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n5480), .B0(n2378),
.B1(n2290), .Y(n5197) );
AOI22X1TS U6264 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n5182), .B0(n2405),
.B1(n2293), .Y(n5196) );
OAI211X1TS U6265 ( .A0(n2317), .A1(n2196), .B0(n5197), .C0(n5196), .Y(n5408)
);
AOI211X1TS U6266 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5408), .B0(n5245),
.C0(n5199), .Y(n5513) );
OAI22X1TS U6267 ( .A0(n5255), .A1(n5646), .B0(n5513), .B1(n5190), .Y(n1404)
);
AO22XLTS U6268 ( .A0(n5229), .A1(FPADDSUB_DmP_EXP_EWSW[18]), .B0(n5207),
.B1(FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1402) );
OAI21X1TS U6269 ( .A0(n5693), .A1(n5240), .B0(n5208), .Y(n5200) );
AOI22X1TS U6270 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n5480), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n2290), .Y(n5202) );
AOI22X1TS U6271 ( .A0(n2407), .A1(n5182), .B0(FPADDSUB_Data_array_SWR[5]),
.B1(n2293), .Y(n5201) );
OAI211X1TS U6272 ( .A0(n5467), .A1(n2196), .B0(n5202), .C0(n5201), .Y(n5461)
);
AOI211X1TS U6273 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5461), .B0(n5245),
.C0(n5203), .Y(n5517) );
OAI22X1TS U6274 ( .A0(n5255), .A1(n5647), .B0(n5517), .B1(n5190), .Y(n1401)
);
AO22XLTS U6275 ( .A0(n5229), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n5207),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1399) );
AOI22X1TS U6276 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n5480), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2290), .Y(n5205) );
AOI22X1TS U6277 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n5182), .B0(
FPADDSUB_Data_array_SWR[7]), .B1(n2293), .Y(n5204) );
OAI211X1TS U6278 ( .A0(n2318), .A1(n2196), .B0(n5205), .C0(n5204), .Y(n5455)
);
AOI211X1TS U6279 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5455), .B0(n5245),
.C0(n5206), .Y(n5514) );
OAI22X1TS U6280 ( .A0(n5255), .A1(n5648), .B0(n5514), .B1(n5190), .Y(n1398)
);
AO22XLTS U6281 ( .A0(n5229), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n5207),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1396) );
AOI22X1TS U6282 ( .A0(n2404), .A1(n5480), .B0(FPADDSUB_Data_array_SWR[3]),
.B1(n2290), .Y(n5211) );
AOI22X1TS U6283 ( .A0(n2406), .A1(n5182), .B0(FPADDSUB_Data_array_SWR[6]),
.B1(n2293), .Y(n5210) );
OAI211X1TS U6284 ( .A0(n5217), .A1(n2196), .B0(n5211), .C0(n5210), .Y(n5464)
);
AOI211X1TS U6285 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5464), .B0(n5245),
.C0(n5212), .Y(n5515) );
OAI22X1TS U6286 ( .A0(n5255), .A1(n5649), .B0(n5515), .B1(n5190), .Y(n1395)
);
AO22XLTS U6287 ( .A0(n5229), .A1(FPADDSUB_DmP_EXP_EWSW[20]), .B0(n5294),
.B1(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1393) );
AOI22X1TS U6288 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n5182), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2293), .Y(n5214) );
AOI22X1TS U6289 ( .A0(n2407), .A1(n5480), .B0(FPADDSUB_Data_array_SWR[5]),
.B1(n2290), .Y(n5213) );
OAI211X1TS U6290 ( .A0(n5462), .A1(n2196), .B0(n5214), .C0(n5213), .Y(n5219)
);
AOI211X1TS U6291 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5219), .B0(n5245),
.C0(n5215), .Y(n5512) );
OAI22X1TS U6292 ( .A0(n5255), .A1(n5650), .B0(n5512), .B1(n5190), .Y(n1392)
);
AO22XLTS U6293 ( .A0(n5229), .A1(FPADDSUB_DmP_EXP_EWSW[17]), .B0(n5294),
.B1(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1390) );
NAND2X1TS U6294 ( .A(FPADDSUB_left_right_SHT2), .B(n5248), .Y(n5489) );
INVX2TS U6295 ( .A(n5489), .Y(n5468) );
AOI211X1TS U6296 ( .A0(n2412), .A1(n5219), .B0(n5218), .C0(n5468), .Y(n5495)
);
OAI22X1TS U6297 ( .A0(n5255), .A1(n5651), .B0(n5495), .B1(n5190), .Y(n1389)
);
AO22XLTS U6298 ( .A0(n5229), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n5294), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1387) );
AOI211X1TS U6299 ( .A0(n2412), .A1(n5222), .B0(n5221), .C0(n5468), .Y(n5497)
);
OAI22X1TS U6300 ( .A0(n5255), .A1(n5652), .B0(n5497), .B1(n2411), .Y(n1386)
);
AO22XLTS U6301 ( .A0(n5229), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n5294), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1384) );
AOI21X1TS U6302 ( .A0(n2407), .A1(n2294), .B0(n5248), .Y(n5224) );
AOI22X1TS U6303 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n5480), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n2291), .Y(n5223) );
OAI211X1TS U6304 ( .A0(n5693), .A1(n5251), .B0(n5224), .C0(n5223), .Y(n5230)
);
INVX2TS U6305 ( .A(n5480), .Y(n5254) );
NOR2X1TS U6306 ( .A(n5248), .B(n5242), .Y(n5253) );
AOI22X1TS U6307 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n2294), .B0(n2406),
.B1(n2291), .Y(n5225) );
OAI211X1TS U6308 ( .A0(n5694), .A1(n5254), .B0(n5253), .C0(n5225), .Y(n5231)
);
AOI22X1TS U6309 ( .A0(n2413), .A1(n5230), .B0(n5231), .B1(n2412), .Y(n5507)
);
OAI22X1TS U6310 ( .A0(n5255), .A1(n5653), .B0(n5507), .B1(n2411), .Y(n1383)
);
AO22XLTS U6311 ( .A0(n5477), .A1(FPADDSUB_DmP_EXP_EWSW[13]), .B0(n5294),
.B1(FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1381) );
AOI22X1TS U6312 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n5182), .B0(n2404),
.B1(n2294), .Y(n5227) );
AOI22X1TS U6313 ( .A0(n2406), .A1(n5480), .B0(FPADDSUB_Data_array_SWR[6]),
.B1(n2290), .Y(n5226) );
OAI211X1TS U6314 ( .A0(n5459), .A1(n2196), .B0(n5227), .C0(n5226), .Y(n5470)
);
AOI211X1TS U6315 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5470), .B0(n5245),
.C0(n5228), .Y(n5511) );
OAI22X1TS U6316 ( .A0(n5255), .A1(n5654), .B0(n5511), .B1(n5190), .Y(n1380)
);
AO22XLTS U6317 ( .A0(n5477), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n5294),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1378) );
AOI22X1TS U6318 ( .A0(n2413), .A1(n5231), .B0(n5230), .B1(n2412), .Y(n5500)
);
OAI22X1TS U6319 ( .A0(n5255), .A1(n5655), .B0(n5500), .B1(n2411), .Y(n1377)
);
AO22XLTS U6320 ( .A0(n5458), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n5294), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1375) );
AOI22X1TS U6321 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n5480), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n2291), .Y(n5233) );
AOI22X1TS U6322 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n2294), .B0(
FPADDSUB_Data_array_SWR[19]), .B1(n5182), .Y(n5232) );
NAND2X1TS U6323 ( .A(n5233), .B(n5232), .Y(n5246) );
AOI22X1TS U6324 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n5480), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2291), .Y(n5235) );
AOI22X1TS U6325 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n2294), .B0(
FPADDSUB_Data_array_SWR[20]), .B1(n5182), .Y(n5234) );
NAND2X1TS U6326 ( .A(n5235), .B(n5234), .Y(n5247) );
OAI22X1TS U6327 ( .A0(n5255), .A1(n5656), .B0(n5505), .B1(n5190), .Y(n1374)
);
AO22XLTS U6328 ( .A0(n5458), .A1(FPADDSUB_DmP_EXP_EWSW[11]), .B0(n5294),
.B1(FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1372) );
AOI22X1TS U6329 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n5182), .B0(
FPADDSUB_Data_array_SWR[10]), .B1(n2293), .Y(n5238) );
AOI22X1TS U6330 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n5480), .B0(n2405),
.B1(n2290), .Y(n5237) );
OAI211X1TS U6331 ( .A0(n5520), .A1(n2196), .B0(n5238), .C0(n5237), .Y(n5457)
);
OAI22X1TS U6332 ( .A0(n5700), .A1(n5240), .B0(n5581), .B1(n5239), .Y(n5241)
);
AOI211X1TS U6333 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5457), .B0(n5245),
.C0(n5244), .Y(n5508) );
OAI22X1TS U6334 ( .A0(n5255), .A1(n5657), .B0(n5508), .B1(n5190), .Y(n1371)
);
AO22XLTS U6335 ( .A0(n5458), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n5294),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1369) );
OAI22X1TS U6336 ( .A0(n5255), .A1(n5658), .B0(n5504), .B1(n5190), .Y(n1368)
);
AO22XLTS U6337 ( .A0(n5458), .A1(FPADDSUB_DmP_EXP_EWSW[10]), .B0(n5294),
.B1(FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1366) );
AOI21X1TS U6338 ( .A0(n2406), .A1(n2294), .B0(n5248), .Y(n5250) );
AOI22X1TS U6339 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n5480), .B0(n2404),
.B1(n2291), .Y(n5249) );
OAI211X1TS U6340 ( .A0(n5694), .A1(n5251), .B0(n5250), .C0(n5249), .Y(n5465)
);
AOI22X1TS U6341 ( .A0(FPADDSUB_Data_array_SWR[13]), .A1(n2294), .B0(n2407),
.B1(n2291), .Y(n5252) );
OAI211X1TS U6342 ( .A0(n5693), .A1(n5254), .B0(n5253), .C0(n5252), .Y(n5466)
);
AOI22X1TS U6343 ( .A0(n2413), .A1(n5465), .B0(n5466), .B1(n2412), .Y(n5506)
);
OAI22X1TS U6344 ( .A0(n5255), .A1(n5659), .B0(n5506), .B1(n2411), .Y(n1365)
);
AOI22X1TS U6345 ( .A0(n5576), .A1(FPADDSUB_intDY_EWSW[18]), .B0(n5681), .B1(
FPADDSUB_intDY_EWSW[17]), .Y(n5256) );
AOI22X1TS U6346 ( .A0(n5675), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5684), .B1(
FPADDSUB_intDY_EWSW[15]), .Y(n5257) );
AOI22X1TS U6347 ( .A0(n5575), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n5682), .B1(
FPADDSUB_intDY_EWSW[13]), .Y(n5258) );
OAI221XLTS U6348 ( .A0(n5575), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n5682),
.B1(FPADDSUB_intDY_EWSW[13]), .C0(n5258), .Y(n5261) );
AOI22X1TS U6349 ( .A0(n5574), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n5680), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n5259) );
OAI221XLTS U6350 ( .A0(n5574), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n5680),
.B1(FPADDSUB_intDY_EWSW[11]), .C0(n5259), .Y(n5260) );
NOR4X1TS U6351 ( .A(n5263), .B(n5261), .C(n5262), .D(n5260), .Y(n5290) );
AOI22X1TS U6352 ( .A0(n5674), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n5679), .B1(
FPADDSUB_intDY_EWSW[9]), .Y(n5264) );
AOI22X1TS U6353 ( .A0(n5695), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n5578), .B1(
FPADDSUB_intDY_EWSW[29]), .Y(n5265) );
OAI221XLTS U6354 ( .A0(n5695), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n5578),
.B1(FPADDSUB_intDY_EWSW[29]), .C0(n5265), .Y(n5270) );
AOI22X1TS U6355 ( .A0(n5696), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n5677), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n5266) );
AOI22X1TS U6356 ( .A0(n5537), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n5678), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n5267) );
OAI221XLTS U6357 ( .A0(n5537), .A1(FPADDSUB_intDY_EWSW[25]), .B0(n5678),
.B1(FPADDSUB_intDY_EWSW[1]), .C0(n5267), .Y(n5268) );
NOR4X1TS U6358 ( .A(n5271), .B(n5270), .C(n5269), .D(n5268), .Y(n5289) );
AOI22X1TS U6359 ( .A0(n5527), .A1(FPADDSUB_intDY_EWSW[24]), .B0(n5642), .B1(
FPADDSUB_intDY_EWSW[23]), .Y(n5272) );
AOI22X1TS U6360 ( .A0(n5577), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n5683), .B1(
FPADDSUB_intDY_EWSW[21]), .Y(n5273) );
OAI221XLTS U6361 ( .A0(n5577), .A1(FPADDSUB_intDY_EWSW[22]), .B0(n5683),
.B1(FPADDSUB_intDY_EWSW[21]), .C0(n5273), .Y(n5286) );
OAI22X1TS U6362 ( .A0(n5673), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n5570), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n5274) );
AOI221X1TS U6363 ( .A0(n5673), .A1(FPADDSUB_intDY_EWSW[19]), .B0(
FPADDSUB_intDY_EWSW[20]), .B1(n5570), .C0(n5274), .Y(n5275) );
OAI221XLTS U6364 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n5686), .B0(n5698), .B1(
FPADDSUB_intDY_EWSW[7]), .C0(n5275), .Y(n5285) );
OAI22X1TS U6365 ( .A0(n5690), .A1(FPADDSUB_intDY_EWSW[0]), .B0(n5536), .B1(
FPADDSUB_intDY_EWSW[26]), .Y(n5276) );
AOI221X1TS U6366 ( .A0(n5690), .A1(FPADDSUB_intDY_EWSW[0]), .B0(
FPADDSUB_intDY_EWSW[26]), .B1(n5536), .C0(n5276), .Y(n5283) );
OAI22X1TS U6367 ( .A0(n5672), .A1(FPADDSUB_intDY_EWSW[2]), .B0(n5571), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n5277) );
AOI221X1TS U6368 ( .A0(n5672), .A1(FPADDSUB_intDY_EWSW[2]), .B0(
FPADDSUB_intDY_EWSW[3]), .B1(n5571), .C0(n5277), .Y(n5282) );
OAI22X1TS U6369 ( .A0(n5573), .A1(FPADDSUB_intDY_EWSW[4]), .B0(n5689), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n5278) );
OAI22X1TS U6370 ( .A0(n5572), .A1(FPADDSUB_intDY_EWSW[6]), .B0(n5671), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n5279) );
AOI221X1TS U6371 ( .A0(n5572), .A1(FPADDSUB_intDY_EWSW[6]), .B0(
FPADDSUB_intDY_EWSW[8]), .B1(n5671), .C0(n5279), .Y(n5280) );
NAND4XLTS U6372 ( .A(n5283), .B(n5282), .C(n5281), .D(n5280), .Y(n5284) );
NOR4X1TS U6373 ( .A(n5287), .B(n5286), .C(n5284), .D(n5285), .Y(n5288) );
CLKXOR2X2TS U6374 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n5297) );
OAI22X1TS U6375 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(n5292), .B0(n5291), .B1(
n5297), .Y(n5293) );
AOI2BB2XLTS U6376 ( .B0(n5783), .B1(n5293), .A0N(FPADDSUB_SIGN_FLAG_EXP),
.A1N(n5783), .Y(n1364) );
AO22XLTS U6377 ( .A0(n5458), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n5294), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1363) );
AO22XLTS U6378 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n5300), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1362) );
AO22XLTS U6379 ( .A0(n5479), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n5499), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1361) );
AO22XLTS U6380 ( .A0(n5414), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n5451), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1360) );
AO22XLTS U6381 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n5295), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n1359) );
AOI2BB2XLTS U6382 ( .B0(FPADDSUB_intDX_EWSW[31]), .B1(n5297), .A0N(n5297),
.A1N(FPADDSUB_intDX_EWSW[31]), .Y(n5299) );
AO22XLTS U6383 ( .A0(n5783), .A1(n5299), .B0(n5298), .B1(
FPADDSUB_OP_FLAG_EXP), .Y(n1357) );
AO22XLTS U6384 ( .A0(n5458), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n5476), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1356) );
INVX4TS U6385 ( .A(n5300), .Y(n5478) );
AO22XLTS U6386 ( .A0(n5478), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n5300), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1355) );
BUFX3TS U6387 ( .A(n5523), .Y(n5503) );
AO22XLTS U6388 ( .A0(n5503), .A1(n5448), .B0(n5475), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1354) );
AOI21X1TS U6389 ( .A0(n5301), .A1(n5714), .B0(n5448), .Y(n5302) );
AOI22X1TS U6390 ( .A0(n5453), .A1(n5528), .B0(n5697), .B1(n5451), .Y(n1351)
);
NOR2XLTS U6391 ( .A(n5435), .B(n5528), .Y(n5303) );
OAI32X1TS U6392 ( .A0(n2219), .A1(n5435), .A2(n5528), .B0(
FPADDSUB_DmP_mant_SFG_SWR[1]), .B1(n5303), .Y(n5304) );
AOI22X1TS U6393 ( .A0(n5453), .A1(n5304), .B0(n5558), .B1(n5451), .Y(n1350)
);
NAND2X1TS U6394 ( .A(n5448), .B(n5305), .Y(n5307) );
OAI21XLTS U6395 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(FPADDSUB_DMP_SFG[0]), .B0(n5310), .Y(n5306) );
XNOR2X1TS U6396 ( .A(n5307), .B(n5306), .Y(n5308) );
AOI2BB2XLTS U6397 ( .B0(n5453), .B1(n5308), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[2]), .A1N(n5414), .Y(n1349) );
OAI21XLTS U6398 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n2218), .B0(n5309),
.Y(n5313) );
AOI22X1TS U6399 ( .A0(n5448), .A1(n5311), .B0(n5310), .B1(n5435), .Y(n5312)
);
XNOR2X1TS U6400 ( .A(n5313), .B(n5312), .Y(n5314) );
AOI22X1TS U6401 ( .A0(n5453), .A1(n5314), .B0(n5533), .B1(n5451), .Y(n1348)
);
AOI21X1TS U6402 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(n2379), .B0(n5315), .Y(n5319) );
AOI22X1TS U6403 ( .A0(n5448), .A1(n5317), .B0(n5316), .B1(n5712), .Y(n5318)
);
XNOR2X1TS U6404 ( .A(n5319), .B(n5318), .Y(n5320) );
AOI22X1TS U6405 ( .A0(n5453), .A1(n5320), .B0(n5535), .B1(n5451), .Y(n1347)
);
BUFX3TS U6406 ( .A(n5435), .Y(n5445) );
AOI22X1TS U6407 ( .A0(n5448), .A1(n5322), .B0(n5321), .B1(n5445), .Y(n5325)
);
OAI21XLTS U6408 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n2220), .B0(n5323),
.Y(n5324) );
XNOR2X1TS U6409 ( .A(n5325), .B(n5324), .Y(n5326) );
AOI22X1TS U6410 ( .A0(n5453), .A1(n5326), .B0(n5555), .B1(n5451), .Y(n1346)
);
AOI21X1TS U6411 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(n5594), .B0(n5327), .Y(n5331) );
AOI22X1TS U6412 ( .A0(n5448), .A1(n5329), .B0(n5328), .B1(n5445), .Y(n5330)
);
XNOR2X1TS U6413 ( .A(n5331), .B(n5330), .Y(n5332) );
AOI22X1TS U6414 ( .A0(n5453), .A1(n5332), .B0(n5534), .B1(n5375), .Y(n1345)
);
AOI22X1TS U6415 ( .A0(n5448), .A1(n5334), .B0(n5333), .B1(n5445), .Y(n5337)
);
OAI21XLTS U6416 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n5544), .B0(n5335),
.Y(n5336) );
XNOR2X1TS U6417 ( .A(n5337), .B(n5336), .Y(n5338) );
AOI22X1TS U6418 ( .A0(n5453), .A1(n5338), .B0(n5564), .B1(n5375), .Y(n1344)
);
AOI21X1TS U6419 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(n5600), .B0(n5339), .Y(n5343) );
AOI22X1TS U6420 ( .A0(n5448), .A1(n5341), .B0(n5340), .B1(n5445), .Y(n5342)
);
XNOR2X1TS U6421 ( .A(n5343), .B(n5342), .Y(n5344) );
AOI22X1TS U6422 ( .A0(n5453), .A1(n5344), .B0(n5531), .B1(n5451), .Y(n1343)
);
AOI22X1TS U6423 ( .A0(n5448), .A1(n5346), .B0(n5345), .B1(n5445), .Y(n5349)
);
XNOR2X1TS U6424 ( .A(n5349), .B(n5348), .Y(n5350) );
AOI22X1TS U6425 ( .A0(n5453), .A1(n5350), .B0(n5547), .B1(n5451), .Y(n1342)
);
INVX4TS U6426 ( .A(n5421), .Y(n5443) );
AOI21X1TS U6427 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(n5604), .B0(n5351), .Y(n5355) );
AOI22X1TS U6428 ( .A0(n5448), .A1(n5353), .B0(n5352), .B1(n5445), .Y(n5354)
);
XNOR2X1TS U6429 ( .A(n5355), .B(n5354), .Y(n5356) );
AOI22X1TS U6430 ( .A0(n5443), .A1(n5356), .B0(n5584), .B1(n5375), .Y(n1341)
);
INVX4TS U6431 ( .A(n5357), .Y(n5438) );
AOI22X1TS U6432 ( .A0(n5438), .A1(n5359), .B0(n5358), .B1(n5445), .Y(n5362)
);
OAI21XLTS U6433 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n5606), .B0(n5360),
.Y(n5361) );
XNOR2X1TS U6434 ( .A(n5362), .B(n5361), .Y(n5363) );
AOI22X1TS U6435 ( .A0(n5443), .A1(n5363), .B0(n5538), .B1(n5375), .Y(n1340)
);
AOI21X1TS U6436 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(n5608), .B0(n5364), .Y(
n5368) );
AOI22X1TS U6437 ( .A0(n5438), .A1(n5366), .B0(n5365), .B1(n5445), .Y(n5367)
);
XNOR2X1TS U6438 ( .A(n5368), .B(n5367), .Y(n5369) );
AOI22X1TS U6439 ( .A0(n5443), .A1(n5369), .B0(n5562), .B1(n5451), .Y(n1339)
);
AOI22X1TS U6440 ( .A0(n5438), .A1(n5371), .B0(n5370), .B1(n5445), .Y(n5374)
);
XNOR2X1TS U6441 ( .A(n5374), .B(n5373), .Y(n5376) );
AOI22X1TS U6442 ( .A0(n5443), .A1(n5376), .B0(n5585), .B1(n5375), .Y(n1338)
);
AOI21X1TS U6443 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(n5624), .B0(n5377), .Y(
n5381) );
AOI22X1TS U6444 ( .A0(n5438), .A1(n5379), .B0(n5378), .B1(n5445), .Y(n5380)
);
XNOR2X1TS U6445 ( .A(n5381), .B(n5380), .Y(n5382) );
AOI22X1TS U6446 ( .A0(n5443), .A1(n5382), .B0(n5636), .B1(n5421), .Y(n1337)
);
AOI22X1TS U6447 ( .A0(n5438), .A1(n5384), .B0(n5383), .B1(n5435), .Y(n5387)
);
OAI21XLTS U6448 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n5614), .B0(n5385),
.Y(n5386) );
XNOR2X1TS U6449 ( .A(n5387), .B(n5386), .Y(n5388) );
AOI22X1TS U6450 ( .A0(n5443), .A1(n5388), .B0(n5597), .B1(n5421), .Y(n1336)
);
AOI21X1TS U6451 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(n5635), .B0(n5389), .Y(
n5393) );
AOI22X1TS U6452 ( .A0(n5438), .A1(n5391), .B0(n5390), .B1(n5435), .Y(n5392)
);
XNOR2X1TS U6453 ( .A(n5393), .B(n5392), .Y(n5394) );
AOI22X1TS U6454 ( .A0(n5443), .A1(n5394), .B0(n5529), .B1(n5726), .Y(n1335)
);
AOI22X1TS U6455 ( .A0(n5438), .A1(n5396), .B0(n5395), .B1(n5435), .Y(n5399)
);
OAI21XLTS U6456 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n5634), .B0(n5397),
.Y(n5398) );
XNOR2X1TS U6457 ( .A(n5399), .B(n5398), .Y(n5400) );
AOI22X1TS U6458 ( .A0(n5443), .A1(n5400), .B0(n5543), .B1(n5421), .Y(n1334)
);
AOI21X1TS U6459 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(n5639), .B0(n5401), .Y(
n5405) );
AOI22X1TS U6460 ( .A0(n5438), .A1(n5403), .B0(n5402), .B1(n5435), .Y(n5404)
);
XNOR2X1TS U6461 ( .A(n5405), .B(n5404), .Y(n5406) );
AOI22X1TS U6462 ( .A0(n5443), .A1(n5406), .B0(n5625), .B1(n5421), .Y(n1333)
);
AOI211X1TS U6463 ( .A0(n2412), .A1(n5408), .B0(n5407), .C0(n5468), .Y(n5494)
);
OAI22X1TS U6464 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5660), .B0(n5494),
.B1(n2411), .Y(n1331) );
AO22XLTS U6465 ( .A0(n5458), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n5476), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1329) );
AO22XLTS U6466 ( .A0(n5458), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n5476), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1327) );
AO22XLTS U6467 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(n2410),
.B1(FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1326) );
AO22XLTS U6468 ( .A0(n5499), .A1(FPADDSUB_DMP_SFG[3]), .B0(n5479), .B1(
FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1325) );
AOI22X1TS U6469 ( .A0(n5438), .A1(n5410), .B0(n5409), .B1(n5435), .Y(n5413)
);
XNOR2X1TS U6470 ( .A(n5413), .B(n5412), .Y(n5415) );
AOI21X1TS U6471 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(n5676), .B0(n5416), .Y(
n5420) );
AOI22X1TS U6472 ( .A0(n5438), .A1(n5418), .B0(n5417), .B1(n5435), .Y(n5419)
);
XNOR2X1TS U6473 ( .A(n5420), .B(n5419), .Y(n5422) );
AOI22X1TS U6474 ( .A0(n5443), .A1(n5422), .B0(n5626), .B1(n5421), .Y(n1322)
);
AOI22X1TS U6475 ( .A0(n5438), .A1(n5424), .B0(n5423), .B1(n5435), .Y(n5427)
);
XNOR2X1TS U6476 ( .A(n5427), .B(n5426), .Y(n5428) );
AOI22X1TS U6477 ( .A0(n5443), .A1(n5428), .B0(n5560), .B1(n5375), .Y(n1321)
);
AOI21X1TS U6478 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(n5691), .B0(n5429), .Y(
n5433) );
AOI22X1TS U6479 ( .A0(n5438), .A1(n5431), .B0(n5430), .B1(n5435), .Y(n5432)
);
XNOR2X1TS U6480 ( .A(n5433), .B(n5432), .Y(n5434) );
AOI22X1TS U6481 ( .A0(n5443), .A1(n5434), .B0(n5542), .B1(n5375), .Y(n1319)
);
AOI22X1TS U6482 ( .A0(n5438), .A1(n5437), .B0(n5436), .B1(n5435), .Y(n5441)
);
XNOR2X1TS U6483 ( .A(n5441), .B(n5440), .Y(n5442) );
AOI22X1TS U6484 ( .A0(n5443), .A1(n5442), .B0(n2205), .B1(n5375), .Y(n1318)
);
AOI21X1TS U6485 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n5704), .B0(n5444),
.Y(n5450) );
AOI22X1TS U6486 ( .A0(n5448), .A1(n5447), .B0(n5446), .B1(n5445), .Y(n5449)
);
XNOR2X1TS U6487 ( .A(n5450), .B(n5449), .Y(n5452) );
AOI22X1TS U6488 ( .A0(n5453), .A1(n5452), .B0(n5596), .B1(n5451), .Y(n1317)
);
AOI211X1TS U6489 ( .A0(n2412), .A1(n5455), .B0(n5454), .C0(n5468), .Y(n5493)
);
OAI22X1TS U6490 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5661), .B0(n5493),
.B1(n2411), .Y(n1315) );
AO22XLTS U6491 ( .A0(n5458), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n5476), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1313) );
AO22XLTS U6492 ( .A0(n5458), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n5476), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1311) );
AO22XLTS U6493 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(n2410),
.B1(FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1310) );
BUFX4TS U6494 ( .A(n5510), .Y(n5501) );
AO22XLTS U6495 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[2]), .B0(n5479), .B1(
FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1309) );
AOI211X1TS U6496 ( .A0(n2412), .A1(n5457), .B0(n5456), .C0(n5468), .Y(n5498)
);
OAI22X1TS U6497 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5662), .B0(n5498),
.B1(n2411), .Y(n1308) );
AO22XLTS U6498 ( .A0(n5458), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n5476), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1306) );
AO22XLTS U6499 ( .A0(n5458), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n5476), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1304) );
AO22XLTS U6500 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(n2409), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1303) );
INVX2TS U6501 ( .A(n5501), .Y(n5518) );
AO22XLTS U6502 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[7]), .B0(n5518), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1302) );
AOI211X1TS U6503 ( .A0(n2305), .A1(n5461), .B0(n5460), .C0(n5468), .Y(n5491)
);
OAI22X1TS U6504 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5663), .B0(n5491),
.B1(n2411), .Y(n1301) );
AO22XLTS U6505 ( .A0(n5477), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n5476), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1299) );
AO22XLTS U6506 ( .A0(n5477), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n5476), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1297) );
AO22XLTS U6507 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(n5300), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1296) );
AO22XLTS U6508 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[0]), .B0(n5479), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1295) );
AOI211X1TS U6509 ( .A0(n2412), .A1(n5464), .B0(n5463), .C0(n5468), .Y(n5492)
);
OAI22X1TS U6510 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5664), .B0(n5492),
.B1(n2411), .Y(n1294) );
AO22XLTS U6511 ( .A0(n5477), .A1(FPADDSUB_DmP_EXP_EWSW[1]), .B0(n5476), .B1(
FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1292) );
AO22XLTS U6512 ( .A0(n5477), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n5472), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1290) );
AO22XLTS U6513 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(n2410), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1289) );
AO22XLTS U6514 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[1]), .B0(n5518), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1288) );
AOI22X1TS U6515 ( .A0(n2413), .A1(n5466), .B0(n5465), .B1(n2412), .Y(n5502)
);
OAI22X1TS U6516 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5665), .B0(n5502),
.B1(n2411), .Y(n1287) );
AO22XLTS U6517 ( .A0(n5477), .A1(FPADDSUB_DmP_EXP_EWSW[9]), .B0(n5472), .B1(
FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1285) );
AO22XLTS U6518 ( .A0(n5477), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n5472), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1283) );
AO22XLTS U6519 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n5864), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1282) );
AO22XLTS U6520 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[9]), .B0(n5518), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1281) );
AOI211X1TS U6521 ( .A0(n2412), .A1(n5470), .B0(n5469), .C0(n5468), .Y(n5496)
);
OAI22X1TS U6522 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[0]), .A1(n5666), .B0(n5496),
.B1(n2411), .Y(n1280) );
AO22XLTS U6523 ( .A0(n5477), .A1(FPADDSUB_DmP_EXP_EWSW[5]), .B0(n5472), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1278) );
AO22XLTS U6524 ( .A0(n5477), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n5472), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1276) );
AO22XLTS U6525 ( .A0(n5871), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(n5864),
.B1(FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1275) );
AO22XLTS U6526 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[5]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1274) );
AO22XLTS U6527 ( .A0(n5477), .A1(FPADDSUB_DmP_EXP_EWSW[12]), .B0(n5472),
.B1(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1272) );
AO22XLTS U6528 ( .A0(n5477), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n5472),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1270) );
AO22XLTS U6529 ( .A0(n5871), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n5864),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1269) );
AO22XLTS U6530 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[12]), .B0(n5518), .B1(
FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1268) );
AO22XLTS U6531 ( .A0(n5477), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n5472),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1266) );
AO22XLTS U6532 ( .A0(n5871), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n5864),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1265) );
AO22XLTS U6533 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[10]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1264) );
AO22XLTS U6534 ( .A0(n5477), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n5472),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1262) );
AO22XLTS U6535 ( .A0(n5871), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n5864),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1261) );
AO22XLTS U6536 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[14]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1260) );
AO22XLTS U6537 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n5472),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1258) );
AO22XLTS U6538 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n5864),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1257) );
AO22XLTS U6539 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[11]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1256) );
AO22XLTS U6540 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n5472), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1254) );
AO22XLTS U6541 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n2409),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1253) );
AO22XLTS U6542 ( .A0(n5501), .A1(FPADDSUB_DMP_SFG[8]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1252) );
AO22XLTS U6543 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n5473),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1250) );
AO22XLTS U6544 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n2410),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1249) );
AO22XLTS U6545 ( .A0(n5503), .A1(FPADDSUB_DMP_SFG[16]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1248) );
AO22XLTS U6546 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n5473),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1246) );
AO22XLTS U6547 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n2409),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1245) );
AO22XLTS U6548 ( .A0(n5503), .A1(FPADDSUB_DMP_SFG[13]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1244) );
AO22XLTS U6549 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n5473), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1242) );
AO22XLTS U6550 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(n2410),
.B1(FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1241) );
AO22XLTS U6551 ( .A0(n5503), .A1(FPADDSUB_DMP_SFG[6]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1240) );
AO22XLTS U6552 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n5473), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1238) );
AO22XLTS U6553 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(n5300), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1237) );
AO22XLTS U6554 ( .A0(n5503), .A1(FPADDSUB_DMP_SFG[4]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1236) );
AO22XLTS U6555 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n5473),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1234) );
AO22XLTS U6556 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n2410),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1233) );
AO22XLTS U6557 ( .A0(n5503), .A1(FPADDSUB_DMP_SFG[17]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1232) );
AO22XLTS U6558 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n5473),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1230) );
AO22XLTS U6559 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n5864),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1229) );
AO22XLTS U6560 ( .A0(n5503), .A1(FPADDSUB_DMP_SFG[20]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1228) );
AO22XLTS U6561 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n5473),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1226) );
AO22XLTS U6562 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n2410),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1225) );
AO22XLTS U6563 ( .A0(n5503), .A1(FPADDSUB_DMP_SFG[19]), .B0(n5479), .B1(
FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1224) );
AO22XLTS U6564 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n5473),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1222) );
AO22XLTS U6565 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n5864),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1221) );
AO22XLTS U6566 ( .A0(n5503), .A1(FPADDSUB_DMP_SFG[21]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1220) );
AO22XLTS U6567 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n5473),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1218) );
AO22XLTS U6568 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n2410),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1217) );
AO22XLTS U6569 ( .A0(n5503), .A1(FPADDSUB_DMP_SFG[18]), .B0(n5518), .B1(
FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1216) );
AO22XLTS U6570 ( .A0(n5474), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n5473),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1214) );
AO22XLTS U6571 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n5864),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1213) );
AO22XLTS U6572 ( .A0(n5523), .A1(FPADDSUB_DMP_SFG[15]), .B0(n5475), .B1(
FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1212) );
AO22XLTS U6573 ( .A0(n5477), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n5476),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1210) );
AO22XLTS U6574 ( .A0(n5478), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n2409),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1209) );
AO22XLTS U6575 ( .A0(n5510), .A1(FPADDSUB_DMP_SFG[22]), .B0(n5479), .B1(
FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1208) );
AOI22X1TS U6576 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n5480), .B0(
FPADDSUB_Data_array_SWR[0]), .B1(n2291), .Y(n5482) );
AOI22X1TS U6577 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n5182), .B0(
FPADDSUB_Data_array_SWR[4]), .B1(n2294), .Y(n5481) );
OAI211X1TS U6578 ( .A0(n5484), .A1(n2196), .B0(n5482), .C0(n5481), .Y(n5521)
);
AOI2BB2XLTS U6579 ( .B0(n2305), .B1(n5521), .A0N(n5520), .A1N(n5216), .Y(
n5485) );
INVX3TS U6580 ( .A(n5523), .Y(n5525) );
AOI32X1TS U6581 ( .A0(n5485), .A1(n5525), .A2(n5489), .B0(n5528), .B1(n5523),
.Y(n1207) );
AOI2BB2XLTS U6582 ( .B0(n2412), .B1(n5487), .A0N(n5486), .A1N(n5216), .Y(
n5490) );
AOI32X1TS U6583 ( .A0(n5490), .A1(n5525), .A2(n5489), .B0(n2219), .B1(n5523),
.Y(n1206) );
AOI2BB2XLTS U6584 ( .B0(n5525), .B1(n5491), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[2]), .A1N(n5518), .Y(n1205) );
AOI22X1TS U6585 ( .A0(n5525), .A1(n5492), .B0(n5595), .B1(n5503), .Y(n1204)
);
AOI22X1TS U6586 ( .A0(n5525), .A1(n5493), .B0(n2379), .B1(n5503), .Y(n1203)
);
INVX3TS U6587 ( .A(n5523), .Y(n5516) );
AOI22X1TS U6588 ( .A0(n5516), .A1(n5494), .B0(n5593), .B1(n5501), .Y(n1202)
);
AOI22X1TS U6589 ( .A0(n5525), .A1(n5495), .B0(n5594), .B1(n5499), .Y(n1201)
);
AOI22X1TS U6590 ( .A0(n5525), .A1(n5496), .B0(n5599), .B1(n5501), .Y(n1200)
);
AOI22X1TS U6591 ( .A0(n5525), .A1(n5497), .B0(n5600), .B1(n5510), .Y(n1199)
);
AOI22X1TS U6592 ( .A0(n5525), .A1(n5498), .B0(n5603), .B1(n5510), .Y(n1198)
);
AOI22X1TS U6593 ( .A0(n5516), .A1(n5500), .B0(n5604), .B1(n5499), .Y(n1197)
);
AOI22X1TS U6594 ( .A0(n5525), .A1(n5502), .B0(n5548), .B1(n5501), .Y(n1196)
);
AOI22X1TS U6595 ( .A0(n5516), .A1(n5504), .B0(n5608), .B1(n5503), .Y(n1195)
);
AOI22X1TS U6596 ( .A0(n5516), .A1(n5505), .B0(n5550), .B1(n5510), .Y(n1194)
);
AOI22X1TS U6597 ( .A0(n5516), .A1(n5506), .B0(n5624), .B1(n5510), .Y(n1193)
);
AOI22X1TS U6598 ( .A0(n5516), .A1(n5507), .B0(n5556), .B1(n5523), .Y(n1192)
);
AOI22X1TS U6599 ( .A0(n5516), .A1(n5508), .B0(n5635), .B1(n5510), .Y(n1191)
);
AOI22X1TS U6600 ( .A0(n5516), .A1(n5509), .B0(n2198), .B1(n5510), .Y(n1190)
);
AOI22X1TS U6601 ( .A0(n5516), .A1(n5511), .B0(n5639), .B1(n5510), .Y(n1189)
);
AOI22X1TS U6602 ( .A0(n5516), .A1(n5512), .B0(n5565), .B1(n5510), .Y(n1188)
);
AOI22X1TS U6603 ( .A0(n5516), .A1(n5513), .B0(n5676), .B1(n5523), .Y(n1187)
);
AOI22X1TS U6604 ( .A0(n5516), .A1(n5514), .B0(n5569), .B1(n5523), .Y(n1186)
);
AOI22X1TS U6605 ( .A0(n5516), .A1(n5515), .B0(n5691), .B1(n5510), .Y(n1185)
);
AOI22X1TS U6606 ( .A0(n5525), .A1(n5517), .B0(n5579), .B1(n5523), .Y(n1184)
);
AOI2BB2XLTS U6607 ( .B0(n5525), .B1(n5519), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[24]), .A1N(n5518), .Y(n1183) );
AOI2BB2XLTS U6608 ( .B0(n2413), .B1(n5521), .A0N(n5520), .A1N(n5186), .Y(
n5526) );
AOI32X1TS U6609 ( .A0(n5526), .A1(n5525), .A2(n5524), .B0(n5714), .B1(n5523),
.Y(n1182) );
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_common.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Block for logic common to all rank machines. Contains
// a clock prescaler, and arbiters for refresh and periodic
// read functions.
`timescale 1 ps / 1 ps
module mig_7series_v2_0_rank_common #
(
parameter TCQ = 100,
parameter DRAM_TYPE = "DDR3",
parameter MAINT_PRESCALER_DIV = 40,
parameter nBANK_MACHS = 4,
parameter nCKESR = 4,
parameter nCK_PER_CLK = 2,
parameter PERIODIC_RD_TIMER_DIV = 20,
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter REFRESH_TIMER_DIV = 39,
parameter ZQ_TIMER_DIV = 640000
)
(/*AUTOARG*/
// Outputs
maint_prescaler_tick_r, refresh_tick, maint_zq_r, maint_sre_r, maint_srx_r,
maint_req_r, maint_rank_r, clear_periodic_rd_request, periodic_rd_r,
periodic_rd_rank_r, app_ref_ack, app_zq_ack, app_sr_active, maint_ref_zq_wip,
// Inputs
clk, rst, init_calib_complete, app_ref_req, app_zq_req, app_sr_req,
insert_maint_r1, refresh_request, maint_wip_r, slot_0_present, slot_1_present,
periodic_rd_request, periodic_rd_ack_r
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input clk;
input rst;
// Maintenance and periodic read prescaler. Nominally 200 nS.
localparam ONE = 1;
localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1);
input init_calib_complete;
reg maint_prescaler_tick_r_lcl;
generate
begin : maint_prescaler
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r;
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns;
wire maint_prescaler_tick_ns =
(maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]);
always @(/*AS*/init_calib_complete or maint_prescaler_r
or maint_prescaler_tick_ns) begin
maint_prescaler_ns = maint_prescaler_r;
if (~init_calib_complete || maint_prescaler_tick_ns)
maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0];
else if (|maint_prescaler_r)
maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0];
end
always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns;
always @(posedge clk) maint_prescaler_tick_r_lcl <=
#TCQ maint_prescaler_tick_ns;
end
endgenerate
output wire maint_prescaler_tick_r;
assign maint_prescaler_tick_r = maint_prescaler_tick_r_lcl;
// Refresh timebase. Nominically 7800 nS.
localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER_DIV + /*idle*/ 1);
wire refresh_tick_lcl;
generate
begin : refresh_timer
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_r;
reg [REFRESH_TIMER_WIDTH-1:0] refresh_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or refresh_tick_lcl or refresh_timer_r) begin
refresh_timer_ns = refresh_timer_r;
if (~init_calib_complete || refresh_tick_lcl)
refresh_timer_ns = REFRESH_TIMER_DIV[REFRESH_TIMER_WIDTH-1:0];
else if (|refresh_timer_r && maint_prescaler_tick_r_lcl)
refresh_timer_ns =
refresh_timer_r - ONE[REFRESH_TIMER_WIDTH-1:0];
end
always @(posedge clk) refresh_timer_r <= #TCQ refresh_timer_ns;
assign refresh_tick_lcl = (refresh_timer_r ==
ONE[REFRESH_TIMER_WIDTH-1:0]) && maint_prescaler_tick_r_lcl;
end
endgenerate
output wire refresh_tick;
assign refresh_tick = refresh_tick_lcl;
// ZQ timebase. Nominally 128 mS
localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1);
input app_zq_req;
input insert_maint_r1;
reg maint_zq_r_lcl;
reg zq_request = 1'b0;
generate
if (DRAM_TYPE == "DDR3") begin : zq_cntrl
reg zq_tick = 1'b0;
if (ZQ_TIMER_DIV !=0) begin : zq_timer
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r;
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r_lcl
or zq_tick or zq_timer_r) begin
zq_timer_ns = zq_timer_r;
if (~init_calib_complete || zq_tick)
zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0];
else if (|zq_timer_r && maint_prescaler_tick_r_lcl)
zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns;
always @(/*AS*/maint_prescaler_tick_r_lcl or zq_timer_r)
zq_tick = (zq_timer_r ==
ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick_r_lcl);
end // zq_timer
// ZQ request. Set request with timer tick, and when exiting PHY init. Never
// request if ZQ_TIMER_DIV == 0.
begin : zq_request_logic
wire zq_clears_zq_request = insert_maint_r1 && maint_zq_r_lcl;
reg zq_request_r;
wire zq_request_ns = ~rst && (DRAM_TYPE == "DDR3") &&
((~init_calib_complete && (ZQ_TIMER_DIV != 0)) ||
(zq_request_r && ~zq_clears_zq_request) ||
zq_tick ||
(app_zq_req && init_calib_complete));
always @(posedge clk) zq_request_r <= #TCQ zq_request_ns;
always @(/*AS*/init_calib_complete or zq_request_r)
zq_request = init_calib_complete && zq_request_r;
end // zq_request_logic
end
endgenerate
// Self-refresh control
localparam nCKESR_CLKS = (nCKESR / nCK_PER_CLK) + (nCKESR % nCK_PER_CLK ? 1 : 0);
localparam CKESR_TIMER_WIDTH = clogb2(nCKESR_CLKS + 1);
input app_sr_req;
reg maint_sre_r_lcl;
reg maint_srx_r_lcl;
reg sre_request = 1'b0;
wire inhbt_srx;
generate begin : sr_cntrl
// SRE request. Set request with user request.
begin : sre_request_logic
reg sre_request_r;
wire sre_clears_sre_request = insert_maint_r1 && maint_sre_r_lcl;
wire sre_request_ns = ~rst && ((sre_request_r && ~sre_clears_sre_request)
|| (app_sr_req && init_calib_complete && ~maint_sre_r_lcl));
always @(posedge clk) sre_request_r <= #TCQ sre_request_ns;
always @(init_calib_complete or sre_request_r)
sre_request = init_calib_complete && sre_request_r;
end // sre_request_logic
// CKESR timer: Self-Refresh must be maintained for a minimum of tCKESR
begin : ckesr_timer
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_r = {CKESR_TIMER_WIDTH{1'b0}};
reg [CKESR_TIMER_WIDTH-1:0] ckesr_timer_ns = {CKESR_TIMER_WIDTH{1'b0}};
always @(insert_maint_r1 or ckesr_timer_r or maint_sre_r_lcl) begin
ckesr_timer_ns = ckesr_timer_r;
if (insert_maint_r1 && maint_sre_r_lcl)
ckesr_timer_ns = nCKESR_CLKS[CKESR_TIMER_WIDTH-1:0];
else if(|ckesr_timer_r)
ckesr_timer_ns = ckesr_timer_r - ONE[CKESR_TIMER_WIDTH-1:0];
end
always @(posedge clk) ckesr_timer_r <= #TCQ ckesr_timer_ns;
assign inhbt_srx = |ckesr_timer_r;
end // ckesr_timer
end
endgenerate
// DRAM maintenance operations of refresh and ZQ calibration, and self-refresh
// DRAM maintenance operations and self-refresh have their own channel in the
// queue. There is also a single, very simple bank machine
// dedicated to these operations. Its assumed that the
// maintenance operations can be completed quickly enough
// to avoid any queuing.
//
// ZQ, refresh and self-refresh requests share a channel into controller.
// Self-refresh is appended to the uppermost bit of the request bus and ZQ is
// appended just below that.
input[RANKS-1:0] refresh_request;
input maint_wip_r;
reg maint_req_r_lcl;
reg [RANK_WIDTH-1:0] maint_rank_r_lcl;
input [7:0] slot_0_present;
input [7:0] slot_1_present;
generate
begin : maintenance_request
// Maintenance request pipeline.
reg upd_last_master_r;
reg new_maint_rank_r;
wire maint_busy = upd_last_master_r || new_maint_rank_r ||
maint_req_r_lcl || maint_wip_r;
wire [RANKS+1:0] maint_request = {sre_request, zq_request, refresh_request[RANKS-1:0]};
wire upd_last_master_ns = |maint_request && ~maint_busy;
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
always @(posedge clk) new_maint_rank_r <= #TCQ upd_last_master_r;
always @(posedge clk) maint_req_r_lcl <= #TCQ new_maint_rank_r;
// Arbitrate maintenance requests.
wire [RANKS+1:0] maint_grant_ns;
wire [RANKS+1:0] maint_grant_r;
mig_7series_v2_0_round_robin_arb #
(.WIDTH (RANKS+2))
maint_arb0
(.grant_ns (maint_grant_ns),
.grant_r (maint_grant_r),
.upd_last_master (upd_last_master_r),
.current_master (maint_grant_r),
.req (maint_request),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// Look at arbitration results. Decide if ZQ, refresh or self-refresh.
// If refresh select the maintenance rank from the winning rank controller.
// If ZQ or self-refresh, generate a sequence of rank numbers corresponding to
// slots populated maint_rank_r is not used for comparisons in the queue for ZQ
// or self-refresh requests. The bank machine will enable CS for the number of
// states equal to the the number of occupied slots. This will produce a
// command to every occupied slot, but not in any particular order.
wire [7:0] present = slot_0_present | slot_1_present;
integer i;
reg [RANK_WIDTH-1:0] maint_rank_ns;
wire maint_zq_ns = ~rst && (upd_last_master_r
? maint_grant_r[RANKS]
: maint_zq_r_lcl);
wire maint_srx_ns = ~rst && (maint_sre_r_lcl
? ~app_sr_req & ~inhbt_srx
: maint_srx_r_lcl && upd_last_master_r
? maint_grant_r[RANKS+1]
: maint_srx_r_lcl);
wire maint_sre_ns = ~rst && (upd_last_master_r
? maint_grant_r[RANKS+1]
: maint_sre_r_lcl && ~maint_srx_ns);
always @(/*AS*/maint_grant_r or maint_rank_r_lcl or maint_zq_ns
or maint_sre_ns or maint_srx_ns or present or rst
or upd_last_master_r) begin
if (rst) maint_rank_ns = {RANK_WIDTH{1'b0}};
else begin
maint_rank_ns = maint_rank_r_lcl;
if (maint_zq_ns || maint_sre_ns || maint_srx_ns) begin
maint_rank_ns = maint_rank_r_lcl + ONE[RANK_WIDTH-1:0];
for (i=0; i<8; i=i+1)
if (~present[maint_rank_ns])
maint_rank_ns = maint_rank_ns + ONE[RANK_WIDTH-1:0];
end
else
if (upd_last_master_r)
for (i=0; i<RANKS; i=i+1)
if (maint_grant_r[i]) maint_rank_ns = i[RANK_WIDTH-1:0];
end
end
always @(posedge clk) maint_rank_r_lcl <= #TCQ maint_rank_ns;
always @(posedge clk) maint_zq_r_lcl <= #TCQ maint_zq_ns;
always @(posedge clk) maint_sre_r_lcl <= #TCQ maint_sre_ns;
always @(posedge clk) maint_srx_r_lcl <= #TCQ maint_srx_ns;
end // block: maintenance_request
endgenerate
output wire maint_zq_r;
assign maint_zq_r = maint_zq_r_lcl;
output wire maint_sre_r;
assign maint_sre_r = maint_sre_r_lcl;
output wire maint_srx_r;
assign maint_srx_r = maint_srx_r_lcl;
output wire maint_req_r;
assign maint_req_r = maint_req_r_lcl;
output wire [RANK_WIDTH-1:0] maint_rank_r;
assign maint_rank_r = maint_rank_r_lcl;
// Indicate whether self-refresh is active or not.
output app_sr_active;
reg app_sr_active_r;
wire app_sr_active_ns =
insert_maint_r1 ? maint_sre_r && ~maint_srx_r : app_sr_active_r;
always @(posedge clk) app_sr_active_r <= #TCQ app_sr_active_ns;
assign app_sr_active = app_sr_active_r;
// Acknowledge user REF and ZQ Requests
input app_ref_req;
output app_ref_ack;
wire app_ref_ack_ns;
wire app_ref_ns;
reg app_ref_ack_r = 1'b0;
reg app_ref_r = 1'b0;
assign app_ref_ns = init_calib_complete && (app_ref_req || app_ref_r && |refresh_request);
assign app_ref_ack_ns = app_ref_r && ~|refresh_request;
always @(posedge clk) app_ref_r <= #TCQ app_ref_ns;
always @(posedge clk) app_ref_ack_r <= #TCQ app_ref_ack_ns;
assign app_ref_ack = app_ref_ack_r;
output app_zq_ack;
wire app_zq_ack_ns;
wire app_zq_ns;
reg app_zq_ack_r = 1'b0;
reg app_zq_r = 1'b0;
assign app_zq_ns = init_calib_complete && (app_zq_req || app_zq_r && zq_request);
assign app_zq_ack_ns = app_zq_r && ~zq_request;
always @(posedge clk) app_zq_r <= #TCQ app_zq_ns;
always @(posedge clk) app_zq_ack_r <= #TCQ app_zq_ack_ns;
assign app_zq_ack = app_zq_ack_r;
// Periodic reads to maintain PHY alignment.
// Demand insertion of periodic read as soon as
// possible. Since the is a single rank, bank compare mechanism
// must be used, periodic reads must be forced in at the
// expense of not accepting a normal request.
input [RANKS-1:0] periodic_rd_request;
reg periodic_rd_r_lcl;
reg [RANK_WIDTH-1:0] periodic_rd_rank_r_lcl;
input periodic_rd_ack_r;
output wire [RANKS-1:0] clear_periodic_rd_request;
output wire periodic_rd_r;
output wire [RANK_WIDTH-1:0] periodic_rd_rank_r;
generate
// This is not needed in 7-Series and should remain disabled
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin : periodic_read_request
// Maintenance request pipeline.
reg periodic_rd_r_cnt;
wire int_periodic_rd_ack_r = (periodic_rd_ack_r && periodic_rd_r_cnt);
reg upd_last_master_r;
wire periodic_rd_busy = upd_last_master_r || periodic_rd_r_lcl;
wire upd_last_master_ns =
init_calib_complete && (|periodic_rd_request && ~periodic_rd_busy);
always @(posedge clk) upd_last_master_r <= #TCQ upd_last_master_ns;
wire periodic_rd_ns = init_calib_complete &&
(upd_last_master_r || (periodic_rd_r_lcl && ~int_periodic_rd_ack_r));
always @(posedge clk) periodic_rd_r_lcl <= #TCQ periodic_rd_ns;
always @(posedge clk) begin
if (rst) periodic_rd_r_cnt <= #TCQ 1'b0;
else if (periodic_rd_r_lcl && periodic_rd_ack_r)
periodic_rd_r_cnt <= ~periodic_rd_r_cnt;
end
// Arbitrate periodic read requests.
wire [RANKS-1:0] periodic_rd_grant_ns;
reg [RANKS-1:0] periodic_rd_grant_r;
mig_7series_v2_0_round_robin_arb #
(.WIDTH (RANKS))
periodic_rd_arb0
(.grant_ns (periodic_rd_grant_ns[RANKS-1:0]),
.grant_r (),
.upd_last_master (upd_last_master_r),
.current_master (periodic_rd_grant_r[RANKS-1:0]),
.req (periodic_rd_request[RANKS-1:0]),
.disable_grant (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
always @(posedge clk) periodic_rd_grant_r = upd_last_master_ns
? periodic_rd_grant_ns
: periodic_rd_grant_r;
// Encode and set periodic read rank into periodic_rd_rank_r.
integer i;
reg [RANK_WIDTH-1:0] periodic_rd_rank_ns;
always @(/*AS*/periodic_rd_grant_r or periodic_rd_rank_r_lcl
or upd_last_master_r) begin
periodic_rd_rank_ns = periodic_rd_rank_r_lcl;
if (upd_last_master_r)
for (i=0; i<RANKS; i=i+1)
if (periodic_rd_grant_r[i])
periodic_rd_rank_ns = i[RANK_WIDTH-1:0];
end
always @(posedge clk) periodic_rd_rank_r_lcl <=
#TCQ periodic_rd_rank_ns;
// Once the request is dropped in the queue, it might be a while before it
// emerges. Can't clear the request based on seeing the read issued.
// Need to clear the request as soon as its made it into the queue.
assign clear_periodic_rd_request =
periodic_rd_grant_r & {RANKS{periodic_rd_ack_r}};
assign periodic_rd_r = periodic_rd_r_lcl;
assign periodic_rd_rank_r = periodic_rd_rank_r_lcl;
end else begin
// Disable periodic reads
assign clear_periodic_rd_request = {RANKS{1'b0}};
assign periodic_rd_r = 1'b0;
assign periodic_rd_rank_r = {RANK_WIDTH{1'b0}};
end // block: periodic_read_request
endgenerate
// Indicate that a refresh is in progress. The PHY will use this to schedule
// tap adjustments during idle bus time
reg maint_ref_zq_wip_r = 1'b0;
output maint_ref_zq_wip;
always @(posedge clk)
if(rst)
maint_ref_zq_wip_r <= #TCQ 1'b0;
else if((zq_request || |refresh_request) && insert_maint_r1)
maint_ref_zq_wip_r <= #TCQ 1'b1;
else if(~maint_wip_r)
maint_ref_zq_wip_r <= #TCQ 1'b0;
assign maint_ref_zq_wip = maint_ref_zq_wip_r;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:15:39 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, intAS, SIGN_FLAG_EXP, OP_FLAG_EXP, ZERO_FLAG_EXP,
SIGN_FLAG_SHT1, OP_FLAG_SHT1, ZERO_FLAG_SHT1, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
OP_FLAG_SFG, ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756,
n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767,
n768, n769, n770, n771, n772, n773, n774, n776, n777, n778, n779,
n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790,
n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801,
n802, n803, n804, n805, n806, n807, n808, n809, n810, n811, n812,
n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823,
n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834,
n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845,
n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856,
n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867,
n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878,
DP_OP_15J20_123_3116_n8, DP_OP_15J20_123_3116_n7,
DP_OP_15J20_123_3116_n6, DP_OP_15J20_123_3116_n5,
DP_OP_15J20_123_3116_n4, intadd_12_B_12_, intadd_12_B_11_,
intadd_12_B_10_, intadd_12_B_9_, intadd_12_B_8_, intadd_12_B_7_,
intadd_12_B_6_, intadd_12_B_5_, intadd_12_B_4_, intadd_12_B_3_,
intadd_12_B_2_, intadd_12_B_1_, intadd_12_B_0_, intadd_12_CI,
intadd_12_SUM_12_, intadd_12_SUM_11_, intadd_12_SUM_10_,
intadd_12_SUM_9_, intadd_12_SUM_8_, intadd_12_SUM_7_,
intadd_12_SUM_6_, intadd_12_SUM_5_, intadd_12_SUM_4_,
intadd_12_SUM_3_, intadd_12_SUM_2_, intadd_12_SUM_1_,
intadd_12_SUM_0_, intadd_12_n13, intadd_12_n12, intadd_12_n11,
intadd_12_n10, intadd_12_n9, intadd_12_n8, intadd_12_n7, intadd_12_n6,
intadd_12_n5, intadd_12_n4, intadd_12_n3, intadd_12_n2, intadd_12_n1,
intadd_13_A_2_, intadd_13_A_1_, intadd_13_B_2_, intadd_13_B_0_,
intadd_13_CI, intadd_13_SUM_2_, intadd_13_SUM_1_, intadd_13_SUM_0_,
intadd_13_n3, intadd_13_n2, intadd_13_n1, intadd_14_A_2_,
intadd_14_A_1_, intadd_14_B_2_, intadd_14_B_0_, intadd_14_CI,
intadd_14_SUM_2_, intadd_14_SUM_1_, intadd_14_SUM_0_, intadd_14_n3,
intadd_14_n2, intadd_14_n1, n879, n880, n881, n883, n884, n885, n886,
n887, n888, n889, n890, n891, n892, n893, n894, n895, n896, n897,
n898, n899, n900, n901, n902, n903, n904, n905, n906, n907, n908,
n909, n910, n911, n912, n913, n914, n915, n916, n917, n918, n919,
n920, n921, n922, n923, n924, n925, n926, n927, n928, n929, n930,
n931, n932, n933, n934, n935, n936, n937, n938, n939, n940, n941,
n942, n943, n944, n945, n946, n947, n948, n949, n950, n951, n952,
n953, n954, n955, n956, n957, n958, n959, n960, n961, n962, n963,
n964, n965, n966, n967, n968, n969, n970, n971, n972, n973, n974,
n975, n976, n977, n978, n979, n980, n981, n982, n983, n984, n985,
n986, n987, n988, n989, n990, n991, n992, n993, n994, n995, n996,
n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006,
n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016,
n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026,
n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036,
n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046,
n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056,
n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066,
n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076,
n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086,
n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096,
n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146,
n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156,
n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166,
n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176,
n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186,
n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196,
n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206,
n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216,
n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226,
n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236,
n1237, n1238, n1239, n1240, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1342, n1343, n1344, n1345, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503,
n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513,
n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523,
n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533,
n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543,
n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553,
n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563,
n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573,
n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1619, n1620, n1621;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:1] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [21:0] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n873), .CK(clk), .RN(n1594), .QN(
n890) );
DFFRXLTS inst_ShiftRegister_Q_reg_1_ ( .D(n871), .CK(clk), .RN(n1587), .Q(
Shift_reg_FLAGS_7[1]) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n869), .CK(clk), .RN(n1591),
.QN(n885) );
DFFRXLTS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n836), .CK(clk), .RN(n1586), .Q(
left_right_SHT2) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1588),
.Q(ready) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n772), .CK(clk), .RN(n1592),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n771), .CK(clk), .RN(n881), .Q(
Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n770), .CK(clk), .RN(n1590),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n769), .CK(clk), .RN(n1593),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n768), .CK(clk), .RN(n1601), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n767), .CK(clk), .RN(n1604), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n766), .CK(clk), .RN(n1596), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n765), .CK(clk), .RN(n1613), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n764), .CK(clk), .RN(n1599), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n763), .CK(clk), .RN(n1600), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n762), .CK(clk), .RN(n1595), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n761), .CK(clk), .RN(n1600), .Q(
final_result_ieee[30]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n760), .CK(clk), .RN(n1592), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n759), .CK(clk), .RN(n1602), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n758), .CK(clk), .RN(n1594), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n757), .CK(clk), .RN(n881), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n756), .CK(clk), .RN(n1590), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n755), .CK(clk), .RN(n1593), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n754), .CK(clk), .RN(n1592), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n753), .CK(clk), .RN(n1586), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n752), .CK(clk), .RN(n881), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n751), .CK(clk), .RN(n1586), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n750), .CK(clk), .RN(n1594), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n749), .CK(clk), .RN(n1587), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n748), .CK(clk), .RN(n1589), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n747), .CK(clk), .RN(n1591), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n746), .CK(clk), .RN(n1588), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n745), .CK(clk), .RN(n1586), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n744), .CK(clk), .RN(n1594), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n743), .CK(clk), .RN(n1587), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n742), .CK(clk), .RN(n1589), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n741), .CK(clk), .RN(n1591), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n740), .CK(clk), .RN(n1588), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n739), .CK(clk), .RN(n1614), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n738), .CK(clk), .RN(n1600), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n733), .CK(clk), .RN(n1614), .QN(n892)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n732), .CK(clk), .RN(n1599), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n731), .CK(clk), .RN(n1613), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n730), .CK(clk), .RN(n1600), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n729), .CK(clk), .RN(n1595), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n728), .CK(clk), .RN(n1600), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n727), .CK(clk), .RN(n1614), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n726), .CK(clk), .RN(n1595), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n725), .CK(clk), .RN(n1600), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n723), .CK(clk), .RN(n1599), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n722), .CK(clk), .RN(n1613), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n720), .CK(clk), .RN(n1596), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n719), .CK(clk), .RN(n1604), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n717), .CK(clk), .RN(n1600), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n716), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n715), .CK(clk), .RN(n1597), .Q(
DMP_SFG[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n714), .CK(clk), .RN(n1609), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n713), .CK(clk), .RN(n1615), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n712), .CK(clk), .RN(n1597), .Q(
DMP_SFG[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n711), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n710), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n708), .CK(clk), .RN(n1615), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n707), .CK(clk), .RN(n1615), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n705), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n704), .CK(clk), .RN(n1602), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n703), .CK(clk), .RN(n1601), .Q(
DMP_SFG[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n702), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n701), .CK(clk), .RN(n1602), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n700), .CK(clk), .RN(n1597), .Q(
DMP_SFG[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n699), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n698), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n696), .CK(clk), .RN(n1598), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n695), .CK(clk), .RN(n1597), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n693), .CK(clk), .RN(n1601), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n692), .CK(clk), .RN(n1602), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n690), .CK(clk), .RN(n1613), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n689), .CK(clk), .RN(n1596), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n687), .CK(clk), .RN(n1604), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n686), .CK(clk), .RN(n1614), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n684), .CK(clk), .RN(n1595), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n683), .CK(clk), .RN(n1600), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n681), .CK(clk), .RN(n1599), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n680), .CK(clk), .RN(n1613), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n678), .CK(clk), .RN(n1599), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n677), .CK(clk), .RN(n1614), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n675), .CK(clk), .RN(n1595), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n674), .CK(clk), .RN(n1614), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n672), .CK(clk), .RN(n1596), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n671), .CK(clk), .RN(n1604), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n669), .CK(clk), .RN(n1613), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n668), .CK(clk), .RN(n1599), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n666), .CK(clk), .RN(n1615), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n665), .CK(clk), .RN(n1598), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n663), .CK(clk), .RN(n1609), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n662), .CK(clk), .RN(n1598), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n660), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n659), .CK(clk), .RN(n1598), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n657), .CK(clk), .RN(n1609), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n656), .CK(clk), .RN(n1609), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n655), .CK(clk), .RN(n1615), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n654), .CK(clk), .RN(n1598), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n652), .CK(clk), .RN(n1602), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n651), .CK(clk), .RN(n1609), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n650), .CK(clk), .RN(n1615), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n649), .CK(clk), .RN(n1615), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n647), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n646), .CK(clk), .RN(n1601), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n645), .CK(clk), .RN(n1601), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n644), .CK(clk), .RN(n1615), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n642), .CK(clk), .RN(n1597), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n641), .CK(clk), .RN(n1615), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n640), .CK(clk), .RN(n941), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n639), .CK(clk), .RN(n1603), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n637), .CK(clk), .RN(n1606), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n636), .CK(clk), .RN(n1610), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n635), .CK(clk), .RN(n940), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n634), .CK(clk), .RN(n940), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n632), .CK(clk), .RN(n941), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n631), .CK(clk), .RN(n1603), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n630), .CK(clk), .RN(n1606), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n629), .CK(clk), .RN(n1610), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n627), .CK(clk), .RN(n1604), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n626), .CK(clk), .RN(n1600), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n625), .CK(clk), .RN(n1596), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n624), .CK(clk), .RN(n1604), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n622), .CK(clk), .RN(n1600), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n621), .CK(clk), .RN(n1595), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n620), .CK(clk), .RN(n1614), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n619), .CK(clk), .RN(n1599), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n617), .CK(clk), .RN(n1613), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n615), .CK(clk), .RN(n1596), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n613), .CK(clk), .RN(n1604), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n611), .CK(clk), .RN(n1608), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n609), .CK(clk), .RN(n1608), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n608), .CK(clk), .RN(n1608), .QN(
n895) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n607), .CK(clk), .RN(n1608), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n606), .CK(clk), .RN(n1608), .QN(
n896) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n605), .CK(clk), .RN(n1608), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n603), .CK(clk), .RN(n1608), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n601), .CK(clk), .RN(n1608), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n599), .CK(clk), .RN(n1608), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n598), .CK(clk), .RN(n1608), .QN(
n894) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n597), .CK(clk), .RN(n1595), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n595), .CK(clk), .RN(n1612), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n594), .CK(clk), .RN(n1611),
.QN(n893) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n593), .CK(clk), .RN(n1605), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n591), .CK(clk), .RN(n1609), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n589), .CK(clk), .RN(n1612), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n587), .CK(clk), .RN(n1591), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n585), .CK(clk), .RN(n941), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n583), .CK(clk), .RN(n1603), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n581), .CK(clk), .RN(n1606), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n579), .CK(clk), .RN(n1615), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n578), .CK(clk), .RN(n1610),
.QN(n897) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n577), .CK(clk), .RN(n940), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n575), .CK(clk), .RN(n941), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n573), .CK(clk), .RN(n1603), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n572), .CK(clk), .RN(n1606),
.QN(n891) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n566), .CK(clk), .RN(n941), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n565), .CK(clk), .RN(n1596), .Q(
overflow_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n564), .CK(clk), .RN(n1603), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n563), .CK(clk), .RN(n1606), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n562), .CK(clk), .RN(n1611), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n561), .CK(clk), .RN(n1605), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n560), .CK(clk), .RN(n1598), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n559), .CK(clk), .RN(n1612), .Q(
zero_flag) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n558), .CK(clk), .RN(n1611), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n557), .CK(clk), .RN(n1605), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n555), .CK(clk), .RN(n1588), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n554), .CK(clk), .RN(n1612), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n553), .CK(clk), .RN(n1611), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n552), .CK(clk), .RN(n1605), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n551), .CK(clk), .RN(n1596), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n550), .CK(clk), .RN(n1604), .Q(
final_result_ieee[31]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n523), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[1]), .QN(n931) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n521), .CK(clk), .RN(n1598), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n516), .CK(clk), .RN(n1610), .Q(
DmP_mant_SFG_SWR[0]), .QN(n932) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n514), .CK(clk), .RN(n1597), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n513), .CK(clk), .RN(n940), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n512), .CK(clk), .RN(n941), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n511), .CK(clk), .RN(n1603), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n510), .CK(clk), .RN(n1606), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n509), .CK(clk), .RN(n1610), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n508), .CK(clk), .RN(n1612), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n507), .CK(clk), .RN(n1611), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n506), .CK(clk), .RN(n1605), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n505), .CK(clk), .RN(n1604), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n504), .CK(clk), .RN(n1612), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n503), .CK(clk), .RN(n1611), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n502), .CK(clk), .RN(n1605), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n501), .CK(clk), .RN(n1587), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n500), .CK(clk), .RN(n1613), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n499), .CK(clk), .RN(n1612), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n498), .CK(clk), .RN(n1611), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n497), .CK(clk), .RN(n1605), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n496), .CK(clk), .RN(n1586), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n495), .CK(clk), .RN(n1599), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n494), .CK(clk), .RN(n1596), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n493), .CK(clk), .RN(n1612), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n492), .CK(clk), .RN(n1611), .Q(
final_result_ieee[22]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n491), .CK(clk), .RN(n1605), .Q(
DmP_mant_SFG_SWR[4]), .QN(n933) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n490), .CK(clk), .RN(n1589), .Q(
DmP_mant_SFG_SWR[5]), .QN(n934) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n489), .CK(clk), .RN(n1604), .Q(
DmP_mant_SFG_SWR[6]), .QN(n936) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n488), .CK(clk), .RN(n1612), .Q(
DmP_mant_SFG_SWR[7]), .QN(n937) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n487), .CK(clk), .RN(n1611), .Q(
DmP_mant_SFG_SWR[8]), .QN(n938) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n486), .CK(clk), .RN(n1605), .Q(
DmP_mant_SFG_SWR[9]), .QN(n935) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n478), .CK(clk), .RN(n1613), .Q(
DmP_mant_SFG_SWR[17]), .QN(n922) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n477), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[18]), .QN(n923) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n476), .CK(clk), .RN(n1604), .Q(
DmP_mant_SFG_SWR[19]), .QN(n924) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n475), .CK(clk), .RN(n1614), .Q(
DmP_mant_SFG_SWR[20]), .QN(n925) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n474), .CK(clk), .RN(n1595), .Q(
DmP_mant_SFG_SWR[21]), .QN(n926) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n473), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[22]), .QN(n927) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n470), .CK(clk), .RN(n1613), .Q(
DmP_mant_SFG_SWR[25]), .QN(n929) );
CMPR32X2TS intadd_12_U14 ( .A(n1522), .B(intadd_12_B_0_), .C(intadd_12_CI),
.CO(intadd_12_n13), .S(intadd_12_SUM_0_) );
CMPR32X2TS intadd_12_U13 ( .A(n1529), .B(intadd_12_B_1_), .C(intadd_12_n13),
.CO(intadd_12_n12), .S(intadd_12_SUM_1_) );
CMPR32X2TS intadd_12_U12 ( .A(n1528), .B(intadd_12_B_2_), .C(intadd_12_n12),
.CO(intadd_12_n11), .S(intadd_12_SUM_2_) );
CMPR32X2TS intadd_12_U11 ( .A(n1536), .B(intadd_12_B_3_), .C(intadd_12_n11),
.CO(intadd_12_n10), .S(intadd_12_SUM_3_) );
CMPR32X2TS intadd_12_U10 ( .A(n1535), .B(intadd_12_B_4_), .C(intadd_12_n10),
.CO(intadd_12_n9), .S(intadd_12_SUM_4_) );
CMPR32X2TS intadd_12_U9 ( .A(n1542), .B(intadd_12_B_5_), .C(intadd_12_n9),
.CO(intadd_12_n8), .S(intadd_12_SUM_5_) );
CMPR32X2TS intadd_12_U8 ( .A(n1562), .B(intadd_12_B_6_), .C(intadd_12_n8),
.CO(intadd_12_n7), .S(intadd_12_SUM_6_) );
CMPR32X2TS intadd_12_U7 ( .A(n1561), .B(intadd_12_B_7_), .C(intadd_12_n7),
.CO(intadd_12_n6), .S(intadd_12_SUM_7_) );
CMPR32X2TS intadd_12_U6 ( .A(n1569), .B(intadd_12_B_8_), .C(intadd_12_n6),
.CO(intadd_12_n5), .S(intadd_12_SUM_8_) );
CMPR32X2TS intadd_12_U5 ( .A(n1568), .B(intadd_12_B_9_), .C(intadd_12_n5),
.CO(intadd_12_n4), .S(intadd_12_SUM_9_) );
CMPR32X2TS intadd_12_U4 ( .A(n1578), .B(intadd_12_B_10_), .C(intadd_12_n4),
.CO(intadd_12_n3), .S(intadd_12_SUM_10_) );
CMPR32X2TS intadd_12_U3 ( .A(n1577), .B(intadd_12_B_11_), .C(intadd_12_n3),
.CO(intadd_12_n2), .S(intadd_12_SUM_11_) );
CMPR32X2TS intadd_12_U2 ( .A(n1582), .B(intadd_12_B_12_), .C(intadd_12_n2),
.CO(intadd_12_n1), .S(intadd_12_SUM_12_) );
CMPR32X2TS intadd_13_U4 ( .A(n1566), .B(intadd_13_B_0_), .C(intadd_13_CI),
.CO(intadd_13_n3), .S(intadd_13_SUM_0_) );
CMPR32X2TS intadd_13_U3 ( .A(intadd_13_A_1_), .B(n901), .C(intadd_13_n3),
.CO(intadd_13_n2), .S(intadd_13_SUM_1_) );
CMPR32X2TS intadd_13_U2 ( .A(intadd_13_A_2_), .B(intadd_13_B_2_), .C(
intadd_13_n2), .CO(intadd_13_n1), .S(intadd_13_SUM_2_) );
CMPR32X2TS intadd_14_U4 ( .A(n1565), .B(intadd_14_B_0_), .C(intadd_14_CI),
.CO(intadd_14_n3), .S(intadd_14_SUM_0_) );
CMPR32X2TS intadd_14_U3 ( .A(intadd_14_A_1_), .B(n900), .C(intadd_14_n3),
.CO(intadd_14_n2), .S(intadd_14_SUM_1_) );
CMPR32X2TS intadd_14_U2 ( .A(intadd_14_A_2_), .B(n920), .C(intadd_14_n2),
.CO(intadd_14_n1), .S(intadd_14_SUM_2_) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n810), .CK(clk), .RN(n1596),
.Q(intDY_EWSW[25]), .QN(n1621) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n820), .CK(clk), .RN(n881), .Q(
intDY_EWSW[15]), .QN(n1620) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n824), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[11]), .QN(n1619) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n618), .CK(clk), .RN(n940), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1567) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n623), .CK(clk), .RN(n1608), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1541) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n628), .CK(clk), .RN(n1602), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1534) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n653), .CK(clk), .RN(n1601), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1521) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n522), .CK(clk), .RN(n1606), .Q(
Raw_mant_NRM_SWR[1]), .QN(n1572) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n515), .CK(clk), .RN(n1610), .Q(
Raw_mant_NRM_SWR[0]), .QN(n1501) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n518), .CK(clk), .RN(n940), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1519) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n548), .CK(clk), .RN(n1601), .Q(
Raw_mant_NRM_SWR[5]), .QN(n1524) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n547), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1571) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n545), .CK(clk), .RN(n1602), .Q(
Raw_mant_NRM_SWR[8]), .QN(n1527) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n546), .CK(clk), .RN(n1602), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1517) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n544), .CK(clk), .RN(n1615), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1492) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n540), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[13]), .QN(n1493) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n543), .CK(clk), .RN(n1602), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1490) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n539), .CK(clk), .RN(n1601), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1491) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n536), .CK(clk), .RN(n940), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1502) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n877), .CK(clk), .RN(
n1587), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1540) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n532), .CK(clk), .RN(n1601), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1499) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n816), .CK(clk), .RN(n1589),
.Q(intDY_EWSW[19]), .QN(n1509) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n808), .CK(clk), .RN(n1589),
.Q(intDY_EWSW[27]), .QN(n1559) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n811), .CK(clk), .RN(n1615),
.Q(intDY_EWSW[24]), .QN(n1495) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n819), .CK(clk), .RN(n1590),
.Q(intDY_EWSW[16]), .QN(n1553) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n826), .CK(clk), .RN(n1591), .Q(
intDY_EWSW[9]), .QN(n1544) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n829), .CK(clk), .RN(n1590), .Q(
intDY_EWSW[6]), .QN(n1538) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n807), .CK(clk), .RN(n1591),
.Q(intDY_EWSW[28]), .QN(n1556) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n531), .CK(clk), .RN(n941), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1497) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n835), .CK(clk), .RN(n1588), .Q(
intDY_EWSW[0]), .QN(n1506) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n833), .CK(clk), .RN(n1594), .Q(
intDY_EWSW[2]), .QN(n1549) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n831), .CK(clk), .RN(n881), .Q(
intDY_EWSW[4]), .QN(n1550) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n828), .CK(clk), .RN(n1593), .Q(
intDY_EWSW[7]), .QN(n1539) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n830), .CK(clk), .RN(n1592), .Q(
intDY_EWSW[5]), .QN(n1505) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n843), .CK(clk), .RN(n1587),
.Q(intDX_EWSW[26]), .QN(n1579) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n841), .CK(clk), .RN(n1589),
.Q(intDX_EWSW[28]), .QN(n1533) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n568), .CK(clk), .RN(n940), .Q(
DmP_EXP_EWSW[26]), .QN(n1513) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n570), .CK(clk), .RN(n1587), .Q(
DmP_EXP_EWSW[24]), .QN(n1510) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n569), .CK(clk), .RN(n941), .Q(
DmP_EXP_EWSW[25]), .QN(n1576) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n735), .CK(clk), .RN(n1595), .Q(
DMP_EXP_EWSW[25]), .QN(n1563) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n734), .CK(clk), .RN(n1600), .Q(
DMP_EXP_EWSW[26]), .QN(n1515) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n736), .CK(clk), .RN(n1596), .Q(
DMP_EXP_EWSW[24]), .QN(n1512) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n530), .CK(clk), .RN(n1603), .Q(
Raw_mant_NRM_SWR[23]), .QN(n1489) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n529), .CK(clk), .RN(n1606), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1494) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n528), .CK(clk), .RN(n1610), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1516) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n776), .CK(clk), .RN(n1590), .Q(
shift_value_SHT2_EWR[3]), .QN(n1532) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n801), .CK(clk), .RN(n1593), .Q(
Data_array_SWR[23]), .QN(n1570) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n788), .CK(clk), .RN(n881), .Q(
Data_array_SWR[10]), .QN(n1580) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1588), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1504) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n526), .CK(clk), .RN(n941), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1564) );
DFFRX2TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n556), .CK(clk), .RN(n1598), .Q(
OP_FLAG_SFG), .QN(n1616) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n537), .CK(clk), .RN(n1603), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1511) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n812), .CK(clk), .RN(n1590),
.Q(intDY_EWSW[23]), .QN(n1557) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n813), .CK(clk), .RN(n881), .Q(
intDY_EWSW[22]), .QN(n1507) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n814), .CK(clk), .RN(n1593),
.Q(intDY_EWSW[21]), .QN(n1546) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n815), .CK(clk), .RN(n1592),
.Q(intDY_EWSW[20]), .QN(n1554) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n821), .CK(clk), .RN(n1590),
.Q(intDY_EWSW[14]), .QN(n1552) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n822), .CK(clk), .RN(n881), .Q(
intDY_EWSW[13]), .QN(n1545) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n823), .CK(clk), .RN(n1593),
.Q(intDY_EWSW[12]), .QN(n1551) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n805), .CK(clk), .RN(n1589),
.Q(intDY_EWSW[30]), .QN(n1558) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n806), .CK(clk), .RN(n1591),
.Q(intDY_EWSW[29]), .QN(n1508) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n809), .CK(clk), .RN(n1599),
.Q(intDY_EWSW[26]), .QN(n1555) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n817), .CK(clk), .RN(n1613),
.Q(intDY_EWSW[18]), .QN(n1560) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n827), .CK(clk), .RN(n1592), .Q(
intDY_EWSW[8]), .QN(n1548) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n832), .CK(clk), .RN(n881), .Q(
intDY_EWSW[3]), .QN(n1543) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n834), .CK(clk), .RN(n1594), .Q(
intDY_EWSW[1]), .QN(n1547) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n844), .CK(clk), .RN(n1586),
.Q(intDX_EWSW[25]), .QN(n1514) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n845), .CK(clk), .RN(n1588),
.Q(intDX_EWSW[24]), .QN(n1575) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n853), .CK(clk), .RN(n1594),
.Q(intDX_EWSW[16]), .QN(n1525) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n862), .CK(clk), .RN(n1594), .Q(
intDX_EWSW[7]), .QN(n1500) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n863), .CK(clk), .RN(n1587), .Q(
intDX_EWSW[6]), .QN(n1526) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n864), .CK(clk), .RN(n1589), .Q(
intDX_EWSW[5]), .QN(n1520) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n865), .CK(clk), .RN(n1591), .Q(
intDX_EWSW[4]), .QN(n1498) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n774), .CK(clk), .RN(n1586), .Q(
shift_value_SHT2_EWR[4]), .QN(n1518) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n792), .CK(clk), .RN(n1588), .Q(
Data_array_SWR[14]), .QN(n1574) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n790), .CK(clk), .RN(n1590), .Q(
Data_array_SWR[12]), .QN(n1573) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n718), .CK(clk), .RN(n1614), .Q(
DMP_SFG[2]), .QN(n1565) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n866), .CK(clk), .RN(n1586), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n846), .CK(clk), .RN(n1587),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n854), .CK(clk), .RN(n1589),
.Q(intDX_EWSW[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n848), .CK(clk), .RN(n1591),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n856), .CK(clk), .RN(n1588),
.Q(intDX_EWSW[13]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n803), .CK(clk), .RN(n1590), .Q(
Data_array_SWR[25]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n802), .CK(clk), .RN(n881), .Q(
Data_array_SWR[24]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n533), .CK(clk), .RN(n1606), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n852), .CK(clk), .RN(n1586),
.Q(intDX_EWSW[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n800), .CK(clk), .RN(n1593), .Q(
Data_array_SWR[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n858), .CK(clk), .RN(n1588),
.Q(intDX_EWSW[11]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n860), .CK(clk), .RN(n1594), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n861), .CK(clk), .RN(n1591), .Q(
intDX_EWSW[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n868), .CK(clk), .RN(n1594), .Q(
intDX_EWSW[1]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n793), .CK(clk), .RN(n1594), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n791), .CK(clk), .RN(n881), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n541), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[12]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n534), .CK(clk), .RN(n1588), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n538), .CK(clk), .RN(n1601), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n851), .CK(clk), .RN(n1589),
.Q(intDX_EWSW[18]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n840), .CK(clk), .RN(n1587),
.Q(intDX_EWSW[29]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n842), .CK(clk), .RN(n1591),
.Q(intDX_EWSW[27]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n878), .CK(clk), .RN(
n1587), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n797), .CK(clk), .RN(n1587), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n786), .CK(clk), .RN(n1593), .Q(
Data_array_SWR[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n549), .CK(clk), .RN(n1597), .Q(
Raw_mant_NRM_SWR[4]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n535), .CK(clk), .RN(n940), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n782), .CK(clk), .RN(n1593), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n783), .CK(clk), .RN(n1592), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n785), .CK(clk), .RN(n881), .Q(
Data_array_SWR[7]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n697), .CK(clk), .RN(n1601), .Q(
DMP_SFG[9]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n709), .CK(clk), .RN(n1609), .Q(
DMP_SFG[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n784), .CK(clk), .RN(n1604), .Q(
Data_array_SWR[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n721), .CK(clk), .RN(n1613), .Q(
DMP_SFG[1]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n838), .CK(clk), .RN(n1591),
.Q(intDX_EWSW[31]) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n872), .CK(clk), .RN(n1586), .Q(
n939), .QN(n1617) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n825), .CK(clk), .RN(n1597),
.Q(intDY_EWSW[10]), .QN(n886) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n602), .CK(clk), .RN(n1609), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n610), .CK(clk), .RN(n1591), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n576), .CK(clk), .RN(n1610), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n582), .CK(clk), .RN(n941), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n584), .CK(clk), .RN(n1603), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n574), .CK(clk), .RN(n1603), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n600), .CK(clk), .RN(n1612), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n590), .CK(clk), .RN(n1605), .Q(
DmP_mant_SHT1_SW[13]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n588), .CK(clk), .RN(n1594), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n596), .CK(clk), .RN(n1612), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n580), .CK(clk), .RN(n1606), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n592), .CK(clk), .RN(n1611), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n586), .CK(clk), .RN(n940), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n604), .CK(clk), .RN(n1611), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n612), .CK(clk), .RN(n1596), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n614), .CK(clk), .RN(n1604), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n616), .CK(clk), .RN(n1599), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n724), .CK(clk), .RN(n1614), .Q(
DMP_SFG[0]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n484), .CK(clk), .RN(n1595), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n485), .CK(clk), .RN(n1605), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n519), .CK(clk), .RN(n1610), .Q(
DmP_mant_SFG_SWR[2]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n527), .CK(clk), .RN(n940), .Q(
DmP_mant_SFG_SWR[3]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n472), .CK(clk), .RN(n1600), .Q(
DmP_mant_SFG_SWR[23]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n480), .CK(clk), .RN(n1614), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n481), .CK(clk), .RN(n1596), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n482), .CK(clk), .RN(n1604), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n483), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n773), .CK(clk), .RN(n881), .Q(
Shift_amount_SHT1_EWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n818), .CK(clk), .RN(n881), .Q(
intDY_EWSW[17]), .QN(n1585) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n737), .CK(clk), .RN(n1604), .Q(
DMP_EXP_EWSW[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n794), .CK(clk), .RN(n1589), .Q(
Data_array_SWR[16]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n633), .CK(clk), .RN(n1615), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n638), .CK(clk), .RN(n1598), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n643), .CK(clk), .RN(n1597), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n648), .CK(clk), .RN(n1597), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n780), .CK(clk), .RN(n1592), .Q(
Data_array_SWR[2]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n804), .CK(clk), .RN(n1586),
.Q(intDY_EWSW[31]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n857), .CK(clk), .RN(n1586),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n849), .CK(clk), .RN(n1591),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n855), .CK(clk), .RN(n1588),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n847), .CK(clk), .RN(n1594),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n867), .CK(clk), .RN(n1587), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n859), .CK(clk), .RN(n1589),
.Q(intDX_EWSW[10]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n839), .CK(clk), .RN(n1589),
.Q(intDX_EWSW[30]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n850), .CK(clk), .RN(n1587),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n787), .CK(clk), .RN(n1592), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n789), .CK(clk), .RN(n1602), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n799), .CK(clk), .RN(n1592), .Q(
Data_array_SWR[21]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n795), .CK(clk), .RN(n1591), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n796), .CK(clk), .RN(n1588), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n798), .CK(clk), .RN(n881), .Q(
Data_array_SWR[20]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n777), .CK(clk), .RN(n1594), .Q(
shift_value_SHT2_EWR[2]), .QN(n1503) );
DFFRX1TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n837), .CK(clk), .RN(n1588), .Q(
intAS) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n471), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[24]), .QN(n928) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n479), .CK(clk), .RN(n1599), .Q(
DmP_mant_SFG_SWR[16]), .QN(n921) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n571), .CK(clk), .RN(n1610), .Q(
DmP_EXP_EWSW[23]), .QN(n930) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n542), .CK(clk), .RN(n1609), .Q(
Raw_mant_NRM_SWR[11]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n781), .CK(clk), .RN(n881), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n779), .CK(clk), .RN(n1590), .Q(
Data_array_SWR[1]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n778), .CK(clk), .RN(n1593), .Q(
Data_array_SWR[0]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n567), .CK(clk), .RN(n940), .Q(
DmP_EXP_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n682), .CK(clk), .RN(n1613), .Q(
DMP_SFG[14]), .QN(n1535) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n688), .CK(clk), .RN(n1599), .Q(
DMP_SFG[12]), .QN(n1528) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n670), .CK(clk), .RN(n1600), .Q(
DMP_SFG[18]), .QN(n1569) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n676), .CK(clk), .RN(n1596), .Q(
DMP_SFG[16]), .QN(n1562) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n679), .CK(clk), .RN(n1604), .Q(
DMP_SFG[15]), .QN(n1542) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n685), .CK(clk), .RN(n1600), .Q(
DMP_SFG[13]), .QN(n1536) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n691), .CK(clk), .RN(n1600), .Q(
DMP_SFG[11]), .QN(n1529) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n694), .CK(clk), .RN(n1602), .Q(
DMP_SFG[10]), .QN(n1522) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n706), .CK(clk), .RN(n1615), .Q(
DMP_SFG[6]), .QN(n1566) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_22_ ( .D(n658), .CK(clk), .RN(n1615), .Q(
DMP_SFG[22]), .QN(n1582) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_21_ ( .D(n661), .CK(clk), .RN(n1615), .Q(
DMP_SFG[21]), .QN(n1577) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_20_ ( .D(n664), .CK(clk), .RN(n1601), .Q(
DMP_SFG[20]), .QN(n1578) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n667), .CK(clk), .RN(n1598), .Q(
DMP_SFG[19]), .QN(n1568) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n673), .CK(clk), .RN(n1613), .Q(
DMP_SFG[17]), .QN(n1561) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n520), .CK(clk), .RN(n1609), .Q(
LZD_output_NRM2_EW[2]), .QN(n1531) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n517), .CK(clk), .RN(n1598), .Q(
LZD_output_NRM2_EW[3]), .QN(n1530) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n524), .CK(clk), .RN(n1602), .Q(
LZD_output_NRM2_EW[4]), .QN(n1537) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n525), .CK(clk), .RN(n1609), .Q(
LZD_output_NRM2_EW[1]), .QN(n1523) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n875), .CK(clk), .RN(n1586), .Q(
n1496), .QN(n1581) );
ADDFX1TS DP_OP_15J20_123_3116_U8 ( .A(n1523), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J20_123_3116_n8), .CO(DP_OP_15J20_123_3116_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J20_123_3116_U7 ( .A(n1531), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J20_123_3116_n7), .CO(DP_OP_15J20_123_3116_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J20_123_3116_U6 ( .A(n1530), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J20_123_3116_n6), .CO(DP_OP_15J20_123_3116_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS DP_OP_15J20_123_3116_U5 ( .A(n1537), .B(DMP_exp_NRM2_EW[4]), .CI(
DP_OP_15J20_123_3116_n5), .CO(DP_OP_15J20_123_3116_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n874), .CK(clk), .RN(n1594), .Q(
n879), .QN(n1583) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n876), .CK(clk), .RN(n1586), .Q(
Shift_reg_FLAGS_7_6), .QN(n883) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n870), .CK(clk), .RN(n1589), .Q(
Shift_reg_FLAGS_7[0]) );
NAND2X4TS U904 ( .A(n902), .B(n1455), .Y(n1339) );
NOR2X4TS U905 ( .A(n1393), .B(n1392), .Y(n1394) );
BUFX4TS U906 ( .A(n940), .Y(n941) );
NAND2X4TS U907 ( .A(n1162), .B(n1161), .Y(n1163) );
AOI222X4TS U908 ( .A0(Data_array_SWR[21]), .A1(n1427), .B0(
Data_array_SWR[17]), .B1(n1426), .C0(Data_array_SWR[25]), .C1(n1385),
.Y(n1443) );
NAND2X4TS U909 ( .A(n1164), .B(n1315), .Y(n1160) );
CLKINVX6TS U910 ( .A(rst), .Y(n940) );
AOI211X2TS U911 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1148), .B0(n1272), .C0(
n1147), .Y(n1180) );
CLKINVX6TS U912 ( .A(n1309), .Y(n1178) );
INVX3TS U913 ( .A(n1301), .Y(n911) );
NOR2X4TS U914 ( .A(n1180), .B(n1355), .Y(n1161) );
NAND3X1TS U915 ( .A(n1265), .B(n1131), .C(Raw_mant_NRM_SWR[1]), .Y(n1261) );
NAND3X1TS U916 ( .A(n1154), .B(n1139), .C(n1264), .Y(n1272) );
OAI211X1TS U917 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1138), .B0(n1266), .C0(
n1524), .Y(n1139) );
BUFX4TS U918 ( .A(n1045), .Y(n899) );
OAI21X1TS U919 ( .A0(Raw_mant_NRM_SWR[6]), .A1(Raw_mant_NRM_SWR[7]), .B0(
n1129), .Y(n1130) );
NOR2X4TS U920 ( .A(n1025), .B(n1084), .Y(n1033) );
INVX4TS U921 ( .A(n1449), .Y(n1396) );
OR2X2TS U922 ( .A(n1140), .B(Raw_mant_NRM_SWR[14]), .Y(n1257) );
INVX4TS U923 ( .A(n1381), .Y(n1367) );
INVX4TS U924 ( .A(n1289), .Y(n880) );
AND2X4TS U925 ( .A(beg_OP), .B(n1283), .Y(n1287) );
NOR2BX4TS U926 ( .AN(Shift_amount_SHT1_EWR[0]), .B(n1356), .Y(n1195) );
NAND4XLTS U927 ( .A(n1516), .B(n1494), .C(n1489), .D(n1497), .Y(n1269) );
BUFX6TS U928 ( .A(n941), .Y(n881) );
NAND2BXLTS U929 ( .AN(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n975) );
NAND2BXLTS U930 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1009) );
NAND2BXLTS U931 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n963) );
NAND2BXLTS U932 ( .AN(intDX_EWSW[9]), .B(intDY_EWSW[9]), .Y(n988) );
NAND2BXLTS U933 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n984) );
NAND2BXLTS U934 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1003) );
NAND3XLTS U935 ( .A(n1555), .B(n963), .C(intDX_EWSW[26]), .Y(n965) );
NAND3BXLTS U936 ( .AN(n1007), .B(n1005), .C(n1004), .Y(n1023) );
AO22XLTS U937 ( .A0(DmP_mant_SFG_SWR[9]), .A1(n918), .B0(n1389), .B1(n935),
.Y(n884) );
AO22XLTS U938 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n919), .B0(n1389), .B1(n934),
.Y(n887) );
AOI222X4TS U939 ( .A0(Data_array_SWR[14]), .A1(n1438), .B0(
Data_array_SWR[22]), .B1(n1437), .C0(Data_array_SWR[18]), .C1(n1439),
.Y(n1407) );
AOI222X4TS U940 ( .A0(Data_array_SWR[24]), .A1(n1437), .B0(
Data_array_SWR[20]), .B1(n1439), .C0(Data_array_SWR[16]), .C1(n1438),
.Y(n1399) );
AOI222X4TS U941 ( .A0(Data_array_SWR[21]), .A1(n1439), .B0(
Data_array_SWR[17]), .B1(n1438), .C0(Data_array_SWR[25]), .C1(n1437),
.Y(n1400) );
AOI222X4TS U942 ( .A0(Data_array_SWR[24]), .A1(n1385), .B0(
Data_array_SWR[20]), .B1(n1427), .C0(Data_array_SWR[16]), .C1(n1426),
.Y(n1412) );
NAND2BXLTS U943 ( .AN(n1274), .B(n956), .Y(n958) );
OAI21XLTS U944 ( .A0(n1524), .A1(n1301), .B0(n1200), .Y(n1201) );
AOI222X1TS U945 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n911), .B0(n915), .B1(n905),
.C0(n1299), .C1(DmP_mant_SHT1_SW[10]), .Y(n1229) );
AOI222X1TS U946 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n911), .B0(n915), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1299), .C1(DmP_mant_SHT1_SW[8]), .Y(n1211)
);
AOI222X1TS U947 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n911), .B0(n915), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1299), .C1(n903), .Y(n1194) );
AOI222X1TS U948 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n911), .B0(n915), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1299), .C1(DmP_mant_SHT1_SW[3]), .Y(n1190)
);
AOI222X1TS U949 ( .A0(n1245), .A1(DMP_SFG[1]), .B0(n1245), .B1(n1372), .C0(
DMP_SFG[1]), .C1(n1372), .Y(intadd_14_CI) );
AOI222X4TS U950 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n911), .B0(n915), .B1(
DmP_mant_SHT1_SW[20]), .C0(n1299), .C1(DmP_mant_SHT1_SW[21]), .Y(n1223) );
OAI21XLTS U951 ( .A0(n1491), .A1(n1221), .B0(n1204), .Y(n1205) );
OAI21XLTS U952 ( .A0(n1493), .A1(n1301), .B0(n1300), .Y(n1302) );
AO22XLTS U953 ( .A0(DmP_mant_SFG_SWR[7]), .A1(n1389), .B0(n1616), .B1(n937),
.Y(n888) );
AOI222X1TS U954 ( .A0(DMP_SFG[5]), .A1(n898), .B0(DMP_SFG[5]), .B1(n1250),
.C0(n898), .C1(n1250), .Y(intadd_13_CI) );
OAI21XLTS U955 ( .A0(n1501), .A1(n1132), .B0(n1261), .Y(n1133) );
OAI211XLTS U956 ( .A0(n1270), .A1(n1269), .B0(n1268), .C0(n1267), .Y(n1271)
);
AOI222X1TS U957 ( .A0(n1447), .A1(n1485), .B0(Data_array_SWR[8]), .B1(n1367),
.C0(n1446), .C1(n1445), .Y(n1472) );
AOI222X1TS U958 ( .A0(n1447), .A1(n1450), .B0(n1396), .B1(Data_array_SWR[8]),
.C0(n1446), .C1(n1444), .Y(n1462) );
AOI222X1TS U959 ( .A0(n1423), .A1(n1485), .B0(Data_array_SWR[6]), .B1(n1367),
.C0(n1422), .C1(n1445), .Y(n1474) );
AOI222X1TS U960 ( .A0(n1414), .A1(n1485), .B0(Data_array_SWR[9]), .B1(n1367),
.C0(n1413), .C1(n1445), .Y(n1471) );
AOI222X1TS U961 ( .A0(n1414), .A1(n1450), .B0(n1396), .B1(Data_array_SWR[9]),
.C0(n1413), .C1(n1444), .Y(n1463) );
OAI21XLTS U962 ( .A0(n1214), .A1(n1160), .B0(n1213), .Y(n798) );
OAI211XLTS U963 ( .A0(n1236), .A1(n1160), .B0(n1235), .C0(n1234), .Y(n795)
);
OAI211XLTS U964 ( .A0(n1211), .A1(n1160), .B0(n1210), .C0(n1209), .Y(n787)
);
AOI2BB2XLTS U965 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1307), .A0N(n1229), .A1N(
n1178), .Y(n1209) );
AO22XLTS U966 ( .A0(n1286), .A1(Data_X[19]), .B0(n1291), .B1(intDX_EWSW[19]),
.Y(n850) );
AO22XLTS U967 ( .A0(n1287), .A1(Data_X[30]), .B0(n1284), .B1(intDX_EWSW[30]),
.Y(n839) );
AO22XLTS U968 ( .A0(n1292), .A1(Data_X[10]), .B0(n1291), .B1(intDX_EWSW[10]),
.Y(n859) );
AO22XLTS U969 ( .A0(n1292), .A1(Data_Y[31]), .B0(n880), .B1(intDY_EWSW[31]),
.Y(n804) );
OAI21XLTS U970 ( .A0(n1298), .A1(n1160), .B0(n1220), .Y(n794) );
AO22XLTS U971 ( .A0(n1469), .A1(n1435), .B0(n1481), .B1(DmP_mant_SFG_SWR[3]),
.Y(n527) );
AO22XLTS U972 ( .A0(n1488), .A1(DMP_SHT2_EWSW[0]), .B0(n1481), .B1(
DMP_SFG[0]), .Y(n724) );
AO22XLTS U973 ( .A0(n1496), .A1(DmP_EXP_EWSW[0]), .B0(n1352), .B1(
DmP_mant_SHT1_SW[0]), .Y(n616) );
AO22XLTS U974 ( .A0(n1496), .A1(DmP_EXP_EWSW[1]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[1]), .Y(n614) );
AO22XLTS U975 ( .A0(n1496), .A1(DmP_EXP_EWSW[2]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[2]), .Y(n612) );
AO22XLTS U976 ( .A0(n1496), .A1(DmP_EXP_EWSW[6]), .B0(n1342), .B1(
DmP_mant_SHT1_SW[6]), .Y(n604) );
AO22XLTS U977 ( .A0(n1351), .A1(DmP_EXP_EWSW[15]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[15]), .Y(n586) );
AO22XLTS U978 ( .A0(n1351), .A1(DmP_EXP_EWSW[12]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[12]), .Y(n592) );
AO22XLTS U979 ( .A0(n1351), .A1(DmP_EXP_EWSW[18]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[18]), .Y(n580) );
AO22XLTS U980 ( .A0(n1351), .A1(DmP_EXP_EWSW[14]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[14]), .Y(n588) );
AO22XLTS U981 ( .A0(n1351), .A1(DmP_EXP_EWSW[13]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[13]), .Y(n590) );
AO22XLTS U982 ( .A0(n1496), .A1(DmP_EXP_EWSW[8]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[8]), .Y(n600) );
AO22XLTS U983 ( .A0(n1351), .A1(DmP_EXP_EWSW[21]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[21]), .Y(n574) );
AO22XLTS U984 ( .A0(n1351), .A1(DmP_EXP_EWSW[16]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[16]), .Y(n584) );
AO22XLTS U985 ( .A0(n1351), .A1(DmP_EXP_EWSW[17]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[17]), .Y(n582) );
AO22XLTS U986 ( .A0(n1351), .A1(DmP_EXP_EWSW[20]), .B0(n1344), .B1(
DmP_mant_SHT1_SW[20]), .Y(n576) );
AO22XLTS U987 ( .A0(n1281), .A1(n1363), .B0(n1282), .B1(n902), .Y(n872) );
AO22XLTS U988 ( .A0(n1292), .A1(Data_X[31]), .B0(n1290), .B1(intDX_EWSW[31]),
.Y(n838) );
AO22XLTS U989 ( .A0(n1488), .A1(DMP_SHT2_EWSW[1]), .B0(n1481), .B1(
DMP_SFG[1]), .Y(n721) );
OAI211XLTS U990 ( .A0(n1206), .A1(n1178), .B0(n1185), .C0(n1184), .Y(n784)
);
OAI211XLTS U991 ( .A0(n1211), .A1(n1178), .B0(n1182), .C0(n1181), .Y(n785)
);
OAI211XLTS U992 ( .A0(n1194), .A1(n1160), .B0(n1177), .C0(n1176), .Y(n783)
);
OAI211XLTS U993 ( .A0(n1190), .A1(n1160), .B0(n1173), .C0(n1172), .Y(n782)
);
OAI21XLTS U994 ( .A0(n1305), .A1(n1178), .B0(n1208), .Y(n786) );
OAI211XLTS U995 ( .A0(n1233), .A1(n1160), .B0(n1232), .C0(n1231), .Y(n797)
);
AO22XLTS U996 ( .A0(n1292), .A1(Data_X[27]), .B0(n880), .B1(intDX_EWSW[27]),
.Y(n842) );
AO22XLTS U997 ( .A0(n1286), .A1(Data_X[29]), .B0(n880), .B1(intDX_EWSW[29]),
.Y(n840) );
AO22XLTS U998 ( .A0(n1289), .A1(Data_X[18]), .B0(n880), .B1(intDX_EWSW[18]),
.Y(n851) );
AO22XLTS U999 ( .A0(n1288), .A1(Data_X[1]), .B0(n880), .B1(intDX_EWSW[1]),
.Y(n868) );
OAI21XLTS U1000 ( .A0(n1519), .A1(n1163), .B0(n1225), .Y(n800) );
OAI211XLTS U1001 ( .A0(n1315), .A1(n1518), .B0(n1256), .C0(n1135), .Y(n774)
);
OAI2BB2XLTS U1002 ( .B0(n1462), .B1(n1456), .A0N(final_result_ieee[6]),
.A1N(n1455), .Y(n496) );
AO22XLTS U1003 ( .A0(n1351), .A1(DmP_EXP_EWSW[22]), .B0(n1344), .B1(n909),
.Y(n572) );
AO22XLTS U1004 ( .A0(n1351), .A1(DmP_EXP_EWSW[19]), .B0(n1344), .B1(n904),
.Y(n578) );
AO22XLTS U1005 ( .A0(n1351), .A1(DmP_EXP_EWSW[9]), .B0(n1342), .B1(n905),
.Y(n598) );
AO22XLTS U1006 ( .A0(n1496), .A1(DmP_EXP_EWSW[5]), .B0(n1344), .B1(n907),
.Y(n606) );
AO22XLTS U1007 ( .A0(n1496), .A1(DmP_EXP_EWSW[4]), .B0(n1344), .B1(n903),
.Y(n608) );
OAI21XLTS U1008 ( .A0(n1125), .A1(n1084), .B0(n1122), .Y(n1123) );
AO22XLTS U1009 ( .A0(n1288), .A1(Data_X[0]), .B0(n1291), .B1(n916), .Y(n869)
);
AO22XLTS U1010 ( .A0(n1282), .A1(busy), .B0(n1281), .B1(n902), .Y(n873) );
OR2X1TS U1011 ( .A(n1356), .B(Shift_amount_SHT1_EWR[0]), .Y(n889) );
BUFX4TS U1012 ( .A(n1339), .Y(n1481) );
OAI211XLTS U1013 ( .A0(n1169), .A1(n1160), .B0(n1168), .C0(n1167), .Y(n779)
);
OAI211XLTS U1014 ( .A0(n1194), .A1(n1178), .B0(n1193), .C0(n1192), .Y(n781)
);
NOR3X1TS U1015 ( .A(shift_value_SHT2_EWR[4]), .B(shift_value_SHT2_EWR[2]),
.C(n1532), .Y(n1368) );
NOR2X2TS U1016 ( .A(n1162), .B(n1355), .Y(n1273) );
NOR4X2TS U1017 ( .A(n1159), .B(n1158), .C(n1157), .D(n1156), .Y(n1162) );
BUFX4TS U1018 ( .A(n941), .Y(n1599) );
NOR2X2TS U1019 ( .A(Raw_mant_NRM_SWR[6]), .B(n1136), .Y(n1266) );
BUFX4TS U1020 ( .A(n1481), .Y(n1486) );
AOI31XLTS U1021 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1144), .A2(n1502), .B0(
n1143), .Y(n1145) );
NOR2BX2TS U1022 ( .AN(n1270), .B(n1269), .Y(n1144) );
BUFX3TS U1023 ( .A(n1581), .Y(n1343) );
OAI211XLTS U1024 ( .A0(n966), .A1(n1088), .B0(n965), .C0(n964), .Y(n971) );
OAI21X2TS U1025 ( .A0(intDX_EWSW[26]), .A1(n1555), .B0(n963), .Y(n1088) );
BUFX4TS U1026 ( .A(n1603), .Y(n1613) );
BUFX4TS U1027 ( .A(n1606), .Y(n1604) );
BUFX4TS U1028 ( .A(n1610), .Y(n1596) );
BUFX4TS U1029 ( .A(n1601), .Y(n1600) );
CLKINVX3TS U1030 ( .A(n1217), .Y(n1239) );
BUFX4TS U1031 ( .A(n1588), .Y(n1601) );
BUFX4TS U1032 ( .A(n1589), .Y(n1615) );
BUFX4TS U1033 ( .A(n1599), .Y(n1602) );
BUFX4TS U1034 ( .A(n1613), .Y(n1597) );
BUFX4TS U1035 ( .A(n1613), .Y(n1588) );
BUFX4TS U1036 ( .A(n1590), .Y(n1594) );
INVX2TS U1037 ( .A(n888), .Y(n898) );
NOR2X2TS U1038 ( .A(Raw_mant_NRM_SWR[13]), .B(n1257), .Y(n1153) );
BUFX4TS U1039 ( .A(n881), .Y(n1586) );
BUFX4TS U1040 ( .A(n1593), .Y(n1591) );
BUFX4TS U1041 ( .A(n1592), .Y(n1589) );
BUFX4TS U1042 ( .A(n1599), .Y(n1587) );
INVX2TS U1043 ( .A(n887), .Y(n900) );
INVX2TS U1044 ( .A(n884), .Y(n901) );
NOR2X4TS U1045 ( .A(n1409), .B(shift_value_SHT2_EWR[4]), .Y(n1395) );
XNOR2X2TS U1046 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J20_123_3116_n4), .Y(
n960) );
BUFX4TS U1047 ( .A(n1369), .Y(n1437) );
BUFX6TS U1048 ( .A(Shift_reg_FLAGS_7[1]), .Y(n1356) );
NOR2X4TS U1049 ( .A(shift_value_SHT2_EWR[4]), .B(n1485), .Y(n1445) );
BUFX6TS U1050 ( .A(left_right_SHT2), .Y(n1485) );
BUFX4TS U1051 ( .A(n1028), .Y(n1336) );
INVX2TS U1052 ( .A(n890), .Y(n902) );
INVX2TS U1053 ( .A(n895), .Y(n903) );
INVX2TS U1054 ( .A(n897), .Y(n904) );
INVX2TS U1055 ( .A(n894), .Y(n905) );
INVX2TS U1056 ( .A(n893), .Y(n906) );
INVX2TS U1057 ( .A(n896), .Y(n907) );
INVX2TS U1058 ( .A(n892), .Y(n908) );
INVX2TS U1059 ( .A(n891), .Y(n909) );
NOR2X4TS U1060 ( .A(shift_value_SHT2_EWR[3]), .B(n1503), .Y(n1427) );
INVX2TS U1061 ( .A(n1301), .Y(n910) );
BUFX4TS U1062 ( .A(n1084), .Y(n1280) );
INVX2TS U1063 ( .A(n1160), .Y(n912) );
INVX2TS U1064 ( .A(n912), .Y(n913) );
INVX3TS U1065 ( .A(n1617), .Y(n1364) );
CLKINVX3TS U1066 ( .A(n889), .Y(n914) );
INVX3TS U1067 ( .A(n889), .Y(n915) );
INVX3TS U1068 ( .A(n1348), .Y(n1455) );
OAI21XLTS U1069 ( .A0(n1214), .A1(n1178), .B0(n1203), .Y(n796) );
OAI211XLTS U1070 ( .A0(n1229), .A1(n913), .B0(n1228), .C0(n1227), .Y(n789)
);
AOI32X1TS U1071 ( .A0(n1560), .A1(n1009), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1509), .Y(n1010) );
AOI221X1TS U1072 ( .A0(n1560), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1509), .C0(n1095), .Y(n1100) );
AOI221X1TS U1073 ( .A0(n1558), .A1(intDX_EWSW[30]), .B0(intDX_EWSW[17]),
.B1(n1585), .C0(n1094), .Y(n1101) );
AOI221X4TS U1074 ( .A0(intDX_EWSW[30]), .A1(n1558), .B0(intDX_EWSW[29]),
.B1(n1508), .C0(n968), .Y(n970) );
INVX2TS U1075 ( .A(n885), .Y(n916) );
AOI221X1TS U1076 ( .A0(n886), .A1(intDX_EWSW[10]), .B0(intDX_EWSW[11]), .B1(
n1619), .C0(n1103), .Y(n1108) );
AOI221X1TS U1077 ( .A0(n1549), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1543), .C0(n1111), .Y(n1116) );
AOI221X1TS U1078 ( .A0(n1507), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1557), .C0(n1097), .Y(n1098) );
AOI221X1TS U1079 ( .A0(n1552), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1620), .C0(n1105), .Y(n1106) );
OAI211X2TS U1080 ( .A0(intDX_EWSW[20]), .A1(n1554), .B0(n1017), .C0(n1003),
.Y(n1012) );
AOI221X1TS U1081 ( .A0(n1554), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]),
.B1(n1546), .C0(n1096), .Y(n1099) );
OAI211X2TS U1082 ( .A0(intDX_EWSW[12]), .A1(n1551), .B0(n998), .C0(n984),
.Y(n1000) );
AOI221X1TS U1083 ( .A0(n1551), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1545), .C0(n1104), .Y(n1107) );
INVX2TS U1084 ( .A(n1616), .Y(n917) );
INVX2TS U1085 ( .A(n917), .Y(n918) );
INVX4TS U1086 ( .A(n917), .Y(n919) );
BUFX4TS U1087 ( .A(n1368), .Y(n1439) );
INVX1TS U1088 ( .A(DMP_SFG[3]), .Y(intadd_14_A_1_) );
INVX1TS U1089 ( .A(DMP_SFG[4]), .Y(intadd_14_A_2_) );
INVX1TS U1090 ( .A(DMP_SFG[7]), .Y(intadd_13_A_1_) );
INVX1TS U1091 ( .A(DMP_SFG[8]), .Y(intadd_13_A_2_) );
OAI211XLTS U1092 ( .A0(n1190), .A1(n1178), .B0(n1189), .C0(n1188), .Y(n780)
);
OAI31XLTS U1093 ( .A0(n1338), .A1(n1125), .A2(n1347), .B0(n1124), .Y(n727)
);
NOR2X4TS U1094 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1426) );
NOR2X2TS U1095 ( .A(n930), .B(DMP_EXP_EWSW[23]), .Y(n1322) );
XNOR2X2TS U1096 ( .A(DMP_exp_NRM2_EW[7]), .B(n947), .Y(n957) );
XNOR2X2TS U1097 ( .A(DMP_exp_NRM2_EW[0]), .B(n1254), .Y(n959) );
INVX1TS U1098 ( .A(LZD_output_NRM2_EW[0]), .Y(n1254) );
XNOR2X2TS U1099 ( .A(DMP_exp_NRM2_EW[6]), .B(n944), .Y(n1274) );
AO22XLTS U1100 ( .A0(DmP_mant_SFG_SWR[6]), .A1(n1616), .B0(n1389), .B1(n936),
.Y(intadd_14_B_2_) );
INVX2TS U1101 ( .A(intadd_14_B_2_), .Y(n920) );
AOI222X4TS U1102 ( .A0(n1249), .A1(intadd_14_A_2_), .B0(n1249), .B1(n920),
.C0(intadd_14_A_2_), .C1(n920), .Y(n1250) );
CLKINVX6TS U1103 ( .A(n1082), .Y(n1058) );
NOR2X4TS U1104 ( .A(shift_value_SHT2_EWR[4]), .B(n1450), .Y(n1444) );
CLKINVX6TS U1105 ( .A(n1485), .Y(n1450) );
AOI2BB2X2TS U1106 ( .B0(DmP_mant_SFG_SWR[3]), .B1(n1389), .A0N(n1389), .A1N(
DmP_mant_SFG_SWR[3]), .Y(n1372) );
AOI2BB2X2TS U1107 ( .B0(DmP_mant_SFG_SWR[10]), .B1(n919), .A0N(n918), .A1N(
DmP_mant_SFG_SWR[10]), .Y(intadd_13_B_2_) );
AOI2BB2X2TS U1108 ( .B0(DmP_mant_SFG_SWR[11]), .B1(n1389), .A0N(OP_FLAG_SFG),
.A1N(DmP_mant_SFG_SWR[11]), .Y(n1359) );
AOI222X1TS U1109 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n910), .B0(
DmP_mant_SHT1_SW[14]), .B1(n1299), .C0(n914), .C1(DmP_mant_SHT1_SW[13]), .Y(n1240) );
AOI222X1TS U1110 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n910), .B0(n914), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1299), .C1(DmP_mant_SHT1_SW[16]), .Y(n1236) );
AOI222X4TS U1111 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n910), .B0(n914), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1299), .C1(DmP_mant_SHT1_SW[17]), .Y(n1218) );
AOI222X1TS U1112 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n911), .B0(n915), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1299), .C1(DmP_mant_SHT1_SW[18]), .Y(n1233) );
AOI222X1TS U1113 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n911), .B0(n915), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1299), .C1(DmP_mant_SHT1_SW[7]), .Y(n1206)
);
NOR2XLTS U1114 ( .A(n986), .B(intDY_EWSW[10]), .Y(n987) );
INVX4TS U1115 ( .A(n1287), .Y(n1290) );
CLKINVX6TS U1116 ( .A(n1583), .Y(busy) );
NAND2X2TS U1117 ( .A(n1355), .B(n1583), .Y(n1315) );
AOI222X1TS U1118 ( .A0(n1423), .A1(n1450), .B0(n1396), .B1(Data_array_SWR[6]), .C0(n1422), .C1(n1444), .Y(n1459) );
AOI222X4TS U1119 ( .A0(DMP_SFG[9]), .A1(n1359), .B0(DMP_SFG[9]), .B1(n1253),
.C0(n1359), .C1(n1253), .Y(intadd_12_B_0_) );
AOI222X1TS U1120 ( .A0(n1418), .A1(n1450), .B0(n1396), .B1(Data_array_SWR[7]), .C0(n1417), .C1(n1444), .Y(n1460) );
AOI222X1TS U1121 ( .A0(n1418), .A1(n1485), .B0(Data_array_SWR[7]), .B1(n1367), .C0(n1417), .C1(n1445), .Y(n1473) );
AOI222X1TS U1122 ( .A0(n1428), .A1(n1450), .B0(n1396), .B1(Data_array_SWR[5]), .C0(n1429), .C1(n1444), .Y(n1458) );
AOI222X1TS U1123 ( .A0(n1428), .A1(n1485), .B0(Data_array_SWR[5]), .B1(n1367), .C0(n1429), .C1(n1445), .Y(n1475) );
AOI222X1TS U1124 ( .A0(n1434), .A1(n1450), .B0(n1396), .B1(Data_array_SWR[4]), .C0(n1433), .C1(n1444), .Y(n1457) );
AOI222X1TS U1125 ( .A0(n1434), .A1(n1485), .B0(Data_array_SWR[4]), .B1(n1367), .C0(n1433), .C1(n1445), .Y(n1476) );
INVX4TS U1126 ( .A(n1481), .Y(n1483) );
INVX3TS U1127 ( .A(n1394), .Y(n1456) );
AOI222X1TS U1128 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n910), .B0(n915), .B1(n904),
.C0(n1299), .C1(DmP_mant_SHT1_SW[20]), .Y(n1230) );
AOI222X4TS U1129 ( .A0(Data_array_SWR[23]), .A1(n1437), .B0(
Data_array_SWR[19]), .B1(n1439), .C0(Data_array_SWR[15]), .C1(n1438),
.Y(n1403) );
NOR2X2TS U1130 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1540), .Y(n1279) );
AOI221X1TS U1131 ( .A0(n1555), .A1(intDX_EWSW[26]), .B0(intDX_EWSW[27]),
.B1(n1559), .C0(n1088), .Y(n1092) );
OAI21X2TS U1132 ( .A0(intDX_EWSW[18]), .A1(n1560), .B0(n1009), .Y(n1095) );
AOI32X1TS U1133 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1150), .A2(n1149), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1150), .Y(n1151) );
NOR3X1TS U1134 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1270) );
AOI222X1TS U1135 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n910), .B0(n914), .B1(n906), .C0(n1299), .C1(DmP_mant_SHT1_SW[12]), .Y(n1244) );
OAI211XLTS U1136 ( .A0(n1244), .A1(n913), .B0(n1243), .C0(n1242), .Y(n791)
);
AOI221X1TS U1137 ( .A0(n1547), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[25]), .B1(
n1621), .C0(n1087), .Y(n1093) );
AOI221X1TS U1138 ( .A0(n1548), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1538), .C0(n1113), .Y(n1114) );
NOR2XLTS U1139 ( .A(n1619), .B(intDX_EWSW[11]), .Y(n986) );
OAI21XLTS U1140 ( .A0(intDX_EWSW[15]), .A1(n1620), .B0(intDX_EWSW[14]), .Y(
n994) );
NOR2XLTS U1141 ( .A(n1007), .B(intDY_EWSW[16]), .Y(n1008) );
OAI21XLTS U1142 ( .A0(intDX_EWSW[23]), .A1(n1557), .B0(intDX_EWSW[22]), .Y(
n1013) );
OAI21XLTS U1143 ( .A0(intDX_EWSW[21]), .A1(n1546), .B0(intDX_EWSW[20]), .Y(
n1006) );
NOR2XLTS U1144 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1149) );
OAI21XLTS U1145 ( .A0(n1361), .A1(n1301), .B0(n1296), .Y(n1297) );
OR2X1TS U1146 ( .A(n958), .B(n957), .Y(n1246) );
OAI21XLTS U1147 ( .A0(n1572), .A1(n1221), .B0(n1196), .Y(n1197) );
OAI21XLTS U1148 ( .A0(n1492), .A1(n1301), .B0(n1215), .Y(n1216) );
OAI21XLTS U1149 ( .A0(n1507), .A1(n1058), .B0(n1036), .Y(n738) );
OAI21XLTS U1150 ( .A0(n1544), .A1(n1347), .B0(n1051), .Y(n751) );
OAI21XLTS U1151 ( .A0(n1295), .A1(n1178), .B0(n1199), .Y(n799) );
OAI211XLTS U1152 ( .A0(n1240), .A1(n913), .B0(n1238), .C0(n1237), .Y(n793)
);
BUFX3TS U1153 ( .A(n940), .Y(n1603) );
BUFX3TS U1154 ( .A(n941), .Y(n1605) );
BUFX3TS U1155 ( .A(n941), .Y(n1606) );
BUFX3TS U1156 ( .A(n1587), .Y(n1598) );
BUFX3TS U1157 ( .A(n940), .Y(n1608) );
BUFX3TS U1158 ( .A(n940), .Y(n1611) );
BUFX3TS U1159 ( .A(n1587), .Y(n1614) );
BUFX3TS U1160 ( .A(n941), .Y(n1612) );
BUFX3TS U1161 ( .A(n940), .Y(n1592) );
BUFX3TS U1162 ( .A(n940), .Y(n1593) );
BUFX3TS U1163 ( .A(n940), .Y(n1610) );
BUFX3TS U1164 ( .A(n1591), .Y(n1609) );
BUFX3TS U1165 ( .A(n941), .Y(n1590) );
BUFX3TS U1166 ( .A(n1601), .Y(n1595) );
INVX2TS U1167 ( .A(DP_OP_15J20_123_3116_n4), .Y(n942) );
NAND2X1TS U1168 ( .A(n1534), .B(n942), .Y(n944) );
INVX2TS U1169 ( .A(n944), .Y(n943) );
NAND2X1TS U1170 ( .A(n1541), .B(n943), .Y(n947) );
AND4X1TS U1171 ( .A(exp_rslt_NRM2_EW1[3]), .B(n959), .C(exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n945) );
AND4X1TS U1172 ( .A(n1274), .B(n960), .C(exp_rslt_NRM2_EW1[4]), .D(n945),
.Y(n946) );
CLKAND2X2TS U1173 ( .A(n957), .B(n946), .Y(n950) );
INVX2TS U1174 ( .A(n947), .Y(n948) );
CLKAND2X2TS U1175 ( .A(n1567), .B(n948), .Y(n949) );
OAI2BB1X1TS U1176 ( .A0N(n950), .A1N(n949), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1392) );
INVX2TS U1177 ( .A(n1392), .Y(n951) );
CLKBUFX2TS U1178 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1348) );
AO22XLTS U1179 ( .A0(n951), .A1(n957), .B0(n1455), .B1(final_result_ieee[30]), .Y(n761) );
NOR2XLTS U1180 ( .A(n959), .B(exp_rslt_NRM2_EW1[1]), .Y(n954) );
INVX2TS U1181 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n953) );
INVX2TS U1182 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n952) );
NAND4BXLTS U1183 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n954), .C(n953), .D(n952),
.Y(n955) );
NOR2XLTS U1184 ( .A(n955), .B(n960), .Y(n956) );
NAND2X2TS U1185 ( .A(n1246), .B(n1348), .Y(n1275) );
OA22X1TS U1186 ( .A0(n1275), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n765) );
OA22X1TS U1187 ( .A0(n1275), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n767) );
OA22X1TS U1188 ( .A0(n1275), .A1(n959), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n768) );
OA22X1TS U1189 ( .A0(n1275), .A1(n960), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n763) );
OA22X1TS U1190 ( .A0(n1275), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n764) );
OA22X1TS U1191 ( .A0(n1275), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n766) );
INVX4TS U1192 ( .A(n1356), .Y(n1355) );
OAI21XLTS U1193 ( .A0(n879), .A1(n1450), .B0(n1355), .Y(n836) );
AOI2BB2XLTS U1194 ( .B0(beg_OP), .B1(n1504), .A0N(n1504), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n961) );
NAND3XLTS U1195 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1504), .C(
n1540), .Y(n1276) );
OAI21XLTS U1196 ( .A0(n1279), .A1(n961), .B0(n1276), .Y(n877) );
NOR2X1TS U1197 ( .A(n1621), .B(intDX_EWSW[25]), .Y(n1020) );
NOR2XLTS U1198 ( .A(n1020), .B(intDY_EWSW[24]), .Y(n962) );
AOI22X1TS U1199 ( .A0(intDX_EWSW[25]), .A1(n1621), .B0(intDX_EWSW[24]), .B1(
n962), .Y(n966) );
NAND2BXLTS U1200 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n964) );
NOR2X1TS U1201 ( .A(n1558), .B(intDX_EWSW[30]), .Y(n969) );
NOR2X1TS U1202 ( .A(n1508), .B(intDX_EWSW[29]), .Y(n967) );
AOI211X1TS U1203 ( .A0(intDY_EWSW[28]), .A1(n1533), .B0(n969), .C0(n967),
.Y(n1019) );
NOR3XLTS U1204 ( .A(n1533), .B(n967), .C(intDY_EWSW[28]), .Y(n968) );
AOI2BB2X1TS U1205 ( .B0(n971), .B1(n1019), .A0N(n970), .A1N(n969), .Y(n1024)
);
NOR2X1TS U1206 ( .A(n1585), .B(intDX_EWSW[17]), .Y(n1007) );
OAI22X1TS U1207 ( .A0(n886), .A1(intDX_EWSW[10]), .B0(n1619), .B1(
intDX_EWSW[11]), .Y(n1103) );
INVX2TS U1208 ( .A(n1103), .Y(n991) );
OAI211XLTS U1209 ( .A0(intDX_EWSW[8]), .A1(n1548), .B0(n988), .C0(n991), .Y(
n1002) );
OAI2BB1X1TS U1210 ( .A0N(n1520), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n972) );
OAI22X1TS U1211 ( .A0(intDY_EWSW[4]), .A1(n972), .B0(n1520), .B1(
intDY_EWSW[5]), .Y(n983) );
OAI2BB1X1TS U1212 ( .A0N(n1500), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n973) );
OAI22X1TS U1213 ( .A0(intDY_EWSW[6]), .A1(n973), .B0(n1500), .B1(
intDY_EWSW[7]), .Y(n982) );
OAI21XLTS U1214 ( .A0(intDX_EWSW[1]), .A1(n1547), .B0(n916), .Y(n974) );
OAI2BB2XLTS U1215 ( .B0(intDY_EWSW[0]), .B1(n974), .A0N(intDX_EWSW[1]),
.A1N(n1547), .Y(n976) );
OAI211XLTS U1216 ( .A0(n1543), .A1(intDX_EWSW[3]), .B0(n976), .C0(n975), .Y(
n979) );
OAI21XLTS U1217 ( .A0(intDX_EWSW[3]), .A1(n1543), .B0(intDX_EWSW[2]), .Y(
n977) );
AOI2BB2XLTS U1218 ( .B0(intDX_EWSW[3]), .B1(n1543), .A0N(intDY_EWSW[2]),
.A1N(n977), .Y(n978) );
AOI222X1TS U1219 ( .A0(intDY_EWSW[4]), .A1(n1498), .B0(n979), .B1(n978),
.C0(intDY_EWSW[5]), .C1(n1520), .Y(n981) );
AOI22X1TS U1220 ( .A0(intDY_EWSW[7]), .A1(n1500), .B0(intDY_EWSW[6]), .B1(
n1526), .Y(n980) );
OAI32X1TS U1221 ( .A0(n983), .A1(n982), .A2(n981), .B0(n980), .B1(n982), .Y(
n1001) );
OA22X1TS U1222 ( .A0(n1552), .A1(intDX_EWSW[14]), .B0(n1620), .B1(
intDX_EWSW[15]), .Y(n998) );
OAI21XLTS U1223 ( .A0(intDX_EWSW[13]), .A1(n1545), .B0(intDX_EWSW[12]), .Y(
n985) );
OAI2BB2XLTS U1224 ( .B0(intDY_EWSW[12]), .B1(n985), .A0N(intDX_EWSW[13]),
.A1N(n1545), .Y(n997) );
AOI22X1TS U1225 ( .A0(intDX_EWSW[11]), .A1(n1619), .B0(intDX_EWSW[10]), .B1(
n987), .Y(n993) );
NAND2BXLTS U1226 ( .AN(intDY_EWSW[9]), .B(intDX_EWSW[9]), .Y(n990) );
NAND3XLTS U1227 ( .A(n1548), .B(n988), .C(intDX_EWSW[8]), .Y(n989) );
AOI21X1TS U1228 ( .A0(n990), .A1(n989), .B0(n1000), .Y(n992) );
OAI2BB2XLTS U1229 ( .B0(n993), .B1(n1000), .A0N(n992), .A1N(n991), .Y(n996)
);
OAI2BB2XLTS U1230 ( .B0(intDY_EWSW[14]), .B1(n994), .A0N(intDX_EWSW[15]),
.A1N(n1620), .Y(n995) );
AOI211X1TS U1231 ( .A0(n998), .A1(n997), .B0(n996), .C0(n995), .Y(n999) );
OAI31X1TS U1232 ( .A0(n1002), .A1(n1001), .A2(n1000), .B0(n999), .Y(n1005)
);
OA22X1TS U1233 ( .A0(n1507), .A1(intDX_EWSW[22]), .B0(n1557), .B1(
intDX_EWSW[23]), .Y(n1017) );
AOI211XLTS U1234 ( .A0(intDY_EWSW[16]), .A1(n1525), .B0(n1012), .C0(n1095),
.Y(n1004) );
OAI2BB2XLTS U1235 ( .B0(intDY_EWSW[20]), .B1(n1006), .A0N(intDX_EWSW[21]),
.A1N(n1546), .Y(n1016) );
AOI22X1TS U1236 ( .A0(intDX_EWSW[17]), .A1(n1585), .B0(intDX_EWSW[16]), .B1(
n1008), .Y(n1011) );
OAI32X1TS U1237 ( .A0(n1095), .A1(n1012), .A2(n1011), .B0(n1010), .B1(n1012),
.Y(n1015) );
OAI2BB2XLTS U1238 ( .B0(intDY_EWSW[22]), .B1(n1013), .A0N(intDX_EWSW[23]),
.A1N(n1557), .Y(n1014) );
AOI211X1TS U1239 ( .A0(n1017), .A1(n1016), .B0(n1015), .C0(n1014), .Y(n1022)
);
NAND2BXLTS U1240 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1018) );
NAND4BBX1TS U1241 ( .AN(n1088), .BN(n1020), .C(n1019), .D(n1018), .Y(n1021)
);
AOI32X1TS U1242 ( .A0(n1024), .A1(n1023), .A2(n1022), .B0(n1021), .B1(n1024),
.Y(n1025) );
INVX2TS U1243 ( .A(Shift_reg_FLAGS_7_6), .Y(n1028) );
INVX4TS U1244 ( .A(n1033), .Y(n1347) );
AND2X2TS U1245 ( .A(Shift_reg_FLAGS_7_6), .B(n1025), .Y(n1048) );
AOI22X1TS U1246 ( .A0(n908), .A1(n1280), .B0(intDX_EWSW[27]), .B1(n1048),
.Y(n1026) );
OAI21XLTS U1247 ( .A0(n1559), .A1(n1347), .B0(n1026), .Y(n733) );
AOI22X1TS U1248 ( .A0(intDX_EWSW[1]), .A1(n1048), .B0(DMP_EXP_EWSW[1]), .B1(
n1336), .Y(n1027) );
OAI21XLTS U1249 ( .A0(n1547), .A1(n1347), .B0(n1027), .Y(n759) );
BUFX3TS U1250 ( .A(n1048), .Y(n1045) );
BUFX4TS U1251 ( .A(n1028), .Y(n1084) );
AOI22X1TS U1252 ( .A0(intDX_EWSW[28]), .A1(n1045), .B0(DMP_EXP_EWSW[28]),
.B1(n1084), .Y(n1029) );
OAI21XLTS U1253 ( .A0(n1556), .A1(n1347), .B0(n1029), .Y(n732) );
AOI22X1TS U1254 ( .A0(intDX_EWSW[29]), .A1(n1045), .B0(DMP_EXP_EWSW[29]),
.B1(n1084), .Y(n1030) );
OAI21XLTS U1255 ( .A0(n1508), .A1(n1347), .B0(n1030), .Y(n731) );
AOI22X1TS U1256 ( .A0(intDX_EWSW[30]), .A1(n1045), .B0(DMP_EXP_EWSW[30]),
.B1(n1336), .Y(n1031) );
OAI21XLTS U1257 ( .A0(n1558), .A1(n1347), .B0(n1031), .Y(n730) );
AOI22X1TS U1258 ( .A0(DMP_EXP_EWSW[23]), .A1(n1280), .B0(intDX_EWSW[23]),
.B1(n1045), .Y(n1032) );
OAI21XLTS U1259 ( .A0(n1557), .A1(n1347), .B0(n1032), .Y(n737) );
BUFX3TS U1260 ( .A(n1033), .Y(n1082) );
AOI22X1TS U1261 ( .A0(intDX_EWSW[20]), .A1(n1045), .B0(DMP_EXP_EWSW[20]),
.B1(n1336), .Y(n1034) );
OAI21XLTS U1262 ( .A0(n1554), .A1(n1058), .B0(n1034), .Y(n740) );
AOI22X1TS U1263 ( .A0(intDX_EWSW[21]), .A1(n1045), .B0(DMP_EXP_EWSW[21]),
.B1(n1084), .Y(n1035) );
OAI21XLTS U1264 ( .A0(n1546), .A1(n1058), .B0(n1035), .Y(n739) );
AOI22X1TS U1265 ( .A0(intDX_EWSW[22]), .A1(n1045), .B0(DMP_EXP_EWSW[22]),
.B1(n1336), .Y(n1036) );
AOI22X1TS U1266 ( .A0(intDX_EWSW[17]), .A1(n1045), .B0(DMP_EXP_EWSW[17]),
.B1(n1084), .Y(n1037) );
OAI21XLTS U1267 ( .A0(n1585), .A1(n1058), .B0(n1037), .Y(n743) );
AOI22X1TS U1268 ( .A0(intDX_EWSW[18]), .A1(n1045), .B0(DMP_EXP_EWSW[18]),
.B1(n1336), .Y(n1038) );
OAI21XLTS U1269 ( .A0(n1560), .A1(n1058), .B0(n1038), .Y(n742) );
AOI22X1TS U1270 ( .A0(intDX_EWSW[7]), .A1(n1048), .B0(DMP_EXP_EWSW[7]), .B1(
n1336), .Y(n1039) );
OAI21XLTS U1271 ( .A0(n1539), .A1(n1058), .B0(n1039), .Y(n753) );
AOI22X1TS U1272 ( .A0(intDX_EWSW[19]), .A1(n1045), .B0(DMP_EXP_EWSW[19]),
.B1(n1084), .Y(n1040) );
OAI21XLTS U1273 ( .A0(n1509), .A1(n1058), .B0(n1040), .Y(n741) );
AOI22X1TS U1274 ( .A0(intDX_EWSW[4]), .A1(n1048), .B0(DMP_EXP_EWSW[4]), .B1(
n1084), .Y(n1041) );
OAI21XLTS U1275 ( .A0(n1550), .A1(n1058), .B0(n1041), .Y(n756) );
AOI22X1TS U1276 ( .A0(intDX_EWSW[2]), .A1(n1048), .B0(DMP_EXP_EWSW[2]), .B1(
n1084), .Y(n1042) );
OAI21XLTS U1277 ( .A0(n1549), .A1(n1058), .B0(n1042), .Y(n758) );
AOI22X1TS U1278 ( .A0(n916), .A1(n1045), .B0(DMP_EXP_EWSW[0]), .B1(n1336),
.Y(n1043) );
OAI21XLTS U1279 ( .A0(n1506), .A1(n1058), .B0(n1043), .Y(n760) );
AOI22X1TS U1280 ( .A0(intDX_EWSW[6]), .A1(n1048), .B0(DMP_EXP_EWSW[6]), .B1(
n1084), .Y(n1044) );
OAI21XLTS U1281 ( .A0(n1538), .A1(n1058), .B0(n1044), .Y(n754) );
AOI22X1TS U1282 ( .A0(intDX_EWSW[5]), .A1(n899), .B0(DMP_EXP_EWSW[5]), .B1(
n1084), .Y(n1046) );
OAI21XLTS U1283 ( .A0(n1505), .A1(n1347), .B0(n1046), .Y(n755) );
AOI22X1TS U1284 ( .A0(intDX_EWSW[16]), .A1(n899), .B0(DMP_EXP_EWSW[16]),
.B1(n1084), .Y(n1047) );
OAI21XLTS U1285 ( .A0(n1553), .A1(n1058), .B0(n1047), .Y(n744) );
AOI222X1TS U1286 ( .A0(n1082), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1336), .C0(intDY_EWSW[23]), .C1(n1048), .Y(n1049) );
INVX2TS U1287 ( .A(n1049), .Y(n571) );
AOI22X1TS U1288 ( .A0(intDX_EWSW[10]), .A1(n899), .B0(DMP_EXP_EWSW[10]),
.B1(n1336), .Y(n1050) );
OAI21XLTS U1289 ( .A0(n886), .A1(n1058), .B0(n1050), .Y(n750) );
AOI22X1TS U1290 ( .A0(intDX_EWSW[9]), .A1(n899), .B0(DMP_EXP_EWSW[9]), .B1(
n1084), .Y(n1051) );
AOI22X1TS U1291 ( .A0(intDX_EWSW[14]), .A1(n899), .B0(DMP_EXP_EWSW[14]),
.B1(n1280), .Y(n1052) );
OAI21XLTS U1292 ( .A0(n1552), .A1(n1058), .B0(n1052), .Y(n746) );
AOI22X1TS U1293 ( .A0(intDX_EWSW[8]), .A1(n899), .B0(DMP_EXP_EWSW[8]), .B1(
n1280), .Y(n1053) );
OAI21XLTS U1294 ( .A0(n1548), .A1(n1058), .B0(n1053), .Y(n752) );
AOI22X1TS U1295 ( .A0(intDX_EWSW[12]), .A1(n899), .B0(DMP_EXP_EWSW[12]),
.B1(n1280), .Y(n1054) );
OAI21XLTS U1296 ( .A0(n1551), .A1(n1058), .B0(n1054), .Y(n748) );
AOI22X1TS U1297 ( .A0(intDX_EWSW[11]), .A1(n899), .B0(DMP_EXP_EWSW[11]),
.B1(n1084), .Y(n1055) );
OAI21XLTS U1298 ( .A0(n1619), .A1(n1058), .B0(n1055), .Y(n749) );
AOI22X1TS U1299 ( .A0(intDX_EWSW[13]), .A1(n899), .B0(DMP_EXP_EWSW[13]),
.B1(n1336), .Y(n1056) );
OAI21XLTS U1300 ( .A0(n1545), .A1(n1058), .B0(n1056), .Y(n747) );
AOI22X1TS U1301 ( .A0(intDX_EWSW[15]), .A1(n899), .B0(DMP_EXP_EWSW[15]),
.B1(n1336), .Y(n1057) );
OAI21XLTS U1302 ( .A0(n1620), .A1(n1058), .B0(n1057), .Y(n745) );
AOI22X1TS U1303 ( .A0(intDX_EWSW[3]), .A1(n899), .B0(DMP_EXP_EWSW[3]), .B1(
n1336), .Y(n1059) );
OAI21XLTS U1304 ( .A0(n1543), .A1(n1347), .B0(n1059), .Y(n757) );
INVX3TS U1305 ( .A(n899), .Y(n1122) );
AOI22X1TS U1306 ( .A0(DmP_EXP_EWSW[27]), .A1(n1280), .B0(intDX_EWSW[27]),
.B1(n1082), .Y(n1060) );
OAI21XLTS U1307 ( .A0(n1559), .A1(n1122), .B0(n1060), .Y(n567) );
AOI22X1TS U1308 ( .A0(intDX_EWSW[12]), .A1(n1082), .B0(DmP_EXP_EWSW[12]),
.B1(n1028), .Y(n1061) );
OAI21XLTS U1309 ( .A0(n1551), .A1(n1122), .B0(n1061), .Y(n593) );
CLKBUFX3TS U1310 ( .A(n1082), .Y(n1085) );
AOI22X1TS U1311 ( .A0(intDX_EWSW[14]), .A1(n1085), .B0(DmP_EXP_EWSW[14]),
.B1(n1028), .Y(n1062) );
OAI21XLTS U1312 ( .A0(n1552), .A1(n1122), .B0(n1062), .Y(n589) );
AOI22X1TS U1313 ( .A0(intDX_EWSW[15]), .A1(n1085), .B0(DmP_EXP_EWSW[15]),
.B1(n1280), .Y(n1063) );
OAI21XLTS U1314 ( .A0(n1620), .A1(n1122), .B0(n1063), .Y(n587) );
AOI22X1TS U1315 ( .A0(intDX_EWSW[13]), .A1(n1085), .B0(DmP_EXP_EWSW[13]),
.B1(n1280), .Y(n1064) );
OAI21XLTS U1316 ( .A0(n1545), .A1(n1122), .B0(n1064), .Y(n591) );
AOI22X1TS U1317 ( .A0(intDX_EWSW[8]), .A1(n1082), .B0(DmP_EXP_EWSW[8]), .B1(
n1336), .Y(n1065) );
OAI21XLTS U1318 ( .A0(n1548), .A1(n1122), .B0(n1065), .Y(n601) );
AOI22X1TS U1319 ( .A0(intDX_EWSW[9]), .A1(n1033), .B0(DmP_EXP_EWSW[9]), .B1(
n1336), .Y(n1066) );
OAI21XLTS U1320 ( .A0(n1544), .A1(n1122), .B0(n1066), .Y(n599) );
AOI22X1TS U1321 ( .A0(intDX_EWSW[6]), .A1(n1082), .B0(DmP_EXP_EWSW[6]), .B1(
n1336), .Y(n1067) );
OAI21XLTS U1322 ( .A0(n1538), .A1(n1122), .B0(n1067), .Y(n605) );
AOI22X1TS U1323 ( .A0(intDX_EWSW[5]), .A1(n1082), .B0(DmP_EXP_EWSW[5]), .B1(
n1336), .Y(n1068) );
OAI21XLTS U1324 ( .A0(n1505), .A1(n1122), .B0(n1068), .Y(n607) );
AOI22X1TS U1325 ( .A0(intDX_EWSW[4]), .A1(n1033), .B0(DmP_EXP_EWSW[4]), .B1(
n1280), .Y(n1069) );
OAI21XLTS U1326 ( .A0(n1550), .A1(n1122), .B0(n1069), .Y(n609) );
AOI22X1TS U1327 ( .A0(intDX_EWSW[7]), .A1(n1033), .B0(DmP_EXP_EWSW[7]), .B1(
n1028), .Y(n1070) );
OAI21XLTS U1328 ( .A0(n1539), .A1(n1122), .B0(n1070), .Y(n603) );
AOI22X1TS U1329 ( .A0(intDX_EWSW[10]), .A1(n1033), .B0(DmP_EXP_EWSW[10]),
.B1(n1084), .Y(n1071) );
OAI21XLTS U1330 ( .A0(n886), .A1(n1122), .B0(n1071), .Y(n597) );
AOI22X1TS U1331 ( .A0(intDX_EWSW[11]), .A1(n1082), .B0(DmP_EXP_EWSW[11]),
.B1(n1028), .Y(n1072) );
OAI21XLTS U1332 ( .A0(n1619), .A1(n1122), .B0(n1072), .Y(n595) );
INVX4TS U1333 ( .A(n899), .Y(n1345) );
AOI22X1TS U1334 ( .A0(intDX_EWSW[20]), .A1(n1085), .B0(DmP_EXP_EWSW[20]),
.B1(n1280), .Y(n1073) );
OAI21XLTS U1335 ( .A0(n1554), .A1(n1345), .B0(n1073), .Y(n577) );
AOI22X1TS U1336 ( .A0(intDX_EWSW[16]), .A1(n1085), .B0(DmP_EXP_EWSW[16]),
.B1(n1280), .Y(n1074) );
OAI21XLTS U1337 ( .A0(n1553), .A1(n1345), .B0(n1074), .Y(n585) );
AOI22X1TS U1338 ( .A0(intDX_EWSW[21]), .A1(n1085), .B0(DmP_EXP_EWSW[21]),
.B1(n1280), .Y(n1075) );
OAI21XLTS U1339 ( .A0(n1546), .A1(n1345), .B0(n1075), .Y(n575) );
AOI22X1TS U1340 ( .A0(intDX_EWSW[18]), .A1(n1033), .B0(DmP_EXP_EWSW[18]),
.B1(n1280), .Y(n1076) );
OAI21XLTS U1341 ( .A0(n1560), .A1(n1345), .B0(n1076), .Y(n581) );
AOI22X1TS U1342 ( .A0(intDX_EWSW[22]), .A1(n1085), .B0(DmP_EXP_EWSW[22]),
.B1(n1280), .Y(n1077) );
OAI21XLTS U1343 ( .A0(n1507), .A1(n1345), .B0(n1077), .Y(n573) );
AOI22X1TS U1344 ( .A0(intDX_EWSW[17]), .A1(n1085), .B0(DmP_EXP_EWSW[17]),
.B1(n1280), .Y(n1078) );
OAI21XLTS U1345 ( .A0(n1585), .A1(n1345), .B0(n1078), .Y(n583) );
AOI22X1TS U1346 ( .A0(intDX_EWSW[19]), .A1(n1085), .B0(DmP_EXP_EWSW[19]),
.B1(n1280), .Y(n1079) );
OAI21XLTS U1347 ( .A0(n1509), .A1(n1345), .B0(n1079), .Y(n579) );
AOI22X1TS U1348 ( .A0(intDX_EWSW[1]), .A1(n1082), .B0(DmP_EXP_EWSW[1]), .B1(
n1280), .Y(n1080) );
OAI21XLTS U1349 ( .A0(n1547), .A1(n1345), .B0(n1080), .Y(n615) );
AOI22X1TS U1350 ( .A0(intDX_EWSW[3]), .A1(n1082), .B0(DmP_EXP_EWSW[3]), .B1(
n1028), .Y(n1081) );
OAI21XLTS U1351 ( .A0(n1543), .A1(n1345), .B0(n1081), .Y(n611) );
AOI22X1TS U1352 ( .A0(intDX_EWSW[2]), .A1(n1082), .B0(DmP_EXP_EWSW[2]), .B1(
n1084), .Y(n1083) );
OAI21XLTS U1353 ( .A0(n1549), .A1(n1345), .B0(n1083), .Y(n613) );
AOI22X1TS U1354 ( .A0(n916), .A1(n1085), .B0(DmP_EXP_EWSW[0]), .B1(n1084),
.Y(n1086) );
OAI21XLTS U1355 ( .A0(n1506), .A1(n1345), .B0(n1086), .Y(n617) );
OAI22X1TS U1356 ( .A0(n1547), .A1(intDX_EWSW[1]), .B0(n1621), .B1(
intDX_EWSW[25]), .Y(n1087) );
OAI22X1TS U1357 ( .A0(n1556), .A1(intDX_EWSW[28]), .B0(n1508), .B1(
intDX_EWSW[29]), .Y(n1089) );
AOI221X1TS U1358 ( .A0(n1556), .A1(intDX_EWSW[28]), .B0(intDX_EWSW[29]),
.B1(n1508), .C0(n1089), .Y(n1091) );
AOI2BB2XLTS U1359 ( .B0(intDX_EWSW[7]), .B1(n1539), .A0N(n1539), .A1N(
intDX_EWSW[7]), .Y(n1090) );
NAND4XLTS U1360 ( .A(n1093), .B(n1092), .C(n1091), .D(n1090), .Y(n1121) );
OAI22X1TS U1361 ( .A0(n1558), .A1(intDX_EWSW[30]), .B0(n1585), .B1(
intDX_EWSW[17]), .Y(n1094) );
OAI22X1TS U1362 ( .A0(n1554), .A1(intDX_EWSW[20]), .B0(n1546), .B1(
intDX_EWSW[21]), .Y(n1096) );
OAI22X1TS U1363 ( .A0(n1507), .A1(intDX_EWSW[22]), .B0(n1557), .B1(
intDX_EWSW[23]), .Y(n1097) );
NAND4XLTS U1364 ( .A(n1101), .B(n1100), .C(n1099), .D(n1098), .Y(n1120) );
OAI22X1TS U1365 ( .A0(n1495), .A1(intDX_EWSW[24]), .B0(n1544), .B1(
intDX_EWSW[9]), .Y(n1102) );
AOI221X1TS U1366 ( .A0(n1495), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n1544), .C0(n1102), .Y(n1109) );
OAI22X1TS U1367 ( .A0(n1551), .A1(intDX_EWSW[12]), .B0(n1545), .B1(
intDX_EWSW[13]), .Y(n1104) );
OAI22X1TS U1368 ( .A0(n1552), .A1(intDX_EWSW[14]), .B0(n1620), .B1(
intDX_EWSW[15]), .Y(n1105) );
NAND4XLTS U1369 ( .A(n1109), .B(n1108), .C(n1107), .D(n1106), .Y(n1119) );
OAI22X1TS U1370 ( .A0(n1553), .A1(intDX_EWSW[16]), .B0(n1506), .B1(n916),
.Y(n1110) );
AOI221X1TS U1371 ( .A0(n1553), .A1(intDX_EWSW[16]), .B0(n916), .B1(n1506),
.C0(n1110), .Y(n1117) );
OAI22X1TS U1372 ( .A0(n1549), .A1(intDX_EWSW[2]), .B0(n1543), .B1(
intDX_EWSW[3]), .Y(n1111) );
OAI22X1TS U1373 ( .A0(n1550), .A1(intDX_EWSW[4]), .B0(n1505), .B1(
intDX_EWSW[5]), .Y(n1112) );
AOI221X1TS U1374 ( .A0(n1550), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1505), .C0(n1112), .Y(n1115) );
OAI22X1TS U1375 ( .A0(n1548), .A1(intDX_EWSW[8]), .B0(n1538), .B1(
intDX_EWSW[6]), .Y(n1113) );
NAND4XLTS U1376 ( .A(n1117), .B(n1116), .C(n1115), .D(n1114), .Y(n1118) );
NOR4X1TS U1377 ( .A(n1121), .B(n1120), .C(n1119), .D(n1118), .Y(n1338) );
CLKXOR2X2TS U1378 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1335) );
INVX2TS U1379 ( .A(n1335), .Y(n1125) );
AOI22X1TS U1380 ( .A0(intDX_EWSW[31]), .A1(n1123), .B0(SIGN_FLAG_EXP), .B1(
n883), .Y(n1124) );
NOR2XLTS U1381 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1127)
);
NOR3X1TS U1382 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[15]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1259) );
NOR2BX1TS U1383 ( .AN(n1144), .B(Raw_mant_NRM_SWR[18]), .Y(n1258) );
NAND2X1TS U1384 ( .A(n1259), .B(n1258), .Y(n1140) );
INVX2TS U1385 ( .A(Raw_mant_NRM_SWR[11]), .Y(n1361) );
NAND2X1TS U1386 ( .A(n1153), .B(n1361), .Y(n1146) );
NOR2X1TS U1387 ( .A(Raw_mant_NRM_SWR[12]), .B(n1146), .Y(n1137) );
NAND2X1TS U1388 ( .A(n1137), .B(n1490), .Y(n1126) );
NOR2X1TS U1389 ( .A(Raw_mant_NRM_SWR[4]), .B(Raw_mant_NRM_SWR[5]), .Y(n1128)
);
NOR3X1TS U1390 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1126),
.Y(n1129) );
NAND2X1TS U1391 ( .A(n1129), .B(n1517), .Y(n1136) );
OAI22X1TS U1392 ( .A0(n1127), .A1(n1126), .B0(n1128), .B1(n1136), .Y(n1134)
);
NOR2X1TS U1393 ( .A(Raw_mant_NRM_SWR[3]), .B(Raw_mant_NRM_SWR[2]), .Y(n1131)
);
NAND2X1TS U1394 ( .A(n1266), .B(n1128), .Y(n1132) );
OAI21X1TS U1395 ( .A0(n1131), .A1(n1132), .B0(n1130), .Y(n1158) );
INVX2TS U1396 ( .A(n1132), .Y(n1265) );
OAI31X1TS U1397 ( .A0(n1134), .A1(n1158), .A2(n1133), .B0(n1356), .Y(n1256)
);
NAND3XLTS U1398 ( .A(n879), .B(Shift_amount_SHT1_EWR[4]), .C(n1355), .Y(
n1135) );
INVX2TS U1399 ( .A(n1136), .Y(n1148) );
NOR2BX1TS U1400 ( .AN(n1137), .B(n1490), .Y(n1263) );
AOI21X1TS U1401 ( .A0(n1144), .A1(Raw_mant_NRM_SWR[18]), .B0(n1263), .Y(
n1154) );
OAI32X1TS U1402 ( .A0(Raw_mant_NRM_SWR[3]), .A1(Raw_mant_NRM_SWR[1]), .A2(
n1501), .B0(n1519), .B1(Raw_mant_NRM_SWR[3]), .Y(n1138) );
NAND2X1TS U1403 ( .A(Raw_mant_NRM_SWR[12]), .B(n1153), .Y(n1264) );
NOR2X1TS U1404 ( .A(n1491), .B(n1140), .Y(n1159) );
INVX2TS U1405 ( .A(n1159), .Y(n1142) );
AOI32X1TS U1406 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1489), .A2(n1499), .B0(
Raw_mant_NRM_SWR[22]), .B1(n1489), .Y(n1141) );
AOI32X1TS U1407 ( .A0(n1494), .A1(n1142), .A2(n1141), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1142), .Y(n1143) );
OAI31X1TS U1408 ( .A0(Raw_mant_NRM_SWR[9]), .A1(n1146), .A2(n1527), .B0(
n1145), .Y(n1147) );
NAND2X2TS U1409 ( .A(n1356), .B(n1180), .Y(n1301) );
BUFX4TS U1410 ( .A(n1195), .Y(n1299) );
AOI22X1TS U1411 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n911), .B0(n1299), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1169) );
NOR2XLTS U1412 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1152) );
NOR2X1TS U1413 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1150) );
AOI211X1TS U1414 ( .A0(n1152), .A1(n1151), .B0(Raw_mant_NRM_SWR[24]), .C0(
Raw_mant_NRM_SWR[25]), .Y(n1157) );
INVX2TS U1415 ( .A(n1153), .Y(n1155) );
OAI31X1TS U1416 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1361), .A2(n1155), .B0(
n1154), .Y(n1156) );
AOI21X1TS U1417 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n1355), .B0(n1273), .Y(
n1164) );
INVX2TS U1418 ( .A(n1315), .Y(n1226) );
BUFX4TS U1419 ( .A(n1226), .Y(n1312) );
INVX2TS U1420 ( .A(n1163), .Y(n1307) );
AOI22X1TS U1421 ( .A0(n1312), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1307), .Y(n1168) );
NOR2X2TS U1422 ( .A(n1312), .B(n1164), .Y(n1309) );
AOI22X1TS U1423 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1161), .B0(n1195), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1166) );
AOI22X1TS U1424 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n910), .B0(n914), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1165) );
NAND2X1TS U1425 ( .A(n1166), .B(n1165), .Y(n1191) );
NAND2X1TS U1426 ( .A(n1309), .B(n1191), .Y(n1167) );
AOI22X1TS U1427 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1161), .B0(n1195), .B1(
n907), .Y(n1171) );
AOI22X1TS U1428 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n910), .B0(n914), .B1(n903),
.Y(n1170) );
NAND2X1TS U1429 ( .A(n1171), .B(n1170), .Y(n1183) );
AOI22X1TS U1430 ( .A0(n1226), .A1(Data_array_SWR[4]), .B0(n1309), .B1(n1183),
.Y(n1173) );
NAND2X1TS U1431 ( .A(Raw_mant_NRM_SWR[20]), .B(n1307), .Y(n1172) );
AOI22X1TS U1432 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1161), .B0(n1195), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1175) );
AOI22X1TS U1433 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n910), .B0(n914), .B1(n907),
.Y(n1174) );
NAND2X1TS U1434 ( .A(n1175), .B(n1174), .Y(n1179) );
AOI22X1TS U1435 ( .A0(n1226), .A1(Data_array_SWR[5]), .B0(n1309), .B1(n1179),
.Y(n1177) );
NAND2X1TS U1436 ( .A(Raw_mant_NRM_SWR[19]), .B(n1307), .Y(n1176) );
AOI22X1TS U1437 ( .A0(n1226), .A1(Data_array_SWR[7]), .B0(n912), .B1(n1179),
.Y(n1182) );
NAND2BX1TS U1438 ( .AN(n1180), .B(n1273), .Y(n1217) );
NAND2X1TS U1439 ( .A(Raw_mant_NRM_SWR[15]), .B(n1239), .Y(n1181) );
AOI22X1TS U1440 ( .A0(n1226), .A1(Data_array_SWR[6]), .B0(n912), .B1(n1183),
.Y(n1185) );
NAND2X1TS U1441 ( .A(Raw_mant_NRM_SWR[16]), .B(n1239), .Y(n1184) );
AOI22X1TS U1442 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1161), .B0(n1299), .B1(
DmP_mant_SHT1_SW[1]), .Y(n1187) );
AOI22X1TS U1443 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n910), .B0(n914), .B1(
DmP_mant_SHT1_SW[0]), .Y(n1186) );
NAND2X1TS U1444 ( .A(n1187), .B(n1186), .Y(n1308) );
AOI22X1TS U1445 ( .A0(n1312), .A1(Data_array_SWR[2]), .B0(n912), .B1(n1308),
.Y(n1189) );
NAND2X1TS U1446 ( .A(Raw_mant_NRM_SWR[20]), .B(n1239), .Y(n1188) );
AOI22X1TS U1447 ( .A0(n1226), .A1(Data_array_SWR[3]), .B0(n912), .B1(n1191),
.Y(n1193) );
NAND2X1TS U1448 ( .A(Raw_mant_NRM_SWR[19]), .B(n1239), .Y(n1192) );
INVX2TS U1449 ( .A(n1161), .Y(n1221) );
AOI22X1TS U1450 ( .A0(n914), .A1(DmP_mant_SHT1_SW[21]), .B0(n1195), .B1(n909), .Y(n1196) );
AOI21X1TS U1451 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n911), .B0(n1197), .Y(n1295)
);
OAI22X1TS U1452 ( .A0(n1230), .A1(n913), .B0(n1564), .B1(n1163), .Y(n1198)
);
AOI21X1TS U1453 ( .A0(n1312), .A1(Data_array_SWR[21]), .B0(n1198), .Y(n1199)
);
AOI22X1TS U1454 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1161), .B0(n1299), .B1(n904), .Y(n1200) );
AOI21X1TS U1455 ( .A0(n915), .A1(DmP_mant_SHT1_SW[18]), .B0(n1201), .Y(n1214) );
OAI22X1TS U1456 ( .A0(n1218), .A1(n913), .B0(n1571), .B1(n1163), .Y(n1202)
);
AOI21X1TS U1457 ( .A0(n1312), .A1(Data_array_SWR[18]), .B0(n1202), .Y(n1203)
);
AOI22X1TS U1458 ( .A0(n914), .A1(DmP_mant_SHT1_SW[8]), .B0(n1299), .B1(n905),
.Y(n1204) );
AOI21X1TS U1459 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n911), .B0(n1205), .Y(n1305) );
OAI22X1TS U1460 ( .A0(n1206), .A1(n913), .B0(n1511), .B1(n1163), .Y(n1207)
);
AOI21X1TS U1461 ( .A0(n1312), .A1(Data_array_SWR[8]), .B0(n1207), .Y(n1208)
);
AOI22X1TS U1462 ( .A0(n1226), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1239), .Y(n1210) );
OAI22X1TS U1463 ( .A0(n1223), .A1(n1178), .B0(n1519), .B1(n1217), .Y(n1212)
);
AOI21X1TS U1464 ( .A0(n1312), .A1(Data_array_SWR[20]), .B0(n1212), .Y(n1213)
);
AOI22X1TS U1465 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1161), .B0(
DmP_mant_SHT1_SW[15]), .B1(n1195), .Y(n1215) );
AOI21X1TS U1466 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n915), .B0(n1216), .Y(n1298) );
OAI22X1TS U1467 ( .A0(n1218), .A1(n1178), .B0(n1571), .B1(n1217), .Y(n1219)
);
AOI21X1TS U1468 ( .A0(n1312), .A1(Data_array_SWR[16]), .B0(n1219), .Y(n1220)
);
OAI22X1TS U1469 ( .A0(n1501), .A1(n1221), .B0(n1572), .B1(n1301), .Y(n1222)
);
AOI211X1TS U1470 ( .A0(n909), .A1(n1355), .B0(n1195), .C0(n1222), .Y(n1293)
);
OAI22X1TS U1471 ( .A0(n1293), .A1(n1178), .B0(n1223), .B1(n913), .Y(n1224)
);
AOI21X1TS U1472 ( .A0(n1312), .A1(Data_array_SWR[22]), .B0(n1224), .Y(n1225)
);
AOI22X1TS U1473 ( .A0(n1226), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1239), .Y(n1228) );
OA22X1TS U1474 ( .A0(n1493), .A1(n1163), .B0(n1244), .B1(n1178), .Y(n1227)
);
AOI22X1TS U1475 ( .A0(n1312), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1239), .Y(n1232) );
OA22X1TS U1476 ( .A0(n1524), .A1(n1163), .B0(n1230), .B1(n1178), .Y(n1231)
);
AOI22X1TS U1477 ( .A0(n1312), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1239), .Y(n1235) );
OA22X1TS U1478 ( .A0(n1517), .A1(n1163), .B0(n1233), .B1(n1178), .Y(n1234)
);
AOI22X1TS U1479 ( .A0(n1312), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1239), .Y(n1238) );
OA22X1TS U1480 ( .A0(n1492), .A1(n1163), .B0(n1236), .B1(n1178), .Y(n1237)
);
AOI22X1TS U1481 ( .A0(n1312), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1239), .Y(n1243) );
OA22X1TS U1482 ( .A0(n1361), .A1(n1163), .B0(n1240), .B1(n1178), .Y(n1242)
);
BUFX4TS U1483 ( .A(OP_FLAG_SFG), .Y(n1389) );
AOI2BB2X1TS U1484 ( .B0(DmP_mant_SFG_SWR[2]), .B1(n1389), .A0N(n1389), .A1N(
DmP_mant_SFG_SWR[2]), .Y(n1383) );
NAND2X1TS U1485 ( .A(n1383), .B(DMP_SFG[0]), .Y(n1382) );
INVX2TS U1486 ( .A(n1382), .Y(n1245) );
INVX2TS U1487 ( .A(n1246), .Y(n1393) );
NOR2XLTS U1488 ( .A(n1393), .B(SIGN_FLAG_SHT1SHT2), .Y(n1247) );
OAI2BB2XLTS U1489 ( .B0(n1247), .B1(n1392), .A0N(n1455), .A1N(
final_result_ieee[31]), .Y(n550) );
AOI22X1TS U1490 ( .A0(DmP_mant_SFG_SWR[4]), .A1(n919), .B0(n1389), .B1(n933),
.Y(intadd_14_B_0_) );
AOI21X1TS U1491 ( .A0(intadd_14_A_1_), .A1(n900), .B0(intadd_14_B_0_), .Y(
n1248) );
AOI2BB2X1TS U1492 ( .B0(DMP_SFG[2]), .B1(n1248), .A0N(intadd_14_A_1_), .A1N(
n900), .Y(n1249) );
AOI22X1TS U1493 ( .A0(DmP_mant_SFG_SWR[8]), .A1(n918), .B0(n1389), .B1(n938),
.Y(intadd_13_B_0_) );
AOI21X1TS U1494 ( .A0(intadd_13_A_1_), .A1(n901), .B0(intadd_13_B_0_), .Y(
n1251) );
AOI2BB2X1TS U1495 ( .B0(DMP_SFG[6]), .B1(n1251), .A0N(intadd_13_A_1_), .A1N(
n901), .Y(n1252) );
AOI222X1TS U1496 ( .A0(n1252), .A1(intadd_13_A_2_), .B0(n1252), .B1(
intadd_13_B_2_), .C0(intadd_13_A_2_), .C1(intadd_13_B_2_), .Y(n1253)
);
INVX2TS U1497 ( .A(n1254), .Y(n1255) );
NAND2X1TS U1498 ( .A(n1521), .B(n1255), .Y(DP_OP_15J20_123_3116_n8) );
MX2X1TS U1499 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n1356),
.Y(n618) );
MX2X1TS U1500 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n1356),
.Y(n623) );
MX2X1TS U1501 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n1356),
.Y(n628) );
MX2X1TS U1502 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n1356),
.Y(n633) );
MX2X1TS U1503 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n1356),
.Y(n638) );
MX2X1TS U1504 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n1356),
.Y(n643) );
MX2X1TS U1505 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n1356),
.Y(n648) );
MX2X1TS U1506 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(n1356),
.Y(n653) );
OAI2BB1X1TS U1507 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n1355), .B0(n1256),
.Y(n524) );
AO21XLTS U1508 ( .A0(n1361), .A1(n1493), .B0(n1257), .Y(n1267) );
OAI2BB1X1TS U1509 ( .A0N(n1259), .A1N(n1491), .B0(n1258), .Y(n1260) );
NAND4XLTS U1510 ( .A(n1356), .B(n1267), .C(n1261), .D(n1260), .Y(n1262) );
NOR3BX1TS U1511 ( .AN(n1264), .B(n1263), .C(n1262), .Y(n1317) );
AOI2BB1XLTS U1512 ( .A0N(n1356), .A1N(LZD_output_NRM2_EW[3]), .B0(n1317),
.Y(n517) );
AOI22X1TS U1513 ( .A0(n1266), .A1(Raw_mant_NRM_SWR[5]), .B0(n1265), .B1(
Raw_mant_NRM_SWR[3]), .Y(n1268) );
OAI21X1TS U1514 ( .A0(n1272), .A1(n1271), .B0(n1356), .Y(n1313) );
OAI2BB1X1TS U1515 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1355), .B0(n1313),
.Y(n520) );
AO21XLTS U1516 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1355), .B0(n1273), .Y(n525) );
AO21XLTS U1517 ( .A0(LZD_output_NRM2_EW[0]), .A1(n1355), .B0(n1161), .Y(n521) );
OA22X1TS U1518 ( .A0(n1275), .A1(n1274), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n762) );
OA21XLTS U1519 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1392),
.Y(n565) );
INVX2TS U1520 ( .A(n1279), .Y(n1277) );
AOI22X1TS U1521 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1277), .B1(n1504), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1522 ( .A(n1277), .B(n1276), .Y(n878) );
NOR2XLTS U1523 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1278) );
AOI32X4TS U1524 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1278), .B1(n1540), .Y(n1282)
);
INVX2TS U1525 ( .A(n1282), .Y(n1281) );
AOI22X1TS U1526 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1279), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1504), .Y(n1283) );
AO22XLTS U1527 ( .A0(n1281), .A1(Shift_reg_FLAGS_7_6), .B0(n1282), .B1(n1283), .Y(n876) );
AOI22X1TS U1528 ( .A0(n1282), .A1(n1280), .B0(n1343), .B1(n1281), .Y(n875)
);
AOI22X1TS U1529 ( .A0(n1282), .A1(n1343), .B0(n1583), .B1(n1281), .Y(n874)
);
INVX4TS U1530 ( .A(n1617), .Y(n1363) );
AOI22X1TS U1531 ( .A0(n1282), .A1(n1617), .B0(n1355), .B1(n1281), .Y(n871)
);
AOI22X1TS U1532 ( .A0(n1282), .A1(n1355), .B0(n1455), .B1(n1281), .Y(n870)
);
BUFX4TS U1533 ( .A(n1287), .Y(n1288) );
BUFX3TS U1534 ( .A(n1287), .Y(n1289) );
BUFX3TS U1535 ( .A(n1287), .Y(n1286) );
AO22XLTS U1536 ( .A0(n1286), .A1(Data_X[2]), .B0(n880), .B1(intDX_EWSW[2]),
.Y(n867) );
BUFX3TS U1537 ( .A(n1287), .Y(n1292) );
AO22XLTS U1538 ( .A0(n1292), .A1(Data_X[3]), .B0(n880), .B1(intDX_EWSW[3]),
.Y(n866) );
AO22XLTS U1539 ( .A0(n1289), .A1(Data_X[4]), .B0(n1291), .B1(intDX_EWSW[4]),
.Y(n865) );
AO22XLTS U1540 ( .A0(n1288), .A1(Data_X[5]), .B0(n880), .B1(intDX_EWSW[5]),
.Y(n864) );
AO22XLTS U1541 ( .A0(n1288), .A1(Data_X[6]), .B0(n880), .B1(intDX_EWSW[6]),
.Y(n863) );
AO22XLTS U1542 ( .A0(n1287), .A1(Data_X[7]), .B0(n1291), .B1(intDX_EWSW[7]),
.Y(n862) );
AO22XLTS U1543 ( .A0(n1292), .A1(Data_X[8]), .B0(n880), .B1(intDX_EWSW[8]),
.Y(n861) );
AO22XLTS U1544 ( .A0(n1292), .A1(Data_X[9]), .B0(n880), .B1(intDX_EWSW[9]),
.Y(n860) );
AO22XLTS U1545 ( .A0(n1292), .A1(Data_X[11]), .B0(n1291), .B1(intDX_EWSW[11]), .Y(n858) );
AO22XLTS U1546 ( .A0(n1288), .A1(Data_X[12]), .B0(n880), .B1(intDX_EWSW[12]),
.Y(n857) );
AO22XLTS U1547 ( .A0(n1289), .A1(Data_X[13]), .B0(n880), .B1(intDX_EWSW[13]),
.Y(n856) );
AO22XLTS U1548 ( .A0(n1287), .A1(Data_X[14]), .B0(n1291), .B1(intDX_EWSW[14]), .Y(n855) );
INVX2TS U1549 ( .A(n1289), .Y(n1291) );
AO22XLTS U1550 ( .A0(n1288), .A1(Data_X[15]), .B0(n1291), .B1(intDX_EWSW[15]), .Y(n854) );
AO22XLTS U1551 ( .A0(n1286), .A1(Data_X[16]), .B0(n880), .B1(intDX_EWSW[16]),
.Y(n853) );
AO22XLTS U1552 ( .A0(n1288), .A1(Data_X[17]), .B0(n880), .B1(intDX_EWSW[17]),
.Y(n852) );
AO22XLTS U1553 ( .A0(n1287), .A1(Data_X[20]), .B0(n1291), .B1(intDX_EWSW[20]), .Y(n849) );
AO22XLTS U1554 ( .A0(n1289), .A1(Data_X[21]), .B0(n880), .B1(intDX_EWSW[21]),
.Y(n848) );
AO22XLTS U1555 ( .A0(n1289), .A1(Data_X[22]), .B0(n880), .B1(intDX_EWSW[22]),
.Y(n847) );
AO22XLTS U1556 ( .A0(n1286), .A1(Data_X[23]), .B0(n1291), .B1(intDX_EWSW[23]), .Y(n846) );
INVX2TS U1557 ( .A(n1287), .Y(n1284) );
AO22XLTS U1558 ( .A0(n1284), .A1(intDX_EWSW[24]), .B0(n1287), .B1(Data_X[24]), .Y(n845) );
AO22XLTS U1559 ( .A0(n1284), .A1(intDX_EWSW[25]), .B0(n1292), .B1(Data_X[25]), .Y(n844) );
AO22XLTS U1560 ( .A0(n1284), .A1(intDX_EWSW[26]), .B0(n1287), .B1(Data_X[26]), .Y(n843) );
AO22XLTS U1561 ( .A0(n1292), .A1(Data_X[28]), .B0(n880), .B1(intDX_EWSW[28]),
.Y(n841) );
AO22XLTS U1562 ( .A0(n1288), .A1(add_subt), .B0(n1284), .B1(intAS), .Y(n837)
);
AO22XLTS U1563 ( .A0(n1284), .A1(intDY_EWSW[0]), .B0(n1292), .B1(Data_Y[0]),
.Y(n835) );
AO22XLTS U1564 ( .A0(n1284), .A1(intDY_EWSW[1]), .B0(n1286), .B1(Data_Y[1]),
.Y(n834) );
AO22XLTS U1565 ( .A0(n1284), .A1(intDY_EWSW[2]), .B0(n1286), .B1(Data_Y[2]),
.Y(n833) );
AO22XLTS U1566 ( .A0(n1284), .A1(intDY_EWSW[3]), .B0(n1286), .B1(Data_Y[3]),
.Y(n832) );
AO22XLTS U1567 ( .A0(n1285), .A1(intDY_EWSW[4]), .B0(n1286), .B1(Data_Y[4]),
.Y(n831) );
AO22XLTS U1568 ( .A0(n1290), .A1(intDY_EWSW[5]), .B0(n1286), .B1(Data_Y[5]),
.Y(n830) );
INVX2TS U1569 ( .A(n1287), .Y(n1285) );
AO22XLTS U1570 ( .A0(n1290), .A1(intDY_EWSW[6]), .B0(n1286), .B1(Data_Y[6]),
.Y(n829) );
AO22XLTS U1571 ( .A0(n1285), .A1(intDY_EWSW[7]), .B0(n1286), .B1(Data_Y[7]),
.Y(n828) );
AO22XLTS U1572 ( .A0(n1290), .A1(intDY_EWSW[8]), .B0(n1286), .B1(Data_Y[8]),
.Y(n827) );
AO22XLTS U1573 ( .A0(n1285), .A1(intDY_EWSW[9]), .B0(n1287), .B1(Data_Y[9]),
.Y(n826) );
AO22XLTS U1574 ( .A0(n1290), .A1(intDY_EWSW[10]), .B0(n1288), .B1(Data_Y[10]), .Y(n825) );
AO22XLTS U1575 ( .A0(n1285), .A1(intDY_EWSW[11]), .B0(n1289), .B1(Data_Y[11]), .Y(n824) );
AO22XLTS U1576 ( .A0(n1290), .A1(intDY_EWSW[12]), .B0(n1288), .B1(Data_Y[12]), .Y(n823) );
AO22XLTS U1577 ( .A0(n1290), .A1(intDY_EWSW[13]), .B0(n1288), .B1(Data_Y[13]), .Y(n822) );
AO22XLTS U1578 ( .A0(n1285), .A1(intDY_EWSW[14]), .B0(n1288), .B1(Data_Y[14]), .Y(n821) );
AO22XLTS U1579 ( .A0(n1290), .A1(intDY_EWSW[15]), .B0(n1288), .B1(Data_Y[15]), .Y(n820) );
AO22XLTS U1580 ( .A0(n1290), .A1(intDY_EWSW[16]), .B0(n1288), .B1(Data_Y[16]), .Y(n819) );
AO22XLTS U1581 ( .A0(n1285), .A1(intDY_EWSW[17]), .B0(n1288), .B1(Data_Y[17]), .Y(n818) );
AO22XLTS U1582 ( .A0(n1290), .A1(intDY_EWSW[18]), .B0(n1288), .B1(Data_Y[18]), .Y(n817) );
AO22XLTS U1583 ( .A0(n1290), .A1(intDY_EWSW[19]), .B0(n1288), .B1(Data_Y[19]), .Y(n816) );
AO22XLTS U1584 ( .A0(n1285), .A1(intDY_EWSW[20]), .B0(n1288), .B1(Data_Y[20]), .Y(n815) );
AO22XLTS U1585 ( .A0(n1290), .A1(intDY_EWSW[21]), .B0(n1288), .B1(Data_Y[21]), .Y(n814) );
AO22XLTS U1586 ( .A0(n1290), .A1(intDY_EWSW[22]), .B0(n1292), .B1(Data_Y[22]), .Y(n813) );
AO22XLTS U1587 ( .A0(n1285), .A1(intDY_EWSW[23]), .B0(n1292), .B1(Data_Y[23]), .Y(n812) );
AO22XLTS U1588 ( .A0(n1285), .A1(intDY_EWSW[24]), .B0(n1292), .B1(Data_Y[24]), .Y(n811) );
AO22XLTS U1589 ( .A0(n1290), .A1(intDY_EWSW[25]), .B0(n1287), .B1(Data_Y[25]), .Y(n810) );
AO22XLTS U1590 ( .A0(n1290), .A1(intDY_EWSW[26]), .B0(n1286), .B1(Data_Y[26]), .Y(n809) );
AO22XLTS U1591 ( .A0(n1290), .A1(intDY_EWSW[27]), .B0(n1287), .B1(Data_Y[27]), .Y(n808) );
AO22XLTS U1592 ( .A0(n1290), .A1(intDY_EWSW[28]), .B0(n1287), .B1(Data_Y[28]), .Y(n807) );
AO22XLTS U1593 ( .A0(n1285), .A1(intDY_EWSW[29]), .B0(n1288), .B1(Data_Y[29]), .Y(n806) );
AO22XLTS U1594 ( .A0(n1290), .A1(intDY_EWSW[30]), .B0(n1289), .B1(Data_Y[30]), .Y(n805) );
AOI21X1TS U1595 ( .A0(n911), .A1(Raw_mant_NRM_SWR[0]), .B0(n915), .Y(n1294)
);
OAI2BB2XLTS U1596 ( .B0(n1294), .B1(n1160), .A0N(n1312), .A1N(
Data_array_SWR[25]), .Y(n803) );
OAI2BB2XLTS U1597 ( .B0(n1293), .B1(n1160), .A0N(n1312), .A1N(
Data_array_SWR[24]), .Y(n802) );
OAI222X1TS U1598 ( .A0(n1570), .A1(n1315), .B0(n1160), .B1(n1295), .C0(n1178), .C1(n1294), .Y(n801) );
AOI22X1TS U1599 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1161), .B0(n1299), .B1(
DmP_mant_SHT1_SW[13]), .Y(n1296) );
AOI21X1TS U1600 ( .A0(n915), .A1(DmP_mant_SHT1_SW[12]), .B0(n1297), .Y(n1303) );
OAI222X1TS U1601 ( .A0(n1315), .A1(n1574), .B0(n1160), .B1(n1303), .C0(n1178), .C1(n1298), .Y(n792) );
AOI22X1TS U1602 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1161), .B0(n1299), .B1(
n906), .Y(n1300) );
AOI21X1TS U1603 ( .A0(n915), .A1(DmP_mant_SHT1_SW[10]), .B0(n1302), .Y(n1304) );
OAI222X1TS U1604 ( .A0(n1573), .A1(n1315), .B0(n1160), .B1(n1304), .C0(n1178), .C1(n1303), .Y(n790) );
OAI222X1TS U1605 ( .A0(n1580), .A1(n1315), .B0(n1160), .B1(n1305), .C0(n1178), .C1(n1304), .Y(n788) );
AOI22X1TS U1606 ( .A0(n1312), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1307), .Y(n1311) );
AOI22X1TS U1607 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n911), .B0(n1309), .B1(
n1308), .Y(n1310) );
NAND2X1TS U1608 ( .A(n1311), .B(n1310), .Y(n778) );
AOI32X1TS U1609 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1315), .A2(n1355),
.B0(shift_value_SHT2_EWR[2]), .B1(n1312), .Y(n1314) );
NAND2X1TS U1610 ( .A(n1314), .B(n1313), .Y(n777) );
AOI21X1TS U1611 ( .A0(n879), .A1(Shift_amount_SHT1_EWR[3]), .B0(n1356), .Y(
n1316) );
OAI22X1TS U1612 ( .A0(n1317), .A1(n1316), .B0(n1315), .B1(n1532), .Y(n776)
);
INVX4TS U1613 ( .A(n1343), .Y(n1351) );
AOI21X1TS U1614 ( .A0(DMP_EXP_EWSW[23]), .A1(n930), .B0(n1322), .Y(n1318) );
INVX4TS U1615 ( .A(n1343), .Y(n1353) );
AOI2BB2XLTS U1616 ( .B0(n1351), .B1(n1318), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1353), .Y(n773) );
NOR2X1TS U1617 ( .A(n1510), .B(DMP_EXP_EWSW[24]), .Y(n1321) );
AOI21X1TS U1618 ( .A0(DMP_EXP_EWSW[24]), .A1(n1510), .B0(n1321), .Y(n1319)
);
XNOR2X1TS U1619 ( .A(n1322), .B(n1319), .Y(n1320) );
AO22XLTS U1620 ( .A0(n1353), .A1(n1320), .B0(n1343), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n772) );
INVX4TS U1621 ( .A(n1343), .Y(n1340) );
OAI22X1TS U1622 ( .A0(n1322), .A1(n1321), .B0(DmP_EXP_EWSW[24]), .B1(n1512),
.Y(n1325) );
NAND2X1TS U1623 ( .A(DmP_EXP_EWSW[25]), .B(n1563), .Y(n1326) );
OAI21XLTS U1624 ( .A0(DmP_EXP_EWSW[25]), .A1(n1563), .B0(n1326), .Y(n1323)
);
XNOR2X1TS U1625 ( .A(n1325), .B(n1323), .Y(n1324) );
AO22XLTS U1626 ( .A0(n1340), .A1(n1324), .B0(n1581), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n771) );
AOI22X1TS U1627 ( .A0(DMP_EXP_EWSW[25]), .A1(n1576), .B0(n1326), .B1(n1325),
.Y(n1329) );
NOR2X1TS U1628 ( .A(n1513), .B(DMP_EXP_EWSW[26]), .Y(n1330) );
AOI21X1TS U1629 ( .A0(DMP_EXP_EWSW[26]), .A1(n1513), .B0(n1330), .Y(n1327)
);
XNOR2X1TS U1630 ( .A(n1329), .B(n1327), .Y(n1328) );
AO22XLTS U1631 ( .A0(n1353), .A1(n1328), .B0(n1581), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n770) );
OAI22X1TS U1632 ( .A0(n1330), .A1(n1329), .B0(DmP_EXP_EWSW[26]), .B1(n1515),
.Y(n1332) );
XNOR2X1TS U1633 ( .A(DmP_EXP_EWSW[27]), .B(n908), .Y(n1331) );
XOR2XLTS U1634 ( .A(n1332), .B(n1331), .Y(n1333) );
BUFX3TS U1635 ( .A(n1581), .Y(n1342) );
AO22XLTS U1636 ( .A0(n1340), .A1(n1333), .B0(n1342), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n769) );
OAI222X1TS U1637 ( .A0(n1345), .A1(n1575), .B0(n1512), .B1(
Shift_reg_FLAGS_7_6), .C0(n1495), .C1(n1347), .Y(n736) );
OAI222X1TS U1638 ( .A0(n1345), .A1(n1514), .B0(n1563), .B1(
Shift_reg_FLAGS_7_6), .C0(n1621), .C1(n1347), .Y(n735) );
OAI222X1TS U1639 ( .A0(n1345), .A1(n1579), .B0(n1515), .B1(
Shift_reg_FLAGS_7_6), .C0(n1555), .C1(n1347), .Y(n734) );
OAI21XLTS U1640 ( .A0(n1335), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1334) );
AOI21X1TS U1641 ( .A0(n1335), .A1(intDX_EWSW[31]), .B0(n1334), .Y(n1337) );
AO21XLTS U1642 ( .A0(OP_FLAG_EXP), .A1(n1336), .B0(n1337), .Y(n729) );
AO22XLTS U1643 ( .A0(n1338), .A1(n1337), .B0(ZERO_FLAG_EXP), .B1(n1336), .Y(
n728) );
AO22XLTS U1644 ( .A0(n1340), .A1(DMP_EXP_EWSW[0]), .B0(n1342), .B1(
DMP_SHT1_EWSW[0]), .Y(n726) );
AO22XLTS U1645 ( .A0(busy), .A1(DMP_SHT1_EWSW[0]), .B0(n1583), .B1(
DMP_SHT2_EWSW[0]), .Y(n725) );
INVX2TS U1646 ( .A(n1481), .Y(n1488) );
AO22XLTS U1647 ( .A0(n1353), .A1(DMP_EXP_EWSW[1]), .B0(n1342), .B1(
DMP_SHT1_EWSW[1]), .Y(n723) );
AO22XLTS U1648 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n1583), .B1(
DMP_SHT2_EWSW[1]), .Y(n722) );
AO22XLTS U1649 ( .A0(n1340), .A1(DMP_EXP_EWSW[2]), .B0(n1342), .B1(
DMP_SHT1_EWSW[2]), .Y(n720) );
AO22XLTS U1650 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n1583), .B1(
DMP_SHT2_EWSW[2]), .Y(n719) );
BUFX3TS U1651 ( .A(n1339), .Y(n1461) );
INVX4TS U1652 ( .A(n1339), .Y(n1479) );
AO22XLTS U1653 ( .A0(n1461), .A1(DMP_SFG[2]), .B0(n1479), .B1(
DMP_SHT2_EWSW[2]), .Y(n718) );
AO22XLTS U1654 ( .A0(n1340), .A1(DMP_EXP_EWSW[3]), .B0(n1342), .B1(
DMP_SHT1_EWSW[3]), .Y(n717) );
AO22XLTS U1655 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n1583), .B1(
DMP_SHT2_EWSW[3]), .Y(n716) );
AO22XLTS U1656 ( .A0(n1461), .A1(DMP_SFG[3]), .B0(n1479), .B1(
DMP_SHT2_EWSW[3]), .Y(n715) );
AO22XLTS U1657 ( .A0(n1340), .A1(DMP_EXP_EWSW[4]), .B0(n1342), .B1(
DMP_SHT1_EWSW[4]), .Y(n714) );
AO22XLTS U1658 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1583), .B1(
DMP_SHT2_EWSW[4]), .Y(n713) );
AO22XLTS U1659 ( .A0(n1461), .A1(DMP_SFG[4]), .B0(n1479), .B1(
DMP_SHT2_EWSW[4]), .Y(n712) );
AO22XLTS U1660 ( .A0(n1340), .A1(DMP_EXP_EWSW[5]), .B0(n1342), .B1(
DMP_SHT1_EWSW[5]), .Y(n711) );
AO22XLTS U1661 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1583), .B1(
DMP_SHT2_EWSW[5]), .Y(n710) );
AO22XLTS U1662 ( .A0(n1488), .A1(DMP_SHT2_EWSW[5]), .B0(n1486), .B1(
DMP_SFG[5]), .Y(n709) );
AO22XLTS U1663 ( .A0(n1340), .A1(DMP_EXP_EWSW[6]), .B0(n1342), .B1(
DMP_SHT1_EWSW[6]), .Y(n708) );
AO22XLTS U1664 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n1583), .B1(
DMP_SHT2_EWSW[6]), .Y(n707) );
AO22XLTS U1665 ( .A0(n1481), .A1(DMP_SFG[6]), .B0(n1479), .B1(
DMP_SHT2_EWSW[6]), .Y(n706) );
AO22XLTS U1666 ( .A0(n1340), .A1(DMP_EXP_EWSW[7]), .B0(n1342), .B1(
DMP_SHT1_EWSW[7]), .Y(n705) );
AO22XLTS U1667 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n1583), .B1(
DMP_SHT2_EWSW[7]), .Y(n704) );
AO22XLTS U1668 ( .A0(n1461), .A1(DMP_SFG[7]), .B0(n1479), .B1(
DMP_SHT2_EWSW[7]), .Y(n703) );
AO22XLTS U1669 ( .A0(n1340), .A1(DMP_EXP_EWSW[8]), .B0(n1342), .B1(
DMP_SHT1_EWSW[8]), .Y(n702) );
AO22XLTS U1670 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n1583), .B1(
DMP_SHT2_EWSW[8]), .Y(n701) );
INVX4TS U1671 ( .A(n1339), .Y(n1469) );
AO22XLTS U1672 ( .A0(n1461), .A1(DMP_SFG[8]), .B0(n1469), .B1(
DMP_SHT2_EWSW[8]), .Y(n700) );
AO22XLTS U1673 ( .A0(n1340), .A1(DMP_EXP_EWSW[9]), .B0(n1342), .B1(
DMP_SHT1_EWSW[9]), .Y(n699) );
AO22XLTS U1674 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n1583), .B1(
DMP_SHT2_EWSW[9]), .Y(n698) );
AO22XLTS U1675 ( .A0(n1488), .A1(DMP_SHT2_EWSW[9]), .B0(n1486), .B1(
DMP_SFG[9]), .Y(n697) );
AO22XLTS U1676 ( .A0(n1340), .A1(DMP_EXP_EWSW[10]), .B0(n1342), .B1(
DMP_SHT1_EWSW[10]), .Y(n696) );
BUFX4TS U1677 ( .A(n1583), .Y(n1350) );
AO22XLTS U1678 ( .A0(n879), .A1(DMP_SHT1_EWSW[10]), .B0(n1350), .B1(
DMP_SHT2_EWSW[10]), .Y(n695) );
AO22XLTS U1679 ( .A0(n1481), .A1(DMP_SFG[10]), .B0(n1479), .B1(
DMP_SHT2_EWSW[10]), .Y(n694) );
BUFX4TS U1680 ( .A(n1581), .Y(n1344) );
AO22XLTS U1681 ( .A0(n1340), .A1(DMP_EXP_EWSW[11]), .B0(n1344), .B1(
DMP_SHT1_EWSW[11]), .Y(n693) );
AO22XLTS U1682 ( .A0(n879), .A1(DMP_SHT1_EWSW[11]), .B0(n1350), .B1(
DMP_SHT2_EWSW[11]), .Y(n692) );
AO22XLTS U1683 ( .A0(n1481), .A1(DMP_SFG[11]), .B0(n1479), .B1(
DMP_SHT2_EWSW[11]), .Y(n691) );
AO22XLTS U1684 ( .A0(n1340), .A1(DMP_EXP_EWSW[12]), .B0(n1581), .B1(
DMP_SHT1_EWSW[12]), .Y(n690) );
AO22XLTS U1685 ( .A0(n879), .A1(DMP_SHT1_EWSW[12]), .B0(n1350), .B1(
DMP_SHT2_EWSW[12]), .Y(n689) );
AO22XLTS U1686 ( .A0(n1461), .A1(DMP_SFG[12]), .B0(n1479), .B1(
DMP_SHT2_EWSW[12]), .Y(n688) );
BUFX3TS U1687 ( .A(n1581), .Y(n1352) );
AO22XLTS U1688 ( .A0(n1340), .A1(DMP_EXP_EWSW[13]), .B0(n1352), .B1(
DMP_SHT1_EWSW[13]), .Y(n687) );
AO22XLTS U1689 ( .A0(n879), .A1(DMP_SHT1_EWSW[13]), .B0(n1350), .B1(
DMP_SHT2_EWSW[13]), .Y(n686) );
AO22XLTS U1690 ( .A0(n1481), .A1(DMP_SFG[13]), .B0(n1479), .B1(
DMP_SHT2_EWSW[13]), .Y(n685) );
AO22XLTS U1691 ( .A0(n1340), .A1(DMP_EXP_EWSW[14]), .B0(n1344), .B1(
DMP_SHT1_EWSW[14]), .Y(n684) );
AO22XLTS U1692 ( .A0(n879), .A1(DMP_SHT1_EWSW[14]), .B0(n1350), .B1(
DMP_SHT2_EWSW[14]), .Y(n683) );
AO22XLTS U1693 ( .A0(n1461), .A1(DMP_SFG[14]), .B0(n1479), .B1(
DMP_SHT2_EWSW[14]), .Y(n682) );
AO22XLTS U1694 ( .A0(n1340), .A1(DMP_EXP_EWSW[15]), .B0(n1581), .B1(
DMP_SHT1_EWSW[15]), .Y(n681) );
AO22XLTS U1695 ( .A0(n879), .A1(DMP_SHT1_EWSW[15]), .B0(n1350), .B1(
DMP_SHT2_EWSW[15]), .Y(n680) );
AO22XLTS U1696 ( .A0(n1339), .A1(DMP_SFG[15]), .B0(n1479), .B1(
DMP_SHT2_EWSW[15]), .Y(n679) );
AO22XLTS U1697 ( .A0(n1340), .A1(DMP_EXP_EWSW[16]), .B0(n1352), .B1(
DMP_SHT1_EWSW[16]), .Y(n678) );
AO22XLTS U1698 ( .A0(busy), .A1(DMP_SHT1_EWSW[16]), .B0(n1350), .B1(
DMP_SHT2_EWSW[16]), .Y(n677) );
AO22XLTS U1699 ( .A0(n1481), .A1(DMP_SFG[16]), .B0(n1479), .B1(
DMP_SHT2_EWSW[16]), .Y(n676) );
AO22XLTS U1700 ( .A0(n1353), .A1(DMP_EXP_EWSW[17]), .B0(n1344), .B1(
DMP_SHT1_EWSW[17]), .Y(n675) );
AO22XLTS U1701 ( .A0(busy), .A1(DMP_SHT1_EWSW[17]), .B0(n1350), .B1(
DMP_SHT2_EWSW[17]), .Y(n674) );
AO22XLTS U1702 ( .A0(n1339), .A1(DMP_SFG[17]), .B0(n1469), .B1(
DMP_SHT2_EWSW[17]), .Y(n673) );
AO22XLTS U1703 ( .A0(n1353), .A1(DMP_EXP_EWSW[18]), .B0(n1343), .B1(
DMP_SHT1_EWSW[18]), .Y(n672) );
AO22XLTS U1704 ( .A0(busy), .A1(DMP_SHT1_EWSW[18]), .B0(n1350), .B1(
DMP_SHT2_EWSW[18]), .Y(n671) );
AO22XLTS U1705 ( .A0(n1461), .A1(DMP_SFG[18]), .B0(n1469), .B1(
DMP_SHT2_EWSW[18]), .Y(n670) );
AO22XLTS U1706 ( .A0(n1353), .A1(DMP_EXP_EWSW[19]), .B0(n1352), .B1(
DMP_SHT1_EWSW[19]), .Y(n669) );
AO22XLTS U1707 ( .A0(busy), .A1(DMP_SHT1_EWSW[19]), .B0(n1350), .B1(
DMP_SHT2_EWSW[19]), .Y(n668) );
AO22XLTS U1708 ( .A0(n1339), .A1(DMP_SFG[19]), .B0(n1469), .B1(
DMP_SHT2_EWSW[19]), .Y(n667) );
AO22XLTS U1709 ( .A0(n1353), .A1(DMP_EXP_EWSW[20]), .B0(n1344), .B1(
DMP_SHT1_EWSW[20]), .Y(n666) );
AO22XLTS U1710 ( .A0(busy), .A1(DMP_SHT1_EWSW[20]), .B0(n1350), .B1(
DMP_SHT2_EWSW[20]), .Y(n665) );
AO22XLTS U1711 ( .A0(n1339), .A1(DMP_SFG[20]), .B0(n1469), .B1(
DMP_SHT2_EWSW[20]), .Y(n664) );
AO22XLTS U1712 ( .A0(n1353), .A1(DMP_EXP_EWSW[21]), .B0(n1343), .B1(
DMP_SHT1_EWSW[21]), .Y(n663) );
AO22XLTS U1713 ( .A0(busy), .A1(DMP_SHT1_EWSW[21]), .B0(n1350), .B1(
DMP_SHT2_EWSW[21]), .Y(n662) );
AO22XLTS U1714 ( .A0(n1486), .A1(DMP_SFG[21]), .B0(n1469), .B1(
DMP_SHT2_EWSW[21]), .Y(n661) );
AO22XLTS U1715 ( .A0(n1353), .A1(DMP_EXP_EWSW[22]), .B0(n1352), .B1(
DMP_SHT1_EWSW[22]), .Y(n660) );
AO22XLTS U1716 ( .A0(busy), .A1(DMP_SHT1_EWSW[22]), .B0(n1583), .B1(
DMP_SHT2_EWSW[22]), .Y(n659) );
AO22XLTS U1717 ( .A0(n1461), .A1(DMP_SFG[22]), .B0(n1469), .B1(
DMP_SHT2_EWSW[22]), .Y(n658) );
AO22XLTS U1718 ( .A0(n1353), .A1(DMP_EXP_EWSW[23]), .B0(n1352), .B1(
DMP_SHT1_EWSW[23]), .Y(n657) );
AO22XLTS U1719 ( .A0(n879), .A1(DMP_SHT1_EWSW[23]), .B0(n1583), .B1(
DMP_SHT2_EWSW[23]), .Y(n656) );
AO22XLTS U1720 ( .A0(n1488), .A1(DMP_SHT2_EWSW[23]), .B0(n1486), .B1(
DMP_SFG[23]), .Y(n655) );
AO22XLTS U1721 ( .A0(n1363), .A1(DMP_SFG[23]), .B0(n1390), .B1(
DMP_exp_NRM_EW[0]), .Y(n654) );
AO22XLTS U1722 ( .A0(n1353), .A1(DMP_EXP_EWSW[24]), .B0(n1352), .B1(
DMP_SHT1_EWSW[24]), .Y(n652) );
AO22XLTS U1723 ( .A0(n879), .A1(DMP_SHT1_EWSW[24]), .B0(n1350), .B1(
DMP_SHT2_EWSW[24]), .Y(n651) );
AO22XLTS U1724 ( .A0(n1488), .A1(DMP_SHT2_EWSW[24]), .B0(n1486), .B1(
DMP_SFG[24]), .Y(n650) );
AO22XLTS U1725 ( .A0(n1363), .A1(DMP_SFG[24]), .B0(n1617), .B1(
DMP_exp_NRM_EW[1]), .Y(n649) );
AO22XLTS U1726 ( .A0(n1353), .A1(DMP_EXP_EWSW[25]), .B0(n1352), .B1(
DMP_SHT1_EWSW[25]), .Y(n647) );
AO22XLTS U1727 ( .A0(n879), .A1(DMP_SHT1_EWSW[25]), .B0(n1350), .B1(
DMP_SHT2_EWSW[25]), .Y(n646) );
AO22XLTS U1728 ( .A0(n1488), .A1(DMP_SHT2_EWSW[25]), .B0(n1486), .B1(
DMP_SFG[25]), .Y(n645) );
AO22XLTS U1729 ( .A0(n1363), .A1(DMP_SFG[25]), .B0(n1617), .B1(
DMP_exp_NRM_EW[2]), .Y(n644) );
AO22XLTS U1730 ( .A0(n1353), .A1(DMP_EXP_EWSW[26]), .B0(n1352), .B1(
DMP_SHT1_EWSW[26]), .Y(n642) );
AO22XLTS U1731 ( .A0(n879), .A1(DMP_SHT1_EWSW[26]), .B0(n1350), .B1(
DMP_SHT2_EWSW[26]), .Y(n641) );
AO22XLTS U1732 ( .A0(n1469), .A1(DMP_SHT2_EWSW[26]), .B0(n1461), .B1(
DMP_SFG[26]), .Y(n640) );
AO22XLTS U1733 ( .A0(n1363), .A1(DMP_SFG[26]), .B0(n1617), .B1(
DMP_exp_NRM_EW[3]), .Y(n639) );
AO22XLTS U1734 ( .A0(n1353), .A1(n908), .B0(n1352), .B1(DMP_SHT1_EWSW[27]),
.Y(n637) );
AO22XLTS U1735 ( .A0(n879), .A1(DMP_SHT1_EWSW[27]), .B0(n1350), .B1(
DMP_SHT2_EWSW[27]), .Y(n636) );
AO22XLTS U1736 ( .A0(n1469), .A1(DMP_SHT2_EWSW[27]), .B0(n1481), .B1(
DMP_SFG[27]), .Y(n635) );
AO22XLTS U1737 ( .A0(n1363), .A1(DMP_SFG[27]), .B0(n1617), .B1(
DMP_exp_NRM_EW[4]), .Y(n634) );
AO22XLTS U1738 ( .A0(n1353), .A1(DMP_EXP_EWSW[28]), .B0(n1352), .B1(
DMP_SHT1_EWSW[28]), .Y(n632) );
AO22XLTS U1739 ( .A0(n879), .A1(DMP_SHT1_EWSW[28]), .B0(n1350), .B1(
DMP_SHT2_EWSW[28]), .Y(n631) );
AO22XLTS U1740 ( .A0(n1469), .A1(DMP_SHT2_EWSW[28]), .B0(n1461), .B1(
DMP_SFG[28]), .Y(n630) );
BUFX4TS U1741 ( .A(n1617), .Y(n1390) );
AO22XLTS U1742 ( .A0(n1363), .A1(DMP_SFG[28]), .B0(n1390), .B1(
DMP_exp_NRM_EW[5]), .Y(n629) );
AO22XLTS U1743 ( .A0(n1353), .A1(DMP_EXP_EWSW[29]), .B0(n1352), .B1(
DMP_SHT1_EWSW[29]), .Y(n627) );
AO22XLTS U1744 ( .A0(n879), .A1(DMP_SHT1_EWSW[29]), .B0(n1350), .B1(
DMP_SHT2_EWSW[29]), .Y(n626) );
AO22XLTS U1745 ( .A0(n1488), .A1(DMP_SHT2_EWSW[29]), .B0(n1481), .B1(
DMP_SFG[29]), .Y(n625) );
AO22XLTS U1746 ( .A0(n1363), .A1(DMP_SFG[29]), .B0(n1390), .B1(
DMP_exp_NRM_EW[6]), .Y(n624) );
AO22XLTS U1747 ( .A0(n1496), .A1(DMP_EXP_EWSW[30]), .B0(n1352), .B1(
DMP_SHT1_EWSW[30]), .Y(n622) );
AO22XLTS U1748 ( .A0(n879), .A1(DMP_SHT1_EWSW[30]), .B0(n1350), .B1(
DMP_SHT2_EWSW[30]), .Y(n621) );
AO22XLTS U1749 ( .A0(n1469), .A1(DMP_SHT2_EWSW[30]), .B0(n1461), .B1(
DMP_SFG[30]), .Y(n620) );
AO22XLTS U1750 ( .A0(n1363), .A1(DMP_SFG[30]), .B0(n1390), .B1(
DMP_exp_NRM_EW[7]), .Y(n619) );
AO22XLTS U1751 ( .A0(n1496), .A1(DmP_EXP_EWSW[3]), .B0(n1581), .B1(
DmP_mant_SHT1_SW[3]), .Y(n610) );
AO22XLTS U1752 ( .A0(n1496), .A1(DmP_EXP_EWSW[7]), .B0(n1343), .B1(
DmP_mant_SHT1_SW[7]), .Y(n602) );
AO22XLTS U1753 ( .A0(n1351), .A1(DmP_EXP_EWSW[10]), .B0(n1343), .B1(
DmP_mant_SHT1_SW[10]), .Y(n596) );
AO22XLTS U1754 ( .A0(n1351), .A1(DmP_EXP_EWSW[11]), .B0(n1343), .B1(n906),
.Y(n594) );
OAI222X1TS U1755 ( .A0(n1347), .A1(n1575), .B0(n1510), .B1(
Shift_reg_FLAGS_7_6), .C0(n1495), .C1(n1345), .Y(n570) );
OAI222X1TS U1756 ( .A0(n1347), .A1(n1514), .B0(n1576), .B1(
Shift_reg_FLAGS_7_6), .C0(n1621), .C1(n1345), .Y(n569) );
OAI222X1TS U1757 ( .A0(n1347), .A1(n1579), .B0(n1513), .B1(
Shift_reg_FLAGS_7_6), .C0(n1555), .C1(n1345), .Y(n568) );
INVX4TS U1758 ( .A(n1348), .Y(n1452) );
NAND2X1TS U1759 ( .A(n1393), .B(Shift_reg_FLAGS_7[0]), .Y(n1349) );
OAI2BB1X1TS U1760 ( .A0N(underflow_flag), .A1N(n1452), .B0(n1349), .Y(n566)
);
AO22XLTS U1761 ( .A0(n1351), .A1(ZERO_FLAG_EXP), .B0(n1343), .B1(
ZERO_FLAG_SHT1), .Y(n564) );
AO22XLTS U1762 ( .A0(n879), .A1(ZERO_FLAG_SHT1), .B0(n1350), .B1(
ZERO_FLAG_SHT2), .Y(n563) );
AO22XLTS U1763 ( .A0(n1469), .A1(ZERO_FLAG_SHT2), .B0(n1481), .B1(
ZERO_FLAG_SFG), .Y(n562) );
AO22XLTS U1764 ( .A0(n1363), .A1(ZERO_FLAG_SFG), .B0(n1390), .B1(
ZERO_FLAG_NRM), .Y(n561) );
AO22XLTS U1765 ( .A0(n1356), .A1(ZERO_FLAG_NRM), .B0(n1355), .B1(
ZERO_FLAG_SHT1SHT2), .Y(n560) );
AO22XLTS U1766 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1452), .B1(zero_flag), .Y(n559) );
AO22XLTS U1767 ( .A0(n1351), .A1(OP_FLAG_EXP), .B0(OP_FLAG_SHT1), .B1(n1581),
.Y(n558) );
AO22XLTS U1768 ( .A0(n879), .A1(OP_FLAG_SHT1), .B0(n1583), .B1(OP_FLAG_SHT2),
.Y(n557) );
AO22XLTS U1769 ( .A0(n1339), .A1(OP_FLAG_SFG), .B0(n1469), .B1(OP_FLAG_SHT2),
.Y(n556) );
AO22XLTS U1770 ( .A0(n1353), .A1(SIGN_FLAG_EXP), .B0(n1352), .B1(
SIGN_FLAG_SHT1), .Y(n555) );
AO22XLTS U1771 ( .A0(n879), .A1(SIGN_FLAG_SHT1), .B0(n1583), .B1(
SIGN_FLAG_SHT2), .Y(n554) );
AO22XLTS U1772 ( .A0(n1469), .A1(SIGN_FLAG_SHT2), .B0(n1481), .B1(
SIGN_FLAG_SFG), .Y(n553) );
AO22XLTS U1773 ( .A0(n1363), .A1(SIGN_FLAG_SFG), .B0(n1617), .B1(
SIGN_FLAG_NRM), .Y(n552) );
AO22XLTS U1774 ( .A0(n1356), .A1(SIGN_FLAG_NRM), .B0(n1355), .B1(
SIGN_FLAG_SHT1SHT2), .Y(n551) );
AOI2BB2XLTS U1775 ( .B0(n1364), .B1(intadd_14_SUM_0_), .A0N(
Raw_mant_NRM_SWR[4]), .A1N(n1363), .Y(n549) );
AOI22X1TS U1776 ( .A0(n1364), .A1(intadd_14_SUM_1_), .B0(n1524), .B1(n1390),
.Y(n548) );
AOI22X1TS U1777 ( .A0(n1364), .A1(intadd_14_SUM_2_), .B0(n1571), .B1(n1390),
.Y(n547) );
XNOR2X1TS U1778 ( .A(DMP_SFG[5]), .B(n898), .Y(n1357) );
XNOR2X1TS U1779 ( .A(intadd_14_n1), .B(n1357), .Y(n1358) );
AOI22X1TS U1780 ( .A0(n1364), .A1(n1358), .B0(n1517), .B1(n1390), .Y(n546)
);
AOI22X1TS U1781 ( .A0(n1364), .A1(intadd_13_SUM_0_), .B0(n1527), .B1(n1390),
.Y(n545) );
AOI22X1TS U1782 ( .A0(n1364), .A1(intadd_13_SUM_1_), .B0(n1492), .B1(n1390),
.Y(n544) );
AOI22X1TS U1783 ( .A0(n1364), .A1(intadd_13_SUM_2_), .B0(n1490), .B1(n1390),
.Y(n543) );
XNOR2X1TS U1784 ( .A(DMP_SFG[9]), .B(n1359), .Y(n1360) );
XNOR2X1TS U1785 ( .A(intadd_13_n1), .B(n1360), .Y(n1362) );
AOI22X1TS U1786 ( .A0(n939), .A1(n1362), .B0(n1361), .B1(n1390), .Y(n542) );
AOI2BB2XLTS U1787 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n919), .A0N(n919), .A1N(
DmP_mant_SFG_SWR[12]), .Y(intadd_12_CI) );
AOI2BB2XLTS U1788 ( .B0(n1364), .B1(intadd_12_SUM_0_), .A0N(
Raw_mant_NRM_SWR[12]), .A1N(n1363), .Y(n541) );
AOI2BB2XLTS U1789 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n919), .A0N(n919), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_12_B_1_) );
AOI22X1TS U1790 ( .A0(n939), .A1(intadd_12_SUM_1_), .B0(n1493), .B1(n1390),
.Y(n540) );
AOI2BB2XLTS U1791 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n919), .A0N(n919), .A1N(
DmP_mant_SFG_SWR[14]), .Y(intadd_12_B_2_) );
AOI22X1TS U1792 ( .A0(n939), .A1(intadd_12_SUM_2_), .B0(n1491), .B1(n1390),
.Y(n539) );
AOI2BB2XLTS U1793 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n919), .A0N(n919), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_12_B_3_) );
AOI2BB2XLTS U1794 ( .B0(n1364), .B1(intadd_12_SUM_3_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1363), .Y(n538) );
AOI22X1TS U1795 ( .A0(DmP_mant_SFG_SWR[16]), .A1(n1616), .B0(n1389), .B1(
n921), .Y(intadd_12_B_4_) );
AOI22X1TS U1796 ( .A0(n1364), .A1(intadd_12_SUM_4_), .B0(n1511), .B1(n1390),
.Y(n537) );
AOI22X1TS U1797 ( .A0(DmP_mant_SFG_SWR[17]), .A1(n1616), .B0(n1389), .B1(
n922), .Y(intadd_12_B_5_) );
AOI22X1TS U1798 ( .A0(n939), .A1(intadd_12_SUM_5_), .B0(n1502), .B1(n1390),
.Y(n536) );
AOI22X1TS U1799 ( .A0(DmP_mant_SFG_SWR[18]), .A1(n1616), .B0(n1389), .B1(
n923), .Y(intadd_12_B_6_) );
AOI2BB2XLTS U1800 ( .B0(n1364), .B1(intadd_12_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1363), .Y(n535) );
AOI22X1TS U1801 ( .A0(DmP_mant_SFG_SWR[19]), .A1(n919), .B0(n1389), .B1(n924), .Y(intadd_12_B_7_) );
AOI2BB2XLTS U1802 ( .B0(n1364), .B1(intadd_12_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1363), .Y(n534) );
AOI22X1TS U1803 ( .A0(DmP_mant_SFG_SWR[20]), .A1(n919), .B0(n1389), .B1(n925), .Y(intadd_12_B_8_) );
AOI2BB2XLTS U1804 ( .B0(n1364), .B1(intadd_12_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1363), .Y(n533) );
AOI22X1TS U1805 ( .A0(DmP_mant_SFG_SWR[21]), .A1(n919), .B0(n1389), .B1(n926), .Y(intadd_12_B_9_) );
AOI22X1TS U1806 ( .A0(n939), .A1(intadd_12_SUM_9_), .B0(n1499), .B1(n1390),
.Y(n532) );
AOI22X1TS U1807 ( .A0(DmP_mant_SFG_SWR[22]), .A1(n1616), .B0(OP_FLAG_SFG),
.B1(n927), .Y(intadd_12_B_10_) );
AOI22X1TS U1808 ( .A0(n939), .A1(intadd_12_SUM_10_), .B0(n1497), .B1(n1390),
.Y(n531) );
AOI2BB2XLTS U1809 ( .B0(DmP_mant_SFG_SWR[23]), .B1(n919), .A0N(n1616), .A1N(
DmP_mant_SFG_SWR[23]), .Y(intadd_12_B_11_) );
AOI22X1TS U1810 ( .A0(n939), .A1(intadd_12_SUM_11_), .B0(n1489), .B1(n1617),
.Y(n530) );
AOI22X1TS U1811 ( .A0(DmP_mant_SFG_SWR[24]), .A1(n919), .B0(OP_FLAG_SFG),
.B1(n928), .Y(intadd_12_B_12_) );
AOI22X1TS U1812 ( .A0(n939), .A1(intadd_12_SUM_12_), .B0(n1494), .B1(n1617),
.Y(n529) );
AOI22X1TS U1813 ( .A0(DmP_mant_SFG_SWR[25]), .A1(OP_FLAG_SFG), .B0(n1616),
.B1(n929), .Y(n1365) );
XNOR2X1TS U1814 ( .A(intadd_12_n1), .B(n1365), .Y(n1366) );
AOI22X1TS U1815 ( .A0(n939), .A1(n1366), .B0(n1516), .B1(n1617), .Y(n528) );
INVX2TS U1816 ( .A(n1426), .Y(n1409) );
NAND2X1TS U1817 ( .A(n1485), .B(n1395), .Y(n1381) );
AOI22X1TS U1818 ( .A0(Data_array_SWR[23]), .A1(n1427), .B0(
Data_array_SWR[19]), .B1(n1426), .Y(n1421) );
AND2X4TS U1819 ( .A(n1427), .B(n1518), .Y(n1438) );
AOI22X1TS U1820 ( .A0(Data_array_SWR[11]), .A1(n1439), .B0(Data_array_SWR[7]), .B1(n1438), .Y(n1371) );
NOR3X1TS U1821 ( .A(shift_value_SHT2_EWR[4]), .B(n1503), .C(n1532), .Y(n1369) );
AOI22X1TS U1822 ( .A0(Data_array_SWR[15]), .A1(n1437), .B0(Data_array_SWR[3]), .B1(n1395), .Y(n1370) );
OAI211X1TS U1823 ( .A0(n1421), .A1(n1518), .B0(n1371), .C0(n1370), .Y(n1448)
);
AO22XLTS U1824 ( .A0(Data_array_SWR[22]), .A1(n1367), .B0(n1450), .B1(n1448),
.Y(n1435) );
XNOR2X1TS U1825 ( .A(DMP_SFG[1]), .B(n1382), .Y(n1373) );
XNOR2X1TS U1826 ( .A(n1373), .B(n1372), .Y(n1374) );
AOI22X1TS U1827 ( .A0(n939), .A1(n1374), .B0(n1564), .B1(n1617), .Y(n526) );
NOR2X1TS U1828 ( .A(shift_value_SHT2_EWR[2]), .B(n1532), .Y(n1385) );
AOI22X1TS U1829 ( .A0(Data_array_SWR[13]), .A1(n1437), .B0(Data_array_SWR[9]), .B1(n1439), .Y(n1376) );
AOI22X1TS U1830 ( .A0(Data_array_SWR[5]), .A1(n1438), .B0(Data_array_SWR[1]),
.B1(n1395), .Y(n1375) );
OAI211X1TS U1831 ( .A0(n1443), .A1(n1518), .B0(n1376), .C0(n1375), .Y(n1454)
);
AOI22X1TS U1832 ( .A0(Data_array_SWR[24]), .A1(n1367), .B0(n1450), .B1(n1454), .Y(n1377) );
AOI22X1TS U1833 ( .A0(n1488), .A1(n1377), .B0(n1486), .B1(n931), .Y(n523) );
AOI22X1TS U1834 ( .A0(DmP_mant_SFG_SWR[1]), .A1(n918), .B0(OP_FLAG_SFG),
.B1(n931), .Y(n1378) );
AOI22X1TS U1835 ( .A0(n939), .A1(n1378), .B0(n1572), .B1(n1617), .Y(n522) );
AO22XLTS U1836 ( .A0(Data_array_SWR[14]), .A1(n1437), .B0(Data_array_SWR[10]), .B1(n1439), .Y(n1380) );
AO22X1TS U1837 ( .A0(Data_array_SWR[22]), .A1(n1427), .B0(Data_array_SWR[18]), .B1(n1426), .Y(n1417) );
AO22XLTS U1838 ( .A0(n1417), .A1(shift_value_SHT2_EWR[4]), .B0(
Data_array_SWR[6]), .B1(n1438), .Y(n1379) );
AOI211X1TS U1839 ( .A0(Data_array_SWR[2]), .A1(n1395), .B0(n1380), .C0(n1379), .Y(n1451) );
OAI22X1TS U1840 ( .A0(n1485), .A1(n1451), .B0(n1570), .B1(n1381), .Y(n1436)
);
AO22XLTS U1841 ( .A0(n1488), .A1(n1436), .B0(n1486), .B1(DmP_mant_SFG_SWR[2]), .Y(n519) );
OAI21XLTS U1842 ( .A0(n1383), .A1(DMP_SFG[0]), .B0(n1382), .Y(n1384) );
AOI22X1TS U1843 ( .A0(n939), .A1(n1384), .B0(n1519), .B1(n1617), .Y(n518) );
AOI22X1TS U1844 ( .A0(Data_array_SWR[12]), .A1(n1437), .B0(Data_array_SWR[8]), .B1(n1439), .Y(n1387) );
AOI22X1TS U1845 ( .A0(Data_array_SWR[4]), .A1(n1438), .B0(Data_array_SWR[0]),
.B1(n1395), .Y(n1386) );
OAI211X1TS U1846 ( .A0(n1412), .A1(n1518), .B0(n1387), .C0(n1386), .Y(n1484)
);
AOI22X1TS U1847 ( .A0(Data_array_SWR[25]), .A1(n1367), .B0(n1450), .B1(n1484), .Y(n1388) );
AOI22X1TS U1848 ( .A0(n1483), .A1(n1388), .B0(n1486), .B1(n932), .Y(n516) );
AOI22X1TS U1849 ( .A0(DmP_mant_SFG_SWR[0]), .A1(n919), .B0(n1389), .B1(n932),
.Y(n1391) );
AOI22X1TS U1850 ( .A0(n1363), .A1(n1391), .B0(n1501), .B1(n1390), .Y(n515)
);
NAND2X1TS U1851 ( .A(n1450), .B(n1395), .Y(n1449) );
AOI22X1TS U1852 ( .A0(Data_array_SWR[12]), .A1(n1396), .B0(
Data_array_SWR[13]), .B1(n1367), .Y(n1397) );
OAI221X1TS U1853 ( .A0(n1485), .A1(n1399), .B0(n1450), .B1(n1400), .C0(n1397), .Y(n1466) );
AO22XLTS U1854 ( .A0(n1394), .A1(n1466), .B0(final_result_ieee[10]), .B1(
n1452), .Y(n514) );
AOI22X1TS U1855 ( .A0(Data_array_SWR[12]), .A1(n1367), .B0(
Data_array_SWR[13]), .B1(n1396), .Y(n1398) );
OAI221X1TS U1856 ( .A0(n1485), .A1(n1400), .B0(n1450), .B1(n1399), .C0(n1398), .Y(n1467) );
AO22XLTS U1857 ( .A0(n1394), .A1(n1467), .B0(final_result_ieee[11]), .B1(
n1452), .Y(n513) );
AOI22X1TS U1858 ( .A0(Data_array_SWR[22]), .A1(n1439), .B0(
Data_array_SWR[18]), .B1(n1438), .Y(n1404) );
AOI22X1TS U1859 ( .A0(Data_array_SWR[14]), .A1(n1367), .B0(
Data_array_SWR[11]), .B1(n1396), .Y(n1401) );
OAI221X1TS U1860 ( .A0(n1485), .A1(n1403), .B0(n1450), .B1(n1404), .C0(n1401), .Y(n1465) );
AO22XLTS U1861 ( .A0(n1394), .A1(n1465), .B0(final_result_ieee[9]), .B1(
n1452), .Y(n512) );
AOI22X1TS U1862 ( .A0(Data_array_SWR[14]), .A1(n1396), .B0(
Data_array_SWR[11]), .B1(n1367), .Y(n1402) );
OAI221X1TS U1863 ( .A0(n1485), .A1(n1404), .B0(n1450), .B1(n1403), .C0(n1402), .Y(n1468) );
AO22XLTS U1864 ( .A0(n1394), .A1(n1468), .B0(final_result_ieee[12]), .B1(
n1452), .Y(n511) );
AOI22X1TS U1865 ( .A0(Data_array_SWR[23]), .A1(n1439), .B0(
Data_array_SWR[19]), .B1(n1438), .Y(n1408) );
AOI22X1TS U1866 ( .A0(Data_array_SWR[10]), .A1(n1396), .B0(
Data_array_SWR[15]), .B1(n1367), .Y(n1405) );
OAI221X1TS U1867 ( .A0(n1485), .A1(n1407), .B0(n1450), .B1(n1408), .C0(n1405), .Y(n1464) );
AO22XLTS U1868 ( .A0(n1394), .A1(n1464), .B0(final_result_ieee[8]), .B1(
n1452), .Y(n510) );
AOI22X1TS U1869 ( .A0(Data_array_SWR[10]), .A1(n1367), .B0(
Data_array_SWR[15]), .B1(n1396), .Y(n1406) );
OAI221X1TS U1870 ( .A0(n1485), .A1(n1408), .B0(n1450), .B1(n1407), .C0(n1406), .Y(n1470) );
AO22XLTS U1871 ( .A0(n1394), .A1(n1470), .B0(final_result_ieee[13]), .B1(
n1452), .Y(n509) );
AOI22X1TS U1872 ( .A0(Data_array_SWR[21]), .A1(n1437), .B0(
Data_array_SWR[13]), .B1(n1438), .Y(n1411) );
NOR2X2TS U1873 ( .A(n1518), .B(n1409), .Y(n1440) );
AOI22X1TS U1874 ( .A0(Data_array_SWR[17]), .A1(n1439), .B0(
Data_array_SWR[25]), .B1(n1440), .Y(n1410) );
NAND2X1TS U1875 ( .A(n1411), .B(n1410), .Y(n1414) );
INVX2TS U1876 ( .A(n1412), .Y(n1413) );
OAI2BB2XLTS U1877 ( .B0(n1463), .B1(n1456), .A0N(final_result_ieee[7]),
.A1N(n1452), .Y(n508) );
OAI2BB2XLTS U1878 ( .B0(n1471), .B1(n1456), .A0N(final_result_ieee[14]),
.A1N(n1452), .Y(n507) );
AOI22X1TS U1879 ( .A0(Data_array_SWR[19]), .A1(n1437), .B0(
Data_array_SWR[11]), .B1(n1438), .Y(n1416) );
AOI22X1TS U1880 ( .A0(Data_array_SWR[23]), .A1(n1440), .B0(
Data_array_SWR[15]), .B1(n1439), .Y(n1415) );
NAND2X1TS U1881 ( .A(n1416), .B(n1415), .Y(n1418) );
OAI2BB2XLTS U1882 ( .B0(n1460), .B1(n1456), .A0N(final_result_ieee[5]),
.A1N(n1452), .Y(n506) );
OAI2BB2XLTS U1883 ( .B0(n1473), .B1(n1456), .A0N(final_result_ieee[16]),
.A1N(n1455), .Y(n505) );
AOI22X1TS U1884 ( .A0(Data_array_SWR[10]), .A1(n1438), .B0(
Data_array_SWR[18]), .B1(n1437), .Y(n1420) );
AOI22X1TS U1885 ( .A0(Data_array_SWR[14]), .A1(n1439), .B0(
Data_array_SWR[22]), .B1(n1440), .Y(n1419) );
NAND2X1TS U1886 ( .A(n1420), .B(n1419), .Y(n1423) );
INVX2TS U1887 ( .A(n1421), .Y(n1422) );
OAI2BB2XLTS U1888 ( .B0(n1459), .B1(n1456), .A0N(final_result_ieee[4]),
.A1N(n1455), .Y(n504) );
OAI2BB2XLTS U1889 ( .B0(n1474), .B1(n1456), .A0N(final_result_ieee[17]),
.A1N(n1455), .Y(n503) );
AOI22X1TS U1890 ( .A0(Data_array_SWR[21]), .A1(n1426), .B0(
Data_array_SWR[25]), .B1(n1427), .Y(n1432) );
AOI22X1TS U1891 ( .A0(Data_array_SWR[17]), .A1(n1437), .B0(Data_array_SWR[9]), .B1(n1438), .Y(n1425) );
NAND2X1TS U1892 ( .A(Data_array_SWR[13]), .B(n1439), .Y(n1424) );
OAI211X1TS U1893 ( .A0(n1432), .A1(n1518), .B0(n1425), .C0(n1424), .Y(n1428)
);
AO22X1TS U1894 ( .A0(Data_array_SWR[24]), .A1(n1427), .B0(Data_array_SWR[20]), .B1(n1426), .Y(n1429) );
OAI2BB2XLTS U1895 ( .B0(n1458), .B1(n1456), .A0N(final_result_ieee[3]),
.A1N(n1455), .Y(n502) );
OAI2BB2XLTS U1896 ( .B0(n1475), .B1(n1456), .A0N(final_result_ieee[18]),
.A1N(n1455), .Y(n501) );
AOI22X1TS U1897 ( .A0(Data_array_SWR[16]), .A1(n1437), .B0(Data_array_SWR[8]), .B1(n1438), .Y(n1431) );
AOI22X1TS U1898 ( .A0(Data_array_SWR[12]), .A1(n1439), .B0(
shift_value_SHT2_EWR[4]), .B1(n1429), .Y(n1430) );
NAND2X1TS U1899 ( .A(n1431), .B(n1430), .Y(n1434) );
INVX2TS U1900 ( .A(n1432), .Y(n1433) );
OAI2BB2XLTS U1901 ( .B0(n1457), .B1(n1456), .A0N(final_result_ieee[2]),
.A1N(n1455), .Y(n500) );
OAI2BB2XLTS U1902 ( .B0(n1476), .B1(n1456), .A0N(final_result_ieee[19]),
.A1N(n1455), .Y(n499) );
AO22XLTS U1903 ( .A0(n1394), .A1(n1435), .B0(final_result_ieee[1]), .B1(
n1452), .Y(n498) );
AO22XLTS U1904 ( .A0(n1394), .A1(n1436), .B0(final_result_ieee[0]), .B1(
n1452), .Y(n497) );
AOI22X1TS U1905 ( .A0(Data_array_SWR[12]), .A1(n1438), .B0(
Data_array_SWR[20]), .B1(n1437), .Y(n1442) );
AOI22X1TS U1906 ( .A0(Data_array_SWR[24]), .A1(n1440), .B0(
Data_array_SWR[16]), .B1(n1439), .Y(n1441) );
NAND2X1TS U1907 ( .A(n1442), .B(n1441), .Y(n1447) );
INVX2TS U1908 ( .A(n1443), .Y(n1446) );
OAI2BB2XLTS U1909 ( .B0(n1472), .B1(n1456), .A0N(final_result_ieee[15]),
.A1N(n1452), .Y(n495) );
AOI22X1TS U1910 ( .A0(Data_array_SWR[22]), .A1(n1396), .B0(n1485), .B1(n1448), .Y(n1477) );
OAI2BB2XLTS U1911 ( .B0(n1477), .B1(n1456), .A0N(final_result_ieee[20]),
.A1N(n1455), .Y(n494) );
OAI22X1TS U1912 ( .A0(n1451), .A1(n1450), .B0(n1570), .B1(n1449), .Y(n1478)
);
AO22XLTS U1913 ( .A0(n1394), .A1(n1478), .B0(final_result_ieee[21]), .B1(
n1452), .Y(n493) );
AOI22X1TS U1914 ( .A0(Data_array_SWR[24]), .A1(n1396), .B0(n1485), .B1(n1454), .Y(n1482) );
OAI2BB2XLTS U1915 ( .B0(n1482), .B1(n1456), .A0N(final_result_ieee[22]),
.A1N(n1455), .Y(n492) );
AOI22X1TS U1916 ( .A0(n1483), .A1(n1457), .B0(n1486), .B1(n933), .Y(n491) );
AOI22X1TS U1917 ( .A0(n1483), .A1(n1458), .B0(n1486), .B1(n934), .Y(n490) );
AOI22X1TS U1918 ( .A0(n1483), .A1(n1459), .B0(n936), .B1(n1486), .Y(n489) );
AOI22X1TS U1919 ( .A0(n1483), .A1(n1460), .B0(n1486), .B1(n937), .Y(n488) );
AOI22X1TS U1920 ( .A0(n1483), .A1(n1462), .B0(n1461), .B1(n938), .Y(n487) );
AOI22X1TS U1921 ( .A0(n1483), .A1(n1463), .B0(n1486), .B1(n935), .Y(n486) );
AO22XLTS U1922 ( .A0(n1339), .A1(DmP_mant_SFG_SWR[10]), .B0(n1479), .B1(
n1464), .Y(n485) );
AO22XLTS U1923 ( .A0(n1339), .A1(DmP_mant_SFG_SWR[11]), .B0(n1479), .B1(
n1465), .Y(n484) );
AO22XLTS U1924 ( .A0(n1339), .A1(DmP_mant_SFG_SWR[12]), .B0(n1469), .B1(
n1466), .Y(n483) );
AO22XLTS U1925 ( .A0(n1339), .A1(DmP_mant_SFG_SWR[13]), .B0(n1479), .B1(
n1467), .Y(n482) );
AO22XLTS U1926 ( .A0(n1339), .A1(DmP_mant_SFG_SWR[14]), .B0(n1469), .B1(
n1468), .Y(n481) );
AO22XLTS U1927 ( .A0(n1339), .A1(DmP_mant_SFG_SWR[15]), .B0(n1479), .B1(
n1470), .Y(n480) );
AOI22X1TS U1928 ( .A0(n1483), .A1(n1471), .B0(n921), .B1(n1486), .Y(n479) );
AOI22X1TS U1929 ( .A0(n1483), .A1(n1472), .B0(n1486), .B1(n922), .Y(n478) );
AOI22X1TS U1930 ( .A0(n1483), .A1(n1473), .B0(n1486), .B1(n923), .Y(n477) );
AOI22X1TS U1931 ( .A0(n1483), .A1(n1474), .B0(n1486), .B1(n924), .Y(n476) );
AOI22X1TS U1932 ( .A0(n1483), .A1(n1475), .B0(n1481), .B1(n925), .Y(n475) );
AOI22X1TS U1933 ( .A0(n1483), .A1(n1476), .B0(n1481), .B1(n926), .Y(n474) );
AOI22X1TS U1934 ( .A0(n1483), .A1(n1477), .B0(n1481), .B1(n927), .Y(n473) );
AO22XLTS U1935 ( .A0(n1339), .A1(DmP_mant_SFG_SWR[23]), .B0(n1479), .B1(
n1478), .Y(n472) );
AOI22X1TS U1936 ( .A0(n1483), .A1(n1482), .B0(n928), .B1(n1481), .Y(n471) );
AOI22X1TS U1937 ( .A0(Data_array_SWR[25]), .A1(n1396), .B0(n1485), .B1(n1484), .Y(n1487) );
AOI22X1TS U1938 ( .A0(n1483), .A1(n1487), .B0(n1486), .B1(n929), .Y(n470) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk30.tcl_ETAIIN16Q8_syn.sdf");
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file spartan3e_pmem.v when simulating
// the core, spartan3e_pmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module spartan3e_pmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3e"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of spartan3e_pmem is "black_box"
endmodule
|
`timescale 1 ns / 1 ps
module axis_bram_reader #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10,
parameter CONTINUOUS = "FALSE"
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [BRAM_ADDR_WIDTH-1:0] cfg_data,
output wire [BRAM_ADDR_WIDTH-1:0] sts_data,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast,
input wire m_axis_config_tready,
output wire m_axis_config_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg int_enbl_reg, int_enbl_next;
reg int_conf_reg, int_conf_next;
wire [BRAM_ADDR_WIDTH-1:0] sum_cntr_wire;
wire int_comp_wire, int_tlast_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_addr_reg <= {(BRAM_ADDR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
int_conf_reg <= 1'b0;
end
else
begin
int_addr_reg <= int_addr_next;
int_enbl_reg <= int_enbl_next;
int_conf_reg <= int_conf_next;
end
end
assign sum_cntr_wire = int_addr_reg + 1'b1;
assign int_comp_wire = int_addr_reg < cfg_data;
assign int_tlast_wire = ~int_comp_wire;
generate
if(CONTINUOUS == "TRUE")
begin : CONTINUOUS
always @*
begin
int_addr_next = int_addr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_enbl_reg & int_comp_wire)
begin
int_addr_next = sum_cntr_wire;
end
if(m_axis_tready & int_enbl_reg & int_tlast_wire)
begin
int_addr_next = {(BRAM_ADDR_WIDTH){1'b0}};
end
end
end
else
begin : STOP
always @*
begin
int_addr_next = int_addr_reg;
int_enbl_next = int_enbl_reg;
int_conf_next = int_conf_reg;
if(~int_enbl_reg & int_comp_wire)
begin
int_enbl_next = 1'b1;
end
if(m_axis_tready & int_enbl_reg & int_comp_wire)
begin
int_addr_next = sum_cntr_wire;
end
if(m_axis_tready & int_enbl_reg & int_tlast_wire)
begin
int_enbl_next = 1'b0;
int_conf_next = 1'b1;
end
if(int_conf_reg & m_axis_config_tready)
begin
int_conf_next = 1'b0;
end
end
end
endgenerate
assign sts_data = int_addr_reg;
assign m_axis_tdata = bram_porta_rddata;
assign m_axis_tvalid = int_enbl_reg;
assign m_axis_tlast = int_enbl_reg & int_tlast_wire;
assign m_axis_config_tvalid = int_conf_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = m_axis_tready & int_enbl_reg ? sum_cntr_wire : int_addr_reg;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O2111A_PP_SYMBOL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2111a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_PP_SYMBOL_V
|
`default_nettype none
`include "common.h"
module mmu_if(
input wire iCLOCK,
input wire inRESET,
input wire iFREE_TLB_FLUSH,
/*************************
To Core
*************************/
//Core -> This
input wire iCORE_REQ,
output wire oCORE_LOCK,
input wire iCORE_DATA_STORE_ACK,
input wire [1:0] iCORE_MMUMOD, //0=NoConvertion 1=none 2=1LevelConvertion 3=2LevelConvertion
input wire [2:0] iCORE_MMUPS,
input wire [31:0] iCORE_PDT, //Page Table Register
input wire [13:0] iCORE_ASID,
input wire [1:0] iCORE_ORDER,
input wire [3:0] iCORE_MASK,
input wire iCORE_RW,
input wire [31:0] iCORE_ADDR,
input wire [31:0] iCORE_DATA,
//This -> Core
output wire oCORE_REQ,
input wire iCORE_LOCK,
output wire oCORE_STORE_ACK,
output wire [63:0] oCORE_DATA,
output wire [23:0] oCORE_MMU_FLAGS,
/************************
To Memory
************************/
//This -> Memory
output wire oMEMORY_REQ,
input wire iMEMORY_LOCK,
output wire [1:0] oMEMORY_ORDER,
output wire [3:0] oMEMORY_MASK,
output wire oMEMORY_RW,
output wire [31:0] oMEMORY_ADDR,
output wire [31:0] oMEMORY_DATA,
//Memory -> This
input wire iMEMORY_REQ,
output wire oMEMORY_LOCK,
input wire [63:0] iMEMORY_DATA
);
localparam L_PARAM_STT_PFAULT_IDLE = 2'h0;
localparam L_PARAM_STT_PFAULT_QUEUEWAIT = 2'h1;
localparam L_PARAM_STT_PFAULT_TOCORE = 2'h2;
/********************************************************************************
Wire and Register
********************************************************************************/
//MMU <-> Memory
wire mmu2memory_req;
wire mmu2memory_lock;
wire mmu2memory_data_store_ack;
wire mmu2memory_rw;
//MMU <-> Matching
wire matching2mmu_full;
wire mmu2matching_type;
wire matching2coreout_type;
wire matching2mmu_empty;
//MMU Flags
wire mmu2mmufifo_req;
wire mmufifo2mmu_lock;
wire [23:0] mmu2mmufifo_flags;
wire [23:0] mmufifo2coreout_flags;
//Core Output Latch
reg b_coreout_req;
reg [63:0] b_coreout_data;
reg [23:0] b_coreout_mmu_flags;
//Condition
wire mmu2core_data_write_ack_condition = mmu2memory_req && mmu2memory_data_store_ack && !iMEMORY_LOCK;
wire mmu2memory_req_condition = mmu2memory_req && !iMEMORY_LOCK && !matching2mmu_full && !mmufifo2mmu_lock;
wire memory2mmu_lock_condition = iMEMORY_LOCK || matching2mmu_full || mmufifo2mmu_lock;
/********************************************************************************
Memory Management Unit
Dorect, 1level, 2level Address Convertion
********************************************************************************/
//MMU
mmu MMU(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
//TLB Flash
.iTLB_FLUSH(iFREE_TLB_FLUSH),
/***********************
Logic Addres Request
***********************/
.iLOGIC_REQ(iCORE_REQ),
.oLOGIC_LOCK(oCORE_LOCK),
.iLOGIC_DATA_STORE_ACK(iCORE_DATA_STORE_ACK),
.iLOGIC_MMUMOD(iCORE_MMUMOD), //0=NoConvertion 1=none 2=1LevelConvertion 3=2LevelConvertion
.iLOGIC_MMUPS(iCORE_MMUPS),
.iLOGIC_PDT(iCORE_PDT), //Page Directory Table
.iLOGIC_ASID(iCORE_ASID), //Task ID
.iLOGIC_ORDER(iCORE_ORDER),
.iLOGIC_MASK(iCORE_MASK),
.iLOGIC_RW(iCORE_RW), //0=Read 1=Write
.iLOGIC_ADDR(iCORE_ADDR),
.iLOGIC_DATA(iCORE_DATA),
/***********************
MMU Flags Output
***********************/
.oMMUFLAGS_REQ(mmu2mmufifo_req),
.iMMUFLAGS_LOCK(mmufifo2mmu_lock),
.oMMUFLAGS_FLAGS(mmu2mmufifo_flags),
/***********************
To Memory
***********************/
//MMU -> Memory
.oMEMORY_REQ(mmu2memory_req),
.iMEMORY_LOCK(memory2mmu_lock_condition),
.oMEMORY_DATA_STORE_ACK(mmu2memory_data_store_ack),
.oMEMORY_MMU_USE(mmu2matching_type),
.oMEMORY_ORDER(oMEMORY_ORDER),
.oMEMORY_MASK(oMEMORY_MASK),
.oMEMORY_RW(mmu2memory_rw),
.oMEMORY_ADDR(oMEMORY_ADDR),
.oMEMORY_DATA(oMEMORY_DATA),
//Memory -> MMU
.iMEMORY_VALID(iMEMORY_REQ && matching2coreout_type && !iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition),
.oMEMORY_LOCK(mmu2memory_lock),
.iMEMORY_DATA(iMEMORY_DATA)
);
/********************************************************************************
Memory Matching Queue
Memory access type queue.
Type 0 : Core Use
1 : MMU Use
********************************************************************************/
mist1032isa_arbiter_matching_queue #(16, 4, 1) MEM_MATCHING_QUEUE( //Queue deep : 16, Queue deep_n : 4, Flag_n : 2
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Flash
.iFLASH(1'b0),
//Write
.iWR_REQ(mmu2memory_req_condition && !mmu2memory_data_store_ack),
.iWR_FLAG(mmu2matching_type),
.oWR_FULL(matching2mmu_full),
//Read
.iRD_REQ(iMEMORY_REQ && !iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition),
.oRD_VALID(),
.oRD_FLAG(matching2coreout_type),
.oRD_EMPTY(matching2mmu_empty)
);
/********************************************************************************
MMU Flags Queue
********************************************************************************/
`ifdef MIST1032ISA_ALTERA_PRIMITIVE
//FIFO Mode : Show Ahead Synchronous FIFO Mode
//Width : 24bit
//Depth : 16Word
//Asynchronous Reset : Use
//Synchronous Reset : Use
//Usedw : Use
//Full : Use
//Empty : Use
//Almost Full : Use(Value=14)
//Almost Empty : Use(Value=2)
//Overflow Checking : Disable
//Undesflow Checking : Disable
altera_primitive_sync_fifo_24in_24out_16depth MMUFLAGS_QUEUE(
.aclr(!inRESET), //Asynchronous Reset
.clock(iCLOCK), //Clock
.data(mmu2mmufifo_flags), //Data-In
.rdreq(iMEMORY_REQ && matching2coreout_type && !iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition), //Read Data Request
.sclr(1'b0), //Synchthronous Reset
.wrreq(mmu2mmufifo_req && !memory2mmu_lock_condition), //Write Req
.almost_empty(),
.almost_full(),
.empty(),
.full(mmufifo2mmu_lock),
.q(mmufifo2coreout_flags), //Dataout
.usedw()
);
`elsif MIST1032ISA_XILINX_PRIMITIVE
`else
mist1032isa_sync_fifo #(24, 16, 4) MMUFLAGS_QUEUE(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iREMOVE(1'b0),
.oCOUNT(),
.iWR_EN(mmu2mmufifo_req && !memory2mmu_lock_condition),
.iWR_DATA(mmu2mmufifo_flags),
.oWR_FULL(mmufifo2mmu_lock),
.iRD_EN(iMEMORY_REQ && matching2coreout_type && !iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition),
.oRD_DATA(mmufifo2coreout_flags),
.oRD_EMPTY()
);
`endif
/********************************************************************************
Core Output Latch
********************************************************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_coreout_req <= 1'b0;
b_coreout_data <= {64{1'b0}};
b_coreout_mmu_flags <= {24{1'b0}};
end
else begin
if(!iCORE_LOCK && !mmu2memory_lock && !mmu2core_data_write_ack_condition)begin
b_coreout_req <= iMEMORY_REQ && !matching2coreout_type;
b_coreout_data <= iMEMORY_DATA;
b_coreout_mmu_flags <= mmufifo2coreout_flags;
end
end
end
/********************************************************************************
Assign
********************************************************************************/
assign oCORE_REQ = b_coreout_req || mmu2core_data_write_ack_condition;
assign oCORE_STORE_ACK = mmu2core_data_write_ack_condition;
assign oCORE_DATA = b_coreout_data;
assign oCORE_MMU_FLAGS = b_coreout_mmu_flags;
assign oMEMORY_REQ = mmu2memory_req_condition;
assign oMEMORY_RW = mmu2memory_rw;
assign oMEMORY_LOCK = iCORE_LOCK || mmu2memory_lock || mmu2core_data_write_ack_condition;
endmodule
`default_nettype wire
|
`include "DC_define.v"
`include "logfunc.h"
`include "scmemc.vh"
module DC_1_databank #(parameter Width = 36, Size =512, Forward=0)
( //I adress 22 bits
//36=>4 bit valid bits+ 4 byte/32 bit data=36 bit in total per entry 1 databank
input clk
,input reset
,input bank_sel
,input req_valid
,output req_retry
,input write
,input[2:0] way_no
,input row_even_odd
,input [4:0] req_Index//I adress 23 bits
//
,input [35:0] req_data//req data 32bit data+4 bit valid bit/write musk
,input [4:0] Load_req
,input Load_req_valid
,output Load_req_retry
,input [6:0] STD_req
,input STD_req_valid
,output STD_req_retry
,input write_musk_reset
,output ack_valid
,input ack_retry
,output [35:0] ack_data
);
//if( bank_sel==1) begin
logic [8:0] req_pos_bank;
logic [4:0] set_index;//5bits VA[10:6]
logic write_bank;
logic [8:0] index_ext,index_;
assign write_bank=write;
logic[35:0] req_data_for_bank,ack_data_ram;
logic [8:0] way_ext, odd_even_ext;//9 bits forr 512 entries as req_pos_bank
parameter sixteen=5'b10000;
assign way_ext ={{6{1'b0}}, way_no};//make 9 bit
assign req_data_for_bank=req_data;
always@(bank_sel or req_Index or row_even_odd or way_no)//***********************************
begin
if(bank_sel) begin
set_index=req_Index;
index_ = {{4{1'b0}}, set_index};//make 5 bit index as 9 bits
index_ext=index_*sixteen ;//index*16=512 which is 9 bits
odd_even_ext={{8{1'b00000000}},row_even_odd};//9 bits
//odd_even_=row_even_odd;
req_pos_bank = (index_ext*16)+(way_ext*2)+odd_even_ext;//way_no starts at 0
end
end
ram_1port_fast
#(.Width(Width), .Size(Size))
bank (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_we (write_bank)
,.req_data (req_data_for_bank)
,.ack_retry (ack_retry)//input
,.req_pos (req_pos_bank)
,.req_retry (req_retry)//output
,. ack_valid ( ack_valid)
,.ack_data (ack_data_ram)
);
always@( req_data_for_bank or bank_sel ) begin//********************************************************888
if((STD_req==`CORE_MOP_XS32)&& STD_req_valid)//|`CORE_MOP_XS00|`CORE_MOP_XS08|`CORE_MOP_XS16|`CORE_MOP_XS32|`CORE_MOP_XS64|`CORE_MOP_XS128|`CORE_MOP_XS256|`CORE_MOP_XS512) begin //
begin
write_bank=1'b1;
end
STD_req_retry=0;//32 bit data+4 bit valid bit per entry 1 data bank
end
always@( req_data_for_bank or bank_sel ) begin//********************************************************888
if(Load_req==`CORE_LOP_L32U) // READ if valid bits==4'b111
begin
if ((ack_data_ram[35:32]==4'b1111)&& Load_req_valid)begin
ack_valid=1;
ack_data=ack_data_ram;
end
end
Load_req_retry=0;
end
always_comb
begin//********************************************************888
if(write_musk_reset)begin //Invalidates make valid bits=0000begin
write_bank=1'b1;
req_data_for_bank[35:32]=4'b0000;
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module num (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [12 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("num.mif"),
.C_INIT_FILE("num.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(5778),
.C_READ_DEPTH_A(5778),
.C_ADDRA_WIDTH(13),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(5778),
.C_READ_DEPTH_B(5778),
.C_ADDRB_WIDTH(13),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("2"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 4.652585 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(13'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(* Finite sets library.
* Authors: Pierre Letouzey and Jean-Christophe Filliâtre
* Institution: LRI, CNRS UMR 8623 - Université Paris Sud
* 91405 Orsay, France *)
(* $Id: Int.v 10739 2008-04-01 14:45:20Z herbelin $ *)
(** An axiomatization of integers. *)
(** We define a signature for an integer datatype based on [Z].
The goal is to allow a switch after extraction to ocaml's
[big_int] or even [int] when finiteness isn't a problem
(typically : when mesuring the height of an AVL tree).
*)
Require Import ZArith.
Require Import ROmega.
Delimit Scope Int_scope with I.
(** * a specification of integers *)
Module Type Int.
Open Scope Int_scope.
Parameter int : Set.
Parameter i2z : int -> Z.
Arguments Scope i2z [ Int_scope ].
Parameter _0 : int.
Parameter _1 : int.
Parameter _2 : int.
Parameter _3 : int.
Parameter plus : int -> int -> int.
Parameter opp : int -> int.
Parameter minus : int -> int -> int.
Parameter mult : int -> int -> int.
Parameter max : int -> int -> int.
Notation "0" := _0 : Int_scope.
Notation "1" := _1 : Int_scope.
Notation "2" := _2 : Int_scope.
Notation "3" := _3 : Int_scope.
Infix "+" := plus : Int_scope.
Infix "-" := minus : Int_scope.
Infix "*" := mult : Int_scope.
Notation "- x" := (opp x) : Int_scope.
(** For logical relations, we can rely on their counterparts in Z,
since they don't appear after extraction. Moreover, using tactics
like omega is easier this way. *)
Notation "x == y" := (i2z x = i2z y)
(at level 70, y at next level, no associativity) : Int_scope.
Notation "x <= y" := (Zle (i2z x) (i2z y)): Int_scope.
Notation "x < y" := (Zlt (i2z x) (i2z y)) : Int_scope.
Notation "x >= y" := (Zge (i2z x) (i2z y)) : Int_scope.
Notation "x > y" := (Zgt (i2z x) (i2z y)): Int_scope.
Notation "x <= y <= z" := (x <= y /\ y <= z) : Int_scope.
Notation "x <= y < z" := (x <= y /\ y < z) : Int_scope.
Notation "x < y < z" := (x < y /\ y < z) : Int_scope.
Notation "x < y <= z" := (x < y /\ y <= z) : Int_scope.
(** Some decidability fonctions (informative). *)
Axiom gt_le_dec : forall x y: int, {x > y} + {x <= y}.
Axiom ge_lt_dec : forall x y : int, {x >= y} + {x < y}.
Axiom eq_dec : forall x y : int, { x == y } + {~ x==y }.
(** Specifications *)
(** First, we ask [i2z] to be injective. Said otherwise, our ad-hoc equality
[==] and the generic [=] are in fact equivalent. We define [==]
nonetheless since the translation to [Z] for using automatic tactic is easier. *)
Axiom i2z_eq : forall n p : int, n == p -> n = p.
(** Then, we express the specifications of the above parameters using their
Z counterparts. *)
Open Scope Z_scope.
Axiom i2z_0 : i2z _0 = 0.
Axiom i2z_1 : i2z _1 = 1.
Axiom i2z_2 : i2z _2 = 2.
Axiom i2z_3 : i2z _3 = 3.
Axiom i2z_plus : forall n p, i2z (n + p) = i2z n + i2z p.
Axiom i2z_opp : forall n, i2z (-n) = -i2z n.
Axiom i2z_minus : forall n p, i2z (n - p) = i2z n - i2z p.
Axiom i2z_mult : forall n p, i2z (n * p) = i2z n * i2z p.
Axiom i2z_max : forall n p, i2z (max n p) = Zmax (i2z n) (i2z p).
End Int.
(** * Facts and tactics using [Int] *)
Module MoreInt (I:Int).
Import I.
Open Scope Int_scope.
(** A magic (but costly) tactic that goes from [int] back to the [Z]
friendly world ... *)
Hint Rewrite ->
i2z_0 i2z_1 i2z_2 i2z_3 i2z_plus i2z_opp i2z_minus i2z_mult i2z_max : i2z.
Ltac i2z := match goal with
| H : (eq (A:=int) ?a ?b) |- _ =>
generalize (f_equal i2z H);
try autorewrite with i2z; clear H; intro H; i2z
| |- (eq (A:=int) ?a ?b) => apply (i2z_eq a b); try autorewrite with i2z; i2z
| H : _ |- _ => progress autorewrite with i2z in H; i2z
| _ => try autorewrite with i2z
end.
(** A reflexive version of the [i2z] tactic *)
(** this [i2z_refl] is actually weaker than [i2z]. For instance, if a
[i2z] is buried deep inside a subterm, [i2z_refl] may miss it.
See also the limitation about [Set] or [Type] part below.
Anyhow, [i2z_refl] is enough for applying [romega]. *)
Ltac i2z_gen := match goal with
| |- (eq (A:=int) ?a ?b) => apply (i2z_eq a b); i2z_gen
| H : (eq (A:=int) ?a ?b) |- _ =>
generalize (f_equal i2z H); clear H; i2z_gen
| H : (eq (A:=Z) ?a ?b) |- _ => generalize H; clear H; i2z_gen
| H : (Zlt ?a ?b) |- _ => generalize H; clear H; i2z_gen
| H : (Zle ?a ?b) |- _ => generalize H; clear H; i2z_gen
| H : (Zgt ?a ?b) |- _ => generalize H; clear H; i2z_gen
| H : (Zge ?a ?b) |- _ => generalize H; clear H; i2z_gen
| H : _ -> ?X |- _ =>
(* A [Set] or [Type] part cannot be dealt with easily
using the [ExprP] datatype. So we forget it, leaving
a goal that can be weaker than the original. *)
match type of X with
| Type => clear H; i2z_gen
| Prop => generalize H; clear H; i2z_gen
end
| H : _ <-> _ |- _ => generalize H; clear H; i2z_gen
| H : _ /\ _ |- _ => generalize H; clear H; i2z_gen
| H : _ \/ _ |- _ => generalize H; clear H; i2z_gen
| H : ~ _ |- _ => generalize H; clear H; i2z_gen
| _ => idtac
end.
Inductive ExprI : Set :=
| EI0 : ExprI
| EI1 : ExprI
| EI2 : ExprI
| EI3 : ExprI
| EIplus : ExprI -> ExprI -> ExprI
| EIopp : ExprI -> ExprI
| EIminus : ExprI -> ExprI -> ExprI
| EImult : ExprI -> ExprI -> ExprI
| EImax : ExprI -> ExprI -> ExprI
| EIraw : int -> ExprI.
Inductive ExprZ : Set :=
| EZplus : ExprZ -> ExprZ -> ExprZ
| EZopp : ExprZ -> ExprZ
| EZminus : ExprZ -> ExprZ -> ExprZ
| EZmult : ExprZ -> ExprZ -> ExprZ
| EZmax : ExprZ -> ExprZ -> ExprZ
| EZofI : ExprI -> ExprZ
| EZraw : Z -> ExprZ.
Inductive ExprP : Type :=
| EPeq : ExprZ -> ExprZ -> ExprP
| EPlt : ExprZ -> ExprZ -> ExprP
| EPle : ExprZ -> ExprZ -> ExprP
| EPgt : ExprZ -> ExprZ -> ExprP
| EPge : ExprZ -> ExprZ -> ExprP
| EPimpl : ExprP -> ExprP -> ExprP
| EPequiv : ExprP -> ExprP -> ExprP
| EPand : ExprP -> ExprP -> ExprP
| EPor : ExprP -> ExprP -> ExprP
| EPneg : ExprP -> ExprP
| EPraw : Prop -> ExprP.
(** [int] to [ExprI] *)
Ltac i2ei trm :=
match constr:trm with
| 0 => constr:EI0
| 1 => constr:EI1
| 2 => constr:EI2
| 3 => constr:EI3
| ?x + ?y => let ex := i2ei x with ey := i2ei y in constr:(EIplus ex ey)
| ?x - ?y => let ex := i2ei x with ey := i2ei y in constr:(EIminus ex ey)
| ?x * ?y => let ex := i2ei x with ey := i2ei y in constr:(EImult ex ey)
| max ?x ?y => let ex := i2ei x with ey := i2ei y in constr:(EImax ex ey)
| - ?x => let ex := i2ei x in constr:(EIopp ex)
| ?x => constr:(EIraw x)
end
(** [Z] to [ExprZ] *)
with z2ez trm :=
match constr:trm with
| (?x+?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZplus ex ey)
| (?x-?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZminus ex ey)
| (?x*?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZmult ex ey)
| (Zmax ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EZmax ex ey)
| (-?x)%Z => let ex := z2ez x in constr:(EZopp ex)
| i2z ?x => let ex := i2ei x in constr:(EZofI ex)
| ?x => constr:(EZraw x)
end.
(** [Prop] to [ExprP] *)
Ltac p2ep trm :=
match constr:trm with
| (?x <-> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPequiv ex ey)
| (?x -> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPimpl ex ey)
| (?x /\ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPand ex ey)
| (?x \/ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPor ex ey)
| (~ ?x) => let ex := p2ep x in constr:(EPneg ex)
| (eq (A:=Z) ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EPeq ex ey)
| (?x<?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPlt ex ey)
| (?x<=?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPle ex ey)
| (?x>?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPgt ex ey)
| (?x>=?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPge ex ey)
| ?x => constr:(EPraw x)
end.
(** [ExprI] to [int] *)
Fixpoint ei2i (e:ExprI) : int :=
match e with
| EI0 => 0
| EI1 => 1
| EI2 => 2
| EI3 => 3
| EIplus e1 e2 => (ei2i e1)+(ei2i e2)
| EIminus e1 e2 => (ei2i e1)-(ei2i e2)
| EImult e1 e2 => (ei2i e1)*(ei2i e2)
| EImax e1 e2 => max (ei2i e1) (ei2i e2)
| EIopp e => -(ei2i e)
| EIraw i => i
end.
(** [ExprZ] to [Z] *)
Fixpoint ez2z (e:ExprZ) : Z :=
match e with
| EZplus e1 e2 => ((ez2z e1)+(ez2z e2))%Z
| EZminus e1 e2 => ((ez2z e1)-(ez2z e2))%Z
| EZmult e1 e2 => ((ez2z e1)*(ez2z e2))%Z
| EZmax e1 e2 => Zmax (ez2z e1) (ez2z e2)
| EZopp e => (-(ez2z e))%Z
| EZofI e => i2z (ei2i e)
| EZraw z => z
end.
(** [ExprP] to [Prop] *)
Fixpoint ep2p (e:ExprP) : Prop :=
match e with
| EPeq e1 e2 => (ez2z e1) = (ez2z e2)
| EPlt e1 e2 => ((ez2z e1)<(ez2z e2))%Z
| EPle e1 e2 => ((ez2z e1)<=(ez2z e2))%Z
| EPgt e1 e2 => ((ez2z e1)>(ez2z e2))%Z
| EPge e1 e2 => ((ez2z e1)>=(ez2z e2))%Z
| EPimpl e1 e2 => (ep2p e1) -> (ep2p e2)
| EPequiv e1 e2 => (ep2p e1) <-> (ep2p e2)
| EPand e1 e2 => (ep2p e1) /\ (ep2p e2)
| EPor e1 e2 => (ep2p e1) \/ (ep2p e2)
| EPneg e => ~ (ep2p e)
| EPraw p => p
end.
(** [ExprI] (supposed under a [i2z]) to a simplified [ExprZ] *)
Fixpoint norm_ei (e:ExprI) : ExprZ :=
match e with
| EI0 => EZraw (0%Z)
| EI1 => EZraw (1%Z)
| EI2 => EZraw (2%Z)
| EI3 => EZraw (3%Z)
| EIplus e1 e2 => EZplus (norm_ei e1) (norm_ei e2)
| EIminus e1 e2 => EZminus (norm_ei e1) (norm_ei e2)
| EImult e1 e2 => EZmult (norm_ei e1) (norm_ei e2)
| EImax e1 e2 => EZmax (norm_ei e1) (norm_ei e2)
| EIopp e => EZopp (norm_ei e)
| EIraw i => EZofI (EIraw i)
end.
(** [ExprZ] to a simplified [ExprZ] *)
Fixpoint norm_ez (e:ExprZ) : ExprZ :=
match e with
| EZplus e1 e2 => EZplus (norm_ez e1) (norm_ez e2)
| EZminus e1 e2 => EZminus (norm_ez e1) (norm_ez e2)
| EZmult e1 e2 => EZmult (norm_ez e1) (norm_ez e2)
| EZmax e1 e2 => EZmax (norm_ez e1) (norm_ez e2)
| EZopp e => EZopp (norm_ez e)
| EZofI e => norm_ei e
| EZraw z => EZraw z
end.
(** [ExprP] to a simplified [ExprP] *)
Fixpoint norm_ep (e:ExprP) : ExprP :=
match e with
| EPeq e1 e2 => EPeq (norm_ez e1) (norm_ez e2)
| EPlt e1 e2 => EPlt (norm_ez e1) (norm_ez e2)
| EPle e1 e2 => EPle (norm_ez e1) (norm_ez e2)
| EPgt e1 e2 => EPgt (norm_ez e1) (norm_ez e2)
| EPge e1 e2 => EPge (norm_ez e1) (norm_ez e2)
| EPimpl e1 e2 => EPimpl (norm_ep e1) (norm_ep e2)
| EPequiv e1 e2 => EPequiv (norm_ep e1) (norm_ep e2)
| EPand e1 e2 => EPand (norm_ep e1) (norm_ep e2)
| EPor e1 e2 => EPor (norm_ep e1) (norm_ep e2)
| EPneg e => EPneg (norm_ep e)
| EPraw p => EPraw p
end.
Lemma norm_ei_correct : forall e:ExprI, ez2z (norm_ei e) = i2z (ei2i e).
Proof.
induction e; simpl; intros; i2z; auto; try congruence.
Qed.
Lemma norm_ez_correct : forall e:ExprZ, ez2z (norm_ez e) = ez2z e.
Proof.
induction e; simpl; intros; i2z; auto; try congruence; apply norm_ei_correct.
Qed.
Lemma norm_ep_correct :
forall e:ExprP, ep2p (norm_ep e) <-> ep2p e.
Proof.
induction e; simpl; repeat (rewrite norm_ez_correct); intuition.
Qed.
Lemma norm_ep_correct2 :
forall e:ExprP, ep2p (norm_ep e) -> ep2p e.
Proof.
intros; destruct (norm_ep_correct e); auto.
Qed.
Ltac i2z_refl :=
i2z_gen;
match goal with |- ?t =>
let e := p2ep t in
change (ep2p e); apply norm_ep_correct2; simpl
end.
(* i2z_refl can be replaced below by (simpl in *; i2z).
The reflexive version improves compilation of AVL files by about 15% *)
Ltac omega_max := i2z_refl; romega with Z.
End MoreInt.
(** * An implementation of [Int] *)
(** It's always nice to know that our [Int] interface is realizable :-) *)
Module Z_as_Int <: Int.
Open Scope Z_scope.
Definition int := Z.
Definition _0 := 0.
Definition _1 := 1.
Definition _2 := 2.
Definition _3 := 3.
Definition plus := Zplus.
Definition opp := Zopp.
Definition minus := Zminus.
Definition mult := Zmult.
Definition max := Zmax.
Definition gt_le_dec := Z_gt_le_dec.
Definition ge_lt_dec := Z_ge_lt_dec.
Definition eq_dec := Z_eq_dec.
Definition i2z : int -> Z := fun n => n.
Lemma i2z_eq : forall n p, i2z n=i2z p -> n = p. Proof. auto. Qed.
Lemma i2z_0 : i2z _0 = 0. Proof. auto. Qed.
Lemma i2z_1 : i2z _1 = 1. Proof. auto. Qed.
Lemma i2z_2 : i2z _2 = 2. Proof. auto. Qed.
Lemma i2z_3 : i2z _3 = 3. Proof. auto. Qed.
Lemma i2z_plus : forall n p, i2z (n + p) = i2z n + i2z p. Proof. auto. Qed.
Lemma i2z_opp : forall n, i2z (- n) = - i2z n. Proof. auto. Qed.
Lemma i2z_minus : forall n p, i2z (n - p) = i2z n - i2z p. Proof. auto. Qed.
Lemma i2z_mult : forall n p, i2z (n * p) = i2z n * i2z p. Proof. auto. Qed.
Lemma i2z_max : forall n p, i2z (max n p) = Zmax (i2z n) (i2z p). Proof. auto. Qed.
End Z_as_Int.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_TB_V
`define SKY130_FD_SC_MS__SDFBBP_TB_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfbbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 RESET_B = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SET_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 RESET_B = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SET_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SET_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 RESET_B = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SET_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 RESET_B = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sdfbbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:43:32 09/23/2013
// Design Name:
// Module Name: Data_Parameters
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Data_Parameters(clock, reset, mem_address, write_value_reg_en, write_data_selector, write_value);
input clock, reset, write_value_reg_en;
input [3:0] mem_address;
input [1:0] write_data_selector;
output reg [3:0] write_value;
// Valores que pueden escribirse en memoria
parameter CINCOH = 4'b0101;
parameter AH = 4'b1010;
parameter FH = 4'b1111;
//Valor obtenido del mux. Es el valor que se va a escribir
wire [3:0] mux_output;
//
initial
begin
write_value <= 4'b0000;
end
//El mux que selecciona el valor que se va a escribir en memoria
Mux_4x1 mod_selector_dato(mem_address, CINCOH, AH, FH ,write_data_selector, mux_output);
//Se guarda la salida del mux siempre que se active la escritura
always @ (posedge clock or posedge reset)
begin
if(reset)
begin
write_value <= 4'b0000;
end
else if(write_value_reg_en)
begin
write_value <= mux_output;
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// File Name: FILEREAD_TESTER.v
// Project: $PROJECT_NAME
// Version: 1.2
// Date: 2005-06-29
//
// Company: Xilinx, Inc.
// Contributor: Wen Ying Wei, Davy Huang
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2005 Xilinx, Inc.
// All rights reserved.
//
//-----------------------------------------------------------------------------
// Aurora FILEREAD_TESTER
// Author: Nigel Gulstone, Davy Huang
//
// Description: Drives the LocalLink, NFC and UFC interfaces and the other
// User signals using vectors from a file...
//-----------------------------------------------------------------------------
`timescale 1 ns / 10 ps
module FILEREAD_TESTER
(
CLK,
TV,
//LocalLink Interface
TX_SOF_N,
TX_EOF_N,
TX_D,
TX_REM,
TX_SRC_RDY_N,
//NFC Interface//Native Flow Control Interface
NFC_NB,
NFC_REQ_N,
//UFC Interface//User Flow Control Interface
UFC_TX_REQ_N,
UFC_TX_MS,
//Control Vector Signals
CTRL
);
// Parameter Declarations ********************************************
parameter GLOBALDLY = 1;
parameter TV_WIDTH = 8; // test vector width: 4,8,12,16, etc.
parameter CV_WIDTH = 4; // control vector width: 4,8,12,16, etc.
parameter LL_DAT_BIT_WIDTH = 64; //8,16,32,64,128,256
parameter LL_REM_BIT_WIDTH = 3; //0,1 ,2, 3, 4, 5
parameter REM_VECTOR_WIDTH = 3; //3 (if LL_REM_BIT_WIDTH <=3) or 7 (if LL_REM_BIT_WIDTH >3)
// Port Declarations ************************************************
input CLK;
input [0:TV_WIDTH-1] TV;
//LocalLink Interface
output TX_SOF_N;
output TX_EOF_N;
output [0:LL_DAT_BIT_WIDTH-1] TX_D;
output [0:LL_REM_BIT_WIDTH-1] TX_REM;
output TX_SRC_RDY_N;
//NFC Interface
output [0:3] NFC_NB;
output NFC_REQ_N;
//UFC Interface
output UFC_TX_REQ_N;
output [0:3] UFC_TX_MS;
//Clock Correction Interface
output [0:CV_WIDTH-1] CTRL;
// Signal Declarations ***********************************************
reg [LL_DAT_BIT_WIDTH + 4 + 4 + 1+1+1+1+1+REM_VECTOR_WIDTH+CV_WIDTH+16+TV_WIDTH:1] stim [0:65535];
integer index;
reg [LL_DAT_BIT_WIDTH + 4 + 4 + 1+1+1+1+1+REM_VECTOR_WIDTH+CV_WIDTH:1] vector;
reg [LL_DAT_BIT_WIDTH + 4 + 4 + 1+1+1+1+1+REM_VECTOR_WIDTH+CV_WIDTH:1] vector_dummy;
wire dummy;
reg [0:15] repeat_count_i;
reg [0:15] repeat_count_dummy;
reg [TV_WIDTH-1:0] testvec;
reg [TV_WIDTH-1:0] testvec_dummy;
reg [0:3] i;
wire [0:REM_VECTOR_WIDTH-1] TX_REM_i;
reg [0:LL_REM_BIT_WIDTH-1] TX_REM;
parameter TX_D_BOUND = LL_DAT_BIT_WIDTH + 4 + 4 + 1+1+1+1+1+REM_VECTOR_WIDTH+CV_WIDTH;
// Main Body of Code *************************************************
initial
begin
index <= 0;
repeat_count_i <= 16'h0000;
$readmemh("user_data_packets.vec",stim);
testvec <= 0;
vector <= 0;
end
// 64, 4 , 4, 1, 1, 1, 1, 1, 3, cv_width
assign {TX_D,NFC_NB,UFC_TX_MS,NFC_REQ_N,UFC_TX_REQ_N,TX_SOF_N,TX_SRC_RDY_N,TX_EOF_N, TX_REM_i,CTRL} = vector;
always @(TX_REM_i)
begin
for (i=0;i<LL_REM_BIT_WIDTH;i=i+1)
TX_REM[i] = TX_REM_i[REM_VECTOR_WIDTH-LL_REM_BIT_WIDTH+i];
end
always @(posedge CLK)
if( repeat_count_i > 0 )
repeat_count_i <= #GLOBALDLY repeat_count_i - 1;
else if( testvec != 0)
begin
for (i=0;i<TV_WIDTH;i=i+1)
if (TV[i]) testvec[TV_WIDTH-1-i] = 1'b0;
if(testvec == 0 && index < 65535)
begin
{vector_dummy,repeat_count_dummy,testvec_dummy} = stim[index];
if (vector_dummy[TX_D_BOUND:TX_D_BOUND-15] == 16'hDEAD) begin
{vector,repeat_count_i,testvec} = #GLOBALDLY stim[0];
index = 1;
end
else begin
{vector,repeat_count_i,testvec} = #GLOBALDLY stim[index];
index = index + 1;
end
end
end
else if( index < 65535 )
begin
{vector_dummy,repeat_count_dummy,testvec_dummy} = stim[index];
if (vector_dummy[TX_D_BOUND:TX_D_BOUND-15] == 16'hDEAD) begin
{vector,repeat_count_i,testvec} = #GLOBALDLY stim[0];
index = 1;
end
else begin
{vector,repeat_count_i,testvec} = #GLOBALDLY stim[index];
index = index + 1;
end
end
endmodule
//-----------------------------------------------------------------------------
// History:
// NG 05/15/03 Begin Coding
// NG 05/16/03 Add test vector
// NG 05/21/03 Generic Test Vectors
// DH 06/12/03 Make it support generic data width
// DH 10/19/03 Generic Control Vectors
// DH 08/30/04 Added "end of vector file" flag to repeat the test
//-----------------------------------------------------------------------------
// $Revision: 1.2 $
// $Date: 2004/12/27 18:12:18 $
|
/*
* Synchronous read 1r1w content addressable memory module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
*
* This module is similar to bsg_cam_1r1w_sync, except it allows for an
* external replacement scheme
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_sync_unmanaged
#(parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(tag_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter safe_els_lp = `BSG_MAX(els_p,1)
)
(input clk_i
, input reset_i
// Synchronous write/invalidate of a tag
// one or zero-hot
, input [safe_els_lp-1:0] w_v_i
, input w_set_not_clear_i
// Tag/data to set on write
, input [tag_width_p-1:0] w_tag_i
, input [data_width_p-1:0] w_data_i
// Metadata useful for an external replacement policy
// Whether there's an empty entry in the tag array
, output [safe_els_lp-1:0] w_empty_o
// Asynchronous read of a tag, if exists
, input r_v_i
, input [tag_width_p-1:0] r_tag_i
, output logic [data_width_p-1:0] r_data_o
, output logic r_v_o
);
// Latch the read request for a synchronous read
logic [tag_width_p-1:0] r_tag_r;
logic r_v_r;
bsg_dff
#(.width_p(1+tag_width_p))
r_tag_reg
(.clk_i(clk_i)
,.data_i({r_v_i, r_tag_i})
,.data_o({r_v_r, r_tag_r})
);
// Read from asynchronous unmanaged CAM
bsg_cam_1r1w_unmanaged
#(.els_p(safe_els_lp)
,.tag_width_p(tag_width_p)
,.data_width_p(data_width_p)
)
cam
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(w_v_i)
,.w_set_not_clear_i(w_set_not_clear_i)
,.w_tag_i(w_tag_i)
,.w_data_i(w_data_i)
,.w_empty_o(w_empty_o)
,.r_v_i(r_v_r)
,.r_tag_i(r_tag_r)
,.r_data_o(r_data_o)
,.r_v_o(r_v_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_cam_1r1w_sync_unmanaged)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_PP_SYMBOL_V
`define SKY130_FD_SC_LS__EINVN_PP_SYMBOL_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__einvn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/23/2016 12:29:09 PM
// Design Name:
// Module Name: Week8Lab
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Week8Lab(
input Clk,
output reg [6:0] Cathodes,
output reg [3:0] Anode
);
reg[1:0 ] digit = 2'b00;
reg [27:0] Count;
reg Rate;
// Initialization
initial begin
Count = 0;
Rate = 0;
end
// Converts to 240 Hz
always @ (posedge Clk)
begin
if (Count == 216666)
begin
Rate = ~Rate;
Count = 0;
end
else
begin
Count = Count + 1;
end
end
// Turns on each led at 240hz per second
always @ (posedge Rate)
begin
case (digit)
// 4
2'b00: begin
Anode[0] = 0;
Anode[1] = 1;
Anode[2] = 1;
Anode[3] = 1;
Cathodes[0] = 1;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 1;
Cathodes[4] = 1;
Cathodes[5] = 0;
Cathodes[6] = 0;
end
// 3
2'b01: begin
Anode[0] = 1;
Anode[1] = 0;
Anode[2] = 1;
Anode[3] = 1;
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 0;
Cathodes[4] = 1;
Cathodes[5] = 1;
Cathodes[6] = 0;
end
// 2
2'b10: begin
Anode[0] = 1;
Anode[1] = 1;
Anode[2] = 0;
Anode[3] = 1;
Cathodes[0] = 0;
Cathodes[1] = 0;
Cathodes[2] = 1;
Cathodes[3] = 0;
Cathodes[4] = 0;
Cathodes[5] = 1;
Cathodes[6] = 0;
end
// 1
2'b11: begin
Anode[0] = 1;
Anode[1] = 1;
Anode[2] = 1;
Anode[3] = 0;
Cathodes[0] = 1;
Cathodes[1] = 0;
Cathodes[2] = 0;
Cathodes[3] = 1;
Cathodes[4] = 1;
Cathodes[5] = 1;
Cathodes[6] = 1;
end
endcase
digit = digit + 1;
end
endmodule
|
module opicorv32_instruction_decoder_wrap (
decoder_trigger_q,
decoder_pseudo_trigger,
decoder_trigger,
mem_rdata_q,
mem_rdata_latched,
mem_done,
mem_do_rinst,
resetn,
clk,
instr_lui,
instr_auipc,
instr_jal,
instr_jalr,
instr_beq,
instr_bne,
instr_blt,
instr_bge,
instr_bltu,
instr_bgeu,
instr_lb,
instr_lh,
instr_lw,
instr_lbu,
instr_lhu,
instr_sb,
instr_sh,
instr_sw,
instr_addi,
instr_slti,
instr_sltiu,
instr_xori,
instr_ori,
instr_andi,
instr_slli,
instr_srli,
instr_srai,
instr_add,
instr_sub,
instr_sll,
instr_slt,
instr_sltu,
instr_xor,
instr_srl,
instr_sra,
instr_or,
instr_and,
instr_rdcycle,
instr_rdcycleh,
instr_rdinstr,
instr_rdinstrh,
instr_getq,
instr_setq,
instr_retirq,
instr_maskirq,
instr_waitirq,
instr_timer,
instr_trap,
is_lui_auipc_jal,
is_lb_lh_lw_lbu_lhu,
is_slli_srli_srai,
is_jalr_addi_slti_sltiu_xori_ori_andi,
is_sb_sh_sw,
is_sll_srl_sra,
is_lui_auipc_jal_jalr_addi_add,
is_slti_blt_slt,
is_sltiu_bltu_sltu,
is_beq_bne_blt_bge_bltu_bgeu,
is_lbu_lhu_lw,
is_alu_reg_imm,
is_alu_reg_reg,
is_compare,
is_rdcycle_rdcycleh_rdinstr_rdinstrh,
pcpi_insn,
decoded_rd,
decoded_rs1,
decoded_rs2,
decoded_imm,
decoded_imm_uj
);
input decoder_trigger_q;
input decoder_pseudo_trigger;
input decoder_trigger;
input [31:0] mem_rdata_q;
input [31:0] mem_rdata_latched;
input mem_done;
input mem_do_rinst;
input resetn;
input clk;
output instr_lui;
output instr_auipc;
output instr_jal;
output instr_jalr;
output instr_beq;
output instr_bne;
output instr_blt;
output instr_bge;
output instr_bltu;
output instr_bgeu;
output instr_lb;
output instr_lh;
output instr_lw;
output instr_lbu;
output instr_lhu;
output instr_sb;
output instr_sh;
output instr_sw;
output instr_addi;
output instr_slti;
output instr_sltiu;
output instr_xori;
output instr_ori;
output instr_andi;
output instr_slli;
output instr_srli;
output instr_srai;
output instr_add;
output instr_sub;
output instr_sll;
output instr_slt;
output instr_sltu;
output instr_xor;
output instr_srl;
output instr_sra;
output instr_or;
output instr_and;
output instr_rdcycle;
output instr_rdcycleh;
output instr_rdinstr;
output instr_rdinstrh;
output instr_getq;
output instr_setq;
output instr_retirq;
output instr_maskirq;
output instr_waitirq;
output instr_timer;
output instr_trap;
output is_lui_auipc_jal;
output is_lb_lh_lw_lbu_lhu;
output is_slli_srli_srai;
output is_jalr_addi_slti_sltiu_xori_ori_andi;
output is_sb_sh_sw;
output is_sll_srl_sra;
output is_lui_auipc_jal_jalr_addi_add;
output is_slti_blt_slt;
output is_sltiu_bltu_sltu;
output is_beq_bne_blt_bge_bltu_bgeu;
output is_lbu_lhu_lw;
output is_alu_reg_imm;
output is_alu_reg_reg;
output is_compare;
output is_rdcycle_rdcycleh_rdinstr_rdinstrh;
output [31:0] pcpi_insn;
output [5:0] decoded_rd;
output [5:0] decoded_rs1;
output [5:0] decoded_rs2;
output [31:0] decoded_imm;
output [31:0] decoded_imm_uj;
/* signal declarations */
wire [31:0] _863;
wire [31:0] _792;
wire [31:0] compare_decoded_imm_uj;
wire [31:0] _865;
wire [31:0] _866;
wire [31:0] _793;
wire [31:0] compare_decoded_imm;
wire [31:0] _868;
wire [5:0] _869;
wire [5:0] _794;
wire [5:0] compare_decoded_rs2;
wire [5:0] _871;
wire [5:0] _872;
wire [5:0] _795;
wire [5:0] compare_decoded_rs1;
wire [5:0] _874;
wire [5:0] _875;
wire [5:0] _796;
wire [5:0] compare_decoded_rd;
wire [5:0] _877;
wire [31:0] _878;
wire [31:0] _797;
wire [31:0] compare_pcpi_insn;
wire [31:0] _880;
wire _881;
wire _862;
wire compare_is_rdcycle_rdcycleh_rdinstr_rdinstrh;
wire _883;
wire _884;
wire _861;
wire compare_is_compare;
wire _886;
wire _887;
wire _860;
wire compare_is_alu_reg_reg;
wire _889;
wire _890;
wire _859;
wire compare_is_alu_reg_imm;
wire _892;
wire _893;
wire _858;
wire compare_is_lbu_lhu_lw;
wire _895;
wire _896;
wire _857;
wire compare_is_beq_bne_blt_bge_bltu_bgeu;
wire _898;
wire _899;
wire _856;
wire compare_is_sltiu_bltu_sltu;
wire _901;
wire _902;
wire _855;
wire compare_is_slti_blt_slt;
wire _904;
wire _905;
wire _854;
wire compare_is_lui_auipc_jal_jalr_addi_add;
wire _907;
wire _908;
wire _853;
wire compare_is_sll_srl_sra;
wire _910;
wire _911;
wire _852;
wire compare_is_sb_sh_sw;
wire _913;
wire _914;
wire _851;
wire compare_is_jalr_addi_slti_sltiu_xori_ori_andi;
wire _916;
wire _917;
wire _850;
wire compare_is_slli_srli_srai;
wire _919;
wire _920;
wire _849;
wire compare_is_lb_lh_lw_lbu_lhu;
wire _922;
wire _923;
wire [14:0] _798;
wire _848;
wire compare_is_lui_auipc_jal;
wire _925;
wire _926;
wire _847;
wire compare_instr_trap;
wire _928;
wire _929;
wire _846;
wire compare_instr_timer;
wire _931;
wire _932;
wire _845;
wire compare_instr_waitirq;
wire _934;
wire _935;
wire _844;
wire compare_instr_maskirq;
wire _937;
wire _938;
wire _843;
wire compare_instr_retirq;
wire _940;
wire _941;
wire _842;
wire compare_instr_setq;
wire _943;
wire _944;
wire _841;
wire compare_instr_getq;
wire _946;
wire _947;
wire _840;
wire compare_instr_rdinstrh;
wire _949;
wire _950;
wire _839;
wire compare_instr_rdinstr;
wire _952;
wire _953;
wire _838;
wire compare_instr_rdcycleh;
wire _955;
wire _956;
wire _837;
wire compare_instr_rdcycle;
wire _958;
wire _959;
wire _836;
wire compare_instr_and;
wire _961;
wire _962;
wire _835;
wire compare_instr_or;
wire _964;
wire _965;
wire _834;
wire compare_instr_sra;
wire _967;
wire _968;
wire _833;
wire compare_instr_srl;
wire _970;
wire _971;
wire _832;
wire compare_instr_xor;
wire _973;
wire _974;
wire _831;
wire compare_instr_sltu;
wire _976;
wire _977;
wire _830;
wire compare_instr_slt;
wire _979;
wire _980;
wire _829;
wire compare_instr_sll;
wire _982;
wire _983;
wire _828;
wire compare_instr_sub;
wire _985;
wire _986;
wire _827;
wire compare_instr_add;
wire _988;
wire _989;
wire _826;
wire compare_instr_srai;
wire _991;
wire _992;
wire _825;
wire compare_instr_srli;
wire _994;
wire _995;
wire _824;
wire compare_instr_slli;
wire _997;
wire _998;
wire _823;
wire compare_instr_andi;
wire _1000;
wire _1001;
wire _822;
wire compare_instr_ori;
wire _1003;
wire _1004;
wire _821;
wire compare_instr_xori;
wire _1006;
wire _1007;
wire _820;
wire compare_instr_sltiu;
wire _1009;
wire _1010;
wire _819;
wire compare_instr_slti;
wire _1012;
wire _1013;
wire _818;
wire compare_instr_addi;
wire _1015;
wire _1016;
wire _817;
wire compare_instr_sw;
wire _1018;
wire _1019;
wire _816;
wire compare_instr_sh;
wire _1021;
wire _1022;
wire _815;
wire compare_instr_sb;
wire _1024;
wire _1025;
wire _814;
wire compare_instr_lhu;
wire _1027;
wire _1028;
wire _813;
wire compare_instr_lbu;
wire _1030;
wire _1031;
wire _812;
wire compare_instr_lw;
wire _1033;
wire _1034;
wire _811;
wire compare_instr_lh;
wire _1036;
wire _1037;
wire _810;
wire compare_instr_lb;
wire _1039;
wire _1040;
wire _809;
wire compare_instr_bgeu;
wire _1042;
wire _1043;
wire _808;
wire compare_instr_bltu;
wire _1045;
wire _1046;
wire _807;
wire compare_instr_bge;
wire _1048;
wire _1049;
wire _806;
wire compare_instr_blt;
wire _1051;
wire _1052;
wire _805;
wire compare_instr_bne;
wire _1054;
wire _1055;
wire _804;
wire compare_instr_beq;
wire _1057;
wire _1058;
wire _803;
wire compare_instr_jalr;
wire _1060;
wire _1061;
wire _802;
wire compare_instr_jal;
wire _1063;
wire _1064;
wire _801;
wire compare_instr_auipc;
wire _1066;
wire [176:0] _789;
wire _1067;
wire [176:0] _791;
wire [47:0] _799;
wire _800;
wire compare_instr_lui;
wire _1069;
/* logic */
assign _863 = _789[176:145];
assign _792 = _791[176:145];
assign compare_decoded_imm_uj = _792 ^ _863;
assign _865 = compare_decoded_imm_uj ^ _863;
assign _866 = _789[144:113];
assign _793 = _791[144:113];
assign compare_decoded_imm = _793 ^ _866;
assign _868 = compare_decoded_imm ^ _866;
assign _869 = _789[112:107];
assign _794 = _791[112:107];
assign compare_decoded_rs2 = _794 ^ _869;
assign _871 = compare_decoded_rs2 ^ _869;
assign _872 = _789[106:101];
assign _795 = _791[106:101];
assign compare_decoded_rs1 = _795 ^ _872;
assign _874 = compare_decoded_rs1 ^ _872;
assign _875 = _789[100:95];
assign _796 = _791[100:95];
assign compare_decoded_rd = _796 ^ _875;
assign _877 = compare_decoded_rd ^ _875;
assign _878 = _789[94:63];
assign _797 = _791[94:63];
assign compare_pcpi_insn = _797 ^ _878;
assign _880 = compare_pcpi_insn ^ _878;
assign _881 = _789[62:62];
assign _862 = _798[14:14];
assign compare_is_rdcycle_rdcycleh_rdinstr_rdinstrh = _862 ^ _881;
assign _883 = compare_is_rdcycle_rdcycleh_rdinstr_rdinstrh ^ _881;
assign _884 = _789[61:61];
assign _861 = _798[13:13];
assign compare_is_compare = _861 ^ _884;
assign _886 = compare_is_compare ^ _884;
assign _887 = _789[60:60];
assign _860 = _798[12:12];
assign compare_is_alu_reg_reg = _860 ^ _887;
assign _889 = compare_is_alu_reg_reg ^ _887;
assign _890 = _789[59:59];
assign _859 = _798[11:11];
assign compare_is_alu_reg_imm = _859 ^ _890;
assign _892 = compare_is_alu_reg_imm ^ _890;
assign _893 = _789[58:58];
assign _858 = _798[10:10];
assign compare_is_lbu_lhu_lw = _858 ^ _893;
assign _895 = compare_is_lbu_lhu_lw ^ _893;
assign _896 = _789[57:57];
assign _857 = _798[9:9];
assign compare_is_beq_bne_blt_bge_bltu_bgeu = _857 ^ _896;
assign _898 = compare_is_beq_bne_blt_bge_bltu_bgeu ^ _896;
assign _899 = _789[56:56];
assign _856 = _798[8:8];
assign compare_is_sltiu_bltu_sltu = _856 ^ _899;
assign _901 = compare_is_sltiu_bltu_sltu ^ _899;
assign _902 = _789[55:55];
assign _855 = _798[7:7];
assign compare_is_slti_blt_slt = _855 ^ _902;
assign _904 = compare_is_slti_blt_slt ^ _902;
assign _905 = _789[54:54];
assign _854 = _798[6:6];
assign compare_is_lui_auipc_jal_jalr_addi_add = _854 ^ _905;
assign _907 = compare_is_lui_auipc_jal_jalr_addi_add ^ _905;
assign _908 = _789[53:53];
assign _853 = _798[5:5];
assign compare_is_sll_srl_sra = _853 ^ _908;
assign _910 = compare_is_sll_srl_sra ^ _908;
assign _911 = _789[52:52];
assign _852 = _798[4:4];
assign compare_is_sb_sh_sw = _852 ^ _911;
assign _913 = compare_is_sb_sh_sw ^ _911;
assign _914 = _789[51:51];
assign _851 = _798[3:3];
assign compare_is_jalr_addi_slti_sltiu_xori_ori_andi = _851 ^ _914;
assign _916 = compare_is_jalr_addi_slti_sltiu_xori_ori_andi ^ _914;
assign _917 = _789[50:50];
assign _850 = _798[2:2];
assign compare_is_slli_srli_srai = _850 ^ _917;
assign _919 = compare_is_slli_srli_srai ^ _917;
assign _920 = _789[49:49];
assign _849 = _798[1:1];
assign compare_is_lb_lh_lw_lbu_lhu = _849 ^ _920;
assign _922 = compare_is_lb_lh_lw_lbu_lhu ^ _920;
assign _923 = _789[48:48];
assign _798 = _791[62:48];
assign _848 = _798[0:0];
assign compare_is_lui_auipc_jal = _848 ^ _923;
assign _925 = compare_is_lui_auipc_jal ^ _923;
assign _926 = _789[47:47];
assign _847 = _799[47:47];
assign compare_instr_trap = _847 ^ _926;
assign _928 = compare_instr_trap ^ _926;
assign _929 = _789[46:46];
assign _846 = _799[46:46];
assign compare_instr_timer = _846 ^ _929;
assign _931 = compare_instr_timer ^ _929;
assign _932 = _789[45:45];
assign _845 = _799[45:45];
assign compare_instr_waitirq = _845 ^ _932;
assign _934 = compare_instr_waitirq ^ _932;
assign _935 = _789[44:44];
assign _844 = _799[44:44];
assign compare_instr_maskirq = _844 ^ _935;
assign _937 = compare_instr_maskirq ^ _935;
assign _938 = _789[43:43];
assign _843 = _799[43:43];
assign compare_instr_retirq = _843 ^ _938;
assign _940 = compare_instr_retirq ^ _938;
assign _941 = _789[42:42];
assign _842 = _799[42:42];
assign compare_instr_setq = _842 ^ _941;
assign _943 = compare_instr_setq ^ _941;
assign _944 = _789[41:41];
assign _841 = _799[41:41];
assign compare_instr_getq = _841 ^ _944;
assign _946 = compare_instr_getq ^ _944;
assign _947 = _789[40:40];
assign _840 = _799[40:40];
assign compare_instr_rdinstrh = _840 ^ _947;
assign _949 = compare_instr_rdinstrh ^ _947;
assign _950 = _789[39:39];
assign _839 = _799[39:39];
assign compare_instr_rdinstr = _839 ^ _950;
assign _952 = compare_instr_rdinstr ^ _950;
assign _953 = _789[38:38];
assign _838 = _799[38:38];
assign compare_instr_rdcycleh = _838 ^ _953;
assign _955 = compare_instr_rdcycleh ^ _953;
assign _956 = _789[37:37];
assign _837 = _799[37:37];
assign compare_instr_rdcycle = _837 ^ _956;
assign _958 = compare_instr_rdcycle ^ _956;
assign _959 = _789[36:36];
assign _836 = _799[36:36];
assign compare_instr_and = _836 ^ _959;
assign _961 = compare_instr_and ^ _959;
assign _962 = _789[35:35];
assign _835 = _799[35:35];
assign compare_instr_or = _835 ^ _962;
assign _964 = compare_instr_or ^ _962;
assign _965 = _789[34:34];
assign _834 = _799[34:34];
assign compare_instr_sra = _834 ^ _965;
assign _967 = compare_instr_sra ^ _965;
assign _968 = _789[33:33];
assign _833 = _799[33:33];
assign compare_instr_srl = _833 ^ _968;
assign _970 = compare_instr_srl ^ _968;
assign _971 = _789[32:32];
assign _832 = _799[32:32];
assign compare_instr_xor = _832 ^ _971;
assign _973 = compare_instr_xor ^ _971;
assign _974 = _789[31:31];
assign _831 = _799[31:31];
assign compare_instr_sltu = _831 ^ _974;
assign _976 = compare_instr_sltu ^ _974;
assign _977 = _789[30:30];
assign _830 = _799[30:30];
assign compare_instr_slt = _830 ^ _977;
assign _979 = compare_instr_slt ^ _977;
assign _980 = _789[29:29];
assign _829 = _799[29:29];
assign compare_instr_sll = _829 ^ _980;
assign _982 = compare_instr_sll ^ _980;
assign _983 = _789[28:28];
assign _828 = _799[28:28];
assign compare_instr_sub = _828 ^ _983;
assign _985 = compare_instr_sub ^ _983;
assign _986 = _789[27:27];
assign _827 = _799[27:27];
assign compare_instr_add = _827 ^ _986;
assign _988 = compare_instr_add ^ _986;
assign _989 = _789[26:26];
assign _826 = _799[26:26];
assign compare_instr_srai = _826 ^ _989;
assign _991 = compare_instr_srai ^ _989;
assign _992 = _789[25:25];
assign _825 = _799[25:25];
assign compare_instr_srli = _825 ^ _992;
assign _994 = compare_instr_srli ^ _992;
assign _995 = _789[24:24];
assign _824 = _799[24:24];
assign compare_instr_slli = _824 ^ _995;
assign _997 = compare_instr_slli ^ _995;
assign _998 = _789[23:23];
assign _823 = _799[23:23];
assign compare_instr_andi = _823 ^ _998;
assign _1000 = compare_instr_andi ^ _998;
assign _1001 = _789[22:22];
assign _822 = _799[22:22];
assign compare_instr_ori = _822 ^ _1001;
assign _1003 = compare_instr_ori ^ _1001;
assign _1004 = _789[21:21];
assign _821 = _799[21:21];
assign compare_instr_xori = _821 ^ _1004;
assign _1006 = compare_instr_xori ^ _1004;
assign _1007 = _789[20:20];
assign _820 = _799[20:20];
assign compare_instr_sltiu = _820 ^ _1007;
assign _1009 = compare_instr_sltiu ^ _1007;
assign _1010 = _789[19:19];
assign _819 = _799[19:19];
assign compare_instr_slti = _819 ^ _1010;
assign _1012 = compare_instr_slti ^ _1010;
assign _1013 = _789[18:18];
assign _818 = _799[18:18];
assign compare_instr_addi = _818 ^ _1013;
assign _1015 = compare_instr_addi ^ _1013;
assign _1016 = _789[17:17];
assign _817 = _799[17:17];
assign compare_instr_sw = _817 ^ _1016;
assign _1018 = compare_instr_sw ^ _1016;
assign _1019 = _789[16:16];
assign _816 = _799[16:16];
assign compare_instr_sh = _816 ^ _1019;
assign _1021 = compare_instr_sh ^ _1019;
assign _1022 = _789[15:15];
assign _815 = _799[15:15];
assign compare_instr_sb = _815 ^ _1022;
assign _1024 = compare_instr_sb ^ _1022;
assign _1025 = _789[14:14];
assign _814 = _799[14:14];
assign compare_instr_lhu = _814 ^ _1025;
assign _1027 = compare_instr_lhu ^ _1025;
assign _1028 = _789[13:13];
assign _813 = _799[13:13];
assign compare_instr_lbu = _813 ^ _1028;
assign _1030 = compare_instr_lbu ^ _1028;
assign _1031 = _789[12:12];
assign _812 = _799[12:12];
assign compare_instr_lw = _812 ^ _1031;
assign _1033 = compare_instr_lw ^ _1031;
assign _1034 = _789[11:11];
assign _811 = _799[11:11];
assign compare_instr_lh = _811 ^ _1034;
assign _1036 = compare_instr_lh ^ _1034;
assign _1037 = _789[10:10];
assign _810 = _799[10:10];
assign compare_instr_lb = _810 ^ _1037;
assign _1039 = compare_instr_lb ^ _1037;
assign _1040 = _789[9:9];
assign _809 = _799[9:9];
assign compare_instr_bgeu = _809 ^ _1040;
assign _1042 = compare_instr_bgeu ^ _1040;
assign _1043 = _789[8:8];
assign _808 = _799[8:8];
assign compare_instr_bltu = _808 ^ _1043;
assign _1045 = compare_instr_bltu ^ _1043;
assign _1046 = _789[7:7];
assign _807 = _799[7:7];
assign compare_instr_bge = _807 ^ _1046;
assign _1048 = compare_instr_bge ^ _1046;
assign _1049 = _789[6:6];
assign _806 = _799[6:6];
assign compare_instr_blt = _806 ^ _1049;
assign _1051 = compare_instr_blt ^ _1049;
assign _1052 = _789[5:5];
assign _805 = _799[5:5];
assign compare_instr_bne = _805 ^ _1052;
assign _1054 = compare_instr_bne ^ _1052;
assign _1055 = _789[4:4];
assign _804 = _799[4:4];
assign compare_instr_beq = _804 ^ _1055;
assign _1057 = compare_instr_beq ^ _1055;
assign _1058 = _789[3:3];
assign _803 = _799[3:3];
assign compare_instr_jalr = _803 ^ _1058;
assign _1060 = compare_instr_jalr ^ _1058;
assign _1061 = _789[2:2];
assign _802 = _799[2:2];
assign compare_instr_jal = _802 ^ _1061;
assign _1063 = compare_instr_jal ^ _1061;
assign _1064 = _789[1:1];
assign _801 = _799[1:1];
assign compare_instr_auipc = _801 ^ _1064;
assign _1066 = compare_instr_auipc ^ _1064;
picorv32_instruction_decoder
#( .ENABLE_COUNTERS(1), .ENABLE_REGS_16_31(1), .ENABLE_PCPI(0), .ENABLE_MUL(1), .ENABLE_IRQ(1), .ENABLE_IRQ_QREGS(1), .ENABLE_IRQ_TIMER(1), .irqregs_offset(32), .regindex_bits(6) )
the_picorv32_instruction_decoder
( .clk(clk), .resetn(resetn), .mem_do_rinst(mem_do_rinst), .mem_done(mem_done), .mem_rdata_latched(mem_rdata_latched), .mem_rdata_q(mem_rdata_q), .decoder_trigger(decoder_trigger), .decoder_pseudo_trigger(decoder_pseudo_trigger), .decoder_trigger_q(decoder_trigger_q), .decoded_imm_uj(_789[176:145]), .decoded_imm(_789[144:113]), .decoded_rs2(_789[112:107]), .decoded_rs1(_789[106:101]), .decoded_rd(_789[100:95]), .pcpi_insn(_789[94:63]), .is_rdcycle_rdcycleh_rdinstr_rdinstrh(_789[62:62]), .is_compare(_789[61:61]), .is_alu_reg_reg(_789[60:60]), .is_alu_reg_imm(_789[59:59]), .is_lbu_lhu_lw(_789[58:58]), .is_beq_bne_blt_bge_bltu_bgeu(_789[57:57]), .is_sltiu_bltu_sltu(_789[56:56]), .is_slti_blt_slt(_789[55:55]), .is_lui_auipc_jal_jalr_addi_add(_789[54:54]), .is_sll_srl_sra(_789[53:53]), .is_sb_sh_sw(_789[52:52]), .is_jalr_addi_slti_sltiu_xori_ori_andi(_789[51:51]), .is_slli_srli_srai(_789[50:50]), .is_lb_lh_lw_lbu_lhu(_789[49:49]), .is_lui_auipc_jal(_789[48:48]), .instr_trap(_789[47:47]), .instr_timer(_789[46:46]), .instr_waitirq(_789[45:45]), .instr_maskirq(_789[44:44]), .instr_retirq(_789[43:43]), .instr_setq(_789[42:42]), .instr_getq(_789[41:41]), .instr_rdinstrh(_789[40:40]), .instr_rdinstr(_789[39:39]), .instr_rdcycleh(_789[38:38]), .instr_rdcycle(_789[37:37]), .instr_and(_789[36:36]), .instr_or(_789[35:35]), .instr_sra(_789[34:34]), .instr_srl(_789[33:33]), .instr_xor(_789[32:32]), .instr_sltu(_789[31:31]), .instr_slt(_789[30:30]), .instr_sll(_789[29:29]), .instr_sub(_789[28:28]), .instr_add(_789[27:27]), .instr_srai(_789[26:26]), .instr_srli(_789[25:25]), .instr_slli(_789[24:24]), .instr_andi(_789[23:23]), .instr_ori(_789[22:22]), .instr_xori(_789[21:21]), .instr_sltiu(_789[20:20]), .instr_slti(_789[19:19]), .instr_addi(_789[18:18]), .instr_sw(_789[17:17]), .instr_sh(_789[16:16]), .instr_sb(_789[15:15]), .instr_lhu(_789[14:14]), .instr_lbu(_789[13:13]), .instr_lw(_789[12:12]), .instr_lh(_789[11:11]), .instr_lb(_789[10:10]), .instr_bgeu(_789[9:9]), .instr_bltu(_789[8:8]), .instr_bge(_789[7:7]), .instr_blt(_789[6:6]), .instr_bne(_789[5:5]), .instr_beq(_789[4:4]), .instr_jalr(_789[3:3]), .instr_jal(_789[2:2]), .instr_auipc(_789[1:1]), .instr_lui(_789[0:0]) );
assign _1067 = _789[0:0];
opicorv32_instruction_decoder
the_opicorv32_instruction_decoder
( .clk(clk), .resetn(resetn), .mem_do_rinst(mem_do_rinst), .mem_done(mem_done), .mem_rdata_latched(mem_rdata_latched), .mem_rdata_q(mem_rdata_q), .decoder_trigger(decoder_trigger), .decoder_pseudo_trigger(decoder_pseudo_trigger), .decoded_imm_uj(_791[176:145]), .decoded_imm(_791[144:113]), .decoded_rs2(_791[112:107]), .decoded_rs1(_791[106:101]), .decoded_rd(_791[100:95]), .pcpi_insn(_791[94:63]), .is(_791[62:48]), .instr(_791[47:0]) );
assign _799 = _791[47:0];
assign _800 = _799[0:0];
assign compare_instr_lui = _800 ^ _1067;
assign _1069 = compare_instr_lui ^ _1067;
/* aliases */
/* output assignments */
assign instr_lui = _1069;
assign instr_auipc = _1066;
assign instr_jal = _1063;
assign instr_jalr = _1060;
assign instr_beq = _1057;
assign instr_bne = _1054;
assign instr_blt = _1051;
assign instr_bge = _1048;
assign instr_bltu = _1045;
assign instr_bgeu = _1042;
assign instr_lb = _1039;
assign instr_lh = _1036;
assign instr_lw = _1033;
assign instr_lbu = _1030;
assign instr_lhu = _1027;
assign instr_sb = _1024;
assign instr_sh = _1021;
assign instr_sw = _1018;
assign instr_addi = _1015;
assign instr_slti = _1012;
assign instr_sltiu = _1009;
assign instr_xori = _1006;
assign instr_ori = _1003;
assign instr_andi = _1000;
assign instr_slli = _997;
assign instr_srli = _994;
assign instr_srai = _991;
assign instr_add = _988;
assign instr_sub = _985;
assign instr_sll = _982;
assign instr_slt = _979;
assign instr_sltu = _976;
assign instr_xor = _973;
assign instr_srl = _970;
assign instr_sra = _967;
assign instr_or = _964;
assign instr_and = _961;
assign instr_rdcycle = _958;
assign instr_rdcycleh = _955;
assign instr_rdinstr = _952;
assign instr_rdinstrh = _949;
assign instr_getq = _946;
assign instr_setq = _943;
assign instr_retirq = _940;
assign instr_maskirq = _937;
assign instr_waitirq = _934;
assign instr_timer = _931;
assign instr_trap = _928;
assign is_lui_auipc_jal = _925;
assign is_lb_lh_lw_lbu_lhu = _922;
assign is_slli_srli_srai = _919;
assign is_jalr_addi_slti_sltiu_xori_ori_andi = _916;
assign is_sb_sh_sw = _913;
assign is_sll_srl_sra = _910;
assign is_lui_auipc_jal_jalr_addi_add = _907;
assign is_slti_blt_slt = _904;
assign is_sltiu_bltu_sltu = _901;
assign is_beq_bne_blt_bge_bltu_bgeu = _898;
assign is_lbu_lhu_lw = _895;
assign is_alu_reg_imm = _892;
assign is_alu_reg_reg = _889;
assign is_compare = _886;
assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = _883;
assign pcpi_insn = _880;
assign decoded_rd = _877;
assign decoded_rs1 = _874;
assign decoded_rs2 = _871;
assign decoded_imm = _868;
assign decoded_imm_uj = _865;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_gpiov2 (IN_H, PAD_A_NOESD_H,PAD_A_ESD_0_H,PAD_A_ESD_1_H,
PAD, DM, HLD_H_N, IN, INP_DIS, IB_MODE_SEL, ENABLE_H, ENABLE_VDDA_H, ENABLE_INP_H, OE_N,
TIE_HI_ESD, TIE_LO_ESD, SLOW, VTRIP_SEL, HLD_OVR, ANALOG_EN, ANALOG_SEL, ENABLE_VDDIO, ENABLE_VSWITCH_H,
ANALOG_POL, OUT, AMUXBUS_A, AMUXBUS_B
,VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD, VSSIO,
VSSD, VSSIO_Q
);
input OUT;
input OE_N;
input HLD_H_N;
input ENABLE_H;
input ENABLE_INP_H;
input ENABLE_VDDA_H;
input ENABLE_VSWITCH_H;
input ENABLE_VDDIO;
input INP_DIS;
input IB_MODE_SEL;
input VTRIP_SEL;
input SLOW;
input HLD_OVR;
input ANALOG_EN;
input ANALOG_SEL;
input ANALOG_POL;
input [2:0] DM;
inout VDDIO;
inout VDDIO_Q;
inout VDDA;
inout VCCD;
inout VSWITCH;
inout VCCHIB;
inout VSSA;
inout VSSD;
inout VSSIO_Q;
inout VSSIO;
inout PAD;
inout PAD_A_NOESD_H,PAD_A_ESD_0_H,PAD_A_ESD_1_H;
inout AMUXBUS_A;
inout AMUXBUS_B;
output IN;
output IN_H;
output TIE_HI_ESD, TIE_LO_ESD;
reg [2:0] dm_final;
reg slow_final, vtrip_sel_final, inp_dis_final, out_final, oe_n_final, hld_ovr_final, analog_en_final, ib_mode_sel_final, analog_en_vdda, analog_en_vswitch,analog_en_vddio_q;
wire [2:0] dm_buf;
wire slow_buf, vtrip_sel_buf, inp_dis_buf, out_buf, oe_n_buf, hld_ovr_buf,ib_mode_sel_buf;
wire [2:0] dm_del;
wire slow_del, vtrip_sel_del, inp_dis_del, out_del, oe_n_del, hld_ovr_del,ib_mode_sel_del;
wire hld_h_n_del;
wire hld_h_n_buf;
reg notifier_dm, notifier_slow, notifier_oe_n, notifier_out, notifier_vtrip_sel, notifier_hld_ovr, notifier_inp_dis, notifier_ib_mode_sel;
reg notifier_enable_h, notifier;
assign hld_h_n_buf = HLD_H_N;
assign hld_ovr_buf = HLD_OVR;
assign dm_buf = DM;
assign inp_dis_buf = INP_DIS;
assign vtrip_sel_buf = VTRIP_SEL;
assign slow_buf = SLOW;
assign oe_n_buf = OE_N;
assign out_buf = OUT;
assign ib_mode_sel_buf = IB_MODE_SEL;
wire pwr_good_amux = ((hld_h_n_buf===0 || ENABLE_H===0) ? 1:(VCCD===1)) && (VSSD===0) && (VSSA===0) && (VSSIO_Q===0);
wire pwr_good_hold_ovr_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0) && (VCCHIB===1);
wire pwr_good_active_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0) && (VCCD===1);
wire pwr_good_hold_mode = (VDDIO_Q===1) && (VDDIO===1) && (VSSD===0);
wire pwr_good_active_mode_vdda = (VDDA===1) && (VSSD===0) && (VCCD===1);
wire pwr_good_hold_mode_vdda = (VDDA===1) && (VSSD===0);
wire pwr_good_inpbuff_hv = (VDDIO_Q===1) && (VSSD===0) && (inp_dis_final===0 && dm_final!==3'b000 && ib_mode_sel_final===1 ? VCCHIB===1 : 1);
wire pwr_good_inpbuff_lv = (VDDIO_Q===1) && (VSSD===0) && (VCCHIB===1);
wire pwr_good_output_driver = (VDDIO===1) && (VDDIO_Q===1)&& (VSSIO===0) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vdda = (VDDA===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vddio_q = (VDDIO_Q ===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_analog_en_vswitch = (VSWITCH ===1) && (VSSD===0) && (VSSA===0) ;
wire pwr_good_amux_vccd = ((hld_h_n_buf===0 || ENABLE_H===0) ? 1:(VCCD===1));
parameter MAX_WARNING_COUNT = 100;
wire pad_tristate = oe_n_final === 1 || dm_final === 3'b000 || dm_final === 3'b001;
wire x_on_pad = !pwr_good_output_driver
|| (dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'bx)
|| (^dm_final[2:0] === 1'bx && oe_n_final===1'b0)
|| (slow_final===1'bx && dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'b0);
`ifdef SKY130_FD_IO_TOP_GPIOV2_SLOW_BEHV
parameter SLOW_1_DELAY= 70;
parameter SLOW_0_DELAY= 40;
`else
parameter SLOW_1_DELAY= 0;
parameter SLOW_0_DELAY= 0;
`endif
integer slow_1_delay,slow_0_delay,slow_delay;
initial slow_1_delay = SLOW_1_DELAY;
initial slow_0_delay = SLOW_0_DELAY;
always @(*)
begin
if (SLOW===1)
slow_delay = slow_1_delay;
else
slow_delay = slow_0_delay;
end
bufif1 (pull1, strong0) #slow_delay dm2 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b010));
bufif1 (strong1, pull0) #slow_delay dm3 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b011));
bufif1 (highz1, strong0) #slow_delay dm4 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b100));
bufif1 (strong1, highz0) #slow_delay dm5 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b101));
bufif1 (strong1, strong0) #slow_delay dm6 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b110));
bufif1 (pull1, pull0) #slow_delay dm7 (PAD, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b111));
tran pad_esd_1 (PAD,PAD_A_NOESD_H);
tran pad_esd_2 (PAD,PAD_A_ESD_0_H);
tran pad_esd_3 (PAD,PAD_A_ESD_1_H);
wire x_on_in_hv = (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===1'b1)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===1'b0);
wire x_on_in_lv = (ENABLE_H===0 && ^ENABLE_INP_H===1'bx)
|| (inp_dis_final===1'bx && ^dm_final[2:0]!==1'bx && dm_final !== 3'b000)
|| (ENABLE_H===0 && ^ENABLE_VDDIO===1'bx)
|| (^ENABLE_H===1'bx)
|| (inp_dis_final===0 && ^dm_final[2:0] === 1'bx)
|| (ib_mode_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (^ENABLE_VDDIO===1'bx && inp_dis_final===0 && dm_final !== 3'b000)
|| (vtrip_sel_final===1'bx && inp_dis_final===0 && dm_final !== 3'b000 && ib_mode_sel_final===1'b0);
wire disable_inp_buff = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_INP_H===0;
assign IN_H = (x_on_in_hv===1 || pwr_good_inpbuff_hv===0) ? 1'bx : (disable_inp_buff===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
wire disable_inp_buff_lv = ENABLE_H===1 ? (dm_final===3'b000 || inp_dis_final===1) : ENABLE_VDDIO===0;
assign IN = (x_on_in_lv===1 || pwr_good_inpbuff_lv===0 ) ? 1'bx : (disable_inp_buff_lv===1 ? 0 : (^PAD===1'bx ? 1'bx : PAD));
assign TIE_HI_ESD = VDDIO===1'b1 ? 1'b1 : 1'bx;
assign TIE_LO_ESD = VSSIO===1'b0 ? 1'b0 : 1'bx;
wire functional_mode_amux = (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_analog_en_vswitch ===1 );
wire x_on_analog_en_vdda = (pwr_good_analog_en_vdda !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VDDA_H ===1'bx) ));
wire zero_on_analog_en_vdda = ( (pwr_good_analog_en_vdda ===1 && ENABLE_VDDA_H ===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vdda ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vddio_q = ( pwr_good_analog_en_vddio_q !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) ));
wire zero_on_analog_en_vddio_q = ( (pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
wire x_on_analog_en_vswitch = (pwr_good_analog_en_vswitch !==1
|| (functional_mode_amux ==1 && (ENABLE_H !==0 && ^hld_h_n_buf === 1'bx) || (hld_h_n_buf!== 0 && ^ENABLE_H=== 1'bx) || pwr_good_amux_vccd !==1 )
|| (functional_mode_amux ==1 && (hld_h_n_buf ===1 && ENABLE_H===1 && ^ANALOG_EN === 1'bx && ENABLE_VDDA_H ===1 && ENABLE_VSWITCH_H===1 ) || (hld_h_n_buf ===1 && ENABLE_H===1 && ANALOG_EN ===0 && ^ENABLE_VSWITCH_H ===1'bx) ));
wire zero_on_analog_en_vswitch = ( (pwr_good_analog_en_vswitch ===1 && ENABLE_VSWITCH_H ===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && hld_h_n_buf===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && ENABLE_H===0)
|| (pwr_good_analog_en_vswitch ===1 && pwr_good_analog_en_vddio_q ===1 && pwr_good_amux_vccd && ANALOG_EN===0) );
always @(*)
begin : LATCH_dm
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
dm_final <= 3'bxxx;
end
else if (ENABLE_H===0)
begin
dm_final <= 3'b000;
end
else if (hld_h_n_buf===1)
begin
dm_final <= (^dm_buf[2:0] === 1'bx || !pwr_good_active_mode) ? 3'bxxx : dm_buf;
end
end
always @(notifier_enable_h or notifier_dm)
begin
disable LATCH_dm; dm_final <= 3'bxxx;
end
always @(*)
begin : LATCH_inp_dis
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
inp_dis_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
inp_dis_final <= 1'b1;
end
else if (hld_h_n_buf===1)
begin
inp_dis_final <= (^inp_dis_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : inp_dis_buf;
end
end
always @(notifier_enable_h or notifier_inp_dis)
begin
disable LATCH_inp_dis; inp_dis_final <= 1'bx;
end
always @(*)
begin : LATCH_vtrip_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
vtrip_sel_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
vtrip_sel_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
vtrip_sel_final <= (^vtrip_sel_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : vtrip_sel_buf;
end
end
always @(notifier_enable_h or notifier_vtrip_sel)
begin
disable LATCH_vtrip_sel; vtrip_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_ib_mode_sel
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
ib_mode_sel_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
ib_mode_sel_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
ib_mode_sel_final <= (^ib_mode_sel_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : ib_mode_sel_buf;
end
end
always @(notifier_enable_h or notifier_ib_mode_sel)
begin
disable LATCH_ib_mode_sel; ib_mode_sel_final <= 1'bx;
end
always @(*)
begin : LATCH_slow
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
slow_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
slow_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
slow_final <= (^slow_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : slow_buf;
end
end
always @(notifier_enable_h or notifier_slow)
begin
disable LATCH_slow; slow_final <= 1'bx;
end
always @(*)
begin : LATCH_hld_ovr
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && ^hld_h_n_buf===1'bx))
begin
hld_ovr_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
hld_ovr_final <= 1'b0;
end
else if (hld_h_n_buf===1)
begin
hld_ovr_final <= (^hld_ovr_buf === 1'bx || !pwr_good_active_mode) ? 1'bx : hld_ovr_buf;
end
end
always @(notifier_enable_h or notifier_hld_ovr)
begin
disable LATCH_hld_ovr; hld_ovr_final <= 1'bx;
end
always @(*)
begin : LATCH_oe_n
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx || (hld_h_n_buf===0 && hld_ovr_final===1'bx) || (hld_h_n_buf===1 && hld_ovr_final===1'bx))))
begin
oe_n_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
oe_n_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
oe_n_final <= (^oe_n_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : oe_n_buf;
end
end
always @(notifier_enable_h or notifier_oe_n)
begin
disable LATCH_oe_n; oe_n_final <= 1'bx;
end
always @(*)
begin : LATCH_out
if (^ENABLE_H===1'bx || !pwr_good_hold_mode || (ENABLE_H===1 && (^hld_h_n_buf===1'bx ||(hld_h_n_buf===0 && hld_ovr_final===1'bx || (hld_h_n_buf===1 && hld_ovr_final===1'bx)))))
begin
out_final <= 1'bx;
end
else if (ENABLE_H===0)
begin
out_final <= 1'b1;
end
else if (hld_h_n_buf===1 || hld_ovr_final===1)
begin
out_final <= (^out_buf === 1'bx || !pwr_good_hold_ovr_mode) ? 1'bx : out_buf;
end
end
always @(notifier_enable_h or notifier_out)
begin
disable LATCH_out; out_final <= 1'bx;
end
always @(*)
begin
if (x_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'bx;
end
else if ( zero_on_analog_en_vdda ===1 )
begin
analog_en_vdda <= 1'b0;
end
else if (x_on_analog_en_vdda !==1 && zero_on_analog_en_vdda !==1)
begin
analog_en_vdda <= ANALOG_EN;
end
if (x_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'bx;
end
else if ( zero_on_analog_en_vddio_q ===1 )
begin
analog_en_vddio_q <= 1'b0;
end
else if ( x_on_analog_en_vddio_q !==1 && zero_on_analog_en_vddio_q !==1)
begin
analog_en_vddio_q <= ANALOG_EN;
end
if (x_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'bx;
end
else if ( zero_on_analog_en_vswitch ===1 )
begin
analog_en_vswitch <= 1'b0;
end
else if (x_on_analog_en_vswitch !==1 && zero_on_analog_en_vswitch !==1)
begin
analog_en_vswitch <= ANALOG_EN;
end
if ( (analog_en_vswitch ===1'bx && analog_en_vdda ===1'bx) || (analog_en_vswitch ===1'bx && analog_en_vddio_q ===1'bx) || (analog_en_vddio_q ===1'bx && analog_en_vdda ===1'bx ) )
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vdda ===1'bx && (analog_en_vddio_q ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vddio_q ===1'bx && (analog_en_vdda ===1 ||analog_en_vswitch===1 ))
begin
analog_en_final <= 1'bx;
end
else if (analog_en_vswitch===1'bx && (analog_en_vdda ===1 || analog_en_vddio_q ===1 ))
begin
analog_en_final <= 1'bx;
end
else if ((analog_en_vdda ===0 && analog_en_vddio_q ===0 )|| (analog_en_vdda ===0 && analog_en_vswitch===0 ) || (analog_en_vddio_q ===0 && analog_en_vswitch===0 ))
begin
analog_en_final <=0;
end
else if (analog_en_vdda ===1 && analog_en_vddio_q ===1 && analog_en_vswitch ===1)
begin
analog_en_final <=1;
end
end
wire [2:0] amux_select = {ANALOG_SEL, ANALOG_POL, out_buf};
wire invalid_controls_amux = (analog_en_final===1'bx && inp_dis_final===1)
|| !pwr_good_amux
|| (analog_en_final===1 && ^amux_select[2:0] === 1'bx && inp_dis_final===1);
wire enable_pad_amuxbus_a = invalid_controls_amux ? 1'bx : (amux_select===3'b001 || amux_select===3'b010) && (analog_en_final===1);
wire enable_pad_amuxbus_b = invalid_controls_amux ? 1'bx : (amux_select===3'b101 || amux_select===3'b110) && (analog_en_final===1);
wire enable_pad_vssio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b100 || amux_select===3'b000) && (analog_en_final===1);
wire enable_pad_vddio_q = invalid_controls_amux ? 1'bx : (amux_select===3'b011 || amux_select===3'b111) && (analog_en_final===1);
tranif1 pad_amuxbus_a (PAD, AMUXBUS_A, enable_pad_amuxbus_a);
tranif1 pad_amuxbus_b (PAD, AMUXBUS_B, enable_pad_amuxbus_b);
bufif1 pad_vddio_q (PAD, VDDIO_Q, enable_pad_vddio_q);
bufif1 pad_vssio_q (PAD, VSSIO_Q, enable_pad_vssio_q);
reg dis_err_msgs;
integer msg_count_pad,msg_count_pad1,msg_count_pad2,msg_count_pad3,msg_count_pad4,msg_count_pad5,msg_count_pad6,msg_count_pad7,msg_count_pad8,msg_count_pad9,msg_count_pad10,msg_count_pad11,msg_count_pad12;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0;
msg_count_pad1 = 0;
msg_count_pad2 = 0;
msg_count_pad3 = 0;
msg_count_pad4 = 0;
msg_count_pad5 = 0;
msg_count_pad6 = 0;
msg_count_pad7 = 0;
msg_count_pad8 = 0;
msg_count_pad9 = 0;
msg_count_pad10 = 0;
msg_count_pad11 = 0;
msg_count_pad12 = 0;
`ifdef SKY130_FD_IO_TOP_GPIOV2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
wire #100 error_enable_vddio = (ENABLE_VDDIO===0 && ENABLE_H===1);
event event_error_enable_vddio;
always @(error_enable_vddio)
begin
if (!dis_err_msgs)
begin
if (error_enable_vddio===1)
begin
msg_count_pad = msg_count_pad + 1;
->event_error_enable_vddio;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : Enable_h (= %b) and ENABLE_VDDIO (= %b) are complement of each \other. This is an illegal combination as ENABLE_VDDIO and ENABLE_H are the same input signals IN different power \domains %m", ENABLE_H, ENABLE_VDDIO, $stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda = ( VDDA===1 && VDDIO_Q !==1 && ENABLE_VDDA_H===1 );
event event_error_vdda;
always @(error_vdda)
begin
if (!dis_err_msgs)
begin
if (error_vdda===1)
begin
msg_count_pad1 = msg_count_pad1 + 1;
->event_error_vdda;
if (msg_count_pad1 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VDDA_H (= %b) cannot be 1 when VDDA (= %b) and VDDIO_Q (= %b) %m",ENABLE_VDDA_H, VDDA,VDDIO_Q,$stime);
end
else
if (msg_count_pad1 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda2 = ( VDDA===1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && VCCD===1 && ANALOG_EN ===1 );
event event_error_vdda2;
always @(error_vdda2)
begin
if (!dis_err_msgs)
begin
if (error_vdda2===1)
begin
msg_count_pad2 = msg_count_pad2 + 1;
->event_error_vdda2;
if (msg_count_pad2 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ANALOG_EN (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b),hld_h_n_buf (= %b) and VCCD (= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad2 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda3 = ( VDDA===1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H===1 && hld_h_n_buf ===1 && VCCD !==1 );
event event_error_vdda3;
always @(error_vdda3)
begin
if (!dis_err_msgs)
begin
if (error_vdda3===1)
begin
msg_count_pad3 = msg_count_pad3 + 1;
->event_error_vdda3;
if (msg_count_pad3 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : VCCD (= %b) cannot be any value other than 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",VCCD,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad3 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch1 = (VDDA !==1 && VDDIO_Q !==1 && VSWITCH ===1 && (ENABLE_VSWITCH_H===1)) ;
event event_error_vswitch1;
always @(error_vswitch1)
begin
if (!dis_err_msgs)
begin
if (error_vswitch1===1)
begin
msg_count_pad4 = msg_count_pad4 + 1;
->event_error_vswitch1;
if (msg_count_pad4 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VSWITCH_H (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad4 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch2 = (VDDA !==1 && VDDIO_Q !==1 && VSWITCH ===1 && VCCD===1 && ANALOG_EN===1);
event event_error_vswitch2;
always @(error_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vswitch2===1)
begin
msg_count_pad5 = msg_count_pad5 + 1;
->event_error_vswitch2;
if (msg_count_pad5 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ANALOG_EN (= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b) & VCCD(= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,VCCD,$stime);
end
else
if (msg_count_pad5 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch3 = (VDDA ===1 && VDDIO_Q !==1 && VSWITCH ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch3;
always @(error_vswitch3)
begin
if (!dis_err_msgs)
begin
if (error_vswitch3===1)
begin
msg_count_pad6 = msg_count_pad6 + 1;
->event_error_vswitch3;
if (msg_count_pad6 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad6 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch4 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_VSWITCH_H===1);
event event_error_vswitch4;
always @(error_vswitch4)
begin
if (!dis_err_msgs)
begin
if (error_vswitch4===1)
begin
msg_count_pad7 = msg_count_pad7 + 1;
->event_error_vswitch4;
if (msg_count_pad7 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VSWITCH_H(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) & VSWITCH(= %b) %m",ENABLE_VSWITCH_H,VDDA,VDDIO_Q,VSWITCH,$stime);
end
else
if (msg_count_pad7 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vswitch5 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1);
event event_error_vswitch5;
always @(error_vswitch5)
begin
if (!dis_err_msgs)
begin
if (error_vswitch5===1)
begin
msg_count_pad8 = msg_count_pad8 + 1;
->event_error_vswitch5;
if (msg_count_pad8 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ANALOG_EN(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b),hld_h_n_buf (= %b) and VCCD (= %b) %m",ANALOG_EN,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad8 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q1 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD!==1);
event event_error_vddio_q1;
always @(error_vddio_q1)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q1===1)
begin
msg_count_pad9 = msg_count_pad9 + 1;
->event_error_vddio_q1;
if (msg_count_pad9 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : VCCD(= %b) cannot be any value other than 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b) and hld_h_n_buf (= %b) %m",VCCD,VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,$stime);
end
else
if (msg_count_pad9 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vddio_q2 = (VDDA !==1 && VDDIO_Q ===1 && VSWITCH !==1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1);
event event_error_vddio_q2;
always @(error_vddio_q2)
begin
if (!dis_err_msgs)
begin
if (error_vddio_q2===1)
begin
msg_count_pad10 = msg_count_pad10 + 1;
->event_error_vddio_q2;
if (msg_count_pad10 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ANALOG_EN(= %b) cannot be 1 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b),ENABLE_H (= %b) , hld_h_n_buf (= %b) && VCCD (= %b) %m",ANALOG_EN, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,$stime);
end
else
if (msg_count_pad10 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_supply_good = ( VDDA ===1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1 && ENABLE_VSWITCH_H !==1 && ENABLE_VSWITCH_H !==0 );
event event_error_supply_good;
always @(error_supply_good)
begin
if (!dis_err_msgs)
begin
if (error_supply_good===1)
begin
msg_count_pad11 = msg_count_pad11 + 1;
->event_error_supply_good;
if (msg_count_pad11 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VSWITCH_H(= %b) should be either 1 or 0 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,VCCD (= %b) and ANALOG_EN(= %b) %m",ENABLE_VSWITCH_H, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,ANALOG_EN,$stime);
end
else
if (msg_count_pad11 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
wire #100 error_vdda_vddioq_vswitch2 = ( VDDA ===1 && VDDIO_Q ===1 && VSWITCH ===1 && ENABLE_H ===1 && hld_h_n_buf ===1 && VCCD ===1 && ANALOG_EN===1 && ENABLE_VDDA_H !==1 && ENABLE_VDDA_H !==0 );
event event_error_vdda_vddioq_vswitch2;
always @(error_vdda_vddioq_vswitch2)
begin
if (!dis_err_msgs)
begin
if (error_vdda_vddioq_vswitch2===1)
begin
msg_count_pad12 = msg_count_pad12 + 1;
->event_error_vdda_vddioq_vswitch2;
if (msg_count_pad12 <= MAX_WARNING_COUNT)
begin
$display(" ===ERROR=== sky130_fd_io__top_gpiov2 : ENABLE_VDDA_H(= %b) should be either 1 or 0 when VDDA (= %b) , VDDIO_Q (= %b) , VSWITCH(= %b), ENABLE_H (= %b), hld_h_n_buf (= %b) ,VCCD (= %b) and ANALOG_EN(= %b) %m",ENABLE_VDDA_H, VDDA,VDDIO_Q,VSWITCH,ENABLE_H,hld_h_n_buf,VCCD,ANALOG_EN,$stime);
end
else
if (msg_count_pad12 == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_gpiov2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
module display_refresher(
input clk,
input DISPLAY1,
input DISPLAY2,
input DISPLAY3,
input DISPLAY4,
output reg [6:0] DISPLAY,
output reg [3:0] ANODES,
output reg contador_seg
);
/* HERE STARTS THE REFRESHING MACHINE */
reg [1:0] Prstate, Nxtstate;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
initial begin Prstate = S0; end
//frecuencia de cambio entre cada display (agregar al informe, en el manual de Xilinx de la Nexys3 viene)
(* keep="soft" *)
wire CLK_1Hz;
(* keep="soft" *)
wire CLK_2Hz;
wire CLK_1KHz;
frequency_divider divisor (CLK_1Hz, CLK_2Hz, CLK_1KHz, clk);
always @ (posedge CLK_1KHz) begin
Prstate = Nxtstate;
end
always @ (posedge CLK_1Hz)
begin
contador_seg = contador_seg + 1;
if (contador_seg == 10)
contador_seg = 0;
end
always @ (Prstate)
case (Prstate)
S0: Nxtstate = S1;
S1: Nxtstate = S2;
S2: Nxtstate = S3;
S3: Nxtstate = S0;
default: Nxtstate = S0;
endcase
always @ (*)
case (Prstate)
S0: // 1,2,3 o 4, en caso de espera es in -
begin
ANODES = 4'b1110;//se indica con un 0 el display
DISPLAY = DISPLAY1;
end
S1: // P
begin
ANODES = 4'b1101;
DISPLAY = DISPLAY2;
end
S2: // A o C
begin
ANODES = 4'b1011;
DISPLAY = DISPLAY3;
end
S3: // S o B
begin
ANODES = 4'b0111;
DISPLAY = DISPLAY4;
end
default:
begin // por defecto esta en espera ----
ANODES = 4'b0000;
DISPLAY = 7'b1111110;
end
endcase
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21A_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O21A_PP_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21A_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O22A_TB_V
`define SKY130_FD_SC_HVL__O22A_TB_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__o22a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hvl__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O22A_TB_V
|
Require Export Iron.Language.SimpleRef.Base.
(********************************************************************)
(* Types *)
Inductive ty : Type :=
| TCon : nat -> ty (* data type constructor *)
| TFun : ty -> ty -> ty (* function type constructor *)
| TRef : ty -> ty. (* reference type constructor *)
Hint Constructors ty.
(* Baked in types. *)
Definition tUnit := TCon 0.
(* Type Environment. *)
Definition tyenv := list ty.
(* Store typing. *)
Definition stenv := list ty.
(********************************************************************)
(* Value Expressions *)
Inductive exp : Type :=
(* Base calculus. *)
| XCon : nat -> exp (* data constructor *)
| XVar : nat -> exp (* deBruijn index *)
| XLam : ty -> exp -> exp (* function abstraction *)
| XApp : exp -> exp -> exp (* function application *)
(* Primitive operators.
We want to define these in fully applied form because so we don't
need to worry about partial application in the typing rules. We
can't use XApp directly becuase the primitives need to be
polymorphic but we only have a monomorphic base calculus. *)
| XNewRef : exp -> exp (* allocate a new reference *)
| XReadRef : exp -> exp (* read a references *)
| XWriteRef : exp -> exp -> exp (* write to a reference *)
(* Expressions created during reduction,
and not usually part of the initial program. *)
| XLoc : nat -> exp. (* store location *)
Hint Constructors exp.
(* The unit data constructor. *)
Definition xUnit := XCon 0.
Hint Unfold xUnit.
(* A heap is a list of expressions.
Later we will define a judegment TYPEH that ensures that well
formed heaps are always closed. *)
Definition heap := list exp.
Hint Unfold heap.
(* Weak normal forms.
Expressions in weak normal form cannot be reduced further by
call-by-value evaluation. *)
Inductive wnfX : exp -> Prop :=
| Wnf_XCon
: forall n
, wnfX (XCon n)
| Wnf_XVar
: forall i
, wnfX (XVar i)
| Wnf_XLam
: forall t1 x2
, wnfX (XLam t1 x2)
| Wnf_XLoc
: forall l
, wnfX (XLoc l).
Hint Constructors wnfX.
(* Well formed expressions are closed under the given environment. *)
Fixpoint wfX (te: tyenv) (xx: exp) : Prop :=
match xx with
| XCon _ => True
| XVar i => exists t, get i te = Some t
| XLam t x => wfX (te :> t) x
| XApp x1 x2 => wfX te x1 /\ wfX te x2
| XNewRef x => wfX te x
| XReadRef x => wfX te x
| XWriteRef x1 x2 => wfX te x1 /\ wfX te x2
| XLoc _ => True
end.
(* Closed expressions are well formed under an empty environment. *)
Definition closedX (xx: exp) : Prop
:= wfX nil xx.
Hint Unfold closedX.
(* Values are closed expressions that cannot be reduced further. *)
Definition value (x : exp)
:= wnfX x /\ closedX x.
Lemma value_wnfX
: forall xx, value xx -> wnfX xx.
Proof. intros. inverts H. auto. Qed.
Hint Resolve value_wnfX.
Lemma value_closedX
: forall xx, value xx -> closedX xx.
Proof. intros. inverts H. auto. Qed.
Hint Resolve value_closedX.
(********************************************************************)
(* Lifting of references into the environment.
When we push new elements on the environment stack, we need
to lift referenes to existing elements across the new ones.
For example given:
t1, t0 |- 0 1 (\. 0 1 2) :: t3
Pushing two more elements gives:
t1, t0, ta, tb |- 2 3 (\. 0 3 4) :: t3
*)
Fixpoint
liftX (d: nat) (* current binding depth in expression *)
(xx: exp) (* expression containing referenes to lift *)
: exp
:= match xx with
| XCon i
=> XCon i
| XVar ix
=> if le_gt_dec d ix
(* Index is referencing the env, so lift it across the new elem *)
then XVar (S ix)
(* Index is locally bound in the expression itself, and
not the environment, so we don't need to change it. *)
else xx
(* Increase the current depth as we move across a lambda,
if we find locally bound indices that reference this lambda
then we don't need to lift them. *)
| XLam t1 x1
=> XLam t1 (liftX (S d) x1)
| XApp x1 x2
=> XApp (liftX d x1) (liftX d x2)
| XNewRef x1
=> XNewRef (liftX d x1)
| XReadRef x1
=> XReadRef (liftX d x1)
| XWriteRef x1 x2
=> XWriteRef (liftX d x1) (liftX d x2)
| XLoc l
=> XLoc l
end.
(*******************************************************************)
(* Substitute for the outermost binder in an expression. *)
Fixpoint
substX (d: nat) (* current binding depth in expression *)
(u: exp) (* new expression to substitute *)
(xx: exp) (* expression to substitute into *)
: exp
:= match xx with
| XCon i
=> XCon i
| XVar ix
=> match nat_compare ix d with
(* Index matches the one we are substituting for. *)
| Eq => u
(* Index was free in the original expression.
As we've removed the outermost binder, also decrease this
index by one. *)
| Gt => XVar (ix - 1)
(* Index was bound in the original expression. *)
| Lt => XVar ix
end
(* Increase the depth as we move across a lambda.
Any free references in the exp being substitued also need
to be lifted across the lambda as we enter it. *)
| XLam t1 x2
=> XLam t1 (substX (S d) (liftX 0 u) x2)
| XApp x1 x2
=> XApp (substX d u x1) (substX d u x2)
| XNewRef x1
=> XNewRef (substX d u x1)
| XReadRef x1
=> XReadRef (substX d u x1)
| XWriteRef x1 x2
=> XWriteRef (substX d u x1) (substX d u x2)
| XLoc l
=> XLoc l
end.
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_3_cols_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_3_cols_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_3_cols_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_3_cols_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/*
* Titor - Barrel Processor - A convenience module for referencing fields of the instruction
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Splitter
`else
`define INC_Splitter
`timescale 1 ns / 100 ps
// Combinational module
// splits the instruction into constituent pieces
module Splitter (
instruction,
fld_opcode,
fld_affect,
fld_field0,
fld_field1,
fld_field2,
fld_shift_type,
fld_shift_IR,
fld_shamt_S,
fld_shamt_I,
fld_shamt_R,
fld_immediate
);
`include "definition/Definition.v"
input [WORD-1 :0] instruction;
output reg [WIDTH_OPCODE-1 :0] fld_opcode;
output reg [WIDTH_AFFECT-1 :0] fld_affect;
output reg [WIDTH_FIELD0-1 :0] fld_field0;
output reg [WIDTH_FIELD1-1 :0] fld_field1;
output reg [WIDTH_FIELD2-1 :0] fld_field2;
output reg [WIDTH_SHIFT_TYPE-1 :0] fld_shift_type;
output reg [WIDTH_SHIFT_IR-1 :0] fld_shift_IR;
output reg [WIDTH_SHAMT_S-1 :0] fld_shamt_S;
output reg [WIDTH_SHAMT_I-1 :0] fld_shamt_I;
output reg [WIDTH_SHAMT_R-1 :0] fld_shamt_R;
output reg [WIDTH_IMMEDIATE-1 :0] fld_immediate;
always @(*) begin
fld_opcode <= instruction[VECT_OPCODE_H :VECT_OPCODE_L];
fld_affect <= instruction[VECT_AFFECT_H :VECT_AFFECT_L];
fld_field0 <= instruction[VECT_FIELD0_H :VECT_FIELD0_L];
fld_field1 <= instruction[VECT_FIELD1_H :VECT_FIELD1_L];
fld_field2 <= instruction[VECT_FIELD2_H :VECT_FIELD2_L];
fld_shift_type <= instruction[VECT_SHIFT_TYPE_H :VECT_SHIFT_TYPE_L];
fld_shift_IR <= instruction[VECT_SHIFT_IR_H :VECT_SHIFT_IR_L];
fld_shamt_S <= instruction[VECT_SHAMT_S_H :VECT_SHAMT_S_L];
fld_shamt_I <= instruction[VECT_SHAMT_I_H :VECT_SHAMT_I_L];
fld_shamt_R <= instruction[VECT_SHAMT_R_H :VECT_SHAMT_R_L];
fld_immediate <= instruction[VECT_IMMEDIATE_H :VECT_IMMEDIATE_L];
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_1_V
`define SKY130_FD_SC_HS__XNOR2_1_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xnor2_1 (
Y ,
A ,
B ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
`define SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_FUNCTIONAL_V
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The HCLKGEN module, mainly include the PLL to generate clock
//
// ====================================================================
`include "e203_defines.v"
module e203_subsys_hclkgen(
input test_mode,
input hfclkrst,// To reset the PLL Clock
input hfextclk,// The original clock from crystal
input pllbypass ,
input pll_RESET ,
input pll_ASLEEP ,
input [1:0] pll_OD,
input [7:0] pll_M,
input [4:0] pll_N,
input plloutdivby1,
input [5:0] plloutdiv,
output inspect_16m_clk,
output inspect_pll_clk,
output hfclk// The generated clock by this module
);
wire hfclkrst_n = ~hfclkrst;
// The PLL module
wire plloutclk;
wire pll_powerd = pll_ASLEEP | hfclkrst; // Power down by PMU or the register programmed
e203_subsys_pll u_e203_subsys_pll(
.pll_asleep (pll_powerd ),
.pll_RESET (pll_RESET),
.pll_OD (pll_OD),
.pll_M (pll_M ),
.pll_N (pll_N ),
.pllrefclk (hfextclk ),
.plloutclk (plloutclk )
);
// The Reset syncer for the PLLout clk
wire plloutclk_rst_n;
e203_subsys_hclkgen_rstsync plloutclk_rstsync(
.clk (plloutclk),
.rst_n_a (hfclkrst_n),
.test_mode(test_mode),
.rst_n (plloutclk_rst_n)
);
// The Reset syncer for the HFextclk
wire hfextclk_rst_n;
e203_subsys_hclkgen_rstsync hfextclk_rstsync(
.clk (hfextclk),
.rst_n_a (hfclkrst_n),
.test_mode(test_mode),
.rst_n (hfextclk_rst_n)
);
// The PLL divider
wire plloutdivclk;
e203_subsys_pllclkdiv u_e203_subsys_pllclkdiv(
.test_mode(test_mode),
.rst_n (plloutclk_rst_n),
.divby1(plloutdivby1),
.div (plloutdiv ),
.clk (plloutclk),// The PLL clock
.clkout(plloutdivclk) // The divided Clock
);
// The glitch free clock mux
wire gfcm_clk;
e203_subsys_gfcm u_e203_subsys_gfcm(
.test_mode(test_mode),
.clk0_rst_n (plloutclk_rst_n),
.clk1_rst_n (hfextclk_rst_n),
.sel1 (pllbypass),
.clk0 (plloutdivclk),// The divided PLL clock
.clk1 (hfextclk),// The original Crystal clock
.clkout (gfcm_clk)
);
assign hfclk = test_mode ? hfextclk : gfcm_clk;
assign inspect_16m_clk = hfextclk ;
assign inspect_pll_clk = plloutclk;
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic 32x32 multiplier ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Generic 32x32 multiplier with pipeline stages. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_gmultp2_32x32.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.2 2002/07/31 02:04:35 lampret
// MAC now follows software convention (signed multiply instead of unsigned).
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.4 2001/12/04 05:02:35 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.3 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
`ifdef OR1200_GENERIC_MULTP2_32X32
`define OR1200_W 32
`define OR1200_WW 64
module or1200_gmultp2_32x32 ( X, Y, CLK, RST, P );
input [`OR1200_W-1:0] X;
input [`OR1200_W-1:0] Y;
input CLK;
input RST;
output [`OR1200_WW-1:0] P;
reg [`OR1200_WW-1:0] p0;
reg [`OR1200_WW-1:0] p1;
integer xi;
integer yi;
//
// Conversion unsigned to signed
//
always @(X)
xi <= X;
//
// Conversion unsigned to signed
//
always @(Y)
yi <= Y;
//
// First multiply stage
//
always @(posedge CLK or posedge RST)
if (RST)
p0 <= `OR1200_WW'b0;
else
p0 <= #1 xi * yi;
//
// Second multiply stage
//
always @(posedge CLK or posedge RST)
if (RST)
p1 <= `OR1200_WW'b0;
else
p1 <= #1 p0;
assign P = p1;
endmodule
`endif
|
(** * Basics: Functional Programming in Coq *)
(* This library definition is included here temporarily
for backward compatibility with Coq 8.3.
Please ignore. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
(* FILL IN HERE *) admit.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb2: (nandb false false) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb3: (nandb false true) = true.
(* FILL IN HERE *) Admitted.
Example test_nandb4: (nandb true true) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
(* FILL IN HERE *) admit.
Example test_andb31: (andb3 true true true) = true.
(* FILL IN HERE *) Admitted.
Example test_andb32: (andb3 false true true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb33: (andb3 true false true) = false.
(* FILL IN HERE *) Admitted.
Example test_andb34: (andb3 true true false) = false.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval simpl in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval simpl in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S m => mult n (factorial m)
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
(andb (ble_nat n m) (negb (beq_nat n m))).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more than [simpl] -- for
example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword keyword [Theorem] instead of
[Example]. Indeed, the latter difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H.
intros H2.
rewrite -> H.
rewrite -> H2.
reflexivity. Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m.
intros H.
rewrite -> plus_1_l.
rewrite -> H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity.
Qed.
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f.
intros H.
intros b.
destruct b.
rewrite H.
rewrite H.
reflexivity.
rewrite H.
rewrite H.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f.
intros H.
intros b.
destruct b.
rewrite H.
rewrite H.
rewrite negb_involutive.
reflexivity.
rewrite H.
rewrite H.
rewrite negb_involutive.
reflexivity.
Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c.
destruct b.
destruct c.
compute.
reflexivity.
compute.
intros H.
rewrite H.
reflexivity.
destruct c.
compute.
intros H.
rewrite H.
reflexivity.
compute.
reflexivity.
Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive bin : Type :=
| B : bin
| E : bin -> bin
| F : bin -> bin.
Fixpoint inc (b : bin) : bin :=
match b with
| B => F B
| E b' => F b'
| F b' => E (inc b')
end.
Fixpoint bin2nat (b : bin) : nat :=
match b with
| B => O
| E b' => (plus (bin2nat b') (bin2nat b'))
| F b' => (plus (plus (bin2nat b') (bin2nat b')) 1)
end.
Fixpoint nat2bin (n : nat) : bin :=
match n with
| O => B
| S n' => (inc (nat2bin n'))
end.
Example test_bin1: (inc (nat2bin 10)) = nat2bin 11.
Proof. reflexivity. Qed.
Example test_bin2: (nat2bin 0) = B.
Proof. compute. reflexivity. Qed.
Example test_bin3: (nat2bin 1) = F B.
Proof. compute. reflexivity. Qed.
Example test_bin4: (nat2bin 2) = E (F B).
Proof. compute. reflexivity. Qed.
Example test_bin5: (nat2bin 5) = F (E (F B)).
Proof. compute. reflexivity. Qed.
Example test_bin6: (bin2nat (nat2bin 10)) = 10.
Proof. compute. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(*
THIS IS NOT THE RIGHT ANSWER
Fixpoint decfunc (n: nat) : nat :=
match n with
| O => O
| _ => match evenb n with
| true => n - 2
| false => n + 1
end
end.
*)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NSR_PP_PG_N_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_NSR_PP_PG_N_TB_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 SET = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 NOTIFIER = 1'b1;
#180 RESET = 1'b1;
#200 SET = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 NOTIFIER = 1'b0;
#300 RESET = 1'b0;
#320 SET = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SET = 1'b1;
#440 RESET = 1'b1;
#460 NOTIFIER = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SET = 1'bx;
#560 RESET = 1'bx;
#580 NOTIFIER = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N dut (.SET(SET), .RESET(RESET), .D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NSR_PP_PG_N_TB_V
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream FIFO with width converter
*/
module axis_fifo_adapter #
(
// FIFO depth in words
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter DEPTH = 4096,
// Width of input AXI stream interface in bits
parameter S_DATA_WIDTH = 8,
// Propagate tkeep signal on input interface
// If disabled, tkeep assumed to be 1'b1
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on input interface
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal on output interface
// If disabled, tkeep assumed to be 1'b1
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle) on output interface
parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of output pipeline registers
parameter PIPELINE_OUTPUT = 2,
// Frame FIFO mode - operate on frames instead of cycles
// When set, m_axis_tvalid will not be deasserted within a frame
// Requires LAST_ENABLE set
parameter FRAME_FIFO = 0,
// tuser value for bad frame marker
parameter USER_BAD_FRAME_VALUE = 1'b1,
// tuser mask for bad frame marker
parameter USER_BAD_FRAME_MASK = 1'b1,
// Drop frames marked bad
// Requires FRAME_FIFO set
parameter DROP_BAD_FRAME = 0,
// Drop incoming frames when full
// When set, s_axis_tready is always asserted
// Requires FRAME_FIFO set
parameter DROP_WHEN_FULL = 0
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [S_DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [M_DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire status_overflow,
output wire status_bad_frame,
output wire status_good_frame
);
// force keep width to 1 when disabled
parameter S_KEEP_WIDTH_INT = S_KEEP_ENABLE ? S_KEEP_WIDTH : 1;
parameter M_KEEP_WIDTH_INT = M_KEEP_ENABLE ? M_KEEP_WIDTH : 1;
// bus word sizes (must be identical)
parameter S_DATA_WORD_SIZE = S_DATA_WIDTH / S_KEEP_WIDTH_INT;
parameter M_DATA_WORD_SIZE = M_DATA_WIDTH / M_KEEP_WIDTH_INT;
// output bus is wider
parameter EXPAND_BUS = M_KEEP_WIDTH_INT > S_KEEP_WIDTH_INT;
// total data and keep widths
parameter DATA_WIDTH = EXPAND_BUS ? M_DATA_WIDTH : S_DATA_WIDTH;
parameter KEEP_WIDTH = EXPAND_BUS ? M_KEEP_WIDTH_INT : S_KEEP_WIDTH_INT;
// bus width assertions
initial begin
if (S_DATA_WORD_SIZE * S_KEEP_WIDTH_INT != S_DATA_WIDTH) begin
$error("Error: input data width not evenly divisble (instance %m)");
$finish;
end
if (M_DATA_WORD_SIZE * M_KEEP_WIDTH_INT != M_DATA_WIDTH) begin
$error("Error: output data width not evenly divisble (instance %m)");
$finish;
end
if (S_DATA_WORD_SIZE != M_DATA_WORD_SIZE) begin
$error("Error: word size mismatch (instance %m)");
$finish;
end
end
wire [DATA_WIDTH-1:0] pre_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] pre_fifo_axis_tkeep;
wire pre_fifo_axis_tvalid;
wire pre_fifo_axis_tready;
wire pre_fifo_axis_tlast;
wire [ID_WIDTH-1:0] pre_fifo_axis_tid;
wire [DEST_WIDTH-1:0] pre_fifo_axis_tdest;
wire [USER_WIDTH-1:0] pre_fifo_axis_tuser;
wire [DATA_WIDTH-1:0] post_fifo_axis_tdata;
wire [KEEP_WIDTH-1:0] post_fifo_axis_tkeep;
wire post_fifo_axis_tvalid;
wire post_fifo_axis_tready;
wire post_fifo_axis_tlast;
wire [ID_WIDTH-1:0] post_fifo_axis_tid;
wire [DEST_WIDTH-1:0] post_fifo_axis_tdest;
wire [USER_WIDTH-1:0] post_fifo_axis_tuser;
generate
if (M_KEEP_WIDTH_INT == S_KEEP_WIDTH_INT) begin
// same width, no adapter needed
assign pre_fifo_axis_tdata = s_axis_tdata;
assign pre_fifo_axis_tkeep = s_axis_tkeep;
assign pre_fifo_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = pre_fifo_axis_tready;
assign pre_fifo_axis_tlast = s_axis_tlast;
assign pre_fifo_axis_tid = s_axis_tid;
assign pre_fifo_axis_tdest = s_axis_tdest;
assign pre_fifo_axis_tuser = s_axis_tuser;
assign m_axis_tdata = post_fifo_axis_tdata;
assign m_axis_tkeep = post_fifo_axis_tkeep;
assign m_axis_tvalid = post_fifo_axis_tvalid;
assign post_fifo_axis_tready = m_axis_tready;
assign m_axis_tlast = post_fifo_axis_tlast;
assign m_axis_tid = post_fifo_axis_tid;
assign m_axis_tdest = post_fifo_axis_tdest;
assign m_axis_tuser = post_fifo_axis_tuser;
end else if (EXPAND_BUS) begin
// output wider, adapt width before FIFO
axis_adapter #(
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(pre_fifo_axis_tdata),
.m_axis_tkeep(pre_fifo_axis_tkeep),
.m_axis_tvalid(pre_fifo_axis_tvalid),
.m_axis_tready(pre_fifo_axis_tready),
.m_axis_tlast(pre_fifo_axis_tlast),
.m_axis_tid(pre_fifo_axis_tid),
.m_axis_tdest(pre_fifo_axis_tdest),
.m_axis_tuser(pre_fifo_axis_tuser)
);
assign m_axis_tdata = post_fifo_axis_tdata;
assign m_axis_tkeep = post_fifo_axis_tkeep;
assign m_axis_tvalid = post_fifo_axis_tvalid;
assign post_fifo_axis_tready = m_axis_tready;
assign m_axis_tlast = post_fifo_axis_tlast;
assign m_axis_tid = post_fifo_axis_tid;
assign m_axis_tdest = post_fifo_axis_tdest;
assign m_axis_tuser = post_fifo_axis_tuser;
end else begin
// input wider, adapt width after FIFO
assign pre_fifo_axis_tdata = s_axis_tdata;
assign pre_fifo_axis_tkeep = s_axis_tkeep;
assign pre_fifo_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = pre_fifo_axis_tready;
assign pre_fifo_axis_tlast = s_axis_tlast;
assign pre_fifo_axis_tid = s_axis_tid;
assign pre_fifo_axis_tdest = s_axis_tdest;
assign pre_fifo_axis_tuser = s_axis_tuser;
axis_adapter #(
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
adapter_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(post_fifo_axis_tdata),
.s_axis_tkeep(post_fifo_axis_tkeep),
.s_axis_tvalid(post_fifo_axis_tvalid),
.s_axis_tready(post_fifo_axis_tready),
.s_axis_tlast(post_fifo_axis_tlast),
.s_axis_tid(post_fifo_axis_tid),
.s_axis_tdest(post_fifo_axis_tdest),
.s_axis_tuser(post_fifo_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
end
endgenerate
axis_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(pre_fifo_axis_tdata),
.s_axis_tkeep(pre_fifo_axis_tkeep),
.s_axis_tvalid(pre_fifo_axis_tvalid),
.s_axis_tready(pre_fifo_axis_tready),
.s_axis_tlast(pre_fifo_axis_tlast),
.s_axis_tid(pre_fifo_axis_tid),
.s_axis_tdest(pre_fifo_axis_tdest),
.s_axis_tuser(pre_fifo_axis_tuser),
// AXI output
.m_axis_tdata(post_fifo_axis_tdata),
.m_axis_tkeep(post_fifo_axis_tkeep),
.m_axis_tvalid(post_fifo_axis_tvalid),
.m_axis_tready(post_fifo_axis_tready),
.m_axis_tlast(post_fifo_axis_tlast),
.m_axis_tid(post_fifo_axis_tid),
.m_axis_tdest(post_fifo_axis_tdest),
.m_axis_tuser(post_fifo_axis_tuser),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_pcie_pipe_pipeline.v
// Version : 1.11
//
// Description: PIPE module for Virtex7 PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PCIEBus_pcie_pipe_pipeline #
(
parameter LINK_CAP_MAX_LINK_WIDTH = 8,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det_i ,
input wire pipe_tx_reset_i ,
input wire pipe_tx_rate_i ,
input wire pipe_tx_deemph_i ,
input wire [2:0] pipe_tx_margin_i ,
input wire pipe_tx_swing_i ,
output wire pipe_tx_rcvr_det_o ,
output wire pipe_tx_reset_o ,
output wire pipe_tx_rate_o ,
output wire pipe_tx_deemph_o ,
output wire [2:0] pipe_tx_margin_o ,
output wire pipe_tx_swing_o ,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k_o ,
output wire [15:0] pipe_rx0_data_o ,
output wire pipe_rx0_valid_o ,
output wire pipe_rx0_chanisaligned_o ,
output wire [ 2:0] pipe_rx0_status_o ,
output wire pipe_rx0_phy_status_o ,
output wire pipe_rx0_elec_idle_o ,
input wire pipe_rx0_polarity_i ,
input wire pipe_tx0_compliance_i ,
input wire [ 1:0] pipe_tx0_char_is_k_i ,
input wire [15:0] pipe_tx0_data_i ,
input wire pipe_tx0_elec_idle_i ,
input wire [ 1:0] pipe_tx0_powerdown_i ,
input wire [ 1:0] pipe_rx0_char_is_k_i ,
input wire [15:0] pipe_rx0_data_i ,
input wire pipe_rx0_valid_i ,
input wire pipe_rx0_chanisaligned_i ,
input wire [ 2:0] pipe_rx0_status_i ,
input wire pipe_rx0_phy_status_i ,
input wire pipe_rx0_elec_idle_i ,
output wire pipe_rx0_polarity_o ,
output wire pipe_tx0_compliance_o ,
output wire [ 1:0] pipe_tx0_char_is_k_o ,
output wire [15:0] pipe_tx0_data_o ,
output wire pipe_tx0_elec_idle_o ,
output wire [ 1:0] pipe_tx0_powerdown_o ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k_o ,
output wire [15:0] pipe_rx1_data_o ,
output wire pipe_rx1_valid_o ,
output wire pipe_rx1_chanisaligned_o ,
output wire [ 2:0] pipe_rx1_status_o ,
output wire pipe_rx1_phy_status_o ,
output wire pipe_rx1_elec_idle_o ,
input wire pipe_rx1_polarity_i ,
input wire pipe_tx1_compliance_i ,
input wire [ 1:0] pipe_tx1_char_is_k_i ,
input wire [15:0] pipe_tx1_data_i ,
input wire pipe_tx1_elec_idle_i ,
input wire [ 1:0] pipe_tx1_powerdown_i ,
input wire [ 1:0] pipe_rx1_char_is_k_i ,
input wire [15:0] pipe_rx1_data_i ,
input wire pipe_rx1_valid_i ,
input wire pipe_rx1_chanisaligned_i ,
input wire [ 2:0] pipe_rx1_status_i ,
input wire pipe_rx1_phy_status_i ,
input wire pipe_rx1_elec_idle_i ,
output wire pipe_rx1_polarity_o ,
output wire pipe_tx1_compliance_o ,
output wire [ 1:0] pipe_tx1_char_is_k_o ,
output wire [15:0] pipe_tx1_data_o ,
output wire pipe_tx1_elec_idle_o ,
output wire [ 1:0] pipe_tx1_powerdown_o ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k_o ,
output wire [15:0] pipe_rx2_data_o ,
output wire pipe_rx2_valid_o ,
output wire pipe_rx2_chanisaligned_o ,
output wire [ 2:0] pipe_rx2_status_o ,
output wire pipe_rx2_phy_status_o ,
output wire pipe_rx2_elec_idle_o ,
input wire pipe_rx2_polarity_i ,
input wire pipe_tx2_compliance_i ,
input wire [ 1:0] pipe_tx2_char_is_k_i ,
input wire [15:0] pipe_tx2_data_i ,
input wire pipe_tx2_elec_idle_i ,
input wire [ 1:0] pipe_tx2_powerdown_i ,
input wire [ 1:0] pipe_rx2_char_is_k_i ,
input wire [15:0] pipe_rx2_data_i ,
input wire pipe_rx2_valid_i ,
input wire pipe_rx2_chanisaligned_i ,
input wire [ 2:0] pipe_rx2_status_i ,
input wire pipe_rx2_phy_status_i ,
input wire pipe_rx2_elec_idle_i ,
output wire pipe_rx2_polarity_o ,
output wire pipe_tx2_compliance_o ,
output wire [ 1:0] pipe_tx2_char_is_k_o ,
output wire [15:0] pipe_tx2_data_o ,
output wire pipe_tx2_elec_idle_o ,
output wire [ 1:0] pipe_tx2_powerdown_o ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k_o ,
output wire [15:0] pipe_rx3_data_o ,
output wire pipe_rx3_valid_o ,
output wire pipe_rx3_chanisaligned_o ,
output wire [ 2:0] pipe_rx3_status_o ,
output wire pipe_rx3_phy_status_o ,
output wire pipe_rx3_elec_idle_o ,
input wire pipe_rx3_polarity_i ,
input wire pipe_tx3_compliance_i ,
input wire [ 1:0] pipe_tx3_char_is_k_i ,
input wire [15:0] pipe_tx3_data_i ,
input wire pipe_tx3_elec_idle_i ,
input wire [ 1:0] pipe_tx3_powerdown_i ,
input wire [ 1:0] pipe_rx3_char_is_k_i ,
input wire [15:0] pipe_rx3_data_i ,
input wire pipe_rx3_valid_i ,
input wire pipe_rx3_chanisaligned_i ,
input wire [ 2:0] pipe_rx3_status_i ,
input wire pipe_rx3_phy_status_i ,
input wire pipe_rx3_elec_idle_i ,
output wire pipe_rx3_polarity_o ,
output wire pipe_tx3_compliance_o ,
output wire [ 1:0] pipe_tx3_char_is_k_o ,
output wire [15:0] pipe_tx3_data_o ,
output wire pipe_tx3_elec_idle_o ,
output wire [ 1:0] pipe_tx3_powerdown_o ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k_o ,
output wire [15:0] pipe_rx4_data_o ,
output wire pipe_rx4_valid_o ,
output wire pipe_rx4_chanisaligned_o ,
output wire [ 2:0] pipe_rx4_status_o ,
output wire pipe_rx4_phy_status_o ,
output wire pipe_rx4_elec_idle_o ,
input wire pipe_rx4_polarity_i ,
input wire pipe_tx4_compliance_i ,
input wire [ 1:0] pipe_tx4_char_is_k_i ,
input wire [15:0] pipe_tx4_data_i ,
input wire pipe_tx4_elec_idle_i ,
input wire [ 1:0] pipe_tx4_powerdown_i ,
input wire [ 1:0] pipe_rx4_char_is_k_i ,
input wire [15:0] pipe_rx4_data_i ,
input wire pipe_rx4_valid_i ,
input wire pipe_rx4_chanisaligned_i ,
input wire [ 2:0] pipe_rx4_status_i ,
input wire pipe_rx4_phy_status_i ,
input wire pipe_rx4_elec_idle_i ,
output wire pipe_rx4_polarity_o ,
output wire pipe_tx4_compliance_o ,
output wire [ 1:0] pipe_tx4_char_is_k_o ,
output wire [15:0] pipe_tx4_data_o ,
output wire pipe_tx4_elec_idle_o ,
output wire [ 1:0] pipe_tx4_powerdown_o ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k_o ,
output wire [15:0] pipe_rx5_data_o ,
output wire pipe_rx5_valid_o ,
output wire pipe_rx5_chanisaligned_o ,
output wire [ 2:0] pipe_rx5_status_o ,
output wire pipe_rx5_phy_status_o ,
output wire pipe_rx5_elec_idle_o ,
input wire pipe_rx5_polarity_i ,
input wire pipe_tx5_compliance_i ,
input wire [ 1:0] pipe_tx5_char_is_k_i ,
input wire [15:0] pipe_tx5_data_i ,
input wire pipe_tx5_elec_idle_i ,
input wire [ 1:0] pipe_tx5_powerdown_i ,
input wire [ 1:0] pipe_rx5_char_is_k_i ,
input wire [15:0] pipe_rx5_data_i ,
input wire pipe_rx5_valid_i ,
input wire pipe_rx5_chanisaligned_i ,
input wire [ 2:0] pipe_rx5_status_i ,
input wire pipe_rx5_phy_status_i ,
input wire pipe_rx5_elec_idle_i ,
output wire pipe_rx5_polarity_o ,
output wire pipe_tx5_compliance_o ,
output wire [ 1:0] pipe_tx5_char_is_k_o ,
output wire [15:0] pipe_tx5_data_o ,
output wire pipe_tx5_elec_idle_o ,
output wire [ 1:0] pipe_tx5_powerdown_o ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k_o ,
output wire [15:0] pipe_rx6_data_o ,
output wire pipe_rx6_valid_o ,
output wire pipe_rx6_chanisaligned_o ,
output wire [ 2:0] pipe_rx6_status_o ,
output wire pipe_rx6_phy_status_o ,
output wire pipe_rx6_elec_idle_o ,
input wire pipe_rx6_polarity_i ,
input wire pipe_tx6_compliance_i ,
input wire [ 1:0] pipe_tx6_char_is_k_i ,
input wire [15:0] pipe_tx6_data_i ,
input wire pipe_tx6_elec_idle_i ,
input wire [ 1:0] pipe_tx6_powerdown_i ,
input wire [ 1:0] pipe_rx6_char_is_k_i ,
input wire [15:0] pipe_rx6_data_i ,
input wire pipe_rx6_valid_i ,
input wire pipe_rx6_chanisaligned_i ,
input wire [ 2:0] pipe_rx6_status_i ,
input wire pipe_rx6_phy_status_i ,
input wire pipe_rx6_elec_idle_i ,
output wire pipe_rx6_polarity_o ,
output wire pipe_tx6_compliance_o ,
output wire [ 1:0] pipe_tx6_char_is_k_o ,
output wire [15:0] pipe_tx6_data_o ,
output wire pipe_tx6_elec_idle_o ,
output wire [ 1:0] pipe_tx6_powerdown_o ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k_o ,
output wire [15:0] pipe_rx7_data_o ,
output wire pipe_rx7_valid_o ,
output wire pipe_rx7_chanisaligned_o ,
output wire [ 2:0] pipe_rx7_status_o ,
output wire pipe_rx7_phy_status_o ,
output wire pipe_rx7_elec_idle_o ,
input wire pipe_rx7_polarity_i ,
input wire pipe_tx7_compliance_i ,
input wire [ 1:0] pipe_tx7_char_is_k_i ,
input wire [15:0] pipe_tx7_data_i ,
input wire pipe_tx7_elec_idle_i ,
input wire [ 1:0] pipe_tx7_powerdown_i ,
input wire [ 1:0] pipe_rx7_char_is_k_i ,
input wire [15:0] pipe_rx7_data_i ,
input wire pipe_rx7_valid_i ,
input wire pipe_rx7_chanisaligned_i ,
input wire [ 2:0] pipe_rx7_status_i ,
input wire pipe_rx7_phy_status_i ,
input wire pipe_rx7_elec_idle_i ,
output wire pipe_rx7_polarity_o ,
output wire pipe_tx7_compliance_o ,
output wire [ 1:0] pipe_tx7_char_is_k_o ,
output wire [15:0] pipe_tx7_data_o ,
output wire pipe_tx7_elec_idle_o ,
output wire [ 1:0] pipe_tx7_powerdown_o ,
// Non PIPE signals
input wire pipe_clk ,
input wire rst_n
);
//******************************************************************//
// Reality check. //
//******************************************************************//
//synthesis translate_off
// initial begin
// $display("[%t] %m LINK_CAP_MAX_LINK_WIDTH %0d PIPE_PIPELINE_STAGES %0d",
// $time, LINK_CAP_MAX_LINK_WIDTH, PIPE_PIPELINE_STAGES);
// end
//synthesis translate_on
generate
PCIEBus_pcie_pipe_misc # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_misc_i (
.pipe_tx_rcvr_det_i(pipe_tx_rcvr_det_i),
.pipe_tx_reset_i(pipe_tx_reset_i),
.pipe_tx_rate_i(pipe_tx_rate_i),
.pipe_tx_deemph_i(pipe_tx_deemph_i),
.pipe_tx_margin_i(pipe_tx_margin_i),
.pipe_tx_swing_i(pipe_tx_swing_i),
.pipe_tx_rcvr_det_o(pipe_tx_rcvr_det_o),
.pipe_tx_reset_o(pipe_tx_reset_o),
.pipe_tx_rate_o(pipe_tx_rate_o),
.pipe_tx_deemph_o(pipe_tx_deemph_o),
.pipe_tx_margin_o(pipe_tx_margin_o),
.pipe_tx_swing_o(pipe_tx_swing_o) ,
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
PCIEBus_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_0_i (
.pipe_rx_char_is_k_o(pipe_rx0_char_is_k_o),
.pipe_rx_data_o(pipe_rx0_data_o),
.pipe_rx_valid_o(pipe_rx0_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx0_chanisaligned_o),
.pipe_rx_status_o(pipe_rx0_status_o),
.pipe_rx_phy_status_o(pipe_rx0_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx0_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx0_polarity_i),
.pipe_tx_compliance_i(pipe_tx0_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx0_char_is_k_i),
.pipe_tx_data_i(pipe_tx0_data_i),
.pipe_tx_elec_idle_i(pipe_tx0_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx0_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx0_char_is_k_i),
.pipe_rx_data_i(pipe_rx0_data_i),
.pipe_rx_valid_i(pipe_rx0_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx0_chanisaligned_i),
.pipe_rx_status_i(pipe_rx0_status_i),
.pipe_rx_phy_status_i(pipe_rx0_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx0_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx0_polarity_o),
.pipe_tx_compliance_o(pipe_tx0_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx0_char_is_k_o),
.pipe_tx_data_o(pipe_tx0_data_o),
.pipe_tx_elec_idle_o(pipe_tx0_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx0_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
if (LINK_CAP_MAX_LINK_WIDTH >= 2) begin : pipe_2_lane
PCIEBus_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_1_i (
.pipe_rx_char_is_k_o(pipe_rx1_char_is_k_o),
.pipe_rx_data_o(pipe_rx1_data_o),
.pipe_rx_valid_o(pipe_rx1_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx1_chanisaligned_o),
.pipe_rx_status_o(pipe_rx1_status_o),
.pipe_rx_phy_status_o(pipe_rx1_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx1_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx1_polarity_i),
.pipe_tx_compliance_i(pipe_tx1_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx1_char_is_k_i),
.pipe_tx_data_i(pipe_tx1_data_i),
.pipe_tx_elec_idle_i(pipe_tx1_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx1_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx1_char_is_k_i),
.pipe_rx_data_i(pipe_rx1_data_i),
.pipe_rx_valid_i(pipe_rx1_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx1_chanisaligned_i),
.pipe_rx_status_i(pipe_rx1_status_i),
.pipe_rx_phy_status_i(pipe_rx1_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx1_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx1_polarity_o),
.pipe_tx_compliance_o(pipe_tx1_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx1_char_is_k_o),
.pipe_tx_data_o(pipe_tx1_data_o),
.pipe_tx_elec_idle_o(pipe_tx1_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx1_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end // if (LINK_CAP_MAX_LINK_WIDTH >= 2)
else
begin
assign pipe_rx1_char_is_k_o = 2'b00;
assign pipe_rx1_data_o = 16'h0000;
assign pipe_rx1_valid_o = 1'b0;
assign pipe_rx1_chanisaligned_o = 1'b0;
assign pipe_rx1_status_o = 3'b000;
assign pipe_rx1_phy_status_o = 1'b0;
assign pipe_rx1_elec_idle_o = 1'b1;
assign pipe_rx1_polarity_o = 1'b0;
assign pipe_tx1_compliance_o = 1'b0;
assign pipe_tx1_char_is_k_o = 2'b00;
assign pipe_tx1_data_o = 16'h0000;
assign pipe_tx1_elec_idle_o = 1'b1;
assign pipe_tx1_powerdown_o = 2'b00;
end // if !(LINK_CAP_MAX_LINK_WIDTH >= 2)
if (LINK_CAP_MAX_LINK_WIDTH >= 4) begin : pipe_4_lane
PCIEBus_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_2_i (
.pipe_rx_char_is_k_o(pipe_rx2_char_is_k_o),
.pipe_rx_data_o(pipe_rx2_data_o),
.pipe_rx_valid_o(pipe_rx2_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx2_chanisaligned_o),
.pipe_rx_status_o(pipe_rx2_status_o),
.pipe_rx_phy_status_o(pipe_rx2_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx2_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx2_polarity_i),
.pipe_tx_compliance_i(pipe_tx2_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx2_char_is_k_i),
.pipe_tx_data_i(pipe_tx2_data_i),
.pipe_tx_elec_idle_i(pipe_tx2_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx2_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx2_char_is_k_i),
.pipe_rx_data_i(pipe_rx2_data_i),
.pipe_rx_valid_i(pipe_rx2_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx2_chanisaligned_i),
.pipe_rx_status_i(pipe_rx2_status_i),
.pipe_rx_phy_status_i(pipe_rx2_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx2_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx2_polarity_o),
.pipe_tx_compliance_o(pipe_tx2_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx2_char_is_k_o),
.pipe_tx_data_o(pipe_tx2_data_o),
.pipe_tx_elec_idle_o(pipe_tx2_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx2_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
PCIEBus_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_3_i (
.pipe_rx_char_is_k_o(pipe_rx3_char_is_k_o),
.pipe_rx_data_o(pipe_rx3_data_o),
.pipe_rx_valid_o(pipe_rx3_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx3_chanisaligned_o),
.pipe_rx_status_o(pipe_rx3_status_o),
.pipe_rx_phy_status_o(pipe_rx3_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx3_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx3_polarity_i),
.pipe_tx_compliance_i(pipe_tx3_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx3_char_is_k_i),
.pipe_tx_data_i(pipe_tx3_data_i),
.pipe_tx_elec_idle_i(pipe_tx3_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx3_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx3_char_is_k_i),
.pipe_rx_data_i(pipe_rx3_data_i),
.pipe_rx_valid_i(pipe_rx3_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx3_chanisaligned_i),
.pipe_rx_status_i(pipe_rx3_status_i),
.pipe_rx_phy_status_i(pipe_rx3_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx3_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx3_polarity_o),
.pipe_tx_compliance_o(pipe_tx3_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx3_char_is_k_o),
.pipe_tx_data_o(pipe_tx3_data_o),
.pipe_tx_elec_idle_o(pipe_tx3_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx3_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end // if (LINK_CAP_MAX_LINK_WIDTH >= 4)
else
begin
assign pipe_rx2_char_is_k_o = 2'b00;
assign pipe_rx2_data_o = 16'h0000;
assign pipe_rx2_valid_o = 1'b0;
assign pipe_rx2_chanisaligned_o = 1'b0;
assign pipe_rx2_status_o = 3'b000;
assign pipe_rx2_phy_status_o = 1'b0;
assign pipe_rx2_elec_idle_o = 1'b1;
assign pipe_rx2_polarity_o = 1'b0;
assign pipe_tx2_compliance_o = 1'b0;
assign pipe_tx2_char_is_k_o = 2'b00;
assign pipe_tx2_data_o = 16'h0000;
assign pipe_tx2_elec_idle_o = 1'b1;
assign pipe_tx2_powerdown_o = 2'b00;
assign pipe_rx3_char_is_k_o = 2'b00;
assign pipe_rx3_data_o = 16'h0000;
assign pipe_rx3_valid_o = 1'b0;
assign pipe_rx3_chanisaligned_o = 1'b0;
assign pipe_rx3_status_o = 3'b000;
assign pipe_rx3_phy_status_o = 1'b0;
assign pipe_rx3_elec_idle_o = 1'b1;
assign pipe_rx3_polarity_o = 1'b0;
assign pipe_tx3_compliance_o = 1'b0;
assign pipe_tx3_char_is_k_o = 2'b00;
assign pipe_tx3_data_o = 16'h0000;
assign pipe_tx3_elec_idle_o = 1'b1;
assign pipe_tx3_powerdown_o = 2'b00;
end // if !(LINK_CAP_MAX_LINK_WIDTH >= 4)
if (LINK_CAP_MAX_LINK_WIDTH >= 8) begin : pipe_8_lane
PCIEBus_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_4_i (
.pipe_rx_char_is_k_o(pipe_rx4_char_is_k_o),
.pipe_rx_data_o(pipe_rx4_data_o),
.pipe_rx_valid_o(pipe_rx4_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx4_chanisaligned_o),
.pipe_rx_status_o(pipe_rx4_status_o),
.pipe_rx_phy_status_o(pipe_rx4_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx4_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx4_polarity_i),
.pipe_tx_compliance_i(pipe_tx4_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx4_char_is_k_i),
.pipe_tx_data_i(pipe_tx4_data_i),
.pipe_tx_elec_idle_i(pipe_tx4_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx4_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx4_char_is_k_i),
.pipe_rx_data_i(pipe_rx4_data_i),
.pipe_rx_valid_i(pipe_rx4_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx4_chanisaligned_i),
.pipe_rx_status_i(pipe_rx4_status_i),
.pipe_rx_phy_status_i(pipe_rx4_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx4_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx4_polarity_o),
.pipe_tx_compliance_o(pipe_tx4_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx4_char_is_k_o),
.pipe_tx_data_o(pipe_tx4_data_o),
.pipe_tx_elec_idle_o(pipe_tx4_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx4_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
PCIEBus_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_5_i (
.pipe_rx_char_is_k_o(pipe_rx5_char_is_k_o),
.pipe_rx_data_o(pipe_rx5_data_o),
.pipe_rx_valid_o(pipe_rx5_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx5_chanisaligned_o),
.pipe_rx_status_o(pipe_rx5_status_o),
.pipe_rx_phy_status_o(pipe_rx5_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx5_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx5_polarity_i),
.pipe_tx_compliance_i(pipe_tx5_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx5_char_is_k_i),
.pipe_tx_data_i(pipe_tx5_data_i),
.pipe_tx_elec_idle_i(pipe_tx5_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx5_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx5_char_is_k_i),
.pipe_rx_data_i(pipe_rx5_data_i),
.pipe_rx_valid_i(pipe_rx5_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx5_chanisaligned_i),
.pipe_rx_status_i(pipe_rx5_status_i),
.pipe_rx_phy_status_i(pipe_rx5_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx5_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx5_polarity_o),
.pipe_tx_compliance_o(pipe_tx5_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx5_char_is_k_o),
.pipe_tx_data_o(pipe_tx5_data_o),
.pipe_tx_elec_idle_o(pipe_tx5_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx5_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
PCIEBus_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_6_i (
.pipe_rx_char_is_k_o(pipe_rx6_char_is_k_o),
.pipe_rx_data_o(pipe_rx6_data_o),
.pipe_rx_valid_o(pipe_rx6_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx6_chanisaligned_o),
.pipe_rx_status_o(pipe_rx6_status_o),
.pipe_rx_phy_status_o(pipe_rx6_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx6_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx6_polarity_i),
.pipe_tx_compliance_i(pipe_tx6_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx6_char_is_k_i),
.pipe_tx_data_i(pipe_tx6_data_i),
.pipe_tx_elec_idle_i(pipe_tx6_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx6_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx6_char_is_k_i),
.pipe_rx_data_i(pipe_rx6_data_i),
.pipe_rx_valid_i(pipe_rx6_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx6_chanisaligned_i),
.pipe_rx_status_i(pipe_rx6_status_i),
.pipe_rx_phy_status_i(pipe_rx6_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx6_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx6_polarity_o),
.pipe_tx_compliance_o(pipe_tx6_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx6_char_is_k_o),
.pipe_tx_data_o(pipe_tx6_data_o),
.pipe_tx_elec_idle_o(pipe_tx6_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx6_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
PCIEBus_pcie_pipe_lane # (
.PIPE_PIPELINE_STAGES(PIPE_PIPELINE_STAGES)
)
pipe_lane_7_i (
.pipe_rx_char_is_k_o(pipe_rx7_char_is_k_o),
.pipe_rx_data_o(pipe_rx7_data_o),
.pipe_rx_valid_o(pipe_rx7_valid_o),
.pipe_rx_chanisaligned_o(pipe_rx7_chanisaligned_o),
.pipe_rx_status_o(pipe_rx7_status_o),
.pipe_rx_phy_status_o(pipe_rx7_phy_status_o),
.pipe_rx_elec_idle_o(pipe_rx7_elec_idle_o),
.pipe_rx_polarity_i(pipe_rx7_polarity_i),
.pipe_tx_compliance_i(pipe_tx7_compliance_i),
.pipe_tx_char_is_k_i(pipe_tx7_char_is_k_i),
.pipe_tx_data_i(pipe_tx7_data_i),
.pipe_tx_elec_idle_i(pipe_tx7_elec_idle_i),
.pipe_tx_powerdown_i(pipe_tx7_powerdown_i),
.pipe_rx_char_is_k_i(pipe_rx7_char_is_k_i),
.pipe_rx_data_i(pipe_rx7_data_i),
.pipe_rx_valid_i(pipe_rx7_valid_i),
.pipe_rx_chanisaligned_i(pipe_rx7_chanisaligned_i),
.pipe_rx_status_i(pipe_rx7_status_i),
.pipe_rx_phy_status_i(pipe_rx7_phy_status_i),
.pipe_rx_elec_idle_i(pipe_rx7_elec_idle_i),
.pipe_rx_polarity_o(pipe_rx7_polarity_o),
.pipe_tx_compliance_o(pipe_tx7_compliance_o),
.pipe_tx_char_is_k_o(pipe_tx7_char_is_k_o),
.pipe_tx_data_o(pipe_tx7_data_o),
.pipe_tx_elec_idle_o(pipe_tx7_elec_idle_o),
.pipe_tx_powerdown_o(pipe_tx7_powerdown_o),
.pipe_clk(pipe_clk),
.rst_n(rst_n)
);
end // if (LINK_CAP_MAX_LINK_WIDTH >= 8)
else
begin
assign pipe_rx4_char_is_k_o = 2'b00;
assign pipe_rx4_data_o = 16'h0000;
assign pipe_rx4_valid_o = 1'b0;
assign pipe_rx4_chanisaligned_o = 1'b0;
assign pipe_rx4_status_o = 3'b000;
assign pipe_rx4_phy_status_o = 1'b0;
assign pipe_rx4_elec_idle_o = 1'b1;
assign pipe_rx4_polarity_o = 1'b0;
assign pipe_tx4_compliance_o = 1'b0;
assign pipe_tx4_char_is_k_o = 2'b00;
assign pipe_tx4_data_o = 16'h0000;
assign pipe_tx4_elec_idle_o = 1'b1;
assign pipe_tx4_powerdown_o = 2'b00;
assign pipe_rx5_char_is_k_o = 2'b00;
assign pipe_rx5_data_o = 16'h0000;
assign pipe_rx5_valid_o = 1'b0;
assign pipe_rx5_chanisaligned_o = 1'b0;
assign pipe_rx5_status_o = 3'b000;
assign pipe_rx5_phy_status_o = 1'b0;
assign pipe_rx5_elec_idle_o = 1'b1;
assign pipe_rx5_polarity_o = 1'b0;
assign pipe_tx5_compliance_o = 1'b0;
assign pipe_tx5_char_is_k_o = 2'b00;
assign pipe_tx5_data_o = 16'h0000;
assign pipe_tx5_elec_idle_o = 1'b1;
assign pipe_tx5_powerdown_o = 2'b00;
assign pipe_rx6_char_is_k_o = 2'b00;
assign pipe_rx6_data_o = 16'h0000;
assign pipe_rx6_valid_o = 1'b0;
assign pipe_rx6_chanisaligned_o = 1'b0;
assign pipe_rx6_status_o = 3'b000;
assign pipe_rx6_phy_status_o = 1'b0;
assign pipe_rx6_elec_idle_o = 1'b1;
assign pipe_rx6_polarity_o = 1'b0;
assign pipe_tx6_compliance_o = 1'b0;
assign pipe_tx6_char_is_k_o = 2'b00;
assign pipe_tx6_data_o = 16'h0000;
assign pipe_tx6_elec_idle_o = 1'b1;
assign pipe_tx6_powerdown_o = 2'b00;
assign pipe_rx7_char_is_k_o = 2'b00;
assign pipe_rx7_data_o = 16'h0000;
assign pipe_rx7_valid_o = 1'b0;
assign pipe_rx7_chanisaligned_o = 1'b0;
assign pipe_rx7_status_o = 3'b000;
assign pipe_rx7_phy_status_o = 1'b0;
assign pipe_rx7_elec_idle_o = 1'b1;
assign pipe_rx7_polarity_o = 1'b0;
assign pipe_tx7_compliance_o = 1'b0;
assign pipe_tx7_char_is_k_o = 2'b00;
assign pipe_tx7_data_o = 16'h0000;
assign pipe_tx7_elec_idle_o = 1'b1;
assign pipe_tx7_powerdown_o = 2'b00;
end // if !(LINK_CAP_MAX_LINK_WIDTH >= 8)
endgenerate
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
// Date : Wed Apr 27 15:28:05 2016
// Host : Dries007Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Github/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/Stack/Stack_sim_netlist.v
// Design : Stack
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "Stack,dist_mem_gen_v8_0_9,{}" *) (* core_generation_info = "Stack,dist_mem_gen_v8_0_9,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dist_mem_gen,x_ipVersion=8.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_ADDR_WIDTH=10,C_DEFAULT_DATA=0,C_DEPTH=1024,C_HAS_CLK=1,C_HAS_D=1,C_HAS_DPO=0,C_HAS_DPRA=0,C_HAS_I_CE=0,C_HAS_QDPO=0,C_HAS_QDPO_CE=0,C_HAS_QDPO_CLK=0,C_HAS_QDPO_RST=0,C_HAS_QDPO_SRST=0,C_HAS_QSPO=0,C_HAS_QSPO_CE=0,C_HAS_QSPO_RST=0,C_HAS_QSPO_SRST=0,C_HAS_SPO=1,C_HAS_WE=1,C_MEM_INIT_FILE=no_coe_file_loaded,C_ELABORATION_DIR=./,C_MEM_TYPE=1,C_PIPELINE_STAGES=0,C_QCE_JOINED=0,C_QUALIFY_WE=0,C_READ_MIF=0,C_REG_A_D_INPUTS=0,C_REG_DPRA_INPUT=0,C_SYNC_ENABLE=1,C_WIDTH=16,C_PARSER_TYPE=1}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "dist_mem_gen_v8_0_9,Vivado 2015.4" *)
(* NotValidForBitStream *)
module Stack
(a,
d,
clk,
we,
spo);
input [9:0]a;
input [15:0]d;
input clk;
input we;
output [15:0]spo;
wire [9:0]a;
wire clk;
wire [15:0]d;
wire [15:0]spo;
wire we;
wire [15:0]NLW_U0_dpo_UNCONNECTED;
wire [15:0]NLW_U0_qdpo_UNCONNECTED;
wire [15:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_CLK = "1" *)
(* C_HAS_D = "1" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *)
(* C_HAS_QDPO = "0" *)
(* C_HAS_QDPO_CE = "0" *)
(* C_HAS_QDPO_CLK = "0" *)
(* C_HAS_QDPO_RST = "0" *)
(* C_HAS_QDPO_SRST = "0" *)
(* C_HAS_WE = "1" *)
(* C_MEM_TYPE = "1" *)
(* C_QCE_JOINED = "0" *)
(* C_REG_DPRA_INPUT = "0" *)
(* c_addr_width = "10" *)
(* c_default_data = "0" *)
(* c_depth = "1024" *)
(* c_elaboration_dir = "./" *)
(* c_has_i_ce = "0" *)
(* c_has_qspo = "0" *)
(* c_has_qspo_ce = "0" *)
(* c_has_qspo_rst = "0" *)
(* c_has_qspo_srst = "0" *)
(* c_has_spo = "1" *)
(* c_mem_init_file = "no_coe_file_loaded" *)
(* c_parser_type = "1" *)
(* c_pipeline_stages = "0" *)
(* c_qualify_we = "0" *)
(* c_read_mif = "0" *)
(* c_reg_a_d_inputs = "0" *)
(* c_sync_enable = "1" *)
(* c_width = "16" *)
Stack_dist_mem_gen_v8_0_9 U0
(.a(a),
.clk(clk),
.d(d),
.dpo(NLW_U0_dpo_UNCONNECTED[15:0]),
.dpra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.i_ce(1'b1),
.qdpo(NLW_U0_qdpo_UNCONNECTED[15:0]),
.qdpo_ce(1'b1),
.qdpo_clk(1'b0),
.qdpo_rst(1'b0),
.qdpo_srst(1'b0),
.qspo(NLW_U0_qspo_UNCONNECTED[15:0]),
.qspo_ce(1'b1),
.qspo_rst(1'b0),
.qspo_srst(1'b0),
.spo(spo),
.we(we));
endmodule
(* C_ADDR_WIDTH = "10" *) (* C_DEFAULT_DATA = "0" *) (* C_DEPTH = "1024" *)
(* C_ELABORATION_DIR = "./" *) (* C_FAMILY = "artix7" *) (* C_HAS_CLK = "1" *)
(* C_HAS_D = "1" *) (* C_HAS_DPO = "0" *) (* C_HAS_DPRA = "0" *)
(* C_HAS_I_CE = "0" *) (* C_HAS_QDPO = "0" *) (* C_HAS_QDPO_CE = "0" *)
(* C_HAS_QDPO_CLK = "0" *) (* C_HAS_QDPO_RST = "0" *) (* C_HAS_QDPO_SRST = "0" *)
(* C_HAS_QSPO = "0" *) (* C_HAS_QSPO_CE = "0" *) (* C_HAS_QSPO_RST = "0" *)
(* C_HAS_QSPO_SRST = "0" *) (* C_HAS_SPO = "1" *) (* C_HAS_WE = "1" *)
(* C_MEM_INIT_FILE = "no_coe_file_loaded" *) (* C_MEM_TYPE = "1" *) (* C_PARSER_TYPE = "1" *)
(* C_PIPELINE_STAGES = "0" *) (* C_QCE_JOINED = "0" *) (* C_QUALIFY_WE = "0" *)
(* C_READ_MIF = "0" *) (* C_REG_A_D_INPUTS = "0" *) (* C_REG_DPRA_INPUT = "0" *)
(* C_SYNC_ENABLE = "1" *) (* C_WIDTH = "16" *) (* ORIG_REF_NAME = "dist_mem_gen_v8_0_9" *)
module Stack_dist_mem_gen_v8_0_9
(a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo);
input [9:0]a;
input [15:0]d;
input [9:0]dpra;
input clk;
input we;
input i_ce;
input qspo_ce;
input qdpo_ce;
input qdpo_clk;
input qspo_rst;
input qdpo_rst;
input qspo_srst;
input qdpo_srst;
output [15:0]spo;
output [15:0]dpo;
output [15:0]qspo;
output [15:0]qdpo;
wire \<const0> ;
wire [9:0]a;
wire clk;
wire [15:0]d;
wire [15:0]spo;
wire we;
assign dpo[15] = \<const0> ;
assign dpo[14] = \<const0> ;
assign dpo[13] = \<const0> ;
assign dpo[12] = \<const0> ;
assign dpo[11] = \<const0> ;
assign dpo[10] = \<const0> ;
assign dpo[9] = \<const0> ;
assign dpo[8] = \<const0> ;
assign dpo[7] = \<const0> ;
assign dpo[6] = \<const0> ;
assign dpo[5] = \<const0> ;
assign dpo[4] = \<const0> ;
assign dpo[3] = \<const0> ;
assign dpo[2] = \<const0> ;
assign dpo[1] = \<const0> ;
assign dpo[0] = \<const0> ;
assign qdpo[15] = \<const0> ;
assign qdpo[14] = \<const0> ;
assign qdpo[13] = \<const0> ;
assign qdpo[12] = \<const0> ;
assign qdpo[11] = \<const0> ;
assign qdpo[10] = \<const0> ;
assign qdpo[9] = \<const0> ;
assign qdpo[8] = \<const0> ;
assign qdpo[7] = \<const0> ;
assign qdpo[6] = \<const0> ;
assign qdpo[5] = \<const0> ;
assign qdpo[4] = \<const0> ;
assign qdpo[3] = \<const0> ;
assign qdpo[2] = \<const0> ;
assign qdpo[1] = \<const0> ;
assign qdpo[0] = \<const0> ;
assign qspo[15] = \<const0> ;
assign qspo[14] = \<const0> ;
assign qspo[13] = \<const0> ;
assign qspo[12] = \<const0> ;
assign qspo[11] = \<const0> ;
assign qspo[10] = \<const0> ;
assign qspo[9] = \<const0> ;
assign qspo[8] = \<const0> ;
assign qspo[7] = \<const0> ;
assign qspo[6] = \<const0> ;
assign qspo[5] = \<const0> ;
assign qspo[4] = \<const0> ;
assign qspo[3] = \<const0> ;
assign qspo[2] = \<const0> ;
assign qspo[1] = \<const0> ;
assign qspo[0] = \<const0> ;
GND GND
(.G(\<const0> ));
Stack_dist_mem_gen_v8_0_9_synth \synth_options.dist_mem_inst
(.a(a),
.clk(clk),
.d(d),
.spo(spo),
.we(we));
endmodule
(* ORIG_REF_NAME = "dist_mem_gen_v8_0_9_synth" *)
module Stack_dist_mem_gen_v8_0_9_synth
(spo,
clk,
d,
a,
we);
output [15:0]spo;
input clk;
input [15:0]d;
input [9:0]a;
input we;
wire [9:0]a;
wire clk;
wire [15:0]d;
wire [15:0]spo;
wire we;
Stack_spram \gen_sp_ram.spram_inst
(.a(a),
.clk(clk),
.d(d),
.spo(spo),
.we(we));
endmodule
(* ORIG_REF_NAME = "spram" *)
module Stack_spram
(spo,
clk,
d,
a,
we);
output [15:0]spo;
input clk;
input [15:0]d;
input [9:0]a;
input we;
wire [9:0]a;
wire clk;
wire [15:0]d;
(* RTL_KEEP = "true" *) wire [15:0]qspo_int;
wire ram_reg_0_255_0_0_i_1_n_0;
wire ram_reg_0_255_0_0_n_0;
wire ram_reg_0_255_10_10_i_1_n_0;
wire ram_reg_0_255_10_10_n_0;
wire ram_reg_0_255_11_11_i_1_n_0;
wire ram_reg_0_255_11_11_n_0;
wire ram_reg_0_255_12_12_i_1_n_0;
wire ram_reg_0_255_12_12_n_0;
wire ram_reg_0_255_13_13_i_1_n_0;
wire ram_reg_0_255_13_13_n_0;
wire ram_reg_0_255_14_14_i_1_n_0;
wire ram_reg_0_255_14_14_n_0;
wire ram_reg_0_255_15_15_i_1_n_0;
wire ram_reg_0_255_15_15_n_0;
wire ram_reg_0_255_1_1_i_1_n_0;
wire ram_reg_0_255_1_1_n_0;
wire ram_reg_0_255_2_2_i_1_n_0;
wire ram_reg_0_255_2_2_n_0;
wire ram_reg_0_255_3_3_i_1_n_0;
wire ram_reg_0_255_3_3_n_0;
wire ram_reg_0_255_4_4_i_1_n_0;
wire ram_reg_0_255_4_4_n_0;
wire ram_reg_0_255_5_5_i_1_n_0;
wire ram_reg_0_255_5_5_n_0;
wire ram_reg_0_255_6_6_i_1_n_0;
wire ram_reg_0_255_6_6_n_0;
wire ram_reg_0_255_7_7_i_1_n_0;
wire ram_reg_0_255_7_7_n_0;
wire ram_reg_0_255_8_8_i_1_n_0;
wire ram_reg_0_255_8_8_n_0;
wire ram_reg_0_255_9_9_i_1_n_0;
wire ram_reg_0_255_9_9_n_0;
wire ram_reg_256_511_0_0_i_1_n_0;
wire ram_reg_256_511_0_0_n_0;
wire ram_reg_256_511_10_10_i_1_n_0;
wire ram_reg_256_511_10_10_n_0;
wire ram_reg_256_511_11_11_i_1_n_0;
wire ram_reg_256_511_11_11_n_0;
wire ram_reg_256_511_12_12_i_1_n_0;
wire ram_reg_256_511_12_12_n_0;
wire ram_reg_256_511_13_13_i_1_n_0;
wire ram_reg_256_511_13_13_n_0;
wire ram_reg_256_511_14_14_i_1_n_0;
wire ram_reg_256_511_14_14_n_0;
wire ram_reg_256_511_15_15_i_1_n_0;
wire ram_reg_256_511_15_15_n_0;
wire ram_reg_256_511_1_1_i_1_n_0;
wire ram_reg_256_511_1_1_n_0;
wire ram_reg_256_511_2_2_i_1_n_0;
wire ram_reg_256_511_2_2_n_0;
wire ram_reg_256_511_3_3_i_1_n_0;
wire ram_reg_256_511_3_3_n_0;
wire ram_reg_256_511_4_4_i_1_n_0;
wire ram_reg_256_511_4_4_n_0;
wire ram_reg_256_511_5_5_i_1_n_0;
wire ram_reg_256_511_5_5_n_0;
wire ram_reg_256_511_6_6_i_1_n_0;
wire ram_reg_256_511_6_6_n_0;
wire ram_reg_256_511_7_7_i_1_n_0;
wire ram_reg_256_511_7_7_n_0;
wire ram_reg_256_511_8_8_i_1_n_0;
wire ram_reg_256_511_8_8_n_0;
wire ram_reg_256_511_9_9_i_1_n_0;
wire ram_reg_256_511_9_9_n_0;
wire ram_reg_512_767_0_0_i_1_n_0;
wire ram_reg_512_767_0_0_n_0;
wire ram_reg_512_767_10_10_i_1_n_0;
wire ram_reg_512_767_10_10_n_0;
wire ram_reg_512_767_11_11_i_1_n_0;
wire ram_reg_512_767_11_11_n_0;
wire ram_reg_512_767_12_12_i_1_n_0;
wire ram_reg_512_767_12_12_n_0;
wire ram_reg_512_767_13_13_i_1_n_0;
wire ram_reg_512_767_13_13_n_0;
wire ram_reg_512_767_14_14_i_1_n_0;
wire ram_reg_512_767_14_14_n_0;
wire ram_reg_512_767_15_15_i_1_n_0;
wire ram_reg_512_767_15_15_n_0;
wire ram_reg_512_767_1_1_i_1_n_0;
wire ram_reg_512_767_1_1_n_0;
wire ram_reg_512_767_2_2_i_1_n_0;
wire ram_reg_512_767_2_2_n_0;
wire ram_reg_512_767_3_3_i_1_n_0;
wire ram_reg_512_767_3_3_n_0;
wire ram_reg_512_767_4_4_i_1_n_0;
wire ram_reg_512_767_4_4_n_0;
wire ram_reg_512_767_5_5_i_1_n_0;
wire ram_reg_512_767_5_5_n_0;
wire ram_reg_512_767_6_6_i_1_n_0;
wire ram_reg_512_767_6_6_n_0;
wire ram_reg_512_767_7_7_i_1_n_0;
wire ram_reg_512_767_7_7_n_0;
wire ram_reg_512_767_8_8_i_1_n_0;
wire ram_reg_512_767_8_8_n_0;
wire ram_reg_512_767_9_9_i_1_n_0;
wire ram_reg_512_767_9_9_n_0;
wire ram_reg_768_1023_0_0_i_1_n_0;
wire ram_reg_768_1023_0_0_n_0;
wire ram_reg_768_1023_10_10_i_1_n_0;
wire ram_reg_768_1023_10_10_n_0;
wire ram_reg_768_1023_11_11_i_1_n_0;
wire ram_reg_768_1023_11_11_n_0;
wire ram_reg_768_1023_12_12_i_1_n_0;
wire ram_reg_768_1023_12_12_n_0;
wire ram_reg_768_1023_13_13_i_1_n_0;
wire ram_reg_768_1023_13_13_n_0;
wire ram_reg_768_1023_14_14_i_1_n_0;
wire ram_reg_768_1023_14_14_n_0;
wire ram_reg_768_1023_15_15_i_1_n_0;
wire ram_reg_768_1023_15_15_n_0;
wire ram_reg_768_1023_1_1_i_1_n_0;
wire ram_reg_768_1023_1_1_n_0;
wire ram_reg_768_1023_2_2_i_1_n_0;
wire ram_reg_768_1023_2_2_n_0;
wire ram_reg_768_1023_3_3_i_1_n_0;
wire ram_reg_768_1023_3_3_n_0;
wire ram_reg_768_1023_4_4_i_1_n_0;
wire ram_reg_768_1023_4_4_n_0;
wire ram_reg_768_1023_5_5_i_1_n_0;
wire ram_reg_768_1023_5_5_n_0;
wire ram_reg_768_1023_6_6_i_1_n_0;
wire ram_reg_768_1023_6_6_n_0;
wire ram_reg_768_1023_7_7_i_1_n_0;
wire ram_reg_768_1023_7_7_n_0;
wire ram_reg_768_1023_8_8_i_1_n_0;
wire ram_reg_768_1023_8_8_n_0;
wire ram_reg_768_1023_9_9_i_1_n_0;
wire ram_reg_768_1023_9_9_n_0;
wire [15:0]spo;
wire we;
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[0]
(.C(clk),
.CE(1'b1),
.D(spo[0]),
.Q(qspo_int[0]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[10]
(.C(clk),
.CE(1'b1),
.D(spo[10]),
.Q(qspo_int[10]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[11]
(.C(clk),
.CE(1'b1),
.D(spo[11]),
.Q(qspo_int[11]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[12]
(.C(clk),
.CE(1'b1),
.D(spo[12]),
.Q(qspo_int[12]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[13]
(.C(clk),
.CE(1'b1),
.D(spo[13]),
.Q(qspo_int[13]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[14]
(.C(clk),
.CE(1'b1),
.D(spo[14]),
.Q(qspo_int[14]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[15]
(.C(clk),
.CE(1'b1),
.D(spo[15]),
.Q(qspo_int[15]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[1]
(.C(clk),
.CE(1'b1),
.D(spo[1]),
.Q(qspo_int[1]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[2]
(.C(clk),
.CE(1'b1),
.D(spo[2]),
.Q(qspo_int[2]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[3]
(.C(clk),
.CE(1'b1),
.D(spo[3]),
.Q(qspo_int[3]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[4]
(.C(clk),
.CE(1'b1),
.D(spo[4]),
.Q(qspo_int[4]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[5]
(.C(clk),
.CE(1'b1),
.D(spo[5]),
.Q(qspo_int[5]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[6]
(.C(clk),
.CE(1'b1),
.D(spo[6]),
.Q(qspo_int[6]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[7]
(.C(clk),
.CE(1'b1),
.D(spo[7]),
.Q(qspo_int[7]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[8]
(.C(clk),
.CE(1'b1),
.D(spo[8]),
.Q(qspo_int[8]),
.R(1'b0));
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\qspo_int_reg[9]
(.C(clk),
.CE(1'b1),
.D(spo[9]),
.Q(qspo_int[9]),
.R(1'b0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_0_0
(.A(a[7:0]),
.D(d[0]),
.O(ram_reg_0_255_0_0_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_0_0_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_0_0_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_0_0_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_10_10
(.A(a[7:0]),
.D(d[10]),
.O(ram_reg_0_255_10_10_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_10_10_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_10_10_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_10_10_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_11_11
(.A(a[7:0]),
.D(d[11]),
.O(ram_reg_0_255_11_11_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_11_11_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_11_11_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_11_11_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_12_12
(.A(a[7:0]),
.D(d[12]),
.O(ram_reg_0_255_12_12_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_12_12_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_12_12_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_12_12_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_13_13
(.A(a[7:0]),
.D(d[13]),
.O(ram_reg_0_255_13_13_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_13_13_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_13_13_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_13_13_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_14_14
(.A(a[7:0]),
.D(d[14]),
.O(ram_reg_0_255_14_14_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_14_14_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_14_14_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_14_14_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_15_15
(.A(a[7:0]),
.D(d[15]),
.O(ram_reg_0_255_15_15_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_15_15_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_15_15_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_15_15_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_1_1
(.A(a[7:0]),
.D(d[1]),
.O(ram_reg_0_255_1_1_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_1_1_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_1_1_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_1_1_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_2_2
(.A(a[7:0]),
.D(d[2]),
.O(ram_reg_0_255_2_2_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_2_2_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_2_2_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_2_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_3_3
(.A(a[7:0]),
.D(d[3]),
.O(ram_reg_0_255_3_3_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_3_3_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_3_3_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_3_3_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_4_4
(.A(a[7:0]),
.D(d[4]),
.O(ram_reg_0_255_4_4_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_4_4_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_4_4_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_4_4_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_5_5
(.A(a[7:0]),
.D(d[5]),
.O(ram_reg_0_255_5_5_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_5_5_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_5_5_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_5_5_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_6_6
(.A(a[7:0]),
.D(d[6]),
.O(ram_reg_0_255_6_6_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_6_6_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_6_6_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_6_6_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_7_7
(.A(a[7:0]),
.D(d[7]),
.O(ram_reg_0_255_7_7_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_7_7_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_7_7_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_7_7_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_8_8
(.A(a[7:0]),
.D(d[8]),
.O(ram_reg_0_255_8_8_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_8_8_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_8_8_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_8_8_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_0_255_9_9
(.A(a[7:0]),
.D(d[9]),
.O(ram_reg_0_255_9_9_n_0),
.WCLK(clk),
.WE(ram_reg_0_255_9_9_i_1_n_0));
LUT3 #(
.INIT(8'h02))
ram_reg_0_255_9_9_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_0_255_9_9_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_0_0
(.A(a[7:0]),
.D(d[0]),
.O(ram_reg_256_511_0_0_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_0_0_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_0_0_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_0_0_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_10_10
(.A(a[7:0]),
.D(d[10]),
.O(ram_reg_256_511_10_10_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_10_10_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_10_10_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_10_10_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_11_11
(.A(a[7:0]),
.D(d[11]),
.O(ram_reg_256_511_11_11_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_11_11_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_11_11_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_11_11_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_12_12
(.A(a[7:0]),
.D(d[12]),
.O(ram_reg_256_511_12_12_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_12_12_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_12_12_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_12_12_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_13_13
(.A(a[7:0]),
.D(d[13]),
.O(ram_reg_256_511_13_13_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_13_13_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_13_13_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_13_13_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_14_14
(.A(a[7:0]),
.D(d[14]),
.O(ram_reg_256_511_14_14_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_14_14_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_14_14_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_14_14_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_15_15
(.A(a[7:0]),
.D(d[15]),
.O(ram_reg_256_511_15_15_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_15_15_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_15_15_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_15_15_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_1_1
(.A(a[7:0]),
.D(d[1]),
.O(ram_reg_256_511_1_1_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_1_1_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_1_1_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_1_1_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_2_2
(.A(a[7:0]),
.D(d[2]),
.O(ram_reg_256_511_2_2_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_2_2_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_2_2_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_2_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_3_3
(.A(a[7:0]),
.D(d[3]),
.O(ram_reg_256_511_3_3_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_3_3_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_3_3_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_3_3_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_4_4
(.A(a[7:0]),
.D(d[4]),
.O(ram_reg_256_511_4_4_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_4_4_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_4_4_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_4_4_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_5_5
(.A(a[7:0]),
.D(d[5]),
.O(ram_reg_256_511_5_5_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_5_5_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_5_5_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_5_5_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_6_6
(.A(a[7:0]),
.D(d[6]),
.O(ram_reg_256_511_6_6_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_6_6_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_6_6_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_6_6_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_7_7
(.A(a[7:0]),
.D(d[7]),
.O(ram_reg_256_511_7_7_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_7_7_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_7_7_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_7_7_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_8_8
(.A(a[7:0]),
.D(d[8]),
.O(ram_reg_256_511_8_8_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_8_8_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_8_8_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_8_8_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_256_511_9_9
(.A(a[7:0]),
.D(d[9]),
.O(ram_reg_256_511_9_9_n_0),
.WCLK(clk),
.WE(ram_reg_256_511_9_9_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_256_511_9_9_i_1
(.I0(a[9]),
.I1(a[8]),
.I2(we),
.O(ram_reg_256_511_9_9_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_0_0
(.A(a[7:0]),
.D(d[0]),
.O(ram_reg_512_767_0_0_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_0_0_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_0_0_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_0_0_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_10_10
(.A(a[7:0]),
.D(d[10]),
.O(ram_reg_512_767_10_10_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_10_10_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_10_10_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_10_10_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_11_11
(.A(a[7:0]),
.D(d[11]),
.O(ram_reg_512_767_11_11_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_11_11_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_11_11_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_11_11_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_12_12
(.A(a[7:0]),
.D(d[12]),
.O(ram_reg_512_767_12_12_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_12_12_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_12_12_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_12_12_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_13_13
(.A(a[7:0]),
.D(d[13]),
.O(ram_reg_512_767_13_13_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_13_13_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_13_13_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_13_13_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_14_14
(.A(a[7:0]),
.D(d[14]),
.O(ram_reg_512_767_14_14_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_14_14_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_14_14_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_14_14_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_15_15
(.A(a[7:0]),
.D(d[15]),
.O(ram_reg_512_767_15_15_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_15_15_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_15_15_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_15_15_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_1_1
(.A(a[7:0]),
.D(d[1]),
.O(ram_reg_512_767_1_1_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_1_1_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_1_1_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_1_1_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_2_2
(.A(a[7:0]),
.D(d[2]),
.O(ram_reg_512_767_2_2_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_2_2_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_2_2_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_2_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_3_3
(.A(a[7:0]),
.D(d[3]),
.O(ram_reg_512_767_3_3_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_3_3_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_3_3_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_3_3_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_4_4
(.A(a[7:0]),
.D(d[4]),
.O(ram_reg_512_767_4_4_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_4_4_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_4_4_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_4_4_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_5_5
(.A(a[7:0]),
.D(d[5]),
.O(ram_reg_512_767_5_5_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_5_5_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_5_5_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_5_5_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_6_6
(.A(a[7:0]),
.D(d[6]),
.O(ram_reg_512_767_6_6_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_6_6_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_6_6_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_6_6_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_7_7
(.A(a[7:0]),
.D(d[7]),
.O(ram_reg_512_767_7_7_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_7_7_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_7_7_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_7_7_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_8_8
(.A(a[7:0]),
.D(d[8]),
.O(ram_reg_512_767_8_8_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_8_8_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_8_8_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_8_8_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_512_767_9_9
(.A(a[7:0]),
.D(d[9]),
.O(ram_reg_512_767_9_9_n_0),
.WCLK(clk),
.WE(ram_reg_512_767_9_9_i_1_n_0));
LUT3 #(
.INIT(8'h40))
ram_reg_512_767_9_9_i_1
(.I0(a[8]),
.I1(a[9]),
.I2(we),
.O(ram_reg_512_767_9_9_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_0_0
(.A(a[7:0]),
.D(d[0]),
.O(ram_reg_768_1023_0_0_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_0_0_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_0_0_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_0_0_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_10_10
(.A(a[7:0]),
.D(d[10]),
.O(ram_reg_768_1023_10_10_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_10_10_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_10_10_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_10_10_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_11_11
(.A(a[7:0]),
.D(d[11]),
.O(ram_reg_768_1023_11_11_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_11_11_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_11_11_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_11_11_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_12_12
(.A(a[7:0]),
.D(d[12]),
.O(ram_reg_768_1023_12_12_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_12_12_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_12_12_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_12_12_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_13_13
(.A(a[7:0]),
.D(d[13]),
.O(ram_reg_768_1023_13_13_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_13_13_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_13_13_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_13_13_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_14_14
(.A(a[7:0]),
.D(d[14]),
.O(ram_reg_768_1023_14_14_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_14_14_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_14_14_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_14_14_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_15_15
(.A(a[7:0]),
.D(d[15]),
.O(ram_reg_768_1023_15_15_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_15_15_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_15_15_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_15_15_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_1_1
(.A(a[7:0]),
.D(d[1]),
.O(ram_reg_768_1023_1_1_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_1_1_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_1_1_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_1_1_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_2_2
(.A(a[7:0]),
.D(d[2]),
.O(ram_reg_768_1023_2_2_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_2_2_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_2_2_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_2_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_3_3
(.A(a[7:0]),
.D(d[3]),
.O(ram_reg_768_1023_3_3_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_3_3_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_3_3_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_3_3_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_4_4
(.A(a[7:0]),
.D(d[4]),
.O(ram_reg_768_1023_4_4_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_4_4_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_4_4_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_4_4_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_5_5
(.A(a[7:0]),
.D(d[5]),
.O(ram_reg_768_1023_5_5_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_5_5_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_5_5_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_5_5_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_6_6
(.A(a[7:0]),
.D(d[6]),
.O(ram_reg_768_1023_6_6_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_6_6_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_6_6_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_6_6_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_7_7
(.A(a[7:0]),
.D(d[7]),
.O(ram_reg_768_1023_7_7_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_7_7_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_7_7_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_7_7_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_8_8
(.A(a[7:0]),
.D(d[8]),
.O(ram_reg_768_1023_8_8_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_8_8_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_8_8_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_8_8_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-5 {cell *THIS*}}" *)
RAM256X1S #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000))
ram_reg_768_1023_9_9
(.A(a[7:0]),
.D(d[9]),
.O(ram_reg_768_1023_9_9_n_0),
.WCLK(clk),
.WE(ram_reg_768_1023_9_9_i_1_n_0));
LUT3 #(
.INIT(8'h80))
ram_reg_768_1023_9_9_i_1
(.I0(we),
.I1(a[8]),
.I2(a[9]),
.O(ram_reg_768_1023_9_9_i_1_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[0]_INST_0
(.I0(ram_reg_768_1023_0_0_n_0),
.I1(ram_reg_512_767_0_0_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_0_0_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_0_0_n_0),
.O(spo[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[10]_INST_0
(.I0(ram_reg_768_1023_10_10_n_0),
.I1(ram_reg_512_767_10_10_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_10_10_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_10_10_n_0),
.O(spo[10]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[11]_INST_0
(.I0(ram_reg_768_1023_11_11_n_0),
.I1(ram_reg_512_767_11_11_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_11_11_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_11_11_n_0),
.O(spo[11]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[12]_INST_0
(.I0(ram_reg_768_1023_12_12_n_0),
.I1(ram_reg_512_767_12_12_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_12_12_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_12_12_n_0),
.O(spo[12]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[13]_INST_0
(.I0(ram_reg_768_1023_13_13_n_0),
.I1(ram_reg_512_767_13_13_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_13_13_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_13_13_n_0),
.O(spo[13]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[14]_INST_0
(.I0(ram_reg_768_1023_14_14_n_0),
.I1(ram_reg_512_767_14_14_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_14_14_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_14_14_n_0),
.O(spo[14]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[15]_INST_0
(.I0(ram_reg_768_1023_15_15_n_0),
.I1(ram_reg_512_767_15_15_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_15_15_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_15_15_n_0),
.O(spo[15]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[1]_INST_0
(.I0(ram_reg_768_1023_1_1_n_0),
.I1(ram_reg_512_767_1_1_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_1_1_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_1_1_n_0),
.O(spo[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[2]_INST_0
(.I0(ram_reg_768_1023_2_2_n_0),
.I1(ram_reg_512_767_2_2_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_2_2_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_2_2_n_0),
.O(spo[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[3]_INST_0
(.I0(ram_reg_768_1023_3_3_n_0),
.I1(ram_reg_512_767_3_3_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_3_3_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_3_3_n_0),
.O(spo[3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[4]_INST_0
(.I0(ram_reg_768_1023_4_4_n_0),
.I1(ram_reg_512_767_4_4_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_4_4_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_4_4_n_0),
.O(spo[4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[5]_INST_0
(.I0(ram_reg_768_1023_5_5_n_0),
.I1(ram_reg_512_767_5_5_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_5_5_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_5_5_n_0),
.O(spo[5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[6]_INST_0
(.I0(ram_reg_768_1023_6_6_n_0),
.I1(ram_reg_512_767_6_6_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_6_6_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_6_6_n_0),
.O(spo[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[7]_INST_0
(.I0(ram_reg_768_1023_7_7_n_0),
.I1(ram_reg_512_767_7_7_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_7_7_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_7_7_n_0),
.O(spo[7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[8]_INST_0
(.I0(ram_reg_768_1023_8_8_n_0),
.I1(ram_reg_512_767_8_8_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_8_8_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_8_8_n_0),
.O(spo[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[9]_INST_0
(.I0(ram_reg_768_1023_9_9_n_0),
.I1(ram_reg_512_767_9_9_n_0),
.I2(a[9]),
.I3(ram_reg_256_511_9_9_n_0),
.I4(a[8]),
.I5(ram_reg_0_255_9_9_n_0),
.O(spo[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// megafunction wizard: %LPM_RAM_DP+%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_128_32x32_be.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 148 04/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module dpram_128_32x32_be (
data,
wren,
wraddress,
rdaddress,
byteena_a,
wrclock,
rdclock,
q);
input [127:0] data;
input wren;
input [3:0] wraddress;
input [5:0] rdaddress;
input [15:0] byteena_a;
input wrclock;
input rdclock;
output [31:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "16"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0]
// Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL rdaddress[5..0]
// Retrieval info: USED_PORT: byteena_a 0 0 16 0 INPUT VCC byteena_a[15..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: CONNECT: @data_a 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
// Retrieval info: CONNECT: @byteena_a 0 0 16 0 byteena_a 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_128_32x32_be_bb.v TRUE
|
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