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// qsys.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module qsys (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
input wire sdram_clock_areset_conduit_export, // sdram_clock_areset_conduit.export
output wire sdram_clock_c0_clk, // sdram_clock_c0.clk
input wire sdram_read_control_fixed_location, // sdram_read_control.fixed_location
input wire [31:0] sdram_read_control_read_base, // .read_base
input wire [31:0] sdram_read_control_read_length, // .read_length
input wire sdram_read_control_go, // .go
output wire sdram_read_control_done, // .done
output wire sdram_read_control_early_done, // .early_done
input wire sdram_read_user_read_buffer, // sdram_read_user.read_buffer
output wire [63:0] sdram_read_user_buffer_output_data, // .buffer_output_data
output wire sdram_read_user_data_available, // .data_available
output wire [12:0] sdram_wire_addr, // sdram_wire.addr
output wire [1:0] sdram_wire_ba, // .ba
output wire sdram_wire_cas_n, // .cas_n
output wire sdram_wire_cke, // .cke
output wire sdram_wire_cs_n, // .cs_n
inout wire [15:0] sdram_wire_dq, // .dq
output wire [1:0] sdram_wire_dqm, // .dqm
output wire sdram_wire_ras_n, // .ras_n
output wire sdram_wire_we_n, // .we_n
input wire sdram_write_control_fixed_location, // sdram_write_control.fixed_location
input wire [31:0] sdram_write_control_write_base, // .write_base
input wire [31:0] sdram_write_control_write_length, // .write_length
input wire sdram_write_control_go, // .go
output wire sdram_write_control_done, // .done
input wire sdram_write_user_write_buffer, // sdram_write_user.write_buffer
input wire [63:0] sdram_write_user_buffer_input_data, // .buffer_input_data
output wire sdram_write_user_buffer_full // .buffer_full
);
wire [63:0] sdram_read_avalon_master_readdata; // mm_interconnect_0:sdram_read_avalon_master_readdata -> sdram_read:master_readdata
wire sdram_read_avalon_master_waitrequest; // mm_interconnect_0:sdram_read_avalon_master_waitrequest -> sdram_read:master_waitrequest
wire [31:0] sdram_read_avalon_master_address; // sdram_read:master_address -> mm_interconnect_0:sdram_read_avalon_master_address
wire sdram_read_avalon_master_read; // sdram_read:master_read -> mm_interconnect_0:sdram_read_avalon_master_read
wire [7:0] sdram_read_avalon_master_byteenable; // sdram_read:master_byteenable -> mm_interconnect_0:sdram_read_avalon_master_byteenable
wire sdram_read_avalon_master_readdatavalid; // mm_interconnect_0:sdram_read_avalon_master_readdatavalid -> sdram_read:master_readdatavalid
wire sdram_write_avalon_master_waitrequest; // mm_interconnect_0:sdram_write_avalon_master_waitrequest -> sdram_write:master_waitrequest
wire [31:0] sdram_write_avalon_master_address; // sdram_write:master_address -> mm_interconnect_0:sdram_write_avalon_master_address
wire [7:0] sdram_write_avalon_master_byteenable; // sdram_write:master_byteenable -> mm_interconnect_0:sdram_write_avalon_master_byteenable
wire sdram_write_avalon_master_write; // sdram_write:master_write -> mm_interconnect_0:sdram_write_avalon_master_write
wire [63:0] sdram_write_avalon_master_writedata; // sdram_write:master_writedata -> mm_interconnect_0:sdram_write_avalon_master_writedata
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs
wire [15:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata
wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest
wire [23:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n
wire [1:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n
wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n
wire [15:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [mm_interconnect_0:sdram_read_clock_reset_reset_reset_bridge_in_reset_reset, sdram:reset_n, sdram_clock:reset, sdram_read:reset, sdram_write:reset]
qsys_sdram sdram (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_wire_addr), // wire.export
.zs_ba (sdram_wire_ba), // .export
.zs_cas_n (sdram_wire_cas_n), // .export
.zs_cke (sdram_wire_cke), // .export
.zs_cs_n (sdram_wire_cs_n), // .export
.zs_dq (sdram_wire_dq), // .export
.zs_dqm (sdram_wire_dqm), // .export
.zs_ras_n (sdram_wire_ras_n), // .export
.zs_we_n (sdram_wire_we_n) // .export
);
qsys_sdram_clock sdram_clock (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_reset_out_reset), // inclk_interface_reset.reset
.read (), // pll_slave.read
.write (), // .write
.address (), // .address
.readdata (), // .readdata
.writedata (), // .writedata
.c0 (sdram_clock_c0_clk), // c0.clk
.areset (sdram_clock_areset_conduit_export), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
custom_master #(
.MASTER_DIRECTION (0),
.DATA_WIDTH (64),
.ADDRESS_WIDTH (32),
.BURST_CAPABLE (0),
.MAXIMUM_BURST_COUNT (2),
.BURST_COUNT_WIDTH (2),
.FIFO_DEPTH (8),
.FIFO_DEPTH_LOG2 (3),
.MEMORY_BASED_FIFO (0)
) sdram_read (
.clk (clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.master_address (sdram_read_avalon_master_address), // avalon_master.address
.master_read (sdram_read_avalon_master_read), // .read
.master_byteenable (sdram_read_avalon_master_byteenable), // .byteenable
.master_readdata (sdram_read_avalon_master_readdata), // .readdata
.master_readdatavalid (sdram_read_avalon_master_readdatavalid), // .readdatavalid
.master_waitrequest (sdram_read_avalon_master_waitrequest), // .waitrequest
.control_fixed_location (sdram_read_control_fixed_location), // control.export
.control_read_base (sdram_read_control_read_base), // .export
.control_read_length (sdram_read_control_read_length), // .export
.control_go (sdram_read_control_go), // .export
.control_done (sdram_read_control_done), // .export
.control_early_done (sdram_read_control_early_done), // .export
.user_read_buffer (sdram_read_user_read_buffer), // user.export
.user_buffer_output_data (sdram_read_user_buffer_output_data), // .export
.user_data_available (sdram_read_user_data_available), // .export
.master_write (), // (terminated)
.master_writedata (), // (terminated)
.master_burstcount (), // (terminated)
.control_write_base (32'b00000000000000000000000000000000), // (terminated)
.control_write_length (32'b00000000000000000000000000000000), // (terminated)
.user_write_buffer (1'b0), // (terminated)
.user_buffer_input_data (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.user_buffer_full () // (terminated)
);
custom_master #(
.MASTER_DIRECTION (1),
.DATA_WIDTH (64),
.ADDRESS_WIDTH (32),
.BURST_CAPABLE (0),
.MAXIMUM_BURST_COUNT (2),
.BURST_COUNT_WIDTH (2),
.FIFO_DEPTH (8),
.FIFO_DEPTH_LOG2 (3),
.MEMORY_BASED_FIFO (0)
) sdram_write (
.clk (clk_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.master_address (sdram_write_avalon_master_address), // avalon_master.address
.master_write (sdram_write_avalon_master_write), // .write
.master_byteenable (sdram_write_avalon_master_byteenable), // .byteenable
.master_writedata (sdram_write_avalon_master_writedata), // .writedata
.master_waitrequest (sdram_write_avalon_master_waitrequest), // .waitrequest
.control_fixed_location (sdram_write_control_fixed_location), // control.export
.control_write_base (sdram_write_control_write_base), // .export
.control_write_length (sdram_write_control_write_length), // .export
.control_go (sdram_write_control_go), // .export
.control_done (sdram_write_control_done), // .export
.user_write_buffer (sdram_write_user_write_buffer), // user.export
.user_buffer_input_data (sdram_write_user_buffer_input_data), // .export
.user_buffer_full (sdram_write_user_buffer_full), // .export
.master_read (), // (terminated)
.master_readdata (64'b0000000000000000000000000000000000000000000000000000000000000000), // (terminated)
.master_readdatavalid (1'b0), // (terminated)
.master_burstcount (), // (terminated)
.control_read_base (32'b00000000000000000000000000000000), // (terminated)
.control_read_length (32'b00000000000000000000000000000000), // (terminated)
.control_early_done (), // (terminated)
.user_read_buffer (1'b0), // (terminated)
.user_buffer_output_data (), // (terminated)
.user_data_available () // (terminated)
);
qsys_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.sdram_read_clock_reset_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // sdram_read_clock_reset_reset_reset_bridge_in_reset.reset
.sdram_read_avalon_master_address (sdram_read_avalon_master_address), // sdram_read_avalon_master.address
.sdram_read_avalon_master_waitrequest (sdram_read_avalon_master_waitrequest), // .waitrequest
.sdram_read_avalon_master_byteenable (sdram_read_avalon_master_byteenable), // .byteenable
.sdram_read_avalon_master_read (sdram_read_avalon_master_read), // .read
.sdram_read_avalon_master_readdata (sdram_read_avalon_master_readdata), // .readdata
.sdram_read_avalon_master_readdatavalid (sdram_read_avalon_master_readdatavalid), // .readdatavalid
.sdram_write_avalon_master_address (sdram_write_avalon_master_address), // sdram_write_avalon_master.address
.sdram_write_avalon_master_waitrequest (sdram_write_avalon_master_waitrequest), // .waitrequest
.sdram_write_avalon_master_byteenable (sdram_write_avalon_master_byteenable), // .byteenable
.sdram_write_avalon_master_write (sdram_write_avalon_master_write), // .write
.sdram_write_avalon_master_writedata (sdram_write_avalon_master_writedata), // .writedata
.sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect) // .chipselect
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
//--------------------------------------------------------------------------------
//-- Filename: CPM.v
//--
//-- Description: Command Process Module(CPM)
//--
//-- The module designed to process read and write command from host.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
`include "CM_HEAD.v"
module CPM (
clk,
rst_n,
en,
//REQ QUEUE WRAPPER
rd_req_data_i,
rd_req_rd_en_o,
rd_req_empty_i,
wr_req_data_i,
wr_req_rd_en_o,
wr_req_empty_i,
//receive cmd fifo
CMGFTL_cmd_fifo_full_i,
CMGFTL_cmd_fifo_almost_full_i,
CMGFTL_cmd_fifo_wr_en_o,
CMGFTL_cmd_fifo_data_o,
//send cmd fifo
FTLCMG_cmd_fifo_empty_i,
FTLCMG_cmd_fifo_almost_empty_i,
FTLCMG_cmd_fifo_rd_en_o,
FTLCMG_cmd_fifo_data_i,
//BAR1 Write Arbiter write port 2
bar1_wr_en2_o,
bar1_addr2_o,
bar1_wr_be2_o,
bar1_wr_d2_o,
bar1_wr_ack2_n_i,
//bar1_wr_exclu2_i,
//bar1_wr_busy2_i,
//BAR1 Write Arbiter write port 3
bar1_wr_en3_o,
bar1_addr3_o,
bar1_wr_be3_o,
bar1_wr_d3_o,
bar1_wr_ack3_n_i,
//bar1_wr_exclu3_i,
//bar1_wr_busy3_i,
bar1_arbiter_busy_i,
bar1_wr_busy_i,
//BAR1
mrd_start_i,
mrd_done_i,
mwr_start_i,
mwr_done_i,
recv_fifo_av_i,
//BAR0 register
req_queue_depth_i,
resp_o,
resp_empty_o,
resp_rd_en_i,
fatal_err_o,
lba_ofr_err_o,
prp_offset_err_o,
id_ob_err_o,
//Interrupt Generator
rd_req_done_o,
wr_req_done_o,
//DMA READ QUEUE
dma_rd_q_wr_en_o,
dma_rd_q_wr_data_o,
dma_rd_q_full_i,
dma_rd_xfer_done_i,
dma_rd_done_entry_i,
dma_rd_xfer_done_ack_o,
/*************ouyang***************/
//response queue interface
response_queue_empty_o,
response_queue_data_o,
response_queue_rd_en_i ,//read enable signal for response queue
/**********************************/
);
parameter WR_REQ_Q_RST = 10'b00_0000_0001;
parameter WR_REQ_Q_FETCH_DW0_3 = 10'b00_0000_0010;
parameter WR_REQ_Q_FETCH_DW4_7 = 10'b00_0000_0100;
parameter WR_REQ_Q_FETCH_DW8_11 = 10'b00_0000_1000;
parameter WR_REQ_Q_FETCH_DW12_15 = 10'b00_0001_0000;
parameter WR_REQ_Q_FETCH_DW16_19 = 10'b00_0010_0000;
parameter WR_REQ_Q_FETCH_DW20_23 = 10'b00_0100_0000;
parameter WR_REQ_Q_FETCH_DW24_27 = 10'b00_1000_0000;
parameter WR_REQ_Q_FETCH_DW28_31 = 10'b01_0000_0000;
parameter WR_REQ_Q_WAIT = 10'b10_0000_0000;
parameter WR_REQ_RST = 4'b0000;
parameter WR_REQ_DECODE = 4'b0001;
parameter WR_REQ_PREPARE = 4'b0010;
parameter WR_REQ_DMA_CONFIG1 = 4'b0011;
parameter WR_REQ_DMA_CONFIG2 = 4'b0100;
parameter WR_REQ_DMA_CONFIG3 = 4'b0101;
parameter WR_REQ_DMA_CONFIG4 = 4'b0110;
parameter WR_REQ_DMA_START = 4'b0111;
parameter WR_REQ_DMA_WAIT = 4'b1000;
parameter WR_REQ_DMA_CLEAR = 4'b1001;
parameter WR_REQ_DMA_CLEAR_ACK = 4'b1010;
parameter WR_REQ_DONE = 4'b1011;
parameter WR_REQ_DONE_RST = 5'b00001;
parameter WR_REQ_DONE_WR_CMD = 5'b00010;
parameter WR_REQ_DONE_WR_CMD_ACK = 5'b00100;
parameter WR_REQ_DONE_WR_RESP = 5'b01000;
parameter WR_REQ_DONE_WR_RESP_ACK = 5'b10000;
parameter RD_REQ_RST = 5'b00000;
parameter RD_REQ_FETCH_DW0_3 = 5'b00001;
parameter RD_REQ_FETCH_DW4_7 = 5'b00010;
parameter RD_REQ_FETCH_DW8_11 = 5'b00011;
parameter RD_REQ_FETCH_DW12_15 = 5'b00100;
parameter RD_REQ_FETCH_DW16_19 = 5'b00101;
parameter RD_REQ_FETCH_DW20_23 = 5'b00110;
parameter RD_REQ_FETCH_DW24_27 = 5'b00111;
parameter RD_REQ_FETCH_DW28_31 = 5'b01000;
parameter RD_REQ_DECODE = 5'b01001;
parameter RD_REQ_GET_ENTRY = 5'b01010;
parameter RD_REQ_GET_ENTRY_ST1 = 5'b01011;
parameter RD_REQ_GET_ENTRY_ST2 = 5'b01100;
parameter RD_REQ_GET_ENTRY_ST3 = 5'b01101;
parameter RD_REQ_GET_ENTRY_ST4 = 5'b01110;
parameter RD_REQ_WRITE_ENTRY = 5'b01111;
parameter RD_REQ_PREPARE = 5'b10000;
parameter RD_REQ_WR_CMD = 5'b10001;
parameter RD_REQ_WR_CMD_ACK = 5'b10010;
parameter RD_REQ_DMA_RST = 4'b0000;
parameter RD_REQ_DMA_FETCH_CMD = 4'b0001;
parameter RD_REQ_DMA_CMD_DECODE = 4'b0010;
parameter RD_REQ_DMA_CONFIG1 = 4'b0011;
parameter RD_REQ_DMA_CONFIG2 = 4'b0100;
parameter RD_REQ_DMA_CONFIG3 = 4'b0101;
parameter RD_REQ_DMA_CONFIG4 = 4'b0110;
parameter RD_REQ_DMA_START = 4'b0111;
parameter RD_REQ_DMA_WAIT = 4'b1000;
parameter RD_REQ_DMA_CLEAR = 4'b1001;
parameter RD_REQ_DMA_CLEAR_ACK = 4'b1010;
parameter RD_REQ_DMA_DONE = 4'b1011;
parameter RD_REQ_DONE_CHECK = 4'b1100;
parameter RD_REQ_WR_RESP = 4'b1101;
parameter RD_REQ_WR_RESP_ACK = 4'b1110;
/*************ouyang***************/
//response queue interface
output response_queue_empty_o;
output [31:0] response_queue_data_o;
input response_queue_rd_en_i ;//read enable signal for response queue
/*********************************/
input clk , rst_n , en;
input [127:0] rd_req_data_i , wr_req_data_i;
output rd_req_rd_en_o , wr_req_rd_en_o;
input rd_req_empty_i , wr_req_empty_i;
input CMGFTL_cmd_fifo_full_i;
input CMGFTL_cmd_fifo_almost_full_i;
output CMGFTL_cmd_fifo_wr_en_o;
output [127:0] CMGFTL_cmd_fifo_data_o;
input FTLCMG_cmd_fifo_empty_i;
input FTLCMG_cmd_fifo_almost_empty_i;
output FTLCMG_cmd_fifo_rd_en_o;
input [127:0] FTLCMG_cmd_fifo_data_i;
output bar1_wr_en2_o;
output [6:0] bar1_addr2_o;
output [3:0] bar1_wr_be2_o;
output [31:0] bar1_wr_d2_o;
input bar1_wr_ack2_n_i;
//input bar1_wr_exclu2_i;
//input bar1_wr_busy2_i;
output bar1_wr_en3_o;
output [6:0] bar1_addr3_o;
output [3:0] bar1_wr_be3_o;
output [31:0] bar1_wr_d3_o;
input bar1_wr_ack3_n_i;
//input bar1_wr_exclu3_i;
//input bar1_wr_busy3_i;
input bar1_arbiter_busy_i;
input bar1_wr_busy_i;
input mrd_start_i , mwr_start_i;
input mrd_done_i , mwr_done_i;
input recv_fifo_av_i;
input [15:0] req_queue_depth_i;
output resp_empty_o;
output [31:0] resp_o;
input resp_rd_en_i;
output fatal_err_o;
output lba_ofr_err_o;
output prp_offset_err_o;
output id_ob_err_o;
output rd_req_done_o;
output wr_req_done_o;
output dma_rd_q_wr_en_o;
output [63:0] dma_rd_q_wr_data_o;
input dma_rd_q_full_i;
input dma_rd_xfer_done_i;
input [63:0] dma_rd_done_entry_i;
output dma_rd_xfer_done_ack_o;
reg rd_req_rd_en_o , wr_req_rd_en_o;
reg CMGFTL_cmd_fifo_wr_en_o;
reg [127:0] CMGFTL_cmd_fifo_data_o;
reg FTLCMG_cmd_fifo_rd_en_o;
reg bar1_wr_en2_o;
reg [6:0] bar1_addr2_o;
reg [3:0] bar1_wr_be2_o;
reg [31:0] bar1_wr_d2_o;
reg bar1_wr_en3_o;
reg [6:0] bar1_addr3_o;
reg [3:0] bar1_wr_be3_o;
reg [31:0] bar1_wr_d3_o;
wire resp_empty_o;
wire [31:0] resp_o;
reg rd_req_done_o;
reg wr_req_done_o;
reg [127:0] wr_req_dw0_3_q , wr_req_dw0_3;
reg [127:0] wr_req_dw4_7_q , wr_req_dw4_7;
reg [127:0] wr_req_dw8_11_q , wr_req_dw8_11;
reg [127:0] wr_req_dw12_15_q , wr_req_dw12_15;
reg [127:0] wr_req_dw16_19_q , wr_req_dw16_19;
reg [127:0] wr_req_dw20_23_q , wr_req_dw20_23;
reg [127:0] wr_req_dw24_27_q , wr_req_dw24_27;
reg [127:0] wr_req_dw28_31_q , wr_req_dw28_31;
reg [127:0] rd_req_dw0_3;
reg [127:0] rd_req_dw4_7;
reg [127:0] rd_req_dw8_11;
reg [127:0] rd_req_dw12_15;
reg [127:0] rd_req_dw16_19;
reg [127:0] rd_req_dw20_23;
reg [127:0] rd_req_dw24_27;
reg [127:0] rd_req_dw28_31;
wire [127:0] rd_req_data_i_sw , wr_req_data_i_sw;
reg wr_req_q_empty;
reg wr_req_empty , wr_req_empty_prev;
//reg rd_req_empty;
reg WrReqFTL_cmd_fifo_wr_en , RdReqFTL_cmd_fifo_wr_en;
reg [127:0] WrReqFTL_cmd_fifo_data , RdReqFTL_cmd_fifo_data;
reg WrReqFTL_cmd_fifo_wr_ack_n , RdReqFTL_cmd_fifo_wr_ack_n;
reg RespQ_wr_en;
reg [31:0] RespQ_wr_data;
wire RespQ_full;
reg WrReq_RespQ_wr_en , RdReq_RespQ_wr_en;
reg [31:0] WrReq_RespQ_wr_data , RdReq_RespQ_wr_data;
reg WrReq_RespQ_wr_ack_n , RdReq_RespQ_wr_ack_n;
`ifdef DEBUG
reg [13:0] resp_tag;
`endif
reg wr_fatal_err;
wire wr_lba_ofr_err = 1'b0;
wire wr_prp_offset_err = 1'b0;
reg wr_id_ob_err;
wire rd_fatal_err;
wire rd_lba_ofr_err;
wire rd_prp_offset_err;
wire rd_id_ob_err;
reg [9:0] wr_req_dma_cnt , rd_req_dma_cnt;
reg [15:0] wr_req_id , rd_req_id;
reg [31:0] wr_req_lba , rd_req_lba;
reg [31:0] wr_req_len , rd_req_len;
reg [31:0] wr_req_prp_pending , rd_req_prp_pending;
reg [31:0] wr_req_lba_pending , rd_req_lba_pending;
reg rd_req_entry_flag [`RD_REQ_BUF_TBSIZE - 1:0];
reg rd_req_done_flag [`RD_REQ_BUF_TBSIZE - 1:0];
reg [15:0] rd_req_entry_id [`RD_REQ_BUF_TBSIZE - 1:0];
reg [31:0] rd_req_total_size [`RD_REQ_BUF_TBSIZE - 1:0];
reg [31:0] rd_req_sent_size [`RD_REQ_BUF_TBSIZE - 1:0];
reg [`RD_REQ_BUF_TBSIZ_ORDER:0] rd_cnt , rd_cnt2;
reg [`RD_REQ_BUF_TBSIZ_ORDER:0] entry_used;
reg [`RD_REQ_BUF_TBSIZ_ORDER - 1:0] free_index;
reg [`RD_REQ_BUF_TBSIZ_ORDER - 1:0] done_index;
reg rd_req_done , rd_req_done_prev;
reg [127:0] rd_req_cmd;
reg [15:0] rd_req_cmd_id;
reg [31:0] rd_req_cmd_prp;
reg dma_rd_q_wr_en_o;
reg [63:0] dma_rd_q_wr_data_o;
reg dma_rd_xfer_done_q;
reg dma_rd_xfer_done_ack_o;
reg [9:0] wr_req_q_state;
reg [3:0] wr_req_state;
reg [4:0] wr_req_done_state;
reg [4:0] rd_req_state;
reg [3:0] rd_req_dma_state;
wire srst = !rst_n | !en;
assign wr_req_data_i_sw = { wr_req_data_i[103:96] , wr_req_data_i[111:104] , wr_req_data_i[119:112] , wr_req_data_i[127:120] ,
wr_req_data_i[71:64] , wr_req_data_i[79:72] , wr_req_data_i[87:80] , wr_req_data_i[95:88] ,
wr_req_data_i[39:32] , wr_req_data_i[47:40] , wr_req_data_i[55:48] , wr_req_data_i[63:56] ,
wr_req_data_i[7:0] , wr_req_data_i[15:8] , wr_req_data_i[23:16] , wr_req_data_i[31:24] };
assign rd_req_data_i_sw = { rd_req_data_i[103:96] , rd_req_data_i[111:104] , rd_req_data_i[119:112] , rd_req_data_i[127:120] ,
rd_req_data_i[71:64] , rd_req_data_i[79:72] , rd_req_data_i[87:80] , rd_req_data_i[95:88] ,
rd_req_data_i[39:32] , rd_req_data_i[47:40] , rd_req_data_i[55:48] , rd_req_data_i[63:56] ,
rd_req_data_i[7:0] , rd_req_data_i[15:8] , rd_req_data_i[23:16] , rd_req_data_i[31:24] };
assign fatal_err_o = wr_fatal_err | rd_fatal_err;
assign lba_ofr_err_o = wr_lba_ofr_err | rd_lba_ofr_err;
assign prp_offset_err_o = wr_prp_offset_err | rd_prp_offset_err;
assign id_ob_err_o = wr_id_ob_err | rd_id_ob_err;
assign wr_req_err = wr_fatal_err | wr_lba_ofr_err | wr_prp_offset_err | wr_id_ob_err;
assign rd_req_err = rd_fatal_err | rd_lba_ofr_err | rd_prp_offset_err | rd_id_ob_err;
// response queue
// DEPTH: 128
// WIDTH: 32
/*
RESPONSE_QUEUE CPM_RESPQ (
.clk( clk ), // input clk
.srst( srst ), // input srst
.din( RespQ_wr_data ), // input [31 : 0] din
.wr_en( RespQ_wr_en ), // input wr_en
.rd_en( resp_rd_en_i ), // input rd_en
.dout( resp_o ), // output [31 : 0] dout
.full( RespQ_full ), // output full
.empty( resp_empty_o ) // output empty
);*/
/***********************ouyang***********************************/
assign resp_o = 0;
assign resp_empty_o = 0;
RESPONSE_QUEUE CPM_RESPQ (
.clk( clk ), // input clk
.srst( srst ), // input srst
.din( RespQ_wr_data ), // input [31 : 0] din
.wr_en( RespQ_wr_en ), // input wr_en
.rd_en( response_queue_rd_en_i ), // input rd_en
.dout( response_queue_data_o ), // output [31 : 0] dout
.full( RespQ_full ), // output full
.empty( response_queue_empty_o ) // output empty
);
/**********************************************************/
//fetch write request from write requset queue to wr_req_dw*_*_q register
//
always @ ( posedge clk ) begin
if( !rst_n | !en ) begin
wr_req_rd_en_o <= 1'b0;
wr_req_q_empty <= 1'b1;
wr_req_dw0_3_q <= 32'b0;
wr_req_dw4_7_q <= 32'b0;
wr_req_dw8_11_q <= 32'b0;
wr_req_dw12_15_q <= 32'b0;
wr_req_dw16_19_q <= 32'b0;
wr_req_dw20_23_q <= 32'b0;
wr_req_dw24_27_q <= 32'b0;
wr_req_dw28_31_q <= 32'b0;
wr_req_q_state <= WR_REQ_Q_RST;
end
else begin
case ( wr_req_q_state )
WR_REQ_Q_RST: begin
if( wr_req_q_empty && !wr_req_empty_i ) begin
wr_req_rd_en_o <= 1'b1;
wr_req_q_state <= WR_REQ_Q_FETCH_DW0_3;
end
end
WR_REQ_Q_FETCH_DW0_3: begin
wr_req_dw0_3_q <= wr_req_data_i_sw;
wr_req_q_state <= WR_REQ_Q_FETCH_DW4_7;
end
WR_REQ_Q_FETCH_DW4_7: begin
wr_req_dw4_7_q <= wr_req_data_i_sw;
wr_req_q_state <= WR_REQ_Q_FETCH_DW8_11;
end
WR_REQ_Q_FETCH_DW8_11: begin
wr_req_dw8_11_q <= wr_req_data_i_sw;
wr_req_q_state <= WR_REQ_Q_FETCH_DW12_15;
end
WR_REQ_Q_FETCH_DW12_15: begin
wr_req_dw12_15_q <= wr_req_data_i_sw;
wr_req_q_state <= WR_REQ_Q_FETCH_DW16_19;
end
WR_REQ_Q_FETCH_DW16_19: begin
wr_req_dw16_19_q <= wr_req_data_i_sw;
wr_req_q_state <= WR_REQ_Q_FETCH_DW20_23;
end
WR_REQ_Q_FETCH_DW20_23: begin
wr_req_dw20_23_q <= wr_req_data_i_sw;
wr_req_q_state <= WR_REQ_Q_FETCH_DW24_27;
end
WR_REQ_Q_FETCH_DW24_27: begin
wr_req_dw24_27_q <= wr_req_data_i_sw;
wr_req_q_state <= WR_REQ_Q_FETCH_DW28_31;
end
WR_REQ_Q_FETCH_DW28_31: begin
wr_req_dw28_31_q <= wr_req_data_i_sw;
wr_req_q_empty <= 1'b0;
wr_req_rd_en_o <= 1'b0;
wr_req_q_state <= WR_REQ_Q_WAIT;
end
WR_REQ_Q_WAIT: begin
if( !wr_req_empty && wr_req_empty_prev ) begin
wr_req_q_empty <= 1'b1;
wr_req_q_state <= WR_REQ_Q_RST;
end
end
default: begin
wr_req_rd_en_o <= 1'b0;
wr_req_q_empty <= 1'b1;
wr_req_q_state <= WR_REQ_Q_RST;
end
endcase
end //if( !rst_n | !en )
end
//write receive cmd fifo arbitration between write request and read request
//
always @ ( * ) begin
if( !rst_n || !en ) begin
CMGFTL_cmd_fifo_wr_en_o = 1'b0;
CMGFTL_cmd_fifo_data_o = 128'b0;
WrReqFTL_cmd_fifo_wr_ack_n = 1'b1;
RdReqFTL_cmd_fifo_wr_ack_n = 1'b1;
end
else begin
if( WrReqFTL_cmd_fifo_wr_en ) begin
CMGFTL_cmd_fifo_wr_en_o = WrReqFTL_cmd_fifo_wr_en;
CMGFTL_cmd_fifo_data_o = WrReqFTL_cmd_fifo_data;
WrReqFTL_cmd_fifo_wr_ack_n = 1'b0;
RdReqFTL_cmd_fifo_wr_ack_n = 1'b1;
end
else if( RdReqFTL_cmd_fifo_wr_en ) begin
CMGFTL_cmd_fifo_wr_en_o = RdReqFTL_cmd_fifo_wr_en;
CMGFTL_cmd_fifo_data_o = RdReqFTL_cmd_fifo_data;
WrReqFTL_cmd_fifo_wr_ack_n = 1'b1;
RdReqFTL_cmd_fifo_wr_ack_n = 1'b0;
end
else begin
CMGFTL_cmd_fifo_wr_en_o = 1'b0;
CMGFTL_cmd_fifo_data_o = 128'b0;
WrReqFTL_cmd_fifo_wr_ack_n = 1'b1;
RdReqFTL_cmd_fifo_wr_ack_n = 1'b1;
end //if( WrReqFTL_cmd_fifo_wr_en )
end //if( !rst_n || !en )
end
`ifdef DEBUG
always @ ( posedge clk ) begin
if( !rst_n || !en ) begin
resp_tag <= 14'b0;
end else begin
if( RespQ_wr_en )
resp_tag <= resp_tag + 1'b1;
end
end
`endif
//write response message arbitration between write request and read request
//
always @ ( * ) begin
if( !rst_n || !en ) begin
RespQ_wr_en = 1'b0;
RespQ_wr_data = 32'b0;
WrReq_RespQ_wr_ack_n = 1'b1;
RdReq_RespQ_wr_ack_n = 1'b1;
end
else begin
if( RdReq_RespQ_wr_en ) begin
RespQ_wr_en = RdReq_RespQ_wr_en;
RespQ_wr_data = RdReq_RespQ_wr_data;
WrReq_RespQ_wr_ack_n = 1'b1;
RdReq_RespQ_wr_ack_n = 1'b0;
end
else if( WrReq_RespQ_wr_en ) begin
RespQ_wr_en = WrReq_RespQ_wr_en;
RespQ_wr_data = WrReq_RespQ_wr_data;
WrReq_RespQ_wr_ack_n = 1'b0;
RdReq_RespQ_wr_ack_n = 1'b1;
end
else begin
RespQ_wr_en = 1'b0;
RespQ_wr_data = 32'b0;
WrReq_RespQ_wr_ack_n = 1'b1;
RdReq_RespQ_wr_ack_n = 1'b1;
end //if( RdReq_RespQ_wr_en )
end //if( !rst_n || !en )
end
//write request error check
//
always @ ( * ) begin
if( !rst_n || !en ) begin
wr_fatal_err = 1'b0;
//wr_lba_ofr_err = 1'b0;
//wr_prp_offset_err = 1'b0;
wr_id_ob_err = 1'b0;
end
else begin
if( !wr_req_empty ) begin
if( wr_req_dw0_3[111:96] >= req_queue_depth_i )
wr_id_ob_err = 1'b1;
else
wr_id_ob_err = 1'b0;
if( ( wr_req_dw0_3[63:32] >> `PAGE_SIZE_ORDER ) > `REQ_PRP_NUMS )
wr_fatal_err = 1'b1;
else
wr_fatal_err = 1'b0;
end
else begin
wr_fatal_err = 1'b0;
//wr_lba_ofr_err = 1'b0;
//wr_prp_offset_err = 1'b0;
wr_id_ob_err = 1'b0;
end
end //if( !rst_n || !en )
end
// this state machine fetch write request and then process
// the request through DMA until the request is finished
//
always @ ( posedge clk ) begin
if( !rst_n || !en ) begin
wr_req_empty <= 1'b1;
wr_req_empty_prev <= 1'b1;
wr_req_dw0_3 <= 128'b0;
wr_req_dw4_7 <= 128'b0;
wr_req_dw8_11 <= 128'b0;
wr_req_dw12_15 <= 128'b0;
wr_req_dw16_19 <= 128'b0;
wr_req_dw20_23 <= 128'b0;
wr_req_dw24_27 <= 128'b0;
wr_req_dw28_31 <= 128'b0;
//WrReqFTL_cmd_fifo_wr_en <= 1'b0;
//WrReqFTL_cmd_fifo_data <= 128'b0;
//WrReq_RespQ_wr_en <= 1'b0;
//WrReq_RespQ_wr_data <= 32'b0;
bar1_wr_en2_o <= 1'b0;
bar1_addr2_o <= 7'b0;
bar1_wr_be2_o <= 4'b0;
bar1_wr_d2_o <= 32'b0;
//wr_req_done_o <= 1'b0;
wr_req_id <= 16'b0;
wr_req_lba <= 32'b0;
wr_req_len <= 32'b0;
wr_req_dma_cnt <= 10'b0;
wr_req_lba_pending <= 32'b0;
wr_req_prp_pending <= 32'b0;
dma_rd_q_wr_en_o <= 1'b0;
dma_rd_q_wr_data_o <= 64'b0;
wr_req_state <= WR_REQ_RST;
end
else begin
wr_req_empty_prev <= wr_req_empty;
dma_rd_q_wr_en_o <= 1'b0;
dma_rd_q_wr_data_o <= 64'b0;
case ( wr_req_state )
WR_REQ_RST: begin
//wr_req_done_o <= 1'b0;
if( !wr_req_q_empty && wr_req_empty ) begin
wr_req_empty <= 1'b0;
wr_req_dw0_3 <= wr_req_dw0_3_q;
wr_req_dw4_7 <= wr_req_dw4_7_q;
wr_req_dw8_11 <= wr_req_dw8_11_q;
wr_req_dw12_15 <= wr_req_dw12_15_q;
wr_req_dw16_19 <= wr_req_dw16_19_q;
wr_req_dw20_23 <= wr_req_dw20_23_q;
wr_req_dw24_27 <= wr_req_dw24_27_q;
wr_req_dw28_31 <= wr_req_dw28_31_q;
wr_req_state <= WR_REQ_DECODE;
end
end
WR_REQ_DECODE: begin
wr_req_id <= wr_req_dw0_3[111:96];
wr_req_lba <= wr_req_dw0_3[95:64];
wr_req_len <= wr_req_dw0_3[63:32];
wr_req_dma_cnt <= 0;
//if( wr_req_err )
// wr_req_state <= WR_REQ_DONE;
//else
wr_req_state <= WR_REQ_PREPARE;
end
WR_REQ_PREPARE: begin
if( wr_req_dma_cnt == 0 )
wr_req_lba_pending <= wr_req_lba;
else
wr_req_lba_pending <= wr_req_lba_pending + 1;
case ( wr_req_dma_cnt[4:2] )
3'b000: begin
case ( wr_req_dma_cnt[1:0] )
2'b00: wr_req_prp_pending <= wr_req_dw8_11[127:96];
2'b01: wr_req_prp_pending <= wr_req_dw8_11[95:64];
2'b10: wr_req_prp_pending <= wr_req_dw8_11[63:32];
2'b11: wr_req_prp_pending <= wr_req_dw8_11[31:0];
endcase
end
3'b001: begin
case ( wr_req_dma_cnt[1:0] )
2'b00: wr_req_prp_pending <= wr_req_dw12_15[127:96];
2'b01: wr_req_prp_pending <= wr_req_dw12_15[95:64];
2'b10: wr_req_prp_pending <= wr_req_dw12_15[63:32];
2'b11: wr_req_prp_pending <= wr_req_dw12_15[31:0];
endcase
end
3'b010: begin
case ( wr_req_dma_cnt[1:0] )
2'b00: wr_req_prp_pending <= wr_req_dw16_19[127:96];
2'b01: wr_req_prp_pending <= wr_req_dw16_19[95:64];
2'b10: wr_req_prp_pending <= wr_req_dw16_19[63:32];
2'b11: wr_req_prp_pending <= wr_req_dw16_19[31:0];
endcase
end
3'b011: begin
case ( wr_req_dma_cnt[1:0] )
2'b00: wr_req_prp_pending <= wr_req_dw20_23[127:96];
2'b01: wr_req_prp_pending <= wr_req_dw20_23[95:64];
2'b10: wr_req_prp_pending <= wr_req_dw20_23[63:32];
2'b11: wr_req_prp_pending <= wr_req_dw20_23[31:0];
endcase
end
3'b100: begin
case ( wr_req_dma_cnt[1:0] )
2'b00: wr_req_prp_pending <= wr_req_dw24_27[127:96];
2'b01: wr_req_prp_pending <= wr_req_dw24_27[95:64];
2'b10: wr_req_prp_pending <= wr_req_dw24_27[63:32];
2'b11: wr_req_prp_pending <= wr_req_dw24_27[31:0];
endcase
end
3'b101: begin
case ( wr_req_dma_cnt[1:0] )
2'b00: wr_req_prp_pending <= wr_req_dw28_31[127:96];
2'b01: wr_req_prp_pending <= wr_req_dw28_31[95:64];
2'b10: wr_req_prp_pending <= wr_req_dw28_31[63:32];
2'b11: wr_req_prp_pending <= wr_req_dw28_31[31:0];
endcase
end
default: wr_req_prp_pending <= 32'b0;
endcase
wr_req_state <= WR_REQ_DMA_CONFIG1;
end
WR_REQ_DMA_CONFIG1: begin
if( !mrd_start_i && !bar1_arbiter_busy_i && recv_fifo_av_i && !bar1_wr_busy_i && !dma_rd_q_full_i ) begin
bar1_wr_en2_o <= 1'b1;
bar1_addr2_o <= `DMA_RD_SIZE_REG;
bar1_wr_be2_o <= 4'b1111;
bar1_wr_d2_o <= `PAGE_SIZE;
wr_req_state <= WR_REQ_DMA_CONFIG2;
end
end
WR_REQ_DMA_CONFIG2: begin
if( !bar1_wr_ack2_n_i ) begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en2_o <= 1'b1;
bar1_addr2_o <= `DMA_RD_ADDR_REG;
bar1_wr_be2_o <= 4'b1111;
bar1_wr_d2_o <= { wr_req_prp_pending[31:2] , 2'b0 };
wr_req_dma_cnt <= wr_req_dma_cnt + 1;
wr_req_state <= WR_REQ_DMA_CONFIG3;
end
end
else begin
bar1_wr_en2_o <= 1'b0;
wr_req_state <= WR_REQ_DMA_CONFIG1;
end //if( !bar1_wr_ack2_n_i )
end
WR_REQ_DMA_CONFIG3: begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en2_o <= 1'b1;
bar1_addr2_o <= `DMA_RD_UPADDR_REG;
bar1_wr_be2_o <= 4'b1111;
if( wr_req_prp_pending[1:0] != 0 )
bar1_wr_d2_o <= { 6'b0 , wr_req_prp_pending[1:0] , 4'b0 , 1'b1 , 19'b0 };
else
bar1_wr_d2_o <= 32'b0;
wr_req_state <= WR_REQ_DMA_CONFIG4;
end
end
WR_REQ_DMA_CONFIG4: begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en2_o <= 1'b1;
bar1_addr2_o <= `DMA_CTRL_STA_REG;
bar1_wr_be2_o <= 4'b1100;
bar1_wr_d2_o <= { 15'b0 , 1'b1 , 16'b0 };
dma_rd_q_wr_en_o <= 1'b1;
if( wr_req_dma_cnt == ( wr_req_len >> `PAGE_SIZE_ORDER ) )
dma_rd_q_wr_data_o <= wr_req_lba_pending | { wr_req_id , 32'b0 } | (3 << 62);
else
dma_rd_q_wr_data_o <= wr_req_lba_pending | (1 << 63);
wr_req_state <= WR_REQ_DMA_START;
end
end
WR_REQ_DMA_START: begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en2_o <= 1'b0;
wr_req_state <= WR_REQ_DMA_WAIT;
end
end
WR_REQ_DMA_WAIT: begin
if( mrd_start_i && mrd_done_i ) begin
wr_req_state <= WR_REQ_DMA_CLEAR;
end
end
WR_REQ_DMA_CLEAR: begin
if( !bar1_arbiter_busy_i ) begin
bar1_wr_en2_o <= 1'b1;
bar1_addr2_o <= `DMA_CTRL_STA_REG;
bar1_wr_be2_o <= 4'b1100;
bar1_wr_d2_o <= 32'b0;
wr_req_state <= WR_REQ_DMA_CLEAR_ACK;
end
end
WR_REQ_DMA_CLEAR_ACK: begin
if( !bar1_wr_ack2_n_i ) begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en2_o <= 1'b0;
wr_req_state <= WR_REQ_DONE;
end
end
else begin
bar1_wr_en2_o <= 1'b0;
wr_req_state <= WR_REQ_DMA_CLEAR;
end //if( !bar1_wr_ack2_n_i )
end
WR_REQ_DONE: begin
if( wr_req_dma_cnt == ( wr_req_len >> `PAGE_SIZE_ORDER ) ) begin
wr_req_empty <= 1'b1;
wr_req_state <= WR_REQ_RST;
end
else
wr_req_state <= WR_REQ_PREPARE;
end
default: begin
wr_req_state <= WR_REQ_RST;
end
endcase
end //if( !rst_n || !en )
end
always @ ( posedge clk ) begin
if( !rst_n || !en ) begin
WrReqFTL_cmd_fifo_wr_en <= 1'b0;
WrReqFTL_cmd_fifo_data <= 128'b0;
WrReq_RespQ_wr_en <= 1'b0;
WrReq_RespQ_wr_data <= 32'b0;
dma_rd_xfer_done_q <= 1'b0;
dma_rd_xfer_done_ack_o <= 1'b0;
wr_req_done_o <= 1'b0;
wr_req_done_state <= WR_REQ_DONE_RST;
end else begin
dma_rd_xfer_done_q <= dma_rd_xfer_done_i;
case(wr_req_done_state)
WR_REQ_DONE_RST: begin
wr_req_done_o <= 1'b0;
if( !dma_rd_xfer_done_q && dma_rd_xfer_done_i ) begin
dma_rd_xfer_done_ack_o <= 1'b1;
wr_req_done_state <= WR_REQ_DONE_WR_CMD;
end
end
WR_REQ_DONE_WR_CMD: begin
if( !CMGFTL_cmd_fifo_full_i && !RdReqFTL_cmd_fifo_wr_en ) begin
WrReqFTL_cmd_fifo_wr_en <= 1'b1;
WrReqFTL_cmd_fifo_data <= { 2'b01 , 94'b0 , dma_rd_done_entry_i[31:0] };
wr_req_done_state <= WR_REQ_DONE_WR_CMD_ACK;
end
end
WR_REQ_DONE_WR_CMD_ACK: begin
WrReqFTL_cmd_fifo_wr_en <= 1'b0;
if( !WrReqFTL_cmd_fifo_wr_ack_n ) begin
if(dma_rd_done_entry_i[62])
wr_req_done_state <= WR_REQ_DONE_WR_RESP;
else begin
dma_rd_xfer_done_ack_o <= 1'b0;
wr_req_done_state <= WR_REQ_DONE_RST;
end
end
else
wr_req_done_state <= WR_REQ_DONE_WR_CMD;
end
WR_REQ_DONE_WR_RESP: begin
if( !RespQ_full && !RdReq_RespQ_wr_en ) begin
WrReq_RespQ_wr_en <= 1'b1;
`ifdef DEBUG
WrReq_RespQ_wr_data <= { 1'b1 , wr_req_err , resp_tag , dma_rd_done_entry_i[47:32] };
`else
WrReq_RespQ_wr_data <= { 1'b1 , wr_req_err , 14'b0 , dma_rd_done_entry_i[47:32] };
`endif
wr_req_done_state <= WR_REQ_DONE_WR_RESP_ACK;
end
end
WR_REQ_DONE_WR_RESP_ACK: begin
WrReq_RespQ_wr_en <= 1'b0;
if( !WrReq_RespQ_wr_ack_n ) begin
wr_req_done_o <= 1'b1;
dma_rd_xfer_done_ack_o <= 1'b0;
wr_req_done_state <= WR_REQ_DONE_RST;
end
else
wr_req_done_state <= WR_REQ_DONE_WR_RESP;
end
default:
wr_req_done_state <= WR_REQ_DONE_RST;
endcase
end
end
// this state machine fetchs requests from read request queue and
// decodes the request then sends corresponded 4K cmd to FTL cmd
// receive fifo.
//
always @ ( posedge clk ) begin
if( !rst_n || !en ) begin
entry_used <= 0;
rd_req_rd_en_o <= 1'b0;
rd_req_dw0_3 <= 128'b0;
rd_req_dw4_7 <= 128'b0;
rd_req_dw8_11 <= 128'b0;
rd_req_dw12_15 <= 128'b0;
rd_req_dw16_19 <= 128'b0;
rd_req_dw20_23 <= 128'b0;
rd_req_dw24_27 <= 128'b0;
rd_req_dw28_31 <= 128'b0;
rd_req_id <= 16'b0;
rd_req_lba <= 32'b0;
rd_req_len <= 32'b0;
rd_req_dma_cnt <= 10'b0;
free_index <= 0;
for( rd_cnt = 0 ; rd_cnt < `RD_REQ_BUF_TBSIZE ; rd_cnt = rd_cnt + 1 ) begin
rd_req_entry_flag[rd_cnt] <= 1'b1;
rd_req_entry_id[rd_cnt] <= 16'b0;
rd_req_total_size[rd_cnt] <= 32'b0;
end
rd_req_lba_pending <= 32'b0;
rd_req_prp_pending <= 32'b0;
RdReqFTL_cmd_fifo_wr_en <= 1'b0;
RdReqFTL_cmd_fifo_data <= 128'b0;
rd_req_state <= RD_REQ_RST;
end
else begin
if( rd_req_done && !rd_req_done_prev ) begin
entry_used <= entry_used - 1'b1;
rd_req_entry_flag[done_index] <= 1'b1;
end
case ( rd_req_state )
RD_REQ_RST: begin
if( !rd_req_empty_i ) begin
rd_req_rd_en_o <= 1'b1;
rd_req_state <= RD_REQ_FETCH_DW0_3;
end
end
RD_REQ_FETCH_DW0_3: begin
rd_req_dw0_3 <= rd_req_data_i_sw;
rd_req_state <= RD_REQ_FETCH_DW4_7;
end
RD_REQ_FETCH_DW4_7: begin
rd_req_dw4_7 <= rd_req_data_i_sw;
rd_req_state <= RD_REQ_FETCH_DW8_11;
end
RD_REQ_FETCH_DW8_11: begin
rd_req_dw8_11 <= rd_req_data_i_sw;
rd_req_state <= RD_REQ_FETCH_DW12_15;
end
RD_REQ_FETCH_DW12_15: begin
rd_req_dw12_15 <= rd_req_data_i_sw;
rd_req_state <= RD_REQ_FETCH_DW16_19;
end
RD_REQ_FETCH_DW16_19: begin
rd_req_dw16_19 <= rd_req_data_i_sw;
rd_req_state <= RD_REQ_FETCH_DW20_23;
end
RD_REQ_FETCH_DW20_23: begin
rd_req_dw20_23 <= rd_req_data_i_sw;
rd_req_state <= RD_REQ_FETCH_DW24_27;
end
RD_REQ_FETCH_DW24_27: begin
rd_req_dw24_27 <= rd_req_data_i_sw;
rd_req_state <= RD_REQ_FETCH_DW28_31;
end
RD_REQ_FETCH_DW28_31: begin
rd_req_dw28_31 <= rd_req_data_i_sw;
rd_req_rd_en_o <= 1'b0;
rd_req_state <= RD_REQ_DECODE;
end
RD_REQ_DECODE: begin
rd_req_id <= rd_req_dw0_3[111:96];
rd_req_lba <= rd_req_dw0_3[95:64];
rd_req_len <= rd_req_dw0_3[63:32];
rd_req_dma_cnt <= 10'b0;
rd_req_state <= RD_REQ_GET_ENTRY;
end
RD_REQ_GET_ENTRY: begin
if( entry_used < `RD_REQ_BUF_TBSIZE ) begin
if( rd_req_entry_flag[0] | rd_req_entry_flag[1] | rd_req_entry_flag[2] | rd_req_entry_flag[3] )
rd_req_state <= RD_REQ_GET_ENTRY_ST1;
else if( rd_req_entry_flag[4] | rd_req_entry_flag[5] | rd_req_entry_flag[6] | rd_req_entry_flag[7] )
rd_req_state <= RD_REQ_GET_ENTRY_ST2;
else if( rd_req_entry_flag[8] | rd_req_entry_flag[9] | rd_req_entry_flag[10] | rd_req_entry_flag[11] )
rd_req_state <= RD_REQ_GET_ENTRY_ST3;
else
rd_req_state <= RD_REQ_GET_ENTRY_ST4;
end
end
RD_REQ_GET_ENTRY_ST1: begin
if( rd_req_entry_flag[0] )
free_index <= 0;
else if( rd_req_entry_flag[1] )
free_index <= 1;
else if( rd_req_entry_flag[2] )
free_index <= 2;
else
free_index <= 3;
rd_req_state <= RD_REQ_WRITE_ENTRY;
end
RD_REQ_GET_ENTRY_ST2: begin
if( rd_req_entry_flag[4] )
free_index <= 4;
else if( rd_req_entry_flag[5] )
free_index <= 5;
else if( rd_req_entry_flag[6] )
free_index <= 6;
else
free_index <= 7;
rd_req_state <= RD_REQ_WRITE_ENTRY;
end
RD_REQ_GET_ENTRY_ST3: begin
if( rd_req_entry_flag[8] )
free_index <= 8;
else if( rd_req_entry_flag[9] )
free_index <= 9;
else if( rd_req_entry_flag[10] )
free_index <= 10;
else
free_index <= 11;
rd_req_state <= RD_REQ_WRITE_ENTRY;
end
RD_REQ_GET_ENTRY_ST4: begin
if( rd_req_entry_flag[12] )
free_index <= 12;
else if( rd_req_entry_flag[13] )
free_index <= 13;
else if( rd_req_entry_flag[14] )
free_index <= 14;
else
free_index <= 15;
rd_req_state <= RD_REQ_WRITE_ENTRY;
end
RD_REQ_WRITE_ENTRY: begin
entry_used <= entry_used + 1'b1;
rd_req_entry_flag[free_index] <= 1'b0;
rd_req_entry_id[free_index] <= rd_req_id;
rd_req_total_size[free_index] <= rd_req_len;
rd_req_state <= RD_REQ_PREPARE;
end
RD_REQ_PREPARE: begin
if( rd_req_dma_cnt == 0 )
rd_req_lba_pending <= rd_req_lba;
else
rd_req_lba_pending <= rd_req_lba_pending + 1;
case ( rd_req_dma_cnt[4:2] )
3'b000: begin
case ( rd_req_dma_cnt[1:0] )
2'b00: rd_req_prp_pending <= rd_req_dw8_11[127:96];
2'b01: rd_req_prp_pending <= rd_req_dw8_11[95:64];
2'b10: rd_req_prp_pending <= rd_req_dw8_11[63:32];
2'b11: rd_req_prp_pending <= rd_req_dw8_11[31:0];
endcase
end
3'b001: begin
case ( rd_req_dma_cnt[1:0] )
2'b00: rd_req_prp_pending <= rd_req_dw12_15[127:96];
2'b01: rd_req_prp_pending <= rd_req_dw12_15[95:64];
2'b10: rd_req_prp_pending <= rd_req_dw12_15[63:32];
2'b11: rd_req_prp_pending <= rd_req_dw12_15[31:0];
endcase
end
3'b010: begin
case ( rd_req_dma_cnt[1:0] )
2'b00: rd_req_prp_pending <= rd_req_dw16_19[127:96];
2'b01: rd_req_prp_pending <= rd_req_dw16_19[95:64];
2'b10: rd_req_prp_pending <= rd_req_dw16_19[63:32];
2'b11: rd_req_prp_pending <= rd_req_dw16_19[31:0];
endcase
end
3'b011: begin
case ( rd_req_dma_cnt[1:0] )
2'b00: rd_req_prp_pending <= rd_req_dw20_23[127:96];
2'b01: rd_req_prp_pending <= rd_req_dw20_23[95:64];
2'b10: rd_req_prp_pending <= rd_req_dw20_23[63:32];
2'b11: rd_req_prp_pending <= rd_req_dw20_23[31:0];
endcase
end
3'b100: begin
case ( rd_req_dma_cnt[1:0] )
2'b00: rd_req_prp_pending <= rd_req_dw24_27[127:96];
2'b01: rd_req_prp_pending <= rd_req_dw24_27[95:64];
2'b10: rd_req_prp_pending <= rd_req_dw24_27[63:32];
2'b11: rd_req_prp_pending <= rd_req_dw24_27[31:0];
endcase
end
3'b101: begin
case ( rd_req_dma_cnt[1:0] )
2'b00: rd_req_prp_pending <= rd_req_dw28_31[127:96];
2'b01: rd_req_prp_pending <= rd_req_dw28_31[95:64];
2'b10: rd_req_prp_pending <= rd_req_dw28_31[63:32];
2'b11: rd_req_prp_pending <= rd_req_dw28_31[31:0];
endcase
end
default: rd_req_prp_pending <= 32'b0;
endcase
rd_req_state <= RD_REQ_WR_CMD;
end
RD_REQ_WR_CMD: begin
if( !CMGFTL_cmd_fifo_full_i && !WrReqFTL_cmd_fifo_wr_en ) begin
RdReqFTL_cmd_fifo_wr_en <= 1'b1;
//CMD format negotiated with FTL
RdReqFTL_cmd_fifo_data <= { 2'b00 , 5'b0 , rd_req_prp_pending , 25'b0 , rd_req_id[12:0] , 19'b0 , rd_req_lba_pending };
rd_req_state <= RD_REQ_WR_CMD_ACK;
end
end
RD_REQ_WR_CMD_ACK: begin
RdReqFTL_cmd_fifo_wr_en <= 1'b0;
if( !RdReqFTL_cmd_fifo_wr_ack_n ) begin
rd_req_dma_cnt <= rd_req_dma_cnt + 1;
if( rd_req_dma_cnt + 1 == ( rd_req_len >> `PAGE_SIZE_ORDER ) )
rd_req_state <= RD_REQ_RST;
else
rd_req_state <= RD_REQ_PREPARE;
end
else
rd_req_state <= RD_REQ_WR_CMD;
end
default:
rd_req_state <= RD_REQ_RST;
endcase
end
end
// this state machine fetch 4KB DMA write cmd from send cmd fifo
// and start DMA transfer.
always @ ( posedge clk ) begin
if( !rst_n || !en ) begin
rd_req_done_prev <= 1'b0;
rd_req_done <= 1'b0;
rd_req_done_o <= 1'b0;
FTLCMG_cmd_fifo_rd_en_o <= 1'b0;
rd_req_cmd <= 128'b0;
rd_req_cmd_id <= 16'b0;
rd_req_cmd_prp <= 32'b0;
bar1_wr_en3_o <= 1'b0;
bar1_addr3_o <= 7'b0;
bar1_wr_be3_o <= 4'b0;
bar1_wr_d3_o <= 32'b0;
for( rd_cnt2 = 0 ; rd_cnt2 < `RD_REQ_BUF_TBSIZE ; rd_cnt2 = rd_cnt2 + 1 ) begin
rd_req_sent_size[rd_cnt2] <= 32'b0;
rd_req_done_flag[rd_cnt2] <= 1'b0;
end
done_index <= 0;
RdReq_RespQ_wr_en <= 1'b0;
RdReq_RespQ_wr_data <= 32'b0;
rd_req_dma_state <= RD_REQ_DMA_RST;
end
else begin
rd_req_done_prev <= rd_req_done;
case ( rd_req_dma_state )
RD_REQ_DMA_RST: begin
rd_req_done_o <= 1'b0;
rd_req_done <= 1'b0;
if( !FTLCMG_cmd_fifo_empty_i ) begin
FTLCMG_cmd_fifo_rd_en_o <= 1'b1;
rd_req_dma_state <= RD_REQ_DMA_FETCH_CMD;
end
end
RD_REQ_DMA_FETCH_CMD: begin
FTLCMG_cmd_fifo_rd_en_o <= 1'b0;
rd_req_cmd <= FTLCMG_cmd_fifo_data_i;
rd_req_dma_state <= RD_REQ_DMA_CMD_DECODE;
end
RD_REQ_DMA_CMD_DECODE: begin
rd_req_cmd_id <= rd_req_cmd[63:51];
rd_req_cmd_prp <= rd_req_cmd[120:89];
rd_req_dma_state <= RD_REQ_DMA_CONFIG1;
end
RD_REQ_DMA_CONFIG1: begin
if( !mwr_start_i && !bar1_arbiter_busy_i ) begin
bar1_wr_en3_o <= 1'b1;
bar1_addr3_o <= `DMA_WR_SIZE_REG;
bar1_wr_be3_o <= 4'b1111;
bar1_wr_d3_o <= `PAGE_SIZE;
rd_req_dma_state <= RD_REQ_DMA_CONFIG2;
end
end
RD_REQ_DMA_CONFIG2: begin
if( !bar1_wr_ack3_n_i ) begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en3_o <= 1'b1;
bar1_addr3_o <= `DMA_WR_ADDR_REG;
bar1_wr_be3_o <= 4'b1111;
bar1_wr_d3_o <= { rd_req_cmd_prp[31:2] , 2'b0 };
rd_req_dma_state <= RD_REQ_DMA_CONFIG3;
end
end
else begin
bar1_wr_en3_o <= 1'b0;
rd_req_dma_state <= RD_REQ_DMA_CONFIG1;
end //if( !bar1_wr_ack3_n_i )
end
RD_REQ_DMA_CONFIG3: begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en3_o <= 1'b1;
bar1_addr3_o <= `DMA_WR_UPADDR_REG;
bar1_wr_be3_o <= 4'b1111;
if( rd_req_cmd_prp[1:0] != 0 )
bar1_wr_d3_o <= { 6'b0 , rd_req_cmd_prp[1:0] , 4'b0 , 1'b1 , 19'b0 };
else
bar1_wr_d3_o <= 32'b0;
rd_req_dma_state <= RD_REQ_DMA_CONFIG4;
end
end
RD_REQ_DMA_CONFIG4: begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en3_o <= 1'b1;
bar1_addr3_o <= `DMA_CTRL_STA_REG;
bar1_wr_be3_o <= 4'b0011;
bar1_wr_d3_o <= { 16'b0 , 15'b0 , 1'b1 };
rd_req_dma_state <= RD_REQ_DMA_START;
end
end
RD_REQ_DMA_START: begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en3_o <= 1'b0;
rd_req_dma_state <= RD_REQ_DMA_WAIT;
end
end
RD_REQ_DMA_WAIT: begin
if( mwr_start_i && mwr_done_i ) begin
rd_req_dma_state <= RD_REQ_DMA_CLEAR;
end
end
RD_REQ_DMA_CLEAR: begin
if( !bar1_arbiter_busy_i ) begin
bar1_wr_en3_o <= 1'b1;
bar1_addr3_o <= `DMA_CTRL_STA_REG;
bar1_wr_be3_o <= 4'b0011;
bar1_wr_d3_o <= 32'b0;
rd_req_dma_state <= RD_REQ_DMA_CLEAR_ACK;
end
end
RD_REQ_DMA_CLEAR_ACK: begin
if( !bar1_wr_ack3_n_i ) begin
if( !bar1_wr_busy_i ) begin
bar1_wr_en3_o <= 1'b0;
rd_req_dma_state <= RD_REQ_DMA_DONE;
end
end
else begin
bar1_wr_en3_o <= 1'b0;
rd_req_dma_state <= RD_REQ_DMA_CLEAR;
end //if( !bar1_wr_ack3_n_i )
end
RD_REQ_DMA_DONE: begin
//rd_req_dma_state <= RD_REQ_DMA_RST;
for( rd_cnt2 = 0 ; rd_cnt2 < `RD_REQ_BUF_TBSIZE ; rd_cnt2 = rd_cnt2 + 1 ) begin
if( !rd_req_entry_flag[rd_cnt2] && (rd_req_cmd_id == rd_req_entry_id[rd_cnt2]) ) begin
//done_index <= rd_cnt2;
if( rd_req_sent_size[rd_cnt2] + `PAGE_SIZE == rd_req_total_size[rd_cnt2] ) begin
//rd_req_done <= 1'b1;
rd_req_sent_size[rd_cnt2] <= 32'b0;
rd_req_done_flag[rd_cnt2] <= 1'b1;
//rd_req_dma_state <= RD_REQ_WR_RESP;
end else begin
rd_req_sent_size[rd_cnt2] <= rd_req_sent_size[rd_cnt2] + `PAGE_SIZE;
//rd_req_dma_state <= RD_REQ_DMA_RST;
end
end
end
rd_req_dma_state <= RD_REQ_DONE_CHECK;
end
RD_REQ_DONE_CHECK: begin
/*
rd_req_dma_state <= RD_REQ_DMA_RST;
if( rd_req_sent_size[done_index] == rd_req_total_size[done_index] ) begin
rd_req_done <= 1'b1;
rd_req_sent_size[done_index] <= 32'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
if( rd_req_done_flag[15] | rd_req_done_flag[15] | rd_req_done_flag[15] | rd_req_done_flag[15]
| rd_req_done_flag[15] | rd_req_done_flag[15] | rd_req_done_flag[15] | rd_req_done_flag[15]
| rd_req_done_flag[15] | rd_req_done_flag[15] | rd_req_done_flag[15] | rd_req_done_flag[15]
| rd_req_done_flag[15] | rd_req_done_flag[15] | rd_req_done_flag[15] | rd_req_done_flag[15]
) begin
rd_req_done <= 1'b1;
rd_req_done_flag <= 0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end else
rd_req_dma_state <= RD_REQ_DMA_RST;
*/
case({ rd_req_done_flag[15] , rd_req_done_flag[14] , rd_req_done_flag[13] , rd_req_done_flag[12]
, rd_req_done_flag[11] , rd_req_done_flag[10] , rd_req_done_flag[9] , rd_req_done_flag[8]
, rd_req_done_flag[7] , rd_req_done_flag[6] , rd_req_done_flag[5] , rd_req_done_flag[4]
, rd_req_done_flag[3] , rd_req_done_flag[2] , rd_req_done_flag[1] , rd_req_done_flag[0]
})
16'b0000_0000_0000_0001: begin
done_index <= 0;
rd_req_done <= 1'b1;
rd_req_done_flag[0] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0000_0000_0010: begin
done_index <= 1;
rd_req_done <= 1'b1;
rd_req_done_flag[1] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0000_0000_0100: begin
done_index <= 2;
rd_req_done <= 1'b1;
rd_req_done_flag[2] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0000_0000_1000: begin
done_index <= 3;
rd_req_done <= 1'b1;
rd_req_done_flag[3] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0000_0001_0000: begin
done_index <= 4;
rd_req_done <= 1'b1;
rd_req_done_flag[4] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0000_0010_0000: begin
done_index <= 5;
rd_req_done <= 1'b1;
rd_req_done_flag[5] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0000_0100_0000: begin
done_index <= 6;
rd_req_done <= 1'b1;
rd_req_done_flag[6] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0000_1000_0000: begin
done_index <= 7;
rd_req_done <= 1'b1;
rd_req_done_flag[7] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0001_0000_0000: begin
done_index <= 8;
rd_req_done <= 1'b1;
rd_req_done_flag[8] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0010_0000_0000: begin
done_index <= 9;
rd_req_done <= 1'b1;
rd_req_done_flag[9] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_0100_0000_0000: begin
done_index <= 10;
rd_req_done <= 1'b1;
rd_req_done_flag[10] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0000_1000_0000_0000: begin
done_index <= 11;
rd_req_done <= 1'b1;
rd_req_done_flag[11] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0001_0000_0000_0000: begin
done_index <= 12;
rd_req_done <= 1'b1;
rd_req_done_flag[12] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0010_0000_0000_0000: begin
done_index <= 13;
rd_req_done <= 1'b1;
rd_req_done_flag[13] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b0100_0000_0000_0000: begin
done_index <= 14;
rd_req_done <= 1'b1;
rd_req_done_flag[14] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
16'b1000_0000_0000_0000: begin
done_index <= 15;
rd_req_done <= 1'b1;
rd_req_done_flag[15] <= 1'b0;
rd_req_dma_state <= RD_REQ_WR_RESP;
end
default: begin
//done_index <= 0;
//rd_req_done <= 1'b0;
//rd_req_done_flag[0] <= 1'b0;
rd_req_dma_state <= RD_REQ_DMA_RST;
end
endcase
end
RD_REQ_WR_RESP: begin
if( !RespQ_full && !WrReq_RespQ_wr_en ) begin
RdReq_RespQ_wr_en <= 1'b1;
`ifdef DEBUG
RdReq_RespQ_wr_data <= { 1'b1 , 1'b0/*rd_req_err*/ , resp_tag, rd_req_cmd_id };
`else
RdReq_RespQ_wr_data <= { 1'b1 , 1'b0/*rd_req_err*/ , 14'b0 , rd_req_cmd_id };
`endif
rd_req_dma_state <= RD_REQ_WR_RESP_ACK;
end
end
RD_REQ_WR_RESP_ACK: begin
RdReq_RespQ_wr_en <= 1'b0;
if( !RdReq_RespQ_wr_ack_n ) begin
rd_req_done_o <= 1'b1;
rd_req_dma_state <= RD_REQ_DMA_RST;
end
else
rd_req_dma_state <= RD_REQ_WR_RESP;
end
default: begin
rd_req_dma_state <= RD_REQ_DMA_RST;
end
endcase
end
end
endmodule
|
//-----------------------------------------------------------------------------
// Title : 10/100/1G Ethernet FIFO for 8-bit Client Interface
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : eth_fifo_8.v
// Version : 1.3
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//------------------------------------------------------------------------
// Description: This is the top-level wrapper for the 10/100/1G Ethernet
// FIFO. The top level wrapper consists of individual FIFOs
// on the transmitter path and on the receiver path.
//
// Each path consists of an 8-bit LocalLink-to-8-bit
// client-interface FIFO.
//------------------------------------------------------------------------
`timescale 1ps / 1ps
module eth_fifo_8 (
// Transmit FIFO MAC TX Interface
tx_clk, // MAC transmit clock
tx_reset, // Synchronous reset (tx_clk)
tx_enable, // Clock enable for tx_clk
tx_data, // Data to MAC transmitter
tx_data_valid, // Valid signal to MAC transmitter
tx_ack, // Ack signal from MAC transmitter
tx_underrun, // Underrun signal to MAC transmitter
tx_collision, // Collsion signal from MAC transmitter
tx_retransmit, // Retransmit signal from MAC transmitter
// Transmit FIFO LocalLink Interface
tx_ll_clock, // Local link write clock
tx_ll_reset, // synchronous reset (tx_ll_clock)
tx_ll_data_in, // Data to Tx FIFO
tx_ll_sof_in_n, // sof indicator to FIFO
tx_ll_eof_in_n, // eof indicator to FIFO
tx_ll_src_rdy_in_n, // src ready indicator to FIFO
tx_ll_dst_rdy_out_n, // dst ready indicator from FIFO
tx_fifo_status, // FIFO memory status
tx_overflow, // FIFO overflow indicator from FIFO
// Receive FIFO MAC RX Interface
rx_clk, // MAC receive clock
rx_reset, // Synchronous reset (rx_clk)
rx_enable, // Clock enable for rx_clk
rx_data, // Data from MAC receiver
rx_data_valid, // Valid signal from MAC receiver
rx_good_frame, // Good frame indicator from MAC receiver
rx_bad_frame, // Bad frame indicator from MAC receiver
rx_overflow, // FIFO overflow indicator from FIFO
// Receive FIFO LocalLink Interface
rx_ll_clock, // Local link read clock
rx_ll_reset, // synchronous reset (rx_ll_clock)
rx_ll_data_out, // Data from Rx FIFO
rx_ll_sof_out_n, // sof indicator from FIFO
rx_ll_eof_out_n, // eof indicator from FIFO
rx_ll_src_rdy_out_n, // src ready indicator from FIFO
rx_ll_dst_rdy_in_n, // dst ready indicator to FIFO
rx_fifo_status // FIFO memory status
);
//---------------------------------------------------------------------------
// Define Interface Signals
//---------------------------------------------------------------------------
parameter FULL_DUPLEX_ONLY = 0;
// Transmit FIFO MAC TX Interface
input tx_clk;
input tx_reset;
input tx_enable;
output [7:0] tx_data;
output tx_data_valid;
input tx_ack;
output tx_underrun;
input tx_collision;
input tx_retransmit;
// Transmit FIFO LocalLink Interface
input tx_ll_clock;
input tx_ll_reset;
input [7:0] tx_ll_data_in;
input tx_ll_sof_in_n;
input tx_ll_eof_in_n;
input tx_ll_src_rdy_in_n;
output tx_ll_dst_rdy_out_n;
output [3:0] tx_fifo_status;
output tx_overflow;
// Receive FIFO MAC RX Interface
input rx_clk;
input rx_reset;
input rx_enable;
input [7:0] rx_data;
input rx_data_valid;
input rx_good_frame;
input rx_bad_frame;
output rx_overflow;
// Receive FIFO LocalLink Interface
input rx_ll_clock;
input rx_ll_reset;
output [7:0] rx_ll_data_out;
output rx_ll_sof_out_n;
output rx_ll_eof_out_n;
output rx_ll_src_rdy_out_n;
input rx_ll_dst_rdy_in_n;
output [3:0] rx_fifo_status;
assign tx_underrun = 1'b0;
// Transmitter FIFO
tx_client_fifo_8 #(
.FULL_DUPLEX_ONLY (FULL_DUPLEX_ONLY)
)
tx_fifo_i (
.rd_clk (tx_clk),
.rd_sreset (tx_reset),
.rd_enable (tx_enable),
.tx_data (tx_data),
.tx_data_valid (tx_data_valid),
.tx_ack (tx_ack),
.tx_collision (tx_collision),
.tx_retransmit (tx_retransmit),
.overflow (tx_overflow),
.wr_clk (tx_ll_clock),
.wr_sreset (tx_ll_reset),
.wr_data (tx_ll_data_in),
.wr_sof_n (tx_ll_sof_in_n),
.wr_eof_n (tx_ll_eof_in_n),
.wr_src_rdy_n (tx_ll_src_rdy_in_n),
.wr_dst_rdy_n (tx_ll_dst_rdy_out_n),
.wr_fifo_status (tx_fifo_status)
);
// Receiver FIFO
rx_client_fifo_8 rx_fifo_i (
.wr_clk (rx_clk),
.wr_enable (rx_enable),
.wr_sreset (rx_reset),
.rx_data (rx_data),
.rx_data_valid (rx_data_valid),
.rx_good_frame (rx_good_frame),
.rx_bad_frame (rx_bad_frame),
.overflow (rx_overflow),
.rd_clk (rx_ll_clock),
.rd_sreset (rx_ll_reset),
.rd_data_out (rx_ll_data_out),
.rd_sof_n (rx_ll_sof_out_n),
.rd_eof_n (rx_ll_eof_out_n),
.rd_src_rdy_n (rx_ll_src_rdy_out_n),
.rd_dst_rdy_n (rx_ll_dst_rdy_in_n),
.rx_fifo_status (rx_fifo_status)
);
endmodule
|
// Model a simple flip flop with asynchronous reset
//
// Notes:
// - Including the reset signal in the sensitivity list is
// what makes the reset asynchronous
//
// - Most flip-flops have an asynchronous reset pin.
// This pin is inferred from the behavioral statement below.
//
// Advantages:
// - Asynchronous resets do not add combinational path delay
// resulting in higher frequency circuits. Most vendor libraries
// include flops with async resets that can be directly inferred
// from the logic below.
//
// - The circuit can be reset without a clock being present
//
// Disadvantages:
// - Async reset can be asserted/deasserted at anytime (e.g.
// from a board pin). The assertion/de-assertion may not
// be clean (i.e. can glitch/bounce). If the reset removal
// happens during during the setup/hold time of the flop,
// flop output can go metastable (this is true for sync
// reset as well - but the problem is more common in async flops).
// It is recommended to use a reset removal circuit to
// remove any glitching for async reset.
// - Suppose the async reset is applied to two flops.
// Each flop could recieve the reset signal at different times
// and cause reset at different times. This will cause
// different registers to exit the reset state at different time.
// This behavior can cascade through the design.
//
// - As a general guideline, always synchronize asynchronous
// reset inputs using a reset synchronizer circuit
// (see reset_synchronizer.v)
//
//
module flop_async_rst(
input clk,
input arst,
input din,
output reg q
);
always@(posedge clk or posedge arst)
if(rst)
q <= 0;
else
q <= din;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O21BA_FUNCTIONAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire nor0_out ;
wire nor1_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_FUNCTIONAL_V
|
`timescale 1ns / 1ps
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
module mmc3_eth_core(
input wire RESET_N,
// clocks from PLL clock buffers
input wire BUS_CLK, CLK125TX, CLK125TX90, CLK125RX,
input wire PLL_LOCKED,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS,
input wire fifo_empty,
input wire fifo_full,
input wire FIFO_NEXT,
output wire FIFO_WRITE,
output wire [31:0] FIFO_DATA,
output wire [7:0] GPIO
);
/* ------- MODULE ADREESSES ------- */
localparam GPIO_BASEADDR = 32'h1000;
localparam GPIO_HIGHADDR = 32'h101f;
/* ------- USER MODULES ------- */
gpio #(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(32),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio_rx (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(GPIO)
);
reg [31:0] datasource;
reg fifo_write;
assign FIFO_WRITE = fifo_write;
reg [31:0] fifo_data_out;
assign FIFO_DATA = fifo_data_out;
/* ------- Main FSM ------- */
always@ (posedge BUS_CLK)
begin
// FIFO handshake
if(FIFO_NEXT) begin
if(!fifo_full) begin
fifo_data_out <= datasource;
datasource <= datasource + 1;
fifo_write <= 1'b1;
end
else
fifo_write <= 1'b0;
end
else begin
datasource <= 'd0;
fifo_write <= 1'b0;
end
end
endmodule
|
//
// Testbench
//
// by
// David M. Koltak 05/30/2017
//
// The MIT License (MIT)
//
// Copyright (c) 2017 David M. Koltak
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
module testbench();
reg sim_rst;
reg sim_clk;
reg sim_clk_gen;
integer cycle_count;
initial
begin
sim_rst = 1;
sim_clk_gen = 0;
$dumpfile("results.vcd");
$dumpvars(0);
cycle_count = 0;
#10 sim_rst = 0;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#5 sim_rst = 1;
#5 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen;
#10 sim_clk_gen = ~sim_clk_gen; sim_rst = 0;
while (1)
begin
#10 sim_clk_gen = ~sim_clk_gen;
cycle_count = (sim_clk_gen) ? cycle_count : cycle_count + 1;
end
end
always @ (sim_clk_gen)
sim_clk <= sim_clk_gen;
integer CLOCK_LIMIT;
wire [4:0] user_leds;
reg [31:0] test_progress;
always @ (posedge sim_clk or posedge sim_rst)
if (sim_rst)
begin
CLOCK_LIMIT <= 32'd0;
test_progress <= de0_nano_soc.testregs.test_progress;
end
else
begin
CLOCK_LIMIT <= CLOCK_LIMIT + 32'd1;
if (CLOCK_LIMIT === `MAX_CLOCKS)
begin
#20;
$display(" ****** MAX CLOCKS - ENDING SIMULATION *****");
$finish();
end
if (de0_nano_soc.testregs.test_progress != test_progress)
begin
test_progress <= de0_nano_soc.testregs.test_progress;
$display(" ****** TEST PROGRESS %X *****",
de0_nano_soc.testregs.test_progress);
end
if (de0_nano_soc.testregs.test_fail != 32'd0)
begin
#20;
$display(" ****** TEST FAILED %08X *****" ,
de0_nano_soc.testregs.test_fail);
$finish();
end
if (de0_nano_soc.testregs.test_pass != 32'd0)
begin
#20;
$display(" ****** TEST PASSED %08X *****" ,
de0_nano_soc.testregs.test_pass);
$finish();
end
end
reg sim_clk_slow;
reg sim_clk_slow_gen;
initial
begin
sim_clk_slow_gen = 0;
while (1)
begin
#33 sim_clk_slow_gen = ~sim_clk_slow_gen;
end
end
always @ (sim_clk_slow_gen)
sim_clk_slow <= sim_clk_slow_gen;
wire uart_tx;
wire uart_rx;
de0_nano_soc de0_nano_soc
(
.FPGA_CLK1_50(sim_clk),
.FPGA_CLK2_50(sim_clk_slow),
.FPGA_CLK3_50(~sim_clk),
.BUTTON({1'b1, !sim_rst}),
.SW(4'd0),
.LED(),
.UART_TX(uart_tx),
.UART_RX(uart_rx),
.SPDR_TX(uart_rx),
.SPDR_RX(uart_tx)
);
endmodule
|
//deps: alu.v
`timescale 1ns/1ps
`undef assert
`include "cpu_constants.vh"
`define assert(signal, value) \
if (signal !== value) \
$display("ASSERTION FAILED in %m: signal != value"); \
module alu_tb;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] SP_out; // From alu of alu.v
wire [3:0] flags_out; // From alu of alu.v
wire lr_wr_en; // From alu of alu.v
wire [15:0] mem_data; // From alu of alu.v
wire [15:0] out; // From alu of alu.v
wire should_branch; // From alu of alu.v
wire write; // From alu of alu.v
// End of automatics
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg [7:0] alu_control; // To alu of alu.v
reg clk; // To alu of alu.v
reg [3:0] condition; // To alu of alu.v
reg en; // To alu of alu.v
reg en_imm; // To alu of alu.v
reg [3:0] flags_in; // To alu of alu.v
reg [15:0] immediate; // To alu of alu.v
reg mem_displacement; // To alu of alu.v
reg [15:0] rD_data; // To alu of alu.v
reg [15:0] rS_data; // To alu of alu.v
// End of automatics
alu alu(/*AUTOINST*/
// Outputs
.should_branch (should_branch),
.out (out[15:0]),
.mem_data (mem_data[15:0]),
.write (write),
.flags_out (flags_out[3:0]),
.SP_out (SP_out[15:0]),
.lr_wr_en (lr_wr_en),
// Inputs
.clk (clk),
.en (en),
.alu_control (alu_control[7:0]),
.en_imm (en_imm),
.rD_data (rD_data[15:0]),
.rS_data (rS_data[15:0]),
.immediate (immediate[15:0]),
.condition (condition[3:0]),
.flags_in (flags_in[3:0]),
.mem_displacement (mem_displacement));
initial begin
alu_control <= 0;
clk <= 0;
condition <= 0;
en <= 0;
en_imm <= 0;
flags_in <= 0;
immediate <= 0;
mem_displacement <= 0;
rD_data <= 0;
rS_data <= 0;
$dumpfile("dump.vcd");
$dumpvars;
end
always #5 clk <= ~clk;
initial begin
#20 en <= 1;
rD_data <= 5;
rS_data <= 2;
alu_control <= `OPC_ADD;
en_imm <= 0;
#10 `assert(out, 7)
alu_control <= `OPC_SUB;
#10 `assert(out, 3)
alu_control <= `OPC_MOV;
en_imm <= 1;
immediate <= 16'h001d;
#10 `assert(out,16'h1d)
rD_data <= 16'h7fff;
immediate <= 16'h0001;
alu_control <= `OPC_ADD;
#10 `assert(out, 16'h8000)
rD_data <= 16'h0fa5;
rS_data <= 16'h1d3c;
en_imm <= 0;
alu_control <= `OPC_AND;
#10 `assert(out, 16'h0d24)
alu_control <= `OPC_OR;
#10 `assert(out,16'h1fbd)
alu_control <= `OPC_XOR;
#10 `assert(out,16'h1299)
alu_control <= `OPC_NOT;
#10 `assert(out,'hf05a)
alu_control <= `OPC_SHL;
immediate <= 'h0003;
en_imm <= 1;
#10 `assert(out,'h7d28)
alu_control <= `OPC_SHR;
#10 `assert(out,'h01f4)
alu_control <= `OPC_ROL;
immediate <= 'h0006;
#10 $display("ROL not implemented yet!");
alu_control <= `OPC_ADC;
flags_in[`FLAG_BIT_CARRY] <= 1;
rD_data <= 'h0001;
#10 `assert(out,'h0008)
alu_control <= `OPC_PUSH;
rD_data <= 'h0567;
rS_data <= 'h0100;
en_imm <= 0;
#10 `assert(out, 'h00fe)
`assert(SP_out, 'h00fe)
`assert(mem_data, 'h0567)
#10 en <= 0;
#20 $finish;
end
endmodule // alu_tb
/*AUTOUNDEF*/
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_1_V
`define SKY130_FD_SC_LP__NAND2B_1_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_1 (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2b_1 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_1_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`timescale 1 ps / 1 ps
module alt_mem_ddrx_burst_tracking
# (
// module parameter port list
parameter
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 4
)
(
// port list
ctl_clk,
ctl_reset_n,
// data burst interface
burst_ready,
burst_valid,
// burstcount counter sent to data_id_manager
burst_pending_burstcount,
burst_next_pending_burstcount,
// burstcount consumed by data_id_manager
burst_consumed_valid,
burst_counsumed_burstcount
);
// -----------------------------
// local parameter declarations
// -----------------------------
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// data burst interface
input burst_ready;
input burst_valid;
// burstcount counter sent to data_id_manager
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
output [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
// burstcount consumed by data_id_manager
input burst_consumed_valid;
input [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// data burst interface
wire burst_ready;
wire burst_valid;
// burstcount counter sent to data_id_manager
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_pending_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_next_pending_burstcount;
//wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_count_accepted;
// burstcount consumed by data_id_manager
wire burst_consumed_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] burst_counsumed_burstcount;
// -----------------------------
// signal declaration
// -----------------------------
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] burst_counter_next;
wire burst_accepted;
// -----------------------------
// module definition
// -----------------------------
assign burst_pending_burstcount = burst_counter;
assign burst_next_pending_burstcount = burst_counter_next;
assign burst_accepted = burst_ready & burst_valid;
always @ (*)
begin
if (burst_accepted & burst_consumed_valid)
begin
burst_counter_next = burst_counter + 1 - burst_counsumed_burstcount;
end
else if (burst_accepted)
begin
burst_counter_next = burst_counter + 1;
end
else if (burst_consumed_valid)
begin
burst_counter_next = burst_counter - burst_counsumed_burstcount;
end
else
begin
burst_counter_next = burst_counter;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
burst_counter <= 0;
end
else
begin
burst_counter <= burst_counter_next;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:42:46 09/09/2015
// Design Name:
// Module Name: buffer_hdl_core
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module buffer_hdl_core #(
parameter WIDTHA = 8,
parameter SIZEA = 512,
parameter ADDRWIDTHA = 9,
parameter WIDTHB = 16,
parameter SIZEB = 256,
parameter ADDRWIDTHB = 8
)(
input wire buffer_clk_a,
input wire buffer_clk_b,
input wire buffer_we_a,
input wire buffer_we_b,
input wire [ADDRWIDTHA-1:0] buffer_addr_a,
input wire [ADDRWIDTHB-1:0] buffer_addr_b,
input wire [WIDTHA-1:0] buffer_din_a,
input wire [WIDTHB-1:0] buffer_din_b,
output reg [WIDTHA-1:0] buffer_dout_a = 0,
output reg [WIDTHB-1:0] buffer_dout_b = 0
);
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
wire enA;
wire enB;
assign enA = 1;
assign enB = 1;
function integer log2;
input integer value;
reg [31:0] shifted;
integer res;
begin
if (value < 2)
log2 = value;
else
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
end
endfunction
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WIDTHA, WIDTHB);
localparam minWIDTH = `min(WIDTHA, WIDTHB);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
// An asymmetric RAM is modeled in a similar way as a symmetric RAM, with an
// array of array reg. Its aspect ratio corresponds to the port with the
// lower data width (larger depth)
reg [minWIDTH-1:0] buffer_core [0:maxSIZE-1];
genvar i;
// Describe the port with the smaller data width exactly as you are used to
// for symmetric block RAMs
always @(posedge buffer_clk_b)
begin : portB
if (enB)
if (buffer_we_b) begin
buffer_core[buffer_addr_b] <= buffer_din_b;
buffer_dout_b <= buffer_din_b;
end else
buffer_dout_b <= buffer_core[buffer_addr_b];
end
// A generate-for is used to describe the port with the larger data width in a
// generic and compact way
`define BIGEND 1
`ifndef BIGEND
`define LITTLEEND 1
`endif
generate for (i = 0; i < RATIO; i = i+1)
begin: portA
`ifdef LITTLEEND
localparam [log2RATIO-1:0] lsbaddr = i;
`elsif BIGEND
localparam [log2RATIO-1:0] lsbaddr = RATIO-i-1;
`endif
always @(posedge buffer_clk_a)
if (enA) begin
if (buffer_we_a) begin
buffer_core[{buffer_addr_a,lsbaddr}] <= buffer_din_a[(i+1)*minWIDTH-1:i*minWIDTH];
buffer_dout_a[(i+1)*minWIDTH-1:i*minWIDTH] <= buffer_din_a[(i+1)*minWIDTH-1:i*minWIDTH];
end else
buffer_dout_a[(i+1)*minWIDTH-1:i*minWIDTH] <= buffer_core[{buffer_addr_a, lsbaddr}];
end
end
endgenerate
endmodule
|
`define MEM_SIZE 256
`define INIT "../lib/initRegisters.txt"
`define VAL "../lib/regVals.txt"
module im (
input clk,
input [31:0] addr,
output [31:0] data
);
reg [31:0] mem [0:`MEM_SIZE-1];
reg [7:0] test_begin, test_end, regVals_begin, regVals_end;
`ifdef R_TYPE
parameter path = "../program/r_type.txt";
`elsif I_TYPE
parameter path = "../program/i_type.txt";
`elsif BRANCH
parameter path = "../program/branch.txt";
`elsif BRANCHN
parameter path = "../program/branchn.txt";
`elsif JUMP
parameter path = "../program/jump.txt";
`elsif JAL
parameter path = "../program/jal.txt";
`elsif LOOP
parameter path = "../program/loop.txt";
`else
parameter path = "../program/test.txt";
`endif
parameter initRegisters = `INIT;
parameter regVals = `VAL;
initial begin
/*
test_begin = 31;
test_end = 30+`CODE_SIZE;
regVals_begin = 30+`CODE_SIZE+1;
regVals_end = 30+`CODE_SIZE+32;
*/
$readmemh(path, mem, 1, `MEM_SIZE-33 );
// $readmemh(initRegisters, mem, 0 , 30 );
// $readmemh(path , mem, 31 , `MEM_SIZE-33);
// $readmemh(regVals , mem, `MEM_SIZE-32, `MEM_SIZE-1);
end
assign data = mem[addr];
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:31:20 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_rp/bg_rp_sim_netlist.v
// Design : bg_rp
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bg_rp,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bg_rp
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [7:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [7:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [7:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [7:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "8" *)
(* C_ADDRB_WIDTH = "8" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.70645 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bg_rp.mem" *)
(* C_INIT_FILE_NAME = "bg_rp.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "156" *)
(* C_READ_DEPTH_B = "156" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "156" *)
(* C_WRITE_DEPTH_B = "156" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
bg_rp_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[7:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[7:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bg_rp_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [7:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [7:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_rp_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_rp_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [7:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [7:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_rp_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_rp_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [7:0]addra;
input [11:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ;
wire [7:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0305060700020301000203010402010704020107030506070002030100030305),
.INIT_01(256'h0001060700000107030506070000010700020301030506070402010704020107),
.INIT_02(256'h0402010702050205020100070001060700000107000001070305060704020107),
.INIT_03(256'h0000010703050607000203010001070500020301030506070402010700010205),
.INIT_04(256'h0305070503050607000203010406030103050607000203010305060700020301),
.INIT_05(256'h0402010704020107000001070406030100020301000001070406030100010607),
.INIT_06(256'h0305060700020301040201070305060703050607000001070305060700000107),
.INIT_07(256'h0003030503050607040201070002060000010607030506070305060703050705),
.INIT_08(256'h0406030100000107000001070305060700020703030506070002030103050607),
.INIT_09(256'h0305060703050607000207030205020502050205040603010305060700020703),
.INIT_0A(256'h0002030100020301000001070305060700010607040603010305060703050705),
.INIT_0B(256'h0002070304020107040201070002030104020107040201070305060700020301),
.INIT_0C(256'h0205020502050205000203010000010703050705030506070001060704020107),
.INIT_0D(256'h0001060700020703030506070402010704020107020502050001030103050607),
.INIT_0E(256'h0205020500020301030506070402010700020703000203010402010704060301),
.INIT_0F(256'h0002030100020703040201070305060700000107030506070402010703050607),
.INIT_10(256'h0402010700020301040201070002070300020703030506070305060700000107),
.INIT_11(256'h0402010700020301000203010402010700020301000203010402010700020301),
.INIT_12(256'h0305060704020107020502050305060700010607040201070305060703050607),
.INIT_13(256'h0000000000000000000000000000000002050205040201070305060700010607),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,dina[5:3],1'b0,1'b0,1'b0,1'b0,1'b0,dina[2:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,dina[11:9],1'b0,1'b0,1'b0,1'b0,1'b0,dina[8:6]}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ,douta[5:3],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ,douta[2:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ,douta[11:9],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ,douta[8:6]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,wea,wea}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bg_rp_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [7:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [7:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_rp_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "8" *) (* C_ADDRB_WIDTH = "8" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.70645 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bg_rp.mem" *)
(* C_INIT_FILE_NAME = "bg_rp.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "156" *) (* C_READ_DEPTH_B = "156" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "156" *) (* C_WRITE_DEPTH_B = "156" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bg_rp_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [7:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [7:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [7:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [7:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [7:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bg_rp_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bg_rp_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [7:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [7:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_rp_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// file: clk_166M_83M_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_166M_83M_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 40.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_166M_83M_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
// Two Way Cache, supporting 64 meg address space.
// Would be easy enough to extend to wider address spaces, just need
// to increase the width of the "tag" blockram.
// If we're targetting Cyclone 3, then we have 9kbit blockrams to play with.
// Each burst, assuming we stick with 4-word bursts, is 64 bits, so a single M9K
// can hold 128 cachelines. Since we're building a 2-way cache, this will end
// up being 2 overlapping sets of 64 cachelines.
// The address is broken down as follows:
// bit 0 is irrelevant because we're working in 16-bit words.
// bits 2:1 specify which word of a burst we're interested in.
// Bits 10:3 specify the six bit address of the cachelines;
// this will map to {1'b0,addr[8:3]} and {1;b1,addr[8:3]} respectively.
// Bits 25:11 have to be stored in the tag, which, it turns out is no problem,
// since we can use 18-bit wide words. The highest bit will be used as
// a "most recently used" flag, leaving one bit spare, so we can support 64 meg
// without changing bit widths.
// (Storing the MRU flag in both tags in a 2-way cache is redundant, so we'll only
// store it in the first tag.)
// FIXME - add bus snooping.
// Bus snooping works simply by invalidating cachelines that match
// addresses appearing on the snoop_addr lines. This is triggered by
// the snoop_req line, which should be taken high when a chipset write to ChipRAM
// takes place.
// Since we can't afford to delay the chipset write accessed, we need to latch
// the snoop address.
module TwoWayCache
(
input clk,
input reset, // active low
input cache_rst,
output ready,
input [31:0] cpu_addr,
input cacheable,
output cache_valid,
input cpu_req, // 1 to request attention
output reg cpu_ack, // 1 to signal that data is ready.
output reg cpu_wr_ack, // 1 to signal that write cycles have been actioned
input cpu_rw, // 1 for read cycles, 0 for write cycles
input cpu_rwl,
input cpu_rwu,
input [15:0] data_from_cpu,
output [15:0] data_to_cpu,
output reg [31:0] sdram_addr,
input [15:0] data_from_sdram,
output reg [15:0] data_to_sdram,
output reg sdram_req,
input sdram_fill,
output reg sdram_rw, // 1 for read cycles, 0 for write cycles
input [20:0] snoop_addr, // Address of chipram writes
input snoop_req // 1 when snoop_addr contains an address that requires invalidation.
);
// States for state machine
parameter WAITING=0, WAITRD=1, WAITFILL=2,
FILL2=3, FILL3=4, FILL4=5, FILL5=6, PAUSE1=7,
WRITE1=8, WRITE2=9, INIT1=10, INIT2=11;
reg [4:0] state = INIT1;
reg init;
reg [7:0] initctr;
assign ready=~init;
// BlockRAM and related signals for data
wire [10:0] data_port1_addr;
wire [10:0] data_port2_addr;
wire [17:0] data_port1_r;
wire [17:0] data_port2_r;
reg[17:0] data_ports_w;
reg data_wren1;
reg data_wren2;
Cache_DataRAM dataram(
.clock(clk),
.address_a(data_port1_addr),
.address_b(data_port2_addr),
.data_a(data_ports_w),
.data_b(data_ports_w),
.q_a(data_port1_r),
.q_b(data_port2_r),
.wren_a(data_wren1),
.wren_b(data_wren2)
);
wire data_valid1;
wire data_valid2;
reg [10:4] latched_cpuaddr;
reg cacheable_l;
reg [15:0] firstword;
assign data_valid1 = data_port1_r[17] & data_port1_r[16];
assign data_valid2 = data_port2_r[17] & data_port2_r[16];
assign data_to_cpu = (readword_burst || !cacheable ? firstword :
((tag_hit1 && data_valid1) ? data_port1_r[15:0] : data_port2_r[15:0]));
assign cache_valid = cacheable & ((tag_hit1 & data_valid1) || (tag_hit2 & data_valid2)) & !readword_burst;
// BlockRAM and related signals for tags.
wire [8:0] tag_port1_addr;
wire [8:0] tag_port2_addr;
wire [17:0] tag_port1_r;
wire [17:0] tag_port2_r;
wire [17:0] tag_port1_w;
wire [17:0] tag_port2_w;
reg tag_wren1;
reg tag_wren2;
reg tag_mru1;
CacheBlockRAM tagram(
.clock(clk),
.address_a(tag_port1_addr),
.address_b(tag_port2_addr),
.data_a(tag_port1_w),
.data_b(tag_port2_w),
.q_a(tag_port1_r),
.q_b(tag_port2_r),
.wren_a(tag_wren1),
.wren_b(tag_wren2)
);
// bits 2:1 specify which word of a burst we're interested in.
// Bits 10:3 specify the six bit address of the cachelines;
// Since we're building a 2-way cache, we'll map this to
// {1'b0,addr[10:3]} and {1;b1,addr[10:3]} respectively.
wire [10:0] cacheline1;
wire [10:0] cacheline2;
reg readword_burst; // Set to 1 when the lsb of the cache address should
// track the SDRAM controller.
reg [9:0] readword;
//assign cacheline1 = {1'b0,cpu_addr[10:3],(readword_burst ? readword : cpu_addr[2:1])};
//assign cacheline2 = {1'b1,cpu_addr[10:3],(readword_burst ? readword : cpu_addr[2:1])};
assign cacheline1 = {1'b0,readword_burst ? readword : cpu_addr[10:1]};
assign cacheline2 = {1'b1,readword_burst ? readword : cpu_addr[10:1]};
// We share each tag between all four words of a cacheline. We therefore only need
// one M9K tag RAM for four M9Ks of data RAM.
assign tag_port1_addr = cacheline1[10:2];
assign tag_port2_addr = cacheline2[10:2];
// The first port contains the mru flag, so we have to write to it on every
// access. The second tag only needs writing when a cacheline in the second
// block is updated, so we tie the write port of the second tag to part of the
// CPU address.
// The first port has to be toggled between old and new data, depending upon
// the state of the mru flag.
// (Writing both ports on every access for troubleshooting)
assign tag_port1_w = {tag_mru1,(tag_mru1 ? cpu_addr[25:9] : tag_port1_r[16:0])};
assign tag_port2_w = {1'b0,(!tag_mru1 ? cpu_addr[25:9] : tag_port2_r[16:0])};
//assign tag_port2_w = {1'b0,cpu_addr[25:9]};
// Boolean signals to indicate cache hits.
wire tag_hit1;
wire tag_hit2;
assign tag_hit1 = tag_port1_r[16:0]==cpu_addr[25:9];
assign tag_hit2 = tag_port2_r[16:0]==cpu_addr[25:9];
// In the data blockram the lower two bits of the address determine
// which word of the burst we're reading. When reading from the cache, this comes
// from the CPU address; when writing to the cache it's determined by the state
// machine.
assign data_port1_addr = init ? {1'b0,initctr} :
readword_burst ? {1'b0,readword} : cacheline1;
assign data_port2_addr = init ? {1'b1,initctr} :
readword_burst ? {1'b1,readword} : cacheline2;
always @(posedge clk)
begin
// Defaults
tag_wren1<=1'b0;
tag_wren2<=1'b0;
data_wren1<=1'b0;
data_wren2<=1'b0;
init<=1'b0;
readword_burst<=1'b0;
cpu_wr_ack<=1'b0;
case(state)
// FIXME - need an init state here that loops through the data clearing
// the valid flag - for which we'll use bit 17 of the data entry.
INIT1:
begin
init<=1'b1; // need to mark the entire cache as invalid before starting.
initctr<=8'b0000_0000;
data_ports_w<=18'b0; // Mark entire cache as invalid
data_wren1<=1'b1;
data_wren2<=1'b1;
state<=INIT2;
end
INIT2:
begin
init<=1'b1;
initctr<=initctr+1;
data_wren1<=1'b1;
data_wren2<=1'b1;
if(initctr==8'b1111_1111)
state<=WAITING;
end
WAITING:
begin
state<=WAITING;
if(cpu_req==1'b1)
begin
if(cpu_rw==1'b1) // Read cycle
state<=WAITRD;
else // Write cycle
state<=WRITE1;
end
end
WRITE1:
begin
// If the current address is in cache,
// we must update the appropriate cacheline
// We mark the two halves of the word separately.
// If this is a byte write, the byte not being written
// will be marked as invalid, triggering a re-read if
// the other byte or whole word is read.
data_ports_w<={~cpu_rwu,~cpu_rwl,data_from_cpu};
if(tag_hit1)
begin
// Write the data to the first cache way
data_wren1<=1'b1;
// Mark tag1 as most recently used.
tag_mru1<=1'b1;
tag_wren1<=1'b1;
end
// Note: it's possible that both ways of the cache will end up caching
// the same address; if so, we must write to both ways, or at least
// invalidate them both, otherwise we'll have problems with stale data.
if(tag_hit2)
begin
// Write the data to the second cache way
data_wren2<=1'b1;
// Mark tag2 as most recently used.
tag_mru1<=1'b0;
tag_wren1<=1'b1;
end
// FIXME - ultimately we should clear a cacheline here and cache
// the data for future use. Need to have a working valid flag first.
state<=WRITE2;
end
WRITE2:
begin
cpu_wr_ack<=1'b1; // Indicate to the Write cache that it's safe to proceed.
if(cpu_req==1'b0) // Wait for the write cycle to finish
state<=WAITING;
end
WAITRD:
begin
state<=WAITING;
// Check both tags for a match...
if(cacheable && tag_hit1 && data_valid1)
begin
// Copy data to output
// data_to_cpu<=data_port1_r;
// cpu_ack<=1'b1;
// Mark tag1 as most recently used.
tag_mru1<=1'b1;
tag_wren1<=1'b1;
end
else if(cacheable && tag_hit2 && data_valid2)
begin
// Copy data to output
// data_to_cpu<=data_port2_r;
// cpu_ack<=1'b1;
// Mark tag2 as most recently used.
tag_mru1<=1'b0;
tag_wren1<=1'b1;
end
else // No matches? How do we decide which one to use?
begin
// invert most recently used flags on both tags.
// (Whichever one was least recently used will be overwritten, so
// is now the most recently used.)
// If either tag matches, but the corresponding data is stale,
// we re-use the stale cacheline.
latched_cpuaddr[10:4]<=cpu_addr[10:4];
if(tag_hit1)
tag_mru1<=1'b1; // Way 1 contains stale data
else if(tag_hit2)
tag_mru1<=1'b0; // Way 2 contains stale data
else
tag_mru1<=!tag_port1_r[17];
// For simulation only, to avoid the unknown value of unitialised blockram
// tag_mru1<=cpu_addr[1];
tag_wren1<=cacheable; // 1'b1;
tag_wren2<=cacheable; // 1'b1;
// If r[17] is 1, tag_mru1 is 0, so we need to write to the second tag.
// FIXME - might be simpler to just write every cycle and switch between new and old data.
// tag_wren2<=tag_port1_r[17];
// Pass request on to RAM controller.
sdram_addr<={cpu_addr[31:3],3'b000};
sdram_req<=1'b1;
sdram_rw<=1'b1; // Read cycle
state<=WAITFILL;
cacheable_l<=cacheable;
end
end
PAUSE1:
begin
state<=PAUSE1;
if(cpu_req==1'b0)
state<=WAITING;
end
WAITFILL:
begin
readword_burst<=1'b1;
// In the interests of performance, read the word we're waiting for first.
readword<=cpu_addr[10:1];
if (sdram_fill==1'b1)
begin
sdram_req<=1'b0;
firstword <= data_from_sdram;
// Forward data to CPU
// (We now latch the address until the current cycle is complete.
// TAGRAM is already written, so just need to take care of
// Data RAM addresses, which we do with the readword signal.
// data_to_cpu<=data_from_sdram;
cpu_ack<=1'b1;
// write first word to Cache...
data_ports_w<={2'b11,data_from_sdram};
data_wren1<=cacheable_l & tag_mru1;
data_wren2<=cacheable_l & !tag_mru1;
state<=FILL2;
end
end
FILL2:
begin
// write second word to Cache...
readword_burst<=1'b1;
readword[1:0]<=readword[1:0]+1;
data_ports_w<={2'b11,data_from_sdram};
data_wren1<=cacheable_l & tag_mru1;
data_wren2<=cacheable_l & !tag_mru1;
state<=FILL3;
end
FILL3:
begin
// write third word to Cache...
readword_burst<=1'b1;
readword[1:0]<=readword[1:0]+1;
data_ports_w<={2'b11,data_from_sdram};
data_wren1<=cacheable_l & tag_mru1;
data_wren2<=cacheable_l & !tag_mru1;
state<=FILL4;
end
FILL4:
begin
// write last word to Cache...
readword_burst<=1'b1;
readword[1:0]<=readword[1:0]+1;
data_ports_w<={2'b11,data_from_sdram};
data_wren1<=cacheable_l & tag_mru1;
data_wren2<=cacheable_l & !tag_mru1;
state<=FILL5;
end
FILL5:
begin
state<=FILL5;
readword_burst<=1'b1;
readword[1:0]<=cpu_addr[2:1];
// Shouldn't need to worry about readword now - only used during burst
// readword=cpu_addr[2:1];
// Remain on state 5 until cpu_ack is low.
// We use this rather than cpu_req because in the time it's taken us to
// reach this point, it's possible the next request could have started.
if(cpu_ack==1'b0)
state<=WAITING;
end
default:
state<=WAITING;
endcase
// Cancel the ack flag as soon as req drops.
// The state machine will wait for this to happen before starting a new cycle.
if(cpu_req==1'b0)
cpu_ack<=1'b0;
if((reset && cache_rst)==1'b0)
begin
state<=INIT1;
cpu_ack<=1'b0;
end
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="image_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.666670,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=5.810000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=27,HLS_SYN_DSP=0,HLS_SYN_FF=10173,HLS_SYN_LUT=19868}" *)
module image_filter (
INPUT_STREAM_TDATA,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
INPUT_STREAM_TDEST,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST,
rows,
cols,
ap_clk,
ap_rst_n,
ap_start,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
ap_done,
ap_idle,
ap_ready
);
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_true = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_const_logic_1 = 1'b1;
input [31:0] INPUT_STREAM_TDATA;
input [3:0] INPUT_STREAM_TKEEP;
input [3:0] INPUT_STREAM_TSTRB;
input [0:0] INPUT_STREAM_TUSER;
input [0:0] INPUT_STREAM_TLAST;
input [0:0] INPUT_STREAM_TID;
input [0:0] INPUT_STREAM_TDEST;
output [31:0] OUTPUT_STREAM_TDATA;
output [3:0] OUTPUT_STREAM_TKEEP;
output [3:0] OUTPUT_STREAM_TSTRB;
output [0:0] OUTPUT_STREAM_TUSER;
output [0:0] OUTPUT_STREAM_TLAST;
output [0:0] OUTPUT_STREAM_TID;
output [0:0] OUTPUT_STREAM_TDEST;
input [31:0] rows;
input [31:0] cols;
input ap_clk;
input ap_rst_n;
input ap_start;
input INPUT_STREAM_TVALID;
output INPUT_STREAM_TREADY;
output OUTPUT_STREAM_TVALID;
input OUTPUT_STREAM_TREADY;
output ap_done;
output ap_idle;
output ap_ready;
reg ap_idle;
reg ap_rst_n_inv;
wire image_filter_Block_proc_U0_ap_start;
wire image_filter_Block_proc_U0_ap_done;
reg image_filter_Block_proc_U0_ap_continue;
wire image_filter_Block_proc_U0_ap_idle;
wire image_filter_Block_proc_U0_ap_ready;
wire [31:0] image_filter_Block_proc_U0_rows;
wire [31:0] image_filter_Block_proc_U0_cols;
wire [11:0] image_filter_Block_proc_U0_ap_return_0;
wire [11:0] image_filter_Block_proc_U0_ap_return_1;
wire [11:0] image_filter_Block_proc_U0_ap_return_2;
wire [11:0] image_filter_Block_proc_U0_ap_return_3;
wire [11:0] image_filter_Block_proc_U0_ap_return_4;
wire [11:0] image_filter_Block_proc_U0_ap_return_5;
wire [11:0] image_filter_Block_proc_U0_ap_return_6;
wire [11:0] image_filter_Block_proc_U0_ap_return_7;
wire [11:0] image_filter_Block_proc_U0_ap_return_8;
wire [11:0] image_filter_Block_proc_U0_ap_return_9;
wire [11:0] image_filter_Block_proc_U0_ap_return_10;
wire [11:0] image_filter_Block_proc_U0_ap_return_11;
wire [11:0] image_filter_Block_proc_U0_ap_return_12;
wire [11:0] image_filter_Block_proc_U0_ap_return_13;
wire [11:0] image_filter_Block_proc_U0_ap_return_14;
wire [11:0] image_filter_Block_proc_U0_ap_return_15;
wire [11:0] image_filter_Block_proc_U0_ap_return_16;
wire [11:0] image_filter_Block_proc_U0_ap_return_17;
reg ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel1;
wire img_0_cols_V_channel1_full_n;
reg ap_reg_ready_img_0_cols_V_channel1_full_n = 1'b0;
reg ap_sig_ready_img_0_cols_V_channel1_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel;
wire img_0_rows_V_channel_full_n;
reg ap_reg_ready_img_0_rows_V_channel_full_n = 1'b0;
reg ap_sig_ready_img_0_rows_V_channel_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel1;
wire img_0_rows_V_channel1_full_n;
reg ap_reg_ready_img_0_rows_V_channel1_full_n = 1'b0;
reg ap_sig_ready_img_0_rows_V_channel1_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel;
wire img_0_cols_V_channel_full_n;
reg ap_reg_ready_img_0_cols_V_channel_full_n = 1'b0;
reg ap_sig_ready_img_0_cols_V_channel_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V;
wire img_1_rows_V_full_n;
reg ap_reg_ready_img_1_rows_V_full_n = 1'b0;
reg ap_sig_ready_img_1_rows_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V;
wire img_1_cols_V_full_n;
reg ap_reg_ready_img_1_cols_V_full_n = 1'b0;
reg ap_sig_ready_img_1_cols_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V;
wire img_2_rows_V_full_n;
reg ap_reg_ready_img_2_rows_V_full_n = 1'b0;
reg ap_sig_ready_img_2_rows_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V_channel;
wire img_2_rows_V_channel_full_n;
reg ap_reg_ready_img_2_rows_V_channel_full_n = 1'b0;
reg ap_sig_ready_img_2_rows_V_channel_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V;
wire img_2_cols_V_full_n;
reg ap_reg_ready_img_2_cols_V_full_n = 1'b0;
reg ap_sig_ready_img_2_cols_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V_channel;
wire img_2_cols_V_channel_full_n;
reg ap_reg_ready_img_2_cols_V_channel_full_n = 1'b0;
reg ap_sig_ready_img_2_cols_V_channel_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V;
wire img_3_rows_V_full_n;
reg ap_reg_ready_img_3_rows_V_full_n = 1'b0;
reg ap_sig_ready_img_3_rows_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V_channel;
wire img_3_rows_V_channel_full_n;
reg ap_reg_ready_img_3_rows_V_channel_full_n = 1'b0;
reg ap_sig_ready_img_3_rows_V_channel_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V;
wire img_3_cols_V_full_n;
reg ap_reg_ready_img_3_cols_V_full_n = 1'b0;
reg ap_sig_ready_img_3_cols_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V_channel;
wire img_3_cols_V_channel_full_n;
reg ap_reg_ready_img_3_cols_V_channel_full_n = 1'b0;
reg ap_sig_ready_img_3_cols_V_channel_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_4_rows_V;
wire img_4_rows_V_full_n;
reg ap_reg_ready_img_4_rows_V_full_n = 1'b0;
reg ap_sig_ready_img_4_rows_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_4_cols_V;
wire img_4_cols_V_full_n;
reg ap_reg_ready_img_4_cols_V_full_n = 1'b0;
reg ap_sig_ready_img_4_cols_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_5_rows_V;
wire img_5_rows_V_full_n;
reg ap_reg_ready_img_5_rows_V_full_n = 1'b0;
reg ap_sig_ready_img_5_rows_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_5_cols_V;
wire img_5_cols_V_full_n;
reg ap_reg_ready_img_5_cols_V_full_n = 1'b0;
reg ap_sig_ready_img_5_cols_V_full_n;
wire image_filter_AXIvideo2Mat_U0_ap_start;
wire image_filter_AXIvideo2Mat_U0_ap_done;
wire image_filter_AXIvideo2Mat_U0_ap_continue;
wire image_filter_AXIvideo2Mat_U0_ap_idle;
wire image_filter_AXIvideo2Mat_U0_ap_ready;
wire [31:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA;
wire image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID;
wire image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY;
wire [3:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP;
wire [3:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB;
wire [0:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER;
wire [0:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST;
wire [0:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID;
wire [0:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST;
wire [11:0] image_filter_AXIvideo2Mat_U0_img_rows_V_read;
wire [11:0] image_filter_AXIvideo2Mat_U0_img_cols_V_read;
wire [7:0] image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write;
wire [7:0] image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write;
wire [7:0] image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write;
wire image_filter_Sobel_U0_ap_start;
wire image_filter_Sobel_U0_ap_done;
wire image_filter_Sobel_U0_ap_continue;
wire image_filter_Sobel_U0_ap_idle;
wire image_filter_Sobel_U0_ap_ready;
wire [11:0] image_filter_Sobel_U0_p_src_rows_V_read;
wire [11:0] image_filter_Sobel_U0_p_src_cols_V_read;
wire [7:0] image_filter_Sobel_U0_p_src_data_stream_0_V_dout;
wire image_filter_Sobel_U0_p_src_data_stream_0_V_empty_n;
wire image_filter_Sobel_U0_p_src_data_stream_0_V_read;
wire [7:0] image_filter_Sobel_U0_p_src_data_stream_1_V_dout;
wire image_filter_Sobel_U0_p_src_data_stream_1_V_empty_n;
wire image_filter_Sobel_U0_p_src_data_stream_1_V_read;
wire [7:0] image_filter_Sobel_U0_p_src_data_stream_2_V_dout;
wire image_filter_Sobel_U0_p_src_data_stream_2_V_empty_n;
wire image_filter_Sobel_U0_p_src_data_stream_2_V_read;
wire [7:0] image_filter_Sobel_U0_p_dst_data_stream_0_V_din;
wire image_filter_Sobel_U0_p_dst_data_stream_0_V_full_n;
wire image_filter_Sobel_U0_p_dst_data_stream_0_V_write;
wire [7:0] image_filter_Sobel_U0_p_dst_data_stream_1_V_din;
wire image_filter_Sobel_U0_p_dst_data_stream_1_V_full_n;
wire image_filter_Sobel_U0_p_dst_data_stream_1_V_write;
wire [7:0] image_filter_Sobel_U0_p_dst_data_stream_2_V_din;
wire image_filter_Sobel_U0_p_dst_data_stream_2_V_full_n;
wire image_filter_Sobel_U0_p_dst_data_stream_2_V_write;
wire image_filter_SubS_U0_ap_start;
wire image_filter_SubS_U0_ap_done;
wire image_filter_SubS_U0_ap_continue;
wire image_filter_SubS_U0_ap_idle;
wire image_filter_SubS_U0_ap_ready;
wire [11:0] image_filter_SubS_U0_src_rows_V_read;
wire [11:0] image_filter_SubS_U0_src_cols_V_read;
wire [7:0] image_filter_SubS_U0_src_data_stream_0_V_dout;
wire image_filter_SubS_U0_src_data_stream_0_V_empty_n;
wire image_filter_SubS_U0_src_data_stream_0_V_read;
wire [7:0] image_filter_SubS_U0_src_data_stream_1_V_dout;
wire image_filter_SubS_U0_src_data_stream_1_V_empty_n;
wire image_filter_SubS_U0_src_data_stream_1_V_read;
wire [7:0] image_filter_SubS_U0_src_data_stream_2_V_dout;
wire image_filter_SubS_U0_src_data_stream_2_V_empty_n;
wire image_filter_SubS_U0_src_data_stream_2_V_read;
wire [11:0] image_filter_SubS_U0_dst_rows_V_read;
wire [11:0] image_filter_SubS_U0_dst_cols_V_read;
wire [7:0] image_filter_SubS_U0_dst_data_stream_0_V_din;
wire image_filter_SubS_U0_dst_data_stream_0_V_full_n;
wire image_filter_SubS_U0_dst_data_stream_0_V_write;
wire [7:0] image_filter_SubS_U0_dst_data_stream_1_V_din;
wire image_filter_SubS_U0_dst_data_stream_1_V_full_n;
wire image_filter_SubS_U0_dst_data_stream_1_V_write;
wire [7:0] image_filter_SubS_U0_dst_data_stream_2_V_din;
wire image_filter_SubS_U0_dst_data_stream_2_V_full_n;
wire image_filter_SubS_U0_dst_data_stream_2_V_write;
wire image_filter_Scale_1080_1920_32_32_int_U0_ap_start;
wire image_filter_Scale_1080_1920_32_32_int_U0_ap_done;
wire image_filter_Scale_1080_1920_32_32_int_U0_ap_continue;
wire image_filter_Scale_1080_1920_32_32_int_U0_ap_idle;
wire image_filter_Scale_1080_1920_32_32_int_U0_ap_ready;
wire [11:0] image_filter_Scale_1080_1920_32_32_int_U0_src_rows_V_read;
wire [11:0] image_filter_Scale_1080_1920_32_32_int_U0_src_cols_V_read;
wire [7:0] image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_0_V_dout;
wire image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_0_V_empty_n;
wire image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_0_V_read;
wire [7:0] image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_1_V_dout;
wire image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_1_V_empty_n;
wire image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_1_V_read;
wire [7:0] image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_2_V_dout;
wire image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_2_V_empty_n;
wire image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_2_V_read;
wire [11:0] image_filter_Scale_1080_1920_32_32_int_U0_dst_rows_V_read;
wire [11:0] image_filter_Scale_1080_1920_32_32_int_U0_dst_cols_V_read;
wire [7:0] image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_0_V_din;
wire image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_0_V_full_n;
wire image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_0_V_write;
wire [7:0] image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_1_V_din;
wire image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_1_V_full_n;
wire image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_1_V_write;
wire [7:0] image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_2_V_din;
wire image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_2_V_full_n;
wire image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_2_V_write;
wire image_filter_Erode_32_32_1080_1920_U0_ap_start;
wire image_filter_Erode_32_32_1080_1920_U0_ap_done;
wire image_filter_Erode_32_32_1080_1920_U0_ap_continue;
wire image_filter_Erode_32_32_1080_1920_U0_ap_idle;
wire image_filter_Erode_32_32_1080_1920_U0_ap_ready;
wire [11:0] image_filter_Erode_32_32_1080_1920_U0_p_src_rows_V_read;
wire [11:0] image_filter_Erode_32_32_1080_1920_U0_p_src_cols_V_read;
wire [7:0] image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_0_V_dout;
wire image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_0_V_empty_n;
wire image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_0_V_read;
wire [7:0] image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_1_V_dout;
wire image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_1_V_empty_n;
wire image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_1_V_read;
wire [7:0] image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_2_V_dout;
wire image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_2_V_empty_n;
wire image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_2_V_read;
wire [7:0] image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_0_V_din;
wire image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_0_V_full_n;
wire image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_0_V_write;
wire [7:0] image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_1_V_din;
wire image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_1_V_full_n;
wire image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_1_V_write;
wire [7:0] image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_2_V_din;
wire image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_2_V_full_n;
wire image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_2_V_write;
wire image_filter_Dilate_32_32_1080_1920_U0_ap_start;
wire image_filter_Dilate_32_32_1080_1920_U0_ap_done;
wire image_filter_Dilate_32_32_1080_1920_U0_ap_continue;
wire image_filter_Dilate_32_32_1080_1920_U0_ap_idle;
wire image_filter_Dilate_32_32_1080_1920_U0_ap_ready;
wire [11:0] image_filter_Dilate_32_32_1080_1920_U0_p_src_rows_V_read;
wire [11:0] image_filter_Dilate_32_32_1080_1920_U0_p_src_cols_V_read;
wire [7:0] image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_0_V_dout;
wire image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_0_V_empty_n;
wire image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_0_V_read;
wire [7:0] image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_1_V_dout;
wire image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_1_V_empty_n;
wire image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_1_V_read;
wire [7:0] image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_2_V_dout;
wire image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_2_V_empty_n;
wire image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_2_V_read;
wire [7:0] image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_0_V_din;
wire image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_0_V_full_n;
wire image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_0_V_write;
wire [7:0] image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_1_V_din;
wire image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_1_V_full_n;
wire image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_1_V_write;
wire [7:0] image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_2_V_din;
wire image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_2_V_full_n;
wire image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_2_V_write;
wire image_filter_Mat2AXIvideo_U0_ap_start;
wire image_filter_Mat2AXIvideo_U0_ap_done;
wire image_filter_Mat2AXIvideo_U0_ap_continue;
wire image_filter_Mat2AXIvideo_U0_ap_idle;
wire image_filter_Mat2AXIvideo_U0_ap_ready;
wire [11:0] image_filter_Mat2AXIvideo_U0_img_rows_V_read;
wire [11:0] image_filter_Mat2AXIvideo_U0_img_cols_V_read;
wire [7:0] image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read;
wire [7:0] image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read;
wire [7:0] image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read;
wire [31:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA;
wire image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID;
wire image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY;
wire [3:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP;
wire [3:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB;
wire [0:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER;
wire [0:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST;
wire [0:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID;
wire [0:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST;
wire ap_sig_hs_continue;
wire img_0_rows_V_channel_U_ap_dummy_ce;
wire [11:0] img_0_rows_V_channel_din;
wire img_0_rows_V_channel_write;
wire [11:0] img_0_rows_V_channel_dout;
wire img_0_rows_V_channel_empty_n;
wire img_0_rows_V_channel_read;
wire img_0_rows_V_channel1_U_ap_dummy_ce;
wire [11:0] img_0_rows_V_channel1_din;
wire img_0_rows_V_channel1_write;
wire [11:0] img_0_rows_V_channel1_dout;
wire img_0_rows_V_channel1_empty_n;
wire img_0_rows_V_channel1_read;
wire img_0_cols_V_channel_U_ap_dummy_ce;
wire [11:0] img_0_cols_V_channel_din;
wire img_0_cols_V_channel_write;
wire [11:0] img_0_cols_V_channel_dout;
wire img_0_cols_V_channel_empty_n;
wire img_0_cols_V_channel_read;
wire img_0_cols_V_channel1_U_ap_dummy_ce;
wire [11:0] img_0_cols_V_channel1_din;
wire img_0_cols_V_channel1_write;
wire [11:0] img_0_cols_V_channel1_dout;
wire img_0_cols_V_channel1_empty_n;
wire img_0_cols_V_channel1_read;
wire img_1_rows_V_U_ap_dummy_ce;
wire [11:0] img_1_rows_V_din;
wire img_1_rows_V_write;
wire [11:0] img_1_rows_V_dout;
wire img_1_rows_V_empty_n;
wire img_1_rows_V_read;
wire img_1_cols_V_U_ap_dummy_ce;
wire [11:0] img_1_cols_V_din;
wire img_1_cols_V_write;
wire [11:0] img_1_cols_V_dout;
wire img_1_cols_V_empty_n;
wire img_1_cols_V_read;
wire img_2_rows_V_U_ap_dummy_ce;
wire [11:0] img_2_rows_V_din;
wire img_2_rows_V_write;
wire [11:0] img_2_rows_V_dout;
wire img_2_rows_V_empty_n;
wire img_2_rows_V_read;
wire img_2_rows_V_channel_U_ap_dummy_ce;
wire [11:0] img_2_rows_V_channel_din;
wire img_2_rows_V_channel_write;
wire [11:0] img_2_rows_V_channel_dout;
wire img_2_rows_V_channel_empty_n;
wire img_2_rows_V_channel_read;
wire img_2_cols_V_U_ap_dummy_ce;
wire [11:0] img_2_cols_V_din;
wire img_2_cols_V_write;
wire [11:0] img_2_cols_V_dout;
wire img_2_cols_V_empty_n;
wire img_2_cols_V_read;
wire img_2_cols_V_channel_U_ap_dummy_ce;
wire [11:0] img_2_cols_V_channel_din;
wire img_2_cols_V_channel_write;
wire [11:0] img_2_cols_V_channel_dout;
wire img_2_cols_V_channel_empty_n;
wire img_2_cols_V_channel_read;
wire img_3_rows_V_U_ap_dummy_ce;
wire [11:0] img_3_rows_V_din;
wire img_3_rows_V_write;
wire [11:0] img_3_rows_V_dout;
wire img_3_rows_V_empty_n;
wire img_3_rows_V_read;
wire img_3_rows_V_channel_U_ap_dummy_ce;
wire [11:0] img_3_rows_V_channel_din;
wire img_3_rows_V_channel_write;
wire [11:0] img_3_rows_V_channel_dout;
wire img_3_rows_V_channel_empty_n;
wire img_3_rows_V_channel_read;
wire img_3_cols_V_U_ap_dummy_ce;
wire [11:0] img_3_cols_V_din;
wire img_3_cols_V_write;
wire [11:0] img_3_cols_V_dout;
wire img_3_cols_V_empty_n;
wire img_3_cols_V_read;
wire img_3_cols_V_channel_U_ap_dummy_ce;
wire [11:0] img_3_cols_V_channel_din;
wire img_3_cols_V_channel_write;
wire [11:0] img_3_cols_V_channel_dout;
wire img_3_cols_V_channel_empty_n;
wire img_3_cols_V_channel_read;
wire img_4_rows_V_U_ap_dummy_ce;
wire [11:0] img_4_rows_V_din;
wire img_4_rows_V_write;
wire [11:0] img_4_rows_V_dout;
wire img_4_rows_V_empty_n;
wire img_4_rows_V_read;
wire img_4_cols_V_U_ap_dummy_ce;
wire [11:0] img_4_cols_V_din;
wire img_4_cols_V_write;
wire [11:0] img_4_cols_V_dout;
wire img_4_cols_V_empty_n;
wire img_4_cols_V_read;
wire img_5_rows_V_U_ap_dummy_ce;
wire [11:0] img_5_rows_V_din;
wire img_5_rows_V_write;
wire [11:0] img_5_rows_V_dout;
wire img_5_rows_V_empty_n;
wire img_5_rows_V_read;
wire img_5_cols_V_U_ap_dummy_ce;
wire [11:0] img_5_cols_V_din;
wire img_5_cols_V_write;
wire [11:0] img_5_cols_V_dout;
wire img_5_cols_V_empty_n;
wire img_5_cols_V_read;
wire img_0_data_stream_0_V_U_ap_dummy_ce;
wire [7:0] img_0_data_stream_0_V_din;
wire img_0_data_stream_0_V_full_n;
wire img_0_data_stream_0_V_write;
wire [7:0] img_0_data_stream_0_V_dout;
wire img_0_data_stream_0_V_empty_n;
wire img_0_data_stream_0_V_read;
wire img_0_data_stream_1_V_U_ap_dummy_ce;
wire [7:0] img_0_data_stream_1_V_din;
wire img_0_data_stream_1_V_full_n;
wire img_0_data_stream_1_V_write;
wire [7:0] img_0_data_stream_1_V_dout;
wire img_0_data_stream_1_V_empty_n;
wire img_0_data_stream_1_V_read;
wire img_0_data_stream_2_V_U_ap_dummy_ce;
wire [7:0] img_0_data_stream_2_V_din;
wire img_0_data_stream_2_V_full_n;
wire img_0_data_stream_2_V_write;
wire [7:0] img_0_data_stream_2_V_dout;
wire img_0_data_stream_2_V_empty_n;
wire img_0_data_stream_2_V_read;
wire img_1_data_stream_0_V_U_ap_dummy_ce;
wire [7:0] img_1_data_stream_0_V_din;
wire img_1_data_stream_0_V_full_n;
wire img_1_data_stream_0_V_write;
wire [7:0] img_1_data_stream_0_V_dout;
wire img_1_data_stream_0_V_empty_n;
wire img_1_data_stream_0_V_read;
wire img_1_data_stream_1_V_U_ap_dummy_ce;
wire [7:0] img_1_data_stream_1_V_din;
wire img_1_data_stream_1_V_full_n;
wire img_1_data_stream_1_V_write;
wire [7:0] img_1_data_stream_1_V_dout;
wire img_1_data_stream_1_V_empty_n;
wire img_1_data_stream_1_V_read;
wire img_1_data_stream_2_V_U_ap_dummy_ce;
wire [7:0] img_1_data_stream_2_V_din;
wire img_1_data_stream_2_V_full_n;
wire img_1_data_stream_2_V_write;
wire [7:0] img_1_data_stream_2_V_dout;
wire img_1_data_stream_2_V_empty_n;
wire img_1_data_stream_2_V_read;
wire img_2_data_stream_0_V_U_ap_dummy_ce;
wire [7:0] img_2_data_stream_0_V_din;
wire img_2_data_stream_0_V_full_n;
wire img_2_data_stream_0_V_write;
wire [7:0] img_2_data_stream_0_V_dout;
wire img_2_data_stream_0_V_empty_n;
wire img_2_data_stream_0_V_read;
wire img_2_data_stream_1_V_U_ap_dummy_ce;
wire [7:0] img_2_data_stream_1_V_din;
wire img_2_data_stream_1_V_full_n;
wire img_2_data_stream_1_V_write;
wire [7:0] img_2_data_stream_1_V_dout;
wire img_2_data_stream_1_V_empty_n;
wire img_2_data_stream_1_V_read;
wire img_2_data_stream_2_V_U_ap_dummy_ce;
wire [7:0] img_2_data_stream_2_V_din;
wire img_2_data_stream_2_V_full_n;
wire img_2_data_stream_2_V_write;
wire [7:0] img_2_data_stream_2_V_dout;
wire img_2_data_stream_2_V_empty_n;
wire img_2_data_stream_2_V_read;
wire img_3_data_stream_0_V_U_ap_dummy_ce;
wire [7:0] img_3_data_stream_0_V_din;
wire img_3_data_stream_0_V_full_n;
wire img_3_data_stream_0_V_write;
wire [7:0] img_3_data_stream_0_V_dout;
wire img_3_data_stream_0_V_empty_n;
wire img_3_data_stream_0_V_read;
wire img_3_data_stream_1_V_U_ap_dummy_ce;
wire [7:0] img_3_data_stream_1_V_din;
wire img_3_data_stream_1_V_full_n;
wire img_3_data_stream_1_V_write;
wire [7:0] img_3_data_stream_1_V_dout;
wire img_3_data_stream_1_V_empty_n;
wire img_3_data_stream_1_V_read;
wire img_3_data_stream_2_V_U_ap_dummy_ce;
wire [7:0] img_3_data_stream_2_V_din;
wire img_3_data_stream_2_V_full_n;
wire img_3_data_stream_2_V_write;
wire [7:0] img_3_data_stream_2_V_dout;
wire img_3_data_stream_2_V_empty_n;
wire img_3_data_stream_2_V_read;
wire img_4_data_stream_0_V_U_ap_dummy_ce;
wire [7:0] img_4_data_stream_0_V_din;
wire img_4_data_stream_0_V_full_n;
wire img_4_data_stream_0_V_write;
wire [7:0] img_4_data_stream_0_V_dout;
wire img_4_data_stream_0_V_empty_n;
wire img_4_data_stream_0_V_read;
wire img_4_data_stream_1_V_U_ap_dummy_ce;
wire [7:0] img_4_data_stream_1_V_din;
wire img_4_data_stream_1_V_full_n;
wire img_4_data_stream_1_V_write;
wire [7:0] img_4_data_stream_1_V_dout;
wire img_4_data_stream_1_V_empty_n;
wire img_4_data_stream_1_V_read;
wire img_4_data_stream_2_V_U_ap_dummy_ce;
wire [7:0] img_4_data_stream_2_V_din;
wire img_4_data_stream_2_V_full_n;
wire img_4_data_stream_2_V_write;
wire [7:0] img_4_data_stream_2_V_dout;
wire img_4_data_stream_2_V_empty_n;
wire img_4_data_stream_2_V_read;
wire img_5_data_stream_0_V_U_ap_dummy_ce;
wire [7:0] img_5_data_stream_0_V_din;
wire img_5_data_stream_0_V_full_n;
wire img_5_data_stream_0_V_write;
wire [7:0] img_5_data_stream_0_V_dout;
wire img_5_data_stream_0_V_empty_n;
wire img_5_data_stream_0_V_read;
wire img_5_data_stream_1_V_U_ap_dummy_ce;
wire [7:0] img_5_data_stream_1_V_din;
wire img_5_data_stream_1_V_full_n;
wire img_5_data_stream_1_V_write;
wire [7:0] img_5_data_stream_1_V_dout;
wire img_5_data_stream_1_V_empty_n;
wire img_5_data_stream_1_V_read;
wire img_5_data_stream_2_V_U_ap_dummy_ce;
wire [7:0] img_5_data_stream_2_V_din;
wire img_5_data_stream_2_V_full_n;
wire img_5_data_stream_2_V_write;
wire [7:0] img_5_data_stream_2_V_dout;
wire img_5_data_stream_2_V_empty_n;
wire img_5_data_stream_2_V_read;
reg ap_reg_procdone_image_filter_Block_proc_U0 = 1'b0;
reg ap_sig_hs_done;
reg ap_reg_procdone_image_filter_AXIvideo2Mat_U0 = 1'b0;
reg ap_reg_procdone_image_filter_Sobel_U0 = 1'b0;
reg ap_reg_procdone_image_filter_SubS_U0 = 1'b0;
reg ap_reg_procdone_image_filter_Scale_1080_1920_32_32_int_U0 = 1'b0;
reg ap_reg_procdone_image_filter_Erode_32_32_1080_1920_U0 = 1'b0;
reg ap_reg_procdone_image_filter_Dilate_32_32_1080_1920_U0 = 1'b0;
reg ap_reg_procdone_image_filter_Mat2AXIvideo_U0 = 1'b0;
reg ap_CS;
wire ap_sig_top_allready;
image_filter_Block_proc image_filter_Block_proc_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_Block_proc_U0_ap_start ),
.ap_done( image_filter_Block_proc_U0_ap_done ),
.ap_continue( image_filter_Block_proc_U0_ap_continue ),
.ap_idle( image_filter_Block_proc_U0_ap_idle ),
.ap_ready( image_filter_Block_proc_U0_ap_ready ),
.rows( image_filter_Block_proc_U0_rows ),
.cols( image_filter_Block_proc_U0_cols ),
.ap_return_0( image_filter_Block_proc_U0_ap_return_0 ),
.ap_return_1( image_filter_Block_proc_U0_ap_return_1 ),
.ap_return_2( image_filter_Block_proc_U0_ap_return_2 ),
.ap_return_3( image_filter_Block_proc_U0_ap_return_3 ),
.ap_return_4( image_filter_Block_proc_U0_ap_return_4 ),
.ap_return_5( image_filter_Block_proc_U0_ap_return_5 ),
.ap_return_6( image_filter_Block_proc_U0_ap_return_6 ),
.ap_return_7( image_filter_Block_proc_U0_ap_return_7 ),
.ap_return_8( image_filter_Block_proc_U0_ap_return_8 ),
.ap_return_9( image_filter_Block_proc_U0_ap_return_9 ),
.ap_return_10( image_filter_Block_proc_U0_ap_return_10 ),
.ap_return_11( image_filter_Block_proc_U0_ap_return_11 ),
.ap_return_12( image_filter_Block_proc_U0_ap_return_12 ),
.ap_return_13( image_filter_Block_proc_U0_ap_return_13 ),
.ap_return_14( image_filter_Block_proc_U0_ap_return_14 ),
.ap_return_15( image_filter_Block_proc_U0_ap_return_15 ),
.ap_return_16( image_filter_Block_proc_U0_ap_return_16 ),
.ap_return_17( image_filter_Block_proc_U0_ap_return_17 )
);
image_filter_AXIvideo2Mat image_filter_AXIvideo2Mat_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_AXIvideo2Mat_U0_ap_start ),
.ap_done( image_filter_AXIvideo2Mat_U0_ap_done ),
.ap_continue( image_filter_AXIvideo2Mat_U0_ap_continue ),
.ap_idle( image_filter_AXIvideo2Mat_U0_ap_idle ),
.ap_ready( image_filter_AXIvideo2Mat_U0_ap_ready ),
.INPUT_STREAM_TDATA( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA ),
.INPUT_STREAM_TVALID( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID ),
.INPUT_STREAM_TREADY( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY ),
.INPUT_STREAM_TKEEP( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP ),
.INPUT_STREAM_TSTRB( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB ),
.INPUT_STREAM_TUSER( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER ),
.INPUT_STREAM_TLAST( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST ),
.INPUT_STREAM_TID( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID ),
.INPUT_STREAM_TDEST( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST ),
.img_rows_V_read( image_filter_AXIvideo2Mat_U0_img_rows_V_read ),
.img_cols_V_read( image_filter_AXIvideo2Mat_U0_img_cols_V_read ),
.img_data_stream_0_V_din( image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din ),
.img_data_stream_0_V_full_n( image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n ),
.img_data_stream_0_V_write( image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write ),
.img_data_stream_1_V_din( image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din ),
.img_data_stream_1_V_full_n( image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n ),
.img_data_stream_1_V_write( image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write ),
.img_data_stream_2_V_din( image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din ),
.img_data_stream_2_V_full_n( image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n ),
.img_data_stream_2_V_write( image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write )
);
image_filter_Sobel image_filter_Sobel_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_Sobel_U0_ap_start ),
.ap_done( image_filter_Sobel_U0_ap_done ),
.ap_continue( image_filter_Sobel_U0_ap_continue ),
.ap_idle( image_filter_Sobel_U0_ap_idle ),
.ap_ready( image_filter_Sobel_U0_ap_ready ),
.p_src_rows_V_read( image_filter_Sobel_U0_p_src_rows_V_read ),
.p_src_cols_V_read( image_filter_Sobel_U0_p_src_cols_V_read ),
.p_src_data_stream_0_V_dout( image_filter_Sobel_U0_p_src_data_stream_0_V_dout ),
.p_src_data_stream_0_V_empty_n( image_filter_Sobel_U0_p_src_data_stream_0_V_empty_n ),
.p_src_data_stream_0_V_read( image_filter_Sobel_U0_p_src_data_stream_0_V_read ),
.p_src_data_stream_1_V_dout( image_filter_Sobel_U0_p_src_data_stream_1_V_dout ),
.p_src_data_stream_1_V_empty_n( image_filter_Sobel_U0_p_src_data_stream_1_V_empty_n ),
.p_src_data_stream_1_V_read( image_filter_Sobel_U0_p_src_data_stream_1_V_read ),
.p_src_data_stream_2_V_dout( image_filter_Sobel_U0_p_src_data_stream_2_V_dout ),
.p_src_data_stream_2_V_empty_n( image_filter_Sobel_U0_p_src_data_stream_2_V_empty_n ),
.p_src_data_stream_2_V_read( image_filter_Sobel_U0_p_src_data_stream_2_V_read ),
.p_dst_data_stream_0_V_din( image_filter_Sobel_U0_p_dst_data_stream_0_V_din ),
.p_dst_data_stream_0_V_full_n( image_filter_Sobel_U0_p_dst_data_stream_0_V_full_n ),
.p_dst_data_stream_0_V_write( image_filter_Sobel_U0_p_dst_data_stream_0_V_write ),
.p_dst_data_stream_1_V_din( image_filter_Sobel_U0_p_dst_data_stream_1_V_din ),
.p_dst_data_stream_1_V_full_n( image_filter_Sobel_U0_p_dst_data_stream_1_V_full_n ),
.p_dst_data_stream_1_V_write( image_filter_Sobel_U0_p_dst_data_stream_1_V_write ),
.p_dst_data_stream_2_V_din( image_filter_Sobel_U0_p_dst_data_stream_2_V_din ),
.p_dst_data_stream_2_V_full_n( image_filter_Sobel_U0_p_dst_data_stream_2_V_full_n ),
.p_dst_data_stream_2_V_write( image_filter_Sobel_U0_p_dst_data_stream_2_V_write )
);
image_filter_SubS image_filter_SubS_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_SubS_U0_ap_start ),
.ap_done( image_filter_SubS_U0_ap_done ),
.ap_continue( image_filter_SubS_U0_ap_continue ),
.ap_idle( image_filter_SubS_U0_ap_idle ),
.ap_ready( image_filter_SubS_U0_ap_ready ),
.src_rows_V_read( image_filter_SubS_U0_src_rows_V_read ),
.src_cols_V_read( image_filter_SubS_U0_src_cols_V_read ),
.src_data_stream_0_V_dout( image_filter_SubS_U0_src_data_stream_0_V_dout ),
.src_data_stream_0_V_empty_n( image_filter_SubS_U0_src_data_stream_0_V_empty_n ),
.src_data_stream_0_V_read( image_filter_SubS_U0_src_data_stream_0_V_read ),
.src_data_stream_1_V_dout( image_filter_SubS_U0_src_data_stream_1_V_dout ),
.src_data_stream_1_V_empty_n( image_filter_SubS_U0_src_data_stream_1_V_empty_n ),
.src_data_stream_1_V_read( image_filter_SubS_U0_src_data_stream_1_V_read ),
.src_data_stream_2_V_dout( image_filter_SubS_U0_src_data_stream_2_V_dout ),
.src_data_stream_2_V_empty_n( image_filter_SubS_U0_src_data_stream_2_V_empty_n ),
.src_data_stream_2_V_read( image_filter_SubS_U0_src_data_stream_2_V_read ),
.dst_rows_V_read( image_filter_SubS_U0_dst_rows_V_read ),
.dst_cols_V_read( image_filter_SubS_U0_dst_cols_V_read ),
.dst_data_stream_0_V_din( image_filter_SubS_U0_dst_data_stream_0_V_din ),
.dst_data_stream_0_V_full_n( image_filter_SubS_U0_dst_data_stream_0_V_full_n ),
.dst_data_stream_0_V_write( image_filter_SubS_U0_dst_data_stream_0_V_write ),
.dst_data_stream_1_V_din( image_filter_SubS_U0_dst_data_stream_1_V_din ),
.dst_data_stream_1_V_full_n( image_filter_SubS_U0_dst_data_stream_1_V_full_n ),
.dst_data_stream_1_V_write( image_filter_SubS_U0_dst_data_stream_1_V_write ),
.dst_data_stream_2_V_din( image_filter_SubS_U0_dst_data_stream_2_V_din ),
.dst_data_stream_2_V_full_n( image_filter_SubS_U0_dst_data_stream_2_V_full_n ),
.dst_data_stream_2_V_write( image_filter_SubS_U0_dst_data_stream_2_V_write )
);
image_filter_Scale_1080_1920_32_32_int_s image_filter_Scale_1080_1920_32_32_int_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_Scale_1080_1920_32_32_int_U0_ap_start ),
.ap_done( image_filter_Scale_1080_1920_32_32_int_U0_ap_done ),
.ap_continue( image_filter_Scale_1080_1920_32_32_int_U0_ap_continue ),
.ap_idle( image_filter_Scale_1080_1920_32_32_int_U0_ap_idle ),
.ap_ready( image_filter_Scale_1080_1920_32_32_int_U0_ap_ready ),
.src_rows_V_read( image_filter_Scale_1080_1920_32_32_int_U0_src_rows_V_read ),
.src_cols_V_read( image_filter_Scale_1080_1920_32_32_int_U0_src_cols_V_read ),
.src_data_stream_0_V_dout( image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_0_V_dout ),
.src_data_stream_0_V_empty_n( image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_0_V_empty_n ),
.src_data_stream_0_V_read( image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_0_V_read ),
.src_data_stream_1_V_dout( image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_1_V_dout ),
.src_data_stream_1_V_empty_n( image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_1_V_empty_n ),
.src_data_stream_1_V_read( image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_1_V_read ),
.src_data_stream_2_V_dout( image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_2_V_dout ),
.src_data_stream_2_V_empty_n( image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_2_V_empty_n ),
.src_data_stream_2_V_read( image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_2_V_read ),
.dst_rows_V_read( image_filter_Scale_1080_1920_32_32_int_U0_dst_rows_V_read ),
.dst_cols_V_read( image_filter_Scale_1080_1920_32_32_int_U0_dst_cols_V_read ),
.dst_data_stream_0_V_din( image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_0_V_din ),
.dst_data_stream_0_V_full_n( image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_0_V_full_n ),
.dst_data_stream_0_V_write( image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_0_V_write ),
.dst_data_stream_1_V_din( image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_1_V_din ),
.dst_data_stream_1_V_full_n( image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_1_V_full_n ),
.dst_data_stream_1_V_write( image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_1_V_write ),
.dst_data_stream_2_V_din( image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_2_V_din ),
.dst_data_stream_2_V_full_n( image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_2_V_full_n ),
.dst_data_stream_2_V_write( image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_2_V_write )
);
image_filter_Erode_32_32_1080_1920_s image_filter_Erode_32_32_1080_1920_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_Erode_32_32_1080_1920_U0_ap_start ),
.ap_done( image_filter_Erode_32_32_1080_1920_U0_ap_done ),
.ap_continue( image_filter_Erode_32_32_1080_1920_U0_ap_continue ),
.ap_idle( image_filter_Erode_32_32_1080_1920_U0_ap_idle ),
.ap_ready( image_filter_Erode_32_32_1080_1920_U0_ap_ready ),
.p_src_rows_V_read( image_filter_Erode_32_32_1080_1920_U0_p_src_rows_V_read ),
.p_src_cols_V_read( image_filter_Erode_32_32_1080_1920_U0_p_src_cols_V_read ),
.p_src_data_stream_0_V_dout( image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_0_V_dout ),
.p_src_data_stream_0_V_empty_n( image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_0_V_empty_n ),
.p_src_data_stream_0_V_read( image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_0_V_read ),
.p_src_data_stream_1_V_dout( image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_1_V_dout ),
.p_src_data_stream_1_V_empty_n( image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_1_V_empty_n ),
.p_src_data_stream_1_V_read( image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_1_V_read ),
.p_src_data_stream_2_V_dout( image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_2_V_dout ),
.p_src_data_stream_2_V_empty_n( image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_2_V_empty_n ),
.p_src_data_stream_2_V_read( image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_2_V_read ),
.p_dst_data_stream_0_V_din( image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_0_V_din ),
.p_dst_data_stream_0_V_full_n( image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_0_V_full_n ),
.p_dst_data_stream_0_V_write( image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_0_V_write ),
.p_dst_data_stream_1_V_din( image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_1_V_din ),
.p_dst_data_stream_1_V_full_n( image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_1_V_full_n ),
.p_dst_data_stream_1_V_write( image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_1_V_write ),
.p_dst_data_stream_2_V_din( image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_2_V_din ),
.p_dst_data_stream_2_V_full_n( image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_2_V_full_n ),
.p_dst_data_stream_2_V_write( image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_2_V_write )
);
image_filter_Dilate_32_32_1080_1920_s image_filter_Dilate_32_32_1080_1920_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_Dilate_32_32_1080_1920_U0_ap_start ),
.ap_done( image_filter_Dilate_32_32_1080_1920_U0_ap_done ),
.ap_continue( image_filter_Dilate_32_32_1080_1920_U0_ap_continue ),
.ap_idle( image_filter_Dilate_32_32_1080_1920_U0_ap_idle ),
.ap_ready( image_filter_Dilate_32_32_1080_1920_U0_ap_ready ),
.p_src_rows_V_read( image_filter_Dilate_32_32_1080_1920_U0_p_src_rows_V_read ),
.p_src_cols_V_read( image_filter_Dilate_32_32_1080_1920_U0_p_src_cols_V_read ),
.p_src_data_stream_0_V_dout( image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_0_V_dout ),
.p_src_data_stream_0_V_empty_n( image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_0_V_empty_n ),
.p_src_data_stream_0_V_read( image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_0_V_read ),
.p_src_data_stream_1_V_dout( image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_1_V_dout ),
.p_src_data_stream_1_V_empty_n( image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_1_V_empty_n ),
.p_src_data_stream_1_V_read( image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_1_V_read ),
.p_src_data_stream_2_V_dout( image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_2_V_dout ),
.p_src_data_stream_2_V_empty_n( image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_2_V_empty_n ),
.p_src_data_stream_2_V_read( image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_2_V_read ),
.p_dst_data_stream_0_V_din( image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_0_V_din ),
.p_dst_data_stream_0_V_full_n( image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_0_V_full_n ),
.p_dst_data_stream_0_V_write( image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_0_V_write ),
.p_dst_data_stream_1_V_din( image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_1_V_din ),
.p_dst_data_stream_1_V_full_n( image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_1_V_full_n ),
.p_dst_data_stream_1_V_write( image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_1_V_write ),
.p_dst_data_stream_2_V_din( image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_2_V_din ),
.p_dst_data_stream_2_V_full_n( image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_2_V_full_n ),
.p_dst_data_stream_2_V_write( image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_2_V_write )
);
image_filter_Mat2AXIvideo image_filter_Mat2AXIvideo_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_Mat2AXIvideo_U0_ap_start ),
.ap_done( image_filter_Mat2AXIvideo_U0_ap_done ),
.ap_continue( image_filter_Mat2AXIvideo_U0_ap_continue ),
.ap_idle( image_filter_Mat2AXIvideo_U0_ap_idle ),
.ap_ready( image_filter_Mat2AXIvideo_U0_ap_ready ),
.img_rows_V_read( image_filter_Mat2AXIvideo_U0_img_rows_V_read ),
.img_cols_V_read( image_filter_Mat2AXIvideo_U0_img_cols_V_read ),
.img_data_stream_0_V_dout( image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout ),
.img_data_stream_0_V_empty_n( image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n ),
.img_data_stream_0_V_read( image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read ),
.img_data_stream_1_V_dout( image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout ),
.img_data_stream_1_V_empty_n( image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n ),
.img_data_stream_1_V_read( image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read ),
.img_data_stream_2_V_dout( image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout ),
.img_data_stream_2_V_empty_n( image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n ),
.img_data_stream_2_V_read( image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read ),
.OUTPUT_STREAM_TDATA( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA ),
.OUTPUT_STREAM_TVALID( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID ),
.OUTPUT_STREAM_TREADY( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY ),
.OUTPUT_STREAM_TKEEP( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP ),
.OUTPUT_STREAM_TSTRB( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB ),
.OUTPUT_STREAM_TUSER( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER ),
.OUTPUT_STREAM_TLAST( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST ),
.OUTPUT_STREAM_TID( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID ),
.OUTPUT_STREAM_TDEST( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST )
);
FIFO_image_filter_img_0_rows_V_channel img_0_rows_V_channel_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_rows_V_channel_U_ap_dummy_ce ),
.if_write_ce( img_0_rows_V_channel_U_ap_dummy_ce ),
.if_din( img_0_rows_V_channel_din ),
.if_full_n( img_0_rows_V_channel_full_n ),
.if_write( img_0_rows_V_channel_write ),
.if_dout( img_0_rows_V_channel_dout ),
.if_empty_n( img_0_rows_V_channel_empty_n ),
.if_read( img_0_rows_V_channel_read )
);
FIFO_image_filter_img_0_rows_V_channel1 img_0_rows_V_channel1_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_rows_V_channel1_U_ap_dummy_ce ),
.if_write_ce( img_0_rows_V_channel1_U_ap_dummy_ce ),
.if_din( img_0_rows_V_channel1_din ),
.if_full_n( img_0_rows_V_channel1_full_n ),
.if_write( img_0_rows_V_channel1_write ),
.if_dout( img_0_rows_V_channel1_dout ),
.if_empty_n( img_0_rows_V_channel1_empty_n ),
.if_read( img_0_rows_V_channel1_read )
);
FIFO_image_filter_img_0_cols_V_channel img_0_cols_V_channel_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_cols_V_channel_U_ap_dummy_ce ),
.if_write_ce( img_0_cols_V_channel_U_ap_dummy_ce ),
.if_din( img_0_cols_V_channel_din ),
.if_full_n( img_0_cols_V_channel_full_n ),
.if_write( img_0_cols_V_channel_write ),
.if_dout( img_0_cols_V_channel_dout ),
.if_empty_n( img_0_cols_V_channel_empty_n ),
.if_read( img_0_cols_V_channel_read )
);
FIFO_image_filter_img_0_cols_V_channel1 img_0_cols_V_channel1_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_cols_V_channel1_U_ap_dummy_ce ),
.if_write_ce( img_0_cols_V_channel1_U_ap_dummy_ce ),
.if_din( img_0_cols_V_channel1_din ),
.if_full_n( img_0_cols_V_channel1_full_n ),
.if_write( img_0_cols_V_channel1_write ),
.if_dout( img_0_cols_V_channel1_dout ),
.if_empty_n( img_0_cols_V_channel1_empty_n ),
.if_read( img_0_cols_V_channel1_read )
);
FIFO_image_filter_img_1_rows_V img_1_rows_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_rows_V_U_ap_dummy_ce ),
.if_write_ce( img_1_rows_V_U_ap_dummy_ce ),
.if_din( img_1_rows_V_din ),
.if_full_n( img_1_rows_V_full_n ),
.if_write( img_1_rows_V_write ),
.if_dout( img_1_rows_V_dout ),
.if_empty_n( img_1_rows_V_empty_n ),
.if_read( img_1_rows_V_read )
);
FIFO_image_filter_img_1_cols_V img_1_cols_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_cols_V_U_ap_dummy_ce ),
.if_write_ce( img_1_cols_V_U_ap_dummy_ce ),
.if_din( img_1_cols_V_din ),
.if_full_n( img_1_cols_V_full_n ),
.if_write( img_1_cols_V_write ),
.if_dout( img_1_cols_V_dout ),
.if_empty_n( img_1_cols_V_empty_n ),
.if_read( img_1_cols_V_read )
);
FIFO_image_filter_img_2_rows_V img_2_rows_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_2_rows_V_U_ap_dummy_ce ),
.if_write_ce( img_2_rows_V_U_ap_dummy_ce ),
.if_din( img_2_rows_V_din ),
.if_full_n( img_2_rows_V_full_n ),
.if_write( img_2_rows_V_write ),
.if_dout( img_2_rows_V_dout ),
.if_empty_n( img_2_rows_V_empty_n ),
.if_read( img_2_rows_V_read )
);
FIFO_image_filter_img_2_rows_V_channel img_2_rows_V_channel_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_2_rows_V_channel_U_ap_dummy_ce ),
.if_write_ce( img_2_rows_V_channel_U_ap_dummy_ce ),
.if_din( img_2_rows_V_channel_din ),
.if_full_n( img_2_rows_V_channel_full_n ),
.if_write( img_2_rows_V_channel_write ),
.if_dout( img_2_rows_V_channel_dout ),
.if_empty_n( img_2_rows_V_channel_empty_n ),
.if_read( img_2_rows_V_channel_read )
);
FIFO_image_filter_img_2_cols_V img_2_cols_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_2_cols_V_U_ap_dummy_ce ),
.if_write_ce( img_2_cols_V_U_ap_dummy_ce ),
.if_din( img_2_cols_V_din ),
.if_full_n( img_2_cols_V_full_n ),
.if_write( img_2_cols_V_write ),
.if_dout( img_2_cols_V_dout ),
.if_empty_n( img_2_cols_V_empty_n ),
.if_read( img_2_cols_V_read )
);
FIFO_image_filter_img_2_cols_V_channel img_2_cols_V_channel_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_2_cols_V_channel_U_ap_dummy_ce ),
.if_write_ce( img_2_cols_V_channel_U_ap_dummy_ce ),
.if_din( img_2_cols_V_channel_din ),
.if_full_n( img_2_cols_V_channel_full_n ),
.if_write( img_2_cols_V_channel_write ),
.if_dout( img_2_cols_V_channel_dout ),
.if_empty_n( img_2_cols_V_channel_empty_n ),
.if_read( img_2_cols_V_channel_read )
);
FIFO_image_filter_img_3_rows_V img_3_rows_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_3_rows_V_U_ap_dummy_ce ),
.if_write_ce( img_3_rows_V_U_ap_dummy_ce ),
.if_din( img_3_rows_V_din ),
.if_full_n( img_3_rows_V_full_n ),
.if_write( img_3_rows_V_write ),
.if_dout( img_3_rows_V_dout ),
.if_empty_n( img_3_rows_V_empty_n ),
.if_read( img_3_rows_V_read )
);
FIFO_image_filter_img_3_rows_V_channel img_3_rows_V_channel_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_3_rows_V_channel_U_ap_dummy_ce ),
.if_write_ce( img_3_rows_V_channel_U_ap_dummy_ce ),
.if_din( img_3_rows_V_channel_din ),
.if_full_n( img_3_rows_V_channel_full_n ),
.if_write( img_3_rows_V_channel_write ),
.if_dout( img_3_rows_V_channel_dout ),
.if_empty_n( img_3_rows_V_channel_empty_n ),
.if_read( img_3_rows_V_channel_read )
);
FIFO_image_filter_img_3_cols_V img_3_cols_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_3_cols_V_U_ap_dummy_ce ),
.if_write_ce( img_3_cols_V_U_ap_dummy_ce ),
.if_din( img_3_cols_V_din ),
.if_full_n( img_3_cols_V_full_n ),
.if_write( img_3_cols_V_write ),
.if_dout( img_3_cols_V_dout ),
.if_empty_n( img_3_cols_V_empty_n ),
.if_read( img_3_cols_V_read )
);
FIFO_image_filter_img_3_cols_V_channel img_3_cols_V_channel_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_3_cols_V_channel_U_ap_dummy_ce ),
.if_write_ce( img_3_cols_V_channel_U_ap_dummy_ce ),
.if_din( img_3_cols_V_channel_din ),
.if_full_n( img_3_cols_V_channel_full_n ),
.if_write( img_3_cols_V_channel_write ),
.if_dout( img_3_cols_V_channel_dout ),
.if_empty_n( img_3_cols_V_channel_empty_n ),
.if_read( img_3_cols_V_channel_read )
);
FIFO_image_filter_img_4_rows_V img_4_rows_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_4_rows_V_U_ap_dummy_ce ),
.if_write_ce( img_4_rows_V_U_ap_dummy_ce ),
.if_din( img_4_rows_V_din ),
.if_full_n( img_4_rows_V_full_n ),
.if_write( img_4_rows_V_write ),
.if_dout( img_4_rows_V_dout ),
.if_empty_n( img_4_rows_V_empty_n ),
.if_read( img_4_rows_V_read )
);
FIFO_image_filter_img_4_cols_V img_4_cols_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_4_cols_V_U_ap_dummy_ce ),
.if_write_ce( img_4_cols_V_U_ap_dummy_ce ),
.if_din( img_4_cols_V_din ),
.if_full_n( img_4_cols_V_full_n ),
.if_write( img_4_cols_V_write ),
.if_dout( img_4_cols_V_dout ),
.if_empty_n( img_4_cols_V_empty_n ),
.if_read( img_4_cols_V_read )
);
FIFO_image_filter_img_5_rows_V img_5_rows_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_5_rows_V_U_ap_dummy_ce ),
.if_write_ce( img_5_rows_V_U_ap_dummy_ce ),
.if_din( img_5_rows_V_din ),
.if_full_n( img_5_rows_V_full_n ),
.if_write( img_5_rows_V_write ),
.if_dout( img_5_rows_V_dout ),
.if_empty_n( img_5_rows_V_empty_n ),
.if_read( img_5_rows_V_read )
);
FIFO_image_filter_img_5_cols_V img_5_cols_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_5_cols_V_U_ap_dummy_ce ),
.if_write_ce( img_5_cols_V_U_ap_dummy_ce ),
.if_din( img_5_cols_V_din ),
.if_full_n( img_5_cols_V_full_n ),
.if_write( img_5_cols_V_write ),
.if_dout( img_5_cols_V_dout ),
.if_empty_n( img_5_cols_V_empty_n ),
.if_read( img_5_cols_V_read )
);
FIFO_image_filter_img_0_data_stream_0_V img_0_data_stream_0_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_data_stream_0_V_U_ap_dummy_ce ),
.if_write_ce( img_0_data_stream_0_V_U_ap_dummy_ce ),
.if_din( img_0_data_stream_0_V_din ),
.if_full_n( img_0_data_stream_0_V_full_n ),
.if_write( img_0_data_stream_0_V_write ),
.if_dout( img_0_data_stream_0_V_dout ),
.if_empty_n( img_0_data_stream_0_V_empty_n ),
.if_read( img_0_data_stream_0_V_read )
);
FIFO_image_filter_img_0_data_stream_1_V img_0_data_stream_1_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_data_stream_1_V_U_ap_dummy_ce ),
.if_write_ce( img_0_data_stream_1_V_U_ap_dummy_ce ),
.if_din( img_0_data_stream_1_V_din ),
.if_full_n( img_0_data_stream_1_V_full_n ),
.if_write( img_0_data_stream_1_V_write ),
.if_dout( img_0_data_stream_1_V_dout ),
.if_empty_n( img_0_data_stream_1_V_empty_n ),
.if_read( img_0_data_stream_1_V_read )
);
FIFO_image_filter_img_0_data_stream_2_V img_0_data_stream_2_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_data_stream_2_V_U_ap_dummy_ce ),
.if_write_ce( img_0_data_stream_2_V_U_ap_dummy_ce ),
.if_din( img_0_data_stream_2_V_din ),
.if_full_n( img_0_data_stream_2_V_full_n ),
.if_write( img_0_data_stream_2_V_write ),
.if_dout( img_0_data_stream_2_V_dout ),
.if_empty_n( img_0_data_stream_2_V_empty_n ),
.if_read( img_0_data_stream_2_V_read )
);
FIFO_image_filter_img_1_data_stream_0_V img_1_data_stream_0_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_data_stream_0_V_U_ap_dummy_ce ),
.if_write_ce( img_1_data_stream_0_V_U_ap_dummy_ce ),
.if_din( img_1_data_stream_0_V_din ),
.if_full_n( img_1_data_stream_0_V_full_n ),
.if_write( img_1_data_stream_0_V_write ),
.if_dout( img_1_data_stream_0_V_dout ),
.if_empty_n( img_1_data_stream_0_V_empty_n ),
.if_read( img_1_data_stream_0_V_read )
);
FIFO_image_filter_img_1_data_stream_1_V img_1_data_stream_1_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_data_stream_1_V_U_ap_dummy_ce ),
.if_write_ce( img_1_data_stream_1_V_U_ap_dummy_ce ),
.if_din( img_1_data_stream_1_V_din ),
.if_full_n( img_1_data_stream_1_V_full_n ),
.if_write( img_1_data_stream_1_V_write ),
.if_dout( img_1_data_stream_1_V_dout ),
.if_empty_n( img_1_data_stream_1_V_empty_n ),
.if_read( img_1_data_stream_1_V_read )
);
FIFO_image_filter_img_1_data_stream_2_V img_1_data_stream_2_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_data_stream_2_V_U_ap_dummy_ce ),
.if_write_ce( img_1_data_stream_2_V_U_ap_dummy_ce ),
.if_din( img_1_data_stream_2_V_din ),
.if_full_n( img_1_data_stream_2_V_full_n ),
.if_write( img_1_data_stream_2_V_write ),
.if_dout( img_1_data_stream_2_V_dout ),
.if_empty_n( img_1_data_stream_2_V_empty_n ),
.if_read( img_1_data_stream_2_V_read )
);
FIFO_image_filter_img_2_data_stream_0_V img_2_data_stream_0_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_2_data_stream_0_V_U_ap_dummy_ce ),
.if_write_ce( img_2_data_stream_0_V_U_ap_dummy_ce ),
.if_din( img_2_data_stream_0_V_din ),
.if_full_n( img_2_data_stream_0_V_full_n ),
.if_write( img_2_data_stream_0_V_write ),
.if_dout( img_2_data_stream_0_V_dout ),
.if_empty_n( img_2_data_stream_0_V_empty_n ),
.if_read( img_2_data_stream_0_V_read )
);
FIFO_image_filter_img_2_data_stream_1_V img_2_data_stream_1_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_2_data_stream_1_V_U_ap_dummy_ce ),
.if_write_ce( img_2_data_stream_1_V_U_ap_dummy_ce ),
.if_din( img_2_data_stream_1_V_din ),
.if_full_n( img_2_data_stream_1_V_full_n ),
.if_write( img_2_data_stream_1_V_write ),
.if_dout( img_2_data_stream_1_V_dout ),
.if_empty_n( img_2_data_stream_1_V_empty_n ),
.if_read( img_2_data_stream_1_V_read )
);
FIFO_image_filter_img_2_data_stream_2_V img_2_data_stream_2_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_2_data_stream_2_V_U_ap_dummy_ce ),
.if_write_ce( img_2_data_stream_2_V_U_ap_dummy_ce ),
.if_din( img_2_data_stream_2_V_din ),
.if_full_n( img_2_data_stream_2_V_full_n ),
.if_write( img_2_data_stream_2_V_write ),
.if_dout( img_2_data_stream_2_V_dout ),
.if_empty_n( img_2_data_stream_2_V_empty_n ),
.if_read( img_2_data_stream_2_V_read )
);
FIFO_image_filter_img_3_data_stream_0_V img_3_data_stream_0_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_3_data_stream_0_V_U_ap_dummy_ce ),
.if_write_ce( img_3_data_stream_0_V_U_ap_dummy_ce ),
.if_din( img_3_data_stream_0_V_din ),
.if_full_n( img_3_data_stream_0_V_full_n ),
.if_write( img_3_data_stream_0_V_write ),
.if_dout( img_3_data_stream_0_V_dout ),
.if_empty_n( img_3_data_stream_0_V_empty_n ),
.if_read( img_3_data_stream_0_V_read )
);
FIFO_image_filter_img_3_data_stream_1_V img_3_data_stream_1_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_3_data_stream_1_V_U_ap_dummy_ce ),
.if_write_ce( img_3_data_stream_1_V_U_ap_dummy_ce ),
.if_din( img_3_data_stream_1_V_din ),
.if_full_n( img_3_data_stream_1_V_full_n ),
.if_write( img_3_data_stream_1_V_write ),
.if_dout( img_3_data_stream_1_V_dout ),
.if_empty_n( img_3_data_stream_1_V_empty_n ),
.if_read( img_3_data_stream_1_V_read )
);
FIFO_image_filter_img_3_data_stream_2_V img_3_data_stream_2_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_3_data_stream_2_V_U_ap_dummy_ce ),
.if_write_ce( img_3_data_stream_2_V_U_ap_dummy_ce ),
.if_din( img_3_data_stream_2_V_din ),
.if_full_n( img_3_data_stream_2_V_full_n ),
.if_write( img_3_data_stream_2_V_write ),
.if_dout( img_3_data_stream_2_V_dout ),
.if_empty_n( img_3_data_stream_2_V_empty_n ),
.if_read( img_3_data_stream_2_V_read )
);
FIFO_image_filter_img_4_data_stream_0_V img_4_data_stream_0_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_4_data_stream_0_V_U_ap_dummy_ce ),
.if_write_ce( img_4_data_stream_0_V_U_ap_dummy_ce ),
.if_din( img_4_data_stream_0_V_din ),
.if_full_n( img_4_data_stream_0_V_full_n ),
.if_write( img_4_data_stream_0_V_write ),
.if_dout( img_4_data_stream_0_V_dout ),
.if_empty_n( img_4_data_stream_0_V_empty_n ),
.if_read( img_4_data_stream_0_V_read )
);
FIFO_image_filter_img_4_data_stream_1_V img_4_data_stream_1_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_4_data_stream_1_V_U_ap_dummy_ce ),
.if_write_ce( img_4_data_stream_1_V_U_ap_dummy_ce ),
.if_din( img_4_data_stream_1_V_din ),
.if_full_n( img_4_data_stream_1_V_full_n ),
.if_write( img_4_data_stream_1_V_write ),
.if_dout( img_4_data_stream_1_V_dout ),
.if_empty_n( img_4_data_stream_1_V_empty_n ),
.if_read( img_4_data_stream_1_V_read )
);
FIFO_image_filter_img_4_data_stream_2_V img_4_data_stream_2_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_4_data_stream_2_V_U_ap_dummy_ce ),
.if_write_ce( img_4_data_stream_2_V_U_ap_dummy_ce ),
.if_din( img_4_data_stream_2_V_din ),
.if_full_n( img_4_data_stream_2_V_full_n ),
.if_write( img_4_data_stream_2_V_write ),
.if_dout( img_4_data_stream_2_V_dout ),
.if_empty_n( img_4_data_stream_2_V_empty_n ),
.if_read( img_4_data_stream_2_V_read )
);
FIFO_image_filter_img_5_data_stream_0_V img_5_data_stream_0_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_5_data_stream_0_V_U_ap_dummy_ce ),
.if_write_ce( img_5_data_stream_0_V_U_ap_dummy_ce ),
.if_din( img_5_data_stream_0_V_din ),
.if_full_n( img_5_data_stream_0_V_full_n ),
.if_write( img_5_data_stream_0_V_write ),
.if_dout( img_5_data_stream_0_V_dout ),
.if_empty_n( img_5_data_stream_0_V_empty_n ),
.if_read( img_5_data_stream_0_V_read )
);
FIFO_image_filter_img_5_data_stream_1_V img_5_data_stream_1_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_5_data_stream_1_V_U_ap_dummy_ce ),
.if_write_ce( img_5_data_stream_1_V_U_ap_dummy_ce ),
.if_din( img_5_data_stream_1_V_din ),
.if_full_n( img_5_data_stream_1_V_full_n ),
.if_write( img_5_data_stream_1_V_write ),
.if_dout( img_5_data_stream_1_V_dout ),
.if_empty_n( img_5_data_stream_1_V_empty_n ),
.if_read( img_5_data_stream_1_V_read )
);
FIFO_image_filter_img_5_data_stream_2_V img_5_data_stream_2_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_5_data_stream_2_V_U_ap_dummy_ce ),
.if_write_ce( img_5_data_stream_2_V_U_ap_dummy_ce ),
.if_din( img_5_data_stream_2_V_din ),
.if_full_n( img_5_data_stream_2_V_full_n ),
.if_write( img_5_data_stream_2_V_write ),
.if_dout( img_5_data_stream_2_V_dout ),
.if_empty_n( img_5_data_stream_2_V_empty_n ),
.if_read( img_5_data_stream_2_V_read )
);
/// ap_reg_procdone_image_filter_AXIvideo2Mat_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_AXIvideo2Mat_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_AXIvideo2Mat_U0_ap_done)) begin
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_Block_proc_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_Block_proc_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
end else if ((image_filter_Block_proc_U0_ap_done == ap_const_logic_1)) begin
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_Dilate_32_32_1080_1920_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_Dilate_32_32_1080_1920_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_Dilate_32_32_1080_1920_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_Dilate_32_32_1080_1920_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_Dilate_32_32_1080_1920_U0_ap_done)) begin
ap_reg_procdone_image_filter_Dilate_32_32_1080_1920_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_Erode_32_32_1080_1920_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_Erode_32_32_1080_1920_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_Erode_32_32_1080_1920_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_Erode_32_32_1080_1920_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_Erode_32_32_1080_1920_U0_ap_done)) begin
ap_reg_procdone_image_filter_Erode_32_32_1080_1920_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_Mat2AXIvideo_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_Mat2AXIvideo_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_Mat2AXIvideo_U0_ap_done)) begin
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_Scale_1080_1920_32_32_int_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_Scale_1080_1920_32_32_int_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_Scale_1080_1920_32_32_int_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_Scale_1080_1920_32_32_int_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_Scale_1080_1920_32_32_int_U0_ap_done)) begin
ap_reg_procdone_image_filter_Scale_1080_1920_32_32_int_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_Sobel_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_Sobel_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_Sobel_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_Sobel_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_Sobel_U0_ap_done)) begin
ap_reg_procdone_image_filter_Sobel_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_SubS_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_SubS_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_SubS_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_SubS_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_SubS_U0_ap_done)) begin
ap_reg_procdone_image_filter_SubS_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_0_cols_V_channel1_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_0_cols_V_channel1_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_0_cols_V_channel1_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_0_cols_V_channel1_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (img_0_cols_V_channel1_full_n == ap_const_logic_1))) begin
ap_reg_ready_img_0_cols_V_channel1_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_0_cols_V_channel_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_0_cols_V_channel_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_0_cols_V_channel_full_n))) begin
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_0_rows_V_channel1_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_0_rows_V_channel1_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_0_rows_V_channel1_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_0_rows_V_channel1_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_0_rows_V_channel1_full_n))) begin
ap_reg_ready_img_0_rows_V_channel1_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_0_rows_V_channel_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_0_rows_V_channel_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_0_rows_V_channel_full_n))) begin
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_1_cols_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_1_cols_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_1_cols_V_full_n))) begin
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_1_rows_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_1_rows_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_1_rows_V_full_n))) begin
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_2_cols_V_channel_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_2_cols_V_channel_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_2_cols_V_channel_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_2_cols_V_channel_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_2_cols_V_channel_full_n))) begin
ap_reg_ready_img_2_cols_V_channel_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_2_cols_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_2_cols_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_2_cols_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_2_cols_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_2_cols_V_full_n))) begin
ap_reg_ready_img_2_cols_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_2_rows_V_channel_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_2_rows_V_channel_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_2_rows_V_channel_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_2_rows_V_channel_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_2_rows_V_channel_full_n))) begin
ap_reg_ready_img_2_rows_V_channel_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_2_rows_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_2_rows_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_2_rows_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_2_rows_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_2_rows_V_full_n))) begin
ap_reg_ready_img_2_rows_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_3_cols_V_channel_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_3_cols_V_channel_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_3_cols_V_channel_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_3_cols_V_channel_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_3_cols_V_channel_full_n))) begin
ap_reg_ready_img_3_cols_V_channel_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_3_cols_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_3_cols_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_3_cols_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_3_cols_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_3_cols_V_full_n))) begin
ap_reg_ready_img_3_cols_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_3_rows_V_channel_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_3_rows_V_channel_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_3_rows_V_channel_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_3_rows_V_channel_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_3_rows_V_channel_full_n))) begin
ap_reg_ready_img_3_rows_V_channel_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_3_rows_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_3_rows_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_3_rows_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_3_rows_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_3_rows_V_full_n))) begin
ap_reg_ready_img_3_rows_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_4_cols_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_4_cols_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_4_cols_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_4_cols_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_4_cols_V_full_n))) begin
ap_reg_ready_img_4_cols_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_4_rows_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_4_rows_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_4_rows_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_4_rows_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_4_rows_V_full_n))) begin
ap_reg_ready_img_4_rows_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_5_cols_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_5_cols_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_5_cols_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_5_cols_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_5_cols_V_full_n))) begin
ap_reg_ready_img_5_cols_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_5_rows_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_5_rows_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_5_rows_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_5_rows_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_5_rows_V_full_n))) begin
ap_reg_ready_img_5_rows_V_full_n <= ap_const_logic_1;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
ap_CS <= ap_const_logic_0;
end
/// ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_0_cols_V_channel_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel1 assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_0_cols_V_channel1_full_n)
begin
if ((ap_reg_ready_img_0_cols_V_channel1_full_n == ap_const_logic_1)) begin
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel1 = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel1 = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_0_rows_V_channel_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel1 assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_0_rows_V_channel1_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_0_rows_V_channel1_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel1 = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel1 = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_1_cols_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_1_rows_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_2_cols_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_2_cols_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V_channel assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_2_cols_V_channel_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_2_cols_V_channel_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V_channel = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V_channel = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_2_rows_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_2_rows_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V_channel assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_2_rows_V_channel_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_2_rows_V_channel_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V_channel = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V_channel = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_3_cols_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_3_cols_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V_channel assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_3_cols_V_channel_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_3_cols_V_channel_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V_channel = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V_channel = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_3_rows_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_3_rows_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V_channel assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_3_rows_V_channel_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_3_rows_V_channel_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V_channel = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V_channel = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_4_cols_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_4_cols_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_4_cols_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_4_cols_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_4_cols_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_4_rows_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_4_rows_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_4_rows_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_4_rows_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_4_rows_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_5_cols_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_5_cols_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_5_cols_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_5_cols_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_5_cols_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_5_rows_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_5_rows_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_5_rows_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_5_rows_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_5_rows_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_idle assign process. ///
always @ (image_filter_Block_proc_U0_ap_idle or image_filter_AXIvideo2Mat_U0_ap_idle or image_filter_Sobel_U0_ap_idle or image_filter_SubS_U0_ap_idle or image_filter_Scale_1080_1920_32_32_int_U0_ap_idle or image_filter_Erode_32_32_1080_1920_U0_ap_idle or image_filter_Dilate_32_32_1080_1920_U0_ap_idle or image_filter_Mat2AXIvideo_U0_ap_idle or img_0_rows_V_channel_empty_n or img_0_rows_V_channel1_empty_n or img_0_cols_V_channel_empty_n or img_0_cols_V_channel1_empty_n or img_1_rows_V_empty_n or img_1_cols_V_empty_n or img_2_rows_V_empty_n or img_2_rows_V_channel_empty_n or img_2_cols_V_empty_n or img_2_cols_V_channel_empty_n or img_3_rows_V_empty_n or img_3_rows_V_channel_empty_n or img_3_cols_V_empty_n or img_3_cols_V_channel_empty_n or img_4_rows_V_empty_n or img_4_cols_V_empty_n or img_5_rows_V_empty_n or img_5_cols_V_empty_n)
begin
if (((image_filter_Block_proc_U0_ap_idle == ap_const_logic_1) & (ap_const_logic_1 == image_filter_AXIvideo2Mat_U0_ap_idle) & (ap_const_logic_1 == image_filter_Sobel_U0_ap_idle) & (ap_const_logic_1 == image_filter_SubS_U0_ap_idle) & (ap_const_logic_1 == image_filter_Scale_1080_1920_32_32_int_U0_ap_idle) & (ap_const_logic_1 == image_filter_Erode_32_32_1080_1920_U0_ap_idle) & (ap_const_logic_1 == image_filter_Dilate_32_32_1080_1920_U0_ap_idle) & (ap_const_logic_1 == image_filter_Mat2AXIvideo_U0_ap_idle) & (ap_const_logic_0 == img_0_rows_V_channel_empty_n) & (ap_const_logic_0 == img_0_rows_V_channel1_empty_n) & (ap_const_logic_0 == img_0_cols_V_channel_empty_n) & (ap_const_logic_0 == img_0_cols_V_channel1_empty_n) & (ap_const_logic_0 == img_1_rows_V_empty_n) & (ap_const_logic_0 == img_1_cols_V_empty_n) & (ap_const_logic_0 == img_2_rows_V_empty_n) & (ap_const_logic_0 == img_2_rows_V_channel_empty_n) & (ap_const_logic_0 == img_2_cols_V_empty_n) & (ap_const_logic_0 == img_2_cols_V_channel_empty_n) & (ap_const_logic_0 == img_3_rows_V_empty_n) & (ap_const_logic_0 == img_3_rows_V_channel_empty_n) & (ap_const_logic_0 == img_3_cols_V_empty_n) & (ap_const_logic_0 == img_3_cols_V_channel_empty_n) & (ap_const_logic_0 == img_4_rows_V_empty_n) & (ap_const_logic_0 == img_4_cols_V_empty_n) & (ap_const_logic_0 == img_5_rows_V_empty_n) & (ap_const_logic_0 == img_5_cols_V_empty_n))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_sig_hs_done assign process. ///
always @ (image_filter_Mat2AXIvideo_U0_ap_done)
begin
if ((ap_const_logic_1 == image_filter_Mat2AXIvideo_U0_ap_done)) begin
ap_sig_hs_done = ap_const_logic_1;
end else begin
ap_sig_hs_done = ap_const_logic_0;
end
end
/// ap_sig_ready_img_0_cols_V_channel1_full_n assign process. ///
always @ (img_0_cols_V_channel1_full_n or ap_reg_ready_img_0_cols_V_channel1_full_n)
begin
if ((ap_reg_ready_img_0_cols_V_channel1_full_n == ap_const_logic_0)) begin
ap_sig_ready_img_0_cols_V_channel1_full_n = img_0_cols_V_channel1_full_n;
end else begin
ap_sig_ready_img_0_cols_V_channel1_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_0_cols_V_channel_full_n assign process. ///
always @ (img_0_cols_V_channel_full_n or ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_0_cols_V_channel_full_n)) begin
ap_sig_ready_img_0_cols_V_channel_full_n = img_0_cols_V_channel_full_n;
end else begin
ap_sig_ready_img_0_cols_V_channel_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_0_rows_V_channel1_full_n assign process. ///
always @ (img_0_rows_V_channel1_full_n or ap_reg_ready_img_0_rows_V_channel1_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_0_rows_V_channel1_full_n)) begin
ap_sig_ready_img_0_rows_V_channel1_full_n = img_0_rows_V_channel1_full_n;
end else begin
ap_sig_ready_img_0_rows_V_channel1_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_0_rows_V_channel_full_n assign process. ///
always @ (img_0_rows_V_channel_full_n or ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_0_rows_V_channel_full_n)) begin
ap_sig_ready_img_0_rows_V_channel_full_n = img_0_rows_V_channel_full_n;
end else begin
ap_sig_ready_img_0_rows_V_channel_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_1_cols_V_full_n assign process. ///
always @ (img_1_cols_V_full_n or ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_1_cols_V_full_n)) begin
ap_sig_ready_img_1_cols_V_full_n = img_1_cols_V_full_n;
end else begin
ap_sig_ready_img_1_cols_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_1_rows_V_full_n assign process. ///
always @ (img_1_rows_V_full_n or ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_1_rows_V_full_n)) begin
ap_sig_ready_img_1_rows_V_full_n = img_1_rows_V_full_n;
end else begin
ap_sig_ready_img_1_rows_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_2_cols_V_channel_full_n assign process. ///
always @ (img_2_cols_V_channel_full_n or ap_reg_ready_img_2_cols_V_channel_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_2_cols_V_channel_full_n)) begin
ap_sig_ready_img_2_cols_V_channel_full_n = img_2_cols_V_channel_full_n;
end else begin
ap_sig_ready_img_2_cols_V_channel_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_2_cols_V_full_n assign process. ///
always @ (img_2_cols_V_full_n or ap_reg_ready_img_2_cols_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_2_cols_V_full_n)) begin
ap_sig_ready_img_2_cols_V_full_n = img_2_cols_V_full_n;
end else begin
ap_sig_ready_img_2_cols_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_2_rows_V_channel_full_n assign process. ///
always @ (img_2_rows_V_channel_full_n or ap_reg_ready_img_2_rows_V_channel_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_2_rows_V_channel_full_n)) begin
ap_sig_ready_img_2_rows_V_channel_full_n = img_2_rows_V_channel_full_n;
end else begin
ap_sig_ready_img_2_rows_V_channel_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_2_rows_V_full_n assign process. ///
always @ (img_2_rows_V_full_n or ap_reg_ready_img_2_rows_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_2_rows_V_full_n)) begin
ap_sig_ready_img_2_rows_V_full_n = img_2_rows_V_full_n;
end else begin
ap_sig_ready_img_2_rows_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_3_cols_V_channel_full_n assign process. ///
always @ (img_3_cols_V_channel_full_n or ap_reg_ready_img_3_cols_V_channel_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_3_cols_V_channel_full_n)) begin
ap_sig_ready_img_3_cols_V_channel_full_n = img_3_cols_V_channel_full_n;
end else begin
ap_sig_ready_img_3_cols_V_channel_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_3_cols_V_full_n assign process. ///
always @ (img_3_cols_V_full_n or ap_reg_ready_img_3_cols_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_3_cols_V_full_n)) begin
ap_sig_ready_img_3_cols_V_full_n = img_3_cols_V_full_n;
end else begin
ap_sig_ready_img_3_cols_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_3_rows_V_channel_full_n assign process. ///
always @ (img_3_rows_V_channel_full_n or ap_reg_ready_img_3_rows_V_channel_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_3_rows_V_channel_full_n)) begin
ap_sig_ready_img_3_rows_V_channel_full_n = img_3_rows_V_channel_full_n;
end else begin
ap_sig_ready_img_3_rows_V_channel_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_3_rows_V_full_n assign process. ///
always @ (img_3_rows_V_full_n or ap_reg_ready_img_3_rows_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_3_rows_V_full_n)) begin
ap_sig_ready_img_3_rows_V_full_n = img_3_rows_V_full_n;
end else begin
ap_sig_ready_img_3_rows_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_4_cols_V_full_n assign process. ///
always @ (img_4_cols_V_full_n or ap_reg_ready_img_4_cols_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_4_cols_V_full_n)) begin
ap_sig_ready_img_4_cols_V_full_n = img_4_cols_V_full_n;
end else begin
ap_sig_ready_img_4_cols_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_4_rows_V_full_n assign process. ///
always @ (img_4_rows_V_full_n or ap_reg_ready_img_4_rows_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_4_rows_V_full_n)) begin
ap_sig_ready_img_4_rows_V_full_n = img_4_rows_V_full_n;
end else begin
ap_sig_ready_img_4_rows_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_5_cols_V_full_n assign process. ///
always @ (img_5_cols_V_full_n or ap_reg_ready_img_5_cols_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_5_cols_V_full_n)) begin
ap_sig_ready_img_5_cols_V_full_n = img_5_cols_V_full_n;
end else begin
ap_sig_ready_img_5_cols_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_5_rows_V_full_n assign process. ///
always @ (img_5_rows_V_full_n or ap_reg_ready_img_5_rows_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_5_rows_V_full_n)) begin
ap_sig_ready_img_5_rows_V_full_n = img_5_rows_V_full_n;
end else begin
ap_sig_ready_img_5_rows_V_full_n = ap_const_logic_1;
end
end
/// image_filter_Block_proc_U0_ap_continue assign process. ///
always @ (ap_sig_ready_img_0_cols_V_channel1_full_n or ap_sig_ready_img_0_rows_V_channel_full_n or ap_sig_ready_img_0_rows_V_channel1_full_n or ap_sig_ready_img_0_cols_V_channel_full_n or ap_sig_ready_img_1_rows_V_full_n or ap_sig_ready_img_1_cols_V_full_n or ap_sig_ready_img_2_rows_V_full_n or ap_sig_ready_img_2_rows_V_channel_full_n or ap_sig_ready_img_2_cols_V_full_n or ap_sig_ready_img_2_cols_V_channel_full_n or ap_sig_ready_img_3_rows_V_full_n or ap_sig_ready_img_3_rows_V_channel_full_n or ap_sig_ready_img_3_cols_V_full_n or ap_sig_ready_img_3_cols_V_channel_full_n or ap_sig_ready_img_4_rows_V_full_n or ap_sig_ready_img_4_cols_V_full_n or ap_sig_ready_img_5_rows_V_full_n or ap_sig_ready_img_5_cols_V_full_n)
begin
if (((ap_sig_ready_img_0_cols_V_channel1_full_n == ap_const_logic_1) & (ap_const_logic_1 == ap_sig_ready_img_0_rows_V_channel_full_n) & (ap_const_logic_1 == ap_sig_ready_img_0_rows_V_channel1_full_n) & (ap_const_logic_1 == ap_sig_ready_img_0_cols_V_channel_full_n) & (ap_const_logic_1 == ap_sig_ready_img_1_rows_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_1_cols_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_2_rows_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_2_rows_V_channel_full_n) & (ap_const_logic_1 == ap_sig_ready_img_2_cols_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_2_cols_V_channel_full_n) & (ap_const_logic_1 == ap_sig_ready_img_3_rows_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_3_rows_V_channel_full_n) & (ap_const_logic_1 == ap_sig_ready_img_3_cols_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_3_cols_V_channel_full_n) & (ap_const_logic_1 == ap_sig_ready_img_4_rows_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_4_cols_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_5_rows_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_5_cols_V_full_n))) begin
image_filter_Block_proc_U0_ap_continue = ap_const_logic_1;
end else begin
image_filter_Block_proc_U0_ap_continue = ap_const_logic_0;
end
end
assign INPUT_STREAM_TREADY = image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY;
assign OUTPUT_STREAM_TDATA = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA;
assign OUTPUT_STREAM_TDEST = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST;
assign OUTPUT_STREAM_TID = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID;
assign OUTPUT_STREAM_TKEEP = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP;
assign OUTPUT_STREAM_TLAST = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST;
assign OUTPUT_STREAM_TSTRB = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB;
assign OUTPUT_STREAM_TUSER = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER;
assign OUTPUT_STREAM_TVALID = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID;
assign ap_done = ap_sig_hs_done;
assign ap_ready = ap_sig_top_allready;
/// ap_rst_n_inv assign process. ///
always @ (ap_rst_n)
begin
ap_rst_n_inv = ~ap_rst_n;
end
assign ap_sig_hs_continue = ap_const_logic_1;
assign ap_sig_top_allready = image_filter_AXIvideo2Mat_U0_ap_ready;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA = INPUT_STREAM_TDATA;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST = INPUT_STREAM_TDEST;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID = INPUT_STREAM_TID;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP = INPUT_STREAM_TKEEP;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST = INPUT_STREAM_TLAST;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB = INPUT_STREAM_TSTRB;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER = INPUT_STREAM_TUSER;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID = INPUT_STREAM_TVALID;
assign image_filter_AXIvideo2Mat_U0_ap_continue = ap_const_logic_1;
assign image_filter_AXIvideo2Mat_U0_ap_start = (ap_start & img_0_rows_V_channel_empty_n & img_0_cols_V_channel_empty_n);
assign image_filter_AXIvideo2Mat_U0_img_cols_V_read = img_0_cols_V_channel_dout;
assign image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n = img_0_data_stream_0_V_full_n;
assign image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n = img_0_data_stream_1_V_full_n;
assign image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n = img_0_data_stream_2_V_full_n;
assign image_filter_AXIvideo2Mat_U0_img_rows_V_read = img_0_rows_V_channel_dout;
assign image_filter_Block_proc_U0_ap_start = ap_start;
assign image_filter_Block_proc_U0_cols = cols;
assign image_filter_Block_proc_U0_rows = rows;
assign image_filter_Dilate_32_32_1080_1920_U0_ap_continue = ap_const_logic_1;
assign image_filter_Dilate_32_32_1080_1920_U0_ap_start = (img_4_rows_V_empty_n & img_4_cols_V_empty_n);
assign image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_0_V_full_n = img_5_data_stream_0_V_full_n;
assign image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_1_V_full_n = img_5_data_stream_1_V_full_n;
assign image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_2_V_full_n = img_5_data_stream_2_V_full_n;
assign image_filter_Dilate_32_32_1080_1920_U0_p_src_cols_V_read = img_4_cols_V_dout;
assign image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_0_V_dout = img_4_data_stream_0_V_dout;
assign image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_0_V_empty_n = img_4_data_stream_0_V_empty_n;
assign image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_1_V_dout = img_4_data_stream_1_V_dout;
assign image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_1_V_empty_n = img_4_data_stream_1_V_empty_n;
assign image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_2_V_dout = img_4_data_stream_2_V_dout;
assign image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_2_V_empty_n = img_4_data_stream_2_V_empty_n;
assign image_filter_Dilate_32_32_1080_1920_U0_p_src_rows_V_read = img_4_rows_V_dout;
assign image_filter_Erode_32_32_1080_1920_U0_ap_continue = ap_const_logic_1;
assign image_filter_Erode_32_32_1080_1920_U0_ap_start = (img_3_rows_V_channel_empty_n & img_3_cols_V_channel_empty_n);
assign image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_0_V_full_n = img_4_data_stream_0_V_full_n;
assign image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_1_V_full_n = img_4_data_stream_1_V_full_n;
assign image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_2_V_full_n = img_4_data_stream_2_V_full_n;
assign image_filter_Erode_32_32_1080_1920_U0_p_src_cols_V_read = img_3_cols_V_channel_dout;
assign image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_0_V_dout = img_3_data_stream_0_V_dout;
assign image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_0_V_empty_n = img_3_data_stream_0_V_empty_n;
assign image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_1_V_dout = img_3_data_stream_1_V_dout;
assign image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_1_V_empty_n = img_3_data_stream_1_V_empty_n;
assign image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_2_V_dout = img_3_data_stream_2_V_dout;
assign image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_2_V_empty_n = img_3_data_stream_2_V_empty_n;
assign image_filter_Erode_32_32_1080_1920_U0_p_src_rows_V_read = img_3_rows_V_channel_dout;
assign image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY = OUTPUT_STREAM_TREADY;
assign image_filter_Mat2AXIvideo_U0_ap_continue = ap_sig_hs_continue;
assign image_filter_Mat2AXIvideo_U0_ap_start = (img_5_rows_V_empty_n & img_5_cols_V_empty_n);
assign image_filter_Mat2AXIvideo_U0_img_cols_V_read = img_5_cols_V_dout;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout = img_5_data_stream_0_V_dout;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n = img_5_data_stream_0_V_empty_n;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout = img_5_data_stream_1_V_dout;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n = img_5_data_stream_1_V_empty_n;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout = img_5_data_stream_2_V_dout;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n = img_5_data_stream_2_V_empty_n;
assign image_filter_Mat2AXIvideo_U0_img_rows_V_read = img_5_rows_V_dout;
assign image_filter_Scale_1080_1920_32_32_int_U0_ap_continue = ap_const_logic_1;
assign image_filter_Scale_1080_1920_32_32_int_U0_ap_start = (img_2_rows_V_channel_empty_n & img_2_cols_V_channel_empty_n & img_3_rows_V_empty_n & img_3_cols_V_empty_n);
assign image_filter_Scale_1080_1920_32_32_int_U0_dst_cols_V_read = img_3_cols_V_dout;
assign image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_0_V_full_n = img_3_data_stream_0_V_full_n;
assign image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_1_V_full_n = img_3_data_stream_1_V_full_n;
assign image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_2_V_full_n = img_3_data_stream_2_V_full_n;
assign image_filter_Scale_1080_1920_32_32_int_U0_dst_rows_V_read = img_3_rows_V_dout;
assign image_filter_Scale_1080_1920_32_32_int_U0_src_cols_V_read = img_2_cols_V_channel_dout;
assign image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_0_V_dout = img_2_data_stream_0_V_dout;
assign image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_0_V_empty_n = img_2_data_stream_0_V_empty_n;
assign image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_1_V_dout = img_2_data_stream_1_V_dout;
assign image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_1_V_empty_n = img_2_data_stream_1_V_empty_n;
assign image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_2_V_dout = img_2_data_stream_2_V_dout;
assign image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_2_V_empty_n = img_2_data_stream_2_V_empty_n;
assign image_filter_Scale_1080_1920_32_32_int_U0_src_rows_V_read = img_2_rows_V_channel_dout;
assign image_filter_Sobel_U0_ap_continue = ap_const_logic_1;
assign image_filter_Sobel_U0_ap_start = (img_0_rows_V_channel1_empty_n & img_0_cols_V_channel1_empty_n);
assign image_filter_Sobel_U0_p_dst_data_stream_0_V_full_n = img_1_data_stream_0_V_full_n;
assign image_filter_Sobel_U0_p_dst_data_stream_1_V_full_n = img_1_data_stream_1_V_full_n;
assign image_filter_Sobel_U0_p_dst_data_stream_2_V_full_n = img_1_data_stream_2_V_full_n;
assign image_filter_Sobel_U0_p_src_cols_V_read = img_0_cols_V_channel1_dout;
assign image_filter_Sobel_U0_p_src_data_stream_0_V_dout = img_0_data_stream_0_V_dout;
assign image_filter_Sobel_U0_p_src_data_stream_0_V_empty_n = img_0_data_stream_0_V_empty_n;
assign image_filter_Sobel_U0_p_src_data_stream_1_V_dout = img_0_data_stream_1_V_dout;
assign image_filter_Sobel_U0_p_src_data_stream_1_V_empty_n = img_0_data_stream_1_V_empty_n;
assign image_filter_Sobel_U0_p_src_data_stream_2_V_dout = img_0_data_stream_2_V_dout;
assign image_filter_Sobel_U0_p_src_data_stream_2_V_empty_n = img_0_data_stream_2_V_empty_n;
assign image_filter_Sobel_U0_p_src_rows_V_read = img_0_rows_V_channel1_dout;
assign image_filter_SubS_U0_ap_continue = ap_const_logic_1;
assign image_filter_SubS_U0_ap_start = (img_1_rows_V_empty_n & img_1_cols_V_empty_n & img_2_rows_V_empty_n & img_2_cols_V_empty_n);
assign image_filter_SubS_U0_dst_cols_V_read = img_2_cols_V_dout;
assign image_filter_SubS_U0_dst_data_stream_0_V_full_n = img_2_data_stream_0_V_full_n;
assign image_filter_SubS_U0_dst_data_stream_1_V_full_n = img_2_data_stream_1_V_full_n;
assign image_filter_SubS_U0_dst_data_stream_2_V_full_n = img_2_data_stream_2_V_full_n;
assign image_filter_SubS_U0_dst_rows_V_read = img_2_rows_V_dout;
assign image_filter_SubS_U0_src_cols_V_read = img_1_cols_V_dout;
assign image_filter_SubS_U0_src_data_stream_0_V_dout = img_1_data_stream_0_V_dout;
assign image_filter_SubS_U0_src_data_stream_0_V_empty_n = img_1_data_stream_0_V_empty_n;
assign image_filter_SubS_U0_src_data_stream_1_V_dout = img_1_data_stream_1_V_dout;
assign image_filter_SubS_U0_src_data_stream_1_V_empty_n = img_1_data_stream_1_V_empty_n;
assign image_filter_SubS_U0_src_data_stream_2_V_dout = img_1_data_stream_2_V_dout;
assign image_filter_SubS_U0_src_data_stream_2_V_empty_n = img_1_data_stream_2_V_empty_n;
assign image_filter_SubS_U0_src_rows_V_read = img_1_rows_V_dout;
assign img_0_cols_V_channel1_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_cols_V_channel1_din = image_filter_Block_proc_U0_ap_return_3;
assign img_0_cols_V_channel1_read = image_filter_Sobel_U0_ap_ready;
assign img_0_cols_V_channel1_write = ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel1;
assign img_0_cols_V_channel_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_cols_V_channel_din = image_filter_Block_proc_U0_ap_return_2;
assign img_0_cols_V_channel_read = image_filter_AXIvideo2Mat_U0_ap_ready;
assign img_0_cols_V_channel_write = ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel;
assign img_0_data_stream_0_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_data_stream_0_V_din = image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din;
assign img_0_data_stream_0_V_read = image_filter_Sobel_U0_p_src_data_stream_0_V_read;
assign img_0_data_stream_0_V_write = image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write;
assign img_0_data_stream_1_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_data_stream_1_V_din = image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din;
assign img_0_data_stream_1_V_read = image_filter_Sobel_U0_p_src_data_stream_1_V_read;
assign img_0_data_stream_1_V_write = image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write;
assign img_0_data_stream_2_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_data_stream_2_V_din = image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din;
assign img_0_data_stream_2_V_read = image_filter_Sobel_U0_p_src_data_stream_2_V_read;
assign img_0_data_stream_2_V_write = image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write;
assign img_0_rows_V_channel1_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_rows_V_channel1_din = image_filter_Block_proc_U0_ap_return_1;
assign img_0_rows_V_channel1_read = image_filter_Sobel_U0_ap_ready;
assign img_0_rows_V_channel1_write = ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel1;
assign img_0_rows_V_channel_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_rows_V_channel_din = image_filter_Block_proc_U0_ap_return_0;
assign img_0_rows_V_channel_read = image_filter_AXIvideo2Mat_U0_ap_ready;
assign img_0_rows_V_channel_write = ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel;
assign img_1_cols_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_cols_V_din = image_filter_Block_proc_U0_ap_return_5;
assign img_1_cols_V_read = image_filter_SubS_U0_ap_ready;
assign img_1_cols_V_write = ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V;
assign img_1_data_stream_0_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_data_stream_0_V_din = image_filter_Sobel_U0_p_dst_data_stream_0_V_din;
assign img_1_data_stream_0_V_read = image_filter_SubS_U0_src_data_stream_0_V_read;
assign img_1_data_stream_0_V_write = image_filter_Sobel_U0_p_dst_data_stream_0_V_write;
assign img_1_data_stream_1_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_data_stream_1_V_din = image_filter_Sobel_U0_p_dst_data_stream_1_V_din;
assign img_1_data_stream_1_V_read = image_filter_SubS_U0_src_data_stream_1_V_read;
assign img_1_data_stream_1_V_write = image_filter_Sobel_U0_p_dst_data_stream_1_V_write;
assign img_1_data_stream_2_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_data_stream_2_V_din = image_filter_Sobel_U0_p_dst_data_stream_2_V_din;
assign img_1_data_stream_2_V_read = image_filter_SubS_U0_src_data_stream_2_V_read;
assign img_1_data_stream_2_V_write = image_filter_Sobel_U0_p_dst_data_stream_2_V_write;
assign img_1_rows_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_rows_V_din = image_filter_Block_proc_U0_ap_return_4;
assign img_1_rows_V_read = image_filter_SubS_U0_ap_ready;
assign img_1_rows_V_write = ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V;
assign img_2_cols_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_2_cols_V_channel_U_ap_dummy_ce = ap_const_logic_1;
assign img_2_cols_V_channel_din = image_filter_Block_proc_U0_ap_return_9;
assign img_2_cols_V_channel_read = image_filter_Scale_1080_1920_32_32_int_U0_ap_ready;
assign img_2_cols_V_channel_write = ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V_channel;
assign img_2_cols_V_din = image_filter_Block_proc_U0_ap_return_8;
assign img_2_cols_V_read = image_filter_SubS_U0_ap_ready;
assign img_2_cols_V_write = ap_chn_write_image_filter_Block_proc_U0_img_2_cols_V;
assign img_2_data_stream_0_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_2_data_stream_0_V_din = image_filter_SubS_U0_dst_data_stream_0_V_din;
assign img_2_data_stream_0_V_read = image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_0_V_read;
assign img_2_data_stream_0_V_write = image_filter_SubS_U0_dst_data_stream_0_V_write;
assign img_2_data_stream_1_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_2_data_stream_1_V_din = image_filter_SubS_U0_dst_data_stream_1_V_din;
assign img_2_data_stream_1_V_read = image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_1_V_read;
assign img_2_data_stream_1_V_write = image_filter_SubS_U0_dst_data_stream_1_V_write;
assign img_2_data_stream_2_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_2_data_stream_2_V_din = image_filter_SubS_U0_dst_data_stream_2_V_din;
assign img_2_data_stream_2_V_read = image_filter_Scale_1080_1920_32_32_int_U0_src_data_stream_2_V_read;
assign img_2_data_stream_2_V_write = image_filter_SubS_U0_dst_data_stream_2_V_write;
assign img_2_rows_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_2_rows_V_channel_U_ap_dummy_ce = ap_const_logic_1;
assign img_2_rows_V_channel_din = image_filter_Block_proc_U0_ap_return_7;
assign img_2_rows_V_channel_read = image_filter_Scale_1080_1920_32_32_int_U0_ap_ready;
assign img_2_rows_V_channel_write = ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V_channel;
assign img_2_rows_V_din = image_filter_Block_proc_U0_ap_return_6;
assign img_2_rows_V_read = image_filter_SubS_U0_ap_ready;
assign img_2_rows_V_write = ap_chn_write_image_filter_Block_proc_U0_img_2_rows_V;
assign img_3_cols_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_3_cols_V_channel_U_ap_dummy_ce = ap_const_logic_1;
assign img_3_cols_V_channel_din = image_filter_Block_proc_U0_ap_return_13;
assign img_3_cols_V_channel_read = image_filter_Erode_32_32_1080_1920_U0_ap_ready;
assign img_3_cols_V_channel_write = ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V_channel;
assign img_3_cols_V_din = image_filter_Block_proc_U0_ap_return_12;
assign img_3_cols_V_read = image_filter_Scale_1080_1920_32_32_int_U0_ap_ready;
assign img_3_cols_V_write = ap_chn_write_image_filter_Block_proc_U0_img_3_cols_V;
assign img_3_data_stream_0_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_3_data_stream_0_V_din = image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_0_V_din;
assign img_3_data_stream_0_V_read = image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_0_V_read;
assign img_3_data_stream_0_V_write = image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_0_V_write;
assign img_3_data_stream_1_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_3_data_stream_1_V_din = image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_1_V_din;
assign img_3_data_stream_1_V_read = image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_1_V_read;
assign img_3_data_stream_1_V_write = image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_1_V_write;
assign img_3_data_stream_2_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_3_data_stream_2_V_din = image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_2_V_din;
assign img_3_data_stream_2_V_read = image_filter_Erode_32_32_1080_1920_U0_p_src_data_stream_2_V_read;
assign img_3_data_stream_2_V_write = image_filter_Scale_1080_1920_32_32_int_U0_dst_data_stream_2_V_write;
assign img_3_rows_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_3_rows_V_channel_U_ap_dummy_ce = ap_const_logic_1;
assign img_3_rows_V_channel_din = image_filter_Block_proc_U0_ap_return_11;
assign img_3_rows_V_channel_read = image_filter_Erode_32_32_1080_1920_U0_ap_ready;
assign img_3_rows_V_channel_write = ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V_channel;
assign img_3_rows_V_din = image_filter_Block_proc_U0_ap_return_10;
assign img_3_rows_V_read = image_filter_Scale_1080_1920_32_32_int_U0_ap_ready;
assign img_3_rows_V_write = ap_chn_write_image_filter_Block_proc_U0_img_3_rows_V;
assign img_4_cols_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_4_cols_V_din = image_filter_Block_proc_U0_ap_return_15;
assign img_4_cols_V_read = image_filter_Dilate_32_32_1080_1920_U0_ap_ready;
assign img_4_cols_V_write = ap_chn_write_image_filter_Block_proc_U0_img_4_cols_V;
assign img_4_data_stream_0_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_4_data_stream_0_V_din = image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_0_V_din;
assign img_4_data_stream_0_V_read = image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_0_V_read;
assign img_4_data_stream_0_V_write = image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_0_V_write;
assign img_4_data_stream_1_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_4_data_stream_1_V_din = image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_1_V_din;
assign img_4_data_stream_1_V_read = image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_1_V_read;
assign img_4_data_stream_1_V_write = image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_1_V_write;
assign img_4_data_stream_2_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_4_data_stream_2_V_din = image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_2_V_din;
assign img_4_data_stream_2_V_read = image_filter_Dilate_32_32_1080_1920_U0_p_src_data_stream_2_V_read;
assign img_4_data_stream_2_V_write = image_filter_Erode_32_32_1080_1920_U0_p_dst_data_stream_2_V_write;
assign img_4_rows_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_4_rows_V_din = image_filter_Block_proc_U0_ap_return_14;
assign img_4_rows_V_read = image_filter_Dilate_32_32_1080_1920_U0_ap_ready;
assign img_4_rows_V_write = ap_chn_write_image_filter_Block_proc_U0_img_4_rows_V;
assign img_5_cols_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_5_cols_V_din = image_filter_Block_proc_U0_ap_return_17;
assign img_5_cols_V_read = image_filter_Mat2AXIvideo_U0_ap_ready;
assign img_5_cols_V_write = ap_chn_write_image_filter_Block_proc_U0_img_5_cols_V;
assign img_5_data_stream_0_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_5_data_stream_0_V_din = image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_0_V_din;
assign img_5_data_stream_0_V_read = image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read;
assign img_5_data_stream_0_V_write = image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_0_V_write;
assign img_5_data_stream_1_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_5_data_stream_1_V_din = image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_1_V_din;
assign img_5_data_stream_1_V_read = image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read;
assign img_5_data_stream_1_V_write = image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_1_V_write;
assign img_5_data_stream_2_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_5_data_stream_2_V_din = image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_2_V_din;
assign img_5_data_stream_2_V_read = image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read;
assign img_5_data_stream_2_V_write = image_filter_Dilate_32_32_1080_1920_U0_p_dst_data_stream_2_V_write;
assign img_5_rows_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_5_rows_V_din = image_filter_Block_proc_U0_ap_return_16;
assign img_5_rows_V_read = image_filter_Mat2AXIvideo_U0_ap_ready;
assign img_5_rows_V_write = ap_chn_write_image_filter_Block_proc_U0_img_5_rows_V;
endmodule //image_filter
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:04:57 EST 2014
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 32 reg
// wsiM0_MByteEn O 4 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 32
// wsiS0_MByteEn I 4
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkBiasWorker4B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n);
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [31 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [3 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [31 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [3 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// signals for module outputs
wire [31 : 0] wciS0_SData, wsiM0_MData;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [3 : 0] wsiM0_MByteEn;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [95 : 0] wsiM_extStatusW_wget, wsiS_extStatusW_wget;
wire [71 : 0] wci_wslv_wciReq_wget;
wire [60 : 0] wsiM_reqFifo_x_wire_wget, wsiS_wsiReq_wget;
wire [33 : 0] wci_wslv_respF_x_wire_wget;
wire [31 : 0] wci_wci_Es_mAddr_w_wget,
wci_wci_Es_mData_w_wget,
wsi_Es_mData_w_wget;
wire [11 : 0] wsi_Es_mBurstLength_w_wget;
wire [7 : 0] wsi_Es_mReqInfo_w_wget;
wire [3 : 0] wci_wci_Es_mByteEn_w_wget, wsi_Es_mByteEn_w_wget;
wire [2 : 0] wci_wci_Es_mCmd_w_wget,
wci_wslv_wEdge_wget,
wsi_Es_mCmd_w_wget;
wire wci_wci_Es_mAddrSpace_w_wget,
wci_wci_Es_mAddrSpace_w_whas,
wci_wci_Es_mAddr_w_whas,
wci_wci_Es_mByteEn_w_whas,
wci_wci_Es_mCmd_w_whas,
wci_wci_Es_mData_w_whas,
wci_wslv_ctlAckReg_1_wget,
wci_wslv_ctlAckReg_1_whas,
wci_wslv_reqF_r_clr_whas,
wci_wslv_reqF_r_deq_whas,
wci_wslv_reqF_r_enq_whas,
wci_wslv_respF_dequeueing_whas,
wci_wslv_respF_enqueueing_whas,
wci_wslv_respF_x_wire_whas,
wci_wslv_sFlagReg_1_wget,
wci_wslv_sFlagReg_1_whas,
wci_wslv_sThreadBusy_pw_whas,
wci_wslv_wEdge_whas,
wci_wslv_wciReq_whas,
wci_wslv_wci_cfrd_pw_whas,
wci_wslv_wci_cfwr_pw_whas,
wci_wslv_wci_ctrl_pw_whas,
wsiM_operateD_1_wget,
wsiM_operateD_1_whas,
wsiM_peerIsReady_1_wget,
wsiM_peerIsReady_1_whas,
wsiM_reqFifo_dequeueing_whas,
wsiM_reqFifo_enqueueing_whas,
wsiM_reqFifo_x_wire_whas,
wsiM_sThreadBusy_pw_whas,
wsiS_operateD_1_wget,
wsiS_operateD_1_whas,
wsiS_peerIsReady_1_wget,
wsiS_peerIsReady_1_whas,
wsiS_reqFifo_doResetClr_whas,
wsiS_reqFifo_doResetDeq_whas,
wsiS_reqFifo_doResetEnq_whas,
wsiS_reqFifo_r_clr_whas,
wsiS_reqFifo_r_deq_whas,
wsiS_reqFifo_r_enq_whas,
wsiS_sThreadBusy_dw_wget,
wsiS_sThreadBusy_dw_whas,
wsiS_wsiReq_whas,
wsi_Es_mBurstLength_w_whas,
wsi_Es_mBurstPrecise_w_whas,
wsi_Es_mByteEn_w_whas,
wsi_Es_mCmd_w_whas,
wsi_Es_mDataInfo_w_whas,
wsi_Es_mData_w_whas,
wsi_Es_mReqInfo_w_whas,
wsi_Es_mReqLast_w_whas;
// register biasValue
reg [31 : 0] biasValue;
wire [31 : 0] biasValue_D_IN;
wire biasValue_EN;
// register controlReg
reg [31 : 0] controlReg;
wire [31 : 0] controlReg_D_IN;
wire controlReg_EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge_D_IN;
wire wci_wslv_cEdge_EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState_D_IN;
wire wci_wslv_cState_EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg_D_IN, wci_wslv_ctlAckReg_EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive_D_IN, wci_wslv_ctlOpActive_EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge_D_IN, wci_wslv_illegalEdge_EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset_D_IN, wci_wslv_isReset_isInReset_EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState_D_IN;
wire wci_wslv_nState_EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg_D_IN;
wire wci_wslv_reqF_countReg_EN;
// register wci_wslv_respF_cntr_r
reg [1 : 0] wci_wslv_respF_cntr_r;
wire [1 : 0] wci_wslv_respF_cntr_r_D_IN;
wire wci_wslv_respF_cntr_r_EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0_D_IN;
wire wci_wslv_respF_q_0_EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1_D_IN;
wire wci_wslv_respF_q_1_EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg_D_IN, wci_wslv_sFlagReg_EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d_D_IN, wci_wslv_sThreadBusy_d_EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind_D_IN;
wire wsiM_burstKind_EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky_D_IN, wsiM_errorSticky_EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount_D_IN;
wire wsiM_iMesgCount_EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset_D_IN, wsiM_isReset_isInReset_EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD_D_IN, wsiM_operateD_EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount_D_IN;
wire wsiM_pMesgCount_EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady_D_IN, wsiM_peerIsReady_EN;
// register wsiM_reqFifo_cntr_r
reg [1 : 0] wsiM_reqFifo_cntr_r;
wire [1 : 0] wsiM_reqFifo_cntr_r_D_IN;
wire wsiM_reqFifo_cntr_r_EN;
// register wsiM_reqFifo_q_0
reg [60 : 0] wsiM_reqFifo_q_0;
reg [60 : 0] wsiM_reqFifo_q_0_D_IN;
wire wsiM_reqFifo_q_0_EN;
// register wsiM_reqFifo_q_1
reg [60 : 0] wsiM_reqFifo_q_1;
reg [60 : 0] wsiM_reqFifo_q_1_D_IN;
wire wsiM_reqFifo_q_1_EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d_D_IN, wsiM_sThreadBusy_d_EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR_D_IN;
wire wsiM_statusR_EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount_D_IN;
wire wsiM_tBusyCount_EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky_D_IN, wsiM_trafficSticky_EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind_D_IN;
wire wsiS_burstKind_EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky_D_IN, wsiS_errorSticky_EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount_D_IN;
wire wsiS_iMesgCount_EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset_D_IN, wsiS_isReset_isInReset_EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength_D_IN;
wire wsiS_mesgWordLength_EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD_D_IN, wsiS_operateD_EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount_D_IN;
wire wsiS_pMesgCount_EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady_D_IN, wsiS_peerIsReady_EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg_D_IN;
wire wsiS_reqFifo_countReg_EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid_D_IN, wsiS_reqFifo_levelsValid_EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR_D_IN;
wire wsiS_statusR_EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount_D_IN;
wire wsiS_tBusyCount_EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky_D_IN, wsiS_trafficSticky_EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount_D_IN;
wire wsiS_wordCount_EN;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF_D_IN, wci_wslv_reqF_D_OUT;
wire wci_wslv_reqF_CLR,
wci_wslv_reqF_DEQ,
wci_wslv_reqF_EMPTY_N,
wci_wslv_reqF_ENQ;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo_D_IN, wsiS_reqFifo_D_OUT;
wire wsiS_reqFifo_CLR,
wsiS_reqFifo_DEQ,
wsiS_reqFifo_EMPTY_N,
wsiS_reqFifo_ENQ,
wsiS_reqFifo_FULL_N;
// rule scheduling signals
wire WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2;
wire [60 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1,
MUX_wsiM_reqFifo_q_0_write_1__VAL_2,
MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1,
MUX_wci_wslv_respF_q_1_write_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2;
wire MUX_biasValue_write_1__SEL_1,
MUX_biasValue_write_1__SEL_2,
MUX_controlReg_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__VAL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_2,
MUX_wci_wslv_respF_q_1_write_1__SEL_1,
MUX_wci_wslv_respF_q_1_write_1__SEL_2,
MUX_wsiM_reqFifo_q_0_write_1__SEL_1,
MUX_wsiM_reqFifo_q_0_write_1__SEL_2,
MUX_wsiM_reqFifo_q_1_write_1__SEL_1,
MUX_wsiM_reqFifo_q_1_write_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3;
// remaining internal signals
reg [63 : 0] v__h10632, v__h10787, v__h3574, v__h3749, v__h3893;
reg [31 : 0] _theResult____h10771;
wire [31 : 0] rdat__h10861,
rdat__h10961,
rdat__h10975,
rdat__h10983,
rdat__h10989,
rdat__h11003,
rdat__h11011,
x_data__h10099;
wire [15 : 0] x__h10865;
wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27;
wire _dfoo1, _dfoo3, _dfoo5, _dfoo7;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[43:12] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[11:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF_D_IN),
.ENQ(wci_wslv_reqF_ENQ),
.DEQ(wci_wslv_reqF_DEQ),
.CLR(wci_wslv_reqF_CLR),
.D_OUT(wci_wslv_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF_EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo_D_IN),
.ENQ(wsiS_reqFifo_ENQ),
.DEQ(wsiS_reqFifo_DEQ),
.CLR(wsiS_reqFifo_CLR),
.D_OUT(wsiS_reqFifo_D_OUT),
.FULL_N(wsiS_reqFifo_FULL_N),
.EMPTY_N(wsiS_reqFifo_EMPTY_N));
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd3 ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfrd_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_enqueueing_whas &&
!(wci_wslv_respF_cntr_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_cntr_r != 2'd0 &&
!wci_wslv_respF_enqueueing_whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_cntr_r != 2'd0 &&
wci_wslv_respF_enqueueing_whas ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
!MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo_FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq_wget[60:58] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// inputs to muxes for submodule ports
assign MUX_biasValue_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ;
assign MUX_biasValue_write_1__SEL_2 =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd0 ;
assign MUX_controlReg_write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ;
assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ;
assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 =
wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N &&
wci_wslv_cState == 3'd2 ;
assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 =
wci_wslv_reqF_D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 =
wci_wslv_respF_cntr_r + 2'd1 ;
assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd1) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd2) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 =
{ 2'd1, _theResult____h10771 } ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 =
{ wsiS_reqFifo_D_OUT[60:44],
x_data__h10099,
wsiS_reqFifo_D_OUT[11:0] } ;
assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
61'h00000AAAAAAAAA00 ;
// inlined wires
assign wci_wslv_wciReq_wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq_whas = 1'd1 ;
assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ;
assign wci_wslv_respF_x_wire_whas =
WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge_wget = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_wEdge_whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1_wget = 1'b0 ;
assign wci_wslv_sFlagReg_1_whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1_wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1_whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
MUX_biasValue_write_1__SEL_2 ;
assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_wci_Es_mAddr_w_wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_wci_Es_mData_w_wget = wciS0_MData ;
assign wci_wci_Es_mData_w_whas = 1'd1 ;
assign wsiS_wsiReq_wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq_whas = 1'd1 ;
assign wsiS_operateD_1_wget = 1'd1 ;
assign wsiS_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1_wget = 1'd1 ;
assign wsiS_peerIsReady_1_whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw_wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw_whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiM_operateD_1_wget = 1'd1 ;
assign wsiM_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1_wget = 1'd1 ;
assign wsiM_peerIsReady_1_whas = wsiM0_SReset_n ;
assign wsi_Es_mCmd_w_wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w_whas = 1'd1 ;
assign wsi_Es_mBurstLength_w_wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w_whas = 1'd1 ;
assign wsi_Es_mData_w_wget = wsiS0_MData ;
assign wsi_Es_mData_w_whas = 1'd1 ;
assign wsi_Es_mByteEn_w_wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w_whas = 1'd1 ;
assign wsi_Es_mReqInfo_w_wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w_whas = 1'd1 ;
assign wci_wslv_reqF_r_enq_whas = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr_whas = 1'b0 ;
assign wci_wslv_respF_enqueueing_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing_whas = wci_wslv_respF_cntr_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw_whas =
wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wsiS_reqFifo_r_enq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_r_clr_whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_doResetClr_whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiM_reqFifo_dequeueing_whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw_whas = wsiM0_SThreadBusy ;
assign wsi_Es_mReqLast_w_whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w_whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w_whas = 1'd1 ;
assign wsiS_extStatusW_wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign wsiM_extStatusW_wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register biasValue
assign biasValue_D_IN =
MUX_biasValue_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
32'd0 ;
assign biasValue_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ||
MUX_biasValue_write_1__SEL_2 ;
// register controlReg
assign controlReg_D_IN =
MUX_controlReg_write_1__SEL_1 ?
wci_wslv_reqF_D_OUT[31:0] :
32'd0 ;
assign controlReg_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h04 ||
MUX_biasValue_write_1__SEL_2 ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_cEdge_EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState_D_IN = wci_wslv_nState ;
assign wci_wslv_cState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg_D_IN = wci_wslv_ctlAckReg_1_whas ;
assign wci_wslv_ctlAckReg_EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge_D_IN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge_write_1__VAL_1 ;
assign wci_wslv_illegalEdge_EN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset_EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF_D_OUT)
begin
case (wci_wslv_reqF_D_OUT[36:34])
3'd0: wci_wslv_nState_D_IN = 3'd1;
3'd1: wci_wslv_nState_D_IN = 3'd2;
3'd2: wci_wslv_nState_D_IN = 3'd3;
default: wci_wslv_nState_D_IN = 3'd0;
endcase
end
assign wci_wslv_nState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg_D_IN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg_EN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq_whas ;
// register wci_wslv_respF_cntr_r
assign wci_wslv_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ?
wci_wslv_respF_cntr_r_8_MINUS_1___d27 :
MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 ;
assign wci_wslv_respF_cntr_r_EN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ||
WILL_FIRE_RL_wci_wslv_respF_incCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0_write_1__SEL_1 or
MUX_wci_wslv_respF_q_0_write_1__VAL_1 or
MUX_wci_wslv_respF_q_0_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0_write_1__SEL_1:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1;
MUX_wci_wslv_respF_q_0_write_1__SEL_2:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0_D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or
MUX_wci_wslv_respF_q_1_write_1__VAL_1 or
MUX_wci_wslv_respF_q_1_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1_write_1__SEL_1:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1;
MUX_wci_wslv_respF_q_1_write_1__SEL_2:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg_D_IN = 1'b0 ;
assign wci_wslv_sFlagReg_EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind_D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[57]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky_D_IN = 1'b0 ;
assign wsiM_errorSticky_EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount_D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset_D_IN = 1'd0 ;
assign wsiM_isReset_isInReset_EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD_EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount_D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady_D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady_EN = 1'd1 ;
// register wsiM_reqFifo_cntr_r
assign wsiM_reqFifo_cntr_r_D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 :
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ;
assign wsiM_reqFifo_cntr_r_EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0_write_1__SEL_1:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1;
MUX_wsiM_reqFifo_q_0_write_1__SEL_2:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0_D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0_D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo7 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1_write_1__SEL_1:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
MUX_wsiM_reqFifo_q_1_write_1__SEL_2:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1_D_IN = 61'h00000AAAAAAAAA00;
default: wsiM_reqFifo_q_1_D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo5 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d_D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR_D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR_EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount_D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount_EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky_D_IN = 1'd1 ;
assign wsiM_trafficSticky_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind_D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq_wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq_wget[57]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky_D_IN = 1'b0 ;
assign wsiS_errorSticky_EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount_D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq_wget[57] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset_D_IN = 1'd0 ;
assign wsiS_isReset_isInReset_EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength_D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq_wget[57] ;
// register wsiS_operateD
assign wsiS_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD_EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount_D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq_wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady_D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady_EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg_D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq !=
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid_D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid_EN =
wsiM_reqFifo_cntr_r != 2'd2 && wsiS_reqFifo_EMPTY_N &&
wci_wslv_cState == 3'd2 ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR_D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR_EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount_D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount_EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky_D_IN = 1'd1 ;
assign wsiS_trafficSticky_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount_D_IN =
wsiS_wsiReq_wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF_D_IN = wci_wslv_wciReq_wget ;
assign wci_wslv_reqF_ENQ = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_DEQ = wci_wslv_reqF_r_deq_whas ;
assign wci_wslv_reqF_CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo_D_IN = wsiS_wsiReq_wget ;
assign wsiS_reqFifo_ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_DEQ = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_CLR = 1'b0 ;
// remaining internal signals
assign _dfoo1 =
wci_wslv_respF_cntr_r != 2'd2 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
assign _dfoo3 =
wci_wslv_respF_cntr_r != 2'd1 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
assign _dfoo5 =
wsiM_reqFifo_cntr_r != 2'd2 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ;
assign _dfoo7 =
wsiM_reqFifo_cntr_r != 2'd1 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ;
assign rdat__h10861 = hasDebugLogic ? { 16'd0, x__h10865 } : 32'd0 ;
assign rdat__h10961 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h10975 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h10983 = hasDebugLogic ? wsiS_extStatusW_wget[31:0] : 32'd0 ;
assign rdat__h10989 = hasDebugLogic ? wsiM_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h11003 = hasDebugLogic ? wsiM_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h11011 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ;
assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 =
wci_wslv_respF_cntr_r - 2'd1 ;
assign x__h10865 = { wsiS_statusR, wsiM_statusR } ;
assign x_data__h10099 = wsiS_reqFifo_D_OUT[43:12] + biasValue ;
always@(wci_wslv_reqF_D_OUT or
biasValue or
controlReg or
rdat__h10861 or
rdat__h10961 or
rdat__h10975 or
rdat__h10983 or rdat__h10989 or rdat__h11003 or rdat__h11011)
begin
case (wci_wslv_reqF_D_OUT[39:32])
8'h0: _theResult____h10771 = biasValue;
8'h04: _theResult____h10771 = controlReg;
8'h20: _theResult____h10771 = rdat__h10861;
8'h24: _theResult____h10771 = rdat__h10961;
8'h28: _theResult____h10771 = rdat__h10975;
8'h2C: _theResult____h10771 = rdat__h10983;
8'h30: _theResult____h10771 = rdat__h10989;
8'h34: _theResult____h10771 = rdat__h11003;
8'h38: _theResult____h10771 = rdat__h11011;
default: _theResult____h10771 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (wci_wslv_cEdge_EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge_D_IN;
if (wci_wslv_cState_EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState_D_IN;
if (wci_wslv_ctlAckReg_EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg_D_IN;
if (wci_wslv_ctlOpActive_EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive_D_IN;
if (wci_wslv_illegalEdge_EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge_D_IN;
if (wci_wslv_nState_EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState_D_IN;
if (wci_wslv_reqF_countReg_EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg_D_IN;
if (wci_wslv_respF_cntr_r_EN)
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wci_wslv_respF_cntr_r_D_IN;
if (wci_wslv_respF_q_0_EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0_D_IN;
if (wci_wslv_respF_q_1_EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1_D_IN;
if (wci_wslv_sFlagReg_EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg_D_IN;
if (wci_wslv_sThreadBusy_d_EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d_D_IN;
if (wsiM_burstKind_EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind_D_IN;
if (wsiM_errorSticky_EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky_D_IN;
if (wsiM_iMesgCount_EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount_D_IN;
if (wsiM_operateD_EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD_D_IN;
if (wsiM_pMesgCount_EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount_D_IN;
if (wsiM_peerIsReady_EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady_D_IN;
if (wsiM_reqFifo_cntr_r_EN)
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY
wsiM_reqFifo_cntr_r_D_IN;
if (wsiM_reqFifo_q_0_EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0_D_IN;
if (wsiM_reqFifo_q_1_EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1_D_IN;
if (wsiM_sThreadBusy_d_EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d_D_IN;
if (wsiM_tBusyCount_EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount_D_IN;
if (wsiM_trafficSticky_EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky_D_IN;
if (wsiS_burstKind_EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind_D_IN;
if (wsiS_errorSticky_EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky_D_IN;
if (wsiS_iMesgCount_EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount_D_IN;
if (wsiS_operateD_EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD_D_IN;
if (wsiS_pMesgCount_EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount_D_IN;
if (wsiS_peerIsReady_EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady_D_IN;
if (wsiS_reqFifo_countReg_EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg_D_IN;
if (wsiS_reqFifo_levelsValid_EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid_D_IN;
if (wsiS_tBusyCount_EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount_D_IN;
if (wsiS_trafficSticky_EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky_D_IN;
if (wsiS_wordCount_EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount_D_IN;
end
if (biasValue_EN) biasValue <= `BSV_ASSIGNMENT_DELAY biasValue_D_IN;
if (controlReg_EN) controlReg <= `BSV_ASSIGNMENT_DELAY controlReg_D_IN;
if (wsiM_statusR_EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR_D_IN;
if (wsiS_mesgWordLength_EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength_D_IN;
if (wsiS_statusR_EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR_D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset_EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset_D_IN;
if (wsiM_isReset_isInReset_EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset_D_IN;
if (wsiS_isReset_isInReset_EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
biasValue = 32'hAAAAAAAA;
controlReg = 32'hAAAAAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_cntr_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_cntr_r = 2'h2;
wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3574 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3574,
wci_wslv_reqF_D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_biasValue_write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 48: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 62: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h10632 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h10632,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
wci_wslv_reqF_D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h3893 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h3893,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3749 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3749,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h10787 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h10787,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
_theResult____h10771);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && MUX_biasValue_write_1__SEL_2)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 28: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && MUX_biasValue_write_1__SEL_2)
$display("Error: \"bsv/wrk/BiasWorker.bsv\", line 67, column 38: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkBiasWorker4B
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:50:04 07/21/2014
// Design Name:
// Module Name: divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module divider(
input [7:0] div, // dividend switch [15:8]
input [7:0] dvr, // divisor switch [7:0]
input clk,
output [7:0] quotient, // quotient
output [7:0] remainder // remainder
);
integer i;
//reg [7:0] r_d_diff;
reg [7:0] diff; // remainder - divisor diff result
//reg [8:0] c0;
reg [7:0] qu;// quotient
reg [7:0] rem;// remainder
always @(posedge clk) begin
//c0[0] = 1'b1;
rem [7:0] = 8'b0; // assign reminader to all zeros initially
qu [7:0] = div[7:0]; // place dividend in Quotient
for (i=0;i<=7;i=i+1) begin
//repeat (8)
rem = rem<<1;// first iteration shift
rem[0] = qu[7];// first iteration shift
qu = qu<<1;// first iteration shift
qu[0] = 1'b0;// first iteration shift
if ( rem >= dvr) begin
rem = rem-dvr;
qu[0] = 1'b1;
end
end
end
assign remainder [7:0] = rem[7:0];
assign quotient [7:0] = qu[7:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_SYMBOL_V
`define SKY130_FD_SC_LP__A2111O_SYMBOL_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2111o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_SYMBOL_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
finalproject_cpu_jtag_debug_module_tck the_finalproject_cpu_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
finalproject_cpu_jtag_debug_module_sysclk the_finalproject_cpu_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic finalproject_cpu_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam finalproject_cpu_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// finalproject_cpu_jtag_debug_module_phy.sld_instance_index = 0,
// finalproject_cpu_jtag_debug_module_phy.sld_ir_width = 2,
// finalproject_cpu_jtag_debug_module_phy.sld_mfg_id = 70,
// finalproject_cpu_jtag_debug_module_phy.sld_sim_action = "",
// finalproject_cpu_jtag_debug_module_phy.sld_sim_n_scan = 0,
// finalproject_cpu_jtag_debug_module_phy.sld_sim_total_length = 0,
// finalproject_cpu_jtag_debug_module_phy.sld_type_id = 34,
// finalproject_cpu_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: gsu_cache.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gsu_cache (
address,
clock,
data,
wren,
q);
input [8:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_cache_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(** * An light axiomatization of integers (used in FSetAVL). *)
(** We define a signature for an integer datatype based on [Z].
The goal is to allow a switch after extraction to ocaml's
[big_int] or even [int] when finiteness isn't a problem
(typically : when mesuring the height of an AVL tree).
*)
Require Import ZArith.
Delimit Scope Int_scope with I.
(** * a specification of integers *)
Module Type Int.
Open Scope Int_scope.
Parameter int : Set.
Parameter i2z : int -> Z.
Arguments Scope i2z [ Int_scope ].
Parameter _0 : int.
Parameter _1 : int.
Parameter _2 : int.
Parameter _3 : int.
Parameter plus : int -> int -> int.
Parameter opp : int -> int.
Parameter minus : int -> int -> int.
Parameter mult : int -> int -> int.
Parameter max : int -> int -> int.
Notation "0" := _0 : Int_scope.
Notation "1" := _1 : Int_scope.
Notation "2" := _2 : Int_scope.
Notation "3" := _3 : Int_scope.
Infix "+" := plus : Int_scope.
Infix "-" := minus : Int_scope.
Infix "*" := mult : Int_scope.
Notation "- x" := (opp x) : Int_scope.
(** For logical relations, we can rely on their counterparts in Z,
since they don't appear after extraction. Moreover, using tactics
like omega is easier this way. *)
Notation "x == y" := (i2z x = i2z y)
(at level 70, y at next level, no associativity) : Int_scope.
Notation "x <= y" := (Zle (i2z x) (i2z y)): Int_scope.
Notation "x < y" := (Zlt (i2z x) (i2z y)) : Int_scope.
Notation "x >= y" := (Zge (i2z x) (i2z y)) : Int_scope.
Notation "x > y" := (Zgt (i2z x) (i2z y)): Int_scope.
Notation "x <= y <= z" := (x <= y /\ y <= z) : Int_scope.
Notation "x <= y < z" := (x <= y /\ y < z) : Int_scope.
Notation "x < y < z" := (x < y /\ y < z) : Int_scope.
Notation "x < y <= z" := (x < y /\ y <= z) : Int_scope.
(** Some decidability fonctions (informative). *)
Axiom gt_le_dec : forall x y: int, {x > y} + {x <= y}.
Axiom ge_lt_dec : forall x y : int, {x >= y} + {x < y}.
Axiom eq_dec : forall x y : int, { x == y } + {~ x==y }.
(** Specifications *)
(** First, we ask [i2z] to be injective. Said otherwise, our ad-hoc equality
[==] and the generic [=] are in fact equivalent. We define [==]
nonetheless since the translation to [Z] for using automatic tactic is easier. *)
Axiom i2z_eq : forall n p : int, n == p -> n = p.
(** Then, we express the specifications of the above parameters using their
Z counterparts. *)
Open Scope Z_scope.
Axiom i2z_0 : i2z _0 = 0.
Axiom i2z_1 : i2z _1 = 1.
Axiom i2z_2 : i2z _2 = 2.
Axiom i2z_3 : i2z _3 = 3.
Axiom i2z_plus : forall n p, i2z (n + p) = i2z n + i2z p.
Axiom i2z_opp : forall n, i2z (-n) = -i2z n.
Axiom i2z_minus : forall n p, i2z (n - p) = i2z n - i2z p.
Axiom i2z_mult : forall n p, i2z (n * p) = i2z n * i2z p.
Axiom i2z_max : forall n p, i2z (max n p) = Zmax (i2z n) (i2z p).
End Int.
(** * Facts and tactics using [Int] *)
Module MoreInt (I:Int).
Import I.
Open Scope Int_scope.
(** A magic (but costly) tactic that goes from [int] back to the [Z]
friendly world ... *)
Hint Rewrite ->
i2z_0 i2z_1 i2z_2 i2z_3 i2z_plus i2z_opp i2z_minus i2z_mult i2z_max : i2z.
Ltac i2z := match goal with
| H : (eq (A:=int) ?a ?b) |- _ =>
generalize (f_equal i2z H);
try autorewrite with i2z; clear H; intro H; i2z
| |- (eq (A:=int) ?a ?b) => apply (i2z_eq a b); try autorewrite with i2z; i2z
| H : _ |- _ => progress autorewrite with i2z in H; i2z
| _ => try autorewrite with i2z
end.
(** A reflexive version of the [i2z] tactic *)
(** this [i2z_refl] is actually weaker than [i2z]. For instance, if a
[i2z] is buried deep inside a subterm, [i2z_refl] may miss it.
See also the limitation about [Set] or [Type] part below.
Anyhow, [i2z_refl] is enough for applying [romega]. *)
Ltac i2z_gen := match goal with
| |- (eq (A:=int) ?a ?b) => apply (i2z_eq a b); i2z_gen
| H : (eq (A:=int) ?a ?b) |- _ =>
generalize (f_equal i2z H); clear H; i2z_gen
| H : (eq (A:=Z) ?a ?b) |- _ => revert H; i2z_gen
| H : (Zlt ?a ?b) |- _ => revert H; i2z_gen
| H : (Zle ?a ?b) |- _ => revert H; i2z_gen
| H : (Zgt ?a ?b) |- _ => revert H; i2z_gen
| H : (Zge ?a ?b) |- _ => revert H; i2z_gen
| H : _ -> ?X |- _ =>
(* A [Set] or [Type] part cannot be dealt with easily
using the [ExprP] datatype. So we forget it, leaving
a goal that can be weaker than the original. *)
match type of X with
| Type => clear H; i2z_gen
| Prop => revert H; i2z_gen
end
| H : _ <-> _ |- _ => revert H; i2z_gen
| H : _ /\ _ |- _ => revert H; i2z_gen
| H : _ \/ _ |- _ => revert H; i2z_gen
| H : ~ _ |- _ => revert H; i2z_gen
| _ => idtac
end.
Inductive ExprI : Set :=
| EI0 : ExprI
| EI1 : ExprI
| EI2 : ExprI
| EI3 : ExprI
| EIplus : ExprI -> ExprI -> ExprI
| EIopp : ExprI -> ExprI
| EIminus : ExprI -> ExprI -> ExprI
| EImult : ExprI -> ExprI -> ExprI
| EImax : ExprI -> ExprI -> ExprI
| EIraw : int -> ExprI.
Inductive ExprZ : Set :=
| EZplus : ExprZ -> ExprZ -> ExprZ
| EZopp : ExprZ -> ExprZ
| EZminus : ExprZ -> ExprZ -> ExprZ
| EZmult : ExprZ -> ExprZ -> ExprZ
| EZmax : ExprZ -> ExprZ -> ExprZ
| EZofI : ExprI -> ExprZ
| EZraw : Z -> ExprZ.
Inductive ExprP : Type :=
| EPeq : ExprZ -> ExprZ -> ExprP
| EPlt : ExprZ -> ExprZ -> ExprP
| EPle : ExprZ -> ExprZ -> ExprP
| EPgt : ExprZ -> ExprZ -> ExprP
| EPge : ExprZ -> ExprZ -> ExprP
| EPimpl : ExprP -> ExprP -> ExprP
| EPequiv : ExprP -> ExprP -> ExprP
| EPand : ExprP -> ExprP -> ExprP
| EPor : ExprP -> ExprP -> ExprP
| EPneg : ExprP -> ExprP
| EPraw : Prop -> ExprP.
(** [int] to [ExprI] *)
Ltac i2ei trm :=
match constr:trm with
| 0 => constr:EI0
| 1 => constr:EI1
| 2 => constr:EI2
| 3 => constr:EI3
| ?x + ?y => let ex := i2ei x with ey := i2ei y in constr:(EIplus ex ey)
| ?x - ?y => let ex := i2ei x with ey := i2ei y in constr:(EIminus ex ey)
| ?x * ?y => let ex := i2ei x with ey := i2ei y in constr:(EImult ex ey)
| max ?x ?y => let ex := i2ei x with ey := i2ei y in constr:(EImax ex ey)
| - ?x => let ex := i2ei x in constr:(EIopp ex)
| ?x => constr:(EIraw x)
end
(** [Z] to [ExprZ] *)
with z2ez trm :=
match constr:trm with
| (?x+?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZplus ex ey)
| (?x-?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZminus ex ey)
| (?x*?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZmult ex ey)
| (Zmax ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EZmax ex ey)
| (-?x)%Z => let ex := z2ez x in constr:(EZopp ex)
| i2z ?x => let ex := i2ei x in constr:(EZofI ex)
| ?x => constr:(EZraw x)
end.
(** [Prop] to [ExprP] *)
Ltac p2ep trm :=
match constr:trm with
| (?x <-> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPequiv ex ey)
| (?x -> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPimpl ex ey)
| (?x /\ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPand ex ey)
| (?x \/ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPor ex ey)
| (~ ?x) => let ex := p2ep x in constr:(EPneg ex)
| (eq (A:=Z) ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EPeq ex ey)
| (?x < ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPlt ex ey)
| (?x <= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPle ex ey)
| (?x > ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPgt ex ey)
| (?x >= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPge ex ey)
| ?x => constr:(EPraw x)
end.
(** [ExprI] to [int] *)
Fixpoint ei2i (e:ExprI) : int :=
match e with
| EI0 => 0
| EI1 => 1
| EI2 => 2
| EI3 => 3
| EIplus e1 e2 => (ei2i e1)+(ei2i e2)
| EIminus e1 e2 => (ei2i e1)-(ei2i e2)
| EImult e1 e2 => (ei2i e1)*(ei2i e2)
| EImax e1 e2 => max (ei2i e1) (ei2i e2)
| EIopp e => -(ei2i e)
| EIraw i => i
end.
(** [ExprZ] to [Z] *)
Fixpoint ez2z (e:ExprZ) : Z :=
match e with
| EZplus e1 e2 => ((ez2z e1)+(ez2z e2))%Z
| EZminus e1 e2 => ((ez2z e1)-(ez2z e2))%Z
| EZmult e1 e2 => ((ez2z e1)*(ez2z e2))%Z
| EZmax e1 e2 => Zmax (ez2z e1) (ez2z e2)
| EZopp e => (-(ez2z e))%Z
| EZofI e => i2z (ei2i e)
| EZraw z => z
end.
(** [ExprP] to [Prop] *)
Fixpoint ep2p (e:ExprP) : Prop :=
match e with
| EPeq e1 e2 => (ez2z e1) = (ez2z e2)
| EPlt e1 e2 => ((ez2z e1)<(ez2z e2))%Z
| EPle e1 e2 => ((ez2z e1)<=(ez2z e2))%Z
| EPgt e1 e2 => ((ez2z e1)>(ez2z e2))%Z
| EPge e1 e2 => ((ez2z e1)>=(ez2z e2))%Z
| EPimpl e1 e2 => (ep2p e1) -> (ep2p e2)
| EPequiv e1 e2 => (ep2p e1) <-> (ep2p e2)
| EPand e1 e2 => (ep2p e1) /\ (ep2p e2)
| EPor e1 e2 => (ep2p e1) \/ (ep2p e2)
| EPneg e => ~ (ep2p e)
| EPraw p => p
end.
(** [ExprI] (supposed under a [i2z]) to a simplified [ExprZ] *)
Fixpoint norm_ei (e:ExprI) : ExprZ :=
match e with
| EI0 => EZraw (0%Z)
| EI1 => EZraw (1%Z)
| EI2 => EZraw (2%Z)
| EI3 => EZraw (3%Z)
| EIplus e1 e2 => EZplus (norm_ei e1) (norm_ei e2)
| EIminus e1 e2 => EZminus (norm_ei e1) (norm_ei e2)
| EImult e1 e2 => EZmult (norm_ei e1) (norm_ei e2)
| EImax e1 e2 => EZmax (norm_ei e1) (norm_ei e2)
| EIopp e => EZopp (norm_ei e)
| EIraw i => EZofI (EIraw i)
end.
(** [ExprZ] to a simplified [ExprZ] *)
Fixpoint norm_ez (e:ExprZ) : ExprZ :=
match e with
| EZplus e1 e2 => EZplus (norm_ez e1) (norm_ez e2)
| EZminus e1 e2 => EZminus (norm_ez e1) (norm_ez e2)
| EZmult e1 e2 => EZmult (norm_ez e1) (norm_ez e2)
| EZmax e1 e2 => EZmax (norm_ez e1) (norm_ez e2)
| EZopp e => EZopp (norm_ez e)
| EZofI e => norm_ei e
| EZraw z => EZraw z
end.
(** [ExprP] to a simplified [ExprP] *)
Fixpoint norm_ep (e:ExprP) : ExprP :=
match e with
| EPeq e1 e2 => EPeq (norm_ez e1) (norm_ez e2)
| EPlt e1 e2 => EPlt (norm_ez e1) (norm_ez e2)
| EPle e1 e2 => EPle (norm_ez e1) (norm_ez e2)
| EPgt e1 e2 => EPgt (norm_ez e1) (norm_ez e2)
| EPge e1 e2 => EPge (norm_ez e1) (norm_ez e2)
| EPimpl e1 e2 => EPimpl (norm_ep e1) (norm_ep e2)
| EPequiv e1 e2 => EPequiv (norm_ep e1) (norm_ep e2)
| EPand e1 e2 => EPand (norm_ep e1) (norm_ep e2)
| EPor e1 e2 => EPor (norm_ep e1) (norm_ep e2)
| EPneg e => EPneg (norm_ep e)
| EPraw p => EPraw p
end.
Lemma norm_ei_correct : forall e:ExprI, ez2z (norm_ei e) = i2z (ei2i e).
Proof.
induction e; simpl; intros; i2z; auto; try congruence.
Qed.
Lemma norm_ez_correct : forall e:ExprZ, ez2z (norm_ez e) = ez2z e.
Proof.
induction e; simpl; intros; i2z; auto; try congruence; apply norm_ei_correct.
Qed.
Lemma norm_ep_correct :
forall e:ExprP, ep2p (norm_ep e) <-> ep2p e.
Proof.
induction e; simpl; repeat (rewrite norm_ez_correct); intuition.
Qed.
Lemma norm_ep_correct2 :
forall e:ExprP, ep2p (norm_ep e) -> ep2p e.
Proof.
intros; destruct (norm_ep_correct e); auto.
Qed.
Ltac i2z_refl :=
i2z_gen;
match goal with |- ?t =>
let e := p2ep t in
change (ep2p e); apply norm_ep_correct2; simpl
end.
(* i2z_refl can be replaced below by (simpl in *; i2z).
The reflexive version improves compilation of AVL files by about 15% *)
End MoreInt.
(** * An implementation of [Int] *)
(** It's always nice to know that our [Int] interface is realizable :-) *)
Module Z_as_Int <: Int.
Open Scope Z_scope.
Definition int := Z.
Definition _0 := 0.
Definition _1 := 1.
Definition _2 := 2.
Definition _3 := 3.
Definition plus := Zplus.
Definition opp := Zopp.
Definition minus := Zminus.
Definition mult := Zmult.
Definition max := Zmax.
Definition gt_le_dec := Z_gt_le_dec.
Definition ge_lt_dec := Z_ge_lt_dec.
Definition eq_dec := Z_eq_dec.
Definition i2z : int -> Z := fun n => n.
Lemma i2z_eq : forall n p, i2z n=i2z p -> n = p. Proof. auto. Qed.
Lemma i2z_0 : i2z _0 = 0. Proof. auto. Qed.
Lemma i2z_1 : i2z _1 = 1. Proof. auto. Qed.
Lemma i2z_2 : i2z _2 = 2. Proof. auto. Qed.
Lemma i2z_3 : i2z _3 = 3. Proof. auto. Qed.
Lemma i2z_plus : forall n p, i2z (n + p) = i2z n + i2z p. Proof. auto. Qed.
Lemma i2z_opp : forall n, i2z (- n) = - i2z n. Proof. auto. Qed.
Lemma i2z_minus : forall n p, i2z (n - p) = i2z n - i2z p. Proof. auto. Qed.
Lemma i2z_mult : forall n p, i2z (n * p) = i2z n * i2z p. Proof. auto. Qed.
Lemma i2z_max : forall n p, i2z (max n p) = Zmax (i2z n) (i2z p). Proof. auto. Qed.
End Z_as_Int.
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_238x128.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.1 Build 201 11/27/2006 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_238x128 (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input [237:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [237:0] q;
output rdempty;
output wrempty;
output wrfull;
output [6:0] wrusedw;
wire sub_wire0;
wire [6:0] sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire [237:0] sub_wire4;
wire rdempty = sub_wire0;
wire [6:0] wrusedw = sub_wire1[6:0];
wire wrfull = sub_wire2;
wire wrempty = sub_wire3;
wire [237:0] q = sub_wire4[237:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrusedw (sub_wire1),
.wrfull (sub_wire2),
.wrempty (sub_wire3),
.q (sub_wire4)
// synopsys translate_off
,
.aclr (),
.rdfull (),
.rdusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 238,
dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "OFF",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "238"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "238"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "238"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 238 0 INPUT NODEFVAL data[237..0]
// Retrieval info: USED_PORT: q 0 0 238 0 OUTPUT NODEFVAL q[237..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 7 0 OUTPUT NODEFVAL wrusedw[6..0]
// Retrieval info: CONNECT: @data 0 0 238 0 data 0 0 238 0
// Retrieval info: CONNECT: q 0 0 238 0 @q 0 0 238 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 7 0 @wrusedw 0 0 7 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_238x128_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRSDFRTN_PP_BLACKBOX_V
/**
* srsdfrtn: Scan flop with sleep mode, inverted reset, inverted
* clock, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTN_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:44:48 03/23/2016
// Design Name: Pi
// Module Name: Y:/TEOCOA/EXP2/TEST_P.v
// Project Name: EXP2
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Pi
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TEST_P;
// Inputs
reg A;
reg B;
// Outputs
wire P;
// Instantiate the Unit Under Test (UUT)
Pi uut (
.A(A),
.B(B),
.P(P)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
// Wait 100 ns for global reset to finish
#100;
A = 0;
B = 1;
// Wait 100 ns for global reset to finish
#100;
A = 1;
B = 0;
// Wait 100 ns for global reset to finish
#100;
A = 1;
B = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
Require Import Coq.Lists.List.
Require Import Coq.Numbers.Natural.Peano.NPeano.
Require Import Coq.omega.Omega Coq.Lists.SetoidList.
Require Export Coq.Setoids.Setoid Coq.Classes.RelationClasses
Coq.Program.Program Coq.Classes.Morphisms.
Require Export Fiat.Common.Coq__8_4__8_5__Compat.
Global Set Implicit Arguments.
Global Generalizable All Variables.
Global Coercion is_true : bool >-> Sortclass.
Coercion bool_of_sumbool {A B} (x : {A} + {B}) : bool := if x then true else false.
Coercion bool_of_sum {A B} (b : sum A B) : bool := if b then true else false.
Lemma bool_of_sum_distr_match {A B C D} (x : sum A B) (c : A -> C) (d : B -> D)
: bool_of_sum (match x with inl k => inl (c k) | inr k => inr (d k) end) = bool_of_sum x.
Proof.
destruct x; reflexivity.
Qed.
(** Test if a tactic succeeds, but always roll-back the results *)
Tactic Notation "test" tactic3(tac) :=
try (first [ tac | fail 2 tac "does not succeed" ]; fail 0 tac "succeeds"; [](* test for [t] solved all goals *)).
(** [not tac] is equivalent to [fail tac "succeeds"] if [tac] succeeds, and is equivalent to [idtac] if [tac] fails *)
Tactic Notation "not" tactic3(tac) := try ((test tac); fail 1 tac "succeeds").
(** Runs [abstract] after clearing the environment, solving the goal
with the tactic associated with [cls <goal type>]. In 8.5, we
could pass a tactic instead. *)
Tactic Notation "clear" "abstract" constr(cls) :=
let G := match goal with |- ?G => constr:(G) end in
let pf := constr:(_ : cls G) in
let pf' := (eval cbv beta in pf) in
repeat match goal with
| [ H : _ |- _ ] => clear H; test (abstract (exact pf'))
end;
[ abstract (exact pf') ].
(** fail if [x] is a function application, a dependent product ([fun _
=> _]), or a sigma type ([forall _, _]) *)
Ltac atomic x :=
idtac;
match x with
| _ => is_evar x; fail 1 x "is not atomic (evar)"
| ?f _ => fail 1 x "is not atomic (application)"
| (fun _ => _) => fail 1 x "is not atomic (fun)"
| forall _, _ => fail 1 x "is not atomic (forall)"
| let x := _ in _ => fail 1 x "is not atomic (let in)"
| match _ with _ => _ end => fail 1 x "is not atomic (match)"
| _ => is_fix x; fail 1 x "is not atomic (fix)"
| context[?E] => (* catch-all *) (not constr_eq E x); fail 1 x "is not atomic (has subterm" E ")"
| _ => idtac
end.
(* [pose proof defn], but only if no hypothesis of the same type exists.
most useful for proofs of a proposition *)
Tactic Notation "unique" "pose" "proof" constr(defn) :=
let T := type of defn in
match goal with
| [ H : T |- _ ] => fail 1
| _ => pose proof defn
end.
(** [pose defn], but only if that hypothesis doesn't exist *)
Tactic Notation "unique" "pose" constr(defn) :=
match goal with
| [ H := defn |- _ ] => fail 1
| _ => pose defn
end.
(** check's if the given hypothesis has a body, i.e., if [clearbody]
could ever succeed. We can't just do [test_tac (clearbody H)],
because maybe the correctness of the proof depends on the body of
H *)
Tactic Notation "has" "body" hyp(H) :=
test (let H' := fresh in pose H as H'; unfold H in H').
Tactic Notation "etransitivity_rev" open_constr(v)
:= match goal with
| [ |- ?R ?LHS ?RHS ]
=> refine ((fun q p => @transitivity _ R _ LHS v RHS p q) _ _)
end.
Tactic Notation "etansitivity_rev" := etransitivity_rev _.
(** find the head of the given expression *)
Ltac head expr :=
match expr with
| ?f _ => head f
| _ => expr
end.
Ltac head_hnf expr := let expr' := eval hnf in expr in head expr'.
(** call [tac H], but first [simpl]ify [H].
This tactic leaves behind the simplified hypothesis. *)
Ltac simpl_do tac H :=
let H' := fresh in pose H as H'; simpl; simpl in H'; tac H'.
(** clear the left-over hypothesis after [simpl_do]ing it *)
Ltac simpl_do_clear tac H := simpl_do ltac:(fun H => tac H; try clear H) H.
Ltac simpl_rewrite term := simpl_do_clear ltac:(fun H => rewrite H) term.
Ltac simpl_rewrite_rev term := simpl_do_clear ltac:(fun H => rewrite <- H) term.
Tactic Notation "simpl" "rewrite" open_constr(term) := simpl_rewrite term.
Tactic Notation "simpl" "rewrite" "->" open_constr(term) := simpl_rewrite term.
Tactic Notation "simpl" "rewrite" "<-" open_constr(term) := simpl_rewrite_rev term.
Ltac do_with_hyp tac :=
match goal with
| [ H : _ |- _ ] => tac H
end.
Ltac rewrite_hyp' := do_with_hyp ltac:(fun H => rewrite H).
Ltac rewrite_hyp := repeat rewrite_hyp'.
Ltac rewrite_rev_hyp' := do_with_hyp ltac:(fun H => rewrite <- H).
Ltac rewrite_rev_hyp := repeat rewrite_rev_hyp'.
Ltac apply_hyp' := do_with_hyp ltac:(fun H => apply H).
Ltac apply_hyp := repeat apply_hyp'.
Ltac eapply_hyp' := do_with_hyp ltac:(fun H => eapply H).
Ltac eapply_hyp := repeat eapply_hyp'.
(** solve simple setiod goals that can be solved by [transitivity] *)
Ltac simpl_transitivity :=
try solve [ match goal with
| [ _ : ?Rel ?a ?b, _ : ?Rel ?b ?c |- ?Rel ?a ?c ] => transitivity b; assumption
end ].
(** given a [matcher] that succeeds on some hypotheses and fails on
others, destruct any matching hypotheses, and then execute [tac]
after each [destruct].
The [tac] part exists so that you can, e.g., [simpl in *], to
speed things up. *)
Ltac do_one_match_then matcher do_tac tac :=
idtac;
match goal with
| [ H : ?T |- _ ]
=> matcher T; do_tac H;
try match type of H with
| T => clear H
end;
tac
end.
Ltac do_all_matches_then matcher do_tac tac :=
repeat do_one_match_then matcher do_tac tac.
Ltac destruct_all_matches_then matcher tac :=
do_all_matches_then matcher ltac:(fun H => destruct H) tac.
Ltac destruct_one_match_then matcher tac :=
do_one_match_then matcher ltac:(fun H => destruct H) tac.
Ltac inversion_all_matches_then matcher tac :=
do_all_matches_then matcher ltac:(fun H => inversion H; subst) tac.
Ltac inversion_one_match_then matcher tac :=
do_one_match_then matcher ltac:(fun H => inversion H; subst) tac.
Ltac destruct_all_matches matcher :=
destruct_all_matches_then matcher ltac:( simpl in * ).
Ltac destruct_one_match matcher := destruct_one_match_then matcher ltac:( simpl in * ).
Ltac destruct_all_matches' matcher := destruct_all_matches_then matcher idtac.
Ltac inversion_all_matches matcher := inversion_all_matches_then matcher ltac:( simpl in * ).
Ltac inversion_one_match matcher := inversion_one_match_then matcher ltac:( simpl in * ).
Ltac inversion_all_matches' matcher := inversion_all_matches_then matcher idtac.
(* matches anything whose type has a [T] in it *)
Ltac destruct_type_matcher T HT :=
match HT with
| context[T] => idtac
end.
Ltac destruct_type T := destruct_all_matches ltac:(destruct_type_matcher T).
Ltac destruct_type' T := destruct_all_matches' ltac:(destruct_type_matcher T).
Ltac destruct_head_matcher T HT :=
match head HT with
| T => idtac
end.
Ltac destruct_head T := destruct_all_matches ltac:(destruct_head_matcher T).
Ltac destruct_one_head T := destruct_one_match ltac:(destruct_head_matcher T).
Ltac destruct_head' T := destruct_all_matches' ltac:(destruct_head_matcher T).
Ltac inversion_head T := inversion_all_matches ltac:(destruct_head_matcher T).
Ltac inversion_one_head T := inversion_one_match ltac:(destruct_head_matcher T).
Ltac inversion_head' T := inversion_all_matches' ltac:(destruct_head_matcher T).
Ltac head_hnf_matcher T HT :=
match head_hnf HT with
| T => idtac
end.
Ltac destruct_head_hnf T := destruct_all_matches ltac:(head_hnf_matcher T).
Ltac destruct_one_head_hnf T := destruct_one_match ltac:(head_hnf_matcher T).
Ltac destruct_head_hnf' T := destruct_all_matches' ltac:(head_hnf_matcher T).
Ltac inversion_head_hnf T := inversion_all_matches ltac:(head_hnf_matcher T).
Ltac inversion_one_head_hnf T := inversion_one_match ltac:(head_hnf_matcher T).
Ltac inversion_head_hnf' T := inversion_all_matches' ltac:(head_hnf_matcher T).
Ltac destruct_sig_matcher HT :=
match eval hnf in HT with
| ex _ => idtac
| ex2 _ _ => idtac
| sig _ => idtac
| sig2 _ _ => idtac
| sigT _ => idtac
| sigT2 _ _ => idtac
| and _ _ => idtac
| prod _ _ => idtac
end.
Ltac destruct_sig := destruct_all_matches destruct_sig_matcher.
Ltac destruct_sig' := destruct_all_matches' destruct_sig_matcher.
Ltac destruct_all_hypotheses := destruct_all_matches ltac:(fun HT =>
destruct_sig_matcher HT || destruct_sig_matcher HT
).
(** if progress can be made by [exists _], but it doesn't matter what
fills in the [_], assume that something exists, and leave the two
goals of finding a member of the apropriate type, and proving that
all members of the appropriate type prove the goal *)
Ltac destruct_exists' T := cut T; try (let H := fresh in intro H; exists H).
Ltac destruct_exists := destruct_head_hnf @sigT;
match goal with
(* | [ |- @sig ?T _ ] => destruct_exists' T*)
| [ |- @sigT ?T _ ] => destruct_exists' T
(* | [ |- @sig2 ?T _ _ ] => destruct_exists' T*)
| [ |- @sigT2 ?T _ _ ] => destruct_exists' T
end.
(** if the goal can be solved by repeated specialization of some
hypothesis with other [specialized] hypotheses, solve the goal by
brute force *)
Ltac specialized_assumption tac := tac;
match goal with
| [ x : ?T, H : forall _ : ?T, _ |- _ ] => specialize (H x); specialized_assumption tac
| _ => assumption
end.
(** for each hypothesis of type [H : forall _ : ?T, _], if there is
exactly one hypothesis of type [H' : T], do [specialize (H H')]. *)
Ltac specialize_uniquely :=
repeat match goal with
| [ x : ?T, y : ?T, H : _ |- _ ] => test (specialize (H x)); fail 1
| [ x : ?T, H : _ |- _ ] => specialize (H x)
end.
(** specialize all hypotheses of type [forall _ : ?T, _] with
appropriately typed hypotheses *)
Ltac specialize_all_ways_forall :=
repeat match goal with
| [ x : ?T, H : forall _ : ?T, _ |- _ ] => unique pose proof (H x)
end.
(** try to specialize all hypotheses with all other hypotheses. This
includes [specialize (H x)] where [H x] requires a coercion from
the type of [H] to Funclass. *)
Ltac specialize_all_ways :=
repeat match goal with
| [ x : ?T, H : _ |- _ ] => unique pose proof (H x)
end.
(** try to specialize all non-dependent hypotheses using [tac] *)
Ltac specialize_by' tac :=
idtac;
match goal with
| [ H : ?A -> ?B |- _ ] => let H' := fresh in assert (H' : A) by tac; specialize (H H'); clear H'
end.
Ltac specialize_by tac := repeat specialize_by' tac.
Ltac apply_in_hyp lem :=
match goal with
| [ H : _ |- _ ] => apply lem in H
end.
Ltac apply_in_hyp_no_match lem :=
match goal with
| [ H : _ |- _ ] => apply lem in H;
match type of H with
| appcontext[match _ with _ => _ end] => fail 1
| _ => idtac
end
end.
Ltac apply_in_hyp_no_cbv_match lem :=
match goal with
| [ H : _ |- _ ]
=> apply lem in H;
cbv beta iota in H;
match type of H with
| appcontext[match _ with _ => _ end] => fail 1
| _ => idtac
end
end.
(* Coq's build in tactics don't work so well with things like [iff]
so split them up into multiple hypotheses *)
Ltac split_in_context_by ident funl funr tac :=
repeat match goal with
| [ H : context p [ident] |- _ ] =>
let H0 := context p[funl] in let H0' := eval simpl in H0 in assert H0' by (tac H);
let H1 := context p[funr] in let H1' := eval simpl in H1 in assert H1' by (tac H);
clear H
end.
Ltac split_in_context ident funl funr :=
split_in_context_by ident funl funr ltac:(fun H => apply H).
Ltac split_iff := split_in_context iff (fun a b : Prop => a -> b) (fun a b : Prop => b -> a).
Ltac split_and' :=
repeat match goal with
| [ H : ?a /\ ?b |- _ ] => let H0 := fresh in let H1 := fresh in
assert (H0 := fst H); assert (H1 := snd H); clear H
end.
Ltac split_and := split_and'; split_in_context and (fun a b : Type => a) (fun a b : Type => b).
Ltac destruct_sum_in_match' :=
match goal with
| [ H : appcontext[match ?E with inl _ => _ | inr _ => _ end] |- _ ]
=> destruct E
| [ |- appcontext[match ?E with inl _ => _ | inr _ => _ end] ]
=> destruct E
end.
Ltac destruct_sum_in_match := repeat destruct_sum_in_match'.
Ltac destruct_ex :=
repeat match goal with
| [ H : ex _ |- _ ] => destruct H
end.
Ltac setoid_rewrite_hyp' := do_with_hyp ltac:(fun H => setoid_rewrite H).
Ltac setoid_rewrite_hyp := repeat setoid_rewrite_hyp'.
Ltac setoid_rewrite_rev_hyp' := do_with_hyp ltac:(fun H => setoid_rewrite <- H).
Ltac setoid_rewrite_rev_hyp := repeat setoid_rewrite_rev_hyp'.
Hint Extern 0 => solve [apply reflexivity] : typeclass_instances.
Ltac set_evars :=
repeat match goal with
| [ |- appcontext[?E] ] => is_evar E; let H := fresh in set (H := E)
end.
Tactic Notation "eunify" open_constr(A) open_constr(B) := unify A B.
Instance pointwise_refl A B (eqB : relation B) `{Reflexive _ eqB} : Reflexive (pointwise_relation A eqB).
Proof.
compute in *; auto.
Defined.
Instance pointwise_sym A B (eqB : relation B) `{Symmetric _ eqB} : Symmetric (pointwise_relation A eqB).
Proof.
compute in *; auto.
Defined.
Instance pointwise_transitive A B (eqB : relation B) `{Transitive _ eqB} : Transitive (pointwise_relation A eqB).
Proof.
compute in *; eauto.
Defined.
Lemma Some_ne_None {T} {x : T} : Some x <> None.
Proof.
congruence.
Qed.
Lemma None_ne_Some {T} {x : T} : None <> Some x.
Proof.
congruence.
Qed.
(* We define a wrapper for [if then else] in order for it to play
nicely with setoid_rewriting. *)
Definition If_Then_Else {A}
(c : bool)
(t e : A) :=
if c then t else e.
Notation "'If' c 'Then' t 'Else' e" :=
(If_Then_Else c t e)
(at level 70).
Definition If_Opt_Then_Else {A B}
(c : option A)
(t : A -> B)
(e : B) :=
match c with
| Some a => t a
| None => e
end.
Notation "'Ifopt' c 'as' c' 'Then' t 'Else' e" :=
(If_Opt_Then_Else c (fun c' => t) e)
(at level 70).
Global Instance If_Then_Else_fun_Proper {T} {R : relation T} {A B C D RA RB RC RD}
{bv tv fv}
{H0 : Proper (RA ==> RB ==> RC ==> RD ==> eq) bv}
{H1 : Proper (RA ==> RB ==> RC ==> RD ==> R) tv}
{H2 : Proper (RA ==> RB ==> RC ==> RD ==> R) fv}
: Proper (RA ==> RB ==> RC ==> RD ==> R) (fun (a : A) (b : B) (c : C) (d : D) => If bv a b c d Then tv a b c d Else fv a b c d).
Proof.
intros ?? Ha ?? Hb ?? Hc ?? Hd.
specialize (H0 _ _ Ha _ _ Hb _ _ Hc _ _ Hd).
rewrite H0; clear H0.
edestruct bv; simpl;
unfold Proper, impl, flip, respectful in *; eauto with nocore.
Qed.
Ltac find_if_inside :=
match goal with
| [ |- context[if ?X then _ else _] ] => destruct X
| [ |- context[If_Then_Else ?X _ _] ] => destruct X
| [ H : context[if ?X then _ else _] |- _ ]=> destruct X
| [ H : context[If_Then_Else ?X _ _] |- _ ]=> destruct X
end.
Ltac substs :=
repeat match goal with
| [ H : ?x = ?y |- _ ]
=> first [ subst x | subst y ]
end.
Ltac substss :=
repeat match goal with
| [ H : ?x = _ ,
H0 : ?x = _ |- _ ]
=> rewrite H in H0
end.
Ltac injections :=
repeat match goal with
| [ H : _ = _ |- _ ]
=> injection H; intros; subst; clear H
end.
Ltac inversion_by rule :=
progress repeat first [ progress destruct_ex
| progress split_and
| apply_in_hyp_no_cbv_match rule ].
Class can_transform_sigma A B := do_transform_sigma : A -> B.
Instance can_transform_sigT_base {A} {P : A -> Type}
: can_transform_sigma (sigT P) (sigT P) | 0
:= fun x => x.
Instance can_transform_sig_base {A} {P : A -> Prop}
: can_transform_sigma (sig P) (sig P) | 0
:= fun x => x.
Instance can_transform_sigT {A B B' C'}
`{forall x : A, can_transform_sigma (B x) (@sigT (B' x) (C' x))}
: can_transform_sigma (forall x : A, B x)
(@sigT (forall x, B' x) (fun b => forall x, C' x (b x))) | 0
:= fun f => existT
(fun b => forall x : A, C' x (b x))
(fun x => projT1 (do_transform_sigma (f x)))
(fun x => projT2 (do_transform_sigma (f x))).
Instance can_transform_sig {A B B' C'}
`{forall x : A, can_transform_sigma (B x) (@sig (B' x) (C' x))}
: can_transform_sigma (forall x : A, B x)
(@sig (forall x, B' x) (fun b => forall x, C' x (b x))) | 0
:= fun f => exist
(fun b => forall x : A, C' x (b x))
(fun x => proj1_sig (do_transform_sigma (f x)))
(fun x => proj2_sig (do_transform_sigma (f x))).
Ltac split_sig' :=
match goal with
| [ H : _ |- _ ]
=> let H' := fresh in
pose proof (@do_transform_sigma _ _ _ H) as H';
clear H;
destruct H'
end.
Ltac split_sig :=
repeat split_sig'.
Ltac clearbodies :=
repeat match goal with
| [ H := _ |- _ ] => clearbody H
end.
Ltac subst_body :=
repeat match goal with
| [ H := _ |- _ ] => subst H
end.
(** TODO: Maybe we should replace uses of this with [case_eq], which the stdlib defined for us? *)
Ltac caseEq x := generalize (refl_equal x); pattern x at -1; case x; intros.
Class ReflexiveT A (R : A -> A -> Type) :=
reflexivityT : forall x, R x x.
Class TransitiveT A (R : A -> A -> Type) :=
transitivityT : forall x y z, R x y -> R y z -> R x z.
Class PreOrderT A (R : A -> A -> Type) :=
{ PreOrderT_ReflexiveT :> ReflexiveT R;
PreOrderT_TransitiveT :> TransitiveT R }.
Definition respectful_heteroT A B C D
(R : A -> B -> Type)
(R' : forall (x : A) (y : B), C x -> D y -> Type)
(f : forall x, C x) (g : forall x, D x)
:= forall x y, R x y -> R' x y (f x) (g y).
(* Lifting forall and pointwise relations to multiple arguments. *)
Definition forall_relation2 {A : Type} {B : A -> Type} {C : forall a, B a -> Type} R :=
forall_relation (fun a => (@forall_relation (B a) (C a) (R a))).
Definition pointwise_relation2 {A B C : Type} (R : relation C) :=
pointwise_relation A (@pointwise_relation B C R).
Definition forall_relation3 {A : Type} {B : A -> Type}
{C : forall a, B a -> Type} {D : forall a b, C a b -> Type} R :=
forall_relation (fun a => (@forall_relation2 (B a) (C a) (D a) (R a))).
Definition pointwise_relation3 {A B C D : Type} (R : relation D) :=
pointwise_relation A (@pointwise_relation2 B C D R).
Definition forall_relation4 {A : Type} {B : A -> Type}
{C : forall a, B a -> Type} {D : forall a b, C a b -> Type}
{E : forall a b c, D a b c -> Type} R :=
forall_relation (fun a => (@forall_relation3 (B a) (C a) (D a) (E a) (R a))).
Definition pointwise_relation4 {A B C D E : Type} (R : relation E) :=
pointwise_relation A (@pointwise_relation3 B C D E R).
Ltac higher_order_1_reflexivity' :=
let a := match goal with |- ?R ?a (?f ?x) => constr:(a) end in
let f := match goal with |- ?R ?a (?f ?x) => constr:(f) end in
let x := match goal with |- ?R ?a (?f ?x) => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac sym_higher_order_1_reflexivity' :=
let a := match goal with |- ?R (?f ?x) ?a => constr:(a) end in
let f := match goal with |- ?R (?f ?x) ?a => constr:(f) end in
let x := match goal with |- ?R (?f ?x) ?a => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
(* refine is an antisymmetric relation, so we can try to apply
symmetric versions of higher_order_1_reflexivity. *)
Ltac higher_order_1_reflexivity :=
solve [ higher_order_1_reflexivity'
| sym_higher_order_1_reflexivity' ].
Ltac higher_order_1_f_reflexivity :=
let a := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(a) end in
let f := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(f) end in
let x := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
(* This applies reflexivity after refining a method. *)
Ltac higher_order_2_reflexivity' :=
let x := match goal with |- ?R ?x (?f ?a ?b) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b) => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac sym_higher_order_2_reflexivity' :=
let x := match goal with |- ?R (?f ?a ?b) ?x => constr:(x) end in
let f := match goal with |- ?R (?f ?a ?b) ?x => constr:(f) end in
let a := match goal with |- ?R (?f ?a ?b) ?x => constr:(a) end in
let b := match goal with |- ?R (?f ?a ?b) ?x => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_2_reflexivity :=
solve [ higher_order_2_reflexivity'
| sym_higher_order_2_reflexivity' ].
Ltac higher_order_2_f_reflexivity :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_3_reflexivity :=
let x := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(b) end in
let c := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(c) end in
let x' := (eval pattern a, b, c in x) in
let f' := match x' with ?f' _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_3_f_reflexivity :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(b) end in
let c := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(c) end in
let x' := (eval pattern a, b, c in x) in
let f' := match x' with ?f' _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_4_reflexivity :=
let x := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(b) end in
let c := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(c) end in
let d := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(d) end in
let x' := (eval pattern a, b, c, d in x) in
let f' := match x' with ?f' _ _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_4_f_reflexivity :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(b) end in
let c := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(c) end in
let d := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(d) end in
let x' := (eval pattern a, b, c, d in x) in
let f' := match x' with ?f' _ _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivity].
Ltac higher_order_reflexivity :=
match goal with
| |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => higher_order_4_f_reflexivity
| |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => higher_order_3_f_reflexivity
| |- ?R (?g ?x) (?g' (?f ?a ?b)) => higher_order_2_f_reflexivity
| |- ?R (?g ?x) (?g' (?f ?a)) => higher_order_1_f_reflexivity
| |- ?R ?x (?f ?a ?b ?c ?d) => higher_order_4_reflexivity
| |- ?R ?x (?f ?a ?b ?c) => higher_order_3_reflexivity
| |- ?R ?x (?f ?a ?b) => higher_order_2_reflexivity
| |- ?R ?x (?f ?a) => higher_order_1_reflexivity
| |- _ => reflexivity
end.
Ltac pre_higher_order_reflexivity_single_evar :=
idtac;
match goal with
| [ |- ?L = ?R ] => has_evar R; not has_evar L; symmetry
| [ |- ?L = ?R ] => has_evar L; not has_evar R
| [ |- ?L = ?R ] => fail 1 "Goal has evars on both sides of the equality" L "=" R
| [ |- ?G ] => fail 1 "Goal is not an equality" G
end.
Ltac higher_order_reflexivity_single_evar_step :=
clear;
match goal with
| [ |- ?f ?x = ?R ] => is_var x; revert x
| [ |- ?f ?x = ?R ]
=> not has_evar x;
let R' := (eval pattern x in R) in
change (f x = R' x)
end;
(lazymatch goal with
| [ |- forall x, ?f x = @?R x ]
=> refine (fun x => f_equal (fun F => F x) (_ : f = R))
| [ |- ?f ?x = ?R ?x ]
=> refine (f_equal (fun F => F x) (_ : f = R))
end);
clear.
Ltac higher_order_reflexivity_single_evar :=
pre_higher_order_reflexivity_single_evar;
repeat (reflexivity || higher_order_reflexivity_single_evar_step).
Ltac higher_order_1_reflexivityT' :=
let a := match goal with |- ?R ?a (?f ?x) => constr:(a) end in
let f := match goal with |- ?R ?a (?f ?x) => constr:(f) end in
let x := match goal with |- ?R ?a (?f ?x) => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac sym_higher_order_1_reflexivityT' :=
let a := match goal with |- ?R (?f ?x) ?a => constr:(a) end in
let f := match goal with |- ?R (?f ?x) ?a => constr:(f) end in
let x := match goal with |- ?R (?f ?x) ?a => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
(* refine is an antisymmetric relation, so we can try to apply
symmetric versions of higher_order_1_reflexivityT. *)
Ltac higher_order_1_reflexivityT :=
solve [ higher_order_1_reflexivityT'
| sym_higher_order_1_reflexivityT' ].
Ltac higher_order_1_f_reflexivityT :=
let a := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(a) end in
let f := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(f) end in
let x := match goal with |- ?R (?g ?a) (?g' (?f ?x)) => constr:(x) end in
let a' := (eval pattern x in a) in
let f' := match a' with ?f' _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
(* This applies reflexivityT after refining a method. *)
Ltac higher_order_2_reflexivityT' :=
let x := match goal with |- ?R ?x (?f ?a ?b) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b) => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac sym_higher_order_2_reflexivityT' :=
let x := match goal with |- ?R (?f ?a ?b) ?x => constr:(x) end in
let f := match goal with |- ?R (?f ?a ?b) ?x => constr:(f) end in
let a := match goal with |- ?R (?f ?a ?b) ?x => constr:(a) end in
let b := match goal with |- ?R (?f ?a ?b) ?x => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_2_reflexivityT :=
solve [ higher_order_2_reflexivityT'
| sym_higher_order_2_reflexivityT' ].
Ltac higher_order_2_f_reflexivityT :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b)) => constr:(b) end in
let x' := (eval pattern a, b in x) in
let f' := match x' with ?f' _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_3_reflexivityT :=
let x := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(b) end in
let c := match goal with |- ?R ?x (?f ?a ?b ?c) => constr:(c) end in
let x' := (eval pattern a, b, c in x) in
let f' := match x' with ?f' _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_3_f_reflexivityT :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(b) end in
let c := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => constr:(c) end in
let x' := (eval pattern a, b, c in x) in
let f' := match x' with ?f' _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_4_reflexivityT :=
let x := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(x) end in
let f := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(f) end in
let a := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(a) end in
let b := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(b) end in
let c := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(c) end in
let d := match goal with |- ?R ?x (?f ?a ?b ?c ?d) => constr:(d) end in
let x' := (eval pattern a, b, c, d in x) in
let f' := match x' with ?f' _ _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_4_f_reflexivityT :=
let x := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(x) end in
let f := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(f) end in
let a := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(a) end in
let b := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(b) end in
let c := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(c) end in
let d := match goal with |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => constr:(d) end in
let x' := (eval pattern a, b, c, d in x) in
let f' := match x' with ?f' _ _ _ _ => constr:(f') end in
unify f f';
cbv beta;
solve [apply reflexivityT].
Ltac higher_order_0_f_reflexivityT :=
match goal with
|- ?R (?g ?a) (?g' ?x) =>
unify a x; solve [apply reflexivityT]
end.
Ltac higher_order_reflexivityT :=
match goal with
| |- ?R (?g ?x) (?g' (?f ?a ?b ?c ?d)) => higher_order_4_f_reflexivityT
| |- ?R (?g ?x) (?g' (?f ?a ?b ?c)) => higher_order_3_f_reflexivityT
| |- ?R (?g ?x) (?g' (?f ?a ?b)) => higher_order_2_f_reflexivityT
| |- ?R (?g ?x) (?g' (?f ?a)) => higher_order_1_f_reflexivityT
| |- ?R (?g ?a) (?g' ?x) => higher_order_0_f_reflexivityT
| |- ?R ?x (?f ?a ?b ?c ?d) => higher_order_4_reflexivityT
| |- ?R ?x (?f ?a ?b ?c) => higher_order_3_reflexivityT
| |- ?R ?x (?f ?a ?b) => higher_order_2_reflexivityT
| |- ?R ?x (?f ?a) => higher_order_1_reflexivityT
| |- _ => reflexivityT
end.
Global Arguments f_equal {A B} f {x y} _ .
Lemma fst_fold_right {A B A'} (f : B -> A -> A) (g : B -> A * A' -> A') a a' ls
: fst (fold_right (fun b aa' => (f b (fst aa'), g b aa')) (a, a') ls)
= fold_right f a ls.
Proof.
induction ls; simpl; trivial.
rewrite IHls; reflexivity.
Qed.
Lemma if_app {A} (ls1 ls1' ls2 : list A) (b : bool)
: (if b then ls1 else ls1') ++ ls2 = if b then (ls1 ++ ls2) else (ls1' ++ ls2).
Proof.
destruct b; reflexivity.
Qed.
Definition pull_if_dep {A B} (P : forall b : bool, A b -> B b) (a : A true) (a' : A false)
(b : bool)
: P b (if b as b return A b then a else a') =
if b as b return B b then P _ a else P _ a'
:= match b with true => eq_refl | false => eq_refl end.
Definition pull_if {A B} (P : A -> B) (a a' : A) (b : bool)
: P (if b then a else a') = if b then P a else P a'
:= pull_if_dep (fun _ => P) a a' b.
(** From [email protected] on coq-club *)
Ltac simplify_hyp' H :=
let T := type of H in
let X := (match eval hnf in T with ?X -> _ => constr:(X) end) in
let H' := fresh in
assert (H' : X) by (tauto || congruence);
specialize (H H');
clear H'.
Ltac simplify_hyps :=
repeat match goal with
| [ H : ?X -> _ |- _ ] => simplify_hyp' H
| [ H : ~?X |- _ ] => simplify_hyp' H
end.
Local Ltac bool_eq_t :=
destruct_head_hnf bool; simpl;
repeat (split || intro || destruct_head iff || congruence);
repeat match goal with
| [ H : ?x = ?x -> _ |- _ ] => specialize (H eq_refl)
| [ H : ?x <> ?x |- _ ] => specialize (H eq_refl)
| [ H : False |- _ ] => destruct H
| _ => progress simplify_hyps
| [ H : ?x = ?y |- _ ] => solve [ inversion H ]
| [ H : false = true -> _ |- _ ] => clear H
end.
Lemma bool_true_iff_beq (b0 b1 b2 b3 : bool)
: (b0 = b1 <-> b2 = b3) <-> (b0 = (if b1
then if b3
then b2
else negb b2
else if b3
then negb b2
else b2)).
Proof. bool_eq_t. Qed.
Lemma bool_true_iff_bneq (b0 b1 b2 b3 : bool)
: (b0 = b1 <-> b2 <> b3) <-> (b0 = (if b1
then if b3
then negb b2
else b2
else if b3
then b2
else negb b2)).
Proof. bool_eq_t. Qed.
Lemma bool_true_iff_bnneq (b0 b1 b2 b3 : bool)
: (b0 = b1 <-> ~b2 <> b3) <-> (b0 = (if b1
then if b3
then b2
else negb b2
else if b3
then negb b2
else b2)).
Proof. bool_eq_t. Qed.
Lemma dn_eqb (x y : bool) : ~~(x = y) -> x = y.
Proof.
destruct x, y; try congruence;
intro H; exfalso; apply H; congruence.
Qed.
Lemma neq_to_eq_negb (x y : bool) : x <> y -> x = negb y.
Proof.
destruct x, y; try congruence; try tauto.
Qed.
Lemma InA_In {A} R (ls : list A) x `{Reflexive _ R}
: List.In x ls -> InA R x ls.
Proof.
revert x.
induction ls; simpl; try tauto.
intros ? [?|?]; subst; [ left | right ]; auto.
Qed.
Lemma InA_In_eq {A} (ls : list A) x
: InA eq x ls <-> List.In x ls.
Proof.
split; [ | eapply InA_In; exact _ ].
revert x.
induction ls; simpl.
{ intros ? H. inversion H. }
{ intros ? H.
inversion H; subst;
first [ left; reflexivity
| right; eauto ]. }
Qed.
Lemma NoDupA_NoDup {A} R (ls : list A) `{Reflexive _ R}
: NoDupA R ls -> NoDup ls.
Proof.
intro H'.
induction H'; constructor; auto.
intro H''; apply (@InA_In _ R) in H''; intuition.
Qed.
Lemma push_if_existT {A} (P : A -> Type) (b : bool) (x y : sigT P)
: (if b then x else y)
= existT P
(if b then (projT1 x) else (projT1 y))
(if b as b return P (if b then (projT1 x) else (projT1 y))
then projT2 x
else projT2 y).
Proof.
destruct b, x, y; reflexivity.
Defined.
(** TODO: Find a better place for these *)
Lemma fold_right_projT1 {A B X} (P : A -> Type) (init : A * B) (ls : list X) (f : X -> A -> A) (g : X -> A -> B -> B) pf pf'
: List.fold_right (fun (x : X) (acc : A * B) =>
(f x (fst acc), g x (fst acc) (snd acc)))
init
ls
= let fr := List.fold_right (fun (x : X) (acc : sigT P * B) =>
(existT P (f x (projT1 (fst acc))) (pf' x acc),
g x (projT1 (fst acc)) (snd acc)))
(existT P (fst init) pf, snd init)
ls in
(projT1 (fst fr), snd fr).
Proof.
revert init pf.
induction ls; simpl; intros [? ?]; trivial; simpl.
intro.
simpl in *.
erewrite IHls; simpl.
reflexivity.
Qed.
Lemma fold_right_projT1' {A X} (P : A -> Type) (init : A) (ls : list X) (f : X -> A -> A) pf pf'
: List.fold_right f init ls
= projT1 (List.fold_right (fun (x : X) (acc : sigT P) =>
existT P (f x (projT1 acc)) (pf' x acc))
(existT P init pf)
ls).
Proof.
revert init pf.
induction ls; simpl; intros; trivial; simpl.
simpl in *.
erewrite IHls; simpl.
reflexivity.
Qed.
Fixpoint combine_sig_helper {T} {P : T -> Prop} (ls : list T) : (forall x, In x ls -> P x) -> list (sig P).
Proof.
refine match ls with
| nil => fun _ => nil
| x::xs => fun H => (exist _ x _)::@combine_sig_helper _ _ xs _
end;
clear combine_sig_helper; simpl in *;
intros;
apply H;
first [ left; reflexivity
| right; assumption ].
Defined.
Lemma Forall_forall1_transparent_helper_1 {A P} {x : A} {xs : list A} {l : list A}
(H : Forall P l) (H' : x::xs = l)
: P x.
Proof.
subst; inversion H; repeat subst; assumption.
Defined.
Lemma Forall_forall1_transparent_helper_2 {A P} {x : A} {xs : list A} {l : list A}
(H : Forall P l) (H' : x::xs = l)
: Forall P xs.
Proof.
subst; inversion H; repeat subst; assumption.
Defined.
Fixpoint Forall_forall1_transparent {A} (P : A -> Prop) (l : list A) {struct l}
: Forall P l -> forall x, In x l -> P x
:= match l as l return Forall P l -> forall x, In x l -> P x with
| nil => fun _ _ f => match f : False with end
| x::xs => fun H x' H' =>
match H' with
| or_introl H'' => eq_rect x
P
(Forall_forall1_transparent_helper_1 H eq_refl)
_
H''
| or_intror H'' => @Forall_forall1_transparent A P xs (Forall_forall1_transparent_helper_2 H eq_refl) _ H''
end
end.
Definition combine_sig {T P ls} (H : List.Forall P ls) : list (@sig T P)
:= combine_sig_helper ls (@Forall_forall1_transparent T P ls H).
Arguments Forall_forall1_transparent_helper_1 : simpl never.
Arguments Forall_forall1_transparent_helper_2 : simpl never.
Lemma In_combine_sig {T P ls H x} (H' : In x ls)
: In (exist P x (@Forall_forall1_transparent T P ls H _ H')) (combine_sig H).
Proof.
unfold combine_sig.
induction ls; simpl in *; trivial.
destruct_head or; subst;
try first [ left; reflexivity ].
right.
revert H.
match goal with
| [ |- context[@eq_refl ?A ?a] ] => generalize (@eq_refl A a)
end.
set (als := a::ls) in *.
change als with (a::ls) at 1.
clearbody als.
intros e H.
destruct H; [ exfalso; solve [ inversion e ] | ].
apply IHls.
Defined.
Fixpoint flatten1 {T} (ls : list (list T)) : list T
:= match ls with
| nil => nil
| x::xs => (x ++ flatten1 xs)%list
end.
Lemma flatten1_length_ne_0 {T} (ls : list (list T)) (H0 : Datatypes.length ls <> 0)
(H1 : Datatypes.length (hd nil ls) <> 0)
: Datatypes.length (flatten1 ls) <> 0.
Proof.
destruct ls as [| [|] ]; simpl in *; auto.
Qed.
Local Hint Constructors List.Forall.
Lemma Forall_app {T} P (ls1 ls2 : list T)
: List.Forall P ls1 /\ List.Forall P ls2 <-> List.Forall P (ls1 ++ ls2).
Proof.
split.
{ intros [H1 H2].
induction H1; simpl; auto. }
{ intro H; split; induction ls1; simpl in *; auto.
{ inversion_clear H; auto. }
{ inversion_clear H; auto. } }
Qed.
Lemma Forall_flatten1 {T ls P}
: List.Forall P (@flatten1 T ls) <-> List.Forall (List.Forall P) ls.
Proof.
induction ls; simpl.
{ repeat first [ esplit | intro | constructor ]. }
{ etransitivity; [ symmetry; apply Forall_app | ].
split_iff.
split.
{ intros [? ?]; auto. }
{ intro H'; inversion_clear H'; split; auto. } }
Qed.
Lemma Forall_map {A B} {f : A -> B} {ls P}
: List.Forall P (map f ls) <-> List.Forall (P ∘ f) ls.
Proof.
induction ls; simpl.
{ repeat first [ esplit | intro | constructor ]. }
{ split_iff.
split;
intro H'; inversion_clear H'; auto. }
Qed.
Lemma fold_right_map {A B C} (f : A -> B) g c ls
: @fold_right C B g
c
(map f ls)
= fold_right (g ∘ f) c ls.
Proof.
induction ls; unfold compose; simpl; f_equal; auto.
Qed.
Lemma fold_right_orb_true ls
: fold_right orb true ls = true.
Proof.
induction ls; destruct_head_hnf bool; simpl in *; trivial.
Qed.
Lemma fold_right_orb b ls
: fold_right orb b ls = true
<-> fold_right or (b = true) (map (fun x => x = true) ls).
Proof.
induction ls; simpl; intros; try reflexivity.
rewrite <- IHls; clear.
repeat match goal with
| _ => assumption
| _ => split
| _ => intro
| _ => progress subst
| _ => progress simpl in *
| _ => progress destruct_head or
| _ => progress destruct_head bool
| _ => left; reflexivity
| _ => right; assumption
end.
Qed.
Local Hint Constructors Exists.
Local Ltac fold_right_orb_map_sig_t :=
repeat match goal with
| _ => split
| _ => intro
| _ => progress simpl in *
| _ => progress subst
| _ => progress destruct_head sumbool
| _ => progress destruct_head sig
| _ => progress destruct_head and
| _ => progress destruct_head or
| [ H : _ = true |- _ ] => rewrite H
| [ H : (_ || _)%bool = true |- _ ] => apply Bool.orb_true_elim in H
| [ H : ?a, H' : ?a -> ?b |- _ ] => specialize (H' H)
| [ H : ?a, H' : @sig ?a ?P -> ?b |- _ ] => specialize (fun b' => H' (exist P H b'))
| [ H' : _ /\ _ -> _ |- _ ] => specialize (fun a b => H' (conj a b))
| [ |- (?a || true)%bool = true ] => destruct a; reflexivity
| _ => solve [ eauto ]
| _ => congruence
end.
Lemma fold_right_orb_map_sig1 {T} f (ls : list T)
: fold_right orb false (map f ls) = true
-> sig (fun x => In x ls /\ f x = true).
Proof.
induction ls; fold_right_orb_map_sig_t.
Qed.
Lemma fold_right_orb_map_sig2 {T} f (ls : list T)
: sig (fun x => In x ls /\ f x = true)
-> fold_right orb false (map f ls) = true.
Proof.
induction ls; fold_right_orb_map_sig_t.
Qed.
Lemma fold_right_orb_map {T} f (ls : list T)
: fold_right orb false (map f ls) = true
<-> List.Exists (fun x => f x = true) ls.
Proof.
induction ls;
repeat match goal with
| _ => split
| _ => intro
| _ => progress simpl in *
| [ H : Exists _ [] |- _ ] => solve [ inversion H ]
| [ H : Exists _ (_::_) |- _ ] => inversion_clear H
| _ => progress split_iff
| _ => progress destruct_head sumbool
| [ H : (_ || _)%bool = true |- _ ] => apply Bool.orb_true_elim in H
| [ H : ?a, H' : ?a -> ?b |- _ ] => specialize (H' H)
| [ H : _ = true |- _ ] => rewrite H
| [ |- (?a || true)%bool = _ ] => destruct a; reflexivity
| _ => solve [ eauto ]
| _ => congruence
end.
Qed.
Lemma fold_right_map_andb_andb {T} x y f g (ls : list T)
: fold_right andb x (map f ls) = true /\ fold_right andb y (map g ls) = true
<-> fold_right andb (andb x y) (map (fun k => andb (f k) (g k)) ls) = true.
Proof.
induction ls; simpl; intros; destruct_head_hnf bool; try tauto;
rewrite !Bool.andb_true_iff;
try tauto.
Qed.
Lemma fold_right_map_andb_orb {T} x y f g (ls : list T)
: fold_right andb x (map f ls) = true /\ fold_right orb y (map g ls) = true
-> fold_right orb (andb x y) (map (fun k => andb (f k) (g k)) ls) = true.
Proof.
induction ls; simpl; intros; destruct_head_hnf bool; try tauto;
repeat match goal with
| [ H : _ |- _ ] => progress rewrite ?Bool.orb_true_iff, ?Bool.andb_true_iff in H
| _ => progress rewrite ?Bool.orb_true_iff, ?Bool.andb_true_iff
end;
try tauto.
Qed.
Lemma fold_right_map_and_and {T} x y f g (ls : list T)
: fold_right and x (map f ls) /\ fold_right and y (map g ls)
<-> fold_right and (x /\ y) (map (fun k => f k /\ g k) ls).
Proof.
revert x y.
induction ls; simpl; intros; try reflexivity.
rewrite <- IHls; clear.
tauto.
Qed.
Lemma fold_right_map_and_or {T} x y f g (ls : list T)
: fold_right and x (map f ls) /\ fold_right or y (map g ls)
-> fold_right or (x /\ y) (map (fun k => f k /\ g k) ls).
Proof.
revert x y.
induction ls; simpl; intros; try assumption.
intuition.
Qed.
Functional Scheme fold_right_rect := Induction for fold_right Sort Type.
Lemma fold_right_andb_map_impl {T} x y f g (ls : list T)
(H0 : x = true -> y = true)
(H1 : forall k, f k = true -> g k = true)
: (fold_right andb x (map f ls) = true -> fold_right andb y (map g ls) = true).
Proof.
induction ls; simpl; intros; try tauto.
rewrite IHls; simpl;
repeat match goal with
| [ H : _ = true |- _ ] => apply Bool.andb_true_iff in H
| [ |- _ = true ] => apply Bool.andb_true_iff
| _ => progress destruct_head and
| _ => split
| _ => auto
end.
Qed.
Lemma fold_right_andb_map_in_iff {A P} {ls : list A}
: fold_right andb true (map P ls) = true
<-> (forall x, List.In x ls -> P x = true).
Proof.
induction ls; simpl;
[
| rewrite Bool.andb_true_iff, IHls; clear IHls ];
intuition (subst; eauto).
Qed.
Lemma fold_right_andb_map_in {A P} {ls : list A} (H : fold_right andb true (map P ls) = true)
: forall x, List.In x ls -> P x = true.
Proof.
rewrite fold_right_andb_map_in_iff in H; assumption.
Qed.
Lemma if_ext {T} (b : bool) (f1 f2 : b = true -> T true) (g1 g2 : b = false -> T false)
(ext_f : forall H, f1 H = f2 H)
(ext_g : forall H, g1 H = g2 H)
: (if b as b' return (b = b' -> T b') then f1 else g1) eq_refl
= (if b as b' return (b = b' -> T b') then f2 else g2) eq_refl.
Proof.
destruct b; trivial.
Defined.
Class constr_eq_helper {T0 T1} (a : T0) (b : T1) := mkconstr_eq : True.
Hint Extern 0 (constr_eq_helper ?a ?b) => constr_eq a b; exact I : typeclass_instances.
(** return the first hypothesis with head [h] *)
Ltac hyp_with_head h
:= match goal with
| [ H : ?T |- _ ] => let h' := head T in
let test := constr:(_ : constr_eq_helper h' h) in
constr:(H)
end.
Ltac hyp_with_head_hnf h
:= match goal with
| [ H : ?T |- _ ] => let h' := head_hnf T in
let test := constr:(_ : constr_eq_helper h' h) in
constr:(H)
end.
Lemma or_False {A} (H : A \/ False) : A.
Proof.
destruct H as [ a | [] ].
exact a.
Qed.
Lemma False_or {A} (H : False \/ A) : A.
Proof.
destruct H as [ [] | a ].
exact a.
Qed.
Lemma path_prod {A B} {x y : A * B}
(H : x = y)
: fst x = fst y /\ snd x = snd y.
Proof.
destruct H; split; reflexivity.
Defined.
Definition path_prod' {A B} {x x' : A} {y y' : B}
(H : (x, y) = (x', y'))
: x = x' /\ y = y'
:= path_prod H.
Lemma lt_irrefl' {n m} (H : n = m) : ~n < m.
Proof.
subst; apply Lt.lt_irrefl.
Qed.
Lemma or_not_l {A B} (H : A \/ B) (H' : ~A) : B.
Proof.
destruct H; intuition.
Qed.
Lemma or_not_r {A B} (H : A \/ B) (H' : ~B) : A.
Proof.
destruct H; intuition.
Qed.
Ltac instantiate_evar :=
instantiate;
match goal with
| [ H : appcontext[?E] |- _ ]
=> is_evar E;
match goal with
| [ H' : _ |- _ ] => unify E H'
end
| [ |- appcontext[?E] ]
=> is_evar E;
match goal with
| [ H' : _ |- _ ] => unify E H'
end
end;
instantiate.
Ltac instantiate_evars :=
repeat instantiate_evar.
Ltac find_eassumption :=
match goal with
| [ H : ?T |- ?T' ] => constr:(H : T')
end.
Ltac pre_eassumption := idtac; let x := find_eassumption in idtac.
Definition functor_sum {A A' B B'} (f : A -> A') (g : B -> B') (x : sum A B) : sum A' B' :=
match x with
| inl a => inl (f a)
| inr b => inr (g b)
end.
Lemma impl_sum_match_match_option {A B ret s s' n r}
{x : option A}
(f : match x with
| Some x' => s x'
| None => n
end -> ret)
(g : s' r -> ret)
: match
match x return A + B with
| Some x' => inl x'
| None => inr r
end
with
| inl x' => s x'
| inr x' => s' x'
end -> ret.
Proof.
destruct x; assumption.
Defined.
Lemma impl_match_option {A ret s n}
{x : option A}
(f : forall x', x = Some x' -> s x' -> ret)
(g : x = None -> n -> ret)
: match x with
| Some x' => s x'
| None => n
end -> ret.
Proof.
destruct x; eauto.
Defined.
Definition option_bind {A} {B} (f : A -> option B) (x : option A)
: option B
:= match x with
| None => None
| Some a => f a
end.
Fixpoint ForallT {T} (P : T -> Type) (ls : list T) : Type
:= match ls return Type with
| nil => True
| x::xs => (P x * ForallT P xs)%type
end.
Fixpoint Forall_tails {T} (P : list T -> Type) (ls : list T) : Type
:= match ls with
| nil => P nil
| x::xs => (P (x::xs) * Forall_tails P xs)%type
end.
Fixpoint Forall_tailsP {T} (P : list T -> Prop) (ls : list T) : Prop
:= match ls with
| nil => P nil
| x::xs => (P (x::xs) /\ Forall_tailsP P xs)%type
end.
Fixpoint ForallT_all {T} {P : T -> Type} (p : forall t, P t) {ls}
: ForallT P ls
:= match ls with
| nil => I
| x::xs => (p _, @ForallT_all T P p xs)
end.
Fixpoint Forall_tails_all {T} {P : list T -> Type} (p : forall t, P t) {ls}
: Forall_tails P ls
:= match ls with
| nil => p _
| x::xs => (p _, @Forall_tails_all T P p xs)
end.
Fixpoint ForallT_impl {T} (P P' : T -> Type) (ls : list T) {struct ls}
: ForallT (fun x => P x -> P' x) ls
-> ForallT P ls
-> ForallT P' ls
:= match ls return ForallT (fun x => P x -> P' x) ls
-> ForallT P ls
-> ForallT P' ls
with
| nil => fun _ _ => I
| x::xs => fun H H' => (fst H (fst H'), @ForallT_impl T P P' xs (snd H) (snd H'))
end.
Fixpoint Forall_tails_impl {T} (P P' : list T -> Type) (ls : list T) {struct ls}
: Forall_tails (fun x => P x -> P' x) ls
-> Forall_tails P ls
-> Forall_tails P' ls
:= match ls return Forall_tails (fun x => P x -> P' x) ls
-> Forall_tails P ls
-> Forall_tails P' ls
with
| nil => fun H H' => H H'
| x::xs => fun H H' => (fst H (fst H'), @Forall_tails_impl T P P' xs (snd H) (snd H'))
end.
Ltac free_in x y :=
idtac;
match y with
| appcontext[x] => fail 1 x "appears in" y
| _ => idtac
end.
Ltac setoid_subst'' R x :=
atomic x;
match goal with
| [ H : R x ?y |- _ ]
=> free_in x y;
rewrite ?H;
repeat setoid_rewrite H;
repeat match goal with
| [ H' : appcontext[x] |- _ ] => not constr_eq H' H; rewrite H in H'
| [ H' : appcontext[x] |- _ ] => not constr_eq H' H; setoid_rewrite H in H'
end;
clear H;
clear x
| [ H : R ?y x |- _ ]
=> free_in x y;
rewrite <- ?H;
repeat setoid_rewrite <- H;
repeat match goal with
| [ H' : appcontext[x] |- _ ] => not constr_eq H' H; rewrite <- H in H'
| [ H' : appcontext[x] |- _ ] => not constr_eq H' H; setoid_rewrite <- H in H'
end;
clear H;
clear x
end.
Ltac setoid_subst' x :=
atomic x;
match goal with
| [ H : ?R x _ |- _ ] => setoid_subst'' R x
| [ H : ?R _ x |- _ ] => setoid_subst'' R x
end.
Ltac setoid_subst_rel' R :=
idtac;
match goal with
| [ H : R ?x _ |- _ ] => setoid_subst'' R x
| [ H : R _ ?x |- _ ] => setoid_subst'' R x
end.
Ltac setoid_subst_rel R := repeat setoid_subst_rel' R.
Ltac setoid_subst_all :=
repeat match goal with
| [ H : ?R ?x ?y |- _ ] => atomic x; setoid_subst'' R x
| [ H : ?R ?x ?y |- _ ] => atomic y; setoid_subst'' R y
end.
Tactic Notation "setoid_subst" ident(x) := setoid_subst' x.
Tactic Notation "setoid_subst" := setoid_subst_all.
Lemma sub_plus {x y z} (H0 : z <= y) (H1 : y <= x)
: x - (y - z) = (x - y) + z.
Proof. omega. Qed.
Lemma fold_right_and_iff {A ls}
: fold_right and A ls <-> (fold_right and True ls /\ A).
Proof.
induction ls; simpl; tauto.
Qed.
Definition impl0_0 {A} : A -> A := fun x => x.
Definition impl0_1 {A B C} : (B -> C) -> ((A -> B) -> (A -> C)). Proof. auto. Defined.
Definition impl1_1 {A B C} : (B -> A) -> ((A -> C) -> (B -> C)). Proof. auto. Defined.
Definition impl1_2 {A A' B C C'} : ((A -> C) -> (A' -> C')) -> ((A -> B -> C) -> (A' -> B -> C')). Proof. eauto. Defined.
Lemma if_aggregate {A} (b1 b2 : bool) (x y : A)
: (if b1 then x else if b2 then x else y) = (if (b1 || b2)%bool then x else y).
Proof.
destruct b1, b2; reflexivity.
Qed.
Lemma if_aggregate2 {A} (b1 b2 b3 : bool) (x y z : A) (H : b1 = false -> b2 = true -> b3 = true -> False)
: (if b1 then x else if b2 then y else if b3 then x else z) = (if (b1 || b3)%bool then x else if b2 then y else z).
Proof.
case_eq b1; case_eq b2; case_eq b3; try reflexivity; simpl; intros; exfalso; subst; eauto.
Qed.
Lemma if_aggregate3 {A} (b1 b2 b3 b4 : bool) (x y z w : A) (H : b1 = false -> (b2 || b3)%bool = true -> b4 = true -> False)
: (if b1 then x else if b2 then y else if b3 then z else if b4 then x else w) = (if (b1 || b4)%bool then x else if b2 then y else if b3 then z else w).
Proof.
case_eq b1; case_eq b2; case_eq b3; case_eq b4; try reflexivity; simpl; intros; exfalso; subst; eauto.
Qed.
Ltac eassumption' :=
eassumption
|| match goal with
| [ H : _ |- _ ] => exact H
end.
Ltac progress_subgoal top tac cont :=
top; (tac; try (cont ()) || (try (cont ()))).
(* ltac is call-by-value, so wrap the cont in a function *)
(* local definition in a_u_s *)
Ltac cont_fn top tac'' x :=
apply_under_subgoal top tac'' with
(* mutually recursive with progress_subgoal *)
(* calls top on each subgoal generated, which may generate more subgoals *)
(* fails when top fails in progress_subgoals *)
apply_under_subgoal top tac'' :=
progress_subgoal top tac'' ltac:(cont_fn top tac'').
Ltac doAny srewrite_fn drills_fn finish_fn :=
let repeat_srewrite_fn := repeat srewrite_fn in
try repeat_srewrite_fn;
apply_under_subgoal drills_fn ltac:(repeat_srewrite_fn);
finish_fn.
Ltac set_refine_evar :=
match goal with
| |- ?R _ (?H _ _ _ _ _) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H _ _ _ _ ) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H _ _ _ ) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H _ _) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H _ ) =>
let H' := fresh in set (H' := H) in *
| |- ?R _ (?H ) =>
let H' := fresh in set (H' := H) in *
end.
Ltac subst_refine_evar :=
match goal with
| |- ?R _ (?H _ _ _ _ _) => subst H
| |- ?R _ (?H _ _ _ _ ) => subst H
| |- ?R _ (?H _ _ _ ) => subst H
| |- ?R _ (?H _ _) => subst H
| |- ?R _ (?H _ ) => subst H
| |- ?R _ (?H ) => subst H
| _ => idtac
end.
(** Change hypotheses of the form [(exists x : A, B x) -> T] into hypotheses of the form [forall (x : A), B x -> T] *)
Class flatten_exC {T} (x : T) {retT} := make_flatten_exC : retT.
Ltac flatten_ex_helper H rec_tac rec_tac_progress :=
let T := type of H in
match eval cbv beta in T with
| forall x : @ex ?A ?B, @?C x => let ret := constr:(fun (a : A) (y : B a) => H (@ex_intro A B a y)) in
rec_tac_progress ret
| forall x : and ?A ?B, @?C x => let ret := constr:(fun (a : A) (b : B) => H (@conj A B a b)) in
rec_tac_progress ret
| forall x : ?A, @?P x => let ret := constr:(fun (x : A) => _ : flatten_exC (H x)) in
let ret := (eval cbv beta delta [flatten_exC] in ret) in
let retT := type of ret in
let retT := (eval cbv beta delta [flatten_exC] in retT) in
let ret := constr:(ret : retT) in
rec_tac ret
end.
Ltac flatten_ex H :=
match H with
| _ => flatten_ex_helper H ltac:(fun x => constr:(x)) flatten_ex
| _ => H
end.
Ltac progress_flatten_ex H :=
flatten_ex_helper H progress_flatten_ex flatten_ex.
Hint Extern 0 (flatten_exC ?H) => let ret := progress_flatten_ex H in exact ret : typeclass_instances.
Ltac flatten_all_ex :=
repeat match goal with
| [ H : context[ex _ -> _] |- _ ]
=> let H' := fresh in
rename H into H';
let term := flatten_ex H' in
pose proof term as H;
cbv beta in H;
clear H'
end.
Fixpoint apply_n {A} (n : nat) (f : A -> A) (a : A) : A :=
match n with
| 0 => a
| S n' => apply_n n' f (f a)
end.
Lemma apply_n_commute {A} n (f : A -> A) v
: apply_n n f (f v) = f (apply_n n f v).
Proof.
revert v; induction n; simpl; trivial.
Qed.
(** Transparent versions of [proj1], [proj2] *)
Definition proj1' : forall {A B}, A /\ B -> A.
Proof. intros ?? [? ?]; assumption. Defined.
Definition proj2' : forall {A B}, A /\ B -> B.
Proof. intros ?? [? ?]; assumption. Defined.
Definition injective_projections'
: forall {A B} {p1 p2 : A * B},
fst p1 = fst p2 -> snd p1 = snd p2 -> p1 = p2.
Proof.
intros; destruct p1, p2; simpl in *; subst; reflexivity.
Defined.
Global Arguments injective_projections' {_ _ _ _} !_ !_.
Module opt.
Definition fst {A B} := Eval compute in @fst A B.
Definition snd {A B} := Eval compute in @snd A B.
End opt.
(** Work around broken [intros []] in trunk (https://coq.inria.fr/bugs/show_bug.cgi?id=4470) *)
Definition intros_destruct_dummy := True.
Ltac intros_destruct :=
assert intros_destruct_dummy by constructor;
let H := fresh in
intro H; destruct H;
repeat match goal with
| [ H' : ?T |- _ ] => first [ constr_eq T intros_destruct_dummy;
fail 2
| revert H' ]
end;
match goal with
| [ H : intros_destruct_dummy |- _ ] => clear H
end.
(** Work around bug 4494, https://coq.inria.fr/bugs/show_bug.cgi?id=4494 (replace is slow and broken under binders *)
Ltac replace_with_at_by x y set_tac tac :=
let H := fresh in
let x' := fresh in
set_tac x' x;
assert (H : y = x') by (subst x'; tac);
clearbody x'; induction H.
Ltac replace_with_at x y set_tac :=
let H := fresh in
let x' := fresh in
set_tac x' x;
cut (y = x');
[ intro H; induction H
| subst x' ].
Tactic Notation "replace" constr(x) "with" constr(y) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) ).
Tactic Notation "replace" constr(x) "with" constr(y) "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * |- ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "*" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * |- * ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "*" "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in * |- * at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "*" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H |- * ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "*" "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H |- * at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H |- ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H ).
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "at" ne_integer_list(n) :=
replace_with_at x y ltac:(fun x' x => set (x' := x) in H at n ).
Tactic Notation "replace" constr(x) "with" constr(y) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) at n ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * at n ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * |- ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "*" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * |- * ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" "*" "|-" "*" "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in * |- * at n ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "*" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H |- * ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "*" "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H |- * at n ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "|-" "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H |- ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H ) tac.
Tactic Notation "replace" constr(x) "with" constr(y) "in" hyp(H) "at" ne_integer_list(n) "by" tactic3(tac) :=
replace_with_at_by x y ltac:(fun x' x => set (x' := x) in H at n ) tac.
Ltac my_eval_vm_compute_in c :=
eval vm_compute in c.
Ltac my_vm_cast_no_check c :=
vm_cast_no_check c.
Ltac my_vm_compute := vm_compute.
Ltac replace_with_vm_compute c :=
let c' := (my_eval_vm_compute_in c) in
(* we'd like to just do: *)
(* replace c with c' by (clear; abstract (my_vm_compute; reflexivity)) *)
(* but [set] is too slow in 8.4, so we write our own version (see https://coq.inria.fr/bugs/show_bug.cgi?id=3280#c13 *)
let set_tac := (fun x' x
=> pose x as x';
change x with x') in
replace_with_at_by c c' set_tac ltac:(clear; my_vm_cast_no_check (eq_refl c')).
Ltac replace_with_vm_compute_in c H :=
let c' := (my_eval_vm_compute_in c) in
(* By constrast [set ... in ...] seems faster than [change .. with ... in ...] in 8.4?! *)
replace c with c' in H by (clear; my_vm_cast_no_check (eq_refl c')).
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
localparam STACK_DEPTH = 7;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("set_local.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 1;
reg [ MEM_ADDR:0] pc = 17;
reg [STACK_DEPTH:0] index = 1;
wire [ 63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR),
.STACK_DEPTH(STACK_DEPTH)
)
dut
(
.clk(clk),
.reset(reset),
.pc(pc),
.index(index),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("set_local_tb.vcd");
$dumpvars(0, cpu_tb);
#1
reset <= 0;
if(USE_64B) begin
#45
`assert(result, 3);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:16:15 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_counter_d_W4_77 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_15 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_16 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_18 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_19 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_20 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_22 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_25 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6_1 ( CLK,
EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, ack_add_subt, add_subt_dataA,
add_subt_dataB, result_add_subt, op_add_subt, ready_add_subt );
input [63:0] data_in;
input [1:0] shift_region_flag;
output [63:0] data_output;
output [63:0] add_subt_dataA;
output [63:0] add_subt_dataB;
input [63:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, ack_add_subt, op_add_subt;
wire d_ff1_operation_out, enab_cont_iter, load_cont_iter, enab_d_ff2_RB2,
enab_d_ff4_Xn, enab_d_ff4_Yn, enab_d_ff4_Zn, enab_d_ff5_data_out,
enab_dff_5, sel_mux_1_reg, d_ff3_sign_out, data_output2_63_,
cordic_FSM_state_next_1_, cont_iter_net3827306,
d_ff5_data_out_net3827270, reg_Z0_net3827270,
reg_val_muxZ_2stage_net3827270, reg_shift_y_net3827270,
d_ff4_Xn_net3827270, d_ff4_Yn_net3827270, d_ff4_Zn_net3827270,
d_ff5_net3827270, n276, n282, n283, n284, n285, n289, n290, n291,
n292, n293, intadd_457_CI, intadd_457_n3, intadd_457_n2,
intadd_457_n1, intadd_458_CI, intadd_458_n3, intadd_458_n2,
intadd_458_n1, n423, n424, n425, n426, n427, n428, n430, n431, n432,
n433, n434, n435, n436, n437, n438, n439, n440, n441, n442, n443,
n444, n445, n446, n447, n448, n449, n450, n451, n452, n453, n454,
n455, n456, n457, n458, n459, n460, n461, n462, n463, n464, n465,
n466, n467, n468, n469, n470, n471, n472, n473, n474, n475, n476,
n477, n478, n479, n480, n481, n482, n483, n484, n485, n486, n487,
n488, n489, n490, n491, n492, n493, n494, n495, n496, n497, n498,
n499, n500, n501, n502, n503, n504, n505, n506, n507, n508, n509,
n510, n511, n512, n513, n514, n515, n516, n517, n518, n519, n520,
n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542,
n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553,
n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564,
n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n575,
n576, n577, n578, n579, n580, n581, n582, n583, n584, n585, n586,
n587, n588, n589, n590, n591, n592, n593, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n606, n607, n609, n610,
n611, n612, n613, n614, n616, n617, n618, n619, n620, n621, n622,
n623, n624, n625, n626, n627, n628, n629, n630, n631, n632, n633,
n634, n635, n636, n637, n638, n639, n640, n641, n642, n643, n644,
n645, n646, n647, n648, n649, n650, n651, n652, n653, n654, n655,
n656, n657, n658, n659, n660, n661, n662, n663, n664, n665, n666,
n667, n668, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688,
n689, n690, n691, n692, n693, n694, n695, n696, n697, n698, n699,
n700, n701, n702, n703, n704, n705, n706, n707, n708, n709, n710,
n711, n712, n713, n714, n715, n716, n717, n718, n719, n720, n721,
n722, n723, n724, n725, n726, n727, n728, n729, n730, n731, n732,
n733, n734, n735, n736, n737, n738, n739, n740, n741, n742, n743,
n744, n745, n746, n747, n748, n749, n750, n751, n752, n753, n754,
n755, n756, n757, n758, n759, n760, n761, n762, n763, n764, n765,
n766, n767, n768, n770, n771, n772, n773, n774;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:1] cont_iter_out;
wire [63:0] d_ff1_Z;
wire [63:0] d_ff_Xn;
wire [63:0] first_mux_X;
wire [63:0] d_ff_Yn;
wire [63:0] first_mux_Y;
wire [63:0] d_ff_Zn;
wire [63:0] first_mux_Z;
wire [63:0] d_ff2_X;
wire [63:0] d_ff2_Y;
wire [63:0] d_ff2_Z;
wire [10:0] sh_exp_x;
wire [10:0] sh_exp_y;
wire [56:0] data_out_LUT;
wire [63:0] d_ff3_sh_x_out;
wire [63:0] d_ff3_sh_y_out;
wire [56:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [63:0] mux_sal;
wire [63:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
SNPS_CLOCK_GATE_HIGH_counter_d_W4_77 cont_iter_clk_gate_count_reg ( .CLK(clk), .EN(enab_cont_iter), .ENCLK(cont_iter_net3827306), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_13 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3827270),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_25 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(load_cont_iter), .ENCLK(reg_Z0_net3827270), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_22 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(enab_d_ff2_RB2), .ENCLK(reg_val_muxZ_2stage_net3827270),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_20 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(n427), .ENCLK(reg_shift_y_net3827270), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_19 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3827270), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_18 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3827270), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_16 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3827270), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W64_0_15 d_ff5_clk_gate_Q_reg ( .CLK(clk), .EN(
enab_dff_5), .ENCLK(d_ff5_net3827270), .TE(1'b0) );
DFFRXLTS reg_ch_mux_2_Q_reg_0_ ( .D(n283), .CK(n768), .RN(n765), .Q(
sel_mux_2_reg[0]), .QN(n706) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(data_out_LUT[0]), .CK(reg_shift_y_net3827270),
.RN(n765), .Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(data_out_LUT[1]), .CK(reg_shift_y_net3827270),
.RN(n765), .Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(data_out_LUT[2]), .CK(reg_shift_y_net3827270),
.RN(n765), .Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(data_out_LUT[3]), .CK(reg_shift_y_net3827270),
.RN(n765), .Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(data_out_LUT[5]), .CK(reg_shift_y_net3827270),
.RN(n765), .Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(data_out_LUT[6]), .CK(reg_shift_y_net3827270),
.RN(n765), .Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(data_out_LUT[7]), .CK(reg_shift_y_net3827270),
.RN(n765), .Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(data_out_LUT[8]), .CK(reg_shift_y_net3827270),
.RN(n765), .Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(data_out_LUT[9]), .CK(reg_shift_y_net3827270),
.RN(n765), .Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(data_out_LUT[10]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_11_ ( .D(data_out_LUT[11]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[11]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(data_out_LUT[12]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(data_out_LUT[13]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_14_ ( .D(data_out_LUT[14]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[14]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(data_out_LUT[15]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_16_ ( .D(data_out_LUT[16]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[16]) );
DFFRXLTS reg_LUT_Q_reg_17_ ( .D(data_out_LUT[17]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[17]) );
DFFRXLTS reg_LUT_Q_reg_18_ ( .D(data_out_LUT[18]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[18]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(data_out_LUT[19]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_20_ ( .D(data_out_LUT[20]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[20]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(data_out_LUT[21]), .CK(
reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_22_ ( .D(data_out_LUT[22]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[22]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(data_out_LUT[23]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(data_out_LUT[24]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(data_out_LUT[26]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(data_out_LUT[27]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[27]) );
DFFRXLTS reg_LUT_Q_reg_29_ ( .D(data_out_LUT[29]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[29]) );
DFFRXLTS reg_LUT_Q_reg_30_ ( .D(data_out_LUT[30]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[30]) );
DFFRXLTS reg_LUT_Q_reg_31_ ( .D(data_out_LUT[31]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[31]) );
DFFRXLTS reg_LUT_Q_reg_33_ ( .D(data_out_LUT[33]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[33]) );
DFFRXLTS reg_LUT_Q_reg_35_ ( .D(data_out_LUT[35]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[35]) );
DFFRXLTS reg_LUT_Q_reg_37_ ( .D(data_out_LUT[37]), .CK(
reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_LUT_out[37]) );
DFFRXLTS reg_LUT_Q_reg_38_ ( .D(data_out_LUT[38]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[38]) );
DFFRXLTS reg_LUT_Q_reg_39_ ( .D(data_out_LUT[39]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[39]) );
DFFRXLTS reg_LUT_Q_reg_40_ ( .D(data_out_LUT[40]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[40]) );
DFFRXLTS reg_LUT_Q_reg_41_ ( .D(data_out_LUT[41]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[41]) );
DFFRXLTS reg_LUT_Q_reg_43_ ( .D(data_out_LUT[43]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[43]) );
DFFRXLTS reg_LUT_Q_reg_45_ ( .D(data_out_LUT[45]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[45]) );
DFFRXLTS reg_LUT_Q_reg_47_ ( .D(data_out_LUT[47]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[47]) );
DFFRXLTS reg_LUT_Q_reg_49_ ( .D(data_out_LUT[49]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[49]) );
DFFRXLTS reg_LUT_Q_reg_50_ ( .D(data_out_LUT[50]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[50]) );
DFFRXLTS reg_LUT_Q_reg_52_ ( .D(n716), .CK(reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[52]) );
DFFRXLTS reg_LUT_Q_reg_53_ ( .D(data_out_LUT[53]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[53]) );
DFFRXLTS reg_LUT_Q_reg_54_ ( .D(data_out_LUT[54]), .CK(
reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_LUT_out[54]) );
DFFRXLTS reg_LUT_Q_reg_55_ ( .D(data_out_LUT[55]), .CK(
reg_shift_y_net3827270), .RN(n761), .Q(d_ff3_LUT_out[55]) );
DFFRXLTS reg_LUT_Q_reg_56_ ( .D(data_out_LUT[56]), .CK(
reg_shift_y_net3827270), .RN(n761), .Q(d_ff3_LUT_out[56]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3827270), .RN(n761),
.Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3827270), .RN(
n760), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_Z0_Q_reg_32_ ( .D(data_in[32]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[32]) );
DFFRXLTS reg_Z0_Q_reg_33_ ( .D(data_in[33]), .CK(reg_Z0_net3827270), .RN(
n759), .Q(d_ff1_Z[33]) );
DFFRXLTS reg_Z0_Q_reg_34_ ( .D(data_in[34]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[34]) );
DFFRXLTS reg_Z0_Q_reg_35_ ( .D(data_in[35]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[35]) );
DFFRXLTS reg_Z0_Q_reg_36_ ( .D(data_in[36]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[36]) );
DFFRXLTS reg_Z0_Q_reg_37_ ( .D(data_in[37]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[37]) );
DFFRXLTS reg_Z0_Q_reg_38_ ( .D(data_in[38]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[38]) );
DFFRXLTS reg_Z0_Q_reg_39_ ( .D(data_in[39]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[39]) );
DFFRXLTS reg_Z0_Q_reg_40_ ( .D(data_in[40]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[40]) );
DFFRXLTS reg_Z0_Q_reg_41_ ( .D(data_in[41]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[41]) );
DFFRXLTS reg_Z0_Q_reg_42_ ( .D(data_in[42]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[42]) );
DFFRXLTS reg_Z0_Q_reg_43_ ( .D(data_in[43]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[43]) );
DFFRXLTS reg_Z0_Q_reg_44_ ( .D(data_in[44]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[44]) );
DFFRXLTS reg_Z0_Q_reg_45_ ( .D(data_in[45]), .CK(reg_Z0_net3827270), .RN(
n758), .Q(d_ff1_Z[45]) );
DFFRXLTS reg_Z0_Q_reg_46_ ( .D(data_in[46]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[46]) );
DFFRXLTS reg_Z0_Q_reg_47_ ( .D(data_in[47]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[47]) );
DFFRXLTS reg_Z0_Q_reg_48_ ( .D(data_in[48]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[48]) );
DFFRXLTS reg_Z0_Q_reg_49_ ( .D(data_in[49]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[49]) );
DFFRXLTS reg_Z0_Q_reg_50_ ( .D(data_in[50]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[50]) );
DFFRXLTS reg_Z0_Q_reg_51_ ( .D(data_in[51]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[51]) );
DFFRXLTS reg_Z0_Q_reg_52_ ( .D(data_in[52]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[52]) );
DFFRXLTS reg_Z0_Q_reg_53_ ( .D(data_in[53]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[53]) );
DFFRXLTS reg_Z0_Q_reg_54_ ( .D(data_in[54]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[54]) );
DFFRXLTS reg_Z0_Q_reg_55_ ( .D(data_in[55]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[55]) );
DFFRXLTS reg_Z0_Q_reg_56_ ( .D(data_in[56]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[56]) );
DFFRXLTS reg_Z0_Q_reg_57_ ( .D(data_in[57]), .CK(reg_Z0_net3827270), .RN(
n757), .Q(d_ff1_Z[57]) );
DFFRXLTS reg_Z0_Q_reg_58_ ( .D(data_in[58]), .CK(reg_Z0_net3827270), .RN(
n756), .Q(d_ff1_Z[58]) );
DFFRXLTS reg_Z0_Q_reg_59_ ( .D(data_in[59]), .CK(reg_Z0_net3827270), .RN(
n756), .Q(d_ff1_Z[59]) );
DFFRXLTS reg_Z0_Q_reg_60_ ( .D(data_in[60]), .CK(reg_Z0_net3827270), .RN(
n756), .Q(d_ff1_Z[60]) );
DFFRXLTS reg_Z0_Q_reg_61_ ( .D(data_in[61]), .CK(reg_Z0_net3827270), .RN(
n756), .Q(d_ff1_Z[61]) );
DFFRXLTS reg_Z0_Q_reg_62_ ( .D(data_in[62]), .CK(reg_Z0_net3827270), .RN(
n756), .Q(d_ff1_Z[62]) );
DFFRXLTS reg_Z0_Q_reg_63_ ( .D(data_in[63]), .CK(reg_Z0_net3827270), .RN(
n756), .Q(d_ff1_Z[63]) );
DFFRXLTS reg_shift_x_Q_reg_52_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3827270), .RN(n756), .Q(d_ff3_sh_x_out[52]) );
DFFRXLTS reg_shift_x_Q_reg_53_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3827270), .RN(n756), .Q(d_ff3_sh_x_out[53]) );
DFFRXLTS reg_shift_x_Q_reg_54_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3827270), .RN(n756), .Q(d_ff3_sh_x_out[54]) );
DFFRXLTS reg_shift_x_Q_reg_55_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3827270), .RN(n756), .Q(d_ff3_sh_x_out[55]) );
DFFRXLTS reg_shift_x_Q_reg_56_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3827270), .RN(n756), .Q(d_ff3_sh_x_out[56]) );
DFFRXLTS reg_shift_x_Q_reg_57_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3827270), .RN(n756), .Q(d_ff3_sh_x_out[57]) );
DFFRXLTS reg_shift_x_Q_reg_58_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3827270), .RN(n760), .Q(d_ff3_sh_x_out[58]) );
DFFRXLTS reg_shift_x_Q_reg_59_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3827270), .RN(n759), .Q(d_ff3_sh_x_out[59]) );
DFFRXLTS reg_shift_x_Q_reg_60_ ( .D(sh_exp_x[8]), .CK(reg_shift_y_net3827270), .RN(n758), .Q(d_ff3_sh_x_out[60]) );
DFFRXLTS reg_shift_x_Q_reg_61_ ( .D(sh_exp_x[9]), .CK(reg_shift_y_net3827270), .RN(n756), .Q(d_ff3_sh_x_out[61]) );
DFFRXLTS reg_shift_x_Q_reg_62_ ( .D(sh_exp_x[10]), .CK(
reg_shift_y_net3827270), .RN(n761), .Q(d_ff3_sh_x_out[62]) );
DFFRXLTS reg_shift_y_Q_reg_52_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3827270), .RN(n762), .Q(d_ff3_sh_y_out[52]) );
DFFRXLTS reg_shift_y_Q_reg_53_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3827270), .RN(n763), .Q(d_ff3_sh_y_out[53]) );
DFFRXLTS reg_shift_y_Q_reg_54_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_sh_y_out[54]) );
DFFRXLTS reg_shift_y_Q_reg_55_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3827270), .RN(n765), .Q(d_ff3_sh_y_out[55]) );
DFFRXLTS reg_shift_y_Q_reg_56_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3827270), .RN(n760), .Q(d_ff3_sh_y_out[56]) );
DFFRXLTS reg_shift_y_Q_reg_57_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3827270), .RN(n759), .Q(d_ff3_sh_y_out[57]) );
DFFRXLTS reg_shift_y_Q_reg_58_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3827270), .RN(n758), .Q(d_ff3_sh_y_out[58]) );
DFFRXLTS reg_shift_y_Q_reg_59_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3827270), .RN(n755), .Q(d_ff3_sh_y_out[59]) );
DFFRXLTS reg_shift_y_Q_reg_60_ ( .D(sh_exp_y[8]), .CK(reg_shift_y_net3827270), .RN(n755), .Q(d_ff3_sh_y_out[60]) );
DFFRXLTS reg_shift_y_Q_reg_61_ ( .D(sh_exp_y[9]), .CK(reg_shift_y_net3827270), .RN(n755), .Q(d_ff3_sh_y_out[61]) );
DFFRXLTS reg_shift_y_Q_reg_62_ ( .D(sh_exp_y[10]), .CK(
reg_shift_y_net3827270), .RN(n755), .Q(d_ff3_sh_y_out[62]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3827270), .RN(n755), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n755), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3827270),
.RN(n755), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3827270), .RN(n755), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n755), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3827270),
.RN(n755), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3827270), .RN(n755), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n755), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3827270),
.RN(n754), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3827270), .RN(n754), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n754), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3827270),
.RN(n754), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3827270), .RN(n754), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n754), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3827270),
.RN(n754), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3827270), .RN(n754), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n754), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3827270),
.RN(n754), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3827270), .RN(n754), .Q(d_ff_Xn[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n754), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3827270),
.RN(n753), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3827270), .RN(n753), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n753), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3827270),
.RN(n753), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3827270), .RN(n753), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n753), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3827270),
.RN(n753), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3827270), .RN(n753), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n753), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3827270),
.RN(n753), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3827270), .RN(n753), .Q(d_ff_Xn[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n753), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3827270), .RN(n752), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3827270), .RN(n752), .Q(d_ff_Xn[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n752), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3827270), .RN(n752), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3827270), .RN(n752), .Q(d_ff_Xn[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n752), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3827270), .RN(n752), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3827270), .RN(n752), .Q(d_ff_Xn[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n752), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3827270), .RN(n752), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3827270), .RN(n752), .Q(d_ff_Xn[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n752), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3827270), .RN(n751), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3827270), .RN(n751), .Q(d_ff_Xn[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n751), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3827270), .RN(n751), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3827270), .RN(n751), .Q(d_ff_Xn[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n751), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3827270), .RN(n751), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3827270), .RN(n751), .Q(d_ff_Xn[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n751), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3827270), .RN(n751), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3827270), .RN(n751), .Q(d_ff_Xn[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n751), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3827270), .RN(n750), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3827270), .RN(n750), .Q(d_ff_Xn[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n750), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3827270), .RN(n750), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3827270), .RN(n750), .Q(d_ff_Xn[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n750), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3827270), .RN(n750), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3827270), .RN(n750), .Q(d_ff_Xn[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n750), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3827270), .RN(n750), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3827270), .RN(n750), .Q(d_ff_Xn[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n750), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3827270), .RN(n749), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3827270), .RN(n749), .Q(d_ff_Xn[23]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n749), .Q(d_ff2_X[23]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(d_ff2_X[23]), .CK(reg_shift_y_net3827270), .RN(n749), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3827270), .RN(n749), .Q(d_ff_Xn[24]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n749), .Q(d_ff2_X[24]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(d_ff2_X[24]), .CK(reg_shift_y_net3827270), .RN(n749), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3827270), .RN(n749), .Q(d_ff_Xn[25]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n749), .Q(d_ff2_X[25]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(d_ff2_X[25]), .CK(reg_shift_y_net3827270), .RN(n749), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3827270), .RN(n749), .Q(d_ff_Xn[26]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n749), .Q(d_ff2_X[26]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(d_ff2_X[26]), .CK(reg_shift_y_net3827270), .RN(n748), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3827270), .RN(n748), .Q(d_ff_Xn[27]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n748), .Q(d_ff2_X[27]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(d_ff2_X[27]), .CK(reg_shift_y_net3827270), .RN(n748), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3827270), .RN(n748), .Q(d_ff_Xn[28]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n748), .Q(d_ff2_X[28]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(d_ff2_X[28]), .CK(reg_shift_y_net3827270), .RN(n748), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3827270), .RN(n748), .Q(d_ff_Xn[29]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n748), .Q(d_ff2_X[29]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(d_ff2_X[29]), .CK(reg_shift_y_net3827270), .RN(n748), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3827270), .RN(n748), .Q(d_ff_Xn[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n748), .Q(d_ff2_X[30]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(d_ff2_X[30]), .CK(reg_shift_y_net3827270), .RN(n747), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3827270), .RN(n747), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n747), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3827270), .RN(n747), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Xn_Q_reg_32_ ( .D(result_add_subt[32]), .CK(
d_ff4_Xn_net3827270), .RN(n747), .Q(d_ff_Xn[32]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_32_ ( .D(first_mux_X[32]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n747), .Q(d_ff2_X[32]) );
DFFRXLTS reg_shift_x_Q_reg_32_ ( .D(d_ff2_X[32]), .CK(reg_shift_y_net3827270), .RN(n747), .Q(d_ff3_sh_x_out[32]) );
DFFRXLTS d_ff4_Xn_Q_reg_33_ ( .D(result_add_subt[33]), .CK(
d_ff4_Xn_net3827270), .RN(n747), .Q(d_ff_Xn[33]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_33_ ( .D(first_mux_X[33]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n747), .Q(d_ff2_X[33]) );
DFFRXLTS reg_shift_x_Q_reg_33_ ( .D(d_ff2_X[33]), .CK(reg_shift_y_net3827270), .RN(n747), .Q(d_ff3_sh_x_out[33]) );
DFFRXLTS d_ff4_Xn_Q_reg_34_ ( .D(result_add_subt[34]), .CK(
d_ff4_Xn_net3827270), .RN(n747), .Q(d_ff_Xn[34]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_34_ ( .D(first_mux_X[34]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n747), .Q(d_ff2_X[34]) );
DFFRXLTS reg_shift_x_Q_reg_34_ ( .D(d_ff2_X[34]), .CK(reg_shift_y_net3827270), .RN(n746), .Q(d_ff3_sh_x_out[34]) );
DFFRXLTS d_ff4_Xn_Q_reg_35_ ( .D(result_add_subt[35]), .CK(
d_ff4_Xn_net3827270), .RN(n746), .Q(d_ff_Xn[35]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_35_ ( .D(first_mux_X[35]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n746), .Q(d_ff2_X[35]) );
DFFRXLTS reg_shift_x_Q_reg_35_ ( .D(d_ff2_X[35]), .CK(reg_shift_y_net3827270), .RN(n746), .Q(d_ff3_sh_x_out[35]) );
DFFRXLTS d_ff4_Xn_Q_reg_36_ ( .D(result_add_subt[36]), .CK(
d_ff4_Xn_net3827270), .RN(n746), .Q(d_ff_Xn[36]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_36_ ( .D(first_mux_X[36]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n746), .Q(d_ff2_X[36]) );
DFFRXLTS reg_shift_x_Q_reg_36_ ( .D(d_ff2_X[36]), .CK(reg_shift_y_net3827270), .RN(n746), .Q(d_ff3_sh_x_out[36]) );
DFFRXLTS d_ff4_Xn_Q_reg_37_ ( .D(result_add_subt[37]), .CK(
d_ff4_Xn_net3827270), .RN(n746), .Q(d_ff_Xn[37]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_37_ ( .D(first_mux_X[37]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n746), .Q(d_ff2_X[37]) );
DFFRXLTS reg_shift_x_Q_reg_37_ ( .D(d_ff2_X[37]), .CK(reg_shift_y_net3827270), .RN(n746), .Q(d_ff3_sh_x_out[37]) );
DFFRXLTS d_ff4_Xn_Q_reg_38_ ( .D(result_add_subt[38]), .CK(
d_ff4_Xn_net3827270), .RN(n746), .Q(d_ff_Xn[38]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_38_ ( .D(first_mux_X[38]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n746), .Q(d_ff2_X[38]) );
DFFRXLTS reg_shift_x_Q_reg_38_ ( .D(d_ff2_X[38]), .CK(reg_shift_y_net3827270), .RN(n745), .Q(d_ff3_sh_x_out[38]) );
DFFRXLTS d_ff4_Xn_Q_reg_39_ ( .D(result_add_subt[39]), .CK(
d_ff4_Xn_net3827270), .RN(n745), .Q(d_ff_Xn[39]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_39_ ( .D(first_mux_X[39]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n745), .Q(d_ff2_X[39]) );
DFFRXLTS reg_shift_x_Q_reg_39_ ( .D(d_ff2_X[39]), .CK(reg_shift_y_net3827270), .RN(n745), .Q(d_ff3_sh_x_out[39]) );
DFFRXLTS d_ff4_Xn_Q_reg_40_ ( .D(result_add_subt[40]), .CK(
d_ff4_Xn_net3827270), .RN(n745), .Q(d_ff_Xn[40]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_40_ ( .D(first_mux_X[40]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n745), .Q(d_ff2_X[40]) );
DFFRXLTS reg_shift_x_Q_reg_40_ ( .D(d_ff2_X[40]), .CK(reg_shift_y_net3827270), .RN(n745), .Q(d_ff3_sh_x_out[40]) );
DFFRXLTS d_ff4_Xn_Q_reg_41_ ( .D(result_add_subt[41]), .CK(
d_ff4_Xn_net3827270), .RN(n745), .Q(d_ff_Xn[41]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_41_ ( .D(first_mux_X[41]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n745), .Q(d_ff2_X[41]) );
DFFRXLTS reg_shift_x_Q_reg_41_ ( .D(d_ff2_X[41]), .CK(reg_shift_y_net3827270), .RN(n745), .Q(d_ff3_sh_x_out[41]) );
DFFRXLTS d_ff4_Xn_Q_reg_42_ ( .D(result_add_subt[42]), .CK(
d_ff4_Xn_net3827270), .RN(n745), .Q(d_ff_Xn[42]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_42_ ( .D(first_mux_X[42]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n745), .Q(d_ff2_X[42]) );
DFFRXLTS reg_shift_x_Q_reg_42_ ( .D(d_ff2_X[42]), .CK(reg_shift_y_net3827270), .RN(n744), .Q(d_ff3_sh_x_out[42]) );
DFFRXLTS d_ff4_Xn_Q_reg_43_ ( .D(result_add_subt[43]), .CK(
d_ff4_Xn_net3827270), .RN(n744), .Q(d_ff_Xn[43]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_43_ ( .D(first_mux_X[43]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n744), .Q(d_ff2_X[43]) );
DFFRXLTS reg_shift_x_Q_reg_43_ ( .D(d_ff2_X[43]), .CK(reg_shift_y_net3827270), .RN(n744), .Q(d_ff3_sh_x_out[43]) );
DFFRXLTS d_ff4_Xn_Q_reg_44_ ( .D(result_add_subt[44]), .CK(
d_ff4_Xn_net3827270), .RN(n744), .Q(d_ff_Xn[44]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_44_ ( .D(first_mux_X[44]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n744), .Q(d_ff2_X[44]) );
DFFRXLTS reg_shift_x_Q_reg_44_ ( .D(d_ff2_X[44]), .CK(reg_shift_y_net3827270), .RN(n744), .Q(d_ff3_sh_x_out[44]) );
DFFRXLTS d_ff4_Xn_Q_reg_45_ ( .D(result_add_subt[45]), .CK(
d_ff4_Xn_net3827270), .RN(n744), .Q(d_ff_Xn[45]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_45_ ( .D(first_mux_X[45]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n744), .Q(d_ff2_X[45]) );
DFFRXLTS reg_shift_x_Q_reg_45_ ( .D(d_ff2_X[45]), .CK(reg_shift_y_net3827270), .RN(n744), .Q(d_ff3_sh_x_out[45]) );
DFFRXLTS d_ff4_Xn_Q_reg_46_ ( .D(result_add_subt[46]), .CK(
d_ff4_Xn_net3827270), .RN(n744), .Q(d_ff_Xn[46]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_46_ ( .D(first_mux_X[46]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n744), .Q(d_ff2_X[46]) );
DFFRXLTS reg_shift_x_Q_reg_46_ ( .D(d_ff2_X[46]), .CK(reg_shift_y_net3827270), .RN(n761), .Q(d_ff3_sh_x_out[46]) );
DFFRXLTS d_ff4_Xn_Q_reg_47_ ( .D(result_add_subt[47]), .CK(
d_ff4_Xn_net3827270), .RN(n757), .Q(d_ff_Xn[47]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_47_ ( .D(first_mux_X[47]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n719), .Q(d_ff2_X[47]) );
DFFRXLTS reg_shift_x_Q_reg_47_ ( .D(d_ff2_X[47]), .CK(reg_shift_y_net3827270), .RN(n749), .Q(d_ff3_sh_x_out[47]) );
DFFRXLTS d_ff4_Xn_Q_reg_48_ ( .D(result_add_subt[48]), .CK(
d_ff4_Xn_net3827270), .RN(n748), .Q(d_ff_Xn[48]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_48_ ( .D(first_mux_X[48]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n762), .Q(d_ff2_X[48]) );
DFFRXLTS reg_shift_x_Q_reg_48_ ( .D(d_ff2_X[48]), .CK(reg_shift_y_net3827270), .RN(n765), .Q(d_ff3_sh_x_out[48]) );
DFFRXLTS d_ff4_Xn_Q_reg_49_ ( .D(result_add_subt[49]), .CK(
d_ff4_Xn_net3827270), .RN(n764), .Q(d_ff_Xn[49]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_49_ ( .D(first_mux_X[49]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n763), .Q(d_ff2_X[49]) );
DFFRXLTS reg_shift_x_Q_reg_49_ ( .D(d_ff2_X[49]), .CK(reg_shift_y_net3827270), .RN(n756), .Q(d_ff3_sh_x_out[49]) );
DFFRXLTS d_ff4_Xn_Q_reg_50_ ( .D(result_add_subt[50]), .CK(
d_ff4_Xn_net3827270), .RN(n762), .Q(d_ff_Xn[50]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_50_ ( .D(first_mux_X[50]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n765), .Q(d_ff2_X[50]) );
DFFRXLTS reg_shift_x_Q_reg_50_ ( .D(d_ff2_X[50]), .CK(reg_shift_y_net3827270), .RN(n743), .Q(d_ff3_sh_x_out[50]) );
DFFRXLTS d_ff4_Xn_Q_reg_51_ ( .D(result_add_subt[51]), .CK(
d_ff4_Xn_net3827270), .RN(n743), .Q(d_ff_Xn[51]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_51_ ( .D(first_mux_X[51]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n743), .Q(d_ff2_X[51]) );
DFFRXLTS reg_shift_x_Q_reg_51_ ( .D(d_ff2_X[51]), .CK(reg_shift_y_net3827270), .RN(n743), .Q(d_ff3_sh_x_out[51]) );
DFFRXLTS d_ff4_Xn_Q_reg_52_ ( .D(result_add_subt[52]), .CK(
d_ff4_Xn_net3827270), .RN(n743), .Q(d_ff_Xn[52]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_52_ ( .D(first_mux_X[52]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n743), .Q(d_ff2_X[52]), .QN(n430)
);
DFFRXLTS d_ff4_Xn_Q_reg_53_ ( .D(result_add_subt[53]), .CK(
d_ff4_Xn_net3827270), .RN(n743), .Q(d_ff_Xn[53]) );
DFFRXLTS d_ff4_Xn_Q_reg_54_ ( .D(result_add_subt[54]), .CK(
d_ff4_Xn_net3827270), .RN(n743), .Q(d_ff_Xn[54]) );
DFFRXLTS d_ff4_Xn_Q_reg_55_ ( .D(result_add_subt[55]), .CK(
d_ff4_Xn_net3827270), .RN(n743), .Q(d_ff_Xn[55]) );
DFFRXLTS d_ff4_Xn_Q_reg_56_ ( .D(result_add_subt[56]), .CK(
d_ff4_Xn_net3827270), .RN(n742), .Q(d_ff_Xn[56]) );
DFFRXLTS d_ff4_Xn_Q_reg_57_ ( .D(result_add_subt[57]), .CK(
d_ff4_Xn_net3827270), .RN(n742), .Q(d_ff_Xn[57]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_57_ ( .D(first_mux_X[57]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n742), .Q(d_ff2_X[57]), .QN(n715)
);
DFFRXLTS d_ff4_Xn_Q_reg_58_ ( .D(result_add_subt[58]), .CK(
d_ff4_Xn_net3827270), .RN(n742), .Q(d_ff_Xn[58]) );
DFFRXLTS d_ff4_Xn_Q_reg_59_ ( .D(result_add_subt[59]), .CK(
d_ff4_Xn_net3827270), .RN(n742), .Q(d_ff_Xn[59]) );
DFFRXLTS d_ff4_Xn_Q_reg_60_ ( .D(result_add_subt[60]), .CK(
d_ff4_Xn_net3827270), .RN(n742), .Q(d_ff_Xn[60]) );
DFFRXLTS d_ff4_Xn_Q_reg_61_ ( .D(result_add_subt[61]), .CK(
d_ff4_Xn_net3827270), .RN(n742), .Q(d_ff_Xn[61]) );
DFFRXLTS d_ff4_Xn_Q_reg_62_ ( .D(result_add_subt[62]), .CK(
d_ff4_Xn_net3827270), .RN(n428), .Q(d_ff_Xn[62]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_62_ ( .D(first_mux_X[62]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n428), .Q(d_ff2_X[62]) );
DFFRXLTS d_ff4_Xn_Q_reg_63_ ( .D(result_add_subt[63]), .CK(
d_ff4_Xn_net3827270), .RN(n428), .Q(d_ff_Xn[63]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_63_ ( .D(first_mux_X[63]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n428), .Q(d_ff2_X[63]) );
DFFRXLTS reg_shift_x_Q_reg_63_ ( .D(d_ff2_X[63]), .CK(reg_shift_y_net3827270), .RN(n428), .Q(d_ff3_sh_x_out[63]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3827270), .RN(n428), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n428), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3827270),
.RN(n428), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3827270), .RN(n428), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n428), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3827270),
.RN(n428), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3827270), .RN(n428), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n428), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3827270),
.RN(n741), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3827270), .RN(n428), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n741), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3827270),
.RN(n428), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3827270), .RN(n741), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n428), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3827270),
.RN(n741), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3827270), .RN(n428), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n741), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3827270),
.RN(n428), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3827270), .RN(n741), .Q(d_ff_Yn[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n741), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3827270),
.RN(n741), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3827270), .RN(n741), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n741), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3827270),
.RN(n741), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3827270), .RN(n741), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n741), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3827270),
.RN(n741), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3827270), .RN(n741), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n741), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3827270),
.RN(n741), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3827270), .RN(n741), .Q(d_ff_Yn[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n740), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3827270), .RN(n740), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3827270), .RN(n740), .Q(d_ff_Yn[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n740), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3827270), .RN(n740), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3827270), .RN(n740), .Q(d_ff_Yn[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n740), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3827270), .RN(n740), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3827270), .RN(n740), .Q(d_ff_Yn[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n740), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3827270), .RN(n740), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3827270), .RN(n740), .Q(d_ff_Yn[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n760), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3827270), .RN(n759), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3827270), .RN(n758), .Q(d_ff_Yn[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n738), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3827270), .RN(n737), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3827270), .RN(n739), .Q(d_ff_Yn[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n743), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3827270), .RN(n742), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3827270), .RN(n735), .Q(d_ff_Yn[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n746), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3827270), .RN(n744), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3827270), .RN(n722), .Q(d_ff_Yn[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n739), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3827270), .RN(n739), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3827270), .RN(n739), .Q(d_ff_Yn[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n739), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3827270), .RN(n739), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3827270), .RN(n739), .Q(d_ff_Yn[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n739), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3827270), .RN(n739), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3827270), .RN(n739), .Q(d_ff_Yn[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n739), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3827270), .RN(n739), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3827270), .RN(n739), .Q(d_ff_Yn[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n737), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3827270), .RN(n738), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3827270), .RN(n722), .Q(d_ff_Yn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n742), .Q(d_ff2_Y[23]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(d_ff2_Y[23]), .CK(reg_shift_y_net3827270), .RN(n740), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3827270), .RN(n723), .Q(d_ff_Yn[24]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n736), .Q(d_ff2_Y[24]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(d_ff2_Y[24]), .CK(reg_shift_y_net3827270), .RN(n734), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3827270), .RN(n757), .Q(d_ff_Yn[25]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n721), .Q(d_ff2_Y[25]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(d_ff2_Y[25]), .CK(reg_shift_y_net3827270), .RN(n764), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3827270), .RN(n724), .Q(d_ff_Yn[26]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n738), .Q(d_ff2_Y[26]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(d_ff2_Y[26]), .CK(reg_shift_y_net3827270), .RN(n738), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3827270), .RN(n738), .Q(d_ff_Yn[27]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n738), .Q(d_ff2_Y[27]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(d_ff2_Y[27]), .CK(reg_shift_y_net3827270), .RN(n738), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3827270), .RN(n738), .Q(d_ff_Yn[28]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n738), .Q(d_ff2_Y[28]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(d_ff2_Y[28]), .CK(reg_shift_y_net3827270), .RN(n738), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3827270), .RN(n738), .Q(d_ff_Yn[29]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n738), .Q(d_ff2_Y[29]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(d_ff2_Y[29]), .CK(reg_shift_y_net3827270), .RN(n738), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3827270), .RN(n738), .Q(d_ff_Yn[30]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n737), .Q(d_ff2_Y[30]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(d_ff2_Y[30]), .CK(reg_shift_y_net3827270), .RN(n737), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3827270), .RN(n737), .Q(d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n737), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3827270), .RN(n737), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_32_ ( .D(result_add_subt[32]), .CK(
d_ff4_Yn_net3827270), .RN(n737), .Q(d_ff_Yn[32]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_32_ ( .D(first_mux_Y[32]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n737), .Q(d_ff2_Y[32]) );
DFFRXLTS reg_shift_y_Q_reg_32_ ( .D(d_ff2_Y[32]), .CK(reg_shift_y_net3827270), .RN(n737), .Q(d_ff3_sh_y_out[32]) );
DFFRXLTS d_ff4_Yn_Q_reg_33_ ( .D(result_add_subt[33]), .CK(
d_ff4_Yn_net3827270), .RN(n737), .Q(d_ff_Yn[33]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_33_ ( .D(first_mux_Y[33]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n737), .Q(d_ff2_Y[33]) );
DFFRXLTS reg_shift_y_Q_reg_33_ ( .D(d_ff2_Y[33]), .CK(reg_shift_y_net3827270), .RN(n737), .Q(d_ff3_sh_y_out[33]) );
DFFRXLTS d_ff4_Yn_Q_reg_34_ ( .D(result_add_subt[34]), .CK(
d_ff4_Yn_net3827270), .RN(n737), .Q(d_ff_Yn[34]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_34_ ( .D(first_mux_Y[34]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n736), .Q(d_ff2_Y[34]) );
DFFRXLTS reg_shift_y_Q_reg_34_ ( .D(d_ff2_Y[34]), .CK(reg_shift_y_net3827270), .RN(n736), .Q(d_ff3_sh_y_out[34]) );
DFFRXLTS d_ff4_Yn_Q_reg_35_ ( .D(result_add_subt[35]), .CK(
d_ff4_Yn_net3827270), .RN(n736), .Q(d_ff_Yn[35]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_35_ ( .D(first_mux_Y[35]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n736), .Q(d_ff2_Y[35]) );
DFFRXLTS reg_shift_y_Q_reg_35_ ( .D(d_ff2_Y[35]), .CK(reg_shift_y_net3827270), .RN(n736), .Q(d_ff3_sh_y_out[35]) );
DFFRXLTS d_ff4_Yn_Q_reg_36_ ( .D(result_add_subt[36]), .CK(
d_ff4_Yn_net3827270), .RN(n736), .Q(d_ff_Yn[36]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_36_ ( .D(first_mux_Y[36]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n736), .Q(d_ff2_Y[36]) );
DFFRXLTS reg_shift_y_Q_reg_36_ ( .D(d_ff2_Y[36]), .CK(reg_shift_y_net3827270), .RN(n736), .Q(d_ff3_sh_y_out[36]) );
DFFRXLTS d_ff4_Yn_Q_reg_37_ ( .D(result_add_subt[37]), .CK(
d_ff4_Yn_net3827270), .RN(n736), .Q(d_ff_Yn[37]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_37_ ( .D(first_mux_Y[37]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n736), .Q(d_ff2_Y[37]) );
DFFRXLTS reg_shift_y_Q_reg_37_ ( .D(d_ff2_Y[37]), .CK(reg_shift_y_net3827270), .RN(n736), .Q(d_ff3_sh_y_out[37]) );
DFFRXLTS d_ff4_Yn_Q_reg_38_ ( .D(result_add_subt[38]), .CK(
d_ff4_Yn_net3827270), .RN(n736), .Q(d_ff_Yn[38]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_38_ ( .D(first_mux_Y[38]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n735), .Q(d_ff2_Y[38]) );
DFFRXLTS reg_shift_y_Q_reg_38_ ( .D(d_ff2_Y[38]), .CK(reg_shift_y_net3827270), .RN(n735), .Q(d_ff3_sh_y_out[38]) );
DFFRXLTS d_ff4_Yn_Q_reg_39_ ( .D(result_add_subt[39]), .CK(
d_ff4_Yn_net3827270), .RN(n735), .Q(d_ff_Yn[39]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_39_ ( .D(first_mux_Y[39]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n735), .Q(d_ff2_Y[39]) );
DFFRXLTS reg_shift_y_Q_reg_39_ ( .D(d_ff2_Y[39]), .CK(reg_shift_y_net3827270), .RN(n735), .Q(d_ff3_sh_y_out[39]) );
DFFRXLTS d_ff4_Yn_Q_reg_40_ ( .D(result_add_subt[40]), .CK(
d_ff4_Yn_net3827270), .RN(n735), .Q(d_ff_Yn[40]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_40_ ( .D(first_mux_Y[40]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n735), .Q(d_ff2_Y[40]) );
DFFRXLTS reg_shift_y_Q_reg_40_ ( .D(d_ff2_Y[40]), .CK(reg_shift_y_net3827270), .RN(n735), .Q(d_ff3_sh_y_out[40]) );
DFFRXLTS d_ff4_Yn_Q_reg_41_ ( .D(result_add_subt[41]), .CK(
d_ff4_Yn_net3827270), .RN(n735), .Q(d_ff_Yn[41]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_41_ ( .D(first_mux_Y[41]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n735), .Q(d_ff2_Y[41]) );
DFFRXLTS reg_shift_y_Q_reg_41_ ( .D(d_ff2_Y[41]), .CK(reg_shift_y_net3827270), .RN(n735), .Q(d_ff3_sh_y_out[41]) );
DFFRXLTS d_ff4_Yn_Q_reg_42_ ( .D(result_add_subt[42]), .CK(
d_ff4_Yn_net3827270), .RN(n735), .Q(d_ff_Yn[42]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_42_ ( .D(first_mux_Y[42]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n734), .Q(d_ff2_Y[42]) );
DFFRXLTS reg_shift_y_Q_reg_42_ ( .D(d_ff2_Y[42]), .CK(reg_shift_y_net3827270), .RN(n734), .Q(d_ff3_sh_y_out[42]) );
DFFRXLTS d_ff4_Yn_Q_reg_43_ ( .D(result_add_subt[43]), .CK(
d_ff4_Yn_net3827270), .RN(n734), .Q(d_ff_Yn[43]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_43_ ( .D(first_mux_Y[43]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n734), .Q(d_ff2_Y[43]) );
DFFRXLTS reg_shift_y_Q_reg_43_ ( .D(d_ff2_Y[43]), .CK(reg_shift_y_net3827270), .RN(n734), .Q(d_ff3_sh_y_out[43]) );
DFFRXLTS d_ff4_Yn_Q_reg_44_ ( .D(result_add_subt[44]), .CK(
d_ff4_Yn_net3827270), .RN(n734), .Q(d_ff_Yn[44]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_44_ ( .D(first_mux_Y[44]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n734), .Q(d_ff2_Y[44]) );
DFFRXLTS reg_shift_y_Q_reg_44_ ( .D(d_ff2_Y[44]), .CK(reg_shift_y_net3827270), .RN(n734), .Q(d_ff3_sh_y_out[44]) );
DFFRXLTS d_ff4_Yn_Q_reg_45_ ( .D(result_add_subt[45]), .CK(
d_ff4_Yn_net3827270), .RN(n734), .Q(d_ff_Yn[45]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_45_ ( .D(first_mux_Y[45]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n734), .Q(d_ff2_Y[45]) );
DFFRXLTS reg_shift_y_Q_reg_45_ ( .D(d_ff2_Y[45]), .CK(reg_shift_y_net3827270), .RN(n734), .Q(d_ff3_sh_y_out[45]) );
DFFRXLTS d_ff4_Yn_Q_reg_46_ ( .D(result_add_subt[46]), .CK(
d_ff4_Yn_net3827270), .RN(n734), .Q(d_ff_Yn[46]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_46_ ( .D(first_mux_Y[46]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n733), .Q(d_ff2_Y[46]) );
DFFRXLTS reg_shift_y_Q_reg_46_ ( .D(d_ff2_Y[46]), .CK(reg_shift_y_net3827270), .RN(n733), .Q(d_ff3_sh_y_out[46]) );
DFFRXLTS d_ff4_Yn_Q_reg_47_ ( .D(result_add_subt[47]), .CK(
d_ff4_Yn_net3827270), .RN(n733), .Q(d_ff_Yn[47]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_47_ ( .D(first_mux_Y[47]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n733), .Q(d_ff2_Y[47]) );
DFFRXLTS reg_shift_y_Q_reg_47_ ( .D(d_ff2_Y[47]), .CK(reg_shift_y_net3827270), .RN(n733), .Q(d_ff3_sh_y_out[47]) );
DFFRXLTS d_ff4_Yn_Q_reg_48_ ( .D(result_add_subt[48]), .CK(
d_ff4_Yn_net3827270), .RN(n733), .Q(d_ff_Yn[48]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_48_ ( .D(first_mux_Y[48]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n733), .Q(d_ff2_Y[48]) );
DFFRXLTS reg_shift_y_Q_reg_48_ ( .D(d_ff2_Y[48]), .CK(reg_shift_y_net3827270), .RN(n733), .Q(d_ff3_sh_y_out[48]) );
DFFRXLTS d_ff4_Yn_Q_reg_49_ ( .D(result_add_subt[49]), .CK(
d_ff4_Yn_net3827270), .RN(n733), .Q(d_ff_Yn[49]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_49_ ( .D(first_mux_Y[49]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n733), .Q(d_ff2_Y[49]) );
DFFRXLTS reg_shift_y_Q_reg_49_ ( .D(d_ff2_Y[49]), .CK(reg_shift_y_net3827270), .RN(n733), .Q(d_ff3_sh_y_out[49]) );
DFFRXLTS d_ff4_Yn_Q_reg_50_ ( .D(result_add_subt[50]), .CK(
d_ff4_Yn_net3827270), .RN(n733), .Q(d_ff_Yn[50]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_50_ ( .D(first_mux_Y[50]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n732), .Q(d_ff2_Y[50]) );
DFFRXLTS reg_shift_y_Q_reg_50_ ( .D(d_ff2_Y[50]), .CK(reg_shift_y_net3827270), .RN(n732), .Q(d_ff3_sh_y_out[50]) );
DFFRXLTS d_ff4_Yn_Q_reg_51_ ( .D(result_add_subt[51]), .CK(
d_ff4_Yn_net3827270), .RN(n732), .Q(d_ff_Yn[51]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_51_ ( .D(first_mux_Y[51]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n732), .Q(d_ff2_Y[51]) );
DFFRXLTS reg_shift_y_Q_reg_51_ ( .D(d_ff2_Y[51]), .CK(reg_shift_y_net3827270), .RN(n732), .Q(d_ff3_sh_y_out[51]) );
DFFRXLTS d_ff4_Yn_Q_reg_52_ ( .D(result_add_subt[52]), .CK(
d_ff4_Yn_net3827270), .RN(n732), .Q(d_ff_Yn[52]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_52_ ( .D(first_mux_Y[52]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n732), .Q(d_ff2_Y[52]), .QN(n431)
);
DFFRXLTS d_ff4_Yn_Q_reg_53_ ( .D(result_add_subt[53]), .CK(
d_ff4_Yn_net3827270), .RN(n732), .Q(d_ff_Yn[53]) );
DFFRXLTS d_ff4_Yn_Q_reg_54_ ( .D(result_add_subt[54]), .CK(
d_ff4_Yn_net3827270), .RN(n732), .Q(d_ff_Yn[54]) );
DFFRXLTS d_ff4_Yn_Q_reg_55_ ( .D(result_add_subt[55]), .CK(
d_ff4_Yn_net3827270), .RN(n732), .Q(d_ff_Yn[55]) );
DFFRXLTS d_ff4_Yn_Q_reg_56_ ( .D(result_add_subt[56]), .CK(
d_ff4_Yn_net3827270), .RN(n731), .Q(d_ff_Yn[56]) );
DFFRXLTS d_ff4_Yn_Q_reg_57_ ( .D(result_add_subt[57]), .CK(
d_ff4_Yn_net3827270), .RN(n731), .Q(d_ff_Yn[57]) );
DFFRXLTS d_ff4_Yn_Q_reg_58_ ( .D(result_add_subt[58]), .CK(
d_ff4_Yn_net3827270), .RN(n731), .Q(d_ff_Yn[58]) );
DFFRXLTS d_ff4_Yn_Q_reg_59_ ( .D(result_add_subt[59]), .CK(
d_ff4_Yn_net3827270), .RN(n731), .Q(d_ff_Yn[59]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_59_ ( .D(first_mux_Y[59]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n731), .Q(d_ff2_Y[59]), .QN(n432)
);
DFFRXLTS d_ff4_Yn_Q_reg_60_ ( .D(result_add_subt[60]), .CK(
d_ff4_Yn_net3827270), .RN(n731), .Q(d_ff_Yn[60]) );
DFFRXLTS d_ff4_Yn_Q_reg_61_ ( .D(result_add_subt[61]), .CK(
d_ff4_Yn_net3827270), .RN(n731), .Q(d_ff_Yn[61]) );
DFFRXLTS d_ff4_Yn_Q_reg_62_ ( .D(result_add_subt[62]), .CK(
d_ff4_Yn_net3827270), .RN(n730), .Q(d_ff_Yn[62]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_62_ ( .D(first_mux_Y[62]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n730), .Q(d_ff2_Y[62]) );
DFFRXLTS d_ff4_Yn_Q_reg_63_ ( .D(result_add_subt[63]), .CK(
d_ff4_Yn_net3827270), .RN(n730), .Q(d_ff_Yn[63]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_63_ ( .D(first_mux_Y[63]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n730), .Q(d_ff2_Y[63]) );
DFFRXLTS reg_shift_y_Q_reg_63_ ( .D(d_ff2_Y[63]), .CK(reg_shift_y_net3827270), .RN(n730), .Q(d_ff3_sh_y_out[63]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3827270), .RN(n730), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n730), .Q(d_ff2_Z[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3827270), .RN(n730), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n730), .Q(d_ff2_Z[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3827270), .RN(n730), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n730), .Q(d_ff2_Z[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3827270), .RN(n729), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n729), .Q(d_ff2_Z[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3827270), .RN(n729), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n729), .Q(d_ff2_Z[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3827270), .RN(n729), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n729), .Q(d_ff2_Z[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3827270), .RN(n729), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n729), .Q(d_ff2_Z[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3827270), .RN(n729), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n729), .Q(d_ff2_Z[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3827270), .RN(n729), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n729), .Q(d_ff2_Z[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3827270), .RN(n728), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n728), .Q(d_ff2_Z[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3827270), .RN(n728), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n728), .Q(d_ff2_Z[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3827270), .RN(n728), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n728), .Q(d_ff2_Z[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3827270), .RN(n728), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n728), .Q(d_ff2_Z[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3827270), .RN(n728), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n728), .Q(d_ff2_Z[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3827270), .RN(n728), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n728), .Q(d_ff2_Z[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3827270), .RN(n727), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n727), .Q(d_ff2_Z[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3827270), .RN(n727), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n727), .Q(d_ff2_Z[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3827270), .RN(n727), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n727), .Q(d_ff2_Z[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3827270), .RN(n727), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n727), .Q(d_ff2_Z[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3827270), .RN(n727), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n727), .Q(d_ff2_Z[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3827270), .RN(n727), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n727), .Q(d_ff2_Z[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3827270), .RN(n726), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n726), .Q(d_ff2_Z[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3827270), .RN(n726), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n726), .Q(d_ff2_Z[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3827270), .RN(n726), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n726), .Q(d_ff2_Z[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3827270), .RN(n726), .Q(d_ff_Zn[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n726), .Q(d_ff2_Z[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3827270), .RN(n726), .Q(d_ff_Zn[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n726), .Q(d_ff2_Z[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3827270), .RN(n726), .Q(d_ff_Zn[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n726), .Q(d_ff2_Z[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3827270), .RN(n725), .Q(d_ff_Zn[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n725), .Q(d_ff2_Z[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3827270), .RN(n725), .Q(d_ff_Zn[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n725), .Q(d_ff2_Z[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3827270), .RN(n725), .Q(d_ff_Zn[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n725), .Q(d_ff2_Z[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3827270), .RN(n725), .Q(d_ff_Zn[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n725), .Q(d_ff2_Z[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3827270), .RN(n725), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n725), .Q(d_ff2_Z[31]) );
DFFRXLTS d_ff4_Zn_Q_reg_32_ ( .D(result_add_subt[32]), .CK(
d_ff4_Zn_net3827270), .RN(n725), .Q(d_ff_Zn[32]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_32_ ( .D(first_mux_Z[32]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n725), .Q(d_ff2_Z[32]) );
DFFRXLTS d_ff4_Zn_Q_reg_33_ ( .D(result_add_subt[33]), .CK(
d_ff4_Zn_net3827270), .RN(n724), .Q(d_ff_Zn[33]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_33_ ( .D(first_mux_Z[33]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n724), .Q(d_ff2_Z[33]) );
DFFRXLTS d_ff4_Zn_Q_reg_34_ ( .D(result_add_subt[34]), .CK(
d_ff4_Zn_net3827270), .RN(n724), .Q(d_ff_Zn[34]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_34_ ( .D(first_mux_Z[34]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n724), .Q(d_ff2_Z[34]) );
DFFRXLTS d_ff4_Zn_Q_reg_35_ ( .D(result_add_subt[35]), .CK(
d_ff4_Zn_net3827270), .RN(n724), .Q(d_ff_Zn[35]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_35_ ( .D(first_mux_Z[35]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n724), .Q(d_ff2_Z[35]) );
DFFRXLTS d_ff4_Zn_Q_reg_36_ ( .D(result_add_subt[36]), .CK(
d_ff4_Zn_net3827270), .RN(n724), .Q(d_ff_Zn[36]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_36_ ( .D(first_mux_Z[36]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n724), .Q(d_ff2_Z[36]) );
DFFRXLTS d_ff4_Zn_Q_reg_37_ ( .D(result_add_subt[37]), .CK(
d_ff4_Zn_net3827270), .RN(n724), .Q(d_ff_Zn[37]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_37_ ( .D(first_mux_Z[37]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n724), .Q(d_ff2_Z[37]) );
DFFRXLTS d_ff4_Zn_Q_reg_38_ ( .D(result_add_subt[38]), .CK(
d_ff4_Zn_net3827270), .RN(n724), .Q(d_ff_Zn[38]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_38_ ( .D(first_mux_Z[38]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n724), .Q(d_ff2_Z[38]) );
DFFRXLTS d_ff4_Zn_Q_reg_39_ ( .D(result_add_subt[39]), .CK(
d_ff4_Zn_net3827270), .RN(n723), .Q(d_ff_Zn[39]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_39_ ( .D(first_mux_Z[39]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n723), .Q(d_ff2_Z[39]) );
DFFRXLTS d_ff4_Zn_Q_reg_40_ ( .D(result_add_subt[40]), .CK(
d_ff4_Zn_net3827270), .RN(n723), .Q(d_ff_Zn[40]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_40_ ( .D(first_mux_Z[40]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n723), .Q(d_ff2_Z[40]) );
DFFRXLTS d_ff4_Zn_Q_reg_41_ ( .D(result_add_subt[41]), .CK(
d_ff4_Zn_net3827270), .RN(n723), .Q(d_ff_Zn[41]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_41_ ( .D(first_mux_Z[41]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n723), .Q(d_ff2_Z[41]) );
DFFRXLTS d_ff4_Zn_Q_reg_42_ ( .D(result_add_subt[42]), .CK(
d_ff4_Zn_net3827270), .RN(n723), .Q(d_ff_Zn[42]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_42_ ( .D(first_mux_Z[42]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n723), .Q(d_ff2_Z[42]) );
DFFRXLTS d_ff4_Zn_Q_reg_43_ ( .D(result_add_subt[43]), .CK(
d_ff4_Zn_net3827270), .RN(n723), .Q(d_ff_Zn[43]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_43_ ( .D(first_mux_Z[43]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n723), .Q(d_ff2_Z[43]) );
DFFRXLTS d_ff4_Zn_Q_reg_44_ ( .D(result_add_subt[44]), .CK(
d_ff4_Zn_net3827270), .RN(n723), .Q(d_ff_Zn[44]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_44_ ( .D(first_mux_Z[44]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n723), .Q(d_ff2_Z[44]) );
DFFRXLTS d_ff4_Zn_Q_reg_45_ ( .D(result_add_subt[45]), .CK(
d_ff4_Zn_net3827270), .RN(n722), .Q(d_ff_Zn[45]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_45_ ( .D(first_mux_Z[45]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n722), .Q(d_ff2_Z[45]) );
DFFRXLTS d_ff4_Zn_Q_reg_46_ ( .D(result_add_subt[46]), .CK(
d_ff4_Zn_net3827270), .RN(n722), .Q(d_ff_Zn[46]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_46_ ( .D(first_mux_Z[46]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n722), .Q(d_ff2_Z[46]) );
DFFRXLTS d_ff4_Zn_Q_reg_47_ ( .D(result_add_subt[47]), .CK(
d_ff4_Zn_net3827270), .RN(n722), .Q(d_ff_Zn[47]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_47_ ( .D(first_mux_Z[47]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n722), .Q(d_ff2_Z[47]) );
DFFRXLTS d_ff4_Zn_Q_reg_48_ ( .D(result_add_subt[48]), .CK(
d_ff4_Zn_net3827270), .RN(n722), .Q(d_ff_Zn[48]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_48_ ( .D(first_mux_Z[48]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n722), .Q(d_ff2_Z[48]) );
DFFRXLTS d_ff4_Zn_Q_reg_49_ ( .D(result_add_subt[49]), .CK(
d_ff4_Zn_net3827270), .RN(n722), .Q(d_ff_Zn[49]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_49_ ( .D(first_mux_Z[49]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n722), .Q(d_ff2_Z[49]) );
DFFRXLTS d_ff4_Zn_Q_reg_50_ ( .D(result_add_subt[50]), .CK(
d_ff4_Zn_net3827270), .RN(n722), .Q(d_ff_Zn[50]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_50_ ( .D(first_mux_Z[50]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n722), .Q(d_ff2_Z[50]) );
DFFRXLTS d_ff4_Zn_Q_reg_51_ ( .D(result_add_subt[51]), .CK(
d_ff4_Zn_net3827270), .RN(n721), .Q(d_ff_Zn[51]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_51_ ( .D(first_mux_Z[51]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n721), .Q(d_ff2_Z[51]) );
DFFRXLTS d_ff4_Zn_Q_reg_52_ ( .D(result_add_subt[52]), .CK(
d_ff4_Zn_net3827270), .RN(n721), .Q(d_ff_Zn[52]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_52_ ( .D(first_mux_Z[52]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n721), .Q(d_ff2_Z[52]) );
DFFRXLTS d_ff4_Zn_Q_reg_53_ ( .D(result_add_subt[53]), .CK(
d_ff4_Zn_net3827270), .RN(n721), .Q(d_ff_Zn[53]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_53_ ( .D(first_mux_Z[53]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n721), .Q(d_ff2_Z[53]) );
DFFRXLTS d_ff4_Zn_Q_reg_54_ ( .D(result_add_subt[54]), .CK(
d_ff4_Zn_net3827270), .RN(n721), .Q(d_ff_Zn[54]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_54_ ( .D(first_mux_Z[54]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n721), .Q(d_ff2_Z[54]) );
DFFRXLTS d_ff4_Zn_Q_reg_55_ ( .D(result_add_subt[55]), .CK(
d_ff4_Zn_net3827270), .RN(n721), .Q(d_ff_Zn[55]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_55_ ( .D(first_mux_Z[55]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n721), .Q(d_ff2_Z[55]) );
DFFRXLTS d_ff4_Zn_Q_reg_56_ ( .D(result_add_subt[56]), .CK(
d_ff4_Zn_net3827270), .RN(n721), .Q(d_ff_Zn[56]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_56_ ( .D(first_mux_Z[56]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n721), .Q(d_ff2_Z[56]) );
DFFRXLTS d_ff4_Zn_Q_reg_57_ ( .D(result_add_subt[57]), .CK(
d_ff4_Zn_net3827270), .RN(n720), .Q(d_ff_Zn[57]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_57_ ( .D(first_mux_Z[57]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n720), .Q(d_ff2_Z[57]) );
DFFRXLTS d_ff4_Zn_Q_reg_58_ ( .D(result_add_subt[58]), .CK(
d_ff4_Zn_net3827270), .RN(n720), .Q(d_ff_Zn[58]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_58_ ( .D(first_mux_Z[58]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n720), .Q(d_ff2_Z[58]) );
DFFRXLTS d_ff4_Zn_Q_reg_59_ ( .D(result_add_subt[59]), .CK(
d_ff4_Zn_net3827270), .RN(n720), .Q(d_ff_Zn[59]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_59_ ( .D(first_mux_Z[59]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n720), .Q(d_ff2_Z[59]) );
DFFRXLTS d_ff4_Zn_Q_reg_60_ ( .D(result_add_subt[60]), .CK(
d_ff4_Zn_net3827270), .RN(n720), .Q(d_ff_Zn[60]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_60_ ( .D(first_mux_Z[60]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n720), .Q(d_ff2_Z[60]) );
DFFRXLTS d_ff4_Zn_Q_reg_61_ ( .D(result_add_subt[61]), .CK(
d_ff4_Zn_net3827270), .RN(n720), .Q(d_ff_Zn[61]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_61_ ( .D(first_mux_Z[61]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n720), .Q(d_ff2_Z[61]) );
DFFRXLTS d_ff4_Zn_Q_reg_62_ ( .D(result_add_subt[62]), .CK(
d_ff4_Zn_net3827270), .RN(n720), .Q(d_ff_Zn[62]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_62_ ( .D(first_mux_Z[62]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n720), .Q(d_ff2_Z[62]) );
DFFRXLTS d_ff4_Zn_Q_reg_63_ ( .D(result_add_subt[63]), .CK(
d_ff4_Zn_net3827270), .RN(n744), .Q(d_ff_Zn[63]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_63_ ( .D(first_mux_Z[63]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n745), .Q(d_ff2_Z[63]) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[63]), .CK(reg_shift_y_net3827270),
.RN(n746), .Q(d_ff3_sign_out) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(mux_sal[0]), .CK(d_ff5_net3827270), .RN(n735),
.Q(sign_inv_out[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(sign_inv_out[0]), .CK(
d_ff5_data_out_net3827270), .RN(n740), .Q(data_output[0]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(mux_sal[1]), .CK(d_ff5_net3827270), .RN(n724),
.Q(sign_inv_out[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(sign_inv_out[1]), .CK(
d_ff5_data_out_net3827270), .RN(n723), .Q(data_output[1]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(mux_sal[2]), .CK(d_ff5_net3827270), .RN(n736),
.Q(sign_inv_out[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(sign_inv_out[2]), .CK(
d_ff5_data_out_net3827270), .RN(n734), .Q(data_output[2]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(mux_sal[3]), .CK(d_ff5_net3827270), .RN(n761),
.Q(sign_inv_out[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(sign_inv_out[3]), .CK(
d_ff5_data_out_net3827270), .RN(n721), .Q(data_output[3]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(mux_sal[4]), .CK(d_ff5_net3827270), .RN(n763),
.Q(sign_inv_out[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(sign_inv_out[4]), .CK(
d_ff5_data_out_net3827270), .RN(n721), .Q(data_output[4]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(mux_sal[5]), .CK(d_ff5_net3827270), .RN(n743),
.Q(sign_inv_out[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(sign_inv_out[5]), .CK(
d_ff5_data_out_net3827270), .RN(n757), .Q(data_output[5]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(mux_sal[6]), .CK(d_ff5_net3827270), .RN(n724),
.Q(sign_inv_out[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(sign_inv_out[6]), .CK(
d_ff5_data_out_net3827270), .RN(n739), .Q(data_output[6]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(mux_sal[7]), .CK(d_ff5_net3827270), .RN(n756),
.Q(sign_inv_out[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(sign_inv_out[7]), .CK(
d_ff5_data_out_net3827270), .RN(n740), .Q(data_output[7]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(mux_sal[8]), .CK(d_ff5_net3827270), .RN(n720),
.Q(sign_inv_out[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(sign_inv_out[8]), .CK(
d_ff5_data_out_net3827270), .RN(n737), .Q(data_output[8]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(mux_sal[9]), .CK(d_ff5_net3827270), .RN(n738),
.Q(sign_inv_out[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(sign_inv_out[9]), .CK(
d_ff5_data_out_net3827270), .RN(n745), .Q(data_output[9]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(mux_sal[10]), .CK(d_ff5_net3827270), .RN(n720),
.Q(sign_inv_out[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(sign_inv_out[10]), .CK(
d_ff5_data_out_net3827270), .RN(n744), .Q(data_output[10]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(mux_sal[11]), .CK(d_ff5_net3827270), .RN(n745),
.Q(sign_inv_out[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(sign_inv_out[11]), .CK(
d_ff5_data_out_net3827270), .RN(n746), .Q(data_output[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(mux_sal[12]), .CK(d_ff5_net3827270), .RN(n735),
.Q(sign_inv_out[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(sign_inv_out[12]), .CK(
d_ff5_data_out_net3827270), .RN(n723), .Q(data_output[12]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(mux_sal[13]), .CK(d_ff5_net3827270), .RN(n736),
.Q(sign_inv_out[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(sign_inv_out[13]), .CK(
d_ff5_data_out_net3827270), .RN(n734), .Q(data_output[13]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(mux_sal[14]), .CK(d_ff5_net3827270), .RN(n722),
.Q(sign_inv_out[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(sign_inv_out[14]), .CK(
d_ff5_data_out_net3827270), .RN(n720), .Q(data_output[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(mux_sal[15]), .CK(d_ff5_net3827270), .RN(n742),
.Q(sign_inv_out[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(sign_inv_out[15]), .CK(
d_ff5_data_out_net3827270), .RN(n743), .Q(data_output[15]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(mux_sal[16]), .CK(d_ff5_net3827270), .RN(n739),
.Q(sign_inv_out[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(sign_inv_out[16]), .CK(
d_ff5_data_out_net3827270), .RN(n717), .Q(data_output[16]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(mux_sal[17]), .CK(d_ff5_net3827270), .RN(n717),
.Q(sign_inv_out[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(sign_inv_out[17]), .CK(
d_ff5_data_out_net3827270), .RN(n755), .Q(data_output[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(mux_sal[18]), .CK(d_ff5_net3827270), .RN(n717),
.Q(sign_inv_out[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(sign_inv_out[18]), .CK(
d_ff5_data_out_net3827270), .RN(n753), .Q(data_output[18]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(mux_sal[19]), .CK(d_ff5_net3827270), .RN(n718),
.Q(sign_inv_out[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(sign_inv_out[19]), .CK(
d_ff5_data_out_net3827270), .RN(n733), .Q(data_output[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(mux_sal[20]), .CK(d_ff5_net3827270), .RN(n728),
.Q(sign_inv_out[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(sign_inv_out[20]), .CK(
d_ff5_data_out_net3827270), .RN(n731), .Q(data_output[20]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(mux_sal[21]), .CK(d_ff5_net3827270), .RN(n433),
.Q(sign_inv_out[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(sign_inv_out[21]), .CK(
d_ff5_data_out_net3827270), .RN(n754), .Q(data_output[21]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(mux_sal[22]), .CK(d_ff5_net3827270), .RN(n732),
.Q(sign_inv_out[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(sign_inv_out[22]), .CK(
d_ff5_data_out_net3827270), .RN(n753), .Q(data_output[22]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(mux_sal[23]), .CK(d_ff5_net3827270), .RN(n754),
.Q(sign_inv_out[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(sign_inv_out[23]), .CK(
d_ff5_data_out_net3827270), .RN(n755), .Q(data_output[23]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(mux_sal[24]), .CK(d_ff5_net3827270), .RN(n750),
.Q(sign_inv_out[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(sign_inv_out[24]), .CK(
d_ff5_data_out_net3827270), .RN(n751), .Q(data_output[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(mux_sal[25]), .CK(d_ff5_net3827270), .RN(n752),
.Q(sign_inv_out[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(sign_inv_out[25]), .CK(
d_ff5_data_out_net3827270), .RN(n747), .Q(data_output[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(mux_sal[26]), .CK(d_ff5_net3827270), .RN(n748),
.Q(sign_inv_out[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(sign_inv_out[26]), .CK(
d_ff5_data_out_net3827270), .RN(n749), .Q(data_output[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(mux_sal[27]), .CK(d_ff5_net3827270), .RN(n754),
.Q(sign_inv_out[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(sign_inv_out[27]), .CK(
d_ff5_data_out_net3827270), .RN(n719), .Q(data_output[27]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(mux_sal[28]), .CK(d_ff5_net3827270), .RN(n753),
.Q(sign_inv_out[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(sign_inv_out[28]), .CK(
d_ff5_data_out_net3827270), .RN(n719), .Q(data_output[28]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(mux_sal[29]), .CK(d_ff5_net3827270), .RN(n719),
.Q(sign_inv_out[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(sign_inv_out[29]), .CK(
d_ff5_data_out_net3827270), .RN(n719), .Q(data_output[29]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(mux_sal[30]), .CK(d_ff5_net3827270), .RN(n719),
.Q(sign_inv_out[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(sign_inv_out[30]), .CK(
d_ff5_data_out_net3827270), .RN(n719), .Q(data_output[30]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(mux_sal[31]), .CK(d_ff5_net3827270), .RN(n719),
.Q(sign_inv_out[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(sign_inv_out[31]), .CK(
d_ff5_data_out_net3827270), .RN(n719), .Q(data_output[31]) );
DFFRXLTS d_ff5_Q_reg_32_ ( .D(mux_sal[32]), .CK(d_ff5_net3827270), .RN(n719),
.Q(sign_inv_out[32]) );
DFFRXLTS d_ff5_data_out_Q_reg_32_ ( .D(sign_inv_out[32]), .CK(
d_ff5_data_out_net3827270), .RN(n719), .Q(data_output[32]) );
DFFRXLTS d_ff5_Q_reg_33_ ( .D(mux_sal[33]), .CK(d_ff5_net3827270), .RN(n719),
.Q(sign_inv_out[33]) );
DFFRXLTS d_ff5_data_out_Q_reg_33_ ( .D(sign_inv_out[33]), .CK(
d_ff5_data_out_net3827270), .RN(n719), .Q(data_output[33]) );
DFFRXLTS d_ff5_Q_reg_34_ ( .D(mux_sal[34]), .CK(d_ff5_net3827270), .RN(n719),
.Q(sign_inv_out[34]) );
DFFRXLTS d_ff5_data_out_Q_reg_34_ ( .D(sign_inv_out[34]), .CK(
d_ff5_data_out_net3827270), .RN(n755), .Q(data_output[34]) );
DFFRXLTS d_ff5_Q_reg_35_ ( .D(mux_sal[35]), .CK(d_ff5_net3827270), .RN(n750),
.Q(sign_inv_out[35]) );
DFFRXLTS d_ff5_data_out_Q_reg_35_ ( .D(sign_inv_out[35]), .CK(
d_ff5_data_out_net3827270), .RN(n751), .Q(data_output[35]) );
DFFRXLTS d_ff5_Q_reg_36_ ( .D(mux_sal[36]), .CK(d_ff5_net3827270), .RN(n752),
.Q(sign_inv_out[36]) );
DFFRXLTS d_ff5_data_out_Q_reg_36_ ( .D(sign_inv_out[36]), .CK(
d_ff5_data_out_net3827270), .RN(n747), .Q(data_output[36]) );
DFFRXLTS d_ff5_Q_reg_37_ ( .D(mux_sal[37]), .CK(d_ff5_net3827270), .RN(n748),
.Q(sign_inv_out[37]) );
DFFRXLTS d_ff5_data_out_Q_reg_37_ ( .D(sign_inv_out[37]), .CK(
d_ff5_data_out_net3827270), .RN(n749), .Q(data_output[37]) );
DFFRXLTS d_ff5_Q_reg_38_ ( .D(mux_sal[38]), .CK(d_ff5_net3827270), .RN(n719),
.Q(sign_inv_out[38]) );
DFFRXLTS d_ff5_data_out_Q_reg_38_ ( .D(sign_inv_out[38]), .CK(
d_ff5_data_out_net3827270), .RN(n750), .Q(data_output[38]) );
DFFRXLTS d_ff5_Q_reg_39_ ( .D(mux_sal[39]), .CK(d_ff5_net3827270), .RN(n751),
.Q(sign_inv_out[39]) );
DFFRXLTS d_ff5_data_out_Q_reg_39_ ( .D(sign_inv_out[39]), .CK(
d_ff5_data_out_net3827270), .RN(n752), .Q(data_output[39]) );
DFFRXLTS d_ff5_Q_reg_40_ ( .D(mux_sal[40]), .CK(d_ff5_net3827270), .RN(n747),
.Q(sign_inv_out[40]) );
DFFRXLTS d_ff5_data_out_Q_reg_40_ ( .D(sign_inv_out[40]), .CK(
d_ff5_data_out_net3827270), .RN(n732), .Q(data_output[40]) );
DFFRXLTS d_ff5_Q_reg_41_ ( .D(mux_sal[41]), .CK(d_ff5_net3827270), .RN(n733),
.Q(sign_inv_out[41]) );
DFFRXLTS d_ff5_data_out_Q_reg_41_ ( .D(sign_inv_out[41]), .CK(
d_ff5_data_out_net3827270), .RN(n728), .Q(data_output[41]) );
DFFRXLTS d_ff5_Q_reg_42_ ( .D(mux_sal[42]), .CK(d_ff5_net3827270), .RN(n729),
.Q(sign_inv_out[42]) );
DFFRXLTS d_ff5_data_out_Q_reg_42_ ( .D(sign_inv_out[42]), .CK(
d_ff5_data_out_net3827270), .RN(n730), .Q(data_output[42]) );
DFFRXLTS d_ff5_Q_reg_43_ ( .D(mux_sal[43]), .CK(d_ff5_net3827270), .RN(n725),
.Q(sign_inv_out[43]) );
DFFRXLTS d_ff5_data_out_Q_reg_43_ ( .D(sign_inv_out[43]), .CK(
d_ff5_data_out_net3827270), .RN(n726), .Q(data_output[43]) );
DFFRXLTS d_ff5_Q_reg_44_ ( .D(mux_sal[44]), .CK(d_ff5_net3827270), .RN(n727),
.Q(sign_inv_out[44]) );
DFFRXLTS d_ff5_data_out_Q_reg_44_ ( .D(sign_inv_out[44]), .CK(
d_ff5_data_out_net3827270), .RN(n733), .Q(data_output[44]) );
DFFRXLTS d_ff5_Q_reg_45_ ( .D(mux_sal[45]), .CK(d_ff5_net3827270), .RN(n718),
.Q(sign_inv_out[45]) );
DFFRXLTS d_ff5_data_out_Q_reg_45_ ( .D(sign_inv_out[45]), .CK(
d_ff5_data_out_net3827270), .RN(n731), .Q(data_output[45]) );
DFFRXLTS d_ff5_Q_reg_46_ ( .D(mux_sal[46]), .CK(d_ff5_net3827270), .RN(n732),
.Q(sign_inv_out[46]) );
DFFRXLTS d_ff5_data_out_Q_reg_46_ ( .D(sign_inv_out[46]), .CK(
d_ff5_data_out_net3827270), .RN(n718), .Q(data_output[46]) );
DFFRXLTS d_ff5_Q_reg_47_ ( .D(mux_sal[47]), .CK(d_ff5_net3827270), .RN(n718),
.Q(sign_inv_out[47]) );
DFFRXLTS d_ff5_data_out_Q_reg_47_ ( .D(sign_inv_out[47]), .CK(
d_ff5_data_out_net3827270), .RN(n718), .Q(data_output[47]) );
DFFRXLTS d_ff5_Q_reg_48_ ( .D(mux_sal[48]), .CK(d_ff5_net3827270), .RN(n718),
.Q(sign_inv_out[48]) );
DFFRXLTS d_ff5_data_out_Q_reg_48_ ( .D(sign_inv_out[48]), .CK(
d_ff5_data_out_net3827270), .RN(n718), .Q(data_output[48]) );
DFFRXLTS d_ff5_Q_reg_49_ ( .D(mux_sal[49]), .CK(d_ff5_net3827270), .RN(n718),
.Q(sign_inv_out[49]) );
DFFRXLTS d_ff5_data_out_Q_reg_49_ ( .D(sign_inv_out[49]), .CK(
d_ff5_data_out_net3827270), .RN(n718), .Q(data_output[49]) );
DFFRXLTS d_ff5_Q_reg_50_ ( .D(mux_sal[50]), .CK(d_ff5_net3827270), .RN(n718),
.Q(sign_inv_out[50]) );
DFFRXLTS d_ff5_data_out_Q_reg_50_ ( .D(sign_inv_out[50]), .CK(
d_ff5_data_out_net3827270), .RN(n718), .Q(data_output[50]) );
DFFRXLTS d_ff5_Q_reg_51_ ( .D(mux_sal[51]), .CK(d_ff5_net3827270), .RN(n718),
.Q(sign_inv_out[51]) );
DFFRXLTS d_ff5_data_out_Q_reg_51_ ( .D(sign_inv_out[51]), .CK(
d_ff5_data_out_net3827270), .RN(n718), .Q(data_output[51]) );
DFFRXLTS d_ff5_Q_reg_52_ ( .D(mux_sal[52]), .CK(d_ff5_net3827270), .RN(n718),
.Q(sign_inv_out[52]) );
DFFRXLTS d_ff5_data_out_Q_reg_52_ ( .D(sign_inv_out[52]), .CK(
d_ff5_data_out_net3827270), .RN(n728), .Q(data_output[52]) );
DFFRXLTS d_ff5_Q_reg_53_ ( .D(mux_sal[53]), .CK(d_ff5_net3827270), .RN(n729),
.Q(sign_inv_out[53]) );
DFFRXLTS d_ff5_data_out_Q_reg_53_ ( .D(sign_inv_out[53]), .CK(
d_ff5_data_out_net3827270), .RN(n730), .Q(data_output[53]) );
DFFRXLTS d_ff5_Q_reg_54_ ( .D(mux_sal[54]), .CK(d_ff5_net3827270), .RN(n725),
.Q(sign_inv_out[54]) );
DFFRXLTS d_ff5_data_out_Q_reg_54_ ( .D(sign_inv_out[54]), .CK(
d_ff5_data_out_net3827270), .RN(n726), .Q(data_output[54]) );
DFFRXLTS d_ff5_Q_reg_55_ ( .D(mux_sal[55]), .CK(d_ff5_net3827270), .RN(n727),
.Q(sign_inv_out[55]) );
DFFRXLTS d_ff5_data_out_Q_reg_55_ ( .D(sign_inv_out[55]), .CK(
d_ff5_data_out_net3827270), .RN(n718), .Q(data_output[55]) );
DFFRXLTS d_ff5_Q_reg_56_ ( .D(mux_sal[56]), .CK(d_ff5_net3827270), .RN(n731),
.Q(sign_inv_out[56]) );
DFFRXLTS d_ff5_data_out_Q_reg_56_ ( .D(sign_inv_out[56]), .CK(
d_ff5_data_out_net3827270), .RN(n729), .Q(data_output[56]) );
DFFRXLTS d_ff5_Q_reg_57_ ( .D(mux_sal[57]), .CK(d_ff5_net3827270), .RN(n730),
.Q(sign_inv_out[57]) );
DFFRXLTS d_ff5_data_out_Q_reg_57_ ( .D(sign_inv_out[57]), .CK(
d_ff5_data_out_net3827270), .RN(n725), .Q(data_output[57]) );
DFFRXLTS d_ff5_Q_reg_58_ ( .D(mux_sal[58]), .CK(d_ff5_net3827270), .RN(n726),
.Q(sign_inv_out[58]) );
DFFRXLTS d_ff5_data_out_Q_reg_58_ ( .D(sign_inv_out[58]), .CK(
d_ff5_data_out_net3827270), .RN(n717), .Q(data_output[58]) );
DFFRXLTS d_ff5_Q_reg_59_ ( .D(mux_sal[59]), .CK(d_ff5_net3827270), .RN(n717),
.Q(sign_inv_out[59]) );
DFFRXLTS d_ff5_data_out_Q_reg_59_ ( .D(sign_inv_out[59]), .CK(
d_ff5_data_out_net3827270), .RN(n717), .Q(data_output[59]) );
DFFRXLTS d_ff5_Q_reg_60_ ( .D(mux_sal[60]), .CK(d_ff5_net3827270), .RN(n717),
.Q(sign_inv_out[60]) );
DFFRXLTS d_ff5_data_out_Q_reg_60_ ( .D(sign_inv_out[60]), .CK(
d_ff5_data_out_net3827270), .RN(n717), .Q(data_output[60]) );
DFFRXLTS d_ff5_Q_reg_61_ ( .D(mux_sal[61]), .CK(d_ff5_net3827270), .RN(n717),
.Q(sign_inv_out[61]) );
DFFRXLTS d_ff5_data_out_Q_reg_61_ ( .D(sign_inv_out[61]), .CK(
d_ff5_data_out_net3827270), .RN(n717), .Q(data_output[61]) );
DFFRXLTS d_ff5_Q_reg_62_ ( .D(mux_sal[62]), .CK(d_ff5_net3827270), .RN(n717),
.Q(sign_inv_out[62]) );
DFFRXLTS d_ff5_data_out_Q_reg_62_ ( .D(sign_inv_out[62]), .CK(
d_ff5_data_out_net3827270), .RN(n717), .Q(data_output[62]) );
DFFRXLTS d_ff5_Q_reg_63_ ( .D(mux_sal[63]), .CK(d_ff5_net3827270), .RN(n717),
.Q(data_output2_63_) );
DFFRXLTS d_ff5_data_out_Q_reg_63_ ( .D(sign_inv_out[63]), .CK(
d_ff5_data_out_net3827270), .RN(n717), .Q(data_output[63]) );
SNPS_CLOCK_GATE_HIGH_CORDIC_Arch2v1_W64_EW11_SW52_SWR55_EWR6_1 clk_gate_reg_ch_mux_2_Q_reg (
.CLK(clk), .EN(n770), .ENCLK(n768), .TE(1'b0) );
DFFRXLTS reg_LUT_Q_reg_48_ ( .D(1'b1), .CK(reg_shift_y_net3827270), .RN(n717), .Q(d_ff3_LUT_out[48]) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3827270), .RN(n766), .Q(d_ff1_shift_region_flag_out[0]),
.QN(n713) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n290), .CK(n768), .RN(n766), .Q(
cont_var_out[1]), .QN(n709) );
DFFRX2TS cont_iter_count_reg_1_ ( .D(n772), .CK(cont_iter_net3827306), .RN(
n766), .Q(cont_iter_out[1]), .QN(n708) );
DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n276), .Q(cordic_FSM_state_reg[1]), .QN(n707) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n289), .CK(n768), .RN(n766), .Q(
cont_var_out[0]), .QN(n705) );
DFFRX2TS cont_iter_count_reg_2_ ( .D(n771), .CK(cont_iter_net3827306), .RN(
n766), .Q(cont_iter_out[2]), .QN(n703) );
DFFRX4TS cont_iter_count_reg_0_ ( .D(n773), .CK(cont_iter_net3827306), .RN(
n766), .Q(n716), .QN(n767) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_59_ ( .D(first_mux_X[59]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n742), .Q(d_ff2_X[59]), .QN(n710)
);
DFFRX1TS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3827270),
.RN(n766), .Q(d_ff1_operation_out) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_56_ ( .D(first_mux_Y[56]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n731), .Q(d_ff2_Y[56]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_56_ ( .D(first_mux_X[56]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n742), .Q(d_ff2_X[56]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_61_ ( .D(first_mux_Y[61]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n730), .Q(d_ff2_Y[61]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_61_ ( .D(first_mux_X[61]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n742), .Q(d_ff2_X[61]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_60_ ( .D(first_mux_Y[60]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n731), .Q(d_ff2_Y[60]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_58_ ( .D(first_mux_Y[58]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n731), .Q(d_ff2_Y[58]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_60_ ( .D(first_mux_X[60]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n742), .Q(d_ff2_X[60]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_58_ ( .D(first_mux_X[58]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n742), .Q(d_ff2_X[58]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_55_ ( .D(first_mux_X[55]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n743), .Q(d_ff2_X[55]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_54_ ( .D(first_mux_X[54]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n743), .Q(d_ff2_X[54]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_53_ ( .D(first_mux_X[53]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n743), .Q(d_ff2_X[53]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_55_ ( .D(first_mux_Y[55]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n731), .Q(d_ff2_Y[55]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_54_ ( .D(first_mux_Y[54]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n732), .Q(d_ff2_Y[54]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_53_ ( .D(first_mux_Y[53]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n732), .Q(d_ff2_Y[53]) );
DFFRX4TS cont_iter_count_reg_3_ ( .D(n774), .CK(cont_iter_net3827306), .RN(
n766), .Q(cont_iter_out[3]), .QN(n704) );
DFFRX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n282), .CK(n768), .RN(n765), .Q(
sel_mux_2_reg[1]) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3827270), .RN(n766), .Q(d_ff1_shift_region_flag_out[1]) );
DFFRX4TS cordic_FSM_state_reg_reg_3_ ( .D(n291), .CK(n768), .RN(n276), .Q(
cordic_FSM_state_reg[3]), .QN(n701) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_57_ ( .D(first_mux_Y[57]), .CK(
reg_val_muxZ_2stage_net3827270), .RN(n731), .Q(d_ff2_Y[57]), .QN(n714)
);
ADDFX1TS intadd_458_U4 ( .A(d_ff2_Y[53]), .B(n708), .CI(intadd_458_CI), .CO(
intadd_458_n3), .S(sh_exp_y[1]) );
ADDFX1TS intadd_457_U4 ( .A(d_ff2_X[53]), .B(n708), .CI(intadd_457_CI), .CO(
intadd_457_n3), .S(sh_exp_x[1]) );
ADDFX1TS intadd_457_U3 ( .A(d_ff2_X[54]), .B(n703), .CI(intadd_457_n3), .CO(
intadd_457_n2), .S(sh_exp_x[2]) );
ADDFX1TS intadd_458_U3 ( .A(d_ff2_Y[54]), .B(n703), .CI(intadd_458_n3), .CO(
intadd_458_n2), .S(sh_exp_y[2]) );
ADDFX1TS intadd_457_U2 ( .A(d_ff2_X[55]), .B(n704), .CI(intadd_457_n2), .CO(
intadd_457_n1), .S(sh_exp_x[3]) );
ADDFX1TS intadd_458_U2 ( .A(d_ff2_Y[55]), .B(n704), .CI(intadd_458_n2), .CO(
intadd_458_n1), .S(sh_exp_y[3]) );
DFFRX4TS cordic_FSM_state_reg_reg_2_ ( .D(n292), .CK(clk), .RN(n276), .Q(
cordic_FSM_state_reg[2]) );
DFFRX4TS cordic_FSM_state_reg_reg_0_ ( .D(n293), .CK(clk), .RN(n276), .Q(
cordic_FSM_state_reg[0]), .QN(n423) );
DFFRX4TS reg_ch_mux_3_Q_reg_0_ ( .D(n285), .CK(n768), .RN(n766), .Q(n702),
.QN(n711) );
DFFRX4TS reg_ch_mux_1_Q_reg_0_ ( .D(n284), .CK(n768), .RN(n765), .Q(
sel_mux_1_reg), .QN(n712) );
AOI222X1TS U757 ( .A0(d_ff2_Y[62]), .A1(n683), .B0(d_ff2_X[62]), .B1(n658),
.C0(n424), .C1(d_ff2_Z[62]), .Y(n470) );
AOI222X1TS U758 ( .A0(n526), .A1(d_ff3_LUT_out[22]), .B0(n569), .B1(
d_ff3_sh_x_out[22]), .C0(n514), .C1(d_ff3_sh_y_out[22]), .Y(n520) );
AOI222X1TS U759 ( .A0(n549), .A1(d_ff3_LUT_out[1]), .B0(n569), .B1(
d_ff3_sh_x_out[1]), .C0(n572), .C1(d_ff3_sh_y_out[1]), .Y(n524) );
AOI222X1TS U760 ( .A0(n549), .A1(d_ff3_LUT_out[3]), .B0(n569), .B1(
d_ff3_sh_x_out[3]), .C0(n572), .C1(d_ff3_sh_y_out[3]), .Y(n523) );
NOR2XLTS U761 ( .A(n586), .B(n557), .Y(enab_d_ff4_Yn) );
INVX8TS U762 ( .A(n433), .Y(n434) );
BUFX6TS U763 ( .A(n440), .Y(n514) );
AOI222X1TS U764 ( .A0(n546), .A1(d_ff2_Z[25]), .B0(n482), .B1(d_ff2_Y[25]),
.C0(n514), .C1(d_ff2_X[25]), .Y(n485) );
AOI222X1TS U765 ( .A0(n526), .A1(d_ff2_Z[43]), .B0(n482), .B1(d_ff2_Y[43]),
.C0(n687), .C1(d_ff2_X[43]), .Y(n517) );
AOI222X1TS U766 ( .A0(n546), .A1(d_ff2_Z[23]), .B0(n482), .B1(d_ff2_Y[23]),
.C0(n514), .C1(d_ff2_X[23]), .Y(n483) );
AOI222X1TS U767 ( .A0(n526), .A1(d_ff2_Z[44]), .B0(n482), .B1(d_ff2_Y[44]),
.C0(n677), .C1(d_ff2_X[44]), .Y(n510) );
BUFX6TS U768 ( .A(n434), .Y(n436) );
AOI222X1TS U769 ( .A0(n526), .A1(d_ff2_Z[41]), .B0(n482), .B1(d_ff2_Y[41]),
.C0(n687), .C1(d_ff2_X[41]), .Y(n516) );
AOI222X1TS U770 ( .A0(n546), .A1(d_ff2_Z[21]), .B0(n482), .B1(d_ff2_Y[21]),
.C0(n514), .C1(d_ff2_X[21]), .Y(n487) );
AOI222X1TS U771 ( .A0(n526), .A1(d_ff2_Z[42]), .B0(n482), .B1(d_ff2_Y[42]),
.C0(n687), .C1(d_ff2_X[42]), .Y(n515) );
AOI222X1TS U772 ( .A0(n526), .A1(d_ff2_Z[40]), .B0(n482), .B1(d_ff2_Y[40]),
.C0(n687), .C1(d_ff2_X[40]), .Y(n518) );
AOI222X1TS U773 ( .A0(n549), .A1(d_ff2_Z[31]), .B0(n482), .B1(d_ff2_Y[31]),
.C0(n552), .C1(d_ff2_X[31]), .Y(n550) );
BUFX6TS U774 ( .A(n514), .Y(n658) );
BUFX6TS U775 ( .A(n468), .Y(n482) );
BUFX3TS U776 ( .A(n439), .Y(n468) );
NAND2X4TS U777 ( .A(n627), .B(n645), .Y(n623) );
NOR2XLTS U778 ( .A(sel_mux_2_reg[1]), .B(n706), .Y(n439) );
NOR2XLTS U779 ( .A(sel_mux_2_reg[0]), .B(sel_mux_2_reg[1]), .Y(n440) );
INVX6TS U780 ( .A(sel_mux_1_reg), .Y(n610) );
BUFX6TS U781 ( .A(n461), .Y(n424) );
AOI222X1TS U782 ( .A0(n549), .A1(d_ff3_LUT_out[20]), .B0(n569), .B1(
d_ff3_sh_x_out[20]), .C0(n514), .C1(d_ff3_sh_y_out[20]), .Y(n533) );
AOI222X1TS U783 ( .A0(n546), .A1(d_ff2_Z[17]), .B0(n573), .B1(d_ff2_Y[17]),
.C0(n552), .C1(d_ff2_X[17]), .Y(n547) );
AOI222X1TS U784 ( .A0(n546), .A1(d_ff2_Z[19]), .B0(n576), .B1(d_ff2_Y[19]),
.C0(n514), .C1(d_ff2_X[19]), .Y(n457) );
AOI222X1TS U785 ( .A0(n685), .A1(d_ff2_Z[30]), .B0(n573), .B1(d_ff2_Y[30]),
.C0(n687), .C1(d_ff2_X[30]), .Y(n568) );
AOI222X1TS U786 ( .A0(n685), .A1(d_ff2_Z[38]), .B0(n482), .B1(d_ff2_Y[38]),
.C0(n687), .C1(d_ff2_X[38]), .Y(n560) );
AOI222X1TS U787 ( .A0(n685), .A1(d_ff2_Z[39]), .B0(n482), .B1(d_ff2_Y[39]),
.C0(n687), .C1(d_ff2_X[39]), .Y(n561) );
AOI222X1TS U788 ( .A0(n549), .A1(d_ff2_Z[53]), .B0(n576), .B1(d_ff2_Y[53]),
.C0(n677), .C1(d_ff2_X[53]), .Y(n505) );
AOI222X1TS U789 ( .A0(n549), .A1(d_ff2_Z[54]), .B0(n576), .B1(d_ff2_Y[54]),
.C0(n677), .C1(d_ff2_X[54]), .Y(n504) );
AOI222X1TS U790 ( .A0(n549), .A1(d_ff2_Z[55]), .B0(n576), .B1(d_ff2_Y[55]),
.C0(n677), .C1(d_ff2_X[55]), .Y(n503) );
AOI222X1TS U791 ( .A0(d_ff2_Y[56]), .A1(n576), .B0(d_ff2_X[56]), .B1(n658),
.C0(n546), .C1(d_ff2_Z[56]), .Y(n474) );
AOI222X1TS U792 ( .A0(d_ff2_Y[60]), .A1(n683), .B0(d_ff2_X[60]), .B1(n658),
.C0(n424), .C1(d_ff2_Z[60]), .Y(n471) );
AOI222X1TS U793 ( .A0(n549), .A1(d_ff2_Z[63]), .B0(n569), .B1(d_ff2_Y[63]),
.C0(n572), .C1(d_ff2_X[63]), .Y(n521) );
OAI32X1TS U794 ( .A0(n585), .A1(n558), .A2(n709), .B0(n425), .B1(n451), .Y(
n282) );
OAI31X1TS U795 ( .A0(cordic_FSM_state_reg[2]), .A1(n593), .A2(n423), .B0(
n592), .Y(n292) );
NOR4X2TS U796 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n603), .D(n707), .Y(n425) );
OR4X2TS U797 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[1]), .C(
n603), .D(n423), .Y(n426) );
INVX2TS U798 ( .A(n426), .Y(n427) );
AOI222X1TS U799 ( .A0(n549), .A1(d_ff3_LUT_out[29]), .B0(n468), .B1(
d_ff3_sh_x_out[29]), .C0(n658), .C1(d_ff3_sh_y_out[29]), .Y(n500) );
AOI222X1TS U800 ( .A0(n549), .A1(d_ff3_LUT_out[24]), .B0(n468), .B1(
d_ff3_sh_x_out[24]), .C0(n658), .C1(d_ff3_sh_y_out[24]), .Y(n499) );
AOI222X1TS U801 ( .A0(n526), .A1(d_ff3_LUT_out[26]), .B0(n468), .B1(
d_ff3_sh_x_out[26]), .C0(n658), .C1(d_ff3_sh_y_out[26]), .Y(n498) );
NOR4X1TS U802 ( .A(cordic_FSM_state_reg[1]), .B(n603), .C(n701), .D(n423),
.Y(ready_cordic) );
BUFX6TS U803 ( .A(n711), .Y(n617) );
AOI222X1TS U804 ( .A0(n603), .A1(cordic_FSM_state_reg[1]), .B0(n603), .B1(
n558), .C0(n707), .C1(n423), .Y(n445) );
NOR2X2TS U805 ( .A(n708), .B(n767), .Y(n584) );
AOI222X1TS U806 ( .A0(n685), .A1(d_ff2_Z[29]), .B0(n482), .B1(d_ff2_Y[29]),
.C0(n514), .C1(d_ff2_X[29]), .Y(n575) );
AOI222X1TS U807 ( .A0(n685), .A1(d_ff2_Z[27]), .B0(n482), .B1(d_ff2_Y[27]),
.C0(n514), .C1(d_ff2_X[27]), .Y(n571) );
AOI222X1TS U808 ( .A0(n685), .A1(d_ff2_Z[36]), .B0(n482), .B1(d_ff2_Y[36]),
.C0(n687), .C1(d_ff2_X[36]), .Y(n567) );
AOI222X1TS U809 ( .A0(n685), .A1(d_ff2_Z[34]), .B0(n482), .B1(d_ff2_Y[34]),
.C0(n687), .C1(d_ff2_X[34]), .Y(n566) );
AOI222X1TS U810 ( .A0(n685), .A1(d_ff2_Z[33]), .B0(n482), .B1(d_ff2_Y[33]),
.C0(n687), .C1(d_ff2_X[33]), .Y(n565) );
AOI222X1TS U811 ( .A0(n685), .A1(d_ff2_Z[32]), .B0(n482), .B1(d_ff2_Y[32]),
.C0(n687), .C1(d_ff2_X[32]), .Y(n564) );
AOI222X1TS U812 ( .A0(n685), .A1(d_ff2_Z[35]), .B0(n482), .B1(d_ff2_Y[35]),
.C0(n687), .C1(d_ff2_X[35]), .Y(n563) );
AOI222X1TS U813 ( .A0(n685), .A1(d_ff2_Z[37]), .B0(n482), .B1(d_ff2_Y[37]),
.C0(n687), .C1(d_ff2_X[37]), .Y(n559) );
AOI222X1TS U814 ( .A0(n685), .A1(d_ff3_LUT_out[19]), .B0(n569), .B1(
d_ff3_sh_x_out[19]), .C0(n572), .C1(d_ff3_sh_y_out[19]), .Y(n570) );
AOI222X1TS U815 ( .A0(n549), .A1(d_ff3_LUT_out[5]), .B0(n569), .B1(
d_ff3_sh_x_out[5]), .C0(n572), .C1(d_ff3_sh_y_out[5]), .Y(n532) );
AOI222X1TS U816 ( .A0(n549), .A1(d_ff3_LUT_out[18]), .B0(n569), .B1(
d_ff3_sh_x_out[18]), .C0(n514), .C1(d_ff3_sh_y_out[18]), .Y(n531) );
AOI222X1TS U817 ( .A0(n549), .A1(d_ff3_LUT_out[12]), .B0(n569), .B1(
d_ff3_sh_x_out[12]), .C0(n514), .C1(d_ff3_sh_y_out[12]), .Y(n530) );
AOI222X1TS U818 ( .A0(n549), .A1(d_ff3_LUT_out[9]), .B0(n569), .B1(
d_ff3_sh_x_out[9]), .C0(n572), .C1(d_ff3_sh_y_out[9]), .Y(n529) );
AOI222X1TS U819 ( .A0(n549), .A1(d_ff3_LUT_out[7]), .B0(n569), .B1(
d_ff3_sh_x_out[7]), .C0(n572), .C1(d_ff3_sh_y_out[7]), .Y(n528) );
AOI222X1TS U820 ( .A0(n526), .A1(d_ff3_LUT_out[6]), .B0(n569), .B1(
d_ff3_sh_x_out[6]), .C0(n572), .C1(d_ff3_sh_y_out[6]), .Y(n527) );
AOI222X1TS U821 ( .A0(n549), .A1(d_ff3_LUT_out[0]), .B0(n569), .B1(
d_ff3_sh_x_out[0]), .C0(n572), .C1(d_ff3_sh_y_out[0]), .Y(n525) );
AOI222X4TS U822 ( .A0(n424), .A1(d_ff3_LUT_out[13]), .B0(n569), .B1(
d_ff3_sh_x_out[13]), .C0(n514), .C1(d_ff3_sh_y_out[13]), .Y(n486) );
AOI222X4TS U823 ( .A0(n424), .A1(d_ff3_LUT_out[8]), .B0(n569), .B1(
d_ff3_sh_x_out[8]), .C0(n572), .C1(d_ff3_sh_y_out[8]), .Y(n484) );
AOI222X4TS U824 ( .A0(n424), .A1(d_ff3_LUT_out[10]), .B0(n569), .B1(
d_ff3_sh_x_out[10]), .C0(n572), .C1(d_ff3_sh_y_out[10]), .Y(n481) );
AOI222X4TS U825 ( .A0(n675), .A1(d_ff3_LUT_out[11]), .B0(n569), .B1(
d_ff3_sh_x_out[11]), .C0(n572), .C1(d_ff3_sh_y_out[11]), .Y(n480) );
AOI222X4TS U826 ( .A0(n546), .A1(d_ff3_LUT_out[14]), .B0(n569), .B1(
d_ff3_sh_x_out[14]), .C0(n514), .C1(d_ff3_sh_y_out[14]), .Y(n479) );
AOI222X4TS U827 ( .A0(n546), .A1(d_ff3_LUT_out[16]), .B0(n569), .B1(
d_ff3_sh_x_out[16]), .C0(n514), .C1(d_ff3_sh_y_out[16]), .Y(n478) );
BUFX4TS U828 ( .A(n678), .Y(n683) );
BUFX4TS U829 ( .A(n468), .Y(n678) );
NOR2X4TS U830 ( .A(cont_iter_out[2]), .B(cont_iter_out[1]), .Y(n628) );
AOI22X4TS U831 ( .A0(n704), .A1(n596), .B0(n628), .B1(n631), .Y(n639) );
AOI211X2TS U832 ( .A0(n596), .A1(n627), .B0(n558), .C0(n456), .Y(n649) );
NOR2X4TS U833 ( .A(n703), .B(n708), .Y(n596) );
AOI222X1TS U834 ( .A0(d_ff2_Y[57]), .A1(n683), .B0(d_ff2_X[57]), .B1(n658),
.C0(n424), .C1(d_ff2_Z[57]), .Y(n473) );
BUFX4TS U835 ( .A(n434), .Y(n437) );
NOR2X4TS U836 ( .A(cont_iter_out[2]), .B(n708), .Y(n645) );
INVX6TS U837 ( .A(n610), .Y(n657) );
CLKINVX6TS U838 ( .A(n610), .Y(n655) );
CLKINVX6TS U839 ( .A(n610), .Y(n656) );
CLKINVX6TS U840 ( .A(n610), .Y(n654) );
NOR2X4TS U841 ( .A(cont_iter_out[3]), .B(n767), .Y(n595) );
CLKINVX6TS U842 ( .A(n610), .Y(n604) );
NAND2X2TS U843 ( .A(n627), .B(n628), .Y(data_out_LUT[50]) );
NOR2X4TS U844 ( .A(n716), .B(cont_iter_out[3]), .Y(n627) );
CLKINVX6TS U845 ( .A(n436), .Y(n741) );
CLKINVX6TS U846 ( .A(n437), .Y(n428) );
CLKINVX6TS U847 ( .A(n711), .Y(n618) );
CLKINVX3TS U848 ( .A(n711), .Y(n616) );
CLKINVX6TS U849 ( .A(n711), .Y(n619) );
INVX2TS U850 ( .A(n644), .Y(n456) );
AOI222X1TS U851 ( .A0(n686), .A1(d_ff2_Z[10]), .B0(n683), .B1(d_ff2_Y[10]),
.C0(n552), .C1(d_ff2_X[10]), .Y(n553) );
AOI222X1TS U852 ( .A0(d_ff2_Y[58]), .A1(n678), .B0(d_ff2_X[58]), .B1(n658),
.C0(n546), .C1(d_ff2_Z[58]), .Y(n475) );
NOR2X2TS U853 ( .A(d_ff2_X[58]), .B(n697), .Y(n696) );
NOR2X2TS U854 ( .A(d_ff2_X[60]), .B(n695), .Y(n699) );
NOR2X2TS U855 ( .A(d_ff2_Y[58]), .B(n691), .Y(n690) );
NOR2X2TS U856 ( .A(d_ff2_Y[60]), .B(n689), .Y(n693) );
AOI222X1TS U857 ( .A0(d_ff2_Y[61]), .A1(n683), .B0(d_ff2_X[61]), .B1(n658),
.C0(n546), .C1(d_ff2_Z[61]), .Y(n472) );
AOI222X1TS U858 ( .A0(n685), .A1(d_ff2_Z[28]), .B0(n573), .B1(d_ff2_Y[28]),
.C0(n572), .C1(d_ff2_X[28]), .Y(n574) );
AOI222X1TS U859 ( .A0(n686), .A1(d_ff2_Z[3]), .B0(n573), .B1(d_ff2_Y[3]),
.C0(n552), .C1(d_ff2_X[3]), .Y(n551) );
AOI222X1TS U860 ( .A0(n686), .A1(d_ff2_Z[7]), .B0(n573), .B1(d_ff2_Y[7]),
.C0(n552), .C1(d_ff2_X[7]), .Y(n548) );
AOI222X1TS U861 ( .A0(n546), .A1(d_ff2_Z[15]), .B0(n573), .B1(d_ff2_Y[15]),
.C0(n552), .C1(d_ff2_X[15]), .Y(n545) );
AOI222X1TS U862 ( .A0(n686), .A1(d_ff2_Z[8]), .B0(n573), .B1(d_ff2_Y[8]),
.C0(n552), .C1(d_ff2_X[8]), .Y(n544) );
AOI222X1TS U863 ( .A0(n686), .A1(d_ff2_Z[13]), .B0(n573), .B1(d_ff2_Y[13]),
.C0(n552), .C1(d_ff2_X[13]), .Y(n543) );
AOI222X1TS U864 ( .A0(n546), .A1(d_ff2_Z[14]), .B0(n573), .B1(d_ff2_Y[14]),
.C0(n552), .C1(d_ff2_X[14]), .Y(n542) );
AOI222X1TS U865 ( .A0(n686), .A1(d_ff2_Z[5]), .B0(n573), .B1(d_ff2_Y[5]),
.C0(n552), .C1(d_ff2_X[5]), .Y(n541) );
AOI222X4TS U866 ( .A0(n686), .A1(d_ff2_Z[2]), .B0(n573), .B1(d_ff2_Y[2]),
.C0(n552), .C1(d_ff2_X[2]), .Y(n540) );
AOI222X4TS U867 ( .A0(n686), .A1(d_ff2_Z[11]), .B0(n573), .B1(d_ff2_Y[11]),
.C0(n552), .C1(d_ff2_X[11]), .Y(n539) );
AOI222X4TS U868 ( .A0(n686), .A1(d_ff2_Z[12]), .B0(n573), .B1(d_ff2_Y[12]),
.C0(n552), .C1(d_ff2_X[12]), .Y(n538) );
AOI222X4TS U869 ( .A0(n546), .A1(d_ff2_Z[16]), .B0(n573), .B1(d_ff2_Y[16]),
.C0(n514), .C1(d_ff2_X[16]), .Y(n537) );
AOI222X4TS U870 ( .A0(n546), .A1(d_ff2_Z[26]), .B0(n573), .B1(d_ff2_Y[26]),
.C0(n572), .C1(d_ff2_X[26]), .Y(n465) );
AOI222X4TS U871 ( .A0(n546), .A1(d_ff2_Z[20]), .B0(n573), .B1(d_ff2_Y[20]),
.C0(n572), .C1(d_ff2_X[20]), .Y(n463) );
AOI222X4TS U872 ( .A0(n546), .A1(d_ff2_Z[24]), .B0(n573), .B1(d_ff2_Y[24]),
.C0(n572), .C1(d_ff2_X[24]), .Y(n460) );
AOI222X4TS U873 ( .A0(n546), .A1(d_ff2_Z[22]), .B0(n573), .B1(d_ff2_Y[22]),
.C0(n572), .C1(d_ff2_X[22]), .Y(n459) );
AOI222X4TS U874 ( .A0(n546), .A1(d_ff2_Z[18]), .B0(n573), .B1(d_ff2_Y[18]),
.C0(n572), .C1(d_ff2_X[18]), .Y(n458) );
BUFX6TS U875 ( .A(n468), .Y(n576) );
NOR4X2TS U876 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[2]),
.C(n701), .D(n423), .Y(ack_add_subt) );
NOR3X2TS U877 ( .A(cordic_FSM_state_reg[2]), .B(cordic_FSM_state_reg[0]),
.C(n707), .Y(n602) );
NAND3X2TS U878 ( .A(cordic_FSM_state_reg[2]), .B(n707), .C(n423), .Y(n770)
);
INVX4TS U879 ( .A(n434), .Y(n766) );
AOI211XLTS U880 ( .A0(n578), .A1(n705), .B0(n427), .C0(n452), .Y(n289) );
OAI21XLTS U881 ( .A0(n698), .A1(n715), .B0(n697), .Y(sh_exp_x[5]) );
INVX2TS U882 ( .A(cordic_FSM_state_reg[2]), .Y(n603) );
NAND4X1TS U883 ( .A(n701), .B(n603), .C(n707), .D(n423), .Y(n433) );
INVX2TS U884 ( .A(n627), .Y(n435) );
INVX2TS U885 ( .A(n628), .Y(n633) );
NAND2X1TS U886 ( .A(cont_iter_out[3]), .B(n633), .Y(n635) );
NOR2X2TS U887 ( .A(cont_iter_out[1]), .B(n703), .Y(n650) );
NAND2X1TS U888 ( .A(n595), .B(n650), .Y(n644) );
OAI211XLTS U889 ( .A0(n435), .A1(n703), .B0(n635), .C0(n644), .Y(
data_out_LUT[14]) );
NAND3X2TS U890 ( .A(n596), .B(n716), .C(cont_iter_out[3]), .Y(
data_out_LUT[56]) );
INVX2TS U891 ( .A(n595), .Y(n640) );
INVX2TS U892 ( .A(data_out_LUT[56]), .Y(n558) );
OAI21XLTS U893 ( .A0(n708), .A1(n640), .B0(n649), .Y(data_out_LUT[23]) );
NAND2X1TS U894 ( .A(n628), .B(n595), .Y(data_out_LUT[40]) );
NAND2X1TS U895 ( .A(n645), .B(n595), .Y(data_out_LUT[38]) );
INVX4TS U896 ( .A(n436), .Y(n755) );
INVX4TS U897 ( .A(n436), .Y(n754) );
INVX4TS U898 ( .A(n437), .Y(n753) );
INVX4TS U899 ( .A(n434), .Y(n762) );
INVX4TS U900 ( .A(n437), .Y(n738) );
INVX4TS U901 ( .A(n437), .Y(n737) );
INVX4TS U902 ( .A(n437), .Y(n739) );
INVX4TS U903 ( .A(n437), .Y(n743) );
INVX4TS U904 ( .A(n437), .Y(n742) );
INVX4TS U905 ( .A(n434), .Y(n765) );
INVX4TS U906 ( .A(n436), .Y(n717) );
INVX4TS U907 ( .A(n434), .Y(n731) );
INVX4TS U908 ( .A(n434), .Y(n718) );
INVX4TS U909 ( .A(n434), .Y(n764) );
INVX4TS U910 ( .A(n436), .Y(n730) );
INVX4TS U911 ( .A(n434), .Y(n733) );
INVX4TS U912 ( .A(n436), .Y(n732) );
INVX4TS U913 ( .A(n436), .Y(n747) );
INVX4TS U914 ( .A(n436), .Y(n752) );
INVX4TS U915 ( .A(n436), .Y(n751) );
INVX4TS U916 ( .A(n436), .Y(n750) );
INVX4TS U917 ( .A(n436), .Y(n719) );
INVX4TS U918 ( .A(n434), .Y(n763) );
INVX4TS U919 ( .A(n436), .Y(n749) );
INVX4TS U920 ( .A(n436), .Y(n748) );
INVX4TS U921 ( .A(n434), .Y(n728) );
INVX4TS U922 ( .A(n434), .Y(n756) );
INVX4TS U923 ( .A(n436), .Y(n727) );
INVX4TS U924 ( .A(n436), .Y(n726) );
INVX4TS U925 ( .A(n436), .Y(n725) );
INVX4TS U926 ( .A(n436), .Y(n729) );
INVX4TS U927 ( .A(n434), .Y(n736) );
INVX4TS U928 ( .A(n437), .Y(n724) );
INVX4TS U929 ( .A(n437), .Y(n740) );
INVX4TS U930 ( .A(n437), .Y(n735) );
INVX4TS U931 ( .A(n437), .Y(n746) );
INVX4TS U932 ( .A(n436), .Y(n745) );
INVX4TS U933 ( .A(n437), .Y(n744) );
INVX4TS U934 ( .A(n434), .Y(n760) );
INVX4TS U935 ( .A(n434), .Y(n720) );
INVX4TS U936 ( .A(n434), .Y(n734) );
INVX4TS U937 ( .A(n434), .Y(n721) );
INVX4TS U938 ( .A(n434), .Y(n759) );
INVX4TS U939 ( .A(n434), .Y(n758) );
INVX4TS U940 ( .A(n434), .Y(n723) );
INVX4TS U941 ( .A(n437), .Y(n722) );
INVX4TS U942 ( .A(n610), .Y(n611) );
AO22XLTS U943 ( .A0(n611), .A1(d_ff_Zn[44]), .B0(n712), .B1(d_ff1_Z[44]),
.Y(first_mux_Z[44]) );
NAND2X1TS U944 ( .A(n627), .B(n703), .Y(data_out_LUT[47]) );
NAND2X1TS U945 ( .A(n645), .B(n704), .Y(data_out_LUT[45]) );
NOR2X2TS U946 ( .A(n704), .B(n716), .Y(n631) );
NAND2X1TS U947 ( .A(n596), .B(n631), .Y(n438) );
NAND3XLTS U948 ( .A(n716), .B(cont_iter_out[3]), .C(n650), .Y(n626) );
NAND4XLTS U949 ( .A(n649), .B(n438), .C(n626), .D(data_out_LUT[45]), .Y(
data_out_LUT[27]) );
INVX2TS U950 ( .A(n596), .Y(n625) );
NAND2X1TS U951 ( .A(n625), .B(n704), .Y(data_out_LUT[20]) );
INVX2TS U952 ( .A(data_out_LUT[20]), .Y(n647) );
NAND2X1TS U953 ( .A(n595), .B(n708), .Y(n624) );
NAND2X1TS U954 ( .A(n647), .B(n624), .Y(data_out_LUT[16]) );
NAND2X1TS U955 ( .A(n704), .B(n633), .Y(data_out_LUT[22]) );
NAND2X1TS U956 ( .A(n628), .B(n704), .Y(data_out_LUT[49]) );
NAND2X2TS U957 ( .A(n627), .B(n650), .Y(n648) );
NAND2X1TS U958 ( .A(data_out_LUT[38]), .B(n648), .Y(n455) );
INVX2TS U959 ( .A(n455), .Y(n637) );
CLKAND2X2TS U960 ( .A(data_out_LUT[49]), .B(n637), .Y(n653) );
NAND2X1TS U961 ( .A(n653), .B(n635), .Y(data_out_LUT[33]) );
NOR2BX1TS U962 ( .AN(sel_mux_2_reg[1]), .B(sel_mux_2_reg[0]), .Y(n461) );
BUFX3TS U963 ( .A(n424), .Y(n675) );
BUFX4TS U964 ( .A(n675), .Y(n686) );
BUFX4TS U965 ( .A(n514), .Y(n682) );
AOI22X1TS U966 ( .A0(n683), .A1(d_ff3_sh_x_out[30]), .B0(n682), .B1(
d_ff3_sh_y_out[30]), .Y(n441) );
OAI2BB1X1TS U967 ( .A0N(n686), .A1N(d_ff3_LUT_out[30]), .B0(n441), .Y(
add_subt_dataB[30]) );
AOI22X1TS U968 ( .A0(n683), .A1(d_ff3_sh_x_out[34]), .B0(n682), .B1(
d_ff3_sh_y_out[34]), .Y(n442) );
OAI2BB1X1TS U969 ( .A0N(n686), .A1N(d_ff3_LUT_out[43]), .B0(n442), .Y(
add_subt_dataB[34]) );
AOI22X1TS U970 ( .A0(n683), .A1(d_ff3_sh_x_out[43]), .B0(n682), .B1(
d_ff3_sh_y_out[43]), .Y(n443) );
OAI2BB1X1TS U971 ( .A0N(n686), .A1N(d_ff3_LUT_out[43]), .B0(n443), .Y(
add_subt_dataB[43]) );
NAND2X1TS U972 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n589) );
NOR3X1TS U973 ( .A(cordic_FSM_state_reg[3]), .B(n603), .C(n589), .Y(
beg_add_subt) );
NAND4BX1TS U974 ( .AN(ack_cordic), .B(cordic_FSM_state_reg[2]), .C(
cordic_FSM_state_reg[3]), .D(n707), .Y(n580) );
INVX2TS U975 ( .A(beg_add_subt), .Y(n444) );
OAI211XLTS U976 ( .A0(n445), .A1(n701), .B0(n580), .C0(n444), .Y(n291) );
INVX4TS U977 ( .A(n434), .Y(n761) );
INVX2TS U978 ( .A(rst), .Y(n276) );
INVX4TS U979 ( .A(n434), .Y(n757) );
NAND2X1TS U980 ( .A(n430), .B(n716), .Y(intadd_457_CI) );
OAI21XLTS U981 ( .A0(n716), .A1(n430), .B0(intadd_457_CI), .Y(sh_exp_x[0])
);
NAND2X1TS U982 ( .A(n431), .B(n716), .Y(intadd_458_CI) );
OAI21XLTS U983 ( .A0(n716), .A1(n431), .B0(intadd_458_CI), .Y(sh_exp_y[0])
);
NOR2XLTS U984 ( .A(cordic_FSM_state_reg[3]), .B(n770), .Y(enab_d_ff2_RB2) );
NAND4XLTS U985 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[1]),
.C(n603), .D(n423), .Y(n448) );
NOR2X1TS U986 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out),
.Y(n621) );
AOI21X1TS U987 ( .A0(d_ff1_operation_out), .A1(
d_ff1_shift_region_flag_out[1]), .B0(n621), .Y(n446) );
XNOR2X1TS U988 ( .A(d_ff1_shift_region_flag_out[0]), .B(n446), .Y(n554) );
NAND3XLTS U989 ( .A(n702), .B(n766), .C(n448), .Y(n447) );
OAI21XLTS U990 ( .A0(n448), .A1(n554), .B0(n447), .Y(n285) );
INVX2TS U991 ( .A(n584), .Y(n646) );
OAI21X1TS U992 ( .A0(cont_iter_out[1]), .A1(n716), .B0(n646), .Y(
data_out_LUT[53]) );
INVX2TS U993 ( .A(n639), .Y(data_out_LUT[17]) );
NOR2X1TS U994 ( .A(d_ff2_Y[56]), .B(intadd_458_n1), .Y(n692) );
OR3X1TS U995 ( .A(d_ff2_Y[57]), .B(d_ff2_Y[56]), .C(intadd_458_n1), .Y(n691)
);
OAI21XLTS U996 ( .A0(n692), .A1(n714), .B0(n691), .Y(sh_exp_y[5]) );
NOR2X1TS U997 ( .A(d_ff2_X[56]), .B(intadd_457_n1), .Y(n698) );
OR3X1TS U998 ( .A(d_ff2_X[57]), .B(d_ff2_X[56]), .C(intadd_457_n1), .Y(n697)
);
NOR3X1TS U999 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[2]),
.C(n589), .Y(n450) );
BUFX4TS U1000 ( .A(n610), .Y(n612) );
NAND2X1TS U1001 ( .A(n450), .B(data_out_LUT[50]), .Y(n449) );
OAI31X1TS U1002 ( .A0(n434), .A1(n450), .A2(n612), .B0(n449), .Y(n284) );
INVX2TS U1003 ( .A(n425), .Y(n585) );
NAND2X1TS U1004 ( .A(sel_mux_2_reg[1]), .B(n766), .Y(n451) );
NAND2X1TS U1005 ( .A(ack_add_subt), .B(data_out_LUT[56]), .Y(n578) );
NAND2X1TS U1006 ( .A(cont_var_out[1]), .B(n705), .Y(n588) );
AOI21X1TS U1007 ( .A0(n588), .A1(n705), .B0(n578), .Y(n452) );
CLKAND2X2TS U1008 ( .A(n602), .B(n701), .Y(load_cont_iter) );
NAND2X1TS U1009 ( .A(n710), .B(n696), .Y(n695) );
OAI21XLTS U1010 ( .A0(n696), .A1(n710), .B0(n695), .Y(sh_exp_x[7]) );
NAND2X1TS U1011 ( .A(n432), .B(n690), .Y(n689) );
OAI21XLTS U1012 ( .A0(n690), .A1(n432), .B0(n689), .Y(sh_exp_y[7]) );
NOR2X1TS U1013 ( .A(n705), .B(n578), .Y(n454) );
NOR2XLTS U1014 ( .A(cont_var_out[1]), .B(n454), .Y(n453) );
AOI211XLTS U1015 ( .A0(cont_var_out[1]), .A1(n454), .B0(n427), .C0(n453),
.Y(n290) );
NOR2X2TS U1016 ( .A(n456), .B(n455), .Y(n638) );
OAI21XLTS U1017 ( .A0(n595), .A1(n625), .B0(n638), .Y(data_out_LUT[25]) );
BUFX4TS U1018 ( .A(n424), .Y(n546) );
BUFX4TS U1019 ( .A(n482), .Y(n573) );
INVX2TS U1020 ( .A(n457), .Y(add_subt_dataA[19]) );
BUFX4TS U1021 ( .A(n514), .Y(n572) );
INVX2TS U1022 ( .A(n458), .Y(add_subt_dataA[18]) );
INVX2TS U1023 ( .A(n459), .Y(add_subt_dataA[22]) );
INVX2TS U1024 ( .A(n460), .Y(add_subt_dataA[24]) );
AOI222X1TS U1025 ( .A0(n424), .A1(d_ff3_LUT_out[35]), .B0(n576), .B1(
d_ff3_sh_x_out[35]), .C0(n514), .C1(d_ff3_sh_y_out[35]), .Y(n462) );
INVX2TS U1026 ( .A(n462), .Y(add_subt_dataB[35]) );
INVX2TS U1027 ( .A(n463), .Y(add_subt_dataA[20]) );
AOI222X1TS U1028 ( .A0(n675), .A1(d_ff3_LUT_out[27]), .B0(n576), .B1(
d_ff3_sh_x_out[27]), .C0(n514), .C1(d_ff3_sh_y_out[27]), .Y(n464) );
INVX2TS U1029 ( .A(n464), .Y(add_subt_dataB[27]) );
INVX2TS U1030 ( .A(n465), .Y(add_subt_dataA[26]) );
AOI222X1TS U1031 ( .A0(n675), .A1(d_ff3_LUT_out[17]), .B0(n576), .B1(
d_ff3_sh_x_out[17]), .C0(n514), .C1(d_ff3_sh_y_out[17]), .Y(n466) );
INVX2TS U1032 ( .A(n466), .Y(add_subt_dataB[17]) );
AOI222X1TS U1033 ( .A0(n424), .A1(d_ff3_LUT_out[15]), .B0(n576), .B1(
d_ff3_sh_x_out[15]), .C0(n514), .C1(d_ff3_sh_y_out[15]), .Y(n467) );
INVX2TS U1034 ( .A(n467), .Y(add_subt_dataB[15]) );
AOI222X1TS U1035 ( .A0(n424), .A1(d_ff3_LUT_out[55]), .B0(n678), .B1(
d_ff3_sh_x_out[55]), .C0(n658), .C1(d_ff3_sh_y_out[55]), .Y(n469) );
INVX2TS U1036 ( .A(n469), .Y(add_subt_dataB[55]) );
INVX2TS U1037 ( .A(n470), .Y(add_subt_dataA[62]) );
INVX2TS U1038 ( .A(n471), .Y(add_subt_dataA[60]) );
INVX2TS U1039 ( .A(n472), .Y(add_subt_dataA[61]) );
INVX2TS U1040 ( .A(n473), .Y(add_subt_dataA[57]) );
INVX2TS U1041 ( .A(n474), .Y(add_subt_dataA[56]) );
INVX2TS U1042 ( .A(n475), .Y(add_subt_dataA[58]) );
AOI222X1TS U1043 ( .A0(n424), .A1(d_ff3_LUT_out[53]), .B0(n678), .B1(
d_ff3_sh_x_out[53]), .C0(n658), .C1(d_ff3_sh_y_out[53]), .Y(n476) );
INVX2TS U1044 ( .A(n476), .Y(add_subt_dataB[53]) );
AOI222X1TS U1045 ( .A0(n424), .A1(d_ff3_LUT_out[56]), .B0(n678), .B1(
d_ff3_sh_x_out[56]), .C0(n658), .C1(d_ff3_sh_y_out[56]), .Y(n477) );
INVX2TS U1046 ( .A(n477), .Y(add_subt_dataB[56]) );
BUFX4TS U1047 ( .A(n468), .Y(n569) );
INVX2TS U1048 ( .A(n478), .Y(add_subt_dataB[16]) );
INVX2TS U1049 ( .A(n479), .Y(add_subt_dataB[14]) );
INVX2TS U1050 ( .A(n480), .Y(add_subt_dataB[11]) );
INVX2TS U1051 ( .A(n481), .Y(add_subt_dataB[10]) );
INVX2TS U1052 ( .A(n483), .Y(add_subt_dataA[23]) );
INVX2TS U1053 ( .A(n484), .Y(add_subt_dataB[8]) );
INVX2TS U1054 ( .A(n485), .Y(add_subt_dataA[25]) );
INVX2TS U1055 ( .A(n486), .Y(add_subt_dataB[13]) );
INVX2TS U1056 ( .A(n487), .Y(add_subt_dataA[21]) );
AOI222X1TS U1057 ( .A0(n675), .A1(d_ff3_LUT_out[39]), .B0(n576), .B1(
d_ff3_sh_x_out[39]), .C0(n658), .C1(d_ff3_sh_y_out[39]), .Y(n488) );
INVX2TS U1058 ( .A(n488), .Y(add_subt_dataB[39]) );
AOI222X1TS U1059 ( .A0(n424), .A1(d_ff3_LUT_out[45]), .B0(n678), .B1(
d_ff3_sh_x_out[45]), .C0(n658), .C1(d_ff3_sh_y_out[45]), .Y(n489) );
INVX2TS U1060 ( .A(n489), .Y(add_subt_dataB[45]) );
AOI222X1TS U1061 ( .A0(n675), .A1(d_ff3_LUT_out[41]), .B0(n482), .B1(
d_ff3_sh_x_out[41]), .C0(n658), .C1(d_ff3_sh_y_out[41]), .Y(n490) );
INVX2TS U1062 ( .A(n490), .Y(add_subt_dataB[41]) );
AOI222X1TS U1063 ( .A0(n675), .A1(d_ff3_LUT_out[25]), .B0(n468), .B1(
d_ff3_sh_x_out[25]), .C0(n658), .C1(d_ff3_sh_y_out[25]), .Y(n491) );
INVX2TS U1064 ( .A(n491), .Y(add_subt_dataB[25]) );
AOI222X1TS U1065 ( .A0(n424), .A1(d_ff3_LUT_out[54]), .B0(n482), .B1(
d_ff3_sh_x_out[54]), .C0(n658), .C1(d_ff3_sh_y_out[54]), .Y(n492) );
INVX2TS U1066 ( .A(n492), .Y(add_subt_dataB[54]) );
AOI222X1TS U1067 ( .A0(n675), .A1(d_ff3_LUT_out[37]), .B0(n468), .B1(
d_ff3_sh_x_out[37]), .C0(n658), .C1(d_ff3_sh_y_out[37]), .Y(n493) );
INVX2TS U1068 ( .A(n493), .Y(add_subt_dataB[37]) );
AOI222X1TS U1069 ( .A0(n424), .A1(d_ff3_LUT_out[33]), .B0(n482), .B1(
d_ff3_sh_x_out[33]), .C0(n658), .C1(d_ff3_sh_y_out[33]), .Y(n494) );
INVX2TS U1070 ( .A(n494), .Y(add_subt_dataB[33]) );
AOI222X1TS U1071 ( .A0(n424), .A1(d_ff3_LUT_out[50]), .B0(n468), .B1(
d_ff3_sh_x_out[50]), .C0(n658), .C1(d_ff3_sh_y_out[50]), .Y(n495) );
INVX2TS U1072 ( .A(n495), .Y(add_subt_dataB[50]) );
AOI222X1TS U1073 ( .A0(n675), .A1(d_ff3_LUT_out[52]), .B0(n482), .B1(
d_ff3_sh_x_out[52]), .C0(n658), .C1(d_ff3_sh_y_out[52]), .Y(n496) );
INVX2TS U1074 ( .A(n496), .Y(add_subt_dataB[52]) );
BUFX4TS U1075 ( .A(n675), .Y(n526) );
AOI222X1TS U1076 ( .A0(n526), .A1(d_ff3_LUT_out[31]), .B0(n468), .B1(
d_ff3_sh_x_out[31]), .C0(n658), .C1(d_ff3_sh_y_out[31]), .Y(n497) );
INVX2TS U1077 ( .A(n497), .Y(add_subt_dataB[31]) );
INVX2TS U1078 ( .A(n498), .Y(add_subt_dataB[26]) );
BUFX4TS U1079 ( .A(n675), .Y(n549) );
INVX2TS U1080 ( .A(n499), .Y(add_subt_dataB[24]) );
INVX2TS U1081 ( .A(n500), .Y(add_subt_dataB[29]) );
BUFX4TS U1082 ( .A(n514), .Y(n677) );
AOI222X1TS U1083 ( .A0(n526), .A1(d_ff2_Z[52]), .B0(n576), .B1(d_ff2_Y[52]),
.C0(n677), .C1(d_ff2_X[52]), .Y(n501) );
INVX2TS U1084 ( .A(n501), .Y(add_subt_dataA[52]) );
AOI222X1TS U1085 ( .A0(n526), .A1(d_ff2_Z[51]), .B0(n576), .B1(d_ff2_Y[51]),
.C0(n677), .C1(d_ff2_X[51]), .Y(n502) );
INVX2TS U1086 ( .A(n502), .Y(add_subt_dataA[51]) );
INVX2TS U1087 ( .A(n503), .Y(add_subt_dataA[55]) );
INVX2TS U1088 ( .A(n504), .Y(add_subt_dataA[54]) );
INVX2TS U1089 ( .A(n505), .Y(add_subt_dataA[53]) );
AOI222X1TS U1090 ( .A0(n526), .A1(d_ff2_Z[48]), .B0(n576), .B1(d_ff2_Y[48]),
.C0(n677), .C1(d_ff2_X[48]), .Y(n506) );
INVX2TS U1091 ( .A(n506), .Y(add_subt_dataA[48]) );
AOI222X1TS U1092 ( .A0(n526), .A1(d_ff2_Z[47]), .B0(n576), .B1(d_ff2_Y[47]),
.C0(n677), .C1(d_ff2_X[47]), .Y(n507) );
INVX2TS U1093 ( .A(n507), .Y(add_subt_dataA[47]) );
AOI222X1TS U1094 ( .A0(n526), .A1(d_ff2_Z[46]), .B0(n576), .B1(d_ff2_Y[46]),
.C0(n677), .C1(d_ff2_X[46]), .Y(n508) );
INVX2TS U1095 ( .A(n508), .Y(add_subt_dataA[46]) );
AOI222X1TS U1096 ( .A0(n526), .A1(d_ff2_Z[45]), .B0(n576), .B1(d_ff2_Y[45]),
.C0(n677), .C1(d_ff2_X[45]), .Y(n509) );
INVX2TS U1097 ( .A(n509), .Y(add_subt_dataA[45]) );
INVX2TS U1098 ( .A(n510), .Y(add_subt_dataA[44]) );
AOI222X1TS U1099 ( .A0(n549), .A1(d_ff2_Z[0]), .B0(n576), .B1(d_ff2_Y[0]),
.C0(n677), .C1(d_ff2_X[0]), .Y(n511) );
INVX2TS U1100 ( .A(n511), .Y(add_subt_dataA[0]) );
AOI222X1TS U1101 ( .A0(n526), .A1(d_ff2_Z[50]), .B0(n576), .B1(d_ff2_Y[50]),
.C0(n677), .C1(d_ff2_X[50]), .Y(n512) );
INVX2TS U1102 ( .A(n512), .Y(add_subt_dataA[50]) );
AOI222X1TS U1103 ( .A0(n526), .A1(d_ff2_Z[49]), .B0(n576), .B1(d_ff2_Y[49]),
.C0(n677), .C1(d_ff2_X[49]), .Y(n513) );
INVX2TS U1104 ( .A(n513), .Y(add_subt_dataA[49]) );
BUFX4TS U1105 ( .A(n514), .Y(n687) );
INVX2TS U1106 ( .A(n515), .Y(add_subt_dataA[42]) );
INVX2TS U1107 ( .A(n516), .Y(add_subt_dataA[41]) );
INVX2TS U1108 ( .A(n517), .Y(add_subt_dataA[43]) );
INVX2TS U1109 ( .A(n518), .Y(add_subt_dataA[40]) );
AOI222X1TS U1110 ( .A0(n526), .A1(d_ff3_LUT_out[23]), .B0(n576), .B1(
d_ff3_sh_x_out[23]), .C0(n514), .C1(d_ff3_sh_y_out[23]), .Y(n519) );
INVX2TS U1111 ( .A(n519), .Y(add_subt_dataB[23]) );
INVX2TS U1112 ( .A(n520), .Y(add_subt_dataB[22]) );
INVX2TS U1113 ( .A(n521), .Y(add_subt_dataA[63]) );
AOI222X1TS U1114 ( .A0(n549), .A1(d_ff3_LUT_out[2]), .B0(n576), .B1(
d_ff3_sh_x_out[2]), .C0(n572), .C1(d_ff3_sh_y_out[2]), .Y(n522) );
INVX2TS U1115 ( .A(n522), .Y(add_subt_dataB[2]) );
INVX2TS U1116 ( .A(n523), .Y(add_subt_dataB[3]) );
INVX2TS U1117 ( .A(n524), .Y(add_subt_dataB[1]) );
INVX2TS U1118 ( .A(n525), .Y(add_subt_dataB[0]) );
INVX2TS U1119 ( .A(n527), .Y(add_subt_dataB[6]) );
INVX2TS U1120 ( .A(n528), .Y(add_subt_dataB[7]) );
INVX2TS U1121 ( .A(n529), .Y(add_subt_dataB[9]) );
INVX2TS U1122 ( .A(n530), .Y(add_subt_dataB[12]) );
INVX2TS U1123 ( .A(n531), .Y(add_subt_dataB[18]) );
INVX2TS U1124 ( .A(n532), .Y(add_subt_dataB[5]) );
INVX2TS U1125 ( .A(n533), .Y(add_subt_dataB[20]) );
AOI222X1TS U1126 ( .A0(n686), .A1(d_ff2_Z[9]), .B0(n683), .B1(d_ff2_Y[9]),
.C0(n682), .C1(d_ff2_X[9]), .Y(n534) );
INVX2TS U1127 ( .A(n534), .Y(add_subt_dataA[9]) );
AOI222X1TS U1128 ( .A0(n686), .A1(d_ff2_Z[4]), .B0(n683), .B1(d_ff2_Y[4]),
.C0(n682), .C1(d_ff2_X[4]), .Y(n535) );
INVX2TS U1129 ( .A(n535), .Y(add_subt_dataA[4]) );
AOI222X1TS U1130 ( .A0(n686), .A1(d_ff2_Z[1]), .B0(n683), .B1(d_ff2_Y[1]),
.C0(n682), .C1(d_ff2_X[1]), .Y(n536) );
INVX2TS U1131 ( .A(n536), .Y(add_subt_dataA[1]) );
BUFX3TS U1132 ( .A(n658), .Y(n552) );
INVX2TS U1133 ( .A(n537), .Y(add_subt_dataA[16]) );
INVX2TS U1134 ( .A(n538), .Y(add_subt_dataA[12]) );
INVX2TS U1135 ( .A(n539), .Y(add_subt_dataA[11]) );
INVX2TS U1136 ( .A(n540), .Y(add_subt_dataA[2]) );
INVX2TS U1137 ( .A(n541), .Y(add_subt_dataA[5]) );
INVX2TS U1138 ( .A(n542), .Y(add_subt_dataA[14]) );
INVX2TS U1139 ( .A(n543), .Y(add_subt_dataA[13]) );
INVX2TS U1140 ( .A(n544), .Y(add_subt_dataA[8]) );
INVX2TS U1141 ( .A(n545), .Y(add_subt_dataA[15]) );
INVX2TS U1142 ( .A(n547), .Y(add_subt_dataA[17]) );
INVX2TS U1143 ( .A(n548), .Y(add_subt_dataA[7]) );
INVX2TS U1144 ( .A(n550), .Y(add_subt_dataA[31]) );
INVX2TS U1145 ( .A(n551), .Y(add_subt_dataA[3]) );
INVX2TS U1146 ( .A(n553), .Y(add_subt_dataA[10]) );
NOR2X1TS U1147 ( .A(data_out_LUT[56]), .B(n554), .Y(n556) );
AOI21X1TS U1148 ( .A0(cont_var_out[0]), .A1(data_out_LUT[56]), .B0(n556),
.Y(n586) );
NAND2X1TS U1149 ( .A(ready_add_subt), .B(n707), .Y(n579) );
NAND4BX1TS U1150 ( .AN(n579), .B(cordic_FSM_state_reg[3]), .C(n423), .D(n603), .Y(n557) );
AOI21X1TS U1151 ( .A0(n709), .A1(n705), .B0(n558), .Y(n555) );
NOR3XLTS U1152 ( .A(n556), .B(n555), .C(n557), .Y(enab_d_ff4_Xn) );
NOR3XLTS U1153 ( .A(n558), .B(n588), .C(n557), .Y(enab_d_ff4_Zn) );
BUFX4TS U1154 ( .A(n686), .Y(n685) );
INVX2TS U1155 ( .A(n559), .Y(add_subt_dataA[37]) );
INVX2TS U1156 ( .A(n560), .Y(add_subt_dataA[38]) );
INVX2TS U1157 ( .A(n561), .Y(add_subt_dataA[39]) );
AOI222X1TS U1158 ( .A0(n685), .A1(d_ff2_Z[6]), .B0(n683), .B1(d_ff2_Y[6]),
.C0(n682), .C1(d_ff2_X[6]), .Y(n562) );
INVX2TS U1159 ( .A(n562), .Y(add_subt_dataA[6]) );
INVX2TS U1160 ( .A(n563), .Y(add_subt_dataA[35]) );
INVX2TS U1161 ( .A(n564), .Y(add_subt_dataA[32]) );
INVX2TS U1162 ( .A(n565), .Y(add_subt_dataA[33]) );
INVX2TS U1163 ( .A(n566), .Y(add_subt_dataA[34]) );
INVX2TS U1164 ( .A(n567), .Y(add_subt_dataA[36]) );
INVX2TS U1165 ( .A(n568), .Y(add_subt_dataA[30]) );
INVX2TS U1166 ( .A(n570), .Y(add_subt_dataB[19]) );
INVX2TS U1167 ( .A(n571), .Y(add_subt_dataA[27]) );
INVX2TS U1168 ( .A(n574), .Y(add_subt_dataA[28]) );
INVX2TS U1169 ( .A(n575), .Y(add_subt_dataA[29]) );
AOI222X1TS U1170 ( .A0(n685), .A1(d_ff3_LUT_out[21]), .B0(n576), .B1(
d_ff3_sh_x_out[21]), .C0(n514), .C1(d_ff3_sh_y_out[21]), .Y(n577) );
INVX2TS U1171 ( .A(n577), .Y(add_subt_dataB[21]) );
NAND2X1TS U1172 ( .A(n701), .B(n707), .Y(n600) );
NOR2X1TS U1173 ( .A(n578), .B(n588), .Y(n583) );
INVX2TS U1174 ( .A(n770), .Y(n590) );
AOI32X1TS U1175 ( .A0(cordic_FSM_state_reg[3]), .A1(n580), .A2(n579), .B0(
cordic_FSM_state_reg[0]), .B1(n580), .Y(n581) );
NOR4X1TS U1176 ( .A(n583), .B(n590), .C(n602), .D(n581), .Y(n582) );
OAI31X1TS U1177 ( .A0(cordic_FSM_state_reg[2]), .A1(beg_fsm_cordic), .A2(
n600), .B0(n582), .Y(n293) );
OR2X1TS U1178 ( .A(n583), .B(load_cont_iter), .Y(enab_cont_iter) );
NOR2XLTS U1179 ( .A(n716), .B(n423), .Y(n773) );
NOR3XLTS U1180 ( .A(cordic_FSM_state_reg[2]), .B(n701), .C(n589), .Y(
enab_dff_5) );
NOR2XLTS U1181 ( .A(n701), .B(n770), .Y(enab_d_ff5_data_out) );
NOR2XLTS U1182 ( .A(n423), .B(data_out_LUT[53]), .Y(n772) );
NOR2X1TS U1183 ( .A(cont_iter_out[2]), .B(n584), .Y(n587) );
AO21XLTS U1184 ( .A0(n584), .A1(cont_iter_out[2]), .B0(n587), .Y(
data_out_LUT[54]) );
NOR2XLTS U1185 ( .A(n423), .B(data_out_LUT[54]), .Y(n771) );
OAI32X1TS U1186 ( .A0(n425), .A1(n434), .A2(n706), .B0(n586), .B1(n585), .Y(
n283) );
OAI21XLTS U1187 ( .A0(cont_iter_out[2]), .A1(n704), .B0(n638), .Y(
data_out_LUT[5]) );
OAI211XLTS U1188 ( .A0(n587), .A1(n704), .B0(n638), .C0(data_out_LUT[50]),
.Y(data_out_LUT[10]) );
AOI31XLTS U1189 ( .A0(cordic_FSM_state_reg[3]), .A1(data_out_LUT[56]), .A2(
n588), .B0(cordic_FSM_state_reg[1]), .Y(n593) );
OAI2BB2XLTS U1190 ( .B0(cordic_FSM_state_reg[1]), .B1(ack_cordic), .A0N(n701), .A1N(n589), .Y(n591) );
AOI21X1TS U1191 ( .A0(cordic_FSM_state_reg[2]), .A1(n591), .B0(n590), .Y(
n592) );
OAI21XLTS U1193 ( .A0(n767), .A1(n625), .B0(cont_iter_out[3]), .Y(n597) );
NAND2X1TS U1194 ( .A(n596), .B(n595), .Y(n641) );
AOI21X1TS U1195 ( .A0(n597), .A1(n641), .B0(n423), .Y(n774) );
INVX2TS U1196 ( .A(beg_fsm_cordic), .Y(n599) );
NAND2X1TS U1197 ( .A(cordic_FSM_state_reg[1]), .B(n701), .Y(n598) );
OAI32X1TS U1198 ( .A0(n423), .A1(n600), .A2(n599), .B0(
cordic_FSM_state_reg[0]), .B1(n598), .Y(n601) );
OR4X2TS U1199 ( .A(n427), .B(ack_add_subt), .C(n602), .D(n601), .Y(
cordic_FSM_state_next_1_) );
CLKAND2X2TS U1200 ( .A(d_ff_Yn[0]), .B(n654), .Y(first_mux_Y[0]) );
CLKAND2X2TS U1201 ( .A(d_ff_Yn[1]), .B(n611), .Y(first_mux_Y[1]) );
CLKAND2X2TS U1202 ( .A(d_ff_Yn[2]), .B(n654), .Y(first_mux_Y[2]) );
CLKAND2X2TS U1203 ( .A(d_ff_Yn[3]), .B(n655), .Y(first_mux_Y[3]) );
CLKAND2X2TS U1204 ( .A(d_ff_Yn[4]), .B(n656), .Y(first_mux_Y[4]) );
CLKAND2X2TS U1205 ( .A(d_ff_Yn[5]), .B(n656), .Y(first_mux_Y[5]) );
CLKAND2X2TS U1206 ( .A(d_ff_Yn[6]), .B(n655), .Y(first_mux_Y[6]) );
CLKAND2X2TS U1207 ( .A(d_ff_Yn[7]), .B(n657), .Y(first_mux_Y[7]) );
CLKAND2X2TS U1208 ( .A(d_ff_Yn[8]), .B(n655), .Y(first_mux_Y[8]) );
CLKAND2X2TS U1209 ( .A(d_ff_Yn[9]), .B(n654), .Y(first_mux_Y[9]) );
CLKAND2X2TS U1210 ( .A(d_ff_Yn[10]), .B(n654), .Y(first_mux_Y[10]) );
CLKAND2X2TS U1211 ( .A(d_ff_Yn[11]), .B(n654), .Y(first_mux_Y[11]) );
CLKAND2X2TS U1212 ( .A(d_ff_Yn[12]), .B(n604), .Y(first_mux_Y[12]) );
CLKAND2X2TS U1213 ( .A(d_ff_Yn[13]), .B(n604), .Y(first_mux_Y[13]) );
CLKAND2X2TS U1214 ( .A(d_ff_Yn[14]), .B(n604), .Y(first_mux_Y[14]) );
CLKAND2X2TS U1215 ( .A(d_ff_Yn[15]), .B(n604), .Y(first_mux_Y[15]) );
CLKAND2X2TS U1216 ( .A(d_ff_Yn[16]), .B(n604), .Y(first_mux_Y[16]) );
CLKAND2X2TS U1217 ( .A(d_ff_Yn[17]), .B(n604), .Y(first_mux_Y[17]) );
CLKAND2X2TS U1218 ( .A(d_ff_Yn[18]), .B(n604), .Y(first_mux_Y[18]) );
CLKAND2X2TS U1219 ( .A(d_ff_Yn[19]), .B(n604), .Y(first_mux_Y[19]) );
CLKAND2X2TS U1220 ( .A(d_ff_Yn[20]), .B(n604), .Y(first_mux_Y[20]) );
CLKAND2X2TS U1221 ( .A(d_ff_Yn[21]), .B(n604), .Y(first_mux_Y[21]) );
CLKAND2X2TS U1222 ( .A(d_ff_Yn[22]), .B(n604), .Y(first_mux_Y[22]) );
CLKAND2X2TS U1223 ( .A(d_ff_Yn[23]), .B(n604), .Y(first_mux_Y[23]) );
CLKAND2X2TS U1224 ( .A(d_ff_Yn[24]), .B(n604), .Y(first_mux_Y[24]) );
INVX4TS U1225 ( .A(n610), .Y(n613) );
CLKAND2X2TS U1226 ( .A(d_ff_Yn[25]), .B(n613), .Y(first_mux_Y[25]) );
CLKAND2X2TS U1227 ( .A(d_ff_Yn[26]), .B(n611), .Y(first_mux_Y[26]) );
CLKAND2X2TS U1228 ( .A(d_ff_Yn[27]), .B(n655), .Y(first_mux_Y[27]) );
CLKAND2X2TS U1229 ( .A(d_ff_Yn[28]), .B(n613), .Y(first_mux_Y[28]) );
CLKAND2X2TS U1230 ( .A(d_ff_Yn[29]), .B(n611), .Y(first_mux_Y[29]) );
CLKAND2X2TS U1231 ( .A(d_ff_Yn[30]), .B(n656), .Y(first_mux_Y[30]) );
CLKAND2X2TS U1232 ( .A(d_ff_Yn[31]), .B(n613), .Y(first_mux_Y[31]) );
CLKAND2X2TS U1233 ( .A(d_ff_Yn[32]), .B(n656), .Y(first_mux_Y[32]) );
CLKAND2X2TS U1234 ( .A(d_ff_Yn[33]), .B(n657), .Y(first_mux_Y[33]) );
CLKAND2X2TS U1235 ( .A(d_ff_Yn[34]), .B(n654), .Y(first_mux_Y[34]) );
CLKAND2X2TS U1236 ( .A(d_ff_Yn[35]), .B(n655), .Y(first_mux_Y[35]) );
CLKAND2X2TS U1237 ( .A(d_ff_Yn[36]), .B(n656), .Y(first_mux_Y[36]) );
CLKAND2X2TS U1238 ( .A(d_ff_Yn[37]), .B(n604), .Y(first_mux_Y[37]) );
INVX4TS U1239 ( .A(n610), .Y(n605) );
CLKAND2X2TS U1240 ( .A(d_ff_Yn[38]), .B(n605), .Y(first_mux_Y[38]) );
INVX4TS U1241 ( .A(n610), .Y(n607) );
CLKAND2X2TS U1242 ( .A(d_ff_Yn[39]), .B(n607), .Y(first_mux_Y[39]) );
INVX4TS U1243 ( .A(n610), .Y(n609) );
CLKAND2X2TS U1244 ( .A(d_ff_Yn[40]), .B(n609), .Y(first_mux_Y[40]) );
CLKAND2X2TS U1245 ( .A(d_ff_Yn[41]), .B(n604), .Y(first_mux_Y[41]) );
CLKAND2X2TS U1246 ( .A(d_ff_Yn[42]), .B(n605), .Y(first_mux_Y[42]) );
CLKAND2X2TS U1247 ( .A(d_ff_Yn[43]), .B(n607), .Y(first_mux_Y[43]) );
CLKAND2X2TS U1248 ( .A(d_ff_Yn[44]), .B(n609), .Y(first_mux_Y[44]) );
CLKAND2X2TS U1249 ( .A(d_ff_Yn[45]), .B(n604), .Y(first_mux_Y[45]) );
CLKAND2X2TS U1250 ( .A(d_ff_Yn[46]), .B(n604), .Y(first_mux_Y[46]) );
CLKAND2X2TS U1251 ( .A(d_ff_Yn[47]), .B(n604), .Y(first_mux_Y[47]) );
CLKAND2X2TS U1252 ( .A(d_ff_Yn[48]), .B(n604), .Y(first_mux_Y[48]) );
CLKAND2X2TS U1253 ( .A(d_ff_Yn[49]), .B(n604), .Y(first_mux_Y[49]) );
CLKAND2X2TS U1254 ( .A(d_ff_Yn[50]), .B(n655), .Y(first_mux_Y[50]) );
CLKAND2X2TS U1255 ( .A(d_ff_Yn[51]), .B(n657), .Y(first_mux_Y[51]) );
CLKAND2X2TS U1256 ( .A(d_ff_Yn[52]), .B(n654), .Y(first_mux_Y[52]) );
CLKAND2X2TS U1257 ( .A(d_ff_Yn[53]), .B(n657), .Y(first_mux_Y[53]) );
CLKAND2X2TS U1258 ( .A(d_ff_Yn[54]), .B(n654), .Y(first_mux_Y[54]) );
CLKAND2X2TS U1259 ( .A(d_ff_Yn[55]), .B(n655), .Y(first_mux_Y[55]) );
CLKAND2X2TS U1260 ( .A(d_ff_Yn[56]), .B(n656), .Y(first_mux_Y[56]) );
CLKAND2X2TS U1261 ( .A(d_ff_Yn[57]), .B(n656), .Y(first_mux_Y[57]) );
CLKAND2X2TS U1262 ( .A(d_ff_Yn[58]), .B(n657), .Y(first_mux_Y[58]) );
CLKAND2X2TS U1263 ( .A(d_ff_Yn[59]), .B(n655), .Y(first_mux_Y[59]) );
CLKAND2X2TS U1264 ( .A(d_ff_Yn[60]), .B(n657), .Y(first_mux_Y[60]) );
CLKAND2X2TS U1265 ( .A(d_ff_Yn[61]), .B(n654), .Y(first_mux_Y[61]) );
CLKAND2X2TS U1266 ( .A(d_ff_Yn[62]), .B(n656), .Y(first_mux_Y[62]) );
CLKAND2X2TS U1267 ( .A(d_ff_Yn[63]), .B(n613), .Y(first_mux_Y[63]) );
AO22XLTS U1268 ( .A0(n613), .A1(d_ff_Zn[0]), .B0(n610), .B1(d_ff1_Z[0]), .Y(
first_mux_Z[0]) );
AO22XLTS U1269 ( .A0(n613), .A1(d_ff_Zn[1]), .B0(n610), .B1(d_ff1_Z[1]), .Y(
first_mux_Z[1]) );
AO22XLTS U1270 ( .A0(n605), .A1(d_ff_Zn[2]), .B0(n610), .B1(d_ff1_Z[2]), .Y(
first_mux_Z[2]) );
AO22XLTS U1271 ( .A0(n605), .A1(d_ff_Zn[3]), .B0(n610), .B1(d_ff1_Z[3]), .Y(
first_mux_Z[3]) );
AO22XLTS U1272 ( .A0(n605), .A1(d_ff_Zn[4]), .B0(n712), .B1(d_ff1_Z[4]), .Y(
first_mux_Z[4]) );
AO22XLTS U1273 ( .A0(n605), .A1(d_ff_Zn[5]), .B0(n610), .B1(d_ff1_Z[5]), .Y(
first_mux_Z[5]) );
BUFX4TS U1274 ( .A(n712), .Y(n606) );
AO22XLTS U1275 ( .A0(n605), .A1(d_ff_Zn[6]), .B0(n606), .B1(d_ff1_Z[6]), .Y(
first_mux_Z[6]) );
AO22XLTS U1276 ( .A0(n605), .A1(d_ff_Zn[7]), .B0(n606), .B1(d_ff1_Z[7]), .Y(
first_mux_Z[7]) );
AO22XLTS U1277 ( .A0(n605), .A1(d_ff_Zn[8]), .B0(n606), .B1(d_ff1_Z[8]), .Y(
first_mux_Z[8]) );
AO22XLTS U1278 ( .A0(n605), .A1(d_ff_Zn[9]), .B0(n606), .B1(d_ff1_Z[9]), .Y(
first_mux_Z[9]) );
AO22XLTS U1279 ( .A0(n605), .A1(d_ff_Zn[10]), .B0(n606), .B1(d_ff1_Z[10]),
.Y(first_mux_Z[10]) );
AO22XLTS U1280 ( .A0(n605), .A1(d_ff_Zn[11]), .B0(n606), .B1(d_ff1_Z[11]),
.Y(first_mux_Z[11]) );
AO22XLTS U1281 ( .A0(n605), .A1(d_ff_Zn[12]), .B0(n606), .B1(d_ff1_Z[12]),
.Y(first_mux_Z[12]) );
AO22XLTS U1282 ( .A0(n605), .A1(d_ff_Zn[13]), .B0(n606), .B1(d_ff1_Z[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U1283 ( .A0(n605), .A1(d_ff_Zn[14]), .B0(n606), .B1(d_ff1_Z[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U1284 ( .A0(n607), .A1(d_ff_Zn[15]), .B0(n606), .B1(d_ff1_Z[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U1285 ( .A0(n607), .A1(d_ff_Zn[16]), .B0(n606), .B1(d_ff1_Z[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U1286 ( .A0(n607), .A1(d_ff_Zn[17]), .B0(n606), .B1(d_ff1_Z[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U1287 ( .A0(n607), .A1(d_ff_Zn[18]), .B0(n712), .B1(d_ff1_Z[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U1288 ( .A0(n607), .A1(d_ff_Zn[19]), .B0(n712), .B1(d_ff1_Z[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U1289 ( .A0(n607), .A1(d_ff_Zn[20]), .B0(n606), .B1(d_ff1_Z[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U1290 ( .A0(n607), .A1(d_ff_Zn[21]), .B0(n606), .B1(d_ff1_Z[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U1291 ( .A0(n607), .A1(d_ff_Zn[22]), .B0(n606), .B1(d_ff1_Z[22]),
.Y(first_mux_Z[22]) );
AO22XLTS U1292 ( .A0(n607), .A1(d_ff_Zn[23]), .B0(n606), .B1(d_ff1_Z[23]),
.Y(first_mux_Z[23]) );
AO22XLTS U1293 ( .A0(n607), .A1(d_ff_Zn[24]), .B0(n606), .B1(d_ff1_Z[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U1294 ( .A0(n607), .A1(d_ff_Zn[25]), .B0(n606), .B1(d_ff1_Z[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U1295 ( .A0(n607), .A1(d_ff_Zn[26]), .B0(n606), .B1(d_ff1_Z[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U1296 ( .A0(n607), .A1(d_ff_Zn[27]), .B0(n606), .B1(d_ff1_Z[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U1297 ( .A0(n609), .A1(d_ff_Zn[28]), .B0(n712), .B1(d_ff1_Z[28]),
.Y(first_mux_Z[28]) );
AO22XLTS U1298 ( .A0(n609), .A1(d_ff_Zn[29]), .B0(n712), .B1(d_ff1_Z[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U1299 ( .A0(n609), .A1(d_ff_Zn[30]), .B0(n712), .B1(d_ff1_Z[30]),
.Y(first_mux_Z[30]) );
AO22XLTS U1300 ( .A0(n609), .A1(d_ff_Zn[31]), .B0(n712), .B1(d_ff1_Z[31]),
.Y(first_mux_Z[31]) );
AO22XLTS U1301 ( .A0(n613), .A1(d_ff_Zn[32]), .B0(n712), .B1(d_ff1_Z[32]),
.Y(first_mux_Z[32]) );
AO22XLTS U1302 ( .A0(n609), .A1(d_ff_Zn[33]), .B0(n712), .B1(d_ff1_Z[33]),
.Y(first_mux_Z[33]) );
AO22XLTS U1303 ( .A0(n609), .A1(d_ff_Zn[34]), .B0(n712), .B1(d_ff1_Z[34]),
.Y(first_mux_Z[34]) );
AO22XLTS U1304 ( .A0(n609), .A1(d_ff_Zn[35]), .B0(n712), .B1(d_ff1_Z[35]),
.Y(first_mux_Z[35]) );
AO22XLTS U1305 ( .A0(n609), .A1(d_ff_Zn[36]), .B0(n712), .B1(d_ff1_Z[36]),
.Y(first_mux_Z[36]) );
AO22XLTS U1306 ( .A0(n609), .A1(d_ff_Zn[37]), .B0(n712), .B1(d_ff1_Z[37]),
.Y(first_mux_Z[37]) );
AO22XLTS U1307 ( .A0(n609), .A1(d_ff_Zn[38]), .B0(n612), .B1(d_ff1_Z[38]),
.Y(first_mux_Z[38]) );
AO22XLTS U1308 ( .A0(n609), .A1(d_ff_Zn[39]), .B0(n612), .B1(d_ff1_Z[39]),
.Y(first_mux_Z[39]) );
AO22XLTS U1309 ( .A0(n609), .A1(d_ff_Zn[40]), .B0(n612), .B1(d_ff1_Z[40]),
.Y(first_mux_Z[40]) );
AO22XLTS U1310 ( .A0(n609), .A1(d_ff_Zn[41]), .B0(n612), .B1(d_ff1_Z[41]),
.Y(first_mux_Z[41]) );
AO22XLTS U1311 ( .A0(n611), .A1(d_ff_Zn[42]), .B0(n612), .B1(d_ff1_Z[42]),
.Y(first_mux_Z[42]) );
AO22XLTS U1312 ( .A0(n611), .A1(d_ff_Zn[43]), .B0(n612), .B1(d_ff1_Z[43]),
.Y(first_mux_Z[43]) );
AO22XLTS U1313 ( .A0(n611), .A1(d_ff_Zn[45]), .B0(n612), .B1(d_ff1_Z[45]),
.Y(first_mux_Z[45]) );
AO22XLTS U1314 ( .A0(n611), .A1(d_ff_Zn[46]), .B0(n612), .B1(d_ff1_Z[46]),
.Y(first_mux_Z[46]) );
AO22XLTS U1315 ( .A0(n611), .A1(d_ff_Zn[47]), .B0(n610), .B1(d_ff1_Z[47]),
.Y(first_mux_Z[47]) );
AO22XLTS U1316 ( .A0(n611), .A1(d_ff_Zn[48]), .B0(n612), .B1(d_ff1_Z[48]),
.Y(first_mux_Z[48]) );
AO22XLTS U1317 ( .A0(n611), .A1(d_ff_Zn[49]), .B0(n610), .B1(d_ff1_Z[49]),
.Y(first_mux_Z[49]) );
AO22XLTS U1318 ( .A0(n611), .A1(d_ff_Zn[50]), .B0(n612), .B1(d_ff1_Z[50]),
.Y(first_mux_Z[50]) );
AO22XLTS U1319 ( .A0(n611), .A1(d_ff_Zn[51]), .B0(n612), .B1(d_ff1_Z[51]),
.Y(first_mux_Z[51]) );
AO22XLTS U1320 ( .A0(n611), .A1(d_ff_Zn[52]), .B0(n612), .B1(d_ff1_Z[52]),
.Y(first_mux_Z[52]) );
AO22XLTS U1321 ( .A0(n611), .A1(d_ff_Zn[53]), .B0(n612), .B1(d_ff1_Z[53]),
.Y(first_mux_Z[53]) );
AO22XLTS U1322 ( .A0(n611), .A1(d_ff_Zn[54]), .B0(n612), .B1(d_ff1_Z[54]),
.Y(first_mux_Z[54]) );
AO22XLTS U1323 ( .A0(n613), .A1(d_ff_Zn[55]), .B0(n612), .B1(d_ff1_Z[55]),
.Y(first_mux_Z[55]) );
AO22XLTS U1324 ( .A0(n613), .A1(d_ff_Zn[56]), .B0(n612), .B1(d_ff1_Z[56]),
.Y(first_mux_Z[56]) );
AO22XLTS U1325 ( .A0(n613), .A1(d_ff_Zn[57]), .B0(n612), .B1(d_ff1_Z[57]),
.Y(first_mux_Z[57]) );
AO22XLTS U1326 ( .A0(n613), .A1(d_ff_Zn[58]), .B0(n612), .B1(d_ff1_Z[58]),
.Y(first_mux_Z[58]) );
AO22XLTS U1327 ( .A0(n613), .A1(d_ff_Zn[59]), .B0(n612), .B1(d_ff1_Z[59]),
.Y(first_mux_Z[59]) );
AO22XLTS U1328 ( .A0(n613), .A1(d_ff_Zn[60]), .B0(n610), .B1(d_ff1_Z[60]),
.Y(first_mux_Z[60]) );
AO22XLTS U1329 ( .A0(n613), .A1(d_ff_Zn[61]), .B0(n610), .B1(d_ff1_Z[61]),
.Y(first_mux_Z[61]) );
AO22XLTS U1330 ( .A0(n613), .A1(d_ff_Zn[62]), .B0(n610), .B1(d_ff1_Z[62]),
.Y(first_mux_Z[62]) );
AO22XLTS U1331 ( .A0(n613), .A1(d_ff_Zn[63]), .B0(n610), .B1(d_ff1_Z[63]),
.Y(first_mux_Z[63]) );
AO22XLTS U1332 ( .A0(n619), .A1(d_ff_Yn[0]), .B0(n617), .B1(d_ff_Xn[0]), .Y(
mux_sal[0]) );
AO22XLTS U1333 ( .A0(n616), .A1(d_ff_Yn[1]), .B0(n614), .B1(d_ff_Xn[1]), .Y(
mux_sal[1]) );
AO22XLTS U1334 ( .A0(n619), .A1(d_ff_Yn[2]), .B0(n617), .B1(d_ff_Xn[2]), .Y(
mux_sal[2]) );
AO22XLTS U1335 ( .A0(n619), .A1(d_ff_Yn[3]), .B0(n614), .B1(d_ff_Xn[3]), .Y(
mux_sal[3]) );
AO22XLTS U1336 ( .A0(n616), .A1(d_ff_Yn[4]), .B0(n620), .B1(d_ff_Xn[4]), .Y(
mux_sal[4]) );
BUFX4TS U1337 ( .A(n711), .Y(n614) );
AO22XLTS U1338 ( .A0(n616), .A1(d_ff_Yn[5]), .B0(n620), .B1(d_ff_Xn[5]), .Y(
mux_sal[5]) );
AO22XLTS U1339 ( .A0(n616), .A1(d_ff_Yn[6]), .B0(n711), .B1(d_ff_Xn[6]), .Y(
mux_sal[6]) );
AO22XLTS U1340 ( .A0(n619), .A1(d_ff_Yn[7]), .B0(n711), .B1(d_ff_Xn[7]), .Y(
mux_sal[7]) );
AO22XLTS U1341 ( .A0(n619), .A1(d_ff_Yn[8]), .B0(n711), .B1(d_ff_Xn[8]), .Y(
mux_sal[8]) );
AO22XLTS U1342 ( .A0(n619), .A1(d_ff_Yn[9]), .B0(n614), .B1(d_ff_Xn[9]), .Y(
mux_sal[9]) );
AO22XLTS U1343 ( .A0(n619), .A1(d_ff_Yn[10]), .B0(n617), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U1344 ( .A0(n616), .A1(d_ff_Yn[11]), .B0(n617), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U1345 ( .A0(n619), .A1(d_ff_Yn[12]), .B0(n614), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
AO22XLTS U1346 ( .A0(n619), .A1(d_ff_Yn[13]), .B0(n620), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U1347 ( .A0(n616), .A1(d_ff_Yn[14]), .B0(n617), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U1348 ( .A0(n619), .A1(d_ff_Yn[15]), .B0(n614), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U1349 ( .A0(n616), .A1(d_ff_Yn[16]), .B0(n620), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U1350 ( .A0(n619), .A1(d_ff_Yn[17]), .B0(n617), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U1351 ( .A0(n619), .A1(d_ff_Yn[18]), .B0(n614), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U1352 ( .A0(n616), .A1(d_ff_Yn[19]), .B0(n617), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U1353 ( .A0(n619), .A1(d_ff_Yn[20]), .B0(n614), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U1354 ( .A0(n619), .A1(d_ff_Yn[21]), .B0(n620), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U1355 ( .A0(n616), .A1(d_ff_Yn[22]), .B0(n617), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U1356 ( .A0(n619), .A1(d_ff_Yn[23]), .B0(n614), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U1357 ( .A0(n618), .A1(d_ff_Yn[24]), .B0(n620), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U1358 ( .A0(n619), .A1(d_ff_Yn[25]), .B0(n617), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U1359 ( .A0(n616), .A1(d_ff_Yn[26]), .B0(n614), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
AO22XLTS U1360 ( .A0(n618), .A1(d_ff_Yn[27]), .B0(n711), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U1361 ( .A0(n618), .A1(d_ff_Yn[28]), .B0(n614), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U1362 ( .A0(n619), .A1(d_ff_Yn[29]), .B0(n617), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U1363 ( .A0(n616), .A1(d_ff_Yn[30]), .B0(n711), .B1(d_ff_Xn[30]),
.Y(mux_sal[30]) );
AO22XLTS U1364 ( .A0(n618), .A1(d_ff_Yn[31]), .B0(n711), .B1(d_ff_Xn[31]),
.Y(mux_sal[31]) );
AO22XLTS U1365 ( .A0(n619), .A1(d_ff_Yn[32]), .B0(n711), .B1(d_ff_Xn[32]),
.Y(mux_sal[32]) );
AO22XLTS U1366 ( .A0(n618), .A1(d_ff_Yn[33]), .B0(n711), .B1(d_ff_Xn[33]),
.Y(mux_sal[33]) );
AO22XLTS U1367 ( .A0(n619), .A1(d_ff_Yn[34]), .B0(n617), .B1(d_ff_Xn[34]),
.Y(mux_sal[34]) );
AO22XLTS U1368 ( .A0(n618), .A1(d_ff_Yn[35]), .B0(n617), .B1(d_ff_Xn[35]),
.Y(mux_sal[35]) );
AO22XLTS U1369 ( .A0(n619), .A1(d_ff_Yn[36]), .B0(n614), .B1(d_ff_Xn[36]),
.Y(mux_sal[36]) );
AO22XLTS U1370 ( .A0(n616), .A1(d_ff_Yn[37]), .B0(n620), .B1(d_ff_Xn[37]),
.Y(mux_sal[37]) );
AO22XLTS U1371 ( .A0(n618), .A1(d_ff_Yn[38]), .B0(n617), .B1(d_ff_Xn[38]),
.Y(mux_sal[38]) );
AO22XLTS U1372 ( .A0(n618), .A1(d_ff_Yn[39]), .B0(n614), .B1(d_ff_Xn[39]),
.Y(mux_sal[39]) );
AO22XLTS U1373 ( .A0(n618), .A1(d_ff_Yn[40]), .B0(n620), .B1(d_ff_Xn[40]),
.Y(mux_sal[40]) );
AO22XLTS U1374 ( .A0(n618), .A1(d_ff_Yn[41]), .B0(n614), .B1(d_ff_Xn[41]),
.Y(mux_sal[41]) );
AO22XLTS U1375 ( .A0(n618), .A1(d_ff_Yn[42]), .B0(n617), .B1(d_ff_Xn[42]),
.Y(mux_sal[42]) );
AO22XLTS U1376 ( .A0(n618), .A1(d_ff_Yn[43]), .B0(n620), .B1(d_ff_Xn[43]),
.Y(mux_sal[43]) );
AO22XLTS U1377 ( .A0(n618), .A1(d_ff_Yn[44]), .B0(n614), .B1(d_ff_Xn[44]),
.Y(mux_sal[44]) );
AO22XLTS U1378 ( .A0(n618), .A1(d_ff_Yn[45]), .B0(n617), .B1(d_ff_Xn[45]),
.Y(mux_sal[45]) );
AO22XLTS U1379 ( .A0(n618), .A1(d_ff_Yn[46]), .B0(n614), .B1(d_ff_Xn[46]),
.Y(mux_sal[46]) );
AO22XLTS U1380 ( .A0(n618), .A1(d_ff_Yn[47]), .B0(n617), .B1(d_ff_Xn[47]),
.Y(mux_sal[47]) );
AO22XLTS U1381 ( .A0(n618), .A1(d_ff_Yn[48]), .B0(n620), .B1(d_ff_Xn[48]),
.Y(mux_sal[48]) );
BUFX3TS U1382 ( .A(n711), .Y(n620) );
AO22XLTS U1383 ( .A0(n618), .A1(d_ff_Yn[49]), .B0(n614), .B1(d_ff_Xn[49]),
.Y(mux_sal[49]) );
AO22XLTS U1384 ( .A0(n618), .A1(d_ff_Yn[50]), .B0(n617), .B1(d_ff_Xn[50]),
.Y(mux_sal[50]) );
AO22XLTS U1385 ( .A0(n618), .A1(d_ff_Yn[51]), .B0(n620), .B1(d_ff_Xn[51]),
.Y(mux_sal[51]) );
AO22XLTS U1386 ( .A0(n702), .A1(d_ff_Yn[52]), .B0(n614), .B1(d_ff_Xn[52]),
.Y(mux_sal[52]) );
AO22XLTS U1387 ( .A0(n702), .A1(d_ff_Yn[53]), .B0(n617), .B1(d_ff_Xn[53]),
.Y(mux_sal[53]) );
AO22XLTS U1388 ( .A0(n702), .A1(d_ff_Yn[54]), .B0(n617), .B1(d_ff_Xn[54]),
.Y(mux_sal[54]) );
AO22XLTS U1389 ( .A0(n702), .A1(d_ff_Yn[55]), .B0(n614), .B1(d_ff_Xn[55]),
.Y(mux_sal[55]) );
AO22XLTS U1390 ( .A0(n702), .A1(d_ff_Yn[56]), .B0(n620), .B1(d_ff_Xn[56]),
.Y(mux_sal[56]) );
AO22XLTS U1391 ( .A0(n702), .A1(d_ff_Yn[57]), .B0(n617), .B1(d_ff_Xn[57]),
.Y(mux_sal[57]) );
AO22XLTS U1392 ( .A0(n702), .A1(d_ff_Yn[58]), .B0(n614), .B1(d_ff_Xn[58]),
.Y(mux_sal[58]) );
AO22XLTS U1393 ( .A0(n618), .A1(d_ff_Yn[59]), .B0(n620), .B1(d_ff_Xn[59]),
.Y(mux_sal[59]) );
AO22XLTS U1394 ( .A0(n618), .A1(d_ff_Yn[60]), .B0(n711), .B1(d_ff_Xn[60]),
.Y(mux_sal[60]) );
AO22XLTS U1395 ( .A0(n619), .A1(d_ff_Yn[61]), .B0(n617), .B1(d_ff_Xn[61]),
.Y(mux_sal[61]) );
AO22XLTS U1396 ( .A0(n702), .A1(d_ff_Yn[62]), .B0(n614), .B1(d_ff_Xn[62]),
.Y(mux_sal[62]) );
AO22XLTS U1397 ( .A0(n702), .A1(d_ff_Yn[63]), .B0(n620), .B1(d_ff_Xn[63]),
.Y(mux_sal[63]) );
AOI32X1TS U1398 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(n713), .A2(
d_ff1_operation_out), .B0(n621), .B1(d_ff1_shift_region_flag_out[0]),
.Y(n622) );
XNOR2X1TS U1399 ( .A(data_output2_63_), .B(n622), .Y(sign_inv_out[63]) );
NAND4XLTS U1400 ( .A(n639), .B(n625), .C(n623), .D(n624), .Y(data_out_LUT[0]) );
NAND4XLTS U1401 ( .A(n639), .B(n637), .C(n626), .D(data_out_LUT[40]), .Y(
data_out_LUT[1]) );
INVX2TS U1402 ( .A(n645), .Y(n629) );
NAND2X1TS U1403 ( .A(n627), .B(n629), .Y(data_out_LUT[2]) );
NAND2X1TS U1404 ( .A(cont_iter_out[2]), .B(cont_iter_out[3]), .Y(n643) );
NAND4XLTS U1405 ( .A(n637), .B(n623), .C(data_out_LUT[40]), .D(n643), .Y(
data_out_LUT[6]) );
NAND3X1TS U1406 ( .A(n716), .B(cont_iter_out[3]), .C(n628), .Y(n636) );
OA21XLTS U1407 ( .A0(n629), .A1(n704), .B0(n636), .Y(n652) );
NAND4XLTS U1408 ( .A(n639), .B(n652), .C(n623), .D(n648), .Y(data_out_LUT[7]) );
INVX2TS U1409 ( .A(data_out_LUT[22]), .Y(n642) );
NAND2X1TS U1410 ( .A(n637), .B(n642), .Y(data_out_LUT[8]) );
OAI21XLTS U1411 ( .A0(n716), .A1(data_out_LUT[20]), .B0(n635), .Y(n630) );
OAI2BB1X1TS U1412 ( .A0N(n631), .A1N(n645), .B0(n630), .Y(data_out_LUT[9])
);
NAND2X1TS U1413 ( .A(n645), .B(n631), .Y(n632) );
NAND4XLTS U1414 ( .A(n637), .B(n633), .C(n641), .D(n632), .Y(
data_out_LUT[11]) );
NAND4XLTS U1415 ( .A(n653), .B(n639), .C(n636), .D(n644), .Y(
data_out_LUT[13]) );
OA21XLTS U1416 ( .A0(n633), .A1(n704), .B0(n641), .Y(n634) );
NAND4XLTS U1417 ( .A(n634), .B(n623), .C(n648), .D(data_out_LUT[40]), .Y(
data_out_LUT[15]) );
NAND4XLTS U1418 ( .A(n637), .B(data_out_LUT[50]), .C(n636), .D(n635), .Y(
data_out_LUT[35]) );
NAND2BXLTS U1419 ( .AN(data_out_LUT[35]), .B(n623), .Y(data_out_LUT[18]) );
NAND3XLTS U1420 ( .A(n639), .B(n638), .C(n623), .Y(data_out_LUT[19]) );
NAND2X1TS U1421 ( .A(n640), .B(data_out_LUT[22]), .Y(data_out_LUT[21]) );
NAND3XLTS U1422 ( .A(n642), .B(n648), .C(n641), .Y(data_out_LUT[26]) );
NAND2X1TS U1423 ( .A(n647), .B(data_out_LUT[47]), .Y(data_out_LUT[30]) );
NAND4XLTS U1424 ( .A(n623), .B(n648), .C(n644), .D(n643), .Y(
data_out_LUT[29]) );
AO21XLTS U1425 ( .A0(n716), .A1(n645), .B0(data_out_LUT[29]), .Y(
data_out_LUT[31]) );
NAND2X1TS U1426 ( .A(cont_iter_out[2]), .B(n704), .Y(data_out_LUT[37]) );
NAND3XLTS U1427 ( .A(n704), .B(data_out_LUT[50]), .C(n646), .Y(
data_out_LUT[39]) );
NAND2BXLTS U1428 ( .AN(data_out_LUT[16]), .B(n623), .Y(data_out_LUT[43]) );
NAND2X1TS U1429 ( .A(n647), .B(n623), .Y(data_out_LUT[41]) );
NAND2BXLTS U1430 ( .AN(data_out_LUT[16]), .B(n648), .Y(data_out_LUT[12]) );
NAND2BXLTS U1431 ( .AN(data_out_LUT[12]), .B(n623), .Y(data_out_LUT[24]) );
NAND3XLTS U1432 ( .A(n653), .B(n649), .C(n623), .Y(data_out_LUT[55]) );
OAI21XLTS U1433 ( .A0(n650), .A1(n704), .B0(n767), .Y(n651) );
NAND3XLTS U1434 ( .A(n653), .B(n652), .C(n651), .Y(data_out_LUT[3]) );
NAND2BXLTS U1435 ( .AN(d_ff_Xn[0]), .B(n654), .Y(first_mux_X[0]) );
CLKAND2X2TS U1436 ( .A(d_ff_Xn[1]), .B(n655), .Y(first_mux_X[1]) );
CLKAND2X2TS U1437 ( .A(d_ff_Xn[2]), .B(n656), .Y(first_mux_X[2]) );
NAND2BXLTS U1438 ( .AN(d_ff_Xn[3]), .B(n654), .Y(first_mux_X[3]) );
CLKAND2X2TS U1439 ( .A(d_ff_Xn[4]), .B(n655), .Y(first_mux_X[4]) );
CLKAND2X2TS U1440 ( .A(d_ff_Xn[5]), .B(n656), .Y(first_mux_X[5]) );
NAND2BXLTS U1441 ( .AN(d_ff_Xn[6]), .B(n655), .Y(first_mux_X[6]) );
NAND2BXLTS U1442 ( .AN(d_ff_Xn[7]), .B(n656), .Y(first_mux_X[7]) );
NAND2BXLTS U1443 ( .AN(d_ff_Xn[8]), .B(n657), .Y(first_mux_X[8]) );
NAND2BXLTS U1444 ( .AN(d_ff_Xn[9]), .B(n655), .Y(first_mux_X[9]) );
CLKAND2X2TS U1445 ( .A(d_ff_Xn[10]), .B(n657), .Y(first_mux_X[10]) );
NAND2BXLTS U1446 ( .AN(d_ff_Xn[11]), .B(n654), .Y(first_mux_X[11]) );
CLKAND2X2TS U1447 ( .A(d_ff_Xn[12]), .B(n657), .Y(first_mux_X[12]) );
NAND2BXLTS U1448 ( .AN(d_ff_Xn[13]), .B(n655), .Y(first_mux_X[13]) );
NAND2BXLTS U1449 ( .AN(d_ff_Xn[14]), .B(n656), .Y(first_mux_X[14]) );
CLKAND2X2TS U1450 ( .A(d_ff_Xn[15]), .B(n655), .Y(first_mux_X[15]) );
CLKAND2X2TS U1451 ( .A(d_ff_Xn[16]), .B(n656), .Y(first_mux_X[16]) );
CLKAND2X2TS U1452 ( .A(d_ff_Xn[17]), .B(n656), .Y(first_mux_X[17]) );
CLKAND2X2TS U1453 ( .A(d_ff_Xn[18]), .B(n654), .Y(first_mux_X[18]) );
NAND2BXLTS U1454 ( .AN(d_ff_Xn[19]), .B(n657), .Y(first_mux_X[19]) );
CLKAND2X2TS U1455 ( .A(d_ff_Xn[20]), .B(n654), .Y(first_mux_X[20]) );
CLKAND2X2TS U1456 ( .A(d_ff_Xn[21]), .B(n656), .Y(first_mux_X[21]) );
CLKAND2X2TS U1457 ( .A(d_ff_Xn[22]), .B(n657), .Y(first_mux_X[22]) );
CLKAND2X2TS U1458 ( .A(d_ff_Xn[23]), .B(n657), .Y(first_mux_X[23]) );
NAND2BXLTS U1459 ( .AN(d_ff_Xn[24]), .B(n656), .Y(first_mux_X[24]) );
CLKAND2X2TS U1460 ( .A(d_ff_Xn[25]), .B(n657), .Y(first_mux_X[25]) );
NAND2BXLTS U1461 ( .AN(d_ff_Xn[26]), .B(n657), .Y(first_mux_X[26]) );
CLKAND2X2TS U1462 ( .A(d_ff_Xn[27]), .B(n657), .Y(first_mux_X[27]) );
NAND2BXLTS U1463 ( .AN(d_ff_Xn[28]), .B(n657), .Y(first_mux_X[28]) );
NAND2BXLTS U1464 ( .AN(d_ff_Xn[29]), .B(n656), .Y(first_mux_X[29]) );
CLKAND2X2TS U1465 ( .A(d_ff_Xn[30]), .B(n657), .Y(first_mux_X[30]) );
NAND2BXLTS U1466 ( .AN(d_ff_Xn[31]), .B(n654), .Y(first_mux_X[31]) );
NAND2BXLTS U1467 ( .AN(d_ff_Xn[32]), .B(n654), .Y(first_mux_X[32]) );
CLKAND2X2TS U1468 ( .A(d_ff_Xn[33]), .B(n657), .Y(first_mux_X[33]) );
NAND2BXLTS U1469 ( .AN(d_ff_Xn[34]), .B(n655), .Y(first_mux_X[34]) );
NAND2BXLTS U1470 ( .AN(d_ff_Xn[35]), .B(n656), .Y(first_mux_X[35]) );
NAND2BXLTS U1471 ( .AN(d_ff_Xn[36]), .B(n657), .Y(first_mux_X[36]) );
CLKAND2X2TS U1472 ( .A(d_ff_Xn[37]), .B(n657), .Y(first_mux_X[37]) );
CLKAND2X2TS U1473 ( .A(d_ff_Xn[38]), .B(n654), .Y(first_mux_X[38]) );
NAND2BXLTS U1474 ( .AN(d_ff_Xn[39]), .B(n657), .Y(first_mux_X[39]) );
CLKAND2X2TS U1475 ( .A(d_ff_Xn[40]), .B(n657), .Y(first_mux_X[40]) );
NAND2BXLTS U1476 ( .AN(d_ff_Xn[41]), .B(n654), .Y(first_mux_X[41]) );
NAND2BXLTS U1477 ( .AN(d_ff_Xn[42]), .B(n655), .Y(first_mux_X[42]) );
NAND2BXLTS U1478 ( .AN(d_ff_Xn[43]), .B(n656), .Y(first_mux_X[43]) );
CLKAND2X2TS U1479 ( .A(d_ff_Xn[44]), .B(n657), .Y(first_mux_X[44]) );
NAND2BXLTS U1480 ( .AN(d_ff_Xn[45]), .B(n655), .Y(first_mux_X[45]) );
NAND2BXLTS U1481 ( .AN(d_ff_Xn[46]), .B(n656), .Y(first_mux_X[46]) );
CLKAND2X2TS U1482 ( .A(d_ff_Xn[47]), .B(n657), .Y(first_mux_X[47]) );
NAND2BXLTS U1483 ( .AN(d_ff_Xn[48]), .B(n613), .Y(first_mux_X[48]) );
NAND2BXLTS U1484 ( .AN(d_ff_Xn[49]), .B(n657), .Y(first_mux_X[49]) );
CLKAND2X2TS U1485 ( .A(d_ff_Xn[50]), .B(n655), .Y(first_mux_X[50]) );
CLKAND2X2TS U1486 ( .A(d_ff_Xn[51]), .B(n655), .Y(first_mux_X[51]) );
CLKAND2X2TS U1487 ( .A(d_ff_Xn[52]), .B(n654), .Y(first_mux_X[52]) );
NAND2BXLTS U1488 ( .AN(d_ff_Xn[53]), .B(n611), .Y(first_mux_X[53]) );
NAND2BXLTS U1489 ( .AN(d_ff_Xn[54]), .B(n613), .Y(first_mux_X[54]) );
NAND2BXLTS U1490 ( .AN(d_ff_Xn[55]), .B(n654), .Y(first_mux_X[55]) );
NAND2BXLTS U1491 ( .AN(d_ff_Xn[56]), .B(n655), .Y(first_mux_X[56]) );
NAND2BXLTS U1492 ( .AN(d_ff_Xn[57]), .B(n654), .Y(first_mux_X[57]) );
NAND2BXLTS U1493 ( .AN(d_ff_Xn[58]), .B(n656), .Y(first_mux_X[58]) );
NAND2BXLTS U1494 ( .AN(d_ff_Xn[59]), .B(n655), .Y(first_mux_X[59]) );
NAND2BXLTS U1495 ( .AN(d_ff_Xn[60]), .B(n611), .Y(first_mux_X[60]) );
NAND2BXLTS U1496 ( .AN(d_ff_Xn[61]), .B(n654), .Y(first_mux_X[61]) );
CLKAND2X2TS U1497 ( .A(d_ff_Xn[62]), .B(n655), .Y(first_mux_X[62]) );
CLKAND2X2TS U1498 ( .A(d_ff_Xn[63]), .B(n656), .Y(first_mux_X[63]) );
AO22XLTS U1499 ( .A0(n576), .A1(d_ff3_sh_x_out[63]), .B0(n658), .B1(
d_ff3_sh_y_out[63]), .Y(add_subt_dataB[63]) );
AO22XLTS U1500 ( .A0(n576), .A1(d_ff3_sh_x_out[62]), .B0(n658), .B1(
d_ff3_sh_y_out[62]), .Y(add_subt_dataB[62]) );
AOI22X1TS U1501 ( .A0(n678), .A1(d_ff3_sh_x_out[61]), .B0(n682), .B1(
d_ff3_sh_y_out[61]), .Y(n659) );
NAND2X2TS U1502 ( .A(n424), .B(d_ff3_LUT_out[48]), .Y(n666) );
NAND2X1TS U1503 ( .A(n659), .B(n666), .Y(add_subt_dataB[61]) );
AOI22X1TS U1504 ( .A0(n678), .A1(d_ff3_sh_x_out[60]), .B0(n677), .B1(
d_ff3_sh_y_out[60]), .Y(n660) );
NAND2X1TS U1505 ( .A(n660), .B(n666), .Y(add_subt_dataB[60]) );
AOI22X1TS U1506 ( .A0(n678), .A1(d_ff3_sh_x_out[59]), .B0(n687), .B1(
d_ff3_sh_y_out[59]), .Y(n661) );
NAND2X1TS U1507 ( .A(n661), .B(n666), .Y(add_subt_dataB[59]) );
AOI22X1TS U1508 ( .A0(n678), .A1(d_ff3_sh_x_out[58]), .B0(n682), .B1(
d_ff3_sh_y_out[58]), .Y(n662) );
NAND2X1TS U1509 ( .A(n662), .B(n666), .Y(add_subt_dataB[58]) );
AOI22X1TS U1510 ( .A0(n678), .A1(d_ff3_sh_x_out[57]), .B0(n677), .B1(
d_ff3_sh_y_out[57]), .Y(n663) );
NAND2X1TS U1511 ( .A(n663), .B(n666), .Y(add_subt_dataB[57]) );
AOI22X1TS U1512 ( .A0(n678), .A1(d_ff3_sh_x_out[51]), .B0(n682), .B1(
d_ff3_sh_y_out[51]), .Y(n664) );
NAND2X1TS U1513 ( .A(n664), .B(n666), .Y(add_subt_dataB[51]) );
AOI22X1TS U1514 ( .A0(n683), .A1(d_ff3_sh_x_out[49]), .B0(n687), .B1(
d_ff3_sh_y_out[49]), .Y(n665) );
NAND2X1TS U1515 ( .A(n424), .B(d_ff3_LUT_out[49]), .Y(n670) );
NAND2X1TS U1516 ( .A(n665), .B(n670), .Y(add_subt_dataB[49]) );
AOI22X1TS U1517 ( .A0(n678), .A1(d_ff3_sh_x_out[48]), .B0(n687), .B1(
d_ff3_sh_y_out[48]), .Y(n667) );
NAND2X1TS U1518 ( .A(n667), .B(n666), .Y(add_subt_dataB[48]) );
AOI22X1TS U1519 ( .A0(n683), .A1(d_ff3_sh_x_out[47]), .B0(n682), .B1(
d_ff3_sh_y_out[47]), .Y(n668) );
OAI2BB1X1TS U1520 ( .A0N(n675), .A1N(d_ff3_LUT_out[47]), .B0(n668), .Y(
add_subt_dataB[47]) );
AOI22X1TS U1521 ( .A0(n678), .A1(d_ff3_sh_x_out[46]), .B0(n677), .B1(
d_ff3_sh_y_out[46]), .Y(n669) );
NAND2X1TS U1522 ( .A(n669), .B(n670), .Y(add_subt_dataB[46]) );
AOI22X1TS U1523 ( .A0(n678), .A1(d_ff3_sh_x_out[44]), .B0(n687), .B1(
d_ff3_sh_y_out[44]), .Y(n671) );
NAND2X1TS U1524 ( .A(n671), .B(n670), .Y(add_subt_dataB[44]) );
AOI22X1TS U1525 ( .A0(n678), .A1(d_ff3_sh_x_out[42]), .B0(n682), .B1(
d_ff3_sh_y_out[42]), .Y(n672) );
OAI2BB1X1TS U1526 ( .A0N(n686), .A1N(d_ff3_LUT_out[47]), .B0(n672), .Y(
add_subt_dataB[42]) );
AOI22X1TS U1527 ( .A0(n683), .A1(d_ff3_sh_x_out[40]), .B0(n682), .B1(
d_ff3_sh_y_out[40]), .Y(n673) );
NAND2X1TS U1528 ( .A(n424), .B(d_ff3_LUT_out[40]), .Y(n680) );
NAND2X1TS U1529 ( .A(n673), .B(n680), .Y(add_subt_dataB[40]) );
AOI22X1TS U1530 ( .A0(n678), .A1(d_ff3_sh_x_out[38]), .B0(n682), .B1(
d_ff3_sh_y_out[38]), .Y(n674) );
OAI2BB1X1TS U1531 ( .A0N(n675), .A1N(d_ff3_LUT_out[38]), .B0(n674), .Y(
add_subt_dataB[38]) );
AOI22X1TS U1532 ( .A0(n683), .A1(d_ff3_sh_x_out[36]), .B0(n682), .B1(
d_ff3_sh_y_out[36]), .Y(n676) );
NAND2X1TS U1533 ( .A(n676), .B(n680), .Y(add_subt_dataB[36]) );
AOI22X1TS U1534 ( .A0(n678), .A1(d_ff3_sh_x_out[32]), .B0(n677), .B1(
d_ff3_sh_y_out[32]), .Y(n679) );
OAI2BB1X1TS U1535 ( .A0N(n686), .A1N(d_ff3_LUT_out[38]), .B0(n679), .Y(
add_subt_dataB[32]) );
AOI22X1TS U1536 ( .A0(n683), .A1(d_ff3_sh_x_out[28]), .B0(n682), .B1(
d_ff3_sh_y_out[28]), .Y(n681) );
NAND2X1TS U1537 ( .A(n681), .B(n680), .Y(add_subt_dataB[28]) );
AOI22X1TS U1538 ( .A0(n683), .A1(d_ff3_sh_x_out[4]), .B0(n682), .B1(
d_ff3_sh_y_out[4]), .Y(n684) );
OAI2BB1X1TS U1539 ( .A0N(n685), .A1N(d_ff3_LUT_out[30]), .B0(n684), .Y(
add_subt_dataB[4]) );
AOI22X1TS U1540 ( .A0(d_ff2_X[59]), .A1(n687), .B0(n686), .B1(d_ff2_Z[59]),
.Y(n688) );
OAI2BB1X1TS U1541 ( .A0N(d_ff2_Y[59]), .A1N(n576), .B0(n688), .Y(
add_subt_dataA[59]) );
XNOR2X1TS U1542 ( .A(cont_var_out[0]), .B(d_ff3_sign_out), .Y(op_add_subt)
);
XOR2XLTS U1544 ( .A(d_ff2_Y[61]), .B(n693), .Y(sh_exp_y[9]) );
AO21XLTS U1545 ( .A0(d_ff2_Y[60]), .A1(n689), .B0(n693), .Y(sh_exp_y[8]) );
AO21XLTS U1546 ( .A0(d_ff2_Y[58]), .A1(n691), .B0(n690), .Y(sh_exp_y[6]) );
AO21XLTS U1547 ( .A0(intadd_458_n1), .A1(d_ff2_Y[56]), .B0(n692), .Y(
sh_exp_y[4]) );
NOR2BX1TS U1548 ( .AN(n693), .B(d_ff2_Y[61]), .Y(n694) );
XOR2XLTS U1549 ( .A(n694), .B(d_ff2_Y[62]), .Y(sh_exp_y[10]) );
XOR2XLTS U1550 ( .A(d_ff2_X[61]), .B(n699), .Y(sh_exp_x[9]) );
AO21XLTS U1551 ( .A0(d_ff2_X[60]), .A1(n695), .B0(n699), .Y(sh_exp_x[8]) );
AO21XLTS U1552 ( .A0(d_ff2_X[58]), .A1(n697), .B0(n696), .Y(sh_exp_x[6]) );
AO21XLTS U1553 ( .A0(intadd_457_n1), .A1(d_ff2_X[56]), .B0(n698), .Y(
sh_exp_x[4]) );
NOR2BX1TS U1554 ( .AN(n699), .B(d_ff2_X[61]), .Y(n700) );
XOR2XLTS U1555 ( .A(n700), .B(d_ff2_X[62]), .Y(sh_exp_x[10]) );
initial $sdf_annotate("CORDIC_Arch2v1_ASIC_fpu_syn_constraints_clk40.tcl_GATED_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_SYMBOL_V
`define SKY130_FD_SC_HS__DLRBN_SYMBOL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlrbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_SYMBOL_V
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_64x24.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.9 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.8 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3 2003/04/07 01:19:07 lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/11/02 18:57:14 lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7 2001/10/22 19:39:56 lampret
// Fixed parameters in generic sprams.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_64x24(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 6;
parameter dw = 24;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_XILINX_RAMB4
wire [7:0] unconnected;
`else
`ifdef OR1200_XILINX_RAMB16
wire [7:0] unconnected;
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_64x24 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_64x24_bist artisan_ssp(
`else
art_hssp_64x24 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_64x24 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_64x24_bist vs_ssp(
`else
vs_hdsp_64x24 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI(di[15:0]),
.EN(ce),
.WE(we),
.DO(doq[15:0])
);
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
.CLK(clk),
.RST(rst),
.ADDR({2'b00, addr}),
.DI({8'h00, di[23:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[23:16]})
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
RAMB16_S36 ramb16_s36(
.CLK(clk),
.SSR(rst),
.ADDR({3'b000, addr}),
.DI({8'h00,di}),
.DIP(4'h0),
.EN(ce),
.WE(we),
.DO({unconnected, doq}),
.DOP()
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
// Date : Thu Apr 5 01:27:51 2018
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v
// Design : design_1_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.4.1" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK0_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP0_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP0_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP0_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB0_PORT_INDCTL_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "FALSE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "0" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(NLW_inst_FCLK_CLK0_UNCONNECTED),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(1'b0),
.M_AXI_GP0_ARADDR(NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP0_ARBURST(NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP0_ARCACHE(NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(NLW_inst_M_AXI_GP0_ARID_UNCONNECTED[11:0]),
.M_AXI_GP0_ARLEN(NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP0_ARLOCK(NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP0_ARPROT(NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP0_ARQOS(NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP0_ARREADY(1'b0),
.M_AXI_GP0_ARSIZE(NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP0_ARVALID(NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED),
.M_AXI_GP0_AWADDR(NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP0_AWBURST(NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP0_AWCACHE(NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP0_AWID(NLW_inst_M_AXI_GP0_AWID_UNCONNECTED[11:0]),
.M_AXI_GP0_AWLEN(NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP0_AWLOCK(NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP0_AWPROT(NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP0_AWQOS(NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP0_AWREADY(1'b0),
.M_AXI_GP0_AWSIZE(NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP0_AWVALID(NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED),
.M_AXI_GP0_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP0_BREADY(NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED),
.M_AXI_GP0_BRESP({1'b0,1'b0}),
.M_AXI_GP0_BVALID(1'b0),
.M_AXI_GP0_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP0_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP0_RLAST(1'b0),
.M_AXI_GP0_RREADY(NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED),
.M_AXI_GP0_RRESP({1'b0,1'b0}),
.M_AXI_GP0_RVALID(1'b0),
.M_AXI_GP0_WDATA(NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP0_WID(NLW_inst_M_AXI_GP0_WID_UNCONNECTED[11:0]),
.M_AXI_GP0_WLAST(NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED),
.M_AXI_GP0_WREADY(1'b0),
.M_AXI_GP0_WSTRB(NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP0_WVALID(NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED),
.TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED),
.TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(NLW_inst_USB0_PORT_INDCTL_UNCONNECTED[1:0]),
.USB0_VBUS_PWRFAULT(1'b0),
.USB0_VBUS_PWRSELECT(NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "FALSE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "0" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK0}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:48:20 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_1_0/system_axi_gpio_1_0_sim_netlist.v
// Design : system_axi_gpio_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_axi_gpio_1_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_axi_gpio_1_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT" *) output ip2intc_irpt;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [15:0]gpio_io_i;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_O" *) output [15:0]gpio_io_o;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_T" *) output [15:0]gpio_io_t;
wire [15:0]gpio_io_i;
wire [15:0]gpio_io_o;
wire [15:0]gpio_io_t;
wire ip2intc_irpt;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "0" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "artix7" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "16" *)
(* C_INTERRUPT_PRESENT = "1" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
system_axi_gpio_1_0_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.ip2intc_irpt(ip2intc_irpt),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "GPIO_Core" *)
module system_axi_gpio_1_0_GPIO_Core
(ip2bus_data,
GPIO_xferAck_i,
gpio_xferAck_Reg,
GPIO_intr,
Q,
gpio_io_o,
gpio_io_t,
Read_Reg_Rst,
\Not_Dual.gpio_OE_reg[15]_0 ,
s_axi_aclk,
\Not_Dual.gpio_OE_reg[14]_0 ,
\Not_Dual.gpio_OE_reg[13]_0 ,
\Not_Dual.gpio_OE_reg[12]_0 ,
\Not_Dual.gpio_OE_reg[11]_0 ,
\Not_Dual.gpio_OE_reg[10]_0 ,
\Not_Dual.gpio_OE_reg[9]_0 ,
\Not_Dual.gpio_OE_reg[8]_0 ,
\Not_Dual.gpio_OE_reg[7]_0 ,
\Not_Dual.gpio_OE_reg[6]_0 ,
\Not_Dual.gpio_OE_reg[5]_0 ,
\Not_Dual.gpio_OE_reg[4]_0 ,
\Not_Dual.gpio_OE_reg[3]_0 ,
\Not_Dual.gpio_OE_reg[2]_0 ,
\Not_Dual.gpio_OE_reg[1]_0 ,
GPIO_DBus_i,
bus2ip_reset,
bus2ip_cs,
gpio_io_i,
E,
D,
bus2ip_rnw_i_reg);
output [15:0]ip2bus_data;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output GPIO_intr;
output [15:0]Q;
output [15:0]gpio_io_o;
output [15:0]gpio_io_t;
input Read_Reg_Rst;
input \Not_Dual.gpio_OE_reg[15]_0 ;
input s_axi_aclk;
input \Not_Dual.gpio_OE_reg[14]_0 ;
input \Not_Dual.gpio_OE_reg[13]_0 ;
input \Not_Dual.gpio_OE_reg[12]_0 ;
input \Not_Dual.gpio_OE_reg[11]_0 ;
input \Not_Dual.gpio_OE_reg[10]_0 ;
input \Not_Dual.gpio_OE_reg[9]_0 ;
input \Not_Dual.gpio_OE_reg[8]_0 ;
input \Not_Dual.gpio_OE_reg[7]_0 ;
input \Not_Dual.gpio_OE_reg[6]_0 ;
input \Not_Dual.gpio_OE_reg[5]_0 ;
input \Not_Dual.gpio_OE_reg[4]_0 ;
input \Not_Dual.gpio_OE_reg[3]_0 ;
input \Not_Dual.gpio_OE_reg[2]_0 ;
input \Not_Dual.gpio_OE_reg[1]_0 ;
input [0:0]GPIO_DBus_i;
input bus2ip_reset;
input [0:0]bus2ip_cs;
input [15:0]gpio_io_i;
input [0:0]E;
input [15:0]D;
input [0:0]bus2ip_rnw_i_reg;
wire [15:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ;
wire \Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ;
wire \Not_Dual.gpio_OE_reg[10]_0 ;
wire \Not_Dual.gpio_OE_reg[11]_0 ;
wire \Not_Dual.gpio_OE_reg[12]_0 ;
wire \Not_Dual.gpio_OE_reg[13]_0 ;
wire \Not_Dual.gpio_OE_reg[14]_0 ;
wire \Not_Dual.gpio_OE_reg[15]_0 ;
wire \Not_Dual.gpio_OE_reg[1]_0 ;
wire \Not_Dual.gpio_OE_reg[2]_0 ;
wire \Not_Dual.gpio_OE_reg[3]_0 ;
wire \Not_Dual.gpio_OE_reg[4]_0 ;
wire \Not_Dual.gpio_OE_reg[5]_0 ;
wire \Not_Dual.gpio_OE_reg[6]_0 ;
wire \Not_Dual.gpio_OE_reg[7]_0 ;
wire \Not_Dual.gpio_OE_reg[8]_0 ;
wire \Not_Dual.gpio_OE_reg[9]_0 ;
wire [15:0]Q;
wire Read_Reg_Rst;
wire [0:0]bus2ip_cs;
wire bus2ip_reset;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:15]gpio_data_in_xor;
wire [15:0]gpio_io_i;
wire [0:15]gpio_io_i_d2;
wire [15:0]gpio_io_o;
wire [15:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire [15:0]ip2bus_data;
wire or_ints;
wire p_11_in;
wire p_12_in;
wire p_13_in;
wire p_1_in;
wire p_2_in;
wire p_3_in;
wire p_4_in;
wire p_5_in;
wire p_6_in;
wire p_9_in;
wire s_axi_aclk;
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_1
(.I0(p_12_in),
.I1(p_11_in),
.I2(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15] ),
.I3(p_13_in),
.I4(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ),
.I5(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ),
.O(or_ints));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2
(.I0(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
.I1(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
.I2(p_2_in),
.I3(p_1_in),
.I4(p_3_in),
.I5(p_4_in),
.O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3
(.I0(p_6_in),
.I1(p_5_in),
.I2(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ),
.I3(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ),
.I4(p_9_in),
.I5(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ),
.O(\Not_Dual.GEN_INTERRUPT.GPIO_intr_i_3_n_0 ));
FDRE \Not_Dual.GEN_INTERRUPT.GPIO_intr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(or_ints),
.Q(GPIO_intr),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[0]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[10]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[10]),
.Q(p_9_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[11]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[11]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[11] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[12]),
.Q(p_11_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[13]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[13]),
.Q(p_12_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[14]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[14]),
.Q(p_13_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[15]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[15]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[15] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[1]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[2]),
.Q(p_1_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[3]),
.Q(p_2_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[4]),
.Q(p_3_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[5]),
.Q(p_4_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[6]),
.Q(p_5_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[7]),
.Q(p_6_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[8]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[8] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[9]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[9]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[9] ),
.R(bus2ip_reset));
system_axi_gpio_1_0_cdc_sync \Not_Dual.INPUT_DOUBLE_REGS3
(.D({gpio_data_in_xor[0],gpio_data_in_xor[1],gpio_data_in_xor[2],gpio_data_in_xor[3],gpio_data_in_xor[4],gpio_data_in_xor[5],gpio_data_in_xor[6],gpio_data_in_xor[7],gpio_data_in_xor[8],gpio_data_in_xor[9],gpio_data_in_xor[10],gpio_data_in_xor[11],gpio_data_in_xor[12],gpio_data_in_xor[13],gpio_data_in_xor[14],gpio_data_in_xor[15]}),
.Q(Q),
.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4],gpio_io_i_d2[5],gpio_io_i_d2[6],gpio_io_i_d2[7],gpio_io_i_d2[8],gpio_io_i_d2[9],gpio_io_i_d2[10],gpio_io_i_d2[11],gpio_io_i_d2[12],gpio_io_i_d2[13],gpio_io_i_d2[14],gpio_io_i_d2[15]}));
FDRE \Not_Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[16]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus_i),
.Q(ip2bus_data[15]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[10]_0 ),
.Q(ip2bus_data[5]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[11]_0 ),
.Q(ip2bus_data[4]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[12]_0 ),
.Q(ip2bus_data[3]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[13]_0 ),
.Q(ip2bus_data[2]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[14]_0 ),
.Q(ip2bus_data[1]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[15]_0 ),
.Q(ip2bus_data[0]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[1]_0 ),
.Q(ip2bus_data[14]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[2]_0 ),
.Q(ip2bus_data[13]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[3]_0 ),
.Q(ip2bus_data[12]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[4]_0 ),
.Q(ip2bus_data[11]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[5]_0 ),
.Q(ip2bus_data[10]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[6]_0 ),
.Q(ip2bus_data[9]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[7]_0 ),
.Q(ip2bus_data[8]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[8]_0 ),
.Q(ip2bus_data[7]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[9]_0 ),
.Q(ip2bus_data[6]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(Q[15]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[10]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[10]),
.Q(Q[5]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[11]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[11]),
.Q(Q[4]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[12]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[12]),
.Q(Q[3]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[13]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[13]),
.Q(Q[2]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[14]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[14]),
.Q(Q[1]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[15]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[15]),
.Q(Q[0]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(Q[14]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(Q[13]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(Q[12]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[4]),
.Q(Q[11]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[5]),
.Q(Q[10]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[6]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[6]),
.Q(Q[9]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[7]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[7]),
.Q(Q[8]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[8]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[8]),
.Q(Q[7]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[9]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[9]),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[15]),
.Q(gpio_io_o[15]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[10]
(.C(s_axi_aclk),
.CE(E),
.D(D[5]),
.Q(gpio_io_o[5]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[11]
(.C(s_axi_aclk),
.CE(E),
.D(D[4]),
.Q(gpio_io_o[4]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[12]
(.C(s_axi_aclk),
.CE(E),
.D(D[3]),
.Q(gpio_io_o[3]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[13]
(.C(s_axi_aclk),
.CE(E),
.D(D[2]),
.Q(gpio_io_o[2]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[14]
(.C(s_axi_aclk),
.CE(E),
.D(D[1]),
.Q(gpio_io_o[1]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[15]
(.C(s_axi_aclk),
.CE(E),
.D(D[0]),
.Q(gpio_io_o[0]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[14]),
.Q(gpio_io_o[14]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[13]),
.Q(gpio_io_o[13]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(D[12]),
.Q(gpio_io_o[12]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(D[11]),
.Q(gpio_io_o[11]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(D[10]),
.Q(gpio_io_o[10]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(D[9]),
.Q(gpio_io_o[9]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(D[8]),
.Q(gpio_io_o[8]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[8]
(.C(s_axi_aclk),
.CE(E),
.D(D[7]),
.Q(gpio_io_o[7]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[9]
(.C(s_axi_aclk),
.CE(E),
.D(D[6]),
.Q(gpio_io_o[6]),
.R(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[15]),
.Q(gpio_io_t[15]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[10]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[5]),
.Q(gpio_io_t[5]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[11]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[4]),
.Q(gpio_io_t[4]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[12]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[3]),
.Q(gpio_io_t[3]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[13]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[2]),
.Q(gpio_io_t[2]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[14]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[1]),
.Q(gpio_io_t[1]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[15]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[0]),
.Q(gpio_io_t[0]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[14]),
.Q(gpio_io_t[14]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[13]),
.Q(gpio_io_t[13]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[12]),
.Q(gpio_io_t[12]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[11]),
.Q(gpio_io_t[11]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[5]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[10]),
.Q(gpio_io_t[10]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[6]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[9]),
.Q(gpio_io_t[9]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[7]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[8]),
.Q(gpio_io_t[8]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[8]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[7]),
.Q(gpio_io_t[7]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[9]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[6]),
.Q(gpio_io_t[6]),
.S(bus2ip_reset));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(bus2ip_reset));
LUT3 #(
.INIT(8'h10))
iGPIO_xferAck_i_1
(.I0(gpio_xferAck_Reg),
.I1(GPIO_xferAck_i),
.I2(bus2ip_cs),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module system_axi_gpio_1_0_address_decoder
(\ip2bus_data_i_D1_reg[0] ,
\Not_Dual.gpio_Data_Out_reg[15] ,
\ip_irpt_enable_reg_reg[0] ,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0]_0 ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0]_0 ,
ipif_glbl_irpt_enable_reg_reg,
start2,
s_axi_aclk,
s_axi_aresetn,
Q,
is_read,
ip2bus_rdack_i_D1,
is_write_reg,
ip2bus_wrack_i_D1,
s_axi_wdata,
\bus2ip_addr_i_reg[8] ,
gpio_io_t,
\Not_Dual.gpio_Data_In_reg[0] ,
bus2ip_rnw_i_reg,
bus2ip_reset,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1);
output \ip2bus_data_i_D1_reg[0] ;
output \Not_Dual.gpio_Data_Out_reg[15] ;
output \ip_irpt_enable_reg_reg[0] ;
output s_axi_arready;
output s_axi_wready;
output [15:0]D;
output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ;
output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ;
output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ;
output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ;
output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ;
output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ;
output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ;
output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ;
output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ;
output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ;
output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ;
output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ;
output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ;
output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ;
output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0]_0 ;
output ipif_glbl_irpt_enable_reg_reg;
input start2;
input s_axi_aclk;
input s_axi_aresetn;
input [3:0]Q;
input is_read;
input ip2bus_rdack_i_D1;
input is_write_reg;
input ip2bus_wrack_i_D1;
input [31:0]s_axi_wdata;
input [6:0]\bus2ip_addr_i_reg[8] ;
input [15:0]gpio_io_t;
input [15:0]\Not_Dual.gpio_Data_In_reg[0] ;
input bus2ip_rnw_i_reg;
input bus2ip_reset;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
wire Bus_RNW_reg_i_1_n_0;
wire [15:0]D;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ;
wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ;
wire \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ;
wire \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ;
wire \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ;
wire \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ;
wire \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ;
wire \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ;
wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ;
wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ;
wire [15:0]\Not_Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_Data_Out_reg[15] ;
wire [3:0]Q;
wire Read_Reg_Rst;
wire [6:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_reset;
wire bus2ip_rnw_i_reg;
wire [15:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire \ip2bus_data_i_D1_reg[0] ;
wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire \ip_irpt_enable_reg_reg[0]_0 ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_write_reg;
wire [0:0]p_0_in;
wire p_10_in;
wire p_10_out;
wire p_11_in;
wire p_11_out;
wire p_12_in;
wire p_12_out;
wire p_13_in;
wire p_13_out;
wire p_14_in;
wire p_14_out;
wire p_15_in;
wire p_15_out;
wire p_16_in;
wire [0:0]p_1_in;
wire p_2_in;
wire [0:0]p_3_in;
wire p_3_in_0;
wire p_4_in;
wire p_4_out;
wire p_5_in;
wire p_5_out;
wire p_6_in;
wire p_6_out;
wire p_7_in;
wire p_7_out;
wire p_8_out;
wire p_9_in;
wire p_9_out;
wire pselect_hit_i_1;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire start2;
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(start2),
.I2(\ip_irpt_enable_reg_reg[0] ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\ip_irpt_enable_reg_reg[0] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0040000000000000))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_9_out));
FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
(.C(s_axi_aclk),
.CE(start2),
.D(p_9_out),
.Q(p_10_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h4000000000000000))
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_8_out));
FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]
(.C(s_axi_aclk),
.CE(start2),
.D(p_8_out),
.Q(p_9_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_7_out));
FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]
(.C(s_axi_aclk),
.CE(start2),
.D(p_7_out),
.Q(\ip2bus_data_i_D1_reg[0] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_6_out));
FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]
(.C(s_axi_aclk),
.CE(start2),
.D(p_6_out),
.Q(p_7_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000000000000))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_5_out));
FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]
(.C(s_axi_aclk),
.CE(start2),
.D(p_5_out),
.Q(p_6_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800000000000000))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_4_out));
FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]
(.C(s_axi_aclk),
.CE(start2),
.D(p_4_out),
.Q(p_5_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000000000000))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ),
.Q(p_4_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800000000000000))
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ),
.Q(p_3_in_0),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0080000000000000))
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ),
.Q(p_2_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT3 #(
.INIT(8'hFD))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1
(.I0(s_axi_aresetn),
.I1(s_axi_arready),
.I2(s_axi_wready),
.O(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_15_out));
FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]
(.C(s_axi_aclk),
.CE(start2),
.D(p_15_out),
.Q(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0001000000000000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
.Q(p_16_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0100000000000000))
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_14_out));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi_aclk),
.CE(start2),
.D(p_14_out),
.Q(p_15_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0002000000000000))
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_13_out));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi_aclk),
.CE(start2),
.D(p_13_out),
.Q(p_14_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0200000000000000))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_12_out));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(start2),
.D(p_12_out),
.Q(p_13_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_11_out));
FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
(.C(s_axi_aclk),
.CE(start2),
.D(p_11_out),
.Q(p_12_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_10_out));
FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]
(.C(s_axi_aclk),
.CE(start2),
.D(p_10_out),
.Q(p_11_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hFE00))
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(intr_rd_ce_or_reduce));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00FE0000))
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(ip2Bus_RdAck_intr_reg_hole_d1),
.I4(\ip_irpt_enable_reg_reg[0] ),
.O(\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h00FE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(intr_wr_ce_or_reduce));
LUT5 #(
.INIT(32'hFFFFFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2
(.I0(p_16_in),
.I1(p_2_in),
.I2(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
.I3(p_14_in),
.I4(p_15_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3
(.I0(p_12_in),
.I1(p_13_in),
.I2(p_10_in),
.I3(p_11_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4
(.I0(p_5_in),
.I1(p_7_in),
.I2(p_3_in_0),
.I3(p_4_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h000000FE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.I4(ip2Bus_WrAck_intr_reg_hole_d1),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ));
LUT6 #(
.INIT(64'h0000000000000002))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(start2),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [4]),
.I3(\bus2ip_addr_i_reg[8] [5]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.I5(\bus2ip_addr_i_reg[8] [2]),
.O(pselect_hit_i_1));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(start2),
.D(pselect_hit_i_1),
.Q(\Not_Dual.gpio_Data_Out_reg[15] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[0].GPIO_DBus_i[16]_i_1
(.I0(gpio_io_t[15]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [15]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(GPIO_DBus_i));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i[26]_i_1
(.I0(gpio_io_t[5]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [5]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i[27]_i_1
(.I0(gpio_io_t[4]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [4]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i[28]_i_1
(.I0(gpio_io_t[3]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i[29]_i_1
(.I0(gpio_io_t[2]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i[30]_i_1
(.I0(gpio_io_t[1]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ));
LUT4 #(
.INIT(16'hFFDF))
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_1
(.I0(\Not_Dual.gpio_Data_Out_reg[15] ),
.I1(GPIO_xferAck_i),
.I2(bus2ip_rnw_i_reg),
.I3(gpio_xferAck_Reg),
.O(Read_Reg_Rst));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i[31]_i_2
(.I0(gpio_io_t[0]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i[17]_i_1
(.I0(gpio_io_t[14]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [14]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i[18]_i_1
(.I0(gpio_io_t[13]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [13]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i[19]_i_1
(.I0(gpio_io_t[12]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [12]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i[20]_i_1
(.I0(gpio_io_t[11]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [11]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i[21]_i_1
(.I0(gpio_io_t[10]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [10]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i[22]_i_1
(.I0(gpio_io_t[9]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [9]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i[23]_i_1
(.I0(gpio_io_t[8]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [8]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i[24]_i_1
(.I0(gpio_io_t[7]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [7]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i[25]_i_1
(.I0(gpio_io_t[6]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [6]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[15] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ));
LUT6 #(
.INIT(64'hFFFFFFFF00000100))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\Not_Dual.gpio_Data_Out_reg[15] ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(bus2ip_reset),
.O(\Not_Dual.gpio_Data_Out_reg[0] ));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[31]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[15]),
.O(D[15]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[10]_i_1
(.I0(s_axi_wdata[21]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[5]),
.O(D[5]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[11]_i_1
(.I0(s_axi_wdata[20]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[4]),
.O(D[4]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[12]_i_1
(.I0(s_axi_wdata[19]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[3]),
.O(D[3]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[13]_i_1
(.I0(s_axi_wdata[18]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[2]),
.O(D[2]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[14]_i_1
(.I0(s_axi_wdata[17]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[1]),
.O(D[1]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[15]_i_1
(.I0(s_axi_wdata[16]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[0]),
.O(D[0]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[30]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[14]),
.O(D[14]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[29]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[13]),
.O(D[13]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[28]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[12]),
.O(D[12]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[27]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[11]),
.O(D[11]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[5]_i_1
(.I0(s_axi_wdata[26]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[10]),
.O(D[10]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[6]_i_1
(.I0(s_axi_wdata[25]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[9]),
.O(D[9]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[7]_i_1
(.I0(s_axi_wdata[24]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[8]),
.O(D[8]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[8]_i_1
(.I0(s_axi_wdata[23]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[7]),
.O(D[7]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[9]_i_1
(.I0(s_axi_wdata[22]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[15] ),
.I3(s_axi_wdata[6]),
.O(D[6]));
LUT6 #(
.INIT(64'hFFFFFFFF01000000))
\Not_Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\Not_Dual.gpio_Data_Out_reg[15] ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(bus2ip_reset),
.O(E));
LUT5 #(
.INIT(32'h44444440))
intr2bus_rdack_i_1
(.I0(irpt_rdack_d1),
.I1(\ip_irpt_enable_reg_reg[0] ),
.I2(p_9_in),
.I3(\ip2bus_data_i_D1_reg[0] ),
.I4(p_6_in),
.O(intr2bus_rdack0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h000000FE))
intr2bus_wrack_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.I4(irpt_wrack_d1),
.O(interrupt_wrce_strb));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00000080))
\ip2bus_data_i_D1[0]_i_1
(.I0(p_0_in),
.I1(p_9_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_6_in),
.I4(\ip2bus_data_i_D1_reg[0] ),
.O(\ip2bus_data_i_D1_reg[0]_0 [1]));
LUT6 #(
.INIT(64'hEEEEAAAAFAAAAAAA))
\ip2bus_data_i_D1[31]_i_1
(.I0(ip2bus_data),
.I1(p_3_in),
.I2(p_1_in),
.I3(p_6_in),
.I4(\ip_irpt_enable_reg_reg[0] ),
.I5(\ip2bus_data_i_D1_reg[0] ),
.O(\ip2bus_data_i_D1_reg[0]_0 [0]));
LUT4 #(
.INIT(16'hFB08))
\ip_irpt_enable_reg[0]_i_1
(.I0(s_axi_wdata[0]),
.I1(p_6_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_1_in),
.O(\ip_irpt_enable_reg_reg[0]_0 ));
LUT4 #(
.INIT(16'hFB08))
ipif_glbl_irpt_enable_reg_i_1
(.I0(s_axi_wdata[31]),
.I1(p_9_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_0_in),
.O(ipif_glbl_irpt_enable_reg_reg));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFE00))
irpt_rdack_d1_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(irpt_rdack));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h00FE))
irpt_wrack_d1_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(irpt_wrack));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_arready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_read),
.I5(ip2bus_rdack_i_D1),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_wready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_write_reg),
.I5(ip2bus_wrack_i_D1),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "0" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "artix7" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "16" *)
(* C_INTERRUPT_PRESENT = "1" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module system_axi_gpio_1_0_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [15:0]gpio_io_i;
output [15:0]gpio_io_o;
output [15:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_24;
wire AXI_LITE_IPIF_I_n_25;
wire AXI_LITE_IPIF_I_n_26;
wire AXI_LITE_IPIF_I_n_27;
wire AXI_LITE_IPIF_I_n_28;
wire AXI_LITE_IPIF_I_n_29;
wire AXI_LITE_IPIF_I_n_30;
wire AXI_LITE_IPIF_I_n_31;
wire AXI_LITE_IPIF_I_n_32;
wire AXI_LITE_IPIF_I_n_33;
wire AXI_LITE_IPIF_I_n_34;
wire AXI_LITE_IPIF_I_n_35;
wire AXI_LITE_IPIF_I_n_36;
wire AXI_LITE_IPIF_I_n_37;
wire AXI_LITE_IPIF_I_n_38;
wire AXI_LITE_IPIF_I_n_40;
wire AXI_LITE_IPIF_I_n_41;
wire AXI_LITE_IPIF_I_n_49;
wire AXI_LITE_IPIF_I_n_51;
wire AXI_LITE_IPIF_I_n_53;
wire AXI_LITE_IPIF_I_n_54;
wire [0:15]DBus_Reg;
wire [16:16]GPIO_DBus_i;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire IP2INTC_Irpt_i;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ;
wire Read_Reg_Rst;
wire [1:1]bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_reset_i_1_n_0;
wire bus2ip_rnw;
wire [0:15]gpio_Data_In;
wire [15:0]gpio_io_i;
wire [15:0]gpio_io_o;
wire [15:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [16:31]ip2bus_data;
wire [31:31]ip2bus_data_i;
wire [0:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i;
wire ip2bus_wrack_i_D1;
wire ip2intc_irpt;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [31:31]p_0_in;
wire [0:0]p_0_out;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [31];
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15:0] = \^s_axi_rdata [15:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
system_axi_gpio_1_0_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13],DBus_Reg[14],DBus_Reg[15]}),
.E(AXI_LITE_IPIF_I_n_40),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_49),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_51),
.\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] (AXI_LITE_IPIF_I_n_29),
.\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] (AXI_LITE_IPIF_I_n_28),
.\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_27),
.\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_26),
.\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_25),
.\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_24),
.\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] (AXI_LITE_IPIF_I_n_38),
.\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] (AXI_LITE_IPIF_I_n_37),
.\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] (AXI_LITE_IPIF_I_n_36),
.\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] (AXI_LITE_IPIF_I_n_35),
.\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] (AXI_LITE_IPIF_I_n_34),
.\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] (AXI_LITE_IPIF_I_n_33),
.\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] (AXI_LITE_IPIF_I_n_32),
.\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] (AXI_LITE_IPIF_I_n_31),
.\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] (AXI_LITE_IPIF_I_n_30),
.\Not_Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_41),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7],gpio_Data_In[8],gpio_Data_In[9],gpio_Data_In[10],gpio_Data_In[11],gpio_Data_In[12],gpio_Data_In[13],gpio_Data_In[14],gpio_Data_In[15]}),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data[31]),
.\ip2bus_data_i_D1_reg[0] ({p_0_out,ip2bus_data_i}),
.\ip2bus_data_i_D1_reg[0]_0 ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[16],ip2bus_data_i_D1[17],ip2bus_data_i_D1[18],ip2bus_data_i_D1[19],ip2bus_data_i_D1[20],ip2bus_data_i_D1[21],ip2bus_data_i_D1[22],ip2bus_data_i_D1[23],ip2bus_data_i_D1[24],ip2bus_data_i_D1[25],ip2bus_data_i_D1[26],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (AXI_LITE_IPIF_I_n_53),
.ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_54),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[8:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[8:2]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [31],\^s_axi_rdata [15:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
system_axi_gpio_1_0_interrupt_control \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] (AXI_LITE_IPIF_I_n_54),
.\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] (AXI_LITE_IPIF_I_n_53),
.GPIO_intr(GPIO_intr),
.GPIO_xferAck_i(GPIO_xferAck_i),
.IP2INTC_Irpt_i(IP2INTC_Irpt_i),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole),
.ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i(ip2bus_wrack_i),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[0]));
FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_rd_ce_or_reduce),
.Q(ip2Bus_RdAck_intr_reg_hole_d1),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_49),
.Q(ip2Bus_RdAck_intr_reg_hole),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_wr_ce_or_reduce),
.Q(ip2Bus_WrAck_intr_reg_hole_d1),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_51),
.Q(ip2Bus_WrAck_intr_reg_hole),
.R(bus2ip_reset));
(* sigis = "INTR_LEVEL_HIGH" *)
FDRE \INTR_CTRLR_GEN.ip2intc_irpt_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(IP2INTC_Irpt_i),
.Q(ip2intc_irpt),
.R(bus2ip_reset));
VCC VCC
(.P(\<const1> ));
LUT1 #(
.INIT(2'h1))
bus2ip_reset_i_1
(.I0(s_axi_aresetn),
.O(bus2ip_reset_i_1_n_0));
FDRE bus2ip_reset_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus2ip_reset_i_1_n_0),
.Q(bus2ip_reset),
.R(1'b0));
system_axi_gpio_1_0_GPIO_Core gpio_core_1
(.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4],DBus_Reg[5],DBus_Reg[6],DBus_Reg[7],DBus_Reg[8],DBus_Reg[9],DBus_Reg[10],DBus_Reg[11],DBus_Reg[12],DBus_Reg[13],DBus_Reg[14],DBus_Reg[15]}),
.E(AXI_LITE_IPIF_I_n_41),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_intr(GPIO_intr),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.gpio_OE_reg[10]_0 (AXI_LITE_IPIF_I_n_29),
.\Not_Dual.gpio_OE_reg[11]_0 (AXI_LITE_IPIF_I_n_28),
.\Not_Dual.gpio_OE_reg[12]_0 (AXI_LITE_IPIF_I_n_27),
.\Not_Dual.gpio_OE_reg[13]_0 (AXI_LITE_IPIF_I_n_26),
.\Not_Dual.gpio_OE_reg[14]_0 (AXI_LITE_IPIF_I_n_25),
.\Not_Dual.gpio_OE_reg[15]_0 (AXI_LITE_IPIF_I_n_24),
.\Not_Dual.gpio_OE_reg[1]_0 (AXI_LITE_IPIF_I_n_38),
.\Not_Dual.gpio_OE_reg[2]_0 (AXI_LITE_IPIF_I_n_37),
.\Not_Dual.gpio_OE_reg[3]_0 (AXI_LITE_IPIF_I_n_36),
.\Not_Dual.gpio_OE_reg[4]_0 (AXI_LITE_IPIF_I_n_35),
.\Not_Dual.gpio_OE_reg[5]_0 (AXI_LITE_IPIF_I_n_34),
.\Not_Dual.gpio_OE_reg[6]_0 (AXI_LITE_IPIF_I_n_33),
.\Not_Dual.gpio_OE_reg[7]_0 (AXI_LITE_IPIF_I_n_32),
.\Not_Dual.gpio_OE_reg[8]_0 (AXI_LITE_IPIF_I_n_31),
.\Not_Dual.gpio_OE_reg[9]_0 (AXI_LITE_IPIF_I_n_30),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4],gpio_Data_In[5],gpio_Data_In[6],gpio_Data_In[7],gpio_Data_In[8],gpio_Data_In[9],gpio_Data_In[10],gpio_Data_In[11],gpio_Data_In[12],gpio_Data_In[13],gpio_Data_In[14],gpio_Data_In[15]}),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_40),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_data({ip2bus_data[16],ip2bus_data[17],ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[16]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[16]),
.Q(ip2bus_data_i_D1[16]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[17]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[17]),
.Q(ip2bus_data_i_D1[17]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[18]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[18]),
.Q(ip2bus_data_i_D1[18]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[19]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[19]),
.Q(ip2bus_data_i_D1[19]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[20]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[20]),
.Q(ip2bus_data_i_D1[20]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[21]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[21]),
.Q(ip2bus_data_i_D1[21]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[22]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[22]),
.Q(ip2bus_data_i_D1[22]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[23]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[23]),
.Q(ip2bus_data_i_D1[23]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[24]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[24]),
.Q(ip2bus_data_i_D1[24]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[25]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[25]),
.Q(ip2bus_data_i_D1[25]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[26]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[26]),
.Q(ip2bus_data_i_D1[26]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data_i),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_wrack_i),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module system_axi_gpio_1_0_axi_lite_ipif
(p_8_in,
bus2ip_rnw,
bus2ip_cs,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0] ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0] ,
ipif_glbl_irpt_enable_reg_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
gpio_io_t,
Q,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]_0 );
output p_8_in;
output bus2ip_rnw;
output [0:0]bus2ip_cs;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [15:0]D;
output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ;
output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ;
output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ;
output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ;
output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ;
output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ;
output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ;
output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ;
output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ;
output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ;
output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ;
output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ;
output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ;
output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ;
output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0] ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0] ;
output ipif_glbl_irpt_enable_reg_reg;
output [16:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [6:0]s_axi_awaddr;
input [6:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [31:0]s_axi_wdata;
input [15:0]gpio_io_t;
input [15:0]Q;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input [16:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire Bus_RNW_reg;
wire [15:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ;
wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ;
wire \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ;
wire \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ;
wire \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ;
wire \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ;
wire \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ;
wire \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ;
wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ;
wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire [15:0]Q;
wire Read_Reg_Rst;
wire [0:0]bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [15:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire [1:0]\ip2bus_data_i_D1_reg[0] ;
wire [16:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
wire p_8_in;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [16:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
system_axi_gpio_1_0_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
.\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ),
.\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ),
.\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ),
.\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] (\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ),
.\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] (\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ),
.\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] (\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ),
.\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] (\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ),
.\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] (\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ),
.\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] (\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ),
.\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] (\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ),
.\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] (\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ),
.\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] (\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ),
.\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] (\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ),
.\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] (\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ),
.\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] (\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_Data_Out_reg[15] (bus2ip_cs),
.\Not_Dual.gpio_OE_reg[0] (bus2ip_rnw),
.Q(Q),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_reset(bus2ip_reset),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data),
.\ip2bus_data_i_D1_reg[0] (p_8_in),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_1 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (Bus_RNW_reg),
.\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0] ),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module system_axi_gpio_1_0_cdc_sync
(D,
scndry_vect_out,
Q,
gpio_io_i,
s_axi_aclk);
output [15:0]D;
output [15:0]scndry_vect_out;
input [15:0]Q;
input [15:0]gpio_io_i;
input s_axi_aclk;
wire [15:0]D;
wire [15:0]Q;
wire [15:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_10;
wire s_level_out_bus_d1_cdc_to_11;
wire s_level_out_bus_d1_cdc_to_12;
wire s_level_out_bus_d1_cdc_to_13;
wire s_level_out_bus_d1_cdc_to_14;
wire s_level_out_bus_d1_cdc_to_15;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d1_cdc_to_5;
wire s_level_out_bus_d1_cdc_to_6;
wire s_level_out_bus_d1_cdc_to_7;
wire s_level_out_bus_d1_cdc_to_8;
wire s_level_out_bus_d1_cdc_to_9;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_10;
wire s_level_out_bus_d2_11;
wire s_level_out_bus_d2_12;
wire s_level_out_bus_d2_13;
wire s_level_out_bus_d2_14;
wire s_level_out_bus_d2_15;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d2_5;
wire s_level_out_bus_d2_6;
wire s_level_out_bus_d2_7;
wire s_level_out_bus_d2_8;
wire s_level_out_bus_d2_9;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_10;
wire s_level_out_bus_d3_11;
wire s_level_out_bus_d3_12;
wire s_level_out_bus_d3_13;
wire s_level_out_bus_d3_14;
wire s_level_out_bus_d3_15;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire s_level_out_bus_d3_5;
wire s_level_out_bus_d3_6;
wire s_level_out_bus_d3_7;
wire s_level_out_bus_d3_8;
wire s_level_out_bus_d3_9;
wire [15:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_10),
.Q(s_level_out_bus_d2_10),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_11),
.Q(s_level_out_bus_d2_11),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_12),
.Q(s_level_out_bus_d2_12),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_13),
.Q(s_level_out_bus_d2_13),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_14),
.Q(s_level_out_bus_d2_14),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_15),
.Q(s_level_out_bus_d2_15),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_5),
.Q(s_level_out_bus_d2_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_6),
.Q(s_level_out_bus_d2_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_7),
.Q(s_level_out_bus_d2_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_8),
.Q(s_level_out_bus_d2_8),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_9),
.Q(s_level_out_bus_d2_9),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_10),
.Q(s_level_out_bus_d3_10),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_11),
.Q(s_level_out_bus_d3_11),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_12),
.Q(s_level_out_bus_d3_12),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_13),
.Q(s_level_out_bus_d3_13),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_14),
.Q(s_level_out_bus_d3_14),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_15),
.Q(s_level_out_bus_d3_15),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_5),
.Q(s_level_out_bus_d3_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_6),
.Q(s_level_out_bus_d3_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_7),
.Q(s_level_out_bus_d3_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_8),
.Q(s_level_out_bus_d3_8),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_9),
.Q(s_level_out_bus_d3_9),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_10),
.Q(scndry_vect_out[10]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_11),
.Q(scndry_vect_out[11]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[12].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_12),
.Q(scndry_vect_out[12]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[13].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_13),
.Q(scndry_vect_out[13]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[14].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_14),
.Q(scndry_vect_out[14]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[15].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_15),
.Q(scndry_vect_out[15]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_5),
.Q(scndry_vect_out[5]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_6),
.Q(scndry_vect_out[6]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_7),
.Q(scndry_vect_out[7]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_8),
.Q(scndry_vect_out[8]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_9),
.Q(scndry_vect_out[9]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[10]),
.Q(s_level_out_bus_d1_cdc_to_10),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[11]),
.Q(s_level_out_bus_d1_cdc_to_11),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[12].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[12]),
.Q(s_level_out_bus_d1_cdc_to_12),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[13].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[13]),
.Q(s_level_out_bus_d1_cdc_to_13),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[14].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[14]),
.Q(s_level_out_bus_d1_cdc_to_14),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[15].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[15]),
.Q(s_level_out_bus_d1_cdc_to_15),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[5]),
.Q(s_level_out_bus_d1_cdc_to_5),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[6]),
.Q(s_level_out_bus_d1_cdc_to_6),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[7]),
.Q(s_level_out_bus_d1_cdc_to_7),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[8]),
.Q(s_level_out_bus_d1_cdc_to_8),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[9]),
.Q(s_level_out_bus_d1_cdc_to_9),
.R(1'b0));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1
(.I0(Q[15]),
.I1(scndry_vect_out[15]),
.O(D[15]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[10]_i_1
(.I0(Q[5]),
.I1(scndry_vect_out[5]),
.O(D[5]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[11]_i_1
(.I0(Q[4]),
.I1(scndry_vect_out[4]),
.O(D[4]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[12]_i_1
(.I0(Q[3]),
.I1(scndry_vect_out[3]),
.O(D[3]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[13]_i_1
(.I0(Q[2]),
.I1(scndry_vect_out[2]),
.O(D[2]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[14]_i_1
(.I0(Q[1]),
.I1(scndry_vect_out[1]),
.O(D[1]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[15]_i_1
(.I0(Q[0]),
.I1(scndry_vect_out[0]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1
(.I0(Q[14]),
.I1(scndry_vect_out[14]),
.O(D[14]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1
(.I0(Q[13]),
.I1(scndry_vect_out[13]),
.O(D[13]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1
(.I0(Q[12]),
.I1(scndry_vect_out[12]),
.O(D[12]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1
(.I0(Q[11]),
.I1(scndry_vect_out[11]),
.O(D[11]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[5]_i_1
(.I0(Q[10]),
.I1(scndry_vect_out[10]),
.O(D[10]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[6]_i_1
(.I0(Q[9]),
.I1(scndry_vect_out[9]),
.O(D[9]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[7]_i_1
(.I0(Q[8]),
.I1(scndry_vect_out[8]),
.O(D[8]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[8]_i_1
(.I0(Q[7]),
.I1(scndry_vect_out[7]),
.O(D[7]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[9]_i_1
(.I0(Q[6]),
.I1(scndry_vect_out[6]),
.O(D[6]));
endmodule
(* ORIG_REF_NAME = "interrupt_control" *)
module system_axi_gpio_1_0_interrupt_control
(irpt_wrack_d1,
p_3_in,
irpt_rdack_d1,
p_1_in,
p_0_in,
IP2INTC_Irpt_i,
ip2bus_wrack_i,
ip2bus_rdack_i,
bus2ip_reset,
irpt_wrack,
s_axi_aclk,
GPIO_intr,
interrupt_wrce_strb,
irpt_rdack,
intr2bus_rdack0,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ,
p_8_in,
s_axi_wdata,
Bus_RNW_reg,
ip2Bus_WrAck_intr_reg_hole,
bus2ip_rnw,
GPIO_xferAck_i,
ip2Bus_RdAck_intr_reg_hole);
output irpt_wrack_d1;
output [0:0]p_3_in;
output irpt_rdack_d1;
output [0:0]p_1_in;
output [0:0]p_0_in;
output IP2INTC_Irpt_i;
output ip2bus_wrack_i;
output ip2bus_rdack_i;
input bus2ip_reset;
input irpt_wrack;
input s_axi_aclk;
input GPIO_intr;
input interrupt_wrce_strb;
input irpt_rdack;
input intr2bus_rdack0;
input \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
input \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
input p_8_in;
input [0:0]s_axi_wdata;
input Bus_RNW_reg;
input ip2Bus_WrAck_intr_reg_hole;
input bus2ip_rnw;
input GPIO_xferAck_i;
input ip2Bus_RdAck_intr_reg_hole;
wire Bus_RNW_reg;
wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
wire \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire IP2INTC_Irpt_i;
wire bus2ip_reset;
wire bus2ip_rnw;
wire interrupt_wrce_strb;
wire intr2bus_rdack;
wire intr2bus_rdack0;
wire intr2bus_wrack;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i;
wire irpt_dly1;
wire irpt_dly2;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
wire p_8_in;
wire s_axi_aclk;
wire [0:0]s_axi_wdata;
FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_intr),
.Q(irpt_dly1),
.S(bus2ip_reset));
FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_dly1),
.Q(irpt_dly2),
.S(bus2ip_reset));
LUT6 #(
.INIT(64'hF4F4F4F44FF4F4F4))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1
(.I0(irpt_dly2),
.I1(irpt_dly1),
.I2(p_3_in),
.I3(p_8_in),
.I4(s_axi_wdata),
.I5(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2
(.I0(irpt_wrack_d1),
.I1(Bus_RNW_reg),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ));
FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ),
.Q(p_3_in),
.R(bus2ip_reset));
LUT3 #(
.INIT(8'h80))
\INTR_CTRLR_GEN.ip2intc_irpt_i_1
(.I0(p_3_in),
.I1(p_1_in),
.I2(p_0_in),
.O(IP2INTC_Irpt_i));
FDRE intr2bus_rdack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr2bus_rdack0),
.Q(intr2bus_rdack),
.R(bus2ip_reset));
FDRE intr2bus_wrack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(interrupt_wrce_strb),
.Q(intr2bus_wrack),
.R(bus2ip_reset));
LUT4 #(
.INIT(16'hFEEE))
ip2bus_rdack_i_D1_i_1
(.I0(ip2Bus_RdAck_intr_reg_hole),
.I1(intr2bus_rdack),
.I2(bus2ip_rnw),
.I3(GPIO_xferAck_i),
.O(ip2bus_rdack_i));
LUT4 #(
.INIT(16'hEFEE))
ip2bus_wrack_i_D1_i_1
(.I0(ip2Bus_WrAck_intr_reg_hole),
.I1(intr2bus_wrack),
.I2(bus2ip_rnw),
.I3(GPIO_xferAck_i),
.O(ip2bus_wrack_i));
FDRE \ip_irpt_enable_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ),
.Q(p_1_in),
.R(bus2ip_reset));
FDRE ipif_glbl_irpt_enable_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ),
.Q(p_0_in),
.R(bus2ip_reset));
FDRE irpt_rdack_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_rdack),
.Q(irpt_rdack_d1),
.R(bus2ip_reset));
FDRE irpt_wrack_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_wrack),
.Q(irpt_wrack_d1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module system_axi_gpio_1_0_slave_attachment
(\ip2bus_data_i_D1_reg[0] ,
\Not_Dual.gpio_OE_reg[0] ,
\Not_Dual.gpio_Data_Out_reg[15] ,
\ip_irpt_enable_reg_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ,
\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ,
\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ,
\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ,
\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ,
\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ,
\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ,
\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ,
\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ,
\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ,
\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ,
\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ,
\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ,
\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ,
\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0]_0 ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0]_0 ,
ipif_glbl_irpt_enable_reg_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
gpio_io_t,
Q,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]_1 );
output \ip2bus_data_i_D1_reg[0] ;
output \Not_Dual.gpio_OE_reg[0] ;
output \Not_Dual.gpio_Data_Out_reg[15] ;
output \ip_irpt_enable_reg_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [15:0]D;
output \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ;
output \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ;
output \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ;
output \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ;
output \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ;
output \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ;
output \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ;
output \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ;
output \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ;
output \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ;
output \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ;
output \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ;
output \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ;
output \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ;
output \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0]_0 ;
output ipif_glbl_irpt_enable_reg_reg;
output [16:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [6:0]s_axi_awaddr;
input [6:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [31:0]s_axi_wdata;
input [15:0]gpio_io_t;
input [15:0]Q;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input [16:0]\ip2bus_data_i_D1_reg[0]_1 ;
wire [15:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ;
wire \Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ;
wire \Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ;
wire \Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ;
wire \Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ;
wire \Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ;
wire \Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ;
wire \Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ;
wire \Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ;
wire \Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ;
wire \Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ;
wire \Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_Data_Out_reg[15] ;
wire \Not_Dual.gpio_OE_reg[0] ;
wire [15:0]Q;
wire Read_Reg_Rst;
wire [0:6]bus2ip_addr;
wire bus2ip_reset;
wire bus2ip_rnw_i06_out;
wire clear;
wire [15:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire \ip2bus_data_i_D1_reg[0] ;
wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire [16:0]\ip2bus_data_i_D1_reg[0]_1 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire \ip_irpt_enable_reg_reg[0]_0 ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [0:0]p_0_in;
wire [1:0]p_0_out__0;
wire [0:0]p_1_in;
wire [8:2]p_1_in__0;
wire [0:0]p_3_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [16:0]s_axi_rdata;
wire s_axi_rdata_i;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
system_axi_gpio_1_0_address_decoder I_DECODER
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
.\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] (\Not_Dual.READ_REG_GEN[10].GPIO_DBus_i_reg[26] ),
.\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] (\Not_Dual.READ_REG_GEN[11].GPIO_DBus_i_reg[27] ),
.\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] (\Not_Dual.READ_REG_GEN[12].GPIO_DBus_i_reg[28] ),
.\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] (\Not_Dual.READ_REG_GEN[13].GPIO_DBus_i_reg[29] ),
.\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] (\Not_Dual.READ_REG_GEN[14].GPIO_DBus_i_reg[30] ),
.\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] (\Not_Dual.READ_REG_GEN[15].GPIO_DBus_i_reg[31] ),
.\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] (\Not_Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[17] ),
.\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] (\Not_Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[18] ),
.\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] (\Not_Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[19] ),
.\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] (\Not_Dual.READ_REG_GEN[4].GPIO_DBus_i_reg[20] ),
.\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] (\Not_Dual.READ_REG_GEN[5].GPIO_DBus_i_reg[21] ),
.\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] (\Not_Dual.READ_REG_GEN[6].GPIO_DBus_i_reg[22] ),
.\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] (\Not_Dual.READ_REG_GEN[7].GPIO_DBus_i_reg[23] ),
.\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] (\Not_Dual.READ_REG_GEN[8].GPIO_DBus_i_reg[24] ),
.\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] (\Not_Dual.READ_REG_GEN[9].GPIO_DBus_i_reg[25] ),
.\Not_Dual.gpio_Data_In_reg[0] (Q),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_Data_Out_reg[15] (\Not_Dual.gpio_Data_Out_reg[15] ),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.Read_Reg_Rst(Read_Reg_Rst),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2],bus2ip_addr[3],bus2ip_addr[4],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw_i_reg(\Not_Dual.gpio_OE_reg[0] ),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data),
.\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (\ip_irpt_enable_reg_reg[0] ),
.\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0]_0 ),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2(start2));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_awaddr[0]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[0]),
.O(p_1_in__0[2]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_awaddr[1]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[1]),
.O(p_1_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_awaddr[2]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[2]),
.O(p_1_in__0[4]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[5]_i_1
(.I0(s_axi_awaddr[3]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[3]),
.O(p_1_in__0[5]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[6]_i_1
(.I0(s_axi_awaddr[4]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[4]),
.O(p_1_in__0[6]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[7]_i_1
(.I0(s_axi_awaddr[5]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[5]),
.O(p_1_in__0[7]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_awaddr[6]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[6]),
.O(p_1_in__0[8]));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[2]),
.Q(bus2ip_addr[6]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[3]),
.Q(bus2ip_addr[5]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[4]),
.Q(bus2ip_addr[4]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[5]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[5]),
.Q(bus2ip_addr[3]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[6]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[6]),
.Q(bus2ip_addr[2]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[7]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[7]),
.Q(bus2ip_addr[1]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[8]),
.Q(bus2ip_addr[0]),
.R(bus2ip_reset));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(bus2ip_rnw_i06_out),
.Q(\Not_Dual.gpio_OE_reg[0] ),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\state[1]_i_2_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(bus2ip_reset));
LUT6 #(
.INIT(64'h1000FFFF10000000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(s_axi_wvalid),
.I3(s_axi_awvalid),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(state[1]),
.I5(state[0]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(bus2ip_reset));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [0]),
.Q(s_axi_rdata[0]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [10]),
.Q(s_axi_rdata[10]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [11]),
.Q(s_axi_rdata[11]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[12]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [12]),
.Q(s_axi_rdata[12]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[13]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [13]),
.Q(s_axi_rdata[13]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[14]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [14]),
.Q(s_axi_rdata[14]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[15]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [15]),
.Q(s_axi_rdata[15]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [1]),
.Q(s_axi_rdata[1]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [2]),
.Q(s_axi_rdata[2]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [16]),
.Q(s_axi_rdata[16]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [3]),
.Q(s_axi_rdata[3]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [4]),
.Q(s_axi_rdata[4]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [5]),
.Q(s_axi_rdata[5]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [6]),
.Q(s_axi_rdata[6]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [7]),
.Q(s_axi_rdata[7]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [8]),
.Q(s_axi_rdata[8]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [9]),
.Q(s_axi_rdata[9]),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h0FFFAACC))
\state[0]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arvalid),
.I2(\state[1]_i_2_n_0 ),
.I3(state[1]),
.I4(state[0]),
.O(p_0_out__0[0]));
LUT6 #(
.INIT(64'h2E2E2E2ECCCCFFCC))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(\state[1]_i_3_n_0 ),
.I4(s_axi_arvalid),
.I5(state[0]),
.O(p_0_out__0[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_3
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out__0[0]),
.Q(state[0]),
.R(bus2ip_reset));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out__0[1]),
.Q(state[1]),
.R(bus2ip_reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_BLACKBOX_V
`define SKY130_FD_SC_HVL__CONB_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__conb (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 27.11.2014 14:15:43
// Design Name:
// Module Name: red_pitaya_iq_fgen_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_iq_modulator_block #(
parameter INBITS = 18,
parameter OUTBITS = 14,
parameter SINBITS = 14,
parameter GAINBITS = 16,
parameter SHIFTBITS = 0)
(
input clk_i,
input signed [SINBITS-1:0] sin,
input signed [SINBITS-1:0] cos,
input signed [GAINBITS-1:0] g1,
input signed [GAINBITS-1:0] g2,
input signed [GAINBITS-1:0] g3,
input signed [GAINBITS-1:0] g4,
input signed [INBITS-1:0] signal1_i,
input signed [INBITS-1:0] signal2_i,
output signed [OUTBITS-1:0] dat_o,
output signed [OUTBITS-1:0] signal_q1_o, //the i-quadrature
output signed [OUTBITS-1:0] signal_q2_o //the q-quadrature
);
// firstproduct
wire signed [OUTBITS-1:0] firstproduct1;
wire signed [OUTBITS-1:0] firstproduct2;
red_pitaya_product_sat #(
.BITS_IN1(INBITS),
.BITS_IN2(GAINBITS),
.SHIFT(GAINBITS+INBITS-OUTBITS-SHIFTBITS),
.BITS_OUT(OUTBITS))
firstproduct_saturation [1:0]
( .factor1_i ( {signal2_i, signal1_i} ),
.factor2_i ( { g4, g1} ),
.product_o ( {firstproduct2, firstproduct1})
);
// buffering - one extra bit for the sum with g2
reg signed [OUTBITS+1-1:0] firstproduct1_reg;
reg signed [OUTBITS+1-1:0] firstproduct2_reg;
always @(posedge clk_i) begin
firstproduct1_reg <= $signed(firstproduct1) + $signed(g2[GAINBITS-1:GAINBITS-OUTBITS]);
firstproduct2_reg <= $signed(firstproduct2);
end
wire signed [OUTBITS+1+SINBITS-1-1:0] secondproduct1;
wire signed [OUTBITS+1+SINBITS-1-1:0] secondproduct2;
assign secondproduct1 = firstproduct1_reg * sin;
assign secondproduct2 = firstproduct2_reg * cos;
//sum of second product has an extra bit
reg signed [OUTBITS+1+SINBITS-1:0] secondproduct_sum;
reg signed [OUTBITS-1:0] secondproduct_out;
wire signed [OUTBITS-1:0] secondproduct_sat;
//summation and saturation management, and buffering
always @(posedge clk_i) begin
secondproduct_sum <= secondproduct1 + secondproduct2;
secondproduct_out <= secondproduct_sat;
end
// SHIFT to compensate: sin multiplication (2**SINBITS-1 is the largest number)
red_pitaya_saturate
#( .BITS_IN(OUTBITS+SINBITS+1),
.BITS_OUT(OUTBITS),
.SHIFT(SINBITS-1)
)
sumsaturation
(
.input_i(secondproduct_sum),
.output_o(secondproduct_sat)
);
assign dat_o = secondproduct_out;
//output the scaled quadrature
wire signed [OUTBITS-1:0] q1_product;
wire signed [OUTBITS-1:0] q2_product;
//output first quadrature to scope etc.
red_pitaya_product_sat #(
.BITS_IN1(INBITS),
.BITS_IN2(GAINBITS),
.SHIFT(SHIFTBITS+2),
.BITS_OUT(OUTBITS))
i0_product_and_sat (
.factor1_i(signal1_i),
.factor2_i(g3),
.product_o(q1_product),
.overflow ()
);
// output second quadrature to scope etc.
red_pitaya_product_sat #(
.BITS_IN1(INBITS),
.BITS_IN2(GAINBITS),
.SHIFT(SHIFTBITS+2),
.BITS_OUT(OUTBITS))
q0_product_and_sat (
.factor1_i(signal2_i),
.factor2_i(g3),
.product_o(q2_product),
.overflow ()
);
// pipeline products
reg signed [OUTBITS-1:0] q1_product_reg;
reg signed [OUTBITS-1:0] q2_product_reg;
always @(posedge clk_i) begin
q1_product_reg <= q1_product;
q2_product_reg <= q2_product;
end
assign signal_q1_o = q1_product_reg;
assign signal_q2_o = q2_product_reg;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Application : MIG
// \ \ Filename : traffic_gen_top.v
// / / Date Last Modified : $Date: 2011/05/27 14:31:13 $
// /___/ /\ Date Created : Fri Mar 26 2010
// \ \ / \
// \___\/\___\
//
//Device : Virtex-7
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : This Traffic Gen supports both nCK_PER_CLK x4 mode and nCK_PER_CLK x2 mode for
// 7series MC UI Interface. The user bus datawidth has a equation: 2*nCK_PER_CLK*DQ_WIDTH.
//
//Reference :
//Revision History : 11/17 Adding CMD_GAP_DELAY to allow control of next command generation after current
// completion of burst command in user interface port.
//*****************************************************************************
`timescale 1ps/1ps
module traffic_gen_top #(
parameter TCQ = 100, // SIMULATION tCQ delay.
parameter SIMULATION = "FALSE",
parameter FAMILY = "VIRTEX7", // "VIRTEX6", "VIRTEX7"
parameter MEM_TYPE = "DDR3",
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands:
// "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE"
// "R_W_INSTR_MODE", "RP_WP_INSTR_MODE
// "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE"
// *******************************
// Virtex 6 Available commands:
// "R_W_INSTR_MODE"
// "FIXED_INSTR_R_MODE" - Only Read commands will be generated.
// "FIXED_INSTR_W_MODE" -- Only Write commands will be generated.
// "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated
// with lower 10 bits address in sequential increment.
// This mode is for Read Eye measurement.
parameter BL_WIDTH = 10, // Define User Interface Burst length width.
// For a maximum 128 continuous back_to_back command, set this to 8.
parameter nCK_PER_CLK = 4, // Memory Clock ratio to fabric clock.
parameter NUM_DQ_PINS = 8, // Total number of memory dq pins in the design.
parameter MEM_BURST_LEN = 8, // MEMROY Burst Length
parameter MEM_COL_WIDTH = 10, // Memory component column width.
parameter PORT_MODE = "BI_MODE",
parameter DATA_PATTERN = "DGEN_ALL", // Default is to generate all data pattern circuits.
parameter CMD_PATTERN = "CGEN_ALL", // Default is to generate all commands pattern circuits.
parameter DATA_WIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, // User Interface Data Width
parameter ADDR_WIDTH = 32, // Command Address Bus width
parameter MASK_SIZE = DATA_WIDTH/8, //
parameter DATA_MODE = 4'b0010, // Default Data mode is set to Address as Data pattern.
// parameters define the address range
parameter BEGIN_ADDRESS = 32'h00000100,
parameter END_ADDRESS = 32'h000002ff,
parameter PRBS_EADDR_MASK_POS = 32'hfffffc00,
// debug parameters
parameter CMDS_GAP_DELAY = 6'd0, // CMDS_GAP_DELAY is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles
// after the last command.
parameter SEL_VICTIM_LINE = NUM_DQ_PINS, // VICTIM LINE is one of the DQ pins is selected to be always asserted when
// DATA MODE is hammer pattern. No VICTIM_LINE will be selected if
// SEL_VICTIM_LINE = NUM_DQ_PINS.
parameter EYE_TEST = "FALSE"
)
(
input clk,
input rst,
input manual_clear_error,
input memc_init_done,
input memc_cmd_full,
output memc_cmd_en,
output [2:0] memc_cmd_instr,
output [5:0] memc_cmd_bl,
output [31:0] memc_cmd_addr,
output memc_wr_en,
output memc_wr_end,
output [DATA_WIDTH/8 - 1:0] memc_wr_mask,
output [DATA_WIDTH - 1:0] memc_wr_data,
input memc_wr_full,
output memc_rd_en,
input [DATA_WIDTH - 1:0] memc_rd_data,
input memc_rd_empty,
// interface to qdr interface
output qdr_wr_cmd_o,
output qdr_rd_cmd_o,
// Signal declarations that can be connected to vio module
input vio_modify_enable,
input [3:0] vio_data_mode_value,
input [2:0] vio_addr_mode_value,
input [3:0] vio_instr_mode_value,
input [1:0] vio_bl_mode_value,
input [BL_WIDTH - 1:0] vio_fixed_bl_value,
input vio_data_mask_gen, // data_mask generation is only supported
// when data mode = address as data .
input [31:0] fixed_addr_i,
// User Specific data pattern interface that used when vio_data_mode vale = 1.4.9.
input [31:0] fixed_data_i,
input [31:0] simple_data0,
input [31:0] simple_data1,
input [31:0] simple_data2,
input [31:0] simple_data3,
input [31:0] simple_data4,
input [31:0] simple_data5,
input [31:0] simple_data6,
input [31:0] simple_data7,
// BRAM interface.
// bram bus formats:
// Only SP6 has been tested.
input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}}
input bram_valid_i,
output bram_rdy_o, //
// status feedback
output [DATA_WIDTH-1:0] cmp_data,
output cmp_data_valid,
output cmp_error,
output error, // asserted whenever the read back data is not correct.
output [64 + (2*DATA_WIDTH - 1):0] error_status
);
//p0 wire declarations
wire tg_run_traffic;
wire [31:0] tg_start_addr;
wire [31:0] tg_end_addr;
wire [31:0] tg_cmd_seed;
wire [31:0] tg_data_seed;
wire tg_load_seed;
wire [2:0] tg_addr_mode;
wire [3:0] tg_instr_mode;
wire [1:0] tg_bl_mode;
wire [3:0] tg_data_mode;
wire tg_mode_load;
wire [BL_WIDTH-1:0] tg_fixed_bl;
wire [2:0] tg_fixed_instr;
wire tg_addr_order;
wire [5:0] cmds_gap_delay_value;
wire tg_memc_wr_en;
wire mem_pattern_init_done;
// reg memc_init_done;
// assign tg_fixed_bl = 64;//{1'b1, {BL_WIDTH-1{1'b0}}} ;//* BURST_LENGTH;
// when in PRBS mode:
// assign tg_fixed_bl = 64;//{1'b1, {BL_WIDTH-1{1'b0}}} ;//* BURST_LENGTH;
// cmds_gap_delay_value is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles after the last command.
assign cmds_gap_delay_value = CMDS_GAP_DELAY;
localparam TG_FAMILY = ((FAMILY == "VIRTEX6") || (FAMILY == "VIRTEX7") || (FAMILY == "7SERIES")
|| (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ) ? "VIRTEX6" : "SPARTAN6";
assign tg_memc_wr_en = (TG_FAMILY == "VIRTEX6") ?memc_cmd_en & ~memc_cmd_full : memc_wr_en ;
// The following 'generate' statement activates the traffic generator for
// init_mem_pattern_ctr module instantiation for Port-0
init_mem_pattern_ctr #
(
.TCQ (TCQ),
.DWIDTH (DATA_WIDTH),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
// .nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_TYPE (MEM_TYPE),
.FAMILY (TG_FAMILY),
.BL_WIDTH (BL_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.CMD_SEED_VALUE (32'h56456783),
.DATA_SEED_VALUE (32'h12345678),
.DATA_MODE (DATA_MODE),
.PORT_MODE (PORT_MODE)
)
u_init_mem_pattern_ctr
(
.clk_i (clk),
.rst_i (rst),
.memc_cmd_en_i (memc_cmd_en),
.memc_wr_en_i (tg_memc_wr_en),
.vio_modify_enable (vio_modify_enable),
.vio_instr_mode_value (vio_instr_mode_value),
.vio_data_mode_value (vio_data_mode_value),
.vio_addr_mode_value (vio_addr_mode_value),
.vio_bl_mode_value (vio_bl_mode_value), // always set to PRBS_BL mode
.vio_fixed_bl_value (vio_fixed_bl_value), // always set to 64 in order to run PRBS data pattern
.vio_data_mask_gen (vio_data_mask_gen),
.memc_init_done_i (memc_init_done),
.cmp_error (error),
.run_traffic_o (tg_run_traffic),
.start_addr_o (tg_start_addr),
.end_addr_o (tg_end_addr),
.cmd_seed_o (tg_cmd_seed),
.data_seed_o (tg_data_seed),
.load_seed_o (tg_load_seed),
.addr_mode_o (tg_addr_mode),
.instr_mode_o (tg_instr_mode),
.bl_mode_o (tg_bl_mode),
.data_mode_o (tg_data_mode),
.mode_load_o (tg_mode_load),
.fixed_bl_o (tg_fixed_bl),
.fixed_instr_o (tg_fixed_instr),
.mem_pattern_init_done_o (mem_pattern_init_done)
);
// traffic generator instantiation for Port-0
memc_traffic_gen #
(
.TCQ (TCQ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.nCK_PER_CLK (nCK_PER_CLK),
.PORT_MODE (PORT_MODE),
.DWIDTH (DATA_WIDTH),
.FAMILY (TG_FAMILY),
.MEM_TYPE (MEM_TYPE),
.SIMULATION (SIMULATION),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN ),
.ADDR_WIDTH (ADDR_WIDTH),
.BL_WIDTH (BL_WIDTH),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.PRBS_SADDR_MASK_POS (BEGIN_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR (BEGIN_ADDRESS),
.PRBS_EADDR (END_ADDRESS),
.EYE_TEST (EYE_TEST)
)
u_memc_traffic_gen
(
.clk_i (clk),
.rst_i (rst),
.run_traffic_i (tg_run_traffic),
.manual_clear_error (manual_clear_error),
.cmds_gap_delay_value (cmds_gap_delay_value),
// runtime parameter
.mem_pattern_init_done_i (mem_pattern_init_done),
.start_addr_i (tg_start_addr),
.end_addr_i (tg_end_addr),
.cmd_seed_i (tg_cmd_seed),
.data_seed_i (tg_data_seed),
.load_seed_i (tg_load_seed),
.addr_mode_i (tg_addr_mode),
.instr_mode_i (tg_instr_mode),
.bl_mode_i (tg_bl_mode),
.data_mode_i (tg_data_mode),
.mode_load_i (tg_mode_load),
.wr_data_mask_gen_i (vio_data_mask_gen),
// fixed pattern inputs interface
.fixed_bl_i (tg_fixed_bl),
.fixed_instr_i (tg_fixed_instr),
.fixed_addr_i (fixed_addr_i),
.fixed_data_i (fixed_data_i),
// BRAM interface.
.bram_cmd_i (bram_cmd_i),
// .bram_addr_i (bram_addr_i ),
// .bram_instr_i ( bram_instr_i),
.bram_valid_i (bram_valid_i),
.bram_rdy_o (bram_rdy_o),
// MCB INTERFACE
.memc_cmd_en_o (memc_cmd_en),
.memc_cmd_instr_o (memc_cmd_instr),
.memc_cmd_bl_o (memc_cmd_bl),
.memc_cmd_addr_o (memc_cmd_addr),
.memc_cmd_full_i (memc_cmd_full),
.memc_wr_en_o (memc_wr_en),
.memc_wr_data_end_o (memc_wr_end),
.memc_wr_mask_o (memc_wr_mask),
.memc_wr_data_o (memc_wr_data),
.memc_wr_full_i (memc_wr_full),
.memc_rd_en_o (memc_rd_en),
.memc_rd_data_i (memc_rd_data),
.memc_rd_empty_i (memc_rd_empty),
.qdr_wr_cmd_o (qdr_wr_cmd_o),
.qdr_rd_cmd_o (qdr_rd_cmd_o),
// status feedback
.counts_rst (rst),
.wr_data_counts (),
.rd_data_counts (),
.error (error), // asserted whenever the read back data is not correct.
.error_status (error_status), // TBD how signals mapped
.cmp_data (cmp_data),
.cmp_data_valid (cmp_data_valid),
.cmp_error (cmp_error),
.mem_rd_data (),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.dq_error_bytelane_cmp (),
.cumlative_dq_lane_error (),
.cumlative_dq_r0_bit_error (),
.cumlative_dq_f0_bit_error (),
.cumlative_dq_r1_bit_error (),
.cumlative_dq_f1_bit_error (),
.dq_r0_bit_error_r (),
.dq_f0_bit_error_r (),
.dq_r1_bit_error_r (),
.dq_f1_bit_error_r (),
.dq_r0_read_bit (),
.dq_f0_read_bit (),
.dq_r1_read_bit (),
.dq_f1_read_bit (),
.dq_r0_expect_bit (),
.dq_f0_expect_bit (),
.dq_r1_expect_bit (),
.dq_f1_expect_bit (),
.error_addr ()
);
endmodule
|
//---------------------------------------------------------------------//
// Name: am_put_fpga.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Computes the exercise price.
//---------------------------------------------------------------------//
module compute_vex(
clk,
nrst,
start,
log_lambda_up,
log_lambda_down,
K_over_S,
v_ex,
wraddr,
wren,
done
);
input clk;
input nrst;
input start;
input [63:0] log_lambda_up;
input [63:0] log_lambda_down;
input [63:0] K_over_S;
output [63:0] v_ex;
output [9:0] wraddr;
output [7:0]wren;
output done;
//---------------------------------------------------------------------//
// Wires
//---------------------------------------------------------------------//
reg [63:0] latched_log_lambda_up;
reg [63:0] latched_log_lambda_down;
reg [63:0] v_ex;
wire [63:0] mult_result;
wire [63:0] exp_result;
wire [63:0] sub_result;
wire [63:0] index_fp;
reg clk_en;
reg cnt_en;
reg [12:0] timer1;
reg [6:0] timer2;
reg [13:0] counter1;
reg [13:0] counter2;
reg [7:0] wren;
wire t1_expire = timer1[12];
wire t2_expire = timer2[6];
reg second_half;
wire first_half_done = (timer1 == 0); // Pulse signal.
assign wraddr[9:0] = counter2[12:3];
// Delay the 'second half' signal by 5 cycles to select for multiply.
reg [4:0]delay;
always@(posedge clk) delay <= {delay[3:0], second_half};
//---------------------------------------------------------------------//
// Instantiations
//---------------------------------------------------------------------//
int_to_fp int_to_fp_inst (
.clk_en(clk_en),
.clock(clk ),
.dataa({20'b0, second_half ? timer1[11:0] : counter1[11:0]}),
.result (index_fp)
);
fp_mult_slow stage1_multiply(
.clk_en(clk_en),
.clock(clk),
.dataa( delay[4] ? latched_log_lambda_down:latched_log_lambda_up ),
.datab(index_fp),
.result(mult_result)
);
fp_exp stage1_exponent (
.clk_en(clk_en),
.clock(clk),
.data(mult_result),
.result(exp_result)
);
fp_sub stage1_sub (
.clk_en(clk_en),
.clock(clk ),
.dataa(K_over_S),
.datab(exp_result),
.result(sub_result)
);
//---------------------------------------------------------------------//
// Control Logic.
//---------------------------------------------------------------------//
// Latch log_lambda_up.
always@(posedge clk)
if(~nrst) latched_log_lambda_up <= 64'h0;
else if(start) latched_log_lambda_up <= log_lambda_up;
else latched_log_lambda_up <= latched_log_lambda_up;
// Latch log_lambda_down.
always@(posedge clk)
if(~nrst) latched_log_lambda_down <= 64'h0;
else if(start) latched_log_lambda_down <= log_lambda_down;
else latched_log_lambda_down <= latched_log_lambda_down;
// Latch for clock enable.
always@(posedge clk)
if(~nrst) clk_en <= 1'b0;
else if(start) clk_en <= 1'b1;
else if(counter2 == 14'd8000) clk_en <= 1'b0;
// else if(counter2 == 14'd160) clk_en <= 1'b0;
// Latch for count enable.
always@(posedge clk)
if(~nrst) cnt_en <= 1'b0;
else if(start) cnt_en <= 1'b1;
else if(counter1 == 14'd3999) cnt_en <= 1'b0;
// else if(counter1 == 14'd79) cnt_en <= 1'b0;
// Latch first_half_done.
always@(posedge clk)
if(~nrst) second_half <= 1'b1;
else if(start) second_half <= 1'b1;
else if(first_half_done) second_half <= 1'b0;
// Assign output based on sign of subtraction result.
always@(posedge clk)
begin
if(sub_result[63]) v_ex[63:0] <= 64'h0000000000000000; // Negative.
else v_ex[63:0] <= sub_result[63:0]; // Positive or 0.
// Debug code, to put incremental into memory.
// if(start) v_ex[63:0] <= 63'd0;
// else v_ex <= v_ex + 1;
end
// One-hot counter for write enable.
always@(posedge clk)
if (~nrst) wren <= 8'b00000000;
else if(~clk_en) wren <= 8'b00000000;
else if(timer2 == 0) wren <= 8'b00000001;
else begin
wren <= {wren[6], wren[5], wren[4], wren[3],
wren[2], wren[1], wren[0], wren[7]};
end
//---------------------------------------------------------------------//
// Timers and Counters
//---------------------------------------------------------------------//
// Timer T1
// - Counts down from 4000, then back up.
// - Stops counting when it reaches -1.
always @(posedge clk)
if (~nrst) timer1 <= -1;
else if(start) timer1 <= {1'b0,12'd4000};
//else if(start) timer1 <= {1'b0,12'd80};
else if(cnt_en && !t1_expire) timer1 <= timer1 - 1;
// Timer T2
// - Counts down from 47 (for 48 cycle latency).
// - Stops counting when it reaches -1.
always @(posedge clk)
if (~nrst) timer2 <= -1;
else if(start) timer2 <= {1'b0,6'b101110};
else if(clk_en && !t2_expire) timer2 <= timer2 - 1;
// Counter C1
// Count up from 0 to 4000;
always @(posedge clk)
if(~nrst) counter1 <= -1;
else if(first_half_done) counter1 <= 1;
else if(cnt_en && t1_expire) counter1 <= counter1 + 1;
// Counter C2
// - Counts from 0 to 8000;
// - Output is used as address + channel selection.
always @(posedge clk)
if (~nrst) counter2 <= 0;
else if(start) counter2 <= 0;
else if(clk_en && t2_expire) counter2 <= counter2 + 1;
// State machine to pulse 'done' when finished.
reg [1:0] state;
assign done = state[1];
always@(posedge clk)
if(!nrst) state <= 2'b00;
else if(start) state <= 2'b01;
else if((state == 2'b01) && ~clk_en) state <= 2'b10;
else if(state == 2'b10) state <= 2'b00;
endmodule
|
/*******************************************************************************
* Function: Packet-->Memory Mapped Transaction Converter
* Author: Andreas Olofsson
* License: MIT (see LICENSE file in OH! repository)
*
* Documentation:
*
* see ./enoc_pack.v for packet formatting
*
******************************************************************************/
module enoc_unpack
#(parameter AW = 32, // address width
parameter PW = 104) // packet width
(
//Input packet
input [PW-1:0] packet_in,
//Write
output cmd_write,//start write
output cmd_write_stop,//stop burst
//Read
output cmd_read,
//Atomic read/write
output cmd_atomic_add,
output cmd_atomic_and,
output cmd_atomic_or,
output cmd_atomic_xor,
output cmd_cas,
//Command Fields
output [3:0] cmd_opcode,//raw opcode
output [3:0] cmd_length,//bust length(up to 16)
output [2:0] cmd_size,//size of each transfer
output [7:0] cmd_user, //user field
//Address/Data
output [AW-1:0] dstaddr, // read/write target address
output [AW-1:0] srcaddr, // read return address
output [2*AW-1:0] data // write data
);
wire [15:0] cmd;
//############################################
// Command Decode
//############################################
enoc_decode enoc_decode (//Input
.cmd_in (cmd[15:0]),
// Outputs
.cmd_write (cmd_write),
.cmd_write_stop (cmd_write_stop),
.cmd_read (cmd_read),
.cmd_cas (cmd_cas),
.cmd_atomic_add (cmd_atomic_add),
.cmd_atomic_and (cmd_atomic_and),
.cmd_atomic_or (cmd_atomic_or),
.cmd_atomic_xor (cmd_atomic_xor),
.cmd_opcode (cmd_opcode[3:0]),
.cmd_user (cmd_user[7:0]),
.cmd_length (cmd_length[3:0]),
.cmd_size (cmd_size[2:0]));
generate
//######################
// 16-Bit ("lite/apb like")
//######################
if(AW==16) begin : aw16
if(PW==40) begin : p40
assign cmd[7:0] = packet_in[7:0];
assign cmd[15:8] = 8'b0;
assign dstaddr[15:0] = packet_in[23:8];
assign srcaddr[15:0] = packet_in[39:24];
assign data[31:0] = {16'b0,packet_in[39:24]};
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw16
//######################
// 32-Bit
//######################
if(AW==32) begin : aw32
if(PW==80) begin: p80
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[31:0] = packet_in[79:48];
assign data[31:0] = packet_in[79:48];
assign data[63:32] = 32'b0;
end
else if(PW==112) begin: p112
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[31:0] = packet_in[79:48];
assign data[63:0] = packet_in[111:48];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw32
//######################
// 64-Bit
//######################
if(AW==64) begin : aw64
if(PW==144) begin: p144
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[127:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = 64'b0;
end
else if(PW==208) begin: p208
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[63:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = packet_in[207:144];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw64
//######################
// 128-Bit
//######################
if(AW==128) begin : aw128
if(PW==272) begin: p272
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[63:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = packet_in[207:144];
assign srcaddr[127:64] = packet_in[207:144];
assign dstaddr[127:64] = packet_in[271:208];
assign data[255:128] = 128'b0;
end
else if(PW==400) begin: p400
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[63:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = packet_in[207:144];
assign srcaddr[127:64] = packet_in[207:144];
assign dstaddr[127:64] = packet_in[271:208];
assign data[255:128] = packet_in[399:272];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw128
endgenerate
endmodule // enoc_unpack
|
// This counter counts up and is occasionally cleared.
// If up and clear are applied on the same cycle, the
// clear occurs first, and then the up.
//
`include "bsg_defines.v"
module bsg_counter_clear_up #(parameter `BSG_INV_PARAM(max_val_p)
// this originally had an "invalid" default value of -1
// which is a bad choice for a counter
,parameter init_val_p = `BSG_UNDEFINED_IN_SIM('0)
,parameter ptr_width_lp =
`BSG_SAFE_CLOG2(max_val_p+1)
,parameter disable_overflow_warning_p = 0
)
(input clk_i
, input reset_i
, input clear_i
, input up_i
// fixme: count_o should be renamed to count_r_o since some modules
// depend on this being a register and we want to indicate this at the interface level
, output logic [ptr_width_lp-1:0] count_o
);
// keeping track of number of entries and updating read and
// write pointers, and displaying errors in case of overflow
// or underflow
always_ff @(posedge clk_i)
begin
if (reset_i)
count_o <= init_val_p;
else
count_o <= clear_i ? (ptr_width_lp ' (up_i) ) : (count_o+(ptr_width_lp ' (up_i)));
end
//synopsys translate_off
always_ff @ (negedge clk_i)
begin
if ((count_o==ptr_width_lp '(max_val_p)) && up_i && (reset_i===0) && !disable_overflow_warning_p)
$display("%m error: counter overflow at time %t", $time);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_counter_clear_up)
|
//------------------------------------------------------------------------------
// File : axi_pat_gen.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: This is a very simple pattern generator which will generate packets
// with the supplied dest_addr and src_addr and incrementing data. The packet size
// increments between the min and max size (which can be set to the same value if a
// specific size is required
//
// the pattteren generator is only throttled by the FIFO hitting full which in turn
// is throttled by the transmit rate of the MAC (10M/100M or 1G). Since the example
// design system does not use active flow control it is possible for the FIFO's to
// overflow on RX. To avoid this a basic rate controller is implemented which will
// throttle the patteren generatoor output to just below the selected speed.
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module axi_pat_gen #(
parameter DEST_ADDR = 48'hda0102030405,
parameter SRC_ADDR = 48'h5a0102030405,
parameter MAX_SIZE = 16'd500,
parameter MIN_SIZE = 16'd64,
parameter ENABLE_VLAN = 1'b0,
parameter VLAN_ID = 12'd2,
parameter VLAN_PRIORITY = 3'd2
)(
input axi_tclk,
input axi_tresetn,
input enable_pat_gen,
input [1:0] speed,
output reg [7:0] tdata,
output tvalid,
output reg tlast,
input tready
);
parameter IDLE = 3'b000,
HEADER = 3'b001,
SIZE = 3'b010,
DATA = 3'b011,
OVERHEAD = 3'b100;
// work out the adjustment required to get the right packet size.
localparam PKT_ADJUST = (ENABLE_VLAN) ? 22 : 18;
// generate the vlan fields
localparam VLAN_HEADER = {8'h81, 8'h00, VLAN_PRIORITY, 1'b0, VLAN_ID};
// generate the require header count compare
localparam HEADER_LENGTH = (ENABLE_VLAN) ? 15 : 11;
// generate the required bandwidth controls based on speed
// we want to use less than 100% bandwidth to avoid loopback overflow
localparam BW_1G = 230;
localparam BW_100M = 23;
localparam BW_10M = 2;
reg [11:0] byte_count;
reg [3:0] header_count;
reg [4:0] overhead_count;
reg [11:0] pkt_size;
reg [2:0] next_gen_state;
reg [2:0] gen_state;
wire [7:0] lut_data;
reg tvalid_int;
// rate control signals
reg [7:0] basic_rc_counter;
reg add_credit;
reg [12:0] credit_count;
wire axi_treset;
assign axi_treset = !axi_tresetn;
// need a packet counter - max size limited to 11 bits
always @(posedge axi_tclk)
begin
if (axi_treset) begin
byte_count <= 0;
end
else if (gen_state == DATA & |byte_count & tready) begin
byte_count <= byte_count -1;
end
else if (gen_state == HEADER) begin
byte_count <= pkt_size;
end
end
// need a smaller count to manage the header insertion
always @(posedge axi_tclk)
begin
if (axi_treset) begin
header_count <= 0;
end
else if (gen_state == HEADER & !(&header_count) & (tready | !tvalid_int)) begin
header_count <= header_count + 1;
end
else if (gen_state == SIZE & tready) begin
header_count <= 0;
end
end
// need a count to manage the frame overhead (assume 24 bytes)
always @(posedge axi_tclk)
begin
if (axi_treset) begin
overhead_count <= 0;
end
else if (gen_state == OVERHEAD & |overhead_count & tready) begin
overhead_count <= overhead_count - 1;
end
else if (gen_state == IDLE) begin
overhead_count <= 24;
end
end
// need a smaller count to manage the header insertion
// adjust parameter values by 18 to allow for header and crc
// so the pkt_size can be issued directly in the size field
always @(posedge axi_tclk)
begin
if (axi_treset) begin
pkt_size <= MIN_SIZE - PKT_ADJUST;
end
else if (gen_state == DATA & next_gen_state != DATA) begin
if (pkt_size == MAX_SIZE - PKT_ADJUST)
pkt_size <= MIN_SIZE - PKT_ADJUST;
else
pkt_size <= pkt_size + 1;
end
end
// store the parametised values in a lut (64 deep)
// this should mean the values could be adjusted in fpga_editor etc..
genvar i;
generate
for (i=0; i<=7; i=i+1) begin
LUT6 #(
.INIT ({48'd0,
VLAN_HEADER[i],
VLAN_HEADER[i+8],
VLAN_HEADER[i+16],
VLAN_HEADER[i+24],
SRC_ADDR[i],
SRC_ADDR[i+8],
SRC_ADDR[i+16],
SRC_ADDR[i+24],
SRC_ADDR[i+32],
SRC_ADDR[i+40],
DEST_ADDR[i],
DEST_ADDR[i+8],
DEST_ADDR[i+16],
DEST_ADDR[i+24],
DEST_ADDR[i+32],
DEST_ADDR[i+40]
}) // Specify LUT Contents
) LUT6_inst (
.O (lut_data[i]),
.I0 (header_count[0]),
.I1 (header_count[1]),
.I2 (header_count[2]),
.I3 (header_count[3]),
.I4 (1'b0),
.I5 (1'b0)
);
end
endgenerate
// rate control logic
// first we need an always active counter to provide the credit control
always @(posedge axi_tclk)
begin
if (axi_treset | !enable_pat_gen)
basic_rc_counter <= 255;
else
basic_rc_counter <= basic_rc_counter + 1;
end
// now we need to set the compare level depending upon the selected speed
// the credits are applied using a simple less-than check
always @(posedge axi_tclk)
begin
if (speed[1])
if (basic_rc_counter < BW_1G)
add_credit <= 1;
else
add_credit <= 0;
else if (speed[0])
if (basic_rc_counter < BW_100M)
add_credit <= 1;
else
add_credit <= 0;
else
if (basic_rc_counter < BW_10M)
add_credit <= 1;
else
add_credit <= 0;
end
// basic credit counter - -ve value means do not send a frame
always @(posedge axi_tclk)
begin
if (axi_treset)
credit_count <= 0;
else begin
// if we are in frame
if (gen_state != IDLE) begin
if (!add_credit & credit_count[12:10] != 3'b110) // stop decrementing at -2048
credit_count <= credit_count - 1;
end
else begin
if (add_credit & credit_count[12:11] != 2'b01) // stop incrementing at 2048
credit_count <= credit_count + 1;
end
end
end
// simple state machine to control the data
// on the transition from IDLE we reset the counters and increment the packet size
always @(gen_state or enable_pat_gen or header_count or tready or byte_count or tvalid_int or
credit_count or overhead_count)
begin
next_gen_state = gen_state;
case (gen_state)
IDLE : begin
if (enable_pat_gen & !tvalid_int & !credit_count[12])
next_gen_state = HEADER;
end
HEADER : begin
if (header_count == HEADER_LENGTH & tready)
next_gen_state = SIZE;
end
SIZE : begin
// when we enter SIZE header count is initially all 1's
// it is cleared when we enter SIZE which gives us the required two cycles in this state
if (header_count == 0 & tready)
next_gen_state = DATA;
end
DATA : begin
// when an AVB AV channel we want to keep valid asserted to indicate a continuous feed of data
// the AVB module is then enitirely resposible for the bandwidth
if (byte_count == 1 & tready) begin
next_gen_state = OVERHEAD;
end
end
OVERHEAD : begin
if (overhead_count == 1 & tready) begin
next_gen_state = IDLE;
end
end
default : begin
next_gen_state = IDLE;
end
endcase
end
always @(posedge axi_tclk)
begin
if (axi_treset) begin
gen_state <= IDLE;
end
else begin
gen_state <= next_gen_state;
end
end
// now generate the TVALID output
always @(posedge axi_tclk)
begin
if (axi_treset)
tvalid_int <= 0;
else if (gen_state != IDLE & gen_state != OVERHEAD)
tvalid_int <= 1;
else if (tready)
tvalid_int <= 0;
end
// now generate the TDATA output
always @(posedge axi_tclk)
begin
if (gen_state == HEADER & (tready | !tvalid_int))
tdata <= lut_data;
else if (gen_state == SIZE & tready) begin
if (header_count[3])
tdata <= {5'h0, pkt_size[10:8]};
else
tdata <= pkt_size[7:0];
end
else if (tready)
tdata <= byte_count[7:0];
end
// now generate the TLAST output
always @(posedge axi_tclk)
begin
if (axi_treset)
tlast <= 0;
else if (byte_count == 1 & tready)
tlast <= 1;
else if (tready)
tlast <= 0;
end
assign tvalid = tvalid_int;
endmodule
|
//`timescale 1 ns / 100 ps
module dv_emon();
parameter DW = 32;
//Stimulus to drive
reg clk;
reg reset;
reg mi_access;
reg [19:0] mi_addr;
reg [31:0] mi_data_in;
reg mi_write;
reg [1:0] test_state;
reg go;
reg erx_rdfifo_access; // To emon of emon.v
reg erx_rdfifo_wait; // To emon of emon.v
reg erx_wbfifo_access; // To emon of emon.v
reg erx_wbfifo_wait; // To emon of emon.v
reg erx_wrfifo_access; // To emon of emon.v
reg erx_wrfifo_wait; // To emon of emon.v
reg etx_rdfifo_access; // To emon of emon.v
reg etx_rdfifo_wait; // To emon of emon.v
reg etx_wbfifo_access; // To emon of emon.v
reg etx_wbfifo_wait; // To emon of emon.v
reg etx_wrfifo_access; // To emon of emon.v
reg etx_wrfifo_wait; // To emon of emon.v
//Reset
initial
begin
$display($time, " << Starting the Simulation >>");
#0
clk = 1'b0; // at time 0
reset = 1'b1; // reset is active
mi_write = 1'b0;
mi_access = 1'b0;
mi_addr[19:0] = 20'h0;
mi_data_in[31:0] = 32'h0;
test_state[1:0] = 2'b00;
go = 1'b0;
erx_rdfifo_access = 1'b1;
erx_rdfifo_wait = 1'b1;
erx_wbfifo_access = 1'b1;
erx_wbfifo_wait = 1'b1;
erx_wrfifo_access = 1'b1;
erx_wrfifo_wait = 1'b1;
etx_rdfifo_access = 1'b1;
etx_rdfifo_wait = 1'b1;
etx_wbfifo_access = 1'b1;
etx_wbfifo_wait = 1'b1;
etx_wrfifo_access = 1'b1;
etx_wrfifo_wait = 1'b1;
#100
reset = 1'b0; // at time 100 release reset
#100
go = 1'b1;
#10000
$finish;
end
//Clock
always
#10 clk = ~clk;
//Pattern generator
//1.) Write in 8 transactions (split into low and high)
//2.) Read back 8 transactions (split into low and high)
always @ (negedge clk)
if(go)
begin
case(test_state[1:0])
2'b00://write
if(~done)
begin
mi_access <= 1'b1;
mi_write <= 1'b1;
mi_addr[19:0] <= 20'hf036c;
mi_data_in[31:0] <= 32'h8_7_6_5_4_3_2_1;
test_state <= 2'b01;
end
2'b01://read
if(~done)
begin
mi_write <= 1'b0;
mi_access <= 1'b1;
mi_addr[19:0] <= mi_addr[19:0]+20'h4;
mi_data_in[31:0] <= mi_data_in[31:0]-4'h8;
end
else
begin
test_state <= 2'b10;
mi_write <= 1'b0;
end // else: !if(~done)
2'b10://init array
begin
mi_addr[19:0] <= mi_addr[19:0]-20'h4;
end
endcase // case (test_state[1:0])
end
wire done = (mi_addr[19:0]==6'b001101);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [5:0] emon_zero_flag; // From emon of emon.v
wire [DW-1:0] mi_data_out; // From emon of emon.v
// End of automatics
/*AUTOWIRE*/
//DUT
emon emon(
/*AUTOINST*/
// Outputs
.mi_data_out (mi_data_out[DW-1:0]),
.emon_zero_flag (emon_zero_flag[5:0]),
// Inputs
.clk (clk),
.reset (reset),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_addr (mi_addr[19:0]),
.mi_data_in (mi_data_in[DW-1:0]),
.erx_rdfifo_access (erx_rdfifo_access),
.erx_rdfifo_wait (erx_rdfifo_wait),
.erx_wrfifo_access (erx_wrfifo_access),
.erx_wrfifo_wait (erx_wrfifo_wait),
.erx_wbfifo_access (erx_wbfifo_access),
.erx_wbfifo_wait (erx_wbfifo_wait),
.etx_rdfifo_access (etx_rdfifo_access),
.etx_rdfifo_wait (etx_rdfifo_wait),
.etx_wrfifo_access (etx_wrfifo_access),
.etx_wrfifo_wait (etx_wrfifo_wait),
.etx_wbfifo_access (etx_wbfifo_access),
.etx_wbfifo_wait (etx_wbfifo_wait));
//Waveform dump
initial
begin
$dumpfile("test.vcd");
$dumpvars(0, dv_emon);
end
endmodule // dv_emon
// Local Variables:
// verilog-library-directories:("." "../hdl" "../../memory/hdl ")
// End:
|
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase_a==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase_a==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase_a==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase_a==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase_a==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase_a==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase_a==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase_a==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase_a==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase_a==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|P%d|%d%d%d|%d", cnt[19:0], u.core.elem_a, u.core.phase_a[2:0], u.core.iter_done_a, u.core.pchange_a, u.core.irst_a, u.core.ecnt_a);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("(%d)", u.core.state);
///////////////// can be parameterized
$write("| %d %d %d %d| %d %d %d %d|",
u.core.im00_a.imf.cnt, u.core.im01_a.imf.cnt, u.core.im02_a.imf.cnt, u.core.im03_a.imf.cnt,
u.core.im00_b.imf.cnt, u.core.im01_b.imf.cnt, u.core.im02_b.imf.cnt, u.core.im03_b.imf.cnt);
$write(" ");
if (u.core.F01_deq_a) $write("%08x %08x %08x %08x ", u.core.F01_dot_a[127:96], u.core.F01_dot_a[95:64], u.core.F01_dot_a[63:32], u.core.F01_dot_a[31:0]); else $write(" ");
if (u.core.F01_deq_b) $write("%08x %08x %08x %08x ", u.core.F01_dot_b[127:96], u.core.F01_dot_b[95:64], u.core.F01_dot_b[63:32], u.core.F01_dot_b[31:0]); else $write(" ");
// $write("| ");
// $write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
(selector == 1) ? {r07,r06,r05,r04} :
(selector == 2) ? {r11,r10,r09,r08} :
(selector == 3) ? {r15,r14,r13,r12} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
// A parallel input shift register clocked on falling edge
`default_nettype none
`timescale 10ns/1ns
// Main test module
module testbench;
reg clk;
reg clk184;
reg ce;
reg rstn;
reg load;
reg [7:0] inbyte;
wire busy;
utx utx0(
.clk(clk),
.rstn(rstn),
.inbyte(inbyte),
.load(load),
.busy(busy)
);
initial begin
$dumpvars(0, testbench);
clk = 0;
rstn = 0;
load = 0;
inbyte = 8'h55;
# 10
rstn = 1;
# 10
load = 1;
# 10
load = 0;
#8700
inbyte = 8'haa;
load = 1;
# 10
load = 0;
#100000 $finish;
end
always #5 clk = ~clk;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ninjasymbol.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ninjasymbol (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/ninjasymbol.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/ninjasymbol.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ninjasymbol_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INV_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_BLACKBOX_V
|
module acl_iface_system (
config_clk_clk,
reset_n,
kernel_clk_clk,
kernel_clk_snoop_clk,
kernel_mem0_waitrequest,
kernel_mem0_readdata,
kernel_mem0_readdatavalid,
kernel_mem0_burstcount,
kernel_mem0_writedata,
kernel_mem0_address,
kernel_mem0_write,
kernel_mem0_read,
kernel_mem0_byteenable,
kernel_mem0_debugaccess,
kernel_reset_reset_n,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
peripheral_hps_io_emac1_inst_TX_CLK,
peripheral_hps_io_emac1_inst_TXD0,
peripheral_hps_io_emac1_inst_TXD1,
peripheral_hps_io_emac1_inst_TXD2,
peripheral_hps_io_emac1_inst_TXD3,
peripheral_hps_io_emac1_inst_RXD0,
peripheral_hps_io_emac1_inst_MDIO,
peripheral_hps_io_emac1_inst_MDC,
peripheral_hps_io_emac1_inst_RX_CTL,
peripheral_hps_io_emac1_inst_TX_CTL,
peripheral_hps_io_emac1_inst_RX_CLK,
peripheral_hps_io_emac1_inst_RXD1,
peripheral_hps_io_emac1_inst_RXD2,
peripheral_hps_io_emac1_inst_RXD3,
peripheral_hps_io_sdio_inst_CMD,
peripheral_hps_io_sdio_inst_D0,
peripheral_hps_io_sdio_inst_D1,
peripheral_hps_io_sdio_inst_CLK,
peripheral_hps_io_sdio_inst_D2,
peripheral_hps_io_sdio_inst_D3,
peripheral_hps_io_usb1_inst_D0,
peripheral_hps_io_usb1_inst_D1,
peripheral_hps_io_usb1_inst_D2,
peripheral_hps_io_usb1_inst_D3,
peripheral_hps_io_usb1_inst_D4,
peripheral_hps_io_usb1_inst_D5,
peripheral_hps_io_usb1_inst_D6,
peripheral_hps_io_usb1_inst_D7,
peripheral_hps_io_usb1_inst_CLK,
peripheral_hps_io_usb1_inst_STP,
peripheral_hps_io_usb1_inst_DIR,
peripheral_hps_io_usb1_inst_NXT,
peripheral_hps_io_uart0_inst_RX,
peripheral_hps_io_uart0_inst_TX,
peripheral_hps_io_i2c1_inst_SDA,
peripheral_hps_io_i2c1_inst_SCL,
peripheral_hps_io_gpio_inst_GPIO53);
input config_clk_clk;
input reset_n;
output kernel_clk_clk;
output kernel_clk_snoop_clk;
output kernel_mem0_waitrequest;
output [255:0] kernel_mem0_readdata;
output kernel_mem0_readdatavalid;
input [4:0] kernel_mem0_burstcount;
input [255:0] kernel_mem0_writedata;
input [24:0] kernel_mem0_address;
input kernel_mem0_write;
input kernel_mem0_read;
input [31:0] kernel_mem0_byteenable;
input kernel_mem0_debugaccess;
output kernel_reset_reset_n;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
output peripheral_hps_io_emac1_inst_TX_CLK;
output peripheral_hps_io_emac1_inst_TXD0;
output peripheral_hps_io_emac1_inst_TXD1;
output peripheral_hps_io_emac1_inst_TXD2;
output peripheral_hps_io_emac1_inst_TXD3;
input peripheral_hps_io_emac1_inst_RXD0;
inout peripheral_hps_io_emac1_inst_MDIO;
output peripheral_hps_io_emac1_inst_MDC;
input peripheral_hps_io_emac1_inst_RX_CTL;
output peripheral_hps_io_emac1_inst_TX_CTL;
input peripheral_hps_io_emac1_inst_RX_CLK;
input peripheral_hps_io_emac1_inst_RXD1;
input peripheral_hps_io_emac1_inst_RXD2;
input peripheral_hps_io_emac1_inst_RXD3;
inout peripheral_hps_io_sdio_inst_CMD;
inout peripheral_hps_io_sdio_inst_D0;
inout peripheral_hps_io_sdio_inst_D1;
output peripheral_hps_io_sdio_inst_CLK;
inout peripheral_hps_io_sdio_inst_D2;
inout peripheral_hps_io_sdio_inst_D3;
inout peripheral_hps_io_usb1_inst_D0;
inout peripheral_hps_io_usb1_inst_D1;
inout peripheral_hps_io_usb1_inst_D2;
inout peripheral_hps_io_usb1_inst_D3;
inout peripheral_hps_io_usb1_inst_D4;
inout peripheral_hps_io_usb1_inst_D5;
inout peripheral_hps_io_usb1_inst_D6;
inout peripheral_hps_io_usb1_inst_D7;
input peripheral_hps_io_usb1_inst_CLK;
output peripheral_hps_io_usb1_inst_STP;
input peripheral_hps_io_usb1_inst_DIR;
input peripheral_hps_io_usb1_inst_NXT;
input peripheral_hps_io_uart0_inst_RX;
output peripheral_hps_io_uart0_inst_TX;
inout peripheral_hps_io_i2c1_inst_SDA;
inout peripheral_hps_io_i2c1_inst_SCL;
inout peripheral_hps_io_gpio_inst_GPIO53;
endmodule
|
module main(
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
output int_n,
output nmi_n,
output wait_n,
output res,
inout [7:0] d,
input [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
output rompg0_n,
output dos_n, // aka rompg1
output rompg2,
output rompg3,
output rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
inout [15:0] rd,
output [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
output [1:0] vred,
output [1:0] vgrn,
output [1:0] vblu,
output vhsync,
output vvsync,
output vcsync,
// AY control and audio/tape
output ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
output [2:0] ide_a,
inout [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
output vg_clk,
output vg_cs_n,
output vg_res_n,
output vg_hrdy,
output vg_rclk,
output vg_rawr,
output [1:0] vg_a, // disk drive selection
output vg_wrd,
output vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
output spiint_n
);
wire zclk; // z80 clock for short
reg [2:0] zclk_gen; // make 3.5 mhz clock
wire rst_n; // global reset
wire rrdy;
wire cbeg;
wire [15:0] rddata;
wire [4:0] rompg;
wire [7:0] zports_dout;
wire zports_dataout;
wire porthit;
wire [4:0] keys;
wire tape_in;
wire [15:0] ideout;
wire [15:0] idein;
wire [7:0] zmem_dout;
wire zmem_dataout;
wire [7:0] sd_dout_to_zports;
wire start_from_zports;
wire sd_inserted;
wire sd_readonly;
reg [3:0] ayclk_gen;
wire [7:0] received;
wire [7:0] tobesent;
wire intrq,drq;
wire vg_wrFF;
// Z80 clock control
assign zclk = clkz_in;
always @(posedge fclk)
zclk_gen <= zclk_gen + 3'd1;
assign clkz_out = zclk_gen[2];
// RESETTER
resetter myrst( .clk(fclk),
.rst_in_n(ide_rdy),
.rst_out_n(rst_n) );
defparam myrst.RST_CNT_SIZE = 6;
assign int_n=1'b1;
assign nmi_n=1'b1;
assign wait_n=1'b1;
assign res=1'b1;
assign d=8'hZZ;
assign csrom=1'b0;
assign romoe_n=1'b1;
assign romwe_n=1'b1;
assign iorq1_n=1'b1;
assign iorq2_n=1'b1;
assign rd=16'hZZZZ;
assign ay_bdir=1'b0;
assign ay_bc1=1'b0;
assign ide_d=16'hZZZZ;
assign ide_dir=1'b1;
assign ide_rs_n = 1'b0;
assign ide_cs1_n = 1'b1;
assign ide_rd_n = 1'b1;
assign ide_wr_n = 1'b1;
assign vg_cs_n=1'b1;
assign vg_res_n=1'b0;
assign sdcs_n=1'b1;
assign spiint_n=1'b1;
//AY control
always @(posedge fclk)
begin
ayclk_gen <= ayclk_gen + 4'd1;
end
assign ay_clk = ayclk_gen[3];
wire blinker;
assign ide_cs0_n = blinker;
mem_tester mytst( .clk(fclk), .rst_n(rst_n), .led(blinker), .rstart(ide_a[0]), .rready(ide_a[1]), .rstop(ide_a[2]),
.DRAM_DQ(rd), .DRAM_MA(ra), .DRAM_RAS0_N(rras0_n), .DRAM_RAS1_N(rras1_n),
.DRAM_LCAS_N(rlcas_n), .DRAM_UCAS_N(rucas_n), .DRAM_WE_N(rwe_n) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__TAP_BEHAVIORAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tap ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_BEHAVIORAL_V
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: spll_pll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module spll_pll (
areset,
inclk0,
pllena,
c0,
c1,
locked);
input areset;
input inclk0;
input pllena;
output c0;
output c1;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "112.500"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "120.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2222"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8888"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_enable1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_sclkout1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: pllena 0 0 0 0 INPUT VCC "pllena"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: @pllena 0 0 0 0 pllena 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll_bb.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll_waveforms.html TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll_wave*.jpg FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spll_pll.ppf TRUE FALSE
|
/// date:2016/3/9
/// engineer: ZhaiShaoMin
module dc_download(//input
clk,
rst,
IN_flit_dc,
v_IN_flit_dc,
In_flit_ctrl_dc,
dc_done_access,
//output
v_dc_download,
dc_download_flits,
dc_download_state
);
/////// reply cmd
parameter wbrep_cmd=5'b10000;
parameter C2Hinvrep_cmd=5'b10001;
parameter flushrep_cmd=5'b10010;
parameter ATflurep_cmd=5'b10011;
parameter shrep_cmd=5'b11000;
parameter exrep_cmd=5'b11001;
parameter SH_exrep_cmd=5'b11010;
parameter SCflurep_cmd=5'b11100;
parameter instrep_cmd=5'b10100;
parameter C2Cinvrep_cmd=5'b11011;
parameter nackrep_cmd=5'b10101;
parameter flushfail_rep_cmd=5'b10110;
parameter wbfail_rep_cmd=5'b10111;
//input
input clk;
input rst;
input [15:0] IN_flit_dc; //from IN fifos
input v_IN_flit_dc;
input [1:0] In_flit_ctrl_dc;
input dc_done_access; // from data cache
//output
output v_dc_download; // to data cache
output [143:0] dc_download_flits;
output [1:0] dc_download_state; // to arbiter_IN_node
//
reg [1:0] dc_download_nstate;
reg [1:0] dc_download_cstate;
parameter dc_download_idle=2'b00;
parameter dc_download_busy=2'b01;
parameter dc_download_rdy=2'b10;
reg [15:0] flit_reg1;
reg [15:0] flit_reg2;
reg [15:0] flit_reg3;
reg [15:0] flit_reg4;
reg [15:0] flit_reg5;
reg [15:0] flit_reg6;
reg [15:0] flit_reg7;
reg [15:0] flit_reg8;
reg [15:0] flit_reg9;
assign dc_download_state=dc_download_cstate;
assign dc_download_flits={flit_reg9,flit_reg8,flit_reg7,flit_reg6,flit_reg5,flit_reg4,flit_reg3,flit_reg2,flit_reg1};
reg v_dc_download;
reg en_flit_dc;
reg inc_cnt;
reg fsm_rst;
/// fsm of ic_download
always@(*)
begin
//default values
dc_download_nstate=dc_download_cstate;
v_dc_download=1'b0;
en_flit_dc=1'b0;
inc_cnt=1'b0;
fsm_rst=1'b0;
case(dc_download_cstate)
dc_download_idle:
begin
if(v_IN_flit_dc)
begin
if(IN_flit_dc[9:5]==nackrep_cmd||IN_flit_dc[9:5]==SCflurep_cmd||IN_flit_dc[9:5]==C2Cinvrep_cmd)
dc_download_nstate=dc_download_rdy;
else
dc_download_nstate=dc_download_busy;
en_flit_dc=1'b1;
inc_cnt=1'b1;
end
end
dc_download_busy:
begin
if(v_IN_flit_dc)
begin
if(In_flit_ctrl_dc==2'b11)
begin
// en_flit_dc=1'b1;
dc_download_nstate=dc_download_rdy;
end
en_flit_dc=1'b1;
inc_cnt=1'b1;
end
end
dc_download_rdy:
begin
v_dc_download=1'b1;
if(dc_done_access)
begin
dc_download_nstate=dc_download_idle;
fsm_rst=1'b1;
end
end
endcase
end
reg [3:0] cnt;
reg [8:0] en_flits;
// select right inst_word_in
always@(*)
begin
case(cnt)
4'b0000:en_flits=9'b000000001;
4'b0001:en_flits=9'b000000010;
4'b0010:en_flits=9'b000000100;
4'b0011:en_flits=9'b000001000;
4'b0100:en_flits=9'b000010000;
4'b0101:en_flits=9'b000100000;
4'b0110:en_flits=9'b001000000;
4'b0111:en_flits=9'b010000000;
4'b1000:en_flits=9'b100000000;
default:en_flits=9'b000000000;
endcase
end
// 1st flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg1<=16'h0000;
else if(en_flits[0]&&en_flit_dc)
flit_reg1<=IN_flit_dc;
end
//2ed flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg2<=16'h0000;
else if(en_flits[1]&&en_flit_dc)
flit_reg2<=IN_flit_dc;
end
// 3rd flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg3<=16'h0000;
else if(en_flits[2]&&en_flit_dc)
flit_reg3<=IN_flit_dc;
end
//4th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg4<=16'h0000;
else if(en_flits[3]&&en_flit_dc)
flit_reg4<=IN_flit_dc;
end
//5th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg5<=16'h0000;
else if(en_flits[4]&&en_flit_dc)
flit_reg5<=IN_flit_dc;
end
//6th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg6<=16'h0000;
else if(en_flits[5]&&en_flit_dc)
flit_reg6<=IN_flit_dc;
end
//7th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg7<=16'h0000;
else if(en_flits[6]&&en_flit_dc)
flit_reg7<=IN_flit_dc;
end
//8th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg8<=16'h0000;
else if(en_flits[7]&&en_flit_dc)
flit_reg8<=IN_flit_dc;
end
//9th flit
always@(posedge clk)
begin
if(rst||fsm_rst)
flit_reg9<=16'h0000;
else if(en_flits[8]&&en_flit_dc)
flit_reg9<=IN_flit_dc;
end
// fsm regs
always@(posedge clk)
begin
if(rst)
dc_download_cstate<=2'b00;
else
dc_download_cstate<=dc_download_nstate;
end
//counter reg
always@(posedge clk)
begin
if(rst||fsm_rst)
cnt<=4'b0000;
else if(inc_cnt)
cnt<=cnt+4'b0001;
end
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i32.const.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i32.const_tb.vcd");
$dumpvars(0, cpu_tb);
#12
`assert(result, 42);
`assert(result_empty, 0);
$finish;
end
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1490159079 : 2899645186;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*
*
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the Viterbi decoder
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
//`include "bmu.v"
module bmutb;
// Modify the number of bits in the ouput bus to be 2
wire [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
reg cx0, cx1;
bmu bmu1 (cx0, cx1, bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7);
initial
begin
cx0=0; cx1=0;
#10;
cx0=0; cx1=1;
#10;
cx0=1; cx1=0;
#10;
cx0=1; cx1=1;
#10;
cx0=0; cx1=0;
#10;
end
initial
begin
$shm_open("bmu.shm");
$shm_probe("AC");
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8)
`timescale 1ps/1ps
module ad_serdes_clk #(
parameter DEVICE_TYPE = 0,
parameter DDR_OR_SDR_N = 1,
parameter CLKIN_DS_OR_SE_N = 1,
parameter SERDES_FACTOR = 8,
parameter MMCM_OR_BUFR_N = 1,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12.000,
parameter MMCM_CLK0_DIV = 2.000,
parameter MMCM_CLK1_DIV = 6) (
// clock and divided clock
input rst,
input clk_in_p,
input clk_in_n,
output clk,
output div_clk,
output out_clk,
output loaden,
output [ 7:0] phase,
// drp interface
input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [31:0] up_drp_wdata,
output [31:0] up_drp_rdata,
output up_drp_ready,
output up_drp_locked);
localparam BUFR_DIVIDE = (DDR_OR_SDR_N == 1'b1) ? SERDES_FACTOR / 2 : SERDES_FACTOR;
// internal signals
wire clk_in_s;
// defaults
assign loaden = 'd0;
assign phase = 'd0;
assign up_drp_rdata[31:16] = 'd0;
// instantiations
generate
if (CLKIN_DS_OR_SE_N == 1) begin
IBUFGDS i_clk_in_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_in_s));
end else begin
IBUF IBUF_inst (
.O(clk_in_s),
.I(clk_in_p));
end
endgenerate
generate
if (MMCM_OR_BUFR_N == 1) begin
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK0_PHASE (0.0),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV),
.MMCM_CLK1_PHASE (0.0),
.MMCM_CLK2_DIV (MMCM_CLK0_DIV),
.MMCM_CLK2_PHASE (90.0))
i_mmcm_drp (
.clk (clk_in_s),
.clk2 (1'b0),
.clk_sel (1'b1),
.mmcm_rst (rst),
.mmcm_clk_0 (clk),
.mmcm_clk_1 (div_clk),
.mmcm_clk_2 (out_clk),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata[15:0]),
.up_drp_rdata (up_drp_rdata[15:0]),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
end
endgenerate
generate
if (MMCM_OR_BUFR_N == 0) begin
BUFIO i_clk_buf (
.I (clk_in_s),
.O (clk));
BUFR #(.BUFR_DIVIDE(BUFR_DIVIDE)) i_div_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (div_clk));
assign out_clk = clk;
assign up_drp_rdata[15:0] = 'd0;
assign up_drp_ready = 'd0;
assign up_drp_locked = 'd0;
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("5.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
(* -*- coq-prog-name: "~/research/coq/trunk/bin/coqtop.byte"; coq-prog-args: ("-emacs-U"); compile-command: "make -C ../.. TIME='time'" -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * CNRS-Ecole Polytechnique-INRIA Futurs-Universite Paris Sud *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(*i $Id: Equality.v 12073 2009-04-08 21:04:42Z msozeau $ i*)
(** Tactics related to (dependent) equality and proof irrelevance. *)
Require Export ProofIrrelevance.
Require Export JMeq.
Require Import Coq.Program.Tactics.
(** Notation for heterogenous equality. *)
Notation " [ x : X ] = [ y : Y ] " := (@JMeq X x Y y) (at level 0, X at next level, Y at next level).
(** Notation for the single element of [x = x] *)
Notation "'refl'" := (@refl_equal _ _).
(** Do something on an heterogeneous equality appearing in the context. *)
Ltac on_JMeq tac :=
match goal with
| [ H : @JMeq ?x ?X ?y ?Y |- _ ] => tac H
end.
(** Try to apply [JMeq_eq] to get back a regular equality when the two types are equal. *)
Ltac simpl_one_JMeq :=
on_JMeq ltac:(fun H => apply JMeq_eq in H).
(** Repeat it for every possible hypothesis. *)
Ltac simpl_JMeq := repeat simpl_one_JMeq.
(** Just simplify an h.eq. without clearing it. *)
Ltac simpl_one_dep_JMeq :=
on_JMeq
ltac:(fun H => let H' := fresh "H" in
assert (H' := JMeq_eq H)).
Require Import Eqdep.
(** Simplify dependent equality using sigmas to equality of the second projections if possible.
Uses UIP. *)
Ltac simpl_existT :=
match goal with
[ H : existT _ ?x _ = existT _ ?x _ |- _ ] =>
let Hi := fresh H in assert(Hi:=inj_pairT2 _ _ _ _ _ H) ; clear H
end.
Ltac simpl_existTs := repeat simpl_existT.
(** Tries to eliminate a call to [eq_rect] (the substitution principle) by any means available. *)
Ltac elim_eq_rect :=
match goal with
| [ |- ?t ] =>
match t with
| context [ @eq_rect _ _ _ _ _ ?p ] =>
let P := fresh "P" in
set (P := p); simpl in P ;
((case P ; clear P) || (clearbody P; rewrite (UIP_refl _ _ P); clear P))
| context [ @eq_rect _ _ _ _ _ ?p _ ] =>
let P := fresh "P" in
set (P := p); simpl in P ;
((case P ; clear P) || (clearbody P; rewrite (UIP_refl _ _ P); clear P))
end
end.
(** Rewrite using uniqueness of indentity proofs [H = refl_equal X]. *)
Ltac simpl_uip :=
match goal with
[ H : ?X = ?X |- _ ] => rewrite (UIP_refl _ _ H) in *; clear H
end.
(** Simplify equalities appearing in the context and goal. *)
Ltac simpl_eq := simpl ; unfold eq_rec_r, eq_rec ; repeat (elim_eq_rect ; simpl) ; repeat (simpl_uip ; simpl).
(** Try to abstract a proof of equality, if no proof of the same equality is present in the context. *)
Ltac abstract_eq_hyp H' p :=
let ty := type of p in
let tyred := eval simpl in ty in
match tyred with
?X = ?Y =>
match goal with
| [ H : X = Y |- _ ] => fail 1
| _ => set (H':=p) ; try (change p with H') ; clearbody H' ; simpl in H'
end
end.
(** Apply the tactic tac to proofs of equality appearing as coercion arguments.
Just redefine this tactic (using [Ltac on_coerce_proof tac ::=]) to handle custom coercion operators.
*)
Ltac on_coerce_proof tac T :=
match T with
| context [ eq_rect _ _ _ _ ?p ] => tac p
end.
Ltac on_coerce_proof_gl tac :=
match goal with
[ |- ?T ] => on_coerce_proof tac T
end.
(** Abstract proofs of equalities of coercions. *)
Ltac abstract_eq_proof := on_coerce_proof_gl ltac:(fun p => let H := fresh "eqH" in abstract_eq_hyp H p).
Ltac abstract_eq_proofs := repeat abstract_eq_proof.
(** Factorize proofs, by using proof irrelevance so that two proofs of the same equality
in the goal become convertible. *)
Ltac pi_eq_proof_hyp p :=
let ty := type of p in
let tyred := eval simpl in ty in
match tyred with
?X = ?Y =>
match goal with
| [ H : X = Y |- _ ] =>
match p with
| H => fail 2
| _ => rewrite (proof_irrelevance (X = Y) p H)
end
| _ => fail " No hypothesis with same type "
end
end.
(** Factorize proofs of equality appearing as coercion arguments. *)
Ltac pi_eq_proof := on_coerce_proof_gl pi_eq_proof_hyp.
Ltac pi_eq_proofs := repeat pi_eq_proof.
(** The two preceding tactics in sequence. *)
Ltac clear_eq_proofs :=
abstract_eq_proofs ; pi_eq_proofs.
Hint Rewrite <- eq_rect_eq : refl_id.
(** The refl_id database should be populated with lemmas of the form
[coerce_* t (refl_equal _) = t]. *)
Ltac rewrite_refl_id := autorewrite with refl_id.
(** Clear the context and goal of equality proofs. *)
Ltac clear_eq_ctx :=
rewrite_refl_id ; clear_eq_proofs.
(** Reapeated elimination of [eq_rect] applications.
Abstracting equalities makes it run much faster than an naive implementation. *)
Ltac simpl_eqs :=
repeat (elim_eq_rect ; simpl ; clear_eq_ctx).
(** Clear unused reflexivity proofs. *)
Ltac clear_refl_eq :=
match goal with [ H : ?X = ?X |- _ ] => clear H end.
Ltac clear_refl_eqs := repeat clear_refl_eq.
(** Clear unused equality proofs. *)
Ltac clear_eq :=
match goal with [ H : _ = _ |- _ ] => clear H end.
Ltac clear_eqs := repeat clear_eq.
(** Combine all the tactics to simplify goals containing coercions. *)
Ltac simplify_eqs :=
simpl ; simpl_eqs ; clear_eq_ctx ; clear_refl_eqs ;
try subst ; simpl ; repeat simpl_uip ; rewrite_refl_id.
(** A tactic that tries to remove trivial equality guards in induction hypotheses coming
from [dependent induction]/[generalize_eqs] invocations. *)
Ltac simpl_IH_eq H :=
match type of H with
| @JMeq _ ?x _ _ -> _ =>
refine_hyp (H (JMeq_refl x))
| _ -> @JMeq _ ?x _ _ -> _ =>
refine_hyp (H _ (JMeq_refl x))
| _ -> _ -> @JMeq _ ?x _ _ -> _ =>
refine_hyp (H _ _ (JMeq_refl x))
| _ -> _ -> _ -> @JMeq _ ?x _ _ -> _ =>
refine_hyp (H _ _ _ (JMeq_refl x))
| _ -> _ -> _ -> _ -> @JMeq _ ?x _ _ -> _ =>
refine_hyp (H _ _ _ _ (JMeq_refl x))
| _ -> _ -> _ -> _ -> _ -> @JMeq _ ?x _ _ -> _ =>
refine_hyp (H _ _ _ _ _ (JMeq_refl x))
| ?x = _ -> _ =>
refine_hyp (H (refl_equal x))
| _ -> ?x = _ -> _ =>
refine_hyp (H _ (refl_equal x))
| _ -> _ -> ?x = _ -> _ =>
refine_hyp (H _ _ (refl_equal x))
| _ -> _ -> _ -> ?x = _ -> _ =>
refine_hyp (H _ _ _ (refl_equal x))
| _ -> _ -> _ -> _ -> ?x = _ -> _ =>
refine_hyp (H _ _ _ _ (refl_equal x))
| _ -> _ -> _ -> _ -> _ -> ?x = _ -> _ =>
refine_hyp (H _ _ _ _ _ (refl_equal x))
end.
Ltac simpl_IH_eqs H := repeat simpl_IH_eq H.
Ltac do_simpl_IHs_eqs :=
match goal with
| [ H : context [ @JMeq _ _ _ _ -> _ ] |- _ ] => progress (simpl_IH_eqs H)
| [ H : context [ _ = _ -> _ ] |- _ ] => progress (simpl_IH_eqs H)
end.
Ltac simpl_IHs_eqs := repeat do_simpl_IHs_eqs.
(** We split substitution tactics in the two directions depending on which
names we want to keep corresponding to the generalization performed by the
[generalize_eqs] tactic. *)
Ltac subst_left_no_fail :=
repeat (match goal with
[ H : ?X = ?Y |- _ ] => subst X
end).
Ltac subst_right_no_fail :=
repeat (match goal with
[ H : ?X = ?Y |- _ ] => subst Y
end).
Ltac inject_left H :=
progress (inversion H ; subst_left_no_fail ; clear_dups) ; clear H.
Ltac inject_right H :=
progress (inversion H ; subst_right_no_fail ; clear_dups) ; clear H.
Ltac autoinjections_left := repeat autoinjection ltac:inject_left.
Ltac autoinjections_right := repeat autoinjection ltac:inject_right.
Ltac simpl_depind := subst_no_fail ; autoinjections ; try discriminates ;
simpl_JMeq ; simpl_existTs ; simpl_IHs_eqs.
Ltac simpl_depind_l := subst_left_no_fail ; autoinjections_left ; try discriminates ;
simpl_JMeq ; simpl_existTs ; simpl_IHs_eqs.
Ltac simpl_depind_r := subst_right_no_fail ; autoinjections_right ; try discriminates ;
simpl_JMeq ; simpl_existTs ; simpl_IHs_eqs.
(** Support for the [Equations] command.
These tactics implement the necessary machinery to solve goals produced by the
[Equations] command relative to dependent pattern-matching.
It is completely inspired from the "Eliminating Dependent Pattern-Matching" paper by
Goguen, McBride and McKinna. *)
(** The NoConfusionPackage class provides a method for making progress on proving a property
[P] implied by an equality on an inductive type [I]. The type of [noConfusion] for a given
[P] should be of the form [ Π Δ, (x y : I Δ) (x = y) -> NoConfusion P x y ], where
[NoConfusion P x y] for constructor-headed [x] and [y] will give a formula ending in [P].
This gives a general method for simplifying by discrimination or injectivity of constructors.
Some actual instances are defined later in the file using the more primitive [discriminate] and
[injection] tactics on which we can always fall back.
*)
Class NoConfusionPackage (I : Type) := { NoConfusion : Π P : Prop, Type ; noConfusion : Π P, NoConfusion P }.
(** The [DependentEliminationPackage] provides the default dependent elimination principle to
be used by the [equations] resolver. It is especially useful to register the dependent elimination
principles for things in [Prop] which are not automatically generated. *)
Class DependentEliminationPackage (A : Type) :=
{ elim_type : Type ; elim : elim_type }.
(** A higher-order tactic to apply a registered eliminator. *)
Ltac elim_tac tac p :=
let ty := type of p in
let eliminator := eval simpl in (elim (A:=ty)) in
tac p eliminator.
(** Specialization to do case analysis or induction.
Note: the [equations] tactic tries [case] before [elim_case]: there is no need to register
generated induction principles. *)
Ltac elim_case p := elim_tac ltac:(fun p el => destruct p using el) p.
Ltac elim_ind p := elim_tac ltac:(fun p el => induction p using el) p.
(** The [BelowPackage] class provides the definition of a [Below] predicate for some datatype,
allowing to talk about course-of-value recursion on it. *)
Class BelowPackage (A : Type) := {
Below : A -> Type ;
below : Π (a : A), Below a }.
(** The [Recursor] class defines a recursor on a type, based on some definition of [Below]. *)
Class Recursor (A : Type) (BP : BelowPackage A) :=
{ rec_type : A -> Type ; rec : Π (a : A), rec_type a }.
(** Lemmas used by the simplifier, mainly rephrasings of [eq_rect], [eq_ind]. *)
Lemma solution_left : Π A (B : A -> Type) (t : A), B t -> (Π x, x = t -> B x).
Proof. intros; subst. apply X. Defined.
Lemma solution_right : Π A (B : A -> Type) (t : A), B t -> (Π x, t = x -> B x).
Proof. intros; subst; apply X. Defined.
Lemma deletion : Π A B (t : A), B -> (t = t -> B).
Proof. intros; assumption. Defined.
Lemma simplification_heq : Π A B (x y : A), (x = y -> B) -> (JMeq x y -> B).
Proof. intros; apply X; apply (JMeq_eq H). Defined.
Lemma simplification_existT2 : Π A (P : A -> Type) B (p : A) (x y : P p),
(x = y -> B) -> (existT P p x = existT P p y -> B).
Proof. intros. apply X. apply inj_pair2. exact H. Defined.
Lemma simplification_existT1 : Π A (P : A -> Type) B (p q : A) (x : P p) (y : P q),
(p = q -> existT P p x = existT P q y -> B) -> (existT P p x = existT P q y -> B).
Proof. intros. injection H. intros ; auto. Defined.
Lemma simplification_K : Π A (x : A) (B : x = x -> Type), B (refl_equal x) -> (Π p : x = x, B p).
Proof. intros. rewrite (UIP_refl A). assumption. Defined.
(** This hint database and the following tactic can be used with [autosimpl] to
unfold everything to [eq_rect]s. *)
Hint Unfold solution_left solution_right deletion simplification_heq
simplification_existT1 simplification_existT2
eq_rect_r eq_rec eq_ind : equations.
(** Simply unfold as much as possible. *)
Ltac unfold_equations := repeat progress autosimpl with equations.
(** The tactic [simplify_equations] is to be used when a program generated using [Equations]
is in the goal. It simplifies it as much as possible, possibly using [K] if needed. *)
Ltac simplify_equations := repeat (unfold_equations ; simplify_eqs).
(** We will use the [block_induction] definition to separate the goal from the
equalities generated by the tactic. *)
Definition block_dep_elim {A : Type} (a : A) := a.
(** Using these we can make a simplifier that will perform the unification
steps needed to put the goal in normalised form (provided there are only
constructor forms). Compare with the lemma 16 of the paper.
We don't have a [noCycle] procedure yet. *)
Ltac simplify_one_dep_elim_term c :=
match c with
| @JMeq _ _ _ _ -> _ => refine (simplification_heq _ _ _ _ _)
| ?t = ?t -> _ => intros _ || refine (simplification_K _ t _ _)
| eq (existT _ _ _) (existT _ _ _) -> _ =>
refine (simplification_existT2 _ _ _ _ _ _ _) ||
refine (simplification_existT1 _ _ _ _ _ _ _ _)
| ?x = ?y -> _ => (* variables case *)
(let hyp := fresh in intros hyp ;
move hyp before x ;
generalize dependent x ; refine (solution_left _ _ _ _) ; intros until 0) ||
(let hyp := fresh in intros hyp ;
move hyp before y ;
generalize dependent y ; refine (solution_right _ _ _ _) ; intros until 0)
| @eq ?A ?t ?u -> ?P => apply (noConfusion (I:=A) P)
| ?f ?x = ?g ?y -> _ => let H := fresh in progress (intros H ; injection H ; clear H)
| ?t = ?u -> _ => let hyp := fresh in
intros hyp ; elimtype False ; discriminate
| ?x = ?y -> _ => let hyp := fresh in
intros hyp ; (try (clear hyp ; (* If non dependent, don't clear it! *) fail 1)) ;
case hyp ; clear hyp
| block_dep_elim ?T => fail 1 (* Do not put any part of the rhs in the hyps *)
| _ => intro
end.
Ltac simplify_one_dep_elim :=
match goal with
| [ |- ?gl ] => simplify_one_dep_elim_term gl
end.
(** Repeat until no progress is possible. By construction, it should leave the goal with
no remaining equalities generated by the [generalize_eqs] tactic. *)
Ltac simplify_dep_elim := repeat simplify_one_dep_elim.
(** To dependent elimination on some hyp. *)
Ltac depelim id :=
generalize_eqs id ; destruct id ; simplify_dep_elim.
(** Do dependent elimination of the last hypothesis, but not simplifying yet
(used internally). *)
Ltac destruct_last :=
on_last_hyp ltac:(fun id => simpl in id ; generalize_eqs id ; destruct id).
(** The rest is support tactics for the [Equations] command. *)
(** Notation for inaccessible patterns. *)
Definition inaccessible_pattern {A : Type} (t : A) := t.
Notation "?( t )" := (inaccessible_pattern t).
(** To handle sections, we need to separate the context in two parts:
variables introduced by the section and the rest. We introduce a dummy variable
between them to indicate that. *)
CoInductive end_of_section := the_end_of_the_section.
Ltac set_eos := let eos := fresh "eos" in
assert (eos:=the_end_of_the_section).
(** We have a specialized [reverse_local] tactic to reverse the goal until the begining of the
section variables *)
Ltac reverse_local :=
match goal with
| [ H : ?T |- _ ] =>
match T with
| end_of_section => idtac | _ => revert H ; reverse_local end
| _ => idtac
end.
(** Do as much as possible to apply a method, trying to get the arguments right.
!!Unsafe!! We use [auto] for the [_nocomp] variant of [Equations], in which case some
non-dependent arguments of the method can remain after [apply]. *)
Ltac simpl_intros m := ((apply m || refine m) ; auto) || (intro ; simpl_intros m).
(** Hopefully the first branch suffices. *)
Ltac try_intros m :=
solve [ intros ; unfold block_dep_elim ; refine m || apply m ] ||
solve [ unfold block_dep_elim ; simpl_intros m ].
(** To solve a goal by inversion on a particular target. *)
Ltac solve_empty target :=
do_nat target intro ; elimtype False ; destruct_last ; simplify_dep_elim.
Ltac simplify_method tac := repeat (tac || simplify_one_dep_elim) ; reverse_local.
(** Solving a method call: we can solve it by splitting on an empty family member
or we must refine the goal until the body can be applied. *)
Ltac solve_method rec :=
match goal with
| [ H := ?body : nat |- _ ] => subst H ; clear ; abstract (simplify_method idtac ; solve_empty body)
| [ H := [ ?body ] : ?T |- _ ] => clear H ; simplify_method ltac:(exact body) ; rec ; try_intros (body:T)
end.
(** Impossible cases, by splitting on a given target. *)
Ltac solve_split :=
match goal with
| [ |- let split := ?x : nat in _ ] => clear ; abstract (intros _ ; solve_empty x)
end.
(** If defining recursive functions, the prototypes come first. *)
Ltac intro_prototypes :=
match goal with
| [ |- Π x : _, _ ] => intro ; intro_prototypes
| _ => idtac
end.
Ltac introduce p :=
first [ match p with _ => idtac end (* Already there *)
| intros until p | intros ].
Ltac do_case p := introduce p ; (destruct p || elim_case p || (case p ; clear p)).
Ltac do_ind p := introduce p ; (induction p || elim_ind p).
Ltac dep_elimify := match goal with [ |- ?T ] => change (block_dep_elim T) end.
Ltac un_dep_elimify := unfold block_dep_elim in *.
Ltac case_last := dep_elimify ;
on_last_hyp ltac:(fun p =>
let ty := type of p in
match ty with
| ?x = ?x => revert p ; refine (simplification_K _ x _ _)
| ?x = ?y => revert p
| _ => simpl in p ; generalize_eqs p ; do_case p
end).
Ltac nonrec_equations :=
solve [solve_equations (case_last) (solve_method idtac)] || solve [ solve_split ]
|| fail "Unnexpected equations goal".
Ltac recursive_equations :=
solve [solve_equations (case_last) (solve_method ltac:intro)] || solve [ solve_split ]
|| fail "Unnexpected recursive equations goal".
(** The [equations] tactic is the toplevel tactic for solving goals generated
by [Equations]. *)
Ltac equations := set_eos ;
match goal with
| [ |- Π x : _, _ ] => intro ; recursive_equations
| _ => nonrec_equations
end.
(** The following tactics allow to do induction on an already instantiated inductive predicate
by first generalizing it and adding the proper equalities to the context, in a maner similar to
the BasicElim tactic of "Elimination with a motive" by Conor McBride. *)
(** The [do_depind] higher-order tactic takes an induction tactic as argument and an hypothesis
and starts a dependent induction using this tactic. *)
Ltac do_depind tac H :=
(try intros until H) ; dep_elimify ; generalize_eqs_vars H ; tac H ; simplify_dep_elim ; un_dep_elimify.
(** A variant where generalized variables should be given by the user. *)
Ltac do_depind' tac H :=
(try intros until H) ; dep_elimify ; generalize_eqs H ; tac H ; simplify_dep_elim ; un_dep_elimify.
(** Calls [destruct] on the generalized hypothesis, results should be similar to inversion.
By default, we don't try to generalize the hyp by its variable indices. *)
Tactic Notation "dependent" "destruction" ident(H) :=
do_depind' ltac:(fun hyp => do_case hyp) H.
Tactic Notation "dependent" "destruction" ident(H) "using" constr(c) :=
do_depind' ltac:(fun hyp => destruct hyp using c) H.
(** This tactic also generalizes the goal by the given variables before the induction. *)
Tactic Notation "dependent" "destruction" ident(H) "generalizing" ne_hyp_list(l) :=
do_depind' ltac:(fun hyp => revert l ; do_case hyp) H.
Tactic Notation "dependent" "destruction" ident(H) "generalizing" ne_hyp_list(l) "using" constr(c) :=
do_depind' ltac:(fun hyp => revert l ; destruct hyp using c) H.
(** Then we have wrappers for usual calls to induction. One can customize the induction tactic by
writting another wrapper calling do_depind. We suppose the hyp has to be generalized before
calling [induction]. *)
Tactic Notation "dependent" "induction" ident(H) :=
do_depind ltac:(fun hyp => do_ind hyp) H.
Tactic Notation "dependent" "induction" ident(H) "using" constr(c) :=
do_depind ltac:(fun hyp => induction hyp using c) H.
(** This tactic also generalizes the goal by the given variables before the induction. *)
Tactic Notation "dependent" "induction" ident(H) "generalizing" ne_hyp_list(l) :=
do_depind' ltac:(fun hyp => generalize l ; clear l ; do_ind hyp) H.
Tactic Notation "dependent" "induction" ident(H) "generalizing" ne_hyp_list(l) "using" constr(c) :=
do_depind' ltac:(fun hyp => generalize l ; clear l ; induction hyp using c) H.
Ltac simplify_IH_hyps := repeat
match goal with
| [ hyp : _ |- _ ] => specialize_hypothesis hyp
end.
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Write-back Mux ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// CPU's write-back stage of the pipeline ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_wbmux.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.3 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.2 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:23 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_wbmux(
// Clock and reset
clk, rst,
// Internal i/f
wb_freeze, rfwb_op,
muxin_a, muxin_b, muxin_c, muxin_d,
muxout, muxreg, muxreg_valid
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Internal i/f
//
input wb_freeze;
input [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
input [width-1:0] muxin_a;
input [width-1:0] muxin_b;
input [width-1:0] muxin_c;
input [width-1:0] muxin_d;
output [width-1:0] muxout;
output [width-1:0] muxreg;
output muxreg_valid;
//
// Internal wires and regs
//
reg [width-1:0] muxout;
reg [width-1:0] muxreg;
reg muxreg_valid;
//
// Registered output from the write-back multiplexer
//
always @(posedge clk or posedge rst) begin
if (rst) begin
muxreg <= #1 32'd0;
muxreg_valid <= #1 1'b0;
end
else if (!wb_freeze) begin
muxreg <= #1 muxout;
muxreg_valid <= #1 rfwb_op[0];
end
end
//
// Write-back multiplexer
//
always @(muxin_a or muxin_b or muxin_c or muxin_d or rfwb_op) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif
2'b00: muxout = muxin_a;
2'b01: begin
muxout = muxin_b;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_b %h", muxin_b);
// synopsys translate_on
`endif
end
2'b10: begin
muxout = muxin_c;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_c %h", muxin_c);
// synopsys translate_on
`endif
end
2'b11: begin
muxout = muxin_d + 32'h8;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" WBMUX: muxin_d %h", muxin_d + 4'h8);
// synopsys translate_on
`endif
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_1_V
`define SKY130_FD_SC_HDLL__A21O_1_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21o_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__INVLP_BEHAVIORAL_PP_V
/**
* invlp: Low Power Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__invlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_BEHAVIORAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_SYMBOL_V
`define SKY130_FD_SC_HVL__NAND3_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_SYMBOL_V
|
/*
--------------------------------------------------------------------------
Pegasus - Copyright (C) 2012 Gregory Matthew James.
This file is part of Pegasus.
Pegasus is free; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
Pegasus is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------
*/
/*
--------------------------------------------------------------------------
-- Project Code : pegasus
-- Module Name : pkt_ff_async
-- Author : mammenx
-- Associated modules: pkt_ff_async_mem, pkt_ff_rptr, pkt_ff_wptr
-- Function : The top module for pkt_ff_async.
--------------------------------------------------------------------------
*/
`timescale 1ns / 10ps
module pkt_ff_async #(WIDTH = 32, DEPTH = 128, MAX_NO_PKTS=2)
(
//--------------------- Misc Ports (Logic) -----------
input ingr_clk,
input ingr_rst_n,
input egr_clk,
input egr_rst_n,
//Ingress packet interface
input ingr_valid,
input ingr_sop,
input ingr_eop,
input [WIDTH-1:0] ingr_data,
output ingr_ready,
input ingr_error,
//Egress packet interface
output egr_valid,
output egr_sop,
output egr_eop,
output [WIDTH-1:0] egr_data,
input egr_ready,
output egr_error
//--------------------- Interfaces --------------------
);
//----------------------- Global parameters Declarations ------------------
localparam PTR_W = $clog2(DEPTH);
//----------------------- Input Declarations ------------------------------
//----------------------- Inout Declarations ------------------------------
//----------------------- Output Declarations -----------------------------
//----------------------- Output Register Declaration ---------------------
//----------------------- Internal Register Declarations ------------------
reg [PTR_W-1:0] credit_cnt_ingr_f;
reg credit_ingr_push_f;
reg [PTR_W-1:0] credit_cnt_egr_f;
//----------------------- Internal Wire Declarations ----------------------
wire [PTR_W-1:0] wptr_w;
wire [PTR_W-1:0] rptr_w;
wire data_ff_rd_en_c;
wire data_ff_wr_en_c;
wire credit_ff_full_w;
wire credit_ff_empty_w;
wire [PTR_W-1:0] credit_ff_rdata_w;
wire credit_egr_pop_c;
//----------------------- Internal Interface Declarations -----------------
//----------------------- FSM Declarations --------------------------------
//----------------------- Start of Code -----------------------------------
//Generate read/write signals for data fifo
assign data_ff_wr_en_c = ingr_valid & ingr_ready & ~ingr_error;
assign data_ff_rd_en_c = egr_valid & egr_ready;
pkt_ff_wptr u_wptr
(
.clk (ingr_clk),
.rst_n (ingr_rst_n),
.valid (ingr_valid),
.sop (ingr_sop),
.eop (ingr_eop),
.error (ingr_error),
.wptr (wptr_w)
);
defparam u_wptr.PTR_W = PTR_W;
pkt_ff_rptr u_rptr
(
.clk (egr_clk),
.rst_n (egr_rst_n),
.rd_en (data_ff_rd_en_c),
.rptr (rptr_w)
);
defparam u_rptr.PTR_W = PTR_W;
pkt_ff_async_mem u_mem
(
.data (ingr_data),
.rdaddress (rptr_w),
.rdclock (egr_clk),
.wraddress (wptr_w),
.wrclock (ingr_clk),
.wren (data_ff_wr_en_c),
.q (egr_data)
);
defparam u_mem.DWIDTH = WIDTH;
defparam u_mem.DEPTH = DEPTH;
/*
* Credit management logic
*/
always@(posedge ingr_clk, negedge ingr_rst_n)
begin
if(~ingr_rst_n)
begin
credit_cnt_ingr_f <= 0;
credit_ingr_push_f <= 0;
end
else
begin
if(ingr_valid & ingr_ready)
begin
if(ingr_sof)
begin
credit_cnt_ingr_f <= WIDTH;
end
else
begin
credit_cnt_ingr_f <= credit_cnt_ingr_f + WIDTH;
end
end
else
begin
credit_cnt_ingr_f <= credit_cnt_ingr_f;
end
credit_ingr_push_f <= ingr_valid & ingr_ready &
ingr_eof & ~ingr_error;
end
end
always@(posedge egr_clk, negedge egr_rst_n)
begin
if(~egr_rst_n)
begin
credit_cnt_egr_f <= 0;
end
else
begin
if(credit_cnt_egr_f == 0)
begin
if(~credit_ff_empty_w)
begin
credit_cnt_egr_f <= credit_ff_rdata_w;
end
end
else if(egr_ready)
begin
credit_cnt_egr_f <= credit_cnt_egr_f - WIDTH;
end
end
end
assign egr_valid = (credit_cnt_egr_f > 0) ? 1'b1 : 1'b0;
assign egr_sop = (credit_cnt_egr_f == credit_ff_rdata_w) ? ~credit_ff_empty_w : 1'b0;
assign egr_eop = (credit_cnt_egr_f <= WIDTH) ? egr_valid : 1'b0;
assign egr_error = 0;
assign credit_egr_pop_c = egr_eop & egr_ready;
assign ingr_ready = ~credit_ff_full_w;
credit_ff_async u_credit_ff
(
.aclr (~ingr_rst_n | ~egr_rst_n),
.data (credit_cnt_ingr_f),
.rdclk (egr_clk),
.rdreq (credit_egr_pop_c),
.wrclk (ingr_clk),
.wrreq (credit_ingr_push_f),
.q (credit_ff_rdata_w),
.rdempty (credit_ff_empty_w),
.wrfull (credit_ff_full_w)
);
defparam u_credit_ff.WIDTH = PTR_W;
defparam u_credit_ff.DEPTH = MAX_NO_PKTS;
endmodule // pkt_ff_async
/*
--------------------------------------------------------------------------
-- <Header>
-- <Log>
[28-06-2014 03:30:57 PM][mammenx] Moved to Verilog
[08-06-2014 04:16:44 PM][mammenx] Initial Commit
[28-05-14 20:18:21] [mammenx] Moved log section to bottom of file
--------------------------------------------------------------------------
*/
|
module ID_EX(input clk,
input reset,
input [1:0] WB_in,
input [1:0] M_in,
input [3:0] EX_in,
input [31:0] RDdata1_in,
input [31:0] RDdata2_in,
input [31:0] sign_extended_in,
input [4:0] Inst_25_to_21_in,
input [4:0] Inst_20_to_16_in,
input [4:0] Inst_15_to_11_in,
input [5:0] Inst_5_to_0_in,
input [31:0] pc_plus4_in,
input hold_i,
output reg[1:0] WB_out,
output reg[1:0] M_out,
output reg ALUSrc_out,
output reg [1:0] ALUOp_out,
output reg RegDst_out,
output reg[31:0] RDdata1_out,
output reg[31:0] RDdata2_out,
output reg[31:0] sign_extended_out,
output reg[4:0] Inst_25_to_21_out,
output reg[4:0] Inst_20_to_16_out,
output reg[4:0] Inst_15_to_11_out,
output reg[5:0] Inst_5_to_0_out);
always@(posedge reset)begin
WB_out = 0;
M_out = 0;
ALUSrc_out = 0;
ALUOp_out = 0;
RegDst_out = 0;
RDdata1_out = 0;
RDdata2_out = 0;
sign_extended_out = 0;
Inst_15_to_11_out = 0;
Inst_20_to_16_out = 0;
Inst_25_to_21_out = 0;
Inst_5_to_0_out = 0;
end
always@(posedge clk)begin
if(hold_i) begin
WB_out <= WB_out;
M_out <= M_out;
ALUSrc_out <= ALUSrc_out;
ALUOp_out <= ALUOp_out;
RegDst_out <= RegDst_out;
RDdata1_out <= RDdata1_out;
RDdata2_out <= RDdata2_out;
sign_extended_out <= sign_extended_out;
Inst_15_to_11_out <= Inst_15_to_11_out;
Inst_20_to_16_out <= Inst_20_to_16_out;
Inst_25_to_21_out <= Inst_25_to_21_out;
Inst_5_to_0_out <= Inst_5_to_0_out;
end
else begin
WB_out <= WB_in;
M_out <= M_in;
ALUSrc_out <= EX_in[0];
ALUOp_out <= EX_in[2:1];
RegDst_out <= EX_in[3];
RDdata1_out <= RDdata1_in;
RDdata2_out <= RDdata2_in;
sign_extended_out <= sign_extended_in;
Inst_15_to_11_out <= Inst_15_to_11_in;
Inst_20_to_16_out <= Inst_20_to_16_in;
Inst_25_to_21_out <= Inst_25_to_21_in;
Inst_5_to_0_out <= Inst_5_to_0_in;
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_src_fifo_inf #(
parameter ID_WIDTH = 3,
parameter DATA_WIDTH = 64,
parameter BEATS_PER_BURST_WIDTH = 4)(
input clk,
input resetn,
input enable,
output enabled,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input eot,
output bl_valid,
input bl_ready,
output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,
input en,
input [DATA_WIDTH-1:0] din,
output reg overflow,
input sync,
output xfer_req,
output fifo_valid,
output [DATA_WIDTH-1:0] fifo_data,
output fifo_last,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start
);
wire ready;
wire valid;
assign enabled = enable;
assign valid = en & ready;
always @(posedge clk)
begin
if (enable) begin
overflow <= en & ~ready;
end else begin
overflow <= en;
end
end
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.bl_valid(bl_valid),
.bl_ready(bl_ready),
.measured_last_burst_length(measured_last_burst_length),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.req_sync_transfer_start(req_sync_transfer_start),
.req_xlast(1'b0),
.s_axi_ready(ready),
.s_axi_valid(valid),
.s_axi_data(din),
.s_axi_sync(sync),
.s_axi_last(1'b0),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data),
.m_axi_last(fifo_last)
);
endmodule
|
`default_nettype none
//---------------------------------------------------------------------
//-- --
//-- Company: University of Bonn --
//-- Engineer: John Bieling --
//-- --
//---------------------------------------------------------------------
//-- --
//-- Copyright (C) 2015 John Bieling --
//-- --
//-- This program is free software; you can redistribute it and/or --
//-- modify it under the terms of the GNU General Public License as --
//-- published by the Free Software Foundation; either version 3 of --
//-- the License, or (at your option) any later version. --
//-- --
//-- This program is distributed in the hope that it will be useful, --
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
//-- GNU General Public License for more details. --
//-- --
//-- You should have received a copy of the GNU General Public --
//-- License along with this program; if not, see --
//-- <http://www.gnu.org/licenses>. --
//-- --
//---------------------------------------------------------------------
module encode_96bit_pattern (edgechoice,enable,d,CLK200,CLK400,code,tdc_hit,scaler_hit);
genvar i;
parameter encodedbits = 9; //including hit
input wire CLK200;
input wire CLK400;
input wire [95:0] d;
input wire edgechoice;
input wire enable;
output reg [encodedbits-1:0] code;
output reg tdc_hit;
output reg scaler_hit;
//0. stage - pipe and order in groups of 4
generate
for (i=0; i < 24; i=i+1) begin : STAGE0 //i = 0,...,23
reg [3:0] pattern;
always@(posedge CLK400)
begin
if (edgechoice == 1'b0) pattern <= d[4*i+3:4*i+0];
else pattern <= ~d[4*i+3:4*i+0];
end
end
endgenerate
//1. stage - encode pattern to addr
generate
for (i=0; i < 24; i=i+1) begin : STAGE1 //i = 0,...,23
reg [1:0] addr;
reg b1111;
reg b0000;
always@(posedge CLK400)
begin
//1. look into each group of four and search for the leading edge and encode 4bit pattern to 2bit LE information
//-- b1111 and b0000 are used later: each valid LE must be followed by !b'0000 and 4'b1111
if (STAGE0[i].pattern == 4'b1111) b1111 <= 1'b1; else b1111 <= 1'b0;
if (STAGE0[i].pattern == 4'b0000) b0000 <= 1'b1; else b0000 <= 1'b0;
case (STAGE0[i].pattern)
//1. valid (but only if followed by !b'0000 and 4'b1111)
4'b1111: begin addr <= 2'b11; end
4'b1110: begin addr <= 2'b11; end
4'b1101: begin addr <= 2'b11; end
4'b1100: begin addr <= 2'b11; end
4'b1011: begin addr <= 2'b11; end
4'b1010: begin addr <= 2'b11; end
4'b1001: begin addr <= 2'b11; end
4'b1000: begin addr <= 2'b11; end
//2. valid (but only if followed by !b'0000 and 4'b1111)
4'b0111: begin addr <= 2'b10; end
4'b0110: begin addr <= 2'b10; end
4'b0101: begin addr <= 2'b10; end
4'b0100: begin addr <= 2'b10; end
//3. valid (but only if followed by !b'0000 and 4'b1111)
4'b0011: begin addr <= 2'b01; end
4'b0010: begin addr <= 2'b01; end
//4. valid (but only if followed by !b'0000 and 4'b1111)
4'b0001: begin addr <= 2'b00; end
//invalid
4'b0000: begin addr <= 2'b00; end
endcase
end
end
endgenerate
//-- 2. stage - a valid LE is none + some + some + all
// - shift index by TWO and remove two first and last group
generate
for (i=0; i < 21; i=i+1) begin : STAGE2 //i = 0,...,20
reg [1:0] addr;
reg valid;
always@(posedge CLK400)
begin
addr <= STAGE1[i+2].addr;
if (STAGE1[i+3].b0000 == 1'b1 && STAGE1[i+2].b0000 == 1'b0 && STAGE1[i+1].b0000 == 1'b0 && STAGE1[i].b1111 == 1'b1)
valid <= 1'b1;
else
valid <= 1'b0;
end
end
endgenerate
//-- 3. stage - mux - first hit wins (21 groups left, cannot simply divide by two)
generate
for (i=0; i < 11; i=i+1) begin : STAGE3 //i = 0,...,10
reg valid;
reg [2:0] addr;
if (i==10) begin
always@(posedge CLK400)
begin
valid <= STAGE2[20].valid;
addr <= {1'b0,STAGE2[20].addr};
end
end else begin
always@(posedge CLK400)
begin
valid <= STAGE2[2*i+1].valid || STAGE2[2*i+0].valid;
if (STAGE2[2*i+1].valid == 1'b1) addr <= {1'b1,STAGE2[2*i+1].addr};
else addr <= {1'b0,STAGE2[2*i+0].addr};
end
end
end
endgenerate
//-- 4. stage - mux - first hit wins (11 groups left, cannot simply divide by two)
generate
for (i=0; i < 6; i=i+1) begin : STAGE4 //i = 0,...,5
reg valid;
reg [3:0] addr;
if (i==5) begin
always@(posedge CLK400)
begin
valid <= STAGE3[10].valid;
addr <= {1'b0,STAGE3[10].addr};
end
end else begin
always@(posedge CLK400)
begin
valid <= STAGE3[2*i+1].valid || STAGE3[2*i+0].valid;
if (STAGE3[2*i+1].valid == 1'b1) addr <= {1'b1,STAGE3[2*i+1].addr};
else addr <= {1'b0,STAGE3[2*i+0].addr};
end
end
end
endgenerate
//-- 5. stage - mux again - first hit wins
generate
for (i=0; i < 3; i=i+1) begin : STAGE5 //i = 0,...,2
reg valid;
reg [4:0] addr;
always@(posedge CLK400)
begin
//first hit wins
valid <= STAGE4[2*i+1].valid || STAGE4[2*i+0].valid;
if (STAGE4[2*i+1].valid == 1'b1) addr <= {1'b1,STAGE4[2*i+1].addr};
else addr <= {1'b0,STAGE4[2*i+0].addr};
end
end
endgenerate
//-- 6. stage - we have 3 groups left
// - if a group is valid, there is a LE somewhere inside the group (addr of that group knows where)
reg [4:0] addr_2;
reg [4:0] addr_1;
reg [4:0] addr_0;
reg [6:0] exclusive_addr_2;
reg [6:0] exclusive_addr_1;
reg [6:0] exclusive_addr_0;
reg [2:0] hitmap;
reg [1:0] lowhit;
reg hit;
reg hit_2A;
reg hit_2B;
reg [6:0] addr_2A;
reg [6:0] addr_2B;
reg Transition400_hit_A;
reg Transition400_hit_B;
reg [6:0] Transition400_addr_A;
reg [6:0] Transition400_addr_B;
always@(posedge CLK400)
begin
//generate hitmap for final mux (reduce signals) and enforce a double hit protection - he should pack this into LUT6
if (STAGE5[2].valid == 1'b1 && lowhit[1] == 1'b0) begin hitmap <= 3'b110; lowhit <= 2'b00; end else
if (STAGE5[1].valid == 1'b1 && lowhit[0] == 1'b0) begin hitmap <= 3'b101; lowhit <= 2'b10; end else
if (STAGE5[0].valid == 1'b1) begin hitmap <= 3'b100; lowhit <= 2'b11; end else
begin hitmap <= 3'b000; lowhit <= 2'b00; end
//pipe addr parallel to creating hitmap
//addr_3 <= STAGE5[3].addr;
addr_2 <= STAGE5[2].addr;
addr_1 <= STAGE5[1].addr;
addr_0 <= STAGE5[0].addr;
//final "mux" - set all addr to zero, except the one which wins, also add group addr
if (hitmap == 3'b110) exclusive_addr_2 <= {2'b10,addr_2}; else exclusive_addr_2 <= 0;
if (hitmap == 3'b101) exclusive_addr_1 <= {2'b01,addr_1}; else exclusive_addr_1 <= 0;
if (hitmap == 3'b100) exclusive_addr_0 <= {2'b00,addr_0}; else exclusive_addr_0 <= 0;
hit <= hitmap[2];
//hit and exclusive_addr are in phase,
//store this and the last hit result, CLK1 will check both and will take the first one
hit_2A <= hit;
addr_2A <= {exclusive_addr_2 | exclusive_addr_1 | exclusive_addr_0};
hit_2B <= hit_2A;
addr_2B <= addr_2A;
Transition400_hit_A <= hit_2A;
Transition400_hit_B <= hit_2B;
Transition400_addr_A <= addr_2A;
Transition400_addr_B <= addr_2B;
end
reg Transition200_hit_A;
reg Transition200_hit_B;
reg [6:0] Transition200_addr_A;
reg [6:0] Transition200_addr_B;
//cross clock
always@(posedge CLK200)
begin
//just copy across clock domain
Transition200_hit_A <= Transition400_hit_A;
Transition200_hit_B <= Transition400_hit_B;
Transition200_addr_A <= Transition400_addr_A;
Transition200_addr_B <= Transition400_addr_B;
//take the first one
if (Transition200_hit_B == 1'b1) begin
scaler_hit <= Transition200_hit_B;
tdc_hit <= Transition200_hit_B & enable;
code <= {Transition200_hit_B & enable,1'b1,Transition200_addr_B};
end else begin
scaler_hit <= Transition200_hit_A;
tdc_hit <= Transition200_hit_A & enable;
code <= {Transition200_hit_A & enable,1'b0,Transition200_addr_A};
end
end
endmodule
|
(** * Hoare2: Hoare Logic, Part II *)
Require Export Hoare.
(* ####################################################### *)
(** * Decorated Programs *)
(** The beauty of Hoare Logic is that it is _compositional_ --
the structure of proofs exactly follows the structure of programs.
This suggests that we can record the essential ideas of a proof
informally (leaving out some low-level calculational details) by
decorating programs with appropriate assertions around each
statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness. *)
(** For example, here is a complete decorated program: *)
(**
{{ True }} ->>
{{ m = m }}
X ::= m;;
{{ X = m }} ->>
{{ X = m /\ p = p }}
Z ::= p;
{{ X = m /\ Z = p }} ->>
{{ Z - X = p - m }}
WHILE X <> 0 DO
{{ Z - X = p - m /\ X <> 0 }} ->>
{{ (Z - 1) - (X - 1) = p - m }}
Z ::= Z - 1;;
{{ Z - (X - 1) = p - m }}
X ::= X - 1
{{ Z - X = p - m }}
END;
{{ Z - X = p - m /\ ~ (X <> 0) }} ->>
{{ Z = p - m }}
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally consistent_ with its accompanying assertions in the
following sense: *)
(**
- [SKIP] is locally consistent if its precondition and
postcondition are the same:
{{ P }}
SKIP
{{ P }}
*)
(**
- The sequential composition of [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1] is
locally consistent (with respect to [P] and [Q]) and [c2] is
locally consistent (with respect to [Q] and [R]):
{{ P }}
c1;;
{{ Q }}
c2
{{ R }}
*)
(**
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
{{ P [X |-> a] }}
X ::= a
{{ P }}
*)
(**
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then"
branch is locally consistent (with respect to [P /\ b] and [Q])
and its "else" branch is locally consistent (with respect to
[P /\ ~b] and [Q]):
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
{{ Q }}
*)
(**
- A while loop with precondition [P] is locally consistent if its
postcondition is [P /\ ~b] and if the pre- and postconditions of
its body are exactly [P /\ b] and [P]:
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
*)
(**
- A pair of assertions separated by [->>] is locally consistent if
the first implies the second (in all states):
{{ P }} ->>
{{ P' }}
This corresponds to the application of [hoare_consequence] and
is the only place in a decorated program where checking if
decorations are correct is not fully mechanical and syntactic,
but involves logical and/or arithmetic reasoning.
*)
(** We have seen above how _verifying_ the correctness of a
given proof involves checking that every single command is locally
consistent with the accompanying assertions. If we are instead
interested in _finding_ a proof for a given specification we need
to discover the right assertions. This can be done in an almost
automatic way, with the exception of finding loop invariants,
which is the subject of in the next section. In the reminder of
this section we explain in detail how to construct decorations for
several simple programs that don't involve non-trivial loop
invariants. *)
(* ####################################################### *)
(** ** Example: Swapping Using Addition and Subtraction *)
(** Here is a program that swaps the values of two variables using
addition and subtraction (instead of by assigning to a temporary
variable).
X ::= X + Y;;
Y ::= X - Y;;
X ::= X - Y
We can prove using decorations that this program is correct --
i.e., it always swaps the values of variables [X] and [Y]. *)
(**
(1) {{ X = m /\ Y = n }} ->>
(2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }}
X ::= X + Y;;
(3) {{ X - (X - Y) = n /\ X - Y = m }}
Y ::= X - Y;;
(4) {{ X - Y = n /\ Y = m }}
X ::= X - Y
(5) {{ X = n /\ Y = m }}
The decorations were constructed as follows:
- We begin with the undecorated program (the unnumbered lines).
- We then add the specification -- i.e., the outer
precondition (1) and postcondition (5). In the precondition we
use auxiliary variables (parameters) [m] and [n] to remember
the initial values of variables [X] and respectively [Y], so
that we can refer to them in the postcondition (5).
- We work backwards mechanically starting from (5) all the way
to (2). At each step, we obtain the precondition of the
assignment from its postcondition by substituting the assigned
variable with the right-hand-side of the assignment. For
instance, we obtain (4) by substituting [X] with [X - Y]
in (5), and (3) by substituting [Y] with [X - Y] in (4).
- Finally, we verify that (1) logically implies (2) -- i.e.,
that the step from (1) to (2) is a valid use of the law of
consequence. For this we substitute [X] by [m] and [Y] by [n]
and calculate as follows:
(m + n) - ((m + n) - n) = n /\ (m + n) - n = m
(m + n) - m = n /\ m = m
n = n /\ m = m
(Note that, since we are working with natural numbers, not
fixed-size machine integers, we don't need to worry about the
possibility of arithmetic overflow anywhere in this argument.)
*)
(* ####################################################### *)
(** ** Example: Simple Conditionals *)
(** Here is a simple decorated program using conditionals:
(1) {{True}}
IFB X <= Y THEN
(2) {{True /\ X <= Y}} ->>
(3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}}
Z ::= Y - X
(4) {{Z + X = Y \/ Z + Y = X}}
ELSE
(5) {{True /\ ~(X <= Y) }} ->>
(6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}}
Z ::= X - Y
(7) {{Z + X = Y \/ Z + Y = X}}
FI
(8) {{Z + X = Y \/ Z + Y = X}}
These decorations were constructed as follows:
- We start with the outer precondition (1) and postcondition (8).
- We follow the format dictated by the [hoare_if] rule and copy the
postcondition (8) to (4) and (7). We conjoin the precondition (1)
with the guard of the conditional to obtain (2). We conjoin (1)
with the negated guard of the conditional to obtain (5).
- In order to use the assignment rule and obtain (3), we substitute
[Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y]
in (7).
- Finally, we verify that (2) implies (3) and (5) implies (6). Both
of these implications crucially depend on the ordering of [X] and
[Y] obtained from the guard. For instance, knowing that [X <= Y]
ensures that subtracting [X] from [Y] and then adding back [X]
produces [Y], as required by the first disjunct of (3). Similarly,
knowing that [~(X <= Y)] ensures that subtracting [Y] from [X] and
then adding back [Y] produces [X], as needed by the second
disjunct of (6). Note that [n - m + m = n] does _not_ hold for
arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 =
5]). *)
(** **** Exercise: 2 stars (if_minus_plus_reloaded) *)
(** Fill in valid decorations for the following program:
{{ True }}
IFB X <= Y THEN
{{ True /\ X <= Y }} ->>
{{ Y = X + (Y - X) }}
Z ::= Y - X
{{ Y = X + Z }}
ELSE
{{ True /\ ~ (X <= Y) }} ->>
{{ X + Z = X + Z }}
Y ::= X + Z
{{ Y = X + Z }}
FI
{{ Y = X + Z }}
*)
(* ####################################################### *)
(** ** Example: Reduce to Zero (Trivial Loop) *)
(** Here is a [WHILE] loop that is so simple it needs no
invariant (i.e., the invariant [True] will do the job).
(1) {{ True }}
WHILE X <> 0 DO
(2) {{ True /\ X <> 0 }} ->>
(3) {{ True }}
X ::= X - 1
(4) {{ True }}
END
(5) {{ True /\ X = 0 }} ->>
(6) {{ X = 0 }}
The decorations can be constructed as follows:
- Start with the outer precondition (1) and postcondition (6).
- Following the format dictated by the [hoare_while] rule, we copy
(1) to (4). We conjoin (1) with the guard to obtain (2) and with
the negation of the guard to obtain (5). Note that, because the
outer postcondition (6) does not syntactically match (5), we need a
trivial use of the consequence rule from (5) to (6).
- Assertion (3) is the same as (4), because [X] does not appear in
[4], so the substitution in the assignment rule is trivial.
- Finally, the implication between (2) and (3) is also trivial.
*)
(** From this informal proof, it is easy to read off a formal proof
using the Coq versions of the Hoare rules. Note that we do _not_
unfold the definition of [hoare_triple] anywhere in this proof --
the idea is to use the Hoare rules as a "self-contained" logic for
reasoning about programs. *)
Definition reduce_to_zero' : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct' :
{{fun st => True}}
reduce_to_zero'
{{fun st => st X = 0}}.
Proof.
unfold reduce_to_zero'.
(* First we need to transform the postcondition so
that hoare_while will apply. *)
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
(* Need to massage precondition before [hoare_asgn] applies *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Proving trivial implication (2) ->> (3) *)
intros st [HT Hbp]. unfold assn_sub. apply I.
Case "Invariant and negated guard imply postcondition".
intros st [Inv GuardFalse].
unfold bassn in GuardFalse. simpl in GuardFalse.
(* SearchAbout helps to find the right lemmas *)
SearchAbout [not true].
rewrite not_true_iff_false in GuardFalse.
SearchAbout [negb false].
rewrite negb_false_iff in GuardFalse.
SearchAbout [beq_nat true].
apply beq_nat_true in GuardFalse.
apply GuardFalse. Qed.
(* ####################################################### *)
(** ** Example: Division *)
(** The following Imp program calculates the integer division and
remainder of two numbers [m] and [n] that are arbitrary constants
in the program.
X ::= m;;
Y ::= 0;;
WHILE n <= X DO
X ::= X - n;;
Y ::= Y + 1
END;
In other words, if we replace [m] and [n] by concrete numbers and
execute the program, it will terminate with the variable [X] set
to the remainder when [m] is divided by [n] and [Y] set to the
quotient. *)
(** In order to give a specification to this program we need to
remember that dividing [m] by [n] produces a reminder [X] and a
quotient [Y] so that [n * Y + X = m /\ X < n].
It turns out that we get lucky with this program and don't have to
think very hard about the loop invariant: the invariant is the
just first conjunct [n * Y + X = m], so we use that to decorate
the program.
(1) {{ True }} ->>
(2) {{ n * 0 + m = m }}
X ::= m;;
(3) {{ n * 0 + X = m }}
Y ::= 0;;
(4) {{ n * Y + X = m }}
WHILE n <= X DO
(5) {{ n * Y + X = m /\ n <= X }} ->>
(6) {{ n * (Y + 1) + (X - n) = m }}
X ::= X - n;;
(7) {{ n * (Y + 1) + X = m }}
Y ::= Y + 1
(8) {{ n * Y + X = m }}
END
(9) {{ n * Y + X = m /\ X < n }}
Assertions (4), (5), (8), and (9) are derived mechanically from
the invariant and the loop's guard. Assertions (8), (7), and (6)
are derived using the assignment rule going backwards from (8) to
(6). Assertions (4), (3), and (2) are again backwards applications
of the assignment rule.
Now that we've decorated the program it only remains to check that
the two uses of the consequence rule are correct -- i.e., that (1)
implies (2) and that (5) implies (6). This is indeed the case, so
we have a valid decorated program.
*)
(* ####################################################### *)
(** * Finding Loop Invariants *)
(** Once the outermost precondition and postcondition are chosen, the
only creative part in verifying programs with Hoare Logic is
finding the right loop invariants. The reason this is difficult
is the same as the reason that doing inductive mathematical proofs
requires creativity: strengthening the loop invariant (or the
induction hypothesis) means that you have a stronger assumption to
work with when trying to establish the postcondition of the loop
body (complete the induction step of the proof), but it also means
that the loop body postcondition itself is harder to prove!
This section is dedicated to teaching you how to approach the
challenge of finding loop invariants using a series of examples
and exercises. *)
(** ** Example: Slow Subtraction *)
(** The following program subtracts the value of [X] from the value of
[Y] by repeatedly decrementing both [X] and [Y]. We want to verify its
correctness with respect to the following specification:
{{ X = m /\ Y = n }}
WHILE X <> 0 DO
Y ::= Y - 1;;
X ::= X - 1
END
{{ Y = n - m }}
To verify this program we need to find an invariant [I] for the
loop. As a first step we can leave [I] as an unknown and build a
_skeleton_ for the proof by applying backward the rules for local
consistency. This process leads to the following skeleton:
(1) {{ X = m /\ Y = n }} ->> (a)
(2) {{ I }}
WHILE X <> 0 DO
(3) {{ I /\ X <> 0 }} ->> (c)
(4) {{ I[X |-> X-1][Y |-> Y-1] }}
Y ::= Y - 1;;
(5) {{ I[X |-> X-1] }}
X ::= X - 1
(6) {{ I }}
END
(7) {{ I /\ ~(X <> 0) }} ->> (b)
(8) {{ Y = n - m }}
By examining this skeleton, we can see that any valid [I] will
have to respect three conditions:
- (a) it must be weak enough to be implied by the loop's
precondition, i.e. (1) must imply (2);
- (b) it must be strong enough to imply the loop's postcondition,
i.e. (7) must imply (8);
- (c) it must be preserved by one iteration of the loop, i.e. (3)
must imply (4). *)
(** These conditions are actually independent of the particular
program and specification we are considering. Indeed, every loop
invariant has to satisfy them. One way to find an invariant that
simultaneously satisfies these three conditions is by using an
iterative process: start with a "candidate" invariant (e.g. a
guess or a heuristic choice) and check the three conditions above;
if any of the checks fails, try to use the information that we get
from the failure to produce another (hopefully better) candidate
invariant, and repeat the process.
For instance, in the reduce-to-zero example above, we saw that,
for a very simple loop, choosing [True] as an invariant did the
job. So let's try it again here! I.e., let's instantiate [I] with
[True] in the skeleton above see what we get...
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ True }}
WHILE X <> 0 DO
(3) {{ True /\ X <> 0 }} ->> (c - OK)
(4) {{ True }}
Y ::= Y - 1;;
(5) {{ True }}
X ::= X - 1
(6) {{ True }}
END
(7) {{ True /\ X = 0 }} ->> (b - WRONG!)
(8) {{ Y = n - m }}
While conditions (a) and (c) are trivially satisfied,
condition (b) is wrong, i.e. it is not the case that (7) [True /\
X = 0] implies (8) [Y = n - m]. In fact, the two assertions are
completely unrelated and it is easy to find a counterexample (say,
[Y = X = m = 0] and [n = 1]).
If we want (b) to hold, we need to strengthen the invariant so
that it implies the postcondition (8). One very simple way to do
this is to let the invariant _be_ the postcondition. So let's
return to our skeleton, instantiate [I] with [Y = n - m], and
check conditions (a) to (c) again.
(1) {{ X = m /\ Y = n }} ->> (a - WRONG!)
(2) {{ Y = n - m }}
WHILE X <> 0 DO
(3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!)
(4) {{ Y - 1 = n - m }}
Y ::= Y - 1;;
(5) {{ Y = n - m }}
X ::= X - 1
(6) {{ Y = n - m }}
END
(7) {{ Y = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
This time, condition (b) holds trivially, but (a) and (c) are
broken. Condition (a) requires that (1) [X = m /\ Y = n]
implies (2) [Y = n - m]. If we substitute [Y] by [n] we have to
show that [n = n - m] for arbitrary [m] and [n], which does not
hold (for instance, when [m = n = 1]). Condition (c) requires that
[n - m - 1 = n - m], which fails, for instance, for [n = 1] and [m =
0]. So, although [Y = n - m] holds at the end of the loop, it does
not hold from the start, and it doesn't hold on each iteration;
it is not a correct invariant.
This failure is not very surprising: the variable [Y] changes
during the loop, while [m] and [n] are constant, so the assertion
we chose didn't have much chance of being an invariant!
To do better, we need to generalize (8) to some statement that is
equivalent to (8) when [X] is [0], since this will be the case
when the loop terminates, and that "fills the gap" in some
appropriate way when [X] is nonzero. Looking at how the loop
works, we can observe that [X] and [Y] are decremented together
until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially,
after one iteration of the loop we obtain [X = 1] and [Y = 4];
after two iterations [X = 0] and [Y = 3]; and then the loop stops.
Notice that the difference between [Y] and [X] stays constant
between iterations; initially, [Y = n] and [X = m], so this
difference is always [n - m]. So let's try instantiating [I] in
the skeleton above with [Y - X = n - m].
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ Y - X = n - m }}
WHILE X <> 0 DO
(3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK)
(4) {{ (Y - 1) - (X - 1) = n - m }}
Y ::= Y - 1;;
(5) {{ Y - (X - 1) = n - m }}
X ::= X - 1
(6) {{ Y - X = n - m }}
END
(7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
Success! Conditions (a), (b) and (c) all hold now. (To
verify (c), we need to check that, under the assumption that [X <>
0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all
natural numbers [X] and [Y].) *)
(* ####################################################### *)
(** ** Exercise: Slow Assignment *)
(** **** Exercise: 2 stars (slow_assignment) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until
it hits [0], incrementing [Y] at each step. Here is a program that
implements this idea:
{{ X = m }}
Y ::= 0;;
WHILE X <> 0 DO
X ::= X - 1;;
Y ::= Y + 1
END
{{ Y = m }}
Write an informal decorated program showing that this is correct. *)
(*
{{ X = m }} ->>
{{ X + 0 = m }}
Y ::= 0;;
{{ X + Y = m }}
WHILE X <> 0 DO
{{ X + Y = m /\ X <> 0 }} ->>
{{ (X - 1) + (Y + 1) = m }}
X ::= X - 1;;
{{ X + (Y + 1) = m }}
Y ::= Y + 1
{{ X + Y = m }}
END
{{ X + Y = m /\ X = 0 }} ->>
{{ Y = m }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Slow Addition *)
(** **** Exercise: 3 stars, optional (add_slowly_decoration) *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z.
WHILE X <> 0 DO
Z ::= Z + 1;;
X ::= X - 1
END
Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(*
{{ X = m /\ Z = n }} ->>
{{ X + Z = m + n }}
WHILE X <> 0 DO
{{ X + Z = m + n /\ X <> 0}} ->>
{{ (X - 1) + (Z + 1) = m + n }}
Z ::= Z + 1;;
{{ (X - 1) + Z = m + n }}
X ::= X - 1
{{ X + Z = m + n }}
END
{{ X + Z = m + n /\ X = 0 }} ->>
{{ Z = m + n }}
*)
(** [] *)
(* ####################################################### *)
(** ** Example: Parity *)
(** Here is a cute little program for computing the parity of the
value initially stored in [X] (due to Daniel Cristofani).
{{ X = m }}
WHILE 2 <= X DO
X ::= X - 2
END
{{ X = parity m }}
The mathematical [parity] function used in the specification is
defined in Coq as follows: *)
Fixpoint parity x :=
match x with
| 0 => 0
| 1 => 1
| S (S x') => parity x'
end.
(** The postcondition does not hold at the beginning of the loop,
since [m = parity m] does not hold for an arbitrary [m], so we
cannot use that as an invariant. To find an invariant that works,
let's think a bit about what this loop does. On each iteration it
decrements [X] by [2], which preserves the parity of [X]. So the
parity of [X] does not change, i.e. it is invariant. The initial
value of [X] is [m], so the parity of [X] is always equal to the
parity of [m]. Using [parity X = parity m] as an invariant we
obtain the following decorated program:
{{ X = m }} ->> (a - OK)
{{ parity X = parity m }}
WHILE 2 <= X DO
{{ parity X = parity m /\ 2 <= X }} ->> (c - OK)
{{ parity (X-2) = parity m }}
X ::= X - 2
{{ parity X = parity m }}
END
{{ parity X = parity m /\ X < 2 }} ->> (b - OK)
{{ X = parity m }}
With this invariant, conditions (a), (b), and (c) are all
satisfied. For verifying (b), we observe that, when [X < 2], we
have [parity X = X] (we can easily see this in the definition of
[parity]). For verifying (c), we observe that, when [2 <= X], we
have [parity X = parity (X-2)]. *)
(** **** Exercise: 3 stars, optional (parity_formal) *)
(** Translate this proof to Coq. Refer to the reduce-to-zero example
for ideas. You may find the following two lemmas useful: *)
Lemma parity_ge_2 : forall x,
2 <= x ->
parity (x - 2) = parity x.
Proof.
induction x; intro. reflexivity.
destruct x. inversion H. inversion H1.
simpl. rewrite <- minus_n_O. reflexivity.
Qed.
Lemma parity_lt_2 : forall x,
~ 2 <= x ->
parity (x) = x.
Proof.
intros. induction x. reflexivity. destruct x. reflexivity.
apply ex_falso_quodlibet. apply H. omega.
Qed.
Theorem parity_correct : forall m,
{{ fun st => st X = m }}
WHILE BLe (ANum 2) (AId X) DO
X ::= AMinus (AId X) (ANum 2)
END
{{ fun st => st X = parity m }}.
Proof.
intro m.
eapply hoare_consequence_post.
(* introduce the [I] *)
eapply hoare_consequence_pre with (fun st => parity (st X) = parity m).
apply hoare_while.
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, beval.
intros st [H1 H2].
apply ble_nat_true in H2. simpl in H2.
rewrite update_eq. simpl.
rewrite (parity_ge_2 (st X)); assumption.
intros st H1; subst; reflexivity.
unfold bassn, assn_sub, beval.
intros st [H1 H2].
SearchAbout [not true].
apply not_true_is_false in H2.
apply ble_nat_false in H2. simpl in H2.
rewrite (parity_lt_2 (st X)) in H1; assumption.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Example: Finding Square Roots *)
(** The following program computes the square root of [X]
by naive iteration:
{{ X=m }}
Z ::= 0;;
WHILE (Z+1)*(Z+1) <= X DO
Z ::= Z+1
END
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
*)
(** As above, we can try to use the postcondition as a candidate
invariant, obtaining the following decorated program:
(1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!)
(2) {{ 0*0 <= m /\ m<1*1 }}
Z ::= 0;;
(3) {{ Z*Z <= m /\ m<(Z+1)*(Z+1) }}
WHILE (Z+1)*(Z+1) <= X DO
(4) {{ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - WRONG!)
(5) {{ (Z+1)*(Z+1)<=m /\ m<(Z+2)*(Z+2) }}
Z ::= Z+1
(6) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
END
(7) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
(8) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This didn't work very well: both conditions (a) and (c) failed.
Looking at condition (c), we see that the second conjunct of (4)
is almost the same as the first conjunct of (5), except that (4)
mentions [X] while (5) mentions [m]. But note that [X] is never
assigned in this program, so we should have [X=m], but we didn't
propagate this information from (1) into the loop invariant.
Also, looking at the second conjunct of (8), it seems quite
hopeless as an invariant -- and we don't even need it, since we
can obtain it from the negation of the guard (third conjunct
in (7)), again under the assumption that [X=m].
So we now try [X=m /\ Z*Z <= m] as the loop invariant:
{{ X=m }} ->> (a - OK)
{{ X=m /\ 0*0 <= m }}
Z ::= 0;
{{ X=m /\ Z*Z <= m }}
WHILE (Z+1)*(Z+1) <= X DO
{{ X=m /\ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - OK)
{{ X=m /\ (Z+1)*(Z+1)<=m }}
Z ::= Z+1
{{ X=m /\ Z*Z<=m }}
END
{{ X=m /\ Z*Z<=m /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This works, since conditions (a), (b), and (c) are now all
trivially satisfied.
Very often, if a variable is used in a loop in a read-only
fashion (i.e., it is referred to by the program or by the
specification and it is not changed by the loop) it is necessary
to add the fact that it doesn't change to the loop invariant. *)
(* ####################################################### *)
(** ** Example: Squaring *)
(** Here is a program that squares [X] by repeated addition:
{{ X = m }}
Y ::= 0;;
Z ::= 0;;
WHILE Y <> X DO
Z ::= Z + X;;
Y ::= Y + 1
END
{{ Z = m*m }}
*)
(** The first thing to note is that the loop reads [X] but doesn't
change its value. As we saw in the previous example, in such cases
it is a good idea to add [X = m] to the invariant. The other thing
we often use in the invariant is the postcondition, so let's add
that too, leading to the invariant candidate [Z = m * m /\ X = m].
{{ X = m }} ->> (a - WRONG)
{{ 0 = m*m /\ X = m }}
Y ::= 0;;
{{ 0 = m*m /\ X = m }}
Z ::= 0;;
{{ Z = m*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - WRONG)
{{ Z+X = m*m /\ X = m }}
Z ::= Z + X;;
{{ Z = m*m /\ X = m }}
Y ::= Y + 1
{{ Z = m*m /\ X = m }}
END
{{ Z = m*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
Conditions (a) and (c) fail because of the [Z = m*m] part. While
[Z] starts at [0] and works itself up to [m*m], we can't expect
[Z] to be [m*m] from the start. If we look at how [Z] progesses
in the loop, after the 1st iteration [Z = m], after the 2nd
iteration [Z = 2*m], and at the end [Z = m*m]. Since the variable
[Y] tracks how many times we go through the loop, we derive the
new invariant candidate [Z = Y*m /\ X = m].
{{ X = m }} ->> (a - OK)
{{ 0 = 0*m /\ X = m }}
Y ::= 0;;
{{ 0 = Y*m /\ X = m }}
Z ::= 0;;
{{ Z = Y*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - OK)
{{ Z+X = (Y+1)*m /\ X = m }}
Z ::= Z + X;
{{ Z = (Y+1)*m /\ X = m }}
Y ::= Y + 1
{{ Z = Y*m /\ X = m }}
END
{{ Z = Y*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
This new invariant makes the proof go through: all three
conditions are easy to check.
It is worth comparing the postcondition [Z = m*m] and the [Z =
Y*m] conjunct of the invariant. It is often the case that one has
to replace auxiliary variabes (parameters) with variables -- or
with expressions involving both variables and parameters (like
[m - Y]) -- when going from postconditions to invariants. *)
(* ####################################################### *)
(** ** Exercise: Factorial *)
(** **** Exercise: 3 stars (factorial) *)
(** Recall that [n!] denotes the factorial of [n] (i.e. [n! =
1*2*...*n]). Here is an Imp program that calculates the factorial
of the number initially stored in the variable [X] and puts it in
the variable [Y]:
{{ X = m }}
Y ::= 1 ;;
WHILE X <> 0
DO
Y ::= Y * X ;;
X ::= X - 1
END
{{ Y = m! }}
Fill in the blanks in following decorated program:
{{ X = m }} ->>
{{ 1 * X! = m! }}
Y ::= 1;;
{{ Y * X! = m! }}
WHILE X <> 0
DO {{ Y * X! = m! /\ X <> 0 }} ->>
{{ (Y * X) * (X - 1)! = m! }}
Y ::= Y * X;;
{{ Y * (X - 1)! = m! }}
X ::= X - 1
{{ Y * X! = m! }}
END
{{ Y * X! = m! /\ X = 0 }} ->>
{{ Y = m! }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Min *)
(** **** Exercise: 3 stars (Min_Hoare) *)
(** Fill in valid decorations for the following program.
For the => steps in your annotations, you may rely (silently) on the
following facts about min
Lemma lemma1 : forall x y,
(x=0 \/ y=0) -> min x y = 0.
Lemma lemma2 : forall x y,
min (x-1) (y-1) = (min x y) - 1.
plus, as usual, standard high-school algebra.
{{ True }} ->>
{{ 0 + min a b = min a b }}
X ::= a;;
{{ 0 + min X b = min a b }}
Y ::= b;;
{{ 0 + min X Y = min a b }}
Z ::= 0;;
{{ Z + min X Y = min a b }}
WHILE (X <> 0 /\ Y <> 0) DO
{{ Z + min X Y = min a b /\ (X <> 0 /\ Y <> 0) }} ->>
{{ (Z + 1) + min (X - 1) (Y - 1) = min a b }}
X := X - 1;;
{{ (Z + 1) + min X (Y - 1) = min a b }}
Y := Y - 1;;
{{ (Z + 1) + min X Y = min a b }}
Z := Z + 1
{{ Z + min X Y = min a b }}
END
{{ Z + min X Y = min a b /\ (X = 0 \/ Y = 0) }} ->>
{{ Z = min a b }}
*)
(** **** Exercise: 3 stars (two_loops) *)
(** Here is a very inefficient way of adding 3 numbers:
X ::= 0;;
Y ::= 0;;
Z ::= c;;
WHILE X <> a DO
X ::= X + 1;;
Z ::= Z + 1
END;;
WHILE Y <> b DO
Y ::= Y + 1;;
Z ::= Z + 1
END
Show that it does what it should by filling in the blanks in the
following decorated program.
{{ True }} ->>
{{ c = c + 0 + 0 /\ 0 = 0 }}
X ::= 0;;
{{ c = c + X + 0 /\ 0 = 0 }}
Y ::= 0;;
{{ c = c + X + Y /\ Y = 0 }}
Z ::= c;;
{{ Z = c + X + Y /\ Y = 0 }}
WHILE X <> a DO
{{ Z = c + X + Y /\ Y = 0 /\ X <> a }} ->>
{{ Z + 1 = c + (X + 1) + Y /\ Y = 0 }}
X ::= X + 1;;
{{ Z + 1 = c + X + Y /\ Y = 0 }}
Z ::= Z + 1
{{ Z = c + X + Y /\ Y = 0 }}
END;;
{{ Z = c + X + Y /\ Y = 0 /\ X = a }} ->>
{{ Z = c + a + Y }}
WHILE Y <> b DO
{{ Z = c + a + Y /\ Y <> b }} ->>
{{ Z + 1 = c + a + (Y + 1) }}
Y ::= Y + 1;;
{{ Z + 1 = c + a + Y }}
Z ::= Z + 1
{{ Z = c + a + Y }}
END
{{ Z = c + a + Y /\ Y = b }} ->>
{{ Z = a + b + c }}
*)
(* ####################################################### *)
(** ** Exercise: Power Series *)
(** **** Exercise: 4 stars, optional (dpow2_down) *)
(** Here is a program that computes the series:
[1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1]
X ::= 0;;
Y ::= 1;;
Z ::= 1;;
WHILE X <> m DO
Z ::= 2 * Z;;
Y ::= Y + Z;;
X ::= X + 1
END
Write a decorated program for this. *)
(*
{{ True }} ->>
{{ 1 = 2^(0+1) - 1 /\ 1 = 2^0 }}
X ::= 0;;
{{ 1 = 2^(X+1) - 1 /\ 1 = 2^X }}
Y ::= 1;;
{{ Y = 2^(X+1) - 1 /\ 1 = 2^X }}
Z ::= 1;;
{{ Y = 2^(X+1) - 1 /\ Z = 2^X }}
WHILE X <> m DO
{{ Y = 2^(X+1) - 1 /\ Z = 2^X /\ X <> m }} ->>
{{ Y + 2*Z = 2^(X+2) - 1 /\ 2*Z = 2^(X+1) }}
Z ::= 2 * Z;;
{{ Y + Z = 2^(X+2) - 1 /\ Z = 2^(X+1) }}
Y ::= Y + Z;;
{{ Y = 2^(X+2) - 1 /\ Z = 2^(X+1) }}
X ::= X + 1
{{ Y = 2^(X+1) - 1 /\ Z = 2^X }}
END
{{ Y = 2^(X+1) - 1 /\ Z = 2^X /\ X = m }} ->>
{{ Y = 2^(m+1) - 1 }}
*)
(* ####################################################### *)
(** * Weakest Preconditions (Advanced) *)
(** Some Hoare triples are more interesting than others.
For example,
{{ False }} X ::= Y + 1 {{ X <= 5 }}
is _not_ very interesting: although it is perfectly valid, it
tells us nothing useful. Since the precondition isn't satisfied
by any state, it doesn't describe any situations where we can use
the command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (for a given
command and postcondition) is this one:
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if,
whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we have
[P' st] implies [P st] for all states [st]. *)
Definition is_wp P c Q :=
{{P}} c {{Q}} /\
forall P', {{P'}} c {{Q}} -> (P' ->> P).
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
executing [c]. *)
(** **** Exercise: 1 star, optional (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
1) {{ X = 5 }} SKIP {{ X = 5 }}
2) {{ Y + Z = 5 }} X ::= Y + Z {{ X = 5 }}
3) {{ True }} X ::= Y {{ X = Y }}
4) {{ (X = 0 /\ Z = 4) \/ (X <> 0 /\ W = 3) }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
5) {{ False }}
X ::= 5
{{ X = 0 }}
6) {{ True }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
*)
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (is_wp_formal) *)
(** Prove formally using the definition of [hoare_triple] that [Y <= 4]
is indeed the weakest precondition of [X ::= Y + 1] with respect to
postcondition [X <= 5]. *)
Theorem is_wp_example :
is_wp (fun st => st Y <= 4)
(X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5).
Proof.
unfold is_wp, hoare_triple.
split.
intros. inversion H; subst.
simpl. rewrite update_eq. omega.
intros P' H st HP.
remember (H st (update st X (st Y + 1))). clear Heql.
assert ((X ::= APlus (AId Y) (ANum 1)) / st
|| update st X (st Y + 1)) by
(apply E_Ass; reflexivity).
remember (l H0 HP). clear Heql0.
rewrite update_eq in l0. omega.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall Q X a,
is_wp (Q [X |-> a]) (X ::= a) Q.
Proof.
unfold is_wp, hoare_triple, assn_sub.
split.
intros; inversion H; subst; assumption.
intros P' H st HP'.
remember (H st (update st X (aeval st a))). clear Heqq.
assert ((X ::= a) / st || update st X (aeval st a)) by
(apply E_Ass; reflexivity).
apply q in H0; assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) *)
(** Show that your [havoc_pre] rule from the [himp_hoare] exercise
in the [Hoare] chapter returns the weakest precondition. *)
Module Himp2.
Import Himp.
Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id),
{{ P }} HAVOC X {{ Q }} ->
P ->> havoc_pre X Q.
Proof.
unfold havoc_pre, hoare_triple.
intros. intros st HP x.
remember (H st (update st X x)). clear Heqq.
assert ((HAVOC X) / st || update st X x) by apply E_Havoc.
apply q in H0; assumption.
Qed.
End Himp2.
(** [] *)
(* ####################################################### *)
(** * Formal Decorated Programs (Advanced) *)
(** The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple logical and algebraic calculations
showing that some assertions imply others. In this section, we
show that this informal presentation style can actually be made
completely formal and indeed that checking the validity of
decorated programs can mostly be automated. *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands with embedded assertions. We call the new
commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom
-> Assertion-> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}"
:= (DCIf b P d P' d' Q)
(at level 80, right associativity) : dcom_scope.
Notation "'->>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '->>' {{ P }}"
:= (DCPost d P)
(at level 80, right associativity) : dcom_scope.
Notation " d ;; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [->>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => True /\ st X <> 0}}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => True /\ st X = 0}} ->>
{{ fun st => st X = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ;; extract d2)
| DCAsgn X a _ => X ::= a
| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
{{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}},
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn X a Q => Q
| DCIf _ _ d1 _ d2 Q => Q
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** Similarly, we can extract the "initial precondition" from a
decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn X a Q => fun st => True
| DCIf _ _ t _ e _ => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]). *)
(** Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified to see that the
decorations are logically consistent and thus add up to a complete
proof of correctness. *)
(** ** Extracting Verification Conditions *)
(** The function [verification_conditions] takes a [dcom] [d] together
with a precondition [P] and returns a _proposition_ that, if it
can be proved, implies that the triple [{{P}} (extract d) {{post d}}]
is valid. *)
(** It does this by walking over [d] and generating a big
conjunction including all the "local checks" that we listed when
we described the informal rules for decorated programs. (Strictly
speaking, we need to massage the informal rules a little bit to
add some uses of the rule of consequence, but the correspondence
should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ->> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn X a Q =>
(P ->> Q [X |-> a])
| DCIf b P1 d1 P2 d2 Q =>
((fun st => P st /\ bassn b st) ->> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ->> P2)
/\ (Q <<->> post d1) /\ (Q <<->> post d2)
/\ verification_conditions P1 d1
/\ verification_conditions P2 d2
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ->> post d)
/\ (Pbody <<->> (fun st => post d st /\ bassn b st))
/\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st)))
/\ verification_conditions Pbody d
| DCPre P' d =>
(P ->> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ->> Q)
end.
(** And now, the key theorem, which states that
[verification_conditions] does its job correctly. Not
surprisingly, we need to use each of the Hoare Logic rules at some
point in the proof. *)
(** We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [[Hd11 Hd12]
[[Hd21 Hd22] [HThen HElse]]]]].
clear H.
apply IHd1 in HThen. clear IHd1.
apply IHd2 in HElse. clear IHd2.
apply hoare_if.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
Case "While".
inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]];
subst; clear H.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
apply hoare_while.
eapply hoare_consequence_pre; eauto.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** ** Examples *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(**
==>
(((fun _ : state => True) ->> (fun _ : state => True)) /\
((fun _ : state => True) ->> (fun _ : state => True)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun _ : state => True) [X |-> AMinus (AId X) (ANum 1)]) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun st : state => st X = 0)
*)
(** In principle, we could certainly work with them using just the
tactics we have so far, but we can make things much smoother with
a bit of automation. We first define a custom [verify] tactic
that applies splitting repeatedly to turn all the conjunctions
into separate subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Lemma ble_nat_true_iff : forall n m : nat,
ble_nat n m = true <-> n <= m.
Proof.
intros n m. split. apply ble_nat_true.
generalize dependent m. induction n; intros m H. reflexivity.
simpl. destruct m. inversion H.
apply le_S_n in H. apply IHn. assumption.
Qed.
Lemma ble_nat_false_iff : forall n m : nat,
ble_nat n m = false <-> ~(n <= m).
Proof.
intros n m. split. apply ble_nat_false.
generalize dependent m. induction n; intros m H.
apply ex_falso_quodlibet. apply H. apply le_0_n.
simpl. destruct m. reflexivity.
apply IHn. intro Hc. apply H. apply le_n_S. assumption.
Qed.
Tactic Notation "verify" :=
apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; intros;
repeat rewrite update_eq;
repeat (rewrite update_neq; [| (intro X; inversion X)]);
simpl in *;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
repeat rewrite not_true_iff_false in *;
repeat rewrite not_false_iff_true in *;
repeat rewrite negb_true_iff in *;
repeat rewrite negb_false_iff in *;
repeat rewrite beq_nat_true_iff in *;
repeat rewrite beq_nat_false_iff in *;
repeat rewrite ble_nat_true_iff in *;
repeat rewrite ble_nat_false_iff in *;
try subst;
repeat
match goal with
[st : state |- _] =>
match goal with
[H : st _ = _ |- _] => rewrite -> H in *; clear H
| [H : _ = st _ |- _] => rewrite <- H in *; clear H
end
end;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For very
simple examples [verify] immediately solves the goal (provided
that the annotations are correct). *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof. verify. Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (m:nat) (p:nat) : dcom := (
{{ fun st => st X = m /\ st Z = p }} ->>
{{ fun st => st Z - st X = p - m }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->>
{{ fun st => (st Z - 1) - (st X - 1) = p - m }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => st Z - (st X - 1) = p - m }} ;;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Z - st X = p - m }}
END
{{ fun st => st Z - st X = p - m /\ st X = 0 }} ->>
{{ fun st => st Z = p - m }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall m p,
dec_correct (subtract_slowly_dec m p).
Proof. intros m p. verify. (* this grinds for a bit! *) Qed.
(** **** Exercise: 3 stars, advanced (slow_assignment_dec) *)
(** In the [slow_assignment] exercise above, we saw a roundabout way
of assigning a number currently stored in [X] to the variable [Y]:
start [Y] at [0], then decrement [X] until it hits [0],
incrementing [Y] at each step.
Write a _formal_ version of this decorated program and prove it
correct. *)
Example slow_assignment_dec (m:nat) : dcom := (
{{ fun st => st X = m }} ->>
{{ fun st => st X + 0 = m }}
Y ::= ANum 0
{{ fun st => st X + st Y = m }};;
WHILE BNot (BEq (AId X) (ANum 0)) DO
{{ fun st => st X + st Y = m /\ st X <> 0 }} ->>
{{ fun st => (st X - 1) + (st Y + 1) = m }}
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st X + (st Y + 1) = m }};;
Y ::= APlus (AId Y) (ANum 1)
{{ fun st => st X + st Y = m }}
END
{{ fun st => st X + st Y = m /\ st X = 0 }} ->>
{{ fun st => st Y = m }}
) % dcom.
Theorem slow_assignment_dec_correct : forall m,
dec_correct (slow_assignment_dec m).
Proof. intro m. verify. Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
(** Following the pattern of [subtract_slowly_dec], write a decorated
program that implements the factorial function and prove it
correct. *)
Example factorial_dec (m:nat) : dcom := (
{{ fun st => st X = m }} ->>
{{ fun st => 1 * real_fact (st X) = real_fact m }}
Y ::= ANum 1
{{ fun st => st Y * real_fact (st X) = real_fact m }};;
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Y * real_fact (st X) = real_fact m /\ st X <> 0 }} ->>
{{ fun st => (st Y * st X) * real_fact (st X - 1) = real_fact m }}
Y ::= AMult (AId Y) (AId X)
{{ fun st => st Y * real_fact (st X - 1) = real_fact m }};;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Y * real_fact (st X) = real_fact m }}
END
{{ fun st => st Y * real_fact (st X) = real_fact m /\ st X = 0 }} ->>
{{ fun st => st Y = real_fact m }}
) % dcom.
Theorem fact_fact :
forall n, n <> 0 -> n * real_fact (n - 1) = real_fact n.
Proof.
intros.
induction n.
apply ex_falso_quodlibet. apply H. reflexivity.
simpl.
SearchAbout [minus].
rewrite <-minus_n_O.
reflexivity.
Qed.
Theorem factorial_dec_correct : forall m,
dec_correct (factorial_dec m).
Proof.
intro m. verify.
SearchAbout [mult].
rewrite mult_assoc_reverse.
rewrite fact_fact.
assumption.
assumption.
simpl in H.
SearchAbout [mult 1].
rewrite mult_1_r in H.
assumption.
Qed.
(** [] *)
(* $Date: 2014-11-12 11:56:38 -0500 (Wed, 12 Nov 2014) $ *)
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:03:18 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W8_35 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_exp_operation_load_diff,
FSM_barrel_shifter_load, FSM_Add_Subt_Sgf_load, FSM_LZA_load,
FSM_Final_Result_load, FSM_selector_D, sign_final_result,
FS_Module_net3617754, final_result_ieee_Module_Sign_S_mux,
YRegister_net3617690, Exp_Operation_Module_exp_result_net3617731,
Leading_Zero_Detector_Module_Output_Reg_net3617695,
final_result_ieee_Module_Final_Result_IEEE_net3617690,
Add_Subt_Sgf_module_Add_Subt_Result_net3617713,
Oper_Start_in_module_MRegister_net3617749,
Barrel_Shifter_module_Output_Reg_net3617713, n400, n401, n404, n405,
n406, n407, n411, n412, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n613, n614,
n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636,
n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647,
n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658,
n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669,
n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680,
n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702,
n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724,
n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746,
n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768,
n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779,
n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790,
n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801,
n802, n803, n804, n805, n806, n807, n808, n809, n810, n811, n812,
n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823,
n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834,
n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845,
n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856,
n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867,
n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878,
n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944,
n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329,
n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349,
n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359,
n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429,
n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452;
wire [1:0] FSM_selector_B;
wire [31:0] intDX;
wire [30:0] intDY;
wire [30:0] DMP;
wire [30:0] DmP;
wire [7:0] exp_oper_result;
wire [4:0] LZA_output;
wire [25:0] Add_Subt_result;
wire [25:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_next;
wire [3:0] FS_Module_state_reg;
wire [30:0] Oper_Start_in_module_intm;
wire [30:0] Oper_Start_in_module_intM;
wire [7:0] Exp_Operation_Module_Data_S;
wire [26:0] Add_Subt_Sgf_module_S_to_D;
wire [4:0] Leading_Zero_Detector_Module_Codec_to_Reg;
wire [22:9] final_result_ieee_Module_Sgf_S_mux;
wire [7:0] final_result_ieee_Module_Exp_S_mux;
wire [51:0] Barrel_Shifter_module_Mux_Array_Data_array;
SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n412), .ENCLK(FS_Module_net3617754), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_5 YRegister_clk_gate_Q_reg ( .CLK(clk), .EN(n411), .ENCLK(YRegister_net3617690), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W8_35 Exp_Operation_Module_exp_result_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_exp_operation_load_diff), .ENCLK(
Exp_Operation_Module_exp_result_net3617731), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W5 Leading_Zero_Detector_Module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_LZA_load), .ENCLK(
Leading_Zero_Detector_Module_Output_Reg_net3617695), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_4 final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_Final_Result_load), .ENCLK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_2 Add_Subt_Sgf_module_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_Add_Subt_Sgf_load), .ENCLK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_6 Oper_Start_in_module_MRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n1423), .ENCLK(
Oper_Start_in_module_MRegister_net3617749), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_3 Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(FSM_barrel_shifter_load), .ENCLK(
Barrel_Shifter_module_Output_Reg_net3617713), .TE(1'b0) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(
Exp_Operation_Module_Data_S[7]), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1409), .Q(
exp_oper_result[7]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(
Exp_Operation_Module_Data_S[6]), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1409), .Q(
exp_oper_result[6]) );
DFFRXLTS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(
Exp_Operation_Module_Data_S[5]), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1409), .Q(
exp_oper_result[5]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(
Oper_Start_in_module_intM[30]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1409), .Q(DMP[30]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(
Oper_Start_in_module_intM[29]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1409), .Q(DMP[29]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(
Oper_Start_in_module_intM[28]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1409), .Q(DMP[28]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(
Oper_Start_in_module_intM[27]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1408), .Q(DMP[27]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(
Oper_Start_in_module_intM[26]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1408), .Q(DMP[26]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(
Oper_Start_in_module_intM[25]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1408), .Q(DMP[25]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(
Oper_Start_in_module_intM[24]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1408), .Q(DMP[24]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(
Oper_Start_in_module_intM[23]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1408), .Q(DMP[23]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(
Oper_Start_in_module_intM[22]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1406), .Q(DMP[22]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(
Oper_Start_in_module_intM[21]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1406), .Q(DMP[21]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(
Oper_Start_in_module_intM[20]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1405), .Q(DMP[20]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(
Oper_Start_in_module_intM[19]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1405), .Q(DMP[19]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(
Oper_Start_in_module_intM[18]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1405), .Q(DMP[18]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(
Oper_Start_in_module_intM[17]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1405), .Q(DMP[17]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(
Oper_Start_in_module_intM[16]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1405), .Q(DMP[16]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(
Oper_Start_in_module_intM[15]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1404), .Q(DMP[15]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(
Oper_Start_in_module_intM[14]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1404), .Q(DMP[14]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(
Oper_Start_in_module_intM[13]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1404), .Q(DMP[13]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(
Oper_Start_in_module_intM[12]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1404), .Q(DMP[12]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(
Oper_Start_in_module_intM[11]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1404), .Q(DMP[11]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(
Oper_Start_in_module_intM[10]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1403), .Q(DMP[10]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(
Oper_Start_in_module_intM[9]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1403), .Q(DMP[9]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(
Oper_Start_in_module_intM[8]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1403), .Q(DMP[8]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(
Oper_Start_in_module_intM[7]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1403), .Q(DMP[7]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(
Oper_Start_in_module_intM[6]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1403), .Q(DMP[6]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(
Oper_Start_in_module_intM[5]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1402), .Q(DMP[5]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(
Oper_Start_in_module_intM[4]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1402), .Q(DMP[4]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(
Oper_Start_in_module_intM[3]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1402), .Q(DMP[3]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(
Oper_Start_in_module_intM[2]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1402), .Q(DMP[2]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(
Oper_Start_in_module_intM[1]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1402), .Q(DMP[1]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(
Oper_Start_in_module_intM[0]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1401), .Q(DMP[0]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(
Oper_Start_in_module_intm[30]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1408), .Q(DmP[30]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(
Oper_Start_in_module_intm[29]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1407), .Q(DmP[29]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(
Oper_Start_in_module_intm[28]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1407), .Q(DmP[28]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(
Oper_Start_in_module_intm[27]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1407), .Q(DmP[27]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(
Oper_Start_in_module_intm[26]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1407), .Q(DmP[26]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(
Oper_Start_in_module_intm[25]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1407), .Q(DmP[25]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(
Oper_Start_in_module_intm[24]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1407), .Q(DmP[24]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(
Oper_Start_in_module_intm[23]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1407), .Q(DmP[23]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(
Oper_Start_in_module_intm[22]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1418), .Q(DmP[22]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(
Oper_Start_in_module_intm[21]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1415), .Q(DmP[21]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(
Oper_Start_in_module_intm[20]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1415), .Q(DmP[20]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(
Oper_Start_in_module_intm[19]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1414), .Q(DmP[19]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(
Oper_Start_in_module_intm[18]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1418), .Q(DmP[18]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(
Oper_Start_in_module_intm[17]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1414), .Q(DmP[17]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(
Oper_Start_in_module_intm[16]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1418), .Q(DmP[16]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(
Oper_Start_in_module_intm[15]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1415), .Q(DmP[15]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(
Oper_Start_in_module_intm[14]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1418), .Q(DmP[14]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(
Oper_Start_in_module_intm[13]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1414), .Q(DmP[13]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(
Oper_Start_in_module_intm[12]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1418), .Q(DmP[12]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(
Oper_Start_in_module_intm[11]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1415), .Q(DmP[11]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(
Oper_Start_in_module_intm[10]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1415), .Q(DmP[10]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(
Oper_Start_in_module_intm[9]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1414), .Q(DmP[9]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(
Oper_Start_in_module_intm[8]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1418), .Q(DmP[8]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(
Oper_Start_in_module_intm[7]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1395), .Q(DmP[7]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(
Oper_Start_in_module_intm[6]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1395), .Q(DmP[6]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(
Oper_Start_in_module_intm[5]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1395), .Q(DmP[5]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(
Oper_Start_in_module_intm[4]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1395), .Q(DmP[4]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(
Oper_Start_in_module_intm[3]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1395), .Q(DmP[3]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(
Oper_Start_in_module_intm[2]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1395), .Q(DmP[2]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(
Oper_Start_in_module_intm[1]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1395), .Q(DmP[1]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(
Oper_Start_in_module_intm[0]), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1395), .Q(DmP[0]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[2]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3617695), .RN(n1410), .Q(
LZA_output[2]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[1]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3617695), .RN(n1407), .Q(
LZA_output[1]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[0]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3617695), .RN(n1407), .Q(
LZA_output[0]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[39]), .QN(n446) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[27]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n1398),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[26]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n1427), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1406), .Q(
Sgf_normalized_result[25]) );
DFFRX1TS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n401), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1398), .Q(
underflow_flag), .QN(n1390) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
Add_Subt_Sgf_module_S_to_D[7]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1410), .Q(
Add_Subt_result[7]), .QN(n1380) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
Add_Subt_Sgf_module_S_to_D[0]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1410), .Q(
Add_Subt_result[0]), .QN(n1379) );
DFFRX1TS YRegister_Q_reg_0_ ( .D(Data_Y[0]), .CK(YRegister_net3617690), .RN(
n1416), .Q(intDY[0]), .QN(n1378) );
DFFRX1TS YRegister_Q_reg_3_ ( .D(Data_Y[3]), .CK(YRegister_net3617690), .RN(
n517), .Q(intDY[3]), .QN(n1377) );
DFFRX1TS YRegister_Q_reg_8_ ( .D(Data_Y[8]), .CK(YRegister_net3617690), .RN(
n1417), .Q(intDY[8]), .QN(n1376) );
DFFRX1TS YRegister_Q_reg_10_ ( .D(Data_Y[10]), .CK(YRegister_net3617690),
.RN(n1393), .Q(intDY[10]), .QN(n1375) );
DFFRX1TS YRegister_Q_reg_6_ ( .D(Data_Y[6]), .CK(YRegister_net3617690), .RN(
n1413), .Q(intDY[6]), .QN(n1374) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(Data_Y[23]), .CK(YRegister_net3617690),
.RN(n1420), .Q(intDY[23]), .QN(n1373) );
DFFRX1TS YRegister_Q_reg_26_ ( .D(Data_Y[26]), .CK(YRegister_net3617690),
.RN(n1420), .Q(intDY[26]), .QN(n1372) );
DFFRX1TS YRegister_Q_reg_25_ ( .D(Data_Y[25]), .CK(YRegister_net3617690),
.RN(n1419), .Q(intDY[25]), .QN(n1371) );
DFFRX1TS YRegister_Q_reg_29_ ( .D(Data_Y[29]), .CK(YRegister_net3617690),
.RN(n1416), .Q(intDY[29]), .QN(n1370) );
DFFRX2TS YRegister_Q_reg_15_ ( .D(Data_Y[15]), .CK(YRegister_net3617690),
.RN(n1420), .Q(intDY[15]), .QN(n1369) );
DFFRX1TS YRegister_Q_reg_17_ ( .D(Data_Y[17]), .CK(YRegister_net3617690),
.RN(n1420), .Q(intDY[17]), .QN(n1368) );
DFFRX1TS YRegister_Q_reg_18_ ( .D(Data_Y[18]), .CK(YRegister_net3617690),
.RN(n1419), .Q(intDY[18]), .QN(n1367) );
DFFRX1TS YRegister_Q_reg_11_ ( .D(Data_Y[11]), .CK(YRegister_net3617690),
.RN(n1393), .Q(intDY[11]), .QN(n1366) );
DFFRX1TS YRegister_Q_reg_27_ ( .D(Data_Y[27]), .CK(YRegister_net3617690),
.RN(n1420), .Q(intDY[27]), .QN(n1365) );
DFFRX1TS YRegister_Q_reg_24_ ( .D(Data_Y[24]), .CK(YRegister_net3617690),
.RN(n1419), .Q(intDY[24]), .QN(n1364) );
DFFRX1TS YRegister_Q_reg_28_ ( .D(Data_Y[28]), .CK(YRegister_net3617690),
.RN(n1416), .Q(intDY[28]), .QN(n1363) );
DFFRX1TS YRegister_Q_reg_20_ ( .D(Data_Y[20]), .CK(YRegister_net3617690),
.RN(n1416), .Q(intDY[20]), .QN(n1362) );
DFFRX1TS YRegister_Q_reg_21_ ( .D(Data_Y[21]), .CK(YRegister_net3617690),
.RN(n1419), .Q(intDY[21]), .QN(n1361) );
DFFRX1TS YRegister_Q_reg_13_ ( .D(Data_Y[13]), .CK(YRegister_net3617690),
.RN(n1420), .Q(intDY[13]), .QN(n1360) );
DFFRX1TS XRegister_Q_reg_12_ ( .D(Data_X[12]), .CK(YRegister_net3617690),
.RN(n1415), .Q(intDX[12]), .QN(n1359) );
DFFRX1TS YRegister_Q_reg_16_ ( .D(Data_Y[16]), .CK(YRegister_net3617690),
.RN(n1416), .Q(intDY[16]), .QN(n1358) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
Add_Subt_Sgf_module_S_to_D[9]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1410), .Q(
Add_Subt_result[9]), .QN(n1356) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
Add_Subt_Sgf_module_S_to_D[13]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[13]), .QN(n1355) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
Add_Subt_Sgf_module_S_to_D[16]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[16]), .QN(n1354) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
Add_Subt_Sgf_module_S_to_D[2]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1410), .Q(
Add_Subt_result[2]), .QN(n1353) );
DFFRX2TS YRegister_Q_reg_9_ ( .D(Data_Y[9]), .CK(YRegister_net3617690), .RN(
n1393), .Q(intDY[9]), .QN(n1352) );
DFFRX2TS YRegister_Q_reg_7_ ( .D(Data_Y[7]), .CK(YRegister_net3617690), .RN(
n1424), .Q(intDY[7]), .QN(n1351) );
DFFRX2TS YRegister_Q_reg_2_ ( .D(Data_Y[2]), .CK(YRegister_net3617690), .RN(
n517), .Q(intDY[2]), .QN(n1350) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[38]), .QN(n1349) );
DFFRX2TS YRegister_Q_reg_4_ ( .D(Data_Y[4]), .CK(YRegister_net3617690), .RN(
n1424), .Q(intDY[4]), .QN(n1348) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[37]), .QN(n1347) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[40]), .QN(n1346) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[41]), .QN(n1345) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[36]), .QN(n1344) );
DFFRX2TS YRegister_Q_reg_5_ ( .D(Data_Y[5]), .CK(YRegister_net3617690), .RN(
n1424), .Q(intDY[5]), .QN(n1343) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
Add_Subt_Sgf_module_S_to_D[19]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1412), .Q(
Add_Subt_result[19]), .QN(n1342) );
DFFRX2TS XRegister_Q_reg_7_ ( .D(Data_X[7]), .CK(YRegister_net3617690), .RN(
n1424), .Q(intDX[7]), .QN(n1341) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
Add_Subt_Sgf_module_S_to_D[4]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[4]), .QN(n1340) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
Add_Subt_Sgf_module_S_to_D[21]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1412), .Q(
Add_Subt_result[21]), .QN(n1339) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(
Exp_Operation_Module_Data_S[0]), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1408), .Q(
exp_oper_result[0]), .QN(n1338) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[45]), .QN(n1337) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[46]), .QN(n1336) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
Add_Subt_Sgf_module_S_to_D[10]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1412), .Q(
Add_Subt_result[10]), .QN(n1335) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
Add_Subt_Sgf_module_S_to_D[18]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[18]), .QN(n1334) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n1406),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[44]), .QN(n1333) );
DFFRX1TS XRegister_Q_reg_30_ ( .D(Data_X[30]), .CK(YRegister_net3617690),
.RN(n1393), .Q(intDX[30]), .QN(n1332) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n1395),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[49]), .QN(n1331) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n1395),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[48]), .QN(n1330) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[47]), .QN(n1329) );
DFFRX2TS XRegister_Q_reg_16_ ( .D(Data_X[16]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[16]), .QN(n1328) );
DFFRX2TS XRegister_Q_reg_5_ ( .D(Data_X[5]), .CK(YRegister_net3617690), .RN(
n1424), .Q(intDX[5]), .QN(n1327) );
DFFRX2TS XRegister_Q_reg_28_ ( .D(Data_X[28]), .CK(YRegister_net3617690),
.RN(n1393), .QN(n1326) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[42]), .QN(n1325) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n1396),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[43]), .QN(n1324) );
DFFRX1TS XRegister_Q_reg_1_ ( .D(Data_X[1]), .CK(YRegister_net3617690), .RN(
n1420), .Q(intDX[1]), .QN(n1323) );
DFFRX1TS XRegister_Q_reg_8_ ( .D(Data_X[8]), .CK(YRegister_net3617690), .RN(
n1417), .Q(intDX[8]), .QN(n1322) );
DFFRX1TS XRegister_Q_reg_3_ ( .D(Data_X[3]), .CK(YRegister_net3617690), .RN(
n1412), .Q(intDX[3]), .QN(n1321) );
DFFRX2TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(
Leading_Zero_Detector_Module_Codec_to_Reg[4]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3617695), .RN(n1407), .Q(
LZA_output[4]), .QN(n1320) );
DFFRX1TS XRegister_Q_reg_23_ ( .D(Data_X[23]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[23]), .QN(n1319) );
DFFRX1TS XRegister_Q_reg_25_ ( .D(Data_X[25]), .CK(YRegister_net3617690),
.RN(n1393), .Q(intDX[25]), .QN(n1318) );
DFFRX1TS XRegister_Q_reg_29_ ( .D(Data_X[29]), .CK(YRegister_net3617690),
.RN(n1393), .Q(intDX[29]), .QN(n1317) );
DFFRX1TS XRegister_Q_reg_21_ ( .D(Data_X[21]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[21]), .QN(n1316) );
DFFRX1TS XRegister_Q_reg_15_ ( .D(Data_X[15]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[15]), .QN(n1315) );
DFFRX1TS XRegister_Q_reg_13_ ( .D(Data_X[13]), .CK(YRegister_net3617690),
.RN(n1414), .Q(intDX[13]), .QN(n1314) );
DFFRX1TS XRegister_Q_reg_19_ ( .D(Data_X[19]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[19]), .QN(n1313) );
DFFRX1TS XRegister_Q_reg_17_ ( .D(Data_X[17]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[17]), .QN(n1312) );
DFFRX2TS YRegister_Q_reg_12_ ( .D(Data_Y[12]), .CK(YRegister_net3617690),
.RN(n1419), .Q(intDY[12]), .QN(n1311) );
DFFRX1TS XRegister_Q_reg_11_ ( .D(Data_X[11]), .CK(YRegister_net3617690),
.RN(n1418), .Q(intDX[11]), .QN(n1309) );
DFFRX2TS Sel_C_Q_reg_0_ ( .D(n407), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n400), .Q(
FSM_selector_C), .QN(n1308) );
DFFRX1TS YRegister_Q_reg_22_ ( .D(Data_Y[22]), .CK(YRegister_net3617690),
.RN(n1416), .Q(intDY[22]), .QN(n1305) );
DFFRX1TS YRegister_Q_reg_14_ ( .D(Data_Y[14]), .CK(YRegister_net3617690),
.RN(n1416), .Q(intDY[14]), .QN(n1304) );
DFFRX1TS YRegister_Q_reg_19_ ( .D(Data_Y[19]), .CK(YRegister_net3617690),
.RN(n1419), .Q(intDY[19]), .QN(n1303) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
Add_Subt_Sgf_module_S_to_D[8]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1410), .Q(
Add_Subt_result[8]), .QN(n1301) );
DFFRX1TS XRegister_Q_reg_6_ ( .D(Data_X[6]), .CK(YRegister_net3617690), .RN(
n1413), .Q(intDX[6]), .QN(n1300) );
DFFRX2TS YRegister_Q_reg_30_ ( .D(Data_Y[30]), .CK(YRegister_net3617690),
.RN(n1419), .Q(intDY[30]), .QN(n1299) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(Data_X[0]), .CK(YRegister_net3617690), .RN(
n1419), .Q(intDX[0]), .QN(n1298) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
Add_Subt_Sgf_module_S_to_D[17]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[17]), .QN(n1297) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
Add_Subt_Sgf_module_S_to_D[12]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[12]), .QN(n1296) );
DFFRX1TS XRegister_Q_reg_4_ ( .D(Data_X[4]), .CK(YRegister_net3617690), .RN(
n1417), .Q(intDX[4]), .QN(n1295) );
DFFRX1TS XRegister_Q_reg_10_ ( .D(Data_X[10]), .CK(YRegister_net3617690),
.RN(n1415), .Q(intDX[10]), .QN(n1294) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(Data_X[2]), .CK(YRegister_net3617690), .RN(
n1420), .Q(intDX[2]), .QN(n1293) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(Data_X[9]), .CK(YRegister_net3617690), .RN(
n1414), .Q(intDX[9]), .QN(n1292) );
DFFRX1TS XRegister_Q_reg_27_ ( .D(Data_X[27]), .CK(YRegister_net3617690),
.RN(n1393), .Q(intDX[27]), .QN(n1291) );
DFFRX1TS XRegister_Q_reg_26_ ( .D(Data_X[26]), .CK(YRegister_net3617690),
.RN(n1393), .Q(intDX[26]), .QN(n1290) );
DFFRX1TS XRegister_Q_reg_24_ ( .D(Data_X[24]), .CK(YRegister_net3617690),
.RN(n1393), .Q(intDX[24]), .QN(n1289) );
DFFRX1TS XRegister_Q_reg_22_ ( .D(Data_X[22]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[22]), .QN(n1288) );
DFFRX1TS XRegister_Q_reg_20_ ( .D(Data_X[20]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[20]), .QN(n1287) );
DFFRX1TS XRegister_Q_reg_18_ ( .D(Data_X[18]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[18]), .QN(n1286) );
DFFRX1TS XRegister_Q_reg_14_ ( .D(Data_X[14]), .CK(YRegister_net3617690),
.RN(n1394), .Q(intDX[14]), .QN(n1285) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(
Exp_Operation_Module_Data_S[4]), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1408), .Q(
exp_oper_result[4]), .QN(n1283) );
DFFRX2TS R_1 ( .D(Leading_Zero_Detector_Module_Codec_to_Reg[3]), .CK(
Leading_Zero_Detector_Module_Output_Reg_net3617695), .RN(n1401), .Q(
n1392), .QN(n1281) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
Add_Subt_Sgf_module_S_to_D[5]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1410), .Q(
Add_Subt_result[5]), .QN(n1280) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
final_result_ieee_Module_Sign_S_mux), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1398),
.Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
final_result_ieee_Module_Exp_S_mux[0]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1398),
.Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
final_result_ieee_Module_Exp_S_mux[1]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1398),
.Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
final_result_ieee_Module_Exp_S_mux[2]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1398),
.Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
final_result_ieee_Module_Exp_S_mux[3]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1398),
.Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
final_result_ieee_Module_Exp_S_mux[4]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1398),
.Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
final_result_ieee_Module_Exp_S_mux[5]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1398),
.Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
final_result_ieee_Module_Exp_S_mux[6]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1398),
.Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
final_result_ieee_Module_Exp_S_mux[7]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n1381),
.CK(final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1401),
.Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n1389),
.CK(final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1401),
.Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n1388),
.CK(final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1401),
.Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n1387),
.CK(final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1401),
.Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n1386),
.CK(final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n1385),
.CK(final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n1384),
.CK(final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n1383),
.CK(final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n1382),
.CK(final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
final_result_ieee_Module_Sgf_S_mux[9]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
final_result_ieee_Module_Sgf_S_mux[10]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
final_result_ieee_Module_Sgf_S_mux[11]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
final_result_ieee_Module_Sgf_S_mux[12]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
final_result_ieee_Module_Sgf_S_mux[13]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
final_result_ieee_Module_Sgf_S_mux[14]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
final_result_ieee_Module_Sgf_S_mux[15]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
final_result_ieee_Module_Sgf_S_mux[16]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
final_result_ieee_Module_Sgf_S_mux[17]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1399),
.Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
final_result_ieee_Module_Sgf_S_mux[18]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
final_result_ieee_Module_Sgf_S_mux[19]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
final_result_ieee_Module_Sgf_S_mux[20]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
final_result_ieee_Module_Sgf_S_mux[21]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
final_result_ieee_Module_Sgf_S_mux[22]), .CK(
final_result_ieee_Module_Final_Result_IEEE_net3617690), .RN(n1400),
.Q(final_result_ieee[22]) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n405), .CK(FS_Module_net3617754), .RN(n400),
.Q(FSM_selector_B[0]), .QN(n1282) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n404), .CK(FS_Module_net3617754), .RN(n400),
.Q(FSM_selector_B[1]), .QN(n1422) );
DFFSX2TS R_0 ( .D(n1391), .CK(YRegister_net3617690), .SN(n1412), .Q(n1421)
);
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(FS_Module_state_next[1]), .CK(
FS_Module_net3617754), .RN(n1420), .Q(FS_Module_state_reg[1]), .QN(
n1357) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(FS_Module_state_next[2]), .CK(
FS_Module_net3617754), .RN(n1409), .Q(FS_Module_state_reg[2]), .QN(
n1284) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n1406),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[51]) );
DFFRX2TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n1406),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[50]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
Add_Subt_Sgf_module_S_to_D[20]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1412), .Q(
Add_Subt_result[20]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
Add_Subt_Sgf_module_S_to_D[14]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1401), .Q(
Add_Subt_result[14]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
Add_Subt_Sgf_module_S_to_D[3]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1410), .Q(
Add_Subt_result[3]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
Add_Subt_Sgf_module_S_to_D[6]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1410), .Q(
Add_Subt_result[6]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
Add_Subt_Sgf_module_S_to_D[1]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1410), .Q(
Add_Subt_result[1]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
Add_Subt_Sgf_module_S_to_D[23]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[23]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
Add_Subt_Sgf_module_S_to_D[11]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[11]) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(
Add_Subt_Sgf_module_S_to_D[26]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1409), .Q(
add_overflow_flag), .QN(n1307) );
DFFRX1TS YRegister_Q_reg_1_ ( .D(Data_Y[1]), .CK(YRegister_net3617690), .RN(
n1414), .Q(intDY[1]), .QN(n448) );
DFFRX1TS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1425), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1401), .Q(
overflow_flag) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n1397),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1431), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1406), .Q(
Sgf_normalized_result[1]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(
Exp_Operation_Module_Data_S[1]), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1408), .Q(
exp_oper_result[1]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(
Exp_Operation_Module_Data_S[2]), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1406), .Q(
exp_oper_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1435), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1401), .Q(
Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1428), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1405), .Q(
Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1429), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1402), .Q(
Sgf_normalized_result[4]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n1430), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1406), .Q(
Sgf_normalized_result[24]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1432), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1405), .Q(
Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1433), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1402), .Q(
Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1434), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1405), .Q(
Sgf_normalized_result[23]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1436), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1405), .Q(
Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1437), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1402), .Q(
Sgf_normalized_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1438), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1405), .Q(
Sgf_normalized_result[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1439), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1401), .Q(
Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1441), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1402), .Q(
Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1442), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1404), .Q(
Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1443), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1402), .Q(
Sgf_normalized_result[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1444), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1404), .Q(
Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1445), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1403), .Q(
Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1446), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1404), .Q(
Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1447), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1403), .Q(
Sgf_normalized_result[10]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1448), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1404), .Q(
Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1449), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1403), .Q(
Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1450), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1403), .Q(
Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1451), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1403), .Q(
Sgf_normalized_result[12]) );
DFFRX4TS FS_Module_state_reg_reg_0_ ( .D(FS_Module_state_next[0]), .CK(
FS_Module_net3617754), .RN(n1409), .Q(FS_Module_state_reg[0]), .QN(
n1310) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
Add_Subt_Sgf_module_S_to_D[24]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1412), .Q(
Add_Subt_result[24]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
Add_Subt_Sgf_module_S_to_D[22]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[22]) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
Add_Subt_Sgf_module_S_to_D[15]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1411), .Q(
Add_Subt_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1440), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1404), .Q(
Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1452), .CK(
Barrel_Shifter_module_Output_Reg_net3617713), .RN(n1406), .Q(
Sgf_normalized_result[0]) );
DFFRX2TS Sel_D_Q_reg_0_ ( .D(n406), .CK(FS_Module_net3617754), .RN(n400),
.Q(FSM_selector_D) );
DFFRX1TS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n1426), .CK(
Oper_Start_in_module_MRegister_net3617749), .RN(n1412), .Q(
sign_final_result), .QN(n1306) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
Add_Subt_Sgf_module_S_to_D[25]), .CK(
Add_Subt_Sgf_module_Add_Subt_Result_net3617713), .RN(n1412), .Q(
Add_Subt_result[25]), .QN(n1302) );
DFFRX2TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(
Exp_Operation_Module_Data_S[3]), .CK(
Exp_Operation_Module_exp_result_net3617731), .RN(n1408), .Q(
exp_oper_result[3]), .QN(n420) );
DFFRX2TS XRegister_Q_reg_31_ ( .D(Data_X[31]), .CK(YRegister_net3617690),
.RN(n1412), .Q(intDX[31]) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(FS_Module_state_next[3]), .CK(
FS_Module_net3617754), .RN(n1409), .Q(FS_Module_state_reg[3]), .QN(
n449) );
INVX2TS U648 ( .A(n941), .Y(n1132) );
NAND2X1TS U649 ( .A(n696), .B(n631), .Y(n692) );
CLKBUFX2TS U650 ( .A(n1243), .Y(n428) );
NAND2X1TS U651 ( .A(n882), .B(LZA_output[4]), .Y(n900) );
NAND2X1TS U652 ( .A(n929), .B(n934), .Y(n937) );
AOI21X1TS U653 ( .A0(n551), .A1(n1157), .B0(n550), .Y(n1133) );
NOR2X1TS U654 ( .A(n597), .B(n599), .Y(n582) );
NOR2XLTS U655 ( .A(n1022), .B(intDY[10]), .Y(n1023) );
OAI21XLTS U656 ( .A0(intDX[15]), .A1(n1369), .B0(intDX[14]), .Y(n1030) );
NOR2XLTS U657 ( .A(n1283), .B(FSM_selector_B[1]), .Y(n531) );
NOR2XLTS U658 ( .A(n645), .B(n531), .Y(n532) );
OAI21XLTS U659 ( .A0(intDX[23]), .A1(n1373), .B0(intDX[22]), .Y(n1050) );
OAI21XLTS U660 ( .A0(n599), .A1(n1119), .B0(n600), .Y(n581) );
OR2X1TS U661 ( .A(n807), .B(n428), .Y(n424) );
OAI21XLTS U662 ( .A0(r_mode[1]), .A1(n520), .B0(sign_final_result), .Y(n521)
);
OR2X1TS U663 ( .A(n1185), .B(n666), .Y(n423) );
INVX2TS U664 ( .A(n594), .Y(n595) );
OAI211XLTS U665 ( .A0(n880), .A1(n1346), .B0(n873), .C0(n872), .Y(n1437) );
OAI211XLTS U666 ( .A0(n798), .A1(n844), .B0(n763), .C0(n762), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
OAI21XLTS U667 ( .A0(n619), .A1(n1271), .B0(n618), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
OAI211XLTS U668 ( .A0(n1379), .A1(n699), .B0(n698), .C0(n1228), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[4]) );
OAI211XLTS U669 ( .A0(n860), .A1(n859), .B0(n858), .C0(n857), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
OAI211XLTS U670 ( .A0(n849), .A1(n798), .B0(n784), .C0(n783), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
OAI211XLTS U671 ( .A0(n782), .A1(n844), .B0(n677), .C0(n676), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
XOR2X1TS U672 ( .A(n1074), .B(n1073), .Y(Add_Subt_Sgf_module_S_to_D[24]) );
XOR2X1TS U673 ( .A(n1083), .B(n1082), .Y(Add_Subt_Sgf_module_S_to_D[22]) );
XOR2X1TS U674 ( .A(n723), .B(n722), .Y(Add_Subt_Sgf_module_S_to_D[14]) );
OAI211X1TS U675 ( .A0(n798), .A1(n848), .B0(n759), .C0(n758), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
OAI211X1TS U676 ( .A0(n831), .A1(n1270), .B0(n830), .C0(n829), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI211X1TS U677 ( .A0(n840), .A1(n844), .B0(n767), .C0(n766), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
OAI211X1TS U678 ( .A0(n849), .A1(n860), .B0(n836), .C0(n835), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
OAI211X1TS U679 ( .A0(n849), .A1(n773), .B0(n745), .C0(n744), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
OAI211X1TS U680 ( .A0(n773), .A1(n848), .B0(n761), .C0(n760), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
OAI211X1TS U681 ( .A0(n798), .A1(n859), .B0(n797), .C0(n796), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
OAI211X1TS U682 ( .A0(n849), .A1(n782), .B0(n753), .C0(n752), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
OAI211X1TS U683 ( .A0(n840), .A1(n859), .B0(n792), .C0(n791), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
OAI211X1TS U684 ( .A0(n840), .A1(n848), .B0(n734), .C0(n733), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
OAI211X1TS U685 ( .A0(n860), .A1(n844), .B0(n843), .C0(n842), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
OAI211X1TS U686 ( .A0(n782), .A1(n859), .B0(n776), .C0(n775), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
OAI211X1TS U687 ( .A0(n782), .A1(n848), .B0(n781), .C0(n780), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
OAI211X1TS U688 ( .A0(n773), .A1(n844), .B0(n765), .C0(n764), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
OAI211X1TS U689 ( .A0(n860), .A1(n848), .B0(n847), .C0(n846), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
OAI211X1TS U690 ( .A0(n849), .A1(n840), .B0(n839), .C0(n838), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
OAI211X1TS U691 ( .A0(n773), .A1(n859), .B0(n772), .C0(n771), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
OAI21X1TS U692 ( .A0(n853), .A1(n852), .B0(n851), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
NAND3X1TS U693 ( .A(n1228), .B(n1227), .C(n1226), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[3]) );
OAI211X1TS U694 ( .A0(n689), .A1(n699), .B0(n688), .C0(n687), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[0]) );
AOI32X2TS U695 ( .A0(n670), .A1(n1273), .A2(n669), .B0(n751), .B1(n852), .Y(
n778) );
INVX2TS U696 ( .A(n820), .Y(n1433) );
OAI21X1TS U697 ( .A0(n1145), .A1(n1141), .B0(n1142), .Y(n1140) );
OAI211X1TS U698 ( .A0(n880), .A1(n1347), .B0(n879), .C0(n878), .Y(n1439) );
OAI211X1TS U699 ( .A0(n880), .A1(n1349), .B0(n867), .C0(n866), .Y(n1429) );
OAI211X1TS U700 ( .A0(n804), .A1(n803), .B0(n802), .C0(n1247), .Y(n1450) );
OAI211X1TS U701 ( .A0(n880), .A1(n1345), .B0(n864), .C0(n863), .Y(n1441) );
OAI211X1TS U702 ( .A0(n641), .A1(n678), .B0(n640), .C0(n687), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[2]) );
OAI21X1TS U703 ( .A0(n1132), .A1(n1128), .B0(n1129), .Y(n1127) );
NAND3X1TS U704 ( .A(n697), .B(Add_Subt_result[1]), .C(n1353), .Y(n1228) );
OAI211X1TS U705 ( .A0(n880), .A1(n1344), .B0(n870), .C0(n869), .Y(n1435) );
NAND3X1TS U706 ( .A(n1267), .B(n834), .C(n444), .Y(n618) );
AOI211X1TS U707 ( .A0(n447), .A1(n861), .B0(n819), .C0(n818), .Y(n820) );
NAND2BX1TS U708 ( .AN(n1255), .B(n1254), .Y(n1427) );
OAI211X1TS U709 ( .A0(n817), .A1(n1336), .B0(n1218), .C0(n816), .Y(n818) );
OAI211X1TS U710 ( .A0(n914), .A1(n1243), .B0(n913), .C0(n912), .Y(n1438) );
OAI211X1TS U711 ( .A0(n703), .A1(n803), .B0(n702), .C0(n1247), .Y(n704) );
OAI211X1TS U712 ( .A0(n892), .A1(n1243), .B0(n891), .C0(n890), .Y(n1434) );
NOR2X1TS U713 ( .A(n1163), .B(n1164), .Y(n1162) );
OAI211X1TS U714 ( .A0(n910), .A1(n1243), .B0(n909), .C0(n908), .Y(n1432) );
OAI211X1TS U715 ( .A0(n907), .A1(n1243), .B0(n906), .C0(n905), .Y(n1440) );
OAI21X1TS U716 ( .A0(Add_Subt_result[3]), .A1(Add_Subt_result[2]), .B0(n690),
.Y(n691) );
OAI211X1TS U717 ( .A0(n806), .A1(n1330), .B0(n651), .C0(n650), .Y(n1448) );
OAI211X1TS U718 ( .A0(n806), .A1(n1337), .B0(n656), .C0(n655), .Y(n1449) );
OAI211X1TS U719 ( .A0(n806), .A1(n1331), .B0(n659), .C0(n658), .Y(n1446) );
NOR2X1TS U720 ( .A(n1270), .B(n437), .Y(n1264) );
OAI211X1TS U721 ( .A0(n624), .A1(n1171), .B0(n623), .C0(n622), .Y(
FS_Module_state_next[3]) );
OAI21X1TS U722 ( .A0(n877), .A1(n1215), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .Y(n869) );
AND2X2TS U723 ( .A(n643), .B(n642), .Y(n806) );
OR2X2TS U724 ( .A(n692), .B(n632), .Y(n638) );
NOR2X1TS U725 ( .A(n809), .B(n808), .Y(n643) );
OAI211X2TS U726 ( .A0(n1392), .A1(n648), .B0(n647), .C0(n646), .Y(n801) );
NOR2X1TS U727 ( .A(n1247), .B(n1329), .Y(n819) );
NAND3X1TS U728 ( .A(n990), .B(n989), .C(n1279), .Y(n614) );
INVX3TS U729 ( .A(n859), .Y(n440) );
NAND3X1TS U730 ( .A(n1202), .B(n1201), .C(n1200), .Y(n1231) );
INVX3TS U731 ( .A(n859), .Y(n439) );
OAI21X1TS U732 ( .A0(n813), .A1(n911), .B0(n812), .Y(n815) );
NOR2X1TS U733 ( .A(n1247), .B(n1337), .Y(n875) );
NOR2X1TS U734 ( .A(n1247), .B(n1330), .Y(n871) );
NOR2X1TS U735 ( .A(n1247), .B(n1336), .Y(n865) );
NOR2X1TS U736 ( .A(n1247), .B(n1331), .Y(n862) );
NAND3X1TS U737 ( .A(n1214), .B(n1213), .C(n1212), .Y(n1242) );
NAND2BX1TS U738 ( .AN(n899), .B(n898), .Y(n1189) );
NAND3BX1TS U739 ( .AN(n1168), .B(n541), .C(n1423), .Y(n622) );
AOI222X1TS U740 ( .A0(n533), .A1(n530), .B0(FSM_selector_B[1]), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .C0(n534), .C1(n1211),
.Y(n799) );
NAND2X1TS U741 ( .A(FS_Module_state_reg[0]), .B(n610), .Y(n1278) );
NOR2X1TS U742 ( .A(n451), .B(n1307), .Y(n452) );
AND2X2TS U743 ( .A(n608), .B(n607), .Y(n667) );
OAI211X1TS U744 ( .A0(n1002), .A1(n1058), .B0(n1001), .C0(n1000), .Y(n1007)
);
NOR2X2TS U745 ( .A(n1422), .B(n885), .Y(n425) );
INVX2TS U746 ( .A(n1252), .Y(n1243) );
CLKAND2X2TS U747 ( .A(n882), .B(n1320), .Y(n530) );
OAI211XLTS U748 ( .A0(n1377), .A1(intDX[3]), .B0(n1012), .C0(n1011), .Y(
n1015) );
OAI211X2TS U749 ( .A0(intDX[12]), .A1(n1311), .B0(n1034), .C0(n1020), .Y(
n1036) );
NOR2X1TS U750 ( .A(n1043), .B(intDY[16]), .Y(n1044) );
NAND2BX1TS U751 ( .AN(Sgf_normalized_result[25]), .B(n983), .Y(n1067) );
NOR2X1TS U752 ( .A(n1057), .B(intDY[24]), .Y(n998) );
OAI221X1TS U753 ( .A0(n1309), .A1(intDY[11]), .B0(n1294), .B1(intDY[10]),
.C0(n1027), .Y(n492) );
NAND3X1TS U754 ( .A(n1372), .B(n999), .C(intDX[26]), .Y(n1001) );
OAI211X2TS U755 ( .A0(intDX[20]), .A1(n1362), .B0(n1054), .C0(n1039), .Y(
n1048) );
OAI221XLTS U756 ( .A0(n1323), .A1(intDY[1]), .B0(n1298), .B1(intDY[0]), .C0(
n482), .Y(n487) );
NOR2X1TS U757 ( .A(Add_Subt_result[15]), .B(Add_Subt_result[16]), .Y(n629)
);
NAND2BX1TS U758 ( .AN(intDX[24]), .B(intDY[24]), .Y(n1055) );
OR2X2TS U759 ( .A(FSM_selector_B[0]), .B(FSM_selector_B[1]), .Y(n456) );
NAND2BX1TS U760 ( .AN(intDX[13]), .B(intDY[13]), .Y(n1020) );
OAI21X1TS U761 ( .A0(r_mode[0]), .A1(n519), .B0(n1306), .Y(n522) );
NAND2BX1TS U762 ( .AN(intDX[19]), .B(intDY[19]), .Y(n1045) );
NOR2X1TS U763 ( .A(n449), .B(n1307), .Y(n529) );
NAND2BX1TS U764 ( .AN(intDX[21]), .B(intDY[21]), .Y(n1039) );
NAND2BX1TS U765 ( .AN(intDX[9]), .B(intDY[9]), .Y(n1024) );
NAND2BX1TS U766 ( .AN(intDY[27]), .B(intDX[27]), .Y(n1000) );
NAND2BX1TS U767 ( .AN(intDX[27]), .B(intDY[27]), .Y(n999) );
OAI21X4TS U768 ( .A0(n1074), .A1(n1070), .B0(n1071), .Y(n1069) );
XNOR2X2TS U769 ( .A(n1421), .B(intDX[31]), .Y(n541) );
OAI21X1TS U770 ( .A0(n1136), .A1(n1142), .B0(n1137), .Y(n564) );
AO21X1TS U771 ( .A0(Exp_Operation_Module_Data_S[7]), .A1(n927), .B0(n994),
.Y(n1425) );
MX2X1TS U772 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n917), .Y(n562)
);
MX2X1TS U773 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n917), .Y(n560)
);
NOR2X1TS U774 ( .A(n930), .B(n937), .Y(n940) );
INVX2TS U775 ( .A(n481), .Y(n610) );
MX2X1TS U776 ( .A(DMP[27]), .B(exp_oper_result[4]), .S0(n983), .Y(n468) );
XOR2X1TS U777 ( .A(n458), .B(n925), .Y(n467) );
OAI32X1TS U778 ( .A0(n1019), .A1(n1018), .A2(n1017), .B0(n1016), .B1(n1018),
.Y(n1037) );
AOI222X1TS U779 ( .A0(intDY[4]), .A1(n1295), .B0(n1015), .B1(n1014), .C0(
intDY[5]), .C1(n1327), .Y(n1017) );
MX2X1TS U780 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(n956), .Y(n579) );
MX2X1TS U781 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n917), .Y(n558)
);
MX2X1TS U782 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n917), .Y(n548)
);
INVX2TS U783 ( .A(n987), .Y(n986) );
AO22XLTS U784 ( .A0(n431), .A1(Add_Subt_result[20]), .B0(DmP[3]), .B1(n741),
.Y(n664) );
AO22XLTS U785 ( .A0(n824), .A1(Add_Subt_result[17]), .B0(DmP[6]), .B1(n741),
.Y(n737) );
NOR2XLTS U786 ( .A(n726), .B(n1340), .Y(n672) );
AO22XLTS U787 ( .A0(n824), .A1(Add_Subt_result[5]), .B0(DmP[18]), .B1(n741),
.Y(n732) );
NOR2X1TS U788 ( .A(n638), .B(Add_Subt_result[4]), .Y(n690) );
NAND3BXLTS U789 ( .AN(n645), .B(n814), .C(n644), .Y(n647) );
AOI222X1TS U790 ( .A0(n1209), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .B1(n1208), .C0(n1207), .C1(Barrel_Shifter_module_Mux_Array_Data_array[35]), .Y(n1233) );
NAND2X1TS U791 ( .A(n1225), .B(n630), .Y(n1221) );
OR2X1TS U792 ( .A(n953), .B(n952), .Y(n1103) );
CLKAND2X2TS U793 ( .A(n639), .B(Add_Subt_result[4]), .Y(n694) );
OR2X1TS U794 ( .A(n961), .B(n960), .Y(n1094) );
NOR2X4TS U795 ( .A(n667), .B(n666), .Y(n1266) );
NOR2X1TS U796 ( .A(n549), .B(n548), .Y(n1158) );
CLKAND2X2TS U797 ( .A(n984), .B(Sgf_normalized_result[1]), .Y(n542) );
XOR2X1TS U798 ( .A(n926), .B(n925), .Y(n994) );
NOR2XLTS U799 ( .A(n681), .B(Add_Subt_result[25]), .Y(n682) );
AOI2BB1XLTS U800 ( .A0N(n680), .A1N(Add_Subt_result[23]), .B0(
Add_Subt_result[24]), .Y(n681) );
NAND4XLTS U801 ( .A(n1180), .B(n1222), .C(Add_Subt_result[8]), .D(n1356),
.Y(n683) );
NOR3X1TS U802 ( .A(Add_Subt_result[21]), .B(Add_Subt_result[20]), .C(
Add_Subt_result[19]), .Y(n636) );
MX2X1TS U803 ( .A(DMP[26]), .B(exp_oper_result[3]), .S0(n980), .Y(n471) );
MX2X1TS U804 ( .A(DMP[24]), .B(exp_oper_result[1]), .S0(n980), .Y(n477) );
XOR2X1TS U805 ( .A(n925), .B(n461), .Y(n476) );
XOR2XLTS U806 ( .A(n713), .B(n627), .Y(Add_Subt_Sgf_module_S_to_D[11]) );
NOR2XLTS U807 ( .A(n1270), .B(n849), .Y(n619) );
XOR2XLTS U808 ( .A(n1145), .B(n1144), .Y(Add_Subt_Sgf_module_S_to_D[5]) );
XOR2XLTS U809 ( .A(n592), .B(n591), .Y(Add_Subt_Sgf_module_S_to_D[12]) );
XOR2XLTS U810 ( .A(n1111), .B(n1110), .Y(Add_Subt_Sgf_module_S_to_D[16]) );
XOR2XLTS U811 ( .A(n1132), .B(n1131), .Y(Add_Subt_Sgf_module_S_to_D[7]) );
MX2X1TS U812 ( .A(DMP[29]), .B(exp_oper_result[6]), .S0(n917), .Y(n919) );
XOR2X1TS U813 ( .A(n925), .B(n454), .Y(n920) );
CLKAND2X2TS U814 ( .A(n915), .B(DmP[29]), .Y(n454) );
NAND2BXLTS U815 ( .AN(intDY[9]), .B(intDX[9]), .Y(n1026) );
NAND3XLTS U816 ( .A(n1376), .B(n1024), .C(intDX[8]), .Y(n1025) );
OAI21XLTS U817 ( .A0(intDX[13]), .A1(n1360), .B0(intDX[12]), .Y(n1021) );
OAI21XLTS U818 ( .A0(intDX[3]), .A1(n1377), .B0(intDX[2]), .Y(n1013) );
NAND2BXLTS U819 ( .AN(intDX[2]), .B(intDY[2]), .Y(n1011) );
OAI2BB2XLTS U820 ( .B0(intDY[0]), .B1(n1010), .A0N(intDX[1]), .A1N(n448),
.Y(n1012) );
OAI21XLTS U821 ( .A0(intDX[1]), .A1(n448), .B0(intDX[0]), .Y(n1010) );
NOR2X1TS U822 ( .A(n928), .B(n932), .Y(n934) );
NAND3BX1TS U823 ( .AN(n1043), .B(n1041), .C(n1040), .Y(n1061) );
MX2X1TS U824 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n980), .Y(
n973) );
MX2X1TS U825 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n980), .Y(
n981) );
AO22XLTS U826 ( .A0(n824), .A1(Add_Subt_result[16]), .B0(DmP[7]), .B1(n741),
.Y(n739) );
MX2X1TS U827 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n956), .Y(n584) );
MX2X1TS U828 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(n980), .Y(
n976) );
MX2X1TS U829 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n917), .Y(n556)
);
MX2X1TS U830 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n956), .Y(
n719) );
MX2X1TS U831 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n980), .Y(
n964) );
NAND2X1TS U832 ( .A(n593), .B(n582), .Y(n930) );
MX2X1TS U833 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n956), .Y(
n588) );
MX2X1TS U834 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n956), .Y(
n952) );
MX2X1TS U835 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n917), .Y(n575)
);
MX2X1TS U836 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n956), .Y(
n957) );
MX2X1TS U837 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n980), .Y(
n969) );
MX2X1TS U838 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n980), .Y(
n960) );
AO22XLTS U839 ( .A0(n431), .A1(Add_Subt_result[15]), .B0(DmP[8]), .B1(n741),
.Y(n742) );
AO22XLTS U840 ( .A0(n430), .A1(Add_Subt_result[13]), .B0(DmP[10]), .B1(n786),
.Y(n738) );
INVX4TS U841 ( .A(n987), .Y(n570) );
MX2X1TS U842 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n956), .Y(
n946) );
MX2X1TS U843 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n956), .Y(
n944) );
MX2X1TS U844 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n956), .Y(
n715) );
NOR2X1TS U845 ( .A(n707), .B(n710), .Y(n929) );
NOR2X1TS U846 ( .A(n716), .B(n715), .Y(n928) );
MX2X1TS U847 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n956), .Y(n577)
);
BUFX3TS U848 ( .A(FSM_selector_D), .Y(n983) );
MX2X1TS U849 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n917), .Y(n573)
);
NAND2X1TS U850 ( .A(n1135), .B(n565), .Y(n567) );
NOR2X1TS U851 ( .A(n1141), .B(n1136), .Y(n565) );
NAND2X1TS U852 ( .A(n610), .B(FSM_selector_C), .Y(n990) );
AO22XLTS U853 ( .A0(n430), .A1(Add_Subt_result[11]), .B0(DmP[12]), .B1(n786),
.Y(n729) );
AO22XLTS U854 ( .A0(n824), .A1(Add_Subt_result[7]), .B0(DmP[16]), .B1(n741),
.Y(n730) );
AO22XLTS U855 ( .A0(n824), .A1(Add_Subt_result[8]), .B0(DmP[15]), .B1(n741),
.Y(n728) );
AO22XLTS U856 ( .A0(n824), .A1(Add_Subt_result[12]), .B0(DmP[11]), .B1(n786),
.Y(n727) );
AO22XLTS U857 ( .A0(n824), .A1(Add_Subt_result[9]), .B0(DmP[14]), .B1(n786),
.Y(n731) );
NAND2X1TS U858 ( .A(n1169), .B(FS_Module_state_reg[2]), .Y(n481) );
CLKAND2X2TS U859 ( .A(n903), .B(n902), .Y(n997) );
OR2X1TS U860 ( .A(n970), .B(n969), .Y(n1085) );
CLKAND2X2TS U861 ( .A(n917), .B(Sgf_normalized_result[0]), .Y(n546) );
NAND2X1TS U862 ( .A(n574), .B(n573), .Y(n1129) );
INVX2TS U863 ( .A(n1063), .Y(n1256) );
INVX2TS U864 ( .A(n1063), .Y(n1258) );
CLKAND2X2TS U865 ( .A(n1169), .B(n611), .Y(n411) );
AND3X1TS U866 ( .A(n613), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[2]), .Y(FSM_Final_Result_load) );
AO22XLTS U867 ( .A0(n1251), .A1(n1243), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B1(n1195), .Y(n1452)
);
NAND4BXLTS U868 ( .AN(n1173), .B(n1172), .C(n1171), .D(n1170), .Y(
FS_Module_state_next[0]) );
AOI2BB2XLTS U869 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[40]), .B1(
n427), .A0N(n654), .A1N(n803), .Y(n655) );
AOI2BB2XLTS U870 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[37]), .B1(
n427), .A0N(n652), .A1N(n803), .Y(n650) );
AOI2BB2XLTS U871 ( .B0(Barrel_Shifter_module_Mux_Array_Data_array[36]), .B1(
n427), .A0N(n701), .A1N(n803), .Y(n658) );
NAND4XLTS U872 ( .A(n1205), .B(n1218), .C(n1204), .D(n1203), .Y(n1445) );
AOI2BB2XLTS U873 ( .B0(n1210), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .A0N(n1233), .A1N(
n1246), .Y(n1204) );
NAND4XLTS U874 ( .A(n1236), .B(n1235), .C(n1234), .D(n1247), .Y(n1444) );
NAND4XLTS U875 ( .A(n1219), .B(n1218), .C(n1217), .D(n1216), .Y(n1443) );
AOI2BB2XLTS U876 ( .B0(n1210), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .A0N(n1244), .A1N(
n1246), .Y(n1217) );
NAND4XLTS U877 ( .A(n1250), .B(n1249), .C(n1248), .D(n1247), .Y(n1442) );
MX2X1TS U878 ( .A(DMP[25]), .B(exp_oper_result[2]), .S0(n980), .Y(n474) );
XOR2X1TS U879 ( .A(n925), .B(n460), .Y(n473) );
OAI2BB2XLTS U880 ( .B0(n997), .B1(n1252), .A0N(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1N(n1195), .Y(n1431) );
XOR2XLTS U881 ( .A(n1164), .B(n1163), .Y(Add_Subt_Sgf_module_S_to_D[1]) );
XOR2XLTS U882 ( .A(n1092), .B(n1091), .Y(Add_Subt_Sgf_module_S_to_D[20]) );
OAI211XLTS U883 ( .A0(FSM_selector_C), .A1(n1278), .B0(n527), .C0(n526), .Y(
FS_Module_state_next[1]) );
OAI21XLTS U884 ( .A0(n1174), .A1(n1422), .B0(n523), .Y(n404) );
CLKAND2X2TS U885 ( .A(n1277), .B(Sgf_normalized_result[24]), .Y(
final_result_ieee_Module_Sgf_S_mux[22]) );
CLKAND2X2TS U886 ( .A(n1277), .B(Sgf_normalized_result[23]), .Y(
final_result_ieee_Module_Sgf_S_mux[21]) );
CLKAND2X2TS U887 ( .A(n1276), .B(Sgf_normalized_result[22]), .Y(
final_result_ieee_Module_Sgf_S_mux[20]) );
CLKAND2X2TS U888 ( .A(n1276), .B(Sgf_normalized_result[21]), .Y(
final_result_ieee_Module_Sgf_S_mux[19]) );
CLKAND2X2TS U889 ( .A(n1276), .B(Sgf_normalized_result[20]), .Y(
final_result_ieee_Module_Sgf_S_mux[18]) );
CLKAND2X2TS U890 ( .A(n1276), .B(Sgf_normalized_result[19]), .Y(
final_result_ieee_Module_Sgf_S_mux[17]) );
CLKAND2X2TS U891 ( .A(n1275), .B(Sgf_normalized_result[18]), .Y(
final_result_ieee_Module_Sgf_S_mux[16]) );
CLKAND2X2TS U892 ( .A(n1276), .B(Sgf_normalized_result[17]), .Y(
final_result_ieee_Module_Sgf_S_mux[15]) );
CLKAND2X2TS U893 ( .A(n1276), .B(Sgf_normalized_result[16]), .Y(
final_result_ieee_Module_Sgf_S_mux[14]) );
CLKAND2X2TS U894 ( .A(n1276), .B(Sgf_normalized_result[15]), .Y(
final_result_ieee_Module_Sgf_S_mux[13]) );
CLKAND2X2TS U895 ( .A(n1276), .B(Sgf_normalized_result[14]), .Y(
final_result_ieee_Module_Sgf_S_mux[12]) );
CLKAND2X2TS U896 ( .A(n1276), .B(Sgf_normalized_result[13]), .Y(
final_result_ieee_Module_Sgf_S_mux[11]) );
CLKAND2X2TS U897 ( .A(n1276), .B(Sgf_normalized_result[12]), .Y(
final_result_ieee_Module_Sgf_S_mux[10]) );
CLKAND2X2TS U898 ( .A(n1277), .B(Sgf_normalized_result[11]), .Y(
final_result_ieee_Module_Sgf_S_mux[9]) );
CLKAND2X2TS U899 ( .A(n1229), .B(Sgf_normalized_result[10]), .Y(n1382) );
CLKAND2X2TS U900 ( .A(n1229), .B(Sgf_normalized_result[9]), .Y(n1383) );
CLKAND2X2TS U901 ( .A(n1229), .B(Sgf_normalized_result[8]), .Y(n1384) );
CLKAND2X2TS U902 ( .A(n1229), .B(Sgf_normalized_result[7]), .Y(n1385) );
CLKAND2X2TS U903 ( .A(n1229), .B(Sgf_normalized_result[6]), .Y(n1386) );
CLKAND2X2TS U904 ( .A(n1229), .B(Sgf_normalized_result[5]), .Y(n1387) );
CLKAND2X2TS U905 ( .A(n1229), .B(Sgf_normalized_result[4]), .Y(n1388) );
CLKAND2X2TS U906 ( .A(n1229), .B(Sgf_normalized_result[3]), .Y(n1389) );
CLKAND2X2TS U907 ( .A(n1229), .B(Sgf_normalized_result[2]), .Y(n1381) );
NAND2BXLTS U908 ( .AN(exp_oper_result[7]), .B(n1277), .Y(
final_result_ieee_Module_Exp_S_mux[7]) );
NAND2BXLTS U909 ( .AN(exp_oper_result[6]), .B(n1277), .Y(
final_result_ieee_Module_Exp_S_mux[6]) );
NAND2BXLTS U910 ( .AN(exp_oper_result[5]), .B(n1277), .Y(
final_result_ieee_Module_Exp_S_mux[5]) );
NAND2BXLTS U911 ( .AN(exp_oper_result[2]), .B(n1277), .Y(
final_result_ieee_Module_Exp_S_mux[2]) );
NAND2BXLTS U912 ( .AN(exp_oper_result[1]), .B(n1277), .Y(
final_result_ieee_Module_Exp_S_mux[1]) );
OAI21XLTS U913 ( .A0(FS_Module_state_reg[0]), .A1(n524), .B0(n786), .Y(n407)
);
AOI31XLTS U914 ( .A0(n1356), .A1(n1301), .A2(n1280), .B0(Add_Subt_result[10]), .Y(n695) );
AOI222X1TS U915 ( .A0(n1265), .A1(n438), .B0(n1269), .B1(n440), .C0(n1268),
.C1(n1266), .Y(n853) );
AOI222X1TS U916 ( .A0(n1268), .A1(n444), .B0(n1267), .B1(n1266), .C0(n1265),
.C1(n439), .Y(n1263) );
XOR2XLTS U917 ( .A(n1101), .B(n1100), .Y(Add_Subt_Sgf_module_S_to_D[18]) );
XOR2XLTS U918 ( .A(n603), .B(n602), .Y(Add_Subt_Sgf_module_S_to_D[10]) );
MX2X1TS U919 ( .A(DMP[23]), .B(exp_oper_result[0]), .S0(n980), .Y(n479) );
XOR2XLTS U920 ( .A(n1152), .B(n1151), .Y(Add_Subt_Sgf_module_S_to_D[4]) );
OR2X1TS U921 ( .A(n525), .B(n984), .Y(n406) );
NAND4XLTS U922 ( .A(n1227), .B(n1183), .C(n684), .D(n683), .Y(n685) );
AOI31XLTS U923 ( .A0(n1225), .A1(Add_Subt_result[16]), .A2(n1297), .B0(n682),
.Y(n684) );
NAND4BXLTS U924 ( .AN(n1184), .B(n1183), .C(n1182), .D(n1181), .Y(
Leading_Zero_Detector_Module_Codec_to_Reg[1]) );
AOI2BB2XLTS U925 ( .B0(n1179), .B1(n1178), .A0N(n1177), .A1N(n1176), .Y(
n1182) );
NAND4XLTS U926 ( .A(n1180), .B(Add_Subt_result[11]), .C(n1355), .D(n1296),
.Y(n1181) );
AOI31XLTS U927 ( .A0(n686), .A1(n693), .A2(Add_Subt_result[5]), .B0(n637),
.Y(n640) );
OAI211XLTS U928 ( .A0(n636), .A1(n635), .B0(n1183), .C0(n634), .Y(n637) );
MX2X1TS U929 ( .A(intDY[0]), .B(intDX[0]), .S0(n1260), .Y(
Oper_Start_in_module_intM[0]) );
MX2X1TS U930 ( .A(intDY[1]), .B(intDX[1]), .S0(n1260), .Y(
Oper_Start_in_module_intM[1]) );
MX2X1TS U931 ( .A(intDY[2]), .B(intDX[2]), .S0(n1260), .Y(
Oper_Start_in_module_intM[2]) );
MX2X1TS U932 ( .A(intDY[3]), .B(intDX[3]), .S0(n1220), .Y(
Oper_Start_in_module_intM[3]) );
MX2X1TS U933 ( .A(intDY[4]), .B(intDX[4]), .S0(n1220), .Y(
Oper_Start_in_module_intM[4]) );
MX2X1TS U934 ( .A(intDY[5]), .B(intDX[5]), .S0(n1220), .Y(
Oper_Start_in_module_intM[5]) );
MX2X1TS U935 ( .A(intDY[6]), .B(intDX[6]), .S0(n1220), .Y(
Oper_Start_in_module_intM[6]) );
MX2X1TS U936 ( .A(intDY[7]), .B(intDX[7]), .S0(n1220), .Y(
Oper_Start_in_module_intM[7]) );
MX2X1TS U937 ( .A(intDY[8]), .B(intDX[8]), .S0(n1220), .Y(
Oper_Start_in_module_intM[8]) );
MX2X1TS U938 ( .A(intDY[9]), .B(intDX[9]), .S0(n1220), .Y(
Oper_Start_in_module_intM[9]) );
MX2X1TS U939 ( .A(intDY[10]), .B(intDX[10]), .S0(n1220), .Y(
Oper_Start_in_module_intM[10]) );
MX2X1TS U940 ( .A(DMP[28]), .B(exp_oper_result[5]), .S0(FSM_selector_D), .Y(
n465) );
XOR2X1TS U941 ( .A(n925), .B(n455), .Y(n464) );
CLKAND2X2TS U942 ( .A(n915), .B(DmP[28]), .Y(n455) );
MX2X1TS U943 ( .A(DMP[30]), .B(exp_oper_result[7]), .S0(n917), .Y(n923) );
XOR2X1TS U944 ( .A(n925), .B(n916), .Y(n924) );
CLKAND2X2TS U945 ( .A(n915), .B(DmP[30]), .Y(n916) );
OR2X1TS U946 ( .A(n1392), .B(LZA_output[4]), .Y(n421) );
OA21XLTS U947 ( .A0(n1325), .A1(exp_oper_result[3]), .B0(n1188), .Y(n422) );
INVX2TS U948 ( .A(n787), .Y(n824) );
INVX2TS U949 ( .A(n424), .Y(n426) );
INVX2TS U950 ( .A(n424), .Y(n427) );
INVX2TS U951 ( .A(n824), .Y(n429) );
INVX2TS U952 ( .A(n429), .Y(n430) );
INVX2TS U953 ( .A(n429), .Y(n431) );
INVX2TS U954 ( .A(n726), .Y(n432) );
INVX2TS U955 ( .A(n726), .Y(n433) );
INVX2TS U956 ( .A(n726), .Y(n434) );
OAI221X1TS U957 ( .A0(n1287), .A1(intDY[20]), .B0(n1313), .B1(intDY[19]),
.C0(n497), .Y(n500) );
OAI221X1TS U958 ( .A0(n1326), .A1(intDY[28]), .B0(n1291), .B1(intDY[27]),
.C0(n505), .Y(n508) );
XOR2X1TS U959 ( .A(n925), .B(n459), .Y(n470) );
NOR3X4TS U960 ( .A(FS_Module_state_reg[3]), .B(n1357), .C(n1284), .Y(
FSM_Add_Subt_Sgf_load) );
AOI32X1TS U961 ( .A0(n833), .A1(n436), .A2(n1269), .B0(n850), .B1(n436), .Y(
n835) );
NOR2X2TS U962 ( .A(n1273), .B(n1271), .Y(n850) );
NOR2X2TS U963 ( .A(n456), .B(n885), .Y(n1238) );
OAI2BB2XLTS U964 ( .B0(n1029), .B1(n1036), .A0N(n1028), .A1N(n1027), .Y(
n1032) );
OAI211XLTS U965 ( .A0(intDX[8]), .A1(n1376), .B0(n1024), .C0(n1027), .Y(
n1038) );
AOI22X2TS U966 ( .A0(n1309), .A1(intDY[11]), .B0(n1294), .B1(intDY[10]), .Y(
n1027) );
OAI21X2TS U967 ( .A0(n1324), .A1(exp_oper_result[3]), .B0(n896), .Y(n1237)
);
OAI21X2TS U968 ( .A0(n1324), .A1(n1392), .B0(n901), .Y(n1239) );
OAI21X2TS U969 ( .A0(n1325), .A1(n1392), .B0(n1190), .Y(n1230) );
INVX2TS U970 ( .A(n422), .Y(n435) );
NOR2X4TS U971 ( .A(n1281), .B(LZA_output[4]), .Y(n805) );
NOR2X4TS U972 ( .A(n811), .B(n1246), .Y(n877) );
INVX2TS U973 ( .A(n844), .Y(n436) );
INVX2TS U974 ( .A(n844), .Y(n437) );
INVX2TS U975 ( .A(n844), .Y(n438) );
NAND2X4TS U976 ( .A(n814), .B(n536), .Y(n1247) );
OAI211X1TS U977 ( .A0(Sgf_normalized_result[1]), .A1(
Sgf_normalized_result[0]), .B0(n522), .C0(n521), .Y(n620) );
BUFX3TS U978 ( .A(n1308), .Y(n741) );
AOI22X2TS U979 ( .A0(n662), .A1(n755), .B0(n754), .B1(n852), .Y(n798) );
INVX2TS U980 ( .A(n421), .Y(n441) );
AOI22X2TS U981 ( .A0(n662), .A1(n743), .B0(n837), .B1(n852), .Y(n785) );
AOI22X2TS U982 ( .A0(n833), .A1(n790), .B0(n828), .B1(n789), .Y(n845) );
AOI22X2TS U983 ( .A0(n834), .A1(n740), .B0(n790), .B1(n852), .Y(n795) );
AOI22X2TS U984 ( .A0(n834), .A1(n828), .B0(n827), .B1(n1270), .Y(n856) );
AOI22X2TS U985 ( .A0(n833), .A1(n757), .B0(n756), .B1(n852), .Y(n793) );
AOI22X2TS U986 ( .A0(n834), .A1(n756), .B0(n826), .B1(n852), .Y(n841) );
AOI22X2TS U987 ( .A0(n834), .A1(n754), .B0(n832), .B1(n852), .Y(n840) );
AOI22X2TS U988 ( .A0(n662), .A1(n832), .B0(n1268), .B1(n852), .Y(n860) );
NOR2X4TS U989 ( .A(n886), .B(n428), .Y(n1195) );
INVX2TS U990 ( .A(n423), .Y(n442) );
INVX2TS U991 ( .A(n423), .Y(n443) );
INVX2TS U992 ( .A(n423), .Y(n444) );
NOR2X1TS U993 ( .A(Add_Subt_result[23]), .B(Add_Subt_result[22]), .Y(n1175)
);
BUFX3TS U994 ( .A(n457), .Y(n882) );
OAI221X1TS U995 ( .A0(n1321), .A1(intDY[3]), .B0(n1293), .B1(intDY[2]), .C0(
n483), .Y(n486) );
OAI221X1TS U996 ( .A0(n1328), .A1(intDY[16]), .B0(n1315), .B1(intDY[15]),
.C0(n495), .Y(n502) );
OAI221X1TS U997 ( .A0(n1289), .A1(intDY[24]), .B0(n1319), .B1(intDY[23]),
.C0(n503), .Y(n510) );
OAI221X1TS U998 ( .A0(n1341), .A1(intDY[7]), .B0(n1300), .B1(intDY[6]), .C0(
n1016), .Y(n494) );
MXI2X2TS U999 ( .A(n1349), .B(n1336), .S0(exp_oper_result[3]), .Y(n534) );
NAND2X2TS U1000 ( .A(n915), .B(exp_oper_result[4]), .Y(n1194) );
NOR2X2TS U1001 ( .A(n535), .B(n420), .Y(n899) );
AOI22X2TS U1002 ( .A0(n696), .A1(Add_Subt_result[10]), .B0(n1225), .B1(
Add_Subt_result[18]), .Y(n1183) );
AOI22X2TS U1003 ( .A0(n662), .A1(n663), .B0(n736), .B1(n789), .Y(n782) );
AOI22X2TS U1004 ( .A0(n833), .A1(n736), .B0(n755), .B1(n789), .Y(n773) );
AOI22X2TS U1005 ( .A0(n833), .A1(n747), .B0(n746), .B1(n789), .Y(n777) );
AOI22X2TS U1006 ( .A0(n834), .A1(n749), .B0(n748), .B1(n789), .Y(n774) );
AOI22X2TS U1007 ( .A0(n833), .A1(n746), .B0(n757), .B1(n789), .Y(n768) );
AOI22X2TS U1008 ( .A0(n662), .A1(n750), .B0(n743), .B1(n789), .Y(n794) );
AOI22X2TS U1009 ( .A0(n834), .A1(n751), .B0(n750), .B1(n789), .Y(n769) );
AOI22X2TS U1010 ( .A0(n833), .A1(n748), .B0(n740), .B1(n789), .Y(n770) );
BUFX3TS U1011 ( .A(n1415), .Y(n1418) );
BUFX3TS U1012 ( .A(n1417), .Y(n1415) );
NOR3X4TS U1013 ( .A(n449), .B(FS_Module_state_reg[2]), .C(
FS_Module_state_reg[0]), .Y(n1174) );
NOR4X2TS U1014 ( .A(FS_Module_state_reg[0]), .B(n449), .C(n1357), .D(n1284),
.Y(ready) );
NOR4X4TS U1015 ( .A(FS_Module_state_reg[0]), .B(n1357), .C(
FS_Module_state_reg[2]), .D(FS_Module_state_reg[3]), .Y(n1423) );
OAI21XLTS U1016 ( .A0(n1246), .A1(n799), .B0(n540), .Y(n1451) );
OAI211XLTS U1017 ( .A0(n895), .A1(n1243), .B0(n894), .C0(n893), .Y(n1436) );
OAI21XLTS U1018 ( .A0(n997), .A1(n1243), .B0(n904), .Y(n1430) );
OAI211XLTS U1019 ( .A0(n889), .A1(n1243), .B0(n888), .C0(n887), .Y(n1428) );
AOI222X1TS U1020 ( .A0(n1209), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(n1208), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .C0(n1207), .C1(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n1244) );
AOI222X1TS U1021 ( .A0(n1209), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n911), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .C0(n447), .C1(n1208),
.Y(n910) );
NOR2X2TS U1022 ( .A(overflow_flag), .B(underflow_flag), .Y(n1275) );
NAND2X2TS U1023 ( .A(n614), .B(add_overflow_flag), .Y(n1271) );
NOR2X2TS U1024 ( .A(Add_Subt_result[13]), .B(Add_Subt_result[11]), .Y(n1222)
);
NOR2X2TS U1025 ( .A(Add_Subt_result[6]), .B(Add_Subt_result[7]), .Y(n693) );
AOI31XLTS U1026 ( .A0(n686), .A1(Add_Subt_result[6]), .A2(n1380), .B0(n685),
.Y(n688) );
NOR2X4TS U1027 ( .A(n667), .B(n666), .Y(n445) );
OAI21X4TS U1028 ( .A0(FSM_selector_B[0]), .A1(n1338), .B0(n609), .Y(n666) );
INVX2TS U1029 ( .A(n446), .Y(n447) );
INVX2TS U1030 ( .A(n1063), .Y(n1198) );
CLKBUFX2TS U1031 ( .A(n1198), .Y(n1196) );
CLKBUFX2TS U1032 ( .A(n1261), .Y(n1197) );
BUFX3TS U1033 ( .A(n1063), .Y(n1220) );
OR2X1TS U1034 ( .A(n945), .B(n944), .Y(n450) );
NOR2XLTS U1035 ( .A(n1366), .B(intDX[11]), .Y(n1022) );
OAI21XLTS U1036 ( .A0(intDX[21]), .A1(n1361), .B0(intDX[20]), .Y(n1042) );
OR2X1TS U1037 ( .A(Sgf_normalized_result[2]), .B(n983), .Y(n544) );
NOR2X1TS U1038 ( .A(n1282), .B(FSM_selector_B[1]), .Y(n457) );
OR2X1TS U1039 ( .A(n947), .B(n946), .Y(n1109) );
OAI21X2TS U1040 ( .A0(n1133), .A1(n567), .B0(n566), .Y(n941) );
OR2X1TS U1041 ( .A(n977), .B(n976), .Y(n1076) );
AOI31XLTS U1042 ( .A0(n1225), .A1(n1224), .A2(n1334), .B0(n1223), .Y(n1226)
);
XOR2X1TS U1043 ( .A(n925), .B(n462), .Y(n478) );
NOR2XLTS U1044 ( .A(n1270), .B(n1185), .Y(n1186) );
NOR2X4TS U1045 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[1]), .Y(
n1169) );
NAND3X2TS U1046 ( .A(n1169), .B(n1284), .C(n1310), .Y(n400) );
BUFX3TS U1047 ( .A(n1308), .Y(n786) );
AOI21X1TS U1048 ( .A0(n610), .A1(n786), .B0(FS_Module_state_reg[0]), .Y(n453) );
NOR2X2TS U1049 ( .A(FS_Module_state_reg[2]), .B(n1310), .Y(n611) );
AOI21X1TS U1050 ( .A0(n611), .A1(FS_Module_state_reg[3]), .B0(n1169), .Y(
n451) );
OAI211X4TS U1051 ( .A0(n453), .A1(FS_Module_state_reg[1]), .B0(n452), .C0(
n400), .Y(n925) );
INVX2TS U1052 ( .A(n456), .Y(n915) );
BUFX3TS U1053 ( .A(FSM_selector_D), .Y(n917) );
INVX2TS U1054 ( .A(n456), .Y(n606) );
OAI2BB1X1TS U1055 ( .A0N(DmP[27]), .A1N(n606), .B0(n900), .Y(n458) );
BUFX3TS U1056 ( .A(FSM_selector_D), .Y(n980) );
INVX2TS U1057 ( .A(n882), .Y(n644) );
OAI2BB2XLTS U1058 ( .B0(n644), .B1(n1281), .A0N(n915), .A1N(DmP[26]), .Y(
n459) );
NAND2X1TS U1059 ( .A(n882), .B(LZA_output[2]), .Y(n605) );
OAI2BB1X1TS U1060 ( .A0N(DmP[25]), .A1N(n915), .B0(n605), .Y(n460) );
NAND2X1TS U1061 ( .A(n882), .B(LZA_output[1]), .Y(n608) );
OAI2BB1X1TS U1062 ( .A0N(DmP[24]), .A1N(n606), .B0(n608), .Y(n461) );
AOI22X1TS U1063 ( .A0(n457), .A1(LZA_output[0]), .B0(FSM_selector_B[1]),
.B1(n1282), .Y(n609) );
OAI2BB1X1TS U1064 ( .A0N(DmP[23]), .A1N(n1282), .B0(n609), .Y(n462) );
AFHCINX2TS U1065 ( .CIN(n463), .B(n464), .A(n465), .S(
Exp_Operation_Module_Data_S[5]), .CO(n918) );
AFHCONX2TS U1066 ( .A(n468), .B(n467), .CI(n466), .CON(n463), .S(
Exp_Operation_Module_Data_S[4]) );
AFHCINX2TS U1067 ( .CIN(n469), .B(n470), .A(n471), .S(
Exp_Operation_Module_Data_S[3]), .CO(n466) );
AFHCONX2TS U1068 ( .A(n474), .B(n473), .CI(n472), .CON(n469), .S(
Exp_Operation_Module_Data_S[2]) );
AFHCINX2TS U1069 ( .CIN(n475), .B(n476), .A(n477), .S(
Exp_Operation_Module_Data_S[1]), .CO(n472) );
AFHCONX2TS U1070 ( .A(n479), .B(n925), .CI(n478), .CON(n475), .S(
Exp_Operation_Module_Data_S[0]) );
INVX2TS U1071 ( .A(n1174), .Y(n480) );
NOR2XLTS U1072 ( .A(FS_Module_state_reg[1]), .B(n480), .Y(FSM_LZA_load) );
INVX2TS U1073 ( .A(rst), .Y(n1424) );
CLKBUFX2TS U1074 ( .A(n1424), .Y(n1417) );
OAI2BB2X1TS U1075 ( .B0(n481), .B1(FS_Module_state_reg[0]), .A0N(n611),
.A1N(FS_Module_state_reg[1]), .Y(FSM_exp_operation_load_diff) );
AOI22X1TS U1076 ( .A0(intDX[30]), .A1(intDY[30]), .B0(n1299), .B1(n1332),
.Y(n488) );
AOI22X1TS U1077 ( .A0(n1323), .A1(intDY[1]), .B0(n1298), .B1(intDY[0]), .Y(
n482) );
AOI22X1TS U1078 ( .A0(n1321), .A1(intDY[3]), .B0(n1293), .B1(intDY[2]), .Y(
n483) );
AOI22X1TS U1079 ( .A0(n1327), .A1(intDY[5]), .B0(n1295), .B1(intDY[4]), .Y(
n484) );
OAI221XLTS U1080 ( .A0(n1327), .A1(intDY[5]), .B0(n1295), .B1(intDY[4]),
.C0(n484), .Y(n485) );
NOR4X1TS U1081 ( .A(n488), .B(n487), .C(n486), .D(n485), .Y(n514) );
AOI22X1TS U1082 ( .A0(intDY[7]), .A1(n1341), .B0(intDY[6]), .B1(n1300), .Y(
n1016) );
AOI22X1TS U1083 ( .A0(n1292), .A1(intDY[9]), .B0(n1322), .B1(intDY[8]), .Y(
n489) );
OAI221XLTS U1084 ( .A0(n1292), .A1(intDY[9]), .B0(n1322), .B1(intDY[8]),
.C0(n489), .Y(n493) );
AOI22X1TS U1085 ( .A0(n1285), .A1(intDY[14]), .B0(n1314), .B1(intDY[13]),
.Y(n490) );
OAI221XLTS U1086 ( .A0(n1285), .A1(intDY[14]), .B0(n1314), .B1(intDY[13]),
.C0(n490), .Y(n491) );
NOR4X1TS U1087 ( .A(n494), .B(n493), .C(n492), .D(n491), .Y(n513) );
AOI22X1TS U1088 ( .A0(n1328), .A1(intDY[16]), .B0(n1315), .B1(intDY[15]),
.Y(n495) );
AOI22X1TS U1089 ( .A0(n1286), .A1(intDY[18]), .B0(n1312), .B1(intDY[17]),
.Y(n496) );
OAI221XLTS U1090 ( .A0(n1286), .A1(intDY[18]), .B0(n1312), .B1(intDY[17]),
.C0(n496), .Y(n501) );
AOI22X1TS U1091 ( .A0(n1287), .A1(intDY[20]), .B0(n1313), .B1(intDY[19]),
.Y(n497) );
AOI22X1TS U1092 ( .A0(n1288), .A1(intDY[22]), .B0(n1316), .B1(intDY[21]),
.Y(n498) );
OAI221XLTS U1093 ( .A0(n1288), .A1(intDY[22]), .B0(n1316), .B1(intDY[21]),
.C0(n498), .Y(n499) );
NOR4X1TS U1094 ( .A(n502), .B(n501), .C(n500), .D(n499), .Y(n512) );
AOI22X1TS U1095 ( .A0(n1289), .A1(intDY[24]), .B0(n1319), .B1(intDY[23]),
.Y(n503) );
AOI22X1TS U1096 ( .A0(n1290), .A1(intDY[26]), .B0(n1318), .B1(intDY[25]),
.Y(n504) );
OAI221XLTS U1097 ( .A0(n1290), .A1(intDY[26]), .B0(n1318), .B1(intDY[25]),
.C0(n504), .Y(n509) );
AOI22X1TS U1098 ( .A0(n1326), .A1(intDY[28]), .B0(n1291), .B1(intDY[27]),
.Y(n505) );
AOI22X1TS U1099 ( .A0(n1317), .A1(intDY[29]), .B0(n1311), .B1(intDX[12]),
.Y(n506) );
OAI221XLTS U1100 ( .A0(n1317), .A1(intDY[29]), .B0(n1311), .B1(intDX[12]),
.C0(n506), .Y(n507) );
NOR4X1TS U1101 ( .A(n510), .B(n509), .C(n508), .D(n507), .Y(n511) );
NAND4X1TS U1102 ( .A(n514), .B(n513), .C(n512), .D(n511), .Y(n1168) );
INVX2TS U1103 ( .A(n1278), .Y(n515) );
NOR2X2TS U1104 ( .A(FS_Module_state_reg[1]), .B(n449), .Y(n613) );
AOI211X1TS U1105 ( .A0(n741), .A1(n515), .B0(FSM_exp_operation_load_diff),
.C0(n613), .Y(n516) );
NAND2X1TS U1106 ( .A(n622), .B(n516), .Y(FS_Module_state_next[2]) );
BUFX3TS U1107 ( .A(n1415), .Y(n1403) );
BUFX3TS U1108 ( .A(n1415), .Y(n1404) );
BUFX3TS U1109 ( .A(n1424), .Y(n1405) );
CLKBUFX2TS U1110 ( .A(n1424), .Y(n1413) );
BUFX3TS U1111 ( .A(n1413), .Y(n1409) );
BUFX3TS U1112 ( .A(n1417), .Y(n1400) );
BUFX3TS U1113 ( .A(n1417), .Y(n1399) );
CLKBUFX2TS U1114 ( .A(n1413), .Y(n517) );
BUFX3TS U1115 ( .A(n517), .Y(n1398) );
BUFX3TS U1116 ( .A(n1413), .Y(n1410) );
BUFX3TS U1117 ( .A(n1424), .Y(n1406) );
BUFX3TS U1118 ( .A(n1413), .Y(n1411) );
CLKBUFX3TS U1119 ( .A(n1418), .Y(n1414) );
BUFX3TS U1120 ( .A(n1414), .Y(n1408) );
BUFX3TS U1121 ( .A(n1414), .Y(n1407) );
BUFX3TS U1122 ( .A(n517), .Y(n1412) );
BUFX3TS U1123 ( .A(n1418), .Y(n1395) );
BUFX3TS U1124 ( .A(n517), .Y(n1416) );
BUFX3TS U1125 ( .A(n1416), .Y(n1420) );
BUFX3TS U1126 ( .A(n1420), .Y(n1419) );
BUFX3TS U1127 ( .A(n1419), .Y(n1394) );
BUFX3TS U1128 ( .A(n517), .Y(n1397) );
BUFX3TS U1129 ( .A(n1418), .Y(n1396) );
BUFX3TS U1130 ( .A(n1419), .Y(n1393) );
INVX2TS U1131 ( .A(ready), .Y(n518) );
OA22X1TS U1132 ( .A0(ack_FSM), .A1(n518), .B0(beg_FSM), .B1(n400), .Y(n412)
);
INVX2TS U1133 ( .A(r_mode[1]), .Y(n519) );
INVX2TS U1134 ( .A(r_mode[0]), .Y(n520) );
NAND2X1TS U1135 ( .A(n611), .B(n613), .Y(n1171) );
NOR2X1TS U1136 ( .A(n620), .B(n1171), .Y(n525) );
BUFX3TS U1137 ( .A(FSM_selector_D), .Y(n984) );
BUFX3TS U1138 ( .A(n1416), .Y(n1402) );
BUFX3TS U1139 ( .A(n1416), .Y(n1401) );
OAI21XLTS U1140 ( .A0(FS_Module_state_reg[1]), .A1(add_overflow_flag), .B0(
n1174), .Y(n523) );
INVX2TS U1141 ( .A(FSM_Add_Subt_Sgf_load), .Y(n524) );
AOI211X1TS U1142 ( .A0(FS_Module_state_reg[0]), .A1(FSM_Add_Subt_Sgf_load),
.B0(n1423), .C0(FSM_Final_Result_load), .Y(n527) );
NAND2X1TS U1143 ( .A(FS_Module_state_reg[1]), .B(n1174), .Y(n621) );
NOR3BX1TS U1144 ( .AN(n621), .B(n525), .C(n411), .Y(n526) );
BUFX3TS U1145 ( .A(n1308), .Y(n823) );
NOR2X1TS U1146 ( .A(n823), .B(FS_Module_state_reg[3]), .Y(n528) );
NOR2X2TS U1147 ( .A(n529), .B(n528), .Y(n812) );
INVX2TS U1148 ( .A(n812), .Y(n1246) );
AOI22X1TS U1149 ( .A0(n1392), .A1(n1336), .B0(n1349), .B1(n1281), .Y(n533)
);
NAND2X1TS U1150 ( .A(n606), .B(n1283), .Y(n535) );
INVX2TS U1151 ( .A(n535), .Y(n1211) );
OAI21X4TS U1152 ( .A0(FS_Module_state_reg[3]), .A1(FSM_selector_C), .B0(
add_overflow_flag), .Y(n885) );
NOR2X2TS U1153 ( .A(n644), .B(n885), .Y(n1240) );
NOR2X1TS U1154 ( .A(n420), .B(FSM_selector_B[1]), .Y(n645) );
NAND2X1TS U1155 ( .A(n644), .B(n532), .Y(n807) );
NOR3X4TS U1156 ( .A(n823), .B(FS_Module_state_reg[3]), .C(add_overflow_flag),
.Y(n1252) );
AOI22X1TS U1157 ( .A0(n1240), .A1(n533), .B0(n447), .B1(n426), .Y(n539) );
AOI22X1TS U1158 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[38]), .A1(
n425), .B0(n1238), .B1(n534), .Y(n538) );
AOI22X1TS U1159 ( .A0(n805), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n441), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .Y(n804) );
NAND2X2TS U1160 ( .A(n882), .B(n1252), .Y(n700) );
NAND2X2TS U1161 ( .A(n899), .B(n1252), .Y(n881) );
OAI22X1TS U1162 ( .A0(n804), .A1(n700), .B0(n1329), .B1(n881), .Y(n537) );
INVX2TS U1163 ( .A(n885), .Y(n814) );
NAND2X1TS U1164 ( .A(n900), .B(n1194), .Y(n536) );
INVX2TS U1165 ( .A(n1247), .Y(n1215) );
NOR4BBX1TS U1166 ( .AN(n539), .BN(n538), .C(n537), .D(n1215), .Y(n540) );
INVX2TS U1167 ( .A(n541), .Y(n1167) );
OR2X4TS U1168 ( .A(n1167), .B(n983), .Y(n987) );
XOR2X1TS U1169 ( .A(n570), .B(Sgf_normalized_result[1]), .Y(n543) );
NOR2X2TS U1170 ( .A(n543), .B(n542), .Y(n1164) );
XOR2X1TS U1171 ( .A(n570), .B(n544), .Y(n549) );
NOR2X1TS U1172 ( .A(n1164), .B(n1158), .Y(n551) );
NOR2BX1TS U1173 ( .AN(Sgf_normalized_result[0]), .B(n983), .Y(n545) );
XOR2X1TS U1174 ( .A(n986), .B(n545), .Y(n1165) );
INVX2TS U1175 ( .A(n1165), .Y(n547) );
NOR2X1TS U1176 ( .A(n986), .B(n546), .Y(n1166) );
NOR2X1TS U1177 ( .A(n547), .B(n1166), .Y(n1157) );
NAND2X1TS U1178 ( .A(n549), .B(n548), .Y(n1159) );
INVX2TS U1179 ( .A(n1159), .Y(n550) );
NOR2BX1TS U1180 ( .AN(Sgf_normalized_result[3]), .B(n983), .Y(n552) );
XOR2X1TS U1181 ( .A(n570), .B(n552), .Y(n557) );
NOR2X1TS U1182 ( .A(n557), .B(n556), .Y(n1146) );
NOR2BX1TS U1183 ( .AN(Sgf_normalized_result[4]), .B(n983), .Y(n553) );
XOR2X1TS U1184 ( .A(n570), .B(n553), .Y(n559) );
NOR2X2TS U1185 ( .A(n559), .B(n558), .Y(n1148) );
NOR2X1TS U1186 ( .A(n1146), .B(n1148), .Y(n1135) );
NOR2BX1TS U1187 ( .AN(Sgf_normalized_result[5]), .B(n983), .Y(n554) );
XOR2X1TS U1188 ( .A(n570), .B(n554), .Y(n561) );
NOR2X2TS U1189 ( .A(n561), .B(n560), .Y(n1141) );
NOR2BX1TS U1190 ( .AN(Sgf_normalized_result[6]), .B(n983), .Y(n555) );
XOR2X1TS U1191 ( .A(n570), .B(n555), .Y(n563) );
NOR2X2TS U1192 ( .A(n563), .B(n562), .Y(n1136) );
NAND2X1TS U1193 ( .A(n557), .B(n556), .Y(n1153) );
NAND2X1TS U1194 ( .A(n559), .B(n558), .Y(n1149) );
OAI21X1TS U1195 ( .A0(n1148), .A1(n1153), .B0(n1149), .Y(n1134) );
NAND2X1TS U1196 ( .A(n561), .B(n560), .Y(n1142) );
NAND2X1TS U1197 ( .A(n563), .B(n562), .Y(n1137) );
AOI21X1TS U1198 ( .A0(n1134), .A1(n565), .B0(n564), .Y(n566) );
BUFX3TS U1199 ( .A(FSM_selector_D), .Y(n966) );
NOR2BX1TS U1200 ( .AN(Sgf_normalized_result[7]), .B(n966), .Y(n568) );
XOR2X1TS U1201 ( .A(n570), .B(n568), .Y(n574) );
NOR2X2TS U1202 ( .A(n574), .B(n573), .Y(n1128) );
NOR2BX1TS U1203 ( .AN(Sgf_normalized_result[8]), .B(n966), .Y(n569) );
XOR2X1TS U1204 ( .A(n570), .B(n569), .Y(n576) );
NOR2X2TS U1205 ( .A(n576), .B(n575), .Y(n1123) );
NOR2X1TS U1206 ( .A(n1128), .B(n1123), .Y(n593) );
INVX4TS U1207 ( .A(n987), .Y(n968) );
NOR2BX1TS U1208 ( .AN(Sgf_normalized_result[9]), .B(n983), .Y(n571) );
XOR2X1TS U1209 ( .A(n968), .B(n571), .Y(n578) );
BUFX3TS U1210 ( .A(FSM_selector_D), .Y(n956) );
NOR2X1TS U1211 ( .A(n578), .B(n577), .Y(n597) );
NOR2BX1TS U1212 ( .AN(Sgf_normalized_result[10]), .B(n966), .Y(n572) );
XOR2X1TS U1213 ( .A(n968), .B(n572), .Y(n580) );
NOR2X2TS U1214 ( .A(n580), .B(n579), .Y(n599) );
NAND2X1TS U1215 ( .A(n576), .B(n575), .Y(n1124) );
OAI21X1TS U1216 ( .A0(n1123), .A1(n1129), .B0(n1124), .Y(n594) );
NAND2X1TS U1217 ( .A(n578), .B(n577), .Y(n1119) );
NAND2X1TS U1218 ( .A(n580), .B(n579), .Y(n600) );
AOI21X1TS U1219 ( .A0(n594), .A1(n582), .B0(n581), .Y(n938) );
OAI21X1TS U1220 ( .A0(n1132), .A1(n930), .B0(n938), .Y(n625) );
NOR2BX1TS U1221 ( .AN(Sgf_normalized_result[11]), .B(n966), .Y(n583) );
XOR2X1TS U1222 ( .A(n968), .B(n583), .Y(n585) );
NOR2X1TS U1223 ( .A(n585), .B(n584), .Y(n707) );
INVX2TS U1224 ( .A(n707), .Y(n626) );
NAND2X1TS U1225 ( .A(n585), .B(n584), .Y(n709) );
INVX2TS U1226 ( .A(n709), .Y(n586) );
AOI21X1TS U1227 ( .A0(n625), .A1(n626), .B0(n586), .Y(n592) );
NOR2BX1TS U1228 ( .AN(Sgf_normalized_result[12]), .B(n966), .Y(n587) );
XOR2X1TS U1229 ( .A(n968), .B(n587), .Y(n589) );
NOR2X2TS U1230 ( .A(n589), .B(n588), .Y(n710) );
INVX2TS U1231 ( .A(n710), .Y(n590) );
NAND2X1TS U1232 ( .A(n589), .B(n588), .Y(n708) );
NAND2X1TS U1233 ( .A(n590), .B(n708), .Y(n591) );
INVX2TS U1234 ( .A(n593), .Y(n596) );
OAI21X1TS U1235 ( .A0(n1132), .A1(n596), .B0(n595), .Y(n1122) );
INVX2TS U1236 ( .A(n597), .Y(n1120) );
INVX2TS U1237 ( .A(n1119), .Y(n598) );
AOI21X1TS U1238 ( .A0(n1122), .A1(n1120), .B0(n598), .Y(n603) );
INVX2TS U1239 ( .A(n599), .Y(n601) );
NAND2X1TS U1240 ( .A(n601), .B(n600), .Y(n602) );
NAND2X1TS U1241 ( .A(n606), .B(exp_oper_result[2]), .Y(n604) );
AND2X2TS U1242 ( .A(n605), .B(n604), .Y(n662) );
INVX2TS U1243 ( .A(n662), .Y(n1270) );
NAND2X1TS U1244 ( .A(n606), .B(exp_oper_result[1]), .Y(n607) );
INVX2TS U1245 ( .A(n667), .Y(n1185) );
INVX2TS U1246 ( .A(n442), .Y(n849) );
NAND3X1TS U1247 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[3]),
.C(n611), .Y(n989) );
NAND3X1TS U1248 ( .A(FS_Module_state_reg[2]), .B(n613), .C(n1310), .Y(n1279)
);
INVX2TS U1249 ( .A(n990), .Y(n615) );
NAND2X2TS U1250 ( .A(n615), .B(n1307), .Y(n787) );
NAND2X2TS U1251 ( .A(n787), .B(FSM_selector_C), .Y(n726) );
NOR2X1TS U1252 ( .A(n726), .B(Add_Subt_result[25]), .Y(n617) );
NOR2X1TS U1253 ( .A(n787), .B(Add_Subt_result[0]), .Y(n616) );
NOR2X2TS U1254 ( .A(n617), .B(n616), .Y(n1267) );
INVX2TS U1255 ( .A(n673), .Y(n833) );
INVX2TS U1256 ( .A(n620), .Y(n624) );
OAI211X1TS U1257 ( .A0(n741), .A1(n1278), .B0(n1279), .C0(n621), .Y(n1173)
);
NOR4BX1TS U1258 ( .AN(n989), .B(FSM_Add_Subt_Sgf_load), .C(
FSM_Final_Result_load), .D(n1173), .Y(n623) );
INVX2TS U1259 ( .A(n625), .Y(n713) );
NAND2X1TS U1260 ( .A(n626), .B(n709), .Y(n627) );
AOI2BB1X1TS U1261 ( .A0N(n1379), .A1N(Add_Subt_result[1]), .B0(
Add_Subt_result[2]), .Y(n689) );
NOR2BX1TS U1262 ( .AN(n689), .B(Add_Subt_result[3]), .Y(n641) );
INVX2TS U1263 ( .A(n636), .Y(n628) );
NOR2X1TS U1264 ( .A(Add_Subt_result[25]), .B(Add_Subt_result[24]), .Y(n1179)
);
NAND2X1TS U1265 ( .A(n1179), .B(n1175), .Y(n635) );
NOR2X2TS U1266 ( .A(n628), .B(n635), .Y(n1225) );
NAND2X1TS U1267 ( .A(n1297), .B(n629), .Y(n1224) );
NOR3X1TS U1268 ( .A(n1224), .B(Add_Subt_result[18]), .C(Add_Subt_result[14]),
.Y(n630) );
NAND2X1TS U1269 ( .A(n1222), .B(n1296), .Y(n633) );
NOR2X2TS U1270 ( .A(n1221), .B(n633), .Y(n696) );
NOR3X1TS U1271 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[10]), .C(
Add_Subt_result[8]), .Y(n631) );
NAND2X1TS U1272 ( .A(n693), .B(n1280), .Y(n632) );
INVX2TS U1273 ( .A(n690), .Y(n678) );
INVX2TS U1274 ( .A(n692), .Y(n686) );
INVX2TS U1275 ( .A(n1221), .Y(n1180) );
NAND2X1TS U1276 ( .A(n1180), .B(n633), .Y(n634) );
INVX2TS U1277 ( .A(n638), .Y(n639) );
INVX2TS U1278 ( .A(n694), .Y(n687) );
NAND2X1TS U1279 ( .A(n915), .B(exp_oper_result[3]), .Y(n883) );
NOR2X1TS U1280 ( .A(n885), .B(n883), .Y(n809) );
INVX2TS U1281 ( .A(n1240), .Y(n648) );
NOR2X1TS U1282 ( .A(n1281), .B(n648), .Y(n808) );
NAND2X1TS U1283 ( .A(n899), .B(n812), .Y(n642) );
INVX2TS U1284 ( .A(n807), .Y(n813) );
NAND2X1TS U1285 ( .A(n812), .B(n813), .Y(n646) );
AOI22X1TS U1286 ( .A0(n805), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n441), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(n654) );
OAI22X1TS U1287 ( .A0(n654), .A1(n700), .B0(n1337), .B1(n881), .Y(n649) );
AOI211X1TS U1288 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[40]), .A1(
n801), .B0(n1215), .C0(n649), .Y(n651) );
AOI22X1TS U1289 ( .A0(n805), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n441), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(n652) );
NAND2X2TS U1290 ( .A(n812), .B(n882), .Y(n803) );
OAI22X1TS U1291 ( .A0(n652), .A1(n700), .B0(n1330), .B1(n881), .Y(n653) );
AOI211X1TS U1292 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[37]), .A1(
n801), .B0(n1215), .C0(n653), .Y(n656) );
AOI22X1TS U1293 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[36]), .A1(
n441), .B0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .B1(n805),
.Y(n703) );
OAI22X1TS U1294 ( .A0(n703), .A1(n700), .B0(n1333), .B1(n881), .Y(n657) );
AOI211X1TS U1295 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[41]), .A1(
n801), .B0(n1215), .C0(n657), .Y(n659) );
AOI22X1TS U1296 ( .A0(n805), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n441), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(n701) );
INVX2TS U1297 ( .A(n673), .Y(n834) );
AOI22X1TS U1298 ( .A0(n431), .A1(Add_Subt_result[22]), .B0(DmP[1]), .B1(n823), .Y(n660) );
OAI2BB1X1TS U1299 ( .A0N(Add_Subt_result[3]), .A1N(n433), .B0(n660), .Y(n663) );
AOI22X1TS U1300 ( .A0(n430), .A1(Add_Subt_result[18]), .B0(DmP[5]), .B1(n823), .Y(n661) );
OAI2BB1X1TS U1301 ( .A0N(Add_Subt_result[7]), .A1N(n433), .B0(n661), .Y(n736) );
INVX2TS U1302 ( .A(n662), .Y(n673) );
BUFX3TS U1303 ( .A(n673), .Y(n789) );
NAND2X2TS U1304 ( .A(n1185), .B(n666), .Y(n844) );
NAND2X2TS U1305 ( .A(n666), .B(n667), .Y(n859) );
AOI22X1TS U1306 ( .A0(n434), .A1(Add_Subt_result[1]), .B0(n431), .B1(
Add_Subt_result[24]), .Y(n665) );
AOI21X1TS U1307 ( .A0(Add_Subt_result[5]), .A1(n433), .B0(n664), .Y(n749) );
AOI22X1TS U1308 ( .A0(n834), .A1(n665), .B0(n749), .B1(n789), .Y(n779) );
AOI22X1TS U1309 ( .A0(n430), .A1(Add_Subt_result[23]), .B0(DmP[0]), .B1(n823), .Y(n670) );
INVX2TS U1310 ( .A(n1270), .Y(n1273) );
NAND2X1TS U1311 ( .A(n433), .B(Add_Subt_result[2]), .Y(n669) );
OAI2BB2XLTS U1312 ( .B0(n787), .B1(n1342), .A0N(DmP[4]), .A1N(n786), .Y(n668) );
AOI21X1TS U1313 ( .A0(n434), .A1(Add_Subt_result[6]), .B0(n668), .Y(n751) );
AOI22X1TS U1314 ( .A0(n440), .A1(n779), .B0(n445), .B1(n778), .Y(n677) );
OAI2BB2XLTS U1315 ( .B0(n787), .B1(n1339), .A0N(DmP[2]), .A1N(n786), .Y(n671) );
NOR2X1TS U1316 ( .A(n672), .B(n671), .Y(n747) );
INVX2TS U1317 ( .A(n747), .Y(n675) );
BUFX3TS U1318 ( .A(n673), .Y(n852) );
OAI22X1TS U1319 ( .A0(n726), .A1(n1379), .B0(n1302), .B1(n787), .Y(n674) );
OAI221XLTS U1320 ( .A0(n1273), .A1(n675), .B0(n852), .B1(n674), .C0(n442),
.Y(n676) );
NOR2X1TS U1321 ( .A(n678), .B(Add_Subt_result[3]), .Y(n697) );
INVX2TS U1322 ( .A(n697), .Y(n699) );
INVX2TS U1323 ( .A(n1225), .Y(n1176) );
NOR4BX1TS U1324 ( .AN(Add_Subt_result[14]), .B(n1176), .C(
Add_Subt_result[18]), .D(n1224), .Y(n679) );
AOI31X1TS U1325 ( .A0(n1180), .A1(Add_Subt_result[12]), .A2(n1355), .B0(n679), .Y(n1227) );
AOI21X1TS U1326 ( .A0(n1339), .A1(Add_Subt_result[20]), .B0(
Add_Subt_result[22]), .Y(n680) );
OAI21X1TS U1327 ( .A0(n693), .A1(n692), .B0(n691), .Y(n1184) );
AOI211X1TS U1328 ( .A0(n696), .A1(n695), .B0(n1184), .C0(n694), .Y(n698) );
INVX2TS U1329 ( .A(n806), .Y(n1206) );
OAI22X1TS U1330 ( .A0(n701), .A1(n700), .B0(n1331), .B1(n881), .Y(n705) );
AOI22X1TS U1331 ( .A0(n801), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .B1(n426), .Y(n702)
);
AOI211X1TS U1332 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1206), .B0(n705), .C0(n704), .Y(n706) );
INVX2TS U1333 ( .A(n706), .Y(n1447) );
INVX2TS U1334 ( .A(n929), .Y(n712) );
OAI21X1TS U1335 ( .A0(n710), .A1(n709), .B0(n708), .Y(n935) );
INVX2TS U1336 ( .A(n935), .Y(n711) );
OAI21X1TS U1337 ( .A0(n713), .A1(n712), .B0(n711), .Y(n1118) );
NOR2BX1TS U1338 ( .AN(Sgf_normalized_result[13]), .B(n966), .Y(n714) );
XOR2X1TS U1339 ( .A(n968), .B(n714), .Y(n716) );
INVX2TS U1340 ( .A(n928), .Y(n1116) );
NAND2X1TS U1341 ( .A(n716), .B(n715), .Y(n1115) );
INVX2TS U1342 ( .A(n1115), .Y(n717) );
AOI21X1TS U1343 ( .A0(n1118), .A1(n1116), .B0(n717), .Y(n723) );
NOR2BX1TS U1344 ( .AN(Sgf_normalized_result[14]), .B(n966), .Y(n718) );
XOR2X1TS U1345 ( .A(n968), .B(n718), .Y(n720) );
NOR2X2TS U1346 ( .A(n720), .B(n719), .Y(n932) );
INVX2TS U1347 ( .A(n932), .Y(n721) );
NAND2X1TS U1348 ( .A(n720), .B(n719), .Y(n931) );
NAND2X1TS U1349 ( .A(n721), .B(n931), .Y(n722) );
AOI22X1TS U1350 ( .A0(n431), .A1(Add_Subt_result[10]), .B0(DmP[13]), .B1(
n823), .Y(n724) );
OAI2BB1X1TS U1351 ( .A0N(Add_Subt_result[15]), .A1N(n434), .B0(n724), .Y(
n754) );
AOI22X1TS U1352 ( .A0(n430), .A1(Add_Subt_result[6]), .B0(DmP[17]), .B1(n823), .Y(n725) );
OAI21X1TS U1353 ( .A0(n1342), .A1(n726), .B0(n725), .Y(n832) );
INVX2TS U1354 ( .A(n1266), .Y(n848) );
AOI21X1TS U1355 ( .A0(n434), .A1(Add_Subt_result[13]), .B0(n727), .Y(n740)
);
AOI21X1TS U1356 ( .A0(n433), .A1(Add_Subt_result[17]), .B0(n728), .Y(n790)
);
AOI21X1TS U1357 ( .A0(Add_Subt_result[14]), .A1(n432), .B0(n729), .Y(n743)
);
AOI21X1TS U1358 ( .A0(Add_Subt_result[18]), .A1(n432), .B0(n730), .Y(n837)
);
AOI22X1TS U1359 ( .A0(n444), .A1(n795), .B0(n440), .B1(n785), .Y(n734) );
AOI21X1TS U1360 ( .A0(Add_Subt_result[16]), .A1(n432), .B0(n731), .Y(n756)
);
AOI21X1TS U1361 ( .A0(Add_Subt_result[20]), .A1(n432), .B0(n732), .Y(n826)
);
NAND2X1TS U1362 ( .A(n438), .B(n841), .Y(n733) );
AOI22X1TS U1363 ( .A0(n430), .A1(Add_Subt_result[14]), .B0(DmP[9]), .B1(n786), .Y(n735) );
OAI2BB1X1TS U1364 ( .A0N(Add_Subt_result[11]), .A1N(n433), .B0(n735), .Y(
n755) );
AOI21X1TS U1365 ( .A0(Add_Subt_result[8]), .A1(n432), .B0(n737), .Y(n746) );
AOI21X1TS U1366 ( .A0(Add_Subt_result[12]), .A1(n432), .B0(n738), .Y(n757)
);
AOI21X1TS U1367 ( .A0(n433), .A1(Add_Subt_result[9]), .B0(n739), .Y(n748) );
AOI22X1TS U1368 ( .A0(n439), .A1(n768), .B0(n445), .B1(n770), .Y(n745) );
AOI21X1TS U1369 ( .A0(Add_Subt_result[10]), .A1(n432), .B0(n742), .Y(n750)
);
NAND2X1TS U1370 ( .A(n438), .B(n794), .Y(n744) );
AOI22X1TS U1371 ( .A0(n439), .A1(n777), .B0(n445), .B1(n774), .Y(n753) );
NAND2X1TS U1372 ( .A(n437), .B(n769), .Y(n752) );
AOI22X1TS U1373 ( .A0(n444), .A1(n770), .B0(n439), .B1(n794), .Y(n759) );
NAND2X1TS U1374 ( .A(n438), .B(n793), .Y(n758) );
AOI22X1TS U1375 ( .A0(n444), .A1(n774), .B0(n439), .B1(n769), .Y(n761) );
NAND2X1TS U1376 ( .A(n437), .B(n768), .Y(n760) );
AOI22X1TS U1377 ( .A0(n443), .A1(n768), .B0(n440), .B1(n770), .Y(n763) );
NAND2X1TS U1378 ( .A(n1266), .B(n794), .Y(n762) );
AOI22X1TS U1379 ( .A0(n444), .A1(n777), .B0(n440), .B1(n774), .Y(n765) );
NAND2X1TS U1380 ( .A(n445), .B(n769), .Y(n764) );
AOI22X1TS U1381 ( .A0(n443), .A1(n793), .B0(n440), .B1(n795), .Y(n767) );
NAND2X1TS U1382 ( .A(n445), .B(n785), .Y(n766) );
AOI22X1TS U1383 ( .A0(n443), .A1(n769), .B0(n445), .B1(n768), .Y(n772) );
NAND2X1TS U1384 ( .A(n437), .B(n770), .Y(n771) );
AOI22X1TS U1385 ( .A0(n443), .A1(n778), .B0(n445), .B1(n777), .Y(n776) );
NAND2X1TS U1386 ( .A(n438), .B(n774), .Y(n775) );
AOI22X1TS U1387 ( .A0(n440), .A1(n778), .B0(n438), .B1(n777), .Y(n781) );
NAND2X1TS U1388 ( .A(n444), .B(n779), .Y(n780) );
AOI22X1TS U1389 ( .A0(n439), .A1(n793), .B0(n445), .B1(n795), .Y(n784) );
NAND2X1TS U1390 ( .A(n436), .B(n785), .Y(n783) );
AOI22X1TS U1391 ( .A0(n443), .A1(n785), .B0(n1266), .B1(n841), .Y(n792) );
OAI2BB2XLTS U1392 ( .B0(n787), .B1(n1340), .A0N(DmP[19]), .A1N(n786), .Y(
n788) );
AOI21X1TS U1393 ( .A0(n434), .A1(Add_Subt_result[21]), .B0(n788), .Y(n828)
);
NAND2X1TS U1394 ( .A(n436), .B(n845), .Y(n791) );
AOI22X1TS U1395 ( .A0(n442), .A1(n794), .B0(n1266), .B1(n793), .Y(n797) );
NAND2X1TS U1396 ( .A(n437), .B(n795), .Y(n796) );
OAI22X1TS U1397 ( .A0(n806), .A1(n1329), .B0(n799), .B1(n428), .Y(n800) );
AOI21X1TS U1398 ( .A0(n447), .A1(n801), .B0(n800), .Y(n802) );
NAND2X1TS U1399 ( .A(n882), .B(n805), .Y(n898) );
OAI21X1TS U1400 ( .A0(n1246), .A1(n898), .B0(n806), .Y(n861) );
AND2X2TS U1401 ( .A(n882), .B(n441), .Y(n911) );
NAND2BX2TS U1402 ( .AN(n911), .B(n807), .Y(n1207) );
INVX2TS U1403 ( .A(n1207), .Y(n886) );
INVX2TS U1404 ( .A(n1195), .Y(n817) );
AOI22X2TS U1405 ( .A0(n809), .A1(exp_oper_result[4]), .B0(LZA_output[4]),
.B1(n808), .Y(n1218) );
OAI22X1TS U1406 ( .A0(n1392), .A1(n900), .B0(n1194), .B1(exp_oper_result[3]),
.Y(n810) );
BUFX3TS U1407 ( .A(n810), .Y(n1209) );
INVX2TS U1408 ( .A(n1209), .Y(n811) );
NAND2X1TS U1409 ( .A(n814), .B(n1207), .Y(n1199) );
NAND2X2TS U1410 ( .A(n815), .B(n1199), .Y(n876) );
AOI22X1TS U1411 ( .A0(n877), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .B1(n876), .Y(n816)
);
AOI22X1TS U1412 ( .A0(n430), .A1(Add_Subt_result[3]), .B0(DmP[20]), .B1(n823), .Y(n821) );
OAI2BB1X2TS U1413 ( .A0N(Add_Subt_result[22]), .A1N(n433), .B0(n821), .Y(
n1269) );
AOI22X1TS U1414 ( .A0(n431), .A1(Add_Subt_result[2]), .B0(DmP[21]), .B1(n823), .Y(n822) );
OAI2BB1X2TS U1415 ( .A0N(Add_Subt_result[23]), .A1N(n434), .B0(n822), .Y(
n1268) );
AOI22X1TS U1416 ( .A0(n1266), .A1(n1269), .B0(n437), .B1(n1268), .Y(n831) );
AOI22X1TS U1417 ( .A0(n431), .A1(Add_Subt_result[1]), .B0(DmP[22]), .B1(n823), .Y(n825) );
OAI2BB1X2TS U1418 ( .A0N(Add_Subt_result[24]), .A1N(n434), .B0(n825), .Y(
n1265) );
AOI2BB2X2TS U1419 ( .B0(n1273), .B1(n826), .A0N(n1265), .A1N(n1273), .Y(n854) );
INVX2TS U1420 ( .A(n1267), .Y(n827) );
AOI22X1TS U1421 ( .A0(n444), .A1(n854), .B0(n440), .B1(n856), .Y(n830) );
NAND2X1TS U1422 ( .A(n850), .B(n1185), .Y(n829) );
AOI22X1TS U1423 ( .A0(n439), .A1(n854), .B0(n1266), .B1(n856), .Y(n836) );
AOI22X1TS U1424 ( .A0(n439), .A1(n841), .B0(n445), .B1(n845), .Y(n839) );
AOI2BB2X2TS U1425 ( .B0(n1273), .B1(n837), .A0N(n1269), .A1N(n1273), .Y(n855) );
NAND2X1TS U1426 ( .A(n436), .B(n855), .Y(n838) );
AOI22X1TS U1427 ( .A0(n443), .A1(n841), .B0(n439), .B1(n845), .Y(n843) );
NAND2X1TS U1428 ( .A(n445), .B(n855), .Y(n842) );
AOI22X1TS U1429 ( .A0(n444), .A1(n845), .B0(n439), .B1(n855), .Y(n847) );
NAND2X1TS U1430 ( .A(n438), .B(n854), .Y(n846) );
AOI22X1TS U1431 ( .A0(n443), .A1(n856), .B0(n850), .B1(n849), .Y(n851) );
AOI22X1TS U1432 ( .A0(n443), .A1(n855), .B0(n1266), .B1(n854), .Y(n858) );
NAND2X1TS U1433 ( .A(n436), .B(n856), .Y(n857) );
INVX2TS U1434 ( .A(n861), .Y(n880) );
INVX2TS U1435 ( .A(n1218), .Y(n874) );
AOI211X1TS U1436 ( .A0(n1195), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n862), .C0(n874),
.Y(n864) );
AOI22X1TS U1437 ( .A0(n877), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .B1(n876), .Y(n863)
);
AOI211X1TS U1438 ( .A0(n1195), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(n865), .C0(n874),
.Y(n867) );
AOI22X1TS U1439 ( .A0(n877), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .B1(n876), .Y(n866)
);
OAI2BB1X1TS U1440 ( .A0N(Barrel_Shifter_module_Mux_Array_Data_array[49]),
.A1N(n1195), .B0(n1218), .Y(n868) );
AOI21X1TS U1441 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[28]), .A1(
n876), .B0(n868), .Y(n870) );
AOI211X1TS U1442 ( .A0(n1195), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n871), .C0(n874),
.Y(n873) );
AOI22X1TS U1443 ( .A0(n877), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .B1(n876), .Y(n872)
);
AOI211X1TS U1444 ( .A0(n1195), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n875), .C0(n874),
.Y(n879) );
AOI22X1TS U1445 ( .A0(n877), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .B1(n876), .Y(n878)
);
INVX2TS U1446 ( .A(n898), .Y(n1208) );
AOI222X1TS U1447 ( .A0(n1209), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .B0(n911), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .C1(n1208), .Y(n889)
);
INVX2TS U1448 ( .A(n881), .Y(n1241) );
INVX2TS U1449 ( .A(n1194), .Y(n897) );
AOI21X1TS U1450 ( .A0(n882), .A1(n421), .B0(n897), .Y(n884) );
AOI21X4TS U1451 ( .A0(n884), .A1(n883), .B0(n885), .Y(n1255) );
AOI21X1TS U1452 ( .A0(n1241), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .B0(n1255), .Y(n888)
);
OAI21X4TS U1453 ( .A0(n1246), .A1(n886), .B0(n885), .Y(n1253) );
AOI22X1TS U1454 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n1253), .B0(Barrel_Shifter_module_Mux_Array_Data_array[30]), .B1(n426),
.Y(n887) );
AOI222X1TS U1455 ( .A0(n1209), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .B0(n911), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .C1(n1208), .Y(n892)
);
AOI21X1TS U1456 ( .A0(n1241), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .B0(n1255), .Y(n891)
);
AOI22X1TS U1457 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[49]), .A1(
n1253), .B0(Barrel_Shifter_module_Mux_Array_Data_array[28]), .B1(n427),
.Y(n890) );
AOI222X1TS U1458 ( .A0(n1209), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(n911), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .C1(n1208), .Y(n895)
);
AOI21X1TS U1459 ( .A0(n1241), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(n1255), .Y(n894)
);
AOI22X1TS U1460 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n1253), .B0(Barrel_Shifter_module_Mux_Array_Data_array[32]), .B1(n426),
.Y(n893) );
NAND2X1TS U1461 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[51]), .B(
exp_oper_result[3]), .Y(n896) );
AOI22X1TS U1462 ( .A0(n897), .A1(n1237), .B0(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .B1(n1207), .Y(n903)
);
INVX2TS U1463 ( .A(n900), .Y(n1191) );
NAND2X1TS U1464 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[51]), .B(
n1392), .Y(n901) );
AOI22X1TS U1465 ( .A0(n1189), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .B0(n1191), .B1(n1239), .Y(n902) );
AOI21X1TS U1466 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[50]), .A1(
n1253), .B0(n1255), .Y(n904) );
AOI222X1TS U1467 ( .A0(n1209), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .B0(n911), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .C1(n1208), .Y(n907)
);
AOI22X1TS U1468 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[33]), .A1(
n427), .B0(Barrel_Shifter_module_Mux_Array_Data_array[44]), .B1(n1253),
.Y(n906) );
AOI21X1TS U1469 ( .A0(n1241), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(n1255), .Y(n905)
);
AOI22X1TS U1470 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[31]), .A1(
n427), .B0(Barrel_Shifter_module_Mux_Array_Data_array[46]), .B1(n1253),
.Y(n909) );
AOI21X1TS U1471 ( .A0(n1241), .A1(n447), .B0(n1255), .Y(n908) );
AOI222X1TS U1472 ( .A0(n1209), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .B0(n911), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .C0(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .C1(n1208), .Y(n914)
);
AOI22X1TS U1473 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[29]), .A1(
n427), .B0(Barrel_Shifter_module_Mux_Array_Data_array[48]), .B1(n1253),
.Y(n913) );
AOI21X1TS U1474 ( .A0(n1241), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .B0(n1255), .Y(n912)
);
CMPR32X2TS U1475 ( .A(n920), .B(n919), .C(n918), .CO(n922), .S(
Exp_Operation_Module_Data_S[6]) );
AND4X1TS U1476 ( .A(Exp_Operation_Module_Data_S[3]), .B(
Exp_Operation_Module_Data_S[2]), .C(Exp_Operation_Module_Data_S[1]),
.D(Exp_Operation_Module_Data_S[0]), .Y(n921) );
AND4X1TS U1477 ( .A(Exp_Operation_Module_Data_S[6]), .B(
Exp_Operation_Module_Data_S[5]), .C(Exp_Operation_Module_Data_S[4]),
.D(n921), .Y(n927) );
CMPR32X2TS U1478 ( .A(n924), .B(n923), .C(n922), .CO(n926), .S(
Exp_Operation_Module_Data_S[7]) );
OAI21X1TS U1479 ( .A0(n932), .A1(n1115), .B0(n931), .Y(n933) );
AOI21X1TS U1480 ( .A0(n935), .A1(n934), .B0(n933), .Y(n936) );
OAI21X2TS U1481 ( .A0(n938), .A1(n937), .B0(n936), .Y(n939) );
AOI21X4TS U1482 ( .A0(n941), .A1(n940), .B0(n939), .Y(n1106) );
NOR2BX1TS U1483 ( .AN(Sgf_normalized_result[15]), .B(n966), .Y(n942) );
XOR2X1TS U1484 ( .A(n968), .B(n942), .Y(n945) );
NOR2BX1TS U1485 ( .AN(Sgf_normalized_result[16]), .B(n966), .Y(n943) );
XOR2X1TS U1486 ( .A(n968), .B(n943), .Y(n947) );
NAND2X1TS U1487 ( .A(n450), .B(n1109), .Y(n950) );
NAND2X1TS U1488 ( .A(n945), .B(n944), .Y(n1112) );
INVX2TS U1489 ( .A(n1112), .Y(n1107) );
NAND2X1TS U1490 ( .A(n947), .B(n946), .Y(n1108) );
INVX2TS U1491 ( .A(n1108), .Y(n948) );
AOI21X1TS U1492 ( .A0(n1109), .A1(n1107), .B0(n948), .Y(n949) );
OAI21X4TS U1493 ( .A0(n1106), .A1(n950), .B0(n949), .Y(n1105) );
NOR2BX1TS U1494 ( .AN(Sgf_normalized_result[17]), .B(n984), .Y(n951) );
XOR2X1TS U1495 ( .A(n968), .B(n951), .Y(n953) );
NAND2X1TS U1496 ( .A(n953), .B(n952), .Y(n1102) );
INVX2TS U1497 ( .A(n1102), .Y(n954) );
AOI21X4TS U1498 ( .A0(n1105), .A1(n1103), .B0(n954), .Y(n1101) );
NOR2BX1TS U1499 ( .AN(Sgf_normalized_result[18]), .B(n984), .Y(n955) );
XOR2X1TS U1500 ( .A(n986), .B(n955), .Y(n958) );
NOR2X1TS U1501 ( .A(n958), .B(n957), .Y(n1097) );
NAND2X1TS U1502 ( .A(n958), .B(n957), .Y(n1098) );
OAI21X4TS U1503 ( .A0(n1101), .A1(n1097), .B0(n1098), .Y(n1096) );
NOR2BX1TS U1504 ( .AN(Sgf_normalized_result[19]), .B(n984), .Y(n959) );
XOR2X1TS U1505 ( .A(n986), .B(n959), .Y(n961) );
NAND2X1TS U1506 ( .A(n961), .B(n960), .Y(n1093) );
INVX2TS U1507 ( .A(n1093), .Y(n962) );
AOI21X4TS U1508 ( .A0(n1096), .A1(n1094), .B0(n962), .Y(n1092) );
NOR2BX1TS U1509 ( .AN(Sgf_normalized_result[20]), .B(n984), .Y(n963) );
XOR2X1TS U1510 ( .A(n986), .B(n963), .Y(n965) );
NOR2X1TS U1511 ( .A(n965), .B(n964), .Y(n1088) );
NAND2X1TS U1512 ( .A(n965), .B(n964), .Y(n1089) );
OAI21X4TS U1513 ( .A0(n1092), .A1(n1088), .B0(n1089), .Y(n1087) );
NOR2BX1TS U1514 ( .AN(Sgf_normalized_result[21]), .B(n966), .Y(n967) );
XOR2X1TS U1515 ( .A(n968), .B(n967), .Y(n970) );
NAND2X1TS U1516 ( .A(n970), .B(n969), .Y(n1084) );
INVX2TS U1517 ( .A(n1084), .Y(n971) );
AOI21X4TS U1518 ( .A0(n1087), .A1(n1085), .B0(n971), .Y(n1083) );
NOR2BX1TS U1519 ( .AN(Sgf_normalized_result[22]), .B(n984), .Y(n972) );
XOR2X1TS U1520 ( .A(n986), .B(n972), .Y(n974) );
NOR2X1TS U1521 ( .A(n974), .B(n973), .Y(n1079) );
NAND2X1TS U1522 ( .A(n974), .B(n973), .Y(n1080) );
OAI21X4TS U1523 ( .A0(n1083), .A1(n1079), .B0(n1080), .Y(n1078) );
NOR2BX1TS U1524 ( .AN(Sgf_normalized_result[23]), .B(n984), .Y(n975) );
XOR2X1TS U1525 ( .A(n986), .B(n975), .Y(n977) );
NAND2X1TS U1526 ( .A(n977), .B(n976), .Y(n1075) );
INVX2TS U1527 ( .A(n1075), .Y(n978) );
AOI21X4TS U1528 ( .A0(n1078), .A1(n1076), .B0(n978), .Y(n1074) );
NOR2BX1TS U1529 ( .AN(Sgf_normalized_result[24]), .B(n984), .Y(n979) );
XOR2X1TS U1530 ( .A(n986), .B(n979), .Y(n982) );
NOR2X1TS U1531 ( .A(n982), .B(n981), .Y(n1070) );
NAND2X1TS U1532 ( .A(n982), .B(n981), .Y(n1071) );
NOR2BX1TS U1533 ( .AN(Sgf_normalized_result[25]), .B(n984), .Y(n985) );
XOR2X1TS U1534 ( .A(n986), .B(n985), .Y(n1065) );
AOI21X2TS U1535 ( .A0(n1069), .A1(n1067), .B0(n1065), .Y(n988) );
XOR2X1TS U1536 ( .A(n988), .B(n987), .Y(Add_Subt_Sgf_module_S_to_D[26]) );
OAI21X1TS U1537 ( .A0(n990), .A1(FS_Module_state_reg[0]), .B0(n989), .Y(n996) );
INVX2TS U1538 ( .A(n996), .Y(n991) );
OR4X2TS U1539 ( .A(Exp_Operation_Module_Data_S[2]), .B(
Exp_Operation_Module_Data_S[1]), .C(Exp_Operation_Module_Data_S[0]),
.D(n991), .Y(n992) );
OR4X2TS U1540 ( .A(Exp_Operation_Module_Data_S[5]), .B(
Exp_Operation_Module_Data_S[4]), .C(Exp_Operation_Module_Data_S[3]),
.D(n992), .Y(n993) );
OR4X2TS U1541 ( .A(n994), .B(Exp_Operation_Module_Data_S[7]), .C(
Exp_Operation_Module_Data_S[6]), .D(n993), .Y(n995) );
OAI21X1TS U1542 ( .A0(n1390), .A1(n996), .B0(n995), .Y(n401) );
NOR2X1TS U1543 ( .A(n1371), .B(intDX[25]), .Y(n1057) );
AOI22X1TS U1544 ( .A0(intDX[25]), .A1(n1371), .B0(intDX[24]), .B1(n998), .Y(
n1002) );
OAI21X1TS U1545 ( .A0(intDX[26]), .A1(n1372), .B0(n999), .Y(n1058) );
NOR2X1TS U1546 ( .A(n1299), .B(intDX[30]), .Y(n1005) );
NOR2X1TS U1547 ( .A(n1370), .B(intDX[29]), .Y(n1003) );
AOI211X1TS U1548 ( .A0(intDY[28]), .A1(n1326), .B0(n1005), .C0(n1003), .Y(
n1056) );
NOR3X1TS U1549 ( .A(n1326), .B(n1003), .C(intDY[28]), .Y(n1004) );
AOI221X1TS U1550 ( .A0(intDX[30]), .A1(n1299), .B0(intDX[29]), .B1(n1370),
.C0(n1004), .Y(n1006) );
AOI2BB2X1TS U1551 ( .B0(n1007), .B1(n1056), .A0N(n1006), .A1N(n1005), .Y(
n1062) );
NOR2X1TS U1552 ( .A(n1368), .B(intDX[17]), .Y(n1043) );
OAI2BB1X1TS U1553 ( .A0N(n1327), .A1N(intDY[5]), .B0(intDX[4]), .Y(n1008) );
OAI22X1TS U1554 ( .A0(intDY[4]), .A1(n1008), .B0(n1327), .B1(intDY[5]), .Y(
n1019) );
OAI2BB1X1TS U1555 ( .A0N(n1341), .A1N(intDY[7]), .B0(intDX[6]), .Y(n1009) );
OAI22X1TS U1556 ( .A0(intDY[6]), .A1(n1009), .B0(n1341), .B1(intDY[7]), .Y(
n1018) );
AOI2BB2X1TS U1557 ( .B0(intDX[3]), .B1(n1377), .A0N(intDY[2]), .A1N(n1013),
.Y(n1014) );
OA22X1TS U1558 ( .A0(n1304), .A1(intDX[14]), .B0(n1369), .B1(intDX[15]), .Y(
n1034) );
OAI2BB2XLTS U1559 ( .B0(intDY[12]), .B1(n1021), .A0N(intDX[13]), .A1N(n1360),
.Y(n1033) );
AOI22X1TS U1560 ( .A0(intDX[11]), .A1(n1366), .B0(intDX[10]), .B1(n1023),
.Y(n1029) );
AOI21X1TS U1561 ( .A0(n1026), .A1(n1025), .B0(n1036), .Y(n1028) );
OAI2BB2XLTS U1562 ( .B0(intDY[14]), .B1(n1030), .A0N(intDX[15]), .A1N(n1369),
.Y(n1031) );
AOI211X1TS U1563 ( .A0(n1034), .A1(n1033), .B0(n1032), .C0(n1031), .Y(n1035)
);
OAI31X1TS U1564 ( .A0(n1038), .A1(n1037), .A2(n1036), .B0(n1035), .Y(n1041)
);
OA22X1TS U1565 ( .A0(n1305), .A1(intDX[22]), .B0(n1373), .B1(intDX[23]), .Y(
n1054) );
OAI21X1TS U1566 ( .A0(intDX[18]), .A1(n1367), .B0(n1045), .Y(n1049) );
AOI211X1TS U1567 ( .A0(intDY[16]), .A1(n1328), .B0(n1048), .C0(n1049), .Y(
n1040) );
OAI2BB2XLTS U1568 ( .B0(intDY[20]), .B1(n1042), .A0N(intDX[21]), .A1N(n1361),
.Y(n1053) );
AOI22X1TS U1569 ( .A0(intDX[17]), .A1(n1368), .B0(intDX[16]), .B1(n1044),
.Y(n1047) );
AOI32X1TS U1570 ( .A0(n1367), .A1(n1045), .A2(intDX[18]), .B0(intDX[19]),
.B1(n1303), .Y(n1046) );
OAI32X1TS U1571 ( .A0(n1049), .A1(n1048), .A2(n1047), .B0(n1046), .B1(n1048),
.Y(n1052) );
OAI2BB2XLTS U1572 ( .B0(intDY[22]), .B1(n1050), .A0N(intDX[23]), .A1N(n1373),
.Y(n1051) );
AOI211X1TS U1573 ( .A0(n1054), .A1(n1053), .B0(n1052), .C0(n1051), .Y(n1060)
);
NAND4BBX1TS U1574 ( .AN(n1058), .BN(n1057), .C(n1056), .D(n1055), .Y(n1059)
);
AOI32X4TS U1575 ( .A0(n1062), .A1(n1061), .A2(n1060), .B0(n1059), .B1(n1062),
.Y(n1063) );
AOI21X1TS U1576 ( .A0(n1256), .A1(n1168), .B0(intDX[31]), .Y(n1064) );
BUFX3TS U1577 ( .A(n1220), .Y(n1260) );
OAI2BB2XLTS U1578 ( .B0(n1064), .B1(n1421), .A0N(intDX[31]), .A1N(n1260),
.Y(n1426) );
BUFX3TS U1579 ( .A(n1275), .Y(n1229) );
XNOR2X1TS U1580 ( .A(add_subt), .B(Data_Y[31]), .Y(n1391) );
INVX2TS U1581 ( .A(n1065), .Y(n1066) );
NAND2X1TS U1582 ( .A(n1067), .B(n1066), .Y(n1068) );
XNOR2X1TS U1583 ( .A(n1069), .B(n1068), .Y(Add_Subt_Sgf_module_S_to_D[25])
);
INVX2TS U1584 ( .A(n1070), .Y(n1072) );
NAND2X1TS U1585 ( .A(n1072), .B(n1071), .Y(n1073) );
NAND2X1TS U1586 ( .A(n1076), .B(n1075), .Y(n1077) );
XNOR2X1TS U1587 ( .A(n1078), .B(n1077), .Y(Add_Subt_Sgf_module_S_to_D[23])
);
INVX2TS U1588 ( .A(n1079), .Y(n1081) );
NAND2X1TS U1589 ( .A(n1081), .B(n1080), .Y(n1082) );
NAND2X1TS U1590 ( .A(n1085), .B(n1084), .Y(n1086) );
XNOR2X1TS U1591 ( .A(n1087), .B(n1086), .Y(Add_Subt_Sgf_module_S_to_D[21])
);
INVX2TS U1592 ( .A(n1088), .Y(n1090) );
NAND2X1TS U1593 ( .A(n1090), .B(n1089), .Y(n1091) );
NAND2X1TS U1594 ( .A(n1094), .B(n1093), .Y(n1095) );
XNOR2X1TS U1595 ( .A(n1096), .B(n1095), .Y(Add_Subt_Sgf_module_S_to_D[19])
);
INVX2TS U1596 ( .A(n1097), .Y(n1099) );
NAND2X1TS U1597 ( .A(n1099), .B(n1098), .Y(n1100) );
NAND2X1TS U1598 ( .A(n1103), .B(n1102), .Y(n1104) );
XNOR2X1TS U1599 ( .A(n1105), .B(n1104), .Y(Add_Subt_Sgf_module_S_to_D[17])
);
INVX2TS U1600 ( .A(n1106), .Y(n1114) );
AOI21X1TS U1601 ( .A0(n1114), .A1(n450), .B0(n1107), .Y(n1111) );
NAND2X1TS U1602 ( .A(n1109), .B(n1108), .Y(n1110) );
NAND2X1TS U1603 ( .A(n450), .B(n1112), .Y(n1113) );
XNOR2X1TS U1604 ( .A(n1114), .B(n1113), .Y(Add_Subt_Sgf_module_S_to_D[15])
);
NAND2X1TS U1605 ( .A(n1116), .B(n1115), .Y(n1117) );
XNOR2X1TS U1606 ( .A(n1118), .B(n1117), .Y(Add_Subt_Sgf_module_S_to_D[13])
);
NAND2X1TS U1607 ( .A(n1120), .B(n1119), .Y(n1121) );
XNOR2X1TS U1608 ( .A(n1122), .B(n1121), .Y(Add_Subt_Sgf_module_S_to_D[9]) );
INVX2TS U1609 ( .A(n1123), .Y(n1125) );
NAND2X1TS U1610 ( .A(n1125), .B(n1124), .Y(n1126) );
XNOR2X1TS U1611 ( .A(n1127), .B(n1126), .Y(Add_Subt_Sgf_module_S_to_D[8]) );
INVX2TS U1612 ( .A(n1128), .Y(n1130) );
NAND2X1TS U1613 ( .A(n1130), .B(n1129), .Y(n1131) );
INVX2TS U1614 ( .A(n1133), .Y(n1156) );
AOI21X1TS U1615 ( .A0(n1156), .A1(n1135), .B0(n1134), .Y(n1145) );
INVX2TS U1616 ( .A(n1136), .Y(n1138) );
NAND2X1TS U1617 ( .A(n1138), .B(n1137), .Y(n1139) );
XNOR2X1TS U1618 ( .A(n1140), .B(n1139), .Y(Add_Subt_Sgf_module_S_to_D[6]) );
INVX2TS U1619 ( .A(n1141), .Y(n1143) );
NAND2X1TS U1620 ( .A(n1143), .B(n1142), .Y(n1144) );
INVX2TS U1621 ( .A(n1146), .Y(n1154) );
INVX2TS U1622 ( .A(n1153), .Y(n1147) );
AOI21X1TS U1623 ( .A0(n1156), .A1(n1154), .B0(n1147), .Y(n1152) );
INVX2TS U1624 ( .A(n1148), .Y(n1150) );
NAND2X1TS U1625 ( .A(n1150), .B(n1149), .Y(n1151) );
NAND2X1TS U1626 ( .A(n1154), .B(n1153), .Y(n1155) );
XNOR2X1TS U1627 ( .A(n1156), .B(n1155), .Y(Add_Subt_Sgf_module_S_to_D[3]) );
INVX2TS U1628 ( .A(n1157), .Y(n1163) );
INVX2TS U1629 ( .A(n1158), .Y(n1160) );
NAND2X1TS U1630 ( .A(n1160), .B(n1159), .Y(n1161) );
XNOR2X1TS U1631 ( .A(n1162), .B(n1161), .Y(Add_Subt_Sgf_module_S_to_D[2]) );
XNOR2X1TS U1632 ( .A(n1166), .B(n1165), .Y(Add_Subt_Sgf_module_S_to_D[0]) );
OAI21XLTS U1633 ( .A0(n1168), .A1(n1167), .B0(n1423), .Y(n1172) );
NAND2X1TS U1634 ( .A(n1169), .B(n1310), .Y(n1170) );
MXI2X1TS U1635 ( .A(n1282), .B(add_overflow_flag), .S0(n1174), .Y(n405) );
MXI2X1TS U1636 ( .A(n1332), .B(n1299), .S0(n1258), .Y(
Oper_Start_in_module_intM[30]) );
MXI2X1TS U1637 ( .A(n1317), .B(n1370), .S0(n1256), .Y(
Oper_Start_in_module_intM[29]) );
MXI2X1TS U1638 ( .A(n1326), .B(n1363), .S0(n1261), .Y(
Oper_Start_in_module_intM[28]) );
MXI2X1TS U1639 ( .A(n1291), .B(n1365), .S0(n1198), .Y(
Oper_Start_in_module_intM[27]) );
MXI2X1TS U1640 ( .A(n1290), .B(n1372), .S0(n1259), .Y(
Oper_Start_in_module_intM[26]) );
MXI2X1TS U1641 ( .A(n1318), .B(n1371), .S0(n1198), .Y(
Oper_Start_in_module_intM[25]) );
MXI2X1TS U1642 ( .A(n1289), .B(n1364), .S0(n1256), .Y(
Oper_Start_in_module_intM[24]) );
MXI2X1TS U1643 ( .A(n1319), .B(n1373), .S0(n1259), .Y(
Oper_Start_in_module_intM[23]) );
MXI2X1TS U1644 ( .A(n1299), .B(n1332), .S0(n1196), .Y(
Oper_Start_in_module_intm[30]) );
MXI2X1TS U1645 ( .A(n1370), .B(n1317), .S0(n1197), .Y(
Oper_Start_in_module_intm[29]) );
MXI2X1TS U1646 ( .A(n1363), .B(n1326), .S0(n1196), .Y(
Oper_Start_in_module_intm[28]) );
MXI2X1TS U1647 ( .A(n1365), .B(n1291), .S0(n1197), .Y(
Oper_Start_in_module_intm[27]) );
MXI2X1TS U1648 ( .A(n1372), .B(n1290), .S0(n1197), .Y(
Oper_Start_in_module_intm[26]) );
MXI2X1TS U1649 ( .A(n1371), .B(n1318), .S0(n1196), .Y(
Oper_Start_in_module_intm[25]) );
MXI2X1TS U1650 ( .A(n1364), .B(n1289), .S0(n1196), .Y(
Oper_Start_in_module_intm[24]) );
OAI31X1TS U1651 ( .A0(n1342), .A1(Add_Subt_result[21]), .A2(
Add_Subt_result[20]), .B0(n1175), .Y(n1178) );
OAI211XLTS U1652 ( .A0(Add_Subt_result[15]), .A1(Add_Subt_result[14]), .B0(
n1297), .C0(n1354), .Y(n1177) );
MXI2X1TS U1653 ( .A(n1373), .B(n1319), .S0(n1197), .Y(
Oper_Start_in_module_intm[23]) );
AOI22X1TS U1654 ( .A0(n443), .A1(n1265), .B0(n440), .B1(n1267), .Y(n1187) );
OAI22X1TS U1655 ( .A0(n1187), .A1(n1270), .B0(n1186), .B1(n1271), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
NAND2X1TS U1656 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[50]), .B(
exp_oper_result[3]), .Y(n1188) );
NAND2X1TS U1657 ( .A(n1189), .B(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(n1193) );
NAND2X1TS U1658 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[50]), .B(
n1392), .Y(n1190) );
AOI22X1TS U1659 ( .A0(n1191), .A1(n1230), .B0(n1207), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .Y(n1192) );
OAI211X1TS U1660 ( .A0(n422), .A1(n1194), .B0(n1193), .C0(n1192), .Y(n1251)
);
MXI2X1TS U1661 ( .A(n1288), .B(n1305), .S0(n1196), .Y(
Oper_Start_in_module_intM[22]) );
MXI2X1TS U1662 ( .A(n1316), .B(n1361), .S0(n1197), .Y(
Oper_Start_in_module_intM[21]) );
MXI2X1TS U1663 ( .A(n1287), .B(n1362), .S0(n1197), .Y(
Oper_Start_in_module_intM[20]) );
MXI2X1TS U1664 ( .A(n1313), .B(n1303), .S0(n1258), .Y(
Oper_Start_in_module_intM[19]) );
MXI2X1TS U1665 ( .A(n1286), .B(n1367), .S0(n1196), .Y(
Oper_Start_in_module_intM[18]) );
MXI2X1TS U1666 ( .A(n1312), .B(n1368), .S0(n1261), .Y(
Oper_Start_in_module_intM[17]) );
MXI2X1TS U1667 ( .A(n1328), .B(n1358), .S0(n1259), .Y(
Oper_Start_in_module_intM[16]) );
MXI2X1TS U1668 ( .A(n1315), .B(n1369), .S0(n1198), .Y(
Oper_Start_in_module_intM[15]) );
MXI2X1TS U1669 ( .A(n1285), .B(n1304), .S0(n1261), .Y(
Oper_Start_in_module_intM[14]) );
MXI2X1TS U1670 ( .A(n1314), .B(n1360), .S0(n1256), .Y(
Oper_Start_in_module_intM[13]) );
MXI2X1TS U1671 ( .A(n1359), .B(n1311), .S0(n1198), .Y(
Oper_Start_in_module_intM[12]) );
MXI2X1TS U1672 ( .A(n1309), .B(n1366), .S0(n1259), .Y(
Oper_Start_in_module_intM[11]) );
NAND2X1TS U1673 ( .A(n1206), .B(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(n1205) );
INVX2TS U1674 ( .A(n1199), .Y(n1210) );
NAND2X1TS U1675 ( .A(n530), .B(n1230), .Y(n1202) );
NAND2X1TS U1676 ( .A(n1211), .B(n435), .Y(n1201) );
NAND2X1TS U1677 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[42]), .B(
FSM_selector_B[1]), .Y(n1200) );
AOI22X1TS U1678 ( .A0(n1215), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .B0(n1231), .B1(n1252), .Y(n1203) );
NAND2X1TS U1679 ( .A(n1206), .B(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(n1219) );
NAND2X1TS U1680 ( .A(n1237), .B(n1211), .Y(n1214) );
NAND2X1TS U1681 ( .A(n530), .B(n1239), .Y(n1213) );
NAND2X1TS U1682 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[43]), .B(
FSM_selector_B[1]), .Y(n1212) );
AOI22X1TS U1683 ( .A0(n1215), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .B0(n1242), .B1(n1252), .Y(n1216) );
AOI21X1TS U1684 ( .A0(n1222), .A1(n1335), .B0(n1221), .Y(n1223) );
BUFX3TS U1685 ( .A(n1275), .Y(n1277) );
NAND2X1TS U1686 ( .A(n1277), .B(n1283), .Y(
final_result_ieee_Module_Exp_S_mux[4]) );
NAND2X1TS U1687 ( .A(n1229), .B(n420), .Y(
final_result_ieee_Module_Exp_S_mux[3]) );
NAND2X1TS U1688 ( .A(n1277), .B(n1338), .Y(
final_result_ieee_Module_Exp_S_mux[0]) );
AOI22X1TS U1689 ( .A0(n1240), .A1(n1230), .B0(n1238), .B1(n435), .Y(n1236)
);
AOI22X1TS U1690 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[43]), .A1(
n1241), .B0(Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(n425),
.Y(n1235) );
INVX2TS U1691 ( .A(n1231), .Y(n1232) );
OA22X1TS U1692 ( .A0(n1233), .A1(n1243), .B0(n1246), .B1(n1232), .Y(n1234)
);
AOI22X1TS U1693 ( .A0(n1240), .A1(n1239), .B0(n1238), .B1(n1237), .Y(n1250)
);
AOI22X1TS U1694 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[43]), .A1(
n425), .B0(Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(n1241),
.Y(n1249) );
INVX2TS U1695 ( .A(n1242), .Y(n1245) );
OA22X1TS U1696 ( .A0(n1246), .A1(n1245), .B0(n1244), .B1(n428), .Y(n1248) );
AOI22X1TS U1697 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[51]), .A1(
n1253), .B0(n1252), .B1(n1251), .Y(n1254) );
AOI21X1TS U1698 ( .A0(n1306), .A1(n1390), .B0(overflow_flag), .Y(
final_result_ieee_Module_Sign_S_mux) );
AOI22X1TS U1699 ( .A0(n1260), .A1(n1378), .B0(n1298), .B1(n1258), .Y(
Oper_Start_in_module_intm[0]) );
BUFX3TS U1700 ( .A(n1063), .Y(n1257) );
INVX2TS U1701 ( .A(n1063), .Y(n1259) );
AOI22X1TS U1702 ( .A0(n1257), .A1(n448), .B0(n1323), .B1(n1258), .Y(
Oper_Start_in_module_intm[1]) );
AOI22X1TS U1703 ( .A0(n1257), .A1(n1350), .B0(n1293), .B1(n1258), .Y(
Oper_Start_in_module_intm[2]) );
AOI22X1TS U1704 ( .A0(n1257), .A1(n1377), .B0(n1321), .B1(n1261), .Y(
Oper_Start_in_module_intm[3]) );
AOI22X1TS U1705 ( .A0(n1257), .A1(n1348), .B0(n1295), .B1(n1198), .Y(
Oper_Start_in_module_intm[4]) );
AOI22X1TS U1706 ( .A0(n1257), .A1(n1343), .B0(n1327), .B1(n1256), .Y(
Oper_Start_in_module_intm[5]) );
AOI22X1TS U1707 ( .A0(n1257), .A1(n1374), .B0(n1300), .B1(n1259), .Y(
Oper_Start_in_module_intm[6]) );
AOI22X1TS U1708 ( .A0(n1257), .A1(n1351), .B0(n1341), .B1(n1258), .Y(
Oper_Start_in_module_intm[7]) );
AOI22X1TS U1709 ( .A0(n1257), .A1(n1376), .B0(n1322), .B1(n1261), .Y(
Oper_Start_in_module_intm[8]) );
BUFX3TS U1710 ( .A(n1063), .Y(n1262) );
AOI22X1TS U1711 ( .A0(n1262), .A1(n1352), .B0(n1292), .B1(n1198), .Y(
Oper_Start_in_module_intm[9]) );
AOI22X1TS U1712 ( .A0(n1262), .A1(n1375), .B0(n1294), .B1(n1256), .Y(
Oper_Start_in_module_intm[10]) );
AOI22X1TS U1713 ( .A0(n1262), .A1(n1366), .B0(n1309), .B1(n1259), .Y(
Oper_Start_in_module_intm[11]) );
INVX2TS U1714 ( .A(n1063), .Y(n1261) );
AOI22X1TS U1715 ( .A0(n1262), .A1(n1311), .B0(n1359), .B1(n1198), .Y(
Oper_Start_in_module_intm[12]) );
AOI22X1TS U1716 ( .A0(n1262), .A1(n1360), .B0(n1314), .B1(n1256), .Y(
Oper_Start_in_module_intm[13]) );
AOI22X1TS U1717 ( .A0(n1262), .A1(n1304), .B0(n1285), .B1(n1259), .Y(
Oper_Start_in_module_intm[14]) );
AOI22X1TS U1718 ( .A0(n1262), .A1(n1369), .B0(n1315), .B1(n1258), .Y(
Oper_Start_in_module_intm[15]) );
AOI22X1TS U1719 ( .A0(n1262), .A1(n1358), .B0(n1328), .B1(n1261), .Y(
Oper_Start_in_module_intm[16]) );
AOI22X1TS U1720 ( .A0(n1262), .A1(n1368), .B0(n1312), .B1(n1258), .Y(
Oper_Start_in_module_intm[17]) );
AOI22X1TS U1721 ( .A0(n1260), .A1(n1367), .B0(n1286), .B1(n1261), .Y(
Oper_Start_in_module_intm[18]) );
AOI22X1TS U1722 ( .A0(n1260), .A1(n1303), .B0(n1313), .B1(n1261), .Y(
Oper_Start_in_module_intm[19]) );
AOI22X1TS U1723 ( .A0(n1260), .A1(n1362), .B0(n1287), .B1(n1198), .Y(
Oper_Start_in_module_intm[20]) );
AOI22X1TS U1724 ( .A0(n1260), .A1(n1361), .B0(n1316), .B1(n1256), .Y(
Oper_Start_in_module_intm[21]) );
AOI22X1TS U1725 ( .A0(n1262), .A1(n1305), .B0(n1288), .B1(n1259), .Y(
Oper_Start_in_module_intm[22]) );
OAI22X1TS U1726 ( .A0(n1271), .A1(n1264), .B0(n1263), .B1(n1270), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
AOI22X1TS U1727 ( .A0(n437), .A1(n1267), .B0(n1266), .B1(n1265), .Y(n1274)
);
AOI22X1TS U1728 ( .A0(n442), .A1(n1269), .B0(n440), .B1(n1268), .Y(n1272) );
AOI32X1TS U1729 ( .A0(n1274), .A1(n1273), .A2(n1272), .B0(n1271), .B1(n1270),
.Y(Barrel_Shifter_module_Mux_Array_Data_array[22]) );
BUFX3TS U1730 ( .A(n1275), .Y(n1276) );
NAND2X1TS U1732 ( .A(n1279), .B(n1278), .Y(FSM_barrel_shifter_load) );
initial $sdf_annotate("FPU_Add_Subtract_Function_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21O_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A21O_PP_SYMBOL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21O_PP_SYMBOL_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:58:48 11/16/2011
// Design Name: toprobertsons
// Module Name: /home/ECONOLITE/lmagasweran/Documents/personal/School/EE412/Robertsons_Multiplier/robertsonstest.v
// Project Name: Robertsons_Multiplier
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: toprobertsons
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module robertsonstest;
// Inputs
reg clk;
reg reset;
reg [7:0] multiplier;
reg [7:0] multiplicand;
// Outputs
wire [15:0] product;
wire done;
// keep track of execution status
reg [31:0] cycle;
// expected results
reg [15:0] expected_product;
// Instantiate the Unit Under Test (UUT)
toprobertsons uut (
.clk(clk),
.reset(reset),
.multiplier(multiplier),
.multiplicand(multiplicand),
.product(product),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
multiplier = 0;
multiplicand = 0;
expected_product = 0;
// Add stimulus here
reset <= 1; # 12; reset <= 0;
cycle <= 1;
// 1.1 Positive Multiplicand and Positive Multiplier
multiplier = 5;
multiplicand = 6;
expected_product = 30;
// 1.2 Positive Multiplicand and Positive Multiplier
//multiplier = 7;
//multiplicand = 5;
//expected_product = 35;
// 2.1 Negative Multiplicand and Positive Multiplier
//multiplier = 5;
//multiplicand = -6;
//expected_product = -30;
// 2.2 Negative Multiplicand and Positive Multiplier
//multiplier = 7;
//multiplicand = -5;
//expected_product = -35;
// 3.1 Positive Multiplicand and Negative Multiplier
//multiplier = -5;
//multiplicand = 6;
//expected_product = -30;
// 3.2 Positive Multiplicand and Negative Multiplier
//multiplier = -7;
//multiplicand = 8;
//expected_product = -56;
// 4.1 Negative Multiplicand and Negative Multiplier
//multiplier = -5;
//multiplicand = -6;
//expected_product = 30;
// 4.2 Negative Multiplicand and Negative Multiplier
//multiplier = -9;
//multiplicand = -4;
//expected_product = 36;
end
// generate clock to sequence tests
always
begin
clk <= 1; # 5; clk <= 0; # 5;
cycle <= cycle + 1;
end
// check results
// If successful, it should write the value 7 to address 84
always@(negedge clk)
begin
if (done) begin
if (product == expected_product) begin
$display("Simulation succeeded");
$stop;
end else begin
$display("Simulation failed");
$stop;
end
end
end
endmodule
|
//
// Written by Synplify
// Product Version "I-2013.09-1 "
// Program "Synplify Premier", Mapper "maprc, Build 1788R"
// Tue Oct 1 15:20:16 2013
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "\/nfs/tools/synopsys/fpga/I-2013.09-1/lib/vhd/std.vhd "
// file 1 "\/nfs/tools/synopsys/fpga/I-2013.09-1/lib/vhd/snps_haps_pkg.vhd "
// file 2 "\/nfs/tools/synopsys/fpga/I-2013.09-1/lib/vhd/std1164.vhd "
// file 3 "\/nfs/tools/synopsys/fpga/I-2013.09-1/lib/vhd/numeric.vhd "
// file 4 "\/nfs/tools/synopsys/fpga/I-2013.09-1/lib/vhd/umr_capim.vhd "
// file 5 "\/nfs/tools/synopsys/fpga/I-2013.09-1/lib/vhd/arith.vhd "
// file 6 "\/nfs/tools/synopsys/fpga/I-2013.09-1/lib/vhd/unsigned.vhd "
// file 7 "\/nfs/projects/faultsim/sim2014/davester/Testcases/b14/b14.vhd "
`timescale 100 ps/100 ps
module b14 (
clock,
reset,
addr,
datai,
datao,
rd,
wr
)
;
input clock ;
input reset ;
output [19:0] addr ;
input [31:0] datai ;
output [31:0] datao ;
output rd ;
output wr ;
wire clock ;
wire reset ;
wire rd ;
wire wr ;
wire [0:0] state;
wire [31:0] ir;
wire [28:0] reg3;
wire [31:0] ir_3;
wire [31:0] reg2;
wire [31:0] m_2;
wire [31:0] reg1;
wire [31:0] r_4;
wire [31:0] reg0;
wire [30:0] un11_r_cry;
wire [1:0] d;
wire [30:30] r_6;
wire [30:0] un26_r_cry;
wire [31:0] reg2_16;
wire [19:0] un1_inf_abs0_10;
wire [19:0] un1_inf_abs0_11;
wire [18:0] reg0_28;
wire [18:0] reg1_16;
wire [28:0] reg3_17;
wire [28:0] b18_cry;
wire [30:30] r_4_3_lut6_2_O5;
wire [9:0] un14_r_0_data_tmp;
wire [16:1] t_6;
wire [0:0] d_cnst;
wire [0:0] dce;
wire [31:0] inf_abs0_2;
wire [31:1] reg3_1_1;
wire [31:0] t_1;
wire [18:17] reg0_28_7_a1;
wire [24:24] reg0_28_7_d;
wire [24:21] reg3_17_a0;
wire [29:29] reg2_16_11_a1;
wire [29:17] reg2_16_11_a2;
wire [29:17] reg2_16_11_a3;
wire [1:0] r_4_2_a0;
wire [13:13] reg3_17_4_a2;
wire [10:10] r_4_1_RNIDBOH1;
wire [25:21] reg2_16_11_a4;
wire [9:9] r_4_1_RNIS3K91;
wire [7:7] r_4_1_RNIFO731;
wire [8:8] r_4_1_RNIIQ731;
wire [5:5] r_4_1_RNI9K731;
wire [6:6] r_4_1_RNICM731;
wire [3:3] r_4_2_a1_lut6_2_RNI5V8R3;
wire [3:3] r_4_2_a1_lut6_2_RNI2T8R3;
wire [24:21] \d_cnst_sn.reg3_17_0_tz ;
wire [4:0] \d_cnst_sn.r_4_0_0 ;
wire [20:20] reg2_16_2_d;
wire [3:3] r_4_2_a1_lut6_2_O6;
wire [3:3] r_4_2_a1_lut6_2_O5;
wire [28:28] \d_cnst_sn.reg2_16_0_1_tz ;
wire [28:28] \d_cnst_sn.reg2_16_11_1_tz ;
wire [7:7] \d_cnst_sn.reg0_28_a0_1 ;
wire [5:5] \d_cnst_sn.reg1_16_a2_0 ;
wire [4:4] \d_cnst_sn.reg0_28_a1_1 ;
wire [3:3] \d_cnst_sn.reg1_16_a0_1 ;
wire [9:9] \d_cnst_sn.reg0_28_7_a0_0 ;
wire [24:24] \d_cnst_sn.reg3_17_a1_2 ;
wire [0:0] state_i;
wire [31:31] r_4_i;
wire [31:0] m_2_i;
wire [28:20] \d_cnst_sn.reg3_17_4_a2_0 ;
wire [21:21] \d_cnst_sn.reg3_17_a2_2_0 ;
wire [8:2] \d_cnst_sn.reg0_1 ;
wire [8:3] \d_cnst_sn.reg1_1 ;
wire [28:12] \d_cnst_sn.reg3_17_6_0 ;
wire [19:12] \d_cnst_sn.reg3_17_6_1 ;
wire [20:19] \d_cnst_sn.reg0_28_0 ;
wire [25:20] \d_cnst_sn.reg2_16_0 ;
wire [29:20] \d_cnst_sn.reg2_16_1 ;
wire [17:17] \d_cnst_sn.reg0_0 ;
wire [18:18] \d_cnst_sn.reg1_0 ;
wire [28:26] \d_cnst_sn.reg2_16_0_1_0 ;
wire [31:31] r_4_3_ci;
wire [31:31] ir_fast;
wire [31:31] ir_3_fast;
wire [31:31] inf_abs0_2_0;
wire [31:31] inf_abs0_2_1;
wire [1:1] \d_cnst_sn.reg2_16_11muxnet_0 ;
wire [1:1] \d_cnst_sn.reg2_16_11muxnet_1 ;
wire b ;
wire VCC ;
wire GND ;
wire addr_4_sqmuxa_1 ;
wire un14_r_0_I_83 ;
wire b18 ;
wire un11_reg0_s_1 ;
wire un11_reg0_s_2 ;
wire un11_reg0_s_3 ;
wire un11_reg0_s_4 ;
wire un11_reg0_s_5 ;
wire un11_reg0_s_6 ;
wire un11_reg0_s_7 ;
wire un11_reg0_s_8 ;
wire un11_reg0_s_9 ;
wire un11_reg0_s_10 ;
wire un11_reg0_s_11 ;
wire un11_reg0_s_12 ;
wire un11_reg0_s_13 ;
wire un11_reg0_s_14 ;
wire un11_reg0_s_15 ;
wire un11_reg0_s_16 ;
wire un11_reg0_s_17 ;
wire un11_reg0_s_18 ;
wire un11_reg0_s_19 ;
wire un11_reg0_s_20 ;
wire un11_reg0_s_21 ;
wire un11_reg0_s_22 ;
wire un11_reg0_s_23 ;
wire un11_reg0_s_24 ;
wire un11_reg0_s_25 ;
wire un11_reg0_s_26 ;
wire un11_reg0_s_27 ;
wire un11_reg0_s_28 ;
wire un11_reg0_s_29 ;
wire rd_18 ;
wire un11_r_df0 ;
wire un11_r_lt0 ;
wire un11_r_df2 ;
wire un11_r_lt2 ;
wire un11_r_df4 ;
wire un11_r_lt4 ;
wire un11_r_df6 ;
wire un11_r_lt6 ;
wire un11_r_df8 ;
wire un11_r_lt8 ;
wire un11_r_df10 ;
wire un11_r_lt10 ;
wire un11_r_df12 ;
wire un11_r_lt12 ;
wire un11_r_df14 ;
wire un11_r_lt14 ;
wire un11_r_df16 ;
wire un11_r_lt16 ;
wire un11_r_df18 ;
wire un11_r_lt18 ;
wire un11_r_df20 ;
wire un11_r_lt20 ;
wire un11_r_df22 ;
wire un11_r_lt22 ;
wire un11_r_df24 ;
wire un11_r_lt24 ;
wire un11_r_df26 ;
wire un11_r_lt26 ;
wire un11_r_df28 ;
wire un11_r_lt28 ;
wire un11_r_df30 ;
wire un11_r_lt30 ;
wire b18_df0 ;
wire b18_lt0 ;
wire b18_df2 ;
wire b18_lt2 ;
wire b18_df4 ;
wire b18_lt4 ;
wire b18_df6 ;
wire b18_lt6 ;
wire b18_df8 ;
wire b18_lt8 ;
wire b18_df10 ;
wire b18_lt10 ;
wire b18_df12 ;
wire b18_lt12 ;
wire b18_df14 ;
wire b18_lt14 ;
wire b18_df16 ;
wire b18_lt16 ;
wire b18_df18 ;
wire b18_lt18 ;
wire b18_df20 ;
wire b18_lt20 ;
wire b18_df22 ;
wire b18_lt22 ;
wire b18_df24 ;
wire b18_lt24 ;
wire b18_df26 ;
wire b18_lt26 ;
wire b18_df28 ;
wire b18_lt28 ;
wire b18_df30 ;
wire b18_lt30 ;
wire un26_r_df0 ;
wire un26_r_lt0 ;
wire un26_r_df2 ;
wire un26_r_lt2 ;
wire un26_r_df4 ;
wire un26_r_lt4 ;
wire un26_r_df6 ;
wire un26_r_lt6 ;
wire un26_r_df8 ;
wire un26_r_lt8 ;
wire un26_r_df10 ;
wire un26_r_lt10 ;
wire un26_r_df12 ;
wire un26_r_lt12 ;
wire un26_r_df14 ;
wire un26_r_lt14 ;
wire un26_r_df16 ;
wire un26_r_lt16 ;
wire un26_r_df18 ;
wire un26_r_lt18 ;
wire un26_r_df20 ;
wire un26_r_lt20 ;
wire un26_r_df22 ;
wire un26_r_lt22 ;
wire un26_r_df24 ;
wire un26_r_lt24 ;
wire un26_r_df26 ;
wire un26_r_lt26 ;
wire un26_r_df28 ;
wire un26_r_lt28 ;
wire un26_r_df30 ;
wire un26_r_lt30 ;
wire r_4_3_30_680_i_m2 ;
wire r_4_3_29_706_i_m2 ;
wire r_4_3_28_732_i_m2 ;
wire r_4_3_27_758_i_m2 ;
wire r_4_3_25_810_i_m2 ;
wire r_4_3_24_836_i_m2 ;
wire r_4_3_23_1078_i_m2 ;
wire r_4_3_22_1104_i_m2 ;
wire r_4_3_20_1156_i_m2 ;
wire r_4_3_19_1182_i_m2 ;
wire r_4_3_18_1208_i_m2 ;
wire r_4_3_17_1234_i_m2 ;
wire r_4_3_16_1260_i_m2 ;
wire r_4_3_15_1286_i_m2 ;
wire r_4_3_14_1312_i_m2 ;
wire r_4_3_13_1338_i_m2 ;
wire r_4_3_12_1364_i_m2 ;
wire r_4_3_11_1390_i_m2 ;
wire r_4_3_10_1416_i_m2 ;
wire r_4_3_9_1442_i_m2 ;
wire r_4_3_8_1467 ;
wire r_4_3_6_1508_i_m2 ;
wire r_4_3_5_1534_i_m2 ;
wire r_4_3_4_1560_i_m2 ;
wire r_4_3_3_1586_i_m2 ;
wire r_4_3_2_1612_i_m2 ;
wire r_4_3_1_1638_i_m2 ;
wire r_4_3_0_1664_i_m2 ;
wire r_4_3_1690_i_m2 ;
wire reg1_16_9 ;
wire reg1_16_8_1837 ;
wire reg1_16_7_1870 ;
wire reg0_28_10_2261_a6_3_2_lut6_2_RNIOK9O5 ;
wire reg0_28_8_2327 ;
wire reg0_28_7_2360 ;
wire reg0_28_6_2393 ;
wire reg0_28_5_2426 ;
wire reg0_28_4_2459 ;
wire reg0_28_3_2492 ;
wire un14_r_0_N_2 ;
wire un14_r_0_N_7 ;
wire un14_r_0_N_14 ;
wire un14_r_0_N_21 ;
wire un14_r_0_N_28 ;
wire un14_r_0_N_35 ;
wire un14_r_0_N_42 ;
wire un14_r_0_N_49 ;
wire un14_r_0_N_56 ;
wire un14_r_0_N_63 ;
wire un14_r_0_N_70 ;
wire N_28 ;
wire N_3550 ;
wire N_3856 ;
wire N_2724 ;
wire N_3673 ;
wire N_939 ;
wire N_3_0 ;
wire N_971 ;
wire N_13 ;
wire un1_cf ;
wire N_1688 ;
wire reg3_1_sqmuxa ;
wire un1_df_16 ;
wire N_1750 ;
wire reg3_14_sqmuxa ;
wire N_1812 ;
wire N_1810 ;
wire N_1841 ;
wire N_1661 ;
wire N_1816 ;
wire N_1681 ;
wire N_1743 ;
wire N_938 ;
wire N_970 ;
wire N_1033 ;
wire N_513_i ;
wire N_3873_2 ;
wire N_512_i ;
wire un1_df_1 ;
wire un36_df ;
wire d_cnst_sm0 ;
wire N_3913 ;
wire N_1342 ;
wire N_1374 ;
wire N_514_i ;
wire N_1566 ;
wire N_1584 ;
wire N_1890 ;
wire un86_df ;
wire N_1664 ;
wire N_1819 ;
wire N_1682 ;
wire N_1837 ;
wire N_527_i ;
wire N_1042 ;
wire N_3916 ;
wire N_1270 ;
wire N_1132 ;
wire N_1892 ;
wire N_2641 ;
wire un87_df ;
wire N_7_i ;
wire N_1043 ;
wire b_2_sqmuxa ;
wire N_3912 ;
wire N_895 ;
wire N_526_i ;
wire un1_df_17_2 ;
wire N_1493 ;
wire N_1337 ;
wire N_1343 ;
wire N_1369 ;
wire N_1375 ;
wire N_1561 ;
wire N_1567 ;
wire N_934 ;
wire N_2722 ;
wire N_45 ;
wire N_54 ;
wire m7 ;
wire N_1901 ;
wire addr_4_sqmuxa_1_1 ;
wire un1_b57 ;
wire rd_4_sqmuxa ;
wire N_1740 ;
wire N_2240_i ;
wire N_3568 ;
wire N_2660_2 ;
wire N_915 ;
wire N_919 ;
wire N_918 ;
wire N_1076 ;
wire N_1044 ;
wire N_953 ;
wire N_921 ;
wire N_959 ;
wire N_927 ;
wire N_969 ;
wire N_937 ;
wire N_1084 ;
wire N_1052 ;
wire N_965 ;
wire N_933 ;
wire N_1741 ;
wire N_1679 ;
wire N_1742 ;
wire N_1680 ;
wire N_3614 ;
wire N_974 ;
wire N_942 ;
wire N_1838 ;
wire N_1683 ;
wire N_1039 ;
wire N_1085 ;
wire N_1053 ;
wire N_1083 ;
wire N_1051 ;
wire N_1040 ;
wire N_1038 ;
wire N_952 ;
wire N_920 ;
wire N_1077 ;
wire N_1045 ;
wire N_1081 ;
wire N_1049 ;
wire N_1827 ;
wire N_1672 ;
wire N_1082 ;
wire N_1050 ;
wire N_964 ;
wire N_932 ;
wire N_962 ;
wire N_930 ;
wire N_967 ;
wire N_935 ;
wire N_1079 ;
wire N_1047 ;
wire N_1068 ;
wire N_1036 ;
wire N_1078 ;
wire N_1046 ;
wire N_968 ;
wire N_936 ;
wire N_1069 ;
wire N_1037 ;
wire N_916 ;
wire N_1080 ;
wire N_1048 ;
wire N_1815 ;
wire N_1660 ;
wire N_1820 ;
wire N_1818 ;
wire N_1814 ;
wire N_1665 ;
wire N_1663 ;
wire N_1659 ;
wire N_1752 ;
wire N_1690 ;
wire N_955 ;
wire N_923 ;
wire N_954 ;
wire N_922 ;
wire N_1823 ;
wire N_1668 ;
wire N_956 ;
wire N_924 ;
wire N_1822 ;
wire N_1667 ;
wire N_957 ;
wire N_925 ;
wire N_1829 ;
wire N_1824 ;
wire N_1674 ;
wire N_1669 ;
wire N_961 ;
wire N_929 ;
wire N_1817 ;
wire N_1662 ;
wire N_963 ;
wire N_931 ;
wire N_1830 ;
wire N_1826 ;
wire N_1675 ;
wire N_1671 ;
wire N_960 ;
wire N_928 ;
wire N_1832 ;
wire N_1677 ;
wire N_1831 ;
wire N_1821 ;
wire N_1676 ;
wire N_1666 ;
wire N_1041 ;
wire N_1828 ;
wire N_1673 ;
wire N_972 ;
wire N_940 ;
wire N_1840 ;
wire N_1685 ;
wire N_975 ;
wire N_943 ;
wire N_1839 ;
wire N_1684 ;
wire N_973 ;
wire N_941 ;
wire N_958 ;
wire N_926 ;
wire un1_b59 ;
wire N_1813 ;
wire N_1732 ;
wire N_1670 ;
wire N_1658 ;
wire N_1751 ;
wire N_1689 ;
wire N_1583 ;
wire N_1582 ;
wire N_1581 ;
wire N_1580 ;
wire N_1575 ;
wire N_1574 ;
wire N_1573 ;
wire N_1572 ;
wire N_1571 ;
wire N_1570 ;
wire N_1569 ;
wire N_1568 ;
wire N_1565 ;
wire N_1564 ;
wire N_1563 ;
wire N_1562 ;
wire N_1560 ;
wire N_1035 ;
wire N_1363 ;
wire N_1362 ;
wire N_1361 ;
wire N_1354 ;
wire N_1353 ;
wire N_1352 ;
wire N_1351 ;
wire N_1383 ;
wire N_1350 ;
wire N_1382 ;
wire N_1349 ;
wire N_1381 ;
wire N_1348 ;
wire N_1380 ;
wire N_1347 ;
wire N_1379 ;
wire N_1346 ;
wire N_1378 ;
wire N_1345 ;
wire N_1377 ;
wire N_1344 ;
wire N_1376 ;
wire N_1341 ;
wire N_1373 ;
wire N_1340 ;
wire N_1372 ;
wire N_1339 ;
wire N_1371 ;
wire N_1338 ;
wire N_1370 ;
wire N_1336 ;
wire N_1368 ;
wire N_1335 ;
wire inf_abs0_2_axb_0 ;
wire inf_abs0_2_cry_0 ;
wire inf_abs0_2_axb_1 ;
wire inf_abs0_2_cry_1 ;
wire inf_abs0_2_axb_2 ;
wire inf_abs0_2_cry_2 ;
wire inf_abs0_2_axb_3 ;
wire inf_abs0_2_cry_3 ;
wire inf_abs0_2_axb_4 ;
wire inf_abs0_2_cry_4 ;
wire inf_abs0_2_axb_5 ;
wire inf_abs0_2_cry_5 ;
wire inf_abs0_2_axb_6 ;
wire inf_abs0_2_cry_6 ;
wire inf_abs0_2_axb_7 ;
wire inf_abs0_2_cry_7 ;
wire inf_abs0_2_axb_8 ;
wire inf_abs0_2_cry_8 ;
wire inf_abs0_2_axb_9 ;
wire inf_abs0_2_cry_9 ;
wire inf_abs0_2_axb_10 ;
wire inf_abs0_2_cry_10 ;
wire inf_abs0_2_axb_11 ;
wire inf_abs0_2_cry_11 ;
wire inf_abs0_2_axb_12 ;
wire inf_abs0_2_cry_12 ;
wire inf_abs0_2_axb_13 ;
wire inf_abs0_2_cry_13 ;
wire inf_abs0_2_axb_14 ;
wire inf_abs0_2_cry_14 ;
wire inf_abs0_2_axb_15 ;
wire inf_abs0_2_cry_15 ;
wire inf_abs0_2_axb_16 ;
wire inf_abs0_2_cry_16 ;
wire inf_abs0_2_axb_17 ;
wire inf_abs0_2_cry_17 ;
wire inf_abs0_2_axb_18 ;
wire inf_abs0_2_cry_18 ;
wire inf_abs0_2_axb_19 ;
wire inf_abs0_2_cry_19 ;
wire inf_abs0_2_axb_20 ;
wire inf_abs0_2_cry_20 ;
wire inf_abs0_2_axb_21 ;
wire inf_abs0_2_cry_21 ;
wire inf_abs0_2_axb_22 ;
wire inf_abs0_2_cry_22 ;
wire inf_abs0_2_axb_23 ;
wire inf_abs0_2_cry_23 ;
wire inf_abs0_2_axb_24 ;
wire inf_abs0_2_cry_24 ;
wire inf_abs0_2_axb_25 ;
wire inf_abs0_2_cry_25 ;
wire inf_abs0_2_axb_26 ;
wire inf_abs0_2_cry_26 ;
wire inf_abs0_2_axb_27 ;
wire inf_abs0_2_cry_27 ;
wire inf_abs0_2_axb_28 ;
wire inf_abs0_2_cry_28 ;
wire inf_abs0_2_axb_29 ;
wire inf_abs0_2_cry_29 ;
wire inf_abs0_2_axb_30 ;
wire reg3_1_1_axb_0 ;
wire reg3_1_1_cry_0 ;
wire reg3_1_1_axb_1 ;
wire reg3_1_1_cry_1 ;
wire reg3_1_1_axb_2 ;
wire reg3_1_1_cry_2 ;
wire reg3_1_1_axb_3 ;
wire reg3_1_1_cry_3 ;
wire reg3_1_1_axb_4 ;
wire reg3_1_1_cry_4 ;
wire reg3_1_1_axb_5 ;
wire reg3_1_1_cry_5 ;
wire reg3_1_1_axb_6 ;
wire reg3_1_1_cry_6 ;
wire reg3_1_1_axb_7 ;
wire reg3_1_1_cry_7 ;
wire reg3_1_1_axb_8 ;
wire reg3_1_1_cry_8 ;
wire reg3_1_1_axb_9 ;
wire reg3_1_1_cry_9 ;
wire reg3_1_1_axb_10 ;
wire reg3_1_1_cry_10 ;
wire reg3_1_1_axb_11 ;
wire reg3_1_1_cry_11 ;
wire reg3_1_1_axb_12 ;
wire reg3_1_1_cry_12 ;
wire reg3_1_1_axb_13 ;
wire reg3_1_1_cry_13 ;
wire reg3_1_1_axb_14 ;
wire reg3_1_1_cry_14 ;
wire reg3_1_1_axb_15 ;
wire reg3_1_1_cry_15 ;
wire reg3_1_1_axb_16 ;
wire reg3_1_1_cry_16 ;
wire reg3_1_1_axb_17 ;
wire reg3_1_1_cry_17 ;
wire reg3_1_1_axb_18 ;
wire reg3_1_1_cry_18 ;
wire reg3_1_1_axb_19 ;
wire reg3_1_1_cry_19 ;
wire reg3_1_1_cry_20 ;
wire reg3_1_1_cry_21 ;
wire reg3_1_1_cry_22 ;
wire reg3_1_1_cry_23 ;
wire reg3_1_1_cry_24 ;
wire reg3_1_1_cry_25 ;
wire reg3_1_1_cry_26 ;
wire reg3_1_1_cry_27 ;
wire reg3_1_1_cry_28 ;
wire reg3_1_1_axb_29 ;
wire reg3_1_1_cry_29 ;
wire reg3_1_1_axb_30 ;
wire reg3_1_1_cry_30 ;
wire reg3_1_1_axb_31 ;
wire un3_t_s_1 ;
wire un3_t_s_2 ;
wire un3_t_s_3 ;
wire un3_t_s_4 ;
wire un3_t_s_5 ;
wire un3_t_s_6 ;
wire un3_t_s_7 ;
wire un3_t_s_8 ;
wire un3_t_s_9 ;
wire un3_t_s_10 ;
wire un3_t_s_11 ;
wire un3_t_s_12 ;
wire un3_t_s_13 ;
wire un3_t_s_14 ;
wire un3_t_s_15 ;
wire un3_t_s_16 ;
wire un3_t_s_17 ;
wire un3_t_s_18 ;
wire un3_t_s_19 ;
wire un3_t_s_20 ;
wire un3_t_s_21 ;
wire un3_t_s_22 ;
wire un3_t_s_23 ;
wire un3_t_s_24 ;
wire un3_t_s_25 ;
wire un3_t_s_26 ;
wire un3_t_s_27 ;
wire un3_t_s_28 ;
wire un3_t_s_29 ;
wire un3_t_s_30 ;
wire un3_t_s_31 ;
wire un3_t_cry_0 ;
wire un3_t_cry_1 ;
wire un3_t_axb_2 ;
wire un3_t_cry_2 ;
wire un3_t_cry_3 ;
wire un3_t_cry_4 ;
wire un3_t_cry_5 ;
wire un3_t_cry_6 ;
wire un3_t_cry_7 ;
wire un3_t_cry_8 ;
wire un3_t_cry_9 ;
wire un3_t_cry_10 ;
wire un3_t_cry_11 ;
wire un3_t_cry_12 ;
wire un3_t_cry_13 ;
wire un3_t_cry_14 ;
wire un3_t_cry_15 ;
wire un3_t_cry_16 ;
wire un3_t_cry_17 ;
wire un3_t_cry_18 ;
wire un3_t_cry_19 ;
wire un3_t_cry_20 ;
wire un3_t_cry_21 ;
wire un3_t_cry_22 ;
wire un3_t_cry_23 ;
wire un3_t_cry_24 ;
wire un3_t_cry_25 ;
wire un3_t_cry_26 ;
wire un3_t_cry_27 ;
wire un3_t_cry_28 ;
wire un3_t_axb_29 ;
wire un3_t_cry_29 ;
wire un3_t_axb_30 ;
wire un3_t_cry_30 ;
wire un3_t_axb_31 ;
wire un11_reg0_axb_0 ;
wire un11_reg0_cry_0 ;
wire un11_reg0_axb_1 ;
wire un11_reg0_cry_1 ;
wire un11_reg0_axb_2 ;
wire un11_reg0_cry_2 ;
wire un11_reg0_axb_3 ;
wire un11_reg0_cry_3 ;
wire un11_reg0_axb_4 ;
wire un11_reg0_cry_4 ;
wire un11_reg0_axb_5 ;
wire un11_reg0_cry_5 ;
wire un11_reg0_axb_6 ;
wire un11_reg0_cry_6 ;
wire un11_reg0_axb_7 ;
wire un11_reg0_cry_7 ;
wire un11_reg0_axb_8 ;
wire un11_reg0_cry_8 ;
wire un11_reg0_axb_9 ;
wire un11_reg0_cry_9 ;
wire un11_reg0_axb_10 ;
wire un11_reg0_cry_10 ;
wire un11_reg0_axb_11 ;
wire un11_reg0_cry_11 ;
wire un11_reg0_axb_12 ;
wire un11_reg0_cry_12 ;
wire un11_reg0_axb_13 ;
wire un11_reg0_cry_13 ;
wire un11_reg0_axb_14 ;
wire un11_reg0_cry_14 ;
wire un11_reg0_axb_15 ;
wire un11_reg0_cry_15 ;
wire un11_reg0_axb_16 ;
wire un11_reg0_cry_16 ;
wire un11_reg0_axb_17 ;
wire un11_reg0_cry_17 ;
wire un11_reg0_axb_18 ;
wire un11_reg0_cry_18 ;
wire un11_reg0_axb_19 ;
wire un11_reg0_cry_19 ;
wire un11_reg0_axb_20 ;
wire un11_reg0_cry_20 ;
wire un11_reg0_axb_21 ;
wire un11_reg0_cry_21 ;
wire un11_reg0_axb_22 ;
wire un11_reg0_cry_22 ;
wire un11_reg0_axb_23 ;
wire un11_reg0_cry_23 ;
wire un11_reg0_axb_24 ;
wire un11_reg0_cry_24 ;
wire un11_reg0_axb_25 ;
wire un11_reg0_cry_25 ;
wire un11_reg0_axb_26 ;
wire un11_reg0_cry_26 ;
wire un11_reg0_axb_27 ;
wire un11_reg0_cry_27 ;
wire un11_reg0_axb_28 ;
wire un11_reg0_cry_28 ;
wire un11_reg0_axb_29 ;
wire un32_reg0_s_1 ;
wire un32_reg0_s_2 ;
wire un32_reg0_s_3 ;
wire un32_reg0_s_4 ;
wire un32_reg0_s_5 ;
wire un32_reg0_s_6 ;
wire un32_reg0_s_7 ;
wire un32_reg0_s_8 ;
wire un32_reg0_s_9 ;
wire un32_reg0_s_10 ;
wire un32_reg0_s_11 ;
wire un32_reg0_s_12 ;
wire un32_reg0_s_13 ;
wire un32_reg0_s_14 ;
wire un32_reg0_s_15 ;
wire un32_reg0_s_16 ;
wire un32_reg0_s_17 ;
wire un32_reg0_s_18 ;
wire un32_reg0_s_19 ;
wire un32_reg0_s_20 ;
wire un32_reg0_s_21 ;
wire un32_reg0_s_22 ;
wire un32_reg0_s_23 ;
wire un32_reg0_s_24 ;
wire un32_reg0_s_25 ;
wire un32_reg0_s_26 ;
wire un32_reg0_s_27 ;
wire un32_reg0_s_28 ;
wire un32_reg0_s_29 ;
wire un32_reg0_cry_0 ;
wire un32_reg0_axb_1 ;
wire un32_reg0_cry_1 ;
wire un32_reg0_axb_2 ;
wire un32_reg0_cry_2 ;
wire un32_reg0_axb_3 ;
wire un32_reg0_cry_3 ;
wire un32_reg0_axb_4 ;
wire un32_reg0_cry_4 ;
wire un32_reg0_axb_5 ;
wire un32_reg0_cry_5 ;
wire un32_reg0_axb_6 ;
wire un32_reg0_cry_6 ;
wire un32_reg0_axb_7 ;
wire un32_reg0_cry_7 ;
wire un32_reg0_axb_8 ;
wire un32_reg0_cry_8 ;
wire un32_reg0_axb_9 ;
wire un32_reg0_cry_9 ;
wire un32_reg0_axb_10 ;
wire un32_reg0_cry_10 ;
wire un32_reg0_axb_11 ;
wire un32_reg0_cry_11 ;
wire un32_reg0_axb_12 ;
wire un32_reg0_cry_12 ;
wire un32_reg0_axb_13 ;
wire un32_reg0_cry_13 ;
wire un32_reg0_axb_14 ;
wire un32_reg0_cry_14 ;
wire un32_reg0_axb_15 ;
wire un32_reg0_cry_15 ;
wire un32_reg0_axb_16 ;
wire un32_reg0_cry_16 ;
wire un32_reg0_axb_17 ;
wire un32_reg0_cry_17 ;
wire un32_reg0_axb_18 ;
wire un32_reg0_cry_18 ;
wire un32_reg0_axb_19 ;
wire un32_reg0_cry_19 ;
wire un32_reg0_axb_20 ;
wire un32_reg0_cry_20 ;
wire un32_reg0_axb_21 ;
wire un32_reg0_cry_21 ;
wire un32_reg0_axb_22 ;
wire un32_reg0_cry_22 ;
wire un32_reg0_axb_23 ;
wire un32_reg0_cry_23 ;
wire un32_reg0_axb_24 ;
wire un32_reg0_cry_24 ;
wire un32_reg0_axb_25 ;
wire un32_reg0_cry_25 ;
wire un32_reg0_axb_26 ;
wire un32_reg0_cry_26 ;
wire un32_reg0_axb_27 ;
wire un32_reg0_cry_27 ;
wire un32_reg0_axb_28 ;
wire un32_reg0_cry_28 ;
wire un32_reg0_axb_29 ;
wire un1_inf_abs0_cry_0 ;
wire un1_inf_abs0_axb_1 ;
wire un1_inf_abs0_cry_1 ;
wire un1_inf_abs0_axb_2 ;
wire un1_inf_abs0_cry_2 ;
wire un1_inf_abs0_axb_3 ;
wire un1_inf_abs0_cry_3 ;
wire un1_inf_abs0_axb_4 ;
wire un1_inf_abs0_cry_4 ;
wire un1_inf_abs0_axb_5 ;
wire un1_inf_abs0_cry_5 ;
wire un1_inf_abs0_axb_6 ;
wire un1_inf_abs0_cry_6 ;
wire un1_inf_abs0_axb_7 ;
wire un1_inf_abs0_cry_7 ;
wire un1_inf_abs0_axb_8 ;
wire un1_inf_abs0_cry_8 ;
wire un1_inf_abs0_axb_9 ;
wire un1_inf_abs0_cry_9 ;
wire un1_inf_abs0_axb_10 ;
wire un1_inf_abs0_cry_10 ;
wire un1_inf_abs0_axb_11 ;
wire un1_inf_abs0_cry_11 ;
wire un1_inf_abs0_axb_12 ;
wire un1_inf_abs0_cry_12 ;
wire un1_inf_abs0_axb_13 ;
wire un1_inf_abs0_cry_13 ;
wire un1_inf_abs0_axb_14 ;
wire un1_inf_abs0_cry_14 ;
wire un1_inf_abs0_axb_15 ;
wire un1_inf_abs0_cry_15 ;
wire un1_inf_abs0_axb_16 ;
wire un1_inf_abs0_cry_16 ;
wire un1_inf_abs0_axb_17 ;
wire un1_inf_abs0_cry_17 ;
wire un1_inf_abs0_axb_18 ;
wire un1_inf_abs0_cry_18 ;
wire un1_inf_abs0_axb_19 ;
wire un1_inf_abs0_0_cry_0 ;
wire un1_inf_abs0_0_axb_1 ;
wire un1_inf_abs0_0_cry_1 ;
wire un1_inf_abs0_0_axb_2 ;
wire un1_inf_abs0_0_cry_2 ;
wire un1_inf_abs0_0_axb_3 ;
wire un1_inf_abs0_0_cry_3 ;
wire un1_inf_abs0_0_axb_4 ;
wire un1_inf_abs0_0_cry_4 ;
wire un1_inf_abs0_0_axb_5 ;
wire un1_inf_abs0_0_cry_5 ;
wire un1_inf_abs0_0_axb_6 ;
wire un1_inf_abs0_0_cry_6 ;
wire un1_inf_abs0_0_axb_7 ;
wire un1_inf_abs0_0_cry_7 ;
wire un1_inf_abs0_0_axb_8 ;
wire un1_inf_abs0_0_cry_8 ;
wire un1_inf_abs0_0_axb_9 ;
wire un1_inf_abs0_0_cry_9 ;
wire un1_inf_abs0_0_axb_10 ;
wire un1_inf_abs0_0_cry_10 ;
wire un1_inf_abs0_0_axb_11 ;
wire un1_inf_abs0_0_cry_11 ;
wire un1_inf_abs0_0_axb_12 ;
wire un1_inf_abs0_0_cry_12 ;
wire un1_inf_abs0_0_axb_13 ;
wire un1_inf_abs0_0_cry_13 ;
wire un1_inf_abs0_0_axb_14 ;
wire un1_inf_abs0_0_cry_14 ;
wire un1_inf_abs0_0_axb_15 ;
wire un1_inf_abs0_0_cry_15 ;
wire un1_inf_abs0_0_axb_16 ;
wire un1_inf_abs0_0_cry_16 ;
wire un1_inf_abs0_0_axb_17 ;
wire un1_inf_abs0_0_cry_17 ;
wire un1_inf_abs0_0_axb_18 ;
wire un1_inf_abs0_0_cry_18 ;
wire un1_inf_abs0_0_axb_19 ;
wire un3_reg3_s_1 ;
wire un3_reg3_s_2 ;
wire un3_reg3_s_3 ;
wire un3_reg3_s_4 ;
wire un3_reg3_s_5 ;
wire un3_reg3_s_6 ;
wire un3_reg3_s_7 ;
wire un3_reg3_s_8 ;
wire un3_reg3_s_9 ;
wire un3_reg3_s_10 ;
wire un3_reg3_s_11 ;
wire un3_reg3_s_12 ;
wire un3_reg3_s_13 ;
wire un3_reg3_s_14 ;
wire un3_reg3_s_15 ;
wire un3_reg3_s_16 ;
wire un3_reg3_s_17 ;
wire un3_reg3_s_18 ;
wire un3_reg3_s_19 ;
wire un3_reg3_s_20 ;
wire un3_reg3_s_21 ;
wire un3_reg3_s_22 ;
wire un3_reg3_s_23 ;
wire un3_reg3_s_24 ;
wire un3_reg3_s_25 ;
wire un3_reg3_cry_25 ;
wire un3_reg3_axb_1 ;
wire un3_reg3_cry_1 ;
wire un3_reg3_axb_2 ;
wire un3_reg3_cry_2 ;
wire un3_reg3_axb_3 ;
wire un3_reg3_cry_3 ;
wire un3_reg3_axb_4 ;
wire un3_reg3_cry_4 ;
wire un3_reg3_axb_5 ;
wire un3_reg3_cry_5 ;
wire un3_reg3_axb_6 ;
wire un3_reg3_cry_6 ;
wire un3_reg3_axb_7 ;
wire un3_reg3_cry_7 ;
wire un3_reg3_axb_8 ;
wire un3_reg3_cry_8 ;
wire un3_reg3_axb_9 ;
wire un3_reg3_cry_9 ;
wire un3_reg3_axb_10 ;
wire un3_reg3_cry_10 ;
wire un3_reg3_axb_11 ;
wire un3_reg3_cry_11 ;
wire un3_reg3_axb_12 ;
wire un3_reg3_cry_12 ;
wire un3_reg3_axb_13 ;
wire un3_reg3_cry_13 ;
wire un3_reg3_axb_14 ;
wire un3_reg3_cry_14 ;
wire un3_reg3_axb_15 ;
wire un3_reg3_cry_15 ;
wire un3_reg3_axb_16 ;
wire un3_reg3_cry_16 ;
wire un3_reg3_axb_17 ;
wire un3_reg3_cry_17 ;
wire un3_reg3_axb_18 ;
wire un3_reg3_cry_18 ;
wire un3_reg3_axb_19 ;
wire un3_reg3_cry_19 ;
wire un3_reg3_axb_20 ;
wire un3_reg3_cry_20 ;
wire un3_reg3_axb_21 ;
wire un3_reg3_cry_21 ;
wire un3_reg3_axb_22 ;
wire un3_reg3_cry_22 ;
wire un3_reg3_axb_23 ;
wire un3_reg3_cry_23 ;
wire un3_reg3_axb_24 ;
wire un3_reg3_cry_24 ;
wire un3_reg3_axb_25 ;
wire t_1_cry_0 ;
wire t_1_cry_1 ;
wire t_1_cry_2 ;
wire t_1_cry_3 ;
wire t_1_cry_4 ;
wire t_1_cry_5 ;
wire t_1_cry_6 ;
wire t_1_cry_7 ;
wire t_1_cry_8 ;
wire t_1_cry_9 ;
wire t_1_cry_10 ;
wire t_1_cry_11 ;
wire t_1_cry_12 ;
wire t_1_cry_13 ;
wire t_1_cry_14 ;
wire t_1_cry_15 ;
wire t_1_cry_16 ;
wire t_1_cry_17 ;
wire t_1_cry_18 ;
wire t_1_cry_19 ;
wire t_1_cry_20 ;
wire t_1_cry_21 ;
wire t_1_cry_22 ;
wire t_1_cry_23 ;
wire t_1_cry_24 ;
wire t_1_cry_25 ;
wire t_1_cry_26 ;
wire t_1_cry_27 ;
wire t_1_cry_28 ;
wire t_1_cry_29 ;
wire t_1_cry_30 ;
wire \d_cnst_sn.reg1_16_8_1837_2_tz ;
wire reg0_28_sn_m6_lut6_2_O5 ;
wire \d_cnst_sn.reg3_17_sn_m7_0 ;
wire reg3_1_sqmuxa_RNIH1DM1 ;
wire reg3_1_sqmuxa_RNIE1DM1 ;
wire reg3_1_sqmuxa_RNIQMUH1 ;
wire reg3_1_sqmuxa_RNITMUH1 ;
wire reg3_1_sqmuxa_RNIKMUH1 ;
wire reg3_1_sqmuxa_RNINMUH1 ;
wire reg3_1_sqmuxa_RNIHMUH1 ;
wire reg3_1_sqmuxa_RNIEMUH1 ;
wire reg0_m9_i_a1 ;
wire \d_cnst_sn.reg2_N_3_mux ;
wire g0_2_0_i2_lut6_2_O6 ;
wire reg3_N_7_i_RNO ;
wire \d_cnst_sn.reg1_16_9_1804_3_tz ;
wire \d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ;
wire \d_cnst_sn.reg0_m8_e_0 ;
wire \d_cnst_sn.reg3_5_sqmuxa_2_1 ;
wire \d_cnst_sn.reg0_28_9_2294_a6_3_0 ;
wire N_3910 ;
wire \d_cnst_sn.un1_state_3_1 ;
wire \d_cnst_sn.b60_0 ;
wire \d_cnst_sn.b64_0 ;
wire \d_cnst_sn.reg0_m9_i_a3_0 ;
wire reg3_17_sn_N_5 ;
wire \d_cnst_sn.reg0_28_2526_a5_1_0 ;
wire N_4571_i ;
wire N_4570_i ;
wire N_4569_i ;
wire N_4568_i ;
wire N_4567_i ;
wire N_4566_i ;
wire N_4565_i ;
wire N_4564_i ;
wire N_4563_i ;
wire N_4562_i ;
wire N_4561_i ;
wire N_4560_i ;
wire N_4559_i ;
wire N_4558_i ;
wire N_4557_i ;
wire N_4556_i ;
wire N_4555_i ;
wire N_4554_i ;
wire N_4553_i ;
wire N_4552_i ;
wire N_4551_i ;
wire N_4550_i ;
wire N_4549_i ;
wire N_4548_i ;
wire N_4547_i ;
wire N_4546_i ;
wire N_4545_i ;
wire N_4544_i ;
wire N_4543_i ;
wire N_4542_i ;
wire N_4541_i ;
wire \d_cnst_sn.reg3_N_7_i ;
wire N_2099_i ;
wire addr_0_sqmuxa_1_i ;
wire N_2119_i ;
wire N_2139_i ;
wire N_2159_i ;
wire N_2179_i ;
wire N_2199_i ;
wire N_2219_i ;
wire N_56_i ;
wire N_2267_i ;
wire N_47_i ;
wire N_2315_i ;
wire N_2335_i ;
wire N_36_i ;
wire N_2516_i ;
wire N_2536_i ;
wire N_2556_i ;
wire N_2576_i ;
wire N_2596_i ;
wire N_2616_i ;
wire N_2636_i ;
wire N_2656_i ;
wire un1_state_1_0_i ;
wire un1_state_3_i ;
wire un1_state_4_i ;
wire \d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ;
wire \d_cnst_sn.m26_0_1 ;
wire \d_cnst_sn.m19_0_1 ;
wire \d_cnst_sn.addr_20_iv_7_654_i_1 ;
wire \d_cnst_sn.addr_20_iv_8_627_i_1 ;
wire \d_cnst_sn.addr_20_iv_16_389_i_1 ;
wire \d_cnst_sn.addr_20_iv_12_497_i_1 ;
wire \d_cnst_sn.addr_20_iv_10_562_i_1 ;
wire \d_cnst_sn.addr_20_iv_14_443_i_2 ;
wire \d_cnst_sn.addr_20_iv_15_416_i_1 ;
wire \d_cnst_sn.addr_20_iv_17_362_i_1 ;
wire \d_cnst_sn.addr_20_iv_13_470_i_1 ;
wire \d_cnst_sn.addr_20_iv_18_335_i_1 ;
wire \d_cnst_sn.addr_20_iv_2_971_i_0 ;
wire \d_cnst_sn.addr_20_iv_1_998_i_0 ;
wire \d_cnst_sn.addr_20_iv_1052_i_0 ;
wire \d_cnst_sn.addr_20_iv_0_1025_i_0 ;
wire \d_cnst_sn.addr_20_iv_3_944_i_0 ;
wire \d_cnst_sn.addr_20_iv_4_917_i_0 ;
wire \d_cnst_sn.addr_20_iv_5_890_i_0 ;
wire \d_cnst_sn.addr_20_iv_6_863_i_0 ;
wire \d_cnst_sn.reg0_28_12_2195_a6_1_2_0 ;
wire \d_cnst_sn.reg0_m9_i_a0_0 ;
wire \d_cnst_sn.reg0_28_5_2426_a6_1_1 ;
wire \d_cnst_sn.reg0_28_5_2426_3_1 ;
wire \d_cnst_sn.reg0_28_8_2327_a6_1_1 ;
wire \d_cnst_sn.reg0_28_6_2393_3_1 ;
wire \d_cnst_sn.reg0_28_6_2393_a6_1_1 ;
wire \d_cnst_sn.reg0_28_7_2360_3_1 ;
wire \d_cnst_sn.reg0_28_7_2360_a6_1_1 ;
wire \d_cnst_sn.reg0_28_14_2135_1_a0_2 ;
wire \d_cnst_sn.reg0_28_9_2294_a6_1_1 ;
wire \d_cnst_sn.reg0_28_9_2294_3_1 ;
wire \d_cnst_sn.reg1_16_7_1870_3_1 ;
wire \d_cnst_sn.reg0_28_10_2261_a6_1_1 ;
wire \d_cnst_sn.reg1_16_8_1837_3_1 ;
wire \d_cnst_sn.reg0_28_11_2228_a6_1_1 ;
wire \d_cnst_sn.reg0_28_3_2492_0 ;
wire \d_cnst_sn.reg0_28_3_2492_1 ;
wire \d_cnst_sn.reg0_28_4_2459_0 ;
wire \d_cnst_sn.reg0_28_8_2327_0 ;
wire \d_cnst_sn.reg0_28_5_2426_0 ;
wire \d_cnst_sn.reg0_28_6_2393_0 ;
wire \d_cnst_sn.reg0_28_7_2360_0 ;
wire \d_cnst_sn.reg0_28_14_0 ;
wire \d_cnst_sn.reg0_28_9_2294_0 ;
wire \d_cnst_sn.reg1_16_7_1870_0 ;
wire \d_cnst_sn.reg1_16_8_1837_0 ;
wire b_0 ;
wire un3_t_axb_28 ;
wire un3_t_axb_27 ;
wire un3_t_axb_26 ;
wire un3_t_axb_25 ;
wire un3_t_axb_24 ;
wire un3_t_axb_23 ;
wire un3_t_axb_22 ;
wire un3_t_axb_21 ;
wire un3_t_axb_20 ;
wire un3_t_axb_19 ;
wire un3_t_axb_18 ;
wire un3_t_axb_17 ;
wire un3_t_axb_16 ;
wire un3_t_axb_15 ;
wire un3_t_axb_14 ;
wire un3_t_axb_13 ;
wire un3_t_axb_12 ;
wire un3_t_axb_11 ;
wire un3_t_axb_10 ;
wire un3_t_axb_9 ;
wire un3_t_axb_8 ;
wire un3_t_axb_7 ;
wire un3_t_axb_6 ;
wire un3_t_axb_5 ;
wire un3_t_axb_4 ;
wire un3_t_axb_3 ;
wire un3_t_axb_1 ;
wire un3_t_axb_0 ;
wire reg3_1_1_axb_28 ;
wire reg3_1_1_axb_27 ;
wire reg3_1_1_axb_26 ;
wire reg3_1_1_axb_25 ;
wire reg3_1_1_axb_24 ;
wire reg3_1_1_axb_23 ;
wire reg3_1_1_axb_22 ;
wire reg3_1_1_axb_21 ;
wire reg3_1_1_axb_20 ;
wire t_1_cry_0_cy ;
wire un3_t_cry_0_cy ;
wire N_7 ;
wire N_12 ;
wire \d_cnst_sn.g0_3_a2_2 ;
wire \d_cnst_sn.g0_3_1 ;
wire \d_cnst_sn.g3 ;
wire \d_cnst_sn.reg0_N_13_0 ;
wire \d_cnst_sn.g0_0_2 ;
wire \d_cnst_sn.g0_1 ;
wire N_7_0 ;
wire \d_cnst_sn.g0_0_0_a5_0_0 ;
wire \d_cnst_sn.g0_0_0_a5_2 ;
wire \d_cnst_sn.g0_0_0_1 ;
wire N_3856_rep1 ;
wire N_3569_rep1 ;
wire N_3289_rep1 ;
wire N_3315_rep1 ;
wire N_3550_rep1 ;
wire N_3341_rep1 ;
wire N_3673_rep1 ;
wire N_3699_rep1 ;
wire N_3725_rep1 ;
wire N_3751_rep1 ;
wire N_3777_rep1 ;
wire N_3803_rep1 ;
wire N_3829_rep1 ;
wire \d_cnst_sn.g0_rn_1 ;
wire reg0_28_7_rep1 ;
wire d_cnst_ss0_x ;
wire un1_cf_x ;
wire un3_reg3_cry_25_0 ;
wire un3_reg3_cry_25_1 ;
wire inf_abs0_2_cry_29_0 ;
wire inf_abs0_2_cry_29_1 ;
GND GND_cZ (
.G(GND)
);
VCC VCC_cZ (
.P(VCC)
);
// @7:74
MUXF8 \d_cnst_sn.reg2_16_11mux[1] (
.I0(\d_cnst_sn.reg2_16_11muxnet_0 [1]),
.I1(\d_cnst_sn.reg2_16_11muxnet_1 [1]),
.S(N_513_i),
.O(reg2_16[1])
);
MUXF7 \d_cnst_sn.reg2_16_11mux_RNO_0[1] (
.I0(N_1560),
.I1(t_6[1]),
.S(N_514_i),
.O(\d_cnst_sn.reg2_16_11muxnet_1 [1])
);
MUXF7 \d_cnst_sn.reg2_16_11mux_RNO[1] (
.I0(N_1336),
.I1(N_1368),
.S(N_514_i),
.O(\d_cnst_sn.reg2_16_11muxnet_0 [1])
);
// @7:83
LUT1 inf_abs0_2_cry_29_outextlut (
.I0(VCC),
.O(inf_abs0_2_cry_29_1)
);
defparam inf_abs0_2_cry_29_outextlut.INIT=2'h3;
// @7:95
LUT1 un3_reg3_cry_25_outextlut (
.I0(VCC),
.O(un3_reg3_cry_25_1)
);
defparam un3_reg3_cry_25_outextlut.INIT=2'h3;
// @7:83
LUT1 inf_abs0_2_cry_30_outextlut (
.I0(VCC),
.O(inf_abs0_2_1[31])
);
defparam inf_abs0_2_cry_30_outextlut.INIT=2'h3;
// @7:97
LUT6_2 \d_cnst_sn.r_4_3_lut6_2[30] (
.I0(reg0[30]),
.I1(reg1[30]),
.I2(reg2[30]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(inf_abs0_2[31]),
.O6(r_4[30]),
.O5(r_4_3_lut6_2_O5[30])
);
defparam \d_cnst_sn.r_4_3_lut6_2[30] .INIT=64'hAAAAAAAA00F0CCAA;
// @7:118
LUT4 un11_r_df0_cZ (
.I0(m_2[0]),
.I1(m_2[1]),
.I2(r_4[0]),
.I3(r_4[1]),
.O(un11_r_df0)
);
defparam un11_r_df0_cZ.INIT=16'h8421;
// @7:118
LUT4 un11_r_df2_cZ (
.I0(N_28),
.I1(m_2[2]),
.I2(m_2[3]),
.I3(r_4[3]),
.O(un11_r_df2)
);
defparam un11_r_df2_cZ.INIT=16'h9009;
// @7:118
LUT4 un11_r_df4_cZ (
.I0(m_2[4]),
.I1(m_2[5]),
.I2(r_4[4]),
.I3(r_4[5]),
.O(un11_r_df4)
);
defparam un11_r_df4_cZ.INIT=16'h8421;
// @7:118
LUT4 un11_r_df6_cZ (
.I0(m_2[6]),
.I1(m_2[7]),
.I2(r_4[6]),
.I3(r_4[7]),
.O(un11_r_df6)
);
defparam un11_r_df6_cZ.INIT=16'h8421;
// @7:118
LUT4 un11_r_df8_cZ (
.I0(m_2[8]),
.I1(m_2[9]),
.I2(r_4[8]),
.I3(r_4[9]),
.O(un11_r_df8)
);
defparam un11_r_df8_cZ.INIT=16'h8421;
// @7:118
LUT4 un11_r_df10_cZ (
.I0(m_2[10]),
.I1(m_2[11]),
.I2(r_4[10]),
.I3(r_4[11]),
.O(un11_r_df10)
);
defparam un11_r_df10_cZ.INIT=16'h8421;
// @7:118
LUT4 un11_r_df12_cZ (
.I0(m_2[12]),
.I1(m_2[13]),
.I2(r_4[12]),
.I3(r_4[13]),
.O(un11_r_df12)
);
defparam un11_r_df12_cZ.INIT=16'h8421;
// @7:118
LUT4 un11_r_df14_cZ (
.I0(m_2[14]),
.I1(m_2[15]),
.I2(r_4[14]),
.I3(r_4[15]),
.O(un11_r_df14)
);
defparam un11_r_df14_cZ.INIT=16'h8421;
// @7:118
LUT4 un11_r_df16_cZ (
.I0(m_2[16]),
.I1(m_2[17]),
.I2(r_4[16]),
.I3(r_4[17]),
.O(un11_r_df16)
);
defparam un11_r_df16_cZ.INIT=16'h8421;
// @7:118
LUT4 un11_r_df18_cZ (
.I0(m_2[18]),
.I1(m_2[19]),
.I2(r_4[18]),
.I3(r_4[19]),
.O(un11_r_df18)
);
defparam un11_r_df18_cZ.INIT=16'h8421;
// @7:143
LUT4 b18_df0_cZ (
.I0(m_2[0]),
.I1(m_2[1]),
.I2(r_4[0]),
.I3(r_4[1]),
.O(b18_df0)
);
defparam b18_df0_cZ.INIT=16'h8421;
// @7:143
LUT4 b18_df2_cZ (
.I0(N_28),
.I1(m_2[2]),
.I2(m_2[3]),
.I3(r_4[3]),
.O(b18_df2)
);
defparam b18_df2_cZ.INIT=16'h9009;
// @7:143
LUT4 b18_df4_cZ (
.I0(m_2[4]),
.I1(m_2[5]),
.I2(r_4[4]),
.I3(r_4[5]),
.O(b18_df4)
);
defparam b18_df4_cZ.INIT=16'h8421;
// @7:143
LUT4 b18_df6_cZ (
.I0(m_2[6]),
.I1(m_2[7]),
.I2(r_4[6]),
.I3(r_4[7]),
.O(b18_df6)
);
defparam b18_df6_cZ.INIT=16'h8421;
// @7:143
LUT4 b18_df8_cZ (
.I0(m_2[8]),
.I1(m_2[9]),
.I2(r_4[8]),
.I3(r_4[9]),
.O(b18_df8)
);
defparam b18_df8_cZ.INIT=16'h8421;
// @7:143
LUT4 b18_df10_cZ (
.I0(m_2[10]),
.I1(m_2[11]),
.I2(r_4[10]),
.I3(r_4[11]),
.O(b18_df10)
);
defparam b18_df10_cZ.INIT=16'h8421;
// @7:143
LUT4 b18_df12_cZ (
.I0(m_2[12]),
.I1(m_2[13]),
.I2(r_4[12]),
.I3(r_4[13]),
.O(b18_df12)
);
defparam b18_df12_cZ.INIT=16'h8421;
// @7:143
LUT4 b18_df14_cZ (
.I0(m_2[14]),
.I1(m_2[15]),
.I2(r_4[14]),
.I3(r_4[15]),
.O(b18_df14)
);
defparam b18_df14_cZ.INIT=16'h8421;
// @7:143
LUT4 b18_df16_cZ (
.I0(m_2[16]),
.I1(m_2[17]),
.I2(r_4[16]),
.I3(r_4[17]),
.O(b18_df16)
);
defparam b18_df16_cZ.INIT=16'h8421;
// @7:143
LUT4 b18_df18_cZ (
.I0(m_2[18]),
.I1(m_2[19]),
.I2(r_4[18]),
.I3(r_4[19]),
.O(b18_df18)
);
defparam b18_df18_cZ.INIT=16'h8421;
// @7:151
LUT4 un26_r_df0_cZ (
.I0(m_2[0]),
.I1(m_2[1]),
.I2(r_4[0]),
.I3(r_4[1]),
.O(un26_r_df0)
);
defparam un26_r_df0_cZ.INIT=16'h8421;
// @7:151
LUT4 un26_r_df2_cZ (
.I0(N_28),
.I1(m_2[2]),
.I2(m_2[3]),
.I3(r_4[3]),
.O(un26_r_df2)
);
defparam un26_r_df2_cZ.INIT=16'h9009;
// @7:151
LUT4 un26_r_df4_cZ (
.I0(m_2[4]),
.I1(m_2[5]),
.I2(r_4[4]),
.I3(r_4[5]),
.O(un26_r_df4)
);
defparam un26_r_df4_cZ.INIT=16'h8421;
// @7:151
LUT4 un26_r_df6_cZ (
.I0(m_2[6]),
.I1(m_2[7]),
.I2(r_4[6]),
.I3(r_4[7]),
.O(un26_r_df6)
);
defparam un26_r_df6_cZ.INIT=16'h8421;
// @7:151
LUT4 un26_r_df8_cZ (
.I0(m_2[8]),
.I1(m_2[9]),
.I2(r_4[8]),
.I3(r_4[9]),
.O(un26_r_df8)
);
defparam un26_r_df8_cZ.INIT=16'h8421;
// @7:151
LUT4 un26_r_df10_cZ (
.I0(m_2[10]),
.I1(m_2[11]),
.I2(r_4[10]),
.I3(r_4[11]),
.O(un26_r_df10)
);
defparam un26_r_df10_cZ.INIT=16'h8421;
// @7:151
LUT4 un26_r_df12_cZ (
.I0(m_2[12]),
.I1(m_2[13]),
.I2(r_4[12]),
.I3(r_4[13]),
.O(un26_r_df12)
);
defparam un26_r_df12_cZ.INIT=16'h8421;
// @7:151
LUT4 un26_r_df14_cZ (
.I0(m_2[14]),
.I1(m_2[15]),
.I2(r_4[14]),
.I3(r_4[15]),
.O(un26_r_df14)
);
defparam un26_r_df14_cZ.INIT=16'h8421;
// @7:151
LUT4 un26_r_df16_cZ (
.I0(m_2[16]),
.I1(m_2[17]),
.I2(r_4[16]),
.I3(r_4[17]),
.O(un26_r_df16)
);
defparam un26_r_df16_cZ.INIT=16'h8421;
// @7:151
LUT4 un26_r_df18_cZ (
.I0(m_2[18]),
.I1(m_2[19]),
.I2(r_4[18]),
.I3(r_4[19]),
.O(un26_r_df18)
);
defparam un26_r_df18_cZ.INIT=16'h8421;
// @7:83
LUT2 inf_abs0_2_axb_0_cZ (
.I0(ir[0]),
.I1(ir_fast[31]),
.O(inf_abs0_2_axb_0)
);
defparam inf_abs0_2_axb_0_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_1_cZ (
.I0(ir[1]),
.I1(ir_fast[31]),
.O(inf_abs0_2_axb_1)
);
defparam inf_abs0_2_axb_1_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_2_cZ (
.I0(ir[2]),
.I1(ir_fast[31]),
.O(inf_abs0_2_axb_2)
);
defparam inf_abs0_2_axb_2_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_3_cZ (
.I0(ir[3]),
.I1(ir_fast[31]),
.O(inf_abs0_2_axb_3)
);
defparam inf_abs0_2_axb_3_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_4_cZ (
.I0(ir[4]),
.I1(ir_fast[31]),
.O(inf_abs0_2_axb_4)
);
defparam inf_abs0_2_axb_4_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_5_cZ (
.I0(ir[5]),
.I1(ir_fast[31]),
.O(inf_abs0_2_axb_5)
);
defparam inf_abs0_2_axb_5_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_6_cZ (
.I0(ir[6]),
.I1(ir_fast[31]),
.O(inf_abs0_2_axb_6)
);
defparam inf_abs0_2_axb_6_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_7_cZ (
.I0(ir[7]),
.I1(ir_fast[31]),
.O(inf_abs0_2_axb_7)
);
defparam inf_abs0_2_axb_7_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_8_cZ (
.I0(ir[8]),
.I1(ir_fast[31]),
.O(inf_abs0_2_axb_8)
);
defparam inf_abs0_2_axb_8_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_9_cZ (
.I0(ir[9]),
.I1(ir[31]),
.O(inf_abs0_2_axb_9)
);
defparam inf_abs0_2_axb_9_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_10_cZ (
.I0(ir[10]),
.I1(ir[31]),
.O(inf_abs0_2_axb_10)
);
defparam inf_abs0_2_axb_10_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_11_cZ (
.I0(ir[11]),
.I1(ir[31]),
.O(inf_abs0_2_axb_11)
);
defparam inf_abs0_2_axb_11_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_12_cZ (
.I0(ir[12]),
.I1(ir[31]),
.O(inf_abs0_2_axb_12)
);
defparam inf_abs0_2_axb_12_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_13_cZ (
.I0(ir[13]),
.I1(ir[31]),
.O(inf_abs0_2_axb_13)
);
defparam inf_abs0_2_axb_13_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_14_cZ (
.I0(ir[14]),
.I1(ir[31]),
.O(inf_abs0_2_axb_14)
);
defparam inf_abs0_2_axb_14_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_15_cZ (
.I0(ir[15]),
.I1(ir[31]),
.O(inf_abs0_2_axb_15)
);
defparam inf_abs0_2_axb_15_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_16_cZ (
.I0(ir[16]),
.I1(ir[31]),
.O(inf_abs0_2_axb_16)
);
defparam inf_abs0_2_axb_16_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_17_cZ (
.I0(ir[17]),
.I1(ir[31]),
.O(inf_abs0_2_axb_17)
);
defparam inf_abs0_2_axb_17_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_18_cZ (
.I0(ir[18]),
.I1(ir[31]),
.O(inf_abs0_2_axb_18)
);
defparam inf_abs0_2_axb_18_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_19_cZ (
.I0(ir[19]),
.I1(ir[31]),
.O(inf_abs0_2_axb_19)
);
defparam inf_abs0_2_axb_19_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_20_cZ (
.I0(ir[20]),
.I1(ir[31]),
.O(inf_abs0_2_axb_20)
);
defparam inf_abs0_2_axb_20_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_21_cZ (
.I0(ir[21]),
.I1(ir[31]),
.O(inf_abs0_2_axb_21)
);
defparam inf_abs0_2_axb_21_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_22_cZ (
.I0(ir[22]),
.I1(ir[31]),
.O(inf_abs0_2_axb_22)
);
defparam inf_abs0_2_axb_22_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_23_cZ (
.I0(ir[23]),
.I1(ir[31]),
.O(inf_abs0_2_axb_23)
);
defparam inf_abs0_2_axb_23_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_24_cZ (
.I0(ir[24]),
.I1(ir[31]),
.O(inf_abs0_2_axb_24)
);
defparam inf_abs0_2_axb_24_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_25_cZ (
.I0(ir[25]),
.I1(ir[31]),
.O(inf_abs0_2_axb_25)
);
defparam inf_abs0_2_axb_25_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_26_cZ (
.I0(ir[26]),
.I1(ir[31]),
.O(inf_abs0_2_axb_26)
);
defparam inf_abs0_2_axb_26_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_27_cZ (
.I0(ir[27]),
.I1(ir[31]),
.O(inf_abs0_2_axb_27)
);
defparam inf_abs0_2_axb_27_cZ.INIT=4'h6;
// @7:83
LUT2 inf_abs0_2_axb_28_cZ (
.I0(ir[28]),
.I1(ir[31]),
.O(inf_abs0_2_axb_28)
);
defparam inf_abs0_2_axb_28_cZ.INIT=4'h6;
LUT4 \datai_RNI2UAU[20] (
.I0(datai[20]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_20)
);
defparam \datai_RNI2UAU[20] .INIT=16'hFF57;
LUT4 \datai_RNI3VAU[21] (
.I0(datai[21]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_21)
);
defparam \datai_RNI3VAU[21] .INIT=16'hFF57;
LUT4 \datai_RNI40BU[22] (
.I0(datai[22]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_22)
);
defparam \datai_RNI40BU[22] .INIT=16'hFF57;
LUT4 \datai_RNI51BU[23] (
.I0(datai[23]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_23)
);
defparam \datai_RNI51BU[23] .INIT=16'hFF57;
LUT4 \datai_RNI62BU[24] (
.I0(datai[24]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_24)
);
defparam \datai_RNI62BU[24] .INIT=16'hFF57;
LUT4 \datai_RNI73BU[25] (
.I0(datai[25]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_25)
);
defparam \datai_RNI73BU[25] .INIT=16'hFF57;
LUT4 \datai_RNI84BU[26] (
.I0(datai[26]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_26)
);
defparam \datai_RNI84BU[26] .INIT=16'hFF57;
LUT4 \datai_RNI95BU[27] (
.I0(datai[27]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_27)
);
defparam \datai_RNI95BU[27] .INIT=16'hFF57;
LUT4 \datai_RNIA6BU[28] (
.I0(datai[28]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_28)
);
defparam \datai_RNIA6BU[28] .INIT=16'hFF57;
// @7:243
LUT4 reg3_1_1_axb_29_cZ (
.I0(datai[29]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_29)
);
defparam reg3_1_1_axb_29_cZ.INIT=16'hFF57;
// @7:243
LUT4 reg3_1_1_axb_30_cZ (
.I0(datai[30]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[31]),
.O(reg3_1_1_axb_30)
);
defparam reg3_1_1_axb_30_cZ.INIT=16'hFF57;
// @7:74
LUT2 un1_inf_abs0_cry_0_RNO (
.I0(inf_abs0_2[0]),
.I1(reg2[0]),
.O(un1_inf_abs0_10[0])
);
defparam un1_inf_abs0_cry_0_RNO.INIT=4'h6;
// @7:74
LUT2 \reg2_RNIEGHO[1] (
.I0(inf_abs0_2[1]),
.I1(reg2[1]),
.O(un1_inf_abs0_axb_1)
);
defparam \reg2_RNIEGHO[1] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIGHHO[2] (
.I0(inf_abs0_2[2]),
.I1(reg2[2]),
.O(un1_inf_abs0_axb_2)
);
defparam \reg2_RNIGHHO[2] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIIIHO[3] (
.I0(inf_abs0_2[3]),
.I1(reg2[3]),
.O(un1_inf_abs0_axb_3)
);
defparam \reg2_RNIIIHO[3] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIKJHO[4] (
.I0(inf_abs0_2[4]),
.I1(reg2[4]),
.O(un1_inf_abs0_axb_4)
);
defparam \reg2_RNIKJHO[4] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIMKHO[5] (
.I0(inf_abs0_2[5]),
.I1(reg2[5]),
.O(un1_inf_abs0_axb_5)
);
defparam \reg2_RNIMKHO[5] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIOLHO[6] (
.I0(inf_abs0_2[6]),
.I1(reg2[6]),
.O(un1_inf_abs0_axb_6)
);
defparam \reg2_RNIOLHO[6] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIQMHO[7] (
.I0(inf_abs0_2[7]),
.I1(reg2[7]),
.O(un1_inf_abs0_axb_7)
);
defparam \reg2_RNIQMHO[7] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNISNHO[8] (
.I0(inf_abs0_2[8]),
.I1(reg2[8]),
.O(un1_inf_abs0_axb_8)
);
defparam \reg2_RNISNHO[8] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIUOHO[9] (
.I0(inf_abs0_2[9]),
.I1(reg2[9]),
.O(un1_inf_abs0_axb_9)
);
defparam \reg2_RNIUOHO[9] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIEK0A[10] (
.I0(inf_abs0_2[10]),
.I1(reg2[10]),
.O(un1_inf_abs0_axb_10)
);
defparam \reg2_RNIEK0A[10] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIGL0A[11] (
.I0(inf_abs0_2[11]),
.I1(reg2[11]),
.O(un1_inf_abs0_axb_11)
);
defparam \reg2_RNIGL0A[11] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIIM0A[12] (
.I0(inf_abs0_2[12]),
.I1(reg2[12]),
.O(un1_inf_abs0_axb_12)
);
defparam \reg2_RNIIM0A[12] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIKN0A[13] (
.I0(inf_abs0_2[13]),
.I1(reg2[13]),
.O(un1_inf_abs0_axb_13)
);
defparam \reg2_RNIKN0A[13] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIMO0A[14] (
.I0(inf_abs0_2[14]),
.I1(reg2[14]),
.O(un1_inf_abs0_axb_14)
);
defparam \reg2_RNIMO0A[14] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIOP0A[15] (
.I0(inf_abs0_2[15]),
.I1(reg2[15]),
.O(un1_inf_abs0_axb_15)
);
defparam \reg2_RNIOP0A[15] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIQQ0A[16] (
.I0(inf_abs0_2[16]),
.I1(reg2[16]),
.O(un1_inf_abs0_axb_16)
);
defparam \reg2_RNIQQ0A[16] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNISR0A[17] (
.I0(inf_abs0_2[17]),
.I1(reg2[17]),
.O(un1_inf_abs0_axb_17)
);
defparam \reg2_RNISR0A[17] .INIT=4'h6;
// @7:74
LUT2 \reg2_RNIUS0A[18] (
.I0(inf_abs0_2[18]),
.I1(reg2[18]),
.O(un1_inf_abs0_axb_18)
);
defparam \reg2_RNIUS0A[18] .INIT=4'h6;
// @7:74
LUT2 un1_inf_abs0_0_cry_0_RNO (
.I0(inf_abs0_2[0]),
.I1(reg1[0]),
.O(un1_inf_abs0_11[0])
);
defparam un1_inf_abs0_0_cry_0_RNO.INIT=4'h6;
// @7:74
LUT2 \reg1_RNIDDEN[1] (
.I0(inf_abs0_2[1]),
.I1(reg1[1]),
.O(un1_inf_abs0_0_axb_1)
);
defparam \reg1_RNIDDEN[1] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIFEEN[2] (
.I0(inf_abs0_2[2]),
.I1(reg1[2]),
.O(un1_inf_abs0_0_axb_2)
);
defparam \reg1_RNIFEEN[2] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIHFEN[3] (
.I0(inf_abs0_2[3]),
.I1(reg1[3]),
.O(un1_inf_abs0_0_axb_3)
);
defparam \reg1_RNIHFEN[3] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIJGEN[4] (
.I0(inf_abs0_2[4]),
.I1(reg1[4]),
.O(un1_inf_abs0_0_axb_4)
);
defparam \reg1_RNIJGEN[4] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNILHEN[5] (
.I0(inf_abs0_2[5]),
.I1(reg1[5]),
.O(un1_inf_abs0_0_axb_5)
);
defparam \reg1_RNILHEN[5] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNINIEN[6] (
.I0(inf_abs0_2[6]),
.I1(reg1[6]),
.O(un1_inf_abs0_0_axb_6)
);
defparam \reg1_RNINIEN[6] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIPJEN[7] (
.I0(inf_abs0_2[7]),
.I1(reg1[7]),
.O(un1_inf_abs0_0_axb_7)
);
defparam \reg1_RNIPJEN[7] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIRKEN[8] (
.I0(inf_abs0_2[8]),
.I1(reg1[8]),
.O(un1_inf_abs0_0_axb_8)
);
defparam \reg1_RNIRKEN[8] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNITLEN[9] (
.I0(inf_abs0_2[9]),
.I1(reg1[9]),
.O(un1_inf_abs0_0_axb_9)
);
defparam \reg1_RNITLEN[9] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIDGQL[10] (
.I0(inf_abs0_2[10]),
.I1(reg1[10]),
.O(un1_inf_abs0_0_axb_10)
);
defparam \reg1_RNIDGQL[10] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIFHQL[11] (
.I0(inf_abs0_2[11]),
.I1(reg1[11]),
.O(un1_inf_abs0_0_axb_11)
);
defparam \reg1_RNIFHQL[11] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIHIQL[12] (
.I0(inf_abs0_2[12]),
.I1(reg1[12]),
.O(un1_inf_abs0_0_axb_12)
);
defparam \reg1_RNIHIQL[12] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIJJQL[13] (
.I0(inf_abs0_2[13]),
.I1(reg1[13]),
.O(un1_inf_abs0_0_axb_13)
);
defparam \reg1_RNIJJQL[13] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNILKQL[14] (
.I0(inf_abs0_2[14]),
.I1(reg1[14]),
.O(un1_inf_abs0_0_axb_14)
);
defparam \reg1_RNILKQL[14] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNINLQL[15] (
.I0(inf_abs0_2[15]),
.I1(reg1[15]),
.O(un1_inf_abs0_0_axb_15)
);
defparam \reg1_RNINLQL[15] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIPMQL[16] (
.I0(inf_abs0_2[16]),
.I1(reg1[16]),
.O(un1_inf_abs0_0_axb_16)
);
defparam \reg1_RNIPMQL[16] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNIRNQL[17] (
.I0(inf_abs0_2[17]),
.I1(reg1[17]),
.O(un1_inf_abs0_0_axb_17)
);
defparam \reg1_RNIRNQL[17] .INIT=4'h6;
// @7:74
LUT2 \reg1_RNITOQL[18] (
.I0(inf_abs0_2[18]),
.I1(reg1[18]),
.O(un1_inf_abs0_0_axb_18)
);
defparam \reg1_RNITOQL[18] .INIT=4'h6;
// @7:95
LUT1 un3_reg3_axb_1_cZ (
.I0(reg3[4]),
.O(un3_reg3_axb_1)
);
defparam un3_reg3_axb_1_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_2_cZ (
.I0(reg3[5]),
.O(un3_reg3_axb_2)
);
defparam un3_reg3_axb_2_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_3_cZ (
.I0(reg3[6]),
.O(un3_reg3_axb_3)
);
defparam un3_reg3_axb_3_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_4_cZ (
.I0(reg3[7]),
.O(un3_reg3_axb_4)
);
defparam un3_reg3_axb_4_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_5_cZ (
.I0(reg3[8]),
.O(un3_reg3_axb_5)
);
defparam un3_reg3_axb_5_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_6_cZ (
.I0(reg3[9]),
.O(un3_reg3_axb_6)
);
defparam un3_reg3_axb_6_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_7_cZ (
.I0(reg3[10]),
.O(un3_reg3_axb_7)
);
defparam un3_reg3_axb_7_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_8_cZ (
.I0(reg3[11]),
.O(un3_reg3_axb_8)
);
defparam un3_reg3_axb_8_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_9_cZ (
.I0(reg3[12]),
.O(un3_reg3_axb_9)
);
defparam un3_reg3_axb_9_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_10_cZ (
.I0(reg3[13]),
.O(un3_reg3_axb_10)
);
defparam un3_reg3_axb_10_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_11_cZ (
.I0(reg3[14]),
.O(un3_reg3_axb_11)
);
defparam un3_reg3_axb_11_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_12_cZ (
.I0(reg3[15]),
.O(un3_reg3_axb_12)
);
defparam un3_reg3_axb_12_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_13_cZ (
.I0(reg3[16]),
.O(un3_reg3_axb_13)
);
defparam un3_reg3_axb_13_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_14_cZ (
.I0(reg3[17]),
.O(un3_reg3_axb_14)
);
defparam un3_reg3_axb_14_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_15_cZ (
.I0(reg3[18]),
.O(un3_reg3_axb_15)
);
defparam un3_reg3_axb_15_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_16_cZ (
.I0(reg3[19]),
.O(un3_reg3_axb_16)
);
defparam un3_reg3_axb_16_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_17_cZ (
.I0(reg3[20]),
.O(un3_reg3_axb_17)
);
defparam un3_reg3_axb_17_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_18_cZ (
.I0(reg3[21]),
.O(un3_reg3_axb_18)
);
defparam un3_reg3_axb_18_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_19_cZ (
.I0(reg3[22]),
.O(un3_reg3_axb_19)
);
defparam un3_reg3_axb_19_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_20_cZ (
.I0(reg3[23]),
.O(un3_reg3_axb_20)
);
defparam un3_reg3_axb_20_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_21_cZ (
.I0(reg3[24]),
.O(un3_reg3_axb_21)
);
defparam un3_reg3_axb_21_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_22_cZ (
.I0(reg3[25]),
.O(un3_reg3_axb_22)
);
defparam un3_reg3_axb_22_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_23_cZ (
.I0(reg3[26]),
.O(un3_reg3_axb_23)
);
defparam un3_reg3_axb_23_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_24_cZ (
.I0(reg3[27]),
.O(un3_reg3_axb_24)
);
defparam un3_reg3_axb_24_cZ.INIT=2'h2;
// @7:95
LUT1 un3_reg3_axb_25_cZ (
.I0(reg3[28]),
.O(un3_reg3_axb_25)
);
defparam un3_reg3_axb_25_cZ.INIT=2'h2;
// @7:466
LUT1 un3_t_s_1_RNIB3TC (
.I0(un3_t_s_1),
.O(N_4541_i)
);
defparam un3_t_s_1_RNIB3TC.INIT=2'h1;
// @7:466
LUT1 un3_t_s_2_RNIC3TC (
.I0(un3_t_s_2),
.O(N_4542_i)
);
defparam un3_t_s_2_RNIC3TC.INIT=2'h1;
// @7:466
LUT1 un3_t_s_3_RNID3TC (
.I0(un3_t_s_3),
.O(N_4543_i)
);
defparam un3_t_s_3_RNID3TC.INIT=2'h1;
// @7:466
LUT1 un3_t_s_4_RNIE3TC (
.I0(un3_t_s_4),
.O(N_4544_i)
);
defparam un3_t_s_4_RNIE3TC.INIT=2'h1;
// @7:466
LUT1 un3_t_s_5_RNIF3TC (
.I0(un3_t_s_5),
.O(N_4545_i)
);
defparam un3_t_s_5_RNIF3TC.INIT=2'h1;
// @7:466
LUT1 un3_t_s_6_RNIG3TC (
.I0(un3_t_s_6),
.O(N_4546_i)
);
defparam un3_t_s_6_RNIG3TC.INIT=2'h1;
// @7:466
LUT1 un3_t_s_7_RNIH3TC (
.I0(un3_t_s_7),
.O(N_4547_i)
);
defparam un3_t_s_7_RNIH3TC.INIT=2'h1;
// @7:466
LUT1 un3_t_s_8_RNII3TC (
.I0(un3_t_s_8),
.O(N_4548_i)
);
defparam un3_t_s_8_RNII3TC.INIT=2'h1;
// @7:466
LUT1 un3_t_s_9_RNIJ3TC (
.I0(un3_t_s_9),
.O(N_4549_i)
);
defparam un3_t_s_9_RNIJ3TC.INIT=2'h1;
// @7:466
LUT1 un3_t_s_10_RNIRF0A (
.I0(un3_t_s_10),
.O(N_4550_i)
);
defparam un3_t_s_10_RNIRF0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_11_RNISF0A (
.I0(un3_t_s_11),
.O(N_4551_i)
);
defparam un3_t_s_11_RNISF0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_12_RNITF0A (
.I0(un3_t_s_12),
.O(N_4552_i)
);
defparam un3_t_s_12_RNITF0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_13_RNIUF0A (
.I0(un3_t_s_13),
.O(N_4553_i)
);
defparam un3_t_s_13_RNIUF0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_14_RNIVF0A (
.I0(un3_t_s_14),
.O(N_4554_i)
);
defparam un3_t_s_14_RNIVF0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_15_RNI0G0A (
.I0(un3_t_s_15),
.O(N_4555_i)
);
defparam un3_t_s_15_RNI0G0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_16_RNI1G0A (
.I0(un3_t_s_16),
.O(N_4556_i)
);
defparam un3_t_s_16_RNI1G0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_17_RNI2G0A (
.I0(un3_t_s_17),
.O(N_4557_i)
);
defparam un3_t_s_17_RNI2G0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_18_RNI3G0A (
.I0(un3_t_s_18),
.O(N_4558_i)
);
defparam un3_t_s_18_RNI3G0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_19_RNI4G0A (
.I0(un3_t_s_19),
.O(N_4559_i)
);
defparam un3_t_s_19_RNI4G0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_20_RNISG0A (
.I0(un3_t_s_20),
.O(N_4560_i)
);
defparam un3_t_s_20_RNISG0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_21_RNITG0A (
.I0(un3_t_s_21),
.O(N_4561_i)
);
defparam un3_t_s_21_RNITG0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_22_RNIUG0A (
.I0(un3_t_s_22),
.O(N_4562_i)
);
defparam un3_t_s_22_RNIUG0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_23_RNIVG0A (
.I0(un3_t_s_23),
.O(N_4563_i)
);
defparam un3_t_s_23_RNIVG0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_24_RNI0H0A (
.I0(un3_t_s_24),
.O(N_4564_i)
);
defparam un3_t_s_24_RNI0H0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_25_RNI1H0A (
.I0(un3_t_s_25),
.O(N_4565_i)
);
defparam un3_t_s_25_RNI1H0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_26_RNI2H0A (
.I0(un3_t_s_26),
.O(N_4566_i)
);
defparam un3_t_s_26_RNI2H0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_27_RNI3H0A (
.I0(un3_t_s_27),
.O(N_4567_i)
);
defparam un3_t_s_27_RNI3H0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_28_RNI4H0A (
.I0(un3_t_s_28),
.O(N_4568_i)
);
defparam un3_t_s_28_RNI4H0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_29_RNI5H0A (
.I0(un3_t_s_29),
.O(N_4569_i)
);
defparam un3_t_s_29_RNI5H0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_30_RNITH0A (
.I0(un3_t_s_30),
.O(N_4570_i)
);
defparam un3_t_s_30_RNITH0A.INIT=2'h1;
// @7:466
LUT1 un3_t_s_31_RNIUH0A (
.I0(un3_t_s_31),
.O(N_4571_i)
);
defparam un3_t_s_31_RNIUH0A.INIT=2'h1;
// @7:83
LUT2 inf_abs0_2_axb_29_cZ (
.I0(ir[29]),
.I1(ir[31]),
.O(inf_abs0_2_axb_29)
);
defparam inf_abs0_2_axb_29_cZ.INIT=4'h6;
// @7:151
LUT4 un26_r_df30_cZ (
.I0(m_2[30]),
.I1(m_2_i[31]),
.I2(r_4_i[31]),
.I3(r_6[30]),
.O(un26_r_df30)
);
defparam un26_r_df30_cZ.INIT=16'h8241;
// @7:128
LUT4 \d_cnst_sn.un14_r_0_I_88 (
.I0(m_2[30]),
.I1(m_2[31]),
.I2(r_4[30]),
.I3(r_4[31]),
.O(un14_r_0_N_2)
);
defparam \d_cnst_sn.un14_r_0_I_88 .INIT=16'h8421;
// @7:47
FDC b_Z (
.Q(b),
.D(b_0),
.C(clock),
.CLR(reset)
);
// @7:47
FDCE \d_Z[0] (
.Q(d[0]),
.D(d_cnst[0]),
.C(clock),
.CLR(reset),
.CE(dce[0])
);
// @7:47
FDCE \d_Z[1] (
.Q(d[1]),
.D(d_cnst_sm0),
.C(clock),
.CLR(reset),
.CE(dce[0])
);
// @7:47
FDC \ir_Z[22] (
.Q(ir[22]),
.D(ir_3[22]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[23] (
.Q(ir[23]),
.D(ir_3[23]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[24] (
.Q(ir[24]),
.D(ir_3[24]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[25] (
.Q(ir[25]),
.D(ir_3[25]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[26] (
.Q(ir[26]),
.D(ir_3[26]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[27] (
.Q(ir[27]),
.D(ir_3[27]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[28] (
.Q(ir[28]),
.D(ir_3[28]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[29] (
.Q(ir[29]),
.D(ir_3[29]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[30] (
.Q(ir[30]),
.D(ir_3[30]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[31] (
.Q(ir[31]),
.D(ir_3[31]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[7] (
.Q(ir[7]),
.D(ir_3[7]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[8] (
.Q(ir[8]),
.D(ir_3[8]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[9] (
.Q(ir[9]),
.D(ir_3[9]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[10] (
.Q(ir[10]),
.D(ir_3[10]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[11] (
.Q(ir[11]),
.D(ir_3[11]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[12] (
.Q(ir[12]),
.D(ir_3[12]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[13] (
.Q(ir[13]),
.D(ir_3[13]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[14] (
.Q(ir[14]),
.D(ir_3[14]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[15] (
.Q(ir[15]),
.D(ir_3[15]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[16] (
.Q(ir[16]),
.D(ir_3[16]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[17] (
.Q(ir[17]),
.D(ir_3[17]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[18] (
.Q(ir[18]),
.D(ir_3[18]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[19] (
.Q(ir[19]),
.D(ir_3[19]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[20] (
.Q(ir[20]),
.D(ir_3[20]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[21] (
.Q(ir[21]),
.D(ir_3[21]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[0] (
.Q(ir[0]),
.D(ir_3[0]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[1] (
.Q(ir[1]),
.D(ir_3[1]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[2] (
.Q(ir[2]),
.D(ir_3[2]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[3] (
.Q(ir[3]),
.D(ir_3[3]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[4] (
.Q(ir[4]),
.D(ir_3[4]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[5] (
.Q(ir[5]),
.D(ir_3[5]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_Z[6] (
.Q(ir[6]),
.D(ir_3[6]),
.C(clock),
.CLR(reset)
);
// @7:47
FDCE \reg0_Z[31] (
.Q(reg0[31]),
.D(N_3856_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[16] (
.Q(reg0[16]),
.D(reg0_28[16]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[17] (
.Q(reg0[17]),
.D(reg0_28[17]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[18] (
.Q(reg0[18]),
.D(reg0_28[18]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[19] (
.Q(reg0[19]),
.D(N_3829_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[20] (
.Q(reg0[20]),
.D(N_3803_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[21] (
.Q(reg0[21]),
.D(N_3777_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[22] (
.Q(reg0[22]),
.D(N_3751_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[23] (
.Q(reg0[23]),
.D(N_3725_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[24] (
.Q(reg0[24]),
.D(N_3699_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[25] (
.Q(reg0[25]),
.D(N_3673_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[26] (
.Q(reg0[26]),
.D(N_3341_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[27] (
.Q(reg0[27]),
.D(N_3315_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[28] (
.Q(reg0[28]),
.D(N_3289_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[29] (
.Q(reg0[29]),
.D(N_3569_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[30] (
.Q(reg0[30]),
.D(N_3550_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[1] (
.Q(reg0[1]),
.D(reg0_28[1]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[2] (
.Q(reg0[2]),
.D(reg0_28[2]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[3] (
.Q(reg0[3]),
.D(reg0_28[3]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[4] (
.Q(reg0[4]),
.D(reg0_28[4]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[5] (
.Q(reg0[5]),
.D(reg0_28[5]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[6] (
.Q(reg0[6]),
.D(reg0_28[6]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[7] (
.Q(reg0[7]),
.D(reg0_28_7_rep1),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[8] (
.Q(reg0[8]),
.D(reg0_28[8]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[9] (
.Q(reg0[9]),
.D(reg0_28[9]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[10] (
.Q(reg0[10]),
.D(reg0_28[10]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[11] (
.Q(reg0[11]),
.D(reg0_28[11]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[12] (
.Q(reg0[12]),
.D(reg0_28[12]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[13] (
.Q(reg0[13]),
.D(reg0_28[13]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[14] (
.Q(reg0[14]),
.D(reg0_28[14]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg0_Z[15] (
.Q(reg0[15]),
.D(reg0_28[15]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg1_Z[18] (
.Q(reg1[18]),
.D(reg1_16[18]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[19] (
.Q(reg1[19]),
.D(reg0_28_3_2492),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[20] (
.Q(reg1[20]),
.D(reg0_28_4_2459),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[21] (
.Q(reg1[21]),
.D(reg0_28_5_2426),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[22] (
.Q(reg1[22]),
.D(reg0_28_6_2393),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[23] (
.Q(reg1[23]),
.D(reg0_28_7_2360),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[24] (
.Q(reg1[24]),
.D(reg0_28_8_2327),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[25] (
.Q(reg1[25]),
.D(N_3673),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[26] (
.Q(reg1[26]),
.D(reg1_16_7_1870),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[27] (
.Q(reg1[27]),
.D(reg1_16_8_1837),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[28] (
.Q(reg1[28]),
.D(reg1_16_9),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[29] (
.Q(reg1[29]),
.D(reg0_28_10_2261_a6_3_2_lut6_2_RNIOK9O5),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[30] (
.Q(reg1[30]),
.D(N_3550),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[31] (
.Q(reg1[31]),
.D(N_3856),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg0_Z[0] (
.Q(reg0[0]),
.D(reg0_28[0]),
.C(clock),
.CLR(reset),
.CE(un1_state_4_i)
);
// @7:47
FDCE \reg1_Z[3] (
.Q(reg1[3]),
.D(reg1_16[3]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[4] (
.Q(reg1[4]),
.D(reg1_16[4]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[5] (
.Q(reg1[5]),
.D(reg1_16[5]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[6] (
.Q(reg1[6]),
.D(reg1_16[6]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[7] (
.Q(reg1[7]),
.D(reg0_28[7]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[8] (
.Q(reg1[8]),
.D(reg1_16[8]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[9] (
.Q(reg1[9]),
.D(reg1_16[9]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[10] (
.Q(reg1[10]),
.D(reg1_16[10]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[11] (
.Q(reg1[11]),
.D(reg1_16[11]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[12] (
.Q(reg1[12]),
.D(reg1_16[12]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[13] (
.Q(reg1[13]),
.D(reg1_16[13]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[14] (
.Q(reg1[14]),
.D(reg1_16[14]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[15] (
.Q(reg1[15]),
.D(reg1_16[15]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[16] (
.Q(reg1[16]),
.D(reg1_16[16]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[17] (
.Q(reg1[17]),
.D(reg1_16[17]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg2_Z[20] (
.Q(reg2[20]),
.D(reg2_16[20]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[21] (
.Q(reg2[21]),
.D(reg2_16[21]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[22] (
.Q(reg2[22]),
.D(reg2_16[22]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[23] (
.Q(reg2[23]),
.D(reg2_16[23]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[24] (
.Q(reg2[24]),
.D(reg2_16[24]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[25] (
.Q(reg2[25]),
.D(reg2_16[25]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[26] (
.Q(reg2[26]),
.D(reg2_16[26]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[27] (
.Q(reg2[27]),
.D(reg2_16[27]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[28] (
.Q(reg2[28]),
.D(reg2_16[28]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[29] (
.Q(reg2[29]),
.D(reg2_16[29]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[30] (
.Q(reg2[30]),
.D(reg2_16[30]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[31] (
.Q(reg2[31]),
.D(reg2_16[31]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg1_Z[0] (
.Q(reg1[0]),
.D(reg1_16[0]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[1] (
.Q(reg1[1]),
.D(reg1_16[1]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg1_Z[2] (
.Q(reg1[2]),
.D(reg1_16[2]),
.C(clock),
.CLR(reset),
.CE(un1_state_3_i)
);
// @7:47
FDCE \reg2_Z[5] (
.Q(reg2[5]),
.D(reg2_16[5]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[6] (
.Q(reg2[6]),
.D(reg2_16[6]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[7] (
.Q(reg2[7]),
.D(reg2_16[7]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[8] (
.Q(reg2[8]),
.D(reg2_16[8]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[9] (
.Q(reg2[9]),
.D(reg2_16[9]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[10] (
.Q(reg2[10]),
.D(reg2_16[10]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[11] (
.Q(reg2[11]),
.D(reg2_16[11]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[12] (
.Q(reg2[12]),
.D(reg2_16[12]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[13] (
.Q(reg2[13]),
.D(reg2_16[13]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[14] (
.Q(reg2[14]),
.D(reg2_16[14]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[15] (
.Q(reg2[15]),
.D(reg2_16[15]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[16] (
.Q(reg2[16]),
.D(reg2_16[16]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[17] (
.Q(reg2[17]),
.D(reg2_16[17]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[18] (
.Q(reg2[18]),
.D(reg2_16[18]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[19] (
.Q(reg2[19]),
.D(reg2_16[19]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \datao_Z[22] (
.Q(datao[22]),
.D(r_4_3_1690_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[23] (
.Q(datao[23]),
.D(r_4_3_0_1664_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[24] (
.Q(datao[24]),
.D(r_4_3_1_1638_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[25] (
.Q(datao[25]),
.D(r_4_3_2_1612_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[26] (
.Q(datao[26]),
.D(r_4_3_3_1586_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[27] (
.Q(datao[27]),
.D(r_4_3_4_1560_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[28] (
.Q(datao[28]),
.D(r_4_3_5_1534_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[29] (
.Q(datao[29]),
.D(r_4_3_6_1508_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[30] (
.Q(datao[30]),
.D(r_4_3_lut6_2_O5[30]),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[31] (
.Q(datao[31]),
.D(r_4_3_8_1467),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \reg2_Z[0] (
.Q(reg2[0]),
.D(reg2_16[0]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[1] (
.Q(reg2[1]),
.D(reg2_16[1]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[2] (
.Q(reg2[2]),
.D(reg2_16[2]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[3] (
.Q(reg2[3]),
.D(reg2_16[3]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \reg2_Z[4] (
.Q(reg2[4]),
.D(reg2_16[4]),
.C(clock),
.CLR(reset),
.CE(un1_state_1_0_i)
);
// @7:47
FDCE \datao_Z[7] (
.Q(datao[7]),
.D(r_4_3_9_1442_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[8] (
.Q(datao[8]),
.D(r_4_3_10_1416_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[9] (
.Q(datao[9]),
.D(r_4_3_11_1390_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[10] (
.Q(datao[10]),
.D(r_4_3_12_1364_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[11] (
.Q(datao[11]),
.D(r_4_3_13_1338_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[12] (
.Q(datao[12]),
.D(r_4_3_14_1312_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[13] (
.Q(datao[13]),
.D(r_4_3_15_1286_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[14] (
.Q(datao[14]),
.D(r_4_3_16_1260_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[15] (
.Q(datao[15]),
.D(r_4_3_17_1234_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[16] (
.Q(datao[16]),
.D(r_4_3_18_1208_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[17] (
.Q(datao[17]),
.D(r_4_3_19_1182_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[18] (
.Q(datao[18]),
.D(r_4_3_20_1156_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[19] (
.Q(datao[19]),
.D(N_2724),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[20] (
.Q(datao[20]),
.D(r_4_3_22_1104_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[21] (
.Q(datao[21]),
.D(r_4_3_23_1078_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \addr_Z[12] (
.Q(addr[12]),
.D(N_2656_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[13] (
.Q(addr[13]),
.D(N_2636_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[14] (
.Q(addr[14]),
.D(N_2616_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[15] (
.Q(addr[15]),
.D(N_2596_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[16] (
.Q(addr[16]),
.D(N_2576_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[17] (
.Q(addr[17]),
.D(N_2556_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[18] (
.Q(addr[18]),
.D(N_2536_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[19] (
.Q(addr[19]),
.D(N_2516_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \datao_Z[0] (
.Q(datao[0]),
.D(r_4_3_24_836_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[1] (
.Q(datao[1]),
.D(r_4_3_25_810_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[2] (
.Q(datao[2]),
.D(N_36_i),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[3] (
.Q(datao[3]),
.D(r_4_3_27_758_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[4] (
.Q(datao[4]),
.D(r_4_3_28_732_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[5] (
.Q(datao[5]),
.D(r_4_3_29_706_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \datao_Z[6] (
.Q(datao[6]),
.D(r_4_3_30_680_i_m2),
.C(clock),
.CLR(reset),
.CE(addr_4_sqmuxa_1)
);
// @7:47
FDCE \reg3_Z[26] (
.Q(reg3[26]),
.D(reg3_17[26]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[27] (
.Q(reg3[27]),
.D(reg3_17[27]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[28] (
.Q(reg3[28]),
.D(reg3_17[28]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \addr_Z[0] (
.Q(addr[0]),
.D(N_2335_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[1] (
.Q(addr[1]),
.D(N_2315_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[2] (
.Q(addr[2]),
.D(N_47_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[3] (
.Q(addr[3]),
.D(N_2267_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[4] (
.Q(addr[4]),
.D(N_56_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[5] (
.Q(addr[5]),
.D(N_2219_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[6] (
.Q(addr[6]),
.D(N_2199_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[7] (
.Q(addr[7]),
.D(N_2179_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[8] (
.Q(addr[8]),
.D(N_2159_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[9] (
.Q(addr[9]),
.D(N_2139_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[10] (
.Q(addr[10]),
.D(N_2119_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \addr_Z[11] (
.Q(addr[11]),
.D(N_2099_i),
.C(clock),
.CLR(reset),
.CE(addr_0_sqmuxa_1_i)
);
// @7:47
FDCE \reg3_Z[11] (
.Q(reg3[11]),
.D(reg3_17[11]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[12] (
.Q(reg3[12]),
.D(reg3_17[12]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[13] (
.Q(reg3[13]),
.D(reg3_17[13]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[14] (
.Q(reg3[14]),
.D(reg3_17[14]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[15] (
.Q(reg3[15]),
.D(reg3_17[15]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[16] (
.Q(reg3[16]),
.D(reg3_17[16]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[17] (
.Q(reg3[17]),
.D(reg3_17[17]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[18] (
.Q(reg3[18]),
.D(reg3_17[18]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[19] (
.Q(reg3[19]),
.D(reg3_17[19]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[20] (
.Q(reg3[20]),
.D(reg3_17[20]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[21] (
.Q(reg3[21]),
.D(reg3_17[21]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[22] (
.Q(reg3[22]),
.D(reg3_17[22]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[23] (
.Q(reg3[23]),
.D(reg3_17[23]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[24] (
.Q(reg3[24]),
.D(reg3_17[24]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[25] (
.Q(reg3[25]),
.D(reg3_17[25]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[0] (
.Q(reg3[0]),
.D(reg3_17[0]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[1] (
.Q(reg3[1]),
.D(reg3_17[1]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[2] (
.Q(reg3[2]),
.D(reg3_17[2]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[3] (
.Q(reg3[3]),
.D(\d_cnst_sn.reg3_N_7_i ),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[4] (
.Q(reg3[4]),
.D(reg3_17[4]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[5] (
.Q(reg3[5]),
.D(reg3_17[5]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[6] (
.Q(reg3[6]),
.D(reg3_17[6]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[7] (
.Q(reg3[7]),
.D(reg3_17[7]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[8] (
.Q(reg3[8]),
.D(reg3_17[8]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[9] (
.Q(reg3[9]),
.D(reg3_17[9]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDCE \reg3_Z[10] (
.Q(reg3[10]),
.D(reg3_17[10]),
.C(clock),
.CLR(reset),
.CE(state[0])
);
// @7:47
FDC rd_Z (
.Q(rd),
.D(rd_18),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \state_Z[0] (
.Q(state[0]),
.D(state_i[0]),
.C(clock),
.CLR(reset)
);
// @7:47
FDC wr_Z (
.Q(wr),
.D(addr_4_sqmuxa_1),
.C(clock),
.CLR(reset)
);
// @7:47
FDC \ir_fast_Z[31] (
.Q(ir_fast[31]),
.D(ir_3_fast[31]),
.C(clock),
.CLR(reset)
);
// @7:83
MUXCY_L inf_abs0_2_cry_29_outext (
.DI(GND),
.CI(inf_abs0_2_cry_29_0),
.S(inf_abs0_2_cry_29_1),
.LO(inf_abs0_2_cry_29)
);
// @7:95
MUXCY un3_reg3_cry_25_outext (
.DI(GND),
.CI(un3_reg3_cry_25_0),
.S(un3_reg3_cry_25_1),
.O(un3_reg3_cry_25)
);
// @7:83
MUXCY inf_abs0_2_cry_30_outext (
.DI(GND),
.CI(inf_abs0_2_0[31]),
.S(inf_abs0_2_1[31]),
.O(inf_abs0_2[31])
);
// @7:128
MUXCY un14_r_0_I_83_cZ (
.DI(GND),
.CI(un14_r_0_data_tmp[9]),
.S(un14_r_0_N_2),
.O(un14_r_0_I_83)
);
// @7:118
MUXCY \un11_r_cry_cZ[30] (
.DI(un11_r_lt30),
.CI(un11_r_cry[28]),
.S(un11_r_df30),
.O(un11_r_cry[30])
);
// @7:143
MUXCY \b18_cry[30] (
.DI(b18_lt30),
.CI(b18_cry[28]),
.S(b18_df30),
.O(b18)
);
// @7:151
MUXCY \un26_r_cry_cZ[30] (
.DI(un26_r_lt30),
.CI(un26_r_cry[28]),
.S(un26_r_df30),
.O(un26_r_cry[30])
);
// @7:83
MUXCY inf_abs0_2_cry_29_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_28),
.S(inf_abs0_2_axb_29),
.O(inf_abs0_2_cry_29_0)
);
// @7:246
LUT5 \d_cnst_sn.un87_df (
.I0(d[0]),
.I1(d[1]),
.I2(d_cnst_ss0_x),
.I3(un1_df_1),
.I4(d_cnst_sm0),
.O(un87_df)
);
defparam \d_cnst_sn.un87_df .INIT=32'h88F08800;
// @7:47
LUT4_L \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_RNIOK9O5 (
.I0(\d_cnst_sn.g0_0_2 ),
.I1(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I2(t_1[29]),
.I3(\d_cnst_sn.g0_rn_1 ),
.LO(reg0_28_10_2261_a6_3_2_lut6_2_RNIOK9O5)
);
defparam \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_RNIOK9O5 .INIT=16'hFF02;
// @7:103
LUT6 \d_cnst_sn.un1_cf_x_RNI07TU1 (
.I0(inf_abs0_2[23]),
.I1(un36_df),
.I2(N_1890),
.I3(m7),
.I4(un1_cf_x),
.I5(un87_df),
.O(\d_cnst_sn.reg3_17_sn_m7_0 )
);
defparam \d_cnst_sn.un1_cf_x_RNI07TU1 .INIT=64'h0000FFFEFFFEFFFE;
// @7:103
LUT4 \d_cnst_sn.un1_cf_x (
.I0(inf_abs0_2[23]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(\d_cnst_sn.reg3_5_sqmuxa_2_1 ),
.O(un1_cf_x)
);
defparam \d_cnst_sn.un1_cf_x .INIT=16'h0400;
// @7:213
LUT3 \d_cnst_sn.d_cnst_ss0_x (
.I0(inf_abs0_2[24]),
.I1(inf_abs0_2[25]),
.I2(inf_abs0_2[26]),
.O(d_cnst_ss0_x)
);
defparam \d_cnst_sn.d_cnst_ss0_x .INIT=8'hBA;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNI0TVT3[7] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg0_1 [7]),
.I4(t_1[7]),
.I5(N_1042),
.LO(reg0_28_7_rep1)
);
defparam \d_cnst_sn.reg0_28_6_RNI0TVT3[7] .INIT=64'h0F00FF0001001100;
// @7:358
LUT6 \d_cnst_sn.m_2_i[0] (
.I0(datai[0]),
.I1(inf_abs0_2_axb_30),
.I2(inf_abs0_2[0]),
.I3(inf_abs0_2_cry_29),
.I4(inf_abs0_2[27]),
.I5(inf_abs0_2[28]),
.O(m_2_i[0])
);
defparam \d_cnst_sn.m_2_i[0] .INIT=64'h1D551D551D550F0F;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_RNIC3O74 (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.g0_1 ),
.I3(un32_reg0_s_29),
.I4(un11_reg0_s_29),
.LO(\d_cnst_sn.g0_rn_1 )
);
defparam \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_RNIC3O74 .INIT=32'hFAF8F2F0;
// @7:213
LUT6 \d_cnst_sn.un1_df_1 (
.I0(b),
.I1(inf_abs0_2_axb_30),
.I2(inf_abs0_2_cry_29),
.I3(inf_abs0_2[24]),
.I4(inf_abs0_2[25]),
.I5(inf_abs0_2[26]),
.O(un1_df_1)
);
defparam \d_cnst_sn.un1_df_1 .INIT=64'h2A3F2A1500000000;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_RNIQARE5 (
.I0(\d_cnst_sn.g0_0_2 ),
.I1(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I2(\d_cnst_sn.g0_1 ),
.I3(t_1[29]),
.I4(\d_cnst_sn.g3 ),
.LO(N_3569_rep1)
);
defparam \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_RNIQARE5 .INIT=32'hFCFEF0F2;
// @7:47
LUT6_L \d_cnst_sn.reg0_28_3_2492_rep1 (
.I0(\d_cnst_sn.reg0_28_2526_a5_1_0 ),
.I1(\d_cnst_sn.reg1_16_8_1837_2_tz ),
.I2(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I3(\d_cnst_sn.reg0_28_0 [19]),
.I4(t_1[19]),
.I5(\d_cnst_sn.reg0_28_3_2492_1 ),
.LO(N_3829_rep1)
);
defparam \d_cnst_sn.reg0_28_3_2492_rep1 .INIT=64'hFFFFFFFF0E00EE00;
// @7:47
LUT6_L \d_cnst_sn.reg0_28_4_2459_rep1 (
.I0(\d_cnst_sn.reg0_28_2526_a5_1_0 ),
.I1(\d_cnst_sn.reg1_16_8_1837_2_tz ),
.I2(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I3(\d_cnst_sn.reg0_28_0 [20]),
.I4(t_1[20]),
.I5(\d_cnst_sn.reg0_28_4_2459_0 ),
.LO(N_3803_rep1)
);
defparam \d_cnst_sn.reg0_28_4_2459_rep1 .INIT=64'hFFFFFFFF0E00EE00;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_5_2426_rep1 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_5_2426_3_1 ),
.I2(\d_cnst_sn.reg0_28_5_2426_a6_1_1 ),
.I3(t_1[21]),
.I4(\d_cnst_sn.reg0_28_5_2426_0 ),
.LO(N_3777_rep1)
);
defparam \d_cnst_sn.reg0_28_5_2426_rep1 .INIT=32'hFFFF54FC;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_6_2393_rep1 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_6_2393_3_1 ),
.I2(\d_cnst_sn.reg0_28_6_2393_a6_1_1 ),
.I3(t_1[22]),
.I4(\d_cnst_sn.reg0_28_6_2393_0 ),
.LO(N_3751_rep1)
);
defparam \d_cnst_sn.reg0_28_6_2393_rep1 .INIT=32'hFFFF54FC;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_7_2360_rep1 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_7_2360_3_1 ),
.I2(\d_cnst_sn.reg0_28_7_2360_a6_1_1 ),
.I3(t_1[23]),
.I4(\d_cnst_sn.reg0_28_7_2360_0 ),
.LO(N_3725_rep1)
);
defparam \d_cnst_sn.reg0_28_7_2360_rep1 .INIT=32'hFFFF54FC;
// @7:47
LUT6_L \d_cnst_sn.reg0_28_8_2327_rep1 (
.I0(\d_cnst_sn.reg1_16_8_1837_2_tz ),
.I1(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I2(reg0_28_7_d[24]),
.I3(\d_cnst_sn.reg0_28_8_2327_a6_1_1 ),
.I4(t_1[24]),
.I5(\d_cnst_sn.reg0_28_8_2327_0 ),
.LO(N_3699_rep1)
);
defparam \d_cnst_sn.reg0_28_8_2327_rep1 .INIT=64'hFFFFFFFF3320FFA8;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_9_2294_rep1 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_9_2294_3_1 ),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_1_1 ),
.I3(t_1[25]),
.I4(\d_cnst_sn.reg0_28_9_2294_0 ),
.LO(N_3673_rep1)
);
defparam \d_cnst_sn.reg0_28_9_2294_rep1 .INIT=32'hFFFF54FC;
// @7:47
LUT5_L \d_cnst_sn.reg1_16_7_1870_rep1 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_10_2261_a6_1_1 ),
.I2(\d_cnst_sn.reg1_16_7_1870_3_1 ),
.I3(t_1[26]),
.I4(\d_cnst_sn.reg1_16_7_1870_0 ),
.LO(N_3341_rep1)
);
defparam \d_cnst_sn.reg1_16_7_1870_rep1 .INIT=32'hFFFF54FC;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_14_rep1 (
.I0(inf_abs0_2[31]),
.I1(\d_cnst_sn.reg0_28_14_2135_1_a0_2 ),
.I2(reg3_1_1[30]),
.I3(\d_cnst_sn.reg0_28_14_0 ),
.I4(t_1[30]),
.LO(N_3550_rep1)
);
defparam \d_cnst_sn.reg0_28_14_rep1 .INIT=32'hFFA0FFEC;
// @7:47
LUT5_L \d_cnst_sn.reg1_16_8_1837_rep1 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_11_2228_a6_1_1 ),
.I2(\d_cnst_sn.reg1_16_8_1837_3_1 ),
.I3(t_1[27]),
.I4(\d_cnst_sn.reg1_16_8_1837_0 ),
.LO(N_3315_rep1)
);
defparam \d_cnst_sn.reg1_16_8_1837_rep1 .INIT=32'hFFFF54FC;
// @7:47
LUT6_L \d_cnst_sn.reg1_16_9_rep1 (
.I0(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I1(m_2[28]),
.I2(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I3(\d_cnst_sn.reg1_16_9_1804_3_tz ),
.I4(t_1[28]),
.I5(N_3614),
.LO(N_3289_rep1)
);
defparam \d_cnst_sn.reg1_16_9_rep1 .INIT=64'hFFFFFFFF8F88FF88;
// @7:47
LUT6_L \d_cnst_sn.reg0_28_a1_1_lut6_2_RNIDLFQ4_0[7] (
.I0(b),
.I1(inf_abs0_2[27]),
.I2(\d_cnst_sn.g0_3_a2_2 ),
.I3(\d_cnst_sn.g0_3_1 ),
.I4(t_1[31]),
.I5(t_1[30]),
.LO(N_3856_rep1)
);
defparam \d_cnst_sn.reg0_28_a1_1_lut6_2_RNIDLFQ4_0[7] .INIT=64'hFF00FF30FF40FF70;
// @7:74
LUT6 \d_cnst_sn.g0_0_0_a5_0 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(\d_cnst_sn.g0_0_0_a5_0_0 ),
.O(N_7_0)
);
defparam \d_cnst_sn.g0_0_0_a5_0 .INIT=64'h0101010000000000;
LUT6 \d_cnst_sn.reg0_28_a2_0_lut6_2_RNI9RAM3[2] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[31]),
.I3(N_7_0),
.I4(\d_cnst_sn.reg1_16_a2_0 [5]),
.I5(reg3_1_1[31]),
.O(\d_cnst_sn.g0_0_0_1 )
);
defparam \d_cnst_sn.reg0_28_a2_0_lut6_2_RNI9RAM3[2] .INIT=64'hFFF1FF00FF00FF00;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_10_2261_a6_1_0_lut6_2_RNI3B3R4 (
.I0(b),
.I1(inf_abs0_2[27]),
.I2(\d_cnst_sn.g0_0_0_a5_2 ),
.I3(\d_cnst_sn.g0_0_0_1 ),
.I4(t_1[31]),
.I5(t_1[30]),
.LO(reg2_16[31])
);
defparam \d_cnst_sn.reg0_28_10_2261_a6_1_0_lut6_2_RNI3B3R4 .INIT=64'hFF00FF30FF40FF70;
// @7:47
LUT3_L \d_cnst_sn.g3_cZ (
.I0(N_1033),
.I1(un32_reg0_s_29),
.I2(un11_reg0_s_29),
.LO(\d_cnst_sn.g3 )
);
defparam \d_cnst_sn.g3_cZ .INIT=8'hE4;
LUT5 \d_cnst_sn.g0_0_2_cZ (
.I0(b),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(\d_cnst_sn.g0_0_2 )
);
defparam \d_cnst_sn.g0_0_2_cZ .INIT=32'h0000040C;
LUT6 \d_cnst_sn.reg0_m9_i_a1_RNI2ROG2 (
.I0(\d_cnst_sn.reg0_N_13_0 ),
.I1(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I2(N_513_i),
.I3(m_2[29]),
.I4(reg0_m9_i_a1),
.I5(reg3_1_1[29]),
.O(\d_cnst_sn.g0_1 )
);
defparam \d_cnst_sn.reg0_m9_i_a1_RNI2ROG2 .INIT=64'hFFFFCD05FFFFCC00;
// @7:47
LUT6 \d_cnst_sn.g0_3_a2_0 (
.I0(datai[31]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.I5(N_7),
.O(N_12)
);
defparam \d_cnst_sn.g0_3_a2_0 .INIT=64'h0000000800000000;
LUT6 \d_cnst_sn.g0_3_1_cZ (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(N_12),
.I5(reg3_1_1[31]),
.O(\d_cnst_sn.g0_3_1 )
);
defparam \d_cnst_sn.g0_3_1_cZ .INIT=64'hFFFFFF01FFFF0000;
// @7:47
LUT6_L \d_cnst_sn.reg0_28_a1_1_lut6_2_RNIDLFQ4[7] (
.I0(b),
.I1(inf_abs0_2[27]),
.I2(\d_cnst_sn.g0_3_a2_2 ),
.I3(\d_cnst_sn.g0_3_1 ),
.I4(t_1[31]),
.I5(t_1[30]),
.LO(N_3856)
);
defparam \d_cnst_sn.reg0_28_a1_1_lut6_2_RNIDLFQ4[7] .INIT=64'hFF00FF30FF40FF70;
// @7:103
LUT4 \d_cnst_sn.reg3_17_0[28] (
.I0(datai[28]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_cf),
.O(N_1685)
);
defparam \d_cnst_sn.reg3_17_0[28] .INIT=16'hA8AA;
// @7:103
LUT4 \d_cnst_sn.reg3_17_0[27] (
.I0(datai[27]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_cf),
.O(N_1684)
);
defparam \d_cnst_sn.reg3_17_0[27] .INIT=16'hA8AA;
// @7:103
LUT4 \d_cnst_sn.reg3_17_0[26] (
.I0(datai[26]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_cf),
.O(N_1683)
);
defparam \d_cnst_sn.reg3_17_0[26] .INIT=16'hA8AA;
// @7:103
LUT4 \d_cnst_sn.reg3_17_0[25] (
.I0(datai[25]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_cf),
.O(N_1682)
);
defparam \d_cnst_sn.reg3_17_0[25] .INIT=16'hA8AA;
// @7:103
LUT4_L \d_cnst_sn.reg3_17_0[24] (
.I0(datai[24]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_cf),
.LO(N_1681)
);
defparam \d_cnst_sn.reg3_17_0[24] .INIT=16'hA8AA;
// @7:103
LUT4_L \d_cnst_sn.reg3_17_0[23] (
.I0(datai[23]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_cf),
.LO(N_1680)
);
defparam \d_cnst_sn.reg3_17_0[23] .INIT=16'hA8AA;
// @7:103
LUT4_L \d_cnst_sn.reg3_17_0[22] (
.I0(datai[22]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_cf),
.LO(N_1679)
);
defparam \d_cnst_sn.reg3_17_0[22] .INIT=16'hA8AA;
// @7:103
LUT4 \d_cnst_sn.reg3_17_0[20] (
.I0(datai[20]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_cf),
.O(N_1677)
);
defparam \d_cnst_sn.reg3_17_0[20] .INIT=16'hA8AA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[7] (
.I0(datai[7]),
.I1(inf_abs0_2[7]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1664)
);
defparam \d_cnst_sn.reg3_17_0[7] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[6] (
.I0(datai[6]),
.I1(inf_abs0_2[6]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1663)
);
defparam \d_cnst_sn.reg3_17_0[6] .INIT=32'hAAACAAAA;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_0[2] (
.I0(datai[2]),
.I1(inf_abs0_2[2]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.LO(N_1659)
);
defparam \d_cnst_sn.reg3_17_0[2] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[9] (
.I0(datai[9]),
.I1(inf_abs0_2[9]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1666)
);
defparam \d_cnst_sn.reg3_17_0[9] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[11] (
.I0(datai[11]),
.I1(inf_abs0_2[11]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1668)
);
defparam \d_cnst_sn.reg3_17_0[11] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[10] (
.I0(datai[10]),
.I1(inf_abs0_2[10]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1667)
);
defparam \d_cnst_sn.reg3_17_0[10] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[17] (
.I0(datai[17]),
.I1(inf_abs0_2[17]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1674)
);
defparam \d_cnst_sn.reg3_17_0[17] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[12] (
.I0(datai[12]),
.I1(inf_abs0_2[12]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1669)
);
defparam \d_cnst_sn.reg3_17_0[12] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[18] (
.I0(datai[18]),
.I1(inf_abs0_2[18]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1675)
);
defparam \d_cnst_sn.reg3_17_0[18] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[14] (
.I0(datai[14]),
.I1(inf_abs0_2[14]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1671)
);
defparam \d_cnst_sn.reg3_17_0[14] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[19] (
.I0(datai[19]),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1676)
);
defparam \d_cnst_sn.reg3_17_0[19] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[13] (
.I0(datai[13]),
.I1(inf_abs0_2[13]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1670)
);
defparam \d_cnst_sn.reg3_17_0[13] .INIT=32'hAAACAAAA;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_0[1] (
.I0(datai[1]),
.I1(inf_abs0_2[1]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.LO(N_1658)
);
defparam \d_cnst_sn.reg3_17_0[1] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[16] (
.I0(datai[16]),
.I1(inf_abs0_2[16]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1673)
);
defparam \d_cnst_sn.reg3_17_0[16] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[15] (
.I0(datai[15]),
.I1(inf_abs0_2[15]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1672)
);
defparam \d_cnst_sn.reg3_17_0[15] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[8] (
.I0(datai[8]),
.I1(inf_abs0_2[8]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1665)
);
defparam \d_cnst_sn.reg3_17_0[8] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.un1_cf (
.I0(inf_abs0_2[23]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(\d_cnst_sn.reg3_5_sqmuxa_2_1 ),
.I4(un87_df),
.O(un1_cf)
);
defparam \d_cnst_sn.un1_cf .INIT=32'h04000000;
// @7:489
LUT5 \d_cnst_sn.rd_4_sqmuxa (
.I0(inf_abs0_2[23]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un36_df),
.I4(N_1890),
.O(rd_4_sqmuxa)
);
defparam \d_cnst_sn.rd_4_sqmuxa .INIT=32'h00000001;
// @7:103
LUT5 \d_cnst_sn.un1_df_16_2_RNISV2O2 (
.I0(inf_abs0_2[23]),
.I1(un1_b57),
.I2(un1_df_17_2),
.I3(un1_df_16),
.I4(\d_cnst_sn.reg3_17_sn_m7_0 ),
.O(N_1841)
);
defparam \d_cnst_sn.un1_df_16_2_RNISV2O2 .INIT=32'h00BF0000;
// @7:103
LUT4 \d_cnst_sn.un1_df_16 (
.I0(inf_abs0_2[23]),
.I1(un36_df),
.I2(un1_b59),
.I3(un87_df),
.O(un1_df_16)
);
defparam \d_cnst_sn.un1_df_16 .INIT=16'h1000;
// @7:103
LUT5 \d_cnst_sn.un1_b57_RNIEFGG1 (
.I0(inf_abs0_2[23]),
.I1(un1_b57),
.I2(un36_df),
.I3(un1_b59),
.I4(un87_df),
.O(N_1810)
);
defparam \d_cnst_sn.un1_b57_RNIEFGG1 .INIT=32'hFAFBFFFF;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_6_0_cZ[19] (
.I0(inf_abs0_2[28]),
.I1(inf_abs0_2[29]),
.I2(N_933),
.I3(N_965),
.I4(reg3_14_sqmuxa),
.LO(\d_cnst_sn.reg3_17_6_0 [19])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[19] .INIT=32'hFD75FFFF;
// @7:103
LUT3_L \d_cnst_sn.reg3_17_4_a2[13] (
.I0(inf_abs0_2[28]),
.I1(reg3_14_sqmuxa),
.I2(t_1[13]),
.LO(reg3_17_4_a2[13])
);
defparam \d_cnst_sn.reg3_17_4_a2[13] .INIT=8'h40;
// @7:103
LUT5 \d_cnst_sn.reg3_17_3[2] (
.I0(inf_abs0_2[2]),
.I1(inf_abs0_2[28]),
.I2(r_4[1]),
.I3(reg3_14_sqmuxa),
.I4(t_1[2]),
.O(N_1752)
);
defparam \d_cnst_sn.reg3_17_3[2] .INIT=32'hC0AAF3AA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_3[1] (
.I0(inf_abs0_2[1]),
.I1(inf_abs0_2[28]),
.I2(r_4[0]),
.I3(reg3_14_sqmuxa),
.I4(t_1[1]),
.O(N_1751)
);
defparam \d_cnst_sn.reg3_17_3[1] .INIT=32'hC0AAF3AA;
// @7:103
LUT4_L \d_cnst_sn.reg3_17_3[0] (
.I0(inf_abs0_2[0]),
.I1(inf_abs0_2[28]),
.I2(reg3_14_sqmuxa),
.I3(t_1[0]),
.LO(N_1750)
);
defparam \d_cnst_sn.reg3_17_3[0] .INIT=16'h0A3A;
// @7:103
LUT5 \d_cnst_sn.reg3_17_6_tz[24] (
.I0(inf_abs0_2[28]),
.I1(r_4[23]),
.I2(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I3(reg3_14_sqmuxa),
.I4(N_1681),
.O(\d_cnst_sn.reg3_17_0_tz [24])
);
defparam \d_cnst_sn.reg3_17_6_tz[24] .INIT=32'h8F0F8000;
// @7:103
LUT5 \d_cnst_sn.reg3_17_6_tz[22] (
.I0(inf_abs0_2[28]),
.I1(r_4[21]),
.I2(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I3(reg3_14_sqmuxa),
.I4(N_1679),
.O(\d_cnst_sn.reg3_17_0_tz [22])
);
defparam \d_cnst_sn.reg3_17_6_tz[22] .INIT=32'h8F0F8000;
// @7:103
LUT5 \d_cnst_sn.reg3_17_6_tz[23] (
.I0(inf_abs0_2[28]),
.I1(r_4[22]),
.I2(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I3(reg3_14_sqmuxa),
.I4(N_1680),
.O(\d_cnst_sn.reg3_17_0_tz [23])
);
defparam \d_cnst_sn.reg3_17_6_tz[23] .INIT=32'h8F0F8000;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_6_0_cZ[17] (
.I0(inf_abs0_2[17]),
.I1(inf_abs0_2[28]),
.I2(r_4[16]),
.I3(rd_4_sqmuxa),
.I4(reg3_14_sqmuxa),
.LO(\d_cnst_sn.reg3_17_6_0 [17])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[17] .INIT=32'hF3F3AAFF;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_6_0_cZ[16] (
.I0(inf_abs0_2[16]),
.I1(inf_abs0_2[28]),
.I2(r_4[15]),
.I3(rd_4_sqmuxa),
.I4(reg3_14_sqmuxa),
.LO(\d_cnst_sn.reg3_17_6_0 [16])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[16] .INIT=32'hF3F3AAFF;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_6_0_cZ[14] (
.I0(inf_abs0_2[14]),
.I1(inf_abs0_2[28]),
.I2(r_4[13]),
.I3(rd_4_sqmuxa),
.I4(reg3_14_sqmuxa),
.LO(\d_cnst_sn.reg3_17_6_0 [14])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[14] .INIT=32'hF3F3AAFF;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_6_0_cZ[15] (
.I0(inf_abs0_2[15]),
.I1(inf_abs0_2[28]),
.I2(r_4[14]),
.I3(rd_4_sqmuxa),
.I4(reg3_14_sqmuxa),
.LO(\d_cnst_sn.reg3_17_6_0 [15])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[15] .INIT=32'hF3F3AAFF;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_6_0_cZ[12] (
.I0(inf_abs0_2[12]),
.I1(inf_abs0_2[28]),
.I2(r_4[11]),
.I3(rd_4_sqmuxa),
.I4(reg3_14_sqmuxa),
.LO(\d_cnst_sn.reg3_17_6_0 [12])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[12] .INIT=32'hF3F3AAFF;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_6_0_cZ[13] (
.I0(inf_abs0_2[13]),
.I1(inf_abs0_2[28]),
.I2(r_4[12]),
.I3(rd_4_sqmuxa),
.I4(reg3_14_sqmuxa),
.LO(\d_cnst_sn.reg3_17_6_0 [13])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[13] .INIT=32'hF3F3AAFF;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_6_0_cZ[18] (
.I0(inf_abs0_2[18]),
.I1(inf_abs0_2[28]),
.I2(r_4[17]),
.I3(rd_4_sqmuxa),
.I4(reg3_14_sqmuxa),
.LO(\d_cnst_sn.reg3_17_6_0 [18])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[18] .INIT=32'hF3F3AAFF;
// @7:103
LUT2 \d_cnst_sn.reg3_17_a1_2[21] (
.I0(inf_abs0_2[28]),
.I1(reg3_14_sqmuxa),
.O(\d_cnst_sn.reg3_17_a1_2 [24])
);
defparam \d_cnst_sn.reg3_17_a1_2[21] .INIT=4'h4;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[4] (
.I0(datai[4]),
.I1(inf_abs0_2[4]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1661)
);
defparam \d_cnst_sn.reg3_17_0[4] .INIT=32'hAAACAAAA;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_0[3] (
.I0(datai[3]),
.I1(inf_abs0_2[3]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.LO(N_1660)
);
defparam \d_cnst_sn.reg3_17_0[3] .INIT=32'hAAACAAAA;
// @7:103
LUT5 \d_cnst_sn.reg3_17_0[5] (
.I0(datai[5]),
.I1(inf_abs0_2[5]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(un1_cf),
.O(N_1662)
);
defparam \d_cnst_sn.reg3_17_0[5] .INIT=32'hAAACAAAA;
// @7:47
LUT6 \d_cnst_sn.reg1_16_8_1837_3_1_cZ (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.I4(r_4[26]),
.I5(reg3_1_1[27]),
.O(\d_cnst_sn.reg1_16_8_1837_3_1 )
);
defparam \d_cnst_sn.reg1_16_8_1837_3_1_cZ .INIT=64'hF8F8F0F808080008;
// @7:47
LUT6 \d_cnst_sn.reg1_16_7_1870_3_1_cZ (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.I4(r_4[25]),
.I5(reg3_1_1[26]),
.O(\d_cnst_sn.reg1_16_7_1870_3_1 )
);
defparam \d_cnst_sn.reg1_16_7_1870_3_1_cZ .INIT=64'hF8F8F0F808080008;
// @7:47
LUT6 \d_cnst_sn.reg0_28_9_2294_3_1_cZ (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.I4(r_4[24]),
.I5(reg3_1_1[25]),
.O(\d_cnst_sn.reg0_28_9_2294_3_1 )
);
defparam \d_cnst_sn.reg0_28_9_2294_3_1_cZ .INIT=64'hF8F8F0F808080008;
// @7:47
LUT6 \d_cnst_sn.reg0_28_7_2360_3_1_cZ (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.I4(r_4[22]),
.I5(reg3_1_1[23]),
.O(\d_cnst_sn.reg0_28_7_2360_3_1 )
);
defparam \d_cnst_sn.reg0_28_7_2360_3_1_cZ .INIT=64'hF8F8F0F808080008;
// @7:47
LUT6 \d_cnst_sn.reg0_28_6_2393_3_1_cZ (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.I4(r_4[21]),
.I5(reg3_1_1[22]),
.O(\d_cnst_sn.reg0_28_6_2393_3_1 )
);
defparam \d_cnst_sn.reg0_28_6_2393_3_1_cZ .INIT=64'hF8F8F0F808080008;
// @7:47
LUT6 \d_cnst_sn.reg0_28_5_2426_3_1_cZ (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.I4(r_4[20]),
.I5(reg3_1_1[21]),
.O(\d_cnst_sn.reg0_28_5_2426_3_1 )
);
defparam \d_cnst_sn.reg0_28_5_2426_3_1_cZ .INIT=64'hF8F8F0F808080008;
LUT6 \d_cnst_sn.r_4_2_RNI0O8E1[18] (
.I0(reg0[18]),
.I1(reg2[18]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_965),
.O(r_4[18])
);
defparam \d_cnst_sn.r_4_2_RNI0O8E1[18] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNI0O8E1_0[18] (
.I0(reg0[18]),
.I1(reg2[18]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_965),
.O(un3_t_axb_18)
);
defparam \d_cnst_sn.r_4_2_RNI0O8E1_0[18] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIE8BE1_0[21] (
.I0(reg0[21]),
.I1(reg2[21]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_968),
.O(un3_t_axb_21)
);
defparam \d_cnst_sn.r_4_2_RNIE8BE1_0[21] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIE8BE1[21] (
.I0(reg0[21]),
.I1(reg2[21]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_968),
.O(r_4[21])
);
defparam \d_cnst_sn.r_4_2_RNIE8BE1[21] .INIT=64'hAFACAFAAA0ACA0AA;
// @7:358
LUT5 un32_reg0_axb_29_cZ (
.I0(datai[29]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[29]),
.O(un32_reg0_axb_29)
);
defparam un32_reg0_axb_29_cZ.INIT=32'h2220DDDF;
// @7:74
LUT6 \d_cnst_sn.reg2_16_6[30] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(m_2[30]),
.I5(reg3_1_1[30]),
.O(N_1493)
);
defparam \d_cnst_sn.reg2_16_6[30] .INIT=64'hFF0DFF01000C0000;
// @7:74
LUT6 \d_cnst_sn.reg2_16[28] (
.I0(un3_reg3_s_25),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[28]),
.I5(reg3_1_1[28]),
.O(N_1363)
);
defparam \d_cnst_sn.reg2_16[28] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16[27] (
.I0(un3_reg3_s_24),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[27]),
.I5(reg3_1_1[27]),
.O(N_1362)
);
defparam \d_cnst_sn.reg2_16[27] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16[26] (
.I0(un3_reg3_s_23),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[26]),
.I5(reg3_1_1[26]),
.O(N_1361)
);
defparam \d_cnst_sn.reg2_16[26] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[19] (
.I0(un3_reg3_s_16),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[19]),
.I5(reg3_1_1[19]),
.O(N_1354)
);
defparam \d_cnst_sn.reg2_16_2[19] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[18] (
.I0(un3_reg3_s_15),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[18]),
.I5(reg3_1_1[18]),
.O(N_1353)
);
defparam \d_cnst_sn.reg2_16_2[18] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[17] (
.I0(un3_reg3_s_14),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[17]),
.I5(reg3_1_1[17]),
.O(N_1352)
);
defparam \d_cnst_sn.reg2_16_2[17] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[16] (
.I0(un3_reg3_s_13),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[16]),
.I5(reg3_1_1[16]),
.O(N_1351)
);
defparam \d_cnst_sn.reg2_16_2[16] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[15] (
.I0(un3_reg3_s_12),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[15]),
.I5(reg3_1_1[15]),
.O(N_1350)
);
defparam \d_cnst_sn.reg2_16_2[15] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[14] (
.I0(un3_reg3_s_11),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[14]),
.I5(reg3_1_1[14]),
.O(N_1349)
);
defparam \d_cnst_sn.reg2_16_2[14] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[13] (
.I0(un3_reg3_s_10),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[13]),
.I5(reg3_1_1[13]),
.O(N_1348)
);
defparam \d_cnst_sn.reg2_16_2[13] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[12] (
.I0(un3_reg3_s_9),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[12]),
.I5(reg3_1_1[12]),
.O(N_1347)
);
defparam \d_cnst_sn.reg2_16_2[12] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[11] (
.I0(un3_reg3_s_8),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[11]),
.I5(reg3_1_1[11]),
.O(N_1346)
);
defparam \d_cnst_sn.reg2_16_2[11] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[10] (
.I0(un3_reg3_s_7),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[10]),
.I5(reg3_1_1[10]),
.O(N_1345)
);
defparam \d_cnst_sn.reg2_16_2[10] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[9] (
.I0(un3_reg3_s_6),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[9]),
.I5(reg3_1_1[9]),
.O(N_1344)
);
defparam \d_cnst_sn.reg2_16_2[9] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[8] (
.I0(un3_reg3_s_5),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[8]),
.I5(reg3_1_1[8]),
.O(N_1343)
);
defparam \d_cnst_sn.reg2_16_2[8] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[7] (
.I0(un3_reg3_s_4),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[7]),
.I5(reg3_1_1[7]),
.O(N_1342)
);
defparam \d_cnst_sn.reg2_16_2[7] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[6] (
.I0(un3_reg3_s_3),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[6]),
.I5(reg3_1_1[6]),
.O(N_1341)
);
defparam \d_cnst_sn.reg2_16_2[6] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[5] (
.I0(un3_reg3_s_2),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[5]),
.I5(reg3_1_1[5]),
.O(N_1340)
);
defparam \d_cnst_sn.reg2_16_2[5] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[4] (
.I0(un3_reg3_s_1),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[4]),
.I5(reg3_1_1[4]),
.O(N_1339)
);
defparam \d_cnst_sn.reg2_16_2[4] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[3] (
.I0(reg3[3]),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[3]),
.I5(reg3_1_1[3]),
.O(N_1338)
);
defparam \d_cnst_sn.reg2_16_2[3] .INIT=64'hFFF7FF0700F40004;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[2] (
.I0(reg3[2]),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[2]),
.I5(reg3_1_1[2]),
.O(N_1337)
);
defparam \d_cnst_sn.reg2_16_2[2] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2[1] (
.I0(reg3[1]),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[1]),
.I5(reg3_1_1[1]),
.O(N_1336)
);
defparam \d_cnst_sn.reg2_16_2[1] .INIT=64'hFFFBFF0B00F80008;
// @7:74
LUT6 \d_cnst_sn.reg2_16_1_0[25] (
.I0(un3_reg3_s_22),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[31]),
.I3(\d_cnst_sn.reg0_28_a0_1 [7]),
.I4(\d_cnst_sn.reg2_16_0 [25]),
.I5(reg3_1_1[25]),
.O(\d_cnst_sn.reg2_16_1 [25])
);
defparam \d_cnst_sn.reg2_16_1_0[25] .INIT=64'hFBFF000008FF0000;
// @7:74
LUT6 \d_cnst_sn.reg2_16_1_0[24] (
.I0(un3_reg3_s_21),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[31]),
.I3(\d_cnst_sn.reg0_28_a0_1 [7]),
.I4(\d_cnst_sn.reg2_16_0 [24]),
.I5(reg3_1_1[24]),
.O(\d_cnst_sn.reg2_16_1 [24])
);
defparam \d_cnst_sn.reg2_16_1_0[24] .INIT=64'hFBFF000008FF0000;
// @7:74
LUT6 \d_cnst_sn.reg2_16_1_0[23] (
.I0(un3_reg3_s_20),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[31]),
.I3(\d_cnst_sn.reg0_28_a0_1 [7]),
.I4(\d_cnst_sn.reg2_16_0 [23]),
.I5(reg3_1_1[23]),
.O(\d_cnst_sn.reg2_16_1 [23])
);
defparam \d_cnst_sn.reg2_16_1_0[23] .INIT=64'hFBFF000008FF0000;
// @7:74
LUT6 \d_cnst_sn.reg2_16_1_0[22] (
.I0(un3_reg3_s_19),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[31]),
.I3(\d_cnst_sn.reg0_28_a0_1 [7]),
.I4(\d_cnst_sn.reg2_16_0 [22]),
.I5(reg3_1_1[22]),
.O(\d_cnst_sn.reg2_16_1 [22])
);
defparam \d_cnst_sn.reg2_16_1_0[22] .INIT=64'hFBFF000008FF0000;
// @7:74
LUT6 \d_cnst_sn.reg2_16_1_0[21] (
.I0(un3_reg3_s_18),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[31]),
.I3(\d_cnst_sn.reg0_28_a0_1 [7]),
.I4(reg3_1_1[21]),
.I5(\d_cnst_sn.reg2_16_0 [21]),
.O(\d_cnst_sn.reg2_16_1 [21])
);
defparam \d_cnst_sn.reg2_16_1_0[21] .INIT=64'hFBFF08FF00000000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_0[16] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[15]),
.I4(reg3_1_1[16]),
.I5(t_1[16]),
.O(N_1083)
);
defparam \d_cnst_sn.reg0_28_0[16] .INIT=64'hFDDD2000FFDF2202;
// @7:74
LUT6 \d_cnst_sn.reg0_28_0[15] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[14]),
.I4(reg3_1_1[15]),
.I5(t_1[15]),
.O(N_1082)
);
defparam \d_cnst_sn.reg0_28_0[15] .INIT=64'hFDDD2000FFDF2202;
// @7:74
LUT6 \d_cnst_sn.reg0_28_0[14] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[13]),
.I4(reg3_1_1[14]),
.I5(t_1[14]),
.O(N_1081)
);
defparam \d_cnst_sn.reg0_28_0[14] .INIT=64'hFDDD2000FFDF2202;
// @7:74
LUT6 \d_cnst_sn.reg0_28_0[13] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[12]),
.I4(reg3_1_1[13]),
.I5(t_1[13]),
.O(N_1080)
);
defparam \d_cnst_sn.reg0_28_0[13] .INIT=64'hFDDD2000FFDF2202;
// @7:74
LUT6 \d_cnst_sn.reg0_28_0[12] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[11]),
.I4(reg3_1_1[12]),
.I5(t_1[12]),
.O(N_1079)
);
defparam \d_cnst_sn.reg0_28_0[12] .INIT=64'hFDDD2000FFDF2202;
// @7:74
LUT6 \d_cnst_sn.reg0_28_0[11] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[10]),
.I4(reg3_1_1[11]),
.I5(t_1[11]),
.O(N_1078)
);
defparam \d_cnst_sn.reg0_28_0[11] .INIT=64'hFDDD2000FFDF2202;
// @7:74
LUT6 \d_cnst_sn.reg0_28_0[10] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[9]),
.I4(reg3_1_1[10]),
.I5(t_1[10]),
.O(N_1077)
);
defparam \d_cnst_sn.reg0_28_0[10] .INIT=64'hFDDD2000FFDF2202;
// @7:74
LUT6 \d_cnst_sn.reg0_28_0[9] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[8]),
.I4(reg3_1_1[9]),
.I5(t_1[9]),
.O(N_1076)
);
defparam \d_cnst_sn.reg0_28_0[9] .INIT=64'hFDDD2000FFDF2202;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_7[2] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(reg3_1_1[2]),
.I4(r_4[1]),
.I5(t_1[2]),
.LO(N_1069)
);
defparam \d_cnst_sn.reg0_28_7[2] .INIT=64'hFD20DD00FF22DF02;
// @7:74
LUT6 \d_cnst_sn.reg0_28_7[1] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(reg3_1_1[1]),
.I4(r_4[0]),
.I5(t_1[1]),
.O(N_1068)
);
defparam \d_cnst_sn.reg0_28_7[1] .INIT=64'hFD20DD00FF22DF02;
// @7:47
LUT6 \d_cnst_sn.reg0_28_14_0_cZ (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(N_3568),
.I5(reg3_1_1[30]),
.O(\d_cnst_sn.reg0_28_14_0 )
);
defparam \d_cnst_sn.reg0_28_14_0_cZ .INIT=64'hFFFFC101FFFF0000;
LUT6 \d_cnst_sn.r_4_RNITKAH1[4] (
.I0(reg1[4]),
.I1(un3_reg3_s_1),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_919),
.O(r_4[4])
);
defparam \d_cnst_sn.r_4_RNITKAH1[4] .INIT=64'hFCFFFAFF0C000A00;
LUT6 \d_cnst_sn.r_4_RNITKAH1_0[4] (
.I0(reg1[4]),
.I1(un3_reg3_s_1),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_919),
.O(un3_t_axb_4)
);
defparam \d_cnst_sn.r_4_RNITKAH1_0[4] .INIT=64'h03000500F3FFF5FF;
LUT6 \d_cnst_sn.r_4_RNI9T9D1_0[1] (
.I0(reg1[1]),
.I1(reg3[1]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_916),
.O(un3_t_axb_1)
);
defparam \d_cnst_sn.r_4_RNI9T9D1_0[1] .INIT=64'h03000500F3FFF5FF;
LUT6 \d_cnst_sn.r_4_RNI9T9D1[1] (
.I0(reg1[1]),
.I1(reg3[1]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_916),
.O(r_4[1])
);
defparam \d_cnst_sn.r_4_RNI9T9D1[1] .INIT=64'hFCFFFAFF0C000A00;
LUT6 \d_cnst_sn.r_4_RNI6Q9D1[0] (
.I0(reg1[0]),
.I1(reg3[0]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_915),
.O(r_4[0])
);
defparam \d_cnst_sn.r_4_RNI6Q9D1[0] .INIT=64'hFCFFFAFF0C000A00;
LUT6 \d_cnst_sn.r_4_RNI6Q9D1_0[0] (
.I0(reg1[0]),
.I1(reg3[0]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_915),
.O(un3_t_axb_0)
);
defparam \d_cnst_sn.r_4_RNI6Q9D1_0[0] .INIT=64'h03000500F3FFF5FF;
LUT6 \d_cnst_sn.r_4_1_RNI3T3N1[24] (
.I0(reg1[24]),
.I1(un3_reg3_s_21),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_939),
.O(r_4[24])
);
defparam \d_cnst_sn.r_4_1_RNI3T3N1[24] .INIT=64'hFCFFFAFF0C000A00;
LUT6 \d_cnst_sn.r_4_1_RNI3T3N1_0[24] (
.I0(reg1[24]),
.I1(un3_reg3_s_21),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_939),
.O(un3_t_axb_24)
);
defparam \d_cnst_sn.r_4_1_RNI3T3N1_0[24] .INIT=64'h03000500F3FFF5FF;
LUT6 \d_cnst_sn.r_4_1_RNI0R3N1[23] (
.I0(reg1[23]),
.I1(un3_reg3_s_20),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_938),
.O(r_4[23])
);
defparam \d_cnst_sn.r_4_1_RNI0R3N1[23] .INIT=64'hFCFFFAFF0C000A00;
LUT6 \d_cnst_sn.r_4_1_RNI0R3N1_0[23] (
.I0(reg1[23]),
.I1(un3_reg3_s_20),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_938),
.O(un3_t_axb_23)
);
defparam \d_cnst_sn.r_4_1_RNI0R3N1_0[23] .INIT=64'h03000500F3FFF5FF;
LUT6 \d_cnst_sn.r_4_1_RNIC34N1[27] (
.I0(reg1[27]),
.I1(un3_reg3_s_24),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_942),
.O(r_4[27])
);
defparam \d_cnst_sn.r_4_1_RNIC34N1[27] .INIT=64'hFCFFFAFF0C000A00;
LUT6 \d_cnst_sn.r_4_1_RNIC34N1_0[27] (
.I0(reg1[27]),
.I1(un3_reg3_s_24),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_942),
.O(un3_t_axb_27)
);
defparam \d_cnst_sn.r_4_1_RNIC34N1_0[27] .INIT=64'h03000500F3FFF5FF;
LUT6 \d_cnst_sn.r_4_1_RNI0K3N1[20] (
.I0(reg1[20]),
.I1(un3_reg3_s_17),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_935),
.O(r_4[20])
);
defparam \d_cnst_sn.r_4_1_RNI0K3N1[20] .INIT=64'hFCFFFAFF0C000A00;
LUT6 \d_cnst_sn.r_4_1_RNI0K3N1_0[20] (
.I0(reg1[20]),
.I1(un3_reg3_s_17),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_935),
.O(un3_t_axb_20)
);
defparam \d_cnst_sn.r_4_1_RNI0K3N1_0[20] .INIT=64'h03000500F3FFF5FF;
LUT6 \d_cnst_sn.r_4_2_RNIQKBE1[25] (
.I0(reg0[25]),
.I1(reg2[25]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_972),
.O(r_4[25])
);
defparam \d_cnst_sn.r_4_2_RNIQKBE1[25] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNIQKBE1_0[25] (
.I0(reg0[25]),
.I1(reg2[25]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_972),
.O(un3_t_axb_25)
);
defparam \d_cnst_sn.r_4_2_RNIQKBE1_0[25] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNI3UBE1[28] (
.I0(reg0[28]),
.I1(reg2[28]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_975),
.O(r_4[28])
);
defparam \d_cnst_sn.r_4_2_RNI3UBE1[28] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNI3UBE1_0[28] (
.I0(reg0[28]),
.I1(reg2[28]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_975),
.O(un3_t_axb_28)
);
defparam \d_cnst_sn.r_4_2_RNI3UBE1_0[28] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNITNBE1[26] (
.I0(reg0[26]),
.I1(reg2[26]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_973),
.O(r_4[26])
);
defparam \d_cnst_sn.r_4_2_RNITNBE1[26] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNITNBE1_0[26] (
.I0(reg0[26]),
.I1(reg2[26]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_973),
.O(un3_t_axb_26)
);
defparam \d_cnst_sn.r_4_2_RNITNBE1_0[26] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_1_RNI6O3N1_0[22] (
.I0(reg1[22]),
.I1(un3_reg3_s_19),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_937),
.O(un3_t_axb_22)
);
defparam \d_cnst_sn.r_4_1_RNI6O3N1_0[22] .INIT=64'h03000500F3FFF5FF;
LUT6 \d_cnst_sn.r_4_1_RNI6O3N1[22] (
.I0(reg1[22]),
.I1(un3_reg3_s_19),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_937),
.O(r_4[22])
);
defparam \d_cnst_sn.r_4_1_RNI6O3N1[22] .INIT=64'hFCFFFAFF0C000A00;
LUT6 \d_cnst_sn.r_4_RNIF3AD1[3] (
.I0(reg1[3]),
.I1(reg3[3]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_918),
.O(r_4[3])
);
defparam \d_cnst_sn.r_4_RNIF3AD1[3] .INIT=64'hF3FFFAFF03000A00;
LUT6 \d_cnst_sn.r_4_RNIF3AD1_0[3] (
.I0(reg1[3]),
.I1(reg3[3]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_918),
.O(un3_t_axb_3)
);
defparam \d_cnst_sn.r_4_RNIF3AD1_0[3] .INIT=64'h0C000500FCFFF5FF;
// @7:103
LUT5 \d_cnst_sn.reg3_17_a2_2_0_cZ[21] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_967),
.I4(N_935),
.O(\d_cnst_sn.reg3_17_a2_2_0 [21])
);
defparam \d_cnst_sn.reg3_17_a2_2_0_cZ[21] .INIT=32'h44044000;
// @7:103
LUT5 \d_cnst_sn.reg3_17_4_a2_0_cZ[27] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_941),
.I4(N_973),
.O(\d_cnst_sn.reg3_17_4_a2_0 [27])
);
defparam \d_cnst_sn.reg3_17_4_a2_0_cZ[27] .INIT=32'h44400400;
// @7:103
LUT5 \d_cnst_sn.reg3_17_4_a2_0_cZ[25] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_971),
.I4(N_939),
.O(\d_cnst_sn.reg3_17_4_a2_0 [25])
);
defparam \d_cnst_sn.reg3_17_4_a2_0_cZ[25] .INIT=32'h44044000;
// @7:103
LUT5 \d_cnst_sn.reg3_17_4_a2_0_cZ[28] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_974),
.I4(N_942),
.O(\d_cnst_sn.reg3_17_4_a2_0 [28])
);
defparam \d_cnst_sn.reg3_17_4_a2_0_cZ[28] .INIT=32'h44044000;
// @7:103
LUT5 \d_cnst_sn.reg3_17_4_a2_0_cZ[26] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_940),
.I4(N_972),
.O(\d_cnst_sn.reg3_17_4_a2_0 [26])
);
defparam \d_cnst_sn.reg3_17_4_a2_0_cZ[26] .INIT=32'h44400400;
// @7:74
LUT6 \d_cnst_sn.reg0_28_7_d[24] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_970),
.I4(N_938),
.I5(reg3_1_1[24]),
.O(reg0_28_7_d[24])
);
defparam \d_cnst_sn.reg0_28_7_d[24] .INIT=64'hFFDFFDDD22022000;
LUT6 \datai_RNIL2NH1[26] (
.I0(datai[26]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_941),
.I4(N_973),
.I5(m7),
.O(un32_reg0_axb_26)
);
defparam \datai_RNIL2NH1[26] .INIT=64'h00CF30FFAA659A55;
LUT6 \datai_RNIIVMH1[25] (
.I0(datai[25]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_940),
.I4(N_972),
.I5(m7),
.O(un32_reg0_axb_25)
);
defparam \datai_RNIIVMH1[25] .INIT=64'h00CF30FFAA659A55;
LUT6 \d_cnst_sn.r_4_2_RNICPMH1[23] (
.I0(datai[23]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_970),
.I4(N_938),
.I5(m7),
.O(un32_reg0_axb_23)
);
defparam \d_cnst_sn.r_4_2_RNICPMH1[23] .INIT=64'h0030CFFFAA9A6555;
LUT6 \d_cnst_sn.r_4_0_0_RNID9G41[1] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(r_4_2_a0[1]),
.I3(\d_cnst_sn.r_4_0_0 [1]),
.I4(N_916),
.I5(m_2[1]),
.O(un32_reg0_axb_1)
);
defparam \d_cnst_sn.r_4_0_0_RNID9G41[1] .INIT=64'hBFBB04004044FBFF;
LUT6 \d_cnst_sn.r_4_2_a0_RNI4HHP2[0] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(m_2_i[0]),
.I3(r_4_2_a0[0]),
.I4(\d_cnst_sn.r_4_0_0 [0]),
.I5(N_915),
.O(N_1035)
);
defparam \d_cnst_sn.r_4_2_a0_RNI4HHP2[0] .INIT=64'h4B0F4B4BF0B4F0F0;
LUT6 \datai_RNIR8NH1[28] (
.I0(datai[28]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_943),
.I4(N_975),
.I5(m7),
.O(un32_reg0_axb_28)
);
defparam \datai_RNIR8NH1[28] .INIT=64'h00CF30FFAA659A55;
LUT6 \d_cnst_sn.r_4_2_RNIO5NH1[27] (
.I0(datai[27]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_974),
.I4(N_942),
.I5(m7),
.O(un32_reg0_axb_27)
);
defparam \d_cnst_sn.r_4_2_RNIO5NH1[27] .INIT=64'h0030CFFFAA9A6555;
LUT6 \datai_RNI3GMH1[20] (
.I0(datai[20]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_967),
.I4(N_935),
.I5(m7),
.O(un32_reg0_axb_20)
);
defparam \datai_RNI3GMH1[20] .INIT=64'h0030CFFFAA9A6555;
LUT6 \d_cnst_sn.r_4_2_RNIFSMH1[24] (
.I0(datai[24]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_971),
.I4(N_939),
.I5(m7),
.O(un32_reg0_axb_24)
);
defparam \d_cnst_sn.r_4_2_RNIFSMH1[24] .INIT=64'h0030CFFFAA9A6555;
LUT6 \datai_RNI9MMH1[22] (
.I0(datai[22]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_969),
.I4(N_937),
.I5(m7),
.O(un32_reg0_axb_22)
);
defparam \datai_RNI9MMH1[22] .INIT=64'h0030CFFFAA9A6555;
LUT6 \d_cnst_sn.r_4_1_RNI6JMH1[21] (
.I0(datai[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[29]),
.I3(N_936),
.I4(N_968),
.I5(m7),
.O(un32_reg0_axb_21)
);
defparam \d_cnst_sn.r_4_1_RNI6JMH1[21] .INIT=64'h00CF30FFAA659A55;
// @7:47
LUT5 \dce_cZ[0] (
.I0(state[0]),
.I1(inf_abs0_2[23]),
.I2(inf_abs0_2[31]),
.I3(un1_df_1),
.I4(un36_df),
.O(dce[0])
);
defparam \dce_cZ[0] .INIT=32'h000000A2;
// @7:74
LUT6 \d_cnst_sn.un1_state_4_1 (
.I0(state[0]),
.I1(inf_abs0_2[23]),
.I2(inf_abs0_2[31]),
.I3(N_1892),
.I4(un36_df),
.I5(N_1890),
.O(\d_cnst_sn.un1_state_3_1 )
);
defparam \d_cnst_sn.un1_state_4_1 .INIT=64'hFFFFFF5DFFFFFFFF;
// @7:103
LUT4 \d_cnst_sn.reg3_m2_7 (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(N_28),
.I3(t_1[3]),
.O(t_6[3])
);
defparam \d_cnst_sn.reg3_m2_7 .INIT=16'h40FB;
// @7:47
LUT6 \d_cnst_sn.reg0_28_12_2195_a6 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(N_1033),
.I4(un32_reg0_s_28),
.I5(un11_reg0_s_28),
.O(N_3614)
);
defparam \d_cnst_sn.reg0_28_12_2195_a6 .INIT=64'h0606060000060000;
// @7:318
LUT5 un11_reg0_axb_29_cZ (
.I0(datai[29]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[29]),
.O(un11_reg0_axb_29)
);
defparam un11_reg0_axb_29_cZ.INIT=32'hDDDF2220;
LUT6 \d_cnst_sn.r_4_3[19] (
.I0(reg0[19]),
.I1(reg2[19]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_2722),
.O(r_4[19])
);
defparam \d_cnst_sn.r_4_3[19] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_3_i[19] (
.I0(reg0[19]),
.I1(reg2[19]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_2722),
.O(un3_t_axb_19)
);
defparam \d_cnst_sn.r_4_3_i[19] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNI7PRB1[6] (
.I0(reg0[6]),
.I1(reg2[6]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_953),
.O(r_4[6])
);
defparam \d_cnst_sn.r_4_2_RNI7PRB1[6] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNI7PRB1_0[6] (
.I0(reg0[6]),
.I1(reg2[6]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_953),
.O(un3_t_axb_6)
);
defparam \d_cnst_sn.r_4_2_RNI7PRB1_0[6] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIE58E1_0[12] (
.I0(reg0[12]),
.I1(reg2[12]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_959),
.O(un3_t_axb_12)
);
defparam \d_cnst_sn.r_4_2_RNIE58E1_0[12] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIE58E1[12] (
.I0(reg0[12]),
.I1(reg2[12]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_959),
.O(r_4[12])
);
defparam \d_cnst_sn.r_4_2_RNIE58E1[12] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNI4MRB1[5] (
.I0(reg0[5]),
.I1(reg2[5]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_952),
.O(r_4[5])
);
defparam \d_cnst_sn.r_4_2_RNI4MRB1[5] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNI4MRB1_0[5] (
.I0(reg0[5]),
.I1(reg2[5]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_952),
.O(un3_t_axb_5)
);
defparam \d_cnst_sn.r_4_2_RNI4MRB1_0[5] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNITK8E1[17] (
.I0(reg0[17]),
.I1(reg2[17]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_964),
.O(r_4[17])
);
defparam \d_cnst_sn.r_4_2_RNITK8E1[17] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNITK8E1_0[17] (
.I0(reg0[17]),
.I1(reg2[17]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_964),
.O(un3_t_axb_17)
);
defparam \d_cnst_sn.r_4_2_RNITK8E1_0[17] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIASRB1[7] (
.I0(reg0[7]),
.I1(reg2[7]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_954),
.O(r_4[7])
);
defparam \d_cnst_sn.r_4_2_RNIASRB1[7] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNIASRB1_0[7] (
.I0(reg0[7]),
.I1(reg2[7]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_954),
.O(un3_t_axb_7)
);
defparam \d_cnst_sn.r_4_2_RNIASRB1_0[7] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIG2SB1[9] (
.I0(reg0[9]),
.I1(reg2[9]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_956),
.O(r_4[9])
);
defparam \d_cnst_sn.r_4_2_RNIG2SB1[9] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNIG2SB1_0[9] (
.I0(reg0[9]),
.I1(reg2[9]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_956),
.O(un3_t_axb_9)
);
defparam \d_cnst_sn.r_4_2_RNIG2SB1_0[9] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNI8V7E1[10] (
.I0(reg0[10]),
.I1(reg2[10]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_957),
.O(r_4[10])
);
defparam \d_cnst_sn.r_4_2_RNI8V7E1[10] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNI8V7E1_0[10] (
.I0(reg0[10]),
.I1(reg2[10]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_957),
.O(un3_t_axb_10)
);
defparam \d_cnst_sn.r_4_2_RNI8V7E1_0[10] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIKB8E1_0[14] (
.I0(reg0[14]),
.I1(reg2[14]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_961),
.O(un3_t_axb_14)
);
defparam \d_cnst_sn.r_4_2_RNIKB8E1_0[14] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIKB8E1[14] (
.I0(reg0[14]),
.I1(reg2[14]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_961),
.O(r_4[14])
);
defparam \d_cnst_sn.r_4_2_RNIKB8E1[14] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNIQH8E1[16] (
.I0(reg0[16]),
.I1(reg2[16]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_963),
.O(r_4[16])
);
defparam \d_cnst_sn.r_4_2_RNIQH8E1[16] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNIQH8E1_0[16] (
.I0(reg0[16]),
.I1(reg2[16]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_963),
.O(un3_t_axb_16)
);
defparam \d_cnst_sn.r_4_2_RNIQH8E1_0[16] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIH88E1[13] (
.I0(reg0[13]),
.I1(reg2[13]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_960),
.O(r_4[13])
);
defparam \d_cnst_sn.r_4_2_RNIH88E1[13] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNIH88E1_0[13] (
.I0(reg0[13]),
.I1(reg2[13]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_960),
.O(un3_t_axb_13)
);
defparam \d_cnst_sn.r_4_2_RNIH88E1_0[13] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_2_RNIB28E1[11] (
.I0(reg0[11]),
.I1(reg2[11]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_958),
.O(r_4[11])
);
defparam \d_cnst_sn.r_4_2_RNIB28E1[11] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNIB28E1_0[11] (
.I0(reg0[11]),
.I1(reg2[11]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_958),
.O(un3_t_axb_11)
);
defparam \d_cnst_sn.r_4_2_RNIB28E1_0[11] .INIT=64'h505350555F535F55;
LUT6 \d_cnst_sn.r_4_0_0_0_RNIFROS1[4] (
.I0(reg1[4]),
.I1(inf_abs0_2[30]),
.I2(\d_cnst_sn.r_4_0_0 [4]),
.I3(N_919),
.I4(m_2[4]),
.I5(N_13),
.O(un32_reg0_axb_4)
);
defparam \d_cnst_sn.r_4_0_0_0_RNIFROS1[4] .INIT=64'hFF0000FFE0E01F1F;
LUT6 \d_cnst_sn.r_4_2_RNINE8E1[15] (
.I0(reg0[15]),
.I1(reg2[15]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_962),
.O(r_4[15])
);
defparam \d_cnst_sn.r_4_2_RNINE8E1[15] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNINE8E1_0[15] (
.I0(reg0[15]),
.I1(reg2[15]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_962),
.O(un3_t_axb_15)
);
defparam \d_cnst_sn.r_4_2_RNINE8E1_0[15] .INIT=64'h505350555F535F55;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_8_627_i_1_RNIKNJN1 (
.I0(state[0]),
.I1(un1_inf_abs0_10[1]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(\d_cnst_sn.addr_20_iv_8_627_i_1 ),
.I5(N_2641),
.LO(N_2315_i)
);
defparam \d_cnst_sn.addr_20_iv_8_627_i_1_RNIKNJN1 .INIT=64'h000000000000DFFF;
LUT6 \d_cnst_sn.r_4_2_RNIDVRB1[8] (
.I0(reg0[8]),
.I1(reg2[8]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_955),
.O(r_4[8])
);
defparam \d_cnst_sn.r_4_2_RNIDVRB1[8] .INIT=64'hAFACAFAAA0ACA0AA;
LUT6 \d_cnst_sn.r_4_2_RNIDVRB1_0[8] (
.I0(reg0[8]),
.I1(reg2[8]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.I5(N_955),
.O(un3_t_axb_8)
);
defparam \d_cnst_sn.r_4_2_RNIDVRB1_0[8] .INIT=64'h505350555F535F55;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_7_654_i_1_RNIG3SC1 (
.I0(reg2[0]),
.I1(inf_abs0_2[0]),
.I2(inf_abs0_2[28]),
.I3(\d_cnst_sn.addr_20_iv_7_654_i_1 ),
.I4(N_2660_2),
.I5(N_2641),
.LO(N_2335_i)
);
defparam \d_cnst_sn.addr_20_iv_7_654_i_1_RNIG3SC1 .INIT=64'h00000000006F00FF;
LUT6 \d_cnst_sn.r_4_0_0_0_RNIBNOS1[3] (
.I0(reg1[3]),
.I1(inf_abs0_2[30]),
.I2(\d_cnst_sn.r_4_0_0 [3]),
.I3(N_918),
.I4(m_2[3]),
.I5(N_13),
.O(un32_reg0_axb_3)
);
defparam \d_cnst_sn.r_4_0_0_0_RNIBNOS1[3] .INIT=64'hFF0000FFE0E01F1F;
LUT6 \datai_RNIO9B94[2] (
.I0(datai[2]),
.I1(inf_abs0_2[2]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(N_28),
.O(un32_reg0_axb_2)
);
defparam \datai_RNIO9B94[2] .INIT=64'hCACACACC35353533;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[22] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_22),
.I3(un11_reg0_s_22),
.O(N_1581)
);
defparam \d_cnst_sn.reg2_16_9[22] .INIT=16'hFD20;
// @7:118
LUT6 un11_r_df22_cZ (
.I0(N_969),
.I1(N_937),
.I2(m_2[22]),
.I3(m_2[23]),
.I4(N_13),
.I5(r_4[23]),
.O(un11_r_df22)
);
defparam un11_r_df22_cZ.INIT=64'hC300A50000C300A5;
// @7:118
LUT6 un11_r_lt22_cZ (
.I0(N_969),
.I1(N_937),
.I2(m_2[22]),
.I3(m_2[23]),
.I4(N_13),
.I5(r_4[23]),
.O(un11_r_lt22)
);
defparam un11_r_lt22_cZ.INIT=64'h30005000FF30FF50;
// @7:151
LUT6 un26_r_lt22_cZ (
.I0(N_969),
.I1(N_937),
.I2(m_2[22]),
.I3(m_2[23]),
.I4(N_13),
.I5(r_4[23]),
.O(un26_r_lt22)
);
defparam un26_r_lt22_cZ.INIT=64'h30005000FF30FF50;
// @7:151
LUT6 un26_r_df22_cZ (
.I0(N_969),
.I1(N_937),
.I2(m_2[22]),
.I3(m_2[23]),
.I4(N_13),
.I5(r_4[23]),
.O(un26_r_df22)
);
defparam un26_r_df22_cZ.INIT=64'hC300A50000C300A5;
// @7:143
LUT6 b18_df22_cZ (
.I0(N_969),
.I1(N_937),
.I2(m_2[22]),
.I3(m_2[23]),
.I4(N_13),
.I5(r_4[23]),
.O(b18_df22)
);
defparam b18_df22_cZ.INIT=64'hC300A50000C300A5;
// @7:143
LUT6 b18_lt22_cZ (
.I0(N_969),
.I1(N_937),
.I2(m_2[22]),
.I3(m_2[23]),
.I4(N_13),
.I5(r_4[23]),
.O(b18_lt22)
);
defparam b18_lt22_cZ.INIT=64'h0CFF0AFF000C000A;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[8] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_8),
.I3(un11_reg0_s_8),
.O(N_1375)
);
defparam \d_cnst_sn.reg2_16_3[8] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[23] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_23),
.I3(un11_reg0_s_23),
.O(N_1582)
);
defparam \d_cnst_sn.reg2_16_9[23] .INIT=16'hFD20;
// @7:103
LUT4_L \d_cnst_sn.b_cnst_0_m2_0 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(b18),
.I3(un26_r_cry[30]),
.LO(N_895)
);
defparam \d_cnst_sn.b_cnst_0_m2_0 .INIT=16'h2F0D;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[21] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_21),
.I3(un11_reg0_s_21),
.O(N_1580)
);
defparam \d_cnst_sn.reg2_16_9[21] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[16] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_16),
.I3(un11_reg0_s_16),
.O(N_1575)
);
defparam \d_cnst_sn.reg2_16_9[16] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[14] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_14),
.I3(un11_reg0_s_14),
.O(N_1381)
);
defparam \d_cnst_sn.reg2_16_3[14] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[24] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_24),
.I3(un11_reg0_s_24),
.O(N_1583)
);
defparam \d_cnst_sn.reg2_16_9[24] .INIT=16'hFD20;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[2] (
.I0(r_4_2_a0[1]),
.I1(\d_cnst_sn.r_4_0_0 [1]),
.I2(N_916),
.I3(N_527_i),
.I4(N_13),
.I5(t_1[2]),
.LO(t_6[2])
);
defparam \d_cnst_sn.reg2_16_11_RNO[2] .INIT=64'hF0004400F0FF44FF;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[2] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un11_reg0_s_2),
.I3(un32_reg0_s_2),
.O(N_1369)
);
defparam \d_cnst_sn.reg2_16_3[2] .INIT=16'hF2D0;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[5] (
.I0(r_4_2_a1_lut6_2_O5[3]),
.I1(\d_cnst_sn.r_4_0_0 [4]),
.I2(N_919),
.I3(N_527_i),
.I4(N_13),
.I5(t_1[5]),
.LO(t_6[5])
);
defparam \d_cnst_sn.reg2_16_11_RNO[5] .INIT=64'hF0004400F0FF44FF;
// @7:103
LUT6_L \d_cnst_sn.r_4_2_a1_lut6_2_RNI5V8R3[3] (
.I0(r_4_2_a1_lut6_2_O5[3]),
.I1(\d_cnst_sn.r_4_0_0 [4]),
.I2(N_919),
.I3(N_527_i),
.I4(N_13),
.I5(t_1[5]),
.LO(r_4_2_a1_lut6_2_RNI5V8R3[3])
);
defparam \d_cnst_sn.r_4_2_a1_lut6_2_RNI5V8R3[3] .INIT=64'h0FFFBBFF0F00BB00;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_21_1130_i_m2 (
.I0(reg1[19]),
.I1(reg0[19]),
.I2(reg2[19]),
.I3(un3_reg3_s_16),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(N_2724)
);
defparam \d_cnst_sn.r_4_3_21_1130_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[4] (
.I0(r_4_2_a1_lut6_2_O6[3]),
.I1(\d_cnst_sn.r_4_0_0 [3]),
.I2(N_918),
.I3(N_527_i),
.I4(N_13),
.I5(t_1[4]),
.LO(t_6[4])
);
defparam \d_cnst_sn.reg2_16_11_RNO[4] .INIT=64'hF0004400F0FF44FF;
// @7:103
LUT6_L \d_cnst_sn.r_4_2_a1_lut6_2_RNI2T8R3[3] (
.I0(r_4_2_a1_lut6_2_O6[3]),
.I1(\d_cnst_sn.r_4_0_0 [3]),
.I2(N_918),
.I3(N_527_i),
.I4(N_13),
.I5(t_1[4]),
.LO(r_4_2_a1_lut6_2_RNI2T8R3[3])
);
defparam \d_cnst_sn.r_4_2_a1_lut6_2_RNI2T8R3[3] .INIT=64'h0FFFBBFF0F00BB00;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[8] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_8),
.I5(un11_reg0_s_8),
.O(N_1043)
);
defparam \d_cnst_sn.reg0_28_6[8] .INIT=64'hFFFFFF3500CA0000;
// @7:118
LUT6 un11_r_df20_cZ (
.I0(N_967),
.I1(N_935),
.I2(m_2[20]),
.I3(m_2[21]),
.I4(N_13),
.I5(r_4[21]),
.O(un11_r_df20)
);
defparam un11_r_df20_cZ.INIT=64'hC300A50000C300A5;
// @7:118
LUT6 un11_r_lt20_cZ (
.I0(N_967),
.I1(N_935),
.I2(m_2[20]),
.I3(m_2[21]),
.I4(N_13),
.I5(r_4[21]),
.O(un11_r_lt20)
);
defparam un11_r_lt20_cZ.INIT=64'h30005000FF30FF50;
// @7:151
LUT6 un26_r_df20_cZ (
.I0(N_967),
.I1(N_935),
.I2(m_2[20]),
.I3(m_2[21]),
.I4(N_13),
.I5(r_4[21]),
.O(un26_r_df20)
);
defparam un26_r_df20_cZ.INIT=64'hC300A50000C300A5;
// @7:151
LUT6 un26_r_lt20_cZ (
.I0(N_967),
.I1(N_935),
.I2(m_2[20]),
.I3(m_2[21]),
.I4(N_13),
.I5(r_4[21]),
.O(un26_r_lt20)
);
defparam un26_r_lt20_cZ.INIT=64'h30005000FF30FF50;
// @7:143
LUT6 b18_df20_cZ (
.I0(N_967),
.I1(N_935),
.I2(m_2[20]),
.I3(m_2[21]),
.I4(N_13),
.I5(r_4[21]),
.O(b18_df20)
);
defparam b18_df20_cZ.INIT=64'hC300A50000C300A5;
// @7:143
LUT6 b18_lt20_cZ (
.I0(N_967),
.I1(N_935),
.I2(m_2[20]),
.I3(m_2[21]),
.I4(N_13),
.I5(r_4[21]),
.O(b18_lt20)
);
defparam b18_lt20_cZ.INIT=64'h0CFF0AFF000C000A;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[12] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_12),
.I3(un11_reg0_s_12),
.O(N_1379)
);
defparam \d_cnst_sn.reg2_16_3[12] .INIT=16'hFD20;
// @7:74
LUT6_L \d_cnst_sn.reg1_16[0] (
.I0(N_513_i),
.I1(m_2[0]),
.I2(N_527_i),
.I3(N_3916),
.I4(N_1035),
.I5(t_1[0]),
.LO(reg1_16[0])
);
defparam \d_cnst_sn.reg1_16[0] .INIT=64'h0044FF44004EFF4E;
// @7:74
LUT6_L \d_cnst_sn.reg0_28[0] (
.I0(N_513_i),
.I1(m_2[0]),
.I2(N_527_i),
.I3(N_3916),
.I4(N_1035),
.I5(t_1[0]),
.LO(reg0_28[0])
);
defparam \d_cnst_sn.reg0_28[0] .INIT=64'h0044FF44004EFF4E;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[15] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_15),
.I3(un11_reg0_s_15),
.O(N_1574)
);
defparam \d_cnst_sn.reg2_16_9[15] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[7] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_7),
.I5(un11_reg0_s_7),
.O(N_1042)
);
defparam \d_cnst_sn.reg0_28_6[7] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[11] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_11),
.I5(un11_reg0_s_11),
.O(N_1046)
);
defparam \d_cnst_sn.reg0_28_6[11] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[13] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_13),
.I3(un11_reg0_s_13),
.O(N_1380)
);
defparam \d_cnst_sn.reg2_16_3[13] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[13] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_13),
.I5(un11_reg0_s_13),
.O(N_1048)
);
defparam \d_cnst_sn.reg0_28_6[13] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[11] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_11),
.I3(un11_reg0_s_11),
.O(N_1378)
);
defparam \d_cnst_sn.reg2_16_3[11] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[10] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_10),
.I3(un11_reg0_s_10),
.O(N_1377)
);
defparam \d_cnst_sn.reg2_16_3[10] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[9] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_9),
.I3(un11_reg0_s_9),
.O(N_1376)
);
defparam \d_cnst_sn.reg2_16_3[9] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[6] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_6),
.I3(un11_reg0_s_6),
.O(N_1373)
);
defparam \d_cnst_sn.reg2_16_3[6] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[3] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_3),
.I3(un11_reg0_s_3),
.O(N_1370)
);
defparam \d_cnst_sn.reg2_16_3[3] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[1] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un11_reg0_s_1),
.I3(un32_reg0_s_1),
.O(N_1368)
);
defparam \d_cnst_sn.reg2_16_3[1] .INIT=16'hF2D0;
// @7:118
LUT6 un11_r_df28_cZ (
.I0(N_943),
.I1(N_975),
.I2(m_2[29]),
.I3(m_2[28]),
.I4(N_13),
.I5(r_4[29]),
.O(un11_r_df28)
);
defparam un11_r_df28_cZ.INIT=64'hA050C0300A050C03;
// @7:118
LUT6 un11_r_lt28_cZ (
.I0(N_943),
.I1(N_975),
.I2(m_2[29]),
.I3(m_2[28]),
.I4(N_13),
.I5(r_4[29]),
.O(un11_r_lt28)
);
defparam un11_r_lt28_cZ.INIT=64'h50003000F5F0F3F0;
// @7:151
LUT6 un26_r_df28_cZ (
.I0(N_943),
.I1(N_975),
.I2(m_2[29]),
.I3(m_2[28]),
.I4(N_13),
.I5(r_4[29]),
.O(un26_r_df28)
);
defparam un26_r_df28_cZ.INIT=64'hA050C0300A050C03;
// @7:151
LUT6 un26_r_lt28_cZ (
.I0(N_943),
.I1(N_975),
.I2(m_2[29]),
.I3(m_2[28]),
.I4(N_13),
.I5(r_4[29]),
.O(un26_r_lt28)
);
defparam un26_r_lt28_cZ.INIT=64'h50003000F5F0F3F0;
// @7:143
LUT6 b18_df28_cZ (
.I0(N_943),
.I1(N_975),
.I2(m_2[29]),
.I3(m_2[28]),
.I4(N_13),
.I5(r_4[29]),
.O(b18_df28)
);
defparam b18_df28_cZ.INIT=64'hA050C0300A050C03;
// @7:143
LUT6 b18_lt28_cZ (
.I0(N_943),
.I1(N_975),
.I2(m_2[29]),
.I3(m_2[28]),
.I4(N_13),
.I5(r_4[29]),
.O(b18_lt28)
);
defparam b18_lt28_cZ.INIT=64'h0FAF0FCF000A000C;
// @7:118
LUT6 un11_r_df26_cZ (
.I0(N_941),
.I1(N_973),
.I2(m_2[26]),
.I3(m_2[27]),
.I4(N_13),
.I5(r_4[27]),
.O(un11_r_df26)
);
defparam un11_r_df26_cZ.INIT=64'hA500C30000A500C3;
// @7:118
LUT6 un11_r_lt26_cZ (
.I0(N_941),
.I1(N_973),
.I2(m_2[26]),
.I3(m_2[27]),
.I4(N_13),
.I5(r_4[27]),
.O(un11_r_lt26)
);
defparam un11_r_lt26_cZ.INIT=64'h50003000FF50FF30;
// @7:143
LUT6 b18_df26_cZ (
.I0(N_941),
.I1(N_973),
.I2(m_2[26]),
.I3(m_2[27]),
.I4(N_13),
.I5(r_4[27]),
.O(b18_df26)
);
defparam b18_df26_cZ.INIT=64'hA500C30000A500C3;
// @7:151
LUT6 un26_r_df26_cZ (
.I0(N_941),
.I1(N_973),
.I2(m_2[26]),
.I3(m_2[27]),
.I4(N_13),
.I5(r_4[27]),
.O(un26_r_df26)
);
defparam un26_r_df26_cZ.INIT=64'hA500C30000A500C3;
// @7:151
LUT6 un26_r_lt26_cZ (
.I0(N_941),
.I1(N_973),
.I2(m_2[26]),
.I3(m_2[27]),
.I4(N_13),
.I5(r_4[27]),
.O(un26_r_lt26)
);
defparam un26_r_lt26_cZ.INIT=64'h50003000FF50FF30;
// @7:143
LUT6 b18_lt26_cZ (
.I0(N_941),
.I1(N_973),
.I2(m_2[26]),
.I3(m_2[27]),
.I4(N_13),
.I5(r_4[27]),
.O(b18_lt26)
);
defparam b18_lt26_cZ.INIT=64'h0AFF0CFF000A000C;
// @7:118
LUT6 un11_r_lt24_cZ (
.I0(N_940),
.I1(N_972),
.I2(m_2[24]),
.I3(m_2[25]),
.I4(N_13),
.I5(r_4[24]),
.O(un11_r_lt24)
);
defparam un11_r_lt24_cZ.INIT=64'h55003300F550F330;
// @7:118
LUT6 un11_r_df24_cZ (
.I0(N_940),
.I1(N_972),
.I2(m_2[24]),
.I3(m_2[25]),
.I4(N_13),
.I5(r_4[24]),
.O(un11_r_df24)
);
defparam un11_r_df24_cZ.INIT=64'hA050C0300A050C03;
// @7:143
LUT6 b18_df24_cZ (
.I0(N_940),
.I1(N_972),
.I2(m_2[24]),
.I3(m_2[25]),
.I4(N_13),
.I5(r_4[24]),
.O(b18_df24)
);
defparam b18_df24_cZ.INIT=64'hA050C0300A050C03;
// @7:143
LUT6 b18_lt24_cZ (
.I0(N_940),
.I1(N_972),
.I2(m_2[24]),
.I3(m_2[25]),
.I4(N_13),
.I5(r_4[24]),
.O(b18_lt24)
);
defparam b18_lt24_cZ.INIT=64'h0AAF0CCF00AA00CC;
// @7:151
LUT6 un26_r_df24_cZ (
.I0(N_940),
.I1(N_972),
.I2(m_2[24]),
.I3(m_2[25]),
.I4(N_13),
.I5(r_4[24]),
.O(un26_r_df24)
);
defparam un26_r_df24_cZ.INIT=64'hA050C0300A050C03;
// @7:151
LUT6 un26_r_lt24_cZ (
.I0(N_940),
.I1(N_972),
.I2(m_2[24]),
.I3(m_2[25]),
.I4(N_13),
.I5(r_4[24]),
.O(un26_r_lt24)
);
defparam un26_r_lt24_cZ.INIT=64'h55003300F550F330;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11mux_RNO_1[1] (
.I0(r_4_2_a0[0]),
.I1(\d_cnst_sn.r_4_0_0 [0]),
.I2(N_915),
.I3(N_527_i),
.I4(N_13),
.I5(t_1[1]),
.LO(t_6[1])
);
defparam \d_cnst_sn.reg2_16_11mux_RNO_1[1] .INIT=64'hF0004400F0FF44FF;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[9] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_9),
.I5(un11_reg0_s_9),
.O(N_1044)
);
defparam \d_cnst_sn.reg0_28_6[9] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[1] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un11_reg0_s_1),
.I5(un32_reg0_s_1),
.O(N_1036)
);
defparam \d_cnst_sn.reg0_28_6[1] .INIT=64'hFFFF00CAFF350000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[2] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un11_reg0_s_2),
.I5(un32_reg0_s_2),
.O(N_1037)
);
defparam \d_cnst_sn.reg0_28_6[2] .INIT=64'hFFFF00CAFF350000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[6] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_6),
.I5(un11_reg0_s_6),
.O(N_1041)
);
defparam \d_cnst_sn.reg0_28_6[6] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a4[22] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_22),
.I5(un11_reg0_s_22),
.O(reg2_16_11_a4[22])
);
defparam \d_cnst_sn.reg2_16_11_a4[22] .INIT=64'h0000002000100030;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a4[21] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_21),
.I5(un11_reg0_s_21),
.O(reg2_16_11_a4[21])
);
defparam \d_cnst_sn.reg2_16_11_a4[21] .INIT=64'h0000002000100030;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a2[17] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_17),
.I5(un11_reg0_s_17),
.O(reg2_16_11_a2[17])
);
defparam \d_cnst_sn.reg2_16_11_a2[17] .INIT=64'h000000080004000C;
// @7:74
LUT6 \d_cnst_sn.reg2_16_1_cZ[20] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.I5(un32_reg0_s_20),
.O(\d_cnst_sn.reg2_16_1 [20])
);
defparam \d_cnst_sn.reg2_16_1_cZ[20] .INIT=64'hFFFFFFFFFFFFF53F;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[14] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_14),
.I3(un11_reg0_s_14),
.O(N_1573)
);
defparam \d_cnst_sn.reg2_16_9[14] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[13] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_13),
.I3(un11_reg0_s_13),
.O(N_1572)
);
defparam \d_cnst_sn.reg2_16_9[13] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[12] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_12),
.I3(un11_reg0_s_12),
.O(N_1571)
);
defparam \d_cnst_sn.reg2_16_9[12] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[11] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_11),
.I3(un11_reg0_s_11),
.O(N_1570)
);
defparam \d_cnst_sn.reg2_16_9[11] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[10] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_10),
.I3(un11_reg0_s_10),
.O(N_1569)
);
defparam \d_cnst_sn.reg2_16_9[10] .INIT=16'hFD20;
// @7:47
LUT5 \d_cnst_sn.addr_20_iv_14_443_i_2_cZ (
.I0(state[0]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_inf_abs0_10[7]),
.I4(un1_inf_abs0_11[7]),
.O(\d_cnst_sn.addr_20_iv_14_443_i_2 )
);
defparam \d_cnst_sn.addr_20_iv_14_443_i_2_cZ .INIT=32'h008022A2;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[15] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_15),
.I3(un11_reg0_s_15),
.O(N_1382)
);
defparam \d_cnst_sn.reg2_16_3[15] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a4[25] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_25),
.I5(un11_reg0_s_25),
.O(reg2_16_11_a4[25])
);
defparam \d_cnst_sn.reg2_16_11_a4[25] .INIT=64'h0000002000100030;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[5] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_5),
.I3(un11_reg0_s_5),
.O(N_1372)
);
defparam \d_cnst_sn.reg2_16_3[5] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[16] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_16),
.I5(un11_reg0_s_16),
.O(N_1051)
);
defparam \d_cnst_sn.reg0_28_6[16] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[4] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_4),
.I3(un11_reg0_s_4),
.O(N_1371)
);
defparam \d_cnst_sn.reg2_16_3[4] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[15] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_15),
.I5(un11_reg0_s_15),
.O(N_1050)
);
defparam \d_cnst_sn.reg0_28_6[15] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[17] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_17),
.I5(un11_reg0_s_17),
.O(N_1052)
);
defparam \d_cnst_sn.reg0_28_6[17] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[16] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_16),
.I3(un11_reg0_s_16),
.O(N_1383)
);
defparam \d_cnst_sn.reg2_16_3[16] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a3[29] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_29),
.I5(un11_reg0_s_29),
.O(reg2_16_11_a3[29])
);
defparam \d_cnst_sn.reg2_16_11_a3[29] .INIT=64'h0030001000200000;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a4[24] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_24),
.I5(un11_reg0_s_24),
.O(reg2_16_11_a4[24])
);
defparam \d_cnst_sn.reg2_16_11_a4[24] .INIT=64'h0000002000100030;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a2[18] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_18),
.I5(un11_reg0_s_18),
.O(reg2_16_11_a2[18])
);
defparam \d_cnst_sn.reg2_16_11_a2[18] .INIT=64'h000000080004000C;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[5] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_5),
.I3(un11_reg0_s_5),
.O(N_1564)
);
defparam \d_cnst_sn.reg2_16_9[5] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[10] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_10),
.I5(un11_reg0_s_10),
.O(N_1045)
);
defparam \d_cnst_sn.reg0_28_6[10] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[14] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_14),
.I5(un11_reg0_s_14),
.O(N_1049)
);
defparam \d_cnst_sn.reg0_28_6[14] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[9] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_9),
.I3(un11_reg0_s_9),
.O(N_1568)
);
defparam \d_cnst_sn.reg2_16_9[9] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a2[19] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_19),
.I5(un11_reg0_s_19),
.O(reg2_16_11_a2[19])
);
defparam \d_cnst_sn.reg2_16_11_a2[19] .INIT=64'h000000080004000C;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[4] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_4),
.I5(un11_reg0_s_4),
.O(N_1039)
);
defparam \d_cnst_sn.reg0_28_6[4] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[18] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_18),
.I5(un11_reg0_s_18),
.O(N_1053)
);
defparam \d_cnst_sn.reg0_28_6[18] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[6] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_6),
.I3(un11_reg0_s_6),
.O(N_1565)
);
defparam \d_cnst_sn.reg2_16_9[6] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_3[7] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_7),
.I3(un11_reg0_s_7),
.O(N_1374)
);
defparam \d_cnst_sn.reg2_16_3[7] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[8] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_8),
.I3(un11_reg0_s_8),
.O(N_1567)
);
defparam \d_cnst_sn.reg2_16_9[8] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a4[23] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_23),
.I5(un11_reg0_s_23),
.O(reg2_16_11_a4[23])
);
defparam \d_cnst_sn.reg2_16_11_a4[23] .INIT=64'h0000002000100030;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[5] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_5),
.I5(un11_reg0_s_5),
.O(N_1040)
);
defparam \d_cnst_sn.reg0_28_6[5] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[3] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_3),
.I5(un11_reg0_s_3),
.O(N_1038)
);
defparam \d_cnst_sn.reg0_28_6[3] .INIT=64'hFFFFFF3500CA0000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_6[12] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.I4(un32_reg0_s_12),
.I5(un11_reg0_s_12),
.O(N_1047)
);
defparam \d_cnst_sn.reg0_28_6[12] .INIT=64'hFFFFFF3500CA0000;
// @7:47
LUT4 \d_cnst_sn.reg0_28_11_2228_a6_1_1_cZ (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(reg3_1_1[27]),
.O(\d_cnst_sn.reg0_28_11_2228_a6_1_1 )
);
defparam \d_cnst_sn.reg0_28_11_2228_a6_1_1_cZ .INIT=16'h0100;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[2] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un11_reg0_s_2),
.I3(un32_reg0_s_2),
.O(N_1561)
);
defparam \d_cnst_sn.reg2_16_9[2] .INIT=16'hF2D0;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[25] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_25),
.I3(un11_reg0_s_25),
.O(N_1584)
);
defparam \d_cnst_sn.reg2_16_9[25] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[4] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_4),
.I3(un11_reg0_s_4),
.O(N_1563)
);
defparam \d_cnst_sn.reg2_16_9[4] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[7] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_7),
.I3(un11_reg0_s_7),
.O(N_1566)
);
defparam \d_cnst_sn.reg2_16_9[7] .INIT=16'hFD20;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[3] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un32_reg0_s_3),
.I3(un11_reg0_s_3),
.O(N_1562)
);
defparam \d_cnst_sn.reg2_16_9[3] .INIT=16'hFD20;
// @7:74
LUT6 \d_cnst_sn.reg2_16_2_d[20] (
.I0(datai[20]),
.I1(un3_reg3_s_17),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(inf_abs0_2[27]),
.I5(inf_abs0_2[28]),
.O(reg2_16_2_d[20])
);
defparam \d_cnst_sn.reg2_16_2_d[20] .INIT=64'hCCACCCACCCACCC0C;
// @7:74
LUT4 \d_cnst_sn.reg2_16_9[1] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.I2(un11_reg0_s_1),
.I3(un32_reg0_s_1),
.O(N_1560)
);
defparam \d_cnst_sn.reg2_16_9[1] .INIT=16'hF2D0;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[7] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_921),
.I4(N_953),
.I5(t_1[7]),
.LO(t_6[7])
);
defparam \d_cnst_sn.reg2_16_11_RNO[7] .INIT=64'h44400400FFFBBFBB;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[6] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_920),
.I4(N_952),
.I5(t_1[6]),
.LO(t_6[6])
);
defparam \d_cnst_sn.reg2_16_11_RNO[6] .INIT=64'h44400400FFFBBFBB;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[13] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_927),
.I4(N_959),
.I5(t_1[13]),
.LO(t_6[13])
);
defparam \d_cnst_sn.reg2_16_11_RNO[13] .INIT=64'h44400400FFFBBFBB;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[15] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_929),
.I4(N_961),
.I5(t_1[15]),
.LO(t_6[15])
);
defparam \d_cnst_sn.reg2_16_11_RNO[15] .INIT=64'h44400400FFFBBFBB;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[16] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_930),
.I4(N_962),
.I5(t_1[16]),
.LO(t_6[16])
);
defparam \d_cnst_sn.reg2_16_11_RNO[16] .INIT=64'h44400400FFFBBFBB;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[14] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_928),
.I4(N_960),
.I5(t_1[14]),
.LO(t_6[14])
);
defparam \d_cnst_sn.reg2_16_11_RNO[14] .INIT=64'h44400400FFFBBFBB;
// @7:103
LUT5 \d_cnst_sn.reg3_17_4_a2_0_cZ[20] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_934),
.I4(N_2722),
.O(\d_cnst_sn.reg3_17_4_a2_0 [20])
);
defparam \d_cnst_sn.reg3_17_4_a2_0_cZ[20] .INIT=32'h44400400;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[0] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_527_i),
.I3(N_1335),
.I4(N_1035),
.I5(t_1[0]),
.LO(reg2_16[0])
);
defparam \d_cnst_sn.reg2_16_11[0] .INIT=64'h1100776619087F6E;
// @7:103
LUT6_L \d_cnst_sn.r_4_1_RNIIQ731[8] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_923),
.I4(N_955),
.I5(t_1[9]),
.LO(r_4_1_RNIIQ731[8])
);
defparam \d_cnst_sn.r_4_1_RNIIQ731[8] .INIT=64'hBBBFFBFF00044044;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[11] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_925),
.I4(N_957),
.I5(t_1[11]),
.LO(t_6[11])
);
defparam \d_cnst_sn.reg2_16_11_RNO[11] .INIT=64'h44400400FFFBBFBB;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[12] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_926),
.I4(N_958),
.I5(t_1[12]),
.LO(t_6[12])
);
defparam \d_cnst_sn.reg2_16_11_RNO[12] .INIT=64'h44400400FFFBBFBB;
// @7:103
LUT6_L \d_cnst_sn.r_4_1_RNI9K731[5] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_920),
.I4(N_952),
.I5(t_1[6]),
.LO(r_4_1_RNI9K731[5])
);
defparam \d_cnst_sn.r_4_1_RNI9K731[5] .INIT=64'hBBBFFBFF00044044;
// @7:103
LUT6_L \d_cnst_sn.r_4_1_RNICM731[6] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_921),
.I4(N_953),
.I5(t_1[7]),
.LO(r_4_1_RNICM731[6])
);
defparam \d_cnst_sn.r_4_1_RNICM731[6] .INIT=64'hBBBFFBFF00044044;
// @7:103
LUT6_L \d_cnst_sn.r_4_1_RNIDBOH1[10] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_925),
.I4(N_957),
.I5(t_1[11]),
.LO(r_4_1_RNIDBOH1[10])
);
defparam \d_cnst_sn.r_4_1_RNIDBOH1[10] .INIT=64'hBBBFFBFF00044044;
// @7:103
LUT6_L \d_cnst_sn.r_4_1_RNIS3K91[9] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_924),
.I4(N_956),
.I5(t_1[10]),
.LO(r_4_1_RNIS3K91[9])
);
defparam \d_cnst_sn.r_4_1_RNIS3K91[9] .INIT=64'hBBBFFBFF00044044;
// @7:103
LUT6_L \d_cnst_sn.r_4_1_RNIFO731[7] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_922),
.I4(N_954),
.I5(t_1[8]),
.LO(r_4_1_RNIFO731[7])
);
defparam \d_cnst_sn.r_4_1_RNIFO731[7] .INIT=64'hBBBFFBFF00044044;
// @7:74
LUT6 \d_cnst_sn.reg0_28_7_a1[17] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[29]),
.I4(N_931),
.I5(N_963),
.O(reg0_28_7_a1[17])
);
defparam \d_cnst_sn.reg0_28_7_a1[17] .INIT=64'h0000002020002020;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[8] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_922),
.I4(N_954),
.I5(t_1[8]),
.LO(t_6[8])
);
defparam \d_cnst_sn.reg2_16_11_RNO[8] .INIT=64'h44400400FFFBBFBB;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[9] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_923),
.I4(N_955),
.I5(t_1[9]),
.LO(t_6[9])
);
defparam \d_cnst_sn.reg2_16_11_RNO[9] .INIT=64'h44400400FFFBBFBB;
// @7:74
LUT6 \d_cnst_sn.reg0_28_7_a1[18] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(inf_abs0_2[29]),
.I4(N_932),
.I5(N_964),
.O(reg0_28_7_a1[18])
);
defparam \d_cnst_sn.reg0_28_7_a1[18] .INIT=64'h0000002020002020;
// @7:86
LUT6_L \d_cnst_sn.reg2_16_11_RNO[10] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.I2(inf_abs0_2[29]),
.I3(N_924),
.I4(N_956),
.I5(t_1[10]),
.LO(t_6[10])
);
defparam \d_cnst_sn.reg2_16_11_RNO[10] .INIT=64'h44400400FFFBBFBB;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_2[23] (
.I0(N_7_i),
.I1(un36_df),
.I2(un1_b59),
.I3(un87_df),
.I4(un32_reg0_s_23),
.I5(un11_reg0_s_23),
.LO(N_1742)
);
defparam \d_cnst_sn.reg3_17_2[23] .INIT=64'hFFFFEFFF10000000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_2[24] (
.I0(N_7_i),
.I1(un36_df),
.I2(un1_b59),
.I3(un87_df),
.I4(un32_reg0_s_24),
.I5(un11_reg0_s_24),
.LO(N_1743)
);
defparam \d_cnst_sn.reg3_17_2[24] .INIT=64'hFFFFEFFF10000000;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_0[18] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[17]),
.I4(reg3_1_1[18]),
.I5(t_1[18]),
.LO(N_1085)
);
defparam \d_cnst_sn.reg0_28_0[18] .INIT=64'hFDDD2000FFDF2202;
// @7:103
LUT6 \d_cnst_sn.reg3_17_2[13] (
.I0(N_7_i),
.I1(un36_df),
.I2(un1_b59),
.I3(un87_df),
.I4(un32_reg0_s_13),
.I5(un11_reg0_s_13),
.O(N_1732)
);
defparam \d_cnst_sn.reg3_17_2[13] .INIT=64'hFFFFEFFF10000000;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_0[17] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[16]),
.I4(reg3_1_1[17]),
.I5(t_1[17]),
.LO(N_1084)
);
defparam \d_cnst_sn.reg0_28_0[17] .INIT=64'hFDDD2000FFDF2202;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[0] (
.I0(datai[0]),
.I1(m_2[0]),
.I2(N_1035),
.I3(un1_cf),
.I4(N_1810),
.O(N_1812)
);
defparam \d_cnst_sn.reg3_17_5[0] .INIT=32'hCCAA0F0F;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_2[22] (
.I0(N_7_i),
.I1(un36_df),
.I2(un1_b59),
.I3(un87_df),
.I4(un32_reg0_s_22),
.I5(un11_reg0_s_22),
.LO(N_1741)
);
defparam \d_cnst_sn.reg3_17_2[22] .INIT=64'hFFFFEFFF10000000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_2[21] (
.I0(N_7_i),
.I1(un36_df),
.I2(un1_b59),
.I3(un87_df),
.I4(un32_reg0_s_21),
.I5(un11_reg0_s_21),
.LO(N_1740)
);
defparam \d_cnst_sn.reg3_17_2[21] .INIT=64'hFFFFEFFF10000000;
// @7:97
MUXCY_L un3_t_cry_0_cy_cZ (
.DI(GND),
.CI(VCC),
.S(r_4_3_ci[31]),
.LO(un3_t_cry_0_cy)
);
// @7:97
LUT6 \d_cnst_sn.r_4_3_ci[31] (
.I0(reg0[31]),
.I1(reg1[31]),
.I2(reg2[31]),
.I3(inf_abs0_2[31]),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.O(r_4_3_ci[31])
);
defparam \d_cnst_sn.r_4_3_ci[31] .INIT=64'hAA00AAF0AACCAAAA;
// @7:466
MUXCY_L t_1_cry_0_cy_cZ (
.DI(GND),
.CI(VCC),
.S(r_4_i[31]),
.LO(t_1_cry_0_cy)
);
LUT5 \d_cnst_sn.m27 (
.I0(reg0[2]),
.I1(reg2[2]),
.I2(inf_abs0_2[31]),
.I3(\d_cnst_sn.m19_0_1 ),
.I4(\d_cnst_sn.m26_0_1 ),
.O(N_28)
);
defparam \d_cnst_sn.m27 .INIT=32'hACA0AFAA;
// @7:466
LUT5 un3_t_axb_2_cZ (
.I0(reg0[2]),
.I1(reg2[2]),
.I2(inf_abs0_2[31]),
.I3(\d_cnst_sn.m19_0_1 ),
.I4(\d_cnst_sn.m26_0_1 ),
.O(un3_t_axb_2)
);
defparam un3_t_axb_2_cZ.INIT=32'h535F5055;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_14 (
.I0(inf_abs0_2[31]),
.I1(\d_cnst_sn.reg0_28_14_2135_1_a0_2 ),
.I2(reg3_1_1[30]),
.I3(\d_cnst_sn.reg0_28_14_0 ),
.I4(t_1[30]),
.LO(N_3550)
);
defparam \d_cnst_sn.reg0_28_14 .INIT=32'hFFA0FFEC;
// @7:103
LUT4 \d_cnst_sn.reg3_17_6_tz[21] (
.I0(m_2[21]),
.I1(\d_cnst_sn.reg3_17_a2_2_0 [21]),
.I2(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I3(reg3_14_sqmuxa),
.O(\d_cnst_sn.reg3_17_0_tz [21])
);
defparam \d_cnst_sn.reg3_17_6_tz[21] .INIT=16'hC00A;
// @7:74
LUT5_L \d_cnst_sn.reg0_28_6_RNIBQPU4[17] (
.I0(N_3916),
.I1(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I2(\d_cnst_sn.reg0_0 [17]),
.I3(t_1[17]),
.I4(N_1052),
.LO(reg0_28[17])
);
defparam \d_cnst_sn.reg0_28_6_RNIBQPU4[17] .INIT=32'hB0F01050;
// @7:74
LUT5_L \d_cnst_sn.reg0_28_6_RNIGTPU4[18] (
.I0(N_3916),
.I1(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I2(\d_cnst_sn.reg1_0 [18]),
.I3(t_1[18]),
.I4(N_1053),
.LO(reg1_16[18])
);
defparam \d_cnst_sn.reg0_28_6_RNIGTPU4[18] .INIT=32'hB0F01050;
// @7:74
LUT1_L \state_RNO[0] (
.I0(state[0]),
.LO(state_i[0])
);
defparam \state_RNO[0] .INIT=2'h1;
// @7:74
LUT2 un1_inf_abs0_0_s_19_RNO (
.I0(reg1[19]),
.I1(inf_abs0_2[19]),
.O(un1_inf_abs0_0_axb_19)
);
defparam un1_inf_abs0_0_s_19_RNO.INIT=4'h6;
// @7:74
LUT2 un1_inf_abs0_s_19_RNO (
.I0(reg2[19]),
.I1(inf_abs0_2[19]),
.O(un1_inf_abs0_axb_19)
);
defparam un1_inf_abs0_s_19_RNO.INIT=4'h6;
LUT2 \d_cnst_sn.m2 (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[30]),
.O(N_3_0)
);
defparam \d_cnst_sn.m2 .INIT=4'h4;
// @7:74
LUT3_L \d_cnst_sn.ir_3[8] (
.I0(datai[8]),
.I1(state[0]),
.I2(inf_abs0_2[8]),
.LO(ir_3[8])
);
defparam \d_cnst_sn.ir_3[8] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[16] (
.I0(datai[16]),
.I1(state[0]),
.I2(inf_abs0_2[16]),
.LO(ir_3[16])
);
defparam \d_cnst_sn.ir_3[16] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[3] (
.I0(datai[3]),
.I1(state[0]),
.I2(inf_abs0_2[3]),
.LO(ir_3[3])
);
defparam \d_cnst_sn.ir_3[3] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[0] (
.I0(datai[0]),
.I1(state[0]),
.I2(inf_abs0_2[0]),
.LO(ir_3[0])
);
defparam \d_cnst_sn.ir_3[0] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[27] (
.I0(datai[27]),
.I1(state[0]),
.I2(inf_abs0_2[27]),
.LO(ir_3[27])
);
defparam \d_cnst_sn.ir_3[27] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[23] (
.I0(datai[23]),
.I1(state[0]),
.I2(inf_abs0_2[23]),
.LO(ir_3[23])
);
defparam \d_cnst_sn.ir_3[23] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[26] (
.I0(datai[26]),
.I1(state[0]),
.I2(inf_abs0_2[26]),
.LO(ir_3[26])
);
defparam \d_cnst_sn.ir_3[26] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[5] (
.I0(datai[5]),
.I1(state[0]),
.I2(inf_abs0_2[5]),
.LO(ir_3[5])
);
defparam \d_cnst_sn.ir_3[5] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[2] (
.I0(datai[2]),
.I1(state[0]),
.I2(inf_abs0_2[2]),
.LO(ir_3[2])
);
defparam \d_cnst_sn.ir_3[2] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[18] (
.I0(datai[18]),
.I1(state[0]),
.I2(inf_abs0_2[18]),
.LO(ir_3[18])
);
defparam \d_cnst_sn.ir_3[18] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[19] (
.I0(datai[19]),
.I1(state[0]),
.I2(inf_abs0_2[19]),
.LO(ir_3[19])
);
defparam \d_cnst_sn.ir_3[19] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[10] (
.I0(datai[10]),
.I1(state[0]),
.I2(inf_abs0_2[10]),
.LO(ir_3[10])
);
defparam \d_cnst_sn.ir_3[10] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[9] (
.I0(datai[9]),
.I1(state[0]),
.I2(inf_abs0_2[9]),
.LO(ir_3[9])
);
defparam \d_cnst_sn.ir_3[9] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[6] (
.I0(datai[6]),
.I1(state[0]),
.I2(inf_abs0_2[6]),
.LO(ir_3[6])
);
defparam \d_cnst_sn.ir_3[6] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[4] (
.I0(datai[4]),
.I1(state[0]),
.I2(inf_abs0_2[4]),
.LO(ir_3[4])
);
defparam \d_cnst_sn.ir_3[4] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[22] (
.I0(datai[22]),
.I1(state[0]),
.I2(inf_abs0_2[22]),
.LO(ir_3[22])
);
defparam \d_cnst_sn.ir_3[22] .INIT=8'hE2;
// @7:47
LUT3 \d_cnst_sn.r_4_3_21_1130_i_m4 (
.I0(reg1[19]),
.I1(un3_reg3_s_16),
.I2(inf_abs0_2[30]),
.O(N_2722)
);
defparam \d_cnst_sn.r_4_3_21_1130_i_m4 .INIT=8'hCA;
// @7:74
LUT3_L \d_cnst_sn.ir_3[21] (
.I0(datai[21]),
.I1(state[0]),
.I2(inf_abs0_2[21]),
.LO(ir_3[21])
);
defparam \d_cnst_sn.ir_3[21] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[1] (
.I0(datai[1]),
.I1(state[0]),
.I2(inf_abs0_2[1]),
.LO(ir_3[1])
);
defparam \d_cnst_sn.ir_3[1] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[7] (
.I0(datai[7]),
.I1(state[0]),
.I2(inf_abs0_2[7]),
.LO(ir_3[7])
);
defparam \d_cnst_sn.ir_3[7] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[25] (
.I0(datai[25]),
.I1(state[0]),
.I2(inf_abs0_2[25]),
.LO(ir_3[25])
);
defparam \d_cnst_sn.ir_3[25] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[24] (
.I0(datai[24]),
.I1(state[0]),
.I2(inf_abs0_2[24]),
.LO(ir_3[24])
);
defparam \d_cnst_sn.ir_3[24] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[29] (
.I0(datai[29]),
.I1(state[0]),
.I2(inf_abs0_2[29]),
.LO(ir_3[29])
);
defparam \d_cnst_sn.ir_3[29] .INIT=8'hE2;
// @7:74
LUT3_L \d_cnst_sn.ir_3[11] (
.I0(datai[11]),
.I1(state[0]),
.I2(inf_abs0_2[11]),
.LO(ir_3[11])
);
defparam \d_cnst_sn.ir_3[11] .INIT=8'hE2;
// @7:97
LUT3 \d_cnst_sn.r_4_2_a0[0] (
.I0(reg3[0]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[30]),
.O(r_4_2_a0[0])
);
defparam \d_cnst_sn.r_4_2_a0[0] .INIT=8'h10;
// @7:97
LUT3 \d_cnst_sn.r_4_2_a0[1] (
.I0(reg3[1]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[30]),
.O(r_4_2_a0[1])
);
defparam \d_cnst_sn.r_4_2_a0[1] .INIT=8'h10;
// @7:97
LUT3 \d_cnst_sn.r_4_0_0_0[0] (
.I0(reg1[0]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[30]),
.O(\d_cnst_sn.r_4_0_0 [0])
);
defparam \d_cnst_sn.r_4_0_0_0[0] .INIT=8'hBA;
// @7:97
LUT3 \d_cnst_sn.r_4_0_0_cZ[1] (
.I0(reg1[1]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[30]),
.O(\d_cnst_sn.r_4_0_0 [1])
);
defparam \d_cnst_sn.r_4_0_0_cZ[1] .INIT=8'hBA;
// @7:106
LUT3 \d_cnst_sn.m7_0 (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.O(m7)
);
defparam \d_cnst_sn.m7_0 .INIT=8'hAB;
// @7:83
LUT2 inf_abs0_2_axb_30_cZ (
.I0(ir[30]),
.I1(ir[31]),
.O(inf_abs0_2_axb_30)
);
defparam inf_abs0_2_axb_30_cZ.INIT=4'h6;
// @7:92
LUT2 \un9_cf_1.SUM0 (
.I0(inf_abs0_2[23]),
.I1(inf_abs0_2[31]),
.O(N_7_i)
);
defparam \un9_cf_1.SUM0 .INIT=4'h2;
LUT2 \d_cnst_sn.m12 (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.O(N_13)
);
defparam \d_cnst_sn.m12 .INIT=4'hB;
// @7:90
LUT2 \d_cnst_sn.SUM3 (
.I0(inf_abs0_2[22]),
.I1(inf_abs0_2[31]),
.O(N_514_i)
);
defparam \d_cnst_sn.SUM3 .INIT=4'h2;
// @7:90
LUT2 \d_cnst_sn.SUM2_0 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.O(N_513_i)
);
defparam \d_cnst_sn.SUM2_0 .INIT=4'h2;
// @7:97
LUT4 \d_cnst_sn.r_4_1[11] (
.I0(reg0[11]),
.I1(reg2[11]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_926)
);
defparam \d_cnst_sn.r_4_1[11] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[26] (
.I0(reg0[26]),
.I1(reg2[26]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_941)
);
defparam \d_cnst_sn.r_4_1[26] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[11] (
.I0(reg1[11]),
.I1(un3_reg3_s_8),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_958)
);
defparam \d_cnst_sn.r_4_2[11] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[26] (
.I0(reg1[26]),
.I1(un3_reg3_s_23),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_973)
);
defparam \d_cnst_sn.r_4_2[26] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[28] (
.I0(reg0[28]),
.I1(reg2[28]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_943)
);
defparam \d_cnst_sn.r_4_1[28] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[28] (
.I0(reg1[28]),
.I1(un3_reg3_s_25),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_975)
);
defparam \d_cnst_sn.r_4_2[28] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[25] (
.I0(reg0[25]),
.I1(reg2[25]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_940)
);
defparam \d_cnst_sn.r_4_1[25] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[25] (
.I0(reg1[25]),
.I1(un3_reg3_s_22),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_972)
);
defparam \d_cnst_sn.r_4_2[25] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[13] (
.I0(reg0[13]),
.I1(reg2[13]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_928)
);
defparam \d_cnst_sn.r_4_1[13] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[13] (
.I0(reg1[13]),
.I1(un3_reg3_s_10),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_960)
);
defparam \d_cnst_sn.r_4_2[13] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[16] (
.I0(reg0[16]),
.I1(reg2[16]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_931)
);
defparam \d_cnst_sn.r_4_1[16] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[16] (
.I0(reg1[16]),
.I1(un3_reg3_s_13),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_963)
);
defparam \d_cnst_sn.r_4_2[16] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[14] (
.I0(reg0[14]),
.I1(reg2[14]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_929)
);
defparam \d_cnst_sn.r_4_1[14] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[14] (
.I0(reg1[14]),
.I1(un3_reg3_s_11),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_961)
);
defparam \d_cnst_sn.r_4_2[14] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[10] (
.I0(reg0[10]),
.I1(reg2[10]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_925)
);
defparam \d_cnst_sn.r_4_1[10] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[10] (
.I0(reg1[10]),
.I1(un3_reg3_s_7),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_957)
);
defparam \d_cnst_sn.r_4_2[10] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[9] (
.I0(reg0[9]),
.I1(reg2[9]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_924)
);
defparam \d_cnst_sn.r_4_1[9] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[9] (
.I0(reg1[9]),
.I1(un3_reg3_s_6),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_956)
);
defparam \d_cnst_sn.r_4_2[9] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[7] (
.I0(reg0[7]),
.I1(reg2[7]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_922)
);
defparam \d_cnst_sn.r_4_1[7] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[8] (
.I0(reg0[8]),
.I1(reg2[8]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_923)
);
defparam \d_cnst_sn.r_4_1[8] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[7] (
.I0(reg1[7]),
.I1(un3_reg3_s_4),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_954)
);
defparam \d_cnst_sn.r_4_2[7] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[8] (
.I0(reg1[8]),
.I1(un3_reg3_s_5),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_955)
);
defparam \d_cnst_sn.r_4_2[8] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[21] (
.I0(reg0[21]),
.I1(reg2[21]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_936)
);
defparam \d_cnst_sn.r_4_1[21] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[21] (
.I0(reg1[21]),
.I1(un3_reg3_s_18),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_968)
);
defparam \d_cnst_sn.r_4_2[21] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[20] (
.I0(reg0[20]),
.I1(reg2[20]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_935)
);
defparam \d_cnst_sn.r_4_1[20] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[20] (
.I0(reg1[20]),
.I1(un3_reg3_s_17),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_967)
);
defparam \d_cnst_sn.r_4_2[20] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[15] (
.I0(reg0[15]),
.I1(reg2[15]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_930)
);
defparam \d_cnst_sn.r_4_1[15] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[17] (
.I0(reg0[17]),
.I1(reg2[17]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_932)
);
defparam \d_cnst_sn.r_4_1[17] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[15] (
.I0(reg1[15]),
.I1(un3_reg3_s_12),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_962)
);
defparam \d_cnst_sn.r_4_2[15] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[17] (
.I0(reg1[17]),
.I1(un3_reg3_s_14),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_964)
);
defparam \d_cnst_sn.r_4_2[17] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[5] (
.I0(reg0[5]),
.I1(reg2[5]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_920)
);
defparam \d_cnst_sn.r_4_1[5] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[5] (
.I0(reg1[5]),
.I1(un3_reg3_s_2),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_952)
);
defparam \d_cnst_sn.r_4_2[5] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[27] (
.I0(reg0[27]),
.I1(reg2[27]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_942)
);
defparam \d_cnst_sn.r_4_1[27] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[27] (
.I0(reg1[27]),
.I1(un3_reg3_s_24),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_974)
);
defparam \d_cnst_sn.r_4_2[27] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[18] (
.I0(reg0[18]),
.I1(reg2[18]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_933)
);
defparam \d_cnst_sn.r_4_1[18] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[18] (
.I0(reg1[18]),
.I1(un3_reg3_s_15),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_965)
);
defparam \d_cnst_sn.r_4_2[18] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[22] (
.I0(reg0[22]),
.I1(reg2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_937)
);
defparam \d_cnst_sn.r_4_1[22] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[22] (
.I0(reg1[22]),
.I1(un3_reg3_s_19),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_969)
);
defparam \d_cnst_sn.r_4_2[22] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[12] (
.I0(reg0[12]),
.I1(reg2[12]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_927)
);
defparam \d_cnst_sn.r_4_1[12] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[12] (
.I0(reg1[12]),
.I1(un3_reg3_s_9),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_959)
);
defparam \d_cnst_sn.r_4_2[12] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[6] (
.I0(reg0[6]),
.I1(reg2[6]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_921)
);
defparam \d_cnst_sn.r_4_1[6] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[6] (
.I0(reg1[6]),
.I1(un3_reg3_s_3),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_953)
);
defparam \d_cnst_sn.r_4_2[6] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[19] (
.I0(reg0[19]),
.I1(reg2[19]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_934)
);
defparam \d_cnst_sn.r_4_1[19] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[23] (
.I0(reg1[23]),
.I1(un3_reg3_s_20),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_970)
);
defparam \d_cnst_sn.r_4_2[23] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[23] (
.I0(reg0[23]),
.I1(reg2[23]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_938)
);
defparam \d_cnst_sn.r_4_1[23] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_2[24] (
.I0(reg1[24]),
.I1(un3_reg3_s_21),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_971)
);
defparam \d_cnst_sn.r_4_2[24] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4_1[24] (
.I0(reg0[24]),
.I1(reg2[24]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_939)
);
defparam \d_cnst_sn.r_4_1[24] .INIT=16'hACAA;
LUT4 \d_cnst_sn.m19_0_1_cZ (
.I0(reg1[2]),
.I1(reg3[2]),
.I2(inf_abs0_2[29]),
.I3(inf_abs0_2[30]),
.O(\d_cnst_sn.m19_0_1 )
);
defparam \d_cnst_sn.m19_0_1_cZ .INIT=16'hCFA0;
LUT4 \d_cnst_sn.m26_0_1_cZ (
.I0(reg1[2]),
.I1(reg3[2]),
.I2(inf_abs0_2[29]),
.I3(inf_abs0_2[30]),
.O(\d_cnst_sn.m26_0_1 )
);
defparam \d_cnst_sn.m26_0_1_cZ .INIT=16'h3F50;
// @7:97
LUT4 \d_cnst_sn.r_4_0_0_0[3] (
.I0(reg1[3]),
.I1(reg3[3]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(\d_cnst_sn.r_4_0_0 [3])
);
defparam \d_cnst_sn.r_4_0_0_0[3] .INIT=16'hA3AF;
// @7:97
LUT4 \d_cnst_sn.r_4_0_0_0[4] (
.I0(reg1[4]),
.I1(un3_reg3_s_1),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(\d_cnst_sn.r_4_0_0 [4])
);
defparam \d_cnst_sn.r_4_0_0_0[4] .INIT=16'hACAF;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_26 (
.I0(m_2[22]),
.I1(m_2[23]),
.I2(m_2[21]),
.I3(r_4[21]),
.I4(r_4[23]),
.I5(r_4[22]),
.O(un14_r_0_N_56)
);
defparam \d_cnst_sn.un14_r_0_I_26 .INIT=64'h8008200240041001;
// @7:47
LUT5 \d_cnst_sn.addr_20_iv_0_1025_i_a6_3 (
.I0(state[0]),
.I1(inf_abs0_2[24]),
.I2(inf_abs0_2[23]),
.I3(inf_abs0_2[25]),
.I4(inf_abs0_2[26]),
.O(N_2641)
);
defparam \d_cnst_sn.addr_20_iv_0_1025_i_a6_3 .INIT=32'h08000000;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_50 (
.I0(m_2[24]),
.I1(m_2[25]),
.I2(m_2[26]),
.I3(r_4[24]),
.I4(r_4[25]),
.I5(r_4[26]),
.O(un14_r_0_N_35)
);
defparam \d_cnst_sn.un14_r_0_I_50 .INIT=64'h8040201008040201;
// @7:97
LUT4 \d_cnst_sn.r_4[0] (
.I0(reg0[0]),
.I1(reg2[0]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_915)
);
defparam \d_cnst_sn.r_4[0] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4[1] (
.I0(reg0[1]),
.I1(reg2[1]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_916)
);
defparam \d_cnst_sn.r_4[1] .INIT=16'hACAA;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_6_1508_i_m2 (
.I0(reg0[29]),
.I1(reg1[29]),
.I2(reg2[29]),
.I3(un3_reg3_cry_25),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_6_1508_i_m2)
);
defparam \d_cnst_sn.r_4_3_6_1508_i_m2 .INIT=64'hFF00F0F0CCCCAAAA;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_5_1534_i_m2 (
.I0(reg1[28]),
.I1(reg0[28]),
.I2(reg2[28]),
.I3(un3_reg3_s_25),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_5_1534_i_m2)
);
defparam \d_cnst_sn.r_4_3_5_1534_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_1_1638_i_m2 (
.I0(reg0[24]),
.I1(reg2[24]),
.I2(reg1[24]),
.I3(un3_reg3_s_21),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_1_1638_i_m2)
);
defparam \d_cnst_sn.r_4_3_1_1638_i_m2 .INIT=64'hFF00CCCCF0F0AAAA;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_18_1208_i_m2 (
.I0(reg1[16]),
.I1(reg0[16]),
.I2(reg2[16]),
.I3(un3_reg3_s_13),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_18_1208_i_m2)
);
defparam \d_cnst_sn.r_4_3_18_1208_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_15_1286_i_m2 (
.I0(reg1[13]),
.I1(reg0[13]),
.I2(reg2[13]),
.I3(un3_reg3_s_10),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_15_1286_i_m2)
);
defparam \d_cnst_sn.r_4_3_15_1286_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_13_1338_i_m2 (
.I0(reg1[11]),
.I1(reg0[11]),
.I2(reg2[11]),
.I3(un3_reg3_s_8),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_13_1338_i_m2)
);
defparam \d_cnst_sn.r_4_3_13_1338_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_19_1182_i_m2 (
.I0(reg1[17]),
.I1(reg0[17]),
.I2(reg2[17]),
.I3(un3_reg3_s_14),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_19_1182_i_m2)
);
defparam \d_cnst_sn.r_4_3_19_1182_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_14_1312_i_m2 (
.I0(reg1[12]),
.I1(reg0[12]),
.I2(reg2[12]),
.I3(un3_reg3_s_9),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_14_1312_i_m2)
);
defparam \d_cnst_sn.r_4_3_14_1312_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_12_1364_i_m2 (
.I0(reg1[10]),
.I1(reg0[10]),
.I2(reg2[10]),
.I3(un3_reg3_s_7),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_12_1364_i_m2)
);
defparam \d_cnst_sn.r_4_3_12_1364_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_3_1586_i_m2 (
.I0(reg1[26]),
.I1(reg0[26]),
.I2(reg2[26]),
.I3(un3_reg3_s_23),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_3_1586_i_m2)
);
defparam \d_cnst_sn.r_4_3_3_1586_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_16_1260_i_m2 (
.I0(reg1[14]),
.I1(reg0[14]),
.I2(reg2[14]),
.I3(un3_reg3_s_11),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_16_1260_i_m2)
);
defparam \d_cnst_sn.r_4_3_16_1260_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_11_1390_i_m2 (
.I0(reg1[9]),
.I1(reg0[9]),
.I2(reg2[9]),
.I3(un3_reg3_s_6),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_11_1390_i_m2)
);
defparam \d_cnst_sn.r_4_3_11_1390_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_30_680_i_m2 (
.I0(reg1[6]),
.I1(reg0[6]),
.I2(reg2[6]),
.I3(un3_reg3_s_3),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_30_680_i_m2)
);
defparam \d_cnst_sn.r_4_3_30_680_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_10_1416_i_m2 (
.I0(reg1[8]),
.I1(reg0[8]),
.I2(reg2[8]),
.I3(un3_reg3_s_5),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_10_1416_i_m2)
);
defparam \d_cnst_sn.r_4_3_10_1416_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_9_1442_i_m2 (
.I0(reg1[7]),
.I1(reg0[7]),
.I2(reg2[7]),
.I3(un3_reg3_s_4),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_9_1442_i_m2)
);
defparam \d_cnst_sn.r_4_3_9_1442_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_0_1664_i_m2 (
.I0(reg0[23]),
.I1(reg2[23]),
.I2(reg1[23]),
.I3(un3_reg3_s_20),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_0_1664_i_m2)
);
defparam \d_cnst_sn.r_4_3_0_1664_i_m2 .INIT=64'hFF00CCCCF0F0AAAA;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_22_1104_i_m2 (
.I0(reg0[20]),
.I1(reg2[20]),
.I2(reg1[20]),
.I3(un3_reg3_s_17),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_22_1104_i_m2)
);
defparam \d_cnst_sn.r_4_3_22_1104_i_m2 .INIT=64'hFF00CCCCF0F0AAAA;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_25_810_i_m2 (
.I0(reg0[1]),
.I1(reg2[1]),
.I2(reg1[1]),
.I3(reg3[1]),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_25_810_i_m2)
);
defparam \d_cnst_sn.r_4_3_25_810_i_m2 .INIT=64'hFF00CCCCF0F0AAAA;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_17_1234_i_m2 (
.I0(reg1[15]),
.I1(reg0[15]),
.I2(reg2[15]),
.I3(un3_reg3_s_12),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_17_1234_i_m2)
);
defparam \d_cnst_sn.r_4_3_17_1234_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_29_706_i_m2 (
.I0(reg1[5]),
.I1(reg0[5]),
.I2(reg2[5]),
.I3(un3_reg3_s_2),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_29_706_i_m2)
);
defparam \d_cnst_sn.r_4_3_29_706_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_24_836_i_m2 (
.I0(reg0[0]),
.I1(reg2[0]),
.I2(reg1[0]),
.I3(reg3[0]),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_24_836_i_m2)
);
defparam \d_cnst_sn.r_4_3_24_836_i_m2 .INIT=64'hFF00CCCCF0F0AAAA;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_4_1560_i_m2 (
.I0(reg0[27]),
.I1(reg2[27]),
.I2(reg1[27]),
.I3(un3_reg3_s_24),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_4_1560_i_m2)
);
defparam \d_cnst_sn.r_4_3_4_1560_i_m2 .INIT=64'hFF00CCCCF0F0AAAA;
// @7:105
LUT4 \d_cnst_sn.m_2[29] (
.I0(datai[29]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[29])
);
defparam \d_cnst_sn.m_2[29] .INIT=16'h2220;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_20_1156_i_m2 (
.I0(reg1[18]),
.I1(reg0[18]),
.I2(reg2[18]),
.I3(un3_reg3_s_15),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_20_1156_i_m2)
);
defparam \d_cnst_sn.r_4_3_20_1156_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_1690_i_m2 (
.I0(reg0[22]),
.I1(reg2[22]),
.I2(reg1[22]),
.I3(un3_reg3_s_19),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_1690_i_m2)
);
defparam \d_cnst_sn.r_4_3_1690_i_m2 .INIT=64'hFF00CCCCF0F0AAAA;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_28_732_i_m2 (
.I0(reg0[4]),
.I1(reg2[4]),
.I2(reg1[4]),
.I3(un3_reg3_s_1),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_28_732_i_m2)
);
defparam \d_cnst_sn.r_4_3_28_732_i_m2 .INIT=64'hFF00CCCCF0F0AAAA;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_2_1612_i_m2 (
.I0(reg1[25]),
.I1(reg0[25]),
.I2(reg2[25]),
.I3(un3_reg3_s_22),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_2_1612_i_m2)
);
defparam \d_cnst_sn.r_4_3_2_1612_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_23_1078_i_m2 (
.I0(reg1[21]),
.I1(reg0[21]),
.I2(reg2[21]),
.I3(un3_reg3_s_18),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_23_1078_i_m2)
);
defparam \d_cnst_sn.r_4_3_23_1078_i_m2 .INIT=64'hFF00F0F0AAAACCCC;
// @7:47
LUT6_L \d_cnst_sn.r_4_3_27_758_i_m2 (
.I0(reg0[3]),
.I1(reg2[3]),
.I2(reg1[3]),
.I3(reg3[3]),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(r_4_3_27_758_i_m2)
);
defparam \d_cnst_sn.r_4_3_27_758_i_m2 .INIT=64'h00FFCCCCF0F0AAAA;
// @7:227
LUT3 \d_cnst_sn.un1_reg0_0_sqmuxa_1_i_o4 (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[31]),
.O(N_1901)
);
defparam \d_cnst_sn.un1_reg0_0_sqmuxa_1_i_o4 .INIT=8'h0E;
// @7:105
LUT5 \d_cnst_sn.m_2[5] (
.I0(datai[5]),
.I1(inf_abs0_2[5]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[5])
);
defparam \d_cnst_sn.m_2[5] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[8] (
.I0(datai[8]),
.I1(inf_abs0_2[8]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[8])
);
defparam \d_cnst_sn.m_2[8] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[15] (
.I0(datai[15]),
.I1(inf_abs0_2[15]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[15])
);
defparam \d_cnst_sn.m_2[15] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[16] (
.I0(datai[16]),
.I1(inf_abs0_2[16]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[16])
);
defparam \d_cnst_sn.m_2[16] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[3] (
.I0(datai[3]),
.I1(inf_abs0_2[3]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[3])
);
defparam \d_cnst_sn.m_2[3] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[1] (
.I0(datai[1]),
.I1(inf_abs0_2[1]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[1])
);
defparam \d_cnst_sn.m_2[1] .INIT=32'hCACACACC;
// @7:47
LUT5_L \d_cnst_sn.r_4_3_8_1467 (
.I0(reg0[31]),
.I1(reg1[31]),
.I2(reg2[31]),
.I3(inf_abs0_2[29]),
.I4(inf_abs0_2[30]),
.LO(r_4_3_8_1467)
);
defparam \d_cnst_sn.r_4_3_8_1467 .INIT=32'h00F0CCAA;
// @7:105
LUT5 \d_cnst_sn.m_2[13] (
.I0(datai[13]),
.I1(inf_abs0_2[13]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[13])
);
defparam \d_cnst_sn.m_2[13] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[19] (
.I0(datai[19]),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[19])
);
defparam \d_cnst_sn.m_2[19] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[14] (
.I0(datai[14]),
.I1(inf_abs0_2[14]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[14])
);
defparam \d_cnst_sn.m_2[14] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[18] (
.I0(datai[18]),
.I1(inf_abs0_2[18]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[18])
);
defparam \d_cnst_sn.m_2[18] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[12] (
.I0(datai[12]),
.I1(inf_abs0_2[12]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[12])
);
defparam \d_cnst_sn.m_2[12] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[17] (
.I0(datai[17]),
.I1(inf_abs0_2[17]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[17])
);
defparam \d_cnst_sn.m_2[17] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[10] (
.I0(datai[10]),
.I1(inf_abs0_2[10]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[10])
);
defparam \d_cnst_sn.m_2[10] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[11] (
.I0(datai[11]),
.I1(inf_abs0_2[11]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[11])
);
defparam \d_cnst_sn.m_2[11] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[9] (
.I0(datai[9]),
.I1(inf_abs0_2[9]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[9])
);
defparam \d_cnst_sn.m_2[9] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[2] (
.I0(datai[2]),
.I1(inf_abs0_2[2]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[2])
);
defparam \d_cnst_sn.m_2[2] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[6] (
.I0(datai[6]),
.I1(inf_abs0_2[6]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[6])
);
defparam \d_cnst_sn.m_2[6] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[7] (
.I0(datai[7]),
.I1(inf_abs0_2[7]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[7])
);
defparam \d_cnst_sn.m_2[7] .INIT=32'hCACACACC;
// @7:105
LUT5 \d_cnst_sn.m_2[4] (
.I0(datai[4]),
.I1(inf_abs0_2[4]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[4])
);
defparam \d_cnst_sn.m_2[4] .INIT=32'hCACACACC;
// @7:47
LUT5_L \d_cnst_sn.addr_20_iv_18_335_i_1_cZ (
.I0(reg3[11]),
.I1(state[0]),
.I2(inf_abs0_2[11]),
.I3(inf_abs0_2[28]),
.I4(N_2641),
.LO(\d_cnst_sn.addr_20_iv_18_335_i_1 )
);
defparam \d_cnst_sn.addr_20_iv_18_335_i_1_cZ .INIT=32'hFFFF111D;
// @7:47
LUT5_L \d_cnst_sn.addr_20_iv_13_470_i_1_cZ (
.I0(reg3[6]),
.I1(state[0]),
.I2(inf_abs0_2[6]),
.I3(inf_abs0_2[28]),
.I4(N_2641),
.LO(\d_cnst_sn.addr_20_iv_13_470_i_1 )
);
defparam \d_cnst_sn.addr_20_iv_13_470_i_1_cZ .INIT=32'hFFFF111D;
// @7:47
LUT5_L \d_cnst_sn.addr_20_iv_17_362_i_1_cZ (
.I0(reg3[10]),
.I1(state[0]),
.I2(inf_abs0_2[10]),
.I3(inf_abs0_2[28]),
.I4(N_2641),
.LO(\d_cnst_sn.addr_20_iv_17_362_i_1 )
);
defparam \d_cnst_sn.addr_20_iv_17_362_i_1_cZ .INIT=32'hFFFF111D;
// @7:47
LUT5_L \d_cnst_sn.addr_20_iv_15_416_i_1_cZ (
.I0(reg3[8]),
.I1(state[0]),
.I2(inf_abs0_2[8]),
.I3(inf_abs0_2[28]),
.I4(N_2641),
.LO(\d_cnst_sn.addr_20_iv_15_416_i_1 )
);
defparam \d_cnst_sn.addr_20_iv_15_416_i_1_cZ .INIT=32'hFFFF111D;
// @7:47
LUT5_L \d_cnst_sn.addr_20_iv_10_562_i_1_cZ (
.I0(reg3[3]),
.I1(state[0]),
.I2(inf_abs0_2[3]),
.I3(inf_abs0_2[28]),
.I4(N_2641),
.LO(\d_cnst_sn.addr_20_iv_10_562_i_1 )
);
defparam \d_cnst_sn.addr_20_iv_10_562_i_1_cZ .INIT=32'hFFFF111D;
// @7:47
LUT5_L \d_cnst_sn.addr_20_iv_12_497_i_1_cZ (
.I0(reg3[5]),
.I1(state[0]),
.I2(inf_abs0_2[5]),
.I3(inf_abs0_2[28]),
.I4(N_2641),
.LO(\d_cnst_sn.addr_20_iv_12_497_i_1 )
);
defparam \d_cnst_sn.addr_20_iv_12_497_i_1_cZ .INIT=32'hFFFF111D;
// @7:47
LUT5_L \d_cnst_sn.addr_20_iv_16_389_i_1_cZ (
.I0(reg3[9]),
.I1(state[0]),
.I2(inf_abs0_2[9]),
.I3(inf_abs0_2[28]),
.I4(N_2641),
.LO(\d_cnst_sn.addr_20_iv_16_389_i_1 )
);
defparam \d_cnst_sn.addr_20_iv_16_389_i_1_cZ .INIT=32'hFFFF111D;
// @7:47
LUT6 \d_cnst_sn.addr_20_iv_8_627_i_1_cZ (
.I0(reg3[1]),
.I1(state[0]),
.I2(inf_abs0_2[1]),
.I3(un1_inf_abs0_11[1]),
.I4(inf_abs0_2[27]),
.I5(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_8_627_i_1 )
);
defparam \d_cnst_sn.addr_20_iv_8_627_i_1_cZ .INIT=64'h111111DD1D1D1DDD;
// @7:97
LUT4 \d_cnst_sn.r_4[4] (
.I0(reg0[4]),
.I1(reg2[4]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_919)
);
defparam \d_cnst_sn.r_4[4] .INIT=16'hACAA;
// @7:97
LUT4 \d_cnst_sn.r_4[3] (
.I0(reg0[3]),
.I1(reg2[3]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[30]),
.O(N_918)
);
defparam \d_cnst_sn.r_4[3] .INIT=16'hACAA;
// @7:74
LUT5 \d_cnst_sn.un1_state_1_1_o6_0 (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.O(N_1890)
);
defparam \d_cnst_sn.un1_state_1_1_o6_0 .INIT=32'hFFFFFFFD;
// @7:74
LUT4 \d_cnst_sn.un36_df (
.I0(inf_abs0_2[24]),
.I1(inf_abs0_2[25]),
.I2(inf_abs0_2[26]),
.I3(inf_abs0_2[31]),
.O(un36_df)
);
defparam \d_cnst_sn.un36_df .INIT=16'h0080;
// @7:105
LUT5 \d_cnst_sn.m[0] (
.I0(datai[0]),
.I1(inf_abs0_2[0]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(m_2[0])
);
defparam \d_cnst_sn.m[0] .INIT=32'hCACACACC;
// @7:47
LUT6 \d_cnst_sn.reg0_28_14_2135_a5_2 (
.I0(datai[30]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.I5(g0_2_0_i2_lut6_2_O6),
.O(N_3568)
);
defparam \d_cnst_sn.reg0_28_14_2135_a5_2 .INIT=64'h0000000000000008;
// @7:243
LUT4 reg3_1_1_axb_31_cZ (
.I0(datai[31]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(reg3_1_1_axb_31)
);
defparam reg3_1_1_axb_31_cZ.INIT=16'hDDDF;
// @7:97
LUT6 \d_cnst_sn.r_4_3[29] (
.I0(reg0[29]),
.I1(reg1[29]),
.I2(reg2[29]),
.I3(un3_reg3_cry_25),
.I4(N_3_0),
.I5(N_13),
.O(r_4[29])
);
defparam \d_cnst_sn.r_4_3[29] .INIT=64'hF0F0AAAAFF00CCCC;
// @7:47
LUT6_L \d_cnst_sn.N_36_i (
.I0(reg0[2]),
.I1(reg1[2]),
.I2(reg2[2]),
.I3(reg3[2]),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.LO(N_36_i)
);
defparam \d_cnst_sn.N_36_i .INIT=64'hFF00F0F0CCCCAAAA;
// @7:318
LUT6 un11_reg0_axb_19_cZ (
.I0(datai[19]),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[19]),
.O(un11_reg0_axb_19)
);
defparam un11_reg0_axb_19_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_18_cZ (
.I0(datai[18]),
.I1(inf_abs0_2[18]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[18]),
.O(un11_reg0_axb_18)
);
defparam un11_reg0_axb_18_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_17_cZ (
.I0(datai[17]),
.I1(inf_abs0_2[17]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[17]),
.O(un11_reg0_axb_17)
);
defparam un11_reg0_axb_17_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_16_cZ (
.I0(datai[16]),
.I1(inf_abs0_2[16]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[16]),
.O(un11_reg0_axb_16)
);
defparam un11_reg0_axb_16_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_15_cZ (
.I0(datai[15]),
.I1(inf_abs0_2[15]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[15]),
.O(un11_reg0_axb_15)
);
defparam un11_reg0_axb_15_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_14_cZ (
.I0(datai[14]),
.I1(inf_abs0_2[14]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[14]),
.O(un11_reg0_axb_14)
);
defparam un11_reg0_axb_14_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_13_cZ (
.I0(datai[13]),
.I1(inf_abs0_2[13]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[13]),
.O(un11_reg0_axb_13)
);
defparam un11_reg0_axb_13_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_12_cZ (
.I0(datai[12]),
.I1(inf_abs0_2[12]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[12]),
.O(un11_reg0_axb_12)
);
defparam un11_reg0_axb_12_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_11_cZ (
.I0(datai[11]),
.I1(inf_abs0_2[11]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[11]),
.O(un11_reg0_axb_11)
);
defparam un11_reg0_axb_11_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_10_cZ (
.I0(datai[10]),
.I1(inf_abs0_2[10]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[10]),
.O(un11_reg0_axb_10)
);
defparam un11_reg0_axb_10_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_9_cZ (
.I0(datai[9]),
.I1(inf_abs0_2[9]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[9]),
.O(un11_reg0_axb_9)
);
defparam un11_reg0_axb_9_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_8_cZ (
.I0(datai[8]),
.I1(inf_abs0_2[8]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[8]),
.O(un11_reg0_axb_8)
);
defparam un11_reg0_axb_8_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_7_cZ (
.I0(datai[7]),
.I1(inf_abs0_2[7]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[7]),
.O(un11_reg0_axb_7)
);
defparam un11_reg0_axb_7_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_6_cZ (
.I0(datai[6]),
.I1(inf_abs0_2[6]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[6]),
.O(un11_reg0_axb_6)
);
defparam un11_reg0_axb_6_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_5_cZ (
.I0(datai[5]),
.I1(inf_abs0_2[5]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[5]),
.O(un11_reg0_axb_5)
);
defparam un11_reg0_axb_5_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_4_cZ (
.I0(datai[4]),
.I1(inf_abs0_2[4]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[4]),
.O(un11_reg0_axb_4)
);
defparam un11_reg0_axb_4_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_3_cZ (
.I0(datai[3]),
.I1(inf_abs0_2[3]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[3]),
.O(un11_reg0_axb_3)
);
defparam un11_reg0_axb_3_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_2_cZ (
.I0(datai[2]),
.I1(inf_abs0_2[2]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(N_28),
.O(un11_reg0_axb_2)
);
defparam un11_reg0_axb_2_cZ.INIT=64'h35353533CACACACC;
// @7:318
LUT6 un11_reg0_axb_1_cZ (
.I0(datai[1]),
.I1(inf_abs0_2[1]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[1]),
.O(un11_reg0_axb_1)
);
defparam un11_reg0_axb_1_cZ.INIT=64'h35353533CACACACC;
// @7:243
LUT5 reg3_1_1_axb_19_cZ (
.I0(datai[19]),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_19)
);
defparam reg3_1_1_axb_19_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_18_cZ (
.I0(datai[18]),
.I1(inf_abs0_2[18]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_18)
);
defparam reg3_1_1_axb_18_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_17_cZ (
.I0(datai[17]),
.I1(inf_abs0_2[17]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_17)
);
defparam reg3_1_1_axb_17_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_16_cZ (
.I0(datai[16]),
.I1(inf_abs0_2[16]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_16)
);
defparam reg3_1_1_axb_16_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_15_cZ (
.I0(datai[15]),
.I1(inf_abs0_2[15]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_15)
);
defparam reg3_1_1_axb_15_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_14_cZ (
.I0(datai[14]),
.I1(inf_abs0_2[14]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_14)
);
defparam reg3_1_1_axb_14_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_13_cZ (
.I0(datai[13]),
.I1(inf_abs0_2[13]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_13)
);
defparam reg3_1_1_axb_13_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_12_cZ (
.I0(datai[12]),
.I1(inf_abs0_2[12]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_12)
);
defparam reg3_1_1_axb_12_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_11_cZ (
.I0(datai[11]),
.I1(inf_abs0_2[11]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_11)
);
defparam reg3_1_1_axb_11_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_10_cZ (
.I0(datai[10]),
.I1(inf_abs0_2[10]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_10)
);
defparam reg3_1_1_axb_10_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_9_cZ (
.I0(datai[9]),
.I1(inf_abs0_2[9]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_9)
);
defparam reg3_1_1_axb_9_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_8_cZ (
.I0(datai[8]),
.I1(inf_abs0_2[8]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_8)
);
defparam reg3_1_1_axb_8_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_7_cZ (
.I0(datai[7]),
.I1(inf_abs0_2[7]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_7)
);
defparam reg3_1_1_axb_7_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_6_cZ (
.I0(datai[6]),
.I1(inf_abs0_2[6]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_6)
);
defparam reg3_1_1_axb_6_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_5_cZ (
.I0(datai[5]),
.I1(inf_abs0_2[5]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_5)
);
defparam reg3_1_1_axb_5_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_4_cZ (
.I0(datai[4]),
.I1(inf_abs0_2[4]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_4)
);
defparam reg3_1_1_axb_4_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_3_cZ (
.I0(datai[3]),
.I1(inf_abs0_2[3]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_3)
);
defparam reg3_1_1_axb_3_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_2_cZ (
.I0(datai[2]),
.I1(inf_abs0_2[2]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_2)
);
defparam reg3_1_1_axb_2_cZ.INIT=32'h35353533;
// @7:243
LUT5 reg3_1_1_axb_1_cZ (
.I0(datai[1]),
.I1(inf_abs0_2[1]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_1)
);
defparam reg3_1_1_axb_1_cZ.INIT=32'h35353533;
// @7:97
LUT6 \d_cnst_sn.r_4_3[31] (
.I0(reg0[31]),
.I1(reg1[31]),
.I2(reg2[31]),
.I3(inf_abs0_2[31]),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.O(r_4[31])
);
defparam \d_cnst_sn.r_4_3[31] .INIT=64'hAA00AAF0AACCAAAA;
// @7:213
LUT4 \d_cnst_sn.d_cnsts2 (
.I0(inf_abs0_2[24]),
.I1(inf_abs0_2[25]),
.I2(inf_abs0_2[26]),
.I3(inf_abs0_2[31]),
.O(d_cnst_sm0)
);
defparam \d_cnst_sn.d_cnsts2 .INIT=16'h00BC;
// @7:47
LUT6 \d_cnst_sn.reg0_28_3_2492_0_cZ (
.I0(datai[19]),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(N_3873_2),
.I5(g0_2_0_i2_lut6_2_O6),
.O(\d_cnst_sn.reg0_28_3_2492_0 )
);
defparam \d_cnst_sn.reg0_28_3_2492_0_cZ .INIT=64'h00CC000000A00000;
// @7:47
LUT6 \d_cnst_sn.addr_20_iv_7_654_i_1_cZ (
.I0(reg1[0]),
.I1(reg3[0]),
.I2(state[0]),
.I3(inf_abs0_2[0]),
.I4(inf_abs0_2[27]),
.I5(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_7_654_i_1 )
);
defparam \d_cnst_sn.addr_20_iv_7_654_i_1_cZ .INIT=64'h0303A35303F3A3F3;
// @7:212
LUT5 \d_cnst_sn.reg3_4_sqmuxa_3_2 (
.I0(inf_abs0_2[24]),
.I1(inf_abs0_2[25]),
.I2(inf_abs0_2[26]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.O(\d_cnst_sn.reg3_5_sqmuxa_2_1 )
);
defparam \d_cnst_sn.reg3_4_sqmuxa_3_2 .INIT=32'hFFFF007F;
// @7:74
LUT5 \d_cnst_sn.reg2_16_11_a1[29] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.I4(r_4[28]),
.O(reg2_16_11_a1[29])
);
defparam \d_cnst_sn.reg2_16_11_a1[29] .INIT=32'h08000000;
// @7:103
LUT6 \d_cnst_sn.b_cnst_0_x2 (
.I0(N_3913),
.I1(N_512_i),
.I2(N_513_i),
.I3(un11_r_cry[30]),
.I4(un14_r_0_I_83),
.I5(N_895),
.O(N_3912)
);
defparam \d_cnst_sn.b_cnst_0_x2 .INIT=64'h5556595AA5A6A9AA;
// @7:318
LUT6 un11_reg0_axb_0_cZ (
.I0(datai[0]),
.I1(inf_abs0_2[0]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.I5(r_4[0]),
.O(un11_reg0_axb_0)
);
defparam un11_reg0_axb_0_cZ.INIT=64'h35353533CACACACC;
// @7:466
LUT6 un3_t_axb_30_cZ (
.I0(reg0[30]),
.I1(reg1[30]),
.I2(reg2[30]),
.I3(inf_abs0_2[31]),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.O(un3_t_axb_30)
);
defparam un3_t_axb_30_cZ.INIT=64'h55FF550F55335555;
// @7:466
LUT6 un3_t_axb_29_cZ (
.I0(reg0[29]),
.I1(reg1[29]),
.I2(reg2[29]),
.I3(un3_reg3_cry_25),
.I4(N_3_0),
.I5(N_13),
.O(un3_t_axb_29)
);
defparam un3_t_axb_29_cZ.INIT=64'h0F0F555500FF3333;
// @7:243
LUT5 reg3_1_1_axb_0_cZ (
.I0(datai[0]),
.I1(inf_abs0_2[0]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.I4(inf_abs0_2[28]),
.O(reg3_1_1_axb_0)
);
defparam reg3_1_1_axb_0_cZ.INIT=32'h35353533;
// @7:47
LUT5 \d_cnst_sn.addr_4_sqmuxa_1_1 (
.I0(inf_abs0_2[24]),
.I1(inf_abs0_2[23]),
.I2(inf_abs0_2[25]),
.I3(inf_abs0_2[26]),
.I4(inf_abs0_2[31]),
.O(addr_4_sqmuxa_1_1)
);
defparam \d_cnst_sn.addr_4_sqmuxa_1_1 .INIT=32'h00002000;
// @7:466
LUT6 \d_cnst_sn.r_4_i[31] (
.I0(reg0[31]),
.I1(reg1[31]),
.I2(reg2[31]),
.I3(inf_abs0_2[31]),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.O(r_4_i[31])
);
defparam \d_cnst_sn.r_4_i[31] .INIT=64'h55FF550F55335555;
// @7:466
LUT6 un3_t_axb_31_cZ (
.I0(reg0[31]),
.I1(reg1[31]),
.I2(reg2[31]),
.I3(inf_abs0_2[31]),
.I4(inf_abs0_2[29]),
.I5(inf_abs0_2[30]),
.O(un3_t_axb_31)
);
defparam un3_t_axb_31_cZ.INIT=64'h55FF550F55335555;
// @7:47
LUT6 \d_cnst_sn.addr_20_iv_9_589_x2 (
.I0(reg2[0]),
.I1(reg1[0]),
.I2(inf_abs0_2[0]),
.I3(inf_abs0_2[31]),
.I4(inf_abs0_2[27]),
.I5(inf_abs0_2[28]),
.O(N_2240_i)
);
defparam \d_cnst_sn.addr_20_iv_9_589_x2 .INIT=64'hF05AF03CF0F0F0F0;
// @7:47
LUT6 \d_cnst_sn.reg0_28_14_2135_1_a0_2_cZ (
.I0(b),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.I4(inf_abs0_2[27]),
.I5(inf_abs0_2[28]),
.O(\d_cnst_sn.reg0_28_14_2135_1_a0_2 )
);
defparam \d_cnst_sn.reg0_28_14_2135_1_a0_2_cZ .INIT=64'h00000000004000C0;
// @7:74
LUT6 \d_cnst_sn.reg2_16_0_cZ[25] (
.I0(N_512_i),
.I1(N_513_i),
.I2(N_514_i),
.I3(m_2[25]),
.I4(N_527_i),
.I5(r_4[24]),
.O(\d_cnst_sn.reg2_16_0 [25])
);
defparam \d_cnst_sn.reg2_16_0_cZ[25] .INIT=64'hFFFDFFFD3F3DFFFD;
// @7:74
LUT6 \d_cnst_sn.reg2_16_0_cZ[24] (
.I0(N_512_i),
.I1(N_513_i),
.I2(N_514_i),
.I3(m_2[24]),
.I4(N_527_i),
.I5(r_4[23]),
.O(\d_cnst_sn.reg2_16_0 [24])
);
defparam \d_cnst_sn.reg2_16_0_cZ[24] .INIT=64'hFFFDFFFD3F3DFFFD;
// @7:74
LUT6 \d_cnst_sn.reg2_16_0_cZ[23] (
.I0(N_512_i),
.I1(N_513_i),
.I2(N_514_i),
.I3(m_2[23]),
.I4(N_527_i),
.I5(r_4[22]),
.O(\d_cnst_sn.reg2_16_0 [23])
);
defparam \d_cnst_sn.reg2_16_0_cZ[23] .INIT=64'hFFFDFFFD3F3DFFFD;
// @7:74
LUT6 \d_cnst_sn.reg2_16_0_cZ[22] (
.I0(N_512_i),
.I1(N_513_i),
.I2(N_514_i),
.I3(m_2[22]),
.I4(N_527_i),
.I5(r_4[21]),
.O(\d_cnst_sn.reg2_16_0 [22])
);
defparam \d_cnst_sn.reg2_16_0_cZ[22] .INIT=64'hFFFDFFFD3F3DFFFD;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_0_cZ[21] (
.I0(N_512_i),
.I1(N_513_i),
.I2(N_514_i),
.I3(m_2[21]),
.I4(N_527_i),
.I5(r_4[20]),
.LO(\d_cnst_sn.reg2_16_0 [21])
);
defparam \d_cnst_sn.reg2_16_0_cZ[21] .INIT=64'hFFFDFFFD3F3DFFFD;
// @7:103
LUT5 \d_cnst_sn.un1_b59 (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.O(un1_b59)
);
defparam \d_cnst_sn.un1_b59 .INIT=32'h00000AC0;
// @7:103
LUT5 \d_cnst_sn.un1_b57 (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.O(un1_b57)
);
defparam \d_cnst_sn.un1_b57 .INIT=32'h00000530;
// @7:47
LUT5 \d_cnst_sn.reg0_m9_i_a1 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.I4(r_4[28]),
.O(reg0_m9_i_a1)
);
defparam \d_cnst_sn.reg0_m9_i_a1 .INIT=32'h08000000;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a2[29] (
.I0(un3_reg3_cry_25),
.I1(N_3913),
.I2(N_512_i),
.I3(\d_cnst_sn.reg1_16_a2_0 [5]),
.I4(m_2[29]),
.I5(reg3_1_1[29]),
.O(reg2_16_11_a2[29])
);
defparam \d_cnst_sn.reg2_16_11_a2[29] .INIT=64'hFE000E00F2000200;
// @7:47
LUT6 \d_cnst_sn.addr_4_sqmuxa_1 (
.I0(state[0]),
.I1(inf_abs0_2[24]),
.I2(inf_abs0_2[23]),
.I3(inf_abs0_2[25]),
.I4(inf_abs0_2[26]),
.I5(inf_abs0_2[31]),
.O(addr_4_sqmuxa_1)
);
defparam \d_cnst_sn.addr_4_sqmuxa_1 .INIT=64'h0000000008000000;
// @7:213
LUT4 \d_cnst_sn.d_cnst_ss0 (
.I0(inf_abs0_2[24]),
.I1(inf_abs0_2[25]),
.I2(inf_abs0_2[26]),
.I3(inf_abs0_2[31]),
.O(d_cnst[0])
);
defparam \d_cnst_sn.d_cnst_ss0 .INIT=16'h00BA;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_17_362_i_1_RNI7JD51 (
.I0(inf_abs0_2[28]),
.I1(un1_inf_abs0_10[10]),
.I2(un1_inf_abs0_11[10]),
.I3(N_2660_2),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I5(\d_cnst_sn.addr_20_iv_17_362_i_1 ),
.LO(N_2119_i)
);
defparam \d_cnst_sn.addr_20_iv_17_362_i_1_RNI7JD51 .INIT=64'h00000000D0F0DDFF;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_16_389_i_1_RNIVH7K1 (
.I0(inf_abs0_2[28]),
.I1(un1_inf_abs0_10[9]),
.I2(un1_inf_abs0_11[9]),
.I3(N_2660_2),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I5(\d_cnst_sn.addr_20_iv_16_389_i_1 ),
.LO(N_2139_i)
);
defparam \d_cnst_sn.addr_20_iv_16_389_i_1_RNIVH7K1 .INIT=64'h00000000D0F0DDFF;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_15_416_i_1_RNI9QLS1 (
.I0(state[0]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_inf_abs0_10[8]),
.I4(un1_inf_abs0_11[8]),
.I5(\d_cnst_sn.addr_20_iv_15_416_i_1 ),
.LO(N_2159_i)
);
defparam \d_cnst_sn.addr_20_iv_15_416_i_1_RNI9QLS1 .INIT=64'h00000000FF7FDD5D;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_14_443_i_2_RNILKQI1 (
.I0(reg3[7]),
.I1(state[0]),
.I2(inf_abs0_2[7]),
.I3(inf_abs0_2[28]),
.I4(\d_cnst_sn.addr_20_iv_14_443_i_2 ),
.I5(N_2641),
.LO(N_2179_i)
);
defparam \d_cnst_sn.addr_20_iv_14_443_i_2_RNILKQI1 .INIT=64'h000000000000EEE2;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_13_470_i_1_RNI3GLV1 (
.I0(state[0]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_inf_abs0_10[6]),
.I4(un1_inf_abs0_11[6]),
.I5(\d_cnst_sn.addr_20_iv_13_470_i_1 ),
.LO(N_2199_i)
);
defparam \d_cnst_sn.addr_20_iv_13_470_i_1_RNI3GLV1 .INIT=64'h00000000FF7FDD5D;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_12_497_i_1_RNI9EOO1 (
.I0(state[0]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_inf_abs0_10[5]),
.I4(un1_inf_abs0_11[5]),
.I5(\d_cnst_sn.addr_20_iv_12_497_i_1 ),
.LO(N_2219_i)
);
defparam \d_cnst_sn.addr_20_iv_12_497_i_1_RNI9EOO1 .INIT=64'h00000000FF7FDD5D;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_10_562_i_1_RNIS0IN1 (
.I0(state[0]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_inf_abs0_10[3]),
.I4(un1_inf_abs0_11[3]),
.I5(\d_cnst_sn.addr_20_iv_10_562_i_1 ),
.LO(N_2267_i)
);
defparam \d_cnst_sn.addr_20_iv_10_562_i_1_RNIS0IN1 .INIT=64'h00000000FF7FDD5D;
// @7:74
LUT6 \d_cnst_sn.reg2_16_0_cZ[20] (
.I0(\d_cnst_sn.reg2_N_3_mux ),
.I1(reg2_16_2_d[20]),
.I2(\d_cnst_sn.reg1_16_a2_0 [5]),
.I3(\d_cnst_sn.reg0_28_a1_1 [4]),
.I4(r_4[19]),
.I5(reg3_1_1[20]),
.O(\d_cnst_sn.reg2_16_0 [20])
);
defparam \d_cnst_sn.reg2_16_0_cZ[20] .INIT=64'hEFEF00EF4F4F004F;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_10 (
.I0(m_2[2]),
.I1(m_2[1]),
.I2(m_2[0]),
.I3(r_4[0]),
.I4(r_4[1]),
.I5(N_28),
.O(un14_r_0_N_70)
);
defparam \d_cnst_sn.un14_r_0_I_10 .INIT=64'h8008200240041001;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_42 (
.I0(m_2[15]),
.I1(m_2[16]),
.I2(m_2[17]),
.I3(r_4[15]),
.I4(r_4[16]),
.I5(r_4[17]),
.O(un14_r_0_N_42)
);
defparam \d_cnst_sn.un14_r_0_I_42 .INIT=64'h8040201008040201;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_74 (
.I0(m_2[3]),
.I1(m_2[4]),
.I2(m_2[5]),
.I3(r_4[3]),
.I4(r_4[4]),
.I5(r_4[5]),
.O(un14_r_0_N_14)
);
defparam \d_cnst_sn.un14_r_0_I_74 .INIT=64'h8040201008040201;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_34 (
.I0(m_2[19]),
.I1(m_2[20]),
.I2(m_2[18]),
.I3(r_4[19]),
.I4(r_4[18]),
.I5(r_4[20]),
.O(un14_r_0_N_49)
);
defparam \d_cnst_sn.un14_r_0_I_34 .INIT=64'h8040080420100201;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_82 (
.I0(m_2[12]),
.I1(m_2[13]),
.I2(m_2[14]),
.I3(r_4[12]),
.I4(r_4[13]),
.I5(r_4[14]),
.O(un14_r_0_N_7)
);
defparam \d_cnst_sn.un14_r_0_I_82 .INIT=64'h8040201008040201;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_58 (
.I0(m_2[9]),
.I1(m_2[10]),
.I2(m_2[11]),
.I3(r_4[11]),
.I4(r_4[9]),
.I5(r_4[10]),
.O(un14_r_0_N_28)
);
defparam \d_cnst_sn.un14_r_0_I_58 .INIT=64'h8008400420021001;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_66 (
.I0(m_2[7]),
.I1(m_2[6]),
.I2(m_2[8]),
.I3(r_4[6]),
.I4(r_4[8]),
.I5(r_4[7]),
.O(un14_r_0_N_21)
);
defparam \d_cnst_sn.un14_r_0_I_66 .INIT=64'h8020080240100401;
// @7:148
LUT6 \d_cnst_sn.r_6[30] (
.I0(reg0[30]),
.I1(reg1[30]),
.I2(reg2[30]),
.I3(N_3_0),
.I4(r_4[31]),
.I5(N_13),
.O(r_6[30])
);
defparam \d_cnst_sn.r_6[30] .INIT=64'hF0AA000000CC0000;
// @7:74
LUT6 \d_cnst_sn.reg0_28_a1_1_lut6_2_RNIH32G2[7] (
.I0(N_3910),
.I1(\d_cnst_sn.reg0_28_a0_1 [7]),
.I2(m_2[7]),
.I3(\d_cnst_sn.reg0_28_a1_1 [4]),
.I4(r_4[6]),
.I5(reg3_1_1[7]),
.O(\d_cnst_sn.reg0_1 [7])
);
defparam \d_cnst_sn.reg0_28_a1_1_lut6_2_RNIH32G2[7] .INIT=64'hF5F500F531310031;
// @7:128
LUT6 \d_cnst_sn.un14_r_0_I_18 (
.I0(m_2[29]),
.I1(m_2[27]),
.I2(m_2[28]),
.I3(r_4[27]),
.I4(r_4[28]),
.I5(r_4[29]),
.O(un14_r_0_N_63)
);
defparam \d_cnst_sn.un14_r_0_I_18 .INIT=64'h8020080240100401;
// @7:212
LUT6 \d_cnst_sn.b_2_sqmuxa (
.I0(N_526_i),
.I1(N_1901),
.I2(N_513_i),
.I3(N_514_i),
.I4(un36_df),
.I5(N_527_i),
.O(b_2_sqmuxa)
);
defparam \d_cnst_sn.b_2_sqmuxa .INIT=64'h0000200000000000;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_18_335_i_1_RNI0IID1 (
.I0(state[0]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_inf_abs0_10[11]),
.I4(un1_inf_abs0_11[11]),
.I5(\d_cnst_sn.addr_20_iv_18_335_i_1 ),
.LO(N_2099_i)
);
defparam \d_cnst_sn.addr_20_iv_18_335_i_1_RNI0IID1 .INIT=64'h00000000FF7FDD5D;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_6_863_i_0_lut6_2_RNI74TR (
.I0(\d_cnst_sn.addr_20_iv_6_863_i_0 ),
.I1(un1_inf_abs0_10[19]),
.I2(un1_inf_abs0_11[19]),
.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),
.I5(N_2641),
.LO(N_2516_i)
);
defparam \d_cnst_sn.addr_20_iv_6_863_i_0_lut6_2_RNI74TR .INIT=64'h0000000040445055;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_1052_i_a6_2_0_lut6_2_RNIUHOV1 (
.I0(\d_cnst_sn.addr_20_iv_5_890_i_0 ),
.I1(un1_inf_abs0_10[18]),
.I2(un1_inf_abs0_11[18]),
.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),
.I5(N_2641),
.LO(N_2536_i)
);
defparam \d_cnst_sn.addr_20_iv_1052_i_a6_2_0_lut6_2_RNIUHOV1 .INIT=64'h0000000040445055;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_4_917_i_0_lut6_2_RNI13AS (
.I0(\d_cnst_sn.addr_20_iv_4_917_i_0 ),
.I1(un1_inf_abs0_10[17]),
.I2(un1_inf_abs0_11[17]),
.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),
.I5(N_2641),
.LO(N_2556_i)
);
defparam \d_cnst_sn.addr_20_iv_4_917_i_0_lut6_2_RNI13AS .INIT=64'h0000000040445055;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_1052_i_a6_2_0_lut6_2_RNIMFOV1 (
.I0(\d_cnst_sn.addr_20_iv_3_944_i_0 ),
.I1(un1_inf_abs0_10[16]),
.I2(un1_inf_abs0_11[16]),
.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),
.I5(N_2641),
.LO(N_2576_i)
);
defparam \d_cnst_sn.addr_20_iv_1052_i_a6_2_0_lut6_2_RNIMFOV1 .INIT=64'h0000000040445055;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_2_971_i_0_lut6_2_RNIRAP31 (
.I0(\d_cnst_sn.addr_20_iv_2_971_i_0 ),
.I1(un1_inf_abs0_10[15]),
.I2(un1_inf_abs0_11[15]),
.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),
.I5(N_2641),
.LO(N_2596_i)
);
defparam \d_cnst_sn.addr_20_iv_2_971_i_0_lut6_2_RNIRAP31 .INIT=64'h0000000040445055;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_1_998_i_0_lut6_2_RNI11O41 (
.I0(\d_cnst_sn.addr_20_iv_1_998_i_0 ),
.I1(un1_inf_abs0_10[14]),
.I2(un1_inf_abs0_11[14]),
.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),
.I5(N_2641),
.LO(N_2616_i)
);
defparam \d_cnst_sn.addr_20_iv_1_998_i_0_lut6_2_RNI11O41 .INIT=64'h0000000040445055;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_0_1025_i_0_lut6_2_RNIS79S (
.I0(\d_cnst_sn.addr_20_iv_0_1025_i_0 ),
.I1(un1_inf_abs0_10[13]),
.I2(un1_inf_abs0_11[13]),
.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),
.I5(N_2641),
.LO(N_2636_i)
);
defparam \d_cnst_sn.addr_20_iv_0_1025_i_0_lut6_2_RNIS79S .INIT=64'h0000000040445055;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_1052_i_0_lut6_2_RNIBHO61 (
.I0(\d_cnst_sn.addr_20_iv_1052_i_0 ),
.I1(un1_inf_abs0_10[12]),
.I2(un1_inf_abs0_11[12]),
.I3(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 ),
.I4(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 ),
.I5(N_2641),
.LO(N_2656_i)
);
defparam \d_cnst_sn.addr_20_iv_1052_i_0_lut6_2_RNIBHO61 .INIT=64'h0000000040445055;
// @7:74
LUT6 \d_cnst_sn.reg2_16_0_1_0_cZ[28] (
.I0(\d_cnst_sn.reg2_16_0_1_tz [28]),
.I1(\d_cnst_sn.reg1_16_a2_0 [5]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[27]),
.I4(N_1363),
.I5(un32_reg0_s_28),
.O(\d_cnst_sn.reg2_16_0_1_0 [28])
);
defparam \d_cnst_sn.reg2_16_0_1_0_cZ[28] .INIT=64'hFF0F3303AA0A2202;
// @7:74
LUT6 \d_cnst_sn.reg2_16_0_1_0_cZ[27] (
.I0(\d_cnst_sn.reg2_16_0_1_tz [28]),
.I1(\d_cnst_sn.reg1_16_a2_0 [5]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[26]),
.I4(N_1362),
.I5(un32_reg0_s_27),
.O(\d_cnst_sn.reg2_16_0_1_0 [27])
);
defparam \d_cnst_sn.reg2_16_0_1_0_cZ[27] .INIT=64'hFF0F3303AA0A2202;
// @7:74
LUT6 \d_cnst_sn.reg2_16_0_1_0_cZ[26] (
.I0(\d_cnst_sn.reg2_16_0_1_tz [28]),
.I1(\d_cnst_sn.reg1_16_a2_0 [5]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[25]),
.I4(N_1361),
.I5(un32_reg0_s_26),
.O(\d_cnst_sn.reg2_16_0_1_0 [26])
);
defparam \d_cnst_sn.reg2_16_0_1_0_cZ[26] .INIT=64'hFF0F3303AA0A2202;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a3[17] (
.I0(N_3913),
.I1(N_513_i),
.I2(N_514_i),
.I3(N_1352),
.I4(un32_reg0_s_17),
.I5(un11_reg0_s_17),
.O(reg2_16_11_a3[17])
);
defparam \d_cnst_sn.reg2_16_11_a3[17] .INIT=64'h0003101320233033;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a3[19] (
.I0(N_3913),
.I1(N_513_i),
.I2(N_514_i),
.I3(N_1354),
.I4(un32_reg0_s_19),
.I5(un11_reg0_s_19),
.O(reg2_16_11_a3[19])
);
defparam \d_cnst_sn.reg2_16_11_a3[19] .INIT=64'h0003101320233033;
// @7:74
LUT6 \d_cnst_sn.reg2_16_11_a3[18] (
.I0(N_3913),
.I1(N_513_i),
.I2(N_514_i),
.I3(N_1353),
.I4(un32_reg0_s_18),
.I5(un11_reg0_s_18),
.O(reg2_16_11_a3[18])
);
defparam \d_cnst_sn.reg2_16_11_a3[18] .INIT=64'h0003101320233033;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[30] (
.I0(inf_abs0_2[22]),
.I1(reg0_28_sn_m6_lut6_2_O5),
.I2(N_513_i),
.I3(N_527_i),
.I4(N_1493),
.I5(t_1[30]),
.LO(reg2_16[30])
);
defparam \d_cnst_sn.reg2_16_11[30] .INIT=64'h0F0F00000F2F0020;
// @7:47
LUT6 \d_cnst_sn.reg1_16_8_1837_0_cZ (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I3(m_2[27]),
.I4(un32_reg0_s_27),
.I5(un11_reg0_s_27),
.O(\d_cnst_sn.reg1_16_8_1837_0 )
);
defparam \d_cnst_sn.reg1_16_8_1837_0_cZ .INIT=64'hFAAAF888F222F000;
// @7:47
LUT6 \d_cnst_sn.reg1_16_7_1870_0_cZ (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I3(m_2[26]),
.I4(un32_reg0_s_26),
.I5(un11_reg0_s_26),
.O(\d_cnst_sn.reg1_16_7_1870_0 )
);
defparam \d_cnst_sn.reg1_16_7_1870_0_cZ .INIT=64'hFAAAF888F222F000;
// @7:47
LUT6 \d_cnst_sn.reg0_28_9_2294_0_cZ (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I3(m_2[25]),
.I4(un32_reg0_s_25),
.I5(un11_reg0_s_25),
.O(\d_cnst_sn.reg0_28_9_2294_0 )
);
defparam \d_cnst_sn.reg0_28_9_2294_0_cZ .INIT=64'hFAAAF888F222F000;
// @7:47
LUT6 \d_cnst_sn.reg0_28_7_2360_0_cZ (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I3(m_2[23]),
.I4(un32_reg0_s_23),
.I5(un11_reg0_s_23),
.O(\d_cnst_sn.reg0_28_7_2360_0 )
);
defparam \d_cnst_sn.reg0_28_7_2360_0_cZ .INIT=64'hFAAAF888F222F000;
// @7:47
LUT6 \d_cnst_sn.reg0_28_6_2393_0_cZ (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I3(m_2[22]),
.I4(un32_reg0_s_22),
.I5(un11_reg0_s_22),
.O(\d_cnst_sn.reg0_28_6_2393_0 )
);
defparam \d_cnst_sn.reg0_28_6_2393_0_cZ .INIT=64'hFAAAF888F222F000;
// @7:47
LUT6 \d_cnst_sn.reg0_28_5_2426_0_cZ (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I3(m_2[21]),
.I4(un32_reg0_s_21),
.I5(un11_reg0_s_21),
.O(\d_cnst_sn.reg0_28_5_2426_0 )
);
defparam \d_cnst_sn.reg0_28_5_2426_0_cZ .INIT=64'hFAAAF888F222F000;
// @7:47
LUT6 \d_cnst_sn.reg0_28_8_2327_0_cZ (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I3(m_2[24]),
.I4(un32_reg0_s_24),
.I5(un11_reg0_s_24),
.O(\d_cnst_sn.reg0_28_8_2327_0 )
);
defparam \d_cnst_sn.reg0_28_8_2327_0_cZ .INIT=64'hFAAAF888F222F000;
// @7:47
LUT6 \d_cnst_sn.reg0_28_4_2459_0_cZ (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I3(m_2[20]),
.I4(un32_reg0_s_20),
.I5(un11_reg0_s_20),
.O(\d_cnst_sn.reg0_28_4_2459_0 )
);
defparam \d_cnst_sn.reg0_28_4_2459_0_cZ .INIT=64'hFAAAF888F222F000;
// @7:47
LUT5 \d_cnst_sn.reg0_28_3_2492_1_cZ (
.I0(\d_cnst_sn.reg0_m9_i_a3_0 ),
.I1(N_1033),
.I2(\d_cnst_sn.reg0_28_3_2492_0 ),
.I3(un32_reg0_s_19),
.I4(un11_reg0_s_19),
.O(\d_cnst_sn.reg0_28_3_2492_1 )
);
defparam \d_cnst_sn.reg0_28_3_2492_1_cZ .INIT=32'hFAF8F2F0;
// @7:74
LUT6 \d_cnst_sn.reg2_16_1_0[29] (
.I0(N_512_i),
.I1(\d_cnst_sn.b60_0 ),
.I2(reg2_16_11_a1[29]),
.I3(reg2_16_11_a2[29]),
.I4(un32_reg0_s_29),
.I5(un11_reg0_s_29),
.O(\d_cnst_sn.reg2_16_1 [29])
);
defparam \d_cnst_sn.reg2_16_1_0[29] .INIT=64'hFFFCFFF4FFF8FFF0;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[3] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1338),
.I3(N_1370),
.I4(N_1562),
.I5(t_6[3]),
.LO(reg2_16[3])
);
defparam \d_cnst_sn.reg2_16_11[3] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[4] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1339),
.I3(N_1371),
.I4(N_1563),
.I5(t_6[4]),
.LO(reg2_16[4])
);
defparam \d_cnst_sn.reg2_16_11[4] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[5] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1340),
.I3(N_1372),
.I4(N_1564),
.I5(t_6[5]),
.LO(reg2_16[5])
);
defparam \d_cnst_sn.reg2_16_11[5] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[6] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1341),
.I3(N_1373),
.I4(N_1565),
.I5(t_6[6]),
.LO(reg2_16[6])
);
defparam \d_cnst_sn.reg2_16_11[6] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[9] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1344),
.I3(N_1376),
.I4(N_1568),
.I5(t_6[9]),
.LO(reg2_16[9])
);
defparam \d_cnst_sn.reg2_16_11[9] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[10] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1345),
.I3(N_1377),
.I4(N_1569),
.I5(t_6[10]),
.LO(reg2_16[10])
);
defparam \d_cnst_sn.reg2_16_11[10] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[11] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1346),
.I3(N_1378),
.I4(N_1570),
.I5(t_6[11]),
.LO(reg2_16[11])
);
defparam \d_cnst_sn.reg2_16_11[11] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[12] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1347),
.I3(N_1379),
.I4(N_1571),
.I5(t_6[12]),
.LO(reg2_16[12])
);
defparam \d_cnst_sn.reg2_16_11[12] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[13] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1348),
.I3(N_1380),
.I4(N_1572),
.I5(t_6[13]),
.LO(reg2_16[13])
);
defparam \d_cnst_sn.reg2_16_11[13] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[14] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1349),
.I3(N_1381),
.I4(N_1573),
.I5(t_6[14]),
.LO(reg2_16[14])
);
defparam \d_cnst_sn.reg2_16_11[14] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[15] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1350),
.I3(N_1382),
.I4(N_1574),
.I5(t_6[15]),
.LO(reg2_16[15])
);
defparam \d_cnst_sn.reg2_16_11[15] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[16] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1351),
.I3(N_1383),
.I4(N_1575),
.I5(t_6[16]),
.LO(reg2_16[16])
);
defparam \d_cnst_sn.reg2_16_11[16] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.rd_18 (
.I0(state[0]),
.I1(N_7_i),
.I2(N_513_i),
.I3(N_514_i),
.I4(un36_df),
.I5(m7),
.LO(rd_18)
);
defparam \d_cnst_sn.rd_18 .INIT=64'h55555555DDDDDFFF;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[8] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1343),
.I3(N_1375),
.I4(N_1567),
.I5(t_6[8]),
.LO(reg2_16[8])
);
defparam \d_cnst_sn.reg2_16_11[8] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[2] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1337),
.I3(N_1369),
.I4(N_1561),
.I5(t_6[2]),
.LO(reg2_16[2])
);
defparam \d_cnst_sn.reg2_16_11[2] .INIT=64'hFEBADC9876325410;
// @7:74
LUT6_L \d_cnst_sn.reg2_16_11[7] (
.I0(N_513_i),
.I1(N_514_i),
.I2(N_1342),
.I3(N_1374),
.I4(N_1566),
.I5(t_6[7]),
.LO(reg2_16[7])
);
defparam \d_cnst_sn.reg2_16_11[7] .INIT=64'hFEBADC9876325410;
// @7:47
LUT6 \d_cnst_sn.addr_0_sqmuxa_1_i (
.I0(state[0]),
.I1(N_7_i),
.I2(N_513_i),
.I3(N_514_i),
.I4(un36_df),
.I5(m7),
.O(addr_0_sqmuxa_1_i)
);
defparam \d_cnst_sn.addr_0_sqmuxa_1_i .INIT=64'h77775555FFFFDFFF;
// @7:47
LUT6 \d_cnst_sn.reg1_16_9_1804_3_tz_cZ (
.I0(\d_cnst_sn.reg0_28_12_2195_a6_1_2_0 ),
.I1(\d_cnst_sn.reg0_m8_e_0 ),
.I2(N_513_i),
.I3(N_527_i),
.I4(r_4[27]),
.I5(reg3_1_1[28]),
.O(\d_cnst_sn.reg1_16_9_1804_3_tz )
);
defparam \d_cnst_sn.reg1_16_9_1804_3_tz_cZ .INIT=64'hBBBBABBBB0B0A0B0;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[17] (
.I0(\d_cnst_sn.reg0_28_a1_1 [4]),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(r_4[16]),
.I3(t_1[17]),
.I4(reg2_16_11_a2[17]),
.I5(reg2_16_11_a3[17]),
.LO(reg2_16[17])
);
defparam \d_cnst_sn.reg2_16[17] .INIT=64'h00000000000031F5;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[19] (
.I0(\d_cnst_sn.reg0_28_a1_1 [4]),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(r_4[18]),
.I3(t_1[19]),
.I4(reg2_16_11_a2[19]),
.I5(reg2_16_11_a3[19]),
.LO(reg2_16[19])
);
defparam \d_cnst_sn.reg2_16[19] .INIT=64'h00000000000031F5;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[18] (
.I0(\d_cnst_sn.reg0_28_a1_1 [4]),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(r_4[17]),
.I3(t_1[18]),
.I4(reg2_16_11_a2[18]),
.I5(reg2_16_11_a3[18]),
.LO(reg2_16[18])
);
defparam \d_cnst_sn.reg2_16[18] .INIT=64'h00000000000031F5;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[20] (
.I0(\d_cnst_sn.reg2_16_11_1_tz [28]),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(\d_cnst_sn.reg2_16_0 [20]),
.I3(un11_reg0_s_20),
.I4(\d_cnst_sn.reg2_16_1 [20]),
.I5(t_1[20]),
.LO(reg2_16[20])
);
defparam \d_cnst_sn.reg2_16[20] .INIT=64'h30200000F0A00000;
// @7:74
LUT5_L \d_cnst_sn.reg2_16_0[28] (
.I0(\d_cnst_sn.reg2_16_11_1_tz [28]),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(un11_reg0_s_28),
.I3(\d_cnst_sn.reg2_16_0_1_0 [28]),
.I4(t_1[28]),
.LO(reg2_16[28])
);
defparam \d_cnst_sn.reg2_16_0[28] .INIT=32'h3200FA00;
// @7:74
LUT5_L \d_cnst_sn.reg2_16_0[27] (
.I0(\d_cnst_sn.reg2_16_11_1_tz [28]),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(un11_reg0_s_27),
.I3(\d_cnst_sn.reg2_16_0_1_0 [27]),
.I4(t_1[27]),
.LO(reg2_16[27])
);
defparam \d_cnst_sn.reg2_16_0[27] .INIT=32'h3200FA00;
// @7:74
LUT5_L \d_cnst_sn.reg2_16_0[26] (
.I0(\d_cnst_sn.reg2_16_11_1_tz [28]),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(un11_reg0_s_26),
.I3(\d_cnst_sn.reg2_16_0_1_0 [26]),
.I4(t_1[26]),
.LO(reg2_16[26])
);
defparam \d_cnst_sn.reg2_16_0[26] .INIT=32'h3200FA00;
// @7:245
LUT5_L \d_cnst_sn.un86_df (
.I0(d[0]),
.I1(d[1]),
.I2(un1_df_1),
.I3(d_cnst[0]),
.I4(d_cnst_sm0),
.LO(un86_df)
);
defparam \d_cnst_sn.un86_df .INIT=32'h404F4040;
// @7:47
LUT6_L \d_cnst_sn.reg0_28_4_2459 (
.I0(\d_cnst_sn.reg0_28_2526_a5_1_0 ),
.I1(\d_cnst_sn.reg1_16_8_1837_2_tz ),
.I2(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I3(\d_cnst_sn.reg0_28_0 [20]),
.I4(t_1[20]),
.I5(\d_cnst_sn.reg0_28_4_2459_0 ),
.LO(reg0_28_4_2459)
);
defparam \d_cnst_sn.reg0_28_4_2459 .INIT=64'hFFFFFFFF0E00EE00;
// @7:47
LUT5_L \d_cnst_sn.reg1_16_8_1837 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_11_2228_a6_1_1 ),
.I2(\d_cnst_sn.reg1_16_8_1837_3_1 ),
.I3(t_1[27]),
.I4(\d_cnst_sn.reg1_16_8_1837_0 ),
.LO(reg1_16_8_1837)
);
defparam \d_cnst_sn.reg1_16_8_1837 .INIT=32'hFFFF54FC;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_7_2360 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_7_2360_3_1 ),
.I2(\d_cnst_sn.reg0_28_7_2360_a6_1_1 ),
.I3(t_1[23]),
.I4(\d_cnst_sn.reg0_28_7_2360_0 ),
.LO(reg0_28_7_2360)
);
defparam \d_cnst_sn.reg0_28_7_2360 .INIT=32'hFFFF54FC;
// @7:47
LUT5_L \d_cnst_sn.reg1_16_7_1870 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_10_2261_a6_1_1 ),
.I2(\d_cnst_sn.reg1_16_7_1870_3_1 ),
.I3(t_1[26]),
.I4(\d_cnst_sn.reg1_16_7_1870_0 ),
.LO(reg1_16_7_1870)
);
defparam \d_cnst_sn.reg1_16_7_1870 .INIT=32'hFFFF54FC;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_5_2426 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_5_2426_3_1 ),
.I2(\d_cnst_sn.reg0_28_5_2426_a6_1_1 ),
.I3(t_1[21]),
.I4(\d_cnst_sn.reg0_28_5_2426_0 ),
.LO(reg0_28_5_2426)
);
defparam \d_cnst_sn.reg0_28_5_2426 .INIT=32'hFFFF54FC;
// @7:47
LUT6_L \d_cnst_sn.reg0_28_3_2492 (
.I0(\d_cnst_sn.reg0_28_2526_a5_1_0 ),
.I1(\d_cnst_sn.reg1_16_8_1837_2_tz ),
.I2(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I3(\d_cnst_sn.reg0_28_0 [19]),
.I4(t_1[19]),
.I5(\d_cnst_sn.reg0_28_3_2492_1 ),
.LO(reg0_28_3_2492)
);
defparam \d_cnst_sn.reg0_28_3_2492 .INIT=64'hFFFFFFFF0E00EE00;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_6_2393 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_6_2393_3_1 ),
.I2(\d_cnst_sn.reg0_28_6_2393_a6_1_1 ),
.I3(t_1[22]),
.I4(\d_cnst_sn.reg0_28_6_2393_0 ),
.LO(reg0_28_6_2393)
);
defparam \d_cnst_sn.reg0_28_6_2393 .INIT=32'hFFFF54FC;
// @7:47
LUT5_L \d_cnst_sn.reg0_28_9_2294 (
.I0(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I1(\d_cnst_sn.reg0_28_9_2294_3_1 ),
.I2(\d_cnst_sn.reg0_28_9_2294_a6_1_1 ),
.I3(t_1[25]),
.I4(\d_cnst_sn.reg0_28_9_2294_0 ),
.LO(N_3673)
);
defparam \d_cnst_sn.reg0_28_9_2294 .INIT=32'hFFFF54FC;
// @7:47
LUT6_L \d_cnst_sn.reg0_28_8_2327 (
.I0(\d_cnst_sn.reg1_16_8_1837_2_tz ),
.I1(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I2(reg0_28_7_d[24]),
.I3(\d_cnst_sn.reg0_28_8_2327_a6_1_1 ),
.I4(t_1[24]),
.I5(\d_cnst_sn.reg0_28_8_2327_0 ),
.LO(reg0_28_8_2327)
);
defparam \d_cnst_sn.reg0_28_8_2327 .INIT=64'hFFFFFFFF3320FFA8;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[29] (
.I0(\d_cnst_sn.reg0_m9_i_a0_0 ),
.I1(N_514_i),
.I2(N_527_i),
.I3(t_1[29]),
.I4(reg2_16_11_a3[29]),
.I5(\d_cnst_sn.reg2_16_1 [29]),
.LO(reg2_16[29])
);
defparam \d_cnst_sn.reg2_16[29] .INIT=64'hFFFFFFFFFFFF0008;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNI0TVT3_0[7] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg0_1 [7]),
.I4(t_1[7]),
.I5(N_1042),
.LO(reg0_28[7])
);
defparam \d_cnst_sn.reg0_28_6_RNI0TVT3_0[7] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[25] (
.I0(\d_cnst_sn.b60_0 ),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(\d_cnst_sn.reg2_16_1 [25]),
.I3(t_1[25]),
.I4(reg2_16_11_a4[25]),
.I5(N_1584),
.LO(reg2_16[25])
);
defparam \d_cnst_sn.reg2_16[25] .INIT=64'h000030F000001050;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[24] (
.I0(\d_cnst_sn.b60_0 ),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(\d_cnst_sn.reg2_16_1 [24]),
.I3(t_1[24]),
.I4(reg2_16_11_a4[24]),
.I5(N_1583),
.LO(reg2_16[24])
);
defparam \d_cnst_sn.reg2_16[24] .INIT=64'h000030F000001050;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[23] (
.I0(\d_cnst_sn.b60_0 ),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(\d_cnst_sn.reg2_16_1 [23]),
.I3(t_1[23]),
.I4(reg2_16_11_a4[23]),
.I5(N_1582),
.LO(reg2_16[23])
);
defparam \d_cnst_sn.reg2_16[23] .INIT=64'h000030F000001050;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[22] (
.I0(\d_cnst_sn.b60_0 ),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(\d_cnst_sn.reg2_16_1 [22]),
.I3(t_1[22]),
.I4(reg2_16_11_a4[22]),
.I5(N_1581),
.LO(reg2_16[22])
);
defparam \d_cnst_sn.reg2_16[22] .INIT=64'h000030F000001050;
// @7:74
LUT6_L \d_cnst_sn.reg2_16[21] (
.I0(\d_cnst_sn.b60_0 ),
.I1(\d_cnst_sn.reg1_16_a0_1 [3]),
.I2(\d_cnst_sn.reg2_16_1 [21]),
.I3(t_1[21]),
.I4(reg2_16_11_a4[21]),
.I5(N_1580),
.LO(reg2_16[21])
);
defparam \d_cnst_sn.reg2_16[21] .INIT=64'h000030F000001050;
// @7:47
LUT6_L b_e (
.I0(b),
.I1(state[0]),
.I2(N_7_i),
.I3(N_514_i),
.I4(b_2_sqmuxa),
.I5(N_3912),
.LO(b_0)
);
defparam b_e.INIT=64'hA222AA2AE2E2EAEA;
// @7:103
LUT6 \d_cnst_sn.un1_df_16_2 (
.I0(d[0]),
.I1(d[1]),
.I2(un1_df_1),
.I3(d_cnst[0]),
.I4(d_cnst_sm0),
.I5(un36_df),
.O(un1_df_17_2)
);
defparam \d_cnst_sn.un1_df_16_2 .INIT=64'h000000008F808080;
LUT6_L \d_cnst_sn.addr_4_sqmuxa_1_1_RNIB1022 (
.I0(inf_abs0_2[4]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_inf_abs0_10[4]),
.I4(un1_inf_abs0_11[4]),
.I5(addr_4_sqmuxa_1_1),
.LO(N_54)
);
defparam \d_cnst_sn.addr_4_sqmuxa_1_1_RNIB1022 .INIT=64'hFFFFFFFF04C435F5;
LUT6_L \d_cnst_sn.addr_4_sqmuxa_1_1_RNI51022 (
.I0(inf_abs0_2[2]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.I3(un1_inf_abs0_10[2]),
.I4(un1_inf_abs0_11[2]),
.I5(addr_4_sqmuxa_1_1),
.LO(N_45)
);
defparam \d_cnst_sn.addr_4_sqmuxa_1_1_RNI51022 .INIT=64'hFFFFFFFF04C435F5;
// @7:169
LUT6 \d_cnst_sn.reg0_28_a1_1_lut6_2_RNISV191_0[7] (
.I0(d[0]),
.I1(d[1]),
.I2(un1_df_1),
.I3(N_3910),
.I4(d_cnst[0]),
.I5(d_cnst_sm0),
.O(N_1132)
);
defparam \d_cnst_sn.reg0_28_a1_1_lut6_2_RNISV191_0[7] .INIT=64'h1000100010001F00;
// @7:169
LUT6 \d_cnst_sn.reg0_28_a1_1_lut6_2_RNISV191[7] (
.I0(d[0]),
.I1(d[1]),
.I2(un1_df_1),
.I3(N_3910),
.I4(d_cnst[0]),
.I5(d_cnst_sm0),
.O(N_1270)
);
defparam \d_cnst_sn.reg0_28_a1_1_lut6_2_RNISV191[7] .INIT=64'h200020002F002000;
// @7:47
LUT6_L \d_cnst_sn.reg1_16_9 (
.I0(\d_cnst_sn.reg0_28_9_2294_a6_3_0 ),
.I1(m_2[28]),
.I2(\d_cnst_sn.reg0_28_7_a0_0 [9]),
.I3(\d_cnst_sn.reg1_16_9_1804_3_tz ),
.I4(t_1[28]),
.I5(N_3614),
.LO(reg1_16_9)
);
defparam \d_cnst_sn.reg1_16_9 .INIT=64'hFFFFFFFF8F88FF88;
// @7:92
LUT6 \d_cnst_sn.reg3_1_sqmuxa (
.I0(N_7_i),
.I1(N_1901),
.I2(N_513_i),
.I3(N_514_i),
.I4(un36_df),
.I5(un87_df),
.O(reg3_1_sqmuxa)
);
defparam \d_cnst_sn.reg3_1_sqmuxa .INIT=64'h0000000100000000;
// @7:92
LUT6 \d_cnst_sn.reg3_14_sqmuxa (
.I0(N_7_i),
.I1(N_1901),
.I2(N_513_i),
.I3(N_514_i),
.I4(un36_df),
.I5(un87_df),
.O(reg3_14_sqmuxa)
);
defparam \d_cnst_sn.reg3_14_sqmuxa .INIT=64'h0000100000000000;
// @7:47
LUT6 \d_cnst_sn.un1_state_4_1_RNIH54E1 (
.I0(d[0]),
.I1(d[1]),
.I2(un1_df_1),
.I3(d_cnst[0]),
.I4(d_cnst_sm0),
.I5(\d_cnst_sn.un1_state_3_1 ),
.O(un1_state_3_i)
);
defparam \d_cnst_sn.un1_state_4_1_RNIH54E1 .INIT=64'h0000000020202F20;
// @7:47
LUT6 \d_cnst_sn.un1_state_4_1_RNIH54E1_0 (
.I0(d[0]),
.I1(d[1]),
.I2(un1_df_1),
.I3(d_cnst[0]),
.I4(d_cnst_sm0),
.I5(\d_cnst_sn.un1_state_3_1 ),
.O(un1_state_4_i)
);
defparam \d_cnst_sn.un1_state_4_1_RNIH54E1_0 .INIT=64'h000000001010101F;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[15] (
.I0(m_2[15]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1050),
.I4(N_1082),
.LO(reg0_28[15])
);
defparam \d_cnst_sn.reg0_28[15] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[15] (
.I0(m_2[15]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1050),
.I4(N_1082),
.LO(reg1_16[15])
);
defparam \d_cnst_sn.reg1_16[15] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[1] (
.I0(m_2[1]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1036),
.I4(N_1068),
.LO(reg0_28[1])
);
defparam \d_cnst_sn.reg0_28[1] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[16] (
.I0(m_2[16]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1051),
.I4(N_1083),
.LO(reg0_28[16])
);
defparam \d_cnst_sn.reg0_28[16] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[18] (
.I0(m_2[18]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1053),
.I4(N_1085),
.LO(reg0_28[18])
);
defparam \d_cnst_sn.reg0_28[18] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[1] (
.I0(m_2[1]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1036),
.I4(N_1068),
.LO(reg1_16[1])
);
defparam \d_cnst_sn.reg1_16[1] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[16] (
.I0(m_2[16]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1051),
.I4(N_1083),
.LO(reg1_16[16])
);
defparam \d_cnst_sn.reg1_16[16] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[13] (
.I0(m_2[13]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1048),
.I4(N_1080),
.LO(reg0_28[13])
);
defparam \d_cnst_sn.reg0_28[13] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[13] (
.I0(m_2[13]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1048),
.I4(N_1080),
.LO(reg1_16[13])
);
defparam \d_cnst_sn.reg1_16[13] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[9] (
.I0(m_2[9]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1044),
.I4(N_1076),
.LO(reg0_28[9])
);
defparam \d_cnst_sn.reg0_28[9] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[10] (
.I0(m_2[10]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1045),
.I4(N_1077),
.LO(reg0_28[10])
);
defparam \d_cnst_sn.reg0_28[10] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[11] (
.I0(m_2[11]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1046),
.I4(N_1078),
.LO(reg0_28[11])
);
defparam \d_cnst_sn.reg0_28[11] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[12] (
.I0(m_2[12]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1047),
.I4(N_1079),
.LO(reg0_28[12])
);
defparam \d_cnst_sn.reg0_28[12] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg0_28[14] (
.I0(m_2[14]),
.I1(N_3916),
.I2(N_1132),
.I3(N_1049),
.I4(N_1081),
.LO(reg0_28[14])
);
defparam \d_cnst_sn.reg0_28[14] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[2] (
.I0(m_2[2]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1037),
.I4(N_1069),
.LO(reg1_16[2])
);
defparam \d_cnst_sn.reg1_16[2] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[9] (
.I0(m_2[9]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1044),
.I4(N_1076),
.LO(reg1_16[9])
);
defparam \d_cnst_sn.reg1_16[9] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[10] (
.I0(m_2[10]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1045),
.I4(N_1077),
.LO(reg1_16[10])
);
defparam \d_cnst_sn.reg1_16[10] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[11] (
.I0(m_2[11]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1046),
.I4(N_1078),
.LO(reg1_16[11])
);
defparam \d_cnst_sn.reg1_16[11] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[12] (
.I0(m_2[12]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1047),
.I4(N_1079),
.LO(reg1_16[12])
);
defparam \d_cnst_sn.reg1_16[12] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[14] (
.I0(m_2[14]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1049),
.I4(N_1081),
.LO(reg1_16[14])
);
defparam \d_cnst_sn.reg1_16[14] .INIT=32'hAFA3ACA0;
// @7:74
LUT5_L \d_cnst_sn.reg1_16[17] (
.I0(m_2[17]),
.I1(N_3916),
.I2(N_1270),
.I3(N_1052),
.I4(N_1084),
.LO(reg1_16[17])
);
defparam \d_cnst_sn.reg1_16[17] .INIT=32'hAFA3ACA0;
// @7:103
LUT6 \d_cnst_sn.reg3_17_a0_0[21] (
.I0(N_7_i),
.I1(N_1901),
.I2(N_513_i),
.I3(N_514_i),
.I4(un1_df_17_2),
.I5(rd_4_sqmuxa),
.O(reg3_17_sn_N_5)
);
defparam \d_cnst_sn.reg3_17_a0_0[21] .INIT=64'h00000000EFFFFFFF;
// @7:47
LUT6 \d_cnst_sn.un86_df_RNIN5BD2 (
.I0(state[0]),
.I1(N_7_i),
.I2(N_1892),
.I3(un36_df),
.I4(N_1890),
.I5(un86_df),
.O(un1_state_1_0_i)
);
defparam \d_cnst_sn.un86_df_RNIN5BD2 .INIT=64'h0002000200000002;
// @7:103
LUT3 \d_cnst_sn.reg3_17_1[1] (
.I0(reg3[1]),
.I1(reg3_1_1[1]),
.I2(reg3_1_sqmuxa),
.O(N_1689)
);
defparam \d_cnst_sn.reg3_17_1[1] .INIT=8'hCA;
// @7:103
LUT3 \d_cnst_sn.reg3_17_1[2] (
.I0(reg3[2]),
.I1(reg3_1_1[2]),
.I2(reg3_1_sqmuxa),
.O(N_1690)
);
defparam \d_cnst_sn.reg3_17_1[2] .INIT=8'hCA;
// @7:103
LUT3 \d_cnst_sn.reg3_17_1[0] (
.I0(reg3[0]),
.I1(m_2[0]),
.I2(reg3_1_sqmuxa),
.O(N_1688)
);
defparam \d_cnst_sn.reg3_17_1[0] .INIT=8'hCA;
// @7:74
LUT6 \d_cnst_sn.reg0_28_7_a1_RNIGOF53[18] (
.I0(N_513_i),
.I1(m_2[18]),
.I2(N_3916),
.I3(reg0_28_7_a1[18]),
.I4(N_1270),
.I5(reg3_1_1[18]),
.O(\d_cnst_sn.reg1_0 [18])
);
defparam \d_cnst_sn.reg0_28_7_a1_RNIGOF53[18] .INIT=64'hCCCCF0FFCCCCF0FA;
// @7:74
LUT6 \d_cnst_sn.reg0_28_7_a1_RNIDMF53[17] (
.I0(N_513_i),
.I1(m_2[17]),
.I2(N_3916),
.I3(reg0_28_7_a1[17]),
.I4(N_1132),
.I5(reg3_1_1[17]),
.O(\d_cnst_sn.reg0_0 [17])
);
defparam \d_cnst_sn.reg0_28_7_a1_RNIDMF53[17] .INIT=64'hCCCCF0FFCCCCF0FA;
// @7:74
LUT6 \d_cnst_sn.m_2_RNI3QJL3[8] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[8]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[7]),
.I4(reg3_1_1[8]),
.I5(N_1132),
.O(\d_cnst_sn.reg0_1 [8])
);
defparam \d_cnst_sn.m_2_RNI3QJL3[8] .INIT=64'hCCCCCCCCFF0F5505;
// @7:74
LUT6 \d_cnst_sn.m_2_RNI3QJL3_0[8] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[8]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[7]),
.I4(reg3_1_1[8]),
.I5(N_1270),
.O(\d_cnst_sn.reg1_1 [8])
);
defparam \d_cnst_sn.m_2_RNI3QJL3_0[8] .INIT=64'hCCCCCCCCFF0F5505;
// @7:74
LUT6 \d_cnst_sn.m_2_RNIPHJL3[6] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[6]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[5]),
.I4(reg3_1_1[6]),
.I5(N_1132),
.O(\d_cnst_sn.reg0_1 [6])
);
defparam \d_cnst_sn.m_2_RNIPHJL3[6] .INIT=64'hCCCCCCCCFF0F5505;
// @7:74
LUT6 \d_cnst_sn.m_2_RNIPHJL3_0[6] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[6]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[5]),
.I4(reg3_1_1[6]),
.I5(N_1270),
.O(\d_cnst_sn.reg1_1 [6])
);
defparam \d_cnst_sn.m_2_RNIPHJL3_0[6] .INIT=64'hCCCCCCCCFF0F5505;
// @7:74
LUT6 \d_cnst_sn.m_2_RNIGF2R3[5] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[5]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[4]),
.I4(reg3_1_1[5]),
.I5(N_1132),
.O(\d_cnst_sn.reg0_1 [5])
);
defparam \d_cnst_sn.m_2_RNIGF2R3[5] .INIT=64'hCCCCCCCCFF0F5505;
// @7:74
LUT6 \d_cnst_sn.m_2_RNIGF2R3_0[5] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[5]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[4]),
.I4(reg3_1_1[5]),
.I5(N_1270),
.O(\d_cnst_sn.reg1_1 [5])
);
defparam \d_cnst_sn.m_2_RNIGF2R3_0[5] .INIT=64'hCCCCCCCCFF0F5505;
// @7:74
LUT6 \d_cnst_sn.m_2_RNI0T1N3[4] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[4]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[3]),
.I4(reg3_1_1[4]),
.I5(N_1270),
.O(\d_cnst_sn.reg1_1 [4])
);
defparam \d_cnst_sn.m_2_RNI0T1N3[4] .INIT=64'hCCCCCCCCFF0F5505;
// @7:74
LUT6 \d_cnst_sn.m_2_RNI0T1N3_0[4] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[4]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(r_4[3]),
.I4(reg3_1_1[4]),
.I5(N_1132),
.O(\d_cnst_sn.reg0_1 [4])
);
defparam \d_cnst_sn.m_2_RNI0T1N3_0[4] .INIT=64'hCCCCCCCCFF0F5505;
// @7:74
LUT6 \d_cnst_sn.m_2_RNIV5355[3] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[3]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(reg3_1_1[3]),
.I4(N_28),
.I5(N_1270),
.O(\d_cnst_sn.reg1_1 [3])
);
defparam \d_cnst_sn.m_2_RNIV5355[3] .INIT=64'hCCCCCCCCFF550F05;
// @7:74
LUT6 \d_cnst_sn.m_2_RNIV5355_0[3] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[3]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(reg3_1_1[3]),
.I4(N_28),
.I5(N_1132),
.O(\d_cnst_sn.reg0_1 [3])
);
defparam \d_cnst_sn.m_2_RNIV5355_0[3] .INIT=64'hCCCCCCCCFF550F05;
// @7:74
LUT6 \d_cnst_sn.m_2_RNIMK1N3[2] (
.I0(\d_cnst_sn.reg1_16_a2_0 [5]),
.I1(m_2[2]),
.I2(\d_cnst_sn.reg0_28_a1_1 [4]),
.I3(reg3_1_1[2]),
.I4(r_4[1]),
.I5(N_1132),
.O(\d_cnst_sn.reg0_1 [2])
);
defparam \d_cnst_sn.m_2_RNIMK1N3[2] .INIT=64'hCCCCCCCCFF550F05;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_9_589_x2_RNIPBNN3 (
.I0(reg3[4]),
.I1(state[0]),
.I2(inf_abs0_2[31]),
.I3(N_2240_i),
.I4(addr_4_sqmuxa_1_1),
.I5(N_54),
.LO(N_56_i)
);
defparam \d_cnst_sn.addr_20_iv_9_589_x2_RNIPBNN3 .INIT=64'hEE22E222EEEEEEEE;
// @7:47
LUT6_L \d_cnst_sn.addr_20_iv_9_589_x2_RNIH9NN3 (
.I0(reg3[2]),
.I1(state[0]),
.I2(inf_abs0_2[31]),
.I3(N_2240_i),
.I4(addr_4_sqmuxa_1_1),
.I5(N_45),
.LO(N_47_i)
);
defparam \d_cnst_sn.addr_20_iv_9_589_x2_RNIH9NN3 .INIT=64'hEE22E222EEEEEEEE;
// @7:103
LUT5 \d_cnst_sn.reg3_N_7_i_RNO (
.I0(reg3[3]),
.I1(inf_abs0_2[3]),
.I2(reg3_1_1[3]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.O(reg3_N_7_i_RNO)
);
defparam \d_cnst_sn.reg3_N_7_i_RNO .INIT=32'h330F33AA;
// @7:103
LUT5 \d_cnst_sn.reg3_1_sqmuxa_RNIEMUH1 (
.I0(un3_reg3_s_1),
.I1(inf_abs0_2[4]),
.I2(reg3_1_1[4]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.O(reg3_1_sqmuxa_RNIEMUH1)
);
defparam \d_cnst_sn.reg3_1_sqmuxa_RNIEMUH1 .INIT=32'h330F3355;
// @7:103
LUT5 \d_cnst_sn.reg3_1_sqmuxa_RNIHMUH1 (
.I0(un3_reg3_s_2),
.I1(inf_abs0_2[5]),
.I2(reg3_1_1[5]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.O(reg3_1_sqmuxa_RNIHMUH1)
);
defparam \d_cnst_sn.reg3_1_sqmuxa_RNIHMUH1 .INIT=32'h330F3355;
// @7:103
LUT5 \d_cnst_sn.reg3_1_sqmuxa_RNINMUH1 (
.I0(un3_reg3_s_4),
.I1(inf_abs0_2[7]),
.I2(reg3_1_1[7]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.O(reg3_1_sqmuxa_RNINMUH1)
);
defparam \d_cnst_sn.reg3_1_sqmuxa_RNINMUH1 .INIT=32'h330F3355;
// @7:103
LUT5 \d_cnst_sn.reg3_1_sqmuxa_RNIKMUH1 (
.I0(un3_reg3_s_3),
.I1(inf_abs0_2[6]),
.I2(reg3_1_1[6]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.O(reg3_1_sqmuxa_RNIKMUH1)
);
defparam \d_cnst_sn.reg3_1_sqmuxa_RNIKMUH1 .INIT=32'h330F3355;
// @7:103
LUT5 \d_cnst_sn.reg3_1_sqmuxa_RNITMUH1 (
.I0(un3_reg3_s_6),
.I1(inf_abs0_2[9]),
.I2(reg3_1_1[9]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.O(reg3_1_sqmuxa_RNITMUH1)
);
defparam \d_cnst_sn.reg3_1_sqmuxa_RNITMUH1 .INIT=32'h330F3355;
// @7:103
LUT5 \d_cnst_sn.reg3_1_sqmuxa_RNIQMUH1 (
.I0(un3_reg3_s_5),
.I1(inf_abs0_2[8]),
.I2(reg3_1_1[8]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.O(reg3_1_sqmuxa_RNIQMUH1)
);
defparam \d_cnst_sn.reg3_1_sqmuxa_RNIQMUH1 .INIT=32'h330F3355;
// @7:103
LUT5 \d_cnst_sn.reg3_1_sqmuxa_RNIE1DM1 (
.I0(un3_reg3_s_7),
.I1(inf_abs0_2[10]),
.I2(reg3_1_1[10]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.O(reg3_1_sqmuxa_RNIE1DM1)
);
defparam \d_cnst_sn.reg3_1_sqmuxa_RNIE1DM1 .INIT=32'h330F3355;
// @7:103
LUT5 \d_cnst_sn.reg3_1_sqmuxa_RNIH1DM1 (
.I0(un3_reg3_s_8),
.I1(inf_abs0_2[11]),
.I2(reg3_1_1[11]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.O(reg3_1_sqmuxa_RNIH1DM1)
);
defparam \d_cnst_sn.reg3_1_sqmuxa_RNIH1DM1 .INIT=32'h330F3355;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[1] (
.I0(un1_df_16),
.I1(N_1810),
.I2(un11_reg0_s_1),
.I3(un32_reg0_s_1),
.I4(N_1658),
.LO(N_1813)
);
defparam \d_cnst_sn.reg3_17_5[1] .INIT=32'hFEDC3210;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[27] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1684),
.I3(un32_reg0_s_27),
.I4(un11_reg0_s_27),
.LO(N_1839)
);
defparam \d_cnst_sn.reg3_17_5[27] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[28] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1685),
.I3(un32_reg0_s_28),
.I4(un11_reg0_s_28),
.LO(N_1840)
);
defparam \d_cnst_sn.reg3_17_5[28] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[16] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1673),
.I3(un32_reg0_s_16),
.I4(un11_reg0_s_16),
.LO(N_1828)
);
defparam \d_cnst_sn.reg3_17_5[16] .INIT=32'hF3D1E2C0;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[9] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1666),
.I3(un32_reg0_s_9),
.I4(un11_reg0_s_9),
.O(N_1821)
);
defparam \d_cnst_sn.reg3_17_5[9] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[19] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1676),
.I3(un32_reg0_s_19),
.I4(un11_reg0_s_19),
.LO(N_1831)
);
defparam \d_cnst_sn.reg3_17_5[19] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[20] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1677),
.I3(un32_reg0_s_20),
.I4(un11_reg0_s_20),
.LO(N_1832)
);
defparam \d_cnst_sn.reg3_17_5[20] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[14] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1671),
.I3(un32_reg0_s_14),
.I4(un11_reg0_s_14),
.LO(N_1826)
);
defparam \d_cnst_sn.reg3_17_5[14] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[18] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1675),
.I3(un32_reg0_s_18),
.I4(un11_reg0_s_18),
.LO(N_1830)
);
defparam \d_cnst_sn.reg3_17_5[18] .INIT=32'hF3D1E2C0;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[5] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1662),
.I3(un32_reg0_s_5),
.I4(un11_reg0_s_5),
.O(N_1817)
);
defparam \d_cnst_sn.reg3_17_5[5] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[12] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1669),
.I3(un32_reg0_s_12),
.I4(un11_reg0_s_12),
.LO(N_1824)
);
defparam \d_cnst_sn.reg3_17_5[12] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[17] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1674),
.I3(un32_reg0_s_17),
.I4(un11_reg0_s_17),
.LO(N_1829)
);
defparam \d_cnst_sn.reg3_17_5[17] .INIT=32'hF3D1E2C0;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[10] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1667),
.I3(un32_reg0_s_10),
.I4(un11_reg0_s_10),
.O(N_1822)
);
defparam \d_cnst_sn.reg3_17_5[10] .INIT=32'hF3D1E2C0;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[11] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1668),
.I3(un32_reg0_s_11),
.I4(un11_reg0_s_11),
.O(N_1823)
);
defparam \d_cnst_sn.reg3_17_5[11] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[2] (
.I0(un1_df_16),
.I1(N_1810),
.I2(un11_reg0_s_2),
.I3(un32_reg0_s_2),
.I4(N_1659),
.LO(N_1814)
);
defparam \d_cnst_sn.reg3_17_5[2] .INIT=32'hFEDC3210;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[6] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1663),
.I3(un32_reg0_s_6),
.I4(un11_reg0_s_6),
.O(N_1818)
);
defparam \d_cnst_sn.reg3_17_5[6] .INIT=32'hF3D1E2C0;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[8] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1665),
.I3(un32_reg0_s_8),
.I4(un11_reg0_s_8),
.O(N_1820)
);
defparam \d_cnst_sn.reg3_17_5[8] .INIT=32'hF3D1E2C0;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[3] (
.I0(un1_df_16),
.I1(N_1810),
.I2(un32_reg0_s_3),
.I3(un11_reg0_s_3),
.I4(N_1660),
.O(N_1815)
);
defparam \d_cnst_sn.reg3_17_5[3] .INIT=32'hFDEC3120;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[15] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1672),
.I3(un32_reg0_s_15),
.I4(un11_reg0_s_15),
.LO(N_1827)
);
defparam \d_cnst_sn.reg3_17_5[15] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[26] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1683),
.I3(un32_reg0_s_26),
.I4(un11_reg0_s_26),
.LO(N_1838)
);
defparam \d_cnst_sn.reg3_17_5[26] .INIT=32'hF3D1E2C0;
// @7:103
LUT5_L \d_cnst_sn.reg3_17_5[25] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1682),
.I3(un32_reg0_s_25),
.I4(un11_reg0_s_25),
.LO(N_1837)
);
defparam \d_cnst_sn.reg3_17_5[25] .INIT=32'hF3D1E2C0;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[7] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1664),
.I3(un32_reg0_s_7),
.I4(un11_reg0_s_7),
.O(N_1819)
);
defparam \d_cnst_sn.reg3_17_5[7] .INIT=32'hF3D1E2C0;
// @7:103
LUT5 \d_cnst_sn.reg3_17_5[4] (
.I0(un1_df_16),
.I1(N_1810),
.I2(N_1661),
.I3(un32_reg0_s_4),
.I4(un11_reg0_s_4),
.O(N_1816)
);
defparam \d_cnst_sn.reg3_17_5[4] .INIT=32'hF3D1E2C0;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_0_cZ[28] (
.I0(un3_reg3_s_25),
.I1(\d_cnst_sn.reg3_17_4_a2_0 [28]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_1[28]),
.I4(reg3_1_sqmuxa),
.I5(reg3_14_sqmuxa),
.O(\d_cnst_sn.reg3_17_6_0 [28])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[28] .INIT=64'hCCCCCCCC0F000A0A;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_0_cZ[27] (
.I0(un3_reg3_s_24),
.I1(\d_cnst_sn.reg3_17_4_a2_0 [27]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_1[27]),
.I4(reg3_1_sqmuxa),
.I5(reg3_14_sqmuxa),
.O(\d_cnst_sn.reg3_17_6_0 [27])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[27] .INIT=64'hCCCCCCCC0F000A0A;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_1_cZ[18] (
.I0(un3_reg3_s_15),
.I1(reg3_1_1[18]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_sqmuxa),
.I4(reg3_14_sqmuxa),
.I5(\d_cnst_sn.reg3_17_6_0 [18]),
.O(\d_cnst_sn.reg3_17_6_1 [18])
);
defparam \d_cnst_sn.reg3_17_6_1_cZ[18] .INIT=64'hFFFFFCFA00000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_1_cZ[19] (
.I0(un3_reg3_s_16),
.I1(reg3_1_1[19]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_sqmuxa),
.I4(reg3_14_sqmuxa),
.I5(\d_cnst_sn.reg3_17_6_0 [19]),
.O(\d_cnst_sn.reg3_17_6_1 [19])
);
defparam \d_cnst_sn.reg3_17_6_1_cZ[19] .INIT=64'hFFFFFCFA00000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_0_cZ[26] (
.I0(un3_reg3_s_23),
.I1(\d_cnst_sn.reg3_17_4_a2_0 [26]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_1[26]),
.I4(reg3_1_sqmuxa),
.I5(reg3_14_sqmuxa),
.O(\d_cnst_sn.reg3_17_6_0 [26])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[26] .INIT=64'hCCCCCCCC0F000A0A;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_1_cZ[17] (
.I0(un3_reg3_s_14),
.I1(reg3_1_1[17]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_sqmuxa),
.I4(reg3_14_sqmuxa),
.I5(\d_cnst_sn.reg3_17_6_0 [17]),
.O(\d_cnst_sn.reg3_17_6_1 [17])
);
defparam \d_cnst_sn.reg3_17_6_1_cZ[17] .INIT=64'hFFFFFCFA00000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_0_cZ[25] (
.I0(un3_reg3_s_22),
.I1(\d_cnst_sn.reg3_17_4_a2_0 [25]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_1[25]),
.I4(reg3_1_sqmuxa),
.I5(reg3_14_sqmuxa),
.O(\d_cnst_sn.reg3_17_6_0 [25])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[25] .INIT=64'hCCCCCCCC0F000A0A;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_1_cZ[16] (
.I0(un3_reg3_s_13),
.I1(reg3_1_1[16]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_sqmuxa),
.I4(reg3_14_sqmuxa),
.I5(\d_cnst_sn.reg3_17_6_0 [16]),
.O(\d_cnst_sn.reg3_17_6_1 [16])
);
defparam \d_cnst_sn.reg3_17_6_1_cZ[16] .INIT=64'hFFFFFCFA00000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_1_cZ[15] (
.I0(un3_reg3_s_12),
.I1(reg3_1_1[15]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_sqmuxa),
.I4(reg3_14_sqmuxa),
.I5(\d_cnst_sn.reg3_17_6_0 [15]),
.O(\d_cnst_sn.reg3_17_6_1 [15])
);
defparam \d_cnst_sn.reg3_17_6_1_cZ[15] .INIT=64'hFFFFFCFA00000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_1_cZ[14] (
.I0(un3_reg3_s_11),
.I1(reg3_1_1[14]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_sqmuxa),
.I4(reg3_14_sqmuxa),
.I5(\d_cnst_sn.reg3_17_6_0 [14]),
.O(\d_cnst_sn.reg3_17_6_1 [14])
);
defparam \d_cnst_sn.reg3_17_6_1_cZ[14] .INIT=64'hFFFFFCFA00000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_1_cZ[13] (
.I0(un3_reg3_s_10),
.I1(reg3_1_1[13]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_sqmuxa),
.I4(reg3_14_sqmuxa),
.I5(\d_cnst_sn.reg3_17_6_0 [13]),
.O(\d_cnst_sn.reg3_17_6_1 [13])
);
defparam \d_cnst_sn.reg3_17_6_1_cZ[13] .INIT=64'hFFFFFCFA00000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_0_cZ[20] (
.I0(un3_reg3_s_17),
.I1(\d_cnst_sn.reg3_17_4_a2_0 [20]),
.I2(reg3_1_1[20]),
.I3(rd_4_sqmuxa),
.I4(reg3_1_sqmuxa),
.I5(reg3_14_sqmuxa),
.O(\d_cnst_sn.reg3_17_6_0 [20])
);
defparam \d_cnst_sn.reg3_17_6_0_cZ[20] .INIT=64'hCCCCCCCC00F000AA;
// @7:103
LUT6 \d_cnst_sn.reg3_17_6_1_cZ[12] (
.I0(un3_reg3_s_9),
.I1(reg3_1_1[12]),
.I2(rd_4_sqmuxa),
.I3(reg3_1_sqmuxa),
.I4(reg3_14_sqmuxa),
.I5(\d_cnst_sn.reg3_17_6_0 [12]),
.O(\d_cnst_sn.reg3_17_6_1 [12])
);
defparam \d_cnst_sn.reg3_17_6_1_cZ[12] .INIT=64'hFFFFFCFA00000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_a0[24] (
.I0(un3_reg3_s_21),
.I1(reg3_1_1[24]),
.I2(N_1810),
.I3(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I4(reg3_1_sqmuxa),
.I5(reg3_17_sn_N_5),
.O(reg3_17_a0[24])
);
defparam \d_cnst_sn.reg3_17_a0[24] .INIT=64'hC000A00000000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_a0[23] (
.I0(un3_reg3_s_20),
.I1(reg3_1_1[23]),
.I2(N_1810),
.I3(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I4(reg3_1_sqmuxa),
.I5(reg3_17_sn_N_5),
.O(reg3_17_a0[23])
);
defparam \d_cnst_sn.reg3_17_a0[23] .INIT=64'hC000A00000000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_a0[22] (
.I0(un3_reg3_s_19),
.I1(reg3_1_1[22]),
.I2(N_1810),
.I3(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I4(reg3_1_sqmuxa),
.I5(reg3_17_sn_N_5),
.O(reg3_17_a0[22])
);
defparam \d_cnst_sn.reg3_17_a0[22] .INIT=64'hC000A00000000000;
// @7:103
LUT6 \d_cnst_sn.reg3_17_a0[21] (
.I0(un3_reg3_s_18),
.I1(reg3_1_1[21]),
.I2(N_1810),
.I3(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I4(reg3_1_sqmuxa),
.I5(reg3_17_sn_N_5),
.O(reg3_17_a0[21])
);
defparam \d_cnst_sn.reg3_17_a0[21] .INIT=64'hC000A00000000000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[1] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_17_sn_N_5),
.I3(N_1689),
.I4(N_1751),
.I5(N_1813),
.LO(reg3_17[1])
);
defparam \d_cnst_sn.reg3_17[1] .INIT=64'hFF7FF77788088000;
// @7:103
LUT5_L \d_cnst_sn.reg3_17[2] (
.I0(reg3_17_sn_N_5),
.I1(N_1690),
.I2(N_1841),
.I3(N_1752),
.I4(N_1814),
.LO(reg3_17[2])
);
defparam \d_cnst_sn.reg3_17[2] .INIT=32'hDF8FD080;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[0] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_17_sn_N_5),
.I3(N_1812),
.I4(N_1688),
.I5(N_1750),
.LO(reg3_17[0])
);
defparam \d_cnst_sn.reg3_17[0] .INIT=64'hFF887F08F7807700;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNI6R0J6_0[3] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg0_1 [3]),
.I4(t_1[3]),
.I5(N_1038),
.LO(reg0_28[3])
);
defparam \d_cnst_sn.reg0_28_6_RNI6R0J6_0[3] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNIR8V45[2] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg0_1 [2]),
.I4(t_1[2]),
.I5(N_1037),
.LO(reg0_28[2])
);
defparam \d_cnst_sn.reg0_28_6_RNIR8V45[2] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNI6R0J6[3] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg1_1 [3]),
.I4(t_1[3]),
.I5(N_1038),
.LO(reg1_16[3])
);
defparam \d_cnst_sn.reg0_28_6_RNI6R0J6[3] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNIKKH35[8] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg0_1 [8]),
.I4(t_1[8]),
.I5(N_1043),
.LO(reg0_28[8])
);
defparam \d_cnst_sn.reg0_28_6_RNIKKH35[8] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNIKKH35_0[8] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg1_1 [8]),
.I4(t_1[8]),
.I5(N_1043),
.LO(reg1_16[8])
);
defparam \d_cnst_sn.reg0_28_6_RNIKKH35_0[8] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNI6AH35_0[6] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg1_1 [6]),
.I4(t_1[6]),
.I5(N_1041),
.LO(reg1_16[6])
);
defparam \d_cnst_sn.reg0_28_6_RNI6AH35_0[6] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNIR6095[5] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg0_1 [5]),
.I4(t_1[5]),
.I5(N_1040),
.LO(reg0_28[5])
);
defparam \d_cnst_sn.reg0_28_6_RNIR6095[5] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNI6AH35[6] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg0_1 [6]),
.I4(t_1[6]),
.I5(N_1041),
.LO(reg0_28[6])
);
defparam \d_cnst_sn.reg0_28_6_RNI6AH35[6] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNI9JV45[4] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg1_1 [4]),
.I4(t_1[4]),
.I5(N_1039),
.LO(reg1_16[4])
);
defparam \d_cnst_sn.reg0_28_6_RNI9JV45[4] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNIR6095_0[5] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg1_1 [5]),
.I4(t_1[5]),
.I5(N_1040),
.LO(reg1_16[5])
);
defparam \d_cnst_sn.reg0_28_6_RNIR6095_0[5] .INIT=64'h0F00FF0001001100;
// @7:74
LUT6_L \d_cnst_sn.reg0_28_6_RNI9JV45_0[4] (
.I0(\d_cnst_sn.b64_0 ),
.I1(\d_cnst_sn.b60_0 ),
.I2(\d_cnst_sn.reg1_16_a0_1 [3]),
.I3(\d_cnst_sn.reg0_1 [4]),
.I4(t_1[4]),
.I5(N_1039),
.LO(reg0_28[4])
);
defparam \d_cnst_sn.reg0_28_6_RNI9JV45_0[4] .INIT=64'h0F00FF0001001100;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_5_RNIRBMC9[4] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_14_sqmuxa),
.I3(reg3_1_sqmuxa_RNIEMUH1),
.I4(N_1816),
.I5(r_4_2_a1_lut6_2_RNI2T8R3[3]),
.LO(reg3_17[4])
);
defparam \d_cnst_sn.reg3_17_5_RNIRBMC9[4] .INIT=64'h777F0008F7FF8088;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_5_RNI2FMC9[5] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_14_sqmuxa),
.I3(reg3_1_sqmuxa_RNIHMUH1),
.I4(N_1817),
.I5(r_4_2_a1_lut6_2_RNI5V8R3[3]),
.LO(reg3_17[5])
);
defparam \d_cnst_sn.reg3_17_5_RNI2FMC9[5] .INIT=64'h777F0008F7FF8088;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_5_RNIH8LK6[7] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_14_sqmuxa),
.I3(reg3_1_sqmuxa_RNINMUH1),
.I4(N_1819),
.I5(r_4_1_RNICM731[6]),
.LO(reg3_17[7])
);
defparam \d_cnst_sn.reg3_17_5_RNIH8LK6[7] .INIT=64'h777F0008F7FF8088;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_5_RNIA5LK6[6] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_14_sqmuxa),
.I3(reg3_1_sqmuxa_RNIKMUH1),
.I4(N_1818),
.I5(r_4_1_RNI9K731[5]),
.LO(reg3_17[6])
);
defparam \d_cnst_sn.reg3_17_5_RNIA5LK6[6] .INIT=64'h777F0008F7FF8088;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_5_RNIVELK6[9] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_14_sqmuxa),
.I3(reg3_1_sqmuxa_RNITMUH1),
.I4(N_1821),
.I5(r_4_1_RNIIQ731[8]),
.LO(reg3_17[9])
);
defparam \d_cnst_sn.reg3_17_5_RNIVELK6[9] .INIT=64'h777F0008F7FF8088;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_5_RNIOBLK6[8] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_14_sqmuxa),
.I3(reg3_1_sqmuxa_RNIQMUH1),
.I4(N_1820),
.I5(r_4_1_RNIFO731[7]),
.LO(reg3_17[8])
);
defparam \d_cnst_sn.reg3_17_5_RNIOBLK6[8] .INIT=64'h777F0008F7FF8088;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_5_RNI2DVL6[10] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_14_sqmuxa),
.I3(reg3_1_sqmuxa_RNIE1DM1),
.I4(N_1822),
.I5(r_4_1_RNIS3K91[9]),
.LO(reg3_17[10])
);
defparam \d_cnst_sn.reg3_17_5_RNI2DVL6[10] .INIT=64'h777F0008F7FF8088;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_5_RNINL3U6[11] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_14_sqmuxa),
.I3(reg3_1_sqmuxa_RNIH1DM1),
.I4(N_1823),
.I5(r_4_1_RNIDBOH1[10]),
.LO(reg3_17[11])
);
defparam \d_cnst_sn.reg3_17_5_RNINL3U6[11] .INIT=64'h777F0008F7FF8088;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[13] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(N_1670),
.I3(\d_cnst_sn.reg3_17_6_1 [13]),
.I4(N_1732),
.I5(reg3_17_4_a2[13]),
.LO(reg3_17[13])
);
defparam \d_cnst_sn.reg3_17[13] .INIT=64'h75752020FD75A820;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[27] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(\d_cnst_sn.reg3_17_6_0 [27]),
.I3(N_1841),
.I4(t_1[27]),
.I5(N_1839),
.LO(reg3_17[27])
);
defparam \d_cnst_sn.reg3_17[27] .INIT=64'hF0FFF4FFF000F400;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[28] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(\d_cnst_sn.reg3_17_6_0 [28]),
.I3(N_1841),
.I4(t_1[28]),
.I5(N_1840),
.LO(reg3_17[28])
);
defparam \d_cnst_sn.reg3_17[28] .INIT=64'hF0FFF4FFF000F400;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[16] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(N_1841),
.I3(\d_cnst_sn.reg3_17_6_1 [16]),
.I4(t_1[16]),
.I5(N_1828),
.LO(reg3_17[16])
);
defparam \d_cnst_sn.reg3_17[16] .INIT=64'hBF0FFF0FB000F000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[19] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(N_1841),
.I3(\d_cnst_sn.reg3_17_6_1 [19]),
.I4(t_1[19]),
.I5(N_1831),
.LO(reg3_17[19])
);
defparam \d_cnst_sn.reg3_17[19] .INIT=64'hBF0FFF0FB000F000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[20] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(\d_cnst_sn.reg3_17_6_0 [20]),
.I3(N_1841),
.I4(t_1[20]),
.I5(N_1832),
.LO(reg3_17[20])
);
defparam \d_cnst_sn.reg3_17[20] .INIT=64'hF0FFF4FFF000F400;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[14] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(t_1[14]),
.I3(N_1841),
.I4(\d_cnst_sn.reg3_17_6_1 [14]),
.I5(N_1826),
.LO(reg3_17[14])
);
defparam \d_cnst_sn.reg3_17[14] .INIT=64'hBFFF00FFBF000000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[18] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(N_1841),
.I3(\d_cnst_sn.reg3_17_6_1 [18]),
.I4(t_1[18]),
.I5(N_1830),
.LO(reg3_17[18])
);
defparam \d_cnst_sn.reg3_17[18] .INIT=64'hBF0FFF0FB000F000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[12] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(t_1[12]),
.I3(N_1841),
.I4(\d_cnst_sn.reg3_17_6_1 [12]),
.I5(N_1824),
.LO(reg3_17[12])
);
defparam \d_cnst_sn.reg3_17[12] .INIT=64'hBFFF00FFBF000000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[17] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(N_1841),
.I3(\d_cnst_sn.reg3_17_6_1 [17]),
.I4(t_1[17]),
.I5(N_1829),
.LO(reg3_17[17])
);
defparam \d_cnst_sn.reg3_17[17] .INIT=64'hBF0FFF0FB000F000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[15] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(N_1841),
.I3(\d_cnst_sn.reg3_17_6_1 [15]),
.I4(t_1[15]),
.I5(N_1827),
.LO(reg3_17[15])
);
defparam \d_cnst_sn.reg3_17[15] .INIT=64'hBF0FFF0FB000F000;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[26] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(\d_cnst_sn.reg3_17_6_0 [26]),
.I3(N_1841),
.I4(t_1[26]),
.I5(N_1838),
.LO(reg3_17[26])
);
defparam \d_cnst_sn.reg3_17[26] .INIT=64'hF0FFF4FFF000F400;
// @7:103
LUT6_L \d_cnst_sn.reg3_17[25] (
.I0(N_527_i),
.I1(reg3_14_sqmuxa),
.I2(\d_cnst_sn.reg3_17_6_0 [25]),
.I3(N_1841),
.I4(t_1[25]),
.I5(N_1837),
.LO(reg3_17[25])
);
defparam \d_cnst_sn.reg3_17[25] .INIT=64'hF0FFF4FFF000F400;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_2_RNI79973[24] (
.I0(N_1810),
.I1(reg3_17_a0[24]),
.I2(\d_cnst_sn.reg3_17_a1_2 [24]),
.I3(\d_cnst_sn.reg3_17_0_tz [24]),
.I4(t_1[24]),
.I5(N_1743),
.LO(reg3_17[24])
);
defparam \d_cnst_sn.reg3_17_2_RNI79973[24] .INIT=64'hFFDDFFFDEECCFEFC;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_2_RNI36973[23] (
.I0(N_1810),
.I1(reg3_17_a0[23]),
.I2(\d_cnst_sn.reg3_17_a1_2 [24]),
.I3(\d_cnst_sn.reg3_17_0_tz [23]),
.I4(t_1[23]),
.I5(N_1742),
.LO(reg3_17[23])
);
defparam \d_cnst_sn.reg3_17_2_RNI36973[23] .INIT=64'hFFDDFFFDEECCFEFC;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_2_RNIV2973[22] (
.I0(N_1810),
.I1(reg3_17_a0[22]),
.I2(\d_cnst_sn.reg3_17_a1_2 [24]),
.I3(\d_cnst_sn.reg3_17_0_tz [22]),
.I4(t_1[22]),
.I5(N_1741),
.LO(reg3_17[22])
);
defparam \d_cnst_sn.reg3_17_2_RNIV2973[22] .INIT=64'hFFDDFFFDEECCFEFC;
// @7:103
LUT6_L \d_cnst_sn.reg3_17_2_RNIRV873[21] (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_0_tz [21]),
.I2(reg3_17_a0[21]),
.I3(\d_cnst_sn.reg3_17_a1_2 [24]),
.I4(t_1[21]),
.I5(N_1740),
.LO(reg3_17[21])
);
defparam \d_cnst_sn.reg3_17_2_RNIRV873[21] .INIT=64'hFDFDFFFDF8F8FFF8;
// @7:47
LUT6_L \d_cnst_sn.reg3_N_7_i_cZ (
.I0(N_1810),
.I1(\d_cnst_sn.reg3_17_sn_m7_0 ),
.I2(reg3_14_sqmuxa),
.I3(reg3_N_7_i_RNO),
.I4(N_1815),
.I5(t_6[3]),
.LO(\d_cnst_sn.reg3_N_7_i )
);
defparam \d_cnst_sn.reg3_N_7_i_cZ .INIT=64'hF7FF8088777F0008;
LUT5 \datai_RNI2IEL2[20] (
.I0(datai[20]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[20]),
.O(un11_reg0_axb_20)
);
defparam \datai_RNI2IEL2[20] .INIT=32'hDDDF2220;
LUT4 \datai_RNI2UAU_0[20] (
.I0(datai[20]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[20])
);
defparam \datai_RNI2UAU_0[20] .INIT=16'h2220;
LUT5 \datai_RNIH7MC2[21] (
.I0(datai[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[21]),
.O(un11_reg0_axb_21)
);
defparam \datai_RNIH7MC2[21] .INIT=32'hDDDF2220;
LUT4 \datai_RNI3VAU_0[21] (
.I0(datai[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[21])
);
defparam \datai_RNI3VAU_0[21] .INIT=16'h2220;
LUT5 \datai_RNIAOEL2[22] (
.I0(datai[22]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[22]),
.O(un11_reg0_axb_22)
);
defparam \datai_RNIAOEL2[22] .INIT=32'hDDDF2220;
LUT4 \datai_RNI40BU_0[22] (
.I0(datai[22]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[22])
);
defparam \datai_RNI40BU_0[22] .INIT=16'h2220;
LUT5 \datai_RNI5SEL2[23] (
.I0(datai[23]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[23]),
.O(un11_reg0_axb_23)
);
defparam \datai_RNI5SEL2[23] .INIT=32'hDDDF2220;
LUT4 \datai_RNI51BU_0[23] (
.I0(datai[23]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[23])
);
defparam \datai_RNI51BU_0[23] .INIT=16'h2220;
LUT5 \datai_RNI9VEL2[24] (
.I0(datai[24]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[24]),
.O(un11_reg0_axb_24)
);
defparam \datai_RNI9VEL2[24] .INIT=32'hDDDF2220;
LUT4 \datai_RNI62BU_0[24] (
.I0(datai[24]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[24])
);
defparam \datai_RNI62BU_0[24] .INIT=16'h2220;
LUT5 \datai_RNI1OMC2[25] (
.I0(datai[25]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[25]),
.O(un11_reg0_axb_25)
);
defparam \datai_RNI1OMC2[25] .INIT=32'hDDDF2220;
LUT4 \datai_RNI73BU_0[25] (
.I0(datai[25]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[25])
);
defparam \datai_RNI73BU_0[25] .INIT=16'h2220;
LUT5 \datai_RNI5SMC2[26] (
.I0(datai[26]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[26]),
.O(un11_reg0_axb_26)
);
defparam \datai_RNI5SMC2[26] .INIT=32'hDDDF2220;
LUT4 \datai_RNI84BU_0[26] (
.I0(datai[26]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[26])
);
defparam \datai_RNI84BU_0[26] .INIT=16'h2220;
LUT5 \datai_RNIL8FL2[27] (
.I0(datai[27]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[27]),
.O(un11_reg0_axb_27)
);
defparam \datai_RNIL8FL2[27] .INIT=32'hDDDF2220;
LUT4 \datai_RNI95BU_0[27] (
.I0(datai[27]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[27])
);
defparam \datai_RNI95BU_0[27] .INIT=16'h2220;
LUT5 \datai_RNID4NC2[28] (
.I0(datai[28]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.I4(r_4[28]),
.O(un11_reg0_axb_28)
);
defparam \datai_RNID4NC2[28] .INIT=32'hDDDF2220;
LUT4 \datai_RNIA6BU_0[28] (
.I0(datai[28]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[28])
);
defparam \datai_RNIA6BU_0[28] .INIT=16'h2220;
LUT5 \d_cnst_sn.r_4_1_RNI4OE61[5] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_920),
.I3(N_952),
.I4(m_2[5]),
.O(un32_reg0_axb_5)
);
defparam \d_cnst_sn.r_4_1_RNI4OE61[5] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNI7RE61[6] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_921),
.I3(N_953),
.I4(m_2[6]),
.O(un32_reg0_axb_6)
);
defparam \d_cnst_sn.r_4_1_RNI7RE61[6] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNIAUE61[7] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_922),
.I3(N_954),
.I4(m_2[7]),
.O(un32_reg0_axb_7)
);
defparam \d_cnst_sn.r_4_1_RNIAUE61[7] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNID1F61[8] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_923),
.I3(N_955),
.I4(m_2[8]),
.O(un32_reg0_axb_8)
);
defparam \d_cnst_sn.r_4_1_RNID1F61[8] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNIG4F61[9] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_924),
.I3(N_956),
.I4(m_2[9]),
.O(un32_reg0_axb_9)
);
defparam \d_cnst_sn.r_4_1_RNIG4F61[9] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNI88L31[10] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_925),
.I3(N_957),
.I4(m_2[10]),
.O(un32_reg0_axb_10)
);
defparam \d_cnst_sn.r_4_1_RNI88L31[10] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNIBBL31[11] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_926),
.I3(N_958),
.I4(m_2[11]),
.O(un32_reg0_axb_11)
);
defparam \d_cnst_sn.r_4_1_RNIBBL31[11] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNIEEL31[12] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_927),
.I3(N_959),
.I4(m_2[12]),
.O(un32_reg0_axb_12)
);
defparam \d_cnst_sn.r_4_1_RNIEEL31[12] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNIHHL31[13] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_928),
.I3(N_960),
.I4(m_2[13]),
.O(un32_reg0_axb_13)
);
defparam \d_cnst_sn.r_4_1_RNIHHL31[13] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNIKKL31[14] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_929),
.I3(N_961),
.I4(m_2[14]),
.O(un32_reg0_axb_14)
);
defparam \d_cnst_sn.r_4_1_RNIKKL31[14] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNINNL31[15] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_930),
.I3(N_962),
.I4(m_2[15]),
.O(un32_reg0_axb_15)
);
defparam \d_cnst_sn.r_4_1_RNINNL31[15] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNIQQL31[16] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_931),
.I3(N_963),
.I4(m_2[16]),
.O(un32_reg0_axb_16)
);
defparam \d_cnst_sn.r_4_1_RNIQQL31[16] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNITTL31[17] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_932),
.I3(N_964),
.I4(m_2[17]),
.O(un32_reg0_axb_17)
);
defparam \d_cnst_sn.r_4_1_RNITTL31[17] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNI01M31[18] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_933),
.I3(N_965),
.I4(m_2[18]),
.O(un32_reg0_axb_18)
);
defparam \d_cnst_sn.r_4_1_RNI01M31[18] .INIT=32'hF4B00B4F;
LUT5 \d_cnst_sn.r_4_1_RNIOJPQ1[19] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[29]),
.I2(N_934),
.I3(N_2722),
.I4(m_2[19]),
.O(un32_reg0_axb_19)
);
defparam \d_cnst_sn.r_4_1_RNIOJPQ1[19] .INIT=32'hF4B00B4F;
// @7:466
XORCY t_1_s_31 (
.LI(r_4[31]),
.CI(t_1_cry_30),
.O(t_1[31])
);
// @7:466
XORCY t_1_s_30 (
.LI(N_4571_i),
.CI(t_1_cry_29),
.O(t_1[30])
);
// @7:466
MUXCY_L t_1_cry_30_cZ (
.DI(VCC),
.CI(t_1_cry_29),
.S(N_4571_i),
.LO(t_1_cry_30)
);
// @7:466
XORCY t_1_s_29 (
.LI(N_4570_i),
.CI(t_1_cry_28),
.O(t_1[29])
);
// @7:466
MUXCY_L t_1_cry_29_cZ (
.DI(VCC),
.CI(t_1_cry_28),
.S(N_4570_i),
.LO(t_1_cry_29)
);
// @7:466
XORCY t_1_s_28 (
.LI(N_4569_i),
.CI(t_1_cry_27),
.O(t_1[28])
);
// @7:466
MUXCY_L t_1_cry_28_cZ (
.DI(VCC),
.CI(t_1_cry_27),
.S(N_4569_i),
.LO(t_1_cry_28)
);
// @7:466
XORCY t_1_s_27 (
.LI(N_4568_i),
.CI(t_1_cry_26),
.O(t_1[27])
);
// @7:466
MUXCY_L t_1_cry_27_cZ (
.DI(VCC),
.CI(t_1_cry_26),
.S(N_4568_i),
.LO(t_1_cry_27)
);
// @7:466
XORCY t_1_s_26 (
.LI(N_4567_i),
.CI(t_1_cry_25),
.O(t_1[26])
);
// @7:466
MUXCY_L t_1_cry_26_cZ (
.DI(VCC),
.CI(t_1_cry_25),
.S(N_4567_i),
.LO(t_1_cry_26)
);
// @7:466
XORCY t_1_s_25 (
.LI(N_4566_i),
.CI(t_1_cry_24),
.O(t_1[25])
);
// @7:466
MUXCY_L t_1_cry_25_cZ (
.DI(VCC),
.CI(t_1_cry_24),
.S(N_4566_i),
.LO(t_1_cry_25)
);
// @7:466
XORCY t_1_s_24 (
.LI(N_4565_i),
.CI(t_1_cry_23),
.O(t_1[24])
);
// @7:466
MUXCY_L t_1_cry_24_cZ (
.DI(VCC),
.CI(t_1_cry_23),
.S(N_4565_i),
.LO(t_1_cry_24)
);
// @7:466
XORCY t_1_s_23 (
.LI(N_4564_i),
.CI(t_1_cry_22),
.O(t_1[23])
);
// @7:466
MUXCY_L t_1_cry_23_cZ (
.DI(VCC),
.CI(t_1_cry_22),
.S(N_4564_i),
.LO(t_1_cry_23)
);
// @7:466
XORCY t_1_s_22 (
.LI(N_4563_i),
.CI(t_1_cry_21),
.O(t_1[22])
);
// @7:466
MUXCY_L t_1_cry_22_cZ (
.DI(VCC),
.CI(t_1_cry_21),
.S(N_4563_i),
.LO(t_1_cry_22)
);
// @7:466
XORCY t_1_s_21 (
.LI(N_4562_i),
.CI(t_1_cry_20),
.O(t_1[21])
);
// @7:466
MUXCY_L t_1_cry_21_cZ (
.DI(VCC),
.CI(t_1_cry_20),
.S(N_4562_i),
.LO(t_1_cry_21)
);
// @7:466
XORCY t_1_s_20 (
.LI(N_4561_i),
.CI(t_1_cry_19),
.O(t_1[20])
);
// @7:466
MUXCY_L t_1_cry_20_cZ (
.DI(VCC),
.CI(t_1_cry_19),
.S(N_4561_i),
.LO(t_1_cry_20)
);
// @7:466
XORCY t_1_s_19 (
.LI(N_4560_i),
.CI(t_1_cry_18),
.O(t_1[19])
);
// @7:466
MUXCY_L t_1_cry_19_cZ (
.DI(VCC),
.CI(t_1_cry_18),
.S(N_4560_i),
.LO(t_1_cry_19)
);
// @7:466
XORCY t_1_s_18 (
.LI(N_4559_i),
.CI(t_1_cry_17),
.O(t_1[18])
);
// @7:466
MUXCY_L t_1_cry_18_cZ (
.DI(VCC),
.CI(t_1_cry_17),
.S(N_4559_i),
.LO(t_1_cry_18)
);
// @7:466
XORCY t_1_s_17 (
.LI(N_4558_i),
.CI(t_1_cry_16),
.O(t_1[17])
);
// @7:466
MUXCY_L t_1_cry_17_cZ (
.DI(VCC),
.CI(t_1_cry_16),
.S(N_4558_i),
.LO(t_1_cry_17)
);
// @7:466
XORCY t_1_s_16 (
.LI(N_4557_i),
.CI(t_1_cry_15),
.O(t_1[16])
);
// @7:466
MUXCY_L t_1_cry_16_cZ (
.DI(VCC),
.CI(t_1_cry_15),
.S(N_4557_i),
.LO(t_1_cry_16)
);
// @7:466
XORCY t_1_s_15 (
.LI(N_4556_i),
.CI(t_1_cry_14),
.O(t_1[15])
);
// @7:466
MUXCY_L t_1_cry_15_cZ (
.DI(VCC),
.CI(t_1_cry_14),
.S(N_4556_i),
.LO(t_1_cry_15)
);
// @7:466
XORCY t_1_s_14 (
.LI(N_4555_i),
.CI(t_1_cry_13),
.O(t_1[14])
);
// @7:466
MUXCY_L t_1_cry_14_cZ (
.DI(VCC),
.CI(t_1_cry_13),
.S(N_4555_i),
.LO(t_1_cry_14)
);
// @7:466
XORCY t_1_s_13 (
.LI(N_4554_i),
.CI(t_1_cry_12),
.O(t_1[13])
);
// @7:466
MUXCY_L t_1_cry_13_cZ (
.DI(VCC),
.CI(t_1_cry_12),
.S(N_4554_i),
.LO(t_1_cry_13)
);
// @7:466
XORCY t_1_s_12 (
.LI(N_4553_i),
.CI(t_1_cry_11),
.O(t_1[12])
);
// @7:466
MUXCY_L t_1_cry_12_cZ (
.DI(VCC),
.CI(t_1_cry_11),
.S(N_4553_i),
.LO(t_1_cry_12)
);
// @7:466
XORCY t_1_s_11 (
.LI(N_4552_i),
.CI(t_1_cry_10),
.O(t_1[11])
);
// @7:466
MUXCY_L t_1_cry_11_cZ (
.DI(VCC),
.CI(t_1_cry_10),
.S(N_4552_i),
.LO(t_1_cry_11)
);
// @7:466
XORCY t_1_s_10 (
.LI(N_4551_i),
.CI(t_1_cry_9),
.O(t_1[10])
);
// @7:466
MUXCY_L t_1_cry_10_cZ (
.DI(VCC),
.CI(t_1_cry_9),
.S(N_4551_i),
.LO(t_1_cry_10)
);
// @7:466
XORCY t_1_s_9 (
.LI(N_4550_i),
.CI(t_1_cry_8),
.O(t_1[9])
);
// @7:466
MUXCY_L t_1_cry_9_cZ (
.DI(VCC),
.CI(t_1_cry_8),
.S(N_4550_i),
.LO(t_1_cry_9)
);
// @7:466
XORCY t_1_s_8 (
.LI(N_4549_i),
.CI(t_1_cry_7),
.O(t_1[8])
);
// @7:466
MUXCY_L t_1_cry_8_cZ (
.DI(VCC),
.CI(t_1_cry_7),
.S(N_4549_i),
.LO(t_1_cry_8)
);
// @7:466
XORCY t_1_s_7 (
.LI(N_4548_i),
.CI(t_1_cry_6),
.O(t_1[7])
);
// @7:466
MUXCY_L t_1_cry_7_cZ (
.DI(VCC),
.CI(t_1_cry_6),
.S(N_4548_i),
.LO(t_1_cry_7)
);
// @7:466
XORCY t_1_s_6 (
.LI(N_4547_i),
.CI(t_1_cry_5),
.O(t_1[6])
);
// @7:466
MUXCY_L t_1_cry_6_cZ (
.DI(VCC),
.CI(t_1_cry_5),
.S(N_4547_i),
.LO(t_1_cry_6)
);
// @7:466
XORCY t_1_s_5 (
.LI(N_4546_i),
.CI(t_1_cry_4),
.O(t_1[5])
);
// @7:466
MUXCY_L t_1_cry_5_cZ (
.DI(VCC),
.CI(t_1_cry_4),
.S(N_4546_i),
.LO(t_1_cry_5)
);
// @7:466
XORCY t_1_s_4 (
.LI(N_4545_i),
.CI(t_1_cry_3),
.O(t_1[4])
);
// @7:466
MUXCY_L t_1_cry_4_cZ (
.DI(VCC),
.CI(t_1_cry_3),
.S(N_4545_i),
.LO(t_1_cry_4)
);
// @7:466
XORCY t_1_s_3 (
.LI(N_4544_i),
.CI(t_1_cry_2),
.O(t_1[3])
);
// @7:466
MUXCY_L t_1_cry_3_cZ (
.DI(VCC),
.CI(t_1_cry_2),
.S(N_4544_i),
.LO(t_1_cry_3)
);
// @7:466
XORCY t_1_s_2 (
.LI(N_4543_i),
.CI(t_1_cry_1),
.O(t_1[2])
);
// @7:466
MUXCY_L t_1_cry_2_cZ (
.DI(VCC),
.CI(t_1_cry_1),
.S(N_4543_i),
.LO(t_1_cry_2)
);
// @7:466
XORCY t_1_s_1 (
.LI(N_4542_i),
.CI(t_1_cry_0),
.O(t_1[1])
);
// @7:466
MUXCY_L t_1_cry_1_cZ (
.DI(VCC),
.CI(t_1_cry_0),
.S(N_4542_i),
.LO(t_1_cry_1)
);
// @7:466
XORCY t_1_s_0 (
.LI(N_4541_i),
.CI(t_1_cry_0_cy),
.O(t_1[0])
);
// @7:466
MUXCY_L t_1_cry_0_cZ (
.DI(VCC),
.CI(t_1_cry_0_cy),
.S(N_4541_i),
.LO(t_1_cry_0)
);
// @7:95
XORCY un3_reg3_s_25_cZ (
.LI(un3_reg3_axb_25),
.CI(un3_reg3_cry_24),
.O(un3_reg3_s_25)
);
// @7:95
MUXCY un3_reg3_cry_25_cZ (
.DI(GND),
.CI(un3_reg3_cry_24),
.S(un3_reg3_axb_25),
.O(un3_reg3_cry_25_0)
);
// @7:95
XORCY un3_reg3_s_24_cZ (
.LI(un3_reg3_axb_24),
.CI(un3_reg3_cry_23),
.O(un3_reg3_s_24)
);
// @7:95
MUXCY_L un3_reg3_cry_24_cZ (
.DI(GND),
.CI(un3_reg3_cry_23),
.S(un3_reg3_axb_24),
.LO(un3_reg3_cry_24)
);
// @7:95
XORCY un3_reg3_s_23_cZ (
.LI(un3_reg3_axb_23),
.CI(un3_reg3_cry_22),
.O(un3_reg3_s_23)
);
// @7:95
MUXCY_L un3_reg3_cry_23_cZ (
.DI(GND),
.CI(un3_reg3_cry_22),
.S(un3_reg3_axb_23),
.LO(un3_reg3_cry_23)
);
// @7:95
XORCY un3_reg3_s_22_cZ (
.LI(un3_reg3_axb_22),
.CI(un3_reg3_cry_21),
.O(un3_reg3_s_22)
);
// @7:95
MUXCY_L un3_reg3_cry_22_cZ (
.DI(GND),
.CI(un3_reg3_cry_21),
.S(un3_reg3_axb_22),
.LO(un3_reg3_cry_22)
);
// @7:95
XORCY un3_reg3_s_21_cZ (
.LI(un3_reg3_axb_21),
.CI(un3_reg3_cry_20),
.O(un3_reg3_s_21)
);
// @7:95
MUXCY_L un3_reg3_cry_21_cZ (
.DI(GND),
.CI(un3_reg3_cry_20),
.S(un3_reg3_axb_21),
.LO(un3_reg3_cry_21)
);
// @7:95
XORCY un3_reg3_s_20_cZ (
.LI(un3_reg3_axb_20),
.CI(un3_reg3_cry_19),
.O(un3_reg3_s_20)
);
// @7:95
MUXCY_L un3_reg3_cry_20_cZ (
.DI(GND),
.CI(un3_reg3_cry_19),
.S(un3_reg3_axb_20),
.LO(un3_reg3_cry_20)
);
// @7:95
XORCY un3_reg3_s_19_cZ (
.LI(un3_reg3_axb_19),
.CI(un3_reg3_cry_18),
.O(un3_reg3_s_19)
);
// @7:95
MUXCY_L un3_reg3_cry_19_cZ (
.DI(GND),
.CI(un3_reg3_cry_18),
.S(un3_reg3_axb_19),
.LO(un3_reg3_cry_19)
);
// @7:95
XORCY un3_reg3_s_18_cZ (
.LI(un3_reg3_axb_18),
.CI(un3_reg3_cry_17),
.O(un3_reg3_s_18)
);
// @7:95
MUXCY_L un3_reg3_cry_18_cZ (
.DI(GND),
.CI(un3_reg3_cry_17),
.S(un3_reg3_axb_18),
.LO(un3_reg3_cry_18)
);
// @7:95
XORCY un3_reg3_s_17_cZ (
.LI(un3_reg3_axb_17),
.CI(un3_reg3_cry_16),
.O(un3_reg3_s_17)
);
// @7:95
MUXCY_L un3_reg3_cry_17_cZ (
.DI(GND),
.CI(un3_reg3_cry_16),
.S(un3_reg3_axb_17),
.LO(un3_reg3_cry_17)
);
// @7:95
XORCY un3_reg3_s_16_cZ (
.LI(un3_reg3_axb_16),
.CI(un3_reg3_cry_15),
.O(un3_reg3_s_16)
);
// @7:95
MUXCY_L un3_reg3_cry_16_cZ (
.DI(GND),
.CI(un3_reg3_cry_15),
.S(un3_reg3_axb_16),
.LO(un3_reg3_cry_16)
);
// @7:95
XORCY un3_reg3_s_15_cZ (
.LI(un3_reg3_axb_15),
.CI(un3_reg3_cry_14),
.O(un3_reg3_s_15)
);
// @7:95
MUXCY_L un3_reg3_cry_15_cZ (
.DI(GND),
.CI(un3_reg3_cry_14),
.S(un3_reg3_axb_15),
.LO(un3_reg3_cry_15)
);
// @7:95
XORCY un3_reg3_s_14_cZ (
.LI(un3_reg3_axb_14),
.CI(un3_reg3_cry_13),
.O(un3_reg3_s_14)
);
// @7:95
MUXCY_L un3_reg3_cry_14_cZ (
.DI(GND),
.CI(un3_reg3_cry_13),
.S(un3_reg3_axb_14),
.LO(un3_reg3_cry_14)
);
// @7:95
XORCY un3_reg3_s_13_cZ (
.LI(un3_reg3_axb_13),
.CI(un3_reg3_cry_12),
.O(un3_reg3_s_13)
);
// @7:95
MUXCY_L un3_reg3_cry_13_cZ (
.DI(GND),
.CI(un3_reg3_cry_12),
.S(un3_reg3_axb_13),
.LO(un3_reg3_cry_13)
);
// @7:95
XORCY un3_reg3_s_12_cZ (
.LI(un3_reg3_axb_12),
.CI(un3_reg3_cry_11),
.O(un3_reg3_s_12)
);
// @7:95
MUXCY_L un3_reg3_cry_12_cZ (
.DI(GND),
.CI(un3_reg3_cry_11),
.S(un3_reg3_axb_12),
.LO(un3_reg3_cry_12)
);
// @7:95
XORCY un3_reg3_s_11_cZ (
.LI(un3_reg3_axb_11),
.CI(un3_reg3_cry_10),
.O(un3_reg3_s_11)
);
// @7:95
MUXCY_L un3_reg3_cry_11_cZ (
.DI(GND),
.CI(un3_reg3_cry_10),
.S(un3_reg3_axb_11),
.LO(un3_reg3_cry_11)
);
// @7:95
XORCY un3_reg3_s_10_cZ (
.LI(un3_reg3_axb_10),
.CI(un3_reg3_cry_9),
.O(un3_reg3_s_10)
);
// @7:95
MUXCY_L un3_reg3_cry_10_cZ (
.DI(GND),
.CI(un3_reg3_cry_9),
.S(un3_reg3_axb_10),
.LO(un3_reg3_cry_10)
);
// @7:95
XORCY un3_reg3_s_9_cZ (
.LI(un3_reg3_axb_9),
.CI(un3_reg3_cry_8),
.O(un3_reg3_s_9)
);
// @7:95
MUXCY_L un3_reg3_cry_9_cZ (
.DI(GND),
.CI(un3_reg3_cry_8),
.S(un3_reg3_axb_9),
.LO(un3_reg3_cry_9)
);
// @7:95
XORCY un3_reg3_s_8_cZ (
.LI(un3_reg3_axb_8),
.CI(un3_reg3_cry_7),
.O(un3_reg3_s_8)
);
// @7:95
MUXCY_L un3_reg3_cry_8_cZ (
.DI(GND),
.CI(un3_reg3_cry_7),
.S(un3_reg3_axb_8),
.LO(un3_reg3_cry_8)
);
// @7:95
XORCY un3_reg3_s_7_cZ (
.LI(un3_reg3_axb_7),
.CI(un3_reg3_cry_6),
.O(un3_reg3_s_7)
);
// @7:95
MUXCY_L un3_reg3_cry_7_cZ (
.DI(GND),
.CI(un3_reg3_cry_6),
.S(un3_reg3_axb_7),
.LO(un3_reg3_cry_7)
);
// @7:95
XORCY un3_reg3_s_6_cZ (
.LI(un3_reg3_axb_6),
.CI(un3_reg3_cry_5),
.O(un3_reg3_s_6)
);
// @7:95
MUXCY_L un3_reg3_cry_6_cZ (
.DI(GND),
.CI(un3_reg3_cry_5),
.S(un3_reg3_axb_6),
.LO(un3_reg3_cry_6)
);
// @7:95
XORCY un3_reg3_s_5_cZ (
.LI(un3_reg3_axb_5),
.CI(un3_reg3_cry_4),
.O(un3_reg3_s_5)
);
// @7:95
MUXCY_L un3_reg3_cry_5_cZ (
.DI(GND),
.CI(un3_reg3_cry_4),
.S(un3_reg3_axb_5),
.LO(un3_reg3_cry_5)
);
// @7:95
XORCY un3_reg3_s_4_cZ (
.LI(un3_reg3_axb_4),
.CI(un3_reg3_cry_3),
.O(un3_reg3_s_4)
);
// @7:95
MUXCY_L un3_reg3_cry_4_cZ (
.DI(GND),
.CI(un3_reg3_cry_3),
.S(un3_reg3_axb_4),
.LO(un3_reg3_cry_4)
);
// @7:95
XORCY un3_reg3_s_3_cZ (
.LI(un3_reg3_axb_3),
.CI(un3_reg3_cry_2),
.O(un3_reg3_s_3)
);
// @7:95
MUXCY_L un3_reg3_cry_3_cZ (
.DI(GND),
.CI(un3_reg3_cry_2),
.S(un3_reg3_axb_3),
.LO(un3_reg3_cry_3)
);
// @7:95
XORCY un3_reg3_s_2_cZ (
.LI(un3_reg3_axb_2),
.CI(un3_reg3_cry_1),
.O(un3_reg3_s_2)
);
// @7:95
MUXCY_L un3_reg3_cry_2_cZ (
.DI(GND),
.CI(un3_reg3_cry_1),
.S(un3_reg3_axb_2),
.LO(un3_reg3_cry_2)
);
// @7:95
XORCY un3_reg3_s_1_cZ (
.LI(un3_reg3_axb_1),
.CI(reg3[3]),
.O(un3_reg3_s_1)
);
// @7:95
MUXCY_L un3_reg3_cry_1_cZ (
.DI(GND),
.CI(reg3[3]),
.S(un3_reg3_axb_1),
.LO(un3_reg3_cry_1)
);
// @7:74
XORCY un1_inf_abs0_0_s_19 (
.LI(un1_inf_abs0_0_axb_19),
.CI(un1_inf_abs0_0_cry_18),
.O(un1_inf_abs0_11[19])
);
// @7:74
XORCY un1_inf_abs0_0_s_18 (
.LI(un1_inf_abs0_0_axb_18),
.CI(un1_inf_abs0_0_cry_17),
.O(un1_inf_abs0_11[18])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_18_cZ (
.DI(inf_abs0_2[18]),
.CI(un1_inf_abs0_0_cry_17),
.S(un1_inf_abs0_0_axb_18),
.LO(un1_inf_abs0_0_cry_18)
);
// @7:74
XORCY un1_inf_abs0_0_s_17 (
.LI(un1_inf_abs0_0_axb_17),
.CI(un1_inf_abs0_0_cry_16),
.O(un1_inf_abs0_11[17])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_17_cZ (
.DI(inf_abs0_2[17]),
.CI(un1_inf_abs0_0_cry_16),
.S(un1_inf_abs0_0_axb_17),
.LO(un1_inf_abs0_0_cry_17)
);
// @7:74
XORCY un1_inf_abs0_0_s_16 (
.LI(un1_inf_abs0_0_axb_16),
.CI(un1_inf_abs0_0_cry_15),
.O(un1_inf_abs0_11[16])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_16_cZ (
.DI(inf_abs0_2[16]),
.CI(un1_inf_abs0_0_cry_15),
.S(un1_inf_abs0_0_axb_16),
.LO(un1_inf_abs0_0_cry_16)
);
// @7:74
XORCY un1_inf_abs0_0_s_15 (
.LI(un1_inf_abs0_0_axb_15),
.CI(un1_inf_abs0_0_cry_14),
.O(un1_inf_abs0_11[15])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_15_cZ (
.DI(inf_abs0_2[15]),
.CI(un1_inf_abs0_0_cry_14),
.S(un1_inf_abs0_0_axb_15),
.LO(un1_inf_abs0_0_cry_15)
);
// @7:74
XORCY un1_inf_abs0_0_s_14 (
.LI(un1_inf_abs0_0_axb_14),
.CI(un1_inf_abs0_0_cry_13),
.O(un1_inf_abs0_11[14])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_14_cZ (
.DI(inf_abs0_2[14]),
.CI(un1_inf_abs0_0_cry_13),
.S(un1_inf_abs0_0_axb_14),
.LO(un1_inf_abs0_0_cry_14)
);
// @7:74
XORCY un1_inf_abs0_0_s_13 (
.LI(un1_inf_abs0_0_axb_13),
.CI(un1_inf_abs0_0_cry_12),
.O(un1_inf_abs0_11[13])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_13_cZ (
.DI(inf_abs0_2[13]),
.CI(un1_inf_abs0_0_cry_12),
.S(un1_inf_abs0_0_axb_13),
.LO(un1_inf_abs0_0_cry_13)
);
// @7:74
XORCY un1_inf_abs0_0_s_12 (
.LI(un1_inf_abs0_0_axb_12),
.CI(un1_inf_abs0_0_cry_11),
.O(un1_inf_abs0_11[12])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_12_cZ (
.DI(inf_abs0_2[12]),
.CI(un1_inf_abs0_0_cry_11),
.S(un1_inf_abs0_0_axb_12),
.LO(un1_inf_abs0_0_cry_12)
);
// @7:74
XORCY un1_inf_abs0_0_s_11 (
.LI(un1_inf_abs0_0_axb_11),
.CI(un1_inf_abs0_0_cry_10),
.O(un1_inf_abs0_11[11])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_11_cZ (
.DI(inf_abs0_2[11]),
.CI(un1_inf_abs0_0_cry_10),
.S(un1_inf_abs0_0_axb_11),
.LO(un1_inf_abs0_0_cry_11)
);
// @7:74
XORCY un1_inf_abs0_0_s_10 (
.LI(un1_inf_abs0_0_axb_10),
.CI(un1_inf_abs0_0_cry_9),
.O(un1_inf_abs0_11[10])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_10_cZ (
.DI(inf_abs0_2[10]),
.CI(un1_inf_abs0_0_cry_9),
.S(un1_inf_abs0_0_axb_10),
.LO(un1_inf_abs0_0_cry_10)
);
// @7:74
XORCY un1_inf_abs0_0_s_9 (
.LI(un1_inf_abs0_0_axb_9),
.CI(un1_inf_abs0_0_cry_8),
.O(un1_inf_abs0_11[9])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_9_cZ (
.DI(inf_abs0_2[9]),
.CI(un1_inf_abs0_0_cry_8),
.S(un1_inf_abs0_0_axb_9),
.LO(un1_inf_abs0_0_cry_9)
);
// @7:74
XORCY un1_inf_abs0_0_s_8 (
.LI(un1_inf_abs0_0_axb_8),
.CI(un1_inf_abs0_0_cry_7),
.O(un1_inf_abs0_11[8])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_8_cZ (
.DI(inf_abs0_2[8]),
.CI(un1_inf_abs0_0_cry_7),
.S(un1_inf_abs0_0_axb_8),
.LO(un1_inf_abs0_0_cry_8)
);
// @7:74
XORCY un1_inf_abs0_0_s_7 (
.LI(un1_inf_abs0_0_axb_7),
.CI(un1_inf_abs0_0_cry_6),
.O(un1_inf_abs0_11[7])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_7_cZ (
.DI(inf_abs0_2[7]),
.CI(un1_inf_abs0_0_cry_6),
.S(un1_inf_abs0_0_axb_7),
.LO(un1_inf_abs0_0_cry_7)
);
// @7:74
XORCY un1_inf_abs0_0_s_6 (
.LI(un1_inf_abs0_0_axb_6),
.CI(un1_inf_abs0_0_cry_5),
.O(un1_inf_abs0_11[6])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_6_cZ (
.DI(inf_abs0_2[6]),
.CI(un1_inf_abs0_0_cry_5),
.S(un1_inf_abs0_0_axb_6),
.LO(un1_inf_abs0_0_cry_6)
);
// @7:74
XORCY un1_inf_abs0_0_s_5 (
.LI(un1_inf_abs0_0_axb_5),
.CI(un1_inf_abs0_0_cry_4),
.O(un1_inf_abs0_11[5])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_5_cZ (
.DI(inf_abs0_2[5]),
.CI(un1_inf_abs0_0_cry_4),
.S(un1_inf_abs0_0_axb_5),
.LO(un1_inf_abs0_0_cry_5)
);
// @7:74
XORCY un1_inf_abs0_0_s_4 (
.LI(un1_inf_abs0_0_axb_4),
.CI(un1_inf_abs0_0_cry_3),
.O(un1_inf_abs0_11[4])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_4_cZ (
.DI(inf_abs0_2[4]),
.CI(un1_inf_abs0_0_cry_3),
.S(un1_inf_abs0_0_axb_4),
.LO(un1_inf_abs0_0_cry_4)
);
// @7:74
XORCY un1_inf_abs0_0_s_3 (
.LI(un1_inf_abs0_0_axb_3),
.CI(un1_inf_abs0_0_cry_2),
.O(un1_inf_abs0_11[3])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_3_cZ (
.DI(inf_abs0_2[3]),
.CI(un1_inf_abs0_0_cry_2),
.S(un1_inf_abs0_0_axb_3),
.LO(un1_inf_abs0_0_cry_3)
);
// @7:74
XORCY un1_inf_abs0_0_s_2 (
.LI(un1_inf_abs0_0_axb_2),
.CI(un1_inf_abs0_0_cry_1),
.O(un1_inf_abs0_11[2])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_2_cZ (
.DI(inf_abs0_2[2]),
.CI(un1_inf_abs0_0_cry_1),
.S(un1_inf_abs0_0_axb_2),
.LO(un1_inf_abs0_0_cry_2)
);
// @7:74
XORCY un1_inf_abs0_0_s_1 (
.LI(un1_inf_abs0_0_axb_1),
.CI(un1_inf_abs0_0_cry_0),
.O(un1_inf_abs0_11[1])
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_1_cZ (
.DI(inf_abs0_2[1]),
.CI(un1_inf_abs0_0_cry_0),
.S(un1_inf_abs0_0_axb_1),
.LO(un1_inf_abs0_0_cry_1)
);
// @7:74
MUXCY_L un1_inf_abs0_0_cry_0_cZ (
.DI(inf_abs0_2[0]),
.CI(GND),
.S(un1_inf_abs0_11[0]),
.LO(un1_inf_abs0_0_cry_0)
);
// @7:74
XORCY un1_inf_abs0_s_19 (
.LI(un1_inf_abs0_axb_19),
.CI(un1_inf_abs0_cry_18),
.O(un1_inf_abs0_10[19])
);
// @7:74
XORCY un1_inf_abs0_s_18 (
.LI(un1_inf_abs0_axb_18),
.CI(un1_inf_abs0_cry_17),
.O(un1_inf_abs0_10[18])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_18_cZ (
.DI(inf_abs0_2[18]),
.CI(un1_inf_abs0_cry_17),
.S(un1_inf_abs0_axb_18),
.LO(un1_inf_abs0_cry_18)
);
// @7:74
XORCY un1_inf_abs0_s_17 (
.LI(un1_inf_abs0_axb_17),
.CI(un1_inf_abs0_cry_16),
.O(un1_inf_abs0_10[17])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_17_cZ (
.DI(inf_abs0_2[17]),
.CI(un1_inf_abs0_cry_16),
.S(un1_inf_abs0_axb_17),
.LO(un1_inf_abs0_cry_17)
);
// @7:74
XORCY un1_inf_abs0_s_16 (
.LI(un1_inf_abs0_axb_16),
.CI(un1_inf_abs0_cry_15),
.O(un1_inf_abs0_10[16])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_16_cZ (
.DI(inf_abs0_2[16]),
.CI(un1_inf_abs0_cry_15),
.S(un1_inf_abs0_axb_16),
.LO(un1_inf_abs0_cry_16)
);
// @7:74
XORCY un1_inf_abs0_s_15 (
.LI(un1_inf_abs0_axb_15),
.CI(un1_inf_abs0_cry_14),
.O(un1_inf_abs0_10[15])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_15_cZ (
.DI(inf_abs0_2[15]),
.CI(un1_inf_abs0_cry_14),
.S(un1_inf_abs0_axb_15),
.LO(un1_inf_abs0_cry_15)
);
// @7:74
XORCY un1_inf_abs0_s_14 (
.LI(un1_inf_abs0_axb_14),
.CI(un1_inf_abs0_cry_13),
.O(un1_inf_abs0_10[14])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_14_cZ (
.DI(inf_abs0_2[14]),
.CI(un1_inf_abs0_cry_13),
.S(un1_inf_abs0_axb_14),
.LO(un1_inf_abs0_cry_14)
);
// @7:74
XORCY un1_inf_abs0_s_13 (
.LI(un1_inf_abs0_axb_13),
.CI(un1_inf_abs0_cry_12),
.O(un1_inf_abs0_10[13])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_13_cZ (
.DI(inf_abs0_2[13]),
.CI(un1_inf_abs0_cry_12),
.S(un1_inf_abs0_axb_13),
.LO(un1_inf_abs0_cry_13)
);
// @7:74
XORCY un1_inf_abs0_s_12 (
.LI(un1_inf_abs0_axb_12),
.CI(un1_inf_abs0_cry_11),
.O(un1_inf_abs0_10[12])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_12_cZ (
.DI(inf_abs0_2[12]),
.CI(un1_inf_abs0_cry_11),
.S(un1_inf_abs0_axb_12),
.LO(un1_inf_abs0_cry_12)
);
// @7:74
XORCY un1_inf_abs0_s_11 (
.LI(un1_inf_abs0_axb_11),
.CI(un1_inf_abs0_cry_10),
.O(un1_inf_abs0_10[11])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_11_cZ (
.DI(inf_abs0_2[11]),
.CI(un1_inf_abs0_cry_10),
.S(un1_inf_abs0_axb_11),
.LO(un1_inf_abs0_cry_11)
);
// @7:74
XORCY un1_inf_abs0_s_10 (
.LI(un1_inf_abs0_axb_10),
.CI(un1_inf_abs0_cry_9),
.O(un1_inf_abs0_10[10])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_10_cZ (
.DI(inf_abs0_2[10]),
.CI(un1_inf_abs0_cry_9),
.S(un1_inf_abs0_axb_10),
.LO(un1_inf_abs0_cry_10)
);
// @7:74
XORCY un1_inf_abs0_s_9 (
.LI(un1_inf_abs0_axb_9),
.CI(un1_inf_abs0_cry_8),
.O(un1_inf_abs0_10[9])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_9_cZ (
.DI(inf_abs0_2[9]),
.CI(un1_inf_abs0_cry_8),
.S(un1_inf_abs0_axb_9),
.LO(un1_inf_abs0_cry_9)
);
// @7:74
XORCY un1_inf_abs0_s_8 (
.LI(un1_inf_abs0_axb_8),
.CI(un1_inf_abs0_cry_7),
.O(un1_inf_abs0_10[8])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_8_cZ (
.DI(inf_abs0_2[8]),
.CI(un1_inf_abs0_cry_7),
.S(un1_inf_abs0_axb_8),
.LO(un1_inf_abs0_cry_8)
);
// @7:74
XORCY un1_inf_abs0_s_7 (
.LI(un1_inf_abs0_axb_7),
.CI(un1_inf_abs0_cry_6),
.O(un1_inf_abs0_10[7])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_7_cZ (
.DI(inf_abs0_2[7]),
.CI(un1_inf_abs0_cry_6),
.S(un1_inf_abs0_axb_7),
.LO(un1_inf_abs0_cry_7)
);
// @7:74
XORCY un1_inf_abs0_s_6 (
.LI(un1_inf_abs0_axb_6),
.CI(un1_inf_abs0_cry_5),
.O(un1_inf_abs0_10[6])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_6_cZ (
.DI(inf_abs0_2[6]),
.CI(un1_inf_abs0_cry_5),
.S(un1_inf_abs0_axb_6),
.LO(un1_inf_abs0_cry_6)
);
// @7:74
XORCY un1_inf_abs0_s_5 (
.LI(un1_inf_abs0_axb_5),
.CI(un1_inf_abs0_cry_4),
.O(un1_inf_abs0_10[5])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_5_cZ (
.DI(inf_abs0_2[5]),
.CI(un1_inf_abs0_cry_4),
.S(un1_inf_abs0_axb_5),
.LO(un1_inf_abs0_cry_5)
);
// @7:74
XORCY un1_inf_abs0_s_4 (
.LI(un1_inf_abs0_axb_4),
.CI(un1_inf_abs0_cry_3),
.O(un1_inf_abs0_10[4])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_4_cZ (
.DI(inf_abs0_2[4]),
.CI(un1_inf_abs0_cry_3),
.S(un1_inf_abs0_axb_4),
.LO(un1_inf_abs0_cry_4)
);
// @7:74
XORCY un1_inf_abs0_s_3 (
.LI(un1_inf_abs0_axb_3),
.CI(un1_inf_abs0_cry_2),
.O(un1_inf_abs0_10[3])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_3_cZ (
.DI(inf_abs0_2[3]),
.CI(un1_inf_abs0_cry_2),
.S(un1_inf_abs0_axb_3),
.LO(un1_inf_abs0_cry_3)
);
// @7:74
XORCY un1_inf_abs0_s_2 (
.LI(un1_inf_abs0_axb_2),
.CI(un1_inf_abs0_cry_1),
.O(un1_inf_abs0_10[2])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_2_cZ (
.DI(inf_abs0_2[2]),
.CI(un1_inf_abs0_cry_1),
.S(un1_inf_abs0_axb_2),
.LO(un1_inf_abs0_cry_2)
);
// @7:74
XORCY un1_inf_abs0_s_1 (
.LI(un1_inf_abs0_axb_1),
.CI(un1_inf_abs0_cry_0),
.O(un1_inf_abs0_10[1])
);
// @7:74
MUXCY_L un1_inf_abs0_cry_1_cZ (
.DI(inf_abs0_2[1]),
.CI(un1_inf_abs0_cry_0),
.S(un1_inf_abs0_axb_1),
.LO(un1_inf_abs0_cry_1)
);
// @7:74
MUXCY_L un1_inf_abs0_cry_0_cZ (
.DI(inf_abs0_2[0]),
.CI(GND),
.S(un1_inf_abs0_10[0]),
.LO(un1_inf_abs0_cry_0)
);
// @7:358
XORCY un32_reg0_s_29_cZ (
.LI(un32_reg0_axb_29),
.CI(un32_reg0_cry_28),
.O(un32_reg0_s_29)
);
// @7:358
XORCY un32_reg0_s_28_cZ (
.LI(un32_reg0_axb_28),
.CI(un32_reg0_cry_27),
.O(un32_reg0_s_28)
);
// @7:358
MUXCY_L un32_reg0_cry_28_cZ (
.DI(r_4[28]),
.CI(un32_reg0_cry_27),
.S(un32_reg0_axb_28),
.LO(un32_reg0_cry_28)
);
// @7:358
XORCY un32_reg0_s_27_cZ (
.LI(un32_reg0_axb_27),
.CI(un32_reg0_cry_26),
.O(un32_reg0_s_27)
);
// @7:358
MUXCY_L un32_reg0_cry_27_cZ (
.DI(r_4[27]),
.CI(un32_reg0_cry_26),
.S(un32_reg0_axb_27),
.LO(un32_reg0_cry_27)
);
// @7:358
XORCY un32_reg0_s_26_cZ (
.LI(un32_reg0_axb_26),
.CI(un32_reg0_cry_25),
.O(un32_reg0_s_26)
);
// @7:358
MUXCY_L un32_reg0_cry_26_cZ (
.DI(r_4[26]),
.CI(un32_reg0_cry_25),
.S(un32_reg0_axb_26),
.LO(un32_reg0_cry_26)
);
// @7:358
XORCY un32_reg0_s_25_cZ (
.LI(un32_reg0_axb_25),
.CI(un32_reg0_cry_24),
.O(un32_reg0_s_25)
);
// @7:358
MUXCY_L un32_reg0_cry_25_cZ (
.DI(r_4[25]),
.CI(un32_reg0_cry_24),
.S(un32_reg0_axb_25),
.LO(un32_reg0_cry_25)
);
// @7:358
XORCY un32_reg0_s_24_cZ (
.LI(un32_reg0_axb_24),
.CI(un32_reg0_cry_23),
.O(un32_reg0_s_24)
);
// @7:358
MUXCY_L un32_reg0_cry_24_cZ (
.DI(r_4[24]),
.CI(un32_reg0_cry_23),
.S(un32_reg0_axb_24),
.LO(un32_reg0_cry_24)
);
// @7:358
XORCY un32_reg0_s_23_cZ (
.LI(un32_reg0_axb_23),
.CI(un32_reg0_cry_22),
.O(un32_reg0_s_23)
);
// @7:358
MUXCY_L un32_reg0_cry_23_cZ (
.DI(r_4[23]),
.CI(un32_reg0_cry_22),
.S(un32_reg0_axb_23),
.LO(un32_reg0_cry_23)
);
// @7:358
XORCY un32_reg0_s_22_cZ (
.LI(un32_reg0_axb_22),
.CI(un32_reg0_cry_21),
.O(un32_reg0_s_22)
);
// @7:358
MUXCY_L un32_reg0_cry_22_cZ (
.DI(r_4[22]),
.CI(un32_reg0_cry_21),
.S(un32_reg0_axb_22),
.LO(un32_reg0_cry_22)
);
// @7:358
XORCY un32_reg0_s_21_cZ (
.LI(un32_reg0_axb_21),
.CI(un32_reg0_cry_20),
.O(un32_reg0_s_21)
);
// @7:358
MUXCY_L un32_reg0_cry_21_cZ (
.DI(r_4[21]),
.CI(un32_reg0_cry_20),
.S(un32_reg0_axb_21),
.LO(un32_reg0_cry_21)
);
// @7:358
XORCY un32_reg0_s_20_cZ (
.LI(un32_reg0_axb_20),
.CI(un32_reg0_cry_19),
.O(un32_reg0_s_20)
);
// @7:358
MUXCY_L un32_reg0_cry_20_cZ (
.DI(r_4[20]),
.CI(un32_reg0_cry_19),
.S(un32_reg0_axb_20),
.LO(un32_reg0_cry_20)
);
// @7:358
XORCY un32_reg0_s_19_cZ (
.LI(un32_reg0_axb_19),
.CI(un32_reg0_cry_18),
.O(un32_reg0_s_19)
);
// @7:358
MUXCY_L un32_reg0_cry_19_cZ (
.DI(r_4[19]),
.CI(un32_reg0_cry_18),
.S(un32_reg0_axb_19),
.LO(un32_reg0_cry_19)
);
// @7:358
XORCY un32_reg0_s_18_cZ (
.LI(un32_reg0_axb_18),
.CI(un32_reg0_cry_17),
.O(un32_reg0_s_18)
);
// @7:358
MUXCY_L un32_reg0_cry_18_cZ (
.DI(r_4[18]),
.CI(un32_reg0_cry_17),
.S(un32_reg0_axb_18),
.LO(un32_reg0_cry_18)
);
// @7:358
XORCY un32_reg0_s_17_cZ (
.LI(un32_reg0_axb_17),
.CI(un32_reg0_cry_16),
.O(un32_reg0_s_17)
);
// @7:358
MUXCY_L un32_reg0_cry_17_cZ (
.DI(r_4[17]),
.CI(un32_reg0_cry_16),
.S(un32_reg0_axb_17),
.LO(un32_reg0_cry_17)
);
// @7:358
XORCY un32_reg0_s_16_cZ (
.LI(un32_reg0_axb_16),
.CI(un32_reg0_cry_15),
.O(un32_reg0_s_16)
);
// @7:358
MUXCY_L un32_reg0_cry_16_cZ (
.DI(r_4[16]),
.CI(un32_reg0_cry_15),
.S(un32_reg0_axb_16),
.LO(un32_reg0_cry_16)
);
// @7:358
XORCY un32_reg0_s_15_cZ (
.LI(un32_reg0_axb_15),
.CI(un32_reg0_cry_14),
.O(un32_reg0_s_15)
);
// @7:358
MUXCY_L un32_reg0_cry_15_cZ (
.DI(r_4[15]),
.CI(un32_reg0_cry_14),
.S(un32_reg0_axb_15),
.LO(un32_reg0_cry_15)
);
// @7:358
XORCY un32_reg0_s_14_cZ (
.LI(un32_reg0_axb_14),
.CI(un32_reg0_cry_13),
.O(un32_reg0_s_14)
);
// @7:358
MUXCY_L un32_reg0_cry_14_cZ (
.DI(r_4[14]),
.CI(un32_reg0_cry_13),
.S(un32_reg0_axb_14),
.LO(un32_reg0_cry_14)
);
// @7:358
XORCY un32_reg0_s_13_cZ (
.LI(un32_reg0_axb_13),
.CI(un32_reg0_cry_12),
.O(un32_reg0_s_13)
);
// @7:358
MUXCY_L un32_reg0_cry_13_cZ (
.DI(r_4[13]),
.CI(un32_reg0_cry_12),
.S(un32_reg0_axb_13),
.LO(un32_reg0_cry_13)
);
// @7:358
XORCY un32_reg0_s_12_cZ (
.LI(un32_reg0_axb_12),
.CI(un32_reg0_cry_11),
.O(un32_reg0_s_12)
);
// @7:358
MUXCY_L un32_reg0_cry_12_cZ (
.DI(r_4[12]),
.CI(un32_reg0_cry_11),
.S(un32_reg0_axb_12),
.LO(un32_reg0_cry_12)
);
// @7:358
XORCY un32_reg0_s_11_cZ (
.LI(un32_reg0_axb_11),
.CI(un32_reg0_cry_10),
.O(un32_reg0_s_11)
);
// @7:358
MUXCY_L un32_reg0_cry_11_cZ (
.DI(r_4[11]),
.CI(un32_reg0_cry_10),
.S(un32_reg0_axb_11),
.LO(un32_reg0_cry_11)
);
// @7:358
XORCY un32_reg0_s_10_cZ (
.LI(un32_reg0_axb_10),
.CI(un32_reg0_cry_9),
.O(un32_reg0_s_10)
);
// @7:358
MUXCY_L un32_reg0_cry_10_cZ (
.DI(r_4[10]),
.CI(un32_reg0_cry_9),
.S(un32_reg0_axb_10),
.LO(un32_reg0_cry_10)
);
// @7:358
XORCY un32_reg0_s_9_cZ (
.LI(un32_reg0_axb_9),
.CI(un32_reg0_cry_8),
.O(un32_reg0_s_9)
);
// @7:358
MUXCY_L un32_reg0_cry_9_cZ (
.DI(r_4[9]),
.CI(un32_reg0_cry_8),
.S(un32_reg0_axb_9),
.LO(un32_reg0_cry_9)
);
// @7:358
XORCY un32_reg0_s_8_cZ (
.LI(un32_reg0_axb_8),
.CI(un32_reg0_cry_7),
.O(un32_reg0_s_8)
);
// @7:358
MUXCY_L un32_reg0_cry_8_cZ (
.DI(r_4[8]),
.CI(un32_reg0_cry_7),
.S(un32_reg0_axb_8),
.LO(un32_reg0_cry_8)
);
// @7:358
XORCY un32_reg0_s_7_cZ (
.LI(un32_reg0_axb_7),
.CI(un32_reg0_cry_6),
.O(un32_reg0_s_7)
);
// @7:358
MUXCY_L un32_reg0_cry_7_cZ (
.DI(r_4[7]),
.CI(un32_reg0_cry_6),
.S(un32_reg0_axb_7),
.LO(un32_reg0_cry_7)
);
// @7:358
XORCY un32_reg0_s_6_cZ (
.LI(un32_reg0_axb_6),
.CI(un32_reg0_cry_5),
.O(un32_reg0_s_6)
);
// @7:358
MUXCY_L un32_reg0_cry_6_cZ (
.DI(r_4[6]),
.CI(un32_reg0_cry_5),
.S(un32_reg0_axb_6),
.LO(un32_reg0_cry_6)
);
// @7:358
XORCY un32_reg0_s_5_cZ (
.LI(un32_reg0_axb_5),
.CI(un32_reg0_cry_4),
.O(un32_reg0_s_5)
);
// @7:358
MUXCY_L un32_reg0_cry_5_cZ (
.DI(r_4[5]),
.CI(un32_reg0_cry_4),
.S(un32_reg0_axb_5),
.LO(un32_reg0_cry_5)
);
// @7:358
XORCY un32_reg0_s_4_cZ (
.LI(un32_reg0_axb_4),
.CI(un32_reg0_cry_3),
.O(un32_reg0_s_4)
);
// @7:358
MUXCY_L un32_reg0_cry_4_cZ (
.DI(r_4[4]),
.CI(un32_reg0_cry_3),
.S(un32_reg0_axb_4),
.LO(un32_reg0_cry_4)
);
// @7:358
XORCY un32_reg0_s_3_cZ (
.LI(un32_reg0_axb_3),
.CI(un32_reg0_cry_2),
.O(un32_reg0_s_3)
);
// @7:358
MUXCY_L un32_reg0_cry_3_cZ (
.DI(r_4[3]),
.CI(un32_reg0_cry_2),
.S(un32_reg0_axb_3),
.LO(un32_reg0_cry_3)
);
// @7:358
XORCY un32_reg0_s_2_cZ (
.LI(un32_reg0_axb_2),
.CI(un32_reg0_cry_1),
.O(un32_reg0_s_2)
);
// @7:358
MUXCY_L un32_reg0_cry_2_cZ (
.DI(N_28),
.CI(un32_reg0_cry_1),
.S(un32_reg0_axb_2),
.LO(un32_reg0_cry_2)
);
// @7:358
XORCY un32_reg0_s_1_cZ (
.LI(un32_reg0_axb_1),
.CI(un32_reg0_cry_0),
.O(un32_reg0_s_1)
);
// @7:358
MUXCY_L un32_reg0_cry_1_cZ (
.DI(r_4[1]),
.CI(un32_reg0_cry_0),
.S(un32_reg0_axb_1),
.LO(un32_reg0_cry_1)
);
// @7:358
MUXCY_L un32_reg0_cry_0_cZ (
.DI(r_4[0]),
.CI(VCC),
.S(N_1035),
.LO(un32_reg0_cry_0)
);
// @7:318
XORCY un11_reg0_s_29_cZ (
.LI(un11_reg0_axb_29),
.CI(un11_reg0_cry_28),
.O(un11_reg0_s_29)
);
// @7:318
XORCY un11_reg0_s_28_cZ (
.LI(un11_reg0_axb_28),
.CI(un11_reg0_cry_27),
.O(un11_reg0_s_28)
);
// @7:318
MUXCY_L un11_reg0_cry_28_cZ (
.DI(m_2[28]),
.CI(un11_reg0_cry_27),
.S(un11_reg0_axb_28),
.LO(un11_reg0_cry_28)
);
// @7:318
XORCY un11_reg0_s_27_cZ (
.LI(un11_reg0_axb_27),
.CI(un11_reg0_cry_26),
.O(un11_reg0_s_27)
);
// @7:318
MUXCY_L un11_reg0_cry_27_cZ (
.DI(m_2[27]),
.CI(un11_reg0_cry_26),
.S(un11_reg0_axb_27),
.LO(un11_reg0_cry_27)
);
// @7:318
XORCY un11_reg0_s_26_cZ (
.LI(un11_reg0_axb_26),
.CI(un11_reg0_cry_25),
.O(un11_reg0_s_26)
);
// @7:318
MUXCY_L un11_reg0_cry_26_cZ (
.DI(m_2[26]),
.CI(un11_reg0_cry_25),
.S(un11_reg0_axb_26),
.LO(un11_reg0_cry_26)
);
// @7:318
XORCY un11_reg0_s_25_cZ (
.LI(un11_reg0_axb_25),
.CI(un11_reg0_cry_24),
.O(un11_reg0_s_25)
);
// @7:318
MUXCY_L un11_reg0_cry_25_cZ (
.DI(m_2[25]),
.CI(un11_reg0_cry_24),
.S(un11_reg0_axb_25),
.LO(un11_reg0_cry_25)
);
// @7:318
XORCY un11_reg0_s_24_cZ (
.LI(un11_reg0_axb_24),
.CI(un11_reg0_cry_23),
.O(un11_reg0_s_24)
);
// @7:318
MUXCY_L un11_reg0_cry_24_cZ (
.DI(m_2[24]),
.CI(un11_reg0_cry_23),
.S(un11_reg0_axb_24),
.LO(un11_reg0_cry_24)
);
// @7:318
XORCY un11_reg0_s_23_cZ (
.LI(un11_reg0_axb_23),
.CI(un11_reg0_cry_22),
.O(un11_reg0_s_23)
);
// @7:318
MUXCY_L un11_reg0_cry_23_cZ (
.DI(m_2[23]),
.CI(un11_reg0_cry_22),
.S(un11_reg0_axb_23),
.LO(un11_reg0_cry_23)
);
// @7:318
XORCY un11_reg0_s_22_cZ (
.LI(un11_reg0_axb_22),
.CI(un11_reg0_cry_21),
.O(un11_reg0_s_22)
);
// @7:318
MUXCY_L un11_reg0_cry_22_cZ (
.DI(m_2[22]),
.CI(un11_reg0_cry_21),
.S(un11_reg0_axb_22),
.LO(un11_reg0_cry_22)
);
// @7:318
XORCY un11_reg0_s_21_cZ (
.LI(un11_reg0_axb_21),
.CI(un11_reg0_cry_20),
.O(un11_reg0_s_21)
);
// @7:318
MUXCY_L un11_reg0_cry_21_cZ (
.DI(m_2[21]),
.CI(un11_reg0_cry_20),
.S(un11_reg0_axb_21),
.LO(un11_reg0_cry_21)
);
// @7:318
XORCY un11_reg0_s_20_cZ (
.LI(un11_reg0_axb_20),
.CI(un11_reg0_cry_19),
.O(un11_reg0_s_20)
);
// @7:318
MUXCY_L un11_reg0_cry_20_cZ (
.DI(m_2[20]),
.CI(un11_reg0_cry_19),
.S(un11_reg0_axb_20),
.LO(un11_reg0_cry_20)
);
// @7:318
XORCY un11_reg0_s_19_cZ (
.LI(un11_reg0_axb_19),
.CI(un11_reg0_cry_18),
.O(un11_reg0_s_19)
);
// @7:318
MUXCY_L un11_reg0_cry_19_cZ (
.DI(r_4[19]),
.CI(un11_reg0_cry_18),
.S(un11_reg0_axb_19),
.LO(un11_reg0_cry_19)
);
// @7:318
XORCY un11_reg0_s_18_cZ (
.LI(un11_reg0_axb_18),
.CI(un11_reg0_cry_17),
.O(un11_reg0_s_18)
);
// @7:318
MUXCY_L un11_reg0_cry_18_cZ (
.DI(r_4[18]),
.CI(un11_reg0_cry_17),
.S(un11_reg0_axb_18),
.LO(un11_reg0_cry_18)
);
// @7:318
XORCY un11_reg0_s_17_cZ (
.LI(un11_reg0_axb_17),
.CI(un11_reg0_cry_16),
.O(un11_reg0_s_17)
);
// @7:318
MUXCY_L un11_reg0_cry_17_cZ (
.DI(r_4[17]),
.CI(un11_reg0_cry_16),
.S(un11_reg0_axb_17),
.LO(un11_reg0_cry_17)
);
// @7:318
XORCY un11_reg0_s_16_cZ (
.LI(un11_reg0_axb_16),
.CI(un11_reg0_cry_15),
.O(un11_reg0_s_16)
);
// @7:318
MUXCY_L un11_reg0_cry_16_cZ (
.DI(r_4[16]),
.CI(un11_reg0_cry_15),
.S(un11_reg0_axb_16),
.LO(un11_reg0_cry_16)
);
// @7:318
XORCY un11_reg0_s_15_cZ (
.LI(un11_reg0_axb_15),
.CI(un11_reg0_cry_14),
.O(un11_reg0_s_15)
);
// @7:318
MUXCY_L un11_reg0_cry_15_cZ (
.DI(r_4[15]),
.CI(un11_reg0_cry_14),
.S(un11_reg0_axb_15),
.LO(un11_reg0_cry_15)
);
// @7:318
XORCY un11_reg0_s_14_cZ (
.LI(un11_reg0_axb_14),
.CI(un11_reg0_cry_13),
.O(un11_reg0_s_14)
);
// @7:318
MUXCY_L un11_reg0_cry_14_cZ (
.DI(r_4[14]),
.CI(un11_reg0_cry_13),
.S(un11_reg0_axb_14),
.LO(un11_reg0_cry_14)
);
// @7:318
XORCY un11_reg0_s_13_cZ (
.LI(un11_reg0_axb_13),
.CI(un11_reg0_cry_12),
.O(un11_reg0_s_13)
);
// @7:318
MUXCY_L un11_reg0_cry_13_cZ (
.DI(r_4[13]),
.CI(un11_reg0_cry_12),
.S(un11_reg0_axb_13),
.LO(un11_reg0_cry_13)
);
// @7:318
XORCY un11_reg0_s_12_cZ (
.LI(un11_reg0_axb_12),
.CI(un11_reg0_cry_11),
.O(un11_reg0_s_12)
);
// @7:318
MUXCY_L un11_reg0_cry_12_cZ (
.DI(r_4[12]),
.CI(un11_reg0_cry_11),
.S(un11_reg0_axb_12),
.LO(un11_reg0_cry_12)
);
// @7:318
XORCY un11_reg0_s_11_cZ (
.LI(un11_reg0_axb_11),
.CI(un11_reg0_cry_10),
.O(un11_reg0_s_11)
);
// @7:318
MUXCY_L un11_reg0_cry_11_cZ (
.DI(r_4[11]),
.CI(un11_reg0_cry_10),
.S(un11_reg0_axb_11),
.LO(un11_reg0_cry_11)
);
// @7:318
XORCY un11_reg0_s_10_cZ (
.LI(un11_reg0_axb_10),
.CI(un11_reg0_cry_9),
.O(un11_reg0_s_10)
);
// @7:318
MUXCY_L un11_reg0_cry_10_cZ (
.DI(r_4[10]),
.CI(un11_reg0_cry_9),
.S(un11_reg0_axb_10),
.LO(un11_reg0_cry_10)
);
// @7:318
XORCY un11_reg0_s_9_cZ (
.LI(un11_reg0_axb_9),
.CI(un11_reg0_cry_8),
.O(un11_reg0_s_9)
);
// @7:318
MUXCY_L un11_reg0_cry_9_cZ (
.DI(r_4[9]),
.CI(un11_reg0_cry_8),
.S(un11_reg0_axb_9),
.LO(un11_reg0_cry_9)
);
// @7:318
XORCY un11_reg0_s_8_cZ (
.LI(un11_reg0_axb_8),
.CI(un11_reg0_cry_7),
.O(un11_reg0_s_8)
);
// @7:318
MUXCY_L un11_reg0_cry_8_cZ (
.DI(r_4[8]),
.CI(un11_reg0_cry_7),
.S(un11_reg0_axb_8),
.LO(un11_reg0_cry_8)
);
// @7:318
XORCY un11_reg0_s_7_cZ (
.LI(un11_reg0_axb_7),
.CI(un11_reg0_cry_6),
.O(un11_reg0_s_7)
);
// @7:318
MUXCY_L un11_reg0_cry_7_cZ (
.DI(r_4[7]),
.CI(un11_reg0_cry_6),
.S(un11_reg0_axb_7),
.LO(un11_reg0_cry_7)
);
// @7:318
XORCY un11_reg0_s_6_cZ (
.LI(un11_reg0_axb_6),
.CI(un11_reg0_cry_5),
.O(un11_reg0_s_6)
);
// @7:318
MUXCY_L un11_reg0_cry_6_cZ (
.DI(r_4[6]),
.CI(un11_reg0_cry_5),
.S(un11_reg0_axb_6),
.LO(un11_reg0_cry_6)
);
// @7:318
XORCY un11_reg0_s_5_cZ (
.LI(un11_reg0_axb_5),
.CI(un11_reg0_cry_4),
.O(un11_reg0_s_5)
);
// @7:318
MUXCY_L un11_reg0_cry_5_cZ (
.DI(r_4[5]),
.CI(un11_reg0_cry_4),
.S(un11_reg0_axb_5),
.LO(un11_reg0_cry_5)
);
// @7:318
XORCY un11_reg0_s_4_cZ (
.LI(un11_reg0_axb_4),
.CI(un11_reg0_cry_3),
.O(un11_reg0_s_4)
);
// @7:318
MUXCY_L un11_reg0_cry_4_cZ (
.DI(r_4[4]),
.CI(un11_reg0_cry_3),
.S(un11_reg0_axb_4),
.LO(un11_reg0_cry_4)
);
// @7:318
XORCY un11_reg0_s_3_cZ (
.LI(un11_reg0_axb_3),
.CI(un11_reg0_cry_2),
.O(un11_reg0_s_3)
);
// @7:318
MUXCY_L un11_reg0_cry_3_cZ (
.DI(r_4[3]),
.CI(un11_reg0_cry_2),
.S(un11_reg0_axb_3),
.LO(un11_reg0_cry_3)
);
// @7:318
XORCY un11_reg0_s_2_cZ (
.LI(un11_reg0_axb_2),
.CI(un11_reg0_cry_1),
.O(un11_reg0_s_2)
);
// @7:318
MUXCY_L un11_reg0_cry_2_cZ (
.DI(N_28),
.CI(un11_reg0_cry_1),
.S(un11_reg0_axb_2),
.LO(un11_reg0_cry_2)
);
// @7:318
XORCY un11_reg0_s_1_cZ (
.LI(un11_reg0_axb_1),
.CI(un11_reg0_cry_0),
.O(un11_reg0_s_1)
);
// @7:318
MUXCY_L un11_reg0_cry_1_cZ (
.DI(r_4[1]),
.CI(un11_reg0_cry_0),
.S(un11_reg0_axb_1),
.LO(un11_reg0_cry_1)
);
// @7:318
MUXCY_L un11_reg0_cry_0_cZ (
.DI(r_4[0]),
.CI(GND),
.S(un11_reg0_axb_0),
.LO(un11_reg0_cry_0)
);
// @7:466
XORCY un3_t_s_31_cZ (
.LI(un3_t_axb_31),
.CI(un3_t_cry_30),
.O(un3_t_s_31)
);
// @7:466
XORCY un3_t_s_30_cZ (
.LI(un3_t_axb_30),
.CI(un3_t_cry_29),
.O(un3_t_s_30)
);
// @7:466
MUXCY_L un3_t_cry_30_cZ (
.DI(GND),
.CI(un3_t_cry_29),
.S(un3_t_axb_30),
.LO(un3_t_cry_30)
);
// @7:466
XORCY un3_t_s_29_cZ (
.LI(un3_t_axb_29),
.CI(un3_t_cry_28),
.O(un3_t_s_29)
);
// @7:466
MUXCY_L un3_t_cry_29_cZ (
.DI(GND),
.CI(un3_t_cry_28),
.S(un3_t_axb_29),
.LO(un3_t_cry_29)
);
// @7:466
XORCY un3_t_s_28_cZ (
.LI(un3_t_axb_28),
.CI(un3_t_cry_27),
.O(un3_t_s_28)
);
// @7:466
MUXCY_L un3_t_cry_28_cZ (
.DI(GND),
.CI(un3_t_cry_27),
.S(un3_t_axb_28),
.LO(un3_t_cry_28)
);
// @7:466
XORCY un3_t_s_27_cZ (
.LI(un3_t_axb_27),
.CI(un3_t_cry_26),
.O(un3_t_s_27)
);
// @7:466
MUXCY_L un3_t_cry_27_cZ (
.DI(GND),
.CI(un3_t_cry_26),
.S(un3_t_axb_27),
.LO(un3_t_cry_27)
);
// @7:466
XORCY un3_t_s_26_cZ (
.LI(un3_t_axb_26),
.CI(un3_t_cry_25),
.O(un3_t_s_26)
);
// @7:466
MUXCY_L un3_t_cry_26_cZ (
.DI(GND),
.CI(un3_t_cry_25),
.S(un3_t_axb_26),
.LO(un3_t_cry_26)
);
// @7:466
XORCY un3_t_s_25_cZ (
.LI(un3_t_axb_25),
.CI(un3_t_cry_24),
.O(un3_t_s_25)
);
// @7:466
MUXCY_L un3_t_cry_25_cZ (
.DI(GND),
.CI(un3_t_cry_24),
.S(un3_t_axb_25),
.LO(un3_t_cry_25)
);
// @7:466
XORCY un3_t_s_24_cZ (
.LI(un3_t_axb_24),
.CI(un3_t_cry_23),
.O(un3_t_s_24)
);
// @7:466
MUXCY_L un3_t_cry_24_cZ (
.DI(GND),
.CI(un3_t_cry_23),
.S(un3_t_axb_24),
.LO(un3_t_cry_24)
);
// @7:466
XORCY un3_t_s_23_cZ (
.LI(un3_t_axb_23),
.CI(un3_t_cry_22),
.O(un3_t_s_23)
);
// @7:466
MUXCY_L un3_t_cry_23_cZ (
.DI(GND),
.CI(un3_t_cry_22),
.S(un3_t_axb_23),
.LO(un3_t_cry_23)
);
// @7:466
XORCY un3_t_s_22_cZ (
.LI(un3_t_axb_22),
.CI(un3_t_cry_21),
.O(un3_t_s_22)
);
// @7:466
MUXCY_L un3_t_cry_22_cZ (
.DI(GND),
.CI(un3_t_cry_21),
.S(un3_t_axb_22),
.LO(un3_t_cry_22)
);
// @7:466
XORCY un3_t_s_21_cZ (
.LI(un3_t_axb_21),
.CI(un3_t_cry_20),
.O(un3_t_s_21)
);
// @7:466
MUXCY_L un3_t_cry_21_cZ (
.DI(GND),
.CI(un3_t_cry_20),
.S(un3_t_axb_21),
.LO(un3_t_cry_21)
);
// @7:466
XORCY un3_t_s_20_cZ (
.LI(un3_t_axb_20),
.CI(un3_t_cry_19),
.O(un3_t_s_20)
);
// @7:466
MUXCY_L un3_t_cry_20_cZ (
.DI(GND),
.CI(un3_t_cry_19),
.S(un3_t_axb_20),
.LO(un3_t_cry_20)
);
// @7:466
XORCY un3_t_s_19_cZ (
.LI(un3_t_axb_19),
.CI(un3_t_cry_18),
.O(un3_t_s_19)
);
// @7:466
MUXCY_L un3_t_cry_19_cZ (
.DI(GND),
.CI(un3_t_cry_18),
.S(un3_t_axb_19),
.LO(un3_t_cry_19)
);
// @7:466
XORCY un3_t_s_18_cZ (
.LI(un3_t_axb_18),
.CI(un3_t_cry_17),
.O(un3_t_s_18)
);
// @7:466
MUXCY_L un3_t_cry_18_cZ (
.DI(GND),
.CI(un3_t_cry_17),
.S(un3_t_axb_18),
.LO(un3_t_cry_18)
);
// @7:466
XORCY un3_t_s_17_cZ (
.LI(un3_t_axb_17),
.CI(un3_t_cry_16),
.O(un3_t_s_17)
);
// @7:466
MUXCY_L un3_t_cry_17_cZ (
.DI(GND),
.CI(un3_t_cry_16),
.S(un3_t_axb_17),
.LO(un3_t_cry_17)
);
// @7:466
XORCY un3_t_s_16_cZ (
.LI(un3_t_axb_16),
.CI(un3_t_cry_15),
.O(un3_t_s_16)
);
// @7:466
MUXCY_L un3_t_cry_16_cZ (
.DI(GND),
.CI(un3_t_cry_15),
.S(un3_t_axb_16),
.LO(un3_t_cry_16)
);
// @7:466
XORCY un3_t_s_15_cZ (
.LI(un3_t_axb_15),
.CI(un3_t_cry_14),
.O(un3_t_s_15)
);
// @7:466
MUXCY_L un3_t_cry_15_cZ (
.DI(GND),
.CI(un3_t_cry_14),
.S(un3_t_axb_15),
.LO(un3_t_cry_15)
);
// @7:466
XORCY un3_t_s_14_cZ (
.LI(un3_t_axb_14),
.CI(un3_t_cry_13),
.O(un3_t_s_14)
);
// @7:466
MUXCY_L un3_t_cry_14_cZ (
.DI(GND),
.CI(un3_t_cry_13),
.S(un3_t_axb_14),
.LO(un3_t_cry_14)
);
// @7:466
XORCY un3_t_s_13_cZ (
.LI(un3_t_axb_13),
.CI(un3_t_cry_12),
.O(un3_t_s_13)
);
// @7:466
MUXCY_L un3_t_cry_13_cZ (
.DI(GND),
.CI(un3_t_cry_12),
.S(un3_t_axb_13),
.LO(un3_t_cry_13)
);
// @7:466
XORCY un3_t_s_12_cZ (
.LI(un3_t_axb_12),
.CI(un3_t_cry_11),
.O(un3_t_s_12)
);
// @7:466
MUXCY_L un3_t_cry_12_cZ (
.DI(GND),
.CI(un3_t_cry_11),
.S(un3_t_axb_12),
.LO(un3_t_cry_12)
);
// @7:466
XORCY un3_t_s_11_cZ (
.LI(un3_t_axb_11),
.CI(un3_t_cry_10),
.O(un3_t_s_11)
);
// @7:466
MUXCY_L un3_t_cry_11_cZ (
.DI(GND),
.CI(un3_t_cry_10),
.S(un3_t_axb_11),
.LO(un3_t_cry_11)
);
// @7:466
XORCY un3_t_s_10_cZ (
.LI(un3_t_axb_10),
.CI(un3_t_cry_9),
.O(un3_t_s_10)
);
// @7:466
MUXCY_L un3_t_cry_10_cZ (
.DI(GND),
.CI(un3_t_cry_9),
.S(un3_t_axb_10),
.LO(un3_t_cry_10)
);
// @7:466
XORCY un3_t_s_9_cZ (
.LI(un3_t_axb_9),
.CI(un3_t_cry_8),
.O(un3_t_s_9)
);
// @7:466
MUXCY_L un3_t_cry_9_cZ (
.DI(GND),
.CI(un3_t_cry_8),
.S(un3_t_axb_9),
.LO(un3_t_cry_9)
);
// @7:466
XORCY un3_t_s_8_cZ (
.LI(un3_t_axb_8),
.CI(un3_t_cry_7),
.O(un3_t_s_8)
);
// @7:466
MUXCY_L un3_t_cry_8_cZ (
.DI(GND),
.CI(un3_t_cry_7),
.S(un3_t_axb_8),
.LO(un3_t_cry_8)
);
// @7:466
XORCY un3_t_s_7_cZ (
.LI(un3_t_axb_7),
.CI(un3_t_cry_6),
.O(un3_t_s_7)
);
// @7:466
MUXCY_L un3_t_cry_7_cZ (
.DI(GND),
.CI(un3_t_cry_6),
.S(un3_t_axb_7),
.LO(un3_t_cry_7)
);
// @7:466
XORCY un3_t_s_6_cZ (
.LI(un3_t_axb_6),
.CI(un3_t_cry_5),
.O(un3_t_s_6)
);
// @7:466
MUXCY_L un3_t_cry_6_cZ (
.DI(GND),
.CI(un3_t_cry_5),
.S(un3_t_axb_6),
.LO(un3_t_cry_6)
);
// @7:466
XORCY un3_t_s_5_cZ (
.LI(un3_t_axb_5),
.CI(un3_t_cry_4),
.O(un3_t_s_5)
);
// @7:466
MUXCY_L un3_t_cry_5_cZ (
.DI(GND),
.CI(un3_t_cry_4),
.S(un3_t_axb_5),
.LO(un3_t_cry_5)
);
// @7:466
XORCY un3_t_s_4_cZ (
.LI(un3_t_axb_4),
.CI(un3_t_cry_3),
.O(un3_t_s_4)
);
// @7:466
MUXCY_L un3_t_cry_4_cZ (
.DI(GND),
.CI(un3_t_cry_3),
.S(un3_t_axb_4),
.LO(un3_t_cry_4)
);
// @7:466
XORCY un3_t_s_3_cZ (
.LI(un3_t_axb_3),
.CI(un3_t_cry_2),
.O(un3_t_s_3)
);
// @7:466
MUXCY_L un3_t_cry_3_cZ (
.DI(GND),
.CI(un3_t_cry_2),
.S(un3_t_axb_3),
.LO(un3_t_cry_3)
);
// @7:466
XORCY un3_t_s_2_cZ (
.LI(un3_t_axb_2),
.CI(un3_t_cry_1),
.O(un3_t_s_2)
);
// @7:466
MUXCY_L un3_t_cry_2_cZ (
.DI(GND),
.CI(un3_t_cry_1),
.S(un3_t_axb_2),
.LO(un3_t_cry_2)
);
// @7:466
XORCY un3_t_s_1_cZ (
.LI(un3_t_axb_1),
.CI(un3_t_cry_0),
.O(un3_t_s_1)
);
// @7:466
MUXCY_L un3_t_cry_1_cZ (
.DI(GND),
.CI(un3_t_cry_0),
.S(un3_t_axb_1),
.LO(un3_t_cry_1)
);
// @7:466
MUXCY_L un3_t_cry_0_cZ (
.DI(GND),
.CI(un3_t_cry_0_cy),
.S(un3_t_axb_0),
.LO(un3_t_cry_0)
);
// @7:243
XORCY reg3_1_1_s_31 (
.LI(reg3_1_1_axb_31),
.CI(reg3_1_1_cry_30),
.O(reg3_1_1[31])
);
// @7:243
XORCY reg3_1_1_s_30 (
.LI(reg3_1_1_axb_30),
.CI(reg3_1_1_cry_29),
.O(reg3_1_1[30])
);
// @7:243
MUXCY_L reg3_1_1_cry_30_cZ (
.DI(GND),
.CI(reg3_1_1_cry_29),
.S(reg3_1_1_axb_30),
.LO(reg3_1_1_cry_30)
);
// @7:243
XORCY reg3_1_1_s_29 (
.LI(reg3_1_1_axb_29),
.CI(reg3_1_1_cry_28),
.O(reg3_1_1[29])
);
// @7:243
MUXCY_L reg3_1_1_cry_29_cZ (
.DI(GND),
.CI(reg3_1_1_cry_28),
.S(reg3_1_1_axb_29),
.LO(reg3_1_1_cry_29)
);
// @7:243
XORCY reg3_1_1_s_28 (
.LI(reg3_1_1_axb_28),
.CI(reg3_1_1_cry_27),
.O(reg3_1_1[28])
);
// @7:243
MUXCY_L reg3_1_1_cry_28_cZ (
.DI(GND),
.CI(reg3_1_1_cry_27),
.S(reg3_1_1_axb_28),
.LO(reg3_1_1_cry_28)
);
// @7:243
XORCY reg3_1_1_s_27 (
.LI(reg3_1_1_axb_27),
.CI(reg3_1_1_cry_26),
.O(reg3_1_1[27])
);
// @7:243
MUXCY_L reg3_1_1_cry_27_cZ (
.DI(GND),
.CI(reg3_1_1_cry_26),
.S(reg3_1_1_axb_27),
.LO(reg3_1_1_cry_27)
);
// @7:243
XORCY reg3_1_1_s_26 (
.LI(reg3_1_1_axb_26),
.CI(reg3_1_1_cry_25),
.O(reg3_1_1[26])
);
// @7:243
MUXCY_L reg3_1_1_cry_26_cZ (
.DI(GND),
.CI(reg3_1_1_cry_25),
.S(reg3_1_1_axb_26),
.LO(reg3_1_1_cry_26)
);
// @7:243
XORCY reg3_1_1_s_25 (
.LI(reg3_1_1_axb_25),
.CI(reg3_1_1_cry_24),
.O(reg3_1_1[25])
);
// @7:243
MUXCY_L reg3_1_1_cry_25_cZ (
.DI(GND),
.CI(reg3_1_1_cry_24),
.S(reg3_1_1_axb_25),
.LO(reg3_1_1_cry_25)
);
// @7:243
XORCY reg3_1_1_s_24 (
.LI(reg3_1_1_axb_24),
.CI(reg3_1_1_cry_23),
.O(reg3_1_1[24])
);
// @7:243
MUXCY_L reg3_1_1_cry_24_cZ (
.DI(GND),
.CI(reg3_1_1_cry_23),
.S(reg3_1_1_axb_24),
.LO(reg3_1_1_cry_24)
);
// @7:243
XORCY reg3_1_1_s_23 (
.LI(reg3_1_1_axb_23),
.CI(reg3_1_1_cry_22),
.O(reg3_1_1[23])
);
// @7:243
MUXCY_L reg3_1_1_cry_23_cZ (
.DI(GND),
.CI(reg3_1_1_cry_22),
.S(reg3_1_1_axb_23),
.LO(reg3_1_1_cry_23)
);
// @7:243
XORCY reg3_1_1_s_22 (
.LI(reg3_1_1_axb_22),
.CI(reg3_1_1_cry_21),
.O(reg3_1_1[22])
);
// @7:243
MUXCY_L reg3_1_1_cry_22_cZ (
.DI(GND),
.CI(reg3_1_1_cry_21),
.S(reg3_1_1_axb_22),
.LO(reg3_1_1_cry_22)
);
// @7:243
XORCY reg3_1_1_s_21 (
.LI(reg3_1_1_axb_21),
.CI(reg3_1_1_cry_20),
.O(reg3_1_1[21])
);
// @7:243
MUXCY_L reg3_1_1_cry_21_cZ (
.DI(GND),
.CI(reg3_1_1_cry_20),
.S(reg3_1_1_axb_21),
.LO(reg3_1_1_cry_21)
);
// @7:243
XORCY reg3_1_1_s_20 (
.LI(reg3_1_1_axb_20),
.CI(reg3_1_1_cry_19),
.O(reg3_1_1[20])
);
// @7:243
MUXCY_L reg3_1_1_cry_20_cZ (
.DI(GND),
.CI(reg3_1_1_cry_19),
.S(reg3_1_1_axb_20),
.LO(reg3_1_1_cry_20)
);
// @7:243
XORCY reg3_1_1_s_19 (
.LI(reg3_1_1_axb_19),
.CI(reg3_1_1_cry_18),
.O(reg3_1_1[19])
);
// @7:243
MUXCY_L reg3_1_1_cry_19_cZ (
.DI(GND),
.CI(reg3_1_1_cry_18),
.S(reg3_1_1_axb_19),
.LO(reg3_1_1_cry_19)
);
// @7:243
XORCY reg3_1_1_s_18 (
.LI(reg3_1_1_axb_18),
.CI(reg3_1_1_cry_17),
.O(reg3_1_1[18])
);
// @7:243
MUXCY_L reg3_1_1_cry_18_cZ (
.DI(GND),
.CI(reg3_1_1_cry_17),
.S(reg3_1_1_axb_18),
.LO(reg3_1_1_cry_18)
);
// @7:243
XORCY reg3_1_1_s_17 (
.LI(reg3_1_1_axb_17),
.CI(reg3_1_1_cry_16),
.O(reg3_1_1[17])
);
// @7:243
MUXCY_L reg3_1_1_cry_17_cZ (
.DI(GND),
.CI(reg3_1_1_cry_16),
.S(reg3_1_1_axb_17),
.LO(reg3_1_1_cry_17)
);
// @7:243
XORCY reg3_1_1_s_16 (
.LI(reg3_1_1_axb_16),
.CI(reg3_1_1_cry_15),
.O(reg3_1_1[16])
);
// @7:243
MUXCY_L reg3_1_1_cry_16_cZ (
.DI(GND),
.CI(reg3_1_1_cry_15),
.S(reg3_1_1_axb_16),
.LO(reg3_1_1_cry_16)
);
// @7:243
XORCY reg3_1_1_s_15 (
.LI(reg3_1_1_axb_15),
.CI(reg3_1_1_cry_14),
.O(reg3_1_1[15])
);
// @7:243
MUXCY_L reg3_1_1_cry_15_cZ (
.DI(GND),
.CI(reg3_1_1_cry_14),
.S(reg3_1_1_axb_15),
.LO(reg3_1_1_cry_15)
);
// @7:243
XORCY reg3_1_1_s_14 (
.LI(reg3_1_1_axb_14),
.CI(reg3_1_1_cry_13),
.O(reg3_1_1[14])
);
// @7:243
MUXCY_L reg3_1_1_cry_14_cZ (
.DI(GND),
.CI(reg3_1_1_cry_13),
.S(reg3_1_1_axb_14),
.LO(reg3_1_1_cry_14)
);
// @7:243
XORCY reg3_1_1_s_13 (
.LI(reg3_1_1_axb_13),
.CI(reg3_1_1_cry_12),
.O(reg3_1_1[13])
);
// @7:243
MUXCY_L reg3_1_1_cry_13_cZ (
.DI(GND),
.CI(reg3_1_1_cry_12),
.S(reg3_1_1_axb_13),
.LO(reg3_1_1_cry_13)
);
// @7:243
XORCY reg3_1_1_s_12 (
.LI(reg3_1_1_axb_12),
.CI(reg3_1_1_cry_11),
.O(reg3_1_1[12])
);
// @7:243
MUXCY_L reg3_1_1_cry_12_cZ (
.DI(GND),
.CI(reg3_1_1_cry_11),
.S(reg3_1_1_axb_12),
.LO(reg3_1_1_cry_12)
);
// @7:243
XORCY reg3_1_1_s_11 (
.LI(reg3_1_1_axb_11),
.CI(reg3_1_1_cry_10),
.O(reg3_1_1[11])
);
// @7:243
MUXCY_L reg3_1_1_cry_11_cZ (
.DI(GND),
.CI(reg3_1_1_cry_10),
.S(reg3_1_1_axb_11),
.LO(reg3_1_1_cry_11)
);
// @7:243
XORCY reg3_1_1_s_10 (
.LI(reg3_1_1_axb_10),
.CI(reg3_1_1_cry_9),
.O(reg3_1_1[10])
);
// @7:243
MUXCY_L reg3_1_1_cry_10_cZ (
.DI(GND),
.CI(reg3_1_1_cry_9),
.S(reg3_1_1_axb_10),
.LO(reg3_1_1_cry_10)
);
// @7:243
XORCY reg3_1_1_s_9 (
.LI(reg3_1_1_axb_9),
.CI(reg3_1_1_cry_8),
.O(reg3_1_1[9])
);
// @7:243
MUXCY_L reg3_1_1_cry_9_cZ (
.DI(GND),
.CI(reg3_1_1_cry_8),
.S(reg3_1_1_axb_9),
.LO(reg3_1_1_cry_9)
);
// @7:243
XORCY reg3_1_1_s_8 (
.LI(reg3_1_1_axb_8),
.CI(reg3_1_1_cry_7),
.O(reg3_1_1[8])
);
// @7:243
MUXCY_L reg3_1_1_cry_8_cZ (
.DI(GND),
.CI(reg3_1_1_cry_7),
.S(reg3_1_1_axb_8),
.LO(reg3_1_1_cry_8)
);
// @7:243
XORCY reg3_1_1_s_7 (
.LI(reg3_1_1_axb_7),
.CI(reg3_1_1_cry_6),
.O(reg3_1_1[7])
);
// @7:243
MUXCY_L reg3_1_1_cry_7_cZ (
.DI(GND),
.CI(reg3_1_1_cry_6),
.S(reg3_1_1_axb_7),
.LO(reg3_1_1_cry_7)
);
// @7:243
XORCY reg3_1_1_s_6 (
.LI(reg3_1_1_axb_6),
.CI(reg3_1_1_cry_5),
.O(reg3_1_1[6])
);
// @7:243
MUXCY_L reg3_1_1_cry_6_cZ (
.DI(GND),
.CI(reg3_1_1_cry_5),
.S(reg3_1_1_axb_6),
.LO(reg3_1_1_cry_6)
);
// @7:243
XORCY reg3_1_1_s_5 (
.LI(reg3_1_1_axb_5),
.CI(reg3_1_1_cry_4),
.O(reg3_1_1[5])
);
// @7:243
MUXCY_L reg3_1_1_cry_5_cZ (
.DI(GND),
.CI(reg3_1_1_cry_4),
.S(reg3_1_1_axb_5),
.LO(reg3_1_1_cry_5)
);
// @7:243
XORCY reg3_1_1_s_4 (
.LI(reg3_1_1_axb_4),
.CI(reg3_1_1_cry_3),
.O(reg3_1_1[4])
);
// @7:243
MUXCY_L reg3_1_1_cry_4_cZ (
.DI(GND),
.CI(reg3_1_1_cry_3),
.S(reg3_1_1_axb_4),
.LO(reg3_1_1_cry_4)
);
// @7:243
XORCY reg3_1_1_s_3 (
.LI(reg3_1_1_axb_3),
.CI(reg3_1_1_cry_2),
.O(reg3_1_1[3])
);
// @7:243
MUXCY_L reg3_1_1_cry_3_cZ (
.DI(GND),
.CI(reg3_1_1_cry_2),
.S(reg3_1_1_axb_3),
.LO(reg3_1_1_cry_3)
);
// @7:243
XORCY reg3_1_1_s_2 (
.LI(reg3_1_1_axb_2),
.CI(reg3_1_1_cry_1),
.O(reg3_1_1[2])
);
// @7:243
MUXCY_L reg3_1_1_cry_2_cZ (
.DI(GND),
.CI(reg3_1_1_cry_1),
.S(reg3_1_1_axb_2),
.LO(reg3_1_1_cry_2)
);
// @7:243
XORCY reg3_1_1_s_1 (
.LI(reg3_1_1_axb_1),
.CI(reg3_1_1_cry_0),
.O(reg3_1_1[1])
);
// @7:243
MUXCY_L reg3_1_1_cry_1_cZ (
.DI(GND),
.CI(reg3_1_1_cry_0),
.S(reg3_1_1_axb_1),
.LO(reg3_1_1_cry_1)
);
// @7:243
MUXCY_L reg3_1_1_cry_0_cZ (
.DI(GND),
.CI(VCC),
.S(reg3_1_1_axb_0),
.LO(reg3_1_1_cry_0)
);
// @7:83
XORCY inf_abs0_2_s_30 (
.LI(inf_abs0_2_axb_30),
.CI(inf_abs0_2_cry_29),
.O(inf_abs0_2[30])
);
// @7:83
MUXCY inf_abs0_2_cry_30 (
.DI(GND),
.CI(inf_abs0_2_cry_29),
.S(inf_abs0_2_axb_30),
.O(inf_abs0_2_0[31])
);
// @7:83
XORCY inf_abs0_2_s_29 (
.LI(inf_abs0_2_axb_29),
.CI(inf_abs0_2_cry_28),
.O(inf_abs0_2[29])
);
// @7:83
XORCY inf_abs0_2_s_28 (
.LI(inf_abs0_2_axb_28),
.CI(inf_abs0_2_cry_27),
.O(inf_abs0_2[28])
);
// @7:83
MUXCY_L inf_abs0_2_cry_28_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_27),
.S(inf_abs0_2_axb_28),
.LO(inf_abs0_2_cry_28)
);
// @7:83
XORCY inf_abs0_2_s_27 (
.LI(inf_abs0_2_axb_27),
.CI(inf_abs0_2_cry_26),
.O(inf_abs0_2[27])
);
// @7:83
MUXCY_L inf_abs0_2_cry_27_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_26),
.S(inf_abs0_2_axb_27),
.LO(inf_abs0_2_cry_27)
);
// @7:83
XORCY inf_abs0_2_s_26 (
.LI(inf_abs0_2_axb_26),
.CI(inf_abs0_2_cry_25),
.O(inf_abs0_2[26])
);
// @7:83
MUXCY_L inf_abs0_2_cry_26_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_25),
.S(inf_abs0_2_axb_26),
.LO(inf_abs0_2_cry_26)
);
// @7:83
XORCY inf_abs0_2_s_25 (
.LI(inf_abs0_2_axb_25),
.CI(inf_abs0_2_cry_24),
.O(inf_abs0_2[25])
);
// @7:83
MUXCY_L inf_abs0_2_cry_25_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_24),
.S(inf_abs0_2_axb_25),
.LO(inf_abs0_2_cry_25)
);
// @7:83
XORCY inf_abs0_2_s_24 (
.LI(inf_abs0_2_axb_24),
.CI(inf_abs0_2_cry_23),
.O(inf_abs0_2[24])
);
// @7:83
MUXCY_L inf_abs0_2_cry_24_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_23),
.S(inf_abs0_2_axb_24),
.LO(inf_abs0_2_cry_24)
);
// @7:83
XORCY inf_abs0_2_s_23 (
.LI(inf_abs0_2_axb_23),
.CI(inf_abs0_2_cry_22),
.O(inf_abs0_2[23])
);
// @7:83
MUXCY_L inf_abs0_2_cry_23_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_22),
.S(inf_abs0_2_axb_23),
.LO(inf_abs0_2_cry_23)
);
// @7:83
XORCY inf_abs0_2_s_22 (
.LI(inf_abs0_2_axb_22),
.CI(inf_abs0_2_cry_21),
.O(inf_abs0_2[22])
);
// @7:83
MUXCY_L inf_abs0_2_cry_22_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_21),
.S(inf_abs0_2_axb_22),
.LO(inf_abs0_2_cry_22)
);
// @7:83
XORCY inf_abs0_2_s_21 (
.LI(inf_abs0_2_axb_21),
.CI(inf_abs0_2_cry_20),
.O(inf_abs0_2[21])
);
// @7:83
MUXCY_L inf_abs0_2_cry_21_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_20),
.S(inf_abs0_2_axb_21),
.LO(inf_abs0_2_cry_21)
);
// @7:83
XORCY inf_abs0_2_s_20 (
.LI(inf_abs0_2_axb_20),
.CI(inf_abs0_2_cry_19),
.O(inf_abs0_2[20])
);
// @7:83
MUXCY_L inf_abs0_2_cry_20_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_19),
.S(inf_abs0_2_axb_20),
.LO(inf_abs0_2_cry_20)
);
// @7:83
XORCY inf_abs0_2_s_19 (
.LI(inf_abs0_2_axb_19),
.CI(inf_abs0_2_cry_18),
.O(inf_abs0_2[19])
);
// @7:83
MUXCY_L inf_abs0_2_cry_19_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_18),
.S(inf_abs0_2_axb_19),
.LO(inf_abs0_2_cry_19)
);
// @7:83
XORCY inf_abs0_2_s_18 (
.LI(inf_abs0_2_axb_18),
.CI(inf_abs0_2_cry_17),
.O(inf_abs0_2[18])
);
// @7:83
MUXCY_L inf_abs0_2_cry_18_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_17),
.S(inf_abs0_2_axb_18),
.LO(inf_abs0_2_cry_18)
);
// @7:83
XORCY inf_abs0_2_s_17 (
.LI(inf_abs0_2_axb_17),
.CI(inf_abs0_2_cry_16),
.O(inf_abs0_2[17])
);
// @7:83
MUXCY_L inf_abs0_2_cry_17_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_16),
.S(inf_abs0_2_axb_17),
.LO(inf_abs0_2_cry_17)
);
// @7:83
XORCY inf_abs0_2_s_16 (
.LI(inf_abs0_2_axb_16),
.CI(inf_abs0_2_cry_15),
.O(inf_abs0_2[16])
);
// @7:83
MUXCY_L inf_abs0_2_cry_16_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_15),
.S(inf_abs0_2_axb_16),
.LO(inf_abs0_2_cry_16)
);
// @7:83
XORCY inf_abs0_2_s_15 (
.LI(inf_abs0_2_axb_15),
.CI(inf_abs0_2_cry_14),
.O(inf_abs0_2[15])
);
// @7:83
MUXCY_L inf_abs0_2_cry_15_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_14),
.S(inf_abs0_2_axb_15),
.LO(inf_abs0_2_cry_15)
);
// @7:83
XORCY inf_abs0_2_s_14 (
.LI(inf_abs0_2_axb_14),
.CI(inf_abs0_2_cry_13),
.O(inf_abs0_2[14])
);
// @7:83
MUXCY_L inf_abs0_2_cry_14_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_13),
.S(inf_abs0_2_axb_14),
.LO(inf_abs0_2_cry_14)
);
// @7:83
XORCY inf_abs0_2_s_13 (
.LI(inf_abs0_2_axb_13),
.CI(inf_abs0_2_cry_12),
.O(inf_abs0_2[13])
);
// @7:83
MUXCY_L inf_abs0_2_cry_13_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_12),
.S(inf_abs0_2_axb_13),
.LO(inf_abs0_2_cry_13)
);
// @7:83
XORCY inf_abs0_2_s_12 (
.LI(inf_abs0_2_axb_12),
.CI(inf_abs0_2_cry_11),
.O(inf_abs0_2[12])
);
// @7:83
MUXCY_L inf_abs0_2_cry_12_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_11),
.S(inf_abs0_2_axb_12),
.LO(inf_abs0_2_cry_12)
);
// @7:83
XORCY inf_abs0_2_s_11 (
.LI(inf_abs0_2_axb_11),
.CI(inf_abs0_2_cry_10),
.O(inf_abs0_2[11])
);
// @7:83
MUXCY_L inf_abs0_2_cry_11_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_10),
.S(inf_abs0_2_axb_11),
.LO(inf_abs0_2_cry_11)
);
// @7:83
XORCY inf_abs0_2_s_10 (
.LI(inf_abs0_2_axb_10),
.CI(inf_abs0_2_cry_9),
.O(inf_abs0_2[10])
);
// @7:83
MUXCY_L inf_abs0_2_cry_10_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_9),
.S(inf_abs0_2_axb_10),
.LO(inf_abs0_2_cry_10)
);
// @7:83
XORCY inf_abs0_2_s_9 (
.LI(inf_abs0_2_axb_9),
.CI(inf_abs0_2_cry_8),
.O(inf_abs0_2[9])
);
// @7:83
MUXCY_L inf_abs0_2_cry_9_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_8),
.S(inf_abs0_2_axb_9),
.LO(inf_abs0_2_cry_9)
);
// @7:83
XORCY inf_abs0_2_s_8 (
.LI(inf_abs0_2_axb_8),
.CI(inf_abs0_2_cry_7),
.O(inf_abs0_2[8])
);
// @7:83
MUXCY_L inf_abs0_2_cry_8_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_7),
.S(inf_abs0_2_axb_8),
.LO(inf_abs0_2_cry_8)
);
// @7:83
XORCY inf_abs0_2_s_7 (
.LI(inf_abs0_2_axb_7),
.CI(inf_abs0_2_cry_6),
.O(inf_abs0_2[7])
);
// @7:83
MUXCY_L inf_abs0_2_cry_7_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_6),
.S(inf_abs0_2_axb_7),
.LO(inf_abs0_2_cry_7)
);
// @7:83
XORCY inf_abs0_2_s_6 (
.LI(inf_abs0_2_axb_6),
.CI(inf_abs0_2_cry_5),
.O(inf_abs0_2[6])
);
// @7:83
MUXCY_L inf_abs0_2_cry_6_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_5),
.S(inf_abs0_2_axb_6),
.LO(inf_abs0_2_cry_6)
);
// @7:83
XORCY inf_abs0_2_s_5 (
.LI(inf_abs0_2_axb_5),
.CI(inf_abs0_2_cry_4),
.O(inf_abs0_2[5])
);
// @7:83
MUXCY_L inf_abs0_2_cry_5_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_4),
.S(inf_abs0_2_axb_5),
.LO(inf_abs0_2_cry_5)
);
// @7:83
XORCY inf_abs0_2_s_4 (
.LI(inf_abs0_2_axb_4),
.CI(inf_abs0_2_cry_3),
.O(inf_abs0_2[4])
);
// @7:83
MUXCY_L inf_abs0_2_cry_4_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_3),
.S(inf_abs0_2_axb_4),
.LO(inf_abs0_2_cry_4)
);
// @7:83
XORCY inf_abs0_2_s_3 (
.LI(inf_abs0_2_axb_3),
.CI(inf_abs0_2_cry_2),
.O(inf_abs0_2[3])
);
// @7:83
MUXCY_L inf_abs0_2_cry_3_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_2),
.S(inf_abs0_2_axb_3),
.LO(inf_abs0_2_cry_3)
);
// @7:83
XORCY inf_abs0_2_s_2 (
.LI(inf_abs0_2_axb_2),
.CI(inf_abs0_2_cry_1),
.O(inf_abs0_2[2])
);
// @7:83
MUXCY_L inf_abs0_2_cry_2_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_1),
.S(inf_abs0_2_axb_2),
.LO(inf_abs0_2_cry_2)
);
// @7:83
XORCY inf_abs0_2_s_1 (
.LI(inf_abs0_2_axb_1),
.CI(inf_abs0_2_cry_0),
.O(inf_abs0_2[1])
);
// @7:83
MUXCY_L inf_abs0_2_cry_1_cZ (
.DI(GND),
.CI(inf_abs0_2_cry_0),
.S(inf_abs0_2_axb_1),
.LO(inf_abs0_2_cry_1)
);
// @7:83
XORCY inf_abs0_2_s_0 (
.LI(inf_abs0_2_axb_0),
.CI(ir_fast[31]),
.O(inf_abs0_2[0])
);
// @7:83
MUXCY_L inf_abs0_2_cry_0_cZ (
.DI(GND),
.CI(ir_fast[31]),
.S(inf_abs0_2_axb_0),
.LO(inf_abs0_2_cry_0)
);
// @7:151
LUT4 un26_r_lt30_cZ (
.I0(m_2_i[31]),
.I1(m_2[30]),
.I2(r_4_i[31]),
.I3(r_6[30]),
.O(un26_r_lt30)
);
defparam un26_r_lt30_cZ.INIT=16'h0A8E;
// @7:151
MUXCY_L \un26_r_cry_cZ[28] (
.DI(un26_r_lt28),
.CI(un26_r_cry[26]),
.S(un26_r_df28),
.LO(un26_r_cry[28])
);
// @7:151
MUXCY_L \un26_r_cry_cZ[26] (
.DI(un26_r_lt26),
.CI(un26_r_cry[24]),
.S(un26_r_df26),
.LO(un26_r_cry[26])
);
// @7:151
MUXCY_L \un26_r_cry_cZ[24] (
.DI(un26_r_lt24),
.CI(un26_r_cry[22]),
.S(un26_r_df24),
.LO(un26_r_cry[24])
);
// @7:151
MUXCY_L \un26_r_cry_cZ[22] (
.DI(un26_r_lt22),
.CI(un26_r_cry[20]),
.S(un26_r_df22),
.LO(un26_r_cry[22])
);
// @7:151
MUXCY_L \un26_r_cry_cZ[20] (
.DI(un26_r_lt20),
.CI(un26_r_cry[18]),
.S(un26_r_df20),
.LO(un26_r_cry[20])
);
// @7:151
MUXCY_L \un26_r_cry_cZ[18] (
.DI(un26_r_lt18),
.CI(un26_r_cry[16]),
.S(un26_r_df18),
.LO(un26_r_cry[18])
);
// @7:151
LUT4 un26_r_lt18_cZ (
.I0(m_2[19]),
.I1(m_2[18]),
.I2(r_4[19]),
.I3(r_4[18]),
.O(un26_r_lt18)
);
defparam un26_r_lt18_cZ.INIT=16'h0A8E;
// @7:151
MUXCY_L \un26_r_cry_cZ[16] (
.DI(un26_r_lt16),
.CI(un26_r_cry[14]),
.S(un26_r_df16),
.LO(un26_r_cry[16])
);
// @7:151
LUT4 un26_r_lt16_cZ (
.I0(m_2[16]),
.I1(m_2[17]),
.I2(r_4[16]),
.I3(r_4[17]),
.O(un26_r_lt16)
);
defparam un26_r_lt16_cZ.INIT=16'h08CE;
// @7:151
MUXCY_L \un26_r_cry_cZ[14] (
.DI(un26_r_lt14),
.CI(un26_r_cry[12]),
.S(un26_r_df14),
.LO(un26_r_cry[14])
);
// @7:151
LUT4 un26_r_lt14_cZ (
.I0(m_2[14]),
.I1(m_2[15]),
.I2(r_4[14]),
.I3(r_4[15]),
.O(un26_r_lt14)
);
defparam un26_r_lt14_cZ.INIT=16'h08CE;
// @7:151
MUXCY_L \un26_r_cry_cZ[12] (
.DI(un26_r_lt12),
.CI(un26_r_cry[10]),
.S(un26_r_df12),
.LO(un26_r_cry[12])
);
// @7:151
LUT4 un26_r_lt12_cZ (
.I0(m_2[12]),
.I1(m_2[13]),
.I2(r_4[12]),
.I3(r_4[13]),
.O(un26_r_lt12)
);
defparam un26_r_lt12_cZ.INIT=16'h08CE;
// @7:151
MUXCY_L \un26_r_cry_cZ[10] (
.DI(un26_r_lt10),
.CI(un26_r_cry[8]),
.S(un26_r_df10),
.LO(un26_r_cry[10])
);
// @7:151
LUT4 un26_r_lt10_cZ (
.I0(m_2[10]),
.I1(m_2[11]),
.I2(r_4[11]),
.I3(r_4[10]),
.O(un26_r_lt10)
);
defparam un26_r_lt10_cZ.INIT=16'h0C8E;
// @7:151
MUXCY_L \un26_r_cry_cZ[8] (
.DI(un26_r_lt8),
.CI(un26_r_cry[6]),
.S(un26_r_df8),
.LO(un26_r_cry[8])
);
// @7:151
LUT4 un26_r_lt8_cZ (
.I0(m_2[8]),
.I1(m_2[9]),
.I2(r_4[8]),
.I3(r_4[9]),
.O(un26_r_lt8)
);
defparam un26_r_lt8_cZ.INIT=16'h08CE;
// @7:151
MUXCY_L \un26_r_cry_cZ[6] (
.DI(un26_r_lt6),
.CI(un26_r_cry[4]),
.S(un26_r_df6),
.LO(un26_r_cry[6])
);
// @7:151
LUT4 un26_r_lt6_cZ (
.I0(m_2[7]),
.I1(m_2[6]),
.I2(r_4[6]),
.I3(r_4[7]),
.O(un26_r_lt6)
);
defparam un26_r_lt6_cZ.INIT=16'h08AE;
// @7:151
MUXCY_L \un26_r_cry_cZ[4] (
.DI(un26_r_lt4),
.CI(un26_r_cry[2]),
.S(un26_r_df4),
.LO(un26_r_cry[4])
);
// @7:151
LUT4 un26_r_lt4_cZ (
.I0(m_2[4]),
.I1(m_2[5]),
.I2(r_4[4]),
.I3(r_4[5]),
.O(un26_r_lt4)
);
defparam un26_r_lt4_cZ.INIT=16'h08CE;
// @7:151
MUXCY_L \un26_r_cry_cZ[2] (
.DI(un26_r_lt2),
.CI(un26_r_cry[0]),
.S(un26_r_df2),
.LO(un26_r_cry[2])
);
// @7:151
LUT4 un26_r_lt2_cZ (
.I0(m_2[2]),
.I1(m_2[3]),
.I2(r_4[3]),
.I3(N_28),
.O(un26_r_lt2)
);
defparam un26_r_lt2_cZ.INIT=16'h0C8E;
// @7:151
MUXCY_L \un26_r_cry_cZ[0] (
.DI(un26_r_lt0),
.CI(GND),
.S(un26_r_df0),
.LO(un26_r_cry[0])
);
// @7:151
LUT4 un26_r_lt0_cZ (
.I0(m_2[1]),
.I1(m_2[0]),
.I2(r_4[0]),
.I3(r_4[1]),
.O(un26_r_lt0)
);
defparam un26_r_lt0_cZ.INIT=16'h08AE;
// @7:143
MUXCY_L \b18_cry_cZ[28] (
.DI(b18_lt28),
.CI(b18_cry[26]),
.S(b18_df28),
.LO(b18_cry[28])
);
// @7:143
MUXCY_L \b18_cry_cZ[26] (
.DI(b18_lt26),
.CI(b18_cry[24]),
.S(b18_df26),
.LO(b18_cry[26])
);
// @7:143
MUXCY_L \b18_cry_cZ[24] (
.DI(b18_lt24),
.CI(b18_cry[22]),
.S(b18_df24),
.LO(b18_cry[24])
);
// @7:143
MUXCY_L \b18_cry_cZ[22] (
.DI(b18_lt22),
.CI(b18_cry[20]),
.S(b18_df22),
.LO(b18_cry[22])
);
// @7:143
MUXCY_L \b18_cry_cZ[20] (
.DI(b18_lt20),
.CI(b18_cry[18]),
.S(b18_df20),
.LO(b18_cry[20])
);
// @7:143
MUXCY_L \b18_cry_cZ[18] (
.DI(b18_lt18),
.CI(b18_cry[16]),
.S(b18_df18),
.LO(b18_cry[18])
);
// @7:143
LUT4 b18_lt18_cZ (
.I0(m_2[19]),
.I1(m_2[18]),
.I2(r_4[19]),
.I3(r_4[18]),
.O(b18_lt18)
);
defparam b18_lt18_cZ.INIT=16'h7150;
// @7:143
MUXCY_L \b18_cry_cZ[16] (
.DI(b18_lt16),
.CI(b18_cry[14]),
.S(b18_df16),
.LO(b18_cry[16])
);
// @7:143
LUT4 b18_lt16_cZ (
.I0(m_2[16]),
.I1(m_2[17]),
.I2(r_4[16]),
.I3(r_4[17]),
.O(b18_lt16)
);
defparam b18_lt16_cZ.INIT=16'h7310;
// @7:143
MUXCY_L \b18_cry_cZ[14] (
.DI(b18_lt14),
.CI(b18_cry[12]),
.S(b18_df14),
.LO(b18_cry[14])
);
// @7:143
LUT4 b18_lt14_cZ (
.I0(m_2[14]),
.I1(m_2[15]),
.I2(r_4[14]),
.I3(r_4[15]),
.O(b18_lt14)
);
defparam b18_lt14_cZ.INIT=16'h7310;
// @7:143
MUXCY_L \b18_cry_cZ[12] (
.DI(b18_lt12),
.CI(b18_cry[10]),
.S(b18_df12),
.LO(b18_cry[12])
);
// @7:143
LUT4 b18_lt12_cZ (
.I0(m_2[12]),
.I1(m_2[13]),
.I2(r_4[12]),
.I3(r_4[13]),
.O(b18_lt12)
);
defparam b18_lt12_cZ.INIT=16'h7310;
// @7:143
MUXCY_L \b18_cry_cZ[10] (
.DI(b18_lt10),
.CI(b18_cry[8]),
.S(b18_df10),
.LO(b18_cry[10])
);
// @7:143
LUT4 b18_lt10_cZ (
.I0(m_2[10]),
.I1(m_2[11]),
.I2(r_4[11]),
.I3(r_4[10]),
.O(b18_lt10)
);
defparam b18_lt10_cZ.INIT=16'h7130;
// @7:143
MUXCY_L \b18_cry_cZ[8] (
.DI(b18_lt8),
.CI(b18_cry[6]),
.S(b18_df8),
.LO(b18_cry[8])
);
// @7:143
LUT4 b18_lt8_cZ (
.I0(m_2[8]),
.I1(m_2[9]),
.I2(r_4[8]),
.I3(r_4[9]),
.O(b18_lt8)
);
defparam b18_lt8_cZ.INIT=16'h7310;
// @7:143
MUXCY_L \b18_cry_cZ[6] (
.DI(b18_lt6),
.CI(b18_cry[4]),
.S(b18_df6),
.LO(b18_cry[6])
);
// @7:143
LUT4 b18_lt6_cZ (
.I0(m_2[7]),
.I1(m_2[6]),
.I2(r_4[6]),
.I3(r_4[7]),
.O(b18_lt6)
);
defparam b18_lt6_cZ.INIT=16'h7510;
// @7:143
MUXCY_L \b18_cry_cZ[4] (
.DI(b18_lt4),
.CI(b18_cry[2]),
.S(b18_df4),
.LO(b18_cry[4])
);
// @7:143
LUT4 b18_lt4_cZ (
.I0(m_2[4]),
.I1(m_2[5]),
.I2(r_4[4]),
.I3(r_4[5]),
.O(b18_lt4)
);
defparam b18_lt4_cZ.INIT=16'h7310;
// @7:143
MUXCY_L \b18_cry_cZ[2] (
.DI(b18_lt2),
.CI(b18_cry[0]),
.S(b18_df2),
.LO(b18_cry[2])
);
// @7:143
LUT4 b18_lt2_cZ (
.I0(m_2[2]),
.I1(m_2[3]),
.I2(r_4[3]),
.I3(N_28),
.O(b18_lt2)
);
defparam b18_lt2_cZ.INIT=16'h7130;
// @7:143
MUXCY_L \b18_cry_cZ[0] (
.DI(b18_lt0),
.CI(GND),
.S(b18_df0),
.LO(b18_cry[0])
);
// @7:143
LUT4 b18_lt0_cZ (
.I0(m_2[1]),
.I1(m_2[0]),
.I2(r_4[0]),
.I3(r_4[1]),
.O(b18_lt0)
);
defparam b18_lt0_cZ.INIT=16'h7510;
// @7:118
MUXCY_L \un11_r_cry_cZ[28] (
.DI(un11_r_lt28),
.CI(un11_r_cry[26]),
.S(un11_r_df28),
.LO(un11_r_cry[28])
);
// @7:118
MUXCY_L \un11_r_cry_cZ[26] (
.DI(un11_r_lt26),
.CI(un11_r_cry[24]),
.S(un11_r_df26),
.LO(un11_r_cry[26])
);
// @7:118
MUXCY_L \un11_r_cry_cZ[24] (
.DI(un11_r_lt24),
.CI(un11_r_cry[22]),
.S(un11_r_df24),
.LO(un11_r_cry[24])
);
// @7:118
MUXCY_L \un11_r_cry_cZ[22] (
.DI(un11_r_lt22),
.CI(un11_r_cry[20]),
.S(un11_r_df22),
.LO(un11_r_cry[22])
);
// @7:118
MUXCY_L \un11_r_cry_cZ[20] (
.DI(un11_r_lt20),
.CI(un11_r_cry[18]),
.S(un11_r_df20),
.LO(un11_r_cry[20])
);
// @7:118
MUXCY_L \un11_r_cry_cZ[18] (
.DI(un11_r_lt18),
.CI(un11_r_cry[16]),
.S(un11_r_df18),
.LO(un11_r_cry[18])
);
// @7:118
LUT4 un11_r_lt18_cZ (
.I0(m_2[19]),
.I1(m_2[18]),
.I2(r_4[19]),
.I3(r_4[18]),
.O(un11_r_lt18)
);
defparam un11_r_lt18_cZ.INIT=16'h0A8E;
// @7:118
MUXCY_L \un11_r_cry_cZ[16] (
.DI(un11_r_lt16),
.CI(un11_r_cry[14]),
.S(un11_r_df16),
.LO(un11_r_cry[16])
);
// @7:118
LUT4 un11_r_lt16_cZ (
.I0(m_2[16]),
.I1(m_2[17]),
.I2(r_4[16]),
.I3(r_4[17]),
.O(un11_r_lt16)
);
defparam un11_r_lt16_cZ.INIT=16'h08CE;
// @7:118
MUXCY_L \un11_r_cry_cZ[14] (
.DI(un11_r_lt14),
.CI(un11_r_cry[12]),
.S(un11_r_df14),
.LO(un11_r_cry[14])
);
// @7:118
LUT4 un11_r_lt14_cZ (
.I0(m_2[14]),
.I1(m_2[15]),
.I2(r_4[14]),
.I3(r_4[15]),
.O(un11_r_lt14)
);
defparam un11_r_lt14_cZ.INIT=16'h08CE;
// @7:118
MUXCY_L \un11_r_cry_cZ[12] (
.DI(un11_r_lt12),
.CI(un11_r_cry[10]),
.S(un11_r_df12),
.LO(un11_r_cry[12])
);
// @7:118
LUT4 un11_r_lt12_cZ (
.I0(m_2[12]),
.I1(m_2[13]),
.I2(r_4[12]),
.I3(r_4[13]),
.O(un11_r_lt12)
);
defparam un11_r_lt12_cZ.INIT=16'h08CE;
// @7:118
MUXCY_L \un11_r_cry_cZ[10] (
.DI(un11_r_lt10),
.CI(un11_r_cry[8]),
.S(un11_r_df10),
.LO(un11_r_cry[10])
);
// @7:118
LUT4 un11_r_lt10_cZ (
.I0(m_2[10]),
.I1(m_2[11]),
.I2(r_4[11]),
.I3(r_4[10]),
.O(un11_r_lt10)
);
defparam un11_r_lt10_cZ.INIT=16'h0C8E;
// @7:118
MUXCY_L \un11_r_cry_cZ[8] (
.DI(un11_r_lt8),
.CI(un11_r_cry[6]),
.S(un11_r_df8),
.LO(un11_r_cry[8])
);
// @7:118
LUT4 un11_r_lt8_cZ (
.I0(m_2[8]),
.I1(m_2[9]),
.I2(r_4[8]),
.I3(r_4[9]),
.O(un11_r_lt8)
);
defparam un11_r_lt8_cZ.INIT=16'h08CE;
// @7:118
MUXCY_L \un11_r_cry_cZ[6] (
.DI(un11_r_lt6),
.CI(un11_r_cry[4]),
.S(un11_r_df6),
.LO(un11_r_cry[6])
);
// @7:118
LUT4 un11_r_lt6_cZ (
.I0(m_2[7]),
.I1(m_2[6]),
.I2(r_4[6]),
.I3(r_4[7]),
.O(un11_r_lt6)
);
defparam un11_r_lt6_cZ.INIT=16'h08AE;
// @7:118
MUXCY_L \un11_r_cry_cZ[4] (
.DI(un11_r_lt4),
.CI(un11_r_cry[2]),
.S(un11_r_df4),
.LO(un11_r_cry[4])
);
// @7:118
LUT4 un11_r_lt4_cZ (
.I0(m_2[4]),
.I1(m_2[5]),
.I2(r_4[4]),
.I3(r_4[5]),
.O(un11_r_lt4)
);
defparam un11_r_lt4_cZ.INIT=16'h08CE;
// @7:118
MUXCY_L \un11_r_cry_cZ[2] (
.DI(un11_r_lt2),
.CI(un11_r_cry[0]),
.S(un11_r_df2),
.LO(un11_r_cry[2])
);
// @7:118
LUT4 un11_r_lt2_cZ (
.I0(m_2[2]),
.I1(m_2[3]),
.I2(r_4[3]),
.I3(N_28),
.O(un11_r_lt2)
);
defparam un11_r_lt2_cZ.INIT=16'h0C8E;
// @7:118
MUXCY_L \un11_r_cry_cZ[0] (
.DI(un11_r_lt0),
.CI(GND),
.S(un11_r_df0),
.LO(un11_r_cry[0])
);
// @7:118
LUT4 un11_r_lt0_cZ (
.I0(m_2[1]),
.I1(m_2[0]),
.I2(r_4[0]),
.I3(r_4[1]),
.O(un11_r_lt0)
);
defparam un11_r_lt0_cZ.INIT=16'h08AE;
// @7:128
MUXCY_L un14_r_0_I_75 (
.DI(GND),
.CI(un14_r_0_data_tmp[3]),
.S(un14_r_0_N_7),
.LO(un14_r_0_data_tmp[4])
);
// @7:128
MUXCY_L un14_r_0_I_67 (
.DI(GND),
.CI(un14_r_0_data_tmp[0]),
.S(un14_r_0_N_14),
.LO(un14_r_0_data_tmp[1])
);
// @7:128
MUXCY_L un14_r_0_I_59 (
.DI(GND),
.CI(un14_r_0_data_tmp[1]),
.S(un14_r_0_N_21),
.LO(un14_r_0_data_tmp[2])
);
// @7:128
MUXCY_L un14_r_0_I_51 (
.DI(GND),
.CI(un14_r_0_data_tmp[2]),
.S(un14_r_0_N_28),
.LO(un14_r_0_data_tmp[3])
);
// @7:128
MUXCY_L un14_r_0_I_43 (
.DI(GND),
.CI(un14_r_0_data_tmp[7]),
.S(un14_r_0_N_35),
.LO(un14_r_0_data_tmp[8])
);
// @7:128
MUXCY_L un14_r_0_I_35 (
.DI(GND),
.CI(un14_r_0_data_tmp[4]),
.S(un14_r_0_N_42),
.LO(un14_r_0_data_tmp[5])
);
// @7:128
MUXCY_L un14_r_0_I_27 (
.DI(GND),
.CI(un14_r_0_data_tmp[5]),
.S(un14_r_0_N_49),
.LO(un14_r_0_data_tmp[6])
);
// @7:128
MUXCY_L un14_r_0_I_19 (
.DI(GND),
.CI(un14_r_0_data_tmp[6]),
.S(un14_r_0_N_56),
.LO(un14_r_0_data_tmp[7])
);
// @7:128
MUXCY_L un14_r_0_I_11 (
.DI(GND),
.CI(un14_r_0_data_tmp[8]),
.S(un14_r_0_N_63),
.LO(un14_r_0_data_tmp[9])
);
// @7:128
MUXCY_L un14_r_0_I_1 (
.DI(GND),
.CI(VCC),
.S(un14_r_0_N_70),
.LO(un14_r_0_data_tmp[0])
);
// @7:47
LUT4 \d_cnst_sn.reg0_28_5_2426_a6_1_1_lut6_2_o6 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(reg3_1_1[21]),
.O(\d_cnst_sn.reg0_28_5_2426_a6_1_1 )
);
defparam \d_cnst_sn.reg0_28_5_2426_a6_1_1_lut6_2_o6 .INIT=16'h0100;
// @7:47
LUT3 \d_cnst_sn.reg0_28_5_2426_a6_1_1_lut6_2_o5 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.O(\d_cnst_sn.reg0_28_12_2195_a6_1_2_0 )
);
defparam \d_cnst_sn.reg0_28_5_2426_a6_1_1_lut6_2_o5 .INIT=8'h01;
// @7:47
LUT4 \d_cnst_sn.reg0_28_9_2294_a6_1_1_lut6_2_o6 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(reg3_1_1[25]),
.O(\d_cnst_sn.reg0_28_9_2294_a6_1_1 )
);
defparam \d_cnst_sn.reg0_28_9_2294_a6_1_1_lut6_2_o6 .INIT=16'h0100;
// @7:47
LUT4 \d_cnst_sn.reg0_28_9_2294_a6_1_1_lut6_2_o5 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(reg3_1_1[26]),
.O(\d_cnst_sn.reg0_28_10_2261_a6_1_1 )
);
defparam \d_cnst_sn.reg0_28_9_2294_a6_1_1_lut6_2_o5 .INIT=16'h0100;
// @7:97
LUT2 \d_cnst_sn.r_4_2_a1_lut6_2_o6[3] (
.I0(reg1[3]),
.I1(inf_abs0_2[30]),
.O(r_4_2_a1_lut6_2_O6[3])
);
defparam \d_cnst_sn.r_4_2_a1_lut6_2_o6[3] .INIT=4'h1;
// @7:97
LUT2 \d_cnst_sn.r_4_2_a1_lut6_2_o5[3] (
.I0(reg1[4]),
.I1(inf_abs0_2[30]),
.O(r_4_2_a1_lut6_2_O5[3])
);
defparam \d_cnst_sn.r_4_2_a1_lut6_2_o5[3] .INIT=4'h1;
// @7:47
LUT4 \d_cnst_sn.reg0_28_7_2360_a6_1_1_lut6_2_o6 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(reg3_1_1[23]),
.O(\d_cnst_sn.reg0_28_7_2360_a6_1_1 )
);
defparam \d_cnst_sn.reg0_28_7_2360_a6_1_1_lut6_2_o6 .INIT=16'h0100;
// @7:47
LUT2 \d_cnst_sn.reg0_28_7_2360_a6_1_1_lut6_2_o5 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.O(N_3873_2)
);
defparam \d_cnst_sn.reg0_28_7_2360_a6_1_1_lut6_2_o5 .INIT=4'h1;
LUT2 \d_cnst_sn.g0_0_0_a5_0_0_lut6_2_o6 (
.I0(datai[31]),
.I1(inf_abs0_2[20]),
.O(\d_cnst_sn.g0_0_0_a5_0_0 )
);
defparam \d_cnst_sn.g0_0_0_a5_0_0_lut6_2_o6 .INIT=4'h8;
LUT3 \d_cnst_sn.g0_0_0_a5_0_0_lut6_2_o5 (
.I0(datai[20]),
.I1(state[0]),
.I2(inf_abs0_2[20]),
.O(ir_3[20])
);
defparam \d_cnst_sn.g0_0_0_a5_0_0_lut6_2_o5 .INIT=8'hE2;
// @7:47
LUT3 \d_cnst_sn.addr_20_iv_1052_i_a6_2_0_lut6_2_o6 (
.I0(state[0]),
.I1(inf_abs0_2[27]),
.I2(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_1052_i_a6_2_0 )
);
defparam \d_cnst_sn.addr_20_iv_1052_i_a6_2_0_lut6_2_o6 .INIT=8'h80;
// @7:47
LUT3 \d_cnst_sn.addr_20_iv_1052_i_a6_2_0_lut6_2_o5 (
.I0(datai[30]),
.I1(state[0]),
.I2(inf_abs0_2[30]),
.O(ir_3[30])
);
defparam \d_cnst_sn.addr_20_iv_1052_i_a6_2_0_lut6_2_o5 .INIT=8'hE2;
// @7:47
LUT2 \d_cnst_sn.addr_20_iv_1052_i_a6_1_0_lut6_2_o6 (
.I0(state[0]),
.I1(inf_abs0_2[27]),
.O(\d_cnst_sn.addr_20_iv_1052_i_a6_1_0 )
);
defparam \d_cnst_sn.addr_20_iv_1052_i_a6_1_0_lut6_2_o6 .INIT=4'h2;
// @7:47
LUT3 \d_cnst_sn.addr_20_iv_1052_i_a6_1_0_lut6_2_o5 (
.I0(datai[31]),
.I1(state[0]),
.I2(inf_abs0_2[31]),
.O(ir_3[31])
);
defparam \d_cnst_sn.addr_20_iv_1052_i_a6_1_0_lut6_2_o5 .INIT=8'hE2;
// @7:47
LUT3 \d_cnst_sn.reg0_28_10_2261_a6_1_0_lut6_2_o6 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.O(\d_cnst_sn.reg0_28_2526_a5_1_0 )
);
defparam \d_cnst_sn.reg0_28_10_2261_a6_1_0_lut6_2_o6 .INIT=8'h01;
// @7:47
LUT4 \d_cnst_sn.reg0_28_10_2261_a6_1_0_lut6_2_o5 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.g0_0_0_a5_2 )
);
defparam \d_cnst_sn.reg0_28_10_2261_a6_1_0_lut6_2_o5 .INIT=16'h0008;
// @7:47
LUT4 \d_cnst_sn.g0_2_lut6_2_o6 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.O(\d_cnst_sn.reg0_N_13_0 )
);
defparam \d_cnst_sn.g0_2_lut6_2_o6 .INIT=16'h003E;
// @7:47
LUT3 \d_cnst_sn.g0_2_lut6_2_o5 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.O(\d_cnst_sn.reg0_m8_e_0 )
);
defparam \d_cnst_sn.g0_2_lut6_2_o5 .INIT=8'h07;
// @7:47
LUT4 \d_cnst_sn.reg0_28_8_2327_a6_1_1_lut6_2_o6 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(reg3_1_1[24]),
.O(\d_cnst_sn.reg0_28_8_2327_a6_1_1 )
);
defparam \d_cnst_sn.reg0_28_8_2327_a6_1_1_lut6_2_o6 .INIT=16'h0100;
// @7:47
LUT3 \d_cnst_sn.reg0_28_8_2327_a6_1_1_lut6_2_o5 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.O(\d_cnst_sn.reg1_16_8_1837_2_tz )
);
defparam \d_cnst_sn.reg0_28_8_2327_a6_1_1_lut6_2_o5 .INIT=8'hF8;
// @7:86
LUT2 \d_cnst_sn.r_4_2_RNIBJSG2_o6[18] (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[28]),
.O(N_527_i)
);
defparam \d_cnst_sn.r_4_2_RNIBJSG2_o6[18] .INIT=4'h4;
// @7:86
LUT5 \d_cnst_sn.r_4_2_RNIBJSG2_o5[18] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[18]),
.I4(reg3_1_1[19]),
.O(\d_cnst_sn.reg0_28_0 [19])
);
defparam \d_cnst_sn.r_4_2_RNIBJSG2_o5[18] .INIT=32'hFFDF2202;
// @7:47
LUT4 \d_cnst_sn.addr_20_iv_6_863_i_0_lut6_2_o6 (
.I0(reg3[19]),
.I1(state[0]),
.I2(inf_abs0_2[19]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_6_863_i_0 )
);
defparam \d_cnst_sn.addr_20_iv_6_863_i_0_lut6_2_o6 .INIT=16'h111D;
// @7:47
LUT3 \d_cnst_sn.addr_20_iv_6_863_i_0_lut6_2_o5 (
.I0(datai[28]),
.I1(state[0]),
.I2(inf_abs0_2[28]),
.O(ir_3[28])
);
defparam \d_cnst_sn.addr_20_iv_6_863_i_0_lut6_2_o5 .INIT=8'hE2;
// @7:106
LUT2 \d_cnst_sn.g0_2_0_i2_lut6_2_o6 (
.I0(inf_abs0_2[27]),
.I1(inf_abs0_2[28]),
.O(g0_2_0_i2_lut6_2_O6)
);
defparam \d_cnst_sn.g0_2_0_i2_lut6_2_o6 .INIT=4'h1;
// @7:106
LUT4 \d_cnst_sn.g0_2_0_i2_lut6_2_o5 (
.I0(reg3[18]),
.I1(state[0]),
.I2(inf_abs0_2[18]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_5_890_i_0 )
);
defparam \d_cnst_sn.g0_2_0_i2_lut6_2_o5 .INIT=16'h111D;
// @7:47
LUT4 \d_cnst_sn.addr_20_iv_4_917_i_0_lut6_2_o6 (
.I0(reg3[17]),
.I1(state[0]),
.I2(inf_abs0_2[17]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_4_917_i_0 )
);
defparam \d_cnst_sn.addr_20_iv_4_917_i_0_lut6_2_o6 .INIT=16'h111D;
// @7:47
LUT3 \d_cnst_sn.addr_20_iv_4_917_i_0_lut6_2_o5 (
.I0(datai[17]),
.I1(state[0]),
.I2(inf_abs0_2[17]),
.O(ir_3[17])
);
defparam \d_cnst_sn.addr_20_iv_4_917_i_0_lut6_2_o5 .INIT=8'hE2;
// @7:47
LUT2 \d_cnst_sn.g0_3_o2_lut6_2_o6 (
.I0(inf_abs0_2[27]),
.I1(inf_abs0_2[28]),
.O(N_7)
);
defparam \d_cnst_sn.g0_3_o2_lut6_2_o6 .INIT=4'hE;
// @7:47
LUT4 \d_cnst_sn.g0_3_o2_lut6_2_o5 (
.I0(reg3[16]),
.I1(state[0]),
.I2(inf_abs0_2[16]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_3_944_i_0 )
);
defparam \d_cnst_sn.g0_3_o2_lut6_2_o5 .INIT=16'h111D;
// @7:47
LUT4 \d_cnst_sn.addr_20_iv_0_1025_i_0_lut6_2_o6 (
.I0(reg3[13]),
.I1(state[0]),
.I2(inf_abs0_2[13]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_0_1025_i_0 )
);
defparam \d_cnst_sn.addr_20_iv_0_1025_i_0_lut6_2_o6 .INIT=16'h111D;
// @7:47
LUT3 \d_cnst_sn.addr_20_iv_0_1025_i_0_lut6_2_o5 (
.I0(datai[13]),
.I1(state[0]),
.I2(inf_abs0_2[13]),
.O(ir_3[13])
);
defparam \d_cnst_sn.addr_20_iv_0_1025_i_0_lut6_2_o5 .INIT=8'hE2;
// @7:47
LUT4 \d_cnst_sn.addr_20_iv_1052_i_0_lut6_2_o6 (
.I0(reg3[12]),
.I1(state[0]),
.I2(inf_abs0_2[12]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_1052_i_0 )
);
defparam \d_cnst_sn.addr_20_iv_1052_i_0_lut6_2_o6 .INIT=16'h111D;
// @7:47
LUT3 \d_cnst_sn.addr_20_iv_1052_i_0_lut6_2_o5 (
.I0(datai[12]),
.I1(state[0]),
.I2(inf_abs0_2[12]),
.O(ir_3[12])
);
defparam \d_cnst_sn.addr_20_iv_1052_i_0_lut6_2_o5 .INIT=8'hE2;
// @7:47
LUT4 \d_cnst_sn.addr_20_iv_1_998_i_0_lut6_2_o6 (
.I0(reg3[14]),
.I1(state[0]),
.I2(inf_abs0_2[14]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_1_998_i_0 )
);
defparam \d_cnst_sn.addr_20_iv_1_998_i_0_lut6_2_o6 .INIT=16'h111D;
// @7:47
LUT3 \d_cnst_sn.addr_20_iv_1_998_i_0_lut6_2_o5 (
.I0(datai[14]),
.I1(state[0]),
.I2(inf_abs0_2[14]),
.O(ir_3[14])
);
defparam \d_cnst_sn.addr_20_iv_1_998_i_0_lut6_2_o5 .INIT=8'hE2;
// @7:47
LUT4 \d_cnst_sn.addr_20_iv_2_971_i_0_lut6_2_o6 (
.I0(reg3[15]),
.I1(state[0]),
.I2(inf_abs0_2[15]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.addr_20_iv_2_971_i_0 )
);
defparam \d_cnst_sn.addr_20_iv_2_971_i_0_lut6_2_o6 .INIT=16'h111D;
// @7:47
LUT3 \d_cnst_sn.addr_20_iv_2_971_i_0_lut6_2_o5 (
.I0(datai[15]),
.I1(state[0]),
.I2(inf_abs0_2[15]),
.O(ir_3[15])
);
defparam \d_cnst_sn.addr_20_iv_2_971_i_0_lut6_2_o5 .INIT=8'hE2;
// @7:47
LUT4 \d_cnst_sn.reg0_28_6_2393_a6_1_1_lut6_2_o6 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(reg3_1_1[22]),
.O(\d_cnst_sn.reg0_28_6_2393_a6_1_1 )
);
defparam \d_cnst_sn.reg0_28_6_2393_a6_1_1_lut6_2_o6 .INIT=16'h0100;
// @7:47
LUT3 \d_cnst_sn.reg0_28_6_2393_a6_1_1_lut6_2_o5 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.O(\d_cnst_sn.b60_0 )
);
defparam \d_cnst_sn.reg0_28_6_2393_a6_1_1_lut6_2_o5 .INIT=8'h02;
// @7:47
LUT2 \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_o6 (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[31]),
.O(N_512_i)
);
defparam \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_o6 .INIT=4'h2;
// @7:47
LUT3 \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_o5 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.O(\d_cnst_sn.reg0_m9_i_a3_0 )
);
defparam \d_cnst_sn.reg0_28_10_2261_a6_3_2_lut6_2_o5 .INIT=8'h06;
// @7:74
LUT5 \d_cnst_sn.reg0_28_0_lut6_2_o6[20] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.I3(r_4[19]),
.I4(reg3_1_1[20]),
.O(\d_cnst_sn.reg0_28_0 [20])
);
defparam \d_cnst_sn.reg0_28_0_lut6_2_o6[20] .INIT=32'hFFDF2202;
// @7:74
LUT3 \d_cnst_sn.reg0_28_0_lut6_2_o5[20] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[28]),
.O(\d_cnst_sn.reg0_28_7_a0_0 [9])
);
defparam \d_cnst_sn.reg0_28_0_lut6_2_o5[20] .INIT=8'h02;
// @7:74
LUT3 \d_cnst_sn.reg0_28_a2_0_lut6_2_o6[2] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.O(\d_cnst_sn.reg1_16_a2_0 [5])
);
defparam \d_cnst_sn.reg0_28_a2_0_lut6_2_o6[2] .INIT=8'hF1;
// @7:74
LUT2 \d_cnst_sn.reg0_28_a2_0_lut6_2_o5[2] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[31]),
.O(N_3913)
);
defparam \d_cnst_sn.reg0_28_a2_0_lut6_2_o5[2] .INIT=4'hD;
// @7:74
LUT3 \d_cnst_sn.reg2_16_11_a0_0_lut6_2_o6[31] (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[31]),
.O(\d_cnst_sn.reg2_N_3_mux )
);
defparam \d_cnst_sn.reg2_16_11_a0_0_lut6_2_o6[31] .INIT=8'hF1;
// @7:74
LUT5 \d_cnst_sn.reg2_16_11_a0_0_lut6_2_o5[31] (
.I0(reg3[0]),
.I1(inf_abs0_2[19]),
.I2(inf_abs0_2[20]),
.I3(inf_abs0_2[31]),
.I4(m_2[0]),
.O(N_1335)
);
defparam \d_cnst_sn.reg2_16_11_a0_0_lut6_2_o5[31] .INIT=32'hFFFB0008;
// @7:179
LUT3 \d_cnst_sn.b64_0_lut6_2_o6 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.O(\d_cnst_sn.b64_0 )
);
defparam \d_cnst_sn.b64_0_lut6_2_o6 .INIT=8'h04;
// @7:179
LUT2 \d_cnst_sn.b64_0_lut6_2_o5 (
.I0(inf_abs0_2[31]),
.I1(inf_abs0_2[27]),
.O(N_526_i)
);
defparam \d_cnst_sn.b64_0_lut6_2_o5 .INIT=4'h4;
// @7:105
LUT4 \d_cnst_sn.m_2_lut6_2_o6[30] (
.I0(datai[30]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[30])
);
defparam \d_cnst_sn.m_2_lut6_2_o6[30] .INIT=16'h2220;
// @7:105
LUT4 \d_cnst_sn.m_2_lut6_2_o5[30] (
.I0(datai[31]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2[31])
);
defparam \d_cnst_sn.m_2_lut6_2_o5[30] .INIT=16'h2220;
// @7:184
LUT3 \d_cnst_sn.reg0_28_sn_m6_lut6_2_o6 (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.O(N_3916)
);
defparam \d_cnst_sn.reg0_28_sn_m6_lut6_2_o6 .INIT=8'h06;
// @7:184
LUT3 \d_cnst_sn.reg0_28_sn_m6_lut6_2_o5 (
.I0(b),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.O(reg0_28_sn_m6_lut6_2_O5)
);
defparam \d_cnst_sn.reg0_28_sn_m6_lut6_2_o5 .INIT=8'h20;
// @7:47
LUT4 \d_cnst_sn.reg0_m9_i_a0_0_lut6_2_o6 (
.I0(b),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[27]),
.O(\d_cnst_sn.reg0_m9_i_a0_0 )
);
defparam \d_cnst_sn.reg0_m9_i_a0_0_lut6_2_o6 .INIT=16'h040C;
// @7:47
LUT2 \d_cnst_sn.reg0_m9_i_a0_0_lut6_2_o5 (
.I0(state[0]),
.I1(inf_abs0_2[27]),
.O(N_2660_2)
);
defparam \d_cnst_sn.reg0_m9_i_a0_0_lut6_2_o5 .INIT=4'h8;
// @7:74
LUT4 \d_cnst_sn.reg0_28_a1_1_lut6_2_o6[7] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.O(N_3910)
);
defparam \d_cnst_sn.reg0_28_a1_1_lut6_2_o6[7] .INIT=16'h0002;
// @7:74
LUT4 \d_cnst_sn.reg0_28_a1_1_lut6_2_o5[7] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.g0_3_a2_2 )
);
defparam \d_cnst_sn.reg0_28_a1_1_lut6_2_o5[7] .INIT=16'h0008;
// @7:74
LUT4 \d_cnst_sn.reg0_28_a1_1_lut6_2_o6[2] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.reg0_28_a1_1 [4])
);
defparam \d_cnst_sn.reg0_28_a1_1_lut6_2_o6[2] .INIT=16'h0800;
// @7:74
LUT4 \d_cnst_sn.reg0_28_a1_1_lut6_2_o5[2] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.O(\d_cnst_sn.reg0_28_9_2294_a6_3_0 )
);
defparam \d_cnst_sn.reg0_28_a1_1_lut6_2_o5[2] .INIT=16'h0002;
// @7:74
LUT4 \d_cnst_sn.reg0_28_a0_1_lut6_2_o6[7] (
.I0(inf_abs0_2[20]),
.I1(inf_abs0_2[21]),
.I2(inf_abs0_2[22]),
.I3(inf_abs0_2[31]),
.O(\d_cnst_sn.reg0_28_a0_1 [7])
);
defparam \d_cnst_sn.reg0_28_a0_1_lut6_2_o6[7] .INIT=16'hFF01;
// @7:74
LUT4 \d_cnst_sn.reg0_28_a0_1_lut6_2_o5[7] (
.I0(inf_abs0_2[21]),
.I1(inf_abs0_2[22]),
.I2(inf_abs0_2[31]),
.I3(inf_abs0_2[28]),
.O(\d_cnst_sn.reg1_16_a0_1 [3])
);
defparam \d_cnst_sn.reg0_28_a0_1_lut6_2_o5[7] .INIT=16'h0008;
// @7:243
LUT4 \d_cnst_sn.m_2_i_lut6_2_o6[31] (
.I0(datai[31]),
.I1(inf_abs0_2[31]),
.I2(inf_abs0_2[27]),
.I3(inf_abs0_2[28]),
.O(m_2_i[31])
);
defparam \d_cnst_sn.m_2_i_lut6_2_o6[31] .INIT=16'hDDDF;
// @7:243
LUT3 \d_cnst_sn.m_2_i_lut6_2_o5[31] (
.I0(datai[31]),
.I1(state[0]),
.I2(inf_abs0_2[31]),
.O(ir_3_fast[31])
);
defparam \d_cnst_sn.m_2_i_lut6_2_o5[31] .INIT=8'hE2;
// @7:184
LUT4 \d_cnst_sn.reg0_28_sn_m4_lut6_2_o6 (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[31]),
.O(N_1033)
);
defparam \d_cnst_sn.reg0_28_sn_m4_lut6_2_o6 .INIT=16'hFF35;
// @7:184
LUT5 \d_cnst_sn.reg0_28_sn_m4_lut6_2_o5 (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.O(\d_cnst_sn.reg2_16_11_1_tz [28])
);
defparam \d_cnst_sn.reg0_28_sn_m4_lut6_2_o5 .INIT=32'hFFFFFACF;
// @7:74
LUT5 \d_cnst_sn.un1_state_1_1_a6_0_lut6_2_o6 (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.O(N_1892)
);
defparam \d_cnst_sn.un1_state_1_1_a6_0_lut6_2_o6 .INIT=32'h0000E000;
// @7:74
LUT5 \d_cnst_sn.un1_state_1_1_a6_0_lut6_2_o5 (
.I0(inf_abs0_2[19]),
.I1(inf_abs0_2[20]),
.I2(inf_abs0_2[21]),
.I3(inf_abs0_2[22]),
.I4(inf_abs0_2[31]),
.O(\d_cnst_sn.reg2_16_0_1_tz [28])
);
defparam \d_cnst_sn.un1_state_1_1_a6_0_lut6_2_o5 .INIT=32'hFFFFF53F;
// @7:143
LUT4 b18_df30_lut6_2_o6 (
.I0(m_2_i[31]),
.I1(r_4[30]),
.I2(m_2[30]),
.I3(r_4_i[31]),
.O(b18_df30)
);
defparam b18_df30_lut6_2_o6.INIT=16'h8241;
// @7:143
LUT4 b18_df30_lut6_2_o5 (
.I0(m_2_i[31]),
.I1(r_4[30]),
.I2(m_2[30]),
.I3(r_4_i[31]),
.O(b18_lt30)
);
defparam b18_df30_lut6_2_o5.INIT=16'h5D04;
// @7:118
LUT4 un11_r_df30_lut6_2_o6 (
.I0(m_2_i[31]),
.I1(r_4[30]),
.I2(m_2[30]),
.I3(r_4_i[31]),
.O(un11_r_df30)
);
defparam un11_r_df30_lut6_2_o6.INIT=16'h8241;
// @7:118
LUT4 un11_r_df30_lut6_2_o5 (
.I0(m_2_i[31]),
.I1(r_4[30]),
.I2(m_2[30]),
.I3(r_4_i[31]),
.O(un11_r_lt30)
);
defparam un11_r_df30_lut6_2_o5.INIT=16'h20BA;
endmodule /* b14 */
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cmp_sram_redhdr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: Efuse Cluster
// Unit Name: cmp_redhdr (sram redundancy header)
// Block Name: EFC
//
// This is the header used to read and write the fuse values to the
// RAM blocks. It is used to drive the ICD, DCD and L2T. It is
// outside the array it is driving.
//
// Top level signal renaming:
// s/ary/<your_ary_name>/g
// s/xfuse/<your_ary_initial>fuse/g
//
// E.g. fuse_ary_wren -> fuse_icd_wren
// efc_spc_xfuse_data -> efc_spc_ifuse_data, efc_sct_fuse_data
//
//-----------------------------------------------------------------------------
`include "sys.h"
`include "iop.h"
//FPGA_SYN enables all FPGA related modifications
`ifdef FPGA_SYN
`define FPGA_SYN_CLK
`endif
module cmp_sram_redhdr (/*AUTOARG*/
// Outputs
fuse_ary_wren, fuse_ary_rid, fuse_ary_repair_value,
fuse_ary_repair_en, spc_efc_xfuse_data, scanout,
// Inputs
rclk, se, scanin, arst_l, testmode_l, efc_spc_fuse_clk1,
efc_spc_fuse_clk2, efc_spc_xfuse_data, efc_spc_xfuse_ashift,
efc_spc_xfuse_dshift, ary_fuse_repair_value, ary_fuse_repair_en
);
input rclk;
input se;
input scanin; // CMP clock, L1 phase
input arst_l;
input testmode_l;
// eFuse controller interface
input efc_spc_fuse_clk1;
input efc_spc_fuse_clk2;
input efc_spc_xfuse_data;
input efc_spc_xfuse_ashift; // addr shift; low during rst
input efc_spc_xfuse_dshift; // data shift; low during rst
// interface to cache redundancy logic
input [7:0] ary_fuse_repair_value; //data out for redundancy register
input [1:0] ary_fuse_repair_en; //enable bits out
// outputs
// interface to icache
output fuse_ary_wren; //redundancy reg wr enable, qualified
output [5:0] fuse_ary_rid; //redundancy register id
output [7:0] fuse_ary_repair_value;//data in for redundancy register
output [1:0] fuse_ary_repair_en; //enable bits to turn on redundancy
// serial rd data to controller
output spc_efc_xfuse_data;
// normal scan out
output scanout;
`ifdef FPGA_SYN_CLK
assign fuse_ary_wren = 1'b0;
assign fuse_ary_rid = 6'b0;
assign fuse_ary_repair_value = 8'b0;
assign fuse_ary_repair_en = 2'b0;
assign spc_efc_xfuse_data = 1'b0;
assign scanout = 1'b0;
`else
// local signals
wire clk;
wire int_clk1;
wire int_clk2;
wire int_scanout; // !! hook up to last flop in scan chain !!
wire int_scanin; // !! hook up to 1st flop in scan chain !!
wire [6:0] addr_shft_nxt;
wire [6:0] addr_shft_ff;
wire addr_shft_en;
wire wren_bit;
wire [11:0] data_shft_nxt;
wire [11:0] data_shft_ff;
wire data_shft_en;
wire dshift_dly1_ff;
wire dshift_dly2_ff;
wire ashift_dly1_ff;
wire ashift_dly2_ff;
wire wren_ff;
wire wren_ph1;
wire rden_ph1;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
//
// Code Begins Here
//
assign clk = rclk;
// Test logic
assign int_clk1 = (~testmode_l) ? rclk : efc_spc_fuse_clk1;
assign int_clk2 = (~testmode_l) ? rclk : efc_spc_fuse_clk2;
assign int_scanout = 1'b0;
// Need latch to avoid hold time problems
// connect int_scanout to last flop in scan chain
bw_u1_scanlg_2x so_lockup(.so (scanout),
.sd (int_scanout),
.ck (clk), .se(se));
// connect int_scanin to first flop in scan chain
bw_u1_scanlg_2x si_lockup(.so (int_scanin),
.sd (scanin),
.ck (clk), .se(se));
// Shift registers
// Address
assign addr_shft_en = efc_spc_xfuse_ashift;
assign addr_shft_nxt = {addr_shft_ff[5:0], efc_spc_xfuse_data};
dffe_s #(7) addr_shft_reg (.din (addr_shft_nxt),
.q (addr_shft_ff),
.en (addr_shft_en),
.clk (int_clk1), .se(se), .si(), .so());
assign fuse_ary_rid[5:0] = addr_shft_ff[6:1];
assign wren_bit = addr_shft_ff[0];
// Data
assign data_shft_en = efc_spc_xfuse_dshift | dshift_dly1_ff | rden_ph1;
// mux2es
assign data_shft_nxt = rden_ph1
? {{3{ary_fuse_repair_en[1]}},
ary_fuse_repair_value[7:0],
ary_fuse_repair_en[0]}
: {data_shft_ff[10:0],
efc_spc_xfuse_data};
// 10:9 is unused
dffe_s #(12) data_shft_reg (.din (data_shft_nxt),
.q (data_shft_ff),
.en (data_shft_en),
.clk (int_clk1), .se(se), .si(), .so());
assign fuse_ary_repair_value = data_shft_ff[8:1];
assign fuse_ary_repair_en = {(data_shft_ff[11] & wren_ff),
(data_shft_ff[0] & wren_ff)};
// Control
dff_s #(1) ashift_dly1_reg (.din (efc_spc_xfuse_ashift),
.q (ashift_dly1_ff),
.clk (int_clk1), .se(se), .si(), .so());
dff_s #(1) ashift_dly2_reg (.din (ashift_dly1_ff),
.q (ashift_dly2_ff),
.clk (int_clk1), .se(se), .si(), .so());
dffrl_async #(1) dshift_dly1_reg (.din (efc_spc_xfuse_dshift),
.q (dshift_dly1_ff),
.rst_l (arst_l),
.clk (int_clk1), .se(se), .si(), .so());
dffrl_async #(1) dshift_dly2_reg (.din (dshift_dly1_ff),
.q (dshift_dly2_ff),
.rst_l (arst_l),
.clk (int_clk1), .se(se), .si(), .so());
assign wren_ph1 = dshift_dly2_ff && ~dshift_dly1_ff && wren_bit;
assign rden_ph1 = ashift_dly2_ff && ~ashift_dly1_ff && ~wren_bit;
// use phase two for wren since array writes in phase one
dffrl_async #(1) wren_reg (.din (wren_ph1),
.q (wren_ff),
.rst_l (arst_l),
.clk (int_clk2), .se(se), .si(), .so());
// address is never shifted out
assign spc_efc_xfuse_data = data_shft_ff[11];
assign fuse_ary_wren = wren_ff & testmode_l;
`endif
endmodule // cmp_sram_redhdr
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// verilog-library-files: ("../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_BLACKBOX_V
`define SKY130_FD_SC_HS__EDFXTP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__edfxtp (
Q ,
CLK,
D ,
DE
);
output Q ;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 18:17:58 09/26/2015
// Design Name: Multiplication controller
// Module Name: Controller
//////////////////////////////////////////////////////////////////////////////////
module Controller(Clock, Reset, Start, Shift1, Shift0, Clear);
input Clock, Reset, Start;
output reg [2:0] Shift0;
output reg [2:0] Shift1;
output reg Clear;
parameter State0 = 4'b0000;
parameter State1 = 4'b0001;
parameter State2 = 4'b0010;
parameter State3 = 4'b0011;
parameter State4 = 4'b0100;
parameter State5 = 4'b0101;
parameter State6 = 4'b0110;
parameter State7 = 4'b0111;
parameter State8 = 4'b1000;
parameter State9 = 4'b1001;
parameter State10 = 4'b1010;
parameter State11 = 4'b1011;
reg [3:0] CurrentState;
reg [3:0] NextState;
always @ CurrentState
case (CurrentState)
State0: {Clear, Shift1, Shift0} <= 7'b1000000; // Do nothing
State1: {Clear, Shift1, Shift0} <= 7'b0000000; // Clear the registers
State2: {Clear, Shift1, Shift0} <= 7'b1101101; // Initialize registers
State3: {Clear, Shift1, Shift0} <= 7'b1010010; // Add and put in top half or product
State4: {Clear, Shift1, Shift0} <= 7'b1111000; // Shift product and multiplier
State5: {Clear, Shift1, Shift0} <= 7'b1010010; // Now we just repeat the last two
State6: {Clear, Shift1, Shift0} <= 7'b1111000;
State7: {Clear, Shift1, Shift0} <= 7'b1010010;
State8: {Clear, Shift1, Shift0} <= 7'b1111000;
State9: {Clear, Shift1, Shift0} <= 7'b1010010;
State10: {Clear, Shift1, Shift0} <= 7'b1111000;
State11: {Clear, Shift1, Shift0} <= 7'b1000000; // We're done
endcase
always @ (posedge Clock or negedge Reset)
if (Reset == 0) begin CurrentState <= State0; NextState <= State0; end
else CurrentState <= NextState;
always @ (CurrentState or Start or NextState)
case (CurrentState)
State0: if (Start == 1) NextState <= State1;
State1: NextState <= State2;
State2: NextState <= State3;
State3: NextState <= State4;
State4: NextState <= State5;
State5: NextState <= State6;
State6: NextState <= State7;
State7: NextState <= State8;
State8: NextState <= State9;
State9: NextState <= State10;
State10: NextState <= State11;
endcase
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:54:48 02/29/2016
// Design Name:
// Module Name: DivFrec
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DivFrec(clk,rst,div,clkd,clk_1kHz);
input wire clk,rst;
input wire [10:0]div;
output wire clkd;
output wire clk_1kHz;
reg [10:0]q = 0;
reg cd = 0;
reg [15:0]q_1kHz = 0;
reg cd_1kHz = 0;
// Para generar el clock dividido variable a partir de la cuenta
always@(posedge clk, posedge rst)
if (rst)
begin
q <= 0;
cd <=0;
end
else
if (q==div)
begin
q <= 0;
cd <= ~cd;
end
else
q <= q + 11'b1;
assign clkd = cd;
// Para generar el clock dividido fijo de 1 kHz
always@(posedge clk, posedge rst)
if (rst)
begin
q_1kHz <= 0;
cd_1kHz <=0;
end
else
if (q_1kHz==16'd49999)
begin
q_1kHz <= 0;
cd_1kHz <= ~cd_1kHz;
end
else
q_1kHz <= q_1kHz + 16'b1;
assign clk_1kHz = cd_1kHz;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_SYMBOL_V
`define SKY130_FD_SC_HVL__DLCLKP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_SYMBOL_V
|
module decode(MmemData, fromPipe1PC, IR, PC_Imm, rA1, rA2, wA, Sext_Imm6, Imm970, Mex1, Mex2, wMem, alu_ctrl, MregWB, MmemR, MmemW, Mr7WB);
output [15:0] PC_Imm, Sext_Imm6, Imm970;
output reg [2:0] rA1, rA2, wA, MregWB;
output reg MmemData;
integer i;
output reg Mex1, Mex2, wMem, alu_ctrl, MmemR, MmemW;
output reg [3:0] Mr7WB;
input [15:0] fromPipe1PC, IR;//from pipe1
wire [15:0] imm6, imm9;
wire select, offset;
wire [8:0] LM_Imm; //Only for LM & SM instruction
assign LM_Imm = IR[8:0];
assign imm6 = {10'd0, IR[5:0]};
assign imm9 = {7'd0, IR[8:0]};
assign select = (IR[15:12]==4'B1000)?1'b0:1'b1; //If opcode is 1000 then select data0.
mux16x2 m1(.data0(imm9), .data1(imm6), .selectInput(select), .out(offset));
add add1(.in1(fromPipe1PC),.in2(offset),.out(PC_Imm));
sext6 s1(.in(IR[5:0]), .out(Sext_Imm6));
assign Imm970 = {IR[8:0], 7'd0};
always@(*)
begin
case (IR[15:12])
4'b0000: //ADD, ADC, ADZ
begin
rA2<= IR[8:6]; //RB
wA<= IR[5:3]; //RC
rA1<= IR[11:9]; //RA
Mex1<= 0; //Rfout1
Mex2<= 0; //Rfout2
alu_ctrl<=0; //Add operation
wMem<=1; // No memory write
MmemR<=0; //Don't Care
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=1; //Write back Alu_out
if(IR[5:3]==3'b111) //If RC is R7
Mr7WB<=3; //Write back Alu_out to R7
else
Mr7WB<=0; //Don't Care
end
4'b0001: //ADI
begin
rA1<= IR[11:9]; //RA
rA2<= 3'b000; //Don't Care
wA<= IR[8:6]; //RB
Mex1<= 0; //Rfout1
Mex2<= 1; //Sext_Imm6;
alu_ctrl<=0; //ADD
wMem<=1; // No memory write
MmemR<=0; //Don't Care
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=1; //Write back Alu_out
if(IR[8:6]==3'b111) //If RB is R7
Mr7WB<=3; //Write back Alu_out to R7
else
Mr7WB<=0; //Don't Care
end
4'b0010: //NDU, NDC, NDZ
begin
rA2<= IR[8:6]; //RB
wA<= IR[5:3]; //RC
rA1<= IR[11:9]; //RA
Mex1<= 0; //Rfout1
Mex2<= 0; //Rfout2
alu_ctrl<=1; //Nand operation
wMem<=1; // No memory write
MmemR<=0; //Don't Care
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=1; //Write back Alu_out
if(IR[5:3]==3'b111) //If RC is R7
Mr7WB<=3; //Write back Alu_out to R7
else
Mr7WB<=0; //Don't Care
end
4'b0011: //LHI
begin
wA<= IR[11:9]; //RA
rA1<= 3'b000; //Don't Care
rA2<= 3'b000; //Don't Care
Mex1<=0; //Don't care
Mex2<=0; //Don't care
alu_ctrl<=0; //Don't care
wMem<=1; //No memory write
MmemR<=0; //Don't Care
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=2; //Write back Imm970 to RA
if(IR[11:9]==3'b111) //If RA is R7
Mr7WB<=0; // Write back Imm970 to R7
else
Mr7WB<=0; //Don't Care
end
4'b0100: //LW
begin
wA<= IR[11:9]; //RA
rA2<=IR[8:6]; //RB
rA1<=3'b000; //Don't Care
Mex1<=1; //Sign Extended Immediate six bit
Mex2<=0; //Rfout2
alu_ctrl<=0; //ADD
wMem<=1; //No memory write
MmemR<=1; //Read from memory using address in Alu_out
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=0; //Write back mem_data
if(IR[11:9]==3'b111) //If RA is R7
Mr7WB<=1; // Write back mem_data to R7
else
Mr7WB<=0; //Don't Care
end
4'b0101: //SW
begin
rA2<= IR[8:6]; //RB
rA1<= IR[11:9]; //RA
wA<= 3'b000; //Don't Care
Mex1<=1; //Sign Extended Immediate six bit
Mex2<=0; //Rfout2
alu_ctrl<=0; //Add
wMem<=0; // Write to memory
MmemR<=0; //Don't Care
MmemW<=1; //Write to memory. address in Alu_out
MmemData<=0; //Write to memory. Data present in rfout1
MregWB<=0; //Don't Care
Mr7WB<=0; //Don't Care
end
4'b0110: //LM
begin
rA1<= IR[11:9]; //RA
rA2<=3'b000; //Don't Care
if(LM_Imm[0]==1)
wA <=3'b000;
else if(LM_Imm[1]==1)
wA <=3'b001;
else if(LM_Imm[2]==1)
wA <=3'b010;
else if(LM_Imm[3]==1)
wA <=3'b011;
else if(LM_Imm[4]==1)
wA <=3'b100;
else if(LM_Imm[5]==1)
wA <=3'b101;
else if(LM_Imm[6]==1)
wA <=3'b110;
else if(LM_Imm[7]==1)
wA <=3'b111;
pipe2IR[11:9]<=wA;
Mex1<=0; //Don't care
Mex2<=0; //Don't Care
alu_ctrl<=0; //Don't Care
wMem<=1; //No memory write operation
MmemR<=0; //Read from memory using address stored in RA
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=0; //Write back the value in mem_data
if(IR[11:9]==3'b111) //If RA is R7
Mr7WB<=1; // Write back mem_data to R7
else
Mr7WB<=0; //Don't Care
end
4'b0111: //SM
begin
rA1<= IR[11:9]; //RA
wA<= 3'b000; //Don't Care
if(LM_Imm[0]==1)
rA2 <=3'b000;
else if(LM_Imm[1]==1)
rA2 <=3'b001;
else if(LM_Imm[2]==1)
rA2 <=3'b010;
else if(LM_Imm[3]==1)
rA2 <=3'b011;
else if(LM_Imm[4]==1)
rA2 <=3'b100;
else if(LM_Imm[5]==1)
rA2 <=3'b101;
else if(LM_Imm[6]==1)
rA2 <=3'b110;
else if(LM_Imm[7]==1)
rA2 <=3'b111;
Mex1<=0; //Don't care
Mex2<=0; //Don't Care
alu_ctrl<=0; //Don't Care
wMem<=1; //Write memory operation done
MmemR<=0; //Don't Care
MmemW<=0; //Write to memory. address in RA
MmemData<=1; //Write to memory. data in Rfout2
MregWB<=0; //Don't Care
Mr7WB<=0; //Don't Care
end
4'b1100: //BEQ
begin
rA1<= IR[11:9]; //RA
rA2<= IR[8:6]; //RB
wA<= 3'b000; //Don't Care
Mex1<=0; //Don't care
Mex2<=0; //Don't Care
alu_ctrl<=0; //Don't Care
wMem<=1; //No memory write
MmemR<=0; //Don't Care
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=0; //Don't Care
Mr7WB<=2; //PC_Imm -> r7
end
4'b1000: //JAL
begin
rA1<= 3'b000; //Don't Care
rA2<= 3'b000; //Don't Care
wA<= IR[11:9]; //RA
Mex1<=0; //Don't care
Mex2<=0; //Don't Care
alu_ctrl<=0; //Don't Care
wMem<=1; //Don't disturb your memory
MmemR<=0; //Don't Care
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=3; //Write back PC+1
Mr7WB<=2; //PC_Imm -> r7
end
4'b1001: //JLR
begin
rA1<= 3'b000; //Don't Care
rA2<= IR[8:6]; //RB
wA<= IR[11:9]; //RA
Mex1<=0; //Don't care
Mex2<=0; //Don't Care
alu_ctrl<=0; //Don't Care
wMem<=1; //Don't disturb your memory
MmemR<=0; //Don't Care
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=3; //Write back PC+1
Mr7WB<=4; //Write Rfout2 to R7
end
default:
begin
rA1<=3'b000;
rA2<=3'b000;
wA<= 3'b000;
Mex1<=0; //Don't care
Mex2<=0; //Don't Care
alu_ctrl<=0; //Don't Care
wMem<=1; //Don't disturb your memory
MmemR<=0; //Don't Care
MmemW<=0; //Don't Care
MmemData<=0; //Don't Care
MregWB<=0;
Mr7WB<=0;
endcase
end
endmodule
module sext6(in, out); // Sign Extension 6 to 16
input [5:0] in;
output [15:0] out;
assign out = {{10{in[5]}}, in[5:0]};
endmodule
module add(in1, in2 , out); // Implements a full 16-bit adder
output [15:0] out;
input [15:0] in1, in2;
wire [16:0] outTemp;
assign outTemp = in1 + in2;
assign out = outTemp[15:0];
endmodule
module mux16x8(data0, data1, data2, data3, data4, data5, data6, data7, selectInput, out); // 8-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3, data4, data5, data6, data7;
input [2:0] selectInput;
always@(data0 or data1 or data2 or data3 or data4 or data5 or data6 or data7 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
4: out = data4;
5: out = data5;
6: out = data6;
7: out = data7;
endcase
end
endmodule
module mux2x4(data0, data1, data2, data3,selectInput,out);
output reg[1:0] out;
input [1:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule
module mux16x4(data0, data1, data2, data3, selectInput, out); // 4-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1, data2, data3;
input [1:0] selectInput;
always@(data0 or data1 or data2 or data3 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
2: out = data2;
3: out = data3;
endcase
end
endmodule
module mux16x2(data0, data1, selectInput, out); // 2-16bit-input mux
output reg [15:0] out;
input [15:0] data0, data1;
input selectInput;
always@(data0 or data1 or selectInput) begin
case(selectInput)
0: out = data0;
1: out = data1;
endcase
end
endmodule
|
// megafunction wizard: %ALTFP_COMPARE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_compare
// ============================================================
// File Name: fp_compare.v
// Megafunction Name(s):
// altfp_compare
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//altfp_compare CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" PIPELINE=3 WIDTH_EXP=8 WIDTH_MAN=23 aeb ageb aleb clock dataa datab
//VERSION_BEGIN 14.1 cbx_altfp_compare 2014:12:03:18:16:05:SJ cbx_cycloneii 2014:12:03:18:16:05:SJ cbx_lpm_add_sub 2014:12:03:18:16:05:SJ cbx_lpm_compare 2014:12:03:18:16:05:SJ cbx_mgl 2014:12:03:20:51:57:SJ cbx_stratix 2014:12:03:18:16:05:SJ cbx_stratixii 2014:12:03:18:16:05:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_compare 4 reg 21
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module fp_compare_altfp_compare_orb
(
aeb,
ageb,
aleb,
clock,
dataa,
datab) ;
output aeb;
output ageb;
output aleb;
input clock;
input [31:0] dataa;
input [31:0] datab;
reg aligned_dataa_sign_adjusted_w_dffe2;
reg aligned_dataa_sign_dffe1;
reg aligned_datab_sign_adjusted_w_dffe2;
reg aligned_datab_sign_dffe1;
reg both_inputs_zero_dffe2;
reg exp_a_all_one_w_dffe1;
reg exp_a_not_zero_w_dffe1;
reg exp_aeb_w_dffe2;
reg exp_agb_w_dffe2;
reg exp_b_all_one_w_dffe1;
reg exp_b_not_zero_w_dffe1;
reg flip_outputs_dffe2;
reg input_dataa_nan_dffe2;
reg input_datab_nan_dffe2;
reg [1:0] man_a_not_zero_w_dffe1;
reg [1:0] man_b_not_zero_w_dffe1;
reg out_aeb_w_dffe3;
reg out_ageb_w_dffe3;
reg out_aleb_w_dffe3;
wire wire_cmpr1_aeb;
wire wire_cmpr1_agb;
wire wire_cmpr2_aeb;
wire wire_cmpr2_agb;
wire wire_cmpr3_aeb;
wire wire_cmpr3_agb;
wire wire_cmpr4_aeb;
wire wire_cmpr4_agb;
wire aclr;
wire aligned_dataa_sign_adjusted_dffe2_wi;
wire aligned_dataa_sign_adjusted_dffe2_wo;
wire aligned_dataa_sign_adjusted_w;
wire aligned_dataa_sign_dffe1_wi;
wire aligned_dataa_sign_dffe1_wo;
wire aligned_dataa_sign_w;
wire [30:0] aligned_dataa_w;
wire aligned_datab_sign_adjusted_dffe2_wi;
wire aligned_datab_sign_adjusted_dffe2_wo;
wire aligned_datab_sign_adjusted_w;
wire aligned_datab_sign_dffe1_wi;
wire aligned_datab_sign_dffe1_wo;
wire aligned_datab_sign_w;
wire [30:0] aligned_datab_w;
wire both_inputs_zero;
wire both_inputs_zero_dffe2_wi;
wire both_inputs_zero_dffe2_wo;
wire clk_en;
wire exp_a_all_one_dffe1_wi;
wire exp_a_all_one_dffe1_wo;
wire [7:0] exp_a_all_one_w;
wire exp_a_not_zero_dffe1_wi;
wire exp_a_not_zero_dffe1_wo;
wire [7:0] exp_a_not_zero_w;
wire [3:0] exp_aeb;
wire [3:0] exp_aeb_tmp_w;
wire exp_aeb_w;
wire exp_aeb_w_dffe2_wi;
wire exp_aeb_w_dffe2_wo;
wire [3:0] exp_agb;
wire [3:0] exp_agb_tmp_w;
wire exp_agb_w;
wire exp_agb_w_dffe2_wi;
wire exp_agb_w_dffe2_wo;
wire exp_b_all_one_dffe1_wi;
wire exp_b_all_one_dffe1_wo;
wire [7:0] exp_b_all_one_w;
wire exp_b_not_zero_dffe1_wi;
wire exp_b_not_zero_dffe1_wo;
wire [7:0] exp_b_not_zero_w;
wire [2:0] exp_eq_grp;
wire [3:0] exp_eq_gt_grp;
wire flip_outputs_dffe2_wi;
wire flip_outputs_dffe2_wo;
wire flip_outputs_w;
wire input_dataa_nan_dffe2_wi;
wire input_dataa_nan_dffe2_wo;
wire input_dataa_nan_w;
wire input_dataa_zero_w;
wire input_datab_nan_dffe2_wi;
wire input_datab_nan_dffe2_wo;
wire input_datab_nan_w;
wire input_datab_zero_w;
wire [1:0] man_a_not_zero_dffe1_wi;
wire [1:0] man_a_not_zero_dffe1_wo;
wire [1:0] man_a_not_zero_merge_w;
wire [22:0] man_a_not_zero_w;
wire [1:0] man_b_not_zero_dffe1_wi;
wire [1:0] man_b_not_zero_dffe1_wo;
wire [1:0] man_b_not_zero_merge_w;
wire [22:0] man_b_not_zero_w;
wire out_aeb_dffe3_wi;
wire out_aeb_dffe3_wo;
wire out_aeb_w;
wire out_agb_w;
wire out_ageb_dffe3_wi;
wire out_ageb_dffe3_wo;
wire out_ageb_w;
wire out_alb_w;
wire out_aleb_dffe3_wi;
wire out_aleb_dffe3_wo;
wire out_aleb_w;
wire out_unordered_w;
// synopsys translate_off
initial
aligned_dataa_sign_adjusted_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_adjusted_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_adjusted_w_dffe2 <= aligned_dataa_sign_adjusted_dffe2_wi;
// synopsys translate_off
initial
aligned_dataa_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_dffe1 <= aligned_dataa_sign_dffe1_wi;
// synopsys translate_off
initial
aligned_datab_sign_adjusted_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_adjusted_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_adjusted_w_dffe2 <= aligned_datab_sign_adjusted_dffe2_wi;
// synopsys translate_off
initial
aligned_datab_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_dffe1 <= aligned_datab_sign_dffe1_wi;
// synopsys translate_off
initial
both_inputs_zero_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_inputs_zero_dffe2 <= 1'b0;
else if (clk_en == 1'b1) both_inputs_zero_dffe2 <= both_inputs_zero_dffe2_wi;
// synopsys translate_off
initial
exp_a_all_one_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_a_all_one_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_a_all_one_w_dffe1 <= exp_a_all_one_dffe1_wi;
// synopsys translate_off
initial
exp_a_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_a_not_zero_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_a_not_zero_w_dffe1 <= exp_a_not_zero_dffe1_wi;
// synopsys translate_off
initial
exp_aeb_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_aeb_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) exp_aeb_w_dffe2 <= exp_aeb_w_dffe2_wi;
// synopsys translate_off
initial
exp_agb_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_agb_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) exp_agb_w_dffe2 <= exp_agb_w_dffe2_wi;
// synopsys translate_off
initial
exp_b_all_one_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_b_all_one_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_b_all_one_w_dffe1 <= exp_b_all_one_dffe1_wi;
// synopsys translate_off
initial
exp_b_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_b_not_zero_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_b_not_zero_w_dffe1 <= exp_b_not_zero_dffe1_wi;
// synopsys translate_off
initial
flip_outputs_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) flip_outputs_dffe2 <= 1'b0;
else if (clk_en == 1'b1) flip_outputs_dffe2 <= flip_outputs_dffe2_wi;
// synopsys translate_off
initial
input_dataa_nan_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_dataa_nan_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_dataa_nan_dffe2 <= input_dataa_nan_dffe2_wi;
// synopsys translate_off
initial
input_datab_nan_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_datab_nan_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_datab_nan_dffe2 <= input_datab_nan_dffe2_wi;
// synopsys translate_off
initial
man_a_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_a_not_zero_w_dffe1 <= 2'b0;
else if (clk_en == 1'b1) man_a_not_zero_w_dffe1 <= man_a_not_zero_dffe1_wi;
// synopsys translate_off
initial
man_b_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_b_not_zero_w_dffe1 <= 2'b0;
else if (clk_en == 1'b1) man_b_not_zero_w_dffe1 <= man_b_not_zero_dffe1_wi;
// synopsys translate_off
initial
out_aeb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aeb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aeb_w_dffe3 <= out_aeb_dffe3_wi;
// synopsys translate_off
initial
out_ageb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_ageb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_ageb_w_dffe3 <= out_ageb_dffe3_wi;
// synopsys translate_off
initial
out_aleb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aleb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aleb_w_dffe3 <= out_aleb_dffe3_wi;
lpm_compare cmpr1
(
.aclr(aclr),
.aeb(wire_cmpr1_aeb),
.agb(wire_cmpr1_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[30:23]),
.datab(aligned_datab_w[30:23]));
defparam
cmpr1.lpm_pipeline = 1,
cmpr1.lpm_representation = "UNSIGNED",
cmpr1.lpm_width = 8,
cmpr1.lpm_type = "lpm_compare";
lpm_compare cmpr2
(
.aclr(aclr),
.aeb(wire_cmpr2_aeb),
.agb(wire_cmpr2_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[22:15]),
.datab(aligned_datab_w[22:15]));
defparam
cmpr2.lpm_pipeline = 1,
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 8,
cmpr2.lpm_type = "lpm_compare";
lpm_compare cmpr3
(
.aclr(aclr),
.aeb(wire_cmpr3_aeb),
.agb(wire_cmpr3_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[14:7]),
.datab(aligned_datab_w[14:7]));
defparam
cmpr3.lpm_pipeline = 1,
cmpr3.lpm_representation = "UNSIGNED",
cmpr3.lpm_width = 8,
cmpr3.lpm_type = "lpm_compare";
lpm_compare cmpr4
(
.aclr(aclr),
.aeb(wire_cmpr4_aeb),
.agb(wire_cmpr4_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[6:0]),
.datab(aligned_datab_w[6:0]));
defparam
cmpr4.lpm_pipeline = 1,
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 7,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
aeb = out_aeb_dffe3_wo,
ageb = out_ageb_dffe3_wo,
aleb = out_aleb_dffe3_wo,
aligned_dataa_sign_adjusted_dffe2_wi = aligned_dataa_sign_adjusted_w,
aligned_dataa_sign_adjusted_dffe2_wo = aligned_dataa_sign_adjusted_w_dffe2,
aligned_dataa_sign_adjusted_w = (aligned_dataa_sign_dffe1_wo & (~ input_dataa_zero_w)),
aligned_dataa_sign_dffe1_wi = aligned_dataa_sign_w,
aligned_dataa_sign_dffe1_wo = aligned_dataa_sign_dffe1,
aligned_dataa_sign_w = dataa[31],
aligned_dataa_w = {dataa[30:0]},
aligned_datab_sign_adjusted_dffe2_wi = aligned_datab_sign_adjusted_w,
aligned_datab_sign_adjusted_dffe2_wo = aligned_datab_sign_adjusted_w_dffe2,
aligned_datab_sign_adjusted_w = (aligned_datab_sign_dffe1_wo & (~ input_datab_zero_w)),
aligned_datab_sign_dffe1_wi = aligned_datab_sign_w,
aligned_datab_sign_dffe1_wo = aligned_datab_sign_dffe1,
aligned_datab_sign_w = datab[31],
aligned_datab_w = {datab[30:0]},
both_inputs_zero = (input_dataa_zero_w & input_datab_zero_w),
both_inputs_zero_dffe2_wi = both_inputs_zero,
both_inputs_zero_dffe2_wo = both_inputs_zero_dffe2,
clk_en = 1'b1,
exp_a_all_one_dffe1_wi = exp_a_all_one_w[7],
exp_a_all_one_dffe1_wo = exp_a_all_one_w_dffe1,
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_dffe1_wi = exp_a_not_zero_w[7],
exp_a_not_zero_dffe1_wo = exp_a_not_zero_w_dffe1,
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_aeb = {wire_cmpr4_aeb, wire_cmpr3_aeb, wire_cmpr2_aeb, wire_cmpr1_aeb},
exp_aeb_tmp_w = {(exp_aeb[3] & exp_aeb_tmp_w[2]), (exp_aeb[2] & exp_aeb_tmp_w[1]), (exp_aeb[1] & exp_aeb_tmp_w[0]), exp_aeb[0]},
exp_aeb_w = exp_aeb_tmp_w[3],
exp_aeb_w_dffe2_wi = exp_aeb_w,
exp_aeb_w_dffe2_wo = exp_aeb_w_dffe2,
exp_agb = {wire_cmpr4_agb, wire_cmpr3_agb, wire_cmpr2_agb, wire_cmpr1_agb},
exp_agb_tmp_w = {(exp_agb_tmp_w[2] | exp_eq_gt_grp[3]), (exp_agb_tmp_w[1] | exp_eq_gt_grp[2]), (exp_agb_tmp_w[0] | exp_eq_gt_grp[1]), exp_eq_gt_grp[0]},
exp_agb_w = exp_agb_tmp_w[3],
exp_agb_w_dffe2_wi = exp_agb_w,
exp_agb_w_dffe2_wo = exp_agb_w_dffe2,
exp_b_all_one_dffe1_wi = exp_b_all_one_w[7],
exp_b_all_one_dffe1_wo = exp_b_all_one_w_dffe1,
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_dffe1_wi = exp_b_not_zero_w[7],
exp_b_not_zero_dffe1_wo = exp_b_not_zero_w_dffe1,
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_eq_grp = {(exp_eq_grp[1] & exp_aeb[2]), (exp_eq_grp[0] & exp_aeb[1]), exp_aeb[0]},
exp_eq_gt_grp = {(exp_eq_grp[2] & exp_agb[3]), (exp_eq_grp[1] & exp_agb[2]), (exp_eq_grp[0] & exp_agb[1]), exp_agb[0]},
flip_outputs_dffe2_wi = flip_outputs_w,
flip_outputs_dffe2_wo = flip_outputs_dffe2,
flip_outputs_w = (aligned_dataa_sign_adjusted_w & aligned_datab_sign_adjusted_w),
input_dataa_nan_dffe2_wi = input_dataa_nan_w,
input_dataa_nan_dffe2_wo = input_dataa_nan_dffe2,
input_dataa_nan_w = (exp_a_all_one_dffe1_wo & man_a_not_zero_merge_w[1]),
input_dataa_zero_w = (~ exp_a_not_zero_dffe1_wo),
input_datab_nan_dffe2_wi = input_datab_nan_w,
input_datab_nan_dffe2_wo = input_datab_nan_dffe2,
input_datab_nan_w = (exp_b_all_one_dffe1_wo & man_b_not_zero_merge_w[1]),
input_datab_zero_w = (~ exp_b_not_zero_dffe1_wo),
man_a_not_zero_dffe1_wi = {man_a_not_zero_w[22], man_a_not_zero_w[11]},
man_a_not_zero_dffe1_wo = man_a_not_zero_w_dffe1,
man_a_not_zero_merge_w = {(man_a_not_zero_dffe1_wo[1] | man_a_not_zero_merge_w[0]), man_a_not_zero_dffe1_wo[0]},
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), dataa[12], (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_not_zero_dffe1_wi = {man_b_not_zero_w[22], man_b_not_zero_w[11]},
man_b_not_zero_dffe1_wo = man_b_not_zero_w_dffe1,
man_b_not_zero_merge_w = {(man_b_not_zero_dffe1_wo[1] | man_b_not_zero_merge_w[0]), man_b_not_zero_dffe1_wo[0]},
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), datab[12], (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
out_aeb_dffe3_wi = out_aeb_w,
out_aeb_dffe3_wo = out_aeb_w_dffe3,
out_aeb_w = ((((~ (aligned_dataa_sign_adjusted_dffe2_wo ^ aligned_datab_sign_adjusted_dffe2_wo)) & exp_aeb_w_dffe2_wo) | both_inputs_zero_dffe2_wo) & (~ out_unordered_w)),
out_agb_w = (((((~ aligned_dataa_sign_adjusted_dffe2_wo) & aligned_datab_sign_adjusted_dffe2_wo) | ((exp_agb_w_dffe2_wo & (~ aligned_dataa_sign_adjusted_dffe2_wo)) & (~ both_inputs_zero_dffe2_wo))) | ((flip_outputs_dffe2_wo & (~ exp_agb_w_dffe2_wo)) & (~ out_aeb_w))) & (~ out_unordered_w)),
out_ageb_dffe3_wi = out_ageb_w,
out_ageb_dffe3_wo = out_ageb_w_dffe3,
out_ageb_w = ((out_agb_w | out_aeb_w) & (~ out_unordered_w)),
out_alb_w = (((~ out_agb_w) & (~ out_aeb_w)) & (~ out_unordered_w)),
out_aleb_dffe3_wi = out_aleb_w,
out_aleb_dffe3_wo = out_aleb_w_dffe3,
out_aleb_w = ((out_alb_w | out_aeb_w) & (~ out_unordered_w)),
out_unordered_w = (input_dataa_nan_dffe2_wo | input_datab_nan_dffe2_wo);
endmodule //fp_compare_altfp_compare_orb
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fp_compare (
clock,
dataa,
datab,
aeb,
ageb,
aleb);
input clock;
input [31:0] dataa;
input [31:0] datab;
output aeb;
output ageb;
output aleb;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire aeb = sub_wire0;
wire ageb = sub_wire1;
wire aleb = sub_wire2;
fp_compare_altfp_compare_orb fp_compare_altfp_compare_orb_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.aeb (sub_wire0),
.ageb (sub_wire1),
.aleb (sub_wire2));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
// Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
// Retrieval info: USED_PORT: aleb 0 0 0 0 OUTPUT NODEFVAL "aleb"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
// Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
// Retrieval info: CONNECT: aleb 0 0 0 0 @aleb 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_compare.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_compare.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_compare.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_compare.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_compare_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fp_compare_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTP_4_V
`define SKY130_FD_SC_HS__DFRTP_4_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrtp_4 (
RESET_B,
CLK ,
D ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrtp_4 (
RESET_B,
CLK ,
D ,
Q
);
input RESET_B;
input CLK ;
input D ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTP_4_V
|
/*
* dat_i_arbiter - arbitrate data coming into the CPU
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module dat_i_arbiter(
// Clock
input wire clock_i,
// Output
output wire [7:0] D,
// Lower Rom module
input [7:0] l_rom,
input l_rom_e,
// Lower Rom module
input [7:0] u_rom,
input u_rom_e,
// Ram module
input [7:0] ram,
input ram_e,
// Extended Ram modules
input [7:0] eram,
input u_ram_e,
// Standard 8255 PIO
input [7:0] pio8255,
input pio8255_e,
// Printer IO
input [7:0] io,
input io_e,
// FDC IO
input [7:0] fdc,
input fdc_e
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
// Assignments ================================================================================
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
//always @(negedge clock_i)
assign D = (l_rom_e) ? l_rom :
(u_rom_e) ? u_rom :
(u_ram_e) ? eram :
(ram_e) ? ram :
(pio8255_e) ? pio8255 :
(io_e) ? io :
(fdc_e) ? fdc :
8'd255;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXBP_1_V
`define SKY130_FD_SC_HVL__DFXBP_1_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__dfxbp_1 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXBP_1_V
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
// A parallel input shift register clocked on falling edge
`default_nettype none
`timescale 10ns/1ns
// Main test module
module testbench;
reg clk;
reg ce;
reg rstn;
reg loaden;
reg unloaden;
wire empty;
wire full;
integer i;
wire [62:0] count;
reg [63:0] datain;
wire [63:0] dataout;
wire [5:0] itemsinfifo;
ptrfifo fifo(
.clk(clk),
.rstn(rstn),
.loaden(loaden),
.unloaden(unloaden),
.datain(datain),
.dataout(dataout),
.itemsinfifo(itemsinfifo)
);
defparam fifo.DEPTH = 6;
defparam fifo.WIDTH = 64;
initial begin
$dumpvars(0, testbench);
ce = 0;
clk = 0;
rstn = 0;
loaden = 0;
unloaden = 0;
datain = 0;
#10
ce = 1;
rstn = 1;
#10
// Clear fifo memory, check full
loaden = 1;
#640
loaden = 0;
# 10
unloaden = 1;
#640
unloaden = 0;
#10
// Load some values in the fifo
datain = 64'h55AA00FFDEADBEEF;
loaden = 1;
# 10
loaden = 0;
datain = 64'hDEADBEEF55AA00FF;
# 10
loaden = 1;
# 10
loaden = 0;
# 10
// Unload the values from the fifo
unloaden = 1;
# 10
unloaden = 0;
# 10
unloaden = 1;
# 10
unloaden = 0;
# 10
#100000 $finish;
end
always #5 clk = ~clk;
endmodule
|
// CPU.v
////////////////////////////////////////////////////////////////////////////////
// subset of MIPS instructions executing five stages pipeline CPU
////////////////////////////////////////////////////////////////////////////////
// Dimitrios Paraschas ([email protected])
////////////////////////////////////////////////////////////////////////////////
// inf.uth.gr
// ce232 Computer Organization and Design
////////////////////////////////////////////////////////////////////////////////
// lab 9
// implementation of a subset of MIPS instruction five stages pipeline CPU
////////////////////////////////////////////////////////////////////////////////
`include "constants.h"
`timescale 1ns/1ps
// modules
////////////////////////////////////////////////////////////////////////////////
module CPU #(
parameter INSTR_MEM_SIZE = 1024,
parameter DATA_MEM_SIZE = 4096
) (
input wire clock,
input wire reset
);
wire [31:0] pc_next;
wire [31:0] pc;
ProgramCounter ProgramCounter_0 (
.clock(clock),
.reset(reset),
.Stall(Stall),
.pc_next(pc_next),
.pc(pc)
);
wire [31:0] pc_plus_four;
PCPlus4 PCPlus4_0 (
.pc(pc),
.pc_plus_four(pc_plus_four)
);
wire [31:0] instruction;
InstructionMemory #(
.SIZE(INSTR_MEM_SIZE)
) InstructionMemory_0 (
.Address(pc),
.Instruction(instruction)
);
wire [31:0] ID_pc_plus_four;
wire [31:0] ID_instruction;
// IF/ID pipeline registers (1st)
IF_ID IF_ID_0 (
.clock(clock),
.WriteEnable(~Stall),
.Flush(0),
.pc_plus_four(pc_plus_four),
.ID_pc_plus_four(ID_pc_plus_four),
.instruction(instruction),
.ID_instruction(ID_instruction)
);
wire [5:0] opcode;
assign opcode = ID_instruction[31:26];
wire [4:0] rs;
assign rs = ID_instruction[25:21];
wire [4:0] rt;
assign rt = ID_instruction[20:16];
wire [4:0] rd;
assign rd = ID_instruction[15:11];
// NOTE
// currently not used
//wire [4:0] shamt;
//assign shamt = ID_instruction[10:6];
wire [5:0] funct;
assign funct = ID_instruction[5:0];
wire [15:0] immediate;
assign immediate = ID_instruction[15:0];
// NOTE
// currently not used
//wire [25:0] address;
//assign address = ID_instruction[25:0];
//wire PC_WriteEnable;
//wire IF_ID_WriteEnable;
//wire ControlStall;
wire Stall;
HazardDetection HazardDetection_0 (
.EX_MemRead(EX_MemRead),
.rs(rs),
.rt(rt),
.EX_rt(EX_rt),
//.PC_WriteEnable(PC_WriteEnable),
//.IF_ID_WriteEnable(IF_ID_WriteEnable),
//.ControlStall(ControlStall)
.Stall(Stall)
);
wire RegWrite;
wire RegDst;
wire MemRead;
wire MemWrite;
wire MemToReg;
wire Branch;
wire ALUSrc;
wire [1:0] ALUOp;
Control Control_0 (
.Opcode(opcode),
.RegWrite(RegWrite),
.RegDst(RegDst),
.MemRead(MemRead),
.MemWrite(MemWrite),
.MemToReg(MemToReg),
.Branch(Branch),
.ALUSrc(ALUSrc),
.ALUOp(ALUOp)
);
wire [8:0] BufferedControl;
mux2to1 #(
.WIDTH(9)
) MuxControlStall (
// TODO 1
// should we do something more complicated but readable here?
.inA( {RegWrite, RegDst, MemRead, MemWrite, MemToReg, Branch, ALUSrc,
ALUOp} ),
.inB(9'b0),
.select(Stall),
.out(BufferedControl)
);
wire [31:0] RegReadDataA;
wire [31:0] RegReadDataB;
wire [31:0] RegWriteData;
Registers Registers_0 (
.clock(clock),
.reset(reset),
.ReadAddressA(rs),
.ReadDataA(RegReadDataA),
.ReadAddressB(rt),
.ReadDataB(RegReadDataB),
.WriteEnable(WB_RegWrite),
.WriteAddress(WB_RegWriteAddress),
.WriteData(RegWriteData)
);
wire [31:0] extended;
SignExtender SignExtender_0 (
.immediate(immediate),
.extended(extended)
);
// TODO 3
// debug wire
wire [31:0] EX_instruction;
wire [31:0] EX_pc_plus_four;
wire [31:0] EX_RegReadDataA;
wire [31:0] EX_RegReadDataB;
wire [31:0] EX_extended;
wire EX_RegWrite;
wire EX_RegDst;
wire EX_MemRead;
wire EX_MemWrite;
wire EX_MemToReg;
wire EX_Branch;
wire EX_ALUSrc;
wire [1:0] EX_ALUOp;
wire [4:0] EX_rs;
wire [4:0] EX_rt;
wire [4:0] EX_rd;
// ID/EX pipeline registers (2nd)
ID_EX ID_EX_0 (
.clock(clock),
// TODO 3
// debug ports
.ID_instruction(ID_instruction),
.EX_instruction(EX_instruction),
.ID_pc_plus_four(ID_pc_plus_four),
.EX_pc_plus_four(EX_pc_plus_four),
.RegReadDataA(RegReadDataA),
.EX_RegReadDataA(EX_RegReadDataA),
.RegReadDataB(RegReadDataB),
.EX_RegReadDataB(EX_RegReadDataB),
.extended(extended),
.EX_extended(EX_extended),
// TODO 1
// we probably should, this isn't readable at all.
.RegWrite(BufferedControl[8]),
.EX_RegWrite(EX_RegWrite),
.RegDst(BufferedControl[7]),
.EX_RegDst(EX_RegDst),
.MemRead(BufferedControl[6]),
.EX_MemRead(EX_MemRead),
.MemWrite(BufferedControl[5]),
.EX_MemWrite(EX_MemWrite),
.MemToReg(BufferedControl[4]),
.EX_MemToReg(EX_MemToReg),
.Branch(BufferedControl[3]),
.EX_Branch(EX_Branch),
.ALUSrc(BufferedControl[2]),
.EX_ALUSrc(EX_ALUSrc),
.ALUOp(BufferedControl[1:0]),
.EX_ALUOp(EX_ALUOp),
.rs(rs),
.EX_rs(EX_rs),
.rt(rt),
.EX_rt(EX_rt),
.rd(rd),
.EX_rd(EX_rd)
);
wire [1:0] ForwardA;
wire [31:0] ALUArgA;
mux4to1 #(
.WIDTH(32)
) MuxForwardA (
.inA(EX_RegReadDataA),
.inB(RegWriteData),
.inC(MEM_ALUResult),
.inD(32'b0),
.select(ForwardA),
.out(ALUArgA)
);
wire [1:0] ForwardB;
wire [31:0] ForwardBOut;
mux4to1 #(
.WIDTH(32)
) MuxForwardB (
.inA(EX_RegReadDataB),
.inB(RegWriteData),
.inC(MEM_ALUResult),
.inD(32'b0),
.select(ForwardB),
.out(ForwardBOut)
);
wire [31:0] ALUArgB;
mux2to1 #(
.WIDTH(32)
) MuxALUSrc (
.inA(ForwardBOut),
.inB(EX_extended),
.select(EX_ALUSrc),
.out(ALUArgB)
);
wire [31:0] ALUResult;
wire Zero;
ALU #(
.WIDTH(32)
) ALU_0 (
.op(ALUCtrl),
.inA(ALUArgA),
.inB(ALUArgB),
.out(ALUResult),
.zero(Zero)
);
wire [5:0] EX_funct;
assign EX_funct = EX_extended[5:0];
wire [3:0] ALUCtrl;
ALUControl ALUControl_0 (
.Funct(EX_funct),
.ALUOp(EX_ALUOp),
.ALUCtrl(ALUCtrl)
);
wire [4:0] RegWriteAddress;
mux2to1 #(
.WIDTH(5)
) MuxRegDst (
.inA(EX_rt),
.inB(EX_rd),
.select(EX_RegDst),
.out(RegWriteAddress)
);
wire [31:0] branch_address;
BranchAdder BranchAdder_0 (
.pc_plus_four(EX_pc_plus_four),
.extended_times_four(EX_extended << 2),
.branch_address(branch_address)
);
wire bneOne;
assign bneOne = ID_instruction[26];
// TODO 3
// debug wire
wire [31:0] MEM_instruction;
wire [31:0] MEM_branch_address;
wire MEM_Zero;
wire [31:0] MEM_ALUResult;
wire [31:0] MEM_ForwardBOut;
wire [4:0] MEM_RegWriteAddress;
wire MEM_RegWrite;
wire MEM_MemRead;
wire MEM_MemWrite;
wire MEM_MemToReg;
wire MEM_Branch;
wire MEM_bneOne;
Forwarding Forwarding_0 (
.EX_rs(EX_rs),
.EX_rt(EX_rt),
.MEM_rd(MEM_rd),
.WB_rd(WB_rd),
.MEM_RegWrite(MEM_RegWrite),
.WB_RegWrite(WB_RegWrite),
.ForwardA(ForwardA),
.ForwardB(ForwardB)
);
// EX/MEM pipeline registers (3rd)
EX_MEM EX_MEM_0 (
.clock(clock),
// TODO 3
// debug ports
.EX_instruction(EX_instruction),
.MEM_instruction(MEM_instruction),
.branch_address(branch_address),
.MEM_branch_address(MEM_branch_address),
.Zero(Zero),
.MEM_Zero(MEM_Zero),
.ALUResult(ALUResult),
.MEM_ALUResult(MEM_ALUResult),
.ForwardBOut(ForwardBOut),
.MEM_ForwardBOut(MEM_ForwardBOut),
.RegWriteAddress(RegWriteAddress),
.MEM_RegWriteAddress(MEM_RegWriteAddress),
.EX_RegWrite(EX_RegWrite),
.MEM_RegWrite(MEM_RegWrite),
.EX_MemRead(EX_MemRead),
.MEM_MemRead(MEM_MemRead),
.EX_MemWrite(EX_MemWrite),
.MEM_MemWrite(MEM_MemWrite),
.EX_MemToReg(EX_MemToReg),
.MEM_MemToReg(MEM_MemToReg),
.EX_Branch(EX_Branch),
.MEM_Branch(MEM_Branch),
.bneOne(bneOne),
.MEM_bneOne(MEM_bneOne)
);
wire pc_chooser;
mux2to1 #(
.WIDTH(1)
) MuxBeqBne (
.inA(MEM_Zero),
.inB(~MEM_Zero),
.select(MEM_bneOne),
.out(pc_chooser)
);
mux2to1 #(
.WIDTH(32)
) MuxPCNext (
.inA(pc_plus_four),
.inB(MEM_branch_address),
.select(MEM_Branch && pc_chooser),
.out(pc_next)
);
wire [31:0] MemReadData;
Memory #(
.SIZE(DATA_MEM_SIZE)
) DataMemory_0 (
.clock(clock),
.Address(MEM_ALUResult),
.ReadEnable(MEM_MemRead),
.ReadData(MemReadData),
.WriteEnable(MEM_MemWrite),
.WriteData(MEM_ForwardBOut)
);
wire [4:0] MEM_rd;
assign MEM_rd = MEM_RegWriteAddress;
// TODO 3
// debug wire
wire [31:0] WB_instruction;
wire [31:0] WB_MemReadData;
wire [31:0] WB_ALUResult;
wire [4:0] WB_RegWriteAddress;
wire WB_RegWrite;
wire WB_MemToReg;
// MEM/WB pipeline registers (4th)
MEM_WB MEM_WB_0 (
.clock(clock),
// TODO 3
// debug ports
.MEM_instruction(MEM_instruction),
.WB_instruction(WB_instruction),
.MemReadData(MemReadData),
.WB_MemReadData(WB_MemReadData),
.MEM_ALUResult(MEM_ALUResult),
.WB_ALUResult(WB_ALUResult),
.MEM_RegWriteAddress(MEM_RegWriteAddress),
.WB_RegWriteAddress(WB_RegWriteAddress),
.MEM_RegWrite(MEM_RegWrite),
.WB_RegWrite(WB_RegWrite),
.MEM_MemToReg(MEM_MemToReg),
.WB_MemToReg(WB_MemToReg)
);
// NOTE
// maybe add an additional forwarding multiplexer, ForwardC
// see lecture 11, page 28
mux2to1 #(
.WIDTH(32)
) MuxMemtoReg (
.inA(WB_ALUResult),
.inB(WB_MemReadData),
.select(WB_MemToReg),
.out(RegWriteData)
);
wire [4:0] WB_rd;
assign WB_rd = WB_RegWriteAddress;
endmodule
////////////////////////////////////////////////////////////////////////////////
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
reg [2:0] xor3;
reg [1:0] xor2;
reg [0:0] xor1;
reg [2:0] ma, mb;
reg [9:0] mc;
reg [4:0] mr1;
reg [30:0] mr2;
reg [67:0] sh1;
reg [67:0] shq;
wire foo, bar; assign {foo,bar} = 2'b1_0;
// surefire lint_off STMINI
initial _ranit = 0;
wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1
: (xor2 == 2'b00) ? 5'h2
: (xor2 == 2'b01) ? 5'h3
: 5'h4);
wire ctrue = 1'b1 ? cond_check[1] : cond_check[0];
wire cfalse = 1'b0 ? cond_check[1] : cond_check[0];
wire cif = cond_check[2] ? cond_check[1] : cond_check[0];
wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0];
wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1};
wire zero = 1'b0;
wire one = 1'b1;
wire [5:0] rep6 = {6{one}};
// verilator lint_off WIDTH
localparam [3:0] bug764_p11 = 1'bx;
// verilator lint_on WIDTH
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
if (rep6 != 6'b111111) $stop;
if (!one) $stop;
if (~one) $stop;
if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop;
// verilator lint_off WIDTH
if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher than ?
// verilator lint_on WIDTH
// surefire lint_off SEQASS
xor1 = 1'b1;
xor2 = 2'b11;
xor3 = 3'b111;
// verilator lint_off WIDTH
if (1'b1 & | (!xor3)) $stop;
// verilator lint_on WIDTH
if ({1{xor1}} != 1'b1) $stop;
if ({4{xor1}} != 4'b1111) $stop;
if (!(~xor1) !== ~(!xor1)) $stop;
if ((^xor1) !== 1'b1) $stop;
if ((^xor2) !== 1'b0) $stop;
if ((^xor3) !== 1'b1) $stop;
if (~(^xor2) !== 1'b1) $stop;
if (~(^xor3) !== 1'b0) $stop;
if ((^~xor1) !== 1'b0) $stop;
if ((^~xor2) !== 1'b1) $stop;
if ((^~xor3) !== 1'b0) $stop;
if ((~^xor1) !== 1'b0) $stop;
if ((~^xor2) !== 1'b1) $stop;
if ((~^xor3) !== 1'b0) $stop;
xor1 = 1'b0;
xor2 = 2'b10;
xor3 = 3'b101;
if ((^xor1) !== 1'b0) $stop;
if ((^xor2) !== 1'b1) $stop;
if ((^xor3) !== 1'b0) $stop;
if (~(^xor2) !== 1'b0) $stop;
if (~(^xor3) !== 1'b1) $stop;
if ((^~xor1) !== 1'b1) $stop;
if ((^~xor2) !== 1'b0) $stop;
if ((^~xor3) !== 1'b1) $stop;
if ((~^xor1) !== 1'b1) $stop;
if ((~^xor2) !== 1'b0) $stop;
if ((~^xor3) !== 1'b1) $stop;
ma = 3'h3;
mb = 3'h4;
mc = 10'h5;
mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch
mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch
if (mr1 !== 5'd12) $stop;
if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch
sh1 = 68'hf_def1_9abc_5678_1234;
shq = sh1 >> 16;
if (shq !== 68'hf_def1_9abc_5678) $stop;
shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch
if (shq !== 68'h1_9abc_5678_1234_0000) $stop;
// surefire lint_on SEQASS
// Test display extraction widthing
$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
// bug736
//verilator lint_off WIDTH
if ((~| 4'b0000) != 4'b0001) $stop;
if ((~| 4'b0010) != 4'b0000) $stop;
if ((~& 4'b1111) != 4'b0000) $stop;
if ((~& 4'b1101) != 4'b0001) $stop;
//verilator lint_on WIDTH
// bug764
//verilator lint_off WIDTH
// X does not sign extend
if (bug764_p11 !== 4'b000x) $stop;
if (~& bug764_p11 !== 1'b1) $stop;
//verilator lint_on WIDTH
// However IEEE 2017 5.7.1 says for constants that smaller-sizes do extend
if (4'bx !== 4'bxxxx) $stop;
if (4'bz !== 4'bzzzz) $stop;
if (4'b1 !== 4'b0001) $stop;
if ((0 -> 0) != 1'b1) $stop;
if ((0 -> 1) != 1'b1) $stop;
if ((1 -> 0) != 1'b0) $stop;
if ((1 -> 1) != 1'b1) $stop;
if ((0 <-> 0) != 1'b1) $stop;
if ((0 <-> 1) != 1'b0) $stop;
if ((1 <-> 0) != 1'b0) $stop;
if ((1 <-> 1) != 1'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
reg [63:0] m_data_pipe2_r;
reg [31:0] m_corr_data_w0, m_corr_data_w1;
reg [7:0] m_corr_data_b8;
initial begin
m_data_pipe2_r = 64'h1234_5678_9abc_def0;
{m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0]
m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0]
m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16]
m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8]
m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4]
m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0]
};
if (m_corr_data_w0 != 32'haf36de00) $stop;
if (m_corr_data_w1 != 32'h1a2b3c4c) $stop;
if (m_corr_data_b8 != 8'h12) $stop;
end
endmodule
|
// simulate fpga top-level with external dram, rom, z80
// (c) 2010-2016 NedoPC
`include "../include/tune.v"
//`define ZLOG 1
`define HALF_CLK_PERIOD (17.8)
`define ZCLK_DELAY (9.5)
// toshibo
//`define Z80_DELAY_DOWN (17.0)
//`define Z80_DELAY_UP (22.0)
// z0840008
`define Z80_DELAY_DOWN 34
`define Z80_DELAY_UP 30
module tb;
reg fclk;
wire clkz_out,clkz_in;
reg iorq_n,mreq_n,rd_n,wr_n; // has some delays relative to z*_n (below)
reg m1_n,rfsh_n; //
wire res; //
tri1 ziorq_n,zmreq_n,zrd_n,zwr_n,zm1_n,zrfsh_n; // connected to Z80
tri1 int_n,wait_n,nmi_n;
wire zint_n,zwait_n,znmi_n;
wire [15:0] #((`Z80_DELAY_DOWN+`Z80_DELAY_UP)/2) za;
wire [ 7:0] #((`Z80_DELAY_DOWN+`Z80_DELAY_UP)/2) zd;
tri1 [ 7:0] zd_dut_to_z80;
reg [15:0] reset_pc = 16'h0000;
reg [15:0] reset_sp = 16'hFFFF;
wire csrom, romoe_n, romwe_n;
wire rompg0_n, dos_n;
wire rompg2,rompg3,rompg4;
wire [15:0] rd;
wire [9:0] ra;
wire rwe_n,rucas_n,rlcas_n,rras0_n,rras1_n;
tri1 [15:0] ide_d;
wire hsync,vsync;
wire [1:0] red,grn,blu;
// sdcard
wire sdcs_n, sddo, sddi, sdclk;
// avr
wire spick, spidi, spido, spics_n;
assign zwait_n = (wait_n==1'b0) ? 1'b0 : 1'b1;
assign znmi_n = (nmi_n==1'b0) ? 1'b0 : 1'b1;
assign zint_n = (int_n==1'b0) ? 1'b0 : 1'b1;
initial
begin
fclk = 1'b0;
forever #`HALF_CLK_PERIOD fclk = ~fclk;
end
assign #`ZCLK_DELAY clkz_in = ~clkz_out;
// set 48k contention and 3.5 MHz
initial
begin
force tb.DUT.zclock.modes_raster = 2'b10;
force tb.DUT.zclock.turbo = 2'b00;
end
top DUT( .fclk(fclk),
.clkz_out(clkz_out),
.clkz_in(clkz_in),
// z80
.iorq_n(iorq_n),
.mreq_n(mreq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.m1_n(m1_n),
.rfsh_n(rfsh_n),
.int_n(int_n),
.nmi_n(nmi_n),
.wait_n(wait_n),
.res(res),
//
.d(zd),
.a(za),
// ROM
.csrom(csrom),
.romoe_n(romoe_n),
.romwe_n(romwe_n),
.rompg0_n(rompg0_n),
.dos_n(dos_n),
.rompg2(rompg2),
.rompg3(rompg3),
.rompg4(rompg4),
// DRAM
.rd(rd),
.ra(ra),
.rwe_n(rwe_n),
.rucas_n(rucas_n),
.rlcas_n(rlcas_n),
.rras0_n(rras0_n),
.rras1_n(rras1_n),
// ZX-bus
.iorqge1(1'b0),
.iorqge2(1'b0),
// IDE
.ide_d(ide_d),
.ide_rdy(1'b1),
// VG93
.step(1'b0),
.vg_sl(1'b0),
.vg_sr(1'b0),
.vg_tr43(1'b0),
.rdat_b_n(1'b1),
.vg_wf_de(1'b0),
.vg_drq(1'b1),
.vg_irq(1'b1),
.vg_wd(1'b0),
// SDcard SPI
.sddi(sddi),
.sddo(sddo),
.sdcs_n(sdcs_n),
.sdclk(sdclk),
// ATmega SPI
.spics_n(spics_n),
.spick(spick),
.spido(spido),
.spidi(spidi),
.vhsync(hsync),
.vvsync(vsync),
.vred(red),
.vgrn(grn),
.vblu(blu)
);
// assign zd_dut_to_z80 = tb.DUT.ena_ram ? tb.DUT.dout_ram : ( tb.DUT.ena_ports ? tb.DUT.dout_ports : ( tb.DUT.drive_ff ? 8'hFF : 8'bZZZZZZZZ ) );
assign zd_dut_to_z80 = tb.DUT.d_ena ? tb.DUT.d_pre_out : 8'bZZZZ_ZZZZ;
wire zrst_n = ~res;
T80a z80( .RESET_n(zrst_n),
.CLK_n(clkz_in),
.WAIT_n(zwait_n),
.INT_n(zint_n),
.NMI_n(znmi_n),
.M1_n(zm1_n),
.RFSH_n(zrfsh_n),
.MREQ_n(zmreq_n),
.IORQ_n(ziorq_n),
.RD_n(zrd_n),
.WR_n(zwr_n),
.BUSRQ_n(1'b1),
.A(za),
.D_I(zd_dut_to_z80),
.D_O(zd),
.ResetPC(reset_pc),
.ResetSP(reset_sp)
);
// now make delayed versions of signals
//
reg mreq_wr_n;
wire iorq_wr_n, full_wr_n;
//
// first, assure there is no X's at the start
//
initial
begin
m1_n = 1'b1;
rfsh_n = 1'b1;
mreq_n = 1'b1;
iorq_n = 1'b1;
rd_n = 1'b1;
wr_n = 1'b1;
mreq_wr_n = 1'b1;
end
//
always @(zm1_n)
if( zm1_n )
m1_n <= #`Z80_DELAY_UP zm1_n;
else
m1_n <= #`Z80_DELAY_DOWN zm1_n;
//
always @(zrfsh_n)
if( zrfsh_n )
rfsh_n <= #`Z80_DELAY_UP zrfsh_n;
else
rfsh_n <= #`Z80_DELAY_DOWN zrfsh_n;
//
always @(zmreq_n)
if( zmreq_n )
mreq_n <= #`Z80_DELAY_UP zmreq_n;
else
mreq_n <= #`Z80_DELAY_DOWN zmreq_n;
//
always @(ziorq_n)
if( ziorq_n )
iorq_n <= #`Z80_DELAY_UP ziorq_n;
else
iorq_n <= #`Z80_DELAY_DOWN ziorq_n;
//
always @(zrd_n)
if( zrd_n )
rd_n <= #`Z80_DELAY_UP zrd_n;
else
rd_n <= #`Z80_DELAY_DOWN zrd_n;
//
//
// special handling for broken T80 WR_n
//
always @(negedge clkz_in)
mreq_wr_n <= zwr_n;
//
assign iorq_wr_n = ziorq_n | (~zrd_n) | (~zm1_n);
//
assign full_wr_n = mreq_wr_n & iorq_wr_n;
//
// this way glitches won't affect state of wr_n
always @(full_wr_n)
if( !full_wr_n )
#`Z80_DELAY_DOWN wr_n <= full_wr_n;
else
#`Z80_DELAY_UP wr_n <= full_wr_n;
// ROM model
rom romko(
.addr( {rompg4,rompg3,rompg2,dos_n, (~rompg0_n), za[13:0]} ),
.data(zd_dut_to_z80),
.ce_n( romoe_n | (~csrom) )
);
// DRAM model
drammem dramko1(
.ma(ra),
.d(rd),
.ras_n(rras0_n),
.ucas_n(rucas_n),
.lcas_n(rlcas_n),
.we_n(rwe_n)
);
//
drammem dramko2(
.ma(ra),
.d(rd),
.ras_n(rras1_n),
.ucas_n(rucas_n),
.lcas_n(rlcas_n),
.we_n(rwe_n)
);
defparam dramko1._verbose_ = 0;
defparam dramko2._verbose_ = 0;
defparam dramko1._init_ = 0;
defparam dramko2._init_ = 0;
`ifndef GATE
// trace rom page
wire rma14,rma15;
assign rma14 = DUT.page[0][0];
assign rma15 = DUT.page[0][1];
always @(rma14 or rma15)
begin
// $display("at time %t us",$time/1000000);
// case( {rma15, rma14} )
// 2'b00: $display("BASIC 48");
// 2'b01: $display("TR-DOS");
// 2'b10: $display("BASIC 128");
// 2'b11: $display("GLUKROM");
// default: $display("unknown");
// endcase
// $display("");
end
// trace ram page
wire [5:0] rpag;
assign rpag=DUT.page[3][5:0];
always @(rpag)
begin
// $display("at time %t us",$time/1000000);
// $display("RAM page is %d",rpag);
// $display("");
end
// key presses/nmi/whatsoever
initial
begin
#1;
tb.DUT.zkbdmus.kbd = 40'd0;
tb.DUT.zkbdmus.kbd[36] = 1'b1;
@(negedge int_n);
@(negedge int_n);
tb.DUT.zkbdmus.kbd[36] = 1'b0;
end
`endif
`ifdef ZLOG
reg [ 7:0] old_opcode;
reg [15:0] old_opcode_addr;
wire [7:0] zdd = zd_dut_to_z80;
reg was_m1;
always @(zm1_n)
if( zm1_n )
was_m1 <= 1'b0;
else
was_m1 = 1'b1;
always @(posedge (zmreq_n | zrd_n | zm1_n | (~zrfsh_n)) )
if( was_m1 )
begin
if( (zdd!==old_opcode) || (za!==old_opcode_addr) )
begin
if( tb.DUT.z80mem.romnram )
// $display("Z80OPROM: addr %x, opcode %x, time %t",za,zdd,$time);
$display("Z80OPROM: addr %x, opcode %x",za,zdd);
else
// $display("Z80OPRAM: addr %x, opcode %x, time %t",za,zdd,$time);
$display("Z80OPRAM: addr %x, opcode %x",za,zdd);
end
old_opcode = zdd;
old_opcode_addr = za;
end
always @(posedge (zmreq_n | zrd_n | (~zm1_n) | (~zrfsh_n)) )
if( !was_m1 )
begin
if( tb.DUT.z80mem.romnram )
// $display("Z80RDROM: addr %x, rddata %x, time %t",za,zdd,$time);
$display("Z80RDROM: addr %x, rddata %x",za,zdd);
else
// $display("Z80RDRAM: addr %x, rddata %x, time %t",za,zdd,$time);
$display("Z80RDRAM: addr %x, rddata %x",za,zdd);
end
always @(posedge (zmreq_n | zwr_n | (~zm1_n) | (~zrfsh_n)) )
begin
if( tb.DUT.z80mem.romnram )
// $display("Z80WRROM: addr %x, wrdata %x, time %t",za,zd,$time);
$display("Z80WRROM: addr %x, wrdata %x",za,zd);
else
// $display("Z80WRRAM: addr %x, wrdata %x, time %t",za,zd,$time);
$display("Z80WRRAM: addr %x, wrdata %x",za,zd);
end
`endif
// port #FE monitor
wire fe_write;
assign fe_write = (za[7:0]==8'hFE) && !wr_n && !iorq_n;
always @(negedge fe_write)
$display("port #FE monitor: border is %d at %t",zd[2:0],$time());
always @(negedge nmi_n)
$display("nmi monitor: negative edge at %t",$time());
`ifndef NO_PIXER
// picture out
pixer pixer
(
.clk(fclk),
.vsync(vsync),
.hsync(hsync),
.red(red),
.grn(grn),
.blu(blu)
);
`endif
/*
// time ticks
always
begin : timemark
integer ms;
ms = ($time/1000000);
// $display("timemark %d ms",ms);
#10000000.0; // 1 ms
end
*/
// init dram
`ifndef NMITEST2
initial
begin : init_dram
integer i;
integer page;
integer offset;
reg [7:0] trd [0:655359];
integer fd;
integer size;
for(i=0;i<4*1024*1024;i=i+1)
begin
put_byte(i,(i%257));
end
// load TRD
fd = $fopen("boot.trd","rb");
size=$fread(trd,fd);
if( size>655360 || size<=0 )
begin
$display("Couldn't load or wrong boot.trd!\n");
$stop;
end
$fclose(fd);
// copy TRD to RAM
page = 32'h0F4;
offset = 0;
for(i=0;i<size;i=i+1)
begin
put_byte( .addr(page*16384+offset), .data(trd[i]) );
offset = offset + 1;
if( offset>=16384 )
begin
offset = 0;
page = page - 1;
end
end
$display("boot.trd loaded!\n");
end
`endif
// cmos simulation
wire [7:0] cmos_addr;
wire [7:0] cmos_read;
wire [7:0] cmos_write;
wire cmos_rnw;
wire cmos_req;
cmosemu cmosemu
(
.zclk(clkz_in),
.cmos_req (cmos_req ),
.cmos_addr (cmos_addr ),
.cmos_rnw (cmos_rnw ),
.cmos_read (cmos_read ),
.cmos_write(cmos_write)
);
assign cmos_req = tb.DUT.wait_start_gluclock;
assign cmos_rnw = tb.DUT.wait_rnw;
assign cmos_addr = tb.DUT.gluclock_addr;
assign cmos_write = tb.DUT.wait_write;
always @*
force tb.DUT.wait_read = cmos_read;
/*
`ifdef SPITEST
// spitest printing module
// does not hurt at any time (yet), so attached forever
spitest_print spitest_print(
.sdclk (sdclk ),
.sddi (sddi ),
.sddo (sddo ),
.sdcs_n(sdcs_n)
);
// spitest AVR imitator
spitest_avr spitest_avr(
.spick (spick ),
.spics_n(spics_n),
.spido (spido ),
.spidi (spidi )
);
`else
assign sddi = 1'b1;
assign spics_n = 1'b1;
assign spick = 1'b0;
assign spido = 1'b1;
`endif
*/
sdgovnoemu sdgovnoemu
(
.cs_n(sdcs_n),
.clk(sdclk),
.doo(sddo),
.di(sddi)
);
// set up breakpoint
/*
wire bpt = za===16'h3FEC && zmreq_n===1'b0 && zrd_n===1'b0 && zm1_n===1'b0;
initial
begin
#(1_800_000_000);
@(posedge fclk);
forever
begin
@(posedge bpt);
$display("Stop at breakpoint");
$stop;
end
end
*/
wire [15:0] #(0.1) dza;
wire [ 7:0] #(0.1) dzw;
wire [ 7:0] #(0.1) dzr;
typedef enum {FETCH,MRD,MWR,IORD,IOWR,IACK} cycle_t;
cycle_t curr_cycle;
cycle_t cycles[0:3];
logic [15:0] addrs[0:3];
logic [ 7:0] wdata[0:3];
logic [ 7:0] rdata[0:3];
wire is_fetch, is_mrd, is_mwr, is_iord, is_iowr, is_iack;
wire is_any;
assign dza = za;
assign dzw = zd;
assign dzr = zd_dut_to_z80;
assign is_fetch = zm1_n===1'b0 && zmreq_n===1'b0 && zrd_n===1'b0;
assign is_mrd = zm1_n===1'b1 && zmreq_n===1'b0 && zrd_n===1'b0;
assign is_mwr = zmreq_n===1'b0 && zwr_n===1'b0;
assign is_iord = ziorq_n===1'b0 && zrd_n===1'b0;
assign is_iowr = ziorq_n===1'b0 && zwr_n===1'b0;
assign is_iack = zm1_n===1'b0 && ziorq_n===1'b0;
assign is_any = is_fetch || is_mrd || is_mwr || is_iord || is_iowr || is_iack;
always @(negedge is_any)
begin : remember
int i;
for(i=1;i<4;i++)
begin
addrs [i] <= addrs [i-1];
cycles[i] <= cycles[i-1];
wdata [i] <= wdata [i-1];
rdata [i] <= rdata [i-1];
end
addrs[0] <= dza;
cycles[0] <= curr_cycle;
wdata[0] <= dzw;
rdata[0] <= dzr;
end
always @(posedge is_any)
if( is_fetch ) curr_cycle <= FETCH;
else if( is_mrd ) curr_cycle <= MRD;
else if( is_mwr ) curr_cycle <= MWR;
else if( is_iord ) curr_cycle <= IORD;
else if( is_iowr ) curr_cycle <= IOWR;
else if( is_iack ) curr_cycle <= IACK;
else
begin
$display("Spurious cycle detect!");
$stop;
end
always @(negedge is_any)
begin
if( curr_cycle==MWR )
begin
$display("MEM WRITE: wraddr=%04x, wrdata=%02x, time=%t",dza,dzw,$time());
end
end
wire paper = tb.DUT.video_top.hpix & tb.DUT.video_top.vpix;
always @(paper)
begin
if( paper )
$display("paper ON!, time=%t",$time());
else
$display("paper Off, time=%t",$time());
end
// timestamps
always
begin
$display("Running for %t ms",$time()/1000000000.0);
#1000000.0;
end
task put_byte;
input [21:0] addr;
input [ 7:0] data;
reg [19:0] arraddr;
begin
arraddr = { addr[21:12], addr[11:2] };
case( addr[1:0] ) // chipsel, bytesel
2'b00: tb.dramko1.array[arraddr][15:8] = data;
2'b01: tb.dramko1.array[arraddr][ 7:0] = data;
2'b10: tb.dramko2.array[arraddr][15:8] = data;
2'b11: tb.dramko2.array[arraddr][ 7:0] = data;
endcase
end
endtask
task put_byte_48k
(
input [15:0] addr,
input [ 7:0] data
);
case( addr[15:14] )
2'b01: put_byte(addr-16'h4000 + 22'h14000,data);
2'b10: put_byte(addr-16'h8000 + 22'h08000,data);
2'b11: put_byte(addr-16'hc000 + 22'h00000,data);
endcase
endtask
endmodule
|
///////////////////////////////////////////////////////////////////////
//// ////
//// Generic Double-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common double-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// double-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Author(s): ////
//// - Michael Unneback, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// New
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_dpram
(
// Generic synchronous double-port RAM interface
clk_a, ce_a, addr_a, do_a,
clk_b, ce_b, we_b, addr_b, di_b
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
//
// Generic synchronous double-port RAM interface
//
input clk_a; // Clock
input ce_a; // Chip enable input
input [aw-1:0] addr_a; // address bus inputs
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input ce_b; // Chip enable input
input we_b; // Write enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
//
// Internal wires and registers
//
//
// Generic double-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; // RAM content
reg [aw-1:0] addr_a_reg; // RAM address registered
integer k;
initial begin
for(k = 0; k < (1 << aw); k = k + 1)
begin
mem[k] = 0;
end
end
// Function to access GPRs (for use by Verilator). No need to hide this one
// from the simulator, since it has an input (as required by IEEE 1364-2001).
function [31:0] get_gpr;
// verilator public
input [aw-1:0] gpr_no;
get_gpr = mem[gpr_no];
endfunction // get_gpr
function [31:0] set_gpr;
// verilator public
input [aw-1:0] gpr_no;
input [dw-1:0] value;
begin
mem[gpr_no] = value;
set_gpr = 0;
end
endfunction // get_gpr
//
// Data output drivers
//
//assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
assign do_a = mem[addr_a_reg];
//
// RAM read
//
always @(posedge clk_a)
if (ce_a)
addr_a_reg <= addr_a;
//
// RAM write
//
always @(posedge clk_b)
if (ce_b & we_b)
mem[addr_b] <= di_b;
endmodule // or1200_dpram
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
// Date : Fri Sep 09 11:35:14 2016
// Host : RDS1 running 64-bit major release (build 9200)
// Command : write_verilog -mode funcsim -nolib -force -file
// C:/Users/jsequeira/Proyectos/Add_Sub/Add_Sub_FPGA_Viv/Dry_runs.sim/sim_1/synth/func/Testbench_FPU_Add_Subt_func_synth.v
// Design : FPU_Add_Subtract_Function
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* SWR = "26" *)
module Add_Subt
(clk,
rst,
load_i,
Add_Sub_op_i,
Data_A_i,
PreData_B_i,
Data_Result_o,
FSM_C_o);
input clk;
input rst;
input load_i;
input Add_Sub_op_i;
input [25:0]Data_A_i;
input [25:0]PreData_B_i;
output [25:0]Data_Result_o;
output FSM_C_o;
wire Add_Sub_op_i;
wire [25:0]Data_A_i;
wire [25:0]Data_Result_o;
wire FSM_C_o;
wire [25:0]PreData_B_i;
wire [26:0]S_to_D;
wire clk;
wire load_i;
wire rst;
(* W = "26" *)
RegisterAdd__parameterized8 Add_Subt_Result
(.D(S_to_D[25:0]),
.Q(Data_Result_o),
.clk(clk),
.load(load_i),
.rst(rst));
(* W = "1" *)
RegisterAdd Add_overflow_Result
(.D(S_to_D[26]),
.Q(FSM_C_o),
.clk(clk),
.load(load_i),
.rst(rst));
(* W = "26" *)
add_sub_carry_out__parameterized0 Sgf_AS
(.Data_A(Data_A_i),
.Data_B(PreData_B_i),
.Data_S(S_to_D),
.op_mode(Add_Sub_op_i));
endmodule
(* EWR = "5" *) (* SWR = "26" *)
module Barrel_Shifter
(clk,
rst,
load_i,
Shift_Value_i,
Shift_Data_i,
Left_Right_i,
Bit_Shift_i,
N_mant_o);
input clk;
input rst;
input load_i;
input [4:0]Shift_Value_i;
input [25:0]Shift_Data_i;
input Left_Right_i;
input Bit_Shift_i;
output [25:0]N_mant_o;
wire Bit_Shift_i;
wire [25:0]Data_Reg;
wire Left_Right_i;
wire [25:0]N_mant_o;
wire [25:0]Shift_Data_i;
wire [4:0]Shift_Value_i;
wire clk;
wire load_i;
wire rst;
(* EWR = "5" *)
(* SWR = "26" *)
Mux_Array Mux_Array
(.Data_i(Shift_Data_i),
.Data_o(Data_Reg),
.FSM_left_right_i(Left_Right_i),
.Shift_Value_i(Shift_Value_i),
.bit_shift_i(Bit_Shift_i),
.clk(clk),
.load_i(1'b0),
.rst(rst));
(* W = "26" *)
RegisterAdd__parameterized7 Output_Reg
(.D(Data_Reg),
.Q(N_mant_o),
.clk(clk),
.load(load_i),
.rst(rst));
endmodule
(* W = "31" *)
module Comparator
(Data_X_i,
Data_Y_i,
gtXY_o,
eqXY_o);
input [30:0]Data_X_i;
input [30:0]Data_Y_i;
output gtXY_o;
output eqXY_o;
wire [30:0]Data_X_i;
wire [30:0]Data_Y_i;
wire eqXY_o;
wire eqXY_o_INST_0_i_10_n_0;
wire eqXY_o_INST_0_i_11_n_0;
wire eqXY_o_INST_0_i_12_n_0;
wire eqXY_o_INST_0_i_13_n_0;
wire eqXY_o_INST_0_i_1_n_0;
wire eqXY_o_INST_0_i_1_n_1;
wire eqXY_o_INST_0_i_1_n_2;
wire eqXY_o_INST_0_i_1_n_3;
wire eqXY_o_INST_0_i_2_n_0;
wire eqXY_o_INST_0_i_3_n_0;
wire eqXY_o_INST_0_i_4_n_0;
wire eqXY_o_INST_0_i_5_n_0;
wire eqXY_o_INST_0_i_5_n_1;
wire eqXY_o_INST_0_i_5_n_2;
wire eqXY_o_INST_0_i_5_n_3;
wire eqXY_o_INST_0_i_6_n_0;
wire eqXY_o_INST_0_i_7_n_0;
wire eqXY_o_INST_0_i_8_n_0;
wire eqXY_o_INST_0_i_9_n_0;
wire eqXY_o_INST_0_n_2;
wire eqXY_o_INST_0_n_3;
wire gtXY_o;
wire gtXY_o_INST_0_i_10_n_0;
wire gtXY_o_INST_0_i_10_n_1;
wire gtXY_o_INST_0_i_10_n_2;
wire gtXY_o_INST_0_i_10_n_3;
wire gtXY_o_INST_0_i_11_n_0;
wire gtXY_o_INST_0_i_12_n_0;
wire gtXY_o_INST_0_i_13_n_0;
wire gtXY_o_INST_0_i_14_n_0;
wire gtXY_o_INST_0_i_15_n_0;
wire gtXY_o_INST_0_i_16_n_0;
wire gtXY_o_INST_0_i_17_n_0;
wire gtXY_o_INST_0_i_18_n_0;
wire gtXY_o_INST_0_i_19_n_0;
wire gtXY_o_INST_0_i_19_n_1;
wire gtXY_o_INST_0_i_19_n_2;
wire gtXY_o_INST_0_i_19_n_3;
wire gtXY_o_INST_0_i_1_n_0;
wire gtXY_o_INST_0_i_1_n_1;
wire gtXY_o_INST_0_i_1_n_2;
wire gtXY_o_INST_0_i_1_n_3;
wire gtXY_o_INST_0_i_20_n_0;
wire gtXY_o_INST_0_i_21_n_0;
wire gtXY_o_INST_0_i_22_n_0;
wire gtXY_o_INST_0_i_23_n_0;
wire gtXY_o_INST_0_i_24_n_0;
wire gtXY_o_INST_0_i_25_n_0;
wire gtXY_o_INST_0_i_26_n_0;
wire gtXY_o_INST_0_i_27_n_0;
wire gtXY_o_INST_0_i_28_n_0;
wire gtXY_o_INST_0_i_29_n_0;
wire gtXY_o_INST_0_i_2_n_0;
wire gtXY_o_INST_0_i_30_n_0;
wire gtXY_o_INST_0_i_31_n_0;
wire gtXY_o_INST_0_i_32_n_0;
wire gtXY_o_INST_0_i_33_n_0;
wire gtXY_o_INST_0_i_34_n_0;
wire gtXY_o_INST_0_i_35_n_0;
wire gtXY_o_INST_0_i_3_n_0;
wire gtXY_o_INST_0_i_4_n_0;
wire gtXY_o_INST_0_i_5_n_0;
wire gtXY_o_INST_0_i_6_n_0;
wire gtXY_o_INST_0_i_7_n_0;
wire gtXY_o_INST_0_i_8_n_0;
wire gtXY_o_INST_0_i_9_n_0;
wire gtXY_o_INST_0_n_1;
wire gtXY_o_INST_0_n_2;
wire gtXY_o_INST_0_n_3;
wire [3:3]NLW_eqXY_o_INST_0_CO_UNCONNECTED;
wire [3:0]NLW_eqXY_o_INST_0_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_INST_0_i_1_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_INST_0_i_5_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_INST_0_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_INST_0_i_1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_INST_0_i_10_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_INST_0_i_19_O_UNCONNECTED;
CARRY4 eqXY_o_INST_0
(.CI(eqXY_o_INST_0_i_1_n_0),
.CO({NLW_eqXY_o_INST_0_CO_UNCONNECTED[3],eqXY_o,eqXY_o_INST_0_n_2,eqXY_o_INST_0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_INST_0_O_UNCONNECTED[3:0]),
.S({1'b0,eqXY_o_INST_0_i_2_n_0,eqXY_o_INST_0_i_3_n_0,eqXY_o_INST_0_i_4_n_0}));
CARRY4 eqXY_o_INST_0_i_1
(.CI(eqXY_o_INST_0_i_5_n_0),
.CO({eqXY_o_INST_0_i_1_n_0,eqXY_o_INST_0_i_1_n_1,eqXY_o_INST_0_i_1_n_2,eqXY_o_INST_0_i_1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_INST_0_i_1_O_UNCONNECTED[3:0]),
.S({eqXY_o_INST_0_i_6_n_0,eqXY_o_INST_0_i_7_n_0,eqXY_o_INST_0_i_8_n_0,eqXY_o_INST_0_i_9_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_10
(.I0(Data_X_i[9]),
.I1(Data_Y_i[9]),
.I2(Data_Y_i[11]),
.I3(Data_X_i[11]),
.I4(Data_Y_i[10]),
.I5(Data_X_i[10]),
.O(eqXY_o_INST_0_i_10_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_11
(.I0(Data_X_i[6]),
.I1(Data_Y_i[6]),
.I2(Data_Y_i[8]),
.I3(Data_X_i[8]),
.I4(Data_Y_i[7]),
.I5(Data_X_i[7]),
.O(eqXY_o_INST_0_i_11_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_12
(.I0(Data_X_i[3]),
.I1(Data_Y_i[3]),
.I2(Data_Y_i[5]),
.I3(Data_X_i[5]),
.I4(Data_Y_i[4]),
.I5(Data_X_i[4]),
.O(eqXY_o_INST_0_i_12_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_13
(.I0(Data_X_i[0]),
.I1(Data_Y_i[0]),
.I2(Data_Y_i[2]),
.I3(Data_X_i[2]),
.I4(Data_Y_i[1]),
.I5(Data_X_i[1]),
.O(eqXY_o_INST_0_i_13_n_0));
LUT2 #(
.INIT(4'h9))
eqXY_o_INST_0_i_2
(.I0(Data_Y_i[30]),
.I1(Data_X_i[30]),
.O(eqXY_o_INST_0_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_3
(.I0(Data_X_i[27]),
.I1(Data_Y_i[27]),
.I2(Data_Y_i[29]),
.I3(Data_X_i[29]),
.I4(Data_Y_i[28]),
.I5(Data_X_i[28]),
.O(eqXY_o_INST_0_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_4
(.I0(Data_X_i[24]),
.I1(Data_Y_i[24]),
.I2(Data_Y_i[26]),
.I3(Data_X_i[26]),
.I4(Data_Y_i[25]),
.I5(Data_X_i[25]),
.O(eqXY_o_INST_0_i_4_n_0));
CARRY4 eqXY_o_INST_0_i_5
(.CI(1'b0),
.CO({eqXY_o_INST_0_i_5_n_0,eqXY_o_INST_0_i_5_n_1,eqXY_o_INST_0_i_5_n_2,eqXY_o_INST_0_i_5_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_INST_0_i_5_O_UNCONNECTED[3:0]),
.S({eqXY_o_INST_0_i_10_n_0,eqXY_o_INST_0_i_11_n_0,eqXY_o_INST_0_i_12_n_0,eqXY_o_INST_0_i_13_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_6
(.I0(Data_X_i[21]),
.I1(Data_Y_i[21]),
.I2(Data_Y_i[23]),
.I3(Data_X_i[23]),
.I4(Data_Y_i[22]),
.I5(Data_X_i[22]),
.O(eqXY_o_INST_0_i_6_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_7
(.I0(Data_X_i[18]),
.I1(Data_Y_i[18]),
.I2(Data_Y_i[20]),
.I3(Data_X_i[20]),
.I4(Data_Y_i[19]),
.I5(Data_X_i[19]),
.O(eqXY_o_INST_0_i_7_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_8
(.I0(Data_X_i[15]),
.I1(Data_Y_i[15]),
.I2(Data_Y_i[17]),
.I3(Data_X_i[17]),
.I4(Data_Y_i[16]),
.I5(Data_X_i[16]),
.O(eqXY_o_INST_0_i_8_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_INST_0_i_9
(.I0(Data_X_i[12]),
.I1(Data_Y_i[12]),
.I2(Data_Y_i[14]),
.I3(Data_X_i[14]),
.I4(Data_Y_i[13]),
.I5(Data_X_i[13]),
.O(eqXY_o_INST_0_i_9_n_0));
CARRY4 gtXY_o_INST_0
(.CI(gtXY_o_INST_0_i_1_n_0),
.CO({gtXY_o,gtXY_o_INST_0_n_1,gtXY_o_INST_0_n_2,gtXY_o_INST_0_n_3}),
.CYINIT(1'b0),
.DI({gtXY_o_INST_0_i_2_n_0,gtXY_o_INST_0_i_3_n_0,gtXY_o_INST_0_i_4_n_0,gtXY_o_INST_0_i_5_n_0}),
.O(NLW_gtXY_o_INST_0_O_UNCONNECTED[3:0]),
.S({gtXY_o_INST_0_i_6_n_0,gtXY_o_INST_0_i_7_n_0,gtXY_o_INST_0_i_8_n_0,gtXY_o_INST_0_i_9_n_0}));
CARRY4 gtXY_o_INST_0_i_1
(.CI(gtXY_o_INST_0_i_10_n_0),
.CO({gtXY_o_INST_0_i_1_n_0,gtXY_o_INST_0_i_1_n_1,gtXY_o_INST_0_i_1_n_2,gtXY_o_INST_0_i_1_n_3}),
.CYINIT(1'b0),
.DI({gtXY_o_INST_0_i_11_n_0,gtXY_o_INST_0_i_12_n_0,gtXY_o_INST_0_i_13_n_0,gtXY_o_INST_0_i_14_n_0}),
.O(NLW_gtXY_o_INST_0_i_1_O_UNCONNECTED[3:0]),
.S({gtXY_o_INST_0_i_15_n_0,gtXY_o_INST_0_i_16_n_0,gtXY_o_INST_0_i_17_n_0,gtXY_o_INST_0_i_18_n_0}));
CARRY4 gtXY_o_INST_0_i_10
(.CI(gtXY_o_INST_0_i_19_n_0),
.CO({gtXY_o_INST_0_i_10_n_0,gtXY_o_INST_0_i_10_n_1,gtXY_o_INST_0_i_10_n_2,gtXY_o_INST_0_i_10_n_3}),
.CYINIT(1'b0),
.DI({gtXY_o_INST_0_i_20_n_0,gtXY_o_INST_0_i_21_n_0,gtXY_o_INST_0_i_22_n_0,gtXY_o_INST_0_i_23_n_0}),
.O(NLW_gtXY_o_INST_0_i_10_O_UNCONNECTED[3:0]),
.S({gtXY_o_INST_0_i_24_n_0,gtXY_o_INST_0_i_25_n_0,gtXY_o_INST_0_i_26_n_0,gtXY_o_INST_0_i_27_n_0}));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_11
(.I0(Data_X_i[22]),
.I1(Data_Y_i[22]),
.I2(Data_Y_i[23]),
.I3(Data_X_i[23]),
.O(gtXY_o_INST_0_i_11_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_12
(.I0(Data_X_i[20]),
.I1(Data_Y_i[20]),
.I2(Data_Y_i[21]),
.I3(Data_X_i[21]),
.O(gtXY_o_INST_0_i_12_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_13
(.I0(Data_X_i[18]),
.I1(Data_Y_i[18]),
.I2(Data_Y_i[19]),
.I3(Data_X_i[19]),
.O(gtXY_o_INST_0_i_13_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_14
(.I0(Data_X_i[16]),
.I1(Data_Y_i[16]),
.I2(Data_Y_i[17]),
.I3(Data_X_i[17]),
.O(gtXY_o_INST_0_i_14_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_15
(.I0(Data_X_i[22]),
.I1(Data_Y_i[22]),
.I2(Data_X_i[23]),
.I3(Data_Y_i[23]),
.O(gtXY_o_INST_0_i_15_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_16
(.I0(Data_X_i[20]),
.I1(Data_Y_i[20]),
.I2(Data_X_i[21]),
.I3(Data_Y_i[21]),
.O(gtXY_o_INST_0_i_16_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_17
(.I0(Data_X_i[18]),
.I1(Data_Y_i[18]),
.I2(Data_X_i[19]),
.I3(Data_Y_i[19]),
.O(gtXY_o_INST_0_i_17_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_18
(.I0(Data_X_i[16]),
.I1(Data_Y_i[16]),
.I2(Data_X_i[17]),
.I3(Data_Y_i[17]),
.O(gtXY_o_INST_0_i_18_n_0));
CARRY4 gtXY_o_INST_0_i_19
(.CI(1'b0),
.CO({gtXY_o_INST_0_i_19_n_0,gtXY_o_INST_0_i_19_n_1,gtXY_o_INST_0_i_19_n_2,gtXY_o_INST_0_i_19_n_3}),
.CYINIT(1'b0),
.DI({gtXY_o_INST_0_i_28_n_0,gtXY_o_INST_0_i_29_n_0,gtXY_o_INST_0_i_30_n_0,gtXY_o_INST_0_i_31_n_0}),
.O(NLW_gtXY_o_INST_0_i_19_O_UNCONNECTED[3:0]),
.S({gtXY_o_INST_0_i_32_n_0,gtXY_o_INST_0_i_33_n_0,gtXY_o_INST_0_i_34_n_0,gtXY_o_INST_0_i_35_n_0}));
LUT2 #(
.INIT(4'h2))
gtXY_o_INST_0_i_2
(.I0(Data_X_i[30]),
.I1(Data_Y_i[30]),
.O(gtXY_o_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_20
(.I0(Data_X_i[14]),
.I1(Data_Y_i[14]),
.I2(Data_Y_i[15]),
.I3(Data_X_i[15]),
.O(gtXY_o_INST_0_i_20_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_21
(.I0(Data_X_i[12]),
.I1(Data_Y_i[12]),
.I2(Data_Y_i[13]),
.I3(Data_X_i[13]),
.O(gtXY_o_INST_0_i_21_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_22
(.I0(Data_X_i[10]),
.I1(Data_Y_i[10]),
.I2(Data_Y_i[11]),
.I3(Data_X_i[11]),
.O(gtXY_o_INST_0_i_22_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_23
(.I0(Data_X_i[8]),
.I1(Data_Y_i[8]),
.I2(Data_Y_i[9]),
.I3(Data_X_i[9]),
.O(gtXY_o_INST_0_i_23_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_24
(.I0(Data_X_i[14]),
.I1(Data_Y_i[14]),
.I2(Data_X_i[15]),
.I3(Data_Y_i[15]),
.O(gtXY_o_INST_0_i_24_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_25
(.I0(Data_X_i[12]),
.I1(Data_Y_i[12]),
.I2(Data_X_i[13]),
.I3(Data_Y_i[13]),
.O(gtXY_o_INST_0_i_25_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_26
(.I0(Data_X_i[10]),
.I1(Data_Y_i[10]),
.I2(Data_X_i[11]),
.I3(Data_Y_i[11]),
.O(gtXY_o_INST_0_i_26_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_27
(.I0(Data_X_i[8]),
.I1(Data_Y_i[8]),
.I2(Data_X_i[9]),
.I3(Data_Y_i[9]),
.O(gtXY_o_INST_0_i_27_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_28
(.I0(Data_X_i[6]),
.I1(Data_Y_i[6]),
.I2(Data_Y_i[7]),
.I3(Data_X_i[7]),
.O(gtXY_o_INST_0_i_28_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_29
(.I0(Data_X_i[4]),
.I1(Data_Y_i[4]),
.I2(Data_Y_i[5]),
.I3(Data_X_i[5]),
.O(gtXY_o_INST_0_i_29_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_3
(.I0(Data_X_i[28]),
.I1(Data_Y_i[28]),
.I2(Data_Y_i[29]),
.I3(Data_X_i[29]),
.O(gtXY_o_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_30
(.I0(Data_X_i[2]),
.I1(Data_Y_i[2]),
.I2(Data_Y_i[3]),
.I3(Data_X_i[3]),
.O(gtXY_o_INST_0_i_30_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_31
(.I0(Data_X_i[0]),
.I1(Data_Y_i[0]),
.I2(Data_Y_i[1]),
.I3(Data_X_i[1]),
.O(gtXY_o_INST_0_i_31_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_32
(.I0(Data_X_i[6]),
.I1(Data_Y_i[6]),
.I2(Data_X_i[7]),
.I3(Data_Y_i[7]),
.O(gtXY_o_INST_0_i_32_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_33
(.I0(Data_X_i[4]),
.I1(Data_Y_i[4]),
.I2(Data_X_i[5]),
.I3(Data_Y_i[5]),
.O(gtXY_o_INST_0_i_33_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_34
(.I0(Data_X_i[2]),
.I1(Data_Y_i[2]),
.I2(Data_X_i[3]),
.I3(Data_Y_i[3]),
.O(gtXY_o_INST_0_i_34_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_35
(.I0(Data_X_i[0]),
.I1(Data_Y_i[0]),
.I2(Data_X_i[1]),
.I3(Data_Y_i[1]),
.O(gtXY_o_INST_0_i_35_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_4
(.I0(Data_X_i[26]),
.I1(Data_Y_i[26]),
.I2(Data_Y_i[27]),
.I3(Data_X_i[27]),
.O(gtXY_o_INST_0_i_4_n_0));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_INST_0_i_5
(.I0(Data_X_i[24]),
.I1(Data_Y_i[24]),
.I2(Data_Y_i[25]),
.I3(Data_X_i[25]),
.O(gtXY_o_INST_0_i_5_n_0));
LUT2 #(
.INIT(4'h9))
gtXY_o_INST_0_i_6
(.I0(Data_Y_i[30]),
.I1(Data_X_i[30]),
.O(gtXY_o_INST_0_i_6_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_7
(.I0(Data_X_i[28]),
.I1(Data_Y_i[28]),
.I2(Data_X_i[29]),
.I3(Data_Y_i[29]),
.O(gtXY_o_INST_0_i_7_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_8
(.I0(Data_X_i[26]),
.I1(Data_Y_i[26]),
.I2(Data_X_i[27]),
.I3(Data_Y_i[27]),
.O(gtXY_o_INST_0_i_8_n_0));
LUT4 #(
.INIT(16'h9009))
gtXY_o_INST_0_i_9
(.I0(Data_X_i[24]),
.I1(Data_Y_i[24]),
.I2(Data_X_i[25]),
.I3(Data_Y_i[25]),
.O(gtXY_o_INST_0_i_9_n_0));
endmodule
(* W = "9" *)
module Comparator_Less
(Data_A,
Data_B,
less);
input [8:0]Data_A;
input [8:0]Data_B;
output less;
wire [8:0]Data_A;
wire less;
wire less_INST_0_i_1_n_0;
wire less_INST_0_i_1_n_1;
wire less_INST_0_i_1_n_2;
wire less_INST_0_i_1_n_3;
wire less_INST_0_i_2_n_0;
wire less_INST_0_i_3_n_0;
wire less_INST_0_i_4_n_0;
wire less_INST_0_i_5_n_0;
wire less_INST_0_i_6_n_0;
wire less_INST_0_i_7_n_0;
wire [3:1]NLW_less_INST_0_CO_UNCONNECTED;
wire [3:0]NLW_less_INST_0_O_UNCONNECTED;
wire [3:0]NLW_less_INST_0_i_1_O_UNCONNECTED;
CARRY4 less_INST_0
(.CI(less_INST_0_i_1_n_0),
.CO({NLW_less_INST_0_CO_UNCONNECTED[3:1],less}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_less_INST_0_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,less_INST_0_i_2_n_0}));
CARRY4 less_INST_0_i_1
(.CI(1'b0),
.CO({less_INST_0_i_1_n_0,less_INST_0_i_1_n_1,less_INST_0_i_1_n_2,less_INST_0_i_1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,less_INST_0_i_3_n_0}),
.O(NLW_less_INST_0_i_1_O_UNCONNECTED[3:0]),
.S({less_INST_0_i_4_n_0,less_INST_0_i_5_n_0,less_INST_0_i_6_n_0,less_INST_0_i_7_n_0}));
LUT1 #(
.INIT(2'h1))
less_INST_0_i_2
(.I0(Data_A[8]),
.O(less_INST_0_i_2_n_0));
LUT2 #(
.INIT(4'h1))
less_INST_0_i_3
(.I0(Data_A[0]),
.I1(Data_A[1]),
.O(less_INST_0_i_3_n_0));
LUT2 #(
.INIT(4'h1))
less_INST_0_i_4
(.I0(Data_A[6]),
.I1(Data_A[7]),
.O(less_INST_0_i_4_n_0));
LUT2 #(
.INIT(4'h1))
less_INST_0_i_5
(.I0(Data_A[4]),
.I1(Data_A[5]),
.O(less_INST_0_i_5_n_0));
LUT2 #(
.INIT(4'h1))
less_INST_0_i_6
(.I0(Data_A[2]),
.I1(Data_A[3]),
.O(less_INST_0_i_6_n_0));
LUT2 #(
.INIT(4'h2))
less_INST_0_i_7
(.I0(Data_A[0]),
.I1(Data_A[1]),
.O(less_INST_0_i_7_n_0));
endmodule
(* W_Exp = "9" *)
module Comparators
(exp,
overflow,
underflow);
input [8:0]exp;
output overflow;
output underflow;
wire [8:0]exp;
wire overflow;
wire underflow;
(* W = "9" *)
Greater_Comparator GTComparator
(.Data_A(exp),
.Data_B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gthan(overflow));
(* W = "9" *)
Comparator_Less LTComparator
(.Data_A(exp),
.Data_B({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.less(underflow));
endmodule
(* EW = "8" *)
module Exp_Operation
(clk,
rst,
load_a_i,
load_b_i,
Data_A_i,
Data_B_i,
Add_Subt_i,
Data_Result_o,
Overflow_flag_o,
Underflow_flag_o);
input clk;
input rst;
input load_a_i;
input load_b_i;
input [7:0]Data_A_i;
input [7:0]Data_B_i;
input Add_Subt_i;
output [7:0]Data_Result_o;
output Overflow_flag_o;
output Underflow_flag_o;
wire Add_Subt_i;
wire [7:0]Data_A_i;
wire [7:0]Data_B_i;
wire [7:0]Data_Result_o;
wire [8:0]Data_S;
wire Overflow_flag;
wire Overflow_flag_o;
wire Underflow_flag;
wire Underflow_flag_o;
wire clk;
wire load_a_i;
wire load_b_i;
wire rst;
(* W = "1" *)
RegisterAdd__6 Overflow
(.D(Overflow_flag),
.Q(Overflow_flag_o),
.clk(clk),
.load(load_a_i),
.rst(rst));
(* W = "1" *)
RegisterAdd__7 Underflow
(.D(Underflow_flag),
.Q(Underflow_flag_o),
.clk(clk),
.load(load_b_i),
.rst(rst));
(* W_Exp = "9" *)
Comparators array_comparators
(.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag));
(* W = "8" *)
add_sub_carry_out exp_add_subt
(.Data_A(Data_A_i),
.Data_B(Data_B_i),
.Data_S(Data_S),
.op_mode(Add_Subt_i));
(* W = "8" *)
RegisterAdd__parameterized5 exp_result
(.D(Data_S[7:0]),
.Q(Data_Result_o),
.clk(clk),
.load(load_a_i),
.rst(rst));
endmodule
(* EW = "8" *) (* EWR = "5" *) (* SW = "23" *)
(* SWR = "26" *) (* W = "32" *)
(* NotValidForBitStream *)
module FPU_Add_Subtract_Function
(clk,
rst,
beg_FSM,
ack_FSM,
Data_X,
Data_Y,
add_subt,
r_mode,
overflow_flag,
underflow_flag,
ready,
final_result_ieee);
input clk;
input rst;
input beg_FSM;
input ack_FSM;
input [31:0]Data_X;
input [31:0]Data_Y;
input add_subt;
input [1:0]r_mode;
output overflow_flag;
output underflow_flag;
output ready;
output [31:0]final_result_ieee;
wire [25:0]Add_Subt_LZD;
wire [25:0]Add_Subt_result;
wire [30:0]DMP;
wire [31:0]Data_X;
wire [31:0]Data_X_IBUF;
wire [31:0]Data_Y;
wire [31:0]Data_Y_IBUF;
wire [30:0]DmP;
wire FSM_Add_Subt_Sgf_load;
wire FSM_Final_Result_load;
wire FSM_LZA_load;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire FSM_barrel_shifter_load;
wire FSM_exp_operation_A_S;
wire FSM_exp_operation_load_OU;
wire FSM_exp_operation_load_diff;
wire FSM_op_start_in_load_a;
wire FSM_op_start_in_load_b;
wire FSM_selector_A;
wire [1:0]FSM_selector_B;
wire FSM_selector_C;
wire FSM_selector_D;
wire [4:0]LZA_output;
wire [25:0]S_A_S_Oper_A;
wire [25:0]S_A_S_Oper_B;
wire S_A_S_op;
wire [25:0]S_Data_Shift;
wire [7:0]S_Oper_A_exp;
wire [7:0]S_Oper_B_exp;
wire [4:0]S_Shift_Value;
wire [25:0]Sgf_normalized_result;
wire ack_FSM;
wire ack_FSM_IBUF;
wire add_overflow_flag;
wire add_subt;
wire add_subt_IBUF;
wire beg_FSM;
wire beg_FSM_IBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire [7:0]exp_oper_result;
wire [31:0]final_result_ieee;
wire [31:0]final_result_ieee_OBUF;
wire load_b;
wire overflow_flag;
wire overflow_flag_OBUF;
wire [1:0]r_mode;
wire [1:0]r_mode_IBUF;
wire ready;
wire ready_OBUF;
wire real_op;
wire round_flag;
wire rst;
wire rst_IBUF;
wire rst_int;
wire [1:0]selector_B;
wire selector_C;
wire selector_D;
wire sign_final_result;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
wire NLW_FS_Module_ctrl_a_o_UNCONNECTED;
(* W = "26" *)
Multiplexer_AC__parameterized158 Add_Sub_Sgf_Oper_A_mux
(.D0({1'b0,DMP[22:0],1'b0,1'b0}),
.D1(Sgf_normalized_result),
.S(S_A_S_Oper_A),
.ctrl(FSM_selector_D));
(* W = "26" *)
Multiplexer_AC__parameterized159 Add_Sub_Sgf_Oper_B_mux
(.D0(Sgf_normalized_result),
.D1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(S_A_S_Oper_B),
.ctrl(FSM_selector_D));
(* W = "1" *)
Multiplexer_AC__parameterized157 Add_Sub_Sgf_op_mux
(.D0(real_op),
.D1(1'b0),
.S(S_A_S_op),
.ctrl(FSM_selector_D));
(* SWR = "26" *)
Add_Subt Add_Subt_Sgf_module
(.Add_Sub_op_i(S_A_S_op),
.Data_A_i(S_A_S_Oper_A),
.Data_Result_o(Add_Subt_result),
.FSM_C_o(add_overflow_flag),
.PreData_B_i(S_A_S_Oper_B),
.clk(clk_IBUF_BUFG),
.load_i(FSM_Add_Subt_Sgf_load),
.rst(rst_int));
(* W = "26" *)
Multiplexer_AC__parameterized0 Barrel_Shifter_D_I_mux
(.D0({1'b0,DmP[22:0],1'b0,1'b0}),
.D1(Add_Subt_result),
.S(S_Data_Shift),
.ctrl(FSM_selector_C));
(* W = "5" *)
Mux_3x1__parameterized0 Barrel_Shifter_S_V_mux
(.D0(exp_oper_result[4:0]),
.D1(LZA_output),
.D2({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(S_Shift_Value),
.ctrl(FSM_selector_B));
(* EWR = "5" *)
(* SWR = "26" *)
Barrel_Shifter Barrel_Shifter_module
(.Bit_Shift_i(FSM_barrel_shifter_B_S),
.Left_Right_i(FSM_barrel_shifter_L_R),
.N_mant_o(Sgf_normalized_result),
.Shift_Data_i(S_Data_Shift),
.Shift_Value_i(S_Shift_Value),
.clk(clk_IBUF_BUFG),
.load_i(FSM_barrel_shifter_load),
.rst(rst_int));
IBUF \Data_X_IBUF[0]_inst
(.I(Data_X[0]),
.O(Data_X_IBUF[0]));
IBUF \Data_X_IBUF[10]_inst
(.I(Data_X[10]),
.O(Data_X_IBUF[10]));
IBUF \Data_X_IBUF[11]_inst
(.I(Data_X[11]),
.O(Data_X_IBUF[11]));
IBUF \Data_X_IBUF[12]_inst
(.I(Data_X[12]),
.O(Data_X_IBUF[12]));
IBUF \Data_X_IBUF[13]_inst
(.I(Data_X[13]),
.O(Data_X_IBUF[13]));
IBUF \Data_X_IBUF[14]_inst
(.I(Data_X[14]),
.O(Data_X_IBUF[14]));
IBUF \Data_X_IBUF[15]_inst
(.I(Data_X[15]),
.O(Data_X_IBUF[15]));
IBUF \Data_X_IBUF[16]_inst
(.I(Data_X[16]),
.O(Data_X_IBUF[16]));
IBUF \Data_X_IBUF[17]_inst
(.I(Data_X[17]),
.O(Data_X_IBUF[17]));
IBUF \Data_X_IBUF[18]_inst
(.I(Data_X[18]),
.O(Data_X_IBUF[18]));
IBUF \Data_X_IBUF[19]_inst
(.I(Data_X[19]),
.O(Data_X_IBUF[19]));
IBUF \Data_X_IBUF[1]_inst
(.I(Data_X[1]),
.O(Data_X_IBUF[1]));
IBUF \Data_X_IBUF[20]_inst
(.I(Data_X[20]),
.O(Data_X_IBUF[20]));
IBUF \Data_X_IBUF[21]_inst
(.I(Data_X[21]),
.O(Data_X_IBUF[21]));
IBUF \Data_X_IBUF[22]_inst
(.I(Data_X[22]),
.O(Data_X_IBUF[22]));
IBUF \Data_X_IBUF[23]_inst
(.I(Data_X[23]),
.O(Data_X_IBUF[23]));
IBUF \Data_X_IBUF[24]_inst
(.I(Data_X[24]),
.O(Data_X_IBUF[24]));
IBUF \Data_X_IBUF[25]_inst
(.I(Data_X[25]),
.O(Data_X_IBUF[25]));
IBUF \Data_X_IBUF[26]_inst
(.I(Data_X[26]),
.O(Data_X_IBUF[26]));
IBUF \Data_X_IBUF[27]_inst
(.I(Data_X[27]),
.O(Data_X_IBUF[27]));
IBUF \Data_X_IBUF[28]_inst
(.I(Data_X[28]),
.O(Data_X_IBUF[28]));
IBUF \Data_X_IBUF[29]_inst
(.I(Data_X[29]),
.O(Data_X_IBUF[29]));
IBUF \Data_X_IBUF[2]_inst
(.I(Data_X[2]),
.O(Data_X_IBUF[2]));
IBUF \Data_X_IBUF[30]_inst
(.I(Data_X[30]),
.O(Data_X_IBUF[30]));
IBUF \Data_X_IBUF[31]_inst
(.I(Data_X[31]),
.O(Data_X_IBUF[31]));
IBUF \Data_X_IBUF[3]_inst
(.I(Data_X[3]),
.O(Data_X_IBUF[3]));
IBUF \Data_X_IBUF[4]_inst
(.I(Data_X[4]),
.O(Data_X_IBUF[4]));
IBUF \Data_X_IBUF[5]_inst
(.I(Data_X[5]),
.O(Data_X_IBUF[5]));
IBUF \Data_X_IBUF[6]_inst
(.I(Data_X[6]),
.O(Data_X_IBUF[6]));
IBUF \Data_X_IBUF[7]_inst
(.I(Data_X[7]),
.O(Data_X_IBUF[7]));
IBUF \Data_X_IBUF[8]_inst
(.I(Data_X[8]),
.O(Data_X_IBUF[8]));
IBUF \Data_X_IBUF[9]_inst
(.I(Data_X[9]),
.O(Data_X_IBUF[9]));
IBUF \Data_Y_IBUF[0]_inst
(.I(Data_Y[0]),
.O(Data_Y_IBUF[0]));
IBUF \Data_Y_IBUF[10]_inst
(.I(Data_Y[10]),
.O(Data_Y_IBUF[10]));
IBUF \Data_Y_IBUF[11]_inst
(.I(Data_Y[11]),
.O(Data_Y_IBUF[11]));
IBUF \Data_Y_IBUF[12]_inst
(.I(Data_Y[12]),
.O(Data_Y_IBUF[12]));
IBUF \Data_Y_IBUF[13]_inst
(.I(Data_Y[13]),
.O(Data_Y_IBUF[13]));
IBUF \Data_Y_IBUF[14]_inst
(.I(Data_Y[14]),
.O(Data_Y_IBUF[14]));
IBUF \Data_Y_IBUF[15]_inst
(.I(Data_Y[15]),
.O(Data_Y_IBUF[15]));
IBUF \Data_Y_IBUF[16]_inst
(.I(Data_Y[16]),
.O(Data_Y_IBUF[16]));
IBUF \Data_Y_IBUF[17]_inst
(.I(Data_Y[17]),
.O(Data_Y_IBUF[17]));
IBUF \Data_Y_IBUF[18]_inst
(.I(Data_Y[18]),
.O(Data_Y_IBUF[18]));
IBUF \Data_Y_IBUF[19]_inst
(.I(Data_Y[19]),
.O(Data_Y_IBUF[19]));
IBUF \Data_Y_IBUF[1]_inst
(.I(Data_Y[1]),
.O(Data_Y_IBUF[1]));
IBUF \Data_Y_IBUF[20]_inst
(.I(Data_Y[20]),
.O(Data_Y_IBUF[20]));
IBUF \Data_Y_IBUF[21]_inst
(.I(Data_Y[21]),
.O(Data_Y_IBUF[21]));
IBUF \Data_Y_IBUF[22]_inst
(.I(Data_Y[22]),
.O(Data_Y_IBUF[22]));
IBUF \Data_Y_IBUF[23]_inst
(.I(Data_Y[23]),
.O(Data_Y_IBUF[23]));
IBUF \Data_Y_IBUF[24]_inst
(.I(Data_Y[24]),
.O(Data_Y_IBUF[24]));
IBUF \Data_Y_IBUF[25]_inst
(.I(Data_Y[25]),
.O(Data_Y_IBUF[25]));
IBUF \Data_Y_IBUF[26]_inst
(.I(Data_Y[26]),
.O(Data_Y_IBUF[26]));
IBUF \Data_Y_IBUF[27]_inst
(.I(Data_Y[27]),
.O(Data_Y_IBUF[27]));
IBUF \Data_Y_IBUF[28]_inst
(.I(Data_Y[28]),
.O(Data_Y_IBUF[28]));
IBUF \Data_Y_IBUF[29]_inst
(.I(Data_Y[29]),
.O(Data_Y_IBUF[29]));
IBUF \Data_Y_IBUF[2]_inst
(.I(Data_Y[2]),
.O(Data_Y_IBUF[2]));
IBUF \Data_Y_IBUF[30]_inst
(.I(Data_Y[30]),
.O(Data_Y_IBUF[30]));
IBUF \Data_Y_IBUF[31]_inst
(.I(Data_Y[31]),
.O(Data_Y_IBUF[31]));
IBUF \Data_Y_IBUF[3]_inst
(.I(Data_Y[3]),
.O(Data_Y_IBUF[3]));
IBUF \Data_Y_IBUF[4]_inst
(.I(Data_Y[4]),
.O(Data_Y_IBUF[4]));
IBUF \Data_Y_IBUF[5]_inst
(.I(Data_Y[5]),
.O(Data_Y_IBUF[5]));
IBUF \Data_Y_IBUF[6]_inst
(.I(Data_Y[6]),
.O(Data_Y_IBUF[6]));
IBUF \Data_Y_IBUF[7]_inst
(.I(Data_Y[7]),
.O(Data_Y_IBUF[7]));
IBUF \Data_Y_IBUF[8]_inst
(.I(Data_Y[8]),
.O(Data_Y_IBUF[8]));
IBUF \Data_Y_IBUF[9]_inst
(.I(Data_Y[9]),
.O(Data_Y_IBUF[9]));
(* W = "8" *)
Multiplexer_AC__1 Exp_Oper_A_mux
(.D0(DMP[30:23]),
.D1(exp_oper_result),
.S(S_Oper_A_exp),
.ctrl(FSM_selector_A));
(* W = "8" *)
Mux_3x1 Exp_Oper_B_mux
(.D0(DmP[30:23]),
.D1({1'b0,1'b0,1'b0,LZA_output}),
.D2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(S_Oper_B_exp),
.ctrl(FSM_selector_B));
(* EW = "8" *)
Exp_Operation Exp_Operation_Module
(.Add_Subt_i(FSM_exp_operation_A_S),
.Data_A_i(S_Oper_A_exp),
.Data_B_i(S_Oper_B_exp),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag_OBUF),
.Underflow_flag_o(underflow_flag_OBUF),
.clk(clk_IBUF_BUFG),
.load_a_i(FSM_exp_operation_load_diff),
.load_b_i(FSM_exp_operation_load_OU),
.rst(rst_int));
(* add_subt = "4'b0110" *)
(* add_subt_r = "4'b0111" *)
(* extra1_64 = "4'b0100" *)
(* extra2_64 = "4'b1011" *)
(* load_diff_exp = "4'b0011" *)
(* load_final_result = "4'b1101" *)
(* load_oper = "4'b0001" *)
(* norm_sgf_first = "4'b0101" *)
(* norm_sgf_r = "4'b1100" *)
(* overflow_add = "4'b1000" *)
(* overflow_add_r = "4'b1010" *)
(* ready_flag = "4'b1110" *)
(* round_sgf = "4'b1001" *)
(* start = "4'b0000" *)
(* zero_info_state = "4'b0010" *)
FSM_Add_Subtract FS_Module
(.A_S_op_o(FSM_exp_operation_A_S),
.add_overflow_i(add_overflow_flag),
.beg_FSM(beg_FSM_IBUF),
.bit_shift_o(FSM_barrel_shifter_B_S),
.clk(clk_IBUF_BUFG),
.ctrl_a_o(NLW_FS_Module_ctrl_a_o_UNCONNECTED),
.ctrl_b_load_o(load_b),
.ctrl_b_o(selector_B),
.ctrl_c_o(selector_C),
.ctrl_d_o(selector_D),
.left_right_o(FSM_barrel_shifter_L_R),
.load_1_o(FSM_op_start_in_load_a),
.load_2_o(FSM_op_start_in_load_b),
.load_3_o(FSM_exp_operation_load_diff),
.load_4_o(FSM_barrel_shifter_load),
.load_5_o(FSM_Add_Subt_Sgf_load),
.load_6_o(FSM_LZA_load),
.load_7_o(FSM_Final_Result_load),
.load_8_o(FSM_exp_operation_load_OU),
.norm_iteration_i(FSM_selector_C),
.ready(ready_OBUF),
.round_i(round_flag),
.rst(rst_IBUF),
.rst_FSM(ack_FSM_IBUF),
.rst_int(rst_int),
.zero_flag_i(zero_flag));
(* EWR = "5" *)
(* SWR = "26" *)
LZD Leading_Zero_Detector_Module
(.Add_subt_result_i(Add_Subt_LZD),
.Shift_Value_o(LZA_output),
.clk(clk_IBUF_BUFG),
.load_i(FSM_LZA_load),
.rst(rst_int));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_1
(.I0(Add_Subt_result[25]),
.O(Add_Subt_LZD[25]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_10
(.I0(Add_Subt_result[16]),
.O(Add_Subt_LZD[16]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_11
(.I0(Add_Subt_result[15]),
.O(Add_Subt_LZD[15]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_12
(.I0(Add_Subt_result[14]),
.O(Add_Subt_LZD[14]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_13
(.I0(Add_Subt_result[13]),
.O(Add_Subt_LZD[13]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_14
(.I0(Add_Subt_result[12]),
.O(Add_Subt_LZD[12]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_15
(.I0(Add_Subt_result[11]),
.O(Add_Subt_LZD[11]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_16
(.I0(Add_Subt_result[10]),
.O(Add_Subt_LZD[10]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_17
(.I0(Add_Subt_result[9]),
.O(Add_Subt_LZD[9]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_18
(.I0(Add_Subt_result[8]),
.O(Add_Subt_LZD[8]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_19
(.I0(Add_Subt_result[7]),
.O(Add_Subt_LZD[7]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_2
(.I0(Add_Subt_result[24]),
.O(Add_Subt_LZD[24]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_20
(.I0(Add_Subt_result[6]),
.O(Add_Subt_LZD[6]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_21
(.I0(Add_Subt_result[5]),
.O(Add_Subt_LZD[5]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_22
(.I0(Add_Subt_result[4]),
.O(Add_Subt_LZD[4]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_23
(.I0(Add_Subt_result[3]),
.O(Add_Subt_LZD[3]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_24
(.I0(Add_Subt_result[2]),
.O(Add_Subt_LZD[2]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_25
(.I0(Add_Subt_result[1]),
.O(Add_Subt_LZD[1]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_26
(.I0(Add_Subt_result[0]),
.O(Add_Subt_LZD[0]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_3
(.I0(Add_Subt_result[23]),
.O(Add_Subt_LZD[23]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_4
(.I0(Add_Subt_result[22]),
.O(Add_Subt_LZD[22]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_5
(.I0(Add_Subt_result[21]),
.O(Add_Subt_LZD[21]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_6
(.I0(Add_Subt_result[20]),
.O(Add_Subt_LZD[20]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_7
(.I0(Add_Subt_result[19]),
.O(Add_Subt_LZD[19]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_8
(.I0(Add_Subt_result[18]),
.O(Add_Subt_LZD[18]));
LUT1 #(
.INIT(2'h1))
Leading_Zero_Detector_Module_i_9
(.I0(Add_Subt_result[17]),
.O(Add_Subt_LZD[17]));
(* W = "32" *)
Oper_Start_In Oper_Start_in_module
(.DMP_o(DMP),
.Data_X_i(Data_X_IBUF),
.Data_Y_i(Data_Y_IBUF),
.DmP_o(DmP),
.add_subt_i(add_subt_IBUF),
.clk(clk_IBUF_BUFG),
.load_a_i(FSM_op_start_in_load_a),
.load_b_i(FSM_op_start_in_load_b),
.real_op_o(real_op),
.rst(rst_int),
.sign_final_result_o(sign_final_result),
.zero_flag_o(zero_flag));
Round_Sgf_Dec Rounding_Decoder
(.Data_i(Sgf_normalized_result[1:0]),
.Round_Flag_o(round_flag),
.Round_Type_i(r_mode_IBUF),
.Sign_Result_i(sign_final_result));
(* W = "1" *)
RegisterAdd__1 Sel_A
(.D(1'b0),
.Q(FSM_selector_A),
.clk(clk_IBUF_BUFG),
.load(selector_D),
.rst(rst_int));
(* W = "2" *)
RegisterAdd__parameterized0 Sel_B
(.D(selector_B),
.Q(FSM_selector_B),
.clk(clk_IBUF_BUFG),
.load(load_b),
.rst(rst_int));
(* W = "1" *)
RegisterAdd__2 Sel_C
(.D(1'b0),
.Q(FSM_selector_C),
.clk(clk_IBUF_BUFG),
.load(selector_C),
.rst(rst_int));
(* W = "1" *)
RegisterAdd__3 Sel_D
(.D(1'b0),
.Q(FSM_selector_D),
.clk(clk_IBUF_BUFG),
.load(selector_D),
.rst(rst_int));
IBUF ack_FSM_IBUF_inst
(.I(ack_FSM),
.O(ack_FSM_IBUF));
IBUF add_subt_IBUF_inst
(.I(add_subt),
.O(add_subt_IBUF));
IBUF beg_FSM_IBUF_inst
(.I(beg_FSM),
.O(beg_FSM_IBUF));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
(* EW = "8" *)
(* SW = "23" *)
(* W = "32" *)
Tenth_Phase final_result_ieee_Module
(.clk(clk_IBUF_BUFG),
.exp_ieee_i(exp_oper_result),
.final_result_ieee_o(final_result_ieee_OBUF),
.load_i(FSM_Final_Result_load),
.rst(rst_int),
.sel_a_i(overflow_flag_OBUF),
.sel_b_i(underflow_flag_OBUF),
.sgf_ieee_i(Sgf_normalized_result[24:2]),
.sign_i(sign_final_result));
OBUF \final_result_ieee_OBUF[0]_inst
(.I(final_result_ieee_OBUF[0]),
.O(final_result_ieee[0]));
OBUF \final_result_ieee_OBUF[10]_inst
(.I(final_result_ieee_OBUF[10]),
.O(final_result_ieee[10]));
OBUF \final_result_ieee_OBUF[11]_inst
(.I(final_result_ieee_OBUF[11]),
.O(final_result_ieee[11]));
OBUF \final_result_ieee_OBUF[12]_inst
(.I(final_result_ieee_OBUF[12]),
.O(final_result_ieee[12]));
OBUF \final_result_ieee_OBUF[13]_inst
(.I(final_result_ieee_OBUF[13]),
.O(final_result_ieee[13]));
OBUF \final_result_ieee_OBUF[14]_inst
(.I(final_result_ieee_OBUF[14]),
.O(final_result_ieee[14]));
OBUF \final_result_ieee_OBUF[15]_inst
(.I(final_result_ieee_OBUF[15]),
.O(final_result_ieee[15]));
OBUF \final_result_ieee_OBUF[16]_inst
(.I(final_result_ieee_OBUF[16]),
.O(final_result_ieee[16]));
OBUF \final_result_ieee_OBUF[17]_inst
(.I(final_result_ieee_OBUF[17]),
.O(final_result_ieee[17]));
OBUF \final_result_ieee_OBUF[18]_inst
(.I(final_result_ieee_OBUF[18]),
.O(final_result_ieee[18]));
OBUF \final_result_ieee_OBUF[19]_inst
(.I(final_result_ieee_OBUF[19]),
.O(final_result_ieee[19]));
OBUF \final_result_ieee_OBUF[1]_inst
(.I(final_result_ieee_OBUF[1]),
.O(final_result_ieee[1]));
OBUF \final_result_ieee_OBUF[20]_inst
(.I(final_result_ieee_OBUF[20]),
.O(final_result_ieee[20]));
OBUF \final_result_ieee_OBUF[21]_inst
(.I(final_result_ieee_OBUF[21]),
.O(final_result_ieee[21]));
OBUF \final_result_ieee_OBUF[22]_inst
(.I(final_result_ieee_OBUF[22]),
.O(final_result_ieee[22]));
OBUF \final_result_ieee_OBUF[23]_inst
(.I(final_result_ieee_OBUF[23]),
.O(final_result_ieee[23]));
OBUF \final_result_ieee_OBUF[24]_inst
(.I(final_result_ieee_OBUF[24]),
.O(final_result_ieee[24]));
OBUF \final_result_ieee_OBUF[25]_inst
(.I(final_result_ieee_OBUF[25]),
.O(final_result_ieee[25]));
OBUF \final_result_ieee_OBUF[26]_inst
(.I(final_result_ieee_OBUF[26]),
.O(final_result_ieee[26]));
OBUF \final_result_ieee_OBUF[27]_inst
(.I(final_result_ieee_OBUF[27]),
.O(final_result_ieee[27]));
OBUF \final_result_ieee_OBUF[28]_inst
(.I(final_result_ieee_OBUF[28]),
.O(final_result_ieee[28]));
OBUF \final_result_ieee_OBUF[29]_inst
(.I(final_result_ieee_OBUF[29]),
.O(final_result_ieee[29]));
OBUF \final_result_ieee_OBUF[2]_inst
(.I(final_result_ieee_OBUF[2]),
.O(final_result_ieee[2]));
OBUF \final_result_ieee_OBUF[30]_inst
(.I(final_result_ieee_OBUF[30]),
.O(final_result_ieee[30]));
OBUF \final_result_ieee_OBUF[31]_inst
(.I(final_result_ieee_OBUF[31]),
.O(final_result_ieee[31]));
OBUF \final_result_ieee_OBUF[3]_inst
(.I(final_result_ieee_OBUF[3]),
.O(final_result_ieee[3]));
OBUF \final_result_ieee_OBUF[4]_inst
(.I(final_result_ieee_OBUF[4]),
.O(final_result_ieee[4]));
OBUF \final_result_ieee_OBUF[5]_inst
(.I(final_result_ieee_OBUF[5]),
.O(final_result_ieee[5]));
OBUF \final_result_ieee_OBUF[6]_inst
(.I(final_result_ieee_OBUF[6]),
.O(final_result_ieee[6]));
OBUF \final_result_ieee_OBUF[7]_inst
(.I(final_result_ieee_OBUF[7]),
.O(final_result_ieee[7]));
OBUF \final_result_ieee_OBUF[8]_inst
(.I(final_result_ieee_OBUF[8]),
.O(final_result_ieee[8]));
OBUF \final_result_ieee_OBUF[9]_inst
(.I(final_result_ieee_OBUF[9]),
.O(final_result_ieee[9]));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
IBUF \r_mode_IBUF[0]_inst
(.I(r_mode[0]),
.O(r_mode_IBUF[0]));
IBUF \r_mode_IBUF[1]_inst
(.I(r_mode[1]),
.O(r_mode_IBUF[1]));
OBUF ready_OBUF_inst
(.I(ready_OBUF),
.O(ready));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
endmodule
(* add_subt = "4'b0110" *) (* add_subt_r = "4'b0111" *) (* extra1_64 = "4'b0100" *)
(* extra2_64 = "4'b1011" *) (* load_diff_exp = "4'b0011" *) (* load_final_result = "4'b1101" *)
(* load_oper = "4'b0001" *) (* norm_sgf_first = "4'b0101" *) (* norm_sgf_r = "4'b1100" *)
(* overflow_add = "4'b1000" *) (* overflow_add_r = "4'b1010" *) (* ready_flag = "4'b1110" *)
(* round_sgf = "4'b1001" *) (* start = "4'b0000" *) (* zero_info_state = "4'b0010" *)
module FSM_Add_Subtract
(clk,
rst,
rst_FSM,
beg_FSM,
zero_flag_i,
norm_iteration_i,
add_overflow_i,
round_i,
load_1_o,
load_2_o,
load_3_o,
load_8_o,
A_S_op_o,
load_4_o,
left_right_o,
bit_shift_o,
load_5_o,
load_6_o,
load_7_o,
ctrl_a_o,
ctrl_b_o,
ctrl_b_load_o,
ctrl_c_o,
ctrl_d_o,
rst_int,
ready);
input clk;
input rst;
input rst_FSM;
input beg_FSM;
input zero_flag_i;
input norm_iteration_i;
input add_overflow_i;
input round_i;
output load_1_o;
output load_2_o;
output load_3_o;
output load_8_o;
output A_S_op_o;
output load_4_o;
output left_right_o;
output bit_shift_o;
output load_5_o;
output load_6_o;
output load_7_o;
output ctrl_a_o;
output [1:0]ctrl_b_o;
output ctrl_b_load_o;
output ctrl_c_o;
output ctrl_d_o;
output rst_int;
output ready;
wire \<const0> ;
wire A_S_op_o;
wire add_overflow_i;
wire beg_FSM;
wire bit_shift_o;
wire clk;
wire ctrl_b_load_o;
wire [1:0]ctrl_b_o;
wire ctrl_c_o;
wire ctrl_d_o;
wire left_right_o;
wire load_1_o;
wire load_2_o;
wire load_3_o;
wire load_4_o;
wire load_5_o;
wire load_6_o;
wire load_7_o;
wire load_8_o;
wire norm_iteration_i;
wire ready;
wire round_i;
wire rst;
wire rst_FSM;
wire rst_int;
wire [3:0]state_next;
wire [3:0]state_reg;
wire \state_reg[3]_i_1_n_0 ;
wire \state_reg[3]_i_3_n_0 ;
wire \state_reg[3]_i_4_n_0 ;
wire zero_flag_i;
assign ctrl_a_o = \<const0> ;
LUT6 #(
.INIT(64'hDFDFFBFFFFFFFFFF))
A_S_op_o_INST_0
(.I0(state_reg[3]),
.I1(state_reg[2]),
.I2(state_reg[1]),
.I3(norm_iteration_i),
.I4(state_reg[0]),
.I5(add_overflow_i),
.O(A_S_op_o));
GND GND
(.G(\<const0> ));
LUT6 #(
.INIT(64'h0704000080800000))
bit_shift_o_INST_0
(.I0(state_reg[0]),
.I1(state_reg[3]),
.I2(state_reg[1]),
.I3(norm_iteration_i),
.I4(add_overflow_i),
.I5(state_reg[2]),
.O(bit_shift_o));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h10))
ctrl_b_load_o_INST_0
(.I0(state_reg[2]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.O(ctrl_b_load_o));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0010))
\ctrl_b_o[0]_INST_0
(.I0(state_reg[0]),
.I1(state_reg[2]),
.I2(state_reg[3]),
.I3(add_overflow_i),
.O(ctrl_b_o[0]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h10101000))
\ctrl_b_o[1]_INST_0
(.I0(state_reg[0]),
.I1(state_reg[2]),
.I2(state_reg[3]),
.I3(add_overflow_i),
.I4(state_reg[1]),
.O(ctrl_b_o[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h1000))
ctrl_c_o_INST_0
(.I0(state_reg[3]),
.I1(state_reg[0]),
.I2(state_reg[1]),
.I3(state_reg[2]),
.O(ctrl_c_o));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00400000))
ctrl_d_o_INST_0
(.I0(state_reg[2]),
.I1(state_reg[0]),
.I2(round_i),
.I3(state_reg[1]),
.I4(state_reg[3]),
.O(ctrl_d_o));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00001000))
left_right_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[3]),
.I2(state_reg[2]),
.I3(norm_iteration_i),
.I4(add_overflow_i),
.O(left_right_o));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0004))
load_1_o_INST_0
(.I0(state_reg[2]),
.I1(state_reg[0]),
.I2(state_reg[1]),
.I3(state_reg[3]),
.O(load_1_o));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0002))
load_2_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[2]),
.O(load_2_o));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0188))
load_3_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[2]),
.O(load_3_o));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h1400))
load_4_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[2]),
.O(load_4_o));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h20))
load_5_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[3]),
.I2(state_reg[2]),
.O(load_5_o));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0100))
load_6_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[2]),
.I2(state_reg[0]),
.I3(state_reg[3]),
.O(load_6_o));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h4000))
load_7_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[2]),
.I2(state_reg[0]),
.I3(state_reg[3]),
.O(load_7_o));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h01800080))
load_8_o_INST_0
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[2]),
.I4(norm_iteration_i),
.O(load_8_o));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h2000))
ready_INST_0
(.I0(state_reg[2]),
.I1(state_reg[0]),
.I2(state_reg[3]),
.I3(state_reg[1]),
.O(ready));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0001))
rst_int_INST_0
(.I0(state_reg[3]),
.I1(state_reg[0]),
.I2(state_reg[1]),
.I3(state_reg[2]),
.O(rst_int));
LUT6 #(
.INIT(64'h00004A4A0A0FF5F5))
\state_reg[0]_i_1
(.I0(state_reg[3]),
.I1(norm_iteration_i),
.I2(state_reg[2]),
.I3(zero_flag_i),
.I4(state_reg[1]),
.I5(state_reg[0]),
.O(state_next[0]));
LUT6 #(
.INIT(64'h3300CFBB00FF0000))
\state_reg[1]_i_1
(.I0(round_i),
.I1(state_reg[3]),
.I2(norm_iteration_i),
.I3(state_reg[2]),
.I4(state_reg[1]),
.I5(state_reg[0]),
.O(state_next[1]));
LUT6 #(
.INIT(64'h0FBA0FBA05FA00FA))
\state_reg[2]_i_1
(.I0(state_reg[3]),
.I1(norm_iteration_i),
.I2(state_reg[2]),
.I3(state_reg[1]),
.I4(zero_flag_i),
.I5(state_reg[0]),
.O(state_next[2]));
LUT6 #(
.INIT(64'hEFEFFFFFFFFFFFFA))
\state_reg[3]_i_1
(.I0(state_reg[0]),
.I1(rst_FSM),
.I2(state_reg[3]),
.I3(beg_FSM),
.I4(state_reg[1]),
.I5(state_reg[2]),
.O(\state_reg[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'hC8F0C8C0))
\state_reg[3]_i_3
(.I0(norm_iteration_i),
.I1(state_reg[2]),
.I2(state_reg[1]),
.I3(state_reg[0]),
.I4(zero_flag_i),
.O(\state_reg[3]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0FF4))
\state_reg[3]_i_4
(.I0(round_i),
.I1(state_reg[0]),
.I2(state_reg[2]),
.I3(state_reg[1]),
.O(\state_reg[3]_i_4_n_0 ));
FDCE #(
.INIT(1'b0))
\state_reg_reg[0]
(.C(clk),
.CE(\state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(state_next[0]),
.Q(state_reg[0]));
FDCE #(
.INIT(1'b0))
\state_reg_reg[1]
(.C(clk),
.CE(\state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(state_next[1]),
.Q(state_reg[1]));
FDCE #(
.INIT(1'b0))
\state_reg_reg[2]
(.C(clk),
.CE(\state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(state_next[2]),
.Q(state_reg[2]));
FDCE #(
.INIT(1'b0))
\state_reg_reg[3]
(.C(clk),
.CE(\state_reg[3]_i_1_n_0 ),
.CLR(rst),
.D(state_next[3]),
.Q(state_reg[3]));
MUXF7 \state_reg_reg[3]_i_2
(.I0(\state_reg[3]_i_3_n_0 ),
.I1(\state_reg[3]_i_4_n_0 ),
.O(state_next[3]),
.S(state_reg[3]));
endmodule
(* W = "9" *)
module Greater_Comparator
(Data_A,
Data_B,
gthan);
input [8:0]Data_A;
input [8:0]Data_B;
output gthan;
wire [8:0]Data_A;
wire gthan;
wire gthan_INST_0_i_1_n_0;
wire gthan_INST_0_i_1_n_1;
wire gthan_INST_0_i_1_n_2;
wire gthan_INST_0_i_1_n_3;
wire gthan_INST_0_i_2_n_0;
wire gthan_INST_0_i_3_n_0;
wire gthan_INST_0_i_4_n_0;
wire gthan_INST_0_i_5_n_0;
wire gthan_INST_0_i_6_n_0;
wire gthan_INST_0_i_7_n_0;
wire [3:1]NLW_gthan_INST_0_CO_UNCONNECTED;
wire [3:0]NLW_gthan_INST_0_O_UNCONNECTED;
wire [3:0]NLW_gthan_INST_0_i_1_O_UNCONNECTED;
CARRY4 gthan_INST_0
(.CI(gthan_INST_0_i_1_n_0),
.CO({NLW_gthan_INST_0_CO_UNCONNECTED[3:1],gthan}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Data_A[8]}),
.O(NLW_gthan_INST_0_O_UNCONNECTED[3:0]),
.S({1'b0,1'b0,1'b0,gthan_INST_0_i_2_n_0}));
CARRY4 gthan_INST_0_i_1
(.CI(1'b0),
.CO({gthan_INST_0_i_1_n_0,gthan_INST_0_i_1_n_1,gthan_INST_0_i_1_n_2,gthan_INST_0_i_1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,gthan_INST_0_i_3_n_0}),
.O(NLW_gthan_INST_0_i_1_O_UNCONNECTED[3:0]),
.S({gthan_INST_0_i_4_n_0,gthan_INST_0_i_5_n_0,gthan_INST_0_i_6_n_0,gthan_INST_0_i_7_n_0}));
LUT1 #(
.INIT(2'h1))
gthan_INST_0_i_2
(.I0(Data_A[8]),
.O(gthan_INST_0_i_2_n_0));
LUT2 #(
.INIT(4'h8))
gthan_INST_0_i_3
(.I0(Data_A[0]),
.I1(Data_A[1]),
.O(gthan_INST_0_i_3_n_0));
LUT2 #(
.INIT(4'h8))
gthan_INST_0_i_4
(.I0(Data_A[6]),
.I1(Data_A[7]),
.O(gthan_INST_0_i_4_n_0));
LUT2 #(
.INIT(4'h8))
gthan_INST_0_i_5
(.I0(Data_A[4]),
.I1(Data_A[5]),
.O(gthan_INST_0_i_5_n_0));
LUT2 #(
.INIT(4'h8))
gthan_INST_0_i_6
(.I0(Data_A[2]),
.I1(Data_A[3]),
.O(gthan_INST_0_i_6_n_0));
LUT2 #(
.INIT(4'h2))
gthan_INST_0_i_7
(.I0(Data_A[1]),
.I1(Data_A[0]),
.O(gthan_INST_0_i_7_n_0));
endmodule
(* EWR = "5" *) (* SWR = "26" *)
module LZD
(clk,
rst,
load_i,
Add_subt_result_i,
Shift_Value_o);
input clk;
input rst;
input load_i;
input [25:0]Add_subt_result_i;
output [4:0]Shift_Value_o;
wire [25:0]Add_subt_result_i;
wire [4:0]Codec_to_Reg;
wire [4:0]Shift_Value_o;
wire clk;
wire load_i;
wire rst;
(* W = "5" *)
RegisterAdd__parameterized9 Output_Reg
(.D(Codec_to_Reg),
.Q(Shift_Value_o),
.clk(clk),
.load(load_i),
.rst(rst));
Priority_Codec_32 \genblk1.Codec_32
(.Data_Bin_o(Codec_to_Reg),
.Data_Dec_i(Add_subt_result_i));
endmodule
(* W = "31" *)
module MultiplexTxT
(select,
D0_i,
D1_i,
S0_o,
S1_o);
input select;
input [30:0]D0_i;
input [30:0]D1_i;
output [30:0]S0_o;
output [30:0]S1_o;
wire [30:0]D0_i;
wire [30:0]D1_i;
wire [30:0]S0_o;
wire [30:0]S1_o;
wire select;
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[0]_INST_0
(.I0(D0_i[0]),
.I1(select),
.I2(D1_i[0]),
.O(S0_o[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[10]_INST_0
(.I0(D0_i[10]),
.I1(select),
.I2(D1_i[10]),
.O(S0_o[10]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[11]_INST_0
(.I0(D0_i[11]),
.I1(select),
.I2(D1_i[11]),
.O(S0_o[11]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[12]_INST_0
(.I0(D0_i[12]),
.I1(select),
.I2(D1_i[12]),
.O(S0_o[12]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[13]_INST_0
(.I0(D0_i[13]),
.I1(select),
.I2(D1_i[13]),
.O(S0_o[13]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[14]_INST_0
(.I0(D0_i[14]),
.I1(select),
.I2(D1_i[14]),
.O(S0_o[14]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[15]_INST_0
(.I0(D0_i[15]),
.I1(select),
.I2(D1_i[15]),
.O(S0_o[15]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[16]_INST_0
(.I0(D0_i[16]),
.I1(select),
.I2(D1_i[16]),
.O(S0_o[16]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[17]_INST_0
(.I0(D0_i[17]),
.I1(select),
.I2(D1_i[17]),
.O(S0_o[17]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[18]_INST_0
(.I0(D0_i[18]),
.I1(select),
.I2(D1_i[18]),
.O(S0_o[18]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[19]_INST_0
(.I0(D0_i[19]),
.I1(select),
.I2(D1_i[19]),
.O(S0_o[19]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[1]_INST_0
(.I0(D0_i[1]),
.I1(select),
.I2(D1_i[1]),
.O(S0_o[1]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[20]_INST_0
(.I0(D0_i[20]),
.I1(select),
.I2(D1_i[20]),
.O(S0_o[20]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[21]_INST_0
(.I0(D0_i[21]),
.I1(select),
.I2(D1_i[21]),
.O(S0_o[21]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[22]_INST_0
(.I0(D0_i[22]),
.I1(select),
.I2(D1_i[22]),
.O(S0_o[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[23]_INST_0
(.I0(D0_i[23]),
.I1(select),
.I2(D1_i[23]),
.O(S0_o[23]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[24]_INST_0
(.I0(D0_i[24]),
.I1(select),
.I2(D1_i[24]),
.O(S0_o[24]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[25]_INST_0
(.I0(D0_i[25]),
.I1(select),
.I2(D1_i[25]),
.O(S0_o[25]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[26]_INST_0
(.I0(D0_i[26]),
.I1(select),
.I2(D1_i[26]),
.O(S0_o[26]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[27]_INST_0
(.I0(D0_i[27]),
.I1(select),
.I2(D1_i[27]),
.O(S0_o[27]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[28]_INST_0
(.I0(D0_i[28]),
.I1(select),
.I2(D1_i[28]),
.O(S0_o[28]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[29]_INST_0
(.I0(D0_i[29]),
.I1(select),
.I2(D1_i[29]),
.O(S0_o[29]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[2]_INST_0
(.I0(D0_i[2]),
.I1(select),
.I2(D1_i[2]),
.O(S0_o[2]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[30]_INST_0
(.I0(D0_i[30]),
.I1(select),
.I2(D1_i[30]),
.O(S0_o[30]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[3]_INST_0
(.I0(D0_i[3]),
.I1(select),
.I2(D1_i[3]),
.O(S0_o[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[4]_INST_0
(.I0(D0_i[4]),
.I1(select),
.I2(D1_i[4]),
.O(S0_o[4]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[5]_INST_0
(.I0(D0_i[5]),
.I1(select),
.I2(D1_i[5]),
.O(S0_o[5]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[6]_INST_0
(.I0(D0_i[6]),
.I1(select),
.I2(D1_i[6]),
.O(S0_o[6]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[7]_INST_0
(.I0(D0_i[7]),
.I1(select),
.I2(D1_i[7]),
.O(S0_o[7]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[8]_INST_0
(.I0(D0_i[8]),
.I1(select),
.I2(D1_i[8]),
.O(S0_o[8]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\S0_o[9]_INST_0
(.I0(D0_i[9]),
.I1(select),
.I2(D1_i[9]),
.O(S0_o[9]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[0]_INST_0
(.I0(D0_i[0]),
.I1(select),
.I2(D1_i[0]),
.O(S1_o[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[10]_INST_0
(.I0(D0_i[10]),
.I1(select),
.I2(D1_i[10]),
.O(S1_o[10]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[11]_INST_0
(.I0(D0_i[11]),
.I1(select),
.I2(D1_i[11]),
.O(S1_o[11]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[12]_INST_0
(.I0(D0_i[12]),
.I1(select),
.I2(D1_i[12]),
.O(S1_o[12]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[13]_INST_0
(.I0(D0_i[13]),
.I1(select),
.I2(D1_i[13]),
.O(S1_o[13]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[14]_INST_0
(.I0(D0_i[14]),
.I1(select),
.I2(D1_i[14]),
.O(S1_o[14]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[15]_INST_0
(.I0(D0_i[15]),
.I1(select),
.I2(D1_i[15]),
.O(S1_o[15]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[16]_INST_0
(.I0(D0_i[16]),
.I1(select),
.I2(D1_i[16]),
.O(S1_o[16]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[17]_INST_0
(.I0(D0_i[17]),
.I1(select),
.I2(D1_i[17]),
.O(S1_o[17]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[18]_INST_0
(.I0(D0_i[18]),
.I1(select),
.I2(D1_i[18]),
.O(S1_o[18]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[19]_INST_0
(.I0(D0_i[19]),
.I1(select),
.I2(D1_i[19]),
.O(S1_o[19]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[1]_INST_0
(.I0(D0_i[1]),
.I1(select),
.I2(D1_i[1]),
.O(S1_o[1]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[20]_INST_0
(.I0(D0_i[20]),
.I1(select),
.I2(D1_i[20]),
.O(S1_o[20]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[21]_INST_0
(.I0(D0_i[21]),
.I1(select),
.I2(D1_i[21]),
.O(S1_o[21]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[22]_INST_0
(.I0(D0_i[22]),
.I1(select),
.I2(D1_i[22]),
.O(S1_o[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[23]_INST_0
(.I0(D0_i[23]),
.I1(select),
.I2(D1_i[23]),
.O(S1_o[23]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[24]_INST_0
(.I0(D0_i[24]),
.I1(select),
.I2(D1_i[24]),
.O(S1_o[24]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[25]_INST_0
(.I0(D0_i[25]),
.I1(select),
.I2(D1_i[25]),
.O(S1_o[25]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[26]_INST_0
(.I0(D0_i[26]),
.I1(select),
.I2(D1_i[26]),
.O(S1_o[26]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[27]_INST_0
(.I0(D0_i[27]),
.I1(select),
.I2(D1_i[27]),
.O(S1_o[27]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[28]_INST_0
(.I0(D0_i[28]),
.I1(select),
.I2(D1_i[28]),
.O(S1_o[28]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[29]_INST_0
(.I0(D0_i[29]),
.I1(select),
.I2(D1_i[29]),
.O(S1_o[29]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[2]_INST_0
(.I0(D0_i[2]),
.I1(select),
.I2(D1_i[2]),
.O(S1_o[2]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[30]_INST_0
(.I0(D0_i[30]),
.I1(select),
.I2(D1_i[30]),
.O(S1_o[30]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[3]_INST_0
(.I0(D0_i[3]),
.I1(select),
.I2(D1_i[3]),
.O(S1_o[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[4]_INST_0
(.I0(D0_i[4]),
.I1(select),
.I2(D1_i[4]),
.O(S1_o[4]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[5]_INST_0
(.I0(D0_i[5]),
.I1(select),
.I2(D1_i[5]),
.O(S1_o[5]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[6]_INST_0
(.I0(D0_i[6]),
.I1(select),
.I2(D1_i[6]),
.O(S1_o[6]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[7]_INST_0
(.I0(D0_i[7]),
.I1(select),
.I2(D1_i[7]),
.O(S1_o[7]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[8]_INST_0
(.I0(D0_i[8]),
.I1(select),
.I2(D1_i[8]),
.O(S1_o[8]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hE2))
\S1_o[9]_INST_0
(.I0(D0_i[9]),
.I1(select),
.I2(D1_i[9]),
.O(S1_o[9]));
endmodule
(* W = "8" *)
module Multiplexer_AC
(ctrl,
D0,
D1,
S);
input ctrl;
input [7:0]D0;
input [7:0]D1;
output [7:0]S;
wire [7:0]D0;
wire [7:0]S;
wire ctrl;
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'hE))
\S[0]_INST_0
(.I0(ctrl),
.I1(D0[0]),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT2 #(
.INIT(4'hE))
\S[1]_INST_0
(.I0(ctrl),
.I1(D0[1]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'hE))
\S[2]_INST_0
(.I0(ctrl),
.I1(D0[2]),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT2 #(
.INIT(4'hE))
\S[3]_INST_0
(.I0(ctrl),
.I1(D0[3]),
.O(S[3]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'hE))
\S[4]_INST_0
(.I0(ctrl),
.I1(D0[4]),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT2 #(
.INIT(4'hE))
\S[5]_INST_0
(.I0(ctrl),
.I1(D0[5]),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'hE))
\S[6]_INST_0
(.I0(ctrl),
.I1(D0[6]),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT2 #(
.INIT(4'hE))
\S[7]_INST_0
(.I0(ctrl),
.I1(D0[7]),
.O(S[7]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "8" *)
module Multiplexer_AC__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [7:0]D0;
input [7:0]D1;
output [7:0]S;
wire [7:0]D0;
wire [7:0]D1;
wire [7:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1[0]),
.I1(ctrl),
.I2(D0[0]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\S[1]_INST_0
(.I0(D1[1]),
.I1(ctrl),
.I2(D0[1]),
.O(S[1]));
LUT3 #(
.INIT(8'hB8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl),
.I2(D0[2]),
.O(S[2]));
LUT3 #(
.INIT(8'hB8))
\S[3]_INST_0
(.I0(D1[3]),
.I1(ctrl),
.I2(D0[3]),
.O(S[3]));
LUT3 #(
.INIT(8'hB8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl),
.I2(D0[4]),
.O(S[4]));
LUT3 #(
.INIT(8'hB8))
\S[5]_INST_0
(.I0(D1[5]),
.I1(ctrl),
.I2(D0[5]),
.O(S[5]));
LUT3 #(
.INIT(8'hB8))
\S[6]_INST_0
(.I0(D1[6]),
.I1(ctrl),
.I2(D0[6]),
.O(S[6]));
LUT3 #(
.INIT(8'hB8))
\S[7]_INST_0
(.I0(D1[7]),
.I1(ctrl),
.I2(D0[7]),
.O(S[7]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "26" *)
module Multiplexer_AC__parameterized0
(ctrl,
D0,
D1,
S);
input ctrl;
input [25:0]D0;
input [25:0]D1;
output [25:0]S;
wire [25:0]D0;
wire [25:0]D1;
wire [25:0]S;
wire ctrl;
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT2 #(
.INIT(4'h8))
\S[0]_INST_0
(.I0(ctrl),
.I1(D1[0]),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\S[10]_INST_0
(.I0(D1[10]),
.I1(ctrl),
.I2(D0[10]),
.O(S[10]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hD8))
\S[11]_INST_0
(.I0(ctrl),
.I1(D1[11]),
.I2(D0[11]),
.O(S[11]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\S[12]_INST_0
(.I0(D1[12]),
.I1(ctrl),
.I2(D0[12]),
.O(S[12]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hD8))
\S[13]_INST_0
(.I0(ctrl),
.I1(D1[13]),
.I2(D0[13]),
.O(S[13]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\S[14]_INST_0
(.I0(D1[14]),
.I1(ctrl),
.I2(D0[14]),
.O(S[14]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hD8))
\S[15]_INST_0
(.I0(ctrl),
.I1(D1[15]),
.I2(D0[15]),
.O(S[15]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\S[16]_INST_0
(.I0(D1[16]),
.I1(ctrl),
.I2(D0[16]),
.O(S[16]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hD8))
\S[17]_INST_0
(.I0(ctrl),
.I1(D1[17]),
.I2(D0[17]),
.O(S[17]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\S[18]_INST_0
(.I0(D1[18]),
.I1(ctrl),
.I2(D0[18]),
.O(S[18]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hD8))
\S[19]_INST_0
(.I0(ctrl),
.I1(D1[19]),
.I2(D0[19]),
.O(S[19]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'h8))
\S[1]_INST_0
(.I0(ctrl),
.I1(D1[1]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\S[20]_INST_0
(.I0(D1[20]),
.I1(ctrl),
.I2(D0[20]),
.O(S[20]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hD8))
\S[21]_INST_0
(.I0(ctrl),
.I1(D1[21]),
.I2(D0[21]),
.O(S[21]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\S[22]_INST_0
(.I0(D1[22]),
.I1(ctrl),
.I2(D0[22]),
.O(S[22]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hD8))
\S[23]_INST_0
(.I0(ctrl),
.I1(D1[23]),
.I2(D0[23]),
.O(S[23]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\S[24]_INST_0
(.I0(D1[24]),
.I1(ctrl),
.I2(D0[24]),
.O(S[24]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT2 #(
.INIT(4'hD))
\S[25]_INST_0
(.I0(ctrl),
.I1(D1[25]),
.O(S[25]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl),
.I2(D0[2]),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hD8))
\S[3]_INST_0
(.I0(ctrl),
.I1(D1[3]),
.I2(D0[3]),
.O(S[3]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl),
.I2(D0[4]),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hD8))
\S[5]_INST_0
(.I0(ctrl),
.I1(D1[5]),
.I2(D0[5]),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\S[6]_INST_0
(.I0(D1[6]),
.I1(ctrl),
.I2(D0[6]),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hD8))
\S[7]_INST_0
(.I0(ctrl),
.I1(D1[7]),
.I2(D0[7]),
.O(S[7]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\S[8]_INST_0
(.I0(D1[8]),
.I1(ctrl),
.I2(D0[8]),
.O(S[8]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hD8))
\S[9]_INST_0
(.I0(ctrl),
.I1(D1[9]),
.I2(D0[9]),
.O(S[9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized10
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized100
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized101
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized102
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized103
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized104
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized105
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized106
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized107
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized108
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized109
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized11
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized110
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized111
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized112
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized113
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized114
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized115
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized116
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized117
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized118
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized119
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized12
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized120
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized121
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized122
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized123
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized124
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized125
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized126
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized127
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized128
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized129
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized13
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized130
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized131
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized131__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized132
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized132__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized133
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized133__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized134
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized134__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized135
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized135__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized136
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized136__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized137
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized137__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized138
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized138__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized139
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized139__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized14
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized140
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized140__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized141
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized141__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized142
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized142__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized143
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized143__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized144
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized144__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized145
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized145__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized146
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized146__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized147
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized147__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized148
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized148__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized149
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized149__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized15
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized150
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized150__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized151
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized151__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized152
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized152__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized153
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized153__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized154
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized154__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized155
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized155__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized156
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized156__1
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized157
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]S;
wire ctrl;
LUT2 #(
.INIT(4'h2))
\S[0]_INST_0
(.I0(D0),
.I1(ctrl),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "26" *)
module Multiplexer_AC__parameterized158
(ctrl,
D0,
D1,
S);
input ctrl;
input [25:0]D0;
input [25:0]D1;
output [25:0]S;
wire [25:0]D0;
wire [25:0]D1;
wire [25:0]S;
wire ctrl;
LUT2 #(
.INIT(4'h8))
\S[0]_INST_0
(.I0(ctrl),
.I1(D1[0]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\S[10]_INST_0
(.I0(D1[10]),
.I1(ctrl),
.I2(D0[10]),
.O(S[10]));
LUT3 #(
.INIT(8'hB8))
\S[11]_INST_0
(.I0(D1[11]),
.I1(ctrl),
.I2(D0[11]),
.O(S[11]));
LUT3 #(
.INIT(8'hB8))
\S[12]_INST_0
(.I0(D1[12]),
.I1(ctrl),
.I2(D0[12]),
.O(S[12]));
LUT3 #(
.INIT(8'hB8))
\S[13]_INST_0
(.I0(D1[13]),
.I1(ctrl),
.I2(D0[13]),
.O(S[13]));
LUT3 #(
.INIT(8'hB8))
\S[14]_INST_0
(.I0(D1[14]),
.I1(ctrl),
.I2(D0[14]),
.O(S[14]));
LUT3 #(
.INIT(8'hB8))
\S[15]_INST_0
(.I0(D1[15]),
.I1(ctrl),
.I2(D0[15]),
.O(S[15]));
LUT3 #(
.INIT(8'hB8))
\S[16]_INST_0
(.I0(D1[16]),
.I1(ctrl),
.I2(D0[16]),
.O(S[16]));
LUT3 #(
.INIT(8'hB8))
\S[17]_INST_0
(.I0(D1[17]),
.I1(ctrl),
.I2(D0[17]),
.O(S[17]));
LUT3 #(
.INIT(8'hB8))
\S[18]_INST_0
(.I0(D1[18]),
.I1(ctrl),
.I2(D0[18]),
.O(S[18]));
LUT3 #(
.INIT(8'hB8))
\S[19]_INST_0
(.I0(D1[19]),
.I1(ctrl),
.I2(D0[19]),
.O(S[19]));
LUT2 #(
.INIT(4'h8))
\S[1]_INST_0
(.I0(ctrl),
.I1(D1[1]),
.O(S[1]));
LUT3 #(
.INIT(8'hB8))
\S[20]_INST_0
(.I0(D1[20]),
.I1(ctrl),
.I2(D0[20]),
.O(S[20]));
LUT3 #(
.INIT(8'hB8))
\S[21]_INST_0
(.I0(D1[21]),
.I1(ctrl),
.I2(D0[21]),
.O(S[21]));
LUT3 #(
.INIT(8'hB8))
\S[22]_INST_0
(.I0(D1[22]),
.I1(ctrl),
.I2(D0[22]),
.O(S[22]));
LUT3 #(
.INIT(8'hB8))
\S[23]_INST_0
(.I0(D1[23]),
.I1(ctrl),
.I2(D0[23]),
.O(S[23]));
LUT3 #(
.INIT(8'hB8))
\S[24]_INST_0
(.I0(D1[24]),
.I1(ctrl),
.I2(D0[24]),
.O(S[24]));
LUT2 #(
.INIT(4'hB))
\S[25]_INST_0
(.I0(D1[25]),
.I1(ctrl),
.O(S[25]));
LUT3 #(
.INIT(8'hB8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl),
.I2(D0[2]),
.O(S[2]));
LUT3 #(
.INIT(8'hB8))
\S[3]_INST_0
(.I0(D1[3]),
.I1(ctrl),
.I2(D0[3]),
.O(S[3]));
LUT3 #(
.INIT(8'hB8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl),
.I2(D0[4]),
.O(S[4]));
LUT3 #(
.INIT(8'hB8))
\S[5]_INST_0
(.I0(D1[5]),
.I1(ctrl),
.I2(D0[5]),
.O(S[5]));
LUT3 #(
.INIT(8'hB8))
\S[6]_INST_0
(.I0(D1[6]),
.I1(ctrl),
.I2(D0[6]),
.O(S[6]));
LUT3 #(
.INIT(8'hB8))
\S[7]_INST_0
(.I0(D1[7]),
.I1(ctrl),
.I2(D0[7]),
.O(S[7]));
LUT3 #(
.INIT(8'hB8))
\S[8]_INST_0
(.I0(D1[8]),
.I1(ctrl),
.I2(D0[8]),
.O(S[8]));
LUT3 #(
.INIT(8'hB8))
\S[9]_INST_0
(.I0(D1[9]),
.I1(ctrl),
.I2(D0[9]),
.O(S[9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "26" *)
module Multiplexer_AC__parameterized159
(ctrl,
D0,
D1,
S);
input ctrl;
input [25:0]D0;
input [25:0]D1;
output [25:0]S;
wire [25:0]D0;
wire [25:0]S;
wire ctrl;
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'h4))
\S[0]_INST_0
(.I0(ctrl),
.I1(D0[0]),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT2 #(
.INIT(4'h4))
\S[10]_INST_0
(.I0(ctrl),
.I1(D0[10]),
.O(S[10]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT2 #(
.INIT(4'h2))
\S[11]_INST_0
(.I0(D0[11]),
.I1(ctrl),
.O(S[11]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT2 #(
.INIT(4'h4))
\S[12]_INST_0
(.I0(ctrl),
.I1(D0[12]),
.O(S[12]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT2 #(
.INIT(4'h2))
\S[13]_INST_0
(.I0(D0[13]),
.I1(ctrl),
.O(S[13]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT2 #(
.INIT(4'h4))
\S[14]_INST_0
(.I0(ctrl),
.I1(D0[14]),
.O(S[14]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT2 #(
.INIT(4'h2))
\S[15]_INST_0
(.I0(D0[15]),
.I1(ctrl),
.O(S[15]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT2 #(
.INIT(4'h4))
\S[16]_INST_0
(.I0(ctrl),
.I1(D0[16]),
.O(S[16]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT2 #(
.INIT(4'h2))
\S[17]_INST_0
(.I0(D0[17]),
.I1(ctrl),
.O(S[17]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT2 #(
.INIT(4'h4))
\S[18]_INST_0
(.I0(ctrl),
.I1(D0[18]),
.O(S[18]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT2 #(
.INIT(4'h2))
\S[19]_INST_0
(.I0(D0[19]),
.I1(ctrl),
.O(S[19]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'h2))
\S[1]_INST_0
(.I0(D0[1]),
.I1(ctrl),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT2 #(
.INIT(4'h4))
\S[20]_INST_0
(.I0(ctrl),
.I1(D0[20]),
.O(S[20]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT2 #(
.INIT(4'h2))
\S[21]_INST_0
(.I0(D0[21]),
.I1(ctrl),
.O(S[21]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h4))
\S[22]_INST_0
(.I0(ctrl),
.I1(D0[22]),
.O(S[22]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h2))
\S[23]_INST_0
(.I0(D0[23]),
.I1(ctrl),
.O(S[23]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT2 #(
.INIT(4'h4))
\S[24]_INST_0
(.I0(ctrl),
.I1(D0[24]),
.O(S[24]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT2 #(
.INIT(4'h2))
\S[25]_INST_0
(.I0(D0[25]),
.I1(ctrl),
.O(S[25]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'hE))
\S[2]_INST_0
(.I0(ctrl),
.I1(D0[2]),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT2 #(
.INIT(4'h2))
\S[3]_INST_0
(.I0(D0[3]),
.I1(ctrl),
.O(S[3]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT2 #(
.INIT(4'h4))
\S[4]_INST_0
(.I0(ctrl),
.I1(D0[4]),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT2 #(
.INIT(4'h2))
\S[5]_INST_0
(.I0(D0[5]),
.I1(ctrl),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h4))
\S[6]_INST_0
(.I0(ctrl),
.I1(D0[6]),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT2 #(
.INIT(4'h2))
\S[7]_INST_0
(.I0(D0[7]),
.I1(ctrl),
.O(S[7]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'h4))
\S[8]_INST_0
(.I0(ctrl),
.I1(D0[8]),
.O(S[8]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT2 #(
.INIT(4'h2))
\S[9]_INST_0
(.I0(D0[9]),
.I1(ctrl),
.O(S[9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized16
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "23" *)
module Multiplexer_AC__parameterized160
(ctrl,
D0,
D1,
S);
input ctrl;
input [22:0]D0;
input [22:0]D1;
output [22:0]S;
wire [22:0]D0;
wire [22:0]S;
wire ctrl;
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h2))
\S[0]_INST_0
(.I0(D0[0]),
.I1(ctrl),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h2))
\S[10]_INST_0
(.I0(D0[10]),
.I1(ctrl),
.O(S[10]));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h4))
\S[11]_INST_0
(.I0(ctrl),
.I1(D0[11]),
.O(S[11]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'h2))
\S[12]_INST_0
(.I0(D0[12]),
.I1(ctrl),
.O(S[12]));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT2 #(
.INIT(4'h4))
\S[13]_INST_0
(.I0(ctrl),
.I1(D0[13]),
.O(S[13]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'h2))
\S[14]_INST_0
(.I0(D0[14]),
.I1(ctrl),
.O(S[14]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT2 #(
.INIT(4'h4))
\S[15]_INST_0
(.I0(ctrl),
.I1(D0[15]),
.O(S[15]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT2 #(
.INIT(4'h2))
\S[16]_INST_0
(.I0(D0[16]),
.I1(ctrl),
.O(S[16]));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT2 #(
.INIT(4'h4))
\S[17]_INST_0
(.I0(ctrl),
.I1(D0[17]),
.O(S[17]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'h2))
\S[18]_INST_0
(.I0(D0[18]),
.I1(ctrl),
.O(S[18]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'h4))
\S[19]_INST_0
(.I0(ctrl),
.I1(D0[19]),
.O(S[19]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT2 #(
.INIT(4'h4))
\S[1]_INST_0
(.I0(ctrl),
.I1(D0[1]),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'h2))
\S[20]_INST_0
(.I0(D0[20]),
.I1(ctrl),
.O(S[20]));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT2 #(
.INIT(4'h4))
\S[21]_INST_0
(.I0(ctrl),
.I1(D0[21]),
.O(S[21]));
LUT2 #(
.INIT(4'h2))
\S[22]_INST_0
(.I0(D0[22]),
.I1(ctrl),
.O(S[22]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h2))
\S[2]_INST_0
(.I0(D0[2]),
.I1(ctrl),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h4))
\S[3]_INST_0
(.I0(ctrl),
.I1(D0[3]),
.O(S[3]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h2))
\S[4]_INST_0
(.I0(D0[4]),
.I1(ctrl),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT2 #(
.INIT(4'h4))
\S[5]_INST_0
(.I0(ctrl),
.I1(D0[5]),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h2))
\S[6]_INST_0
(.I0(D0[6]),
.I1(ctrl),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'h4))
\S[7]_INST_0
(.I0(ctrl),
.I1(D0[7]),
.O(S[7]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h2))
\S[8]_INST_0
(.I0(D0[8]),
.I1(ctrl),
.O(S[8]));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT2 #(
.INIT(4'h4))
\S[9]_INST_0
(.I0(ctrl),
.I1(D0[9]),
.O(S[9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized17
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized18
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized19
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized2
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized20
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized21
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized22
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized23
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized24
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized25
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized26
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized27
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized28
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized29
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized3
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized30
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized31
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized32
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized33
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized34
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized35
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized36
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized37
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized38
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized39
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized4
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized40
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized41
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized42
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized43
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized44
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized45
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized46
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized47
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized48
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized49
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized5
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized50
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized51
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized52
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized53
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized54
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized55
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized56
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized57
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized58
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized59
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized6
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized60
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized61
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized62
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized63
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized64
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized65
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized66
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized67
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized68
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized69
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized7
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized70
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized71
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized72
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized73
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized74
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized75
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized76
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized77
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized78
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized79
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized8
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized80
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized81
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized82
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized83
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized84
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized85
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized86
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized87
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized88
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized89
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized9
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized90
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized91
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized92
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized93
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized94
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized95
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized96
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized97
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized98
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *) (* W = "1" *)
module Multiplexer_AC__parameterized99
(ctrl,
D0,
D1,
S);
input ctrl;
input [0:0]D0;
input [0:0]D1;
output [0:0]S;
wire [0:0]D0;
wire [0:0]D1;
wire [0:0]S;
wire ctrl;
LUT3 #(
.INIT(8'hB8))
\S[0]_INST_0
(.I0(D1),
.I1(ctrl),
.I2(D0),
.O(S));
endmodule
(* W = "8" *)
module Mux_3x1
(ctrl,
D0,
D1,
D2,
S);
input [1:0]ctrl;
input [7:0]D0;
input [7:0]D1;
input [7:0]D2;
output [7:0]S;
wire [7:0]D0;
wire [7:0]D1;
wire [7:0]S;
wire [1:0]ctrl;
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT4 #(
.INIT(16'h3B38))
\S[0]_INST_0
(.I0(D1[0]),
.I1(ctrl[0]),
.I2(ctrl[1]),
.I3(D0[0]),
.O(S[0]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT4 #(
.INIT(16'h00B8))
\S[1]_INST_0
(.I0(D1[1]),
.I1(ctrl[0]),
.I2(D0[1]),
.I3(ctrl[1]),
.O(S[1]));
LUT4 #(
.INIT(16'h00B8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl[0]),
.I2(D0[2]),
.I3(ctrl[1]),
.O(S[2]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT4 #(
.INIT(16'h00B8))
\S[3]_INST_0
(.I0(D1[3]),
.I1(ctrl[0]),
.I2(D0[3]),
.I3(ctrl[1]),
.O(S[3]));
LUT4 #(
.INIT(16'h00B8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl[0]),
.I2(D0[4]),
.I3(ctrl[1]),
.O(S[4]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'h10))
\S[5]_INST_0
(.I0(ctrl[0]),
.I1(ctrl[1]),
.I2(D0[5]),
.O(S[5]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'h10))
\S[6]_INST_0
(.I0(ctrl[0]),
.I1(ctrl[1]),
.I2(D0[6]),
.O(S[6]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'h10))
\S[7]_INST_0
(.I0(ctrl[0]),
.I1(ctrl[1]),
.I2(D0[7]),
.O(S[7]));
endmodule
(* ORIG_REF_NAME = "Mux_3x1" *) (* W = "5" *)
module Mux_3x1__parameterized0
(ctrl,
D0,
D1,
D2,
S);
input [1:0]ctrl;
input [4:0]D0;
input [4:0]D1;
input [4:0]D2;
output [4:0]S;
wire [4:0]D0;
wire [4:0]D1;
wire [4:0]S;
wire [1:0]ctrl;
LUT4 #(
.INIT(16'h3B38))
\S[0]_INST_0
(.I0(D1[0]),
.I1(ctrl[0]),
.I2(ctrl[1]),
.I3(D0[0]),
.O(S[0]));
LUT4 #(
.INIT(16'h00B8))
\S[1]_INST_0
(.I0(D1[1]),
.I1(ctrl[0]),
.I2(D0[1]),
.I3(ctrl[1]),
.O(S[1]));
LUT4 #(
.INIT(16'h00B8))
\S[2]_INST_0
(.I0(D1[2]),
.I1(ctrl[0]),
.I2(D0[2]),
.I3(ctrl[1]),
.O(S[2]));
LUT4 #(
.INIT(16'h00B8))
\S[3]_INST_0
(.I0(D1[3]),
.I1(ctrl[0]),
.I2(D0[3]),
.I3(ctrl[1]),
.O(S[3]));
LUT4 #(
.INIT(16'h00B8))
\S[4]_INST_0
(.I0(D1[4]),
.I1(ctrl[0]),
.I2(D0[4]),
.I3(ctrl[1]),
.O(S[4]));
endmodule
(* ORIG_REF_NAME = "Mux_3x1" *) (* W = "1" *)
module Mux_3x1__parameterized1
(ctrl,
D0,
D1,
D2,
S);
input [1:0]ctrl;
input [0:0]D0;
input [0:0]D1;
input [0:0]D2;
output [0:0]S;
wire [0:0]D0;
wire [0:0]S;
wire [1:0]ctrl;
LUT3 #(
.INIT(8'h0E))
\S[0]_INST_0
(.I0(ctrl[0]),
.I1(D0),
.I2(ctrl[1]),
.O(S));
endmodule
(* EWR = "5" *) (* SWR = "26" *)
module Mux_Array
(clk,
rst,
load_i,
Shift_Value_i,
Data_i,
FSM_left_right_i,
bit_shift_i,
Data_o);
input clk;
input rst;
input load_i;
input [4:0]Shift_Value_i;
input [25:0]Data_i;
input FSM_left_right_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]\Data_array[0] ;
wire [25:0]\Data_array[1] ;
wire [25:0]\Data_array[2] ;
wire [25:0]\Data_array[3] ;
wire [25:0]\Data_array[4] ;
wire [25:0]\Data_array[5] ;
wire [25:0]\Data_array[6] ;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire FSM_left_right_i;
wire [4:0]Shift_Value_i;
wire bit_shift_i;
wire clk;
wire rst;
(* W = "26" *)
RegisterAdd__parameterized6 Mid_Reg
(.D(\Data_array[3] ),
.Q(\Data_array[4] ),
.clk(clk),
.load(1'b0),
.rst(rst));
(* SWR = "26" *)
Rotate_Mux_Array__1 first_rotate
(.Data_i(Data_i),
.Data_o(\Data_array[0] ),
.select_i(FSM_left_right_i));
(* LEVEL = "0" *)
(* SWR = "26" *)
shift_mux_array \genblk1[0].shift_mux_array
(.Data_i(\Data_array[0] ),
.Data_o(\Data_array[1] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[0]));
(* LEVEL = "1" *)
(* SWR = "26" *)
shift_mux_array__parameterized0 \genblk1[1].shift_mux_array
(.Data_i(\Data_array[1] ),
.Data_o(\Data_array[2] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[1]));
(* LEVEL = "2" *)
(* SWR = "26" *)
shift_mux_array__parameterized1 \genblk1[2].shift_mux_array
(.Data_i(\Data_array[2] ),
.Data_o(\Data_array[3] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[2]));
(* LEVEL = "3" *)
(* SWR = "26" *)
shift_mux_array__parameterized2 \genblk2[3].shift_mux_array
(.Data_i(\Data_array[4] ),
.Data_o(\Data_array[5] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[3]));
(* LEVEL = "4" *)
(* SWR = "26" *)
shift_mux_array__parameterized3 \genblk2[4].shift_mux_array
(.Data_i(\Data_array[5] ),
.Data_o(\Data_array[6] ),
.bit_shift_i(bit_shift_i),
.select_i(Shift_Value_i[4]));
(* SWR = "26" *)
Rotate_Mux_Array last_rotate
(.Data_i(\Data_array[6] ),
.Data_o(Data_o),
.select_i(FSM_left_right_i));
endmodule
(* W = "32" *)
module Oper_Start_In
(clk,
rst,
load_a_i,
load_b_i,
add_subt_i,
Data_X_i,
Data_Y_i,
DMP_o,
DmP_o,
zero_flag_o,
real_op_o,
sign_final_result_o);
input clk;
input rst;
input load_a_i;
input load_b_i;
input add_subt_i;
input [31:0]Data_X_i;
input [31:0]Data_Y_i;
output [30:0]DMP_o;
output [30:0]DmP_o;
output zero_flag_o;
output real_op_o;
output sign_final_result_o;
wire [30:0]DMP_o;
wire [31:0]Data_X_i;
wire [31:0]Data_Y_i;
wire [30:0]DmP_o;
wire add_subt_i;
wire clk;
wire eqXY;
wire gtXY;
wire intAS;
wire [31:0]intDX;
wire [31:0]intDY;
wire [30:0]intM;
wire [30:0]intm;
wire load_a_i;
wire load_b_i;
wire real_op_o;
wire rst;
wire sign_final_result_o;
wire sign_result;
wire zero_flag_o;
(* W = "1" *)
RegisterAdd__4 ASRegister
(.D(add_subt_i),
.Q(intAS),
.clk(clk),
.load(load_a_i),
.rst(rst));
(* W = "31" *)
RegisterAdd__parameterized3 MRegister
(.D(intM),
.Q(DMP_o),
.clk(clk),
.load(load_b_i),
.rst(rst));
(* W = "31" *)
Comparator Magnitude_Comparator
(.Data_X_i(intDX[30:0]),
.Data_Y_i(intDY[30:0]),
.eqXY_o(eqXY),
.gtXY_o(gtXY));
(* W = "31" *)
MultiplexTxT MuxXY
(.D0_i(intDX[30:0]),
.D1_i(intDY[30:0]),
.S0_o(intM),
.S1_o(intm),
.select(gtXY));
(* W = "32" *)
xor_tri Op_verification
(.A_i(intDX[31]),
.B_i(intDY[31]),
.C_i(intAS),
.Z_o(real_op_o));
(* W = "1" *)
RegisterAdd__5 SignRegister
(.D(sign_result),
.Q(sign_final_result_o),
.clk(clk),
.load(load_b_i),
.rst(rst));
(* W = "32" *)
RegisterAdd__parameterized1 XRegister
(.D(Data_X_i),
.Q(intDX),
.clk(clk),
.load(load_a_i),
.rst(rst));
(* W = "32" *)
RegisterAdd__parameterized2 YRegister
(.D(Data_Y_i),
.Q(intDY),
.clk(clk),
.load(load_a_i),
.rst(rst));
(* W = "31" *)
RegisterAdd__parameterized4 mRegister
(.D(intm),
.Q(DmP_o),
.clk(clk),
.load(load_b_i),
.rst(rst));
sgn_result result_sign_bit
(.Add_Subt_i(intAS),
.eqXY_i(eqXY),
.gtXY_i(gtXY),
.sgn_X_i(intDX[31]),
.sgn_Y_i(intDY[31]),
.sgn_result_o(sign_result));
LUT2 #(
.INIT(4'h8))
zero_flag_o_INST_0
(.I0(real_op_o),
.I1(eqXY),
.O(zero_flag_o));
endmodule
module Priority_Codec_32
(Data_Dec_i,
Data_Bin_o);
input [25:0]Data_Dec_i;
output [4:0]Data_Bin_o;
wire [4:0]Data_Bin_o;
wire \Data_Bin_o[0]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_3_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_4_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_5_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_6_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_7_n_0 ;
wire \Data_Bin_o[0]_INST_0_i_8_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_3_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_4_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_5_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_6_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_7_n_0 ;
wire \Data_Bin_o[1]_INST_0_i_8_n_0 ;
wire \Data_Bin_o[2]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[2]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_3_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_4_n_0 ;
wire \Data_Bin_o[3]_INST_0_i_5_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_1_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_2_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_3_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_4_n_0 ;
wire \Data_Bin_o[4]_INST_0_i_5_n_0 ;
wire [25:0]Data_Dec_i;
LUT6 #(
.INIT(64'hFE00FFFFFE00FE00))
\Data_Bin_o[0]_INST_0
(.I0(\Data_Bin_o[0]_INST_0_i_1_n_0 ),
.I1(\Data_Bin_o[0]_INST_0_i_2_n_0 ),
.I2(\Data_Bin_o[0]_INST_0_i_3_n_0 ),
.I3(\Data_Bin_o[0]_INST_0_i_4_n_0 ),
.I4(Data_Dec_i[24]),
.I5(Data_Dec_i[25]),
.O(Data_Bin_o[0]));
LUT5 #(
.INIT(32'h5DFFFFFF))
\Data_Bin_o[0]_INST_0_i_1
(.I0(Data_Dec_i[18]),
.I1(Data_Dec_i[17]),
.I2(Data_Dec_i[16]),
.I3(Data_Dec_i[22]),
.I4(Data_Dec_i[20]),
.O(\Data_Bin_o[0]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h5555444455554044))
\Data_Bin_o[0]_INST_0_i_2
(.I0(\Data_Bin_o[0]_INST_0_i_5_n_0 ),
.I1(Data_Dec_i[9]),
.I2(\Data_Bin_o[0]_INST_0_i_6_n_0 ),
.I3(Data_Dec_i[8]),
.I4(\Data_Bin_o[0]_INST_0_i_7_n_0 ),
.I5(\Data_Bin_o[0]_INST_0_i_8_n_0 ),
.O(\Data_Bin_o[0]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'h40))
\Data_Bin_o[0]_INST_0_i_3
(.I0(Data_Dec_i[14]),
.I1(Data_Dec_i[15]),
.I2(Data_Dec_i[17]),
.O(\Data_Bin_o[0]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'h8888088808080808))
\Data_Bin_o[0]_INST_0_i_4
(.I0(Data_Dec_i[23]),
.I1(Data_Dec_i[25]),
.I2(Data_Dec_i[22]),
.I3(Data_Dec_i[20]),
.I4(Data_Dec_i[19]),
.I5(Data_Dec_i[21]),
.O(\Data_Bin_o[0]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT5 #(
.INIT(32'h7FFF7F7F))
\Data_Bin_o[0]_INST_0_i_5
(.I0(Data_Dec_i[13]),
.I1(Data_Dec_i[17]),
.I2(Data_Dec_i[15]),
.I3(Data_Dec_i[11]),
.I4(Data_Dec_i[12]),
.O(\Data_Bin_o[0]_INST_0_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT4 #(
.INIT(16'h4F00))
\Data_Bin_o[0]_INST_0_i_6
(.I0(Data_Dec_i[4]),
.I1(Data_Dec_i[5]),
.I2(Data_Dec_i[6]),
.I3(Data_Dec_i[7]),
.O(\Data_Bin_o[0]_INST_0_i_6_n_0 ));
LUT3 #(
.INIT(8'h4F))
\Data_Bin_o[0]_INST_0_i_7
(.I0(Data_Dec_i[10]),
.I1(Data_Dec_i[11]),
.I2(Data_Dec_i[12]),
.O(\Data_Bin_o[0]_INST_0_i_7_n_0 ));
LUT6 #(
.INIT(64'h0080008080800080))
\Data_Bin_o[0]_INST_0_i_8
(.I0(Data_Dec_i[3]),
.I1(Data_Dec_i[5]),
.I2(Data_Dec_i[7]),
.I3(Data_Dec_i[2]),
.I4(Data_Dec_i[1]),
.I5(Data_Dec_i[0]),
.O(\Data_Bin_o[0]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFF800000000000))
\Data_Bin_o[1]_INST_0
(.I0(\Data_Bin_o[1]_INST_0_i_1_n_0 ),
.I1(Data_Dec_i[20]),
.I2(Data_Dec_i[21]),
.I3(\Data_Bin_o[1]_INST_0_i_2_n_0 ),
.I4(\Data_Bin_o[1]_INST_0_i_3_n_0 ),
.I5(\Data_Bin_o[1]_INST_0_i_4_n_0 ),
.O(Data_Bin_o[1]));
LUT6 #(
.INIT(64'hFFFFFFFFFF40FFFF))
\Data_Bin_o[1]_INST_0_i_1
(.I0(\Data_Bin_o[1]_INST_0_i_5_n_0 ),
.I1(\Data_Bin_o[4]_INST_0_i_4_n_0 ),
.I2(\Data_Bin_o[1]_INST_0_i_6_n_0 ),
.I3(\Data_Bin_o[1]_INST_0_i_7_n_0 ),
.I4(Data_Dec_i[15]),
.I5(\Data_Bin_o[1]_INST_0_i_8_n_0 ),
.O(\Data_Bin_o[1]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT4 #(
.INIT(16'h8FFF))
\Data_Bin_o[1]_INST_0_i_2
(.I0(Data_Dec_i[17]),
.I1(Data_Dec_i[16]),
.I2(Data_Dec_i[19]),
.I3(Data_Dec_i[18]),
.O(\Data_Bin_o[1]_INST_0_i_2_n_0 ));
LUT2 #(
.INIT(4'h7))
\Data_Bin_o[1]_INST_0_i_3
(.I0(Data_Dec_i[22]),
.I1(Data_Dec_i[23]),
.O(\Data_Bin_o[1]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT2 #(
.INIT(4'h8))
\Data_Bin_o[1]_INST_0_i_4
(.I0(Data_Dec_i[24]),
.I1(Data_Dec_i[25]),
.O(\Data_Bin_o[1]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT2 #(
.INIT(4'h7))
\Data_Bin_o[1]_INST_0_i_5
(.I0(Data_Dec_i[13]),
.I1(Data_Dec_i[12]),
.O(\Data_Bin_o[1]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h7000FFFFFFFFFFFF))
\Data_Bin_o[1]_INST_0_i_6
(.I0(Data_Dec_i[3]),
.I1(Data_Dec_i[2]),
.I2(Data_Dec_i[4]),
.I3(Data_Dec_i[5]),
.I4(Data_Dec_i[7]),
.I5(Data_Dec_i[6]),
.O(\Data_Bin_o[1]_INST_0_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT2 #(
.INIT(4'h7))
\Data_Bin_o[1]_INST_0_i_7
(.I0(Data_Dec_i[19]),
.I1(Data_Dec_i[18]),
.O(\Data_Bin_o[1]_INST_0_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT5 #(
.INIT(32'h0888FFFF))
\Data_Bin_o[1]_INST_0_i_8
(.I0(Data_Dec_i[12]),
.I1(Data_Dec_i[13]),
.I2(Data_Dec_i[10]),
.I3(Data_Dec_i[11]),
.I4(Data_Dec_i[14]),
.O(\Data_Bin_o[1]_INST_0_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFF00F800000000))
\Data_Bin_o[2]_INST_0
(.I0(\Data_Bin_o[2]_INST_0_i_1_n_0 ),
.I1(\Data_Bin_o[2]_INST_0_i_2_n_0 ),
.I2(\Data_Bin_o[3]_INST_0_i_4_n_0 ),
.I3(\Data_Bin_o[3]_INST_0_i_5_n_0 ),
.I4(\Data_Bin_o[4]_INST_0_i_3_n_0 ),
.I5(\Data_Bin_o[3]_INST_0_i_1_n_0 ),
.O(Data_Bin_o[2]));
LUT6 #(
.INIT(64'h5DFFFFFFFFFFFFFF))
\Data_Bin_o[2]_INST_0_i_1
(.I0(Data_Dec_i[5]),
.I1(Data_Dec_i[1]),
.I2(Data_Dec_i[0]),
.I3(Data_Dec_i[4]),
.I4(Data_Dec_i[3]),
.I5(Data_Dec_i[2]),
.O(\Data_Bin_o[2]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT4 #(
.INIT(16'h8000))
\Data_Bin_o[2]_INST_0_i_2
(.I0(Data_Dec_i[7]),
.I1(Data_Dec_i[6]),
.I2(Data_Dec_i[9]),
.I3(Data_Dec_i[8]),
.O(\Data_Bin_o[2]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'h4444444444440040))
\Data_Bin_o[3]_INST_0
(.I0(\Data_Bin_o[4]_INST_0_i_3_n_0 ),
.I1(\Data_Bin_o[3]_INST_0_i_1_n_0 ),
.I2(\Data_Bin_o[3]_INST_0_i_2_n_0 ),
.I3(\Data_Bin_o[3]_INST_0_i_3_n_0 ),
.I4(\Data_Bin_o[3]_INST_0_i_4_n_0 ),
.I5(\Data_Bin_o[3]_INST_0_i_5_n_0 ),
.O(Data_Bin_o[3]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT4 #(
.INIT(16'h8000))
\Data_Bin_o[3]_INST_0_i_1
(.I0(Data_Dec_i[24]),
.I1(Data_Dec_i[25]),
.I2(Data_Dec_i[23]),
.I3(Data_Dec_i[22]),
.O(\Data_Bin_o[3]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0080000000000000))
\Data_Bin_o[3]_INST_0_i_2
(.I0(Data_Dec_i[5]),
.I1(Data_Dec_i[7]),
.I2(Data_Dec_i[6]),
.I3(Data_Dec_i[1]),
.I4(Data_Dec_i[9]),
.I5(Data_Dec_i[8]),
.O(\Data_Bin_o[3]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h7F))
\Data_Bin_o[3]_INST_0_i_3
(.I0(Data_Dec_i[2]),
.I1(Data_Dec_i[3]),
.I2(Data_Dec_i[4]),
.O(\Data_Bin_o[3]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT4 #(
.INIT(16'h7FFF))
\Data_Bin_o[3]_INST_0_i_4
(.I0(Data_Dec_i[12]),
.I1(Data_Dec_i[13]),
.I2(Data_Dec_i[10]),
.I3(Data_Dec_i[11]),
.O(\Data_Bin_o[3]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT4 #(
.INIT(16'h7FFF))
\Data_Bin_o[3]_INST_0_i_5
(.I0(Data_Dec_i[14]),
.I1(Data_Dec_i[16]),
.I2(Data_Dec_i[15]),
.I3(Data_Dec_i[17]),
.O(\Data_Bin_o[3]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'h0000000020000000))
\Data_Bin_o[4]_INST_0
(.I0(\Data_Bin_o[4]_INST_0_i_1_n_0 ),
.I1(\Data_Bin_o[4]_INST_0_i_2_n_0 ),
.I2(Data_Dec_i[24]),
.I3(Data_Dec_i[22]),
.I4(Data_Dec_i[23]),
.I5(\Data_Bin_o[4]_INST_0_i_3_n_0 ),
.O(Data_Bin_o[4]));
LUT6 #(
.INIT(64'h0000000080000000))
\Data_Bin_o[4]_INST_0_i_1
(.I0(Data_Dec_i[11]),
.I1(Data_Dec_i[10]),
.I2(Data_Dec_i[13]),
.I3(Data_Dec_i[12]),
.I4(Data_Dec_i[25]),
.I5(\Data_Bin_o[3]_INST_0_i_5_n_0 ),
.O(\Data_Bin_o[4]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
\Data_Bin_o[4]_INST_0_i_2
(.I0(Data_Dec_i[6]),
.I1(Data_Dec_i[1]),
.I2(Data_Dec_i[0]),
.I3(\Data_Bin_o[4]_INST_0_i_4_n_0 ),
.I4(\Data_Bin_o[4]_INST_0_i_5_n_0 ),
.I5(\Data_Bin_o[3]_INST_0_i_3_n_0 ),
.O(\Data_Bin_o[4]_INST_0_i_2_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\Data_Bin_o[4]_INST_0_i_3
(.I0(Data_Dec_i[21]),
.I1(Data_Dec_i[18]),
.I2(Data_Dec_i[19]),
.I3(Data_Dec_i[20]),
.O(\Data_Bin_o[4]_INST_0_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT2 #(
.INIT(4'h8))
\Data_Bin_o[4]_INST_0_i_4
(.I0(Data_Dec_i[9]),
.I1(Data_Dec_i[8]),
.O(\Data_Bin_o[4]_INST_0_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h8))
\Data_Bin_o[4]_INST_0_i_5
(.I0(Data_Dec_i[5]),
.I1(Data_Dec_i[7]),
.O(\Data_Bin_o[4]_INST_0_i_5_n_0 ));
endmodule
(* W = "1" *)
module RegisterAdd
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__1
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]Q;
wire \Q[0]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
LUT2 #(
.INIT(4'hE))
\Q[0]_i_1
(.I0(load),
.I1(Q),
.O(\Q[0]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__2
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]Q;
wire \Q[0]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
LUT2 #(
.INIT(4'hE))
\Q[0]_i_1
(.I0(load),
.I1(Q),
.O(\Q[0]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__3
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]Q;
wire \Q[0]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
LUT2 #(
.INIT(4'hE))
\Q[0]_i_1
(.I0(load),
.I1(Q),
.O(\Q[0]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__4
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__5
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__6
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "1" *)
module RegisterAdd__7
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [0:0]D;
output [0:0]Q;
wire [0:0]D;
wire [0:0]Q;
wire \Q[0]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
LUT3 #(
.INIT(8'hB8))
\Q[0]_i_1
(.I0(D),
.I1(load),
.I2(Q),
.O(\Q[0]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "2" *)
module RegisterAdd__parameterized0
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [1:0]D;
output [1:0]Q;
wire [1:0]D;
wire [1:0]Q;
wire \Q[0]_i_1_n_0 ;
wire \Q[1]_i_1_n_0 ;
wire clk;
wire load;
wire rst;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hD8))
\Q[0]_i_1
(.I0(load),
.I1(D[0]),
.I2(Q[0]),
.O(\Q[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1
(.I0(D[1]),
.I1(load),
.I2(Q[1]),
.O(\Q[1]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[0]_i_1_n_0 ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(\Q[1]_i_1_n_0 ),
.Q(Q[1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "32" *)
module RegisterAdd__parameterized1
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [31:0]D;
output [31:0]Q;
wire [31:0]D;
wire [31:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "32" *)
module RegisterAdd__parameterized10
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [31:0]D;
output [31:0]Q;
wire [31:0]D;
wire [31:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "32" *)
module RegisterAdd__parameterized2
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [31:0]D;
output [31:0]Q;
wire [31:0]D;
wire [31:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "31" *)
module RegisterAdd__parameterized3
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [30:0]D;
output [30:0]Q;
wire [30:0]D;
wire [30:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "31" *)
module RegisterAdd__parameterized4
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [30:0]D;
output [30:0]Q;
wire [30:0]D;
wire [30:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "8" *)
module RegisterAdd__parameterized5
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [7:0]D;
output [7:0]Q;
wire [7:0]D;
wire [7:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "26" *)
module RegisterAdd__parameterized6
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [25:0]D;
output [25:0]Q;
wire [25:0]D;
wire [25:0]Q;
wire clk;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(1'b1),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "26" *)
module RegisterAdd__parameterized7
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [25:0]D;
output [25:0]Q;
wire [25:0]D;
wire [25:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "26" *)
module RegisterAdd__parameterized8
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [25:0]D;
output [25:0]Q;
wire [25:0]D;
wire [25:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *) (* W = "5" *)
module RegisterAdd__parameterized9
(clk,
rst,
load,
D,
Q);
input clk;
input rst;
input load;
input [4:0]D;
output [4:0]Q;
wire [4:0]D;
wire [4:0]Q;
wire clk;
wire load;
wire rst;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(clk),
.CE(load),
.CLR(rst),
.D(D[4]),
.Q(Q[4]));
endmodule
(* SWR = "26" *)
module Rotate_Mux_Array
(Data_i,
select_i,
Data_o);
input [25:0]Data_i;
input select_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized131 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[25]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized141 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[15]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized142 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[14]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized143 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[13]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized144 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[12]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized145 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[11]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized146 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[10]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized147 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[9]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized148 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[8]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized149 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[7]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized150 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[6]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized132 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[24]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized151 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[5]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized152 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[4]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized153 \genblk1[22].genblk1_0.rotate_mux
(.D0(Data_i[22]),
.D1(Data_i[3]),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized154 \genblk1[23].genblk1_0.rotate_mux
(.D0(Data_i[23]),
.D1(Data_i[2]),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized155 \genblk1[24].genblk1_0.rotate_mux
(.D0(Data_i[24]),
.D1(Data_i[1]),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized156 \genblk1[25].genblk1_0.rotate_mux
(.D0(Data_i[25]),
.D1(Data_i[0]),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized133 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[23]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized134 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[22]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized135 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[21]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized136 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[20]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized137 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[19]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized138 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[18]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized139 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[17]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized140 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[16]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* ORIG_REF_NAME = "Rotate_Mux_Array" *) (* SWR = "26" *)
module Rotate_Mux_Array__1
(Data_i,
select_i,
Data_o);
input [25:0]Data_i;
input select_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized131__1 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[25]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized141__1 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[15]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized142__1 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[14]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized143__1 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[13]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized144__1 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[12]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized145__1 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[11]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized146__1 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[10]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized147__1 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[9]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized148__1 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[8]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized149__1 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[7]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized150__1 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[6]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized132__1 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[24]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized151__1 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[5]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized152__1 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[4]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized153__1 \genblk1[22].genblk1_0.rotate_mux
(.D0(Data_i[22]),
.D1(Data_i[3]),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized154__1 \genblk1[23].genblk1_0.rotate_mux
(.D0(Data_i[23]),
.D1(Data_i[2]),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized155__1 \genblk1[24].genblk1_0.rotate_mux
(.D0(Data_i[24]),
.D1(Data_i[1]),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized156__1 \genblk1[25].genblk1_0.rotate_mux
(.D0(Data_i[25]),
.D1(Data_i[0]),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized133__1 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[23]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized134__1 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[22]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized135__1 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[21]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized136__1 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[20]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized137__1 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[19]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized138__1 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[18]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized139__1 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[17]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized140__1 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[16]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
module Round_Sgf_Dec
(Data_i,
Round_Type_i,
Sign_Result_i,
Round_Flag_o);
input [1:0]Data_i;
input [1:0]Round_Type_i;
input Sign_Result_i;
output Round_Flag_o;
wire [1:0]Data_i;
wire Round_Flag_o;
wire [1:0]Round_Type_i;
wire Sign_Result_i;
LUT5 #(
.INIT(32'h00E00E00))
Round_Flag_o_INST_0
(.I0(Data_i[1]),
.I1(Data_i[0]),
.I2(Sign_Result_i),
.I3(Round_Type_i[1]),
.I4(Round_Type_i[0]),
.O(Round_Flag_o));
endmodule
(* EW = "8" *) (* SW = "23" *) (* W = "32" *)
module Tenth_Phase
(clk,
rst,
load_i,
sel_a_i,
sel_b_i,
sign_i,
exp_ieee_i,
sgf_ieee_i,
final_result_ieee_o);
input clk;
input rst;
input load_i;
input sel_a_i;
input sel_b_i;
input sign_i;
input [7:0]exp_ieee_i;
input [22:0]sgf_ieee_i;
output [31:0]final_result_ieee_o;
wire [7:0]Exp_S_mux;
wire [22:0]Sgf_S_mux;
wire Sign_S_mux;
wire clk;
wire [7:0]exp_ieee_i;
wire [31:0]final_result_ieee_o;
wire load_i;
wire overunder;
wire rst;
wire sel_a_i;
wire sel_b_i;
wire [22:0]sgf_ieee_i;
wire sign_i;
(* W = "8" *)
Multiplexer_AC Exp_Mux
(.D0(exp_ieee_i),
.D1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(Exp_S_mux),
.ctrl(overunder));
LUT2 #(
.INIT(4'hE))
Exp_Mux_i_1
(.I0(sel_a_i),
.I1(sel_b_i),
.O(overunder));
(* W = "32" *)
RegisterAdd__parameterized10 Final_Result_IEEE
(.D({Sign_S_mux,Exp_S_mux,Sgf_S_mux}),
.Q(final_result_ieee_o),
.clk(clk),
.load(load_i),
.rst(rst));
(* W = "23" *)
Multiplexer_AC__parameterized160 Sgf_Mux
(.D0(sgf_ieee_i),
.D1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S(Sgf_S_mux),
.ctrl(overunder));
(* W = "1" *)
Mux_3x1__parameterized1 Sign_Mux
(.D0(sign_i),
.D1(1'b0),
.D2(1'b0),
.S(Sign_S_mux),
.ctrl({sel_a_i,sel_b_i}));
endmodule
(* W = "8" *)
module add_sub_carry_out
(op_mode,
Data_A,
Data_B,
Data_S);
input op_mode;
input [7:0]Data_A;
input [7:0]Data_B;
output [8:0]Data_S;
wire [7:0]Data_A;
wire [7:0]Data_B;
wire [8:0]Data_S;
wire \Data_S[0]_INST_0_i_1_n_0 ;
wire \Data_S[0]_INST_0_i_2_n_0 ;
wire \Data_S[0]_INST_0_i_3_n_0 ;
wire \Data_S[0]_INST_0_n_0 ;
wire \Data_S[0]_INST_0_n_1 ;
wire \Data_S[0]_INST_0_n_2 ;
wire \Data_S[0]_INST_0_n_3 ;
wire \Data_S[4]_INST_0_i_1_n_0 ;
wire \Data_S[4]_INST_0_i_2_n_0 ;
wire \Data_S[4]_INST_0_i_3_n_0 ;
wire \Data_S[4]_INST_0_i_4_n_0 ;
wire \Data_S[4]_INST_0_n_0 ;
wire \Data_S[4]_INST_0_n_1 ;
wire \Data_S[4]_INST_0_n_2 ;
wire \Data_S[4]_INST_0_n_3 ;
wire op_mode;
wire [3:0]\NLW_Data_S[8]_INST_0_CO_UNCONNECTED ;
wire [3:1]\NLW_Data_S[8]_INST_0_O_UNCONNECTED ;
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[0]_INST_0
(.CI(1'b0),
.CO({\Data_S[0]_INST_0_n_0 ,\Data_S[0]_INST_0_n_1 ,\Data_S[0]_INST_0_n_2 ,\Data_S[0]_INST_0_n_3 }),
.CYINIT(Data_A[0]),
.DI({Data_A[3:1],op_mode}),
.O(Data_S[3:0]),
.S({\Data_S[0]_INST_0_i_1_n_0 ,\Data_S[0]_INST_0_i_2_n_0 ,\Data_S[0]_INST_0_i_3_n_0 ,Data_B[0]}));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_1
(.I0(Data_B[3]),
.I1(op_mode),
.I2(Data_A[3]),
.O(\Data_S[0]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_2
(.I0(Data_B[2]),
.I1(op_mode),
.I2(Data_A[2]),
.O(\Data_S[0]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_3
(.I0(Data_B[1]),
.I1(op_mode),
.I2(Data_A[1]),
.O(\Data_S[0]_INST_0_i_3_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[4]_INST_0
(.CI(\Data_S[0]_INST_0_n_0 ),
.CO({\Data_S[4]_INST_0_n_0 ,\Data_S[4]_INST_0_n_1 ,\Data_S[4]_INST_0_n_2 ,\Data_S[4]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[7:4]),
.O(Data_S[7:4]),
.S({\Data_S[4]_INST_0_i_1_n_0 ,\Data_S[4]_INST_0_i_2_n_0 ,\Data_S[4]_INST_0_i_3_n_0 ,\Data_S[4]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_1
(.I0(Data_B[7]),
.I1(op_mode),
.I2(Data_A[7]),
.O(\Data_S[4]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_2
(.I0(Data_B[6]),
.I1(op_mode),
.I2(Data_A[6]),
.O(\Data_S[4]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_3
(.I0(Data_B[5]),
.I1(op_mode),
.I2(Data_A[5]),
.O(\Data_S[4]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_4
(.I0(Data_B[4]),
.I1(op_mode),
.I2(Data_A[4]),
.O(\Data_S[4]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[8]_INST_0
(.CI(\Data_S[4]_INST_0_n_0 ),
.CO(\NLW_Data_S[8]_INST_0_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Data_S[8]_INST_0_O_UNCONNECTED [3:1],Data_S[8]}),
.S({1'b0,1'b0,1'b0,op_mode}));
endmodule
(* ORIG_REF_NAME = "add_sub_carry_out" *) (* W = "26" *)
module add_sub_carry_out__parameterized0
(op_mode,
Data_A,
Data_B,
Data_S);
input op_mode;
input [25:0]Data_A;
input [25:0]Data_B;
output [26:0]Data_S;
wire [25:0]Data_A;
wire [25:0]Data_B;
wire [26:0]Data_S;
wire \Data_S[0]_INST_0_i_1_n_0 ;
wire \Data_S[0]_INST_0_i_2_n_0 ;
wire \Data_S[0]_INST_0_i_3_n_0 ;
wire \Data_S[0]_INST_0_n_0 ;
wire \Data_S[0]_INST_0_n_1 ;
wire \Data_S[0]_INST_0_n_2 ;
wire \Data_S[0]_INST_0_n_3 ;
wire \Data_S[12]_INST_0_i_1_n_0 ;
wire \Data_S[12]_INST_0_i_2_n_0 ;
wire \Data_S[12]_INST_0_i_3_n_0 ;
wire \Data_S[12]_INST_0_i_4_n_0 ;
wire \Data_S[12]_INST_0_n_0 ;
wire \Data_S[12]_INST_0_n_1 ;
wire \Data_S[12]_INST_0_n_2 ;
wire \Data_S[12]_INST_0_n_3 ;
wire \Data_S[16]_INST_0_i_1_n_0 ;
wire \Data_S[16]_INST_0_i_2_n_0 ;
wire \Data_S[16]_INST_0_i_3_n_0 ;
wire \Data_S[16]_INST_0_i_4_n_0 ;
wire \Data_S[16]_INST_0_n_0 ;
wire \Data_S[16]_INST_0_n_1 ;
wire \Data_S[16]_INST_0_n_2 ;
wire \Data_S[16]_INST_0_n_3 ;
wire \Data_S[20]_INST_0_i_1_n_0 ;
wire \Data_S[20]_INST_0_i_2_n_0 ;
wire \Data_S[20]_INST_0_i_3_n_0 ;
wire \Data_S[20]_INST_0_i_4_n_0 ;
wire \Data_S[20]_INST_0_n_0 ;
wire \Data_S[20]_INST_0_n_1 ;
wire \Data_S[20]_INST_0_n_2 ;
wire \Data_S[20]_INST_0_n_3 ;
wire \Data_S[24]_INST_0_i_2_n_0 ;
wire \Data_S[24]_INST_0_i_3_n_0 ;
wire \Data_S[24]_INST_0_n_2 ;
wire \Data_S[24]_INST_0_n_3 ;
wire \Data_S[4]_INST_0_i_1_n_0 ;
wire \Data_S[4]_INST_0_i_2_n_0 ;
wire \Data_S[4]_INST_0_i_3_n_0 ;
wire \Data_S[4]_INST_0_i_4_n_0 ;
wire \Data_S[4]_INST_0_n_0 ;
wire \Data_S[4]_INST_0_n_1 ;
wire \Data_S[4]_INST_0_n_2 ;
wire \Data_S[4]_INST_0_n_3 ;
wire \Data_S[8]_INST_0_i_1_n_0 ;
wire \Data_S[8]_INST_0_i_2_n_0 ;
wire \Data_S[8]_INST_0_i_3_n_0 ;
wire \Data_S[8]_INST_0_i_4_n_0 ;
wire \Data_S[8]_INST_0_n_0 ;
wire \Data_S[8]_INST_0_n_1 ;
wire \Data_S[8]_INST_0_n_2 ;
wire \Data_S[8]_INST_0_n_3 ;
wire op_mode;
wire [3:2]\NLW_Data_S[24]_INST_0_CO_UNCONNECTED ;
wire [3:3]\NLW_Data_S[24]_INST_0_O_UNCONNECTED ;
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[0]_INST_0
(.CI(1'b0),
.CO({\Data_S[0]_INST_0_n_0 ,\Data_S[0]_INST_0_n_1 ,\Data_S[0]_INST_0_n_2 ,\Data_S[0]_INST_0_n_3 }),
.CYINIT(Data_A[0]),
.DI({Data_A[3:1],op_mode}),
.O(Data_S[3:0]),
.S({\Data_S[0]_INST_0_i_1_n_0 ,\Data_S[0]_INST_0_i_2_n_0 ,\Data_S[0]_INST_0_i_3_n_0 ,Data_B[0]}));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_1
(.I0(Data_B[3]),
.I1(op_mode),
.I2(Data_A[3]),
.O(\Data_S[0]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_2
(.I0(Data_B[2]),
.I1(op_mode),
.I2(Data_A[2]),
.O(\Data_S[0]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[0]_INST_0_i_3
(.I0(Data_B[1]),
.I1(op_mode),
.I2(Data_A[1]),
.O(\Data_S[0]_INST_0_i_3_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[12]_INST_0
(.CI(\Data_S[8]_INST_0_n_0 ),
.CO({\Data_S[12]_INST_0_n_0 ,\Data_S[12]_INST_0_n_1 ,\Data_S[12]_INST_0_n_2 ,\Data_S[12]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[15:12]),
.O(Data_S[15:12]),
.S({\Data_S[12]_INST_0_i_1_n_0 ,\Data_S[12]_INST_0_i_2_n_0 ,\Data_S[12]_INST_0_i_3_n_0 ,\Data_S[12]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[12]_INST_0_i_1
(.I0(Data_B[15]),
.I1(op_mode),
.I2(Data_A[15]),
.O(\Data_S[12]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[12]_INST_0_i_2
(.I0(Data_B[14]),
.I1(op_mode),
.I2(Data_A[14]),
.O(\Data_S[12]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[12]_INST_0_i_3
(.I0(Data_B[13]),
.I1(op_mode),
.I2(Data_A[13]),
.O(\Data_S[12]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[12]_INST_0_i_4
(.I0(Data_B[12]),
.I1(op_mode),
.I2(Data_A[12]),
.O(\Data_S[12]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[16]_INST_0
(.CI(\Data_S[12]_INST_0_n_0 ),
.CO({\Data_S[16]_INST_0_n_0 ,\Data_S[16]_INST_0_n_1 ,\Data_S[16]_INST_0_n_2 ,\Data_S[16]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[19:16]),
.O(Data_S[19:16]),
.S({\Data_S[16]_INST_0_i_1_n_0 ,\Data_S[16]_INST_0_i_2_n_0 ,\Data_S[16]_INST_0_i_3_n_0 ,\Data_S[16]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[16]_INST_0_i_1
(.I0(Data_B[19]),
.I1(op_mode),
.I2(Data_A[19]),
.O(\Data_S[16]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[16]_INST_0_i_2
(.I0(Data_B[18]),
.I1(op_mode),
.I2(Data_A[18]),
.O(\Data_S[16]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[16]_INST_0_i_3
(.I0(Data_B[17]),
.I1(op_mode),
.I2(Data_A[17]),
.O(\Data_S[16]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[16]_INST_0_i_4
(.I0(Data_B[16]),
.I1(op_mode),
.I2(Data_A[16]),
.O(\Data_S[16]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[20]_INST_0
(.CI(\Data_S[16]_INST_0_n_0 ),
.CO({\Data_S[20]_INST_0_n_0 ,\Data_S[20]_INST_0_n_1 ,\Data_S[20]_INST_0_n_2 ,\Data_S[20]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[23:20]),
.O(Data_S[23:20]),
.S({\Data_S[20]_INST_0_i_1_n_0 ,\Data_S[20]_INST_0_i_2_n_0 ,\Data_S[20]_INST_0_i_3_n_0 ,\Data_S[20]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[20]_INST_0_i_1
(.I0(Data_B[23]),
.I1(op_mode),
.I2(Data_A[23]),
.O(\Data_S[20]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[20]_INST_0_i_2
(.I0(Data_B[22]),
.I1(op_mode),
.I2(Data_A[22]),
.O(\Data_S[20]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[20]_INST_0_i_3
(.I0(Data_B[21]),
.I1(op_mode),
.I2(Data_A[21]),
.O(\Data_S[20]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[20]_INST_0_i_4
(.I0(Data_B[20]),
.I1(op_mode),
.I2(Data_A[20]),
.O(\Data_S[20]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[24]_INST_0
(.CI(\Data_S[20]_INST_0_n_0 ),
.CO({\NLW_Data_S[24]_INST_0_CO_UNCONNECTED [3:2],\Data_S[24]_INST_0_n_2 ,\Data_S[24]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,Data_A[25:24]}),
.O({\NLW_Data_S[24]_INST_0_O_UNCONNECTED [3],Data_S[26:24]}),
.S({1'b0,op_mode,\Data_S[24]_INST_0_i_2_n_0 ,\Data_S[24]_INST_0_i_3_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[24]_INST_0_i_2
(.I0(Data_B[25]),
.I1(op_mode),
.I2(Data_A[25]),
.O(\Data_S[24]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[24]_INST_0_i_3
(.I0(Data_B[24]),
.I1(op_mode),
.I2(Data_A[24]),
.O(\Data_S[24]_INST_0_i_3_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[4]_INST_0
(.CI(\Data_S[0]_INST_0_n_0 ),
.CO({\Data_S[4]_INST_0_n_0 ,\Data_S[4]_INST_0_n_1 ,\Data_S[4]_INST_0_n_2 ,\Data_S[4]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[7:4]),
.O(Data_S[7:4]),
.S({\Data_S[4]_INST_0_i_1_n_0 ,\Data_S[4]_INST_0_i_2_n_0 ,\Data_S[4]_INST_0_i_3_n_0 ,\Data_S[4]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_1
(.I0(Data_B[7]),
.I1(op_mode),
.I2(Data_A[7]),
.O(\Data_S[4]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_2
(.I0(Data_B[6]),
.I1(op_mode),
.I2(Data_A[6]),
.O(\Data_S[4]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_3
(.I0(Data_B[5]),
.I1(op_mode),
.I2(Data_A[5]),
.O(\Data_S[4]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[4]_INST_0_i_4
(.I0(Data_B[4]),
.I1(op_mode),
.I2(Data_A[4]),
.O(\Data_S[4]_INST_0_i_4_n_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Data_S[8]_INST_0
(.CI(\Data_S[4]_INST_0_n_0 ),
.CO({\Data_S[8]_INST_0_n_0 ,\Data_S[8]_INST_0_n_1 ,\Data_S[8]_INST_0_n_2 ,\Data_S[8]_INST_0_n_3 }),
.CYINIT(1'b0),
.DI(Data_A[11:8]),
.O(Data_S[11:8]),
.S({\Data_S[8]_INST_0_i_1_n_0 ,\Data_S[8]_INST_0_i_2_n_0 ,\Data_S[8]_INST_0_i_3_n_0 ,\Data_S[8]_INST_0_i_4_n_0 }));
LUT3 #(
.INIT(8'h96))
\Data_S[8]_INST_0_i_1
(.I0(Data_B[11]),
.I1(op_mode),
.I2(Data_A[11]),
.O(\Data_S[8]_INST_0_i_1_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[8]_INST_0_i_2
(.I0(Data_B[10]),
.I1(op_mode),
.I2(Data_A[10]),
.O(\Data_S[8]_INST_0_i_2_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[8]_INST_0_i_3
(.I0(Data_B[9]),
.I1(op_mode),
.I2(Data_A[9]),
.O(\Data_S[8]_INST_0_i_3_n_0 ));
LUT3 #(
.INIT(8'h96))
\Data_S[8]_INST_0_i_4
(.I0(Data_B[8]),
.I1(op_mode),
.I2(Data_A[8]),
.O(\Data_S[8]_INST_0_i_4_n_0 ));
endmodule
module sgn_result
(Add_Subt_i,
sgn_X_i,
sgn_Y_i,
gtXY_i,
eqXY_i,
sgn_result_o);
input Add_Subt_i;
input sgn_X_i;
input sgn_Y_i;
input gtXY_i;
input eqXY_i;
output sgn_result_o;
wire Add_Subt_i;
wire eqXY_i;
wire gtXY_i;
wire sgn_X_i;
wire sgn_Y_i;
wire sgn_result_o;
LUT5 #(
.INIT(32'hFF3C0014))
sgn_result_o_INST_0
(.I0(eqXY_i),
.I1(sgn_Y_i),
.I2(Add_Subt_i),
.I3(gtXY_i),
.I4(sgn_X_i),
.O(sgn_result_o));
endmodule
(* LEVEL = "0" *) (* SWR = "26" *)
module shift_mux_array
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized1 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[1]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized11 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[11]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized12 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[12]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized13 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[13]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized14 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[14]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized15 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[15]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized16 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[16]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized17 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[17]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized18 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[18]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized19 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[19]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized20 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[20]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized2 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[2]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized21 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[21]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized22 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[22]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized23 \genblk1[22].genblk1_0.rotate_mux
(.D0(Data_i[22]),
.D1(Data_i[23]),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized24 \genblk1[23].genblk1_0.rotate_mux
(.D0(Data_i[23]),
.D1(Data_i[24]),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized25 \genblk1[24].genblk1_0.rotate_mux
(.D0(Data_i[24]),
.D1(Data_i[25]),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized26 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized3 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[3]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized4 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[4]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized5 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[5]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized6 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[6]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized7 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[7]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized8 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[8]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized9 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[9]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized10 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[10]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* LEVEL = "1" *) (* ORIG_REF_NAME = "shift_mux_array" *) (* SWR = "26" *)
module shift_mux_array__parameterized0
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized27 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[2]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized37 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[12]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized38 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[13]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized39 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[14]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized40 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[15]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized41 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[16]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized42 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[17]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized43 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[18]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized44 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[19]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized45 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[20]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized46 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[21]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized28 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[3]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized47 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[22]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized48 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[23]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized49 \genblk1[22].genblk1_0.rotate_mux
(.D0(Data_i[22]),
.D1(Data_i[24]),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized50 \genblk1[23].genblk1_0.rotate_mux
(.D0(Data_i[23]),
.D1(Data_i[25]),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized51 \genblk1[24].genblk1.rotate_mux
(.D0(Data_i[24]),
.D1(bit_shift_i),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized52 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized29 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[4]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized30 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[5]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized31 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[6]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized32 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[7]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized33 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[8]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized34 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[9]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized35 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[10]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized36 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[11]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* LEVEL = "2" *) (* ORIG_REF_NAME = "shift_mux_array" *) (* SWR = "26" *)
module shift_mux_array__parameterized1
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized53 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[4]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized63 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[14]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized64 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[15]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized65 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[16]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized66 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[17]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized67 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[18]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized68 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[19]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized69 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[20]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized70 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[21]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized71 \genblk1[18].genblk1_0.rotate_mux
(.D0(Data_i[18]),
.D1(Data_i[22]),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized72 \genblk1[19].genblk1_0.rotate_mux
(.D0(Data_i[19]),
.D1(Data_i[23]),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized54 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[5]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized73 \genblk1[20].genblk1_0.rotate_mux
(.D0(Data_i[20]),
.D1(Data_i[24]),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized74 \genblk1[21].genblk1_0.rotate_mux
(.D0(Data_i[21]),
.D1(Data_i[25]),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized75 \genblk1[22].genblk1.rotate_mux
(.D0(Data_i[22]),
.D1(bit_shift_i),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized76 \genblk1[23].genblk1.rotate_mux
(.D0(Data_i[23]),
.D1(bit_shift_i),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized77 \genblk1[24].genblk1.rotate_mux
(.D0(Data_i[24]),
.D1(bit_shift_i),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized78 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized55 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[6]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized56 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[7]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized57 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[8]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized58 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[9]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized59 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[10]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized60 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[11]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized61 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[12]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized62 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[13]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* LEVEL = "3" *) (* ORIG_REF_NAME = "shift_mux_array" *) (* SWR = "26" *)
module shift_mux_array__parameterized2
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized79 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[8]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized89 \genblk1[10].genblk1_0.rotate_mux
(.D0(Data_i[10]),
.D1(Data_i[18]),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized90 \genblk1[11].genblk1_0.rotate_mux
(.D0(Data_i[11]),
.D1(Data_i[19]),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized91 \genblk1[12].genblk1_0.rotate_mux
(.D0(Data_i[12]),
.D1(Data_i[20]),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized92 \genblk1[13].genblk1_0.rotate_mux
(.D0(Data_i[13]),
.D1(Data_i[21]),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized93 \genblk1[14].genblk1_0.rotate_mux
(.D0(Data_i[14]),
.D1(Data_i[22]),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized94 \genblk1[15].genblk1_0.rotate_mux
(.D0(Data_i[15]),
.D1(Data_i[23]),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized95 \genblk1[16].genblk1_0.rotate_mux
(.D0(Data_i[16]),
.D1(Data_i[24]),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized96 \genblk1[17].genblk1_0.rotate_mux
(.D0(Data_i[17]),
.D1(Data_i[25]),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized97 \genblk1[18].genblk1.rotate_mux
(.D0(Data_i[18]),
.D1(bit_shift_i),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized98 \genblk1[19].genblk1.rotate_mux
(.D0(Data_i[19]),
.D1(bit_shift_i),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized80 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[9]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized99 \genblk1[20].genblk1.rotate_mux
(.D0(Data_i[20]),
.D1(bit_shift_i),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized100 \genblk1[21].genblk1.rotate_mux
(.D0(Data_i[21]),
.D1(bit_shift_i),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized101 \genblk1[22].genblk1.rotate_mux
(.D0(Data_i[22]),
.D1(bit_shift_i),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized102 \genblk1[23].genblk1.rotate_mux
(.D0(Data_i[23]),
.D1(bit_shift_i),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized103 \genblk1[24].genblk1.rotate_mux
(.D0(Data_i[24]),
.D1(bit_shift_i),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized104 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized81 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[10]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized82 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[11]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized83 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[12]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized84 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[13]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized85 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[14]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized86 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[15]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized87 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[16]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized88 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[17]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* LEVEL = "4" *) (* ORIG_REF_NAME = "shift_mux_array" *) (* SWR = "26" *)
module shift_mux_array__parameterized3
(Data_i,
select_i,
bit_shift_i,
Data_o);
input [25:0]Data_i;
input select_i;
input bit_shift_i;
output [25:0]Data_o;
wire [25:0]Data_i;
wire [25:0]Data_o;
wire bit_shift_i;
wire select_i;
(* W = "1" *)
Multiplexer_AC__parameterized105 \genblk1[0].genblk1_0.rotate_mux
(.D0(Data_i[0]),
.D1(Data_i[16]),
.S(Data_o[0]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized115 \genblk1[10].genblk1.rotate_mux
(.D0(Data_i[10]),
.D1(bit_shift_i),
.S(Data_o[10]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized116 \genblk1[11].genblk1.rotate_mux
(.D0(Data_i[11]),
.D1(bit_shift_i),
.S(Data_o[11]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized117 \genblk1[12].genblk1.rotate_mux
(.D0(Data_i[12]),
.D1(bit_shift_i),
.S(Data_o[12]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized118 \genblk1[13].genblk1.rotate_mux
(.D0(Data_i[13]),
.D1(bit_shift_i),
.S(Data_o[13]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized119 \genblk1[14].genblk1.rotate_mux
(.D0(Data_i[14]),
.D1(bit_shift_i),
.S(Data_o[14]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized120 \genblk1[15].genblk1.rotate_mux
(.D0(Data_i[15]),
.D1(bit_shift_i),
.S(Data_o[15]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized121 \genblk1[16].genblk1.rotate_mux
(.D0(Data_i[16]),
.D1(bit_shift_i),
.S(Data_o[16]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized122 \genblk1[17].genblk1.rotate_mux
(.D0(Data_i[17]),
.D1(bit_shift_i),
.S(Data_o[17]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized123 \genblk1[18].genblk1.rotate_mux
(.D0(Data_i[18]),
.D1(bit_shift_i),
.S(Data_o[18]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized124 \genblk1[19].genblk1.rotate_mux
(.D0(Data_i[19]),
.D1(bit_shift_i),
.S(Data_o[19]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized106 \genblk1[1].genblk1_0.rotate_mux
(.D0(Data_i[1]),
.D1(Data_i[17]),
.S(Data_o[1]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized125 \genblk1[20].genblk1.rotate_mux
(.D0(Data_i[20]),
.D1(bit_shift_i),
.S(Data_o[20]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized126 \genblk1[21].genblk1.rotate_mux
(.D0(Data_i[21]),
.D1(bit_shift_i),
.S(Data_o[21]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized127 \genblk1[22].genblk1.rotate_mux
(.D0(Data_i[22]),
.D1(bit_shift_i),
.S(Data_o[22]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized128 \genblk1[23].genblk1.rotate_mux
(.D0(Data_i[23]),
.D1(bit_shift_i),
.S(Data_o[23]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized129 \genblk1[24].genblk1.rotate_mux
(.D0(Data_i[24]),
.D1(bit_shift_i),
.S(Data_o[24]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized130 \genblk1[25].genblk1.rotate_mux
(.D0(Data_i[25]),
.D1(bit_shift_i),
.S(Data_o[25]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized107 \genblk1[2].genblk1_0.rotate_mux
(.D0(Data_i[2]),
.D1(Data_i[18]),
.S(Data_o[2]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized108 \genblk1[3].genblk1_0.rotate_mux
(.D0(Data_i[3]),
.D1(Data_i[19]),
.S(Data_o[3]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized109 \genblk1[4].genblk1_0.rotate_mux
(.D0(Data_i[4]),
.D1(Data_i[20]),
.S(Data_o[4]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized110 \genblk1[5].genblk1_0.rotate_mux
(.D0(Data_i[5]),
.D1(Data_i[21]),
.S(Data_o[5]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized111 \genblk1[6].genblk1_0.rotate_mux
(.D0(Data_i[6]),
.D1(Data_i[22]),
.S(Data_o[6]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized112 \genblk1[7].genblk1_0.rotate_mux
(.D0(Data_i[7]),
.D1(Data_i[23]),
.S(Data_o[7]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized113 \genblk1[8].genblk1_0.rotate_mux
(.D0(Data_i[8]),
.D1(Data_i[24]),
.S(Data_o[8]),
.ctrl(select_i));
(* W = "1" *)
Multiplexer_AC__parameterized114 \genblk1[9].genblk1_0.rotate_mux
(.D0(Data_i[9]),
.D1(Data_i[25]),
.S(Data_o[9]),
.ctrl(select_i));
endmodule
(* W = "32" *)
module xor_tri
(A_i,
B_i,
C_i,
Z_o);
input A_i;
input B_i;
input C_i;
output Z_o;
wire A_i;
wire B_i;
wire C_i;
wire Z_o;
LUT3 #(
.INIT(8'h96))
Z_o_INST_0
(.I0(A_i),
.I1(B_i),
.I2(C_i),
.O(Z_o));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
/*
tab size 4
*/
module jt51_lfo_lfsr #(parameter init=220 )(
input rst,
input clk,
input base,
output out
);
reg [18:0] bb;
assign out = bb[18];
reg last_base;
always @(posedge clk) begin : base_counter
if( rst ) begin
bb <= init[18:0];
last_base <= 1'b0;
end
else begin
last_base <= base;
if( last_base != base ) begin
bb[18:1] <= bb[17:0];
bb[0] <= ^{bb[0],bb[1],bb[14],bb[15],bb[17],bb[18]};
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_1_V
`define SKY130_FD_SC_HD__FAH_1_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fah_1 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__fah_1 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_1_V
|
module fake_nonburstboundary #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BURSTCOUNT_WIDTH-1:0] master_burstcount,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata,
input master_readdatavalid
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_burstcount = slave_burstcount;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = master_readdatavalid;
assign slave_readdata = master_readdata;
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
(** We allow to unfold the [relation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind relational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : relation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : relation A) : relation A := fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : relation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : relation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : relation A) :=
asymmetry : forall {x y}, R x y -> R y x -> False.
Class Transitive (R : relation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : relation A) : Prop := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : relation A) : Prop := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence relation is Symmetric and Transitive. *)
Class PER (R : relation A) : Prop := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence relations. *)
Class Equivalence (R : relation A) : Prop := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(E:Equivalence R) : PER R | 10 :=
{ }.
(** An Equivalence is a PreOrder plus symmetry. *)
Global Instance Equivalence_PreOrder {R} `(E:Equivalence R) : PreOrder R | 10 :=
{ }.
(** We can now define antisymmetry w.r.t. an equivalence relation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : relation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : relation A) : Prop :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric relation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros. red in H0. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite relation on a given support: declares a relation as a rewrite
relation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
relations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : relation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite relation. *)
Global Instance equivalence_rewrite_relation `(Equivalence eqA) : RewriteRelation eqA.
Defined.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence relation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite relations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Defined.
Instance: RewriteRelation iff.
Defined.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Arguments irreflexivity {A R Irreflexive} [x] _.
Arguments symmetry {A} {R} {_} [x] [y] _.
Arguments asymmetry {A} {R} {_} [x] [y] _ _.
Arguments transitivity {A} {R} {_} [x] [y] [z] _ _.
Arguments Antisymmetric A eqA {_} _.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for relations. *)
Ltac solve_relation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_relation : relations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_relation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_relation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence relation. *)
Program Instance iff_equivalence : Equivalence iff.
(** We now develop a generalization of results on relations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary relations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(* Note, we do not use [list Type] because it imposes unnecessary universe constraints *)
#[universes(template)]
Inductive Tlist : Type := Tnil : Tlist | Tcons : Type -> Tlist -> Tlist.
Local Infix "::" := Tcons.
Fixpoint arrows (l : Tlist) (r : Type) : Type :=
match l with
| Tnil => r
| A :: l' => A -> arrows l' r
end.
(** We can define abbreviations for operation and relation types based on [arrows]. *)
Definition unary_operation A := arrows (A::Tnil) A.
Definition binary_operation A := arrows (A::A::Tnil) A.
Definition ternary_operation A := arrows (A::A::A::Tnil) A.
(** We define n-ary [predicate]s as functions into [Prop]. *)
Notation predicate l := (arrows l Prop).
(** Unary predicates, or sets. *)
Definition unary_predicate A := predicate (A::Tnil).
(** Homogeneous binary relations, equivalent to [relation A]. *)
Definition binary_relation A := predicate (A::A::Tnil).
(** We can close a predicate by universal or existential quantification. *)
Fixpoint predicate_all (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => forall x : A, predicate_all tl (f x)
end.
Fixpoint predicate_exists (l : Tlist) : predicate l -> Prop :=
match l with
| Tnil => fun f => f
| A :: tl => fun f => exists x : A, predicate_exists tl (f x)
end.
(** Pointwise extension of a binary operation on [T] to a binary operation
on functions whose codomain is [T].
For an operator on [Prop] this lifts the operator to a binary operation. *)
Fixpoint pointwise_extension {T : Type} (op : binary_operation T)
(l : Tlist) : binary_operation (arrows l T) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
fun x => pointwise_extension op tl (R x) (R' x)
end.
(** Pointwise lifting, equivalent to doing [pointwise_extension] and closing using [predicate_all]. *)
Fixpoint pointwise_lifting (op : binary_relation Prop) (l : Tlist) : binary_relation (predicate l) :=
match l with
| Tnil => fun R R' => op R R'
| A :: tl => fun R R' =>
forall x, pointwise_lifting op tl (R x) (R' x)
end.
(** The n-ary equivalence relation, defined by lifting the 0-ary [iff] relation. *)
Definition predicate_equivalence {l : Tlist} : binary_relation (predicate l) :=
pointwise_lifting iff l.
(** The n-ary implication relation, defined by lifting the 0-ary [impl] relation. *)
Definition predicate_implication {l : Tlist} :=
pointwise_lifting impl l.
(** Notations for pointwise equivalence and implication of predicates. *)
Declare Scope predicate_scope.
Infix "<∙>" := predicate_equivalence (at level 95, no associativity) : predicate_scope.
Infix "-∙>" := predicate_implication (at level 70, right associativity) : predicate_scope.
Local Open Scope predicate_scope.
(** The pointwise liftings of conjunction and disjunctions.
Note that these are [binary_operation]s, building new relations out of old ones. *)
Definition predicate_intersection := pointwise_extension and.
Definition predicate_union := pointwise_extension or.
Infix "/∙\" := predicate_intersection (at level 80, right associativity) : predicate_scope.
Infix "\∙/" := predicate_union (at level 85, right associativity) : predicate_scope.
(** The always [True] and always [False] predicates. *)
Fixpoint true_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => True
| A :: tl => fun _ => @true_predicate tl
end.
Fixpoint false_predicate {l : Tlist} : predicate l :=
match l with
| Tnil => False
| A :: tl => fun _ => @false_predicate tl
end.
Notation "∙⊤∙" := true_predicate : predicate_scope.
Notation "∙⊥∙" := false_predicate : predicate_scope.
(** Predicate equivalence is an equivalence, and predicate implication defines a preorder. *)
Program Instance predicate_equivalence_equivalence :
Equivalence (@predicate_equivalence l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
fold pointwise_lifting.
induction l. firstorder.
intros. simpl in *. pose (IHl (x x0) (y x0) (z x0)).
firstorder.
Qed.
Program Instance predicate_implication_preorder :
PreOrder (@predicate_implication l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l. firstorder.
unfold predicate_implication in *. simpl in *.
intro. pose (IHl (x x0) (y x0) (z x0)). firstorder.
Qed.
(** We define the various operations which define the algebra on binary relations,
from the general ones. *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : relation (relation A) :=
@predicate_equivalence (_::_::Tnil).
Global Instance: RewriteRelation relation_equivalence.
Defined.
Definition relation_conjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_intersection (A::A::Tnil) R R'.
Definition relation_disjunction (R : relation A) (R' : relation A) : relation A :=
@predicate_union (A::A::Tnil) R R'.
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. exact (@predicate_equivalence_equivalence (A::A::Tnil)). Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. exact (@predicate_implication_preorder (A::A::Tnil)). Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence relation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
pose proof partial_order_equivalence as poe. do 3 red in poe.
apply <- poe. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. firstorder. Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and relation equivalence. *)
Program Instance subrelation_partial_order :
! PartialOrder (relation A) relation_equivalence subrelation.
Next Obligation.
Proof.
unfold relation_equivalence in *. compute; firstorder.
Qed.
Typeclasses Opaque arrows predicate_implication predicate_equivalence
relation_equivalence pointwise_lifting.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:06:28 09/07/2015
// Design Name:
// Module Name: Ninth_Phase_M
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Ninth_Phase_M
//SINGLE PRECISION PARAMETERS
# (parameter W_Exp = 8)
//DOUBLE PRECISION PARAMETERS
/* # (parameter W_Exp = 11) */
(
input wire clk, //system clock
input wire rst, //module's reset signal
input wire load_a, //load signals for registers
input wire load_b,
input wire [W_Exp-1:0] Exp_X, //Exponents of the operands
input wire [W_Exp-1:0] Exp_Y,
output wire [W_Exp:0] Exp_Add, //Result of the add function
output wire underflow_f //underflow flag
);
wire [W_Exp:0] U_Limit;
wire [W_Exp:0] Exp_Add_Verif;
wire underflow_exp_reg;
add_sub_carry_out #(.W(W_Exp)) EXP_Add_Reg (
.op_mode(1'b0),
.Data_A(Exp_X),
.Data_B(Exp_Y),
.Data_S(Exp_Add_Verif)
);
RegisterMult #(.W(W_Exp+1)) ExpAdd_Register ( //Data Y input register
.clk(clk),
.rst(rst),
.load(load_a),
.D(Exp_Add_Verif),
.Q(Exp_Add)
);
Comparator_Less #(.W(W_Exp+1)) Exp_unflow_Comparator (
.Data_A(Exp_Add),
.Data_B(U_Limit),
.less(underflow_exp_reg)
);
RegisterMult #(.W(1)) ExpUnderflow_Register ( //Data Y input register
.clk(clk),
.rst(rst),
.load(load_b),
.D(underflow_exp_reg),
.Q(underflow_f)
);
generate
if (W_Exp == 8)
assign U_Limit = 9'd127;
else
assign U_Limit = 12'd1023;
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_addrgen.v
// Version : v1.0
// Description: Generates address for the next beat in the transfer.
// used to index mstram to read/write data.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_addrgen
#(
parameter USE_ADDR_OFFSET = 0,
parameter C_DATA_WIDTH = 64,
parameter IS_READ = 1,
parameter C_ATG_BASIC_AXI4 = 1,
parameter C_ATG_AXI4LITE = 0
) (
input Clk ,
input rst_l ,
input [15:0] in_addr ,
input [8:0] in_addr_offset ,
input [15:0] in_id ,
input [7:0] in_len ,
input [2:0] in_size ,
input [5:0] in_lastaddr ,
input [1:0] in_burst ,
input in_push ,
input in_pop ,
input [0:0] in_user ,
output [0:0] out_user ,
output [15:0] out_addr ,
output [15:0] out_id ,
output [C_DATA_WIDTH/8-1:0] out_be ,
output out_done ,
output out_valid
);
localparam ADDR_BITS = (C_DATA_WIDTH == 32 ) ? 2 :
(C_DATA_WIDTH == 64 ) ? 3 :
(C_DATA_WIDTH == 128) ? 4 :
(C_DATA_WIDTH == 256) ? 5 : 6;
reg [15:0 ] addr_ff ;
reg [7:0 ] len_ff ;
reg [C_DATA_WIDTH/8-1:0] be_ff ;
reg [2:0 ] size_ff ;
reg [1:0 ] burst_ff ;
reg [ADDR_BITS-1:0 ] lastaddr_ff ;
reg [11:0 ] wrap_mask_ff ;
reg [11:0 ] addr_offset_ff;
reg [15:0 ] addr_base_ff ;
reg [15:0 ] id_ff ;
reg [0:0 ] user_ff ;
reg done_ff, valid_ff ;
wire [2:0 ] size_opt ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_NARROW_YES
assign size_opt = in_size;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_NARROW_NO
if(C_DATA_WIDTH == 32) begin
assign size_opt = 2 ;
end
if(C_DATA_WIDTH == 64) begin
assign size_opt = 3 ;
end
if(C_DATA_WIDTH == 128) begin
assign size_opt = 4 ;
end
if(C_DATA_WIDTH == 256) begin
assign size_opt = 5 ;
end
if(C_DATA_WIDTH == 512) begin
assign size_opt = 6 ;
end
end
endgenerate
wire [0:0] user = (in_push) ? in_user : user_ff;
wire [2:0] size = (in_push) ? size_opt[2:0] : size_ff[2:0];
wire [1:0] burst = (in_push) ? in_burst[1:0] : burst_ff[1:0];
wire [15:0] id = (in_push) ? in_id[15:0] : id_ff[15:0];
wire [4:0] mask_raw ;
wire [8:0] wrap_mask_raw ;
wire [11:0] wrap_mask ;
wire [8:0] addr_offset_new ;
wire [12:0] addr_in_masked ;
wire [12:0] addr_off_masked ;
wire [12:0] addr_base_add_pre ;
wire [12:0] addr_base_add ;
wire [6:0] inc ;
wire [15:0] addr_mask_pre ;
wire [15:0] addr_mask2 ;
wire [15:0] addr_mask ;
wire [12:0] addr_aligned_pre ;
wire [15:0] addr_aligned ;
wire [11:0] addr_offset_inced_pre ;
wire [11:0] addr_offset_inced ;
wire [15:0] addr_inced ;
wire [15:0] addr_base ;
wire [15:0] addr ;
wire [11:0] addr_offset ;
wire [7:0] len ;
generate if(C_ATG_BASIC_AXI4 == 0 && C_ATG_AXI4LITE == 0) begin : ATG_WRAP_FIXED_YES
assign mask_raw = (8'h1 << size_opt[2:0]) - 8'h1;
assign wrap_mask_raw = (in_len[3]) ? { mask_raw[4:0], 4'b1111 } :
(in_len[2]) ? { mask_raw[4:0], 3'b111 } :
(in_len[1]) ? { 1'b0, mask_raw[4:0], 2'b11 } :
{ 2'b00, mask_raw[4:0], 1'b1 };
assign wrap_mask = (in_push) ?
((in_burst[1]) ? { 3'h0, wrap_mask_raw[8:0] } :
(in_burst[0]) ? 12'hfff : 12'h0) :
wrap_mask_ff[11:0];
assign addr_offset_new = (in_burst[1]) ?
in_addr_offset[8:0] & wrap_mask_raw[8:0] : 9'h00;
assign addr_in_masked = { 4'h0, in_addr[8:0] & wrap_mask_raw[8:0] };
assign addr_off_masked = { 4'h0, in_addr_offset[8:0] & wrap_mask_raw[8:0]};
assign addr_base_add_pre = addr_in_masked[12:0] - addr_off_masked[12:0];
assign addr_base_add = (in_burst[1] && USE_ADDR_OFFSET) ?
addr_base_add_pre[12:0] : 13'h00;
assign inc = 7'h1 << size_ff[2:0];
assign addr_mask_pre = 16'hffff << size_opt[2:0];
assign addr_mask2 = (in_burst[1]) ? { 7'h0, wrap_mask_raw[8:0] } : 16'h0;
assign addr_mask = addr_mask_pre[15:0] & ~addr_mask2[15:0];
assign addr_aligned_pre = (in_addr[12:0] & addr_mask[12:0]) +
addr_base_add[12:0];
assign addr_aligned = { in_addr[15:13], addr_aligned_pre[12:0] };
assign addr_offset_inced_pre = addr_offset_ff[11:0] + { 5'h0, inc[6:0] };
assign addr_offset_inced = (addr_offset_ff[11:0] & ~wrap_mask_ff[11:0]) |
(addr_offset_inced_pre[11:0] & wrap_mask_ff[11:0]);
assign addr_inced = addr_base_ff[15:0] + { 4'h0, addr_offset_inced[11:0]};
assign addr_base = (in_push) ? addr_aligned[15:0] : addr_base_ff[15:0];
assign addr = (in_push) ? in_addr[15:0] :
(in_pop) ? { addr_base_ff[15:13], addr_inced[12:0] } :
addr_ff[15:0];
assign addr_offset = (in_push) ? { 3'h0, addr_offset_new[8:0] } :
(in_pop) ? addr_offset_inced[11:0] : addr_offset_ff[11:0];
end
assign len = (in_push) ? in_len[7:0] :
(in_pop) ? len_ff[7:0] - 8'h1 : len_ff[7:0];
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1 && C_ATG_AXI4LITE == 0) begin : ATG_WRAP_FIXED_NO
assign inc = 7'h1 << size_ff[2:0];
assign addr_offset_inced = addr_offset_ff[11:0] + { 5'h0, inc[6:0] };
assign addr_inced = addr_base_ff[15:0] + { 4'h0, addr_offset_inced[11:0]};
assign addr_base = (in_push) ? in_addr[15:0] : addr_base_ff[15:0];
assign addr_offset = (in_push) ? 12'h0 : (in_pop) ? addr_offset_inced[11:0] : addr_offset_ff[11:0];
assign addr = (in_push) ? in_addr[15:0] :
(in_pop) ? { addr_base_ff[15:13], addr_inced[12:0] } :
addr_ff[15:0];
assign len = (in_push) ? in_len[7:0] :
(in_pop) ? len_ff[7:0] - 8'h1 : len_ff[7:0];
end
endgenerate
generate if(C_ATG_AXI4LITE == 1) begin : ATG_AXI4LITE
assign addr = (in_push) ? in_addr[15:0] : addr_ff[15:0];
assign len = 8'h0;
end
endgenerate
wire done = (len[7:0] == 8'h0);
wire [C_DATA_WIDTH/8-1:0] be;
wire [ADDR_BITS-1:0] lastaddr ;
wire [C_DATA_WIDTH/8-1:0] be_mask0 ;
wire [6:0] be_mask_size ;
wire [ADDR_BITS-1:0] be_shift ;
wire [ADDR_BITS-1:0] be_shift2 ;
wire [C_DATA_WIDTH/8-1:0] be_mask_shift ;
wire [C_DATA_WIDTH/8-1:0] be_notlast ;
wire [C_DATA_WIDTH/8-1:0] be_last ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_STRB_YES
assign lastaddr = (in_push) ? in_lastaddr[ADDR_BITS-1:0] :
lastaddr_ff[ADDR_BITS-1:0];
assign be_mask0 = (64'h1 << (7'h1 << size[2:0])) - 64'h1;
// So size==0 -> (1 << 1) - 1 = 1
// size==1 -> (1 << 2) - 1 = 3
// size==2 -> (1 << 4) - 1 = 0xf
// size==3 -> (1 << 8) - 1 = 0xff
// size==4 -> (1 << 16) - 1 = 0xffff
// size==5 -> (1 << 32) - 1 = 0xffffffff
// size==6 -> (1 << 64) - 1 = 0xffff_ffff_ffff_ffff
assign be_mask_size = (7'h1 << size[2:0]) - 7'h1;
assign be_shift = be_mask_size[6:0] & addr[6:0];
assign be_shift2 = ~be_mask_size[6:0] & addr[6:0];
assign be_mask_shift =
(64'hffffffff_ffffffff << be_shift[ADDR_BITS-1:0]);
assign be_notlast =
(be_mask_shift[C_DATA_WIDTH/8-1:0] & be_mask0[C_DATA_WIDTH/8-1:0]) <<
be_shift2[ADDR_BITS-1:0];
assign be_last = (lastaddr[ADDR_BITS-1:0] == 'h0) ?
64'hffffffff_ffffffff : (64'h1 << lastaddr[ADDR_BITS-1:0]) - 64'h1;
assign be = (done) ? be_notlast[C_DATA_WIDTH/8-1:0] &
be_last[C_DATA_WIDTH/8-1:0] : be_notlast[C_DATA_WIDTH/8-1:0];
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_STRB_NO
assign be = {C_DATA_WIDTH/8{1'b1}};
end
endgenerate
wire complete = in_pop && done_ff;
wire valid = in_push || (~complete && valid_ff);
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_FF_0
always @(posedge Clk) begin
addr_ff[15:0] <= (rst_l) ? addr[15:0] : 16'h0 ;
addr_base_ff[15:0] <= (rst_l) ? addr_base[15:0] : 16'h0 ;
addr_offset_ff[11:0] <= (rst_l) ? addr_offset[11:0] : 12'h0 ;
wrap_mask_ff[11:0] <= (rst_l) ? wrap_mask[11:0] : 12'hfff ;
id_ff[15:0] <= (rst_l) ? id[15:0] : 16'h0 ;
user_ff[0:0] <= (rst_l) ? user[0:0] : 1'h0 ;
size_ff[2:0] <= (rst_l) ? size[2:0] : 3'b000 ;
burst_ff[1:0] <= (rst_l) ? burst[1:0] : 2'b00 ;
len_ff[7:0] <= (rst_l) ? len[7:0] : 8'h0 ;
be_ff[C_DATA_WIDTH/8-1:0] <= (rst_l) ? be[C_DATA_WIDTH/8-1:0] : 'h0 ;
lastaddr_ff[ADDR_BITS-1:0] <= (rst_l) ? lastaddr[ADDR_BITS-1:0] : 'h0;
done_ff <= (rst_l) ? done : 1'b0 ;
valid_ff <= (rst_l) ? valid : 1'b0 ;
end
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_FF_1
always @(posedge Clk) begin
addr_offset_ff[11:0] <= (rst_l) ? addr_offset[11:0] : 12'h0 ;
addr_base_ff[15:0] <= (rst_l) ? addr_base[15:0] : 16'h0 ;
addr_ff[15:0] <= (rst_l) ? addr[15:0] : 16'h0 ;
size_ff[2:0] <= (rst_l) ? size[2:0] : 3'b000 ;
id_ff[15:0] <= (rst_l) ? id[15:0] : 16'h0 ;
len_ff[7:0] <= (rst_l) ? len[7:0] : 8'h0 ;
be_ff[C_DATA_WIDTH/8-1:0] <= (rst_l) ? be[C_DATA_WIDTH/8-1:0] : 'h0 ;
valid_ff <= (rst_l) ? valid : 1'b0 ;
done_ff <= (rst_l) ? done : 1'b0 ;
user_ff[0:0] <= (rst_l) ? user[0:0] : 1'h0 ;
end
end
endgenerate
assign out_addr[15:0] = addr_ff[15:0] ;
assign out_id[15:0] = id_ff[15:0] ;
assign out_be[C_DATA_WIDTH/8-1:0] = be_ff[C_DATA_WIDTH/8-1:0];
assign out_valid = valid_ff ;
assign out_done = done_ff ;
assign out_user = user_ff ;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
// IP Revision: 10
(* X_CORE_INFO = "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "mig_wrap_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}" *)
(* CORE_GENERATION_INFO = "mig_wrap_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=virtex7,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH\
=1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module mig_wrap_auto_cc_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [3 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [3 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [3 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [3 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
input wire m_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
input wire m_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [3 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [3 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [3 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [3 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_clock_converter_v2_1_10_axi_clock_converter #(
.C_FAMILY("virtex7"),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(1),
.C_AXI_PROTOCOL(0),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(4'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
Filename : ALU.v
Compiler : Quartus II
Description : ALU ---- Arithmetic and Logic Unit
INPUT : input [31:0]in1, in2,
input [5:0]ALUFun,
input sign,
OUTPUT : output reg [31:0] out
Author : Zhang Chuanyi
Release : 2015/7/20
*/
module ALU (
input [31:0] in1, in2,
input [5:0] ALUFun,
input sign,
output reg [31:0] out
);
reg zero, overflow;
wire negative;
reg [31:0] out00, out01, out10, out11;
reg nega;
assign negative = sign&nega;
always @ (*) begin
case (ALUFun[0])
1'b0: begin
out00 = in1 + in2;
zero = (out00 == 1'b0)? 1'b1 : 1'b0;
overflow = (sign&(in1[31]&in2[31]) ^ (in1[30]&in2[30])) | (~sign&(in1[31]&in2[31]));
nega = out00[31];
end
1'b1: begin
out00 = in1 + ~in2 + 32'b1;
zero = (out00 == 1'b0)? 1'b1 : 1'b0;
overflow = (sign&(in1[31]&in2[31]) ^ (in1[30]&in2[30])) | (~sign&(in1[31]&in2[31]));
nega = out00[31];
end
default : out00 = 32'b0;
endcase
case (ALUFun[3:1])
3'b001: out11 = zero ? 32'b1 : 32'b0;
3'b000: out11 = zero ? 32'b0 : 32'b1;
3'b010: out11 = nega ? 32'b1 : 32'b0;
3'b110: out11 = (nega|zero) ? 32'b1 : 32'b0; // blez
3'b100: out11 = (~in1[31]) ? 32'b1 : 32'b0; // bgez
3'b111: out11 = (~in1[31]&~zero) ? 32'b1 : 32'b0; // bgtz
default : out11 = 32'b0;
endcase
case (ALUFun[3:0])
4'b1000: out01 = in1 & in2;
4'b1110: out01 = in1 | in2;
4'b0110: out01 = in1 ^ in2;
4'b0001: out01 = ~(in1 | in2);
4'b1010: out01 = in1;
default : out01 = 32'b0;
endcase
case (ALUFun[1:0])
2'b00: begin // sll
out10 = in2;
if (in1[4]) out10 = out10<<16;
if (in1[3]) out10 = out10<<8;
if (in1[2]) out10 = out10<<4;
if (in1[1]) out10 = out10<<2;
if (in1[0]) out10 = out10<<1;
end
2'b01: begin // srl
out10 = in2;
if (in1[4]) out10 = out10>>16;
if (in1[3]) out10 = out10>>8;
if (in1[2]) out10 = out10>>4;
if (in1[1]) out10 = out10>>2;
if (in1[0]) out10 = out10>>1;
end
2'b11: begin // sra
out10 = in2;
if (in1[4]) out10 = (out10>>16) | {{16{in2[31]}},{16{1'b0}}};
if (in1[3]) out10 = ((out10>>8) | {{8{in2[31]}},{24{1'b0}}});
if (in1[2]) out10 = (out10>>4) | {{4{in2[31]}},{28{1'b0}}};
if (in1[1]) out10 = (out10>>2) | {{2{in2[31]}},{30{1'b0}}};
if (in1[0]) out10 = (out10>>1) | {{1{in2[31]}},{31{1'b0}}};
end
default : out10 = 32'b0;
endcase
case(ALUFun[5:4])
2'b00: out = out00;
2'b01: out = out01;
2'b10: out = out10;
2'b11: out = out11;
default: out<= 32'b0;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S4S_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLYMETAL6S4S_BEHAVIORAL_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__dlymetal6s4s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S4S_BEHAVIORAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFSTP_1_V
`define SKY130_FD_SC_HVL__SDFSTP_1_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFSTP_1_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction decode ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Majority of instruction decoding is performed here. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
//
// $Log: or1200_ctrl.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Major update:
// Structure reordered and bugs fixed.
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ctrl
(
// Clock and reset
clk, rst,
// Internal i/f
except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
wb_flushpipe,
id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, alu_op2, mac_op,
comp_op, rf_addrw, rfwb_op, fpu_op,
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
sel_b, id_lsu_op,
cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
ex_spr_write,
id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal, dc_no_writethrough
, sp_refresh_disable
);
//
// I/O
//
input clk;
input rst;
input id_freeze;
input ex_freeze /* verilator public */;
input wb_freeze /* verilator public */;
output if_flushpipe;
output id_flushpipe;
output ex_flushpipe;
output wb_flushpipe;
input extend_flush;
input except_flushpipe;
input abort_mvspr ;
input [31:0] if_insn;
output [31:0] id_insn;
output [31:0] ex_insn /* verilator public */;
output [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
output [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
input ex_branch_taken;
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
output [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
output rf_rda;
output rf_rdb;
output [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
output [`OR1200_MACOP_WIDTH-1:0] mac_op;
output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
output [`OR1200_FPUOP_WIDTH-1:0] fpu_op;
input pc_we;
output [31:0] wb_insn;
output [31:2] id_branch_addrtarget;
output [31:2] ex_branch_addrtarget;
output [`OR1200_SEL_WIDTH-1:0] sel_a;
output [`OR1200_SEL_WIDTH-1:0] sel_b;
output [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
output [`OR1200_COMPOP_WIDTH-1:0] comp_op;
output [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
output [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
output [4:0] cust5_op;
output [5:0] cust5_limm;
input [31:0] id_pc;
input [31:0] ex_pc;
output [31:0] id_simm;
output [31:0] ex_simm;
input wbforw_valid;
input du_hwbkpt;
output sig_syscall;
output sig_trap;
output force_dslot_fetch;
output no_more_dslot;
output id_void;
output ex_void;
output ex_spr_read;
output ex_spr_write;
output [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
output id_macrc_op;
output ex_macrc_op;
output rfe;
output except_illegal;
output dc_no_writethrough;
output sp_refresh_disable;
//
// Internal wires and regs
//
reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op;
reg [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op;
reg [`OR1200_ALUOP_WIDTH-1:0] alu_op;
reg [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
wire if_maci_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] ex_mac_op;
reg [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
reg ex_macrc_op;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire ex_macrc_op;
`endif
reg [31:0] id_insn /* verilator public */;
reg [31:0] ex_insn /* verilator public */;
reg [31:0] wb_insn /* verilator public */;
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
reg [`OR1200_SEL_WIDTH-1:0] sel_a;
reg [`OR1200_SEL_WIDTH-1:0] sel_b;
reg sel_imm;
reg [`OR1200_LSUOP_WIDTH-1:0] id_lsu_op;
reg [`OR1200_COMPOP_WIDTH-1:0] comp_op;
reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
reg [`OR1200_WAIT_ON_WIDTH-1:0] wait_on;
reg [31:0] id_simm;
reg [31:0] ex_simm;
reg sig_syscall;
reg sig_trap;
reg except_illegal;
wire id_void;
wire ex_void;
wire wb_void;
reg ex_delayslot_dsi;
reg ex_delayslot_nop;
reg spr_read;
reg spr_write;
reg [31:2] ex_branch_addrtarget;
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
reg dc_no_writethrough;
`endif
reg sp_refresh_disable;
//
// Register file read addresses
//
assign rf_addra = if_insn[20:16];
assign rf_addrb = if_insn[15:11];
assign rf_rda = if_insn[31] || if_maci_op;
assign rf_rdb = if_insn[30];
//
// Force fetch of delay slot instruction when jump/branch is preceeded by
// load/store instructions
//
assign force_dslot_fetch = 1'b0;
assign no_more_dslot = (|ex_branch_op & !id_void & ex_branch_taken) |
(ex_branch_op == `OR1200_BRANCHOP_RFE);
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
assign ex_spr_write = spr_write && !abort_mvspr;
assign ex_spr_read = spr_read && !abort_mvspr;
//
// ex_delayslot_dsi: delay slot insn is in EX stage
// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops
// jump/branch was executed)
//
// ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
// !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage,
// next different is DS insn, previous different was Jump/Branch
// !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
ex_delayslot_nop <= 1'b0;
ex_delayslot_dsi <= 1'b0;
end
else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
ex_delayslot_nop <= id_void;
ex_delayslot_dsi <= !id_void;
end
else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
ex_delayslot_nop <= 1'b0;
ex_delayslot_dsi <= 1'b0;
end
else if (!ex_freeze) begin
ex_delayslot_nop <= id_void && ex_branch_taken &&
(ex_branch_op != `OR1200_BRANCHOP_NOP) &&
(ex_branch_op != `OR1200_BRANCHOP_RFE);
ex_delayslot_dsi <= !id_void && ex_branch_taken &&
(ex_branch_op != `OR1200_BRANCHOP_NOP) &&
(ex_branch_op != `OR1200_BRANCHOP_RFE);
end
end
//
// Flush pipeline
//
assign if_flushpipe = except_flushpipe | pc_we | extend_flush;
assign id_flushpipe = except_flushpipe | pc_we | extend_flush;
assign ex_flushpipe = except_flushpipe | pc_we | extend_flush;
assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
//
// EX Sign/Zero extension of immediates
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
ex_simm <= 32'h0000_0000;
else if (!ex_freeze) begin
ex_simm <= id_simm;
end
end
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if(rst == `OR1200_RST_VALUE)
sp_refresh_disable <= 1'b0;
else if(id_insn == 32'h1500DEAD)
sp_refresh_disable <= 1'b1;
else if(id_insn == 32'h1500BEEF)
sp_refresh_disable <= 1'b0;
end
//
// ID Sign/Zero extension of immediate
//
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.addi
`OR1200_OR32_ADDI:
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
// l.addic
`OR1200_OR32_ADDIC:
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
// l.lxx (load instructions)
`OR1200_OR32_LWZ, `OR1200_OR32_LWS,
`OR1200_OR32_LBZ, `OR1200_OR32_LBS,
`OR1200_OR32_LHZ, `OR1200_OR32_LHS:
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
// l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI:
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
`endif
// l.maci
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACI:
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
`endif
// l.mtspr
`OR1200_OR32_MTSPR:
id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};
// l.sxx (store instructions)
`OR1200_OR32_SW, `OR1200_OR32_SH, `OR1200_OR32_SB:
id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
// l.xori
`OR1200_OR32_XORI:
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
// l.sfxxi (SFXX with immediate)
`OR1200_OR32_SFXXI:
id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
// Instructions with no or zero extended immediate
default:
id_simm = {{16'b0}, id_insn[15:0]};
endcase
end
//
// ID Sign extension of branch offset
//
assign id_branch_addrtarget = {{4{id_insn[25]}}, id_insn[25:0]} + id_pc[31:2];
//
// EX Sign extension of branch offset
//
// pipeline ID and EX branch target address
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
ex_branch_addrtarget <= 0;
else if (!ex_freeze)
ex_branch_addrtarget <= id_branch_addrtarget;
end
// not pipelined
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
//
// l.maci in IF stage
//
`ifdef OR1200_MAC_IMPLEMENTED
assign if_maci_op = (if_insn[31:26] == `OR1200_OR32_MACI);
`else
assign if_maci_op = 1'b0;
`endif
//
// l.macrc in ID stage
//
`ifdef OR1200_MAC_IMPLEMENTED
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MACRC) & id_insn[16];
`else
assign id_macrc_op = 1'b0;
`endif
//
// l.macrc in EX stage
//
`ifdef OR1200_MAC_IMPLEMENTED
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
ex_macrc_op <= 1'b0;
else if (!ex_freeze & id_freeze | ex_flushpipe)
ex_macrc_op <= 1'b0;
else if (!ex_freeze)
ex_macrc_op <= id_macrc_op;
end
`else
assign ex_macrc_op = 1'b0;
`endif
//
// cust5_op, cust5_limm (L immediate)
//
assign cust5_op = ex_insn[4:0];
assign cust5_limm = ex_insn[10:5];
//
//
//
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) |
(ex_branch_op == `OR1200_BRANCHOP_RFE);
`ifdef verilator
// Function to access wb_insn (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_wb_insn;
// verilator public
get_wb_insn = wb_insn;
endfunction // get_wb_insn
// Function to access id_insn (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_id_insn;
// verilator public
get_id_insn = id_insn;
endfunction // get_id_insn
// Function to access ex_insn (for Verilator). Have to hide this from
// simulator, since functions with no inputs are not allowed in IEEE
// 1364-2001.
function [31:0] get_ex_insn;
// verilator public
get_ex_insn = ex_insn;
endfunction // get_ex_insn
`endif
//
// Generation of sel_a
//
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
sel_a = `OR1200_SEL_EX_FORW;
else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
sel_a = `OR1200_SEL_WB_FORW;
else
sel_a = `OR1200_SEL_RF;
//
// Generation of sel_b
//
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or
wb_rfaddrw)
if (sel_imm)
sel_b = `OR1200_SEL_IMM;
else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
sel_b = `OR1200_SEL_EX_FORW;
else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
sel_b = `OR1200_SEL_WB_FORW;
else
sel_b = `OR1200_SEL_RF;
//
// Decode of multicycle
//
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.rfe
`OR1200_OR32_RFE,
// l.mfspr
`OR1200_OR32_MFSPR:
multicycle = `OR1200_TWO_CYCLES; // to read from ITLB/DTLB (sync RAMs)
// Single cycle instructions
default: begin
multicycle = `OR1200_ONE_CYCLE;
end
endcase
end // always @ (id_insn)
//
// Encode wait_on signal
//
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
`OR1200_OR32_ALU:
wait_on = ( 1'b0
`ifdef OR1200_DIV_IMPLEMENTED
| (id_insn[4:0] == `OR1200_ALUOP_DIV)
| (id_insn[4:0] == `OR1200_ALUOP_DIVU)
`endif
`ifdef OR1200_MULT_IMPLEMENTED
| (id_insn[4:0] == `OR1200_ALUOP_MUL)
| (id_insn[4:0] == `OR1200_ALUOP_MULU)
`endif
) ? `OR1200_WAIT_ON_MULTMAC : `OR1200_WAIT_ON_NOTHING;
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACMSB,
`OR1200_OR32_MACI,
`endif
`OR1200_OR32_MULI:
wait_on = `OR1200_WAIT_ON_MULTMAC;
`endif
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACRC:
wait_on = id_insn[16] ? `OR1200_WAIT_ON_MULTMAC :
`OR1200_WAIT_ON_NOTHING;
`endif
`ifdef OR1200_FPU_IMPLEMENTED
`OR1200_OR32_FLOAT: begin
wait_on = id_insn[`OR1200_FPUOP_DOUBLE_BIT] ? 0 : `OR1200_WAIT_ON_FPU;
end
`endif
`ifndef OR1200_DC_WRITEHROUGH
// l.mtspr
`OR1200_OR32_MTSPR: begin
wait_on = `OR1200_WAIT_ON_MTSPR;
end
`endif
default: begin
wait_on = `OR1200_WAIT_ON_NOTHING;
end
endcase // case (id_insn[31:26])
end // always @ (id_insn)
//
// Register file write address
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
rf_addrw <= 5'd0;
else if (!ex_freeze & id_freeze)
rf_addrw <= 5'd00;
else if (!ex_freeze)
case (id_insn[31:26]) // synopsys parallel_case
`OR1200_OR32_JAL, `OR1200_OR32_JALR:
rf_addrw <= 5'd09; // link register r9
default:
rf_addrw <= id_insn[25:21];
endcase
end
//
// rf_addrw in wb stage (used in forwarding logic)
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
wb_rfaddrw <= 5'd0;
else if (!wb_freeze)
wb_rfaddrw <= rf_addrw;
end
//
// Instruction latch in id_insn
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
else if (id_flushpipe)
id_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> id_insn[16] must be 1
else if (!id_freeze) begin
id_insn <= if_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: id_insn <= %h", $time, if_insn);
// synopsys translate_on
`endif
end
end
//
// Instruction latch in ex_insn
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
else if (!ex_freeze & id_freeze | ex_flushpipe)
ex_insn <= {`OR1200_OR32_NOP, 26'h041_0000}; // NOP -> ex_insn[16] must be 1
else if (!ex_freeze) begin
ex_insn <= id_insn;
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: ex_insn <= %h", $time, id_insn);
// synopsys translate_on
`endif
end
end
//
// Instruction latch in wb_insn
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
wb_insn <= {`OR1200_OR32_NOP, 26'h041_0000};
// wb_insn should not be changed by exceptions due to correct
// recording of display_arch_state in the or1200_monitor!
// wb_insn changed by exception is not used elsewhere!
else if (!wb_freeze) begin
wb_insn <= ex_insn;
end
end
//
// Decode of sel_imm
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
sel_imm <= 1'b0;
else if (!id_freeze) begin
case (if_insn[31:26]) // synopsys parallel_case
// j.jalr
`OR1200_OR32_JALR:
sel_imm <= 1'b0;
// l.jr
`OR1200_OR32_JR:
sel_imm <= 1'b0;
// l.rfe
`OR1200_OR32_RFE:
sel_imm <= 1'b0;
// l.mfspr
`OR1200_OR32_MFSPR:
sel_imm <= 1'b0;
// l.mtspr
`OR1200_OR32_MTSPR:
sel_imm <= 1'b0;
// l.sys, l.brk and all three sync insns
`OR1200_OR32_XSYNC:
sel_imm <= 1'b0;
// l.mac/l.msb
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACMSB:
sel_imm <= 1'b0;
`endif
// l.sw
`OR1200_OR32_SW:
sel_imm <= 1'b0;
// l.sb
`OR1200_OR32_SB:
sel_imm <= 1'b0;
// l.sh
`OR1200_OR32_SH:
sel_imm <= 1'b0;
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
sel_imm <= 1'b0;
// SFXX instructions
`OR1200_OR32_SFXX:
sel_imm <= 1'b0;
`ifdef OR1200_IMPL_ALU_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
sel_imm <= 1'b0;
`endif
`ifdef OR1200_FPU_IMPLEMENTED
// FPU instructions
`OR1200_OR32_FLOAT:
sel_imm <= 1'b0;
`endif
// l.nop
`OR1200_OR32_NOP:
sel_imm <= 1'b0;
// All instructions with immediates
default: begin
sel_imm <= 1'b1;
end
endcase
end
end
//
// Decode of except_illegal
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
except_illegal <= 1'b0;
else if (!ex_freeze & id_freeze | ex_flushpipe)
except_illegal <= 1'b0;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
`OR1200_OR32_J,
`OR1200_OR32_JAL,
`OR1200_OR32_JALR,
`OR1200_OR32_JR,
`OR1200_OR32_BNF,
`OR1200_OR32_BF,
`OR1200_OR32_RFE,
`OR1200_OR32_MOVHI,
`OR1200_OR32_MFSPR,
`OR1200_OR32_XSYNC,
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACI,
`endif
`OR1200_OR32_LWZ,
`OR1200_OR32_LWS,
`OR1200_OR32_LBZ,
`OR1200_OR32_LBS,
`OR1200_OR32_LHZ,
`OR1200_OR32_LHS,
`OR1200_OR32_ADDI,
`OR1200_OR32_ADDIC,
`OR1200_OR32_ANDI,
`OR1200_OR32_ORI,
`OR1200_OR32_XORI,
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI,
`endif
`OR1200_OR32_SH_ROTI,
`OR1200_OR32_SFXXI,
`OR1200_OR32_MTSPR,
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACMSB,
`endif
`OR1200_OR32_SW,
`OR1200_OR32_SB,
`OR1200_OR32_SH,
`OR1200_OR32_SFXX,
`ifdef OR1200_IMPL_ALU_CUST5
`OR1200_OR32_CUST5,
`endif
`OR1200_OR32_NOP:
except_illegal <= 1'b0;
`ifdef OR1200_FPU_IMPLEMENTED
`OR1200_OR32_FLOAT:
// Check it's not a double precision instruction
except_illegal <= id_insn[`OR1200_FPUOP_DOUBLE_BIT];
`endif
`OR1200_OR32_ALU:
except_illegal <= 1'b0
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
`else
| (id_insn[4:0] == `OR1200_ALUOP_DIV)
| (id_insn[4:0] == `OR1200_ALUOP_DIVU)
`endif
`else
| (id_insn[4:0] == `OR1200_ALUOP_DIV)
| (id_insn[4:0] == `OR1200_ALUOP_DIVU)
| (id_insn[4:0] == `OR1200_ALUOP_MUL)
`endif
`ifdef OR1200_IMPL_ADDC
`else
| (id_insn[4:0] == `OR1200_ALUOP_ADDC)
`endif
`ifdef OR1200_IMPL_ALU_FFL1
`else
| (id_insn[4:0] == `OR1200_ALUOP_FFL1)
`endif
`ifdef OR1200_IMPL_ALU_ROTATE
`else
| ((id_insn[4:0] == `OR1200_ALUOP_SHROT) &
(id_insn[9:6] == `OR1200_SHROTOP_ROR))
`endif
`ifdef OR1200_IMPL_SUB
`else
| (id_insn[4:0] == `OR1200_ALUOP_SUB)
`endif
`ifdef OR1200_IMPL_ALU_EXT
`else
| (id_insn[4:0] == `OR1200_ALUOP_EXTHB)
| (id_insn[4:0] == `OR1200_ALUOP_EXTW)
`endif
;
// Illegal and OR1200 unsupported instructions
default:
except_illegal <= 1'b1;
endcase
end // if (!ex_freeze)
end
//
// Decode of alu_op
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
alu_op <= `OR1200_ALUOP_NOP;
else if (!ex_freeze & id_freeze | ex_flushpipe)
alu_op <= `OR1200_ALUOP_NOP;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.movhi
`OR1200_OR32_MOVHI:
alu_op <= `OR1200_ALUOP_MOVHI;
// l.addi
`OR1200_OR32_ADDI:
alu_op <= `OR1200_ALUOP_ADD;
// l.addic
`OR1200_OR32_ADDIC:
alu_op <= `OR1200_ALUOP_ADDC;
// l.andi
`OR1200_OR32_ANDI:
alu_op <= `OR1200_ALUOP_AND;
// l.ori
`OR1200_OR32_ORI:
alu_op <= `OR1200_ALUOP_OR;
// l.xori
`OR1200_OR32_XORI:
alu_op <= `OR1200_ALUOP_XOR;
// l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI:
alu_op <= `OR1200_ALUOP_MUL;
`endif
// Shift and rotate insns with immediate
`OR1200_OR32_SH_ROTI:
alu_op <= `OR1200_ALUOP_SHROT;
// SFXX insns with immediate
`OR1200_OR32_SFXXI:
alu_op <= `OR1200_ALUOP_COMP;
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
alu_op <= {1'b0,id_insn[3:0]};
// SFXX instructions
`OR1200_OR32_SFXX:
alu_op <= `OR1200_ALUOP_COMP;
`ifdef OR1200_IMPL_ALU_CUST5
// l.cust5
`OR1200_OR32_CUST5:
alu_op <= `OR1200_ALUOP_CUST5;
`endif
// Default
default: begin
alu_op <= `OR1200_ALUOP_NOP;
end
endcase
end
end
//
// Decode of second ALU operation field [9:6]
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
alu_op2 <= 0;
else if (!ex_freeze & id_freeze | ex_flushpipe)
alu_op2 <= 0;
else if (!ex_freeze) begin
alu_op2 <= id_insn[`OR1200_ALUOP2_POS];
end
end
//
// Decode of spr_read, spr_write
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
spr_read <= 1'b0;
spr_write <= 1'b0;
end
else if (!ex_freeze & id_freeze | ex_flushpipe) begin
spr_read <= 1'b0;
spr_write <= 1'b0;
end
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.mfspr
`OR1200_OR32_MFSPR: begin
spr_read <= 1'b1;
spr_write <= 1'b0;
end
// l.mtspr
`OR1200_OR32_MTSPR: begin
spr_read <= 1'b0;
spr_write <= 1'b1;
end
// Default
default: begin
spr_read <= 1'b0;
spr_write <= 1'b0;
end
endcase
end
end
//
// Decode of mac_op
//
`ifdef OR1200_MAC_IMPLEMENTED
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.maci
`OR1200_OR32_MACI:
id_mac_op = `OR1200_MACOP_MAC;
// l.mac, l.msb
`OR1200_OR32_MACMSB:
id_mac_op = id_insn[2:0];
// Illegal and OR1200 unsupported instructions
default:
id_mac_op = `OR1200_MACOP_NOP;
endcase
end
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
ex_mac_op <= `OR1200_MACOP_NOP;
else if (!ex_freeze & id_freeze | ex_flushpipe)
ex_mac_op <= `OR1200_MACOP_NOP;
else if (!ex_freeze)
ex_mac_op <= id_mac_op;
end
assign mac_op = abort_mvspr ? `OR1200_MACOP_NOP : ex_mac_op;
`else
assign id_mac_op = `OR1200_MACOP_NOP;
assign mac_op = `OR1200_MACOP_NOP;
`endif
//
// Decode of rfwb_op
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
rfwb_op <= `OR1200_RFWBOP_NOP;
else if (!ex_freeze & id_freeze | ex_flushpipe)
rfwb_op <= `OR1200_RFWBOP_NOP;
else if (!ex_freeze) begin
case (id_insn[31:26]) // synopsys parallel_case
// j.jal
`OR1200_OR32_JAL:
rfwb_op <= {`OR1200_RFWBOP_LR, 1'b1};
// j.jalr
`OR1200_OR32_JALR:
rfwb_op <= {`OR1200_RFWBOP_LR, 1'b1};
// l.movhi
`OR1200_OR32_MOVHI:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
// l.mfspr
`OR1200_OR32_MFSPR:
rfwb_op <= {`OR1200_RFWBOP_SPRS, 1'b1};
// l.lwz
`OR1200_OR32_LWZ:
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
// l.lws
`OR1200_OR32_LWS:
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
// l.lbz
`OR1200_OR32_LBZ:
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
// l.lbs
`OR1200_OR32_LBS:
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
// l.lhz
`OR1200_OR32_LHZ:
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
// l.lhs
`OR1200_OR32_LHS:
rfwb_op <= {`OR1200_RFWBOP_LSU, 1'b1};
// l.addi
`OR1200_OR32_ADDI:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
// l.addic
`OR1200_OR32_ADDIC:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
// l.andi
`OR1200_OR32_ANDI:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
// l.ori
`OR1200_OR32_ORI:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
// l.xori
`OR1200_OR32_XORI:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
// l.muli
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_OR32_MULI:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
`endif
// Shift and rotate insns with immediate
`OR1200_OR32_SH_ROTI:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
`ifdef OR1200_ALU_IMPL_CUST5
// l.cust5 instructions
`OR1200_OR32_CUST5:
rfwb_op <= {`OR1200_RFWBOP_ALU, 1'b1};
`endif
`ifdef OR1200_FPU_IMPLEMENTED
// FPU instructions, lf.XXX.s, except sfxx
`OR1200_OR32_FLOAT:
rfwb_op <= {`OR1200_RFWBOP_FPU,!id_insn[3]};
`endif
// Instructions w/o register-file write-back
default:
rfwb_op <= `OR1200_RFWBOP_NOP;
endcase
end
end
//
// Decode of id_branch_op
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
id_branch_op <= `OR1200_BRANCHOP_NOP;
else if (id_flushpipe)
id_branch_op <= `OR1200_BRANCHOP_NOP;
else if (!id_freeze) begin
case (if_insn[31:26]) // synopsys parallel_case
// l.j
`OR1200_OR32_J:
id_branch_op <= `OR1200_BRANCHOP_J;
// j.jal
`OR1200_OR32_JAL:
id_branch_op <= `OR1200_BRANCHOP_J;
// j.jalr
`OR1200_OR32_JALR:
id_branch_op <= `OR1200_BRANCHOP_JR;
// l.jr
`OR1200_OR32_JR:
id_branch_op <= `OR1200_BRANCHOP_JR;
// l.bnf
`OR1200_OR32_BNF:
id_branch_op <= `OR1200_BRANCHOP_BNF;
// l.bf
`OR1200_OR32_BF:
id_branch_op <= `OR1200_BRANCHOP_BF;
// l.rfe
`OR1200_OR32_RFE:
id_branch_op <= `OR1200_BRANCHOP_RFE;
// Non branch instructions
default:
id_branch_op <= `OR1200_BRANCHOP_NOP;
endcase
end
end
//
// Generation of ex_branch_op
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
ex_branch_op <= `OR1200_BRANCHOP_NOP;
else if (!ex_freeze & id_freeze | ex_flushpipe)
ex_branch_op <= `OR1200_BRANCHOP_NOP;
else if (!ex_freeze)
ex_branch_op <= id_branch_op;
//
// Decode of id_lsu_op
//
always @(id_insn) begin
case (id_insn[31:26]) // synopsys parallel_case
// l.lwz
`OR1200_OR32_LWZ:
id_lsu_op = `OR1200_LSUOP_LWZ;
// l.lws
`OR1200_OR32_LWS:
id_lsu_op = `OR1200_LSUOP_LWS;
// l.lbz
`OR1200_OR32_LBZ:
id_lsu_op = `OR1200_LSUOP_LBZ;
// l.lbs
`OR1200_OR32_LBS:
id_lsu_op = `OR1200_LSUOP_LBS;
// l.lhz
`OR1200_OR32_LHZ:
id_lsu_op = `OR1200_LSUOP_LHZ;
// l.lhs
`OR1200_OR32_LHS:
id_lsu_op = `OR1200_LSUOP_LHS;
// l.sw
`OR1200_OR32_SW:
id_lsu_op = `OR1200_LSUOP_SW;
// l.sb
`OR1200_OR32_SB:
id_lsu_op = `OR1200_LSUOP_SB;
// l.sh
`OR1200_OR32_SH:
id_lsu_op = `OR1200_LSUOP_SH;
// Non load/store instructions
default:
id_lsu_op = `OR1200_LSUOP_NOP;
endcase
end
//
// Decode of comp_op
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
comp_op <= 4'd0;
end else if (!ex_freeze & id_freeze | ex_flushpipe)
comp_op <= 4'd0;
else if (!ex_freeze)
comp_op <= id_insn[24:21];
end
`ifdef OR1200_FPU_IMPLEMENTED
//
// Decode of FPU ops
//
assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT),
id_insn[`OR1200_FPUOP_WIDTH-2:0]};
`else
assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}};
`endif
//
// Decode of l.sys
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
sig_syscall <= 1'b0;
else if (!ex_freeze & id_freeze | ex_flushpipe)
sig_syscall <= 1'b0;
else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
$display("Generating sig_syscall");
// synopsys translate_on
`endif
sig_syscall <= (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
end
end
//
// Decode of l.trap
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
sig_trap <= 1'b0;
else if (!ex_freeze & id_freeze | ex_flushpipe)
sig_trap <= 1'b0;
else if (!ex_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
$display("Generating sig_trap");
// synopsys translate_on
`endif
sig_trap <= (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
| du_hwbkpt;
end
end
// Decode destination register address for data cache to check if store ops
// are being done from the stack register (r1) or frame pointer register (r2)
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
dc_no_writethrough <= 0;
else if (!ex_freeze)
dc_no_writethrough <= (id_insn[20:16] == 5'd1) | (id_insn[20:16] == 5'd2);
end
`else
assign dc_no_writethrough = 0;
`endif
endmodule
|
/*
* File: demo_top.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
* top module for FPGA demo on XUP board
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module demo_top(
FPGA_SYSTEMACE_CLOCK,
SW_0, SW_1, SW_2, SW_3,
PB_ENTER, PB_UP, PB_DOWN, PB_LEFT, PB_RIGHT,
LED_0, LED_1, LED_2, LED_3,
RS232_TX_DATA, RS232_RX_DATA
);
//
// I/O
//
// clock to DCM
input FPGA_SYSTEMACE_CLOCK; // 32MHz
// swith on board
input SW_0;
input SW_1;
input SW_2;
input SW_3;
// pushbotton on board
input PB_ENTER;
input PB_UP;
input PB_DOWN;
input PB_LEFT;
input PB_RIGHT;
// led on board
output LED_0;
output LED_1;
output LED_2;
output LED_3;
// uart on board
input RS232_RX_DATA;
output RS232_TX_DATA;
//
// interconnections
//
wire dsu_sram_we;
wire [31:0] iimx_adr_o;
wire iimx_rqt_o;
wire [31:0] iimx_dat_i;
wire iimx_ack_i;
wire iimx_rty_i;
wire iimx_err_i;
wire [31:0] iimx_adr_i;
wire [31:0] dimx_adr_o;
wire dimx_rqt_o;
wire dimx_we_o;
wire [3:0] dimx_sel_o;
wire [31:0] dimx_dat_o;
wire [31:0] dimx_dat_i;
wire dimx_ack_i;
wire dimx_err_i;
//
// clock and reset
//
demo_clk demo_clk (
.CLK_IN(FPGA_SYSTEMACE_CLOCK),
.RST(1'b0),
.CLK1X(clk32M),
.CLK2X(clk),
.LOCK(dcm_lock)
);
// [TBD] BUFG
assign rst = !PB_ENTER;
//
// heartbreak logic: clock is running
//
// Note: frequency of clk is 64MHz. 1s = 15.5ns * 64 * 10e6 (0x3D0_9000, 0011_1101_0000_1001_0000_0000_0000)
reg [26:0] clk_counter;
always @(posedge clk or posedge rst) begin
if(rst)
clk_counter <= 27'd0;
else
clk_counter <= clk_counter + 27'd1;
end
//
// reserved logic: just to keep core un-optimized by synthesis tool
//
wire iimx_rqt_status;
wire iimx_rsp_status;
wire dimx_rqt_status;
wire dimx_rsp_status;
assign iimx_rqt_status = (|iimx_adr_o) & iimx_rqt_o;
assign dimx_rqt_status = (|dimx_adr_o) & dimx_rqt_o;
assign iimx_rsp_status = (|iimx_dat_i) & iimx_ack_i;
assign dimx_rsp_status = ((|dimx_dat_i) | dimx_we_o) & dimx_ack_i;
//
// xup-v2p board source
// Note: When the FPGA drives a logic 0, the corresponding LED turns on. A single four-position DIP
// switch and five push buttons are provided for user input. If the DIP switch is up, closed, or on,
// or the push button is pressed, a logic 0 is seen by the FPGA, otherwise a logic 1 is indicated.
// signal pushed assert when push push-buttons
assign pushed = !(PB_UP & PB_DOWN & PB_LEFT & PB_RIGHT);
//
//
//
reg [9:0] num_burn_word;
always @(posedge clk or posedge rst) begin
if(rst)
num_burn_word <= 10'd0;
else if (dsu_sram_we)
num_burn_word <= num_burn_word + 10'd1;
end
//
// LED & SW
//
// SW_0: enable heartbreak flashing
// SW_1: enable imx rqt status flashing
// SW_2: enable imx rsp status flashing
// SW_3: enable for dsu burning mode
//
// LED0: status of clk
// LED1: status of imx request
// LED2: status of imx response
// LED3: status of on-chip ram burning process
assign dsu_rst = pushed;
assign dsu_burn_enable = SW_3;
assign LED0_light = clk_counter[26] & !rst & SW_0;
assign LED1_light = iimx_rqt_status | dimx_rqt_status & SW_1;
assign LED2_light = iimx_rsp_status | dimx_rsp_status & SW_2;
assign LED3_light = |num_burn_word;
assign LED_0 = ! LED0_light;
assign LED_1 = ! LED1_light;
assign LED_2 = ! LED2_light;
assign LED_3 = ! LED3_light;
//
// sys_top
//
top_pss sys_top_pss(
.clk(clk),
.rst(rst),
.dsu_rst(dsu_rst),
.dsu_burn_enable(dsu_burn_enable),
.dsu_sram_we(dsu_sram_we),
.txd(RS232_TX_DATA),
.rxd(RS232_RX_DATA),
.iimx_adr_o(iimx_adr_o),
.iimx_rqt_o(iimx_rqt_o),
.iimx_rty_i(iimx_rty_i),
.iimx_ack_i(iimx_ack_i),
.iimx_err_i(iimx_err_i),
.iimx_dat_i(iimx_dat_i),
.iimx_adr_i(iimx_adr_i),
.dimx_adr_o(dimx_adr_o),
.dimx_rqt_o(dimx_rqt_o),
.dimx_we_o(dimx_we_o),
.dimx_sel_o(dimx_sel_o),
.dimx_dat_o(dimx_dat_o),
.dimx_dat_i(dimx_dat_i),
.dimx_ack_i(dimx_ack_i),
.dimx_err_i(dimx_err_i)
);
endmodule
|
/*
Copyright (c) 2014-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* ARP block for IPv4, ethernet frame interface
*/
module arp #
(
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
// If disabled, tkeep assumed to be 1'b1
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Log2 of ARP cache size
parameter CACHE_ADDR_WIDTH = 9,
// ARP request retry count
parameter REQUEST_RETRY_COUNT = 4,
// ARP request retry interval (in cycles)
parameter REQUEST_RETRY_INTERVAL = 125000000*2,
// ARP request timeout (in cycles)
parameter REQUEST_TIMEOUT = 125000000*30
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* ARP requests
*/
input wire arp_request_valid,
output wire arp_request_ready,
input wire [31:0] arp_request_ip,
output wire arp_response_valid,
input wire arp_response_ready,
output wire arp_response_error,
output wire [47:0] arp_response_mac,
/*
* Configuration
*/
input wire [47:0] local_mac,
input wire [31:0] local_ip,
input wire [31:0] gateway_ip,
input wire [31:0] subnet_mask,
input wire clear_cache
);
localparam [15:0]
ARP_OPER_ARP_REQUEST = 16'h0001,
ARP_OPER_ARP_REPLY = 16'h0002,
ARP_OPER_INARP_REQUEST = 16'h0008,
ARP_OPER_INARP_REPLY = 16'h0009;
wire incoming_frame_valid;
reg incoming_frame_ready;
wire [47:0] incoming_eth_dest_mac;
wire [47:0] incoming_eth_src_mac;
wire [15:0] incoming_eth_type;
wire [15:0] incoming_arp_htype;
wire [15:0] incoming_arp_ptype;
wire [7:0] incoming_arp_hlen;
wire [7:0] incoming_arp_plen;
wire [15:0] incoming_arp_oper;
wire [47:0] incoming_arp_sha;
wire [31:0] incoming_arp_spa;
wire [47:0] incoming_arp_tha;
wire [31:0] incoming_arp_tpa;
/*
* ARP frame processing
*/
arp_eth_rx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
arp_eth_rx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// ARP frame output
.m_frame_valid(incoming_frame_valid),
.m_frame_ready(incoming_frame_ready),
.m_eth_dest_mac(incoming_eth_dest_mac),
.m_eth_src_mac(incoming_eth_src_mac),
.m_eth_type(incoming_eth_type),
.m_arp_htype(incoming_arp_htype),
.m_arp_ptype(incoming_arp_ptype),
.m_arp_hlen(incoming_arp_hlen),
.m_arp_plen(incoming_arp_plen),
.m_arp_oper(incoming_arp_oper),
.m_arp_sha(incoming_arp_sha),
.m_arp_spa(incoming_arp_spa),
.m_arp_tha(incoming_arp_tha),
.m_arp_tpa(incoming_arp_tpa),
// Status signals
.busy(),
.error_header_early_termination(),
.error_invalid_header()
);
reg outgoing_frame_valid_reg = 1'b0, outgoing_frame_valid_next;
wire outgoing_frame_ready;
reg [47:0] outgoing_eth_dest_mac_reg = 48'd0, outgoing_eth_dest_mac_next;
reg [15:0] outgoing_arp_oper_reg = 16'd0, outgoing_arp_oper_next;
reg [47:0] outgoing_arp_tha_reg = 48'd0, outgoing_arp_tha_next;
reg [31:0] outgoing_arp_tpa_reg = 32'd0, outgoing_arp_tpa_next;
arp_eth_tx #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH)
)
arp_eth_tx_inst (
.clk(clk),
.rst(rst),
// ARP frame input
.s_frame_valid(outgoing_frame_valid_reg),
.s_frame_ready(outgoing_frame_ready),
.s_eth_dest_mac(outgoing_eth_dest_mac_reg),
.s_eth_src_mac(local_mac),
.s_eth_type(16'h0806),
.s_arp_htype(16'h0001),
.s_arp_ptype(16'h0800),
.s_arp_oper(outgoing_arp_oper_reg),
.s_arp_sha(local_mac),
.s_arp_spa(local_ip),
.s_arp_tha(outgoing_arp_tha_reg),
.s_arp_tpa(outgoing_arp_tpa_reg),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy()
);
reg cache_query_request_valid_reg = 1'b0, cache_query_request_valid_next;
reg [31:0] cache_query_request_ip_reg = 32'd0, cache_query_request_ip_next;
wire cache_query_response_valid;
wire cache_query_response_error;
wire [47:0] cache_query_response_mac;
reg cache_write_request_valid_reg = 1'b0, cache_write_request_valid_next;
reg [31:0] cache_write_request_ip_reg = 32'd0, cache_write_request_ip_next;
reg [47:0] cache_write_request_mac_reg = 48'd0, cache_write_request_mac_next;
/*
* ARP cache
*/
arp_cache #(
.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH)
)
arp_cache_inst (
.clk(clk),
.rst(rst),
// Query cache
.query_request_valid(cache_query_request_valid_reg),
.query_request_ready(),
.query_request_ip(cache_query_request_ip_reg),
.query_response_valid(cache_query_response_valid),
.query_response_ready(1'b1),
.query_response_error(cache_query_response_error),
.query_response_mac(cache_query_response_mac),
// Write cache
.write_request_valid(cache_write_request_valid_reg),
.write_request_ready(),
.write_request_ip(cache_write_request_ip_reg),
.write_request_mac(cache_write_request_mac_reg),
// Configuration
.clear_cache(clear_cache)
);
reg arp_request_operation_reg = 1'b0, arp_request_operation_next;
reg arp_request_ready_reg = 1'b0, arp_request_ready_next;
reg [31:0] arp_request_ip_reg = 32'd0, arp_request_ip_next;
reg arp_response_valid_reg = 1'b0, arp_response_valid_next;
reg arp_response_error_reg = 1'b0, arp_response_error_next;
reg [47:0] arp_response_mac_reg = 48'd0, arp_response_mac_next;
reg [5:0] arp_request_retry_cnt_reg = 6'd0, arp_request_retry_cnt_next;
reg [35:0] arp_request_timer_reg = 36'd0, arp_request_timer_next;
assign arp_request_ready = arp_request_ready_reg;
assign arp_response_valid = arp_response_valid_reg;
assign arp_response_error = arp_response_error_reg;
assign arp_response_mac = arp_response_mac_reg;
always @* begin
incoming_frame_ready = 1'b0;
outgoing_frame_valid_next = outgoing_frame_valid_reg && !outgoing_frame_ready;
outgoing_eth_dest_mac_next = outgoing_eth_dest_mac_reg;
outgoing_arp_oper_next = outgoing_arp_oper_reg;
outgoing_arp_tha_next = outgoing_arp_tha_reg;
outgoing_arp_tpa_next = outgoing_arp_tpa_reg;
cache_query_request_valid_next = 1'b0;
cache_query_request_ip_next = cache_query_request_ip_reg;
cache_write_request_valid_next = 1'b0;
cache_write_request_mac_next = cache_write_request_mac_reg;
cache_write_request_ip_next = cache_write_request_ip_reg;
arp_request_ready_next = 1'b0;
arp_request_ip_next = arp_request_ip_reg;
arp_request_operation_next = arp_request_operation_reg;
arp_request_retry_cnt_next = arp_request_retry_cnt_reg;
arp_request_timer_next = arp_request_timer_reg;
arp_response_valid_next = arp_response_valid_reg && !arp_response_ready;
arp_response_error_next = 1'b0;
arp_response_mac_next = 48'd0;
// manage incoming frames
incoming_frame_ready = outgoing_frame_ready;
if (incoming_frame_valid && incoming_frame_ready) begin
if (incoming_eth_type == 16'h0806 && incoming_arp_htype == 16'h0001 && incoming_arp_ptype == 16'h0800) begin
// store sender addresses in cache
cache_write_request_valid_next = 1'b1;
cache_write_request_ip_next = incoming_arp_spa;
cache_write_request_mac_next = incoming_arp_sha;
if (incoming_arp_oper == ARP_OPER_ARP_REQUEST) begin
// ARP request
if (incoming_arp_tpa == local_ip) begin
// send reply frame to valid incoming request
outgoing_frame_valid_next = 1'b1;
outgoing_eth_dest_mac_next = incoming_eth_src_mac;
outgoing_arp_oper_next = ARP_OPER_ARP_REPLY;
outgoing_arp_tha_next = incoming_arp_sha;
outgoing_arp_tpa_next = incoming_arp_spa;
end
end else if (incoming_arp_oper == ARP_OPER_INARP_REQUEST) begin
// INARP request
if (incoming_arp_tha == local_mac) begin
// send reply frame to valid incoming request
outgoing_frame_valid_next = 1'b1;
outgoing_eth_dest_mac_next = incoming_eth_src_mac;
outgoing_arp_oper_next = ARP_OPER_INARP_REPLY;
outgoing_arp_tha_next = incoming_arp_sha;
outgoing_arp_tpa_next = incoming_arp_spa;
end
end
end
end
// manage ARP lookup requests
if (arp_request_operation_reg) begin
arp_request_ready_next = 1'b0;
cache_query_request_valid_next = 1'b1;
arp_request_timer_next = arp_request_timer_reg - 1;
// if we got a response, it will go in the cache, so when the query succeds, we're done
if (cache_query_response_valid && !cache_query_response_error) begin
arp_request_operation_next = 1'b0;
cache_query_request_valid_next = 1'b0;
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b0;
arp_response_mac_next = cache_query_response_mac;
end
// timer timeout
if (arp_request_timer_reg == 0) begin
if (arp_request_retry_cnt_reg > 0) begin
// have more retries
// send ARP request frame
outgoing_frame_valid_next = 1'b1;
outgoing_eth_dest_mac_next = 48'hffffffffffff;
outgoing_arp_oper_next = ARP_OPER_ARP_REQUEST;
outgoing_arp_tha_next = 48'h000000000000;
outgoing_arp_tpa_next = arp_request_ip_reg;
arp_request_retry_cnt_next = arp_request_retry_cnt_reg - 1;
if (arp_request_retry_cnt_reg > 1) begin
arp_request_timer_next = REQUEST_RETRY_INTERVAL;
end else begin
arp_request_timer_next = REQUEST_TIMEOUT;
end
end else begin
// out of retries
arp_request_operation_next = 1'b0;
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b1;
cache_query_request_valid_next = 1'b0;
end
end
end else begin
arp_request_ready_next = !arp_response_valid_next;
if (cache_query_request_valid_reg) begin
cache_query_request_valid_next = 1'b1;
if (cache_query_response_valid) begin
if (cache_query_response_error) begin
arp_request_operation_next = 1'b1;
// send ARP request frame
outgoing_frame_valid_next = 1'b1;
outgoing_eth_dest_mac_next = 48'hffffffffffff;
outgoing_arp_oper_next = ARP_OPER_ARP_REQUEST;
outgoing_arp_tha_next = 48'h000000000000;
outgoing_arp_tpa_next = arp_request_ip_reg;
arp_request_retry_cnt_next = REQUEST_RETRY_COUNT-1;
arp_request_timer_next = REQUEST_RETRY_INTERVAL;
end else begin
cache_query_request_valid_next = 1'b0;
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b0;
arp_response_mac_next = cache_query_response_mac;
end
end
end else if (arp_request_valid && arp_request_ready) begin
if (arp_request_ip == 32'hffffffff) begin
// broadcast address; use broadcast MAC address
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b0;
arp_response_mac_next = 48'hffffffffffff;
end else if (((arp_request_ip ^ gateway_ip) & subnet_mask) == 0) begin
// within subnet
// (no bits differ between request IP and gateway IP where subnet mask is set)
if (~(arp_request_ip | subnet_mask) == 0) begin
// broadcast address; use broadcast MAC address
// (all bits in request IP set where subnet mask is clear)
arp_response_valid_next = 1'b1;
arp_response_error_next = 1'b0;
arp_response_mac_next = 48'hffffffffffff;
end else begin
// unicast address; look up IP directly
cache_query_request_valid_next = 1'b1;
cache_query_request_ip_next = arp_request_ip;
arp_request_ip_next = arp_request_ip;
end
end else begin
// outside of subnet, so look up gateway address
cache_query_request_valid_next = 1'b1;
cache_query_request_ip_next = gateway_ip;
arp_request_ip_next = gateway_ip;
end
end
end
end
always @(posedge clk) begin
if (rst) begin
outgoing_frame_valid_reg <= 1'b0;
cache_query_request_valid_reg <= 1'b0;
cache_write_request_valid_reg <= 1'b0;
arp_request_ready_reg <= 1'b0;
arp_request_operation_reg <= 1'b0;
arp_request_retry_cnt_reg <= 6'd0;
arp_request_timer_reg <= 36'd0;
arp_response_valid_reg <= 1'b0;
end else begin
outgoing_frame_valid_reg <= outgoing_frame_valid_next;
cache_query_request_valid_reg <= cache_query_request_valid_next;
cache_write_request_valid_reg <= cache_write_request_valid_next;
arp_request_ready_reg <= arp_request_ready_next;
arp_request_operation_reg <= arp_request_operation_next;
arp_request_retry_cnt_reg <= arp_request_retry_cnt_next;
arp_request_timer_reg <= arp_request_timer_next;
arp_response_valid_reg <= arp_response_valid_next;
end
cache_query_request_ip_reg <= cache_query_request_ip_next;
outgoing_eth_dest_mac_reg <= outgoing_eth_dest_mac_next;
outgoing_arp_oper_reg <= outgoing_arp_oper_next;
outgoing_arp_tha_reg <= outgoing_arp_tha_next;
outgoing_arp_tpa_reg <= outgoing_arp_tpa_next;
cache_write_request_mac_reg <= cache_write_request_mac_next;
cache_write_request_ip_reg <= cache_write_request_ip_next;
arp_request_ip_reg <= arp_request_ip_next;
arp_response_error_reg <= arp_response_error_next;
arp_response_mac_reg <= arp_response_mac_next;
end
endmodule
`resetall
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/14/2017 09:30:41 AM
// Design Name:
// Module Name: Msg_In
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Msg_In(input clk,
input rst,
input start,
input [31:0]msg_in,
output reg done,
output reg [511:0]msg_out
);
//reg done;
//reg [511:0]msg_out;
reg [9:0]count;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
done <= 0;
msg_out <= 0;
count <= 0;
end else begin
if(start)
if(count < 17)
count <= count + 1;
end
end
always@(count) begin
if(count == 1)
msg_out[511:480] = msg_in;
else if(count == 2)
msg_out[479:448] = msg_in;
else if(count == 3)
msg_out[447:416] = msg_in;
else if(count == 4)
msg_out[415:384] = msg_in;
else if(count == 5)
msg_out[383:352] = msg_in;
else if (count == 6)
msg_out[351:320] = msg_in;
else if (count == 7)
msg_out[319:288] = msg_in;
else if (count == 8)
msg_out[287:256] = msg_in;
else if (count == 9)
msg_out[255:224] = msg_in;
else if (count == 10)
msg_out[223:192] = msg_in;
else if (count == 11)
msg_out[191:160] = msg_in;
else if (count == 12)
msg_out[159:128] = msg_in;
else if (count == 13)
msg_out[127:96] = msg_in;
else if (count == 14)
msg_out[95:64] = msg_in;
else if (count == 15)
msg_out[63:32] = msg_in;
else if (count == 16)
msg_out[31:0] = msg_in;
else if (count == 17)
done = 1;
else begin end
end
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_load_store_unit.v
// Title : Load and store unit
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : Instead of disallowing an instruction cache miss on a data cache
// : miss, both can now occur at the same time. If both occur at same
// : time, then restart address is the address of instruction that
// : caused data cache miss.
// Version : 3.2
// : EBRs use SYNC resets instead of ASYNC resets.
// Version : 3.3
// : Support for new non-cacheable Data Memory that is accessible by
// : the data port and has a one cycle access latency.
// Version : 3.4
// : No change
// Version : 3.5
// : Bug fix: Inline memory is correctly generated if it is not a
// : power-of-two
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_load_store_unit (
// ----- Inputs -------
clk_i,
rst_i,
// From pipeline
stall_a,
stall_x,
stall_m,
kill_x,
kill_m,
exception_m,
store_operand_x,
load_store_address_x,
load_store_address_m,
load_store_address_w,
load_x,
store_x,
load_q_x,
store_q_x,
load_q_m,
store_q_m,
sign_extend_x,
size_x,
`ifdef CFG_DCACHE_ENABLED
dflush,
`endif
`ifdef CFG_IROM_ENABLED
irom_data_m,
`endif
// From Wishbone
d_dat_i,
d_ack_i,
d_err_i,
d_rty_i,
// ----- Outputs -------
// To pipeline
`ifdef CFG_DCACHE_ENABLED
dcache_refill_request,
dcache_restart_request,
dcache_stall_request,
dcache_refilling,
`endif
`ifdef CFG_IROM_ENABLED
irom_store_data_m,
irom_address_xm,
irom_we_xm,
irom_stall_request_x,
`endif
load_data_w,
stall_wb_load,
// To Wishbone
d_dat_o,
d_adr_o,
d_cyc_o,
d_sel_o,
d_stb_o,
d_we_o,
d_cti_o,
d_lock_o,
d_bte_o
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter associativity = 1; // Associativity of the cache (Number of ways)
parameter sets = 512; // Number of sets
parameter bytes_per_line = 16; // Number of bytes per cache line
parameter base_address = 0; // Base address of cachable memory
parameter limit = 0; // Limit (highest address) of cachable memory
// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
localparam addr_offset_lsb = 2;
localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input stall_a; // A stage stall
input stall_x; // X stage stall
input stall_m; // M stage stall
input kill_x; // Kill instruction in X stage
input kill_m; // Kill instruction in M stage
input exception_m; // An exception occured in the M stage
input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address
input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed)
input load_x; // Load instruction in X stage
input store_x; // Store instruction in X stage
input load_q_x; // Load instruction in X stage
input store_q_x; // Store instruction in X stage
input load_q_m; // Load instruction in M stage
input store_q_m; // Store instruction in M stage
input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend
input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word)
`ifdef CFG_DCACHE_ENABLED
input dflush; // Flush the data cache
`endif
`ifdef CFG_IROM_ENABLED
input [`LM32_WORD_RNG] irom_data_m; // Data from Instruction-ROM
`endif
input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
input d_ack_i; // Data Wishbone interface acknowledgement
input d_err_i; // Data Wishbone interface error
input d_rty_i; // Data Wishbone interface retry
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_DCACHE_ENABLED
output dcache_refill_request; // Request to refill data cache
wire dcache_refill_request;
output dcache_restart_request; // Request to restart the instruction that caused a data cache miss
wire dcache_restart_request;
output dcache_stall_request; // Data cache stall request
wire dcache_stall_request;
output dcache_refilling;
wire dcache_refilling;
`endif
`ifdef CFG_IROM_ENABLED
output irom_store_data_m; // Store data to Instruction ROM
wire [`LM32_WORD_RNG] irom_store_data_m;
output [`LM32_WORD_RNG] irom_address_xm; // Load/store address to Instruction ROM
wire [`LM32_WORD_RNG] irom_address_xm;
output irom_we_xm; // Write-enable of 2nd port of Instruction ROM
wire irom_we_xm;
output irom_stall_request_x; // Stall instruction in D stage
wire irom_stall_request_x;
`endif
output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
reg [`LM32_WORD_RNG] load_data_w;
output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface
reg stall_wb_load;
output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data
reg [`LM32_WORD_RNG] d_dat_o;
output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address
reg [`LM32_WORD_RNG] d_adr_o;
output d_cyc_o; // Data Wishbone interface cycle
reg d_cyc_o;
output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select
reg [`LM32_BYTE_SELECT_RNG] d_sel_o;
output d_stb_o; // Data Wishbone interface strobe
reg d_stb_o;
output d_we_o; // Data Wishbone interface write enable
reg d_we_o;
output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type
reg [`LM32_CTYPE_RNG] d_cti_o;
output d_lock_o; // Date Wishbone interface lock bus
reg d_lock_o;
output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
wire [`LM32_BTYPE_RNG] d_bte_o;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
// Microcode pipeline registers - See inputs for description
reg [`LM32_SIZE_RNG] size_m;
reg [`LM32_SIZE_RNG] size_w;
reg sign_extend_m;
reg sign_extend_w;
reg [`LM32_WORD_RNG] store_data_x;
reg [`LM32_WORD_RNG] store_data_m;
reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
wire [`LM32_WORD_RNG] data_m;
reg [`LM32_WORD_RNG] data_w;
`ifdef CFG_DCACHE_ENABLED
wire dcache_select_x; // Select data cache to load from / store to
reg dcache_select_m;
wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
reg dcache_refill_ready; // Indicates the next word of refill data is ready
wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
wire last_word; // Indicates if this is the last word in the cache line
wire [`LM32_WORD_RNG] first_address; // First cache refill address
`endif
`ifdef CFG_DRAM_ENABLED
wire dram_select_x; // Select data RAM to load from / store to
reg dram_select_m;
reg dram_bypass_en; // RAW in data RAM; read latched (bypass) value rather than value from memory
reg [`LM32_WORD_RNG] dram_bypass_data; // Latched value of store'd data to data RAM
wire [`LM32_WORD_RNG] dram_data_out; // Data read from data RAM
wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM: bypass value or value from memory
wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM
`endif
wire wb_select_x; // Select Wishbone to load from / store to
`ifdef CFG_IROM_ENABLED
wire irom_select_x; // Select instruction ROM to load from / store to
reg irom_select_m;
`endif
reg wb_select_m;
reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
reg wb_load_complete; // Indicates when a Wishbone load is complete
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
`ifdef CFG_DRAM_ENABLED
// Data RAM
pmi_ram_dp_true
#(
// ----- Parameters -------
.pmi_family (`LATTICE_FAMILY),
//.pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
//.pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
//.pmi_data_width_a (`LM32_WORD_WIDTH),
//.pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
//.pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
//.pmi_data_width_b (`LM32_WORD_WIDTH),
.pmi_addr_depth_a (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
.pmi_addr_width_a (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
.pmi_data_width_a (`LM32_WORD_WIDTH),
.pmi_addr_depth_b (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
.pmi_addr_width_b (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
.pmi_data_width_b (`LM32_WORD_WIDTH),
.pmi_regmode_a ("noreg"),
.pmi_regmode_b ("noreg"),
.pmi_gsr ("enable"),
.pmi_resetmode ("sync"),
.pmi_init_file (`CFG_DRAM_INIT_FILE),
.pmi_init_file_format (`CFG_DRAM_INIT_FILE_FORMAT),
.module_type ("pmi_ram_dp_true")
)
ram (
// ----- Inputs -------
.ClockA (clk_i),
.ClockB (clk_i),
.ResetA (rst_i),
.ResetB (rst_i),
.DataInA ({32{1'b0}}),
.DataInB (dram_store_data_m),
.AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
.AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
// .ClockEnA (!stall_x & (load_x | store_x)),
.ClockEnA (!stall_x),
.ClockEnB (!stall_m),
.WrA (`FALSE),
.WrB (store_q_m & dram_select_m),
// ----- Outputs -------
.QA (dram_data_out),
.QB ()
);
/*----------------------------------------------------------------------
EBRs cannot perform reads from location 'written to' on the same clock
edge. Therefore bypass logic is required to latch the store'd value
and use it for the load (instead of value from memory).
----------------------------------------------------------------------*/
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
if (rst_i == `TRUE)
begin
dram_bypass_en <= `FALSE;
dram_bypass_data <= 0;
end
else
begin
if (stall_x == `FALSE)
dram_bypass_data <= dram_store_data_m;
if ( (stall_m == `FALSE)
&& (stall_x == `FALSE)
&& (store_q_m == `TRUE)
&& ( (load_x == `TRUE)
|| (store_x == `TRUE)
)
&& (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
)
dram_bypass_en <= `TRUE;
else
if ( (dram_bypass_en == `TRUE)
&& (stall_x == `FALSE)
)
dram_bypass_en <= `FALSE;
end
assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
`endif
`ifdef CFG_DCACHE_ENABLED
// Data cache
lm32_dcache #(
.associativity (associativity),
.sets (sets),
.bytes_per_line (bytes_per_line),
.base_address (base_address),
.limit (limit)
) dcache (
// ----- Inputs -----
.clk_i (clk_i),
.rst_i (rst_i),
.stall_a (stall_a),
.stall_x (stall_x),
.stall_m (stall_m),
.address_x (load_store_address_x),
.address_m (load_store_address_m),
.load_q_m (load_q_m & dcache_select_m),
.store_q_m (store_q_m & dcache_select_m),
.store_data (store_data_m),
.store_byte_select (byte_enable_m & {4{dcache_select_m}}),
.refill_ready (dcache_refill_ready),
.refill_data (wb_data_m),
.dflush (dflush),
// ----- Outputs -----
.stall_request (dcache_stall_request),
.restart_request (dcache_restart_request),
.refill_request (dcache_refill_request),
.refill_address (dcache_refill_address),
.refilling (dcache_refilling),
.load_data (dcache_data_m)
);
`endif
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Select where data should be loaded from / stored to
`ifdef CFG_DRAM_ENABLED
assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_DRAM_LIMIT);
`endif
`ifdef CFG_IROM_ENABLED
assign irom_select_x = (load_store_address_x >= `CFG_IROM_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_IROM_LIMIT);
`endif
`ifdef CFG_DCACHE_ENABLED
assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS)
&& (load_store_address_x <= `CFG_DCACHE_LIMIT)
`ifdef CFG_DRAM_ENABLED
&& (dram_select_x == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_x == `FALSE)
`endif
;
`endif
assign wb_select_x = `TRUE
`ifdef CFG_DCACHE_ENABLED
&& !dcache_select_x
`endif
`ifdef CFG_DRAM_ENABLED
&& !dram_select_x
`endif
`ifdef CFG_IROM_ENABLED
&& !irom_select_x
`endif
;
// Make sure data to store is in correct byte lane
always @(*)
begin
case (size_x)
`LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}};
`LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
`LM32_SIZE_WORD: store_data_x = store_operand_x;
default: store_data_x = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
// Generate byte enable accoring to size of load or store and address being accessed
always @(*)
begin
casez ({size_x, load_store_address_x[1:0]})
{`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001;
{`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010;
{`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100;
{`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000;
{`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
{`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
{`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111;
default: byte_enable_x = 4'bxxxx;
endcase
end
`ifdef CFG_DRAM_ENABLED
// Only replace selected bytes
assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
`endif
`ifdef CFG_IROM_ENABLED
// Only replace selected bytes
assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
`endif
`ifdef CFG_IROM_ENABLED
// Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
// a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
// byte is replaced, and the whole 32-bit value is written back
assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
? load_store_address_m
: load_store_address_x;
// All store instructions perform a write operation in the M stage
assign irom_we_xm = (irom_select_m == `TRUE)
&& (store_q_m == `TRUE);
// A single port in instruction ROM is available to load-store unit for doing loads/stores.
// Since every store requires a load (in X stage) and then a store (in M stage), we cannot
// allow load (or store) instructions sequentially after the store instructions to proceed
// until the store instruction has vacated M stage (i.e., completed the store operation)
assign irom_stall_request_x = (irom_select_x == `TRUE)
&& (store_q_x == `TRUE);
`endif
`ifdef CFG_DCACHE_ENABLED
`ifdef CFG_DRAM_ENABLED
`ifdef CFG_IROM_ENABLED
// WB + DC + DRAM + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: irom_select_m == `TRUE
? irom_data_m
: dcache_data_m;
`else
// WB + DC + DRAM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: dcache_data_m;
`endif
`else
`ifdef CFG_IROM_ENABLED
// WB + DC + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: irom_select_m == `TRUE
? irom_data_m
: dcache_data_m;
`else
// WB + DC
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dcache_data_m;
`endif
`endif
`else
`ifdef CFG_DRAM_ENABLED
`ifdef CFG_IROM_ENABLED
// WB + DRAM + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_select_m == `TRUE
? dram_data_m
: irom_data_m;
`else
// WB + DRAM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: dram_data_m;
`endif
`else
`ifdef CFG_IROM_ENABLED
// WB + IROM
assign data_m = wb_select_m == `TRUE
? wb_data_m
: irom_data_m;
`else
// WB
assign data_m = wb_data_m;
`endif
`endif
`endif
// Sub-word selection and sign/zero-extension for loads
always @(*)
begin
casez ({size_w, load_store_address_w[1:0]})
{`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
{`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
{`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
{`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
{`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
{`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
{`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w;
default: load_data_w = {`LM32_WORD_WIDTH{1'bx}};
endcase
end
// Unused/constant Wishbone signals
assign d_bte_o = `LM32_BTYPE_LINEAR;
`ifdef CFG_DCACHE_ENABLED
// Generate signal to indicate last word in cache line
generate
case (bytes_per_line)
4:
begin
assign first_cycle_type = `LM32_CTYPE_END;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = `TRUE;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
end
8:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = `LM32_CTYPE_END;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
16:
begin
assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
end
endcase
endgenerate
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Data Wishbone interface
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
d_we_o <= `FALSE;
d_cti_o <= `LM32_CTYPE_END;
d_lock_o <= `FALSE;
wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
wb_load_complete <= `FALSE;
stall_wb_load <= `FALSE;
`ifdef CFG_DCACHE_ENABLED
dcache_refill_ready <= `FALSE;
`endif
end
else
begin
`ifdef CFG_DCACHE_ENABLED
// Refill ready should only be asserted for a single cycle
dcache_refill_ready <= `FALSE;
`endif
// Is a Wishbone cycle already in progress?
if (d_cyc_o == `TRUE)
begin
// Is the cycle complete?
if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
begin
`ifdef CFG_DCACHE_ENABLED
if ((dcache_refilling == `TRUE) && (!last_word))
begin
// Fetch next word of cache line
d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
end
else
`endif
begin
// Refill/access complete
d_cyc_o <= `FALSE;
d_stb_o <= `FALSE;
d_lock_o <= `FALSE;
end
`ifdef CFG_DCACHE_ENABLED
d_cti_o <= next_cycle_type;
// If we are performing a refill, indicate to cache next word of data is ready
dcache_refill_ready <= dcache_refilling;
`endif
// Register data read from Wishbone interface
wb_data_m <= d_dat_i;
// Don't set when stores complete - otherwise we'll deadlock if load in m stage
wb_load_complete <= !d_we_o;
end
// synthesis translate_off
if (d_err_i == `TRUE)
$display ("Data bus error. Address: %x", d_adr_o);
// synthesis translate_on
end
else
begin
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
begin
// Start cache refill
d_adr_o <= first_address;
d_cyc_o <= `TRUE;
d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
d_stb_o <= `TRUE;
d_we_o <= `FALSE;
d_cti_o <= first_cycle_type;
//d_lock_o <= `TRUE;
end
else
`endif
if ( (store_q_m == `TRUE)
&& (stall_m == `FALSE)
`ifdef CFG_DRAM_ENABLED
&& (dram_select_m == `FALSE)
`endif
`ifdef CFG_IROM_ENABLED
&& (irom_select_m == `FALSE)
`endif
)
begin
// Data cache is write through, so all stores go to memory
d_dat_o <= store_data_m;
d_adr_o <= load_store_address_m;
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;
d_we_o <= `TRUE;
d_cti_o <= `LM32_CTYPE_END;
end
else if ( (load_q_m == `TRUE)
&& (wb_select_m == `TRUE)
&& (wb_load_complete == `FALSE)
// stall_m will be TRUE, because stall_wb_load will be TRUE
)
begin
// Read requested address
stall_wb_load <= `FALSE;
d_adr_o <= load_store_address_m;
d_cyc_o <= `TRUE;
d_sel_o <= byte_enable_m;
d_stb_o <= `TRUE;
d_we_o <= `FALSE;
d_cti_o <= `LM32_CTYPE_END;
end
end
// Clear load/store complete flag when instruction leaves M stage
if (stall_m == `FALSE)
wb_load_complete <= `FALSE;
// When a Wishbone load first enters the M stage, we need to stall it
if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
stall_wb_load <= `TRUE;
// Clear stall request if load instruction is killed
if ((kill_m == `TRUE) || (exception_m == `TRUE))
stall_wb_load <= `FALSE;
end
end
// Pipeline registers
// X/M stage pipeline registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
sign_extend_m <= `FALSE;
size_m <= 2'b00;
byte_enable_m <= `FALSE;
store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
`ifdef CFG_DCACHE_ENABLED
dcache_select_m <= `FALSE;
`endif
`ifdef CFG_DRAM_ENABLED
dram_select_m <= `FALSE;
`endif
`ifdef CFG_IROM_ENABLED
irom_select_m <= `FALSE;
`endif
wb_select_m <= `FALSE;
end
else
begin
if (stall_m == `FALSE)
begin
sign_extend_m <= sign_extend_x;
size_m <= size_x;
byte_enable_m <= byte_enable_x;
store_data_m <= store_data_x;
`ifdef CFG_DCACHE_ENABLED
dcache_select_m <= dcache_select_x;
`endif
`ifdef CFG_DRAM_ENABLED
dram_select_m <= dram_select_x;
`endif
`ifdef CFG_IROM_ENABLED
irom_select_m <= irom_select_x;
`endif
wb_select_m <= wb_select_x;
end
end
end
// M/W stage pipeline registers
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
size_w <= 2'b00;
data_w <= {`LM32_WORD_WIDTH{1'b0}};
sign_extend_w <= `FALSE;
end
else
begin
size_w <= size_m;
data_w <= data_m;
sign_extend_w <= sign_extend_m;
end
end
/////////////////////////////////////////////////////
// Behavioural Logic
/////////////////////////////////////////////////////
// synthesis translate_off
// Check for non-aligned loads or stores
always @(posedge clk_i)
begin
if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE))
begin
if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
$display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
$display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
end
end
// synthesis translate_on
endmodule
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