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// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_auto_pc_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_16_V
`define SKY130_FD_SC_HD__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__bufbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_16_V
|
(* Copyright (c) 2008, Harvard University
* All rights reserved.
*
* Author: Greg Morrisett
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* - The names of contributors may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*)
Require Import String.
Require Import List.
Require Import Ascii.
Require Import Omega.
(*Require Import Eqdep.*)
Require Import Data.Stream.
Set Implicit Arguments.
(* This section defines grammars and parsers -- should be turned into a
* functor over the char and char_eq variables.
*)
Section PARSE.
Variable char : Set.
Variable char_eq : forall (c1 c2:char), {c1 = c2} + {c1 <> c2}.
Section GRAMMAR.
(* We describe the syntax of grammars using Adam's approach from ltamer *)
Section VARS.
Variable var : Set -> Type.
Inductive term: Set -> Type :=
| GVar : forall t:Set, var t -> term t
| GEpsilon : forall t:Set, t -> term t
| GSatisfy : (char -> bool) -> term char
| GCat : forall (t1 t2:Set), term t1 -> term t2 -> term (t1 * t2)
| GAlt : forall t, term t -> term t -> term t
| GTry : forall t, term t -> term t
| GRec : forall t:Set, (var t -> term t) -> term t
| GMap : forall (t1 t2:Set), (t1 -> t2) -> term t1 -> term t2.
(* A relational definition of substitution for terms -- used in the definition
* of the semantics below, in particular for the rec case *)
Inductive Subst :
forall (t1 t2:Set), (var t1->term t2)->(term t1)->(term t2)->Type :=
| SEpsilon : forall (t1 t2:Set) (v:t2) (e:term t1),
Subst (fun _ => GEpsilon v) e (GEpsilon v)
| SSatisfy : forall t1 (f:char->bool) (e:term t1),
Subst (fun _ => GSatisfy f) e (GSatisfy f)
| SCat :
forall t1 t2 t3 (f1:var t1 -> term t2) (f2:var t1 -> term t3) (e:term t1)
(e1:term t2)(e2:term t3),
Subst f1 e e1 -> Subst f2 e e2 ->
Subst (fun v => GCat (f1 v) (f2 v)) e (GCat e1 e2)
| SAlt :
forall t1 t2 (f1 f2:var t1 -> term t2) (e:term t1)(e1 e2:term t2),
Subst f1 e e1 -> Subst f2 e e2 ->
Subst (fun v => GAlt (f1 v) (f2 v)) e (GAlt e1 e2)
| SMap :
forall (t1 t2 t3:Set)
(f:var t1 -> term t2) (e:term t1) (g:t2->t3) (e1:term t2),
Subst f e e1 ->
Subst (fun v => GMap g (f v)) e (GMap g e1)
| STry :
forall t1 t2 (f1:var t1 -> term t2) (e : term t1) (e1:term t2),
Subst f1 e e1 -> Subst (fun v => GTry (f1 v)) e (GTry e1)
| SVarEq :
forall t (e:term t), Subst (@GVar t) e e
| SVarNeq :
forall t1 t2 (v:var t2) (e:term t1), Subst (fun _ => GVar v) e (GVar v)
| SRec :
forall t1 t2 (f1:var t1->var t2->term t2) (f2:var t2->term t2)(e:term t1),
(forall v', Subst (fun v => f1 v v') e (f2 v')) ->
Subst (fun v => GRec (f1 v)) e (GRec f2).
End VARS.
Definition Term t := forall V, term V t.
Implicit Arguments GVar [var t].
Implicit Arguments GEpsilon [var t].
Implicit Arguments GSatisfy [var].
Implicit Arguments GCat [var t1 t2].
Implicit Arguments GAlt [var t].
Implicit Arguments GTry [var t].
Implicit Arguments GRec [var t].
Implicit Arguments GMap [var t1 t2].
Fixpoint flatten(V:Set->Type)(t:Set)(e: term (term V) t) {struct e} : term V t :=
match e in (term _ t) return (term V t) with
| GVar _ v => v
| GEpsilon t v => GEpsilon v
| GSatisfy f => GSatisfy f
| GCat t1 t2 e1 e2 => GCat (flatten e1) (flatten e2)
| GAlt t e1 e2 => GAlt (flatten e1) (flatten e2)
| GMap t1 t2 f e => GMap f (flatten e)
| GTry t e => GTry (flatten e)
| GRec t f => GRec (fun (v:V t) => flatten (f (GVar v)))
end.
Definition unroll(t:Set)(f:forall V, V t -> term V t) : Term t :=
fun V => flatten (f (term V) (GRec (f V))).
Inductive empty_set : Set := .
Definition empvar := (fun _:Set => empty_set).
(* It would be nice if we could prove the following axiom so that the definition
* of Gfix was simpler:
Axiom Unroll : forall (t:Set)(f:forall var, var t -> term var t),
Subst (f empvar) (GRec (f empvar)) (unroll f empvar).
*)
Inductive consumed_t : Set := Consumed | NotConsumed.
Inductive reply_t(a:Set) : Set :=
| Okay : consumed_t -> a -> list char -> reply_t a
| Error : consumed_t -> reply_t a.
Implicit Arguments Error [a].
Definition join_cons (nc1 nc2 : consumed_t) : consumed_t :=
match (nc1, nc2) with
| (Consumed, _) => Consumed
| (_, Consumed) => Consumed
| (_, _) => NotConsumed
end.
(* We give meaning to grammars here, following the style of Parsec combinators.
* In particular, note that we only try the second grammar of an alternation when
* the first one does not consume input. The presentation here is slightly different
* from Parsec in that (a) we don't worry about space leaks since this is intended
* for specification only, and (b) instead of representing concatenation with a
* bind-like construct, we simply return a pair of the results. We have a separate
* operation GMap that allows us to transform a t1 grammar to a t2 grammar. The
* intention here is that grammars should use a minimum of meta-level stuff in
* revealing their structure, so that we can potentially analyze and transform them.
*)
Section DENOTE.
(* What I'm doing here is defining a denotational semantics that maps grammar terms
* down to a simpler language with a monadic structure. Then we give an operational
* semantics to the monadic structure. Note that I've instantiated the var in the
* phoas so that it always yields an empty set. This ensures that the term does not
* have a free variable. *)
Inductive M: Set -> Type :=
| MReturn : forall t, reply_t t -> M t
| MBind : forall t1 t2, M t1 -> (reply_t t1 -> M t2) -> M t2
| MFix : forall t (f:empvar t -> term empvar t), list char -> M t.
Notation "'Return' x" := (MReturn x) (at level 75) : gdenote_scope.
Notation "x <- c1 ; c2" := (MBind c1 (fun x => c2))
(right associativity, at level 84, c1 at next level) : gdenote_scope.
Definition wfCoerce (t:Set)(v:empvar t) : M t := match v with end.
Open Local Scope gdenote_scope.
(* here we map a term e to a computation over lists of characters -- this is
* essentially the same as with Parsec-style combinators, though I've chosen
* slightly different combinators that are closer to arrows than the monadic
* interpretation. *)
Fixpoint denote(t:Set)(e:term empvar t)(s:list char) {struct e} : M t :=
match e in term _ t return M t with
| GVar _ v => wfCoerce v
| GEpsilon _ x => Return Okay NotConsumed x s
| GSatisfy test =>
Return match s with
| c :: cs => if (test c) then Okay Consumed c cs else
Error NotConsumed
| nil => Error NotConsumed
end
| GMap t1 t2 f e =>
r <- denote e s ;
Return match r with
| Okay nc v s2 => Okay nc (f v) s2
| Error nc => Error nc
end
| GTry t e =>
r <- denote e s ;
Return match r with
| Error Consumed => Error NotConsumed
| Okay Consumed v s2 => Okay NotConsumed v s2
| _ => r
end
| GCat t1 t2 e1 e2 =>
r1 <- denote e1 s ;
match r1 with
| Error nc => Return Error nc
| Okay nc1 v1 s1 =>
r2 <- denote e2 s1 ;
Return match r2 with
| Error nc2 => Error (join_cons nc1 nc2)
| Okay nc2 v2 s2 => Okay (join_cons nc1 nc2) (v1,v2) s2
end
end
| GAlt t e1 e2 =>
r1 <- denote e1 s ;
match r1 with
| Error Consumed => Return Error Consumed
| Error NotConsumed => denote e2 s
| Okay NotConsumed v s2 =>
r2 <- denote e2 s ;
Return match r2 with
| Error NotConsumed => Okay NotConsumed v s2
| Okay NotConsumed _ _ => Okay NotConsumed v s2
| r2 => r2
end
| Okay Consumed v s2 => Return Okay Consumed v s2
end
| GRec t f => MFix f s
end.
(* We now give an operational semantics to the monadic terms generated by the
* denotation function. Note that in essence, we just delay unrolling the
* fix operator. *)
Inductive evals : forall t, M t -> reply_t t -> Prop :=
| eMReturn : forall t (r:reply_t t), evals (MReturn r) r
| eMBind : forall t1 t2 (c:M t1) (r1:reply_t t1) (f:reply_t t1 -> M t2) r2,
evals c r1 -> evals (f r1) r2 -> evals (MBind c f) r2
| eMFix :
forall t (f:empvar t -> term empvar t) (s:list char) (e:term empvar t) (r:reply_t t),
Subst f (GRec f) e -> evals (denote e s) r -> evals (MFix f s) r.
(* Then we say that a term t parses string s yielding result r if the following
* if evaluating the denotation of e, when applied to s yields r. *)
Definition parses(t:Set)(e:Term t)(s:list char)(r:reply_t t) :=
evals (denote (e empvar) s) r.
End DENOTE.
End GRAMMAR.
Require Import Ynot.
Inductive parse_reply_t(t:Set) : Set :=
| OKAY : consumed_t -> nat -> t -> parse_reply_t t
| ERROR : consumed_t -> string -> parse_reply_t t.
Fixpoint nthtail(A:Type)(cs:list A)(n:nat) {struct n} : list A :=
match (n,cs) with
| (0,cs) => cs
| (S n, c::cs) => nthtail cs n
| (S n, nil) => nil
end.
Definition okay(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t)(m:nat)(v:t) :=
(n ~~ let elts := stream_elts i in
elts ~~ [parses e (nthtail elts n) (Okay c v (nthtail elts (m+n)))])%hprop.
Definition okaystr(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t)(m:nat)(v:t) :=
(okay n i e c m v * (n ~~ rep i (m+n)))%hprop.
Definition error(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t) :=
(n ~~ let elts := stream_elts i in
elts ~~ [parses e (nthtail elts n) (Error t c)])%hprop.
Definition errorstr(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t) :=
(error n i e c * (Exists m :@ nat, rep i m))%hprop.
Definition ans_correct(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(ans:parse_reply_t t) :=
match ans with
| OKAY c m v => okay n i e c m v
| ERROR c _ => error n i e c
end.
Definition ans_str_correct(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(ans:parse_reply_t t) :=
match ans with
| OKAY c m v => okaystr n i e c m v
| ERROR c _ => errorstr n i e c
end.
Definition parser_t(t:Set)(e:Term t) :=
forall (ins:instream_t char)(n:[nat]), STsep (n ~~ rep ins n) (ans_str_correct n ins e).
Implicit Arguments parser_t [t].
Open Local Scope stsep_scope.
Lemma EmpImpInj(P:Prop) :
P -> __ ==> [P].
Proof.
intros. sep fail auto.
Qed.
Lemma NthErrorNoneNthTail(A:Type)(i:nat)(vs:list A) :
nth_error vs i = None -> nthtail vs i = nil.
Proof.
induction i ; destruct vs ; auto ; simpl ; intros. unfold value in H. congruence.
apply IHi. auto.
Qed.
Lemma NthErrorSomeNthTail(A:Type)(i:nat)(vs:list A)(v:A) :
nth_error vs i = Some v ->
exists vs1, exists vs2, vs = vs1 ++ v::vs2 /\ nthtail vs i = v::vs2.
Proof.
induction i ; destruct vs ; auto ; simpl ; intros. unfold Specif.error in H. congruence.
unfold value in H. inversion H. subst. exists (nil(A:=A)). simpl. eauto.
unfold Specif.error in H. congruence. pose (IHi _ _ H). destruct e as [vs1 [vs2 [H1 H2]]].
exists (a::vs1). exists vs2. split. rewrite H1. simpl. auto. auto.
Qed.
Lemma NthTailSucc(A:Type)(i:nat)(vs vs2:list A)(v:A) :
nthtail vs i = v::vs2 -> nthtail vs (S i) = vs2.
Proof.
induction i ; simpl ; intros. rewrite H. auto. destruct vs. congruence.
pose (IHi _ _ _ H). apply e.
Qed.
Lemma PlusAssoc(n m p:nat) : n + (m + p) = n + m + p. intros ; omega. Qed.
Ltac mysep :=
match goal with
| [ |- (__ ==> [ _ ])%hprop ] => apply EmpImpInj
| [ |- evals (MReturn ?r) ?r ] => constructor
| [ |- evals (MBind _ _) _] => econstructor
| [ |- context[?n + (?m + ?p)]] => rewrite (PlusAssoc n m p)
| [ |- context[if (?f ?c) then _ else _] ] =>
let H := fresh "H" in
assert (H: f c = true \/ f c = false) ; [ destruct (f c) ; tauto |
destruct H ; [ rewrite H ; simpl | rewrite H ; simpl ]]
| _ => auto
end.
Definition gsatisfy(f:char -> bool) vars := GSatisfy vars f.
Definition gepsilon(t:Set)(v:t) vars := GEpsilon vars v.
Definition galt(t:Set)(e1 e2:Term t) vars := GAlt (e1 vars) (e2 vars).
Definition gmap(t1 t2:Set)(f:t1 -> t2)(e:Term t1) vars := GMap f (e vars).
Definition gcat(t1 t2:Set)(e1:Term t1)(e2:Term t2) vars := GCat (e1 vars) (e2 vars).
Definition gtry(t:Set)(e:Term t) vars := GTry (e vars).
Definition grec(t:Set)(f:forall (var:Set->Type), var t -> term var t)(var:Set -> Type) :=
GRec (f var).
Ltac myunfold := unfold ans_str_correct, ans_correct, okaystr, okay, errorstr, error,
parses, gsatisfy, gepsilon, galt, gmap, gcat, gtry, grec.
Ltac psimp := (myunfold ; sep fail auto ; mysep ; simpl ; eauto).
Ltac rsimp := psimp ;
match goal with
| [ |- context[match ?a with | OKAY c m v => _ | ERROR c _ => _ end] ] => destruct a
| [ |- context[match ?c with | Consumed => _ | NotConsumed => _ end] ] => destruct c
| _ => idtac
end.
Lemma NthError(x:list char)(n:nat) :
(nth_error x n = None \/ exists c, nth_error x n = Some c).
Proof. intros. destruct (nth_error x n). right. eauto. left. eauto.
Qed.
Lemma EvalsMReturn(t:Set)(r1 r2:reply_t t) : r1 = r2 -> evals (MReturn r1) r2.
Proof. intros. rewrite <- H. constructor. Qed.
(* the parser for a single character *)
Definition satisfy(f:char -> bool) : parser_t (gsatisfy f).
intros f instream n.
refine (copt <- next instream n ;
Return (match copt with
| None => ERROR char NotConsumed "bad character"
| Some c => if f c then OKAY Consumed 1 c
else ERROR char NotConsumed "bad character"
end) <@>
match copt with
| None => errorstr n instream (gsatisfy f) NotConsumed
| Some c => if f c then okaystr n instream (gsatisfy f) Consumed 1 c
else errorstr n instream (gsatisfy f) NotConsumed
end @> _) ; psimp ;
match goal with
[ |- _ ==> match nth_error ?x ?n with | Some c => _ | None => _ end] =>
let H := fresh in pose (H := NthError x n) ; destruct H ; [ rewrite H ; psimp ;
rewrite (NthErrorNoneNthTail _ _ H) ; psimp | destruct H ; rewrite H ; psimp ; psimp ;
let H1 := fresh in let v1 := fresh in let v2 := fresh in
let H2 := fresh in let H3 := fresh in
pose (H1 := NthErrorSomeNthTail _ _ H) ; destruct H1 as [v1 [v2 [H1 H2]]] ;
rewrite H2 ; psimp ; pose (H3 := (NthTailSucc _ _ H2)) ;
simpl in H3 ; eapply EvalsMReturn ; congruence]
| [ |- match ?copt with | Some c => _ | None => _ end ==> _] => destruct copt ;
repeat psimp
end.
Defined.
(* the parser for the empty string *)
Definition epsilon(t:Set)(v:t) : parser_t (gepsilon v).
intros t v instream n.
refine ({{Return (OKAY NotConsumed 0 v) <@> (n ~~ rep instream n)}}) ;
repeat psimp.
Defined.
(* left-biased alternation -- need to fix error message propagation here *)
Definition alt(t:Set)(e1 e2:Term t)(p1:parser_t e1)(p2:parser_t e2) : parser_t (galt e1 e2).
intros t e1 e2 p1 p2 instream n.
unfold galt.
refine (n0 <- position instream n @> (fun n0 => n ~~ rep instream n * [n0=n])%hprop ;
ans1 <- p1 instream n <@> (n ~~ [n0=n])%hprop @>
(fun ans1 => ans_str_correct n instream e1 ans1 * (n ~~ [n0=n]))%hprop ;
let frame := fun ans => ((n ~~ [n0=n]) * ans_correct n instream e1 ans)%hprop in
match ans1 as ans1'
return STsep (ans_str_correct n instream e1 ans1' * (n ~~ [n0=n]))%hprop
(ans_str_correct n instream (galt e1 e2))
with
| ERROR NotConsumed msg1 =>
seek instream n0 <@> frame (ERROR t NotConsumed msg1) ;;
p2 instream n <@> frame (ERROR t NotConsumed msg1) @> _
| OKAY NotConsumed m1 v1 =>
seek instream n0 <@> frame (OKAY NotConsumed m1 v1) ;;
ans2 <- p2 instream n <@> frame (OKAY NotConsumed m1 v1) ;
match ans2 as ans2'
return STsep (frame (OKAY NotConsumed m1 v1) *
ans_str_correct n instream e2 ans2')
(ans_str_correct n instream (galt e1 e2))
with
| ERROR NotConsumed msg2 =>
(* interestingly, I forgot to do the seek here and in the next
case and then got stuck doing the proof! *)
seek instream (m1 + n0) <@>
frame (OKAY NotConsumed m1 v1) *
ans_correct n instream e2 (ERROR t NotConsumed msg2) ;;
Return OKAY NotConsumed m1 v1 <@>
frame (OKAY NotConsumed m1 v1) *
rep instream (m1 + n0) *
ans_correct n instream e2 (ERROR t NotConsumed msg2) @> _
| OKAY NotConsumed m2 v2 =>
seek instream (m1 + n0) <@>
frame (OKAY NotConsumed m1 v1) *
ans_correct n instream e2 (OKAY NotConsumed m2 v2) ;;
Return OKAY NotConsumed m1 v1 <@>
frame (OKAY NotConsumed m1 v1) *
rep instream (m1 + n0) *
ans_correct n instream e2 (OKAY NotConsumed m2 v2) @> _
| ans =>
{{Return ans <@>
frame (OKAY NotConsumed m1 v1) * ans_str_correct n instream e2 ans}}
end
| ans =>
{{Return ans <@>
((n ~~ [n0=n]) * ans_str_correct n instream e1 ans)%hprop}}
end) ; (try unfold frame) ; repeat rsimp.
Defined.
(* the parser for (gmap f e) given f and a parser p for e *)
Definition map(t1 t2:Set)(f:t1->t2)(e:Term t1)(p:parser_t e) : parser_t (gmap f e).
intros t1 t2 f e p instream n.
refine (ans <- p instream n;
Return (match ans with
| OKAY c m v => OKAY c m (f v)
| ERROR c msg => ERROR t2 c msg
end) <@> ans_str_correct n instream e ans @> _) ; psimp.
destruct ans ; repeat psimp.
Defined.
(* parser for concatenation *)
Definition cat(t1 t2:Set)(e1:Term t1)(e2:Term t2)(p1:parser_t e1)(p2:parser_t e2) :
parser_t (gcat e1 e2).
intros t1 t2 e1 e2 p1 p2 instream n.
refine (n0 <- position instream n ;
ans1 <- p1 instream n <@> (n ~~ [n0 = n])%hprop ;
match ans1 as ans1' return
STsep (ans_str_correct n instream e1 ans1' * (n ~~ [n0 = n])%hprop)
(ans_str_correct n instream (gcat e1 e2))
with
| OKAY c1 m1 v1 =>
ans2 <- p2 instream (inhabits (m1+n0))<@>
(ans_correct n instream e1 (OKAY c1 m1 v1) * (n ~~ [n0=n]))%hprop;
Return match ans2 with
| OKAY c2 m2 v2 => OKAY (join_cons c1 c2) (m2 + m1) (v1,v2)
| ERROR c2 msg => ERROR (t1*t2)%type (join_cons c1 c2) msg
end <@>
(ans_correct n instream e1 (OKAY c1 m1 v1) * (n ~~ [n0=n]) *
ans_str_correct (inhabits (m1+n0)) instream e2 ans2)%hprop @> _
| ERROR c1 msg =>
{{Return ERROR (t1*t2) c1 msg <@>
(ans_str_correct n instream e1 (ERROR t1 c1 msg) * (n ~~ [n0 = n]))%hprop}}
end) ; repeat rsimp.
Defined.
(* try combinator *)
Definition try(t:Set)(e:Term t)(p:parser_t e) : parser_t (gtry e).
intros t e p instream n.
refine (ans <- p instream n ;
Return match ans with
| ERROR Consumed msg => ERROR t NotConsumed msg
| OKAY Consumed m v => OKAY NotConsumed m v
| ans => ans
end <@> ans_str_correct n instream e ans @> _) ; psimp.
destruct ans ; destruct c ; repeat psimp.
Defined.
(* used in construction of fixed-point *)
Definition coerce_parse_fn(t:Set)(f:forall var, var t -> term var t)(e:Term t)
(H:Subst (f empvar) (GRec (f empvar)) (e empvar))
(F:parser_t (grec f) -> parser_t e) :
parser_t (grec f) -> parser_t (grec f).
intros t f e H1 F p instream n.
refine ((F p instream n) @> _). destruct v ; psimp ; econstructor ; eauto.
Qed.
Definition parser_t'(t:Set)(e:Term t)(p:(instream_t char * [nat])) :=
let ins := fst p in
let n := snd p in
STsep (n ~~ rep ins n) (ans_str_correct n ins e).
(* Alas, note that we need H here -- can't easily prove this once and for all *)
Definition Gfix(t:Set)(f:forall V, V t -> term V t)
(F:parser_t (grec f) -> parser_t (unroll f))
(H: Subst (f empvar) (GRec (f empvar)) (unroll f empvar)) :
parser_t (grec f) :=
(* coerce F so that its result is re-rolled *)
let Fc : parser_t (grec f) -> parser_t (grec f) := coerce_parse_fn H F in
(* Grrr. To call SepFix, I have to uncurry Fc *)
let Fu : (forall p, parser_t' (grec f) p) -> (forall p, parser_t' (grec f) p) :=
fun f arg => Fc (fun ins n => f (ins,n)) (fst arg) (snd arg) in
fun instream n => (SepFix _ _ Fu) (instream,n).
Implicit Arguments Gfix [t f].
End PARSE.
Section Examples.
Delimit Scope grammar_scope with grammar.
Notation "!!!! v" := (GVar _ _ _ v) (at level 1) : grammar_scope.
Notation "# c" := (GSatisfy(char:=ascii) _
(fun c2 => if ascii_dec (c%char) c2 then true else false))
(at level 1) : grammar_scope.
Notation "e1 ^ e2" := (GCat e1 e2)
(right associativity, at level 30) : grammar_scope.
Notation "e @ f" := (GMap f e)
(left associativity, at level 78) : grammar_scope.
Notation "e1 '|||' e2" := (GAlt e1 e2)
(right associativity, at level 79) : grammar_scope.
Notation "% v" := (GEpsilon ascii _ v) (at level 1) : grammar_scope.
Delimit Scope parser_scope with parser.
Notation "e1 ^ e2" := (cat e1 e2)
(right associativity, at level 30) : parser_scope.
Notation "e @ f" := (map f e)
(left associativity, at level 78) : parser_scope.
Notation "e1 '|||' e2" := (alt e1 e2)
(right associativity, at level 79) : parser_scope.
Notation "# c" := (satisfy (fun c2 => if ascii_dec (c%char) c2 then true else false))
(at level 1) : parser_scope.
Notation "% v" := (epsilon(char:=ascii) v) : parser_scope.
Notation "'gfix' e" := (Gfix e _) (at level 70).
Ltac gtac := unfold unroll, grec ; simpl ; repeat (progress constructor).
(* Example grammar : N -> a | b N b *)
Definition g : Term ascii unit :=
grec (fun var N => #"a" @ (fun _ => tt)
||| #"b" ^ !!!!N ^ #"b" @ (fun _ => tt))%grammar.
(* Example parser for grammar g *)
Definition g_parser : parser_t g.
refine (gfix (fun (p:parser_t g) =>
#"a" @ (fun _ => tt)
||| #"b" ^ p ^ #"b" @ (fun _ => tt))%parser) ;
gtac.
Defined.
(* A grammar for digits *)
Definition is_digit(c:ascii):bool :=
if le_lt_dec (nat_of_ascii "0"%char) (nat_of_ascii c) then
(if le_lt_dec (nat_of_ascii c) (nat_of_ascii "9"%char) then true else false)
else false.
Definition digit : Term ascii ascii := gsatisfy is_digit.
(* A parser for digits *)
Definition digit_p : parser_t digit := satisfy is_digit.
(* A grammar for numbers: note that this computes the value of the number *)
Definition number :=
grec (fun V number =>
digit _ @ nat_of_ascii
||| !!!!number ^ digit _ @ (fun p => 10 * fst p + nat_of_ascii (snd p)))%grammar.
(* A parser for numbers: number := digit | number digit *)
Definition number_p : parser_t number.
refine (gfix (fun (number:parser_t number) =>
digit_p @ nat_of_ascii
||| number ^ digit_p @ (fun p => 10 * fst p + nat_of_ascii (snd p)))%parser).
unfold digit, gsatisfy. gtac.
Defined.
Definition tab : ascii := ascii_of_nat 9.
Definition cr : ascii := ascii_of_nat 10.
(* whitespace *)
Definition ws :=
grec (fun V ws =>
% tt
||| (#" " ^ !!!!ws ||| #tab ^ !!!!ws ||| #cr ^ !!!!ws) @ (fun _ => tt))%grammar.
Definition ws_p : parser_t ws.
refine (gfix (fun (ws_p:parser_t ws) =>
% tt
||| (#" " ^ ws_p ||| #tab ^ ws_p ||| #cr ^ ws_p) @ (fun _ => tt))%parser).
gtac.
Defined.
(* A grammar for expressions that computes the result of evaluating the expression:
expr := number | expr + expr | expr - expr *)
Definition expr :=
grec (fun V expr =>
ws _ ^ number _ ^ ws _ @ (fun t => fst (snd t))
||| !!!!expr ^ #"+" ^ !!!!expr @ (fun t => fst t + (snd (snd t)))
||| !!!!expr ^ #"-" ^ !!!!expr @ (fun t => fst t - (snd (snd t))))%grammar.
(* A parser for expressions *)
Definition expr_p : parser_t expr.
refine (gfix (fun (expr_p:parser_t expr) =>
ws_p ^ number_p ^ ws_p @ (fun t => fst (snd t))
||| expr_p ^ #"+" ^ expr_p @ (fun t => fst t + (snd (snd t)))
||| expr_p ^ #"-" ^ expr_p @ (fun t => fst t - (snd (snd t))))%parser).
unfold number, digit, ws, gsatisfy ; gtac.
Defined.
End Examples.
|
module DE1_SoC_Computer (
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
CLOCK_50,
CLOCK2_50,
CLOCK3_50,
CLOCK4_50,
// ADC
ADC_CS_N,
ADC_DIN,
ADC_DOUT,
ADC_SCLK,
// Audio
AUD_ADCDAT,
AUD_ADCLRCK,
AUD_BCLK,
AUD_DACDAT,
AUD_DACLRCK,
AUD_XCK,
// SDRAM
DRAM_ADDR,
DRAM_BA,
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ,
DRAM_LDQM,
DRAM_RAS_N,
DRAM_UDQM,
DRAM_WE_N,
// I2C Bus for Configuration of the Audio and Video-In Chips
FPGA_I2C_SCLK,
FPGA_I2C_SDAT,
// 40-Pin Headers
GPIO_0,
GPIO_1,
// Seven Segment Displays
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
// IR
IRDA_RXD,
IRDA_TXD,
// Pushbuttons
KEY,
// LEDs
LEDR,
// PS2 Ports
PS2_CLK,
PS2_DAT,
PS2_CLK2,
PS2_DAT2,
// Slider Switches
SW,
// Video-In
TD_CLK27,
TD_DATA,
TD_HS,
TD_RESET_N,
TD_VS,
// VGA
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_G,
VGA_HS,
VGA_R,
VGA_SYNC_N,
VGA_VS,
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
HPS_DDR3_ADDR,
HPS_DDR3_BA,
HPS_DDR3_CAS_N,
HPS_DDR3_CKE,
HPS_DDR3_CK_N,
HPS_DDR3_CK_P,
HPS_DDR3_CS_N,
HPS_DDR3_DM,
HPS_DDR3_DQ,
HPS_DDR3_DQS_N,
HPS_DDR3_DQS_P,
HPS_DDR3_ODT,
HPS_DDR3_RAS_N,
HPS_DDR3_RESET_N,
HPS_DDR3_RZQ,
HPS_DDR3_WE_N,
// Ethernet
HPS_ENET_GTX_CLK,
HPS_ENET_INT_N,
HPS_ENET_MDC,
HPS_ENET_MDIO,
HPS_ENET_RX_CLK,
HPS_ENET_RX_DATA,
HPS_ENET_RX_DV,
HPS_ENET_TX_DATA,
HPS_ENET_TX_EN,
// Flash
HPS_FLASH_DATA,
HPS_FLASH_DCLK,
HPS_FLASH_NCSO,
// Accelerometer
HPS_GSENSOR_INT,
// General Purpose I/O
HPS_GPIO,
// I2C
HPS_I2C_CONTROL,
HPS_I2C1_SCLK,
HPS_I2C1_SDAT,
HPS_I2C2_SCLK,
HPS_I2C2_SDAT,
// Pushbutton
HPS_KEY,
// LED
HPS_LED,
// SD Card
HPS_SD_CLK,
HPS_SD_CMD,
HPS_SD_DATA,
// SPI
HPS_SPIM_CLK,
HPS_SPIM_MISO,
HPS_SPIM_MOSI,
HPS_SPIM_SS,
// UART
HPS_UART_RX,
HPS_UART_TX,
// USB
HPS_CONV_USB_N,
HPS_USB_CLKOUT,
HPS_USB_DATA,
HPS_USB_DIR,
HPS_USB_NXT,
HPS_USB_STP
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
////////////////////////////////////
// FPGA Pins
////////////////////////////////////
// Clock pins
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input CLOCK4_50;
// ADC
inout ADC_CS_N;
output ADC_DIN;
input ADC_DOUT;
output ADC_SCLK;
// Audio
input AUD_ADCDAT;
inout AUD_ADCLRCK;
inout AUD_BCLK;
output AUD_DACDAT;
inout AUD_DACLRCK;
output AUD_XCK;
// SDRAM
output [12: 0] DRAM_ADDR;
output [ 1: 0] DRAM_BA;
output DRAM_CAS_N;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CS_N;
inout [15: 0] DRAM_DQ;
output DRAM_LDQM;
output DRAM_RAS_N;
output DRAM_UDQM;
output DRAM_WE_N;
// I2C Bus for Configuration of the Audio and Video-In Chips
output FPGA_I2C_SCLK;
inout FPGA_I2C_SDAT;
// 40-pin headers
inout [35: 0] GPIO_0;
inout [35: 0] GPIO_1;
// Seven Segment Displays
output [ 6: 0] HEX0;
output [ 6: 0] HEX1;
output [ 6: 0] HEX2;
output [ 6: 0] HEX3;
output [ 6: 0] HEX4;
output [ 6: 0] HEX5;
// IR
input IRDA_RXD;
output IRDA_TXD;
// Pushbuttons
input [ 3: 0] KEY;
// LEDs
output [ 9: 0] LEDR;
// PS2 Ports
inout PS2_CLK;
inout PS2_DAT;
inout PS2_CLK2;
inout PS2_DAT2;
// Slider Switches
input [ 9: 0] SW;
// Video-In
input TD_CLK27;
input [ 7: 0] TD_DATA;
input TD_HS;
output TD_RESET_N;
input TD_VS;
// VGA
output [ 7: 0] VGA_B;
output VGA_BLANK_N;
output VGA_CLK;
output [ 7: 0] VGA_G;
output VGA_HS;
output [ 7: 0] VGA_R;
output VGA_SYNC_N;
output VGA_VS;
////////////////////////////////////
// HPS Pins
////////////////////////////////////
// DDR3 SDRAM
output [14: 0] HPS_DDR3_ADDR;
output [ 2: 0] HPS_DDR3_BA;
output HPS_DDR3_CAS_N;
output HPS_DDR3_CKE;
output HPS_DDR3_CK_N;
output HPS_DDR3_CK_P;
output HPS_DDR3_CS_N;
output [ 3: 0] HPS_DDR3_DM;
inout [31: 0] HPS_DDR3_DQ;
inout [ 3: 0] HPS_DDR3_DQS_N;
inout [ 3: 0] HPS_DDR3_DQS_P;
output HPS_DDR3_ODT;
output HPS_DDR3_RAS_N;
output HPS_DDR3_RESET_N;
input HPS_DDR3_RZQ;
output HPS_DDR3_WE_N;
// Ethernet
output HPS_ENET_GTX_CLK;
inout HPS_ENET_INT_N;
output HPS_ENET_MDC;
inout HPS_ENET_MDIO;
input HPS_ENET_RX_CLK;
input [ 3: 0] HPS_ENET_RX_DATA;
input HPS_ENET_RX_DV;
output [ 3: 0] HPS_ENET_TX_DATA;
output HPS_ENET_TX_EN;
// Flash
inout [ 3: 0] HPS_FLASH_DATA;
output HPS_FLASH_DCLK;
output HPS_FLASH_NCSO;
// Accelerometer
inout HPS_GSENSOR_INT;
// General Purpose I/O
inout [ 1: 0] HPS_GPIO;
// I2C
inout HPS_I2C_CONTROL;
inout HPS_I2C1_SCLK;
inout HPS_I2C1_SDAT;
inout HPS_I2C2_SCLK;
inout HPS_I2C2_SDAT;
// Pushbutton
inout HPS_KEY;
// LED
inout HPS_LED;
// SD Card
output HPS_SD_CLK;
inout HPS_SD_CMD;
inout [ 3: 0] HPS_SD_DATA;
// SPI
output HPS_SPIM_CLK;
input HPS_SPIM_MISO;
output HPS_SPIM_MOSI;
inout HPS_SPIM_SS;
// UART
input HPS_UART_RX;
output HPS_UART_TX;
// USB
inout HPS_CONV_USB_N;
input HPS_USB_CLKOUT;
inout [ 7: 0] HPS_USB_DATA;
input HPS_USB_DIR;
input HPS_USB_NXT;
output HPS_USB_STP;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire [31: 0] hex3_hex0;
wire [15: 0] hex5_hex4;
assign HEX0 = ~hex3_hex0[ 6: 0];
assign HEX1 = ~hex3_hex0[14: 8];
assign HEX2 = ~hex3_hex0[22:16];
assign HEX3 = ~hex3_hex0[30:24];
assign HEX4 = ~hex5_hex4[ 6: 0];
assign HEX5 = ~hex5_hex4[14: 8];
//=======================================================
// Structural coding
//=======================================================
Computer_System The_System (
////////////////////////////////////
// FPGA Side
////////////////////////////////////
// Global signals
.system_pll_ref_clk_clk (CLOCK_50),
.system_pll_ref_reset_reset (1'b0),
// AV Config
// .av_config_SCLK (FPGA_I2C_SCLK),
// .av_config_SDAT (FPGA_I2C_SDAT),
// Audio Subsystem
// .audio_pll_ref_clk_clk (CLOCK3_50),
// .audio_pll_ref_reset_reset (1'b0),
// .audio_clk_clk (AUD_XCK),
// .audio_ADCDAT (AUD_ADCDAT),
// .audio_ADCLRCK (AUD_ADCLRCK),
// .audio_BCLK (AUD_BCLK),
// .audio_DACDAT (AUD_DACDAT),
// .audio_DACLRCK (AUD_DACLRCK),
// Slider Switches
.slider_switches_export (SW),
// Pushbuttons
.pushbuttons_export (~KEY[3:0]),
// Expansion JP1
.expansion_jp1_export ({GPIO_0[35:19], GPIO_0[17], GPIO_0[15:3], GPIO_0[1]}),
// Expansion JP2
.expansion_jp2_export ({GPIO_1[35:19], GPIO_1[17], GPIO_1[15:3], GPIO_1[1]}),
// LEDs
.leds_export (LEDR),
// Seven Segs
// .hex3_hex0_export (hex3_hex0),
// .hex5_hex4_export (hex5_hex4),
// PS2 Ports
// .ps2_port_CLK (PS2_CLK),
// .ps2_port_DAT (PS2_DAT),
// .ps2_port_dual_CLK (PS2_CLK2),
// .ps2_port_dual_DAT (PS2_DAT2),
// IrDA
// .irda_RXD (IRDA_RXD),
// .irda_TXD (IRDA_TXD),
// VGA Subsystem
.vga_pll_ref_clk_clk (CLOCK2_50),
.vga_pll_ref_reset_reset (1'b0),
.vga_CLK (VGA_CLK),
.vga_BLANK (VGA_BLANK_N),
.vga_SYNC (VGA_SYNC_N),
.vga_HS (VGA_HS),
.vga_VS (VGA_VS),
.vga_R (VGA_R),
.vga_G (VGA_G),
.vga_B (VGA_B),
// Video In Subsystem
.video_in_TD_CLK27 (TD_CLK27),
.video_in_TD_DATA (TD_DATA),
.video_in_TD_HS (TD_HS),
.video_in_TD_VS (TD_VS),
.video_in_clk27_reset (),
.video_in_TD_RESET (TD_RESET_N),
.video_in_overflow_flag (),
// SDRAM
.sdram_clk_clk (DRAM_CLK),
.sdram_addr (DRAM_ADDR),
.sdram_ba (DRAM_BA),
.sdram_cas_n (DRAM_CAS_N),
.sdram_cke (DRAM_CKE),
.sdram_cs_n (DRAM_CS_N),
.sdram_dq (DRAM_DQ),
.sdram_dqm ({DRAM_UDQM,DRAM_LDQM}),
.sdram_ras_n (DRAM_RAS_N),
.sdram_we_n (DRAM_WE_N),
////////////////////////////////////
// HPS Side
////////////////////////////////////
// DDR3 SDRAM
.memory_mem_a (HPS_DDR3_ADDR),
.memory_mem_ba (HPS_DDR3_BA),
.memory_mem_ck (HPS_DDR3_CK_P),
.memory_mem_ck_n (HPS_DDR3_CK_N),
.memory_mem_cke (HPS_DDR3_CKE),
.memory_mem_cs_n (HPS_DDR3_CS_N),
.memory_mem_ras_n (HPS_DDR3_RAS_N),
.memory_mem_cas_n (HPS_DDR3_CAS_N),
.memory_mem_we_n (HPS_DDR3_WE_N),
.memory_mem_reset_n (HPS_DDR3_RESET_N),
.memory_mem_dq (HPS_DDR3_DQ),
.memory_mem_dqs (HPS_DDR3_DQS_P),
.memory_mem_dqs_n (HPS_DDR3_DQS_N),
.memory_mem_odt (HPS_DDR3_ODT),
.memory_mem_dm (HPS_DDR3_DM),
.memory_oct_rzqin (HPS_DDR3_RZQ),
// Ethernet
.hps_io_hps_io_gpio_inst_GPIO35 (HPS_ENET_INT_N),
.hps_io_hps_io_emac1_inst_TX_CLK (HPS_ENET_GTX_CLK),
.hps_io_hps_io_emac1_inst_TXD0 (HPS_ENET_TX_DATA[0]),
.hps_io_hps_io_emac1_inst_TXD1 (HPS_ENET_TX_DATA[1]),
.hps_io_hps_io_emac1_inst_TXD2 (HPS_ENET_TX_DATA[2]),
.hps_io_hps_io_emac1_inst_TXD3 (HPS_ENET_TX_DATA[3]),
.hps_io_hps_io_emac1_inst_RXD0 (HPS_ENET_RX_DATA[0]),
.hps_io_hps_io_emac1_inst_MDIO (HPS_ENET_MDIO),
.hps_io_hps_io_emac1_inst_MDC (HPS_ENET_MDC),
.hps_io_hps_io_emac1_inst_RX_CTL (HPS_ENET_RX_DV),
.hps_io_hps_io_emac1_inst_TX_CTL (HPS_ENET_TX_EN),
.hps_io_hps_io_emac1_inst_RX_CLK (HPS_ENET_RX_CLK),
.hps_io_hps_io_emac1_inst_RXD1 (HPS_ENET_RX_DATA[1]),
.hps_io_hps_io_emac1_inst_RXD2 (HPS_ENET_RX_DATA[2]),
.hps_io_hps_io_emac1_inst_RXD3 (HPS_ENET_RX_DATA[3]),
// Flash
.hps_io_hps_io_qspi_inst_IO0 (HPS_FLASH_DATA[0]),
.hps_io_hps_io_qspi_inst_IO1 (HPS_FLASH_DATA[1]),
.hps_io_hps_io_qspi_inst_IO2 (HPS_FLASH_DATA[2]),
.hps_io_hps_io_qspi_inst_IO3 (HPS_FLASH_DATA[3]),
.hps_io_hps_io_qspi_inst_SS0 (HPS_FLASH_NCSO),
.hps_io_hps_io_qspi_inst_CLK (HPS_FLASH_DCLK),
// Accelerometer
.hps_io_hps_io_gpio_inst_GPIO61 (HPS_GSENSOR_INT),
// .adc_sclk (ADC_SCLK),
// .adc_cs_n (ADC_CS_N),
// .adc_dout (ADC_DOUT),
// .adc_din (ADC_DIN),
// General Purpose I/O
.hps_io_hps_io_gpio_inst_GPIO40 (HPS_GPIO[0]),
.hps_io_hps_io_gpio_inst_GPIO41 (HPS_GPIO[1]),
// I2C
.hps_io_hps_io_gpio_inst_GPIO48 (HPS_I2C_CONTROL),
.hps_io_hps_io_i2c0_inst_SDA (HPS_I2C1_SDAT),
.hps_io_hps_io_i2c0_inst_SCL (HPS_I2C1_SCLK),
.hps_io_hps_io_i2c1_inst_SDA (HPS_I2C2_SDAT),
.hps_io_hps_io_i2c1_inst_SCL (HPS_I2C2_SCLK),
// Pushbutton
.hps_io_hps_io_gpio_inst_GPIO54 (HPS_KEY),
// LED
.hps_io_hps_io_gpio_inst_GPIO53 (HPS_LED),
// SD Card
.hps_io_hps_io_sdio_inst_CMD (HPS_SD_CMD),
.hps_io_hps_io_sdio_inst_D0 (HPS_SD_DATA[0]),
.hps_io_hps_io_sdio_inst_D1 (HPS_SD_DATA[1]),
.hps_io_hps_io_sdio_inst_CLK (HPS_SD_CLK),
.hps_io_hps_io_sdio_inst_D2 (HPS_SD_DATA[2]),
.hps_io_hps_io_sdio_inst_D3 (HPS_SD_DATA[3]),
// SPI
.hps_io_hps_io_spim1_inst_CLK (HPS_SPIM_CLK),
.hps_io_hps_io_spim1_inst_MOSI (HPS_SPIM_MOSI),
.hps_io_hps_io_spim1_inst_MISO (HPS_SPIM_MISO),
.hps_io_hps_io_spim1_inst_SS0 (HPS_SPIM_SS),
// UART
.hps_io_hps_io_uart0_inst_RX (HPS_UART_RX),
.hps_io_hps_io_uart0_inst_TX (HPS_UART_TX),
// USB
.hps_io_hps_io_gpio_inst_GPIO09 (HPS_CONV_USB_N),
.hps_io_hps_io_usb1_inst_D0 (HPS_USB_DATA[0]),
.hps_io_hps_io_usb1_inst_D1 (HPS_USB_DATA[1]),
.hps_io_hps_io_usb1_inst_D2 (HPS_USB_DATA[2]),
.hps_io_hps_io_usb1_inst_D3 (HPS_USB_DATA[3]),
.hps_io_hps_io_usb1_inst_D4 (HPS_USB_DATA[4]),
.hps_io_hps_io_usb1_inst_D5 (HPS_USB_DATA[5]),
.hps_io_hps_io_usb1_inst_D6 (HPS_USB_DATA[6]),
.hps_io_hps_io_usb1_inst_D7 (HPS_USB_DATA[7]),
.hps_io_hps_io_usb1_inst_CLK (HPS_USB_CLKOUT),
.hps_io_hps_io_usb1_inst_STP (HPS_USB_STP),
.hps_io_hps_io_usb1_inst_DIR (HPS_USB_DIR),
.hps_io_hps_io_usb1_inst_NXT (HPS_USB_NXT)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_mclk_txrx.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_mclk_txrx(/*AUTOARG*/
// Outputs
out,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, cbu, cbd, data, oe, odt_enable
);
// INPUTS
input [7:0] vrefcode; // impedence control bits
input odt_enable; // ODT control
input vdd_h; // IO power
input [8:1] cbu; // Impedence Control bits for Pullup driver
input [8:1] cbd; // Impedence Control bits for Pulldn driver
input data; // Data input to Driver
input oe; // Output tristate control (active high)
// INOUTS
inout pad; // Output/Input pad of Driver/Receiver
// OUTPUTS
output out; // Receiver output
//////////////////////////
// CODE
//////////////////////////
assign pad = oe ? data : 1'bz;
assign out = pad;
// FIX FOR MAKING INPUT DQS WEAK 0/1 WHEN BUS IS IN "Z" STATE.
//wire pad_in;
//pulldown p1(pad_in); // pulldown by default if no driver
//assign out = (pad === 1'bz) ? pad_in : pad;
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD3_SYMBOL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD3_SYMBOL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd3 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD3_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:04:51 05/16/2016
// Design Name:
// Module Name: Controlador_reloj_digital
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Controlador_reloj_digital(
input clk,reset,
output reg_a_d,reg_cs,reg_rd,reg_wr,
output [7:0]port_id,out_port,fin_lectura_escritura,
inout [7:0]dato
);
// CABLES DECONEXION DEL PICOBLAZE
wire [11:0]address;
wire [17:0]instruction;
wire bram_enable;
reg [7:0]in_port;
//wire [7:0]out_port;
//wire [7:0]port_id;
wire write_strobe;
wire k_write_strobe;
wire read_strobe;
wire interrupt;
wire interrupt_ack;
wire sleep;
wire rst;
wire flag_done;
reg [7:0]fin_lectura_escritura;
wire [7:0]out_dato;
reg state_reg_flag,state_next_flag;
assign interrupt = 0;
assign interrupt_ack = 0;
assign sleep = 0;
/// INTANCIACION DE MICROCONTROLADOR PICOBLAZE
kcpsm6 microntroller_picoblaze (
.address(address),
.instruction(instruction),
.bram_enable(bram_enable),
.in_port(in_port),
.out_port(out_port),
.port_id(port_id),
.write_strobe(write_strobe),
.k_write_strobe(k_write_strobe),
.read_strobe(read_strobe),
.interrupt(interrupt),
.interrupt_ack(interrupt_ack),
.sleep(sleep),
.reset(rst),
.clk(clk)
);
/// MEMORIA DE INSTRUCCIONES ROM
ROM_programa ROM_0 (
.address(address),
.instruction(instruction),
.enable(bram_enable),
.rdl(rst),
.clk(clk)
);
escritor_lector_rtc instance_escritor_lector_rtc (
.clk(clk),
.reset(reset),
.port_id(port_id),
.in_dato(out_port),
.write_strobe(write_strobe),
.read_strobe(read_strobe),
.reg_a_d(reg_a_d),
.reg_cs(reg_cs),
.reg_rd(reg_rd),
.reg_wr(reg_wr),
.out_dato(out_dato),
.fin_lectura_escritura(flag_done),
.dato(dato)
);
always @ (posedge clk)
begin
case (port_id)
8'h0F : in_port <= fin_lectura_escritura;
8'h10 : in_port <= out_dato;
default : in_port <= 8'bXXXXXXXX ;
endcase
end
/// maquina de estados para manipular fin lectura escritura
always @ (negedge clk,posedge reset) begin
if (reset) state_reg_flag = 1'b0;
else state_reg_flag = state_next_flag;
end
always@ (*) begin
state_next_flag = state_reg_flag;
case (state_reg_flag)
1'b0: begin
fin_lectura_escritura = 8'h00;
if (flag_done == 1) state_next_flag = 1'b1;
else state_next_flag = 1'b0;
end
1'b1: begin
fin_lectura_escritura = 8'h01;
if(port_id == 8'h0F && read_strobe == 1) state_next_flag = 1'b0;
else state_next_flag = 1'b1;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFSBP_TB_V
`define SKY130_FD_SC_HS__DFSBP_TB_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfsbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 SET_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 SET_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 SET_B = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 SET_B = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__dfsbp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFSBP_TB_V
|
(****************************************************************************)
(* Copyright 2021 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Coq.Strings.String.
Require Import Coq.Arith.PeanoNat.
Require Import Coq.micromega.Lia.
Require Import Coq.NArith.NArith.
Require Import Coq.ZArith.ZArith.
Require Import Coq.Init.Byte.
Require Import Coq.Lists.List.
Require Import coqutil.Tactics.Tactics.
Require Import Cava.Util.BitArithmetic.
Require Import Cava.Util.BitArithmeticProperties.
Require Import Cava.Util.Byte.
Require Import Cava.Util.If.
Require Import Cava.Util.List.
Require Import Cava.Util.Nat.
Require Import Cava.Util.Tactics.
Require Import Cava.Types.
Require Import Cava.Expr.
Require Import Cava.ExprProperties.
Require Import Cava.Invariant.
Require Import Cava.Primitives.
Require Import Cava.Semantics.
Require Import HmacSpec.SHA256Properties.
Require Import HmacHardware.Sha256.
Require Import HmacHardware.Sha256InnerProperties.
Require Import HmacHardware.Sha256PadderProperties.
Require HmacSpec.SHA256.
Import ListNotations.
Require Import coqutil.Tactics.autoforward.
Ltac autoforward_in db H ::=
let tmp := fresh H in
rename H into tmp;
let A := type of tmp in
pose proof ((ltac:(typeclasses eauto with db) : autoforward A _) tmp) as H;
(* Recently, this `move` was added in coqutil, which breaks this proof script,
because through destruct_one_match_hyp, it depends on the hypotheses order,
and the most straightforward way to fix the broken proofs requires too
much memory to work on CI *)
(* move H after tmp; *)
clear tmp.
(* Higher-level representation for sha256:
msg : message so far
msg_complete : whether the message is complete
byte_index : index indicating the last byte the padder has gotten to
t : compression round index
cleared : whether the circuit is cleared
*)
Instance sha256_invariant
: invariant_for sha256 (list byte * bool * nat * nat * nat * bool) :=
fun (state : denote_type ((Bit ** sha_block ** sha_digest ** BitVec 6 ** Bit)
** state_of sha256_padder
** state_of sha256_inner))
repr =>
let '((ready, (block, (digest, (count, done)))),
(sha256_padder_state, sha256_inner_state)) := state in
let '(msg, msg_complete, padder_byte_index, inner_byte_index, t, cleared) := repr in
(* block index is byte_index / 64 (64 bytes per block) *)
let padder_block_index := padder_byte_index / 64 in
let inner_block_index := inner_byte_index / 64 - 1 in
(* compute representation for padder state *)
let padder_repr :=
if cleared
then (reset_repr (c:=sha256_padder))
else (msg, msg_complete,
padder_byte_index =? padded_message_size msg, padder_byte_index) in
(* compute representation for inner *)
let inner_repr :=
if cleared
then (reset_repr (c:=sha256_inner))
else
(firstn (inner_byte_index / 64 * 16) (SHA256.padded_msg msg)
, inner_block_index
, t
, if t =? 64 then true else inner_byte_index =? 0
, inner_byte_index =? 0) in
(* index of the block that's currently in progress (i.e. next block whose
digest will be produced) *)
let completed_block_index :=
if (count <=? 15)%N
then
(* padder is running; same block index the padder is on *)
padder_block_index
else if (count =? 16)%N
then
(* padder is done, so padder_block_index has just moved to the
next block; subtract 1 to get the current index *)
padder_block_index - 1
else
if t =? 64
then
(* inner circuit is done; next block to be produced will be
whatever block index the padder is on *)
padder_block_index
else
(* inner circuit is in progress; next block to be produced will
be whatever block index the inner circuit is on *)
inner_block_index in
(* the invariant for sha256_padder is satisfied *)
sha256_padder_invariant sha256_padder_state padder_repr
(* ...and the invariant for sha256_inner is satisfied *)
/\ sha256_inner_invariant sha256_inner_state inner_repr
(* ...and the length of [block] is always 16 *)
/\ length block = 16
(* ...and count is always in the range [0,17] *)
/\ (count <= 17)%N
(* ...and byte indices are always at a word boundary *)
/\ padder_byte_index mod 4 = 0
/\ (if cleared
then
(* if the circuit is cleared, it must be in the reset state
(including subcircuits) *)
padder_byte_index = 0
/\ inner_byte_index = 0
/\ t = 0
/\ msg = []
/\ msg_complete = false
/\ count = 0%N
/\ done = true
/\ digest = SHA256.H0
else
(* the byte index (padder counter) is within the range
[4,padded_message_size msg] *)
4 <= padder_byte_index <= padded_message_size msg
(* ...and t (inner loop counter) is in the range [0,64] *)
/\ t <= 64
(* ...and ready is true iff count < 16 *)
/\ ready = (count <? 16)%N
(* ...and the digest must be the expected digest (digest is only
stored at the end of each inner loop) *)
/\ digest = fold_left (SHA256.sha256_step msg)
(seq 0 completed_block_index) SHA256.H0
(* ...and the index is past the end of the message iff the message is
complete *)
/\ (if msg_complete then length msg <= padder_byte_index else padder_byte_index = length msg)
(* ...and if [done] is true, we must be at the end of the message *)
/\ (if done
then padder_byte_index = inner_byte_index
/\ padder_byte_index = padded_message_size msg
/\ count = 0%N
/\ t = 64
else True)
(* ...and the state variables agree with [count] *)
/\ (if (count <=? 15)%N
then
(* padder is running *)
skipn (16 - N.to_nat count) block
= List.slice 0%N (SHA256.padded_msg msg) (padder_block_index * 16) (N.to_nat count)
/\ padder_byte_index mod 64 = N.to_nat count * 4 (* byte_index is on the [count]th word *)
/\ (if (padder_byte_index <? 64) then t = 0 else t = 64) (* inner is between blocks *)
/\ inner_byte_index = padder_block_index * 64
else
(* inner loop is running or about to run *)
padder_byte_index mod 64 = 0 (* byte index is at the end of a block *)
/\ (if (count =? 16)%N
then
(* padder has just finished a block; send the completed
block to start inner loop *)
block = List.slice 0%N (SHA256.padded_msg msg)
(inner_byte_index / 64 * 16) 16
/\ (if (padder_byte_index =? 64) then t = 0 else t = 64)
/\ padder_byte_index = inner_byte_index + 64
else
(* inner loop is in progress *)
0 <= t < 64
/\ inner_byte_index = padder_byte_index))
).
Instance sha256_specification
: specification_for sha256 (list byte * bool * nat * nat * nat * bool) :=
{| reset_repr := ([], false, 0, 0, 0, true);
update_repr :=
fun (input : denote_type [Bit; sha_word; Bit; BitVec 4; Bit])
repr =>
let '(fifo_data_valid,
(fifo_data, (is_final, (final_length, (clear, _))))) := input in
let '(msg, msg_complete, padder_byte_index, inner_byte_index, t, cleared) := repr in
let new_bytes :=
new_msg_bytes fifo_data_valid fifo_data is_final final_length in
if clear
then ([], false, 0, 0, 0, true)
else if cleared
then if fifo_data_valid
then (new_bytes, is_final, 4, 0, 0, false)
else ([], false, 0, 0, 0, true) (* stay in cleared state *)
else if (padder_byte_index =? inner_byte_index)
then if t =? 64
then
(* sha256_inner has finished; start the padder on the
next block if we can *)
if (padder_byte_index =? padded_message_size msg)
then
(* padder is at the end of the message and
processing is completely done; hold state
constant *)
repr
else
if msg_complete
then
(* step padder *)
(msg, msg_complete, padder_byte_index + 4, inner_byte_index, t, cleared)
else if fifo_data_valid
then
(* step padder *)
(msg ++ new_bytes, is_final, padder_byte_index + 4, inner_byte_index, t, cleared)
else
(* message is incomplete and next word isn't
available; wait *)
repr
else
(* sha256_inner is already in progress; increment t *)
(msg, msg_complete, padder_byte_index, inner_byte_index, S t, cleared)
else
if (padder_byte_index =? inner_byte_index + 64)
then
(* padder just finished a block; start sha256_inner by
passing in the new block and reset t to 0 *)
(msg, msg_complete, padder_byte_index, padder_byte_index, 0, cleared)
else
(* padder is midway through a block; take another step if possible *)
if msg_complete
then
(* step padder *)
(msg, msg_complete, padder_byte_index + 4, inner_byte_index, t, cleared)
else if fifo_data_valid
then
(* step padder *)
(msg ++ new_bytes, is_final, padder_byte_index + 4, inner_byte_index, t, cleared)
else
(* message is incomplete and next word isn't
available; wait *)
(msg, msg_complete, padder_byte_index, inner_byte_index, t, cleared);
precondition :=
fun (input : denote_type [Bit; sha_word; Bit; BitVec 4; Bit])
repr =>
let '(fifo_data_valid,
(fifo_data, (is_final, (final_length, (clear, _))))) := input in
let '(msg, msg_complete, padder_byte_index, inner_byte_index, t, cleared) := repr in
let new_bytes :=
new_msg_bytes fifo_data_valid fifo_data is_final final_length in
(* the total message length (including any new data) cannot exceed 2 ^
64 bits (2^61 bytes) -- using N so Coq doesn't try to compute 2 ^ 61
in nat *)
(N.of_nat (length (msg ++ new_bytes)) < 2 ^ 61)%N
(* ...and if data is valid, it must be in expected range *)
/\ (if fifo_data_valid
then if is_final
then (fifo_data < 2 ^ (8 * final_length))%N
/\ (1 <= final_length <= 4)%N
else (fifo_data < 2 ^ 32)%N
else True)
(* ...and if msg_complete is true, then new valid data cannot be passed
(must clear first) *)
/\ (if msg_complete then fifo_data_valid = false else True);
postcondition :=
fun (input : denote_type [Bit; sha_word; Bit; BitVec 4; Bit])
repr (output : denote_type (Bit ** sha_digest ** Bit)) =>
let '(fifo_data_valid,
(fifo_data, (is_final, (final_length, (clear, _))))) := input in
let '(msg, msg_complete, padder_byte_index, inner_byte_index, t, cleared) := repr in
(* new value of [cleared] *)
let is_cleared := if clear
then true
else if cleared
then negb (fifo_data_valid)
else false in
let count_16_pre :=
if (if (padder_byte_index =? 64) then t =? 0 else t =? 64)
then if (padder_byte_index =? inner_byte_index + 64) then true else false else false
in
let count_le15_pre :=
if (padder_byte_index <? 64) then t =? 0 else t =? 64
in
let is_cleared_or_done :=
if is_cleared
then true
else if fifo_data_valid
then false
else
if count_16_pre
then false
else
if (padder_byte_index =? padded_message_size msg) then if (t =? 64) then true else false else false
in
(* new value of [padder_byte_index] *)
let new_padder_byte_index :=
if clear
then 0
else if cleared
then 0
else if (padder_byte_index =? inner_byte_index)
then if t =? 64
then if (padder_byte_index =? padded_message_size msg)
then padder_byte_index
else if msg_complete
then padder_byte_index + 4
else if fifo_data_valid
then padder_byte_index + 4
else padder_byte_index
else padder_byte_index
else if (padder_byte_index =? inner_byte_index + 64)
then padder_byte_index
else if msg_complete
then padder_byte_index + 4
else if fifo_data_valid
then padder_byte_index + 4
else padder_byte_index in
(* new value of [t] *)
let new_t :=
if clear
then 0
else if cleared
then 0
else if (padder_byte_index =? inner_byte_index)
then if t =? 64
then t
else S t
else if (padder_byte_index =? inner_byte_index + 64)
then 0
else t in
(* ready for new input only if the inner loop is done and the padder is
not *)
let is_ready :=
if is_cleared
then true
else
if count_16_pre then false
else if count_le15_pre then
if (if padder_byte_index =? padded_message_size msg
then fifo_data_valid
else if msg_complete then true else fifo_data_valid)
then padder_byte_index mod 64 <=? 56
else true
else if inner_byte_index =? padder_byte_index
then
if if (t =? 64)%nat then true else (inner_byte_index =? 0)%nat
then true
else (t =? 63)%nat
else true
in
exists done digest ready,
output = (done, (digest, ready))
/\ done = is_cleared_or_done
/\ ready = is_ready
/\ if is_cleared
then digest = SHA256.H0
else if is_cleared_or_done
then digest = BigEndianBytes.bytes_to_Ns
4 (SHA256.sha256 msg)
else True (* no guarantees about intermediate output *)
|}.
Local Hint Unfold
sha256_state
sha256_outer_state
padder_state
sha256_inner_state
: stepsimpl.
Lemma sha256_invariant_at_reset : invariant_at_reset sha256.
Proof.
simplify_invariant sha256.
cbn [reset_repr reset_state sha256 sha256_specification
sha256_padder_specification
sha256_inner_specification].
stepsimpl. cbn [Nat.eqb]. compute_expr (0 mod 64).
ssplit;
lazymatch goal with
| |- sha256_padder_invariant _ _ => apply sha256_padder_invariant_at_reset
| |- sha256_inner_invariant _ _ => apply sha256_inner_invariant_at_reset
| _ => reflexivity || lia
end.
Qed.
Lemma test_nth_byte_of_x x i :
(x < 2 ^ 32)%N ->
N.testbit
(Byte.to_N
(nth (N.to_nat (i / 8))
[N_to_byte (N.shiftr x (N.of_nat (4 - 1 - 3) * 8));
N_to_byte (N.shiftr x (N.of_nat (4 - 1 - 2) * 8));
N_to_byte (N.shiftr x (N.of_nat (4 - 1 - 1) * 8));
N_to_byte (N.shiftr x (N.of_nat (4 - 1 - 0) * 8))] "000"%byte))
(i mod 8) = N.testbit x i.
Proof.
intros.
remember (N.to_nat (i/8)) as m.
destr (m <? 4).
{
repeat (destruct m as [|m]; try prove_by_zify);
cbn [List.app nth Nat.mul Nat.add];
rewrite N2Byte.id;
replace 256%N with (2^8)%N by now cbn.
{ assert(i < 8)%N by prove_by_zify.
rewrite N.mod_small with (b:=8%N) by lia.
testbit_crush.
}
{ assert(i - 8 < 8)%N by prove_by_zify.
replace (i mod 8)%N with ((i - 8) mod 8)%N by prove_by_zify.
rewrite N.mod_small with (b:=8%N) by lia.
cbn [Nat.sub].
testbit_crush.
now replace ((i - 8 + N.of_nat 1 * 8))%N with i by prove_by_zify.
}
{ assert(i - 16 < 8)%N by prove_by_zify.
replace (i mod 8)%N with ((i - 16) mod 8)%N by prove_by_zify.
rewrite N.mod_small with (b:=8%N) by lia.
cbn [Nat.sub].
testbit_crush.
now replace ((i - 16 + N.of_nat 2 * 8))%N with i by prove_by_zify.
}
{ assert(i - 24 < 8)%N by prove_by_zify.
replace (i mod 8)%N with ((i - 24) mod 8)%N by prove_by_zify.
rewrite N.mod_small with (b:=8%N) by lia.
cbn [Nat.sub].
testbit_crush.
now replace ((i - 24 + N.of_nat 3 * 8))%N with i by prove_by_zify.
}
}
assert (32 <= i)%N by prove_by_zify.
rewrite nth_overflow by now push_length.
destr (x=?0)%N;subst;push_Ntestbit;[reflexivity|].
apply N.log2_lt_pow2 in H.
{ rewrite N.bits_above_log2; lia. }
lia.
Qed.
Lemma concat_digest_to_N_id xs:
Forall (fun x => x < 2 ^ 32)%N xs ->
length xs = 8 ->
BigEndianBytes.bytes_to_Ns 4 (SHA256.concat_digest xs) = xs.
Proof.
intros.
cbv [SHA256.concat_digest SHA256.w].
cbv [seq SHA256.w].
replace (N.to_nat 32 / 8) with 4 by prove_by_zify.
repeat (destruct xs as [ | ?x xs];[now cbn in *| cbn in H0;
let h := fresh in pose proof (Forall_inv H) as h;
cbn beta in h;
let h' := fresh in
pose proof (Forall_inv_tail H) as h';
clear H; rename h' into H;
try lia]).
clear H.
destruct xs;[|cbn in H0; lia].
apply nth_ext with (d:=0%N) (d':=0%N).
{ now cbn. }
intros.
cbv [SHA256.concat_digest].
rewrite nth_bytes_to_Ns; cycle 1.
{ now cbn. }
{ lia. }
revert H.
rewrite flat_map_concat_map.
cbv [seq].
cbn [List.map seq nth Nat.mul Nat.add concat List.app].
cbv [BigEndianBytes.N_to_bytes seq BigEndianBytes.bytes_to_Ns ].
push_length; intros.
cbv [List.map].
repeat (destruct n; [
cbn [List.app nth Nat.mul Nat.add];
apply N.bits_inj; intro i;
rewrite concat_bytes_spec;
apply test_nth_byte_of_x; trivial
|]).
exfalso; prove_by_zify.
Qed.
Require Import Coq.derive.Derive.
(* simplifies the sha256 circuit so we don't have to wait for the slow
simplifications in every proof *)
Derive step_sha256_simplified
SuchThat
(forall ready block digest count done sha256_padder_state sha256_inner_state
fifo_data_valid fifo_data is_final final_length clear,
let state := ((ready, (block, (digest, (count, done)))),
(sha256_padder_state, sha256_inner_state)) in
let input := (fifo_data_valid,
(fifo_data, (is_final, (final_length, (clear, tt))))) in
step sha256 state input =
step_sha256_simplified ready block digest count done sha256_padder_state sha256_inner_state
fifo_data_valid fifo_data is_final final_length clear)
As step_sha256_simplified_eq.
Proof.
cbv [sha256]; intros; stepsimpl.
repeat (destruct_inner_pair_let; cbn [fst snd]).
rewrite <-!tup_if. cbn [fst snd].
subst step_sha256_simplified. instantiate_app_by_reflexivity.
Qed.
Lemma sha256_invariant_preserved : invariant_preserved sha256.
Proof.
simplify_invariant sha256. cbn [absorb_any].
simplify_spec sha256.
(* The following gymnastics results in input_, state_, and repr_ being posed
as let-hypotheses, which makes proof debugging easier because one can look
at them and see what case the proof is dealing with *)
intros input state repr.
pose (input_:=input). pose (state_:=state). pose (repr_:=repr).
revert dependent repr. revert dependent state. revert dependent input.
intros (fifo_data_valid,
(fifo_data, (is_final, (final_length, (clear, []))))).
intro.
intros ((ready, (block, (digest, (count, done)))),
(sha256_padder_state, sha256_inner_state)).
intro.
intros (((((msg, msg_complete), padder_byte_index), inner_byte_index), t), cleared).
intros; logical_simplify; subst.
rewrite step_sha256_simplified_eq. cbv [step_sha256_simplified]. cbn [fst snd].
rewrite <-!tup_if. cbn [fst snd].
(* A whole bunch of assertions about the properties of padded_message_size
related to all 3 possible next messages *)
pose proof padded_message_size_mono
msg (new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof padded_message_bytes_longer_than_input msg.
pose proof padded_message_bytes_longer_than_input
(new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof padded_message_bytes_longer_than_input
(msg ++ new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof min_padded_message_size msg.
pose proof min_padded_message_size
(new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof min_padded_message_size
(msg ++ new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof padded_message_size_modulo msg.
pose proof padded_message_size_modulo
(new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof padded_message_size_modulo
(msg ++ new_msg_bytes fifo_data_valid fifo_data is_final final_length).
(* prove that padder precondition is satisfied *)
lazymatch goal with
| H : sha256_padder_invariant ?state ?repr
|- context [step sha256_padder ?state ?input] =>
assert (precondition sha256_padder input repr)
end.
{ simplify_spec sha256_padder. cbn [reset_repr sha256_padder_specification].
destr cleared; logical_simplify; subst;
[ destr fifo_data_valid; destr is_final; logical_simplify; subst;
ssplit; solve [auto] | ].
ssplit; [ assumption | ].
destr fifo_data_valid; logical_simplify; subst; [ | tauto ].
destr is_final; logical_simplify; subst; split; try tauto.
{ destruct msg_complete; try lia. }
{ destruct msg_complete; try lia. }
}
use_correctness' sha256_padder.
cbn [reset_repr sha256_padder_specification] in *.
(* prove that inner precondition is satisfied *)
lazymatch goal with
| H : sha256_inner_invariant ?state ?repr
|- context [step sha256_inner ?state ?input] =>
assert (precondition sha256_inner input repr)
end.
{ simplify_spec sha256_inner. cbn [reset_repr sha256_inner_specification].
destr cleared; logical_simplify; subst;
[ destr fifo_data_valid; destr is_final; logical_simplify; subst;
ssplit; solve [auto] | ].
rewrite fold_left_sha256_step_alt_firstn.
all:destr (t =? 64); logical_simplify; subst; try lia.
all:destr (count <=? 15)%N; logical_simplify; subst.
all:destr (count =? 16)%N; logical_simplify; subst; try lia.
all:repeat (destruct_one_match; logical_simplify; subst; try lia).
all:repeat lazymatch goal with
| H : (Nat.eqb ?x ?y) = false |- _ => apply Nat.eqb_neq in H
end.
all:try (destr (padder_byte_index <? 64); logical_simplify; subst; [ | lia ]).
all:rewrite ?Nat.div_mul, ?Nat.div_small in * by lia.
all:try reflexivity.
all:try discriminate.
all:natsimpl.
all:repeat lazymatch goal with
| |- context [(?x + ?y) / ?y] => replace ((x + y) / y) with (x / y + 1) by prove_by_zify
| |- context [S (?x - 1)] => replace (S (x - 1)) with x by prove_by_zify
end.
all:natsimpl.
all:try (destr (inner_byte_index + 64 =? 64); logical_simplify; subst; lia).
all:lazymatch goal with
| |- _ /\ _ /\ _ => ssplit; [ reflexivity | | length_hammer ]
| _ => idtac
end.
all:rewrite ?firstn_slice_app by (push_length; prove_by_zify).
all:lazymatch goal with
| |- fold_left _ _ _ = fold_left _ _ _ =>
eapply fold_left_ext_In; intros *;
rewrite in_seq; intros;
rewrite !sha256_step_alt_firstn by lia;
try reflexivity
end. }
use_correctness' sha256_inner.
cbn [reset_repr sha256_inner_specification] in *.
ssplit.
{ (* prove that padder invariant is preserved *)
eapply invariant_preserved_pf; [ | eassumption .. ].
(* prove that padder state rep is updated correctly *)
cbn [reset_repr update_repr sha256_padder_specification] in *.
destr clear; [ destruct cleared; reflexivity | ].
destr cleared; logical_simplify; subst.
{ (* cleared=true *)
destr fifo_data_valid; logical_simplify; subst;
[ | destruct_one_match; reflexivity ].
repeat (destruct_one_match; try lia); try reflexivity; [ ].
lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
end.
reflexivity. }
{ (* cleared=false *)
destr fifo_data_valid; logical_simplify; subst;
cbn [Nat.eqb].
{ (* data_valid=true *)
rewrite ?Tauto.if_same.
destr (length msg =? padded_message_size msg); [ lia | ].
destr (count <=? 15)%N; logical_simplify; subst;
[ destr (count =? 0)%N; logical_simplify; subst
| destr (count =? 16)%N; logical_simplify; subst ].
all:try lia.
all:cbn [N.eqb Pos.eqb Nat.eqb] in *.
all:repeat destruct_one_match; try lia.
all:repeat lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
end.
all:try reflexivity.
all:try prove_by_zify.
{ destruct msg_complete; try lia. }
{ destruct msg_complete; try lia. }
{ destruct_one_match_hyp; logical_simplify; subst; try lia.
repeat (destruct_one_match_hyp; logical_simplify; subst; try lia).
}
}
{ (* data_valid = false *)
destr msg_complete; logical_simplify; subst;
rewrite ?Tauto.if_same; [ | repeat destruct_one_match; reflexivity ].
assert (padder_byte_index mod 64 = 0 ->
padder_byte_index + 4 <> padded_message_size msg) by prove_by_zify.
repeat (destruct_one_match; try lia); logical_simplify; subst.
all:rewrite ?Nat.eqb_refl; try reflexivity.
all:repeat lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
end.
all:destr (count =? 16)%N; subst; try lia.
all:try (exfalso; prove_by_zify).
all:destr (padder_byte_index <? 64); lia. } } }
Optimize Proof.
{ (* prove that inner invariant is preserved *)
eapply invariant_preserved_pf; [ | eassumption .. ].
(* prove that inner state rep is updated correctly *)
cbn [reset_repr update_repr sha256_inner_specification].
destr clear; [ destr cleared; reflexivity | ].
destr cleared; logical_simplify; subst;
[ cbn [N.leb N.compare] in *; logical_simplify; subst;
destr fifo_data_valid; logical_simplify; subst; reflexivity | ].
destr (padder_byte_index =? padded_message_size msg); logical_simplify; subst.
{ (* padder has reached end of message *)
(* only one possible case for data_valid and msg_complete;
data_valid=false and msg_complete=true *)
abstract(
destr fifo_data_valid; destr msg_complete;
logical_simplify; subst; try lia; [ ];
destr (count <=? 15)%N; logical_simplify; subst;
rewrite ?Tauto.if_same in *; cbn [fst snd] in *;
boolsimpl;
repeat (first [ destruct_one_match | destruct_one_match_hyp];
logical_simplify; subst; try lia; try reflexivity);
try (exfalso; prove_by_zify);
repeat lazymatch goal with
| H : (Nat.eqb ?x ?y) = true |- _ => apply Nat.eqb_eq in H; subst; try lia
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
| |- context [Nat.ltb ?x ?y] => destr (Nat.ltb x y); try lia
end;
try reflexivity;
rewrite firstn_slice_app by (push_length; prove_by_zify);
(* structure already matches; use prove_by_zify for nat arguments *)
repeat (f_equal; lazymatch goal with
| |- @eq nat _ _ => prove_by_zify
| _ => idtac
end)).
}
{ (* padder is not yet at end of message *)
rewrite Tauto.if_same.
destr (padder_byte_index =? inner_byte_index); logical_simplify; subst.
{ (* inner is running or just finished running *)
all: repeat
(repeat lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
| |- context [Nat.ltb ?x ?y] => destr (Nat.ltb x y); try lia
end;
try reflexivity;
(destruct_one_match_hyp; logical_simplify; subst; try lia)).
all: now rewrite firstn_padded_msg_truncate by prove_by_zify.
}
{ (* padder is running or just finished running *)
destr (padder_byte_index =? inner_byte_index + 64); logical_simplify; subst.
{ (* padder just finished running (count=16) *)
destr (count <=? 15)%N; logical_simplify; subst;
[ exfalso; prove_by_zify | ].
destr (count =? 16)%N; [ | exfalso; prove_by_zify ].
all: repeat
(repeat lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
| |- context [Nat.ltb ?x ?y] => destr (Nat.ltb x y); try lia
end;
try reflexivity;
(destruct_one_match_hyp; logical_simplify; subst; try lia)).
all:repeat destruct_one_match; logical_simplify; subst; try lia.
all:rewrite ?firstn_slice_app by (push_length; prove_by_zify).
all:rewrite ?Nat.eqb_refl in *; try discriminate.
all:repeat (f_equal; lazymatch goal with
| |- @eq nat _ _ => prove_by_zify
| _ => idtac
end).
}
{ (* padder is still running (count <= 15) *)
destr (count <=? 15)%N; logical_simplify; subst;
[ | destr (count =? 16)%N; logical_simplify; subst;
exfalso; prove_by_zify ].
all: repeat
(repeat lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
| |- context [Nat.ltb ?x ?y] => destr (Nat.ltb x y); try lia
end;
try reflexivity;
(destruct_one_match_hyp; logical_simplify; subst; try lia)).
all:repeat destruct_one_match; logical_simplify; subst; try lia.
all:try reflexivity.
all:try prove_by_zify.
all:rewrite firstn_padded_msg_truncate by prove_by_zify.
all:reflexivity. } } } }
Optimize Proof.
{ (* length block = 16 *)
fold denote_type; change (denote_type sha_word) with N.
repeat destruct_one_match.
all:cbn [N.leb Pos.compare N.compare fst snd] in *.
all:logical_simplify; subst; boolsimpl.
all:repeat destruct_one_match; length_hammer. }
{ (* count <= 17 *)
repeat destruct_one_match.
all:cbn [N.leb Pos.compare N.compare fst snd] in *.
all:logical_simplify; subst; boolsimpl.
all:try lia.
all:boolsimpl_hyps; N.bool_to_prop.
all:compute_expr (2 ^ N.of_nat 6)%N.
all:rewrite ?N.mod_small by lia.
all:lia. }
{ (* padder_byte_index mod 4 = 0 *)
repeat destruct_one_match; try reflexivity.
all:try assumption.
all:prove_by_zify. }
{ (* big if cleared then ... else ... clause *)
compute_expr (2 ^ N.of_nat 6)%N.
destr clear; [ ssplit; reflexivity | ].
destr cleared; logical_simplify; subst.
{ (* cleared=true *)
cbn [N.leb Pos.compare N.compare fst snd] in *.
logical_simplify; subst.
(* if data isn't valid, we stay cleared *)
destr fifo_data_valid; logical_simplify; subst; boolsimpl;
[ | ssplit; reflexivity ].
natsimpl.
rewrite !Nat.mod_small, !N.mod_small by lia.
rewrite !Nat.div_small by lia.
ssplit; try lia.
all:repeat lazymatch goal with
| |- context [N.leb ?x ?y] => destr (N.leb x y); try lia
| |- context [N.ltb ?x ?y] => destr (N.ltb x y); try lia
end.
all:try reflexivity.
all:ssplit; try lia.
all:repeat destruct_one_match; logical_simplify; subst; try lia.
all:lazymatch goal with
| |- context [length (new_msg_bytes _ _ _ _)] => cbv [new_msg_bytes]; length_hammer
| _ => idtac
end.
(* should be only one case left, expression for block *)
compute_expr (N.to_nat (0 + 1)). natsimpl.
rewrite skipn_tl.
(* simplify implicit types *)
fold denote_type. change (denote_type sha_word) with N.
push_skipn; listsimpl.
rewrite slice_map_nth; cbn [List.map seq].
reflexivity. }
Optimize Proof.
{ (* cleared = false *)
rewrite ?Tauto.if_same.
(* destruct cases for [count] *)
destr (count <=? 15)%N;
[ destr (count =? 0)%N | destr (count =? 16)%N ];
logical_simplify; subst; cbn [fst snd] in *.
{ idtac "subgoal 1: count=0 (transition from inner to padder".
destr (padder_byte_index =? padder_byte_index / 64 * 64);
[ | exfalso; prove_by_zify ].
compute_expr ((0 + 1) mod 64)%N.
repeat (natsimpl || boolsimpl || cbn [Nat.eqb N.eqb Pos.eqb]).
ssplit.
{ (* padder_byte_index <= padded_message_size msg *)
repeat destruct_one_match; logical_simplify; subst; lia. }
{ (* padder_byte_index <= padded_message_size msg *)
repeat destruct_one_match; logical_simplify; subst; try lia;
prove_by_zify. }
{ (* t <= 64 *)
repeat destruct_one_match; logical_simplify; subst; lia. }
{ (* ready = (count <? 16)%N *)
repeat destruct_one_match; logical_simplify; subst;
repeat lazymatch goal with
| |- context [N.leb ?x ?y] => destr (N.leb x y); try lia
| |- context [N.ltb ?x ?y] => destr (N.ltb x y); try lia
end. }
{ (* digest = fold_left (SHA256.sha256_step msg)
(seq 0 completed_block_index) SHA256.H0 *)
all: repeat
(repeat lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
| |- context [Nat.ltb ?x ?y] => destr (Nat.ltb x y); try lia
end;
try reflexivity;
(destruct_one_match_hyp; logical_simplify; subst; try lia)).
all: boolsimpl.
all: repeat lazymatch goal with
| |- context [N.leb ?x ?y] => destr (N.leb x y); try lia
| |- context [N.ltb ?x ?y] => destr (N.ltb x y); try lia
end.
all:lazymatch goal with
| H : ?x = ?x / ?y * ?y |- context [(?x + ?z) / ?y] =>
rewrite H; rewrite (Nat.div_add_l (x / y) y) by lia;
rewrite ?Nat.div_small by lia; rewrite <-?H
end.
all:natsimpl; try reflexivity.
all:lazymatch goal with
| |- fold_left _ _ _ = fold_left _ _ _ =>
eapply fold_left_ext_In; intros *;
rewrite in_seq; intros
end.
all:rewrite sha256_step_truncate by prove_by_zify.
all:reflexivity. }
{ (* (if msg_complete
then length msg <= padder_byte_index
else padder_byte_index = length msg) *)
repeat (destruct_one_match; logical_simplify; subst; try lia);
cbv [new_msg_bytes]; length_hammer. }
{ (* (if done then ... else True) *)
repeat
(repeat lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
| |- context [Nat.ltb ?x ?y] => destr (Nat.ltb x y); try lia
end;
try reflexivity;
(destruct_one_match_hyp; logical_simplify; subst; try lia)).
all: boolsimpl; ssplit; try lia.
all: prove_by_zify.
}
{ (* clause that depends on count; in this case next count will always be <= 15 *)
repeat
(repeat lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
| |- context [Nat.ltb ?x ?y] => destr (Nat.ltb x y); try lia
| |- context [N.leb ?x ?y] => destr (N.leb x y); try lia
end;
try reflexivity;
(destruct_one_match_hyp; logical_simplify; subst; try lia)).
all: ssplit; try lia.
all: try abstract prove_by_zify.
all:
match goal with
| H: skipn ?X _ = _ |- skipn ?X _ = _ => rewrite H
| |- skipn ?X _ = _ => compute_expr X
end.
all: try reflexivity.
all:rewrite ?tl_app by (intro; subst; cbn [length] in *; discriminate).
all:fold denote_type.
all:compute_expr (N.to_nat 1).
all:change (denote_type sha_word) with N.
all:push_skipn; push_length.
all:push_skipn; listsimpl.
all:rewrite slice_map_nth; cbn [seq List.map].
all:repeat (f_equal; lazymatch goal with
| |- @eq nat _ _ => prove_by_zify
| _ => idtac
end). }
}
{ idtac "subgoal 2: 0 < count <= 15 (padder running)".
destr (17 =? count)%N; [lia|].
destr (16 =? count)%N; [lia|].
destr fifo_data_valid; destr msg_complete; logical_simplify; subst;
try discriminate; boolsimpl.
all:rewrite ?Tauto.if_same in *; cbn [Nat.eqb].
all: match goal with
| |- context [( ?X mod ?Y )%N] => rewrite (N.mod_small X Y) by lia
| |- _ => idtac
end.
(* { *)
all: repeat lazymatch goal with
| |- context [Nat.eqb ?x ?y] => destr (Nat.eqb x y); try lia
| |- context [Nat.ltb ?x ?y] => destr (Nat.ltb x y); try lia
| |- context [N.ltb ?x ?y] => destr (N.ltb x y); try lia
| |- context [N.leb ?x ?y] => destr (N.leb x y); try lia
end.
all: try (exfalso; prove_by_zify).
(* all: repeat (destruct_one_match; logical_simplify; subst; try lia). *)
all: autorewrite with Nnat.
all:try match goal with
| |- context [(?x + 4) / ?y] =>
replace ((x + 4)/y) with (x/y) by prove_by_zify
| |- context [(?x + 4)/ ?y - 1] =>
replace ((x + 4)/y - 1) with (x/y) by prove_by_zify
end.
all: natsimpl.
all: destr (Datatypes.length msg <? 64); try (exfalso; lia).
all: try (destr (padder_byte_index <? 64); try lia).
all: try (destruct done; try lia; try prove_by_zify).
all: repeat destruct_one_match.
all: ssplit;
first
[ reflexivity
| lia
| cbn [new_msg_bytes]; push_length; lia
| prove_by_zify
| idtac
].
all: cbn [sha_word].
all: lazymatch goal with
| H: skipn _ _ = _ |- context [skipn _ _ ] =>
rewrite ?skipn_tl; rewrite ?skipn_app;
replace (S (16 - (N.to_nat count + 1))) with (16 - N.to_nat count) by prove_by_zify;
rewrite H
| |- _ => idtac
end.
all: replace (16 - N.to_nat count - Datatypes.length block) with 0 by lia.
all: rewrite ?skipn_O.
all: replace (N.to_nat count + 1) with (S (N.to_nat count)) by lia.
all: subst.
all: repeat destruct_one_match.
all: try lazymatch goal with
| |- fold_left _ _ _ = fold_left _ _ _ =>
eapply fold_left_ext_In; intros *; rewrite in_seq; intros
end.
all: try (
rewrite <-slice_snoc; rewrite slicen_padded_msg_truncate by lia;
f_equal; f_equal;
rewrite ?nth_padded_msg;
cbv [SHA256.padded_msg_bytes];
rewrite <-!app_assoc; push_nth;
reflexivity
).
all: try (rewrite sha256_step_truncate; [reflexivity|prove_by_zify]).
all: try reflexivity.
all: try (
replace ((padder_byte_index + 4 - 4)/ 4)
with (padder_byte_index / 64 * 16 + N.to_nat count) by prove_by_zify).
all: try (
replace ((length msg + 4 - 4)/ 4)
with (length msg / 64 * 16 + N.to_nat count) by prove_by_zify).
all: try now rewrite slice_snoc.
all: try (
rewrite <- slice_snoc;
f_equal;
now rewrite slicen_padded_msg_truncate by prove_by_zify).
all:
assert (count = 15)%N by prove_by_zify;
replace (16 - N.to_nat count) with 1 in * by lia;
rewrite skipn_1 in H24;
rewrite tl_app by (destruct block; cbn [length] in H5; [lia|congruence]);
rewrite H24.
all:
try (
match goal with
| |- context[ new_msg_bytes _ _ ?T _ ] =>
rewrite <- slicen_padded_msg_truncate with (msg2:=
(new_msg_bytes true fifo_data T final_length)) by prove_by_zify
end).
all: try rewrite slice_snoc.
all:
f_equal; prove_by_zify;
reflexivity.
}
{ idtac "subgoal 3".
abstract (
destr fifo_data_valid; destr msg_complete; logical_simplify; subst;
try discriminate; boolsimpl;
rewrite ?Tauto.if_same in *; cbn [Nat.eqb];
repeat (destruct_one_match; logical_simplify; subst; try lia);
ssplit; try reflexivity; try lia; try prove_by_zify).
}
{ idtac "subgoal 4".
destr fifo_data_valid; destr msg_complete; logical_simplify; subst;
try discriminate; boolsimpl;
rewrite ?Tauto.if_same in *; cbn [Nat.eqb];
repeat (destruct_one_match; logical_simplify; subst; try lia);
destr(17 =? count)%N; try lia;
try destr (padder_byte_index =? 0); try lia;
try destr (t =? 63); try lia;
destr (count =? 0)%N; try lia;
ssplit; try reflexivity; try lia; try prove_by_zify;
try match goal with
| |- false = ?X => destr X; lia
end;
replace (16 - N.to_nat 0) with 16 by lia;
try rewrite Tauto.if_same in E4; try lia;
try (destr (length msg =? 0); lia);
try rewrite skipn_all2 by lia; try reflexivity.
all: destr (length msg =? 0); try lia.
all: rewrite H29.
all: rewrite fold_left_sha256_step_alt_firstn.
all: try replace ( S (padder_byte_index / 64 - 1) ) with (padder_byte_index / 64) in * by prove_by_zify.
all: try replace ( S (length msg / 64 - 1) ) with (length msg / 64) in * by prove_by_zify.
all: try reflexivity.
all:
rewrite <- fold_left_sha256_step_alt_firstn' by lia;
rewrite <- fold_left_sha256_step_alt_firstn' by lia;
reflexivity.
}
}
}
Time Qed.
Lemma sha256_output_correct : output_correct sha256.
Proof.
simplify_invariant sha256. cbn [absorb_any].
simplify_spec sha256.
(* The following gymnastics results in input_, state_, and repr_ being posed
as let-hypotheses, which makes proof debugging easier because one can look
at them and see what case the proof is dealing with *)
intros input state repr.
pose (input_:=input). pose (state_:=state). pose (repr_:=repr).
revert dependent repr. revert dependent state. revert dependent input.
intros (fifo_data_valid,
(fifo_data, (is_final, (final_length, (clear, []))))).
intro.
intros ((ready, (block, (digest, (count, done)))),
(sha256_padder_state, sha256_inner_state)).
intro.
intros (((((msg, msg_complete), padder_byte_index), inner_byte_index), t), cleared).
intros; logical_simplify; subst.
rewrite step_sha256_simplified_eq. cbv [step_sha256_simplified]. cbn [fst snd].
(* A whole bunch of assertions about the properties of padded_message_size
related to all 3 possible next messages *)
pose proof padded_message_size_mono
msg (new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof padded_message_bytes_longer_than_input msg.
pose proof padded_message_bytes_longer_than_input
(new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof padded_message_bytes_longer_than_input
(msg ++ new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof min_padded_message_size msg.
pose proof min_padded_message_size
(new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof min_padded_message_size
(msg ++ new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof padded_message_size_modulo msg.
pose proof padded_message_size_modulo
(new_msg_bytes fifo_data_valid fifo_data is_final final_length).
pose proof padded_message_size_modulo
(msg ++ new_msg_bytes fifo_data_valid fifo_data is_final final_length).
lazymatch goal with
| H : sha256_padder_invariant ?state ?repr
|- context [step sha256_padder ?state ?input] =>
assert (precondition sha256_padder input repr)
end.
{ simplify_spec sha256_padder; cbn [reset_repr sha256_padder_specification];
destr cleared; logical_simplify; subst;
[ destr fifo_data_valid; destr is_final; logical_simplify; subst;
ssplit; solve [auto] | ];
ssplit; [ assumption | ];
destr fifo_data_valid; logical_simplify; subst; [ | tauto ];
destr is_final; logical_simplify; subst; try tauto.
all: ssplit; try tauto.
all: destruct msg_complete; lia.
}
use_correctness' sha256_padder.
cbn [reset_repr sha256_padder_specification] in *.
(* prove that inner precondition is satisfied *)
lazymatch goal with
| H : sha256_inner_invariant ?state ?repr
|- context [step sha256_inner ?state ?input] =>
assert (precondition sha256_inner input repr)
end.
{
abstract (
simplify_spec sha256_inner; cbn [reset_repr sha256_inner_specification];
destr cleared; logical_simplify; subst;
[ destr fifo_data_valid; destr is_final; logical_simplify; subst;
ssplit; solve [auto] | ];
rewrite fold_left_sha256_step_alt_firstn;
destr (t =? 64); logical_simplify; subst; try lia;
destr (count <=? 15)%N; logical_simplify; subst;
destr (count =? 16)%N; logical_simplify; subst; try lia;
repeat (destruct_one_match; logical_simplify; subst; try lia);
repeat lazymatch goal with
| H : (Nat.eqb ?x ?y) = false |- _ => apply Nat.eqb_neq in H
end;
try (destr (padder_byte_index <? 64); logical_simplify; subst; [ | lia ]);
rewrite ?Nat.div_mul, ?Nat.div_small in * by lia;
try reflexivity;
try discriminate;
natsimpl;
repeat lazymatch goal with
| |- context [(?x + ?y) / ?y] => replace ((x + y) / y) with (x / y + 1) by prove_by_zify
| |- context [S (?x - 1)] => replace (S (x - 1)) with x by prove_by_zify
end;
natsimpl;
try (destr (inner_byte_index + 64 =? 64); logical_simplify; subst; lia);
lazymatch goal with
| |- _ /\ _ /\ _ => ssplit; [ reflexivity | | length_hammer ]
| _ => idtac
end;
rewrite ?firstn_slice_app by (push_length; prove_by_zify);
lazymatch goal with
| |- fold_left _ _ _ = fold_left _ _ _ =>
eapply fold_left_ext_In; intros *;
rewrite in_seq; intros;
rewrite !sha256_step_alt_firstn by lia;
try reflexivity
end).
}
use_correctness' sha256_inner.
cbn [reset_repr sha256_inner_specification] in *.
do 3 eexists; ssplit.
{ reflexivity. }
{ abstract(
destruct clear; [reflexivity|]; logical_simplify; subst;
destruct cleared; logical_simplify; subst; cbn [fst snd];
destr (0 <=? 15)%N; destr (16 =? 0)%N; destr (0 =? 0)%N; try lia; boolsimpl; logical_simplify;
subst; [ destruct fifo_data_valid; boolsimpl; reflexivity| ];
destr (count <=? 15)%N; destr (16 =? count)%N; try lia; boolsimpl; logical_simplify; subst;
repeat (destruct_one_match; logical_simplify; subst; try lia); boolsimpl;
repeat (match goal with
| |- context [ ?X =? ?Y ] => destr ( X =? Y); try lia
| |- context [ ?X <=? ?Y ] => destr ( X <=? Y); try lia
| |- context [ ( ?X =? ?Y )%N ] => destr ( X =? Y)%N; try lia
| |- context [ ( ?X <=? ?Y )%N ] => destr ( X <=? Y)%N; try lia
end; boolsimpl);
try lia;
repeat (destruct_one_match_hyp; logical_simplify; subst; try lia);
try lia; try prove_by_zify
).
}
{
abstract (
destruct clear; [reflexivity|]; logical_simplify; subst;
destruct cleared; logical_simplify; subst; cbn [fst snd];
destr (0 <=? 15)%N; destr (16 =? 0)%N; destr (0 =? 0)%N; try lia; boolsimpl; logical_simplify; subst;
[ destruct fifo_data_valid; boolsimpl; reflexivity |];
rewrite N.mod_small by (cbn; prove_by_zify);
destr (count <=? 15)%N; try lia; boolsimpl; logical_simplify; subst;
destr (16 =? count)%N; try lia; boolsimpl; logical_simplify; subst;
repeat (destruct_one_match; logical_simplify; subst; try lia);
boolsimpl;
repeat (match goal with
| |- context [ ?X =? ?Y ] => destr ( X =? Y); try lia
| |- context [ ?X <=? ?Y ] => destr ( X <=? Y); try lia
| |- context [ ( ?X =? ?Y )%N ] => destr ( X =? Y)%N; try lia
| |- context [ ( ?X <=? ?Y )%N ] => destr ( X <=? Y)%N; try lia
end; boolsimpl); try prove_by_zify;
repeat (match goal with
| H: context [ ?X =? ?Y ] |- _ => destr ( X =? Y); try lia
| H: context [ ?X <=? ?Y ] |- _ => destr ( X <=? Y); try lia
| H: context [ ( ?X =? ?Y )%N ] |- _ => destr ( X =? Y)%N; try lia
| H: context [ ( ?X <=? ?Y )%N ] |- _ => destr ( X <=? Y)%N; try lia
end; boolsimpl);
try lia; try prove_by_zify;
repeat (destruct_one_match_hyp; logical_simplify; subst; try lia);
try lia; try prove_by_zify).
}
destruct clear; [abstract reflexivity|]; logical_simplify; subst.
destruct cleared; logical_simplify; subst; cbn [fst snd];
destruct fifo_data_valid; boolsimpl; cbn [fst snd]; [abstract reflexivity .. | ].
destruct_one_match;[|abstract reflexivity].
Optimize Proof.
cbv [SHA256.sha256 SHA256.w]; replace (512 / N.to_nat 32) with 16 by (abstract prove_by_zify);
rewrite concat_digest_to_N_id; rewrite padded_message_length; cycle 1.
{ Time abstract (cbv [SHA256.sha256_step];
assert (seq 0 (padded_message_size msg / 4 / 16) <> []);
[ assert (1 <= padded_message_size msg / 4 / 16) by prove_by_zify;
apply length_pos_nonnil;
length_hammer
|];
pose proof (fold_left_exists_final (fun (H0 : list N) (i : nat) =>
List.map2 SHA256.add_mod H0
(fold_left (SHA256.sha256_compress (SHA256.W msg i)) (seq 0 64) H0))
(seq 0 (padded_message_size msg / 4 / 16)) SHA256.H0 H19) as Hff;
logical_simplify;
rewrite H21;
remember (fold_left (SHA256.sha256_compress (SHA256.W msg x4)) (seq 0 64) x3) as X;
clear;
rename x3 into a;
rename X into b;
rewrite map2_resize with (d := 0%N);
cbn zeta;
apply Forall2_implies_Forall_map2;
revert a;
induction b;
[ intros; destruct a; now cbn|];
intros;
destruct a0;[now cbn|];
push_length;
rewrite <- Min.succ_min_distr;
cbn zeta;
rewrite ? resize_cons;
constructor;
[ apply sha256_add_mod_bounded|];
apply IHb).
}
{ abstract (apply fold_left_sha256_step_length; reflexivity). }
destruct_one_match.
{ abstract (
destr (inner_byte_index =? 0);
[
repeat (match goal with
| H: context [ ?X =? ?Y ] |- _ => destr ( X =? Y); try lia
| H: context [ ?X <=? ?Y ] |- _ => destr ( X <=? Y); try lia
| H: context [ ( ?X =? ?Y )%N ] |- _ => destr ( X =? Y)%N; try lia
| H: context [ ( ?X <=? ?Y )%N ] |- _ => destr ( X <=? Y)%N; try lia
end; boolsimpl)|
];
destr (16 =? count)%N; try prove_by_zify;
destr (if if t =? 64 then true else false then true else t =? 63); [|prove_by_zify];
destr done; destr (count <=? 15)%N; destr (count =? 16)%N; logical_simplify; subst; try prove_by_zify;
repeat (match goal with
| H: context [ ?X =? ?Y ] |- _ => destr ( X =? Y); try lia
| H: context [ ?X <=? ?Y ] |- _ => destr ( X <=? Y); try lia
| H: context [ ( ?X =? ?Y )%N ] |- _ => destr ( X =? Y)%N; try lia
| H: context [ ( ?X <=? ?Y )%N ] |- _ => destr ( X <=? Y)%N; try lia
end; boolsimpl); try prove_by_zify).
}
all: repeat (match goal with
| H: context [ ?X =? ?Y ] |- _ => destr ( X =? Y); try lia
| H: context [ ?X <=? ?Y ] |- _ => destr ( X <=? Y); try lia
| H: context [ ( ?X =? ?Y )%N ] |- _ => destr ( X =? Y)%N; try lia
| H: context [ ( ?X <=? ?Y )%N ] |- _ => destr ( X <=? Y)%N; try lia
end; boolsimpl); try prove_by_zify.
all: logical_simplify; subst.
{ rewrite <- E4. reflexivity. }
do 2 f_equal.
prove_by_zify.
Qed.
Existing Instances sha256_invariant_preserved sha256_output_correct sha256_invariant_at_reset.
Global Instance sha256_correctness : correctness_for sha256.
Proof. constructor; try typeclasses eauto. Defined.
|
module logic_analyzer # (
parameter CAPTURE_WIDTH = 32,
parameter CAPTURE_DEPTH = 10
) (
input clk,
input rst,
input i_cap_clk,
input i_cap_ext_trig,
input [31:0] i_cap_data,
input [31:0] i_trigger,
input [31:0] i_trigger_mask,
input [31:0] i_trigger_after,
input [31:0] i_trigger_edge,
input [31:0] i_both_edges,
input [31:0] i_repeat_count,
input i_force_stb,
input i_enable,
input i_restart,
output reg [31:0] o_capture_start,
output reg o_finished = 0,
output [31:0] o_capture_size,
input [31:0] i_bram_addr,
output [CAPTURE_WIDTH - 1:0] o_bram_data
);
//Local Parameter
localparam CAPTURE_SIZE = (1 << CAPTURE_DEPTH);
localparam IDLE = 0;
localparam SETUP = 1;
localparam CONT_READ = 2;
localparam CAPTURE = 3;
localparam FINISHED = 4;
//Registers/Wires
reg [3:0] state;
reg [CAPTURE_DEPTH - 1: 0] r_in_pointer;
reg [CAPTURE_DEPTH - 1: 0] r_out_pointer;
reg [CAPTURE_DEPTH - 1: 0] r_start;
wire [CAPTURE_DEPTH - 1: 0] w_last;
wire w_full;
reg r_cap_wr_stb;
reg r_start_stb;
reg r_pos_start_stb;
reg r_neg_start_stb;
reg [31:0] r_repeat_count;
reg [31:0] r_prev_cap;
wire [31:0] w_cap_pos_edge;
wire [31:0] w_cap_neg_edge;
wire [31:0] w_cap_sig_start;
wire w_cap_start;
wire [31:0] w_inv_cap_data;
wire [31:0] w_inv_cap_prev_data;
//Submodules
dpb #(
.DATA_WIDTH (CAPTURE_WIDTH ),
.ADDR_WIDTH (CAPTURE_DEPTH )
) local_buffer (
.clka (i_cap_clk ),
.wea (r_cap_wr_stb ),
.addra (r_in_pointer ),
.dina (r_prev_cap ),
.clkb (clk ),
.web (1'b0 ),
.addrb (i_bram_addr[CAPTURE_DEPTH - 1:0] ),
.dinb (32'h0 ),
.doutb (o_bram_data )
);
//Asynchronous Logic
assign o_capture_size = CAPTURE_SIZE;
assign w_last = r_start + ((CAPTURE_SIZE - 1) - i_trigger_after);
assign w_full = r_in_pointer == w_last;
assign w_cap_start = (w_cap_sig_start == 32'hFFFFFFFF);
assign w_inv_cap_data = ~i_cap_data;
assign w_inv_cap_prev_data = ~r_prev_cap;
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : la
assign w_cap_pos_edge[i] = i_cap_data[i] & ~r_prev_cap[i];
assign w_cap_neg_edge[i] = ~i_cap_data[i] & r_prev_cap[i];
assign w_cap_sig_start[i] =
(~i_trigger_mask[i]) ? 1 : //If the mask is 0 then this is true
i_trigger_edge[i] ? //Look For Edge
(i_both_edges[i] & (w_cap_pos_edge[i] | w_cap_neg_edge[i])) | //Both Edges
(i_trigger[i] & w_cap_pos_edge[i]) | (~i_trigger[i] & w_cap_neg_edge[i]) : //Pos/Neg Edge
(i_trigger[i] & i_cap_data[i]) | (~i_trigger[i] & ~i_cap_data[i]);//Not edge but level and data
end
endgenerate
//Synchronous Logic
always @ (posedge i_cap_clk) begin
r_cap_wr_stb <= 0;
if (rst) begin
r_in_pointer <= 0;
r_start <= 0;
o_capture_start <= 0;
r_repeat_count <= 0;
r_prev_cap <= 32'h0;
state <= IDLE;
o_finished <= 0;
end
else begin
r_prev_cap <= i_cap_data;
case (state)
IDLE: begin
o_capture_start <= 0;
r_in_pointer <= 0;
r_repeat_count <= 0;
r_start <= 0;
if (i_enable) begin
if ((i_trigger_after > 0) || (i_repeat_count > 0)) begin
//Special Case, need to continue reading data, we have a history
state <= CONT_READ;
end
else if(w_cap_start || i_cap_ext_trig) begin
r_cap_wr_stb <= 1;
state <= CAPTURE;
end
end
if (i_force_stb) begin
state <= CAPTURE;
end
end
CONT_READ: begin
r_cap_wr_stb <= 1;
r_start <= r_start + 1;
r_in_pointer <= r_start + 1;
if (w_cap_start) begin
if (r_repeat_count < i_repeat_count) begin
r_repeat_count <= r_repeat_count + 1;
end
else begin
state <= CAPTURE;
end
end
end
CAPTURE: begin
if (w_full) begin
state <= FINISHED;
if (r_start < i_trigger_after) begin
//Wrap around case
o_capture_start <= (CAPTURE_SIZE - 1) + r_start - i_trigger_after;
end
else begin
o_capture_start <= r_start - i_trigger_after;
end
end
else begin
r_cap_wr_stb <= 1;
r_in_pointer <= r_in_pointer + 1;
end
end
FINISHED: begin
o_finished <= 1;
if (!i_enable) begin
o_finished <= 0;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////
// Module Name: vga
/////////////////////////////////////////////////////////////////
module vga_controller
(
input wire pclk,reset,
output wire hsync,vsync,valid,
output wire [9:0]h_cnt,
output wire [9:0]v_cnt
);
reg [9:0]pixel_cnt;
reg [9:0]line_cnt;
reg hsync_i,vsync_i;
wire hsync_default, vsync_default;
wire [9:0] HD, HF, HS, HB, HT, VD, VF, VS, VB, VT;
assign HD = 640;
assign HF = 16;
assign HS = 96;
assign HB = 48;
assign HT = 800;
assign VD = 480;
assign VF = 10;
assign VS = 2;
assign VB = 33;
assign VT = 525;
assign hsync_default = 1'b1;
assign vsync_default = 1'b1;
always@(posedge pclk)
if(reset)
pixel_cnt <= 0;
else if(pixel_cnt < (HT - 1))
pixel_cnt <= pixel_cnt + 1;
else
pixel_cnt <= 0;
always@(posedge pclk)
if(reset)
hsync_i <= hsync_default;
else if((pixel_cnt >= (HD + HF - 1))&&(pixel_cnt < (HD + HF + HS - 1)))
hsync_i <= ~hsync_default;
else
hsync_i <= hsync_default;
always@(posedge pclk)
if(reset)
line_cnt <= 0;
else if(pixel_cnt == (HT -1))
if(line_cnt < (VT - 1))
line_cnt <= line_cnt + 1;
else
line_cnt <= 0;
always@(posedge pclk)
if(reset)
vsync_i <= vsync_default;
else if((line_cnt >= (VD + VF - 1))&&(line_cnt < (VD + VF + VS - 1)))
vsync_i <= ~vsync_default;
else
vsync_i <= vsync_default;
assign hsync = hsync_i;
assign vsync = vsync_i;
assign valid = ((pixel_cnt < HD) && (line_cnt < VD));
assign h_cnt = (pixel_cnt < HD) ? pixel_cnt:10'd0;
assign v_cnt = (line_cnt < VD) ? line_cnt:10'd0;
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Configuration Simulation Model
// /___/ /\ Filename : SIM_CONFIGE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 10/31/12 - Initial version
// 09/09/13 - Fixed output IDCODE (CR 727695).
// 10/23/13 - Fixed IDCODE when ICAP_WIDTH = X16 (CR 737079).
// 02/14/14 - Fixed Non-Continous data loading problem (CR 690809).
// 05/28/14 - New simulation library message format.
// End Revision
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module SIM_CONFIGE3 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter DEVICE_ID = 32'h0,
parameter ICAP_SUPPORT = "FALSE",
parameter ICAP_WIDTH = "X8"
) (
output AVAIL,
output CSOB,
output PRDONE,
output PRERROR,
inout DONE,
input CCLK,
input CSB,
inout [31:0] D,
inout INITB,
input [2:0] M,
input PROGB,
input RDWRB
);
localparam FRAME_RBT_OUT_FILENAME = "frame_data_e2_rbt_out.txt";
localparam cfg_Tprog = 250000; // min PROG must be low
localparam cfg_Tpl = 100000; // max program latency us.
localparam STARTUP_PH0 = 3'b000;
localparam STARTUP_PH1 = 3'b001;
localparam STARTUP_PH2 = 3'b010;
localparam STARTUP_PH3 = 3'b011;
localparam STARTUP_PH4 = 3'b100;
localparam STARTUP_PH5 = 3'b101;
localparam STARTUP_PH6 = 3'b110;
localparam STARTUP_PH7 = 3'b111;
// tri0 GSR, GTS, GWE;
wire GSR;
wire GTS;
wire GWE;
wire cclk_in;
wire init_b_in;
wire prog_b_in;
wire rdwr_b_in;
reg rdwr_b_in1;
reg checka_en;
reg init_b_out;
reg [3:0] done_o;
integer frame_data_fd;
integer farn;
integer ib;
integer ib_skp, ci, bi;
reg frame_data_wen;
tri1 p_up;
reg por_b;
wire [2:0] m_in;
wire [31:0] d_in;
wire [31:0] d_out;
wire busy_out;
wire cso_b_out;
wire csi_b_in;
reg csi_b_ins;
wire d_out_en;
wire pll_locked;
reg pll_lockwt;
wire init_b_t;
wire prog_b_t;
wire bus_en;
wire [3:0] desync_flag;
wire [3:0] crc_rst;
reg [3:0] crc_bypass;
reg icap_on;
reg icap_clr;
reg icap_sync;
reg icap_desynch;
reg rd_desynch;
reg rd_desynch_tmp;
reg icap_init_done;
reg icap_init_done_dly;
wire [3:0] desynch_set1;
reg [1:0] icap_bw;
// assign DONE = p_up;
// assign INITB = p_up;
assign (strong1, weak0) glbl.GSR = GSR;
assign (strong1, weak0) glbl.GTS = GTS;
assign glbl.PROGB_GLBL = PROGB;
assign pll_locked = (glbl.PLL_LOCKG === 0) ? 0 : 1;
buf buf_cso (CSOB, cso_b_out);
buf buf_cclk (cclk_in, CCLK);
buf buf_cs (csi_b_in, CSB);
buf buf_din[31:0] (d_in, D);
bufif1 buf_dout[31:0] (D, d_out, d_out_en);
buf buf_init (init_b_in, INITB);
buf buf_m_0 (m_in[0], M[0]);
buf buf_m_1 (m_in[1], M[1]);
buf buf_m_2 (m_in[2], M[2]);
buf buf_prog (prog_b_in, PROGB);
buf buf_rw (rdwr_b_in, RDWRB);
time prog_pulse_low_edge;
time prog_pulse_low;
reg mode_sample_flag;
reg [3:0] buswid_flag_init;
reg [3:0] buswid_flag;
reg [1:0] buswidth[3:0];
wire [1:0] buswidth_ibtmp;
reg [1:0] buswidth_tmp[3:0];
reg [31:0] pack_in_reg[3:0];
reg [31:0] pack_in_reg_tmp0;
reg [31:0] pack_in_reg_tmps0;
reg [31:0] pack_in_reg_tmp;
reg [4:0] reg_addr[3:0];
reg [4:0] reg_addr_tmp;
reg [3:0] new_data_in_flag;
reg [3:0] wr_flag;
reg [3:0] rd_flag;
reg [3:0] cmd_wr_flag;
reg [3:0] cmd_reg_new_flag;
reg [3:0] cmd_rd_flag;
reg [3:0] bus_sync_flag;
reg [3:0] conti_data_flag;
integer wr_cnt[3:0];
integer conti_data_cnt[3:0];
integer rd_data_cnt[3:0];
integer abort_cnt;
reg [2:0] st_state0;
reg [2:0] st_state1;
reg [2:0] st_state2;
reg [2:0] st_state3;
reg [2:0] st_state0i;
reg [2:0] st_state1i;
reg [2:0] st_state2i;
reg [2:0] st_state3i;
reg startup_begin_flag0;
reg startup_end_flag0;
reg startup_begin_flag1;
reg startup_end_flag1;
reg startup_begin_flag2;
reg startup_end_flag2;
reg startup_begin_flag3;
reg startup_end_flag3;
reg [3:0] crc_ck;
reg [3:0] crc_ck_en;
reg [3:0] crc_err_flag;
wire [3:0] crc_err_flag_tot;
reg [3:0] crc_err_flag_reg;
wire [3:0] crc_en;
reg [31:0] crc_curr[3:0];
reg [31:0] crc_curr_tmp;
wire [31:0] crc_curr_cktmp;
reg [31:0] crc_new;
reg [36:0] crc_input;
reg [31:0] rbcrc_curr[3:0];
reg [31:0] rbcrc_new;
reg [36:0] rbcrc_input;
reg [3:0] gwe_out;
reg [3:0] gts_out;
reg [31:0] d_o;
reg [31:0] outbus;
reg [31:0] outbus_dly;
reg [31:0] outbus_dly1;
reg busy_o;
reg [31:0] tmp_val1;
reg [31:0] tmp_val2;
reg [31:0] crc_reg[3:0];
reg [31:0] crc_reg_tmp;
wire [31:0] crc_reg_cktmp;
reg [31:0] far_reg[3:0];
reg [31:0] far_addr;
reg [31:0] fdri_reg[3:0];
reg [31:0] fdro_reg[3:0];
reg [4:0] cmd_reg[3:0];
reg [31:0] ctl0_reg[3:0];
reg [31:0] mask_reg[3:0];
wire [31:0] stat_reg[3:0];
wire [31:0] stat_reg_tmp0;
wire [31:0] stat_reg_tmp1;
wire [31:0] stat_reg_tmp2;
wire [31:0] stat_reg_tmp3;
reg [31:0] lout_reg[3:0];
reg [31:0] cor0_reg[3:0];
reg [31:0] cor0_reg_tmp0;
reg [31:0] cor0_reg_tmp1;
reg [31:0] cor0_reg_tmp2;
reg [31:0] cor0_reg_tmp3;
reg [31:0] mfwr_reg[3:0];
reg [31:0] cbc_reg[3:0];
reg [31:0] idcode_reg[3:0];
reg [31:0] axss_reg[3:0];
reg [31:0] cor1_reg[3:0];
reg [31:0] cor1_reg_tmp0;
reg [31:0] cor1_reg_tmp1;
reg [31:0] cor1_reg_tmp2;
reg [31:0] cor1_reg_tmp3;
reg [31:0] csob_reg[3:0];
reg [31:0] wbstar_reg[3:0];
reg [31:0] timer_reg[3:0];
reg [31:0] rbcrc_hw_reg[3:0];
reg [31:0] rbcrc_sw_reg[3:0];
reg [31:0] rbcrc_live_reg[3:0];
reg [31:0] efar_reg[3:0];
reg [31:0] bootsts_reg[3:0];
reg [31:0] ctl1_reg[3:0];
reg [31:0] testmode_reg[3:0];
reg [31:0] memrd_param_reg[3:0];
reg [31:0] dwc_reg[3:0];
reg [31:0] trim_reg[3:0];
reg [31:0] bout_reg[3:0];
reg [31:0] bspi_reg[3:0];
reg [2:0] mode_pin_in;
reg [2:0] mode_reg;
reg [3:0] crc_reset;
reg [3:0] gsr_set;
reg [3:0] gts_usr_b;
reg [3:0] done_pin_drv;
reg [3:0] shutdown_set;
reg [3:0] desynch_set;
reg [2:0] done_cycle_reg0;
reg [2:0] done_cycle_reg1;
reg [2:0] done_cycle_reg2;
reg [2:0] done_cycle_reg3;
reg [2:0] gts_cycle_reg0;
reg [2:0] gts_cycle_reg1;
reg [2:0] gts_cycle_reg2;
reg [2:0] gts_cycle_reg3;
reg [2:0] gwe_cycle_reg0;
reg [2:0] gwe_cycle_reg1;
reg [2:0] gwe_cycle_reg2;
reg [2:0] gwe_cycle_reg3;
reg init_pin;
reg init_rst;
reg [2:0] nx_st_state0;
reg [2:0] nx_st_state1;
reg [2:0] nx_st_state2;
reg [2:0] nx_st_state3;
reg [3:0] ghigh_b;
reg [3:0] gts_cfg_b;
reg [3:0] eos_startup;
reg [3:0] startup_set;
reg [1:0] startup_set_pulse0;
reg [1:0] startup_set_pulse1;
reg [1:0] startup_set_pulse2;
reg [1:0] startup_set_pulse3;
reg abort_out_en;
reg [31:0] tmp_dword;
reg [15:0] tmp_word;
reg [7:0] tmp_byte;
reg [3:0] id_error_flag;
wire id_error_flag_t;
reg [3:0] iprog_b;
wire iprog_b_t;
reg [3:0] i_init_b_cmd;
wire i_init_b_cmd_t;
reg i_init_b;
reg [7:0] abort_status;
reg [3:0] persist_en;
reg [3:0] rst_sync;
reg [3:0] abort_dis;
reg [2:0] lock_cycle_reg0;
reg [2:0] lock_cycle_reg1;
reg [2:0] lock_cycle_reg2;
reg [2:0] lock_cycle_reg3;
reg [3:0] rbcrc_no_pin;
reg abort_flag_rst;
reg [3:0] gsr_st_out;
reg [3:0] gsr_cmd_out;
reg [3:0] gsr_cmd_out_pulse;
reg d_o_en;
wire rst_intl;
wire rw_en_tmp1;
wire [3:0] rw_en;
wire [3:0] gsr_out;
wire [3:0] cfgerr_b_flag;
reg [3:0] abort_flag;
integer downcont_cnt;
reg rst_en;
reg prog_b_a;
reg [3:0] csbo_flag;
reg [3:0] bout_flag;
reg [3:0] bout_flags;
reg [3:0] bout_bf;
reg [3:0] bout_en;
reg rd_sw_en;
integer csbo_cnt[3:0];
integer bout_cnt[3:0];
integer bout_cnt_tmp;
reg [4:0] rd_reg_addr[3:0];
reg done_release;
wire iprog_b_0;
wire iprog_b_1;
wire iprog_b_2;
wire iprog_b_3;
wire i_init_b_cmd_0;
wire i_init_b_cmd_1;
wire i_init_b_cmd_2;
wire i_init_b_cmd_3;
wire rw_en_tmp;
wire desync_flag_t;
wire abort_dis_bi;
assign (weak1, strong0) INITB=(mode_sample_flag) ? ~crc_err_flag_tot[ib] : init_b_out;
assign (weak1, strong0) DONE = (done_o[0] !== 1'b0) &&
((bout_en[1] == 0) || (done_o[1] !== 1'b0)) &&
((bout_en[2] == 0) || (done_o[2] !== 1'b0)) &&
((bout_en[3] == 0) || (done_o[3] !== 1'b0));
//
// assign (weak1, strong0) DONE= (bout_en[1] == 0) || done_o[1];
// assign (weak1, strong0) DONE= (bout_en[2] == 0) || done_o[2];
// assign (weak1, strong0) DONE= (bout_en[3] == 0) || done_o[3];
reg PRDONE_out;
assign PRDONE = PRDONE_out;
reg fdri_rst_prdone_flag;
localparam MODULE_NAME = "SIM_CONFIGE3";
always @(fdri_rst_prdone_flag or desync_flag or eos_startup)
if (fdri_rst_prdone_flag) begin
PRDONE_out = 1'b0;
end else if ((&desync_flag) & (&eos_startup)) begin
PRDONE_out = 1'b1;
end
assign PRERROR = (|rw_en) & (|crc_err_flag_tot);
initial begin
if (DEVICE_ID == "036A2093" || DEVICE_ID == "03702093")
bout_en = 4'b0011;
else if (DEVICE_ID == "036A4093" || DEVICE_ID == "03704093")
bout_en = 4'b0111;
else if (DEVICE_ID == "036A6093")
bout_en = 4'b1111;
else
bout_en = 4'b0001;
end
initial begin
buswidth_tmp[0] = 2'b00;
buswidth_tmp[1] = 2'b00;
buswidth_tmp[2] = 2'b00;
buswidth_tmp[3] = 2'b00;
pack_in_reg[0] = 32'b0;
pack_in_reg[1] = 32'b0;
pack_in_reg[2] = 32'b0;
pack_in_reg[3] = 32'b0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
pack_in_reg_tmp = 32'b0;
crc_curr[0] = 32'b0;
crc_curr[1] = 32'b0;
crc_curr[2] = 32'b0;
crc_curr[3] = 32'b0;
rbcrc_curr[0] = 32'b0;
rbcrc_curr[1] = 32'b0;
rbcrc_curr[2] = 32'b0;
rbcrc_curr[3] = 32'b0;
ctl0_reg[0] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[1] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[2] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
ctl0_reg[3] = 32'b000xxxxxxxxxxxxxx000000100000xx1;
cor0_reg[0] = 32'b00000000000000000011111111101100;
cor0_reg[1] = 32'b00000000000000000011111111101100;
cor0_reg[2] = 32'b00000000000000000011111111101100;
cor0_reg[3] = 32'b00000000000000000011111111101100;
cor0_reg_tmp0 = cor0_reg[0];
cor0_reg_tmp1 = cor0_reg[1];
cor0_reg_tmp2 = cor0_reg[2];
cor0_reg_tmp3 = cor0_reg[3];
done_cycle_reg0 = cor0_reg_tmp0[14:12];
lock_cycle_reg0 = cor0_reg_tmp0[8:6];
done_cycle_reg1 = cor0_reg_tmp0[14:12];
lock_cycle_reg1 = cor0_reg_tmp0[8:6];
done_cycle_reg2 = cor0_reg_tmp0[14:12];
lock_cycle_reg2 = cor0_reg_tmp0[8:6];
done_cycle_reg3 = cor0_reg_tmp0[14:12];
lock_cycle_reg3 = cor0_reg_tmp0[8:6];
cor1_reg[0] = 32'b0;
cor1_reg[1] = 32'b0;
cor1_reg[2] = 32'b0;
cor1_reg[3] = 32'b0;
cor1_reg_tmp0 = 32'b0;
cor1_reg_tmp1 = 32'b0;
cor1_reg_tmp2 = 32'b0;
cor1_reg_tmp3 = 32'b0;
wbstar_reg[0] = 32'b0;
wbstar_reg[1] = 32'b0;
wbstar_reg[2] = 32'b0;
wbstar_reg[3] = 32'b0;
timer_reg[0] = 32'b0;
timer_reg[1] = 32'b0;
timer_reg[2] = 32'b0;
timer_reg[3] = 32'b0;
bootsts_reg[0] = 32'b0;
bootsts_reg[1] = 32'b0;
bootsts_reg[2] = 32'b0;
bootsts_reg[3] = 32'b0;
ctl1_reg[0] = 32'b0;
ctl1_reg[1] = 32'b0;
ctl1_reg[2] = 32'b0;
ctl1_reg[3] = 32'b0;
testmode_reg[0] = 32'b0;
testmode_reg[1] = 32'b0;
testmode_reg[2] = 32'b0;
testmode_reg[3] = 32'b0;
memrd_param_reg[0] = 32'b0;
memrd_param_reg[1] = 32'b0;
memrd_param_reg[2] = 32'b0;
memrd_param_reg[3] = 32'b0;
dwc_reg[0] = 32'b0;
dwc_reg[1] = 32'b0;
dwc_reg[2] = 32'b0;
dwc_reg[3] = 32'b0;
trim_reg[0] = 32'b0;
trim_reg[1] = 32'b0;
trim_reg[2] = 32'b0;
trim_reg[3] = 32'b0;
bout_reg[0] = 32'b0;
bout_reg[1] = 32'b0;
bout_reg[2] = 32'b0;
bout_reg[3] = 32'b0;
bspi_reg[0] = 32'h000B;
bspi_reg[1] = 32'h000B;
bspi_reg[2] = 32'h000B;
bspi_reg[3] = 32'h000B;
rd_reg_addr[0] = 5'b0;
rd_reg_addr[1] = 5'b0;
rd_reg_addr[2] = 5'b0;
rd_reg_addr[3] = 5'b0;
wr_cnt[0] = 0;
wr_cnt[1] = 0;
wr_cnt[2] = 0;
wr_cnt[3] = 0;
bout_cnt[0] = 0;
bout_cnt[1] = 0;
bout_cnt[2] = 0;
bout_cnt[3] = 0;
done_o = 4'b0;
checka_en = 1'b0;
init_b_out = 1'b1;
farn = 0;
ib = 0;
csi_b_ins = 1'b1;
crc_bypass = 4'b0000;
icap_clr = 1'b0;
icap_desynch = 1'b0;
rd_desynch = 1'b0;
rd_desynch_tmp = 1'b0;
icap_init_done = 1'b0;
icap_init_done_dly = 1'b0;
prog_pulse_low_edge = 0;
prog_pulse_low = 0;
mode_sample_flag = 1'b0;
buswid_flag_init = 4'b0000;
buswid_flag = 4'b0000;
new_data_in_flag = 4'b0000;
wr_flag = 4'b0000;
rd_flag = 4'b0000;
cmd_wr_flag = 4'b0000;
cmd_reg_new_flag = 4'b0000;
cmd_rd_flag = 4'b0000;
bus_sync_flag = 4'b0000;
conti_data_flag = 4'b0000;
st_state0 = STARTUP_PH0;
st_state1 = STARTUP_PH0;
st_state2 = STARTUP_PH0;
st_state3 = STARTUP_PH0;
st_state0i = STARTUP_PH0;
st_state1i = STARTUP_PH0;
st_state2i = STARTUP_PH0;
st_state3i = STARTUP_PH0;
startup_begin_flag0 = 1'b0;
startup_end_flag0 = 1'b0;
startup_begin_flag1 = 1'b0;
startup_end_flag1 = 1'b0;
startup_begin_flag2 = 1'b0;
startup_end_flag2 = 1'b0;
startup_begin_flag3 = 1'b0;
startup_end_flag3 = 1'b0;
crc_ck = 4'b0000;
crc_ck_en = 4'b1111;
crc_err_flag = 4'b0000;
crc_err_flag_reg = 4'b0000;
gwe_out = 4'b0000;
gts_out = 4'b1111;
d_o = 32'h0;
outbus = 32'h0;
outbus_dly = 32'h0;
outbus_dly1 = 32'h0;
busy_o = 1'b0;
mode_pin_in = 3'b000;
crc_reset = 4'b0000;
gsr_set = 4'b0000;
gts_usr_b = 4'b1111; // was 4'b111
done_pin_drv = 4'b0000;
shutdown_set = 4'b0000;
desynch_set = 4'b0000;
done_cycle_reg0 = 3'b011;
done_cycle_reg1 = 3'b011;
done_cycle_reg2 = 3'b011;
done_cycle_reg3 = 3'b011;
gts_cycle_reg0 = 3'b101;
gts_cycle_reg1 = 3'b101;
gts_cycle_reg2 = 3'b101;
gts_cycle_reg3 = 3'b101;
gwe_cycle_reg0 = 3'b100;
gwe_cycle_reg1 = 3'b100;
gwe_cycle_reg2 = 3'b100;
gwe_cycle_reg3 = 3'b100;
init_rst = 1'b0;
nx_st_state0 = 3'b000;
nx_st_state1 = 3'b000;
nx_st_state2 = 3'b000;
nx_st_state3 = 3'b000;
ghigh_b = 4'b0000;
gts_cfg_b = 4'b0000;
eos_startup = 4'b0000;
startup_set = 4'b0000;
startup_set_pulse0 = 2'b00;
startup_set_pulse1 = 2'b00;
startup_set_pulse2 = 2'b00;
startup_set_pulse3 = 2'b00;
abort_out_en = 1'b0;
id_error_flag = 4'b0000;
iprog_b = 4'b1111;
i_init_b_cmd = 4'b1111;
i_init_b = 1'b0;
abort_status = 8'b00000000;
persist_en = 1'b0;
rst_sync = 1'b0;
abort_dis = 1'b0;
lock_cycle_reg0 = 3'b000;
lock_cycle_reg1 = 3'b000;
lock_cycle_reg2 = 3'b000;
lock_cycle_reg3 = 3'b000;
rbcrc_no_pin = 4'b0000;
abort_flag_rst = 1'b0;
gsr_st_out = 4'b1111;
gsr_cmd_out = 4'b0000;
gsr_cmd_out_pulse = 4'b0000;
d_o_en = 1'b0;
abort_flag = 4'b0000;
downcont_cnt = 0;
rst_en = 1'b0;
prog_b_a = 1'b1;
csbo_flag = 4'b0000;
bout_flag = 4'b0000;
bout_flags = 4'b0000;
bout_bf = 4'b0000;
rd_sw_en = 1'b0;
done_release = 1'b0;
PRDONE_out = 1'b0;
fdri_rst_prdone_flag = 1'b0;
end
initial begin
case (ICAP_SUPPORT)
"FALSE" : icap_on = 0;
"TRUE" : icap_on = 1;
default : icap_on = 0;
endcase
if (DEVICE_ID == 32'h0 && icap_on == 0) begin
$display("Error: [Unisim %s-1] DEVICE_ID attribute is not set. Instance: %m", MODULE_NAME);
end
if (ICAP_SUPPORT == "TRUE") begin
case (ICAP_WIDTH)
"X8" : icap_bw = 2'b01;
"X16" : icap_bw = 2'b10;
"X32" : icap_bw = 2'b11;
default : icap_bw = 2'b01;
endcase
frame_data_fd = $fopen(FRAME_RBT_OUT_FILENAME, "w");
if (frame_data_fd != 0) begin
frame_data_wen = 1;
$fwriteh(frame_data_fd, "frame_address frame_data readback_crc_value\n");
end
end
else begin
icap_bw = 2'b00;
frame_data_wen = 0;
end
icap_sync = 0;
end
assign GSR = gsr_out[0];
assign GTS = gts_out[0];
assign GWE = gwe_out[0];
assign busy_out = busy_o;
assign cfgerr_b_flag[0] = rw_en[0] & ~crc_err_flag_tot[0];
assign cfgerr_b_flag[1] = rw_en[1] & ~crc_err_flag_tot[1];
assign cfgerr_b_flag[2] = rw_en[2] & ~crc_err_flag_tot[2];
assign cfgerr_b_flag[3] = rw_en[3] & ~crc_err_flag_tot[3];
assign crc_err_flag_tot[0] = id_error_flag[0] | crc_err_flag_reg[0];
assign crc_err_flag_tot[1] = id_error_flag[1] | crc_err_flag_reg[1];
assign crc_err_flag_tot[2] = id_error_flag[2] | crc_err_flag_reg[2];
assign crc_err_flag_tot[3] = id_error_flag[3] | crc_err_flag_reg[3];
assign d_out[7:0] = (abort_out_en ) ? abort_status : outbus_dly[7:0];
assign d_out[31:8] = (abort_out_en ) ? 24'b0 : outbus_dly[31:8];
assign d_out_en = d_o_en;
assign cso_b_out = (csbo_flag[0] == 1) ? 0 : 1;
assign crc_en = (icap_init_done) ? 4'b0 : 4'b1111;
always @(posedge cclk_in) begin
outbus_dly <= outbus_dly1;
outbus_dly1 <= outbus;
end
always @(posedge cclk_in or csi_b_in)
if (csi_b_in == 1)
csi_b_ins <= csi_b_in;
else begin
if (cclk_in != 1)
csi_b_ins <= csi_b_in;
else
@(negedge cclk_in)
csi_b_ins <= csi_b_in;
end
always @(abort_out_en or csi_b_in or rdwr_b_in && rd_flag[ib] )
if (abort_out_en == 1)
d_o_en = 1;
else
d_o_en = rdwr_b_in & ~csi_b_in & rd_flag[ib];
assign init_b_t = init_b_in & i_init_b_cmd_t;
always @( negedge prog_b_in) begin
rst_en = 0;
rst_en <= #cfg_Tprog 1;
end
assign iprog_b_0 = iprog_b[0];
assign iprog_b_1 = (bout_en[1] == 1) ? iprog_b[1] : 1;
assign iprog_b_2 = (bout_en[2] == 1) ? iprog_b[2] : 1;
assign iprog_b_3 = (bout_en[3] == 1) ? iprog_b[3] : 1;
assign iprog_b_t = iprog_b_3 & iprog_b_2 & iprog_b_1 & iprog_b_0;
assign i_init_b_cmd_0 = i_init_b_cmd[0];
assign i_init_b_cmd_1 = (bout_en[1] == 1) ? i_init_b_cmd[1] : 1;
assign i_init_b_cmd_2 = (bout_en[2] == 1) ? i_init_b_cmd[2] : 1;
assign i_init_b_cmd_3 = (bout_en[3] == 1) ? i_init_b_cmd[3] : 1;
assign i_init_b_cmd_t = i_init_b_cmd_0 & i_init_b_cmd_1 & i_init_b_cmd_2
& i_init_b_cmd_3;
always @( rst_en or init_rst or prog_b_in or iprog_b_t )
if (icap_on == 0) begin
if (init_rst == 1)
init_b_out <= 0;
else begin
if ((prog_b_in == 0 ) && (rst_en == 1) || (iprog_b_t == 0))
init_b_out <= 0;
else if ((prog_b_in == 1 ) && (rst_en == 1) || (iprog_b_t == 1))
init_b_out <= #(cfg_Tpl) 1;
end
end
assign id_error_flag_t = &id_error_flag;
always @(posedge id_error_flag_t) begin
init_rst <= 1;
init_rst <= #cfg_Tprog 0;
end
always @( rst_en or prog_b_in or prog_pulse_low)
if (rst_en == 1) begin
if (prog_pulse_low==cfg_Tprog) begin
prog_b_a = 0;
prog_b_a <= #500 1;
end
else
prog_b_a = prog_b_in;
end
else
prog_b_a = 1;
initial begin
por_b = 0;
por_b = #400000 1;
end
assign prog_b_t = prog_b_a & iprog_b_t & por_b;
assign rst_intl = (prog_b_t==0 ) ? 0 : 1;
always @( init_b_t or prog_b_t)
if (prog_b_t == 0)
mode_sample_flag <= 0;
else if (init_b_t && mode_sample_flag == 0) begin
if (prog_b_t == 1) begin
mode_pin_in <= m_in;
if (m_in !== 3'b110) begin
mode_sample_flag <= 0;
if ( icap_on == 0)
$display("Error: [Unisim %s-2] Input M is %h. Only Slave SelectMAP mode M=110 is supported. Instance %m.", MODULE_NAME, m_in);
end
else
mode_sample_flag <= #1 1;
end
end
always @(posedge init_b_t )
if (prog_b_t != 1) begin
if ($time != 0 && icap_on == 0)
$display("Error: [Unisim %s-3] PROGB is not high when INITB goes high at time %t. Instance %m.", MODULE_NAME, $time);
end
always @(m_in)
if (mode_sample_flag == 1 && persist_en[0] == 1 && icap_on == 0)
$display("Error: [Unisim %s-4] Mode pine M[2:0] changed after rising edge of INITB at time %t. Instance %m.", MODULE_NAME, $time);
always @(posedge prog_b_in or negedge prog_b_in)
if (prog_b_in == 0)
prog_pulse_low_edge <= $time;
else if (prog_b_in == 1 && $time > 0) begin
prog_pulse_low = $time - prog_pulse_low_edge;
if (prog_pulse_low < cfg_Tprog && icap_on == 0)
$display("Error: [Unisim %s-5] Low time of PROGB is less than required minimum Tprogram time %d at time %t. Instance %m.", MODULE_NAME, cfg_Tprog, $time);
end
assign bus_en = (mode_sample_flag == 1 && csi_b_in ==0) ? 1 : 0;
always @(posedge cclk_in or negedge rst_intl )
if (rst_intl == 0 ) begin
buswid_flag_init <= 4'b0;
buswid_flag <= 4'b0;
buswidth_tmp[0] <= 2'b00;
buswidth_tmp[1] <= 2'b00;
buswidth_tmp[2] <= 2'b00;
buswidth_tmp[3] <= 2'b00;
end
else
if (buswid_flag[ib] == 0) begin
if (bus_en == 1 && rdwr_b_in == 0) begin
tmp_byte = bit_revers8(d_in[7:0]);
if (buswid_flag_init[ib] == 0) begin
if (tmp_byte == 8'hBB)
buswid_flag_init[ib] <= 1;
end
else begin
if (tmp_byte == 8'h11) begin // x8
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b01;
end
else if (tmp_byte == 8'h22) begin // x16
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b10;
end
else if (tmp_byte == 8'h44) begin // x32
buswid_flag[ib] <= 1;
buswidth_tmp[ib] <= 2'b11;
end
else begin
buswid_flag[ib] <= 0;
buswidth_tmp[ib] <= 2'b00;
buswid_flag_init[ib] <= 0;
if (icap_on == 0)
$display("Error: [Unisim %s-6] BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on D[7:0] followed 0xBB at time %t. Instance %m.", MODULE_NAME, $time);
else
$display("Error: [Unisim %s-7] BUS Width Auto Dection did not find 0x11 or 0x22 or 0x44 on dix[7:0] followed 0xBB on ICAPE3 instance at time %t. Instance %m.", MODULE_NAME, $time);
end
end
end
end
assign buswidth_ibtmp = (icap_on == 1 && icap_init_done == 1) ? icap_bw[1:0] : buswidth_tmp[ib];
always @(buswidth_ibtmp)
buswidth[ib] = buswidth_ibtmp;
assign rw_en_tmp = (bus_en == 1 ) ? 1 : 0;
assign rw_en[0] = ( buswid_flag[0] == 1) ? rw_en_tmp : 0;
assign rw_en[1] = ( buswid_flag[1] == 1) ? rw_en_tmp : 0;
assign rw_en[2] = ( buswid_flag[2] == 1) ? rw_en_tmp : 0;
assign rw_en[3] = ( buswid_flag[3] == 1) ? rw_en_tmp : 0;
assign desynch_set1[0] = desynch_set[0] | icap_desynch | rd_desynch;
assign desynch_set1[1] = desynch_set[1] | icap_desynch | rd_desynch;
assign desynch_set1[2] = desynch_set[2] | icap_desynch | rd_desynch;
assign desynch_set1[3] = desynch_set[3] | icap_desynch | rd_desynch;
assign desync_flag[0] = ~rst_intl | desynch_set1[0] | crc_err_flag[0] | id_error_flag[0];
assign desync_flag[1] = ~rst_intl | desynch_set1[1] | crc_err_flag[1] | id_error_flag[1];
assign desync_flag[2] = ~rst_intl | desynch_set1[2] | crc_err_flag[2] | id_error_flag[2];
assign desync_flag[3] = ~rst_intl | desynch_set1[3] | crc_err_flag[3] | id_error_flag[3];
always @(posedge eos_startup[0])
if (icap_on == 1) begin
$fclose(frame_data_fd);
icap_init_done <= 1;
@(posedge cclk_in);
@(posedge cclk_in)
if (icap_init_done_dly == 0)
icap_desynch <= 1;
@(posedge cclk_in);
@(posedge cclk_in) begin
icap_desynch <= 0;
icap_init_done_dly <= 1;
end
@(posedge cclk_in);
@(posedge cclk_in);
@(posedge cclk_in);
end
else begin
icap_clr <= 0;
icap_desynch <= 0;
end
always @(posedge cclk_in or negedge rdwr_b_in)
if (rdwr_b_in == 0)
rd_sw_en <= 0;
else begin
if (csi_b_in == 1 && rdwr_b_in ==1)
rd_sw_en <= 1;
end
assign desync_flag_t = |desync_flag;
always @(posedge cclk_in or posedge desync_flag_t or negedge csi_b_in) begin
if (desync_flag[ib] == 1) begin
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
if (desync_flag[0] == 1 ) begin
new_data_in_flag[0] = 0;
bus_sync_flag[0] = 0;
wr_cnt[0] = 0;
wr_flag[0] = 0;
rd_flag[0] = 0;
end
if (desync_flag[1] == 1 ) begin
new_data_in_flag[1] = 0;
bus_sync_flag[1] = 0;
wr_cnt[1] = 0;
wr_flag[1] = 0;
rd_flag[1] = 0;
end
if (desync_flag[2] == 1 ) begin
new_data_in_flag[2] = 0;
bus_sync_flag[2] = 0;
wr_cnt[2] = 0;
wr_flag[2] = 0;
rd_flag[2] = 0;
end
if (desync_flag[3] == 1 ) begin
new_data_in_flag[3] = 0;
bus_sync_flag[3] = 0;
wr_cnt[3] = 0;
wr_flag[3] = 0;
rd_flag[3] = 0;
end
if (icap_init_done == 1 && csi_b_in == 1 && rdwr_b_in == 0) begin
new_data_in_flag = 4'b0;
wr_cnt[0] = 0;
wr_cnt[1] = 0;
wr_cnt[2] = 0;
wr_cnt[3] = 0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
else begin
if (icap_clr == 1) begin
new_data_in_flag <= 4'b0;
wr_cnt[0] <= 0;
wr_cnt[1] <= 0;
wr_cnt[2] <= 0;
wr_cnt[3] <= 0;
wr_flag <= 4'b0;
rd_flag <= 4'b0;
pack_in_reg_tmp0 = 32'b0;
pack_in_reg_tmps0 = 32'b0;
end
else if (rw_en[ib] == 1 && desync_flag[ib] == 0) begin
if (rdwr_b_in == 0) begin
wr_flag[ib] <= 1;
rd_flag[ib] <= 0;
if (buswidth[ib] == 2'b01 || (icap_sync == 1 && bus_sync_flag[ib] == 0)) begin
tmp_byte = bit_revers8(d_in[7:0]);
if (bus_sync_flag[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (pack_in_reg_tmp0[23:16] == 8'hAA && pack_in_reg_tmp0[15:8] == 8'h99
&& pack_in_reg_tmp0[7:0] == 8'h55 && tmp_byte == 8'h66) begin
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 0;
end
else begin
pack_in_reg_tmp0[31:24] = pack_in_reg_tmp0[23:16];
pack_in_reg_tmp0[23:16] = pack_in_reg_tmp0[15:8];
pack_in_reg_tmp0[15:8] = pack_in_reg_tmp0[7:0];
pack_in_reg_tmp0[7:0] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
end
end
else begin
if (wr_cnt[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[31:24] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 1;
end
else if (wr_cnt[ib] == 1) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[23:16] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 2;
end
else if (wr_cnt[ib] == 2) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[15:8] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 3;
end
else if (wr_cnt[ib] == 3) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
pack_in_reg_tmp0[7:0] = tmp_byte;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 1;
wr_cnt[ib] <= 0;
end
end
end
else if (buswidth[ib] == 2'b10) begin
tmp_word = {bit_revers8(d_in[15:8]), bit_revers8(d_in[7:0])};
if (bus_sync_flag[ib] == 0) begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (pack_in_reg_tmp0[15:0] == 16'hAA99 && tmp_word ==16'h5566) begin
wr_cnt[ib] <= 0;
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
end
else begin
pack_in_reg_tmp0[31:16] = pack_in_reg_tmp0[15:0];
pack_in_reg_tmp0[15:0] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 0;
end
end
else begin
pack_in_reg_tmp0 = pack_in_reg[ib];
if (wr_cnt[ib] == 0) begin
pack_in_reg_tmp0[31:16] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 0;
wr_cnt[ib] <= 1;
end
else if (wr_cnt[ib] == 1) begin
pack_in_reg_tmp0[15:0] = tmp_word;
pack_in_reg_tmps0 <= pack_in_reg_tmp0;
new_data_in_flag[ib] <= 1;
wr_cnt[ib] <= 0;
end
end
end
else if (buswidth[ib] == 2'b11 ) begin
tmp_dword = {bit_revers8(d_in[31:24]), bit_revers8(d_in[23:16]), bit_revers8(d_in[15:8]),
bit_revers8(d_in[7:0])};
pack_in_reg_tmp0 <= tmp_dword;
pack_in_reg_tmps0 <= tmp_dword;
if (bus_sync_flag[ib] == 0) begin
if (tmp_dword == 32'hAA995566) begin
bus_sync_flag[ib] <= 1;
new_data_in_flag[ib] <= 0;
end
end
else begin
pack_in_reg_tmp0 <= tmp_dword;
pack_in_reg_tmps0 <= tmp_dword;
new_data_in_flag[ib] <= 1;
end
end
end
else begin
wr_flag[ib] <= 0;
new_data_in_flag[ib] <= 0;
if (rd_sw_en ==1)
rd_flag[ib] <= 1;
end
end
else begin
wr_flag[ib] <= 0;
rd_flag[ib] <= 0;
new_data_in_flag[ib] <= 0;
end
end
end
always @(pack_in_reg_tmps0 or desync_flag or icap_clr)
begin
if (desync_flag[0] == 1 || icap_clr == 1)
pack_in_reg[0] = 32'b0;
if (desync_flag[1] == 1 || icap_clr == 1)
pack_in_reg[1] = 32'b0;
if (desync_flag[2] == 1 || icap_clr == 1)
pack_in_reg[2] = 32'b0;
if (desync_flag[3] == 1 || icap_clr == 1)
pack_in_reg[3] = 32'b0;
if (ib == 0 && desync_flag[0] == 0 && icap_clr == 0) begin
pack_in_reg[0] = pack_in_reg_tmps0;
end
else if (ib == 1 && desync_flag[1] == 0 && icap_clr == 0)
pack_in_reg[1] = pack_in_reg_tmps0;
else if (ib == 2 && desync_flag[2] == 0 && icap_clr == 0)
pack_in_reg[2] = pack_in_reg_tmps0;
else if (ib == 3 && desync_flag[3] == 0 && icap_clr == 0)
pack_in_reg[3] = pack_in_reg_tmps0;
end
task rst_pack_dec;
input ib_d;
begin
conti_data_flag[ib_d] <= 0;
conti_data_cnt[ib_d] <= 0;
cmd_wr_flag[ib_d] <= 0;
cmd_rd_flag[ib_d] <= 0;
id_error_flag[ib_d] <= 0;
crc_curr[ib_d] <= 32'b0;
crc_ck[ib_d] <= 0;
csbo_cnt[ib_d] <= 0;
csbo_flag[ib_d] <= 0;
downcont_cnt <= 0;
rd_data_cnt[ib_d] <= 0;
end
endtask
always @(negedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
rst_pack_dec(0);
rst_pack_dec(1);
rst_pack_dec(2);
rst_pack_dec(3);
bout_flag <= 4'b0;
bout_cnt[0] <= 0;
bout_cnt[1] <= 0;
bout_cnt[2] <= 0;
bout_cnt[3] <= 0;
end
else begin
if (icap_clr == 1) begin
rst_pack_dec(0);
rst_pack_dec(1);
rst_pack_dec(2);
rst_pack_dec(3);
bout_flag <= 4'b0;
bout_cnt[0] <= 0;
bout_cnt[1] <= 0;
bout_cnt[2] <= 0;
bout_cnt[3] <= 0;
end
if (crc_reset[ib] == 1 ) begin
crc_reg[ib] <= 32'b0;
crc_ck[ib] <= 0;
crc_curr[ib] <= 32'b0;
end
if (crc_ck[ib] == 1) begin
crc_curr[ib] <= 32'b0;
crc_ck[ib] <= 0;
end
if (desynch_set1[0] == 1 || crc_err_flag[0] == 1) begin
bout_flag[0] <= 0;
bout_cnt[0] <= 0;
rst_pack_dec(0);
end
if (desynch_set1[1] == 1 || crc_err_flag[1] == 1) begin
bout_flag[1] <= 0;
bout_cnt[1] <= 0;
rst_pack_dec(1);
end
if (desynch_set1[2] == 1 || crc_err_flag[2] == 1) begin
bout_flag[2] <= 0;
bout_cnt[2] <= 0;
rst_pack_dec(2);
end
if (desynch_set1[3] == 1 || crc_err_flag[3] == 1) begin
bout_flag[3] <= 0;
bout_cnt[3] <= 0;
rst_pack_dec(3);
end
if (new_data_in_flag[ib] == 1 && wr_flag[ib] == 1 && csi_b_ins == 0
&& desynch_set1[ib] == 0 && crc_err_flag[ib] == 0 && icap_clr == 0) begin
pack_in_reg_tmp = pack_in_reg[ib];
if (conti_data_flag[ib] == 1 ) begin
reg_addr_tmp = reg_addr[ib];
case (reg_addr_tmp)
5'b00000 : begin
crc_reg[ib] <= pack_in_reg[ib];
crc_reg_tmp <= pack_in_reg[ib];
crc_ck[ib] <= 1;
end
5'b00001 : far_reg[ib] <= {6'b0, pack_in_reg_tmp[25:0]};
5'b00010 : begin
fdri_reg[ib] <= pack_in_reg[ib];
fdri_rst_prdone_flag <= ~fdri_rst_prdone_flag;
end
5'b00100 : cmd_reg[ib] <= pack_in_reg_tmp[4:0];
5'b00101 : ctl0_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl0_reg[ib] & ~mask_reg[ib]);
5'b00110 : mask_reg[ib] <= pack_in_reg[ib];
5'b01000 : lout_reg[ib] <= pack_in_reg[ib];
5'b01001 : cor0_reg[ib] <= pack_in_reg[ib];
5'b01010 : mfwr_reg[ib] <= pack_in_reg[ib];
5'b01011 : cbc_reg[ib] <= pack_in_reg[ib];
5'b01100 : begin
idcode_reg[ib] <= pack_in_reg[ib];
if (pack_in_reg_tmp[27:0] != DEVICE_ID[27:0]) begin
id_error_flag[ib] <= 1;
if (icap_on == 0)
$display("Error: [Unisim %s-8] Written value to IDCODE register is %h which does not match with DEVICE ID %h on %s at time %t. Instance %m", MODULE_NAME, pack_in_reg[ib], DEVICE_ID, MODULE_NAME, $time);
else
$display("Error: [Unisim %s-9] Written value to IDCODE register is %h which does not match with DEVICE ID %h on ICAPE3 at time %t. Instance %m", MODULE_NAME, pack_in_reg[ib], DEVICE_ID, $time);
end
else
id_error_flag[ib] <= 0;
end
5'b01101 : axss_reg[ib] <= pack_in_reg[ib];
5'b01110 : cor1_reg[ib] <= pack_in_reg[ib];
5'b01111 : csob_reg[ib] <= pack_in_reg[ib];
5'b10000 : wbstar_reg[ib] <= pack_in_reg[ib];
5'b10001 : timer_reg[ib] <= pack_in_reg[ib];
5'b10011 : rbcrc_sw_reg[ib] <= pack_in_reg[ib];
5'b10111 : testmode_reg[ib] <= pack_in_reg[ib];
5'b11000 : ctl1_reg[ib] <= (pack_in_reg[ib] & mask_reg[ib]) | (ctl1_reg[ib] & ~mask_reg[ib]);
5'b11001 : memrd_param_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]};
5'b11010 : dwc_reg[ib] <= {4'b0, pack_in_reg_tmp[27:0]};
5'b11011 : trim_reg[ib] <= pack_in_reg[ib];
5'b11110 : bout_reg[ib] <= pack_in_reg[ib];
5'b11111 : bspi_reg[ib] <= pack_in_reg[ib];
endcase
if (reg_addr[ib] != 5'b00000)
crc_ck[ib] <= 0;
if (reg_addr_tmp == 5'b00100)
cmd_reg_new_flag[ib] <= 1;
else
cmd_reg_new_flag[ib] <= 0;
if (crc_en[ib] == 1) begin
if (reg_addr[ib] == 5'h04 && pack_in_reg_tmp[4:0] == 5'b00111)
crc_curr[ib] = 32'b0;
else begin
if ( reg_addr[ib] != 5'h0f && reg_addr[ib] != 5'h12 && reg_addr[ib] != 5'h14
&& reg_addr[ib] != 5'h15 && reg_addr[ib] != 5'h16 && reg_addr[ib] != 5'h00) begin
crc_input = {reg_addr[ib], pack_in_reg_tmp};
crc_curr_tmp = crc_curr[ib];
crc_new = bcc_next(crc_curr_tmp, crc_input);
crc_curr[ib] <= crc_new;
end
end
end
if (conti_data_cnt[ib] <= 1) begin
conti_data_cnt[ib] <= 0;
end
else
conti_data_cnt[ib] <= conti_data_cnt[ib] - 1;
end
else if (conti_data_flag[ib] == 0 ) begin
if ( downcont_cnt >= 1) begin
if (crc_en[ib] == 1) begin
crc_input[36:0] = {5'b00010, pack_in_reg[ib]};
crc_new = bcc_next(crc_curr[ib], crc_input);
crc_curr[ib] <= crc_new;
end
if (ib == 0) begin
if (farn <= 80)
farn <= farn + 1;
else begin
far_addr <= far_addr + 1;
farn <= 0;
end
if (frame_data_wen == 1 && icap_init_done == 0) begin
rbcrc_input[36:0] = {5'b00011, pack_in_reg[ib]};
rbcrc_new[31:0] = bcc_next(rbcrc_curr[ib], rbcrc_input);
rbcrc_curr[ib] <= rbcrc_new;
$fwriteh(frame_data_fd, far_addr);
$fwriteh(frame_data_fd, "\t");
$fwriteh(frame_data_fd, pack_in_reg[ib]);
$fwriteh(frame_data_fd, "\t");
$fwriteh(frame_data_fd, rbcrc_new);
$fwriteh(frame_data_fd, "\n");
end
end
end
if (pack_in_reg_tmp[31:29] == 3'b010 ) begin
bout_cnt_tmp = bout_cnt[ib];
if (reg_addr[ib] == 5'b00010 && downcont_cnt == 0 ) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
downcont_cnt <= pack_in_reg_tmp[26:0];
far_addr <= far_reg[ib];
end
else if (reg_addr_tmp == 5'b11110 && bout_cnt_tmp == 0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
bout_flag[ib] <= 1;
bout_cnt[ib] <= pack_in_reg_tmp[26:0];
end
else if (reg_addr[ib] == 5'b01000 && csbo_cnt[ib] == 0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
csbo_flag[ib] <= 1;
csbo_cnt[ib] <= pack_in_reg_tmp[26:0];
end
end
else if (pack_in_reg_tmp[31:29] == 3'b001) begin // type 1 package
if (pack_in_reg_tmp[28:27] == 2'b01 && downcont_cnt == 0) begin
if (pack_in_reg_tmp[10:0] != 11'b0) begin
cmd_rd_flag[ib] <= 1;
cmd_wr_flag[ib] <= 0;
rd_data_cnt[ib] <= 4;
conti_data_cnt[ib] <= 0;
conti_data_flag[ib] <= 0;
rd_reg_addr[ib] <= pack_in_reg_tmp[17:13];
end
end
else if (pack_in_reg_tmp[28:27] == 2'b10 && downcont_cnt == 0) begin
if (pack_in_reg_tmp[17:13] == 5'b01000) begin // lout reg
lout_reg[ib] <= pack_in_reg_tmp;
conti_data_flag[ib] = 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
cmd_wr_flag[ib] <= 1;
conti_data_cnt[ib] <= 5'b0;
end
else if (pack_in_reg_tmp[17:13] == 5'b11110) begin // bout reg
bout_reg[ib] <= pack_in_reg_tmp;
bout_flags[ib] <= 1;
conti_data_flag[ib] = 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
cmd_wr_flag[ib] <= 1;
conti_data_cnt[ib]<= 5'b0;
end
else begin
if (pack_in_reg_tmp[10:0] != 10'b0) begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 1;
conti_data_flag[ib] <= 1;
conti_data_cnt[ib] <= pack_in_reg_tmp[10:0];
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
end
else begin
cmd_rd_flag[ib] <= 0;
cmd_wr_flag[ib] <= 1;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
reg_addr[ib] <= pack_in_reg_tmp[17:13];
reg_addr_tmp <= pack_in_reg_tmp[17:13];
end
end
end
else begin
cmd_wr_flag[ib] <= 0;
conti_data_flag[ib] <= 0;
conti_data_cnt[ib] <= 0;
end
end
end // if (conti_data_flag == 0 )
if (csbo_cnt[ib] != 0 ) begin
if (csbo_flag[ib] == 1)
csbo_cnt[ib] <= csbo_cnt[ib] - 1;
end
else
csbo_flag[ib] <= 0;
if (bout_cnt[0] != 0 && bout_flag[0] == 1) begin
if (bout_cnt[0] == 1) begin
bout_cnt[0] <= 0;
bout_flag[0] <= 0;
end
else
bout_cnt[0] <= bout_cnt[0] - 1;
end
if (bout_cnt[1] != 0 && bout_flag[1] == 1) begin
if (bout_cnt[1] == 1) begin
bout_cnt[1] <= 0;
bout_flag[1] <= 0;
end
else
bout_cnt[1] <= bout_cnt[1] - 1;
end
if (bout_cnt[2] != 0 && bout_flag[2] == 1) begin
bout_cnt[2] <= bout_cnt[2] - 1;
if (bout_cnt[2] == 1) begin
bout_cnt[2] <= 0;
bout_flag[2] <= 0;
end
else
bout_cnt[2] <= bout_cnt[2] - 1;
end
if (bout_cnt[3] != 0 && bout_flag[3] == 1 ) begin
if (bout_cnt[3] == 1) begin
bout_cnt[3] <= 0;
bout_flag[3] <= 0;
end
else
bout_cnt[3] <= bout_cnt[3] - 1;
end
if (conti_data_cnt[ib] == 5'b00001 )
conti_data_flag[ib] <= 0;
if (crc_ck[ib] == 1 || icap_init_done == 1)
crc_ck[ib] <= 0;
end
if (rw_en[ib] == 1 && csi_b_ins == 0) begin
if (rd_data_cnt[ib] == 1 && rd_flag[ib] == 1)
rd_data_cnt[ib] <= 0;
else if (rd_data_cnt[ib] == 0 && rd_flag[ib] == 1) begin
cmd_rd_flag[ib] <= 0;
end
else if (cmd_rd_flag[ib] ==1 && rd_flag[ib] == 1)
rd_data_cnt[ib] <= rd_data_cnt[ib] - 1;
if (downcont_cnt >= 1 && conti_data_flag[ib] == 0 && new_data_in_flag[ib] == 1 && wr_flag[ib] == 1)
downcont_cnt <= downcont_cnt - 1;
end
if (cmd_reg_new_flag[ib] == 1 )
cmd_reg_new_flag[ib] <= 0;
end
always @(bout_flag)
if (bout_flag[3] == 1) begin
ib = 3;
ib_skp = 1;
end
else if (bout_flag[2] == 1) begin
ib = 3;
ib_skp = 0;
end
else if (bout_flag[1] == 1) begin
ib = 2;
ib_skp = 0;
end
else if (bout_flag[0] == 1) begin
ib = 1;
ib_skp = 0;
end
else begin
ib = 0;
ib_skp = 0;
end
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
outbus <= 32'b0;
end
else begin
if (cmd_rd_flag[ib] == 1 && rdwr_b_in == 1 && csi_b_in == 0) begin
case (rd_reg_addr[ib])
5'b00000 : if (buswidth[ib] == 2'b01)
rdbk_byte(crc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(crc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(crc_reg[ib], rd_data_cnt[ib]);
5'b00001 : if (buswidth[ib] == 2'b01)
rdbk_byte(far_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(far_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(far_reg[ib], rd_data_cnt[ib]);
5'b00011 : if (buswidth[ib] == 2'b01)
rdbk_byte(fdro_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(fdro_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(fdro_reg[ib], rd_data_cnt[ib]);
5'b00100 : if (buswidth[ib] == 2'b01)
rdbk_byte(cmd_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cmd_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cmd_reg[ib], rd_data_cnt[ib]);
5'b00101 : if (buswidth[ib] == 2'b01)
rdbk_byte(ctl0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(ctl0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(ctl0_reg[ib], rd_data_cnt[ib]);
5'b00110 : if (buswidth[ib] == 2'b01)
rdbk_byte(mask_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(mask_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(mask_reg[ib], rd_data_cnt[ib]);
5'b00111 : if (buswidth[ib] == 2'b01)
rdbk_byte(stat_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(stat_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(stat_reg[ib], rd_data_cnt[ib]);
5'b01001 : if (buswidth[ib] == 2'b01)
rdbk_byte(cor0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cor0_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cor0_reg[ib], rd_data_cnt[ib]);
5'b01100 : if (buswidth[ib] == 2'b01)
rdbk_byte(DEVICE_ID, rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(DEVICE_ID, rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(DEVICE_ID, rd_data_cnt[ib]);
5'b01101 : if (buswidth[ib] == 2'b01)
rdbk_byte(axss_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(axss_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(axss_reg[ib], rd_data_cnt[ib]);
5'b01110 : if (buswidth[ib] == 2'b01)
rdbk_byte(cor1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(cor1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(cor1_reg[ib], rd_data_cnt[ib]);
5'b10000 : if (buswidth[ib] == 2'b01)
rdbk_byte(wbstar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(wbstar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(wbstar_reg[ib], rd_data_cnt[ib]);
5'b10001 : if (buswidth[ib] == 2'b01)
rdbk_byte(timer_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(timer_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(timer_reg[ib], rd_data_cnt[ib]);
5'b10010 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_hw_reg[ib], rd_data_cnt[ib]);
5'b10011 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_sw_reg[ib], rd_data_cnt[ib]);
5'b10100 : if (buswidth[ib] == 2'b01)
rdbk_byte(rbcrc_live_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(rbcrc_live_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(rbcrc_live_reg[ib], rd_data_cnt[ib]);
5'b10101 : if (buswidth[ib] == 2'b01)
rdbk_byte(efar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(efar_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(efar_reg[ib], rd_data_cnt[ib]);
5'b10110 : if (buswidth[ib] == 2'b01)
rdbk_byte(bootsts_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(bootsts_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(bootsts_reg[ib], rd_data_cnt[ib]);
5'b11000 : if (buswidth[ib] == 2'b01)
rdbk_byte(ctl1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(ctl1_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(ctl1_reg[ib], rd_data_cnt[ib]);
5'b11001 : if (buswidth[ib] == 2'b01)
rdbk_byte(memrd_param_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(memrd_param_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(memrd_param_reg[ib], rd_data_cnt[ib]);
5'b11010 : if (buswidth[ib] == 2'b01)
rdbk_byte( dwc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd( dwc_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(dwc_reg[ib], rd_data_cnt[ib]);
5'b11011 : if (buswidth[ib] == 2'b01)
rdbk_byte(trim_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(trim_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(trim_reg[ib], rd_data_cnt[ib]);
5'b11111 : if (buswidth[ib] == 2'b01)
rdbk_byte(bspi_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b10)
rdbk_wd(bspi_reg[ib], rd_data_cnt[ib]);
else if (buswidth[ib] == 2'b11)
rdbk_2wd(bspi_reg[ib], rd_data_cnt[ib]);
endcase
if (ib != 0) begin
if (rd_data_cnt[ib] == 1)
rd_desynch_tmp <= 1;
end
end
else begin
outbus <= 32'b0;
rd_desynch <= rd_desynch_tmp;
rd_desynch_tmp <= 0;
end
end
assign crc_rst[0] = crc_reset[0] | ~rst_intl;
assign crc_rst[1] = crc_reset[1] | ~rst_intl;
assign crc_rst[2] = crc_reset[2] | ~rst_intl;
assign crc_rst[3] = crc_reset[3] | ~rst_intl;
assign crc_curr_cktmp = crc_curr[0];
assign crc_reg_cktmp = crc_reg[0];
always @(posedge cclk_in or posedge crc_rst[0] )
if (crc_rst[0] == 1) begin
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 1;
end
else
if (crc_ck[0] == 1 && crc_ck_en[0] == 1 ) begin
if (crc_curr[0] != crc_reg[0])
crc_err_flag[0] <= 1;
else
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 0;
end
else begin
crc_err_flag[0] <= 0;
crc_ck_en[0] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[1] )
if (crc_rst[1] == 1) begin
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 1;
end
else
if (crc_ck[1] == 1 && crc_ck_en[1] == 1 ) begin
if (crc_curr[1] != crc_reg[1])
crc_err_flag[1] <= 1;
else
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 0;
end
else begin
crc_err_flag[1] <= 0;
crc_ck_en[1] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[2] )
if (crc_rst[2] == 1) begin
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 1;
end
else
if (crc_ck[2] == 1 && crc_ck_en[2] == 1) begin
if (crc_curr[2] != crc_reg[2])
crc_err_flag[2] <= 1;
else
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 0;
end
else begin
crc_err_flag[2] <= 0;
crc_ck_en[2] <= 1;
end
always @(posedge cclk_in or posedge crc_rst[3] )
if (crc_rst[3] == 1) begin
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 1;
end
else
if (crc_ck[3] == 1 && crc_ck_en[3] == 1) begin
if (crc_curr[3] != crc_reg[3])
crc_err_flag[3] <= 1;
else
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 0;
end
else begin
crc_err_flag[3] <= 0;
crc_ck_en[3] <= 1;
end
always @(posedge crc_err_flag[0] or negedge rst_intl or posedge bus_sync_flag[0])
if (rst_intl == 0)
crc_err_flag_reg[0] <= 0;
else if (crc_err_flag[0] == 1)
crc_err_flag_reg[0] <= 1;
else
crc_err_flag_reg[0] <= 0;
always @(posedge crc_err_flag[1] or negedge rst_intl or posedge bus_sync_flag[1])
if (rst_intl == 0)
crc_err_flag_reg[1] <= 0;
else if (crc_err_flag[1] == 1)
crc_err_flag_reg[1] <= 1;
else
crc_err_flag_reg[1] <= 0;
always @(posedge crc_err_flag[2] or negedge rst_intl or posedge bus_sync_flag[2])
if (rst_intl == 0)
crc_err_flag_reg[2] <= 0;
else if (crc_err_flag[2] == 1)
crc_err_flag_reg[2] <= 1;
else
crc_err_flag_reg[2] <= 0;
always @(posedge crc_err_flag[3] or negedge rst_intl or posedge bus_sync_flag[3])
if (rst_intl == 0)
crc_err_flag_reg[3] <= 0;
else if (crc_err_flag[3] == 1)
crc_err_flag_reg[3] <= 1;
else
crc_err_flag_reg[3] <= 0;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
startup_set <= 4'b0;
crc_reset <= 4'b0;
gsr_cmd_out <= 4'b0;
shutdown_set <= 4'b0;
desynch_set <= 4'b0;
ghigh_b <= 4'b0;
end
else
for (ci = 0; ci <=3; ci = ci+1) begin
if (cmd_reg_new_flag[ci] == 1) begin
if (cmd_reg[ci] == 5'b00011)
ghigh_b[ci] <= 1;
else if (cmd_reg[ci] == 5'b01000)
ghigh_b[ci] <= 0;
if (cmd_reg[ci] == 5'b00101)
startup_set[ci] <= 1;
else
startup_set[ci] <= 0;
if (cmd_reg[ci] == 5'b00111)
crc_reset[ci] <= 1;
else
crc_reset[ci] <= 0;
if (cmd_reg[ci] == 5'b01010)
gsr_cmd_out[ci] <= 1;
else
gsr_cmd_out[ci] <= 0;
if (cmd_reg[ci] == 5'b01011)
shutdown_set[ci] <= 1;
else
shutdown_set[ci] <= 0;
if (cmd_reg[ci] == 5'b01101)
desynch_set[ci] <= 1;
else
desynch_set[ci] <= 0;
if (cmd_reg[ci] == 5'b01111) begin
iprog_b[ci] <= 0;
i_init_b_cmd[ci] <= 0;
iprog_b[ci] <= #cfg_Tprog 1;
i_init_b_cmd[ci] <=#(cfg_Tprog + cfg_Tpl) 1;
end
end
else begin
startup_set[ci] <= 0;
crc_reset[ci] <= 0;
gsr_cmd_out[ci] <= 0;
shutdown_set[ci] <= 0;
desynch_set[ci] <= 0;
end
end
always @(posedge startup_set[0] or posedge desynch_set[0] or posedge rw_en[0] )
if (rw_en[0] == 1 || desynch_set[0] == 1)
begin
if (startup_set_pulse0 == 2'b00 && startup_set[0] ==1) begin
if (icap_on == 0)
startup_set_pulse0 <= 2'b01;
else begin
startup_set_pulse0 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse0 <= 2'b00;
end
end
else if (desynch_set[0] == 1 && startup_set_pulse0 == 2'b01) begin
startup_set_pulse0 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse0 <= 2'b00;
end
end
always @(posedge startup_set[1] or posedge desynch_set[1] or posedge rw_en[1] )
if (rw_en[1] == 1 || desynch_set[1] == 1)
begin
if (startup_set_pulse1 == 2'b00 && startup_set[1] ==1) begin
if (icap_on == 0)
startup_set_pulse1 <= 2'b01;
else begin
startup_set_pulse1 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse1 <= 2'b00;
end
end
else if (desynch_set[1] == 1 && startup_set_pulse1 == 2'b01) begin
startup_set_pulse1 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse1 <= 2'b00;
end
end
always @(posedge startup_set[2] or posedge desynch_set[2] or posedge rw_en[2])
if (rw_en[2] == 1 || desynch_set[2] == 1)
begin
if (startup_set_pulse2 == 2'b00 && startup_set[2] ==1) begin
if (icap_on == 0)
startup_set_pulse2 <= 2'b01;
else begin
startup_set_pulse2 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse2 <= 2'b00;
end
end
else if (desynch_set[2] == 1 && startup_set_pulse2 == 2'b01) begin
startup_set_pulse2 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse2 <= 2'b00;
end
end
always @(posedge startup_set[3] or posedge desynch_set[3] or posedge rw_en[3])
if (rw_en[3] == 1 || desynch_set[3] == 1)
begin
if (startup_set_pulse3 == 2'b00 && startup_set[3] ==1) begin
if (icap_on == 0)
startup_set_pulse3 <= 2'b01;
else begin
startup_set_pulse3 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse3 <= 2'b00;
end
end
else if (desynch_set[3] == 1 && startup_set_pulse3 == 2'b01) begin
startup_set_pulse3 <= 2'b11;
@(posedge cclk_in )
startup_set_pulse3 <= 2'b00;
end
end
always @(posedge gsr_cmd_out[0] or negedge rw_en[0])
if (rw_en[0] == 0)
gsr_cmd_out_pulse[0] <= 0;
else
begin
gsr_cmd_out_pulse[0] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[0] <= 0;
end
always @(posedge gsr_cmd_out[1] or negedge rw_en[1])
if (rw_en[1] == 0)
gsr_cmd_out_pulse[1] <= 0;
else
begin
gsr_cmd_out_pulse[1] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[1] <= 0;
end
always @(posedge gsr_cmd_out[2] or negedge rw_en[2])
if (rw_en[2] == 0)
gsr_cmd_out_pulse[2] <= 0;
else
begin
gsr_cmd_out_pulse[2] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[2] <= 0;
end
always @(posedge gsr_cmd_out[3] or negedge rw_en[3])
if (rw_en[3] == 0)
gsr_cmd_out_pulse[3] <= 0;
else
begin
gsr_cmd_out_pulse[3] <= 1;
@(posedge cclk_in );
@(posedge cclk_in )
gsr_cmd_out_pulse[3] <= 0;
end
reg [31:0] ctl0_reg_tmp0, ctl0_reg_tmp1, ctl0_reg_tmp2, ctl0_reg_tmp3;
always @(ctl0_reg[0]) begin
ctl0_reg_tmp0 = ctl0_reg[0];
if (ctl0_reg_tmp0[9] == 1)
abort_dis[0] = 1;
else
abort_dis[0] = 0;
if (ctl0_reg_tmp0[3] == 1)
persist_en[0] = 1;
else
persist_en[0] = 0;
if (ctl0_reg_tmp0[0] == 1)
gts_usr_b[0] = 1;
else
gts_usr_b[0] = 0;
end
always @(ctl0_reg[1]) begin
ctl0_reg_tmp1 = ctl0_reg[1];
if (ctl0_reg_tmp1[9] == 1)
abort_dis[1] = 1;
else
abort_dis[1] = 0;
if (ctl0_reg_tmp1[3] == 1)
persist_en[1] = 1;
else
persist_en[1] = 0;
if (ctl0_reg_tmp1[0] == 1)
gts_usr_b[1] = 1;
else
gts_usr_b[1] = 0;
end
always @(ctl0_reg[2]) begin
ctl0_reg_tmp2 = ctl0_reg[2];
if (ctl0_reg_tmp2[9] == 1)
abort_dis[2] = 1;
else
abort_dis[2] = 0;
if (ctl0_reg_tmp2[3] == 1)
persist_en[2] = 1;
else
persist_en[2] = 0;
if (ctl0_reg_tmp0[2] == 1)
gts_usr_b[2] = 1;
else
gts_usr_b[2] = 0;
end
always @(ctl0_reg[3]) begin
ctl0_reg_tmp3 = ctl0_reg[3];
if (ctl0_reg_tmp3[9] == 1)
abort_dis[3] = 1;
else
abort_dis[3] = 0;
if (ctl0_reg_tmp3[3] == 1)
persist_en[3] = 1;
else
persist_en[3] = 0;
if (ctl0_reg_tmp3[0] == 1)
gts_usr_b[3] = 1;
else
gts_usr_b[3] = 0;
end
always @(cor0_reg[0])
begin
cor0_reg_tmp0 = cor0_reg[0];
done_cycle_reg0 = cor0_reg_tmp0[14:12];
lock_cycle_reg0 = cor0_reg_tmp0[8:6];
gts_cycle_reg0 = cor0_reg_tmp0[5:3];
gwe_cycle_reg0 = cor0_reg_tmp0[2:0];
if (cor0_reg_tmp0[24] == 1'b1)
done_pin_drv[0] = 1;
else
done_pin_drv[0] = 0;
if (cor0_reg_tmp0[28] == 1'b1)
crc_bypass[0] = 1;
else
crc_bypass[0] = 0;
end
always @(cor0_reg[1])
begin
cor0_reg_tmp1 = cor0_reg[1];
done_cycle_reg1 = cor0_reg_tmp1[14:12];
lock_cycle_reg1 = cor0_reg_tmp1[8:6];
gts_cycle_reg1 = cor0_reg_tmp1[5:3];
gwe_cycle_reg1 = cor0_reg_tmp1[2:0];
if (cor0_reg_tmp1[24] == 1'b1)
done_pin_drv[1] = 1;
else
done_pin_drv[1] = 0;
if (cor0_reg_tmp1[28] == 1'b1)
crc_bypass[1] = 1;
else
crc_bypass[1] = 0;
end
always @(cor0_reg[2])
begin
cor0_reg_tmp2 = cor0_reg[2];
done_cycle_reg2 = cor0_reg_tmp2[14:12];
lock_cycle_reg2 = cor0_reg_tmp2[8:6];
gts_cycle_reg2 = cor0_reg_tmp2[5:3];
gwe_cycle_reg2 = cor0_reg_tmp2[2:0];
if (cor0_reg_tmp2[24] == 1'b1)
done_pin_drv[2] = 1;
else
done_pin_drv[2] = 0;
if (cor0_reg_tmp2[28] == 1'b1)
crc_bypass[2] = 1;
else
crc_bypass[2] = 0;
end
always @(cor0_reg[3])
begin
cor0_reg_tmp3 = cor0_reg[3];
done_cycle_reg3 = cor0_reg_tmp3[14:12];
lock_cycle_reg3 = cor0_reg_tmp3[8:6];
gts_cycle_reg3 = cor0_reg_tmp3[5:3];
gwe_cycle_reg3 = cor0_reg_tmp3[2:0];
if (cor0_reg_tmp3[24] == 1'b1)
done_pin_drv[3] = 1;
else
done_pin_drv[3] = 0;
if (cor0_reg_tmp3[28] == 1'b1)
crc_bypass[3] = 1;
else
crc_bypass[3] = 0;
end
always @(cor1_reg[0]) begin
cor1_reg_tmp0 = cor1_reg[0];
rbcrc_no_pin[0] = cor1_reg_tmp0[8];
end
always @(cor1_reg[1]) begin
cor1_reg_tmp1 = cor1_reg[1];
rbcrc_no_pin[1] = cor1_reg_tmp1[8];
end
always @(cor1_reg[2]) begin
cor1_reg_tmp2 = cor1_reg[2];
rbcrc_no_pin[2] = cor1_reg_tmp2[8];
end
always @(cor1_reg[3]) begin
cor1_reg_tmp3 = cor1_reg[3];
rbcrc_no_pin[3] = cor1_reg_tmp3[8];
end
assign stat_reg_tmp0[31:27] = 5'b00000;
assign stat_reg_tmp1[31:27] = 5'b00000;
assign stat_reg_tmp2[31:27] = 5'b00000;
assign stat_reg_tmp3[31:27] = 5'b00000;
assign stat_reg_tmp0[24:21] = 4'bxxx0;
assign stat_reg_tmp1[24:21] = 4'bxxx0;
assign stat_reg_tmp2[24:21] = 4'bxxx0;
assign stat_reg_tmp3[24:21] = 4'bxxx0;
assign stat_reg_tmp0[17:16] = 2'b0;
assign stat_reg_tmp1[17:16] = 2'b0;
assign stat_reg_tmp2[17:16] = 2'b0;
assign stat_reg_tmp3[17:16] = 2'b0;
assign stat_reg_tmp0[14] = DONE;
assign stat_reg_tmp1[14] = DONE;
assign stat_reg_tmp2[14] = DONE;
assign stat_reg_tmp3[14] = DONE;
assign stat_reg_tmp0[13] = (done_o[0] !== 0) ? 1 : 0;
assign stat_reg_tmp1[13] = (done_o[1] !== 0) ? 1 : 0;
assign stat_reg_tmp2[13] = (done_o[2] !== 0) ? 1 : 0;
assign stat_reg_tmp3[13] = (done_o[3] !== 0) ? 1 : 0;
assign stat_reg_tmp0[12] = INITB;
assign stat_reg_tmp1[12] = INITB;
assign stat_reg_tmp2[12] = INITB;
assign stat_reg_tmp3[12] = INITB;
assign stat_reg_tmp0[11] = mode_sample_flag;
assign stat_reg_tmp1[11] = mode_sample_flag;
assign stat_reg_tmp2[11] = mode_sample_flag;
assign stat_reg_tmp3[11] = mode_sample_flag;
assign stat_reg_tmp0[10:8] = mode_pin_in;
assign stat_reg_tmp1[10:8] = mode_pin_in;
assign stat_reg_tmp2[10:8] = mode_pin_in;
assign stat_reg_tmp3[10:8] = mode_pin_in;
assign stat_reg_tmp0[3] = 1'b1;
assign stat_reg_tmp1[3] = 1'b1;
assign stat_reg_tmp2[3] = 1'b1;
assign stat_reg_tmp3[3] = 1'b1;
assign stat_reg_tmp0[2] = pll_locked;
assign stat_reg_tmp1[2] = pll_locked;
assign stat_reg_tmp2[2] = pll_locked;
assign stat_reg_tmp3[2] = pll_locked;
assign stat_reg_tmp0[1] = 1'b0;
assign stat_reg_tmp1[1] = 1'b0;
assign stat_reg_tmp2[1] = 1'b0;
assign stat_reg_tmp3[1] = 1'b0;
assign stat_reg_tmp0[26:25] = buswidth[0];
assign stat_reg_tmp0[20:18] = st_state0;
assign stat_reg_tmp0[15] = id_error_flag[0];
assign stat_reg_tmp0[7] = ghigh_b[0];
assign stat_reg_tmp0[6] = gwe_out[0];
assign stat_reg_tmp0[5] = gts_cfg_b[0];
assign stat_reg_tmp0[4] = eos_startup[0];
assign stat_reg_tmp0[0] = crc_err_flag_reg[0];
assign stat_reg_tmp1[26:25] = buswidth[1];
assign stat_reg_tmp1[20:18] = st_state1;
assign stat_reg_tmp1[15] = id_error_flag[1];
assign stat_reg_tmp1[7] = ghigh_b[1];
assign stat_reg_tmp1[6] = gwe_out[1];
assign stat_reg_tmp1[5] = gts_cfg_b[1];
assign stat_reg_tmp1[4] = eos_startup[1];
assign stat_reg_tmp1[0] = crc_err_flag_reg[1];
assign stat_reg_tmp2[26:25] = buswidth[2];
assign stat_reg_tmp2[20:18] = st_state2;
assign stat_reg_tmp2[15] = id_error_flag[2];
assign stat_reg_tmp2[7] = ghigh_b[2];
assign stat_reg_tmp2[6] = gwe_out[2];
assign stat_reg_tmp2[5] = gts_cfg_b[2];
assign stat_reg_tmp2[4] = eos_startup[2];
assign stat_reg_tmp2[0] = crc_err_flag_reg[2];
assign stat_reg_tmp3[26:25] = buswidth[3];
assign stat_reg_tmp3[20:18] = st_state3;
assign stat_reg_tmp3[15] = id_error_flag[3];
assign stat_reg_tmp3[7] = ghigh_b[3];
assign stat_reg_tmp3[6] = gwe_out[3];
assign stat_reg_tmp3[5] = gts_cfg_b[3];
assign stat_reg_tmp3[4] = eos_startup[3];
assign stat_reg_tmp3[0] = crc_err_flag_reg[3];
assign stat_reg[0] = stat_reg_tmp0;
assign stat_reg[1] = stat_reg_tmp1;
assign stat_reg[2] = stat_reg_tmp2;
assign stat_reg[3] = stat_reg_tmp3;
always @(posedge cclk_in or negedge rst_intl)
if (rst_intl == 0) begin
st_state0 <= STARTUP_PH0;
st_state1 <= STARTUP_PH0;
st_state2 <= STARTUP_PH0;
st_state3 <= STARTUP_PH0;
startup_begin_flag0 <= 0;
startup_begin_flag1 <= 0;
startup_begin_flag2 <= 0;
startup_begin_flag3 <= 0;
startup_end_flag0 <= 0;
startup_end_flag1 <= 0;
startup_end_flag2 <= 0;
startup_end_flag3 <= 0;
end
else begin
st_state0i = st_state0;
cur_st_tsk(startup_begin_flag0, startup_end_flag0, st_state0,
st_state0i, nx_st_state0,lock_cycle_reg0);
st_state1i = st_state1;
cur_st_tsk(startup_begin_flag1, startup_end_flag1, st_state1,
st_state1i, nx_st_state1,lock_cycle_reg1);
st_state2i = st_state2;
cur_st_tsk(startup_begin_flag2, startup_end_flag2, st_state2,
st_state2i, nx_st_state2,lock_cycle_reg2);
st_state3i = st_state3;
cur_st_tsk(startup_begin_flag3, startup_end_flag3, st_state3,
st_state3i, nx_st_state3,lock_cycle_reg3);
end
task cur_st_tsk;
output stup_bflag;
output stup_eflag;
output [2:0] cst_o;
input [2:0] cst_in;
input [2:0] nst_in;
input [2:0] lock_cycle_in;
begin
if (nst_in == STARTUP_PH1) begin
stup_bflag = 1;
stup_eflag = 0;
end
else if (cst_in == STARTUP_PH7) begin
stup_eflag = 1;
stup_bflag = 0;
end
if ((lock_cycle_in == 3'b111) || (pll_locked == 1) || (pll_locked == 0 && cst_in != lock_cycle_in)) begin
cst_o = nst_in;
end
else
cst_o = cst_in;
end
endtask
always @(st_state0 or startup_set_pulse0 or DONE ) begin
nx_st_tsk(nx_st_state0,st_state0, startup_set_pulse0, done_cycle_reg0);
end
always @(st_state1 or startup_set_pulse1 or DONE ) begin
nx_st_tsk(nx_st_state1,st_state1, startup_set_pulse1, done_cycle_reg1);
end
always @(st_state2 or startup_set_pulse2 or DONE ) begin
nx_st_tsk(nx_st_state2,st_state2, startup_set_pulse2, done_cycle_reg2);
end
always @(st_state3 or startup_set_pulse3 or DONE ) begin
nx_st_tsk(nx_st_state3,st_state3, startup_set_pulse3, done_cycle_reg3);
end
task nx_st_tsk;
output [2:0] nx_st;
input [2:0] cur_st;
input [1:0] stup_pulse;
input [2:0] done_cycle_in;
begin
if (((cur_st == done_cycle_in) && (DONE !== 0)) || (cur_st != done_cycle_in))
case (cur_st)
STARTUP_PH0 : if (stup_pulse == 2'b11 )
nx_st = STARTUP_PH1;
else
nx_st = STARTUP_PH0;
STARTUP_PH1 : nx_st = STARTUP_PH2;
STARTUP_PH2 : nx_st = STARTUP_PH3;
STARTUP_PH3 : nx_st = STARTUP_PH4;
STARTUP_PH4 : nx_st = STARTUP_PH5;
STARTUP_PH5 : nx_st = STARTUP_PH6;
STARTUP_PH6 : nx_st = STARTUP_PH7;
STARTUP_PH7 : nx_st = STARTUP_PH0;
endcase
end
endtask
always @(posedge cclk_in or negedge rst_intl )
if (rst_intl == 0) begin
gwe_out <= 4'b0;
gts_out <= 4'b1111;
eos_startup <= 4'b0;
gsr_st_out <= 4'b1111;
done_o <= 4'b0;
end
else begin
if (nx_st_state0 == done_cycle_reg0 || st_state0 == done_cycle_reg0) begin
if (DONE !== 0 || done_pin_drv[0] === 1)
done_o[0] <= 1'b1;
else
done_o[0] <= 1'bz;
end
if (nx_st_state1 == done_cycle_reg1 || st_state1 == done_cycle_reg1) begin
if (DONE !== 0 || done_pin_drv[1] == 1)
done_o[1] <= 1'b1;
else
done_o[1] <= 1'bz;
end
if (nx_st_state2 == done_cycle_reg2 || st_state2 == done_cycle_reg2) begin
if (DONE !== 0 || done_pin_drv[2] == 1)
done_o[2] <= 1'b1;
else
done_o[2] <= 1'bz;
end
if (nx_st_state3 == done_cycle_reg3 || st_state3 == done_cycle_reg3) begin
if (DONE !== 0 || done_pin_drv[3] == 1)
done_o[3] <= 1'b1;
else
done_o[3] <= 1'bz;
end
if (st_state0 == gwe_cycle_reg0)
gwe_out[0] <= 1;
if (st_state1 == gwe_cycle_reg1)
gwe_out[1] <= 1;
if (st_state2 == gwe_cycle_reg2)
gwe_out[2] <= 1;
if (st_state3 == gwe_cycle_reg3)
gwe_out[3] <= 1;
if (st_state0 == gts_cycle_reg0 )
gts_out[0] <= 0;
if (st_state1 == gts_cycle_reg1 )
gts_out[1] <= 0;
if (st_state2 == gts_cycle_reg2 )
gts_out[2] <= 0;
if (st_state3 == gts_cycle_reg3 )
gts_out[3] <= 0;
if (st_state0 == STARTUP_PH6 )
gsr_st_out[0] <= 0;
if (st_state1 == STARTUP_PH6 )
gsr_st_out[1] <= 0;
if (st_state2 == STARTUP_PH6 )
gsr_st_out[2] <= 0;
if (st_state3 == STARTUP_PH6 )
gsr_st_out[3] <= 0;
if (st_state0 == STARTUP_PH7 )
eos_startup[0] <= 1;
if (st_state1 == STARTUP_PH7 )
eos_startup[1] <= 1;
if (st_state2 == STARTUP_PH7 )
eos_startup[2] <= 1;
if (st_state3 == STARTUP_PH7 )
eos_startup[3] <= 1;
end
assign gsr_out[0] = gsr_st_out[0] | gsr_cmd_out[0];
assign gsr_out[1] = gsr_st_out[1] | gsr_cmd_out[1];
assign gsr_out[2] = gsr_st_out[2] | gsr_cmd_out[2];
assign gsr_out[3] = gsr_st_out[3] | gsr_cmd_out[3];
assign abort_dis_bi = abort_dis[ib];
always @(posedge cclk_in or negedge rst_intl or
posedge abort_flag_rst or posedge csi_b_in)
if (rst_intl == 0 || abort_flag_rst == 1 || csi_b_in == 1) begin
abort_flag[ib] <= 0;
checka_en <= 0;
rdwr_b_in1 <= rdwr_b_in;
end
else begin
if ( abort_dis_bi == 0 && csi_b_in == 0) begin
if ((rdwr_b_in1 != rdwr_b_in) && checka_en != 0) begin
abort_flag[ib] <= 1;
if (icap_on == 0)
$display("Warning: [Unisim %s-10]Warning : RDWRB changes when CSB low, which causes Configuration abort at time %t. Instance %m", MODULE_NAME, $time);
end
end
else
abort_flag[ib] <= 0;
rdwr_b_in1 <= rdwr_b_in;
checka_en <= 1;
end
always @(posedge abort_flag[ib])
begin
abort_out_en <= 1;
abort_status <= {cfgerr_b_flag[ib], bus_sync_flag[ib], 1'b0, 1'b1, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b1, 1'b0, 1'b0, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b0, 4'b1111};
@(posedge cclk_in)
abort_status <= {cfgerr_b_flag[ib], 1'b0, 1'b0, 1'b1, 4'b1111};
@(posedge cclk_in) begin
abort_out_en <= 0;
abort_flag_rst <= 1;
end
@(posedge cclk_in)
abort_flag_rst <= 0;
end
function [31:0] bcc_next;
input [31:0] bcc;
input [36:0] in;
reg [31:0] x;
reg [36:0] m;
begin
m = in;
x = in[31:0] ^ bcc;
bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0];
bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0];
bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3];
bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2];
bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1];
bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0];
bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1];
bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0];
bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2];
bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3];
bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2];
bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0];
bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0];
bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0];
bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2];
bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1];
bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1];
bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2];
bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0];
bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2];
bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0];
bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1];
bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3];
bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0];
bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3];
bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2];
bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1];
bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0];
end
endfunction
function [7:0] bit_revers8;
input [7:0] din8;
begin
bit_revers8[0] = din8[7];
bit_revers8[1] = din8[6];
bit_revers8[2] = din8[5];
bit_revers8[3] = din8[4];
bit_revers8[4] = din8[3];
bit_revers8[5] = din8[2];
bit_revers8[6] = din8[1];
bit_revers8[7] = din8[0];
end
endfunction
task rdbk_byte;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
outbus[31:8] <= 24'b0;
if (rd_dcnt==1)
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
else if (rd_dcnt==2)
outbus[7:0] <= bit_revers8(rdbk_reg[15:8]);
else if (rd_dcnt==3)
outbus[7:0] <= bit_revers8(rdbk_reg[23:16]);
else if (rd_dcnt==4)
outbus[7:0] <= bit_revers8(rdbk_reg[31:24]);
end
endtask
task rdbk_wd;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
outbus[31:16] <= 16'b0;
if (rd_dcnt==1)
outbus[15:0] <= 16'b0;
else if (rd_dcnt==2)
outbus[15:0] <= 16'b0;
else if (rd_dcnt==3) begin
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
outbus[15:8] <= bit_revers8(rdbk_reg[15:8]);
end
else if (rd_dcnt==4) begin
outbus[7:0] <= bit_revers8(rdbk_reg[23:16]);
outbus[15:8] <= bit_revers8(rdbk_reg[31:24]);
end
end
endtask
task rdbk_2wd;
input [31:0] rdbk_reg;
input integer rd_dcnt;
begin
if (rd_dcnt==1)
outbus <= 32'b0;
else if (rd_dcnt==2)
outbus <= 32'b0;
else if (rd_dcnt==3)
outbus <= 32'b0;
else if (rd_dcnt==4) begin
outbus[7:0] <= bit_revers8(rdbk_reg[7:0]);
outbus[15:8] <= bit_revers8(rdbk_reg[15:8]);
outbus[23:16] <= bit_revers8(rdbk_reg[23:16]);
outbus[31:24] <= bit_revers8(rdbk_reg[31:24]);
end
end
endtask
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O32A_PP_SYMBOL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o32a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32A_PP_SYMBOL_V
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`include "qlf_k6n10f/cells_sim.v"
module tb();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#2 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Filter control
reg [2:0] fcnt;
reg [3:0] dcnt;
initial begin
fcnt <= 0;
dcnt <= 0;
end
// MAC cycle counter
always @(posedge clk)
if (rst) fcnt <= 0;
else begin
if (fcnt == 4)
fcnt <= 0;
else
fcnt <= fcnt + 1;
end
wire stb = (fcnt == 4);
// Data address counter
always @(posedge clk)
if (rst) dcnt <= 0;
else if (stb) dcnt <= dcnt + 1;
// Filter coeffs (S0.19)
reg signed [19:0] coeff;
always @(*) case (fcnt)
2'd0: coeff <= 20'h0000B;
2'd1: coeff <= 20'h0000E;
2'd2: coeff <= 20'h0000E;
2'd3: coeff <= 20'h0000F;
default: coeff <= 20'h00000;
endcase
// Input data (S0.17)
reg signed [17:0] data;
always @(*) case (dcnt)
'd0: data <= 18'h00400;
'd1: data <= 18'h00000;
'd2: data <= 18'h00000;
'd3: data <= 18'h00000;
'd4: data <= 18'h00000;
'd5: data <= 18'h00000;
'd6: data <= 18'h00000;
'd7: data <= 18'h00000;
'd8: data <= 18'h00800;
default data <= 18'h00000;
endcase
// UUT
wire signed [5:0] acc_fir_i = 6'h0;
wire signed [19:0] A = coeff;
wire signed [17:0] B = data;
wire signed [37:0] Z;
dsp_t1_sim # (
) uut (
.clock_i (clk),
.s_reset (rst),
.a_i ((!stb) ? A : 20'h0),
.b_i ((!stb) ? B : 18'h0),
.acc_fir_i ((!stb) ? acc_fir_i : 4'h0),
.unsigned_a_i (1'b0),
.unsigned_b_i (1'b0),
.feedback_i (stb),
.load_acc_i (1'b1),
.shift_right_i (6'd10),
.register_inputs_i (1'b0),
.output_select_i (3'h1),
.round_i (1'b1),
.saturate_enable_i (1'b1),
.subtract_i (1'b0),
.z_o (Z)
);
// Output counter
integer ocnt;
initial ocnt <= 0;
always @(posedge clk)
if (stb) ocnt <= ocnt + 1;
// Expected output data
reg signed [31:0] odata;
always @(*) case (ocnt)
'd0: odata <= 32'h000036;
'd1: odata <= 32'h000000;
'd2: odata <= 32'h000000;
'd3: odata <= 32'h000000;
'd4: odata <= 32'h000000;
'd5: odata <= 32'h000000;
'd6: odata <= 32'h000000;
'd7: odata <= 32'h000000;
'd8: odata <= 32'h00006C;
default: odata <= 32'h000000;
endcase
// Error detection
wire error = stb && (odata !== Z[31:0]);
// Error counting
integer error_count;
initial error_count <= 0;
always @(posedge clk) begin
if (error) error_count <= error_count + 1;
end
// Simulation control / data dump
initial begin
$dumpfile(`VCD_FILE);
$dumpvars(0, tb);
#150 $finish_and_return( (error_count == 0) ? 0 : -1 );
end
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream SRL-based FIFO
*/
module axis_srl_fifo #
(
parameter DATA_WIDTH = 8,
parameter DEPTH = 16
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Status
*/
output wire [$clog2(DEPTH+1)-1:0] count
);
reg [DATA_WIDTH+2-1:0] data_reg[DEPTH-1:0];
reg [$clog2(DEPTH+1)-1:0] ptr_reg = 0, ptr_next;
reg full_reg = 0, full_next;
reg empty_reg = 1, empty_next;
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_reg[ptr_reg-1];
assign input_axis_tready = ~full_reg;
assign output_axis_tvalid = ~empty_reg;
assign count = ptr_reg;
wire ptr_empty = ptr_reg == 0;
wire ptr_empty1 = ptr_reg == 1;
wire ptr_full = ptr_reg == DEPTH;
wire ptr_full1 = ptr_reg == DEPTH-1;
reg shift;
reg inc;
reg dec;
integer i;
initial begin
for (i = 0; i < DEPTH; i = i + 1) begin
data_reg[i] <= 0;
end
end
always @* begin
shift = 0;
inc = 0;
dec = 0;
ptr_next = ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
if (output_axis_tready & input_axis_tvalid & ~full_reg) begin
shift = 1;
inc = ptr_empty;
empty_next = 0;
end else if (output_axis_tready & output_axis_tvalid) begin
dec = 1;
full_next = 0;
empty_next = ptr_empty1;
end else if (input_axis_tvalid & input_axis_tready) begin
shift = 1;
inc = 1;
full_next = ptr_full1;
empty_next = 0;
end
end
always @(posedge clk) begin
if (rst) begin
ptr_reg <= 0;
end else begin
if (shift) begin
data_reg[0] <= {input_axis_tlast, input_axis_tuser, input_axis_tdata};
for (i = 0; i < DEPTH-1; i = i + 1) begin
data_reg[i+1] <= data_reg[i];
end
end
if (inc) begin
ptr_reg <= ptr_reg + 1;
end else if (dec) begin
ptr_reg <= ptr_reg - 1;
end else begin
ptr_reg <= ptr_reg;
end
full_reg <= full_next;
empty_reg <= empty_next;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_SYMBOL_V
/**
* udp_dff$NR_pp$PKG$s: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$NR_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE SD Card Controller IP Core ////
//// ////
//// sd_controller_wb.v ////
//// ////
//// This file is part of the WISHBONE SD Card ////
//// Controller IP Core project ////
//// http://opencores.org/project,sd_card_controller ////
//// ////
//// Description ////
//// Wishbone interface responsible for comunication with core ////
//// ////
//// Author(s): ////
//// - Marek Czerski, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// Based on original work by ////
//// Adam Edvardsson ([email protected]) ////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "sd_defines.h"
module sd_controller_wb(
// WISHBONE slave
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
cmd_start,
data_int_rst,
cmd_int_rst,
argument_reg,
command_reg,
response_0_reg,
response_1_reg,
response_2_reg,
response_3_reg,
software_reset_reg,
timeout_reg,
block_size_reg,
controll_setting_reg,
cmd_int_status_reg,
cmd_int_enable_reg,
clock_divider_reg,
block_count_reg,
dma_addr_reg,
data_int_status_reg,
data_int_enable_reg
);
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output reg [31:0] wb_dat_o; // WISHBONE data output
// WISHBONE error output
// WISHBONE slave
input [7:0] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output reg wb_ack_o; // WISHBONE acknowledge output
output reg cmd_start;
//Buss accessible registers
output reg [31:0] argument_reg;
output reg [`CMD_REG_SIZE-1:0] command_reg;
input wire [31:0] response_0_reg;
input wire [31:0] response_1_reg;
input wire [31:0] response_2_reg;
input wire [31:0] response_3_reg;
output reg [0:0] software_reset_reg;
output reg [15:0] timeout_reg;
output reg [`BLKSIZE_W-1:0] block_size_reg;
output reg [15:0] controll_setting_reg;
input wire [`INT_CMD_SIZE-1:0] cmd_int_status_reg;
output reg [`INT_CMD_SIZE-1:0] cmd_int_enable_reg;
output reg [7:0] clock_divider_reg;
input wire [`INT_DATA_SIZE-1:0] data_int_status_reg;
output reg [`INT_DATA_SIZE-1:0] data_int_enable_reg;
//Register Controll
output reg data_int_rst;
output reg cmd_int_rst;
output reg [`BLKCNT_W-1:0]block_count_reg;
output reg [31:0] dma_addr_reg;
parameter voltage_controll_reg = `SUPPLY_VOLTAGE_mV;
parameter capabilies_reg = 16'b0000_0000_0000_0000;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)begin
argument_reg <= 0;
command_reg <= 0;
software_reset_reg <= 0;
timeout_reg <= 0;
block_size_reg <= `RESET_BLOCK_SIZE;
controll_setting_reg <= 0;
cmd_int_enable_reg <= 0;
clock_divider_reg <= `RESET_CLK_DIV;
wb_ack_o <= 0;
cmd_start <= 0;
data_int_rst <= 0;
data_int_enable_reg <= 0;
cmd_int_rst <= 0;
block_count_reg <= 0;
dma_addr_reg <= 0;
end
else
begin
cmd_start <= 1'b0;
data_int_rst <= 0;
cmd_int_rst <= 0;
if ((wb_stb_i & wb_cyc_i) || wb_ack_o)begin
if (wb_we_i) begin
case (wb_adr_i)
`argument: begin
argument_reg <= wb_dat_i;
cmd_start <= 1'b1;
end
`command: command_reg <= wb_dat_i[`CMD_REG_SIZE-1:0];
`reset: software_reset_reg <= wb_dat_i[0];
`timeout: timeout_reg <= wb_dat_i[15:0];
`blksize: block_size_reg <= wb_dat_i[`BLKSIZE_W-1:0];
`controller: controll_setting_reg <= wb_dat_i[15:0];
`cmd_iser: cmd_int_enable_reg <= wb_dat_i[4:0];
`cmd_isr: cmd_int_rst <= 1;
`clock_d: clock_divider_reg <= wb_dat_i[7:0];
`data_isr: data_int_rst <= 1;
`data_iser: data_int_enable_reg <= wb_dat_i[`INT_DATA_SIZE-1:0];
`dst_src_addr: dma_addr_reg <= wb_dat_i;
`blkcnt: block_count_reg <= wb_dat_i[`BLKCNT_W-1:0];
endcase
end
wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
end
end
end
always @(posedge wb_clk_i or posedge wb_rst_i)begin
if (wb_rst_i == 1)
wb_dat_o <= 0;
else
if (wb_stb_i & wb_cyc_i) begin //CS
case (wb_adr_i)
`argument: wb_dat_o <= argument_reg;
`command: wb_dat_o <= command_reg;
`resp0: wb_dat_o <= response_0_reg;
`resp1: wb_dat_o <= response_1_reg;
`resp2: wb_dat_o <= response_2_reg;
`resp3: wb_dat_o <= response_3_reg;
`controller: wb_dat_o <= controll_setting_reg;
`blksize: wb_dat_o <= block_size_reg;
`voltage: wb_dat_o <= voltage_controll_reg;
`reset: wb_dat_o <= software_reset_reg;
`timeout: wb_dat_o <= timeout_reg;
`cmd_isr: wb_dat_o <= cmd_int_status_reg;
`cmd_iser: wb_dat_o <= cmd_int_enable_reg;
`clock_d: wb_dat_o <= clock_divider_reg;
`capa: wb_dat_o <= capabilies_reg;
`data_isr: wb_dat_o <= data_int_status_reg;
`blkcnt: wb_dat_o <= block_count_reg;
`data_iser: wb_dat_o <= data_int_enable_reg;
`dst_src_addr: wb_dat_o <= dma_addr_reg;
endcase
end
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 16 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 16 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 16 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 16 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 16 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 16 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 16 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 16 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 16 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 16 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 16 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 16 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 16 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 16 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 16 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 16 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_1x3(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [15 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [15 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [15 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [15 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [15 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [15 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [15 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [15 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [15 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [15 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [15 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [15 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [15 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [15 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [15 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [15 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [15 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_to_slaves_0_arid,
v_to_slaves_0_awid,
v_to_slaves_1_arid,
v_to_slaves_1_awid,
v_to_slaves_2_arid,
v_to_slaves_2_awid;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_to_slaves_0_arcache,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
wire [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
wire [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
wire [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [23 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ;
// ports of submodule fabric_v_f_rd_mis_0
wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [15 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ;
// ports of submodule fabric_v_f_wr_mis_0
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$D_IN,
fabric_v_f_wr_mis_0$D_OUT,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$D_IN,
fabric_v_f_wr_mis_1$D_OUT,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$D_IN,
fabric_v_f_wr_mis_2$D_OUT,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [82 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
wire [17 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h6565;
reg [31 : 0] v__h6916;
reg [31 : 0] v__h7267;
reg [31 : 0] v__h7953;
reg [31 : 0] v__h8200;
reg [31 : 0] v__h8557;
reg [31 : 0] v__h8827;
reg [31 : 0] v__h9097;
reg [31 : 0] v__h9331;
reg [31 : 0] v__h9735;
reg [31 : 0] v__h10073;
reg [31 : 0] v__h10411;
reg [31 : 0] v__h11108;
reg [31 : 0] v__h11389;
reg [31 : 0] v__h11757;
reg [31 : 0] v__h12028;
reg [31 : 0] v__h12396;
reg [31 : 0] v__h12667;
reg [31 : 0] v__h13120;
reg [31 : 0] v__h4397;
reg [31 : 0] v__h6910;
reg [31 : 0] v__h4391;
reg [31 : 0] v__h6559;
reg [31 : 0] v__h7261;
reg [31 : 0] v__h7947;
reg [31 : 0] v__h8194;
reg [31 : 0] v__h8551;
reg [31 : 0] v__h8821;
reg [31 : 0] v__h9091;
reg [31 : 0] v__h9325;
reg [31 : 0] v__h9729;
reg [31 : 0] v__h10067;
reg [31 : 0] v__h10405;
reg [31 : 0] v__h11102;
reg [31 : 0] v__h11383;
reg [31 : 0] v__h11751;
reg [31 : 0] v__h12022;
reg [31 : 0] v__h12390;
reg [31 : 0] v__h12661;
reg [31 : 0] v__h13114;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1;
wire [7 : 0] x__h11272, x__h11921, x__h12560, x__h13057, x__h8102;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_ETC___d245,
IF_fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_ETC___d284,
IF_fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_ETC___d323,
x1_avValue_rresp__h11250,
x1_avValue_rresp__h11899,
x1_avValue_rresp__h12538;
wire fabric_v_f_wd_tasks_0_i_notEmpty__9_AND_fabric_ETC___d78,
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218,
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258,
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297,
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338,
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d170,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d171,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[17:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[82:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd24),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd16),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) &&
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__9_AND_fabric_ETC___d78 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
!fabric_v_f_wr_mis_0$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_1$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_2$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167) &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d170 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d171) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167) &&
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d170 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d171 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
(fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_0$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_1$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_2$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ?
8'd0 :
x__h11272 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ?
8'd0 :
x__h11921 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ?
8'd0 :
x__h12560 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 ?
8'd0 :
x__h8102 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_ETC___d245,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_ETC___d284,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_ETC___d323,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[15:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
assign fabric_v_rg_r_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
assign fabric_v_rg_r_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
assign fabric_v_rg_r_beat_count_2$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 ?
8'd0 :
x__h13057 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN = 24'h0 ;
assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
{ 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign fabric_v_f_rd_mis_0$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_v_f_rd_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN = fabric_v_f_rd_mis_0$D_IN ;
assign fabric_v_f_rd_mis_1$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
assign fabric_v_f_rd_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN = fabric_v_f_rd_mis_0$D_IN ;
assign fabric_v_f_rd_mis_2$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN = 16'h0 ;
assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_0$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_v_f_wr_mis_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_1$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_v_f_wr_mis_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_2$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_mis_2$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
83'h2AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
18'b101010101010101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_ETC___d245 =
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ?
x1_avValue_rresp__h11250 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_ETC___d284 =
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ?
x1_avValue_rresp__h11899 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_ETC___d323 =
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ?
x1_avValue_rresp__h12538 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__9_AND_fabric_ETC___d78 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[23:16] ;
assign fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'h0000000002000000 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'd33603584 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d170 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'h000000000C000000 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d171 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'd205520896 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'h0000000002000000 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'd33603584 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'h000000000C000000 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'd205520896 ;
assign x1_avValue_rresp__h11250 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h11899 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h12538 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h11272 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h11921 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h12560 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h13057 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h8102 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h6565 = $stime;
#0;
end
v__h6559 = v__h6565 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h6559,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h6916 = $stime;
#0;
end
v__h6910 = v__h6916 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h6910,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7267 = $stime;
#0;
end
v__h7261 = v__h7267 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h7261,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7953 = $stime;
#0;
end
v__h7947 = v__h7953 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h7947,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8],
fabric_v_rg_wd_beat_count_0,
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h8200 = $stime;
#0;
end
v__h8194 = v__h8200 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h8194,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8557 = $stime;
#0;
end
v__h8551 = v__h8557 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h8551,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8827 = $stime;
#0;
end
v__h8821 = v__h8827 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h8821,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9097 = $stime;
#0;
end
v__h9091 = v__h9097 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h9091,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9331 = $stime;
#0;
end
v__h9325 = v__h9331 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h9325,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9735 = $stime;
#0;
end
v__h9729 = v__h9735 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h9729,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10073 = $stime;
#0;
end
v__h10067 = v__h10073 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h10067,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10411 = $stime;
#0;
end
v__h10405 = v__h10411 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h10405,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h11108 = $stime;
#0;
end
v__h11102 = v__h11108 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h11102,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11389 = $stime;
#0;
end
v__h11383 = v__h11389 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h11383,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_ETC___d245);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h11757 = $stime;
#0;
end
v__h11751 = v__h11757 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h11751,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12028 = $stime;
#0;
end
v__h12022 = v__h12028 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h12022,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_ETC___d284);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h12396 = $stime;
#0;
end
v__h12390 = v__h12396 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h12390,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12667 = $stime;
#0;
end
v__h12661 = v__h12667 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h12661,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_ETC___d323);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13120 = $stime;
#0;
end
v__h13114 = v__h13120 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h13114,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[15:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h4397 = $stime;
#0;
end
v__h4391 = v__h4397 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h4391);
end
// synopsys translate_on
endmodule // mkFabric_1x3
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__INPUTISO0P_BEHAVIORAL_PP_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire sleepn ;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepn , SLEEP );
and and0 (and0_out_X, A, sleepn );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0P_BEHAVIORAL_PP_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_databuf_ca.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
//
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module cpx_databuf_ca(/*AUTOARG*/
// Outputs
sctag_cpx_data_buf_pa,
// Inputs
sctag_cpx_data_pa
);
output [144:0] sctag_cpx_data_buf_pa;
input [144:0] sctag_cpx_data_pa;
assign sctag_cpx_data_buf_pa = sctag_cpx_data_pa;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A311OI_PP_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311OI_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Hasan Hassan
//
// Create Date: 08/24/2015 04:50:25 PM
// Design Name:
// Module Name: SHDScheduler
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SHDScheduler #(parameter DNA_DATA_WIDTH = 128, NUM_PES = 4) (
input clk,
input rst,
//Receiver Interface
output dna_rd_en,
input[DNA_DATA_WIDTH - 1:0] dna_data_in,
input[DNA_DATA_WIDTH - 1:0] dna_data_ref_in,
input dna_valid_in,
//SHDs Interface
input shd_clk,
input[NUM_PES - 1:0] shd_rd_en_in,
output[NUM_PES - 1:0] shd_valid_out,
output[NUM_PES*DNA_DATA_WIDTH - 1:0] shd_dna_data_out,
output[NUM_PES*DNA_DATA_WIDTH - 1:0] shd_dna_data_ref_out
);
reg[DNA_DATA_WIDTH - 1:0] dna_data_r;
reg[DNA_DATA_WIDTH - 1:0] dna_data_ref_r;
reg dna_valid_r = 0;
wire accept_dna_data;
reg dna_issued;
//Register incoming dna data
always@(posedge clk) begin
dna_valid_r <= 1'b0;
if(rst) begin
dna_data_r <= 0;
dna_data_ref_r <= 0;
dna_valid_r <= 0;
end
else begin
if(accept_dna_data) begin
dna_data_r <= dna_data_in;
dna_data_ref_r <= dna_data_ref_in;
dna_valid_r <= dna_valid_in;
end
end
end
assign accept_dna_data = !dna_valid_r || dna_issued;
assign dna_rd_en = accept_dna_data;
//SHD FIFOs
wire[NUM_PES - 1:0] shd_fifo_full, shd_fifo_empty;
reg[NUM_PES - 1:0] shd_fifo_wr_en;
genvar i;
generate
for (i=0; i < NUM_PES; i=i+1) begin
shd_fifo i_shd_fifo (
.rst(rst), // input wire rst
.wr_clk(clk), // input wire wr_clk
.rd_clk(shd_clk), // input wire rd_clk
.din({dna_data_r, dna_data_ref_r}), // input wire [255 : 0] din
.wr_en(shd_fifo_wr_en[i]), // input wire wr_en
.rd_en(shd_rd_en_in[i]), // input wire rd_en
.dout({shd_dna_data_out[i*DNA_DATA_WIDTH +: DNA_DATA_WIDTH], shd_dna_data_ref_out[i*DNA_DATA_WIDTH +: DNA_DATA_WIDTH]}), // output wire [255 : 0] dout
.full(shd_fifo_full[i]), // output wire full
.empty(shd_fifo_empty[i]) // output wire empty
);
end
endgenerate
assign shd_valid_out = ~shd_fifo_empty;
// --- ARBITRATION LOGIC ---
//SHD PE iterator
parameter PE_BITS = $clog2(NUM_PES);
reg[PE_BITS - 1:0] pe_iterator = 0;
wire advance_pe_it;
always@(posedge clk) begin
if(rst) begin
pe_iterator <= 0;
end
else begin
if(advance_pe_it) begin
pe_iterator <= pe_iterator + 1'b1;
end
end
end
assign advance_pe_it = /*shd_fifo_full[pe_iterator] ||*/ dna_issued; //We want to preserve the order. Looking for non-full FIFOs may break it
//Issue to current FIFO if not full
always@* begin
shd_fifo_wr_en = {NUM_PES{1'b0}};
dna_issued = 1'b0;
if(dna_valid_r && ~shd_fifo_full[pe_iterator]) begin
shd_fifo_wr_en[pe_iterator] = 1'b1;
dna_issued = 1'b1;
end
end
// --- END - ARBITRATION LOGIC ---
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.08.2013 15:05:03
// Design Name:
// Module Name: vc709_10g_interface
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module eth10g_interface(
// 200MHz reference clock input
input reset,
input aresetn,
// 156.25 MHz clock in
input xphy_refclk_p,
input xphy_refclk_n,
output xphy0_txp,
output xphy0_txn,
input xphy0_rxp,
input xphy0_rxn,
output xphy1_txp,
output xphy1_txn,
input xphy1_rxp,
input xphy1_rxn,
output xphy2_txp,
output xphy2_txn,
input xphy2_rxp,
input xphy2_rxn,
output xphy3_txp,
output xphy3_txn,
input xphy3_rxp,
input xphy3_rxn,
output[63:0] axis_i_0_tdata,
output axis_i_0_tvalid,
output axis_i_0_tlast,
output axis_i_0_tuser,
output[7:0] axis_i_0_tkeep,
input axis_i_0_tready,
//rx status
output nic_rx_fifo_overflow,
output [29:0] nic_rx_statistics_vector,
output nic_rx_statistics_valid,
input[63:0] axis_o_0_tdata,
input axis_o_0_tvalid,
input axis_o_0_tlast,
input axis_o_0_tuser,
input[7:0] axis_o_0_tkeep,
output axis_o_0_tready,
output[3:0] sfp_tx_disable,
output clk156_out,
output clk_ref_200_out,
output network_reset_done,
output [7:0] led
);
wire clk_ref_200;
wire[7:0] core0_status;
wire[7:0] core1_status;
wire[7:0] core2_status;
wire[7:0] core3_status;
// Shared clk signals
wire gt_txclk322;
wire gt_txusrclk;
wire gt_txusrclk2;
wire gt_qplllock;
wire gt_gpllrefclklost;
wire gt_gplloutrefclk;
wire gt_gplllock_txusrclk2;
wire gttxreset_txusrclk2;
wire gt_txuserrdy;
wire tx_fault;
wire core_reset;
wire gt0_tx_resetdone;
wire gt1_tx_resetdone;
wire gt2_tx_resetdone;
wire gt3_tx_resetdone;
wire areset_clk_156_25_bufh;
wire areset_clk_156_25;
wire mmcm_locked_clk156;
wire reset_counter_done;
wire gttxreset;
wire gtrxreset;
wire clk156_25;
wire dclk_i;
wire xphyrefclk_i;
assign network_reset_done = ~core_reset;
wire[63:0] axis_i_1_tdata;
wire axis_i_1_tvalid;
wire axis_i_1_tlast;
wire axis_i_1_tuser;
wire[7:0] axis_i_1_tkeep;
wire axis_i_1_tready;
wire[63:0] axis_o_1_tdata;
wire axis_o_1_tvalid;
wire axis_o_1_tlast;
//wire axis_o_1_tuser;
wire[7:0] axis_o_1_tkeep;
wire axis_o_1_tready;
wire[63:0] axis_i_2_tdata;
wire axis_i_2_tvalid;
wire axis_i_2_tlast;
wire axis_i_2_tuser;
wire[7:0] axis_i_2_tkeep;
wire axis_i_2_tready;
wire[63:0] axis_o_2_tdata;
wire axis_o_2_tvalid;
wire axis_o_2_tlast;
//wire axis_o_2_tuser;
wire[7:0] axis_o_2_tkeep;
wire axis_o_2_tready;
wire[63:0] axis_i_3_tdata;
wire axis_i_3_tvalid;
wire axis_i_3_tlast;
wire axis_i_3_tuser;
wire[7:0] axis_i_3_tkeep;
wire axis_i_3_tready;
wire[63:0] axis_o_3_tdata;
wire axis_o_3_tvalid;
wire axis_o_3_tlast;
//wire axis_o_3_tuser;
wire[7:0] axis_o_3_tkeep;
wire axis_o_3_tready;
assign clk156_out = clk156_25;
assign clk_ref_200_out = clk_ref_200;
/*
* Clocks
*/
/*
* Network modules
*/
wire[7:0] tx_ifg_delay;
wire signal_detect;
//wire tx_fault;
assign tx_ifg_delay = 8'h00;
assign signal_detect = 1'b1;
//assign tx_fault = 1'b0;
network_module network_inst_0
(
.clk156 (clk156_25),
.reset(reset),
.aresetn(aresetn),
.dclk (dclk_i),
.txusrclk (gt_txusrclk),
.txusrclk2 (gt_txusrclk2),
.txclk322 (gt_txclk322),
.areset_refclk_bufh (areset_clk_156_25_bufh),
.areset_clk156 (areset_clk_156_25),
.mmcm_locked_clk156 (mmcm_locked_clk156),
.gttxreset_txusrclk2 (gttxreset_txusrclk2),
.gttxreset (gttxreset),
.gtrxreset (gtrxreset),
.txuserrdy (gt_txuserrdy),
.qplllock (gt_qplllock),
.qplloutclk (gt_qplloutclk),
.qplloutrefclk (gt_qplloutrefclk),
.reset_counter_done (reset_counter_done),
.tx_resetdone (gt0_tx_resetdone),
.txp(xphy0_txp),
.txn(xphy0_txn),
.rxp(xphy0_rxp),
.rxn(xphy0_rxn),
.tx_axis_tdata(axis_o_0_tdata),
.tx_axis_tvalid(axis_o_0_tvalid),
.tx_axis_tlast(axis_o_0_tlast),
.tx_axis_tuser(1'b0),
.tx_axis_tkeep(axis_o_0_tkeep),
.tx_axis_tready(axis_o_0_tready),
.rx_axis_tdata(axis_i_0_tdata),
.rx_axis_tvalid(axis_i_0_tvalid),
.rx_axis_tuser(axis_i_0_tuser),
.rx_axis_tlast(axis_i_0_tlast),
.rx_axis_tkeep(axis_i_0_tkeep),
.rx_axis_tready(axis_i_0_tready),
.core_reset(core_reset),
.tx_fault(tx_fault),
.signal_detect(signal_detect),
.tx_ifg_delay(tx_ifg_delay),
.tx_disable(),
.rx_fifo_overflow(nic_rx_fifo_overflow),
.rx_statistics_vector(nic_rx_statistics_vector),
.rx_statistics_valid(nic_rx_statistics_valid),
.core_status(core0_status)
);
//wire xphyrefclk_i;
IBUFDS_GTE2 xgphy_refclk_ibuf (
.I (xphy_refclk_p),
.IB (xphy_refclk_n),
.O (xphyrefclk_i ),
.CEB (1'b0 ),
.ODIV2 ( )
);
assign gt1_tx_resetdone = 1'b1;
assign gt2_tx_resetdone = 1'b1;
assign gt3_tx_resetdone = 1'b1;
xgbaser_gt_same_quad_wrapper #(
.WRAPPER_SIM_GTRESET_SPEEDUP ("TRUE" )
) xgbaser_gt_wrapper_inst (
.gt_txclk322 (gt_txclk322),
.gt_txusrclk (gt_txusrclk),
.gt_txusrclk2 (gt_txusrclk2),
.qplllock (gt_qplllock),
.qpllrefclklost (gt_qpllrefclklost),
.qplloutclk (gt_qplloutclk),
.qplloutrefclk (gt_qplloutrefclk),
.qplllock_txusrclk2 (gt_qplllock_txusrclk2), //not used
.gttxreset_txusrclk2 (gttxreset_txusrclk2),
.txuserrdy (gt_txuserrdy),
.tx_fault (tx_fault),
.core_reset (core_reset),
.gt0_tx_resetdone (gt0_tx_resetdone),
.gt1_tx_resetdone (gt1_tx_resetdone),
.gt2_tx_resetdone (gt2_tx_resetdone),
.gt3_tx_resetdone (gt3_tx_resetdone),
.areset_clk_156_25_bufh (areset_clk_156_25_bufh),
.areset_clk_156_25 (areset_clk_156_25),
.mmcm_locked_clk156 (mmcm_locked_clk156),
.reset_counter_done (reset_counter_done),
.gttxreset (gttxreset),
.gtrxreset (gtrxreset),
.clk156 (clk156_25 ),
.areset (reset),
.dclk (dclk_i ),
.gt_refclk (xphyrefclk_i )
);
assign sfp_tx_disable = 4'b0000;
localparam LED_CTR_WIDTH = 26;
reg [LED_CTR_WIDTH-1:0] l1_ctr;
reg [LED_CTR_WIDTH-1:0] l2_ctr;
always @(posedge clk156_25)
begin
l1_ctr <= l1_ctr + {{(LED_CTR_WIDTH-1){1'b0}}, 1'b1};
end
assign led[0] = l1_ctr[LED_CTR_WIDTH-1];
assign led[1] = l2_ctr[LED_CTR_WIDTH-1];
//assign led[2] = reset;
//assign led[3] = core_reset;
assign led[2] = core0_status[0];
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos2_term_up.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_cmos2_term_up (
vddo, out
);
inout out;
input vddo;
endmodule
|
// File : ../RTL/hostController/getpacket.v
// Generated : 11/10/06 05:37:20
// From : ../RTL/hostController/getpacket.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// getpacket
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
`include "usbConstants_h.v"
module getPacket (RXDataIn, RXDataValid, RXFifoData, RXFifoFull, RXFifoWEn, RXPacketRdy, RXPktStatus, RXStreamStatusIn, RxPID, SIERxTimeOut, SIERxTimeOutEn, clk, getPacketEn, rst);
input [7:0] RXDataIn;
input RXDataValid;
input RXFifoFull;
input [7:0] RXStreamStatusIn;
input SIERxTimeOut; // Single cycle pulse
input clk;
input getPacketEn;
input rst;
output [7:0] RXFifoData;
output RXFifoWEn;
output RXPacketRdy;
output [7:0] RXPktStatus;
output [3:0] RxPID;
output SIERxTimeOutEn;
wire [7:0] RXDataIn;
wire RXDataValid;
reg [7:0] RXFifoData, next_RXFifoData;
wire RXFifoFull;
reg RXFifoWEn, next_RXFifoWEn;
reg RXPacketRdy, next_RXPacketRdy;
reg [7:0] RXPktStatus;
wire [7:0] RXStreamStatusIn;
reg [3:0] RxPID, next_RxPID;
wire SIERxTimeOut;
reg SIERxTimeOutEn, next_SIERxTimeOutEn;
wire clk;
wire getPacketEn;
wire rst;
// diagram signals declarations
reg ACKRxed, next_ACKRxed;
reg CRCError, next_CRCError;
reg NAKRxed, next_NAKRxed;
reg [7:0]RXByteOld, next_RXByteOld;
reg [7:0]RXByteOldest, next_RXByteOldest;
reg [7:0]RXByte, next_RXByte;
reg RXOverflow, next_RXOverflow;
reg [7:0]RXStreamStatus, next_RXStreamStatus;
reg RXTimeOut, next_RXTimeOut;
reg bitStuffError, next_bitStuffError;
reg dataSequence, next_dataSequence;
reg stallRxed, next_stallRxed;
// BINARY ENCODED state machine: getPkt
// State codes definitions:
`define PROC_PKT_CHK_PID 5'b00000
`define PROC_PKT_HS 5'b00001
`define PROC_PKT_DATA_W_D1 5'b00010
`define PROC_PKT_DATA_CHK_D1 5'b00011
`define PROC_PKT_DATA_W_D2 5'b00100
`define PROC_PKT_DATA_FIN 5'b00101
`define PROC_PKT_DATA_CHK_D2 5'b00110
`define PROC_PKT_DATA_W_D3 5'b00111
`define PROC_PKT_DATA_CHK_D3 5'b01000
`define PROC_PKT_DATA_LOOP_CHK_FIFO 5'b01001
`define PROC_PKT_DATA_LOOP_FIFO_FULL 5'b01010
`define PROC_PKT_DATA_LOOP_W_D 5'b01011
`define START_GP 5'b01100
`define WAIT_PKT 5'b01101
`define CHK_PKT_START 5'b01110
`define WAIT_EN 5'b01111
`define PKT_RDY 5'b10000
`define PROC_PKT_DATA_LOOP_DELAY 5'b10001
reg [4:0] CurrState_getPkt;
reg [4:0] NextState_getPkt;
// Diagram actions (continuous assignments allowed only: assign ...)
always @
(CRCError or bitStuffError or
RXOverflow or RXTimeOut or
NAKRxed or stallRxed or
ACKRxed or dataSequence)
begin
RXPktStatus <= {
dataSequence, ACKRxed,
stallRxed, NAKRxed,
RXTimeOut, RXOverflow,
bitStuffError, CRCError};
end
//--------------------------------------------------------------------
// Machine: getPkt
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RXDataIn or RXStreamStatusIn or RXByte or RXByteOldest or RXByteOld or SIERxTimeOut or RXDataValid or RXStreamStatus or getPacketEn or RXFifoFull or CRCError or bitStuffError or RXOverflow or RXTimeOut or NAKRxed or stallRxed or ACKRxed or dataSequence or SIERxTimeOutEn or RxPID or RXPacketRdy or RXFifoWEn or RXFifoData or CurrState_getPkt)
begin : getPkt_NextState
NextState_getPkt <= CurrState_getPkt;
// Set default values for outputs and signals
next_CRCError <= CRCError;
next_bitStuffError <= bitStuffError;
next_RXOverflow <= RXOverflow;
next_RXTimeOut <= RXTimeOut;
next_NAKRxed <= NAKRxed;
next_stallRxed <= stallRxed;
next_ACKRxed <= ACKRxed;
next_dataSequence <= dataSequence;
next_SIERxTimeOutEn <= SIERxTimeOutEn;
next_RXByte <= RXByte;
next_RXStreamStatus <= RXStreamStatus;
next_RxPID <= RxPID;
next_RXPacketRdy <= RXPacketRdy;
next_RXByteOldest <= RXByteOldest;
next_RXByteOld <= RXByteOld;
next_RXFifoWEn <= RXFifoWEn;
next_RXFifoData <= RXFifoData;
case (CurrState_getPkt)
`START_GP:
NextState_getPkt <= `WAIT_EN;
`WAIT_PKT:
begin
next_CRCError <= 1'b0;
next_bitStuffError <= 1'b0;
next_RXOverflow <= 1'b0;
next_RXTimeOut <= 1'b0;
next_NAKRxed <= 1'b0;
next_stallRxed <= 1'b0;
next_ACKRxed <= 1'b0;
next_dataSequence <= 1'b0;
next_SIERxTimeOutEn <= 1'b1;
if (SIERxTimeOut == 1'b1)
begin
NextState_getPkt <= `PKT_RDY;
next_RXTimeOut <= 1'b1;
end
else if (RXDataValid == 1'b1)
begin
NextState_getPkt <= `CHK_PKT_START;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
end
`CHK_PKT_START:
if (RXStreamStatus == `RX_PACKET_START)
begin
NextState_getPkt <= `PROC_PKT_CHK_PID;
next_RxPID <= RXByte[3:0];
end
else
begin
NextState_getPkt <= `PKT_RDY;
next_RXTimeOut <= 1'b1;
end
`WAIT_EN:
begin
next_RXPacketRdy <= 1'b0;
next_SIERxTimeOutEn <= 1'b0;
if (getPacketEn == 1'b1)
NextState_getPkt <= `WAIT_PKT;
end
`PKT_RDY:
begin
next_RXPacketRdy <= 1'b1;
NextState_getPkt <= `WAIT_EN;
end
`PROC_PKT_CHK_PID:
if (RXByte[1:0] == `HANDSHAKE)
NextState_getPkt <= `PROC_PKT_HS;
else if (RXByte[1:0] == `DATA)
NextState_getPkt <= `PROC_PKT_DATA_W_D1;
else
NextState_getPkt <= `PKT_RDY;
`PROC_PKT_HS:
if (RXDataValid == 1'b1)
begin
NextState_getPkt <= `PKT_RDY;
next_RXOverflow <= RXDataIn[`RX_OVERFLOW_BIT];
next_NAKRxed <= RXDataIn[`NAK_RXED_BIT];
next_stallRxed <= RXDataIn[`STALL_RXED_BIT];
next_ACKRxed <= RXDataIn[`ACK_RXED_BIT];
end
`PROC_PKT_DATA_W_D1:
if (RXDataValid == 1'b1)
begin
NextState_getPkt <= `PROC_PKT_DATA_CHK_D1;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
`PROC_PKT_DATA_CHK_D1:
if (RXStreamStatus == `RX_PACKET_STREAM)
begin
NextState_getPkt <= `PROC_PKT_DATA_W_D2;
next_RXByteOldest <= RXByte;
end
else
NextState_getPkt <= `PROC_PKT_DATA_FIN;
`PROC_PKT_DATA_W_D2:
if (RXDataValid == 1'b1)
begin
NextState_getPkt <= `PROC_PKT_DATA_CHK_D2;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
`PROC_PKT_DATA_FIN:
begin
next_CRCError <= RXByte[`CRC_ERROR_BIT];
next_bitStuffError <= RXByte[`BIT_STUFF_ERROR_BIT];
next_dataSequence <= RXByte[`DATA_SEQUENCE_BIT];
NextState_getPkt <= `PKT_RDY;
end
`PROC_PKT_DATA_CHK_D2:
if (RXStreamStatus == `RX_PACKET_STREAM)
begin
NextState_getPkt <= `PROC_PKT_DATA_W_D3;
next_RXByteOld <= RXByte;
end
else
NextState_getPkt <= `PROC_PKT_DATA_FIN;
`PROC_PKT_DATA_W_D3:
if (RXDataValid == 1'b1)
begin
NextState_getPkt <= `PROC_PKT_DATA_CHK_D3;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
`PROC_PKT_DATA_CHK_D3:
if (RXStreamStatus == `RX_PACKET_STREAM)
NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
else
NextState_getPkt <= `PROC_PKT_DATA_FIN;
`PROC_PKT_DATA_LOOP_CHK_FIFO:
if (RXFifoFull == 1'b1)
begin
NextState_getPkt <= `PROC_PKT_DATA_LOOP_FIFO_FULL;
next_RXOverflow <= 1'b1;
end
else
begin
NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
next_RXFifoWEn <= 1'b1;
next_RXFifoData <= RXByteOldest;
next_RXByteOldest <= RXByteOld;
next_RXByteOld <= RXByte;
end
`PROC_PKT_DATA_LOOP_FIFO_FULL:
NextState_getPkt <= `PROC_PKT_DATA_LOOP_W_D;
`PROC_PKT_DATA_LOOP_W_D:
begin
next_RXFifoWEn <= 1'b0;
if ((RXDataValid == 1'b1) && (RXStreamStatusIn == `RX_PACKET_STREAM))
begin
NextState_getPkt <= `PROC_PKT_DATA_LOOP_DELAY;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
else if (RXDataValid == 1'b1)
begin
NextState_getPkt <= `PROC_PKT_DATA_FIN;
next_RXByte <= RXDataIn;
next_RXStreamStatus <= RXStreamStatusIn;
end
end
`PROC_PKT_DATA_LOOP_DELAY:
NextState_getPkt <= `PROC_PKT_DATA_LOOP_CHK_FIFO;
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : getPkt_CurrentState
if (rst)
CurrState_getPkt <= `START_GP;
else
CurrState_getPkt <= NextState_getPkt;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : getPkt_RegOutput
if (rst)
begin
RXByteOld <= 8'h00;
RXByteOldest <= 8'h00;
CRCError <= 1'b0;
bitStuffError <= 1'b0;
RXOverflow <= 1'b0;
RXTimeOut <= 1'b0;
NAKRxed <= 1'b0;
stallRxed <= 1'b0;
ACKRxed <= 1'b0;
dataSequence <= 1'b0;
RXByte <= 8'h00;
RXStreamStatus <= 8'h00;
RXPacketRdy <= 1'b0;
RXFifoWEn <= 1'b0;
RXFifoData <= 8'h00;
RxPID <= 4'h0;
SIERxTimeOutEn <= 1'b0;
end
else
begin
RXByteOld <= next_RXByteOld;
RXByteOldest <= next_RXByteOldest;
CRCError <= next_CRCError;
bitStuffError <= next_bitStuffError;
RXOverflow <= next_RXOverflow;
RXTimeOut <= next_RXTimeOut;
NAKRxed <= next_NAKRxed;
stallRxed <= next_stallRxed;
ACKRxed <= next_ACKRxed;
dataSequence <= next_dataSequence;
RXByte <= next_RXByte;
RXStreamStatus <= next_RXStreamStatus;
RXPacketRdy <= next_RXPacketRdy;
RXFifoWEn <= next_RXFifoWEn;
RXFifoData <= next_RXFifoData;
RxPID <= next_RxPID;
SIERxTimeOutEn <= next_SIERxTimeOutEn;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_1_V
`define SKY130_FD_SC_HS__O31AI_1_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31ai_1 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 19:31:56 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
output [31:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire n1729, Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, left_right_SHT2, SIGN_FLAG_SHT2, OP_FLAG_SHT2,
ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2, ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM,
ZERO_FLAG_NRM, SIGN_FLAG_SFG, OP_FLAG_SFG, ZERO_FLAG_SFG,
inst_FSM_INPUT_ENABLE_state_next_1_, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539,
n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550,
n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561,
n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572,
n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594,
n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616,
n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638,
n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660,
n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671,
n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682,
n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693,
n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704,
n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726,
n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748,
n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792,
n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803,
n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814,
n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825,
n826, n827, n828, n830, n831, n832, n833, n834, n835, n836, n837,
n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848,
n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859,
n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870,
n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881,
n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892,
n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903,
n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, n914,
n915, n916, n917, n918, n919, n920, n921, n922, n923, n925, n927,
n928, n929, n930, n931, n932, DP_OP_15J39_125_2314_n8,
DP_OP_15J39_125_2314_n7, DP_OP_15J39_125_2314_n6,
DP_OP_15J39_125_2314_n5, DP_OP_15J39_125_2314_n4, intadd_44_A_9_,
intadd_44_A_8_, intadd_44_A_7_, intadd_44_A_6_, intadd_44_A_5_,
intadd_44_A_4_, intadd_44_A_3_, intadd_44_A_2_, intadd_44_A_1_,
intadd_44_A_0_, intadd_44_B_12_, intadd_44_B_11_, intadd_44_B_10_,
intadd_44_B_9_, intadd_44_B_8_, intadd_44_B_7_, intadd_44_B_6_,
intadd_44_B_5_, intadd_44_B_4_, intadd_44_B_3_, intadd_44_B_2_,
intadd_44_B_1_, intadd_44_B_0_, intadd_44_CI, intadd_44_SUM_12_,
intadd_44_SUM_11_, intadd_44_SUM_10_, intadd_44_SUM_9_,
intadd_44_SUM_8_, intadd_44_SUM_7_, intadd_44_SUM_6_,
intadd_44_SUM_5_, intadd_44_SUM_4_, intadd_44_SUM_3_,
intadd_44_SUM_2_, intadd_44_SUM_1_, intadd_44_SUM_0_, intadd_44_n13,
intadd_44_n12, intadd_44_n11, intadd_44_n10, intadd_44_n9,
intadd_44_n8, intadd_44_n7, intadd_44_n6, intadd_44_n5, intadd_44_n4,
intadd_44_n3, intadd_44_n2, intadd_44_n1, n933, n934, n935, n936,
n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947,
n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958,
n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969,
n970, n971, n972, n973, n974, n975, n976, n977, n978, n979, n980,
n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991,
n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002,
n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012,
n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022,
n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032,
n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042,
n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052,
n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062,
n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072,
n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082,
n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092,
n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102,
n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112,
n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122,
n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132,
n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142,
n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152,
n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162,
n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172,
n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423,
n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433,
n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443,
n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453,
n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463,
n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473,
n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483,
n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493,
n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1728;
wire [1:0] Shift_reg_FLAGS_7;
wire [31:0] intDX_EWSW;
wire [31:0] intDY_EWSW;
wire [30:0] DMP_EXP_EWSW;
wire [27:0] DmP_EXP_EWSW;
wire [30:0] DMP_SHT1_EWSW;
wire [22:2] DmP_mant_SHT1_SW;
wire [4:0] Shift_amount_SHT1_EWR;
wire [25:0] Raw_mant_NRM_SWR;
wire [25:0] Data_array_SWR;
wire [30:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [7:0] DMP_exp_NRM2_EW;
wire [7:0] DMP_exp_NRM_EW;
wire [4:0] LZD_output_NRM2_EW;
wire [4:1] exp_rslt_NRM2_EW1;
wire [30:0] DMP_SFG;
wire [25:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS inst_ShiftRegister_Q_reg_3_ ( .D(n927), .CK(clk), .RN(n1693), .QN(
n942) );
DFFRXLTS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n913), .CK(clk), .RN(n1698),
.QN(n940) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n888), .CK(clk), .RN(n1696), .Q(
intDY_EWSW[1]), .QN(n1669) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n887), .CK(clk), .RN(n1695), .Q(
intDY_EWSW[2]), .QN(n947) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n880), .CK(clk), .RN(n1722), .Q(
intDY_EWSW[9]), .QN(n949) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n873), .CK(clk), .RN(n1698),
.Q(intDY_EWSW[16]), .QN(n948) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n871), .CK(clk), .RN(n1697),
.Q(intDY_EWSW[18]), .QN(n1630) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n826), .CK(clk), .RN(n1693),
.Q(Shift_amount_SHT1_EWR[1]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n825), .CK(clk), .RN(n1717),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n824), .CK(clk), .RN(n1692),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n823), .CK(clk), .RN(n1722),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_0_ ( .D(n814), .CK(clk), .RN(n1723), .Q(
DMP_EXP_EWSW[0]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_1_ ( .D(n813), .CK(clk), .RN(n1711), .Q(
DMP_EXP_EWSW[1]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_2_ ( .D(n812), .CK(clk), .RN(n1697), .Q(
DMP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_3_ ( .D(n811), .CK(clk), .RN(n1711), .Q(
DMP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_4_ ( .D(n810), .CK(clk), .RN(n1699), .Q(
DMP_EXP_EWSW[4]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_5_ ( .D(n809), .CK(clk), .RN(n1723), .Q(
DMP_EXP_EWSW[5]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_6_ ( .D(n808), .CK(clk), .RN(n1721), .Q(
DMP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_7_ ( .D(n807), .CK(clk), .RN(n1717), .Q(
DMP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_8_ ( .D(n806), .CK(clk), .RN(n1716), .Q(
DMP_EXP_EWSW[8]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_9_ ( .D(n805), .CK(clk), .RN(n1718), .Q(
DMP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_10_ ( .D(n804), .CK(clk), .RN(n1711), .Q(
DMP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_11_ ( .D(n803), .CK(clk), .RN(n1694), .Q(
DMP_EXP_EWSW[11]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_12_ ( .D(n802), .CK(clk), .RN(n1722), .Q(
DMP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_13_ ( .D(n801), .CK(clk), .RN(n1717), .Q(
DMP_EXP_EWSW[13]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_14_ ( .D(n800), .CK(clk), .RN(n1714), .Q(
DMP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_15_ ( .D(n799), .CK(clk), .RN(n1699), .Q(
DMP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_16_ ( .D(n798), .CK(clk), .RN(n1720), .Q(
DMP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_17_ ( .D(n797), .CK(clk), .RN(n1719), .Q(
DMP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_18_ ( .D(n796), .CK(clk), .RN(n1708), .Q(
DMP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_19_ ( .D(n795), .CK(clk), .RN(n1700), .Q(
DMP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_20_ ( .D(n794), .CK(clk), .RN(n1718), .Q(
DMP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_21_ ( .D(n793), .CK(clk), .RN(n1704), .Q(
DMP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_22_ ( .D(n792), .CK(clk), .RN(n1703), .Q(
DMP_EXP_EWSW[22]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_27_ ( .D(n787), .CK(clk), .RN(n1702), .QN(n937)
);
DFFRXLTS EXP_STAGE_DMP_Q_reg_28_ ( .D(n786), .CK(clk), .RN(n1705), .Q(
DMP_EXP_EWSW[28]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_29_ ( .D(n785), .CK(clk), .RN(n1060), .Q(
DMP_EXP_EWSW[29]) );
DFFRXLTS EXP_STAGE_DMP_Q_reg_30_ ( .D(n784), .CK(clk), .RN(n971), .Q(
DMP_EXP_EWSW[30]) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n783), .CK(clk), .RN(n1706), .Q(
OP_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n782), .CK(clk), .RN(n971), .Q(
ZERO_FLAG_EXP) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n781), .CK(clk), .RN(n1706), .Q(
SIGN_FLAG_EXP) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n780), .CK(clk), .RN(n1701), .Q(
DMP_SHT1_EWSW[0]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n779), .CK(clk), .RN(n1704), .Q(
DMP_SHT2_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n777), .CK(clk), .RN(n1703), .Q(
DMP_SHT1_EWSW[1]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n776), .CK(clk), .RN(n1702), .Q(
DMP_SHT2_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n774), .CK(clk), .RN(n1705), .Q(
DMP_SHT1_EWSW[2]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n773), .CK(clk), .RN(n1060), .Q(
DMP_SHT2_EWSW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n771), .CK(clk), .RN(n971), .Q(
DMP_SHT1_EWSW[3]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n770), .CK(clk), .RN(n1706), .Q(
DMP_SHT2_EWSW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n768), .CK(clk), .RN(n1701), .Q(
DMP_SHT1_EWSW[4]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n767), .CK(clk), .RN(n1704), .Q(
DMP_SHT2_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n765), .CK(clk), .RN(n1703), .Q(
DMP_SHT1_EWSW[5]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n764), .CK(clk), .RN(n1702), .Q(
DMP_SHT2_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n762), .CK(clk), .RN(n1705), .Q(
DMP_SHT1_EWSW[6]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n761), .CK(clk), .RN(n1060), .Q(
DMP_SHT2_EWSW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n759), .CK(clk), .RN(n971), .Q(
DMP_SHT1_EWSW[7]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n758), .CK(clk), .RN(n1706), .Q(
DMP_SHT2_EWSW[7]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n756), .CK(clk), .RN(n1701), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n755), .CK(clk), .RN(n1704), .Q(
DMP_SHT2_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n753), .CK(clk), .RN(n1703), .Q(
DMP_SHT1_EWSW[9]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n752), .CK(clk), .RN(n1702), .Q(
DMP_SHT2_EWSW[9]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n750), .CK(clk), .RN(n1705), .Q(
DMP_SHT1_EWSW[10]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n749), .CK(clk), .RN(n1060), .Q(
DMP_SHT2_EWSW[10]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n748), .CK(clk), .RN(n971), .Q(
DMP_SFG[10]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n747), .CK(clk), .RN(n1706), .Q(
DMP_SHT1_EWSW[11]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n746), .CK(clk), .RN(n1701), .Q(
DMP_SHT2_EWSW[11]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n745), .CK(clk), .RN(n1706), .Q(
DMP_SFG[11]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n744), .CK(clk), .RN(n1701), .Q(
DMP_SHT1_EWSW[12]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n743), .CK(clk), .RN(n1704), .Q(
DMP_SHT2_EWSW[12]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_12_ ( .D(n742), .CK(clk), .RN(n1703), .Q(
DMP_SFG[12]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n741), .CK(clk), .RN(n1702), .Q(
DMP_SHT1_EWSW[13]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n740), .CK(clk), .RN(n1705), .Q(
DMP_SHT2_EWSW[13]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_13_ ( .D(n739), .CK(clk), .RN(n1706), .Q(
DMP_SFG[13]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n738), .CK(clk), .RN(n1701), .Q(
DMP_SHT1_EWSW[14]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n737), .CK(clk), .RN(n1704), .Q(
DMP_SHT2_EWSW[14]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_14_ ( .D(n736), .CK(clk), .RN(n1703), .Q(
DMP_SFG[14]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n735), .CK(clk), .RN(n1702), .Q(
DMP_SHT1_EWSW[15]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n734), .CK(clk), .RN(n1705), .Q(
DMP_SHT2_EWSW[15]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_15_ ( .D(n733), .CK(clk), .RN(n1706), .Q(
DMP_SFG[15]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n732), .CK(clk), .RN(n1701), .Q(
DMP_SHT1_EWSW[16]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n731), .CK(clk), .RN(n1704), .Q(
DMP_SHT2_EWSW[16]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_16_ ( .D(n730), .CK(clk), .RN(n1703), .Q(
DMP_SFG[16]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n729), .CK(clk), .RN(n1702), .Q(
DMP_SHT1_EWSW[17]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n728), .CK(clk), .RN(n1705), .Q(
DMP_SHT2_EWSW[17]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_17_ ( .D(n727), .CK(clk), .RN(n1706), .Q(
DMP_SFG[17]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n726), .CK(clk), .RN(n1701), .Q(
DMP_SHT1_EWSW[18]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n725), .CK(clk), .RN(n1704), .Q(
DMP_SHT2_EWSW[18]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_18_ ( .D(n724), .CK(clk), .RN(n1703), .Q(
DMP_SFG[18]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n723), .CK(clk), .RN(n1702), .Q(
DMP_SHT1_EWSW[19]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n722), .CK(clk), .RN(n1705), .Q(
DMP_SHT2_EWSW[19]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_19_ ( .D(n721), .CK(clk), .RN(n1713), .Q(
DMP_SFG[19]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n720), .CK(clk), .RN(n1716), .Q(
DMP_SHT1_EWSW[20]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n719), .CK(clk), .RN(n1723), .Q(
DMP_SHT2_EWSW[20]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n717), .CK(clk), .RN(n1707), .Q(
DMP_SHT1_EWSW[21]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n716), .CK(clk), .RN(n1709), .Q(
DMP_SHT2_EWSW[21]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n714), .CK(clk), .RN(n1712), .Q(
DMP_SHT1_EWSW[22]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n713), .CK(clk), .RN(n1710), .Q(
DMP_SHT2_EWSW[22]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n711), .CK(clk), .RN(n1721), .Q(
DMP_SHT1_EWSW[23]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n710), .CK(clk), .RN(n1692), .Q(
DMP_SHT2_EWSW[23]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_23_ ( .D(n709), .CK(clk), .RN(n1711), .Q(
DMP_SFG[23]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n708), .CK(clk), .RN(n1694), .Q(
DMP_exp_NRM_EW[0]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n706), .CK(clk), .RN(n1722), .Q(
DMP_SHT1_EWSW[24]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n705), .CK(clk), .RN(n1717), .Q(
DMP_SHT2_EWSW[24]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_24_ ( .D(n704), .CK(clk), .RN(n1714), .Q(
DMP_SFG[24]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n703), .CK(clk), .RN(n1699), .Q(
DMP_exp_NRM_EW[1]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n701), .CK(clk), .RN(n1717), .Q(
DMP_SHT1_EWSW[25]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n700), .CK(clk), .RN(n1714), .Q(
DMP_SHT2_EWSW[25]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_25_ ( .D(n699), .CK(clk), .RN(n1699), .Q(
DMP_SFG[25]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n698), .CK(clk), .RN(n1720), .Q(
DMP_exp_NRM_EW[2]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n696), .CK(clk), .RN(n1719), .Q(
DMP_SHT1_EWSW[26]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n695), .CK(clk), .RN(n1708), .Q(
DMP_SHT2_EWSW[26]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_26_ ( .D(n694), .CK(clk), .RN(n1715), .Q(
DMP_SFG[26]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n693), .CK(clk), .RN(n1713), .Q(
DMP_exp_NRM_EW[3]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n691), .CK(clk), .RN(n1716), .Q(
DMP_SHT1_EWSW[27]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n690), .CK(clk), .RN(n1723), .Q(
DMP_SHT2_EWSW[27]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_27_ ( .D(n689), .CK(clk), .RN(n1707), .Q(
DMP_SFG[27]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n688), .CK(clk), .RN(n1709), .Q(
DMP_exp_NRM_EW[4]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n686), .CK(clk), .RN(n1712), .Q(
DMP_SHT1_EWSW[28]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n685), .CK(clk), .RN(n1710), .Q(
DMP_SHT2_EWSW[28]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_28_ ( .D(n684), .CK(clk), .RN(n1721), .Q(
DMP_SFG[28]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n683), .CK(clk), .RN(n1692), .Q(
DMP_exp_NRM_EW[5]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n681), .CK(clk), .RN(n1697), .Q(
DMP_SHT1_EWSW[29]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n680), .CK(clk), .RN(n1715), .Q(
DMP_SHT2_EWSW[29]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_29_ ( .D(n679), .CK(clk), .RN(n1712), .Q(
DMP_SFG[29]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n678), .CK(clk), .RN(n1710), .Q(
DMP_exp_NRM_EW[6]) );
DFFRXLTS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n676), .CK(clk), .RN(n1721), .Q(
DMP_SHT1_EWSW[30]) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n675), .CK(clk), .RN(n1692), .Q(
DMP_SHT2_EWSW[30]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_30_ ( .D(n674), .CK(clk), .RN(n1697), .Q(
DMP_SFG[30]) );
DFFRXLTS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n673), .CK(clk), .RN(n1715), .Q(
DMP_exp_NRM_EW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_0_ ( .D(n671), .CK(clk), .RN(n1713), .Q(
DmP_EXP_EWSW[0]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n670), .CK(clk), .RN(n1716), .QN(
n953) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_1_ ( .D(n669), .CK(clk), .RN(n1723), .Q(
DmP_EXP_EWSW[1]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n668), .CK(clk), .RN(n1707), .QN(
n954) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_2_ ( .D(n667), .CK(clk), .RN(n1709), .Q(
DmP_EXP_EWSW[2]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_3_ ( .D(n665), .CK(clk), .RN(n1699), .Q(
DmP_EXP_EWSW[3]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_4_ ( .D(n663), .CK(clk), .RN(n1694), .Q(
DmP_EXP_EWSW[4]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n662), .CK(clk), .RN(n1722), .QN(
n936) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_5_ ( .D(n661), .CK(clk), .RN(n1720), .Q(
DmP_EXP_EWSW[5]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n660), .CK(clk), .RN(n1719), .QN(
n951) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_6_ ( .D(n659), .CK(clk), .RN(n1708), .Q(
DmP_EXP_EWSW[6]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_7_ ( .D(n657), .CK(clk), .RN(n1700), .Q(
DmP_EXP_EWSW[7]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_8_ ( .D(n655), .CK(clk), .RN(n1718), .Q(
DmP_EXP_EWSW[8]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n654), .CK(clk), .RN(n1711), .QN(
n955) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_9_ ( .D(n653), .CK(clk), .RN(n1712), .Q(
DmP_EXP_EWSW[9]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_10_ ( .D(n651), .CK(clk), .RN(n1710), .Q(
DmP_EXP_EWSW[10]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_11_ ( .D(n649), .CK(clk), .RN(n1721), .Q(
DmP_EXP_EWSW[11]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n648), .CK(clk), .RN(n1692),
.QN(n935) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_12_ ( .D(n647), .CK(clk), .RN(n1697), .Q(
DmP_EXP_EWSW[12]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_13_ ( .D(n645), .CK(clk), .RN(n1715), .Q(
DmP_EXP_EWSW[13]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n644), .CK(clk), .RN(n1713),
.QN(n952) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_14_ ( .D(n643), .CK(clk), .RN(n1697), .Q(
DmP_EXP_EWSW[14]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_15_ ( .D(n641), .CK(clk), .RN(n1718), .Q(
DmP_EXP_EWSW[15]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_16_ ( .D(n639), .CK(clk), .RN(n1692), .Q(
DmP_EXP_EWSW[16]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_17_ ( .D(n637), .CK(clk), .RN(n1714), .Q(
DmP_EXP_EWSW[17]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_18_ ( .D(n635), .CK(clk), .RN(n1718), .Q(
DmP_EXP_EWSW[18]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_19_ ( .D(n633), .CK(clk), .RN(n1716), .Q(
DmP_EXP_EWSW[19]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_20_ ( .D(n631), .CK(clk), .RN(n1710), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_21_ ( .D(n629), .CK(clk), .RN(n1694), .Q(
DmP_EXP_EWSW[21]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_22_ ( .D(n627), .CK(clk), .RN(n1721), .Q(
DmP_EXP_EWSW[22]) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n618), .CK(clk), .RN(n1707), .Q(
ZERO_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n617), .CK(clk), .RN(n1708), .Q(
ZERO_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n616), .CK(clk), .RN(n1722), .Q(
ZERO_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n615), .CK(clk), .RN(n1712), .Q(
ZERO_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n614), .CK(clk), .RN(n1699), .Q(
ZERO_FLAG_SHT1SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n612), .CK(clk), .RN(n1722), .Q(
OP_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n611), .CK(clk), .RN(n1692), .Q(
OP_FLAG_SHT2) );
DFFRXLTS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n609), .CK(clk), .RN(n1715), .Q(
SIGN_FLAG_SHT1) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n608), .CK(clk), .RN(n1720), .Q(
SIGN_FLAG_SHT2) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n607), .CK(clk), .RN(n1709), .Q(
SIGN_FLAG_SFG) );
DFFRXLTS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n606), .CK(clk), .RN(n1710), .Q(
SIGN_FLAG_NRM) );
DFFRXLTS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n605), .CK(clk), .RN(n1694), .Q(
SIGN_FLAG_SHT1SHT2) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n587), .CK(clk), .RN(n1712), .Q(
LZD_output_NRM2_EW[4]), .QN(n1656) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n584), .CK(clk), .RN(n1707), .Q(
LZD_output_NRM2_EW[2]), .QN(n1651) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n579), .CK(clk), .RN(n1713), .Q(
LZD_output_NRM2_EW[0]) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n576), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[2]), .QN(n1014) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n573), .CK(clk), .RN(n1709), .Q(
LZD_output_NRM2_EW[3]), .QN(n1657) );
DFFRXLTS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n572), .CK(clk), .RN(n1710), .Q(
LZD_output_NRM2_EW[1]), .QN(n1650) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n566), .CK(clk), .RN(n1721), .Q(
DmP_mant_SFG_SWR[6]), .QN(n1019) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n563), .CK(clk), .RN(n1700), .Q(
DmP_mant_SFG_SWR[4]), .QN(n1023) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n555), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[5]), .QN(n1026) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n524), .CK(clk), .RN(n1717), .Q(
DmP_mant_SFG_SWR[25]), .QN(n1029) );
CMPR32X2TS intadd_44_U14 ( .A(intadd_44_A_0_), .B(intadd_44_B_0_), .C(
intadd_44_CI), .CO(intadd_44_n13), .S(intadd_44_SUM_0_) );
CMPR32X2TS intadd_44_U13 ( .A(intadd_44_A_1_), .B(intadd_44_B_1_), .C(
intadd_44_n13), .CO(intadd_44_n12), .S(intadd_44_SUM_1_) );
CMPR32X2TS intadd_44_U12 ( .A(intadd_44_A_2_), .B(intadd_44_B_2_), .C(
intadd_44_n12), .CO(intadd_44_n11), .S(intadd_44_SUM_2_) );
CMPR32X2TS intadd_44_U11 ( .A(intadd_44_A_3_), .B(intadd_44_B_3_), .C(
intadd_44_n11), .CO(intadd_44_n10), .S(intadd_44_SUM_3_) );
CMPR32X2TS intadd_44_U10 ( .A(intadd_44_A_4_), .B(intadd_44_B_4_), .C(
intadd_44_n10), .CO(intadd_44_n9), .S(intadd_44_SUM_4_) );
CMPR32X2TS intadd_44_U9 ( .A(intadd_44_A_5_), .B(intadd_44_B_5_), .C(
intadd_44_n9), .CO(intadd_44_n8), .S(intadd_44_SUM_5_) );
CMPR32X2TS intadd_44_U8 ( .A(intadd_44_A_6_), .B(intadd_44_B_6_), .C(
intadd_44_n8), .CO(intadd_44_n7), .S(intadd_44_SUM_6_) );
CMPR32X2TS intadd_44_U7 ( .A(intadd_44_A_7_), .B(intadd_44_B_7_), .C(
intadd_44_n7), .CO(intadd_44_n6), .S(intadd_44_SUM_7_) );
CMPR32X2TS intadd_44_U6 ( .A(intadd_44_A_8_), .B(intadd_44_B_8_), .C(
intadd_44_n6), .CO(intadd_44_n5), .S(intadd_44_SUM_8_) );
CMPR32X2TS intadd_44_U5 ( .A(intadd_44_A_9_), .B(intadd_44_B_9_), .C(
intadd_44_n5), .CO(intadd_44_n4), .S(intadd_44_SUM_9_) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n895), .CK(clk), .RN(n1700),
.QN(n1671) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n881), .CK(clk), .RN(n1696),
.QN(n1670) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n872), .CK(clk), .RN(n1693),
.QN(n1668) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n874), .CK(clk), .RN(n970),
.QN(n1667) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n886), .CK(clk), .RN(n1693),
.QN(n1666) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n864), .CK(clk), .RN(n1696),
.QN(n1665) );
DFFRXLTS Ready_reg_Q_reg_0_ ( .D(Shift_reg_FLAGS_7[0]), .CK(clk), .RN(n1698),
.Q(ready) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n613), .CK(clk), .RN(n1714), .Q(
zero_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n565), .CK(clk), .RN(n1717), .Q(
final_result_ieee[4]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n564), .CK(clk), .RN(n1700), .Q(
final_result_ieee[17]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n562), .CK(clk), .RN(n1699), .Q(
final_result_ieee[2]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n561), .CK(clk), .RN(n1720), .Q(
final_result_ieee[19]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n557), .CK(clk), .RN(n1719), .Q(
final_result_ieee[7]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n556), .CK(clk), .RN(n1708), .Q(
final_result_ieee[14]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n554), .CK(clk), .RN(n1700), .Q(
final_result_ieee[3]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n553), .CK(clk), .RN(n1718), .Q(
final_result_ieee[18]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n546), .CK(clk), .RN(n1699), .Q(
final_result_ieee[5]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n545), .CK(clk), .RN(n1717), .Q(
final_result_ieee[16]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n544), .CK(clk), .RN(n1714), .Q(
final_result_ieee[1]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n543), .CK(clk), .RN(n1699), .Q(
final_result_ieee[0]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n542), .CK(clk), .RN(n1720), .Q(
final_result_ieee[6]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n541), .CK(clk), .RN(n1719), .Q(
final_result_ieee[15]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n540), .CK(clk), .RN(n1708), .Q(
final_result_ieee[20]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n539), .CK(clk), .RN(n1700), .Q(
final_result_ieee[21]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n538), .CK(clk), .RN(n1709), .Q(
final_result_ieee[22]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n620), .CK(clk), .RN(n1715), .Q(
underflow_flag) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n619), .CK(clk), .RN(n1714), .Q(
overflow_flag) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n560), .CK(clk), .RN(n1711), .Q(
final_result_ieee[10]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n559), .CK(clk), .RN(n1694), .Q(
final_result_ieee[11]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n552), .CK(clk), .RN(n1722), .Q(
final_result_ieee[9]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n551), .CK(clk), .RN(n1717), .Q(
final_result_ieee[12]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n549), .CK(clk), .RN(n1718), .Q(
final_result_ieee[8]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n548), .CK(clk), .RN(n1711), .Q(
final_result_ieee[13]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n822), .CK(clk), .RN(n1721), .Q(
final_result_ieee[23]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n821), .CK(clk), .RN(n1699), .Q(
final_result_ieee[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n820), .CK(clk), .RN(n1720), .Q(
final_result_ieee[25]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n819), .CK(clk), .RN(n1719), .Q(
final_result_ieee[26]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n818), .CK(clk), .RN(n1708), .Q(
final_result_ieee[27]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n817), .CK(clk), .RN(n1700), .Q(
final_result_ieee[28]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n816), .CK(clk), .RN(n1718), .Q(
final_result_ieee[29]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n815), .CK(clk), .RN(n1711), .Q(
final_result_ieee[30]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n604), .CK(clk), .RN(n1694), .Q(
final_result_ieee[31]) );
DFFSX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n1006), .CK(clk), .SN(n1061), .Q(
n1724), .QN(Shift_reg_FLAGS_7[0]) );
DFFSX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1617), .CK(clk), .SN(n1062), .Q(
n1726), .QN(n1725) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n1696), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n1652) );
DFFRX2TS inst_ShiftRegister_Q_reg_6_ ( .D(n930), .CK(clk), .RN(n1693), .Q(
Shift_reg_FLAGS_7_6), .QN(n1624) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n929), .CK(clk), .RN(n1695), .Q(
Shift_reg_FLAGS_7_5), .QN(n1634) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n568), .CK(clk), .RN(n1710), .Q(
Raw_mant_NRM_SWR[6]), .QN(n1643) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n918), .CK(clk), .RN(n1696), .Q(
intDX_EWSW[5]), .QN(n1642) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n907), .CK(clk), .RN(n1717),
.Q(intDX_EWSW[16]), .QN(n1647) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n916), .CK(clk), .RN(n1695), .Q(
intDX_EWSW[7]), .QN(n1623) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n917), .CK(clk), .RN(n970), .Q(
intDX_EWSW[6]), .QN(n1644) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n919), .CK(clk), .RN(n1713), .Q(
intDX_EWSW[4]), .QN(n1621) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n862), .CK(clk), .RN(n1716),
.Q(intDY_EWSW[27]), .QN(n1662) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n870), .CK(clk), .RN(n1695),
.Q(intDY_EWSW[19]), .QN(n1674) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n877), .CK(clk), .RN(n1695),
.Q(intDY_EWSW[12]), .QN(n1660) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n882), .CK(clk), .RN(n1696), .Q(
intDY_EWSW[7]), .QN(n1663) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n884), .CK(clk), .RN(n971), .Q(
intDY_EWSW[5]), .QN(n1626) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n885), .CK(clk), .RN(n1698), .Q(
intDY_EWSW[4]), .QN(n1659) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n866), .CK(clk), .RN(n1698),
.Q(intDY_EWSW[23]), .QN(n1672) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n601), .CK(clk), .RN(n1699), .Q(
Raw_mant_NRM_SWR[14]), .QN(n1636) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n828), .CK(clk), .RN(n1705), .Q(
shift_value_SHT2_EWR[4]), .QN(n1655) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n599), .CK(clk), .RN(n1712), .Q(
Raw_mant_NRM_SWR[16]), .QN(n1679) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n844), .CK(clk), .RN(n1694), .Q(
Data_array_SWR[12]), .QN(n1684) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n854), .CK(clk), .RN(n1693), .Q(
Data_array_SWR[22]), .QN(n1678) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n846), .CK(clk), .RN(n1720), .Q(
Data_array_SWR[14]), .QN(n1685) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n672), .CK(clk), .RN(n1062), .Q(
DMP_exp_NRM2_EW[7]), .QN(n1680) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n677), .CK(clk), .RN(n1061), .Q(
DMP_exp_NRM2_EW[6]), .QN(n1675) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n682), .CK(clk), .RN(n1716), .Q(
DMP_exp_NRM2_EW[5]), .QN(n1664) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n707), .CK(clk), .RN(n1723), .Q(
DMP_exp_NRM2_EW[0]), .QN(n1646) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n575), .CK(clk), .RN(n1700), .Q(
Raw_mant_NRM_SWR[2]), .QN(n1641) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n574), .CK(clk), .RN(n1709), .Q(
Raw_mant_NRM_SWR[3]), .QN(n1677) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n859), .CK(clk), .RN(n1693),
.Q(intDY_EWSW[30]), .QN(n1649) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n860), .CK(clk), .RN(n1695),
.Q(intDY_EWSW[29]), .QN(n1625) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n894), .CK(clk), .RN(n1695),
.Q(intDX_EWSW[29]), .QN(n1673) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n897), .CK(clk), .RN(n1698),
.Q(intDX_EWSW[26]), .QN(n1633) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n898), .CK(clk), .RN(n1698),
.Q(intDX_EWSW[25]), .QN(n1632) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n899), .CK(clk), .RN(n1714),
.Q(intDX_EWSW[24]), .QN(n1682) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n581), .CK(clk), .RN(n1715), .Q(
Raw_mant_NRM_SWR[9]), .QN(n1653) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n580), .CK(clk), .RN(n1709), .Q(
Raw_mant_NRM_SWR[10]), .QN(n1640) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n603), .CK(clk), .RN(n1707), .Q(
Raw_mant_NRM_SWR[12]), .QN(n1638) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n588), .CK(clk), .RN(n1717), .Q(
Raw_mant_NRM_SWR[11]), .QN(n1637) );
DFFRX1TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n830), .CK(clk), .RN(n1696), .Q(
shift_value_SHT2_EWR[3]), .QN(n1645) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n598), .CK(clk), .RN(n1708), .Q(
Raw_mant_NRM_SWR[17]), .QN(n1654) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n789), .CK(clk), .RN(n1703), .Q(
DMP_EXP_EWSW[25]), .QN(n1676) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n790), .CK(clk), .RN(n1702), .Q(
DMP_EXP_EWSW[24]), .QN(n1619) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n788), .CK(clk), .RN(n1705), .Q(
DMP_EXP_EWSW[26]), .QN(n1683) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n623), .CK(clk), .RN(n1711), .Q(
DmP_EXP_EWSW[25]), .QN(n1686) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n624), .CK(clk), .RN(n1716), .Q(
DmP_EXP_EWSW[24]), .QN(n1631) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n622), .CK(clk), .RN(n1714), .Q(
DmP_EXP_EWSW[26]), .QN(n1681) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n842), .CK(clk), .RN(n1719), .Q(
Data_array_SWR[10]), .QN(n1687) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n594), .CK(clk), .RN(n1699), .Q(
Raw_mant_NRM_SWR[21]), .QN(n1648) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n593), .CK(clk), .RN(n1713), .Q(
Raw_mant_NRM_SWR[22]), .QN(n1620) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n852), .CK(clk), .RN(n1700), .Q(
Data_array_SWR[20]), .QN(n1688) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n591), .CK(clk), .RN(n1723), .Q(
Raw_mant_NRM_SWR[24]), .QN(n1618) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n590), .CK(clk), .RN(n1720), .Q(
Raw_mant_NRM_SWR[25]), .QN(n1635) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n920), .CK(clk), .RN(n1718), .Q(
intDX_EWSW[3]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n900), .CK(clk), .RN(n1698),
.Q(intDX_EWSW[23]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n902), .CK(clk), .RN(n1693),
.Q(intDX_EWSW[21]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n910), .CK(clk), .RN(n1693),
.Q(intDX_EWSW[13]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n908), .CK(clk), .RN(n1695),
.Q(intDX_EWSW[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n855), .CK(clk), .RN(n1721), .Q(
Data_array_SWR[23]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n856), .CK(clk), .RN(n1696), .Q(
Data_array_SWR[24]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n915), .CK(clk), .RN(n1696), .Q(
intDX_EWSW[8]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n595), .CK(clk), .RN(n1714), .Q(
Raw_mant_NRM_SWR[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n906), .CK(clk), .RN(n1696),
.Q(intDX_EWSW[17]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_3_ ( .D(n769), .CK(clk), .RN(n1706), .Q(
DMP_SFG[3]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n857), .CK(clk), .RN(n970), .Q(
Data_array_SWR[25]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n914), .CK(clk), .RN(n1698), .Q(
intDX_EWSW[9]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n896), .CK(clk), .RN(n1693),
.Q(intDX_EWSW[27]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n912), .CK(clk), .RN(n1696),
.Q(intDX_EWSW[11]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n602), .CK(clk), .RN(n1723), .Q(
Raw_mant_NRM_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n569), .CK(clk), .RN(n1699), .Q(
Raw_mant_NRM_SWR[5]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n847), .CK(clk), .RN(n1693), .Q(
Data_array_SWR[15]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n845), .CK(clk), .RN(n1708), .Q(
Data_array_SWR[13]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n600), .CK(clk), .RN(n1719), .Q(
Raw_mant_NRM_SWR[15]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n923), .CK(clk), .RN(n971), .Q(
intDX_EWSW[0]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n596), .CK(clk), .RN(n1722), .Q(
Raw_mant_NRM_SWR[19]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n582), .CK(clk), .RN(n1709), .Q(
Raw_mant_NRM_SWR[8]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n905), .CK(clk), .RN(n970), .Q(
intDX_EWSW[18]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n585), .CK(clk), .RN(n1697), .Q(
Raw_mant_NRM_SWR[1]) );
DFFRX2TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n932), .CK(clk), .RN(
n1698), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n831), .CK(clk), .RN(n1695), .Q(
shift_value_SHT2_EWR[2]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n840), .CK(clk), .RN(n1692), .Q(
Data_array_SWR[8]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n850), .CK(clk), .RN(n1695), .Q(
Data_array_SWR[18]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n848), .CK(clk), .RN(n1696), .Q(
Data_array_SWR[16]) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n597), .CK(clk), .RN(n1707), .Q(
Raw_mant_NRM_SWR[18]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n863), .CK(clk), .RN(n1697),
.QN(n1689) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n836), .CK(clk), .RN(n1697), .Q(
Data_array_SWR[4]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n837), .CK(clk), .RN(n1721), .Q(
Data_array_SWR[5]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n838), .CK(clk), .RN(n1718), .Q(
Data_array_SWR[6]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n839), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[7]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n592), .CK(clk), .RN(n1712), .Q(
Raw_mant_NRM_SWR[23]), .QN(n938) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_5_ ( .D(n763), .CK(clk), .RN(n1702), .Q(
DMP_SFG[5]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_1_ ( .D(n775), .CK(clk), .RN(n1701), .Q(
DMP_SFG[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_6_ ( .D(n760), .CK(clk), .RN(n1705), .Q(
DMP_SFG[6]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_7_ ( .D(n757), .CK(clk), .RN(n971), .Q(
DMP_SFG[7]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n892), .CK(clk), .RN(n1715),
.Q(intDX_EWSW[31]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_9_ ( .D(n751), .CK(clk), .RN(n1701), .Q(
DMP_SFG[9]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n570), .CK(clk), .RN(n1700), .Q(
Raw_mant_NRM_SWR[4]), .QN(n941) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n883), .CK(clk), .RN(n1698), .Q(
intDY_EWSW[6]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n865), .CK(clk), .RN(n1695),
.Q(intDY_EWSW[24]) );
DFFRX1TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n893), .CK(clk), .RN(n1717),
.Q(intDX_EWSW[30]), .QN(n950) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n626), .CK(clk), .RN(n1710), .Q(
DmP_mant_SHT1_SW[22]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n636), .CK(clk), .RN(n1712), .Q(
DmP_mant_SHT1_SW[17]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n638), .CK(clk), .RN(n1718), .Q(
DmP_mant_SHT1_SW[16]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n656), .CK(clk), .RN(n1717), .Q(
DmP_mant_SHT1_SW[7]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n664), .CK(clk), .RN(n1714), .Q(
DmP_mant_SHT1_SW[3]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n634), .CK(clk), .RN(n1722), .Q(
DmP_mant_SHT1_SW[18]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n646), .CK(clk), .RN(n1709), .Q(
DmP_mant_SHT1_SW[12]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n650), .CK(clk), .RN(n1712), .Q(
DmP_mant_SHT1_SW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n630), .CK(clk), .RN(n1720), .Q(
DmP_mant_SHT1_SW[20]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n642), .CK(clk), .RN(n1710), .Q(
DmP_mant_SHT1_SW[14]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n628), .CK(clk), .RN(n1711), .Q(
DmP_mant_SHT1_SW[21]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n652), .CK(clk), .RN(n1697), .Q(
DmP_mant_SHT1_SW[9]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n658), .CK(clk), .RN(n1699), .Q(
DmP_mant_SHT1_SW[6]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n666), .CK(clk), .RN(n1707), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_4_ ( .D(n766), .CK(clk), .RN(n1060), .Q(
DMP_SFG[4]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_2_ ( .D(n772), .CK(clk), .RN(n1704), .Q(
DMP_SFG[2]) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n928), .CK(clk), .RN(n1723), .Q(
n1729), .QN(n1728) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n827), .CK(clk), .RN(n1693),
.Q(Shift_amount_SHT1_EWR[0]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_8_ ( .D(n754), .CK(clk), .RN(n1704), .Q(
DMP_SFG[8]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n550), .CK(clk), .RN(n1708), .Q(
DmP_mant_SFG_SWR[10]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n589), .CK(clk), .RN(n1697), .Q(
DmP_mant_SFG_SWR[11]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n534), .CK(clk), .RN(n1716), .Q(
DmP_mant_SFG_SWR[15]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n535), .CK(clk), .RN(n1723), .Q(
DmP_mant_SFG_SWR[14]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n536), .CK(clk), .RN(n1692), .Q(
DmP_mant_SFG_SWR[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n537), .CK(clk), .RN(n1721), .Q(
DmP_mant_SFG_SWR[12]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_0_ ( .D(n778), .CK(clk), .RN(n1703), .Q(
DMP_SFG[0]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n791), .CK(clk), .RN(n1060), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n692), .CK(clk), .RN(n1697), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n697), .CK(clk), .RN(n1715), .Q(
DMP_exp_NRM2_EW[2]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n702), .CK(clk), .RN(n1713), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n712), .CK(clk), .RN(n1715), .QN(n1009) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n715), .CK(clk), .RN(n1713), .QN(n1007) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n718), .CK(clk), .RN(n1697), .QN(n1010) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n889), .CK(clk), .RN(n1708), .Q(
intDY_EWSW[0]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n911), .CK(clk), .RN(n1695),
.Q(intDX_EWSW[12]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n903), .CK(clk), .RN(n1698),
.Q(intDX_EWSW[20]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n909), .CK(clk), .RN(n1715),
.Q(intDX_EWSW[14]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n901), .CK(clk), .RN(n1711),
.Q(intDX_EWSW[22]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n922), .CK(clk), .RN(n1714), .Q(
intDX_EWSW[1]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n921), .CK(clk), .RN(n971), .Q(
intDX_EWSW[2]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n861), .CK(clk), .RN(n1698),
.Q(intDY_EWSW[28]) );
DFFRX2TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n904), .CK(clk), .RN(n1693),
.Q(intDX_EWSW[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n841), .CK(clk), .RN(n1717), .Q(
Data_array_SWR[9]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n843), .CK(clk), .RN(n1715), .Q(
Data_array_SWR[11]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n851), .CK(clk), .RN(n971), .Q(
Data_array_SWR[19]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n849), .CK(clk), .RN(n1698), .Q(
Data_array_SWR[17]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n853), .CK(clk), .RN(n1695), .Q(
Data_array_SWR[21]) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n577), .CK(clk), .RN(n1719), .Q(
Raw_mant_NRM_SWR[0]) );
DFFRX2TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n878), .CK(clk), .RN(n1713),
.QN(n1691) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n876), .CK(clk), .RN(n1719),
.Q(intDY_EWSW[13]), .QN(n1690) );
DFFRXLTS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n869), .CK(clk), .RN(n1709),
.Q(intDY_EWSW[20]), .QN(n1661) );
DFFRX1TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n931), .CK(clk), .RN(
n1720), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n1629) );
DFFRX1TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n567), .CK(clk), .RN(n1694), .Q(
Raw_mant_NRM_SWR[7]), .QN(n1639) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n875), .CK(clk), .RN(n1713),
.Q(intDY_EWSW[14]), .QN(n1627) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n867), .CK(clk), .RN(n1696),
.Q(intDY_EWSW[22]), .QN(n1628) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n640), .CK(clk), .RN(n1710), .Q(
DmP_mant_SHT1_SW[15]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n632), .CK(clk), .RN(n1692), .Q(
DmP_mant_SHT1_SW[19]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n583), .CK(clk), .RN(n1719), .Q(
DmP_mant_SFG_SWR[8]), .QN(n1015) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n571), .CK(clk), .RN(n1713), .Q(
DmP_mant_SFG_SWR[3]), .QN(n1012) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n558), .CK(clk), .RN(n1717), .Q(
DmP_mant_SFG_SWR[9]), .QN(n1017) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n625), .CK(clk), .RN(n1697), .Q(
DmP_EXP_EWSW[23]), .QN(n1008) );
DFFRX1TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n891), .CK(clk), .RN(n1706), .Q(
intAS) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n879), .CK(clk), .RN(n1715),
.Q(intDY_EWSW[10]) );
DFFRX1TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n687), .CK(clk), .RN(n1692), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n868), .CK(clk), .RN(n1694),
.Q(intDY_EWSW[21]), .QN(n1658) );
DFFRX1TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n858), .CK(clk), .RN(n1696),
.Q(intDY_EWSW[31]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n832), .CK(clk), .RN(n1698), .Q(
Data_array_SWR[0]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n835), .CK(clk), .RN(n1693), .Q(
Data_array_SWR[3]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n834), .CK(clk), .RN(n1695), .Q(
Data_array_SWR[2]) );
DFFRX1TS SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n833), .CK(clk), .RN(n1696), .Q(
Data_array_SWR[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n621), .CK(clk), .RN(n1699), .Q(
DmP_EXP_EWSW[27]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n586), .CK(clk), .RN(n1713), .Q(
DmP_mant_SFG_SWR[1]), .QN(n1028) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n578), .CK(clk), .RN(n1712), .Q(
DmP_mant_SFG_SWR[0]), .QN(n1030) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n533), .CK(clk), .RN(n1713), .Q(
DmP_mant_SFG_SWR[16]), .QN(n1018) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n532), .CK(clk), .RN(n1716), .Q(
DmP_mant_SFG_SWR[17]), .QN(n1016) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n531), .CK(clk), .RN(n1723), .Q(
DmP_mant_SFG_SWR[18]), .QN(n1021) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n530), .CK(clk), .RN(n1697), .Q(
DmP_mant_SFG_SWR[19]), .QN(n1020) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n529), .CK(clk), .RN(n1715), .Q(
DmP_mant_SFG_SWR[20]), .QN(n1025) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n528), .CK(clk), .RN(n1713), .Q(
DmP_mant_SFG_SWR[21]), .QN(n1024) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n527), .CK(clk), .RN(n1707), .Q(
DmP_mant_SFG_SWR[22]), .QN(n1011) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n526), .CK(clk), .RN(n1694), .Q(
DmP_mant_SFG_SWR[23]), .QN(n1013) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n525), .CK(clk), .RN(n1722), .Q(
DmP_mant_SFG_SWR[24]), .QN(n1027) );
DFFRXLTS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n547), .CK(clk), .RN(n1714), .Q(
DmP_mant_SFG_SWR[7]), .QN(n1022) );
ADDFX1TS DP_OP_15J39_125_2314_U8 ( .A(n1650), .B(DMP_exp_NRM2_EW[1]), .CI(
DP_OP_15J39_125_2314_n8), .CO(DP_OP_15J39_125_2314_n7), .S(
exp_rslt_NRM2_EW1[1]) );
ADDFX1TS DP_OP_15J39_125_2314_U7 ( .A(n1651), .B(DMP_exp_NRM2_EW[2]), .CI(
DP_OP_15J39_125_2314_n7), .CO(DP_OP_15J39_125_2314_n6), .S(
exp_rslt_NRM2_EW1[2]) );
ADDFX1TS DP_OP_15J39_125_2314_U6 ( .A(n1657), .B(DMP_exp_NRM2_EW[3]), .CI(
DP_OP_15J39_125_2314_n6), .CO(DP_OP_15J39_125_2314_n5), .S(
exp_rslt_NRM2_EW1[3]) );
ADDFX1TS intadd_44_U3 ( .A(n1007), .B(intadd_44_B_11_), .CI(intadd_44_n3),
.CO(intadd_44_n2), .S(intadd_44_SUM_11_) );
ADDFX1TS intadd_44_U2 ( .A(n1009), .B(intadd_44_B_12_), .CI(intadd_44_n2),
.CO(intadd_44_n1), .S(intadd_44_SUM_12_) );
DFFRX4TS SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n610), .CK(clk), .RN(n1707), .Q(
OP_FLAG_SFG), .QN(n1622) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n925), .CK(clk), .RN(n1695), .Q(
Shift_reg_FLAGS_7[1]), .QN(n946) );
CMPR32X2TS DP_OP_15J39_125_2314_U5 ( .A(n1656), .B(DMP_exp_NRM2_EW[4]), .C(
DP_OP_15J39_125_2314_n5), .CO(DP_OP_15J39_125_2314_n4), .S(
exp_rslt_NRM2_EW1[4]) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n890), .CK(clk), .RN(n1693), .Q(
left_right_SHT2), .QN(n934) );
CMPR32X2TS intadd_44_U4 ( .A(n1010), .B(intadd_44_B_10_), .C(intadd_44_n4),
.CO(intadd_44_n3), .S(intadd_44_SUM_10_) );
AOI222X1TS U940 ( .A0(n1163), .A1(left_right_SHT2), .B0(Data_array_SWR[8]),
.B1(n994), .C0(n1162), .C1(n1158), .Y(n1603) );
AOI222X1TS U941 ( .A0(n1163), .A1(n934), .B0(n957), .B1(Data_array_SWR[8]),
.C0(n1162), .C1(n1161), .Y(n1522) );
AOI211X1TS U942 ( .A0(DmP_mant_SHT1_SW[22]), .A1(n946), .B0(n1462), .C0(
n1449), .Y(n1456) );
CMPR32X2TS U943 ( .A(DMP_SFG[6]), .B(n1524), .C(n1523), .CO(n1529), .S(n1526) );
AOI222X2TS U944 ( .A0(Data_array_SWR[22]), .A1(n1582), .B0(
Data_array_SWR[14]), .B1(n1078), .C0(Data_array_SWR[18]), .C1(n998),
.Y(n1586) );
BUFX3TS U945 ( .A(n1345), .Y(n972) );
OAI211X1TS U946 ( .A0(DMP_SFG[7]), .A1(n1528), .B0(n1532), .C0(n1498), .Y(
n1499) );
BUFX3TS U947 ( .A(n1255), .Y(n933) );
CLKAND2X4TS U948 ( .A(Shift_amount_SHT1_EWR[0]), .B(n1450), .Y(n1340) );
CLKBUFX2TS U949 ( .A(n1690), .Y(n1001) );
CLKBUFX2TS U950 ( .A(n1661), .Y(n992) );
INVX1TS U951 ( .A(LZD_output_NRM2_EW[0]), .Y(n1412) );
AOI222X1TS U952 ( .A0(Raw_mant_NRM_SWR[7]), .A1(n1448), .B0(n1002), .B1(
DmP_mant_SHT1_SW[16]), .C0(n1340), .C1(DmP_mant_SHT1_SW[17]), .Y(n1400) );
AOI222X1TS U953 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1466), .B0(n1003), .B1(
DmP_mant_SHT1_SW[6]), .C0(n1340), .C1(DmP_mant_SHT1_SW[7]), .Y(n1406)
);
AOI222X1TS U954 ( .A0(Raw_mant_NRM_SWR[10]), .A1(n1448), .B0(n1003), .B1(
n978), .C0(n1462), .C1(DmP_mant_SHT1_SW[14]), .Y(n1381) );
NOR2X1TS U955 ( .A(n1347), .B(n1464), .Y(n1348) );
INVX3TS U956 ( .A(n1454), .Y(n1466) );
INVX3TS U957 ( .A(n1454), .Y(n1448) );
NAND2X4TS U958 ( .A(n1333), .B(n1470), .Y(n1334) );
AOI31X1TS U959 ( .A0(n1052), .A1(Raw_mant_NRM_SWR[8]), .A2(n1653), .B0(n1180), .Y(n1053) );
INVX3TS U960 ( .A(n933), .Y(n1481) );
INVX3TS U961 ( .A(n933), .Y(n1314) );
INVX3TS U962 ( .A(n1294), .Y(n1480) );
ADDFX1TS U963 ( .A(DMP_SFG[7]), .B(n1529), .CI(n1528), .CO(n1531), .S(n1530)
);
INVX3TS U964 ( .A(n1294), .Y(n1285) );
NOR2X4TS U965 ( .A(n1254), .B(n1624), .Y(n1255) );
AO21X1TS U966 ( .A0(n1047), .A1(Raw_mant_NRM_SWR[18]), .B0(n1171), .Y(n1048)
);
XOR2XLTS U967 ( .A(n1556), .B(n1559), .Y(n1557) );
AOI211XLTS U968 ( .A0(n990), .A1(n1647), .B0(n1239), .C0(n1240), .Y(n1231)
);
OR2X4TS U969 ( .A(n959), .B(n1490), .Y(n1470) );
CLKBUFX3TS U970 ( .A(n1078), .Y(n995) );
INVX3TS U971 ( .A(n945), .Y(n1003) );
NAND2X4TS U972 ( .A(beg_OP), .B(n1429), .Y(n1430) );
OAI211X2TS U973 ( .A0(intDX_EWSW[20]), .A1(n992), .B0(n1245), .C0(n1230),
.Y(n1239) );
OAI211X2TS U974 ( .A0(intDX_EWSW[12]), .A1(n1660), .B0(n1225), .C0(n1211),
.Y(n1227) );
NAND2X4TS U975 ( .A(n976), .B(n1724), .Y(n1485) );
INVX3TS U976 ( .A(OP_FLAG_SFG), .Y(n1538) );
NOR2X4TS U977 ( .A(shift_value_SHT2_EWR[4]), .B(n1117), .Y(n1078) );
INVX3TS U978 ( .A(OP_FLAG_SFG), .Y(n1520) );
CLKBUFX2TS U979 ( .A(n1026), .Y(n974) );
CLKBUFX3TS U980 ( .A(n1726), .Y(n1568) );
INVX4TS U981 ( .A(n1729), .Y(n975) );
INVX4TS U982 ( .A(rst), .Y(n971) );
NAND2X1TS U983 ( .A(n1164), .B(n1636), .Y(n1033) );
AOI31XLTS U984 ( .A0(n1047), .A1(Raw_mant_NRM_SWR[16]), .A2(n1654), .B0(
n1046), .Y(n1054) );
NAND2X1TS U985 ( .A(n1328), .B(n941), .Y(n1178) );
AOI2BB2XLTS U986 ( .B0(DmP_mant_SFG_SWR[13]), .B1(n1520), .A0N(n1622), .A1N(
DmP_mant_SFG_SWR[13]), .Y(intadd_44_B_1_) );
NAND2X1TS U987 ( .A(n1050), .B(n1637), .Y(n1034) );
CLKAND2X2TS U988 ( .A(n1166), .B(n1167), .Y(n1164) );
NOR2X1TS U989 ( .A(Raw_mant_NRM_SWR[10]), .B(n1034), .Y(n1052) );
OAI21XLTS U990 ( .A0(Raw_mant_NRM_SWR[3]), .A1(n1641), .B0(n941), .Y(n1049)
);
NOR2XLTS U991 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .Y(n1037)
);
AOI222X1TS U992 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1448), .B0(n1003), .B1(
DmP_mant_SHT1_SW[17]), .C0(n1340), .C1(DmP_mant_SHT1_SW[18]), .Y(n1385) );
AOI222X1TS U993 ( .A0(Raw_mant_NRM_SWR[14]), .A1(n1448), .B0(n1003), .B1(
DmP_mant_SHT1_SW[9]), .C0(n1340), .C1(DmP_mant_SHT1_SW[10]), .Y(n1371)
);
AOI222X1TS U994 ( .A0(Raw_mant_NRM_SWR[16]), .A1(n1448), .B0(n1003), .B1(
DmP_mant_SHT1_SW[7]), .C0(n1340), .C1(n980), .Y(n1374) );
AOI222X1TS U995 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n1448), .B0(n1003), .B1(
DmP_mant_SHT1_SW[3]), .C0(n1340), .C1(n977), .Y(n1354) );
AOI222X1TS U996 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1466), .B0(n1003), .B1(
DmP_mant_SHT1_SW[2]), .C0(n1340), .C1(DmP_mant_SHT1_SW[3]), .Y(n1366)
);
AOI2BB2XLTS U997 ( .B0(DmP_mant_SFG_SWR[15]), .B1(n1520), .A0N(n1622), .A1N(
DmP_mant_SFG_SWR[15]), .Y(intadd_44_B_3_) );
AOI222X1TS U998 ( .A0(Raw_mant_NRM_SWR[12]), .A1(n1448), .B0(n1003), .B1(
n979), .C0(n1340), .C1(DmP_mant_SHT1_SW[12]), .Y(n1384) );
AOI222X1TS U999 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1448), .B0(n1002), .B1(
DmP_mant_SHT1_SW[21]), .C0(n1340), .C1(DmP_mant_SHT1_SW[22]), .Y(n1393) );
AOI2BB2XLTS U1000 ( .B0(DmP_mant_SFG_SWR[12]), .B1(n1520), .A0N(n1622),
.A1N(DmP_mant_SFG_SWR[12]), .Y(intadd_44_CI) );
OAI21XLTS U1001 ( .A0(n1653), .A1(n1454), .B0(n1397), .Y(n1398) );
NAND2BXLTS U1002 ( .AN(intDX_EWSW[2]), .B(n988), .Y(n1202) );
AOI2BB2XLTS U1003 ( .B0(intDX_EWSW[3]), .B1(n1666), .A0N(n988), .A1N(n1204),
.Y(n1205) );
NAND2BXLTS U1004 ( .AN(n986), .B(intDX_EWSW[9]), .Y(n1217) );
NAND3XLTS U1005 ( .A(n1670), .B(n1215), .C(intDX_EWSW[8]), .Y(n1216) );
NAND2BXLTS U1006 ( .AN(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n1236) );
NAND2BXLTS U1007 ( .AN(intDX_EWSW[27]), .B(intDY_EWSW[27]), .Y(n1189) );
NAND2BXLTS U1008 ( .AN(intDX_EWSW[9]), .B(n986), .Y(n1215) );
OAI2BB2XLTS U1009 ( .B0(intDY_EWSW[12]), .B1(n1212), .A0N(intDX_EWSW[13]),
.A1N(n1001), .Y(n1224) );
NAND2BXLTS U1010 ( .AN(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n1211) );
NAND2BXLTS U1011 ( .AN(intDX_EWSW[21]), .B(intDY_EWSW[21]), .Y(n1230) );
NOR2XLTS U1012 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n1038) );
AOI221X1TS U1013 ( .A0(n1660), .A1(intDX_EWSW[12]), .B0(intDX_EWSW[13]),
.B1(n1001), .C0(n1095), .Y(n1098) );
OAI211XLTS U1014 ( .A0(n1192), .A1(n1249), .B0(n1191), .C0(n1190), .Y(n1197)
);
NAND2BXLTS U1015 ( .AN(intDY_EWSW[27]), .B(intDX_EWSW[27]), .Y(n1190) );
NAND3XLTS U1016 ( .A(n1689), .B(n1189), .C(intDX_EWSW[26]), .Y(n1191) );
NAND2BXLTS U1017 ( .AN(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n1246) );
NAND3BXLTS U1018 ( .AN(n1234), .B(n1232), .C(n1231), .Y(n1252) );
AOI222X4TS U1019 ( .A0(Data_array_SWR[21]), .A1(n1155), .B0(
Data_array_SWR[17]), .B1(n1154), .C0(Data_array_SWR[25]), .C1(n1153),
.Y(n1518) );
AOI222X1TS U1020 ( .A0(n1494), .A1(DMP_SFG[5]), .B0(n1494), .B1(n973), .C0(
DMP_SFG[5]), .C1(n973), .Y(n1495) );
AOI222X1TS U1021 ( .A0(n1560), .A1(n1493), .B0(n1560), .B1(DMP_SFG[3]), .C0(
n1493), .C1(DMP_SFG[3]), .Y(n1496) );
AOI222X4TS U1022 ( .A0(Data_array_SWR[21]), .A1(n998), .B0(
Data_array_SWR[17]), .B1(n1078), .C0(Data_array_SWR[25]), .C1(n1582),
.Y(n1575) );
NAND2BXLTS U1023 ( .AN(n1129), .B(n1420), .Y(n1130) );
NAND3XLTS U1024 ( .A(n1419), .B(exp_rslt_NRM2_EW1[4]), .C(n1128), .Y(n1129)
);
NOR2XLTS U1025 ( .A(n1418), .B(exp_rslt_NRM2_EW1[1]), .Y(n1121) );
AOI31XLTS U1026 ( .A0(n1638), .A1(Raw_mant_NRM_SWR[11]), .A2(n1050), .B0(
n1048), .Y(n1043) );
NAND2BXLTS U1027 ( .AN(n1177), .B(Raw_mant_NRM_SWR[5]), .Y(n1323) );
AOI221X1TS U1028 ( .A0(n992), .A1(intDX_EWSW[20]), .B0(intDX_EWSW[21]), .B1(
n1439), .C0(n1088), .Y(n1091) );
INVX2TS U1029 ( .A(n958), .Y(n959) );
NAND3XLTS U1030 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1652), .C(
n1629), .Y(n1424) );
INVX2TS U1031 ( .A(n1470), .Y(n1380) );
OAI21XLTS U1032 ( .A0(n1636), .A1(n1464), .B0(n1403), .Y(n1404) );
CLKAND2X2TS U1033 ( .A(n1491), .B(DMP_SFG[8]), .Y(n1511) );
CLKAND2X2TS U1034 ( .A(n1183), .B(DMP_SFG[0]), .Y(n1544) );
OAI21XLTS U1035 ( .A0(n1677), .A1(n1454), .B0(n1453), .Y(n1455) );
AO22XLTS U1036 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1448), .B0(
Raw_mant_NRM_SWR[0]), .B1(n1452), .Y(n1449) );
OAI21XLTS U1037 ( .A0(n1640), .A1(n1464), .B0(n1459), .Y(n1460) );
OAI21XLTS U1038 ( .A0(n1638), .A1(n1464), .B0(n1463), .Y(n1465) );
AOI2BB2XLTS U1039 ( .B0(DmP_mant_SFG_SWR[14]), .B1(n1520), .A0N(n1538),
.A1N(DmP_mant_SFG_SWR[14]), .Y(intadd_44_B_2_) );
CLKAND2X2TS U1040 ( .A(n1680), .B(n1132), .Y(n1133) );
NOR2XLTS U1041 ( .A(n1409), .B(n1130), .Y(n1134) );
OR2X1TS U1042 ( .A(n1126), .B(n1127), .Y(n1482) );
NAND2BXLTS U1043 ( .AN(n1420), .B(n1123), .Y(n1126) );
NAND4BXLTS U1044 ( .AN(exp_rslt_NRM2_EW1[4]), .B(n1121), .C(n1120), .D(n1119), .Y(n1122) );
AOI222X1TS U1045 ( .A0(n1142), .A1(n965), .B0(Data_array_SWR[9]), .B1(n994),
.C0(n1141), .C1(n1158), .Y(n1602) );
NAND4XLTS U1046 ( .A(n1169), .B(n1174), .C(n1329), .D(n1168), .Y(n1170) );
OAI21XLTS U1047 ( .A0(n1325), .A1(n1324), .B0(n1323), .Y(n1326) );
CLKINVX3TS U1048 ( .A(n1477), .Y(n1488) );
INVX2TS U1049 ( .A(n1430), .Y(n1444) );
AO22XLTS U1050 ( .A0(n1446), .A1(Data_Y[31]), .B0(n1445), .B1(intDY_EWSW[31]), .Y(n858) );
AO22XLTS U1051 ( .A0(n1441), .A1(add_subt), .B0(n1445), .B1(intAS), .Y(n891)
);
AO22XLTS U1052 ( .A0(n1486), .A1(DmP_EXP_EWSW[19]), .B0(n1488), .B1(
DmP_mant_SHT1_SW[19]), .Y(n632) );
OAI21XLTS U1053 ( .A0(n1565), .A1(n1564), .B0(n1563), .Y(n1566) );
OAI211XLTS U1054 ( .A0(n1385), .A1(n1334), .B0(n1370), .C0(n1369), .Y(n851)
);
AOI2BB2XLTS U1055 ( .B0(Raw_mant_NRM_SWR[5]), .B1(n1395), .A0N(n1377), .A1N(
n1345), .Y(n1369) );
AOI2BB2XLTS U1056 ( .B0(Raw_mant_NRM_SWR[13]), .B1(n1395), .A0N(n1384),
.A1N(n1345), .Y(n1367) );
OAI211XLTS U1057 ( .A0(n1374), .A1(n1334), .B0(n1373), .C0(n1372), .Y(n841)
);
AOI2BB2XLTS U1058 ( .B0(Raw_mant_NRM_SWR[15]), .B1(n1395), .A0N(n1371),
.A1N(n1345), .Y(n1372) );
AO22XLTS U1059 ( .A0(n1442), .A1(Data_X[19]), .B0(n1445), .B1(intDX_EWSW[19]), .Y(n904) );
AO22XLTS U1060 ( .A0(n1444), .A1(Data_Y[28]), .B0(n1445), .B1(intDY_EWSW[28]), .Y(n861) );
AO22XLTS U1061 ( .A0(n1442), .A1(Data_X[2]), .B0(n1430), .B1(intDX_EWSW[2]),
.Y(n921) );
AO22XLTS U1062 ( .A0(n1446), .A1(Data_X[1]), .B0(n1430), .B1(intDX_EWSW[1]),
.Y(n922) );
AO22XLTS U1063 ( .A0(n1441), .A1(Data_X[22]), .B0(n1445), .B1(intDX_EWSW[22]), .Y(n901) );
AO22XLTS U1064 ( .A0(n1446), .A1(Data_X[14]), .B0(n1431), .B1(intDX_EWSW[14]), .Y(n909) );
AO22XLTS U1065 ( .A0(n961), .A1(Data_X[20]), .B0(n1445), .B1(intDX_EWSW[20]),
.Y(n903) );
AO22XLTS U1066 ( .A0(n1441), .A1(Data_X[12]), .B0(n1431), .B1(intDX_EWSW[12]), .Y(n911) );
OAI21XLTS U1067 ( .A0(n1672), .A1(n1314), .B0(n1287), .Y(n791) );
AO22XLTS U1068 ( .A0(n1600), .A1(DMP_SHT2_EWSW[0]), .B0(n1598), .B1(
DMP_SFG[0]), .Y(n778) );
AO22XLTS U1069 ( .A0(n1614), .A1(DmP_mant_SFG_SWR[12]), .B0(n1475), .B1(
n1595), .Y(n537) );
AO22XLTS U1070 ( .A0(n1601), .A1(DmP_mant_SFG_SWR[13]), .B0(n1600), .B1(
n1596), .Y(n536) );
AO22XLTS U1071 ( .A0(n1598), .A1(DmP_mant_SFG_SWR[14]), .B0(n1475), .B1(
n1597), .Y(n535) );
AO22XLTS U1072 ( .A0(n1601), .A1(DmP_mant_SFG_SWR[15]), .B0(n1600), .B1(
n1599), .Y(n534) );
AO22XLTS U1073 ( .A0(n1475), .A1(n1578), .B0(n1598), .B1(
DmP_mant_SFG_SWR[11]), .Y(n589) );
AO22XLTS U1074 ( .A0(n1601), .A1(DmP_mant_SFG_SWR[10]), .B0(n1600), .B1(
n1584), .Y(n550) );
AO22XLTS U1075 ( .A0(n1475), .A1(DMP_SHT2_EWSW[8]), .B0(n1485), .B1(
DMP_SFG[8]), .Y(n754) );
AO22XLTS U1076 ( .A0(n1600), .A1(DMP_SHT2_EWSW[2]), .B0(n1614), .B1(
DMP_SFG[2]), .Y(n772) );
AO22XLTS U1077 ( .A0(n1475), .A1(DMP_SHT2_EWSW[4]), .B0(n1614), .B1(
DMP_SFG[4]), .Y(n766) );
AO22XLTS U1078 ( .A0(n1486), .A1(DmP_EXP_EWSW[2]), .B0(n1634), .B1(
DmP_mant_SHT1_SW[2]), .Y(n666) );
AO22XLTS U1079 ( .A0(n1478), .A1(DmP_EXP_EWSW[6]), .B0(n1634), .B1(
DmP_mant_SHT1_SW[6]), .Y(n658) );
AO22XLTS U1080 ( .A0(n1489), .A1(DmP_EXP_EWSW[9]), .B0(n1634), .B1(
DmP_mant_SHT1_SW[9]), .Y(n652) );
AO22XLTS U1081 ( .A0(n1486), .A1(DmP_EXP_EWSW[21]), .B0(n1488), .B1(
DmP_mant_SHT1_SW[21]), .Y(n628) );
AO22XLTS U1082 ( .A0(n1486), .A1(DmP_EXP_EWSW[20]), .B0(n1488), .B1(
DmP_mant_SHT1_SW[20]), .Y(n630) );
AO22XLTS U1083 ( .A0(n1478), .A1(DmP_EXP_EWSW[10]), .B0(n1634), .B1(
DmP_mant_SHT1_SW[10]), .Y(n650) );
AO22XLTS U1084 ( .A0(n1486), .A1(DmP_EXP_EWSW[12]), .B0(n1634), .B1(
DmP_mant_SHT1_SW[12]), .Y(n646) );
AO22XLTS U1085 ( .A0(n1489), .A1(DmP_EXP_EWSW[18]), .B0(n1488), .B1(
DmP_mant_SHT1_SW[18]), .Y(n634) );
AO22XLTS U1086 ( .A0(n1489), .A1(DmP_EXP_EWSW[3]), .B0(n1634), .B1(
DmP_mant_SHT1_SW[3]), .Y(n664) );
AO22XLTS U1087 ( .A0(n967), .A1(DmP_EXP_EWSW[7]), .B0(n1634), .B1(
DmP_mant_SHT1_SW[7]), .Y(n656) );
AO22XLTS U1088 ( .A0(n967), .A1(DmP_EXP_EWSW[16]), .B0(n1488), .B1(
DmP_mant_SHT1_SW[16]), .Y(n638) );
AO22XLTS U1089 ( .A0(n1489), .A1(DmP_EXP_EWSW[17]), .B0(n1488), .B1(
DmP_mant_SHT1_SW[17]), .Y(n636) );
AO22XLTS U1090 ( .A0(n1478), .A1(DmP_EXP_EWSW[22]), .B0(n1488), .B1(
DmP_mant_SHT1_SW[22]), .Y(n626) );
AO22XLTS U1091 ( .A0(n1616), .A1(DMP_SHT2_EWSW[9]), .B0(n1598), .B1(
DMP_SFG[9]), .Y(n751) );
AO22XLTS U1092 ( .A0(n1437), .A1(Data_X[31]), .B0(n1445), .B1(intDX_EWSW[31]), .Y(n892) );
AO22XLTS U1093 ( .A0(n1600), .A1(DMP_SHT2_EWSW[7]), .B0(n1485), .B1(
DMP_SFG[7]), .Y(n757) );
AO22XLTS U1094 ( .A0(n1475), .A1(DMP_SHT2_EWSW[6]), .B0(n1598), .B1(
DMP_SFG[6]), .Y(n760) );
AO22XLTS U1095 ( .A0(n1611), .A1(DMP_SHT2_EWSW[1]), .B0(n1485), .B1(
DMP_SFG[1]), .Y(n775) );
AO22XLTS U1096 ( .A0(n1600), .A1(DMP_SHT2_EWSW[5]), .B0(n1614), .B1(
DMP_SFG[5]), .Y(n763) );
OAI211XLTS U1097 ( .A0(n1374), .A1(n972), .B0(n1350), .C0(n1349), .Y(n839)
);
OAI211XLTS U1098 ( .A0(n1406), .A1(n972), .B0(n1358), .C0(n1357), .Y(n838)
);
OAI211XLTS U1099 ( .A0(n1354), .A1(n1334), .B0(n1344), .C0(n1343), .Y(n837)
);
OAI211XLTS U1100 ( .A0(n1366), .A1(n1334), .B0(n1362), .C0(n1361), .Y(n836)
);
AOI2BB2XLTS U1101 ( .B0(n1558), .B1(intadd_44_SUM_6_), .A0N(
Raw_mant_NRM_SWR[18]), .A1N(n1527), .Y(n597) );
OAI21XLTS U1102 ( .A0(n1461), .A1(n1334), .B0(n1402), .Y(n848) );
OAI21XLTS U1103 ( .A0(n1457), .A1(n972), .B0(n1392), .Y(n850) );
AOI32X1TS U1104 ( .A0(Shift_amount_SHT1_EWR[2]), .A1(n1470), .A2(n1450),
.B0(shift_value_SHT2_EWR[2]), .B1(n1451), .Y(n1182) );
AO22XLTS U1105 ( .A0(n1442), .A1(Data_X[18]), .B0(n1445), .B1(intDX_EWSW[18]), .Y(n905) );
AO22XLTS U1106 ( .A0(n1527), .A1(n1526), .B0(n1525), .B1(Raw_mant_NRM_SWR[8]), .Y(n582) );
AOI2BB2XLTS U1107 ( .B0(n1558), .B1(intadd_44_SUM_7_), .A0N(
Raw_mant_NRM_SWR[19]), .A1N(n1527), .Y(n596) );
AO22XLTS U1108 ( .A0(n1446), .A1(Data_X[0]), .B0(n1445), .B1(intDX_EWSW[0]),
.Y(n923) );
AOI2BB2XLTS U1109 ( .B0(n1558), .B1(intadd_44_SUM_3_), .A0N(
Raw_mant_NRM_SWR[15]), .A1N(n1527), .Y(n600) );
AOI2BB2XLTS U1110 ( .B0(n1558), .B1(n1557), .A0N(Raw_mant_NRM_SWR[5]), .A1N(
n1725), .Y(n569) );
AOI2BB2XLTS U1111 ( .B0(n1558), .B1(intadd_44_SUM_1_), .A0N(
Raw_mant_NRM_SWR[13]), .A1N(n1527), .Y(n602) );
AO22XLTS U1112 ( .A0(n1437), .A1(Data_X[11]), .B0(n1431), .B1(intDX_EWSW[11]), .Y(n912) );
AO22XLTS U1113 ( .A0(n1446), .A1(Data_X[27]), .B0(n1445), .B1(intDX_EWSW[27]), .Y(n896) );
AO22XLTS U1114 ( .A0(n960), .A1(Data_X[9]), .B0(n1431), .B1(intDX_EWSW[9]),
.Y(n914) );
AO22XLTS U1115 ( .A0(n1600), .A1(DMP_SHT2_EWSW[3]), .B0(n1598), .B1(
DMP_SFG[3]), .Y(n769) );
AO22XLTS U1116 ( .A0(n961), .A1(Data_X[17]), .B0(n1445), .B1(intDX_EWSW[17]),
.Y(n906) );
AOI2BB2XLTS U1117 ( .B0(n1558), .B1(intadd_44_SUM_8_), .A0N(
Raw_mant_NRM_SWR[20]), .A1N(n1527), .Y(n595) );
AO22XLTS U1118 ( .A0(n1444), .A1(Data_X[8]), .B0(n1431), .B1(intDX_EWSW[8]),
.Y(n915) );
OAI21XLTS U1119 ( .A0(n1447), .A1(n972), .B0(n1396), .Y(n855) );
AO22XLTS U1120 ( .A0(n1444), .A1(Data_X[15]), .B0(n1431), .B1(intDX_EWSW[15]), .Y(n908) );
AO22XLTS U1121 ( .A0(n1441), .A1(Data_X[13]), .B0(n1431), .B1(intDX_EWSW[13]), .Y(n910) );
AO22XLTS U1122 ( .A0(n960), .A1(Data_X[21]), .B0(n1445), .B1(intDX_EWSW[21]),
.Y(n902) );
AO22XLTS U1123 ( .A0(n1441), .A1(Data_X[23]), .B0(n1445), .B1(intDX_EWSW[23]), .Y(n900) );
AO22XLTS U1124 ( .A0(n961), .A1(Data_X[3]), .B0(n1431), .B1(intDX_EWSW[3]),
.Y(n920) );
AOI2BB1XLTS U1125 ( .A0N(n1511), .A1N(n1531), .B0(n1510), .Y(n1512) );
AO22XLTS U1126 ( .A0(n961), .A1(Data_Y[29]), .B0(n1445), .B1(intDY_EWSW[29]),
.Y(n860) );
AO22XLTS U1127 ( .A0(n1437), .A1(Data_Y[30]), .B0(n1445), .B1(intDY_EWSW[30]), .Y(n859) );
AO22XLTS U1128 ( .A0(n1437), .A1(Data_X[4]), .B0(n1430), .B1(intDX_EWSW[4]),
.Y(n919) );
AO22XLTS U1129 ( .A0(n1437), .A1(Data_X[6]), .B0(n1431), .B1(intDX_EWSW[6]),
.Y(n917) );
AO22XLTS U1130 ( .A0(n1442), .A1(Data_X[7]), .B0(n1431), .B1(intDX_EWSW[7]),
.Y(n916) );
AO22XLTS U1131 ( .A0(n961), .A1(Data_X[16]), .B0(n1431), .B1(intDX_EWSW[16]),
.Y(n907) );
AO22XLTS U1132 ( .A0(n1442), .A1(Data_X[5]), .B0(n1431), .B1(intDX_EWSW[5]),
.Y(n918) );
NOR2XLTS U1133 ( .A(n1410), .B(SIGN_FLAG_SHT1SHT2), .Y(n1411) );
AO22XLTS U1134 ( .A0(n1588), .A1(n1599), .B0(final_result_ieee[13]), .B1(
n1005), .Y(n548) );
AO22XLTS U1135 ( .A0(n1588), .A1(n1584), .B0(final_result_ieee[8]), .B1(
n1005), .Y(n549) );
AO22XLTS U1136 ( .A0(n1588), .A1(n1597), .B0(final_result_ieee[12]), .B1(
n1005), .Y(n551) );
AO22XLTS U1137 ( .A0(n1588), .A1(n1578), .B0(final_result_ieee[9]), .B1(
n1005), .Y(n552) );
AO22XLTS U1138 ( .A0(n1588), .A1(n1596), .B0(final_result_ieee[11]), .B1(
n1005), .Y(n559) );
AO22XLTS U1139 ( .A0(n1588), .A1(n1595), .B0(final_result_ieee[10]), .B1(
n1005), .Y(n560) );
AO21XLTS U1140 ( .A0(underflow_flag), .A1(n1005), .B0(n1483), .Y(n620) );
AO21XLTS U1141 ( .A0(LZD_output_NRM2_EW[1]), .A1(n1450), .B0(n1173), .Y(n572) );
AO21XLTS U1142 ( .A0(LZD_output_NRM2_EW[4]), .A1(n1450), .B0(n1415), .Y(n587) );
OAI21XLTS U1143 ( .A0(n1439), .A1(n1480), .B0(n1265), .Y(n629) );
OAI21XLTS U1144 ( .A0(n992), .A1(n1480), .B0(n1266), .Y(n631) );
OAI21XLTS U1145 ( .A0(n1630), .A1(n1480), .B0(n1274), .Y(n635) );
OAI21XLTS U1146 ( .A0(n1668), .A1(n1480), .B0(n1263), .Y(n637) );
OAI21XLTS U1147 ( .A0(n989), .A1(n1285), .B0(n1262), .Y(n639) );
OAI21XLTS U1148 ( .A0(n1667), .A1(n1285), .B0(n1284), .Y(n641) );
AO22XLTS U1149 ( .A0(n1489), .A1(DmP_EXP_EWSW[13]), .B0(n1488), .B1(n978),
.Y(n644) );
OAI21XLTS U1150 ( .A0(n1001), .A1(n1285), .B0(n1264), .Y(n645) );
AO22XLTS U1151 ( .A0(n1478), .A1(DmP_EXP_EWSW[11]), .B0(n1634), .B1(n979),
.Y(n648) );
OAI21XLTS U1152 ( .A0(n1435), .A1(n1285), .B0(n1276), .Y(n651) );
OAI21XLTS U1153 ( .A0(n985), .A1(n1285), .B0(n1278), .Y(n653) );
OAI21XLTS U1154 ( .A0(n1670), .A1(n1285), .B0(n1272), .Y(n655) );
OAI21XLTS U1155 ( .A0(n1663), .A1(n1285), .B0(n1267), .Y(n657) );
OAI21XLTS U1156 ( .A0(n1434), .A1(n1285), .B0(n1270), .Y(n659) );
AO22XLTS U1157 ( .A0(n967), .A1(DmP_EXP_EWSW[5]), .B0(n1634), .B1(n981), .Y(
n660) );
AO22XLTS U1158 ( .A0(n1478), .A1(DmP_EXP_EWSW[4]), .B0(n1634), .B1(n977),
.Y(n662) );
OAI21XLTS U1159 ( .A0(n1659), .A1(n1296), .B0(n1269), .Y(n663) );
OAI21XLTS U1160 ( .A0(n1666), .A1(n1296), .B0(n1277), .Y(n665) );
OAI21XLTS U1161 ( .A0(n987), .A1(n1296), .B0(n1280), .Y(n667) );
OAI21XLTS U1162 ( .A0(n1433), .A1(n1296), .B0(n1279), .Y(n669) );
OAI21XLTS U1163 ( .A0(n1432), .A1(n1296), .B0(n1275), .Y(n671) );
AO22XLTS U1164 ( .A0(n1616), .A1(DMP_SHT2_EWSW[28]), .B0(n1598), .B1(
DMP_SFG[28]), .Y(n684) );
AO22XLTS U1165 ( .A0(n1611), .A1(DMP_SHT2_EWSW[27]), .B0(n1485), .B1(
DMP_SFG[27]), .Y(n689) );
AO22XLTS U1166 ( .A0(n1616), .A1(DMP_SHT2_EWSW[26]), .B0(n1614), .B1(
DMP_SFG[26]), .Y(n694) );
AO22XLTS U1167 ( .A0(n1611), .A1(DMP_SHT2_EWSW[25]), .B0(n1614), .B1(
DMP_SFG[25]), .Y(n699) );
AO22XLTS U1168 ( .A0(n1300), .A1(n1473), .B0(ZERO_FLAG_EXP), .B1(n1624), .Y(
n782) );
OAI21XLTS U1169 ( .A0(n950), .A1(n1296), .B0(n1261), .Y(n784) );
OAI21XLTS U1170 ( .A0(n1673), .A1(n1296), .B0(n1260), .Y(n785) );
OAI21XLTS U1171 ( .A0(n1671), .A1(n1480), .B0(n1257), .Y(n786) );
OAI21XLTS U1172 ( .A0(n1662), .A1(n1481), .B0(n1309), .Y(n787) );
OAI21XLTS U1173 ( .A0(n1439), .A1(n1481), .B0(n1291), .Y(n793) );
OAI21XLTS U1174 ( .A0(n992), .A1(n1481), .B0(n1293), .Y(n794) );
OAI21XLTS U1175 ( .A0(n1674), .A1(n1481), .B0(n1301), .Y(n795) );
OAI21XLTS U1176 ( .A0(n1438), .A1(n1314), .B0(n1302), .Y(n796) );
OAI21XLTS U1177 ( .A0(n1668), .A1(n1314), .B0(n1305), .Y(n797) );
OAI21XLTS U1178 ( .A0(n989), .A1(n1314), .B0(n1290), .Y(n798) );
OAI21XLTS U1179 ( .A0(n1667), .A1(n1314), .B0(n1313), .Y(n799) );
OAI21XLTS U1180 ( .A0(n1001), .A1(n1314), .B0(n1310), .Y(n801) );
OAI21XLTS U1181 ( .A0(n1660), .A1(n1314), .B0(n1307), .Y(n802) );
OAI21XLTS U1182 ( .A0(n1691), .A1(n1314), .B0(n1306), .Y(n803) );
OAI21XLTS U1183 ( .A0(n1435), .A1(n1314), .B0(n1303), .Y(n804) );
OAI21XLTS U1184 ( .A0(n1670), .A1(n1314), .B0(n1288), .Y(n806) );
OAI21XLTS U1185 ( .A0(n1663), .A1(n1314), .B0(n1286), .Y(n807) );
OAI21XLTS U1186 ( .A0(n1434), .A1(n1322), .B0(n1319), .Y(n808) );
OAI21XLTS U1187 ( .A0(n1626), .A1(n1322), .B0(n1316), .Y(n809) );
OAI21XLTS U1188 ( .A0(n1659), .A1(n1322), .B0(n1315), .Y(n810) );
OAI21XLTS U1189 ( .A0(n1666), .A1(n1322), .B0(n1317), .Y(n811) );
OAI21XLTS U1190 ( .A0(n987), .A1(n1322), .B0(n1318), .Y(n812) );
OAI21XLTS U1191 ( .A0(n1433), .A1(n1322), .B0(n1321), .Y(n813) );
OAI21XLTS U1192 ( .A0(n1432), .A1(n1481), .B0(n1292), .Y(n814) );
AO22XLTS U1193 ( .A0(n961), .A1(Data_X[10]), .B0(n1431), .B1(n1004), .Y(n913) );
OA22X1TS U1194 ( .A0(n1520), .A1(DmP_mant_SFG_SWR[7]), .B0(n1022), .B1(
OP_FLAG_SFG), .Y(n939) );
OR2X1TS U1195 ( .A(n965), .B(n1515), .Y(n943) );
OR2X1TS U1196 ( .A(n966), .B(n1515), .Y(n944) );
OR2X1TS U1197 ( .A(Shift_reg_FLAGS_7[1]), .B(Shift_amount_SHT1_EWR[0]), .Y(
n945) );
INVX2TS U1198 ( .A(Shift_reg_FLAGS_7[1]), .Y(n958) );
INVX2TS U1199 ( .A(left_right_SHT2), .Y(n964) );
INVX2TS U1200 ( .A(n943), .Y(n956) );
INVX2TS U1201 ( .A(n943), .Y(n957) );
INVX2TS U1202 ( .A(n1430), .Y(n960) );
INVX2TS U1203 ( .A(n1430), .Y(n961) );
INVX2TS U1204 ( .A(n1588), .Y(n962) );
INVX2TS U1205 ( .A(n1588), .Y(n963) );
INVX2TS U1206 ( .A(n964), .Y(n965) );
INVX2TS U1207 ( .A(n965), .Y(n966) );
INVX2TS U1208 ( .A(n1488), .Y(n967) );
CLKINVX3TS U1209 ( .A(n967), .Y(n968) );
INVX2TS U1210 ( .A(n967), .Y(n969) );
OAI21XLTS U1211 ( .A0(n1662), .A1(n1285), .B0(n1282), .Y(n621) );
OAI211XLTS U1212 ( .A0(n1339), .A1(n1334), .B0(n1338), .C0(n1337), .Y(n833)
);
OAI211XLTS U1213 ( .A0(n1366), .A1(n972), .B0(n1365), .C0(n1364), .Y(n834)
);
OAI211XLTS U1214 ( .A0(n1354), .A1(n972), .B0(n1353), .C0(n1352), .Y(n835)
);
NOR2XLTS U1215 ( .A(n1213), .B(intDY_EWSW[10]), .Y(n1214) );
INVX2TS U1216 ( .A(rst), .Y(n970) );
AOI222X1TS U1217 ( .A0(n1560), .A1(DMP_SFG[3]), .B0(n1560), .B1(n1559), .C0(
DMP_SFG[3]), .C1(n1559), .Y(n1565) );
OAI21X2TS U1218 ( .A0(n1555), .A1(n1554), .B0(n1553), .Y(n1559) );
AOI31XLTS U1219 ( .A0(n1508), .A1(n1552), .A2(n1507), .B0(n1506), .Y(n1509)
);
AOI222X1TS U1220 ( .A0(n1523), .A1(DMP_SFG[6]), .B0(n1523), .B1(n1506), .C0(
DMP_SFG[6]), .C1(n1506), .Y(n1497) );
OAI21X2TS U1221 ( .A0(n1505), .A1(n1496), .B0(n1495), .Y(n1506) );
BUFX4TS U1222 ( .A(n1431), .Y(n1445) );
BUFX4TS U1223 ( .A(Shift_reg_FLAGS_7_5), .Y(n1486) );
BUFX4TS U1224 ( .A(Shift_reg_FLAGS_7_5), .Y(n1478) );
INVX2TS U1225 ( .A(n939), .Y(n973) );
NOR2X4TS U1226 ( .A(shift_value_SHT2_EWR[4]), .B(left_right_SHT2), .Y(n1158)
);
BUFX4TS U1227 ( .A(n1701), .Y(n1698) );
BUFX4TS U1228 ( .A(n1704), .Y(n1693) );
BUFX4TS U1229 ( .A(n1703), .Y(n1695) );
BUFX4TS U1230 ( .A(n1702), .Y(n1696) );
BUFX3TS U1231 ( .A(n970), .Y(n1061) );
INVX2TS U1232 ( .A(n942), .Y(n976) );
AOI22X4TS U1233 ( .A0(DmP_mant_SFG_SWR[5]), .A1(n1539), .B0(n1520), .B1(n974), .Y(n1560) );
AOI22X2TS U1234 ( .A0(n1539), .A1(DmP_mant_SFG_SWR[9]), .B0(n1017), .B1(
n1538), .Y(n1528) );
BUFX4TS U1235 ( .A(OP_FLAG_SFG), .Y(n1539) );
AOI222X1TS U1236 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1448), .B0(
DmP_mant_SHT1_SW[20]), .B1(n1340), .C0(n1003), .C1(
DmP_mant_SHT1_SW[19]), .Y(n1377) );
INVX2TS U1237 ( .A(n936), .Y(n977) );
INVX2TS U1238 ( .A(n952), .Y(n978) );
INVX2TS U1239 ( .A(n935), .Y(n979) );
AOI222X1TS U1240 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1448), .B0(n1003), .B1(
DmP_mant_SHT1_SW[15]), .C0(n1340), .C1(DmP_mant_SHT1_SW[16]), .Y(n1388) );
BUFX4TS U1241 ( .A(n1485), .Y(n1601) );
INVX2TS U1242 ( .A(n955), .Y(n980) );
INVX2TS U1243 ( .A(n951), .Y(n981) );
INVX2TS U1244 ( .A(n954), .Y(n982) );
INVX2TS U1245 ( .A(n953), .Y(n983) );
INVX2TS U1246 ( .A(n937), .Y(n984) );
OAI21XLTS U1247 ( .A0(n1628), .A1(n1480), .B0(n1259), .Y(n627) );
INVX2TS U1248 ( .A(intDY_EWSW[9]), .Y(n985) );
INVX2TS U1249 ( .A(n985), .Y(n986) );
OAI21XLTS U1250 ( .A0(n1627), .A1(n1285), .B0(n1258), .Y(n643) );
OAI21XLTS U1251 ( .A0(n1627), .A1(n1314), .B0(n1308), .Y(n800) );
INVX2TS U1252 ( .A(intDY_EWSW[2]), .Y(n987) );
INVX2TS U1253 ( .A(n987), .Y(n988) );
NAND2X1TS U1254 ( .A(n1035), .B(n1639), .Y(n1177) );
INVX2TS U1255 ( .A(intDY_EWSW[16]), .Y(n989) );
INVX2TS U1256 ( .A(n989), .Y(n990) );
OAI21XLTS U1257 ( .A0(n1423), .A1(n1185), .B0(n1424), .Y(n931) );
NOR2X4TS U1258 ( .A(n1410), .B(n1422), .Y(n1588) );
OAI2BB1X2TS U1259 ( .A0N(n1134), .A1N(n1133), .B0(Shift_reg_FLAGS_7[0]), .Y(
n1422) );
INVX4TS U1260 ( .A(Shift_reg_FLAGS_7_6), .Y(n991) );
BUFX3TS U1261 ( .A(n1485), .Y(n1614) );
BUFX4TS U1262 ( .A(n933), .Y(n1281) );
INVX2TS U1263 ( .A(n944), .Y(n993) );
INVX2TS U1264 ( .A(n944), .Y(n994) );
INVX2TS U1265 ( .A(n1077), .Y(n996) );
INVX2TS U1266 ( .A(n996), .Y(n997) );
INVX2TS U1267 ( .A(n996), .Y(n998) );
INVX2TS U1268 ( .A(n1334), .Y(n999) );
INVX2TS U1269 ( .A(n999), .Y(n1000) );
AOI221X1TS U1270 ( .A0(n1435), .A1(n1004), .B0(intDX_EWSW[11]), .B1(n1691),
.C0(n1198), .Y(n1099) );
OAI21XLTS U1271 ( .A0(n1691), .A1(n1285), .B0(n1271), .Y(n649) );
CLKINVX3TS U1272 ( .A(n945), .Y(n1002) );
CLKINVX3TS U1273 ( .A(n1477), .Y(n1474) );
CLKINVX3TS U1274 ( .A(n1477), .Y(n1484) );
INVX4TS U1275 ( .A(n1598), .Y(n1600) );
INVX4TS U1276 ( .A(n1598), .Y(n1475) );
INVX4TS U1277 ( .A(n1470), .Y(n1451) );
INVX4TS U1278 ( .A(n1614), .Y(n1487) );
INVX4TS U1279 ( .A(n1614), .Y(n1616) );
INVX4TS U1280 ( .A(n1614), .Y(n1611) );
OAI211XLTS U1281 ( .A0(n1377), .A1(n1000), .B0(n1376), .C0(n1375), .Y(n853)
);
OAI211XLTS U1282 ( .A0(n1388), .A1(n1000), .B0(n1387), .C0(n1386), .Y(n849)
);
AOI222X4TS U1283 ( .A0(Data_array_SWR[23]), .A1(n1582), .B0(
Data_array_SWR[19]), .B1(n998), .C0(Data_array_SWR[15]), .C1(n1078),
.Y(n1580) );
OAI211XLTS U1284 ( .A0(n1371), .A1(n1000), .B0(n1368), .C0(n1367), .Y(n843)
);
AOI222X1TS U1285 ( .A0(n1142), .A1(n966), .B0(n957), .B1(Data_array_SWR[9]),
.C0(n1141), .C1(n1161), .Y(n1576) );
AOI32X1TS U1286 ( .A0(n1438), .A1(n1236), .A2(intDX_EWSW[18]), .B0(
intDX_EWSW[19]), .B1(n1674), .Y(n1237) );
AOI221X1TS U1287 ( .A0(n1630), .A1(intDX_EWSW[18]), .B0(intDX_EWSW[19]),
.B1(n1674), .C0(n1240), .Y(n1092) );
AOI221X1TS U1288 ( .A0(n1662), .A1(intDX_EWSW[27]), .B0(intDY_EWSW[28]),
.B1(n1671), .C0(n1081), .Y(n1085) );
INVX2TS U1289 ( .A(n940), .Y(n1004) );
AOI221X1TS U1290 ( .A0(n987), .A1(intDX_EWSW[2]), .B0(intDX_EWSW[3]), .B1(
n1666), .C0(n1102), .Y(n1107) );
AOI221X1TS U1291 ( .A0(n1433), .A1(intDX_EWSW[1]), .B0(intDX_EWSW[17]), .B1(
n1668), .C0(n1087), .Y(n1093) );
AOI221X1TS U1292 ( .A0(n1440), .A1(intDX_EWSW[22]), .B0(intDX_EWSW[23]),
.B1(n1672), .C0(n1089), .Y(n1090) );
AOI221X1TS U1293 ( .A0(n1436), .A1(intDX_EWSW[14]), .B0(intDX_EWSW[15]),
.B1(n1667), .C0(n1096), .Y(n1097) );
NOR2X2TS U1294 ( .A(n1008), .B(DMP_EXP_EWSW[23]), .Y(n1471) );
AOI22X2TS U1295 ( .A0(OP_FLAG_SFG), .A1(DmP_mant_SFG_SWR[3]), .B0(n1012),
.B1(n1520), .Y(n1546) );
AOI22X2TS U1296 ( .A0(n1539), .A1(DmP_mant_SFG_SWR[8]), .B0(n1015), .B1(
n1538), .Y(n1523) );
XNOR2X2TS U1297 ( .A(DMP_exp_NRM2_EW[6]), .B(n1124), .Y(n1420) );
XNOR2X2TS U1298 ( .A(DMP_exp_NRM2_EW[0]), .B(n1412), .Y(n1418) );
NOR2XLTS U1299 ( .A(n1122), .B(n1419), .Y(n1123) );
XNOR2X2TS U1300 ( .A(DMP_exp_NRM2_EW[5]), .B(DP_OP_15J39_125_2314_n4), .Y(
n1419) );
NOR2X4TS U1301 ( .A(shift_value_SHT2_EWR[4]), .B(n966), .Y(n1161) );
OAI31XLTS U1302 ( .A0(n1300), .A1(n1299), .A2(n1481), .B0(n1298), .Y(n781)
);
OAI21XLTS U1303 ( .A0(n1299), .A1(n1624), .B0(n1296), .Y(n1297) );
XNOR2X2TS U1304 ( .A(intDY_EWSW[31]), .B(intAS), .Y(n1299) );
BUFX4TS U1305 ( .A(n1062), .Y(n1713) );
BUFX4TS U1306 ( .A(n1061), .Y(n1699) );
BUFX4TS U1307 ( .A(n1062), .Y(n1697) );
BUFX4TS U1308 ( .A(n1061), .Y(n1714) );
BUFX4TS U1309 ( .A(n1062), .Y(n1715) );
BUFX4TS U1310 ( .A(n1061), .Y(n1717) );
BUFX3TS U1311 ( .A(n970), .Y(n1062) );
AOI2BB2X2TS U1312 ( .B0(OP_FLAG_SFG), .B1(DmP_mant_SFG_SWR[11]), .A0N(
DmP_mant_SFG_SWR[11]), .A1N(OP_FLAG_SFG), .Y(n1504) );
NOR2X2TS U1313 ( .A(DMP_SFG[2]), .B(n1186), .Y(n1555) );
AOI221X1TS U1314 ( .A0(intDX_EWSW[30]), .A1(n1649), .B0(intDX_EWSW[29]),
.B1(n1625), .C0(n1194), .Y(n1196) );
NOR2XLTS U1315 ( .A(n1248), .B(intDY_EWSW[24]), .Y(n1188) );
INVX4TS U1316 ( .A(n1430), .Y(n1437) );
AOI222X4TS U1317 ( .A0(DMP_SFG[1]), .A1(n1544), .B0(DMP_SFG[1]), .B1(n1546),
.C0(n1544), .C1(n1546), .Y(n1554) );
XOR2XLTS U1318 ( .A(DMP_SFG[1]), .B(n1544), .Y(n1545) );
AOI222X1TS U1319 ( .A0(n1157), .A1(n966), .B0(n957), .B1(Data_array_SWR[7]),
.C0(n1156), .C1(n1161), .Y(n1589) );
AOI222X1TS U1320 ( .A0(n1157), .A1(left_right_SHT2), .B0(Data_array_SWR[7]),
.B1(n994), .C0(n1156), .C1(n1158), .Y(n1604) );
AOI222X1TS U1321 ( .A0(n1138), .A1(n965), .B0(Data_array_SWR[6]), .B1(n994),
.C0(n1137), .C1(n1158), .Y(n1605) );
AOI222X1TS U1322 ( .A0(n1138), .A1(n966), .B0(n957), .B1(Data_array_SWR[6]),
.C0(n1137), .C1(n1161), .Y(n1570) );
AOI222X1TS U1323 ( .A0(n1160), .A1(n964), .B0(n957), .B1(Data_array_SWR[5]),
.C0(n1159), .C1(n1161), .Y(n1577) );
AOI222X1TS U1324 ( .A0(n1160), .A1(left_right_SHT2), .B0(Data_array_SWR[5]),
.B1(n994), .C0(n1159), .C1(n1158), .Y(n1606) );
AOI222X1TS U1325 ( .A0(n1145), .A1(n965), .B0(Data_array_SWR[4]), .B1(n994),
.C0(n1146), .C1(n1158), .Y(n1607) );
AOI222X1TS U1326 ( .A0(n1145), .A1(n964), .B0(n957), .B1(Data_array_SWR[4]),
.C0(n1146), .C1(n1161), .Y(n1571) );
NOR2BX1TS U1327 ( .AN(n1047), .B(Raw_mant_NRM_SWR[18]), .Y(n1166) );
AOI222X4TS U1328 ( .A0(Data_array_SWR[20]), .A1(n998), .B0(
Data_array_SWR[24]), .B1(n1582), .C0(Data_array_SWR[16]), .C1(n1078),
.Y(n1574) );
AOI222X4TS U1329 ( .A0(Data_array_SWR[20]), .A1(n1155), .B0(
Data_array_SWR[24]), .B1(n1153), .C0(Data_array_SWR[16]), .C1(n1154),
.Y(n1536) );
NOR2X2TS U1330 ( .A(shift_value_SHT2_EWR[2]), .B(n1645), .Y(n1153) );
NOR2X4TS U1331 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.Y(n1154) );
NOR2X2TS U1332 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n1629), .Y(n1423) );
OAI21X2TS U1333 ( .A0(intDX_EWSW[18]), .A1(n1438), .B0(n1236), .Y(n1240) );
AOI32X1TS U1334 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1039), .A2(n1038), .B0(
Raw_mant_NRM_SWR[19]), .B1(n1039), .Y(n1040) );
NOR3X1TS U1335 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[19]), .C(
Raw_mant_NRM_SWR[20]), .Y(n1176) );
OAI21XLTS U1336 ( .A0(intDX_EWSW[1]), .A1(n1669), .B0(intDX_EWSW[0]), .Y(
n1201) );
OAI211XLTS U1337 ( .A0(n1384), .A1(n1000), .B0(n1383), .C0(n1382), .Y(n845)
);
OAI211XLTS U1338 ( .A0(n1381), .A1(n1334), .B0(n1379), .C0(n1378), .Y(n847)
);
INVX4TS U1339 ( .A(Shift_reg_FLAGS_7[0]), .Y(n1005) );
NOR2XLTS U1340 ( .A(n1482), .B(n1724), .Y(n1483) );
NOR2X2TS U1341 ( .A(Raw_mant_NRM_SWR[13]), .B(n1033), .Y(n1050) );
OAI211XLTS U1342 ( .A0(intDX_EWSW[8]), .A1(n1670), .B0(n1215), .C0(n1218),
.Y(n1229) );
OAI21XLTS U1343 ( .A0(intDX_EWSW[13]), .A1(n1001), .B0(intDX_EWSW[12]), .Y(
n1212) );
OAI21XLTS U1344 ( .A0(intDX_EWSW[21]), .A1(n1658), .B0(intDX_EWSW[20]), .Y(
n1233) );
OAI21XLTS U1345 ( .A0(intDX_EWSW[23]), .A1(n1672), .B0(intDX_EWSW[22]), .Y(
n1241) );
OAI21XLTS U1346 ( .A0(intDX_EWSW[3]), .A1(n1666), .B0(intDX_EWSW[2]), .Y(
n1204) );
OAI211XLTS U1347 ( .A0(n1666), .A1(intDX_EWSW[3]), .B0(n1203), .C0(n1202),
.Y(n1206) );
AO22XLTS U1348 ( .A0(n1428), .A1(n1450), .B0(n1005), .B1(n1427), .Y(n1006)
);
NOR2XLTS U1349 ( .A(n1691), .B(intDX_EWSW[11]), .Y(n1213) );
OAI21XLTS U1350 ( .A0(intDX_EWSW[15]), .A1(n1667), .B0(intDX_EWSW[14]), .Y(
n1221) );
NOR2XLTS U1351 ( .A(n1234), .B(n990), .Y(n1235) );
NOR2XLTS U1352 ( .A(Raw_mant_NRM_SWR[23]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1041) );
NAND2X1TS U1353 ( .A(n1052), .B(n1638), .Y(n1324) );
OAI21XLTS U1354 ( .A0(n941), .A1(n1464), .B0(n1389), .Y(n1390) );
AOI31XLTS U1355 ( .A0(n1490), .A1(Shift_amount_SHT1_EWR[4]), .A2(n958), .B0(
n1415), .Y(n1332) );
OAI21XLTS U1356 ( .A0(n1470), .A1(n1655), .B0(n1332), .Y(n828) );
INVX2TS U1357 ( .A(n1032), .Y(n1617) );
OAI21XLTS U1358 ( .A0(n1674), .A1(n1480), .B0(n1256), .Y(n633) );
OAI21XLTS U1359 ( .A0(n1660), .A1(n1285), .B0(n1273), .Y(n647) );
OAI21XLTS U1360 ( .A0(n1626), .A1(n1285), .B0(n1268), .Y(n661) );
OAI21XLTS U1361 ( .A0(n1628), .A1(n1481), .B0(n1295), .Y(n792) );
OAI21XLTS U1362 ( .A0(n949), .A1(n1314), .B0(n1289), .Y(n805) );
OAI21XLTS U1363 ( .A0(n1468), .A1(n972), .B0(n1408), .Y(n840) );
NOR2XLTS U1364 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n1031) );
AOI32X4TS U1365 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B0(n1031), .B1(n1629), .Y(n1428)
);
CLKBUFX3TS U1366 ( .A(n1726), .Y(n1525) );
OAI2BB2XLTS U1367 ( .B0(n1428), .B1(n1525), .A0N(n1428), .A1N(n976), .Y(
n1032) );
INVX4TS U1368 ( .A(n959), .Y(n1450) );
INVX2TS U1369 ( .A(n1428), .Y(n1427) );
AOI22X1TS U1370 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(n1423), .B0(
inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n1652), .Y(n1429) );
OAI2BB2XLTS U1371 ( .B0(n1428), .B1(n1624), .A0N(n1428), .A1N(n1429), .Y(
n930) );
INVX4TS U1372 ( .A(n975), .Y(n1490) );
NAND4X1TS U1373 ( .A(n938), .B(n1620), .C(n1635), .D(n1618), .Y(n1175) );
NOR2BX2TS U1374 ( .AN(n1176), .B(n1175), .Y(n1047) );
NOR3X1TS U1375 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[17]), .C(
Raw_mant_NRM_SWR[16]), .Y(n1167) );
NAND2X1TS U1376 ( .A(Raw_mant_NRM_SWR[14]), .B(n1164), .Y(n1045) );
NOR3X1TS U1377 ( .A(Raw_mant_NRM_SWR[12]), .B(n1640), .C(n1034), .Y(n1171)
);
NOR3X1TS U1378 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .C(n1324),
.Y(n1035) );
NOR3X2TS U1379 ( .A(Raw_mant_NRM_SWR[6]), .B(Raw_mant_NRM_SWR[5]), .C(n1177),
.Y(n1328) );
OAI21XLTS U1380 ( .A0(Raw_mant_NRM_SWR[7]), .A1(Raw_mant_NRM_SWR[6]), .B0(
n1035), .Y(n1036) );
OAI21X1TS U1381 ( .A0(n1037), .A1(n1178), .B0(n1036), .Y(n1327) );
NOR2X1TS U1382 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[20]), .Y(
n1039) );
AOI211X1TS U1383 ( .A0(n1041), .A1(n1040), .B0(Raw_mant_NRM_SWR[25]), .C0(
Raw_mant_NRM_SWR[24]), .Y(n1042) );
NOR4BBX2TS U1384 ( .AN(n1045), .BN(n1043), .C(n1327), .D(n1042), .Y(n1347)
);
AOI32X1TS U1385 ( .A0(Raw_mant_NRM_SWR[20]), .A1(n938), .A2(n1648), .B0(
Raw_mant_NRM_SWR[22]), .B1(n938), .Y(n1044) );
AOI32X1TS U1386 ( .A0(n1618), .A1(n1045), .A2(n1044), .B0(
Raw_mant_NRM_SWR[25]), .B1(n1045), .Y(n1046) );
NOR3X1TS U1387 ( .A(Raw_mant_NRM_SWR[2]), .B(Raw_mant_NRM_SWR[3]), .C(n1178),
.Y(n1165) );
NAND2X1TS U1388 ( .A(n1165), .B(Raw_mant_NRM_SWR[0]), .Y(n1330) );
AOI21X1TS U1389 ( .A0(n1328), .A1(n1049), .B0(n1048), .Y(n1051) );
NAND2X1TS U1390 ( .A(Raw_mant_NRM_SWR[12]), .B(n1050), .Y(n1169) );
OAI211X1TS U1391 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1330), .B0(n1051), .C0(
n1169), .Y(n1180) );
OAI211X1TS U1392 ( .A0(n1643), .A1(n1177), .B0(n1054), .C0(n1053), .Y(n1055)
);
NAND2X2TS U1393 ( .A(n1055), .B(n959), .Y(n1464) );
INVX2TS U1394 ( .A(n1464), .Y(n1452) );
NAND2X2TS U1395 ( .A(n1347), .B(n1452), .Y(n1405) );
INVX2TS U1396 ( .A(n1405), .Y(n1395) );
AOI22X1TS U1397 ( .A0(n1451), .A1(Data_array_SWR[0]), .B0(
Raw_mant_NRM_SWR[24]), .B1(n1395), .Y(n1059) );
OR2X2TS U1398 ( .A(n958), .B(n1055), .Y(n1454) );
NOR2X1TS U1399 ( .A(n1347), .B(n1450), .Y(n1173) );
AOI21X1TS U1400 ( .A0(Shift_amount_SHT1_EWR[1]), .A1(n1450), .B0(n1173), .Y(
n1333) );
NOR2X2TS U1401 ( .A(n1380), .B(n1333), .Y(n1360) );
BUFX3TS U1402 ( .A(n1340), .Y(n1462) );
AOI22X1TS U1403 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1452), .B0(n1462), .B1(
n982), .Y(n1057) );
AOI22X1TS U1404 ( .A0(Raw_mant_NRM_SWR[23]), .A1(n1466), .B0(n1002), .B1(
n983), .Y(n1056) );
NAND2X1TS U1405 ( .A(n1057), .B(n1056), .Y(n1363) );
AOI22X1TS U1406 ( .A0(Raw_mant_NRM_SWR[25]), .A1(n1466), .B0(n1360), .B1(
n1363), .Y(n1058) );
NAND2X1TS U1407 ( .A(n1059), .B(n1058), .Y(n832) );
BUFX3TS U1408 ( .A(n970), .Y(n1706) );
CLKBUFX2TS U1409 ( .A(n971), .Y(n1060) );
BUFX3TS U1410 ( .A(n1062), .Y(n1707) );
BUFX3TS U1411 ( .A(n1061), .Y(n1708) );
BUFX3TS U1412 ( .A(n1062), .Y(n1709) );
BUFX3TS U1413 ( .A(n970), .Y(n1705) );
BUFX3TS U1414 ( .A(n1061), .Y(n1711) );
BUFX3TS U1415 ( .A(n1062), .Y(n1712) );
BUFX3TS U1416 ( .A(n1061), .Y(n1700) );
BUFX3TS U1417 ( .A(n970), .Y(n1702) );
BUFX3TS U1418 ( .A(n971), .Y(n1703) );
BUFX3TS U1419 ( .A(n971), .Y(n1704) );
BUFX3TS U1420 ( .A(n1061), .Y(n1722) );
BUFX3TS U1421 ( .A(n1062), .Y(n1721) );
BUFX3TS U1422 ( .A(n1061), .Y(n1720) );
BUFX3TS U1423 ( .A(n1062), .Y(n1723) );
BUFX3TS U1424 ( .A(n1062), .Y(n1692) );
BUFX3TS U1425 ( .A(n1062), .Y(n1716) );
BUFX3TS U1426 ( .A(n1062), .Y(n1710) );
BUFX3TS U1427 ( .A(n1061), .Y(n1719) );
BUFX3TS U1428 ( .A(n971), .Y(n1701) );
BUFX3TS U1429 ( .A(n1061), .Y(n1694) );
BUFX3TS U1430 ( .A(n1061), .Y(n1718) );
AO22XLTS U1431 ( .A0(Shift_reg_FLAGS_7[1]), .A1(ZERO_FLAG_NRM), .B0(n1450),
.B1(ZERO_FLAG_SHT1SHT2), .Y(n614) );
AO22XLTS U1432 ( .A0(Shift_reg_FLAGS_7[1]), .A1(SIGN_FLAG_NRM), .B0(n1450),
.B1(SIGN_FLAG_SHT1SHT2), .Y(n605) );
NOR2X1TS U1433 ( .A(n1631), .B(DMP_EXP_EWSW[24]), .Y(n1065) );
AOI21X1TS U1434 ( .A0(DMP_EXP_EWSW[24]), .A1(n1631), .B0(n1065), .Y(n1063)
);
XNOR2X1TS U1435 ( .A(n1471), .B(n1063), .Y(n1064) );
AO22XLTS U1436 ( .A0(n1478), .A1(n1064), .B0(n1484), .B1(
Shift_amount_SHT1_EWR[1]), .Y(n826) );
OAI22X1TS U1437 ( .A0(n1471), .A1(n1065), .B0(DmP_EXP_EWSW[24]), .B1(n1619),
.Y(n1068) );
NAND2X1TS U1438 ( .A(DmP_EXP_EWSW[25]), .B(n1676), .Y(n1069) );
OAI21XLTS U1439 ( .A0(DmP_EXP_EWSW[25]), .A1(n1676), .B0(n1069), .Y(n1066)
);
XNOR2X1TS U1440 ( .A(n1068), .B(n1066), .Y(n1067) );
AO22XLTS U1441 ( .A0(n1489), .A1(n1067), .B0(n1484), .B1(
Shift_amount_SHT1_EWR[2]), .Y(n825) );
AOI22X1TS U1442 ( .A0(DMP_EXP_EWSW[25]), .A1(n1686), .B0(n1069), .B1(n1068),
.Y(n1072) );
NOR2X1TS U1443 ( .A(n1681), .B(DMP_EXP_EWSW[26]), .Y(n1073) );
AOI21X1TS U1444 ( .A0(DMP_EXP_EWSW[26]), .A1(n1681), .B0(n1073), .Y(n1070)
);
XNOR2X1TS U1445 ( .A(n1072), .B(n1070), .Y(n1071) );
AO22XLTS U1446 ( .A0(n1478), .A1(n1071), .B0(n968), .B1(
Shift_amount_SHT1_EWR[3]), .Y(n824) );
OAI22X1TS U1447 ( .A0(n1073), .A1(n1072), .B0(DmP_EXP_EWSW[26]), .B1(n1683),
.Y(n1075) );
XNOR2X1TS U1448 ( .A(DmP_EXP_EWSW[27]), .B(n984), .Y(n1074) );
XOR2XLTS U1449 ( .A(n1075), .B(n1074), .Y(n1076) );
AO22XLTS U1450 ( .A0(n1486), .A1(n1076), .B0(n968), .B1(
Shift_amount_SHT1_EWR[4]), .Y(n823) );
INVX4TS U1451 ( .A(n975), .Y(busy) );
BUFX3TS U1452 ( .A(n1485), .Y(n1598) );
AND3X4TS U1453 ( .A(shift_value_SHT2_EWR[2]), .B(shift_value_SHT2_EWR[3]),
.C(n1655), .Y(n1582) );
NOR2BX1TS U1454 ( .AN(n1153), .B(shift_value_SHT2_EWR[4]), .Y(n1077) );
NAND2X1TS U1455 ( .A(n1645), .B(shift_value_SHT2_EWR[2]), .Y(n1117) );
AOI22X1TS U1456 ( .A0(Data_array_SWR[22]), .A1(n997), .B0(Data_array_SWR[18]), .B1(n1078), .Y(n1581) );
NAND2X1TS U1457 ( .A(n1154), .B(n1655), .Y(n1515) );
AOI22X1TS U1458 ( .A0(Data_array_SWR[14]), .A1(n993), .B0(Data_array_SWR[11]), .B1(n956), .Y(n1079) );
OAI221X1TS U1459 ( .A0(left_right_SHT2), .A1(n1580), .B0(n964), .B1(n1581),
.C0(n1079), .Y(n1578) );
OAI22X1TS U1460 ( .A0(n1665), .A1(intDX_EWSW[25]), .B0(n1689), .B1(
intDX_EWSW[26]), .Y(n1080) );
AOI221X1TS U1461 ( .A0(n1665), .A1(intDX_EWSW[25]), .B0(intDX_EWSW[26]),
.B1(n1689), .C0(n1080), .Y(n1086) );
OAI22X1TS U1462 ( .A0(n1662), .A1(intDX_EWSW[27]), .B0(n1671), .B1(
intDY_EWSW[28]), .Y(n1081) );
OAI22X1TS U1463 ( .A0(n1673), .A1(intDY_EWSW[29]), .B0(n950), .B1(
intDY_EWSW[30]), .Y(n1082) );
AOI221X1TS U1464 ( .A0(n1673), .A1(intDY_EWSW[29]), .B0(intDY_EWSW[30]),
.B1(n950), .C0(n1082), .Y(n1084) );
AOI2BB2XLTS U1465 ( .B0(intDX_EWSW[7]), .B1(n1663), .A0N(n1663), .A1N(
intDX_EWSW[7]), .Y(n1083) );
NAND4XLTS U1466 ( .A(n1086), .B(n1085), .C(n1084), .D(n1083), .Y(n1112) );
INVX2TS U1467 ( .A(intDY_EWSW[1]), .Y(n1433) );
OAI22X1TS U1468 ( .A0(n1433), .A1(intDX_EWSW[1]), .B0(n1668), .B1(
intDX_EWSW[17]), .Y(n1087) );
INVX2TS U1469 ( .A(intDY_EWSW[18]), .Y(n1438) );
INVX2TS U1470 ( .A(intDY_EWSW[21]), .Y(n1439) );
OAI22X1TS U1471 ( .A0(n992), .A1(intDX_EWSW[20]), .B0(n1439), .B1(
intDX_EWSW[21]), .Y(n1088) );
INVX2TS U1472 ( .A(intDY_EWSW[22]), .Y(n1440) );
OAI22X1TS U1473 ( .A0(n1628), .A1(intDX_EWSW[22]), .B0(n1672), .B1(
intDX_EWSW[23]), .Y(n1089) );
NAND4XLTS U1474 ( .A(n1093), .B(n1092), .C(n1091), .D(n1090), .Y(n1111) );
INVX2TS U1475 ( .A(intDY_EWSW[24]), .Y(n1479) );
OAI22X1TS U1476 ( .A0(n1479), .A1(intDX_EWSW[24]), .B0(n949), .B1(
intDX_EWSW[9]), .Y(n1094) );
AOI221X1TS U1477 ( .A0(n1479), .A1(intDX_EWSW[24]), .B0(intDX_EWSW[9]), .B1(
n985), .C0(n1094), .Y(n1100) );
INVX2TS U1478 ( .A(intDY_EWSW[10]), .Y(n1435) );
OAI22X1TS U1479 ( .A0(n1435), .A1(n1004), .B0(n1691), .B1(intDX_EWSW[11]),
.Y(n1198) );
OAI22X1TS U1480 ( .A0(n1660), .A1(intDX_EWSW[12]), .B0(n1001), .B1(
intDX_EWSW[13]), .Y(n1095) );
INVX2TS U1481 ( .A(intDY_EWSW[14]), .Y(n1436) );
OAI22X1TS U1482 ( .A0(n1627), .A1(intDX_EWSW[14]), .B0(n1667), .B1(
intDX_EWSW[15]), .Y(n1096) );
NAND4XLTS U1483 ( .A(n1100), .B(n1099), .C(n1098), .D(n1097), .Y(n1110) );
INVX2TS U1484 ( .A(intDY_EWSW[0]), .Y(n1432) );
OAI22X1TS U1485 ( .A0(n948), .A1(intDX_EWSW[16]), .B0(n1432), .B1(
intDX_EWSW[0]), .Y(n1101) );
AOI221X1TS U1486 ( .A0(n989), .A1(intDX_EWSW[16]), .B0(intDX_EWSW[0]), .B1(
n1432), .C0(n1101), .Y(n1108) );
OAI22X1TS U1487 ( .A0(n947), .A1(intDX_EWSW[2]), .B0(n1666), .B1(
intDX_EWSW[3]), .Y(n1102) );
OAI22X1TS U1488 ( .A0(n1659), .A1(intDX_EWSW[4]), .B0(n1626), .B1(
intDX_EWSW[5]), .Y(n1103) );
AOI221X1TS U1489 ( .A0(n1659), .A1(intDX_EWSW[4]), .B0(intDX_EWSW[5]), .B1(
n1626), .C0(n1103), .Y(n1106) );
INVX2TS U1490 ( .A(intDY_EWSW[6]), .Y(n1434) );
OAI22X1TS U1491 ( .A0(n1670), .A1(intDX_EWSW[8]), .B0(n1434), .B1(
intDX_EWSW[6]), .Y(n1104) );
AOI221X1TS U1492 ( .A0(n1670), .A1(intDX_EWSW[8]), .B0(intDX_EWSW[6]), .B1(
n1434), .C0(n1104), .Y(n1105) );
NAND4XLTS U1493 ( .A(n1108), .B(n1107), .C(n1106), .D(n1105), .Y(n1109) );
NOR4X1TS U1494 ( .A(n1112), .B(n1111), .C(n1110), .D(n1109), .Y(n1300) );
INVX2TS U1495 ( .A(n1299), .Y(n1114) );
OAI21XLTS U1496 ( .A0(n1114), .A1(intDX_EWSW[31]), .B0(Shift_reg_FLAGS_7_6),
.Y(n1113) );
AOI21X1TS U1497 ( .A0(n1114), .A1(intDX_EWSW[31]), .B0(n1113), .Y(n1473) );
AOI22X1TS U1498 ( .A0(Data_array_SWR[15]), .A1(n998), .B0(Data_array_SWR[11]), .B1(n995), .Y(n1116) );
NOR2BX2TS U1499 ( .AN(n1154), .B(n1655), .Y(n1150) );
AOI22X1TS U1500 ( .A0(Data_array_SWR[23]), .A1(n1150), .B0(
Data_array_SWR[19]), .B1(n1582), .Y(n1115) );
NAND2X1TS U1501 ( .A(n1116), .B(n1115), .Y(n1157) );
INVX2TS U1502 ( .A(n1117), .Y(n1155) );
AOI22X1TS U1503 ( .A0(Data_array_SWR[22]), .A1(n1155), .B0(
Data_array_SWR[18]), .B1(n1154), .Y(n1543) );
INVX2TS U1504 ( .A(n1543), .Y(n1156) );
INVX2TS U1505 ( .A(DP_OP_15J39_125_2314_n4), .Y(n1118) );
NAND2X1TS U1506 ( .A(n1664), .B(n1118), .Y(n1124) );
INVX2TS U1507 ( .A(exp_rslt_NRM2_EW1[3]), .Y(n1120) );
INVX2TS U1508 ( .A(exp_rslt_NRM2_EW1[2]), .Y(n1119) );
INVX2TS U1509 ( .A(n1124), .Y(n1125) );
NAND2X1TS U1510 ( .A(n1675), .B(n1125), .Y(n1131) );
XNOR2X1TS U1511 ( .A(DMP_exp_NRM2_EW[7]), .B(n1131), .Y(n1127) );
INVX2TS U1512 ( .A(n1482), .Y(n1410) );
INVX2TS U1513 ( .A(n1127), .Y(n1409) );
AND4X1TS U1514 ( .A(exp_rslt_NRM2_EW1[3]), .B(n1418), .C(
exp_rslt_NRM2_EW1[2]), .D(exp_rslt_NRM2_EW1[1]), .Y(n1128) );
INVX2TS U1515 ( .A(n1131), .Y(n1132) );
OAI2BB2XLTS U1516 ( .B0(n1589), .B1(n962), .A0N(final_result_ieee[5]), .A1N(
n1724), .Y(n546) );
AOI22X1TS U1517 ( .A0(Data_array_SWR[14]), .A1(n998), .B0(Data_array_SWR[10]), .B1(n995), .Y(n1136) );
AOI22X1TS U1518 ( .A0(Data_array_SWR[22]), .A1(n1150), .B0(
Data_array_SWR[18]), .B1(n1582), .Y(n1135) );
NAND2X1TS U1519 ( .A(n1136), .B(n1135), .Y(n1138) );
AOI22X1TS U1520 ( .A0(Data_array_SWR[23]), .A1(n1155), .B0(
Data_array_SWR[19]), .B1(n1154), .Y(n1551) );
INVX2TS U1521 ( .A(n1551), .Y(n1137) );
OAI2BB2XLTS U1522 ( .B0(n1605), .B1(n963), .A0N(final_result_ieee[17]),
.A1N(n1724), .Y(n564) );
OAI2BB2XLTS U1523 ( .B0(n1570), .B1(n963), .A0N(final_result_ieee[4]), .A1N(
n1724), .Y(n565) );
AOI22X1TS U1524 ( .A0(Data_array_SWR[17]), .A1(n998), .B0(Data_array_SWR[13]), .B1(n995), .Y(n1140) );
AOI22X1TS U1525 ( .A0(Data_array_SWR[21]), .A1(n1582), .B0(
Data_array_SWR[25]), .B1(n1150), .Y(n1139) );
NAND2X1TS U1526 ( .A(n1140), .B(n1139), .Y(n1142) );
INVX2TS U1527 ( .A(n1536), .Y(n1141) );
OAI2BB2XLTS U1528 ( .B0(n1602), .B1(n963), .A0N(final_result_ieee[14]),
.A1N(n1724), .Y(n556) );
OAI2BB2XLTS U1529 ( .B0(n1576), .B1(n963), .A0N(final_result_ieee[7]), .A1N(
n1724), .Y(n557) );
AOI22X1TS U1530 ( .A0(Data_array_SWR[20]), .A1(n1154), .B0(
Data_array_SWR[24]), .B1(n1155), .Y(n1149) );
AOI22X1TS U1531 ( .A0(Data_array_SWR[12]), .A1(n997), .B0(Data_array_SWR[8]),
.B1(n995), .Y(n1144) );
NAND2X1TS U1532 ( .A(Data_array_SWR[16]), .B(n1582), .Y(n1143) );
OAI211X1TS U1533 ( .A0(n1149), .A1(n1655), .B0(n1144), .C0(n1143), .Y(n1145)
);
AO22X1TS U1534 ( .A0(Data_array_SWR[25]), .A1(n1155), .B0(Data_array_SWR[21]), .B1(n1154), .Y(n1146) );
OAI2BB2XLTS U1535 ( .B0(n1607), .B1(n962), .A0N(final_result_ieee[19]),
.A1N(n1724), .Y(n561) );
OAI2BB2XLTS U1536 ( .B0(n1571), .B1(n962), .A0N(final_result_ieee[2]), .A1N(
n1724), .Y(n562) );
AOI22X1TS U1537 ( .A0(Data_array_SWR[13]), .A1(n998), .B0(Data_array_SWR[9]),
.B1(n1078), .Y(n1148) );
AOI22X1TS U1538 ( .A0(Data_array_SWR[17]), .A1(n1582), .B0(
shift_value_SHT2_EWR[4]), .B1(n1146), .Y(n1147) );
NAND2X1TS U1539 ( .A(n1148), .B(n1147), .Y(n1160) );
INVX2TS U1540 ( .A(n1149), .Y(n1159) );
OAI2BB2XLTS U1541 ( .B0(n1577), .B1(n963), .A0N(final_result_ieee[3]), .A1N(
n1724), .Y(n554) );
AOI22X1TS U1542 ( .A0(Data_array_SWR[12]), .A1(n1078), .B0(
Data_array_SWR[16]), .B1(n997), .Y(n1152) );
AOI22X1TS U1543 ( .A0(Data_array_SWR[20]), .A1(n1582), .B0(
Data_array_SWR[24]), .B1(n1150), .Y(n1151) );
NAND2X1TS U1544 ( .A(n1152), .B(n1151), .Y(n1163) );
INVX2TS U1545 ( .A(n1518), .Y(n1162) );
OAI2BB2XLTS U1546 ( .B0(n1603), .B1(n963), .A0N(final_result_ieee[15]),
.A1N(n1724), .Y(n541) );
OAI2BB2XLTS U1547 ( .B0(n1604), .B1(n963), .A0N(final_result_ieee[16]),
.A1N(n1724), .Y(n545) );
OAI2BB2XLTS U1548 ( .B0(n1606), .B1(n963), .A0N(final_result_ieee[18]),
.A1N(n1724), .Y(n553) );
OAI2BB2XLTS U1549 ( .B0(n1522), .B1(n963), .A0N(final_result_ieee[6]), .A1N(
n1005), .Y(n542) );
AOI32X1TS U1550 ( .A0(Shift_amount_SHT1_EWR[3]), .A1(n1470), .A2(n1450),
.B0(shift_value_SHT2_EWR[3]), .B1(n1451), .Y(n1172) );
OAI211X1TS U1551 ( .A0(Raw_mant_NRM_SWR[11]), .A1(Raw_mant_NRM_SWR[13]),
.B0(n1164), .C0(n1636), .Y(n1174) );
NAND2X1TS U1552 ( .A(Raw_mant_NRM_SWR[1]), .B(n1165), .Y(n1329) );
OAI2BB1X1TS U1553 ( .A0N(n1167), .A1N(n1636), .B0(n1166), .Y(n1168) );
OAI21X1TS U1554 ( .A0(n1171), .A1(n1170), .B0(Shift_reg_FLAGS_7[1]), .Y(
n1416) );
NAND2X1TS U1555 ( .A(n1172), .B(n1416), .Y(n830) );
OAI21XLTS U1556 ( .A0(n1176), .A1(n1175), .B0(n1174), .Y(n1181) );
OAI22X1TS U1557 ( .A0(Raw_mant_NRM_SWR[6]), .A1(n1323), .B0(n1178), .B1(
n1677), .Y(n1179) );
OAI31X1TS U1558 ( .A0(n1181), .A1(n1180), .A2(n1179), .B0(
Shift_reg_FLAGS_7[1]), .Y(n1417) );
NAND2X1TS U1559 ( .A(n1182), .B(n1417), .Y(n831) );
OAI21XLTS U1560 ( .A0(n1490), .A1(n966), .B0(n1450), .Y(n890) );
AOI22X1TS U1561 ( .A0(OP_FLAG_SFG), .A1(DmP_mant_SFG_SWR[2]), .B0(n1520),
.B1(n1014), .Y(n1183) );
NOR2XLTS U1562 ( .A(n1183), .B(DMP_SFG[0]), .Y(n1184) );
OAI32X1TS U1563 ( .A0(n1726), .A1(n1544), .A2(n1184), .B0(n1725), .B1(n1641),
.Y(n575) );
AOI2BB2XLTS U1564 ( .B0(beg_OP), .B1(n1652), .A0N(n1652), .A1N(
inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n1185) );
AOI22X1TS U1565 ( .A0(n1539), .A1(DmP_mant_SFG_SWR[4]), .B0(n1538), .B1(
n1023), .Y(n1186) );
NAND2X1TS U1566 ( .A(DMP_SFG[2]), .B(n1186), .Y(n1553) );
INVX2TS U1567 ( .A(n1553), .Y(n1493) );
NOR3X1TS U1568 ( .A(n1555), .B(n1493), .C(n1554), .Y(n1507) );
OA21XLTS U1569 ( .A0(n1555), .A1(n1493), .B0(n1554), .Y(n1187) );
OAI32X1TS U1570 ( .A0(n1726), .A1(n1507), .A2(n1187), .B0(n1725), .B1(n941),
.Y(n570) );
NOR2X1TS U1571 ( .A(n1665), .B(intDX_EWSW[25]), .Y(n1248) );
AOI22X1TS U1572 ( .A0(intDX_EWSW[25]), .A1(n1665), .B0(intDX_EWSW[24]), .B1(
n1188), .Y(n1192) );
OAI21X1TS U1573 ( .A0(intDX_EWSW[26]), .A1(n1689), .B0(n1189), .Y(n1249) );
NOR2X1TS U1574 ( .A(n1649), .B(intDX_EWSW[30]), .Y(n1195) );
NOR2X1TS U1575 ( .A(n1625), .B(intDX_EWSW[29]), .Y(n1193) );
AOI211X1TS U1576 ( .A0(intDY_EWSW[28]), .A1(n1671), .B0(n1195), .C0(n1193),
.Y(n1247) );
NOR3X1TS U1577 ( .A(n1671), .B(n1193), .C(intDY_EWSW[28]), .Y(n1194) );
AOI2BB2X1TS U1578 ( .B0(n1197), .B1(n1247), .A0N(n1196), .A1N(n1195), .Y(
n1253) );
NOR2X1TS U1579 ( .A(n1668), .B(intDX_EWSW[17]), .Y(n1234) );
INVX2TS U1580 ( .A(n1198), .Y(n1218) );
OAI2BB1X1TS U1581 ( .A0N(n1642), .A1N(intDY_EWSW[5]), .B0(intDX_EWSW[4]),
.Y(n1199) );
OAI22X1TS U1582 ( .A0(intDY_EWSW[4]), .A1(n1199), .B0(n1642), .B1(
intDY_EWSW[5]), .Y(n1210) );
OAI2BB1X1TS U1583 ( .A0N(n1623), .A1N(intDY_EWSW[7]), .B0(intDX_EWSW[6]),
.Y(n1200) );
OAI22X1TS U1584 ( .A0(intDY_EWSW[6]), .A1(n1200), .B0(n1623), .B1(
intDY_EWSW[7]), .Y(n1209) );
OAI2BB2XLTS U1585 ( .B0(intDY_EWSW[0]), .B1(n1201), .A0N(intDX_EWSW[1]),
.A1N(n1669), .Y(n1203) );
AOI222X1TS U1586 ( .A0(intDY_EWSW[4]), .A1(n1621), .B0(n1206), .B1(n1205),
.C0(intDY_EWSW[5]), .C1(n1642), .Y(n1208) );
AOI22X1TS U1587 ( .A0(intDY_EWSW[7]), .A1(n1623), .B0(intDY_EWSW[6]), .B1(
n1644), .Y(n1207) );
OAI32X1TS U1588 ( .A0(n1210), .A1(n1209), .A2(n1208), .B0(n1207), .B1(n1209),
.Y(n1228) );
OA22X1TS U1589 ( .A0(n1436), .A1(intDX_EWSW[14]), .B0(n1667), .B1(
intDX_EWSW[15]), .Y(n1225) );
AOI22X1TS U1590 ( .A0(intDX_EWSW[11]), .A1(n1691), .B0(n1004), .B1(n1214),
.Y(n1220) );
AOI21X1TS U1591 ( .A0(n1217), .A1(n1216), .B0(n1227), .Y(n1219) );
OAI2BB2XLTS U1592 ( .B0(n1220), .B1(n1227), .A0N(n1219), .A1N(n1218), .Y(
n1223) );
OAI2BB2XLTS U1593 ( .B0(intDY_EWSW[14]), .B1(n1221), .A0N(intDX_EWSW[15]),
.A1N(n1667), .Y(n1222) );
AOI211X1TS U1594 ( .A0(n1225), .A1(n1224), .B0(n1223), .C0(n1222), .Y(n1226)
);
OAI31X1TS U1595 ( .A0(n1229), .A1(n1228), .A2(n1227), .B0(n1226), .Y(n1232)
);
OA22X1TS U1596 ( .A0(n1440), .A1(intDX_EWSW[22]), .B0(n1672), .B1(
intDX_EWSW[23]), .Y(n1245) );
OAI2BB2XLTS U1597 ( .B0(intDY_EWSW[20]), .B1(n1233), .A0N(intDX_EWSW[21]),
.A1N(n1658), .Y(n1244) );
AOI22X1TS U1598 ( .A0(intDX_EWSW[17]), .A1(n1668), .B0(intDX_EWSW[16]), .B1(
n1235), .Y(n1238) );
OAI32X1TS U1599 ( .A0(n1240), .A1(n1239), .A2(n1238), .B0(n1237), .B1(n1239),
.Y(n1243) );
OAI2BB2XLTS U1600 ( .B0(intDY_EWSW[22]), .B1(n1241), .A0N(intDX_EWSW[23]),
.A1N(n1672), .Y(n1242) );
AOI211X1TS U1601 ( .A0(n1245), .A1(n1244), .B0(n1243), .C0(n1242), .Y(n1251)
);
NAND4BBX1TS U1602 ( .AN(n1249), .BN(n1248), .C(n1247), .D(n1246), .Y(n1250)
);
AOI32X1TS U1603 ( .A0(n1253), .A1(n1252), .A2(n1251), .B0(n1250), .B1(n1253),
.Y(n1254) );
AND2X2TS U1604 ( .A(Shift_reg_FLAGS_7_6), .B(n1254), .Y(n1294) );
BUFX3TS U1605 ( .A(n991), .Y(n1426) );
AOI22X1TS U1606 ( .A0(intDX_EWSW[19]), .A1(n1255), .B0(DmP_EXP_EWSW[19]),
.B1(n1426), .Y(n1256) );
BUFX3TS U1607 ( .A(n1624), .Y(n1311) );
AOI22X1TS U1608 ( .A0(intDY_EWSW[28]), .A1(n1255), .B0(DMP_EXP_EWSW[28]),
.B1(n1311), .Y(n1257) );
AOI22X1TS U1609 ( .A0(intDX_EWSW[14]), .A1(n1255), .B0(DmP_EXP_EWSW[14]),
.B1(n1426), .Y(n1258) );
AOI22X1TS U1610 ( .A0(intDX_EWSW[22]), .A1(n1255), .B0(DmP_EXP_EWSW[22]),
.B1(n1426), .Y(n1259) );
INVX2TS U1611 ( .A(n1294), .Y(n1296) );
AOI22X1TS U1612 ( .A0(intDY_EWSW[29]), .A1(n933), .B0(DMP_EXP_EWSW[29]),
.B1(n1311), .Y(n1260) );
AOI22X1TS U1613 ( .A0(intDY_EWSW[30]), .A1(n933), .B0(DMP_EXP_EWSW[30]),
.B1(n1311), .Y(n1261) );
AOI22X1TS U1614 ( .A0(intDX_EWSW[16]), .A1(n933), .B0(DmP_EXP_EWSW[16]),
.B1(n1426), .Y(n1262) );
AOI22X1TS U1615 ( .A0(intDX_EWSW[17]), .A1(n933), .B0(DmP_EXP_EWSW[17]),
.B1(n1426), .Y(n1263) );
BUFX3TS U1616 ( .A(n991), .Y(n1283) );
AOI22X1TS U1617 ( .A0(intDX_EWSW[13]), .A1(n933), .B0(DmP_EXP_EWSW[13]),
.B1(n1283), .Y(n1264) );
AOI22X1TS U1618 ( .A0(intDX_EWSW[21]), .A1(n933), .B0(DmP_EXP_EWSW[21]),
.B1(n1426), .Y(n1265) );
AOI22X1TS U1619 ( .A0(intDX_EWSW[20]), .A1(n933), .B0(DmP_EXP_EWSW[20]),
.B1(n1426), .Y(n1266) );
AOI22X1TS U1620 ( .A0(intDX_EWSW[7]), .A1(n1281), .B0(DmP_EXP_EWSW[7]), .B1(
n1283), .Y(n1267) );
AOI22X1TS U1621 ( .A0(intDX_EWSW[5]), .A1(n1281), .B0(DmP_EXP_EWSW[5]), .B1(
n1283), .Y(n1268) );
AOI22X1TS U1622 ( .A0(intDX_EWSW[4]), .A1(n1281), .B0(DmP_EXP_EWSW[4]), .B1(
n1283), .Y(n1269) );
AOI22X1TS U1623 ( .A0(intDX_EWSW[6]), .A1(n1281), .B0(DmP_EXP_EWSW[6]), .B1(
n1283), .Y(n1270) );
AOI22X1TS U1624 ( .A0(intDX_EWSW[11]), .A1(n1281), .B0(DmP_EXP_EWSW[11]),
.B1(n1283), .Y(n1271) );
AOI22X1TS U1625 ( .A0(intDX_EWSW[8]), .A1(n1281), .B0(DmP_EXP_EWSW[8]), .B1(
n1283), .Y(n1272) );
AOI22X1TS U1626 ( .A0(intDX_EWSW[12]), .A1(n1281), .B0(DmP_EXP_EWSW[12]),
.B1(n1426), .Y(n1273) );
AOI22X1TS U1627 ( .A0(intDX_EWSW[18]), .A1(n1281), .B0(DmP_EXP_EWSW[18]),
.B1(n1426), .Y(n1274) );
AOI22X1TS U1628 ( .A0(intDX_EWSW[0]), .A1(n1281), .B0(DmP_EXP_EWSW[0]), .B1(
n1283), .Y(n1275) );
AOI22X1TS U1629 ( .A0(n1004), .A1(n1281), .B0(DmP_EXP_EWSW[10]), .B1(n1311),
.Y(n1276) );
AOI22X1TS U1630 ( .A0(intDX_EWSW[3]), .A1(n1281), .B0(DmP_EXP_EWSW[3]), .B1(
n1283), .Y(n1277) );
AOI22X1TS U1631 ( .A0(intDX_EWSW[9]), .A1(n1281), .B0(DmP_EXP_EWSW[9]), .B1(
n1283), .Y(n1278) );
AOI22X1TS U1632 ( .A0(intDX_EWSW[1]), .A1(n1281), .B0(DmP_EXP_EWSW[1]), .B1(
n1283), .Y(n1279) );
AOI22X1TS U1633 ( .A0(intDX_EWSW[2]), .A1(n1281), .B0(DmP_EXP_EWSW[2]), .B1(
n1283), .Y(n1280) );
AOI22X1TS U1634 ( .A0(DmP_EXP_EWSW[27]), .A1(n1426), .B0(intDX_EWSW[27]),
.B1(n1281), .Y(n1282) );
AOI22X1TS U1635 ( .A0(intDX_EWSW[15]), .A1(n1255), .B0(DmP_EXP_EWSW[15]),
.B1(n1283), .Y(n1284) );
BUFX3TS U1636 ( .A(n1294), .Y(n1320) );
AOI22X1TS U1637 ( .A0(intDX_EWSW[7]), .A1(n1320), .B0(DMP_EXP_EWSW[7]), .B1(
n991), .Y(n1286) );
AOI22X1TS U1638 ( .A0(DMP_EXP_EWSW[23]), .A1(n1426), .B0(intDX_EWSW[23]),
.B1(n1294), .Y(n1287) );
AOI22X1TS U1639 ( .A0(intDX_EWSW[8]), .A1(n1320), .B0(DMP_EXP_EWSW[8]), .B1(
n991), .Y(n1288) );
AOI22X1TS U1640 ( .A0(intDX_EWSW[9]), .A1(n1320), .B0(DMP_EXP_EWSW[9]), .B1(
n991), .Y(n1289) );
BUFX3TS U1641 ( .A(n1320), .Y(n1312) );
AOI22X1TS U1642 ( .A0(intDX_EWSW[16]), .A1(n1312), .B0(DMP_EXP_EWSW[16]),
.B1(n991), .Y(n1290) );
AOI22X1TS U1643 ( .A0(intDX_EWSW[21]), .A1(n1320), .B0(DMP_EXP_EWSW[21]),
.B1(n1311), .Y(n1291) );
AOI22X1TS U1644 ( .A0(intDX_EWSW[0]), .A1(n1320), .B0(DMP_EXP_EWSW[0]), .B1(
n1624), .Y(n1292) );
AOI22X1TS U1645 ( .A0(intDX_EWSW[20]), .A1(n1294), .B0(DMP_EXP_EWSW[20]),
.B1(n1311), .Y(n1293) );
AOI22X1TS U1646 ( .A0(intDX_EWSW[22]), .A1(n1294), .B0(DMP_EXP_EWSW[22]),
.B1(n1311), .Y(n1295) );
AOI22X1TS U1647 ( .A0(intDX_EWSW[31]), .A1(n1297), .B0(SIGN_FLAG_EXP), .B1(
n1311), .Y(n1298) );
AOI22X1TS U1648 ( .A0(intDX_EWSW[19]), .A1(n1312), .B0(DMP_EXP_EWSW[19]),
.B1(n1311), .Y(n1301) );
AOI22X1TS U1649 ( .A0(intDX_EWSW[18]), .A1(n1312), .B0(DMP_EXP_EWSW[18]),
.B1(n1311), .Y(n1302) );
AOI22X1TS U1650 ( .A0(n1004), .A1(n1312), .B0(DMP_EXP_EWSW[10]), .B1(n1311),
.Y(n1303) );
AOI222X1TS U1651 ( .A0(n933), .A1(intDX_EWSW[23]), .B0(DmP_EXP_EWSW[23]),
.B1(n1624), .C0(intDY_EWSW[23]), .C1(n1312), .Y(n1304) );
INVX2TS U1652 ( .A(n1304), .Y(n625) );
AOI22X1TS U1653 ( .A0(intDX_EWSW[17]), .A1(n1312), .B0(DMP_EXP_EWSW[17]),
.B1(n1311), .Y(n1305) );
AOI22X1TS U1654 ( .A0(intDX_EWSW[11]), .A1(n1312), .B0(DMP_EXP_EWSW[11]),
.B1(n991), .Y(n1306) );
AOI22X1TS U1655 ( .A0(intDX_EWSW[12]), .A1(n1312), .B0(DMP_EXP_EWSW[12]),
.B1(n991), .Y(n1307) );
AOI22X1TS U1656 ( .A0(intDX_EWSW[14]), .A1(n1312), .B0(DMP_EXP_EWSW[14]),
.B1(n991), .Y(n1308) );
AOI22X1TS U1657 ( .A0(n984), .A1(n1426), .B0(intDX_EWSW[27]), .B1(n1312),
.Y(n1309) );
AOI22X1TS U1658 ( .A0(intDX_EWSW[13]), .A1(n1312), .B0(DMP_EXP_EWSW[13]),
.B1(n991), .Y(n1310) );
AOI22X1TS U1659 ( .A0(intDX_EWSW[15]), .A1(n1312), .B0(DMP_EXP_EWSW[15]),
.B1(n1311), .Y(n1313) );
INVX2TS U1660 ( .A(n933), .Y(n1322) );
AOI22X1TS U1661 ( .A0(intDX_EWSW[4]), .A1(n1320), .B0(DMP_EXP_EWSW[4]), .B1(
n991), .Y(n1315) );
AOI22X1TS U1662 ( .A0(intDX_EWSW[5]), .A1(n1320), .B0(DMP_EXP_EWSW[5]), .B1(
n991), .Y(n1316) );
AOI22X1TS U1663 ( .A0(intDX_EWSW[3]), .A1(n1320), .B0(DMP_EXP_EWSW[3]), .B1(
n991), .Y(n1317) );
AOI22X1TS U1664 ( .A0(intDX_EWSW[2]), .A1(n1320), .B0(DMP_EXP_EWSW[2]), .B1(
n1624), .Y(n1318) );
AOI22X1TS U1665 ( .A0(intDX_EWSW[6]), .A1(n1320), .B0(DMP_EXP_EWSW[6]), .B1(
n991), .Y(n1319) );
AOI22X1TS U1666 ( .A0(intDX_EWSW[1]), .A1(n1320), .B0(DMP_EXP_EWSW[1]), .B1(
n991), .Y(n1321) );
NOR2XLTS U1667 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[9]), .Y(n1325)
);
AOI211X1TS U1668 ( .A0(Raw_mant_NRM_SWR[4]), .A1(n1328), .B0(n1327), .C0(
n1326), .Y(n1331) );
AOI31X1TS U1669 ( .A0(n1331), .A1(n1330), .A2(n1329), .B0(n946), .Y(n1415)
);
INVX2TS U1670 ( .A(DMP_SFG[10]), .Y(intadd_44_A_0_) );
INVX2TS U1671 ( .A(DMP_SFG[11]), .Y(intadd_44_A_1_) );
INVX2TS U1672 ( .A(DMP_SFG[12]), .Y(intadd_44_A_2_) );
INVX2TS U1673 ( .A(DMP_SFG[13]), .Y(intadd_44_A_3_) );
INVX2TS U1674 ( .A(DMP_SFG[14]), .Y(intadd_44_A_4_) );
INVX2TS U1675 ( .A(DMP_SFG[15]), .Y(intadd_44_A_5_) );
INVX2TS U1676 ( .A(DMP_SFG[16]), .Y(intadd_44_A_6_) );
INVX2TS U1677 ( .A(DMP_SFG[17]), .Y(intadd_44_A_7_) );
INVX2TS U1678 ( .A(DMP_SFG[18]), .Y(intadd_44_A_8_) );
INVX2TS U1679 ( .A(DMP_SFG[19]), .Y(intadd_44_A_9_) );
AOI22X1TS U1680 ( .A0(Raw_mant_NRM_SWR[24]), .A1(n1466), .B0(n1462), .B1(
n983), .Y(n1339) );
AOI22X1TS U1681 ( .A0(n1451), .A1(Data_array_SWR[1]), .B0(
Raw_mant_NRM_SWR[23]), .B1(n1395), .Y(n1338) );
AOI22X1TS U1682 ( .A0(Raw_mant_NRM_SWR[21]), .A1(n1452), .B0(n1462), .B1(
DmP_mant_SHT1_SW[2]), .Y(n1336) );
AOI22X1TS U1683 ( .A0(Raw_mant_NRM_SWR[22]), .A1(n1466), .B0(n1002), .B1(
n982), .Y(n1335) );
NAND2X1TS U1684 ( .A(n1336), .B(n1335), .Y(n1351) );
NAND2X1TS U1685 ( .A(n1360), .B(n1351), .Y(n1337) );
AOI22X1TS U1686 ( .A0(Raw_mant_NRM_SWR[17]), .A1(n1452), .B0(n1462), .B1(
DmP_mant_SHT1_SW[6]), .Y(n1342) );
AOI22X1TS U1687 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1466), .B0(n1002), .B1(
n981), .Y(n1341) );
NAND2X1TS U1688 ( .A(n1342), .B(n1341), .Y(n1346) );
AOI22X1TS U1689 ( .A0(n1451), .A1(Data_array_SWR[5]), .B0(n1360), .B1(n1346),
.Y(n1344) );
NAND2X1TS U1690 ( .A(Raw_mant_NRM_SWR[19]), .B(n1395), .Y(n1343) );
INVX2TS U1691 ( .A(n1360), .Y(n1345) );
AOI22X1TS U1692 ( .A0(n1451), .A1(Data_array_SWR[7]), .B0(n999), .B1(n1346),
.Y(n1350) );
BUFX3TS U1693 ( .A(n1348), .Y(n1399) );
NAND2X1TS U1694 ( .A(Raw_mant_NRM_SWR[15]), .B(n1399), .Y(n1349) );
AOI22X1TS U1695 ( .A0(n1451), .A1(Data_array_SWR[3]), .B0(n999), .B1(n1351),
.Y(n1353) );
NAND2X1TS U1696 ( .A(Raw_mant_NRM_SWR[19]), .B(n1399), .Y(n1352) );
AOI22X1TS U1697 ( .A0(Raw_mant_NRM_SWR[18]), .A1(n1452), .B0(n1462), .B1(
n981), .Y(n1356) );
AOI22X1TS U1698 ( .A0(Raw_mant_NRM_SWR[19]), .A1(n1466), .B0(n1002), .B1(
n977), .Y(n1355) );
NAND2X1TS U1699 ( .A(n1356), .B(n1355), .Y(n1359) );
AOI22X1TS U1700 ( .A0(n1451), .A1(Data_array_SWR[6]), .B0(n999), .B1(n1359),
.Y(n1358) );
NAND2X1TS U1701 ( .A(Raw_mant_NRM_SWR[16]), .B(n1399), .Y(n1357) );
AOI22X1TS U1702 ( .A0(n1451), .A1(Data_array_SWR[4]), .B0(n1360), .B1(n1359),
.Y(n1362) );
NAND2X1TS U1703 ( .A(Raw_mant_NRM_SWR[20]), .B(n1395), .Y(n1361) );
AOI22X1TS U1704 ( .A0(n1451), .A1(Data_array_SWR[2]), .B0(n999), .B1(n1363),
.Y(n1365) );
NAND2X1TS U1705 ( .A(Raw_mant_NRM_SWR[20]), .B(n1399), .Y(n1364) );
AOI22X1TS U1706 ( .A0(n1380), .A1(Data_array_SWR[11]), .B0(
Raw_mant_NRM_SWR[11]), .B1(n1399), .Y(n1368) );
AOI22X1TS U1707 ( .A0(n1451), .A1(Data_array_SWR[19]), .B0(
Raw_mant_NRM_SWR[3]), .B1(n1399), .Y(n1370) );
AOI22X1TS U1708 ( .A0(n1380), .A1(Data_array_SWR[9]), .B0(
Raw_mant_NRM_SWR[13]), .B1(n1399), .Y(n1373) );
AOI22X1TS U1709 ( .A0(n1380), .A1(Data_array_SWR[21]), .B0(
Raw_mant_NRM_SWR[1]), .B1(n1399), .Y(n1376) );
OA22X1TS U1710 ( .A0(n1677), .A1(n1405), .B0(n1393), .B1(n1345), .Y(n1375)
);
AOI22X1TS U1711 ( .A0(n1380), .A1(Data_array_SWR[15]), .B0(
Raw_mant_NRM_SWR[7]), .B1(n1399), .Y(n1379) );
OA22X1TS U1712 ( .A0(n1653), .A1(n1405), .B0(n1388), .B1(n1345), .Y(n1378)
);
AOI22X1TS U1713 ( .A0(n1380), .A1(Data_array_SWR[13]), .B0(
Raw_mant_NRM_SWR[9]), .B1(n1399), .Y(n1383) );
OA22X1TS U1714 ( .A0(n1637), .A1(n1405), .B0(n1381), .B1(n1345), .Y(n1382)
);
AOI22X1TS U1715 ( .A0(n1380), .A1(Data_array_SWR[17]), .B0(
Raw_mant_NRM_SWR[5]), .B1(n1399), .Y(n1387) );
OA22X1TS U1716 ( .A0(n1639), .A1(n1405), .B0(n1385), .B1(n1345), .Y(n1386)
);
AOI22X1TS U1717 ( .A0(n1002), .A1(DmP_mant_SHT1_SW[18]), .B0(n1462), .B1(
DmP_mant_SHT1_SW[19]), .Y(n1389) );
AOI21X1TS U1718 ( .A0(Raw_mant_NRM_SWR[5]), .A1(n1466), .B0(n1390), .Y(n1457) );
OAI22X1TS U1719 ( .A0(n1400), .A1(n1000), .B0(n1643), .B1(n1405), .Y(n1391)
);
AOI21X1TS U1720 ( .A0(n1451), .A1(Data_array_SWR[18]), .B0(n1391), .Y(n1392)
);
AOI21X1TS U1721 ( .A0(n1466), .A1(Raw_mant_NRM_SWR[0]), .B0(n1003), .Y(n1447) );
OAI2BB2XLTS U1722 ( .B0(n1393), .B1(n1000), .A0N(n1380), .A1N(
Data_array_SWR[23]), .Y(n1394) );
AOI21X1TS U1723 ( .A0(Raw_mant_NRM_SWR[1]), .A1(n1395), .B0(n1394), .Y(n1396) );
AOI22X1TS U1724 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n1452), .B0(n1462), .B1(
DmP_mant_SHT1_SW[15]), .Y(n1397) );
AOI21X1TS U1725 ( .A0(n1003), .A1(DmP_mant_SHT1_SW[14]), .B0(n1398), .Y(
n1461) );
OAI2BB2XLTS U1726 ( .B0(n1400), .B1(n1345), .A0N(Raw_mant_NRM_SWR[6]), .A1N(
n1399), .Y(n1401) );
AOI21X1TS U1727 ( .A0(n1451), .A1(Data_array_SWR[16]), .B0(n1401), .Y(n1402)
);
AOI22X1TS U1728 ( .A0(n1002), .A1(n980), .B0(n1462), .B1(DmP_mant_SHT1_SW[9]), .Y(n1403) );
AOI21X1TS U1729 ( .A0(Raw_mant_NRM_SWR[15]), .A1(n1466), .B0(n1404), .Y(
n1468) );
OAI22X1TS U1730 ( .A0(n1406), .A1(n1000), .B0(n1679), .B1(n1405), .Y(n1407)
);
AOI21X1TS U1731 ( .A0(n1380), .A1(Data_array_SWR[8]), .B0(n1407), .Y(n1408)
);
OAI2BB2XLTS U1732 ( .B0(n1422), .B1(n1409), .A0N(n1724), .A1N(
final_result_ieee[30]), .Y(n815) );
OAI2BB2XLTS U1733 ( .B0(n1411), .B1(n1422), .A0N(n1724), .A1N(
final_result_ieee[31]), .Y(n604) );
INVX2TS U1734 ( .A(n1412), .Y(n1413) );
NAND2X1TS U1735 ( .A(n1646), .B(n1413), .Y(DP_OP_15J39_125_2314_n8) );
MX2X1TS U1736 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n672) );
MX2X1TS U1737 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n677) );
MX2X1TS U1738 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n682) );
MX2X1TS U1739 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n687) );
MX2X1TS U1740 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n692) );
MX2X1TS U1741 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n697) );
MX2X1TS U1742 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n702) );
MX2X1TS U1743 ( .A(DMP_exp_NRM2_EW[0]), .B(DMP_exp_NRM_EW[0]), .S0(
Shift_reg_FLAGS_7[1]), .Y(n707) );
OAI2BB1X1TS U1744 ( .A0N(LZD_output_NRM2_EW[3]), .A1N(n1450), .B0(n1416),
.Y(n573) );
OAI2BB1X1TS U1745 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n1450), .B0(n1417),
.Y(n584) );
OAI2BB1X1TS U1746 ( .A0N(LZD_output_NRM2_EW[0]), .A1N(n1450), .B0(n1464),
.Y(n579) );
NAND2X2TS U1747 ( .A(n1482), .B(Shift_reg_FLAGS_7[0]), .Y(n1421) );
OA22X1TS U1748 ( .A0(n1421), .A1(n1418), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[23]), .Y(n822) );
OA22X1TS U1749 ( .A0(n1421), .A1(exp_rslt_NRM2_EW1[1]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[24]), .Y(n821) );
OA22X1TS U1750 ( .A0(n1421), .A1(exp_rslt_NRM2_EW1[2]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[25]), .Y(n820) );
OA22X1TS U1751 ( .A0(n1421), .A1(exp_rslt_NRM2_EW1[3]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[26]), .Y(n819) );
OA22X1TS U1752 ( .A0(n1421), .A1(exp_rslt_NRM2_EW1[4]), .B0(
Shift_reg_FLAGS_7[0]), .B1(final_result_ieee[27]), .Y(n818) );
OA22X1TS U1753 ( .A0(n1421), .A1(n1419), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[28]), .Y(n817) );
OA22X1TS U1754 ( .A0(n1421), .A1(n1420), .B0(Shift_reg_FLAGS_7[0]), .B1(
final_result_ieee[29]), .Y(n816) );
OA21XLTS U1755 ( .A0(Shift_reg_FLAGS_7[0]), .A1(overflow_flag), .B0(n1422),
.Y(n619) );
INVX2TS U1756 ( .A(n1423), .Y(n1425) );
AOI22X1TS U1757 ( .A0(inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1425), .B1(n1652), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
NAND2X1TS U1758 ( .A(n1425), .B(n1424), .Y(n932) );
AOI22X1TS U1759 ( .A0(n1428), .A1(n1426), .B0(n1488), .B1(n1427), .Y(n929)
);
AOI22X1TS U1760 ( .A0(n1428), .A1(n1488), .B0(n975), .B1(n1427), .Y(n928) );
OAI2BB2XLTS U1761 ( .B0(n1427), .B1(n975), .A0N(n1427), .A1N(n976), .Y(n927)
);
AOI22X1TS U1762 ( .A0(n1428), .A1(n1726), .B0(n1450), .B1(n1427), .Y(n925)
);
BUFX3TS U1763 ( .A(n1430), .Y(n1431) );
INVX4TS U1764 ( .A(n1430), .Y(n1446) );
INVX4TS U1765 ( .A(n1430), .Y(n1442) );
INVX4TS U1766 ( .A(n1430), .Y(n1441) );
OAI2BB2XLTS U1767 ( .B0(n1446), .B1(n1682), .A0N(n1444), .A1N(Data_X[24]),
.Y(n899) );
OAI2BB2XLTS U1768 ( .B0(n1441), .B1(n1632), .A0N(n1441), .A1N(Data_X[25]),
.Y(n898) );
OAI2BB2XLTS U1769 ( .B0(n960), .B1(n1633), .A0N(n1444), .A1N(Data_X[26]),
.Y(n897) );
OAI2BB2XLTS U1770 ( .B0(n1442), .B1(n1671), .A0N(n961), .A1N(Data_X[28]),
.Y(n895) );
OAI2BB2XLTS U1771 ( .B0(n1446), .B1(n1673), .A0N(n1442), .A1N(Data_X[29]),
.Y(n894) );
OAI2BB2XLTS U1772 ( .B0(n1441), .B1(n950), .A0N(n1437), .A1N(Data_X[30]),
.Y(n893) );
OAI2BB2XLTS U1773 ( .B0(n1441), .B1(n1432), .A0N(n1446), .A1N(Data_Y[0]),
.Y(n889) );
OAI2BB2XLTS U1774 ( .B0(n1437), .B1(n1433), .A0N(n1444), .A1N(Data_Y[1]),
.Y(n888) );
OAI2BB2XLTS U1775 ( .B0(n1444), .B1(n947), .A0N(n1446), .A1N(Data_Y[2]), .Y(
n887) );
OAI2BB2XLTS U1776 ( .B0(n960), .B1(n1666), .A0N(n1444), .A1N(Data_Y[3]), .Y(
n886) );
OAI2BB2XLTS U1777 ( .B0(n1442), .B1(n1659), .A0N(n1443), .A1N(Data_Y[4]),
.Y(n885) );
OAI2BB2XLTS U1778 ( .B0(n1441), .B1(n1626), .A0N(n1443), .A1N(Data_Y[5]),
.Y(n884) );
OAI2BB2XLTS U1779 ( .B0(n1437), .B1(n1434), .A0N(n1443), .A1N(Data_Y[6]),
.Y(n883) );
OAI2BB2XLTS U1780 ( .B0(n960), .B1(n1663), .A0N(n1443), .A1N(Data_Y[7]), .Y(
n882) );
INVX2TS U1781 ( .A(n1430), .Y(n1443) );
OAI2BB2XLTS U1782 ( .B0(n1446), .B1(n1670), .A0N(n1443), .A1N(Data_Y[8]),
.Y(n881) );
OAI2BB2XLTS U1783 ( .B0(n1441), .B1(n985), .A0N(n1441), .A1N(Data_Y[9]), .Y(
n880) );
OAI2BB2XLTS U1784 ( .B0(n1446), .B1(n1435), .A0N(n1446), .A1N(Data_Y[10]),
.Y(n879) );
OAI2BB2XLTS U1785 ( .B0(n1437), .B1(n1691), .A0N(n1437), .A1N(Data_Y[11]),
.Y(n878) );
OAI2BB2XLTS U1786 ( .B0(n1437), .B1(n1660), .A0N(n1442), .A1N(Data_Y[12]),
.Y(n877) );
OAI2BB2XLTS U1787 ( .B0(n1446), .B1(n1001), .A0N(n1437), .A1N(Data_Y[13]),
.Y(n876) );
OAI2BB2XLTS U1788 ( .B0(n1442), .B1(n1436), .A0N(n1444), .A1N(Data_Y[14]),
.Y(n875) );
OAI2BB2XLTS U1789 ( .B0(n1441), .B1(n1667), .A0N(n1443), .A1N(Data_Y[15]),
.Y(n874) );
OAI2BB2XLTS U1790 ( .B0(n960), .B1(n948), .A0N(n1437), .A1N(Data_Y[16]), .Y(
n873) );
OAI2BB2XLTS U1791 ( .B0(n1446), .B1(n1668), .A0N(n960), .A1N(Data_Y[17]),
.Y(n872) );
OAI2BB2XLTS U1792 ( .B0(n1442), .B1(n1438), .A0N(n1443), .A1N(Data_Y[18]),
.Y(n871) );
OAI2BB2XLTS U1793 ( .B0(n1446), .B1(n1674), .A0N(n1443), .A1N(Data_Y[19]),
.Y(n870) );
OAI2BB2XLTS U1794 ( .B0(n1442), .B1(n992), .A0N(n961), .A1N(Data_Y[20]), .Y(
n869) );
OAI2BB2XLTS U1795 ( .B0(n1442), .B1(n1439), .A0N(n961), .A1N(Data_Y[21]),
.Y(n868) );
OAI2BB2XLTS U1796 ( .B0(n960), .B1(n1440), .A0N(n1443), .A1N(Data_Y[22]),
.Y(n867) );
OAI2BB2XLTS U1797 ( .B0(n1442), .B1(n1672), .A0N(n1442), .A1N(Data_Y[23]),
.Y(n866) );
OAI2BB2XLTS U1798 ( .B0(n1441), .B1(n1479), .A0N(n961), .A1N(Data_Y[24]),
.Y(n865) );
OAI2BB2XLTS U1799 ( .B0(n960), .B1(n1665), .A0N(n1443), .A1N(Data_Y[25]),
.Y(n864) );
OAI2BB2XLTS U1800 ( .B0(n1437), .B1(n1689), .A0N(n1441), .A1N(Data_Y[26]),
.Y(n863) );
OAI2BB2XLTS U1801 ( .B0(n1437), .B1(n1662), .A0N(n1444), .A1N(Data_Y[27]),
.Y(n862) );
OAI2BB2XLTS U1802 ( .B0(n1447), .B1(n1334), .A0N(n1451), .A1N(
Data_array_SWR[25]), .Y(n857) );
OAI2BB2XLTS U1803 ( .B0(n1456), .B1(n1334), .A0N(n1451), .A1N(
Data_array_SWR[24]), .Y(n856) );
AOI22X1TS U1804 ( .A0(Raw_mant_NRM_SWR[2]), .A1(n1452), .B0(
DmP_mant_SHT1_SW[21]), .B1(n1462), .Y(n1453) );
AOI21X1TS U1805 ( .A0(DmP_mant_SHT1_SW[20]), .A1(n1003), .B0(n1455), .Y(
n1458) );
OAI222X1TS U1806 ( .A0(n1470), .A1(n1678), .B0(n972), .B1(n1456), .C0(n1334),
.C1(n1458), .Y(n854) );
OAI222X1TS U1807 ( .A0(n1688), .A1(n1470), .B0(n972), .B1(n1458), .C0(n1334),
.C1(n1457), .Y(n852) );
AOI22X1TS U1808 ( .A0(n1002), .A1(DmP_mant_SHT1_SW[12]), .B0(n1462), .B1(
n978), .Y(n1459) );
AOI21X1TS U1809 ( .A0(Raw_mant_NRM_SWR[11]), .A1(n1466), .B0(n1460), .Y(
n1467) );
OAI222X1TS U1810 ( .A0(n1685), .A1(n1470), .B0(n972), .B1(n1461), .C0(n1334),
.C1(n1467), .Y(n846) );
AOI22X1TS U1811 ( .A0(n1002), .A1(DmP_mant_SHT1_SW[10]), .B0(n1462), .B1(
n979), .Y(n1463) );
AOI21X1TS U1812 ( .A0(Raw_mant_NRM_SWR[13]), .A1(n1466), .B0(n1465), .Y(
n1469) );
OAI222X1TS U1813 ( .A0(n1684), .A1(n1470), .B0(n972), .B1(n1467), .C0(n1334),
.C1(n1469), .Y(n844) );
OAI222X1TS U1814 ( .A0(n1687), .A1(n1470), .B0(n972), .B1(n1469), .C0(n1334),
.C1(n1468), .Y(n842) );
AOI21X1TS U1815 ( .A0(DMP_EXP_EWSW[23]), .A1(n1008), .B0(n1471), .Y(n1472)
);
AOI2BB2XLTS U1816 ( .B0(n1477), .B1(n1472), .A0N(Shift_amount_SHT1_EWR[0]),
.A1N(n1477), .Y(n827) );
OAI222X1TS U1817 ( .A0(n1480), .A1(n1682), .B0(n1619), .B1(
Shift_reg_FLAGS_7_6), .C0(n1479), .C1(n1481), .Y(n790) );
OAI222X1TS U1818 ( .A0(n1480), .A1(n1632), .B0(n1676), .B1(
Shift_reg_FLAGS_7_6), .C0(n1665), .C1(n1481), .Y(n789) );
OAI222X1TS U1819 ( .A0(n1480), .A1(n1633), .B0(n1683), .B1(
Shift_reg_FLAGS_7_6), .C0(n1689), .C1(n1481), .Y(n788) );
AO21XLTS U1820 ( .A0(OP_FLAG_EXP), .A1(n1624), .B0(n1473), .Y(n783) );
AO22XLTS U1821 ( .A0(n1489), .A1(DMP_EXP_EWSW[0]), .B0(n1484), .B1(
DMP_SHT1_EWSW[0]), .Y(n780) );
AO22XLTS U1822 ( .A0(n1490), .A1(DMP_SHT1_EWSW[0]), .B0(n975), .B1(
DMP_SHT2_EWSW[0]), .Y(n779) );
AO22XLTS U1823 ( .A0(n1478), .A1(DMP_EXP_EWSW[1]), .B0(n968), .B1(
DMP_SHT1_EWSW[1]), .Y(n777) );
AO22XLTS U1824 ( .A0(busy), .A1(DMP_SHT1_EWSW[1]), .B0(n975), .B1(
DMP_SHT2_EWSW[1]), .Y(n776) );
AO22XLTS U1825 ( .A0(n1486), .A1(DMP_EXP_EWSW[2]), .B0(n1484), .B1(
DMP_SHT1_EWSW[2]), .Y(n774) );
AO22XLTS U1826 ( .A0(busy), .A1(DMP_SHT1_EWSW[2]), .B0(n975), .B1(
DMP_SHT2_EWSW[2]), .Y(n773) );
AO22XLTS U1827 ( .A0(n1478), .A1(DMP_EXP_EWSW[3]), .B0(n1474), .B1(
DMP_SHT1_EWSW[3]), .Y(n771) );
AO22XLTS U1828 ( .A0(busy), .A1(DMP_SHT1_EWSW[3]), .B0(n975), .B1(
DMP_SHT2_EWSW[3]), .Y(n770) );
AO22XLTS U1829 ( .A0(n1489), .A1(DMP_EXP_EWSW[4]), .B0(n968), .B1(
DMP_SHT1_EWSW[4]), .Y(n768) );
AO22XLTS U1830 ( .A0(busy), .A1(DMP_SHT1_EWSW[4]), .B0(n1728), .B1(
DMP_SHT2_EWSW[4]), .Y(n767) );
AO22XLTS U1831 ( .A0(n1486), .A1(DMP_EXP_EWSW[5]), .B0(n1474), .B1(
DMP_SHT1_EWSW[5]), .Y(n765) );
AO22XLTS U1832 ( .A0(busy), .A1(DMP_SHT1_EWSW[5]), .B0(n1476), .B1(
DMP_SHT2_EWSW[5]), .Y(n764) );
BUFX3TS U1833 ( .A(Shift_reg_FLAGS_7_5), .Y(n1477) );
AO22XLTS U1834 ( .A0(n1477), .A1(DMP_EXP_EWSW[6]), .B0(n1474), .B1(
DMP_SHT1_EWSW[6]), .Y(n762) );
AO22XLTS U1835 ( .A0(busy), .A1(DMP_SHT1_EWSW[6]), .B0(n975), .B1(
DMP_SHT2_EWSW[6]), .Y(n761) );
AO22XLTS U1836 ( .A0(n1478), .A1(DMP_EXP_EWSW[7]), .B0(n1474), .B1(
DMP_SHT1_EWSW[7]), .Y(n759) );
AO22XLTS U1837 ( .A0(busy), .A1(DMP_SHT1_EWSW[7]), .B0(n975), .B1(
DMP_SHT2_EWSW[7]), .Y(n758) );
BUFX3TS U1838 ( .A(Shift_reg_FLAGS_7_5), .Y(n1489) );
AO22XLTS U1839 ( .A0(n1486), .A1(DMP_EXP_EWSW[8]), .B0(n1474), .B1(
DMP_SHT1_EWSW[8]), .Y(n756) );
AO22XLTS U1840 ( .A0(busy), .A1(DMP_SHT1_EWSW[8]), .B0(n975), .B1(
DMP_SHT2_EWSW[8]), .Y(n755) );
AO22XLTS U1841 ( .A0(n1477), .A1(DMP_EXP_EWSW[9]), .B0(n1474), .B1(
DMP_SHT1_EWSW[9]), .Y(n753) );
AO22XLTS U1842 ( .A0(busy), .A1(DMP_SHT1_EWSW[9]), .B0(n975), .B1(
DMP_SHT2_EWSW[9]), .Y(n752) );
AO22XLTS U1843 ( .A0(n1489), .A1(DMP_EXP_EWSW[10]), .B0(n1474), .B1(
DMP_SHT1_EWSW[10]), .Y(n750) );
INVX2TS U1844 ( .A(n1729), .Y(n1476) );
AO22XLTS U1845 ( .A0(busy), .A1(DMP_SHT1_EWSW[10]), .B0(n1476), .B1(
DMP_SHT2_EWSW[10]), .Y(n749) );
OAI2BB2XLTS U1846 ( .B0(n1487), .B1(intadd_44_A_0_), .A0N(n1600), .A1N(
DMP_SHT2_EWSW[10]), .Y(n748) );
AO22XLTS U1847 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[11]), .B0(n968),
.B1(DMP_SHT1_EWSW[11]), .Y(n747) );
AO22XLTS U1848 ( .A0(busy), .A1(DMP_SHT1_EWSW[11]), .B0(n1476), .B1(
DMP_SHT2_EWSW[11]), .Y(n746) );
OAI2BB2XLTS U1849 ( .B0(n1487), .B1(intadd_44_A_1_), .A0N(n1616), .A1N(
DMP_SHT2_EWSW[11]), .Y(n745) );
AO22XLTS U1850 ( .A0(n1477), .A1(DMP_EXP_EWSW[12]), .B0(n968), .B1(
DMP_SHT1_EWSW[12]), .Y(n744) );
AO22XLTS U1851 ( .A0(busy), .A1(DMP_SHT1_EWSW[12]), .B0(n975), .B1(
DMP_SHT2_EWSW[12]), .Y(n743) );
OAI2BB2XLTS U1852 ( .B0(n1487), .B1(intadd_44_A_2_), .A0N(n1611), .A1N(
DMP_SHT2_EWSW[12]), .Y(n742) );
AO22XLTS U1853 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[13]), .B0(n968),
.B1(DMP_SHT1_EWSW[13]), .Y(n741) );
AO22XLTS U1854 ( .A0(busy), .A1(DMP_SHT1_EWSW[13]), .B0(n1728), .B1(
DMP_SHT2_EWSW[13]), .Y(n740) );
OAI2BB2XLTS U1855 ( .B0(n1487), .B1(intadd_44_A_3_), .A0N(n1475), .A1N(
DMP_SHT2_EWSW[13]), .Y(n739) );
AO22XLTS U1856 ( .A0(n1486), .A1(DMP_EXP_EWSW[14]), .B0(n968), .B1(
DMP_SHT1_EWSW[14]), .Y(n738) );
AO22XLTS U1857 ( .A0(busy), .A1(DMP_SHT1_EWSW[14]), .B0(n1476), .B1(
DMP_SHT2_EWSW[14]), .Y(n737) );
OAI2BB2XLTS U1858 ( .B0(n1487), .B1(intadd_44_A_4_), .A0N(n1600), .A1N(
DMP_SHT2_EWSW[14]), .Y(n736) );
AO22XLTS U1859 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[15]), .B0(n968),
.B1(DMP_SHT1_EWSW[15]), .Y(n735) );
AO22XLTS U1860 ( .A0(busy), .A1(DMP_SHT1_EWSW[15]), .B0(n1476), .B1(
DMP_SHT2_EWSW[15]), .Y(n734) );
OAI2BB2XLTS U1861 ( .B0(n1487), .B1(intadd_44_A_5_), .A0N(n1475), .A1N(
DMP_SHT2_EWSW[15]), .Y(n733) );
AO22XLTS U1862 ( .A0(Shift_reg_FLAGS_7_5), .A1(DMP_EXP_EWSW[16]), .B0(n968),
.B1(DMP_SHT1_EWSW[16]), .Y(n732) );
AO22XLTS U1863 ( .A0(n1490), .A1(DMP_SHT1_EWSW[16]), .B0(n1476), .B1(
DMP_SHT2_EWSW[16]), .Y(n731) );
OAI2BB2XLTS U1864 ( .B0(n1487), .B1(intadd_44_A_6_), .A0N(n1475), .A1N(
DMP_SHT2_EWSW[16]), .Y(n730) );
AO22XLTS U1865 ( .A0(n1489), .A1(DMP_EXP_EWSW[17]), .B0(n968), .B1(
DMP_SHT1_EWSW[17]), .Y(n729) );
AO22XLTS U1866 ( .A0(n1729), .A1(DMP_SHT1_EWSW[17]), .B0(n1476), .B1(
DMP_SHT2_EWSW[17]), .Y(n728) );
OAI2BB2XLTS U1867 ( .B0(n1487), .B1(intadd_44_A_7_), .A0N(n1600), .A1N(
DMP_SHT2_EWSW[17]), .Y(n727) );
AO22XLTS U1868 ( .A0(n1478), .A1(DMP_EXP_EWSW[18]), .B0(n1484), .B1(
DMP_SHT1_EWSW[18]), .Y(n726) );
AO22XLTS U1869 ( .A0(n1729), .A1(DMP_SHT1_EWSW[18]), .B0(n1476), .B1(
DMP_SHT2_EWSW[18]), .Y(n725) );
OAI2BB2XLTS U1870 ( .B0(n1487), .B1(intadd_44_A_8_), .A0N(n1475), .A1N(
DMP_SHT2_EWSW[18]), .Y(n724) );
AO22XLTS U1871 ( .A0(n1489), .A1(DMP_EXP_EWSW[19]), .B0(n969), .B1(
DMP_SHT1_EWSW[19]), .Y(n723) );
AO22XLTS U1872 ( .A0(n1729), .A1(DMP_SHT1_EWSW[19]), .B0(n1476), .B1(
DMP_SHT2_EWSW[19]), .Y(n722) );
OAI2BB2XLTS U1873 ( .B0(n1487), .B1(intadd_44_A_9_), .A0N(n1475), .A1N(
DMP_SHT2_EWSW[19]), .Y(n721) );
AO22XLTS U1874 ( .A0(n1478), .A1(DMP_EXP_EWSW[20]), .B0(n1484), .B1(
DMP_SHT1_EWSW[20]), .Y(n720) );
AO22XLTS U1875 ( .A0(n1729), .A1(DMP_SHT1_EWSW[20]), .B0(n1476), .B1(
DMP_SHT2_EWSW[20]), .Y(n719) );
OAI2BB2XLTS U1876 ( .B0(n1487), .B1(n1010), .A0N(n1600), .A1N(
DMP_SHT2_EWSW[20]), .Y(n718) );
AO22XLTS U1877 ( .A0(n1486), .A1(DMP_EXP_EWSW[21]), .B0(n969), .B1(
DMP_SHT1_EWSW[21]), .Y(n717) );
AO22XLTS U1878 ( .A0(n1729), .A1(DMP_SHT1_EWSW[21]), .B0(n975), .B1(
DMP_SHT2_EWSW[21]), .Y(n716) );
OAI2BB2XLTS U1879 ( .B0(n1487), .B1(n1007), .A0N(n1475), .A1N(
DMP_SHT2_EWSW[21]), .Y(n715) );
AO22XLTS U1880 ( .A0(n1486), .A1(DMP_EXP_EWSW[22]), .B0(n969), .B1(
DMP_SHT1_EWSW[22]), .Y(n714) );
AO22XLTS U1881 ( .A0(n1729), .A1(DMP_SHT1_EWSW[22]), .B0(n1728), .B1(
DMP_SHT2_EWSW[22]), .Y(n713) );
OAI2BB2XLTS U1882 ( .B0(n1487), .B1(n1009), .A0N(n1475), .A1N(
DMP_SHT2_EWSW[22]), .Y(n712) );
AO22XLTS U1883 ( .A0(n1489), .A1(DMP_EXP_EWSW[23]), .B0(n1484), .B1(
DMP_SHT1_EWSW[23]), .Y(n711) );
AO22XLTS U1884 ( .A0(n1729), .A1(DMP_SHT1_EWSW[23]), .B0(n1728), .B1(
DMP_SHT2_EWSW[23]), .Y(n710) );
AO22XLTS U1885 ( .A0(n1600), .A1(DMP_SHT2_EWSW[23]), .B0(n1598), .B1(
DMP_SFG[23]), .Y(n709) );
INVX4TS U1886 ( .A(n1726), .Y(n1527) );
AO22XLTS U1887 ( .A0(n1527), .A1(DMP_SFG[23]), .B0(n1525), .B1(
DMP_exp_NRM_EW[0]), .Y(n708) );
OAI2BB2XLTS U1888 ( .B0(n1484), .B1(n1619), .A0N(n1474), .A1N(
DMP_SHT1_EWSW[24]), .Y(n706) );
AO22XLTS U1889 ( .A0(n1490), .A1(DMP_SHT1_EWSW[24]), .B0(n1728), .B1(
DMP_SHT2_EWSW[24]), .Y(n705) );
AO22XLTS U1890 ( .A0(n1475), .A1(DMP_SHT2_EWSW[24]), .B0(n1598), .B1(
DMP_SFG[24]), .Y(n704) );
AO22XLTS U1891 ( .A0(n1527), .A1(DMP_SFG[24]), .B0(n1525), .B1(
DMP_exp_NRM_EW[1]), .Y(n703) );
OAI2BB2XLTS U1892 ( .B0(n1474), .B1(n1676), .A0N(n1474), .A1N(
DMP_SHT1_EWSW[25]), .Y(n701) );
AO22XLTS U1893 ( .A0(n1490), .A1(DMP_SHT1_EWSW[25]), .B0(n1728), .B1(
DMP_SHT2_EWSW[25]), .Y(n700) );
AO22XLTS U1894 ( .A0(n1527), .A1(DMP_SFG[25]), .B0(n1525), .B1(
DMP_exp_NRM_EW[2]), .Y(n698) );
OAI2BB2XLTS U1895 ( .B0(n1474), .B1(n1683), .A0N(n1474), .A1N(
DMP_SHT1_EWSW[26]), .Y(n696) );
AO22XLTS U1896 ( .A0(n1490), .A1(DMP_SHT1_EWSW[26]), .B0(n1728), .B1(
DMP_SHT2_EWSW[26]), .Y(n695) );
AO22XLTS U1897 ( .A0(n1527), .A1(DMP_SFG[26]), .B0(n1525), .B1(
DMP_exp_NRM_EW[3]), .Y(n693) );
AO22XLTS U1898 ( .A0(n1478), .A1(n984), .B0(n969), .B1(DMP_SHT1_EWSW[27]),
.Y(n691) );
AO22XLTS U1899 ( .A0(n1490), .A1(DMP_SHT1_EWSW[27]), .B0(n1728), .B1(
DMP_SHT2_EWSW[27]), .Y(n690) );
AO22XLTS U1900 ( .A0(n1527), .A1(DMP_SFG[27]), .B0(n1525), .B1(
DMP_exp_NRM_EW[4]), .Y(n688) );
AO22XLTS U1901 ( .A0(n1486), .A1(DMP_EXP_EWSW[28]), .B0(n969), .B1(
DMP_SHT1_EWSW[28]), .Y(n686) );
AO22XLTS U1902 ( .A0(n1490), .A1(DMP_SHT1_EWSW[28]), .B0(n1728), .B1(
DMP_SHT2_EWSW[28]), .Y(n685) );
AO22XLTS U1903 ( .A0(n1527), .A1(DMP_SFG[28]), .B0(n1525), .B1(
DMP_exp_NRM_EW[5]), .Y(n683) );
AO22XLTS U1904 ( .A0(n1478), .A1(DMP_EXP_EWSW[29]), .B0(n1484), .B1(
DMP_SHT1_EWSW[29]), .Y(n681) );
AO22XLTS U1905 ( .A0(n1490), .A1(DMP_SHT1_EWSW[29]), .B0(n1728), .B1(
DMP_SHT2_EWSW[29]), .Y(n680) );
AO22XLTS U1906 ( .A0(n1600), .A1(DMP_SHT2_EWSW[29]), .B0(n1598), .B1(
DMP_SFG[29]), .Y(n679) );
AO22XLTS U1907 ( .A0(n1527), .A1(DMP_SFG[29]), .B0(n1525), .B1(
DMP_exp_NRM_EW[6]), .Y(n678) );
AO22XLTS U1908 ( .A0(n1489), .A1(DMP_EXP_EWSW[30]), .B0(n969), .B1(
DMP_SHT1_EWSW[30]), .Y(n676) );
AO22XLTS U1909 ( .A0(n1490), .A1(DMP_SHT1_EWSW[30]), .B0(n1728), .B1(
DMP_SHT2_EWSW[30]), .Y(n675) );
AO22XLTS U1910 ( .A0(n1475), .A1(DMP_SHT2_EWSW[30]), .B0(n1598), .B1(
DMP_SFG[30]), .Y(n674) );
AO22XLTS U1911 ( .A0(n1527), .A1(DMP_SFG[30]), .B0(n1525), .B1(
DMP_exp_NRM_EW[7]), .Y(n673) );
AO22XLTS U1912 ( .A0(n1477), .A1(DmP_EXP_EWSW[0]), .B0(n969), .B1(n983), .Y(
n670) );
AO22XLTS U1913 ( .A0(n1477), .A1(DmP_EXP_EWSW[1]), .B0(n1484), .B1(n982),
.Y(n668) );
AO22XLTS U1914 ( .A0(n1477), .A1(DmP_EXP_EWSW[8]), .B0(n969), .B1(n980), .Y(
n654) );
AO22XLTS U1915 ( .A0(n1486), .A1(DmP_EXP_EWSW[14]), .B0(n1484), .B1(
DmP_mant_SHT1_SW[14]), .Y(n642) );
AO22XLTS U1916 ( .A0(n1489), .A1(DmP_EXP_EWSW[15]), .B0(n969), .B1(
DmP_mant_SHT1_SW[15]), .Y(n640) );
OAI222X1TS U1917 ( .A0(n1481), .A1(n1682), .B0(n1631), .B1(
Shift_reg_FLAGS_7_6), .C0(n1479), .C1(n1480), .Y(n624) );
OAI222X1TS U1918 ( .A0(n1481), .A1(n1632), .B0(n1686), .B1(
Shift_reg_FLAGS_7_6), .C0(n1665), .C1(n1480), .Y(n623) );
OAI222X1TS U1919 ( .A0(n1481), .A1(n1633), .B0(n1681), .B1(
Shift_reg_FLAGS_7_6), .C0(n1689), .C1(n1480), .Y(n622) );
AO22XLTS U1920 ( .A0(n1478), .A1(ZERO_FLAG_EXP), .B0(n1484), .B1(
ZERO_FLAG_SHT1), .Y(n618) );
AO22XLTS U1921 ( .A0(n1490), .A1(ZERO_FLAG_SHT1), .B0(n1728), .B1(
ZERO_FLAG_SHT2), .Y(n617) );
AO22XLTS U1922 ( .A0(n1487), .A1(ZERO_FLAG_SHT2), .B0(n1601), .B1(
ZERO_FLAG_SFG), .Y(n616) );
AO22XLTS U1923 ( .A0(n1527), .A1(ZERO_FLAG_SFG), .B0(n1525), .B1(
ZERO_FLAG_NRM), .Y(n615) );
AO22XLTS U1924 ( .A0(Shift_reg_FLAGS_7[0]), .A1(ZERO_FLAG_SHT1SHT2), .B0(
n1005), .B1(zero_flag), .Y(n613) );
AO22XLTS U1925 ( .A0(Shift_reg_FLAGS_7_5), .A1(OP_FLAG_EXP), .B0(n968), .B1(
OP_FLAG_SHT1), .Y(n612) );
AO22XLTS U1926 ( .A0(n1490), .A1(OP_FLAG_SHT1), .B0(n1728), .B1(OP_FLAG_SHT2), .Y(n611) );
OAI2BB2XLTS U1927 ( .B0(n1487), .B1(n1538), .A0N(n1600), .A1N(OP_FLAG_SHT2),
.Y(n610) );
AO22XLTS U1928 ( .A0(n1486), .A1(SIGN_FLAG_EXP), .B0(n969), .B1(
SIGN_FLAG_SHT1), .Y(n609) );
AO22XLTS U1929 ( .A0(n1490), .A1(SIGN_FLAG_SHT1), .B0(n1728), .B1(
SIGN_FLAG_SHT2), .Y(n608) );
AO22XLTS U1930 ( .A0(n1611), .A1(SIGN_FLAG_SHT2), .B0(n1601), .B1(
SIGN_FLAG_SFG), .Y(n607) );
INVX4TS U1931 ( .A(n1726), .Y(n1558) );
AO22XLTS U1932 ( .A0(n1558), .A1(SIGN_FLAG_SFG), .B0(n1726), .B1(
SIGN_FLAG_NRM), .Y(n606) );
AOI2BB2X1TS U1933 ( .B0(n1539), .B1(DmP_mant_SFG_SWR[10]), .A0N(
DmP_mant_SFG_SWR[10]), .A1N(OP_FLAG_SFG), .Y(n1491) );
NOR2X1TS U1934 ( .A(n1491), .B(DMP_SFG[8]), .Y(n1510) );
NOR2X1TS U1935 ( .A(n1511), .B(n1510), .Y(n1532) );
XOR2X1TS U1936 ( .A(DMP_SFG[5]), .B(n973), .Y(n1567) );
AOI22X1TS U1937 ( .A0(n1539), .A1(DmP_mant_SFG_SWR[6]), .B0(n1538), .B1(
n1019), .Y(n1492) );
NOR2X1TS U1938 ( .A(DMP_SFG[4]), .B(n1492), .Y(n1564) );
NAND2X1TS U1939 ( .A(DMP_SFG[4]), .B(n1492), .Y(n1563) );
INVX2TS U1940 ( .A(n1563), .Y(n1494) );
NOR2X1TS U1941 ( .A(n1564), .B(n1494), .Y(n1561) );
NAND2X1TS U1942 ( .A(n1567), .B(n1561), .Y(n1505) );
OAI2BB1X1TS U1943 ( .A0N(DMP_SFG[7]), .A1N(n1528), .B0(n1497), .Y(n1498) );
OAI2BB1X1TS U1944 ( .A0N(n1504), .A1N(DMP_SFG[9]), .B0(n1499), .Y(n1500) );
OAI22X1TS U1945 ( .A0(n1500), .A1(n1511), .B0(n1504), .B1(DMP_SFG[9]), .Y(
intadd_44_B_0_) );
AOI22X1TS U1946 ( .A0(n1558), .A1(intadd_44_SUM_0_), .B0(n1638), .B1(n1568),
.Y(n603) );
AOI22X1TS U1947 ( .A0(n1558), .A1(intadd_44_SUM_2_), .B0(n1636), .B1(n1568),
.Y(n601) );
AOI22X1TS U1948 ( .A0(n1539), .A1(n1018), .B0(DmP_mant_SFG_SWR[16]), .B1(
n1538), .Y(intadd_44_B_4_) );
AOI22X1TS U1949 ( .A0(n1725), .A1(intadd_44_SUM_4_), .B0(n1679), .B1(n1568),
.Y(n599) );
AOI22X1TS U1950 ( .A0(n1539), .A1(n1016), .B0(DmP_mant_SFG_SWR[17]), .B1(
n1538), .Y(intadd_44_B_5_) );
AOI22X1TS U1951 ( .A0(n1725), .A1(intadd_44_SUM_5_), .B0(n1654), .B1(n1568),
.Y(n598) );
AOI22X1TS U1952 ( .A0(n1539), .A1(n1021), .B0(DmP_mant_SFG_SWR[18]), .B1(
n1538), .Y(intadd_44_B_6_) );
AOI22X1TS U1953 ( .A0(OP_FLAG_SFG), .A1(n1020), .B0(DmP_mant_SFG_SWR[19]),
.B1(n1538), .Y(intadd_44_B_7_) );
AOI22X1TS U1954 ( .A0(OP_FLAG_SFG), .A1(n1025), .B0(DmP_mant_SFG_SWR[20]),
.B1(n1538), .Y(intadd_44_B_8_) );
AOI22X1TS U1955 ( .A0(n1539), .A1(n1024), .B0(DmP_mant_SFG_SWR[21]), .B1(
n1538), .Y(intadd_44_B_9_) );
AOI22X1TS U1956 ( .A0(n1725), .A1(intadd_44_SUM_9_), .B0(n1648), .B1(n1568),
.Y(n594) );
AOI22X1TS U1957 ( .A0(n1539), .A1(n1011), .B0(DmP_mant_SFG_SWR[22]), .B1(
n1520), .Y(intadd_44_B_10_) );
AOI22X1TS U1958 ( .A0(n1725), .A1(intadd_44_SUM_10_), .B0(n1620), .B1(n1568),
.Y(n593) );
AOI22X1TS U1959 ( .A0(OP_FLAG_SFG), .A1(n1013), .B0(DmP_mant_SFG_SWR[23]),
.B1(n1520), .Y(intadd_44_B_11_) );
AOI22X1TS U1960 ( .A0(n1725), .A1(intadd_44_SUM_11_), .B0(n938), .B1(n1568),
.Y(n592) );
AOI22X1TS U1961 ( .A0(n1539), .A1(n1027), .B0(DmP_mant_SFG_SWR[24]), .B1(
n1520), .Y(intadd_44_B_12_) );
AOI22X1TS U1962 ( .A0(n1558), .A1(intadd_44_SUM_12_), .B0(n1618), .B1(n1568),
.Y(n591) );
AOI22X1TS U1963 ( .A0(OP_FLAG_SFG), .A1(DmP_mant_SFG_SWR[25]), .B0(n1520),
.B1(n1029), .Y(n1502) );
XNOR2X1TS U1964 ( .A(intadd_44_n1), .B(n1502), .Y(n1503) );
AOI22X1TS U1965 ( .A0(n1725), .A1(n1503), .B0(n1635), .B1(n1568), .Y(n590)
);
XOR2XLTS U1966 ( .A(DMP_SFG[9]), .B(n1504), .Y(n1513) );
INVX2TS U1967 ( .A(n1505), .Y(n1508) );
AOI2BB2X1TS U1968 ( .B0(n1560), .B1(DMP_SFG[3]), .A0N(DMP_SFG[3]), .A1N(
n1560), .Y(n1552) );
INVX2TS U1969 ( .A(n1509), .Y(n1524) );
XNOR2X1TS U1970 ( .A(n1513), .B(n1512), .Y(n1514) );
AOI22X1TS U1971 ( .A0(n1725), .A1(n1514), .B0(n1637), .B1(n1726), .Y(n588)
);
AOI22X1TS U1972 ( .A0(Data_array_SWR[13]), .A1(n1582), .B0(Data_array_SWR[9]), .B1(n997), .Y(n1517) );
INVX2TS U1973 ( .A(n1515), .Y(n1548) );
AOI22X1TS U1974 ( .A0(Data_array_SWR[5]), .A1(n995), .B0(Data_array_SWR[1]),
.B1(n1548), .Y(n1516) );
OAI211X1TS U1975 ( .A0(n1518), .A1(n1655), .B0(n1517), .C0(n1516), .Y(n1594)
);
AOI22X1TS U1976 ( .A0(Data_array_SWR[24]), .A1(n994), .B0(n966), .B1(n1594),
.Y(n1519) );
AOI22X1TS U1977 ( .A0(n1611), .A1(n1519), .B0(n1028), .B1(n1601), .Y(n586)
);
AOI22X1TS U1978 ( .A0(n1539), .A1(n1028), .B0(DmP_mant_SFG_SWR[1]), .B1(
n1520), .Y(n1521) );
AOI2BB2XLTS U1979 ( .B0(n1558), .B1(n1521), .A0N(Raw_mant_NRM_SWR[1]), .A1N(
n1558), .Y(n585) );
AOI22X1TS U1980 ( .A0(n1616), .A1(n1522), .B0(n1015), .B1(n1601), .Y(n583)
);
OAI2BB2XLTS U1981 ( .B0(n1558), .B1(n1653), .A0N(n1725), .A1N(n1530), .Y(
n581) );
XNOR2X1TS U1982 ( .A(n1532), .B(n1531), .Y(n1533) );
AOI22X1TS U1983 ( .A0(n1725), .A1(n1533), .B0(n1640), .B1(n1726), .Y(n580)
);
AOI22X1TS U1984 ( .A0(Data_array_SWR[12]), .A1(n1582), .B0(Data_array_SWR[8]), .B1(n998), .Y(n1535) );
AOI22X1TS U1985 ( .A0(Data_array_SWR[4]), .A1(n1078), .B0(Data_array_SWR[0]),
.B1(n1548), .Y(n1534) );
OAI211X1TS U1986 ( .A0(n1536), .A1(n1655), .B0(n1535), .C0(n1534), .Y(n1612)
);
AOI22X1TS U1987 ( .A0(Data_array_SWR[25]), .A1(n994), .B0(n964), .B1(n1612),
.Y(n1537) );
AOI22X1TS U1988 ( .A0(n1611), .A1(n1537), .B0(n1030), .B1(n1601), .Y(n578)
);
AOI22X1TS U1989 ( .A0(n1539), .A1(n1030), .B0(DmP_mant_SFG_SWR[0]), .B1(
n1538), .Y(n1540) );
AOI2BB2XLTS U1990 ( .B0(n1558), .B1(n1540), .A0N(Raw_mant_NRM_SWR[0]), .A1N(
n1558), .Y(n577) );
AOI22X1TS U1991 ( .A0(Data_array_SWR[14]), .A1(n1582), .B0(
Data_array_SWR[10]), .B1(n997), .Y(n1542) );
AOI22X1TS U1992 ( .A0(Data_array_SWR[6]), .A1(n995), .B0(Data_array_SWR[2]),
.B1(n1548), .Y(n1541) );
OAI211X1TS U1993 ( .A0(n1543), .A1(n1655), .B0(n1542), .C0(n1541), .Y(n1593)
);
AOI22X1TS U1994 ( .A0(Data_array_SWR[23]), .A1(n993), .B0(n934), .B1(n1593),
.Y(n1591) );
AOI22X1TS U1995 ( .A0(n1616), .A1(n1591), .B0(n1601), .B1(n1014), .Y(n576)
);
XNOR2X1TS U1996 ( .A(n1546), .B(n1545), .Y(n1547) );
AOI22X1TS U1997 ( .A0(n1725), .A1(n1547), .B0(n1677), .B1(n1726), .Y(n574)
);
AOI22X1TS U1998 ( .A0(Data_array_SWR[15]), .A1(n1582), .B0(
Data_array_SWR[11]), .B1(n997), .Y(n1550) );
AOI22X1TS U1999 ( .A0(Data_array_SWR[7]), .A1(n995), .B0(Data_array_SWR[3]),
.B1(n1548), .Y(n1549) );
OAI211X1TS U2000 ( .A0(n1551), .A1(n1655), .B0(n1550), .C0(n1549), .Y(n1592)
);
AOI22X1TS U2001 ( .A0(Data_array_SWR[22]), .A1(n994), .B0(n966), .B1(n1592),
.Y(n1590) );
AOI22X1TS U2002 ( .A0(n1611), .A1(n1590), .B0(n1012), .B1(n1601), .Y(n571)
);
INVX2TS U2003 ( .A(n1552), .Y(n1556) );
XOR2X1TS U2004 ( .A(n1565), .B(n1561), .Y(n1562) );
AOI22X1TS U2005 ( .A0(n1725), .A1(n1562), .B0(n1643), .B1(n1726), .Y(n568)
);
XNOR2X1TS U2006 ( .A(n1567), .B(n1566), .Y(n1569) );
AOI22X1TS U2007 ( .A0(n1725), .A1(n1569), .B0(n1639), .B1(n1568), .Y(n567)
);
AOI22X1TS U2008 ( .A0(n1616), .A1(n1570), .B0(n1601), .B1(n1019), .Y(n566)
);
AOI22X1TS U2009 ( .A0(n1611), .A1(n1571), .B0(n1601), .B1(n1023), .Y(n563)
);
AOI22X1TS U2010 ( .A0(Data_array_SWR[12]), .A1(n956), .B0(Data_array_SWR[13]), .B1(n993), .Y(n1572) );
OAI221X1TS U2011 ( .A0(n965), .A1(n1574), .B0(n964), .B1(n1575), .C0(n1572),
.Y(n1595) );
AOI22X1TS U2012 ( .A0(Data_array_SWR[12]), .A1(n993), .B0(Data_array_SWR[13]), .B1(n956), .Y(n1573) );
OAI221X1TS U2013 ( .A0(left_right_SHT2), .A1(n1575), .B0(n964), .B1(n1574),
.C0(n1573), .Y(n1596) );
AOI22X1TS U2014 ( .A0(n1616), .A1(n1576), .B0(n1017), .B1(n1601), .Y(n558)
);
AOI22X1TS U2015 ( .A0(n1611), .A1(n1577), .B0(n974), .B1(n1601), .Y(n555) );
AOI22X1TS U2016 ( .A0(Data_array_SWR[14]), .A1(n956), .B0(Data_array_SWR[11]), .B1(n993), .Y(n1579) );
OAI221X1TS U2017 ( .A0(n965), .A1(n1581), .B0(n964), .B1(n1580), .C0(n1579),
.Y(n1597) );
AOI22X1TS U2018 ( .A0(Data_array_SWR[23]), .A1(n997), .B0(Data_array_SWR[19]), .B1(n1078), .Y(n1587) );
AOI22X1TS U2019 ( .A0(Data_array_SWR[10]), .A1(n956), .B0(Data_array_SWR[15]), .B1(n993), .Y(n1583) );
OAI221X1TS U2020 ( .A0(left_right_SHT2), .A1(n1586), .B0(n966), .B1(n1587),
.C0(n1583), .Y(n1584) );
AOI22X1TS U2021 ( .A0(Data_array_SWR[10]), .A1(n993), .B0(Data_array_SWR[15]), .B1(n956), .Y(n1585) );
OAI221X1TS U2022 ( .A0(left_right_SHT2), .A1(n1587), .B0(n964), .B1(n1586),
.C0(n1585), .Y(n1599) );
AOI22X1TS U2023 ( .A0(n1616), .A1(n1589), .B0(n1022), .B1(n1601), .Y(n547)
);
OAI2BB2XLTS U2024 ( .B0(n1590), .B1(n962), .A0N(final_result_ieee[1]), .A1N(
n1005), .Y(n544) );
OAI2BB2XLTS U2025 ( .B0(n1591), .B1(n962), .A0N(final_result_ieee[0]), .A1N(
n1005), .Y(n543) );
AOI22X1TS U2026 ( .A0(Data_array_SWR[22]), .A1(n956), .B0(left_right_SHT2),
.B1(n1592), .Y(n1608) );
OAI2BB2XLTS U2027 ( .B0(n1608), .B1(n962), .A0N(final_result_ieee[20]),
.A1N(n1005), .Y(n540) );
AOI22X1TS U2028 ( .A0(Data_array_SWR[23]), .A1(n957), .B0(left_right_SHT2),
.B1(n1593), .Y(n1609) );
OAI2BB2XLTS U2029 ( .B0(n1609), .B1(n962), .A0N(final_result_ieee[21]),
.A1N(n1005), .Y(n539) );
AOI22X1TS U2030 ( .A0(Data_array_SWR[24]), .A1(n957), .B0(left_right_SHT2),
.B1(n1594), .Y(n1610) );
OAI2BB2XLTS U2031 ( .B0(n1610), .B1(n962), .A0N(final_result_ieee[22]),
.A1N(n1005), .Y(n538) );
AOI22X1TS U2032 ( .A0(n1611), .A1(n1602), .B0(n1018), .B1(n1485), .Y(n533)
);
AOI22X1TS U2033 ( .A0(n1616), .A1(n1603), .B0(n1016), .B1(n1485), .Y(n532)
);
AOI22X1TS U2034 ( .A0(n1611), .A1(n1604), .B0(n1021), .B1(n1485), .Y(n531)
);
AOI22X1TS U2035 ( .A0(n1616), .A1(n1605), .B0(n1020), .B1(n1485), .Y(n530)
);
AOI22X1TS U2036 ( .A0(n1611), .A1(n1606), .B0(n1025), .B1(n1485), .Y(n529)
);
AOI22X1TS U2037 ( .A0(n1616), .A1(n1607), .B0(n1024), .B1(n1485), .Y(n528)
);
AOI22X1TS U2038 ( .A0(n1611), .A1(n1608), .B0(n1011), .B1(n1485), .Y(n527)
);
AOI22X1TS U2039 ( .A0(n1616), .A1(n1609), .B0(n1013), .B1(n1485), .Y(n526)
);
AOI22X1TS U2040 ( .A0(n1611), .A1(n1610), .B0(n1027), .B1(n1614), .Y(n525)
);
AOI22X1TS U2041 ( .A0(Data_array_SWR[25]), .A1(n957), .B0(left_right_SHT2),
.B1(n1612), .Y(n1615) );
AOI22X1TS U2042 ( .A0(n1616), .A1(n1615), .B0(n1614), .B1(n1029), .Y(n524)
);
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk20.tcl_GDAN16M4P8_syn.sdf");
endmodule
|
//--------------------------------------------------------------------------------
// Logic_Sniffer.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Logic Analyzer top level module. It connects the core with the hardware
// dependend IO modules and defines all inputs and outputs that represent
// phyisical pins of the fpga.
//
// It defines two constants FREQ and RATE. The first is the clock frequency
// used for receiver and transmitter for generating the proper baud rate.
// The second defines the speed at which to operate the serial port.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis (IED) - mygizmos.org
//
`timescale 1ns/100ps
`define COMM_TYPE_SPI 1 // comment out for UART mode
module Logic_Sniffer #(
`ifdef COMM_TYPE_SPI
parameter [31:0] MEMORY_DEPTH=6,
parameter [31:0] CLOCK_SPEED=50,
parameter [1:0] SPEED=2'b00
`else
// Sets the speed for UART communications
// SYSTEM_JITTER = "1000 ps"
parameter FREQ = 100000000, // limited to 100M by onboard SRAM
parameter TRXSCALE = 28, // 100M / 28 / 115200 = 31 (5bit) --If serial communications are not working then try adjusting this number.
parameter RATE = 115200 // maximum & base rate
`endif
)(
// system signals
input wire bf_clock,
// logic analyzer signals
input wire extClockIn,
output wire extClockOut,
input wire extTriggerIn,
output wire extTriggerOut,
//
inout wire [31:0] extData,
//
output wire dataReady,
output wire armLEDnn,
output wire triggerLEDnn,
// host interface
`ifdef COMM_TYPE_SPI
input wire spi_sclk,
input wire spi_cs_n,
input wire spi_mosi,
output wire spi_miso
`else
input wire rx,
output wire tx
`endif
);
// system signals
wire sys_clk;
wire sys_clk_p;
wire sys_clk_n;
wire sys_rst = 1'b0;
// external signals
wire ext_clk_p;
wire ext_clk_n;
// data path signals
wire sti_clk_p;
wire sti_clk_n;
wire [31:0] sti_data;
wire [31:0] sti_data_p;
wire [31:0] sti_data_n;
wire extClock_mode;
wire extTestMode;
wire [39:0] cmd;
wire [31:0] sram_wrdata;
wire [31:0] sram_rddata;
wire [3:0] sram_rdvalid;
wire [31:0] stableInput;
wire [7:0] opcode;
wire [31:0] config_data;
assign {config_data,opcode} = cmd;
//--------------------------------------------------------------------------------
// clocking
//--------------------------------------------------------------------------------
wire sys_clk_ref;
wire sys_clk_buf;
wire ext_clk_ref;
wire ext_clk_buf;
// DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
// Xilinx HDL Language Template version 8.1i
DCM #(
.CLK_FEEDBACK("1X")
) dcm_sys_clk (
.CLKIN (bf_clock), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK (1'b 0), // Dynamic phase adjust clock input
.PSEN (1'b 0), // Dynamic phase adjust enable input
.PSINCDEC (1'b 0), // Dynamic phase adjust increment/decrement
.RST (1'b 0), // DCM asynchronous reset input
// clock outputs
.CLK2X (sys_clk),
.CLKFX (sys_clk_p),
.CLKFX180 (sys_clk_n),
// feedback
.CLK0 (sys_clk_ref),
.CLKFB (sys_clk_buf)
);
BUFG BUFG_sys_clk_fb (
.I (sys_clk_ref),
.O (sys_clk_buf)
);
DCM #(
.CLK_FEEDBACK("2X")
) dcm_ext_clk (
.CLKIN (extClockIn), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK (1'b 0), // Dynamic phase adjust clock input
.PSEN (1'b 0), // Dynamic phase adjust enable input
.PSINCDEC (1'b 0), // Dynamic phase adjust increment/decrement
.RST (1'b 0), // DCM asynchronous reset input
.CLK0 (ext_clk_p),
.CLK180 (ext_clk_n),
// feedback
.CLK2X (ext_clk_ref),
.CLKFB (ext_clk_buf)
);
BUFG BUFG_ext_clk_fb (
.I (ext_clk_ref),
.O (ext_clk_buf)
);
//
// Select between internal and external sampling clock...
//
//BUFGMUX bufmux_sti_clk [1:0] (
// .O ({sti_clk_p, sti_clk_n}), // Clock MUX output
// .I0 ({sys_clk_p, sys_clk_n}), // Clock0 input
// .I1 ({ext_clk_p, ext_clk_n}), // Clock1 input
// .S (extClock_mode) // Clock select
//);
assign sti_clk_p = sys_clk_p;
assign sti_clk_n = sys_clk_n;
//--------------------------------------------------------------------------------
// IO
//--------------------------------------------------------------------------------
// Use DDR output buffer to isolate clock & avoid skew penalty...
ODDR2 ODDR2 (
.Q (extClockOut),
.D0 (1'b0),
.D1 (1'b1),
.C0 (sti_clk_n),
.C1 (sti_clk_p),
.S (1'b0),
.R (1'b0)
);
//
// Configure the probe pins...
//
reg [10:0] test_counter;
always @ (posedge sys_clk, posedge sys_rst)
if (sys_rst) test_counter <= 'b0;
else test_counter <= test_counter + 'b1;
wire [15:0] test_pattern = {8{test_counter[10], test_counter[4]}};
IOBUF #(
.DRIVE (12), // Specify the output drive strength
.IBUF_DELAY_VALUE ("0"), // Specify the amount of added input delay for the buffer,
// "0"-"12" (Spartan-3E only)
.IFD_DELAY_VALUE ("AUTO"), // Specify the amount of added delay for input register,
// "AUTO", "0"-"6" (Spartan-3E only)
.IOSTANDARD ("DEFAULT"), // Specify the I/O standard
.SLEW ("SLOW") // Specify the output slew rate
) IOBUF [31:16] (
.O (sti_data[31:16]), // Buffer output
.IO (extData [31:16]), // Buffer inout port (connect directly to top-level port)
.I (test_pattern), // Buffer input
.T ({16{~extTestMode}}) // 3-state enable input, high=input, low=output
);
IBUF #(
.CAPACITANCE ("DONT_CARE"),
.IBUF_DELAY_VALUE ("0"),
.IBUF_LOW_PWR ("TRUE"),
.IFD_DELAY_VALUE ("AUTO"),
.IOSTANDARD ("DEFAULT")
) IBUF [15:0] (
.O (sti_data[15:0]), // Buffer output
.I (extData [15:0]) // Buffer input port (connect directly to top-level port)
);
IDDR2 #(
.DDR_ALIGNMENT ("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT_Q0 (1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
.INIT_Q1 (1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
.SRTYPE ("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) IDDR2 [31:0] (
.Q0 (sti_data_p), // 1-bit output captured with C0 clock
.Q1 (sti_data_n), // 1-bit output captured with C1 clock
.C0 (sti_clk_p), // 1-bit clock input
.C1 (sti_clk_n), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable input
.D (sti_data), // 1-bit DDR data input
.R (1'b0), // 1-bit reset input
.S (1'b0) // 1-bit set input
);
//--------------------------------------------------------------------------------
// rtl instances
//--------------------------------------------------------------------------------
// Output dataReady to PIC (so it'll enable our SPI CS#)...
dly_signal dataReady_reg (sys_clk, busy, dataReady);
//
// Instantiate serial interface....
//
`ifdef COMM_TYPE_SPI
spi_slave spi_slave (
// system signals
.clk (sys_clk),
.rst (sys_rst),
// input stream
.dataIn (stableInput),
.send (send),
.send_data (sram_rddata),
.send_valid (sram_rdvalid),
// output configuration
.cmd (cmd),
.execute (execute),
.busy (busy),
// SPI signals
.spi_sclk (spi_sclk),
.spi_cs_n (spi_cs_n),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso)
);
`else
eia232 #(
.FREQ (FREQ),
.SCALE (TRXSCALE),
.RATE (RATE)
) eia232 (
.clock (sys_clk),
.reset (sys_rst),
.speed (SPEED),
.rx (rx),
.tx (tx),
.cmd (cmd),
.execute (execute),
.data (output),
.send (send),
.busy (busy)
);
`endif
//
// Instantiate core...
//
core #(
.SDW (32),
.MDW (32)
) core (
// system signsls
.sys_clk (sys_clk),
.sys_rst (sys_rst),
// input stream
.sti_clk (sti_clk_p),
.sti_data_p (sti_data_p),
.sti_data_n (sti_data_n),
//
.extTriggerIn (extTriggerIn),
.opcode (opcode),
.config_data (config_data),
.execute (execute),
.outputBusy (busy),
// outputs...
.sampleReady50 (),
.stableInput (stableInput),
.outputSend (send),
.extTriggerOut (extTriggerOut),
.armLEDnn (armLEDnn),
.triggerLEDnn (triggerLEDnn),
.wrFlags (wrFlags),
.extClock_mode (extClock_mode),
.extTestMode (extTestMode),
// memory interface
.memoryWrData (sram_wrdata),
.memoryRead (read),
.memoryWrite (write),
.memoryLastWrite (lastwrite)
);
//
// Instantiate the memory interface...
//
sram_interface sram_interface (
// system signals
.clk (sys_clk),
.rst (sys_rst),
// configuration/control signals
.wrFlags (wrFlags),
.config_data (config_data[5:2]),
// write interface
.write (write),
.lastwrite (lastwrite),
.wrdata (sram_wrdata),
// read interface
.rd_ready (read),
.rd_valid (),
.rd_keep (sram_rdvalid),
.rd_data (sram_rddata)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module hls_saturation_enhance_AXILiteS_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
// axi4 lite slave signals
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
// user signals
output wire [15:0] height,
output wire [15:0] width,
output wire [7:0] sat
);
//------------------------Address Info-------------------
// 0x00 : reserved
// 0x04 : reserved
// 0x08 : reserved
// 0x0c : reserved
// 0x10 : Data signal of height
// bit 15~0 - height[15:0] (Read/Write)
// others - reserved
// 0x14 : reserved
// 0x18 : Data signal of width
// bit 15~0 - width[15:0] (Read/Write)
// others - reserved
// 0x1c : reserved
// 0x20 : Data signal of sat
// bit 7~0 - sat[7:0] (Read/Write)
// others - reserved
// 0x24 : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_HEIGHT_DATA_0 = 6'h10,
ADDR_HEIGHT_CTRL = 6'h14,
ADDR_WIDTH_DATA_0 = 6'h18,
ADDR_WIDTH_CTRL = 6'h1c,
ADDR_SAT_DATA_0 = 6'h20,
ADDR_SAT_CTRL = 6'h24,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [31:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [31:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg [15:0] int_height = 'b0;
reg [15:0] int_width = 'b0;
reg [7:0] int_sat = 'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 1'b0;
case (raddr)
ADDR_HEIGHT_DATA_0: begin
rdata <= int_height[15:0];
end
ADDR_WIDTH_DATA_0: begin
rdata <= int_width[15:0];
end
ADDR_SAT_DATA_0: begin
rdata <= int_sat[7:0];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign height = int_height;
assign width = int_width;
assign sat = int_sat;
// int_height[15:0]
always @(posedge ACLK) begin
if (ARESET)
int_height[15:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_HEIGHT_DATA_0)
int_height[15:0] <= (WDATA[31:0] & wmask) | (int_height[15:0] & ~wmask);
end
end
// int_width[15:0]
always @(posedge ACLK) begin
if (ARESET)
int_width[15:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_WIDTH_DATA_0)
int_width[15:0] <= (WDATA[31:0] & wmask) | (int_width[15:0] & ~wmask);
end
end
// int_sat[7:0]
always @(posedge ACLK) begin
if (ARESET)
int_sat[7:0] <= 0;
else if (ACLK_EN) begin
if (w_hs && waddr == ADDR_SAT_DATA_0)
int_sat[7:0] <= (WDATA[31:0] & wmask) | (int_sat[7:0] & ~wmask);
end
end
//------------------------Memory logic-------------------
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_PP_SYMBOL_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_PP_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvpwrvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NOR2_PP_SYMBOL_V
/**
* nor2: 2-input NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVER_BLACKBOX_V
/**
* busdriver: Bus driver (pmoshvt devices).
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdriver (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER_BLACKBOX_V
|
module FORWARDINGTEST;
reg [15:0] one, two;
reg one_A, one_B, two_A, two_B;
wire [15:0] outA, outB;
wire forwarda, forwardb;
Forwarding fw (one, two, one_A, one_B, two_A, two_B, forwarda, forwardb, outA, outB);
initial begin
$dumpfile("ForwadingTest.vcd");
$dumpvars(0, FORWARDINGTEST);
$monitor ("%t: one = %b, two = %b, one_A = %b, one_B = %b, two_A = %b, two_B = %b, outA = %b, outB = %b", $time, one, two, one_A, one_B, two_A, two_B, outA, outB);
one = 16'b0000_0000_1111_0000; two = 16'b0000_0000_0000_1111;
one_A = 1'b0; one_B = 1'b0; two_A = 1'b0; two_B = 1'b0;
#10
one_A = 1'b0; one_B = 1'b0; two_A = 1'b0; two_B = 1'b1;
#10
one_A = 1'b0; one_B = 1'b0; two_A = 1'b1; two_B = 1'b0;
#10
one_A = 1'b0; one_B = 1'b0; two_A = 1'b1; two_B = 1'b1;
#10
one_A = 1'b0; one_B = 1'b1; two_A = 1'b0; two_B = 1'b0;
#10
one_A = 1'b0; one_B = 1'b1; two_A = 1'b0; two_B = 1'b1;
#10
one_A = 1'b0; one_B = 1'b1; two_A = 1'b1; two_B = 1'b0;
#10
one_A = 1'b0; one_B = 1'b1; two_A = 1'b1; two_B = 1'b1;
#10
one_A = 1'b1; one_B = 1'b0; two_A = 1'b0; two_B = 1'b0;
#10
one_A = 1'b1; one_B = 1'b0; two_A = 1'b0; two_B = 1'b1;
#10
one_A = 1'b1; one_B = 1'b0; two_A = 1'b1; two_B = 1'b0;
#10
one_A = 1'b1; one_B = 1'b0; two_A = 1'b1; two_B = 1'b1;
#10
one_A = 1'b1; one_B = 1'b1; two_A = 1'b0; two_B = 1'b0;
#10
one_A = 1'b1; one_B = 1'b1; two_A = 1'b0; two_B = 1'b1;
#10
one_A = 1'b1; one_B = 1'b1; two_A = 1'b1; two_B = 1'b0;
#10
one_A = 1'b1; one_B = 1'b1; two_A = 1'b1; two_B = 1'b1;
#10
one_A = 1'b0; one_B = 1'b0; two_A = 1'b0; two_B = 1'b0;
#10 $finish;
end
endmodule // MUXTEST
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: pipefetch.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: Keeping our CPU fed with instructions, at one per clock and
// with no stalls, can be quite a chore. Worse, the Wishbone
// takes a couple of cycles just to read one instruction from
// the bus. However, if we use pipeline accesses to the Wishbone
// bus, then we can read more and faster. Further, if we cache
// these results so that we have them before we need them, then
// we have a chance of keeping our CPU from stalling. Those are
// the purposes of this instruction fetch module: 1) Pipeline
// wishbone accesses, and 2) an instruction cache.
//
// 20150919 -- Fixed a nasty race condition whereby the pipefetch routine
// would produce either the same instruction twice, or skip
// an instruction. This condition was dependent on the CPU stall
// condition, and would only take place if the pipeline wasn't
// completely full throughout the stall.
//
// Interface support was also added for trapping on illegal
// instructions (i.e., instruction fetches that cause bus errors),
// however the internal interface has not caught up to supporting
// these exceptions yet.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
o_i, o_pc, o_v,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
o_illegal);
parameter RESET_ADDRESS=32'h0010_0000,
LGCACHELEN = 6, ADDRESS_WIDTH=24,
CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
input wire i_clk, i_rst, i_new_pc,
i_clear_cache, i_stall_n;
input wire [(AW-1):0] i_pc;
output reg [(BUSW-1):0] o_i;
output reg [(AW-1):0] o_pc;
output wire o_v;
//
output reg o_wb_cyc, o_wb_stb;
output wire o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output wire [(BUSW-1):0] o_wb_data;
//
input wire i_wb_ack, i_wb_stall, i_wb_err;
input wire [(BUSW-1):0] i_wb_data;
//
// Is the (data) memory unit also requesting access to the bus?
input wire i_wb_request;
output wire o_illegal;
// Fixed bus outputs: we read from the bus only, never write.
// Thus the output data is ... irrelevant and don't care. We set it
// to zero just to set it to something.
assign o_wb_we = 1'b0;
assign o_wb_data = 0;
reg [(AW-1):0] r_cache_base;
reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
reg [(BUSW-1):0] cache[0:(CACHELEN-1)];
wire [(LGCACHELEN-1):0] w_cache_offset;
reg [1:0] r_cache_offset;
reg r_addr_set;
reg [(AW-1):0] r_addr;
wire [(AW-1):0] bus_nvalid;
assign bus_nvalid = { {(AW-LGCACHELEN-1){1'b0}}, r_nvalid };
// What are some of the conditions for which we need to restart the
// cache?
wire w_pc_out_of_bounds;
assign w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
||(i_pc < r_cache_base)
||(i_pc >= r_cache_base + CACHELEN)
||(i_pc >= r_cache_base + bus_nvalid+5)));
wire w_ran_off_end_of_cache;
assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
||(r_addr >= r_cache_base + CACHELEN)
||(r_addr >= r_cache_base + bus_nvalid+5)));
wire w_running_out_of_cache;
assign w_running_out_of_cache = (r_addr_set)
&&(r_addr >= r_cache_base +
// {{(AW-LGCACHELEN-1),{1'b0}},2'b11,
// {(LGCACHELEN-1){1'b0}}})
// (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))
+(3<<(LGCACHELEN-2)))
&&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
initial r_cache_base = RESET_ADDRESS[(AW+1):2];
always @(posedge i_clk)
begin
if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
begin
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
// r_cache_base <= RESET_ADDRESS;
// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
// &&(i_pc >= r_cache_base)
// &&(i_pc < r_cache_base + bus_nvalid))
// begin
// The new instruction is in our cache, do nothing
// with the bus here.
end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
begin
// We need to abandon our bus action to start over in
// a new region, setting up a new cache. This may
// happen mid cycle while waiting for a result. By
// dropping o_wb_cyc, we state that we are no longer
// interested in that result--whatever it might be.
o_wb_cyc <= 1'b0;
o_wb_stb <= 1'b0;
end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))
begin
// Restart a bus cycle that was interrupted when the
// data section wanted access to our bus.
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
// o_wb_addr <= r_cache_base + bus_nvalid;
end else if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
begin
// Start a bus transaction
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
// o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
// r_nvalid <= 0;
// r_cache_base <= (i_new_pc) ? i_pc : r_addr;
// w_cache_offset <= 0;
end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
begin
// If we're using the last quarter of the cache, then
// let's start a bus transaction to extend the cache.
o_wb_cyc <= 1'b1;
o_wb_stb <= 1'b1;
// o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
// r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
// r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
// w_cache_offset <= w_cache_offset + (1<<(LGCACHELEN-2));
end else if (o_wb_cyc)
begin
// This handles everything ... but the case where
// while reading we need to extend our cache.
if ((o_wb_stb)&&(~i_wb_stall))
begin
// o_wb_addr <= o_wb_addr + 1;
if ((o_wb_addr - r_cache_base >= CACHELEN-1)
||(i_wb_request))
o_wb_stb <= 1'b0;
end
if (i_wb_ack)
begin
// r_nvalid <= r_nvalid + 1;
if ((r_acks_waiting == 1)&&(~o_wb_stb))
o_wb_cyc <= 1'b0;
end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
o_wb_cyc <= 1'b0;
end
end
initial r_nvalid = 0;
always @(posedge i_clk)
if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
r_nvalid <= 0;
else if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
r_nvalid <= 0;
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
r_nvalid[LGCACHELEN:(LGCACHELEN-2)]
<= r_nvalid[LGCACHELEN:(LGCACHELEN-2)] +3'b111;
// i.e. - (1<<(LGCACHELEN-2));
else if ((o_wb_cyc)&&(i_wb_ack))
r_nvalid <= r_nvalid + {{(LGCACHELEN){1'b0}},1'b1}; // +1;
always @(posedge i_clk)
if (i_clear_cache)
r_cache_base <= i_pc;
else if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)
||(w_ran_off_end_of_cache)))
r_cache_base <= (i_new_pc) ? i_pc : r_addr;
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
r_cache_base[(AW-1):(LGCACHELEN-2)]
<= r_cache_base[(AW-1):(LGCACHELEN-2)]
+ {{(AW-LGCACHELEN+1){1'b0}},1'b1};
// i.e. + (1<<(LGCACHELEN-2));
always @(posedge i_clk)
if (i_clear_cache)
r_cache_offset <= 0;
else if ((~o_wb_cyc)&&(
(w_pc_out_of_bounds)
||(w_ran_off_end_of_cache)))
r_cache_offset <= 0;
else if ((~o_wb_cyc)&&(w_running_out_of_cache))
r_cache_offset[1:0] <= r_cache_offset[1:0] + 2'b01;
assign w_cache_offset = { r_cache_offset, {(LGCACHELEN-2){1'b0}} };
always @(posedge i_clk)
if (i_clear_cache)
o_wb_addr <= i_pc;
else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
begin
if (i_wb_ack)
o_wb_addr <= r_cache_base + bus_nvalid+1;
else
o_wb_addr <= r_cache_base + bus_nvalid;
end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
||(w_ran_off_end_of_cache)))
o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
else if ((o_wb_stb)&&(~i_wb_stall)) // && o_wb_cyc
o_wb_addr <= o_wb_addr + 1;
initial r_acks_waiting = 0;
always @(posedge i_clk)
if (~o_wb_cyc)
r_acks_waiting <= 0;
// o_wb_cyc *must* be true for all following
else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) //&&(o_wb_cyc)
r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall))) //&&(o_wb_cyc)
r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_ack))
cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
<= i_wb_data;
initial r_addr_set = 1'b0;
always @(posedge i_clk)
if ((i_rst)||(i_new_pc))
r_addr_set <= 1'b1;
else if (i_clear_cache)
r_addr_set <= 1'b0;
// Now, read from the cache
wire w_cv; // Cache valid, address is in the cache
reg r_cv;
assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
&&(r_addr-r_cache_base < bus_nvalid));
always @(posedge i_clk)
r_cv <= (~i_new_pc)&&((w_cv)||((~i_stall_n)&&(r_cv)));
assign o_v = (r_cv)&&(~i_new_pc);
always @(posedge i_clk)
if (i_new_pc)
r_addr <= i_pc;
else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
r_addr <= r_addr + {{(AW-1){1'b0}},1'b1};
wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;
assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];
assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+w_cache_offset;
always @(posedge i_clk)
if ((~o_v)||((i_stall_n)&&(o_v)))
o_i <= cache[c_rdaddr];
always @(posedge i_clk)
if ((~o_v)||((i_stall_n)&&(o_v)))
o_pc <= r_addr;
reg [(AW-1):0] ill_address;
initial ill_address = 0;
always @(posedge i_clk)
if ((o_wb_cyc)&&(i_wb_err))
ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
assign o_illegal = (o_pc == ill_address)&&(~i_rst)&&(~i_new_pc)&&(~i_clear_cache);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_SYMBOL_V
`define SKY130_FD_SC_LP__A2BB2O_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFBBN_BEHAVIORAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_BEHAVIORAL_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 8
(* X_CORE_INFO = "axi_crossbar_v2_1_8_axi_crossbar,Vivado 2015.4.2" *)
(* CHECK_LICENSE_TYPE = "design_SWandHW_standalone_xbar_0,axi_crossbar_v2_1_8_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "design_SWandHW_standalone_xbar_0,axi_crossbar_v2_1_8_axi_crossbar,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=7,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x000000004044000000000000404300000000000040420000000000004041000000000000404000000000000043c000000000000041200000,C_M_AXI_ADDR_WIDTH=0x00000010000000100000001000000010000000100000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x00000001000000010000000100000001000000010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000000000000000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_SWandHW_standalone_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192]" *)
output wire [223 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24]" *)
output wire [27 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192]" *)
input wire [223 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_rready;
axi_crossbar_v2_1_8_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(7),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(448'H000000004044000000000000404300000000000040420000000000004041000000000000404000000000000043c000000000000041200000),
.C_M_AXI_ADDR_WIDTH(224'H00000010000000100000001000000010000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(224'H00000001000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(224'H00000001000000010000000100000001000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(224'H00000000000000000000000000000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(7'H00),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(7'H00),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(7'H00),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(7'H7F),
.m_axi_ruser(7'H00),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_TB_V
/**
* udp_dff$P_pp$PKG$sN: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_p_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg NOTIFIER;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 NOTIFIER = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 NOTIFIER = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 NOTIFIER = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 NOTIFIER = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$P_pp$PKG$sN dut (.D(D), .SLEEP_B(SLEEP_B), .NOTIFIER(NOTIFIER), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_P_PP_PKG_SN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_4_V
`define SKY130_FD_SC_HD__NOR4_4_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4_4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4_4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_4_V
|
//library ieee;
//use ieee.std_logic_1164.all;
//use ieee.std_logic_unsigned.all;
//-----------------------------------------------------
// Design Name : ram_dp_sr_sw
// File Name : ram_dp_sr_sw.v
// Function : Synchronous read write RAM
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
`timescale 1ns/1ps
module blk_mem #(
parameter DATA_WIDTH = 8,
parameter ADDRESS_WIDTH = 4,
parameter INC_NUM_PATTERN = 0
)(
input clka,
input wea,
input [ADDRESS_WIDTH - 1 :0] addra,
input [DATA_WIDTH - 1:0] dina,
input clkb,
input [ADDRESS_WIDTH - 1:0] addrb,
output [DATA_WIDTH - 1:0] doutb
);
//Parameters
//Registers/Wires
reg [DATA_WIDTH - 1:0] mem [0:2 ** ADDRESS_WIDTH];
reg [DATA_WIDTH - 1:0] dout;
//Submodules
//Asynchronous Logic
assign doutb = dout;
//Synchronous Logic
//write only on the A side
`ifdef SIMULATION
integer i;
initial begin
i = 0;
for (i = 0; i < (2 ** ADDRESS_WIDTH); i = i + 1) begin
if (INC_NUM_PATTERN) begin
mem[i] <= i;
end
else begin
//Zero Everything Out
mem[i] <= 0;
end
end
end
`endif
always @ (posedge clka)
begin
if ( wea ) begin
mem[addra] <= dina;
end
end
//read only on the b side
always @ (posedge clkb)
begin
dout <= mem[addrb];
end
endmodule
|
//==================================================================================================
// Filename : uart_send.v
// Created On : 2015-05-27 11:13:22
// Last Modified : 2015-05-27 12:46:45
// Revision : 1.0
// Author : Ángel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Testbench UART input generator
//==================================================================================================
`timescale 1ns/100ps
module uart_send #(
parameter BAUD_RATE = 115200
)(
input clk,
input [7:0] tx_data,
input send,
output reg uart_tx,
output reg uart_tx_busy
);
//----------------------------------------------------------------------------
// localparams
//----------------------------------------------------------------------------
localparam UART_PERIOD = 1000000000/BAUD_RATE; // nS
// each clock, trigger the task. Only if send == 1'b1
//----------------------------------------------------------------------------
always @(posedge clk) begin
if (send) begin
task_uart_tx;
end
end
//----------------------------------------------------------------------------
// task
//----------------------------------------------------------------------------
task task_uart_tx;
reg [9:0] tx_buffer; // output buffer
integer tx_cnt; // counter
// task
begin
#(1); // delay FTW
uart_tx_busy = 1'b1; //
uart_tx = 1'b1; // idle
tx_buffer = {1'b1, tx_data, 1'b0}; // extend data
for(tx_cnt = 0; tx_cnt < 10; tx_cnt = tx_cnt + 1) begin
#(UART_PERIOD);
uart_tx = tx_buffer[tx_cnt];
end
uart_tx_busy = 1'b0;
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211A_SYMBOL_V
`define SKY130_FD_SC_HD__O211A_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o211a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41O_TB_V
`define SKY130_FD_SC_HS__A41O_TB_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a41o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 A4 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 A3 = 1'b0;
#360 A4 = 1'b0;
#380 B1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 B1 = 1'b1;
#500 A4 = 1'b1;
#520 A3 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 B1 = 1'bx;
#640 A4 = 1'bx;
#660 A3 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__a41o dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41O_TB_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : DLP Store.
// File : dlp_store.v
// Author : Frank Bruno
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// this module stores the dlp data and outputs the data when needed
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module dlp_store
#(parameter BYTES = 4)
(
input hb_clk, // Host bus clock.
input hb_rstn, // Reset signal for control signals
input dlp_rstn_mc, // Synchronous stopping of DLP
input dlp_wreg_pop, // DLP push signal.
input [(BYTES*8)-1:0] dlp_data, // memory controller data in
input dlf, // format selector for format 4
input text, // text mode selector
input char_select, // character selector
input [3:0] sorg_upper, // Upper 4 bits of sorg
output reg [1:0] list_format, // Display list format
output [1:0] wcount, /* Number of registers to write:
* 00 (default) write 3 words
* 01 one word
* 10 two words
* 11 three words */
output wvs, // Wait for vertical sync */
output [31:0] table_org0, // Origin pointer to text tables
output [31:0] table_org1, // Origin pointer to text tables
output char_count, // number of characters 0=1, 1=2
output [31:0] curr_sorg, // Source origin of current entry
output [3:0] curr_pg_cnt, // Pages of current entry
output [7:0] curr_height, // height of current entry
output [7:0] curr_width, // width of current entry
output [8:2] aad,bad,cad, // Address for data
output [127:0] dl_temp, // Mux'd input to DLP
output [15:0] dest_x, // X destination for text mode
output [15:0] dest_y // Y destiantion for text mode
);
reg [127:0] dl_data_reg; // Store data from MC
reg [127:0] dl_text_reg; // Store data from MC
wire [1:0] dlp_format; /* format of the dlp, consists of
* dlf in the command reg
* reg[25:24]
* 000: 3 register write mode
* 001: dma mode
* 01x: textmode
* 1xx: four register write mode */
wire [31:0] dest0, /* XY destination of glyphs */
dest1; /* XY destination of glyphs */
wire [27:0] sorg0, /* Source origin for glyphs */
sorg1; /* Source origin for glyphs */
wire [3:0] pg_cnt0, /* number of pages of glyph */
pg_cnt1; /* number of pages of glyph */
wire [7:0] height0, /* height of glyph */
height1; /* height of glyph */
wire [7:0] width0, /* width of glyph */
width1; /* width of glyph */
wire [7:0] x_off0, /* X offset into the glyph */
x_off1; /* x offset into the glyph */
wire [7:0] y_off0, /* y offset into the glyph */
y_off1; /* y offset into the glyph */
wire curr_org; /* which half of table entry */
wire [15:0] y_off_n; /* inverted Y offset */
wire [31:0] curr_dest; /* destination of current entry */
wire [7:0] curr_x_off; /* X offset of current entry */
wire [7:0] curr_y_off; /* Y offset of current entry */
localparam
REG3 = 2'b00, // 3 registers programmable
REG4 = 2'b01, // 4 registers fixed
DMA = 2'b10, // AGP DMA mode
TEXT = 2'b11; // Text processing mode
/************************************************************************/
/* Mode selector ********************************************************/
always @*
casex ({dlf, dlp_format}) /* synopsys full_case parallel_case */
3'b1_xx: list_format = REG4;
3'b0_00: list_format = REG3;
3'b0_01: list_format = DMA;
3'b0_1x: list_format = TEXT;
endcase
/* Data Registers *******************************************************/
always @(posedge hb_clk or negedge hb_rstn)
if (!hb_rstn) begin
dl_data_reg[31] <= 1'b0;
dl_data_reg[27:24] <= 4'b0;
end else if (dlp_rstn_mc) begin
dl_data_reg[31] <= 1'b0;
dl_data_reg[27:24] <= 4'b0;
end else if (dlp_wreg_pop) begin
if (~text)
case (BYTES)
4: begin
dl_data_reg[127:96] <= dlp_data;
dl_data_reg[95:64] <= dl_data_reg[127:96];
dl_data_reg[63:32] <= dl_data_reg[95:64];
dl_data_reg[31:0] <= dl_data_reg[63:32];
end
8: begin
dl_data_reg[127:64] <= dlp_data;
dl_data_reg[63:0] <= dl_data_reg[127:64];
end
default:
// BYTES = 16
dl_data_reg <= dlp_data;
endcase // case(BYTES)
else
case (BYTES)
4: begin
dl_text_reg[127:96] <= dlp_data;
dl_text_reg[95:64] <= dl_text_reg[127:96];
dl_text_reg[63:32] <= dl_text_reg[95:64];
dl_text_reg[31:0] <= dl_text_reg[63:32];
end
8: begin
dl_text_reg[127:64] <= dlp_data;
dl_text_reg[63:0] <= dl_text_reg[127:64];
end
default:
// BYTES = 16
dl_text_reg <= dlp_data;
endcase // case(BYTES)
end
/* Address Mux **********************************************************/
assign dl_temp = dl_data_reg;
// Command Data for REG3, REG4, DMA modes
assign aad = {dl_data_reg[28], dl_data_reg[7:2]};
assign bad = {dl_data_reg[29], dl_data_reg[15:10]};
assign cad = {dl_data_reg[30], dl_data_reg[23:18]};
assign dlp_format = dl_data_reg[25:24];
assign wcount = dl_data_reg[27:26];
assign wvs = dl_data_reg[31];
// Data for TEXT mode
// assign table_org0 = {dl_data_reg[95:89], dl_data_reg[24:0]};
assign table_org0 = {7'h0, dl_data_reg[24:0]};
assign char_count = dl_data_reg[27];
assign dest0 = dl_data_reg[63:32];
// assign table_org1 = dl_data_reg[95:64];
assign table_org1 = {7'h0, dl_data_reg[88:64]};
assign dest1 = dl_data_reg[127:96];
// assign sorg0 = dl_text_reg[27:0];
assign sorg0 = {3'b000, dl_text_reg[24:0]};
assign pg_cnt0 = dl_text_reg[31:28];
assign height0 = dl_text_reg[39:32];
assign width0 = dl_text_reg[47:40];
assign y_off0 = dl_text_reg[55:48];
assign x_off0 = dl_text_reg[63:56];
// assign sorg1 = dl_text_reg[91:64];
assign sorg1 = {3'b000, dl_text_reg[88:64]};
assign pg_cnt1 = dl_text_reg[95:92];
assign height1 = dl_text_reg[103:96];
assign width1 = dl_text_reg[111:104];
assign y_off1 = dl_text_reg[119:112];
assign x_off1 = dl_text_reg[127:120];
// Select current character
assign curr_org = (char_select) ? table_org1[3] : table_org0[3];
assign curr_dest = (char_select) ? dest1 : dest0;
// assign curr_sorg = (curr_org) ? {sorg_upper, sorg1} : {sorg_upper, sorg0};
assign curr_sorg = (curr_org) ? {4'h0, sorg1} : {4'h0, sorg0};
assign curr_pg_cnt = (curr_org) ? pg_cnt1 : pg_cnt0;
assign curr_height = (curr_org) ? height1 : height0;
assign curr_width = (curr_org) ? width1 : width0;
assign curr_x_off = (curr_org) ? x_off1 : x_off0;
assign curr_y_off = (curr_org) ? y_off1 : y_off0;
//
// Formerly DLP_ALU
// X offset adder
assign dest_x = curr_dest[31:16] +
{{8{curr_x_off[7]}}, curr_x_off}; // X offset adder
// Y offset subtractor
assign y_off_n = ~{{8{curr_y_off[7]}}, curr_y_off};
assign dest_y = curr_dest[15:0] + y_off_n + 16'h1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLXTP_BEHAVIORAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTP_BEHAVIORAL_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
// No shared code for this OVL
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not FALSE");
end
end
end
assign fire_2state_1 = (test_expr == 1'b1);
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
`else
reg fire_xcheck_1;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
end
wire valid_test_expr = ((test_expr ^ test_expr) == 1'b0);
always @ (valid_test_expr) begin
if (valid_test_expr) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
// No coverage for this OVL
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:12.0
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dcfifo_32in_32out_16kb_wr_cnt (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
wr_data_count
);
input wire rst;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
input wire wr_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [31 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [31 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire [1 : 0] wr_data_count;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(32),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_FAMILY("artix7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(509),
.C_PROG_FULL_THRESH_NEGATE_VAL(508),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(2),
.C_WR_DEPTH(512),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(9'B0),
.prog_empty_thresh_assert(9'B0),
.prog_empty_thresh_negate(9'B0),
.prog_full_thresh(9'B0),
.prog_full_thresh_assert(9'B0),
.prog_full_thresh_negate(9'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(wr_data_count),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__MUX2_FUNCTIONAL_PP_V
/**
* mux2: 2-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to10_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_2to10_out_X , A0, A1, S );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_2to10_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_FUNCTIONAL_PP_V
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: obc_lower.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module obc_lower (
address,
clock,
data,
wren,
q);
input [8:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "9"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL obc_lower_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32O_1_V
`define SKY130_FD_SC_HS__A32O_1_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a32o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a32o_1 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32O_1_V
|
// file: Clock50MHz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module Clock50MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock50MHz_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dec_table.v when simulating
// the core, dec_table. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dec_table(
clka,
addra,
douta
);
input clka;
input [7 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("dec_table.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// Code generated by Icestudio 0.8.1w202112300112
`default_nettype none
//---- Top entity
module main #(
parameter v771499 = "v771499.list"
) (
input [1:0] v2b2ed6,
input vclk,
output v290ef3,
output [7:0] v036815
);
localparam p1 = v771499;
wire [0:7] w0;
wire [0:1] w2;
wire [0:1] w3;
wire [0:7] w4;
wire w5;
wire w6;
wire w7;
assign v036815 = w0;
assign w3 = v2b2ed6;
assign v290ef3 = w5;
assign w6 = vclk;
assign w7 = vclk;
assign w7 = w6;
v6809d2 #(
.v9298ae(p1)
) v60d27e (
.vc4e0ba(w0),
.v6d8c97(w4),
.v6dda25(w6)
);
v8efab2 v40be46 (
.v0c06c3(w2),
.v20cbde(w4)
);
v7caf1c v46ef23 (
.ved9bf3(w2),
.vcc8287(w3),
.v25ab12(w7)
);
vd30ca9 v56c957 (
.v9fb85f(w5)
);
endmodule
//---- Top entity
module v6809d2 #(
parameter v9298ae = "v9298ae.list"
) (
input v6dda25,
input [7:0] v6d8c97,
output [7:0] vc4e0ba
);
localparam p3 = v9298ae;
wire w0;
wire w1;
wire w2;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:7] w8;
wire [0:7] w9;
wire w10;
wire [0:31] w11;
wire [0:31] w12;
wire [0:31] w13;
wire [0:31] w14;
wire [0:31] w15;
wire [0:3] w16;
wire w17;
wire w18;
wire w19;
assign w4 = v6dda25;
assign w5 = v6dda25;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign vc4e0ba = w8;
assign w9 = v6d8c97;
assign w1 = w0;
assign w5 = w4;
assign w6 = w4;
assign w6 = w5;
assign w7 = w4;
assign w7 = w5;
assign w7 = w6;
assign w12 = w11;
vf1cffe v468719 (
.ve9ba68(w0),
.v79476f(w1),
.v6dda25(w4),
.v27dec4(w10),
.v9231ba(w11),
.vfc9252(w13),
.va0e119(w14),
.ve17e80(w16)
);
vd30ca9 v16f275 (
.v9fb85f(w0)
);
v893ac6 #(
.vba98fe(p3)
) vc59f55 (
.v6dda25(w5),
.v5d7e06(w11),
.v9a5b8a(w15)
);
ve4c3a8 v29c9ed (
.v5c832d(w12),
.v4642b6(w17),
.vd02149(w18),
.vafdfa0(w19)
);
vf68661 v66eb94 (
.v6dda25(w7),
.vfeb41a(w8),
.vf837fe(w13),
.ve9e5a1(w16),
.ve146f6(w19)
);
v145d1e v3f3e01 (
.vc74a9c(w9),
.vb76294(w14),
.vb79ed5(w15),
.v6287a6(w17),
.v19f646(w18)
);
v04e061 vb15d38 (
.v4642b6(w2),
.vd6bebe(w6)
);
v3676a0 vd1c5e9 (
.v0e28cb(w2),
.vcbab45(w10)
);
endmodule
//---------------------------------------------------
//-- Generic-comp-clk
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic component with clk input
//---------------------------------------------------
//---- Top entity
module vf1cffe (
input v6dda25,
input v27dec4,
input [31:0] va0e119,
input v79476f,
input ve9ba68,
output [31:0] v9231ba,
output [31:0] vfc9252,
output [3:0] ve17e80,
output v8d2eee
);
wire w0;
wire [0:31] w1;
wire w2;
wire w3;
wire [0:31] w4;
wire [0:31] w5;
wire [0:3] w6;
wire w7;
wire w8;
assign w0 = v27dec4;
assign w1 = va0e119;
assign w2 = v79476f;
assign w3 = ve9ba68;
assign v9231ba = w4;
assign vfc9252 = w5;
assign ve17e80 = w6;
assign v8d2eee = w7;
assign w8 = v6dda25;
vf1cffe_v172245 v172245 (
.reset(w0),
.mem_rdata(w1),
.mem_rbusy(w2),
.mem_wbusy(w3),
.mem_addr(w4),
.mem_wdata(w5),
.mem_wmask(w6),
.mem_rstrb(w7),
.clk(w8)
);
endmodule
//---------------------------------------------------
//-- RV32I
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- RV32I
//---------------------------------------------------
module vf1cffe_v172245 (
input clk,
input reset,
input [31:0] mem_rdata,
input mem_rbusy,
input mem_wbusy,
output [31:0] mem_addr,
output [31:0] mem_wdata,
output [3:0] mem_wmask,
output mem_rstrb
);
localparam RESET_ADDR = 0;
parameter ADDR_WIDTH = 24;
localparam ADDR_PAD = {(32-ADDR_WIDTH){1'b0}}; // 32-bits padding for addrs
/***************************************************************************/
// Instruction decoding.
/***************************************************************************/
// Extracts rd,rs1,rs2,funct3,imm and opcode from instruction.
// Reference: Table page 104 of:
// https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
// The destination register
wire [4:0] rdId = instr[11:7];
// The ALU function, decoded in 1-hot form (doing so reduces LUT count)
// It is used as follows: funct3Is[val] <=> funct3 == val
(* onehot *)
wire [7:0] funct3Is = 8'b00000001 << instr[14:12];
// The five immediate formats, see RiscV reference (link above), Fig. 2.4 p. 12
wire [31:0] Uimm = { instr[31], instr[30:12], {12{1'b0}}};
wire [31:0] Iimm = {{21{instr[31]}}, instr[30:20]};
/* verilator lint_off UNUSED */ // MSBs of SBJimms are not used by addr adder.
wire [31:0] Simm = {{21{instr[31]}}, instr[30:25],instr[11:7]};
wire [31:0] Bimm = {{20{instr[31]}}, instr[7],instr[30:25],instr[11:8],1'b0};
wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12],instr[20],instr[30:21],1'b0};
/* verilator lint_on UNUSED */
// Base RISC-V (RV32I) has only 10 different instructions !
wire isLoad = (instr[6:2] == 5'b00000); // rd <- mem[rs1+Iimm]
wire isALUimm = (instr[6:2] == 5'b00100); // rd <- rs1 OP Iimm
wire isAUIPC = (instr[6:2] == 5'b00101); // rd <- PC + Uimm
wire isStore = (instr[6:2] == 5'b01000); // mem[rs1+Simm] <- rs2
wire isALUreg = (instr[6:2] == 5'b01100); // rd <- rs1 OP rs2
wire isLUI = (instr[6:2] == 5'b01101); // rd <- Uimm
wire isBranch = (instr[6:2] == 5'b11000); // if(rs1 OP rs2) PC<-PC+Bimm
wire isJALR = (instr[6:2] == 5'b11001); // rd <- PC+4; PC<-rs1+Iimm
wire isJAL = (instr[6:2] == 5'b11011); // rd <- PC+4; PC<-PC+Jimm
wire isSYSTEM = (instr[6:2] == 5'b11100); // rd <- cycles
wire isALU = isALUimm | isALUreg;
/***************************************************************************/
// The register file.
/***************************************************************************/
reg [31:0] rs1;
reg [31:0] rs2;
reg [31:0] registerFile [31:0];
always @(posedge clk) begin
if (writeBack)
if (rdId != 0)
registerFile[rdId] <= writeBackData;
end
/***************************************************************************/
// The ALU. Does operations and tests combinatorially, except shifts.
/***************************************************************************/
// First ALU source, always rs1
wire [31:0] aluIn1 = rs1;
// Second ALU source, depends on opcode:
// ALUreg, Branch: rs2
// ALUimm, Load, JALR: Iimm
wire [31:0] aluIn2 = isALUreg | isBranch ? rs2 : Iimm;
reg [31:0] aluReg; // The internal register of the ALU, used by shift.
reg [4:0] aluShamt; // Current shift amount.
wire aluBusy = |aluShamt; // ALU is busy if shift amount is non-zero.
wire aluWr; // ALU write strobe, starts shifting.
// The adder is used by both arithmetic instructions and JALR.
wire [31:0] aluPlus = aluIn1 + aluIn2;
// Use a single 33 bits subtract to do subtraction and all comparisons
// (trick borrowed from swapforth/J1)
wire [32:0] aluMinus = {1'b1, ~aluIn2} + {1'b0,aluIn1} + 33'b1;
wire LT = (aluIn1[31] ^ aluIn2[31]) ? aluIn1[31] : aluMinus[32];
wire LTU = aluMinus[32];
wire EQ = (aluMinus[31:0] == 0);
// Notes:
// - instr[30] is 1 for SUB and 0 for ADD
// - for SUB, need to test also instr[5] to discriminate ADDI:
// (1 for ADD/SUB, 0 for ADDI, and Iimm used by ADDI overlaps bit 30 !)
// - instr[30] is 1 for SRA (do sign extension) and 0 for SRL
wire [31:0] aluOut =
(funct3Is[0] ? instr[30] & instr[5] ? aluMinus[31:0] : aluPlus : 32'b0) |
(funct3Is[2] ? {31'b0, LT} : 32'b0) |
(funct3Is[3] ? {31'b0, LTU} : 32'b0) |
(funct3Is[4] ? aluIn1 ^ aluIn2 : 32'b0) |
(funct3Is[6] ? aluIn1 | aluIn2 : 32'b0) |
(funct3Is[7] ? aluIn1 & aluIn2 : 32'b0) |
(funct3IsShift ? aluReg : 32'b0) ;
wire funct3IsShift = funct3Is[1] | funct3Is[5];
always @(posedge clk) begin
if(aluWr) begin
if (funct3IsShift) begin // SLL, SRA, SRL
aluReg <= aluIn1;
aluShamt <= aluIn2[4:0];
end
end
// Compact form of:
// funct3=001 -> SLL (aluReg <= aluReg << 1)
// funct3=101 & instr[30] -> SRA (aluReg <= {aluReg[31], aluReg[31:1]})
// funct3=101 & !instr[30] -> SRL (aluReg <= {1'b0, aluReg[31:1]})
if (|aluShamt) begin
aluShamt <= aluShamt - 1;
aluReg <= funct3Is[1] ? aluReg << 1 : // SLL
{instr[30] & aluReg[31], aluReg[31:1]}; // SRA,SRL
end
end
/***************************************************************************/
// The predicate for conditional branches.
/***************************************************************************/
wire predicate =
funct3Is[0] & EQ | // BEQ
funct3Is[1] & !EQ | // BNE
funct3Is[4] & LT | // BLT
funct3Is[5] & !LT | // BGE
funct3Is[6] & LTU | // BLTU
funct3Is[7] & !LTU ; // BGEU
/***************************************************************************/
// Program counter and branch target computation.
/***************************************************************************/
reg [ADDR_WIDTH-1:0] PC; // The program counter.
reg [31:2] instr; // Latched instruction. Note that bits 0 and 1 are
// ignored (not used in RV32I base instr set).
wire [ADDR_WIDTH-1:0] PCplus4 = PC + 4;
// An adder used to compute branch address, JAL address and AUIPC.
// branch->PC+Bimm AUIPC->PC+Uimm JAL->PC+Jimm
// Equivalent to PCplusImm = PC + (isJAL ? Jimm : isAUIPC ? Uimm : Bimm)
wire [ADDR_WIDTH-1:0] PCplusImm = PC + ( instr[3] ? Jimm[ADDR_WIDTH-1:0] :
instr[4] ? Uimm[ADDR_WIDTH-1:0] :
Bimm[ADDR_WIDTH-1:0] );
// A separate adder to compute the destination of load/store.
// testing instr[5] is equivalent to testing isStore in this context.
wire [ADDR_WIDTH-1:0] loadstore_addr = rs1[ADDR_WIDTH-1:0] +
(instr[5] ? Simm[ADDR_WIDTH-1:0] : Iimm[ADDR_WIDTH-1:0]);
assign mem_addr = {ADDR_PAD,
state[WAIT_INSTR_bit] | state[FETCH_INSTR_bit] ?
PC : loadstore_addr
};
/***************************************************************************/
// The value written back to the register file.
/***************************************************************************/
wire [31:0] writeBackData =
/* verilator lint_off WIDTH */
(isSYSTEM ? cycles : 32'b0) | // SYSTEM
/* verilator lint_on WIDTH */
(isLUI ? Uimm : 32'b0) | // LUI
(isALU ? aluOut : 32'b0) | // ALUreg, ALUimm
(isAUIPC ? {ADDR_PAD,PCplusImm} : 32'b0) | // AUIPC
(isJALR | isJAL ? {ADDR_PAD,PCplus4 } : 32'b0) | // JAL, JALR
(isLoad ? LOAD_data : 32'b0); // Load
/***************************************************************************/
// LOAD/STORE
/***************************************************************************/
// All memory accesses are aligned on 32 bits boundary. For this
// reason, we need some circuitry that does unaligned halfword
// and byte load/store, based on:
// - funct3[1:0]: 00->byte 01->halfword 10->word
// - mem_addr[1:0]: indicates which byte/halfword is accessed
wire mem_byteAccess = instr[13:12] == 2'b00; // funct3[1:0] == 2'b00;
wire mem_halfwordAccess = instr[13:12] == 2'b01; // funct3[1:0] == 2'b01;
// LOAD, in addition to funct3[1:0], LOAD depends on:
// - funct3[2] (instr[14]): 0->do sign expansion 1->no sign expansion
wire LOAD_sign =
!instr[14] & (mem_byteAccess ? LOAD_byte[7] : LOAD_halfword[15]);
wire [31:0] LOAD_data =
mem_byteAccess ? {{24{LOAD_sign}}, LOAD_byte} :
mem_halfwordAccess ? {{16{LOAD_sign}}, LOAD_halfword} :
mem_rdata ;
wire [15:0] LOAD_halfword =
loadstore_addr[1] ? mem_rdata[31:16] : mem_rdata[15:0];
wire [7:0] LOAD_byte =
loadstore_addr[0] ? LOAD_halfword[15:8] : LOAD_halfword[7:0];
// STORE
assign mem_wdata[ 7: 0] = rs2[7:0];
assign mem_wdata[15: 8] = loadstore_addr[0] ? rs2[7:0] : rs2[15: 8];
assign mem_wdata[23:16] = loadstore_addr[1] ? rs2[7:0] : rs2[23:16];
assign mem_wdata[31:24] = loadstore_addr[0] ? rs2[7:0] :
loadstore_addr[1] ? rs2[15:8] : rs2[31:24];
// The memory write mask:
// 1111 if writing a word
// 0011 or 1100 if writing a halfword
// (depending on loadstore_addr[1])
// 0001, 0010, 0100 or 1000 if writing a byte
// (depending on loadstore_addr[1:0])
wire [3:0] STORE_wmask =
mem_byteAccess ?
(loadstore_addr[1] ?
(loadstore_addr[0] ? 4'b1000 : 4'b0100) :
(loadstore_addr[0] ? 4'b0010 : 4'b0001)
) :
mem_halfwordAccess ?
(loadstore_addr[1] ? 4'b1100 : 4'b0011) :
4'b1111;
/*************************************************************************/
// And, last but not least, the state machine.
/*************************************************************************/
localparam FETCH_INSTR_bit = 0;
localparam WAIT_INSTR_bit = 1;
localparam EXECUTE_bit = 2;
localparam WAIT_ALU_OR_MEM_bit = 3;
localparam NB_STATES = 4;
localparam FETCH_INSTR = 1 << FETCH_INSTR_bit;
localparam WAIT_INSTR = 1 << WAIT_INSTR_bit;
localparam EXECUTE = 1 << EXECUTE_bit;
localparam WAIT_ALU_OR_MEM = 1 << WAIT_ALU_OR_MEM_bit;
(* onehot *)
reg [NB_STATES-1:0] state;
// The signals (internal and external) that are determined
// combinatorially from state and other signals.
// register write-back enable.
wire writeBack = ~(isBranch | isStore ) &
(state[EXECUTE_bit] | state[WAIT_ALU_OR_MEM_bit]);
// The memory-read signal.
assign mem_rstrb = state[EXECUTE_bit] & isLoad | state[FETCH_INSTR_bit];
// The mask for memory-write.
assign mem_wmask = {4{state[EXECUTE_bit] & isStore}} & STORE_wmask;
// aluWr starts computation (shifts) in the ALU.
assign aluWr = state[EXECUTE_bit] & isALU;
wire jumpToPCplusImm = isJAL | (isBranch & predicate);
`ifdef NRV_IS_IO_ADDR
wire needToWait = isLoad |
isStore & `NRV_IS_IO_ADDR(mem_addr) |
isALU & funct3IsShift;
`else
wire needToWait = isLoad | isStore | isALU & funct3IsShift;
`endif
always @(posedge clk) begin
if(!reset) begin
state <= WAIT_ALU_OR_MEM; // Just waiting for !mem_wbusy
PC <= RESET_ADDR[ADDR_WIDTH-1:0];
end else
// See note [1] at the end of this file.
(* parallel_case *)
case(1'b1)
state[WAIT_INSTR_bit]: begin
if(!mem_rbusy) begin // may be high when executing from SPI flash
rs1 <= registerFile[mem_rdata[19:15]];
rs2 <= registerFile[mem_rdata[24:20]];
instr <= mem_rdata[31:2]; // Bits 0 and 1 are ignored (see
state <= EXECUTE; // also the declaration of instr).
end
end
state[EXECUTE_bit]: begin
PC <= isJALR ? {aluPlus[ADDR_WIDTH-1:1],1'b0} :
jumpToPCplusImm ? PCplusImm :
PCplus4;
state <= needToWait ? WAIT_ALU_OR_MEM : FETCH_INSTR;
end
state[WAIT_ALU_OR_MEM_bit]: begin
if(!aluBusy & !mem_rbusy & !mem_wbusy) state <= FETCH_INSTR;
end
default: begin // FETCH_INSTR
state <= WAIT_INSTR;
end
endcase
end
/***************************************************************************/
// Cycle counter
/***************************************************************************/
`ifdef NRV_COUNTER_WIDTH
reg [`NRV_COUNTER_WIDTH-1:0] cycles;
`else
reg [31:0] cycles;
`endif
always @(posedge clk) cycles <= cycles + 1;
`ifdef BENCH
initial begin
cycles = 0;
aluShamt = 0;
registerFile[0] = 0;
end
`endif
/*****************************************************************************/
// Notes:
//
// [1] About the "reverse case" statement, also used in Claire Wolf's picorv32:
// It is just a cleaner way of writing a series of cascaded if() statements,
// To understand it, think about the case statement *in general* as follows:
// case (expr)
// val_1: statement_1
// val_2: statement_2
// ... val_n: statement_n
// endcase
// The first statement_i such that expr == val_i is executed.
// Now if expr is 1'b1:
// case (1'b1)
// cond_1: statement_1
// cond_2: statement_2
// ... cond_n: statement_n
// endcase
// It is *exactly the same thing*, the first statement_i such that
// expr == cond_i is executed (that is, such that 1'b1 == cond_i,
// in other words, such that cond_i is true)
// More on this:
// https://stackoverflow.com/questions/15418636/case-statement-in-verilog
//
// [2] state uses 1-hot encoding (at any time, state has only one bit set to 1).
// It uses a larger number of bits (one bit per state), but often results in
// a both more compact (fewer LUTs) and faster state machine.
endmodule
//---- Top entity
module vd30ca9 (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vd30ca9_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 0
//---------------------------------------------------
module vd30ca9_vb2eccd (
output q
);
//-- Constant bit-0
assign q = 1'b0;
endmodule
//---- Top entity
module v893ac6 #(
parameter vba98fe = "vba98fe.list"
) (
input v6dda25,
input [31:0] v5d7e06,
output [31:0] v9a5b8a
);
localparam p6 = vba98fe;
wire w0;
wire [0:31] w1;
wire w2;
wire [0:31] w3;
wire [0:9] w4;
wire [0:31] w5;
wire w7;
wire [0:31] w8;
wire [0:31] w9;
assign w7 = v6dda25;
assign v9a5b8a = w8;
assign w9 = v5d7e06;
v7a4adb v57e893 (
.v712289(w0),
.v51eedb(w1),
.v4f6beb(w9)
);
vd30ca9 vc98086 (
.v9fb85f(w0)
);
v7a4adb vddefc3 (
.v4f6beb(w1),
.v51eedb(w5)
);
vd30ca9 v30628d (
.v9fb85f(w2)
);
v2c97f6 v773b48 (
.v7c9bd8(w3)
);
v675d07 #(
.v5a4ee6(p6)
) vdbacf7 (
.v23dc54(w2),
.v6f4b70(w3),
.vb261ad(w4),
.v922e3d(w7),
.vddff9f(w8)
);
v794b6d va8ea8d (
.vef1612(w4),
.ve841af(w5)
);
endmodule
//---------------------------------------------------
//-- Generic-comp-clk
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic component with clk input
//---------------------------------------------------
//---- Top entity
module v7a4adb (
input v712289,
input [31:0] v4f6beb,
output [31:0] v51eedb,
output v7e4f0f
);
wire [0:31] w0;
wire w1;
wire w2;
wire [0:30] w3;
wire [0:31] w4;
assign w0 = v4f6beb;
assign v7e4f0f = w1;
assign w2 = v712289;
assign v51eedb = w4;
vecd30a vd4273f (
.ve841af(w0),
.v8d1a42(w1),
.v11ef80(w3)
);
v51b3c0 v9b7810 (
.v411a12(w2),
.vd40455(w3),
.v7d0a31(w4)
);
endmodule
//---------------------------------------------------
//-- SR1-32bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- SR1-32bits: Shift a 32-bit value one bit right. MSB is filled with the input "in"
//---------------------------------------------------
//---- Top entity
module vecd30a (
input [31:0] ve841af,
output [30:0] v11ef80,
output v8d1a42
);
wire [0:31] w0;
wire w1;
wire [0:30] w2;
assign w0 = ve841af;
assign v8d1a42 = w1;
assign v11ef80 = w2;
vecd30a_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-31-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-31-1: Split the 32-bits bus into two buses of 31 and 1 wires
//---------------------------------------------------
module vecd30a_v9a2a06 (
input [31:0] i,
output [30:0] o1,
output o0
);
assign o1 = i[31:1];
assign o0 = i[0];
endmodule
//---- Top entity
module v51b3c0 (
input v411a12,
input [30:0] vd40455,
output [31:0] v7d0a31
);
wire [0:31] w0;
wire [0:30] w1;
wire w2;
assign v7d0a31 = w0;
assign w1 = vd40455;
assign w2 = v411a12;
v51b3c0_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Join-1-31
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Join-1-31: Join the two buses into an 32-bits Bus
//---------------------------------------------------
module v51b3c0_v9a2a06 (
input i1,
input [30:0] i0,
output [31:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v2c97f6 #(
parameter vfffc23 = 0
) (
output [31:0] v7c9bd8
);
localparam p0 = vfffc23;
wire [0:31] w1;
assign v7c9bd8 = w1;
v959751 #(
.vc5c8ea(p0)
) v9f49e7 (
.vbc97e4(w1)
);
endmodule
//---------------------------------------------------
//-- 32bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 32bits constant value: 0
//---------------------------------------------------
//---- Top entity
module v959751 #(
parameter vc5c8ea = 0
) (
output [31:0] vbc97e4
);
localparam p0 = vc5c8ea;
wire [0:31] w1;
assign vbc97e4 = w1;
v959751_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 32-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 32-bits generic constant
//---------------------------------------------------
module v959751_v465065 #(
parameter VALUE = 0
) (
output [31:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v675d07 #(
parameter v5a4ee6 = "v5a4ee6.list"
) (
input v922e3d,
input [9:0] vb261ad,
input [31:0] v6f4b70,
input v23dc54,
output [31:0] vddff9f
);
localparam p2 = v5a4ee6;
wire w0;
wire w1;
wire [0:9] w3;
wire [0:31] w4;
wire [0:31] w5;
assign w0 = v922e3d;
assign w1 = v23dc54;
assign w3 = vb261ad;
assign vddff9f = w4;
assign w5 = v6f4b70;
v675d07_vbaa912 #(
.ROMF(p2)
) vbaa912 (
.clk(w0),
.wr(w1),
.addr(w3),
.data_out(w4),
.data_in(w5)
);
endmodule
//---------------------------------------------------
//-- Memory-1Kx32
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Smem 1kx32: Synchronous memory: 1024 words of 32 bits
//---------------------------------------------------
module v675d07_vbaa912 #(
parameter ROMF = 0
) (
input clk,
input [9:0] addr,
input [31:0] data_in,
input wr,
output [31:0] data_out
);
//-- Address with
localparam ADDR_WIDTH = 10;
//-- Data with
localparam DATA_WIDTH = 32;
//-- Size of the memory
localparam SIZE = 1 << ADDR_WIDTH;
//-- Memory itself
reg [DATA_WIDTH-1:0] mem[0:SIZE-1];
//-- The data_out is a registered output (not a wire)
reg data_out;
//-- Reading port: Synchronous
always @(posedge clk)
begin
data_out <= mem[addr];
end
//-- Writing port: Synchronous
always @(posedge clk)
begin
if (wr) mem[addr] <= data_in;
end
//-- Init the memory
initial begin
if (ROMF)
$readmemh(ROMF, mem, 0, SIZE-1);
end
endmodule
//---- Top entity
module v794b6d (
input [31:0] ve841af,
output [21:0] v51fb1f,
output [9:0] vef1612
);
wire [0:31] w0;
wire [0:9] w1;
wire [0:21] w2;
assign w0 = ve841af;
assign vef1612 = w1;
assign v51fb1f = w2;
v794b6d_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-22-10
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-22-10: Split the 32-bits bus into two buses of 22 and 10 wires
//---------------------------------------------------
module v794b6d_v9a2a06 (
input [31:0] i,
output [21:0] o1,
output [9:0] o0
);
assign o1 = i[31:10];
assign o0 = i[9:0];
endmodule
//---- Top entity
module ve4c3a8 #(
parameter v389bd1 = 5'h1F
) (
input [31:0] v5c832d,
output v4642b6,
output vafdfa0,
output vd02149
);
localparam p8 = v389bd1;
wire w0;
wire w1;
wire w2;
wire [0:14] w3;
wire [0:4] w4;
wire [0:4] w5;
wire [0:4] w6;
wire [0:4] w7;
wire [0:2] w9;
wire [0:31] w10;
wire [0:31] w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
assign w10 = v5c832d;
assign w11 = v5c832d;
assign v4642b6 = w12;
assign vafdfa0 = w13;
assign vd02149 = w14;
assign w2 = w1;
assign w6 = w4;
assign w11 = w10;
assign w16 = w15;
v3676a0 v8f98d9 (
.vcbab45(w0),
.v0e28cb(w1)
);
vba518e v72db53 (
.v0e28cb(w0),
.vcbab45(w13),
.v3ca442(w16)
);
vba518e v97a3cf (
.v3ca442(w2),
.vcbab45(w14),
.v0e28cb(w15)
);
v9a2795 v666bdb (
.vda577d(w1),
.vdee7c7(w9)
);
va7b832 ve316c5 (
.v29a212(w3),
.ve841af(w10)
);
vef0f91 v3ffece (
.vcbe66f(w3),
.vfa86aa(w4)
);
v1cc648 v736214 (
.vfad888(w4),
.vd80e4f(w5),
.v4642b6(w12)
);
v108a6d v2a89b0 (
.v6ece80(w5)
);
v1cc648 v01ba64 (
.vd80e4f(w6),
.vfad888(w7),
.v4642b6(w15)
);
v3693fc #(
.vc5c8ea(p8)
) v006a39 (
.vc8d3b9(w7)
);
ve500df vfe8608 (
.vbb2522(w9),
.ve841af(w11)
);
endmodule
//---------------------------------------------------
//-- Generic-comp
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Componente genérico
//---------------------------------------------------
//---- Top entity
module v3676a0 (
input v0e28cb,
output vcbab45
);
wire w0;
wire w1;
assign w0 = v0e28cb;
assign vcbab45 = w1;
v3676a0_vd54ca1 vd54ca1 (
.a(w0),
.q(w1)
);
endmodule
//---------------------------------------------------
//-- NOT
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- NOT gate (Verilog implementation)
//---------------------------------------------------
module v3676a0_vd54ca1 (
input a,
output q
);
//-- NOT Gate
assign q = ~a;
endmodule
//---- Top entity
module vba518e (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vba518e_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- AND2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Two bits input And gate
//---------------------------------------------------
module vba518e_vf4938a (
input a,
input b,
output c
);
//-- AND gate
//-- Verilog implementation
assign c = a & b;
endmodule
//---- Top entity
module v9a2795 (
input [2:0] vdee7c7,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire [0:2] w2;
wire w3;
assign v3f8943 = w0;
assign v64d863 = w1;
assign w2 = vdee7c7;
assign vda577d = w3;
v9a2795_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2),
.o2(w3)
);
endmodule
//---------------------------------------------------
//-- Bus3-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus3-Split-all: Split the 3-bits bus into three wires
//---------------------------------------------------
module v9a2795_v9a2a06 (
input [2:0] i,
output o2,
output o1,
output o0
);
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module va7b832 (
input [31:0] ve841af,
output [16:0] v62a8c1,
output [14:0] v29a212
);
wire [0:31] w0;
wire [0:14] w1;
wire [0:16] w2;
assign w0 = ve841af;
assign v29a212 = w1;
assign v62a8c1 = w2;
va7b832_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-17-15
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-17-15: Split the 32-bits bus into two buses of 17 and 15 wires
//---------------------------------------------------
module va7b832_v9a2a06 (
input [31:0] i,
output [16:0] o1,
output [14:0] o0
);
assign o1 = i[31:15];
assign o0 = i[14:0];
endmodule
//---- Top entity
module vef0f91 (
input [14:0] vcbe66f,
output [4:0] vfa86aa,
output [9:0] vbdb2c8
);
wire [0:14] w0;
wire [0:9] w1;
wire [0:4] w2;
assign w0 = vcbe66f;
assign vbdb2c8 = w1;
assign vfa86aa = w2;
vef0f91_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus15-Split-7-8 CLONE
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus15-Split-7-8: Split the 15-bits bus into two buses of 7 and 8 bits
//---------------------------------------------------
module vef0f91_v9a2a06 (
input [14:0] i,
output [4:0] o1,
output [9:0] o0
);
assign o1 = i[14:10];
assign o0 = i[9:0];
endmodule
//---- Top entity
module v1cc648 (
input [4:0] vd80e4f,
input [4:0] vfad888,
output v4642b6
);
wire w0;
wire [0:4] w1;
wire [0:4] w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
assign v4642b6 = w0;
assign w1 = vfad888;
assign w2 = vd80e4f;
v23b15b vc1b29d (
.v4642b6(w3),
.v27dec4(w5),
.v6848e9(w7)
);
v91f34c vf38386 (
.v427dd1(w1),
.v53baa6(w7),
.v479af4(w8)
);
v91f34c v83c3c9 (
.v427dd1(w2),
.v53baa6(w5),
.v479af4(w6)
);
v438230 v577a36 (
.v4642b6(w4),
.v693354(w6),
.v5369cd(w8)
);
vba518e v707c6e (
.vcbab45(w0),
.v0e28cb(w3),
.v3ca442(w4)
);
endmodule
//---------------------------------------------------
//-- comp2-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-5bit: Comparator of two 5-bit numbers
//---------------------------------------------------
//---- Top entity
module v23b15b (
input v27dec4,
input v6848e9,
output v4642b6
);
wire w0;
wire w1;
wire w2;
wire w3;
assign w1 = v27dec4;
assign v4642b6 = w2;
assign w3 = v6848e9;
vd12401 v955b2b (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v3676a0 vf92936 (
.v0e28cb(w0),
.vcbab45(w2)
);
endmodule
//---------------------------------------------------
//-- comp2-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-1bit: Comparator of two 1-bit numbers
//---------------------------------------------------
//---- Top entity
module vd12401 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vd12401_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- XOR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- XOR gate: two bits input xor gate
//---------------------------------------------------
module vd12401_vf4938a (
input a,
input b,
output c
);
//-- XOR gate
//-- Verilog implementation
assign c = a ^ b;
endmodule
//---- Top entity
module v91f34c (
input [4:0] v427dd1,
output v53baa6,
output [3:0] v479af4
);
wire [0:3] w0;
wire [0:4] w1;
wire w2;
assign v479af4 = w0;
assign w1 = v427dd1;
assign v53baa6 = w2;
v91f34c_v9a2a06 v9a2a06 (
.o0(w0),
.i(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus5-Split-1-4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus5-Split-1-4: Split the 5-bits bus into two buses of 1 and 4 bits
//---------------------------------------------------
module v91f34c_v9a2a06 (
input [4:0] i,
output o1,
output [3:0] o0
);
assign o1 = i[4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module v438230 (
input [3:0] v693354,
input [3:0] v5369cd,
output v4642b6
);
wire w0;
wire [0:3] w1;
wire [0:3] w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
assign v4642b6 = w0;
assign w1 = v693354;
assign w2 = v5369cd;
v23b15b v09a5a5 (
.v4642b6(w3),
.v27dec4(w12),
.v6848e9(w14)
);
v23b15b vc1b29d (
.v4642b6(w4),
.v27dec4(w11),
.v6848e9(w13)
);
v23b15b vcd27ce (
.v4642b6(w5),
.v27dec4(w9),
.v6848e9(w10)
);
vc4f23a vea9c80 (
.v985fcb(w1),
.v4f1fd3(w7),
.vda577d(w9),
.v3f8943(w11),
.v64d863(w12)
);
vc4f23a va7dcdc (
.v985fcb(w2),
.v4f1fd3(w8),
.vda577d(w10),
.v3f8943(w13),
.v64d863(w14)
);
v23b15b va0849c (
.v4642b6(w6),
.v27dec4(w7),
.v6848e9(w8)
);
veffd42 v6e3e65 (
.vcbab45(w0),
.v3ca442(w3),
.v0e28cb(w4),
.v033bf6(w5),
.v9eb652(w6)
);
endmodule
//---------------------------------------------------
//-- comp2-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Comp2-4bit: Comparator of two 4-bit numbers
//---------------------------------------------------
//---- Top entity
module vc4f23a (
input [3:0] v985fcb,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign w4 = v985fcb;
vc4f23a_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.i(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Split-all: Split the 4-bits bus into its wires
//---------------------------------------------------
module vc4f23a_v9a2a06 (
input [3:0] i,
output o3,
output o2,
output o1,
output o0
);
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module veffd42 (
input v9eb652,
input v033bf6,
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = v3ca442;
assign w1 = v9eb652;
assign w2 = v033bf6;
assign w3 = v0e28cb;
assign vcbab45 = w4;
vba518e vf3ef0f (
.v3ca442(w0),
.v0e28cb(w3),
.vcbab45(w6)
);
vba518e vdcc53d (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w5)
);
vba518e v17ac22 (
.vcbab45(w4),
.v0e28cb(w5),
.v3ca442(w6)
);
endmodule
//---------------------------------------------------
//-- AND4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Three bits input And gate
//---------------------------------------------------
//---- Top entity
module v108a6d #(
parameter vfffc23 = 0
) (
output [4:0] v6ece80
);
localparam p0 = vfffc23;
wire [0:4] w1;
assign v6ece80 = w1;
v3693fc #(
.vc5c8ea(p0)
) ve88537 (
.vc8d3b9(w1)
);
endmodule
//---------------------------------------------------
//-- 5bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 5bits constant value: 0
//---------------------------------------------------
//---- Top entity
module v3693fc #(
parameter vc5c8ea = 0
) (
output [4:0] vc8d3b9
);
localparam p0 = vc5c8ea;
wire [0:4] w1;
assign vc8d3b9 = w1;
v3693fc_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 5-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 5-bits generic constant (0-31)
//---------------------------------------------------
module v3693fc_v465065 #(
parameter VALUE = 0
) (
output [4:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module ve500df (
input [31:0] ve841af,
output [28:0] vfc82fb,
output [2:0] vbb2522
);
wire [0:31] w0;
wire [0:2] w1;
wire [0:28] w2;
assign w0 = ve841af;
assign vbb2522 = w1;
assign vfc82fb = w2;
ve500df_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-29-3
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-29-3: Split the 29-bits bus into two buses of 29 and 3 wires
//---------------------------------------------------
module ve500df_v9a2a06 (
input [31:0] i,
output [28:0] o1,
output [2:0] o0
);
assign o1 = i[31:3];
assign o0 = i[2:0];
endmodule
//---- Top entity
module vf68661 (
input v6dda25,
input [31:0] vf837fe,
input [3:0] ve9e5a1,
input ve146f6,
output [7:0] vfeb41a
);
wire w0;
wire [0:7] w1;
wire w2;
wire [0:7] w3;
wire w4;
wire [0:31] w5;
wire [0:3] w6;
wire w7;
assign vfeb41a = w3;
assign w4 = v6dda25;
assign w5 = vf837fe;
assign w6 = ve9e5a1;
assign w7 = ve146f6;
vf61fa3 v8cf02b (
.vcbab45(w0),
.vaf45b8(w6)
);
vba518e v7c2c65 (
.v0e28cb(w0),
.vcbab45(w2),
.v3ca442(w7)
);
v468a05 v4dcb81 (
.vc6471a(w1),
.ve841af(w5)
);
v857d2e v415624 (
.vec26ff(w1),
.vccca56(w2),
.v19a59f(w3),
.v6dda25(w4)
);
endmodule
//---------------------------------------------------
//-- Generic-comp-clk
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic component with clk input
//---------------------------------------------------
//---- Top entity
module vf61fa3 (
input [3:0] vaf45b8,
output vcbab45
);
wire w0;
wire [0:3] w1;
wire w2;
wire w3;
wire w4;
wire w5;
assign vcbab45 = w0;
assign w1 = vaf45b8;
vc4f23a v5f4674 (
.v985fcb(w1),
.v4f1fd3(w2),
.vda577d(w3),
.v3f8943(w4),
.v64d863(w5)
);
vf49321 vea932e (
.vcbab45(w0),
.ve86251(w2),
.v0e28cb(w3),
.v3ca442(w4),
.v8b2684(w5)
);
endmodule
//---------------------------------------------------
//-- OR-BUS4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR-BUS4: OR gate with 4-bits bus input
//---------------------------------------------------
//---- Top entity
module vf49321 (
input ve86251,
input v0e28cb,
input v3ca442,
input v8b2684,
output vcbab45
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w0 = ve86251;
assign w1 = v0e28cb;
assign w3 = v3ca442;
assign vcbab45 = w5;
assign w6 = v8b2684;
v873425 v1edc96 (
.v0e28cb(w0),
.v3ca442(w1),
.vcbab45(w2)
);
v873425 v5591ec (
.v0e28cb(w2),
.v3ca442(w3),
.vcbab45(w4)
);
v873425 vdba9a4 (
.v0e28cb(w4),
.vcbab45(w5),
.v3ca442(w6)
);
endmodule
//---------------------------------------------------
//-- OR4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR4: Four bits input OR gate
//---------------------------------------------------
//---- Top entity
module v873425 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
v873425_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- OR2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- OR2: Two bits input OR gate
//---------------------------------------------------
module v873425_vf4938a (
input a,
input b,
output c
);
//-- OR Gate
//-- Verilog implementation
assign c = a | b;
endmodule
//---- Top entity
module v468a05 (
input [31:0] ve841af,
output [7:0] vdd0469,
output [7:0] v4ba85d,
output [7:0] vf93ecb,
output [7:0] vc6471a
);
wire [0:31] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
assign w0 = ve841af;
assign vc6471a = w1;
assign vf93ecb = w2;
assign v4ba85d = w3;
assign vdd0469 = w4;
v468a05_v9a2a06 v9a2a06 (
.i(w0),
.o0(w1),
.o1(w2),
.o2(w3),
.o3(w4)
);
endmodule
//---------------------------------------------------
//-- Bus32-Split-quarter
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Split-quarter: Split the 32-bits bus into four buses of 8 wires
//---------------------------------------------------
module v468a05_v9a2a06 (
input [31:0] i,
output [7:0] o3,
output [7:0] o2,
output [7:0] o1,
output [7:0] o0
);
assign o3 = i[32:24];
assign o2 = i[23:16];
assign o1 = i[15:8];
assign o0 = i[7:0];
endmodule
//---- Top entity
module v857d2e (
input v6dda25,
input [7:0] vec26ff,
input vccca56,
output [7:0] v19a59f
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:3] w2;
wire [0:3] w3;
wire [0:3] w4;
wire [0:3] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = vec26ff;
assign v19a59f = w1;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = vccca56;
assign w9 = vccca56;
assign w7 = w6;
assign w9 = w8;
v6bdcd9 v8e04d7 (
.vcc8c7c(w0),
.v651522(w2),
.v2cc41f(w4)
);
vafb28f vdbcc53 (
.va9ac17(w1),
.v515fe7(w3),
.v3c88fc(w5)
);
v370cd6 v732df5 (
.v2856c0(w2),
.v7891f9(w3),
.v6dda25(w6),
.vccca56(w8)
);
v370cd6 v21c6af (
.v2856c0(w4),
.v7891f9(w5),
.v6dda25(w7),
.vccca56(w9)
);
endmodule
//---------------------------------------------------
//-- Reg-x08
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x08: 8-bits register
//---------------------------------------------------
//---- Top entity
module v6bdcd9 (
input [7:0] vcc8c7c,
output [3:0] v651522,
output [3:0] v2cc41f
);
wire [0:3] w0;
wire [0:3] w1;
wire [0:7] w2;
assign v651522 = w0;
assign v2cc41f = w1;
assign w2 = vcc8c7c;
v6bdcd9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Split-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Split-half: Split the 8-bits bus into two buses of the same size
//---------------------------------------------------
module v6bdcd9_v9a2a06 (
input [7:0] i,
output [3:0] o1,
output [3:0] o0
);
assign o1 = i[7:4];
assign o0 = i[3:0];
endmodule
//---- Top entity
module vafb28f (
input [3:0] v515fe7,
input [3:0] v3c88fc,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:3] w1;
wire [0:3] w2;
assign va9ac17 = w0;
assign w1 = v515fe7;
assign w2 = v3c88fc;
vafb28f_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Join-half
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Join-half: Join the two same halves into an 8-bits Bus
//---------------------------------------------------
module vafb28f_v9a2a06 (
input [3:0] i1,
input [3:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v370cd6 (
input v6dda25,
input [3:0] v2856c0,
input vccca56,
output [3:0] v7891f9
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v2856c0;
assign v7891f9 = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = vccca56;
assign w15 = vccca56;
assign w16 = vccca56;
assign w17 = vccca56;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
v22cb98 v1ba30c (
.v27dec4(w0),
.v4642b6(w2),
.ve4a668(w12),
.vd793aa(w16)
);
v22cb98 v38f79d (
.v27dec4(w1),
.v4642b6(w3),
.ve4a668(w13),
.vd793aa(w17)
);
v22cb98 v009467 (
.v27dec4(w4),
.v4642b6(w5),
.ve4a668(w11),
.vd793aa(w15)
);
vc4f23a vf2e2c0 (
.v3f8943(w0),
.v64d863(w1),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v947047 (
.vee8a83(w2),
.v03aaf0(w3),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v22cb98 v3a0f4c (
.v27dec4(w8),
.v4642b6(w9),
.ve4a668(w10),
.vd793aa(w14)
);
endmodule
//---------------------------------------------------
//-- Reg-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg-x04: 4-bits register
//---------------------------------------------------
//---- Top entity
module v22cb98 #(
parameter v5462c0 = 0
) (
input ve4a668,
input v27dec4,
input vd793aa,
output v4642b6
);
localparam p1 = v5462c0;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign w2 = ve4a668;
assign w3 = v27dec4;
assign v4642b6 = w5;
assign w6 = vd793aa;
assign w5 = w4;
va40d2f v9ff767 (
.v030ad0(w0),
.vb192d0(w3),
.v27dec4(w4),
.v2d3366(w6)
);
v053dc2 #(
.v71e305(p1)
) v89c757 (
.vf54559(w0),
.va4102a(w2),
.ve8318d(w4)
);
endmodule
//---------------------------------------------------
//-- 1-bit-reg
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Reg: 1-Bit register
//---------------------------------------------------
//---- Top entity
module va40d2f (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
assign v030ad0 = w0;
assign w1 = v2d3366;
assign w2 = v27dec4;
assign w3 = vb192d0;
vd0c4e5 v0f3fef (
.v030ad0(w0),
.v2d3366(w1),
.vb192d0(w2),
.v27dec4(w3)
);
endmodule
//---------------------------------------------------
//-- MuxF-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels). Fippled version
//---------------------------------------------------
//---- Top entity
module vd0c4e5 (
input v27dec4,
input vb192d0,
input v2d3366,
output v030ad0
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
assign v030ad0 = w0;
assign w2 = v2d3366;
assign w3 = v2d3366;
assign w6 = v27dec4;
assign w7 = vb192d0;
assign w3 = w2;
v873425 vaaee1f (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w4)
);
vba518e v569873 (
.vcbab45(w1),
.v3ca442(w2),
.v0e28cb(w6)
);
v3676a0 v1f00ae (
.v0e28cb(w3),
.vcbab45(w5)
);
vba518e vc8527f (
.vcbab45(w4),
.v3ca442(w5),
.v0e28cb(w7)
);
endmodule
//---------------------------------------------------
//-- Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (1-bit channels)
//---------------------------------------------------
//---- Top entity
module v053dc2 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v053dc2_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule
//---------------------------------------------------
//-- DFF
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- D Flip-flop (verilog implementation)
//---------------------------------------------------
module v053dc2_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule
//---- Top entity
module v84f0a1 (
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [3:0] v11bca5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire [0:3] w4;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign w2 = vf8041d;
assign w3 = vd84a57;
assign v11bca5 = w4;
v84f0a1_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.i2(w2),
.i3(w3),
.o(w4)
);
endmodule
//---------------------------------------------------
//-- Bus4-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus4-Join-all: Join all the wires into a 4-bits Bus
//---------------------------------------------------
module v84f0a1_v9a2a06 (
input i3,
input i2,
input i1,
input i0,
output [3:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module v145d1e (
input [31:0] vb79ed5,
input [7:0] vc74a9c,
input v6287a6,
input v19f646,
output [31:0] vb76294
);
wire [0:31] w0;
wire [0:31] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
wire [0:31] w5;
wire [0:31] w6;
wire [0:31] w7;
wire [0:7] w8;
wire w9;
wire w10;
assign w6 = vb79ed5;
assign vb76294 = w7;
assign w8 = vc74a9c;
assign w9 = v6287a6;
assign w10 = v19f646;
assign w3 = w2;
assign w4 = w2;
assign w4 = w3;
v15006c v7f618a (
.v3d79e8(w0),
.v53354a(w6),
.vd99bd0(w7),
.v2d3366(w9)
);
v15006c vf576d8 (
.vd99bd0(w0),
.v53354a(w1),
.v3d79e8(w5),
.v2d3366(w10)
);
v78e0a3 v9e8b5c (
.v7d0a31(w1),
.v6127ee(w2),
.v12d067(w3),
.vea9d11(w4),
.v29bdec(w8)
);
vda0861 vfb1ecd (
.vffb58f(w2)
);
v2c97f6 v1dbb84 (
.v7c9bd8(w5)
);
endmodule
//---------------------------------------------------
//-- Generic-comp
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Componente genérico
//---------------------------------------------------
//---- Top entity
module v15006c (
input [31:0] v53354a,
input [31:0] v3d79e8,
input v2d3366,
output [31:0] vd99bd0
);
wire [0:7] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:31] w3;
wire [0:31] w4;
wire [0:31] w5;
wire [0:7] w6;
wire [0:7] w7;
wire [0:7] w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire [0:7] w13;
wire [0:7] w14;
wire [0:7] w15;
wire [0:7] w16;
wire [0:7] w17;
wire [0:7] w18;
assign vd99bd0 = w3;
assign w4 = v3d79e8;
assign w5 = v53354a;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
v1bbb5b v41cfb0 (
.v9d2a6a(w0),
.v2d3366(w12),
.v2a1cbe(w17),
.v9d7ae8(w18)
);
v1bbb5b vf7893e (
.v9d2a6a(w1),
.v2d3366(w11),
.v2a1cbe(w15),
.v9d7ae8(w16)
);
v1bbb5b v40a6d4 (
.v9d2a6a(w2),
.v2d3366(w10),
.v2a1cbe(w13),
.v9d7ae8(w14)
);
v78e0a3 v2e8dfc (
.v29bdec(w0),
.vea9d11(w1),
.v6127ee(w2),
.v7d0a31(w3),
.v12d067(w6)
);
v468a05 v95e147 (
.ve841af(w5),
.vdd0469(w7),
.v4ba85d(w13),
.vf93ecb(w15),
.vc6471a(w17)
);
v468a05 v44f594 (
.ve841af(w4),
.vdd0469(w8),
.v4ba85d(w14),
.vf93ecb(w16),
.vc6471a(w18)
);
v1bbb5b v68fd67 (
.v9d2a6a(w6),
.v2a1cbe(w7),
.v9d7ae8(w8),
.v2d3366(w9)
);
endmodule
//---------------------------------------------------
//-- 32-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (32-bit channels)
//---------------------------------------------------
//---- Top entity
module v1bbb5b (
input [7:0] v2a1cbe,
input [7:0] v9d7ae8,
input v2d3366,
output [7:0] v9d2a6a
);
wire [0:3] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:3] w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire [0:3] w10;
assign v9d2a6a = w1;
assign w2 = v2a1cbe;
assign w3 = v9d7ae8;
assign w8 = v2d3366;
assign w9 = v2d3366;
assign w9 = w8;
v952eda v54aed2 (
.v6833fd(w0),
.v54ac99(w7),
.v2d3366(w9),
.ve2616d(w10)
);
vafb28f v117a88 (
.v3c88fc(w0),
.va9ac17(w1),
.v515fe7(w4)
);
v6bdcd9 v9f32ae (
.vcc8c7c(w2),
.v651522(w5),
.v2cc41f(w7)
);
v6bdcd9 v9881c7 (
.vcc8c7c(w3),
.v651522(w6),
.v2cc41f(w10)
);
v952eda v34a43a (
.v6833fd(w4),
.v54ac99(w5),
.ve2616d(w6),
.v2d3366(w8)
);
endmodule
//---------------------------------------------------
//-- 8-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (8-bit channels)
//---------------------------------------------------
//---- Top entity
module v952eda (
input [3:0] v54ac99,
input [3:0] ve2616d,
input v2d3366,
output [3:0] v6833fd
);
wire w0;
wire w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign v6833fd = w3;
assign w5 = ve2616d;
assign w6 = v54ac99;
assign w9 = v2d3366;
assign w10 = v2d3366;
assign w11 = v2d3366;
assign w12 = v2d3366;
assign w10 = w9;
assign w11 = w9;
assign w11 = w10;
assign w12 = w9;
assign w12 = w10;
assign w12 = w11;
vd0c4e5 v6d94c9 (
.v030ad0(w0),
.v2d3366(w11),
.v27dec4(w15),
.vb192d0(w17)
);
vd0c4e5 vebe465 (
.v030ad0(w1),
.v2d3366(w12),
.v27dec4(w16),
.vb192d0(w18)
);
vd0c4e5 ve1c21f (
.v030ad0(w2),
.v2d3366(w10),
.v27dec4(w13),
.vb192d0(w14)
);
v84f0a1 va44bdf (
.vee8a83(w0),
.v03aaf0(w1),
.vf8041d(w2),
.v11bca5(w3),
.vd84a57(w4)
);
vd0c4e5 v2ebff3 (
.v030ad0(w4),
.v27dec4(w7),
.vb192d0(w8),
.v2d3366(w9)
);
vc4f23a v3c3a57 (
.v985fcb(w5),
.v4f1fd3(w8),
.vda577d(w14),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a vd6d480 (
.v985fcb(w6),
.v4f1fd3(w7),
.vda577d(w13),
.v3f8943(w15),
.v64d863(w16)
);
endmodule
//---------------------------------------------------
//-- 4-bits-Mux-2-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 2-to-1 Multplexer (4-bit channels)
//---------------------------------------------------
//---- Top entity
module v78e0a3 (
input [7:0] v12d067,
input [7:0] v6127ee,
input [7:0] vea9d11,
input [7:0] v29bdec,
output [31:0] v7d0a31
);
wire [0:31] w0;
wire [0:7] w1;
wire [0:7] w2;
wire [0:7] w3;
wire [0:7] w4;
assign v7d0a31 = w0;
assign w1 = v29bdec;
assign w2 = vea9d11;
assign w3 = v6127ee;
assign w4 = v12d067;
v78e0a3_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2),
.i2(w3),
.i3(w4)
);
endmodule
//---------------------------------------------------
//-- Bus32-Join-quarter
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus32-Join-quarter: Join the four buses into an 32-bits Bus
//---------------------------------------------------
module v78e0a3_v9a2a06 (
input [7:0] i3,
input [7:0] i2,
input [7:0] i1,
input [7:0] i0,
output [31:0] o
);
assign o = {i3, i2, i1, i0};
endmodule
//---- Top entity
module vda0861 #(
parameter vfffc23 = 0
) (
output [7:0] vffb58f
);
localparam p0 = vfffc23;
wire [0:7] w1;
assign vffb58f = w1;
vffc517 #(
.vc5c8ea(p0)
) v778577 (
.va0aeac(w1)
);
endmodule
//---------------------------------------------------
//-- 8bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 8bits constant value: 0
//---------------------------------------------------
//---- Top entity
module vffc517 #(
parameter vc5c8ea = 0
) (
output [7:0] va0aeac
);
localparam p0 = vc5c8ea;
wire [0:7] w1;
assign va0aeac = w1;
vffc517_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 8-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 8-bits generic constant (0-255)
//---------------------------------------------------
module vffc517_v465065 #(
parameter VALUE = 0
) (
output [7:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v04e061 #(
parameter v001ed5 = 1
) (
input vd6bebe,
output v4642b6,
output [4:0] vb385cd,
output vd9f5b6
);
localparam p1 = v001ed5;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:4] w8;
wire w9;
wire w10;
wire w11;
wire [0:4] w12;
assign v4642b6 = w2;
assign vd9f5b6 = w6;
assign vb385cd = w8;
assign w9 = vd6bebe;
assign w10 = vd6bebe;
assign w4 = w2;
assign w5 = w3;
assign w10 = w9;
assign w11 = w2;
assign w11 = w4;
v144728 #(
.v573b2a(p1)
) v04fe70 (
.v27dec4(w0),
.v4642b6(w2),
.v92a149(w3),
.v6dda25(w9)
);
vd30ca9 v8af589 (
.v9fb85f(w0)
);
vba518e ve66489 (
.v0e28cb(w5),
.vcbab45(w6),
.v3ca442(w11)
);
vaf1249 ve31e7c (
.ve37344(w3),
.ve556f1(w7),
.v6dda25(w10),
.va1c800(w12)
);
vd30ca9 va31481 (
.v9fb85f(w7)
);
v51353d vabd391 (
.v427380(w4),
.v81cd93(w8),
.v083523(w12)
);
endmodule
//---------------------------------------------------
//-- start-5-bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- start-5-bit: 32 cycles width pulse
//---------------------------------------------------
//---- Top entity
module v144728 #(
parameter v573b2a = 0
) (
input v6dda25,
input v27dec4,
input v92a149,
output v4642b6
);
localparam p0 = v573b2a;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w5 = v6dda25;
assign v4642b6 = w6;
assign w8 = v27dec4;
assign w9 = v92a149;
assign w7 = w6;
v053dc2 #(
.v71e305(p0)
) v24b497 (
.vf54559(w1),
.va4102a(w5),
.ve8318d(w6)
);
vd0c4e5 vda4b54 (
.v030ad0(w1),
.v27dec4(w2),
.vb192d0(w3),
.v2d3366(w8)
);
vfebcfe v2141a0 (
.v9fb85f(w2)
);
vd0c4e5 v75d8ff (
.v030ad0(w3),
.v27dec4(w4),
.vb192d0(w7),
.v2d3366(w9)
);
vd30ca9 va595cf (
.v9fb85f(w4)
);
endmodule
//---------------------------------------------------
//-- RS-FF-set
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- RS-FF-set. RS Flip-flop with priority set
//---------------------------------------------------
//---- Top entity
module vfebcfe (
output v9fb85f
);
wire w0;
assign v9fb85f = w0;
vfebcfe_vb2eccd vb2eccd (
.q(w0)
);
endmodule
//---------------------------------------------------
//-- bit-1
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Constant bit 1
//---------------------------------------------------
module vfebcfe_vb2eccd (
output q
);
//-- Constant bit-1
assign q = 1'b1;
endmodule
//---- Top entity
module vaf1249 (
input v6dda25,
input ve556f1,
output [4:0] va1c800,
output ve37344
);
wire w0;
wire [0:4] w1;
wire [0:4] w2;
wire w3;
wire [0:4] w4;
wire w5;
assign w0 = ve556f1;
assign w3 = v6dda25;
assign va1c800 = w4;
assign ve37344 = w5;
assign w4 = w1;
v6ed669 vad9b51 (
.v782748(w0),
.vcc30ea(w1),
.v35dd11(w2),
.v6dda25(w3)
);
vd0bb30 v1e9706 (
.vd03823(w1),
.vb4c454(w2),
.v4642b6(w5)
);
endmodule
//---------------------------------------------------
//-- syscounter-rst-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 5-bits Syscounter with reset
//---------------------------------------------------
//---- Top entity
module v6ed669 (
input v6dda25,
input v782748,
input [4:0] v35dd11,
output [4:0] vcc30ea
);
wire [0:4] w0;
wire [0:3] w1;
wire w2;
wire [0:3] w3;
wire w4;
wire [0:4] w5;
wire w6;
wire w7;
wire w8;
wire w9;
assign w0 = v35dd11;
assign vcc30ea = w5;
assign w6 = v6dda25;
assign w7 = v6dda25;
assign w8 = v782748;
assign w9 = v782748;
assign w7 = w6;
assign w9 = w8;
v2be0f8 v8aa818 (
.vf354ee(w2),
.v4642b6(w4),
.vd53b77(w6),
.v27dec4(w8)
);
v5c75f6 vbdef88 (
.v4de61b(w1),
.v50034e(w3),
.v6dda25(w7),
.v782748(w9)
);
v91f34c v122992 (
.v427dd1(w0),
.v479af4(w1),
.v53baa6(w2)
);
vcdce79 v93fefd (
.v167ed7(w3),
.vee8a83(w4),
.v6a2e9e(w5)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x05
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x05: Five D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module v2be0f8 #(
parameter vbd3217 = 0
) (
input vd53b77,
input v27dec4,
input vf354ee,
output v4642b6
);
localparam p5 = vbd3217;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w6;
assign w2 = v27dec4;
assign w3 = vf354ee;
assign v4642b6 = w4;
assign w6 = vd53b77;
v3676a0 v7539bf (
.vcbab45(w1),
.v0e28cb(w2)
);
vba518e vfe8158 (
.vcbab45(w0),
.v0e28cb(w1),
.v3ca442(w3)
);
v053dc2 #(
.v71e305(p5)
) vd104a4 (
.vf54559(w0),
.ve8318d(w4),
.va4102a(w6)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0
//---------------------------------------------------
//---- Top entity
module v5c75f6 (
input v6dda25,
input v782748,
input [3:0] v4de61b,
output [3:0] v50034e
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
assign w6 = v4de61b;
assign v50034e = w7;
assign w10 = v6dda25;
assign w11 = v6dda25;
assign w12 = v6dda25;
assign w13 = v6dda25;
assign w14 = v782748;
assign w15 = v782748;
assign w16 = v782748;
assign w17 = v782748;
assign w11 = w10;
assign w12 = w10;
assign w12 = w11;
assign w13 = w10;
assign w13 = w11;
assign w13 = w12;
assign w15 = w14;
assign w16 = w14;
assign w16 = w15;
assign w17 = w14;
assign w17 = w15;
assign w17 = w16;
vc4f23a v4b1225 (
.v3f8943(w2),
.v64d863(w3),
.vda577d(w4),
.v985fcb(w6),
.v4f1fd3(w8)
);
v84f0a1 v6491fd (
.v03aaf0(w0),
.vee8a83(w1),
.vf8041d(w5),
.v11bca5(w7),
.vd84a57(w9)
);
v2be0f8 v10a04f (
.v4642b6(w0),
.vf354ee(w3),
.vd53b77(w13),
.v27dec4(w17)
);
v2be0f8 v7d9648 (
.v4642b6(w1),
.vf354ee(w2),
.vd53b77(w12),
.v27dec4(w16)
);
v2be0f8 v004b14 (
.vf354ee(w4),
.v4642b6(w5),
.vd53b77(w11),
.v27dec4(w15)
);
v2be0f8 v8aa818 (
.vf354ee(w8),
.v4642b6(w9),
.vd53b77(w10),
.v27dec4(w14)
);
endmodule
//---------------------------------------------------
//-- DFF-rst-x04
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- DFF-rst-x04: Three D flip-flops in paralell with reset
//---------------------------------------------------
//---- Top entity
module vcdce79 (
input vee8a83,
input [3:0] v167ed7,
output [4:0] v6a2e9e
);
wire [0:4] w0;
wire w1;
wire [0:3] w2;
assign v6a2e9e = w0;
assign w1 = vee8a83;
assign w2 = v167ed7;
vcdce79_v9a2a06 v9a2a06 (
.o(w0),
.i1(w1),
.i0(w2)
);
endmodule
//---------------------------------------------------
//-- Bus5-Join-1-4
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus5-Join-1-4: Join the two buses of 1 and 4 bits into a 5-bits Bus
//---------------------------------------------------
module vcdce79_v9a2a06 (
input i1,
input [3:0] i0,
output [4:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module vd0bb30 #(
parameter v6c5139 = 1
) (
input [4:0] vd03823,
output v4642b6,
output [4:0] vb4c454
);
localparam p1 = v6c5139;
wire w0;
wire [0:4] w2;
wire [0:4] w3;
assign v4642b6 = w0;
assign w2 = vd03823;
assign vb4c454 = w3;
va17f79 #(
.vd73390(p1)
) vc288d0 (
.v4642b6(w0),
.va6f14e(w2),
.v919f01(w3)
);
endmodule
//---------------------------------------------------
//-- Inc1-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Inc1-5bit: Increment a 5-bits number by one
//---------------------------------------------------
//---- Top entity
module va17f79 #(
parameter vd73390 = 0
) (
input [4:0] va6f14e,
output v4642b6,
output [4:0] v919f01
);
localparam p1 = vd73390;
wire w0;
wire [0:4] w2;
wire [0:4] w3;
wire [0:4] w4;
assign v4642b6 = w0;
assign w3 = va6f14e;
assign v919f01 = w4;
v0cfc7a v530cb5 (
.v4642b6(w0),
.v225d34(w2),
.vbb6b94(w3),
.vae8b91(w4)
);
v3693fc #(
.vc5c8ea(p1)
) v809c3c (
.vc8d3b9(w2)
);
endmodule
//---------------------------------------------------
//-- AdderK-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderK-5bit: Adder of 5-bit operand and 5-bit constant
//---------------------------------------------------
//---- Top entity
module v0cfc7a (
input [4:0] v225d34,
input [4:0] vbb6b94,
output v4642b6,
output [4:0] vae8b91
);
wire w0;
wire w1;
wire [0:4] w2;
wire [0:4] w3;
wire [0:4] w4;
wire w5;
wire [0:3] w6;
wire w7;
wire [0:3] w8;
wire w9;
wire [0:3] w10;
assign w2 = vbb6b94;
assign w3 = v225d34;
assign vae8b91 = w4;
assign v4642b6 = w5;
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w5),
.v27dec4(w7),
.v82de4f(w9)
);
v91f34c v144430 (
.v427dd1(w2),
.v53baa6(w9),
.v479af4(w10)
);
v91f34c v09d2c7 (
.v427dd1(w3),
.v53baa6(w7),
.v479af4(w8)
);
v25966b vd35762 (
.v4642b6(w0),
.v817794(w6),
.v0550b6(w8),
.v24708e(w10)
);
vcdce79 v758283 (
.vee8a83(w1),
.v6a2e9e(w4),
.v167ed7(w6)
);
endmodule
//---------------------------------------------------
//-- Adder-5bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-5bits: Adder of two operands of 5 bits
//---------------------------------------------------
//---- Top entity
module vad119b (
input v27dec4,
input v82de4f,
input v0ef266,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
wire w9;
wire w10;
wire w11;
assign v8e8a67 = w1;
assign v4642b6 = w5;
assign w6 = v27dec4;
assign w7 = v27dec4;
assign w8 = v82de4f;
assign w9 = v82de4f;
assign w10 = v0ef266;
assign w11 = v0ef266;
assign w2 = w0;
assign w7 = w6;
assign w9 = w8;
assign w11 = w10;
vd12401 v2e3d9f (
.vcbab45(w0),
.v0e28cb(w7),
.v3ca442(w9)
);
vd12401 vb50462 (
.v0e28cb(w0),
.vcbab45(w1),
.v3ca442(w11)
);
vba518e v4882f4 (
.v3ca442(w2),
.vcbab45(w3),
.v0e28cb(w10)
);
vba518e v8fcf41 (
.vcbab45(w4),
.v0e28cb(w6),
.v3ca442(w8)
);
v873425 vc5b8b9 (
.v3ca442(w3),
.v0e28cb(w4),
.vcbab45(w5)
);
endmodule
//---------------------------------------------------
//-- AdderC-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AdderC-1bit: Adder of two operands of 1 bit plus the carry in
//---------------------------------------------------
//---- Top entity
module v25966b (
input [3:0] v0550b6,
input [3:0] v24708e,
output v4642b6,
output [3:0] v817794
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:3] w5;
wire [0:3] w6;
wire [0:3] w7;
wire w8;
wire w9;
wire w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
wire w17;
wire w18;
assign w5 = v24708e;
assign w6 = v0550b6;
assign v817794 = w7;
assign v4642b6 = w9;
v1ea21d vdbe125 (
.v4642b6(w0),
.v8e8a67(w2),
.v27dec4(w15),
.v82de4f(w18)
);
vad119b vb8ad86 (
.v0ef266(w0),
.v8e8a67(w1),
.v4642b6(w3),
.v27dec4(w14),
.v82de4f(w17)
);
vad119b v5d29b2 (
.v0ef266(w3),
.v8e8a67(w4),
.v4642b6(w8),
.v27dec4(w12),
.v82de4f(w16)
);
vc4f23a vf4a6ff (
.v985fcb(w5),
.v4f1fd3(w13),
.vda577d(w16),
.v3f8943(w17),
.v64d863(w18)
);
vc4f23a v9d4632 (
.v985fcb(w6),
.v4f1fd3(w11),
.vda577d(w12),
.v3f8943(w14),
.v64d863(w15)
);
v84f0a1 v140dbf (
.vee8a83(w1),
.v03aaf0(w2),
.vf8041d(w4),
.v11bca5(w7),
.vd84a57(w10)
);
vad119b v5c5937 (
.v0ef266(w8),
.v4642b6(w9),
.v8e8a67(w10),
.v27dec4(w11),
.v82de4f(w13)
);
endmodule
//---------------------------------------------------
//-- Adder-4bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-4bits: Adder of two operands of 4 bits
//---------------------------------------------------
//---- Top entity
module v1ea21d (
input v27dec4,
input v82de4f,
output v4642b6,
output v8e8a67
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = v82de4f;
assign w1 = v27dec4;
assign v4642b6 = w3;
assign v8e8a67 = w4;
vad119b vb820a1 (
.v82de4f(w0),
.v27dec4(w1),
.v0ef266(w2),
.v4642b6(w3),
.v8e8a67(w4)
);
vd30ca9 v23ebb6 (
.v9fb85f(w2)
);
endmodule
//---------------------------------------------------
//-- Adder-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Adder-1bit: Adder of two operands of 1 bit
//---------------------------------------------------
//---- Top entity
module v51353d (
input [4:0] v083523,
input v427380,
output [4:0] v81cd93
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire [0:4] w8;
wire w9;
wire [0:4] w10;
wire w11;
wire w12;
wire w13;
wire w14;
wire w15;
wire w16;
assign w1 = v427380;
assign w2 = v427380;
assign w6 = v427380;
assign w8 = v083523;
assign v81cd93 = w10;
assign w13 = v427380;
assign w14 = v427380;
assign w2 = w1;
assign w6 = w1;
assign w6 = w2;
assign w13 = w1;
assign w13 = w2;
assign w13 = w6;
assign w14 = w1;
assign w14 = w2;
assign w14 = w6;
assign w14 = w13;
vba518e v984c00 (
.v0e28cb(w0),
.v3ca442(w2),
.vcbab45(w3)
);
vba518e v63c547 (
.v3ca442(w1),
.vcbab45(w4),
.v0e28cb(w9)
);
vba518e v017827 (
.v0e28cb(w5),
.v3ca442(w6),
.vcbab45(w7)
);
v60f5a9 v3aadcd (
.v3f8943(w0),
.vda577d(w5),
.v427dd1(w8),
.v64d863(w9),
.v53baa6(w11),
.v4f1fd3(w12)
);
v36cddd v6e87bf (
.vee8a83(w3),
.v03aaf0(w4),
.vf8041d(w7),
.v6a2e9e(w10),
.vd84a57(w15),
.v684b0d(w16)
);
vba518e vd994d2 (
.v0e28cb(w12),
.v3ca442(w13),
.vcbab45(w15)
);
vba518e v0bd924 (
.v0e28cb(w11),
.v3ca442(w14),
.vcbab45(w16)
);
endmodule
//---------------------------------------------------
//-- AND-Busen-5
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- AND-Busen-5: Enable a 5-bits bus. When the enable signal is 0, the output is 0
//---------------------------------------------------
//---- Top entity
module v60f5a9 (
input [4:0] v427dd1,
output v53baa6,
output v4f1fd3,
output vda577d,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire [0:4] w5;
assign v3f8943 = w0;
assign v64d863 = w1;
assign vda577d = w2;
assign v4f1fd3 = w3;
assign v53baa6 = w4;
assign w5 = v427dd1;
v60f5a9_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.o2(w2),
.o3(w3),
.o4(w4),
.i(w5)
);
endmodule
//---------------------------------------------------
//-- Bus5-Split-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus5-Split-all: Split the 5-bits bus into its wires
//---------------------------------------------------
module v60f5a9_v9a2a06 (
input [4:0] i,
output o4,
output o3,
output o2,
output o1,
output o0
);
assign o4 = i[4];
assign o3 = i[3];
assign o2 = i[2];
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module v36cddd (
input v684b0d,
input vd84a57,
input vf8041d,
input vee8a83,
input v03aaf0,
output [4:0] v6a2e9e
);
wire w0;
wire w1;
wire [0:4] w2;
wire w3;
wire w4;
wire w5;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign v6a2e9e = w2;
assign w3 = vf8041d;
assign w4 = vd84a57;
assign w5 = v684b0d;
v36cddd_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.o(w2),
.i2(w3),
.i3(w4),
.i4(w5)
);
endmodule
//---------------------------------------------------
//-- Bus5-Join-all
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus5-Join-all: Join all the wires into a 5-bits Bus
//---------------------------------------------------
module v36cddd_v9a2a06 (
input i4,
input i3,
input i2,
input i1,
input i0,
output [4:0] o
);
assign o = {i4, i3, i2, i1, i0};
endmodule
//---- Top entity
module v8efab2 (
input [1:0] v0c06c3,
output [7:0] v20cbde
);
wire [0:7] w0;
wire [0:1] w1;
wire [0:5] w2;
assign v20cbde = w0;
assign w1 = v0c06c3;
v2ae6c6 vab1711 (
.va9ac17(w0),
.v05ee31(w1),
.v164ff1(w2)
);
v54ad57 va8e954 (
.ve45beb(w2)
);
endmodule
//---------------------------------------------------
//-- UINT8-2bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- UINT8-2bits: Extend a 2-bits unsigned integer to 8-bits
//---------------------------------------------------
//---- Top entity
module v2ae6c6 (
input [5:0] v164ff1,
input [1:0] v05ee31,
output [7:0] va9ac17
);
wire [0:7] w0;
wire [0:1] w1;
wire [0:5] w2;
assign va9ac17 = w0;
assign w1 = v05ee31;
assign w2 = v164ff1;
v2ae6c6_v9a2a06 v9a2a06 (
.o(w0),
.i0(w1),
.i1(w2)
);
endmodule
//---------------------------------------------------
//-- Bus8-Join-6-2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Bus8-Join-6-2: Join the two buses into an 8-bits Bus
//---------------------------------------------------
module v2ae6c6_v9a2a06 (
input [5:0] i1,
input [1:0] i0,
output [7:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module v54ad57 #(
parameter vfffc23 = 0
) (
output [5:0] ve45beb
);
localparam p0 = vfffc23;
wire [0:5] w1;
assign ve45beb = w1;
va5ad63 #(
.vc5c8ea(p0)
) ve95ea8 (
.vbbba94(w1)
);
endmodule
//---------------------------------------------------
//-- 6bits-Value_0
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 6bits constant value: 0
//---------------------------------------------------
//---- Top entity
module va5ad63 #(
parameter vc5c8ea = 0
) (
output [5:0] vbbba94
);
localparam p0 = vc5c8ea;
wire [0:5] w1;
assign vbbba94 = w1;
va5ad63_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- 6-bits-gen-constant
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Generic: 6-bits generic constant (0-63)
//---------------------------------------------------
module va5ad63_v465065 #(
parameter VALUE = 0
) (
output [5:0] k
);
assign k = VALUE;
endmodule
//---- Top entity
module v7caf1c #(
parameter v17ea21 = 0,
parameter v803182 = 0
) (
input v25ab12,
input [1:0] vcc8287,
output [1:0] ved9bf3
);
localparam p6 = v17ea21;
localparam p7 = v803182;
localparam p8 = v803182;
localparam p9 = v17ea21;
wire [0:1] w0;
wire [0:1] w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w10;
wire w11;
assign w0 = vcc8287;
assign ved9bf3 = w1;
assign w10 = v25ab12;
assign w11 = v25ab12;
assign w11 = w10;
vfc9dac v5d6804 (
.v8b19dd(w0),
.v3f8943(w2),
.v64d863(w3)
);
vd4bd04 v8e7ca4 (
.v67a3fc(w1),
.v03aaf0(w4),
.vee8a83(w5)
);
vda434a #(
.v17ea21(p6),
.v803182(p8)
) v693378 (
.v27dec4(w2),
.v4642b6(w5),
.v25ab12(w10)
);
vda434a #(
.v803182(p7),
.v17ea21(p9)
) v6de0cd (
.v27dec4(w3),
.v4642b6(w4),
.v25ab12(w11)
);
endmodule
//---------------------------------------------------
//-- Buttonx2
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Configurable buttons (pull-up on/off. Not on/off)
//---------------------------------------------------
//---- Top entity
module vfc9dac (
input [1:0] v8b19dd,
output v3f8943,
output v64d863
);
wire w0;
wire w1;
wire [0:1] w2;
assign v3f8943 = w0;
assign v64d863 = w1;
assign w2 = v8b19dd;
vfc9dac_v9a2a06 v9a2a06 (
.o1(w0),
.o0(w1),
.i(w2)
);
endmodule
//---------------------------------------------------
//-- Separador-bus
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Separador de bus de 2-bits en dos cables
//---------------------------------------------------
module vfc9dac_v9a2a06 (
input [1:0] i,
output o1,
output o0
);
assign o1 = i[1];
assign o0 = i[0];
endmodule
//---- Top entity
module vd4bd04 (
input vee8a83,
input v03aaf0,
output [1:0] v67a3fc
);
wire w0;
wire w1;
wire [0:1] w2;
assign w0 = vee8a83;
assign w1 = v03aaf0;
assign v67a3fc = w2;
vd4bd04_v9a2a06 v9a2a06 (
.i1(w0),
.i0(w1),
.o(w2)
);
endmodule
//---------------------------------------------------
//-- Agregador-bus
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Agregador de 2 cables en un bus de 2-bits
//---------------------------------------------------
module vd4bd04_v9a2a06 (
input i1,
input i0,
output [1:0] o
);
assign o = {i1, i0};
endmodule
//---- Top entity
module vda434a #(
parameter v17ea21 = 0,
parameter v803182 = 0
) (
input v25ab12,
input v27dec4,
output v4642b6
);
localparam p1 = v803182;
wire w0;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
assign v4642b6 = w3;
assign w4 = v27dec4;
assign w5 = v25ab12;
assign w6 = v25ab12;
assign w6 = w5;
v76118c ve103e3 (
.v3c12b5(w0),
.ve7f5e6(w4),
.v717e81(w5)
);
v5645be #(
.v6a9fe4(p1)
) v4106a0 (
.v27dec4(w0),
.v4642b6(w2)
);
ve77f7c v451422 (
.v6a82dd(w2),
.vd4e5d7(w3),
.v444878(w6)
);
endmodule
//---------------------------------------------------
//-- Button
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Configurable button (pull-up on/off. Not on/off)
//---------------------------------------------------
//---- Top entity
module v76118c (
input v717e81,
input ve7f5e6,
output v3c12b5
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = ve7f5e6;
assign v3c12b5 = w2;
assign w3 = v717e81;
assign w4 = v717e81;
assign w4 = w3;
vc8cfba v7b82fa (
.vf54559(w0),
.ve8318d(w1),
.va4102a(w4)
);
vc8cfba va9ea2a (
.vf54559(w1),
.ve8318d(w2),
.va4102a(w3)
);
endmodule
//---------------------------------------------------
//-- Sync-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Sync 1-bit input with the system clock domain
//---------------------------------------------------
//---- Top entity
module vc8cfba #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
vc8cfba_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule
//---------------------------------------------------
//-- DFF
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- D Flip-flop (verilog implementation)
//---------------------------------------------------
module vc8cfba_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
//-- Initial value
reg q = INI;
//-- Capture the input data
//-- on the rising edge of
//-- the system clock
always @(posedge clk)
q <= d;
endmodule
//---- Top entity
module v5645be #(
parameter v6a9fe4 = 0
) (
input v27dec4,
output v4642b6
);
localparam p0 = v6a9fe4;
wire w1;
wire w2;
wire w3;
assign w2 = v27dec4;
assign v4642b6 = w3;
v3ba5d0 #(
.vc5c8ea(p0)
) vce5802 (
.v268bfc(w1)
);
vb70dd9 vacb84d (
.v0e28cb(w1),
.v3ca442(w2),
.vcbab45(w3)
);
endmodule
//---------------------------------------------------
//-- not-wire-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Select positive or negative logic for the input (0=positive, 1=negative)
//---------------------------------------------------
//---- Top entity
module v3ba5d0 #(
parameter vc5c8ea = 0
) (
output v268bfc
);
localparam p0 = vc5c8ea;
wire w1;
assign v268bfc = w1;
v3ba5d0_v465065 #(
.VALUE(p0)
) v465065 (
.k(w1)
);
endmodule
//---------------------------------------------------
//-- Constante-1bits
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Valor genérico constante, de 1 bits. Su valor se introduce como parámetro. Por defecto vale 0
//---------------------------------------------------
module v3ba5d0_v465065 #(
parameter VALUE = 0
) (
output k
);
assign k = VALUE;
endmodule
//---- Top entity
module vb70dd9 (
input v0e28cb,
input v3ca442,
output vcbab45
);
wire w0;
wire w1;
wire w2;
assign w0 = v0e28cb;
assign w1 = v3ca442;
assign vcbab45 = w2;
vb70dd9_vf4938a vf4938a (
.a(w0),
.b(w1),
.c(w2)
);
endmodule
//---------------------------------------------------
//-- XOR
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Puerta XOR
//---------------------------------------------------
module vb70dd9_vf4938a (
input a,
input b,
output c
);
//-- Puerta XOR
//-- module xor (input wire a, input wire b,
//-- output wire c);
assign c = a ^ b;
//-- endmodule
endmodule
//---- Top entity
module ve77f7c (
input v444878,
input v6a82dd,
output vd4e5d7
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
wire w5;
wire w6;
wire w7;
wire w8;
assign w3 = v444878;
assign w4 = v444878;
assign w5 = v444878;
assign vd4e5d7 = w6;
assign w7 = v6a82dd;
assign w8 = v6a82dd;
assign w4 = w3;
assign w5 = w3;
assign w5 = w4;
assign w8 = w7;
v93adf6 ve5d8ab (
.v9afc1f(w0),
.va4102a(w3),
.ve8318d(w6),
.vf54559(w7)
);
v8d4ef5 v25f434 (
.v712cd1(w0),
.v7c533e(w1),
.ve61673(w2),
.vdd729a(w4)
);
vbd4c1c v584300 (
.v3487af(w2),
.ved8395(w5),
.ve78ab8(w8)
);
vfebcfe vfd2d50 (
.v9fb85f(w1)
);
endmodule
//---------------------------------------------------
//-- Debouncer-x01
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Remove the rebound on a mechanical switch
//---------------------------------------------------
//---- Top entity
module v93adf6 #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
input v9afc1f,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
wire w4;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
assign w4 = v9afc1f;
v93adf6_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3),
.load(w4)
);
endmodule
//---------------------------------------------------
//-- Reg-1bit
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- 1bit register (implemented in verilog)
//---------------------------------------------------
module v93adf6_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
input load,
output q
);
reg q = INI;
always @(posedge clk)
if (load)
q <= d;
endmodule
//---- Top entity
module v8d4ef5 #(
parameter v5e4a03 = 'h10000
) (
input vdd729a,
input ve61673,
input v7c533e,
output [15:0] va1a83a,
output v712cd1
);
localparam p1 = v5e4a03;
wire w0;
wire w2;
wire w3;
wire w4;
wire [0:15] w5;
assign w0 = ve61673;
assign w2 = v7c533e;
assign w3 = vdd729a;
assign v712cd1 = w4;
assign va1a83a = w5;
v8d4ef5_vbd6086 #(
.M(p1)
) vbd6086 (
.rst(w0),
.cnt(w2),
.clk(w3),
.ov(w4),
.q(w5)
);
endmodule
//---------------------------------------------------
//-- Contador-16bits-up-rst
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Contador módulo M, ascendente, de 16 bits, con reset
//---------------------------------------------------
module v8d4ef5_vbd6086 #(
parameter M = 0
) (
input clk,
input rst,
input cnt,
output [15:0] q,
output ov
);
//-- Numero de bits del contador
localparam N = 16;
//-- En contadores de N bits:
//-- M = 2 ** N
//-- Internamente usamos un bit mas
//-- (N+1) bits
reg [N:0] qi = 0;
always @(posedge clk)
if (rst | ov)
qi <= 0;
else
if (cnt)
qi <= qi + 1;
assign q = qi;
//-- Comprobar overflow
assign ov = (qi == M);
endmodule
//---- Top entity
module vbd4c1c (
input ved8395,
input ve78ab8,
output v3487af
);
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
assign w0 = ve78ab8;
assign w1 = ved8395;
assign v3487af = w2;
assign w4 = ve78ab8;
assign w4 = w0;
v1c7dae vbf8366 (
.vf54559(w0),
.va4102a(w1),
.ve8318d(w3)
);
vd12401 v456da5 (
.vcbab45(w2),
.v0e28cb(w3),
.v3ca442(w4)
);
endmodule
//---------------------------------------------------
//-- Edges-detector
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input
//---------------------------------------------------
//---- Top entity
module v1c7dae #(
parameter v71e305 = 0
) (
input va4102a,
input vf54559,
output ve8318d
);
localparam p2 = v71e305;
wire w0;
wire w1;
wire w3;
assign w0 = va4102a;
assign ve8318d = w1;
assign w3 = vf54559;
v1c7dae_vb8adf8 #(
.INI(p2)
) vb8adf8 (
.clk(w0),
.q(w1),
.d(w3)
);
endmodule
//---------------------------------------------------
//-- Biestable-D
//-- - - - - - - - - - - - - - - - - - - - - - - - --
//-- Biestable de datos (Tipo D). Cuando se recibe un tic por load se captura el dato
//---------------------------------------------------
module v1c7dae_vb8adf8 #(
parameter INI = 0
) (
input clk,
input d,
output q
);
reg q = INI;
always @(posedge clk)
q <= d;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_BLACKBOX_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_BLACKBOX_V
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={650} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=525, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.034, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.03, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.082, PCW_UIPARAM_DDR_BOARD_DELAY0=0.176, PCW_UIPARAM_DDR_BOARD_DELAY1=0.159, PCW_UIPARAM_DDR_BOARD_DELAY2=0.162, PCW_UIPARAM_DDR_BOARD_DELAY3=0.187, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50.000000, PCW_APU_PERIPHERAL_FREQMHZ=650, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K128M16 JT-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=EMIO, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 46, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=0, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
/*
* Copyright (c) 2011-2014 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
`include "defines.v"
module cpu(
input clk,
input rst,
output mem_re,
output mem_we,
output [29:0] memaddr,
input [31:0] rmemdata,
output [31:0] wmemdata,
output [31:0] debugout
);
/* unused bits for now */
assign mem_we = 0;
assign wmemdata = 0;
assign debugout = 0;
wire stall_2to1;
wire [31:0] ir_1to2;
wire [29:0] nextpc_1to2;
wire take_branch_3to1;
wire [29:0] branch_pc_3to1;
stage1_fetch stage1(
.clk_i(clk),
.rst_i(rst),
/* inter-stage */
.take_branch_i(take_branch_3to1),
.branch_pc_i(branch_pc_3to1),
.stall_i(stall_2to1),
.ir_o(ir_1to2),
.nextpc_o(nextpc_1to2),
/* memory interface */
.re_o(mem_re),
.rmemaddr_o(memaddr),
.rmemdata_i(rmemdata)
);
wire do_wb_5to2;
wire [4:0] wb_reg_5to2;
wire [31:0] wb_val_5to2;
wire stall_3to2;
wire [29:0] nextpc_2to3;
wire [1:0] control_branch_2to3;
wire control_load_2to3;
wire control_store_2to3;
wire [3:0] aluop_2to3;
wire [31:0] alu_a_2to3;
wire [31:0] alu_b_2to3;
wire [31:0] branch_test_val_2to3;
wire do_wb_2to3;
wire [4:0] wb_reg_2to3;
stage2_decode stage2(
.clk_i(clk),
.rst_i(rst),
/* inter-stage */
.ir_i(ir_1to2),
.nextpc_i(nextpc_1to2),
.stall_i(stall_3to2),
/* from stage 5 */
.do_wb_i(do_wb_5to2),
.wb_reg_i(wb_reg_5to2),
.wb_val_i(wb_val_5to2),
/* output to stage3 */
.stall_o(stall_2to1),
.control_branch_o(control_branch_2to3),
.control_load_o(control_load_2to3),
.control_store_o(control_store_2to3),
.aluop_o(aluop_2to3),
.alu_a_o(alu_a_2to3),
.alu_b_o(alu_b_2to3),
.branch_test_val_o(branch_test_val_2to3),
.do_wb_o(do_wb_2to3),
.wb_reg_o(wb_reg_2to3)
);
wire stall_4to3;
wire control_load_3to4;
wire control_store_3to4;
wire do_wb_3to4;
wire [4:0] wb_reg_3to4;
wire [31:0] alu_3to4;
stage3_execute stage3(
.clk_i(clk),
.rst_i(rst),
.stall_i(stall_4to3),
.control_branch_i(control_branch_2to3),
.control_load_i(control_load_2to3),
.control_store_i(control_store_2to3),
.aluop_i(aluop_2to3),
.alu_a_i(alu_a_2to3),
.alu_b_i(alu_b_2to3),
.branch_test_val_i(branch_test_val_2to3),
.do_wb_i(do_wb_2to3),
.wb_reg_i(wb_reg_2to3),
.stall_o(stall_3to2),
.alu_o(alu_3to4),
.take_branch_o(take_branch_3to1),
.branch_pc_o(branch_pc_3to1),
.control_load_o(control_load_3to4),
.control_store_o(control_store_3to4),
.do_wb_o(do_wb_3to4),
.wb_reg_o(wb_reg_3to4)
);
wire do_wb_4to5;
wire [4:0] wb_reg_4to5;
wire [31:0] wb_val_4to5;
stage4_memory stage4(
.clk_i(clk),
.rst_i(rst),
.alu_i(alu_3to4),
.control_load_i(control_load_3to4),
.control_store_i(control_store_3to4),
.do_wb_i(do_wb_3to4),
.wb_reg_i(wb_reg_3to4),
.stall_o(stall_4to3),
.do_wb_o(do_wb_4to5),
.wb_reg_o(wb_reg_4to5),
.wb_val_o(wb_val_4to5)
);
stage5_writeback stage5(
.clk_i(clk),
.rst_i(rst),
.do_wb_i(do_wb_4to5),
.wb_reg_i(wb_reg_4to5),
.wb_val_i(wb_val_4to5),
.do_wb_o(do_wb_5to2),
.wb_reg_o(wb_reg_5to2),
.wb_val_o(wb_val_5to2)
);
`ifdef UNUSED
assign wmemdata = (mem_we && !mem_re) ? reg_c : 32'bz;
assign debugout = pc;
/* next pc */
reg [29:0] pc;
reg [29:0] nextpc;
reg [3:0] control_branch;
`define CONTROL_BRANCH_NOTAKE 4'b1xxx
`define CONTROL_BRANCH_UNCOND 4'b000?
`define CONTROL_BRANCH_COND_Z 4'b0010
`define CONTROL_BRANCH_COND_NZ 4'b0011
`define CONTROL_BRANCH_RA_UNCOND 4'b010?
`define CONTROL_BRANCH_RA_COND_Z 4'b0110
`define CONTROL_BRANCH_RA_COND_NZ 4'b0111
always @(control_branch or reg_c or aluout or reg_a or pc)
begin
casex (control_branch)
`CONTROL_BRANCH_NOTAKE: nextpc = pc;
`CONTROL_BRANCH_COND_Z: nextpc = (reg_c == 32'd0) ? aluout[29:0] : pc;
`CONTROL_BRANCH_COND_NZ: nextpc = (reg_c != 32'd0) ? aluout[29:0] : pc;
`CONTROL_BRANCH_UNCOND: nextpc = aluout[29:0];
`CONTROL_BRANCH_RA_COND_Z: nextpc = (reg_c == 32'd0) ? (reg_a >> 2) : pc;
`CONTROL_BRANCH_RA_COND_NZ: nextpc = (reg_c != 32'd0) ? (reg_a >> 2) : pc;
`CONTROL_BRANCH_RA_UNCOND: nextpc = (reg_a >> 2);
endcase
end
`define STATE_RST 3'd0
`define STATE_FETCH 3'd1
`define STATE_DECODE 3'd2
`define STATE_LOAD 3'd3
`define STATE_STORE 3'd4
reg [2:0] state;
reg control_load;
reg control_store;
/* top level states */
reg [2:0] nextstate;
always @(rst or state or control_load or control_store)
begin
if (rst)
nextstate = `STATE_RST;
else if (state == `STATE_RST || state == `STATE_LOAD || state == `STATE_STORE)
nextstate = `STATE_FETCH;
else if (state == `STATE_FETCH)
nextstate = `STATE_DECODE;
else if (control_load)
nextstate = `STATE_LOAD;
else if (control_store)
nextstate = `STATE_STORE;
else
nextstate = `STATE_FETCH;
end
assign mem_we = (nextstate == `STATE_STORE);
assign mem_re = ((nextstate == `STATE_FETCH) || (nextstate == `STATE_LOAD));
always @(nextstate or pc or nextpc or aluout)
begin
case (nextstate)
`STATE_RST: memaddr = pc;
`STATE_FETCH: memaddr = nextpc;
`STATE_DECODE: memaddr = 30'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
`STATE_LOAD: memaddr = aluout[31:2];
`STATE_STORE: memaddr = aluout[31:2];
default: memaddr = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
endcase
end
always @(posedge clk)
begin
state <= nextstate;
case (nextstate)
`STATE_RST: begin
pc <= 0;
end
`STATE_FETCH: begin
pc <= nextpc;
end
`STATE_DECODE: begin
pc <= aluout[29:0];
ir <= rmemdata;
end
endcase
end
/* alu */
reg [3:0] aluop;
wire [31:0] aluout;
wire [31:0] aluain;
wire [31:0] alubin;
alu alu0(
.op(aluop),
.a(aluain),
.b(alubin),
.res(aluout)
);
/* register file */
reg [3:0] reg_a_sel;
reg [3:0] reg_b_sel;
reg [3:0] reg_w_sel;
wire [31:0] reg_a;
wire [31:0] reg_b;
wire [31:0] reg_c;
wire [31:0] reg_wdata;
reg control_reg_wb;
regfile #(32, 4) regs(
.clk(clk),
.we(control_reg_wb),
.wsel(reg_w_sel),
.wdata(reg_wdata),
.asel(reg_a_sel),
.adata(reg_a),
.bsel(reg_b_sel),
.bdata(reg_b),
.csel(decode_rd),
.cdata(reg_c)
);
/* alu a input mux */
reg alu_a_mux_sel;
`define ALU_A_SEL_DC 1'bx
`define ALU_A_SEL_REG 1'b0
`define ALU_A_SEL_PC 1'b1
mux2 #(32) alu_a_mux(
.sel(alu_a_mux_sel),
.in0(reg_a),
.in1({ 2'b0, pc }),
.out(aluain)
);
/* alu b input mux */
reg [1:0] alu_b_mux_sel;
`define ALU_B_SEL_DC 2'bxx
`define ALU_B_SEL_REG 2'b00
`define ALU_B_SEL_IMM16 2'b01
`define ALU_B_SEL_IMM22 2'b10
`define ALU_B_SEL_ONE 2'b11
mux4 #(32) alu_b_mux(
.sel(alu_b_mux_sel),
.in0(reg_b),
.in1(decode_imm16_signed),
.in2(decode_imm22_signed),
.in3(32'd1),
.out(alubin)
);
/* register file write mux */
reg [1:0] reg_w_mux_sel;
`define REG_W_SEL_DC 2'bxx
`define REG_W_SEL_ALU 2'b00
`define REG_W_SEL_MEM 2'b01
`define REG_W_SEL_PC 2'b10
`define REG_W_SEL_ZERO 2'b11
mux4 #(32) reg_w_mux(
.sel(reg_w_mux_sel),
.in0(aluout),
.in1(rmemdata),
.in2({ pc, 2'b0 }),
.in3(0),
.out(reg_wdata)
);
/* decoder */
reg [31:0] ir;
wire [1:0] decode_form = ir[31:30];
wire [5:0] decode_op = ir[29:24];
wire [3:0] decode_rd = ir[27:24];
wire [3:0] decode_aluop = ir[23:20];
wire [3:0] decode_ra = ir[19:16];
wire [3:0] decode_rb = ir[15:12];
wire [31:0] decode_imm16_signed = (ir[15]) ? { 16'b1111111111111111, ir[15:0] } : { 16'b0000000000000000, ir[15:0] };
wire [31:0] decode_imm22_signed = (ir[21]) ? { 10'b1111111111, ir[21:0] } : { 10'b0000000000, ir[21:0] };
always @(ir or state or decode_form or decode_op or decode_rd or decode_aluop or decode_ra or decode_rb or decode_imm16_signed or decode_imm22_signed)
begin
/* undefined state */
aluop = 4'bxxxx;
control_load = 0;
control_store = 0;
control_branch = `CONTROL_BRANCH_NOTAKE;
control_reg_wb = 0;
reg_a_sel = 4'bxxxx;
reg_b_sel = 4'bxxxx;
reg_w_sel = 4'bxxxx;
alu_a_mux_sel = `ALU_A_SEL_DC;
alu_b_mux_sel = `ALU_B_SEL_DC;
reg_w_mux_sel = `REG_W_SEL_DC;
case (state)
`STATE_FETCH: begin
/* use the alu to calculate the next pc */
aluop = 4'b0000; // add
alu_a_mux_sel = `ALU_A_SEL_PC;
alu_b_mux_sel = `ALU_B_SEL_ONE;
end
`STATE_DECODE: begin
casex (decode_form)
2'b0?: begin /* form 0 and form 1 are very similar */
aluop = decode_aluop;
reg_a_sel = decode_ra;
reg_b_sel = decode_rb;
if (decode_form == 0) begin
$display("form 0");
alu_a_mux_sel = `ALU_A_SEL_REG;
alu_b_mux_sel = `ALU_B_SEL_IMM16;
end else begin
$display("form 1");
alu_a_mux_sel = `ALU_A_SEL_REG;
alu_b_mux_sel = `ALU_B_SEL_REG;
end
casex (decode_op)
default: begin
control_reg_wb = 1;
reg_w_sel = decode_rd;
reg_w_mux_sel = `REG_W_SEL_ALU;
end
/* load */
6'b01????: begin
$display("load");
control_load = 1;
end
/* store */
6'b10????: begin
$display("store");
control_store = 1;
end
endcase
end
2'b10: begin
$display("form 2 - branch");
if (ir[29] == 0) begin
// pc relative branch
aluop = 0; // add
control_branch = { 1'b0, 1'b0, ir[23], ir[22] };
alu_a_mux_sel = `ALU_A_SEL_PC;
alu_b_mux_sel = `ALU_B_SEL_IMM22;
end else begin
// branch to reg
control_branch = { 1'b0, 1'b1, ir[23], ir[22] };
reg_a_sel = decode_ra;
end
// branch and link
if (ir[28]) begin
reg_w_sel = 15; // LR
reg_w_mux_sel = `REG_W_SEL_PC;
control_reg_wb = 1;
end
end
2'b11: begin
$display("form 3 - undefined");
end
endcase
end
`STATE_LOAD: begin
control_reg_wb = 1;
reg_w_sel = decode_rd;
reg_w_mux_sel = `REG_W_SEL_MEM;
end
default: begin
end
endcase
end
`endif
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:16:05 04/24/2015
// Design Name:
// Module Name: StartCastle
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BlackKeyRoom(clk_vga, CurrentX, CurrentY, mapData, wall);
input clk_vga;
input [9:0]CurrentX;
input [8:0]CurrentY;
input [7:0]wall;
output [7:0]mapData;
reg [7:0]mColor;
always @(posedge clk_vga) begin
//Top wall with door
if(((CurrentY < 40) && (CurrentX < 260)) || ((CurrentY < 40) && ~(CurrentX < 380))) begin
mColor[7:0] <= wall;
end
//Left side wall
else if(CurrentX < 40) begin
mColor[7:0] <= wall;
end
//Right side wall
else if(~(CurrentX < 600)) begin
mColor[7:0] <= wall;
end
//Bottom wall
else if(~(CurrentY < 440)) begin
mColor[7:0] <= wall;
//Floor area
end else
mColor[7:0] <= 8'b10110110;
end
assign mapData = mColor;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 29.06.2017 23:55:46
// Design Name:
// Module Name: instructionfetch
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Initially, the Jump/Branch/+4 decision was done by cascaded
// 2:1 muxs. This was causing a problem as the Jump address was arriving to PCPrime
// (wire) at the same posedge clk cycle that created it. Thus the jump occured in
// the current clock cycle and not in the next clock cycle. The Branch address was
// working as intended as the branch occured in the next cycle. The reason for this
// was that the Branch address had to go through 2 2:1 muxs, and the added
// propagation delay was enough to prevent the signal from reaching PCPrime at the
// same time as the current rising clk signal. PCJump only had to go through 1 mux
// and therefore the propagation delay wasn't enough.
//
// To fix this, I combined both control signals and created a 3:1 mux, (so all 3
// signals shared the same propagation delay) and stored the result into a new
// register (PCPrimeReg). This was to ensure that the next PC address and the
// current PC address remain separated.
//
// Added signals for the registers so I could monitor them on the simulation.
//
// Added reset switch to PC and PCPrimeReg register in order to initialise a 0
// value in them during normal operation.
//////////////////////////////////////////////////////////////////////////////////
module instructionfetch(
output [31:0] PCPlus4F,
output [31:0] instruction,
input [31:0] PCBranchF,
input [27:0] WAinstrF,
input clk, reset, JumpF, PCSrcF
);
wire [31:0] PCJump;
wire [1:0] controlSignals;
reg [31:0] PC, PCPrime;
instrmem instrmem_if(
.A( PC ),
.RD( instruction )
);
assign controlSignals = {JumpF, PCSrcF};
always @ (controlSignals or posedge reset or posedge clk) begin
if(reset) begin
PCPrime <= 0;
end else begin
case (controlSignals)
2'b00: PCPrime <= PCPlus4F;
2'b01: PCPrime <= PCBranchF;
2'b10: PCPrime <= PCJump;
default: PCPrime <= 0;
endcase
end
end
always @ (posedge clk or posedge reset) begin // I have no idea why, but PC required it's own always block, separate to PCPrime. The problem was that the Jump instruction address
if(reset) begin // was skipping PCPrime and being saved straight to PC. When I separated the 2 always blocks, 1 for each register, it appeared to fix
PC <= 0; // the problem. Using 'or' or ',' in the sensitivity list made no difference, perhaps the conflict was the level sensitivity of
end else begin // controlSignals that was causing the signal to go from PCJump -> PCPrime -> PC in 1 clock cycle. In the simulation, the PC register
PC <= PCPrime; // was going from 0 -> 4 -> 0, and skipping the 3rd instruction (in the testjump.dat file) which was the jump file. But it was still
end // functionally jumping, just a clock cycle too early, and the jump instruction appeared to have never been sent. Perhaps, if I lower
end // the clock period, I will be able to see that the jump instruction does get sent and does not get overwritten by the instruction
// that it is jumping to. Although, I am confused because this means that there is something that I don't understand about
// sensitivity lists and non-blocking assignments. I will be more careful in the future.
assign PCJump = {PCPlus4F[31:28], WAinstrF};
assign PCPlus4F = PCPrime + 32'h4;
initial begin
PC = 32'h00000000;
PCPrime = 32'h00000000;
$display(PC);
$display(PCPrime);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_REFGEN_NEW_SYMBOL_V
`define SKY130_FD_IO__TOP_REFGEN_NEW_SYMBOL_V
/**
* top_refgen_new: The REFGEN block (sky130_fd_io__top_refgen) is used
* to provide the input trip point (VINREF) for the
* differential input buffer in SIO and also
* the output buffer regulated output level (VOUTREF).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_refgen_new (
//# {{data|Data Signals}}
input DFT_REFGEN ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input ENABLE_H ,
input ENABLE_VDDA_H,
input HLD_H_N ,
input IBUF_SEL ,
//# {{power|Power}}
input [2:0] VOH_SEL ,
input [1:0] VREF_SEL ,
input VREG_EN ,
input VTRIP_SEL ,
inout REFLEAK_BIAS ,
output VINREF ,
inout VINREF_DFT ,
input VOHREF ,
output VOUTREF ,
inout VOUTREF_DFT
);
// Voltage supply signals
supply1 VCCD ;
supply1 VCCHIB ;
supply1 VDDA ;
supply1 VDDIO ;
supply1 VDDIO_Q;
supply0 VSSD ;
supply0 VSSIO ;
supply0 VSSIO_Q;
supply1 VSWITCH;
supply0 VSSA ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_REFGEN_NEW_SYMBOL_V
|
/**
* @module forward_unit
* @author sabertazimi
* @email [email protected]
* @brief data hazards detection and forward signals generation
* @input ID_rs rs value in ID stage
* @input ID_rt rt value in ID stage
* @input EX_rs rs value in EX stage
* @input EX_rt rt value in EX stage
* @input MEM_rt rt value in MEM stage
* @input MEM_ramwe ramwe signal in MEM stage
* @input MEM_regwe regwe signal in MEM stage
* @input WB_regwe regwe signal in WB stage
* @input MEM_RW RW value in MEM stage
* @input WB_RW RW value in WB stage
* @output ID_forwardA forward signal for R1out in ID stage
* @output ID_forwardB forward signal for R2out in ID stage
* @output EX_forwardA forward signal for ALUXin in EX stage
* @output EX_forwardB forward signal for ALUYin in EX stage
* @output MEM_forward forward signal for RAMin in MEM stage
*/
module forward_unit
(
input [4:0] ID_rs,
input [4:0] ID_rt,
input [4:0] EX_rs,
input [4:0] EX_rt,
input [4:0] MEM_rt,
input MEM_ramwe,
input MEM_regwe,
input WB_regwe,
input [4:0] MEM_RW,
input [4:0] WB_RW,
output reg [1:0] ID_forwardA,
output reg [1:0] ID_forwardB,
output reg [1:0] EX_forwardA,
output reg [1:0] EX_forwardB,
output MEM_forward
);
// ID stage forward
// for branch usage in decode stage
// for WB.RegData -> ID/EX pipeline register data hazard
always @ ( * ) begin
if ((ID_rs != 0) && (ID_rs == MEM_RW) && MEM_regwe) begin
ID_forwardA <= 2'b10; // from MEM stage
end else if ((ID_rs != 0) && (ID_rs == WB_RW) && WB_regwe) begin
ID_forwardA <= 2'b01; // from WB stage
end else begin
ID_forwardA <= 2'b00; // no forwarding
end
end
always @ ( * ) begin
if ((ID_rt != 0) && (ID_rt == MEM_RW) && MEM_regwe) begin
ID_forwardB <= 2'b10; // from MEM stage
end else if ((ID_rt != 0) && (ID_rt == WB_RW) && WB_regwe) begin
ID_forwardB <= 2'b01; // from WB stage
end else begin
ID_forwardB <= 2'b00; // no forwarding
end
end
// EX stage forward
// id/ex r-instr(r-r-alu, r-imm-alu, load/store, branch) + mem/wb r-r-alu: $rd => $rs/$rt
// id/ex r-instr(r-r-alu, r-imm-alu, load/store, branch) + mem/wb r-imm-alu: $rd => $rs/$rt
// id/ex r-instr(r-r-alu, r-imm-alu, load/store, branch) + mem/wb load: $rt => $rs/$rt
// id/ex r-instr(r-r-alu, r-imm-alu, load/store, branch) + mem/wb jal : $ra => $rs/$rt
always @ ( * ) begin
if ((EX_rs != 0) && (EX_rs == MEM_RW) && MEM_regwe) begin
EX_forwardA <= 2'b10; // from memory MEM stage
end else if ((EX_rs != 0) && (EX_rs == WB_RW) && WB_regwe) begin
EX_forwardA <= 2'b01; // from WB stage
end else begin
EX_forwardA <= 2'b00; // no forwarding
end
end
always @ ( * ) begin
if ((EX_rt != 0) && (EX_rt == MEM_RW) && MEM_regwe) begin
EX_forwardB <= 2'b10; // from memory access stage
end else if ((EX_rt != 0) && (EX_rt == WB_RW) && WB_regwe) begin
EX_forwardB <= 2'b01; // from write back stage
end else begin
EX_forwardB <= 2'b00; // no forwarding
end
end
// MEM stage forward
// ex/mem sw + mem/wb load: $rt => $rt
assign MEM_forward = (WB_regwe && MEM_ramwe && MEM_rt != 0 && MEM_rt == WB_RW);
endmodule // forward_unit
|
reg reset;
wire [WIDTH-1:0] data_in_sig;
reg data_in_clock;
wire data_in_enable;
wire data_in_start_sig;
wire data_in_end_sig;
wire [WIDTH-1:0] data_out_sig;
wire data_out_start_sig;
wire data_out_end_sig;
reg data_out_clock;
wire data_out_enable;
fifo #(
.DATA_WIDTH (WIDTH),
.FIFO_DEPTH (DEPTH)
)
ff (
.reset(reset),
// IN PORT
.data_in(data_in_sig),
.data_in_clock(data_in_clock),
.data_in_enable(data_in_enable),
.data_in_start(data_in_start_sig),
.data_in_end(data_in_end_sig),
// OUT PORT
.data_out(data_out_sig),
.data_out_clock(data_out_clock),
.data_out_enable(data_out_enable),
.data_out_start(data_out_start_sig),
.data_out_end(data_out_end_sig)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
util (
.data_in(),
.data_in_enable(),
.data_out(),
.data_out_enable(),
.clock(clock)
);
utilities #(.OUT_WIDTH (WIDTH),
.IN_WIDTH (WIDTH),
.DEBUG(1))
data_in (
.data_in(),
.data_in_enable(),
.data_out(data_in_sig),
.data_out_enable(data_in_enable),
.clock(data_in_clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_in_start (
.data_in(),
.data_in_enable(),
.data_out(data_in_start_sig),
.data_out_enable(),
.clock(data_in_clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_in_end (
.data_in(),
.data_in_enable(),
.data_out(data_in_end_sig),
.data_out_enable(),
.clock(data_in_clock)
);
utilities #(.OUT_WIDTH (WIDTH),
.IN_WIDTH (WIDTH),
.DEBUG(1))
data_out (
.data_in(data_out_sig),
.data_in_enable(data_out_enable),
.data_out(),
.data_out_enable(),
.clock(data_out_clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_out_start (
.data_in(data_out_start_sig),
.data_in_enable(),
.data_out(),
.data_out_enable(),
.clock(data_out_clock)
);
utilities #(.OUT_WIDTH (1),
.IN_WIDTH (1))
data_out_end (
.data_in(data_out_end_sig),
.data_in_enable(),
.data_out(),
.data_out_enable(),
.clock(data_out_clock)
);
initial
begin
data_in_clock = 0;
data_out_clock = 0;
reset = 1;
end
always
#5 data_in_clock = ~data_in_clock;
always
#5 data_out_clock = ~data_out_clock;
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altera_mult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.lpm_type = "altera_mult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.selected_device_family = "CYCLONEII",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altera_mult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.lpm_type = "altera_mult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.selected_device_family = "CYCLONEII",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_2_V
`define SKY130_FD_SC_LS__DLRTN_2_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog wrapper for dlrtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlrtn_2 (
Q ,
RESET_B,
D ,
GATE_N
);
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlrtn base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_2_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.28xd
// \ \ Application: netgen
// / / Filename: top_synthesis.v
// /___/ /\ Timestamp: Sat Nov 08 17:52:16 2014
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim top.ngc top_synthesis.v
// Device : xc6vlx240t-3-ff1156
// Input file : top.ngc
// Output file : F:\pro\DSPA\proj_dspa\netgen\synthesis\top_synthesis.v
// # of Modules : 1
// Design Name : top
// Xilinx : C:\Xilinx\14.2\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module top (
clock, a1, a2, store000_out, store001_out, store010_out, store100_out, store101_out, store110_out, cout1, cout2, cout3, cout4, cout5, cout6
);
input clock;
input [4 : 0] a1;
input [4 : 0] a2;
output [3 : 0] store000_out;
output [3 : 0] store001_out;
output [3 : 0] store010_out;
output [3 : 0] store100_out;
output [3 : 0] store101_out;
output [3 : 0] store110_out;
output [1 : 0] cout1;
output [1 : 0] cout2;
output [1 : 0] cout3;
output [1 : 0] cout4;
output [1 : 0] cout5;
output [1 : 0] cout6;
wire a1_4_IBUF_0;
wire a1_3_IBUF_1;
wire a1_2_IBUF_2;
wire a1_1_IBUF_3;
wire a1_0_IBUF_4;
wire a2_4_IBUF_5;
wire a2_3_IBUF_6;
wire a2_2_IBUF_7;
wire a2_1_IBUF_8;
wire a2_0_IBUF_9;
wire clock_BUFGP_10;
wire \dbns1/store010[0] ;
wire \dbns2/store010[2] ;
wire \dbns2/store010[0] ;
wire N1;
wire \dbns2/PWR_2_o_b[4]_AND_1_o21 ;
wire \dbns2/Mmux_b[4]_a[4]_mux_69_OUT52_72 ;
wire \dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT51 ;
wire \dbns2/Mmux_b[4]_a[4]_mux_69_OUT51 ;
wire \dbns2/Mmux_b[4]_b[4]_mux_66_OUT_A51 ;
wire \dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4> ;
wire \dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> ;
wire \dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1> ;
wire \dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> ;
wire \dbns2/_n0555_inv_86 ;
wire \dbns2/_n0541_inv ;
wire \dbns2/_n0496_inv ;
wire \dbns2/_n0374_inv ;
wire \dbns2/_n0329_inv ;
wire \dbns2/_n0435_inv ;
wire \dbns2/_n0268_inv ;
wire \dbns2/_n0207_inv_93 ;
wire \dbns2/_n0557_inv ;
wire \dbns2/PWR_2_o_PWR_2_o_AND_6_o ;
wire \dbns2/r1[4]_GND_2_o_mux_65_OUT<0> ;
wire \dbns2/r1[4]_GND_2_o_mux_65_OUT<1> ;
wire \dbns2/r1[4]_GND_2_o_mux_65_OUT<2> ;
wire \dbns2/r1[4]_GND_2_o_mux_65_OUT<3> ;
wire \dbns2/r1[4]_GND_2_o_mux_65_OUT<4> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_83_OUT<0> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<0> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<1> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<2> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<3> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<0> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<1> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<2> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<3> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_80_OUT<0> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_80_OUT<2> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<0> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<1> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<2> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<3> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_78_OUT<0> ;
wire \dbns2/r1[4]_GND_2_o_wide_mux_78_OUT<1> ;
wire \dbns2/PWR_2_o_b[4]_AND_5_o_118 ;
wire \dbns2/PWR_2_o_b[4]_AND_3_o ;
wire \dbns2/PWR_2_o_b[4]_AND_1_o ;
wire \dbns2/_n0198_123 ;
wire \dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<1> ;
wire \dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ;
wire \dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<3> ;
wire \dbns2/b[4]_a[4]_mux_69_OUT<0> ;
wire \dbns2/b[4]_a[4]_mux_69_OUT<1> ;
wire \dbns2/b[4]_a[4]_mux_69_OUT<2> ;
wire \dbns2/b[4]_a[4]_mux_69_OUT<3> ;
wire \dbns2/b[4]_a[4]_mux_69_OUT<4> ;
wire \dbns1/PWR_2_o_b[4]_AND_1_o21 ;
wire \dbns1/Mmux_b[4]_a[4]_mux_69_OUT52_146 ;
wire \dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT51 ;
wire \dbns1/Mmux_b[4]_a[4]_mux_69_OUT51 ;
wire \dbns1/Mmux_b[4]_b[4]_mux_66_OUT_A51 ;
wire \dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4> ;
wire \dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> ;
wire \dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1> ;
wire \dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> ;
wire \dbns1/_n0555_inv_160 ;
wire \dbns1/_n0541_inv ;
wire \dbns1/_n0496_inv ;
wire \dbns1/_n0374_inv ;
wire \dbns1/_n0329_inv ;
wire \dbns1/_n0435_inv ;
wire \dbns1/_n0268_inv ;
wire \dbns1/_n0207_inv_167 ;
wire \dbns1/_n0557_inv ;
wire \dbns1/count_inv ;
wire \dbns1/PWR_2_o_PWR_2_o_AND_6_o ;
wire \dbns1/r1[4]_GND_2_o_mux_65_OUT<0> ;
wire \dbns1/r1[4]_GND_2_o_mux_65_OUT<1> ;
wire \dbns1/r1[4]_GND_2_o_mux_65_OUT<2> ;
wire \dbns1/r1[4]_GND_2_o_mux_65_OUT<3> ;
wire \dbns1/r1[4]_GND_2_o_mux_65_OUT<4> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_83_OUT<0> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<0> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<1> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<2> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<3> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<0> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<1> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<2> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<3> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_80_OUT<0> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_80_OUT<2> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<0> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<1> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<2> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<3> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_78_OUT<0> ;
wire \dbns1/r1[4]_GND_2_o_wide_mux_78_OUT<1> ;
wire \dbns1/PWR_2_o_b[4]_AND_5_o_193 ;
wire \dbns1/PWR_2_o_b[4]_AND_3_o ;
wire \dbns1/PWR_2_o_b[4]_AND_1_o ;
wire \dbns1/_n0198_198 ;
wire \dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<1> ;
wire \dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ;
wire \dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<3> ;
wire \dbns2/count_210 ;
wire \dbns1/b[4]_a[4]_mux_69_OUT<0> ;
wire \dbns1/b[4]_a[4]_mux_69_OUT<1> ;
wire \dbns1/b[4]_a[4]_mux_69_OUT<2> ;
wire \dbns1/b[4]_a[4]_mux_69_OUT<3> ;
wire \dbns1/b[4]_a[4]_mux_69_OUT<4> ;
wire \addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 ;
wire \addn_1/case110/out[3]_input2[3]_mux_204_OUT<0> ;
wire \addn_1/case110/out[3]_input2[3]_mux_204_OUT<1> ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT266 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT117 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT36_228 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT116 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT35_230 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT115 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT25_232 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT114_233 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT34_234 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT113_235 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT33_236 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT112_237 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT23_238 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT111_239 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT32_240 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT22_241 ;
wire \addn_1/case101/SF2 ;
wire \addn_1/case101/SF1 ;
wire \addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT61 ;
wire \addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>4 ;
wire \addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT102 ;
wire \addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT122 ;
wire \addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 ;
wire \addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>3 ;
wire \addn_1/case101/_n0296<40>2 ;
wire \addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT13 ;
wire \addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT121 ;
wire \addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>2 ;
wire \addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT101 ;
wire \addn_1/case101/_n0296<42>1 ;
wire \addn_1/case101/_n0296<30>1 ;
wire \addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>1 ;
wire \addn_1/case101/Mmux_input2[3]_input2[3]_mux_196_OUT1 ;
wire \addn_1/case101/_n0269_inv ;
wire \addn_1/case101/_n0296[55] ;
wire \addn_1/case101/_n0296[49] ;
wire \addn_1/case101/_n0296[46] ;
wire \addn_1/case101/_n0296[43] ;
wire \addn_1/case101/_n0296[40] ;
wire \addn_1/case101/_n0296[36] ;
wire \addn_1/case101/_n0296[34] ;
wire \addn_1/case101/_n0296[30] ;
wire \addn_1/case101/_n0296[26] ;
wire \addn_1/case101/_n0296[28] ;
wire \addn_1/case101/_n0296[29] ;
wire \addn_1/case101/_n0296[24] ;
wire \addn_1/case101/_n0296[20] ;
wire \addn_1/case101/_n0296[22] ;
wire \addn_1/case101/_n0296[23] ;
wire \addn_1/case101/_n0296[18] ;
wire \addn_1/case101/_n0296[16] ;
wire \addn_1/case101/_n0296[17] ;
wire \addn_1/case101/_n0296[12] ;
wire \addn_1/case101/_n0296[10] ;
wire \addn_1/case101/input2[3]_input2[3]_mux_128_OUT<0> ;
wire \addn_1/case101/input1[3]_input1[3]_OR_6_o ;
wire \addn_1/case101/input1[3]_input1[3]_OR_8_o ;
wire \addn_1/case101/input1[3]_input1[3]_OR_7_o ;
wire \addn_1/case101/input1[3]_GND_4_o_equal_17_o ;
wire \addn_1/case101/input1[3]_PWR_6_o_equal_37_o ;
wire \addn_1/case101/input1[3]_PWR_6_o_equal_27_o ;
wire \addn_1/case101/_n0241 ;
wire \addn_1/case101/out[3]_input2[3]_mux_204_OUT<0> ;
wire \addn_1/case101/out[3]_input2[3]_mux_204_OUT<1> ;
wire \addn_1/case101/out[3]_input2[3]_mux_204_OUT<2> ;
wire \addn_1/case101/out[3]_input2[3]_mux_204_OUT<3> ;
wire \addn_1/case101/cout[1]_input2[3]_mux_205_OUT<0> ;
wire \addn_1/case101/cout[1]_input2[3]_mux_205_OUT<1> ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT116 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT115 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT114 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT34_297 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT113 ;
wire \addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT613 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT33_300 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT112 ;
wire \addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT612 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT111 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT22_304 ;
wire \addn_1/case100/_n0296<66>1 ;
wire \addn_1/case100/SF2 ;
wire \addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT122 ;
wire \addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT14 ;
wire \addn_1/case100/_n0296<40>2 ;
wire \addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT121 ;
wire \addn_1/case100/_n0296<42>1 ;
wire \addn_1/case100/_n0296<40>1 ;
wire \addn_1/case100/_n0296<30>1 ;
wire \addn_1/case100/input2[3]_input2[3]_mux_134_OUT<0>1 ;
wire \addn_1/case100/_n0296[46] ;
wire \addn_1/case100/_n0296[40] ;
wire \addn_1/case100/_n0296[34] ;
wire \addn_1/case100/_n0296[29] ;
wire \addn_1/case100/_n0296[20] ;
wire \addn_1/case100/_n0296[22] ;
wire \addn_1/case100/_n0296[23] ;
wire \addn_1/case100/_n0296[16] ;
wire \addn_1/case100/_n0296[17] ;
wire \addn_1/case100/_n0296[10] ;
wire \addn_1/case100/input1[3]_input1[3]_OR_7_o ;
wire \addn_1/case100/_n0241 ;
wire \addn_1/case100/out[3]_input2[3]_mux_204_OUT<0> ;
wire \addn_1/case100/out[3]_input2[3]_mux_204_OUT<1> ;
wire \addn_1/case100/out[3]_input2[3]_mux_204_OUT<2> ;
wire \addn_1/case100/out[3]_input2[3]_mux_204_OUT<3> ;
wire \addn_1/case100/cout[1]_input2[3]_mux_205_OUT<0> ;
wire \addn_1/case100/cout[1]_input2[3]_mux_205_OUT<1> ;
wire \dbns1/store010[2] ;
wire \addn_1/case010/out[3]_input2[3]_mux_204_OUT<0> ;
wire \addn_1/case010/out[3]_input2[3]_mux_204_OUT<1> ;
wire \addn_1/case010/out[3]_input2[3]_mux_204_OUT<2> ;
wire \addn_1/case010/out[3]_input2[3]_mux_204_OUT<3> ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT116 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT115 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT114 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT34_341 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT113 ;
wire \addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT613 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT33_344 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT112 ;
wire \addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT612 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT111 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT22_348 ;
wire \addn_1/case001/_n0296<66>1 ;
wire \addn_1/case001/SF2 ;
wire \addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT122 ;
wire \addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT14 ;
wire \addn_1/case001/_n0296<40>2 ;
wire \addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT121 ;
wire \addn_1/case001/_n0296<42>1 ;
wire \addn_1/case001/_n0296<40>1 ;
wire \addn_1/case001/_n0296<30>1 ;
wire \addn_1/case001/input2[3]_input2[3]_mux_134_OUT<0>1 ;
wire \addn_1/case001/_n0296[46] ;
wire \addn_1/case001/_n0296[40] ;
wire \addn_1/case001/_n0296[34] ;
wire \addn_1/case001/_n0296[29] ;
wire \addn_1/case001/_n0296[20] ;
wire \addn_1/case001/_n0296[22] ;
wire \addn_1/case001/_n0296[23] ;
wire \addn_1/case001/_n0296[16] ;
wire \addn_1/case001/_n0296[17] ;
wire \addn_1/case001/_n0296[10] ;
wire \addn_1/case001/input1[3]_input1[3]_OR_7_o ;
wire \addn_1/case001/_n0241 ;
wire \addn_1/case001/out[3]_input2[3]_mux_204_OUT<0> ;
wire \addn_1/case001/out[3]_input2[3]_mux_204_OUT<1> ;
wire \addn_1/case001/out[3]_input2[3]_mux_204_OUT<2> ;
wire \addn_1/case001/out[3]_input2[3]_mux_204_OUT<3> ;
wire \addn_1/case001/cout[1]_input2[3]_mux_205_OUT<0> ;
wire \addn_1/case001/cout[1]_input2[3]_mux_205_OUT<1> ;
wire \addn_1/case000/out[3]_input2[3]_mux_204_OUT<0> ;
wire \addn_1/case000/out[3]_input2[3]_mux_204_OUT<1> ;
wire \addn_1/case000/out[3]_input2[3]_mux_204_OUT<2> ;
wire \addn_1/case000/out[3]_input2[3]_mux_204_OUT<3> ;
wire N2;
wire N4;
wire N6;
wire N12;
wire N14;
wire \dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>1_386 ;
wire N16;
wire N18;
wire N20;
wire N26;
wire N28;
wire \dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>1_392 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT2 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT21_394 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT22_395 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT24 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT26_397 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT27_398 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT21 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT24_400 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT26_401 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT27_402 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT28_403 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT29_404 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT210_405 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT211_406 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT212 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT1 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT11_409 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT12 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT14_411 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT15_412 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT17_413 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT18_414 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT4 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT41_416 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT42_417 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT43_418 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT44_419 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT45_420 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT47 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT48_422 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT49_423 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT2661_424 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT2662_425 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT3 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT31_427 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT37_428 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT38_429 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT39 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT310_431 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT311_432 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT312_433 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT314 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT315 ;
wire \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT316 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT11_438 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT12_439 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT13_440 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT14_441 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT15_442 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT16_443 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT17_444 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT18_445 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT19_446 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT110_447 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT118 ;
wire \addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT119 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT22 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT23_451 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT24_452 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT25_453 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT27_454 ;
wire N30;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT11 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT12_457 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT13_458 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT14_459 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT15_460 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT18 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT4 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT41_463 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT42_464 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT43_465 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT45 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT46_467 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT32 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT37_469 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT39 ;
wire \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT310 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT1 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT11_473 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT14 ;
wire \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT18 ;
wire N32;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT22 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT23_478 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT24_479 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT25_480 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT27_481 ;
wire N36;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT11 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT12_484 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT13_485 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT14_486 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT15_487 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT18 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT4 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT41_490 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT42_491 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT43_492 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT45 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT46_494 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT32 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT37_496 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT39 ;
wire \addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT310 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT1 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT11_500 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT14 ;
wire \addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT18 ;
wire N38;
wire N60;
wire N62;
wire N64;
wire N65;
wire N67;
wire N68;
wire N90;
wire N92;
wire N94;
wire N112;
wire N114;
wire N116;
wire N118;
wire N126;
wire N128;
wire N130;
wire N132;
wire N134;
wire N136;
wire N138;
wire N140;
wire N142;
wire N144;
wire N152;
wire N154;
wire N156;
wire N158;
wire N177;
wire N178;
wire N180;
wire N181;
wire N183;
wire N185;
wire N189;
wire N191;
wire N193;
wire N195;
wire N197;
wire N199;
wire N213;
wire N215;
wire N219;
wire N225;
wire N226;
wire N235;
wire N237;
wire N239;
wire N240;
wire N242;
wire N244;
wire N246;
wire N247;
wire N248;
wire N250;
wire N264;
wire \dbns1/store101_0_1_606 ;
wire \dbns1/store101_3_1_607 ;
wire \dbns1/store101_1_1_608 ;
wire \dbns2/store101_1_1_609 ;
wire \dbns1/store101_0_2_610 ;
wire N266;
wire N267;
wire N268;
wire N269;
wire N270;
wire N271;
wire N272;
wire N273;
wire N274;
wire N275;
wire [1 : 0] \dbns1/store000 ;
wire [3 : 0] \dbns1/store001 ;
wire [3 : 0] \dbns1/store100 ;
wire [3 : 0] \dbns1/store101 ;
wire [1 : 0] \dbns2/store000 ;
wire [3 : 0] \dbns2/store001 ;
wire [3 : 0] \dbns2/store100 ;
wire [3 : 0] \dbns2/store101 ;
wire [3 : 0] \addn_1/case000/out ;
wire [3 : 0] \addn_1/case001/out ;
wire [3 : 0] \addn_1/case010/out ;
wire [3 : 0] \addn_1/case100/out ;
wire [3 : 0] \addn_1/case101/out ;
wire [1 : 0] \addn_1/case110/out ;
wire [1 : 0] \addn_1/case001/cout ;
wire [1 : 0] \addn_1/case100/cout ;
wire [1 : 0] \addn_1/case101/cout ;
wire [2 : 0] \dbns2/remain ;
wire [2 : 0] \dbns2/Result ;
wire [1 : 0] \dbns2/PWR_2_o_GND_2_o_mux_47_OUT ;
wire [2 : 0] \dbns2/shift ;
wire [4 : 0] \dbns2/r1 ;
wire [4 : 0] \dbns2/b ;
wire [2 : 0] \dbns1/remain ;
wire [2 : 0] \dbns1/Result ;
wire [1 : 0] \dbns1/PWR_2_o_GND_2_o_mux_47_OUT ;
wire [2 : 0] \dbns1/shift ;
wire [4 : 0] \dbns1/r1 ;
wire [4 : 0] \dbns1/b ;
wire [0 : 0] \dbns2/store110 ;
wire [0 : 0] \dbns1/store110 ;
GND XST_GND (
.G(\addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 )
);
VCC XST_VCC (
.P(N1)
);
FDRE #(
.INIT ( 1'b0 ))
\dbns2/remain_0 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0555_inv_86 ),
.D(\dbns2/Result [0]),
.R(\dbns1/count_inv ),
.Q(\dbns2/remain [0])
);
FDSE #(
.INIT ( 1'b1 ))
\dbns2/remain_2 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0555_inv_86 ),
.D(\dbns2/Result [2]),
.S(\dbns1/count_inv ),
.Q(\dbns2/remain [2])
);
FDRE #(
.INIT ( 1'b0 ))
\dbns2/remain_1 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0555_inv_86 ),
.D(\dbns2/Result [1]),
.R(\dbns1/count_inv ),
.Q(\dbns2/remain [1])
);
FDE \dbns2/store110_0 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0541_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_83_OUT<0> ),
.Q(\dbns2/store110 [0])
);
FDE \dbns2/store101_3 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0496_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<3> ),
.Q(\dbns2/store101 [3])
);
FDE \dbns2/store101_2 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0496_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<2> ),
.Q(\dbns2/store101 [2])
);
FDE \dbns2/store101_1 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0496_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<1> ),
.Q(\dbns2/store101 [1])
);
FDE \dbns2/store101_0 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0496_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<0> ),
.Q(\dbns2/store101 [0])
);
FDE \dbns2/store010_2 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0374_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_80_OUT<2> ),
.Q(\dbns2/store010[2] )
);
FDE \dbns2/store010_0 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0374_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_80_OUT<0> ),
.Q(\dbns2/store010[0] )
);
FDE \dbns2/store001_3 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0329_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<3> ),
.Q(\dbns2/store001 [3])
);
FDE \dbns2/store001_2 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0329_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<2> ),
.Q(\dbns2/store001 [2])
);
FDE \dbns2/store001_1 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0329_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<1> ),
.Q(\dbns2/store001 [1])
);
FDE \dbns2/store001_0 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0329_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<0> ),
.Q(\dbns2/store001 [0])
);
FDE \dbns2/store100_3 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0435_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<3> ),
.Q(\dbns2/store100 [3])
);
FDE \dbns2/store100_2 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0435_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<2> ),
.Q(\dbns2/store100 [2])
);
FDE \dbns2/store100_1 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0435_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<1> ),
.Q(\dbns2/store100 [1])
);
FDE \dbns2/store100_0 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0435_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<0> ),
.Q(\dbns2/store100 [0])
);
FDE \dbns2/store000_1 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0268_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_78_OUT<1> ),
.Q(\dbns2/store000 [1])
);
FDE \dbns2/store000_0 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0268_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_78_OUT<0> ),
.Q(\dbns2/store000 [0])
);
FDE \dbns2/r1_4 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0207_inv_93 ),
.D(\dbns2/r1[4]_GND_2_o_mux_65_OUT<4> ),
.Q(\dbns2/r1 [4])
);
FDE \dbns2/r1_3 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0207_inv_93 ),
.D(\dbns2/r1[4]_GND_2_o_mux_65_OUT<3> ),
.Q(\dbns2/r1 [3])
);
FDE \dbns2/r1_2 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0207_inv_93 ),
.D(\dbns2/r1[4]_GND_2_o_mux_65_OUT<2> ),
.Q(\dbns2/r1 [2])
);
FDE \dbns2/r1_1 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0207_inv_93 ),
.D(\dbns2/r1[4]_GND_2_o_mux_65_OUT<1> ),
.Q(\dbns2/r1 [1])
);
FDE \dbns2/r1_0 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0207_inv_93 ),
.D(\dbns2/r1[4]_GND_2_o_mux_65_OUT<0> ),
.Q(\dbns2/r1 [0])
);
FDRE #(
.INIT ( 1'b0 ))
\dbns2/shift_2 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0557_inv ),
.D(\dbns2/PWR_2_o_b[4]_AND_1_o21 ),
.R(\dbns2/_n0198_123 ),
.Q(\dbns2/shift [2])
);
FDRE #(
.INIT ( 1'b0 ))
\dbns2/shift_1 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0557_inv ),
.D(\dbns2/PWR_2_o_GND_2_o_mux_47_OUT [1]),
.R(\dbns2/_n0198_123 ),
.Q(\dbns2/shift [1])
);
FDRE #(
.INIT ( 1'b0 ))
\dbns2/shift_0 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0557_inv ),
.D(\dbns2/PWR_2_o_GND_2_o_mux_47_OUT [0]),
.R(\dbns2/_n0198_123 ),
.Q(\dbns2/shift [0])
);
FD \dbns2/b_4 (
.C(clock_BUFGP_10),
.D(\dbns2/b[4]_a[4]_mux_69_OUT<4> ),
.Q(\dbns2/b [4])
);
FD \dbns2/b_3 (
.C(clock_BUFGP_10),
.D(\dbns2/b[4]_a[4]_mux_69_OUT<3> ),
.Q(\dbns2/b [3])
);
FD \dbns2/b_2 (
.C(clock_BUFGP_10),
.D(\dbns2/b[4]_a[4]_mux_69_OUT<2> ),
.Q(\dbns2/b [2])
);
FD \dbns2/b_1 (
.C(clock_BUFGP_10),
.D(\dbns2/b[4]_a[4]_mux_69_OUT<1> ),
.Q(\dbns2/b [1])
);
FD \dbns2/b_0 (
.C(clock_BUFGP_10),
.D(\dbns2/b[4]_a[4]_mux_69_OUT<0> ),
.Q(\dbns2/b [0])
);
FDS #(
.INIT ( 1'b0 ))
\dbns2/count (
.C(clock_BUFGP_10),
.D(\dbns2/count_210 ),
.S(\dbns1/count_inv ),
.Q(\dbns2/count_210 )
);
FDRE #(
.INIT ( 1'b0 ))
\dbns1/remain_0 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0555_inv_160 ),
.D(\dbns1/Result [0]),
.R(\dbns1/count_inv ),
.Q(\dbns1/remain [0])
);
FDSE #(
.INIT ( 1'b1 ))
\dbns1/remain_2 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0555_inv_160 ),
.D(\dbns1/Result [2]),
.S(\dbns1/count_inv ),
.Q(\dbns1/remain [2])
);
FDRE #(
.INIT ( 1'b0 ))
\dbns1/remain_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0555_inv_160 ),
.D(\dbns1/Result [1]),
.R(\dbns1/count_inv ),
.Q(\dbns1/remain [1])
);
FDE \dbns1/store110_0 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0541_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_83_OUT<0> ),
.Q(\dbns1/store110 [0])
);
FDE \dbns1/store101_3 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0496_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<3> ),
.Q(\dbns1/store101 [3])
);
FDE \dbns1/store101_2 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0496_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<2> ),
.Q(\dbns1/store101 [2])
);
FDE \dbns1/store101_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0496_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<1> ),
.Q(\dbns1/store101 [1])
);
FDE \dbns1/store101_0 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0496_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<0> ),
.Q(\dbns1/store101 [0])
);
FDE \dbns1/store010_2 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0374_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_80_OUT<2> ),
.Q(\dbns1/store010[2] )
);
FDE \dbns1/store010_0 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0374_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_80_OUT<0> ),
.Q(\dbns1/store010[0] )
);
FDE \dbns1/store001_3 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0329_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<3> ),
.Q(\dbns1/store001 [3])
);
FDE \dbns1/store001_2 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0329_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<2> ),
.Q(\dbns1/store001 [2])
);
FDE \dbns1/store001_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0329_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<1> ),
.Q(\dbns1/store001 [1])
);
FDE \dbns1/store001_0 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0329_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<0> ),
.Q(\dbns1/store001 [0])
);
FDE \dbns1/store100_3 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0435_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<3> ),
.Q(\dbns1/store100 [3])
);
FDE \dbns1/store100_2 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0435_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<2> ),
.Q(\dbns1/store100 [2])
);
FDE \dbns1/store100_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0435_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<1> ),
.Q(\dbns1/store100 [1])
);
FDE \dbns1/store100_0 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0435_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<0> ),
.Q(\dbns1/store100 [0])
);
FDE \dbns1/store000_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0268_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_78_OUT<1> ),
.Q(\dbns1/store000 [1])
);
FDE \dbns1/store000_0 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0268_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_78_OUT<0> ),
.Q(\dbns1/store000 [0])
);
FDE \dbns1/r1_4 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0207_inv_167 ),
.D(\dbns1/r1[4]_GND_2_o_mux_65_OUT<4> ),
.Q(\dbns1/r1 [4])
);
FDE \dbns1/r1_3 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0207_inv_167 ),
.D(\dbns1/r1[4]_GND_2_o_mux_65_OUT<3> ),
.Q(\dbns1/r1 [3])
);
FDE \dbns1/r1_2 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0207_inv_167 ),
.D(\dbns1/r1[4]_GND_2_o_mux_65_OUT<2> ),
.Q(\dbns1/r1 [2])
);
FDE \dbns1/r1_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0207_inv_167 ),
.D(\dbns1/r1[4]_GND_2_o_mux_65_OUT<1> ),
.Q(\dbns1/r1 [1])
);
FDE \dbns1/r1_0 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0207_inv_167 ),
.D(\dbns1/r1[4]_GND_2_o_mux_65_OUT<0> ),
.Q(\dbns1/r1 [0])
);
FDRE #(
.INIT ( 1'b0 ))
\dbns1/shift_2 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0557_inv ),
.D(\dbns1/PWR_2_o_b[4]_AND_1_o21 ),
.R(\dbns1/_n0198_198 ),
.Q(\dbns1/shift [2])
);
FDRE #(
.INIT ( 1'b0 ))
\dbns1/shift_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0557_inv ),
.D(\dbns1/PWR_2_o_GND_2_o_mux_47_OUT [1]),
.R(\dbns1/_n0198_198 ),
.Q(\dbns1/shift [1])
);
FDRE #(
.INIT ( 1'b0 ))
\dbns1/shift_0 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0557_inv ),
.D(\dbns1/PWR_2_o_GND_2_o_mux_47_OUT [0]),
.R(\dbns1/_n0198_198 ),
.Q(\dbns1/shift [0])
);
FD \dbns1/b_4 (
.C(clock_BUFGP_10),
.D(\dbns1/b[4]_a[4]_mux_69_OUT<4> ),
.Q(\dbns1/b [4])
);
FD \dbns1/b_3 (
.C(clock_BUFGP_10),
.D(\dbns1/b[4]_a[4]_mux_69_OUT<3> ),
.Q(\dbns1/b [3])
);
FD \dbns1/b_2 (
.C(clock_BUFGP_10),
.D(\dbns1/b[4]_a[4]_mux_69_OUT<2> ),
.Q(\dbns1/b [2])
);
FD \dbns1/b_1 (
.C(clock_BUFGP_10),
.D(\dbns1/b[4]_a[4]_mux_69_OUT<1> ),
.Q(\dbns1/b [1])
);
FD \dbns1/b_0 (
.C(clock_BUFGP_10),
.D(\dbns1/b[4]_a[4]_mux_69_OUT<0> ),
.Q(\dbns1/b [0])
);
FDE \addn_1/case110/out_1 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case110/out[3]_input2[3]_mux_204_OUT<1> ),
.Q(\addn_1/case110/out [1])
);
FDE \addn_1/case110/out_0 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case110/out[3]_input2[3]_mux_204_OUT<0> ),
.Q(\addn_1/case110/out [0])
);
FDE \addn_1/case101/out_3 (
.C(clock_BUFGP_10),
.CE(\addn_1/case101/_n0269_inv ),
.D(\addn_1/case101/out[3]_input2[3]_mux_204_OUT<3> ),
.Q(\addn_1/case101/out [3])
);
FDE \addn_1/case101/out_2 (
.C(clock_BUFGP_10),
.CE(\addn_1/case101/_n0269_inv ),
.D(\addn_1/case101/out[3]_input2[3]_mux_204_OUT<2> ),
.Q(\addn_1/case101/out [2])
);
FDE \addn_1/case101/out_1 (
.C(clock_BUFGP_10),
.CE(\addn_1/case101/_n0269_inv ),
.D(\addn_1/case101/out[3]_input2[3]_mux_204_OUT<1> ),
.Q(\addn_1/case101/out [1])
);
FDE \addn_1/case101/out_0 (
.C(clock_BUFGP_10),
.CE(\addn_1/case101/_n0269_inv ),
.D(\addn_1/case101/out[3]_input2[3]_mux_204_OUT<0> ),
.Q(\addn_1/case101/out [0])
);
FDE \addn_1/case101/cout_1 (
.C(clock_BUFGP_10),
.CE(\addn_1/case101/_n0269_inv ),
.D(\addn_1/case101/cout[1]_input2[3]_mux_205_OUT<1> ),
.Q(\addn_1/case101/cout [1])
);
FDE \addn_1/case101/cout_0 (
.C(clock_BUFGP_10),
.CE(\addn_1/case101/_n0269_inv ),
.D(\addn_1/case101/cout[1]_input2[3]_mux_205_OUT<0> ),
.Q(\addn_1/case101/cout [0])
);
FDE \addn_1/case100/out_3 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case100/out[3]_input2[3]_mux_204_OUT<3> ),
.Q(\addn_1/case100/out [3])
);
FDE \addn_1/case100/out_2 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case100/out[3]_input2[3]_mux_204_OUT<2> ),
.Q(\addn_1/case100/out [2])
);
FDE \addn_1/case100/out_1 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case100/out[3]_input2[3]_mux_204_OUT<1> ),
.Q(\addn_1/case100/out [1])
);
FDE \addn_1/case100/out_0 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case100/out[3]_input2[3]_mux_204_OUT<0> ),
.Q(\addn_1/case100/out [0])
);
FDE \addn_1/case100/cout_1 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case100/cout[1]_input2[3]_mux_205_OUT<1> ),
.Q(\addn_1/case100/cout [1])
);
FDE \addn_1/case100/cout_0 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case100/cout[1]_input2[3]_mux_205_OUT<0> ),
.Q(\addn_1/case100/cout [0])
);
FDE \addn_1/case010/out_3 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case010/out[3]_input2[3]_mux_204_OUT<3> ),
.Q(\addn_1/case010/out [3])
);
FDE \addn_1/case010/out_2 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case010/out[3]_input2[3]_mux_204_OUT<2> ),
.Q(\addn_1/case010/out [2])
);
FDE \addn_1/case010/out_1 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case010/out[3]_input2[3]_mux_204_OUT<1> ),
.Q(\addn_1/case010/out [1])
);
FDE \addn_1/case010/out_0 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case010/out[3]_input2[3]_mux_204_OUT<0> ),
.Q(\addn_1/case010/out [0])
);
FDE \addn_1/case001/out_3 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case001/out[3]_input2[3]_mux_204_OUT<3> ),
.Q(\addn_1/case001/out [3])
);
FDE \addn_1/case001/out_2 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case001/out[3]_input2[3]_mux_204_OUT<2> ),
.Q(\addn_1/case001/out [2])
);
FDE \addn_1/case001/out_1 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case001/out[3]_input2[3]_mux_204_OUT<1> ),
.Q(\addn_1/case001/out [1])
);
FDE \addn_1/case001/out_0 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case001/out[3]_input2[3]_mux_204_OUT<0> ),
.Q(\addn_1/case001/out [0])
);
FDE \addn_1/case001/cout_1 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case001/cout[1]_input2[3]_mux_205_OUT<1> ),
.Q(\addn_1/case001/cout [1])
);
FDE \addn_1/case001/cout_0 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case001/cout[1]_input2[3]_mux_205_OUT<0> ),
.Q(\addn_1/case001/cout [0])
);
FDE \addn_1/case000/out_3 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case000/out[3]_input2[3]_mux_204_OUT<3> ),
.Q(\addn_1/case000/out [3])
);
FDE \addn_1/case000/out_2 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case000/out[3]_input2[3]_mux_204_OUT<2> ),
.Q(\addn_1/case000/out [2])
);
FDE \addn_1/case000/out_1 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case000/out[3]_input2[3]_mux_204_OUT<1> ),
.Q(\addn_1/case000/out [1])
);
FDE \addn_1/case000/out_0 (
.C(clock_BUFGP_10),
.CE(N1),
.D(\addn_1/case000/out[3]_input2[3]_mux_204_OUT<0> ),
.Q(\addn_1/case000/out [0])
);
LUT4 #(
.INIT ( 16'hADA8 ))
\dbns2/_n0435_inv1 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [0]),
.I2(\dbns2/r1 [1]),
.I3(\dbns2/r1 [4]),
.O(\dbns2/_n0435_inv )
);
LUT4 #(
.INIT ( 16'hECA8 ))
\dbns2/_n0496_inv1 (
.I0(\dbns2/r1 [1]),
.I1(\dbns2/r1 [2]),
.I2(\dbns2/r1 [4]),
.I3(\dbns2/r1 [0]),
.O(\dbns2/_n0496_inv )
);
LUT4 #(
.INIT ( 16'hA8EC ))
\dbns2/_n0329_inv1 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [1]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [4]),
.O(\dbns2/_n0329_inv )
);
LUT4 #(
.INIT ( 16'hA8AD ))
\dbns2/_n0268_inv1 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [0]),
.I2(\dbns2/r1 [1]),
.I3(\dbns2/r1 [4]),
.O(\dbns2/_n0268_inv )
);
LUT5 #(
.INIT ( 32'h11111000 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_79_OUT41 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store001 [3]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<3> )
);
LUT5 #(
.INIT ( 32'h44444000 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_82_OUT41 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store101 [3]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<3> )
);
LUT5 #(
.INIT ( 32'h44444000 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_81_OUT41 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store100 [3]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<3> )
);
LUT5 #(
.INIT ( 32'h11110100 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_79_OUT31 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store001 [2]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<2> )
);
LUT5 #(
.INIT ( 32'h44440400 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_82_OUT31 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store101 [2]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<2> )
);
LUT5 #(
.INIT ( 32'h44440400 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_81_OUT31 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store100 [2]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<2> )
);
LUT5 #(
.INIT ( 32'h11110100 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_79_OUT21 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [3]),
.I3(\dbns2/r1 [0]),
.I4(\dbns2/store001 [1]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<1> )
);
LUT5 #(
.INIT ( 32'h11110100 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_78_OUT21 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [3]),
.I3(\dbns2/r1 [0]),
.I4(\dbns2/store000 [1]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_78_OUT<1> )
);
LUT5 #(
.INIT ( 32'h44440400 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_82_OUT21 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [3]),
.I3(\dbns2/r1 [0]),
.I4(\dbns2/store101 [1]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<1> )
);
LUT5 #(
.INIT ( 32'h44440400 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_81_OUT21 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [3]),
.I3(\dbns2/r1 [0]),
.I4(\dbns2/store100 [1]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<1> )
);
LUT5 #(
.INIT ( 32'h11110001 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_79_OUT11 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store001 [0]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_79_OUT<0> )
);
LUT5 #(
.INIT ( 32'h11110001 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_78_OUT11 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store000 [0]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_78_OUT<0> )
);
LUT5 #(
.INIT ( 32'h44440004 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_82_OUT11 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store101 [0]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<0> )
);
LUT5 #(
.INIT ( 32'h44440004 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_81_OUT11 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [4]),
.I2(\dbns2/r1 [0]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store100 [0]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_81_OUT<0> )
);
LUT5 #(
.INIT ( 32'h10100010 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_83_OUT11 (
.I0(\dbns2/r1 [0]),
.I1(\dbns2/r1 [1]),
.I2(\dbns2/r1 [4]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store110 [0]),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_83_OUT<0> )
);
LUT4 #(
.INIT ( 16'hAA8A ))
\dbns2/_n0374_inv1 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [1]),
.I2(\dbns2/r1 [4]),
.I3(\dbns2/r1 [0]),
.O(\dbns2/_n0374_inv )
);
LUT5 #(
.INIT ( 32'h01010001 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_80_OUT11 (
.I0(\dbns2/r1 [0]),
.I1(\dbns2/r1 [1]),
.I2(\dbns2/r1 [4]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store010[0] ),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_80_OUT<0> )
);
LUT5 #(
.INIT ( 32'h01010100 ))
\dbns2/Mmux_r1[4]_GND_2_o_wide_mux_80_OUT31 (
.I0(\dbns2/r1 [0]),
.I1(\dbns2/r1 [1]),
.I2(\dbns2/r1 [4]),
.I3(\dbns2/r1 [3]),
.I4(\dbns2/store010[2] ),
.O(\dbns2/r1[4]_GND_2_o_wide_mux_80_OUT<2> )
);
LUT4 #(
.INIT ( 16'hAAA8 ))
\dbns2/_n0541_inv1 (
.I0(\dbns2/r1 [2]),
.I1(\dbns2/r1 [0]),
.I2(\dbns2/r1 [1]),
.I3(\dbns2/r1 [4]),
.O(\dbns2/_n0541_inv )
);
LUT5 #(
.INIT ( 32'hAAAA696A ))
\dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT21 (
.I0(\dbns2/remain [1]),
.I1(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I2(\dbns2/remain [0]),
.I3(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I4(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns2/r1[4]_GND_2_o_mux_65_OUT<1> )
);
LUT6 #(
.INIT ( 64'hA9AAA99999A99999 ))
\dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT31 (
.I0(\dbns2/remain [2]),
.I1(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.I2(\dbns2/remain [1]),
.I3(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I4(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I5(\dbns2/remain [0]),
.O(\dbns2/r1[4]_GND_2_o_mux_65_OUT<2> )
);
LUT4 #(
.INIT ( 16'h999A ))
\dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT11 (
.I0(\dbns2/remain [0]),
.I1(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.I2(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I3(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.O(\dbns2/r1[4]_GND_2_o_mux_65_OUT<0> )
);
LUT6 #(
.INIT ( 64'h8880000088000000 ))
\dbns2/PWR_2_o_PWR_2_o_AND_6_o1 (
.I0(\dbns2/remain [2]),
.I1(\dbns2/b [4]),
.I2(\dbns2/b [0]),
.I3(\dbns2/b [2]),
.I4(\dbns2/b [3]),
.I5(\dbns2/b [1]),
.O(\dbns2/PWR_2_o_PWR_2_o_AND_6_o )
);
LUT4 #(
.INIT ( 16'hD782 ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT31 (
.I0(\dbns2/count_210 ),
.I1(\dbns2/Mmux_b[4]_a[4]_mux_69_OUT51 ),
.I2(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.I3(a2_2_IBUF_7),
.O(\dbns2/b[4]_a[4]_mux_69_OUT<2> )
);
LUT6 #(
.INIT ( 64'h222EEEEE222E2222 ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT41 (
.I0(a2_3_IBUF_6),
.I1(\dbns2/count_210 ),
.I2(\dbns2/Mmux_b[4]_a[4]_mux_69_OUT51 ),
.I3(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.I4(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> ),
.I5(\dbns2/Mmux_b[4]_a[4]_mux_69_OUT52_72 ),
.O(\dbns2/b[4]_a[4]_mux_69_OUT<3> )
);
LUT4 #(
.INIT ( 16'h5545 ))
\dbns2/Mmux_PWR_2_o_GND_2_o_mux_47_OUT21 (
.I0(\dbns2/b [3]),
.I1(\dbns2/b [2]),
.I2(\dbns2/b [0]),
.I3(\dbns2/b [1]),
.O(\dbns2/PWR_2_o_GND_2_o_mux_47_OUT [1])
);
LUT5 #(
.INIT ( 32'hAAAA0222 ))
\dbns2/PWR_2_o_b[4]_AND_1_o1 (
.I0(\dbns2/b [4]),
.I1(\dbns2/remain [2]),
.I2(\dbns2/remain [0]),
.I3(\dbns2/remain [1]),
.I4(\dbns2/PWR_2_o_b[4]_AND_1_o21 ),
.O(\dbns2/PWR_2_o_b[4]_AND_1_o )
);
LUT6 #(
.INIT ( 64'hAAAA8088FFFFFFFF ))
\dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT52 (
.I0(\dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT51 ),
.I1(\dbns2/b [1]),
.I2(\dbns2/b [0]),
.I3(\dbns2/b [3]),
.I4(\dbns2/b [2]),
.I5(\dbns2/b [4]),
.O(\dbns2/r1[4]_GND_2_o_mux_65_OUT<4> )
);
LUT5 #(
.INIT ( 32'h0A080000 ))
\dbns2/PWR_2_o_b[4]_AND_3_o1 (
.I0(\dbns2/b [4]),
.I1(\dbns2/b [2]),
.I2(\dbns2/b [3]),
.I3(\dbns2/b [1]),
.I4(\dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT51 ),
.O(\dbns2/PWR_2_o_b[4]_AND_3_o )
);
LUT3 #(
.INIT ( 8'h01 ))
\dbns2/PWR_2_o_b[4]_AND_1_o211 (
.I0(\dbns2/b [3]),
.I1(\dbns2/b [2]),
.I2(\dbns2/b [1]),
.O(\dbns2/PWR_2_o_b[4]_AND_1_o21 )
);
LUT2 #(
.INIT ( 4'h8 ))
\dbns2/_n0557_inv1 (
.I0(\dbns2/count_210 ),
.I1(\dbns2/_n0555_inv_86 ),
.O(\dbns2/_n0557_inv )
);
LUT3 #(
.INIT ( 8'hF8 ))
\dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT511 (
.I0(\dbns2/remain [0]),
.I1(\dbns2/remain [1]),
.I2(\dbns2/remain [2]),
.O(\dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT51 )
);
LUT3 #(
.INIT ( 8'h72 ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT11 (
.I0(\dbns2/count_210 ),
.I1(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> ),
.I2(a2_0_IBUF_9),
.O(\dbns2/b[4]_a[4]_mux_69_OUT<0> )
);
LUT3 #(
.INIT ( 8'hF4 ))
\dbns2/Mmux_PWR_2_o_GND_2_o_mux_47_OUT11 (
.I0(\dbns2/b [2]),
.I1(\dbns2/b [1]),
.I2(\dbns2/b [3]),
.O(\dbns2/PWR_2_o_GND_2_o_mux_47_OUT [0])
);
LUT4 #(
.INIT ( 16'hADA8 ))
\dbns1/_n0435_inv1 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [0]),
.I2(\dbns1/r1 [1]),
.I3(\dbns1/r1 [4]),
.O(\dbns1/_n0435_inv )
);
LUT4 #(
.INIT ( 16'hECA8 ))
\dbns1/_n0496_inv1 (
.I0(\dbns1/r1 [1]),
.I1(\dbns1/r1 [2]),
.I2(\dbns1/r1 [4]),
.I3(\dbns1/r1 [0]),
.O(\dbns1/_n0496_inv )
);
LUT4 #(
.INIT ( 16'hA8EC ))
\dbns1/_n0329_inv1 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [1]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [4]),
.O(\dbns1/_n0329_inv )
);
LUT4 #(
.INIT ( 16'hA8AD ))
\dbns1/_n0268_inv1 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [0]),
.I2(\dbns1/r1 [1]),
.I3(\dbns1/r1 [4]),
.O(\dbns1/_n0268_inv )
);
LUT5 #(
.INIT ( 32'h11111000 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_79_OUT41 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store001 [3]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<3> )
);
LUT5 #(
.INIT ( 32'h44444000 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_82_OUT41 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store101 [3]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<3> )
);
LUT5 #(
.INIT ( 32'h44444000 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_81_OUT41 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store100 [3]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<3> )
);
LUT5 #(
.INIT ( 32'h11110100 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_79_OUT31 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store001 [2]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<2> )
);
LUT5 #(
.INIT ( 32'h44440400 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_82_OUT31 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store101 [2]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<2> )
);
LUT5 #(
.INIT ( 32'h44440400 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_81_OUT31 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store100 [2]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<2> )
);
LUT5 #(
.INIT ( 32'h11110100 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_79_OUT21 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [3]),
.I3(\dbns1/r1 [0]),
.I4(\dbns1/store001 [1]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<1> )
);
LUT5 #(
.INIT ( 32'h11110100 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_78_OUT21 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [3]),
.I3(\dbns1/r1 [0]),
.I4(\dbns1/store000 [1]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_78_OUT<1> )
);
LUT5 #(
.INIT ( 32'h44440400 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_82_OUT21 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [3]),
.I3(\dbns1/r1 [0]),
.I4(\dbns1/store101 [1]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<1> )
);
LUT5 #(
.INIT ( 32'h44440400 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_81_OUT21 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [3]),
.I3(\dbns1/r1 [0]),
.I4(\dbns1/store100 [1]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<1> )
);
LUT5 #(
.INIT ( 32'h11110001 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_79_OUT11 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store001 [0]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_79_OUT<0> )
);
LUT5 #(
.INIT ( 32'h11110001 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_78_OUT11 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store000 [0]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_78_OUT<0> )
);
LUT5 #(
.INIT ( 32'h44440004 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_82_OUT11 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store101 [0]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<0> )
);
LUT5 #(
.INIT ( 32'h44440004 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_81_OUT11 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [4]),
.I2(\dbns1/r1 [0]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store100 [0]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_81_OUT<0> )
);
LUT5 #(
.INIT ( 32'h10100010 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_83_OUT11 (
.I0(\dbns1/r1 [0]),
.I1(\dbns1/r1 [1]),
.I2(\dbns1/r1 [4]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store110 [0]),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_83_OUT<0> )
);
LUT4 #(
.INIT ( 16'hAA8A ))
\dbns1/_n0374_inv1 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [1]),
.I2(\dbns1/r1 [4]),
.I3(\dbns1/r1 [0]),
.O(\dbns1/_n0374_inv )
);
LUT5 #(
.INIT ( 32'h01010001 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_80_OUT11 (
.I0(\dbns1/r1 [0]),
.I1(\dbns1/r1 [1]),
.I2(\dbns1/r1 [4]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store010[0] ),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_80_OUT<0> )
);
LUT5 #(
.INIT ( 32'h01010100 ))
\dbns1/Mmux_r1[4]_GND_2_o_wide_mux_80_OUT31 (
.I0(\dbns1/r1 [0]),
.I1(\dbns1/r1 [1]),
.I2(\dbns1/r1 [4]),
.I3(\dbns1/r1 [3]),
.I4(\dbns1/store010[2] ),
.O(\dbns1/r1[4]_GND_2_o_wide_mux_80_OUT<2> )
);
LUT4 #(
.INIT ( 16'hAAA8 ))
\dbns1/_n0541_inv1 (
.I0(\dbns1/r1 [2]),
.I1(\dbns1/r1 [0]),
.I2(\dbns1/r1 [1]),
.I3(\dbns1/r1 [4]),
.O(\dbns1/_n0541_inv )
);
LUT5 #(
.INIT ( 32'hAAAA696A ))
\dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT21 (
.I0(\dbns1/remain [1]),
.I1(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I2(\dbns1/remain [0]),
.I3(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I4(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns1/r1[4]_GND_2_o_mux_65_OUT<1> )
);
LUT6 #(
.INIT ( 64'hA9AAA99999A99999 ))
\dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT31 (
.I0(\dbns1/remain [2]),
.I1(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.I2(\dbns1/remain [1]),
.I3(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I4(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I5(\dbns1/remain [0]),
.O(\dbns1/r1[4]_GND_2_o_mux_65_OUT<2> )
);
LUT4 #(
.INIT ( 16'h999A ))
\dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT11 (
.I0(\dbns1/remain [0]),
.I1(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.I2(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I3(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.O(\dbns1/r1[4]_GND_2_o_mux_65_OUT<0> )
);
LUT6 #(
.INIT ( 64'h8880000088000000 ))
\dbns1/PWR_2_o_PWR_2_o_AND_6_o1 (
.I0(\dbns1/remain [2]),
.I1(\dbns1/b [4]),
.I2(\dbns1/b [0]),
.I3(\dbns1/b [2]),
.I4(\dbns1/b [3]),
.I5(\dbns1/b [1]),
.O(\dbns1/PWR_2_o_PWR_2_o_AND_6_o )
);
LUT4 #(
.INIT ( 16'hD782 ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT31 (
.I0(\dbns2/count_210 ),
.I1(\dbns1/Mmux_b[4]_a[4]_mux_69_OUT51 ),
.I2(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.I3(a1_2_IBUF_2),
.O(\dbns1/b[4]_a[4]_mux_69_OUT<2> )
);
LUT6 #(
.INIT ( 64'h222EEEEE222E2222 ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT41 (
.I0(a1_3_IBUF_1),
.I1(\dbns2/count_210 ),
.I2(\dbns1/Mmux_b[4]_a[4]_mux_69_OUT51 ),
.I3(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.I4(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> ),
.I5(\dbns1/Mmux_b[4]_a[4]_mux_69_OUT52_146 ),
.O(\dbns1/b[4]_a[4]_mux_69_OUT<3> )
);
LUT4 #(
.INIT ( 16'h5545 ))
\dbns1/Mmux_PWR_2_o_GND_2_o_mux_47_OUT21 (
.I0(\dbns1/b [3]),
.I1(\dbns1/b [2]),
.I2(\dbns1/b [0]),
.I3(\dbns1/b [1]),
.O(\dbns1/PWR_2_o_GND_2_o_mux_47_OUT [1])
);
LUT5 #(
.INIT ( 32'hAAAA0222 ))
\dbns1/PWR_2_o_b[4]_AND_1_o1 (
.I0(\dbns1/b [4]),
.I1(\dbns1/remain [2]),
.I2(\dbns1/remain [0]),
.I3(\dbns1/remain [1]),
.I4(\dbns1/PWR_2_o_b[4]_AND_1_o21 ),
.O(\dbns1/PWR_2_o_b[4]_AND_1_o )
);
LUT6 #(
.INIT ( 64'hAAAA8088FFFFFFFF ))
\dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT52 (
.I0(\dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT51 ),
.I1(\dbns1/b [1]),
.I2(\dbns1/b [0]),
.I3(\dbns1/b [3]),
.I4(\dbns1/b [2]),
.I5(\dbns1/b [4]),
.O(\dbns1/r1[4]_GND_2_o_mux_65_OUT<4> )
);
LUT5 #(
.INIT ( 32'h0A080000 ))
\dbns1/PWR_2_o_b[4]_AND_3_o1 (
.I0(\dbns1/b [4]),
.I1(\dbns1/b [2]),
.I2(\dbns1/b [3]),
.I3(\dbns1/b [1]),
.I4(\dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT51 ),
.O(\dbns1/PWR_2_o_b[4]_AND_3_o )
);
LUT3 #(
.INIT ( 8'h01 ))
\dbns1/PWR_2_o_b[4]_AND_1_o211 (
.I0(\dbns1/b [3]),
.I1(\dbns1/b [2]),
.I2(\dbns1/b [1]),
.O(\dbns1/PWR_2_o_b[4]_AND_1_o21 )
);
LUT2 #(
.INIT ( 4'h8 ))
\dbns1/_n0557_inv1 (
.I0(\dbns2/count_210 ),
.I1(\dbns1/_n0555_inv_160 ),
.O(\dbns1/_n0557_inv )
);
LUT3 #(
.INIT ( 8'hF8 ))
\dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT511 (
.I0(\dbns1/remain [0]),
.I1(\dbns1/remain [1]),
.I2(\dbns1/remain [2]),
.O(\dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT51 )
);
LUT3 #(
.INIT ( 8'h72 ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT11 (
.I0(\dbns2/count_210 ),
.I1(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> ),
.I2(a1_0_IBUF_4),
.O(\dbns1/b[4]_a[4]_mux_69_OUT<0> )
);
LUT3 #(
.INIT ( 8'hF4 ))
\dbns1/Mmux_PWR_2_o_GND_2_o_mux_47_OUT11 (
.I0(\dbns1/b [2]),
.I1(\dbns1/b [1]),
.I2(\dbns1/b [3]),
.O(\dbns1/PWR_2_o_GND_2_o_mux_47_OUT [0])
);
LUT2 #(
.INIT ( 4'h8 ))
\addn_1/case110/Mmux_out[3]_input2[3]_mux_204_OUT21 (
.I0(\dbns1/store110 [0]),
.I1(\dbns2/store110 [0]),
.O(\addn_1/case110/out[3]_input2[3]_mux_204_OUT<1> )
);
LUT2 #(
.INIT ( 4'h6 ))
\addn_1/case110/Mmux_out[3]_input2[3]_mux_204_OUT11 (
.I0(\dbns2/store110 [0]),
.I1(\dbns1/store110 [0]),
.O(\addn_1/case110/out[3]_input2[3]_mux_204_OUT<0> )
);
LUT4 #(
.INIT ( 16'h2000 ))
\addn_1/case101/input1[3]_PWR_6_o_equal_37_o<3>1 (
.I0(\dbns1/store101 [2]),
.I1(\dbns1/store101 [1]),
.I2(\dbns1/store101 [0]),
.I3(\dbns1/store101 [3]),
.O(\addn_1/case101/input1[3]_PWR_6_o_equal_37_o )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case101/input1[3]_PWR_6_o_equal_27_o<3>1 (
.I0(\dbns1/store101 [2]),
.I1(\dbns1/store101 [1]),
.I2(\dbns1/store101 [0]),
.I3(\dbns1/store101 [3]),
.O(\addn_1/case101/input1[3]_PWR_6_o_equal_27_o )
);
LUT4 #(
.INIT ( 16'h0140 ))
\addn_1/case101/input1[3]_input1[3]_OR_6_o1 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [0]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [2]),
.O(\addn_1/case101/input1[3]_input1[3]_OR_6_o )
);
LUT4 #(
.INIT ( 16'h0280 ))
\addn_1/case101/input1[3]_input1[3]_OR_8_o1 (
.I0(\dbns1/store101_3_1_607 ),
.I1(\dbns1/store101_0_2_610 ),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [2]),
.O(\addn_1/case101/input1[3]_input1[3]_OR_8_o )
);
LUT4 #(
.INIT ( 16'h0180 ))
\addn_1/case101/input1[3]_input1[3]_OR_7_o1 (
.I0(\dbns1/store101_0_1_606 ),
.I1(\dbns1/store101_1_1_608 ),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [3]),
.O(\addn_1/case101/input1[3]_input1[3]_OR_7_o )
);
LUT4 #(
.INIT ( 16'hE01E ))
\addn_1/case101/_n0296<23>1 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [1]),
.I2(\dbns2/store101 [2]),
.I3(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296[23] )
);
LUT3 #(
.INIT ( 8'h86 ))
\addn_1/case101/_n0296<17>1 (
.I0(\dbns2/store101 [1]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296[17] )
);
LUT3 #(
.INIT ( 8'h18 ))
\addn_1/case101/_n0296<34>1 (
.I0(\dbns2/store101 [1]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296[34] )
);
LUT4 #(
.INIT ( 16'h7807 ))
\addn_1/case101/_n0296<29>1 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [1]),
.I2(\dbns2/store101 [2]),
.I3(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296[29] )
);
LUT3 #(
.INIT ( 8'h61 ))
\addn_1/case101/_n0296<16>1 (
.I0(\dbns2/store101 [1]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296[16] )
);
LUT4 #(
.INIT ( 16'h2444 ))
\addn_1/case101/_n0296<28>1 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.I2(\dbns2/store101 [1]),
.I3(\dbns2/store101 [0]),
.O(\addn_1/case101/_n0296[28] )
);
LUT3 #(
.INIT ( 8'h7E ))
\addn_1/case101/_n0296<36>1 (
.I0(\dbns2/store101 [1]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296[36] )
);
LUT4 #(
.INIT ( 16'h4449 ))
\addn_1/case101/_n0296<22>1 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.I2(\dbns2/store101 [1]),
.I3(\dbns2/store101 [0]),
.O(\addn_1/case101/_n0296[22] )
);
LUT4 #(
.INIT ( 16'h9222 ))
\addn_1/case101/_n0296<46>1 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.I2(\dbns2/store101 [1]),
.I3(\dbns2/store101 [0]),
.O(\addn_1/case101/_n0296[46] )
);
LUT4 #(
.INIT ( 16'h2224 ))
\addn_1/case101/_n0296<40>3 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.I2(\dbns2/store101 [1]),
.I3(\dbns2/store101 [0]),
.O(\addn_1/case101/_n0296[40] )
);
LUT6 #(
.INIT ( 64'h88AA880ACCFFCC0F ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT231 (
.I0(\addn_1/case101/_n0296[18] ),
.I1(\addn_1/case101/_n0296[55] ),
.I2(\addn_1/case101/input1[3]_PWR_6_o_equal_37_o ),
.I3(\addn_1/case101/input1[3]_input1[3]_OR_8_o ),
.I4(\addn_1/case101/_n0296[10] ),
.I5(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT102 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT23_238 )
);
LUT6 #(
.INIT ( 64'hE4F50000E4F5E4F5 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT221 (
.I0(\addn_1/case101/input1[3]_input1[3]_OR_8_o ),
.I1(\addn_1/case101/_n0296[55] ),
.I2(\addn_1/case101/_n0296[49] ),
.I3(\addn_1/case101/input1[3]_PWR_6_o_equal_37_o ),
.I4(\addn_1/case101/_n0296[12] ),
.I5(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT102 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT22_241 )
);
LUT3 #(
.INIT ( 8'hA8 ))
\addn_1/case101/_n0296<55>1 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101_1_1_609 ),
.I2(\dbns2/store101 [2]),
.O(\addn_1/case101/_n0296[55] )
);
LUT4 #(
.INIT ( 16'hAA80 ))
\addn_1/case101/_n0296<49>1 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [1]),
.I3(\dbns2/store101 [2]),
.O(\addn_1/case101/_n0296[49] )
);
LUT3 #(
.INIT ( 8'hFE ))
\addn_1/case101/_n0296<40>21 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [1]),
.O(\addn_1/case101/_n0296<40>2 )
);
LUT2 #(
.INIT ( 4'hE ))
\addn_1/case101/_n0296<42>11 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296<42>1 )
);
LUT2 #(
.INIT ( 4'h7 ))
\addn_1/case101/_n0296<30>11 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296<30>1 )
);
LUT3 #(
.INIT ( 8'hF8 ))
\addn_1/case101/_n0296<18>1 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [1]),
.I2(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296[18] )
);
LUT2 #(
.INIT ( 4'h2 ))
\addn_1/case101/_n0296<20>1 (
.I0(\dbns2/store101 [1]),
.I1(\dbns2/store101 [0]),
.O(\addn_1/case101/_n0296[20] )
);
LUT2 #(
.INIT ( 4'h2 ))
\addn_1/case101/_n0296<26>1 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [1]),
.O(\addn_1/case101/_n0296[26] )
);
LUT2 #(
.INIT ( 4'h7 ))
\addn_1/case101/_n0269_inv1 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case001/cout [0]),
.O(\addn_1/case101/_n0269_inv )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case101/input1[3]_GND_4_o_equal_17_o<3>1 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [1]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [0]),
.O(\addn_1/case101/input1[3]_GND_4_o_equal_17_o )
);
LUT2 #(
.INIT ( 4'hE ))
\addn_1/case101/_n0241<3>1 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.O(\addn_1/case101/_n0241 )
);
LUT4 #(
.INIT ( 16'h2000 ))
\addn_1/case100/input1[3]_PWR_6_o_equal_37_o<3>1 (
.I0(\dbns1/store100 [2]),
.I1(\dbns1/store100 [1]),
.I2(\dbns1/store100 [0]),
.I3(\dbns1/store100 [3]),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT113 )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case100/input1[3]_PWR_6_o_equal_27_o<3>1 (
.I0(\dbns1/store100 [2]),
.I1(\dbns1/store100 [1]),
.I2(\dbns1/store100 [0]),
.I3(\dbns1/store100 [3]),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT116 )
);
LUT4 #(
.INIT ( 16'h0140 ))
\addn_1/case100/input1[3]_input1[3]_OR_6_o1 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [0]),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [2]),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT34_297 )
);
LUT4 #(
.INIT ( 16'h2000 ))
\addn_1/case100/input1[3]_PWR_6_o_equal_40_o<3>1 (
.I0(\dbns1/store100 [1]),
.I1(\dbns1/store100 [0]),
.I2(\dbns1/store100 [2]),
.I3(\dbns1/store100 [3]),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT111 )
);
LUT4 #(
.INIT ( 16'h0180 ))
\addn_1/case100/input1[3]_input1[3]_OR_7_o1 (
.I0(\dbns1/store100 [0]),
.I1(\dbns1/store100 [1]),
.I2(\dbns1/store100 [2]),
.I3(\dbns1/store100 [3]),
.O(\addn_1/case100/input1[3]_input1[3]_OR_7_o )
);
LUT4 #(
.INIT ( 16'hE01E ))
\addn_1/case100/_n0296<23>1 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [1]),
.I2(\dbns2/store100 [2]),
.I3(\dbns2/store100 [3]),
.O(\addn_1/case100/_n0296[23] )
);
LUT3 #(
.INIT ( 8'h86 ))
\addn_1/case100/_n0296<17>1 (
.I0(\dbns2/store100 [1]),
.I1(\dbns2/store100 [2]),
.I2(\dbns2/store100 [3]),
.O(\addn_1/case100/_n0296[17] )
);
LUT3 #(
.INIT ( 8'h18 ))
\addn_1/case100/_n0296<34>1 (
.I0(\dbns2/store100 [1]),
.I1(\dbns2/store100 [2]),
.I2(\dbns2/store100 [3]),
.O(\addn_1/case100/_n0296[34] )
);
LUT4 #(
.INIT ( 16'h7807 ))
\addn_1/case100/_n0296<29>1 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [1]),
.I2(\dbns2/store100 [2]),
.I3(\dbns2/store100 [3]),
.O(\addn_1/case100/_n0296[29] )
);
LUT3 #(
.INIT ( 8'h61 ))
\addn_1/case100/_n0296<16>1 (
.I0(\dbns2/store100 [1]),
.I1(\dbns2/store100 [2]),
.I2(\dbns2/store100 [3]),
.O(\addn_1/case100/_n0296[16] )
);
LUT4 #(
.INIT ( 16'h4449 ))
\addn_1/case100/_n0296<22>1 (
.I0(\dbns2/store100 [2]),
.I1(\dbns2/store100 [3]),
.I2(\dbns2/store100 [1]),
.I3(\dbns2/store100 [0]),
.O(\addn_1/case100/_n0296[22] )
);
LUT4 #(
.INIT ( 16'h9222 ))
\addn_1/case100/_n0296<46>1 (
.I0(\dbns2/store100 [2]),
.I1(\dbns2/store100 [3]),
.I2(\dbns2/store100 [1]),
.I3(\dbns2/store100 [0]),
.O(\addn_1/case100/_n0296[46] )
);
LUT4 #(
.INIT ( 16'h2224 ))
\addn_1/case100/_n0296<40>3 (
.I0(\dbns2/store100 [2]),
.I1(\dbns2/store100 [3]),
.I2(\dbns2/store100 [1]),
.I3(\dbns2/store100 [0]),
.O(\addn_1/case100/_n0296[40] )
);
LUT6 #(
.INIT ( 64'h008000CC8080FFFF ))
\addn_1/case100/SF21 (
.I0(\dbns2/store100 [2]),
.I1(\dbns2/store100 [3]),
.I2(\addn_1/case100/_n0296<40>1 ),
.I3(\addn_1/case100/_n0296<66>1 ),
.I4(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.I5(\addn_1/case100/input1[3]_input1[3]_OR_7_o ),
.O(\addn_1/case100/SF2 )
);
LUT3 #(
.INIT ( 8'h7F ))
\addn_1/case100/_n0296<66>11 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [1]),
.I2(\dbns2/store100 [2]),
.O(\addn_1/case100/_n0296<66>1 )
);
LUT3 #(
.INIT ( 8'hFE ))
\addn_1/case100/_n0296<40>21 (
.I0(\dbns2/store100 [2]),
.I1(\dbns2/store100 [0]),
.I2(\dbns2/store100 [1]),
.O(\addn_1/case100/_n0296<40>2 )
);
LUT2 #(
.INIT ( 4'hE ))
\addn_1/case100/_n0296<42>11 (
.I0(\dbns2/store100 [2]),
.I1(\dbns2/store100 [3]),
.O(\addn_1/case100/_n0296<42>1 )
);
LUT2 #(
.INIT ( 4'hE ))
\addn_1/case100/_n0296<40>11 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [1]),
.O(\addn_1/case100/_n0296<40>1 )
);
LUT2 #(
.INIT ( 4'h7 ))
\addn_1/case100/_n0296<30>11 (
.I0(\dbns2/store100 [2]),
.I1(\dbns2/store100 [3]),
.O(\addn_1/case100/_n0296<30>1 )
);
LUT2 #(
.INIT ( 4'h2 ))
\addn_1/case100/_n0296<20>1 (
.I0(\dbns2/store100 [1]),
.I1(\dbns2/store100 [0]),
.O(\addn_1/case100/_n0296[20] )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case100/input1[3]_GND_4_o_equal_17_o<3>1 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [1]),
.I2(\dbns1/store100 [2]),
.I3(\dbns1/store100 [0]),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT33_300 )
);
LUT2 #(
.INIT ( 4'hE ))
\addn_1/case100/_n0241<3>1 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [2]),
.O(\addn_1/case100/_n0241 )
);
LUT4 #(
.INIT ( 16'h2000 ))
\addn_1/case001/input1[3]_PWR_6_o_equal_37_o<3>1 (
.I0(\dbns1/store001 [2]),
.I1(\dbns1/store001 [1]),
.I2(\dbns1/store001 [0]),
.I3(\dbns1/store001 [3]),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT113 )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case001/input1[3]_PWR_6_o_equal_27_o<3>1 (
.I0(\dbns1/store001 [2]),
.I1(\dbns1/store001 [1]),
.I2(\dbns1/store001 [0]),
.I3(\dbns1/store001 [3]),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT116 )
);
LUT4 #(
.INIT ( 16'h0140 ))
\addn_1/case001/input1[3]_input1[3]_OR_6_o1 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [0]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [2]),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT34_341 )
);
LUT4 #(
.INIT ( 16'h2000 ))
\addn_1/case001/input1[3]_PWR_6_o_equal_40_o<3>1 (
.I0(\dbns1/store001 [1]),
.I1(\dbns1/store001 [0]),
.I2(\dbns1/store001 [2]),
.I3(\dbns1/store001 [3]),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT111 )
);
LUT4 #(
.INIT ( 16'h0180 ))
\addn_1/case001/input1[3]_input1[3]_OR_7_o1 (
.I0(\dbns1/store001 [0]),
.I1(\dbns1/store001 [1]),
.I2(\dbns1/store001 [2]),
.I3(\dbns1/store001 [3]),
.O(\addn_1/case001/input1[3]_input1[3]_OR_7_o )
);
LUT4 #(
.INIT ( 16'hE01E ))
\addn_1/case001/_n0296<23>1 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [1]),
.I2(\dbns2/store001 [2]),
.I3(\dbns2/store001 [3]),
.O(\addn_1/case001/_n0296[23] )
);
LUT3 #(
.INIT ( 8'h86 ))
\addn_1/case001/_n0296<17>1 (
.I0(\dbns2/store001 [1]),
.I1(\dbns2/store001 [2]),
.I2(\dbns2/store001 [3]),
.O(\addn_1/case001/_n0296[17] )
);
LUT3 #(
.INIT ( 8'h18 ))
\addn_1/case001/_n0296<34>1 (
.I0(\dbns2/store001 [1]),
.I1(\dbns2/store001 [2]),
.I2(\dbns2/store001 [3]),
.O(\addn_1/case001/_n0296[34] )
);
LUT4 #(
.INIT ( 16'h7807 ))
\addn_1/case001/_n0296<29>1 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [1]),
.I2(\dbns2/store001 [2]),
.I3(\dbns2/store001 [3]),
.O(\addn_1/case001/_n0296[29] )
);
LUT3 #(
.INIT ( 8'h61 ))
\addn_1/case001/_n0296<16>1 (
.I0(\dbns2/store001 [1]),
.I1(\dbns2/store001 [2]),
.I2(\dbns2/store001 [3]),
.O(\addn_1/case001/_n0296[16] )
);
LUT4 #(
.INIT ( 16'h4449 ))
\addn_1/case001/_n0296<22>1 (
.I0(\dbns2/store001 [2]),
.I1(\dbns2/store001 [3]),
.I2(\dbns2/store001 [1]),
.I3(\dbns2/store001 [0]),
.O(\addn_1/case001/_n0296[22] )
);
LUT4 #(
.INIT ( 16'h9222 ))
\addn_1/case001/_n0296<46>1 (
.I0(\dbns2/store001 [2]),
.I1(\dbns2/store001 [3]),
.I2(\dbns2/store001 [1]),
.I3(\dbns2/store001 [0]),
.O(\addn_1/case001/_n0296[46] )
);
LUT4 #(
.INIT ( 16'h2224 ))
\addn_1/case001/_n0296<40>3 (
.I0(\dbns2/store001 [2]),
.I1(\dbns2/store001 [3]),
.I2(\dbns2/store001 [1]),
.I3(\dbns2/store001 [0]),
.O(\addn_1/case001/_n0296[40] )
);
LUT6 #(
.INIT ( 64'h008000CC8080FFFF ))
\addn_1/case001/SF21 (
.I0(\dbns2/store001 [2]),
.I1(\dbns2/store001 [3]),
.I2(\addn_1/case001/_n0296<40>1 ),
.I3(\addn_1/case001/_n0296<66>1 ),
.I4(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.I5(\addn_1/case001/input1[3]_input1[3]_OR_7_o ),
.O(\addn_1/case001/SF2 )
);
LUT3 #(
.INIT ( 8'h7F ))
\addn_1/case001/_n0296<66>11 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [1]),
.I2(\dbns2/store001 [2]),
.O(\addn_1/case001/_n0296<66>1 )
);
LUT3 #(
.INIT ( 8'hFE ))
\addn_1/case001/_n0296<40>21 (
.I0(\dbns2/store001 [2]),
.I1(\dbns2/store001 [0]),
.I2(\dbns2/store001 [1]),
.O(\addn_1/case001/_n0296<40>2 )
);
LUT2 #(
.INIT ( 4'hE ))
\addn_1/case001/_n0296<42>11 (
.I0(\dbns2/store001 [2]),
.I1(\dbns2/store001 [3]),
.O(\addn_1/case001/_n0296<42>1 )
);
LUT2 #(
.INIT ( 4'hE ))
\addn_1/case001/_n0296<40>11 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [1]),
.O(\addn_1/case001/_n0296<40>1 )
);
LUT2 #(
.INIT ( 4'h7 ))
\addn_1/case001/_n0296<30>11 (
.I0(\dbns2/store001 [2]),
.I1(\dbns2/store001 [3]),
.O(\addn_1/case001/_n0296<30>1 )
);
LUT2 #(
.INIT ( 4'h2 ))
\addn_1/case001/_n0296<20>1 (
.I0(\dbns2/store001 [1]),
.I1(\dbns2/store001 [0]),
.O(\addn_1/case001/_n0296[20] )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case001/input1[3]_GND_4_o_equal_17_o<3>1 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [1]),
.I2(\dbns1/store001 [2]),
.I3(\dbns1/store001 [0]),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT33_344 )
);
LUT2 #(
.INIT ( 4'hE ))
\addn_1/case001/_n0241<3>1 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [2]),
.O(\addn_1/case001/_n0241 )
);
LUT3 #(
.INIT ( 8'hF7 ))
\dbns2/_n0555_inv_SW0 (
.I0(\dbns2/remain [1]),
.I1(\dbns2/remain [0]),
.I2(\dbns2/remain [2]),
.O(N2)
);
LUT6 #(
.INIT ( 64'h55555555FD55DD55 ))
\dbns2/_n0555_inv (
.I0(\dbns2/b [4]),
.I1(\dbns2/b [2]),
.I2(\dbns2/b [0]),
.I3(\dbns2/b [3]),
.I4(\dbns2/b [1]),
.I5(N2),
.O(\dbns2/_n0555_inv_86 )
);
LUT4 #(
.INIT ( 16'hFF7F ))
\dbns2/_n0198_SW0 (
.I0(\dbns2/remain [1]),
.I1(\dbns2/remain [0]),
.I2(\dbns2/count_210 ),
.I3(\dbns2/remain [2]),
.O(N4)
);
LUT6 #(
.INIT ( 64'h0808080008000800 ))
\dbns2/_n0198 (
.I0(\dbns2/b [3]),
.I1(\dbns2/b [4]),
.I2(N4),
.I3(\dbns2/b [2]),
.I4(\dbns2/b [0]),
.I5(\dbns2/b [1]),
.O(\dbns2/_n0198_123 )
);
LUT3 #(
.INIT ( 8'h01 ))
\dbns2/PWR_2_o_b[4]_AND_5_o_SW0 (
.I0(\dbns2/remain [2]),
.I1(\dbns2/remain [1]),
.I2(\dbns2/remain [0]),
.O(N6)
);
LUT6 #(
.INIT ( 64'h0000000002000A00 ))
\dbns2/PWR_2_o_b[4]_AND_5_o (
.I0(\dbns2/b [4]),
.I1(\dbns2/b [0]),
.I2(\dbns2/b [2]),
.I3(\dbns2/b [3]),
.I4(\dbns2/b [1]),
.I5(N6),
.O(\dbns2/PWR_2_o_b[4]_AND_5_o_118 )
);
LUT5 #(
.INIT ( 32'h151FB5BF ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_A4_SW0 (
.I0(\dbns2/shift [0]),
.I1(\dbns2/b [1]),
.I2(\dbns2/shift [1]),
.I3(\dbns2/b [2]),
.I4(\dbns2/b [0]),
.O(N12)
);
LUT4 #(
.INIT ( 16'hAA80 ))
\dbns2/_n0207_inv_SW0 (
.I0(\dbns2/remain [0]),
.I1(\dbns2/b [1]),
.I2(\dbns2/b [0]),
.I3(\dbns2/b [2]),
.O(N14)
);
LUT6 #(
.INIT ( 64'h8888888808888888 ))
\dbns2/_n0207_inv (
.I0(\dbns2/b [4]),
.I1(\dbns2/count_210 ),
.I2(\dbns2/b [3]),
.I3(\dbns2/remain [1]),
.I4(N14),
.I5(\dbns2/remain [2]),
.O(\dbns2/_n0207_inv_93 )
);
LUT6 #(
.INIT ( 64'h5450141044400400 ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>1 (
.I0(\dbns2/shift [2]),
.I1(\dbns2/shift [0]),
.I2(\dbns2/shift [1]),
.I3(\dbns2/b [3]),
.I4(\dbns2/b [1]),
.I5(\dbns2/b [2]),
.O(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>1_386 )
);
LUT3 #(
.INIT ( 8'hF7 ))
\dbns1/_n0555_inv_SW0 (
.I0(\dbns1/remain [1]),
.I1(\dbns1/remain [0]),
.I2(\dbns1/remain [2]),
.O(N16)
);
LUT6 #(
.INIT ( 64'h55555555FD55DD55 ))
\dbns1/_n0555_inv (
.I0(\dbns1/b [4]),
.I1(\dbns1/b [2]),
.I2(\dbns1/b [0]),
.I3(\dbns1/b [3]),
.I4(\dbns1/b [1]),
.I5(N16),
.O(\dbns1/_n0555_inv_160 )
);
LUT4 #(
.INIT ( 16'hFF7F ))
\dbns1/_n0198_SW0 (
.I0(\dbns1/remain [1]),
.I1(\dbns1/remain [0]),
.I2(\dbns2/count_210 ),
.I3(\dbns1/remain [2]),
.O(N18)
);
LUT6 #(
.INIT ( 64'h0808080008000800 ))
\dbns1/_n0198 (
.I0(\dbns1/b [3]),
.I1(\dbns1/b [4]),
.I2(N18),
.I3(\dbns1/b [2]),
.I4(\dbns1/b [0]),
.I5(\dbns1/b [1]),
.O(\dbns1/_n0198_198 )
);
LUT3 #(
.INIT ( 8'h01 ))
\dbns1/PWR_2_o_b[4]_AND_5_o_SW0 (
.I0(\dbns1/remain [2]),
.I1(\dbns1/remain [1]),
.I2(\dbns1/remain [0]),
.O(N20)
);
LUT6 #(
.INIT ( 64'h0000000002000A00 ))
\dbns1/PWR_2_o_b[4]_AND_5_o (
.I0(\dbns1/b [4]),
.I1(\dbns1/b [0]),
.I2(\dbns1/b [2]),
.I3(\dbns1/b [3]),
.I4(\dbns1/b [1]),
.I5(N20),
.O(\dbns1/PWR_2_o_b[4]_AND_5_o_193 )
);
LUT5 #(
.INIT ( 32'h151FB5BF ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_A4_SW0 (
.I0(\dbns1/shift [0]),
.I1(\dbns1/b [1]),
.I2(\dbns1/shift [1]),
.I3(\dbns1/b [2]),
.I4(\dbns1/b [0]),
.O(N26)
);
LUT4 #(
.INIT ( 16'hAA80 ))
\dbns1/_n0207_inv_SW0 (
.I0(\dbns1/remain [0]),
.I1(\dbns1/b [1]),
.I2(\dbns1/b [0]),
.I3(\dbns1/b [2]),
.O(N28)
);
LUT6 #(
.INIT ( 64'h8888888808888888 ))
\dbns1/_n0207_inv (
.I0(\dbns1/b [4]),
.I1(\dbns2/count_210 ),
.I2(\dbns1/b [3]),
.I3(\dbns1/remain [1]),
.I4(N28),
.I5(\dbns1/remain [2]),
.O(\dbns1/_n0207_inv_167 )
);
LUT6 #(
.INIT ( 64'h5450141044400400 ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>1 (
.I0(\dbns1/shift [2]),
.I1(\dbns1/shift [0]),
.I2(\dbns1/shift [1]),
.I3(\dbns1/b [3]),
.I4(\dbns1/b [1]),
.I5(\dbns1/b [2]),
.O(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>1_392 )
);
LUT6 #(
.INIT ( 64'hBE8EB282B282B282 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT21 (
.I0(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>4 ),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [1]),
.I3(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>3 ),
.I4(\addn_1/case101/_n0296<42>1 ),
.I5(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>2 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT2 )
);
LUT6 #(
.INIT ( 64'hFB62FB62FB62D940 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT23 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [1]),
.I2(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>2 ),
.I3(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>3 ),
.I4(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>4 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT21_394 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT22_395 )
);
LUT6 #(
.INIT ( 64'h5555555544440040 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT28 (
.I0(\addn_1/case001/cout [0]),
.I1(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT11_409 ),
.I2(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_196_OUT1 ),
.I3(\addn_1/case101/input1[3]_GND_4_o_equal_17_o ),
.I4(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT26_397 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT24 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT27_398 )
);
LUT3 #(
.INIT ( 8'h08 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT23 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.I2(\addn_1/case001/cout [1]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT24_400 )
);
LUT6 #(
.INIT ( 64'h8AAA000000AA0000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT26 (
.I0(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT27_402 ),
.I1(\addn_1/case101/_n0296[12] ),
.I2(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT101 ),
.I3(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I4(\addn_1/case101/SF1 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT23_238 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT28_403 )
);
LUT5 #(
.INIT ( 32'hEEAAECA0 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT27 (
.I0(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT24_400 ),
.I1(\addn_1/case101/_n0296[49] ),
.I2(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT26_401 ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT266 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT28_403 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT29_404 )
);
LUT6 #(
.INIT ( 64'h8AAA000000AA0000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT29 (
.I0(\addn_1/case001/cout [0]),
.I1(\addn_1/case101/_n0296[12] ),
.I2(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT101 ),
.I3(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I4(\addn_1/case101/SF1 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT23_238 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT211_406 )
);
LUT6 #(
.INIT ( 64'hF3F35151F3F35100 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT210 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/input1[3]_PWR_6_o_equal_27_o ),
.I2(\addn_1/case101/input1[3]_input1[3]_OR_7_o ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT210_405 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT266 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT211_406 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT212 )
);
LUT5 #(
.INIT ( 32'hC8C8C8C0 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT211 (
.I0(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I1(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I2(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT21 ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT29_404 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT212 ),
.O(\addn_1/case101/cout[1]_input2[3]_mux_205_OUT<1> )
);
LUT6 #(
.INIT ( 64'hAAAAAAAA80888000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT13 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT11_409 ),
.I2(\addn_1/case101/_n0296[26] ),
.I3(\addn_1/case101/input1[3]_GND_4_o_equal_17_o ),
.I4(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_196_OUT1 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT1 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT12 )
);
LUT6 #(
.INIT ( 64'hFEFAFCF0EEAACC00 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT15 (
.I0(\addn_1/case101/_n0296[20] ),
.I1(\addn_1/case101/_n0296[26] ),
.I2(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT14_411 ),
.I3(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>2 ),
.I4(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>3 ),
.I5(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>4 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT15_412 )
);
LUT6 #(
.INIT ( 64'hAAA2AA2280800000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT17 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [1]),
.I2(\addn_1/case101/_n0296<30>1 ),
.I3(\addn_1/case101/_n0296<42>1 ),
.I4(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>3 ),
.I5(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>4 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT17_413 )
);
LUT6 #(
.INIT ( 64'hDC70CC3050500000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT41 (
.I0(\addn_1/case001/cout [0]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [3]),
.I3(\dbns2/store101 [1]),
.I4(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>4 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT36_228 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT4 )
);
LUT5 #(
.INIT ( 32'hFFFFD5C0 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT43 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/_n0296[17] ),
.I2(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT33_236 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT4 ),
.I4(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT41_416 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT42_417 )
);
LUT6 #(
.INIT ( 64'hFFFFF888F888F888 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT45 (
.I0(\addn_1/case101/_n0296[29] ),
.I1(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT25_232 ),
.I2(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT43_418 ),
.I4(\addn_1/case101/_n0296[23] ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT32_240 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT44_419 )
);
LUT5 #(
.INIT ( 32'hECCCA000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT49 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/_n0296[46] ),
.I2(\addn_1/case101/_n0296[23] ),
.I3(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT102 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT112_237 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT48_422 )
);
LUT6 #(
.INIT ( 64'hF0F0F0F0E0C0A000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT410 (
.I0(\addn_1/case101/_n0296[17] ),
.I1(\addn_1/case101/_n0296[40] ),
.I2(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT111_239 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT48_422 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT49_423 )
);
LUT6 #(
.INIT ( 64'hFFFFC8C8FFFFC8C0 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT411 (
.I0(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I1(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I2(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT44_419 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT49_423 ),
.I4(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT42_417 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT47 ),
.O(\addn_1/case101/out[3]_input2[3]_mux_204_OUT<3> )
);
LUT5 #(
.INIT ( 32'hA020AA22 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT2661 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/input1[3]_input1[3]_OR_7_o ),
.I2(\addn_1/case101/_n0296[55] ),
.I3(\addn_1/case101/_n0296[43] ),
.I4(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT13 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT2661_424 )
);
LUT6 #(
.INIT ( 64'hB8BB0000B8BBB8BB ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT2662 (
.I0(\addn_1/case101/_n0296[10] ),
.I1(\addn_1/case101/input1[3]_input1[3]_OR_8_o ),
.I2(\addn_1/case101/_n0296[12] ),
.I3(\addn_1/case101/input1[3]_PWR_6_o_equal_37_o ),
.I4(\addn_1/case101/_n0296[24] ),
.I5(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT102 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT2662_425 )
);
LUT5 #(
.INIT ( 32'hBF000F00 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT2663 (
.I0(\addn_1/case101/_n0296[18] ),
.I1(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT101 ),
.I2(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT2661_424 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT2662_425 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT266 )
);
LUT3 #(
.INIT ( 8'h14 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT31 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [1]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT3 )
);
LUT5 #(
.INIT ( 32'h55551000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT32 (
.I0(\addn_1/case001/cout [0]),
.I1(\dbns2/store101 [3]),
.I2(\dbns2/store101 [0]),
.I3(\dbns2/store101 [1]),
.I4(\dbns2/store101 [2]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT31_427 )
);
LUT5 #(
.INIT ( 32'h54445000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT33 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT3 ),
.I2(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>4 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT31_427 ),
.I4(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT36_228 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT37_428 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFECA0 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT35 (
.I0(\addn_1/case101/_n0296[16] ),
.I1(\addn_1/case101/_n0296[29] ),
.I2(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT33_236 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT34_234 ),
.I4(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT38_429 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT37_428 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT39 )
);
LUT6 #(
.INIT ( 64'hFFFFF888F888F888 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT37 (
.I0(\addn_1/case101/_n0296[28] ),
.I1(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT25_232 ),
.I2(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT310_431 ),
.I4(\addn_1/case101/_n0296[22] ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT32_240 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT311_432 )
);
LUT5 #(
.INIT ( 32'hECCCA000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT311 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/_n0296[29] ),
.I2(\addn_1/case101/_n0296[22] ),
.I3(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT102 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT112_237 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT315 )
);
LUT6 #(
.INIT ( 64'hF0F0F0F0E0C0A000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT312 (
.I0(\addn_1/case101/_n0296[16] ),
.I1(\addn_1/case101/_n0296[23] ),
.I2(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT111_239 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT315 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT316 )
);
LUT6 #(
.INIT ( 64'hFFC8FFC8FFC8FFC0 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT313 (
.I0(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I1(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I2(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT311_432 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT39 ),
.I4(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT316 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT314 ),
.O(\addn_1/case101/out[3]_input2[3]_mux_204_OUT<2> )
);
LUT5 #(
.INIT ( 32'hF444F000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT11 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/_n0296[55] ),
.I2(\addn_1/case101/_n0296[10] ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT35_230 ),
.I4(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT36_228 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1 )
);
LUT5 #(
.INIT ( 32'hFFFFECA0 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT12 (
.I0(\addn_1/case101/_n0296[18] ),
.I1(\addn_1/case101/_n0296[12] ),
.I2(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT33_236 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT34_234 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT11_438 )
);
LUT6 #(
.INIT ( 64'hFFFFF888F888F888 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT14 (
.I0(\addn_1/case101/_n0296[30] ),
.I1(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT25_232 ),
.I2(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT12_439 ),
.I4(\addn_1/case101/_n0296[24] ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT32_240 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT13_440 )
);
LUT3 #(
.INIT ( 8'h57 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT15 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101 [1]),
.I2(\dbns2/store101 [2]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT14_441 )
);
LUT5 #(
.INIT ( 32'h575F0000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT16 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [2]),
.I3(\dbns2/store101 [1]),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT114_233 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT15_442 )
);
LUT6 #(
.INIT ( 64'h3310330010100000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT17 (
.I0(\addn_1/case001/cout [0]),
.I1(\addn_1/case001/cout [1]),
.I2(\addn_1/case101/input1[3]_input1[3]_OR_7_o ),
.I3(\addn_1/case101/_n0296[36] ),
.I4(\addn_1/case101/_n0296[30] ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT16_443 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFF888 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT19 (
.I0(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.I1(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT17_444 ),
.I2(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT113_235 ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT14_441 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT16_443 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT15_442 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT18_445 )
);
LUT6 #(
.INIT ( 64'hFF131313FF000000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT111 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.I2(\dbns2/store101 [1]),
.I3(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT102 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT19_446 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT110_447 )
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAA0888 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT113 (
.I0(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I1(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT111_239 ),
.I2(\dbns2/store101 [3]),
.I3(\addn_1/case101/_n0296<40>2 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT118 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT110_447 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT119 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFC8C8C8C0 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT114 (
.I0(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I1(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I2(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT13_440 ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT18_445 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT119 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT11_438 ),
.O(\addn_1/case101/cout[1]_input2[3]_mux_205_OUT<0> )
);
LUT6 #(
.INIT ( 64'h0828080800200000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT28 (
.I0(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT15_460 ),
.I1(\dbns2/store100 [1]),
.I2(\dbns2/store100 [0]),
.I3(\addn_1/case100/input1[3]_input1[3]_OR_7_o ),
.I4(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT612 ),
.I5(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT613 ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT27_454 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFAAAA2220 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT29 (
.I0(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT23_451 ),
.I1(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT33_300 ),
.I2(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT27_454 ),
.I3(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT25_453 ),
.I4(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT24_452 ),
.I5(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT22 ),
.O(\addn_1/case100/out[3]_input2[3]_mux_204_OUT<1> )
);
LUT6 #(
.INIT ( 64'h02222222FFFFFFFF ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT2_SW0 (
.I0(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I1(\addn_1/case100/input1[3]_input1[3]_OR_7_o ),
.I2(\dbns2/store100 [1]),
.I3(\dbns2/store100 [2]),
.I4(\dbns2/store100 [3]),
.I5(\addn_1/case100/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.O(N30)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFA2A2A2A0 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT110 (
.I0(\addn_1/case100/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I1(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT34_297 ),
.I2(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT13_458 ),
.I3(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT14_459 ),
.I4(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT18 ),
.I5(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT12_457 ),
.O(\addn_1/case100/out[3]_input2[3]_mux_204_OUT<0> )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFECA0 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT43 (
.I0(\addn_1/case100/_n0296[17] ),
.I1(\addn_1/case100/_n0296[46] ),
.I2(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT33_300 ),
.I3(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT34_297 ),
.I4(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT41_463 ),
.I5(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT4 ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT42_464 )
);
LUT5 #(
.INIT ( 32'hFFF0FF80 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT48 (
.I0(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I1(\addn_1/case100/_n0296[23] ),
.I2(\addn_1/case100/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I3(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT42_464 ),
.I4(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT46_467 ),
.O(\addn_1/case100/out[3]_input2[3]_mux_204_OUT<3> )
);
LUT5 #(
.INIT ( 32'hFFF0FF80 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT38 (
.I0(\addn_1/case100/_n0296[22] ),
.I1(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I2(\addn_1/case100/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I3(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT32 ),
.I4(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT310 ),
.O(\addn_1/case100/out[3]_input2[3]_mux_204_OUT<2> )
);
LUT6 #(
.INIT ( 64'hF1F0110000000000 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT11 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [1]),
.I2(\addn_1/case100/_n0296<30>1 ),
.I3(\addn_1/case100/_n0296<42>1 ),
.I4(\addn_1/case100/_n0296<40>1 ),
.I5(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT1 )
);
LUT6 #(
.INIT ( 64'h7777000050000000 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT15 (
.I0(\dbns2/store100 [3]),
.I1(\addn_1/case100/_n0296<40>2 ),
.I2(\addn_1/case100/_n0296<66>1 ),
.I3(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT112 ),
.I4(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I5(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT111 ),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT14 )
);
LUT4 #(
.INIT ( 16'hAA80 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT22_SW0 (
.I0(\dbns2/store100 [3]),
.I1(\dbns2/store100 [0]),
.I2(\dbns2/store100 [1]),
.I3(\dbns2/store100 [2]),
.O(N32)
);
LUT6 #(
.INIT ( 64'h0828080800200000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT28 (
.I0(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT15_487 ),
.I1(\dbns2/store001 [1]),
.I2(\dbns2/store001 [0]),
.I3(\addn_1/case001/input1[3]_input1[3]_OR_7_o ),
.I4(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT612 ),
.I5(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT613 ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT27_481 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFAAAA2220 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT29 (
.I0(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT23_478 ),
.I1(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT33_344 ),
.I2(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT27_481 ),
.I3(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT25_480 ),
.I4(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT24_479 ),
.I5(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT22 ),
.O(\addn_1/case001/out[3]_input2[3]_mux_204_OUT<1> )
);
LUT6 #(
.INIT ( 64'h02222222FFFFFFFF ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT2_SW0 (
.I0(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I1(\addn_1/case001/input1[3]_input1[3]_OR_7_o ),
.I2(\dbns2/store001 [1]),
.I3(\dbns2/store001 [2]),
.I4(\dbns2/store001 [3]),
.I5(\addn_1/case001/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.O(N36)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFAAAA2220 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT110 (
.I0(\addn_1/case001/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I1(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT34_341 ),
.I2(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT18 ),
.I3(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT14_486 ),
.I4(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT13_485 ),
.I5(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT12_484 ),
.O(\addn_1/case001/out[3]_input2[3]_mux_204_OUT<0> )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFECA0 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT43 (
.I0(\addn_1/case001/_n0296[17] ),
.I1(\addn_1/case001/_n0296[46] ),
.I2(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT33_344 ),
.I3(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT34_341 ),
.I4(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT41_490 ),
.I5(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT4 ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT42_491 )
);
LUT5 #(
.INIT ( 32'hFFF0FF80 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT48 (
.I0(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I1(\addn_1/case001/_n0296[23] ),
.I2(\addn_1/case001/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I3(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT42_491 ),
.I4(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT46_494 ),
.O(\addn_1/case001/out[3]_input2[3]_mux_204_OUT<3> )
);
LUT5 #(
.INIT ( 32'hFFF0FF80 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT38 (
.I0(\addn_1/case001/_n0296[22] ),
.I1(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I2(\addn_1/case001/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I3(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT32 ),
.I4(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT310 ),
.O(\addn_1/case001/out[3]_input2[3]_mux_204_OUT<2> )
);
LUT6 #(
.INIT ( 64'hF1F0110000000000 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT11 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [1]),
.I2(\addn_1/case001/_n0296<30>1 ),
.I3(\addn_1/case001/_n0296<42>1 ),
.I4(\addn_1/case001/_n0296<40>1 ),
.I5(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT1 )
);
LUT6 #(
.INIT ( 64'h7777000050000000 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT15 (
.I0(\dbns2/store001 [3]),
.I1(\addn_1/case001/_n0296<40>2 ),
.I2(\addn_1/case001/_n0296<66>1 ),
.I3(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT112 ),
.I4(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I5(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT111 ),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT14 )
);
LUT4 #(
.INIT ( 16'hAA80 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT22_SW0 (
.I0(\dbns2/store001 [3]),
.I1(\dbns2/store001 [0]),
.I2(\dbns2/store001 [1]),
.I3(\dbns2/store001 [2]),
.O(N38)
);
IBUF a1_4_IBUF (
.I(a1[4]),
.O(a1_4_IBUF_0)
);
IBUF a1_3_IBUF (
.I(a1[3]),
.O(a1_3_IBUF_1)
);
IBUF a1_2_IBUF (
.I(a1[2]),
.O(a1_2_IBUF_2)
);
IBUF a1_1_IBUF (
.I(a1[1]),
.O(a1_1_IBUF_3)
);
IBUF a1_0_IBUF (
.I(a1[0]),
.O(a1_0_IBUF_4)
);
IBUF a2_4_IBUF (
.I(a2[4]),
.O(a2_4_IBUF_5)
);
IBUF a2_3_IBUF (
.I(a2[3]),
.O(a2_3_IBUF_6)
);
IBUF a2_2_IBUF (
.I(a2[2]),
.O(a2_2_IBUF_7)
);
IBUF a2_1_IBUF (
.I(a2[1]),
.O(a2_1_IBUF_8)
);
IBUF a2_0_IBUF (
.I(a2[0]),
.O(a2_0_IBUF_9)
);
OBUF store000_out_3_OBUF (
.I(\addn_1/case000/out [3]),
.O(store000_out[3])
);
OBUF store000_out_2_OBUF (
.I(\addn_1/case000/out [2]),
.O(store000_out[2])
);
OBUF store000_out_1_OBUF (
.I(\addn_1/case000/out [1]),
.O(store000_out[1])
);
OBUF store000_out_0_OBUF (
.I(\addn_1/case000/out [0]),
.O(store000_out[0])
);
OBUF store001_out_3_OBUF (
.I(\addn_1/case001/out [3]),
.O(store001_out[3])
);
OBUF store001_out_2_OBUF (
.I(\addn_1/case001/out [2]),
.O(store001_out[2])
);
OBUF store001_out_1_OBUF (
.I(\addn_1/case001/out [1]),
.O(store001_out[1])
);
OBUF store001_out_0_OBUF (
.I(\addn_1/case001/out [0]),
.O(store001_out[0])
);
OBUF store010_out_3_OBUF (
.I(\addn_1/case010/out [3]),
.O(store010_out[3])
);
OBUF store010_out_2_OBUF (
.I(\addn_1/case010/out [2]),
.O(store010_out[2])
);
OBUF store010_out_1_OBUF (
.I(\addn_1/case010/out [1]),
.O(store010_out[1])
);
OBUF store010_out_0_OBUF (
.I(\addn_1/case010/out [0]),
.O(store010_out[0])
);
OBUF store100_out_3_OBUF (
.I(\addn_1/case100/out [3]),
.O(store100_out[3])
);
OBUF store100_out_2_OBUF (
.I(\addn_1/case100/out [2]),
.O(store100_out[2])
);
OBUF store100_out_1_OBUF (
.I(\addn_1/case100/out [1]),
.O(store100_out[1])
);
OBUF store100_out_0_OBUF (
.I(\addn_1/case100/out [0]),
.O(store100_out[0])
);
OBUF store101_out_3_OBUF (
.I(\addn_1/case101/out [3]),
.O(store101_out[3])
);
OBUF store101_out_2_OBUF (
.I(\addn_1/case101/out [2]),
.O(store101_out[2])
);
OBUF store101_out_1_OBUF (
.I(\addn_1/case101/out [1]),
.O(store101_out[1])
);
OBUF store101_out_0_OBUF (
.I(\addn_1/case101/out [0]),
.O(store101_out[0])
);
OBUF store110_out_3_OBUF (
.I(\addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.O(store110_out[3])
);
OBUF store110_out_2_OBUF (
.I(\addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.O(store110_out[2])
);
OBUF store110_out_1_OBUF (
.I(\addn_1/case110/out [1]),
.O(store110_out[1])
);
OBUF store110_out_0_OBUF (
.I(\addn_1/case110/out [0]),
.O(store110_out[0])
);
OBUF cout1_1_OBUF (
.I(\addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.O(cout1[1])
);
OBUF cout1_0_OBUF (
.I(\addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.O(cout1[0])
);
OBUF cout2_1_OBUF (
.I(\addn_1/case001/cout [1]),
.O(cout2[1])
);
OBUF cout2_0_OBUF (
.I(\addn_1/case001/cout [0]),
.O(cout2[0])
);
OBUF cout3_1_OBUF (
.I(\addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.O(cout3[1])
);
OBUF cout3_0_OBUF (
.I(\addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.O(cout3[0])
);
OBUF cout4_1_OBUF (
.I(\addn_1/case100/cout [1]),
.O(cout4[1])
);
OBUF cout4_0_OBUF (
.I(\addn_1/case100/cout [0]),
.O(cout4[0])
);
OBUF cout5_1_OBUF (
.I(\addn_1/case101/cout [1]),
.O(cout5[1])
);
OBUF cout5_0_OBUF (
.I(\addn_1/case101/cout [0]),
.O(cout5[0])
);
OBUF cout6_1_OBUF (
.I(\addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.O(cout6[1])
);
OBUF cout6_0_OBUF (
.I(\addn_1/case110/Mmux_cout[1]_input2[3]_mux_205_OUT117 ),
.O(cout6[0])
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFDDDA888 ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT521 (
.I0(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1> ),
.I1(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> ),
.I2(\dbns2/b [0]),
.I3(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_A51 ),
.I4(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<1> ),
.I5(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.O(\dbns2/Mmux_b[4]_a[4]_mux_69_OUT52_72 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFDDDA888 ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT521 (
.I0(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1> ),
.I1(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> ),
.I2(\dbns1/b [0]),
.I3(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_A51 ),
.I4(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<1> ),
.I5(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.O(\dbns1/Mmux_b[4]_a[4]_mux_69_OUT52_146 )
);
LUT6 #(
.INIT ( 64'h575F555F575F0000 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT14_SW0 (
.I0(\dbns2/store100 [3]),
.I1(\dbns2/store100 [0]),
.I2(\dbns2/store100 [2]),
.I3(\dbns2/store100 [1]),
.I4(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT114 ),
.I5(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT113 ),
.O(N60)
);
LUT6 #(
.INIT ( 64'h575F555F575F0000 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT14_SW0 (
.I0(\dbns2/store001 [3]),
.I1(\dbns2/store001 [0]),
.I2(\dbns2/store001 [2]),
.I3(\dbns2/store001 [1]),
.I4(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT114 ),
.I5(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT113 ),
.O(N62)
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT131 (
.I0(\dbns1/store100 [2]),
.I1(\dbns1/store100 [0]),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [3]),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT115 )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT131 (
.I0(\dbns1/store001 [2]),
.I1(\dbns1/store001 [0]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [3]),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT115 )
);
LUT6 #(
.INIT ( 64'hAAAAAAABAAAAAAA8 ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>3 (
.I0(\dbns2/b [4]),
.I1(\dbns2/PWR_2_o_PWR_2_o_AND_6_o ),
.I2(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I3(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I4(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.I5(N90),
.O(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4> )
);
LUT6 #(
.INIT ( 64'hAAAAAAABAAAAAAA8 ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>3 (
.I0(\dbns1/b [4]),
.I1(\dbns1/PWR_2_o_PWR_2_o_AND_6_o ),
.I2(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I3(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I4(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.I5(N92),
.O(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4> )
);
LUT6 #(
.INIT ( 64'h5155000000550000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT28 (
.I0(\addn_1/case001/cout [0]),
.I1(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT101 ),
.I2(\addn_1/case101/_n0296[10] ),
.I3(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I4(\addn_1/case101/SF2 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT22_241 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT210_405 )
);
LUT4 #(
.INIT ( 16'hD777 ))
\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT1021 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.O(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT102 )
);
LUT4 #(
.INIT ( 16'hEAAA ))
\addn_1/case101/_n0296<12>1 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [1]),
.I3(\dbns2/store101 [2]),
.O(\addn_1/case101/_n0296[12] )
);
LUT2 #(
.INIT ( 4'hD ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT21131_SW0 (
.I0(\dbns2/store101 [1]),
.I1(\addn_1/case001/cout [0]),
.O(N94)
);
LUT6 #(
.INIT ( 64'h5155000000550000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT24 (
.I0(N94),
.I1(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT101 ),
.I2(\addn_1/case101/_n0296[10] ),
.I3(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I4(\addn_1/case101/SF2 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT22_241 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT26_401 )
);
LUT2 #(
.INIT ( 4'hE ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_B41_SW0 (
.I0(\dbns1/shift [1]),
.I1(\dbns1/shift [0]),
.O(N112)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFF1 ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_A511 (
.I0(\dbns1/shift [2]),
.I1(N112),
.I2(\dbns1/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I4(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_A51 )
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAAAAAC ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_A2 (
.I0(\dbns1/b [1]),
.I1(N114),
.I2(\dbns1/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I4(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<1> )
);
LUT2 #(
.INIT ( 4'hE ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_B41_SW0 (
.I0(\dbns2/shift [1]),
.I1(\dbns2/shift [0]),
.O(N116)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFF1 ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_A511 (
.I0(\dbns2/shift [2]),
.I1(N116),
.I2(\dbns2/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I4(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_A51 )
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAAAAAC ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_A2 (
.I0(\dbns2/b [1]),
.I1(N118),
.I2(\dbns2/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I4(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<1> )
);
LUT6 #(
.INIT ( 64'h55555555AAAA55AC ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1>1 (
.I0(\dbns2/b [1]),
.I1(N126),
.I2(\dbns2/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I4(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1> )
);
LUT6 #(
.INIT ( 64'h55555555AAAA55AC ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1>1 (
.I0(\dbns1/b [1]),
.I1(N128),
.I2(\dbns1/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I4(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1> )
);
LUT5 #(
.INIT ( 32'hFEFFAAAA ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3>1_SW0 (
.I0(\dbns2/shift [2]),
.I1(\dbns2/shift [1]),
.I2(\dbns2/shift [0]),
.I3(\dbns2/b [3]),
.I4(N12),
.O(N130)
);
LUT6 #(
.INIT ( 64'h555555AB555555A8 ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3>1 (
.I0(\dbns2/b [3]),
.I1(\dbns2/PWR_2_o_PWR_2_o_AND_6_o ),
.I2(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I3(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I4(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.I5(N130),
.O(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> )
);
LUT5 #(
.INIT ( 32'hFEFFAAAA ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3>1_SW0 (
.I0(\dbns1/shift [2]),
.I1(\dbns1/shift [1]),
.I2(\dbns1/shift [0]),
.I3(\dbns1/b [3]),
.I4(N26),
.O(N132)
);
LUT6 #(
.INIT ( 64'h555555AB555555A8 ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3>1 (
.I0(\dbns1/b [3]),
.I1(\dbns1/PWR_2_o_PWR_2_o_AND_6_o ),
.I2(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I3(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I4(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.I5(N132),
.O(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> )
);
LUT6 #(
.INIT ( 64'hCCCCCCCCCCCCCC80 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT47 (
.I0(\addn_1/case100/_n0296[34] ),
.I1(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I2(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT113 ),
.I3(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT43_465 ),
.I4(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT45 ),
.I5(N134),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT46_467 )
);
LUT6 #(
.INIT ( 64'hCCCCCCCCCCCCCC80 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT37 (
.I0(\addn_1/case100/_n0296[17] ),
.I1(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I2(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT113 ),
.I3(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT37_469 ),
.I4(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT39 ),
.I5(N136),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT310 )
);
LUT6 #(
.INIT ( 64'hCCCCCCCCCCCCCC80 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT47 (
.I0(\addn_1/case001/_n0296[34] ),
.I1(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I2(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT113 ),
.I3(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT43_492 ),
.I4(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT45 ),
.I5(N138),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT46_494 )
);
LUT6 #(
.INIT ( 64'hCCCCCCCCCCCCCC80 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT37 (
.I0(\addn_1/case001/_n0296[17] ),
.I1(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I2(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT113 ),
.I3(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT37_496 ),
.I4(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT39 ),
.I5(N140),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT310 )
);
LUT3 #(
.INIT ( 8'hFE ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0>1_SW0 (
.I0(\dbns2/shift [2]),
.I1(\dbns2/shift [1]),
.I2(\dbns2/shift [0]),
.O(N142)
);
LUT6 #(
.INIT ( 64'h55555555555555AD ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0>1 (
.I0(\dbns2/b [0]),
.I1(N142),
.I2(\dbns2/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I4(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> )
);
LUT3 #(
.INIT ( 8'hFE ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0>1_SW0 (
.I0(\dbns1/shift [2]),
.I1(\dbns1/shift [1]),
.I2(\dbns1/shift [0]),
.O(N144)
);
LUT6 #(
.INIT ( 64'h55555555555555AD ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0>1 (
.I0(\dbns1/b [0]),
.I1(N144),
.I2(\dbns1/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I4(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> )
);
LUT4 #(
.INIT ( 16'hEBBB ))
\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT1211 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.O(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT121 )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT131 (
.I0(\dbns1/store101 [2]),
.I1(\dbns1/store101 [0]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [3]),
.O(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT13 )
);
LUT4 #(
.INIT ( 16'h2000 ))
\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT1011 (
.I0(\dbns1/store101 [2]),
.I1(\dbns1/store101 [0]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [3]),
.O(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT101 )
);
LUT4 #(
.INIT ( 16'h0001 ))
\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>41 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [0]),
.I3(\dbns1/store101 [1]),
.O(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>4 )
);
LUT4 #(
.INIT ( 16'h0100 ))
\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>31 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.O(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>3 )
);
LUT4 #(
.INIT ( 16'hAAA8 ))
\addn_1/case101/_n0296<10>1 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [0]),
.I3(\dbns2/store101 [1]),
.O(\addn_1/case101/_n0296[10] )
);
LUT4 #(
.INIT ( 16'h8880 ))
\addn_1/case101/_n0296<43>1 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.I2(\dbns2/store101 [0]),
.I3(\dbns2/store101 [1]),
.O(\addn_1/case101/_n0296[43] )
);
LUT4 #(
.INIT ( 16'hFFA8 ))
\addn_1/case101/_n0296<24>1 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [1]),
.I3(\dbns2/store101 [3]),
.O(\addn_1/case101/_n0296[24] )
);
LUT5 #(
.INIT ( 32'h00045555 ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_B41_SW2 (
.I0(\dbns1/shift [2]),
.I1(\dbns1/b [3]),
.I2(\dbns1/shift [0]),
.I3(\dbns1/shift [1]),
.I4(N26),
.O(N152)
);
LUT6 #(
.INIT ( 64'hAAAAAAABAAAAAAA8 ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_A4 (
.I0(\dbns1/b [3]),
.I1(\dbns1/PWR_2_o_PWR_2_o_AND_6_o ),
.I2(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I3(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I4(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.I5(N152),
.O(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<3> )
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAAAAAC ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_A3 (
.I0(\dbns1/b [2]),
.I1(N154),
.I2(\dbns1/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns1/PWR_2_o_b[4]_AND_5_o_193 ),
.I4(\dbns1/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns1/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> )
);
LUT5 #(
.INIT ( 32'h00045555 ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_B41_SW2 (
.I0(\dbns2/shift [2]),
.I1(\dbns2/b [3]),
.I2(\dbns2/shift [0]),
.I3(\dbns2/shift [1]),
.I4(N12),
.O(N156)
);
LUT6 #(
.INIT ( 64'hAAAAAAABAAAAAAA8 ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_A4 (
.I0(\dbns2/b [3]),
.I1(\dbns2/PWR_2_o_PWR_2_o_AND_6_o ),
.I2(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I3(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I4(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.I5(N156),
.O(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<3> )
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAAAAAC ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_A3 (
.I0(\dbns2/b [2]),
.I1(N158),
.I2(\dbns2/PWR_2_o_PWR_2_o_AND_6_o ),
.I3(\dbns2/PWR_2_o_b[4]_AND_5_o_118 ),
.I4(\dbns2/PWR_2_o_b[4]_AND_3_o ),
.I5(\dbns2/PWR_2_o_b[4]_AND_1_o ),
.O(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> )
);
LUT6 #(
.INIT ( 64'hC000E0C0C000FFFF ))
\addn_1/case101/SF11 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [3]),
.I3(\dbns2/store101 [1]),
.I4(\addn_1/case101/input1[3]_input1[3]_OR_7_o ),
.I5(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT13 ),
.O(\addn_1/case101/SF1 )
);
LUT4 #(
.INIT ( 16'hBDDD ))
\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT141 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.O(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT14 )
);
LUT5 #(
.INIT ( 32'h11011000 ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_B41_SW1 (
.I0(\dbns1/shift [2]),
.I1(\dbns1/shift [1]),
.I2(\dbns1/shift [0]),
.I3(\dbns1/b [0]),
.I4(\dbns1/b [1]),
.O(N114)
);
LUT5 #(
.INIT ( 32'h11011000 ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_B41_SW1 (
.I0(\dbns2/shift [2]),
.I1(\dbns2/shift [1]),
.I2(\dbns2/shift [0]),
.I3(\dbns2/b [0]),
.I4(\dbns2/b [1]),
.O(N118)
);
LUT5 #(
.INIT ( 32'hFFFFABEF ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1>1_SW0 (
.I0(\dbns2/shift [1]),
.I1(\dbns2/shift [0]),
.I2(\dbns2/b [1]),
.I3(\dbns2/b [0]),
.I4(\dbns2/shift [2]),
.O(N126)
);
LUT5 #(
.INIT ( 32'hFFFFABEF ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1>1_SW0 (
.I0(\dbns1/shift [1]),
.I1(\dbns1/shift [0]),
.I2(\dbns1/b [1]),
.I3(\dbns1/b [0]),
.I4(\dbns1/shift [2]),
.O(N128)
);
LUT5 #(
.INIT ( 32'hEFE0F0FF ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT52_SW4 (
.I0(\dbns2/Mmux_b[4]_a[4]_mux_69_OUT51 ),
.I1(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.I2(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> ),
.I3(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<3> ),
.I4(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4> ),
.O(N177)
);
LUT5 #(
.INIT ( 32'hEFE0000F ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT52_SW5 (
.I0(\dbns2/Mmux_b[4]_a[4]_mux_69_OUT51 ),
.I1(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.I2(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> ),
.I3(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<3> ),
.I4(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4> ),
.O(N178)
);
LUT5 #(
.INIT ( 32'h2E2E22EE ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT52 (
.I0(a2_4_IBUF_5),
.I1(\dbns2/count_210 ),
.I2(N178),
.I3(N177),
.I4(\dbns2/Mmux_b[4]_a[4]_mux_69_OUT52_72 ),
.O(\dbns2/b[4]_a[4]_mux_69_OUT<4> )
);
LUT5 #(
.INIT ( 32'hEFE0F0FF ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT52_SW4 (
.I0(\dbns1/Mmux_b[4]_a[4]_mux_69_OUT51 ),
.I1(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.I2(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> ),
.I3(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<3> ),
.I4(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4> ),
.O(N180)
);
LUT5 #(
.INIT ( 32'hEFE0000F ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT52_SW5 (
.I0(\dbns1/Mmux_b[4]_a[4]_mux_69_OUT51 ),
.I1(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<2> ),
.I2(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<3> ),
.I3(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_A<3> ),
.I4(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4> ),
.O(N181)
);
LUT5 #(
.INIT ( 32'h2E2E22EE ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT52 (
.I0(a1_4_IBUF_0),
.I1(\dbns2/count_210 ),
.I2(N181),
.I3(N180),
.I4(\dbns1/Mmux_b[4]_a[4]_mux_69_OUT52_146 ),
.O(\dbns1/b[4]_a[4]_mux_69_OUT<4> )
);
LUT6 #(
.INIT ( 64'h0A0AFAFA3AFACA0A ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT21 (
.I0(a2_1_IBUF_8),
.I1(\dbns2/b [0]),
.I2(\dbns2/count_210 ),
.I3(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_A51 ),
.I4(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1> ),
.I5(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> ),
.O(\dbns2/b[4]_a[4]_mux_69_OUT<1> )
);
LUT6 #(
.INIT ( 64'h0A0AFAFA3AFACA0A ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT21 (
.I0(a1_1_IBUF_3),
.I1(\dbns1/b [0]),
.I2(\dbns2/count_210 ),
.I3(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_A51 ),
.I4(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<1> ),
.I5(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<0> ),
.O(\dbns1/b[4]_a[4]_mux_69_OUT<1> )
);
LUT6 #(
.INIT ( 64'h1505140411011000 ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_B41_SW3 (
.I0(\dbns1/shift [2]),
.I1(\dbns1/shift [1]),
.I2(\dbns1/shift [0]),
.I3(\dbns1/b [1]),
.I4(\dbns1/b [2]),
.I5(\dbns1/b [0]),
.O(N154)
);
LUT6 #(
.INIT ( 64'h1505140411011000 ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_B41_SW3 (
.I0(\dbns2/shift [2]),
.I1(\dbns2/shift [1]),
.I2(\dbns2/shift [0]),
.I3(\dbns2/b [1]),
.I4(\dbns2/b [2]),
.I5(\dbns2/b [0]),
.O(N158)
);
LUT6 #(
.INIT ( 64'hFFFBFCF8FFF3FCF0 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT110 (
.I0(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I1(\addn_1/case100/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I2(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT18 ),
.I3(N65),
.I4(N64),
.I5(N183),
.O(\addn_1/case100/cout[1]_input2[3]_mux_205_OUT<0> )
);
LUT6 #(
.INIT ( 64'hFFFBFCF8FFF3FCF0 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT110 (
.I0(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT121 ),
.I1(\addn_1/case001/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I2(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT18 ),
.I3(N68),
.I4(N67),
.I5(N185),
.O(\addn_1/case001/cout[1]_input2[3]_mux_205_OUT<0> )
);
LUT6 #(
.INIT ( 64'h00000000FCFDFEFF ))
\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>3_SW0 (
.I0(\dbns2/shift [2]),
.I1(\dbns2/shift [1]),
.I2(\dbns2/shift [0]),
.I3(\dbns2/b [4]),
.I4(\dbns2/b [0]),
.I5(\dbns2/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>1_386 ),
.O(N90)
);
LUT6 #(
.INIT ( 64'h00000000FCFDFEFF ))
\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>3_SW0 (
.I0(\dbns1/shift [2]),
.I1(\dbns1/shift [1]),
.I2(\dbns1/shift [0]),
.I3(\dbns1/b [4]),
.I4(\dbns1/b [0]),
.I5(\dbns1/Mmux_b[4]_b[4]_mux_66_OUT_rs_lut<4>1_392 ),
.O(N92)
);
LUT6 #(
.INIT ( 64'h0000000000BF0033 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT2 (
.I0(\addn_1/case100/_n0296[10] ),
.I1(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I2(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT111 ),
.I3(N30),
.I4(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT22_304 ),
.I5(N189),
.O(\addn_1/case100/cout[1]_input2[3]_mux_205_OUT<1> )
);
LUT6 #(
.INIT ( 64'h0000000000BF0033 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT2 (
.I0(\addn_1/case001/_n0296[10] ),
.I1(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT14 ),
.I2(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT111 ),
.I3(N36),
.I4(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT22_348 ),
.I5(N191),
.O(\addn_1/case001/cout[1]_input2[3]_mux_205_OUT<1> )
);
LUT6 #(
.INIT ( 64'h000000000000A4CC ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT41 (
.I0(\dbns2/store100 [2]),
.I1(\dbns2/store100 [3]),
.I2(\dbns2/store100 [1]),
.I3(\dbns1/store100 [0]),
.I4(\dbns1/store100 [1]),
.I5(\addn_1/case100/_n0241 ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT4 )
);
LUT6 #(
.INIT ( 64'h0000000000009F80 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT41 (
.I0(\dbns2/store001 [2]),
.I1(\dbns2/store001 [1]),
.I2(\dbns1/store001 [0]),
.I3(\dbns2/store001 [3]),
.I4(\dbns1/store001 [1]),
.I5(\addn_1/case001/_n0241 ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT4 )
);
LUT6 #(
.INIT ( 64'h0000021C00000000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT34 (
.I0(\addn_1/case001/cout [0]),
.I1(\addn_1/case001/cout [1]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.I4(\addn_1/case101/_n0241 ),
.I5(\addn_1/case101/_n0296[23] ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT38_429 )
);
LUT6 #(
.INIT ( 64'hAAA0A0A022202020 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT17_SW0 (
.I0(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT34_297 ),
.I1(\addn_1/case100/_n0296<66>1 ),
.I2(\addn_1/case100/_n0241 ),
.I3(\dbns1/store100 [1]),
.I4(\dbns1/store100 [0]),
.I5(\dbns2/store100 [3]),
.O(N64)
);
LUT6 #(
.INIT ( 64'hAAA0A0A022202020 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT17_SW0 (
.I0(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT34_341 ),
.I1(\addn_1/case001/_n0296<66>1 ),
.I2(\addn_1/case001/_n0241 ),
.I3(\dbns1/store001 [1]),
.I4(\dbns1/store001 [0]),
.I5(\dbns2/store001 [3]),
.O(N67)
);
LUT6 #(
.INIT ( 64'h0200002002200008 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1141 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\addn_1/case001/cout [1]),
.I4(\dbns1/store101 [0]),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT114_233 )
);
LUT4 #(
.INIT ( 16'h0280 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT1141 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [1]),
.I2(\dbns1/store100 [0]),
.I3(\dbns1/store100 [2]),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT114 )
);
LUT4 #(
.INIT ( 16'h0280 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT1141 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [1]),
.I2(\dbns1/store001 [0]),
.I3(\dbns1/store001 [2]),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT114 )
);
LUT6 #(
.INIT ( 64'h40A4040444444444 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1171 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case001/cout [0]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [0]),
.I4(\dbns1/store101 [1]),
.I5(\dbns1/store101 [3]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT117 )
);
LUT6 #(
.INIT ( 64'h10A1410111111111 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1121 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case001/cout [0]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [1]),
.I4(\dbns1/store101 [0]),
.I5(\dbns1/store101 [3]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT112_237 )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT1221 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [0]),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [2]),
.O(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT122 )
);
LUT4 #(
.INIT ( 16'hD777 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT1121 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [2]),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [0]),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT112 )
);
LUT4 #(
.INIT ( 16'hBDDD ))
\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT141 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [2]),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [0]),
.O(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT14 )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT1221 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [0]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [2]),
.O(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT122 )
);
LUT4 #(
.INIT ( 16'hD777 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT1121 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [2]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [0]),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT112 )
);
LUT4 #(
.INIT ( 16'hBDDD ))
\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT141 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [2]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [0]),
.O(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT14 )
);
LUT6 #(
.INIT ( 64'h0100001001100004 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT341 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\addn_1/case001/cout [1]),
.I4(\dbns1/store101 [0]),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT34_234 )
);
LUT5 #(
.INIT ( 32'h40020200 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1161 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.I4(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT116 )
);
LUT4 #(
.INIT ( 16'h7FEA ))
\addn_1/case101/_n0296<30>2 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101 [1]),
.I2(\dbns2/store101 [0]),
.I3(\dbns2/store101 [2]),
.O(\addn_1/case101/_n0296[30] )
);
LUT4 #(
.INIT ( 16'h1999 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT14 (
.I0(\dbns2/store101 [1]),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [3]),
.I3(\dbns2/store101 [2]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT14_411 )
);
LUT5 #(
.INIT ( 32'h00010100 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT361 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\addn_1/case001/cout [0]),
.I4(\dbns1/store101 [0]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT36_228 )
);
LUT4 #(
.INIT ( 16'h0100 ))
\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>21 (
.I0(\dbns1/store101 [0]),
.I1(\dbns1/store101 [3]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [1]),
.O(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>2 )
);
LUT3 #(
.INIT ( 8'hA8 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT25 (
.I0(\addn_1/case001/cout [0]),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [1]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT27_402 )
);
LUT5 #(
.INIT ( 32'h00022222 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT110 (
.I0(\addn_1/case001/cout [1]),
.I1(\dbns2/store101 [3]),
.I2(\dbns2/store101 [1]),
.I3(\dbns2/store101 [0]),
.I4(\dbns2/store101 [2]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT19_446 )
);
LUT6 #(
.INIT ( 64'h0500005004000040 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT22 (
.I0(\dbns1/store101 [3]),
.I1(\dbns2/store101 [3]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [1]),
.I4(\dbns1/store101 [0]),
.I5(\dbns2/store101 [2]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT21_394 )
);
LUT2 #(
.INIT ( 4'hD ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT12_SW0 (
.I0(\dbns2/store100 [0]),
.I1(\dbns1/store100 [1]),
.O(N193)
);
LUT6 #(
.INIT ( 64'h1110010101000101 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT12 (
.I0(\addn_1/case100/_n0241 ),
.I1(N193),
.I2(\dbns1/store100 [0]),
.I3(\addn_1/case100/_n0296<42>1 ),
.I4(\dbns2/store100 [1]),
.I5(\addn_1/case100/_n0296<30>1 ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT11 )
);
LUT5 #(
.INIT ( 32'hF951F955 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT31_SW0 (
.I0(\dbns2/store100 [2]),
.I1(\dbns2/store100 [1]),
.I2(\dbns2/store100 [3]),
.I3(\dbns1/store100 [0]),
.I4(\dbns2/store100 [0]),
.O(N195)
);
LUT2 #(
.INIT ( 4'hD ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT12_SW0 (
.I0(\dbns2/store001 [0]),
.I1(\dbns1/store001 [1]),
.O(N197)
);
LUT6 #(
.INIT ( 64'h1110010101000101 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT12 (
.I0(\addn_1/case001/_n0241 ),
.I1(N197),
.I2(\dbns1/store001 [0]),
.I3(\addn_1/case001/_n0296<42>1 ),
.I4(\dbns2/store001 [1]),
.I5(\addn_1/case001/_n0296<30>1 ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT11 )
);
LUT5 #(
.INIT ( 32'hF951F955 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT31_SW0 (
.I0(\dbns2/store001 [2]),
.I1(\dbns2/store001 [1]),
.I2(\dbns2/store001 [3]),
.I3(\dbns1/store001 [0]),
.I4(\dbns2/store001 [0]),
.O(N199)
);
LUT5 #(
.INIT ( 32'hFFFF5140 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT18 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [1]),
.I2(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>2 ),
.I3(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>3 ),
.I4(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT17_413 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT18_414 )
);
LUT6 #(
.INIT ( 64'hECCCA888FFFFA888 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT17_SW1 (
.I0(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I1(\dbns2/store100 [3]),
.I2(\addn_1/case100/_n0296<40>1 ),
.I3(\dbns2/store100 [2]),
.I4(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT34_297 ),
.I5(\addn_1/case100/_n0296<66>1 ),
.O(N65)
);
LUT6 #(
.INIT ( 64'hECCCA888FFFFA888 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT17_SW1 (
.I0(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I1(\dbns2/store001 [3]),
.I2(\addn_1/case001/_n0296<40>1 ),
.I3(\dbns2/store001 [2]),
.I4(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT34_341 ),
.I5(\addn_1/case001/_n0296<66>1 ),
.O(N68)
);
LUT5 #(
.INIT ( 32'h070F0000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT112 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [3]),
.I3(\dbns2/store101 [1]),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT112_237 ),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT118 )
);
LUT6 #(
.INIT ( 64'h0000000078070000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT46 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [1]),
.I2(\dbns2/store101 [2]),
.I3(\dbns2/store101 [3]),
.I4(\addn_1/case101/input1[3]_input1[3]_OR_7_o ),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT45_420 )
);
LUT6 #(
.INIT ( 64'h0410005000000000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT38 (
.I0(\addn_1/case001/cout [0]),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [3]),
.I3(\dbns2/store101 [2]),
.I4(\dbns2/store101 [1]),
.I5(\addn_1/case101/input1[3]_input1[3]_OR_7_o ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT312_433 )
);
LUT6 #(
.INIT ( 64'h0000011000010010 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT351 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\addn_1/case001/cout [1]),
.I3(\dbns1/store101 [0]),
.I4(\dbns1/store101 [1]),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT35_230 )
);
LUT4 #(
.INIT ( 16'hFEEE ))
\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>11 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [0]),
.I3(\dbns1/store101 [1]),
.O(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>1 )
);
LUT3 #(
.INIT ( 8'h81 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT13_SW0 (
.I0(\dbns2/store100 [3]),
.I1(\dbns2/store100 [2]),
.I2(\dbns2/store100 [1]),
.O(N213)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFF4 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT110_SW0 (
.I0(N213),
.I1(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I2(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT11_473 ),
.I3(N60),
.I4(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT1 ),
.I5(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT14 ),
.O(N183)
);
LUT3 #(
.INIT ( 8'h81 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT13_SW0 (
.I0(\dbns2/store001 [3]),
.I1(\dbns2/store001 [2]),
.I2(\dbns2/store001 [1]),
.O(N215)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFF4 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT110_SW0 (
.I0(N215),
.I1(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I2(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT11_500 ),
.I3(N62),
.I4(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT1 ),
.I5(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT14 ),
.O(N185)
);
LUT5 #(
.INIT ( 32'h7EFC0000 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT12 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [3]),
.I2(\dbns2/store100 [2]),
.I3(\dbns2/store100 [1]),
.I4(\addn_1/case100/input1[3]_input1[3]_OR_7_o ),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT11_473 )
);
LUT5 #(
.INIT ( 32'h7EFC0000 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT12 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [3]),
.I2(\dbns2/store001 [2]),
.I3(\dbns2/store001 [1]),
.I4(\addn_1/case001/input1[3]_input1[3]_OR_7_o ),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT11_500 )
);
LUT6 #(
.INIT ( 64'h9249924992499999 ))
\addn_1/case101/input2[3]_input2[3]_mux_128_OUT<0>7 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [1]),
.I2(\dbns1/store101 [0]),
.I3(\dbns1/store101 [1]),
.I4(\dbns1/store101 [3]),
.I5(\dbns1/store101 [2]),
.O(\addn_1/case101/input2[3]_input2[3]_mux_128_OUT<0> )
);
LUT6 #(
.INIT ( 64'h4444999422244444 ))
\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT614 (
.I0(\dbns2/store101 [1]),
.I1(\dbns2/store101 [0]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [3]),
.I4(\dbns1/store101 [1]),
.I5(\dbns1/store101 [0]),
.O(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT61 )
);
LUT6 #(
.INIT ( 64'h2222424299922222 ))
\addn_1/case101/Mmux_input2[3]_input2[3]_mux_196_OUT13 (
.I0(\dbns2/store101 [1]),
.I1(\dbns2/store101 [0]),
.I2(\dbns1/store101 [3]),
.I3(\dbns1/store101 [2]),
.I4(\dbns1/store101 [1]),
.I5(\dbns1/store101 [0]),
.O(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_196_OUT1 )
);
LUT4 #(
.INIT ( 16'h57FE ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT18 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101 [0]),
.I2(\dbns2/store101 [1]),
.I3(\dbns2/store101 [2]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT17_444 )
);
LUT6 #(
.INIT ( 64'h0404040426040404 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT19 (
.I0(\dbns1/store001 [1]),
.I1(\dbns1/store001 [0]),
.I2(N219),
.I3(\addn_1/case001/_n0296<40>2 ),
.I4(\dbns2/store001 [3]),
.I5(\addn_1/case001/_n0241 ),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT18 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFF10001404 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT13 (
.I0(\addn_1/case100/_n0241 ),
.I1(\dbns1/store100 [0]),
.I2(\dbns1/store100 [1]),
.I3(\addn_1/case100/_n0296[20] ),
.I4(\addn_1/case100/_n0296<40>1 ),
.I5(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT11 ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT12_457 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFF10001404 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT13 (
.I0(\addn_1/case001/_n0241 ),
.I1(\dbns1/store001 [0]),
.I2(\dbns1/store001 [1]),
.I3(\addn_1/case001/_n0296[20] ),
.I4(\addn_1/case001/_n0296<40>1 ),
.I5(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT11 ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT12_484 )
);
LUT6 #(
.INIT ( 64'hFBFBFBFB6565656D ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT23_SW0 (
.I0(\dbns2/store001 [1]),
.I1(\dbns2/store001 [0]),
.I2(\dbns1/store001 [1]),
.I3(\dbns2/store001 [3]),
.I4(\dbns2/store001 [2]),
.I5(\dbns1/store001 [0]),
.O(N225)
);
LUT6 #(
.INIT ( 64'hDB65DB65DB65DB6D ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT23_SW1 (
.I0(\dbns2/store001 [1]),
.I1(\dbns2/store001 [0]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [0]),
.I4(\dbns2/store001 [3]),
.I5(\dbns2/store001 [2]),
.O(N226)
);
LUT3 #(
.INIT ( 8'hD7 ))
\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT6131 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [1]),
.I2(\dbns1/store100 [0]),
.O(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT613 )
);
LUT3 #(
.INIT ( 8'hD7 ))
\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT6131 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [1]),
.I2(\dbns1/store001 [0]),
.O(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT613 )
);
LUT6 #(
.INIT ( 64'h0200082000200800 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1131 (
.I0(\dbns1/store101 [3]),
.I1(\addn_1/case001/cout [1]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [1]),
.I4(\dbns1/store101 [0]),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT113_235 )
);
LUT6 #(
.INIT ( 64'h0100041000100400 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT331 (
.I0(\dbns1/store101 [3]),
.I1(\addn_1/case001/cout [1]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [1]),
.I4(\dbns1/store101 [0]),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT33_236 )
);
LUT3 #(
.INIT ( 8'h08 ))
\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT6121 (
.I0(\dbns1/store100 [0]),
.I1(\dbns1/store100 [3]),
.I2(\dbns1/store100 [1]),
.O(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT612 )
);
LUT3 #(
.INIT ( 8'h08 ))
\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT6121 (
.I0(\dbns1/store001 [0]),
.I1(\dbns1/store001 [3]),
.I2(\dbns1/store001 [1]),
.O(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT612 )
);
LUT4 #(
.INIT ( 16'h1000 ))
\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT1221 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [0]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [2]),
.O(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT122 )
);
LUT6 #(
.INIT ( 64'h4002020040020020 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1151 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.I4(\addn_1/case001/cout [1]),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT115 )
);
LUT6 #(
.INIT ( 64'h2008080020080080 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT1111 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.I4(\addn_1/case001/cout [1]),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT111_239 )
);
LUT4 #(
.INIT ( 16'hEBBB ))
\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT1211 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [2]),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [0]),
.O(\addn_1/case100/Mmux_input2[3]_input2[3]_mux_128_OUT121 )
);
LUT4 #(
.INIT ( 16'hEBBB ))
\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT1211 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [2]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [0]),
.O(\addn_1/case001/Mmux_input2[3]_input2[3]_mux_128_OUT121 )
);
LUT6 #(
.INIT ( 64'h0200002002000000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT251 (
.I0(\dbns1/store101 [2]),
.I1(\dbns1/store101 [3]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.I4(\addn_1/case001/cout [1]),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT25_232 )
);
LUT6 #(
.INIT ( 64'h1004040010040040 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT321 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [0]),
.I4(\addn_1/case001/cout [1]),
.I5(\addn_1/case001/cout [0]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT32_240 )
);
LUT6 #(
.INIT ( 64'h0001100010000510 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT11 (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns2/store101 [1]),
.I4(\dbns2/store101 [0]),
.I5(\dbns1/store101 [0]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT1 )
);
LUT4 #(
.INIT ( 16'hFFA8 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT26 (
.I0(\dbns1/store101 [2]),
.I1(\dbns1/store101 [0]),
.I2(\dbns1/store101 [1]),
.I3(\dbns1/store101 [3]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT11_409 )
);
LUT4 #(
.INIT ( 16'h2802 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT44 (
.I0(\addn_1/case001/cout [1]),
.I1(\dbns2/store101 [1]),
.I2(\dbns2/store101 [2]),
.I3(\dbns2/store101 [3]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT43_418 )
);
LUT4 #(
.INIT ( 16'h0280 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT36 (
.I0(\addn_1/case001/cout [1]),
.I1(\dbns2/store101 [1]),
.I2(\dbns2/store101 [2]),
.I3(\dbns2/store101 [3]),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT310_431 )
);
LUT4 #(
.INIT ( 16'h2AA8 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT13 (
.I0(\addn_1/case001/cout [1]),
.I1(\dbns2/store101 [1]),
.I2(\dbns2/store101 [2]),
.I3(\dbns2/store101 [3]),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT12_439 )
);
LUT4 #(
.INIT ( 16'hFDFF ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT27 (
.I0(\dbns1/store100 [1]),
.I1(\dbns1/store100 [0]),
.I2(\dbns1/store100 [3]),
.I3(\dbns1/store100 [2]),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT15_460 )
);
LUT4 #(
.INIT ( 16'hFDFF ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT27 (
.I0(\dbns1/store001 [1]),
.I1(\dbns1/store001 [0]),
.I2(\dbns1/store001 [3]),
.I3(\dbns1/store001 [2]),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT15_487 )
);
LUT5 #(
.INIT ( 32'h01000000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT42 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [2]),
.I2(\dbns1/store100 [0]),
.I3(\dbns1/store100 [1]),
.I4(\addn_1/case100/_n0296[40] ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT41_463 )
);
LUT5 #(
.INIT ( 32'h01000000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT42 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [2]),
.I2(\dbns1/store001 [0]),
.I3(\dbns1/store001 [1]),
.I4(\addn_1/case001/_n0296[40] ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT41_490 )
);
LUT5 #(
.INIT ( 32'hFFFF1557 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT19_SW0 (
.I0(\dbns2/store001 [3]),
.I1(\dbns2/store001 [2]),
.I2(\dbns2/store001 [1]),
.I3(\dbns1/store001 [2]),
.I4(\dbns1/store001 [3]),
.O(N219)
);
LUT6 #(
.INIT ( 64'hFEEEFAAAFCCCF000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT47_SW0 (
.I0(\addn_1/case101/_n0296[34] ),
.I1(\addn_1/case101/_n0296[28] ),
.I2(\addn_1/case101/_n0296[22] ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT114_233 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT113_235 ),
.O(N235)
);
LUT5 #(
.INIT ( 32'hFFFF5540 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT48 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/_n0296[16] ),
.I2(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT45_420 ),
.I4(N235),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT47 )
);
LUT6 #(
.INIT ( 64'hFEFCFAF0EECCAA00 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT39_SW0 (
.I0(\addn_1/case101/_n0296[17] ),
.I1(\addn_1/case101/_n0296[40] ),
.I2(\addn_1/case101/_n0296[46] ),
.I3(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT113_235 ),
.I4(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.I5(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT114_233 ),
.O(N237)
);
LUT5 #(
.INIT ( 32'hFFFF5540 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT310 (
.I0(\addn_1/case001/cout [1]),
.I1(\addn_1/case101/_n0296[34] ),
.I2(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I3(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT312_433 ),
.I4(N237),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT314 )
);
LUT4 #(
.INIT ( 16'hFEEE ))
\addn_1/case100/input2[3]_input2[3]_mux_134_OUT<0>11 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [2]),
.I2(\dbns1/store100 [0]),
.I3(\dbns1/store100 [1]),
.O(\addn_1/case100/input2[3]_input2[3]_mux_134_OUT<0>1 )
);
LUT4 #(
.INIT ( 16'hFEEE ))
\addn_1/case001/input2[3]_input2[3]_mux_134_OUT<0>11 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [2]),
.I2(\dbns1/store001 [0]),
.I3(\dbns1/store001 [1]),
.O(\addn_1/case001/input2[3]_input2[3]_mux_134_OUT<0>1 )
);
LUT6 #(
.INIT ( 64'hF3F3F1F1F3F2F1F0 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT110 (
.I0(\addn_1/case001/cout [0]),
.I1(\addn_1/case001/cout [1]),
.I2(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT12 ),
.I3(N239),
.I4(N240),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT18_414 ),
.O(\addn_1/case101/out[3]_input2[3]_mux_204_OUT<0> )
);
LUT5 #(
.INIT ( 32'h1444FFFF ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT21131_SW0 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [2]),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [0]),
.I4(\addn_1/case100/SF2 ),
.O(N189)
);
LUT5 #(
.INIT ( 32'h1444FFFF ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT21131_SW0 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [2]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [0]),
.I4(\addn_1/case001/SF2 ),
.O(N191)
);
LUT6 #(
.INIT ( 64'h49C349C30CC30000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT44 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [3]),
.I2(\dbns2/store100 [2]),
.I3(\dbns2/store100 [1]),
.I4(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I5(\addn_1/case100/input1[3]_input1[3]_OR_7_o ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT43_465 )
);
LUT6 #(
.INIT ( 64'h240C240C300C0000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT34 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [3]),
.I2(\dbns2/store100 [2]),
.I3(\dbns2/store100 [1]),
.I4(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I5(\addn_1/case100/input1[3]_input1[3]_OR_7_o ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT37_469 )
);
LUT6 #(
.INIT ( 64'h49C349C30CC30000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT44 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [3]),
.I2(\dbns2/store001 [2]),
.I3(\dbns2/store001 [1]),
.I4(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I5(\addn_1/case001/input1[3]_input1[3]_OR_7_o ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT43_492 )
);
LUT6 #(
.INIT ( 64'h240C240C300C0000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT34 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [3]),
.I2(\dbns2/store001 [2]),
.I3(\dbns2/store001 [1]),
.I4(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT116 ),
.I5(\addn_1/case001/input1[3]_input1[3]_OR_7_o ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT37_496 )
);
LUT5 #(
.INIT ( 32'hEFFFEAFA ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT33_SW0 (
.I0(\dbns1/store100 [2]),
.I1(\dbns1/store100 [0]),
.I2(\dbns1/store100 [1]),
.I3(\addn_1/case100/_n0296[23] ),
.I4(N195),
.O(N242)
);
LUT6 #(
.INIT ( 64'hFCF0CC00FDF5DD55 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT33 (
.I0(\dbns1/store100 [3]),
.I1(\addn_1/case100/_n0296[16] ),
.I2(\addn_1/case100/_n0296[29] ),
.I3(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT33_300 ),
.I4(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT34_297 ),
.I5(N242),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT32 )
);
LUT5 #(
.INIT ( 32'hEFFFEAFA ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT33_SW0 (
.I0(\dbns1/store001 [2]),
.I1(\dbns1/store001 [0]),
.I2(\dbns1/store001 [1]),
.I3(\addn_1/case001/_n0296[23] ),
.I4(N199),
.O(N244)
);
LUT6 #(
.INIT ( 64'hFCF0CC00FDF5DD55 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT33 (
.I0(\dbns1/store001 [3]),
.I1(\addn_1/case001/_n0296[16] ),
.I2(\addn_1/case001/_n0296[29] ),
.I3(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT33_344 ),
.I4(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT34_341 ),
.I5(N244),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT32 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFAAA8A8A8 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT19_SW1 (
.I0(\addn_1/case101/input2[3]_input2[3]_mux_128_OUT<0> ),
.I1(\dbns1/store101 [3]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [1]),
.I4(\dbns1/store101 [0]),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT15_412 ),
.O(N240)
);
MUXF7 \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT29 (
.I0(N246),
.I1(N247),
.S(\addn_1/case001/cout [1]),
.O(\addn_1/case101/out[3]_input2[3]_mux_204_OUT<1> )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFAAAA2000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT29_F (
.I0(\addn_1/case001/cout [0]),
.I1(\addn_1/case101/input1[3]_input1[3]_OR_6_o ),
.I2(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I3(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT61 ),
.I4(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT22_395 ),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT27_398 ),
.O(N246)
);
LUT6 #(
.INIT ( 64'hAAA0FFFFAAA0EAAA ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT22_SW1 (
.I0(\dbns2/store100 [3]),
.I1(\dbns2/store100 [0]),
.I2(\dbns2/store100 [2]),
.I3(\dbns2/store100 [1]),
.I4(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT113 ),
.I5(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT111 ),
.O(N248)
);
LUT6 #(
.INIT ( 64'hFFFFDFF720080000 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT22 (
.I0(\dbns1/store100 [3]),
.I1(\dbns1/store100 [2]),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [0]),
.I4(N32),
.I5(N248),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT22_304 )
);
LUT6 #(
.INIT ( 64'hAAA0FFFFAAA0EAAA ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT22_SW1 (
.I0(\dbns2/store001 [3]),
.I1(\dbns2/store001 [0]),
.I2(\dbns2/store001 [2]),
.I3(\dbns2/store001 [1]),
.I4(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT113 ),
.I5(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT111 ),
.O(N250)
);
LUT6 #(
.INIT ( 64'hFFFFDFF720080000 ))
\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT22 (
.I0(\dbns1/store001 [3]),
.I1(\dbns1/store001 [2]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [0]),
.I4(N38),
.I5(N250),
.O(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT22_348 )
);
LUT6 #(
.INIT ( 64'h8292828282828282 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT15 (
.I0(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT33_344 ),
.I1(\dbns2/store001 [0]),
.I2(\dbns2/store001 [1]),
.I3(\dbns1/store001 [0]),
.I4(\dbns1/store001 [1]),
.I5(\addn_1/case001/_n0241 ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT14_486 )
);
LUT6 #(
.INIT ( 64'h8292828282828282 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT15 (
.I0(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT33_300 ),
.I1(\dbns2/store100 [0]),
.I2(\dbns2/store100 [1]),
.I3(\dbns1/store100 [0]),
.I4(\dbns1/store100 [1]),
.I5(\addn_1/case100/_n0241 ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT14_459 )
);
LUT6 #(
.INIT ( 64'h008022A2119133B3 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT23 (
.I0(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT34_341 ),
.I1(\addn_1/case001/_n0241 ),
.I2(\dbns2/store001 [1]),
.I3(\dbns2/store001 [0]),
.I4(N226),
.I5(N225),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT22 )
);
LUT2 #(
.INIT ( 4'h8 ))
\addn_1/case010/Mmux_out[3]_input2[3]_mux_204_OUT41 (
.I0(\dbns1/store010[2] ),
.I1(\dbns2/store010[2] ),
.O(\addn_1/case010/out[3]_input2[3]_mux_204_OUT<3> )
);
LUT2 #(
.INIT ( 4'h6 ))
\addn_1/case010/Mmux_out[3]_input2[3]_mux_204_OUT11 (
.I0(\dbns1/store010[0] ),
.I1(\dbns2/store010[0] ),
.O(\addn_1/case010/out[3]_input2[3]_mux_204_OUT<0> )
);
LUT4 #(
.INIT ( 16'h8808 ))
\addn_1/case010/Mmux_out[3]_input2[3]_mux_204_OUT21 (
.I0(\dbns2/store010[0] ),
.I1(\dbns1/store010[0] ),
.I2(\dbns1/store010[2] ),
.I3(\dbns2/store010[2] ),
.O(\addn_1/case010/out[3]_input2[3]_mux_204_OUT<1> )
);
LUT4 #(
.INIT ( 16'h693C ))
\dbns2/Maccum_remain_xor<1>11 (
.I0(\dbns2/remain [0]),
.I1(\dbns2/remain [1]),
.I2(\dbns2/shift [1]),
.I3(\dbns2/shift [0]),
.O(\dbns2/Result [1])
);
LUT4 #(
.INIT ( 16'h693C ))
\dbns1/Maccum_remain_xor<1>11 (
.I0(\dbns1/remain [0]),
.I1(\dbns1/remain [1]),
.I2(\dbns1/shift [1]),
.I3(\dbns1/shift [0]),
.O(\dbns1/Result [1])
);
LUT4 #(
.INIT ( 16'hFFA8 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT24 (
.I0(\dbns1/store100 [2]),
.I1(\dbns1/store100 [0]),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [3]),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT23_451 )
);
LUT4 #(
.INIT ( 16'hFFA8 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT24 (
.I0(\dbns1/store001 [2]),
.I1(\dbns1/store001 [0]),
.I2(\dbns1/store001 [1]),
.I3(\dbns1/store001 [3]),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT23_478 )
);
LUT4 #(
.INIT ( 16'hAAA8 ))
\addn_1/case100/_n0296<10>1 (
.I0(\dbns2/store100 [3]),
.I1(\dbns2/store100 [2]),
.I2(\dbns2/store100 [0]),
.I3(\dbns2/store100 [1]),
.O(\addn_1/case100/_n0296[10] )
);
LUT4 #(
.INIT ( 16'hAAA8 ))
\addn_1/case001/_n0296<10>1 (
.I0(\dbns2/store001 [3]),
.I1(\dbns2/store001 [2]),
.I2(\dbns2/store001 [0]),
.I3(\dbns2/store001 [1]),
.O(\addn_1/case001/_n0296[10] )
);
LUT6 #(
.INIT ( 64'h0000000202000000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT14 (
.I0(\dbns2/store100 [0]),
.I1(\dbns1/store100 [3]),
.I2(\dbns2/store100 [1]),
.I3(\dbns1/store100 [0]),
.I4(\dbns1/store100 [1]),
.I5(\dbns1/store100 [2]),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT13_458 )
);
LUT6 #(
.INIT ( 64'h0000000202000000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT14 (
.I0(\dbns2/store001 [0]),
.I1(\dbns1/store001 [3]),
.I2(\dbns2/store001 [1]),
.I3(\dbns1/store001 [0]),
.I4(\dbns1/store001 [1]),
.I5(\dbns1/store001 [2]),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT13_485 )
);
LUT4 #(
.INIT ( 16'h4924 ))
\addn_1/case000/Mmux_out[3]_input2[3]_mux_204_OUT211 (
.I0(\dbns2/store000 [0]),
.I1(\dbns2/store000 [1]),
.I2(\dbns1/store000 [0]),
.I3(\dbns1/store000 [1]),
.O(\addn_1/case000/out[3]_input2[3]_mux_204_OUT<1> )
);
LUT5 #(
.INIT ( 32'hA888FFFF ))
\dbns2/Mmux_r1[4]_GND_2_o_mux_65_OUT41 (
.I0(\dbns2/b [3]),
.I1(\dbns2/remain [2]),
.I2(\dbns2/remain [0]),
.I3(\dbns2/remain [1]),
.I4(\dbns2/b [4]),
.O(\dbns2/r1[4]_GND_2_o_mux_65_OUT<3> )
);
LUT2 #(
.INIT ( 4'h6 ))
\dbns2/Maccum_remain_xor<0>11 (
.I0(\dbns2/remain [0]),
.I1(\dbns2/shift [0]),
.O(\dbns2/Result [0])
);
LUT5 #(
.INIT ( 32'hA888FFFF ))
\dbns1/Mmux_r1[4]_GND_2_o_mux_65_OUT41 (
.I0(\dbns1/b [3]),
.I1(\dbns1/remain [2]),
.I2(\dbns1/remain [0]),
.I3(\dbns1/remain [1]),
.I4(\dbns1/b [4]),
.O(\dbns1/r1[4]_GND_2_o_mux_65_OUT<3> )
);
LUT2 #(
.INIT ( 4'h6 ))
\dbns1/Maccum_remain_xor<0>11 (
.I0(\dbns1/remain [0]),
.I1(\dbns1/shift [0]),
.O(\dbns1/Result [0])
);
LUT5 #(
.INIT ( 32'h00E00000 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT27 (
.I0(\dbns2/store101 [3]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [0]),
.I3(\dbns2/store101 [1]),
.I4(\addn_1/case101/input1[3]_GND_4_o_equal_17_o ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT26_397 )
);
LUT5 #(
.INIT ( 32'h40404000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT25 (
.I0(\dbns2/store100 [1]),
.I1(\dbns2/store100 [0]),
.I2(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT33_300 ),
.I3(\dbns2/store100 [2]),
.I4(\dbns2/store100 [3]),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT24_452 )
);
LUT5 #(
.INIT ( 32'h40404000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT25 (
.I0(\dbns2/store001 [1]),
.I1(\dbns2/store001 [0]),
.I2(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT33_344 ),
.I3(\dbns2/store001 [2]),
.I4(\dbns2/store001 [3]),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT24_479 )
);
LUT5 #(
.INIT ( 32'h22A20080 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT19_SW0 (
.I0(\addn_1/case101/input2[3]_input2[3]_mux_134_OUT<0>1 ),
.I1(\addn_1/case101/input1[3]_input1[3]_OR_6_o ),
.I2(\dbns2/store101 [0]),
.I3(\dbns2/store101 [1]),
.I4(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT61 ),
.O(N239)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFAAA8A8A8 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT29_G (
.I0(\addn_1/case101/input2[3]_input2[3]_mux_128_OUT<0> ),
.I1(\dbns1/store101 [3]),
.I2(\dbns1/store101 [2]),
.I3(\dbns1/store101 [0]),
.I4(\dbns1/store101 [1]),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT2 ),
.O(N247)
);
LUT2 #(
.INIT ( 4'h8 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT22_SW0 (
.I0(\dbns2/store101 [0]),
.I1(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT25_232 ),
.O(N264)
);
LUT6 #(
.INIT ( 64'h8080808080000000 ))
\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT22 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.I2(\dbns2/store101 [1]),
.I3(\addn_1/case001/cout [1]),
.I4(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT122 ),
.I5(N264),
.O(\addn_1/case101/Mmux_cout[1]_input2[3]_mux_205_OUT21 )
);
LUT6 #(
.INIT ( 64'h78871EE15AA50FF0 ))
\dbns2/Maccum_remain_xor<2>11 (
.I0(\dbns2/remain [1]),
.I1(\dbns2/remain [0]),
.I2(\dbns2/remain [2]),
.I3(\dbns2/shift [2]),
.I4(\dbns2/shift [1]),
.I5(\dbns2/shift [0]),
.O(\dbns2/Result [2])
);
LUT6 #(
.INIT ( 64'h78871EE15AA50FF0 ))
\dbns1/Maccum_remain_xor<2>11 (
.I0(\dbns1/remain [1]),
.I1(\dbns1/remain [0]),
.I2(\dbns1/remain [2]),
.I3(\dbns1/shift [2]),
.I4(\dbns1/shift [1]),
.I5(\dbns1/shift [0]),
.O(\dbns1/Result [2])
);
LUT2 #(
.INIT ( 4'h6 ))
\addn_1/case010/Mmux_out[3]_input2[3]_mux_204_OUT3 (
.I0(\dbns2/store010[2] ),
.I1(\dbns1/store010[2] ),
.O(\addn_1/case010/out[3]_input2[3]_mux_204_OUT<2> )
);
LUT4 #(
.INIT ( 16'h4924 ))
\addn_1/case000/Mmux_out[3]_input2[3]_mux_204_OUT12 (
.I0(\dbns2/store000 [1]),
.I1(\dbns1/store000 [0]),
.I2(\dbns1/store000 [1]),
.I3(\dbns2/store000 [0]),
.O(\addn_1/case000/out[3]_input2[3]_mux_204_OUT<0> )
);
LUT4 #(
.INIT ( 16'h8000 ))
\addn_1/case000/Mmux_out[3]_input2[3]_mux_204_OUT411 (
.I0(\dbns1/store000 [0]),
.I1(\dbns1/store000 [1]),
.I2(\dbns2/store000 [0]),
.I3(\dbns2/store000 [1]),
.O(\addn_1/case000/out[3]_input2[3]_mux_204_OUT<3> )
);
LUT6 #(
.INIT ( 64'h2092200220922222 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT19 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [1]),
.I2(\dbns1/store001 [0]),
.I3(\dbns1/store001 [1]),
.I4(\dbns1/store001 [3]),
.I5(\dbns1/store001 [2]),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT18 )
);
LUT4 #(
.INIT ( 16'h6EE8 ))
\addn_1/case000/Mmux_out[3]_input2[3]_mux_204_OUT31 (
.I0(\dbns2/store000 [1]),
.I1(\dbns1/store000 [1]),
.I2(\dbns1/store000 [0]),
.I3(\dbns2/store000 [0]),
.O(\addn_1/case000/out[3]_input2[3]_mux_204_OUT<2> )
);
LUT6 #(
.INIT ( 64'h4440000000004440 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT26 (
.I0(\dbns1/store001 [0]),
.I1(\dbns1/store001 [1]),
.I2(\dbns1/store001 [2]),
.I3(\dbns1/store001 [3]),
.I4(\dbns2/store001 [1]),
.I5(\dbns2/store001 [0]),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT25_480 )
);
LUT6 #(
.INIT ( 64'h4440000000004440 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT26 (
.I0(\dbns1/store100 [0]),
.I1(\dbns1/store100 [1]),
.I2(\dbns1/store100 [2]),
.I3(\dbns1/store100 [3]),
.I4(\dbns2/store100 [1]),
.I5(\dbns2/store100 [0]),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT25_453 )
);
FDE \dbns1/store101_0_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0496_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<0> ),
.Q(\dbns1/store101_0_1_606 )
);
FDE \dbns1/store101_3_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0496_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<3> ),
.Q(\dbns1/store101_3_1_607 )
);
FDE \dbns1/store101_1_1 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0496_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<1> ),
.Q(\dbns1/store101_1_1_608 )
);
LUT6 #(
.INIT ( 64'h2092200220922222 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT19 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [1]),
.I2(\dbns1/store100 [0]),
.I3(\dbns1/store100 [1]),
.I4(\dbns1/store100 [3]),
.I5(\dbns1/store100 [2]),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT18 )
);
LUT6 #(
.INIT ( 64'h2C4D0C49240C0000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT46 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [3]),
.I2(\dbns2/store100 [2]),
.I3(\dbns2/store100 [1]),
.I4(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT114 ),
.I5(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT45 )
);
LUT6 #(
.INIT ( 64'h2C4D0C49240C0000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT46 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [3]),
.I2(\dbns2/store001 [2]),
.I3(\dbns2/store001 [1]),
.I4(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT114 ),
.I5(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT45 )
);
LUT6 #(
.INIT ( 64'h8000C0808000FFFF ))
\addn_1/case101/SF21 (
.I0(\dbns2/store101 [0]),
.I1(\dbns2/store101 [2]),
.I2(\dbns2/store101 [3]),
.I3(\dbns2/store101 [1]),
.I4(\addn_1/case101/input1[3]_input1[3]_OR_7_o ),
.I5(\addn_1/case101/Mmux_input2[3]_input2[3]_mux_128_OUT13 ),
.O(\addn_1/case101/SF2 )
);
LUT6 #(
.INIT ( 64'h9B33933308000000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT45_SW0 (
.I0(\dbns1/store100 [2]),
.I1(\dbns1/store100 [3]),
.I2(\dbns1/store100 [0]),
.I3(\dbns1/store100 [1]),
.I4(\addn_1/case100/_n0296[40] ),
.I5(\addn_1/case100/_n0296[46] ),
.O(N134)
);
LUT6 #(
.INIT ( 64'h9B33080093330000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT35_SW0 (
.I0(\dbns1/store100 [2]),
.I1(\dbns1/store100 [3]),
.I2(\dbns1/store100 [0]),
.I3(\dbns1/store100 [1]),
.I4(\addn_1/case100/_n0296[29] ),
.I5(\addn_1/case100/_n0296[23] ),
.O(N136)
);
LUT6 #(
.INIT ( 64'h9B33933308000000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT45_SW0 (
.I0(\dbns1/store001 [2]),
.I1(\dbns1/store001 [3]),
.I2(\dbns1/store001 [0]),
.I3(\dbns1/store001 [1]),
.I4(\addn_1/case001/_n0296[40] ),
.I5(\addn_1/case001/_n0296[46] ),
.O(N138)
);
LUT6 #(
.INIT ( 64'h9B33080093330000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT35_SW0 (
.I0(\dbns1/store001 [2]),
.I1(\dbns1/store001 [3]),
.I2(\dbns1/store001 [0]),
.I3(\dbns1/store001 [1]),
.I4(\addn_1/case001/_n0296[29] ),
.I5(\addn_1/case001/_n0296[23] ),
.O(N140)
);
LUT6 #(
.INIT ( 64'hB234302492300000 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT36 (
.I0(\dbns2/store100 [0]),
.I1(\dbns2/store100 [3]),
.I2(\dbns2/store100 [2]),
.I3(\dbns2/store100 [1]),
.I4(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT114 ),
.I5(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT39 )
);
LUT6 #(
.INIT ( 64'hB234302492300000 ))
\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT36 (
.I0(\dbns2/store001 [0]),
.I1(\dbns2/store001 [3]),
.I2(\dbns2/store001 [2]),
.I3(\dbns2/store001 [1]),
.I4(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT114 ),
.I5(\addn_1/case001/Mmux_cout[1]_input2[3]_mux_205_OUT115 ),
.O(\addn_1/case001/Mmux_out[3]_input2[3]_mux_204_OUT39 )
);
FDE \dbns2/store101_1_1 (
.C(clock_BUFGP_10),
.CE(\dbns2/_n0496_inv ),
.D(\dbns2/r1[4]_GND_2_o_wide_mux_82_OUT<1> ),
.Q(\dbns2/store101_1_1_609 )
);
FDE \dbns1/store101_0_2 (
.C(clock_BUFGP_10),
.CE(\dbns1/_n0496_inv ),
.D(\dbns1/r1[4]_GND_2_o_wide_mux_82_OUT<0> ),
.Q(\dbns1/store101_0_2_610 )
);
LUT6 #(
.INIT ( 64'hB222226490202020 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT42 (
.I0(\dbns2/store101 [2]),
.I1(\dbns2/store101 [3]),
.I2(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT34_234 ),
.I3(\dbns2/store101 [1]),
.I4(\dbns2/store101 [0]),
.I5(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT35_230 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT41_416 )
);
BUFGP clock_BUFGP (
.I(clock),
.O(clock_BUFGP_10)
);
INV \dbns2/count_inv1_INV_0 (
.I(\dbns2/count_210 ),
.O(\dbns1/count_inv )
);
MUXF7 \addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT19 (
.I0(N266),
.I1(N267),
.S(\dbns1/store100 [1]),
.O(\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT18 )
);
LUT6 #(
.INIT ( 64'h2220202020202000 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT19_F (
.I0(\dbns1/store100 [0]),
.I1(\dbns1/store100 [3]),
.I2(\dbns2/store100 [3]),
.I3(\dbns2/store100 [1]),
.I4(\dbns1/store100 [2]),
.I5(\dbns2/store100 [2]),
.O(N266)
);
LUT5 #(
.INIT ( 32'h01000000 ))
\addn_1/case100/Mmux_cout[1]_input2[3]_mux_205_OUT19_G (
.I0(\dbns1/store100 [0]),
.I1(\dbns1/store100 [3]),
.I2(\dbns1/store100 [2]),
.I3(\dbns2/store100 [3]),
.I4(\addn_1/case100/_n0296<40>2 ),
.O(N267)
);
MUXF7 \addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT23 (
.I0(N268),
.I1(N269),
.S(\dbns2/store100 [0]),
.O(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT22 )
);
LUT5 #(
.INIT ( 32'h8888805A ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT23_F (
.I0(\dbns2/store100 [1]),
.I1(\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT34_297 ),
.I2(\dbns1/store100 [1]),
.I3(\dbns1/store100 [0]),
.I4(\addn_1/case100/_n0241 ),
.O(N268)
);
LUT6 #(
.INIT ( 64'h0404040414141410 ))
\addn_1/case100/Mmux_out[3]_input2[3]_mux_204_OUT23_G (
.I0(\addn_1/case100/_n0241 ),
.I1(\dbns2/store100 [1]),
.I2(\dbns1/store100 [0]),
.I3(\dbns2/store100 [2]),
.I4(\dbns2/store100 [3]),
.I5(\dbns1/store100 [1]),
.O(N269)
);
MUXF7 \dbns2/Mmux_b[4]_a[4]_mux_69_OUT511 (
.I0(N270),
.I1(N271),
.S(\dbns2/b [3]),
.O(\dbns2/Mmux_b[4]_a[4]_mux_69_OUT51 )
);
LUT6 #(
.INIT ( 64'hFF15FFFFFFFFFFFF ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT511_F (
.I0(\dbns2/remain [2]),
.I1(\dbns2/remain [1]),
.I2(\dbns2/remain [0]),
.I3(\dbns2/b [1]),
.I4(\dbns2/b [2]),
.I5(\dbns2/b [4]),
.O(N270)
);
LUT5 #(
.INIT ( 32'hD5FFFFFF ))
\dbns2/Mmux_b[4]_a[4]_mux_69_OUT511_G (
.I0(\dbns2/remain [2]),
.I1(\dbns2/b [0]),
.I2(\dbns2/b [1]),
.I3(\dbns2/b [2]),
.I4(\dbns2/b [4]),
.O(N271)
);
MUXF7 \dbns1/Mmux_b[4]_a[4]_mux_69_OUT511 (
.I0(N272),
.I1(N273),
.S(\dbns1/b [3]),
.O(\dbns1/Mmux_b[4]_a[4]_mux_69_OUT51 )
);
LUT6 #(
.INIT ( 64'hFF15FFFFFFFFFFFF ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT511_F (
.I0(\dbns1/remain [2]),
.I1(\dbns1/remain [1]),
.I2(\dbns1/remain [0]),
.I3(\dbns1/b [1]),
.I4(\dbns1/b [2]),
.I5(\dbns1/b [4]),
.O(N272)
);
LUT5 #(
.INIT ( 32'hD5FFFFFF ))
\dbns1/Mmux_b[4]_a[4]_mux_69_OUT511_G (
.I0(\dbns1/remain [2]),
.I1(\dbns1/b [0]),
.I2(\dbns1/b [1]),
.I3(\dbns1/b [2]),
.I4(\dbns1/b [4]),
.O(N273)
);
MUXF7 \addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT25 (
.I0(N274),
.I1(N275),
.S(\addn_1/case101/_n0296<42>1 ),
.O(\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT24 )
);
LUT6 #(
.INIT ( 64'h0001100010000510 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT25_F (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns1/store101 [1]),
.I3(\dbns2/store101 [1]),
.I4(\dbns1/store101 [0]),
.I5(\dbns2/store101 [0]),
.O(N274)
);
LUT6 #(
.INIT ( 64'h0010011010010050 ))
\addn_1/case101/Mmux_out[3]_input2[3]_mux_204_OUT25_G (
.I0(\dbns1/store101 [3]),
.I1(\dbns1/store101 [2]),
.I2(\dbns2/store101 [1]),
.I3(\dbns1/store101 [0]),
.I4(\dbns1/store101 [1]),
.I5(\dbns2/store101 [0]),
.O(N275)
);
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019
// Date : Fri Jul 16 06:51:34 2021
// Host : goeders-ssh8 running 64-bit Ubuntu 20.04.2 LTS
// Command : write_verilog -force -file /home/jaromharris/bfasst/build/xilinx_yosys_impl/basic/add32_r_rst/add32_impl.v
// Design : add32
// Purpose : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
// IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
// design files.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* ECO_CHECKSUM = "be08f03c" *)
(* STRUCTURAL_NETLIST = "yes" *)
module add32
(clk,
rst,
a,
b,
o);
input clk;
input rst;
input [31:0]a;
input [31:0]b;
output [31:0]o;
wire \<const0> ;
wire \<const1> ;
wire [31:0]a;
wire [31:0]a_IBUF;
wire [31:0]b;
wire [31:0]b_IBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire [31:0]o;
wire \o[11]_i_2_n_0 ;
wire \o[11]_i_3_n_0 ;
wire \o[11]_i_4_n_0 ;
wire \o[11]_i_5_n_0 ;
wire \o[15]_i_2_n_0 ;
wire \o[15]_i_3_n_0 ;
wire \o[15]_i_4_n_0 ;
wire \o[15]_i_5_n_0 ;
wire \o[19]_i_2_n_0 ;
wire \o[19]_i_3_n_0 ;
wire \o[19]_i_4_n_0 ;
wire \o[19]_i_5_n_0 ;
wire \o[23]_i_2_n_0 ;
wire \o[23]_i_3_n_0 ;
wire \o[23]_i_4_n_0 ;
wire \o[23]_i_5_n_0 ;
wire \o[27]_i_2_n_0 ;
wire \o[27]_i_3_n_0 ;
wire \o[27]_i_4_n_0 ;
wire \o[27]_i_5_n_0 ;
wire \o[31]_i_2_n_0 ;
wire \o[31]_i_3_n_0 ;
wire \o[31]_i_4_n_0 ;
wire \o[31]_i_5_n_0 ;
wire \o[3]_i_2_n_0 ;
wire \o[3]_i_3_n_0 ;
wire \o[3]_i_4_n_0 ;
wire \o[3]_i_5_n_0 ;
wire \o[7]_i_2_n_0 ;
wire \o[7]_i_3_n_0 ;
wire \o[7]_i_4_n_0 ;
wire \o[7]_i_5_n_0 ;
wire [31:0]o_OBUF;
wire \o_reg[11]_i_1_n_0 ;
wire \o_reg[15]_i_1_n_0 ;
wire \o_reg[19]_i_1_n_0 ;
wire \o_reg[23]_i_1_n_0 ;
wire \o_reg[27]_i_1_n_0 ;
wire \o_reg[3]_i_1_n_0 ;
wire \o_reg[7]_i_1_n_0 ;
wire [31:0]p_0_in;
wire rst;
wire rst_IBUF;
wire [3:0]\NLW_o_reg[11]_i_1_CO_UNCONNECTED ;
wire [3:0]\NLW_o_reg[15]_i_1_CO_UNCONNECTED ;
wire [3:0]\NLW_o_reg[19]_i_1_CO_UNCONNECTED ;
wire [3:0]\NLW_o_reg[23]_i_1_CO_UNCONNECTED ;
wire [3:0]\NLW_o_reg[27]_i_1_CO_UNCONNECTED ;
wire [3:0]\NLW_o_reg[3]_i_1_CO_UNCONNECTED ;
wire [3:0]\NLW_o_reg[7]_i_1_CO_UNCONNECTED ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
IBUF \a_IBUF[0]_inst
(.I(a[0]),
.O(a_IBUF[0]));
IBUF \a_IBUF[10]_inst
(.I(a[10]),
.O(a_IBUF[10]));
IBUF \a_IBUF[11]_inst
(.I(a[11]),
.O(a_IBUF[11]));
IBUF \a_IBUF[12]_inst
(.I(a[12]),
.O(a_IBUF[12]));
IBUF \a_IBUF[13]_inst
(.I(a[13]),
.O(a_IBUF[13]));
IBUF \a_IBUF[14]_inst
(.I(a[14]),
.O(a_IBUF[14]));
IBUF \a_IBUF[15]_inst
(.I(a[15]),
.O(a_IBUF[15]));
IBUF \a_IBUF[16]_inst
(.I(a[16]),
.O(a_IBUF[16]));
IBUF \a_IBUF[17]_inst
(.I(a[17]),
.O(a_IBUF[17]));
IBUF \a_IBUF[18]_inst
(.I(a[18]),
.O(a_IBUF[18]));
IBUF \a_IBUF[19]_inst
(.I(a[19]),
.O(a_IBUF[19]));
IBUF \a_IBUF[1]_inst
(.I(a[1]),
.O(a_IBUF[1]));
IBUF \a_IBUF[20]_inst
(.I(a[20]),
.O(a_IBUF[20]));
IBUF \a_IBUF[21]_inst
(.I(a[21]),
.O(a_IBUF[21]));
IBUF \a_IBUF[22]_inst
(.I(a[22]),
.O(a_IBUF[22]));
IBUF \a_IBUF[23]_inst
(.I(a[23]),
.O(a_IBUF[23]));
IBUF \a_IBUF[24]_inst
(.I(a[24]),
.O(a_IBUF[24]));
IBUF \a_IBUF[25]_inst
(.I(a[25]),
.O(a_IBUF[25]));
IBUF \a_IBUF[26]_inst
(.I(a[26]),
.O(a_IBUF[26]));
IBUF \a_IBUF[27]_inst
(.I(a[27]),
.O(a_IBUF[27]));
IBUF \a_IBUF[28]_inst
(.I(a[28]),
.O(a_IBUF[28]));
IBUF \a_IBUF[29]_inst
(.I(a[29]),
.O(a_IBUF[29]));
IBUF \a_IBUF[2]_inst
(.I(a[2]),
.O(a_IBUF[2]));
IBUF \a_IBUF[30]_inst
(.I(a[30]),
.O(a_IBUF[30]));
IBUF \a_IBUF[31]_inst
(.I(a[31]),
.O(a_IBUF[31]));
IBUF \a_IBUF[3]_inst
(.I(a[3]),
.O(a_IBUF[3]));
IBUF \a_IBUF[4]_inst
(.I(a[4]),
.O(a_IBUF[4]));
IBUF \a_IBUF[5]_inst
(.I(a[5]),
.O(a_IBUF[5]));
IBUF \a_IBUF[6]_inst
(.I(a[6]),
.O(a_IBUF[6]));
IBUF \a_IBUF[7]_inst
(.I(a[7]),
.O(a_IBUF[7]));
IBUF \a_IBUF[8]_inst
(.I(a[8]),
.O(a_IBUF[8]));
IBUF \a_IBUF[9]_inst
(.I(a[9]),
.O(a_IBUF[9]));
IBUF \b_IBUF[0]_inst
(.I(b[0]),
.O(b_IBUF[0]));
IBUF \b_IBUF[10]_inst
(.I(b[10]),
.O(b_IBUF[10]));
IBUF \b_IBUF[11]_inst
(.I(b[11]),
.O(b_IBUF[11]));
IBUF \b_IBUF[12]_inst
(.I(b[12]),
.O(b_IBUF[12]));
IBUF \b_IBUF[13]_inst
(.I(b[13]),
.O(b_IBUF[13]));
IBUF \b_IBUF[14]_inst
(.I(b[14]),
.O(b_IBUF[14]));
IBUF \b_IBUF[15]_inst
(.I(b[15]),
.O(b_IBUF[15]));
IBUF \b_IBUF[16]_inst
(.I(b[16]),
.O(b_IBUF[16]));
IBUF \b_IBUF[17]_inst
(.I(b[17]),
.O(b_IBUF[17]));
IBUF \b_IBUF[18]_inst
(.I(b[18]),
.O(b_IBUF[18]));
IBUF \b_IBUF[19]_inst
(.I(b[19]),
.O(b_IBUF[19]));
IBUF \b_IBUF[1]_inst
(.I(b[1]),
.O(b_IBUF[1]));
IBUF \b_IBUF[20]_inst
(.I(b[20]),
.O(b_IBUF[20]));
IBUF \b_IBUF[21]_inst
(.I(b[21]),
.O(b_IBUF[21]));
IBUF \b_IBUF[22]_inst
(.I(b[22]),
.O(b_IBUF[22]));
IBUF \b_IBUF[23]_inst
(.I(b[23]),
.O(b_IBUF[23]));
IBUF \b_IBUF[24]_inst
(.I(b[24]),
.O(b_IBUF[24]));
IBUF \b_IBUF[25]_inst
(.I(b[25]),
.O(b_IBUF[25]));
IBUF \b_IBUF[26]_inst
(.I(b[26]),
.O(b_IBUF[26]));
IBUF \b_IBUF[27]_inst
(.I(b[27]),
.O(b_IBUF[27]));
IBUF \b_IBUF[28]_inst
(.I(b[28]),
.O(b_IBUF[28]));
IBUF \b_IBUF[29]_inst
(.I(b[29]),
.O(b_IBUF[29]));
IBUF \b_IBUF[2]_inst
(.I(b[2]),
.O(b_IBUF[2]));
IBUF \b_IBUF[30]_inst
(.I(b[30]),
.O(b_IBUF[30]));
IBUF \b_IBUF[31]_inst
(.I(b[31]),
.O(b_IBUF[31]));
IBUF \b_IBUF[3]_inst
(.I(b[3]),
.O(b_IBUF[3]));
IBUF \b_IBUF[4]_inst
(.I(b[4]),
.O(b_IBUF[4]));
IBUF \b_IBUF[5]_inst
(.I(b[5]),
.O(b_IBUF[5]));
IBUF \b_IBUF[6]_inst
(.I(b[6]),
.O(b_IBUF[6]));
IBUF \b_IBUF[7]_inst
(.I(b[7]),
.O(b_IBUF[7]));
IBUF \b_IBUF[8]_inst
(.I(b[8]),
.O(b_IBUF[8]));
IBUF \b_IBUF[9]_inst
(.I(b[9]),
.O(b_IBUF[9]));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
LUT2 #(
.INIT(4'h6))
\o[11]_i_2
(.I0(a_IBUF[11]),
.I1(b_IBUF[11]),
.O(\o[11]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[11]_i_3
(.I0(a_IBUF[10]),
.I1(b_IBUF[10]),
.O(\o[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[11]_i_4
(.I0(a_IBUF[9]),
.I1(b_IBUF[9]),
.O(\o[11]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[11]_i_5
(.I0(a_IBUF[8]),
.I1(b_IBUF[8]),
.O(\o[11]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[15]_i_2
(.I0(a_IBUF[15]),
.I1(b_IBUF[15]),
.O(\o[15]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[15]_i_3
(.I0(a_IBUF[14]),
.I1(b_IBUF[14]),
.O(\o[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[15]_i_4
(.I0(a_IBUF[13]),
.I1(b_IBUF[13]),
.O(\o[15]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[15]_i_5
(.I0(a_IBUF[12]),
.I1(b_IBUF[12]),
.O(\o[15]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[19]_i_2
(.I0(a_IBUF[19]),
.I1(b_IBUF[19]),
.O(\o[19]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[19]_i_3
(.I0(a_IBUF[18]),
.I1(b_IBUF[18]),
.O(\o[19]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[19]_i_4
(.I0(a_IBUF[17]),
.I1(b_IBUF[17]),
.O(\o[19]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[19]_i_5
(.I0(a_IBUF[16]),
.I1(b_IBUF[16]),
.O(\o[19]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[23]_i_2
(.I0(a_IBUF[23]),
.I1(b_IBUF[23]),
.O(\o[23]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[23]_i_3
(.I0(a_IBUF[22]),
.I1(b_IBUF[22]),
.O(\o[23]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[23]_i_4
(.I0(a_IBUF[21]),
.I1(b_IBUF[21]),
.O(\o[23]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[23]_i_5
(.I0(a_IBUF[20]),
.I1(b_IBUF[20]),
.O(\o[23]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[27]_i_2
(.I0(a_IBUF[27]),
.I1(b_IBUF[27]),
.O(\o[27]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[27]_i_3
(.I0(a_IBUF[26]),
.I1(b_IBUF[26]),
.O(\o[27]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[27]_i_4
(.I0(a_IBUF[25]),
.I1(b_IBUF[25]),
.O(\o[27]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[27]_i_5
(.I0(a_IBUF[24]),
.I1(b_IBUF[24]),
.O(\o[27]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[31]_i_2
(.I0(a_IBUF[31]),
.I1(b_IBUF[31]),
.O(\o[31]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[31]_i_3
(.I0(a_IBUF[30]),
.I1(b_IBUF[30]),
.O(\o[31]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[31]_i_4
(.I0(a_IBUF[29]),
.I1(b_IBUF[29]),
.O(\o[31]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[31]_i_5
(.I0(a_IBUF[28]),
.I1(b_IBUF[28]),
.O(\o[31]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[3]_i_2
(.I0(a_IBUF[3]),
.I1(b_IBUF[3]),
.O(\o[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[3]_i_3
(.I0(a_IBUF[2]),
.I1(b_IBUF[2]),
.O(\o[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[3]_i_4
(.I0(a_IBUF[1]),
.I1(b_IBUF[1]),
.O(\o[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[3]_i_5
(.I0(a_IBUF[0]),
.I1(b_IBUF[0]),
.O(\o[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[7]_i_2
(.I0(a_IBUF[7]),
.I1(b_IBUF[7]),
.O(\o[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[7]_i_3
(.I0(a_IBUF[6]),
.I1(b_IBUF[6]),
.O(\o[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[7]_i_4
(.I0(a_IBUF[5]),
.I1(b_IBUF[5]),
.O(\o[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\o[7]_i_5
(.I0(a_IBUF[4]),
.I1(b_IBUF[4]),
.O(\o[7]_i_5_n_0 ));
OBUF \o_OBUF[0]_inst
(.I(o_OBUF[0]),
.O(o[0]));
OBUF \o_OBUF[10]_inst
(.I(o_OBUF[10]),
.O(o[10]));
OBUF \o_OBUF[11]_inst
(.I(o_OBUF[11]),
.O(o[11]));
OBUF \o_OBUF[12]_inst
(.I(o_OBUF[12]),
.O(o[12]));
OBUF \o_OBUF[13]_inst
(.I(o_OBUF[13]),
.O(o[13]));
OBUF \o_OBUF[14]_inst
(.I(o_OBUF[14]),
.O(o[14]));
OBUF \o_OBUF[15]_inst
(.I(o_OBUF[15]),
.O(o[15]));
OBUF \o_OBUF[16]_inst
(.I(o_OBUF[16]),
.O(o[16]));
OBUF \o_OBUF[17]_inst
(.I(o_OBUF[17]),
.O(o[17]));
OBUF \o_OBUF[18]_inst
(.I(o_OBUF[18]),
.O(o[18]));
OBUF \o_OBUF[19]_inst
(.I(o_OBUF[19]),
.O(o[19]));
OBUF \o_OBUF[1]_inst
(.I(o_OBUF[1]),
.O(o[1]));
OBUF \o_OBUF[20]_inst
(.I(o_OBUF[20]),
.O(o[20]));
OBUF \o_OBUF[21]_inst
(.I(o_OBUF[21]),
.O(o[21]));
OBUF \o_OBUF[22]_inst
(.I(o_OBUF[22]),
.O(o[22]));
OBUF \o_OBUF[23]_inst
(.I(o_OBUF[23]),
.O(o[23]));
OBUF \o_OBUF[24]_inst
(.I(o_OBUF[24]),
.O(o[24]));
OBUF \o_OBUF[25]_inst
(.I(o_OBUF[25]),
.O(o[25]));
OBUF \o_OBUF[26]_inst
(.I(o_OBUF[26]),
.O(o[26]));
OBUF \o_OBUF[27]_inst
(.I(o_OBUF[27]),
.O(o[27]));
OBUF \o_OBUF[28]_inst
(.I(o_OBUF[28]),
.O(o[28]));
OBUF \o_OBUF[29]_inst
(.I(o_OBUF[29]),
.O(o[29]));
OBUF \o_OBUF[2]_inst
(.I(o_OBUF[2]),
.O(o[2]));
OBUF \o_OBUF[30]_inst
(.I(o_OBUF[30]),
.O(o[30]));
OBUF \o_OBUF[31]_inst
(.I(o_OBUF[31]),
.O(o[31]));
OBUF \o_OBUF[3]_inst
(.I(o_OBUF[3]),
.O(o[3]));
OBUF \o_OBUF[4]_inst
(.I(o_OBUF[4]),
.O(o[4]));
OBUF \o_OBUF[5]_inst
(.I(o_OBUF[5]),
.O(o[5]));
OBUF \o_OBUF[6]_inst
(.I(o_OBUF[6]),
.O(o[6]));
OBUF \o_OBUF[7]_inst
(.I(o_OBUF[7]),
.O(o[7]));
OBUF \o_OBUF[8]_inst
(.I(o_OBUF[8]),
.O(o[8]));
OBUF \o_OBUF[9]_inst
(.I(o_OBUF[9]),
.O(o[9]));
FDRE #(
.INIT(1'b0))
\o_reg[0]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[0]),
.Q(o_OBUF[0]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[10]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[10]),
.Q(o_OBUF[10]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[11]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[11]),
.Q(o_OBUF[11]),
.R(rst_IBUF));
(* OPT_MODIFIED = "SWEEP" *)
CARRY4 \o_reg[11]_i_1
(.CI(\o_reg[7]_i_1_n_0 ),
.CO({\o_reg[11]_i_1_n_0 ,\NLW_o_reg[11]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(\<const0> ),
.DI(a_IBUF[11:8]),
.O(p_0_in[11:8]),
.S({\o[11]_i_2_n_0 ,\o[11]_i_3_n_0 ,\o[11]_i_4_n_0 ,\o[11]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\o_reg[12]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[12]),
.Q(o_OBUF[12]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[13]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[13]),
.Q(o_OBUF[13]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[14]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[14]),
.Q(o_OBUF[14]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[15]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[15]),
.Q(o_OBUF[15]),
.R(rst_IBUF));
(* OPT_MODIFIED = "SWEEP" *)
CARRY4 \o_reg[15]_i_1
(.CI(\o_reg[11]_i_1_n_0 ),
.CO({\o_reg[15]_i_1_n_0 ,\NLW_o_reg[15]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(\<const0> ),
.DI(a_IBUF[15:12]),
.O(p_0_in[15:12]),
.S({\o[15]_i_2_n_0 ,\o[15]_i_3_n_0 ,\o[15]_i_4_n_0 ,\o[15]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\o_reg[16]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[16]),
.Q(o_OBUF[16]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[17]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[17]),
.Q(o_OBUF[17]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[18]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[18]),
.Q(o_OBUF[18]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[19]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[19]),
.Q(o_OBUF[19]),
.R(rst_IBUF));
(* OPT_MODIFIED = "SWEEP" *)
CARRY4 \o_reg[19]_i_1
(.CI(\o_reg[15]_i_1_n_0 ),
.CO({\o_reg[19]_i_1_n_0 ,\NLW_o_reg[19]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(\<const0> ),
.DI(a_IBUF[19:16]),
.O(p_0_in[19:16]),
.S({\o[19]_i_2_n_0 ,\o[19]_i_3_n_0 ,\o[19]_i_4_n_0 ,\o[19]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\o_reg[1]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[1]),
.Q(o_OBUF[1]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[20]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[20]),
.Q(o_OBUF[20]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[21]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[21]),
.Q(o_OBUF[21]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[22]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[22]),
.Q(o_OBUF[22]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[23]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[23]),
.Q(o_OBUF[23]),
.R(rst_IBUF));
(* OPT_MODIFIED = "SWEEP" *)
CARRY4 \o_reg[23]_i_1
(.CI(\o_reg[19]_i_1_n_0 ),
.CO({\o_reg[23]_i_1_n_0 ,\NLW_o_reg[23]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(\<const0> ),
.DI(a_IBUF[23:20]),
.O(p_0_in[23:20]),
.S({\o[23]_i_2_n_0 ,\o[23]_i_3_n_0 ,\o[23]_i_4_n_0 ,\o[23]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\o_reg[24]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[24]),
.Q(o_OBUF[24]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[25]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[25]),
.Q(o_OBUF[25]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[26]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[26]),
.Q(o_OBUF[26]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[27]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[27]),
.Q(o_OBUF[27]),
.R(rst_IBUF));
(* OPT_MODIFIED = "SWEEP" *)
CARRY4 \o_reg[27]_i_1
(.CI(\o_reg[23]_i_1_n_0 ),
.CO({\o_reg[27]_i_1_n_0 ,\NLW_o_reg[27]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(\<const0> ),
.DI(a_IBUF[27:24]),
.O(p_0_in[27:24]),
.S({\o[27]_i_2_n_0 ,\o[27]_i_3_n_0 ,\o[27]_i_4_n_0 ,\o[27]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\o_reg[28]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[28]),
.Q(o_OBUF[28]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[29]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[29]),
.Q(o_OBUF[29]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[2]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[2]),
.Q(o_OBUF[2]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[30]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[30]),
.Q(o_OBUF[30]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[31]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[31]),
.Q(o_OBUF[31]),
.R(rst_IBUF));
(* OPT_MODIFIED = "SWEEP" *)
CARRY4 \o_reg[31]_i_1
(.CI(\o_reg[27]_i_1_n_0 ),
.CYINIT(\<const0> ),
.DI({\<const0> ,a_IBUF[30:28]}),
.O(p_0_in[31:28]),
.S({\o[31]_i_2_n_0 ,\o[31]_i_3_n_0 ,\o[31]_i_4_n_0 ,\o[31]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\o_reg[3]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[3]),
.Q(o_OBUF[3]),
.R(rst_IBUF));
(* OPT_MODIFIED = "SWEEP" *)
CARRY4 \o_reg[3]_i_1
(.CI(\<const0> ),
.CO({\o_reg[3]_i_1_n_0 ,\NLW_o_reg[3]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(\<const0> ),
.DI(a_IBUF[3:0]),
.O(p_0_in[3:0]),
.S({\o[3]_i_2_n_0 ,\o[3]_i_3_n_0 ,\o[3]_i_4_n_0 ,\o[3]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\o_reg[4]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[4]),
.Q(o_OBUF[4]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[5]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[5]),
.Q(o_OBUF[5]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[6]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[6]),
.Q(o_OBUF[6]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[7]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[7]),
.Q(o_OBUF[7]),
.R(rst_IBUF));
(* OPT_MODIFIED = "SWEEP" *)
CARRY4 \o_reg[7]_i_1
(.CI(\o_reg[3]_i_1_n_0 ),
.CO({\o_reg[7]_i_1_n_0 ,\NLW_o_reg[7]_i_1_CO_UNCONNECTED [2:0]}),
.CYINIT(\<const0> ),
.DI(a_IBUF[7:4]),
.O(p_0_in[7:4]),
.S({\o[7]_i_2_n_0 ,\o[7]_i_3_n_0 ,\o[7]_i_4_n_0 ,\o[7]_i_5_n_0 }));
FDRE #(
.INIT(1'b0))
\o_reg[8]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[8]),
.Q(o_OBUF[8]),
.R(rst_IBUF));
FDRE #(
.INIT(1'b0))
\o_reg[9]
(.C(clk_IBUF_BUFG),
.CE(\<const1> ),
.D(p_0_in[9]),
.Q(o_OBUF[9]),
.R(rst_IBUF));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__BUF_FUNCTIONAL_PP_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__buf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUF_FUNCTIONAL_PP_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood_pp$PG (
UDP_OUT,
UDP_IN ,
VPWR ,
VGND
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_PG_BLACKBOX_V
|
// file: Clock50MHz_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module Clock50MHz_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
Clock50MHz_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
module gayle_fifo
(
input clk, // bus clock
input clk7_en,
input reset, // reset
input [15:0] data_in, // data in
output reg [15:0] data_out, // data out
input rd, // read from fifo
input wr, // write to fifo
output full, // fifo is full
output empty, // fifo is empty
output last // the last word of a sector is being read
);
// local signals and registers
reg [15:0] mem [4095:0]; // 16 bit wide fifo memory
reg [12:0] inptr; // fifo input pointer
reg [12:0] outptr; // fifo output pointer
wire empty_rd; // fifo empty flag (set immediately after reading the last word)
reg empty_wr; // fifo empty flag (set one clock after writting the empty fifo)
// main fifo memory (implemented using synchronous block ram)
always @(posedge clk)
if (clk7_en) begin
if (wr)
mem[inptr[11:0]] <= data_in;
end
always @(posedge clk)
if (clk7_en) begin
data_out <= mem[outptr[11:0]];
end
// fifo write pointer control
always @(posedge clk)
if (clk7_en) begin
if (reset)
inptr <= 12'd0;
else if (wr)
inptr <= inptr + 12'd1;
end
// fifo read pointer control
always @(posedge clk)
if (clk7_en) begin
if (reset)
outptr <= 0;
else if (rd)
outptr <= outptr + 13'd1;
end
// the empty flag is set immediately after reading the last word from the fifo
assign empty_rd = inptr==outptr ? 1'b1 : 1'b0;
// after writting empty fifo the empty flag is delayed by one clock to handle ram write delay
always @(posedge clk)
if (clk7_en) begin
empty_wr <= empty_rd;
end
assign empty = empty_rd | empty_wr;
// at least 512 bytes are in FIFO
// this signal is activated when 512th byte is written to the empty fifo
// then it's deactivated when 512th byte is read from the fifo (hysteresis)
assign full = inptr[12:8]!=outptr[12:8] ? 1'b1 : 1'b0;
assign last = outptr[7:0] == 8'hFF ? 1'b1 : 1'b0;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_mux.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module arb_mux #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_VECT_INDX = 11,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter CS_WIDTH = 4,
parameter CWL = 5,
parameter DATA_BUF_ADDR_VECT_INDX = 31,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # DRAM CKs per fabric CLKs
parameter nCS_PER_RANK = 1,
parameter nCNFG2WR = 2,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nSLOTS = 2,
parameter nWR = 6, // Write recovery (CKs)
parameter RANK_VECT_INDX = 15,
parameter RANK_WIDTH = 2,
parameter ROW_VECT_INDX = 63,
parameter ROW_WIDTH = 16,
parameter RTT_NOM = "40",
parameter RTT_WR = "120",
parameter SLOT_0_CONFIG = 8'b0000_0101,
parameter SLOT_1_CONFIG = 8'b0000_1010
)
(/*AUTOARG*/
// Outputs
output [ROW_WIDTH-1:0] col_a, // From arb_select0 of arb_select.v
output [BANK_WIDTH-1:0] col_ba, // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr,// From arb_select0 of arb_select.v
output col_periodic_rd, // From arb_select0 of arb_select.v
output [RANK_WIDTH-1:0] col_ra, // From arb_select0 of arb_select.v
output col_rmw, // From arb_select0 of arb_select.v
output col_rd_wr,
output [ROW_WIDTH-1:0] col_row, // From arb_select0 of arb_select.v
output col_size, // From arb_select0 of arb_select.v
output [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr,// From arb_select0 of arb_select.v
output wire [nCK_PER_CLK-1:0] mc_ras_n,
output wire [nCK_PER_CLK-1:0] mc_cas_n,
output wire [nCK_PER_CLK-1:0] mc_we_n,
output wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
output wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
output wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
output wire [3:0] mc_aux_out0,
output wire [3:0] mc_aux_out1,
output [2:0] mc_cmd,
output [5:0] mc_data_offset,
output [1:0] mc_cas_slot,
output [RANK_WIDTH:0] io_config, // From arb_select0 of arb_select.v
output io_config_valid_r, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_row, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_pre,
output sent_col, // From arb_row_col0 of arb_row_col.v
output sent_row, // From arb_row_col0 of arb_row_col.v
output [nBANK_MACHS-1:0] sending_col,
output io_config_strobe,
output insert_maint_r1,
// Inputs
input clk,
input rst,
input init_calib_complete,
input [5:0] calib_rddata_offset,
input [ROW_VECT_INDX:0] col_addr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] col_rdy_wr, // To arb_row_col0 of arb_row_col.v
input force_io_config_rd_r, // To arb_row_col0 of arb_row_col.v
input insert_maint_r, // To arb_row_col0 of arb_row_col.v
input [RANK_WIDTH-1:0] maint_rank_r, // To arb_select0 of arb_select.v
input maint_zq_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rd_wr_r, // To arb_select0 of arb_select.v
input [BANK_VECT_INDX:0] req_bank_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_cas, // To arb_select0 of arb_select.v
input [DATA_BUF_ADDR_VECT_INDX:0] req_data_buf_addr_r,// To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_periodic_rd_r, // To arb_select0 of arb_select.v
input [RANK_VECT_INDX:0] req_rank_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_ras, // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] req_row_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_size_r, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] req_wr_r, // To arb_select0 of arb_select.v
input [ROW_VECT_INDX:0] row_addr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] row_cmd_wr, // To arb_select0 of arb_select.v
input [nBANK_MACHS-1:0] rtc, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_col, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_row, // To arb_row_col0 of arb_row_col.v
input [nBANK_MACHS-1:0] rts_pre, // To arb_row_col0 of arb_row_col.v
input [7:0] slot_0_present, // To arb_select0 of arb_select.v
input [7:0] slot_1_present // To arb_select0 of arb_select.v
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire cs_en0; // From arb_row_col0 of arb_row_col.v
wire cs_en1; // From arb_row_col0 of arb_row_col.v
wire force_io_config_rd_r1; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_col_wr; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_config_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_row_r; // From arb_row_col0 of arb_row_col.v
wire [nBANK_MACHS-1:0] grant_pre_r; // From arb_row_col0 of arb_row_col.v
wire send_cmd0_col; // From arb_row_col0 of arb_row_col.v
wire send_cmd1_row; // From arb_row_col0 of arb_row_col.v
wire send_cmd1_col;
wire send_cmd1_pre;
wire send_cmd2_col;
wire send_cmd2_pre;
wire send_cmd3_col;
wire send_cmd3_pre;
wire [5:0] col_channel_offset;
// End of automatics
wire sent_col_i;
assign sent_col = sent_col_i;
arb_row_col #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.CWL (CWL),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCNFG2WR (nCNFG2WR),
.nRAS (nRAS),
.nRCD (nRCD),
.nWR (nWR))
arb_row_col0
(/*AUTOINST*/
// Outputs
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
.sent_row (sent_row),
.sending_row (sending_row[nBANK_MACHS-1:0]),
.sending_pre (sending_pre[nBANK_MACHS-1:0]),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.io_config_strobe (io_config_strobe),
.force_io_config_rd_r1 (force_io_config_rd_r1),
.io_config_valid_r (io_config_valid_r),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.sending_col (sending_col[nBANK_MACHS-1:0]),
.sent_col (sent_col_i),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.send_cmd1_col (send_cmd1_col),
.send_cmd1_pre (send_cmd1_pre),
.send_cmd2_col (send_cmd2_col),
.send_cmd2_pre (send_cmd2_pre),
.send_cmd3_col (send_cmd3_col),
.send_cmd3_pre (send_cmd3_pre),
.col_channel_offset (col_channel_offset),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.cs_en2 (cs_en2),
.cs_en3 (cs_en3),
.insert_maint_r1 (insert_maint_r1),
// Inputs
.clk (clk),
.rst (rst),
.rts_row (rts_row[nBANK_MACHS-1:0]),
.rts_pre (rts_pre[nBANK_MACHS-1:0]),
.insert_maint_r (insert_maint_r),
.rts_col (rts_col[nBANK_MACHS-1:0]),
.rtc (rtc[nBANK_MACHS-1:0]),
.force_io_config_rd_r (force_io_config_rd_r),
.col_rdy_wr (col_rdy_wr[nBANK_MACHS-1:0]));
arb_select #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_VECT_INDX (BANK_VECT_INDX),
.BANK_WIDTH (BANK_WIDTH),
.BURST_MODE (BURST_MODE),
.CS_WIDTH (CS_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_VECT_INDX (DATA_BUF_ADDR_VECT_INDX),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.EARLY_WR_DATA_ADDR (EARLY_WR_DATA_ADDR),
.ECC (ECC),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nCS_PER_RANK (nCS_PER_RANK),
.nSLOTS (nSLOTS),
.RANK_VECT_INDX (RANK_VECT_INDX),
.RANK_WIDTH (RANK_WIDTH),
.ROW_VECT_INDX (ROW_VECT_INDX),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG))
arb_select0
(/*AUTOINST*/
// Outputs
.col_periodic_rd (col_periodic_rd),
.col_ra (col_ra[RANK_WIDTH-1:0]),
.col_ba (col_ba[BANK_WIDTH-1:0]),
.col_a (col_a[ROW_WIDTH-1:0]),
.col_rmw (col_rmw),
.col_rd_wr (col_rd_wr),
.col_size (col_size),
.col_row (col_row[ROW_WIDTH-1:0]),
.col_data_buf_addr (col_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.col_wr_data_buf_addr (col_wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.mc_bank (mc_bank),
.mc_address (mc_address),
.mc_ras_n (mc_ras_n),
.mc_cas_n (mc_cas_n),
.mc_we_n (mc_we_n),
.mc_cs_n (mc_cs_n),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_cmd (mc_cmd),
.mc_data_offset (mc_data_offset),
.mc_cas_slot (mc_cas_slot),
.col_channel_offset (col_channel_offset),
.io_config (io_config[RANK_WIDTH:0]),
// Inputs
.clk (clk),
.rst (rst),
.init_calib_complete (init_calib_complete),
.calib_rddata_offset (calib_rddata_offset),
.req_rank_r (req_rank_r[RANK_VECT_INDX:0]),
.req_bank_r (req_bank_r[BANK_VECT_INDX:0]),
.req_ras (req_ras[nBANK_MACHS-1:0]),
.req_cas (req_cas[nBANK_MACHS-1:0]),
.req_wr_r (req_wr_r[nBANK_MACHS-1:0]),
.grant_row_r (grant_row_r[nBANK_MACHS-1:0]),
.grant_pre_r (grant_pre_r[nBANK_MACHS-1:0]),
.row_addr (row_addr[ROW_VECT_INDX:0]),
.row_cmd_wr (row_cmd_wr[nBANK_MACHS-1:0]),
.insert_maint_r1 (insert_maint_r1),
.maint_zq_r (maint_zq_r),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r[nBANK_MACHS-1:0]),
.req_size_r (req_size_r[nBANK_MACHS-1:0]),
.rd_wr_r (rd_wr_r[nBANK_MACHS-1:0]),
.req_row_r (req_row_r[ROW_VECT_INDX:0]),
.col_addr (col_addr[ROW_VECT_INDX:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_VECT_INDX:0]),
.grant_col_r (grant_col_r[nBANK_MACHS-1:0]),
.grant_col_wr (grant_col_wr[nBANK_MACHS-1:0]),
.send_cmd0_col (send_cmd0_col),
.send_cmd1_row (send_cmd1_row),
.send_cmd1_col (send_cmd1_col),
.send_cmd1_pre (send_cmd1_pre),
.send_cmd2_col (send_cmd2_col),
.send_cmd2_pre (send_cmd2_pre),
.send_cmd3_col (send_cmd3_col),
.send_cmd3_pre (send_cmd3_pre),
.sent_col (sent_col_i),
.cs_en0 (cs_en0),
.cs_en1 (cs_en1),
.cs_en2 (cs_en2),
.cs_en3 (cs_en3),
.force_io_config_rd_r1 (force_io_config_rd_r1),
.grant_config_r (grant_config_r[nBANK_MACHS-1:0]),
.io_config_strobe (io_config_strobe),
.slot_0_present (slot_0_present[7:0]),
.slot_1_present (slot_1_present[7:0]));
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sat Nov 19 20:29:56 2016
/////////////////////////////////////////////////////////////
module FPU_PIPELINED_FPADDSUB_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_OP,
Data_X, Data_Y, add_subt, busy, overflow_flag, underflow_flag,
zero_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
output [63:0] final_result_ieee;
input clk, rst, beg_OP, add_subt;
output busy, overflow_flag, underflow_flag, zero_flag, ready;
wire Shift_reg_FLAGS_7_6, Shift_reg_FLAGS_7_5, intAS, SIGN_FLAG_EXP,
OP_FLAG_EXP, ZERO_FLAG_EXP, SIGN_FLAG_SHT1, OP_FLAG_SHT1,
ZERO_FLAG_SHT1, Data_array_SWR_3__53_, left_right_SHT2,
SIGN_FLAG_SHT2, OP_FLAG_SHT2, ZERO_FLAG_SHT2, SIGN_FLAG_SHT1SHT2,
ZERO_FLAG_SHT1SHT2, SIGN_FLAG_NRM, ZERO_FLAG_NRM, SIGN_FLAG_SFG,
ZERO_FLAG_SFG, inst_FSM_INPUT_ENABLE_state_next_1_, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1065, n1066, n1067, n1068, n1075, n1076, n1077,
n1078, n1079, n1080, n1082, n1083, n1085, n1086, n1089, n1090, n1091,
n1094, n1095, n1096, n1097, n1098, n1099, n1102, n1103, n1104, n1105,
n1107, n1108, n1110, n1111, n1112, n1113, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1155, n1156, n1157, n1158, n1159, n1160,
n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170,
n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180,
n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1607, n1608, n1609, n1626, n1627, n1628,
n1635, n1644, n1645, n1663, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1848, n1849, n1850, n1851, n1852, n1853, n1854,
n1856, n1857, n1859, n1860, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1881, n1882, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1986, n1987, n1988, n1989, n1990, n1991,
n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001,
n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2119, n2120, n2121, n2122, n2123,
n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133,
n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143,
n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153,
n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163,
n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173,
n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183,
n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193,
n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203,
n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213,
n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223,
n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233,
n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243,
n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253,
n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263,
n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273,
n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283,
n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434,
n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444,
n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454,
n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464,
n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474,
n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484,
n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494,
n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2601, n2602, n2603, n2604, n2605, n2606,
n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615, n2616,
n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625, n2626,
n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635, n2636,
n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645, n2646,
n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655, n2656,
n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665, n2666,
n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675, n2676,
n2677, n2678, n2679, n2681, n2682, n2683, n2684, n2685, n2686, n2687,
n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695, n2697, n2698,
n2699, n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769,
n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859,
n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869,
n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2944, n2945, n2946, n2947, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991,
n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001,
n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011,
n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021,
n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051,
n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061,
n3062, n3063, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093,
n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255,
n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265,
n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275,
n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285,
n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295,
n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305,
n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315,
n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325,
n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335,
n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345,
n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355,
n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365,
n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375,
n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385,
n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395,
n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405,
n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415,
n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425,
n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435,
n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445,
n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455,
n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465,
n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535,
n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545,
n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555,
n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565,
n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575,
n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585,
n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595,
n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605,
n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615,
n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625,
n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635,
n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645,
n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655,
n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665,
n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675,
n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685,
n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695,
n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3991, n3992, n3993, n3994, n3995, n3996,
n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005, n4006,
n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015, n4016,
n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025, n4026,
n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035, n4036,
n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045, n4046,
n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055, n4056,
n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065, n4066,
n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075, n4076,
n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085, n4086,
n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095, n4096,
n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105, n4106,
n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116,
n4117, n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126, n4127,
n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136, n4137,
n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146, n4147,
n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156, n4157,
n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166, n4167,
n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176, n4177,
n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186, n4187,
n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196, n4197,
n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206, n4207,
n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216, n4217,
n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226, n4227,
n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236, n4237,
n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246, n4247,
n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256, n4257,
n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266, n4267,
n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276, n4277,
n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286, n4288,
n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298,
n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308,
n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318,
n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328,
n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338,
n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348,
n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358,
n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368,
n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376, n4377, n4378,
n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386, n4387, n4388,
n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396, n4397, n4398,
n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406, n4407, n4408,
n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416, n4417, n4418,
n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426, n4427, n4428,
n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436, n4437, n4438,
n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446, n4447, n4448,
n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456, n4457, n4458,
n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466, n4467, n4468,
n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476, n4477, n4478,
n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486, n4487, n4488,
n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496, n4497, n4498,
n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506, n4507, n4508,
n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516, n4517, n4518,
n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526, n4527, n4528,
n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536, n4537, n4538,
n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546, n4547, n4548,
n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556, n4557, n4558,
n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566, n4567, n4568,
n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576, n4577, n4578,
n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586, n4587, n4588,
n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596, n4597, n4598,
n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606, n4607, n4608,
n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616, n4617, n4618,
n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626, n4627, n4628,
n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636, n4637, n4638,
n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646, n4647, n4648,
n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656, n4657, n4658,
n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666, n4667, n4668,
n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676, n4677, n4678,
n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686, n4687, n4688,
n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696, n4697, n4698,
n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706, n4707, n4708,
n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716, n4717, n4718,
n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726, n4727, n4728,
n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736, n4737, n4738,
n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746, n4747, n4748,
n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757, n4758,
n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767, n4768,
n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776, n4777, n4778,
n4779, n4780, n4781, n4782, n4783, n4784, n4785, n4786, n4787, n4788,
n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796, n4797, n4798,
n4799, n4800, n4801, n4802, n4803, n4804, n4805, n4806, n4807, n4808,
n4809, n4810, n4811, n4812, n4813, n4814, n4815, n4816, n4817, n4818,
n4819, n4820, n4821, n4822, n4823, n4824, n4825, n4826, n4827, n4828,
n4829, n4830, n4831, n4832, n4833, n4834, n4835, n4836, n4837, n4838,
n4839, n4840, n4841, n4842, n4843, n4844, n4845, n4846, n4847, n4848,
n4849, n4850, n4851, n4852, n4853, n4854, n4855, n4856, n4857, n4858,
n4859, n4860, n4861, n4862, n4863, n4864, n4865, n4866, n4867, n4868,
n4869, n4870, n4871, n4872, n4873, n4874, n4875, n4876, n4877, n4878,
n4879, n4880, n4881, n4882, n4883, n4884, n4885, n4886, n4887, n4888,
n4889, n4890, n4891, n4892, n4893, n4894, n4895, n4896, n4897, n4898,
n4899, n4900, n4901, n4902, n4903, n4904, n4905, n4906, n4907, n4908,
n4909, n4910, n4911, n4912, n4913, n4914, n4915, n4916, n4917, n4918,
n4919, n4920, n4921, n4922, n4923, n4924, n4925, n4926, n4927, n4928,
n4929, n4930, n4931, n4932, n4933, n4934, n4935, n4936, n4937, n4938,
n4939, n4940, n4941, n4942, n4943, n4944, n4945, n4946, n4947, n4948,
n4949, n4950, n4951, n4952, n4953, n4954, n4955, n4956, n4957, n4958,
n4959, n4960, n4961, n4962, n4963, n4964, n4965, n4966, n4967, n4968,
n4969, n4970, n4971, n4972, n4973, n4974, n4975, n4976, n4977, n4978,
n4979, n4980, n4981, n4982, n4983, n4984, n4985, n4986, n4987, n4988,
n4989, n4990, n4991, n4992, n4993, n4994, n4995, n4996, n4997, n4998,
n4999, n5000, n5001, n5002, n5003, n5004, n5005, n5006, n5007, n5008,
n5009, n5010, n5011, n5012, n5013, n5014, n5015, n5016, n5017, n5018,
n5019, n5020, n5021, n5022, n5023, n5024, n5025, n5026, n5027, n5028,
n5029, n5030, n5031, n5032, n5033, n5034, n5035, n5036, n5037, n5038,
n5039, n5040, n5041, n5042, n5043, n5044, n5045, n5046, n5047, n5048,
n5049, n5050, n5051, n5052, n5053, n5054, n5055, n5056, n5057, n5058,
n5059, n5060, n5061, n5062, n5063, n5064, n5065, n5066, n5067, n5068,
n5069, n5070, n5071, n5072, n5073, n5074, n5075, n5076, n5077, n5078,
n5079, n5080, n5081, n5082, n5083, n5084, n5085, n5086, n5087, n5088,
n5089, n5090, n5091, n5092, n5093, n5094, n5095, n5096, n5097, n5098,
n5099, n5100, n5101, n5102, n5103, n5104, n5105, n5106, n5107, n5108,
n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116, n5117, n5118,
n5119, n5120, n5121, n5122, n5123, n5124, n5125, n5126, n5127, n5128,
n5129, n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5137, n5138,
n5139, n5140, n5141, n5142, n5143, n5144, n5145, n5146, n5147, n5148,
n5149, n5150, n5151, n5152, n5153, n5154, n5155, n5156, n5157, n5158,
n5159, n5160, n5161, n5162, n5163, n5164, n5165, n5166, n5167, n5168,
n5169, n5170, n5171, n5172, n5173, n5174, n5175, n5176, n5177, n5178,
n5179, n5180, n5181, n5182, n5183, n5184, n5185, n5186, n5187, n5188,
n5189, n5190, n5191, n5192, n5193, n5194, n5195, n5196, n5197, n5198,
n5199, n5200, n5201, n5202, n5203, n5204, n5205, n5206, n5207, n5208,
n5209, n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217, n5218,
n5219, n5220, n5221, n5222, n5223, n5224, n5225, n5226, n5227, n5228,
n5229, n5230, n5231, n5232, n5233, n5234, n5235, n5236, n5237, n5238,
n5239, n5240, n5241, n5242, n5243, n5244, n5245, n5246, n5247, n5248,
n5249, n5250, n5251, n5252, n5253, n5254, n5255, n5256, n5257, n5258,
n5259, n5260, n5261, n5262, n5263, n5264, n5265, n5266, n5267, n5268,
n5269, n5270, n5271, n5272, n5273, n5274, n5275, n5276, n5277, n5278,
n5279, n5280, n5281, n5282, n5283, n5284, n5285, n5286, n5287, n5288,
n5289, n5290, n5291, n5292, n5293, n5294, n5295, n5296, n5297, n5298,
n5299, n5300, n5301, n5302, n5303, n5304, n5305, n5306, n5307, n5308,
n5309, n5310, n5311, n5312, n5313, n5314, n5315, n5316, n5317, n5318,
n5319, n5320, n5321, n5322, n5323, n5324, n5325, n5326, n5327, n5328,
n5329, n5330, n5332, n5335, n5337, n5338, n5339, n5340, n5341, n5342,
n5343, n5344, n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352,
n5353, n5354, n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362,
n5363, n5364, n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372,
n5373, n5374, n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382,
n5383, n5384, n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392,
n5393, n5394, n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402,
n5403, n5404, n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412,
n5413, n5414, n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422,
n5423, n5424, n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432,
n5433, n5434, n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442,
n5443, n5444, n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452,
n5453, n5454, n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462,
n5463, n5464, n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472,
n5473, n5474, n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482,
n5483, n5484, n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492,
n5493, n5494, n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502,
n5503, n5504, n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512,
n5513, n5514, n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522,
n5523, n5524, n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532,
n5533, n5534, n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542,
n5543, n5544, n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552,
n5553, n5554, n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562,
n5563, n5564, n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572,
n5573, n5574, n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582,
n5583, n5584, n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592,
n5593, n5594, n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602,
n5603, n5604, n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612,
n5613, n5614, n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622,
n5623, n5624, n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632,
n5633, n5634, n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642,
n5643, n5644, n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652,
n5653, n5654, n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662,
n5663, n5664, n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672,
n5673, n5674, n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682,
n5683, n5684, n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692,
n5693, n5694, n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702,
n5703, n5704, n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712,
n5713, n5714, n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722,
n5723, n5724, n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732,
n5733, n5734, n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742,
n5743, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755,
n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765,
n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775,
n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785,
n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795,
n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805,
n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815,
n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825,
n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835,
n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845,
n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855,
n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865,
n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875,
n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885,
n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895,
n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905,
n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915,
n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925,
n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935,
n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945,
n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955,
n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965,
n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975,
n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985,
n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995,
n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005,
n6006, n6007, n6008, n6009, n6010, n6011, n6013, n6014, n6015, n6016,
n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025, n6026,
n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035, n6036,
n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045, n6046,
n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055, n6056,
n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065, n6066,
n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075, n6076,
n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085, n6086,
n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095, n6096,
n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, n6106,
n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, n6116,
n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, n6126,
n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, n6136,
n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, n6146,
n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, n6156,
n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, n6166,
n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, n6176,
n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, n6186,
n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, n6196,
n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, n6206,
n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, n6216,
n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, n6226,
n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, n6236,
n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, n6246,
n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, n6256,
n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, n6266,
n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, n6276,
n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, n6286,
n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6295, n6296, n6297,
n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, n6306, n6307,
n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315, n6316, n6317,
n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325, n6326, n6327,
n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335, n6336, n6337,
n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345, n6346, n6347,
n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355, n6356, n6357,
n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365, n6366, n6367,
n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375, n6376, n6377,
n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385, n6386, n6387,
n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395, n6396, n6397,
n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405, n6406, n6407,
n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415, n6416, n6417,
n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425, n6426, n6427,
n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435, n6436, n6437,
n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445, n6446, n6447,
n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455, n6456, n6457,
n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465;
wire [3:0] Shift_reg_FLAGS_7;
wire [63:0] intDX_EWSW;
wire [63:0] intDY_EWSW;
wire [62:0] DMP_EXP_EWSW;
wire [57:0] DmP_EXP_EWSW;
wire [62:0] DMP_SHT1_EWSW;
wire [51:0] DmP_mant_SHT1_SW;
wire [5:0] Shift_amount_SHT1_EWR;
wire [53:0] Raw_mant_NRM_SWR;
wire [62:0] DMP_SHT2_EWSW;
wire [4:2] shift_value_SHT2_EWR;
wire [10:0] DMP_exp_NRM2_EW;
wire [10:0] DMP_exp_NRM_EW;
wire [5:0] LZD_output_NRM2_EW;
wire [62:0] DMP_SFG;
wire [54:0] DmP_mant_SFG_SWR;
wire [2:0] inst_FSM_INPUT_ENABLE_state_reg;
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n6254), .Q(
inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n5489) );
DFFRX2TS inst_ShiftRegister_Q_reg_3_ ( .D(n1798), .CK(clk), .RN(n6254), .Q(
Shift_reg_FLAGS_7[3]), .QN(n5447) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1782), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[12]), .QN(n3289) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1781), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[13]), .QN(n3340) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1779), .CK(clk), .RN(n6274),
.Q(intDX_EWSW[15]), .QN(n3290) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1778), .CK(clk), .RN(n6288),
.Q(intDX_EWSW[16]), .QN(n3310) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1777), .CK(clk), .RN(n4462),
.Q(intDX_EWSW[17]), .QN(n3341) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1776), .CK(clk), .RN(n5651),
.Q(intDX_EWSW[18]), .QN(n3356) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1775), .CK(clk), .RN(n6244),
.Q(intDX_EWSW[19]), .QN(n3291) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1774), .CK(clk), .RN(n5648),
.Q(intDX_EWSW[20]), .QN(n3303) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1773), .CK(clk), .RN(n4461),
.Q(intDX_EWSW[21]), .QN(n3311) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1772), .CK(clk), .RN(n4461),
.Q(intDX_EWSW[22]), .QN(n3333) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1771), .CK(clk), .RN(n6267),
.Q(intDX_EWSW[23]), .QN(n3342) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1770), .CK(clk), .RN(n5670),
.Q(intDX_EWSW[24]), .QN(n3348) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1769), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[25]), .QN(n3357) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1768), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[26]), .QN(n3361) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1767), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[27]), .QN(n3292) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1766), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[28]), .QN(n3300) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1765), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[29]), .QN(n3304) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1764), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[30]), .QN(n3307) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1763), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[31]), .QN(n3312) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_32_ ( .D(n1762), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[32]), .QN(n3316) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_33_ ( .D(n1761), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[33]), .QN(n3334) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_34_ ( .D(n1760), .CK(clk), .RN(n6282),
.Q(intDX_EWSW[34]), .QN(n3337) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_35_ ( .D(n1759), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[35]), .QN(n3343) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_36_ ( .D(n1758), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[36]), .QN(n3346) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_37_ ( .D(n1757), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[37]), .QN(n3349) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_38_ ( .D(n1756), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[38]), .QN(n3351) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_39_ ( .D(n1755), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[39]), .QN(n3358) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_40_ ( .D(n1754), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[40]), .QN(n3360) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_41_ ( .D(n1753), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[41]), .QN(n3362) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_42_ ( .D(n1752), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[42]), .QN(n3363) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_43_ ( .D(n1751), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[43]), .QN(n3293) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_44_ ( .D(n1750), .CK(clk), .RN(n6283),
.Q(intDX_EWSW[44]), .QN(n3294) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_45_ ( .D(n1749), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[45]), .QN(n3301) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_46_ ( .D(n1748), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[46]), .QN(n3302) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_47_ ( .D(n1747), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[47]), .QN(n3305) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_48_ ( .D(n1746), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[48]), .QN(n3306) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_49_ ( .D(n1745), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[49]), .QN(n3308) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_50_ ( .D(n1744), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[50]), .QN(n3309) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_51_ ( .D(n1743), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[51]), .QN(n3313) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_52_ ( .D(n1742), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[52]), .QN(n3314) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_53_ ( .D(n1741), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[53]), .QN(n3318) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_54_ ( .D(n1740), .CK(clk), .RN(n6284),
.Q(intDX_EWSW[54]), .QN(n3332) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_55_ ( .D(n1739), .CK(clk), .RN(n6285),
.Q(intDX_EWSW[55]), .QN(n3335) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_56_ ( .D(n1738), .CK(clk), .RN(n6285),
.Q(intDX_EWSW[56]), .QN(n3336) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_57_ ( .D(n1737), .CK(clk), .RN(n6285),
.Q(intDX_EWSW[57]), .QN(n3338) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_58_ ( .D(n1736), .CK(clk), .RN(n6285),
.Q(intDX_EWSW[58]), .QN(n3339) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_59_ ( .D(n1735), .CK(clk), .RN(n6285),
.Q(intDX_EWSW[59]), .QN(n3344) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_60_ ( .D(n1734), .CK(clk), .RN(n6285),
.Q(intDX_EWSW[60]), .QN(n3345) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_61_ ( .D(n1733), .CK(clk), .RN(n6285),
.Q(intDX_EWSW[61]), .QN(n3347) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_62_ ( .D(n1732), .CK(clk), .RN(n6285),
.Q(intDX_EWSW[62]), .QN(n3377) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[27]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[28]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[29]), .QN(n2254) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[30]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[31]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_32_ ( .D(n1696), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[32]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_33_ ( .D(n1695), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[33]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_34_ ( .D(n1694), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[34]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_35_ ( .D(n1693), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[35]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_36_ ( .D(n1692), .CK(clk), .RN(n6277),
.Q(intDY_EWSW[36]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_37_ ( .D(n1691), .CK(clk), .RN(n6278),
.Q(intDY_EWSW[37]), .QN(n2320) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_38_ ( .D(n1690), .CK(clk), .RN(n6278),
.Q(intDY_EWSW[38]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_39_ ( .D(n1689), .CK(clk), .RN(n6278),
.Q(intDY_EWSW[39]), .QN(n2302) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_40_ ( .D(n1688), .CK(clk), .RN(n6278),
.Q(intDY_EWSW[40]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_41_ ( .D(n1687), .CK(clk), .RN(n6278),
.Q(intDY_EWSW[41]), .QN(n2485) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_42_ ( .D(n1686), .CK(clk), .RN(n6278),
.Q(intDY_EWSW[42]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_43_ ( .D(n1685), .CK(clk), .RN(n6278),
.Q(intDY_EWSW[43]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_44_ ( .D(n1684), .CK(clk), .RN(n6278),
.Q(intDY_EWSW[44]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_46_ ( .D(n1682), .CK(clk), .RN(n6278),
.Q(intDY_EWSW[46]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_62_ ( .D(n1666), .CK(clk), .RN(n6285),
.Q(intDY_EWSW[62]) );
DFFRX2TS SHT2_SHIFT_DATA_Q_reg_53_ ( .D(n1663), .CK(clk), .RN(n6260), .Q(
Data_array_SWR_3__53_) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1603), .CK(clk), .RN(n6270),
.Q(Shift_amount_SHT1_EWR[1]), .QN(n3366) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1601), .CK(clk), .RN(n6263),
.Q(Shift_amount_SHT1_EWR[3]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1600), .CK(clk), .RN(n6269),
.Q(Shift_amount_SHT1_EWR[4]) );
DFFRXLTS SHT1_STAGE_sft_amount_Q_reg_5_ ( .D(n1599), .CK(clk), .RN(n6269),
.Q(Shift_amount_SHT1_EWR[5]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_0_ ( .D(n1587), .CK(clk), .RN(n6260), .Q(
DMP_EXP_EWSW[0]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_3_ ( .D(n1584), .CK(clk), .RN(n5659), .Q(
DMP_EXP_EWSW[3]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_8_ ( .D(n1579), .CK(clk), .RN(n6266), .Q(
DMP_EXP_EWSW[8]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_9_ ( .D(n1578), .CK(clk), .RN(n5675), .Q(
DMP_EXP_EWSW[9]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_15_ ( .D(n1572), .CK(clk), .RN(n6241), .Q(
DMP_EXP_EWSW[15]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_18_ ( .D(n1569), .CK(clk), .RN(n6242), .Q(
DMP_EXP_EWSW[18]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_20_ ( .D(n1567), .CK(clk), .RN(n6243), .Q(
DMP_EXP_EWSW[20]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_23_ ( .D(n1564), .CK(clk), .RN(n6244), .Q(
DMP_EXP_EWSW[23]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_24_ ( .D(n1563), .CK(clk), .RN(n6245), .Q(
DMP_EXP_EWSW[24]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_25_ ( .D(n1562), .CK(clk), .RN(n6245), .Q(
DMP_EXP_EWSW[25]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_27_ ( .D(n1560), .CK(clk), .RN(n6246), .Q(
DMP_EXP_EWSW[27]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_28_ ( .D(n1559), .CK(clk), .RN(n6246), .Q(
DMP_EXP_EWSW[28]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_29_ ( .D(n1558), .CK(clk), .RN(n6247), .Q(
DMP_EXP_EWSW[29]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_31_ ( .D(n1556), .CK(clk), .RN(n6248), .Q(
DMP_EXP_EWSW[31]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_33_ ( .D(n1554), .CK(clk), .RN(n6248), .Q(
DMP_EXP_EWSW[33]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_39_ ( .D(n1548), .CK(clk), .RN(n6291), .Q(
DMP_EXP_EWSW[39]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_42_ ( .D(n1545), .CK(clk), .RN(n6250), .Q(
DMP_EXP_EWSW[42]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_45_ ( .D(n1542), .CK(clk), .RN(n6251), .Q(
DMP_EXP_EWSW[45]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_46_ ( .D(n1541), .CK(clk), .RN(n6252), .Q(
DMP_EXP_EWSW[46]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_47_ ( .D(n1540), .CK(clk), .RN(n6252), .Q(
DMP_EXP_EWSW[47]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_48_ ( .D(n1539), .CK(clk), .RN(n6252), .Q(
DMP_EXP_EWSW[48]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_49_ ( .D(n1538), .CK(clk), .RN(n2544), .Q(
DMP_EXP_EWSW[49]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_51_ ( .D(n1536), .CK(clk), .RN(n5623), .Q(
DMP_EXP_EWSW[51]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_55_ ( .D(n1532), .CK(clk), .RN(n6273), .Q(
DMP_EXP_EWSW[55]), .QN(n5555) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_56_ ( .D(n1531), .CK(clk), .RN(n6273), .Q(
DMP_EXP_EWSW[56]), .QN(n5554) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_58_ ( .D(n1529), .CK(clk), .RN(n6274), .Q(
DMP_EXP_EWSW[58]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_59_ ( .D(n1528), .CK(clk), .RN(n6275), .Q(
DMP_EXP_EWSW[59]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_61_ ( .D(n1526), .CK(clk), .RN(n6240), .Q(
DMP_EXP_EWSW[61]) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_62_ ( .D(n1525), .CK(clk), .RN(n6240), .Q(
DMP_EXP_EWSW[62]) );
DFFRX1TS EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1524), .CK(clk), .RN(n2515), .Q(
OP_FLAG_EXP) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1521), .CK(clk), .RN(n6260), .Q(
DMP_SHT1_EWSW[0]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1520), .CK(clk), .RN(n6260), .Q(
DMP_SHT2_EWSW[0]), .QN(n5361) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1518), .CK(clk), .RN(n5658), .Q(
DMP_SHT1_EWSW[1]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1517), .CK(clk), .RN(n5670), .Q(
DMP_SHT2_EWSW[1]), .QN(n5452) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_1_ ( .D(n1516), .CK(clk), .RN(n4462), .Q(
DMP_SFG[1]), .QN(n5350) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1515), .CK(clk), .RN(n2542), .Q(
DMP_SHT1_EWSW[2]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1514), .CK(clk), .RN(n2541), .Q(
DMP_SHT2_EWSW[2]), .QN(n5453) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_2_ ( .D(n1513), .CK(clk), .RN(n6264), .Q(
DMP_SFG[2]), .QN(n5351) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1512), .CK(clk), .RN(n5659), .Q(
DMP_SHT1_EWSW[3]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1511), .CK(clk), .RN(n5652), .Q(
DMP_SHT2_EWSW[3]), .QN(n5362) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1509), .CK(clk), .RN(n6266), .Q(
DMP_SHT1_EWSW[4]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1508), .CK(clk), .RN(n6266), .Q(
DMP_SHT2_EWSW[4]), .QN(n5449) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_4_ ( .D(n1507), .CK(clk), .RN(n6265), .Q(
DMP_SFG[4]), .QN(n5347) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1506), .CK(clk), .RN(n6253), .Q(
DMP_SHT1_EWSW[5]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1505), .CK(clk), .RN(n5675), .Q(
DMP_SHT2_EWSW[5]), .QN(n5456) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_5_ ( .D(n1504), .CK(clk), .RN(n5675), .Q(
DMP_SFG[5]), .QN(n5353) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1503), .CK(clk), .RN(n6263), .Q(
DMP_SHT1_EWSW[6]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1502), .CK(clk), .RN(n6263), .Q(
DMP_SHT2_EWSW[6]), .QN(n5455) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_6_ ( .D(n1501), .CK(clk), .RN(n6263), .Q(
DMP_SFG[6]), .QN(n5352) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1500), .CK(clk), .RN(n6265), .Q(
DMP_SHT1_EWSW[7]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1499), .CK(clk), .RN(n6265), .Q(
DMP_SHT2_EWSW[7]), .QN(n5450) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_7_ ( .D(n1498), .CK(clk), .RN(n6265), .Q(
DMP_SFG[7]), .QN(n5348) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1497), .CK(clk), .RN(n6266), .Q(
DMP_SHT1_EWSW[8]) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_8_ ( .D(n1495), .CK(clk), .RN(n6266), .Q(
DMP_SFG[8]), .QN(n5346) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1494), .CK(clk), .RN(n5675), .Q(
DMP_SHT1_EWSW[9]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1493), .CK(clk), .RN(n6261), .Q(
DMP_SHT2_EWSW[9]), .QN(n5457) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_9_ ( .D(n1492), .CK(clk), .RN(n6261), .Q(
DMP_SFG[9]), .QN(n5354) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1490), .CK(clk), .RN(n6261), .Q(
DMP_SHT2_EWSW[10]), .QN(n5458) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_10_ ( .D(n1489), .CK(clk), .RN(n6261), .Q(
DMP_SFG[10]), .QN(n5355) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1488), .CK(clk), .RN(n6265), .Q(
DMP_SHT1_EWSW[11]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1487), .CK(clk), .RN(n6265), .Q(
DMP_SHT2_EWSW[11]), .QN(n5451) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_11_ ( .D(n1486), .CK(clk), .RN(n6265), .Q(
DMP_SFG[11]), .QN(n5349) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1485), .CK(clk), .RN(n6264), .Q(
DMP_SHT1_EWSW[12]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1484), .CK(clk), .RN(n6264), .Q(
DMP_SHT2_EWSW[12]), .QN(n5454) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1482), .CK(clk), .RN(n6270), .Q(
DMP_SHT1_EWSW[13]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1481), .CK(clk), .RN(n6269), .Q(
DMP_SHT2_EWSW[13]), .QN(n5360) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_13_ ( .D(n1480), .CK(clk), .RN(n6269), .Q(
DMP_SFG[13]), .QN(n5467) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1479), .CK(clk), .RN(n6241), .Q(
DMP_SHT1_EWSW[14]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_14_ ( .D(n1477), .CK(clk), .RN(n6241), .Q(
DMP_SFG[14]), .QN(n5473) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1476), .CK(clk), .RN(n6241), .Q(
DMP_SHT1_EWSW[15]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1475), .CK(clk), .RN(n6241), .Q(
DMP_SHT2_EWSW[15]), .QN(n5395) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_15_ ( .D(n1474), .CK(clk), .RN(n6241), .Q(
DMP_SFG[15]), .QN(n5486) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1473), .CK(clk), .RN(n6242), .Q(
DMP_SHT1_EWSW[16]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1472), .CK(clk), .RN(n6241), .Q(
DMP_SHT2_EWSW[16]), .QN(n5394) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1470), .CK(clk), .RN(n6242), .Q(
DMP_SHT1_EWSW[17]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1469), .CK(clk), .RN(n6242), .Q(
DMP_SHT2_EWSW[17]), .QN(n5393) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_17_ ( .D(n1468), .CK(clk), .RN(n6242), .Q(
DMP_SFG[17]), .QN(n5466) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1467), .CK(clk), .RN(n6242), .Q(
DMP_SHT1_EWSW[18]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1466), .CK(clk), .RN(n6242), .Q(
DMP_SHT2_EWSW[18]), .QN(n5392) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_18_ ( .D(n1465), .CK(clk), .RN(n6242), .Q(
DMP_SFG[18]), .QN(n5477) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1464), .CK(clk), .RN(n6243), .Q(
DMP_SHT1_EWSW[19]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_19_ ( .D(n1462), .CK(clk), .RN(n6243), .Q(
DMP_SFG[19]), .QN(n5517) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1461), .CK(clk), .RN(n6243), .Q(
DMP_SHT1_EWSW[20]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1460), .CK(clk), .RN(n6243), .Q(
DMP_SHT2_EWSW[20]), .QN(n5390) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_20_ ( .D(n1459), .CK(clk), .RN(n6243), .Q(
DMP_SFG[20]), .QN(n5461) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1458), .CK(clk), .RN(n6244), .Q(
DMP_SHT1_EWSW[21]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1457), .CK(clk), .RN(n6243), .Q(
DMP_SHT2_EWSW[21]), .QN(n5389) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_21_ ( .D(n1456), .CK(clk), .RN(n6243), .Q(
DMP_SFG[21]), .QN(n5485) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1455), .CK(clk), .RN(n6244), .Q(
DMP_SHT1_EWSW[22]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1454), .CK(clk), .RN(n6244), .Q(
DMP_SHT2_EWSW[22]), .QN(n5388) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1452), .CK(clk), .RN(n6244), .Q(
DMP_SHT1_EWSW[23]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1451), .CK(clk), .RN(n6244), .Q(
DMP_SHT2_EWSW[23]), .QN(n5387) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_23_ ( .D(n1450), .CK(clk), .RN(n6244), .Q(
DMP_SFG[23]), .QN(n5465) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1449), .CK(clk), .RN(n6245), .Q(
DMP_SHT1_EWSW[24]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_24_ ( .D(n1447), .CK(clk), .RN(n6245), .Q(
DMP_SFG[24]), .QN(n5476) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n6245), .Q(
DMP_SHT1_EWSW[25]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n6245), .Q(
DMP_SHT2_EWSW[25]), .QN(n5385) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_25_ ( .D(n1444), .CK(clk), .RN(n6245), .Q(
DMP_SFG[25]), .QN(n5464) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n6246), .Q(
DMP_SHT1_EWSW[26]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n6245), .Q(
DMP_SHT2_EWSW[26]), .QN(n5384) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1440), .CK(clk), .RN(n6246), .Q(
DMP_SHT1_EWSW[27]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n6246), .Q(
DMP_SHT2_EWSW[27]), .QN(n5383) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1437), .CK(clk), .RN(n6246), .Q(
DMP_SHT1_EWSW[28]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1436), .CK(clk), .RN(n6246), .Q(
DMP_SHT2_EWSW[28]), .QN(n5382) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_28_ ( .D(n1435), .CK(clk), .RN(n6246), .Q(
DMP_SFG[28]), .QN(n5475) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1434), .CK(clk), .RN(n6247), .Q(
DMP_SHT1_EWSW[29]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_29_ ( .D(n1432), .CK(clk), .RN(n6247), .Q(
DMP_SFG[29]), .QN(n5484) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1431), .CK(clk), .RN(n6247), .Q(
DMP_SHT1_EWSW[30]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1430), .CK(clk), .RN(n6247), .Q(
DMP_SHT2_EWSW[30]), .QN(n5380) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_30_ ( .D(n1429), .CK(clk), .RN(n6247), .Q(
DMP_SFG[30]), .QN(n5471) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_31_ ( .D(n1428), .CK(clk), .RN(n6248), .Q(
DMP_SHT1_EWSW[31]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_31_ ( .D(n1427), .CK(clk), .RN(n6247), .Q(
DMP_SHT2_EWSW[31]), .QN(n5379) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_31_ ( .D(n1426), .CK(clk), .RN(n6247), .Q(
DMP_SFG[31]), .QN(n5483) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_32_ ( .D(n1425), .CK(clk), .RN(n6248), .Q(
DMP_SHT1_EWSW[32]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_32_ ( .D(n1424), .CK(clk), .RN(n6248), .Q(
DMP_SHT2_EWSW[32]), .QN(n5378) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_32_ ( .D(n1423), .CK(clk), .RN(n6248), .Q(
DMP_SFG[32]), .QN(n5482) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_33_ ( .D(n1422), .CK(clk), .RN(n6248), .Q(
DMP_SHT1_EWSW[33]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_33_ ( .D(n1421), .CK(clk), .RN(n6248), .Q(
DMP_SHT2_EWSW[33]), .QN(n5377) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_33_ ( .D(n1420), .CK(clk), .RN(n6248), .Q(
DMP_SFG[33]), .QN(n5481) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_34_ ( .D(n1419), .CK(clk), .RN(n1881), .Q(
DMP_SHT1_EWSW[34]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_34_ ( .D(n1417), .CK(clk), .RN(n1880), .Q(
DMP_SFG[34]), .QN(n5470) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_35_ ( .D(n1416), .CK(clk), .RN(n1882), .Q(
DMP_SHT1_EWSW[35]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_35_ ( .D(n1415), .CK(clk), .RN(n1882), .Q(
DMP_SHT2_EWSW[35]), .QN(n5375) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_35_ ( .D(n1414), .CK(clk), .RN(n1880), .Q(
DMP_SFG[35]), .QN(n5515) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_36_ ( .D(n1413), .CK(clk), .RN(n2515), .Q(
DMP_SHT1_EWSW[36]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_36_ ( .D(n1411), .CK(clk), .RN(n1880), .Q(
DMP_SFG[36]), .QN(n5463) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_37_ ( .D(n1410), .CK(clk), .RN(n5681), .Q(
DMP_SHT1_EWSW[37]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_37_ ( .D(n1409), .CK(clk), .RN(n6233), .Q(
DMP_SHT2_EWSW[37]), .QN(n5373) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_37_ ( .D(n1408), .CK(clk), .RN(n5681), .Q(
DMP_SFG[37]), .QN(n5514) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_38_ ( .D(n1407), .CK(clk), .RN(n5685), .Q(
DMP_SHT1_EWSW[38]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_38_ ( .D(n1406), .CK(clk), .RN(n5683), .Q(
DMP_SHT2_EWSW[38]), .QN(n5372) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_38_ ( .D(n1405), .CK(clk), .RN(n2566), .Q(
DMP_SFG[38]), .QN(n5469) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_39_ ( .D(n1404), .CK(clk), .RN(n2542), .Q(
DMP_SHT1_EWSW[39]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_40_ ( .D(n1401), .CK(clk), .RN(n5647), .Q(
DMP_SHT1_EWSW[40]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_40_ ( .D(n1400), .CK(clk), .RN(n2541), .Q(
DMP_SHT2_EWSW[40]), .QN(n6406) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_41_ ( .D(n1398), .CK(clk), .RN(n6250), .Q(
DMP_SHT1_EWSW[41]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_41_ ( .D(n1397), .CK(clk), .RN(n2542), .Q(
DMP_SHT2_EWSW[41]), .QN(n5337) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_41_ ( .D(n1396), .CK(clk), .RN(n6255), .Q(
DMP_SFG[41]), .QN(n5398) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_42_ ( .D(n1395), .CK(clk), .RN(n6250), .Q(
DMP_SHT1_EWSW[42]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_42_ ( .D(n1393), .CK(clk), .RN(n6250), .Q(
DMP_SFG[42]), .QN(n5462) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_43_ ( .D(n1392), .CK(clk), .RN(n6250), .Q(
DMP_SHT1_EWSW[43]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_43_ ( .D(n1391), .CK(clk), .RN(n6250), .Q(
DMP_SHT2_EWSW[43]), .QN(n5370) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_43_ ( .D(n1390), .CK(clk), .RN(n6250), .Q(
DMP_SFG[43]), .QN(n5480) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_44_ ( .D(n1389), .CK(clk), .RN(n6251), .Q(
DMP_SHT1_EWSW[44]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_44_ ( .D(n1388), .CK(clk), .RN(n6251), .Q(
DMP_SHT2_EWSW[44]), .QN(n5369) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_44_ ( .D(n1387), .CK(clk), .RN(n6251), .Q(
DMP_SFG[44]), .QN(n5474) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_45_ ( .D(n1386), .CK(clk), .RN(n6251), .Q(
DMP_SHT1_EWSW[45]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_45_ ( .D(n1385), .CK(clk), .RN(n6251), .Q(
DMP_SHT2_EWSW[45]), .QN(n5368) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_45_ ( .D(n1384), .CK(clk), .RN(n6251), .Q(
DMP_SFG[45]), .QN(n5479) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_46_ ( .D(n1383), .CK(clk), .RN(n6252), .Q(
DMP_SHT1_EWSW[46]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_46_ ( .D(n1382), .CK(clk), .RN(n6251), .Q(
DMP_SHT2_EWSW[46]), .QN(n5367) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_46_ ( .D(n1381), .CK(clk), .RN(n6251), .Q(
DMP_SFG[46]), .QN(n5468) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_47_ ( .D(n1380), .CK(clk), .RN(n6252), .Q(
DMP_SHT1_EWSW[47]) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_47_ ( .D(n1378), .CK(clk), .RN(n6252), .Q(
DMP_SFG[47]), .QN(n5513) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_48_ ( .D(n1377), .CK(clk), .RN(n6252), .Q(
DMP_SHT1_EWSW[48]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_48_ ( .D(n1376), .CK(clk), .RN(n6252), .Q(
DMP_SHT2_EWSW[48]), .QN(n5365) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_48_ ( .D(n1375), .CK(clk), .RN(n6252), .Q(
DMP_SFG[48]), .QN(n5460) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_49_ ( .D(n1374), .CK(clk), .RN(n6287), .Q(
DMP_SHT1_EWSW[49]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_49_ ( .D(n1373), .CK(clk), .RN(n6258), .Q(
DMP_SHT2_EWSW[49]), .QN(n5459) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_50_ ( .D(n1371), .CK(clk), .RN(n2545), .Q(
DMP_SHT1_EWSW[50]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_51_ ( .D(n1368), .CK(clk), .RN(n5623), .Q(
DMP_SHT1_EWSW[51]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_51_ ( .D(n1367), .CK(clk), .RN(n2512), .Q(
DMP_SHT2_EWSW[51]), .QN(n5363) );
DFFRX2TS SHT2_STAGE_DMP_Q_reg_52_ ( .D(n1364), .CK(clk), .RN(n6271), .QN(
n5501) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1362), .CK(clk), .RN(n2515), .Q(
DMP_exp_NRM_EW[0]) );
DFFRX2TS SHT2_STAGE_DMP_Q_reg_53_ ( .D(n1359), .CK(clk), .RN(n6271), .QN(
n5500) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_53_ ( .D(n1358), .CK(clk), .RN(n6271), .Q(
DMP_SFG[53]), .QN(n5409) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n6271), .Q(
DMP_exp_NRM_EW[1]) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(n6272), .Q(
DMP_exp_NRM_EW[2]) );
DFFRX2TS SHT2_STAGE_DMP_Q_reg_55_ ( .D(n1349), .CK(clk), .RN(n6272), .QN(
n5498) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1347), .CK(clk), .RN(n6272), .Q(
DMP_exp_NRM_EW[3]) );
DFFRX2TS SHT2_STAGE_DMP_Q_reg_56_ ( .D(n1344), .CK(clk), .RN(n6273), .QN(
n5497) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1342), .CK(clk), .RN(n6273), .Q(
DMP_exp_NRM_EW[4]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1341), .CK(clk), .RN(n6273), .Q(
DMP_exp_NRM2_EW[4]) );
DFFRX2TS SHT1_STAGE_DMP_Q_reg_57_ ( .D(n1340), .CK(clk), .RN(n6274), .QN(
n5402) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_57_ ( .D(n1338), .CK(clk), .RN(n6273), .Q(
DMP_SFG[57]), .QN(n5408) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1337), .CK(clk), .RN(n6273), .Q(
DMP_exp_NRM_EW[5]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1336), .CK(clk), .RN(n6273), .Q(
DMP_exp_NRM2_EW[5]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_58_ ( .D(n1335), .CK(clk), .RN(n6274), .Q(
DMP_SHT1_EWSW[58]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_58_ ( .D(n1334), .CK(clk), .RN(n6274), .Q(
DMP_SHT2_EWSW[58]), .QN(n5359) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1332), .CK(clk), .RN(n6274), .Q(
DMP_exp_NRM_EW[6]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_59_ ( .D(n1330), .CK(clk), .RN(n6275), .Q(
DMP_SHT1_EWSW[59]) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_59_ ( .D(n1328), .CK(clk), .RN(n6275), .Q(
DMP_SFG[59]), .QN(n5510) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1327), .CK(clk), .RN(n6275), .Q(
DMP_exp_NRM_EW[7]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_60_ ( .D(n1325), .CK(clk), .RN(n6275), .Q(
DMP_SHT1_EWSW[60]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_60_ ( .D(n1324), .CK(clk), .RN(n6275), .Q(
DMP_SHT2_EWSW[60]), .QN(n5357) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_60_ ( .D(n1323), .CK(clk), .RN(n6275), .Q(
DMP_SFG[60]), .QN(n5509) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_8_ ( .D(n1322), .CK(clk), .RN(n6275), .Q(
DMP_exp_NRM_EW[8]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_61_ ( .D(n1320), .CK(clk), .RN(n2566), .Q(
DMP_SHT1_EWSW[61]) );
DFFRX1TS SHT2_STAGE_DMP_Q_reg_61_ ( .D(n1319), .CK(clk), .RN(n6256), .Q(
DMP_SHT2_EWSW[61]), .QN(n5356) );
DFFRX1TS SGF_STAGE_DMP_Q_reg_61_ ( .D(n1318), .CK(clk), .RN(n2543), .Q(
DMP_SFG[61]), .QN(n5508) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_9_ ( .D(n1317), .CK(clk), .RN(n2538), .Q(
DMP_exp_NRM_EW[9]) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_62_ ( .D(n1315), .CK(clk), .RN(n2511), .Q(
DMP_SHT1_EWSW[62]) );
DFFRX1TS NRM_STAGE_DMP_exp_Q_reg_10_ ( .D(n1312), .CK(clk), .RN(n2512), .Q(
DMP_exp_NRM_EW[10]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1309), .CK(clk), .RN(n2545), .Q(
DmP_mant_SHT1_SW[0]) );
DFFRX1TS SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1307), .CK(clk), .RN(n2544), .Q(
DmP_mant_SHT1_SW[1]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_2_ ( .D(n1306), .CK(clk), .RN(n2543), .Q(
DmP_EXP_EWSW[2]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_4_ ( .D(n1302), .CK(clk), .RN(n2532), .Q(
DmP_EXP_EWSW[4]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_6_ ( .D(n1298), .CK(clk), .RN(n5668), .Q(
DmP_EXP_EWSW[6]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_7_ ( .D(n1296), .CK(clk), .RN(n2532), .Q(
DmP_EXP_EWSW[7]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_10_ ( .D(n1290), .CK(clk), .RN(n2532), .Q(
DmP_EXP_EWSW[10]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_15_ ( .D(n1280), .CK(clk), .RN(n6260), .Q(
DmP_EXP_EWSW[15]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_16_ ( .D(n1278), .CK(clk), .RN(n5671), .Q(
DmP_EXP_EWSW[16]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_17_ ( .D(n1276), .CK(clk), .RN(n2540), .Q(
DmP_EXP_EWSW[17]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_21_ ( .D(n1268), .CK(clk), .RN(n6264), .Q(
DmP_EXP_EWSW[21]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_22_ ( .D(n1266), .CK(clk), .RN(n2566), .Q(
DmP_EXP_EWSW[22]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_24_ ( .D(n1262), .CK(clk), .RN(n6263), .Q(
DmP_EXP_EWSW[24]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_28_ ( .D(n1254), .CK(clk), .RN(n6232), .Q(
DmP_EXP_EWSW[28]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_30_ ( .D(n1250), .CK(clk), .RN(n2566), .Q(
DmP_EXP_EWSW[30]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_31_ ( .D(n1248), .CK(clk), .RN(n5683), .Q(
DmP_EXP_EWSW[31]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_32_ ( .D(n1246), .CK(clk), .RN(n2566), .Q(
DmP_EXP_EWSW[32]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_33_ ( .D(n1244), .CK(clk), .RN(n2567), .Q(
DmP_EXP_EWSW[33]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_35_ ( .D(n1240), .CK(clk), .RN(n5629), .Q(
DmP_EXP_EWSW[35]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_36_ ( .D(n1238), .CK(clk), .RN(n5683), .Q(
DmP_EXP_EWSW[36]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_37_ ( .D(n1236), .CK(clk), .RN(n5683), .Q(
DmP_EXP_EWSW[37]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_39_ ( .D(n1232), .CK(clk), .RN(n6261), .Q(
DmP_EXP_EWSW[39]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_41_ ( .D(n1228), .CK(clk), .RN(n5675), .Q(
DmP_EXP_EWSW[41]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_42_ ( .D(n1226), .CK(clk), .RN(n5658), .Q(
DmP_EXP_EWSW[42]) );
DFFRX1TS EXP_STAGE_DmP_Q_reg_46_ ( .D(n1218), .CK(clk), .RN(n5668), .Q(
DmP_EXP_EWSW[46]) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_0_ ( .D(n1198), .CK(clk), .RN(n5644), .Q(
ZERO_FLAG_SHT1) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_0_ ( .D(n1197), .CK(clk), .RN(n5670), .Q(
ZERO_FLAG_SHT2), .QN(n6464) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1194), .CK(clk), .RN(n6262),
.Q(ZERO_FLAG_SHT1SHT2) );
DFFRX1TS SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1191), .CK(clk), .RN(n2515), .Q(
OP_FLAG_SHT2) );
DFFRX1TS SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1189), .CK(clk), .RN(n6253), .Q(
SIGN_FLAG_SHT1) );
DFFRX1TS NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1186), .CK(clk), .RN(n6253), .Q(
SIGN_FLAG_NRM) );
DFFRX1TS SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1185), .CK(clk), .RN(n5633),
.Q(SIGN_FLAG_SHT1SHT2) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1142), .CK(clk), .RN(n5633), .Q(
Raw_mant_NRM_SWR[14]), .QN(n5570) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1140), .CK(clk), .RN(n6256), .Q(
DmP_mant_SFG_SWR[1]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1137), .CK(clk), .RN(n6258), .Q(
DmP_mant_SFG_SWR[0]) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_46_ ( .D(n1024), .CK(clk), .RN(n2511), .Q(
DmP_mant_SFG_SWR[46]), .QN(n5559) );
DFFSX1TS R_15 ( .D(n6363), .CK(clk), .SN(n5645), .Q(n6195) );
DFFSX1TS R_35 ( .D(n6325), .CK(clk), .SN(n2533), .Q(n6194) );
DFFSX1TS R_47 ( .D(n6388), .CK(clk), .SN(n5638), .Q(n6193) );
DFFSX1TS R_75 ( .D(n6336), .CK(clk), .SN(n5661), .Q(n6190) );
DFFSX1TS R_88 ( .D(n6402), .CK(clk), .SN(n5624), .Q(n6189) );
DFFSX1TS R_91 ( .D(n6375), .CK(clk), .SN(n5638), .Q(n6188) );
DFFSX1TS R_110 ( .D(n6296), .CK(clk), .SN(n2541), .Q(n6183) );
DFFSX1TS R_134 ( .D(n6359), .CK(clk), .SN(n5646), .Q(n6172) );
DFFSX1TS R_138 ( .D(n6300), .CK(clk), .SN(n2567), .Q(n6171) );
DFFSX1TS R_162 ( .D(n6398), .CK(clk), .SN(n5630), .Q(n6164) );
DFFSX1TS R_164 ( .D(n6397), .CK(clk), .SN(n5630), .Q(n6163) );
DFFSX1TS R_172 ( .D(n6365), .CK(clk), .SN(n5645), .Q(n6162) );
DFFSX1TS R_189 ( .D(n6380), .CK(clk), .SN(n5638), .Q(n6159) );
DFFSX1TS R_203 ( .D(n6367), .CK(clk), .SN(n5646), .Q(n6157) );
DFFSX1TS R_211 ( .D(n6306), .CK(clk), .SN(n5681), .Q(n6156) );
DFFSX1TS R_234 ( .D(n6395), .CK(clk), .SN(n5634), .Q(n6150) );
DFFSX1TS R_235 ( .D(n6394), .CK(clk), .SN(n5634), .Q(n6149) );
DFFSX1TS R_236 ( .D(n6393), .CK(clk), .SN(n5634), .Q(n6148) );
DFFSX1TS R_247 ( .D(n6384), .CK(clk), .SN(n5638), .Q(n6143) );
DFFSX2TS R_249 ( .D(n6382), .CK(clk), .SN(n5639), .Q(n6141) );
DFFSX1TS R_254 ( .D(n6349), .CK(clk), .SN(n5654), .Q(n6138) );
DFFSX2TS R_281 ( .D(n2506), .CK(clk), .SN(n6254), .Q(n6124) );
DFFSX2TS R_289 ( .D(n1906), .CK(clk), .SN(n5646), .Q(n6120) );
DFFSX1TS R_307 ( .D(n6329), .CK(clk), .SN(n2545), .Q(n6108) );
DFFSX1TS R_308 ( .D(n6328), .CK(clk), .SN(n2544), .Q(n6107) );
DFFSX1TS R_309 ( .D(n6327), .CK(clk), .SN(n2545), .Q(n6106) );
DFFRX2TS R_319 ( .D(n6392), .CK(clk), .RN(n5653), .Q(n6101) );
DFFRX1TS R_508 ( .D(n6339), .CK(clk), .RN(n5661), .Q(n5965) );
DFFSX2TS R_517 ( .D(n2497), .CK(clk), .SN(n5679), .Q(n5958) );
DFFSX2TS R_525 ( .D(n6203), .CK(clk), .SN(n5649), .QN(n2225) );
DFFSX2TS R_537 ( .D(n6204), .CK(clk), .SN(n5665), .Q(n5951) );
DFFRX2TS R_550 ( .D(DmP_mant_SHT1_SW[20]), .CK(clk), .RN(n5634), .Q(n5945)
);
DFFSX2TS R_555 ( .D(n6200), .CK(clk), .SN(n5656), .QN(n2231) );
DFFSX2TS R_597 ( .D(n6223), .CK(clk), .SN(n5626), .Q(n5914) );
DFFSX2TS R_584 ( .D(DmP_mant_SHT1_SW[28]), .CK(clk), .SN(n5627), .Q(n5927)
);
DFFRX1TS R_585 ( .D(n6305), .CK(clk), .RN(n5624), .Q(n5926) );
DFFSX2TS R_586 ( .D(DmP_mant_SHT1_SW[39]), .CK(clk), .SN(n5627), .Q(n5925)
);
DFFSX2TS R_588 ( .D(DmP_mant_SHT1_SW[47]), .CK(clk), .SN(n5627), .Q(n5923)
);
DFFSX2TS R_590 ( .D(DmP_mant_SHT1_SW[45]), .CK(clk), .SN(n5627), .Q(n5921)
);
DFFRX1TS R_591 ( .D(n6324), .CK(clk), .RN(n5624), .Q(n5920) );
DFFRX1TS R_593 ( .D(n6319), .CK(clk), .RN(n5624), .Q(n5918) );
DFFSX2TS R_594 ( .D(DmP_mant_SHT1_SW[41]), .CK(clk), .SN(n5627), .Q(n5917)
);
DFFSX2TS R_596 ( .D(DmP_mant_SHT1_SW[35]), .CK(clk), .SN(n5626), .Q(n5915)
);
DFFSX2TS R_599 ( .D(DmP_mant_SHT1_SW[24]), .CK(clk), .SN(n5626), .Q(n5912)
);
DFFSX2TS R_522_RW_0 ( .D(DmP_mant_SHT1_SW[22]), .CK(clk), .SN(n5626), .Q(
n5957) );
DFFRX2TS R_631 ( .D(n6211), .CK(clk), .RN(n5660), .Q(n5892) );
DFFSX2TS R_645 ( .D(n6200), .CK(clk), .SN(n5657), .Q(n5882) );
DFFSX2TS R_659 ( .D(n6223), .CK(clk), .SN(n5627), .Q(n5873) );
DFFSX2TS R_657 ( .D(n2501), .CK(clk), .SN(n5626), .Q(n5874) );
DFFRX2TS R_662 ( .D(n6413), .CK(clk), .RN(n6236), .Q(n5870) );
DFFSX2TS R_692 ( .D(n2500), .CK(clk), .SN(n5651), .Q(n5853) );
DFFRX2TS R_701 ( .D(Raw_mant_NRM_SWR[28]), .CK(clk), .RN(n5676), .Q(n5848)
);
DFFRX1TS R_708 ( .D(n2441), .CK(clk), .RN(n2532), .Q(n5843) );
DFFSX2TS R_794 ( .D(n6201), .CK(clk), .SN(n5643), .Q(n5795) );
DFFSX2TS R_835 ( .D(n2497), .CK(clk), .SN(n5681), .Q(n5771) );
DFFSX2TS R_837 ( .D(n2506), .CK(clk), .SN(n5643), .Q(n5770) );
DFFRX2TS R_842 ( .D(n6455), .CK(clk), .RN(n2540), .Q(n5768) );
DFFRX2TS R_846 ( .D(n6457), .CK(clk), .RN(n5650), .Q(n5766) );
DFFSX2TS R_858 ( .D(n2556), .CK(clk), .SN(n5680), .Q(n5757) );
DFFSX2TS R_864 ( .D(n6203), .CK(clk), .SN(n2541), .Q(n5754) );
DFFSX2TS R_883 ( .D(n2506), .CK(clk), .SN(n5651), .Q(n5743) );
DFFRX2TS R_906 ( .D(n6439), .CK(clk), .RN(n2544), .Q(n5731) );
DFFSX2TS R_931 ( .D(n2506), .CK(clk), .SN(n6288), .Q(n5712) );
DFFRX2TS R_936 ( .D(n6441), .CK(clk), .RN(n2545), .Q(n5710) );
DFFSX2TS R_939 ( .D(n2496), .CK(clk), .SN(n5635), .Q(n5709) );
DFFSX2TS R_947 ( .D(n6204), .CK(clk), .SN(n5667), .Q(n5705) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_3_ ( .D(n1510), .CK(clk), .RN(n5652), .Q(
DMP_SFG[3]), .QN(n5512) );
DFFRXLTS SGF_STAGE_DMP_Q_reg_0_ ( .D(n1519), .CK(clk), .RN(n6260), .Q(
DMP_SFG[0]), .QN(n5511) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_48_ ( .D(n1067), .CK(clk), .RN(n2520), .Q(
final_result_ieee[48]), .QN(n5506) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1107), .CK(clk), .RN(n6234), .Q(
final_result_ieee[27]), .QN(n5537) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1103), .CK(clk), .RN(n6286), .Q(
final_result_ieee[22]), .QN(n5532) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1102), .CK(clk), .RN(n6234), .Q(
final_result_ieee[28]), .QN(n5538) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1098), .CK(clk), .RN(n6255), .Q(
final_result_ieee[26]), .QN(n5536) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1095), .CK(clk), .RN(n6235), .Q(
final_result_ieee[8]), .QN(n5529) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_42_ ( .D(n1094), .CK(clk), .RN(n2521), .Q(
final_result_ieee[42]), .QN(n5541) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_43_ ( .D(n1090), .CK(clk), .RN(n2520), .Q(
final_result_ieee[43]), .QN(n5542) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1086), .CK(clk), .RN(n6235), .Q(
final_result_ieee[9]), .QN(n5530) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_41_ ( .D(n1085), .CK(clk), .RN(n2521), .Q(
final_result_ieee[41]), .QN(n5540) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1080), .CK(clk), .RN(n6235), .Q(
final_result_ieee[6]), .QN(n5527) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_44_ ( .D(n1079), .CK(clk), .RN(n2520), .Q(
final_result_ieee[44]), .QN(n5543) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1078), .CK(clk), .RN(n6235), .Q(
final_result_ieee[5]), .QN(n5526) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1076), .CK(clk), .RN(n6235), .Q(
final_result_ieee[4]), .QN(n5525) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_46_ ( .D(n1075), .CK(clk), .RN(n2520), .Q(
final_result_ieee[46]), .QN(n5544) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1066), .CK(clk), .RN(n6235), .Q(
final_result_ieee[1]), .QN(n5522) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1065), .CK(clk), .RN(n6235), .Q(
final_result_ieee[3]), .QN(n5524) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_47_ ( .D(n1060), .CK(clk), .RN(n2521), .Q(
final_result_ieee[47]), .QN(n5545) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_0_ ( .D(n1523), .CK(clk), .RN(n5636), .Q(
ZERO_FLAG_EXP), .QN(n5401) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_62_ ( .D(n1588), .CK(clk), .RN(n6256), .Q(
final_result_ieee[62]), .QN(n5503) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1059), .CK(clk), .RN(n6235), .Q(
final_result_ieee[0]), .QN(n5504) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_50_ ( .D(n1057), .CK(clk), .RN(n6289), .Q(
final_result_ieee[50]), .QN(n5505) );
DFFSX2TS R_741 ( .D(n6433), .CK(clk), .SN(n6288), .Q(n5822) );
DFFSX2TS R_745 ( .D(n6431), .CK(clk), .SN(n5622), .Q(n5820) );
DFFSX2TS R_751 ( .D(n6438), .CK(clk), .SN(n5618), .Q(n5816) );
DFFSX2TS R_755 ( .D(n6442), .CK(clk), .SN(n5618), .Q(n5814) );
DFFSX2TS R_759 ( .D(n6460), .CK(clk), .SN(n5620), .Q(n5812) );
DFFSX2TS R_769 ( .D(n6416), .CK(clk), .SN(n5622), .Q(n5807) );
DFFSX2TS R_775 ( .D(n6420), .CK(clk), .SN(n6288), .Q(n5804) );
DFFSX2TS R_789 ( .D(n6435), .CK(clk), .SN(n6232), .Q(n5798) );
DFFSX2TS R_793 ( .D(n6458), .CK(clk), .SN(n5620), .Q(n5796) );
DFFSX2TS R_803 ( .D(n6463), .CK(clk), .SN(n2521), .Q(n5791) );
DFFSX2TS R_807 ( .D(n6456), .CK(clk), .SN(n5621), .Q(n5789) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1200), .CK(clk), .RN(n2544), .Q(
underflow_flag) );
DFFRXLTS R_729 ( .D(n6449), .CK(clk), .RN(n5660), .Q(n5830) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_52_ ( .D(n1598), .CK(clk), .RN(n6289), .Q(
final_result_ieee[52]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_54_ ( .D(n1596), .CK(clk), .RN(n4465), .Q(
final_result_ieee[54]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_56_ ( .D(n1594), .CK(clk), .RN(n5628), .Q(
final_result_ieee[56]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_58_ ( .D(n1592), .CK(clk), .RN(n5632), .Q(
final_result_ieee[58]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_60_ ( .D(n1590), .CK(clk), .RN(n5632), .Q(
final_result_ieee[60]) );
DFFSX1TS R_150 ( .D(n6425), .CK(clk), .SN(n5649), .Q(n6168) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_63_ ( .D(n1184), .CK(clk), .RN(n5628), .Q(
final_result_ieee[63]) );
DFFRXLTS FRMT_STAGE_FLAGS_Q_reg_0_ ( .D(n1193), .CK(clk), .RN(n6292), .Q(
zero_flag) );
DFFSX1TS R_115 ( .D(n6428), .CK(clk), .SN(n6290), .Q(n6181) );
DFFSX1TS R_118 ( .D(n6423), .CK(clk), .SN(n4463), .Q(n6179) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_57_ ( .D(n1201), .CK(clk), .RN(n6270), .Q(
DmP_EXP_EWSW[57]), .QN(n5496) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_53_ ( .D(n1597), .CK(clk), .RN(n6273), .Q(
final_result_ieee[53]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_55_ ( .D(n1595), .CK(clk), .RN(n4465), .Q(
final_result_ieee[55]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_57_ ( .D(n1593), .CK(clk), .RN(n5628), .Q(
final_result_ieee[57]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_59_ ( .D(n1591), .CK(clk), .RN(n2515), .Q(
final_result_ieee[59]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_61_ ( .D(n1589), .CK(clk), .RN(n6236), .Q(
final_result_ieee[61]) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1301), .CK(clk), .RN(n2532), .Q(
DmP_mant_SHT1_SW[4]), .QN(n5595) );
DFFRXLTS SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1299), .CK(clk), .RN(n5668), .Q(
DmP_mant_SHT1_SW[5]) );
DFFSX2TS R_351 ( .D(n6225), .CK(clk), .SN(n5655), .Q(n6075) );
DFFSX2TS R_382 ( .D(n2556), .CK(clk), .SN(n5654), .Q(n6053) );
DFFSX1TS R_326 ( .D(n6302), .CK(clk), .SN(n5681), .Q(n6094) );
DFFSX1TS R_665 ( .D(n6389), .CK(clk), .SN(n5636), .Q(n5867) );
DFFSX1TS R_325 ( .D(n6303), .CK(clk), .SN(n5681), .Q(n6095) );
DFFSX1TS R_664 ( .D(n6390), .CK(clk), .SN(n5636), .Q(n5868) );
DFFSX1TS R_324 ( .D(n6304), .CK(clk), .SN(n5681), .Q(n6096) );
DFFSX1TS R_663 ( .D(n6391), .CK(clk), .SN(n5635), .Q(n5869) );
DFFSX2TS R_477 ( .D(n2564), .CK(clk), .SN(n2533), .Q(n5985) );
DFFSX2TS R_426 ( .D(n5600), .CK(clk), .SN(n5640), .Q(n6022) );
DFFSX2TS R_438 ( .D(n5587), .CK(clk), .SN(n5641), .Q(n6011) );
DFFSX2TS R_450 ( .D(n5586), .CK(clk), .SN(n6257), .Q(n6005) );
DFFSX2TS R_478 ( .D(n5597), .CK(clk), .SN(n2533), .Q(n5984) );
DFFSX2TS R_544 ( .D(n1915), .CK(clk), .SN(n5649), .Q(n5949) );
DFFSX2TS R_436 ( .D(n5422), .CK(clk), .SN(n5641), .Q(n6013) );
DFFRXLTS R_316 ( .D(n6409), .CK(clk), .RN(n5653), .Q(n6103) );
DFFSX1TS R_577 ( .D(n6226), .CK(clk), .SN(n5632), .Q(n5932) );
DFFSX2TS R_466 ( .D(n5575), .CK(clk), .SN(n5656), .QN(n2222) );
DFFSX2TS R_447 ( .D(n2346), .CK(clk), .SN(n6257), .QN(n2220) );
DFFSX2TS R_421 ( .D(n2564), .CK(clk), .SN(n5663), .Q(n6026) );
DFFSX2TS R_441 ( .D(n6223), .CK(clk), .SN(n5672), .QN(n2226) );
DFFSX2TS R_445 ( .D(n2499), .CK(clk), .SN(n5635), .Q(n6008) );
DFFSX2TS R_457 ( .D(n6224), .CK(clk), .SN(n5673), .Q(n5999) );
DFFSX2TS R_469 ( .D(n2564), .CK(clk), .SN(n5635), .Q(n5992) );
DFFSX2TS R_473 ( .D(n2498), .CK(clk), .SN(n5682), .Q(n5988) );
DFFSX2TS R_481 ( .D(n6223), .CK(clk), .SN(n5677), .Q(n5982) );
DFFSX2TS R_485 ( .D(n6223), .CK(clk), .SN(n5641), .Q(n5978) );
DFFSX2TS R_489 ( .D(n2564), .CK(clk), .SN(n5664), .Q(n5975) );
DFFSX2TS R_369 ( .D(n6225), .CK(clk), .SN(n2545), .Q(n6063) );
DFFSX2TS R_760 ( .D(n2287), .CK(clk), .SN(n2533), .Q(n5811) );
DFFSX2TS R_422 ( .D(n5617), .CK(clk), .SN(n5663), .Q(n6025) );
DFFSX2TS R_446 ( .D(n5611), .CK(clk), .SN(n5635), .Q(n6007) );
DFFSX2TS R_454 ( .D(n5582), .CK(clk), .SN(n5648), .Q(n6002) );
DFFSX2TS R_458 ( .D(n5601), .CK(clk), .SN(n5673), .Q(n5998) );
DFFSX2TS R_462 ( .D(n5578), .CK(clk), .SN(n5649), .Q(n5994) );
DFFSX2TS R_470 ( .D(n5594), .CK(clk), .SN(n5635), .Q(n5991) );
DFFSX2TS R_482 ( .D(n5576), .CK(clk), .SN(n5677), .Q(n5981) );
DFFSX2TS R_486 ( .D(n5414), .CK(clk), .SN(n5641), .Q(n5977) );
DFFSX2TS R_490 ( .D(n5413), .CK(clk), .SN(n5664), .Q(n5974) );
DFFSX2TS R_499 ( .D(n5584), .CK(clk), .SN(n5678), .Q(n5969) );
DFFSX2TS R_562 ( .D(n2523), .CK(clk), .SN(n5632), .Q(n5942) );
DFFSX2TS R_412 ( .D(n5570), .CK(clk), .SN(n5663), .Q(n6032) );
DFFSX2TS R_444 ( .D(n5573), .CK(clk), .SN(n5635), .Q(n6009) );
DFFSX2TS R_460 ( .D(n1857), .CK(clk), .SN(n5649), .Q(n5996) );
DFFSX2TS R_480 ( .D(n3298), .CK(clk), .SN(n5677), .QN(n2408) );
DFFSX2TS R_484 ( .D(n5491), .CK(clk), .SN(n5641), .Q(n5979) );
DFFSX2TS R_488 ( .D(n5439), .CK(clk), .SN(n5664), .QN(n2415) );
DFFSX2TS R_497 ( .D(n5427), .CK(clk), .SN(n5678), .QN(n2219) );
DFFSX2TS R_511 ( .D(n1635), .CK(clk), .SN(n5629), .Q(n5962) );
DFFSX2TS R_515 ( .D(n1626), .CK(clk), .SN(n5649), .Q(n5959) );
DFFSX2TS R_713 ( .D(n1627), .CK(clk), .SN(n5674), .Q(n5839) );
DFFSX2TS R_455 ( .D(n5342), .CK(clk), .SN(n5672), .Q(n6001) );
DFFSX2TS R_671 ( .D(n2306), .CK(clk), .SN(n5680), .Q(n5863) );
DFFSX2TS R_711 ( .D(n2306), .CK(clk), .SN(n5674), .Q(n5841) );
DFFSX2TS R_619 ( .D(n6226), .CK(clk), .SN(n5674), .Q(n5898) );
DFFSX2TS R_668 ( .D(n6225), .CK(clk), .SN(n5657), .Q(n5865) );
DFFSX2TS R_553 ( .D(n2528), .CK(clk), .SN(n5625), .Q(n5943) );
DFFSX2TS R_628 ( .D(n2498), .CK(clk), .SN(n5650), .Q(n5894) );
DFFSX2TS R_635 ( .D(n2499), .CK(clk), .SN(n5656), .Q(n5890) );
DFFSX2TS R_639 ( .D(n2498), .CK(clk), .SN(n5627), .Q(n5887) );
DFFSX2TS R_655 ( .D(n6224), .CK(clk), .SN(n5665), .Q(n5876) );
DFFSX2TS R_839 ( .D(n2523), .CK(clk), .SN(n5643), .Q(n5769) );
DFFSX2TS R_849 ( .D(n2523), .CK(clk), .SN(n5680), .Q(n5763) );
DFFSX2TS R_866 ( .D(n2523), .CK(clk), .SN(n2542), .Q(n5753) );
DFFSX2TS R_881 ( .D(n1915), .CK(clk), .SN(n5675), .QN(n1842) );
DFFSX2TS R_901 ( .D(n2523), .CK(clk), .SN(n5685), .Q(n5733) );
DFFSX2TS R_941 ( .D(n6212), .CK(clk), .SN(n6286), .Q(n5708) );
DFFSX2TS R_623 ( .D(n6200), .CK(clk), .SN(n5650), .Q(n5896) );
DFFSX2TS R_889 ( .D(n6200), .CK(clk), .SN(n4463), .Q(n5739) );
DFFSX2TS R_897 ( .D(n2496), .CK(clk), .SN(n5639), .Q(n5735) );
DFFSX2TS R_921 ( .D(n6201), .CK(clk), .SN(n5636), .Q(n5719) );
DFFSX2TS R_945 ( .D(n6201), .CK(clk), .SN(n5677), .Q(n5706) );
DFFSX2TS R_359 ( .D(n6224), .CK(clk), .SN(n5630), .Q(n6069) );
DFFSX2TS R_363 ( .D(n6223), .CK(clk), .SN(n5647), .QN(n2229) );
DFFSX2TS R_524 ( .D(n5445), .CK(clk), .SN(n5625), .QN(n2413) );
DFFSX2TS R_536 ( .D(n5440), .CK(clk), .SN(n5664), .QN(n2411) );
DFFSX2TS R_598 ( .D(n5608), .CK(clk), .SN(n5626), .Q(n5913) );
DFFSX2TS R_601 ( .D(n5590), .CK(clk), .SN(n5626), .Q(n5910) );
DFFSX2TS R_629 ( .D(n2974), .CK(clk), .SN(n5650), .Q(n5893) );
DFFSX2TS R_636 ( .D(n2971), .CK(clk), .SN(n5657), .Q(n5889) );
DFFSX2TS R_640 ( .D(n2976), .CK(clk), .SN(n5627), .Q(n5886) );
DFFSX2TS R_644 ( .D(n5598), .CK(clk), .SN(n5665), .Q(n5883) );
DFFSX2TS R_648 ( .D(n5607), .CK(clk), .SN(n5657), .Q(n5880) );
DFFSX2TS R_656 ( .D(n5603), .CK(clk), .SN(n5665), .Q(n5875) );
DFFSX2TS R_660 ( .D(n5606), .CK(clk), .SN(n5624), .Q(n5872) );
DFFSX2TS R_894 ( .D(n2301), .CK(clk), .SN(n5666), .QN(n2409) );
DFFSX2TS R_500 ( .D(n6226), .CK(clk), .SN(n5631), .Q(n5968) );
DFFSX2TS R_895 ( .D(n6204), .CK(clk), .SN(n5640), .Q(n5736) );
DFFSX2TS R_919 ( .D(n2500), .CK(clk), .SN(n6233), .Q(n5721) );
DFFSX2TS R_958 ( .D(n2506), .CK(clk), .SN(n5678), .Q(n5698) );
DFFSX2TS R_346 ( .D(n5615), .CK(clk), .SN(n5678), .Q(n6078) );
DFFSX2TS R_350 ( .D(n2969), .CK(clk), .SN(n2542), .Q(n6076) );
DFFSX2TS R_360 ( .D(n5595), .CK(clk), .SN(n5630), .Q(n6068) );
DFFSX2TS R_364 ( .D(n5593), .CK(clk), .SN(n5648), .QN(n2230) );
DFFSX2TS R_381 ( .D(n5605), .CK(clk), .SN(n5669), .Q(n6054) );
DFFSX2TS R_387 ( .D(n5589), .CK(clk), .SN(n5648), .Q(n6050) );
DFFSX2TS R_391 ( .D(n5609), .CK(clk), .SN(n5664), .QN(n2414) );
DFFSX2TS R_402 ( .D(n5613), .CK(clk), .SN(n5648), .Q(n6040) );
DFFSX2TS R_406 ( .D(n5416), .CK(clk), .SN(n5640), .Q(n6036) );
DFFSX2TS R_410 ( .D(n5592), .CK(clk), .SN(n5672), .Q(n6034) );
DFFSX2TS R_430 ( .D(n5616), .CK(clk), .SN(n5655), .Q(n6019) );
DFFSX2TS R_434 ( .D(n5591), .CK(clk), .SN(n5631), .Q(n6015) );
DFFSX2TS R_357 ( .D(n3367), .CK(clk), .SN(n5631), .Q(n6071) );
DFFSX2TS R_431 ( .D(n5432), .CK(clk), .SN(n5631), .Q(n6018) );
DFFSX2TS R_826 ( .D(n6227), .CK(clk), .SN(n5643), .Q(n5777) );
DFFSX2TS R_851 ( .D(n2556), .CK(clk), .SN(n2541), .Q(n5762) );
DFFSX2TS R_955 ( .D(n2501), .CK(clk), .SN(n5658), .Q(n5700) );
DFFRXLTS R_725 ( .D(n6399), .CK(clk), .RN(n5628), .Q(n5831) );
DFFSX1TS R_493 ( .D(n6297), .CK(clk), .SN(n2568), .Q(n5971) );
DFFSX2TS R_404 ( .D(n2015), .CK(clk), .SN(n5640), .Q(n6038) );
DFFRXLTS R_920 ( .D(DmP_mant_SHT1_SW[7]), .CK(clk), .RN(n5633), .Q(n5720) );
DFFSX2TS R_746 ( .D(n2553), .CK(clk), .SN(n5636), .Q(n5819) );
DFFSX2TS R_736 ( .D(n6412), .CK(clk), .SN(n5651), .Q(n5825) );
DFFSX2TS R_870 ( .D(n6212), .CK(clk), .SN(n5636), .Q(n5751) );
DFFSX2TS R_368 ( .D(n5585), .CK(clk), .SN(n2545), .Q(n6064) );
DFFSX2TS R_418 ( .D(n6224), .CK(clk), .SN(n5655), .Q(n6027) );
DFFSX2TS R_190 ( .D(n6212), .CK(clk), .SN(n5662), .Q(n6158) );
DFFSX2TS R_278 ( .D(n6213), .CK(clk), .SN(n5625), .Q(n6126) );
DFFSX2TS R_735 ( .D(n6353), .CK(clk), .SN(n5651), .Q(n5826) );
DFFSX2TS R_565 ( .D(n2497), .CK(clk), .SN(n5673), .Q(n5940) );
DFFSX2TS R_970 ( .D(n1628), .CK(clk), .SN(n5667), .Q(n5691) );
DFFSX2TS R_974 ( .D(n6200), .CK(clk), .SN(n5658), .Q(n5688) );
DFFSX2TS R_416 ( .D(n5423), .CK(clk), .SN(n5655), .QN(n2412) );
DFFSX2TS R_568 ( .D(n5604), .CK(clk), .SN(n5679), .Q(n5938) );
DFFSX2TS R_572 ( .D(n5577), .CK(clk), .SN(n5673), .Q(n5935) );
DFFSX2TS R_911 ( .D(n6203), .CK(clk), .SN(n6290), .Q(n5727) );
DFFSX2TS R_332 ( .D(n5599), .CK(clk), .SN(n5630), .QN(n2407) );
DFFSX2TS R_355 ( .D(n2498), .CK(clk), .SN(n5684), .Q(n6073) );
DFFSX2TS R_417 ( .D(n5602), .CK(clk), .SN(n5655), .Q(n6028) );
DFFSX2TS R_569 ( .D(n6410), .CK(clk), .SN(n5679), .Q(n5937) );
DFFSX2TS R_573 ( .D(n6411), .CK(clk), .SN(n5673), .Q(n5934) );
DFFSX2TS R_365 ( .D(n5433), .CK(clk), .SN(n2544), .Q(n6067) );
DFFSX2TS R_567 ( .D(n2499), .CK(clk), .SN(n5679), .Q(n5939) );
DFFSX2TS R_808 ( .D(Raw_mant_NRM_SWR[19]), .CK(clk), .SN(n5685), .Q(n5788)
);
DFFSX2TS R_968 ( .D(n2553), .CK(clk), .SN(n5661), .Q(n5693) );
DFFSX1TS R_492 ( .D(n6298), .CK(clk), .SN(n2568), .Q(n5972) );
DFFSX1TS R_732 ( .D(n6225), .CK(clk), .SN(n5685), .Q(n5828) );
DFFRX2TS NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1128), .CK(clk), .RN(n5628), .Q(
Raw_mant_NRM_SWR[3]), .QN(n5339) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_40_ ( .D(n1158), .CK(clk), .RN(n6269), .Q(
Raw_mant_NRM_SWR[40]), .QN(n6207) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_45_ ( .D(n1153), .CK(clk), .RN(n6268), .Q(
Raw_mant_NRM_SWR[45]), .QN(n5487) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1793), .CK(clk), .RN(n6280),
.Q(intDX_EWSW[1]), .QN(n3328) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1792), .CK(clk), .RN(n6280),
.Q(intDX_EWSW[2]), .QN(n3327) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[7]), .QN(n2478) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[11]), .QN(n2477) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1791), .CK(clk), .RN(n6280),
.Q(intDX_EWSW[3]), .QN(n3326) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n6234),
.Q(intDY_EWSW[6]), .QN(n2481) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1794), .CK(clk), .RN(n6280),
.Q(intDX_EWSW[0]), .QN(n3325) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n5634),
.Q(intDY_EWSW[19]), .QN(n2372) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1790), .CK(clk), .RN(n6280),
.Q(intDX_EWSW[4]), .QN(n3324) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n5632),
.Q(intDY_EWSW[17]), .QN(n2442) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[13]), .QN(n2486) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[15]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_48_ ( .D(n1680), .CK(clk), .RN(n6279),
.Q(intDY_EWSW[48]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_49_ ( .D(n1679), .CK(clk), .RN(n6279),
.Q(intDY_EWSW[49]), .QN(n2376) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_55_ ( .D(n1673), .CK(clk), .RN(n6279),
.Q(intDY_EWSW[55]), .QN(n2475) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_51_ ( .D(n1677), .CK(clk), .RN(n6279),
.Q(intDY_EWSW[51]) );
DFFRX4TS R_785 ( .D(n6147), .CK(clk), .RN(n2514), .Q(n6161), .QN(n2294) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_50_ ( .D(n1678), .CK(clk), .RN(n6279),
.Q(intDY_EWSW[50]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_56_ ( .D(n1672), .CK(clk), .RN(n6279),
.Q(intDY_EWSW[56]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1182), .CK(clk), .RN(n6264), .Q(
Raw_mant_NRM_SWR[16]), .QN(n5581) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_52_ ( .D(n1676), .CK(clk), .RN(n6279),
.Q(intDY_EWSW[52]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_57_ ( .D(n1671), .CK(clk), .RN(n6280),
.Q(intDY_EWSW[57]), .QN(n2371) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_47_ ( .D(n1681), .CK(clk), .RN(n6279),
.Q(intDY_EWSW[47]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[12]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n5633),
.Q(intDY_EWSW[23]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_54_ ( .D(n1674), .CK(clk), .RN(n6279),
.Q(intDY_EWSW[54]), .QN(n2332) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n5636),
.Q(intDY_EWSW[26]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n2543),
.Q(intDY_EWSW[2]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n5618),
.Q(intDY_EWSW[24]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n6240),
.Q(intDY_EWSW[3]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[16]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n5619),
.Q(intDY_EWSW[18]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n5634),
.Q(intDY_EWSW[22]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n5632),
.Q(intDY_EWSW[20]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_14_ ( .D(n1125), .CK(clk), .RN(n6258),
.Q(LZD_output_NRM2_EW[3]), .QN(n3376) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n6240),
.Q(intDY_EWSW[4]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_58_ ( .D(n1670), .CK(clk), .RN(n6280),
.Q(intDY_EWSW[58]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1139), .CK(clk), .RN(n6256), .Q(
Raw_mant_NRM_SWR[1]), .QN(n5419) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1331), .CK(clk), .RN(n6274), .Q(
DMP_exp_NRM2_EW[6]), .QN(n5435) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1131), .CK(clk), .RN(n5652), .Q(
Raw_mant_NRM_SWR[5]), .QN(n5429) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1179), .CK(clk), .RN(n6266), .Q(
Raw_mant_NRM_SWR[19]), .QN(n5341) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_59_ ( .D(n1669), .CK(clk), .RN(n6280),
.Q(intDY_EWSW[59]), .QN(n2374) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1116), .CK(clk), .RN(n5637), .Q(
Raw_mant_NRM_SWR[11]), .QN(n5490) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(n6272), .Q(
DMP_exp_NRM2_EW[3]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_60_ ( .D(n1668), .CK(clk), .RN(n6280),
.Q(intDY_EWSW[60]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n6256),
.Q(intDY_EWSW[0]) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_61_ ( .D(n1667), .CK(clk), .RN(n6280),
.Q(intDY_EWSW[61]) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1321), .CK(clk), .RN(n6275), .Q(
DMP_exp_NRM2_EW[8]) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_12_ ( .D(n1483), .CK(clk), .RN(n6263), .Q(
DMP_SFG[12]), .QN(n3350) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1783), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[11]), .QN(n3323) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1096), .CK(clk), .RN(n5623), .Q(
Raw_mant_NRM_SWR[10]), .QN(n5439) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1120), .CK(clk), .RN(n5637), .Q(
Raw_mant_NRM_SWR[7]), .QN(n5424) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n6271), .Q(
DMP_exp_NRM2_EW[1]) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1787), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[7]), .QN(n3352) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1138), .CK(clk), .RN(n6236),
.Q(LZD_output_NRM2_EW[0]), .QN(n3321) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1180), .CK(clk), .RN(n6264), .Q(
Raw_mant_NRM_SWR[18]), .QN(n5440) );
DFFRX2TS R_322 ( .D(n6369), .CK(clk), .RN(n5638), .Q(n6098) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1110), .CK(clk), .RN(n5628), .Q(
Raw_mant_NRM_SWR[13]), .QN(n5443) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1789), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[5]), .QN(n3359) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_16_ ( .D(n1141), .CK(clk), .RN(n6257),
.Q(LZD_output_NRM2_EW[5]), .QN(n3369) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1785), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[9]), .QN(n3319) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1176), .CK(clk), .RN(n5670), .Q(
Raw_mant_NRM_SWR[22]), .QN(n5441) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1780), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[14]), .QN(n3355) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1788), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[6]), .QN(n3317) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_15_ ( .D(n1135), .CK(clk), .RN(n6259),
.Q(LZD_output_NRM2_EW[4]), .QN(n3373) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_29_ ( .D(n1169), .CK(clk), .RN(n6291), .Q(
Raw_mant_NRM_SWR[29]), .QN(n5343) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1136), .CK(clk), .RN(n6259), .Q(
Raw_mant_NRM_SWR[0]), .QN(n5546) );
DFFRX2TS R_672 ( .D(Raw_mant_NRM_SWR[18]), .CK(clk), .RN(n5676), .Q(n5862)
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1173), .CK(clk), .RN(n4466), .Q(
Raw_mant_NRM_SWR[25]), .QN(n3298) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1326), .CK(clk), .RN(n6274), .Q(
DMP_exp_NRM2_EW[7]) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_13_ ( .D(n1122), .CK(clk), .RN(n6258),
.Q(LZD_output_NRM2_EW[2]), .QN(n3375) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_38_ ( .D(n1160), .CK(clk), .RN(n6269), .Q(
Raw_mant_NRM_SWR[38]), .QN(n3371) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_55_ ( .D(n1203), .CK(clk), .RN(n6270), .Q(
DmP_EXP_EWSW[55]), .QN(n3354) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1784), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[10]), .QN(n3353) );
DFFRX2TS R_948 ( .D(DmP_mant_SHT1_SW[41]), .CK(clk), .RN(n5659), .Q(n5704)
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1123), .CK(clk), .RN(n5623), .Q(
Raw_mant_NRM_SWR[6]), .QN(n5423) );
DFFRX4TS INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1786), .CK(clk), .RN(n6281),
.Q(intDX_EWSW[8]), .QN(n3315) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_36_ ( .D(n1162), .CK(clk), .RN(n6268), .Q(
Raw_mant_NRM_SWR[36]), .QN(n6209) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_35_ ( .D(n1163), .CK(clk), .RN(n6268), .Q(
Raw_mant_NRM_SWR[35]), .QN(n3364) );
DFFRX2TS inst_ShiftRegister_Q_reg_5_ ( .D(n1800), .CK(clk), .RN(n6257), .Q(
Shift_reg_FLAGS_7_5), .QN(n5596) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1112), .CK(clk), .RN(n5644), .Q(
Raw_mant_NRM_SWR[12]), .QN(n5438) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1118), .CK(clk), .RN(n5633), .Q(
Raw_mant_NRM_SWR[8]), .QN(n5491) );
DFFRX4TS R_878 ( .D(n5747), .CK(clk), .RN(n2514), .Q(n6405), .QN(n5421) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1054), .CK(clk), .RN(n6237), .Q(
DmP_mant_SFG_SWR[16]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_35_ ( .D(n1035), .CK(clk), .RN(n6238), .Q(
DmP_mant_SFG_SWR[35]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1177), .CK(clk), .RN(n6291), .Q(
Raw_mant_NRM_SWR[21]), .QN(n5427) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n1609), .CK(clk), .RN(n5628),
.Q(shift_value_SHT2_EWR[2]), .QN(n5436) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1183), .CK(clk), .RN(n6264), .Q(
Raw_mant_NRM_SWR[15]), .QN(n5426) );
DFFRX2TS R_714 ( .D(n5041), .CK(clk), .RN(n4463), .Q(n5838) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n1607), .CK(clk), .RN(n5623),
.Q(shift_value_SHT2_EWR[4]), .QN(n3372) );
DFFSX1TS R_816 ( .D(final_result_ieee[31]), .CK(clk), .SN(n5621), .Q(n5783)
);
DFFSX1TS R_804 ( .D(final_result_ieee[37]), .CK(clk), .SN(n5621), .Q(n5790)
);
DFFSX1TS R_800 ( .D(final_result_ieee[40]), .CK(clk), .SN(n2521), .Q(n5792)
);
DFFSX1TS R_790 ( .D(final_result_ieee[38]), .CK(clk), .SN(n5621), .Q(n5797)
);
DFFSX1TS R_786 ( .D(final_result_ieee[20]), .CK(clk), .SN(n6255), .Q(n5799)
);
DFFSX1TS R_780 ( .D(final_result_ieee[10]), .CK(clk), .SN(n5622), .Q(n5801)
);
DFFSX1TS R_776 ( .D(final_result_ieee[12]), .CK(clk), .SN(n5685), .Q(n5803)
);
DFFSX1TS R_772 ( .D(final_result_ieee[13]), .CK(clk), .SN(n6255), .Q(n5805)
);
DFFSX1TS R_766 ( .D(final_result_ieee[11]), .CK(clk), .SN(n5685), .Q(n5808)
);
DFFSX1TS R_756 ( .D(final_result_ieee[39]), .CK(clk), .SN(n5620), .Q(n5813)
);
DFFSX1TS R_752 ( .D(final_result_ieee[32]), .CK(clk), .SN(n5619), .Q(n5815)
);
DFFSX1TS R_748 ( .D(final_result_ieee[30]), .CK(clk), .SN(n5618), .Q(n5817)
);
DFFSX1TS R_742 ( .D(final_result_ieee[18]), .CK(clk), .SN(n5622), .Q(n5821)
);
DFFSX1TS R_738 ( .D(final_result_ieee[19]), .CK(clk), .SN(n5643), .Q(n5823)
);
DFFSX1TS R_154 ( .D(n6429), .CK(clk), .SN(n4464), .Q(n6165) );
DFFSX1TS R_102 ( .D(n6453), .CK(clk), .SN(n5619), .Q(n6184) );
DFFSX1TS R_99 ( .D(n6447), .CK(clk), .SN(n5620), .Q(n6186) );
DFFSX1TS R_12 ( .D(n6444), .CK(clk), .SN(n5619), .Q(n6196) );
DFFSX1TS R_9 ( .D(n6450), .CK(clk), .SN(n5620), .Q(n6197) );
DFFSX1TS R_151 ( .D(n6424), .CK(clk), .SN(n6290), .Q(n6167) );
DFFSX1TS R_117 ( .D(n6427), .CK(clk), .SN(n6288), .Q(n6180) );
DFFSX1TS R_120 ( .D(n6422), .CK(clk), .SN(n6290), .Q(n6178) );
DFFSRHQX4TS SHT2_STAGE_DMP_Q_reg_62_ ( .D(n1314), .CK(clk), .SN(1'b1), .RN(
n6233), .Q(DMP_SHT2_EWSW[62]) );
DFFRHQX2TS SHT2_STAGE_DMP_Q_reg_57_ ( .D(n1339), .CK(clk), .RN(n6254), .Q(
n5335) );
DFFRHQX4TS SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1192), .CK(clk), .RN(n6232), .Q(
OP_FLAG_SHT1) );
DFFRHQX4TS SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1491), .CK(clk), .RN(n2521), .Q(
DMP_SHT1_EWSW[10]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_45_ ( .D(n1219), .CK(clk), .RN(n2539),
.Q(DmP_mant_SHT1_SW[45]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1277), .CK(clk), .RN(n5671),
.Q(DmP_mant_SHT1_SW[16]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1289), .CK(clk), .RN(n2533),
.Q(DmP_mant_SHT1_SW[10]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1265), .CK(clk), .RN(n2567),
.Q(DmP_mant_SHT1_SW[22]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_50_ ( .D(n1209), .CK(clk), .RN(n6287),
.Q(DmP_mant_SHT1_SW[50]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1271), .CK(clk), .RN(n6287),
.Q(DmP_mant_SHT1_SW[19]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_38_ ( .D(n1233), .CK(clk), .RN(n5671),
.Q(DmP_mant_SHT1_SW[38]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_25_ ( .D(n1259), .CK(clk), .RN(n6263),
.Q(DmP_mant_SHT1_SW[25]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_41_ ( .D(n1227), .CK(clk), .RN(n5675),
.Q(DmP_mant_SHT1_SW[41]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1281), .CK(clk), .RN(n6236),
.Q(DmP_mant_SHT1_SW[14]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_39_ ( .D(n1231), .CK(clk), .RN(n6261),
.Q(DmP_mant_SHT1_SW[39]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1291), .CK(clk), .RN(n2533),
.Q(DmP_mant_SHT1_SW[9]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_48_ ( .D(n1213), .CK(clk), .RN(n6260),
.Q(DmP_mant_SHT1_SW[48]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_32_ ( .D(n1245), .CK(clk), .RN(n2568),
.Q(DmP_mant_SHT1_SW[32]) );
DFFRHQX8TS SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1303), .CK(clk), .RN(n5668),
.Q(DmP_mant_SHT1_SW[3]) );
DFFRHQX1TS Ready_reg_Q_reg_0_ ( .D(n6293), .CK(clk), .RN(n2539), .Q(ready)
);
DFFSX4TS R_916 ( .D(n5574), .CK(clk), .SN(n2545), .Q(n5723) );
DFFSRHQX4TS INPUT_STAGE_OPERANDX_Q_reg_63_ ( .D(n1731), .CK(clk), .SN(1'b1),
.RN(n6232), .Q(intDX_EWSW[63]) );
DFFSX1TS R_643 ( .D(n2564), .CK(clk), .SN(n5665), .Q(n5884) );
DFFSX1TS R_600 ( .D(n2564), .CK(clk), .SN(n5626), .Q(n5911) );
DFFSX1TS R_401 ( .D(n6224), .CK(clk), .SN(n5648), .Q(n6041) );
DFFSX1TS R_390 ( .D(n2564), .CK(clk), .SN(n5663), .Q(n6048) );
DFFSX1TS R_386 ( .D(n2564), .CK(clk), .SN(n5647), .Q(n6051) );
DFFSX1TS R_367 ( .D(n2499), .CK(clk), .SN(n2544), .Q(n6065) );
DFFSX1TS R_925 ( .D(n6212), .CK(clk), .SN(n5678), .Q(n5717) );
DFFSX1TS R_917 ( .D(n6212), .CK(clk), .SN(n5666), .Q(n5722) );
DFFSX1TS R_913 ( .D(n6212), .CK(clk), .SN(n5651), .Q(n5725) );
DFFSX1TS R_862 ( .D(n6212), .CK(clk), .SN(n5632), .Q(n5755) );
DFFSX1TS R_843 ( .D(n6212), .CK(clk), .SN(n5666), .Q(n5767) );
DFFSX1TS R_814 ( .D(n2557), .CK(clk), .SN(n5636), .Q(n5784) );
DFFSX1TS R_615 ( .D(n6220), .CK(clk), .SN(n5674), .Q(n5900) );
DFFSX1TS R_523 ( .D(n2528), .CK(clk), .SN(n5625), .Q(n5956) );
DFFSX1TS R_487 ( .D(n3046), .CK(clk), .SN(n5664), .Q(n5976) );
DFFSX1TS R_435 ( .D(n3046), .CK(clk), .SN(n5641), .Q(n6014) );
DFFSX1TS R_415 ( .D(n6222), .CK(clk), .SN(n5654), .Q(n6029) );
DFFSX1TS R_389 ( .D(n2528), .CK(clk), .SN(n5662), .Q(n6049) );
DFFSX1TS R_371 ( .D(n2528), .CK(clk), .SN(n5681), .Q(n6062) );
DFFSX1TS R_366 ( .D(n6220), .CK(clk), .SN(n2545), .Q(n6066) );
DFFSX1TS R_331 ( .D(n2528), .CK(clk), .SN(n5630), .Q(n6090) );
DFFSX1TS R_874 ( .D(n2496), .CK(clk), .SN(n5670), .Q(n5748) );
DFFSX1TS R_284 ( .D(n6409), .CK(clk), .SN(n2512), .Q(n6123) );
DFFSX1TS R_269 ( .D(n6374), .CK(clk), .SN(n5639), .Q(n6132) );
DFFSX1TS R_100 ( .D(n6454), .CK(clk), .SN(n5619), .Q(n6185) );
DFFSX1TS R_606 ( .D(n6316), .CK(clk), .SN(n5674), .Q(n5906) );
DFFSX1TS R_303 ( .D(n6313), .CK(clk), .SN(n5678), .Q(n6111) );
DFFSX1TS R_276 ( .D(n6434), .CK(clk), .SN(n5667), .Q(n6127) );
DFFSX1TS R_264 ( .D(n6432), .CK(clk), .SN(n5668), .Q(n6134) );
DFFSX1TS R_260 ( .D(n6415), .CK(clk), .SN(n5667), .Q(n6136) );
DFFSX1TS R_274 ( .D(n6417), .CK(clk), .SN(n5667), .Q(n6128) );
DFFSX1TS R_272 ( .D(n6421), .CK(clk), .SN(n6238), .Q(n6129) );
DFFSX1TS R_258 ( .D(n6436), .CK(clk), .SN(n6254), .Q(n6137) );
DFFSX1TS R_262 ( .D(n6419), .CK(clk), .SN(n6261), .Q(n6135) );
DFFSX1TS R_126 ( .D(n6337), .CK(clk), .SN(n5661), .Q(n6173) );
DFFSX1TS R_301 ( .D(n6356), .CK(clk), .SN(n5647), .Q(n6113) );
DFFSX1TS R_122 ( .D(n6346), .CK(clk), .SN(n5655), .Q(n6176) );
DFFSX1TS R_97 ( .D(n6448), .CK(clk), .SN(n5619), .Q(n6187) );
DFFSX1TS R_335 ( .D(n6377), .CK(clk), .SN(n5639), .Q(n6087) );
DFFSX1TS R_737 ( .D(n6352), .CK(clk), .SN(n5651), .Q(n5824) );
DFFSX1TS R_245 ( .D(n6400), .CK(clk), .SN(n5625), .Q(n6144) );
DFFSX1TS R_270 ( .D(n6373), .CK(clk), .SN(n5639), .Q(n6131) );
DFFSX1TS R_227 ( .D(n6331), .CK(clk), .SN(n6257), .Q(n6153) );
DFFSX1TS R_340 ( .D(n6322), .CK(clk), .SN(n5672), .Q(n6082) );
DFFSX1TS R_334 ( .D(n6378), .CK(clk), .SN(n5640), .Q(n6088) );
DFFSX1TS R_604 ( .D(n6386), .CK(clk), .SN(n5641), .Q(n5908) );
DFFSX1TS R_607 ( .D(n6315), .CK(clk), .SN(n5674), .Q(n5905) );
DFFSX1TS R_152 ( .D(n6430), .CK(clk), .SN(n5663), .Q(n6166) );
DFFSX1TS R_338 ( .D(n6334), .CK(clk), .SN(n5662), .Q(n6084) );
DFFSX1TS R_393 ( .D(n6309), .CK(clk), .SN(n5678), .Q(n6046) );
DFFSX1TS R_149 ( .D(n6426), .CK(clk), .SN(n5661), .Q(n6169) );
DFFSX1TS R_341 ( .D(n6321), .CK(clk), .SN(n5667), .Q(n6081) );
DFFSX1TS R_55 ( .D(n6317), .CK(clk), .SN(n4463), .Q(n6192) );
DFFSX1TS R_375 ( .D(n6343), .CK(clk), .SN(n5662), .Q(n6059) );
DFFSX1TS R_226 ( .D(n5430), .CK(clk), .SN(n6258), .Q(n6154) );
DFFSX1TS R_300 ( .D(n6357), .CK(clk), .SN(n5646), .Q(n6114) );
DFFSX1TS R_337 ( .D(n6335), .CK(clk), .SN(n5662), .Q(n6085) );
DFFSX1TS R_603 ( .D(n6387), .CK(clk), .SN(n5642), .Q(n5909) );
DFFSX1TS R_125 ( .D(n6338), .CK(clk), .SN(n5661), .Q(n6174) );
DFFSX1TS R_248 ( .D(n6383), .CK(clk), .SN(n5638), .Q(n6142) );
DFFSX1TS R_7 ( .D(n6451), .CK(clk), .SN(n5620), .Q(n6198) );
DFFSX1TS R_868 ( .D(n6226), .CK(clk), .SN(n2533), .Q(n5752) );
DFFSX1TS R_820 ( .D(n6225), .CK(clk), .SN(n5636), .Q(n5781) );
DFFSX1TS R_677 ( .D(n6227), .CK(clk), .SN(n5642), .Q(n5859) );
DFFSX1TS R_653 ( .D(n6226), .CK(clk), .SN(n5666), .Q(n5877) );
DFFSX1TS R_649 ( .D(n6226), .CK(clk), .SN(n5679), .Q(n5879) );
DFFSX1TS R_621 ( .D(n2556), .CK(clk), .SN(n5650), .Q(n5897) );
DFFSX1TS R_549 ( .D(n6225), .CK(clk), .SN(n5635), .Q(n5946) );
DFFSX1TS R_244 ( .D(n2375), .CK(clk), .SN(n5624), .Q(n6145) );
DFFSX1TS R_608 ( .D(n6314), .CK(clk), .SN(n5674), .Q(n5904) );
DFFSX1TS R_394 ( .D(n6308), .CK(clk), .SN(n5678), .Q(n6045) );
DFFSX1TS R_339 ( .D(n6333), .CK(clk), .SN(n5662), .Q(n6083) );
DFFSX1TS R_228 ( .D(n6330), .CK(clk), .SN(n6257), .Q(n6152) );
DFFSX1TS R_305 ( .D(n6311), .CK(clk), .SN(n5677), .Q(n6109) );
DFFSX1TS R_392 ( .D(n6310), .CK(clk), .SN(n5677), .Q(n6047) );
DFFSX1TS R_314 ( .D(n6326), .CK(clk), .SN(n2544), .Q(n6104) );
DFFSX1TS R_323 ( .D(n6368), .CK(clk), .SN(n5639), .Q(n6097) );
DFFSX1TS R_317 ( .D(n6350), .CK(clk), .SN(n5654), .Q(n6102) );
DFFSX1TS R_491 ( .D(n6299), .CK(clk), .SN(n2567), .Q(n5973) );
DFFSX1TS R_231 ( .D(n6318), .CK(clk), .SN(n5638), .Q(n6151) );
DFFSX1TS R_224 ( .D(n6307), .CK(clk), .SN(n5677), .Q(n6155) );
DFFSX1TS R_243 ( .D(n6401), .CK(clk), .SN(n5625), .Q(n6146) );
DFFSX1TS R_605 ( .D(n6385), .CK(clk), .SN(n5642), .Q(n5907) );
DFFSX1TS R_336 ( .D(n6376), .CK(clk), .SN(n5640), .Q(n6086) );
DFFSX1TS R_302 ( .D(n6355), .CK(clk), .SN(n5646), .Q(n6112) );
DFFSX1TS R_271 ( .D(n6372), .CK(clk), .SN(n5639), .Q(n6130) );
DFFSX1TS R_123 ( .D(n6345), .CK(clk), .SN(n5654), .Q(n6175) );
DFFSX1TS R_320 ( .D(n6348), .CK(clk), .SN(n5654), .Q(n6100) );
DFFSX1TS R_290 ( .D(n6354), .CK(clk), .SN(n5646), .Q(n6119) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_50_ ( .D(n1369), .CK(clk), .RN(n2539), .Q(
DMP_SFG[50]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_49_ ( .D(n1372), .CK(clk), .RN(n2538), .Q(
DMP_SFG[49]) );
DFFRHQX2TS SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1187), .CK(clk), .RN(n4465), .Q(
SIGN_FLAG_SFG) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_62_ ( .D(n1313), .CK(clk), .RN(n2511), .Q(
DMP_SFG[62]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_51_ ( .D(n1366), .CK(clk), .RN(n2539), .Q(
DMP_SFG[51]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_58_ ( .D(n1333), .CK(clk), .RN(n6274), .Q(
DMP_SFG[58]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_56_ ( .D(n1343), .CK(clk), .RN(n2538), .Q(
DMP_SFG[56]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_54_ ( .D(n1353), .CK(clk), .RN(n6272), .Q(
DMP_SFG[54]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_52_ ( .D(n1363), .CK(clk), .RN(n2515), .Q(
DMP_SFG[52]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_55_ ( .D(n1348), .CK(clk), .RN(n6272), .Q(
DMP_SFG[55]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1111), .CK(clk), .RN(n2539),
.Q(DmP_mant_SFG_SWR[13]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1113), .CK(clk), .RN(n5644),
.Q(DmP_mant_SFG_SWR[12]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1119), .CK(clk), .RN(n2539),
.Q(DmP_mant_SFG_SWR[8]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1134), .CK(clk), .RN(n5652),
.Q(DmP_mant_SFG_SWR[2]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1129), .CK(clk), .RN(n2538),
.Q(DmP_mant_SFG_SWR[3]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1105), .CK(clk), .RN(n2539),
.Q(DmP_mant_SFG_SWR[9]) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_53_ ( .D(n1534), .CK(clk), .RN(n6271), .Q(
DMP_EXP_EWSW[53]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1097), .CK(clk), .RN(n5623),
.Q(DmP_mant_SFG_SWR[10]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1124), .CK(clk), .RN(n5623),
.Q(DmP_mant_SFG_SWR[6]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1132), .CK(clk), .RN(n5652),
.Q(DmP_mant_SFG_SWR[5]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1117), .CK(clk), .RN(n5637),
.Q(DmP_mant_SFG_SWR[11]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1127), .CK(clk), .RN(n2538),
.Q(DmP_mant_SFG_SWR[4]) );
DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_51_ ( .D(n1147), .CK(clk), .RN(n6267),
.Q(Raw_mant_NRM_SWR[51]) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1121), .CK(clk), .RN(n5637),
.Q(DmP_mant_SFG_SWR[7]) );
DFFRXLTS R_765 ( .D(n6459), .CK(clk), .RN(n5618), .Q(n5809) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_43_ ( .D(n1224), .CK(clk), .RN(n2538), .Q(
DmP_EXP_EWSW[43]) );
DFFRHQX1TS R_877 ( .D(n1143), .CK(clk), .RN(n2538), .Q(n5332) );
DFFSRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_63_ ( .D(n1665), .CK(clk), .SN(1'b1),
.RN(n6286), .Q(intDY_EWSW[63]) );
DFFSHQX8TS NRM_STAGE_Raw_mant_Q_reg_44_ ( .D(n5330), .CK(clk), .SN(n6465),
.Q(n5428) );
DFFRX1TS SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1604), .CK(clk), .RN(n6270),
.Q(Shift_amount_SHT1_EWR[0]), .QN(n5434) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1496), .CK(clk), .RN(n6266), .Q(
DMP_SHT2_EWSW[8]), .QN(n5448) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1448), .CK(clk), .RN(n6245), .Q(
DMP_SHT2_EWSW[24]), .QN(n5386) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1433), .CK(clk), .RN(n6247), .Q(
DMP_SHT2_EWSW[29]), .QN(n5381) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_34_ ( .D(n1418), .CK(clk), .RN(n1882), .Q(
DMP_SHT2_EWSW[34]), .QN(n5376) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_39_ ( .D(n1403), .CK(clk), .RN(n6258), .Q(
DMP_SHT2_EWSW[39]), .QN(n5338) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_50_ ( .D(n1370), .CK(clk), .RN(n6233), .Q(
DMP_SHT2_EWSW[50]), .QN(n5364) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_50_ ( .D(n1020), .CK(clk), .RN(n2512), .Q(
DmP_mant_SFG_SWR[50]), .QN(n5558) );
DFFRXLTS R_709 ( .D(n6208), .CK(clk), .RN(n2532), .Q(n5842) );
DFFRXLTS R_957 ( .D(n6351), .CK(clk), .RN(n5652), .Q(n5699) );
DFFSX1TS R_783 ( .D(n6414), .CK(clk), .SN(n5622), .Q(n5800) );
DFFSX1TS R_819 ( .D(n6440), .CK(clk), .SN(n5621), .Q(n5782) );
DFFRX1TS EXP_STAGE_DMP_Q_reg_52_ ( .D(n1535), .CK(clk), .RN(n6271), .Q(
DMP_EXP_EWSW[52]), .QN(n5557) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1279), .CK(clk), .RN(n5671),
.Q(DmP_mant_SHT1_SW[15]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1287), .CK(clk), .RN(n6258),
.Q(DmP_mant_SHT1_SW[11]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_29_ ( .D(n1041), .CK(clk), .RN(n6238), .Q(
n2293), .QN(n5518) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_31_ ( .D(n1039), .CK(clk), .RN(n6238), .Q(
DmP_mant_SFG_SWR[31]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_30_ ( .D(n1040), .CK(clk), .RN(n6238), .Q(
DmP_mant_SFG_SWR[30]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_33_ ( .D(n1165), .CK(clk), .RN(n6268), .Q(
Raw_mant_NRM_SWR[33]), .QN(n5569) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_33_ ( .D(n1037), .CK(clk), .RN(n6238), .Q(
DmP_mant_SFG_SWR[33]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_37_ ( .D(n1033), .CK(clk), .RN(n6239), .Q(
DmP_mant_SFG_SWR[37]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_44_ ( .D(n1221), .CK(clk), .RN(n6465),
.Q(DmP_mant_SHT1_SW[44]), .QN(n5416) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_26_ ( .D(n1172), .CK(clk), .RN(n5625), .Q(
Raw_mant_NRM_SWR[26]), .QN(n5431) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_48_ ( .D(n1150), .CK(clk), .RN(n6267), .Q(
Raw_mant_NRM_SWR[48]), .QN(n5420) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_37_ ( .D(n1161), .CK(clk), .RN(n6269), .Q(
Raw_mant_NRM_SWR[37]), .QN(n5345) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1052), .CK(clk), .RN(n6237), .Q(
DmP_mant_SFG_SWR[18]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_43_ ( .D(n1155), .CK(clk), .RN(n6268), .Q(
Raw_mant_NRM_SWR[43]), .QN(n5433) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[10]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_36_ ( .D(n1034), .CK(clk), .RN(n6239), .Q(
DmP_mant_SFG_SWR[36]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_42_ ( .D(n1156), .CK(clk), .RN(n6268), .Q(
Raw_mant_NRM_SWR[42]), .QN(n2416) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_50_ ( .D(n1148), .CK(clk), .RN(n6267), .Q(
Raw_mant_NRM_SWR[50]), .QN(n5580) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_32_ ( .D(n1166), .CK(clk), .RN(n4466), .Q(
Raw_mant_NRM_SWR[32]), .QN(n5573) );
DFFRX4TS inst_ShiftRegister_Q_reg_6_ ( .D(n1801), .CK(clk), .RN(n6291), .Q(
Shift_reg_FLAGS_7_6), .QN(n5495) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_47_ ( .D(n1151), .CK(clk), .RN(n6267), .Q(
Raw_mant_NRM_SWR[47]), .QN(n5579) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[14]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_46_ ( .D(n1152), .CK(clk), .RN(n6268), .Q(
Raw_mant_NRM_SWR[46]), .QN(n5425) );
DFFRX4TS R_965 ( .D(Raw_mant_NRM_SWR[17]), .CK(clk), .RN(n5659), .Q(n5695)
);
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1181), .CK(clk), .RN(n6264), .Q(
Raw_mant_NRM_SWR[17]), .QN(n5572) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_52_ ( .D(n1206), .CK(clk), .RN(n6270), .Q(
DmP_EXP_EWSW[52]), .QN(n3329) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_53_ ( .D(n1205), .CK(clk), .RN(n6270), .Q(
DmP_EXP_EWSW[53]), .QN(n3331) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[8]), .QN(n2288) );
DFFRX4TS SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n1608), .CK(clk), .RN(n5633),
.Q(shift_value_SHT2_EWR[3]), .QN(n5344) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_54_ ( .D(n1533), .CK(clk), .RN(n6272), .Q(
DMP_EXP_EWSW[54]), .QN(n5556) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n6271), .Q(
DMP_exp_NRM2_EW[2]), .QN(n1867) );
DFFRX4TS INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n6276),
.Q(intDY_EWSW[9]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_38_ ( .D(n1032), .CK(clk), .RN(n6239), .Q(
DmP_mant_SFG_SWR[38]) );
DFFRX4TS inst_ShiftRegister_Q_reg_0_ ( .D(n1795), .CK(clk), .RN(n6285), .Q(
Shift_reg_FLAGS_7[0]), .QN(n5571) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_28_ ( .D(n1170), .CK(clk), .RN(n5625), .Q(
Raw_mant_NRM_SWR[28]), .QN(n5492) );
DFFRX4TS SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1361), .CK(clk), .RN(n2514), .Q(
DMP_exp_NRM2_EW[0]) );
DFFRX4TS inst_ShiftRegister_Q_reg_2_ ( .D(n1797), .CK(clk), .RN(n5658), .Q(
Shift_reg_FLAGS_7[2]), .QN(n5446) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_40_ ( .D(n1399), .CK(clk), .RN(n5670), .Q(
DMP_SFG[40]), .QN(n5399) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1175), .CK(clk), .RN(n4466), .Q(
Raw_mant_NRM_SWR[23]), .QN(n5342) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_53_ ( .D(n1145), .CK(clk), .RN(n6267), .Q(
Raw_mant_NRM_SWR[53]), .QN(n5574) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_41_ ( .D(n1157), .CK(clk), .RN(n6268), .Q(
Raw_mant_NRM_SWR[41]), .QN(n5422) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_27_ ( .D(n1171), .CK(clk), .RN(n6240), .Q(
Raw_mant_NRM_SWR[27]), .QN(n5432) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1104), .CK(clk), .RN(n5628), .Q(
Raw_mant_NRM_SWR[9]), .QN(n5340) );
DFFRX4TS SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1729), .CK(clk), .RN(n6269),
.Q(left_right_SHT2), .QN(n2449) );
DFFRX2TS R_510 ( .D(Raw_mant_NRM_SWR[26]), .CK(clk), .RN(n5628), .Q(n5963)
);
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_44_ ( .D(n1026), .CK(clk), .RN(n6239), .Q(
DmP_mant_SFG_SWR[44]), .QN(n5552) );
DFFSX2TS R_429 ( .D(n6224), .CK(clk), .SN(n5655), .Q(n6020) );
DFFRX2TS SGF_STAGE_DMP_Q_reg_39_ ( .D(n1402), .CK(clk), .RN(n6289), .Q(
DMP_SFG[39]), .QN(n5400) );
DFFSX2TS R_380 ( .D(n2499), .CK(clk), .SN(n5669), .Q(n6055) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_30_ ( .D(n1168), .CK(clk), .RN(n6269), .Q(
Raw_mant_NRM_SWR[30]), .QN(n5445) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1049), .CK(clk), .RN(n6237), .Q(
DmP_mant_SFG_SWR[21]), .QN(n5564) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n1803), .CK(clk), .RN(
n6253), .Q(inst_FSM_INPUT_ENABLE_state_reg[2]), .QN(n5494) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1045), .CK(clk), .RN(n6237), .Q(
DmP_mant_SFG_SWR[25]) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_31_ ( .D(n1167), .CK(clk), .RN(n6267), .Q(
Raw_mant_NRM_SWR[31]), .QN(n5442) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_52_ ( .D(n1018), .CK(clk), .RN(n2512),
.QN(n5548) );
DFFRX2TS R_311 ( .D(n6147), .CK(clk), .RN(n2515), .Q(n6160) );
DFFSX2TS R_633 ( .D(n2556), .CK(clk), .SN(n5657), .Q(n5891) );
DFFSX4TS R_506 ( .D(DmP_mant_SHT1_SW[30]), .CK(clk), .SN(n5664), .Q(n5966)
);
DFFSX2TS R_409 ( .D(n5032), .CK(clk), .SN(n5673), .Q(n6035) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1046), .CK(clk), .RN(n6237), .Q(
DmP_mant_SFG_SWR[24]), .QN(n5521) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1048), .CK(clk), .RN(n6237), .Q(
DmP_mant_SFG_SWR[22]), .QN(n5563) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_34_ ( .D(n1164), .CK(clk), .RN(n6268), .Q(
Raw_mant_NRM_SWR[34]), .QN(n5437) );
DFFSX2TS R_453 ( .D(n6223), .CK(clk), .SN(n5648), .Q(n6003) );
DFFSX2TS R_449 ( .D(n2564), .CK(clk), .SN(n6257), .Q(n6006) );
DFFRX4TS inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n1802), .CK(clk), .RN(
n5643), .Q(inst_FSM_INPUT_ENABLE_state_reg[0]), .QN(n5444) );
DFFSX2TS R_641 ( .D(n6226), .CK(clk), .SN(n5665), .Q(n5885) );
DFFRX2TS R_313 ( .D(n6381), .CK(clk), .RN(n2543), .Q(n6105) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_39_ ( .D(n1031), .CK(clk), .RN(n6239), .Q(
DmP_mant_SFG_SWR[39]) );
DFFSX4TS R_978 ( .D(n2287), .CK(clk), .SN(n5631), .QN(n2436) );
DFFRX4TS R_979 ( .D(Raw_mant_NRM_SWR[2]), .CK(clk), .RN(n5629), .QN(n2379)
);
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_41_ ( .D(n1029), .CK(clk), .RN(n6239), .Q(
DmP_mant_SFG_SWR[41]), .QN(n5561) );
DFFSX4TS R_980 ( .D(n6201), .CK(clk), .SN(n5630), .Q(n5687) );
DFFSX4TS R_321 ( .D(n6408), .CK(clk), .SN(n5639), .Q(n6099) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1133), .CK(clk), .RN(n5644), .Q(
Raw_mant_NRM_SWR[2]), .QN(n5412) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1055), .CK(clk), .RN(n5623), .Q(
DmP_mant_SFG_SWR[15]), .QN(n5566) );
DFFSX2TS R_483 ( .D(n3046), .CK(clk), .SN(n5641), .Q(n5980) );
DFFSX4TS R_964 ( .D(n2553), .CK(clk), .SN(n5661), .Q(n5696) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_26_ ( .D(n1044), .CK(clk), .RN(n6238), .Q(
DmP_mant_SFG_SWR[26]), .QN(n5520) );
DFFRX4TS inst_ShiftRegister_Q_reg_1_ ( .D(n1796), .CK(clk), .RN(n6289), .Q(
Shift_reg_FLAGS_7[1]), .QN(n2384) );
DFFSX2TS R_951 ( .D(n6204), .CK(clk), .SN(n5645), .Q(n5702) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_49_ ( .D(n1058), .CK(clk), .RN(n2520), .Q(
final_result_ieee[49]), .QN(n5502) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_51_ ( .D(n1056), .CK(clk), .RN(n6289), .Q(
final_result_ieee[51]), .QN(n5507) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1068), .CK(clk), .RN(n6235), .Q(
final_result_ieee[2]), .QN(n5523) );
DFFSX4TS R_673 ( .D(n1645), .CK(clk), .SN(n5679), .Q(n5861) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_52_ ( .D(n1146), .CK(clk), .RN(n6267), .Q(
Raw_mant_NRM_SWR[52]), .QN(n5417) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_40_ ( .D(n1030), .CK(clk), .RN(n6239), .Q(
DmP_mant_SFG_SWR[40]), .QN(n5562) );
DFFSX2TS R_479 ( .D(n3046), .CK(clk), .SN(n5677), .Q(n5983) );
DFFSX2TS R_342 ( .D(n6320), .CK(clk), .SN(n4463), .Q(n6080) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_48_ ( .D(n1022), .CK(clk), .RN(n2511), .Q(
DmP_mant_SFG_SWR[48]), .QN(n5550) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_32_ ( .D(n1038), .CK(clk), .RN(n6238), .Q(
DmP_mant_SFG_SWR[32]), .QN(n5568) );
DFFSX4TS R_611 ( .D(n6227), .CK(clk), .SN(n5665), .Q(n5902) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1089), .CK(clk), .RN(n6234), .Q(
final_result_ieee[25]), .QN(n5535) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1099), .CK(clk), .RN(n6234), .Q(
final_result_ieee[24]), .QN(n5534) );
DFFSX2TS R_907 ( .D(n2553), .CK(clk), .SN(n5658), .Q(n5730) );
DFFSX2TS R_329 ( .D(n6360), .CK(clk), .SN(n5647), .Q(n6091) );
DFFRX1TS FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1083), .CK(clk), .RN(n6234), .Q(
final_result_ieee[21]), .QN(n5531) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1293), .CK(clk), .RN(n2543), .Q(
DmP_mant_SHT1_SW[8]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1305), .CK(clk), .RN(n2543), .Q(
DmP_mant_SHT1_SW[2]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_51_ ( .D(n1207), .CK(clk), .RN(n6260),
.Q(DmP_mant_SHT1_SW[51]), .QN(n5617) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_57_ ( .D(n1530), .CK(clk), .RN(n6274), .Q(
DMP_EXP_EWSW[57]), .QN(n5553) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_28_ ( .D(n1253), .CK(clk), .RN(n2569),
.Q(DmP_mant_SHT1_SW[28]), .QN(n5576) );
DFFRX4TS SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1602), .CK(clk), .RN(n2540),
.Q(Shift_amount_SHT1_EWR[2]) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_37_ ( .D(n1235), .CK(clk), .RN(n5683),
.Q(DmP_mant_SHT1_SW[37]), .QN(n5588) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_26_ ( .D(n1257), .CK(clk), .RN(n5685),
.Q(DmP_mant_SHT1_SW[26]), .QN(n5591) );
DFFRX4TS INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1730), .CK(clk), .RN(n2514), .Q(
intAS) );
DFFSX2TS R_333 ( .D(n2564), .CK(clk), .SN(n5630), .Q(n6089) );
DFFSX2TS R_345 ( .D(n6223), .CK(clk), .SN(n5676), .Q(n6079) );
DFFSX2TS R_349 ( .D(n2499), .CK(clk), .SN(n2541), .Q(n6077) );
DFFSX2TS R_413 ( .D(n2499), .CK(clk), .SN(n5663), .Q(n6031) );
DFFSX2TS R_425 ( .D(n2499), .CK(clk), .SN(n5640), .Q(n6023) );
DFFSX2TS R_437 ( .D(n2498), .CK(clk), .SN(n5641), .QN(n1898) );
DFFSX2TS R_461 ( .D(n2498), .CK(clk), .SN(n5649), .Q(n5995) );
DFFSX2TS R_498 ( .D(n2498), .CK(clk), .SN(n5678), .Q(n5970) );
DFFSX2TS R_571 ( .D(n6224), .CK(clk), .SN(n5673), .Q(n5936) );
DFFSX2TS R_647 ( .D(n6224), .CK(clk), .SN(n5657), .Q(n5881) );
DFFSX2TS R_702 ( .D(n2523), .CK(clk), .SN(n5680), .Q(n5847) );
DFFSX2TS R_698 ( .D(n2557), .CK(clk), .SN(n5642), .Q(n5850) );
DFFSX2TS R_694 ( .D(n2557), .CK(clk), .SN(n5650), .Q(n5852) );
DFFSX2TS R_685 ( .D(n2557), .CK(clk), .SN(n2520), .Q(n5855) );
DFFSX2TS R_915 ( .D(n2557), .CK(clk), .SN(n2544), .Q(n5724) );
DFFSX2TS R_909 ( .D(n2557), .CK(clk), .SN(n5657), .Q(n5728) );
DFFSX2TS R_893 ( .D(n2557), .CK(clk), .SN(n5666), .Q(n5737) );
DFFSX2TS R_885 ( .D(n2557), .CK(clk), .SN(n5651), .Q(n5742) );
DFFSX2TS R_831 ( .D(n2557), .CK(clk), .SN(n6258), .Q(n5773) );
DFFSX2TS R_297 ( .D(n2557), .CK(clk), .SN(n5646), .Q(n6116) );
DFFSX4TS R_717 ( .D(n6201), .CK(clk), .SN(n5680), .Q(n5836) );
DFFSX4TS R_723 ( .D(n6227), .CK(clk), .SN(n5632), .Q(n5833) );
DFFSX2TS R_927 ( .D(n2553), .CK(clk), .SN(n5669), .Q(n5716) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_54_ ( .D(n1204), .CK(clk), .RN(n6270), .Q(
DmP_EXP_EWSW[54]), .QN(n3330) );
DFFSX2TS R_266 ( .D(n6204), .CK(clk), .SN(n5677), .Q(n6133) );
DFFSX2TS R_822 ( .D(n6203), .CK(clk), .SN(n5666), .Q(n5780) );
DFFSX2TS R_294 ( .D(n2500), .CK(clk), .SN(n5630), .Q(n6117) );
DFFSX2TS R_535 ( .D(n6220), .CK(clk), .SN(n5664), .Q(n5952) );
DFFSX2TS R_531 ( .D(n6222), .CK(clk), .SN(n5656), .Q(n5954) );
DFFSX2TS R_403 ( .D(n2528), .CK(clk), .SN(n5640), .Q(n6039) );
DFFSX2TS R_395 ( .D(n6222), .CK(clk), .SN(n2514), .Q(n6044) );
DFFSX2TS R_424 ( .D(n6222), .CK(clk), .SN(n5640), .Q(n6024) );
DFFSX2TS R_456 ( .D(n2528), .CK(clk), .SN(n5672), .Q(n6000) );
DFFSX2TS R_468 ( .D(n6220), .CK(clk), .SN(n5635), .Q(n5993) );
DFFSX2TS R_476 ( .D(n6222), .CK(clk), .SN(n2533), .Q(n5986) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_5_ ( .D(n1582), .CK(clk), .RN(n6465), .Q(
DMP_EXP_EWSW[5]) );
DFFRX4TS NRM_STAGE_FLAGS_Q_reg_0_ ( .D(n1195), .CK(clk), .RN(n6465), .Q(
ZERO_FLAG_NRM) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_29_ ( .D(n1251), .CK(clk), .RN(n6465),
.Q(DmP_mant_SHT1_SW[29]), .QN(n5610) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_35_ ( .D(n1239), .CK(clk), .RN(n6465),
.Q(DmP_mant_SHT1_SW[35]), .QN(n5603) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_43_ ( .D(n1223), .CK(clk), .RN(n6465),
.Q(DmP_mant_SHT1_SW[43]), .QN(n5413) );
DFFSX2TS R_972 ( .D(n2500), .CK(clk), .SN(n5654), .Q(n5690) );
DFFSX2TS R_291 ( .D(n2501), .CK(clk), .SN(n5646), .Q(n6118) );
DFFSX4TS R_923 ( .D(n2508), .CK(clk), .SN(n6262), .Q(n5718) );
DFFRX4TS NRM_STAGE_Raw_mant_Q_reg_49_ ( .D(n1149), .CK(clk), .RN(n6267), .Q(
Raw_mant_NRM_SWR[49]), .QN(n3367) );
DFFSX2TS R_67 ( .D(n6332), .CK(clk), .SN(n6258), .Q(n6191) );
DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_47_ ( .D(n1215), .CK(clk), .RN(n5659),
.Q(DmP_mant_SHT1_SW[47]) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_34_ ( .D(n1036), .CK(clk), .RN(n6238), .Q(
DmP_mant_SFG_SWR[34]), .QN(n5567) );
DFFRHQX2TS INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n5631),
.Q(n2479) );
DFFRX4TS FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1199), .CK(clk), .RN(n5670), .Q(
overflow_flag), .QN(n5411) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_17_ ( .D(n1570), .CK(clk), .RN(n6242), .Q(
DMP_EXP_EWSW[17]) );
DFFSX4TS R_779 ( .D(n6418), .CK(clk), .SN(n6286), .Q(n5802) );
DFFRX4TS R_724 ( .D(DmP_mant_SHT1_SW[49]), .CK(clk), .RN(n5629), .Q(n5832)
);
DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_49_ ( .D(n1211), .CK(clk), .RN(n6287),
.Q(DmP_mant_SHT1_SW[49]) );
DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_27_ ( .D(n1255), .CK(clk), .RN(n6266),
.Q(DmP_mant_SHT1_SW[27]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1269), .CK(clk), .RN(n2542),
.Q(DmP_mant_SHT1_SW[20]) );
DFFRHQX2TS SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1283), .CK(clk), .RN(n6236),
.Q(DmP_mant_SHT1_SW[13]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_51_ ( .D(n1019), .CK(clk), .RN(n2511), .Q(
n2451), .QN(n5418) );
DFFSRHQX4TS SGF_STAGE_DmP_mant_Q_reg_28_ ( .D(n1042), .CK(clk), .SN(1'b1),
.RN(n2539), .Q(DmP_mant_SFG_SWR[28]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_53_ ( .D(n1017), .CK(clk), .RN(n2511), .Q(
n2450), .QN(n5547) );
DFFRX4TS SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1295), .CK(clk), .RN(n2533), .Q(
DmP_mant_SHT1_SW[7]), .QN(n5616) );
DFFSX2TS R_176 ( .D(n6340), .CK(clk), .SN(n5662), .QN(n2390) );
DFFRX4TS inst_ShiftRegister_Q_reg_4_ ( .D(n1799), .CK(clk), .RN(n5667), .Q(
n2383), .QN(n5493) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_43_ ( .D(n1027), .CK(clk), .RN(n6239), .Q(
DmP_mant_SFG_SWR[43]) );
DFFRHQX8TS R_876 ( .D(n6147), .CK(clk), .RN(n2514), .Q(n2487) );
DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_39_ ( .D(n1159), .CK(clk), .RN(n6268),
.Q(n2345) );
DFFRX2TS R_761 ( .D(Raw_mant_NRM_SWR[46]), .CK(clk), .RN(n2532), .Q(n5810)
);
DFFSX4TS R_872 ( .D(n1823), .CK(clk), .SN(n5670), .Q(n5750) );
DFFSX4TS R_730 ( .D(n1823), .CK(clk), .SN(n5666), .Q(n5829) );
DFFSX2TS R_114 ( .D(n6344), .CK(clk), .SN(n5661), .Q(n6182) );
DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_54_ ( .D(n1144), .CK(clk), .RN(n6267),
.Q(n2323) );
DFFSX2TS R_253 ( .D(n6370), .CK(clk), .SN(n5639), .Q(n6139) );
DFFRX4TS R_587 ( .D(n6364), .CK(clk), .RN(n5624), .Q(n5924) );
DFFRX4TS R_734 ( .D(n6301), .CK(clk), .RN(n5684), .Q(n5827) );
DFFRX4TS R_853 ( .D(n6295), .CK(clk), .RN(n2540), .Q(n5761) );
DFFRX4TS R_828 ( .D(n6379), .CK(clk), .RN(n5637), .Q(n5776) );
DFFRX4TS R_589 ( .D(n6366), .CK(clk), .RN(n5624), .Q(n5922) );
DFFSX2TS R_513 ( .D(n2287), .CK(clk), .SN(n5649), .Q(n5961) );
DFFSX2TS R_704 ( .D(n2553), .CK(clk), .SN(n5657), .Q(n5846) );
DFFRHQX4TS EXP_STAGE_DmP_Q_reg_8_ ( .D(n1294), .CK(clk), .RN(n2532), .Q(
n2312) );
DFFSX2TS R_304 ( .D(n6312), .CK(clk), .SN(n5677), .Q(n6110) );
DFFRHQX2TS SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1130), .CK(clk), .RN(n6257),
.Q(n2307) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_49_ ( .D(n1021), .CK(clk), .RN(n2512), .Q(
DmP_mant_SFG_SWR[49]), .QN(n5549) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_45_ ( .D(n1220), .CK(clk), .RN(n6233), .Q(
DmP_EXP_EWSW[45]) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1174), .CK(clk), .RN(n6291),
.Q(n2300) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_45_ ( .D(n1025), .CK(clk), .RN(n6239),
.Q(n2298) );
DFFSX2TS R_252 ( .D(n6371), .CK(clk), .SN(n5639), .Q(n6140) );
DFFRHQX8TS R_238 ( .D(n6147), .CK(clk), .RN(n2514), .Q(n2492) );
DFFSX2TS R_376 ( .D(n6342), .CK(clk), .SN(n5662), .Q(n6058) );
DFFRHQX2TS INPUT_STAGE_OPERANDY_Q_reg_53_ ( .D(n1675), .CK(clk), .RN(n6279),
.Q(n2292) );
DFFRX4TS SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1047), .CK(clk), .RN(n6237), .Q(
DmP_mant_SFG_SWR[23]) );
DFFSX4TS R_983 ( .D(n5686), .CK(clk), .SN(n2515), .Q(n2488), .QN(n5864) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_52_ ( .D(n1365), .CK(clk), .RN(n6271), .QN(
n5407) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_53_ ( .D(n1360), .CK(clk), .RN(n6271), .QN(
n5406) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_54_ ( .D(n1355), .CK(clk), .RN(n6272), .QN(
n5405) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_55_ ( .D(n1350), .CK(clk), .RN(n6272), .QN(
n5404) );
DFFRX1TS SHT1_STAGE_DMP_Q_reg_56_ ( .D(n1345), .CK(clk), .RN(n6273), .QN(
n5403) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_46_ ( .D(n1217), .CK(clk), .RN(n6262),
.Q(DmP_mant_SHT1_SW[46]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_40_ ( .D(n1229), .CK(clk), .RN(n6261),
.Q(DmP_mant_SHT1_SW[40]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_36_ ( .D(n1237), .CK(clk), .RN(n5683),
.Q(DmP_mant_SHT1_SW[36]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_34_ ( .D(n1241), .CK(clk), .RN(n5683),
.Q(DmP_mant_SHT1_SW[34]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_33_ ( .D(n1243), .CK(clk), .RN(n2567),
.Q(DmP_mant_SHT1_SW[33]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_31_ ( .D(n1247), .CK(clk), .RN(n5683),
.Q(DmP_mant_SHT1_SW[31]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_23_ ( .D(n1263), .CK(clk), .RN(n2568),
.Q(DmP_mant_SHT1_SW[23]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1273), .CK(clk), .RN(n2542),
.Q(DmP_mant_SHT1_SW[18]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1267), .CK(clk), .RN(n6264),
.Q(DmP_mant_SHT1_SW[21]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_30_ ( .D(n1249), .CK(clk), .RN(n5683),
.Q(DmP_mant_SHT1_SW[30]) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_24_ ( .D(n1261), .CK(clk), .RN(n6263),
.Q(DmP_mant_SHT1_SW[24]) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1082), .CK(clk), .RN(n6234), .Q(
final_result_ieee[29]), .QN(n5539) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1091), .CK(clk), .RN(n6235), .Q(
final_result_ieee[7]), .QN(n5528) );
DFFRXLTS R_688 ( .D(n6210), .CK(clk), .RN(n5634), .Q(n5854) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_32_ ( .D(n1555), .CK(clk), .RN(n6248), .Q(
DMP_EXP_EWSW[32]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_30_ ( .D(n1557), .CK(clk), .RN(n6247), .Q(
DMP_EXP_EWSW[30]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_0_ ( .D(n1310), .CK(clk), .RN(n2543), .Q(
DmP_EXP_EWSW[0]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_37_ ( .D(n1550), .CK(clk), .RN(n6286), .Q(
DMP_EXP_EWSW[37]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_26_ ( .D(n1561), .CK(clk), .RN(n6246), .Q(
DMP_EXP_EWSW[26]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_50_ ( .D(n1210), .CK(clk), .RN(n6265), .Q(
DmP_EXP_EWSW[50]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_38_ ( .D(n1234), .CK(clk), .RN(n5671), .Q(
DmP_EXP_EWSW[38]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_25_ ( .D(n1260), .CK(clk), .RN(n6263), .Q(
DmP_EXP_EWSW[25]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_13_ ( .D(n1574), .CK(clk), .RN(n6270), .Q(
DMP_EXP_EWSW[13]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_40_ ( .D(n1230), .CK(clk), .RN(n6261), .Q(
DmP_EXP_EWSW[40]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_49_ ( .D(n1212), .CK(clk), .RN(n6257), .Q(
DmP_EXP_EWSW[49]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_34_ ( .D(n1242), .CK(clk), .RN(n5683), .Q(
DmP_EXP_EWSW[34]) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_29_ ( .D(n1252), .CK(clk), .RN(n6262), .Q(
DmP_EXP_EWSW[29]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_6_ ( .D(n1581), .CK(clk), .RN(n6263), .Q(
DMP_EXP_EWSW[6]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_1_ ( .D(n1586), .CK(clk), .RN(n6236), .Q(
DMP_EXP_EWSW[1]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_12_ ( .D(n1575), .CK(clk), .RN(n6264), .Q(
DMP_EXP_EWSW[12]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_26_ ( .D(n1258), .CK(clk), .RN(n6286), .Q(
DmP_EXP_EWSW[26]) );
DFFRX4TS R_809 ( .D(n6219), .CK(clk), .RN(n5684), .Q(n5787) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_23_ ( .D(n1264), .CK(clk), .RN(n2566), .Q(
DmP_EXP_EWSW[23]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_41_ ( .D(n1546), .CK(clk), .RN(n6250), .Q(
DMP_EXP_EWSW[41]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_12_ ( .D(n1286), .CK(clk), .RN(n6256), .Q(
DmP_EXP_EWSW[12]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_35_ ( .D(n1552), .CK(clk), .RN(n1880), .Q(
DMP_EXP_EWSW[35]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_11_ ( .D(n1576), .CK(clk), .RN(n6265), .Q(
DMP_EXP_EWSW[11]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_7_ ( .D(n1580), .CK(clk), .RN(n6265), .Q(
DMP_EXP_EWSW[7]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_56_ ( .D(n1202), .CK(clk), .RN(n6270), .Q(
DmP_EXP_EWSW[56]), .QN(n5488) );
DFFRXLTS EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1522), .CK(clk), .RN(n5633), .Q(
SIGN_FLAG_EXP) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_19_ ( .D(n1272), .CK(clk), .RN(n5670), .Q(
DmP_EXP_EWSW[19]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_13_ ( .D(n1284), .CK(clk), .RN(n6256), .Q(
DmP_EXP_EWSW[13]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_1_ ( .D(n1308), .CK(clk), .RN(n2543), .Q(
DmP_EXP_EWSW[1]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_36_ ( .D(n1551), .CK(clk), .RN(n6233), .Q(
DMP_EXP_EWSW[36]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_9_ ( .D(n1292), .CK(clk), .RN(n2532), .Q(
DmP_EXP_EWSW[9]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_27_ ( .D(n1256), .CK(clk), .RN(n6266), .Q(
DmP_EXP_EWSW[27]) );
DFFSX2TS R_443 ( .D(n3046), .CK(clk), .SN(n5634), .Q(n6010) );
DFFRXLTS FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1108), .CK(clk), .RN(n6234), .Q(
final_result_ieee[23]), .QN(n5533) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_44_ ( .D(n1543), .CK(clk), .RN(n6251), .Q(
DMP_EXP_EWSW[44]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_51_ ( .D(n1208), .CK(clk), .RN(n6260), .Q(
DmP_EXP_EWSW[51]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_10_ ( .D(n1577), .CK(clk), .RN(n6261), .Q(
DMP_EXP_EWSW[10]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_5_ ( .D(n1300), .CK(clk), .RN(n5668), .Q(
DmP_EXP_EWSW[5]) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_19_ ( .D(n1568), .CK(clk), .RN(n6243), .Q(
n2259) );
DFFRHQX8TS R_625 ( .D(n6147), .CK(clk), .RN(n2514), .Q(n2257) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_18_ ( .D(n1274), .CK(clk), .RN(n2540), .Q(
n2256) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_21_ ( .D(n1566), .CK(clk), .RN(n6244), .Q(
n2255) );
DFFSX2TS R_411 ( .D(n6220), .CK(clk), .SN(n5663), .Q(n6033) );
DFFRHQX4TS NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1178), .CK(clk), .RN(n6236),
.Q(n2252) );
DFFRHQX2TS INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n5635),
.Q(n2250) );
DFFSX2TS R_991 ( .D(n3582), .CK(clk), .SN(n5659), .Q(n2249) );
DFFSX2TS R_992 ( .D(n3583), .CK(clk), .SN(n5659), .Q(n2248) );
DFFSX2TS R_993 ( .D(n3581), .CK(clk), .SN(n5659), .Q(n2247) );
DFFSX2TS R_994 ( .D(n2690), .CK(clk), .SN(n5619), .Q(n2246) );
DFFRX2TS R_995 ( .D(n5183), .CK(clk), .RN(n5619), .Q(n2245) );
DFFSX2TS R_996 ( .D(n6215), .CK(clk), .SN(n4463), .Q(n2244) );
DFFSX2TS R_997 ( .D(n3616), .CK(clk), .SN(n5618), .Q(n2243) );
DFFSX2TS R_998 ( .D(n3617), .CK(clk), .SN(n5621), .Q(n2242) );
DFFSX2TS R_999 ( .D(n3615), .CK(clk), .SN(n6232), .Q(n2241) );
DFFSX2TS R_1000 ( .D(n3598), .CK(clk), .SN(n1881), .Q(n2240) );
DFFSX2TS R_1001 ( .D(n3599), .CK(clk), .SN(n1882), .Q(n2239) );
DFFSX2TS R_1002 ( .D(n3597), .CK(clk), .SN(n1881), .Q(n2238) );
DFFSX2TS R_1003 ( .D(n4387), .CK(clk), .SN(n6259), .Q(n2237) );
DFFSX2TS R_1004 ( .D(n4388), .CK(clk), .SN(n6259), .Q(n2236) );
DFFSX2TS R_1005 ( .D(n4386), .CK(clk), .SN(n6259), .Q(n2235) );
DFFSX1TS R_299 ( .D(n6358), .CK(clk), .SN(n5646), .Q(n6115) );
DFFSX2TS R_575 ( .D(n6226), .CK(clk), .SN(n5665), .Q(n5933) );
DFFSX4TS R_502 ( .D(n6200), .CK(clk), .SN(n5631), .Q(n5967) );
DFFSX2TS R_719 ( .D(n6227), .CK(clk), .SN(n5651), .Q(n5835) );
DFFSX4TS R_583 ( .D(n1906), .CK(clk), .SN(n5626), .Q(n5928) );
DFFSX1TS R_121 ( .D(n6347), .CK(clk), .SN(n5654), .Q(n6177) );
DFFSX2TS R_442 ( .D(n5612), .CK(clk), .SN(n5672), .QN(n2227) );
DFFSX2TS R_465 ( .D(n2498), .CK(clk), .SN(n5656), .QN(n2221) );
DFFSX1TS R_405 ( .D(n6224), .CK(clk), .SN(n5640), .Q(n6037) );
DFFSX4TS R_372 ( .D(n2301), .CK(clk), .SN(n5681), .QN(n2438) );
DFFSX1TS R_280 ( .D(n6403), .CK(clk), .SN(n5625), .Q(n6125) );
DFFSX1TS R_427 ( .D(n2528), .CK(clk), .SN(n5655), .Q(n6021) );
DFFSX1TS R_397 ( .D(n2498), .CK(clk), .SN(n2521), .Q(n6043) );
DFFSX2TS R_398 ( .D(n5415), .CK(clk), .SN(n2514), .Q(n6042) );
DFFSX1TS R_715 ( .D(n2556), .CK(clk), .SN(n5680), .Q(n5837) );
DFFSX1TS R_358 ( .D(n6222), .CK(clk), .SN(n5631), .Q(n6070) );
DFFSX1TS R_384 ( .D(n6222), .CK(clk), .SN(n5647), .Q(n6052) );
DFFRX2TS R_1017 ( .D(n5571), .CK(clk), .RN(n5643), .Q(n2218) );
DFFSX1TS R_353 ( .D(n2528), .CK(clk), .SN(n5684), .Q(n6074) );
DFFSX1TS R_637 ( .D(n6225), .CK(clk), .SN(n5627), .Q(n5888) );
DFFSX1TS R_626 ( .D(n6225), .CK(clk), .SN(n5650), .Q(n5895) );
DFFSX1TS R_471 ( .D(n3046), .CK(clk), .SN(n5682), .Q(n5990) );
DFFSX1TS R_451 ( .D(n3046), .CK(clk), .SN(n5648), .Q(n6004) );
DFFSX1TS R_796 ( .D(n6212), .CK(clk), .SN(n5642), .Q(n5794) );
DFFSX4TS R_847 ( .D(n2553), .CK(clk), .SN(n5680), .Q(n5765) );
DFFSX1TS R_373 ( .D(n2499), .CK(clk), .SN(n5682), .Q(n6061) );
DFFSX1TS R_613 ( .D(n6222), .CK(clk), .SN(n5679), .Q(n5901) );
DFFSX2TS R_533 ( .D(n2506), .CK(clk), .SN(n5664), .Q(n5953) );
DFFRX2TS R_888 ( .D(Raw_mant_NRM_SWR[14]), .CK(clk), .RN(n5671), .Q(n5740)
);
DFFSX2TS R_1027 ( .D(n6462), .CK(clk), .SN(n6292), .Q(n2214) );
DFFSX1TS R_539 ( .D(n6222), .CK(clk), .SN(n5664), .Q(n5950) );
DFFSX1TS R_433 ( .D(n6224), .CK(clk), .SN(n5631), .Q(n6016) );
DFFSX1TS R_432 ( .D(n6220), .CK(clk), .SN(n5631), .Q(n6017) );
DFFRX2TS R_928 ( .D(Raw_mant_NRM_SWR[10]), .CK(clk), .RN(n5668), .Q(n5715)
);
DFFSX1TS R_706 ( .D(n6212), .CK(clk), .SN(n5657), .Q(n5844) );
DFFRX2TS R_705 ( .D(Raw_mant_NRM_SWR[41]), .CK(clk), .RN(n5653), .Q(n5845)
);
DFFRX2TS R_969 ( .D(Raw_mant_NRM_SWR[33]), .CK(clk), .RN(n5659), .Q(n5692)
);
DFFSX4TS R_966 ( .D(n1644), .CK(clk), .SN(n5661), .Q(n5694) );
DFFRX2TS R_1031 ( .D(n5571), .CK(clk), .RN(n6256), .Q(n2213) );
DFFSX2TS R_1032 ( .D(n2088), .CK(clk), .SN(n5619), .Q(n2212) );
DFFSX2TS R_1034 ( .D(n2509), .CK(clk), .SN(n5619), .Q(n2211) );
DFFSX2TS R_949 ( .D(n2497), .CK(clk), .SN(n5667), .Q(n5703) );
DFFSX1TS R_563 ( .D(n6225), .CK(clk), .SN(n5673), .Q(n5941) );
DFFSX2TS R_679 ( .D(n2500), .CK(clk), .SN(n5682), .Q(n5858) );
DFFRX2TS R_973 ( .D(DmP_mant_SHT1_SW[45]), .CK(clk), .RN(n5652), .Q(n5689)
);
DFFSX2TS R_1038 ( .D(n2453), .CK(clk), .SN(n5622), .Q(n2209) );
DFFSX1TS R_547 ( .D(n2528), .CK(clk), .SN(n2568), .Q(n5947) );
DFFSX4TS R_824 ( .D(n6200), .CK(clk), .SN(n5666), .Q(n5778) );
DFFSX2TS R_891 ( .D(n2501), .CK(clk), .SN(n5666), .Q(n5738) );
DFFSX2TS R_1041 ( .D(n2088), .CK(clk), .SN(n5618), .Q(n2208) );
DFFSX1TS R_529 ( .D(n6225), .CK(clk), .SN(n5656), .Q(n5955) );
DFFRXLTS R_873 ( .D(Raw_mant_NRM_SWR[6]), .CK(clk), .RN(n5668), .Q(n5749) );
DFFSX4TS R_829 ( .D(n1823), .CK(clk), .SN(n5676), .Q(n5775) );
DFFRX4TS R_1044 ( .D(DmP_mant_SHT1_SW[44]), .CK(clk), .RN(n5652), .Q(n2206)
);
DFFSX2TS R_1045 ( .D(n5345), .CK(clk), .SN(n5650), .Q(n2205) );
DFFSX2TS R_1046 ( .D(n5492), .CK(clk), .SN(n2567), .Q(n2204) );
DFFSX2TS R_1047 ( .D(n6396), .CK(clk), .SN(n5654), .Q(n2203) );
DFFRX4TS R_1048 ( .D(n2873), .CK(clk), .RN(n5628), .Q(n2202) );
DFFRX4TS R_1049 ( .D(DmP_mant_SHT1_SW[29]), .CK(clk), .RN(n5675), .Q(n2201)
);
DFFRX4TS R_1050 ( .D(DmP_mant_SHT1_SW[46]), .CK(clk), .RN(n5644), .Q(n2200)
);
DFFRX4TS R_1051 ( .D(DmP_mant_SHT1_SW[40]), .CK(clk), .RN(n5659), .Q(n2199)
);
DFFRX4TS R_1052 ( .D(DmP_mant_SHT1_SW[36]), .CK(clk), .RN(n5660), .Q(n2198)
);
DFFRX4TS R_1053 ( .D(DmP_mant_SHT1_SW[34]), .CK(clk), .RN(n5643), .Q(n2197)
);
DFFRX4TS R_1054 ( .D(DmP_mant_SHT1_SW[33]), .CK(clk), .RN(n5676), .Q(n2196)
);
DFFRX4TS R_1055 ( .D(DmP_mant_SHT1_SW[31]), .CK(clk), .RN(n5671), .Q(n2195)
);
DFFRX4TS R_1056 ( .D(DmP_mant_SHT1_SW[23]), .CK(clk), .RN(n5629), .Q(n2194)
);
DFFRX4TS R_1057 ( .D(DmP_mant_SHT1_SW[18]), .CK(clk), .RN(n5633), .Q(n2193)
);
DFFRX4TS R_1058 ( .D(DmP_mant_SHT1_SW[21]), .CK(clk), .RN(n5623), .Q(n2192)
);
DFFSX2TS R_1060 ( .D(n5339), .CK(clk), .SN(n5630), .Q(n2190) );
DFFSX2TS R_1061 ( .D(n6207), .CK(clk), .SN(n5658), .Q(n2189), .QN(n2188) );
DFFSX2TS R_1062 ( .D(n5429), .CK(clk), .SN(n5647), .Q(n2187), .QN(n2186) );
DFFSX2TS R_1063 ( .D(n5341), .CK(clk), .SN(n5680), .Q(n2185) );
DFFSX4TS R_1064 ( .D(n5490), .CK(clk), .SN(n2520), .Q(n2184) );
DFFSX4TS R_1065 ( .D(n5424), .CK(clk), .SN(n5669), .Q(n2183), .QN(n1907) );
DFFSX2TS R_1066 ( .D(n5443), .CK(clk), .SN(n5648), .Q(n2182) );
DFFSX2TS R_1067 ( .D(n5441), .CK(clk), .SN(n5662), .Q(n2181), .QN(n2180) );
DFFSX2TS R_1068 ( .D(n5343), .CK(clk), .SN(n5679), .Q(n2179) );
DFFSX2TS R_1069 ( .D(n3371), .CK(clk), .SN(n5656), .Q(n2178), .QN(n2177) );
DFFSX2TS R_1070 ( .D(n6209), .CK(clk), .SN(n5647), .Q(n2176) );
DFFSX2TS R_1071 ( .D(n3364), .CK(clk), .SN(n5672), .Q(n2175) );
DFFSX2TS R_1073 ( .D(n5426), .CK(clk), .SN(n5673), .Q(n2173) );
DFFRX2TS R_1074 ( .D(DmP_mant_SHT1_SW[16]), .CK(clk), .RN(n5671), .Q(n2172)
);
DFFRX2TS R_1075 ( .D(DmP_mant_SHT1_SW[10]), .CK(clk), .RN(n5637), .Q(n2171)
);
DFFRX4TS R_1076 ( .D(DmP_mant_SHT1_SW[50]), .CK(clk), .RN(n5637), .Q(n2170)
);
DFFRX4TS R_1078 ( .D(DmP_mant_SHT1_SW[38]), .CK(clk), .RN(n5644), .Q(n2168)
);
DFFRX4TS R_1079 ( .D(DmP_mant_SHT1_SW[25]), .CK(clk), .RN(n5675), .Q(n2167)
);
DFFRX2TS R_1080 ( .D(DmP_mant_SHT1_SW[14]), .CK(clk), .RN(n5645), .Q(n2166)
);
DFFRX2TS R_1081 ( .D(DmP_mant_SHT1_SW[12]), .CK(clk), .RN(n5653), .Q(n2165)
);
DFFRX2TS R_1082 ( .D(DmP_mant_SHT1_SW[9]), .CK(clk), .RN(n5637), .Q(n2164)
);
DFFRX4TS R_1083 ( .D(DmP_mant_SHT1_SW[17]), .CK(clk), .RN(n5648), .Q(n2163)
);
DFFRX2TS R_1084 ( .D(DmP_mant_SHT1_SW[48]), .CK(clk), .RN(n5629), .Q(n2162)
);
DFFRX2TS R_1085 ( .D(DmP_mant_SHT1_SW[32]), .CK(clk), .RN(n5671), .Q(n2161)
);
DFFRX2TS R_1086 ( .D(DmP_mant_SHT1_SW[6]), .CK(clk), .RN(n5633), .Q(n2160)
);
DFFSX2TS R_1087 ( .D(n5428), .CK(clk), .SN(n5657), .Q(n2159) );
DFFSX2TS R_1088 ( .D(n6231), .CK(clk), .SN(n5673), .Q(n2158) );
DFFSX2TS R_1089 ( .D(n6216), .CK(clk), .SN(n5646), .Q(n2157) );
DFFRX2TS R_1090 ( .D(DmP_mant_SHT1_SW[11]), .CK(clk), .RN(n5645), .Q(n2156),
.QN(n2155) );
DFFRX4TS R_1092 ( .D(n6228), .CK(clk), .RN(n5676), .Q(n2153) );
DFFSX2TS R_1093 ( .D(n5431), .CK(clk), .SN(n5682), .Q(n2152) );
DFFSX2TS R_1094 ( .D(n5580), .CK(clk), .SN(n5656), .Q(n2151) );
DFFSX2TS R_1095 ( .D(n5579), .CK(clk), .SN(n5642), .Q(n2150) );
DFFRX2TS R_1096 ( .D(n6446), .CK(clk), .RN(n5618), .Q(n2149) );
DFFSX2TS R_1097 ( .D(n5425), .CK(clk), .SN(n5655), .Q(n2148) );
DFFSX2TS R_1098 ( .D(n5572), .CK(clk), .SN(n5676), .Q(n2147), .QN(n2146) );
DFFRX2TS R_1099 ( .D(n6452), .CK(clk), .RN(n5618), .Q(n2145) );
DFFRX2TS R_1100 ( .D(n6443), .CK(clk), .RN(n2512), .Q(n2144) );
DFFSX2TS R_1102 ( .D(n5442), .CK(clk), .SN(n5674), .Q(n2143), .QN(n2142) );
DFFSX2TS R_1103 ( .D(n5437), .CK(clk), .SN(n5665), .Q(n2141) );
DFFRX2TS R_1105 ( .D(n2572), .CK(clk), .RN(n5638), .Q(n2138) );
DFFRX2TS R_1106 ( .D(DmP_mant_SHT1_SW[8]), .CK(clk), .RN(n5653), .Q(n2137),
.QN(n2136) );
DFFRX4TS R_1107 ( .D(DmP_mant_SHT1_SW[2]), .CK(clk), .RN(n5653), .Q(n2135)
);
DFFRX2TS R_1108 ( .D(DmP_mant_SHT1_SW[26]), .CK(clk), .RN(n5623), .Q(n2134)
);
DFFRX4TS R_1110 ( .D(DmP_mant_SHT1_SW[42]), .CK(clk), .RN(n5638), .Q(n2132)
);
DFFRX4TS R_1111 ( .D(DmP_mant_SHT1_SW[43]), .CK(clk), .RN(n5637), .Q(n2131)
);
DFFRX4TS R_1112 ( .D(DmP_mant_SHT1_SW[47]), .CK(clk), .RN(n5629), .Q(n2130)
);
DFFSX2TS R_1113 ( .D(n2527), .CK(clk), .SN(n5650), .Q(n2129) );
DFFRX2TS R_1114 ( .D(DmP_mant_SHT1_SW[27]), .CK(clk), .RN(n5676), .Q(n2128),
.QN(n1903) );
DFFRX2TS R_1115 ( .D(DmP_mant_SHT1_SW[13]), .CK(clk), .RN(n6256), .Q(n2127)
);
DFFRX4TS R_1116 ( .D(DmP_mant_SHT1_SW[30]), .CK(clk), .RN(n5675), .Q(n2126)
);
DFFRX2TS R_1117 ( .D(DmP_mant_SHT1_SW[24]), .CK(clk), .RN(n5624), .Q(n2125)
);
DFFSX2TS R_1120 ( .D(n2253), .CK(clk), .SN(n5663), .Q(n2124) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_40_ ( .D(n1547), .CK(clk), .RN(n2540), .Q(
n2123) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_43_ ( .D(n1544), .CK(clk), .RN(n6250), .Q(
n2122) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_3_ ( .D(n1304), .CK(clk), .RN(n5668), .Q(
DmP_EXP_EWSW[3]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_44_ ( .D(n1222), .CK(clk), .RN(n6287), .Q(
DmP_EXP_EWSW[44]) );
DFFRHQX2TS FRMT_STAGE_DATAOUT_Q_reg_45_ ( .D(n1077), .CK(clk), .RN(n2520),
.Q(final_result_ieee[45]) );
DFFSX2TS R_960 ( .D(n6200), .CK(clk), .SN(n5649), .Q(n5697) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n6245), .Q(
DMP_SFG[26]), .QN(n5472) );
DFFSX4TS R_414 ( .D(n5583), .CK(clk), .SN(n5663), .Q(n6030) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_47_ ( .D(n1023), .CK(clk), .RN(n2512), .Q(
DmP_mant_SFG_SWR[47]), .QN(n5551) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1050), .CK(clk), .RN(n6237), .Q(
DmP_mant_SFG_SWR[20]), .QN(n5565) );
DFFRX4TS SGF_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n6246), .Q(
DMP_SFG[27]), .QN(n5516) );
DFFSX4TS R_810 ( .D(n2496), .CK(clk), .SN(n5685), .Q(n5786) );
DFFSX4TS R_1059 ( .D(n6221), .CK(clk), .SN(n6291), .Q(n2191) );
DFFSX2TS R_579 ( .D(n6226), .CK(clk), .SN(n5674), .Q(n5930) );
DFFSX4TS R_1104 ( .D(n5412), .CK(clk), .SN(n6290), .Q(n2140), .QN(n2139) );
DFFRX4TS R_1077 ( .D(DmP_mant_SHT1_SW[19]), .CK(clk), .RN(n2540), .Q(n2169)
);
DFFRX4TS R_731 ( .D(Raw_mant_NRM_SWR[9]), .CK(clk), .RN(n5660), .QN(n2410)
);
DFFSX4TS R_651 ( .D(n6226), .CK(clk), .SN(n5665), .Q(n5878) );
DFFRX4TS R_1109 ( .D(DmP_mant_SHT1_SW[35]), .CK(clk), .RN(n5661), .Q(n2133)
);
DFFSX2TS R_377 ( .D(n6341), .CK(clk), .SN(n5662), .Q(n6057) );
DFFSX4TS R_953 ( .D(n6200), .CK(clk), .SN(n6290), .Q(n5701) );
DFFSX4TS R_1014 ( .D(n6221), .CK(clk), .SN(n5656), .Q(n2233), .QN(n1902) );
DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_45_ ( .D(n1683), .CK(clk), .RN(n6278),
.Q(n2299) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1053), .CK(clk), .RN(n6237), .Q(
DmP_mant_SFG_SWR[17]) );
DFFSX2TS R_459 ( .D(n3046), .CK(clk), .SN(n5649), .Q(n5997) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1478), .CK(clk), .RN(n6241), .Q(
DMP_SHT2_EWSW[14]), .QN(n5396) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1463), .CK(clk), .RN(n6243), .Q(
DMP_SHT2_EWSW[19]), .QN(n5391) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_36_ ( .D(n1412), .CK(clk), .RN(n1881), .Q(
DMP_SHT2_EWSW[36]), .QN(n5374) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_42_ ( .D(n1394), .CK(clk), .RN(n6250), .Q(
DMP_SHT2_EWSW[42]), .QN(n5371) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_47_ ( .D(n1379), .CK(clk), .RN(n6252), .Q(
DMP_SHT2_EWSW[47]), .QN(n5366) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_54_ ( .D(n1354), .CK(clk), .RN(n6272), .QN(
n5499) );
DFFRXLTS SHT2_STAGE_DMP_Q_reg_59_ ( .D(n1329), .CK(clk), .RN(n6275), .Q(
DMP_SHT2_EWSW[59]), .QN(n5358) );
DFFRXLTS SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1188), .CK(clk), .RN(n6253), .Q(
SIGN_FLAG_SHT2), .QN(n5397) );
DFFRXLTS R_285 ( .D(n6408), .CK(clk), .RN(n2511), .Q(n6122) );
DFFRXLTS SGF_STAGE_FLAGS_Q_reg_0_ ( .D(n1196), .CK(clk), .RN(n2541), .Q(
ZERO_FLAG_SFG), .QN(n5410) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1297), .CK(clk), .RN(n5668),
.Q(DmP_mant_SHT1_SW[6]) );
DFFRHQX2TS SGF_STAGE_DMP_Q_reg_22_ ( .D(n1453), .CK(clk), .RN(n6292), .Q(
DMP_SFG[22]) );
DFFRX1TS SGF_STAGE_DmP_mant_Q_reg_27_ ( .D(n1043), .CK(clk), .RN(n6238), .Q(
DmP_mant_SFG_SWR[27]), .QN(n5519) );
DFFSX2TS R_592 ( .D(DmP_mant_SHT1_SW[37]), .CK(clk), .SN(n5627), .Q(n5919)
);
DFFRXLTS R_799 ( .D(n6461), .CK(clk), .RN(n2520), .Q(n5793) );
DFFSX1TS R_700 ( .D(n2287), .CK(clk), .SN(n5680), .Q(n5849) );
DFFRXLTS R_578 ( .D(DmP_mant_SHT1_SW[3]), .CK(clk), .RN(n5629), .Q(n5931) );
DFFSX1TS R_374 ( .D(n5610), .CK(clk), .SN(n5682), .Q(n6060) );
DFFRX1TS R_908 ( .D(Raw_mant_NRM_SWR[37]), .CK(clk), .RN(n5652), .Q(n5729)
);
DFFRHQX1TS SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1285), .CK(clk), .RN(n6259),
.Q(DmP_mant_SHT1_SW[12]) );
DFFRX4TS EXP_STAGE_DmP_Q_reg_20_ ( .D(n1270), .CK(clk), .RN(n6259), .Q(
DmP_EXP_EWSW[20]) );
DFFRXLTS R_661 ( .D(n6201), .CK(clk), .RN(n6259), .Q(n5871) );
DFFRXLTS R_904 ( .D(n6437), .CK(clk), .RN(n6259), .Q(n5732) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_11_ ( .D(n1288), .CK(clk), .RN(n6256), .Q(
n1864) );
DFFSX2TS R_142 ( .D(n6404), .CK(clk), .SN(n5625), .Q(n6170) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_16_ ( .D(n1571), .CK(clk), .RN(n6242), .Q(
DMP_EXP_EWSW[16]) );
DFFRHQX2TS NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1126), .CK(clk), .RN(n5633),
.Q(n1856) );
DFFRXLTS EXP_STAGE_DmP_Q_reg_48_ ( .D(n1214), .CK(clk), .RN(n6260), .Q(
DmP_EXP_EWSW[48]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_4_ ( .D(n1583), .CK(clk), .RN(n6266), .Q(
DMP_EXP_EWSW[4]) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_22_ ( .D(n1565), .CK(clk), .RN(n6244), .Q(
DMP_EXP_EWSW[22]) );
DFFSX2TS R_879 ( .D(n2287), .CK(clk), .SN(n5671), .QN(n1844) );
DFFRHQX2TS SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1051), .CK(clk), .RN(n6237),
.Q(n1840) );
DFFRX4TS EXP_STAGE_DMP_Q_reg_14_ ( .D(n1573), .CK(clk), .RN(n6241), .Q(
DMP_EXP_EWSW[14]) );
DFFSX4TS R_696 ( .D(n2501), .CK(clk), .SN(n5642), .Q(n5851) );
DFFRX4TS R_595 ( .D(n6323), .CK(clk), .RN(n5624), .Q(n5916) );
DFFSX4TS R_857 ( .D(n2015), .CK(clk), .SN(n6240), .Q(n5758) );
DFFSX4TS R_929 ( .D(n6200), .CK(clk), .SN(n5669), .Q(n5714) );
DFFRHQX4TS SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1275), .CK(clk), .RN(n2541),
.Q(DmP_mant_SHT1_SW[17]) );
DFFRHQX2TS EXP_STAGE_DmP_Q_reg_14_ ( .D(n1282), .CK(clk), .RN(n2545), .Q(
n2313) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_2_ ( .D(n1585), .CK(clk), .RN(n2540), .Q(
n2276) );
DFFRX4TS R_930 ( .D(DmP_mant_SHT1_SW[39]), .CK(clk), .RN(n5669), .Q(n5713)
);
DFFRX4TS SGF_STAGE_DMP_Q_reg_16_ ( .D(n1471), .CK(clk), .RN(n6241), .QN(
n5478) );
DFFRHQX8TS SHT2_STAGE_SHFTVARS1_Q_reg_5_ ( .D(n1605), .CK(clk), .RN(n6269),
.Q(n2330) );
DFFSX4TS R_1072 ( .D(n5438), .CK(clk), .SN(n5666), .Q(n2174) );
DFFSX2TS R_328 ( .D(n6361), .CK(clk), .SN(n5647), .Q(n6092) );
DFFSX4TS R_509 ( .D(n2287), .CK(clk), .SN(n5629), .Q(n5964) );
DFFSX2TS R_327 ( .D(n6362), .CK(clk), .SN(n5647), .Q(n6093) );
DFFSX4TS R_887 ( .D(n2287), .CK(clk), .SN(n5679), .Q(n5741) );
DFFSX4TS R_856 ( .D(n6213), .CK(clk), .SN(n2514), .Q(n5759) );
DFFRHQX4TS R_984 ( .D(n6147), .CK(clk), .RN(n2515), .Q(n1839) );
DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n2539),
.Q(n2295) );
DFFRHQX4TS INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n6262),
.Q(n2310) );
DFFSX2TS R_860 ( .D(n6204), .CK(clk), .SN(n5632), .Q(n5756) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_42_ ( .D(n1028), .CK(clk), .RN(n6239), .Q(
DmP_mant_SFG_SWR[42]), .QN(n5560) );
DFFRX2TS R_848 ( .D(Raw_mant_NRM_SWR[16]), .CK(clk), .RN(n5676), .Q(n5764)
);
DFFRX2TS R_823 ( .D(DmP_mant_SHT1_SW[37]), .CK(clk), .RN(n5660), .Q(n5779)
);
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1316), .CK(clk), .RN(n2569), .Q(
DMP_exp_NRM2_EW[9]) );
DFFSX2TS R_933 ( .D(n6200), .CK(clk), .SN(n5680), .Q(n5711) );
DFFSX2TS R_683 ( .D(n2508), .CK(clk), .SN(n6234), .Q(n5856) );
DFFSX2TS R_379 ( .D(n6222), .CK(clk), .SN(n5669), .Q(n6056) );
DFFSX2TS R_472 ( .D(n5581), .CK(clk), .SN(n5682), .Q(n5989) );
DFFSX2TS R_474 ( .D(n5588), .CK(clk), .SN(n5682), .Q(n5987) );
DFFSX1TS R_617 ( .D(n6227), .CK(clk), .SN(n5682), .Q(n5899) );
DFFSX1TS R_854 ( .D(n2508), .CK(clk), .SN(n2521), .Q(n5760) );
DFFSX1TS R_833 ( .D(n2508), .CK(clk), .SN(n5681), .Q(n5772) );
DFFSX2TS R_899 ( .D(n2506), .CK(clk), .SN(n5684), .Q(n5734) );
DFFSX1TS R_770 ( .D(n6227), .CK(clk), .SN(n6236), .Q(n5806) );
DFFRX2TS R_912 ( .D(DmP_mant_SHT1_SW[51]), .CK(clk), .RN(n5644), .Q(n5726)
);
DFFRX2TS R_712 ( .D(Raw_mant_NRM_SWR[36]), .CK(clk), .RN(n5651), .Q(n5840)
);
DFFSX1TS R_666 ( .D(n2556), .CK(clk), .SN(n5642), .Q(n5866) );
DFFSX2TS R_609 ( .D(n6227), .CK(clk), .SN(n5679), .Q(n5903) );
DFFSX1TS R_943 ( .D(n2508), .CK(clk), .SN(n5678), .Q(n5707) );
DFFSX2TS R_551 ( .D(n6201), .CK(clk), .SN(n5626), .Q(n5944) );
DFFSX2TS R_1091 ( .D(n5569), .CK(clk), .SN(n2542), .Q(n2154), .QN(n1843) );
DFFRX2TS R_880 ( .D(Raw_mant_NRM_SWR[30]), .CK(clk), .RN(n5644), .QN(n1845)
);
DFFRX2TS R_514 ( .D(n2037), .CK(clk), .RN(n5645), .Q(n5960) );
DFFRX2TS R_830 ( .D(n1825), .CK(clk), .RN(n5663), .Q(n5774) );
DFFRX2TS R_747 ( .D(n1986), .CK(clk), .RN(n5634), .Q(n5818) );
DFFSX2TS R_356 ( .D(n5614), .CK(clk), .SN(n5684), .Q(n6072) );
DFFSX2TS R_721 ( .D(n6227), .CK(clk), .SN(n5642), .Q(n5834) );
DFFSX2TS R_675 ( .D(n6227), .CK(clk), .SN(n5650), .Q(n5860) );
DFFSX1TS R_681 ( .D(n2523), .CK(clk), .SN(n5682), .Q(n5857) );
DFFSX1TS R_545 ( .D(n2508), .CK(clk), .SN(n2568), .Q(n5948) );
DFFSX1TS R_581 ( .D(n6201), .CK(clk), .SN(n5674), .Q(n5929) );
DFFRX2TS SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1311), .CK(clk), .RN(n6255),
.Q(DMP_exp_NRM2_EW[10]) );
DFFRX2TS R_1043 ( .D(DmP_mant_SHT1_SW[15]), .CK(clk), .RN(n5637), .Q(n2207)
);
DFFSX1TS R_286 ( .D(n6407), .CK(clk), .SN(n2512), .Q(n6121) );
DFFSX1TS R_812 ( .D(n2497), .CK(clk), .SN(n5636), .Q(n5785) );
DFFRX2TS SGF_STAGE_DmP_mant_Q_reg_54_ ( .D(n1016), .CK(clk), .RN(n2511), .Q(
DmP_mant_SFG_SWR[54]) );
DFFRHQX2TS EXP_STAGE_DMP_Q_reg_60_ ( .D(n1527), .CK(clk), .RN(n6465), .Q(
n2303) );
DFFRX2TS SHT1_STAGE_DmP_mant_Q_reg_42_ ( .D(n1225), .CK(clk), .RN(n6465),
.Q(DmP_mant_SHT1_SW[42]), .QN(n5415) );
NOR2BX1TS U1842 ( .AN(n2018), .B(n2990), .Y(n2509) );
INVX2TS U1843 ( .A(n3261), .Y(n1915) );
OAI2BB1X1TS U1844 ( .A0N(n5149), .A1N(n6441), .B0(n5148), .Y(n1036) );
NAND2X6TS U1845 ( .A(n2925), .B(Raw_mant_NRM_SWR[18]), .Y(n6320) );
NAND2X1TS U1846 ( .A(n6204), .B(DmP_mant_SHT1_SW[3]), .Y(n6394) );
BUFX8TS U1847 ( .A(n5032), .Y(n6223) );
NAND2X1TS U1848 ( .A(n3124), .B(intDY_EWSW[38]), .Y(n3617) );
INVX8TS U1849 ( .A(n1906), .Y(n2556) );
CLKINVX2TS U1850 ( .A(n1879), .Y(n1882) );
CLKINVX2TS U1851 ( .A(n1879), .Y(n1881) );
OAI21X2TS U1852 ( .A0(n4617), .A1(n5216), .B0(n1826), .Y(n1021) );
NAND2X6TS U1853 ( .A(n2495), .B(Raw_mant_NRM_SWR[1]), .Y(n6333) );
NAND2X2TS U1854 ( .A(n4863), .B(intDX_EWSW[34]), .Y(n3598) );
MXI2X2TS U1855 ( .A(n5290), .B(n5558), .S0(n1868), .Y(n1020) );
CLKMX2X3TS U1856 ( .A(Data_Y[38]), .B(intDY_EWSW[38]), .S0(n5235), .Y(n1690)
);
BUFX12TS U1857 ( .A(n2925), .Y(n1823) );
AND2X2TS U1858 ( .A(n3261), .B(n2012), .Y(n2441) );
NAND2X4TS U1859 ( .A(n2984), .B(n5127), .Y(n1016) );
CLKINVX2TS U1860 ( .A(n1879), .Y(n1880) );
MXI2X1TS U1861 ( .A(n5251), .B(n5250), .S0(n2554), .Y(n1105) );
NAND3X2TS U1862 ( .A(n3660), .B(n3661), .C(n3659), .Y(n1525) );
NAND2X2TS U1863 ( .A(n4545), .B(n4544), .Y(n1052) );
NAND3X4TS U1864 ( .A(n4441), .B(n4442), .C(n4440), .Y(n1575) );
NAND3X4TS U1865 ( .A(n4399), .B(n4398), .C(n4397), .Y(n1536) );
MXI2X1TS U1866 ( .A(n2989), .B(n4303), .S0(n2505), .Y(n1134) );
NAND3X2TS U1867 ( .A(n4402), .B(n4401), .C(n4400), .Y(n1582) );
NAND3X2TS U1868 ( .A(n3817), .B(n3818), .C(n3816), .Y(n1288) );
INVX12TS U1869 ( .A(n3261), .Y(n6213) );
NAND2X2TS U1870 ( .A(n2531), .B(n2295), .Y(n4402) );
NAND2X2TS U1871 ( .A(n4807), .B(n2026), .Y(n3690) );
NAND2X2TS U1872 ( .A(n2049), .B(intDX_EWSW[53]), .Y(n4367) );
NAND2X2TS U1873 ( .A(n6449), .B(n5123), .Y(n4508) );
NAND2X2TS U1874 ( .A(n4863), .B(intDX_EWSW[12]), .Y(n4441) );
NAND2X1TS U1875 ( .A(n1836), .B(intDX_EWSW[11]), .Y(n3818) );
CLKINVX2TS U1876 ( .A(n2527), .Y(n1873) );
OR2X6TS U1877 ( .A(n3266), .B(n2439), .Y(n3285) );
NAND2X1TS U1878 ( .A(n6443), .B(n4543), .Y(n4481) );
INVX4TS U1879 ( .A(n4332), .Y(n5041) );
AND2X6TS U1880 ( .A(n2500), .B(DmP_mant_SHT1_SW[28]), .Y(n2428) );
NAND2X1TS U1881 ( .A(n1838), .B(intDY_EWSW[19]), .Y(n3682) );
BUFX4TS U1882 ( .A(Shift_reg_FLAGS_7[0]), .Y(n5292) );
NAND2X4TS U1883 ( .A(n2648), .B(n2986), .Y(n6412) );
NAND3X1TS U1884 ( .A(n2240), .B(n2239), .C(n2238), .Y(n1553) );
NAND3X1TS U1885 ( .A(n2243), .B(n2242), .C(n2241), .Y(n1549) );
NAND3X1TS U1886 ( .A(n2237), .B(n2236), .C(n2235), .Y(n1537) );
NAND3X1TS U1887 ( .A(n2249), .B(n2248), .C(n2247), .Y(n1216) );
NAND2X2TS U1888 ( .A(n2053), .B(intDY_EWSW[11]), .Y(n3817) );
NAND2X2TS U1889 ( .A(n4424), .B(n2046), .Y(n4423) );
NAND2X2TS U1890 ( .A(n2530), .B(n1923), .Y(n4442) );
NAND2X2TS U1891 ( .A(n4425), .B(intDX_EWSW[62]), .Y(n3660) );
BUFX3TS U1892 ( .A(Shift_reg_FLAGS_7[0]), .Y(n5287) );
NAND2X6TS U1893 ( .A(n2452), .B(intDX_EWSW[17]), .Y(n3669) );
NAND2X1TS U1894 ( .A(n5264), .B(DmP_mant_SFG_SWR[23]), .Y(n3063) );
NAND2XLTS U1895 ( .A(n5319), .B(n1913), .Y(n3186) );
NAND2XLTS U1896 ( .A(n5205), .B(n5428), .Y(n2907) );
NAND2XLTS U1897 ( .A(n5319), .B(Raw_mant_NRM_SWR[36]), .Y(n2903) );
NAND2X1TS U1898 ( .A(n4396), .B(DMP_EXP_EWSW[48]), .Y(n4389) );
NAND2X6TS U1899 ( .A(n2964), .B(n2049), .Y(n4809) );
INVX6TS U1900 ( .A(n1817), .Y(n1816) );
NAND2XLTS U1901 ( .A(n4853), .B(DmP_EXP_EWSW[23]), .Y(n4828) );
NAND2XLTS U1902 ( .A(n5216), .B(n3136), .Y(n3135) );
NAND2XLTS U1903 ( .A(n5245), .B(DmP_mant_SFG_SWR[8]), .Y(n3109) );
NAND2XLTS U1904 ( .A(n2554), .B(n2450), .Y(n2953) );
NAND2X1TS U1905 ( .A(n5005), .B(Raw_mant_NRM_SWR[51]), .Y(n2718) );
NOR2X6TS U1906 ( .A(n1937), .B(n1935), .Y(n3320) );
NAND2XLTS U1907 ( .A(n4864), .B(DmP_EXP_EWSW[6]), .Y(n4111) );
NAND2XLTS U1908 ( .A(n4396), .B(DMP_EXP_EWSW[41]), .Y(n3600) );
NAND2XLTS U1909 ( .A(n4396), .B(DMP_EXP_EWSW[44]), .Y(n3609) );
NAND2XLTS U1910 ( .A(n4864), .B(DmP_EXP_EWSW[5]), .Y(n4865) );
NAND2XLTS U1911 ( .A(n4864), .B(DmP_EXP_EWSW[3]), .Y(n4403) );
MX2X2TS U1912 ( .A(n6460), .B(n5561), .S0(n5224), .Y(n5142) );
NAND2X2TS U1913 ( .A(n2116), .B(n2745), .Y(n4824) );
NAND2X4TS U1914 ( .A(n2649), .B(n2669), .Y(n2668) );
BUFX3TS U1915 ( .A(n6289), .Y(n6259) );
NAND2XLTS U1916 ( .A(n2534), .B(n2313), .Y(n4307) );
AND2X4TS U1917 ( .A(n4416), .B(n2045), .Y(n2265) );
NAND2X2TS U1918 ( .A(n4430), .B(intDY_EWSW[7]), .Y(n4076) );
NAND2X4TS U1919 ( .A(n2951), .B(intDY_EWSW[48]), .Y(n4104) );
NAND2XLTS U1920 ( .A(n5005), .B(n5029), .Y(n3277) );
NAND2XLTS U1921 ( .A(n5005), .B(n2037), .Y(n3203) );
NAND2XLTS U1922 ( .A(n2012), .B(n2551), .Y(n3279) );
NAND2X2TS U1923 ( .A(n4369), .B(intDX_EWSW[40]), .Y(n3592) );
NAND2XLTS U1924 ( .A(n2535), .B(n2276), .Y(n4878) );
INVX1TS U1925 ( .A(Raw_mant_NRM_SWR[41]), .Y(n2327) );
NAND2X2TS U1926 ( .A(n2731), .B(n2730), .Y(n2729) );
MX2X4TS U1927 ( .A(n6416), .B(n5131), .S0(n2505), .Y(n5132) );
NAND2X4TS U1928 ( .A(n5124), .B(n5123), .Y(n2984) );
OR2X2TS U1929 ( .A(n3231), .B(n3877), .Y(n3228) );
NAND2X2TS U1930 ( .A(n3587), .B(intDX_EWSW[20]), .Y(n4848) );
NAND2X2TS U1931 ( .A(n4807), .B(intDX_EWSW[61]), .Y(n3678) );
MX2X4TS U1932 ( .A(n6435), .B(n5563), .S0(n5159), .Y(n5152) );
NAND3X4TS U1933 ( .A(n2677), .B(n2402), .C(n3178), .Y(n3176) );
NAND2X2TS U1934 ( .A(n2725), .B(n2735), .Y(n2724) );
NAND2BXLTS U1935 ( .AN(n2546), .B(n2571), .Y(n2776) );
OR2X2TS U1936 ( .A(n2835), .B(n2444), .Y(n2369) );
OA21X1TS U1937 ( .A0(n2382), .A1(n2373), .B0(n3208), .Y(n2671) );
NAND2X2TS U1938 ( .A(n5163), .B(n3119), .Y(n4587) );
NAND2X1TS U1939 ( .A(n5227), .B(n2021), .Y(n2020) );
NAND2X2TS U1940 ( .A(n3181), .B(n3178), .Y(n3177) );
NAND2XLTS U1941 ( .A(n5227), .B(n2451), .Y(n2841) );
NAND2X2TS U1942 ( .A(n6455), .B(n5149), .Y(n2828) );
INVX2TS U1943 ( .A(n6249), .Y(n1879) );
NAND3X2TS U1944 ( .A(n2835), .B(n2836), .C(n2834), .Y(n2830) );
NAND2X2TS U1945 ( .A(n2876), .B(n2875), .Y(n2874) );
NAND2XLTS U1946 ( .A(n5216), .B(n1827), .Y(n1826) );
BUFX6TS U1947 ( .A(n4791), .Y(n4853) );
BUFX6TS U1948 ( .A(n4791), .Y(n4426) );
OR2X6TS U1949 ( .A(n2502), .B(n2560), .Y(n2710) );
INVX2TS U1950 ( .A(n1875), .Y(n1878) );
BUFX16TS U1951 ( .A(n3125), .Y(n2526) );
INVX2TS U1952 ( .A(n2733), .Y(n2725) );
NAND2X1TS U1953 ( .A(n3921), .B(n3232), .Y(n2382) );
CLKBUFX2TS U1954 ( .A(Raw_mant_NRM_SWR[49]), .Y(n2012) );
INVX2TS U1955 ( .A(n6465), .Y(n2537) );
CLKBUFX2TS U1956 ( .A(Shift_amount_SHT1_EWR[4]), .Y(n2571) );
NAND2X4TS U1957 ( .A(n1963), .B(n1959), .Y(n6449) );
BUFX4TS U1958 ( .A(n5123), .Y(n5149) );
NAND2XLTS U1959 ( .A(n4737), .B(n4746), .Y(n4738) );
INVX4TS U1960 ( .A(n6293), .Y(n5277) );
NAND2X1TS U1961 ( .A(n5030), .B(n4722), .Y(n4725) );
NAND2X1TS U1962 ( .A(n4712), .B(n4711), .Y(n4713) );
NAND2X1TS U1963 ( .A(n2757), .B(n2738), .Y(n5098) );
NAND2X1TS U1964 ( .A(n4723), .B(n1635), .Y(n4687) );
NAND2XLTS U1965 ( .A(n5328), .B(n2673), .Y(n5329) );
INVX4TS U1966 ( .A(n5315), .Y(n2525) );
OAI2BB1X2TS U1967 ( .A0N(n5141), .A1N(n3062), .B0(n4605), .Y(n1831) );
NAND2X1TS U1968 ( .A(n5150), .B(n4685), .Y(n4501) );
CLKBUFX2TS U1969 ( .A(intDY_EWSW[18]), .Y(n2025) );
CLKBUFX2TS U1970 ( .A(intDY_EWSW[3]), .Y(n2737) );
NAND2XLTS U1971 ( .A(n4995), .B(n4994), .Y(n2359) );
INVX4TS U1972 ( .A(n2342), .Y(n2284) );
CLKAND2X2TS U1973 ( .A(n3275), .B(n4779), .Y(n2360) );
NAND2XLTS U1974 ( .A(n4928), .B(n4927), .Y(n2358) );
AND2X2TS U1975 ( .A(n3407), .B(n3406), .Y(n1841) );
NAND2X4TS U1976 ( .A(n4614), .B(n4613), .Y(n4615) );
NAND2X2TS U1977 ( .A(n3892), .B(n2735), .Y(n2728) );
CLKBUFX2TS U1978 ( .A(n5685), .Y(n6249) );
NAND2XLTS U1979 ( .A(n3016), .B(n4949), .Y(n4950) );
NAND2XLTS U1980 ( .A(n5086), .B(n5085), .Y(n5087) );
INVX2TS U1981 ( .A(n5294), .Y(n5299) );
NOR2X1TS U1982 ( .A(n3918), .B(n2550), .Y(n3173) );
CLKAND2X2TS U1983 ( .A(n3918), .B(n3179), .Y(n3178) );
NOR2X4TS U1984 ( .A(n2836), .B(n2444), .Y(n2833) );
INVX2TS U1985 ( .A(n4332), .Y(n6230) );
CLKAND2X2TS U1986 ( .A(n5324), .B(n5323), .Y(n2355) );
NOR2X6TS U1987 ( .A(n3085), .B(n1828), .Y(n2591) );
INVX6TS U1988 ( .A(n2883), .Y(n2876) );
CLKAND2X2TS U1989 ( .A(n4909), .B(n2373), .Y(n2352) );
NAND2XLTS U1990 ( .A(n3374), .B(n4241), .Y(n2434) );
NAND2X2TS U1991 ( .A(n4243), .B(n3374), .Y(n2835) );
CLKBUFX2TS U1992 ( .A(intDY_EWSW[42]), .Y(n1815) );
CLKAND2X2TS U1993 ( .A(n4974), .B(n4975), .Y(n2361) );
NAND2X4TS U1994 ( .A(n2988), .B(n3784), .Y(n2968) );
CLKBUFX2TS U1995 ( .A(intDY_EWSW[41]), .Y(n2026) );
NOR2X1TS U1996 ( .A(n3921), .B(n2670), .Y(n2669) );
NOR2X2TS U1997 ( .A(n4498), .B(n4497), .Y(n4504) );
NOR3X1TS U1998 ( .A(n4242), .B(n4244), .C(n5205), .Y(n2834) );
NOR2X1TS U1999 ( .A(n4689), .B(n4678), .Y(n4680) );
CLKAND2X2TS U2000 ( .A(n4771), .B(n4767), .Y(n2365) );
NAND2X2TS U2001 ( .A(n2880), .B(n2881), .Y(n2381) );
CLKINVX1TS U2002 ( .A(intDY_EWSW[40]), .Y(n1818) );
NAND2X2TS U2003 ( .A(n2400), .B(n3043), .Y(n3042) );
BUFX3TS U2004 ( .A(n4917), .Y(n5005) );
BUFX3TS U2005 ( .A(n5259), .Y(n5218) );
NAND2X6TS U2006 ( .A(n4079), .B(n4077), .Y(n1817) );
OAI22X2TS U2007 ( .A0(n4718), .A1(n4643), .B0(n4716), .B1(n4642), .Y(n4648)
);
NAND2X2TS U2008 ( .A(n3031), .B(n5297), .Y(n3030) );
INVX2TS U2009 ( .A(n5549), .Y(n1827) );
CLKINVX1TS U2010 ( .A(n5006), .Y(n4070) );
NAND2X1TS U2011 ( .A(n5075), .B(n5073), .Y(n4735) );
NOR2X2TS U2012 ( .A(n4677), .B(n4679), .Y(n2590) );
CLKAND2X2TS U2013 ( .A(n1914), .B(n4749), .Y(n2366) );
OAI21X1TS U2014 ( .A0(n2444), .A1(n4241), .B0(n3278), .Y(n2832) );
BUFX3TS U2015 ( .A(n2317), .Y(n2325) );
INVX2TS U2016 ( .A(n5327), .Y(n5328) );
BUFX6TS U2017 ( .A(n2764), .Y(n5125) );
NAND2X1TS U2018 ( .A(n2389), .B(n3920), .Y(n3921) );
NAND2XLTS U2019 ( .A(n2373), .B(n3179), .Y(n2670) );
NAND2X2TS U2020 ( .A(n5154), .B(n4711), .Y(n4541) );
NAND2X1TS U2021 ( .A(n4722), .B(n5036), .Y(n2816) );
BUFX16TS U2022 ( .A(n2334), .Y(n2362) );
AND2X2TS U2023 ( .A(n3910), .B(n3912), .Y(n2402) );
NAND2X1TS U2024 ( .A(n5488), .B(DMP_EXP_EWSW[56]), .Y(n5306) );
NAND2X1TS U2025 ( .A(n4618), .B(n2516), .Y(n4609) );
NAND2X4TS U2026 ( .A(n3246), .B(n2677), .Y(n2836) );
INVX2TS U2027 ( .A(n4952), .Y(n4954) );
NAND2X1TS U2028 ( .A(n5143), .B(n2518), .Y(n4607) );
OAI22X1TS U2029 ( .A0(n6411), .A1(n4709), .B0(n4718), .B1(n4684), .Y(n2639)
);
NAND2X2TS U2030 ( .A(n5138), .B(n2519), .Y(n3067) );
AND4X4TS U2031 ( .A(n2894), .B(n4344), .C(n2753), .D(n2893), .Y(n2377) );
NOR2X1TS U2032 ( .A(n2611), .B(n4674), .Y(n4677) );
NAND2X2TS U2033 ( .A(n4686), .B(n2517), .Y(n3104) );
CLKINVX1TS U2034 ( .A(n5073), .Y(n5074) );
NAND2X6TS U2035 ( .A(n3242), .B(n3237), .Y(n3239) );
BUFX3TS U2036 ( .A(n4917), .Y(n5205) );
INVX2TS U2037 ( .A(n4977), .Y(n4964) );
INVX2TS U2038 ( .A(n4980), .Y(n4963) );
NAND2XLTS U2039 ( .A(n5232), .B(DmP_mant_SFG_SWR[10]), .Y(n2886) );
CLKINVX6TS U2040 ( .A(n3091), .Y(n2765) );
NAND2X4TS U2041 ( .A(n3172), .B(n4135), .Y(n3171) );
INVX2TS U2042 ( .A(n3913), .Y(n3268) );
CLKINVX3TS U2043 ( .A(n4243), .Y(n3211) );
NOR2X1TS U2044 ( .A(n4021), .B(n2663), .Y(n2662) );
NOR2X6TS U2045 ( .A(n3081), .B(n2778), .Y(n5309) );
INVX1TS U2046 ( .A(n4240), .Y(n3908) );
NAND2X2TS U2047 ( .A(n3232), .B(n4244), .Y(n2444) );
INVX2TS U2048 ( .A(n4943), .Y(n2120) );
NAND2X1TS U2049 ( .A(n5294), .B(n3032), .Y(n3031) );
OR2X2TS U2050 ( .A(n4493), .B(n4492), .Y(n2503) );
NOR2X2TS U2051 ( .A(n2552), .B(n6411), .Y(n4679) );
INVX4TS U2052 ( .A(n2549), .Y(n2550) );
CLKAND2X4TS U2053 ( .A(n4890), .B(n2429), .Y(n2272) );
NAND2X2TS U2054 ( .A(n2419), .B(n2522), .Y(n2880) );
NAND2X2TS U2055 ( .A(n5139), .B(n5147), .Y(n3161) );
OR2X4TS U2056 ( .A(n2330), .B(n2560), .Y(n4477) );
CLKINVX3TS U2057 ( .A(n3281), .Y(n2755) );
NAND2X2TS U2058 ( .A(n1872), .B(n4089), .Y(n2960) );
INVX2TS U2059 ( .A(n4734), .Y(n5075) );
BUFX6TS U2060 ( .A(n4543), .Y(n5161) );
NAND2BX2TS U2061 ( .AN(n4673), .B(n3086), .Y(n3085) );
AOI21X1TS U2062 ( .A0(DmP_mant_SHT1_SW[51]), .A1(n2384), .B0(n5019), .Y(
n4435) );
NAND2X2TS U2063 ( .A(n4649), .B(n5145), .Y(n4650) );
INVX4TS U2064 ( .A(n4683), .Y(n1828) );
NAND2BX2TS U2065 ( .AN(n3160), .B(n4692), .Y(n3159) );
NAND2X1TS U2066 ( .A(n4708), .B(n4656), .Y(n2089) );
CLKAND2X2TS U2067 ( .A(n4909), .B(n2389), .Y(n2339) );
NAND2X2TS U2068 ( .A(n5140), .B(n2519), .Y(n3105) );
NAND2X2TS U2069 ( .A(n2022), .B(n2519), .Y(n4625) );
NAND2X2TS U2070 ( .A(n4645), .B(n4685), .Y(n2100) );
NAND2X2TS U2071 ( .A(n4721), .B(n5145), .Y(n1939) );
NAND2X2TS U2072 ( .A(n4977), .B(n1921), .Y(n4982) );
AND2X4TS U2073 ( .A(n3896), .B(n3232), .Y(n2735) );
NAND3BX2TS U2074 ( .AN(n4894), .B(n4887), .C(n4902), .Y(n2075) );
NAND2BX2TS U2075 ( .AN(n2393), .B(n4692), .Y(n3066) );
NAND2X2TS U2076 ( .A(n4987), .B(n4923), .Y(n4925) );
NOR2X2TS U2077 ( .A(n4669), .B(n2560), .Y(n5274) );
AOI21X2TS U2078 ( .A0(n3281), .A1(n5000), .B0(n4999), .Y(n5001) );
NOR2X2TS U2079 ( .A(n3887), .B(n2665), .Y(n2664) );
OAI21X1TS U2080 ( .A0(n4756), .A1(n4755), .B0(n4754), .Y(n4757) );
NAND2X4TS U2081 ( .A(n4971), .B(n4987), .Y(n4973) );
NOR2X4TS U2082 ( .A(n4537), .B(n4536), .Y(n4539) );
CLKINVX2TS U2083 ( .A(n4769), .Y(n4765) );
NOR2X1TS U2084 ( .A(n4702), .B(n5058), .Y(n3802) );
CLKBUFX2TS U2085 ( .A(n2405), .Y(n2757) );
CLKBUFX2TS U2086 ( .A(n4338), .Y(n2753) );
NAND2X1TS U2087 ( .A(n4722), .B(n5017), .Y(n4695) );
INVX2TS U2088 ( .A(n3919), .Y(n4909) );
CLKBUFX2TS U2089 ( .A(DmP_mant_SHT1_SW[4]), .Y(n2548) );
NOR2X4TS U2090 ( .A(n4958), .B(n4914), .Y(n4943) );
NAND2X1TS U2091 ( .A(n4722), .B(n4331), .Y(n4127) );
BUFX6TS U2092 ( .A(n3365), .Y(n5147) );
NAND2X2TS U2093 ( .A(n5139), .B(n2517), .Y(n3146) );
INVX2TS U2094 ( .A(n4918), .Y(n4923) );
NAND2X2TS U2095 ( .A(n4682), .B(n4681), .Y(n4683) );
CLKXOR2X2TS U2096 ( .A(n2257), .B(DmP_mant_SFG_SWR[54]), .Y(n4244) );
NOR2X6TS U2097 ( .A(n4958), .B(n4961), .Y(n4977) );
NAND2X2TS U2098 ( .A(n3913), .B(n3912), .Y(n2785) );
INVX2TS U2099 ( .A(n1875), .Y(n1877) );
AOI2BB2X1TS U2100 ( .B0(Raw_mant_NRM_SWR[32]), .B1(n4343), .A0N(n3248),
.A1N(n5492), .Y(n4344) );
INVX8TS U2101 ( .A(n2393), .Y(n2516) );
NOR2BX2TS U2102 ( .AN(n1856), .B(n2474), .Y(n3199) );
NAND2X1TS U2103 ( .A(n3880), .B(n3232), .Y(n3231) );
NOR2X1TS U2104 ( .A(n4706), .B(n4668), .Y(n3799) );
CLKAND2X2TS U2105 ( .A(n4240), .B(n3374), .Y(n3246) );
OAI22X2TS U2106 ( .A0(n6411), .A1(n1874), .B0(n4702), .B1(n4684), .Y(n1960)
);
INVX4TS U2107 ( .A(n4286), .Y(n1832) );
NOR2X2TS U2108 ( .A(n4709), .B(n4710), .Y(n4532) );
BUFX3TS U2109 ( .A(n4917), .Y(n5089) );
NAND2X2TS U2110 ( .A(n3909), .B(DMP_SFG[51]), .Y(n4241) );
NOR2X1TS U2111 ( .A(n4689), .B(n4653), .Y(n4596) );
NOR2X4TS U2112 ( .A(n4968), .B(n4993), .Y(n4971) );
NAND2X2TS U2113 ( .A(n5086), .B(n3295), .Y(n4755) );
OAI22X2TS U2114 ( .A0(n2611), .A1(n4490), .B0(n4716), .B1(n4489), .Y(n4493)
);
NOR2X2TS U2115 ( .A(n4669), .B(n4325), .Y(n4326) );
CLKAND2X2TS U2116 ( .A(n5061), .B(n5019), .Y(n2427) );
OAI22X2TS U2117 ( .A0(n4665), .A1(n4702), .B0(n4666), .B1(n4718), .Y(n3115)
);
NAND2X2TS U2118 ( .A(n4135), .B(n3283), .Y(n2473) );
NAND2X2TS U2119 ( .A(n3240), .B(n4350), .Y(n2893) );
NAND2X1TS U2120 ( .A(n3019), .B(n3018), .Y(n2900) );
OAI21X1TS U2121 ( .A0(n5297), .A1(n5300), .B0(n5301), .Y(n3081) );
INVX2TS U2122 ( .A(n1875), .Y(n1876) );
AOI21X1TS U2123 ( .A0(n1920), .A1(n3295), .B0(n4753), .Y(n4754) );
INVX4TS U2124 ( .A(n4620), .Y(n5050) );
NAND2X1TS U2125 ( .A(n3262), .B(n2751), .Y(n4898) );
CLKINVX6TS U2126 ( .A(n4657), .Y(n5058) );
NAND2X1TS U2127 ( .A(n2723), .B(DMP_SFG[26]), .Y(n4767) );
AND2X6TS U2128 ( .A(n2560), .B(n1951), .Y(n3062) );
INVX2TS U2129 ( .A(n4751), .Y(n5086) );
NAND2X1TS U2130 ( .A(n3354), .B(DMP_EXP_EWSW[55]), .Y(n5301) );
INVX2TS U2131 ( .A(n4989), .Y(n4968) );
BUFX4TS U2132 ( .A(n4920), .Y(n2930) );
INVX2TS U2133 ( .A(n3898), .Y(n3912) );
INVX4TS U2134 ( .A(n5022), .Y(n4710) );
INVX6TS U2135 ( .A(n2080), .Y(n5138) );
CLKINVX6TS U2136 ( .A(n5013), .Y(n4653) );
INVX3TS U2137 ( .A(n5028), .Y(n4325) );
INVX4TS U2138 ( .A(n4523), .Y(n5049) );
NAND2X1TS U2139 ( .A(n4708), .B(n5038), .Y(n2630) );
INVX2TS U2140 ( .A(n4342), .Y(n3019) );
INVX2TS U2141 ( .A(n3897), .Y(n4136) );
INVX4TS U2142 ( .A(n1626), .Y(n4717) );
NAND2X4TS U2143 ( .A(n3275), .B(n4959), .Y(n4961) );
NAND2X6TS U2144 ( .A(n3147), .B(n4641), .Y(n5139) );
CLKINVX1TS U2145 ( .A(n4254), .Y(n4255) );
INVX3TS U2146 ( .A(n4333), .Y(n4489) );
NAND2X2TS U2147 ( .A(n3269), .B(n4020), .Y(n4021) );
NOR2X4TS U2148 ( .A(n4958), .B(n4783), .Y(n5322) );
NAND2X6TS U2149 ( .A(n4336), .B(n4252), .Y(n4266) );
NOR2X6TS U2150 ( .A(n2663), .B(n4019), .Y(n3910) );
OR2X2TS U2151 ( .A(n3909), .B(DMP_SFG[51]), .Y(n3374) );
NOR2BX1TS U2152 ( .AN(n2252), .B(n4341), .Y(n3018) );
AOI22X2TS U2153 ( .A0(n4659), .A1(n5037), .B0(n2780), .B1(n4322), .Y(n3857)
);
NAND2X2TS U2154 ( .A(n2529), .B(n5025), .Y(n4059) );
NAND2X2TS U2155 ( .A(n4658), .B(n4620), .Y(n4621) );
NAND2X4TS U2156 ( .A(n2780), .B(n5051), .Y(n4329) );
OR2X4TS U2157 ( .A(n4654), .B(n3858), .Y(n2103) );
NAND2X2TS U2158 ( .A(n2555), .B(n5033), .Y(n4624) );
OAI21X2TS U2159 ( .A0(n4351), .A1(n2037), .B0(n2897), .Y(n2896) );
INVX4TS U2160 ( .A(n4672), .Y(n5057) );
NAND2X6TS U2161 ( .A(n5140), .B(n4691), .Y(n2601) );
XNOR2X1TS U2162 ( .A(intDX_EWSW[1]), .B(n2310), .Y(n4152) );
NOR2BX2TS U2163 ( .AN(n2392), .B(n4893), .Y(n2899) );
NAND2X1TS U2164 ( .A(n4722), .B(n5020), .Y(n2703) );
XNOR2X1TS U2165 ( .A(intDX_EWSW[37]), .B(intDY_EWSW[37]), .Y(n4157) );
NAND2X2TS U2166 ( .A(n2262), .B(n5033), .Y(n4485) );
NOR2X6TS U2167 ( .A(n4702), .B(n4715), .Y(n2071) );
INVX2TS U2168 ( .A(n4785), .Y(n5324) );
NAND2X2TS U2169 ( .A(n4722), .B(n5013), .Y(n2104) );
INVX3TS U2170 ( .A(n3900), .Y(n4998) );
NOR2X2TS U2171 ( .A(n4517), .B(n4516), .Y(n4528) );
AND2X4TS U2172 ( .A(n4063), .B(n4066), .Y(n2941) );
XNOR2X2TS U2173 ( .A(n2028), .B(intDY_EWSW[39]), .Y(n4155) );
OR2X2TS U2174 ( .A(n4701), .B(n4662), .Y(n3060) );
XOR2X1TS U2175 ( .A(intDX_EWSW[55]), .B(n2475), .Y(n4211) );
CLKINVX1TS U2176 ( .A(n4685), .Y(n2079) );
XNOR2X1TS U2177 ( .A(intDX_EWSW[57]), .B(intDY_EWSW[57]), .Y(n4210) );
AND2X4TS U2178 ( .A(n4120), .B(n4122), .Y(n2578) );
NAND2X2TS U2179 ( .A(n3237), .B(n5006), .Y(n2854) );
NAND4X2TS U2180 ( .A(n4087), .B(n6150), .C(n6149), .D(n6148), .Y(n5015) );
NAND2X1TS U2181 ( .A(n4473), .B(n5014), .Y(n4084) );
INVX1TS U2182 ( .A(n4716), .Y(n2632) );
CLKINVX3TS U2183 ( .A(n5038), .Y(n4701) );
INVX6TS U2184 ( .A(n5035), .Y(n4715) );
NAND2X4TS U2185 ( .A(n2054), .B(n4247), .Y(n4891) );
NAND2X2TS U2186 ( .A(n5024), .B(n4658), .Y(n3972) );
CLKINVX6TS U2187 ( .A(n5021), .Y(n4643) );
BUFX4TS U2188 ( .A(n4910), .Y(n4911) );
NAND2X4TS U2189 ( .A(n4691), .B(n2529), .Y(n4706) );
NAND2X4TS U2190 ( .A(n4711), .B(n2560), .Y(n2393) );
NAND2X6TS U2191 ( .A(n4935), .B(n3275), .Y(n4936) );
NAND2X2TS U2192 ( .A(n1644), .B(n1919), .Y(n4064) );
BUFX16TS U2193 ( .A(n4669), .Y(n4702) );
INVX6TS U2194 ( .A(n4763), .Y(n4958) );
INVX6TS U2195 ( .A(n2952), .Y(n4962) );
INVX2TS U2196 ( .A(n4698), .Y(n2106) );
NOR2X6TS U2197 ( .A(n2077), .B(n5439), .Y(n4885) );
NOR2X4TS U2198 ( .A(Shift_amount_SHT1_EWR[0]), .B(n2562), .Y(n5006) );
OR2X2TS U2199 ( .A(n2646), .B(n2464), .Y(n4259) );
INVX6TS U2200 ( .A(n5262), .Y(n4696) );
NAND2X2TS U2201 ( .A(n1919), .B(n5037), .Y(n3093) );
INVX2TS U2202 ( .A(n4332), .Y(n6229) );
INVX2TS U2203 ( .A(n2855), .Y(n3237) );
CLKAND2X2TS U2204 ( .A(n5054), .B(n2262), .Y(n2398) );
INVX8TS U2205 ( .A(n1627), .Y(n4684) );
NAND2X2TS U2206 ( .A(n2555), .B(n1917), .Y(n4066) );
INVX2TS U2207 ( .A(n4019), .Y(n3269) );
INVX6TS U2208 ( .A(n5036), .Y(n4534) );
AND2X6TS U2209 ( .A(n3255), .B(n3254), .Y(n3222) );
AND2X6TS U2210 ( .A(n3024), .B(n3023), .Y(n4339) );
NAND2X4TS U2211 ( .A(n3888), .B(DMP_SFG[47]), .Y(n4135) );
OA22X2TS U2212 ( .A0(n2225), .A1(n2155), .B0(n2232), .B1(n2189), .Y(n3946)
);
NAND2X4TS U2213 ( .A(n4658), .B(n5033), .Y(n4080) );
INVX3TS U2214 ( .A(n4049), .Y(n4521) );
NOR2X4TS U2215 ( .A(n2902), .B(n3068), .Y(n4912) );
CLKINVX3TS U2216 ( .A(n5045), .Y(n1918) );
NAND2X2TS U2217 ( .A(n2529), .B(n1859), .Y(n4524) );
INVX8TS U2218 ( .A(n2076), .Y(n2077) );
BUFX16TS U2219 ( .A(n3833), .Y(n4716) );
NOR2BX2TS U2220 ( .AN(n4257), .B(n3745), .Y(n2646) );
OAI2BB2X2TS U2221 ( .B0(n2154), .B1(n2232), .A0N(n2223), .A1N(n2224), .Y(
n3703) );
NOR2X6TS U2222 ( .A(n3919), .B(n3873), .Y(n4018) );
NAND2X2TS U2223 ( .A(n3894), .B(DMP_SFG[50]), .Y(n3901) );
NAND2X2TS U2224 ( .A(n3890), .B(DMP_SFG[49]), .Y(n5003) );
NAND3X4TS U2225 ( .A(n2563), .B(n3023), .C(n3024), .Y(n3026) );
BUFX4TS U2226 ( .A(left_right_SHT2), .Y(n2560) );
BUFX3TS U2227 ( .A(n4781), .Y(n2759) );
CLKINVX6TS U2228 ( .A(n4689), .Y(n4488) );
AND2X4TS U2229 ( .A(n4593), .B(n4592), .Y(n2081) );
NAND2X2TS U2230 ( .A(n3241), .B(n5061), .Y(n2855) );
INVX4TS U2231 ( .A(n2551), .Y(n3287) );
INVX12TS U2232 ( .A(n4644), .Y(n1870) );
INVX6TS U2233 ( .A(n3781), .Y(n3188) );
BUFX6TS U2234 ( .A(n3804), .Y(n4659) );
AND2X6TS U2235 ( .A(n3401), .B(n4989), .Y(n2397) );
CLKAND2X2TS U2236 ( .A(n5819), .B(n5818), .Y(n3948) );
AND2X2TS U2237 ( .A(n5824), .B(n6119), .Y(n2459) );
INVX4TS U2238 ( .A(n5174), .Y(n3130) );
NAND2X4TS U2239 ( .A(n3027), .B(n4257), .Y(n3023) );
INVX12TS U2240 ( .A(n4669), .Y(n4722) );
NAND2X6TS U2241 ( .A(n2644), .B(n2640), .Y(n1644) );
NAND2X4TS U2242 ( .A(n2821), .B(n2087), .Y(n5023) );
NAND4BX2TS U2243 ( .AN(n4036), .B(n4035), .C(n4034), .D(n6170), .Y(n1860) );
NAND2X2TS U2244 ( .A(n5834), .B(n2207), .Y(n3707) );
OAI22X2TS U2245 ( .A0(n6074), .A1(n2124), .B0(n6073), .B1(n6072), .Y(n3959)
);
NOR2X4TS U2246 ( .A(n2979), .B(n3201), .Y(n2978) );
NOR2X6TS U2247 ( .A(n4138), .B(n3897), .Y(n5000) );
NAND2X4TS U2248 ( .A(n1971), .B(n1972), .Y(n3887) );
INVX4TS U2249 ( .A(n2742), .Y(n2076) );
OR3X2TS U2250 ( .A(n4300), .B(n4299), .C(n4298), .Y(n5031) );
BUFX12TS U2251 ( .A(n4600), .Y(n2780) );
NOR2X2TS U2252 ( .A(n2607), .B(n2606), .Y(n2610) );
AOI21X2TS U2253 ( .A0(n4974), .A1(n3134), .B0(n3133), .Y(n3254) );
AOI21X2TS U2254 ( .A0(n3885), .A1(n3368), .B0(n3884), .Y(n1965) );
BUFX6TS U2255 ( .A(n4600), .Y(n1869) );
XNOR2X2TS U2256 ( .A(n2285), .B(n4013), .Y(n1848) );
BUFX3TS U2257 ( .A(n3185), .Y(n4974) );
CLKINVX6TS U2258 ( .A(n4681), .Y(n4062) );
AND3X2TS U2259 ( .A(n6114), .B(n6113), .C(n6112), .Y(n3934) );
NAND3X1TS U2260 ( .A(n6154), .B(n6153), .C(n6152), .Y(n3836) );
OR2X6TS U2261 ( .A(n3233), .B(n3753), .Y(n1894) );
AND2X2TS U2262 ( .A(n6144), .B(n6145), .Y(n2809) );
CLKAND2X2TS U2263 ( .A(n6146), .B(n6189), .Y(n2810) );
NOR2BX2TS U2264 ( .AN(n2438), .B(n6062), .Y(n2796) );
NOR2X1TS U2265 ( .A(n5442), .B(Raw_mant_NRM_SWR[32]), .Y(n3755) );
INVX4TS U2266 ( .A(n5054), .Y(n2607) );
NAND2X6TS U2267 ( .A(n4959), .B(n1896), .Y(n3215) );
AOI22X2TS U2268 ( .A0(n5690), .A1(n5689), .B0(n5688), .B1(n2206), .Y(n3971)
);
NAND2BX2TS U2269 ( .AN(n5737), .B(n2409), .Y(n3048) );
NOR2X2TS U2270 ( .A(n5826), .B(n5825), .Y(n2462) );
NOR2X6TS U2271 ( .A(n4267), .B(n3028), .Y(n3027) );
NAND2X4TS U2272 ( .A(n1849), .B(n2911), .Y(n2910) );
NOR2X6TS U2273 ( .A(n3154), .B(n3152), .Y(n3151) );
AOI2BB2X2TS U2274 ( .B0(n5891), .B1(n2171), .A0N(n5890), .A1N(n5889), .Y(
n4023) );
NAND2X2TS U2275 ( .A(n5903), .B(n2195), .Y(n3697) );
AOI21X2TS U2276 ( .A0(n5877), .A1(n2197), .B0(n2645), .Y(n2644) );
NOR2X6TS U2277 ( .A(n2464), .B(n2000), .Y(n1999) );
AOI2BB2X2TS U2278 ( .B0(n2220), .B1(n1902), .A0N(n6006), .A1N(n6005), .Y(
n3835) );
AOI2BB2X2TS U2279 ( .B0(n1902), .B1(n2219), .A0N(n5970), .A1N(n5969), .Y(
n3699) );
CLKAND2X2TS U2280 ( .A(n4009), .B(n4008), .Y(n2311) );
NAND2BX1TS U2281 ( .AN(n1903), .B(n5879), .Y(n2087) );
NOR2X6TS U2282 ( .A(n1973), .B(n1969), .Y(n1967) );
INVX4TS U2283 ( .A(n2561), .Y(n2513) );
NOR2X4TS U2284 ( .A(n3890), .B(DMP_SFG[49]), .Y(n5002) );
AND2X4TS U2285 ( .A(n3185), .B(n4995), .Y(n3401) );
NAND2X2TS U2286 ( .A(n3757), .B(n2032), .Y(n3761) );
OR2X6TS U2287 ( .A(n4926), .B(n4921), .Y(n2949) );
NAND2X1TS U2288 ( .A(n6063), .B(n2164), .Y(n3859) );
AND2X6TS U2289 ( .A(n2406), .B(n5083), .Y(n2921) );
BUFX4TS U2290 ( .A(n4983), .Y(n2760) );
NAND2X2TS U2291 ( .A(n3400), .B(DMP_SFG[39]), .Y(n4975) );
AND2X6TS U2292 ( .A(n4347), .B(n5438), .Y(n2078) );
INVX2TS U2293 ( .A(n1933), .Y(n1926) );
NAND2X2TS U2294 ( .A(n3394), .B(DMP_SFG[34]), .Y(n4944) );
AND2X4TS U2295 ( .A(n4019), .B(n4020), .Y(n1969) );
CLKINVX3TS U2296 ( .A(n2490), .Y(n3753) );
CLKINVX6TS U2297 ( .A(n1997), .Y(n1996) );
NAND2X6TS U2298 ( .A(n2699), .B(n2694), .Y(n5047) );
AOI21X2TS U2299 ( .A0(n5921), .A1(n4047), .B0(n5920), .Y(n3838) );
NAND2X2TS U2300 ( .A(n6175), .B(n6176), .Y(n2784) );
NOR2X2TS U2301 ( .A(n3397), .B(DMP_SFG[36]), .Y(n4918) );
BUFX16TS U2302 ( .A(n4600), .Y(n4658) );
NAND2X2TS U2303 ( .A(n3876), .B(DMP_SFG[45]), .Y(n3916) );
INVX2TS U2304 ( .A(n2837), .Y(n2822) );
NAND2X6TS U2305 ( .A(n4749), .B(n2651), .Y(n2952) );
BUFX16TS U2306 ( .A(n4600), .Y(n2529) );
NAND2X2TS U2307 ( .A(n3879), .B(DMP_SFG[46]), .Y(n3883) );
NAND2X2TS U2308 ( .A(n3395), .B(DMP_SFG[35]), .Y(n4949) );
NAND2X2TS U2309 ( .A(n3398), .B(DMP_SFG[37]), .Y(n4927) );
BUFX3TS U2310 ( .A(n3111), .Y(n1951) );
AOI21X2TS U2311 ( .A0(n2131), .A1(n5748), .B0(n2774), .Y(n2773) );
NAND2X4TS U2312 ( .A(n4271), .B(n3769), .Y(n4280) );
NOR2X2TS U2313 ( .A(n1929), .B(n1928), .Y(n1927) );
NOR2X6TS U2314 ( .A(n3113), .B(n3207), .Y(n3112) );
CLKBUFX2TS U2315 ( .A(Raw_mant_NRM_SWR[47]), .Y(n2032) );
OR2X4TS U2316 ( .A(n4886), .B(Raw_mant_NRM_SWR[2]), .Y(n2403) );
NAND2X2TS U2317 ( .A(n3998), .B(n3997), .Y(n3999) );
NOR2X6TS U2318 ( .A(n2319), .B(n5443), .Y(n3756) );
INVX2TS U2319 ( .A(n4267), .Y(n3249) );
INVX6TS U2320 ( .A(n4004), .Y(n2843) );
CLKAND2X2TS U2321 ( .A(n6109), .B(n6110), .Y(n2839) );
NAND2X4TS U2322 ( .A(n4600), .B(n1925), .Y(n1957) );
INVX2TS U2323 ( .A(n4251), .Y(n3770) );
NOR2X6TS U2324 ( .A(n3874), .B(DMP_SFG[43]), .Y(n4019) );
AOI21X2TS U2325 ( .A0(n5848), .A1(n5849), .B0(n3138), .Y(n3137) );
INVX12TS U2326 ( .A(n4779), .Y(n3272) );
BUFX3TS U2327 ( .A(n4012), .Y(n2962) );
INVX2TS U2328 ( .A(n3870), .Y(n3871) );
NAND2X2TS U2329 ( .A(n2652), .B(DMP_SFG[24]), .Y(n4749) );
NAND2BX2TS U2330 ( .AN(n5983), .B(n2408), .Y(n2824) );
OR2X4TS U2331 ( .A(n3879), .B(DMP_SFG[46]), .Y(n3368) );
NAND2X4TS U2332 ( .A(n4257), .B(n2037), .Y(n1997) );
AND2X4TS U2333 ( .A(n3693), .B(n3694), .Y(n1901) );
NOR2X6TS U2334 ( .A(n3221), .B(n2752), .Y(n3220) );
NAND2X6TS U2335 ( .A(n4892), .B(n3744), .Y(n4886) );
NAND2X6TS U2336 ( .A(n3461), .B(n3478), .Y(n3481) );
AOI2BB2X2TS U2337 ( .B0(n5958), .B1(n2196), .A0N(n2232), .A1N(n2147), .Y(
n3695) );
NAND2X2TS U2338 ( .A(n3397), .B(DMP_SFG[36]), .Y(n4921) );
BUFX2TS U2339 ( .A(n2465), .Y(n1824) );
AND2X4TS U2340 ( .A(n4347), .B(n3783), .Y(n3035) );
NAND2X2TS U2341 ( .A(n3508), .B(n3523), .Y(n3509) );
NOR2X2TS U2342 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM2_EW[8]), .Y(n4002)
);
INVX2TS U2343 ( .A(n2947), .Y(n3978) );
NOR2X4TS U2344 ( .A(n4258), .B(n1986), .Y(n3735) );
NOR2X4TS U2345 ( .A(n3513), .B(n3559), .Y(n3518) );
INVX6TS U2346 ( .A(n3094), .Y(n1850) );
NAND2X1TS U2347 ( .A(n3785), .B(n3784), .Y(n3788) );
BUFX3TS U2348 ( .A(Raw_mant_NRM_SWR[53]), .Y(n2019) );
NAND2X2TS U2349 ( .A(n3405), .B(DMP_SFG[42]), .Y(n3870) );
BUFX3TS U2350 ( .A(n3984), .Y(n2947) );
NAND3X4TS U2351 ( .A(n2616), .B(n3779), .C(n2615), .Y(n4246) );
BUFX4TS U2352 ( .A(n3750), .Y(n3219) );
OR2X4TS U2353 ( .A(n4005), .B(n4007), .Y(n4004) );
INVX2TS U2354 ( .A(n4759), .Y(n3387) );
NOR2X6TS U2355 ( .A(n3876), .B(DMP_SFG[45]), .Y(n3915) );
NAND2X4TS U2356 ( .A(n3515), .B(n3560), .Y(n3517) );
OR2X4TS U2357 ( .A(n3403), .B(DMP_SFG[41]), .Y(n2389) );
BUFX3TS U2358 ( .A(Raw_mant_NRM_SWR[43]), .Y(n1986) );
NAND2X2TS U2359 ( .A(n3774), .B(n2766), .Y(n4260) );
NOR2X6TS U2360 ( .A(n3380), .B(n5095), .Y(n3381) );
NOR2X1TS U2361 ( .A(n6001), .B(n6000), .Y(n2592) );
NAND2BX2TS U2362 ( .AN(Raw_mant_NRM_SWR[6]), .B(n4248), .Y(n3731) );
INVX4TS U2363 ( .A(n4742), .Y(n4753) );
OR2X4TS U2364 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM2_EW[6]), .Y(n2387) );
INVX6TS U2365 ( .A(n1925), .Y(n1953) );
NOR2X2TS U2366 ( .A(n2173), .B(n2232), .Y(n2582) );
NAND2BX2TS U2367 ( .AN(n3041), .B(n5445), .Y(n3040) );
INVX2TS U2368 ( .A(n3920), .Y(n3872) );
INVX6TS U2369 ( .A(n4748), .Y(n1914) );
NOR2X4TS U2370 ( .A(n3460), .B(n3473), .Y(n3461) );
NOR2X4TS U2371 ( .A(n3485), .B(n2768), .Y(n3467) );
BUFX4TS U2372 ( .A(Raw_mant_NRM_SWR[35]), .Y(n2037) );
AND2X6TS U2373 ( .A(intDX_EWSW[6]), .B(n2481), .Y(n3420) );
BUFX8TS U2374 ( .A(n4939), .Y(n2744) );
BUFX4TS U2375 ( .A(n2467), .Y(n2052) );
NAND2X4TS U2376 ( .A(n5420), .B(n2889), .Y(n4349) );
BUFX4TS U2377 ( .A(n3980), .Y(n2011) );
NAND2X2TS U2378 ( .A(n2844), .B(DMP_SFG[32]), .Y(n4955) );
NOR2X6TS U2379 ( .A(n3561), .B(n2708), .Y(n3516) );
NAND2X4TS U2380 ( .A(n3392), .B(DMP_SFG[30]), .Y(n4978) );
NOR2X6TS U2381 ( .A(n3342), .B(intDY_EWSW[23]), .Y(n3476) );
NOR2X6TS U2382 ( .A(n2652), .B(DMP_SFG[24]), .Y(n4748) );
NAND2X2TS U2383 ( .A(n3356), .B(intDY_EWSW[18]), .Y(n2455) );
NAND2X2TS U2384 ( .A(n3289), .B(intDY_EWSW[12]), .Y(n3446) );
NOR2X2TS U2385 ( .A(n3315), .B(intDY_EWSW[8]), .Y(n3434) );
NAND2X4TS U2386 ( .A(n3310), .B(intDY_EWSW[16]), .Y(n2458) );
NOR2X2TS U2387 ( .A(n3289), .B(intDY_EWSW[12]), .Y(n3431) );
NAND2X6TS U2388 ( .A(n2862), .B(n3545), .Y(n3548) );
NOR2X6TS U2389 ( .A(n2687), .B(n2705), .Y(n3553) );
NAND2X2TS U2390 ( .A(n3762), .B(n3763), .Y(n2626) );
NOR2X4TS U2391 ( .A(n3333), .B(intDY_EWSW[22]), .Y(n3118) );
NAND2X2TS U2392 ( .A(n3340), .B(intDY_EWSW[13]), .Y(n3445) );
NAND2X2TS U2393 ( .A(n3323), .B(intDY_EWSW[11]), .Y(n3439) );
NAND2X2TS U2394 ( .A(n3317), .B(intDY_EWSW[6]), .Y(n3426) );
NAND2X2TS U2395 ( .A(n3332), .B(intDY_EWSW[54]), .Y(n3558) );
NAND2X6TS U2396 ( .A(n2031), .B(intDY_EWSW[58]), .Y(n2804) );
NAND2X2TS U2397 ( .A(n3369), .B(DMP_exp_NRM2_EW[5]), .Y(n4008) );
NAND2X6TS U2398 ( .A(n4780), .B(n2667), .Y(n2674) );
NOR2X4TS U2399 ( .A(n3356), .B(intDY_EWSW[18]), .Y(n2456) );
NAND2X6TS U2400 ( .A(n3306), .B(intDY_EWSW[48]), .Y(n2689) );
NAND2X2TS U2401 ( .A(n3359), .B(n2295), .Y(n3422) );
NAND2X2TS U2402 ( .A(n3328), .B(n2310), .Y(n3410) );
NOR2X4TS U2403 ( .A(n3183), .B(DMP_SFG[15]), .Y(n5095) );
NAND2X2TS U2404 ( .A(n3319), .B(intDY_EWSW[9]), .Y(n2741) );
NOR2X6TS U2405 ( .A(n3357), .B(n2250), .Y(n3485) );
NAND3X4TS U2406 ( .A(n2015), .B(n3782), .C(n3743), .Y(n4245) );
NAND2X4TS U2407 ( .A(n1987), .B(intDY_EWSW[56]), .Y(n2808) );
INVX12TS U2408 ( .A(n1866), .Y(n3986) );
NAND2X2TS U2409 ( .A(n2301), .B(n3772), .Y(n2625) );
BUFX6TS U2410 ( .A(n4270), .Y(n2038) );
INVX3TS U2411 ( .A(n3765), .Y(n2869) );
OR2X6TS U2412 ( .A(n3379), .B(DMP_SFG[17]), .Y(n3370) );
AND2X6TS U2413 ( .A(intDX_EWSW[54]), .B(n2332), .Y(n3512) );
INVX4TS U2414 ( .A(n2650), .Y(n3389) );
NAND2X4TS U2415 ( .A(n3373), .B(DMP_exp_NRM2_EW[4]), .Y(n4012) );
NOR2X4TS U2416 ( .A(n3336), .B(intDY_EWSW[56]), .Y(n3514) );
NAND2X4TS U2417 ( .A(n3360), .B(intDY_EWSW[40]), .Y(n3531) );
INVX2TS U2418 ( .A(n2004), .Y(n3748) );
NOR2X2TS U2419 ( .A(n5999), .B(n5998), .Y(n2595) );
NOR2X6TS U2420 ( .A(n2007), .B(n2006), .Y(n3523) );
NAND2X2TS U2421 ( .A(n3302), .B(intDY_EWSW[46]), .Y(n3542) );
OR2X4TS U2422 ( .A(n3346), .B(intDY_EWSW[36]), .Y(n1900) );
INVX4TS U2423 ( .A(n6216), .Y(n5029) );
NOR2X4TS U2424 ( .A(n3306), .B(intDY_EWSW[48]), .Y(n2117) );
AND2X6TS U2425 ( .A(n5279), .B(n5473), .Y(n2343) );
NOR2X6TS U2426 ( .A(Raw_mant_NRM_SWR[8]), .B(Raw_mant_NRM_SWR[7]), .Y(n4248)
);
NOR2X6TS U2427 ( .A(DMP_SFG[31]), .B(n2628), .Y(n4983) );
INVX8TS U2428 ( .A(n4348), .Y(n2851) );
NAND2X2TS U2429 ( .A(n3349), .B(intDY_EWSW[37]), .Y(n3524) );
INVX4TS U2430 ( .A(n2307), .Y(n2308) );
NOR2X4TS U2431 ( .A(n3360), .B(intDY_EWSW[40]), .Y(n2860) );
NOR2X2TS U2432 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[9]), .Y(n3742)
);
NOR2X2TS U2433 ( .A(Raw_mant_NRM_SWR[35]), .B(Raw_mant_NRM_SWR[34]), .Y(
n2868) );
NOR2X6TS U2434 ( .A(n3301), .B(n2299), .Y(n3540) );
NOR2X6TS U2435 ( .A(n3363), .B(intDY_EWSW[42]), .Y(n2861) );
NAND2X6TS U2436 ( .A(n3762), .B(n2005), .Y(n2004) );
NOR2X2TS U2437 ( .A(n2300), .B(n2252), .Y(n2005) );
NAND2X6TS U2438 ( .A(n3789), .B(n3790), .Y(n4348) );
NAND2X4TS U2439 ( .A(n2062), .B(n2061), .Y(n2063) );
NOR2X4TS U2440 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[22]), .Y(
n1991) );
NAND2X6TS U2441 ( .A(n2057), .B(n2056), .Y(n2060) );
NOR2X6TS U2442 ( .A(Raw_mant_NRM_SWR[28]), .B(Raw_mant_NRM_SWR[34]), .Y(
n2065) );
INVX4TS U2443 ( .A(n1851), .Y(n1852) );
INVX6TS U2444 ( .A(n1851), .Y(n1853) );
INVX3TS U2445 ( .A(Raw_mant_NRM_SWR[49]), .Y(n3726) );
INVX2TS U2446 ( .A(n1854), .Y(n2493) );
INVX8TS U2447 ( .A(n1851), .Y(n1854) );
INVX16TS U2448 ( .A(n2934), .Y(n2495) );
OAI22X4TS U2449 ( .A0(n5248), .A1(n1916), .B0(n5287), .B1(n5526), .Y(n1078)
);
NAND2X4TS U2450 ( .A(n5138), .B(n5145), .Y(n3148) );
BUFX20TS U2451 ( .A(n6221), .Y(n6222) );
NOR2X6TS U2452 ( .A(n6456), .B(n5245), .Y(n3145) );
OR3X6TS U2453 ( .A(n3058), .B(n2503), .C(n2504), .Y(n5124) );
INVX12TS U2454 ( .A(n1906), .Y(n6227) );
CLKINVX6TS U2455 ( .A(n1958), .Y(n4474) );
NAND2X2TS U2456 ( .A(n4905), .B(n4904), .Y(n1605) );
NAND2X2TS U2457 ( .A(n4548), .B(n4547), .Y(n1034) );
NAND2X4TS U2458 ( .A(n4512), .B(n5161), .Y(n4515) );
NAND3X8TS U2459 ( .A(n2573), .B(n2579), .C(n2424), .Y(n4512) );
OAI2BB1X4TS U2460 ( .A0N(n5161), .A1N(n6459), .B0(n5132), .Y(n1111) );
NAND3X4TS U2461 ( .A(n3586), .B(n3585), .C(n3584), .Y(n1224) );
OAI21X4TS U2462 ( .A0(n4606), .A1(n5264), .B0(n3079), .Y(n1040) );
AND2X8TS U2463 ( .A(n3080), .B(n2775), .Y(n4606) );
NAND3X4TS U2464 ( .A(n4312), .B(n4311), .C(n4310), .Y(n1294) );
NAND3X8TS U2465 ( .A(n3974), .B(n3973), .C(n3972), .Y(n4618) );
NAND2X8TS U2466 ( .A(n3839), .B(n2704), .Y(n4682) );
NAND2X4TS U2467 ( .A(n5051), .B(n2555), .Y(n3839) );
NAND2X4TS U2468 ( .A(n5263), .B(n2449), .Y(n2852) );
NOR2X6TS U2469 ( .A(n4630), .B(n4629), .Y(n5254) );
NAND2X4TS U2470 ( .A(n3156), .B(n3155), .Y(n1039) );
AOI22X2TS U2471 ( .A0(n4637), .A1(n4672), .B0(n5054), .B1(n3846), .Y(n3096)
);
INVX16TS U2472 ( .A(n3045), .Y(n3046) );
INVX8TS U2473 ( .A(n1635), .Y(n4678) );
NOR2X4TS U2474 ( .A(n2611), .B(n5049), .Y(n4533) );
INVX6TS U2475 ( .A(n2767), .Y(n5096) );
NAND2X4TS U2476 ( .A(n4672), .B(n2529), .Y(n3099) );
OAI21X2TS U2477 ( .A0(n5249), .A1(n2554), .B0(n3109), .Y(n1119) );
NAND4X4TS U2478 ( .A(n4623), .B(n4621), .C(n4622), .D(n4624), .Y(n5136) );
NAND3X6TS U2479 ( .A(n4082), .B(n4081), .C(n4080), .Y(n4704) );
NAND3BX2TS U2480 ( .AN(n2928), .B(n4030), .C(n4031), .Y(n2927) );
NAND2X2TS U2481 ( .A(n6174), .B(n6173), .Y(n2928) );
OA22X4TS U2482 ( .A0(n5980), .A1(n5979), .B0(n5978), .B1(n5977), .Y(n3936)
);
NAND2X8TS U2483 ( .A(n3044), .B(n2941), .Y(n2637) );
NAND2X4TS U2484 ( .A(n5124), .B(n5161), .Y(n4495) );
AOI22X2TS U2485 ( .A0(n4633), .A1(n3062), .B0(n2518), .B1(n4721), .Y(n2472)
);
NAND2X2TS U2486 ( .A(n4633), .B(n5147), .Y(n4628) );
OAI21X2TS U2487 ( .A0(n4662), .A1(n4675), .B0(n3857), .Y(n3867) );
INVX16TS U2488 ( .A(n4662), .Y(n2555) );
NOR3X8TS U2489 ( .A(n2390), .B(n5965), .C(n3053), .Y(n3052) );
NAND3X6TS U2490 ( .A(n4041), .B(n4040), .C(n4039), .Y(n4712) );
CLKINVX12TS U2491 ( .A(n6221), .Y(n3045) );
BUFX8TS U2492 ( .A(n6221), .Y(n6220) );
NAND2X4TS U2493 ( .A(n5143), .B(n4685), .Y(n2798) );
AOI22X2TS U2494 ( .A0(n4637), .A1(n4699), .B0(n2780), .B1(n5035), .Y(n4086)
);
NAND2X2TS U2495 ( .A(n4658), .B(n4699), .Y(n4484) );
NAND2X2TS U2496 ( .A(n2261), .B(n4699), .Y(n4622) );
NOR2X8TS U2497 ( .A(n3145), .B(n2385), .Y(n3144) );
NAND2X4TS U2498 ( .A(n2041), .B(intDX_EWSW[43]), .Y(n3586) );
OAI2BB1X2TS U2499 ( .A0N(n4543), .A1N(n6452), .B0(n4507), .Y(n1054) );
NAND2X4TS U2500 ( .A(n2027), .B(intDX_EWSW[8]), .Y(n4312) );
NAND3X4TS U2501 ( .A(n4422), .B(n4423), .C(n4421), .Y(n1561) );
NOR2X2TS U2502 ( .A(n3853), .B(n3852), .Y(n3856) );
AOI22X2TS U2503 ( .A0(n5941), .A1(n2192), .B0(n5940), .B1(n2169), .Y(n3855)
);
NAND3X8TS U2504 ( .A(n3933), .B(n3934), .C(n3151), .Y(n5025) );
OR2X4TS U2505 ( .A(n5722), .B(n2176), .Y(n4031) );
NAND2X4TS U2506 ( .A(n1944), .B(n5028), .Y(n1942) );
AOI21X4TS U2507 ( .A0(n3245), .A1(n5075), .B0(n5074), .Y(n5080) );
OAI2BB1X4TS U2508 ( .A0N(n5016), .A1N(n2558), .B0(n4486), .Y(n3061) );
INVX6TS U2509 ( .A(n5030), .Y(n4490) );
NAND2X4TS U2510 ( .A(n5344), .B(n5436), .Y(n2769) );
NOR2X6TS U2511 ( .A(n5436), .B(n5344), .Y(n3804) );
OAI21X2TS U2512 ( .A0(n4756), .A1(n4751), .B0(n5085), .Y(n4740) );
NAND4X2TS U2513 ( .A(n4173), .B(n4172), .C(n4171), .D(n4170), .Y(n4184) );
INVX16TS U2514 ( .A(n3234), .Y(n2557) );
NAND3X4TS U2515 ( .A(n3592), .B(n3593), .C(n3591), .Y(n1547) );
NAND2X4TS U2516 ( .A(intDX_EWSW[59]), .B(n4873), .Y(n3589) );
NAND3X8TS U2517 ( .A(n2105), .B(n2104), .C(n2103), .Y(n2102) );
NAND2X4TS U2518 ( .A(n4671), .B(n2330), .Y(n3072) );
NAND4BX4TS U2519 ( .AN(n3715), .B(n3714), .C(n6140), .D(n6139), .Y(n5275) );
AOI2BB2X4TS U2520 ( .B0(n5948), .B1(n2194), .A0N(n5947), .A1N(n2204), .Y(
n3960) );
NAND3X4TS U2521 ( .A(n2998), .B(n2997), .C(n2996), .Y(n2995) );
OAI21X2TS U2522 ( .A0(n2904), .A1(n5005), .B0(n2903), .Y(n1162) );
NAND2X8TS U2523 ( .A(n2968), .B(n4320), .Y(n6381) );
OAI22X4TS U2524 ( .A0(n6037), .A1(n6036), .B0(n6039), .B1(n6038), .Y(n3721)
);
AOI21X4TS U2525 ( .A0(n5777), .A1(n2131), .B0(n5776), .Y(n3720) );
NAND3X2TS U2526 ( .A(n3690), .B(n3691), .C(n3689), .Y(n1228) );
CLKINVX12TS U2527 ( .A(n4656), .Y(n6410) );
NAND2X8TS U2528 ( .A(n3139), .B(n3137), .Y(n4656) );
NAND2X4TS U2529 ( .A(n5153), .B(n4487), .Y(n2998) );
NAND2X8TS U2530 ( .A(n4091), .B(n4090), .Y(n5153) );
OAI22X2TS U2531 ( .A0(n1916), .A1(n5249), .B0(n5287), .B1(n5527), .Y(n1080)
);
MX2X4TS U2532 ( .A(n5090), .B(Raw_mant_NRM_SWR[22]), .S0(n5205), .Y(n1176)
);
AOI2BB1X4TS U2533 ( .A0N(n6440), .A1N(n5159), .B0(n2380), .Y(n2588) );
NOR2X8TS U2534 ( .A(n4616), .B(n4615), .Y(n5266) );
AOI22X2TS U2535 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[13]), .B0(n5014), .B1(
n6230), .Y(n6361) );
NOR2X6TS U2536 ( .A(n3384), .B(DMP_SFG[20]), .Y(n4751) );
NAND2X4TS U2537 ( .A(DMP_SFG[20]), .B(n3384), .Y(n5085) );
NOR2X6TS U2538 ( .A(n3005), .B(n3000), .Y(n2999) );
NAND4BX4TS U2539 ( .AN(n4664), .B(n6164), .C(n4663), .D(n6163), .Y(n5043) );
OAI22X2TS U2540 ( .A0(n6071), .A1(n6070), .B0(n6069), .B1(n6068), .Y(n4664)
);
NAND2X2TS U2541 ( .A(n5932), .B(n5931), .Y(n4663) );
OAI22X4TS U2542 ( .A0(n6052), .A1(n2187), .B0(n6051), .B1(n6050), .Y(n3718)
);
AOI21X4TS U2543 ( .A0(n4047), .A1(n5923), .B0(n5922), .Y(n3717) );
NOR4X2TS U2544 ( .A(n4224), .B(n4223), .C(n4222), .D(n4221), .Y(n4225) );
NAND4X2TS U2545 ( .A(n4209), .B(n4208), .C(n4207), .D(n4206), .Y(n4224) );
NAND2X8TS U2546 ( .A(n4131), .B(n2939), .Y(n1143) );
NAND2X4TS U2547 ( .A(n4412), .B(intDX_EWSW[26]), .Y(n4422) );
AOI22X4TS U2548 ( .A0(n5930), .A1(n2163), .B0(n5929), .B1(n2207), .Y(n3829)
);
NOR2X8TS U2549 ( .A(n6353), .B(n3022), .Y(n3047) );
INVX6TS U2550 ( .A(n2653), .Y(n2906) );
AOI22X2TS U2551 ( .A0(n4659), .A1(n1644), .B0(n2780), .B1(n5036), .Y(n4048)
);
NAND4BX2TS U2552 ( .AN(n3715), .B(n3714), .C(n6140), .D(n6139), .Y(n2297) );
NAND2X4TS U2553 ( .A(n6206), .B(n1986), .Y(n2016) );
BUFX20TS U2554 ( .A(n4430), .Y(n2041) );
NAND3X6TS U2555 ( .A(n4420), .B(n4419), .C(n4418), .Y(n1577) );
NAND2X4TS U2556 ( .A(n4863), .B(intDX_EWSW[10]), .Y(n4419) );
NAND2X4TS U2557 ( .A(n4877), .B(intDX_EWSW[5]), .Y(n4401) );
NAND3X4TS U2558 ( .A(n4450), .B(n4451), .C(n4449), .Y(n1202) );
BUFX20TS U2559 ( .A(n3261), .Y(n3234) );
NAND3X4TS U2560 ( .A(n4829), .B(n4830), .C(n4828), .Y(n1264) );
NAND3X4TS U2561 ( .A(n4841), .B(n4842), .C(n4840), .Y(n1258) );
NAND2X2TS U2562 ( .A(n2529), .B(n1628), .Y(n4294) );
NAND2X2TS U2563 ( .A(n6461), .B(n6215), .Y(n6415) );
NAND2X2TS U2564 ( .A(n6439), .B(n6215), .Y(n6434) );
AND2X6TS U2565 ( .A(n4424), .B(intDX_EWSW[22]), .Y(n2281) );
NAND2X4TS U2566 ( .A(n2115), .B(intDY_EWSW[56]), .Y(n4450) );
NAND2X4TS U2567 ( .A(n5157), .B(n4691), .Y(n2579) );
OAI21X2TS U2568 ( .A0(n3209), .A1(n2550), .B0(n3267), .Y(n1145) );
NAND3X4TS U2569 ( .A(n3579), .B(n3580), .C(n3578), .Y(n1222) );
NOR2X4TS U2570 ( .A(n3398), .B(DMP_SFG[37]), .Y(n4926) );
NAND2X4TS U2571 ( .A(n3846), .B(n5262), .Y(n4530) );
NAND2X4TS U2572 ( .A(n2261), .B(n5262), .Y(n4060) );
NAND2X4TS U2573 ( .A(n4416), .B(intDX_EWSW[51]), .Y(n4110) );
OAI22X2TS U2574 ( .A0(n1916), .A1(n4092), .B0(n5289), .B1(n5544), .Y(n1075)
);
NAND3X6TS U2575 ( .A(n3672), .B(n3673), .C(n3671), .Y(n1569) );
NAND2X4TS U2576 ( .A(n4863), .B(intDX_EWSW[18]), .Y(n3672) );
NAND2X2TS U2577 ( .A(n3630), .B(intDX_EWSW[24]), .Y(n4833) );
NAND2BX2TS U2578 ( .AN(n2965), .B(n4102), .Y(n1278) );
NAND3X4TS U2579 ( .A(n4872), .B(n4871), .C(n4870), .Y(n1573) );
NAND2X4TS U2580 ( .A(n4379), .B(intDX_EWSW[14]), .Y(n4871) );
OAI22X2TS U2581 ( .A0(n3022), .A1(n2324), .B0(n4332), .B1(n5010), .Y(n5011)
);
BUFX20TS U2582 ( .A(n5040), .Y(n3022) );
NAND2X4TS U2583 ( .A(n2988), .B(Raw_mant_NRM_SWR[50]), .Y(n4306) );
CLKINVX12TS U2584 ( .A(n2648), .Y(n2988) );
AOI22X2TS U2585 ( .A0(n4657), .A1(n1869), .B0(n5021), .B1(n4659), .Y(n4660)
);
OAI21X4TS U2586 ( .A0(Raw_mant_NRM_SWR[8]), .A1(n5424), .B0(n5340), .Y(n4253) );
NAND2X4TS U2587 ( .A(n4078), .B(n1816), .Y(n1574) );
NAND3X6TS U2588 ( .A(n3670), .B(n3669), .C(n3668), .Y(n1570) );
INVX16TS U2589 ( .A(n2934), .Y(n2287) );
NAND3X6TS U2590 ( .A(n4075), .B(n4076), .C(n4074), .Y(n1580) );
INVX16TS U2591 ( .A(n6202), .Y(n2496) );
NAND2X2TS U2592 ( .A(n6381), .B(n6408), .Y(n6382) );
NAND2X2TS U2593 ( .A(n6408), .B(n4321), .Y(n6327) );
NAND2X2TS U2594 ( .A(n4412), .B(intDY_EWSW[49]), .Y(n4850) );
NAND2X6TS U2595 ( .A(n2951), .B(n1815), .Y(n3576) );
AOI22X2TS U2596 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[7]), .B0(n5024), .B1(
n5041), .Y(n6346) );
NOR2X8TS U2597 ( .A(n4939), .B(n4983), .Y(n3070) );
INVX12TS U2598 ( .A(n4965), .Y(n1921) );
NOR2X8TS U2599 ( .A(n2972), .B(n1899), .Y(n6388) );
AND2X6TS U2600 ( .A(n6203), .B(DmP_mant_SHT1_SW[43]), .Y(n1899) );
NAND3X6TS U2601 ( .A(n4411), .B(n4410), .C(n4409), .Y(n1578) );
NAND2X4TS U2602 ( .A(n4877), .B(intDX_EWSW[9]), .Y(n4410) );
BUFX20TS U2603 ( .A(n3087), .Y(n2531) );
NAND2X4TS U2604 ( .A(n2494), .B(n5175), .Y(n1595) );
NAND2X4TS U2605 ( .A(n2494), .B(n5177), .Y(n1597) );
NAND2X4TS U2606 ( .A(n2494), .B(n5179), .Y(n1593) );
NAND2X4TS U2607 ( .A(n2494), .B(n5181), .Y(n1589) );
NAND2X4TS U2608 ( .A(n2494), .B(n5165), .Y(n1596) );
NAND2X4TS U2609 ( .A(n2494), .B(n5173), .Y(n1591) );
NAND2X4TS U2610 ( .A(n2494), .B(n5171), .Y(n1594) );
NAND2X4TS U2611 ( .A(n2494), .B(n5167), .Y(n1590) );
NAND2X4TS U2612 ( .A(n2494), .B(n5168), .Y(n1592) );
NAND2X4TS U2613 ( .A(n2494), .B(n5170), .Y(n1598) );
AOI22X2TS U2614 ( .A0(n6218), .A1(Raw_mant_NRM_SWR[21]), .B0(n6199), .B1(
DmP_mant_SHT1_SW[28]), .Y(n6340) );
AOI22X2TS U2615 ( .A0(n6218), .A1(n1856), .B0(n6199), .B1(
DmP_mant_SHT1_SW[45]), .Y(n6367) );
NAND2X4TS U2616 ( .A(n6199), .B(DmP_mant_SHT1_SW[22]), .Y(n6298) );
NAND2X4TS U2617 ( .A(n6199), .B(DmP_mant_SHT1_SW[16]), .Y(n6338) );
AOI22X2TS U2618 ( .A0(n6206), .A1(Raw_mant_NRM_SWR[17]), .B0(n5033), .B1(
n6230), .Y(n6303) );
NAND4X6TS U2619 ( .A(n3038), .B(n4279), .C(n2647), .D(n3037), .Y(n3201) );
NAND3X4TS U2620 ( .A(n4281), .B(n4279), .C(n4280), .Y(n4282) );
NAND3X6TS U2621 ( .A(n4362), .B(n4361), .C(n4360), .Y(n1535) );
NAND2X4TS U2622 ( .A(n2116), .B(intDX_EWSW[52]), .Y(n4361) );
NAND2X2TS U2623 ( .A(n5157), .B(n1872), .Y(n1963) );
NAND2XLTS U2624 ( .A(n5264), .B(DmP_mant_SFG_SWR[30]), .Y(n3079) );
NAND2X2TS U2625 ( .A(n4379), .B(intDY_EWSW[8]), .Y(n4311) );
AOI22X4TS U2626 ( .A0(n5882), .A1(n2165), .B0(n2127), .B1(n5700), .Y(n2234)
);
NAND2X2TS U2627 ( .A(n1837), .B(intDY_EWSW[50]), .Y(n4836) );
MXI2X2TS U2628 ( .A(n5394), .B(n5478), .S0(n5224), .Y(n1471) );
NAND2X4TS U2629 ( .A(n4412), .B(intDX_EWSW[51]), .Y(n4398) );
OAI22X2TS U2630 ( .A0(n5268), .A1(n2453), .B0(n5287), .B1(n5523), .Y(n1068)
);
OAI22X2TS U2631 ( .A0(n2597), .A1(n2453), .B0(n5292), .B1(n5542), .Y(n1090)
);
NAND2X2TS U2632 ( .A(n2535), .B(DmP_EXP_EWSW[2]), .Y(n4373) );
NAND2X4TS U2633 ( .A(n4417), .B(DmP_EXP_EWSW[40]), .Y(n3683) );
NAND2X4TS U2634 ( .A(n2536), .B(DMP_EXP_EWSW[6]), .Y(n4443) );
AND2X4TS U2635 ( .A(n5176), .B(n5169), .Y(n4017) );
INVX6TS U2636 ( .A(n2011), .Y(n3982) );
NAND2X6TS U2637 ( .A(DMP_exp_NRM2_EW[1]), .B(n2308), .Y(n3981) );
OR3X8TS U2638 ( .A(n2281), .B(n2280), .C(n2282), .Y(n1266) );
NOR2X8TS U2639 ( .A(n3327), .B(intDY_EWSW[2]), .Y(n3413) );
NAND2X6TS U2640 ( .A(n2951), .B(intDX_EWSW[48]), .Y(n4390) );
INVX6TS U2641 ( .A(n6214), .Y(n2306) );
NAND2X6TS U2642 ( .A(n3249), .B(n1996), .Y(n1995) );
NAND2BX4TS U2643 ( .AN(n1818), .B(n2951), .Y(n3684) );
BUFX16TS U2644 ( .A(n5027), .Y(n6219) );
NOR2X8TS U2645 ( .A(n3083), .B(n2398), .Y(n3082) );
INVX6TS U2646 ( .A(n4026), .Y(n6200) );
NAND2X4TS U2647 ( .A(n5047), .B(n2780), .Y(n3868) );
NAND3X6TS U2648 ( .A(n3647), .B(n3648), .C(n3646), .Y(n1555) );
NOR3X8TS U2649 ( .A(n4268), .B(Raw_mant_NRM_SWR[30]), .C(n3770), .Y(n2983)
);
NAND2X8TS U2650 ( .A(n1820), .B(n1819), .Y(n2693) );
AND2X8TS U2651 ( .A(n2697), .B(n2698), .Y(n1819) );
OR2X8TS U2652 ( .A(n2436), .B(n2379), .Y(n1820) );
MX2X6TS U2653 ( .A(n6433), .B(n5564), .S0(n5245), .Y(n5160) );
OAI21X4TS U2654 ( .A0(n3751), .A1(Raw_mant_NRM_SWR[17]), .B0(n5440), .Y(
n3754) );
NAND2X2TS U2655 ( .A(n2691), .B(n4487), .Y(n3090) );
AOI22X4TS U2656 ( .A0(n5957), .A1(n4047), .B0(n5874), .B1(n2192), .Y(n2813)
);
INVX12TS U2657 ( .A(n5928), .Y(n4047) );
NOR2X8TS U2658 ( .A(n2812), .B(n2814), .Y(n2811) );
AOI22X4TS U2659 ( .A0(n4061), .A1(n1876), .B0(n5150), .B1(n5145), .Y(n4092)
);
NAND3X8TS U2660 ( .A(n4057), .B(n4056), .C(n4058), .Y(n4061) );
NOR2X6TS U2661 ( .A(n2937), .B(n1911), .Y(n2033) );
AND2X8TS U2662 ( .A(n3989), .B(n1821), .Y(n2936) );
NOR2X4TS U2663 ( .A(n3987), .B(n3984), .Y(n1821) );
INVX4TS U2664 ( .A(n2966), .Y(n1822) );
NAND2X4TS U2665 ( .A(n1822), .B(n4104), .Y(n1214) );
AOI22X2TS U2666 ( .A0(n6219), .A1(n2012), .B0(n5031), .B1(n6228), .Y(n6350)
);
BUFX6TS U2667 ( .A(Raw_mant_NRM_SWR[34]), .Y(n1825) );
NAND3X6TS U2668 ( .A(n2001), .B(n1999), .C(n1894), .Y(n1998) );
NAND2X8TS U2669 ( .A(n2285), .B(n2843), .Y(n2750) );
BUFX16TS U2670 ( .A(n5027), .Y(n6218) );
BUFX20TS U2671 ( .A(n2470), .Y(n2088) );
BUFX20TS U2672 ( .A(n3087), .Y(n4424) );
NAND3X8TS U2673 ( .A(n3244), .B(n4249), .C(n3243), .Y(n2034) );
NAND3X8TS U2674 ( .A(n3073), .B(n3072), .C(n3071), .Y(n4604) );
NAND2X2TS U2675 ( .A(n4473), .B(n4672), .Y(n3844) );
NAND2X8TS U2676 ( .A(n1990), .B(n1991), .Y(n1992) );
NOR2X8TS U2677 ( .A(n4246), .B(n3731), .Y(n2942) );
BUFX20TS U2678 ( .A(n3087), .Y(n2530) );
NAND2X4TS U2679 ( .A(n4369), .B(n2945), .Y(n4802) );
NAND3X6TS U2680 ( .A(n3590), .B(n3589), .C(n3588), .Y(n1528) );
OAI2BB1X4TS U2681 ( .A0N(n5149), .A1N(n6439), .B0(n2588), .Y(n1037) );
OAI21X4TS U2682 ( .A0(n2685), .A1(n3559), .B0(n1829), .Y(n3570) );
AOI21X4TS U2683 ( .A0(n2682), .A1(n2684), .B0(n2681), .Y(n1829) );
NAND2X8TS U2684 ( .A(n5580), .B(n3726), .Y(n2890) );
NAND2X8TS U2685 ( .A(n2921), .B(n5084), .Y(n2915) );
NOR2X8TS U2686 ( .A(n1830), .B(n2603), .Y(n3108) );
NAND2X8TS U2687 ( .A(n2601), .B(n2602), .Y(n1830) );
NAND2X8TS U2688 ( .A(n3240), .B(Raw_mant_NRM_SWR[25]), .Y(n4281) );
BUFX20TS U2689 ( .A(n3123), .Y(n3125) );
OAI2BB1X4TS U2690 ( .A0N(n5051), .A1N(n4659), .B0(n4117), .Y(n3083) );
MXI2X4TS U2691 ( .A(n2349), .B(n5445), .S0(n4997), .Y(n1168) );
BUFX20TS U2692 ( .A(n2114), .Y(n4863) );
NAND2BX4TS U2693 ( .AN(n2445), .B(n4110), .Y(n2956) );
NOR2X6TS U2694 ( .A(n3318), .B(n2292), .Y(n3556) );
NAND2X6TS U2695 ( .A(n3100), .B(n3099), .Y(n3098) );
NOR2X8TS U2696 ( .A(n3103), .B(n1831), .Y(n5255) );
AND4X8TS U2697 ( .A(n1832), .B(n4902), .C(n4285), .D(n4284), .Y(n2483) );
OR3X6TS U2698 ( .A(n2277), .B(n2265), .C(n4392), .Y(n1540) );
NOR2X8TS U2699 ( .A(n1833), .B(n3065), .Y(n5257) );
OAI2BB1X4TS U2700 ( .A0N(n5139), .A1N(n5158), .B0(n4650), .Y(n1833) );
NOR2X4TS U2701 ( .A(n3329), .B(DMP_EXP_EWSW[52]), .Y(n5311) );
XNOR2X4TS U2702 ( .A(n2488), .B(DmP_mant_SFG_SWR[23]), .Y(n3385) );
INVX12TS U2703 ( .A(n3128), .Y(n2636) );
BUFX6TS U2704 ( .A(n2937), .Y(n2916) );
INVX2TS U2705 ( .A(n5283), .Y(n1835) );
BUFX20TS U2706 ( .A(n2334), .Y(n2653) );
BUFX20TS U2707 ( .A(n3125), .Y(n1836) );
BUFX20TS U2708 ( .A(n4790), .Y(n1837) );
BUFX20TS U2709 ( .A(n3087), .Y(n1838) );
NAND2X2TS U2710 ( .A(n2963), .B(intDY_EWSW[52]), .Y(n4362) );
NAND2X2TS U2711 ( .A(n4430), .B(intDY_EWSW[58]), .Y(n4359) );
NAND2X2TS U2712 ( .A(n3587), .B(n2024), .Y(n4872) );
NAND2X2TS U2713 ( .A(n1836), .B(n2050), .Y(n4411) );
NAND2X4TS U2714 ( .A(n2963), .B(intDY_EWSW[13]), .Y(n4079) );
BUFX20TS U2715 ( .A(n4431), .Y(n2049) );
BUFX20TS U2716 ( .A(n2114), .Y(n4877) );
OR2X6TS U2717 ( .A(n2936), .B(n3988), .Y(n2285) );
OR2X6TS U2718 ( .A(n2936), .B(n3988), .Y(n2286) );
AND2X4TS U2719 ( .A(n3748), .B(n3264), .Y(n3263) );
INVX12TS U2720 ( .A(n3264), .Y(n4268) );
NAND2X4TS U2721 ( .A(n3122), .B(n4586), .Y(n3121) );
NAND2X2TS U2722 ( .A(n4807), .B(intDX_EWSW[24]), .Y(n4414) );
NAND2X8TS U2723 ( .A(n2344), .B(DMP_SFG[14]), .Y(n5316) );
NAND2X6TS U2724 ( .A(n3270), .B(n5279), .Y(n2344) );
NAND2X2TS U2725 ( .A(n4425), .B(intDX_EWSW[37]), .Y(n3632) );
NAND2X4TS U2726 ( .A(n2336), .B(n4998), .Y(n2756) );
XOR2X4TS U2727 ( .A(n3408), .B(n1841), .Y(n3409) );
AOI2BB2X4TS U2728 ( .B0(n1842), .B1(n1843), .A0N(n1844), .A1N(n1845), .Y(
n3854) );
NOR2X8TS U2729 ( .A(n3193), .B(n3192), .Y(n2870) );
NAND4X6TS U2730 ( .A(n3188), .B(n2476), .C(n3187), .D(n3194), .Y(n3193) );
CLKINVX6TS U2731 ( .A(n2866), .Y(n2865) );
NAND2X6TS U2732 ( .A(n2977), .B(n3797), .Y(n2853) );
OAI22X2TS U2733 ( .A0(n1916), .A1(n5288), .B0(n5287), .B1(n5507), .Y(n1056)
);
OAI21X2TS U2734 ( .A0(n5288), .A1(n5218), .B0(n2953), .Y(n1017) );
OAI2BB2X2TS U2735 ( .B0(n2232), .B1(n2151), .A0N(n2221), .A1N(n2222), .Y(
n4299) );
AND2X8TS U2736 ( .A(n3793), .B(n3735), .Y(n1849) );
NAND3X6TS U2737 ( .A(n3684), .B(n3685), .C(n3683), .Y(n1230) );
NAND2X8TS U2738 ( .A(n1850), .B(n3850), .Y(n5037) );
INVX16TS U2739 ( .A(n2492), .Y(n1851) );
INVX4TS U2740 ( .A(n1856), .Y(n1857) );
NAND2X8TS U2741 ( .A(n2983), .B(n3771), .Y(n3248) );
NAND2X4TS U2742 ( .A(n3846), .B(n5047), .Y(n3100) );
NAND3X4TS U2743 ( .A(n1910), .B(n5164), .C(n4017), .Y(n3129) );
NOR3X8TS U2744 ( .A(n2620), .B(n2618), .C(n3781), .Y(n2967) );
NAND4BX4TS U2745 ( .AN(n4036), .B(n4035), .C(n4034), .D(n6170), .Y(n1859) );
NAND4BX2TS U2746 ( .AN(n4036), .B(n4035), .C(n4034), .D(n6170), .Y(n5022) );
NAND4X8TS U2747 ( .A(n3216), .B(n3212), .C(n3215), .D(n2386), .Y(n2466) );
MX2X4TS U2748 ( .A(n4745), .B(Raw_mant_NRM_SWR[23]), .S0(n5089), .Y(n1175)
);
AND2X8TS U2749 ( .A(n4249), .B(n2935), .Y(n3034) );
NOR3X4TS U2750 ( .A(n3747), .B(Raw_mant_NRM_SWR[23]), .C(
Raw_mant_NRM_SWR[19]), .Y(n3749) );
NAND2X8TS U2751 ( .A(n2915), .B(n2279), .Y(n3182) );
NAND2X6TS U2752 ( .A(n2636), .B(n2635), .Y(n2470) );
CLKINVX12TS U2753 ( .A(Raw_mant_NRM_SWR[50]), .Y(n2056) );
BUFX12TS U2754 ( .A(n4790), .Y(n4379) );
AOI21X2TS U2755 ( .A0(n2019), .A1(n6205), .B0(n5011), .Y(n6407) );
OAI21X4TS U2756 ( .A0(n5073), .A1(n5076), .B0(n5077), .Y(n2289) );
OAI21X2TS U2757 ( .A0(n5073), .A1(n5076), .B0(n5077), .Y(n5082) );
NAND2X8TS U2758 ( .A(n3381), .B(n5064), .Y(n2634) );
BUFX20TS U2759 ( .A(n3123), .Y(n3087) );
OR2X8TS U2760 ( .A(n2936), .B(n3988), .Y(n1865) );
AOI22X1TS U2761 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[22]), .B0(n2873), .B1(
n5021), .Y(n6309) );
NAND2X2TS U2762 ( .A(n4412), .B(n2310), .Y(n4377) );
NAND2X2TS U2763 ( .A(n4425), .B(intDX_EWSW[36]), .Y(n3622) );
NAND2X2TS U2764 ( .A(n4379), .B(n2737), .Y(n4404) );
AND2X8TS U2765 ( .A(n4838), .B(n2017), .Y(n2023) );
NAND3X6TS U2766 ( .A(n4029), .B(n4028), .C(n3025), .Y(n5040) );
NOR2X8TS U2767 ( .A(LZD_output_NRM2_EW[2]), .B(n1867), .Y(n1866) );
INVX16TS U2768 ( .A(n5283), .Y(n2494) );
INVX8TS U2769 ( .A(n2657), .Y(n2676) );
INVX16TS U2770 ( .A(n2002), .Y(n3262) );
NAND2X6TS U2771 ( .A(n3262), .B(n2621), .Y(n3195) );
NAND3X4TS U2772 ( .A(n4296), .B(n4295), .C(n4294), .Y(n4297) );
AOI22X4TS U2773 ( .A0(n5693), .A1(n5692), .B0(n5691), .B1(n2153), .Y(n4030)
);
BUFX12TS U2774 ( .A(n2114), .Y(n4873) );
BUFX20TS U2775 ( .A(n5227), .Y(n1868) );
MXI2X4TS U2776 ( .A(n5380), .B(n5471), .S0(n5227), .Y(n1429) );
MXI2X4TS U2777 ( .A(n5379), .B(n5483), .S0(n5227), .Y(n1426) );
MXI2X4TS U2778 ( .A(n5382), .B(n5475), .S0(n5227), .Y(n1435) );
MXI2X4TS U2779 ( .A(n5384), .B(n5472), .S0(n5227), .Y(n1441) );
BUFX20TS U2780 ( .A(n2764), .Y(n5227) );
NAND2X2TS U2781 ( .A(n4425), .B(intDX_EWSW[25]), .Y(n4428) );
NAND2X2TS U2782 ( .A(n4412), .B(intDY_EWSW[4]), .Y(n4115) );
NAND2X2TS U2783 ( .A(n1837), .B(intDY_EWSW[0]), .Y(n4381) );
NAND2X2TS U2784 ( .A(n1837), .B(n2295), .Y(n4866) );
NAND2X2TS U2785 ( .A(n2116), .B(intDY_EWSW[57]), .Y(n4788) );
NAND2X2TS U2786 ( .A(n4600), .B(shift_value_SHT2_EWR[4]), .Y(n1958) );
NAND2X6TS U2787 ( .A(n1917), .B(n1869), .Y(n4039) );
INVX16TS U2788 ( .A(n1870), .Y(n1871) );
INVX4TS U2789 ( .A(n1870), .Y(n1872) );
NAND2X2TS U2790 ( .A(n1837), .B(intDX_EWSW[23]), .Y(n4407) );
CLKINVX12TS U2791 ( .A(n4488), .Y(n1874) );
INVX16TS U2792 ( .A(n2559), .Y(n1875) );
NOR2X4TS U2793 ( .A(n3540), .B(n2863), .Y(n2862) );
INVX2TS U2794 ( .A(n2751), .Y(n3777) );
NOR2X6TS U2795 ( .A(Raw_mant_NRM_SWR[48]), .B(Raw_mant_NRM_SWR[47]), .Y(
n3787) );
NAND2BX2TS U2796 ( .AN(n6089), .B(n2407), .Y(n2695) );
XNOR2X2TS U2797 ( .A(intDX_EWSW[28]), .B(n2745), .Y(n4191) );
NAND2X2TS U2798 ( .A(n5023), .B(n2780), .Y(n2108) );
NAND2X2TS U2799 ( .A(n2261), .B(n4620), .Y(n3965) );
XNOR2X1TS U2800 ( .A(intDX_EWSW[11]), .B(intDY_EWSW[11]), .Y(n4219) );
NOR2BX2TS U2801 ( .AN(shift_value_SHT2_EWR[4]), .B(n2331), .Y(n4487) );
NOR2X1TS U2802 ( .A(n4752), .B(n4755), .Y(n4758) );
NOR2X4TS U2803 ( .A(n2111), .B(n4266), .Y(n2110) );
OA22X2TS U2804 ( .A0(n6010), .A1(n6009), .B0(n6008), .B1(n6007), .Y(n3930)
);
INVX2TS U2805 ( .A(n4585), .Y(n2030) );
NAND2X2TS U2806 ( .A(n2262), .B(n5018), .Y(n3974) );
NAND2X1TS U2807 ( .A(n4141), .B(n3287), .Y(n3286) );
NAND2X1TS U2808 ( .A(n3296), .B(n3870), .Y(n2363) );
NAND2X2TS U2809 ( .A(n5835), .B(n2162), .Y(n3933) );
AND2X2TS U2810 ( .A(n4923), .B(n4921), .Y(n2364) );
OAI21X2TS U2811 ( .A0(n5096), .A1(n5095), .B0(n5094), .Y(n5099) );
AOI22X2TS U2812 ( .A0(n4618), .A1(n2519), .B0(n5143), .B1(n2517), .Y(n2775)
);
NAND2X1TS U2813 ( .A(n3087), .B(intDX_EWSW[19]), .Y(n4859) );
INVX4TS U2814 ( .A(DmP_mant_SFG_SWR[28]), .Y(n2758) );
NAND2X1TS U2815 ( .A(n5271), .B(DmP_mant_SFG_SWR[25]), .Y(n3101) );
CLKBUFX2TS U2816 ( .A(intDY_EWSW[15]), .Y(n2035) );
NAND2X2TS U2817 ( .A(n2530), .B(intDY_EWSW[48]), .Y(n4391) );
CLKBUFX2TS U2818 ( .A(intDY_EWSW[43]), .Y(n2051) );
NOR2X1TS U2819 ( .A(n2449), .B(n1916), .Y(n6462) );
AND2X8TS U2820 ( .A(n3296), .B(n3872), .Y(n1895) );
AND3X6TS U2821 ( .A(n3218), .B(n3272), .C(n3396), .Y(n1896) );
AND2X4TS U2822 ( .A(n2262), .B(n5047), .Y(n1897) );
NOR2X6TS U2823 ( .A(n2885), .B(n2884), .Y(n2883) );
OR4X2TS U2824 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[40]), .C(n5345), .D(n5029), .Y(n1904) );
AND2X8TS U2825 ( .A(n3738), .B(n4270), .Y(n1905) );
OR2X8TS U2826 ( .A(n6353), .B(n4070), .Y(n1906) );
NOR2X4TS U2827 ( .A(n3394), .B(DMP_SFG[34]), .Y(n4915) );
OA21X4TS U2828 ( .A0(n4891), .A1(n5424), .B0(n4890), .Y(n1908) );
OR2X8TS U2829 ( .A(n2034), .B(n2403), .Y(n1909) );
XNOR2X4TS U2830 ( .A(n2285), .B(n4013), .Y(n1910) );
OR2X6TS U2831 ( .A(n3992), .B(n5166), .Y(n1911) );
NAND2X6TS U2832 ( .A(n3378), .B(DMP_SFG[13]), .Y(n5279) );
CLKINVX12TS U2833 ( .A(Raw_mant_NRM_SWR[45]), .Y(n1912) );
INVX16TS U2834 ( .A(n1912), .Y(n1913) );
NAND2X2TS U2835 ( .A(n4877), .B(n2051), .Y(n3585) );
NAND2X2TS U2836 ( .A(n4369), .B(intDY_EWSW[13]), .Y(n3814) );
NAND2X2TS U2837 ( .A(n4877), .B(intDX_EWSW[1]), .Y(n4875) );
NAND2X2TS U2838 ( .A(n4369), .B(intDX_EWSW[44]), .Y(n3610) );
NAND2X2TS U2839 ( .A(n4877), .B(intDX_EWSW[41]), .Y(n3601) );
INVX4TS U2840 ( .A(n4263), .Y(n2113) );
INVX4TS U2841 ( .A(n2023), .Y(n4109) );
INVX3TS U2842 ( .A(n4946), .Y(n2121) );
INVX3TS U2843 ( .A(n3171), .Y(n3170) );
OAI21X2TS U2844 ( .A0(n2432), .A1(n3887), .B0(n2659), .Y(n2658) );
AND2X6TS U2845 ( .A(n3090), .B(n3089), .Y(n2424) );
INVX2TS U2846 ( .A(n4137), .Y(n3169) );
NAND2X2TS U2847 ( .A(n3887), .B(n4021), .Y(n2659) );
NAND2X4TS U2848 ( .A(n1967), .B(n1968), .Y(n1966) );
INVX6TS U2849 ( .A(n5023), .Y(n4661) );
INVX2TS U2850 ( .A(n4645), .Y(n2283) );
NOR2X4TS U2851 ( .A(n4958), .B(n3207), .Y(n4769) );
INVX8TS U2852 ( .A(n5191), .Y(n3157) );
NAND2X2TS U2853 ( .A(n4473), .B(n4707), .Y(n4045) );
INVX4TS U2854 ( .A(n3906), .Y(n1964) );
BUFX12TS U2855 ( .A(n5233), .Y(n5235) );
BUFX8TS U2856 ( .A(n5034), .Y(n1917) );
BUFX12TS U2857 ( .A(n5233), .Y(n5253) );
BUFX12TS U2858 ( .A(n5233), .Y(n5236) );
AND2X2TS U2859 ( .A(n4985), .B(n4984), .Y(n2356) );
BUFX12TS U2860 ( .A(n5233), .Y(n5258) );
BUFX8TS U2861 ( .A(n2764), .Y(n5216) );
BUFX20TS U2862 ( .A(n5259), .Y(n2764) );
BUFX8TS U2863 ( .A(n5259), .Y(n5159) );
NAND2X2TS U2864 ( .A(n2261), .B(Data_array_SWR_3__53_), .Y(n3869) );
BUFX8TS U2865 ( .A(n5259), .Y(n5271) );
BUFX8TS U2866 ( .A(n5259), .Y(n5224) );
OR2X4TS U2867 ( .A(n3706), .B(n2096), .Y(n5013) );
NAND2X2TS U2868 ( .A(n1919), .B(n4518), .Y(n4091) );
BUFX8TS U2869 ( .A(n5259), .Y(n5245) );
AND2X2TS U2870 ( .A(n3912), .B(n3911), .Y(n2367) );
NAND2X1TS U2871 ( .A(n2513), .B(LZD_output_NRM2_EW[3]), .Y(n3196) );
INVX2TS U2872 ( .A(n4747), .Y(n4737) );
BUFX6TS U2873 ( .A(n5234), .Y(n5233) );
NAND2X1TS U2874 ( .A(n4396), .B(DMP_EXP_EWSW[42]), .Y(n3612) );
NAND2X1TS U2875 ( .A(n4864), .B(DmP_EXP_EWSW[7]), .Y(n3819) );
NAND2X1TS U2876 ( .A(n4426), .B(DMP_EXP_EWSW[24]), .Y(n4413) );
NAND2X1TS U2877 ( .A(n4864), .B(DmP_EXP_EWSW[46]), .Y(n4096) );
NAND2X1TS U2878 ( .A(n4426), .B(DMP_EXP_EWSW[23]), .Y(n4406) );
NAND2X1TS U2879 ( .A(n4864), .B(DmP_EXP_EWSW[10]), .Y(n4313) );
NAND2X1TS U2880 ( .A(n4426), .B(DMP_EXP_EWSW[29]), .Y(n3649) );
INVX2TS U2881 ( .A(n4994), .Y(n3134) );
NAND2X1TS U2882 ( .A(n4997), .B(Raw_mant_NRM_SWR[37]), .Y(n2931) );
INVX2TS U2883 ( .A(n5095), .Y(n5091) );
NAND2X1TS U2884 ( .A(n5089), .B(Raw_mant_NRM_SWR[46]), .Y(n2954) );
INVX2TS U2885 ( .A(n2228), .Y(n3927) );
NAND2X1TS U2886 ( .A(n4396), .B(DMP_EXP_EWSW[49]), .Y(n4393) );
NAND2X1TS U2887 ( .A(n4853), .B(DmP_EXP_EWSW[31]), .Y(n4817) );
NAND2X1TS U2888 ( .A(n4396), .B(DMP_EXP_EWSW[51]), .Y(n4397) );
NAND2X1TS U2889 ( .A(n4853), .B(DmP_EXP_EWSW[30]), .Y(n4792) );
NAND2X1TS U2890 ( .A(n4417), .B(DMP_EXP_EWSW[0]), .Y(n4383) );
NAND2X1TS U2891 ( .A(n4853), .B(DmP_EXP_EWSW[24]), .Y(n4831) );
NAND2X1TS U2892 ( .A(n4853), .B(DmP_EXP_EWSW[37]), .Y(n4820) );
INVX2TS U2893 ( .A(n4138), .Y(n4140) );
NAND2X1TS U2894 ( .A(n4853), .B(DmP_EXP_EWSW[32]), .Y(n4804) );
NAND2X6TS U2895 ( .A(n3516), .B(n3563), .Y(n3566) );
NAND2X1TS U2896 ( .A(n4396), .B(DMP_EXP_EWSW[45]), .Y(n3603) );
NAND2X1TS U2897 ( .A(n4396), .B(DMP_EXP_EWSW[46]), .Y(n3594) );
NAND4BBX2TS U2898 ( .AN(n2796), .BN(n5926), .C(n6156), .D(n2067), .Y(n2066)
);
NAND2X1TS U2899 ( .A(n4853), .B(DmP_EXP_EWSW[33]), .Y(n4801) );
NAND2X1TS U2900 ( .A(n4853), .B(DmP_EXP_EWSW[36]), .Y(n4814) );
NAND2X4TS U2901 ( .A(n3385), .B(DMP_SFG[21]), .Y(n4742) );
INVX8TS U2902 ( .A(n5200), .Y(n5202) );
INVX8TS U2903 ( .A(n5200), .Y(n5203) );
NAND2X1TS U2904 ( .A(n2535), .B(DMP_EXP_EWSW[1]), .Y(n4874) );
INVX8TS U2905 ( .A(n5200), .Y(n5194) );
NAND2X1TS U2906 ( .A(n2535), .B(DMP_EXP_EWSW[12]), .Y(n4440) );
NAND2BX2TS U2907 ( .AN(n3860), .B(n3859), .Y(n1943) );
INVX16TS U2908 ( .A(n5101), .Y(n2562) );
INVX4TS U2909 ( .A(n4248), .Y(n3191) );
NAND2X2TS U2910 ( .A(n2095), .B(n1898), .Y(n2090) );
MXI2X2TS U2911 ( .A(n5494), .B(inst_FSM_INPUT_ENABLE_state_reg[1]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n4579) );
NAND2X1TS U2912 ( .A(n2214), .B(n2144), .Y(n5189) );
NAND2X1TS U2913 ( .A(n2214), .B(n2145), .Y(n5186) );
CLKBUFX2TS U2914 ( .A(Shift_amount_SHT1_EWR[5]), .Y(n2570) );
INVX2TS U2915 ( .A(n6182), .Y(n1988) );
INVX4TS U2916 ( .A(n2257), .Y(n2258) );
INVX8TS U2917 ( .A(Raw_mant_NRM_SWR[33]), .Y(n2062) );
BUFX8TS U2918 ( .A(left_right_SHT2), .Y(n2559) );
INVX2TS U2919 ( .A(n2156), .Y(n2094) );
INVX2TS U2920 ( .A(n6011), .Y(n2095) );
INVX2TS U2921 ( .A(n5552), .Y(n2021) );
INVX12TS U2922 ( .A(n3261), .Y(n2523) );
NAND2X4TS U2923 ( .A(n3197), .B(n3196), .Y(n1125) );
NAND2X4TS U2924 ( .A(n4881), .B(n2561), .Y(n3197) );
NAND4X6TS U2925 ( .A(n2272), .B(n2113), .C(n4352), .D(n2110), .Y(n4881) );
NAND3X2TS U2926 ( .A(n4428), .B(n4429), .C(n4427), .Y(n1562) );
NAND3X2TS U2927 ( .A(n4867), .B(n4866), .C(n4865), .Y(n1300) );
NAND3X2TS U2928 ( .A(n4859), .B(n4858), .C(n4857), .Y(n1272) );
NAND2X4TS U2929 ( .A(n2112), .B(n4262), .Y(n2111) );
NOR2X4TS U2930 ( .A(n2732), .B(n3892), .Y(n2731) );
NAND2X2TS U2931 ( .A(n2877), .B(n2874), .Y(n1097) );
INVX3TS U2932 ( .A(n3181), .Y(n3914) );
NAND2X4TS U2933 ( .A(n4885), .B(n5490), .Y(n2112) );
NAND2X4TS U2934 ( .A(n3144), .B(n2828), .Y(n1031) );
NOR2X4TS U2935 ( .A(n3171), .B(n3169), .Y(n3168) );
MX2X2TS U2936 ( .A(n4739), .B(Raw_mant_NRM_SWR[25]), .S0(n5089), .Y(n1173)
);
NAND2X4TS U2937 ( .A(n2733), .B(n2734), .Y(n2732) );
NAND2BX2TS U2938 ( .AN(n5490), .B(n4337), .Y(n2894) );
NAND2X4TS U2939 ( .A(n3105), .B(n3104), .Y(n3103) );
NAND2X4TS U2940 ( .A(n2785), .B(n3911), .Y(n3181) );
NOR2X4TS U2941 ( .A(n1961), .B(n1960), .Y(n1959) );
AND2X4TS U2942 ( .A(n4943), .B(n3017), .Y(n2321) );
NOR2X4TS U2943 ( .A(n2882), .B(n1936), .Y(n1935) );
NAND2X4TS U2944 ( .A(n1970), .B(n1964), .Y(n3273) );
NAND2X4TS U2945 ( .A(n6457), .B(n5161), .Y(n2939) );
NOR2X4TS U2946 ( .A(n2069), .B(n4703), .Y(n2068) );
OR2X4TS U2947 ( .A(n4137), .B(n3286), .Y(n2439) );
NAND2X4TS U2948 ( .A(n3067), .B(n3066), .Y(n3065) );
NAND2X6TS U2949 ( .A(n1966), .B(n1965), .Y(n1970) );
NAND3X4TS U2950 ( .A(n2820), .B(n2817), .C(n2816), .Y(n2815) );
NAND2X4TS U2951 ( .A(n2631), .B(n2630), .Y(n2629) );
NAND2X4TS U2952 ( .A(n4608), .B(n1872), .Y(n2801) );
NAND2X4TS U2953 ( .A(n2578), .B(n4121), .Y(n2577) );
INVX2TS U2954 ( .A(n4772), .Y(n4764) );
NOR2X4TS U2955 ( .A(n2072), .B(n2071), .Y(n2070) );
NOR2X4TS U2956 ( .A(n2819), .B(n2818), .Y(n2817) );
AND2X4TS U2957 ( .A(n3217), .B(n2728), .Y(n2727) );
NOR2X6TS U2958 ( .A(n3906), .B(n3900), .Y(n4240) );
INVX2TS U2959 ( .A(n5274), .Y(n2264) );
AOI21X2TS U2960 ( .A0(n3272), .A1(n2759), .B0(n2959), .Y(n4782) );
NAND2X4TS U2961 ( .A(n2086), .B(n2085), .Y(n2084) );
CLKMX2X2TS U2962 ( .A(Data_Y[48]), .B(intDY_EWSW[48]), .S0(n5253), .Y(n1680)
);
INVX4TS U2963 ( .A(n3284), .Y(n3283) );
AND2X4TS U2964 ( .A(n3964), .B(n3966), .Y(n2802) );
INVX2TS U2965 ( .A(n2519), .Y(n3160) );
NAND2X2TS U2966 ( .A(n5216), .B(n2923), .Y(n2922) );
AND2X4TS U2967 ( .A(n4064), .B(n4065), .Y(n3044) );
NAND2X4TS U2968 ( .A(n1645), .B(n4637), .Y(n2085) );
NAND2X4TS U2969 ( .A(n3886), .B(n4018), .Y(n3900) );
CLKMX2X2TS U2970 ( .A(Data_X[46]), .B(intDX_EWSW[46]), .S0(n5238), .Y(n1748)
);
CLKMX2X2TS U2971 ( .A(Data_X[39]), .B(n2028), .S0(n5239), .Y(n1755) );
NAND3X6TS U2972 ( .A(n3723), .B(n3724), .C(n3722), .Y(n4645) );
BUFX12TS U2973 ( .A(n5217), .Y(n5240) );
BUFX12TS U2974 ( .A(n5242), .Y(n5237) );
BUFX12TS U2975 ( .A(n5217), .Y(n5238) );
NOR2X4TS U2976 ( .A(n3881), .B(n5002), .Y(n3893) );
INVX2TS U2977 ( .A(n3227), .Y(n3226) );
CLKMX2X2TS U2978 ( .A(Data_Y[10]), .B(n2048), .S0(n4531), .Y(n1718) );
CLKMX2X2TS U2979 ( .A(Data_Y[14]), .B(n2024), .S0(n4531), .Y(n1714) );
CLKMX2X2TS U2980 ( .A(Data_Y[8]), .B(intDY_EWSW[8]), .S0(n4531), .Y(n1720)
);
CLKMX2X2TS U2981 ( .A(Data_Y[9]), .B(n2050), .S0(n4531), .Y(n1719) );
INVX2TS U2982 ( .A(n4349), .Y(n2898) );
BUFX16TS U2983 ( .A(n4332), .Y(n5061) );
INVX6TS U2984 ( .A(n4332), .Y(n2873) );
CLKMX2X3TS U2985 ( .A(add_subt), .B(intAS), .S0(n5242), .Y(n1730) );
INVX6TS U2986 ( .A(n4332), .Y(n6228) );
NOR2X4TS U2987 ( .A(n1973), .B(n4019), .Y(n3886) );
NAND2X4TS U2988 ( .A(n3401), .B(n4988), .Y(n3255) );
BUFX8TS U2989 ( .A(n4332), .Y(n6231) );
AND2X2TS U2990 ( .A(n4334), .B(Raw_mant_NRM_SWR[0]), .Y(n2986) );
INVX6TS U2991 ( .A(n4018), .Y(n2663) );
BUFX8TS U2992 ( .A(n5234), .Y(n5252) );
NOR2X4TS U2993 ( .A(n2593), .B(n2592), .Y(n2596) );
CLKMX2X2TS U2994 ( .A(DmP_mant_SHT1_SW[8]), .B(n2312), .S0(n5207), .Y(n1293)
);
CLKMX2X2TS U2995 ( .A(DmP_mant_SHT1_SW[2]), .B(DmP_EXP_EWSW[2]), .S0(n5207),
.Y(n1305) );
CLKMX2X2TS U2996 ( .A(DmP_mant_SHT1_SW[51]), .B(DmP_EXP_EWSW[51]), .S0(n5213), .Y(n1207) );
CLKMX2X2TS U2997 ( .A(DmP_mant_SHT1_SW[37]), .B(DmP_EXP_EWSW[37]), .S0(n5204), .Y(n1235) );
CLKMX2X2TS U2998 ( .A(DmP_mant_SHT1_SW[26]), .B(DmP_EXP_EWSW[26]), .S0(n5204), .Y(n1257) );
INVX2TS U2999 ( .A(n4932), .Y(n4933) );
AND2X2TS U3000 ( .A(n3017), .B(n4944), .Y(n4916) );
BUFX8TS U3001 ( .A(n3365), .Y(n5145) );
BUFX4TS U3002 ( .A(n2289), .Y(n2924) );
BUFX8TS U3003 ( .A(n5259), .Y(n5265) );
BUFX12TS U3004 ( .A(n5259), .Y(n5191) );
INVX2TS U3005 ( .A(n4999), .Y(n3891) );
AND2X2TS U3006 ( .A(n1921), .B(n4978), .Y(n4966) );
AND2X2TS U3007 ( .A(n5004), .B(n5003), .Y(n2338) );
AND2X2TS U3008 ( .A(n3069), .B(n4955), .Y(n2337) );
MX2X1TS U3009 ( .A(Data_X[62]), .B(intDX_EWSW[62]), .S0(n5234), .Y(n1732) );
BUFX12TS U3010 ( .A(n3062), .Y(n5155) );
MX2X1TS U3011 ( .A(Data_Y[62]), .B(intDY_EWSW[62]), .S0(n5234), .Y(n1666) );
BUFX8TS U3012 ( .A(n5234), .Y(n5239) );
BUFX12TS U3013 ( .A(n5234), .Y(n5242) );
BUFX8TS U3014 ( .A(n3062), .Y(n5158) );
BUFX8TS U3015 ( .A(n5234), .Y(n4531) );
NOR2X4TS U3016 ( .A(n3143), .B(n3140), .Y(n3139) );
NOR2X4TS U3017 ( .A(n2823), .B(n2822), .Y(n2821) );
BUFX8TS U3018 ( .A(n5234), .Y(n5241) );
NAND4X6TS U3019 ( .A(n1926), .B(n6059), .C(n1930), .D(n1927), .Y(n5034) );
NAND2X1TS U3020 ( .A(n3652), .B(n2123), .Y(n3591) );
NAND2X1TS U3021 ( .A(n4417), .B(n2122), .Y(n3606) );
INVX2TS U3022 ( .A(n2558), .Y(n2606) );
INVX2TS U3023 ( .A(n5094), .Y(n5066) );
INVX6TS U3024 ( .A(n4915), .Y(n3017) );
AND2X2TS U3025 ( .A(n4417), .B(DmP_EXP_EWSW[51]), .Y(n2445) );
NAND2X1TS U3026 ( .A(n5089), .B(n1986), .Y(n3208) );
INVX8TS U3027 ( .A(n5200), .Y(n5204) );
INVX2TS U3028 ( .A(n3883), .Y(n3884) );
INVX8TS U3029 ( .A(n4997), .Y(n5208) );
NAND2BX1TS U3030 ( .AN(n5504), .B(n5571), .Y(n2991) );
AND2X2TS U3031 ( .A(n4864), .B(DmP_EXP_EWSW[16]), .Y(n2446) );
INVX8TS U3032 ( .A(n5200), .Y(n5211) );
AND2X2TS U3033 ( .A(n4417), .B(DmP_EXP_EWSW[48]), .Y(n2447) );
INVX8TS U3034 ( .A(n5200), .Y(n5213) );
INVX8TS U3035 ( .A(n5200), .Y(n5206) );
INVX8TS U3036 ( .A(n5200), .Y(n5207) );
NAND2X1TS U3037 ( .A(n2244), .B(n2145), .Y(n4467) );
NAND2X1TS U3038 ( .A(n2244), .B(n2149), .Y(n5190) );
NAND2X1TS U3039 ( .A(n2244), .B(n2144), .Y(n5185) );
INVX8TS U3040 ( .A(n5284), .Y(n5198) );
INVX8TS U3041 ( .A(n5284), .Y(n5199) );
NAND2X1TS U3042 ( .A(n6293), .B(SIGN_FLAG_SHT1SHT2), .Y(n3119) );
NAND2X4TS U3043 ( .A(n2599), .B(n2598), .Y(n3822) );
INVX2TS U3044 ( .A(n1876), .Y(n1936) );
AND4X6TS U3045 ( .A(n3957), .B(n3956), .C(n3955), .D(n3954), .Y(n2266) );
NAND2BX2TS U3046 ( .AN(n6014), .B(n2092), .Y(n2091) );
NOR2X4TS U3047 ( .A(n4042), .B(n3076), .Y(n2920) );
BUFX8TS U3048 ( .A(n2993), .Y(n2522) );
INVX16TS U3049 ( .A(n5101), .Y(n2561) );
INVX8TS U3050 ( .A(n5244), .Y(n5196) );
INVX8TS U3051 ( .A(n5244), .Y(n5195) );
NAND2X4TS U3052 ( .A(n3386), .B(DMP_SFG[22]), .Y(n4759) );
INVX3TS U3053 ( .A(n3762), .Y(n3773) );
NAND2X4TS U3054 ( .A(n3875), .B(DMP_SFG[44]), .Y(n3911) );
INVX8TS U3055 ( .A(n5244), .Y(busy) );
INVX8TS U3056 ( .A(n5200), .Y(n5201) );
INVX8TS U3057 ( .A(n2546), .Y(n2547) );
NAND2X4TS U3058 ( .A(n3399), .B(DMP_SFG[38]), .Y(n4994) );
INVX8TS U3059 ( .A(n5284), .Y(n5197) );
NAND2X4TS U3060 ( .A(n5833), .B(n5832), .Y(n2698) );
NAND2X4TS U3061 ( .A(n2130), .B(n5687), .Y(n2697) );
INVX2TS U3062 ( .A(n6013), .Y(n2092) );
NOR2X4TS U3063 ( .A(n6033), .B(n6032), .Y(n1928) );
NAND2X4TS U3064 ( .A(n6057), .B(n6058), .Y(n1929) );
AND2X4TS U3065 ( .A(n5780), .B(n5779), .Y(n1931) );
NAND3X1TS U3066 ( .A(n6169), .B(n6168), .C(n6167), .Y(final_result_ieee[15])
);
NAND2X1TS U3067 ( .A(n2211), .B(n5830), .Y(n5187) );
NAND2X8TS U3068 ( .A(n2384), .B(n3366), .Y(n3797) );
NAND2X1TS U3069 ( .A(n2211), .B(n2149), .Y(n5188) );
INVX8TS U3070 ( .A(Shift_reg_FLAGS_7_6), .Y(n4791) );
CLKAND2X2TS U3071 ( .A(n6053), .B(n2135), .Y(n4298) );
OR2X2TS U3072 ( .A(n5496), .B(DMP_EXP_EWSW[57]), .Y(n3407) );
INVX8TS U3073 ( .A(n5596), .Y(n2546) );
NAND2X4TS U3074 ( .A(n5964), .B(n5963), .Y(n2598) );
INVX2TS U3075 ( .A(n6077), .Y(n2223) );
INVX2TS U3076 ( .A(n6076), .Y(n2224) );
INVX2TS U3077 ( .A(intDX_EWSW[63]), .Y(n4229) );
INVX12TS U3078 ( .A(Shift_reg_FLAGS_7_5), .Y(n5200) );
INVX6TS U3079 ( .A(n5596), .Y(n5209) );
BUFX20TS U3080 ( .A(Shift_reg_FLAGS_7[0]), .Y(n6293) );
NOR2X4TS U3081 ( .A(Raw_mant_NRM_SWR[26]), .B(Raw_mant_NRM_SWR[6]), .Y(n2919) );
INVX6TS U3082 ( .A(n5596), .Y(n5210) );
BUFX8TS U3083 ( .A(n3336), .Y(n1987) );
INVX4TS U3084 ( .A(n2300), .Y(n2301) );
INVX2TS U3085 ( .A(n2252), .Y(n2253) );
NAND2X4TS U3086 ( .A(n3348), .B(intDY_EWSW[24]), .Y(n3484) );
INVX3TS U3087 ( .A(DmP_mant_SFG_SWR[15]), .Y(n2333) );
INVX8TS U3088 ( .A(Raw_mant_NRM_SWR[42]), .Y(n6216) );
BUFX8TS U3089 ( .A(n5493), .Y(n5244) );
NAND2X6TS U3090 ( .A(n2016), .B(n2946), .Y(n4025) );
NAND2X6TS U3091 ( .A(n4306), .B(n4305), .Y(n4321) );
NOR2X4TS U3092 ( .A(n2421), .B(n2970), .Y(n6332) );
INVX8TS U3093 ( .A(n3239), .Y(n6396) );
NAND2X4TS U3094 ( .A(n4881), .B(n2562), .Y(n4883) );
NAND2X4TS U3095 ( .A(n2713), .B(n3268), .Y(n3899) );
NAND2X4TS U3096 ( .A(n2756), .B(n2755), .Y(n2754) );
MX2X2TS U3097 ( .A(n5321), .B(n2307), .S0(n2513), .Y(n1130) );
NAND2X4TS U3098 ( .A(n3283), .B(n3168), .Y(n3167) );
NAND2X4TS U3099 ( .A(n2336), .B(n3910), .Y(n2713) );
NAND2X4TS U3100 ( .A(n4888), .B(n4903), .Y(n2073) );
BUFX20TS U3101 ( .A(n2470), .Y(n1916) );
MX2X2TS U3102 ( .A(n4762), .B(n2300), .S0(n5005), .Y(n1174) );
MX2X2TS U3103 ( .A(n5081), .B(Raw_mant_NRM_SWR[21]), .S0(n4997), .Y(n1177)
);
NAND2X4TS U3104 ( .A(n3158), .B(n3157), .Y(n3156) );
NAND2X6TS U3105 ( .A(n3281), .B(n3893), .Y(n2733) );
NAND2X4TS U3106 ( .A(n4495), .B(n4494), .Y(n1137) );
NAND3X6TS U3107 ( .A(n1940), .B(n1939), .C(n1938), .Y(n1937) );
MX2X2TS U3108 ( .A(n4736), .B(n2252), .S0(n2550), .Y(n1178) );
NOR2X6TS U3109 ( .A(n3042), .B(n2047), .Y(n5261) );
NAND2X4TS U3110 ( .A(n2703), .B(n2575), .Y(n2574) );
NAND2X6TS U3111 ( .A(n3273), .B(n3905), .Y(n4243) );
NAND3X6TS U3112 ( .A(n4688), .B(n4687), .C(n2638), .Y(n6459) );
OAI2BB1X2TS U3113 ( .A0N(n5161), .A1N(n6461), .B0(n5134), .Y(n1113) );
NAND4X4TS U3114 ( .A(n3163), .B(n3162), .C(n3161), .D(n3159), .Y(n3158) );
NOR2X4TS U3115 ( .A(n2879), .B(n2878), .Y(n2877) );
AND2X4TS U3116 ( .A(n4634), .B(n2472), .Y(n2471) );
MX2X4TS U3117 ( .A(n6463), .B(n5560), .S0(n5159), .Y(n5137) );
MX2X4TS U3118 ( .A(n6418), .B(n4130), .S0(n5264), .Y(n4131) );
MX2X2TS U3119 ( .A(n5093), .B(Raw_mant_NRM_SWR[17]), .S0(n5005), .Y(n1181)
);
MX2X2TS U3120 ( .A(n6458), .B(n5562), .S0(n5265), .Y(n5144) );
NAND2X4TS U3121 ( .A(n2884), .B(n1877), .Y(n1938) );
NAND2X6TS U3122 ( .A(n2786), .B(n4020), .Y(n3913) );
INVX8TS U3123 ( .A(n1970), .Y(n3907) );
NAND4X4TS U3124 ( .A(n4727), .B(n4726), .C(n4725), .D(n4724), .Y(n6461) );
INVX8TS U3125 ( .A(n2647), .Y(n2464) );
NAND2X6TS U3126 ( .A(n3887), .B(n3269), .Y(n2786) );
NAND2X6TS U3127 ( .A(n4597), .B(n2083), .Y(n4649) );
INVX3TS U3128 ( .A(n2419), .Y(n2882) );
CLKMX2X2TS U3129 ( .A(n6431), .B(n5565), .S0(n5232), .Y(n5156) );
XOR2X2TS U3130 ( .A(n5096), .B(n5092), .Y(n5093) );
CLKBUFX3TS U3131 ( .A(n4461), .Y(n5643) );
MX2X4TS U3132 ( .A(n6438), .B(n5568), .S0(n5159), .Y(n5146) );
NAND2X4TS U3133 ( .A(n2632), .B(n5030), .Y(n2631) );
NAND2X2TS U3134 ( .A(n4628), .B(n4627), .Y(n4629) );
AND2X4TS U3135 ( .A(n3893), .B(n4998), .Y(n2401) );
NAND2X4TS U3136 ( .A(n4607), .B(n4609), .Y(n2047) );
BUFX12TS U3137 ( .A(n5135), .Y(n2022) );
AND3X6TS U3138 ( .A(n4693), .B(n4695), .C(n2437), .Y(n2829) );
XNOR2X1TS U3139 ( .A(n5318), .B(n5317), .Y(n5320) );
NAND2X4TS U3140 ( .A(n4998), .B(n4136), .Y(n4137) );
OA21X4TS U3141 ( .A0(n4962), .A1(n4783), .B0(n4782), .Y(n5325) );
NAND2X4TS U3142 ( .A(n4472), .B(n3372), .Y(n4476) );
MXI2X2TS U3143 ( .A(n5455), .B(n5352), .S0(n2505), .Y(n1501) );
MXI2X2TS U3144 ( .A(n5457), .B(n5354), .S0(n2505), .Y(n1492) );
MXI2X2TS U3145 ( .A(n5458), .B(n5355), .S0(n2505), .Y(n1489) );
MXI2X2TS U3146 ( .A(n5453), .B(n5351), .S0(n2505), .Y(n1513) );
MXI2X2TS U3147 ( .A(n5451), .B(n5349), .S0(n2505), .Y(n1486) );
INVX4TS U3148 ( .A(n3194), .Y(n2979) );
NAND3X6TS U3149 ( .A(n1971), .B(n1972), .C(n4020), .Y(n1968) );
INVX8TS U3150 ( .A(n4709), .Y(n1944) );
OA22X2TS U3151 ( .A0(n3832), .A1(n4654), .B0(n4716), .B1(n4653), .Y(n4655)
);
NAND2X6TS U3152 ( .A(n2425), .B(n4519), .Y(n5135) );
INVX6TS U3153 ( .A(n4722), .Y(n2552) );
NAND2X1TS U3154 ( .A(n2341), .B(n5316), .Y(n5318) );
MXI2X2TS U3155 ( .A(n5362), .B(n5512), .S0(n2505), .Y(n1510) );
MXI2X2TS U3156 ( .A(n5361), .B(n5511), .S0(n2505), .Y(n1519) );
CLKMX2X2TS U3157 ( .A(Data_Y[30]), .B(intDY_EWSW[30]), .S0(n5236), .Y(n1698)
);
CLKMX2X2TS U3158 ( .A(Data_Y[23]), .B(n1984), .S0(n5258), .Y(n1705) );
CLKMX2X2TS U3159 ( .A(Data_Y[58]), .B(intDY_EWSW[58]), .S0(n5252), .Y(n1670)
);
CLKMX2X2TS U3160 ( .A(Data_Y[54]), .B(intDY_EWSW[54]), .S0(n5253), .Y(n1674)
);
CLKMX2X2TS U3161 ( .A(Data_Y[40]), .B(intDY_EWSW[40]), .S0(n5235), .Y(n1688)
);
INVX12TS U3162 ( .A(n3157), .Y(n2505) );
CLKMX2X2TS U3163 ( .A(Data_Y[39]), .B(intDY_EWSW[39]), .S0(n5235), .Y(n1689)
);
CLKMX2X2TS U3164 ( .A(Data_X[27]), .B(intDX_EWSW[27]), .S0(n5237), .Y(n1767)
);
CLKMX2X2TS U3165 ( .A(Data_X[26]), .B(intDX_EWSW[26]), .S0(n5237), .Y(n1768)
);
CLKMX2X2TS U3166 ( .A(Data_X[5]), .B(intDX_EWSW[5]), .S0(n5241), .Y(n1789)
);
CLKMX2X2TS U3167 ( .A(Data_Y[47]), .B(n2045), .S0(n5253), .Y(n1681) );
MX2X2TS U3168 ( .A(Data_X[32]), .B(intDX_EWSW[32]), .S0(n5237), .Y(n1762) );
CLKMX2X2TS U3169 ( .A(Data_Y[27]), .B(n2964), .S0(n5236), .Y(n1701) );
CLKMX2X2TS U3170 ( .A(Data_X[31]), .B(intDX_EWSW[31]), .S0(n5237), .Y(n1763)
);
CLKMX2X2TS U3171 ( .A(Data_X[30]), .B(intDX_EWSW[30]), .S0(n5237), .Y(n1764)
);
CLKMX2X2TS U3172 ( .A(Data_X[28]), .B(intDX_EWSW[28]), .S0(n5237), .Y(n1766)
);
CLKMX2X2TS U3173 ( .A(Data_X[29]), .B(intDX_EWSW[29]), .S0(n5237), .Y(n1765)
);
CLKMX2X2TS U3174 ( .A(Data_Y[52]), .B(intDY_EWSW[52]), .S0(n5253), .Y(n1676)
);
CLKMX2X2TS U3175 ( .A(Data_Y[59]), .B(intDY_EWSW[59]), .S0(n5252), .Y(n1669)
);
CLKMX2X2TS U3176 ( .A(Data_X[50]), .B(intDX_EWSW[50]), .S0(n5238), .Y(n1744)
);
CLKMX2X2TS U3177 ( .A(Data_X[49]), .B(intDX_EWSW[49]), .S0(n5238), .Y(n1745)
);
CLKMX2X2TS U3178 ( .A(Data_X[48]), .B(intDX_EWSW[48]), .S0(n5238), .Y(n1746)
);
CLKMX2X2TS U3179 ( .A(Data_Y[20]), .B(intDY_EWSW[20]), .S0(n5258), .Y(n1708)
);
CLKMX2X2TS U3180 ( .A(Data_X[51]), .B(intDX_EWSW[51]), .S0(n5238), .Y(n1743)
);
CLKMX2X2TS U3181 ( .A(Data_X[47]), .B(intDX_EWSW[47]), .S0(n5238), .Y(n1747)
);
AND2X4TS U3182 ( .A(n4084), .B(n4083), .Y(n1946) );
CLKMX2X2TS U3183 ( .A(Data_Y[22]), .B(n2036), .S0(n5258), .Y(n1706) );
CLKMX2X2TS U3184 ( .A(Data_Y[60]), .B(intDY_EWSW[60]), .S0(n5252), .Y(n1668)
);
CLKMX2X2TS U3185 ( .A(Data_X[52]), .B(intDX_EWSW[52]), .S0(n5238), .Y(n1742)
);
CLKMX2X2TS U3186 ( .A(Data_X[45]), .B(intDX_EWSW[45]), .S0(n5238), .Y(n1749)
);
CLKMX2X2TS U3187 ( .A(Data_X[44]), .B(intDX_EWSW[44]), .S0(n5238), .Y(n1750)
);
CLKMX2X2TS U3188 ( .A(Data_Y[18]), .B(n2025), .S0(n5258), .Y(n1710) );
CLKMX2X2TS U3189 ( .A(Data_X[53]), .B(intDX_EWSW[53]), .S0(n5238), .Y(n1741)
);
CLKMX2X2TS U3190 ( .A(Data_Y[43]), .B(n2051), .S0(n5235), .Y(n1685) );
CLKMX2X2TS U3191 ( .A(Data_Y[28]), .B(n2745), .S0(n5236), .Y(n1700) );
CLKMX2X2TS U3192 ( .A(Data_Y[44]), .B(intDY_EWSW[44]), .S0(n5235), .Y(n1684)
);
MXI2X2TS U3193 ( .A(n5456), .B(n5353), .S0(n5227), .Y(n1504) );
CLKMX2X2TS U3194 ( .A(Data_Y[24]), .B(intDY_EWSW[24]), .S0(n5258), .Y(n1704)
);
CLKMX2X2TS U3195 ( .A(Data_Y[41]), .B(n2026), .S0(n5235), .Y(n1687) );
CLKMX2X2TS U3196 ( .A(Data_X[7]), .B(intDX_EWSW[7]), .S0(n5241), .Y(n1787)
);
CLKMX2X2TS U3197 ( .A(Data_Y[26]), .B(n2046), .S0(n5236), .Y(n1702) );
NAND2X4TS U3198 ( .A(n3469), .B(n3504), .Y(n3014) );
CLKMX2X2TS U3199 ( .A(Data_Y[29]), .B(intDY_EWSW[29]), .S0(n5236), .Y(n1699)
);
NAND2X4TS U3200 ( .A(n4656), .B(n4658), .Y(n2086) );
CLKMX2X2TS U3201 ( .A(Data_Y[46]), .B(n1922), .S0(n5253), .Y(n1682) );
CLKMX2X2TS U3202 ( .A(Data_X[12]), .B(intDX_EWSW[12]), .S0(n5241), .Y(n1782)
);
CLKMX2X2TS U3203 ( .A(Data_Y[33]), .B(n2945), .S0(n5236), .Y(n1695) );
CLKMX2X2TS U3204 ( .A(Data_Y[35]), .B(n2940), .S0(n5236), .Y(n1693) );
CLKMX2X2TS U3205 ( .A(Data_X[4]), .B(intDX_EWSW[4]), .S0(n5241), .Y(n1790)
);
NAND2BX2TS U3206 ( .AN(n2898), .B(n2851), .Y(n2897) );
CLKMX2X2TS U3207 ( .A(Data_Y[34]), .B(n2740), .S0(n5236), .Y(n1694) );
CLKMX2X2TS U3208 ( .A(Data_X[0]), .B(intDX_EWSW[0]), .S0(n5252), .Y(n1794)
);
CLKMX2X2TS U3209 ( .A(Data_X[10]), .B(intDX_EWSW[10]), .S0(n5241), .Y(n1784)
);
CLKMX2X2TS U3210 ( .A(Data_X[3]), .B(intDX_EWSW[3]), .S0(n5252), .Y(n1791)
);
CLKMX2X2TS U3211 ( .A(Data_X[8]), .B(intDX_EWSW[8]), .S0(n5241), .Y(n1786)
);
CLKMX2X2TS U3212 ( .A(Data_X[1]), .B(intDX_EWSW[1]), .S0(n5252), .Y(n1793)
);
NAND2X6TS U3213 ( .A(n4060), .B(n4059), .Y(n5150) );
CLKMX2X2TS U3214 ( .A(Data_X[2]), .B(intDX_EWSW[2]), .S0(n5252), .Y(n1792)
);
CLKMX2X2TS U3215 ( .A(Data_X[20]), .B(intDX_EWSW[20]), .S0(n5240), .Y(n1774)
);
CLKMX2X2TS U3216 ( .A(Data_Y[36]), .B(intDY_EWSW[36]), .S0(n5235), .Y(n1692)
);
CLKMX2X2TS U3217 ( .A(Data_X[19]), .B(intDX_EWSW[19]), .S0(n5240), .Y(n1775)
);
CLKMX2X2TS U3218 ( .A(Data_Y[56]), .B(intDY_EWSW[56]), .S0(n5252), .Y(n1672)
);
CLKMX2X2TS U3219 ( .A(Data_X[6]), .B(intDX_EWSW[6]), .S0(n5241), .Y(n1788)
);
CLKMX2X2TS U3220 ( .A(Data_X[21]), .B(intDX_EWSW[21]), .S0(n5240), .Y(n1773)
);
CLKMX2X2TS U3221 ( .A(Data_Y[50]), .B(intDY_EWSW[50]), .S0(n5253), .Y(n1678)
);
CLKMX2X2TS U3222 ( .A(Data_X[22]), .B(intDX_EWSW[22]), .S0(n5240), .Y(n1772)
);
CLKMX2X2TS U3223 ( .A(Data_X[18]), .B(intDX_EWSW[18]), .S0(n5240), .Y(n1776)
);
CLKMX2X2TS U3224 ( .A(Data_X[17]), .B(intDX_EWSW[17]), .S0(n5240), .Y(n1777)
);
CLKMX2X2TS U3225 ( .A(Data_Y[31]), .B(n2961), .S0(n5236), .Y(n1697) );
CLKMX2X2TS U3226 ( .A(Data_Y[37]), .B(intDY_EWSW[37]), .S0(n5235), .Y(n1691)
);
CLKMX2X2TS U3227 ( .A(Data_X[23]), .B(intDX_EWSW[23]), .S0(n5240), .Y(n1771)
);
CLKMX2X2TS U3228 ( .A(Data_X[16]), .B(intDX_EWSW[16]), .S0(n5240), .Y(n1778)
);
CLKMX2X2TS U3229 ( .A(Data_Y[51]), .B(n2017), .S0(n5253), .Y(n1677) );
CLKMX2X2TS U3230 ( .A(Data_X[25]), .B(intDX_EWSW[25]), .S0(n5237), .Y(n1769)
);
OAI2BB1X1TS U3231 ( .A0N(OP_FLAG_EXP), .A1N(n2535), .B0(n5162), .Y(n1524) );
CLKMX2X2TS U3232 ( .A(Data_X[9]), .B(intDX_EWSW[9]), .S0(n5241), .Y(n1785)
);
CLKMX2X2TS U3233 ( .A(Data_Y[55]), .B(intDY_EWSW[55]), .S0(n5253), .Y(n1673)
);
CLKMX2X2TS U3234 ( .A(Data_X[24]), .B(intDX_EWSW[24]), .S0(n5237), .Y(n1770)
);
CLKMX2X2TS U3235 ( .A(Data_X[15]), .B(intDX_EWSW[15]), .S0(n5240), .Y(n1779)
);
CLKMX2X2TS U3236 ( .A(Data_X[13]), .B(intDX_EWSW[13]), .S0(n5241), .Y(n1781)
);
AND2X2TS U3237 ( .A(n5224), .B(DmP_mant_SFG_SWR[33]), .Y(n2380) );
CLKMX2X2TS U3238 ( .A(Data_X[40]), .B(intDX_EWSW[40]), .S0(n5239), .Y(n1754)
);
CLKMX2X2TS U3239 ( .A(Data_X[38]), .B(intDX_EWSW[38]), .S0(n5239), .Y(n1756)
);
CLKMX2X2TS U3240 ( .A(Data_X[37]), .B(intDX_EWSW[37]), .S0(n5239), .Y(n1757)
);
CLKMX2X2TS U3241 ( .A(Data_X[41]), .B(intDX_EWSW[41]), .S0(n5239), .Y(n1753)
);
CLKMX2X2TS U3242 ( .A(Data_X[36]), .B(intDX_EWSW[36]), .S0(n5239), .Y(n1758)
);
CLKMX2X2TS U3243 ( .A(Data_X[42]), .B(intDX_EWSW[42]), .S0(n5239), .Y(n1752)
);
CLKMX2X3TS U3244 ( .A(Data_Y[0]), .B(intDY_EWSW[0]), .S0(n5242), .Y(n1728)
);
CLKMX2X3TS U3245 ( .A(Data_Y[63]), .B(intDY_EWSW[63]), .S0(n5242), .Y(n1665)
);
INVX2TS U3246 ( .A(n4767), .Y(n4770) );
INVX8TS U3247 ( .A(n2924), .Y(n4756) );
NAND2X2TS U3248 ( .A(n4226), .B(n4227), .Y(n1924) );
NAND2X6TS U3249 ( .A(n2596), .B(n3847), .Y(n5026) );
INVX2TS U3250 ( .A(n4988), .Y(n4969) );
CLKMX2X2TS U3251 ( .A(Data_X[34]), .B(intDX_EWSW[34]), .S0(n5239), .Y(n1760)
);
CLKMX2X2TS U3252 ( .A(Data_X[35]), .B(intDX_EWSW[35]), .S0(n5239), .Y(n1759)
);
NAND2X2TS U3253 ( .A(DmP_mant_SFG_SWR[43]), .B(n5191), .Y(n2827) );
CLKMX2X3TS U3254 ( .A(Data_Y[4]), .B(intDY_EWSW[4]), .S0(n5242), .Y(n1724)
);
CLKMX2X2TS U3255 ( .A(Data_X[57]), .B(intDX_EWSW[57]), .S0(n5217), .Y(n1737)
);
CLKMX2X2TS U3256 ( .A(Data_X[58]), .B(intDX_EWSW[58]), .S0(n5217), .Y(n1736)
);
CLKMX2X2TS U3257 ( .A(Data_X[59]), .B(intDX_EWSW[59]), .S0(n5217), .Y(n1735)
);
INVX12TS U3258 ( .A(n2393), .Y(n2517) );
INVX12TS U3259 ( .A(n2395), .Y(n2519) );
INVX1TS U3260 ( .A(n4260), .Y(n4261) );
CLKMX2X2TS U3261 ( .A(Data_X[60]), .B(intDX_EWSW[60]), .S0(n5217), .Y(n1734)
);
CLKMX2X2TS U3262 ( .A(Data_Y[12]), .B(n1923), .S0(n4531), .Y(n1716) );
CLKMX2X3TS U3263 ( .A(Data_Y[3]), .B(n2737), .S0(n5242), .Y(n1725) );
INVX2TS U3264 ( .A(n5324), .Y(n2290) );
CLKMX2X2TS U3265 ( .A(Data_X[61]), .B(intDX_EWSW[61]), .S0(n5217), .Y(n1733)
);
CLKMX2X2TS U3266 ( .A(Data_Y[7]), .B(intDY_EWSW[7]), .S0(n4531), .Y(n1721)
);
CLKMX2X2TS U3267 ( .A(Data_X[56]), .B(intDX_EWSW[56]), .S0(n5217), .Y(n1738)
);
CLKMX2X2TS U3268 ( .A(Data_X[54]), .B(intDX_EWSW[54]), .S0(n5217), .Y(n1740)
);
CLKMX2X2TS U3269 ( .A(Data_Y[15]), .B(n2035), .S0(n4531), .Y(n1713) );
CLKMX2X2TS U3270 ( .A(Data_Y[6]), .B(intDY_EWSW[6]), .S0(n4531), .Y(n1722)
);
NAND2X2TS U3271 ( .A(n5091), .B(n2757), .Y(n5068) );
CLKMX2X2TS U3272 ( .A(Data_Y[13]), .B(intDY_EWSW[13]), .S0(n4531), .Y(n1715)
);
CLKMX2X2TS U3273 ( .A(Data_X[55]), .B(intDX_EWSW[55]), .S0(n5217), .Y(n1739)
);
CLKMX2X2TS U3274 ( .A(Data_Y[11]), .B(intDY_EWSW[11]), .S0(n4531), .Y(n1717)
);
NOR2X4TS U3275 ( .A(n2551), .B(n3880), .Y(n3227) );
CLKMX2X2TS U3276 ( .A(DmP_mant_SHT1_SW[47]), .B(n1216), .S0(n5206), .Y(n1215) );
NAND2X2TS U3277 ( .A(n4742), .B(n3295), .Y(n4743) );
NAND2X2TS U3278 ( .A(n3917), .B(n3916), .Y(n3918) );
XNOR2X1TS U3279 ( .A(n5281), .B(n5280), .Y(n5282) );
OR2X6TS U3280 ( .A(n3861), .B(n1943), .Y(n5028) );
CLKMX2X2TS U3281 ( .A(ZERO_FLAG_NRM), .B(ZERO_FLAG_SFG), .S0(n5208), .Y(
n1195) );
BUFX8TS U3282 ( .A(n5259), .Y(n5232) );
BUFX12TS U3283 ( .A(n5234), .Y(n5217) );
NAND2X6TS U3284 ( .A(n2722), .B(DMP_SFG[27]), .Y(n4775) );
CLKMX2X2TS U3285 ( .A(DmP_mant_SHT1_SW[36]), .B(DmP_EXP_EWSW[36]), .S0(n5204), .Y(n1237) );
CLKMX2X2TS U3286 ( .A(DmP_mant_SHT1_SW[46]), .B(DmP_EXP_EWSW[46]), .S0(n5213), .Y(n1217) );
INVX2TS U3287 ( .A(n2760), .Y(n4985) );
MXI2X1TS U3288 ( .A(n2513), .B(n5243), .S0(n5314), .Y(n1795) );
NAND2X6TS U3289 ( .A(n3904), .B(n5000), .Y(n3906) );
CLKINVX2TS U3290 ( .A(n5019), .Y(n4334) );
NAND2X6TS U3291 ( .A(n4711), .B(n2449), .Y(n2395) );
CLKMX2X2TS U3292 ( .A(DmP_mant_SHT1_SW[31]), .B(DmP_EXP_EWSW[31]), .S0(n5204), .Y(n1247) );
NAND2X6TS U3293 ( .A(n3882), .B(n3368), .Y(n1973) );
MXI2X1TS U3294 ( .A(n4580), .B(n2525), .S0(n5314), .Y(n1801) );
MX2X1TS U3295 ( .A(n2040), .B(DMP_exp_NRM_EW[0]), .S0(n2561), .Y(n1361) );
INVX12TS U3296 ( .A(n2266), .Y(n5033) );
INVX12TS U3297 ( .A(n2551), .Y(n3179) );
NAND4BX2TS U3298 ( .AN(n2093), .B(n2097), .C(n2091), .D(n2090), .Y(n2096) );
INVX12TS U3299 ( .A(n2551), .Y(n3232) );
INVX2TS U3300 ( .A(n4978), .Y(n4979) );
NAND2X2TS U3301 ( .A(n2550), .B(n2019), .Y(n3267) );
INVX2TS U3302 ( .A(n4926), .Y(n4928) );
INVX2TS U3303 ( .A(n4921), .Y(n4922) );
INVX6TS U3304 ( .A(n4993), .Y(n4995) );
INVX2TS U3305 ( .A(n5002), .Y(n5004) );
INVX2TS U3306 ( .A(n4955), .Y(n4937) );
AND2X2TS U3307 ( .A(n4853), .B(DmP_EXP_EWSW[22]), .Y(n2282) );
NAND2X1TS U3308 ( .A(n2525), .B(DMP_EXP_EWSW[20]), .Y(n3674) );
NAND2X1TS U3309 ( .A(n4396), .B(n1537), .Y(n4386) );
NOR3X6TS U3310 ( .A(n3251), .B(n3253), .C(n2747), .Y(n3250) );
INVX2TS U3311 ( .A(n3915), .Y(n3917) );
BUFX4TS U3312 ( .A(n5128), .Y(n4555) );
INVX6TS U3313 ( .A(n4948), .Y(n3016) );
BUFX4TS U3314 ( .A(n4551), .Y(n4554) );
INVX2TS U3315 ( .A(n4975), .Y(n3133) );
NAND2X4TS U3316 ( .A(n2594), .B(n6192), .Y(n2593) );
NAND2X1TS U3317 ( .A(n5212), .B(n4470), .Y(n1803) );
INVX2TS U3318 ( .A(n2297), .Y(n2263) );
NOR2X6TS U3319 ( .A(n3969), .B(n2795), .Y(n2794) );
NAND2X6TS U3320 ( .A(n3296), .B(n2389), .Y(n3873) );
AND2X2TS U3321 ( .A(n4396), .B(DMP_EXP_EWSW[47]), .Y(n4392) );
NOR2X4TS U3322 ( .A(n4579), .B(n4578), .Y(n5314) );
INVX16TS U3323 ( .A(n2260), .Y(n1919) );
CLKAND2X2TS U3324 ( .A(n4346), .B(Raw_mant_NRM_SWR[14]), .Y(n2392) );
INVX4TS U3325 ( .A(n3805), .Y(n1950) );
NOR3X6TS U3326 ( .A(n2463), .B(n2462), .C(n2461), .Y(n2460) );
NAND3X4TS U3327 ( .A(n3713), .B(n2824), .C(n2839), .Y(n2823) );
INVX12TS U3328 ( .A(n2549), .Y(n2551) );
AND2X2TS U3329 ( .A(n2534), .B(DmP_EXP_EWSW[17]), .Y(n4852) );
CLKMX2X2TS U3330 ( .A(DmP_mant_SHT1_SW[24]), .B(DmP_EXP_EWSW[24]), .S0(n5210), .Y(n1261) );
NOR3X6TS U3331 ( .A(n2784), .B(n2783), .C(n2782), .Y(n2781) );
CLKMX2X2TS U3332 ( .A(DmP_mant_SHT1_SW[21]), .B(DmP_EXP_EWSW[21]), .S0(n5210), .Y(n1267) );
CLKMX2X2TS U3333 ( .A(DmP_mant_SHT1_SW[18]), .B(n2256), .S0(n5209), .Y(n1273) );
CLKMX2X2TS U3334 ( .A(DmP_mant_SHT1_SW[27]), .B(DmP_EXP_EWSW[27]), .S0(n2546), .Y(n1255) );
BUFX12TS U3335 ( .A(n4917), .Y(n5319) );
BUFX8TS U3336 ( .A(n4791), .Y(n4864) );
BUFX8TS U3337 ( .A(n4791), .Y(n4417) );
INVX6TS U3338 ( .A(n5085), .Y(n1920) );
INVX2TS U3339 ( .A(n3789), .Y(n3791) );
NAND2X6TS U3340 ( .A(n3183), .B(DMP_SFG[15]), .Y(n5094) );
NAND2X6TS U3341 ( .A(n3874), .B(DMP_SFG[43]), .Y(n4020) );
NAND2X6TS U3342 ( .A(n3402), .B(DMP_SFG[40]), .Y(n2373) );
NOR2X2TS U3343 ( .A(n3739), .B(Raw_mant_NRM_SWR[29]), .Y(n2491) );
INVX12TS U3344 ( .A(n5315), .Y(n2524) );
NAND2X1TS U3345 ( .A(n2534), .B(DmP_EXP_EWSW[13]), .Y(n3813) );
BUFX8TS U3346 ( .A(n4791), .Y(n4396) );
INVX12TS U3347 ( .A(n5101), .Y(n2563) );
BUFX8TS U3348 ( .A(n4791), .Y(n3652) );
INVX3TS U3349 ( .A(n3400), .Y(n3184) );
BUFX12TS U3350 ( .A(n4917), .Y(n4997) );
NOR3X6TS U3351 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[13]), .C(
Raw_mant_NRM_SWR[15]), .Y(n2623) );
INVX2TS U3352 ( .A(n2323), .Y(n2324) );
BUFX3TS U3353 ( .A(Shift_amount_SHT1_EWR[3]), .Y(n2565) );
INVX8TS U3354 ( .A(n5446), .Y(n2549) );
INVX2TS U3355 ( .A(n5335), .Y(n5214) );
INVX6TS U3356 ( .A(Shift_reg_FLAGS_7_6), .Y(n2534) );
NOR2X6TS U3357 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n5444), .Y(n4471) );
MX2X1TS U3358 ( .A(DMP_SHT2_EWSW[14]), .B(DMP_SHT1_EWSW[14]), .S0(n2383),
.Y(n1478) );
INVX6TS U3359 ( .A(Raw_mant_NRM_SWR[35]), .Y(n2061) );
NAND2X2TS U3360 ( .A(n5839), .B(n5838), .Y(n3075) );
INVX12TS U3361 ( .A(Shift_reg_FLAGS_7[1]), .Y(n5101) );
NAND2X1TS U3362 ( .A(n2246), .B(n2245), .Y(n6445) );
BUFX4TS U3363 ( .A(intDX_EWSW[39]), .Y(n2028) );
CLKINVX6TS U3364 ( .A(Raw_mant_NRM_SWR[47]), .Y(n2059) );
INVX4TS U3365 ( .A(left_right_SHT2), .Y(n2993) );
NOR2X4TS U3366 ( .A(n5975), .B(n5974), .Y(n2210) );
INVX2TS U3367 ( .A(n5559), .Y(n2923) );
INVX2TS U3368 ( .A(n2449), .Y(n2018) );
XNOR2X2TS U3369 ( .A(n2257), .B(n5547), .Y(n3909) );
MX2X1TS U3370 ( .A(DMP_SHT2_EWSW[62]), .B(DMP_SHT1_EWSW[62]), .S0(n2383),
.Y(n1314) );
INVX2TS U3371 ( .A(DmP_mant_SHT1_SW[34]), .Y(n5612) );
OAI22X2TS U3372 ( .A0(n2182), .A1(n2191), .B0(n6041), .B1(n6040), .Y(n3712)
);
XOR2X2TS U3373 ( .A(n6160), .B(DmP_mant_SFG_SWR[39]), .Y(n3398) );
CLKINVX6TS U3374 ( .A(n2488), .Y(n2489) );
BUFX3TS U3375 ( .A(DmP_mant_SHT1_SW[5]), .Y(n2572) );
INVX2TS U3376 ( .A(DMP_SHT2_EWSW[62]), .Y(n5226) );
INVX2TS U3377 ( .A(DmP_mant_SHT1_SW[15]), .Y(n5607) );
NOR2X4TS U3378 ( .A(n5939), .B(n5938), .Y(n2215) );
BUFX6TS U3379 ( .A(intDY_EWSW[46]), .Y(n1922) );
NAND2X8TS U3380 ( .A(n3220), .B(n2634), .Y(n5084) );
NAND4X2TS U3381 ( .A(n4217), .B(n4216), .C(n4215), .D(n4214), .Y(n4222) );
BUFX6TS U3382 ( .A(intDY_EWSW[12]), .Y(n1923) );
NAND3X4TS U3383 ( .A(n4733), .B(n3124), .C(n4729), .Y(n4233) );
NAND3BX4TS U3384 ( .AN(n1924), .B(n4225), .C(n4228), .Y(n4733) );
MXI2X4TS U3385 ( .A(n5256), .B(n2758), .S0(n5265), .Y(n1042) );
BUFX16TS U3386 ( .A(n3111), .Y(n1925) );
NOR2X8TS U3387 ( .A(shift_value_SHT2_EWR[4]), .B(n2330), .Y(n3111) );
NOR2X8TS U3388 ( .A(n1932), .B(n1931), .Y(n1930) );
OAI2BB1X4TS U3389 ( .A0N(n2198), .A1N(n5778), .B0(n4038), .Y(n1932) );
NOR2BX4TS U3390 ( .AN(n1934), .B(n6031), .Y(n1933) );
INVX2TS U3391 ( .A(n6030), .Y(n1934) );
NAND2X4TS U3392 ( .A(n2885), .B(n1877), .Y(n1940) );
OAI21X4TS U3393 ( .A0(n3320), .A1(n1868), .B0(n2020), .Y(n1026) );
NOR2X8TS U3394 ( .A(n2576), .B(n1941), .Y(n2575) );
OAI21X4TS U3395 ( .A0(n4689), .A1(n1918), .B0(n1942), .Y(n1941) );
AOI22X4TS U3396 ( .A0(n4603), .A1(n1878), .B0(n5145), .B1(n5153), .Y(n5290)
);
NAND4X8TS U3397 ( .A(n1948), .B(n1947), .C(n2960), .D(n1945), .Y(n4603) );
NAND2X8TS U3398 ( .A(n5182), .B(n2330), .Y(n1945) );
NAND2X8TS U3399 ( .A(n4085), .B(n1946), .Y(n5182) );
AOI2BB1X4TS U3400 ( .A0N(n4489), .A1N(n1874), .B0(n2633), .Y(n1947) );
AOI2BB1X4TS U3401 ( .A0N(n4088), .A1N(n4702), .B0(n2629), .Y(n1948) );
BUFX6TS U3402 ( .A(n3111), .Y(n1949) );
INVX16TS U3403 ( .A(n1952), .Y(n3833) );
OR2X8TS U3404 ( .A(n5344), .B(shift_value_SHT2_EWR[2]), .Y(n3805) );
NOR2X8TS U3405 ( .A(n3805), .B(n1953), .Y(n1952) );
NOR2X4TS U3406 ( .A(n3514), .B(n1954), .Y(n3515) );
OAI22X4TS U3407 ( .A0(n2808), .A1(n1954), .B0(intDX_EWSW[57]), .B1(n2371),
.Y(n2807) );
NOR2X8TS U3408 ( .A(n3338), .B(intDY_EWSW[57]), .Y(n1954) );
NOR2X6TS U3409 ( .A(n2860), .B(n1955), .Y(n2859) );
OAI21X4TS U3410 ( .A0(n1955), .A1(n3531), .B0(n3530), .Y(n3537) );
NOR2X8TS U3411 ( .A(n3362), .B(intDY_EWSW[41]), .Y(n1955) );
NOR2X8TS U3412 ( .A(n3512), .B(n1956), .Y(n2684) );
OAI21X4TS U3413 ( .A0(n1956), .A1(n3558), .B0(n3557), .Y(n2681) );
NOR2X8TS U3414 ( .A(n3335), .B(intDY_EWSW[55]), .Y(n1956) );
XOR2X4TS U3415 ( .A(DmP_mant_SFG_SWR[31]), .B(n1854), .Y(n3391) );
INVX12TS U3416 ( .A(n1957), .Y(n3110) );
AOI22X4TS U3417 ( .A0(n5047), .A1(n2558), .B0(n1869), .B1(n5054), .Y(n2704)
);
OAI21X4TS U3418 ( .A0(n3833), .A1(n4678), .B0(n1962), .Y(n1961) );
AOI2BB2X4TS U3419 ( .B0(n2691), .B1(n4691), .A0N(n3832), .A1N(n4675), .Y(
n1962) );
NAND2X8TS U3420 ( .A(n3868), .B(n3869), .Y(n2691) );
NAND2X8TS U3421 ( .A(n3082), .B(n4119), .Y(n5157) );
NOR2X8TS U3422 ( .A(n3902), .B(n5002), .Y(n3904) );
NOR2X6TS U3423 ( .A(n3894), .B(DMP_SFG[50]), .Y(n3902) );
OR2X8TS U3424 ( .A(n3873), .B(n2373), .Y(n1971) );
NOR2X8TS U3425 ( .A(n3871), .B(n1895), .Y(n1972) );
XOR2X4TS U3426 ( .A(DmP_mant_SFG_SWR[46]), .B(n2487), .Y(n3875) );
NAND2X6TS U3427 ( .A(n1975), .B(n1974), .Y(n2913) );
NOR2X4TS U3428 ( .A(n2858), .B(n3548), .Y(n1974) );
NAND2X8TS U3429 ( .A(n2859), .B(n3536), .Y(n2858) );
OAI21X4TS U3430 ( .A0(n1981), .A1(n3529), .B0(n1976), .Y(n1975) );
AOI21X4TS U3431 ( .A0(n1978), .A1(n1980), .B0(n1977), .Y(n1976) );
OAI21X4TS U3432 ( .A0(n3528), .A1(n3527), .B0(n3526), .Y(n1977) );
OAI21X4TS U3433 ( .A0(n2679), .A1(n3525), .B0(n3524), .Y(n1978) );
NAND3X8TS U3434 ( .A(n1900), .B(n1980), .C(n1979), .Y(n3529) );
INVX3TS U3435 ( .A(n2679), .Y(n1979) );
NOR2X8TS U3436 ( .A(n3506), .B(n3528), .Y(n1980) );
AOI21X4TS U3437 ( .A0(n3523), .A1(n1983), .B0(n1982), .Y(n1981) );
OAI21X4TS U3438 ( .A0(n2007), .A1(n3522), .B0(n3521), .Y(n1982) );
OAI21X4TS U3439 ( .A0(n3520), .A1(n2008), .B0(n3519), .Y(n1983) );
BUFX6TS U3440 ( .A(intDY_EWSW[23]), .Y(n1984) );
OR2X8TS U3441 ( .A(n3233), .B(n3189), .Y(n2423) );
AOI22X4TS U3442 ( .A0(n2637), .A1(n2518), .B0(n5143), .B1(n5155), .Y(n6418)
);
NOR3X4TS U3443 ( .A(n1988), .B(n2642), .C(n2641), .Y(n2640) );
OR2X8TS U3444 ( .A(n3405), .B(DMP_SFG[42]), .Y(n3296) );
BUFX16TS U3445 ( .A(n3779), .Y(n1989) );
NOR2X8TS U3446 ( .A(Raw_mant_NRM_SWR[15]), .B(Raw_mant_NRM_SWR[25]), .Y(
n1990) );
INVX16TS U3447 ( .A(n1992), .Y(n3779) );
NOR2X8TS U3448 ( .A(n1998), .B(n1993), .Y(n4029) );
NAND3X6TS U3449 ( .A(n1909), .B(n1995), .C(n1994), .Y(n1993) );
OR2X8TS U3450 ( .A(n1904), .B(n2748), .Y(n1994) );
OAI2BB1X4TS U3451 ( .A0N(n2251), .A1N(n2324), .B0(n3741), .Y(n2000) );
NAND2X6TS U3452 ( .A(n3262), .B(n2749), .Y(n2001) );
NAND3X8TS U3453 ( .A(n3263), .B(n3299), .C(n3749), .Y(n2002) );
NAND2X8TS U3454 ( .A(n1905), .B(n2003), .Y(n2850) );
NAND4X8TS U3455 ( .A(n1905), .B(n2849), .C(n2003), .D(n2851), .Y(n2848) );
AND2X8TS U3456 ( .A(n3727), .B(n3728), .Y(n2003) );
NOR2X8TS U3457 ( .A(Raw_mant_NRM_SWR[21]), .B(Raw_mant_NRM_SWR[22]), .Y(
n3762) );
NOR2X4TS U3458 ( .A(n3337), .B(intDY_EWSW[34]), .Y(n2006) );
NOR2X8TS U3459 ( .A(n3343), .B(intDY_EWSW[35]), .Y(n2007) );
NAND2X4TS U3460 ( .A(n3316), .B(intDY_EWSW[32]), .Y(n2008) );
NOR2X8TS U3461 ( .A(n3334), .B(intDY_EWSW[33]), .Y(n3520) );
NOR2X6TS U3462 ( .A(n2456), .B(n2009), .Y(n3470) );
OAI22X4TS U3463 ( .A0(n2009), .A1(n2455), .B0(intDX_EWSW[19]), .B1(n2372),
.Y(n2454) );
NOR2X8TS U3464 ( .A(n3291), .B(intDY_EWSW[19]), .Y(n2009) );
NAND2X2TS U3465 ( .A(n2526), .B(n2017), .Y(n4399) );
NAND2X2TS U3466 ( .A(n1836), .B(intDY_EWSW[59]), .Y(n3590) );
OAI21X4TS U3467 ( .A0(n2627), .A1(n3426), .B0(n3425), .Y(n3427) );
AND2X8TS U3468 ( .A(n2478), .B(intDX_EWSW[7]), .Y(n2627) );
NAND3X6TS U3469 ( .A(n4444), .B(n4445), .C(n4443), .Y(n1581) );
NAND2X8TS U3470 ( .A(n3202), .B(n2563), .Y(n2985) );
CLKINVX12TS U3471 ( .A(n2013), .Y(n2616) );
AND2X8TS U3472 ( .A(n4425), .B(n2036), .Y(n2280) );
BUFX16TS U3473 ( .A(n2902), .Y(n2846) );
NAND3X8TS U3474 ( .A(n4335), .B(n3772), .C(n5431), .Y(n2013) );
NAND3X6TS U3475 ( .A(n2787), .B(n2788), .C(n3222), .Y(n2336) );
NOR2X8TS U3476 ( .A(n3392), .B(DMP_SFG[30]), .Y(n4965) );
XOR2X4TS U3477 ( .A(DmP_mant_SFG_SWR[32]), .B(n1854), .Y(n3392) );
XOR2X4TS U3478 ( .A(DmP_mant_SFG_SWR[33]), .B(n1852), .Y(n2628) );
AOI22X2TS U3479 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[23]), .B0(n6199), .B1(
DmP_mant_SHT1_SW[26]), .Y(n6306) );
AOI22X2TS U3480 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[12]), .B0(n6199), .B1(
DmP_mant_SHT1_SW[37]), .Y(n6365) );
AOI22X2TS U3481 ( .A0(n6199), .A1(DmP_mant_SHT1_SW[3]), .B0(n2548), .B1(
n2500), .Y(n6325) );
NOR2X8TS U3482 ( .A(n2014), .B(n2063), .Y(n2394) );
NAND3X8TS U3483 ( .A(n2064), .B(n2065), .C(n5442), .Y(n2014) );
NAND2X4TS U3484 ( .A(n3337), .B(intDY_EWSW[34]), .Y(n3522) );
BUFX6TS U3485 ( .A(n5340), .Y(n2015) );
AOI2BB1X4TS U3486 ( .A0N(n3752), .A1N(Raw_mant_NRM_SWR[25]), .B0(
Raw_mant_NRM_SWR[26]), .Y(n2490) );
AOI2BB2X2TS U3487 ( .B0(n5709), .B1(n2193), .A0N(n5708), .A1N(n2141), .Y(
n3929) );
BUFX6TS U3488 ( .A(intDY_EWSW[51]), .Y(n2017) );
NOR2X8TS U3489 ( .A(n3420), .B(n2627), .Y(n3428) );
NAND2X2TS U3490 ( .A(n3587), .B(intDY_EWSW[62]), .Y(n3661) );
CLKINVX12TS U3491 ( .A(Raw_mant_NRM_SWR[48]), .Y(n2057) );
BUFX20TS U3492 ( .A(n4790), .Y(n4425) );
AOI22X1TS U3493 ( .A0(n6206), .A1(n2252), .B0(n5037), .B1(n2873), .Y(n6321)
);
NOR2X8TS U3494 ( .A(n2848), .B(n3750), .Y(n2847) );
NAND2X8TS U3495 ( .A(n2394), .B(n2892), .Y(n3750) );
NAND2X8TS U3496 ( .A(n2033), .B(n3127), .Y(n2635) );
OR2X8TS U3497 ( .A(n3233), .B(n3759), .Y(n3760) );
AND3X6TS U3498 ( .A(n5178), .B(n5172), .C(n4016), .Y(n2944) );
NOR4X2TS U3499 ( .A(n4185), .B(n4184), .C(n4183), .D(n4182), .Y(n4227) );
NAND2X4TS U3500 ( .A(n3362), .B(intDY_EWSW[41]), .Y(n3530) );
NOR2X4TS U3501 ( .A(Raw_mant_NRM_SWR[36]), .B(Raw_mant_NRM_SWR[30]), .Y(
n3729) );
OAI2BB1X4TS U3502 ( .A0N(n5161), .A1N(n6455), .B0(n5130), .Y(n1055) );
OAI22X2TS U3503 ( .A0(n2990), .A1(n5063), .B0(n5287), .B1(n2119), .Y(n1077)
);
AOI22X2TS U3504 ( .A0(n6218), .A1(Raw_mant_NRM_SWR[48]), .B0(n5043), .B1(
n6230), .Y(n6398) );
AOI22X4TS U3505 ( .A0(n5139), .A1(n2519), .B0(n5155), .B1(n5138), .Y(n6420)
);
AOI22X2TS U3506 ( .A0(n6205), .A1(n2012), .B0(n5015), .B1(n5041), .Y(n6395)
);
NAND2X2TS U3507 ( .A(n2529), .B(n5021), .Y(n4638) );
NAND2X2TS U3508 ( .A(n3846), .B(n5025), .Y(n3944) );
AND2X8TS U3509 ( .A(n2320), .B(intDX_EWSW[37]), .Y(n2679) );
OAI22X4TS U3510 ( .A0(n4684), .A1(n2611), .B0(n4709), .B1(n4324), .Y(n3837)
);
NAND2X2TS U3511 ( .A(n3587), .B(n2036), .Y(n3639) );
INVX12TS U3512 ( .A(n3805), .Y(n3846) );
NAND2X4TS U3513 ( .A(n2555), .B(n1644), .Y(n4525) );
NAND4X6TS U3514 ( .A(n4527), .B(n4526), .C(n4525), .D(n4524), .Y(n4633) );
OAI22X4TS U3515 ( .A0(n4617), .A1(n2990), .B0(n5292), .B1(n5545), .Y(n1060)
);
AND2X8TS U3516 ( .A(n4873), .B(intDY_EWSW[17]), .Y(n2271) );
NAND2X4TS U3517 ( .A(n5141), .B(n5147), .Y(n4614) );
NAND2BX4TS U3518 ( .AN(n4266), .B(n4265), .Y(n4288) );
NAND2X4TS U3519 ( .A(n3678), .B(n2305), .Y(n1526) );
NAND2X4TS U3520 ( .A(n1919), .B(n1917), .Y(n4290) );
BUFX6TS U3521 ( .A(intDY_EWSW[14]), .Y(n2024) );
BUFX6TS U3522 ( .A(n3587), .Y(n2027) );
AOI22X1TS U3523 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[52]), .B0(n5020), .B1(
n2873), .Y(n6329) );
NOR2X8TS U3524 ( .A(n2029), .B(n2060), .Y(n2891) );
NAND2X8TS U3525 ( .A(n2058), .B(n2059), .Y(n2029) );
NOR2X8TS U3526 ( .A(Raw_mant_NRM_SWR[53]), .B(n2323), .Y(n3790) );
AND2X8TS U3527 ( .A(n3120), .B(n2030), .Y(n5283) );
BUFX6TS U3528 ( .A(n3339), .Y(n2031) );
NAND3X6TS U3529 ( .A(n4352), .B(n2417), .C(n2377), .Y(n4353) );
NAND2X8TS U3530 ( .A(n4353), .B(n2562), .Y(n4908) );
NAND2X8TS U3531 ( .A(n3132), .B(n5286), .Y(n2937) );
BUFX20TS U3532 ( .A(n4790), .Y(n4412) );
NAND2X1TS U3533 ( .A(n3087), .B(intDX_EWSW[57]), .Y(n4789) );
NOR2X6TS U3534 ( .A(n3118), .B(n3476), .Y(n3478) );
INVX16TS U3535 ( .A(n6217), .Y(n2934) );
NOR2X8TS U3536 ( .A(Raw_mant_NRM_SWR[23]), .B(n2300), .Y(n4335) );
NAND2X8TS U3537 ( .A(n6205), .B(n1913), .Y(n3260) );
NAND3X2TS U3538 ( .A(n4112), .B(n4113), .C(n4111), .Y(n1298) );
MXI2X4TS U3539 ( .A(n2763), .B(n5411), .S0(n5277), .Y(n1199) );
BUFX20TS U3540 ( .A(n3087), .Y(n3630) );
INVX12TS U3541 ( .A(n3175), .Y(n2342) );
AOI22X4TS U3542 ( .A0(n4604), .A1(n2560), .B0(n2691), .B1(n3365), .Y(n4617)
);
NAND2X2TS U3543 ( .A(n4474), .B(n5262), .Y(n4083) );
BUFX6TS U3544 ( .A(intDY_EWSW[22]), .Y(n2036) );
NAND2X8TS U3545 ( .A(n2452), .B(intDX_EWSW[3]), .Y(n4433) );
NAND2X4TS U3546 ( .A(n2049), .B(n2050), .Y(n4317) );
NAND3X4TS U3547 ( .A(n4317), .B(n4318), .C(n4316), .Y(n1292) );
NOR2X6TS U3548 ( .A(n5421), .B(n3350), .Y(n3378) );
NAND2X8TS U3549 ( .A(n5316), .B(n2039), .Y(n5064) );
NAND2X8TS U3550 ( .A(n2341), .B(n5317), .Y(n2039) );
NAND2X8TS U3551 ( .A(n2343), .B(n3270), .Y(n2341) );
NOR4X2TS U3552 ( .A(n4205), .B(n4204), .C(n4203), .D(n4202), .Y(n4226) );
BUFX6TS U3553 ( .A(DMP_exp_NRM2_EW[0]), .Y(n2040) );
NAND2X4TS U3554 ( .A(n4116), .B(n4114), .Y(n2958) );
NAND2X2TS U3555 ( .A(n2963), .B(intDY_EWSW[49]), .Y(n4395) );
BUFX6TS U3556 ( .A(n3550), .Y(n2042) );
CLKINVX6TS U3557 ( .A(n3907), .Y(n3281) );
OR2X8TS U3558 ( .A(n3907), .B(n3897), .Y(n3172) );
NOR2X6TS U3559 ( .A(n3307), .B(intDY_EWSW[30]), .Y(n3464) );
INVX4TS U3560 ( .A(n2440), .Y(n2314) );
NAND3X6TS U3561 ( .A(n2723), .B(n2789), .C(DMP_SFG[26]), .Y(n2675) );
NOR2X6TS U3562 ( .A(n3302), .B(intDY_EWSW[46]), .Y(n2864) );
NAND2X8TS U3563 ( .A(n2802), .B(n2043), .Y(n4608) );
AND2X8TS U3564 ( .A(n3963), .B(n3965), .Y(n2043) );
NAND4BX4TS U3565 ( .AN(n3932), .B(n2799), .C(n2801), .D(n2798), .Y(n4619) );
NAND2X2TS U3566 ( .A(n4699), .B(n3846), .Y(n3964) );
INVX8TS U3567 ( .A(n4920), .Y(n3256) );
AOI21X4TS U3568 ( .A0(n3490), .A1(n3489), .B0(n2044), .Y(n3502) );
OAI21X4TS U3569 ( .A0(n3487), .A1(n3488), .B0(n3486), .Y(n2044) );
AND2X8TS U3570 ( .A(n2302), .B(intDX_EWSW[39]), .Y(n3528) );
NOR2X8TS U3571 ( .A(DMP_exp_NRM2_EW[1]), .B(n2308), .Y(n3980) );
AND2X8TS U3572 ( .A(n4771), .B(n2789), .Y(n4781) );
BUFX6TS U3573 ( .A(intDY_EWSW[47]), .Y(n2045) );
OAI22X2TS U3574 ( .A0(n2453), .A1(n5256), .B0(n5289), .B1(n5536), .Y(n1098)
);
OAI22X2TS U3575 ( .A0(n2453), .A1(n5255), .B0(n5292), .B1(n5533), .Y(n1108)
);
NOR2X8TS U3576 ( .A(n2610), .B(n2609), .Y(n2608) );
BUFX6TS U3577 ( .A(intDY_EWSW[26]), .Y(n2046) );
NAND2X4TS U3578 ( .A(n3303), .B(intDY_EWSW[20]), .Y(n3472) );
OAI22X4TS U3579 ( .A0(n3322), .A1(n1916), .B0(n5292), .B1(n5529), .Y(n1095)
);
XOR2X4TS U3580 ( .A(DmP_mant_SFG_SWR[35]), .B(n1852), .Y(n2842) );
BUFX6TS U3581 ( .A(intDY_EWSW[10]), .Y(n2048) );
BUFX6TS U3582 ( .A(intDY_EWSW[9]), .Y(n2050) );
NOR2X8TS U3583 ( .A(n2274), .B(n3010), .Y(n2273) );
NAND4X8TS U3584 ( .A(n4029), .B(n4028), .C(n4338), .D(n4339), .Y(n3202) );
NOR2X8TS U3585 ( .A(n4340), .B(n2888), .Y(n4028) );
NOR2X8TS U3586 ( .A(n3432), .B(n3450), .Y(n3452) );
OAI21X4TS U3587 ( .A0(n3495), .A1(n3496), .B0(n3494), .Y(n3497) );
AND2X8TS U3588 ( .A(n4838), .B(n2299), .Y(n2275) );
NAND2X2TS U3589 ( .A(n4430), .B(intDY_EWSW[8]), .Y(n4134) );
NAND3X6TS U3590 ( .A(n4133), .B(n4134), .C(n4132), .Y(n1579) );
NAND2X2TS U3591 ( .A(n4430), .B(intDY_EWSW[0]), .Y(n4385) );
NAND2X2TS U3592 ( .A(n1838), .B(n2250), .Y(n4429) );
NAND2X2TS U3593 ( .A(n3587), .B(intDY_EWSW[20]), .Y(n3676) );
NAND3BX4TS U3594 ( .AN(n2275), .B(n4826), .C(n4827), .Y(n1220) );
BUFX20TS U3595 ( .A(n4838), .Y(n2053) );
NAND2X8TS U3596 ( .A(n2053), .B(intDX_EWSW[30]), .Y(n3644) );
NAND2X8TS U3597 ( .A(n2053), .B(intDX_EWSW[32]), .Y(n3647) );
NAND2X8TS U3598 ( .A(n2495), .B(n2300), .Y(n6311) );
NAND2X6TS U3599 ( .A(n2925), .B(Raw_mant_NRM_SWR[11]), .Y(n6360) );
BUFX12TS U3600 ( .A(n2980), .Y(n2054) );
NAND2X6TS U3601 ( .A(n2055), .B(n2980), .Y(n3187) );
NAND2X4TS U3602 ( .A(n3780), .B(n4260), .Y(n2055) );
NAND2X8TS U3603 ( .A(n3734), .B(n2480), .Y(n3265) );
NAND2X8TS U3604 ( .A(n3035), .B(n2980), .Y(n4897) );
INVX16TS U3605 ( .A(n3233), .Y(n2980) );
CLKINVX12TS U3606 ( .A(Raw_mant_NRM_SWR[27]), .Y(n2058) );
NOR2X8TS U3607 ( .A(Raw_mant_NRM_SWR[29]), .B(Raw_mant_NRM_SWR[32]), .Y(
n2064) );
OR2X8TS U3608 ( .A(n2066), .B(n2797), .Y(n4620) );
AOI22X4TS U3609 ( .A0(n4047), .A1(n5927), .B0(n5858), .B1(n2128), .Y(n2067)
);
OAI2BB1X4TS U3610 ( .A0N(n5161), .A1N(n6441), .B0(n5156), .Y(n1050) );
NAND3BX4TS U3611 ( .AN(n4700), .B(n2068), .C(n4705), .Y(n6441) );
OAI21X4TS U3612 ( .A0(n3833), .A1(n5050), .B0(n2070), .Y(n2069) );
OAI22X4TS U3613 ( .A0(n4697), .A1(n4698), .B0(n4706), .B1(n4696), .Y(n2072)
);
OAI2BB1X4TS U3614 ( .A0N(LZD_output_NRM2_EW[5]), .A1N(n2513), .B0(n4905),
.Y(n1141) );
OAI21X4TS U3615 ( .A0(n2074), .A1(n2073), .B0(n2563), .Y(n4905) );
NAND3BX4TS U3616 ( .AN(n2075), .B(n1908), .C(n4889), .Y(n2074) );
INVX16TS U3617 ( .A(n3233), .Y(n2480) );
NAND2X8TS U3618 ( .A(n2480), .B(n2078), .Y(n2742) );
OAI21X4TS U3619 ( .A0(n2079), .A1(n2080), .B0(n2082), .Y(n3091) );
AND3X8TS U3620 ( .A(n2081), .B(n4591), .C(n4590), .Y(n2080) );
NAND2X8TS U3621 ( .A(n4649), .B(n1872), .Y(n2082) );
AOI21X4TS U3622 ( .A0(n5023), .A1(n2261), .B0(n2084), .Y(n2083) );
NAND3X8TS U3623 ( .A(n3695), .B(n3696), .C(n1901), .Y(n1645) );
OAI22X4TS U3624 ( .A0(n5291), .A1(n2088), .B0(n6293), .B1(n5502), .Y(n1058)
);
AOI2BB2X4TS U3625 ( .B0(n5276), .B1(n1877), .A0N(n2263), .A1N(n2264), .Y(
n5291) );
NAND4X8TS U3626 ( .A(n3114), .B(n4655), .C(n3116), .D(n2089), .Y(n5276) );
NOR2BX4TS U3627 ( .AN(n5859), .B(n2094), .Y(n2093) );
AOI22X4TS U3628 ( .A0(n2164), .A1(n5735), .B0(n5736), .B1(n2171), .Y(n2097)
);
NOR2X8TS U3629 ( .A(Raw_mant_NRM_SWR[40]), .B(n2345), .Y(n4270) );
OAI21X4TS U3630 ( .A0(n2099), .A1(n4997), .B0(n2098), .Y(n1159) );
NAND2X1TS U3631 ( .A(n4997), .B(n2345), .Y(n2098) );
XOR2X4TS U3632 ( .A(n4929), .B(n2358), .Y(n2099) );
NAND4BBX4TS U3633 ( .AN(n3704), .BN(n3705), .C(n2101), .D(n2100), .Y(n4496)
);
NOR2X8TS U3634 ( .A(n2107), .B(n2102), .Y(n2101) );
NAND2BX4TS U3635 ( .AN(n4643), .B(n2106), .Y(n2105) );
AOI21X4TS U3636 ( .A0(n2109), .A1(n2108), .B0(n2826), .Y(n2107) );
AOI22X2TS U3637 ( .A0(n1645), .A1(n1950), .B0(n4636), .B1(n4659), .Y(n2109)
);
BUFX20TS U3638 ( .A(n2510), .Y(n2114) );
BUFX20TS U3639 ( .A(n4431), .Y(n2115) );
BUFX20TS U3640 ( .A(n2114), .Y(n2116) );
AND2X8TS U3641 ( .A(n3571), .B(Shift_reg_FLAGS_7_6), .Y(n2510) );
NOR2X8TS U3642 ( .A(n2117), .B(n2042), .Y(n3510) );
NOR2X8TS U3643 ( .A(n3308), .B(intDY_EWSW[49]), .Y(n3550) );
INVX2TS U3644 ( .A(final_result_ieee[45]), .Y(n2119) );
OA21X4TS U3645 ( .A0(n2120), .A1(n2653), .B0(n2121), .Y(n2905) );
AOI22X4TS U3646 ( .A0(n5155), .A1(n5154), .B0(n2517), .B1(n5153), .Y(n6431)
);
NAND4X8TS U3647 ( .A(n4292), .B(n4289), .C(n4290), .D(n4291), .Y(n5154) );
NAND3X8TS U3648 ( .A(n3944), .B(n3942), .C(n2418), .Y(n5143) );
AOI22X2TS U3649 ( .A0(n2637), .A1(n2516), .B0(n5145), .B1(n5143), .Y(n6458)
);
NAND2X2TS U3650 ( .A(n1919), .B(n5016), .Y(n3942) );
NAND2X2TS U3651 ( .A(n4807), .B(intDX_EWSW[20]), .Y(n3675) );
OAI22X2TS U3652 ( .A0(n5876), .A1(n5875), .B0(n2124), .B1(n6158), .Y(n2641)
);
OAI2BB1X4TS U3653 ( .A0N(n5726), .A1N(n5727), .B0(n6120), .Y(n2461) );
NAND2BX4TS U3654 ( .AN(n5928), .B(n5966), .Y(n3054) );
OA22X2TS U3655 ( .A0(n2205), .A1(n2129), .B0(n2178), .B1(n5949), .Y(n3925)
);
NAND2X1TS U3656 ( .A(n5878), .B(n2132), .Y(n4043) );
AOI2BB2X2TS U3657 ( .B0(n5851), .B1(n2132), .A0N(n5850), .A1N(n2184), .Y(
n3719) );
NAND2X1TS U3658 ( .A(n5781), .B(n2137), .Y(n3950) );
NAND2X1TS U3659 ( .A(n5752), .B(n2138), .Y(n3863) );
AOI2BB2X1TS U3660 ( .B0(n5795), .B1(n2138), .A0N(n5794), .A1N(n2150), .Y(
n4594) );
AOI2BB2X1TS U3661 ( .B0(n5951), .B1(n2163), .A0N(n5950), .A1N(n2141), .Y(
n4033) );
NOR2X1TS U3662 ( .A(n5751), .B(n2148), .Y(n3949) );
OAI22X1TS U3663 ( .A0(n6021), .A1(n2148), .B0(n6020), .B1(n6019), .Y(n4051)
);
OAI22X2TS U3664 ( .A0(n6061), .A1(n6060), .B0(n5857), .B1(n2152), .Y(n2797)
);
OA22X4TS U3665 ( .A0(n2231), .A1(n2136), .B0(n2232), .B1(n2157), .Y(n4024)
);
OAI21X1TS U3666 ( .A0(n6116), .A1(n2157), .B0(n6115), .Y(n3947) );
OAI22X2TS U3667 ( .A0(n5936), .A1(n5935), .B0(n5934), .B1(n2158), .Y(n3852)
);
OA22X1TS U3668 ( .A0(n2159), .A1(n5993), .B0(n5992), .B1(n5991), .Y(n3952)
);
AOI2BB2X2TS U3669 ( .B0(n5846), .B1(n5845), .A0N(n5844), .A1N(n2159), .Y(
n4022) );
AND2X2TS U3670 ( .A(n6075), .B(n2160), .Y(n4050) );
AOI22X2TS U3671 ( .A0(n5721), .A1(n5720), .B0(n5719), .B1(n2160), .Y(n3951)
);
AOI22X2TS U3672 ( .A0(n5698), .A1(n2161), .B0(n5697), .B1(n2195), .Y(n3849)
);
OAI2BB2X2TS U3673 ( .B0(n2190), .B1(n6090), .A0N(n2162), .A1N(n5756), .Y(
n2700) );
AOI2BB2X2TS U3674 ( .B0(n5895), .B1(n2165), .A0N(n5894), .A1N(n5893), .Y(
n3945) );
AOI22X2TS U3675 ( .A0(n5897), .A1(n2172), .B0(n5896), .B1(n2166), .Y(n3924)
);
AOI22X2TS U3676 ( .A0(n5968), .A1(n2167), .B0(n5967), .B1(n2194), .Y(n3823)
);
NAND2X4TS U3677 ( .A(n5902), .B(n2168), .Y(n4038) );
AOI21X2TS U3678 ( .A0(n5762), .A1(n2169), .B0(n5761), .Y(n3702) );
NAND2X2TS U3679 ( .A(n5933), .B(n2170), .Y(n3967) );
AOI2BB2X2TS U3680 ( .B0(n5754), .B1(n2193), .A0N(n5753), .A1N(n2175), .Y(
n3701) );
AOI2BB2X4TS U3681 ( .B0(n5853), .B1(n2200), .A0N(n5852), .A1N(n2183), .Y(
n3716) );
OAI22X2TS U3682 ( .A0(n6044), .A1(n2184), .B0(n6043), .B1(n6042), .Y(n3842)
);
AOI2BB2X2TS U3683 ( .B0(n2226), .B1(n2227), .A0N(n2185), .A1N(n2232), .Y(
n3850) );
AOI2BB2X1TS U3684 ( .B0(n5885), .B1(n2193), .A0N(n5884), .A1N(n5883), .Y(
n4032) );
NAND2X2TS U3685 ( .A(n5757), .B(n2196), .Y(n3848) );
AOI22X2TS U3686 ( .A0(n5772), .A1(n2133), .B0(n5771), .B1(n2197), .Y(n3955)
);
NAND2X1TS U3687 ( .A(n5899), .B(n2198), .Y(n3954) );
NAND2X2TS U3688 ( .A(n5865), .B(n2200), .Y(n3970) );
NAND2X4TS U3689 ( .A(n5962), .B(n2202), .Y(n2599) );
OAI2BB1X1TS U3690 ( .A0N(n2203), .A1N(n6101), .B0(n6100), .Y(n4052) );
OAI2BB1X1TS U3691 ( .A0N(n2203), .A1N(n6105), .B0(n6104), .Y(n3861) );
OAI21X4TS U3692 ( .A0(n6126), .A1(n2204), .B0(n6125), .Y(n4036) );
AOI2BB2X2TS U3693 ( .B0(n5775), .B1(n5774), .A0N(n5773), .A1N(n2205), .Y(
n3828) );
OA22X4TS U3694 ( .A0(n2205), .A1(n6024), .B0(n6023), .B1(n6022), .Y(n3708)
);
NAND2X2TS U3695 ( .A(n5866), .B(n2206), .Y(n3935) );
NOR2BX2TS U3696 ( .AN(n5829), .B(n2410), .Y(n3076) );
AOI22X4TS U3697 ( .A0(n2166), .A1(n5955), .B0(n5729), .B1(n5730), .Y(n3001)
);
AOI2BB2X1TS U3698 ( .B0(n5803), .B1(n2213), .A0N(n2208), .A1N(n5802), .Y(
n5107) );
AOI2BB2X1TS U3699 ( .B0(n5817), .B1(n2213), .A0N(n2208), .A1N(n5816), .Y(
n5110) );
AOI21X4TS U3700 ( .A0(n6118), .A1(n2207), .B0(n3923), .Y(n3926) );
OAI2BB1X4TS U3701 ( .A0N(n2201), .A1N(n5738), .B0(n3054), .Y(n3053) );
INVX8TS U3702 ( .A(n3922), .Y(n6203) );
AOI2BB2X1TS U3703 ( .B0(n5801), .B1(n2213), .A0N(n2209), .A1N(n5800), .Y(
n5116) );
AOI21X4TS U3704 ( .A0(n6117), .A1(n2125), .B0(n3822), .Y(n3825) );
AOI22X4TS U3705 ( .A0(n5788), .A1(n5787), .B0(n5786), .B1(n2126), .Y(n3958)
);
AOI22X4TS U3706 ( .A0(n5716), .A1(n5715), .B0(n5714), .B1(n5713), .Y(n3840)
);
AOI21X4TS U3707 ( .A0(n5703), .A1(n2199), .B0(n2210), .Y(n3078) );
AOI2BB2X4TS U3708 ( .B0(n5856), .B1(n2199), .A0N(n5855), .A1N(n2182), .Y(
n3841) );
AOI22X4TS U3709 ( .A0(n5707), .A1(n2126), .B0(n5706), .B1(n2201), .Y(n3698)
);
AOI22X4TS U3710 ( .A0(n5739), .A1(n2133), .B0(n5718), .B1(n2198), .Y(n2585)
);
AOI21X2TS U3711 ( .A0(n5760), .A1(n2206), .B0(n2772), .Y(n2771) );
AOI2BB2X1TS U3712 ( .B0(n5808), .B1(n2213), .A0N(n2212), .A1N(n5807), .Y(
n5109) );
AOI2BB2X1TS U3713 ( .B0(n5805), .B1(n2213), .A0N(n2212), .A1N(n5804), .Y(
n5114) );
AOI2BB2X4TS U3714 ( .B0(n5765), .B1(n5764), .A0N(n5763), .A1N(n2185), .Y(
n3693) );
AOI22X4TS U3715 ( .A0(n2202), .A1(n5694), .B0(n5696), .B1(n5695), .Y(n2643)
);
OAI22X1TS U3716 ( .A0(n6067), .A1(n6066), .B0(n6065), .B1(n6064), .Y(n3860)
);
OAI22X1TS U3717 ( .A0(n6018), .A1(n6017), .B0(n6016), .B1(n6015), .Y(n3826)
);
NOR2BX4TS U3718 ( .AN(n2411), .B(n5952), .Y(n2645) );
OAI2BB1X4TS U3719 ( .A0N(n2130), .A1N(n5702), .B0(n3153), .Y(n3152) );
AOI21X4TS U3720 ( .A0(n5705), .A1(n5704), .B0(n5892), .Y(n3077) );
AOI21X4TS U3721 ( .A0(n6133), .A1(n2197), .B0(n3692), .Y(n3696) );
AO22X4TS U3722 ( .A0(n5961), .A1(n5960), .B0(n5959), .B1(n2202), .Y(n3923)
);
AOI22X4TS U3723 ( .A0(n4047), .A1(n5919), .B0(n5741), .B1(n5740), .Y(n2587)
);
AOI21X4TS U3724 ( .A0(n6124), .A1(n2172), .B0(n3827), .Y(n3830) );
OAI2BB1X4TS U3725 ( .A0N(n2196), .A1N(n5953), .B0(n2643), .Y(n2642) );
AOI21X4TS U3726 ( .A0(n5734), .A1(n2195), .B0(n5827), .Y(n3057) );
AOI22X4TS U3727 ( .A0(n5712), .A1(n2134), .B0(n5711), .B1(n2167), .Y(n3713)
);
AOI2BB2X4TS U3728 ( .B0(n5743), .B1(n2168), .A0N(n5742), .A1N(n2173), .Y(
n3710) );
AOI2BB2X4TS U3729 ( .B0(n5770), .B1(n2170), .A0N(n5769), .A1N(n2190), .Y(
n3714) );
OAI2BB2X4TS U3730 ( .B0(n5901), .B1(n2179), .A0N(n2194), .A1N(n5837), .Y(
n3143) );
OAI21X4TS U3731 ( .A0(n5733), .A1(n2181), .B0(n3057), .Y(n3056) );
NOR2BX4TS U3732 ( .AN(n2142), .B(n5847), .Y(n3138) );
OA22X2TS U3733 ( .A0(n2204), .A1(n2129), .B0(n2179), .B1(n5942), .Y(n3824)
);
NOR2X8TS U3734 ( .A(n2950), .B(n3056), .Y(n3055) );
AOI2BB2X4TS U3735 ( .B0(n5944), .B1(n2125), .A0N(n5943), .A1N(n2152), .Y(
n4034) );
AOI21X4TS U3736 ( .A0(n5836), .A1(n2192), .B0(n2215), .Y(n3141) );
NOR2BX4TS U3737 ( .AN(n2415), .B(n5976), .Y(n2217) );
OAI22X4TS U3738 ( .A0(n5995), .A1(n5994), .B0(n5997), .B1(n5996), .Y(n3154)
);
OA22X4TS U3739 ( .A0(n6004), .A1(n2174), .B0(n6003), .B1(n6002), .Y(n3939)
);
OA22X2TS U3740 ( .A0(n5990), .A1(n5989), .B0(n5988), .B1(n5987), .Y(n3956)
);
INVX4TS U3741 ( .A(n2217), .Y(n2216) );
OAI21X4TS U3742 ( .A0(n5873), .A1(n5872), .B0(n2813), .Y(n2812) );
AOI2BB2X4TS U3743 ( .B0(n4047), .B1(n5915), .A0N(n5914), .A1N(n5913), .Y(
n3694) );
OAI22X1TS U3744 ( .A0(n2175), .A1(n2191), .B0(n6079), .B1(n6078), .Y(n3831)
);
BUFX12TS U3745 ( .A(n5032), .Y(n2498) );
OAI22X4TS U3746 ( .A0(n6055), .A1(n6054), .B0(n5759), .B1(n5758), .Y(n2772)
);
AOI2BB2X1TS U3747 ( .B0(n5783), .B1(n2218), .A0N(n2212), .A1N(n5782), .Y(
n5102) );
AOI2BB2X1TS U3748 ( .B0(n5790), .B1(n2218), .A0N(n2208), .A1N(n5789), .Y(
n5117) );
AOI2BB2X1TS U3749 ( .B0(n5792), .B1(n2218), .A0N(n2209), .A1N(n5791), .Y(
n5121) );
AOI2BB2X1TS U3750 ( .B0(n5797), .B1(n2218), .A0N(n2212), .A1N(n5796), .Y(
n5105) );
AOI2BB2X1TS U3751 ( .B0(n5799), .B1(n2218), .A0N(n2208), .A1N(n5798), .Y(
n5115) );
AOI2BB2X1TS U3752 ( .B0(n5813), .B1(n2218), .A0N(n2209), .A1N(n5812), .Y(
n5112) );
AOI2BB2X1TS U3753 ( .B0(n5815), .B1(n2218), .A0N(n2212), .A1N(n5814), .Y(
n5119) );
AOI2BB2X1TS U3754 ( .B0(n5821), .B1(n2218), .A0N(n2209), .A1N(n5820), .Y(
n5104) );
AOI2BB2X1TS U3755 ( .B0(n5823), .B1(n2218), .A0N(n2209), .A1N(n5822), .Y(
n5108) );
OA22X2TS U3756 ( .A0(n2150), .A1(n5986), .B0(n5985), .B1(n5984), .Y(n3864)
);
NOR2BX4TS U3757 ( .AN(n2177), .B(n5954), .Y(n3004) );
NOR2BX4TS U3758 ( .AN(n2412), .B(n6029), .Y(n2783) );
NOR2BX4TS U3759 ( .AN(n1907), .B(n6056), .Y(n2774) );
NOR2BX4TS U3760 ( .AN(n2180), .B(n6049), .Y(n3050) );
NOR2BX4TS U3761 ( .AN(n2413), .B(n5956), .Y(n2814) );
NAND2X2TS U3762 ( .A(n2555), .B(n1860), .Y(n4295) );
AOI21X4TS U3763 ( .A0(n1860), .A1(n4708), .B0(n4037), .Y(n4058) );
NAND2X2TS U3764 ( .A(n4723), .B(n1859), .Y(n4126) );
NAND2X2TS U3765 ( .A(n2529), .B(n1645), .Y(n3806) );
AND3X4TS U3766 ( .A(n4638), .B(n4640), .C(n4639), .Y(n3147) );
AOI2BB2X4TS U3767 ( .B0(n2229), .B1(n2230), .A0N(n2232), .A1N(n2176), .Y(
n2228) );
BUFX16TS U3768 ( .A(n2233), .Y(n2232) );
OAI21X4TS U3769 ( .A0(n5881), .A1(n5880), .B0(n2234), .Y(n3005) );
OAI21X4TS U3770 ( .A0(n6028), .A1(n6027), .B0(n6177), .Y(n2782) );
NOR2BX4TS U3771 ( .AN(n2414), .B(n6048), .Y(n3051) );
AOI2BB2X2TS U3772 ( .B0(n4047), .B1(n5912), .A0N(n5911), .A1N(n5910), .Y(
n3961) );
OA22X2TS U3773 ( .A0(n2191), .A1(n2140), .B0(n6026), .B1(n6025), .Y(n3968)
);
NOR2BX4TS U3774 ( .AN(n2146), .B(n5717), .Y(n2581) );
NOR2BX4TS U3775 ( .AN(n2139), .B(n5725), .Y(n2463) );
NAND2BX4TS U3776 ( .AN(n5755), .B(n2186), .Y(n2702) );
NOR2X4TS U3777 ( .A(n5767), .B(n2174), .Y(n4042) );
NAND2X1TS U3778 ( .A(n5946), .B(n5945), .Y(n3928) );
NOR2X4TS U3779 ( .A(n4718), .B(n4710), .Y(n2819) );
NAND4X6TS U3780 ( .A(n4129), .B(n4128), .C(n4127), .D(n4126), .Y(n6457) );
OAI2BB1X4TS U3781 ( .A0N(n5828), .A1N(n2161), .B0(n3958), .Y(n2950) );
NAND4X4TS U3782 ( .A(n3929), .B(n3930), .C(n3931), .D(n3928), .Y(n5035) );
NAND2X1TS U3783 ( .A(n5806), .B(n2127), .Y(n3834) );
NAND2X4TS U3784 ( .A(n5860), .B(n2199), .Y(n3938) );
AOI21X4TS U3785 ( .A0(n5898), .A1(n2201), .B0(n2595), .Y(n2594) );
NOR2BX4TS U3786 ( .AN(n2188), .B(n5728), .Y(n3003) );
AOI2BB2X4TS U3787 ( .B0(n5785), .B1(n2135), .A0N(n5784), .A1N(n2151), .Y(
n4087) );
NAND4X1TS U3788 ( .A(n4123), .B(n6108), .C(n6107), .D(n6106), .Y(n5020) );
NAND2X4TS U3789 ( .A(n5701), .B(n2200), .Y(n3153) );
NAND2X1TS U3790 ( .A(n3652), .B(n1553), .Y(n3597) );
NAND2X1TS U3791 ( .A(n3652), .B(n1549), .Y(n3615) );
NAND3X2TS U3792 ( .A(n6445), .B(n5189), .C(n6196), .Y(final_result_ieee[33])
);
NAND2X1TS U3793 ( .A(n2535), .B(n1216), .Y(n3581) );
NAND3X6TS U3794 ( .A(n4433), .B(n4434), .C(n4432), .Y(n1584) );
NAND2X2TS U3795 ( .A(n4369), .B(n2250), .Y(n4855) );
AO21X4TS U3796 ( .A0(n3740), .A1(n5417), .B0(n2019), .Y(n2251) );
NOR2X4TS U3797 ( .A(n3481), .B(n3462), .Y(n3469) );
NOR2X8TS U3798 ( .A(n3501), .B(n3468), .Y(n3504) );
AOI22X2TS U3799 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[38]), .B0(n5041), .B1(
n5017), .Y(n6373) );
AOI22X2TS U3800 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[9]), .B0(n2873), .B1(
n5016), .Y(n6386) );
AOI22X2TS U3801 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[1]), .B0(n5262), .B1(
n5041), .Y(n6352) );
AOI22X2TS U3802 ( .A0(n6205), .A1(n2300), .B0(n6230), .B1(n5026), .Y(n6315)
);
AOI22X2TS U3803 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[3]), .B0(n5018), .B1(
n2873), .Y(n6334) );
AND2X8TS U3804 ( .A(intDX_EWSW[29]), .B(n2254), .Y(n3493) );
NOR2X2TS U3805 ( .A(n4245), .B(n2319), .Y(n4247) );
NAND2X8TS U3806 ( .A(n2750), .B(n4003), .Y(n4015) );
NOR2X4TS U3807 ( .A(n4015), .B(DMP_exp_NRM2_EW[10]), .Y(n4016) );
BUFX20TS U3808 ( .A(n4026), .Y(n6202) );
BUFX20TS U3809 ( .A(n2114), .Y(n4431) );
BUFX16TS U3810 ( .A(n2114), .Y(n4369) );
NAND2X4TS U3811 ( .A(n3376), .B(DMP_exp_NRM2_EW[3]), .Y(n3985) );
NAND2X2TS U3812 ( .A(n4873), .B(n1923), .Y(n3573) );
NAND2X2TS U3813 ( .A(n2116), .B(intDX_EWSW[35]), .Y(n3625) );
AND2X8TS U3814 ( .A(n4838), .B(intDX_EWSW[47]), .Y(n2277) );
NAND2X2TS U3815 ( .A(n4877), .B(intDY_EWSW[38]), .Y(n4100) );
NAND2X2TS U3816 ( .A(n4863), .B(n1984), .Y(n4829) );
NAND2X4TS U3817 ( .A(n2049), .B(intDX_EWSW[13]), .Y(n4078) );
NAND2X8TS U3818 ( .A(n2889), .B(n3787), .Y(n3258) );
AOI21X4TS U3819 ( .A0(n3240), .A1(Raw_mant_NRM_SWR[26]), .B0(n4259), .Y(
n4262) );
BUFX20TS U3820 ( .A(n2054), .Y(n3240) );
NAND3X2TS U3821 ( .A(n3682), .B(n3681), .C(n3680), .Y(n1568) );
BUFX20TS U3822 ( .A(n2502), .Y(n2453) );
INVX16TS U3823 ( .A(n2399), .Y(n2260) );
INVX12TS U3824 ( .A(n2260), .Y(n2261) );
INVX12TS U3825 ( .A(n2260), .Y(n2262) );
NOR2X4TS U3826 ( .A(n5436), .B(shift_value_SHT2_EWR[3]), .Y(n2399) );
NAND2X2TS U3827 ( .A(n2116), .B(intDX_EWSW[11]), .Y(n4143) );
NAND2X4TS U3828 ( .A(n2115), .B(intDX_EWSW[7]), .Y(n4075) );
NAND2X4TS U3829 ( .A(n2115), .B(intDX_EWSW[8]), .Y(n4133) );
INVX12TS U3830 ( .A(n2870), .Y(n2872) );
NAND2X4TS U3831 ( .A(n2115), .B(n2046), .Y(n4841) );
NAND2X4TS U3832 ( .A(n2049), .B(intDX_EWSW[6]), .Y(n4444) );
NAND2BX4TS U3833 ( .AN(n2956), .B(n4109), .Y(n1208) );
NAND2X4TS U3834 ( .A(n5138), .B(n2517), .Y(n3162) );
INVX8TS U3835 ( .A(n6203), .Y(n2507) );
OAI21X2TS U3836 ( .A0(n4631), .A1(n5191), .B0(n2827), .Y(n1027) );
OAI22X2TS U3837 ( .A0(n2990), .A1(n4631), .B0(n5292), .B1(n5540), .Y(n1085)
);
NOR2X6TS U3838 ( .A(n5180), .B(n5172), .Y(n3132) );
NOR2X6TS U3839 ( .A(n3375), .B(DMP_exp_NRM2_EW[2]), .Y(n3984) );
AND2X8TS U3840 ( .A(n4901), .B(Raw_mant_NRM_SWR[6]), .Y(n3200) );
NOR2X6TS U3841 ( .A(n4891), .B(n3191), .Y(n4901) );
NAND2X4TS U3842 ( .A(n4908), .B(n4907), .Y(n1609) );
OR2X8TS U3843 ( .A(intDX_EWSW[8]), .B(n2288), .Y(n2267) );
NAND3X8TS U3844 ( .A(n2616), .B(n3779), .C(n2615), .Y(n2268) );
NAND3X6TS U3845 ( .A(n4390), .B(n4391), .C(n4389), .Y(n1539) );
AOI2BB1X4TS U3846 ( .A0N(n2290), .A1N(n5325), .B0(n2269), .Y(n2656) );
OAI21X2TS U3847 ( .A0(n2334), .A1(n5326), .B0(n5323), .Y(n2269) );
NOR3X2TS U3848 ( .A(n2899), .B(n4340), .C(n2896), .Y(n2895) );
NAND2X4TS U3849 ( .A(n3262), .B(n4345), .Y(n4893) );
NAND3X6TS U3850 ( .A(n4810), .B(n4809), .C(n4808), .Y(n1256) );
NAND3X4TS U3851 ( .A(n4233), .B(n4232), .C(n4231), .Y(n1522) );
NAND2X4TS U3852 ( .A(n4425), .B(intDX_EWSW[63]), .Y(n4232) );
AOI2BB2X4TS U3853 ( .B0(n4488), .B1(n5044), .A0N(n4709), .A1N(n4521), .Y(
n4301) );
OR3X8TS U3854 ( .A(n2270), .B(n2271), .C(n4852), .Y(n1276) );
AND2X4TS U3855 ( .A(n1836), .B(intDX_EWSW[17]), .Y(n2270) );
NAND2X4TS U3856 ( .A(n3428), .B(n3421), .Y(n3430) );
OR2X4TS U3857 ( .A(n3509), .B(n3529), .Y(n2274) );
NAND2X2TS U3858 ( .A(n4369), .B(intDX_EWSW[4]), .Y(n4072) );
NAND2X2TS U3859 ( .A(n4877), .B(intDY_EWSW[24]), .Y(n4832) );
NAND2X4TS U3860 ( .A(n2531), .B(n2025), .Y(n3673) );
BUFX20TS U3861 ( .A(n3087), .Y(n4439) );
NOR2X8TS U3862 ( .A(n3784), .B(n1913), .Y(n3738) );
NAND2X8TS U3863 ( .A(n3737), .B(n3738), .Y(n3765) );
NOR3X4TS U3864 ( .A(n3765), .B(Raw_mant_NRM_SWR[41]), .C(n5029), .Y(n3766)
);
AND3X4TS U3865 ( .A(n3779), .B(n2616), .C(n2615), .Y(n2278) );
BUFX20TS U3866 ( .A(n5046), .Y(n6206) );
NAND2X2TS U3867 ( .A(n4863), .B(intDX_EWSW[27]), .Y(n3657) );
NAND2X2TS U3868 ( .A(n1836), .B(intDY_EWSW[56]), .Y(n4236) );
NAND2X2TS U3869 ( .A(n4430), .B(intDY_EWSW[55]), .Y(n4239) );
NAND2X4TS U3870 ( .A(n2526), .B(n2048), .Y(n4420) );
NAND2X4TS U3871 ( .A(n4416), .B(intDX_EWSW[4]), .Y(n4116) );
OR2X4TS U3872 ( .A(n4342), .B(n5427), .Y(n4284) );
NAND4X6TS U3873 ( .A(n3937), .B(n3936), .C(n6193), .D(n3935), .Y(n5016) );
NAND2X2TS U3874 ( .A(n4877), .B(n2740), .Y(n4796) );
NAND2X2TS U3875 ( .A(n4877), .B(intDY_EWSW[29]), .Y(n4799) );
AOI21X4TS U3876 ( .A0(n2289), .A1(n2406), .B0(n3388), .Y(n2279) );
NAND2X2TS U3877 ( .A(n2116), .B(n2961), .Y(n4818) );
NAND3X2TS U3878 ( .A(n2677), .B(n2401), .C(n2735), .Y(n2726) );
NAND2X2TS U3879 ( .A(n4807), .B(intDX_EWSW[58]), .Y(n4358) );
INVX8TS U3880 ( .A(n2934), .Y(n2553) );
BUFX20TS U3881 ( .A(n4431), .Y(n2951) );
NAND3X4TS U3882 ( .A(n3644), .B(n3645), .C(n3643), .Y(n1557) );
OAI21X4TS U3883 ( .A0(n3280), .A1(n2550), .B0(n3279), .Y(n1149) );
NAND2X4TS U3884 ( .A(n3334), .B(intDY_EWSW[33]), .Y(n3519) );
INVX8TS U3885 ( .A(n2507), .Y(n2506) );
NAND2X2TS U3886 ( .A(n4807), .B(intDY_EWSW[37]), .Y(n4821) );
INVX12TS U3887 ( .A(n3219), .Y(n3244) );
NAND2X2TS U3888 ( .A(n4807), .B(intDY_EWSW[20]), .Y(n4847) );
NAND2X2TS U3889 ( .A(n4379), .B(n2940), .Y(n4812) );
NAND2X2TS U3890 ( .A(n4425), .B(intDY_EWSW[30]), .Y(n4793) );
MXI2X2TS U3891 ( .A(n5454), .B(n3350), .S0(n5265), .Y(n1483) );
NOR2X6TS U3892 ( .A(n1848), .B(n5178), .Y(n4586) );
NAND3X6TS U3893 ( .A(n4897), .B(n2423), .C(n2619), .Y(n2620) );
NAND2X8TS U3894 ( .A(n3034), .B(n2980), .Y(n2619) );
INVX8TS U3895 ( .A(n3922), .Y(n2501) );
NAND4X4TS U3896 ( .A(n2416), .B(n2867), .C(n2868), .D(n3767), .Y(n2866) );
NOR3X6TS U3897 ( .A(Raw_mant_NRM_SWR[33]), .B(Raw_mant_NRM_SWR[41]), .C(
Raw_mant_NRM_SWR[36]), .Y(n2867) );
NAND2BX4TS U3898 ( .AN(n2447), .B(n4105), .Y(n2966) );
NAND2X4TS U3899 ( .A(n3587), .B(intDX_EWSW[48]), .Y(n4105) );
XOR2X4TS U3900 ( .A(n2905), .B(n4916), .Y(n2904) );
NAND2X4TS U3901 ( .A(n3465), .B(n3498), .Y(n3501) );
AO22X4TS U3902 ( .A0(n4587), .A1(n2763), .B0(final_result_ieee[63]), .B1(
n5571), .Y(n1184) );
INVX16TS U3903 ( .A(n2769), .Y(n4600) );
BUFX16TS U3904 ( .A(n6221), .Y(n2528) );
INVX12TS U3905 ( .A(n3047), .Y(n6221) );
OAI21X4TS U3906 ( .A0(n3493), .A1(n3492), .B0(n3491), .Y(n3499) );
NAND2X8TS U3907 ( .A(n2635), .B(n2636), .Y(n2502) );
OAI22X2TS U3908 ( .A0(n5251), .A1(n2453), .B0(n5292), .B1(n5528), .Y(n1091)
);
CLKBUFX2TS U3909 ( .A(n5278), .Y(n2763) );
NOR2X4TS U3910 ( .A(n2611), .B(n4324), .Y(n2576) );
BUFX20TS U3911 ( .A(n3832), .Y(n2611) );
NAND4BX4TS U3912 ( .AN(n3836), .B(n3835), .C(n6191), .D(n3834), .Y(n5042) );
NOR2X8TS U3913 ( .A(n3121), .B(n2916), .Y(n3120) );
OAI22X2TS U3914 ( .A0(n1916), .A1(n5260), .B0(n5287), .B1(n5539), .Y(n1082)
);
NAND2X4TS U3915 ( .A(n4712), .B(n3372), .Y(n4046) );
NAND2X2TS U3916 ( .A(n5024), .B(n2261), .Y(n2792) );
AND2X4TS U3917 ( .A(n3844), .B(n3843), .Y(n2926) );
NOR2X4TS U3918 ( .A(n3355), .B(intDY_EWSW[14]), .Y(n3432) );
INVX4TS U3919 ( .A(n4331), .Y(n4520) );
NAND2X4TS U3920 ( .A(n3039), .B(n4257), .Y(n3038) );
OR2X4TS U3921 ( .A(n3796), .B(n2038), .Y(n3037) );
NOR2X4TS U3922 ( .A(n3373), .B(DMP_exp_NRM2_EW[4]), .Y(n4005) );
AOI22X2TS U3923 ( .A0(n4722), .A1(n5031), .B0(n4708), .B1(n5036), .Y(n2997)
);
OR2X4TS U3924 ( .A(n4520), .B(n3832), .Y(n2996) );
INVX4TS U3925 ( .A(n2330), .Y(n2331) );
NOR2X4TS U3926 ( .A(n3888), .B(DMP_SFG[47]), .Y(n3897) );
NOR2X4TS U3927 ( .A(n3875), .B(DMP_SFG[44]), .Y(n3898) );
NAND2X4TS U3928 ( .A(n3967), .B(n6190), .Y(n2795) );
AND2X4TS U3929 ( .A(n3736), .B(n6216), .Y(n2911) );
NAND2X6TS U3930 ( .A(n4343), .B(n3755), .Y(n3024) );
NAND2X1TS U3931 ( .A(n3364), .B(Raw_mant_NRM_SWR[33]), .Y(n3029) );
INVX4TS U3932 ( .A(n5164), .Y(n4583) );
NAND2X4TS U3933 ( .A(n4707), .B(n4658), .Y(n2791) );
NAND2BX2TS U3934 ( .AN(n4706), .B(Data_array_SWR_3__53_), .Y(n3086) );
NOR2X4TS U3935 ( .A(n3372), .B(n2330), .Y(n4681) );
NOR2X4TS U3936 ( .A(n2582), .B(n2581), .Y(n2580) );
NOR2X4TS U3937 ( .A(n3051), .B(n3050), .Y(n3049) );
NAND2X1TS U3938 ( .A(n4708), .B(n4322), .Y(n3089) );
INVX2TS U3939 ( .A(n5831), .Y(n2694) );
NOR2X4TS U3940 ( .A(n3328), .B(n2310), .Y(n3411) );
NOR2X4TS U3941 ( .A(n3359), .B(n2295), .Y(n3424) );
NAND2X4TS U3942 ( .A(n3324), .B(intDY_EWSW[4]), .Y(n3423) );
NAND2X2TS U3943 ( .A(n3335), .B(intDY_EWSW[55]), .Y(n3557) );
NAND2X2TS U3944 ( .A(n3345), .B(intDY_EWSW[60]), .Y(n3021) );
NOR2X2TS U3945 ( .A(n3310), .B(intDY_EWSW[16]), .Y(n2707) );
NOR2X4TS U3946 ( .A(n3348), .B(intDY_EWSW[24]), .Y(n2768) );
NOR2X4TS U3947 ( .A(n3431), .B(n3447), .Y(n3433) );
INVX4TS U3948 ( .A(n4751), .Y(n2857) );
NAND2X4TS U3949 ( .A(n3403), .B(DMP_SFG[41]), .Y(n3920) );
NAND2X4TS U3950 ( .A(n3889), .B(DMP_SFG[48]), .Y(n4139) );
INVX12TS U3951 ( .A(n3068), .Y(n3218) );
NOR2X4TS U3952 ( .A(Raw_mant_NRM_SWR[32]), .B(Raw_mant_NRM_SWR[31]), .Y(
n4251) );
NAND4X4TS U3953 ( .A(n3782), .B(n3742), .C(n4248), .D(n3743), .Y(n2617) );
NAND2X2TS U3954 ( .A(n2605), .B(n4723), .Y(n2604) );
NAND2X2TS U3955 ( .A(n1950), .B(n5021), .Y(n4597) );
NOR2X2TS U3956 ( .A(n3896), .B(n2551), .Y(n2734) );
NAND2X2TS U3957 ( .A(n1635), .B(n1869), .Y(n2614) );
INVX2TS U3958 ( .A(n5083), .Y(n4752) );
INVX6TS U3959 ( .A(n3994), .Y(n3998) );
NOR2X6TS U3960 ( .A(n3130), .B(n3129), .Y(n3131) );
NAND2X6TS U3961 ( .A(n2994), .B(n2929), .Y(n5263) );
NAND2X4TS U3962 ( .A(n2388), .B(n4528), .Y(n2884) );
NOR2X1TS U3963 ( .A(n4752), .B(n4751), .Y(n4741) );
NOR2X1TS U3964 ( .A(n3271), .B(n3226), .Y(n3225) );
NAND2X4TS U3965 ( .A(n3383), .B(DMP_SFG[19]), .Y(n5077) );
INVX2TS U3966 ( .A(n5076), .Y(n5078) );
NAND2X2TS U3967 ( .A(n4952), .B(n3069), .Y(n4938) );
INVX4TS U3968 ( .A(n4288), .Y(n2482) );
NOR2X6TS U3969 ( .A(n4734), .B(n5076), .Y(n5083) );
AND2X4TS U3970 ( .A(n4021), .B(n2663), .Y(n2432) );
INVX2TS U3971 ( .A(n4021), .Y(n2665) );
NAND2X4TS U3972 ( .A(n4987), .B(n4989), .Y(n4992) );
NAND3X2TS U3973 ( .A(n4582), .B(n6293), .C(n4581), .Y(n4584) );
AND3X6TS U3974 ( .A(n2793), .B(n2792), .C(n2791), .Y(n2425) );
NAND2X2TS U3975 ( .A(n5018), .B(n1950), .Y(n2793) );
NAND2X2TS U3976 ( .A(n1950), .B(n5055), .Y(n4593) );
NOR2X6TS U3977 ( .A(n2779), .B(n5298), .Y(n2778) );
MX2X1TS U3978 ( .A(Data_Y[16]), .B(intDY_EWSW[16]), .S0(n5258), .Y(n1712) );
MX2X2TS U3979 ( .A(Data_Y[2]), .B(intDY_EWSW[2]), .S0(n5242), .Y(n1726) );
MX2X1TS U3980 ( .A(Data_Y[25]), .B(n2250), .S0(n5258), .Y(n1703) );
MX2X1TS U3981 ( .A(Data_Y[19]), .B(intDY_EWSW[19]), .S0(n5258), .Y(n1709) );
NOR2X6TS U3982 ( .A(n3312), .B(intDY_EWSW[31]), .Y(n3496) );
NAND2X2TS U3983 ( .A(n3307), .B(intDY_EWSW[30]), .Y(n3495) );
NAND2X4TS U3984 ( .A(n3309), .B(intDY_EWSW[50]), .Y(n3552) );
NAND2X2TS U3985 ( .A(n3333), .B(intDY_EWSW[22]), .Y(n3475) );
NOR2X4TS U3986 ( .A(n3294), .B(intDY_EWSW[44]), .Y(n2863) );
NAND2X2TS U3987 ( .A(n3318), .B(n2292), .Y(n3554) );
NAND2X2TS U3988 ( .A(n3347), .B(intDY_EWSW[61]), .Y(n3020) );
NOR2X4TS U3989 ( .A(n3345), .B(intDY_EWSW[60]), .Y(n2708) );
NOR2X6TS U3990 ( .A(n4931), .B(n2744), .Y(n3393) );
NAND2X1TS U3991 ( .A(n5343), .B(Raw_mant_NRM_SWR[28]), .Y(n3041) );
INVX6TS U3992 ( .A(n4586), .Y(n3126) );
NAND2X4TS U3993 ( .A(n3470), .B(n2706), .Y(n3462) );
NOR2X4TS U3994 ( .A(n3455), .B(n3437), .Y(n3458) );
NAND2X6TS U3995 ( .A(n2613), .B(n2612), .Y(n2609) );
NAND2X2TS U3996 ( .A(n5026), .B(n1919), .Y(n2612) );
INVX6TS U3997 ( .A(n4763), .Y(n3113) );
NOR3X1TS U3998 ( .A(Raw_mant_NRM_SWR[29]), .B(Raw_mant_NRM_SWR[28]), .C(
Raw_mant_NRM_SWR[26]), .Y(n4278) );
NOR2X4TS U3999 ( .A(n4892), .B(Raw_mant_NRM_SWR[6]), .Y(n2935) );
INVX2TS U4000 ( .A(n4346), .Y(n2622) );
NOR2X2TS U4001 ( .A(n2611), .B(n4717), .Y(n2633) );
CLKINVX6TS U4002 ( .A(n5042), .Y(n4324) );
XNOR2X1TS U4003 ( .A(intDX_EWSW[53]), .B(n2292), .Y(n4213) );
NOR2X4TS U4004 ( .A(n5982), .B(n5981), .Y(n2838) );
NOR2X4TS U4005 ( .A(n5937), .B(n2158), .Y(n3142) );
INVX4TS U4006 ( .A(n2617), .Y(n3778) );
NOR2X2TS U4007 ( .A(n5166), .B(n3992), .Y(n3122) );
NAND2X2TS U4008 ( .A(n1950), .B(n5014), .Y(n4486) );
NAND2X2TS U4009 ( .A(n2637), .B(n3062), .Y(n3043) );
NOR2X4TS U4010 ( .A(n4698), .B(n5057), .Y(n4673) );
OAI22X2TS U4011 ( .A0(n2611), .A1(n5053), .B0(n2552), .B1(n4661), .Y(n4646)
);
NAND2X4TS U4012 ( .A(n5322), .B(n5324), .Y(n5326) );
INVX2TS U4013 ( .A(n5322), .Y(n4784) );
NAND2X6TS U4014 ( .A(n3390), .B(DMP_SFG[25]), .Y(n4779) );
INVX2TS U4015 ( .A(n4944), .Y(n4945) );
INVX2TS U4016 ( .A(n2373), .Y(n3404) );
NAND2X4TS U4017 ( .A(n5001), .B(n2721), .Y(n2720) );
INVX2TS U4018 ( .A(n4686), .Y(n3107) );
INVX2TS U4019 ( .A(n5155), .Y(n3106) );
NAND2X2TS U4020 ( .A(n4769), .B(n4771), .Y(n4774) );
NAND2X6TS U4021 ( .A(n2909), .B(n5516), .Y(n2789) );
NOR2X2TS U4022 ( .A(n2387), .B(DMP_exp_NRM2_EW[8]), .Y(n3997) );
NOR2X2TS U4023 ( .A(n4718), .B(n4534), .Y(n4537) );
INVX2TS U4024 ( .A(n3365), .Y(n2825) );
NAND2X2TS U4025 ( .A(n4721), .B(n5155), .Y(n2881) );
NAND2X2TS U4026 ( .A(n5136), .B(n5147), .Y(n4632) );
NAND2X2TS U4027 ( .A(n4723), .B(n1644), .Y(n2820) );
NOR2X4TS U4028 ( .A(n5049), .B(n4709), .Y(n2818) );
NAND2X2TS U4029 ( .A(n4637), .B(n5018), .Y(n4041) );
MX2X2TS U4030 ( .A(Data_Y[53]), .B(n2292), .S0(n5253), .Y(n1675) );
NAND2X2TS U4031 ( .A(n6201), .B(DmP_mant_SHT1_SW[49]), .Y(n6371) );
NAND2X2TS U4032 ( .A(n5216), .B(n2298), .Y(n2761) );
NAND2X2TS U4033 ( .A(n1873), .B(Raw_mant_NRM_SWR[2]), .Y(n6370) );
NAND3X4TS U4034 ( .A(n2831), .B(n2830), .C(n2369), .Y(n1144) );
OAI21X2TS U4035 ( .A0(n2362), .A1(n4925), .B0(n4924), .Y(n4929) );
MX2X1TS U4036 ( .A(DmP_mant_SHT1_SW[29]), .B(DmP_EXP_EWSW[29]), .S0(n5204),
.Y(n1251) );
INVX2TS U4037 ( .A(n3158), .Y(n5260) );
OAI21X2TS U4038 ( .A0(n5063), .A1(n5216), .B0(n3135), .Y(n1023) );
INVX2TS U4039 ( .A(n5551), .Y(n3136) );
NAND2X2TS U4040 ( .A(n1838), .B(intDX_EWSW[52]), .Y(n4454) );
NAND2X1TS U4041 ( .A(n2550), .B(n2032), .Y(n3274) );
NAND2X1TS U4042 ( .A(n5191), .B(DmP_mant_SFG_SWR[31]), .Y(n3155) );
OAI2BB2X2TS U4043 ( .B0(n2527), .B1(n5420), .A0N(n5045), .A1N(n6230), .Y(
n6208) );
INVX3TS U4044 ( .A(rst), .Y(n6465) );
NAND2X2TS U4045 ( .A(n2690), .B(n4671), .Y(n6451) );
NAND2X2TS U4046 ( .A(n3234), .B(Raw_mant_NRM_SWR[10]), .Y(n6387) );
AOI2BB2X2TS U4047 ( .B0(n2306), .B1(n5029), .A0N(n4653), .A1N(n6231), .Y(
n6377) );
NAND2X2TS U4048 ( .A(n3234), .B(Raw_mant_NRM_SWR[27]), .Y(n6313) );
NAND2X2TS U4049 ( .A(n3234), .B(Raw_mant_NRM_SWR[25]), .Y(n6316) );
NAND2X2TS U4050 ( .A(n2690), .B(n4506), .Y(n6454) );
MX2X1TS U4051 ( .A(DmP_mant_SHT1_SW[34]), .B(DmP_EXP_EWSW[34]), .S0(n5204),
.Y(n1241) );
AOI22X1TS U4052 ( .A0(n4506), .A1(n4542), .B0(DmP_mant_SFG_SWR[16]), .B1(
n5218), .Y(n4507) );
OAI21X2TS U4053 ( .A0(n3204), .A1(n5005), .B0(n3203), .Y(n1163) );
NAND2X1TS U4054 ( .A(n2384), .B(LZD_output_NRM2_EW[0]), .Y(n2987) );
MX2X1TS U4055 ( .A(Data_X[11]), .B(intDX_EWSW[11]), .S0(n5241), .Y(n1783) );
MX2X1TS U4056 ( .A(Data_Y[61]), .B(intDY_EWSW[61]), .S0(n5252), .Y(n1667) );
MX2X1TS U4057 ( .A(Data_Y[57]), .B(intDY_EWSW[57]), .S0(n5252), .Y(n1671) );
MX2X1TS U4058 ( .A(Data_Y[49]), .B(intDY_EWSW[49]), .S0(n5253), .Y(n1679) );
MX2X1TS U4059 ( .A(Data_Y[17]), .B(intDY_EWSW[17]), .S0(n5258), .Y(n1711) );
NAND3X6TS U4060 ( .A(n2661), .B(n2660), .C(n2658), .Y(n2666) );
INVX2TS U4061 ( .A(n5319), .Y(n2318) );
INVX2TS U4062 ( .A(DmP_mant_SHT1_SW[47]), .Y(n5602) );
INVX2TS U4063 ( .A(DmP_mant_SHT1_SW[50]), .Y(n5599) );
INVX2TS U4064 ( .A(DmP_mant_SHT1_SW[22]), .Y(n5577) );
INVX2TS U4065 ( .A(DmP_mant_SHT1_SW[24]), .Y(n5604) );
INVX2TS U4066 ( .A(DmP_mant_SHT1_SW[10]), .Y(n5585) );
INVX2TS U4067 ( .A(DmP_mant_SHT1_SW[38]), .Y(n5592) );
INVX2TS U4068 ( .A(DmP_mant_SHT1_SW[40]), .Y(n5613) );
INVX2TS U4069 ( .A(DmP_mant_SHT1_SW[31]), .Y(n5609) );
INVX2TS U4070 ( .A(DmP_mant_SHT1_SW[48]), .Y(n5589) );
INVX2TS U4071 ( .A(DmP_mant_SHT1_SW[46]), .Y(n5605) );
INVX2TS U4072 ( .A(DmP_mant_SHT1_SW[17]), .Y(n5593) );
INVX2TS U4073 ( .A(DmP_mant_SHT1_SW[18]), .Y(n5615) );
INVX2TS U4074 ( .A(DmP_mant_SHT1_SW[23]), .Y(n5606) );
INVX2TS U4075 ( .A(DmP_mant_SHT1_SW[19]), .Y(n5598) );
INVX2TS U4076 ( .A(DmP_mant_SHT1_SW[25]), .Y(n5590) );
INVX2TS U4077 ( .A(DmP_mant_SHT1_SW[36]), .Y(n5608) );
INVX2TS U4078 ( .A(DmP_mant_SHT1_SW[32]), .Y(n5584) );
INVX2TS U4079 ( .A(DmP_mant_SHT1_SW[45]), .Y(n5414) );
INVX2TS U4080 ( .A(DmP_mant_SHT1_SW[9]), .Y(n5594) );
INVX2TS U4081 ( .A(DmP_mant_SHT1_SW[49]), .Y(n5578) );
INVX2TS U4082 ( .A(DmP_mant_SHT1_SW[41]), .Y(n5582) );
INVX2TS U4083 ( .A(DmP_mant_SHT1_SW[21]), .Y(n5611) );
INVX2TS U4084 ( .A(DmP_mant_SHT1_SW[39]), .Y(n5583) );
INVX2TS U4085 ( .A(DmP_mant_SHT1_SW[3]), .Y(n5575) );
INVX2TS U4086 ( .A(DmP_mant_SHT1_SW[6]), .Y(n5597) );
INVX2TS U4087 ( .A(DmP_mant_SHT1_SW[14]), .Y(n5586) );
INVX2TS U4088 ( .A(DmP_mant_SHT1_SW[12]), .Y(n5587) );
INVX2TS U4089 ( .A(DmP_mant_SHT1_SW[16]), .Y(n5600) );
AOI2BB2X2TS U4090 ( .B0(n6205), .B1(Raw_mant_NRM_SWR[33]), .A0N(n4715),
.A1N(n4332), .Y(n6391) );
NAND2X2TS U4091 ( .A(n3234), .B(Raw_mant_NRM_SWR[18]), .Y(n6304) );
NAND2X2TS U4092 ( .A(n5184), .B(n4506), .Y(n6423) );
OAI22X2TS U4093 ( .A0(n1916), .A1(n4145), .B0(n5289), .B1(n5543), .Y(n1079)
);
INVX2TS U4094 ( .A(n2537), .Y(n2521) );
BUFX3TS U4095 ( .A(n6292), .Y(n6234) );
CLKINVX3TS U4096 ( .A(rst), .Y(n2520) );
NAND2X4TS U4097 ( .A(n3260), .B(n3259), .Y(n6210) );
NAND2X1TS U4098 ( .A(n2873), .B(n4333), .Y(n3259) );
INVX2TS U4099 ( .A(DmP_mant_SHT1_SW[33]), .Y(n5614) );
NAND2X2TS U4100 ( .A(n6228), .B(n4049), .Y(n2946) );
NAND2X2TS U4101 ( .A(n3234), .B(Raw_mant_NRM_SWR[30]), .Y(n6300) );
NOR2X2TS U4102 ( .A(n4026), .B(n2974), .Y(n2973) );
CLKINVX3TS U4103 ( .A(rst), .Y(n2533) );
BUFX3TS U4104 ( .A(n6289), .Y(n6257) );
NAND2X1TS U4105 ( .A(n4417), .B(DmP_EXP_EWSW[41]), .Y(n3689) );
NAND2X1TS U4106 ( .A(n4417), .B(DmP_EXP_EWSW[39]), .Y(n3686) );
NAND2X2TS U4107 ( .A(n2116), .B(intDY_EWSW[39]), .Y(n3687) );
NAND2X1TS U4108 ( .A(n4864), .B(DmP_EXP_EWSW[38]), .Y(n4099) );
NAND2X2TS U4109 ( .A(n3630), .B(intDX_EWSW[33]), .Y(n4803) );
NAND2X2TS U4110 ( .A(n2531), .B(intDX_EWSW[32]), .Y(n4806) );
NAND2X2TS U4111 ( .A(n1838), .B(intDX_EWSW[30]), .Y(n4794) );
CLKBUFX3TS U4112 ( .A(n6292), .Y(n6232) );
NAND2X1TS U4113 ( .A(n4853), .B(DmP_EXP_EWSW[25]), .Y(n4854) );
NAND2X2TS U4114 ( .A(n4424), .B(intDX_EWSW[25]), .Y(n4856) );
NAND2X2TS U4115 ( .A(n3630), .B(intDX_EWSW[23]), .Y(n4830) );
NAND2X1TS U4116 ( .A(n4417), .B(DmP_EXP_EWSW[15]), .Y(n4106) );
NAND2X2TS U4117 ( .A(n4412), .B(n2035), .Y(n4107) );
NAND2X1TS U4118 ( .A(n4864), .B(DmP_EXP_EWSW[4]), .Y(n4114) );
NAND2X2TS U4119 ( .A(n4873), .B(intDY_EWSW[2]), .Y(n4374) );
CLKINVX3TS U4120 ( .A(n2537), .Y(n2545) );
BUFX3TS U4121 ( .A(n6233), .Y(n6253) );
MXI2X1TS U4122 ( .A(n4728), .B(SIGN_FLAG_EXP), .S0(n2524), .Y(n4231) );
NAND2X1TS U4123 ( .A(n2525), .B(DMP_EXP_EWSW[62]), .Y(n3659) );
INVX2TS U4124 ( .A(rst), .Y(n2544) );
NAND2X1TS U4125 ( .A(n3652), .B(DMP_EXP_EWSW[39]), .Y(n3618) );
NAND2X1TS U4126 ( .A(n3652), .B(DMP_EXP_EWSW[37]), .Y(n3631) );
NAND2X1TS U4127 ( .A(n3652), .B(DMP_EXP_EWSW[36]), .Y(n3621) );
NAND2X1TS U4128 ( .A(n3652), .B(DMP_EXP_EWSW[35]), .Y(n3624) );
NAND2X1TS U4129 ( .A(n3652), .B(DMP_EXP_EWSW[33]), .Y(n3627) );
NAND2X1TS U4130 ( .A(n3652), .B(DMP_EXP_EWSW[32]), .Y(n3646) );
NAND2X1TS U4131 ( .A(n3652), .B(DMP_EXP_EWSW[31]), .Y(n3653) );
NAND2X1TS U4132 ( .A(n4426), .B(DMP_EXP_EWSW[28]), .Y(n3640) );
NAND2X1TS U4133 ( .A(n4426), .B(DMP_EXP_EWSW[27]), .Y(n3656) );
NAND2X1TS U4134 ( .A(n4426), .B(DMP_EXP_EWSW[26]), .Y(n4421) );
NAND2X1TS U4135 ( .A(n4426), .B(DMP_EXP_EWSW[25]), .Y(n4427) );
NAND2X1TS U4136 ( .A(n4426), .B(DMP_EXP_EWSW[22]), .Y(n3637) );
NAND2X1TS U4137 ( .A(n4426), .B(n2255), .Y(n3634) );
NAND2X1TS U4138 ( .A(n2525), .B(n2259), .Y(n3680) );
NAND2X2TS U4139 ( .A(n2049), .B(intDX_EWSW[19]), .Y(n3681) );
NAND2X1TS U4140 ( .A(n4417), .B(DMP_EXP_EWSW[10]), .Y(n4418) );
NAND2X1TS U4141 ( .A(n4417), .B(DMP_EXP_EWSW[9]), .Y(n4409) );
NAND2X1TS U4142 ( .A(n4834), .B(DMP_EXP_EWSW[7]), .Y(n4074) );
NAND2X2TS U4143 ( .A(n3124), .B(intDY_EWSW[6]), .Y(n4445) );
NAND2X2TS U4144 ( .A(n2526), .B(n2737), .Y(n4434) );
BUFX3TS U4145 ( .A(n6289), .Y(n6236) );
MX2X4TS U4146 ( .A(n3409), .B(n2570), .S0(n2547), .Y(n1599) );
NAND2X1TS U4147 ( .A(n6230), .B(Data_array_SWR_3__53_), .Y(n4436) );
MX2X1TS U4148 ( .A(Data_Y[42]), .B(n1815), .S0(n5235), .Y(n1686) );
MX2X1TS U4149 ( .A(Data_Y[32]), .B(n2957), .S0(n5236), .Y(n1696) );
NAND2X8TS U4150 ( .A(n2736), .B(n3007), .Y(n3006) );
XOR2X4TS U4151 ( .A(n2493), .B(n2293), .Y(n2909) );
XNOR2X4TS U4152 ( .A(n2294), .B(DmP_mant_SFG_SWR[22]), .Y(n3384) );
NOR2X6TS U4153 ( .A(n5040), .B(n2855), .Y(n3236) );
AOI22X2TS U4154 ( .A0(n6206), .A1(Raw_mant_NRM_SWR[15]), .B0(n1917), .B1(
n6228), .Y(n6342) );
NAND4BX4TS U4155 ( .AN(n3715), .B(n3714), .C(n6140), .D(n6139), .Y(n2296) );
CLKMX2X3TS U4156 ( .A(Data_Y[5]), .B(n2295), .S0(n5242), .Y(n1723) );
NAND2X2TS U4157 ( .A(n1837), .B(intDX_EWSW[15]), .Y(n3666) );
NAND2X2TS U4158 ( .A(n4807), .B(n2048), .Y(n4314) );
NAND2X4TS U4159 ( .A(n3677), .B(n3679), .Y(n2304) );
INVX4TS U4160 ( .A(n2304), .Y(n2305) );
NAND2X4TS U4161 ( .A(n4416), .B(intDY_EWSW[61]), .Y(n3679) );
NAND2X2TS U4162 ( .A(n4863), .B(intDX_EWSW[16]), .Y(n3663) );
NAND2X2TS U4163 ( .A(n4369), .B(intDX_EWSW[22]), .Y(n3638) );
INVX12TS U4164 ( .A(n2853), .Y(n3235) );
NAND2X4TS U4165 ( .A(n4610), .B(n4611), .Y(n4616) );
NAND2X2TS U4166 ( .A(n5140), .B(n2516), .Y(n4611) );
INVX12TS U4167 ( .A(n5046), .Y(n6214) );
OA21X4TS U4168 ( .A0(n2011), .A1(n2465), .B0(n3981), .Y(n2309) );
AOI22X2TS U4169 ( .A0(n6205), .A1(Raw_mant_NRM_SWR[26]), .B0(n5023), .B1(
n5041), .Y(n6312) );
XNOR2X4TS U4170 ( .A(n4010), .B(n2311), .Y(n5178) );
AND2X4TS U4171 ( .A(n2262), .B(n5025), .Y(n3150) );
OAI21X2TS U4172 ( .A0(n5291), .A1(n5216), .B0(n2841), .Y(n1019) );
AOI22X2TS U4173 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[0]), .B0(n2296), .B1(
n6228), .Y(n6368) );
AND2X4TS U4174 ( .A(n4474), .B(n2296), .Y(n2430) );
NAND2X2TS U4175 ( .A(n4838), .B(intDY_EWSW[54]), .Y(n4447) );
NAND3X2TS U4176 ( .A(n4825), .B(n4824), .C(n4823), .Y(n1254) );
BUFX12TS U4177 ( .A(n2985), .Y(n2648) );
NAND2X2TS U4178 ( .A(n6219), .B(Raw_mant_NRM_SWR[5]), .Y(n6345) );
MXI2X2TS U4179 ( .A(n5266), .B(n5518), .S0(n2554), .Y(n1041) );
BUFX20TS U4180 ( .A(n2502), .Y(n2990) );
NAND2X4TS U4181 ( .A(n3294), .B(intDY_EWSW[44]), .Y(n3539) );
NAND4X4TS U4182 ( .A(n2314), .B(n2315), .C(n3167), .D(n3285), .Y(n1148) );
OA21X4TS U4183 ( .A0(n3170), .A1(n3286), .B0(n3288), .Y(n2315) );
NAND2X2TS U4184 ( .A(n6218), .B(Raw_mant_NRM_SWR[40]), .Y(n6376) );
INVX6TS U4185 ( .A(n4766), .Y(n4771) );
NAND3X6TS U4186 ( .A(n4257), .B(n3299), .C(Raw_mant_NRM_SWR[27]), .Y(n4279)
);
AND2X4TS U4187 ( .A(n3272), .B(n4912), .Y(n2316) );
NOR2X8TS U4188 ( .A(n2316), .B(n4911), .Y(n4913) );
OAI22X2TS U4189 ( .A0(n2453), .A1(n4652), .B0(n5292), .B1(n5530), .Y(n1086)
);
BUFX20TS U4190 ( .A(n5046), .Y(n2982) );
AOI22X4TS U4191 ( .A0(n2516), .A1(n5136), .B0(n2022), .B1(n5145), .Y(n6463)
);
AND4X8TS U4192 ( .A(n3216), .B(n3212), .C(n3215), .D(n2386), .Y(n2317) );
MXI2X4TS U4193 ( .A(n6207), .B(n2347), .S0(n2318), .Y(n1158) );
NAND3X4TS U4194 ( .A(n2615), .B(n1989), .C(n2616), .Y(n2319) );
BUFX12TS U4195 ( .A(n3804), .Y(n4637) );
INVX1TS U4196 ( .A(n3149), .Y(n5321) );
AOI21X2TS U4197 ( .A0(n4901), .A1(n4900), .B0(n4899), .Y(n4903) );
NOR2X4TS U4198 ( .A(n4026), .B(n5415), .Y(n2972) );
INVX16TS U4199 ( .A(n4026), .Y(n6199) );
NOR3X6TS U4200 ( .A(n4027), .B(n4254), .C(n3026), .Y(n3025) );
INVX12TS U4201 ( .A(n2317), .Y(n4990) );
BUFX12TS U4202 ( .A(n5032), .Y(n6224) );
BUFX12TS U4203 ( .A(n5032), .Y(n2564) );
BUFX12TS U4204 ( .A(n5032), .Y(n2499) );
NOR2X4TS U4205 ( .A(Raw_mant_NRM_SWR[36]), .B(Raw_mant_NRM_SWR[43]), .Y(
n3252) );
NOR2X4TS U4206 ( .A(Raw_mant_NRM_SWR[43]), .B(Raw_mant_NRM_SWR[42]), .Y(
n3727) );
NOR2X4TS U4207 ( .A(Raw_mant_NRM_SWR[43]), .B(Raw_mant_NRM_SWR[46]), .Y(
n3737) );
OAI2BB1X4TS U4208 ( .A0N(n2906), .A1N(n2321), .B0(n4947), .Y(n4951) );
XOR2X4TS U4209 ( .A(n2322), .B(n2363), .Y(n2908) );
AOI21X4TS U4210 ( .A0(n2677), .A1(n2339), .B0(n2340), .Y(n2322) );
AOI21X2TS U4211 ( .A0(n4990), .A1(n4923), .B0(n4922), .Y(n4924) );
NAND2X4TS U4212 ( .A(n2278), .B(n3190), .Y(n3189) );
AND3X6TS U4213 ( .A(n2942), .B(n3732), .C(n3733), .Y(n3734) );
AOI2BB2X4TS U4214 ( .B0(n2497), .B1(DmP_mant_SHT1_SW[32]), .A0N(n5341),
.A1N(n2527), .Y(n6344) );
NAND2X4TS U4215 ( .A(n2648), .B(n2987), .Y(n1138) );
NAND4X6TS U4216 ( .A(n3213), .B(n2952), .C(n3275), .D(n3218), .Y(n3212) );
BUFX16TS U4217 ( .A(n3833), .Y(n4709) );
MXI2X4TS U4218 ( .A(n2328), .B(n2327), .S0(n5319), .Y(n1157) );
XOR2X4TS U4219 ( .A(n4996), .B(n2359), .Y(n2347) );
OAI2BB1X4TS U4220 ( .A0N(n3272), .A1N(n4935), .B0(n2326), .Y(n2368) );
AND2X8TS U4221 ( .A(n4933), .B(n2717), .Y(n2326) );
NAND2X4TS U4222 ( .A(n5037), .B(n2555), .Y(n2613) );
NOR2X4TS U4223 ( .A(n3402), .B(DMP_SFG[40]), .Y(n3919) );
XNOR2X4TS U4224 ( .A(n4976), .B(n2361), .Y(n2328) );
AND3X8TS U4225 ( .A(n2423), .B(n4897), .C(n2619), .Y(n2329) );
NOR2X6TS U4226 ( .A(n3511), .B(n3556), .Y(n2683) );
NAND2X6TS U4227 ( .A(n3266), .B(n2664), .Y(n2661) );
INVX16TS U4228 ( .A(n2342), .Y(n3266) );
INVX16TS U4229 ( .A(n3261), .Y(n6212) );
XOR2X4TS U4230 ( .A(n2333), .B(n2258), .Y(n5281) );
INVX16TS U4231 ( .A(n2712), .Y(n3175) );
NAND3X8TS U4232 ( .A(n2787), .B(n2788), .C(n3222), .Y(n2712) );
NAND2X4TS U4233 ( .A(n3767), .B(n5422), .Y(n2747) );
NOR2X4TS U4234 ( .A(n2368), .B(n2715), .Y(n4953) );
NAND2X4TS U4235 ( .A(n2711), .B(n4930), .Y(n2717) );
NAND2XLTS U4236 ( .A(n5089), .B(n2323), .Y(n3278) );
CLKBUFX2TS U4237 ( .A(n4780), .Y(n2959) );
NAND2X4TS U4238 ( .A(n2426), .B(n2677), .Y(n2721) );
AND2X8TS U4239 ( .A(n2915), .B(n3257), .Y(n2334) );
MXI2X2TS U4240 ( .A(n2335), .B(n5573), .S0(n5319), .Y(n1166) );
XNOR2X4TS U4241 ( .A(n4967), .B(n4966), .Y(n2335) );
XOR2X4TS U4242 ( .A(n4956), .B(n2337), .Y(n4957) );
NOR2X4TS U4243 ( .A(Raw_mant_NRM_SWR[46]), .B(Raw_mant_NRM_SWR[41]), .Y(
n3728) );
NOR2X6TS U4244 ( .A(n1913), .B(Raw_mant_NRM_SWR[46]), .Y(n3785) );
NAND3X2TS U4245 ( .A(n3757), .B(n1913), .C(n5425), .Y(n3741) );
XNOR2X4TS U4246 ( .A(n2720), .B(n2338), .Y(n2719) );
AO21X1TS U4247 ( .A0(n3404), .A1(n2389), .B0(n3872), .Y(n2340) );
CLKBUFX2TS U4248 ( .A(n5064), .Y(n2767) );
NAND2X8TS U4249 ( .A(n2404), .B(n5281), .Y(n3270) );
INVX6TS U4250 ( .A(n2345), .Y(n2346) );
NAND2X4TS U4251 ( .A(n2346), .B(n3252), .Y(n3251) );
MXI2X2TS U4252 ( .A(n2348), .B(n3371), .S0(n5205), .Y(n1160) );
XNOR2X4TS U4253 ( .A(n4919), .B(n2364), .Y(n2348) );
XNOR2X4TS U4254 ( .A(n4786), .B(n2355), .Y(n2349) );
MXI2X4TS U4255 ( .A(n5432), .B(n2350), .S0(n3232), .Y(n1171) );
XNOR2X4TS U4256 ( .A(n4778), .B(n2360), .Y(n2350) );
NAND2X4TS U4257 ( .A(n4250), .B(n5432), .Y(n3747) );
AOI2BB2X2TS U4258 ( .B0(n6203), .B1(DmP_mant_SHT1_SW[22]), .A0N(n5445),
.A1N(n2527), .Y(n6307) );
MXI2X4TS U4259 ( .A(n5569), .B(n2351), .S0(n3232), .Y(n1165) );
XNOR2X4TS U4260 ( .A(n4986), .B(n2356), .Y(n2351) );
XNOR2X4TS U4261 ( .A(n2677), .B(n2352), .Y(n3276) );
MXI2X2TS U4262 ( .A(n5492), .B(n2353), .S0(n3232), .Y(n1170) );
XNOR2X4TS U4263 ( .A(n4768), .B(n2365), .Y(n2353) );
MXI2X4TS U4264 ( .A(n5431), .B(n2354), .S0(n3287), .Y(n1172) );
XNOR2X4TS U4265 ( .A(n4750), .B(n2366), .Y(n2354) );
MXI2X4TS U4266 ( .A(n5343), .B(n2357), .S0(n3287), .Y(n1169) );
XOR2X4TS U4267 ( .A(n4777), .B(n4776), .Y(n2357) );
XNOR2X4TS U4268 ( .A(n3899), .B(n2367), .Y(n2955) );
INVX16TS U4269 ( .A(n3175), .Y(n2677) );
AOI21X2TS U4270 ( .A0(n3245), .A1(n4741), .B0(n4740), .Y(n4744) );
AOI21X2TS U4271 ( .A0(n3245), .A1(n4758), .B0(n4757), .Y(n4761) );
MX2X6TS U4272 ( .A(OP_FLAG_SHT2), .B(n2489), .S0(n2764), .Y(n6147) );
NAND2X4TS U4273 ( .A(n2401), .B(n2342), .Y(n2730) );
OR2X2TS U4274 ( .A(n3878), .B(n3231), .Y(n2370) );
INVX2TS U4275 ( .A(n4241), .Y(n4242) );
INVX12TS U4276 ( .A(n4062), .Y(n4711) );
INVX2TS U4277 ( .A(n2917), .Y(n2723) );
OR2X2TS U4278 ( .A(n4026), .B(n2969), .Y(n2375) );
INVX6TS U4279 ( .A(n2992), .Y(n2989) );
AND2X8TS U4280 ( .A(n3298), .B(n5440), .Y(n2378) );
NAND2X1TS U4281 ( .A(n2551), .B(Raw_mant_NRM_SWR[50]), .Y(n3288) );
AND2X2TS U4282 ( .A(n5271), .B(DmP_mant_SFG_SWR[39]), .Y(n2385) );
OA21X2TS U4283 ( .A0(n4948), .A1(n4944), .B0(n4949), .Y(n2386) );
OR2X2TS U4284 ( .A(n4718), .B(n4520), .Y(n2388) );
AND2X2TS U4285 ( .A(n4637), .B(Data_array_SWR_3__53_), .Y(n2391) );
AND2X2TS U4286 ( .A(n2780), .B(n5026), .Y(n2396) );
INVX8TS U4287 ( .A(n3207), .Y(n3275) );
INVX12TS U4288 ( .A(n1906), .Y(n6225) );
INVX12TS U4289 ( .A(n1906), .Y(n6226) );
NAND2X2TS U4290 ( .A(n4608), .B(n5147), .Y(n2400) );
OR2X8TS U4291 ( .A(n3378), .B(DMP_SFG[13]), .Y(n2404) );
INVX8TS U4292 ( .A(n5097), .Y(n5065) );
NAND2X4TS U4293 ( .A(n2840), .B(n5478), .Y(n2405) );
AND3X8TS U4294 ( .A(n2857), .B(n3297), .C(n3295), .Y(n2406) );
AND4X4TS U4295 ( .A(n2901), .B(n2900), .C(n2895), .D(n4339), .Y(n2417) );
AND2X8TS U4296 ( .A(n3941), .B(n3943), .Y(n2418) );
INVX8TS U4297 ( .A(n2611), .Y(n4723) );
AND2X4TS U4298 ( .A(n5135), .B(n4685), .Y(n2419) );
AND2X8TS U4299 ( .A(n3078), .B(n3077), .Y(n2420) );
AND2X8TS U4300 ( .A(n2501), .B(DmP_mant_SHT1_SW[12]), .Y(n2421) );
AND2X4TS U4301 ( .A(n3218), .B(n3396), .Y(n2422) );
INVX2TS U4302 ( .A(n3878), .Y(n3271) );
NAND2X4TS U4303 ( .A(n3910), .B(n3882), .Y(n3878) );
AND2X2TS U4304 ( .A(n4998), .B(n5000), .Y(n2426) );
AND2X4TS U4305 ( .A(n4281), .B(n4274), .Y(n2429) );
INVX2TS U4306 ( .A(n4930), .Y(n4934) );
NOR2X4TS U4307 ( .A(n2760), .B(n4965), .Y(n4930) );
AND2X2TS U4308 ( .A(n4136), .B(n4135), .Y(n2431) );
NAND2X2TS U4309 ( .A(n2261), .B(n5051), .Y(n2433) );
OR2X8TS U4310 ( .A(n2649), .B(n2382), .Y(n2435) );
OR2X2TS U4311 ( .A(n3833), .B(n6410), .Y(n2437) );
INVX2TS U4312 ( .A(n1871), .Y(n2826) );
AND2X4TS U4313 ( .A(n3175), .B(n2678), .Y(n2440) );
NAND2X4TS U4314 ( .A(n6216), .B(n6207), .Y(n3253) );
INVX2TS U4315 ( .A(n3032), .Y(n5298) );
OR2X2TS U4316 ( .A(n3331), .B(DMP_EXP_EWSW[53]), .Y(n2443) );
AND2X2TS U4317 ( .A(n2550), .B(Raw_mant_NRM_SWR[48]), .Y(n2448) );
INVX2TS U4318 ( .A(n2673), .Y(n3166) );
INVX2TS U4319 ( .A(DmP_mant_SHT1_SW[11]), .Y(n2971) );
INVX6TS U4320 ( .A(n5428), .Y(n3784) );
INVX2TS U4321 ( .A(DmP_mant_SHT1_SW[13]), .Y(n2974) );
INVX2TS U4322 ( .A(DmP_mant_SHT1_SW[20]), .Y(n2969) );
INVX2TS U4323 ( .A(DmP_mant_SHT1_SW[27]), .Y(n2976) );
INVX2TS U4324 ( .A(n2537), .Y(n2540) );
CLKINVX3TS U4325 ( .A(rst), .Y(n2512) );
CLKBUFX3TS U4326 ( .A(n6289), .Y(n6258) );
INVX3TS U4327 ( .A(rst), .Y(n2514) );
CLKBUFX2TS U4328 ( .A(n4465), .Y(n6240) );
INVX2TS U4329 ( .A(rst), .Y(n2542) );
INVX2TS U4330 ( .A(rst), .Y(n2541) );
BUFX3TS U4331 ( .A(n6289), .Y(n6256) );
INVX2TS U4332 ( .A(rst), .Y(n2543) );
INVX2TS U4333 ( .A(n2537), .Y(n2511) );
BUFX20TS U4334 ( .A(n4838), .Y(n2452) );
OAI21X4TS U4335 ( .A0(n2989), .A1(n2088), .B0(n2991), .Y(n1059) );
AOI21X4TS U4336 ( .A0(n2457), .A1(n3470), .B0(n2454), .Y(n3482) );
OAI22X4TS U4337 ( .A0(n2467), .A1(n2458), .B0(intDX_EWSW[17]), .B1(n2442),
.Y(n2457) );
NOR2X8TS U4338 ( .A(n3341), .B(intDY_EWSW[17]), .Y(n2467) );
NOR2X8TS U4339 ( .A(n3248), .B(n2491), .Y(n4027) );
NAND2X8TS U4340 ( .A(n2460), .B(n2459), .Y(n5262) );
OAI21X4TS U4341 ( .A0(n2465), .A1(n3980), .B0(n3981), .Y(n3989) );
XOR2X4TS U4342 ( .A(n3983), .B(n1824), .Y(n5176) );
NOR2X8TS U4343 ( .A(n3321), .B(DMP_exp_NRM2_EW[0]), .Y(n2465) );
NAND2X8TS U4344 ( .A(n2466), .B(n2397), .Y(n2787) );
NOR2X8TS U4345 ( .A(n2707), .B(n2052), .Y(n2706) );
AND2X8TS U4346 ( .A(n2486), .B(intDX_EWSW[13]), .Y(n3447) );
XOR2X4TS U4347 ( .A(DmP_mant_SFG_SWR[26]), .B(n1839), .Y(n2652) );
NAND2X8TS U4348 ( .A(n2468), .B(n1914), .Y(n2651) );
INVX8TS U4349 ( .A(n4746), .Y(n2468) );
OR2X8TS U4350 ( .A(n2650), .B(n5465), .Y(n4746) );
NOR2X8TS U4351 ( .A(n2469), .B(n2850), .Y(n3243) );
NAND2X4TS U4352 ( .A(n2851), .B(n2849), .Y(n2469) );
AND2X8TS U4353 ( .A(n2891), .B(n3367), .Y(n2849) );
AND2X8TS U4354 ( .A(n2471), .B(n4632), .Y(n5256) );
NAND2X4TS U4355 ( .A(n3314), .B(intDY_EWSW[52]), .Y(n3555) );
NOR2X6TS U4356 ( .A(n3311), .B(n2479), .Y(n3473) );
NAND2XLTS U4357 ( .A(n3370), .B(n5069), .Y(n5070) );
XNOR2X2TS U4358 ( .A(n3245), .B(n4735), .Y(n4736) );
NAND2X2TS U4359 ( .A(n6215), .B(n6455), .Y(n6421) );
NAND2X2TS U4360 ( .A(n6215), .B(n6437), .Y(n6436) );
NAND2X2TS U4361 ( .A(n6215), .B(n6441), .Y(n6432) );
NAND2X2TS U4362 ( .A(n6215), .B(n6459), .Y(n6417) );
NAND2X2TS U4363 ( .A(n6215), .B(n6449), .Y(n6425) );
NAND2X2TS U4364 ( .A(n6215), .B(n6457), .Y(n6419) );
NAND2X2TS U4365 ( .A(n2116), .B(n2479), .Y(n4861) );
NOR2BX4TS U4366 ( .AN(n3172), .B(n2473), .Y(n2678) );
XOR2X4TS U4367 ( .A(n3210), .B(n2434), .Y(n3209) );
NAND3X4TS U4368 ( .A(n3244), .B(n3243), .C(n4249), .Y(n2474) );
NAND2X2TS U4369 ( .A(n2690), .B(n5182), .Y(n6448) );
NAND2X4TS U4370 ( .A(n2558), .B(n5262), .Y(n3943) );
BUFX20TS U4371 ( .A(n3125), .Y(n3587) );
NAND2X4TS U4372 ( .A(n3262), .B(n2621), .Y(n2476) );
AND2X8TS U4373 ( .A(intDX_EWSW[11]), .B(n2477), .Y(n3441) );
OAI22X2TS U4374 ( .A0(n2990), .A1(n5246), .B0(n5289), .B1(n5535), .Y(n1089)
);
OAI21X1TS U4375 ( .A0(n3248), .A1(n4278), .B0(n4351), .Y(n4283) );
INVX12TS U4376 ( .A(n5046), .Y(n2527) );
NAND2X4TS U4377 ( .A(n3351), .B(intDY_EWSW[38]), .Y(n3527) );
NOR2X8TS U4378 ( .A(n3351), .B(intDY_EWSW[38]), .Y(n3506) );
BUFX20TS U4379 ( .A(n3125), .Y(n4430) );
NAND3X4TS U4380 ( .A(n4284), .B(n4255), .C(n4256), .Y(n4263) );
NAND2X2TS U4381 ( .A(n4884), .B(n4253), .Y(n4256) );
INVX16TS U4382 ( .A(n2847), .Y(n3233) );
NOR2X4TS U4383 ( .A(n4349), .B(n4348), .Y(n3757) );
NAND2X8TS U4384 ( .A(n2482), .B(n2483), .Y(n2484) );
NAND2X8TS U4385 ( .A(n2484), .B(n2563), .Y(n4869) );
OAI22X2TS U4386 ( .A0(n2990), .A1(n5254), .B0(n5289), .B1(n5534), .Y(n1099)
);
NAND2X2TS U4387 ( .A(n2262), .B(n5055), .Y(n3723) );
NOR2X4TS U4388 ( .A(n3507), .B(n3520), .Y(n3508) );
XNOR2X1TS U4389 ( .A(n3362), .B(n2485), .Y(n4217) );
AOI21X4TS U4390 ( .A0(n4055), .A1(n1871), .B0(n4054), .Y(n4056) );
AOI21X2TS U4391 ( .A0(n3245), .A1(n5083), .B0(n2924), .Y(n5088) );
XNOR2X4TS U4392 ( .A(n2754), .B(n2431), .Y(n3280) );
OAI2BB1X2TS U4393 ( .A0N(n5123), .A1N(n6452), .B0(n4505), .Y(n1032) );
NAND3X2TS U4394 ( .A(n4896), .B(n4897), .C(n4898), .Y(n4899) );
NAND2X8TS U4395 ( .A(n3036), .B(n2329), .Y(n3192) );
NOR2X8TS U4396 ( .A(n3201), .B(n2513), .Y(n3036) );
OAI21X2TS U4397 ( .A0(n3773), .A1(n3772), .B0(n4335), .Y(n3774) );
NOR2X8TS U4398 ( .A(n3464), .B(n3496), .Y(n3498) );
INVX12TS U4399 ( .A(n6353), .Y(n6408) );
BUFX4TS U4400 ( .A(n5084), .Y(n3245) );
AOI2BB2X4TS U4401 ( .B0(n2496), .B1(DmP_mant_SHT1_SW[10]), .A0N(n5422),
.A1N(n2527), .Y(n6359) );
NAND2X8TS U4402 ( .A(n3756), .B(n2480), .Y(n4896) );
NAND2X1TS U4403 ( .A(n2789), .B(n4775), .Y(n4776) );
AOI21X2TS U4404 ( .A0(DmP_mant_SHT1_SW[14]), .A1(n6204), .B0(n2973), .Y(
n6375) );
AOI22X4TS U4405 ( .A0(n2496), .A1(DmP_mant_SHT1_SW[38]), .B0(
DmP_mant_SHT1_SW[39]), .B1(n6204), .Y(n6363) );
INVX8TS U4406 ( .A(n3922), .Y(n2500) );
INVX8TS U4407 ( .A(n3922), .Y(n6204) );
INVX16TS U4408 ( .A(n6202), .Y(n2497) );
BUFX20TS U4409 ( .A(n3125), .Y(n4416) );
BUFX4TS U4410 ( .A(n2716), .Y(n2711) );
AO22X2TS U4411 ( .A0(n4488), .A1(n5015), .B0(n5150), .B1(n4487), .Y(n2504)
);
OAI22X2TS U4412 ( .A0(n2088), .A1(n5266), .B0(n5289), .B1(n5537), .Y(n1107)
);
OAI22X2TS U4413 ( .A0(n2088), .A1(n4606), .B0(n5289), .B1(n5538), .Y(n1102)
);
OAI22X2TS U4414 ( .A0(n2088), .A1(n5270), .B0(n5287), .B1(n5524), .Y(n1065)
);
OAI22X2TS U4415 ( .A0(n2088), .A1(n5293), .B0(n5292), .B1(n5505), .Y(n1057)
);
AOI21X4TS U4416 ( .A0(n4047), .A1(n5925), .B0(n5924), .Y(n3711) );
MXI2X2TS U4417 ( .A(n5248), .B(n5247), .S0(n2554), .Y(n1121) );
NAND2X6TS U4418 ( .A(n3433), .B(n3452), .Y(n3455) );
AOI21X4TS U4419 ( .A0(n2501), .A1(DmP_mant_SHT1_SW[9]), .B0(n4025), .Y(n6349) );
NOR2X2TS U4420 ( .A(n5342), .B(n2300), .Y(n3752) );
NAND2X4TS U4421 ( .A(n4416), .B(intDX_EWSW[16]), .Y(n4103) );
MXI2X2TS U4422 ( .A(n5273), .B(n5272), .S0(n5265), .Y(n1129) );
INVX8TS U4423 ( .A(n2507), .Y(n2508) );
NAND2X2TS U4424 ( .A(n4412), .B(n1922), .Y(n4097) );
NAND2X2TS U4425 ( .A(n1837), .B(n2957), .Y(n4805) );
NAND2X2TS U4426 ( .A(n4412), .B(intDX_EWSW[45]), .Y(n3604) );
NAND2X2TS U4427 ( .A(n4379), .B(n2028), .Y(n3619) );
NAND2X2TS U4428 ( .A(n4412), .B(intDX_EWSW[42]), .Y(n3613) );
INVX2TS U4429 ( .A(n2537), .Y(n2538) );
INVX8TS U4430 ( .A(n4026), .Y(n6201) );
NOR2X2TS U4431 ( .A(n3858), .B(n4701), .Y(n4703) );
NOR2X2TS U4432 ( .A(n4718), .B(n4717), .Y(n4719) );
OAI22X2TS U4433 ( .A0(n4717), .A1(n4716), .B0(n4718), .B1(n4490), .Y(n2800)
);
BUFX12TS U4434 ( .A(n3858), .Y(n4718) );
BUFX20TS U4435 ( .A(n2510), .Y(n4790) );
AOI22X1TS U4436 ( .A0(n6217), .A1(Raw_mant_NRM_SWR[27]), .B0(n5038), .B1(
n6228), .Y(n6299) );
AOI22X2TS U4437 ( .A0(n6218), .A1(n1913), .B0(n6228), .B1(n5044), .Y(n6348)
);
AOI22X2TS U4438 ( .A0(n6218), .A1(n5029), .B0(n2845), .B1(n5028), .Y(n6326)
);
NAND2X2TS U4439 ( .A(n6219), .B(Raw_mant_NRM_SWR[13]), .Y(n6341) );
NAND2X2TS U4440 ( .A(n6218), .B(Raw_mant_NRM_SWR[7]), .Y(n6385) );
NOR2X2TS U4441 ( .A(n4689), .B(n6410), .Y(n3803) );
NOR2X2TS U4442 ( .A(n4689), .B(n4535), .Y(n4124) );
NAND2X2TS U4443 ( .A(n4425), .B(intDY_EWSW[36]), .Y(n4815) );
NAND2X2TS U4444 ( .A(n4807), .B(intDX_EWSW[31]), .Y(n3654) );
NAND2X2TS U4445 ( .A(n4379), .B(intDX_EWSW[0]), .Y(n4384) );
NAND2X2TS U4446 ( .A(n1837), .B(intDX_EWSW[28]), .Y(n3641) );
NAND2X2TS U4447 ( .A(n4425), .B(intDY_EWSW[16]), .Y(n4102) );
NAND2X2TS U4448 ( .A(n1837), .B(intDX_EWSW[46]), .Y(n3595) );
NAND2X2TS U4449 ( .A(n2116), .B(intDX_EWSW[29]), .Y(n3650) );
NAND2X2TS U4450 ( .A(n4863), .B(intDX_EWSW[49]), .Y(n4394) );
BUFX20TS U4451 ( .A(n6217), .Y(n2925) );
NAND2X2TS U4452 ( .A(n4807), .B(intDX_EWSW[57]), .Y(n4371) );
NAND2X2TS U4453 ( .A(n4425), .B(intDY_EWSW[7]), .Y(n3820) );
NAND2X2TS U4454 ( .A(n1837), .B(intDX_EWSW[55]), .Y(n4238) );
NAND2X2TS U4455 ( .A(n4863), .B(intDY_EWSW[44]), .Y(n3579) );
NAND2X2TS U4456 ( .A(n4412), .B(intDX_EWSW[56]), .Y(n4235) );
NAND2X2TS U4457 ( .A(n2049), .B(intDX_EWSW[21]), .Y(n3635) );
NAND2X2TS U4458 ( .A(n4873), .B(intDY_EWSW[6]), .Y(n4112) );
NAND2X2TS U4459 ( .A(n1837), .B(intDX_EWSW[33]), .Y(n3628) );
NAND2X4TS U4460 ( .A(n3797), .B(n2384), .Y(n3241) );
CLKINVX3TS U4461 ( .A(n2537), .Y(n2515) );
INVX6TS U4462 ( .A(n2395), .Y(n2518) );
INVX16TS U4463 ( .A(n3238), .Y(n3261) );
INVX8TS U4464 ( .A(n5495), .Y(n5315) );
NOR2X2TS U4465 ( .A(n4730), .B(n2524), .Y(n4731) );
OAI22X2TS U4466 ( .A0(n6214), .A1(n1857), .B0(n5061), .B1(n5048), .Y(n6399)
);
OAI22X2TS U4467 ( .A0(n6214), .A1(n3298), .B0(n6231), .B1(n5050), .Y(n6305)
);
OAI22X2TS U4468 ( .A0(n6214), .A1(n5581), .B0(n6231), .B1(n2607), .Y(n6319)
);
OAI22X2TS U4469 ( .A0(n6214), .A1(n5491), .B0(n6231), .B1(n5052), .Y(n6324)
);
OAI22X2TS U4470 ( .A0(n6214), .A1(n5342), .B0(n6231), .B1(n5049), .Y(n6339)
);
OAI22X2TS U4471 ( .A0(n6214), .A1(n5438), .B0(n6231), .B1(n5057), .Y(n6323)
);
AOI2BB2X2TS U4472 ( .B0(n2501), .B1(DmP_mant_SHT1_SW[20]), .A0N(n5573),
.A1N(n6214), .Y(n6318) );
OAI22X2TS U4473 ( .A0(n2527), .A1(n5427), .B0(n6231), .B1(n5059), .Y(n6301)
);
OAI22X2TS U4474 ( .A0(n6214), .A1(n5423), .B0(n5061), .B1(n5056), .Y(n6366)
);
OAI22X2TS U4475 ( .A0(n2527), .A1(n5439), .B0(n5061), .B1(n5062), .Y(n6379)
);
OAI22X2TS U4476 ( .A0(n2527), .A1(n5437), .B0(n5061), .B1(n5058), .Y(n6295)
);
OAI22X2TS U4477 ( .A0(n2527), .A1(n5570), .B0(n5061), .B1(n5053), .Y(n6364)
);
NAND2X2TS U4478 ( .A(n2963), .B(intDY_EWSW[4]), .Y(n4073) );
NAND2X2TS U4479 ( .A(n4424), .B(intDY_EWSW[16]), .Y(n3664) );
NAND2X2TS U4480 ( .A(n3124), .B(n2035), .Y(n3667) );
NAND2X2TS U4481 ( .A(n2530), .B(intDY_EWSW[17]), .Y(n3670) );
CLKINVX3TS U4482 ( .A(n2537), .Y(n2532) );
CLKINVX6TS U4483 ( .A(Shift_reg_FLAGS_7_6), .Y(n2535) );
CLKINVX6TS U4484 ( .A(Shift_reg_FLAGS_7_6), .Y(n2536) );
CLKINVX3TS U4485 ( .A(n2537), .Y(n2539) );
NAND2X1TS U4486 ( .A(n2500), .B(DmP_mant_SHT1_SW[6]), .Y(n6383) );
NAND2X1TS U4487 ( .A(n6203), .B(DmP_mant_SHT1_SW[0]), .Y(n6328) );
CLKBUFX3TS U4488 ( .A(n6292), .Y(n6286) );
INVX12TS U4489 ( .A(Shift_reg_FLAGS_7[2]), .Y(n4917) );
NOR2X2TS U4490 ( .A(n4702), .B(n4535), .Y(n4536) );
OAI22X2TS U4491 ( .A0(n4689), .A1(n4521), .B0(n4702), .B1(n4053), .Y(n4054)
);
NAND2X2TS U4492 ( .A(n1919), .B(n4523), .Y(n4526) );
NAND2X2TS U4493 ( .A(n1919), .B(n1645), .Y(n4639) );
BUFX8TS U4494 ( .A(n2764), .Y(n2554) );
NOR2X1TS U4495 ( .A(n2554), .B(n1876), .Y(n2875) );
NOR2X2TS U4496 ( .A(n2880), .B(n2554), .Y(n2879) );
OAI21X2TS U4497 ( .A0(n2881), .A1(n5265), .B0(n2886), .Y(n2878) );
MXI2X2TS U4498 ( .A(n5270), .B(n5269), .S0(n5264), .Y(n1132) );
NAND2X4TS U4499 ( .A(n3846), .B(n5024), .Y(n4040) );
INVX16TS U4500 ( .A(n3846), .Y(n4662) );
BUFX16TS U4501 ( .A(n3804), .Y(n2558) );
NAND2X2TS U4502 ( .A(n2558), .B(n5024), .Y(n4291) );
NAND2X2TS U4503 ( .A(n4659), .B(n5033), .Y(n3966) );
NAND2X8TS U4504 ( .A(n1949), .B(n2558), .Y(n3832) );
NAND2X2TS U4505 ( .A(n2041), .B(intDY_EWSW[2]), .Y(n4880) );
NAND2X2TS U4506 ( .A(n1836), .B(intDX_EWSW[21]), .Y(n4862) );
NAND2X2TS U4507 ( .A(n1836), .B(intDY_EWSW[11]), .Y(n4144) );
NAND2X2TS U4508 ( .A(n1836), .B(intDX_EWSW[2]), .Y(n4375) );
NAND2X2TS U4509 ( .A(n2531), .B(intDX_EWSW[1]), .Y(n4378) );
NAND2X2TS U4510 ( .A(n2526), .B(intDX_EWSW[0]), .Y(n4382) );
NOR2X8TS U4511 ( .A(n2764), .B(n2560), .Y(n4543) );
CLKBUFX2TS U4512 ( .A(n6262), .Y(n2566) );
CLKBUFX2TS U4513 ( .A(n2569), .Y(n2567) );
CLKBUFX2TS U4514 ( .A(n2569), .Y(n2568) );
CLKBUFX2TS U4515 ( .A(n2541), .Y(n2569) );
XOR2X4TS U4516 ( .A(intDY_EWSW[63]), .B(intAS), .Y(n4729) );
CLKMX2X2TS U4517 ( .A(n5296), .B(Shift_amount_SHT1_EWR[2]), .S0(n2547), .Y(
n1602) );
AOI22X2TS U4518 ( .A0(n4906), .A1(Shift_amount_SHT1_EWR[2]), .B0(
shift_value_SHT2_EWR[2]), .B1(n6230), .Y(n4907) );
AOI22X1TS U4519 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[46]), .B0(n2873), .B1(
n5039), .Y(n6384) );
AOI22X1TS U4520 ( .A0(n6217), .A1(n2345), .B0(n5041), .B1(n5030), .Y(n6358)
);
AOI21X4TS U4521 ( .A0(n2577), .A1(n4711), .B0(n2574), .Y(n2573) );
NAND2X8TS U4522 ( .A(n2583), .B(n2580), .Y(n5054) );
NOR2X8TS U4523 ( .A(n2586), .B(n2584), .Y(n2583) );
OAI21X4TS U4524 ( .A0(n6035), .A1(n6034), .B0(n2585), .Y(n2584) );
NAND2BX4TS U4525 ( .AN(n5918), .B(n2587), .Y(n2586) );
AOI22X4TS U4526 ( .A0(n5157), .A1(n5145), .B0(n2691), .B1(n2518), .Y(n6440)
);
NAND4BBX4TS U4527 ( .AN(n4676), .BN(n4680), .C(n2591), .D(n2590), .Y(n6439)
);
OAI21X2TS U4528 ( .A0(n2597), .A1(n1868), .B0(n2761), .Y(n1025) );
AOI22X4TS U4529 ( .A0(n4651), .A1(n1878), .B0(n3365), .B1(n4686), .Y(n2597)
);
NAND2X8TS U4530 ( .A(n4612), .B(n1872), .Y(n2602) );
NAND2BX4TS U4531 ( .AN(n4323), .B(n2604), .Y(n2603) );
INVX2TS U4532 ( .A(n6411), .Y(n2605) );
INVX12TS U4533 ( .A(n4322), .Y(n6411) );
NAND2X8TS U4534 ( .A(n2608), .B(n2614), .Y(n4612) );
OAI22X4TS U4535 ( .A0(n5273), .A1(n2088), .B0(n5287), .B1(n5522), .Y(n1066)
);
CLKINVX12TS U4536 ( .A(n4895), .Y(n2615) );
NAND2X8TS U4537 ( .A(n3763), .B(n3730), .Y(n4895) );
NOR2X8TS U4538 ( .A(n2268), .B(n2617), .Y(n4249) );
NAND2X8TS U4539 ( .A(n3187), .B(n3195), .Y(n2618) );
NOR2BX4TS U4540 ( .AN(n2622), .B(n3794), .Y(n2621) );
NAND2X8TS U4541 ( .A(n4280), .B(n4273), .Y(n3781) );
NAND4X8TS U4542 ( .A(n2623), .B(n5342), .C(n5431), .D(n2378), .Y(n2624) );
NOR2X8TS U4543 ( .A(Raw_mant_NRM_SWR[26]), .B(Raw_mant_NRM_SWR[25]), .Y(
n4250) );
NOR3X8TS U4544 ( .A(n2626), .B(n2625), .C(n2624), .Y(n4347) );
NAND3X8TS U4545 ( .A(n3070), .B(n3069), .C(n1921), .Y(n3068) );
NAND2X2TS U4546 ( .A(n2628), .B(DMP_SFG[31]), .Y(n4984) );
INVX12TS U4547 ( .A(n4708), .Y(n4698) );
AND2X8TS U4548 ( .A(n1919), .B(n4681), .Y(n4708) );
NAND4BX4TS U4549 ( .AN(n3947), .B(n3946), .C(n6172), .D(n3945), .Y(n5030) );
NAND4BX4TS U4550 ( .AN(n3927), .B(n3926), .C(n3924), .D(n3925), .Y(n1626) );
OAI21X4TS U4551 ( .A0(n3472), .A1(n3473), .B0(n3471), .Y(n3479) );
NAND2X4TS U4552 ( .A(n3327), .B(intDY_EWSW[2]), .Y(n3415) );
NAND4X4TS U4553 ( .A(n2729), .B(n2727), .C(n2726), .D(n2724), .Y(n1146) );
NAND2X4TS U4554 ( .A(n3002), .B(n3001), .Y(n3000) );
NOR2X8TS U4555 ( .A(n2676), .B(DMP_SFG[28]), .Y(n4785) );
XOR2X4TS U4556 ( .A(n5088), .B(n5087), .Y(n5090) );
OAI22X4TS U4557 ( .A0(n5257), .A1(n2990), .B0(n5292), .B1(n5531), .Y(n1083)
);
AOI22X2TS U4558 ( .A0(n2637), .A1(n5147), .B0(n4608), .B1(n5158), .Y(n3080)
);
OAI2BB1X4TS U4559 ( .A0N(n5149), .A1N(n6459), .B0(n5142), .Y(n1029) );
AOI21X4TS U4560 ( .A0(n4685), .A1(n4686), .B0(n2639), .Y(n2638) );
NAND3BX4TS U4561 ( .AN(n1897), .B(n4329), .C(n4330), .Y(n4686) );
NAND2X8TS U4562 ( .A(n4257), .B(n3746), .Y(n2647) );
NOR2X8TS U4563 ( .A(n2985), .B(n3149), .Y(n5027) );
NAND2X8TS U4564 ( .A(n2677), .B(n4909), .Y(n2649) );
XNOR2X4TS U4565 ( .A(DmP_mant_SFG_SWR[25]), .B(n1839), .Y(n2650) );
OAI21X4TS U4566 ( .A0(n2655), .A1(n2550), .B0(n2654), .Y(n1167) );
NAND2X1TS U4567 ( .A(n2551), .B(Raw_mant_NRM_SWR[31]), .Y(n2654) );
XNOR2X4TS U4568 ( .A(n2656), .B(n5329), .Y(n2655) );
AND2X8TS U4569 ( .A(n5472), .B(n2917), .Y(n4766) );
NAND2X8TS U4570 ( .A(n4781), .B(n2667), .Y(n2902) );
NOR2X8TS U4571 ( .A(n4785), .B(n5327), .Y(n2667) );
NOR2X8TS U4572 ( .A(n3391), .B(DMP_SFG[29]), .Y(n5327) );
XNOR2X4TS U4573 ( .A(n1853), .B(DmP_mant_SFG_SWR[30]), .Y(n2657) );
NAND2BX4TS U4574 ( .AN(n3175), .B(n2402), .Y(n3174) );
NAND2X4TS U4575 ( .A(n2677), .B(n2662), .Y(n2660) );
OAI21X4TS U4576 ( .A0(n2666), .A1(n5005), .B0(n3186), .Y(n1153) );
NAND3X8TS U4577 ( .A(n2435), .B(n2671), .C(n2668), .Y(n1155) );
NAND2X8TS U4578 ( .A(n2674), .B(n2672), .Y(n2716) );
AOI2BB1X4TS U4579 ( .A0N(n5323), .A1N(n5327), .B0(n3166), .Y(n2672) );
NAND2X4TS U4580 ( .A(DMP_SFG[29]), .B(n3391), .Y(n2673) );
NAND2X8TS U4581 ( .A(n2676), .B(DMP_SFG[28]), .Y(n5323) );
NAND2X8TS U4582 ( .A(n2675), .B(n4775), .Y(n4780) );
OAI21X4TS U4583 ( .A0(n3556), .A1(n3555), .B0(n3554), .Y(n2682) );
NAND2X6TS U4584 ( .A(n2684), .B(n2683), .Y(n3559) );
AOI21X4TS U4585 ( .A0(n2688), .A1(n3553), .B0(n2686), .Y(n2685) );
OAI21X4TS U4586 ( .A0(n2705), .A1(n3552), .B0(n3551), .Y(n2686) );
NOR2X8TS U4587 ( .A(n3309), .B(intDY_EWSW[50]), .Y(n2687) );
OAI22X4TS U4588 ( .A0(n3550), .A1(n2689), .B0(intDX_EWSW[49]), .B1(n2376),
.Y(n2688) );
NOR2X8TS U4589 ( .A(n2990), .B(n4477), .Y(n2690) );
AOI22X2TS U4590 ( .A0(n5157), .A1(n5158), .B0(n2516), .B1(n2691), .Y(n6433)
);
AOI22X4TS U4591 ( .A0(n4604), .A1(n2522), .B0(n5158), .B1(n2691), .Y(n5270)
);
NAND3X8TS U4592 ( .A(n2695), .B(n2702), .C(n2692), .Y(n2701) );
CLKINVX12TS U4593 ( .A(n2693), .Y(n2692) );
NOR2X8TS U4594 ( .A(n2701), .B(n2700), .Y(n2699) );
NOR2X8TS U4595 ( .A(n3313), .B(intDY_EWSW[51]), .Y(n2705) );
NOR2X8TS U4596 ( .A(n3347), .B(intDY_EWSW[61]), .Y(n3561) );
INVX16TS U4597 ( .A(n2710), .Y(n6215) );
XOR2X4TS U4598 ( .A(n1853), .B(n2758), .Y(n2917) );
NAND2X8TS U4599 ( .A(n2716), .B(n3218), .Y(n3165) );
OAI22X4TS U4600 ( .A0(n2714), .A1(n2368), .B0(n4937), .B1(n3069), .Y(n3206)
);
OR2X8TS U4601 ( .A(n2715), .B(n4937), .Y(n2714) );
NOR2X8TS U4602 ( .A(n4936), .B(n4962), .Y(n2715) );
OAI21X4TS U4603 ( .A0(n2719), .A1(n5005), .B0(n2718), .Y(n1147) );
INVX3TS U4604 ( .A(n2909), .Y(n2722) );
NAND2X8TS U4605 ( .A(n3008), .B(n3011), .Y(n2736) );
NAND3X8TS U4606 ( .A(n3182), .B(n3256), .C(n2397), .Y(n2788) );
CLKBUFX2TS U4607 ( .A(n5097), .Y(n2738) );
NAND2X6TS U4608 ( .A(n2739), .B(n5069), .Y(n3221) );
NAND2X4TS U4609 ( .A(n5065), .B(n3370), .Y(n2739) );
BUFX6TS U4610 ( .A(intDY_EWSW[34]), .Y(n2740) );
OAI21X4TS U4611 ( .A0(n3438), .A1(n2267), .B0(n2741), .Y(n3444) );
NOR2X8TS U4612 ( .A(n3319), .B(intDY_EWSW[9]), .Y(n3438) );
NOR2X6TS U4613 ( .A(n3488), .B(n3466), .Y(n3489) );
INVX8TS U4614 ( .A(n4062), .Y(n4644) );
NAND2BX4TS U4615 ( .AN(n3851), .B(n3848), .Y(n3095) );
NOR2X8TS U4616 ( .A(n3290), .B(intDY_EWSW[15]), .Y(n3450) );
NAND2X2TS U4617 ( .A(n4721), .B(n2516), .Y(n4627) );
OR2X8TS U4618 ( .A(n3092), .B(n2396), .Y(n5141) );
OAI21X4TS U4619 ( .A0(n2743), .A1(n3430), .B0(n2912), .Y(n3459) );
AOI21X4TS U4620 ( .A0(n3417), .A1(n3418), .B0(n2746), .Y(n2743) );
NAND2X8TS U4621 ( .A(n2967), .B(n2978), .Y(n2977) );
NOR2X6TS U4622 ( .A(n3292), .B(intDY_EWSW[27]), .Y(n3488) );
NAND2X2TS U4623 ( .A(n3312), .B(intDY_EWSW[31]), .Y(n3494) );
BUFX6TS U4624 ( .A(intDY_EWSW[28]), .Y(n2745) );
OAI21X4TS U4625 ( .A0(n3415), .A1(n3416), .B0(n3414), .Y(n2746) );
NAND2X2TS U4626 ( .A(n3355), .B(intDY_EWSW[14]), .Y(n3449) );
NAND2X2TS U4627 ( .A(n4658), .B(n5037), .Y(n4119) );
NAND2X2TS U4628 ( .A(n2529), .B(n5038), .Y(n3963) );
NAND2X2TS U4629 ( .A(n1627), .B(n2780), .Y(n4120) );
NOR2X6TS U4630 ( .A(n3435), .B(n3441), .Y(n3443) );
NAND2X8TS U4631 ( .A(n5183), .B(n2330), .Y(n3116) );
NAND2X8TS U4632 ( .A(n4476), .B(n3117), .Y(n5183) );
NAND2X4TS U4633 ( .A(n3467), .B(n3489), .Y(n3468) );
NAND2X4TS U4634 ( .A(n3346), .B(intDY_EWSW[36]), .Y(n3525) );
NOR2X8TS U4635 ( .A(n4254), .B(n4027), .Y(n4338) );
NOR2X4TS U4636 ( .A(n3314), .B(intDY_EWSW[52]), .Y(n3511) );
NOR2X4TS U4637 ( .A(n3361), .B(intDY_EWSW[26]), .Y(n3466) );
OAI21X2TS U4638 ( .A0(n4662), .A1(n4661), .B0(n4660), .Y(n4667) );
NOR2X2TS U4639 ( .A(n5900), .B(n2143), .Y(n3853) );
NAND2X2TS U4640 ( .A(n4659), .B(n5055), .Y(n3808) );
INVX8TS U4641 ( .A(n2846), .Y(n2914) );
INVX6TS U4642 ( .A(n2902), .Y(n4959) );
AOI2BB1X4TS U4643 ( .A0N(n4678), .A1N(n4698), .B0(n3837), .Y(n3074) );
NAND3X8TS U4644 ( .A(n3149), .B(n3202), .C(n2562), .Y(n2981) );
NOR2X4TS U4645 ( .A(n3434), .B(n3438), .Y(n3436) );
NAND2X8TS U4646 ( .A(n3793), .B(n3735), .Y(n2748) );
NOR2X8TS U4647 ( .A(n4934), .B(n2846), .Y(n4935) );
NOR2X4TS U4648 ( .A(n3324), .B(intDY_EWSW[4]), .Y(n3419) );
OAI22X2TS U4649 ( .A0(n2453), .A1(n5286), .B0(n5287), .B1(n5503), .Y(n1588)
);
NAND2X4TS U4650 ( .A(n6449), .B(n4543), .Y(n4510) );
AOI22X2TS U4651 ( .A0(n6218), .A1(Raw_mant_NRM_SWR[29]), .B0(n5036), .B1(
n2845), .Y(n6401) );
NOR2X4TS U4652 ( .A(n3413), .B(n3416), .Y(n3417) );
CLKINVX12TS U4653 ( .A(n4268), .Y(n3793) );
BUFX20TS U4654 ( .A(n4250), .Y(n2766) );
OAI21X4TS U4655 ( .A0(n3441), .A1(n3440), .B0(n3439), .Y(n3442) );
NAND2X4TS U4656 ( .A(n3363), .B(intDY_EWSW[42]), .Y(n3533) );
NAND2X2TS U4657 ( .A(n4479), .B(n4478), .Y(n1035) );
INVX2TS U4658 ( .A(n3754), .Y(n2749) );
XOR2X4TS U4659 ( .A(n4015), .B(DMP_exp_NRM2_EW[10]), .Y(n5286) );
XOR2X4TS U4660 ( .A(n2309), .B(n3979), .Y(n5164) );
AOI21X4TS U4661 ( .A0(n3545), .A1(n3546), .B0(n3544), .Y(n3547) );
OAI21X4TS U4662 ( .A0(n3476), .A1(n3475), .B0(n3474), .Y(n3477) );
BUFX6TS U4663 ( .A(n4895), .Y(n2751) );
OAI21X4TS U4664 ( .A0(n3485), .A1(n3484), .B0(n3483), .Y(n3490) );
NAND2X2TS U4665 ( .A(n4637), .B(n5025), .Y(n4082) );
NOR2X8TS U4666 ( .A(n5094), .B(n3380), .Y(n2752) );
MX2X4TS U4667 ( .A(n6420), .B(n5566), .S0(n5224), .Y(n5130) );
INVX16TS U4668 ( .A(n4095), .Y(n4026) );
NAND3X6TS U4669 ( .A(n3174), .B(n3914), .C(n3173), .Y(n3180) );
NAND2X8TS U4670 ( .A(n5278), .B(n6293), .Y(n3128) );
NAND2X8TS U4671 ( .A(n2944), .B(n3131), .Y(n5278) );
NAND2X4TS U4672 ( .A(n2762), .B(n2856), .Y(n3388) );
AOI21X4TS U4673 ( .A0(n4753), .A1(n3297), .B0(n3387), .Y(n2762) );
OR2X8TS U4674 ( .A(n2840), .B(n5478), .Y(n5097) );
XNOR2X4TS U4675 ( .A(n2489), .B(DmP_mant_SFG_SWR[18]), .Y(n2840) );
NAND3X8TS U4676 ( .A(n2422), .B(n3112), .C(n2914), .Y(n4920) );
NAND4X4TS U4677 ( .A(n3229), .B(n3223), .C(n3224), .D(n3228), .Y(n1150) );
XOR2X4TS U4678 ( .A(n2487), .B(DmP_mant_SFG_SWR[44]), .Y(n3405) );
NAND2X4TS U4679 ( .A(n3436), .B(n3443), .Y(n3437) );
OAI21X4TS U4680 ( .A0(n3175), .A1(n3908), .B0(n3211), .Y(n3210) );
OAI21X4TS U4681 ( .A0(n3412), .A1(n3411), .B0(n3410), .Y(n3418) );
OAI21X4TS U4682 ( .A0(n3534), .A1(n3533), .B0(n3532), .Y(n3535) );
NAND2X4TS U4683 ( .A(n6396), .B(n6369), .Y(n4438) );
NOR2X4TS U4684 ( .A(n3004), .B(n3003), .Y(n3002) );
NAND2X4TS U4685 ( .A(n4633), .B(n4711), .Y(n2887) );
OAI21X4TS U4686 ( .A0(n3450), .A1(n3449), .B0(n3448), .Y(n3451) );
NAND2X2TS U4687 ( .A(n4482), .B(n4481), .Y(n1051) );
AOI22X4TS U4688 ( .A0(n4496), .A1(n2449), .B0(n5155), .B1(n4645), .Y(n4652)
);
NOR2X4TS U4689 ( .A(n4480), .B(n5125), .Y(n4542) );
NAND3X8TS U4690 ( .A(n2765), .B(n4599), .C(n4598), .Y(n4635) );
NAND2X2TS U4691 ( .A(n4658), .B(n5016), .Y(n4529) );
NAND2X8TS U4692 ( .A(n2872), .B(n3797), .Y(n4069) );
OA21X4TS U4693 ( .A0(n3549), .A1(n3548), .B0(n3547), .Y(n2933) );
NOR2X4TS U4694 ( .A(n3463), .B(n3493), .Y(n3465) );
NAND4X4TS U4695 ( .A(n3776), .B(n3778), .C(n3777), .D(n1989), .Y(n3780) );
NOR2X4TS U4696 ( .A(n2428), .B(n2975), .Y(n6317) );
NOR2X2TS U4697 ( .A(n4720), .B(n4719), .Y(n4727) );
NOR2X4TS U4698 ( .A(n3353), .B(intDY_EWSW[10]), .Y(n3435) );
AOI21X4TS U4699 ( .A0(n3444), .A1(n3443), .B0(n3442), .Y(n3456) );
OAI2BB1X4TS U4700 ( .A0N(n5749), .A1N(n5750), .B0(n2770), .Y(n5051) );
AND3X8TS U4701 ( .A(n2773), .B(n2771), .C(n3838), .Y(n2770) );
OAI21X4TS U4702 ( .A0(n2777), .A1(n2547), .B0(n2776), .Y(n1600) );
XNOR2X4TS U4703 ( .A(n5308), .B(n5309), .Y(n2777) );
NAND2X8TS U4704 ( .A(n5294), .B(n5302), .Y(n2779) );
NAND2X8TS U4705 ( .A(n3033), .B(n5310), .Y(n5294) );
NAND3X8TS U4706 ( .A(n2781), .B(n3971), .C(n3970), .Y(n5024) );
XOR2X4TS U4707 ( .A(DmP_mant_SFG_SWR[42]), .B(n6161), .Y(n3402) );
NOR2X8TS U4708 ( .A(n3325), .B(intDY_EWSW[0]), .Y(n3412) );
NAND2X8TS U4709 ( .A(n2790), .B(n4008), .Y(n3994) );
OR2X8TS U4710 ( .A(n4007), .B(n4012), .Y(n2790) );
NOR2X8TS U4711 ( .A(n3369), .B(DMP_exp_NRM2_EW[5]), .Y(n4007) );
NAND4X8TS U4712 ( .A(n2216), .B(n2920), .C(n4043), .D(n2420), .Y(n4707) );
NAND2X8TS U4713 ( .A(n3968), .B(n2794), .Y(n5018) );
AOI22X4TS U4714 ( .A0(n4619), .A1(n2560), .B0(n4618), .B1(n5145), .Y(n4145)
);
AOI2BB1X4TS U4715 ( .A0N(n4669), .A1N(n4489), .B0(n2800), .Y(n2799) );
AOI21X4TS U4716 ( .A0(n2807), .A1(n3560), .B0(n2803), .Y(n3567) );
OAI22X4TS U4717 ( .A0(n2806), .A1(n2804), .B0(intDX_EWSW[59]), .B1(n2374),
.Y(n2803) );
NOR2X8TS U4718 ( .A(n2806), .B(n2805), .Y(n3560) );
NOR2X8TS U4719 ( .A(n3339), .B(intDY_EWSW[58]), .Y(n2805) );
NOR2X8TS U4720 ( .A(n3344), .B(intDY_EWSW[59]), .Y(n2806) );
NAND3X8TS U4721 ( .A(n2811), .B(n2810), .C(n2809), .Y(n5036) );
OAI2BB1X4TS U4722 ( .A0N(n5161), .A1N(n6437), .B0(n5152), .Y(n1048) );
NAND3BX4TS U4723 ( .AN(n2815), .B(n4714), .C(n4713), .Y(n6437) );
NOR2X8TS U4724 ( .A(n3326), .B(intDY_EWSW[3]), .Y(n3416) );
AOI2BB2X4TS U4725 ( .B0(n4496), .B1(n2560), .A0N(n2283), .A1N(n2825), .Y(
n4631) );
NAND3BX4TS U4726 ( .AN(n4690), .B(n4694), .C(n2829), .Y(n6455) );
XNOR2X4TS U4727 ( .A(n5418), .B(n2257), .Y(n3890) );
NOR2X8TS U4728 ( .A(n2833), .B(n2832), .Y(n2831) );
NOR2BX4TS U4729 ( .AN(n6111), .B(n2838), .Y(n2837) );
NOR2X8TS U4730 ( .A(DMP_SFG[33]), .B(n2842), .Y(n4939) );
NAND2X4TS U4731 ( .A(DMP_SFG[33]), .B(n2842), .Y(n4940) );
NOR2X8TS U4732 ( .A(n2844), .B(DMP_SFG[32]), .Y(n4931) );
XOR2X4TS U4733 ( .A(DmP_mant_SFG_SWR[34]), .B(n1853), .Y(n2844) );
INVX16TS U4734 ( .A(n2845), .Y(n4332) );
NOR2X8TS U4735 ( .A(n2383), .B(n2561), .Y(n2845) );
AOI22X1TS U4736 ( .A0(n4906), .A1(n2570), .B0(n6229), .B1(n2330), .Y(n4904)
);
NOR2X8TS U4737 ( .A(n2902), .B(n3214), .Y(n3213) );
NOR2X8TS U4738 ( .A(Raw_mant_NRM_SWR[38]), .B(Raw_mant_NRM_SWR[37]), .Y(
n3767) );
NOR2X8TS U4739 ( .A(n1856), .B(Raw_mant_NRM_SWR[3]), .Y(n4892) );
OAI2BB1X4TS U4740 ( .A0N(n2203), .A1N(n6103), .B0(n6102), .Y(n4300) );
OAI2BB1X4TS U4741 ( .A0N(n2560), .A1N(n4302), .B0(n2852), .Y(n2992) );
NOR2X8TS U4742 ( .A(n3235), .B(n2854), .Y(n4095) );
NAND3X4TS U4743 ( .A(n3295), .B(n3297), .C(n1920), .Y(n2856) );
OR2X8TS U4744 ( .A(n3548), .B(n2858), .Y(n3010) );
NOR2X8TS U4745 ( .A(n3534), .B(n2861), .Y(n3536) );
NOR2X8TS U4746 ( .A(n3293), .B(intDY_EWSW[43]), .Y(n3534) );
NOR2X8TS U4747 ( .A(n3543), .B(n2864), .Y(n3545) );
NOR2X8TS U4748 ( .A(n3305), .B(intDY_EWSW[47]), .Y(n3543) );
NAND3X8TS U4749 ( .A(n2869), .B(n2865), .C(n2038), .Y(n3795) );
NAND2X8TS U4750 ( .A(n2872), .B(n2871), .Y(n6353) );
NOR2BX4TS U4751 ( .AN(n3797), .B(n6229), .Y(n2871) );
AOI21X4TS U4752 ( .A0(n2876), .A1(n2449), .B0(n2381), .Y(n3322) );
NAND2BX4TS U4753 ( .AN(n4522), .B(n2887), .Y(n2885) );
NAND3X8TS U4754 ( .A(n3760), .B(n4896), .C(n3761), .Y(n4340) );
NAND2X8TS U4755 ( .A(n3265), .B(n2910), .Y(n4254) );
NOR2X8TS U4756 ( .A(n2742), .B(n3764), .Y(n2888) );
CLKINVX12TS U4757 ( .A(n2890), .Y(n2889) );
NOR2X8TS U4758 ( .A(Raw_mant_NRM_SWR[51]), .B(Raw_mant_NRM_SWR[52]), .Y(
n3789) );
AND2X8TS U4759 ( .A(n3729), .B(n3767), .Y(n2892) );
OR2X8TS U4760 ( .A(n4336), .B(n4341), .Y(n2901) );
OR2X8TS U4761 ( .A(n4342), .B(n5441), .Y(n4336) );
NAND2X8TS U4762 ( .A(n2766), .B(n2054), .Y(n4342) );
OAI21X4TS U4763 ( .A0(n2908), .A1(n5005), .B0(n2907), .Y(n5330) );
NOR2X8TS U4764 ( .A(Raw_mant_NRM_SWR[14]), .B(Raw_mant_NRM_SWR[18]), .Y(
n3730) );
NAND2X2TS U4765 ( .A(n3313), .B(intDY_EWSW[51]), .Y(n3551) );
NAND2X2TS U4766 ( .A(n3352), .B(intDY_EWSW[7]), .Y(n3425) );
AOI21X4TS U4767 ( .A0(n3429), .A1(n3428), .B0(n3427), .Y(n2912) );
NAND2X8TS U4768 ( .A(n2913), .B(n2933), .Y(n3008) );
NAND2X2TS U4769 ( .A(n3357), .B(n2250), .Y(n3483) );
NAND2X2TS U4770 ( .A(n3361), .B(intDY_EWSW[26]), .Y(n3487) );
NAND2X2TS U4771 ( .A(n1950), .B(n5275), .Y(n3724) );
AOI22X4TS U4772 ( .A0(n5263), .A1(n1877), .B0(n5262), .B1(n5274), .Y(n5293)
);
OAI21X4TS U4773 ( .A0(n3482), .A1(n3481), .B0(n3480), .Y(n3505) );
NOR2X4TS U4774 ( .A(n3303), .B(intDY_EWSW[20]), .Y(n3460) );
NAND2X2TS U4775 ( .A(n4721), .B(n4685), .Y(n4726) );
OAI2BB1X4TS U4776 ( .A0N(n5149), .A1N(n6461), .B0(n5137), .Y(n1028) );
NAND2X2TS U4777 ( .A(n3326), .B(intDY_EWSW[3]), .Y(n3414) );
NAND2X2TS U4778 ( .A(n4637), .B(n5275), .Y(n4592) );
NAND2X2TS U4779 ( .A(n3587), .B(intDX_EWSW[3]), .Y(n4405) );
AOI21X4TS U4780 ( .A0(n3453), .A1(n3452), .B0(n3451), .Y(n3454) );
INVX16TS U4781 ( .A(n4268), .Y(n4257) );
NOR2X2TS U4782 ( .A(n4596), .B(n4595), .Y(n4598) );
NOR2BX4TS U4783 ( .AN(n2918), .B(n3775), .Y(n3776) );
NOR2BX4TS U4784 ( .AN(n2919), .B(Raw_mant_NRM_SWR[2]), .Y(n2918) );
NAND4X2TS U4785 ( .A(n4594), .B(n6143), .C(n6142), .D(n6141), .Y(n5039) );
NAND3X2TS U4786 ( .A(n6085), .B(n6084), .C(n6083), .Y(n3969) );
NAND2X2TS U4787 ( .A(n2022), .B(n2517), .Y(n4634) );
NOR2X6TS U4788 ( .A(n3517), .B(n3566), .Y(n3569) );
NAND2X2TS U4789 ( .A(n4511), .B(n4510), .Y(n1053) );
OAI21X4TS U4790 ( .A0(n4145), .A1(n1868), .B0(n2922), .Y(n1024) );
AOI21X4TS U4791 ( .A0(n3537), .A1(n3536), .B0(n3535), .Y(n3549) );
NOR2X2TS U4792 ( .A(n4258), .B(n5433), .Y(n3746) );
OAI22X4TS U4793 ( .A0(n5261), .A1(n2990), .B0(n5292), .B1(n5532), .Y(n1103)
);
NAND2X8TS U4794 ( .A(n3845), .B(n2926), .Y(n4671) );
NAND2X2TS U4795 ( .A(n3301), .B(n2299), .Y(n3538) );
OAI21X4TS U4796 ( .A0(n3540), .A1(n3539), .B0(n3538), .Y(n3546) );
OAI21X2TS U4797 ( .A0(n4969), .A1(n4993), .B0(n4994), .Y(n4970) );
NAND2X2TS U4798 ( .A(n6219), .B(Raw_mant_NRM_SWR[3]), .Y(n6355) );
NAND2X2TS U4799 ( .A(n3342), .B(intDY_EWSW[23]), .Y(n3474) );
OAI2BB1X4TS U4800 ( .A0N(n5149), .A1N(n6437), .B0(n5146), .Y(n1038) );
AOI22X4TS U4801 ( .A0(n3365), .A1(n5151), .B0(n2518), .B1(n5150), .Y(n6438)
);
NAND2X2TS U4802 ( .A(n2780), .B(n5014), .Y(n3941) );
NOR2X2TS U4803 ( .A(n3832), .B(n4534), .Y(n4517) );
NOR2X6TS U4804 ( .A(n3266), .B(n2370), .Y(n3230) );
AOI21X4TS U4805 ( .A0(n3564), .A1(n3563), .B0(n3562), .Y(n3565) );
OAI21X4TS U4806 ( .A0(n3567), .A1(n3566), .B0(n3565), .Y(n3568) );
NAND3BX4TS U4807 ( .AN(n2927), .B(n4033), .C(n4032), .Y(n1628) );
AOI22X4TS U4808 ( .A0(n4297), .A1(n1871), .B0(n4685), .B1(n5154), .Y(n2929)
);
XNOR2X2TS U4809 ( .A(intDX_EWSW[14]), .B(n2024), .Y(n4180) );
NAND2X2TS U4810 ( .A(n3311), .B(n2479), .Y(n3471) );
NOR2X8TS U4811 ( .A(n3390), .B(DMP_SFG[25]), .Y(n3207) );
BUFX20TS U4812 ( .A(n4790), .Y(n4807) );
NAND2X2TS U4813 ( .A(n5136), .B(n3062), .Y(n4626) );
NAND2X2TS U4814 ( .A(n4686), .B(n2518), .Y(n4610) );
NAND2X2TS U4815 ( .A(n4612), .B(n5147), .Y(n4605) );
MXI2X4TS U4816 ( .A(n5254), .B(n5520), .S0(n2554), .Y(n1044) );
INVX8TS U4817 ( .A(n1628), .Y(n4535) );
OAI22X2TS U4818 ( .A0(n3832), .A1(n4535), .B0(n4716), .B1(n4520), .Y(n4037)
);
NAND2X8TS U4819 ( .A(n2405), .B(n3370), .Y(n3380) );
NAND2X4TS U4820 ( .A(n4883), .B(n4882), .Y(n1608) );
NAND4BX4TS U4821 ( .AN(n3709), .B(n3708), .C(n6188), .D(n3707), .Y(n5017) );
OAI2BB1X4TS U4822 ( .A0N(underflow_flag), .A1N(n5571), .B0(n1835), .Y(n1200)
);
NAND2X2TS U4823 ( .A(n3290), .B(intDY_EWSW[15]), .Y(n3448) );
NAND2X4TS U4824 ( .A(n3510), .B(n3553), .Y(n3513) );
OAI21X4TS U4825 ( .A0(n2932), .A1(n5205), .B0(n2931), .Y(n1161) );
XOR2X4TS U4826 ( .A(n4951), .B(n4950), .Y(n2932) );
NAND2X2TS U4827 ( .A(n6218), .B(Raw_mant_NRM_SWR[36]), .Y(n6372) );
NAND2X2TS U4828 ( .A(n4838), .B(intDY_EWSW[55]), .Y(n4459) );
NAND2X4TS U4829 ( .A(n3096), .B(n3093), .Y(n3092) );
NOR2X2TS U4830 ( .A(n4327), .B(n4326), .Y(n4328) );
OR2X8TS U4831 ( .A(n3386), .B(DMP_SFG[22]), .Y(n3297) );
NOR2X2TS U4832 ( .A(n4533), .B(n4532), .Y(n4540) );
NAND2X4TS U4833 ( .A(n4869), .B(n4868), .Y(n1607) );
BUFX6TS U4834 ( .A(n5140), .Y(n2938) );
NAND4X2TS U4835 ( .A(n4273), .B(n4274), .C(n4275), .D(n4272), .Y(n4286) );
NOR2X2TS U4836 ( .A(n4589), .B(n4588), .Y(n4599) );
XOR2X4TS U4837 ( .A(n1143), .B(n6147), .Y(n5747) );
NAND2X2TS U4838 ( .A(n4637), .B(n4707), .Y(n4065) );
BUFX6TS U4839 ( .A(intDY_EWSW[35]), .Y(n2940) );
NOR4X2TS U4840 ( .A(n4165), .B(n4164), .C(n4163), .D(n4162), .Y(n4228) );
OAI22X2TS U4841 ( .A0(n4733), .A1(n5162), .B0(Shift_reg_FLAGS_7_6), .B1(
n5401), .Y(n1523) );
NAND2X4TS U4842 ( .A(n3766), .B(n3264), .Y(n3796) );
NAND2X2TS U4843 ( .A(n2555), .B(n4672), .Y(n4117) );
INVX16TS U4844 ( .A(n2981), .Y(n5046) );
BUFX6TS U4845 ( .A(intDY_EWSW[33]), .Y(n2945) );
OAI21X4TS U4846 ( .A0(n3502), .A1(n3501), .B0(n3500), .Y(n3503) );
OAI22X2TS U4847 ( .A0(n4718), .A1(n4325), .B0(n4702), .B1(n1918), .Y(n3866)
);
NAND2X8TS U4848 ( .A(n2949), .B(n4927), .Y(n4988) );
BUFX20TS U4849 ( .A(n5046), .Y(n6205) );
AOI22X4TS U4850 ( .A0(n2519), .A1(n5141), .B0(n2938), .B1(n5158), .Y(n6416)
);
NOR2X2TS U4851 ( .A(n3801), .B(n3800), .Y(n3811) );
XOR2X4TS U4852 ( .A(DmP_mant_SFG_SWR[47]), .B(n2487), .Y(n3876) );
AOI22X4TS U4853 ( .A0(n2519), .A1(n5136), .B0(n2022), .B1(n5158), .Y(n6414)
);
NAND2X6TS U4854 ( .A(n4602), .B(n4601), .Y(n4692) );
AOI22X2TS U4855 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[32]), .B0(n6199), .B1(
DmP_mant_SHT1_SW[17]), .Y(n6296) );
AOI22X2TS U4856 ( .A0(n6218), .A1(Raw_mant_NRM_SWR[8]), .B0(n6199), .B1(
DmP_mant_SHT1_SW[41]), .Y(n6380) );
AOI21X4TS U4857 ( .A0(n2286), .A1(n2843), .B0(n3994), .Y(n3991) );
NAND2X2TS U4858 ( .A(n3358), .B(intDY_EWSW[39]), .Y(n3526) );
NOR2X4TS U4859 ( .A(n3316), .B(n2957), .Y(n3507) );
NAND2X2TS U4860 ( .A(n2529), .B(n5060), .Y(n3722) );
NAND2X2TS U4861 ( .A(n3304), .B(intDY_EWSW[29]), .Y(n3491) );
NAND3X2TS U4862 ( .A(n6082), .B(n6081), .C(n6080), .Y(n3851) );
NAND2X2TS U4863 ( .A(n3846), .B(n5016), .Y(n4081) );
NAND3X2TS U4864 ( .A(n6093), .B(n6092), .C(n6091), .Y(n3940) );
AOI22X4TS U4865 ( .A0(n4603), .A1(n2522), .B0(n5158), .B1(n5153), .Y(n5268)
);
AOI22X4TS U4866 ( .A0(n5155), .A1(n5151), .B0(n2516), .B1(n5150), .Y(n6435)
);
NAND2X2TS U4867 ( .A(n3305), .B(intDY_EWSW[47]), .Y(n3541) );
NAND2X2TS U4868 ( .A(n4612), .B(n5155), .Y(n4613) );
AND3X2TS U4869 ( .A(n5909), .B(n5908), .C(n5907), .Y(n3937) );
AND2X8TS U4870 ( .A(n3011), .B(n2273), .Y(n3009) );
OA21X4TS U4871 ( .A0(n3022), .A1(n5487), .B0(n4319), .Y(n4320) );
NAND4X4TS U4872 ( .A(n4583), .B(n3130), .C(n4582), .D(n4581), .Y(n4014) );
OAI21X4TS U4873 ( .A0(n2947), .A1(n2309), .B0(n3986), .Y(n3977) );
NAND2X4TS U4874 ( .A(n3998), .B(n5435), .Y(n3995) );
NAND2X2TS U4875 ( .A(n3292), .B(intDY_EWSW[27]), .Y(n3486) );
CLKINVX6TS U4876 ( .A(n5017), .Y(n4654) );
MXI2X2TS U4877 ( .A(n5293), .B(n5548), .S0(n5265), .Y(n1018) );
NAND2X2TS U4878 ( .A(n5060), .B(n3846), .Y(n3807) );
MXI2X2TS U4879 ( .A(n5268), .B(n5267), .S0(n5264), .Y(n1127) );
NAND2X2TS U4880 ( .A(n5046), .B(Raw_mant_NRM_SWR[0]), .Y(n4437) );
XNOR2X4TS U4881 ( .A(n5548), .B(n2257), .Y(n3894) );
AOI22X4TS U4882 ( .A0(n4512), .A1(n1878), .B0(Data_array_SWR_3__53_), .B1(
n5274), .Y(n5288) );
CLKINVX12TS U4883 ( .A(n3795), .Y(n3771) );
NAND2X2TS U4884 ( .A(n3343), .B(intDY_EWSW[35]), .Y(n3521) );
AOI22X4TS U4885 ( .A0(n4061), .A1(n2522), .B0(n5158), .B1(n5150), .Y(n4094)
);
OAI21X2TS U4886 ( .A0(n4662), .A1(n5050), .B0(n4086), .Y(n4089) );
OAI21X4TS U4887 ( .A0(n2955), .A1(n5089), .B0(n2954), .Y(n1152) );
NOR2X6TS U4888 ( .A(n3395), .B(DMP_SFG[35]), .Y(n4948) );
NAND2X2TS U4889 ( .A(n3300), .B(intDY_EWSW[28]), .Y(n3492) );
BUFX6TS U4890 ( .A(intDY_EWSW[32]), .Y(n2957) );
NOR2X6TS U4891 ( .A(n3383), .B(DMP_SFG[19]), .Y(n5076) );
NAND2BX2TS U4892 ( .AN(n2958), .B(n4115), .Y(n1302) );
AOI21X4TS U4893 ( .A0(n3499), .A1(n3498), .B0(n3497), .Y(n3500) );
NOR2X2TS U4894 ( .A(n3300), .B(intDY_EWSW[28]), .Y(n3463) );
NAND3X2TS U4895 ( .A(n4515), .B(n4514), .C(n4513), .Y(n1140) );
BUFX20TS U4896 ( .A(n3125), .Y(n2963) );
OAI21X4TS U4897 ( .A0(n3456), .A1(n3455), .B0(n3454), .Y(n3457) );
NAND2X2TS U4898 ( .A(n3353), .B(intDY_EWSW[10]), .Y(n3440) );
NOR2X2TS U4899 ( .A(n3768), .B(n4269), .Y(n3769) );
NAND2X2TS U4900 ( .A(n3293), .B(intDY_EWSW[43]), .Y(n3532) );
XOR2X4TS U4901 ( .A(DmP_mant_SFG_SWR[43]), .B(n2487), .Y(n3403) );
CLKXOR2X4TS U4902 ( .A(n1839), .B(DmP_mant_SFG_SWR[20]), .Y(n3382) );
XOR2X4TS U4903 ( .A(DmP_mant_SFG_SWR[24]), .B(n2487), .Y(n3386) );
OR3X4TS U4904 ( .A(n4052), .B(n4051), .C(n4050), .Y(n5044) );
NAND4X4TS U4905 ( .A(n3856), .B(n3855), .C(n6151), .D(n3854), .Y(n4322) );
NAND3X2TS U4906 ( .A(n4788), .B(n4789), .C(n4787), .Y(n1201) );
NOR2X8TS U4907 ( .A(n2391), .B(n3098), .Y(n3097) );
MXI2X4TS U4908 ( .A(n5261), .B(n5521), .S0(n2554), .Y(n1046) );
BUFX3TS U4909 ( .A(intDY_EWSW[31]), .Y(n2961) );
BUFX20TS U4910 ( .A(n4790), .Y(n4838) );
AOI21X2TS U4911 ( .A0(n4253), .A1(n5439), .B0(Raw_mant_NRM_SWR[11]), .Y(
n3764) );
OAI22X2TS U4912 ( .A0(n1916), .A1(n3320), .B0(n5289), .B1(n5541), .Y(n1094)
);
NOR2X1TS U4913 ( .A(n4669), .B(n4521), .Y(n4522) );
OAI22X2TS U4914 ( .A0(n2990), .A1(n5290), .B0(n5289), .B1(n5506), .Y(n1067)
);
NAND3X2TS U4915 ( .A(n4875), .B(n4876), .C(n4874), .Y(n1586) );
NAND3X2TS U4916 ( .A(n4847), .B(n4848), .C(n4846), .Y(n1270) );
NAND3X2TS U4917 ( .A(n4844), .B(n4845), .C(n4843), .Y(n1274) );
NAND3X2TS U4918 ( .A(n4850), .B(n4851), .C(n4849), .Y(n1212) );
NAND3X2TS U4919 ( .A(n4836), .B(n4837), .C(n4835), .Y(n1210) );
AOI22X4TS U4920 ( .A0(n5147), .A1(n5154), .B0(n2518), .B1(n5153), .Y(n6442)
);
BUFX6TS U4921 ( .A(intDY_EWSW[27]), .Y(n2964) );
NAND3X6TS U4922 ( .A(n3577), .B(n3576), .C(n3575), .Y(n1226) );
XOR2X4TS U4923 ( .A(n4744), .B(n4743), .Y(n4745) );
XOR2X4TS U4924 ( .A(n4761), .B(n4760), .Y(n4762) );
XOR2X4TS U4925 ( .A(n5080), .B(n5079), .Y(n5081) );
NAND2BX4TS U4926 ( .AN(n2446), .B(n4103), .Y(n2965) );
OAI2BB1X4TS U4927 ( .A0N(n5161), .A1N(n6439), .B0(n5160), .Y(n1049) );
INVX12TS U4928 ( .A(n2977), .Y(n3149) );
AOI21X2TS U4929 ( .A0(n3788), .A1(n3787), .B0(n3786), .Y(n3792) );
OAI21X4TS U4930 ( .A0(n3792), .A1(n3791), .B0(n3790), .Y(n3194) );
NOR2X2TS U4931 ( .A(n4026), .B(n2971), .Y(n2970) );
NOR2X2TS U4932 ( .A(n4026), .B(n2976), .Y(n2975) );
XOR2X4TS U4933 ( .A(DmP_mant_SFG_SWR[48]), .B(n2257), .Y(n3879) );
OAI21X4TS U4934 ( .A0(n2648), .A1(n5579), .B0(n4068), .Y(n6392) );
OAI21X4TS U4935 ( .A0(n2648), .A1(n5009), .B0(n5008), .Y(n6409) );
NOR2BX4TS U4936 ( .AN(n4301), .B(n2995), .Y(n2994) );
NAND2BX4TS U4937 ( .AN(n5699), .B(n2999), .Y(n4331) );
AOI21X4TS U4938 ( .A0(n3012), .A1(n3009), .B0(n3006), .Y(n3571) );
AOI21X4TS U4939 ( .A0(n3570), .A1(n3569), .B0(n3568), .Y(n3007) );
AND2X8TS U4940 ( .A(n3569), .B(n3518), .Y(n3011) );
OAI21X4TS U4941 ( .A0(n3015), .A1(n3014), .B0(n3013), .Y(n3012) );
AOI21X4TS U4942 ( .A0(n3505), .A1(n3504), .B0(n3503), .Y(n3013) );
AOI21X4TS U4943 ( .A0(n3459), .A1(n3458), .B0(n3457), .Y(n3015) );
INVX12TS U4944 ( .A(n3214), .Y(n3396) );
NAND2X8TS U4945 ( .A(n3017), .B(n3016), .Y(n3214) );
XOR2X4TS U4946 ( .A(n1853), .B(DmP_mant_SFG_SWR[37]), .Y(n3395) );
XOR2X4TS U4947 ( .A(n1854), .B(DmP_mant_SFG_SWR[36]), .Y(n3394) );
OAI21X4TS U4948 ( .A0(n3561), .A1(n3021), .B0(n3020), .Y(n3564) );
NAND2BX4TS U4949 ( .AN(n3029), .B(n5437), .Y(n3028) );
XNOR2X4TS U4950 ( .A(n3030), .B(n5303), .Y(n5304) );
NAND2BX4TS U4951 ( .AN(n3330), .B(n5556), .Y(n3032) );
NAND2BX4TS U4952 ( .AN(n5311), .B(n2443), .Y(n3033) );
NOR2X8TS U4953 ( .A(n3040), .B(n3795), .Y(n3039) );
NAND3X8TS U4954 ( .A(n3052), .B(n3049), .C(n3048), .Y(n4523) );
NAND2BX4TS U4955 ( .AN(n3959), .B(n3055), .Y(n4699) );
OAI2BB1X4TS U4956 ( .A0N(n4691), .A1N(n5151), .B0(n3059), .Y(n3058) );
OAI2BB1X4TS U4957 ( .A0N(n3060), .A1N(n4483), .B0(n4711), .Y(n3059) );
NAND3BX4TS U4958 ( .AN(n3061), .B(n4485), .C(n4484), .Y(n5151) );
OAI21X4TS U4959 ( .A0(n5257), .A1(n5218), .B0(n3063), .Y(n1047) );
INVX12TS U4960 ( .A(n4931), .Y(n3069) );
NAND2BX4TS U4961 ( .AN(n2826), .B(n3867), .Y(n3071) );
NOR2BX4TS U4962 ( .AN(n3074), .B(n3866), .Y(n3073) );
OAI2BB1X4TS U4963 ( .A0N(n5841), .A1N(n5840), .B0(n3075), .Y(n3827) );
OAI21X4TS U4964 ( .A0(n5309), .A1(n5305), .B0(n5306), .Y(n3408) );
NAND2BX4TS U4965 ( .AN(n5556), .B(n3330), .Y(n5297) );
OR2X8TS U4966 ( .A(n2331), .B(shift_value_SHT2_EWR[4]), .Y(n4293) );
NOR2X8TS U4967 ( .A(n2524), .B(n3571), .Y(n3123) );
NAND4BX4TS U4968 ( .AN(n3842), .B(n3840), .C(n3841), .D(n3088), .Y(n4672) );
AOI21X4TS U4969 ( .A0(n5917), .A1(n4047), .B0(n5916), .Y(n3088) );
AOI22X4TS U4970 ( .A0(n4635), .A1(n2449), .B0(n4692), .B1(n5158), .Y(n5248)
);
AOI22X4TS U4971 ( .A0(n5145), .A1(n2938), .B0(n2517), .B1(n5141), .Y(n6460)
);
NAND2BX4TS U4972 ( .AN(n3095), .B(n3849), .Y(n3094) );
NAND2X8TS U4973 ( .A(n3097), .B(n2433), .Y(n5140) );
OAI21X4TS U4974 ( .A0(n5255), .A1(n5218), .B0(n3101), .Y(n1045) );
AOI2BB2X4TS U4975 ( .B0(n4651), .B1(n2522), .A0N(n3107), .A1N(n3106), .Y(
n5251) );
NAND2X8TS U4976 ( .A(n3108), .B(n4328), .Y(n4651) );
AOI22X4TS U4977 ( .A0(n4619), .A1(n2522), .B0(n4618), .B1(n5155), .Y(n5249)
);
NAND2X8TS U4978 ( .A(n2261), .B(n1951), .Y(n3858) );
INVX16TS U4979 ( .A(n3110), .Y(n4669) );
AND2X8TS U4980 ( .A(n2993), .B(n1951), .Y(n3365) );
AOI21X4TS U4981 ( .A0(n4667), .A1(n4711), .B0(n3115), .Y(n3114) );
NOR2BX4TS U4982 ( .AN(n4475), .B(n2430), .Y(n3117) );
NOR2X8TS U4983 ( .A(n3376), .B(DMP_exp_NRM2_EW[3]), .Y(n3987) );
NAND2BX4TS U4984 ( .AN(n4585), .B(n3120), .Y(n5163) );
XOR2X4TS U4985 ( .A(n3993), .B(DMP_exp_NRM2_EW[8]), .Y(n5166) );
BUFX20TS U4986 ( .A(n3087), .Y(n3124) );
NOR2X8TS U4987 ( .A(n3126), .B(n4014), .Y(n3127) );
AOI22X4TS U4988 ( .A0(n4635), .A1(n1878), .B0(n4692), .B1(n3365), .Y(n5063)
);
NAND3BX4TS U4989 ( .AN(n3142), .B(n6155), .C(n3141), .Y(n3140) );
OAI2BB1X4TS U4990 ( .A0N(n6098), .A1N(n6099), .B0(n6097), .Y(n3715) );
AND2X8TS U4991 ( .A(n3148), .B(n3146), .Y(n6456) );
INVX12TS U4992 ( .A(n3235), .Y(n3242) );
NAND3BX4TS U4993 ( .AN(n3150), .B(n4530), .C(n4529), .Y(n4721) );
NAND2X2TS U4994 ( .A(n4649), .B(n5158), .Y(n3163) );
OAI21X4TS U4995 ( .A0(n4983), .A1(n4978), .B0(n4984), .Y(n4932) );
NAND2X8TS U4996 ( .A(n3165), .B(n3164), .Y(n4910) );
AOI21X4TS U4997 ( .A0(n4932), .A1(n3393), .B0(n3282), .Y(n3164) );
NAND3X2TS U4998 ( .A(n4879), .B(n4880), .C(n4878), .Y(n1585) );
NAND3X2TS U4999 ( .A(n4861), .B(n4862), .C(n4860), .Y(n1268) );
NAND3X2TS U5000 ( .A(n4799), .B(n4800), .C(n4798), .Y(n1252) );
NAND3X2TS U5001 ( .A(n4796), .B(n4797), .C(n4795), .Y(n1242) );
NAND3X2TS U5002 ( .A(n4812), .B(n4813), .C(n4811), .Y(n1240) );
NAND3X2TS U5003 ( .A(n4832), .B(n4833), .C(n4831), .Y(n1262) );
NAND3X2TS U5004 ( .A(n4793), .B(n4794), .C(n4792), .Y(n1250) );
NAND3X2TS U5005 ( .A(n4805), .B(n4806), .C(n4804), .Y(n1246) );
NAND3X2TS U5006 ( .A(n4815), .B(n4816), .C(n4814), .Y(n1238) );
NAND3X2TS U5007 ( .A(n4802), .B(n4803), .C(n4801), .Y(n1244) );
NAND3X2TS U5008 ( .A(n4818), .B(n4819), .C(n4817), .Y(n1248) );
NAND3X2TS U5009 ( .A(n4855), .B(n4856), .C(n4854), .Y(n1260) );
NAND3X2TS U5010 ( .A(n4821), .B(n4822), .C(n4820), .Y(n1236) );
CLKINVX6TS U5011 ( .A(n3796), .Y(n4271) );
XOR2X4TS U5012 ( .A(n1839), .B(DmP_mant_SFG_SWR[16]), .Y(n5317) );
NAND2X4TS U5013 ( .A(n6443), .B(n5149), .Y(n4478) );
NAND4BX4TS U5014 ( .AN(n3703), .B(n3702), .C(n3701), .D(n6183), .Y(n4657) );
NOR2X2TS U5015 ( .A(Raw_mant_NRM_SWR[6]), .B(n5419), .Y(n3744) );
NAND4X4TS U5016 ( .A(n3180), .B(n3274), .C(n3177), .D(n3176), .Y(n1151) );
XOR2X4TS U5017 ( .A(DmP_mant_SFG_SWR[17]), .B(n1839), .Y(n3183) );
NAND2BX4TS U5018 ( .AN(DMP_SFG[39]), .B(n3184), .Y(n3185) );
NOR2BX4TS U5019 ( .AN(n3191), .B(n4245), .Y(n3190) );
NAND2X8TS U5020 ( .A(n2427), .B(n4069), .Y(n3922) );
NOR3X8TS U5021 ( .A(n3200), .B(n3199), .C(n3198), .Y(n4352) );
NOR2BX4TS U5022 ( .AN(n3253), .B(n2748), .Y(n3198) );
NOR2X8TS U5023 ( .A(n2850), .B(n3750), .Y(n3299) );
XOR2X4TS U5024 ( .A(n3205), .B(n4942), .Y(n3204) );
OAI21X4TS U5025 ( .A0(n2362), .A1(n4938), .B0(n3206), .Y(n3205) );
NAND2X8TS U5026 ( .A(n4910), .B(n3396), .Y(n3216) );
NAND2XLTS U5027 ( .A(n2551), .B(Raw_mant_NRM_SWR[52]), .Y(n3217) );
XOR2X4TS U5028 ( .A(DmP_mant_SFG_SWR[21]), .B(n6161), .Y(n3383) );
NAND3X2TS U5029 ( .A(n2284), .B(n3877), .C(n3227), .Y(n3223) );
NAND2X2TS U5030 ( .A(n3877), .B(n3225), .Y(n3224) );
NOR2X8TS U5031 ( .A(n3230), .B(n2448), .Y(n3229) );
NAND2X8TS U5032 ( .A(n3242), .B(n3236), .Y(n3238) );
OAI22X4TS U5033 ( .A0(n6412), .A1(n3239), .B0(n5012), .B1(n6231), .Y(n6413)
);
NAND2X8TS U5034 ( .A(n3240), .B(n4261), .Y(n4274) );
OR2X8TS U5035 ( .A(n4891), .B(n5491), .Y(n4890) );
XOR2X4TS U5036 ( .A(n2298), .B(n6161), .Y(n3874) );
NAND2X8TS U5037 ( .A(n3745), .B(n3250), .Y(n4267) );
AOI21X4TS U5038 ( .A0(n5082), .A1(n2406), .B0(n3388), .Y(n3257) );
NOR2X8TS U5039 ( .A(n3258), .B(n4348), .Y(n3264) );
XOR2X4TS U5040 ( .A(DmP_mant_SFG_SWR[41]), .B(n2487), .Y(n3400) );
XOR2X4TS U5041 ( .A(DmP_mant_SFG_SWR[40]), .B(n6161), .Y(n3399) );
XOR2X4TS U5042 ( .A(DmP_mant_SFG_SWR[27]), .B(n1839), .Y(n3390) );
OAI21X4TS U5043 ( .A0(n3276), .A1(n5319), .B0(n3277), .Y(n1156) );
OAI21X4TS U5044 ( .A0(n4955), .A1(n4939), .B0(n4940), .Y(n3282) );
NAND2BX4TS U5045 ( .AN(n4141), .B(n3287), .Y(n3284) );
AND2X8TS U5046 ( .A(n2262), .B(n3372), .Y(n4473) );
OAI21X4TS U5047 ( .A0(n3543), .A1(n3542), .B0(n3541), .Y(n3544) );
OAI21X4TS U5048 ( .A0(n3447), .A1(n3446), .B0(n3445), .Y(n3453) );
OAI21X2TS U5049 ( .A0(n4662), .A1(n5049), .B0(n4048), .Y(n4055) );
NOR2X2TS U5050 ( .A(n4669), .B(n4666), .Y(n4595) );
CLKINVX3TS U5051 ( .A(n5039), .Y(n4666) );
NAND2X4TS U5052 ( .A(n3982), .B(n3981), .Y(n3983) );
NOR2X2TS U5053 ( .A(n3833), .B(n4684), .Y(n4323) );
NAND2X8TS U5054 ( .A(n6408), .B(n5019), .Y(n5032) );
OAI21X4TS U5055 ( .A0(n3987), .A1(n3986), .B0(n3985), .Y(n3988) );
NOR2X4TS U5056 ( .A(n4283), .B(n4282), .Y(n4285) );
NAND2X4TS U5057 ( .A(n4277), .B(n1825), .Y(n4351) );
AOI21X4TS U5058 ( .A0(n3478), .A1(n3479), .B0(n3477), .Y(n3480) );
NOR3X4TS U5059 ( .A(n4648), .B(n4647), .C(n4646), .Y(n5246) );
AND2X4TS U5060 ( .A(n4645), .B(n1872), .Y(n4647) );
OR2X4TS U5061 ( .A(n2523), .B(n2346), .Y(n6374) );
OR2X4TS U5062 ( .A(n2523), .B(n5570), .Y(n6362) );
OR2X4TS U5063 ( .A(n6213), .B(n5573), .Y(n6402) );
OR2X4TS U5064 ( .A(n6213), .B(n5581), .Y(n6343) );
MX2X4TS U5065 ( .A(n4957), .B(n1825), .S0(n5205), .Y(n1164) );
AOI22X2TS U5066 ( .A0(n6204), .A1(DmP_mant_SHT1_SW[49]), .B0(n6199), .B1(
DmP_mant_SHT1_SW[48]), .Y(n6336) );
NAND4BX4TS U5067 ( .AN(n3712), .B(n3711), .C(n3710), .D(n6162), .Y(n4636) );
NAND4X4TS U5068 ( .A(n3953), .B(n3952), .C(n3951), .D(n3950), .Y(n4333) );
XOR2X4TS U5069 ( .A(n2362), .B(n4738), .Y(n4739) );
NAND4X4TS U5070 ( .A(n6138), .B(n4024), .C(n4023), .D(n4022), .Y(n4049) );
NAND2X2TS U5071 ( .A(n6219), .B(Raw_mant_NRM_SWR[38]), .Y(n6330) );
NAND2X2TS U5072 ( .A(n6218), .B(n2252), .Y(n6308) );
NAND2X1TS U5073 ( .A(n5091), .B(n5094), .Y(n5092) );
NAND4X4TS U5074 ( .A(n3812), .B(n3811), .C(n3810), .D(n3809), .Y(n6443) );
NOR2X2TS U5075 ( .A(n3799), .B(n3798), .Y(n3812) );
NAND4BX4TS U5076 ( .AN(n3721), .B(n3720), .C(n3719), .D(n6159), .Y(n5060) );
NAND4BX4TS U5077 ( .AN(n3718), .B(n3717), .C(n3716), .D(n6157), .Y(n5055) );
XOR2X4TS U5078 ( .A(n5864), .B(n1840), .Y(n3379) );
NAND4BX4TS U5079 ( .AN(n3962), .B(n3961), .C(n3960), .D(n6171), .Y(n5038) );
OR2X4TS U5080 ( .A(n6213), .B(n5342), .Y(n6310) );
OAI22X2TS U5081 ( .A0(n4893), .A1(n5426), .B0(n4892), .B1(n2474), .Y(n4894)
);
OR2X4TS U5082 ( .A(n2523), .B(n5422), .Y(n5430) );
MX2X4TS U5083 ( .A(DMP_exp_NRM2_EW[2]), .B(DMP_exp_NRM_EW[2]), .S0(n2563),
.Y(n1351) );
BUFX20TS U5084 ( .A(n5027), .Y(n6217) );
NAND2X4TS U5085 ( .A(n4658), .B(n1644), .Y(n4289) );
NOR2X2TS U5086 ( .A(n3833), .B(n4535), .Y(n4516) );
AOI2BB2X4TS U5087 ( .B0(n5888), .B1(n2134), .A0N(n5887), .A1N(n5886), .Y(
n4035) );
NAND2X2TS U5088 ( .A(n3978), .B(n3986), .Y(n3979) );
NAND4X4TS U5089 ( .A(n4504), .B(n4503), .C(n4502), .D(n4501), .Y(n6452) );
NOR2X2TS U5090 ( .A(n4500), .B(n4499), .Y(n4502) );
OAI21X2TS U5091 ( .A0(n2252), .A1(n5341), .B0(n5427), .Y(n3758) );
NOR2X8TS U5092 ( .A(Raw_mant_NRM_SWR[19]), .B(n2252), .Y(n3772) );
BUFX20TS U5093 ( .A(n3858), .Y(n4689) );
NOR2X2TS U5094 ( .A(n4125), .B(n4124), .Y(n4129) );
NAND4X4TS U5095 ( .A(n4541), .B(n4540), .C(n4539), .D(n4538), .Y(n6446) );
NAND3X6TS U5096 ( .A(n3771), .B(n3793), .C(n3770), .Y(n4273) );
MXI2X4TS U5097 ( .A(n5276), .B(n4670), .S0(n1876), .Y(n5273) );
NAND4BX4TS U5098 ( .AN(n3700), .B(n3699), .C(n3698), .D(n3697), .Y(n5021) );
INVX4TS U5099 ( .A(n4258), .Y(n3745) );
NOR2X8TS U5100 ( .A(Raw_mant_NRM_SWR[12]), .B(Raw_mant_NRM_SWR[11]), .Y(
n3782) );
NOR2X8TS U5101 ( .A(n3795), .B(n4268), .Y(n4343) );
NAND2X4TS U5102 ( .A(n4626), .B(n4625), .Y(n4630) );
NAND4X4TS U5103 ( .A(n3865), .B(n3864), .C(n6194), .D(n3863), .Y(n5045) );
NOR3X4TS U5104 ( .A(n5843), .B(n5842), .C(n3862), .Y(n3865) );
XOR2X4TS U5105 ( .A(n3991), .B(DMP_exp_NRM2_EW[6]), .Y(n3992) );
OR2X4TS U5106 ( .A(n6213), .B(n5427), .Y(n6322) );
OR2X4TS U5107 ( .A(n6213), .B(n5423), .Y(n6357) );
OR2X4TS U5108 ( .A(n6213), .B(n5491), .Y(n6347) );
OR2X4TS U5109 ( .A(n6213), .B(n1857), .Y(n6335) );
OR2X4TS U5110 ( .A(n6213), .B(n5433), .Y(n6378) );
NAND2X2TS U5111 ( .A(n4508), .B(n4509), .Y(n1033) );
NAND4BX4TS U5112 ( .AN(n3826), .B(n3825), .C(n3824), .D(n3823), .Y(n1635) );
NOR2X8TS U5113 ( .A(Raw_mant_NRM_SWR[13]), .B(Raw_mant_NRM_SWR[10]), .Y(
n3743) );
XNOR2X4TS U5114 ( .A(n3977), .B(n3976), .Y(n5174) );
NAND2X2TS U5115 ( .A(n3975), .B(n3985), .Y(n3976) );
XOR2X4TS U5116 ( .A(n3996), .B(DMP_exp_NRM2_EW[7]), .Y(n5172) );
OR2X8TS U5117 ( .A(n3385), .B(DMP_SFG[21]), .Y(n3295) );
CLKBUFX3TS U5118 ( .A(n6290), .Y(n4462) );
CLKBUFX3TS U5119 ( .A(n6254), .Y(n6288) );
CLKBUFX3TS U5120 ( .A(n6288), .Y(n6290) );
INVX2TS U5121 ( .A(n5000), .Y(n3881) );
NAND2X4TS U5122 ( .A(n3275), .B(n4912), .Y(n4914) );
NAND2X4TS U5123 ( .A(n3275), .B(n2759), .Y(n4783) );
NAND2X2TS U5124 ( .A(n3379), .B(DMP_SFG[17]), .Y(n5069) );
NAND2X2TS U5125 ( .A(n3368), .B(n3883), .Y(n3880) );
NOR2XLTS U5126 ( .A(n4669), .B(n4696), .Y(n4302) );
NAND2X1TS U5127 ( .A(n4439), .B(n2745), .Y(n3642) );
CLKBUFX3TS U5128 ( .A(n6233), .Y(n4465) );
BUFX3TS U5129 ( .A(n4465), .Y(n6238) );
INVX2TS U5130 ( .A(DmP_mant_SHT1_SW[30]), .Y(n5601) );
CLKBUFX3TS U5131 ( .A(n4466), .Y(n5655) );
CLKBUFX2TS U5132 ( .A(n6286), .Y(n5620) );
CLKBUFX3TS U5133 ( .A(n2521), .Y(n5680) );
CLKBUFX3TS U5134 ( .A(n4462), .Y(n5649) );
CLKBUFX3TS U5135 ( .A(n6286), .Y(n5629) );
CLKBUFX3TS U5136 ( .A(n4462), .Y(n5646) );
BUFX3TS U5137 ( .A(n5655), .Y(n6275) );
BUFX3TS U5138 ( .A(n4465), .Y(n6241) );
XOR2X4TS U5139 ( .A(n6161), .B(DmP_mant_SFG_SWR[38]), .Y(n3397) );
NOR2X8TS U5140 ( .A(n4918), .B(n4926), .Y(n4989) );
NOR2X8TS U5141 ( .A(n3399), .B(DMP_SFG[38]), .Y(n4993) );
NOR2X8TS U5142 ( .A(n3389), .B(DMP_SFG[23]), .Y(n4747) );
NOR2X8TS U5143 ( .A(n4747), .B(n4748), .Y(n4763) );
NOR2X8TS U5144 ( .A(n3382), .B(DMP_SFG[18]), .Y(n4734) );
NAND2X8TS U5145 ( .A(n3382), .B(DMP_SFG[18]), .Y(n5073) );
NAND2X1TS U5150 ( .A(n3331), .B(DMP_EXP_EWSW[53]), .Y(n5310) );
NOR2X2TS U5151 ( .A(n3354), .B(DMP_EXP_EWSW[55]), .Y(n5300) );
NOR2X1TS U5152 ( .A(n5488), .B(DMP_EXP_EWSW[56]), .Y(n5305) );
NAND2X1TS U5153 ( .A(n5496), .B(DMP_EXP_EWSW[57]), .Y(n3406) );
NOR2X4TS U5154 ( .A(n3424), .B(n3419), .Y(n3421) );
OAI21X4TS U5155 ( .A0(n3424), .A1(n3423), .B0(n3422), .Y(n3429) );
OR2X4TS U5156 ( .A(n3377), .B(intDY_EWSW[62]), .Y(n3563) );
AND2X2TS U5157 ( .A(n3377), .B(intDY_EWSW[62]), .Y(n3562) );
NAND2X2TS U5158 ( .A(n2963), .B(intDX_EWSW[12]), .Y(n3574) );
NAND2X1TS U5159 ( .A(n2534), .B(DmP_EXP_EWSW[12]), .Y(n3572) );
NAND3X2TS U5160 ( .A(n3573), .B(n3574), .C(n3572), .Y(n1286) );
NAND2X2TS U5161 ( .A(n1838), .B(intDX_EWSW[42]), .Y(n3577) );
BUFX4TS U5162 ( .A(n5495), .Y(n4839) );
NAND2X1TS U5163 ( .A(n4839), .B(DmP_EXP_EWSW[42]), .Y(n3575) );
NAND2X2TS U5164 ( .A(n2530), .B(intDX_EWSW[44]), .Y(n3580) );
NAND2X1TS U5165 ( .A(n4839), .B(DmP_EXP_EWSW[44]), .Y(n3578) );
NAND2X2TS U5166 ( .A(n2041), .B(intDX_EWSW[47]), .Y(n3583) );
NAND2X1TS U5167 ( .A(n4369), .B(n2045), .Y(n3582) );
NAND2X1TS U5168 ( .A(n4839), .B(DmP_EXP_EWSW[43]), .Y(n3584) );
NAND2X1TS U5169 ( .A(n2535), .B(DMP_EXP_EWSW[59]), .Y(n3588) );
NAND2X2TS U5170 ( .A(n2530), .B(intDY_EWSW[40]), .Y(n3593) );
NAND2X2TS U5171 ( .A(n2526), .B(n1922), .Y(n3596) );
NAND3X2TS U5172 ( .A(n3595), .B(n3596), .C(n3594), .Y(n1541) );
NAND2X2TS U5173 ( .A(n3630), .B(n2740), .Y(n3599) );
NAND2X2TS U5174 ( .A(n2531), .B(n2026), .Y(n3602) );
NAND3X2TS U5175 ( .A(n3601), .B(n3602), .C(n3600), .Y(n1546) );
NAND2X2TS U5176 ( .A(n1836), .B(n2299), .Y(n3605) );
NAND3X2TS U5177 ( .A(n3604), .B(n3605), .C(n3603), .Y(n1542) );
NAND2X2TS U5178 ( .A(n2041), .B(n2051), .Y(n3608) );
NAND2X1TS U5179 ( .A(n4873), .B(intDX_EWSW[43]), .Y(n3607) );
NAND3X2TS U5180 ( .A(n3608), .B(n3607), .C(n3606), .Y(n1544) );
NAND2X2TS U5181 ( .A(n2526), .B(intDY_EWSW[44]), .Y(n3611) );
NAND3X2TS U5182 ( .A(n3610), .B(n3611), .C(n3609), .Y(n1543) );
NAND2X2TS U5183 ( .A(n2530), .B(n1815), .Y(n3614) );
NAND3X2TS U5184 ( .A(n3613), .B(n3614), .C(n3612), .Y(n1545) );
NAND2X1TS U5185 ( .A(n2053), .B(intDX_EWSW[38]), .Y(n3616) );
NAND2X2TS U5186 ( .A(n2531), .B(intDY_EWSW[39]), .Y(n3620) );
NAND3X2TS U5187 ( .A(n3619), .B(n3620), .C(n3618), .Y(n1548) );
NAND2X2TS U5188 ( .A(n2531), .B(intDY_EWSW[36]), .Y(n3623) );
NAND3X2TS U5189 ( .A(n3622), .B(n3623), .C(n3621), .Y(n1551) );
NAND2X2TS U5190 ( .A(n4424), .B(n2940), .Y(n3626) );
NAND3X2TS U5191 ( .A(n3625), .B(n3626), .C(n3624), .Y(n1552) );
NAND2X2TS U5192 ( .A(n1838), .B(n2945), .Y(n3629) );
NAND3X2TS U5193 ( .A(n3628), .B(n3629), .C(n3627), .Y(n1554) );
NAND2X2TS U5194 ( .A(n2530), .B(intDY_EWSW[37]), .Y(n3633) );
NAND3X2TS U5195 ( .A(n3632), .B(n3633), .C(n3631), .Y(n1550) );
NAND2X1TS U5196 ( .A(n2526), .B(n2479), .Y(n3636) );
NAND3X2TS U5197 ( .A(n3636), .B(n3635), .C(n3634), .Y(n1566) );
NAND3X2TS U5198 ( .A(n3639), .B(n3638), .C(n3637), .Y(n1565) );
NAND3X2TS U5199 ( .A(n3642), .B(n3641), .C(n3640), .Y(n1559) );
NAND2X2TS U5200 ( .A(n3124), .B(intDY_EWSW[30]), .Y(n3645) );
NAND2X2TS U5201 ( .A(n4426), .B(DMP_EXP_EWSW[30]), .Y(n3643) );
NAND2X2TS U5202 ( .A(n1838), .B(n2957), .Y(n3648) );
NAND2X2TS U5203 ( .A(n4424), .B(intDY_EWSW[29]), .Y(n3651) );
NAND3X2TS U5204 ( .A(n3650), .B(n3651), .C(n3649), .Y(n1558) );
NAND2X2TS U5205 ( .A(n1838), .B(n2961), .Y(n3655) );
NAND3X2TS U5206 ( .A(n3654), .B(n3655), .C(n3653), .Y(n1556) );
NAND2X2TS U5207 ( .A(n3124), .B(n2964), .Y(n3658) );
NAND3X2TS U5208 ( .A(n3657), .B(n3658), .C(n3656), .Y(n1560) );
NAND2X1TS U5209 ( .A(n2525), .B(DMP_EXP_EWSW[16]), .Y(n3662) );
NAND3X2TS U5210 ( .A(n3664), .B(n3663), .C(n3662), .Y(n1571) );
NAND2X1TS U5211 ( .A(n2525), .B(DMP_EXP_EWSW[15]), .Y(n3665) );
NAND3X2TS U5212 ( .A(n3666), .B(n3667), .C(n3665), .Y(n1572) );
NAND2X1TS U5213 ( .A(n2525), .B(DMP_EXP_EWSW[17]), .Y(n3668) );
NAND2X1TS U5214 ( .A(n2525), .B(DMP_EXP_EWSW[18]), .Y(n3671) );
NAND3X2TS U5215 ( .A(n3675), .B(n3676), .C(n3674), .Y(n1567) );
NAND2X1TS U5216 ( .A(n2524), .B(DMP_EXP_EWSW[61]), .Y(n3677) );
NAND2X2TS U5217 ( .A(n4430), .B(intDX_EWSW[40]), .Y(n3685) );
NAND2X2TS U5218 ( .A(n2963), .B(n2028), .Y(n3688) );
NAND3X2TS U5219 ( .A(n3687), .B(n3688), .C(n3686), .Y(n1232) );
NAND2X2TS U5220 ( .A(n4430), .B(intDX_EWSW[41]), .Y(n3691) );
AO22X4TS U5221 ( .A0(n5863), .A1(n5862), .B0(n5861), .B1(n2153), .Y(n3692)
);
NAND3X1TS U5222 ( .A(n6047), .B(n6046), .C(n6045), .Y(n3700) );
NOR2X1TS U5223 ( .A(n3832), .B(n6410), .Y(n3705) );
NOR2X1TS U5224 ( .A(n4716), .B(n5058), .Y(n3704) );
NAND3X1TS U5225 ( .A(n6088), .B(n6087), .C(n6086), .Y(n3706) );
NAND3X1TS U5226 ( .A(n6132), .B(n6131), .C(n6130), .Y(n3709) );
INVX2TS U5227 ( .A(DmP_mant_SFG_SWR[11]), .Y(n3725) );
INVX16TS U5228 ( .A(n6293), .Y(n5243) );
NAND2X8TS U5229 ( .A(n5243), .B(Shift_reg_FLAGS_7[3]), .Y(n5259) );
MXI2X2TS U5230 ( .A(n4652), .B(n3725), .S0(n5218), .Y(n1117) );
INVX2TS U5231 ( .A(n4245), .Y(n3733) );
OAI21X1TS U5232 ( .A0(n1856), .A1(n5339), .B0(n5429), .Y(n3732) );
NOR2X8TS U5233 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[16]), .Y(
n3763) );
NAND2X6TS U5234 ( .A(n5428), .B(n3785), .Y(n4258) );
OAI21X1TS U5235 ( .A0(Raw_mant_NRM_SWR[40]), .A1(n2346), .B0(n5422), .Y(
n3736) );
NOR2X1TS U5236 ( .A(n5432), .B(Raw_mant_NRM_SWR[28]), .Y(n3739) );
INVX2TS U5237 ( .A(Raw_mant_NRM_SWR[51]), .Y(n5009) );
OAI21X2TS U5238 ( .A0(Raw_mant_NRM_SWR[50]), .A1(n3367), .B0(n5009), .Y(
n3740) );
NOR2X1TS U5239 ( .A(n5426), .B(Raw_mant_NRM_SWR[16]), .Y(n3751) );
NAND4X1TS U5240 ( .A(n3758), .B(n4335), .C(n2766), .D(n5441), .Y(n3759) );
OAI2BB1X1TS U5241 ( .A0N(n6209), .A1N(n3364), .B0(n4270), .Y(n3768) );
INVX2TS U5242 ( .A(n3767), .Y(n4269) );
NAND2X1TS U5243 ( .A(n5419), .B(Raw_mant_NRM_SWR[0]), .Y(n3775) );
INVX2TS U5244 ( .A(n3782), .Y(n3783) );
CLKINVX1TS U5245 ( .A(n2889), .Y(n3786) );
NOR2X2TS U5246 ( .A(Raw_mant_NRM_SWR[17]), .B(Raw_mant_NRM_SWR[18]), .Y(
n4345) );
INVX2TS U5247 ( .A(n4345), .Y(n3794) );
NOR2X2TS U5248 ( .A(Raw_mant_NRM_SWR[16]), .B(Raw_mant_NRM_SWR[15]), .Y(
n4346) );
CLKINVX6TS U5249 ( .A(n4293), .Y(n4691) );
INVX2TS U5250 ( .A(n2296), .Y(n4668) );
INVX2TS U5251 ( .A(n4636), .Y(n5053) );
NOR2X1TS U5252 ( .A(n4698), .B(n5053), .Y(n3798) );
NOR2X1TS U5253 ( .A(n3832), .B(n4643), .Y(n3801) );
NOR2X1TS U5254 ( .A(n3833), .B(n4661), .Y(n3800) );
NOR2X1TS U5255 ( .A(n3803), .B(n3802), .Y(n3810) );
NAND3X4TS U5256 ( .A(n3808), .B(n3807), .C(n3806), .Y(n4472) );
NAND2X1TS U5257 ( .A(n4472), .B(n1871), .Y(n3809) );
NAND2X2TS U5258 ( .A(n2526), .B(intDX_EWSW[13]), .Y(n3815) );
NAND3X2TS U5259 ( .A(n3814), .B(n3815), .C(n3813), .Y(n1284) );
NAND2X1TS U5260 ( .A(n2536), .B(n1864), .Y(n3816) );
NAND2X2TS U5261 ( .A(n3630), .B(intDX_EWSW[7]), .Y(n3821) );
NAND3X2TS U5262 ( .A(n3820), .B(n3821), .C(n3819), .Y(n1296) );
NAND4BX4TS U5263 ( .AN(n3831), .B(n3830), .C(n3829), .D(n3828), .Y(n1627) );
NAND2X4TS U5264 ( .A(n4682), .B(n3372), .Y(n3845) );
NAND2X1TS U5265 ( .A(n4474), .B(Data_array_SWR_3__53_), .Y(n3843) );
AND3X2TS U5266 ( .A(n5906), .B(n5905), .C(n5904), .Y(n3847) );
INVX2TS U5267 ( .A(n5026), .Y(n4675) );
AND2X2TS U5268 ( .A(n5811), .B(n5810), .Y(n3862) );
NOR2X8TS U5269 ( .A(n3898), .B(n3915), .Y(n3882) );
OAI21X4TS U5270 ( .A0(n3915), .A1(n3911), .B0(n3916), .Y(n3885) );
AOI21X4TS U5271 ( .A0(n3913), .A1(n3882), .B0(n3885), .Y(n3877) );
XOR2X4TS U5272 ( .A(n2257), .B(DmP_mant_SFG_SWR[50]), .Y(n3889) );
NOR2X8TS U5273 ( .A(n3889), .B(DMP_SFG[48]), .Y(n4138) );
XOR2X4TS U5274 ( .A(n2257), .B(DmP_mant_SFG_SWR[49]), .Y(n3888) );
OAI21X4TS U5275 ( .A0(n4138), .A1(n4135), .B0(n4139), .Y(n4999) );
OAI21X4TS U5276 ( .A0(n3891), .A1(n5002), .B0(n5003), .Y(n3892) );
INVX2TS U5277 ( .A(n3902), .Y(n3895) );
NAND2X2TS U5278 ( .A(n3895), .B(n3901), .Y(n3896) );
NOR2X8TS U5279 ( .A(n5434), .B(n2561), .Y(n5019) );
AOI22X2TS U5280 ( .A0(n6219), .A1(Raw_mant_NRM_SWR[25]), .B0(n2501), .B1(
DmP_mant_SHT1_SW[25]), .Y(n6404) );
OAI21X4TS U5281 ( .A0(n3902), .A1(n5003), .B0(n3901), .Y(n3903) );
AOI21X4TS U5282 ( .A0(n4999), .A1(n3904), .B0(n3903), .Y(n3905) );
NAND2X2TS U5283 ( .A(n2500), .B(DmP_mant_SHT1_SW[19]), .Y(n6390) );
AND3X2TS U5284 ( .A(n5869), .B(n5868), .C(n5867), .Y(n3931) );
NOR2X1TS U5285 ( .A(n2611), .B(n4715), .Y(n3932) );
NAND4BX4TS U5286 ( .AN(n3940), .B(n3939), .C(n6195), .D(n3938), .Y(n5014) );
NOR3X4TS U5287 ( .A(n3949), .B(n5854), .C(n3948), .Y(n3953) );
AND3X2TS U5288 ( .A(n6096), .B(n6095), .C(n6094), .Y(n3957) );
NAND3X1TS U5289 ( .A(n5973), .B(n5972), .C(n5971), .Y(n3962) );
OR2X4TS U5290 ( .A(n5871), .B(n5870), .Y(n4518) );
NAND2X2TS U5291 ( .A(n1950), .B(n4518), .Y(n3973) );
CLKINVX1TS U5292 ( .A(n3987), .Y(n3975) );
INVX2TS U5293 ( .A(n5176), .Y(n4582) );
XNOR2X2TS U5294 ( .A(n3321), .B(n2040), .Y(n5169) );
INVX2TS U5295 ( .A(n5169), .Y(n4581) );
OR2X8TS U5296 ( .A(n3994), .B(n2387), .Y(n4001) );
AOI21X4TS U5297 ( .A0(n2286), .A1(n2843), .B0(n4001), .Y(n3993) );
AOI21X4TS U5298 ( .A0(n1865), .A1(n2843), .B0(n3995), .Y(n3996) );
AOI21X4TS U5299 ( .A0(n2286), .A1(n2843), .B0(n3999), .Y(n4000) );
XOR2X4TS U5300 ( .A(n4000), .B(DMP_exp_NRM2_EW[9]), .Y(n5180) );
NOR2BX4TS U5301 ( .AN(n4002), .B(n4001), .Y(n4003) );
INVX2TS U5302 ( .A(n4005), .Y(n4011) );
INVX2TS U5303 ( .A(n2962), .Y(n4006) );
AOI21X4TS U5304 ( .A0(n1865), .A1(n4011), .B0(n4006), .Y(n4010) );
INVX2TS U5305 ( .A(n4007), .Y(n4009) );
NAND2X2TS U5306 ( .A(n2962), .B(n4011), .Y(n4013) );
BUFX4TS U5307 ( .A(Shift_reg_FLAGS_7[0]), .Y(n5289) );
NAND2X1TS U5308 ( .A(n4474), .B(n4518), .Y(n4044) );
NAND3X6TS U5309 ( .A(n4046), .B(n4045), .C(n4044), .Y(n4506) );
NAND2X4TS U5310 ( .A(n4506), .B(n2330), .Y(n4057) );
INVX2TS U5311 ( .A(n5044), .Y(n4053) );
OAI22X2TS U5312 ( .A0(n2088), .A1(n4094), .B0(n5287), .B1(n5525), .Y(n1076)
);
NAND2X1TS U5313 ( .A(n4658), .B(n4523), .Y(n4063) );
AOI22X1TS U5314 ( .A0(n5019), .A1(n2572), .B0(n5006), .B1(n2548), .Y(n4067)
);
OA21X4TS U5315 ( .A0(n3022), .A1(n5420), .B0(n4067), .Y(n4068) );
BUFX4TS U5316 ( .A(n5495), .Y(n4834) );
NAND2X1TS U5317 ( .A(n4834), .B(DMP_EXP_EWSW[4]), .Y(n4071) );
NAND3X2TS U5318 ( .A(n4073), .B(n4072), .C(n4071), .Y(n1583) );
NAND2X1TS U5319 ( .A(n4834), .B(DMP_EXP_EWSW[13]), .Y(n4077) );
NAND2X4TS U5320 ( .A(n4704), .B(n3372), .Y(n4085) );
INVX2TS U5321 ( .A(n5015), .Y(n4088) );
NAND2X2TS U5322 ( .A(n2529), .B(n5018), .Y(n4090) );
MXI2X2TS U5323 ( .A(n4092), .B(n5550), .S0(n5216), .Y(n1022) );
INVX2TS U5324 ( .A(DmP_mant_SFG_SWR[6]), .Y(n4093) );
MXI2X2TS U5325 ( .A(n4094), .B(n4093), .S0(n5218), .Y(n1124) );
NAND2X2TS U5326 ( .A(n3124), .B(intDX_EWSW[46]), .Y(n4098) );
NAND3X2TS U5327 ( .A(n4097), .B(n4098), .C(n4096), .Y(n1218) );
NAND2X2TS U5328 ( .A(n3630), .B(intDX_EWSW[38]), .Y(n4101) );
NAND3X2TS U5329 ( .A(n4100), .B(n4101), .C(n4099), .Y(n1234) );
NAND2X2TS U5330 ( .A(n4424), .B(intDX_EWSW[15]), .Y(n4108) );
NAND3X2TS U5331 ( .A(n4107), .B(n4108), .C(n4106), .Y(n1280) );
NAND2X2TS U5332 ( .A(n2531), .B(intDX_EWSW[6]), .Y(n4113) );
NAND2X1TS U5333 ( .A(n2558), .B(n5026), .Y(n4122) );
NAND2X2TS U5334 ( .A(n2555), .B(n1635), .Y(n4121) );
OR2X2TS U5335 ( .A(n5724), .B(n5723), .Y(n4123) );
BUFX12TS U5336 ( .A(n2764), .Y(n5264) );
NOR2X1TS U5337 ( .A(n4716), .B(n4534), .Y(n4125) );
NAND2X2TS U5338 ( .A(n4618), .B(n4691), .Y(n4128) );
INVX2TS U5339 ( .A(n5332), .Y(n4130) );
NAND2X1TS U5340 ( .A(n4834), .B(DMP_EXP_EWSW[8]), .Y(n4132) );
NAND2X2TS U5341 ( .A(n4140), .B(n4139), .Y(n4141) );
NAND2X1TS U5342 ( .A(n4834), .B(DMP_EXP_EWSW[11]), .Y(n4142) );
NAND3X2TS U5343 ( .A(n4144), .B(n4143), .C(n4142), .Y(n1576) );
OR2X2TS U5344 ( .A(n2522), .B(n2330), .Y(n4480) );
NOR2X8TS U5345 ( .A(n2453), .B(n4480), .Y(n5184) );
XNOR2X1TS U5346 ( .A(intDX_EWSW[45]), .B(n2299), .Y(n4149) );
XNOR2X1TS U5347 ( .A(intDX_EWSW[44]), .B(intDY_EWSW[44]), .Y(n4148) );
XNOR2X1TS U5348 ( .A(intDX_EWSW[47]), .B(n2045), .Y(n4147) );
XNOR2X1TS U5349 ( .A(intDX_EWSW[46]), .B(n1922), .Y(n4146) );
NAND4X1TS U5350 ( .A(n4149), .B(n4148), .C(n4147), .D(n4146), .Y(n4165) );
XNOR2X1TS U5351 ( .A(intDX_EWSW[33]), .B(n2945), .Y(n4153) );
XNOR2X1TS U5352 ( .A(intDX_EWSW[35]), .B(n2940), .Y(n4151) );
XNOR2X1TS U5353 ( .A(intDX_EWSW[34]), .B(n2740), .Y(n4150) );
NAND4X1TS U5354 ( .A(n4153), .B(n4152), .C(n4151), .D(n4150), .Y(n4164) );
XNOR2X1TS U5355 ( .A(intDX_EWSW[36]), .B(intDY_EWSW[36]), .Y(n4156) );
XNOR2X1TS U5356 ( .A(intDX_EWSW[38]), .B(intDY_EWSW[38]), .Y(n4154) );
NAND4X1TS U5357 ( .A(n4157), .B(n4156), .C(n4155), .D(n4154), .Y(n4163) );
XNOR2X1TS U5358 ( .A(intDX_EWSW[31]), .B(n2961), .Y(n4161) );
XNOR2X1TS U5359 ( .A(intDX_EWSW[30]), .B(intDY_EWSW[30]), .Y(n4160) );
XNOR2X1TS U5360 ( .A(intDX_EWSW[29]), .B(intDY_EWSW[29]), .Y(n4159) );
XNOR2X1TS U5361 ( .A(intDX_EWSW[20]), .B(intDY_EWSW[20]), .Y(n4158) );
NAND4X1TS U5362 ( .A(n4161), .B(n4160), .C(n4159), .D(n4158), .Y(n4162) );
XNOR2X1TS U5363 ( .A(intDX_EWSW[27]), .B(n2964), .Y(n4169) );
XNOR2X1TS U5364 ( .A(intDX_EWSW[26]), .B(n2046), .Y(n4168) );
XNOR2X1TS U5365 ( .A(intDX_EWSW[32]), .B(n2957), .Y(n4167) );
XNOR2X1TS U5366 ( .A(intDX_EWSW[25]), .B(n2250), .Y(n4166) );
NAND4X1TS U5367 ( .A(n4169), .B(n4168), .C(n4167), .D(n4166), .Y(n4185) );
XNOR2X1TS U5368 ( .A(intDX_EWSW[23]), .B(n1984), .Y(n4173) );
XNOR2X1TS U5369 ( .A(intDX_EWSW[22]), .B(n2036), .Y(n4172) );
XNOR2X1TS U5370 ( .A(intDX_EWSW[48]), .B(intDY_EWSW[48]), .Y(n4171) );
XNOR2X1TS U5371 ( .A(intDX_EWSW[21]), .B(n2479), .Y(n4170) );
XNOR2X1TS U5372 ( .A(intDX_EWSW[19]), .B(intDY_EWSW[19]), .Y(n4177) );
XNOR2X1TS U5373 ( .A(intDX_EWSW[18]), .B(intDY_EWSW[18]), .Y(n4176) );
XNOR2X1TS U5374 ( .A(intDX_EWSW[24]), .B(intDY_EWSW[24]), .Y(n4175) );
XNOR2X1TS U5375 ( .A(intDX_EWSW[17]), .B(intDY_EWSW[17]), .Y(n4174) );
NAND4X1TS U5376 ( .A(n4177), .B(n4176), .C(n4175), .D(n4174), .Y(n4183) );
XNOR2X1TS U5377 ( .A(intDX_EWSW[15]), .B(intDY_EWSW[15]), .Y(n4181) );
XNOR2X1TS U5378 ( .A(intDX_EWSW[13]), .B(intDY_EWSW[13]), .Y(n4179) );
XNOR2X1TS U5379 ( .A(intDX_EWSW[4]), .B(intDY_EWSW[4]), .Y(n4178) );
NAND4X1TS U5380 ( .A(n4181), .B(n4180), .C(n4179), .D(n4178), .Y(n4182) );
XNOR2X1TS U5381 ( .A(intDX_EWSW[12]), .B(n1923), .Y(n4189) );
XNOR2X1TS U5382 ( .A(intDX_EWSW[10]), .B(n2048), .Y(n4188) );
XNOR2X1TS U5383 ( .A(intDX_EWSW[16]), .B(intDY_EWSW[16]), .Y(n4187) );
XNOR2X1TS U5384 ( .A(intDX_EWSW[9]), .B(n2050), .Y(n4186) );
NAND4X1TS U5385 ( .A(n4189), .B(n4188), .C(n4187), .D(n4186), .Y(n4205) );
XNOR2X1TS U5386 ( .A(intDX_EWSW[7]), .B(intDY_EWSW[7]), .Y(n4193) );
XNOR2X1TS U5387 ( .A(intDX_EWSW[6]), .B(intDY_EWSW[6]), .Y(n4192) );
XNOR2X1TS U5388 ( .A(intDX_EWSW[5]), .B(n2295), .Y(n4190) );
NAND4X1TS U5389 ( .A(n4193), .B(n4192), .C(n4191), .D(n4190), .Y(n4204) );
XNOR2X1TS U5390 ( .A(intDX_EWSW[58]), .B(intDY_EWSW[58]), .Y(n4197) );
XNOR2X1TS U5391 ( .A(intDX_EWSW[60]), .B(intDY_EWSW[60]), .Y(n4196) );
XNOR2X1TS U5392 ( .A(intDX_EWSW[59]), .B(intDY_EWSW[59]), .Y(n4195) );
XNOR2X1TS U5393 ( .A(intDX_EWSW[62]), .B(intDY_EWSW[62]), .Y(n4194) );
NAND4X1TS U5394 ( .A(n4197), .B(n4196), .C(n4195), .D(n4194), .Y(n4203) );
XNOR2X1TS U5395 ( .A(intDX_EWSW[3]), .B(intDY_EWSW[3]), .Y(n4201) );
XNOR2X1TS U5396 ( .A(intDX_EWSW[2]), .B(intDY_EWSW[2]), .Y(n4200) );
XNOR2X1TS U5397 ( .A(intDX_EWSW[8]), .B(intDY_EWSW[8]), .Y(n4199) );
XNOR2X1TS U5398 ( .A(intDX_EWSW[0]), .B(intDY_EWSW[0]), .Y(n4198) );
NAND4X1TS U5399 ( .A(n4201), .B(n4200), .C(n4199), .D(n4198), .Y(n4202) );
XNOR2X1TS U5400 ( .A(intDX_EWSW[49]), .B(intDY_EWSW[49]), .Y(n4209) );
XNOR2X1TS U5401 ( .A(intDX_EWSW[52]), .B(intDY_EWSW[52]), .Y(n4208) );
XNOR2X1TS U5402 ( .A(intDX_EWSW[51]), .B(n2017), .Y(n4207) );
XNOR2X1TS U5403 ( .A(intDX_EWSW[54]), .B(intDY_EWSW[54]), .Y(n4206) );
XNOR2X1TS U5404 ( .A(intDX_EWSW[56]), .B(intDY_EWSW[56]), .Y(n4212) );
NAND4X1TS U5405 ( .A(n4213), .B(n4212), .C(n4211), .D(n4210), .Y(n4223) );
XNOR2X1TS U5406 ( .A(intDX_EWSW[40]), .B(intDY_EWSW[40]), .Y(n4216) );
XNOR2X1TS U5407 ( .A(intDX_EWSW[43]), .B(intDY_EWSW[43]), .Y(n4215) );
XNOR2X1TS U5408 ( .A(intDX_EWSW[42]), .B(intDY_EWSW[42]), .Y(n4214) );
XNOR2X1TS U5409 ( .A(intDX_EWSW[61]), .B(intDY_EWSW[61]), .Y(n4220) );
XNOR2X1TS U5410 ( .A(intDX_EWSW[50]), .B(intDY_EWSW[50]), .Y(n4218) );
NAND3X1TS U5411 ( .A(n4220), .B(n4219), .C(n4218), .Y(n4221) );
INVX2TS U5412 ( .A(n4729), .Y(n4230) );
NOR2X2TS U5413 ( .A(n4230), .B(n4229), .Y(n4728) );
NAND2X1TS U5414 ( .A(n2534), .B(DMP_EXP_EWSW[56]), .Y(n4234) );
NAND3X2TS U5415 ( .A(n4235), .B(n4236), .C(n4234), .Y(n1531) );
NAND2X1TS U5416 ( .A(n2534), .B(DMP_EXP_EWSW[55]), .Y(n4237) );
NAND3X2TS U5417 ( .A(n4238), .B(n4239), .C(n4237), .Y(n1532) );
NAND3X1TS U5418 ( .A(n4343), .B(n4251), .C(Raw_mant_NRM_SWR[30]), .Y(n4252)
);
NOR2X8TS U5419 ( .A(n2077), .B(Raw_mant_NRM_SWR[11]), .Y(n4884) );
NAND2X1TS U5420 ( .A(n4892), .B(n5423), .Y(n4264) );
NOR2X8TS U5421 ( .A(n2474), .B(n4264), .Y(n4276) );
OAI21X1TS U5422 ( .A0(Raw_mant_NRM_SWR[2]), .A1(Raw_mant_NRM_SWR[1]), .B0(
n4276), .Y(n4265) );
NOR2X4TS U5423 ( .A(n4267), .B(n4268), .Y(n4277) );
NAND2X1TS U5424 ( .A(n4277), .B(Raw_mant_NRM_SWR[33]), .Y(n4275) );
NAND3X1TS U5425 ( .A(n4271), .B(n2038), .C(n4269), .Y(n4272) );
NAND2X4TS U5426 ( .A(n4276), .B(Raw_mant_NRM_SWR[0]), .Y(n4902) );
OAI2BB1X4TS U5427 ( .A0N(LZD_output_NRM2_EW[4]), .A1N(n2384), .B0(n4869),
.Y(n1135) );
NAND2X4TS U5428 ( .A(n2555), .B(n4707), .Y(n4292) );
INVX4TS U5429 ( .A(n4293), .Y(n4685) );
NAND2X1TS U5430 ( .A(n4659), .B(n4523), .Y(n4296) );
INVX2TS U5431 ( .A(DmP_mant_SFG_SWR[2]), .Y(n4303) );
AOI22X1TS U5432 ( .A0(n5019), .A1(DmP_mant_SHT1_SW[2]), .B0(n5006), .B1(
DmP_mant_SHT1_SW[1]), .Y(n4304) );
OA21X4TS U5433 ( .A0(n3022), .A1(n5009), .B0(n4304), .Y(n4305) );
NAND2X4TS U5434 ( .A(n4321), .B(n6396), .Y(n6397) );
NAND2X2TS U5435 ( .A(n2041), .B(intDX_EWSW[14]), .Y(n4309) );
NAND2X1TS U5436 ( .A(n2951), .B(n2024), .Y(n4308) );
NAND3X2TS U5437 ( .A(n4308), .B(n4309), .C(n4307), .Y(n1282) );
NAND2X1TS U5438 ( .A(n2536), .B(n2312), .Y(n4310) );
NAND2X2TS U5439 ( .A(n3630), .B(intDX_EWSW[10]), .Y(n4315) );
NAND3X2TS U5440 ( .A(n4314), .B(n4315), .C(n4313), .Y(n1290) );
NAND2X2TS U5441 ( .A(n1838), .B(intDX_EWSW[9]), .Y(n4318) );
NAND2X2TS U5442 ( .A(n4864), .B(DmP_EXP_EWSW[9]), .Y(n4316) );
AOI22X1TS U5443 ( .A0(n5019), .A1(DmP_mant_SHT1_SW[8]), .B0(n5006), .B1(
DmP_mant_SHT1_SW[7]), .Y(n4319) );
NOR2X1TS U5444 ( .A(n4689), .B(n4324), .Y(n4327) );
NAND2X1TS U5445 ( .A(n3846), .B(Data_array_SWR_3__53_), .Y(n4330) );
AO22X4TS U5446 ( .A0(n6206), .A1(n2345), .B0(n4331), .B1(n6228), .Y(n6351)
);
AO22X4TS U5447 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[11]), .B0(n4707), .B1(
n5041), .Y(n6211) );
NAND2X2TS U5448 ( .A(n6201), .B(DmP_mant_SHT1_SW[50]), .Y(n6354) );
INVX2TS U5449 ( .A(n4335), .Y(n4341) );
INVX2TS U5450 ( .A(n2077), .Y(n4337) );
AND2X2TS U5451 ( .A(n4347), .B(Raw_mant_NRM_SWR[12]), .Y(n4350) );
OAI2BB1X4TS U5452 ( .A0N(LZD_output_NRM2_EW[2]), .A1N(n2384), .B0(n4908),
.Y(n1122) );
NAND2X1TS U5453 ( .A(n3587), .B(intDY_EWSW[60]), .Y(n4356) );
NAND2X1TS U5454 ( .A(n4863), .B(intDX_EWSW[60]), .Y(n4355) );
NAND2X1TS U5455 ( .A(n2524), .B(n2303), .Y(n4354) );
NAND3X2TS U5456 ( .A(n4356), .B(n4355), .C(n4354), .Y(n1527) );
NAND2X1TS U5457 ( .A(n2524), .B(DMP_EXP_EWSW[58]), .Y(n4357) );
NAND3X2TS U5458 ( .A(n4359), .B(n4358), .C(n4357), .Y(n1529) );
NAND2X1TS U5459 ( .A(n2536), .B(DMP_EXP_EWSW[52]), .Y(n4360) );
NAND2X2TS U5460 ( .A(n2526), .B(intDY_EWSW[54]), .Y(n4365) );
NAND2X2TS U5461 ( .A(n4369), .B(intDX_EWSW[54]), .Y(n4364) );
NAND2X1TS U5462 ( .A(n2534), .B(DMP_EXP_EWSW[54]), .Y(n4363) );
NAND3X2TS U5463 ( .A(n4365), .B(n4364), .C(n4363), .Y(n1533) );
NAND2X1TS U5464 ( .A(n2963), .B(n2292), .Y(n4368) );
NAND2X1TS U5465 ( .A(n2536), .B(DMP_EXP_EWSW[53]), .Y(n4366) );
NAND3X2TS U5466 ( .A(n4368), .B(n4367), .C(n4366), .Y(n1534) );
NAND2X1TS U5467 ( .A(n3087), .B(intDY_EWSW[57]), .Y(n4372) );
NAND2X1TS U5468 ( .A(n2534), .B(DMP_EXP_EWSW[57]), .Y(n4370) );
NAND3X2TS U5469 ( .A(n4372), .B(n4371), .C(n4370), .Y(n1530) );
NAND3X2TS U5470 ( .A(n4374), .B(n4375), .C(n4373), .Y(n1306) );
NAND2X1TS U5471 ( .A(n2535), .B(DmP_EXP_EWSW[1]), .Y(n4376) );
NAND3X2TS U5472 ( .A(n4377), .B(n4378), .C(n4376), .Y(n1308) );
NAND2X1TS U5473 ( .A(n2536), .B(DmP_EXP_EWSW[0]), .Y(n4380) );
NAND3X2TS U5474 ( .A(n4381), .B(n4382), .C(n4380), .Y(n1310) );
NAND3X2TS U5475 ( .A(n4384), .B(n4385), .C(n4383), .Y(n1587) );
NAND2X2TS U5476 ( .A(n5184), .B(n4671), .Y(n6426) );
NAND2X1TS U5477 ( .A(n4430), .B(intDY_EWSW[50]), .Y(n4388) );
NAND2X1TS U5478 ( .A(n2053), .B(intDX_EWSW[50]), .Y(n4387) );
NAND3X2TS U5479 ( .A(n4394), .B(n4395), .C(n4393), .Y(n1538) );
NAND2X1TS U5480 ( .A(n4839), .B(DMP_EXP_EWSW[5]), .Y(n4400) );
NAND3X2TS U5481 ( .A(n4404), .B(n4405), .C(n4403), .Y(n1304) );
NAND2X1TS U5482 ( .A(n4439), .B(n1984), .Y(n4408) );
NAND3X2TS U5483 ( .A(n4408), .B(n4407), .C(n4406), .Y(n1564) );
NAND2X1TS U5484 ( .A(n4439), .B(intDY_EWSW[24]), .Y(n4415) );
NAND3X2TS U5485 ( .A(n4415), .B(n4414), .C(n4413), .Y(n1563) );
NAND2X1TS U5486 ( .A(n2525), .B(DMP_EXP_EWSW[3]), .Y(n4432) );
OAI21X4TS U5487 ( .A0(n3022), .A1(n5419), .B0(n4435), .Y(n6369) );
NAND3X2TS U5488 ( .A(n4438), .B(n4437), .C(n4436), .Y(n1663) );
NAND2X2TS U5489 ( .A(n3630), .B(intDX_EWSW[54]), .Y(n4448) );
NAND2X1TS U5490 ( .A(n4834), .B(DmP_EXP_EWSW[54]), .Y(n4446) );
NAND3X2TS U5491 ( .A(n4448), .B(n4447), .C(n4446), .Y(n1204) );
NAND2X2TS U5492 ( .A(n4424), .B(intDX_EWSW[56]), .Y(n4451) );
NAND2X1TS U5493 ( .A(n2536), .B(DmP_EXP_EWSW[56]), .Y(n4449) );
NAND2X2TS U5494 ( .A(n4877), .B(intDY_EWSW[52]), .Y(n4453) );
NAND2X1TS U5495 ( .A(n4834), .B(DmP_EXP_EWSW[52]), .Y(n4452) );
NAND3X2TS U5496 ( .A(n4454), .B(n4453), .C(n4452), .Y(n1206) );
NAND2X2TS U5497 ( .A(n3124), .B(intDX_EWSW[53]), .Y(n4457) );
NAND2X2TS U5498 ( .A(n4838), .B(n2292), .Y(n4456) );
NAND2X1TS U5499 ( .A(n4834), .B(DmP_EXP_EWSW[53]), .Y(n4455) );
NAND3X2TS U5500 ( .A(n4457), .B(n4456), .C(n4455), .Y(n1205) );
NAND2X2TS U5501 ( .A(n2530), .B(intDX_EWSW[55]), .Y(n4460) );
NAND2X1TS U5502 ( .A(n2534), .B(DmP_EXP_EWSW[55]), .Y(n4458) );
NAND3X2TS U5503 ( .A(n4460), .B(n4459), .C(n4458), .Y(n1203) );
NAND2X2TS U5504 ( .A(n6392), .B(n6408), .Y(n6393) );
CLKBUFX3TS U5505 ( .A(n2533), .Y(n6262) );
CLKBUFX3TS U5506 ( .A(n6262), .Y(n6292) );
CLKBUFX3TS U5507 ( .A(n6292), .Y(n6254) );
CLKBUFX3TS U5508 ( .A(n6288), .Y(n4463) );
CLKBUFX2TS U5509 ( .A(n4463), .Y(n5672) );
CLKBUFX3TS U5510 ( .A(n4463), .Y(n5674) );
CLKBUFX3TS U5511 ( .A(n6290), .Y(n4464) );
CLKBUFX3TS U5512 ( .A(n4464), .Y(n5662) );
CLKBUFX3TS U5513 ( .A(n4462), .Y(n5647) );
CLKBUFX3TS U5514 ( .A(n4462), .Y(n5648) );
CLKBUFX3TS U5515 ( .A(n4463), .Y(n5673) );
CLKBUFX3TS U5516 ( .A(n6290), .Y(n4466) );
CLKBUFX3TS U5517 ( .A(n6290), .Y(n4461) );
CLKBUFX3TS U5518 ( .A(n4461), .Y(n5641) );
CLKBUFX3TS U5519 ( .A(n4461), .Y(n5640) );
CLKBUFX3TS U5520 ( .A(n4464), .Y(n5663) );
CLKBUFX3TS U5521 ( .A(n5621), .Y(n5678) );
CLKBUFX3TS U5522 ( .A(n4464), .Y(n5664) );
CLKBUFX3TS U5523 ( .A(n4466), .Y(n5656) );
CLKBUFX3TS U5524 ( .A(n6232), .Y(n5632) );
CLKBUFX3TS U5525 ( .A(n5620), .Y(n5679) );
CLKBUFX3TS U5526 ( .A(n4461), .Y(n5642) );
CLKBUFX3TS U5527 ( .A(n4462), .Y(n5650) );
CLKBUFX3TS U5528 ( .A(n4464), .Y(n5665) );
CLKBUFX3TS U5529 ( .A(n6292), .Y(n6233) );
CLKBUFX3TS U5530 ( .A(n4466), .Y(n5657) );
CLKBUFX3TS U5531 ( .A(n6254), .Y(n5619) );
CLKBUFX2TS U5532 ( .A(n5658), .Y(n5622) );
CLKBUFX2TS U5533 ( .A(n6232), .Y(n5621) );
CLKBUFX3TS U5534 ( .A(n6233), .Y(n5630) );
CLKBUFX3TS U5535 ( .A(n6255), .Y(n5631) );
CLKBUFX3TS U5536 ( .A(n6292), .Y(n6255) );
CLKBUFX3TS U5537 ( .A(n6255), .Y(n5635) );
BUFX3TS U5538 ( .A(n4465), .Y(n6289) );
CLKBUFX3TS U5539 ( .A(n4462), .Y(n5651) );
CLKBUFX3TS U5540 ( .A(n5618), .Y(n5677) );
CLKBUFX3TS U5541 ( .A(n6286), .Y(n5636) );
CLKBUFX3TS U5542 ( .A(n4464), .Y(n5666) );
CLKBUFX3TS U5543 ( .A(n4461), .Y(n5639) );
CLKBUFX3TS U5544 ( .A(n4466), .Y(n5654) );
BUFX3TS U5545 ( .A(n5643), .Y(n6287) );
BUFX3TS U5546 ( .A(n6287), .Y(n6235) );
BUFX3TS U5547 ( .A(n2569), .Y(n5683) );
CLKBUFX3TS U5548 ( .A(n4464), .Y(n5661) );
CLKBUFX3TS U5549 ( .A(n6255), .Y(n5618) );
BUFX3TS U5550 ( .A(n4465), .Y(n6239) );
BUFX3TS U5551 ( .A(n6286), .Y(n6281) );
BUFX3TS U5552 ( .A(n4461), .Y(n6267) );
BUFX3TS U5553 ( .A(n6232), .Y(n6282) );
BUFX3TS U5554 ( .A(n6254), .Y(n6283) );
BUFX3TS U5555 ( .A(n6255), .Y(n6284) );
BUFX3TS U5556 ( .A(n6236), .Y(n5670) );
BUFX3TS U5557 ( .A(n5641), .Y(n6280) );
BUFX3TS U5558 ( .A(n6234), .Y(n6285) );
BUFX3TS U5559 ( .A(n6287), .Y(n6268) );
BUFX3TS U5560 ( .A(n5656), .Y(n6279) );
BUFX3TS U5561 ( .A(n6254), .Y(n6278) );
BUFX3TS U5562 ( .A(n5654), .Y(n6276) );
CLKBUFX2TS U5563 ( .A(n4466), .Y(n5653) );
CLKBUFX3TS U5564 ( .A(n4464), .Y(n5667) );
BUFX3TS U5565 ( .A(n5667), .Y(n6247) );
CLKBUFX3TS U5566 ( .A(n4466), .Y(n5658) );
BUFX3TS U5567 ( .A(n5658), .Y(n6248) );
BUFX3TS U5568 ( .A(n6292), .Y(n6291) );
BUFX3TS U5569 ( .A(n2538), .Y(n6250) );
BUFX3TS U5570 ( .A(n2515), .Y(n6251) );
BUFX3TS U5571 ( .A(n2520), .Y(n6252) );
BUFX3TS U5572 ( .A(n5667), .Y(n6271) );
BUFX3TS U5573 ( .A(n5658), .Y(n6272) );
CLKBUFX3TS U5574 ( .A(n2532), .Y(n5676) );
BUFX3TS U5575 ( .A(n6232), .Y(n5628) );
CLKBUFX3TS U5576 ( .A(n6262), .Y(n5685) );
BUFX3TS U5577 ( .A(n6287), .Y(n6274) );
CLKBUFX3TS U5578 ( .A(n4461), .Y(n5638) );
BUFX3TS U5579 ( .A(n6288), .Y(n6260) );
BUFX3TS U5580 ( .A(n6259), .Y(n6237) );
BUFX3TS U5581 ( .A(n5643), .Y(n6263) );
BUFX3TS U5582 ( .A(n6232), .Y(n6266) );
BUFX3TS U5583 ( .A(n6288), .Y(n6261) );
BUFX3TS U5584 ( .A(n4465), .Y(n6265) );
BUFX3TS U5585 ( .A(n2512), .Y(n6264) );
BUFX3TS U5586 ( .A(n6287), .Y(n6270) );
BUFX3TS U5587 ( .A(n6287), .Y(n6269) );
BUFX3TS U5588 ( .A(n6291), .Y(n6246) );
CLKBUFX2TS U5589 ( .A(n4462), .Y(n5645) );
BUFX3TS U5590 ( .A(n4461), .Y(n5637) );
CLKBUFX3TS U5591 ( .A(n6236), .Y(n5669) );
CLKBUFX2TS U5592 ( .A(n4464), .Y(n5660) );
BUFX3TS U5593 ( .A(n6254), .Y(n5633) );
BUFX3TS U5594 ( .A(n6257), .Y(n5668) );
BUFX3TS U5595 ( .A(n5660), .Y(n5675) );
CLKBUFX3TS U5596 ( .A(n4462), .Y(n5644) );
BUFX3TS U5597 ( .A(n4463), .Y(n5671) );
CLKBUFX3TS U5598 ( .A(n6255), .Y(n5634) );
BUFX3TS U5599 ( .A(n6291), .Y(n6245) );
BUFX3TS U5600 ( .A(n4464), .Y(n5659) );
BUFX3TS U5601 ( .A(n4465), .Y(n6242) );
CLKBUFX3TS U5602 ( .A(n4466), .Y(n5652) );
BUFX3TS U5603 ( .A(n6291), .Y(n6243) );
BUFX3TS U5604 ( .A(n6291), .Y(n6244) );
OAI21X1TS U5605 ( .A0(n2383), .A1(n2522), .B0(n2384), .Y(n1729) );
CLKMX2X2TS U5606 ( .A(DMP_exp_NRM2_EW[9]), .B(DMP_exp_NRM_EW[9]), .S0(n2563),
.Y(n1316) );
CLKMX2X2TS U5607 ( .A(DMP_exp_NRM2_EW[6]), .B(DMP_exp_NRM_EW[6]), .S0(n2562),
.Y(n1331) );
NAND3X2TS U5608 ( .A(n6179), .B(n4467), .C(n6178), .Y(final_result_ieee[14])
);
NAND2X1TS U5609 ( .A(n5571), .B(final_result_ieee[14]), .Y(n6422) );
CLKMX2X2TS U5610 ( .A(DMP_exp_NRM2_EW[3]), .B(DMP_exp_NRM_EW[3]), .S0(n2563),
.Y(n1346) );
CLKMX2X2TS U5611 ( .A(DMP_exp_NRM2_EW[7]), .B(DMP_exp_NRM_EW[7]), .S0(n2562),
.Y(n1326) );
CLKMX2X2TS U5612 ( .A(DMP_exp_NRM2_EW[1]), .B(DMP_exp_NRM_EW[1]), .S0(n2563),
.Y(n1356) );
CLKMX2X2TS U5613 ( .A(DMP_exp_NRM2_EW[8]), .B(DMP_exp_NRM_EW[8]), .S0(n2562),
.Y(n1321) );
MXI2X1TS U5614 ( .A(beg_OP), .B(n5494), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n4469) );
NOR2X1TS U5615 ( .A(inst_FSM_INPUT_ENABLE_state_reg[1]), .B(
inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n4468) );
NAND2X1TS U5616 ( .A(n4468), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(
n4470) );
OAI21X1TS U5617 ( .A0(n4469), .A1(n4471), .B0(n4470), .Y(n1802) );
INVX2TS U5618 ( .A(n4471), .Y(n5212) );
MXI2X4TS U5619 ( .A(inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n4471), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(n4577) );
NAND2X8TS U5620 ( .A(n4577), .B(beg_OP), .Y(n5234) );
NAND2X1TS U5621 ( .A(n4473), .B(n4636), .Y(n4475) );
NOR2X2TS U5622 ( .A(n2764), .B(n4477), .Y(n4546) );
AOI22X1TS U5623 ( .A0(n5183), .A1(n4546), .B0(DmP_mant_SFG_SWR[35]), .B1(
n5125), .Y(n4479) );
NOR2X8TS U5624 ( .A(n2764), .B(n2449), .Y(n5123) );
AOI22X1TS U5625 ( .A0(n5183), .A1(n4542), .B0(n1840), .B1(n5125), .Y(n4482)
);
AOI22X1TS U5626 ( .A0(n4637), .A1(n4620), .B0(n2780), .B1(n1626), .Y(n4483)
);
OAI2BB1X1TS U5627 ( .A0N(n6123), .A1N(n6122), .B0(n6121), .Y(n4491) );
INVX2TS U5628 ( .A(n4491), .Y(n5010) );
OAI22X1TS U5629 ( .A0(n4698), .A1(n4715), .B0(n4702), .B1(n5010), .Y(n4492)
);
INVX2TS U5630 ( .A(n4518), .Y(n5012) );
NOR2X1TS U5631 ( .A(n4669), .B(n5012), .Y(n5126) );
AOI22X1TS U5632 ( .A0(n5126), .A1(n5149), .B0(DmP_mant_SFG_SWR[0]), .B1(
n5125), .Y(n4494) );
CLKMX2X3TS U5633 ( .A(Data_Y[1]), .B(n2310), .S0(n5242), .Y(n1727) );
NOR2X1TS U5634 ( .A(n2611), .B(n5050), .Y(n4498) );
NOR2X1TS U5635 ( .A(n4702), .B(n4717), .Y(n4497) );
NAND2X2TS U5636 ( .A(n5151), .B(n1871), .Y(n4503) );
NOR2X1TS U5637 ( .A(n4718), .B(n4715), .Y(n4500) );
NOR2X1TS U5638 ( .A(n3833), .B(n4701), .Y(n4499) );
AOI22X1TS U5639 ( .A0(n4506), .A1(n4546), .B0(DmP_mant_SFG_SWR[38]), .B1(
n5125), .Y(n4505) );
AOI22X1TS U5640 ( .A0(n4671), .A1(n4546), .B0(DmP_mant_SFG_SWR[37]), .B1(
n5125), .Y(n4509) );
AOI22X1TS U5641 ( .A0(n4671), .A1(n4542), .B0(DmP_mant_SFG_SWR[17]), .B1(
n5125), .Y(n4511) );
NAND2X1TS U5642 ( .A(n2764), .B(DmP_mant_SFG_SWR[1]), .Y(n4514) );
NAND3X1TS U5643 ( .A(n4722), .B(n5123), .C(Data_array_SWR_3__53_), .Y(n4513)
);
NAND2X1TS U5644 ( .A(n4659), .B(n4518), .Y(n4519) );
NAND2X1TS U5645 ( .A(n4659), .B(n5034), .Y(n4527) );
NAND2X2TS U5646 ( .A(n5153), .B(n4685), .Y(n4538) );
AOI22X1TS U5647 ( .A0(n5182), .A1(n4542), .B0(DmP_mant_SFG_SWR[18]), .B1(
n5125), .Y(n4545) );
NAND2X2TS U5648 ( .A(n6446), .B(n4543), .Y(n4544) );
AOI22X1TS U5649 ( .A0(n5182), .A1(n4546), .B0(DmP_mant_SFG_SWR[36]), .B1(
n5125), .Y(n4548) );
NAND2X2TS U5650 ( .A(n6446), .B(n5149), .Y(n4547) );
MXI2X1TS U5651 ( .A(Raw_mant_NRM_SWR[10]), .B(DMP_SFG[8]), .S0(n3287), .Y(
n4550) );
NOR2BX4TS U5652 ( .AN(n2487), .B(n4917), .Y(n4551) );
NOR2BX4TS U5653 ( .AN(n2549), .B(n2257), .Y(n5128) );
MXI2X1TS U5654 ( .A(n4554), .B(n4555), .S0(DmP_mant_SFG_SWR[10]), .Y(n4549)
);
NAND2X1TS U5655 ( .A(n4550), .B(n4549), .Y(n1096) );
MXI2X1TS U5656 ( .A(Raw_mant_NRM_SWR[12]), .B(DMP_SFG[10]), .S0(n3232), .Y(
n4553) );
MXI2X1TS U5657 ( .A(n4551), .B(n4555), .S0(DmP_mant_SFG_SWR[12]), .Y(n4552)
);
NAND2X1TS U5658 ( .A(n4553), .B(n4552), .Y(n1112) );
MXI2X1TS U5659 ( .A(Raw_mant_NRM_SWR[6]), .B(DMP_SFG[4]), .S0(n3179), .Y(
n4557) );
MXI2X1TS U5660 ( .A(n4551), .B(n5128), .S0(DmP_mant_SFG_SWR[6]), .Y(n4556)
);
NAND2X1TS U5661 ( .A(n4557), .B(n4556), .Y(n1123) );
MXI2X1TS U5662 ( .A(Raw_mant_NRM_SWR[11]), .B(DMP_SFG[9]), .S0(n3287), .Y(
n4559) );
MXI2X1TS U5663 ( .A(n4554), .B(n5128), .S0(DmP_mant_SFG_SWR[11]), .Y(n4558)
);
NAND2X1TS U5664 ( .A(n4559), .B(n4558), .Y(n1116) );
MXI2X1TS U5665 ( .A(Raw_mant_NRM_SWR[7]), .B(DMP_SFG[5]), .S0(n3232), .Y(
n4561) );
MXI2X1TS U5666 ( .A(n4551), .B(n5128), .S0(DmP_mant_SFG_SWR[7]), .Y(n4560)
);
NAND2X1TS U5667 ( .A(n4561), .B(n4560), .Y(n1120) );
MXI2X1TS U5668 ( .A(Raw_mant_NRM_SWR[8]), .B(DMP_SFG[6]), .S0(n3287), .Y(
n4563) );
MXI2X1TS U5669 ( .A(n4554), .B(n4555), .S0(DmP_mant_SFG_SWR[8]), .Y(n4562)
);
NAND2X1TS U5670 ( .A(n4563), .B(n4562), .Y(n1118) );
MXI2X1TS U5671 ( .A(n1856), .B(DMP_SFG[2]), .S0(n3287), .Y(n4565) );
MXI2X1TS U5672 ( .A(n4554), .B(n4555), .S0(DmP_mant_SFG_SWR[4]), .Y(n4564)
);
NAND2X1TS U5673 ( .A(n4565), .B(n4564), .Y(n1126) );
MXI2X1TS U5674 ( .A(Raw_mant_NRM_SWR[13]), .B(DMP_SFG[11]), .S0(n3232), .Y(
n4567) );
MXI2X1TS U5675 ( .A(n4554), .B(n4555), .S0(DmP_mant_SFG_SWR[13]), .Y(n4566)
);
NAND2X1TS U5676 ( .A(n4567), .B(n4566), .Y(n1110) );
MXI2X1TS U5677 ( .A(Raw_mant_NRM_SWR[5]), .B(DMP_SFG[3]), .S0(n5208), .Y(
n4569) );
MXI2X1TS U5678 ( .A(n4554), .B(n5128), .S0(DmP_mant_SFG_SWR[5]), .Y(n4568)
);
NAND2X1TS U5679 ( .A(n4569), .B(n4568), .Y(n1131) );
MXI2X1TS U5680 ( .A(Raw_mant_NRM_SWR[2]), .B(DMP_SFG[0]), .S0(n5208), .Y(
n4571) );
MXI2X1TS U5681 ( .A(n4551), .B(n5128), .S0(DmP_mant_SFG_SWR[2]), .Y(n4570)
);
NAND2X1TS U5682 ( .A(n4571), .B(n4570), .Y(n1133) );
MXI2X1TS U5683 ( .A(Raw_mant_NRM_SWR[3]), .B(DMP_SFG[1]), .S0(n3287), .Y(
n4573) );
MXI2X1TS U5684 ( .A(n4551), .B(n5128), .S0(DmP_mant_SFG_SWR[3]), .Y(n4572)
);
NAND2X1TS U5685 ( .A(n4573), .B(n4572), .Y(n1128) );
MXI2X1TS U5686 ( .A(Raw_mant_NRM_SWR[9]), .B(DMP_SFG[7]), .S0(n3287), .Y(
n4575) );
MXI2X1TS U5687 ( .A(n4554), .B(n5128), .S0(DmP_mant_SFG_SWR[9]), .Y(n4574)
);
NAND2X1TS U5688 ( .A(n4575), .B(n4574), .Y(n1104) );
MXI2X1TS U5689 ( .A(n4551), .B(n4555), .S0(DmP_mant_SFG_SWR[1]), .Y(n4576)
);
OAI21X1TS U5690 ( .A0(n5208), .A1(n5419), .B0(n4576), .Y(n1139) );
CLKINVX1TS U5691 ( .A(n4577), .Y(n4580) );
NOR2X1TS U5692 ( .A(n5489), .B(inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n4578) );
NAND3BX2TS U5693 ( .AN(n4584), .B(n4583), .C(n3130), .Y(n4585) );
NOR2X1TS U5694 ( .A(n3832), .B(n5058), .Y(n4589) );
NOR2X1TS U5695 ( .A(n4716), .B(n4654), .Y(n4588) );
NAND2X1TS U5696 ( .A(n1919), .B(n5060), .Y(n4591) );
NAND2X1TS U5697 ( .A(n1869), .B(n4636), .Y(n4590) );
NAND2X2TS U5698 ( .A(n2261), .B(n2297), .Y(n4602) );
NAND2X2TS U5699 ( .A(n1869), .B(n5055), .Y(n4601) );
NAND2X1TS U5700 ( .A(n2558), .B(n5014), .Y(n4623) );
NAND2X1TS U5701 ( .A(n2555), .B(n4636), .Y(n4641) );
NAND2X1TS U5702 ( .A(n4637), .B(n5060), .Y(n4640) );
INVX2TS U5703 ( .A(n1645), .Y(n4642) );
INVX2TS U5704 ( .A(n5043), .Y(n4665) );
NOR2X1TS U5705 ( .A(n4669), .B(n4668), .Y(n4670) );
INVX2TS U5706 ( .A(n5037), .Y(n4674) );
NOR2X1TS U5707 ( .A(n3833), .B(n4675), .Y(n4676) );
NAND2X2TS U5708 ( .A(n4722), .B(n5042), .Y(n4688) );
NOR2X1TS U5709 ( .A(n4689), .B(n5058), .Y(n4690) );
NAND2X2TS U5710 ( .A(n4692), .B(n4691), .Y(n4694) );
NAND2X2TS U5711 ( .A(n4723), .B(n5023), .Y(n4693) );
INVX2TS U5712 ( .A(n5014), .Y(n4697) );
INVX2TS U5713 ( .A(n4699), .Y(n5059) );
NOR2X1TS U5714 ( .A(n3832), .B(n5059), .Y(n4700) );
NAND2X1TS U5715 ( .A(n4704), .B(n4711), .Y(n4705) );
AOI2BB2X1TS U5716 ( .B0(n4708), .B1(n4707), .A0N(n4706), .A1N(n5012), .Y(
n4714) );
NOR2X1TS U5717 ( .A(n4716), .B(n4715), .Y(n4720) );
NAND2X2TS U5718 ( .A(n4723), .B(n5038), .Y(n4724) );
INVX2TS U5719 ( .A(n4728), .Y(n4732) );
NOR2X1TS U5720 ( .A(n4729), .B(intDX_EWSW[63]), .Y(n4730) );
NAND2X2TS U5721 ( .A(n4732), .B(n4731), .Y(n5162) );
OAI21X4TS U5722 ( .A0(n2362), .A1(n4747), .B0(n4746), .Y(n4750) );
NAND2X2TS U5723 ( .A(n3297), .B(n4759), .Y(n4760) );
OAI21X4TS U5724 ( .A0(n4962), .A1(n3207), .B0(n4779), .Y(n4772) );
OAI21X4TS U5725 ( .A0(n2653), .A1(n4765), .B0(n4764), .Y(n4768) );
AOI21X4TS U5726 ( .A0(n4772), .A1(n4771), .B0(n4770), .Y(n4773) );
OAI21X4TS U5727 ( .A0(n2362), .A1(n4774), .B0(n4773), .Y(n4777) );
OAI21X4TS U5728 ( .A0(n2362), .A1(n4958), .B0(n4962), .Y(n4778) );
OAI21X4TS U5729 ( .A0(n2362), .A1(n4784), .B0(n5325), .Y(n4786) );
NAND2X1TS U5730 ( .A(n2535), .B(DmP_EXP_EWSW[57]), .Y(n4787) );
NAND2X2TS U5731 ( .A(n3630), .B(intDX_EWSW[34]), .Y(n4797) );
NAND2X1TS U5732 ( .A(n4839), .B(DmP_EXP_EWSW[34]), .Y(n4795) );
NAND2X2TS U5733 ( .A(n1838), .B(intDX_EWSW[29]), .Y(n4800) );
NAND2X1TS U5734 ( .A(n4839), .B(DmP_EXP_EWSW[29]), .Y(n4798) );
NAND2X2TS U5735 ( .A(n2531), .B(intDX_EWSW[27]), .Y(n4810) );
NAND2X1TS U5736 ( .A(n4834), .B(DmP_EXP_EWSW[27]), .Y(n4808) );
NAND2X2TS U5737 ( .A(n3630), .B(intDX_EWSW[35]), .Y(n4813) );
NAND2X1TS U5738 ( .A(n4839), .B(DmP_EXP_EWSW[35]), .Y(n4811) );
NAND2X2TS U5739 ( .A(n3124), .B(intDX_EWSW[36]), .Y(n4816) );
NAND2X2TS U5740 ( .A(n3124), .B(intDX_EWSW[31]), .Y(n4819) );
NAND2X2TS U5741 ( .A(n4424), .B(intDX_EWSW[37]), .Y(n4822) );
NAND2X2TS U5742 ( .A(n4424), .B(intDX_EWSW[28]), .Y(n4825) );
NAND2X1TS U5743 ( .A(n4839), .B(DmP_EXP_EWSW[28]), .Y(n4823) );
NAND2X2TS U5744 ( .A(n2530), .B(intDX_EWSW[45]), .Y(n4827) );
NAND2X1TS U5745 ( .A(n4839), .B(DmP_EXP_EWSW[45]), .Y(n4826) );
NAND2X2TS U5746 ( .A(n4430), .B(intDX_EWSW[50]), .Y(n4837) );
NAND2X1TS U5747 ( .A(n4834), .B(DmP_EXP_EWSW[50]), .Y(n4835) );
NAND2X2TS U5748 ( .A(n2530), .B(intDX_EWSW[26]), .Y(n4842) );
NAND2X1TS U5749 ( .A(n4839), .B(DmP_EXP_EWSW[26]), .Y(n4840) );
NAND2X2TS U5750 ( .A(n2027), .B(intDX_EWSW[18]), .Y(n4845) );
NAND2X1TS U5751 ( .A(n4369), .B(n2025), .Y(n4844) );
NAND2X1TS U5752 ( .A(n2536), .B(n2256), .Y(n4843) );
NAND2X1TS U5753 ( .A(n2536), .B(DmP_EXP_EWSW[20]), .Y(n4846) );
NAND2X2TS U5754 ( .A(n2963), .B(intDX_EWSW[49]), .Y(n4851) );
NAND2X1TS U5755 ( .A(n2535), .B(DmP_EXP_EWSW[49]), .Y(n4849) );
NAND2X2TS U5756 ( .A(n2116), .B(intDY_EWSW[19]), .Y(n4858) );
NAND2X1TS U5757 ( .A(n2534), .B(DmP_EXP_EWSW[19]), .Y(n4857) );
NAND2X1TS U5758 ( .A(n2536), .B(DmP_EXP_EWSW[21]), .Y(n4860) );
NAND2X2TS U5759 ( .A(n2963), .B(intDX_EWSW[5]), .Y(n4867) );
NOR2X2TS U5760 ( .A(n5493), .B(n2561), .Y(n4906) );
AOI22X1TS U5761 ( .A0(n4906), .A1(n2571), .B0(shift_value_SHT2_EWR[4]), .B1(
n6229), .Y(n4868) );
NAND2X1TS U5762 ( .A(n2524), .B(DMP_EXP_EWSW[14]), .Y(n4870) );
NAND2X2TS U5763 ( .A(n1836), .B(n2310), .Y(n4876) );
NAND2X1TS U5764 ( .A(n2951), .B(intDX_EWSW[2]), .Y(n4879) );
AOI22X1TS U5765 ( .A0(n4906), .A1(n2565), .B0(shift_value_SHT2_EWR[3]), .B1(
n6229), .Y(n4882) );
NAND2X1TS U5766 ( .A(n4884), .B(Raw_mant_NRM_SWR[9]), .Y(n4889) );
INVX2TS U5767 ( .A(n4885), .Y(n4888) );
OR2X2TS U5768 ( .A(n2474), .B(n4886), .Y(n4887) );
OR3X1TS U5769 ( .A(Raw_mant_NRM_SWR[5]), .B(Raw_mant_NRM_SWR[2]), .C(
Raw_mant_NRM_SWR[6]), .Y(n4900) );
OAI21X4TS U5770 ( .A0(n4962), .A1(n4914), .B0(n4913), .Y(n4946) );
OAI21X4TS U5771 ( .A0(n2653), .A1(n2930), .B0(n2325), .Y(n4919) );
INVX12TS U5772 ( .A(n2930), .Y(n4987) );
NOR2X8TS U5773 ( .A(n4958), .B(n4936), .Y(n4952) );
INVX2TS U5774 ( .A(n2744), .Y(n4941) );
NAND2X2TS U5775 ( .A(n4941), .B(n4940), .Y(n4942) );
AOI21X4TS U5776 ( .A0(n4946), .A1(n3017), .B0(n4945), .Y(n4947) );
OAI21X4TS U5777 ( .A0(n2653), .A1(n4954), .B0(n4953), .Y(n4956) );
AOI21X4TS U5778 ( .A0(n3272), .A1(n4959), .B0(n2711), .Y(n4960) );
OAI21X4TS U5779 ( .A0(n4962), .A1(n4961), .B0(n4960), .Y(n4980) );
OAI21X4TS U5780 ( .A0(n2653), .A1(n4964), .B0(n4963), .Y(n4967) );
AOI21X4TS U5781 ( .A0(n4990), .A1(n4971), .B0(n4970), .Y(n4972) );
OAI21X4TS U5782 ( .A0(n2362), .A1(n4973), .B0(n4972), .Y(n4976) );
AOI21X4TS U5783 ( .A0(n4980), .A1(n1921), .B0(n4979), .Y(n4981) );
OAI21X4TS U5784 ( .A0(n2362), .A1(n4982), .B0(n4981), .Y(n4986) );
AOI21X4TS U5785 ( .A0(n4990), .A1(n4989), .B0(n4988), .Y(n4991) );
OAI21X4TS U5786 ( .A0(n2362), .A1(n4992), .B0(n4991), .Y(n4996) );
AOI22X1TS U5787 ( .A0(n5019), .A1(DmP_mant_SHT1_SW[1]), .B0(n5006), .B1(
DmP_mant_SHT1_SW[0]), .Y(n5007) );
OA21X4TS U5788 ( .A0(n3022), .A1(n5417), .B0(n5007), .Y(n5008) );
NAND2X1TS U5789 ( .A(n6205), .B(n2037), .Y(n6337) );
NAND2X1TS U5790 ( .A(n6206), .B(Raw_mant_NRM_SWR[29]), .Y(n6297) );
NAND2X1TS U5791 ( .A(n6217), .B(Raw_mant_NRM_SWR[22]), .Y(n6314) );
NAND2X1TS U5792 ( .A(n2982), .B(Raw_mant_NRM_SWR[31]), .Y(n6400) );
NAND2X1TS U5793 ( .A(n6217), .B(Raw_mant_NRM_SWR[31]), .Y(n6389) );
NAND2X1TS U5794 ( .A(n6217), .B(Raw_mant_NRM_SWR[15]), .Y(n6302) );
AOI22X1TS U5795 ( .A0(n6206), .A1(Raw_mant_NRM_SWR[27]), .B0(n1859), .B1(
n5041), .Y(n6403) );
AOI22X1TS U5796 ( .A0(n6206), .A1(Raw_mant_NRM_SWR[5]), .B0(n5025), .B1(
n6230), .Y(n6356) );
AOI22X1TS U5797 ( .A0(n2982), .A1(Raw_mant_NRM_SWR[40]), .B0(n5042), .B1(
n6228), .Y(n6331) );
INVX2TS U5798 ( .A(n5047), .Y(n5048) );
INVX2TS U5799 ( .A(n5051), .Y(n5052) );
INVX2TS U5800 ( .A(n5055), .Y(n5056) );
INVX2TS U5801 ( .A(n5060), .Y(n5062) );
AOI21X4TS U5802 ( .A0(n5066), .A1(n2757), .B0(n5065), .Y(n5067) );
OAI21X4TS U5803 ( .A0(n5068), .A1(n5096), .B0(n5067), .Y(n5071) );
XNOR2X4TS U5804 ( .A(n5071), .B(n5070), .Y(n5072) );
CLKMX2X2TS U5805 ( .A(n5072), .B(Raw_mant_NRM_SWR[19]), .S0(n5089), .Y(n1179) );
NAND2X2TS U5806 ( .A(n5078), .B(n5077), .Y(n5079) );
XNOR2X4TS U5807 ( .A(n5099), .B(n5098), .Y(n5100) );
CLKMX2X2TS U5808 ( .A(n5100), .B(Raw_mant_NRM_SWR[18]), .S0(n5319), .Y(n1180) );
CLKMX2X2TS U5809 ( .A(ZERO_FLAG_SHT1SHT2), .B(ZERO_FLAG_NRM), .S0(n2563),
.Y(n1194) );
CLKMX2X2TS U5810 ( .A(SIGN_FLAG_SHT1SHT2), .B(SIGN_FLAG_NRM), .S0(n2562),
.Y(n1185) );
CLKMX2X2TS U5811 ( .A(DMP_exp_NRM2_EW[4]), .B(DMP_exp_NRM_EW[4]), .S0(n2562),
.Y(n1341) );
CLKMX2X2TS U5812 ( .A(DMP_exp_NRM2_EW[5]), .B(DMP_exp_NRM_EW[5]), .S0(n2563),
.Y(n1336) );
CLKMX2X2TS U5813 ( .A(DMP_exp_NRM2_EW[10]), .B(DMP_exp_NRM_EW[10]), .S0(
n2562), .Y(n1311) );
CLKBUFX3TS U5814 ( .A(n6253), .Y(n5627) );
CLKBUFX3TS U5815 ( .A(n2569), .Y(n5682) );
CLKBUFX3TS U5816 ( .A(n6253), .Y(n5625) );
CLKBUFX3TS U5817 ( .A(n6253), .Y(n5626) );
CLKBUFX3TS U5818 ( .A(n6262), .Y(n5681) );
CLKBUFX2TS U5819 ( .A(n6262), .Y(n5684) );
BUFX3TS U5820 ( .A(n2539), .Y(n6277) );
BUFX3TS U5821 ( .A(n5685), .Y(n6273) );
BUFX3TS U5822 ( .A(n6253), .Y(n5623) );
BUFX3TS U5823 ( .A(n6253), .Y(n5624) );
NAND2X1TS U5824 ( .A(n2214), .B(n5731), .Y(n5103) );
NAND2X2TS U5825 ( .A(n5103), .B(n5102), .Y(final_result_ieee[31]) );
NAND2X2TS U5826 ( .A(n6134), .B(n5104), .Y(final_result_ieee[18]) );
NAND2X1TS U5827 ( .A(n2214), .B(n5766), .Y(n5106) );
NAND2X2TS U5828 ( .A(n5106), .B(n5105), .Y(final_result_ieee[38]) );
NAND2X2TS U5829 ( .A(n6135), .B(n5107), .Y(final_result_ieee[12]) );
NAND2X2TS U5830 ( .A(n6127), .B(n5108), .Y(final_result_ieee[19]) );
NAND2X2TS U5831 ( .A(n6128), .B(n5109), .Y(final_result_ieee[11]) );
NAND2X1TS U5832 ( .A(n2211), .B(n5732), .Y(n5111) );
NAND2X2TS U5833 ( .A(n5111), .B(n5110), .Y(final_result_ieee[30]) );
NAND2X1TS U5834 ( .A(n2214), .B(n5809), .Y(n5113) );
NAND2X2TS U5835 ( .A(n5113), .B(n5112), .Y(final_result_ieee[39]) );
NAND2X2TS U5836 ( .A(n6129), .B(n5114), .Y(final_result_ieee[13]) );
NAND2X2TS U5837 ( .A(n6137), .B(n5115), .Y(final_result_ieee[20]) );
NAND2X2TS U5838 ( .A(n6136), .B(n5116), .Y(final_result_ieee[10]) );
NAND2X1TS U5839 ( .A(n2211), .B(n5768), .Y(n5118) );
NAND2X2TS U5840 ( .A(n5118), .B(n5117), .Y(final_result_ieee[37]) );
NAND2X1TS U5841 ( .A(n2211), .B(n5710), .Y(n5120) );
NAND2X2TS U5842 ( .A(n5120), .B(n5119), .Y(final_result_ieee[32]) );
NAND2X1TS U5843 ( .A(n2214), .B(n5793), .Y(n5122) );
NAND2X2TS U5844 ( .A(n5122), .B(n5121), .Y(final_result_ieee[40]) );
INVX2TS U5845 ( .A(n6147), .Y(n5686) );
AOI22X1TS U5846 ( .A0(n5126), .A1(n5161), .B0(DmP_mant_SFG_SWR[54]), .B1(
n5125), .Y(n5127) );
MXI2X1TS U5847 ( .A(n4554), .B(n5128), .S0(DmP_mant_SFG_SWR[0]), .Y(n5129)
);
OAI21X1TS U5848 ( .A0(n5208), .A1(n5546), .B0(n5129), .Y(n1136) );
INVX2TS U5849 ( .A(DmP_mant_SFG_SWR[13]), .Y(n5131) );
INVX2TS U5850 ( .A(DmP_mant_SFG_SWR[12]), .Y(n5133) );
CLKMX2X2TS U5851 ( .A(n6414), .B(n5133), .S0(n5232), .Y(n5134) );
OAI2BB1X2TS U5852 ( .A0N(n5149), .A1N(n6457), .B0(n5144), .Y(n1030) );
CLKMX2X2TS U5853 ( .A(n6442), .B(n5567), .S0(n5271), .Y(n5148) );
MXI2X1TS U5854 ( .A(n5164), .B(final_result_ieee[54]), .S0(n5277), .Y(n5165)
);
MXI2X1TS U5855 ( .A(n5166), .B(final_result_ieee[60]), .S0(n5277), .Y(n5167)
);
MXI2X1TS U5856 ( .A(n3992), .B(final_result_ieee[58]), .S0(n5277), .Y(n5168)
);
MXI2X1TS U5857 ( .A(n5169), .B(final_result_ieee[52]), .S0(n5243), .Y(n5170)
);
MXI2X1TS U5858 ( .A(n1910), .B(final_result_ieee[56]), .S0(n5277), .Y(n5171)
);
MXI2X1TS U5859 ( .A(n5172), .B(final_result_ieee[59]), .S0(n5277), .Y(n5173)
);
MXI2X1TS U5860 ( .A(n5174), .B(final_result_ieee[55]), .S0(n5277), .Y(n5175)
);
MXI2X1TS U5861 ( .A(n5176), .B(final_result_ieee[53]), .S0(n5277), .Y(n5177)
);
MXI2X1TS U5862 ( .A(n5178), .B(final_result_ieee[57]), .S0(n5277), .Y(n5179)
);
MXI2X1TS U5863 ( .A(n5180), .B(final_result_ieee[61]), .S0(n5277), .Y(n5181)
);
NAND2X2TS U5864 ( .A(n5184), .B(n5182), .Y(n6428) );
NAND2X2TS U5865 ( .A(n5184), .B(n5183), .Y(n6430) );
NAND3X2TS U5866 ( .A(n6166), .B(n5185), .C(n6165), .Y(final_result_ieee[17])
);
NAND3X2TS U5867 ( .A(n6185), .B(n5186), .C(n6184), .Y(final_result_ieee[36])
);
NAND3X2TS U5868 ( .A(n6198), .B(n5187), .C(n6197), .Y(final_result_ieee[35])
);
NAND3X2TS U5869 ( .A(n6187), .B(n5188), .C(n6186), .Y(final_result_ieee[34])
);
NAND3X2TS U5870 ( .A(n6181), .B(n5190), .C(n6180), .Y(final_result_ieee[16])
);
MXI2X1TS U5871 ( .A(n5358), .B(n5510), .S0(n5191), .Y(n1328) );
MXI2X1TS U5872 ( .A(n5357), .B(n5509), .S0(n5191), .Y(n1323) );
MXI2X1TS U5873 ( .A(n5356), .B(n5508), .S0(n5191), .Y(n1318) );
MXI2X1TS U5874 ( .A(n5500), .B(n5409), .S0(n5191), .Y(n1358) );
MXI2X1TS U5875 ( .A(n6406), .B(n5399), .S0(n5271), .Y(n1399) );
MXI2X1TS U5876 ( .A(n5499), .B(n5405), .S0(busy), .Y(n1354) );
MXI2X1TS U5877 ( .A(n5497), .B(n5403), .S0(busy), .Y(n1344) );
MXI2X1TS U5878 ( .A(n5214), .B(n5402), .S0(n2383), .Y(n1339) );
MXI2X1TS U5879 ( .A(n5501), .B(n5407), .S0(n2383), .Y(n1364) );
MXI2X1TS U5880 ( .A(n5500), .B(n5406), .S0(n2383), .Y(n1359) );
MXI2X1TS U5881 ( .A(n5498), .B(n5404), .S0(n2383), .Y(n1349) );
NAND2X1TS U5882 ( .A(n5243), .B(final_result_ieee[17]), .Y(n6429) );
NAND2X1TS U5883 ( .A(n5243), .B(final_result_ieee[36]), .Y(n6453) );
NAND2X1TS U5884 ( .A(n5243), .B(final_result_ieee[35]), .Y(n6450) );
NAND2X1TS U5885 ( .A(n5243), .B(final_result_ieee[34]), .Y(n6447) );
NAND2X1TS U5886 ( .A(n5243), .B(final_result_ieee[33]), .Y(n6444) );
NAND2X1TS U5887 ( .A(n5243), .B(final_result_ieee[15]), .Y(n6424) );
NAND2X1TS U5888 ( .A(n5243), .B(final_result_ieee[16]), .Y(n6427) );
NOR2X1TS U5889 ( .A(n6405), .B(DMP_SFG[12]), .Y(n5192) );
MXI2X1TS U5890 ( .A(n5192), .B(n5570), .S0(n5319), .Y(n1142) );
MXI2X1TS U5891 ( .A(n5404), .B(n5555), .S0(n5194), .Y(n1350) );
MXI2X1TS U5892 ( .A(n5403), .B(n5554), .S0(n5194), .Y(n1345) );
INVX2TS U5893 ( .A(DMP_EXP_EWSW[53]), .Y(n5193) );
MXI2X1TS U5894 ( .A(n5406), .B(n5193), .S0(n5194), .Y(n1360) );
MXI2X1TS U5895 ( .A(n5407), .B(n5557), .S0(n5194), .Y(n1365) );
MXI2X1TS U5896 ( .A(n5405), .B(n5556), .S0(n5194), .Y(n1355) );
MXI2X1TS U5897 ( .A(n5402), .B(n5553), .S0(n5194), .Y(n1340) );
CLKMX2X2TS U5898 ( .A(DMP_SHT2_EWSW[4]), .B(DMP_SHT1_EWSW[4]), .S0(busy),
.Y(n1508) );
CLKMX2X2TS U5899 ( .A(OP_FLAG_SHT2), .B(OP_FLAG_SHT1), .S0(busy), .Y(n1191)
);
CLKMX2X2TS U5900 ( .A(DMP_SHT2_EWSW[13]), .B(DMP_SHT1_EWSW[13]), .S0(busy),
.Y(n1481) );
CLKMX2X2TS U5901 ( .A(DMP_SHT2_EWSW[61]), .B(DMP_SHT1_EWSW[61]), .S0(busy),
.Y(n1319) );
CLKMX2X2TS U5902 ( .A(DMP_SHT2_EWSW[8]), .B(DMP_SHT1_EWSW[8]), .S0(busy),
.Y(n1496) );
CLKMX2X2TS U5903 ( .A(DMP_SHT2_EWSW[58]), .B(DMP_SHT1_EWSW[58]), .S0(busy),
.Y(n1334) );
CLKMX2X2TS U5904 ( .A(DMP_SHT2_EWSW[60]), .B(DMP_SHT1_EWSW[60]), .S0(busy),
.Y(n1324) );
CLKMX2X2TS U5905 ( .A(DMP_SHT2_EWSW[59]), .B(DMP_SHT1_EWSW[59]), .S0(busy),
.Y(n1329) );
CLKMX2X2TS U5906 ( .A(DMP_SHT1_EWSW[7]), .B(DMP_EXP_EWSW[7]), .S0(n5209),
.Y(n1500) );
CLKMX2X2TS U5907 ( .A(DMP_SHT1_EWSW[12]), .B(DMP_EXP_EWSW[12]), .S0(n5210),
.Y(n1485) );
CLKMX2X2TS U5908 ( .A(DMP_SHT1_EWSW[4]), .B(DMP_EXP_EWSW[4]), .S0(n5209),
.Y(n1509) );
CLKMX2X2TS U5909 ( .A(DMP_SHT1_EWSW[1]), .B(DMP_EXP_EWSW[1]), .S0(n5209),
.Y(n1518) );
CLKMX2X2TS U5910 ( .A(DMP_SHT1_EWSW[6]), .B(DMP_EXP_EWSW[6]), .S0(n5210),
.Y(n1503) );
CLKMX2X2TS U5911 ( .A(DMP_SHT1_EWSW[11]), .B(DMP_EXP_EWSW[11]), .S0(n5209),
.Y(n1488) );
CLKMX2X2TS U5912 ( .A(DMP_SHT1_EWSW[2]), .B(n2276), .S0(n5210), .Y(n1515) );
CLKMX2X2TS U5913 ( .A(DMP_SHT1_EWSW[62]), .B(DMP_EXP_EWSW[62]), .S0(n5194),
.Y(n1315) );
CLKMX2X2TS U5914 ( .A(DMP_SHT1_EWSW[14]), .B(DMP_EXP_EWSW[14]), .S0(n5194),
.Y(n1479) );
CLKMX2X2TS U5915 ( .A(SIGN_FLAG_SHT1), .B(SIGN_FLAG_EXP), .S0(n5194), .Y(
n1189) );
CLKMX2X2TS U5916 ( .A(DMP_SHT1_EWSW[16]), .B(DMP_EXP_EWSW[16]), .S0(n5194),
.Y(n1473) );
CLKMX2X2TS U5917 ( .A(DMP_SHT1_EWSW[61]), .B(DMP_EXP_EWSW[61]), .S0(n2546),
.Y(n1320) );
CLKMX2X2TS U5918 ( .A(OP_FLAG_SHT1), .B(OP_FLAG_EXP), .S0(n2546), .Y(n1192)
);
CLKMX2X2TS U5919 ( .A(DMP_SHT1_EWSW[59]), .B(DMP_EXP_EWSW[59]), .S0(n2546),
.Y(n1330) );
CLKMX2X2TS U5920 ( .A(DMP_SHT1_EWSW[13]), .B(DMP_EXP_EWSW[13]), .S0(n2546),
.Y(n1482) );
CLKMX2X2TS U5921 ( .A(DMP_SHT1_EWSW[8]), .B(DMP_EXP_EWSW[8]), .S0(n2546),
.Y(n1497) );
CLKMX2X2TS U5922 ( .A(DMP_SHT1_EWSW[60]), .B(n2303), .S0(n2546), .Y(n1325)
);
CLKMX2X2TS U5923 ( .A(DMP_SHT1_EWSW[58]), .B(DMP_EXP_EWSW[58]), .S0(n2546),
.Y(n1335) );
CLKMX2X2TS U5924 ( .A(DMP_SHT2_EWSW[43]), .B(DMP_SHT1_EWSW[43]), .S0(n5195),
.Y(n1391) );
CLKMX2X2TS U5925 ( .A(DMP_SHT2_EWSW[1]), .B(DMP_SHT1_EWSW[1]), .S0(n5196),
.Y(n1517) );
CLKMX2X2TS U5926 ( .A(DMP_SHT2_EWSW[11]), .B(DMP_SHT1_EWSW[11]), .S0(n5196),
.Y(n1487) );
CLKMX2X2TS U5927 ( .A(DMP_SHT2_EWSW[46]), .B(DMP_SHT1_EWSW[46]), .S0(n5195),
.Y(n1382) );
CLKMX2X2TS U5928 ( .A(DMP_SHT2_EWSW[51]), .B(DMP_SHT1_EWSW[51]), .S0(n5195),
.Y(n1367) );
CLKMX2X2TS U5929 ( .A(DMP_SHT2_EWSW[45]), .B(DMP_SHT1_EWSW[45]), .S0(n5195),
.Y(n1385) );
CLKMX2X2TS U5930 ( .A(DMP_SHT2_EWSW[5]), .B(DMP_SHT1_EWSW[5]), .S0(n5196),
.Y(n1505) );
CLKMX2X2TS U5931 ( .A(DMP_SHT2_EWSW[48]), .B(DMP_SHT1_EWSW[48]), .S0(n5195),
.Y(n1376) );
CLKMX2X2TS U5932 ( .A(DMP_SHT2_EWSW[12]), .B(DMP_SHT1_EWSW[12]), .S0(n5196),
.Y(n1484) );
CLKMX2X2TS U5933 ( .A(DMP_SHT2_EWSW[3]), .B(DMP_SHT1_EWSW[3]), .S0(n5195),
.Y(n1511) );
CLKMX2X2TS U5934 ( .A(DMP_SHT2_EWSW[0]), .B(DMP_SHT1_EWSW[0]), .S0(n5196),
.Y(n1520) );
CLKMX2X2TS U5935 ( .A(DMP_SHT2_EWSW[44]), .B(DMP_SHT1_EWSW[44]), .S0(n5195),
.Y(n1388) );
CLKMX2X2TS U5936 ( .A(DMP_SHT2_EWSW[49]), .B(DMP_SHT1_EWSW[49]), .S0(n5195),
.Y(n1373) );
CLKMX2X2TS U5937 ( .A(DMP_SHT2_EWSW[50]), .B(DMP_SHT1_EWSW[50]), .S0(n5195),
.Y(n1370) );
CLKMX2X2TS U5938 ( .A(DMP_SHT2_EWSW[2]), .B(DMP_SHT1_EWSW[2]), .S0(n5196),
.Y(n1514) );
CLKMX2X2TS U5939 ( .A(DMP_SHT2_EWSW[6]), .B(DMP_SHT1_EWSW[6]), .S0(n5196),
.Y(n1502) );
CLKMX2X2TS U5940 ( .A(DMP_SHT2_EWSW[47]), .B(DMP_SHT1_EWSW[47]), .S0(n5195),
.Y(n1379) );
CLKMX2X2TS U5941 ( .A(DMP_SHT2_EWSW[9]), .B(DMP_SHT1_EWSW[9]), .S0(n5196),
.Y(n1493) );
CLKMX2X2TS U5942 ( .A(DMP_SHT2_EWSW[10]), .B(DMP_SHT1_EWSW[10]), .S0(n5196),
.Y(n1490) );
CLKMX2X2TS U5943 ( .A(DMP_SHT2_EWSW[7]), .B(DMP_SHT1_EWSW[7]), .S0(n5196),
.Y(n1499) );
BUFX8TS U5944 ( .A(n5493), .Y(n5284) );
CLKMX2X2TS U5945 ( .A(DMP_SHT2_EWSW[37]), .B(DMP_SHT1_EWSW[37]), .S0(n5197),
.Y(n1409) );
CLKMX2X2TS U5946 ( .A(SIGN_FLAG_SHT2), .B(SIGN_FLAG_SHT1), .S0(n5199), .Y(
n1188) );
CLKMX2X2TS U5947 ( .A(DMP_SHT2_EWSW[36]), .B(DMP_SHT1_EWSW[36]), .S0(n5197),
.Y(n1412) );
CLKMX2X2TS U5948 ( .A(DMP_SHT2_EWSW[30]), .B(DMP_SHT1_EWSW[30]), .S0(n5198),
.Y(n1430) );
CLKMX2X2TS U5949 ( .A(DMP_SHT2_EWSW[31]), .B(DMP_SHT1_EWSW[31]), .S0(n5198),
.Y(n1427) );
CLKMX2X2TS U5950 ( .A(DMP_SHT2_EWSW[25]), .B(DMP_SHT1_EWSW[25]), .S0(n5198),
.Y(n1445) );
CLKMX2X2TS U5951 ( .A(DMP_SHT2_EWSW[34]), .B(DMP_SHT1_EWSW[34]), .S0(n5197),
.Y(n1418) );
CLKMX2X2TS U5952 ( .A(DMP_SHT2_EWSW[41]), .B(DMP_SHT1_EWSW[41]), .S0(n5197),
.Y(n1397) );
CLKMX2X2TS U5953 ( .A(DMP_SHT2_EWSW[26]), .B(DMP_SHT1_EWSW[26]), .S0(n5198),
.Y(n1442) );
CLKMX2X2TS U5954 ( .A(DMP_SHT2_EWSW[33]), .B(DMP_SHT1_EWSW[33]), .S0(n5198),
.Y(n1421) );
CLKMX2X2TS U5955 ( .A(DMP_SHT2_EWSW[42]), .B(DMP_SHT1_EWSW[42]), .S0(n5197),
.Y(n1394) );
CLKMX2X2TS U5956 ( .A(DMP_SHT2_EWSW[32]), .B(DMP_SHT1_EWSW[32]), .S0(n5198),
.Y(n1424) );
CLKMX2X2TS U5957 ( .A(DMP_SHT2_EWSW[40]), .B(DMP_SHT1_EWSW[40]), .S0(n5197),
.Y(n1400) );
CLKMX2X2TS U5958 ( .A(DMP_SHT2_EWSW[39]), .B(DMP_SHT1_EWSW[39]), .S0(n5197),
.Y(n1403) );
CLKMX2X2TS U5959 ( .A(DMP_SHT2_EWSW[35]), .B(DMP_SHT1_EWSW[35]), .S0(n5197),
.Y(n1415) );
CLKMX2X2TS U5960 ( .A(DMP_SHT2_EWSW[24]), .B(DMP_SHT1_EWSW[24]), .S0(n5198),
.Y(n1448) );
CLKMX2X2TS U5961 ( .A(DMP_SHT2_EWSW[28]), .B(DMP_SHT1_EWSW[28]), .S0(n5198),
.Y(n1436) );
CLKMX2X2TS U5962 ( .A(DMP_SHT2_EWSW[27]), .B(DMP_SHT1_EWSW[27]), .S0(n5197),
.Y(n1439) );
CLKMX2X2TS U5963 ( .A(DMP_SHT2_EWSW[38]), .B(DMP_SHT1_EWSW[38]), .S0(n5197),
.Y(n1406) );
CLKMX2X2TS U5964 ( .A(ZERO_FLAG_SHT2), .B(ZERO_FLAG_SHT1), .S0(n5199), .Y(
n1197) );
CLKMX2X2TS U5965 ( .A(DMP_SHT2_EWSW[29]), .B(DMP_SHT1_EWSW[29]), .S0(n5198),
.Y(n1433) );
CLKMX2X2TS U5966 ( .A(DMP_SHT2_EWSW[20]), .B(DMP_SHT1_EWSW[20]), .S0(n5199),
.Y(n1460) );
CLKMX2X2TS U5967 ( .A(DMP_SHT2_EWSW[19]), .B(DMP_SHT1_EWSW[19]), .S0(n5199),
.Y(n1463) );
CLKMX2X2TS U5968 ( .A(DMP_SHT2_EWSW[16]), .B(DMP_SHT1_EWSW[16]), .S0(n5199),
.Y(n1472) );
CLKMX2X2TS U5969 ( .A(DMP_SHT2_EWSW[15]), .B(DMP_SHT1_EWSW[15]), .S0(n5199),
.Y(n1475) );
CLKMX2X2TS U5970 ( .A(DMP_SHT2_EWSW[23]), .B(DMP_SHT1_EWSW[23]), .S0(n5198),
.Y(n1451) );
CLKMX2X2TS U5971 ( .A(DMP_SHT2_EWSW[22]), .B(DMP_SHT1_EWSW[22]), .S0(n5199),
.Y(n1454) );
CLKMX2X2TS U5972 ( .A(DMP_SHT2_EWSW[18]), .B(DMP_SHT1_EWSW[18]), .S0(n5199),
.Y(n1466) );
CLKMX2X2TS U5973 ( .A(DMP_SHT2_EWSW[21]), .B(DMP_SHT1_EWSW[21]), .S0(n5199),
.Y(n1457) );
CLKMX2X2TS U5974 ( .A(DMP_SHT2_EWSW[17]), .B(DMP_SHT1_EWSW[17]), .S0(n5199),
.Y(n1469) );
CLKMX2X2TS U5975 ( .A(DmP_mant_SHT1_SW[7]), .B(DmP_EXP_EWSW[7]), .S0(n5207),
.Y(n1295) );
CLKMX2X2TS U5976 ( .A(n2548), .B(DmP_EXP_EWSW[4]), .S0(n5207), .Y(n1301) );
CLKMX2X2TS U5977 ( .A(DMP_SHT1_EWSW[40]), .B(n2123), .S0(n5201), .Y(n1401)
);
CLKMX2X2TS U5978 ( .A(DMP_SHT1_EWSW[5]), .B(DMP_EXP_EWSW[5]), .S0(n5211),
.Y(n1506) );
CLKMX2X2TS U5979 ( .A(DMP_SHT1_EWSW[39]), .B(DMP_EXP_EWSW[39]), .S0(n5201),
.Y(n1404) );
CLKMX2X2TS U5980 ( .A(DMP_SHT1_EWSW[51]), .B(DMP_EXP_EWSW[51]), .S0(n5206),
.Y(n1368) );
CLKMX2X2TS U5981 ( .A(DMP_SHT1_EWSW[48]), .B(DMP_EXP_EWSW[48]), .S0(n5206),
.Y(n1377) );
CLKMX2X2TS U5982 ( .A(DMP_SHT1_EWSW[37]), .B(DMP_EXP_EWSW[37]), .S0(n5201),
.Y(n1410) );
CLKMX2X2TS U5983 ( .A(DMP_SHT1_EWSW[9]), .B(DMP_EXP_EWSW[9]), .S0(n5211),
.Y(n1494) );
CLKMX2X2TS U5984 ( .A(DmP_mant_SHT1_SW[1]), .B(DmP_EXP_EWSW[1]), .S0(n5207),
.Y(n1307) );
CLKMX2X2TS U5985 ( .A(DMP_SHT1_EWSW[0]), .B(DMP_EXP_EWSW[0]), .S0(n5211),
.Y(n1521) );
CLKMX2X2TS U5986 ( .A(DMP_SHT1_EWSW[42]), .B(DMP_EXP_EWSW[42]), .S0(n5201),
.Y(n1395) );
CLKMX2X2TS U5987 ( .A(DmP_mant_SHT1_SW[0]), .B(DmP_EXP_EWSW[0]), .S0(n5207),
.Y(n1309) );
CLKMX2X2TS U5988 ( .A(DMP_SHT1_EWSW[3]), .B(DMP_EXP_EWSW[3]), .S0(n5206),
.Y(n1512) );
CLKMX2X2TS U5989 ( .A(DmP_mant_SHT1_SW[28]), .B(DmP_EXP_EWSW[28]), .S0(n5204), .Y(n1253) );
CLKMX2X2TS U5990 ( .A(DMP_SHT1_EWSW[36]), .B(DMP_EXP_EWSW[36]), .S0(n5201),
.Y(n1413) );
CLKMX2X2TS U5991 ( .A(DMP_SHT1_EWSW[47]), .B(DMP_EXP_EWSW[47]), .S0(n5206),
.Y(n1380) );
CLKMX2X2TS U5992 ( .A(DMP_SHT1_EWSW[50]), .B(n1537), .S0(n5206), .Y(n1371)
);
CLKMX2X2TS U5993 ( .A(DMP_SHT1_EWSW[43]), .B(n2122), .S0(n5201), .Y(n1392)
);
CLKMX2X2TS U5994 ( .A(DMP_SHT1_EWSW[49]), .B(DMP_EXP_EWSW[49]), .S0(n5206),
.Y(n1374) );
CLKMX2X2TS U5995 ( .A(DMP_SHT1_EWSW[44]), .B(DMP_EXP_EWSW[44]), .S0(n5201),
.Y(n1389) );
CLKMX2X2TS U5996 ( .A(DMP_SHT1_EWSW[38]), .B(n1549), .S0(n5201), .Y(n1407)
);
CLKMX2X2TS U5997 ( .A(DMP_SHT1_EWSW[41]), .B(DMP_EXP_EWSW[41]), .S0(n5201),
.Y(n1398) );
CLKMX2X2TS U5998 ( .A(DMP_SHT1_EWSW[10]), .B(DMP_EXP_EWSW[10]), .S0(n5211),
.Y(n1491) );
CLKMX2X2TS U5999 ( .A(DMP_SHT1_EWSW[45]), .B(DMP_EXP_EWSW[45]), .S0(n5201),
.Y(n1386) );
CLKMX2X2TS U6000 ( .A(DMP_SHT1_EWSW[46]), .B(DMP_EXP_EWSW[46]), .S0(n5206),
.Y(n1383) );
CLKMX2X2TS U6001 ( .A(ZERO_FLAG_SHT1), .B(ZERO_FLAG_EXP), .S0(n5213), .Y(
n1198) );
CLKMX2X2TS U6002 ( .A(DMP_SHT1_EWSW[18]), .B(DMP_EXP_EWSW[18]), .S0(n5202),
.Y(n1467) );
CLKMX2X2TS U6003 ( .A(DMP_SHT1_EWSW[23]), .B(DMP_EXP_EWSW[23]), .S0(n5202),
.Y(n1452) );
CLKMX2X2TS U6004 ( .A(DMP_SHT1_EWSW[33]), .B(DMP_EXP_EWSW[33]), .S0(n5203),
.Y(n1422) );
CLKMX2X2TS U6005 ( .A(DMP_SHT1_EWSW[26]), .B(DMP_EXP_EWSW[26]), .S0(n5203),
.Y(n1443) );
CLKMX2X2TS U6006 ( .A(DMP_SHT1_EWSW[28]), .B(DMP_EXP_EWSW[28]), .S0(n5203),
.Y(n1437) );
CLKMX2X2TS U6007 ( .A(DMP_SHT1_EWSW[22]), .B(DMP_EXP_EWSW[22]), .S0(n5202),
.Y(n1455) );
CLKMX2X2TS U6008 ( .A(DMP_SHT1_EWSW[19]), .B(n2259), .S0(n5202), .Y(n1464)
);
CLKMX2X2TS U6009 ( .A(DMP_SHT1_EWSW[24]), .B(DMP_EXP_EWSW[24]), .S0(n5202),
.Y(n1449) );
CLKMX2X2TS U6010 ( .A(DMP_SHT1_EWSW[17]), .B(DMP_EXP_EWSW[17]), .S0(n5202),
.Y(n1470) );
CLKMX2X2TS U6011 ( .A(DMP_SHT1_EWSW[15]), .B(DMP_EXP_EWSW[15]), .S0(n5202),
.Y(n1476) );
CLKMX2X2TS U6012 ( .A(DMP_SHT1_EWSW[21]), .B(n2255), .S0(n5202), .Y(n1458)
);
CLKMX2X2TS U6013 ( .A(DMP_SHT1_EWSW[20]), .B(DMP_EXP_EWSW[20]), .S0(n5202),
.Y(n1461) );
CLKMX2X2TS U6014 ( .A(DMP_SHT1_EWSW[35]), .B(DMP_EXP_EWSW[35]), .S0(n5203),
.Y(n1416) );
CLKMX2X2TS U6015 ( .A(DMP_SHT1_EWSW[25]), .B(DMP_EXP_EWSW[25]), .S0(n5202),
.Y(n1446) );
CLKMX2X2TS U6016 ( .A(DMP_SHT1_EWSW[32]), .B(DMP_EXP_EWSW[32]), .S0(n5203),
.Y(n1425) );
CLKMX2X2TS U6017 ( .A(DMP_SHT1_EWSW[27]), .B(DMP_EXP_EWSW[27]), .S0(n5203),
.Y(n1440) );
CLKMX2X2TS U6018 ( .A(DMP_SHT1_EWSW[29]), .B(DMP_EXP_EWSW[29]), .S0(n5203),
.Y(n1434) );
CLKMX2X2TS U6019 ( .A(DMP_SHT1_EWSW[31]), .B(DMP_EXP_EWSW[31]), .S0(n5203),
.Y(n1428) );
CLKMX2X2TS U6020 ( .A(DMP_SHT1_EWSW[30]), .B(DMP_EXP_EWSW[30]), .S0(n5203),
.Y(n1431) );
CLKMX2X2TS U6021 ( .A(DMP_SHT1_EWSW[34]), .B(n1553), .S0(n5203), .Y(n1419)
);
CLKMX2X2TS U6022 ( .A(DmP_mant_SHT1_SW[35]), .B(DmP_EXP_EWSW[35]), .S0(n5204), .Y(n1239) );
CLKMX2X2TS U6023 ( .A(DmP_mant_SHT1_SW[43]), .B(DmP_EXP_EWSW[43]), .S0(n5211), .Y(n1223) );
CLKMX2X2TS U6024 ( .A(DmP_mant_SHT1_SW[44]), .B(DmP_EXP_EWSW[44]), .S0(n5211), .Y(n1221) );
CLKMX2X2TS U6025 ( .A(DmP_mant_SHT1_SW[45]), .B(DmP_EXP_EWSW[45]), .S0(n5204), .Y(n1219) );
CLKMX2X2TS U6026 ( .A(DmP_mant_SHT1_SW[42]), .B(DmP_EXP_EWSW[42]), .S0(n5211), .Y(n1225) );
CLKMX2X2TS U6027 ( .A(DmP_mant_SHT1_SW[33]), .B(DmP_EXP_EWSW[33]), .S0(n5210), .Y(n1243) );
CLKMX2X2TS U6028 ( .A(DmP_mant_SHT1_SW[40]), .B(DmP_EXP_EWSW[40]), .S0(n5211), .Y(n1229) );
CLKMX2X2TS U6029 ( .A(DmP_mant_SHT1_SW[15]), .B(DmP_EXP_EWSW[15]), .S0(n5213), .Y(n1279) );
CLKMX2X2TS U6030 ( .A(DmP_mant_SHT1_SW[23]), .B(DmP_EXP_EWSW[23]), .S0(n5210), .Y(n1263) );
CLKMX2X2TS U6031 ( .A(DmP_mant_SHT1_SW[30]), .B(DmP_EXP_EWSW[30]), .S0(n5204), .Y(n1249) );
CLKMX2X2TS U6032 ( .A(n2572), .B(DmP_EXP_EWSW[5]), .S0(n5213), .Y(n1299) );
CLKMX2X2TS U6033 ( .A(zero_flag), .B(ZERO_FLAG_SHT1SHT2), .S0(n5289), .Y(
n1193) );
CLKMX2X2TS U6034 ( .A(DmP_mant_SHT1_SW[16]), .B(DmP_EXP_EWSW[16]), .S0(n5213), .Y(n1277) );
CLKMX2X2TS U6035 ( .A(DmP_mant_SHT1_SW[9]), .B(DmP_EXP_EWSW[9]), .S0(n5207),
.Y(n1291) );
CLKMX2X2TS U6036 ( .A(DmP_mant_SHT1_SW[25]), .B(DmP_EXP_EWSW[25]), .S0(n5210), .Y(n1259) );
CLKMX2X2TS U6037 ( .A(DmP_mant_SHT1_SW[38]), .B(DmP_EXP_EWSW[38]), .S0(n5213), .Y(n1233) );
CLKMX2X2TS U6038 ( .A(DmP_mant_SHT1_SW[17]), .B(DmP_EXP_EWSW[17]), .S0(n5209), .Y(n1275) );
CLKMX2X2TS U6039 ( .A(DmP_mant_SHT1_SW[13]), .B(DmP_EXP_EWSW[13]), .S0(n5207), .Y(n1283) );
CLKMX2X2TS U6040 ( .A(DmP_mant_SHT1_SW[48]), .B(DmP_EXP_EWSW[48]), .S0(n5213), .Y(n1213) );
CLKMX2X2TS U6041 ( .A(DmP_mant_SHT1_SW[11]), .B(n1864), .S0(n5206), .Y(n1287) );
CLKMX2X2TS U6042 ( .A(DMP_exp_NRM_EW[4]), .B(DMP_SFG[56]), .S0(n3179), .Y(
n1342) );
CLKMX2X2TS U6043 ( .A(SIGN_FLAG_NRM), .B(SIGN_FLAG_SFG), .S0(n3179), .Y(
n1186) );
CLKMX2X2TS U6044 ( .A(DMP_exp_NRM_EW[6]), .B(DMP_SFG[58]), .S0(n3179), .Y(
n1332) );
CLKMX2X2TS U6045 ( .A(DMP_exp_NRM_EW[7]), .B(DMP_SFG[59]), .S0(n3179), .Y(
n1327) );
CLKMX2X2TS U6046 ( .A(DMP_exp_NRM_EW[8]), .B(DMP_SFG[60]), .S0(n3179), .Y(
n1322) );
CLKMX2X2TS U6047 ( .A(DMP_exp_NRM_EW[10]), .B(DMP_SFG[62]), .S0(n3179), .Y(
n1312) );
CLKMX2X2TS U6048 ( .A(DMP_exp_NRM_EW[9]), .B(DMP_SFG[61]), .S0(n3179), .Y(
n1317) );
CLKMX2X2TS U6049 ( .A(DmP_mant_SHT1_SW[14]), .B(n2313), .S0(n5207), .Y(n1281) );
CLKMX2X2TS U6050 ( .A(DmP_mant_SHT1_SW[12]), .B(DmP_EXP_EWSW[12]), .S0(n5206), .Y(n1285) );
CLKMX2X2TS U6051 ( .A(DmP_mant_SHT1_SW[10]), .B(DmP_EXP_EWSW[10]), .S0(n5207), .Y(n1289) );
CLKMX2X2TS U6052 ( .A(DmP_mant_SHT1_SW[32]), .B(DmP_EXP_EWSW[32]), .S0(n5210), .Y(n1245) );
CLKMX2X2TS U6053 ( .A(DmP_mant_SHT1_SW[39]), .B(DmP_EXP_EWSW[39]), .S0(n5211), .Y(n1231) );
CLKMX2X2TS U6054 ( .A(DMP_exp_NRM_EW[5]), .B(DMP_SFG[57]), .S0(n5208), .Y(
n1337) );
CLKMX2X2TS U6055 ( .A(DMP_exp_NRM_EW[2]), .B(DMP_SFG[54]), .S0(n5208), .Y(
n1352) );
CLKMX2X2TS U6056 ( .A(DMP_exp_NRM_EW[3]), .B(DMP_SFG[55]), .S0(n5208), .Y(
n1347) );
CLKMX2X2TS U6057 ( .A(DMP_exp_NRM_EW[0]), .B(DMP_SFG[52]), .S0(n5208), .Y(
n1362) );
CLKMX2X2TS U6058 ( .A(DMP_exp_NRM_EW[1]), .B(DMP_SFG[53]), .S0(n5208), .Y(
n1357) );
CLKMX2X2TS U6059 ( .A(DmP_mant_SHT1_SW[50]), .B(DmP_EXP_EWSW[50]), .S0(n5209), .Y(n1209) );
CLKMX2X2TS U6060 ( .A(DmP_mant_SHT1_SW[6]), .B(DmP_EXP_EWSW[6]), .S0(n5213),
.Y(n1297) );
CLKMX2X2TS U6061 ( .A(DmP_mant_SHT1_SW[19]), .B(DmP_EXP_EWSW[19]), .S0(n5209), .Y(n1271) );
CLKMX2X2TS U6062 ( .A(DmP_mant_SHT1_SW[49]), .B(DmP_EXP_EWSW[49]), .S0(n5209), .Y(n1211) );
CLKMX2X2TS U6063 ( .A(DmP_mant_SHT1_SW[20]), .B(DmP_EXP_EWSW[20]), .S0(n5209), .Y(n1269) );
CLKMX2X2TS U6064 ( .A(DmP_mant_SHT1_SW[22]), .B(DmP_EXP_EWSW[22]), .S0(n5210), .Y(n1265) );
CLKMX2X2TS U6065 ( .A(DmP_mant_SHT1_SW[41]), .B(DmP_EXP_EWSW[41]), .S0(n5211), .Y(n1227) );
MXI2X1TS U6066 ( .A(n5212), .B(inst_FSM_INPUT_ENABLE_state_reg[0]), .S0(
inst_FSM_INPUT_ENABLE_state_reg[1]), .Y(
inst_FSM_INPUT_ENABLE_state_next_1_) );
CLKMX2X2TS U6067 ( .A(DmP_mant_SHT1_SW[3]), .B(DmP_EXP_EWSW[3]), .S0(n5213),
.Y(n1303) );
MXI2X1TS U6068 ( .A(n5214), .B(n5408), .S0(n5191), .Y(n1338) );
INVX2TS U6069 ( .A(DMP_SFG[22]), .Y(n5215) );
MXI2X1TS U6070 ( .A(n5388), .B(n5215), .S0(n5191), .Y(n1453) );
CLKMX2X3TS U6071 ( .A(Data_X[63]), .B(intDX_EWSW[63]), .S0(n5242), .Y(n1731)
);
MXI2X1TS U6072 ( .A(n5383), .B(n5516), .S0(n5216), .Y(n1438) );
MXI2X1TS U6073 ( .A(n5385), .B(n5464), .S0(n5216), .Y(n1444) );
MXI2X1TS U6074 ( .A(n5381), .B(n5484), .S0(n5216), .Y(n1432) );
MXI2X1TS U6075 ( .A(n5387), .B(n5465), .S0(n5224), .Y(n1450) );
MXI2X1TS U6076 ( .A(n5386), .B(n5476), .S0(n5232), .Y(n1447) );
MXI2X1TS U6077 ( .A(n5390), .B(n5461), .S0(n5265), .Y(n1459) );
MXI2X1TS U6078 ( .A(n5395), .B(n5486), .S0(n5265), .Y(n1474) );
MXI2X1TS U6079 ( .A(n5396), .B(n5473), .S0(n5245), .Y(n1477) );
MXI2X1TS U6080 ( .A(n5392), .B(n5477), .S0(n5232), .Y(n1465) );
MXI2X1TS U6081 ( .A(n5389), .B(n5485), .S0(n5271), .Y(n1456) );
MXI2X1TS U6082 ( .A(n5393), .B(n5466), .S0(n5224), .Y(n1468) );
MXI2X1TS U6083 ( .A(n5391), .B(n5517), .S0(n5245), .Y(n1462) );
INVX2TS U6084 ( .A(DMP_SFG[55]), .Y(n5219) );
MXI2X1TS U6085 ( .A(n5498), .B(n5219), .S0(n2505), .Y(n1348) );
MXI2X1TS U6086 ( .A(n5449), .B(n5347), .S0(n5224), .Y(n1507) );
MXI2X1TS U6087 ( .A(n5448), .B(n5346), .S0(n5265), .Y(n1495) );
MXI2X1TS U6088 ( .A(n5452), .B(n5350), .S0(n5232), .Y(n1516) );
MXI2X1TS U6089 ( .A(n5450), .B(n5348), .S0(n5245), .Y(n1498) );
INVX2TS U6090 ( .A(DMP_SFG[58]), .Y(n5220) );
MXI2X1TS U6091 ( .A(n5359), .B(n5220), .S0(n5264), .Y(n1333) );
INVX2TS U6092 ( .A(DMP_SFG[56]), .Y(n5221) );
MXI2X1TS U6093 ( .A(n5497), .B(n5221), .S0(n5264), .Y(n1343) );
INVX2TS U6094 ( .A(DMP_SFG[54]), .Y(n5222) );
MXI2X1TS U6095 ( .A(n5499), .B(n5222), .S0(n2554), .Y(n1353) );
INVX2TS U6096 ( .A(DMP_SFG[52]), .Y(n5223) );
MXI2X1TS U6097 ( .A(n5501), .B(n5223), .S0(n5264), .Y(n1363) );
MXI2X1TS U6098 ( .A(n5360), .B(n5467), .S0(n5271), .Y(n1480) );
MXI2X1TS U6099 ( .A(n5338), .B(n5400), .S0(n5271), .Y(n1402) );
INVX2TS U6100 ( .A(DMP_SFG[62]), .Y(n5225) );
MXI2X1TS U6101 ( .A(n5226), .B(n5225), .S0(n5245), .Y(n1313) );
INVX2TS U6102 ( .A(DMP_SFG[49]), .Y(n5228) );
MXI2X1TS U6103 ( .A(n5459), .B(n5228), .S0(n5265), .Y(n1372) );
INVX2TS U6104 ( .A(DMP_SFG[50]), .Y(n5229) );
MXI2X1TS U6105 ( .A(n5364), .B(n5229), .S0(n5264), .Y(n1369) );
INVX2TS U6106 ( .A(SIGN_FLAG_SFG), .Y(n5230) );
MXI2X1TS U6107 ( .A(n5397), .B(n5230), .S0(n5245), .Y(n1187) );
INVX2TS U6108 ( .A(DMP_SFG[51]), .Y(n5231) );
MXI2X1TS U6109 ( .A(n5363), .B(n5231), .S0(n5245), .Y(n1366) );
MXI2X1TS U6110 ( .A(n6464), .B(n5410), .S0(n5224), .Y(n1196) );
MXI2X1TS U6111 ( .A(n5373), .B(n5514), .S0(n5271), .Y(n1408) );
MXI2X1TS U6112 ( .A(n5372), .B(n5469), .S0(n5232), .Y(n1405) );
MXI2X1TS U6113 ( .A(n5370), .B(n5480), .S0(n5159), .Y(n1390) );
MXI2X1TS U6114 ( .A(n5368), .B(n5479), .S0(n5271), .Y(n1384) );
MXI2X1TS U6115 ( .A(n5366), .B(n5513), .S0(n5159), .Y(n1378) );
MXI2X1TS U6116 ( .A(n5337), .B(n5398), .S0(n5271), .Y(n1396) );
MXI2X1TS U6117 ( .A(n5377), .B(n5481), .S0(n5232), .Y(n1420) );
MXI2X1TS U6118 ( .A(n5365), .B(n5460), .S0(n5159), .Y(n1375) );
MXI2X1TS U6119 ( .A(n5371), .B(n5462), .S0(n5245), .Y(n1393) );
MXI2X1TS U6120 ( .A(n5374), .B(n5463), .S0(n5232), .Y(n1411) );
MXI2X1TS U6121 ( .A(n5375), .B(n5515), .S0(n5232), .Y(n1414) );
MXI2X1TS U6122 ( .A(n5376), .B(n5470), .S0(n5224), .Y(n1417) );
MXI2X1TS U6123 ( .A(n5367), .B(n5468), .S0(n5224), .Y(n1381) );
MXI2X1TS U6124 ( .A(n5378), .B(n5482), .S0(n5159), .Y(n1423) );
MXI2X1TS U6125 ( .A(n5369), .B(n5474), .S0(n5159), .Y(n1387) );
CLKMX2X3TS U6126 ( .A(Data_Y[45]), .B(n2299), .S0(n5235), .Y(n1683) );
CLKMX2X2TS U6127 ( .A(Data_X[43]), .B(intDX_EWSW[43]), .S0(n5239), .Y(n1751)
);
CLKMX2X2TS U6128 ( .A(Data_X[33]), .B(intDX_EWSW[33]), .S0(n5237), .Y(n1761)
);
CLKMX2X2TS U6129 ( .A(Data_X[14]), .B(intDX_EWSW[14]), .S0(n5240), .Y(n1780)
);
MXI2X1TS U6130 ( .A(n5447), .B(n5205), .S0(n5314), .Y(n1797) );
MXI2X1TS U6131 ( .A(n5089), .B(n2384), .S0(n5314), .Y(n1796) );
MXI2X1TS U6132 ( .A(n5244), .B(n5447), .S0(n5314), .Y(n1798) );
MXI2X1TS U6133 ( .A(n5246), .B(n5519), .S0(n5159), .Y(n1043) );
INVX2TS U6134 ( .A(DmP_mant_SFG_SWR[7]), .Y(n5247) );
INVX2TS U6135 ( .A(DmP_mant_SFG_SWR[9]), .Y(n5250) );
CLKMX2X3TS U6136 ( .A(Data_Y[21]), .B(n2479), .S0(n5258), .Y(n1707) );
INVX2TS U6137 ( .A(DmP_mant_SFG_SWR[4]), .Y(n5267) );
INVX2TS U6138 ( .A(DmP_mant_SFG_SWR[5]), .Y(n5269) );
INVX2TS U6139 ( .A(DmP_mant_SFG_SWR[3]), .Y(n5272) );
NAND2X4TS U6140 ( .A(n2404), .B(n5279), .Y(n5280) );
CLKMX2X2TS U6141 ( .A(n5282), .B(Raw_mant_NRM_SWR[15]), .S0(n5319), .Y(n1183) );
MXI2X1TS U6142 ( .A(n2547), .B(n5284), .S0(n5314), .Y(n1799) );
XNOR2X1TS U6143 ( .A(n3329), .B(DMP_EXP_EWSW[52]), .Y(n5285) );
CLKMX2X2TS U6144 ( .A(n5285), .B(Shift_amount_SHT1_EWR[0]), .S0(n2547), .Y(
n1604) );
NAND2X1TS U6145 ( .A(n3032), .B(n5297), .Y(n5295) );
XOR2X1TS U6146 ( .A(n5299), .B(n5295), .Y(n5296) );
INVX2TS U6147 ( .A(n5300), .Y(n5302) );
NAND2X1TS U6148 ( .A(n5302), .B(n5301), .Y(n5303) );
CLKMX2X2TS U6149 ( .A(n5304), .B(n2565), .S0(n2547), .Y(n1601) );
INVX2TS U6150 ( .A(n5305), .Y(n5307) );
NAND2X1TS U6151 ( .A(n5307), .B(n5306), .Y(n5308) );
NAND2X1TS U6152 ( .A(n2443), .B(n5310), .Y(n5312) );
XOR2X1TS U6153 ( .A(n5312), .B(n5311), .Y(n5313) );
CLKMX2X2TS U6154 ( .A(n5313), .B(Shift_amount_SHT1_EWR[1]), .S0(n2547), .Y(
n1603) );
MXI2X1TS U6155 ( .A(n2525), .B(n2547), .S0(n5314), .Y(n1800) );
CLKMX2X2TS U6156 ( .A(n5320), .B(Raw_mant_NRM_SWR[16]), .S0(n5205), .Y(n1182) );
initial $sdf_annotate("FPU_PIPELINED_FPADDSUB_ASIC_fpadd_approx_syn_constraints_clk1.tcl_LOA_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTP_TB_V
`define SKY130_FD_SC_HD__SDFRTP_TB_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfrtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTP_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:29:35 03/29/2015
// Design Name:
// Module Name: regfileparam_behav
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module regfileparam_behav
#(parameter BITSIZE = 16,
parameter ADDSIZE = 4)
(output [BITSIZE-1:0] adat,
output [BITSIZE-1:0] bdat,
output [BITSIZE-1:0] zeroDat,
input [ADDSIZE-1:0] ra, // Read A Address
input [ADDSIZE-1:0] rb, // Read B Address
input [ADDSIZE-1:0] rw, // Write Address
input [BITSIZE-1:0] wdat,
input wren,
input clk, rst
);
integer i;
reg [BITSIZE-1:0] array_reg [2**ADDSIZE-1:0];
always @(posedge clk, negedge rst) begin
if(~rst) begin
for(i = 0; i < 2**ADDSIZE; i = i + 1) begin
array_reg[i] <= 0;
end
end
else if(wren) begin
array_reg[rw] <= wdat;
end
end
// Asynchronous Read
assign adat = array_reg[ra];
assign bdat = array_reg[rb];
assign zeroDat = array_reg[0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3B_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NAND3B_PP_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand3b (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3B_PP_BLACKBOX_V
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE DMA One Channel Register File ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_dma_ch_rf.v,v 1.5 2002-02-01 01:54:45 rudi Exp $
//
// $Date: 2002-02-01 01:54:45 $
// $Revision: 1.5 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.4 2001/10/30 02:06:17 rudi
//
// - Fixed problem where synthesis tools would instantiate latches instead of flip-flops
//
// Revision 1.3 2001/10/19 04:35:04 rudi
//
// - Made the core parameterized
//
// Revision 1.2 2001/08/15 05:40:30 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
// - Added Section 3.10, describing DMA restart.
//
// Revision 1.1 2001/07/29 08:57:02 rudi
//
//
// 1) Changed Directory Structure
// 2) Added restart signal (REST)
//
// Revision 1.3 2001/06/14 08:50:01 rudi
//
// Changed Module Name to match file name.
//
// Revision 1.2 2001/06/13 02:26:48 rudi
//
//
// Small changes after running lint.
//
// Revision 1.1 2001/06/05 10:25:27 rudi
//
//
// Initial checkin of register file for one channel.
//
//
//
//
`include "wb_dma_defines.v"
module wb_dma_ch_rf( clk, rst,
pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, irq,
wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
// DMA Registers Write Back Channel Select
ch_sel, ndnr,
// DMA Engine Status
dma_busy, dma_err, dma_done, dma_done_all,
// DMA Engine Reg File Update ctrl signals
de_csr, de_txsz, de_adr0, de_adr1,
de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
de_fetch_descr, dma_rest,
ptr_set
);
parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID
parameter [0:0] CH_EN = 1'b1; // This channel exists
parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS
parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors
parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers
input clk, rst;
output [31:0] pointer;
output [31:0] pointer_s;
output [31:0] ch_csr;
output [31:0] ch_txsz;
output [31:0] ch_adr0;
output [31:0] ch_adr1;
output [31:0] ch_am0;
output [31:0] ch_am1;
output [31:0] sw_pointer;
output ch_stop;
output ch_dis;
output irq;
input [31:0] wb_rf_din;
input [7:0] wb_rf_adr;
input wb_rf_we;
input wb_rf_re;
input [4:0] ch_sel;
input ndnr;
// DMA Engine Status
input dma_busy, dma_err, dma_done, dma_done_all;
// DMA Engine Reg File Update ctrl signals
input [31:0] de_csr;
input [11:0] de_txsz;
input [31:0] de_adr0;
input [31:0] de_adr1;
input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
input de_fetch_descr;
input dma_rest;
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
wire [31:0] pointer;
reg [27:0] pointer_r;
reg [27:0] pointer_sr;
reg ptr_valid;
reg ch_eol;
wire [31:0] ch_csr, ch_txsz;
reg [8:0] ch_csr_r;
reg [2:0] ch_csr_r2;
reg [2:0] ch_csr_r3;
reg [2:0] int_src_r;
reg ch_err_r;
reg ch_stop;
reg ch_busy;
reg ch_done;
reg ch_err;
reg rest_en;
reg [10:0] ch_chk_sz_r;
reg [11:0] ch_tot_sz_r;
// Transfer-size register
reg [1:0] ch_tr_sz_r;
reg [22:0] ch_txsz_s;
reg ch_sz_inf;
wire [31:0] ch_adr0, ch_adr1;
reg [31:0] ch_adr0_r, ch_adr1_r;
wire [31:0] ch_am0, ch_am1;
reg [27:0] ch_am0_r, ch_am1_r;
reg [31:0] ch_adr0_s, ch_adr1_s;
reg [29:0] sw_pointer_r;
wire sw_pointer_we;
wire [28:0] cmp_adr;
reg ch_dis;
wire ch_enable;
wire pointer_we;
wire ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we;
wire ch_am0_we, ch_am1_we;
reg ch_rl;
wire ch_done_we;
wire ch_err_we;
wire chunk_done_we;
wire ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe;
wire this_ptr_set;
wire ptr_inv;
////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign ch_adr0 = CH_EN ? ch_adr0_r : 32'h0;
assign ch_adr1 = CH_EN ? ch_adr1_r : 32'h0;
assign ch_am0 = (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0} : 32'hffff_fff0;
assign ch_am1 = (CH_EN & HAVE_CBUF) ? {ch_am1_r, 4'h0} : 32'hffff_fff0;
assign sw_pointer = (CH_EN & HAVE_CBUF) ? {sw_pointer_r,2'h0} : 32'h0;
assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;
assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0;
assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;
assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 1'h0, ch_tr_sz_r, ch_tot_sz_r} : 32'h0;
assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0;
////////////////////////////////////////////////////////////////////
//
// CH0 control signals
//
parameter [4:0] CH_ADR = CH_NO + 5'h1;
assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1);
assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2);
assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3);
assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4);
assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);
assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);
assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done;
assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err;
assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO);
assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO);
assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO);
assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO);
assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr;
assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO);
always @(posedge clk)
ch_rl <= #1 CH_EN & HAVE_ARS & (
(rest_en & dma_rest) |
((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
);
// ---------------------------------------------------
// Pointers
always @(posedge clk or negedge rst)
if(!rst) ptr_valid <= #1 1'b0;
else
if(CH_EN & HAVE_ED)
begin
if( this_ptr_set | (rest_en & dma_rest) )
ptr_valid <= #1 1'b1;
else
if(ptr_inv) ptr_valid <= #1 1'b0;
end
else ptr_valid <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) ch_eol <= #1 1'b0;
else
if(CH_EN & HAVE_ED)
begin
if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL];
else
if(ch_done_we) ch_eol <= #1 1'b0;
end
else ch_eol <= #1 1'b0;
always @(posedge clk)
if(CH_EN & HAVE_ED)
begin
if(pointer_we) pointer_r <= #1 wb_rf_din[31:4];
else
if(this_ptr_set) pointer_r <= #1 de_csr[31:4];
end
else pointer_r <= #1 1'b0;
always @(posedge clk)
if(CH_EN & HAVE_ED)
begin
if(this_ptr_set) pointer_sr <= #1 pointer_r;
end
else pointer_sr <= #1 1'b0;
// ---------------------------------------------------
// CSR
always @(posedge clk or negedge rst)
if(!rst) ch_csr_r <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];
else
begin
if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
end
end
// done bit
always @(posedge clk or negedge rst)
if(!rst) ch_done <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
else
if(ch_done_we) ch_done <= #1 1'b1;
end
// busy bit
always @(posedge clk)
ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy;
// stop bit
always @(posedge clk)
ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP];
// error bit
always @(posedge clk or negedge rst)
if(!rst) ch_err <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_err_we) ch_err <= #1 1'b1;
else
if(ch_csr_re) ch_err <= #1 1'b0;
end
// Priority Bits
always @(posedge clk or negedge rst)
if(!rst) ch_csr_r2 <= #1 3'h0;
else
if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13];
// Restart Enable Bit (REST)
always @(posedge clk or negedge rst)
if(!rst) rest_en <= #1 1'b0;
else
if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16];
// irq Mask
always @(posedge clk or negedge rst)
if(!rst) ch_csr_r3 <= #1 3'h0;
else
if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17];
// irq Source
always @(posedge clk or negedge rst)
if(!rst) int_src_r[2] <= #1 1'b0;
else
if(CH_EN)
begin
if(chunk_done_we) int_src_r[2] <= #1 1'b1;
else
if(ch_csr_re) int_src_r[2] <= #1 1'b0;
end
always @(posedge clk or negedge rst)
if(!rst) int_src_r[1] <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_done_we) int_src_r[1] <= #1 1'b1;
else
if(ch_csr_re) int_src_r[1] <= #1 1'b0;
end
always @(posedge clk or negedge rst)
if(!rst) int_src_r[0] <= #1 1'b0;
else
if(CH_EN)
begin
if(ch_err_we) int_src_r[0] <= #1 1'b1;
else
if(ch_csr_re) int_src_r[0] <= #1 1'b0;
end
// Interrupt Output
assign irq = |(int_src_r & ch_csr_r3) & CH_EN;
// ---------------------------------------------------
// TXZS
always @(posedge clk)
if(CH_EN)
begin
if(ch_txsz_we)
{ch_chk_sz_r, ch_tr_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[13:12], wb_rf_din[11:0]};
else
if(ch_txsz_dewe)
ch_tot_sz_r <= #1 de_txsz; // TODO:
else
if(ch_rl)
{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s; // TODO:
end
// txsz shadow register
always @(posedge clk)
if(CH_EN & HAVE_ARS)
begin
if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
else
if(rest_en & ch_txsz_dewe & de_fetch_descr)
ch_txsz_s[11:0] <= #1 de_txsz[11:0];
end
// Infinite Size indicator
always @(posedge clk)
if(CH_EN)
begin
if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];
end
// ---------------------------------------------------
// ADR0
always @(posedge clk)
if(CH_EN)
begin
if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:0];
else
if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:0];
else
if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;
end
// Adr0 shadow register
always @(posedge clk)
if(CH_EN & HAVE_ARS)
begin
if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:0];
else
if(rest_en & ch_adr0_dewe & de_fetch_descr)
ch_adr0_s <= #1 de_adr0[31:0];
end
// ---------------------------------------------------
// AM0
always @(posedge clk or negedge rst)
if(!rst) ch_am0_r <= #1 28'hfffffff;
else
if(ch_am0_we) ch_am0_r <= #1 wb_rf_din[31:4];
// ---------------------------------------------------
// ADR1
always @(posedge clk)
if(CH_EN)
begin
if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:0];
else
if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:0];
else
if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;
end
// Adr1 shadow register
always @(posedge clk)
if(CH_EN & HAVE_ARS)
begin
if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:0];
else
if(rest_en & ch_adr1_dewe & de_fetch_descr)
ch_adr1_s <= #1 de_adr1[31:0];
end
// ---------------------------------------------------
// AM1
always @(posedge clk or negedge rst)
if(!rst) ch_am1_r <= #1 28'hfffffff;
else
if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4];
// ---------------------------------------------------
// Software Pointer
always @(posedge clk or negedge rst)
if(!rst) sw_pointer_r <= #1 28'h0;
else
if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4];
// ---------------------------------------------------
// Software Pointer Match logic
assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];
always @(posedge clk)
ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31];
endmodule
module wb_dma_ch_rf_dummy(clk, rst,
pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, irq,
wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
// DMA Registers Write Back Channel Select
ch_sel, ndnr,
// DMA Engine Status
dma_busy, dma_err, dma_done, dma_done_all,
// DMA Engine Reg File Update ctrl signals
de_csr, de_txsz, de_adr0, de_adr1,
de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
de_fetch_descr, dma_rest,
ptr_set
);
parameter CH_NO = 0;
parameter HAVE_ARS = 1;
parameter HAVE_ED = 1;
parameter HAVE_CBUF= 1;
input clk, rst;
output [31:0] pointer;
output [31:0] pointer_s;
output [31:0] ch_csr;
output [31:0] ch_txsz;
output [31:0] ch_adr0;
output [31:0] ch_adr1;
output [31:0] ch_am0;
output [31:0] ch_am1;
output [31:0] sw_pointer;
output ch_stop;
output ch_dis;
output irq;
input [31:0] wb_rf_din;
input [7:0] wb_rf_adr;
input wb_rf_we;
input wb_rf_re;
input [4:0] ch_sel;
input ndnr;
// DMA Engine Status
input dma_busy, dma_err, dma_done, dma_done_all;
// DMA Engine Reg File Update ctrl signals
input [31:0] de_csr;
input [11:0] de_txsz;
input [31:0] de_adr0;
input [31:0] de_adr1;
input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
input de_fetch_descr;
input dma_rest;
assign pointer = 32'h0;
assign pointer_s = 32'h0;
assign ch_csr = 32'h0;
assign ch_txsz = 32'h0;
assign ch_adr0 = 32'h0;
assign ch_adr1 = 32'h0;
assign ch_am0 = 32'h0;
assign ch_am1 = 32'h0;
assign sw_pointer = 32'h0;
assign ch_stop = 1'b0;
assign ch_dis = 1'b0;
assign irq = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DFBBP_PP_SYMBOL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBP_PP_SYMBOL_V
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_system.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module pll_system (
inclk0,
c1,
c4,
locked);
input inclk0;
output c1;
output c4;
output locked;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "5"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "40.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_system.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_system.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_system.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_system.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_system.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_system.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_system_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_system_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
ROM_form.v
Production template for a 0.25K program (256 instructions) for KCPSM6 in a Spartan-6,
Virtex-6 or 7-Series device using 18 Slices.
Nick Sawyer (Xilinx Ltd)
Ken Chapman (Xilinx Ltd)
14th March 2013 - First Release
This is a verilog template file for the KCPSM6 assembler.
This verilog file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.v' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the verilog.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
//
///////////////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010-2013, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
///////////////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////////////////
//
//
// Production definition of a 0.25K program (256 instructions) for KCPSM6 in a Spartan-6,
// Virtex-6 or 7-Series device using 18 Slices.
//
// Note: The full 12-bit KCPSM6 address is connected but only the lower 8-bits will be
// employed. Likewise the 'bram_enable' should still be connected to 'enable'.
// This minimises the changes required to the hardware description of a design
// when moving between different memory types and selecting different sizes.
//
//
// Program defined by '{psmname}.psm'.
//
// Generated by KCPSM6 Assembler: {timestamp}.
//
// Assembler used ROM_form template: ROM_form_128_14March13.v
//
//
`timescale 1ps/1ps
//
//
module {name} (
input [11:0] address,
output [17:0] instruction,
input enable,
input clk );
//
//
wire [17:0] rom_value;
//
//
genvar i;
generate
for (i = 0; i <= 17; i = i+1)
begin : instruction_bit
//
FDRE kcpsm6_rom_flop ( .D (rom_value[i]),
.Q (instruction[i]),
.CE (enable),
.R (address[7+(i/4)]),
.C (clk));
end
endgenerate
//
//
ROM128X1
#( .INIT (256'h{INIT128_0}))
kcpsm6_rom0( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[0]));
//
ROM128X1
#( .INIT (256'h{INIT128_1}))
kcpsm6_rom1( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[1]));
//
ROM128X1
#( .INIT (256'h{INIT128_2}))
kcpsm6_rom2( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[2]));
//
ROM128X1
#( .INIT (256'h{INIT128_3}))
kcpsm6_rom3( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[3]));
//
ROM128X1
#( .INIT (256'h{INIT128_4}))
kcpsm6_rom4( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[4]));
//
ROM128X1
#( .INIT (256'h{INIT128_5}))
kcpsm6_rom5( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[5]));
//
ROM128X1
#( .INIT (256'h{INIT128_6}))
kcpsm6_rom6( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[6]));
//
ROM128X1
#( .INIT (256'h{INIT128_7}))
kcpsm6_rom7( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[7]));
//
ROM128X1
#( .INIT (256'h{INIT128_8}))
kcpsm6_rom8( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[8]));
//
ROM128X1
#( .INIT (256'h{INIT128_9}))
kcpsm6_rom9( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[9]));
//
ROM128X1
#( .INIT (256'h{INIT128_10}))
kcpsm6_rom10( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[10]));
//
ROM128X1
#( .INIT (256'h{INIT128_11}))
kcpsm6_rom11( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[11]));
//
ROM128X1
#( .INIT (256'h{INIT128_12}))
kcpsm6_rom12( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[12]));
//
ROM128X1
#( .INIT (256'h{INIT128_13}))
kcpsm6_rom13( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[13]));
//
ROM128X1
#( .INIT (256'h{INIT128_14}))
kcpsm6_rom14( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[14]));
//
ROM128X1
#( .INIT (256'h{INIT128_15}))
kcpsm6_rom15( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[15]));
//
ROM128X1
#( .INIT (256'h{INIT128_16}))
kcpsm6_rom16( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[16]));
//
ROM128X1
#( .INIT (256'h{INIT128_17}))
kcpsm6_rom17( .A0 (address[0]),
.A1 (address[1]),
.A2 (address[2]),
.A3 (address[3]),
.A4 (address[4]),
.A5 (address[5]),
.A6 (address[6]),
.O (rom_value[17]));
//
//
endmodule
//
////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE {name}.v
//
////////////////////////////////////////////////////////////////////////////////////
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
module offset_to_mask
#(parameter C_MASK_SWAP = 1,
parameter C_MASK_WIDTH = 4)
(
input OFFSET_ENABLE,
input [clog2s(C_MASK_WIDTH)-1:0] OFFSET,
output [C_MASK_WIDTH-1:0] MASK
);
`include "functions.vh"
reg [7:0] _rMask,_rMaskSwap;
wire [3:0] wSelect;
assign wSelect = {OFFSET_ENABLE,{{(3-clog2s(C_MASK_WIDTH)){1'b0}},OFFSET}};
assign MASK = (C_MASK_SWAP)? _rMaskSwap[7 -: C_MASK_WIDTH]: _rMask[C_MASK_WIDTH-1:0];
always @(*) begin
_rMask = 0;
_rMaskSwap = 0;
/* verilator lint_off CASEX */
casex(wSelect)
default: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b1111_1111;
end
4'b1000: begin
_rMask = 8'b0000_0001;
_rMaskSwap = 8'b1111_1111;
end
4'b1001: begin
_rMask = 8'b0000_0011;
_rMaskSwap = 8'b0111_1111;
end
4'b1010: begin
_rMask = 8'b0000_0111;
_rMaskSwap = 8'b0011_1111;
end
4'b1011: begin
_rMask = 8'b0000_1111;
_rMaskSwap = 8'b0001_1111;
end
4'b1100: begin
_rMask = 8'b0001_1111;
_rMaskSwap = 8'b0000_1111;
end
4'b1101: begin
_rMask = 8'b0011_1111;
_rMaskSwap = 8'b0000_0111;
end
4'b1110: begin
_rMask = 8'b0111_1111;
_rMaskSwap = 8'b0000_0011;
end
4'b1111: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b0000_0001;
end
endcase // casez ({OFFSET_MASK,OFFSET})
/* verilator lint_on CASEX */
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:28:59 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_0/zqynq_lab_1_design_axi_gpio_1_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_gpio_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_gpio_1_0,axi_gpio,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_gpio,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_axi_gpio_1_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i);
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [8:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [8:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT" *) output ip2intc_irpt;
(* x_interface_info = "xilinx.com:interface:gpio:1.0 GPIO TRI_I" *) input [4:0]gpio_io_i;
wire [4:0]gpio_io_i;
wire ip2intc_irpt;
wire s_axi_aclk;
wire [8:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [31:0]NLW_U0_gpio2_io_o_UNCONNECTED;
wire [31:0]NLW_U0_gpio2_io_t_UNCONNECTED;
wire [4:0]NLW_U0_gpio_io_o_UNCONNECTED;
wire [4:0]NLW_U0_gpio_io_t_UNCONNECTED;
(* C_ALL_INPUTS = "1" *)
(* C_ALL_INPUTS_2 = "0" *)
(* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *)
(* C_DOUT_DEFAULT = "0" *)
(* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *)
(* C_GPIO2_WIDTH = "32" *)
(* C_GPIO_WIDTH = "5" *)
(* C_INTERRUPT_PRESENT = "1" *)
(* C_IS_DUAL = "0" *)
(* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRI_DEFAULT = "-1" *)
(* C_TRI_DEFAULT_2 = "-1" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* ip_group = "LOGICORE" *)
zqynq_lab_1_design_axi_gpio_1_0_axi_gpio U0
(.gpio2_io_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.gpio2_io_o(NLW_U0_gpio2_io_o_UNCONNECTED[31:0]),
.gpio2_io_t(NLW_U0_gpio2_io_t_UNCONNECTED[31:0]),
.gpio_io_i(gpio_io_i),
.gpio_io_o(NLW_U0_gpio_io_o_UNCONNECTED[4:0]),
.gpio_io_t(NLW_U0_gpio_io_t_UNCONNECTED[4:0]),
.ip2intc_irpt(ip2intc_irpt),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "GPIO_Core" *)
module zqynq_lab_1_design_axi_gpio_1_0_GPIO_Core
(ip2bus_data,
GPIO_xferAck_i,
gpio_xferAck_Reg,
GPIO_intr,
Q,
gpio_io_o,
gpio_io_t,
Read_Reg_Rst,
\Not_Dual.gpio_OE_reg[4]_0 ,
s_axi_aclk,
\Not_Dual.gpio_OE_reg[3]_0 ,
\Not_Dual.gpio_OE_reg[2]_0 ,
\Not_Dual.gpio_OE_reg[1]_0 ,
GPIO_DBus_i,
bus2ip_reset,
bus2ip_cs,
gpio_io_i,
E,
D,
bus2ip_rnw_i_reg);
output [4:0]ip2bus_data;
output GPIO_xferAck_i;
output gpio_xferAck_Reg;
output GPIO_intr;
output [4:0]Q;
output [4:0]gpio_io_o;
output [4:0]gpio_io_t;
input Read_Reg_Rst;
input \Not_Dual.gpio_OE_reg[4]_0 ;
input s_axi_aclk;
input \Not_Dual.gpio_OE_reg[3]_0 ;
input \Not_Dual.gpio_OE_reg[2]_0 ;
input \Not_Dual.gpio_OE_reg[1]_0 ;
input [0:0]GPIO_DBus_i;
input bus2ip_reset;
input [0:0]bus2ip_cs;
input [4:0]gpio_io_i;
input [0:0]E;
input [4:0]D;
input [0:0]bus2ip_rnw_i_reg;
wire [4:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ;
wire \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4] ;
wire \Not_Dual.gpio_OE_reg[1]_0 ;
wire \Not_Dual.gpio_OE_reg[2]_0 ;
wire \Not_Dual.gpio_OE_reg[3]_0 ;
wire \Not_Dual.gpio_OE_reg[4]_0 ;
wire [4:0]Q;
wire Read_Reg_Rst;
wire [0:0]bus2ip_cs;
wire bus2ip_reset;
wire [0:0]bus2ip_rnw_i_reg;
wire [0:4]gpio_data_in_xor;
wire [4:0]gpio_io_i;
wire [0:4]gpio_io_i_d2;
wire [4:0]gpio_io_o;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire iGPIO_xferAck;
wire [4:0]ip2bus_data;
wire or_ints;
wire p_1_in;
wire p_2_in;
wire s_axi_aclk;
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_DBus_i),
.Q(ip2bus_data[4]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[1]_0 ),
.Q(ip2bus_data[3]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[2]_0 ),
.Q(ip2bus_data[2]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[3]_0 ),
.Q(ip2bus_data[1]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\Not_Dual.gpio_OE_reg[4]_0 ),
.Q(ip2bus_data[0]),
.R(Read_Reg_Rst));
FDRE \Not_Dual.GEN_INTERRUPT.GPIO_intr_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(or_ints),
.Q(GPIO_intr),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[0]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[1]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[2]),
.Q(p_1_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[3]),
.Q(p_2_in),
.R(bus2ip_reset));
FDRE \Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_data_in_xor[4]),
.Q(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4] ),
.R(bus2ip_reset));
zqynq_lab_1_design_axi_gpio_1_0_cdc_sync \Not_Dual.INPUT_DOUBLE_REGS3
(.D({gpio_data_in_xor[0],gpio_data_in_xor[1],gpio_data_in_xor[2],gpio_data_in_xor[3],gpio_data_in_xor[4]}),
.Q(Q),
.gpio_io_i(gpio_io_i),
.s_axi_aclk(s_axi_aclk),
.scndry_vect_out({gpio_io_i_d2[0],gpio_io_i_d2[1],gpio_io_i_d2[2],gpio_io_i_d2[3],gpio_io_i_d2[4]}));
FDRE \Not_Dual.gpio_Data_In_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[0]),
.Q(Q[4]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[1]),
.Q(Q[3]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[3]),
.Q(Q[1]),
.R(1'b0));
FDRE \Not_Dual.gpio_Data_In_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i_d2[4]),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(D[4]),
.Q(gpio_io_o[4]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(D[3]),
.Q(gpio_io_o[3]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(D[2]),
.Q(gpio_io_o[2]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(D[1]),
.Q(gpio_io_o[1]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\Not_Dual.gpio_Data_Out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(D[0]),
.Q(gpio_io_o[0]),
.R(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[0]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[4]),
.Q(gpio_io_t[4]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[1]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[3]),
.Q(gpio_io_t[3]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[2]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[2]),
.Q(gpio_io_t[2]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[3]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[1]),
.Q(gpio_io_t[1]),
.S(bus2ip_reset));
FDSE #(
.INIT(1'b1))
\Not_Dual.gpio_OE_reg[4]
(.C(s_axi_aclk),
.CE(bus2ip_rnw_i_reg),
.D(D[0]),
.Q(gpio_io_t[0]),
.S(bus2ip_reset));
FDRE gpio_xferAck_Reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_xferAck_i),
.Q(gpio_xferAck_Reg),
.R(bus2ip_reset));
LUT3 #(
.INIT(8'h10))
iGPIO_xferAck_i_1
(.I0(gpio_xferAck_Reg),
.I1(GPIO_xferAck_i),
.I2(bus2ip_cs),
.O(iGPIO_xferAck));
FDRE iGPIO_xferAck_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(iGPIO_xferAck),
.Q(GPIO_xferAck_i),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'hFFFFFFFE))
or_reduce
(.I0(p_1_in),
.I1(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[4] ),
.I2(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[0] ),
.I3(\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg_reg_n_0_[1] ),
.I4(p_2_in),
.O(or_ints));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module zqynq_lab_1_design_axi_gpio_1_0_address_decoder
(\ip2bus_data_i_D1_reg[0] ,
\Not_Dual.gpio_Data_Out_reg[4] ,
\ip_irpt_enable_reg_reg[0] ,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0]_0 ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0]_0 ,
ipif_glbl_irpt_enable_reg_reg,
start2,
s_axi_aclk,
s_axi_aresetn,
Q,
is_read,
ip2bus_rdack_i_D1,
is_write_reg,
ip2bus_wrack_i_D1,
s_axi_wdata,
\bus2ip_addr_i_reg[8] ,
gpio_io_t,
\Not_Dual.gpio_Data_In_reg[0] ,
bus2ip_rnw_i_reg,
bus2ip_reset,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1);
output \ip2bus_data_i_D1_reg[0] ;
output \Not_Dual.gpio_Data_Out_reg[4] ;
output \ip_irpt_enable_reg_reg[0] ;
output s_axi_arready;
output s_axi_wready;
output [4:0]D;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0]_0 ;
output ipif_glbl_irpt_enable_reg_reg;
input start2;
input s_axi_aclk;
input s_axi_aresetn;
input [3:0]Q;
input is_read;
input ip2bus_rdack_i_D1;
input is_write_reg;
input ip2bus_wrack_i_D1;
input [9:0]s_axi_wdata;
input [6:0]\bus2ip_addr_i_reg[8] ;
input [4:0]gpio_io_t;
input [4:0]\Not_Dual.gpio_Data_In_reg[0] ;
input bus2ip_rnw_i_reg;
input bus2ip_reset;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
wire Bus_RNW_reg_i_1_n_0;
wire [4:0]D;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ;
wire \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
wire [4:0]\Not_Dual.gpio_Data_In_reg[0] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_Data_Out_reg[4] ;
wire [3:0]Q;
wire Read_Reg_Rst;
wire [6:0]\bus2ip_addr_i_reg[8] ;
wire bus2ip_reset;
wire bus2ip_rnw_i_reg;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire \ip2bus_data_i_D1_reg[0] ;
wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire \ip_irpt_enable_reg_reg[0]_0 ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_write_reg;
wire [0:0]p_0_in;
wire p_10_in;
wire p_10_out;
wire p_11_in;
wire p_11_out;
wire p_12_in;
wire p_12_out;
wire p_13_in;
wire p_13_out;
wire p_14_in;
wire p_14_out;
wire p_15_in;
wire p_15_out;
wire p_16_in;
wire [0:0]p_1_in;
wire p_2_in;
wire [0:0]p_3_in;
wire p_3_in_0;
wire p_4_in;
wire p_4_out;
wire p_5_in;
wire p_5_out;
wire p_6_in;
wire p_6_out;
wire p_7_in;
wire p_7_out;
wire p_8_out;
wire p_9_in;
wire p_9_out;
wire pselect_hit_i_1;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire [9:0]s_axi_wdata;
wire s_axi_wready;
wire start2;
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(start2),
.I2(\ip_irpt_enable_reg_reg[0] ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\ip_irpt_enable_reg_reg[0] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0040000000000000))
\GEN_BKEND_CE_REGISTERS[10].ce_out_i[10]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_9_out));
FDRE \GEN_BKEND_CE_REGISTERS[10].ce_out_i_reg[10]
(.C(s_axi_aclk),
.CE(start2),
.D(p_9_out),
.Q(p_10_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h4000000000000000))
\GEN_BKEND_CE_REGISTERS[11].ce_out_i[11]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_8_out));
FDRE \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11]
(.C(s_axi_aclk),
.CE(start2),
.D(p_8_out),
.Q(p_9_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
\GEN_BKEND_CE_REGISTERS[12].ce_out_i[12]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_7_out));
FDRE \GEN_BKEND_CE_REGISTERS[12].ce_out_i_reg[12]
(.C(s_axi_aclk),
.CE(start2),
.D(p_7_out),
.Q(\ip2bus_data_i_D1_reg[0] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\GEN_BKEND_CE_REGISTERS[13].ce_out_i[13]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_6_out));
FDRE \GEN_BKEND_CE_REGISTERS[13].ce_out_i_reg[13]
(.C(s_axi_aclk),
.CE(start2),
.D(p_6_out),
.Q(p_7_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000000000000))
\GEN_BKEND_CE_REGISTERS[14].ce_out_i[14]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_5_out));
FDRE \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14]
(.C(s_axi_aclk),
.CE(start2),
.D(p_5_out),
.Q(p_6_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800000000000000))
\GEN_BKEND_CE_REGISTERS[15].ce_out_i[15]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [3]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_4_out));
FDRE \GEN_BKEND_CE_REGISTERS[15].ce_out_i_reg[15]
(.C(s_axi_aclk),
.CE(start2),
.D(p_4_out),
.Q(p_5_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0008000000000000))
\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[16].ce_out_i_reg[16]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[16].ce_out_i[16]_i_1_n_0 ),
.Q(p_4_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0800000000000000))
\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[17].ce_out_i_reg[17]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[17].ce_out_i[17]_i_1_n_0 ),
.Q(p_3_in_0),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0080000000000000))
\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[18].ce_out_i_reg[18]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[18].ce_out_i[18]_i_1_n_0 ),
.Q(p_2_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT3 #(
.INIT(8'hFD))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1
(.I0(s_axi_aresetn),
.I1(s_axi_arready),
.I2(s_axi_wready),
.O(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_2
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\bus2ip_addr_i_reg[8] [2]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_15_out));
FDRE \GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg[19]
(.C(s_axi_aclk),
.CE(start2),
.D(p_15_out),
.Q(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0001000000000000))
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi_aclk),
.CE(start2),
.D(\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1_n_0 ),
.Q(p_16_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0100000000000000))
\GEN_BKEND_CE_REGISTERS[5].ce_out_i[5]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_14_out));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi_aclk),
.CE(start2),
.D(p_14_out),
.Q(p_15_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0002000000000000))
\GEN_BKEND_CE_REGISTERS[6].ce_out_i[6]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_13_out));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi_aclk),
.CE(start2),
.D(p_13_out),
.Q(p_14_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0200000000000000))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(\bus2ip_addr_i_reg[8] [1]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [3]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_12_out));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(start2),
.D(p_12_out),
.Q(p_13_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0004000000000000))
\GEN_BKEND_CE_REGISTERS[8].ce_out_i[8]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_11_out));
FDRE \GEN_BKEND_CE_REGISTERS[8].ce_out_i_reg[8]
(.C(s_axi_aclk),
.CE(start2),
.D(p_11_out),
.Q(p_12_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0400000000000000))
\GEN_BKEND_CE_REGISTERS[9].ce_out_i[9]_i_1
(.I0(\bus2ip_addr_i_reg[8] [3]),
.I1(\bus2ip_addr_i_reg[8] [2]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\bus2ip_addr_i_reg[8] [0]),
.I4(\bus2ip_addr_i_reg[8] [6]),
.I5(start2),
.O(p_10_out));
FDRE \GEN_BKEND_CE_REGISTERS[9].ce_out_i_reg[9]
(.C(s_axi_aclk),
.CE(start2),
.D(p_10_out),
.Q(p_11_in),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFE00))
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(intr_rd_ce_or_reduce));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00FE0000))
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(ip2Bus_RdAck_intr_reg_hole_d1),
.I4(\ip_irpt_enable_reg_reg[0] ),
.O(\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h00FE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(intr_wr_ce_or_reduce));
LUT5 #(
.INIT(32'hFFFFFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2
(.I0(p_16_in),
.I1(p_2_in),
.I2(\GEN_BKEND_CE_REGISTERS[19].ce_out_i_reg_n_0_[19] ),
.I3(p_14_in),
.I4(p_15_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3
(.I0(p_12_in),
.I1(p_13_in),
.I2(p_10_in),
.I3(p_11_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4
(.I0(p_5_in),
.I1(p_7_in),
.I2(p_3_in_0),
.I3(p_4_in),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h000000FE))
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_i_1
(.I0(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_2_n_0 ),
.I1(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_3_n_0 ),
.I2(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_i_4_n_0 ),
.I3(\ip_irpt_enable_reg_reg[0] ),
.I4(ip2Bus_WrAck_intr_reg_hole_d1),
.O(\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ));
LUT6 #(
.INIT(64'h0000000000000002))
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1
(.I0(start2),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [4]),
.I3(\bus2ip_addr_i_reg[8] [5]),
.I4(\bus2ip_addr_i_reg[8] [3]),
.I5(\bus2ip_addr_i_reg[8] [2]),
.O(pselect_hit_i_1));
FDRE \MEM_DECODE_GEN[0].cs_out_i_reg[0]
(.C(s_axi_aclk),
.CE(start2),
.D(pselect_hit_i_1),
.Q(\Not_Dual.gpio_Data_Out_reg[4] ),
.R(\GEN_BKEND_CE_REGISTERS[19].ce_out_i[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i[27]_i_1
(.I0(gpio_io_t[4]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [4]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[4] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(GPIO_DBus_i));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i[28]_i_1
(.I0(gpio_io_t[3]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [3]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[4] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i[29]_i_1
(.I0(gpio_io_t[2]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [2]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[4] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i[30]_i_1
(.I0(gpio_io_t[1]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [1]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[4] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ));
LUT4 #(
.INIT(16'hFFDF))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_1
(.I0(\Not_Dual.gpio_Data_Out_reg[4] ),
.I1(GPIO_xferAck_i),
.I2(bus2ip_rnw_i_reg),
.I3(gpio_xferAck_Reg),
.O(Read_Reg_Rst));
LUT6 #(
.INIT(64'h000A0000000C0000))
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_2
(.I0(gpio_io_t[0]),
.I1(\Not_Dual.gpio_Data_In_reg[0] [0]),
.I2(\bus2ip_addr_i_reg[8] [6]),
.I3(\bus2ip_addr_i_reg[8] [1]),
.I4(\Not_Dual.gpio_Data_Out_reg[4] ),
.I5(\bus2ip_addr_i_reg[8] [0]),
.O(\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ));
LUT6 #(
.INIT(64'hFFFFFFFF00000100))
\Not_Dual.gpio_Data_Out[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\Not_Dual.gpio_Data_Out_reg[4] ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(bus2ip_reset),
.O(\Not_Dual.gpio_Data_Out_reg[0] ));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[0]_i_2
(.I0(s_axi_wdata[9]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[4] ),
.I3(s_axi_wdata[4]),
.O(D[4]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[1]_i_1
(.I0(s_axi_wdata[8]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[4] ),
.I3(s_axi_wdata[3]),
.O(D[3]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[2]_i_1
(.I0(s_axi_wdata[7]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[4] ),
.I3(s_axi_wdata[2]),
.O(D[2]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[3]_i_1
(.I0(s_axi_wdata[6]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[4] ),
.I3(s_axi_wdata[1]),
.O(D[1]));
LUT4 #(
.INIT(16'hBA8A))
\Not_Dual.gpio_Data_Out[4]_i_1
(.I0(s_axi_wdata[5]),
.I1(\bus2ip_addr_i_reg[8] [1]),
.I2(\Not_Dual.gpio_Data_Out_reg[4] ),
.I3(s_axi_wdata[0]),
.O(D[0]));
LUT6 #(
.INIT(64'hFFFFFFFF01000000))
\Not_Dual.gpio_OE[0]_i_1
(.I0(bus2ip_rnw_i_reg),
.I1(\bus2ip_addr_i_reg[8] [6]),
.I2(\bus2ip_addr_i_reg[8] [1]),
.I3(\Not_Dual.gpio_Data_Out_reg[4] ),
.I4(\bus2ip_addr_i_reg[8] [0]),
.I5(bus2ip_reset),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h44444440))
intr2bus_rdack_i_1
(.I0(irpt_rdack_d1),
.I1(\ip_irpt_enable_reg_reg[0] ),
.I2(p_9_in),
.I3(\ip2bus_data_i_D1_reg[0] ),
.I4(p_6_in),
.O(intr2bus_rdack0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h000000FE))
intr2bus_wrack_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.I4(irpt_wrack_d1),
.O(interrupt_wrce_strb));
LUT5 #(
.INIT(32'h00000080))
\ip2bus_data_i_D1[0]_i_1
(.I0(p_0_in),
.I1(p_9_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_6_in),
.I4(\ip2bus_data_i_D1_reg[0] ),
.O(\ip2bus_data_i_D1_reg[0]_0 [1]));
LUT6 #(
.INIT(64'hEEEEAAAAFAAAAAAA))
\ip2bus_data_i_D1[31]_i_1
(.I0(ip2bus_data),
.I1(p_3_in),
.I2(p_1_in),
.I3(p_6_in),
.I4(\ip_irpt_enable_reg_reg[0] ),
.I5(\ip2bus_data_i_D1_reg[0] ),
.O(\ip2bus_data_i_D1_reg[0]_0 [0]));
LUT4 #(
.INIT(16'hFB08))
\ip_irpt_enable_reg[0]_i_1
(.I0(s_axi_wdata[0]),
.I1(p_6_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_1_in),
.O(\ip_irpt_enable_reg_reg[0]_0 ));
LUT4 #(
.INIT(16'hFB08))
ipif_glbl_irpt_enable_reg_i_1
(.I0(s_axi_wdata[9]),
.I1(p_9_in),
.I2(\ip_irpt_enable_reg_reg[0] ),
.I3(p_0_in),
.O(ipif_glbl_irpt_enable_reg_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'hFE00))
irpt_rdack_d1_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(irpt_rdack));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h00FE))
irpt_wrack_d1_i_1
(.I0(p_9_in),
.I1(\ip2bus_data_i_D1_reg[0] ),
.I2(p_6_in),
.I3(\ip_irpt_enable_reg_reg[0] ),
.O(irpt_wrack));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_arready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_read),
.I5(ip2bus_rdack_i_D1),
.O(s_axi_arready));
LUT6 #(
.INIT(64'hFFFFFFFF00020000))
s_axi_wready_INST_0
(.I0(Q[3]),
.I1(Q[2]),
.I2(Q[1]),
.I3(Q[0]),
.I4(is_write_reg),
.I5(ip2bus_wrack_i_D1),
.O(s_axi_wready));
endmodule
(* C_ALL_INPUTS = "1" *) (* C_ALL_INPUTS_2 = "0" *) (* C_ALL_OUTPUTS = "0" *)
(* C_ALL_OUTPUTS_2 = "0" *) (* C_DOUT_DEFAULT = "0" *) (* C_DOUT_DEFAULT_2 = "0" *)
(* C_FAMILY = "zynq" *) (* C_GPIO2_WIDTH = "32" *) (* C_GPIO_WIDTH = "5" *)
(* C_INTERRUPT_PRESENT = "1" *) (* C_IS_DUAL = "0" *) (* C_S_AXI_ADDR_WIDTH = "9" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRI_DEFAULT = "-1" *) (* C_TRI_DEFAULT_2 = "-1" *)
(* ORIG_REF_NAME = "axi_gpio" *) (* downgradeipidentifiedwarnings = "yes" *) (* ip_group = "LOGICORE" *)
module zqynq_lab_1_design_axi_gpio_1_0_axi_gpio
(s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
ip2intc_irpt,
gpio_io_i,
gpio_io_o,
gpio_io_t,
gpio2_io_i,
gpio2_io_o,
gpio2_io_t);
(* max_fanout = "10000" *) (* sigis = "Clk" *) input s_axi_aclk;
(* max_fanout = "10000" *) (* sigis = "Rst" *) input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
(* sigis = "INTR_LEVEL_HIGH" *) output ip2intc_irpt;
input [4:0]gpio_io_i;
output [4:0]gpio_io_o;
output [4:0]gpio_io_t;
input [31:0]gpio2_io_i;
output [31:0]gpio2_io_o;
output [31:0]gpio2_io_t;
wire \<const0> ;
wire \<const1> ;
wire AXI_LITE_IPIF_I_n_13;
wire AXI_LITE_IPIF_I_n_14;
wire AXI_LITE_IPIF_I_n_15;
wire AXI_LITE_IPIF_I_n_16;
wire AXI_LITE_IPIF_I_n_18;
wire AXI_LITE_IPIF_I_n_19;
wire AXI_LITE_IPIF_I_n_27;
wire AXI_LITE_IPIF_I_n_29;
wire AXI_LITE_IPIF_I_n_31;
wire AXI_LITE_IPIF_I_n_32;
wire [0:4]DBus_Reg;
wire [27:27]GPIO_DBus_i;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire IP2INTC_Irpt_i;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ;
wire Read_Reg_Rst;
wire [1:1]bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_reset_i_1_n_0;
wire bus2ip_rnw;
wire [0:4]gpio_Data_In;
wire [4:0]gpio_io_i;
wire [4:0]gpio_io_o;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [27:31]ip2bus_data;
wire [31:31]ip2bus_data_i;
wire [0:31]ip2bus_data_i_D1;
wire ip2bus_rdack_i;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i;
wire ip2bus_wrack_i_D1;
wire ip2intc_irpt;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [31:31]p_0_in;
wire [0:0]p_0_out;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Clk" *) wire s_axi_aclk;
wire [8:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) (* sigis = "Rst" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [8:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]\^s_axi_rdata ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign gpio2_io_o[31] = \<const0> ;
assign gpio2_io_o[30] = \<const0> ;
assign gpio2_io_o[29] = \<const0> ;
assign gpio2_io_o[28] = \<const0> ;
assign gpio2_io_o[27] = \<const0> ;
assign gpio2_io_o[26] = \<const0> ;
assign gpio2_io_o[25] = \<const0> ;
assign gpio2_io_o[24] = \<const0> ;
assign gpio2_io_o[23] = \<const0> ;
assign gpio2_io_o[22] = \<const0> ;
assign gpio2_io_o[21] = \<const0> ;
assign gpio2_io_o[20] = \<const0> ;
assign gpio2_io_o[19] = \<const0> ;
assign gpio2_io_o[18] = \<const0> ;
assign gpio2_io_o[17] = \<const0> ;
assign gpio2_io_o[16] = \<const0> ;
assign gpio2_io_o[15] = \<const0> ;
assign gpio2_io_o[14] = \<const0> ;
assign gpio2_io_o[13] = \<const0> ;
assign gpio2_io_o[12] = \<const0> ;
assign gpio2_io_o[11] = \<const0> ;
assign gpio2_io_o[10] = \<const0> ;
assign gpio2_io_o[9] = \<const0> ;
assign gpio2_io_o[8] = \<const0> ;
assign gpio2_io_o[7] = \<const0> ;
assign gpio2_io_o[6] = \<const0> ;
assign gpio2_io_o[5] = \<const0> ;
assign gpio2_io_o[4] = \<const0> ;
assign gpio2_io_o[3] = \<const0> ;
assign gpio2_io_o[2] = \<const0> ;
assign gpio2_io_o[1] = \<const0> ;
assign gpio2_io_o[0] = \<const0> ;
assign gpio2_io_t[31] = \<const1> ;
assign gpio2_io_t[30] = \<const1> ;
assign gpio2_io_t[29] = \<const1> ;
assign gpio2_io_t[28] = \<const1> ;
assign gpio2_io_t[27] = \<const1> ;
assign gpio2_io_t[26] = \<const1> ;
assign gpio2_io_t[25] = \<const1> ;
assign gpio2_io_t[24] = \<const1> ;
assign gpio2_io_t[23] = \<const1> ;
assign gpio2_io_t[22] = \<const1> ;
assign gpio2_io_t[21] = \<const1> ;
assign gpio2_io_t[20] = \<const1> ;
assign gpio2_io_t[19] = \<const1> ;
assign gpio2_io_t[18] = \<const1> ;
assign gpio2_io_t[17] = \<const1> ;
assign gpio2_io_t[16] = \<const1> ;
assign gpio2_io_t[15] = \<const1> ;
assign gpio2_io_t[14] = \<const1> ;
assign gpio2_io_t[13] = \<const1> ;
assign gpio2_io_t[12] = \<const1> ;
assign gpio2_io_t[11] = \<const1> ;
assign gpio2_io_t[10] = \<const1> ;
assign gpio2_io_t[9] = \<const1> ;
assign gpio2_io_t[8] = \<const1> ;
assign gpio2_io_t[7] = \<const1> ;
assign gpio2_io_t[6] = \<const1> ;
assign gpio2_io_t[5] = \<const1> ;
assign gpio2_io_t[4] = \<const1> ;
assign gpio2_io_t[3] = \<const1> ;
assign gpio2_io_t[2] = \<const1> ;
assign gpio2_io_t[1] = \<const1> ;
assign gpio2_io_t[0] = \<const1> ;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rdata[31] = \^s_axi_rdata [31];
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4:0] = \^s_axi_rdata [4:0];
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
zqynq_lab_1_design_axi_gpio_1_0_axi_lite_ipif AXI_LITE_IPIF_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4]}),
.E(AXI_LITE_IPIF_I_n_18),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_27),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (AXI_LITE_IPIF_I_n_29),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] (AXI_LITE_IPIF_I_n_16),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] (AXI_LITE_IPIF_I_n_15),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] (AXI_LITE_IPIF_I_n_14),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] (AXI_LITE_IPIF_I_n_13),
.\Not_Dual.gpio_Data_Out_reg[0] (AXI_LITE_IPIF_I_n_19),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4]}),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data[31]),
.\ip2bus_data_i_D1_reg[0] ({p_0_out,ip2bus_data_i}),
.\ip2bus_data_i_D1_reg[0]_0 ({ip2bus_data_i_D1[0],ip2bus_data_i_D1[27],ip2bus_data_i_D1[28],ip2bus_data_i_D1[29],ip2bus_data_i_D1[30],ip2bus_data_i_D1[31]}),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (AXI_LITE_IPIF_I_n_31),
.ipif_glbl_irpt_enable_reg_reg(AXI_LITE_IPIF_I_n_32),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[8:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[8:2]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata({\^s_axi_rdata [31],\^s_axi_rdata [4:0]}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata({s_axi_wdata[31:27],s_axi_wdata[4:0]}),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
zqynq_lab_1_design_axi_gpio_1_0_interrupt_control \INTR_CTRLR_GEN.INTERRUPT_CONTROL_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] (AXI_LITE_IPIF_I_n_32),
.\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] (AXI_LITE_IPIF_I_n_31),
.GPIO_intr(GPIO_intr),
.GPIO_xferAck_i(GPIO_xferAck_i),
.IP2INTC_Irpt_i(IP2INTC_Irpt_i),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw(bus2ip_rnw),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.ip2Bus_RdAck_intr_reg_hole(ip2Bus_RdAck_intr_reg_hole),
.ip2Bus_WrAck_intr_reg_hole(ip2Bus_WrAck_intr_reg_hole),
.ip2bus_rdack_i(ip2bus_rdack_i),
.ip2bus_wrack_i(ip2bus_wrack_i),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.p_8_in(\I_SLAVE_ATTACHMENT/I_DECODER/p_8_in ),
.s_axi_aclk(s_axi_aclk),
.s_axi_wdata(s_axi_wdata[0]));
FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_rd_ce_or_reduce),
.Q(ip2Bus_RdAck_intr_reg_hole_d1),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_27),
.Q(ip2Bus_RdAck_intr_reg_hole),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr_wr_ce_or_reduce),
.Q(ip2Bus_WrAck_intr_reg_hole_d1),
.R(bus2ip_reset));
FDRE \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(AXI_LITE_IPIF_I_n_29),
.Q(ip2Bus_WrAck_intr_reg_hole),
.R(bus2ip_reset));
(* sigis = "INTR_LEVEL_HIGH" *)
FDRE \INTR_CTRLR_GEN.ip2intc_irpt_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(IP2INTC_Irpt_i),
.Q(ip2intc_irpt),
.R(bus2ip_reset));
VCC VCC
(.P(\<const1> ));
LUT1 #(
.INIT(2'h1))
bus2ip_reset_i_1
(.I0(s_axi_aresetn),
.O(bus2ip_reset_i_1_n_0));
FDRE bus2ip_reset_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus2ip_reset_i_1_n_0),
.Q(bus2ip_reset),
.R(1'b0));
zqynq_lab_1_design_axi_gpio_1_0_GPIO_Core gpio_core_1
(.D({DBus_Reg[0],DBus_Reg[1],DBus_Reg[2],DBus_Reg[3],DBus_Reg[4]}),
.E(AXI_LITE_IPIF_I_n_19),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_intr(GPIO_intr),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\Not_Dual.gpio_OE_reg[1]_0 (AXI_LITE_IPIF_I_n_16),
.\Not_Dual.gpio_OE_reg[2]_0 (AXI_LITE_IPIF_I_n_15),
.\Not_Dual.gpio_OE_reg[3]_0 (AXI_LITE_IPIF_I_n_14),
.\Not_Dual.gpio_OE_reg[4]_0 (AXI_LITE_IPIF_I_n_13),
.Q({gpio_Data_In[0],gpio_Data_In[1],gpio_Data_In[2],gpio_Data_In[3],gpio_Data_In[4]}),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_cs(bus2ip_cs),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw_i_reg(AXI_LITE_IPIF_I_n_18),
.gpio_io_i(gpio_io_i),
.gpio_io_o(gpio_io_o),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.ip2bus_data({ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.s_axi_aclk(s_axi_aclk));
FDRE \ip2bus_data_i_D1_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out),
.Q(ip2bus_data_i_D1[0]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[27]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[27]),
.Q(ip2bus_data_i_D1[27]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[28]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[28]),
.Q(ip2bus_data_i_D1[28]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[29]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[29]),
.Q(ip2bus_data_i_D1[29]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[30]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data[30]),
.Q(ip2bus_data_i_D1[30]),
.R(bus2ip_reset));
FDRE \ip2bus_data_i_D1_reg[31]
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_data_i),
.Q(ip2bus_data_i_D1[31]),
.R(bus2ip_reset));
FDRE ip2bus_rdack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_rdack_i),
.Q(ip2bus_rdack_i_D1),
.R(bus2ip_reset));
FDRE ip2bus_wrack_i_D1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(ip2bus_wrack_i),
.Q(ip2bus_wrack_i_D1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module zqynq_lab_1_design_axi_gpio_1_0_axi_lite_ipif
(p_8_in,
bus2ip_rnw,
bus2ip_cs,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0] ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0] ,
ipif_glbl_irpt_enable_reg_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
gpio_io_t,
Q,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]_0 );
output p_8_in;
output bus2ip_rnw;
output [0:0]bus2ip_cs;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [4:0]D;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0] ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0] ;
output ipif_glbl_irpt_enable_reg_reg;
output [5:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [6:0]s_axi_awaddr;
input [6:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [9:0]s_axi_wdata;
input [4:0]gpio_io_t;
input [4:0]Q;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input [5:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire Bus_RNW_reg;
wire [4:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire [4:0]Q;
wire Read_Reg_Rst;
wire [0:0]bus2ip_cs;
wire bus2ip_reset;
wire bus2ip_rnw;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire [1:0]\ip2bus_data_i_D1_reg[0] ;
wire [5:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
wire p_8_in;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [5:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [9:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
zqynq_lab_1_design_axi_gpio_1_0_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_Data_Out_reg[4] (bus2ip_cs),
.\Not_Dual.gpio_OE_reg[0] (bus2ip_rnw),
.Q(Q),
.Read_Reg_Rst(Read_Reg_Rst),
.bus2ip_reset(bus2ip_reset),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data),
.\ip2bus_data_i_D1_reg[0] (p_8_in),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_1 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (Bus_RNW_reg),
.\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0] ),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module zqynq_lab_1_design_axi_gpio_1_0_cdc_sync
(D,
scndry_vect_out,
Q,
gpio_io_i,
s_axi_aclk);
output [4:0]D;
output [4:0]scndry_vect_out;
input [4:0]Q;
input [4:0]gpio_io_i;
input s_axi_aclk;
wire [4:0]D;
wire [4:0]Q;
wire [4:0]gpio_io_i;
wire s_axi_aclk;
wire s_level_out_bus_d1_cdc_to_0;
wire s_level_out_bus_d1_cdc_to_1;
wire s_level_out_bus_d1_cdc_to_2;
wire s_level_out_bus_d1_cdc_to_3;
wire s_level_out_bus_d1_cdc_to_4;
wire s_level_out_bus_d2_0;
wire s_level_out_bus_d2_1;
wire s_level_out_bus_d2_2;
wire s_level_out_bus_d2_3;
wire s_level_out_bus_d2_4;
wire s_level_out_bus_d3_0;
wire s_level_out_bus_d3_1;
wire s_level_out_bus_d3_2;
wire s_level_out_bus_d3_3;
wire s_level_out_bus_d3_4;
wire [4:0]scndry_vect_out;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_0),
.Q(s_level_out_bus_d2_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_1),
.Q(s_level_out_bus_d2_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_2),
.Q(s_level_out_bus_d2_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_3),
.Q(s_level_out_bus_d2_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d1_cdc_to_4),
.Q(s_level_out_bus_d2_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_0),
.Q(s_level_out_bus_d3_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_1),
.Q(s_level_out_bus_d3_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_2),
.Q(s_level_out_bus_d3_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_3),
.Q(s_level_out_bus_d3_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d2_4),
.Q(s_level_out_bus_d3_4),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_0),
.Q(scndry_vect_out[0]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_1),
.Q(scndry_vect_out[1]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_2),
.Q(scndry_vect_out[2]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_3),
.Q(scndry_vect_out[3]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_bus_d3_4),
.Q(scndry_vect_out[4]),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[0]),
.Q(s_level_out_bus_d1_cdc_to_0),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[1]),
.Q(s_level_out_bus_d1_cdc_to_1),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[2]),
.Q(s_level_out_bus_d1_cdc_to_2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[3]),
.Q(s_level_out_bus_d1_cdc_to_3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(gpio_io_i[4]),
.Q(s_level_out_bus_d1_cdc_to_4),
.R(1'b0));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[0]_i_1
(.I0(Q[4]),
.I1(scndry_vect_out[4]),
.O(D[4]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[1]_i_1
(.I0(Q[3]),
.I1(scndry_vect_out[3]),
.O(D[3]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[2]_i_1
(.I0(Q[2]),
.I1(scndry_vect_out[2]),
.O(D[2]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[3]_i_1
(.I0(Q[1]),
.I1(scndry_vect_out[1]),
.O(D[1]));
LUT2 #(
.INIT(4'h6))
\Not_Dual.GEN_INTERRUPT.gpio_data_in_xor_reg[4]_i_1
(.I0(Q[0]),
.I1(scndry_vect_out[0]),
.O(D[0]));
endmodule
(* ORIG_REF_NAME = "interrupt_control" *)
module zqynq_lab_1_design_axi_gpio_1_0_interrupt_control
(irpt_wrack_d1,
p_3_in,
irpt_rdack_d1,
p_1_in,
p_0_in,
IP2INTC_Irpt_i,
ip2bus_wrack_i,
ip2bus_rdack_i,
bus2ip_reset,
irpt_wrack,
s_axi_aclk,
GPIO_intr,
interrupt_wrce_strb,
irpt_rdack,
intr2bus_rdack0,
\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ,
\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ,
p_8_in,
s_axi_wdata,
Bus_RNW_reg,
ip2Bus_WrAck_intr_reg_hole,
bus2ip_rnw,
GPIO_xferAck_i,
ip2Bus_RdAck_intr_reg_hole);
output irpt_wrack_d1;
output [0:0]p_3_in;
output irpt_rdack_d1;
output [0:0]p_1_in;
output [0:0]p_0_in;
output IP2INTC_Irpt_i;
output ip2bus_wrack_i;
output ip2bus_rdack_i;
input bus2ip_reset;
input irpt_wrack;
input s_axi_aclk;
input GPIO_intr;
input interrupt_wrce_strb;
input irpt_rdack;
input intr2bus_rdack0;
input \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
input \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
input p_8_in;
input [0:0]s_axi_wdata;
input Bus_RNW_reg;
input ip2Bus_WrAck_intr_reg_hole;
input bus2ip_rnw;
input GPIO_xferAck_i;
input ip2Bus_RdAck_intr_reg_hole;
wire Bus_RNW_reg;
wire \GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ;
wire \GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ;
wire \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ;
wire GPIO_intr;
wire GPIO_xferAck_i;
wire IP2INTC_Irpt_i;
wire bus2ip_reset;
wire bus2ip_rnw;
wire interrupt_wrce_strb;
wire intr2bus_rdack;
wire intr2bus_rdack0;
wire intr2bus_wrack;
wire ip2Bus_RdAck_intr_reg_hole;
wire ip2Bus_WrAck_intr_reg_hole;
wire ip2bus_rdack_i;
wire ip2bus_wrack_i;
wire irpt_dly1;
wire irpt_dly2;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire [0:0]p_0_in;
wire [0:0]p_1_in;
wire [0:0]p_3_in;
wire p_8_in;
wire s_axi_aclk;
wire [0:0]s_axi_wdata;
FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GPIO_intr),
.Q(irpt_dly1),
.S(bus2ip_reset));
FDSE \DO_IRPT_INPUT[0].GEN_POS_EDGE_DETECT.irpt_dly2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_dly1),
.Q(irpt_dly2),
.S(bus2ip_reset));
LUT6 #(
.INIT(64'hF4F4F4F44FF4F4F4))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1
(.I0(irpt_dly2),
.I1(irpt_dly1),
.I2(p_3_in),
.I3(p_8_in),
.I4(s_axi_wdata),
.I5(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'hE))
\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2
(.I0(irpt_wrack_d1),
.I1(Bus_RNW_reg),
.O(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_2_n_0 ));
FDRE \GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_IP_IRPT_STATUS_REG[0].GEN_REG_STATUS.ip_irpt_status_reg[0]_i_1_n_0 ),
.Q(p_3_in),
.R(bus2ip_reset));
LUT3 #(
.INIT(8'h80))
\INTR_CTRLR_GEN.ip2intc_irpt_i_1
(.I0(p_3_in),
.I1(p_1_in),
.I2(p_0_in),
.O(IP2INTC_Irpt_i));
FDRE intr2bus_rdack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(intr2bus_rdack0),
.Q(intr2bus_rdack),
.R(bus2ip_reset));
FDRE intr2bus_wrack_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(interrupt_wrce_strb),
.Q(intr2bus_wrack),
.R(bus2ip_reset));
LUT4 #(
.INIT(16'hFEEE))
ip2bus_rdack_i_D1_i_1
(.I0(ip2Bus_RdAck_intr_reg_hole),
.I1(intr2bus_rdack),
.I2(bus2ip_rnw),
.I3(GPIO_xferAck_i),
.O(ip2bus_rdack_i));
LUT4 #(
.INIT(16'hEFEE))
ip2bus_wrack_i_D1_i_1
(.I0(ip2Bus_WrAck_intr_reg_hole),
.I1(intr2bus_wrack),
.I2(bus2ip_rnw),
.I3(GPIO_xferAck_i),
.O(ip2bus_wrack_i));
FDRE \ip_irpt_enable_reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[14].ce_out_i_reg[14] ),
.Q(p_1_in),
.R(bus2ip_reset));
FDRE ipif_glbl_irpt_enable_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[11].ce_out_i_reg[11] ),
.Q(p_0_in),
.R(bus2ip_reset));
FDRE irpt_rdack_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_rdack),
.Q(irpt_rdack_d1),
.R(bus2ip_reset));
FDRE irpt_wrack_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(irpt_wrack),
.Q(irpt_wrack_d1),
.R(bus2ip_reset));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module zqynq_lab_1_design_axi_gpio_1_0_slave_attachment
(\ip2bus_data_i_D1_reg[0] ,
\Not_Dual.gpio_OE_reg[0] ,
\Not_Dual.gpio_Data_Out_reg[4] ,
\ip_irpt_enable_reg_reg[0] ,
s_axi_rvalid,
s_axi_bvalid,
s_axi_arready,
s_axi_wready,
D,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ,
GPIO_DBus_i,
E,
\Not_Dual.gpio_Data_Out_reg[0] ,
\ip2bus_data_i_D1_reg[0]_0 ,
intr2bus_rdack0,
irpt_rdack,
irpt_wrack,
interrupt_wrce_strb,
Read_Reg_Rst,
\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ,
intr_rd_ce_or_reduce,
\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ,
intr_wr_ce_or_reduce,
\ip_irpt_enable_reg_reg[0]_0 ,
ipif_glbl_irpt_enable_reg_reg,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
s_axi_arvalid,
s_axi_aresetn,
ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1,
s_axi_bready,
s_axi_rready,
s_axi_awaddr,
s_axi_araddr,
s_axi_awvalid,
s_axi_wvalid,
s_axi_wdata,
gpio_io_t,
Q,
p_0_in,
irpt_rdack_d1,
irpt_wrack_d1,
ip2bus_data,
p_3_in,
p_1_in,
GPIO_xferAck_i,
gpio_xferAck_Reg,
ip2Bus_RdAck_intr_reg_hole_d1,
ip2Bus_WrAck_intr_reg_hole_d1,
\ip2bus_data_i_D1_reg[0]_1 );
output \ip2bus_data_i_D1_reg[0] ;
output \Not_Dual.gpio_OE_reg[0] ;
output \Not_Dual.gpio_Data_Out_reg[4] ;
output \ip_irpt_enable_reg_reg[0] ;
output s_axi_rvalid;
output s_axi_bvalid;
output s_axi_arready;
output s_axi_wready;
output [4:0]D;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
output \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
output [0:0]GPIO_DBus_i;
output [0:0]E;
output [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
output [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
output intr2bus_rdack0;
output irpt_rdack;
output irpt_wrack;
output interrupt_wrce_strb;
output Read_Reg_Rst;
output \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
output intr_rd_ce_or_reduce;
output \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
output intr_wr_ce_or_reduce;
output \ip_irpt_enable_reg_reg[0]_0 ;
output ipif_glbl_irpt_enable_reg_reg;
output [5:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input s_axi_arvalid;
input s_axi_aresetn;
input ip2bus_rdack_i_D1;
input ip2bus_wrack_i_D1;
input s_axi_bready;
input s_axi_rready;
input [6:0]s_axi_awaddr;
input [6:0]s_axi_araddr;
input s_axi_awvalid;
input s_axi_wvalid;
input [9:0]s_axi_wdata;
input [4:0]gpio_io_t;
input [4:0]Q;
input [0:0]p_0_in;
input irpt_rdack_d1;
input irpt_wrack_d1;
input [0:0]ip2bus_data;
input [0:0]p_3_in;
input [0:0]p_1_in;
input GPIO_xferAck_i;
input gpio_xferAck_Reg;
input ip2Bus_RdAck_intr_reg_hole_d1;
input ip2Bus_WrAck_intr_reg_hole_d1;
input [5:0]\ip2bus_data_i_D1_reg[0]_1 ;
wire [4:0]D;
wire [0:0]E;
wire [0:0]GPIO_DBus_i;
wire GPIO_xferAck_i;
wire [3:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire \INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ;
wire \INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ;
wire \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ;
wire [0:0]\Not_Dual.gpio_Data_Out_reg[0] ;
wire \Not_Dual.gpio_Data_Out_reg[4] ;
wire \Not_Dual.gpio_OE_reg[0] ;
wire [4:0]Q;
wire Read_Reg_Rst;
wire [0:6]bus2ip_addr;
wire bus2ip_reset;
wire bus2ip_rnw_i06_out;
wire clear;
wire [4:0]gpio_io_t;
wire gpio_xferAck_Reg;
wire interrupt_wrce_strb;
wire intr2bus_rdack0;
wire intr_rd_ce_or_reduce;
wire intr_wr_ce_or_reduce;
wire ip2Bus_RdAck_intr_reg_hole_d1;
wire ip2Bus_WrAck_intr_reg_hole_d1;
wire [0:0]ip2bus_data;
wire \ip2bus_data_i_D1_reg[0] ;
wire [1:0]\ip2bus_data_i_D1_reg[0]_0 ;
wire [5:0]\ip2bus_data_i_D1_reg[0]_1 ;
wire ip2bus_rdack_i_D1;
wire ip2bus_wrack_i_D1;
wire \ip_irpt_enable_reg_reg[0] ;
wire \ip_irpt_enable_reg_reg[0]_0 ;
wire ipif_glbl_irpt_enable_reg_reg;
wire irpt_rdack;
wire irpt_rdack_d1;
wire irpt_wrack;
wire irpt_wrack_d1;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire [0:0]p_0_in;
wire [1:0]p_0_out__0;
wire [0:0]p_1_in;
wire [8:2]p_1_in__0;
wire [0:0]p_3_in;
wire [3:0]plusOp;
wire s_axi_aclk;
wire [6:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [6:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire s_axi_bvalid_i_i_1_n_0;
wire [5:0]s_axi_rdata;
wire s_axi_rdata_i;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_i_1_n_0;
wire [9:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire \state[1]_i_2_n_0 ;
wire \state[1]_i_3_n_0 ;
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(state[1]),
.I1(state[0]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
zqynq_lab_1_design_axi_gpio_1_0_address_decoder I_DECODER
(.D(D),
.E(E),
.GPIO_DBus_i(GPIO_DBus_i),
.GPIO_xferAck_i(GPIO_xferAck_i),
.\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_RdAck_intr_reg_hole_reg ),
.\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg (\INTR_CTRLR_GEN.ip2Bus_WrAck_intr_reg_hole_reg ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30] ),
.\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] (\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31] ),
.\Not_Dual.gpio_Data_In_reg[0] (Q),
.\Not_Dual.gpio_Data_Out_reg[0] (\Not_Dual.gpio_Data_Out_reg[0] ),
.\Not_Dual.gpio_Data_Out_reg[4] (\Not_Dual.gpio_Data_Out_reg[4] ),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.Read_Reg_Rst(Read_Reg_Rst),
.\bus2ip_addr_i_reg[8] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2],bus2ip_addr[3],bus2ip_addr[4],bus2ip_addr[5],bus2ip_addr[6]}),
.bus2ip_reset(bus2ip_reset),
.bus2ip_rnw_i_reg(\Not_Dual.gpio_OE_reg[0] ),
.gpio_io_t(gpio_io_t),
.gpio_xferAck_Reg(gpio_xferAck_Reg),
.interrupt_wrce_strb(interrupt_wrce_strb),
.intr2bus_rdack0(intr2bus_rdack0),
.intr_rd_ce_or_reduce(intr_rd_ce_or_reduce),
.intr_wr_ce_or_reduce(intr_wr_ce_or_reduce),
.ip2Bus_RdAck_intr_reg_hole_d1(ip2Bus_RdAck_intr_reg_hole_d1),
.ip2Bus_WrAck_intr_reg_hole_d1(ip2Bus_WrAck_intr_reg_hole_d1),
.ip2bus_data(ip2bus_data),
.\ip2bus_data_i_D1_reg[0] (\ip2bus_data_i_D1_reg[0] ),
.\ip2bus_data_i_D1_reg[0]_0 (\ip2bus_data_i_D1_reg[0]_0 ),
.ip2bus_rdack_i_D1(ip2bus_rdack_i_D1),
.ip2bus_wrack_i_D1(ip2bus_wrack_i_D1),
.\ip_irpt_enable_reg_reg[0] (\ip_irpt_enable_reg_reg[0] ),
.\ip_irpt_enable_reg_reg[0]_0 (\ip_irpt_enable_reg_reg[0]_0 ),
.ipif_glbl_irpt_enable_reg_reg(ipif_glbl_irpt_enable_reg_reg),
.irpt_rdack(irpt_rdack),
.irpt_rdack_d1(irpt_rdack_d1),
.irpt_wrack(irpt_wrack),
.irpt_wrack_d1(irpt_wrack_d1),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.p_3_in(p_3_in),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.start2(start2));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_awaddr[0]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[0]),
.O(p_1_in__0[2]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_awaddr[1]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[1]),
.O(p_1_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_awaddr[2]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[2]),
.O(p_1_in__0[4]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[5]_i_1
(.I0(s_axi_awaddr[3]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[3]),
.O(p_1_in__0[5]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[6]_i_1
(.I0(s_axi_awaddr[4]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[4]),
.O(p_1_in__0[6]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[7]_i_1
(.I0(s_axi_awaddr[5]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[5]),
.O(p_1_in__0[7]));
LUT5 #(
.INIT(32'hABAAA8AA))
\bus2ip_addr_i[8]_i_1
(.I0(s_axi_awaddr[6]),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_arvalid),
.I4(s_axi_araddr[6]),
.O(p_1_in__0[8]));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[2]),
.Q(bus2ip_addr[6]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[3]),
.Q(bus2ip_addr[5]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[4]),
.Q(bus2ip_addr[4]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[5]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[5]),
.Q(bus2ip_addr[3]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[6]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[6]),
.Q(bus2ip_addr[2]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[7]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[7]),
.Q(bus2ip_addr[1]),
.R(bus2ip_reset));
FDRE \bus2ip_addr_i_reg[8]
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(p_1_in__0[8]),
.Q(bus2ip_addr[0]),
.R(bus2ip_reset));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
bus2ip_rnw_i_i_1
(.I0(s_axi_arvalid),
.I1(state[0]),
.I2(state[1]),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(start2_i_1_n_0),
.D(bus2ip_rnw_i06_out),
.Q(\Not_Dual.gpio_OE_reg[0] ),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(\state[1]_i_2_n_0 ),
.I2(state[1]),
.I3(state[0]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(bus2ip_reset));
LUT6 #(
.INIT(64'h1000FFFF10000000))
is_write_i_1
(.I0(state[1]),
.I1(s_axi_arvalid),
.I2(s_axi_wvalid),
.I3(s_axi_awvalid),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.I4(state[1]),
.I5(state[0]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(state[1]),
.I2(state[0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.O(s_axi_bvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_bvalid_i_i_1_n_0),
.Q(s_axi_bvalid),
.R(bus2ip_reset));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(s_axi_rdata_i));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [0]),
.Q(s_axi_rdata[0]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [1]),
.Q(s_axi_rdata[1]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [2]),
.Q(s_axi_rdata[2]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [5]),
.Q(s_axi_rdata[5]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [3]),
.Q(s_axi_rdata[3]),
.R(bus2ip_reset));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(s_axi_rdata_i),
.D(\ip2bus_data_i_D1_reg[0]_1 [4]),
.Q(s_axi_rdata[4]),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid),
.O(s_axi_rvalid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_axi_rvalid_i_i_1_n_0),
.Q(s_axi_rvalid),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[0]),
.I4(state[1]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(bus2ip_reset));
LUT5 #(
.INIT(32'h0FFFAACC))
\state[0]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arvalid),
.I2(\state[1]_i_2_n_0 ),
.I3(state[1]),
.I4(state[0]),
.O(p_0_out__0[0]));
LUT6 #(
.INIT(64'h2E2E2E2ECCCCFFCC))
\state[1]_i_1
(.I0(s_axi_arready),
.I1(state[1]),
.I2(\state[1]_i_2_n_0 ),
.I3(\state[1]_i_3_n_0 ),
.I4(s_axi_arvalid),
.I5(state[0]),
.O(p_0_out__0[1]));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(\state[1]_i_2_n_0 ));
LUT2 #(
.INIT(4'h8))
\state[1]_i_3
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out__0[0]),
.Q(state[0]),
.R(bus2ip_reset));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(p_0_out__0[1]),
.Q(state[1]),
.R(bus2ip_reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Verilog testbench template generated by SCUBA Diamond (64-bit) 3.4.0.80
`timescale 1 ns / 1 ps
module tb;
reg [13:0] WrAddress = 14'b0;
reg [13:0] RdAddress = 14'b0;
reg [7:0] Data = 8'b0;
reg WE = 0;
reg RdClock = 0;
reg RdClockEn = 0;
reg Reset = 0;
reg WrClock = 0;
reg WrClockEn = 0;
wire [7:0] Q;
integer i0 = 0, i1 = 0, i2 = 0, i3 = 0, i4 = 0, i5 = 0, i6 = 0, i7 = 0, i8 = 0, i9 = 0;
GSR GSR_INST (.GSR(1'b1));
PUR PUR_INST (.PUR(1'b1));
ram u1 (.WrAddress(WrAddress), .RdAddress(RdAddress), .Data(Data), .WE(WE),
.RdClock(RdClock), .RdClockEn(RdClockEn), .Reset(Reset), .WrClock(WrClock),
.WrClockEn(WrClockEn), .Q(Q)
);
initial
begin
WrAddress <= 0;
#100;
@(Reset == 1'b0);
for (i1 = 0; i1 < 32774; i1 = i1 + 1) begin
@(posedge WrClock);
#1 WrAddress <= WrAddress + 1'b1;
end
end
initial
begin
RdAddress <= 0;
#100;
@(Reset == 1'b0);
for (i2 = 0; i2 < 32774; i2 = i2 + 1) begin
@(posedge RdClock);
#1 RdAddress <= RdAddress + 1'b1;
end
end
initial
begin
Data <= 0;
#100;
@(Reset == 1'b0);
for (i3 = 0; i3 < 16387; i3 = i3 + 1) begin
@(posedge WrClock);
#1 Data <= Data + 1'b1;
end
end
initial
begin
WE <= 1'b0;
@(Reset == 1'b0);
for (i4 = 0; i4 < 16387; i4 = i4 + 1) begin
@(posedge WrClock);
#1 WE <= 1'b1;
end
WE <= 1'b0;
end
always
#5.00 RdClock <= ~ RdClock;
initial
begin
RdClockEn <= 1'b0;
#100;
@(Reset == 1'b0);
RdClockEn <= 1'b1;
end
initial
begin
Reset <= 1'b1;
#100;
Reset <= 1'b0;
end
always
#5.00 WrClock <= ~ WrClock;
initial
begin
WrClockEn <= 1'b0;
#100;
@(Reset == 1'b0);
WrClockEn <= 1'b1;
end
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 05/11/2009
Version 2.0
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of rs_cfg_fe1
//
// Generated
// by: lutscher
// on: Wed Dec 14 16:43:33 2005
// cmd: /home/lutscher/work/MIX/mix_0.pl -strip -nodelta ../../reg_shell.sxc
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: lutscher $
// $Id: rs_cfg_fe1.v,v 1.4 2005/12/14 15:43:56 lutscher Exp $
// $Date: 2005/12/14 15:43:56 $
// $Log: rs_cfg_fe1.v,v $
// Revision 1.4 2005/12/14 15:43:56 lutscher
// updated
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.72 2005/11/30 14:01:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.43 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of rs_cfg_fe1
//
// No user `defines in this module
`define tie0_1_c 1'b0
module rs_cfg_fe1
//
// Generated module rs_cfg_fe1_i
//
(
input wire clk_f20,
input wire res_f20_n_i,
input wire test_i,
input wire [13:0] addr_i,
input wire trans_start,
input wire [31:0] wr_data_i,
input wire rd_wr_i,
output wire [31:0] rd_data_o,
output wire rd_err_o,
output wire trans_done_o,
output wire Cvbsdetect_par_o,
input wire Cvbsdetect_set_p_i,
input wire ycdetect_par_i,
input wire usr_r_test_par_i,
input wire usr_r_test_trans_done_p_i,
output reg usr_r_test_rd_p_o,
input wire [7:0] sha_r_test_par_i,
output wire [4:0] mvstart_par_o,
output reg [5:0] mvstop_par_o,
output wire [3:0] usr_rw_test_par_o,
input wire [3:0] usr_rw_test_par_i,
input wire usr_rw_test_trans_done_p_i,
output reg usr_rw_test_rd_p_o,
output reg usr_rw_test_wr_p_o,
output reg [31:0] sha_rw2_par_o,
output wire [15:0] wd_16_test_par_o,
output wire [7:0] wd_16_test2_par_o,
input wire upd_rw_en_i,
input wire upd_rw_force_i,
input wire upd_rw_i,
input wire upd_r_en_i,
input wire upd_r_force_i,
input wire upd_r_i
);
// Module parameters:
parameter sync = 0;
parameter cgtransp = 0;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire int_upd_r_p;
wire int_upd_rw_p;
wire tie0_1;
wire u10_ccgc_ishdw_clk;
wire u10_ccgc_ishdw_clk_en;
wire u11_ccgc_ird_clk;
wire u11_ccgc_ird_clk_en;
wire u7_sync_generic_i_trans_start_p;
wire u8_sync_rst_i_int_rst_n;
wire u9_ccgc_iwr_clk;
wire u9_ccgc_iwr_clk_en;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign tie0_1 = `tie0_1_c;
/*
Generator information:
used package Micronas::Reg is version 1.16
this module is version 1.20
*/
/*
local definitions
*/
`define REG_00_OFFS 0 // reg_0x0
`define REG_04_OFFS 1 // reg_0x4
`define REG_08_OFFS 2 // reg_0x8
`define REG_0C_OFFS 3 // reg_0xC
`define REG_10_OFFS 4 // reg_0x10
`define REG_14_OFFS 5 // reg_0x14
`define REG_18_OFFS 6 // reg_0x18
`define REG_1C_OFFS 7 // reg_0x1C
`define REG_20_OFFS 8 // reg_0x20
`define REG_28_OFFS 10 // reg_0x28
/*
local wire or register declarations
*/
reg [31:0] REG_00;
reg [31:0] REG_04;
reg [31:0] REG_08;
reg [7:0] sha_r_test_shdw;
reg [31:0] REG_0C;
wire [5:0] mvstop_shdw;
reg [31:0] REG_10;
reg [31:0] REG_14;
wire [31:0] sha_rw2_shdw;
reg [31:0] REG_18;
reg [31:0] REG_1C;
reg [31:0] REG_20;
reg [31:0] REG_28;
reg int_upd_rw;
reg int_upd_r;
wire wr_p;
wire rd_p;
reg int_trans_done;
wire [3:0] iaddr;
wire addr_overshoot;
wire trans_done_p;
reg rd_done_p;
reg wr_done_p;
reg fwd_txn;
wire [1:0] fwd_decode_vec;
wire [1:0] fwd_done_vec;
reg [31:0] mux_rd_data;
reg mux_rd_err;
reg [31:0] mux_rd_data_0_0;
reg mux_rd_err_0_0;
reg [31:0] mux_rd_data_0_1;
reg mux_rd_err_0_1;
/*
local wire and output assignments
*/
assign Cvbsdetect_par_o = REG_04[0];
assign mvstop_shdw = REG_0C[10:5];
assign mvstart_par_o = REG_0C[4:0];
assign sha_rw2_shdw = REG_14;
assign wd_16_test_par_o = REG_18[15:0];
assign wd_16_test2_par_o = REG_1C[7:0];
assign usr_rw_test_par_o = wr_data_i[14:11];
// clip address to decoded range
assign iaddr = addr_i[5:2];
assign addr_overshoot = |addr_i[13:6];
/*
clock enable signals
*/
assign u9_ccgc_iwr_clk_en = wr_p; // write-clock enable
assign u10_ccgc_ishdw_clk_en = int_upd_rw | int_upd_r; // shadow-clock enable
assign u11_ccgc_ird_clk_en = rd_p; // read-clock enable
// write txn start pulse
assign wr_p = ~rd_wr_i & u7_sync_generic_i_trans_start_p;
// read txn start pulse
assign rd_p = rd_wr_i & u7_sync_generic_i_trans_start_p;
/*
generate txn done signals
*/
assign fwd_done_vec = {usr_r_test_trans_done_p_i, usr_rw_test_trans_done_p_i}; // ack for forwarded txns
assign trans_done_p = ((wr_done_p | rd_done_p) & ~fwd_txn) | ((fwd_done_vec != 0) & fwd_txn);
always @(posedge clk_f20 or negedge u8_sync_rst_i_int_rst_n) begin
if (~u8_sync_rst_i_int_rst_n) begin
int_trans_done <= 0;
wr_done_p <= 0;
rd_done_p <= 0;
end
else begin
wr_done_p <= wr_p;
rd_done_p <= rd_p;
if (trans_done_p)
int_trans_done <= ~int_trans_done;
end
end
assign trans_done_o = int_trans_done;
/*
write process
*/
always @(posedge u9_ccgc_iwr_clk or negedge u8_sync_rst_i_int_rst_n) begin
if (~u8_sync_rst_i_int_rst_n) begin
REG_0C[10:5] <= 'hc;
REG_0C[4:0] <= 'h7;
REG_14 <= 'h0;
REG_18[15:0] <= 'ha;
REG_1C[7:0] <= 'hff;
end
else begin
case (iaddr)
`REG_0C_OFFS: begin
REG_0C[10:5] <= wr_data_i[10:5];
REG_0C[4:0] <= wr_data_i[4:0];
end
`REG_14_OFFS: begin
REG_14 <= wr_data_i;
end
`REG_18_OFFS: begin
REG_18[15:0] <= wr_data_i[15:0];
end
`REG_1C_OFFS: begin
REG_1C[7:0] <= wr_data_i[7:0];
end
endcase
end
end
/*
write process for status registers
*/
always @(posedge clk_f20 or negedge u8_sync_rst_i_int_rst_n) begin
if (~u8_sync_rst_i_int_rst_n) begin
REG_04[0] <= 'h0;
end
else begin
if (Cvbsdetect_set_p_i)
REG_04[0] <= 1;
else if (wr_p && iaddr == `REG_04_OFFS)
REG_04[0] <= REG_04[0] & ~wr_data_i[0];
end
end
/*
txn forwarding process
*/
// decode addresses of USR registers and read/write
assign fwd_decode_vec = {(iaddr == `REG_08_OFFS) & rd_wr_i, (iaddr == `REG_10_OFFS)};
always @(posedge clk_f20 or negedge u8_sync_rst_i_int_rst_n) begin
if (~u8_sync_rst_i_int_rst_n) begin
fwd_txn <= 0;
usr_r_test_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
end
else begin
usr_r_test_rd_p_o <= 0;
usr_rw_test_rd_p_o <= 0;
usr_rw_test_wr_p_o <= 0;
if (u7_sync_generic_i_trans_start_p) begin
fwd_txn <= |fwd_decode_vec; // set flag for forwarded txn
usr_r_test_rd_p_o <= fwd_decode_vec[1] & rd_wr_i;
usr_rw_test_rd_p_o <= fwd_decode_vec[0] & rd_wr_i;
usr_rw_test_wr_p_o <= fwd_decode_vec[0] & ~rd_wr_i;
end
else if (trans_done_p)
fwd_txn <= 0; // reset flag for forwarded transaction
end
end
/*
shadowing for update signal 'upd_rw'
*/
// generate internal update signal
always @(posedge clk_f20 or negedge u8_sync_rst_i_int_rst_n) begin
if (~u8_sync_rst_i_int_rst_n)
int_upd_rw <= 1;
else
int_upd_rw <= (int_upd_rw_p & upd_rw_en_i) | upd_rw_force_i;
end
// shadow process
always @(posedge u10_ccgc_ishdw_clk) begin
if (int_upd_rw) begin
mvstop_par_o <= mvstop_shdw;
sha_rw2_par_o <= sha_rw2_shdw;
end
end
/*
shadowing for update signal 'upd_r'
*/
// generate internal update signal
always @(posedge clk_f20 or negedge u8_sync_rst_i_int_rst_n) begin
if (~u8_sync_rst_i_int_rst_n)
int_upd_r <= 1;
else
int_upd_r <= (int_upd_r_p & upd_r_en_i) | upd_r_force_i;
end
// shadow process
always @(posedge u10_ccgc_ishdw_clk) begin
if (int_upd_r) begin
sha_r_test_shdw <= sha_r_test_par_i;
end
end
/*
read logic and mux process
*/
assign rd_data_o = mux_rd_data;
assign rd_err_o = mux_rd_err | addr_overshoot;
always @(iaddr or mux_rd_data_0_0 or mux_rd_err_0_0 or mux_rd_data_0_1 or mux_rd_err_0_1) begin // stage 1
case (iaddr[3:2])
0: begin
mux_rd_data <= mux_rd_data_0_0;
mux_rd_err <= mux_rd_err_0_0;
end
1: begin
mux_rd_data <= mux_rd_data_0_1;
mux_rd_err <= mux_rd_err_0_1;
end
default: begin
mux_rd_data <= 0;
mux_rd_err <= 1;
end
endcase
end
always @(posedge u11_ccgc_ird_clk or negedge u8_sync_rst_i_int_rst_n) begin // stage 0
if (~u8_sync_rst_i_int_rst_n) begin
mux_rd_data_0_0 <= 0;
mux_rd_err_0_0 <= 0;
end
else begin
mux_rd_err_0_0 <= 0;
case (iaddr[1:0])
1: begin
mux_rd_data_0_0[0] <= REG_04[0];
end
2: begin
mux_rd_data_0_0[1] <= ycdetect_par_i;
mux_rd_data_0_0[2] <= usr_r_test_par_i;
mux_rd_data_0_0[10:3] <= sha_r_test_shdw;
end
3: begin
mux_rd_data_0_0[4:0] <= REG_0C[4:0];
mux_rd_data_0_0[10:5] <= mvstop_shdw;
end
default: begin
mux_rd_data_0_0 <= 0;
mux_rd_err_0_0 <= 1;
end
endcase
end
end
always @(posedge u11_ccgc_ird_clk or negedge u8_sync_rst_i_int_rst_n) begin // stage 0
if (~u8_sync_rst_i_int_rst_n) begin
mux_rd_data_0_1 <= 0;
mux_rd_err_0_1 <= 0;
end
else begin
mux_rd_err_0_1 <= 0;
case (iaddr[1:0])
0: begin
mux_rd_data_0_1[14:11] <= usr_rw_test_par_i;
end
1: begin
mux_rd_data_0_1 <= sha_rw2_shdw;
end
2: begin
mux_rd_data_0_1[15:0] <= REG_18[15:0];
end
default: begin
mux_rd_data_0_1 <= 0;
mux_rd_err_0_1 <= 1;
end
endcase
end
end
/*
checking code
*/
`ifdef ASSERT_ON
property p_pos_pulse_check (sig); // check for positive pulse
@(posedge clk_f20) disable iff (~u8_sync_rst_i_int_rst_n)
sig |=> ~sig;
endproperty
assert property(p_pos_pulse_check(Cvbsdetect_set_p_i));
assert property(p_pos_pulse_check(usr_r_test_trans_done_p_i));
assert property(p_pos_pulse_check(usr_rw_test_trans_done_p_i));
p_fwd_done_expected: assert property
(
@(posedge clk_f20) disable iff (~u8_sync_rst_i_int_rst_n)
usr_r_test_trans_done_p_i || usr_rw_test_trans_done_p_i |-> fwd_txn
);
p_fwd_done_onehot: assert property
(
@(posedge clk_f20) disable iff (~u8_sync_rst_i_int_rst_n)
usr_r_test_trans_done_p_i || usr_rw_test_trans_done_p_i |-> onehot(fwd_done_vec)
);
p_fwd_done_only_when_fwd_txn: assert property
(
@(posedge clk_f20) disable iff (~u8_sync_rst_i_int_rst_n)
fwd_done_vec != 0 |-> fwd_txn
);
function onehot (input [1:0] vec); // not built-in to SV yet
integer i,j;
begin
j = 0;
for (i=0; i<2; i=i+1) j = j + vec[i] ? 1 : 0;
onehot = (j==1) ? 1 : 0;
end
endfunction
`endif
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for u10_ccgc_i
ccgc #(
.cgtransp(cgtransp) // __W_ILLEGAL_PARAM
) u10_ccgc_i ( // Clock-gating cell for shadow-clock
.clk_i(clk_f20),
.clk_o(u10_ccgc_ishdw_clk),
.enable_i(u10_ccgc_ishdw_clk_en),
.test_i(test_i)
);
// End of Generated Instance Port Map for u10_ccgc_i
// Generated Instance Port Map for u11_ccgc_i
ccgc #(
.cgtransp(cgtransp) // __W_ILLEGAL_PARAM
) u11_ccgc_i ( // Clock-gating cell for read-clock
.clk_i(clk_f20),
.clk_o(u11_ccgc_ird_clk),
.enable_i(u11_ccgc_ird_clk_en),
.test_i(test_i)
);
// End of Generated Instance Port Map for u11_ccgc_i
// Generated Instance Port Map for u12_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u12_sync_generic_i ( // Synchronizer for update-signal upd_rw
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(int_upd_rw_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(upd_rw_i)
);
// End of Generated Instance Port Map for u12_sync_generic_i
// Generated Instance Port Map for u13_sync_generic_i
sync_generic #(
.act(1),
.kind(3),
.rstact(0),
.rstval(0),
.sync(1)
) u13_sync_generic_i ( // Synchronizer for update-signal upd_r
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(int_upd_r_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(upd_r_i)
);
// End of Generated Instance Port Map for u13_sync_generic_i
// Generated Instance Port Map for u7_sync_generic_i
sync_generic #(
.act(1),
.kind(2),
.rstact(0),
.rstval(0),
.sync(0)
) u7_sync_generic_i ( // Synchronizer for trans_done signal
.clk_r(clk_f20),
.clk_s(tie0_1),
.rcv_o(u7_sync_generic_i_trans_start_p),
.rst_r(res_f20_n_i),
.rst_s(tie0_1),
.snd_i(trans_start)
);
// End of Generated Instance Port Map for u7_sync_generic_i
// Generated Instance Port Map for u8_sync_rst_i
sync_rst #(
.act(0),
.sync(0)
) u8_sync_rst_i ( // Reset synchronizer
.clk_r(clk_f20),
.rst_i(res_f20_n_i),
.rst_o(u8_sync_rst_i_int_rst_n)
);
// End of Generated Instance Port Map for u8_sync_rst_i
// Generated Instance Port Map for u9_ccgc_i
ccgc #(
.cgtransp(cgtransp) // __W_ILLEGAL_PARAM
) u9_ccgc_i ( // Clock-gating cell for write-clock
.clk_i(clk_f20),
.clk_o(u9_ccgc_iwr_clk),
.enable_i(u9_ccgc_iwr_clk_en),
.test_i(test_i)
);
// End of Generated Instance Port Map for u9_ccgc_i
endmodule
//
// End of Generated Module rtl of rs_cfg_fe1
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: anode_decoder
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: Produces anode patterns to illuminate one digit on the SSD at a time.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module anode_decoder(
anode,
control
);
// ==============================================================================
// Port Declarations
// ==============================================================================
output [3:0] anode;
input [1:0] control;
// ==============================================================================
// Implementation
// ==============================================================================
// Anode Mux
assign anode = (control == 2'b00) ? 4'b1110 :
(control == 2'b01) ? 4'b1101 :
(control == 2'b10) ? 4'b1011 :
4'b0111;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2O_2_V
`define SKY130_FD_SC_HD__A2BB2O_2_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2bb2o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a2bb2o_2 (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2bb2o base (
.X(X),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2O_2_V
|
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//------------------------------------------------------------------------------
// Module Description : top level testbench
`timescale 1ns/10ps
// DEFINES FOR TOP LEVEL TB
`define C_RAND_SEED 0
`define C_CLOCK_PERIOD 13
`define TB_ACTIVE_EDGE "rise"
`define TB_DRIVE_DELAY 2
`define TB_OUTPUT_FILE 0
`define C_CLOCK_PERIOD_AXI 10
`define C_S_AXI_CLK_FREQ_HZ 100000000
`define C_ACTIVE_COLS 1920
`define C_ACTIVE_ROWS 1080
`define C_ACTIVE_SIZE (`C_ACTIVE_ROWS<<16)+ `C_ACTIVE_COLS
`define C_HAS_INTC_IF 0
`define C_HAS_AXI4_LITE 0
`define C_AXI4LITE_AWIDTH 9
`define C_AXI4LITE_DWIDTH 32
`define C_AXIS_MST_TDATA_WIDTH 8
`define C_AXIS_SLV_TDATA_WIDTH 24
`define TB_STIMULI_TYPE 0 // 0 = RAMP DATA, 1 = CMODEL GENERATED FILE
`define STIMULI_FILE_NAME "EMPTY"
module tb_tutorial_v_cfa_0_0;
//REG & DRIVERS
reg tb_clk;
reg tb_sclr;
wire tb_sclr_n;
wire tb_ce;
reg tb_clk_axi;
reg tb_sclr_axi;
wire tb_sclr_n_axi;
wire tb_ce_axi;
reg EOS;
reg EOS_VIDEO;
reg EOS_AXI;
integer clock_period = `C_CLOCK_PERIOD;
integer clock_period_axi = `C_CLOCK_PERIOD_AXI;
integer rseed = `C_RAND_SEED;
integer total_errors = 0;
//AXI4-STREAM VIDEO MASTER WIRES
wire [`C_AXIS_MST_TDATA_WIDTH-1:0] m_video_data_w;
wire m_ready_w;
wire m_valid_w;
wire m_sof_w;
wire m_eol_w;
wire m_EOF_w;
wire [`C_AXIS_MST_TDATA_WIDTH/8-1:0] m_tstrb_w;
wire [`C_AXIS_MST_TDATA_WIDTH/8-1:0] m_tkeep_w;
wire m_tdest_w;
wire m_tid_w;
//AXI4-STREAM VIDEO SLAVE WIRES
wire [`C_AXIS_SLV_TDATA_WIDTH-1:0] s_video_data_w;
wire s_ready_w;
wire s_valid_w;
wire s_sof_w;
wire s_eol_w;
wire s_EOF_w;
wire [31:0] s_error_count_w;
//AXI4-LITE MASTER WIRES
wire m_awready_w;
wire m_awvalid_w;
wire [`C_AXI4LITE_AWIDTH-1:0] m_awaddr_w;
wire [2:0] m_awprot_w;
wire m_wready_w;
wire m_wvalid_w;
wire [`C_AXI4LITE_DWIDTH-1:0] m_wdata_w;
wire [(`C_AXI4LITE_DWIDTH/8)-1:0] m_wstrb_w;
wire m_bvalid_w;
wire [1:0] m_bresp_w;
wire m_bready_w;
wire m_arready_w;
wire m_arvalid_w;
wire [`C_AXI4LITE_AWIDTH-1:0] m_araddr_w;
wire [2:0] m_arprot_w;
wire m_rvalid_w;
wire [`C_AXI4LITE_DWIDTH-1:0] m_rdata_w;
wire [1:0] m_rresp_w;
wire m_rready_w;
reg [`C_AXI4LITE_DWIDTH-1:0] reg_data;
//INTERRUPT WIRE
wire irq_w;
//INTC_IF WIRE
wire [8:0] intc_if_w;
// uut INSTANCE
tutorial_v_cfa_0_0 uut
(
.aclk (tb_clk),
.aresetn (tb_sclr_n),
.aclken (tb_ce),
.s_axis_video_tready (m_ready_w),
.s_axis_video_tdata (m_video_data_w),
.s_axis_video_tvalid (m_valid_w),
.s_axis_video_tlast (m_eol_w),
.s_axis_video_tuser (m_sof_w),
.m_axis_video_tready (s_ready_w),
.m_axis_video_tdata (s_video_data_w),
.m_axis_video_tvalid (s_valid_w),
.m_axis_video_tlast (s_eol_w),
.m_axis_video_tuser (s_sof_w)
);
//CE (clock enable) GENERATOR INSTANCE
ce_gen CE_GEN
(
.clk_in (tb_clk),
.sclr_in (tb_sclr),
.ce_out (tb_ce)
);
//CE GENERATOR INSTANCE FOR AXI4LITE
ce_gen CE_GEN_AXI
(
.clk_in (tb_clk_axi),
.sclr_in (tb_sclr_axi),
//.ce_out (tb_ce_axi)
.ce_out ( )
);
assign tb_ce_axi = 1;
//AXI4-LITE MASTER INSTANCE
axi4lite_mst
#(
.module_id ("AXI4-LITE MASTER 1"),
.drive_edge (`TB_ACTIVE_EDGE),
.datawidth (`C_AXI4LITE_DWIDTH),
.addrwidth (`C_AXI4LITE_AWIDTH),
.drive_dly (`TB_DRIVE_DELAY)
) AXI4LITE_MST (
.aclk (tb_clk_axi),
.aclken (tb_ce_axi),
.aresetn (tb_sclr_n_axi),
.awready (m_awready_w),
.awvalid (m_awvalid_w),
.awaddr (m_awaddr_w),
.awprot (m_awprot_w),
.wready (m_wready_w),
.wvalid (m_wvalid_w),
.wdata (m_wdata_w),
.wstrb (m_wstrb_w),
.bvalid (m_bvalid_w),
.bresp (m_bresp_w),
.bready (m_bready_w),
.arready (m_arready_w),
.arvalid (m_arvalid_w),
.araddr (m_araddr_w),
.arprot (m_arprot_w),
.rvalid (m_rvalid_w),
.rdata (m_rdata_w),
.rresp (m_rresp_w),
.rready (m_rready_w)
);
//AXI4-STREAM VIDEO MASTER INSTANCE
axi4s_video_mst
#(
.module_id ("AXI-S Video Master 1"),
.drive_edge (`TB_ACTIVE_EDGE),
.datawidth (`C_AXIS_MST_TDATA_WIDTH),
.drive_dly (`TB_DRIVE_DELAY)
) MST (
.aclk (tb_clk),
.aclken (tb_ce),
.aresetn (tb_sclr_n),
.tready (m_ready_w),
.tdata (m_video_data_w),
.tvalid (m_valid_w),
.tstrb (m_tstrb_w),
.tkeep (m_tkeep_w),
.tdest (m_tdest_w),
.tid (m_tid_w),
.sof (m_sof_w),
.eol (m_eol_w),
.EOF (m_EOF_w)
);
//AXI4-STREAM VIDEO SLAVE INSTANCE
axi4s_video_slv
#(
.module_id ("AXI-S Video Slave 1"),
.drive_edge (`TB_ACTIVE_EDGE),
.datawidth (`C_AXIS_SLV_TDATA_WIDTH),
.output_file (`TB_OUTPUT_FILE),
.drive_dly (`TB_DRIVE_DELAY)
) SLV (
.aclk (tb_clk),
.aclken (tb_ce),
.aresetn (tb_sclr_n),
.tready (s_ready_w),
.tdata (s_video_data_w),
.tvalid (s_valid_w),
.sof (s_sof_w),
.eol (s_eol_w),
.error_count (s_error_count_w),
.EOF (s_EOF_w)
);
assign tb_sclr_n = ~tb_sclr;
assign tb_sclr_n_axi = ~tb_sclr_axi;
//================================================
// TESTBENCH TASK TO WAIT for "clk_period" CYCLES
//================================================
task wait_cycle;
input integer wait_length;
begin
#(clock_period * wait_length);
end
endtask
//======================
// TESTBENCH RESET TASK
//======================
task reset;
input integer reset_length;
begin
tb_sclr = 1'b1;
tb_sclr_axi = 1'b1;
$display("@%10t : TB_TOP : SYSTEM RESET ASSERTED!", $time);
wait_cycle(reset_length);
tb_sclr = 1'b0;
tb_sclr_axi = 1'b0;
$display("@%10t : TB_TOP : SYSTEM RESET DEASSERTED!", $time);
wait_cycle(1);
end
endtask
//==========================
// TESTBENCH CLK GENERATION
//==========================
initial
begin
tb_clk = 0;
tb_sclr = 0;
EOS = 0;
EOS_VIDEO = 0;
while (1)
begin
#(clock_period/2);
if((!EOS)&&(!EOS_VIDEO)) tb_clk = ~tb_clk;
end
end
initial
begin
tb_clk_axi = 0;
tb_sclr_axi = 0;
EOS_AXI = 0;
while (1)
begin
#(clock_period_axi/2);
if((!EOS)&&(!EOS_AXI)) tb_clk_axi = ~tb_clk_axi;
end
end
task test_summary;
begin
total_errors = total_errors + s_error_count_w;
if(total_errors > 0)
begin
$display("*******************************");
$display("** TEST FAILED !!!");
$display("** TOTAL ERRORS = %d", total_errors);
$display("*******************************");
end
else
begin
$display("\n***********************");
$display("** TEST PASSED **");
$display("***********************\n");
$display(" Test completed successfully \n");
end
EOS = 1;
$finish;
end
endtask
task test_sequence;
begin
reset(100);
wait_cycle(50);
// if (`TB_STIMULI_TYPE == 0)
// begin
MST.is_ramp_gen(`C_ACTIVE_ROWS, `C_ACTIVE_COLS, 2);
// end
// if (`TB_STIMULI_TYPE == 1)
// begin
// MST.use_file(`STIMULI_FILE_NAME);
// end
SLV.is_passive;
CE_GEN.start;
wait_cycle(50);
MST.set_timeout(`C_ACTIVE_COLS * 7);
MST.start;
SLV.start;
wait(m_EOF_w ==1);
wait_cycle(10);
MST.stop;
SLV.stop;
wait_cycle(10);
$display("TEST END :");
end
endtask
//=========================
// TEST FLOW
//=========================
initial
begin
$display("TEST BEGIN :");
test_sequence;
test_summary;
$display("TEST END :");
end
endmodule //END OF TESTBENCH
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_BLACKBOX_V
`define SKY130_FD_SC_HS__A21BO_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_BLACKBOX_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:57:31 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188,
n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210,
n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221,
n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232,
n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254,
n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265,
n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276,
n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287,
n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298,
n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309,
n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320,
n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331,
n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342,
n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353,
n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364,
n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386,
n387, n388, n389;
XOR2X2TS U35 ( .A(n190), .B(n189), .Y(res[28]) );
NAND2X1TS U36 ( .A(n55), .B(n205), .Y(n189) );
NAND2X1TS U37 ( .A(n54), .B(n219), .Y(n220) );
NAND2X1TS U38 ( .A(n202), .B(n204), .Y(n193) );
NAND2X1TS U39 ( .A(n52), .B(n229), .Y(n215) );
NAND2XLTS U40 ( .A(n283), .B(n282), .Y(n284) );
NAND2X1TS U41 ( .A(n199), .B(n198), .Y(n200) );
NAND2X1TS U42 ( .A(n252), .B(n251), .Y(n253) );
NAND2XLTS U43 ( .A(n50), .B(n263), .Y(n264) );
NAND2X1TS U44 ( .A(n257), .B(n256), .Y(n258) );
NAND2XLTS U45 ( .A(n273), .B(n272), .Y(n274) );
NAND2XLTS U46 ( .A(n245), .B(n244), .Y(n246) );
OA21X1TS U47 ( .A0(n237), .A1(n241), .B0(n238), .Y(n6) );
NAND2X6TS U48 ( .A(n9), .B(n241), .Y(n8) );
OAI21X2TS U49 ( .A0(n259), .A1(n255), .B0(n256), .Y(n254) );
AOI21X2TS U50 ( .A0(n268), .A1(n51), .B0(n262), .Y(n265) );
OAI21X1TS U51 ( .A0(n280), .A1(n276), .B0(n277), .Y(n275) );
NAND2X4TS U52 ( .A(n7), .B(n235), .Y(n31) );
INVX2TS U53 ( .A(n261), .Y(n268) );
INVX2TS U54 ( .A(n270), .Y(n280) );
CLKBUFX2TS U55 ( .A(n293), .Y(n301) );
NOR2X2TS U56 ( .A(n237), .B(n236), .Y(n235) );
INVX2TS U57 ( .A(n236), .Y(n242) );
CLKBUFX2TS U58 ( .A(n269), .Y(n270) );
MX2X2TS U59 ( .A(in2[31]), .B(n224), .S0(add_sub), .Y(n234) );
CLKMX2X2TS U60 ( .A(in2[30]), .B(n227), .S0(n323), .Y(n233) );
NAND2X1TS U61 ( .A(n214), .B(in1[29]), .Y(n229) );
OR2X2TS U62 ( .A(n326), .B(in1[4]), .Y(n332) );
NAND2BX1TS U63 ( .AN(in2[29]), .B(n222), .Y(n225) );
OR2X4TS U64 ( .A(n188), .B(in1[28]), .Y(n55) );
NAND2X2TS U65 ( .A(n159), .B(in1[22]), .Y(n256) );
NAND2X2TS U66 ( .A(n160), .B(in1[23]), .Y(n251) );
CLKMX2X2TS U67 ( .A(in2[29]), .B(n213), .S0(n226), .Y(n214) );
NAND2X2TS U68 ( .A(n180), .B(in1[26]), .Y(n219) );
NAND2X1TS U69 ( .A(in1[0]), .B(in2[0]), .Y(n388) );
NAND2X2TS U70 ( .A(n179), .B(in1[25]), .Y(n198) );
NAND2X2TS U71 ( .A(n188), .B(in1[28]), .Y(n205) );
CLKMX2X4TS U72 ( .A(in2[27]), .B(n177), .S0(n226), .Y(n182) );
OAI21X2TS U73 ( .A0(n271), .A1(n277), .B0(n272), .Y(n138) );
NOR2X4TS U74 ( .A(in1[19]), .B(n137), .Y(n271) );
NOR2X6TS U75 ( .A(n179), .B(in1[25]), .Y(n197) );
NOR2X4TS U76 ( .A(n136), .B(in1[18]), .Y(n276) );
NOR2X2TS U77 ( .A(n178), .B(in1[24]), .Y(n195) );
NAND2X2TS U78 ( .A(n137), .B(in1[19]), .Y(n272) );
NOR2X1TS U79 ( .A(n155), .B(n163), .Y(n156) );
INVX2TS U80 ( .A(n282), .Y(n24) );
NAND2X1TS U81 ( .A(n143), .B(in2[19]), .Y(n131) );
XOR2X1TS U82 ( .A(n142), .B(in2[21]), .Y(n145) );
XNOR2X1TS U83 ( .A(n155), .B(in2[20]), .Y(n146) );
INVX2TS U84 ( .A(n298), .Y(n113) );
CLKINVX2TS U85 ( .A(n212), .Y(n171) );
NAND2X1TS U86 ( .A(n175), .B(n174), .Y(n185) );
OR2X4TS U87 ( .A(n119), .B(in1[15]), .Y(n49) );
NAND2X4TS U88 ( .A(n370), .B(in1[11]), .Y(n371) );
NAND2X2TS U89 ( .A(n104), .B(in1[12]), .Y(n307) );
NOR2X1TS U90 ( .A(in2[25]), .B(in2[24]), .Y(n175) );
INVX2TS U91 ( .A(in2[26]), .Y(n174) );
NAND2X2TS U92 ( .A(n111), .B(in1[14]), .Y(n295) );
CLKINVX6TS U93 ( .A(n294), .Y(n299) );
OR2X4TS U94 ( .A(n111), .B(in1[14]), .Y(n53) );
OR2X2TS U95 ( .A(in2[21]), .B(in2[20]), .Y(n163) );
NAND2X4TS U96 ( .A(n349), .B(in1[7]), .Y(n352) );
XNOR2X2TS U97 ( .A(n95), .B(in2[10]), .Y(n92) );
XNOR2X2TS U98 ( .A(n96), .B(in2[11]), .Y(n97) );
XOR2X2TS U99 ( .A(n118), .B(in2[12]), .Y(n103) );
OR2X4TS U100 ( .A(n339), .B(in1[6]), .Y(n67) );
NOR2X1TS U101 ( .A(in2[19]), .B(in2[18]), .Y(n140) );
NOR2X2TS U102 ( .A(in2[17]), .B(in2[16]), .Y(n141) );
NAND2X1TS U103 ( .A(n143), .B(in2[13]), .Y(n16) );
NAND2X6TS U104 ( .A(n339), .B(in1[6]), .Y(n343) );
NAND2X1TS U105 ( .A(n116), .B(n33), .Y(n32) );
INVX2TS U106 ( .A(in2[14]), .Y(n116) );
INVX2TS U107 ( .A(in2[15]), .Y(n33) );
INVX2TS U108 ( .A(n226), .Y(n143) );
INVX4TS U109 ( .A(n35), .Y(n118) );
NOR2BX2TS U110 ( .AN(n59), .B(n58), .Y(n62) );
NAND3X4TS U111 ( .A(n46), .B(n43), .C(n42), .Y(n41) );
INVX4TS U112 ( .A(n321), .Y(n43) );
CLKINVX3TS U113 ( .A(n80), .Y(n46) );
NOR3X6TS U114 ( .A(n70), .B(in2[7]), .C(in2[6]), .Y(n78) );
INVX8TS U115 ( .A(in2[0]), .Y(n44) );
INVX6TS U116 ( .A(in2[3]), .Y(n47) );
CLKINVX6TS U117 ( .A(in2[8]), .Y(n91) );
CLKINVX6TS U118 ( .A(in2[9]), .Y(n90) );
NAND2X2TS U119 ( .A(n36), .B(n100), .Y(n13) );
NOR2X2TS U120 ( .A(in2[13]), .B(in2[12]), .Y(n117) );
XNOR2X2TS U121 ( .A(in2[14]), .B(n120), .Y(n107) );
NAND2X2TS U122 ( .A(n283), .B(n288), .Y(n129) );
XOR2X1TS U123 ( .A(n156), .B(in2[22]), .Y(n157) );
BUFX6TS U124 ( .A(add_sub), .Y(n226) );
NOR2X2TS U125 ( .A(n160), .B(in1[23]), .Y(n250) );
CLKMX2X2TS U126 ( .A(in2[28]), .B(n187), .S0(n313), .Y(n188) );
NAND2X1TS U127 ( .A(n315), .B(in1[1]), .Y(n381) );
OAI21X2TS U128 ( .A0(n335), .A1(n334), .B0(n333), .Y(n347) );
OR2X1TS U129 ( .A(n370), .B(in1[11]), .Y(n372) );
NAND2X1TS U130 ( .A(n119), .B(in1[15]), .Y(n291) );
NAND2X2TS U131 ( .A(n178), .B(in1[24]), .Y(n244) );
OR2X1TS U132 ( .A(in1[0]), .B(in2[0]), .Y(n389) );
OAI21XLTS U133 ( .A0(n338), .A1(n342), .B0(n344), .Y(n341) );
AOI21X1TS U134 ( .A0(n369), .A1(n368), .B0(n367), .Y(n379) );
NAND2X1TS U135 ( .A(n278), .B(n277), .Y(n279) );
INVX2TS U136 ( .A(n4), .Y(n5) );
INVX2TS U137 ( .A(n286), .Y(n4) );
NOR2X2TS U138 ( .A(n60), .B(n70), .Y(n59) );
XOR2X1TS U139 ( .A(n265), .B(n264), .Y(res[21]) );
INVX4TS U140 ( .A(n249), .Y(n259) );
NAND2X4TS U141 ( .A(n248), .B(n162), .Y(n40) );
NOR2X6TS U142 ( .A(n27), .B(n293), .Y(n25) );
OR2X4TS U143 ( .A(n214), .B(in1[29]), .Y(n52) );
CLKAND2X2TS U144 ( .A(n389), .B(n388), .Y(res[0]) );
NAND2X4TS U145 ( .A(n202), .B(n55), .Y(n209) );
NAND2X4TS U146 ( .A(n218), .B(n54), .Y(n203) );
INVX2TS U147 ( .A(n204), .Y(n207) );
NAND2X4TS U148 ( .A(n233), .B(in1[30]), .Y(n241) );
NOR2X4TS U149 ( .A(n182), .B(in1[27]), .Y(n192) );
XNOR2X1TS U150 ( .A(n153), .B(in2[23]), .Y(n154) );
NOR2X2TS U151 ( .A(n212), .B(n211), .Y(n186) );
NOR2X2TS U152 ( .A(n212), .B(n185), .Y(n176) );
NOR2X2TS U153 ( .A(n155), .B(in2[20]), .Y(n142) );
OR2X4TS U154 ( .A(n185), .B(in2[27]), .Y(n211) );
NOR4X2TS U155 ( .A(n164), .B(n163), .C(in2[23]), .D(in2[22]), .Y(n165) );
NAND2X6TS U156 ( .A(n45), .B(n44), .Y(n321) );
NOR4X2TS U157 ( .A(in2[1]), .B(in2[5]), .C(in2[7]), .D(in2[6]), .Y(n81) );
INVX2TS U158 ( .A(n237), .Y(n239) );
INVX2TS U159 ( .A(n250), .Y(n252) );
INVX2TS U160 ( .A(n205), .Y(n206) );
OA21X4TS U161 ( .A0(n250), .A1(n256), .B0(n251), .Y(n161) );
OR2X6TS U162 ( .A(n180), .B(in1[26]), .Y(n54) );
INVX2TS U163 ( .A(n49), .Y(n29) );
OR2X4TS U164 ( .A(n149), .B(in1[21]), .Y(n50) );
NOR2X4TS U165 ( .A(n159), .B(in1[22]), .Y(n255) );
NAND2X2TS U166 ( .A(n171), .B(n175), .Y(n172) );
INVX2TS U167 ( .A(n295), .Y(n112) );
XNOR2X1TS U168 ( .A(n176), .B(in2[27]), .Y(n177) );
NOR2X4TS U169 ( .A(n121), .B(in2[16]), .Y(n122) );
NOR3X2TS U170 ( .A(n155), .B(in2[22]), .C(n163), .Y(n153) );
INVX2TS U171 ( .A(n99), .Y(n100) );
CLKAND2X2TS U172 ( .A(n117), .B(n116), .Y(n21) );
INVX2TS U173 ( .A(in2[18]), .Y(n135) );
NAND2X2TS U174 ( .A(n239), .B(n238), .Y(n240) );
INVX4TS U175 ( .A(n203), .Y(n3) );
NOR2X4TS U176 ( .A(n233), .B(in1[30]), .Y(n236) );
INVX4TS U177 ( .A(n192), .Y(n202) );
INVX2TS U178 ( .A(n229), .Y(n230) );
NAND2X4TS U179 ( .A(n127), .B(in1[17]), .Y(n282) );
INVX2TS U180 ( .A(n195), .Y(n245) );
NAND2X4TS U181 ( .A(n182), .B(in1[27]), .Y(n204) );
NAND2X4TS U182 ( .A(n53), .B(n299), .Y(n115) );
INVX4TS U183 ( .A(n281), .Y(n288) );
NAND2X4TS U184 ( .A(n136), .B(in1[18]), .Y(n277) );
NOR2X4TS U185 ( .A(in1[13]), .B(n15), .Y(n294) );
NOR2X4TS U186 ( .A(n126), .B(in1[16]), .Y(n281) );
NOR3X4TS U187 ( .A(n212), .B(in2[28]), .C(n211), .Y(n222) );
NOR2X2TS U188 ( .A(n133), .B(in2[18]), .Y(n130) );
NOR2X4TS U189 ( .A(n93), .B(in1[10]), .Y(n375) );
NOR2X4TS U190 ( .A(n95), .B(in2[10]), .Y(n96) );
MX2X2TS U191 ( .A(in2[3]), .B(n324), .S0(n226), .Y(n325) );
NAND2X4TS U192 ( .A(n41), .B(add_sub), .Y(n56) );
NOR2X2TS U193 ( .A(n315), .B(in1[1]), .Y(n380) );
NOR2X2TS U194 ( .A(n321), .B(in2[2]), .Y(n322) );
INVX12TS U195 ( .A(n232), .Y(n247) );
XNOR2X1TS U196 ( .A(n275), .B(n274), .Y(res[19]) );
XOR2X1TS U197 ( .A(n280), .B(n279), .Y(res[18]) );
OAI21X1TS U198 ( .A0(n5), .A1(n281), .B0(n287), .Y(n285) );
INVX2TS U199 ( .A(n210), .Y(n191) );
NAND2X2TS U200 ( .A(n242), .B(n241), .Y(n243) );
XOR2X1TS U201 ( .A(n301), .B(n300), .Y(res[13]) );
OAI21X1TS U202 ( .A0(n305), .A1(n304), .B0(n371), .Y(n310) );
OAI21X1TS U203 ( .A0(n294), .A1(n301), .B0(n298), .Y(n297) );
INVX2TS U204 ( .A(n219), .Y(n181) );
INVX2TS U205 ( .A(n271), .Y(n273) );
INVX3TS U206 ( .A(n115), .Y(n28) );
NAND2X2TS U207 ( .A(n50), .B(n51), .Y(n152) );
NAND2X1TS U208 ( .A(n288), .B(n287), .Y(n289) );
NOR2X6TS U209 ( .A(n127), .B(in1[17]), .Y(n128) );
XOR2X1TS U210 ( .A(n365), .B(n364), .Y(res[8]) );
XOR2X1TS U211 ( .A(n379), .B(n378), .Y(res[10]) );
OR2X4TS U212 ( .A(n148), .B(in1[20]), .Y(n51) );
NOR2X2TS U213 ( .A(n225), .B(in2[30]), .Y(n223) );
NOR2X4TS U214 ( .A(n304), .B(n306), .Y(n106) );
NAND2X4TS U215 ( .A(n126), .B(in1[16]), .Y(n287) );
XNOR2X2TS U216 ( .A(n122), .B(in2[17]), .Y(n123) );
XOR2X1TS U217 ( .A(n338), .B(n337), .Y(res[5]) );
XOR2X1TS U218 ( .A(n328), .B(n327), .Y(res[4]) );
NAND2X2TS U219 ( .A(n19), .B(n226), .Y(n18) );
XOR2X2TS U220 ( .A(n109), .B(in2[13]), .Y(n110) );
XOR2X2TS U221 ( .A(n20), .B(in2[15]), .Y(n19) );
NOR2X6TS U222 ( .A(n370), .B(in1[11]), .Y(n304) );
NAND2X2TS U223 ( .A(n118), .B(n108), .Y(n109) );
NAND2X4TS U224 ( .A(n93), .B(in1[10]), .Y(n376) );
NAND2X6TS U225 ( .A(n57), .B(in1[5]), .Y(n344) );
OR2X2TS U226 ( .A(n351), .B(in1[8]), .Y(n363) );
NAND2X4TS U227 ( .A(n351), .B(in1[8]), .Y(n362) );
NAND2X6TS U228 ( .A(n65), .B(n64), .Y(n339) );
OR2X2TS U229 ( .A(n325), .B(in1[3]), .Y(n385) );
NAND2X2TS U230 ( .A(n325), .B(in1[3]), .Y(n384) );
XOR2XLTS U231 ( .A(n383), .B(n388), .Y(res[1]) );
NAND2X2TS U232 ( .A(n312), .B(in1[2]), .Y(n317) );
OR2X2TS U233 ( .A(n312), .B(in1[2]), .Y(n319) );
NOR2X4TS U234 ( .A(n62), .B(n61), .Y(n65) );
OAI31X2TS U235 ( .A0(n321), .A1(n70), .A2(in2[6]), .B0(n63), .Y(n64) );
NAND2X2TS U236 ( .A(n141), .B(n140), .Y(n164) );
INVX2TS U237 ( .A(n117), .Y(n34) );
XNOR2X2TS U238 ( .A(n222), .B(in2[29]), .Y(n213) );
NAND2X4TS U239 ( .A(n326), .B(in1[4]), .Y(n329) );
NAND2X4TS U240 ( .A(n58), .B(n226), .Y(n74) );
OAI21X2TS U241 ( .A0(n380), .A1(n388), .B0(n381), .Y(n320) );
XNOR2X2TS U242 ( .A(n130), .B(in2[19]), .Y(n132) );
AND2X4TS U243 ( .A(n102), .B(n101), .Y(n36) );
NAND2X8TS U244 ( .A(n166), .B(n165), .Y(n212) );
INVX8TS U245 ( .A(n39), .Y(n232) );
NOR2X2TS U246 ( .A(n250), .B(n255), .Y(n162) );
NAND2X4TS U247 ( .A(n91), .B(n90), .Y(n99) );
NAND2X4TS U248 ( .A(n18), .B(n17), .Y(n119) );
NAND2X4TS U249 ( .A(n28), .B(n49), .Y(n27) );
OAI2BB1X4TS U250 ( .A0N(n323), .A1N(n110), .B0(n16), .Y(n15) );
XNOR2X2TS U251 ( .A(n212), .B(in2[24]), .Y(n169) );
CLKINVX12TS U252 ( .A(n98), .Y(n14) );
NAND2X2TS U253 ( .A(n148), .B(in1[20]), .Y(n266) );
MXI2X8TS U254 ( .A(n174), .B(n173), .S0(n313), .Y(n180) );
XNOR2X1TS U255 ( .A(n133), .B(in2[18]), .Y(n134) );
NAND2X2TS U256 ( .A(n166), .B(n141), .Y(n133) );
MX2X4TS U257 ( .A(in2[23]), .B(n154), .S0(n313), .Y(n160) );
OR2X8TS U258 ( .A(n35), .B(n34), .Y(n120) );
AOI21X4TS U259 ( .A0(n50), .A1(n262), .B0(n150), .Y(n151) );
INVX4TS U260 ( .A(n266), .Y(n262) );
NAND4X8TS U261 ( .A(n47), .B(n45), .C(n48), .D(n44), .Y(n58) );
NAND2X8TS U262 ( .A(n14), .B(n12), .Y(n35) );
CLKINVX6TS U263 ( .A(n13), .Y(n12) );
OAI2BB1X4TS U264 ( .A0N(n323), .A1N(n132), .B0(n131), .Y(n137) );
AOI21X2TS U265 ( .A0(n320), .A1(n319), .B0(n318), .Y(n335) );
BUFX16TS U266 ( .A(add_sub), .Y(n313) );
INVX2TS U267 ( .A(n362), .Y(n353) );
OR2X1TS U268 ( .A(n357), .B(in1[9]), .Y(n368) );
NAND2X1TS U269 ( .A(n332), .B(n385), .Y(n334) );
AOI21X1TS U270 ( .A0(n332), .A1(n331), .B0(n330), .Y(n333) );
INVX2TS U271 ( .A(n329), .Y(n330) );
MXI2X4TS U272 ( .A(n116), .B(n107), .S0(n313), .Y(n111) );
NAND2X1TS U273 ( .A(n143), .B(in2[15]), .Y(n17) );
MX2X4TS U274 ( .A(in2[17]), .B(n123), .S0(n313), .Y(n127) );
NOR2X2TS U275 ( .A(n271), .B(n276), .Y(n139) );
XOR2X1TS U276 ( .A(n225), .B(in2[30]), .Y(n227) );
INVX2TS U277 ( .A(n352), .Y(n359) );
OR2X1TS U278 ( .A(n349), .B(in1[7]), .Y(n360) );
INVX2TS U279 ( .A(n356), .Y(n361) );
INVX2TS U280 ( .A(n366), .Y(n367) );
INVX2TS U281 ( .A(n303), .Y(n305) );
CLKBUFX2TS U282 ( .A(n302), .Y(n303) );
NAND2X4TS U283 ( .A(n15), .B(in1[13]), .Y(n298) );
INVX2TS U284 ( .A(n244), .Y(n196) );
INVX2TS U285 ( .A(in2[6]), .Y(n60) );
NAND2X6TS U286 ( .A(n48), .B(n47), .Y(n80) );
INVX2TS U287 ( .A(in2[7]), .Y(n69) );
CLKINVX6TS U288 ( .A(n58), .Y(n77) );
CLKINVX6TS U289 ( .A(in2[5]), .Y(n30) );
NOR2X4TS U290 ( .A(n357), .B(in1[9]), .Y(n86) );
NOR2X2TS U291 ( .A(n351), .B(in1[8]), .Y(n85) );
NAND2X2TS U292 ( .A(n118), .B(n21), .Y(n20) );
NOR2X2TS U293 ( .A(n209), .B(n38), .Y(n37) );
NAND2X1TS U294 ( .A(n52), .B(n3), .Y(n38) );
XNOR2X1TS U295 ( .A(in2[0]), .B(in2[1]), .Y(n314) );
XNOR2X1TS U296 ( .A(n321), .B(in2[2]), .Y(n311) );
OR2X4TS U297 ( .A(n99), .B(n98), .Y(n95) );
INVX2TS U298 ( .A(n263), .Y(n150) );
XNOR2X1TS U299 ( .A(n223), .B(in2[31]), .Y(n224) );
NAND2X2TS U300 ( .A(n149), .B(in1[21]), .Y(n263) );
CLKBUFX2TS U301 ( .A(n260), .Y(n261) );
CLKBUFX2TS U302 ( .A(n248), .Y(n249) );
NOR2X4TS U303 ( .A(n234), .B(in1[31]), .Y(n237) );
NAND2X2TS U304 ( .A(n234), .B(in1[31]), .Y(n238) );
NAND2X1TS U305 ( .A(n360), .B(n352), .Y(n350) );
INVX2TS U306 ( .A(n375), .Y(n377) );
NAND2X1TS U307 ( .A(n308), .B(n307), .Y(n309) );
INVX2TS U308 ( .A(n306), .Y(n308) );
NAND2X1TS U309 ( .A(n299), .B(n298), .Y(n300) );
NAND2X1TS U310 ( .A(n53), .B(n295), .Y(n296) );
NAND2X1TS U311 ( .A(n49), .B(n291), .Y(n292) );
XNOR2X1TS U312 ( .A(n268), .B(n267), .Y(res[20]) );
NAND2X1TS U313 ( .A(n51), .B(n266), .Y(n267) );
XOR2X1TS U314 ( .A(n259), .B(n258), .Y(res[22]) );
INVX2TS U315 ( .A(n255), .Y(n257) );
XNOR2X1TS U316 ( .A(n247), .B(n246), .Y(res[24]) );
INVX2TS U317 ( .A(n197), .Y(n199) );
OAI21X1TS U318 ( .A0(n210), .A1(n192), .B0(n204), .Y(n183) );
NOR2X1TS U319 ( .A(n209), .B(n203), .Y(n228) );
INVX2TS U320 ( .A(n343), .Y(n66) );
NOR2X8TS U321 ( .A(n26), .B(n25), .Y(n286) );
INVX8TS U322 ( .A(in2[1]), .Y(n45) );
OAI21XLTS U323 ( .A0(n293), .A1(n115), .B0(n114), .Y(n290) );
INVX8TS U324 ( .A(in2[2]), .Y(n48) );
NOR2X1TS U325 ( .A(n339), .B(in1[6]), .Y(n345) );
NOR2X4TS U326 ( .A(n104), .B(in1[12]), .Y(n306) );
NAND2X8TS U327 ( .A(n78), .B(n77), .Y(n98) );
NAND2X2TS U328 ( .A(n82), .B(n81), .Y(n83) );
NAND2X4TS U329 ( .A(n357), .B(in1[9]), .Y(n366) );
MXI2X4TS U330 ( .A(n91), .B(n79), .S0(n323), .Y(n351) );
MXI2X4TS U331 ( .A(n90), .B(n84), .S0(n313), .Y(n357) );
XNOR2X1TS U332 ( .A(n313), .B(in2[7]), .Y(n71) );
XOR2X1TS U333 ( .A(n323), .B(in2[6]), .Y(n63) );
XNOR2X1TS U334 ( .A(n285), .B(n284), .Y(res[17]) );
BUFX12TS U335 ( .A(n22), .Y(n7) );
XNOR2X2TS U336 ( .A(n8), .B(n240), .Y(res[31]) );
NAND2X8TS U337 ( .A(n22), .B(n242), .Y(n9) );
NAND2X8TS U338 ( .A(n11), .B(n10), .Y(n22) );
AOI21X4TS U339 ( .A0(n231), .A1(n52), .B0(n230), .Y(n10) );
NAND2X8TS U340 ( .A(n39), .B(n37), .Y(n11) );
XNOR2X2TS U341 ( .A(n7), .B(n243), .Y(res[30]) );
OAI21X4TS U342 ( .A0(n210), .A1(n209), .B0(n208), .Y(n231) );
NAND2X8TS U343 ( .A(n40), .B(n161), .Y(n39) );
OAI21X4TS U344 ( .A0(n286), .A1(n129), .B0(n23), .Y(n269) );
AOI2BB1X4TS U345 ( .A0N(n128), .A1N(n287), .B0(n24), .Y(n23) );
OAI21X4TS U346 ( .A0(n29), .A1(n114), .B0(n291), .Y(n26) );
AOI21X4TS U347 ( .A0(n269), .A1(n139), .B0(n138), .Y(n260) );
AND3X2TS U348 ( .A(n80), .B(n60), .C(add_sub), .Y(n61) );
NAND2X8TS U349 ( .A(n42), .B(n30), .Y(n70) );
NAND2X2TS U350 ( .A(n31), .B(n6), .Y(res[32]) );
NOR2X8TS U351 ( .A(n120), .B(n32), .Y(n166) );
OAI21X4TS U352 ( .A0(n260), .A1(n152), .B0(n151), .Y(n248) );
INVX12TS U353 ( .A(in2[4]), .Y(n42) );
INVX4TS U354 ( .A(n166), .Y(n121) );
OAI21X4TS U355 ( .A0(n74), .A1(in2[7]), .B0(n73), .Y(n349) );
NOR2X8TS U356 ( .A(n57), .B(in1[5]), .Y(n342) );
OAI21X4TS U357 ( .A0(n356), .A1(n355), .B0(n354), .Y(n369) );
AOI21X4TS U358 ( .A0(n348), .A1(n347), .B0(n346), .Y(n356) );
MXI2X4TS U359 ( .A(n158), .B(n157), .S0(n323), .Y(n159) );
XNOR2X4TS U360 ( .A(n167), .B(in2[25]), .Y(n168) );
NOR2X4TS U361 ( .A(n212), .B(in2[24]), .Y(n167) );
MXI2X4TS U362 ( .A(n170), .B(n169), .S0(n323), .Y(n178) );
MXI2X4TS U363 ( .A(n135), .B(n134), .S0(n313), .Y(n136) );
NOR2X1TS U364 ( .A(n203), .B(n192), .Y(n184) );
NAND2X1TS U365 ( .A(n67), .B(n343), .Y(n340) );
NAND2X1TS U366 ( .A(n372), .B(n371), .Y(n373) );
XNOR2X4TS U367 ( .A(n56), .B(in2[5]), .Y(n57) );
BUFX20TS U368 ( .A(add_sub), .Y(n323) );
XNOR2X4TS U369 ( .A(n74), .B(in2[4]), .Y(n326) );
OAI21X4TS U370 ( .A0(n342), .A1(n329), .B0(n344), .Y(n68) );
AOI21X4TS U371 ( .A0(n68), .A1(n67), .B0(n66), .Y(n76) );
NOR3X1TS U372 ( .A(in2[6]), .B(n70), .C(n69), .Y(n72) );
AOI2BB2X2TS U373 ( .B0(n72), .B1(n77), .A0N(n78), .A1N(n71), .Y(n73) );
NOR2X4TS U374 ( .A(n349), .B(in1[7]), .Y(n75) );
OAI21X4TS U375 ( .A0(n76), .A1(n75), .B0(n352), .Y(n89) );
XNOR2X4TS U376 ( .A(in2[8]), .B(n98), .Y(n79) );
NOR4X4TS U377 ( .A(n80), .B(in2[0]), .C(in2[4]), .D(in2[8]), .Y(n82) );
XNOR2X4TS U378 ( .A(n83), .B(in2[9]), .Y(n84) );
NOR2X4TS U379 ( .A(n85), .B(n86), .Y(n88) );
OAI21X4TS U380 ( .A0(n86), .A1(n362), .B0(n366), .Y(n87) );
AOI21X4TS U381 ( .A0(n89), .A1(n88), .B0(n87), .Y(n94) );
INVX2TS U382 ( .A(in2[10]), .Y(n101) );
MXI2X4TS U383 ( .A(n101), .B(n92), .S0(n323), .Y(n93) );
OAI21X4TS U384 ( .A0(n94), .A1(n375), .B0(n376), .Y(n302) );
MX2X4TS U385 ( .A(in2[11]), .B(n97), .S0(n313), .Y(n370) );
INVX2TS U386 ( .A(in2[12]), .Y(n108) );
INVX2TS U387 ( .A(in2[11]), .Y(n102) );
MXI2X4TS U388 ( .A(n108), .B(n103), .S0(n226), .Y(n104) );
OAI21X4TS U389 ( .A0(n306), .A1(n371), .B0(n307), .Y(n105) );
AOI21X4TS U390 ( .A0(n302), .A1(n106), .B0(n105), .Y(n293) );
AOI21X4TS U391 ( .A0(n53), .A1(n113), .B0(n112), .Y(n114) );
INVX6TS U392 ( .A(n128), .Y(n283) );
INVX2TS U393 ( .A(in2[16]), .Y(n125) );
XOR2X1TS U394 ( .A(n166), .B(in2[16]), .Y(n124) );
MXI2X4TS U395 ( .A(n125), .B(n124), .S0(n323), .Y(n126) );
NAND2BX4TS U396 ( .AN(n164), .B(n166), .Y(n155) );
INVX2TS U397 ( .A(in2[21]), .Y(n144) );
MXI2X4TS U398 ( .A(n145), .B(n144), .S0(n143), .Y(n149) );
INVX2TS U399 ( .A(in2[20]), .Y(n147) );
MXI2X2TS U400 ( .A(n147), .B(n146), .S0(n226), .Y(n148) );
INVX2TS U401 ( .A(in2[22]), .Y(n158) );
MX2X4TS U402 ( .A(in2[25]), .B(n168), .S0(n313), .Y(n179) );
INVX2TS U403 ( .A(in2[24]), .Y(n170) );
NOR2X8TS U404 ( .A(n197), .B(n195), .Y(n218) );
XNOR2X4TS U405 ( .A(n172), .B(in2[26]), .Y(n173) );
OAI21X4TS U406 ( .A0(n197), .A1(n244), .B0(n198), .Y(n217) );
AOI21X4TS U407 ( .A0(n54), .A1(n217), .B0(n181), .Y(n210) );
AOI21X4TS U408 ( .A0(n247), .A1(n184), .B0(n183), .Y(n190) );
XNOR2X1TS U409 ( .A(n186), .B(in2[28]), .Y(n187) );
AOI21X4TS U410 ( .A0(n247), .A1(n3), .B0(n191), .Y(n194) );
XOR2X2TS U411 ( .A(n194), .B(n193), .Y(res[27]) );
AOI21X4TS U412 ( .A0(n247), .A1(n245), .B0(n196), .Y(n201) );
XOR2X2TS U413 ( .A(n201), .B(n200), .Y(res[25]) );
AOI21X4TS U414 ( .A0(n207), .A1(n55), .B0(n206), .Y(n208) );
AOI21X4TS U415 ( .A0(n247), .A1(n228), .B0(n231), .Y(n216) );
XOR2X2TS U416 ( .A(n216), .B(n215), .Y(res[29]) );
AOI21X4TS U417 ( .A0(n247), .A1(n218), .B0(n217), .Y(n221) );
XOR2X2TS U418 ( .A(n221), .B(n220), .Y(res[26]) );
XNOR2X2TS U419 ( .A(n254), .B(n253), .Y(res[23]) );
INVX2TS U420 ( .A(n276), .Y(n278) );
XNOR2X1TS U421 ( .A(n4), .B(n289), .Y(res[16]) );
XNOR2X1TS U422 ( .A(n290), .B(n292), .Y(res[15]) );
XNOR2X1TS U423 ( .A(n297), .B(n296), .Y(res[14]) );
XNOR2X1TS U424 ( .A(n310), .B(n309), .Y(res[12]) );
MXI2X2TS U425 ( .A(n48), .B(n311), .S0(n226), .Y(n312) );
NAND2X1TS U426 ( .A(n319), .B(n317), .Y(n316) );
MXI2X2TS U427 ( .A(n45), .B(n314), .S0(n226), .Y(n315) );
XNOR2X1TS U428 ( .A(n316), .B(n320), .Y(res[2]) );
INVX2TS U429 ( .A(n317), .Y(n318) );
INVX2TS U430 ( .A(n335), .Y(n387) );
XNOR2X1TS U431 ( .A(n322), .B(in2[3]), .Y(n324) );
INVX2TS U432 ( .A(n384), .Y(n331) );
AOI21X1TS U433 ( .A0(n387), .A1(n385), .B0(n331), .Y(n328) );
NAND2X1TS U434 ( .A(n332), .B(n329), .Y(n327) );
INVX2TS U435 ( .A(n347), .Y(n338) );
INVX2TS U436 ( .A(n342), .Y(n336) );
NAND2X1TS U437 ( .A(n336), .B(n344), .Y(n337) );
XNOR2X1TS U438 ( .A(n341), .B(n340), .Y(res[6]) );
NOR2X1TS U439 ( .A(n342), .B(n345), .Y(n348) );
OAI21X1TS U440 ( .A0(n345), .A1(n344), .B0(n343), .Y(n346) );
XNOR2X1TS U441 ( .A(n361), .B(n350), .Y(res[7]) );
NAND2X1TS U442 ( .A(n363), .B(n360), .Y(n355) );
AOI21X1TS U443 ( .A0(n363), .A1(n359), .B0(n353), .Y(n354) );
NAND2X1TS U444 ( .A(n368), .B(n366), .Y(n358) );
XNOR2X1TS U445 ( .A(n369), .B(n358), .Y(res[9]) );
AOI21X1TS U446 ( .A0(n361), .A1(n360), .B0(n359), .Y(n365) );
NAND2X1TS U447 ( .A(n363), .B(n362), .Y(n364) );
OAI21X1TS U448 ( .A0(n379), .A1(n375), .B0(n376), .Y(n374) );
XNOR2X1TS U449 ( .A(n374), .B(n373), .Y(res[11]) );
NAND2X1TS U450 ( .A(n377), .B(n376), .Y(n378) );
INVX2TS U451 ( .A(n380), .Y(n382) );
NAND2X1TS U452 ( .A(n382), .B(n381), .Y(n383) );
NAND2X1TS U453 ( .A(n385), .B(n384), .Y(n386) );
XNOR2X1TS U454 ( .A(n387), .B(n386), .Y(res[3]) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_GeArN16R4P8_syn.sdf");
endmodule
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`include "consts.vh"
module arbiter (
input clk,
input reset,
output [31:0] request_data,
output stall,
input [31:0] fetch_addr,
input fetch_request,
output fetch_data_valid,
input [31:0] dmem_addr,
input [31:0] dmem_write_data,
input [3:0] dmem_write_mask,
input dmem_request,
input dmem_request_type,
output dmem_data_valid,
/* memory interface */
output reg [31:0] mem_addr,
output [3:0] mem_mask, /* write */
output mem_enable,
output reg mem_cmd,
input [31:0] mem_data,
output [31:0] mem_wdata,
input mem_valid
);
wire requests_pending = fetch_request | dmem_request;
reg fetch_satisfied;
reg memory_satisfied;
localparam S_IDLE = 3'd0;
localparam S_SVC_FETCH = 3'd1;
localparam S_SVC_MEM_R = 3'd2;
localparam S_SVC_MEM_W = 3'd3;
reg [2:0] state;
reg [2:0] next_state;
always @ (posedge clk) begin
if (reset) begin
state <= S_IDLE;
end else begin
state <= next_state;
end
end
always @ (posedge clk) begin
if (reset) begin
fetch_satisfied <= 1;
end else if (state == S_IDLE && next_state != S_IDLE) begin
fetch_satisfied <= (fetch_request ? 0 : 1);
end else if (state == S_SVC_FETCH && mem_valid) begin
fetch_satisfied <= 1;
end
if (reset) begin
memory_satisfied <= 1;
end else if (state == S_IDLE && next_state != S_IDLE) begin
memory_satisfied <= (dmem_request ? 0 : 1);
end else if (state == S_SVC_MEM_R && mem_valid) begin
memory_satisfied <= 1;
end
end
always @ (*) begin
case (state)
S_IDLE:
if (requests_pending)
if (fetch_request)
next_state = S_SVC_FETCH;
else if (dmem_request)
if (dmem_request_type == `MEM_REQ_WRITE)
next_state = S_SVC_MEM_W;
else
next_state = S_SVC_MEM_R;
else
next_state = S_IDLE;
else
next_state = S_IDLE;
S_SVC_FETCH:
if (!fetch_satisfied)
next_state = S_SVC_FETCH;
else if (dmem_request)
if (dmem_request_type == `MEM_REQ_WRITE)
next_state = S_SVC_MEM_W;
else
next_state = S_SVC_MEM_R;
else
next_state = S_IDLE;
S_SVC_MEM_R:
if (!memory_satisfied)
next_state = S_SVC_MEM_R;
else
next_state = S_IDLE;
S_SVC_MEM_W:
/* allow writes to go... write through */
next_state = S_IDLE;
default:
next_state = S_IDLE;
endcase
end
always @ (*) begin
case (state)
S_SVC_FETCH:
mem_addr = fetch_addr;
S_SVC_MEM_R, S_SVC_MEM_W:
mem_addr = dmem_addr;
default:
mem_addr = 0;
endcase
end
assign stall = (next_state != S_IDLE);
assign fetch_data_valid = (state == S_SVC_FETCH & mem_valid);
assign dmem_data_valid = (state == S_SVC_MEM_R & mem_valid);
assign request_data = mem_data;
assign mem_wdata = dmem_write_data;
assign mem_enable = (state == S_SVC_FETCH && !fetch_satisfied) ||
(state == S_SVC_MEM_R && !memory_satisfied) ||
(state == S_SVC_MEM_W);
assign mem_mask = dmem_write_mask;
always @ (*) begin
case (state)
S_SVC_FETCH: mem_cmd = `MEM_CMD_READ;
S_SVC_MEM_R: mem_cmd = `MEM_CMD_READ;
S_SVC_MEM_W: mem_cmd = `MEM_CMD_WRITE;
default: mem_cmd = 0;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_1_V
`define SKY130_FD_SC_HS__A222O_1_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a222o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222o_1 (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_1_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module AESL_axi_slave_gcd_bus (
clk,
reset,
TRAN_s_axi_gcd_bus_AWADDR,
TRAN_s_axi_gcd_bus_AWVALID,
TRAN_s_axi_gcd_bus_AWREADY,
TRAN_s_axi_gcd_bus_WVALID,
TRAN_s_axi_gcd_bus_WREADY,
TRAN_s_axi_gcd_bus_WDATA,
TRAN_s_axi_gcd_bus_WSTRB,
TRAN_s_axi_gcd_bus_ARADDR,
TRAN_s_axi_gcd_bus_ARVALID,
TRAN_s_axi_gcd_bus_ARREADY,
TRAN_s_axi_gcd_bus_RVALID,
TRAN_s_axi_gcd_bus_RREADY,
TRAN_s_axi_gcd_bus_RDATA,
TRAN_s_axi_gcd_bus_RRESP,
TRAN_s_axi_gcd_bus_BVALID,
TRAN_s_axi_gcd_bus_BREADY,
TRAN_s_axi_gcd_bus_BRESP,
TRAN_gcd_bus_write_data_finish,
TRAN_gcd_bus_read_data_finish,
TRAN_gcd_bus_start_in,
TRAN_gcd_bus_idle_out,
TRAN_gcd_bus_ready_out,
TRAN_gcd_bus_ready_in,
TRAN_gcd_bus_done_out,
TRAN_gcd_bus_write_start_in ,
TRAN_gcd_bus_write_start_finish,
TRAN_gcd_bus_interrupt,
TRAN_gcd_bus_transaction_done_in
);
//------------------------Parameter----------------------
`define TV_IN_a "../tv/cdatafile/c.gcd.autotvin_a.dat"
`define TV_IN_b "../tv/cdatafile/c.gcd.autotvin_b.dat"
`define TV_OUT_pResult "../tv/rtldatafile/rtl.gcd.autotvout_pResult.dat"
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 32;
parameter a_DEPTH = 1;
reg [31 : 0] a_OPERATE_DEPTH = 0;
parameter a_c_bitwidth = 16;
parameter b_DEPTH = 1;
reg [31 : 0] b_OPERATE_DEPTH = 0;
parameter b_c_bitwidth = 16;
parameter pResult_DEPTH = 1;
reg [31 : 0] pResult_OPERATE_DEPTH = 0;
parameter pResult_c_bitwidth = 16;
parameter START_ADDR = 0;
parameter gcd_continue_addr = 0;
parameter gcd_auto_start_addr = 0;
parameter a_data_in_addr = 16;
parameter b_data_in_addr = 24;
parameter pResult_data_out_addr = 32;
parameter pResult_valid_out_addr = 36;
parameter STATUS_ADDR = 0;
output [ADDR_WIDTH - 1 : 0] TRAN_s_axi_gcd_bus_AWADDR;
output TRAN_s_axi_gcd_bus_AWVALID;
input TRAN_s_axi_gcd_bus_AWREADY;
output TRAN_s_axi_gcd_bus_WVALID;
input TRAN_s_axi_gcd_bus_WREADY;
output [DATA_WIDTH - 1 : 0] TRAN_s_axi_gcd_bus_WDATA;
output [DATA_WIDTH/8 - 1 : 0] TRAN_s_axi_gcd_bus_WSTRB;
output [ADDR_WIDTH - 1 : 0] TRAN_s_axi_gcd_bus_ARADDR;
output TRAN_s_axi_gcd_bus_ARVALID;
input TRAN_s_axi_gcd_bus_ARREADY;
input TRAN_s_axi_gcd_bus_RVALID;
output TRAN_s_axi_gcd_bus_RREADY;
input [DATA_WIDTH - 1 : 0] TRAN_s_axi_gcd_bus_RDATA;
input [2 - 1 : 0] TRAN_s_axi_gcd_bus_RRESP;
input TRAN_s_axi_gcd_bus_BVALID;
output TRAN_s_axi_gcd_bus_BREADY;
input [2 - 1 : 0] TRAN_s_axi_gcd_bus_BRESP;
output TRAN_gcd_bus_write_data_finish;
output TRAN_gcd_bus_read_data_finish;
input clk;
input reset;
input TRAN_gcd_bus_start_in;
output TRAN_gcd_bus_done_out;
output TRAN_gcd_bus_ready_out;
input TRAN_gcd_bus_ready_in;
output TRAN_gcd_bus_idle_out;
input TRAN_gcd_bus_write_start_in ;
output TRAN_gcd_bus_write_start_finish;
input TRAN_gcd_bus_interrupt;
input TRAN_gcd_bus_transaction_done_in;
reg [ADDR_WIDTH - 1 : 0] AWADDR_reg = 0;
reg AWVALID_reg = 0;
reg WVALID_reg = 0;
reg [DATA_WIDTH - 1 : 0] WDATA_reg = 0;
reg [DATA_WIDTH/8 - 1 : 0] WSTRB_reg = 0;
reg [ADDR_WIDTH - 1 : 0] ARADDR_reg = 0;
reg ARVALID_reg = 0;
reg RREADY_reg = 0;
reg [DATA_WIDTH - 1 : 0] RDATA_reg = 0;
reg BREADY_reg = 0;
reg [DATA_WIDTH - 1 : 0] mem_a [a_DEPTH - 1 : 0];
reg a_write_data_finish;
reg [DATA_WIDTH - 1 : 0] mem_b [b_DEPTH - 1 : 0];
reg b_write_data_finish;
reg [DATA_WIDTH - 1 : 0] mem_pResult [pResult_DEPTH - 1 : 0];
reg pResult_read_data_finish;
reg AESL_ready_out_index_reg = 0;
reg AESL_write_start_finish = 0;
reg AESL_ready_reg;
reg ready_initial;
reg AESL_done_index_reg = 0;
reg AESL_idle_index_reg = 0;
reg AESL_auto_restart_index_reg;
reg process_0_finish = 0;
reg process_1_finish = 0;
reg process_2_finish = 0;
reg process_3_finish = 0;
reg process_4_finish = 0;
//write a reg
reg [31 : 0] write_a_count = 0;
reg write_a_run_flag = 0;
reg write_one_a_data_done = 0;
//write b reg
reg [31 : 0] write_b_count = 0;
reg write_b_run_flag = 0;
reg write_one_b_data_done = 0;
//read pResult reg
reg [31 : 0] read_pResult_count = 0;
reg read_pResult_run_flag = 0;
reg read_one_pResult_data_done = 0;
reg [31 : 0] write_start_count = 0;
reg write_start_run_flag = 0;
//===================process control=================
reg [31 : 0] ongoing_process_number = 0;
//process number depends on how much processes needed.
reg process_busy = 0;
//=================== signal connection ==============
assign TRAN_s_axi_gcd_bus_AWADDR = AWADDR_reg;
assign TRAN_s_axi_gcd_bus_AWVALID = AWVALID_reg;
assign TRAN_s_axi_gcd_bus_WVALID = WVALID_reg;
assign TRAN_s_axi_gcd_bus_WDATA = WDATA_reg;
assign TRAN_s_axi_gcd_bus_WSTRB = WSTRB_reg;
assign TRAN_s_axi_gcd_bus_ARADDR = ARADDR_reg;
assign TRAN_s_axi_gcd_bus_ARVALID = ARVALID_reg;
assign TRAN_s_axi_gcd_bus_RREADY = RREADY_reg;
assign TRAN_s_axi_gcd_bus_BREADY = BREADY_reg;
assign TRAN_gcd_bus_write_start_finish = AESL_write_start_finish;
assign TRAN_gcd_bus_done_out = AESL_done_index_reg;
assign TRAN_gcd_bus_ready_out = AESL_ready_out_index_reg;
assign TRAN_gcd_bus_idle_out = AESL_idle_index_reg;
assign TRAN_gcd_bus_read_data_finish = 1 & pResult_read_data_finish;
assign TRAN_gcd_bus_write_data_finish = 1 & a_write_data_finish & b_write_data_finish;
always @(TRAN_gcd_bus_ready_in or ready_initial)
begin
AESL_ready_reg <= TRAN_gcd_bus_ready_in | ready_initial;
end
always @(reset or process_0_finish or process_1_finish or process_2_finish or process_3_finish or process_4_finish ) begin
if (reset == 0) begin
ongoing_process_number <= 0;
end
else if (ongoing_process_number == 0 && process_0_finish == 1) begin
ongoing_process_number <= ongoing_process_number + 1;
end
else if (ongoing_process_number == 1 && process_1_finish == 1) begin
ongoing_process_number <= ongoing_process_number + 1;
end
else if (ongoing_process_number == 2 && process_2_finish == 1) begin
ongoing_process_number <= ongoing_process_number + 1;
end
else if (ongoing_process_number == 3 && process_3_finish == 1) begin
ongoing_process_number <= ongoing_process_number + 1;
end
else if (ongoing_process_number == 4 && process_4_finish == 1) begin
ongoing_process_number <= 0;
end
end
task count_c_data_four_byte_num_by_bitwidth;
input integer bitwidth;
output integer num;
integer factor;
integer i;
begin
factor = 32;
for (i = 1; i <= 32; i = i + 1) begin
if (bitwidth <= factor && bitwidth > factor - 32) begin
num = i;
end
factor = factor + 32;
end
end
endtask
task count_seperate_factor_by_bitwidth;
input integer bitwidth;
output integer factor;
begin
if (bitwidth <= 8 ) begin
factor=4;
end
if (bitwidth <= 16 & bitwidth > 8 ) begin
factor=2;
end
if (bitwidth <= 32 & bitwidth > 16 ) begin
factor=1;
end
if (bitwidth <= 1024 & bitwidth > 32 ) begin
factor=1;
end
end
endtask
task count_operate_depth_by_bitwidth_and_depth;
input integer bitwidth;
input integer depth;
output integer operate_depth;
integer factor;
integer remain;
begin
count_seperate_factor_by_bitwidth (bitwidth , factor);
operate_depth = depth / factor;
remain = depth % factor;
if (remain > 0) begin
operate_depth = operate_depth + 1;
end
end
endtask
task write; /*{{{*/
input reg [ADDR_WIDTH - 1:0] waddr; // write address
input reg [DATA_WIDTH - 1:0] wdata; // write data
output reg wresp;
reg aw_flag;
reg w_flag;
reg [DATA_WIDTH/8 - 1:0] wstrb_reg;
integer i;
begin
wresp = 0;
aw_flag = 0;
w_flag = 0;
//=======================one single write operate======================
AWADDR_reg <= waddr;
AWVALID_reg <= 1;
WDATA_reg <= wdata;
WVALID_reg <= 1;
for (i = 0; i < DATA_WIDTH/8; i = i + 1) begin
wstrb_reg [i] = 1;
end
WSTRB_reg <= wstrb_reg;
while (!(aw_flag && w_flag)) begin
@(posedge clk);
if (aw_flag != 1)
aw_flag = TRAN_s_axi_gcd_bus_AWREADY & AWVALID_reg;
if (w_flag != 1)
w_flag = TRAN_s_axi_gcd_bus_WREADY & WVALID_reg;
AWVALID_reg <= !aw_flag;
WVALID_reg <= !w_flag;
end
BREADY_reg <= 1;
while (TRAN_s_axi_gcd_bus_BVALID != 1) begin
//wait for response
@(posedge clk);
end
@(posedge clk);
BREADY_reg <= 0;
if (TRAN_s_axi_gcd_bus_BRESP === 2'b00) begin
wresp = 1;
//input success. in fact BRESP is always 2'b00
end
//=======================one single write operate======================
end
endtask/*}}}*/
task read (/*{{{*/
input [ADDR_WIDTH - 1:0] raddr , // write address
output [DATA_WIDTH - 1:0] RDATA_result ,
output rresp
);
begin
rresp = 0;
//=======================one single read operate======================
ARADDR_reg <= raddr;
ARVALID_reg <= 1;
while (TRAN_s_axi_gcd_bus_ARREADY !== 1) begin
@(posedge clk);
end
@(posedge clk);
ARVALID_reg <= 0;
RREADY_reg <= 1;
while (TRAN_s_axi_gcd_bus_RVALID !== 1) begin
//wait for response
@(posedge clk);
end
@(posedge clk);
RDATA_result <= TRAN_s_axi_gcd_bus_RDATA;
RREADY_reg <= 0;
if (TRAN_s_axi_gcd_bus_RRESP === 2'b00 ) begin
rresp <= 1;
//output success. in fact RRESP is always 2'b00
end
@(posedge clk);
//=======================one single read operate end======================
end
endtask/*}}}*/
initial begin : ready_initial_process
ready_initial = 0;
wait(reset === 1);
@(posedge clk);
ready_initial = 1;
@(posedge clk);
ready_initial = 0;
end
initial begin : update_status
integer process_num ;
integer read_status_resp;
wait(reset === 1);
@(posedge clk);
process_num = 0;
while (1) begin
process_0_finish = 0;
AESL_done_index_reg <= 0;
AESL_ready_out_index_reg <= 0;
if (ongoing_process_number === process_num && process_busy === 0) begin
process_busy = 1;
read (STATUS_ADDR, RDATA_reg, read_status_resp);
AESL_done_index_reg <= RDATA_reg[1 : 1];
AESL_ready_out_index_reg <= RDATA_reg[1 : 1];
AESL_idle_index_reg <= RDATA_reg[2 : 2];
process_0_finish = 1;
process_busy = 0;
end
@(posedge clk);
end
end
always @(reset or posedge clk) begin
if (reset == 0) begin
a_write_data_finish <= 0;
write_a_run_flag <= 0;
write_a_count = 0;
count_operate_depth_by_bitwidth_and_depth (a_c_bitwidth, a_DEPTH, a_OPERATE_DEPTH);
end
else begin
if (TRAN_gcd_bus_start_in === 1) begin
a_write_data_finish <= 0;
end
if (AESL_ready_reg === 1) begin
write_a_run_flag <= 1;
write_a_count = 0;
end
if (write_one_a_data_done === 1) begin
write_a_count = write_a_count + 1;
if (write_a_count == a_OPERATE_DEPTH) begin
write_a_run_flag <= 0;
a_write_data_finish <= 1;
end
end
end
end
initial begin : write_a
integer write_a_resp;
integer process_num ;
integer get_ack;
integer four_byte_num;
integer c_bitwidth;
integer i;
integer j;
reg [31 : 0] a_data_tmp_reg;
wait(reset === 1);
@(posedge clk);
c_bitwidth = a_c_bitwidth;
process_num = 1;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (1) begin
process_1_finish <= 0;
if (ongoing_process_number === process_num && process_busy === 0 ) begin
get_ack = 1;
if (write_a_run_flag === 1 && get_ack === 1) begin
process_busy = 1;
//write a data
for (i = 0 ; i < four_byte_num ; i = i+1) begin
if (a_c_bitwidth < 32) begin
a_data_tmp_reg = mem_a[write_a_count];
end
else begin
for (j=0 ; j<32 ; j = j + 1) begin
if (i*32 + j < a_c_bitwidth) begin
a_data_tmp_reg[j] = mem_a[write_a_count][i*32 + j];
end
else begin
a_data_tmp_reg[j] = 0;
end
end
end
write (a_data_in_addr + write_a_count * four_byte_num * 4 + i * 4, a_data_tmp_reg, write_a_resp);
end
process_busy = 0;
write_one_a_data_done <= 1;
@(posedge clk);
write_one_a_data_done <= 0;
end
process_1_finish <= 1;
end
@(posedge clk);
end
end
always @(reset or posedge clk) begin
if (reset == 0) begin
b_write_data_finish <= 0;
write_b_run_flag <= 0;
write_b_count = 0;
count_operate_depth_by_bitwidth_and_depth (b_c_bitwidth, b_DEPTH, b_OPERATE_DEPTH);
end
else begin
if (TRAN_gcd_bus_start_in === 1) begin
b_write_data_finish <= 0;
end
if (AESL_ready_reg === 1) begin
write_b_run_flag <= 1;
write_b_count = 0;
end
if (write_one_b_data_done === 1) begin
write_b_count = write_b_count + 1;
if (write_b_count == b_OPERATE_DEPTH) begin
write_b_run_flag <= 0;
b_write_data_finish <= 1;
end
end
end
end
initial begin : write_b
integer write_b_resp;
integer process_num ;
integer get_ack;
integer four_byte_num;
integer c_bitwidth;
integer i;
integer j;
reg [31 : 0] b_data_tmp_reg;
wait(reset === 1);
@(posedge clk);
c_bitwidth = b_c_bitwidth;
process_num = 2;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (1) begin
process_2_finish <= 0;
if (ongoing_process_number === process_num && process_busy === 0 ) begin
get_ack = 1;
if (write_b_run_flag === 1 && get_ack === 1) begin
process_busy = 1;
//write b data
for (i = 0 ; i < four_byte_num ; i = i+1) begin
if (b_c_bitwidth < 32) begin
b_data_tmp_reg = mem_b[write_b_count];
end
else begin
for (j=0 ; j<32 ; j = j + 1) begin
if (i*32 + j < b_c_bitwidth) begin
b_data_tmp_reg[j] = mem_b[write_b_count][i*32 + j];
end
else begin
b_data_tmp_reg[j] = 0;
end
end
end
write (b_data_in_addr + write_b_count * four_byte_num * 4 + i * 4, b_data_tmp_reg, write_b_resp);
end
process_busy = 0;
write_one_b_data_done <= 1;
@(posedge clk);
write_one_b_data_done <= 0;
end
process_2_finish <= 1;
end
@(posedge clk);
end
end
always @(reset or posedge clk) begin
if (reset == 0) begin
write_start_run_flag <= 0;
write_start_count <= 0;
end
else begin
if (write_start_count >= 5) begin
write_start_run_flag <= 0;
end
else if (TRAN_gcd_bus_write_start_in === 1) begin
write_start_run_flag <= 1;
end
if (AESL_write_start_finish === 1) begin
write_start_count <= write_start_count + 1;
write_start_run_flag <= 0;
end
end
end
initial begin : write_start
reg [DATA_WIDTH - 1 : 0] write_start_tmp;
integer process_num;
integer write_start_resp;
wait(reset === 1);
@(posedge clk);
process_num = 3;
while (1) begin
process_3_finish = 0;
if (ongoing_process_number === process_num && process_busy === 0 ) begin
if (write_start_run_flag === 1) begin
process_busy = 1;
write_start_tmp=0;
write_start_tmp[0 : 0] = 1;
write (START_ADDR, write_start_tmp, write_start_resp);
process_busy = 0;
AESL_write_start_finish <= 1;
@(posedge clk);
AESL_write_start_finish <= 0;
end
process_3_finish <= 1;
end
@(posedge clk);
end
end
always @(reset or posedge clk) begin
if (reset == 0) begin
pResult_read_data_finish <= 0;
read_pResult_run_flag <= 0;
read_pResult_count = 0;
count_operate_depth_by_bitwidth_and_depth (pResult_c_bitwidth, pResult_DEPTH, pResult_OPERATE_DEPTH);
end
else begin
if (TRAN_gcd_bus_start_in === 1) begin
read_pResult_run_flag = 1;
end
if (TRAN_gcd_bus_transaction_done_in === 1) begin
pResult_read_data_finish <= 0;
read_pResult_count = 0;
end
if (read_one_pResult_data_done === 1) begin
read_pResult_count = read_pResult_count + 1;
if (read_pResult_count == pResult_OPERATE_DEPTH) begin
read_pResult_run_flag <= 0;
pResult_read_data_finish <= 1;
end
end
end
end
initial begin : read_pResult
integer read_pResult_resp;
integer process_num;
integer get_vld;
integer four_byte_num;
integer c_bitwidth;
integer i;
integer j;
wait(reset === 1);
@(posedge clk);
c_bitwidth = pResult_c_bitwidth;
process_num = 4;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (1) begin
process_4_finish <= 0;
if (ongoing_process_number === process_num && process_busy === 0 ) begin
if (read_pResult_run_flag === 1) begin
process_busy = 1;
get_vld = 0;
//read pResult vld
read (pResult_valid_out_addr, RDATA_reg, read_pResult_resp);
if (RDATA_reg[0 : 0] == 1) begin
get_vld = 1;
end
if (get_vld == 1) begin
//read pResult data
for (i = 0 ; i < four_byte_num ; i = i+1) begin
read (pResult_data_out_addr + read_pResult_count * four_byte_num * 4 + i * 4, RDATA_reg, read_pResult_resp);
if (pResult_c_bitwidth < 32) begin
mem_pResult[read_pResult_count] <= RDATA_reg;
end
else begin
for (j=0 ; j < 32 ; j = j + 1) begin
if (i*32 + j < pResult_c_bitwidth) begin
mem_pResult[read_pResult_count][i*32 + j] <= RDATA_reg[j];
end
end
end
end
read_one_pResult_data_done <= 1;
@(posedge clk);
read_one_pResult_data_done <= 0;
end
process_busy = 0;
end
process_4_finish <= 1;
end
@(posedge clk);
end
end
//------------------------Task and function--------------
task read_token;
input integer fp;
output reg [127 : 0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
//------------------------Read file------------------------
// Read data from file
initial begin : read_a_file_process
integer fp;
integer ret;
integer factor;
reg [127 : 0] token;
reg [127 : 0] token_tmp;
//reg [a_c_bitwidth - 1 : 0] token_tmp;
reg [DATA_WIDTH - 1 : 0] mem_tmp;
reg [ 8*5 : 1] str;
integer transaction_idx;
integer i;
transaction_idx = 0;
mem_tmp [DATA_WIDTH - 1 : 0] = 0;
count_seperate_factor_by_bitwidth (a_c_bitwidth , factor);
fp = $fopen(`TV_IN_a ,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `TV_IN_a);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
@(posedge clk);
# 0.2;
while(AESL_ready_reg !== 1) begin
@(posedge clk);
# 0.2;
end
for(i = 0; i < a_DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", token_tmp);
if (factor == 4) begin
if (i%factor == 0) begin
mem_tmp [7 : 0] = token_tmp;
end
if (i%factor == 1) begin
mem_tmp [15 : 8] = token_tmp;
end
if (i%factor == 2) begin
mem_tmp [23 : 16] = token_tmp;
end
if (i%factor == 3) begin
mem_tmp [31 : 24] = token_tmp;
mem_a [i/factor] = mem_tmp;
mem_tmp [DATA_WIDTH - 1 : 0] = 0;
end
end
if (factor == 2) begin
if (i%factor == 0) begin
mem_tmp [15 : 0] = token_tmp;
end
if (i%factor == 1) begin
mem_tmp [31 : 16] = token_tmp;
mem_a [i/factor] = mem_tmp;
mem_tmp [DATA_WIDTH - 1: 0] = 0;
end
end
if (factor == 1) begin
mem_a [i] = token_tmp;
end
end
if (factor == 4) begin
if (i%factor != 0) begin
mem_a [i/factor] = mem_tmp;
end
end
if (factor == 2) begin
if (i%factor != 0) begin
mem_a [i/factor] = mem_tmp;
end
end
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
//------------------------Read file------------------------
// Read data from file
initial begin : read_b_file_process
integer fp;
integer ret;
integer factor;
reg [127 : 0] token;
reg [127 : 0] token_tmp;
//reg [b_c_bitwidth - 1 : 0] token_tmp;
reg [DATA_WIDTH - 1 : 0] mem_tmp;
reg [ 8*5 : 1] str;
integer transaction_idx;
integer i;
transaction_idx = 0;
mem_tmp [DATA_WIDTH - 1 : 0] = 0;
count_seperate_factor_by_bitwidth (b_c_bitwidth , factor);
fp = $fopen(`TV_IN_b ,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `TV_IN_b);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
@(posedge clk);
# 0.2;
while(AESL_ready_reg !== 1) begin
@(posedge clk);
# 0.2;
end
for(i = 0; i < b_DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", token_tmp);
if (factor == 4) begin
if (i%factor == 0) begin
mem_tmp [7 : 0] = token_tmp;
end
if (i%factor == 1) begin
mem_tmp [15 : 8] = token_tmp;
end
if (i%factor == 2) begin
mem_tmp [23 : 16] = token_tmp;
end
if (i%factor == 3) begin
mem_tmp [31 : 24] = token_tmp;
mem_b [i/factor] = mem_tmp;
mem_tmp [DATA_WIDTH - 1 : 0] = 0;
end
end
if (factor == 2) begin
if (i%factor == 0) begin
mem_tmp [15 : 0] = token_tmp;
end
if (i%factor == 1) begin
mem_tmp [31 : 16] = token_tmp;
mem_b [i/factor] = mem_tmp;
mem_tmp [DATA_WIDTH - 1: 0] = 0;
end
end
if (factor == 1) begin
mem_b [i] = token_tmp;
end
end
if (factor == 4) begin
if (i%factor != 0) begin
mem_b [i/factor] = mem_tmp;
end
end
if (factor == 2) begin
if (i%factor != 0) begin
mem_b [i/factor] = mem_tmp;
end
end
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
//------------------------Write file-----------------------
// Write data to file
initial begin : write_pResult_file_proc
integer fp;
integer factor;
integer transaction_idx;
reg [pResult_c_bitwidth - 1 : 0] mem_tmp;
reg [ 100*8 : 1] str;
integer i;
transaction_idx = 0;
count_seperate_factor_by_bitwidth (pResult_c_bitwidth , factor);
while(1) begin
@(posedge clk);
while (pResult_read_data_finish !== 1) begin
@(posedge clk);
end
# 0.1;
fp = $fopen(`TV_OUT_pResult, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", `TV_OUT_pResult);
$finish;
end
$fdisplay(fp, "[[transaction]] %d", transaction_idx);
for (i = 0; i < (pResult_DEPTH - pResult_DEPTH % factor); i = i + 1) begin
if (factor == 4) begin
if (i%factor == 0) begin
mem_tmp = mem_pResult[i/factor][7:0];
end
if (i%factor == 1) begin
mem_tmp = mem_pResult[i/factor][15:8];
end
if (i%factor == 2) begin
mem_tmp = mem_pResult[i/factor][23:16];
end
if (i%factor == 3) begin
mem_tmp = mem_pResult[i/factor][31:24];
end
$fdisplay(fp,"0x%x",mem_tmp);
end
if (factor == 2) begin
if (i%factor == 0) begin
mem_tmp = mem_pResult[i/factor][15:0];
end
if (i%factor == 1) begin
mem_tmp = mem_pResult[i/factor][31:16];
end
$fdisplay(fp,"0x%x",mem_tmp);
end
if (factor == 1) begin
$fdisplay(fp,"0x%x",mem_pResult[i]);
end
end
if (factor == 4) begin
if ((pResult_DEPTH - 1) % factor == 2) begin
$fdisplay(fp,"0x%x",mem_pResult[pResult_DEPTH / factor][7:0]);
$fdisplay(fp,"0x%x",mem_pResult[pResult_DEPTH / factor][15:8]);
$fdisplay(fp,"0x%x",mem_pResult[pResult_DEPTH / factor][23:16]);
end
if ((pResult_DEPTH - 1) % factor == 1) begin
$fdisplay(fp,"0x%x",mem_pResult[pResult_DEPTH / factor][7:0]);
$fdisplay(fp,"0x%x",mem_pResult[pResult_DEPTH / factor][15:8]);
end
if ((pResult_DEPTH - 1) % factor == 0) begin
$fdisplay(fp,"0x%x",mem_pResult[pResult_DEPTH / factor][7:0]);
end
end
if (factor == 2) begin
if ((pResult_DEPTH - 1) % factor == 0) begin
$fdisplay(fp,"0x%x",mem_pResult[pResult_DEPTH / factor][15:0]);
end
end
$fdisplay(fp, "[[/transaction]]");
transaction_idx = transaction_idx + 1;
$fclose(fp);
while (TRAN_gcd_bus_start_in !== 1) begin
@(posedge clk);
end
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_dram_ddr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_dram_ddr (/*AUTOARG*/
// Outputs
so, rclk, dbginit_l, cluster_grst_l,
// Inputs
si, se, grst_l, gdbginit_l, gclk, cluster_cken, arst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cluster_grst_l; // From cluster_header of cluster_header.v
output dbginit_l; // From cluster_header of cluster_header.v
output rclk; // From cluster_header of cluster_header.v
output so; // From cluster_header of cluster_header.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To cluster_header of cluster_header.v
input arst_l; // To cluster_header of cluster_header.v
input cluster_cken; // To cluster_header of cluster_header.v
input gclk; // To cluster_header of cluster_header.v
input gdbginit_l; // To cluster_header of cluster_header.v
input grst_l; // To cluster_header of cluster_header.v
input se; // To cluster_header of cluster_header.v
input si; // To cluster_header of cluster_header.v
// End of automatics
/* cluster_header AUTO_TEMPLATE (
); */
cluster_header cluster_header
(/*AUTOINST*/
// Outputs
.dbginit_l (dbginit_l),
.cluster_grst_l (cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken (cluster_cken),
.arst_l (arst_l),
.grst_l (grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l),
.si (si),
.se (se));
endmodule // bw_clk_cl_ddr_ddr
// Local Variables:
// verilog-library-directories:("../../common/rtl")
// verilog-auto-sense-defines-constant:t
// End:
|
module mapper_router(clk, rst, Data_in_N, Data_in_S, Data_in_W, Data_in_E, Data_in_ready_N, Data_in_ready_S, Data_in_ready_W,
Data_in_ready_E, Data_out_N, Data_out_S, Data_out_W, Data_out_E,
Data_out_ready_N, Data_out_ready_S, Data_out_ready_W, Data_out_ready_E,
Data_in_valid_N, Data_in_valid_E, Data_in_valid_S, Data_in_valid_W,
Data_out_valid_N, Data_out_valid_S, Data_out_valid_W, Data_out_valid_E,
noc_locationx, noc_locationy);
parameter WIDTH=36;
parameter DEPTH=8;
parameter ADDR=4;
parameter lhsCount=5;
parameter rhsCount=5;
input clk;
input rst;
input [1:0] noc_locationx;
input [1:0] noc_locationy;
input [WIDTH-1:0] Data_in_N;
input [WIDTH-1:0] Data_in_S;
input [WIDTH-1:0] Data_in_W;
input [WIDTH-1:0] Data_in_E;
//input [WIDTH-1:0] Data_in_L;
input Data_in_ready_N;
input Data_in_ready_S;
input Data_in_ready_W;
input Data_in_ready_E;
//input Data_in_ready_L;
output [WIDTH-1:0] Data_out_N;
output [WIDTH-1:0] Data_out_S;
output [WIDTH-1:0] Data_out_W;
output [WIDTH-1:0] Data_out_E;
//output [WIDTH-1:0] Data_out_L;
output Data_out_ready_N;
output Data_out_ready_E;
output Data_out_ready_S;
output Data_out_ready_W;
//output Data_out_ready_L;
input Data_in_valid_N;
input Data_in_valid_E;
input Data_in_valid_S;
input Data_in_valid_W;
output Data_out_valid_N;
output Data_out_valid_E;
output Data_out_valid_S;
output Data_out_valid_W;
wire [4:0] Data_out_valid;
wire Valid_router2mapper;
assign Data_out_valid_N = Data_out_valid[0];
assign Data_out_valid_E = Data_out_valid[1] ;
assign Data_out_valid_S = Data_out_valid[2] ;
assign Data_out_valid_W = Data_out_valid[3] ;
assign Valid_router2mapper = Data_out_valid[4];
// Data_out_valid[4] should connect to the enbalein of PE
wire [31:0] Data_router2mapper;
wire [WIDTH-1:0] Data_router2mapper_36;
wire [31:0] Data_mapper2router;
wire [WIDTH-1:0] Data_mapper2router_36;
wire Ready_router2mapper;
wire Ready_mapper2router;
wire Valid_mapper2router;
wire [5*WIDTH-1:0] Data_out;
assign Data_out_N = Data_out[WIDTH-1:0];
assign Data_out_E = Data_out[2*WIDTH-1:WIDTH];
assign Data_out_S = Data_out[3*WIDTH-1:2*WIDTH];
assign Data_out_W = Data_out[4*WIDTH-1:3*WIDTH];
assign Data_router2mapper_36 = Data_out[5*WIDTH-1:4*WIDTH];
assign Data_router2mapper = Data_router2mapper_36[35:4];
wire [4:0] Data_out_ready;
assign Data_out_ready[0] = Data_out_ready_N;
assign Data_out_ready[1] = Data_out_ready_E;
assign Data_out_ready[2] = Data_out_ready_S;
assign Data_out_ready[3] = Data_out_ready_W;
assign Data_out_ready[4] = Ready_router2mapper;
wire [5*WIDTH-1:0] Data_in;
assign Data_in[WIDTH-1:0] = Data_in_N;
assign Data_in[2*WIDTH-1:WIDTH] = Data_in_E;
assign Data_in[3*WIDTH-1:2*WIDTH] = Data_in_S;
assign Data_in[4*WIDTH-1:3*WIDTH] = Data_in_W;
assign Data_in[5*WIDTH-1:4*WIDTH] = Data_mapper2router_36;
assign Data_mapper2router_36[35:4] = Data_mapper2router;
// Reducer location: 1101
assign Data_mapper2router_36[3:0] = (Valid_mapper2router==1 && (Data_mapper2router!=0))?4'b1101:4'b0000;
wire [4:0] Data_in_valid;
//assign Data_in_valid[4]
assign Data_in_valid[0] = Data_in_valid_N;
assign Data_in_valid[1] = Data_in_valid_E;
assign Data_in_valid[2] = Data_in_valid_S;
assign Data_in_valid[3] = Data_in_valid_W;
// Attention
assign Data_in_valid[4] = Valid_mapper2router;
//Connect to 'bustorouter_ready' of router
wire [4:0] Data_in_ready;
assign Data_in_ready[0] = Data_in_ready_N;
assign Data_in_ready[1] = Data_in_ready_E;
assign Data_in_ready[2] = Data_in_ready_S;
assign Data_in_ready[3] = Data_in_ready_W;
assign Data_in_ready[4] = Ready_mapper2router;
// Attention
//assign Ready_mapper2router = !Valid_mapper2router;
assign Ready_mapper2router = 1'bz;
router router0(
.clk(clk),
.reset_b(rst),
.bustorouter_data(Data_in),
.bustorouter_ready(Data_in_ready),
.bustorouter_valid(Data_in_valid),
.X(noc_locationx),
.Y(noc_locationy),
.routertobus_data(Data_out),
.routertobus_ready(),
.routertobus_valid(Data_out_valid)
);
mapper_noc mapper_noc0(
.clk(clk),
.rst(rst),
.data_in(Data_router2mapper),
//!!!!!!!!!!!!!!!!!!!!!!!!!!!!
.data_in_ready(Data_in_valid_W),
.fifo_in_ready(1'b1),
.data_out(Data_mapper2router),
//.data_out_ready(Valid_mapper2router));
.data_out_ready(data_out_ready));
reg data_out_ready_reg;
wire data_out_ready;
assign Valid_mapper2router = data_out_ready && (Data_mapper2router!=0);
/*always@(posedge clk or negedge rst)
if(!rst)
data_out_ready_reg <= 0;
else
data_out_ready_reg <= data_out_ready; */
endmodule
|
//======================================================================
//
// tb_blake2.v
// -----------
// Testbench for the Blake2 top level wrapper.
//
//
// Copyright (c) 2013, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_blake2();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 2;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_write_read;
reg [7 : 0] tb_address;
reg [31 : 0] tb_data_in;
wire [31 : 0] tb_data_out;
reg [63 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg error_found;
reg [31 : 0] read_data;
reg [511 : 0] extracted_data;
reg display_cycle_ctr;
reg display_read_write;
//----------------------------------------------------------------
// Blake2 device under test.
//----------------------------------------------------------------
blake2 dut(
// Clock and reset.
.clk(tb_clk),
.reset_n(tb_reset_n),
// Control.
.cs(tb_cs),
.we(tb_write_read),
// Data ports.
.address(tb_address),
.write_data(tb_data_in),
.read_data(tb_data_out)
);
//----------------------------------------------------------------
// clk_gen
//
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
//
// Monitor displaying information every cycle.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (display_cycle_ctr)
begin
$display("cycle = %016x:", cycle_ctr);
end
end // dut_monitor
//----------------------------------------------------------------
// reset_dut
//----------------------------------------------------------------
task reset_dut;
begin
tb_reset_n = 0;
#(4 * CLK_HALF_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// dump_dut_state
//
// Dump the internal state of the dut to std out.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("");
$display("DUT internal state");
$display("------------------");
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d test cases did not complete successfully.", error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// init_dut()
//
// Set the input to the DUT to defined values.
//----------------------------------------------------------------
task init_dut;
begin
// Set clock, reset and DUT input signals to
// defined values at simulation start.
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 0;
tb_cs = 0;
tb_write_read = 0;
tb_address = 8'h00;
tb_data_in = 32'h00000000;
end
endtask // init_dut
//----------------------------------------------------------------
// blake2_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : blake2_test
$display(" -- Testbench for blake2 started --");
init_dut();
reset_dut();
$display("State at init after reset:");
dump_dut_state();
display_test_result();
$display("*** blake2 simulation done.");
$finish;
end // blake2_test
endmodule // tb_blake2
//======================================================================
// EOF tb_blake2.v
//======================================================================
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21BOI_PP_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFBUF_BLACKBOX_V
`define SKY130_FD_SC_HDLL__BUFBUF_BLACKBOX_V
/**
* bufbuf: Double buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__bufbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFBUF_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_SYMBOL_V
`define SKY130_FD_SC_LP__A22O_SYMBOL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a22o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__AND2B_FUNCTIONAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2B_FUNCTIONAL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_2_V
`define SKY130_FD_SC_LS__OR3_2_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_2_V
|
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